diff -Nru a/CREDITS b/CREDITS
--- a/CREDITS	Fri Mar 15 17:51:01 2002
+++ b/CREDITS	Fri Mar 15 17:51:01 2002
@@ -1914,13 +1914,13 @@
 S: USA
 
 N: Petko Manolov
-E: petkan@dce.bg
-D: USB ethernet (pegasus) driver
+E: petkan@users.sourceforge.net
+D: USB ethernet pegasus/pegasus-II driver
 D: optimizing i[45]86 string routines
-D: i386 task swithing hacks
-S: 5, Vrah Mancho str.
-S: 1324 Sofia
-S: Bulgaria
+D: i386 task switching hacks
+S: 482 Shadowgraph Dr.
+S: San Jose, CA  95110
+S: USA
 
 N: Martin Mares
 E: mj@ucw.cz
diff -Nru a/Documentation/BK-usage/bk-kernel-howto.txt b/Documentation/BK-usage/bk-kernel-howto.txt
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/BK-usage/bk-kernel-howto.txt	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,275 @@
+
+		   Doing the BK Thing, Penguin-Style
+
+
+
+
+This set of notes is intended mainly for kernel developers, occasional
+or full-time, but sysadmins and power users may find parts of it useful
+as well.  It assumes at least a basic familiarity with CVS, both at a
+user level (use on the cmd line) and at a higher level (client-server model).
+Due to the author's background, an operation may be described in terms
+of CVS, or in terms of how that operation differs from CVS.
+
+This is -not- intended to be BitKeeper documentation.  Always run
+"bk help <command>" or in X "bk helptool <command>" for reference
+documentation.
+
+
+BitKeeper Concepts
+------------------
+
+In the true nature of the Internet itself, BitKeeper is a distributed
+system.  When applied to revision control, this means doing away with
+client-server, and changing to a parent-child model... essentially
+peer-to-peer.  On the developer's end, this also represents a
+fundamental disruption in the standard workflow of changes, commits,
+and merges.  You will need to take a few minutes to think about
+how to best work under BitKeeper, and re-optimize things a bit.
+In some sense it is a bit radical, because it might described as
+tossing changes out into a maelstrom and having them them magically
+land at the right destination... but I'm getting ahead of myself.
+
+Let's start with this progression:
+Each BitKeeper source tree on disk is a repository unto itself.
+Each repository has a parent.
+Each repository contains a set of a changsets ("csets").
+Each cset is one or more changed files, bundled together.
+
+Each tree is a repository, so all changes are checked into the local
+tree.  When a change is checked in, all modified files are grouped
+into a logical unit, the changeset.  Internally, BK links these
+changesets in a tree, representing various converging and diverging
+lines of development.  These changesets are the bread and butter of
+the BK system.
+
+After the concept of changesets, the next thing you need to get used
+to having multiple copies of source trees lying around.  This -really-
+takes some getting used to, for some people.  Separate source trees
+are the means in BitKeeper by which you delineate parallel lines
+of development, both minor and major.  What would be branches in
+CVS become separate source trees, or "clones" in BitKeeper [heh,
+or Star Wars] terminology.
+
+Clones and changesets are the tools from which most of the power of
+BitKeeper is derived.  As mentioned earlier, each clone has a parent,
+the tree used as the source when the new clone was created.  In a
+CVS-like setup, the parent would be a remote server on the Internet,
+and the child is your local clone of that tree.
+
+Once you have established a common baseline between two source trees --
+a common parent -- then you can merge changesets between those two
+trees with ease.  Merging changes into a tree is called a "pull", and
+is analagous to 'cvs update'.  A pull downloads all the changesets in
+the remote tree you do not have, and merges them.  Sending changes in
+one tree to another tree is called a "push".  Push sends all changes
+in the local tree the remote does not yet have, and merges them.
+
+From these concepts come some initial command examples:
+
+1) bk clone -q http://linux.bkbits.net/linux-2.5 linus-2.5
+Download a 2.5 stock kernel tree, naming it "linus-2.5" in the local dir.
+The "-q" disables listing every single file as it is downloaded.
+
+2) bk clone -ql linus-2.5 alpha-2.5
+Create a separate source tree for the Alpha AXP architecture.
+The "-l" uses hard links instead of copying data, since both trees are
+on the local disk.  You can also replace the above with "bk lclone -q ..."
+
+You only clone a tree -once-.  After cloning the tree lives a long time
+on disk, being updating by pushes and pulls.
+
+3) cd alpha-2.5 ; bk pull http://gkernel.bkbits.net/alpha-2.5
+Download changes in "alpha-2.5" repository which are not present
+in the local repository, and merge them into the source tree.
+
+4) bk -r co -q
+Because every tree is a repository, files must be checked out before
+they will be in their standard places in the source tree.
+
+5)	bk vi fs/inode.c				# example change...
+	bk citool					# checkin, using X tool
+	bk push bk://gkernel@bkbits.net/alpha-2.5	# upload change
+Typical example of a BK sequence that would replace the analagous CVS
+situation,
+	vi fs/inode.c
+	cvs commit
+
+As this is just supposed to be a quick BK intro, for more in-depth
+tutorials, live working demos, and docs, see http://www.bitkeeper.com/
+
+
+
+BK and Kernel Development Workflow
+----------------------------------
+Currently the latest 2.5 tree is available via "bk clone $URL"
+and "bk pull $URL" at http://linux.bkbits.net/linux-2.5
+This should change in a few weeks to a kernel.org URL.
+
+
+A big part of using BitKeeper is organizing the various trees you have
+on your local disk, and organizing the flow of changes among those
+trees, and remote trees.  If one were to graph the relationships between
+a desired BK setup, you are likely to see a few-many-few graph, like
+this:
+
+		    linux-2.5
+		        |
+	       merge-to-linus-2.5
+		 /    |      |
+	        /     |      |
+	vm-hacks  bugfixes  filesys   personal-hacks
+	      \	      |	     |		/
+	       \      |      |         /
+		\     |      |        /
+	         testing-and-validation
+
+Since a "bk push" sends all changes not in the target tree, and
+since a "bk pull" receives all changes not in the source tree, you want
+to make sure you are only pushing specific changes to the desired tree,
+not all changes from "peer parent" trees.  For example, pushing a change
+from the testing-and-validation tree would probably be a bad idea,
+because it will push all changes from vm-hacks, bugfixes, filesys, and
+personal-hacks trees into the target tree.
+
+One would typically work on only one "theme" at a time, either
+vm-hacks or bugfixes or filesys, keeping those changes isolated in
+their own tree during development, and only merge the isolated with
+other changes when going upstream (to Linus or other maintainers) or
+downstream (to your "union" trees, like testing-and-validation above).
+
+It should be noted that some of this separation is not just recommended
+practice, it's actually [for now] -enforced- by BitKeeper.  BitKeeper
+requires that changesets maintain a certain order, which is the reason
+that "bk push" sends all local changesets the remote doesn't have.  This
+separation may look like a lot of wasted disk space at first, but it
+helps when two unrelated changes may "pollute" the same area of code, or
+don't follow the same pace of development, or any other of the standard
+reasons why one creates a development branch.
+
+Small development branches (clones) will appear and disappear:
+
+	-------- A --------- B --------- C --------- D -------
+	          \                                 /
+		   -----short-term devel branch-----
+
+While long-term branches will parallel a tree (or trees), with period
+merge points.  In this first example, we pull from a tree (pulls,
+"\") periodically, such a what occurs when tracking changes in a
+vendor tree, never pushing changes back up the line:
+
+	-------- A --------- B --------- C --------- D -------
+	          \                       \           \
+	           ----long-term devel branch-----------------
+
+And then a more common case in Linux kernel development, a long term
+branch with periodic merges back into the tree (pushes, "/"):
+
+	-------- A --------- B --------- C --------- D -------
+	          \                       \         / \
+	           ----long-term devel branch-----------------
+
+
+
+
+
+Submitting Changes to Linus
+---------------------------
+There's a bit of an art, or style, of submitting changes to Linus.
+Since Linus's tree is now (you might say) fully integrated into the
+distributed BitKeeper system, there are several prerequisites to
+properly submitting a BitKeeper change.  All these prereq's are just
+general cleanliness of BK usage, so as people become experts at BK, feel
+free to optimize this process further (assuming Linus agrees, of
+course).
+
+
+
+0) Make sure your tree was originally cloned from the linux-2.5 tree
+created by Linus.  If your tree does not have this as its ancestor, it
+is impossible to reliably exchanges changesets.
+
+
+
+1) Pay attention to your commit text.  The commit message that
+accompanies each changeset you submit will live on forever in history,
+and is used by Linus to accurately summarize the changes in each
+pre-patch.  Remember that there is no context, so
+	"fix for new scheduler changes"
+would be too vague, but
+	"fix mips64 arch for new scheduler switch_to(), TIF_xxx semantics"
+would be much better.
+
+You can and should use the command "bk comment -C<rev>" to update the
+commit text, and improve it after the fact.  This is very useful for
+development: poor, quick descriptions during development, which get
+cleaned up using "bk comment" before issuing the "bk push" to submit the
+changes.
+
+
+
+2) Include an Internet-available URL for Linus to pull from, such as
+
+	Pull from:  http://gkernel.bkbits.net/net-drivers-2.5
+
+
+
+3) Include a summary and "diffstat -p1" of each changeset that will be
+downloaded, when Linus issues a "bk pull".  The author auto-generates
+these summaries using "bk push -nl <parent> 2>&1", to obtain a listing
+of all the pending-to-send changesets, and their commit messages.
+
+It is important to show Linus what he will be downloading when he issues
+a "bk pull", to reduce the time required to sift the changes once they
+are downloaded to Linus's local machine.
+
+IMPORTANT NOTE:  One of the features of BK is that your repository does
+not have to be up to date, in order for Linus to receive your changes.
+It is considered a courtesy to keep your repository fairly recent, to
+lessen any potential merge work Linus may need to do.
+
+
+4) Split up your changes.  Each maintainer<->Linus situation is likely
+to be slightly different here, so take this just as general advice.  The
+author splits up changes according to "themes" when merging with Linus.
+Simultaneous pushes from local development to goes special trees which
+exist solely to house changes "queued" for Linus.  Example of the trees:
+
+	net-drivers-2.5 -- on-going net driver maintenance
+	vm-2.5 -- VM-related changes
+	fs-2.5 -- filesystem-related changes
+
+Linus then has much more freedom for pulling changes.  He could (for
+example) issue a "bk pull" on vm-2.5 and fs-2.5 trees, to merge their
+changes, but hold off net-drivers-2.5 because of a change that needs
+more discussion.
+
+Other maintainers may find that a single linus-pull-from tree is
+adequate for passing BK changesets to him.
+
+
+
+Frequently Answered Questions
+-----------------------------
+1) How do I change the e-mail address shown in the changelog?
+A. When you run "bk citool" or "bk commit", set environment
+   variables BK_USER and BK_HOST to the desired username
+   and host/domain name.
+
+
+2) How do I use tags / get a diff between two kernel versions?
+A. Pass the tags Linus uses to 'bk export'.
+
+ChangeSets are in a forward-progressing order, so it's pretty easy
+to get a snapshot starting and ending at any two points in time.
+Linus puts tags on each release and pre-release, so you could use
+these two examples:
+
+    bk export -tpatch -hdu -rv2.5.4,v2.5.5 | less
+        # creates patch-2.5.5 essentially
+    bk export -tpatch -du -rv2.5.5-pre1,v2.5.5 | less
+        # changes from pre1 to final
+
+A tag is just an alias for a specific changeset... and since changesets
+are ordered, a tag is thus a marker for a specific point in time (or
+specific state of the tree).
diff -Nru a/Documentation/BK-usage/bk-make-sum b/Documentation/BK-usage/bk-make-sum
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/BK-usage/bk-make-sum	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,37 @@
+#!/bin/sh -e
+# DIR=$HOME/BK/axp-2.5
+# cd $DIR
+
+LINUS_REPO=$1
+DIRBASE=`basename $PWD`
+
+{
+cat <<EOT
+Linus, please do a
+
+	bk pull http://gkernel.bkbits.net/$DIRBASE
+
+This will update the following files:
+
+EOT
+
+bk changes -L -d'$unless(:MERGE:){:CSETREV:\n}' $LINUS_REPO |
+while read rev; do
+  bk export -tpatch -r$rev
+done | diffstat -p1 2>/dev/null
+
+cat <<EOT
+
+through these ChangeSets:
+
+EOT
+
+bk changes -L -d'$unless(:MERGE:){ChangeSet|:CSETREV:\n}' $LINUS_REPO |
+bk -R prs -h -d'$unless(:MERGE:){<:P:@:HOST:> (:D: :I:)\n$each(:C:){   (:C:)\n}\n}' -
+
+} > /tmp/linus.txt
+
+cat <<EOT
+Mail text in /tmp/linus.txt; please check and send using your favourite
+mailer.
+EOT
diff -Nru a/Documentation/BK-usage/cset-to-linus b/Documentation/BK-usage/cset-to-linus
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/BK-usage/cset-to-linus	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,49 @@
+#!/usr/bin/perl5.6.1 -w
+
+use strict;
+
+my ($lhs, $rev, $tmp, $rhs, $s);
+my @cset_text = ();
+my @pipe_text = ();
+my $have_cset = 0;
+
+while (<>) {
+	next if /^---/;
+
+	if (($lhs, $tmp, $rhs) = (/^(ChangeSet\@)([^,]+)(, .*)$/)) {
+		&cset_rev if ($have_cset);
+
+		$rev = $tmp;
+		$have_cset = 1;
+
+		push(@cset_text, $_);
+	}
+
+	elsif ($have_cset) {
+		push(@cset_text, $_);
+	}
+}
+&cset_rev if ($have_cset);
+exit(0);
+
+
+sub cset_rev {
+	my $empty_cset = 0;
+
+	open PIPE, "bk export -tpatch -hdu -r $rev | diffstat -p1 2>/dev/null |" or die;
+	while ($s = <PIPE>) {
+		$empty_cset = 1 if ($s =~ /0 files changed/);
+		push(@pipe_text, $s);
+	}
+	close(PIPE);
+
+	if (! $empty_cset) {
+		print @cset_text;
+		print @pipe_text;
+		print "\n\n";
+	}
+
+	@pipe_text = ();
+	@cset_text = ();
+}
+
diff -Nru a/Documentation/BK-usage/csets-to-patches b/Documentation/BK-usage/csets-to-patches
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/BK-usage/csets-to-patches	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,44 @@
+#!/usr/bin/perl5.6.1 -w
+
+use strict;
+
+my ($lhs, $rev, $tmp, $rhs, $s);
+my @cset_text = ();
+my @pipe_text = ();
+my $have_cset = 0;
+
+while (<>) {
+	next if /^---/;
+
+	if (($lhs, $tmp, $rhs) = (/^(ChangeSet\@)([^,]+)(, .*)$/)) {
+		&cset_rev if ($have_cset);
+
+		$rev = $tmp;
+		$have_cset = 1;
+
+		push(@cset_text, $_);
+	}
+
+	elsif ($have_cset) {
+		push(@cset_text, $_);
+	}
+}
+&cset_rev if ($have_cset);
+exit(0);
+
+
+sub cset_rev {
+	my $empty_cset = 0;
+
+	system("bk export -tpatch -du -r $rev > /tmp/rev-$rev.patch");
+
+	if (! $empty_cset) {
+		print @cset_text;
+		print @pipe_text;
+		print "\n\n";
+	}
+
+	@pipe_text = ();
+	@cset_text = ();
+}
+
diff -Nru a/Documentation/DMA-mapping.txt b/Documentation/DMA-mapping.txt
--- a/Documentation/DMA-mapping.txt	Fri Mar 15 17:51:03 2002
+++ b/Documentation/DMA-mapping.txt	Fri Mar 15 17:51:03 2002
@@ -8,7 +8,7 @@
 Most of the 64bit platforms have special hardware that translates bus
 addresses (DMA addresses) into physical addresses.  This is similar to
 how page tables and/or a TLB translates virtual addresses to physical
-addresses on a cpu.  This is needed so that e.g. PCI devices can
+addresses on a CPU.  This is needed so that e.g. PCI devices can
 access with a Single Address Cycle (32bit DMA address) any page in the
 64bit physical address space.  Previously in Linux those 64bit
 platforms had to set artificial limits on the maximum RAM size in the
@@ -37,7 +37,7 @@
 			 What memory is DMA'able?
 
 The first piece of information you must know is what kernel memory can
-be used with the DMA mapping facilitites.  There has been an unwritten
+be used with the DMA mapping facilities.  There has been an unwritten
 set of rules regarding this, and this text is an attempt to finally
 write them down.
 
@@ -106,7 +106,7 @@
 3) Ignore this device and do not initialize it.
 
 It is recommended that your driver print a kernel KERN_WARNING message
-when you end up performing either #2 or #2.  In this manner, if a user
+when you end up performing either #2 or #3.  In this manner, if a user
 of your driver reports that performance is bad or that the device is not
 even detected, you can ask them for the kernel messages to find out
 exactly why.
@@ -146,7 +146,7 @@
 If your 64-bit device is going to be an enormous consumer of DMA
 mappings, this can be problematic since the DMA mappings are a
 finite resource on many platforms.  Please see the "DAC Addressing
-for Address Space Hungry Devices" setion near the end of this
+for Address Space Hungry Devices" section near the end of this
 document for how to handle this case.
 
 Finally, if your device can only drive the low 24-bits of
@@ -205,7 +205,7 @@
 
 - Consistent DMA mappings which are usually mapped at driver
   initialization, unmapped at the end and for which the hardware should
-  guarantee that the device and the cpu can access the data
+  guarantee that the device and the CPU can access the data
   in parallel and will see updates made by each other without any
   explicit software flushing.
 
@@ -222,12 +222,12 @@
 	- Device firmware microcode executed out of
 	  main memory.
 
-  The invariant these examples all require is that any cpu store
+  The invariant these examples all require is that any CPU store
   to memory is immediately visible to the device, and vice
   versa.  Consistent mappings guarantee this.
 
   IMPORTANT: Consistent DMA memory does not preclude the usage of
-             proper memory barriers.  The cpu may reorder stores to
+             proper memory barriers.  The CPU may reorder stores to
 	     consistent memory just as it may normal memory.  Example:
 	     if it is important for the device to see the first word
 	     of a descriptor updated before the second, you must do
@@ -284,7 +284,7 @@
 the pci_pool interface, described below.
 
 The consistent DMA mapping interfaces, for non-NULL dev, will always
-return a DMA address which is SAC (Single Address Cycle) addressible.
+return a DMA address which is SAC (Single Address Cycle) addressable.
 Even if the device indicates (via PCI dma mask) that it may address
 the upper 32-bits and thus perform DAC cycles, consistent allocation
 will still only return 32-bit PCI addresses for DMA.  This is true
@@ -622,7 +622,7 @@
 Note that for streaming type mappings you must either use these
 interfaces, or the dynamic mapping interfaces above.  You may not mix
 usage of both for the same device.  Such an act is illegal and is
-guarenteed to put a banana in your tailpipe.
+guaranteed to put a banana in your tailpipe.
 
 However, consistent mappings may in fact be used in conjunction with
 these interfaces.  Remember that, as defined, consistent mappings are
@@ -637,7 +637,7 @@
 use the following interfaces if this routine fails.
 
 Next, DMA addresses using this API are kept track of using the
-dma64_addr_t type.  It is guarenteed to be big enough to hold any
+dma64_addr_t type.  It is guaranteed to be big enough to hold any
 DAC address the platform layer will give to you from the following
 routines.  If you have consistent mappings as well, you still
 use plain dma_addr_t to keep track of those.
@@ -745,7 +745,7 @@
 			 PCI_DMA_FROMDEVICE);
 
 It really should be self-explanatory.  We treat the ADDR and LEN
-seperately, because it is possible for an implementation to only
+separately, because it is possible for an implementation to only
 need the address in order to perform the unmap operation.
 
 			Platform Issues
diff -Nru a/Documentation/filesystems/Locking b/Documentation/filesystems/Locking
--- a/Documentation/filesystems/Locking	Fri Mar 15 17:51:02 2002
+++ b/Documentation/filesystems/Locking	Fri Mar 15 17:51:02 2002
@@ -121,10 +121,16 @@
 
 --------------------------- file_system_type ---------------------------
 prototypes:
-	struct super_block *(*read_super) (struct super_block *, void *, int);
+	struct super_block *(*get_sb) (struct file_system_type *, int, char *, void *);
+	void (*kill_sb) (struct super_block *);
 locking rules:
-may block	BKL	->s_lock	mount_sem
-yes		yes	yes		maybe
+		may block	BKL
+get_sb		yes		yes
+kill_sb		yes		yes
+
+->get_sb() returns error or a locked superblock (exclusive on ->s_umount).
+->kill_sb() takes a locked superblock, does all shutdown work on it,
+unlocks and drops the reference.
 
 --------------------------- address_space_operations --------------------------
 prototypes:
diff -Nru a/Documentation/filesystems/porting b/Documentation/filesystems/porting
--- a/Documentation/filesystems/porting	Fri Mar 15 17:51:02 2002
+++ b/Documentation/filesystems/porting	Fri Mar 15 17:51:02 2002
@@ -99,3 +99,20 @@
 
 ->link() callers hold ->i_sem on the object we are linking to.  Some of your
 problems might be over...
+
+---
+[mandatory]
+
+new file_system_type method - kill_sb(superblock).  If you are converting
+an existing filesystem, set it according to ->fs_flags:
+	FS_REQUIRES_DEV		-	kill_block_super
+	FS_LITTER		-	kill_litter_super
+	neither			-	kill_anon_super
+FS_LITTER is gone - just remove it from fs_flags.
+
+---
+[mandatory]
+
+	FS_SINGLE is gone (actually, that had happened back when ->get_sb()
+went in - and hadn't been documented ;-/).  Just remove it from fs_flags
+(and see ->get_sb() entry for other actions).
diff -Nru a/Documentation/filesystems/tmpfs.txt b/Documentation/filesystems/tmpfs.txt
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/filesystems/tmpfs.txt	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,102 @@
+Tmpfs is a file system which keeps all files in virtual memory.
+
+
+Everything in tmpfs is temporary in the sense that no files will be
+created on your hard drive. If you unmount a tmpfs instance,
+everything stored therein is lost.
+
+tmpfs puts everything into the kernel internal caches and grows and
+shrinks to accommodate the files it contains and is able to swap
+unneeded pages out to swap space. It has maximum size limits which can
+be adjusted on the fly via 'mount -o remount ...'
+
+If you compare it to ramfs (which was the template to create tmpfs)
+you gain swapping and limit checking. Another similar thing is the RAM
+disk (/dev/ram*), which simulates a fixed size hard disk in physical
+RAM, where you have to create an ordinary filesystem on top. Ramdisks
+cannot swap and you do not have the possibility to resize them. 
+
+Since tmpfs lives completely in the page cache and on swap, all tmpfs
+pages currently in memory will show up as cached. It will not show up
+as shared or something like that. Further on you can check the actual
+RAM+swap use of a tmpfs instance with df(1) and du(1).
+
+
+tmpfs has the following uses:
+
+1) There is always a kernel internal mount which you will not see at
+   all. This is used for shared anonymous mappings and SYSV shared
+   memory. 
+
+   This mount does not depend on CONFIG_TMPFS. If CONFIG_TMPFS is not
+   set, the user visible part of tmpfs is not build. But the internal
+   mechanisms are always present.
+
+2) glibc 2.2 and above expects tmpfs to be mounted at /dev/shm for
+   POSIX shared memory (shm_open, shm_unlink). Adding the following
+   line to /etc/fstab should take care of this:
+
+	tmpfs	/dev/shm	tmpfs	defaults	0 0
+
+   Remember to create the directory that you intend to mount tmpfs on
+   if necessary (/dev/shm is automagically created if you use devfs).
+
+   This mount is _not_ needed for SYSV shared memory. The internal
+   mount is used for that. (In the 2.3 kernel versions it was
+   necessary to mount the predecessor of tmpfs (shm fs) to use SYSV
+   shared memory)
+
+3) Some people (including me) find it very convenient to mount it
+   e.g. on /tmp and /var/tmp and have a big swap partition. But be
+   aware: loop mounts of tmpfs files do not work due to the internal
+   design. So mkinitrd shipped by most distributions will fail with a
+   tmpfs /tmp.
+
+4) And probably a lot more I do not know about :-)
+
+
+tmpfs has a couple of mount options:
+
+size:	   The limit of allocated bytes for this tmpfs instance. The 
+           default is half of your physical RAM without swap. If you
+	   oversize your tmpfs instances the machine will deadlock
+	   since the OOM handler will not be able to free that memory.
+nr_blocks: The same as size, but in blocks of PAGECACHE_SIZE.
+nr_inodes: The maximum number of inodes for this instance. The default
+           is half of the number of your physical RAM pages.
+
+These parameters accept a suffix k, m or g for kilo, mega and giga and
+can be changed on remount.
+
+To specify the initial root directory you can use the following mount
+options:
+
+mode:	The permissions as an octal number
+uid:	The user id 
+gid:	The group id
+
+These options do not have any effect on remount. You can change these
+parameters with chmod(1), chown(1) and chgrp(1) on a mounted filesystem.
+
+
+So 'mount -t tmpfs -o size=10G,nr_inodes=10k,mode=700 tmpfs /mytmpfs'
+will give you tmpfs instance on /mytmpfs which can allocate 10GB
+RAM/SWAP in 10240 inodes and it is only accessible by root.
+
+
+TODOs:
+
+1) give the size option a percent semantic: If you give a mount option
+   size=50% the tmpfs instance should be able to grow to 50 percent of
+   RAM + swap. So the instance should adapt automatically if you add
+   or remove swap space.
+2) loop mounts: This is difficult since loop.c relies on the readpage
+   operation. This operation gets a page from the caller to be filled
+   with the content of the file at that position. But tmpfs always has
+   the page and thus cannot copy the content to the given page. So it
+   cannot provide this operation. The VM had to be changed seriously
+   to achieve this.
+3) Show the number of tmpfs RAM pages. (As shared?)
+
+Author:
+   Christoph Rohland <cr@sap.com>, 1.12.01
diff -Nru a/Documentation/ia64/IRQ-redir.txt b/Documentation/ia64/IRQ-redir.txt
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/ia64/IRQ-redir.txt	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,69 @@
+IRQ affinity on IA64 platforms
+------------------------------
+                           07.01.2002, Erich Focht <efocht@ess.nec.de>
+
+
+By writing to /proc/irq/IRQ#/smp_affinity the interrupt routing can be
+controlled. The behavior on IA64 platforms is slightly different from
+that described in Documentation/IRQ-affinity.txt for i386 systems.
+
+Because of the usage of SAPIC mode and physical destination mode the
+IRQ target is one particular CPU and cannot be a mask of several
+CPUs. Only the first non-zero bit is taken into account.
+
+
+Usage examples:
+
+The target CPU has to be specified as a hexadecimal CPU mask. The
+first non-zero bit is the selected CPU. This format has been kept for
+compatibility reasons with i386.
+
+Set the delivery mode of interrupt 41 to fixed and route the
+interrupts to CPU #3 (logical CPU number) (2^3=0x08):
+     echo "8" >/proc/irq/41/smp_affinity
+
+Set the default route for IRQ number 41 to CPU 6 in lowest priority
+delivery mode (redirectable):
+     echo "r 40" >/proc/irq/41/smp_affinity
+
+The output of the command
+     cat /proc/irq/IRQ#/smp_affinity
+gives the target CPU mask for the specified interrupt vector. If the CPU
+mask is preceeded by the character "r", the interrupt is redirectable
+(i.e. lowest priority mode routing is used), otherwise its route is
+fixed.
+
+
+
+Initialization and default behavior:
+
+If the platform features IRQ redirection (info provided by SAL) all
+IO-SAPIC interrupts are initialized with CPU#0 as their default target
+and the routing is the so called "lowest priority mode" (actually
+fixed SAPIC mode with hint). The XTP chipset registers are used as hints
+for the IRQ routing. Currently in Linux XTP registers can have three
+values:
+	- minimal for an idle task,
+	- normal if any other task runs,
+	- maximal if the CPU is going to be switched off.
+The IRQ is routed to the CPU with lowest XTP register value, the
+search begins at the default CPU. Therefore most of the interrupts
+will be handled by CPU #0.
+
+If the platform doesn't feature interrupt redirection IOSAPIC fixed
+routing is used. The target CPUs are distributed in a round robin
+manner. IRQs will be routed only to the selected target CPUs. Check
+with
+        cat /proc/interrupts
+
+
+
+Comments:
+
+On large (multi-node) systems it is recommended to route the IRQs to
+the node to which the corresponding device is connected.
+For systems like the NEC AzusA we get IRQ node-affinity for free. This
+is because usually the chipsets on each node redirect the interrupts
+only to their own CPUs (as they cannot see the XTP registers on the
+other nodes).
+
diff -Nru a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
--- a/Documentation/kernel-parameters.txt	Fri Mar 15 17:51:03 2002
+++ b/Documentation/kernel-parameters.txt	Fri Mar 15 17:51:03 2002
@@ -467,6 +467,14 @@
 					whatever the firmware may have
 					done.
 
+		usepirqmask		[IA-32] Honor the possible IRQ mask
+					stored in the BIOS $PIR table. This is
+					needed on some systems with broken
+					BIOSes, notably some HP Pavilion N5400
+					and Omnibook XE3 notebooks. This will
+					have no effect if ACPI IRQ routing is
+					enabled.
+
 	pd.		[PARIDE]
 
 	pf.		[PARIDE]
diff -Nru a/Documentation/networking/NAPI_HOWTO.txt b/Documentation/networking/NAPI_HOWTO.txt
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/networking/NAPI_HOWTO.txt	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,749 @@
+HISTORY:
+February 16/2002 -- revision 0.2.1:
+COR typo corrected
+February 10/2002 -- revision 0.2:
+some spell checking ;->
+January 12/2002 -- revision 0.1
+This is still work in progress so may change.
+To keep up to date please watch this space.
+
+Introduction to NAPI
+====================
+
+NAPI is a proven (www.cyberus.ca/~hadi/usenix-paper.tgz) technique
+to improve network performance on Linux. For more details please
+read that paper.
+NAPI provides a "inherent mitigation" which is bound by system capacity
+as can be seen from the following data collected by Robert on Gigabit 
+ethernet (e1000):
+
+ Psize    Ipps       Tput     Rxint     Txint    Done     Ndone
+ ---------------------------------------------------------------
+   60    890000     409362        17     27622        7     6823
+  128    758150     464364        21      9301       10     7738
+  256    445632     774646        42     15507       21    12906
+  512    232666     994445    241292     19147   241192     1062
+ 1024    119061    1000003    872519     19258   872511        0
+ 1440     85193    1000003    946576     19505   946569        0
+ 
+
+Legend:
+"Ipps" stands for input packets per second. 
+"Tput" == packets out of total 1M that made it out.
+"txint" == transmit completion interrupts seen
+"Done" == The number of times that the poll() managed to pull all
+packets out of the rx ring. Note from this that the lower the
+load the more we could clean up the rxring
+"Ndone" == is the converse of "Done". Note again, that the higher
+the load the more times we couldnt clean up the rxring.
+
+Observe that:
+when the NIC receives 890Kpackets/sec only 17 rx interrupts are generated. 
+The system cant handle the processing at 1 interrupt/packet at that load level. 
+At lower rates on the other hand, rx interrupts go up and therefore the
+interrupt/packet ratio goes up (as observable from that table). So there is
+possibility that under low enough input, you get one poll call for each
+input packet caused by a single interrupt each time. And if the system 
+cant handle interrupt per packet ratio of 1, then it will just have to 
+chug along ....
+
+
+0) Prerequisites:
+==================
+A driver MAY continue using the old 2.4 technique for interfacing
+to the network stack and not benefit from the NAPI changes.
+NAPI additions to the kernel do not break backward compatibility.
+NAPI, however, requires the following features to be available:
+
+A) DMA ring or enough RAM to store packets in software devices.
+
+B) Ability to turn off interrupts or maybe events that send packets up 
+the stack.
+
+NAPI processes packet events in what is known as dev->poll() method.
+Typically, only packet receive events are processed in dev->poll(). 
+The rest of the events MAY be processed by the regular interrupt handler 
+to reduce processing latency (justified also because there are not that 
+many of them).
+Note, however, NAPI does not enforce that dev->poll() only processes 
+receive events. 
+Tests with the tulip driver indicated slightly increased latency if
+all of the interrupt handler is moved to dev->poll(). Also MII handling
+gets a little trickier.
+The example used in this document is to move the receive processing only
+to dev->poll(); this is shown with the patch for the tulip driver.
+For an example of code that moves all the interrupt driver to 
+dev->poll() look at the ported e1000 code.
+
+There are caveats that might force you to go with moving everything to 
+dev->poll(). Different NICs work differently depending on their status/event 
+acknowledgement setup. 
+There are two types of event register ACK mechanisms.
+	I)  what is known as Clear-on-read (COR).
+	when you read the status/event register, it clears everything!
+	The natsemi and sunbmac NICs are known to do this.
+	In this case your only choice is to move all to dev->poll()
+
+	II) Clear-on-write (COW)
+	 i) you clear the status by writting a 1 in the bit-location you want.
+		These are the majority of the NICs and work the best with NAPI.
+		Put only receive events in dev->poll(); leave the rest in
+		the old interrupt handler.
+	 ii) whatever you write in the status register clears every thing ;->
+		Cant seem to find any supported by Linux which do this. If
+		someone knows such a chip email us please.
+		Move all to dev->poll()
+
+C) Ability to detect new work correctly.
+NAPI works by shutting down event interrupts when theres work and
+turning them on when theres none. 
+New packets might show up in the small window while interrupts were being 
+re-enabled (refer to appendix 2).  A packet might sneak in during the period 
+we are enabling interrupts. We only get to know about such a packet when the 
+next new packet arrives and generates an interrupt. 
+Essentially, there is a small window of opportunity for a race condition
+which for clarity we'll refer to as the "rotting packet".
+
+This is a very important topic and appendix 2 is dedicated for more 
+discussion.
+
+Locking rules and environmental guarantees
+==========================================
+
+-Guarantee: Only one CPU at any time can call dev->poll(); this is because
+only one CPU can pick the initial interrupt and hence the initial
+netif_rx_schedule(dev);
+- The core layer invokes devices to send packets in a round robin format.
+This implies receive is totaly lockless because of the guarantee only that 
+one CPU is executing it.
+-  contention can only be the result of some other CPU accessing the rx
+ring. This happens only in close() and suspend() (when these methods
+try to clean the rx ring); 
+****guarantee: driver authors need not worry about this; synchronization 
+is taken care for them by the top net layer.
+-local interrupts are enabled (if you dont move all to dev->poll()). For 
+example link/MII and txcomplete continue functioning just same old way. 
+This improves the latency of processing these events. It is also assumed that 
+the receive interrupt is the largest cause of noise. Note this might not 
+always be true. 
+[according to Manfred Spraul, the winbond insists on sending one 
+txmitcomplete interrupt for each packet (although this can be mitigated)].
+For these broken drivers, move all to dev->poll().
+
+For the rest of this text, we'll assume that dev->poll() only
+processes receive events.
+
+new methods introduce by NAPI
+=============================
+
+a) netif_rx_schedule(dev)
+Called by an IRQ handler to schedule a poll for device
+
+b) netif_rx_schedule_prep(dev)
+puts the device in a state which allows for it to be added to the
+CPU polling list if it is up and running. You can look at this as
+the first half of  netif_rx_schedule(dev) above; the second half
+being c) below.
+
+c) __netif_rx_schedule(dev)
+Add device to the poll list for this CPU; assuming that _prep above
+has already been called and returned 1.
+
+d) netif_rx_reschedule(dev, undo)
+Called to reschedule polling for device specifically for some
+deficient hardware. Read Appendix 2 for more details.
+
+e) netif_rx_complete(dev)
+
+Remove interface from the CPU poll list: it must be in the poll list
+on current cpu. This primitive is called by dev->poll(), when
+it completes its work. The device cannot be out of poll list at this
+call, if it is then clearly it is a BUG(). You'll know ;->
+
+All these above nethods are used below. So keep reading for clarity.
+
+Device driver changes to be made when porting NAPI
+==================================================
+
+Below we describe what kind of changes are required for NAPI to work.
+
+1) introduction of dev->poll() method 
+=====================================
+
+This is the method that is invoked by the network core when it requests
+for new packets from the driver. A driver is allowed to send upto
+dev->quota packets by the current CPU before yielding to the network
+subsystem (so other devices can also get opportunity to send to the stack).
+
+dev->poll() prototype looks as follows:
+int my_poll(struct net_device *dev, int *budget)
+
+budget is the remaining number of packets the network subsystem on the
+current CPU can send up the stack before yielding to other system tasks.
+*Each driver is responsible for decrementing budget by the total number of
+packets sent.
+	Total number of packets cannot exceed dev->quota.
+
+dev->poll() method is invoked by the top layer, the driver just sends if it 
+can to the stack the packet quantity requested.
+
+more on dev->poll() below after the interrupt changes are explained.
+
+2) registering dev->poll() method
+===================================
+
+dev->poll should be set in the dev->probe() method. 
+e.g:
+dev->open = my_open;
+.
+.
+/* two new additions */
+/* first register my poll method */
+dev->poll = my_poll;
+/* next register my weight/quanta; can be overriden in /proc */
+dev->weight = 16;
+.
+.
+dev->stop = my_close;
+
+
+
+3) scheduling dev->poll()
+=============================
+This involves modifying the interrupt handler and the code
+path which takes the packet off the NIC and sends them to the 
+stack.
+
+it's important at this point to introduce the classical D Becker 
+interrupt processor:
+
+------------------
+static void
+netdevice_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+
+	struct net_device *dev = (struct net_device *)dev_instance;
+	struct my_private *tp = (struct my_private *)dev->priv;
+
+	int work_count = my_work_count;
+        status = read_interrupt_status_reg();
+        if (status == 0)
+                return;         /* Shared IRQ: not us */
+        if (status == 0xffff)
+                return;         /* Hot unplug */
+        if (status & error)
+		do_some_error_handling()
+        
+	do {
+		acknowledge_ints_ASAP();
+
+		if (status & link_interrupt) {
+			spin_lock(&tp->link_lock);
+			do_some_link_stat_stuff();
+			spin_lock(&tp->link_lock);
+		}
+		
+		if (status & rx_interrupt) {
+			receive_packets(dev);
+		}
+
+		if (status & rx_nobufs) {
+			make_rx_buffs_avail();
+		}
+			
+		if (status & tx_related) {
+			spin_lock(&tp->lock);
+			tx_ring_free(dev);
+			if (tx_died)
+				restart_tx();
+			spin_unlock(&tp->lock);
+		}
+
+		status = read_interrupt_status_reg();
+
+	} while (!(status & error) || more_work_to_be_done);
+
+}
+
+----------------------------------------------------------------------
+
+We now change this to what is shown below to NAPI-enable it:
+
+----------------------------------------------------------------------
+static void
+netdevice_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+	struct net_device *dev = (struct net_device *)dev_instance;
+	struct my_private *tp = (struct my_private *)dev->priv;
+
+        status = read_interrupt_status_reg();
+        if (status == 0)
+                return;         /* Shared IRQ: not us */
+        if (status == 0xffff)
+                return;         /* Hot unplug */
+        if (status & error)
+		do_some_error_handling();
+        
+	do {
+/************************ start note *********************************/		
+		acknowledge_ints_ASAP();  // dont ack rx and rxnobuff here
+/************************ end note *********************************/		
+
+		if (status & link_interrupt) {
+			spin_lock(&tp->link_lock);
+			do_some_link_stat_stuff();
+			spin_unlock(&tp->link_lock);
+		}
+/************************ start note *********************************/		
+		if (status & rx_interrupt || (status & rx_nobuffs)) {
+			if (netif_rx_schedule_prep(dev)) {
+
+				/* disable interrupts caused 
+			         *	by arriving packets */
+				disable_rx_and_rxnobuff_ints();
+				/* tell system we have work to be done. */
+				__netif_rx_schedule(dev);
+			} else {
+				printk("driver bug! interrupt while in poll\n");
+				/* FIX by disabling interrupts  */
+				disable_rx_and_rxnobuff_ints();
+			}
+		}
+/************************ end note note *********************************/		
+			
+		if (status & tx_related) {
+			spin_lock(&tp->lock);
+			tx_ring_free(dev);
+
+			if (tx_died)
+				restart_tx();
+			spin_unlock(&tp->lock);
+		}
+
+		status = read_interrupt_status_reg();
+
+/************************ start note *********************************/		
+	} while (!(status & error) || more_work_to_be_done(status));
+/************************ end note note *********************************/		
+
+}
+
+---------------------------------------------------------------------
+
+
+We note several things from above:
+
+I) Any interrupt source which is caused by arriving packets is now
+turned off when it occurs. Depending on the hardware, there could be
+several reasons that arriving packets would cause interrupts; these are the
+interrupt sources we wish to avoid. The two common ones are a) a packet 
+arriving (rxint) b) a packet arriving and finding no DMA buffers available
+(rxnobuff) .
+This means also acknowledge_ints_ASAP() will not clear the status
+register for those two items above; clearing is done in the place where 
+proper work is done within NAPI; at the poll() and refill_rx_ring() 
+discussed further below.
+netif_rx_schedule_prep() returns 1 if device is in running state and
+gets successfully added to the core poll list. If we get a zero value
+we can _almost_ assume are already added to the list (instead of not running. 
+Logic based on the fact that you shouldnt get interrupt if not running)
+We rectify this by disabling rx and rxnobuf interrupts.
+
+II) that receive_packets(dev) and make_rx_buffs_avail() may have dissapeared.
+These functionalities are still around actually......
+
+infact, receive_packets(dev) is very close to my_poll() and 
+make_rx_buffs_avail() is invoked from my_poll()
+
+4) converting receive_packets() to dev->poll()
+===============================================
+
+We need to convert the classical D Becker receive_packets(dev) to my_poll()
+
+First the typical receive_packets() below:
+-------------------------------------------------------------------
+
+/* this is called by interrupt handler */
+static void receive_packets (struct net_device *dev)
+{
+
+	struct my_private *tp = (struct my_private *)dev->priv;
+	rx_ring = tp->rx_ring;
+	cur_rx = tp->cur_rx;
+	int entry = cur_rx % RX_RING_SIZE;
+	int received = 0;
+	int rx_work_limit = tp->dirty_rx + RX_RING_SIZE - tp->cur_rx;
+
+	while (rx_ring_not_empty) {
+		u32 rx_status;
+		unsigned int rx_size;
+		unsigned int pkt_size;
+		struct sk_buff *skb;
+                /* read size+status of next frame from DMA ring buffer */
+		/* the number 16 and 4 are just examples */
+                rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
+                rx_size = rx_status >> 16;
+                pkt_size = rx_size - 4;
+
+		/* process errors */
+                if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
+                    (!(rx_status & RxStatusOK))) {
+                        netdrv_rx_err (rx_status, dev, tp, ioaddr);
+                        return;
+                }
+
+                if (--rx_work_limit < 0)
+                        break;
+
+		/* grab a skb */
+                skb = dev_alloc_skb (pkt_size + 2);
+                if (skb) {
+			.
+			.
+			netif_rx (skb);
+			.
+			.
+                } else {  /* OOM */
+			/*seems very driver specific ... some just pass
+			whatever is on the ring already. */
+                }
+
+		/* move to the next skb on the ring */
+		entry = (++tp->cur_rx) % RX_RING_SIZE;
+		received++ ;
+
+        }
+
+	/* store current ring pointer state */
+        tp->cur_rx = cur_rx;
+
+        /* Refill the Rx ring buffers if they are needed */
+	refill_rx_ring();
+	.
+	.
+
+}
+-------------------------------------------------------------------
+We change it to a new one below; note the additional parameter in
+the call.
+
+-------------------------------------------------------------------
+
+/* this is called by the network core */
+static void my_poll (struct net_device *dev, int *budget)
+{
+
+	struct my_private *tp = (struct my_private *)dev->priv;
+	rx_ring = tp->rx_ring;
+	cur_rx = tp->cur_rx;
+	int entry = cur_rx % RX_BUF_LEN;
+	/* maximum packets to send to the stack */
+/************************ note note *********************************/		
+	int rx_work_limit = dev->quota;
+
+/************************ end note note *********************************/		
+    do {  // outer beggining loop starts here
+
+	clear_rx_status_register_bit();
+
+	while (rx_ring_not_empty) {
+		u32 rx_status;
+		unsigned int rx_size;
+		unsigned int pkt_size;
+		struct sk_buff *skb;
+                /* read size+status of next frame from DMA ring buffer */
+		/* the number 16 and 4 are just examples */
+                rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
+                rx_size = rx_status >> 16;
+                pkt_size = rx_size - 4;
+
+		/* process errors */
+                if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
+                    (!(rx_status & RxStatusOK))) {
+                        netdrv_rx_err (rx_status, dev, tp, ioaddr);
+                        return;
+                }
+
+/************************ note note *********************************/		
+                if (--rx_work_limit < 0) { /* we got packets, but no quota */
+			/* store current ring pointer state */
+			tp->cur_rx = cur_rx;
+
+			/* Refill the Rx ring buffers if they are needed */
+			refill_rx_ring(dev);
+                        goto not_done;
+		}
+/**********************  end note **********************************/
+
+		/* grab a skb */
+                skb = dev_alloc_skb (pkt_size + 2);
+                if (skb) {
+			.
+			.
+/************************ note note *********************************/		
+			netif_receive_skb (skb);
+/**********************  end note **********************************/
+			.
+			.
+                } else {  /* OOM */
+			/*seems very driver specific ... common is just pass
+			whatever is on the ring already. */
+                }
+
+		/* move to the next skb on the ring */
+		entry = (++tp->cur_rx) % RX_RING_SIZE;
+		received++ ;
+
+        }
+
+	/* store current ring pointer state */
+        tp->cur_rx = cur_rx;
+
+        /* Refill the Rx ring buffers if they are needed */
+	refill_rx_ring(dev);
+	
+	/* no packets on ring; but new ones can arrive since we last 
+	   checked  */
+	status = read_interrupt_status_reg();
+	if (rx status is not set) {
+                        /* If something arrives in this narrow window,
+			an interrupt will be generated */
+                        goto done;
+	}
+	/* done! at least thats what it looks like ;->
+	if new packets came in after our last check on status bits
+	they'll be caught by the while check and we go back and clear them 
+	since we havent exceeded our quota */
+    } while (rx_status_is_set); 
+
+done:
+
+/************************ note note *********************************/		
+        dev->quota -= received;
+        *budget -= received;
+
+        /* If RX ring is not full we are out of memory. */
+        if (tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
+                goto oom;
+
+	/* we are happy/done, no more packets on ring; put us back
+	to where we can start processing interrupts again */
+        netif_rx_complete(dev);
+	enable_rx_and_rxnobuf_ints();
+
+       /* The last op happens after poll completion. Which means the following:
+        * 1. it can race with disabling irqs in irq handler (which are done to 
+	* schedule polls)
+        * 2. it can race with dis/enabling irqs in other poll threads
+        * 3. if an irq raised after the begining of the outer  beginning 
+        * loop(marked in the code above), it will be immediately
+        * triggered here.
+        *
+        * Summarizing: the logic may results in some redundant irqs both
+        * due to races in masking and due to too late acking of already
+        * processed irqs. The good news: no events are ever lost.
+        */
+
+        return 0;   /* done */
+
+not_done:
+        if (tp->cur_rx - tp->dirty_rx > RX_RING_SIZE/2 ||
+            tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
+                refill_rx_ring(dev);
+
+        if (!received) {
+                printk("received==0\n");
+                received = 1;
+        }
+        dev->quota -= received;
+        *budget -= received;
+        return 1;  /* not_done */
+
+oom:
+        /* Start timer, stop polling, but do not enable rx interrupts. */
+	start_poll_timer(dev);
+        return 0;  /* we'll take it from here so tell core "done"*/
+
+/************************ End note note *********************************/		
+}
+-------------------------------------------------------------------
+
+From above we note that:
+0) rx_work_limit = dev->quota 
+1) refill_rx_ring() is in charge of clearing the bit for rxnobuff when
+it does the work.
+2) We have a done and not_done state.
+3) instead of netif_rx() we call netif_receive_skb() to pass the skb.
+4) we have a new way of handling oom condition
+5) A new outer for (;;) loop has been added. This serves the purpose of
+ensuring that if a new packet has come in, after we are all set and done,
+and we have not exceeded our quota that we continue sending packets up.
+ 
+
+-----------------------------------------------------------
+Poll timer code will need to do the following:
+
+a) 
+
+        if (tp->cur_rx - tp->dirty_rx > RX_RING_SIZE/2 ||
+            tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL) 
+                refill_rx_ring(dev);
+
+        /* If RX ring is not full we are still out of memory.
+	   Restart the timer again. Else we re-add ourselves 
+           to the master poll list.
+         */
+
+        if (tp->rx_buffers[tp->dirty_rx % RX_RING_SIZE].skb == NULL)
+                restart_timer();
+
+	else netif_rx_schedule(dev);  /* we are back on the poll list */
+	
+5) dev->close() and dev->suspend() issues
+==========================================
+The driver writter neednt worry about this. The top net layer takes
+care of it.
+
+6) Adding new Stats to /proc 
+=============================
+In order to debug some of the new features, we introduce new stats
+that need to be collected.
+TODO: Fill this later.
+
+APPENDIX 1: discussion on using ethernet HW FC
+==============================================
+Most chips with FC only send a pause packet when they run out of Rx buffers.
+Since packets are pulled off the DMA ring by a softirq in NAPI,
+if the system is slow in grabbing them and we have a high input
+rate (faster than the system's capacity to remove packets), then theoretically
+there will only be one rx interrupt for all packets during a given packetstorm.
+Under low load, we might have a single interrupt per packet.
+FC should be programmed to apply in the case when the system cant pull out
+packets fast enough i.e send a pause only when you run out of rx buffers.
+Note FC in itself is a good solution but we have found it to not be
+much of a commodity feature (both in NICs and switches) and hence falls
+under the same category as using NIC based mitigation. Also experiments
+indicate that its much harder to resolve the resource allocation
+issue (aka lazy receiving that NAPI offers) and hence quantify its usefullness
+proved harder. In any case, FC works even better with NAPI but is not
+necessary.
+
+
+APPENDIX 2: the "rotting packet" race-window avoidance scheme 
+=============================================================
+
+There are two types of associations seen here
+
+1) status/int which honors level triggered IRQ
+
+If a status bit for receive or rxnobuff is set and the corresponding 
+interrupt-enable bit is not on, then no interrupts will be generated. However, 
+as soon as the "interrupt-enable" bit is unmasked, an immediate interrupt is 
+generated.  [assuming the status bit was not turned off].
+Generally the concept of level triggered IRQs in association with a status and
+interrupt-enable CSR register set is used to avoid the race.
+
+If we take the example of the tulip:
+"pending work" is indicated by the status bit(CSR5 in tulip).
+the corresponding interrupt bit (CSR7 in tulip) might be turned off (but
+the CSR5 will continue to be turned on with new packet arrivals even if
+we clear it the first time)
+Very important is the fact that if we turn on the interrupt bit on when
+status is set that an immediate irq is triggered.
+ 
+If we cleared the rx ring and proclaimed there was "no more work
+to be done" and then went on to do a few other things;  then when we enable
+interrupts, there is a possibility that a new packet might sneak in during
+this phase. It helps to look at the pseudo code for the tulip poll
+routine:
+
+--------------------------
+        do {
+                ACK;
+                while (ring_is_not_empty()) {
+                        work-work-work
+                        if quota is exceeded: exit, no touching irq status/mask
+                }
+                /* No packets, but new can arrive while we are doing this*/
+                CSR5 := read
+                if (CSR5 is not set) {
+                        /* If something arrives in this narrow window here,
+                        *  where the comments are ;-> irq will be generated */
+                        unmask irqs;
+                        exit poll;
+                }
+        } while (rx_status_is_set);
+------------------------
+
+CSR5 bit of interest is only the rx status. 
+If you look at the last if statement: 
+you just finished grabbing all the packets from the rx ring .. you check if
+status bit says theres more packets just in ... it says none; you then
+enable rx interrupts again; if a new packet just came in during this check,
+we are counting that CSR5 will be set in that small window of opportunity
+and that by re-enabling interrupts, we would actually triger an interrupt
+to register the new packet for processing.
+
+[The above description nay be very verbose, if you have better wording 
+that will make this more understandable, please suggest it.]
+
+2) non-capable hardware
+
+These do not generally respect level triggered IRQs. Normally,
+irqs may be lost while being masked and the only way to leave poll is to do
+a double check for new input after netif_rx_complete() is invoked
+and re-enable polling (after seeing this new input).
+
+Sample code:
+
+---------
+	.
+	.
+restart_poll:
+	while (ring_is_not_empty()) {
+		work-work-work
+		if quota is exceeded: exit, not touching irq status/mask
+	}
+	.
+	.
+	.
+	enable_rx_interrupts()
+	netif_rx_complete(dev);
+	if (ring_has_new_packet() && netif_rx_reschedule(dev, received)) {
+		disable_rx_and_rxnobufs()
+		goto restart_poll
+	} while (rx_status_is_set);
+---------
+		
+Basically netif_rx_complete() removes us from the poll list, but because a
+new packet which will never be caught due to the possibility of a race
+might come in, we attempt to re-add ourselves to the poll list. 
+
+
+
+--------------------------------------------------------------------
+
+relevant sites:
+==================
+ftp://robur.slu.se/pub/Linux/net-development/NAPI/
+
+
+--------------------------------------------------------------------
+TODO: Write net-skeleton.c driver.
+-------------------------------------------------------------
+
+Authors:
+========
+Alexey Kuznetsov <kuznet@ms2.inr.ac.ru>
+Jamal Hadi Salim <hadi@cyberus.ca>
+Robert Olsson <Robert.Olsson@data.slu.se>
+
+Acknowledgements:
+================
+People who made this document better:
+
+Lennert Buytenhek <buytenh@gnu.org>
+Andrew Morton  <akpm@zip.com.au>
+Manfred Spraul <manfred@colorfullife.com>
+Donald Becker <becker@scyld.com>
+Jeff Garzik <jgarzik@mandrakesoft.com>
diff -Nru a/Documentation/networking/comx.txt b/Documentation/networking/comx.txt
--- a/Documentation/networking/comx.txt	Fri Mar 15 17:51:02 2002
+++ b/Documentation/networking/comx.txt	Fri Mar 15 17:51:02 2002
@@ -24,6 +24,8 @@
 LoCOMX (1x512 kbps passive board)
 MixCOM (1x512 or 2x512kbps passive board with a hardware watchdog an
 	optional BRI interface and optional flashROM (1-32M))
+SliceCOM	(1x2Mbps channelized E1 board)
+PciCOM	(X21)
 
 At the moment of writing this document, the (Cisco)-HDLC, LAPB, SyncPPP and
 Frame Relay (DTE, rfc1294 IP encapsulation with partially implemented Q933a 
@@ -72,7 +74,7 @@
 To create the interface 'comx0' which is the first channel of a COMX card:
 
 insmod comx 
-# insmod comx-hw-comx ; insmod comx-proto-hdlc  (these are usually
+# insmod comx-hw-comx ; insmod comx-proto-ppp  (these are usually
 autoloaded if you use the kernel module loader)
 
 mkdir /proc/comx/comx0
@@ -141,47 +143,45 @@
 The MixCOM board doesn't require firmware, the driver communicates with
 it through I/O ports. You can have three of these cards in one machine.
 
-THE HDLC LINE PROTOCOL DRIVER
+THE SLICECOM DRIVER
+
+The SliceCOM board doesn't require firmware. You can have 4 of these cards
+in one machine. The driver doesn't (yet) support shared interrupts, so
+you will need a separate IRQ line for every board.
+Read linux/Documentation/networking/slicecom.txt for help on configuring
+this adapter.
+
+THE HDLC/PPP LINE PROTOCOL DRIVER
+
+The HDLC/SyncPPP line protocol driver uses the kernel's built-in syncppp
+driver (syncppp.o). You don't have to manually select syncppp.o when building
+the kernel, the dependencies compile it in automatically.
 
-There's only one configurable parameter with this protocol: the 'keepalive'
-value. You can set this in seconds or set to 'off'. Agree with the administrator
-of your peer router on this setting. The default is 10 (seconds).
 
-EXAMPLE
 
+
+EXAMPLE
 (setting up hw parameters, see above)
+
+# using HDLC:
 echo hdlc >/proc/comx/comx0/protocol
 echo 10 >/proc/comx/comx0/keepalive	<- not necessary, 10 is the default
 ifconfig comx0 1.2.3.4 pointopoint 5.6.7.8 netmask 255.255.255.255
 
-
-THE PPP LINE PROTOCOL DRIVER
-
-To use this driver, you have to have ppp-2.3.4, and have a modified version of
-pppd (this pppd will work as async pppd to, the modifiactions merely relax 
-some restricions in order to be able to use non-async lines too.
-If configured, this driver can use Van Jacobson TCP header compression (you'll
-need the slhc.o module for this).
-Additionally to use this protocol, enable async ppp in your kernel config, and
-create the comx device special files in /dev. They're character special files
-with major 88, and their names must be the same as their network interface
-counterparts (i.e /dev/comx0 with minor 0 corresponds interface comx0 and so
-on).
-
-EXAMPLE
-
 (setting up hw parameters, see above)
+
+# using PPP:
 echo ppp >/proc/comx/comx0/protocol
 ifconfig comx0 up
-pppd comx0 1.2.3.4:5.6.7.8 persist	<- with this option pppd won't exit
-					   when the line goes down
+ifconfig comx0 1.2.3.4 pointopoint 5.6.7.8 netmask 255.255.255.255
+
 
 THE LAPB LINE PROTOCOL DRIVER
 
 For this, you'll need to configure LAPB support (See 'LAPB Data Link Driver' in
 'Network options' section) into your kernel (thanks to Jonathan Naylor for his 
 excellent implementation). 
-comxlapb.o provides the following files in the appropriate directory
+comx-proto-lapb.o provides the following files in the appropriate directory
 (the default values in parens): t1 (5), t2 (1), n2 (20), mode (DTE, STD) and
 window (7). Agree with the administrator of your peer router on these
 settings (most people use defaults, but you have to know if you are DTE or
@@ -221,7 +221,7 @@
 
 boardtype:
 Type of the hardware. Valid values are:
- 'comx', 'hicomx', 'locomx', 'cmx'.
+ 'comx', 'hicomx', 'locomx', 'cmx', 'slicecom'.
 
 protocol:
 Data-link protocol on this channel. Can be: HDLC, LAPB, PPP, FRAD
diff -Nru a/Documentation/networking/slicecom.hun b/Documentation/networking/slicecom.hun
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/networking/slicecom.hun	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,371 @@
+
+SliceCOM adapter felhasznaloi dokumentacioja - 0.51 verziohoz
+
+Bartók István <bartoki@itc.hu>
+Utolso modositas: Wed Aug 29 17:26:58 CEST 2001
+
+-----------------------------------------------------------------
+
+Hasznalata:
+
+Forditas:
+
+Code maturity level options
+	[*] Prompt for development and/or incomplete code/drivers
+
+Network device support
+	Wan interfaces
+		<M> MultiGate (COMX) synchronous
+			<M> Support for MUNICH based boards: SliceCOM, PCICOM (NEW)
+			<M> Support for HDLC and syncPPP...
+
+
+A modulok betoltese:
+
+modprobe comx
+
+modprobe comx-proto-ppp		# a Cisco-HDLC es a SyncPPP protokollt is
+				# ez a modul adja
+
+modprobe comx-hw-munich		# a modul betoltodeskor azonnal jelent a
+				# syslogba a detektalt kartyakrol
+
+
+Konfiguralas:
+
+# Ezen az interfeszen Cisco-HDLC vonali protokoll fog futni
+# Az interfeszhez rendelt idoszeletek: 1,2 (128 kbit/sec-es vonal)
+# (a G.703 keretben az elso adatot vivo idoszelet az 1-es)
+#
+mkdir /proc/comx/comx0.1/
+echo slicecom	>/proc/comx/comx0.1/boardtype
+echo hdlc	>/proc/comx/comx0.1/protocol
+echo 1 2	>/proc/comx/comx0.1/timeslots
+
+
+# Ezen az interfeszen SyncPPP vonali protokoll fog futni
+# Az interfeszhez rendelt idoszelet: 3 (64 kbit/sec-es vonal)
+#
+mkdir /proc/comx/comx0.2/
+echo slicecom	>/proc/comx/comx0.2/boardtype
+echo ppp	>/proc/comx/comx0.2/protocol
+echo 3		>/proc/comx/comx0.2/timeslots
+
+...
+
+ifconfig comx0.1 up
+ifconfig comx0.2 up
+
+-----------------------------------------------------------------
+
+A COMX driverek default 20 csomagnyi transmit queue-t rendelnek a halozati
+interfeszekhez. WAN halozatokban ennel hosszabbat is szokas hasznalni
+(20 es 100 kozott), hogy a vonal kihasznaltsaga nagy terheles eseten jobb
+legyen (bar ezzel megno a varhato kesleltetes a csomagok sorban allasa miatt):
+
+# ifconfig comx0 txqueuelen 50
+
+Ezt a beallitasi lehetoseget csak az ujabb disztribuciok ifconfig parancsa
+tamogatja (amik mar a 2.2 kernelekhez keszultek, mint a RedHat 6.1 vagy a
+Debian 2.2).
+
+A 2.1-es Debian disztribuciohoz a http://www.debian.org/~rcw/2.2/netbase/
+cimrol toltheto le ujabb netbase csomag, ami mar ilyet tamogato ifconfig
+parancsot tartalmaz. Bovebben a 2.2 kernel hasznalatarol Debian 2.1 alatt:
+http://www.debian.org/releases/stable/running-kernel-2.2
+
+-----------------------------------------------------------------
+
+A kartya LED-jeinek jelentese:
+
+piros	- eg, ha Remote Alarm-ot kuld a tuloldal
+zold	- eg, ha a vett jelben megtalalja a keretszinkront
+
+Reszletesebben:
+
+piros:	zold:	jelentes:
+
+-	-	nincs keretszinkron (nincs jel, vagy rossz a jel)
+-	eg	"minden rendben"
+eg	eg	a vetel OK, de a tuloldal Remote Alarm-ot kuld
+eg	-	ez nincs ertelmezve, egyelore funkcio nelkul
+
+-----------------------------------------------------------------
+
+Reszletesebb leiras a hardver beallitasi lehetosegeirol:
+
+Az altalanos,- es a protokoll-retegek beallitasi lehetosegeirol a 'comx.txt'
+fajlban leirtak SliceCOM kartyanal is ervenyesek, itt csak a hardver-specifikus
+beallitasi lehetosegek vannak osszefoglalva:
+
+Konfiguralasi interfesz a /proc/comx/ alatt:
+
+Minden timeslot-csoportnak kulon comx* interfeszt kell letrehozni mkdir-rel:
+comx0, comx1, .. stb. Itt beallithato, hogy az adott interfesz hanyadik kartya
+melyik timeslotja(i)bol alljon ossze. A Cisco-fele serial3:1 elnevezesek
+(serial3:1 = a 3. kartyaban az 1-es idoszelet-csoport) Linuxon aliasing-ot
+jelentenenek, ezert mi nem tudunk ilyen elnevezest hasznalni.
+
+Tobb kartya eseten a comx0.1, comx0.2, ... vagy slice0.1, slice0.2 nevek
+hasznalhatoak.
+
+Tobb SliceCOM kartya is lehet egy gepben, de sajat interrupt kell mindegyiknek,
+nem tud meg megosztott interruptot kezelni.
+
+Az egesz kartyat erinto beallitasok:
+
+Az ioport es irq beallitas nincs: amit a PCI BIOS kioszt a rendszernek,
+azt hasznalja a driver.
+
+
+comx0/boardnum	- hanyadik SliceCOM kartya a gepben (a 'termeszetes' PCI
+		sorrendben ertve: ahogyan a /proc/pci-ban vagy az 'lspci'
+		kimeneteben megjelenik, altalaban az alaplapi PCI meghajto
+		aramkorokhoz kozelebb eso kartyak a kisebb sorszamuak)
+
+		Default: 0 (0-tol kezdodik a szamolas)
+
+
+Bar a kovetkezoket csak egy-egy interfeszen allitjuk at, megis az egesz kartya
+mukodeset egyszerre allitjak. A megkotes hogy csak UP-ban levo interfeszen
+hasznalhatoak, azert van, mert kulonben nem vart eredmenyekre vezetne egy ilyen
+paranccsorozat:
+
+	echo 0        >boardnum
+	echo internal >clock_source
+	echo 1        >boardnum
+
+- Ez a 0-s board clock_source-at allitana at.
+
+Ezek a beallitasok megmaradnak az osszes interfesz torlesekor, de torlodnek
+a driver modul ki/betoltesekor.
+
+
+comx0/clock_source - A Tx orajelforrasa, a Cisco-val hasonlatosra keszult.
+	Hasznalata:
+
+	papaya:# echo line     >/proc/comx/comx0/clock_source
+	papaya:# echo internal >/proc/comx/comx0/clock_source
+
+	line     - A Tx orajelet a vett adatfolyambol dekodolja, igyekszik
+		igazodni hozza. Ha nem lat orajelet az inputon, akkor
+		atall a sajat orajelgeneratorara.
+	internal - A Tx orajelet a sajat orajelgeneratora szolgaltatja.
+
+	Default: line
+
+	Normal osszeallitas eseten a tavkozlesi szolgaltato eszkoze
+	(pl. HDSL modem) adja az orajelet, ezert ez a default.
+
+
+comx0/framing	- A CRC4 ki/be kapcsolasa
+
+	A CRC4: 16 PCM keretet (A PCM keret az, amibe a 32 darab 64
+	kilobites csatorna van bemultiplexalva. Nem osszetevesztendo a HDLC
+	kerettel.) 2x8 -as csoportokra osztanak, es azokhoz 4-4 bites CRC-t
+	szamolnak. Elsosorban a vonal minosegenek a monitorozasara szolgal.
+
+	papaya:~# echo crc4	>/proc/comx/comx0/framing
+	papaya:~# echo no-crc4	>/proc/comx/comx0/framing
+
+	Default a 'crc4', a MATAV vonalak altalaban igy futnak. De ha nem
+	egyforma is a beallitas a vonal ket vegen, attol a forgalom altalaban
+	at tud menni.
+
+
+comx0/linecode	- A vonali kodolas beallitasa
+
+	papaya:~# echo hdb3	>/proc/comx/comx0/linecode
+	papaya:~# echo ami	>/proc/comx/comx0/linecode
+
+	Default a 'hdb3', a MATAV vonalak igy futnak.
+	
+	(az AMI kodolas igen ritka E1-es vonalaknal). Ha ez a beallitas nem
+	egyezik a vonal ket vegen, akkor elofordulhat hogy a keretszinkron
+	osszejon, de CRC4-hibak es a vonalakon atvitt adatokban is hibak
+	keletkeznek (amit a HDLC/SyncPPP szinten CRC-hibaval jelez)
+
+
+comx0/reg	- a kartya aramkoreinek, a MUNICH (reg) es a FALC (lbireg)
+comx0/lbireg	regisztereinek kozvetlen elerese. Hasznalata:
+
+		echo >reg 0x04 0x0	- a 4-es regiszterbe 0-t ir
+		echo >reg 0x104		- printk()-val kiirja a 4-es regiszter
+					tartalmat a syslogba.
+
+		WARNING: ezek csak a fejleszteshez keszultek, sok galibat
+		lehet veluk okozni!
+
+
+comx0/loopback - A kartya G.703 jelenek a visszahurkolasara is van lehetoseg:
+
+	papaya:# echo none   >/proc/comx/comx0/loopback
+	papaya:# echo local  >/proc/comx/comx0/loopback
+	papaya:# echo remote >/proc/comx/comx0/loopback
+
+	none   - nincs visszahurkolas, normal mukodes
+	local  - a kartya a sajat maga altal adott jelet kapja vissza
+	remote - a kartya a kivulrol vett jelet adja kifele
+
+	Default: none
+
+-----------------------------------------------------------------
+
+Az interfeszhez (Cisco terminologiaban 'channel-group') kapcsolodo beallitasok:
+
+comx0/timeslots	- mely timeslotok (idoszeletek) tartoznak az adott interfeszhez.
+
+	papaya:~# cat /proc/comx/comx0/timeslots
+	1 3 4 5 6
+	papaya:~#
+
+	Egy timeslot megkeresese (hanyas interfeszbe tartozik nalunk):
+
+	papaya:~# grep ' 4' /proc/comx/comx*/timeslots
+	/proc/comx/comx0/timeslots:1 3 4 5 6
+	papaya:~#
+
+	Beallitasa:
+	papaya:~# echo '1 5 2 6 7 8' >/proc/comx/comx0/timeslots
+	
+	A timeslotok sorrendje nem szamit, '1 3 2' ugyanaz mint az '1 2 3'.
+
+	Beallitashoz az adott interfesznek DOWN-ban kell lennie
+	(ifconfig comx0 down), de ugyanannak a kartyanak a tobbi interfesze
+	uzemelhet kozben.
+
+	Beallitaskor leellenorzi, hogy az uj timeslotok nem utkoznek-e egy
+	masik interfesz timeslotjaival. Ha utkoznek, akkor nem allitja at.
+
+	Mindig 10-es szamrendszerben tortenik a timeslotok ertelmezese, nehogy
+	a 08, 09 alaku felirast rosszul ertelmezze.
+
+-----------------------------------------------------------------
+
+Az interfeszek es a kartya allapotanak lekerdezese:
+
+- A ' '-szel kezdodo sorok az eredeti kimenetet, a //-rel kezdodo sorok a
+magyarazatot jelzik.
+
+ papaya:~$ cat /proc/comx/comx1/status
+ Interface administrative status is UP, modem status is UP, protocol is UP
+ Modem status changes: 0, Transmitter status is IDLE, tbusy: 0
+ Interface load (input): 978376 / 947808 / 951024 bits/s (5s/5m/15m)
+               (output): 978376 / 947848 / 951024 bits/s (5s/5m/15m)
+ Debug flags: none
+ RX errors: len: 22, overrun: 1, crc: 0, aborts: 0
+            buffer overrun: 0, pbuffer overrun: 0
+ TX errors: underrun: 0
+ Line keepalive (value: 10) status UP [0]
+
+// Itt kezdodik a hardver-specifikus resz:
+ Controller status:
+         No alarms
+
+// Alarm: hibajelzes:
+//
+// No alarms - minden rendben
+//
+// LOS  - Loss Of Signal - nem erzekel jelet a bemeneten.
+// AIS  - Alarm Indication Signal - csak egymas utani 1-esek jonnek
+//	a bemeneten, a tuloldal igy is jelezheti hogy meghibasodott vagy
+//	nincs inicializalva.
+// AUXP - Auxiliary Pattern Indication - 01010101.. sorozat jon a bemeneten.
+// LFA  - Loss of Frame Alignment - nincs keretszinkron
+// RRA  - Receive Remote Alarm - a tuloldal el, de hibat jelez.
+// LMFA - Loss of CRC4 Multiframe Alignment - nincs CRC4-multikeret-szinkron
+// NMF  - No Multiframe alignment Found after 400 msec - ilyen alarm a no-crc4
+//	es crc4 keretezesek eseten nincs, lasd lentebb
+//
+// Egyeb lehetseges hibajelzesek:
+//
+// Transmit Line Short - a kartya ugy erzi hogy az adasi kimenete rovidre
+//	van zarva, ezert kikapcsolta az adast. (nem feltetlenul veszi eszre
+//	a kulso rovidzarat)
+
+// A veteli oldal csomagjainak lancolt listai, debug celokra:
+
+ Rx ring:
+         rafutott: 0
+         lastcheck: 50845731, jiffies: 51314281
+         base: 017b1858
+         rx_desc_ptr: 0
+         rx_desc_ptr: 017b1858
+         hw_curr_ptr: 017b1858
+         06040000 017b1868 017b1898 c016ff00
+         06040000 017b1878 017b1e9c c016ff00
+         46040000 017b1888 017b24a0 c016ff00
+         06040000 017b1858 017b2aa4 c016ff00
+
+// A kartyat hasznalo tobbi interfesz: a 0-s channel-group a comx1 interfesz,
+// es az 1,2,...,16 timeslotok tartoznak hozza:
+
+ Interfaces using this board: (channel-group, interface, timeslots)
+          0 comx1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+          1 comx2: 17
+          2 comx3: 18
+          3 comx4: 19
+          4 comx5: 20
+          5 comx6: 21
+          6 comx7: 22
+          7 comx8: 23
+          8 comx9: 24
+          9 comx10: 25
+         10 comx11: 26
+         11 comx12: 27
+         12 comx13: 28
+         13 comx14: 29
+         14 comx15: 30
+         15 comx16: 31
+
+// Hany esemenyt kezelt le a driver egy-egy hardver-interrupt kiszolgalasanal:
+
+ Interrupt work histogram:
+ hist[ 0]:        0 hist[ 1]:        2 hist[ 2]:    18574 hist[ 3]:       79
+ hist[ 4]:       14 hist[ 5]:        1 hist[ 6]:        0 hist[ 7]:        1
+ hist[ 8]:        0 hist[ 9]:        7
+
+// Hany kikuldendo csomag volt mar a Tx-ringben amikor ujabb lett irva bele:
+
+ Tx ring histogram:
+ hist[ 0]:     2329 hist[ 1]:        0 hist[ 2]:        0 hist[ 3]:        0
+
+// Az E1-interfesz hiba-szamlaloi, az rfc2495-nek megfeleloen:
+// (kb. a Cisco routerek "show controllers e1" formatumaban: http://www.cisco.com/univercd/cc/td/doc/product/software/ios11/rbook/rinterfc.htm#xtocid25669126)
+
+Data in current interval (91 seconds elapsed):
+   9516 Line Code Violations, 65 Path Code Violations, 2 E-Bit Errors
+   0 Slip Secs, 2 Fr Loss Secs, 2 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 11 Unavail Secs
+Data in Interval 1 (15 minutes):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 4 intervals (1 hour):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 96 intervals (24 hours):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+
+-----------------------------------------------------------------
+
+Nehany kulonlegesebb beallitasi lehetoseg (idovel beepulhetnek majd a driverbe):
+Ezekkel sok galibat lehet okozni, nagyon ovatosan kell oket hasznalni!
+
+	modified CRC-4, for improved interworking of CRC-4 and non-CRC-4
+	devices: (lasd page 107 es g706 Annex B)
+		lbireg[ 0x1b ] |= 0x08
+		lbireg[ 0x1c ] |= 0xc0
+	- ilyenkor ertelmezett az NMF - 'No Multiframe alignment Found after
+	400 msec' alarm.
+
+	FALC - a vonali meghajto IC
+	local loop - a sajat adasomat halljam vissza
+	remote loop - a kivulrol jovo adast adom vissza
+
+	Egy hibakeresesre hasznalhato dolog:
+		- 1-es timeslot local loop a FALC-ban:	echo >lbireg 0x1d 0x21
+		- local loop kikapcsolasa:		echo >lbireg 0x1d 0x00
diff -Nru a/Documentation/networking/slicecom.txt b/Documentation/networking/slicecom.txt
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/networking/slicecom.txt	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,369 @@
+
+SliceCOM adapter user's documentation - for the 0.51 driver version
+
+Written by Bartók István <bartoki@itc.hu>
+
+English translation: Lakatos György <gyuri@itc.hu>
+Mon Dec 11 15:28:42 CET 2000
+
+Last modified: Wed Aug 29 17:25:37 CEST 2001
+
+-----------------------------------------------------------------
+
+Usage:
+
+Compiling the kernel:
+
+Code maturity level options
+	[*] Prompt for development and/or incomplete code/drivers
+
+Network device support
+	Wan interfaces
+		<M> MultiGate (COMX) synchronous
+			<M> Support for MUNICH based boards: SliceCOM, PCICOM (NEW)
+			<M> Support for HDLC and syncPPP...
+
+
+Loading the modules:
+
+modprobe comx
+
+modprobe comx-proto-ppp		# module for  Cisco-HDLC and SyncPPP protocols
+
+modprobe comx-hw-munich		# the module logs information by the kernel
+				# about the detected boards
+
+
+Configuring the board:
+
+# This interface will use the Cisco-HDLC line protocol,
+# the timeslices assigned are 1,2 (128 KiBit line speed)
+# (the first data timeslice in the G.703 frame is no. 1)
+#
+mkdir /proc/comx/comx0.1/
+echo slicecom	>/proc/comx/comx0.1/boardtype
+echo hdlc	>/proc/comx/comx0.1/protocol
+echo 1 2	>/proc/comx/comx0.1/timeslots
+
+
+# This interface uses SyncPPP line protocol, the assigned 
+# is no. 3 (64 KiBit line speed)
+#
+mkdir /proc/comx/comx0.2/
+echo slicecom	>/proc/comx/comx0.2/boardtype
+echo ppp	>/proc/comx/comx0.2/protocol
+echo 3		>/proc/comx/comx0.2/timeslots
+
+...
+
+ifconfig comx0.1 up
+ifconfig comx0.2 up
+
+-----------------------------------------------------------------
+
+The COMX interfaces use a 10 packet transmit queue by default, however WAN
+networks sometimes use bigger values (20 to 100), to utilize the line better
+by large traffic (though the line delay increases because of more packets
+join the queue).
+
+# ifconfig comx0 txqueuelen 50
+
+This option is only supported by the ifconfig command of the later 
+distributions, which came with 2.2 kernels, such as RedHat 6.1 or Debian 2.2.
+
+You can download a newer netbase packet from 
+http://www.debian.org/~rcw/2.2/netbase/ for Debian 2.1, which has a new
+ifconfig. You can get further information about using 2.2 kernel with
+Debian 2.1 from http://www.debian.org/releases/stable/running-kernel-2.2
+
+-----------------------------------------------------------------
+
+The SliceCom LEDs:
+
+red	- on, if the interface is unconfigured, or it gets Remote Alarm-s
+green	- on, if the board finds frame-sync in the received signal 	
+
+A bit more detailed:
+
+red:	green:	meaning:
+
+-	-	no frame-sync, no signal received, or signal SNAFU.
+-	on	"Everything is OK"
+on	on	Recepion is ok, but the remote end sends Remote Alarm
+on	-	The interface is unconfigured
+
+-----------------------------------------------------------------
+
+A more detailed description of the hardware setting options:
+
+The general and the protocol layer options described in the 'comx.txt' file
+apply to the SliceCom as well, I only summarize the SliceCom hardware specific
+settings below.
+
+The '/proc/comx' configuring interface:
+
+An interface directory should be created for every timeslot group with
+'mkdir', e,g: 'comx0', 'comx1' etc. The timeslots can be assigned here to the
+specific interface. The Cisco-like naming convention (serial3:1 - first
+timeslot group of the 3rd. board) can't be used here, because these mean IP
+aliasing in Linux.
+
+You can give any meaningful name to keep the configuration clear; 
+e.g: 'comx0.1', 'comx0.2', 'comx1.1', comx1.2', if you have two boards
+with two interfaces each.
+
+Settings, which apply to the board:
+
+Neither 'io' nor 'irq' settings required, the driver uses the resources
+given by the PCI BIOS.
+
+comx0/boardnum	- board number of the SliceCom in the PC (using the 'natural'
+		PCI order) as listed in '/proc/pci' or the output of the
+	 	'lspci' command, generally the slots nearer to the motherboard
+		PCI driver chips have the lower numbers.
+		
+		Default: 0 (the counting starts with 0)
+
+Though the options below are to be set on a single interface, they apply to the
+whole board. The restriction, to use them on 'UP' interfaces, is because the 
+command sequence below could lead to unpredicable results.
+
+	# echo 0        >boardnum
+	# echo internal >clock_source
+	# echo 1        >boardnum
+
+The sequence would set the clock source of board 0.
+
+These settings will persist after all the interfaces are cleared, but are
+cleared when the driver module is unloaded and loaded again.
+
+comx0/clock_source - source of the transmit clock
+	Usage:
+
+	# echo line     >/proc/comx/comx0/clock_source
+	# echo internal >/proc/comx/comx0/clock_source
+
+	line	- The Tx clock is being decoded if the input data stream,
+		if no clock seen on the input, then the board will use it's
+		own clock generator.
+
+	internal - The Tx clock is supplied by the builtin clock generator. 	
+
+	Default: line
+
+	Normally, the telecommunication company's end device (the HDSL
+	modem) provides the Tx clock, that's why 'line' is the default.
+
+comx0/framing	- Switching CRC4 off/on
+
+	CRC4: 16 PCM frames (The 32 64Kibit channels are multiplexed into a
+	PCM frame, nothing to do with HDLC frames) are divided into 2x8
+	groups, each group has a 4 bit CRC.
+
+	# echo crc4	>/proc/comx/comx0/framing
+	# echo no-crc4	>/proc/comx/comx0/framing
+
+	Default is 'crc4', the Hungarian MATAV lines behave like this. 
+	The traffic generally passes if this setting on both ends don't match.
+
+comx0/linecode	- Setting the line coding
+
+	# echo hdb3	>/proc/comx/comx0/linecode
+	# echo ami	>/proc/comx/comx0/linecode
+
+	Default a 'hdb3', MATAV lines use this.
+	
+	(AMI coding is rarely used with E1 lines). Frame sync may occur, if
+	this setting doesn't match the other end's, but CRC4 and data errors
+	will come, which will result in CRC errors on HDLC/SyncPPP level. 
+
+comx0/reg	- direct access to the board's MUNICH (reg) and FALC (lbireg)
+comx0/lbireg	circuit's registers  
+
+	# echo >reg 0x04 0x0	- write 0 to register 4
+	# echo >reg 0x104	- write the contents of register 4 with
+				printk() to syslog
+
+WARNING! These are only for development purposes, messing with this will
+	result much trouble!
+
+comx0/loopback - Places a loop to the board's G.703 signals
+
+	# echo none   >/proc/comx/comx0/loopback
+	# echo local  >/proc/comx/comx0/loopback
+	# echo remote >/proc/comx/comx0/loopback
+
+	none   - normal operation, no loop
+	local  - the board receives it's own output
+	remote - the board sends the received data to the remote side
+
+	Default: none
+
+-----------------------------------------------------------------
+
+Interface (channel group in Cisco terms) settings: 
+
+comx0/timeslots	- which timeslots belong to the given interface
+
+	Setting:
+
+	# echo '1 5 2 6 7 8' >/proc/comx/comx0/timeslots
+
+	# cat /proc/comx/comx0/timeslots
+	1 2 5 6 7 8 
+	#
+
+	Finding a timeslot: 
+
+	# grep ' 4' /proc/comx/comx*/timeslots
+	/proc/comx/comx0/timeslots:1 3 4 5 6
+	#
+
+	The timeslots can be in any order, '1 2 3' is the same as '1 3 2'.
+
+	The interface has to be DOWN during the setting ('ifconfig comx0
+	down'), but the other interfaces could operate normally.
+
+	The driver checks if the assigned timeslots are vacant, if not, then
+	the setting won't be applied.
+
+	The timeslot values are treated as decimal numbers, not to misunderstand
+	values of 08, 09 form.
+
+-----------------------------------------------------------------
+
+Checking the interface and board status:
+
+- Lines beginning with ' ' (space) belong to the original output, the lines
+which begin with '//' are the comments.
+
+ papaya:~$ cat /proc/comx/comx1/status
+ Interface administrative status is UP, modem status is UP, protocol is UP
+ Modem status changes: 0, Transmitter status is IDLE, tbusy: 0
+ Interface load (input): 978376 / 947808 / 951024 bits/s (5s/5m/15m)
+               (output): 978376 / 947848 / 951024 bits/s (5s/5m/15m)
+ Debug flags: none
+ RX errors: len: 22, overrun: 1, crc: 0, aborts: 0
+            buffer overrun: 0, pbuffer overrun: 0
+ TX errors: underrun: 0
+ Line keepalive (value: 10) status UP [0]
+
+// The hardware specific part starts here:
+ Controller status:
+         No alarms
+
+// Alarm: 
+//
+// No alarms - Everything OK
+//
+// LOS  - Loss Of Signal - No signal sensed on the input
+// AIS  - Alarm Indication Signal - The remot side sends '11111111'-s, 
+//	it tells, that there's an error condition, or it's not
+//	initialised.
+// AUXP - Auxiliary Pattern Indication - 01010101.. received.
+// LFA  - Loss of Frame Alignment - no frame sync received.
+// RRA  - Receive Remote Alarm - the remote end's OK, but singnals error cond.
+// LMFA - Loss of CRC4 Multiframe Alignment - no CRC4 multiframe sync.
+// NMF  - No Multiframe alignment Found after 400 msec - no such alarm using
+//	no-crc4 or crc4 framing, see below.
+//
+// Other possible error messages:
+//
+// Transmit Line Short - the board felt, that it's output is short-circuited,
+// 	so it switched the transmission off. (The board can't definitely tell,
+//	that it's output is short-circuited.)
+
+// Chained list of the received packets, for debug purposes:
+
+ Rx ring:
+         rafutott: 0
+         lastcheck: 50845731, jiffies: 51314281
+         base: 017b1858
+         rx_desc_ptr: 0
+         rx_desc_ptr: 017b1858
+         hw_curr_ptr: 017b1858
+         06040000 017b1868 017b1898 c016ff00
+         06040000 017b1878 017b1e9c c016ff00
+         46040000 017b1888 017b24a0 c016ff00
+         06040000 017b1858 017b2aa4 c016ff00
+
+// All the interfaces using the board: comx1, using the 1,2,...16 timeslots,
+// comx2, using timeslot 17, etc.
+
+ Interfaces using this board: (channel-group, interface, timeslots)
+          0 comx1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+          1 comx2: 17
+          2 comx3: 18
+          3 comx4: 19
+          4 comx5: 20
+          5 comx6: 21
+          6 comx7: 22
+          7 comx8: 23
+          8 comx9: 24
+          9 comx10: 25
+         10 comx11: 26
+         11 comx12: 27
+         12 comx13: 28
+         13 comx14: 29
+         14 comx15: 30
+         15 comx16: 31
+
+// The number of events handled by the driver during an interrupt cycle:
+
+ Interrupt work histogram:
+ hist[ 0]:        0 hist[ 1]:        2 hist[ 2]:    18574 hist[ 3]:       79
+ hist[ 4]:       14 hist[ 5]:        1 hist[ 6]:        0 hist[ 7]:        1
+ hist[ 8]:        0 hist[ 9]:        7
+
+// The number of packets to send in the Tx ring, when a new one arrived:
+
+ Tx ring histogram:
+ hist[ 0]:     2329 hist[ 1]:        0 hist[ 2]:        0 hist[ 3]:        0
+
+// The error counters of the E1 interface, according to the RFC2495,
+// (similar to the Cisco "show controllers e1" command's output:
+// http://www.cisco.com/univercd/cc/td/doc/product/software/ios11/rbook/rinterfc.htm#xtocid25669126)
+
+Data in current interval (91 seconds elapsed):
+   9516 Line Code Violations, 65 Path Code Violations, 2 E-Bit Errors
+   0 Slip Secs, 2 Fr Loss Secs, 2 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 11 Unavail Secs
+Data in Interval 1 (15 minutes):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 4 intervals (1 hour):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+Data in last 96 intervals (24 hours):
+   0 Line Code Violations, 0 Path Code Violations, 0 E-Bit Errors
+   0 Slip Secs, 0 Fr Loss Secs, 0 Line Err Secs, 0 Degraded Mins
+   0 Errored Secs, 0 Bursty Err Secs, 0 Severely Err Secs, 0 Unavail Secs
+
+-----------------------------------------------------------------
+
+Some unique options, (may get into the driver later):
+Treat them very carefully, these can cause much trouble!
+
+	modified CRC-4, for improved interworking of CRC-4 and non-CRC-4
+	devices: (see page 107 and g706 Annex B)
+		lbireg[ 0x1b ] |= 0x08
+		lbireg[ 0x1c ] |= 0xc0
+
+	- The NMF - 'No Multiframe alignment Found after 400 msec' alarm 
+	comes into account.
+
+	FALC - the line driver chip.
+	local loop - I hear my transmission back.
+	remote loop - I echo the remote transmission back.
+
+	Something useful for finding errors:
+	
+		- local loop for timeslot 1 in the FALC chip:
+
+	# echo >lbireg 0x1d 0x21
+
+		- Swithing the loop off:
+
+	# echo >lbireg 0x1d 0x00
diff -Nru a/Documentation/video4linux/API.html b/Documentation/video4linux/API.html
--- a/Documentation/video4linux/API.html	Fri Mar 15 17:51:03 2002
+++ b/Documentation/video4linux/API.html	Fri Mar 15 17:51:03 2002
@@ -105,7 +105,7 @@
 <TR><TD><b>height</b><TD>The height of the image capture.</TD>
 <TR><TD><b>chromakey</b><TD>A host order RGB32 value for the chroma key.</TD>
 <TR><TD><b>flags</b><TD>Additional capture flags.</TD>
-<TR><TD><b>clips</b><TD>A list of clipping rectangles. <em>(Set only)</em)</TD>
+<TR><TD><b>clips</b><TD>A list of clipping rectangles. <em>(Set only)</em></TD>
 <TR><TD><b>clipcount</b><TD>The number of clipping rectangles. <em>(Set only)</em></TD>
 </TABLE>
 <P>
@@ -120,6 +120,7 @@
 </TABLE>
 <P>
 Merely setting the window does not enable capturing. Overlay capturing
+(i.e. PCI-PCI transfer to the frame buffer of the video card)
 is activated by passing the <b>VIDIOCCAPTURE</b> ioctl a value of 1, and
 disabled by passing it a value of 0. 
 <P>
@@ -310,9 +311,10 @@
 </TABLE>
 <P>
 <H3>Reading Images</H3>
-Each call to the <b>read</b> syscall returns the next available image from
-the device. It is up to the caller to set the format and then to pass a 
-suitable size buffer and length to the function. Not all devices will support
+Each call to the <b>read</b> syscall returns the next available image
+from the device. It is up to the caller to set format and size (using
+the VIDIOCSPICT and VIDIOCSWIN ioctls) and then to pass a suitable
+size buffer and length to the function. Not all devices will support
 read operations.
 <P>
 A second way to handle image capture is via the mmap interface if supported.
@@ -329,16 +331,39 @@
 <TR><TD><b>offsets</b><TD>The offset of each frame</TD>
 </TABLE>
 <P>
-Once the mmap has been made the VIDIOCMCAPTURE ioctl sets the image size
-you wish to use (which should match or be below the initial query size).
-Having done so it will begin capturing to the memory mapped buffer. Whenever
-a buffer is "used" by the program it should called VIDIOCSYNC to free this
-frame up and continue. <em>to add:</em>VIDIOCSYNC takes the frame number
-you are freeing as its argument. When the buffer is unmapped or all the
-buffers are full capture ceases. While capturing to memory the driver will
-make a "best effort" attempt to capture to screen as well if requested. This
-normally means all frames that "miss" memory mapped capture will go to the
-display.
+Once the mmap has been made the VIDIOCMCAPTURE ioctl starts the
+capture to a frame using the format and image size specified in the
+video_mmap (which should match or be below the initial query size).
+When the VIDIOCMCAPTURE ioctl returns the frame is <em>not</em>
+captured yet, the driver just instructed the hardware to start the
+capture.  The application has to use the VIDIOCSYNC ioctl to wait
+until the capture of a frame is finished.  VIDIOCSYNC takes the frame
+number you want to wait for as argument.
+<p>
+It is allowed to call VIDIOCMCAPTURE multiple times (with different
+frame numbers in video_mmap->frame of course) and thus have multiple
+outstanding capture requests.  A simple way do to double-buffering
+using this feature looks like this:
+<pre>
+/* setup everything */
+VIDIOCMCAPTURE(0)
+while (whatever) {
+   VIDIOCMCAPTURE(1)
+   VIDIOCSYNC(0)
+   /* process frame 0 while the hardware captures frame 1 */
+   VIDIOCMCAPTURE(0)
+   VIDIOCSYNC(1)
+   /* process frame 1 while the hardware captures frame 0 */
+}
+</pre>
+Note that you are <em>not</em> limited to only two frames.  The API
+allows up to 32 frames, the VIDIOCGMBUF ioctl returns the number of
+frames the driver granted.  Thus it is possible to build deeper queues
+to avoid loosing frames on load peaks.
+<p>
+While capturing to memory the driver will make a "best effort" attempt
+to capture to screen as well if requested. This normally means all
+frames that "miss" memory mapped capture will go to the display.
 <P>
 A final ioctl exists to allow a device to obtain related devices if a
 driver has multiple components (for example video0 may not be associated
diff -Nru a/Documentation/video4linux/bttv/CARDLIST b/Documentation/video4linux/bttv/CARDLIST
--- a/Documentation/video4linux/bttv/CARDLIST	Fri Mar 15 17:51:01 2002
+++ b/Documentation/video4linux/bttv/CARDLIST	Fri Mar 15 17:51:01 2002
@@ -7,13 +7,13 @@
   card=5 - Diamond DTV2000
   card=6 - AVerMedia TVPhone
   card=7 - MATRIX-Vision MV-Delta
-  card=8 - Fly Video II (Bt848)
-  card=9 - TurboTV
+  card=8 - FlyVideo II (Bt848) LR26
+  card=9 - IXMicro TurboTV
   card=10 - Hauppauge (bt878)
   card=11 - MIRO PCTV pro
   card=12 - ADS Technologies Channel Surfer TV
   card=13 - AVerMedia TVCapture 98
-  card=14 - Aimslab VHX
+  card=14 - Aimslab Video Highway Xtreme (VHX)
   card=15 - Zoltrix TV-Max
   card=16 - Pixelview PlayTV (bt878)
   card=17 - Leadtek WinView 601
@@ -21,7 +21,7 @@
   card=19 - LifeView FlyKit w/o Tuner
   card=20 - CEI Raffles Card
   card=21 - Lucky Star Image World ConferenceTV
-  card=22 - Phoebe Tv Master + FM
+  card=22 - Phoebe Tv Master + FM (CPH050)
   card=23 - Modular Technology MM205 PCTV, bt878
   card=24 - [many vendors] CPH05X/06X (bt878)
   card=25 - Terratec/Vobis TV-Boostar
@@ -54,12 +54,12 @@
   card=52 - Pinnacle PCTV Studio Pro
   card=53 - Typhoon TView RDS + FM Stereo / KNC1 TV Station RDS
   card=54 - Lifetec LT 9415 TV (LR90 Rev.F)
-  card=55 - BESTBUY Easy TV
+  card=55 - BESTBUY Easy TV (CPH031)
   card=56 - FlyVideo '98/FM
-  card=57 - GrandTec 'Grand Video Capture'
-  card=58 - Phoebe TV Master Only (No FM)
-  card=59 - TV Capturer
-  card=60 - MM100PCTV
+  card=57 - GrandTec 'Grand Video Capture' (Bt848)
+  card=58 - Phoebe TV Master Only (No FM) CPH060
+  card=59 - TV Capturer (CPH03X)
+  card=60 - Modular Technology MM100PCTV
   card=61 - AG Electronics GMV1
   card=62 - BESTBUY Easy TV (bt878)
   card=63 - ATI TV-Wonder
@@ -72,6 +72,12 @@
   card=70 - PV-BT878P+
   card=71 - Flyvideo 98EZ (capture only)
   card=72 - Prolink PV-BT878P+9B (PlayTV Pro rev.9B FM+NICAM)
+  card=73 - Sensoray 311
+  card=74 - RemoteVision MX (RV605)
+  card=75 - Powercolor MTV878/ MTV878R/ MTV878F
+  card=76 - Canopus WinDVR PCI (COMPAQ Presario 3524JP, 5112JP)
+  card=77 - GrandTec Multi Capture Card (Bt878)
+  card=78 - AOPEN VA1000
 
 tuner.o
   type=0 - Temic PAL (4002 FH5)
@@ -94,7 +100,7 @@
   type=17 - Philips NTSC_M (MK2)
   type=18 - Temic PAL_I (4066 FY5)
   type=19 - Temic PAL* auto (4006 FN5)
-  type=20 - Temic PAL (4009 FR5)
+  type=20 - Temic PAL_BG (4009 FR5) or PAL_I (4069 FR5)
   type=21 - Temic NTSC (4039 FR5)
   type=22 - Temic PAL/SECAM multi (4046 FM5)
   type=23 - Philips PAL_DK
diff -Nru a/Documentation/video4linux/bttv/Cards b/Documentation/video4linux/bttv/Cards
--- a/Documentation/video4linux/bttv/Cards	Fri Mar 15 17:51:02 2002
+++ b/Documentation/video4linux/bttv/Cards	Fri Mar 15 17:51:02 2002
@@ -15,6 +15,10 @@
 All other cards only differ by additional components as tuners, sound decoders,
 EEPROMs, teletext decoders ...
 
+Unsupported Cards: 
+------------------
+Cards with Zoran (ZR) or Philips (SAA) or ISA are not supported by this driver. 
+
 
 MATRIX Vision
 -------------
@@ -137,20 +141,37 @@
       1851:1850 = Flyvideo 98
       1851:1851 = Flyvideo 98 EZ (capture only)
   2) There is a print on the PCB:
-      LR25       = Flyvideo (Zoran)
-      LR37 Rev.C = Capture only (ZR36120 + SAA7110)
+      LR25       = Flyvideo (Zoran ZR36120, SAA7110A)
+      LR26 Rev.N = Flyvideo II (Bt848)
+           Rev.O = Flyvideo II (Bt878)
+      LR37 Rev.C = Flyvideo EZ (Capture only, ZR36120 + SAA7110)
+      LR38 Rev.A1= Flyvideo II EZ (Bt848 capture only)
       LR50 Rev.Q = Flyvideo 98 (w/eeprom and PCI subsystem ID)
-      LR50 Rev.W = Flyvideo 98 (no eeprom)
+           Rev.W = Flyvideo 98 (no eeprom)
       LR51 Rev.E = Flyvideo 98 EZ (capture only)
       LR90       = Flyvideo 2000 series
-      LR90 Rev.F = Lifetec/Medion LT 9815
+      LR91       = Stereo daughter card for LR90
       LR97       = Flyvideo DVBS
+      LR138 Rev.C= Flyvideo 2000 (SAA7130)
+	        or Flyvideo 3000 (SAA7134) w/Stereo TV
+		   These exist in variations w/FM and w/Remote sometimes denoted
+		   by suffixes "FM" and "R".
+
+      Lifeview.com.tw states (Feb. 2002):
+      "The FlyVideo2000 and FlyVideo2000s product name have renamed to FlyVideo98."
+      Their Bt8x8 cards are listed as discontinued.
+      Flyvideo 2000S was probably sold as Flyvideo 3000 in some contries(Europe?).
+      The new Flyvideo 2000/3000 are SAA7130/SAA7134 based. 
+      Flyvideo 2100/3100 are half-sized cards (for system integrators etc.)
 
   "Flyvideo II" had been the name for the 848 cards, nowadays (in Germany)
   this name is re-used for LR50 Rev.W.
-  The Lifeview website has even more names: Flyvideo III,2100,3000,3100.
+  The Lifeview website mentioned Flyvideo III at some time, but such a card
+  has never been seen. 
   These cards are sold by many OEMs too.
 
+  FlyVideo A2 = LR90 Rev.F (w/Remote, w/o FM, stereo TV by tda9821)
+
 
 Typhoon TV card series:
 -----------------------
@@ -176,6 +197,7 @@
 
 Guillemot
 ---------
+  Maxi-TV PCI (ZR36120)
   Maxi TV Video 2 = LR50 Rev.Q (FI1216MF, PAL BG+SECAM)
   Maxi TV Video 3 = CPH064 (PAL BG + SECAM)
 
@@ -208,3 +230,163 @@
 Genius/Kye
 ----------
    Video Wonder/Genius Internet Video Kit = LR37 Rev.C
+   Video Wonder Pro II (848 or 878) = LR26
+
+Tekram
+------
+   VideoCap C205 (Bt848)
+   VideoCap C210 (Zoran ZR36120 +Philips)
+   CaptureTV M200 (ISA)
+   CaptureTV M205 (Bt848)
+
+Lucky Star
+----------
+   Image World Conference TV = LR50 Rev. Q
+
+Leadtek
+-------
+   WinView 601 (Bt848)
+   WinView 610 (Zoran)
+   WinFast2000
+
+KNC One
+-------
+   TV-Station
+   TV-Station SE (+Software Bundle)
+   TV-Station pro (+TV stereo)
+   TV-Station FM (+Radio)
+   TV-Station RDS (+RDS)
+
+PV951 cards:
+------------
+  These are sold as:
+   Boeder TV-FM Video Capture Card
+   Titanmedia Supervision TV-2400
+   Provideo PV951 TF
+   3DeMon PV951
+   MediaForte TV-Vision PV951
+   Yoko PV951
+
+Highscreen
+----------
+   TV Karte = LR50 Rev.S
+   TV-Boostar = Terratec Terra TV+ Version 1.0 (Bt848, TDA9821) "ceb105.pcb"
+
+Zoltrix
+-------
+   Face To Face TV MAX (Bt848) (PCB "VP-8482 Rev1.3")
+   Genie TV (Bt878) (PCB "VP-8790 Rev 2.1")
+
+AVerMedia
+---------
+   AVer FunTV Lite (ISA, AV3001 chipset)  "M101.C"
+   AVerTV
+   AVerTV Stereo
+   AVerTV Studio (w/FM)
+   AVerMedia TV98 with Remote 
+   AVerMedia TV/FM98 Stereo
+   AVerMedia TVCAM98
+   TVCapture (Bt848)
+   TVPhone (Bt848)
+   TVCapture98 (="AVerMedia TV98" in USA) (Bt878)
+   TVPhone98 (Bt878, w/FM)
+
+   PCB      PCI-ID      Model-Name      Eeprom  Tuner  Sound    Country
+   --------------------------------------------------------------------
+   M1A8-A      --       AVer TV-Phone           FM1216  --
+   M168-T   1461:0003   AVerTV Studio   48:17   FM1216 TDA9840T  D    (1) w/FM w/Remote
+   M168-U   1461:0004   TVCapture98     40:11   FI1216   --      D    w/Remote
+   M168II-B 1461:0003   Medion MD9592   48:16   FM1216 TDA9873H  D    w/FM
+
+   (1) Daughterboard MB68-A with TDA9820T and TDA9840T
+
+Aimslab
+-------
+   Video Highway Xtreme (aka "VHX") (Bt848, FM w/ TEA5757)
+
+IXMicro
+-------
+   IXTV BT848
+   IXTV BT878
+   TurboTV (Bt848)
+
+Lifetec/Medion/Tevion/Aldi
+-------
+   LT9415/MD9415 = LR90 Rev. F
+          MD9592 = Avermedia TVphone98 (PCI_ID=1461:0003), PCB-Rev=M168II-B (w/TDA9873H)
+
+Modular Technologies (www.modulartech.com) UK
+--------------------
+   MM100 PCTV (Bt848)
+   MM205 PCTV (Bt878)
+   MM210 PCTV (Bt878) (Galaxy TV)
+
+Terratec
+--------
+   Terra TV+ Version 1.0 (Bt848), "ceb105.PCB" printed on the PCB, TDA9821
+   Terra TV+ Version 1.1 (Bt878), "LR74 Rev.E" printed on the PCB, TDA9821
+   Terra TValueRadio,             "LR102 Rev.C" printed on the PCB
+   Terra TV/Radio+ Version 1.0,   "80-CP2830100-0" TTTV3 printed on the PCB, i
+				     "CPH010-E83" on the back, SAA6588T, TDA9873H
+   Terra TValue Version BT878,    "80-CP2830110-0 TTTV4" printed on the PCB, 
+				     "CPH011-D83" on back
+   Terra TValue Version 1.0       "ceb105.PCB" (really identical to Terra TV+ Version 1.0)
+
+   LR74 is a newer PCB revision of ceb105 (both incl. connector for Active Radio Upgrade)
+
+
+Technisat
+---------
+   Mediafocus I (ZR36120/ZR36125)
+   Mediafocus II (SAA7146)
+
+Siemens
+-------
+   Multimedia eXtension Board (MXB) (SAA7146, SAA7111)
+
+Stradis
+-------
+   SDM275,SDM250,SDM026,SDM025 (SAA7146, IBMMPEG2): MPEG2 decoder only
+
+Powercolor
+----------
+   MTV878
+   MTV878R w/Remote Control
+   MTV878F w/Remote Control w/FM radio
+
+Pinnacle
+--------
+   Mirovideo PCTV (Bt848)
+   Mirovideo PCTV SE (Bt848)
+   Mirovideo PCTV Pro (Bt848 + Daughterboard)
+   Studio PCTV Rave (Bt878 w/o infrared)
+   Studio PCTV
+   Studio PCTV Pro (Bt878 stereo w/ FM)
+
+   DC1+ (ISA)
+   DC10  (zr36057 + zr36060 + saa7110 + adv7176)
+   DC10+ (zr36067 + zr36060 + saa7110 + adv7176)
+   DC20
+   DC30
+   DC30+ (zr36067 + zr36050 + zr36016 + vpx3220 + adv7176)
+
+Lenco
+-----
+   MXR-9565 (=Technisat Mediafocus?)
+   MXR-9571 (Bt848)
+   MXR-9575
+   MXR-9477 (Bt878)
+   MXTV-9578CP (= Prolink PV-BT878P+4E)
+
+Iomega
+------
+   Buz (Zoran zr36067 + zr36060 + SAA7111 + SAA7185)
+
+LML
+---
+   LML33 (zr36067 + zr36060 + bt819+ bt856)
+
+Grandtec
+--------
+   Grand Video Capture (Bt848)
+   Multi Capture Card  (Bt878)
diff -Nru a/Documentation/video4linux/bttv/Insmod-options b/Documentation/video4linux/bttv/Insmod-options
--- a/Documentation/video4linux/bttv/Insmod-options	Fri Mar 15 17:51:01 2002
+++ b/Documentation/video4linux/bttv/Insmod-options	Fri Mar 15 17:51:01 2002
@@ -28,7 +28,7 @@
 				default is 0 (off).
 		irq_debug=0/1	irq handler debug messages.
 				default is 0 (off).
-		gbuffers=2-64	number of capture buffers for mmap'ed capture.
+		gbuffers=2-32	number of capture buffers for mmap'ed capture.
 				default is 2.
 		gbufsize=	size of capture buffers. default and
 				maximum value is 0x208000 (~2MB)
@@ -38,6 +38,13 @@
 				push used by bttv.  bttv will disable overlay
 				by default on this hardware to avoid crashes.
 				With this insmod option you can override this.
+		automute=0/1	Automatically mutes the sound if there is
+				no TV signal, on by default.  You might try
+				to disable this if you have bad input signal
+				quality which leading to unwanted sound
+				dropouts.
+		chroma_agc=0/1	AGC of chroma signal, off by default.
+		adc_crush=0/1	Luminance ADC crush, on by default.
 
 		bttv_gpio=0/1
 		gpiomask=
@@ -89,6 +96,8 @@
 	insmod args for tda9874a:
 		tda9874a_SIF=1/2	select sound IF input pin (1 or 2)
 					(default is pin 1)
+		tda9874a_AMSEL=0/1	auto-mute select for NICAM (default=0)
+					Please read note 3 below!
 		tda9874a_STD=n		select TV sound standard (0..8):
 					0 - A2, B/G
 					1 - A2, M (Korea)
@@ -100,11 +109,20 @@
 					7 - NICAM, D/K (default)
 					8 - NICAM, L
 
-	Note: tda9874a is very similar to tda9874 (without 'A'-suffix), but
-	this driver will not work for the latter device (will not load).
-	Note: tda9874a and tda9875 (which is supported separately by
+	Note 1: tda9874a supports both tda9874h (old) and tda9874a (new) chips.
+	Note 2: tda9874h/a and tda9875 (which is supported separately by
 	tda9875.o) use the same i2c address so both modules should not be
 	used at the same time.
+	Note 3: Using tda9874a_AMSEL option depends on your TV card design!
+		AMSEL=0: auto-mute will switch between NICAM sound
+			 and the sound on 1st carrier (i.e. FM mono or AM).
+		AMSEL=1: auto-mute will switch between NICAM sound
+			 and the analog mono input (MONOIN pin).
+	If tda9874a decoder on your card has MONOIN pin not connected, then
+	use only tda9874_AMSEL=0 or don't specify this option at all.
+	For example:
+	  card=65 (FlyVideo 2000S) - set AMSEL=1 or AMSEL=0
+	  card=72 (Prolink PV-BT878P rev.9B) - set AMSEL=0 only
 
 msp3400.o
 	The driver for the msp34xx sound processor chips. If you have a
diff -Nru a/Documentation/video4linux/bttv/README.freeze b/Documentation/video4linux/bttv/README.freeze
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/Documentation/video4linux/bttv/README.freeze	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,69 @@
+
+If the box freezes hard with bttv ...
+=====================================
+
+It might be a bttv driver bug.  It also might be bad hardware.  It also
+might be something else ...
+
+Just mailing me "bttv freezes" isn't going to help much.  This README
+has a few hints how you can help to pin down the problem.
+
+
+bttv bugs
+---------
+
+If some version works and another doesn't it is likely to be a driver
+bug.  It is very helpful if you can tell where exactly it broke
+(i.e. the last working and the first broken version).
+
+With a hard freeze you probably doesn't find anything in the logfiles.
+The only way to capture any kernel messages is to hook up a serial
+console and let some terminal application log the messages.  /me uses
+screen.  See Documentation/serial-console.txt for details on setting
+up a serial console.
+
+Read Documentation/oops-tracing.txt to learn how to get any useful
+information out of a register+stack dump printed by the kernel on
+protection faults (so-called "kernel oops").
+
+If you run into some kind of deadlock, you can try to dump a call trace
+for each process using sysrq-t (see Documentation/sysrq.txt).  ksymoops
+will translate these dumps into kernel symbols too.  This way it is
+possible to figure where *exactly* some process in "D" state is stuck.
+
+I've seen reports that bttv 0.7.x crashes whereas 0.8.x works rock solid
+for some people.  Thus probably a small buglet left somewhere in bttv
+0.7.x.  I have no idea where exactly, it works stable for me and alot of
+other people.  But in case you have problems with the 0.7.x versions you
+can give 0.8.x a try ...
+
+
+hardware bugs
+-------------
+
+Some hardware can't deal with PCI-PCI transfers (i.e. grabber => vga).
+Sometimes problems show up with bttv just because of the high load on
+the PCI bus. The bt848/878 chips have a few workarounds for known
+incompatibilities, see README.quirks.
+
+Some folks report that increasing the pci latency helps too,
+althrought I'm not sure whenever this really fixes the problems or
+only makes it less likely to happen.
+
+Some mainboard have problems to deal correctly with multiple devices
+doing DMA at the same time.  bttv + ide seems to cause this sometimes,
+if this is the case you likely see freezes only with video and hard disk
+access at the same time.  Updating the IDE driver to get the latest and
+greatest workarounds for hardware bugs might fix these problems.
+
+
+other
+-----
+
+IRQ sharing is known to cause problems in some cases.  It works just
+fine in theory and many configurations.  Neverless it might be worth a
+try to shuffle around the PCI cards to give bttv another IRQ or make
+it share the IRQ with some other piece of hardware.  IRQ sharing with
+VGA cards seems to cause trouble sometimes.  I've also seen funny
+effects with bttv sharing the IRQ with the ACPI bridge (and
+apci-enabled kernel).
diff -Nru a/Documentation/video4linux/bttv/Sound-FAQ b/Documentation/video4linux/bttv/Sound-FAQ
--- a/Documentation/video4linux/bttv/Sound-FAQ	Fri Mar 15 17:51:03 2002
+++ b/Documentation/video4linux/bttv/Sound-FAQ	Fri Mar 15 17:51:03 2002
@@ -62,7 +62,7 @@
 {
 	[ ... ]
         u32 gpiomask;
-        u32 audiomux[5];  /* audio mux: tuner, radio, external, internal, mute */
+        u32 audiomux[6]; /* Tuner, Radio, external, internal, mute, stereo */
 };
 
 gpiomask specifies which pins are used to control the audio mux chip.
@@ -127,6 +127,9 @@
 *_modulename    - hint whenever some card needs this or that audio
                   module loaded to work properly.
 has_radio	- whenever this TV card has a radio tuner.
+no_msp34xx	- "1" disables loading of msp3400.o module
+no_tda9875	- "1" disables loading of tda9875.o module 
+needs_tvaudio	- set to "1" to load tvaudio.o module 
 
 If some config item is specified both from the tvcards array and as
 insmod option, the insmod option takes precedence.
diff -Nru a/MAINTAINERS b/MAINTAINERS
--- a/MAINTAINERS	Fri Mar 15 17:51:01 2002
+++ b/MAINTAINERS	Fri Mar 15 17:51:01 2002
@@ -709,14 +709,12 @@
 S:	Supported 
 
 IDE DRIVER [GENERAL]
-P:	Andre Hedrick
-M:	andre@linux-ide.org
-M:	andre@linuxdiskcert.org
-L:	linux-kernel@vger.kernel.org
-W:	http://www.kernel.org/pub/linux/kernel/people/hedrick/
-W:	http://www.linux-ide.org/
-W:	http://www.linuxdiskcert.org/
-S:	Maintained
+P:	Martin Dalecki
+M:	martin@dalecki.de
+I:	pl_PL.ISO8859-2, de_DE.ISO8859-15, (en_US.ISO8859-1)
+L:	linux-kernel@vger.kernel.org
+W:	http://www.dalecki.de
+S:	Developement
 
 IDE/ATAPI CDROM DRIVER
 P:	Jens Axboe
@@ -1659,7 +1657,7 @@
 
 USB PEGASUS DRIVER
 P:	Petko Manolov
-M:	petkan@dce.bg
+M:	petkan@users.sourceforge.net
 L:	linux-usb-users@lists.sourceforge.net
 L:	linux-usb-devel@lists.sourceforge.net
 S:	Maintained
diff -Nru a/Makefile b/Makefile
--- a/Makefile	Fri Mar 15 17:51:01 2002
+++ b/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 5
-SUBLEVEL = 6
-EXTRAVERSION =
+SUBLEVEL = 7
+EXTRAVERSION =-pre2
 
 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
 
@@ -246,14 +246,14 @@
 
 include arch/$(ARCH)/Makefile
 
-export	CPPFLAGS CFLAGS AFLAGS
+export	CPPFLAGS CFLAGS CFLAGS_KERNEL AFLAGS AFLAGS_KERNEL
 
 export	NETWORKS DRIVERS LIBS HEAD LDFLAGS LINKFLAGS MAKEBOOT ASFLAGS
 
 .S.s:
-	$(CPP) $(AFLAGS) -traditional -o $*.s $<
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -traditional -o $*.s $<
 .S.o:
-	$(CC) $(AFLAGS) -traditional -c -o $*.o $<
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -traditional -c -o $*.o $<
 
 Version: dummy
 	@rm -f include/linux/compile.h
diff -Nru a/Rules.make b/Rules.make
--- a/Rules.make	Fri Mar 15 17:51:02 2002
+++ b/Rules.make	Fri Mar 15 17:51:02 2002
@@ -120,6 +120,24 @@
 	) > $(dir $@)/.$(notdir $@).flags
 endif
 
+#
+# Rule to link composite objects
+#
+
+# for make >= 3.78 the following is cleaner:
+# multi-used := $(foreach m,$(obj-y) $(obj-m), $(if $($(basename $(m))-objs), $(m)))
+multi-used := $(sort $(foreach m,$(obj-y) $(obj-m),$(patsubst %,$(m),$($(basename $(m))-objs))))
+ld-multi-used := $(filter-out $(list-multi),$(multi-used))
+ld-multi-objs := $(foreach m, $(ld-multi-used), $($(basename $(m))-objs))
+
+$(ld-multi-used) : %.o: $(ld-multi-objs)
+	rm -f $@
+	$(LD) $(EXTRA_LDFLAGS) -r -o $@ $(filter $($(basename $@)-objs), $^)
+	@ ( \
+	    echo 'ifeq ($(strip $(subst $(comma),:,$(LD) $(EXTRA_LDFLAGS) $($(basename $@)-objs)),$$(strip $$(subst $$(comma),:,$$(LD) $$(EXTRA_LDFLAGS) $$($(basename $@)-objs)))))' ; \
+	    echo 'FILES_FLAGS_UP_TO_DATE += $@' ; \
+	    echo 'endif' \
+	) > $(dir $@)/.$(notdir $@).flags
 
 #
 # This make dependencies quickly
@@ -200,8 +218,7 @@
 #
 ifdef CONFIG_MODULES
 
-multi-used	:= $(filter $(list-multi), $(obj-y) $(obj-m))
-multi-objs	:= $(foreach m, $(multi-used), $($(basename $(m))-objs))
+multi-objs	:= $(foreach m, $(obj-y) $(obj-m), $($(basename $(m))-objs))
 active-objs	:= $(sort $(multi-objs) $(obj-y) $(obj-m))
 
 ifdef CONFIG_MODVERSIONS
diff -Nru a/arch/alpha/defconfig b/arch/alpha/defconfig
--- a/arch/alpha/defconfig	Fri Mar 15 17:51:03 2002
+++ b/arch/alpha/defconfig	Fri Mar 15 17:51:03 2002
@@ -253,9 +253,7 @@
 # CONFIG_IDEDMA_ONLYDISK is not set
 CONFIG_BLK_DEV_IDEDMA=y
 # CONFIG_IDEDMA_PCI_WIP is not set
-# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
 # CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_AEC62XX_TUNING is not set
 CONFIG_BLK_DEV_ALI15X3=y
diff -Nru a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
--- a/arch/alpha/kernel/smp.c	Fri Mar 15 17:51:02 2002
+++ b/arch/alpha/kernel/smp.c	Fri Mar 15 17:51:02 2002
@@ -460,7 +460,7 @@
 	if (fork_by_hand() < 0)
 		panic("failed fork for CPU %d", cpuid);
 
-	idle = init_task.prev_task;
+	idle = prev_task(&init_task);
 	if (!idle)
 		panic("No idle process for CPU %d", cpuid);
 
diff -Nru a/arch/arm/def-configs/badge4 b/arch/arm/def-configs/badge4
--- a/arch/arm/def-configs/badge4	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/def-configs/badge4	Fri Mar 15 17:51:03 2002
@@ -15,7 +15,14 @@
 # Code maturity level options
 #
 CONFIG_EXPERIMENTAL=y
-# CONFIG_OBSOLETE is not set
+
+#
+# General setup
+#
+CONFIG_NET=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
 
 #
 # Loadable module support
@@ -27,6 +34,7 @@
 #
 # System Type
 #
+# CONFIG_ARCH_ADIFCC is not set
 # CONFIG_ARCH_ANAKIN is not set
 # CONFIG_ARCH_ARCA5K is not set
 # CONFIG_ARCH_CLPS7500 is not set
@@ -36,6 +44,7 @@
 # CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_IOP310 is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
@@ -48,15 +57,23 @@
 #
 # Archimedes/A5000 Implementations (select only ONE)
 #
+# CONFIG_ARCH_ARC is not set
+# CONFIG_ARCH_A5K is not set
 
 #
 # Footbridge Implementations
 #
+# CONFIG_ARCH_CATS is not set
+# CONFIG_ARCH_PERSONAL_SERVER is not set
+# CONFIG_ARCH_EBSA285_ADDIN is not set
+# CONFIG_ARCH_EBSA285_HOST is not set
+# CONFIG_ARCH_NETWINDER is not set
 
 #
 # SA11x0 Implementations
 #
 # CONFIG_SA1100_ASSABET is not set
+# CONFIG_ASSABET_NEPONSET is not set
 # CONFIG_SA1100_ADSBITSY is not set
 # CONFIG_SA1100_BRUTUS is not set
 # CONFIG_SA1100_CERF is not set
@@ -78,6 +95,7 @@
 # CONFIG_SA1100_OMNIMETER is not set
 # CONFIG_SA1100_PANGOLIN is not set
 # CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_PT_SYSTEM3 is not set
 # CONFIG_SA1100_SHANNON is not set
 # CONFIG_SA1100_SHERMAN is not set
 # CONFIG_SA1100_SIMPAD is not set
@@ -85,15 +103,23 @@
 # CONFIG_SA1100_VICTOR is not set
 # CONFIG_SA1100_XP860 is not set
 # CONFIG_SA1100_YOPY is not set
+# CONFIG_SA1100_STORK is not set
 CONFIG_SA1111=y
 CONFIG_FORCE_MAX_ZONEORDER=9
-CONFIG_SA1100_USB=m
-CONFIG_SA1100_USB_NETLINK=m
-CONFIG_SA1100_USB_CHAR=m
+# CONFIG_SA1100_USB is not set
+# CONFIG_SA1100_USB_NETLINK is not set
+# CONFIG_SA1100_USB_CHAR is not set
+# CONFIG_H3600_SLEEVE is not set
 
 #
 # CLPS711X/EP721X Implementations
 #
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
+# CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_FORTUNET is not set
 # CONFIG_ARCH_EP7211 is not set
 # CONFIG_ARCH_EP7212 is not set
 # CONFIG_ARCH_ACORN is not set
@@ -117,6 +143,7 @@
 # CONFIG_CPU_ARM1020 is not set
 # CONFIG_CPU_SA110 is not set
 CONFIG_CPU_SA1100=y
+# CONFIG_XSCALE_PMU is not set
 # CONFIG_ARM_THUMB is not set
 CONFIG_DISCONTIGMEM=y
 
@@ -126,6 +153,7 @@
 # CONFIG_PCI is not set
 CONFIG_ISA=y
 # CONFIG_ISA_DMA is not set
+# CONFIG_FIQ is not set
 CONFIG_CPU_FREQ=y
 CONFIG_HOTPLUG=y
 
@@ -134,13 +162,11 @@
 #
 CONFIG_PCMCIA=y
 CONFIG_PCMCIA_PROBE=y
+# CONFIG_I82092 is not set
 # CONFIG_I82365 is not set
 # CONFIG_TCIC is not set
+# CONFIG_PCMCIA_CLPS6700 is not set
 CONFIG_PCMCIA_SA1100=y
-CONFIG_NET=y
-# CONFIG_SYSVIPC is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
 
 #
 # At least one math emulation must be selected
@@ -153,6 +179,8 @@
 CONFIG_BINFMT_ELF=y
 CONFIG_BINFMT_MISC=m
 # CONFIG_PM is not set
+# CONFIG_PREEMPT is not set
+# CONFIG_APM is not set
 CONFIG_ARTHUR=m
 CONFIG_CMDLINE="init=/linuxrc root=/dev/mtdblock3"
 # CONFIG_LEDS is not set
@@ -161,14 +189,23 @@
 #
 # Parallel port support
 #
-# CONFIG_PARPORT is not set
+CONFIG_PARPORT=m
+# CONFIG_PARPORT_PC is not set
+# CONFIG_PARPORT_ARC is not set
+# CONFIG_PARPORT_AMIGA is not set
+# CONFIG_PARPORT_MFC3 is not set
+# CONFIG_PARPORT_ATARI is not set
+# CONFIG_PARPORT_GSC is not set
+# CONFIG_PARPORT_SUNBPP is not set
+# CONFIG_PARPORT_OTHER is not set
+# CONFIG_PARPORT_1284 is not set
 
 #
 # Memory Technology Devices (MTD)
 #
 CONFIG_MTD=y
 CONFIG_MTD_DEBUG=y
-CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_DEBUG_VERBOSE=0
 CONFIG_MTD_PARTITIONS=y
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_BOOTLDR_PARTS is not set
@@ -205,6 +242,9 @@
 # CONFIG_MTD_ROM is not set
 # CONFIG_MTD_ABSENT is not set
 # CONFIG_MTD_OBSOLETE_CHIPS is not set
+# CONFIG_MTD_AMDSTD is not set
+# CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
 
 #
 # Mapping drivers for chip access
@@ -212,17 +252,21 @@
 # CONFIG_MTD_PHYSMAP is not set
 # CONFIG_MTD_NORA is not set
 # CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
 CONFIG_MTD_SA1100=y
+# CONFIG_MTD_2PARTS_IPAQ is not set
+# CONFIG_MTD_DC21285 is not set
 # CONFIG_MTD_IQ80310 is not set
+# CONFIG_MTD_EPXA10DB is not set
+# CONFIG_MTD_PCI is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_PMC551 is not set
 # CONFIG_MTD_SLRAM is not set
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTDRAM_TOTAL_SIZE=4096
-CONFIG_MTDRAM_ERASE_SIZE=128
-CONFIG_MTD_BLKMTD=m
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
 
 #
 # Disk-On-Chip Device Drivers
@@ -241,22 +285,35 @@
 # Plug and Play configuration
 #
 # CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
 
 #
 # Block devices
 #
 # CONFIG_BLK_DEV_FD is not set
 # CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
+# CONFIG_BLK_DEV_DAC960 is not set
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_NBD=m
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_RAM is not set
 # CONFIG_BLK_DEV_INITRD is not set
 
 #
 # Multi-device support (RAID and LVM)
 #
 # CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
 
 #
 # Networking options
@@ -325,9 +382,16 @@
 #
 # Ethernet (1000 Mbit)
 #
-# CONFIG_ACENIC_OMIT_TIGON_I is not set
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
 
@@ -336,15 +400,23 @@
 #
 CONFIG_NET_RADIO=y
 # CONFIG_STRIP is not set
-# CONFIG_WAVELAN is not set
 # CONFIG_ARLAN is not set
 # CONFIG_AIRONET4500 is not set
+# CONFIG_AIRONET4500_NONCS is not set
+# CONFIG_AIRONET4500_PROC is not set
+
+#
+# Wireless ISA/PCI cards support
+#
+# CONFIG_WAVELAN is not set
 # CONFIG_AIRO is not set
 CONFIG_HERMES=y
 
 #
-# Wireless Pcmcia cards support
+# Wireless Pcmcia/Cardbus cards support
 #
+CONFIG_PCMCIA_NETWAVE=m
+CONFIG_PCMCIA_WAVELAN=m
 CONFIG_PCMCIA_HERMES=y
 CONFIG_AIRO_CS=m
 CONFIG_NET_WIRELESS=y
@@ -354,6 +426,7 @@
 #
 # CONFIG_TR is not set
 # CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
 # CONFIG_SHAPER is not set
 
 #
@@ -369,14 +442,15 @@
 CONFIG_PCMCIA_3C574=m
 CONFIG_PCMCIA_FMVJ18X=m
 CONFIG_PCMCIA_PCNET=y
-CONFIG_PCMCIA_AXNET=m
 CONFIG_PCMCIA_NMCLAN=m
 CONFIG_PCMCIA_SMC91C92=m
 CONFIG_PCMCIA_XIRC2PS=m
+CONFIG_PCMCIA_AXNET=m
+# CONFIG_ARCNET_COM20020_CS is not set
+# CONFIG_PCMCIA_IBMTR is not set
 CONFIG_NET_PCMCIA_RADIO=y
 CONFIG_PCMCIA_RAYCS=m
-CONFIG_PCMCIA_NETWAVE=m
-CONFIG_PCMCIA_WAVELAN=m
+# CONFIG_AIRONET4500_CS is not set
 
 #
 # Amateur Radio support
@@ -392,9 +466,16 @@
 # IrDA protocols
 #
 CONFIG_IRLAN=y
+# CONFIG_IRNET is not set
 CONFIG_IRCOMM=y
 CONFIG_IRDA_ULTRA=y
-# CONFIG_IRDA_OPTIONS is not set
+
+#
+# IrDA options
+#
+# CONFIG_IRDA_CACHE_LAST_LSAP is not set
+# CONFIG_IRDA_FAST_RR is not set
+# CONFIG_IRDA_DEBUG is not set
 
 #
 # Infrared-port device drivers
@@ -440,23 +521,36 @@
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_BLK_DEV_IDEDISK=m
 # CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_IDEDISK_STROKE is not set
 # CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
 # CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
 # CONFIG_BLK_DEV_IDECS is not set
 CONFIG_BLK_DEV_IDECD=m
-CONFIG_BLK_DEV_IDETAPE=m
+# CONFIG_BLK_DEV_IDETAPE is not set
 CONFIG_BLK_DEV_IDEFLOPPY=m
 CONFIG_BLK_DEV_IDESCSI=m
+# CONFIG_IDE_TASK_IOCTL is not set
 
 #
 # IDE chipset support/bugfixes
 #
 # CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
 # CONFIG_IDE_CHIPSETS is not set
 # CONFIG_IDEDMA_AUTO is not set
 # CONFIG_DMA_NONPCI is not set
 # CONFIG_BLK_DEV_IDE_MODES is not set
 # CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
 
 #
 # SCSI support
@@ -469,7 +563,7 @@
 CONFIG_BLK_DEV_SD=y
 CONFIG_SD_EXTRA_DEVS=40
 CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
+# CONFIG_CHR_DEV_OSST is not set
 CONFIG_BLK_DEV_SR=m
 # CONFIG_BLK_DEV_SR_VENDOR is not set
 CONFIG_SR_EXTRA_DEVS=2
@@ -478,7 +572,6 @@
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-# CONFIG_SCSI_DEBUG_QUEUES is not set
 # CONFIG_SCSI_MULTI_LUN is not set
 # CONFIG_SCSI_CONSTANTS is not set
 # CONFIG_SCSI_LOGGING is not set
@@ -496,8 +589,10 @@
 # CONFIG_SCSI_DPT_I2O is not set
 # CONFIG_SCSI_ADVANSYS is not set
 # CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
 # CONFIG_SCSI_MEGARAID is not set
 # CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
 # CONFIG_SCSI_DTC3280 is not set
 # CONFIG_SCSI_EATA is not set
 # CONFIG_SCSI_EATA_DMA is not set
@@ -505,10 +600,12 @@
 # CONFIG_SCSI_FUTURE_DOMAIN is not set
 # CONFIG_SCSI_GDTH is not set
 # CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
 # CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_NCR53C7xx_sync is not set
-# CONFIG_SCSI_NCR53C7xx_FAST is not set
-# CONFIG_SCSI_NCR53C7xx_DISCONNECT is not set
+# CONFIG_SCSI_NCR53C7xx is not set
 # CONFIG_SCSI_PAS16 is not set
 # CONFIG_SCSI_PCI2000 is not set
 # CONFIG_SCSI_PCI2220I is not set
@@ -528,11 +625,11 @@
 #
 # I2O device support
 #
-CONFIG_I2O=m
-CONFIG_I2O_BLOCK=m
-CONFIG_I2O_LAN=m
-CONFIG_I2O_SCSI=m
-CONFIG_I2O_PROC=m
+# CONFIG_I2O is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
 
 #
 # ISDN subsystem
@@ -540,40 +637,75 @@
 # CONFIG_ISDN is not set
 
 #
-# Input core support
+# Input device support
 #
-CONFIG_INPUT=m
-CONFIG_INPUT_KEYBDEV=m
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
 # CONFIG_INPUT_MOUSEDEV is not set
 # CONFIG_INPUT_JOYDEV is not set
 # CONFIG_INPUT_EVDEV is not set
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_GAMEPORT_NS558 is not set
+# CONFIG_GAMEPORT_L4 is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_GAMEPORT_PCIGAME is not set
+# CONFIG_GAMEPORT_FM801 is not set
+# CONFIG_GAMEPORT_CS461x is not set
+# CONFIG_SERIO is not set
+# CONFIG_SERIO_SERPORT is not set
 
 #
 # Character devices
 #
 # CONFIG_VT is not set
 # CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 
 #
 # Serial drivers
 #
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
 CONFIG_SERIAL_SA1100=y
 CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SA1100_DEFAULT_BAUDRATE=115200
 # CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_ATOMWIDE_SERIAL is not set
+# CONFIG_DUALSP_SERIAL is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_RSA is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_PRINTER is not set
+# CONFIG_PPDEV is not set
 
 #
 # I2C support
 #
 CONFIG_I2C=m
 CONFIG_I2C_ALGOBIT=m
+# CONFIG_I2C_PHILIPSPAR is not set
 CONFIG_I2C_ELV=m
 CONFIG_I2C_VELLEMAN=m
+# CONFIG_I2C_BIT_SA1100_GPIO is not set
 CONFIG_I2C_ALGOPCF=m
 CONFIG_I2C_ELEKTOR=m
 CONFIG_I2C_CHARDEV=m
@@ -582,11 +714,14 @@
 #
 # L3 serial bus support
 #
-CONFIG_L3=m
+CONFIG_L3=y
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
 
 #
 # Other L3 adapters
 #
+CONFIG_L3_SA1111=y
 # CONFIG_BIT_SA1100_GPIO is not set
 
 #
@@ -594,17 +729,6 @@
 #
 # CONFIG_BUSMOUSE is not set
 # CONFIG_MOUSE is not set
-
-#
-# Joysticks
-#
-# CONFIG_INPUT_GAMEPORT is not set
-# CONFIG_INPUT_SERIO is not set
-
-#
-# Joysticks
-#
-# CONFIG_INPUT_IFORCE_USB is not set
 # CONFIG_QIC02_TAPE is not set
 
 #
@@ -618,6 +742,8 @@
 # CONFIG_PCWATCHDOG is not set
 # CONFIG_ACQUIRE_WDT is not set
 # CONFIG_ADVANTECH_WDT is not set
+# CONFIG_21285_WATCHDOG is not set
+# CONFIG_977_WATCHDOG is not set
 CONFIG_SA1100_WATCHDOG=m
 # CONFIG_EUROTECH_WDT is not set
 # CONFIG_IB700_WDT is not set
@@ -626,6 +752,7 @@
 # CONFIG_60XX_WDT is not set
 # CONFIG_W83877F_WDT is not set
 # CONFIG_MACHZ_WDT is not set
+# CONFIG_INTEL_RNG is not set
 # CONFIG_NVRAM is not set
 CONFIG_RTC=m
 CONFIG_SA1100_RTC=m
@@ -647,7 +774,51 @@
 #
 # Multimedia devices
 #
-# CONFIG_VIDEO_DEV is not set
+CONFIG_VIDEO_DEV=y
+
+#
+# Video For Linux
+#
+CONFIG_VIDEO_PROC_FS=y
+# CONFIG_I2C_PARPORT is not set
+
+#
+# Video Adapters
+#
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_BWQCAM is not set
+# CONFIG_VIDEO_CQCAM is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_TUNER_3036 is not set
+# CONFIG_VIDEO_STRADIS is not set
+# CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIDEO_ZORAN_BUZ is not set
+# CONFIG_VIDEO_ZORAN_DC10 is not set
+# CONFIG_VIDEO_ZORAN_LML33 is not set
+# CONFIG_VIDEO_ZR36120 is not set
+# CONFIG_VIDEO_MEYE is not set
+# CONFIG_VIDEO_CYBERPRO is not set
+
+#
+# Radio Adapters
+#
+# CONFIG_RADIO_CADET is not set
+# CONFIG_RADIO_RTRACK is not set
+# CONFIG_RADIO_RTRACK2 is not set
+# CONFIG_RADIO_AZTECH is not set
+# CONFIG_RADIO_GEMTEK is not set
+# CONFIG_RADIO_GEMTEK_PCI is not set
+# CONFIG_RADIO_MAXIRADIO is not set
+# CONFIG_RADIO_MAESTRO is not set
+# CONFIG_RADIO_MIROPCM20 is not set
+# CONFIG_RADIO_MIROPCM20_RDS is not set
+# CONFIG_RADIO_SF16FMI is not set
+# CONFIG_RADIO_TERRATEC is not set
+# CONFIG_RADIO_TRUST is not set
+# CONFIG_RADIO_TYPHOON is not set
+# CONFIG_RADIO_ZOLTRIX is not set
 
 #
 # File systems
@@ -656,15 +827,18 @@
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
 CONFIG_EXT3_FS=m
 CONFIG_JBD=m
 # CONFIG_JBD_DEBUG is not set
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
 # CONFIG_UMSDOS_FS is not set
 CONFIG_VFAT_FS=m
 # CONFIG_EFS_FS is not set
@@ -672,12 +846,15 @@
 CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_CRAMFS=m
-# CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_TMPFS=y
+CONFIG_RAMFS=y
 # CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 CONFIG_MINIX_FS=m
 # CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
 CONFIG_PROC_FS=y
 CONFIG_DEVFS_FS=y
@@ -685,11 +862,14 @@
 # CONFIG_DEVFS_DEBUG is not set
 # CONFIG_DEVPTS_FS is not set
 # CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
 # CONFIG_ROMFS_FS is not set
 CONFIG_EXT2_FS=m
 # CONFIG_SYSV_FS is not set
 # CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
 
 #
 # Network File Systems
@@ -698,21 +878,43 @@
 # CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
 # CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
 CONFIG_SUNRPC=m
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
 CONFIG_SMB_FS=m
 # CONFIG_SMB_NLS_DEFAULT is not set
 # CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
 # CONFIG_ZISOFS_FS is not set
-CONFIG_ZLIB_FS_INFLATE=m
 
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
 CONFIG_SMB_NLS=y
 CONFIG_NLS=y
 
@@ -761,26 +963,56 @@
 # Sound
 #
 CONFIG_SOUND=y
+
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=y
 # CONFIG_SOUND_BT878 is not set
+# CONFIG_SOUND_CMPCI is not set
+# CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
 # CONFIG_SOUND_FUSION is not set
 # CONFIG_SOUND_CS4281 is not set
+# CONFIG_SOUND_ES1370 is not set
+# CONFIG_SOUND_ES1371 is not set
 # CONFIG_SOUND_ESSSOLO1 is not set
 # CONFIG_SOUND_MAESTRO is not set
+# CONFIG_SOUND_MAESTRO3 is not set
+# CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
 # CONFIG_SOUND_SONICVIBES is not set
 # CONFIG_SOUND_TRIDENT is not set
 # CONFIG_SOUND_MSNDCLAS is not set
 # CONFIG_SOUND_MSNDPIN is not set
+# CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
 CONFIG_SOUND_SA1100=y
-CONFIG_SOUND_UDA1341=m
-CONFIG_SOUND_SA1111_UDA1341=m
-CONFIG_SOUND_SA1100SSP=m
+CONFIG_SOUND_UDA1341=y
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+CONFIG_SOUND_SA1111_UDA1341=y
+# CONFIG_SOUND_STORK_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
+# CONFIG_SOUND_STORK_AC97 is not set
 # CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
 # CONFIG_SOUND_TVMIXER is not set
 
 #
+# Advanced Linux Sound Architecture
+#
+# CONFIG_SND is not set
+
+#
 # Multimedia Capabilities Port drivers
 #
-# CONFIG_MCP is not set
+CONFIG_MCP=y
+CONFIG_MCP_SA1100=y
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
 
 #
 # USB support
@@ -796,8 +1028,10 @@
 # CONFIG_USB_LONG_TIMEOUT is not set
 
 #
-# USB Controllers
+# USB Host Controller Drivers
 #
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
 # CONFIG_USB_UHCI is not set
 # CONFIG_USB_UHCI_ALT is not set
 # CONFIG_USB_OHCI is not set
@@ -810,24 +1044,23 @@
 CONFIG_USB_BLUETOOTH=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DEBUG=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_ISD200=y
-CONFIG_USB_STORAGE_DPCM=y
-CONFIG_USB_STORAGE_HP8200e=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
 CONFIG_USB_ACM=m
 CONFIG_USB_PRINTER=m
 
 #
 # USB Human Interface Devices (HID)
 #
-CONFIG_USB_HID=m
-# CONFIG_USB_HIDDEV is not set
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB_WACOM=m
+
+#
+#   Input core support is needed for USB HID
+#
 
 #
 # USB Imaging devices
@@ -841,10 +1074,15 @@
 #
 # USB Multimedia devices
 #
-
-#
-#   Video4Linux support is needed for USB Multimedia device support
-#
+CONFIG_USB_IBMCAM=m
+CONFIG_USB_OV511=m
+CONFIG_USB_PWC=m
+CONFIG_USB_SE401=m
+# CONFIG_USB_STV680 is not set
+CONFIG_USB_VICAM=m
+CONFIG_USB_DSBR=m
+CONFIG_USB_DABUSB=m
+CONFIG_USB_KONICAWC=m
 
 #
 # USB Network adaptors
@@ -858,18 +1096,20 @@
 #
 # USB port drivers
 #
+CONFIG_USB_USS720=m
 
 #
 # USB Serial Converter support
 #
 CONFIG_USB_SERIAL=m
-# CONFIG_USB_SERIAL_GENERIC is not set
+CONFIG_USB_SERIAL_GENERIC=y
 CONFIG_USB_SERIAL_BELKIN=m
 CONFIG_USB_SERIAL_WHITEHEAT=m
 CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
 CONFIG_USB_SERIAL_EMPEG=m
 CONFIG_USB_SERIAL_FTDI_SIO=m
 CONFIG_USB_SERIAL_VISOR=m
+# CONFIG_USB_SERIAL_IPAQ is not set
 CONFIG_USB_SERIAL_IR=m
 CONFIG_USB_SERIAL_EDGEPORT=m
 CONFIG_USB_SERIAL_KEYSPAN_PDA=m
@@ -883,6 +1123,7 @@
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_KLSI is not set
 CONFIG_USB_SERIAL_PL2303=m
 CONFIG_USB_SERIAL_CYBERJACK=m
 CONFIG_USB_SERIAL_XIRCOM=m
@@ -892,6 +1133,7 @@
 # USB Miscellaneous drivers
 #
 CONFIG_USB_RIO500=m
+# CONFIG_USB_AUERSWALD is not set
 
 #
 # Bluetooth support
@@ -920,4 +1162,12 @@
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
-CONFIG_DEBUG_LL_SER3=y
+# CONFIG_DEBUG_DC21285_PORT is not set
+# CONFIG_DEBUG_CLPS711X_UART2 is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
diff -Nru a/arch/arm/def-configs/iq80310 b/arch/arm/def-configs/iq80310
--- a/arch/arm/def-configs/iq80310	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/def-configs/iq80310	Fri Mar 15 17:51:01 2002
@@ -454,7 +454,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 # CONFIG_IDEPCI_SHARE_IRQ is not set
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/arm/def-configs/jornada720 b/arch/arm/def-configs/jornada720
--- a/arch/arm/def-configs/jornada720	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/def-configs/jornada720	Fri Mar 15 17:51:02 2002
@@ -1,11 +1,15 @@
 #
-# Automatically generated make config: don't edit
+# Automatically generated by make menuconfig: don't edit
 #
 CONFIG_ARM=y
 # CONFIG_EISA is not set
 # CONFIG_SBUS is not set
 # CONFIG_MCA is not set
 CONFIG_UID16=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+# CONFIG_GENERIC_BUST_SPINLOCK is not set
+# CONFIG_GENERIC_ISA_DMA is not set
 
 #
 # Code maturity level options
@@ -23,24 +27,23 @@
 #
 # System Type
 #
+# CONFIG_ARCH_ANAKIN is not set
 # CONFIG_ARCH_ARCA5K is not set
 # CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
 # CONFIG_ARCH_CO285 is not set
 # CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_CAMELOT is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
 # CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
-# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_SHARK is not set
 
 #
 # Archimedes/A5000 Implementations
 #
-
-#
-# Archimedes/A5000 Implementations (select only ONE)
-#
 # CONFIG_ARCH_ARC is not set
 # CONFIG_ARCH_A5K is not set
 
@@ -58,12 +61,18 @@
 #
 # CONFIG_SA1100_ASSABET is not set
 # CONFIG_ASSABET_NEPONSET is not set
+# CONFIG_SA1100_ADSBITSY is not set
 # CONFIG_SA1100_BRUTUS is not set
 # CONFIG_SA1100_CERF is not set
-# CONFIG_SA1100_BITSY is not set
+# CONFIG_SA1100_H3100 is not set
+# CONFIG_SA1100_H3600 is not set
+# CONFIG_SA1100_H3800 is not set
+# CONFIG_SA1100_H3XXX is not set
 # CONFIG_SA1100_EXTENEX1 is not set
+# CONFIG_SA1100_FLEXANET is not set
 # CONFIG_SA1100_FREEBIRD is not set
 # CONFIG_SA1100_GRAPHICSCLIENT is not set
+# CONFIG_SA1100_GRAPHICSMASTER is not set
 CONFIG_SA1100_JORNADA720=y
 # CONFIG_SA1100_HUW_WEBPANEL is not set
 # CONFIG_SA1100_ITSY is not set
@@ -72,70 +81,75 @@
 # CONFIG_SA1100_OMNIMETER is not set
 # CONFIG_SA1100_PANGOLIN is not set
 # CONFIG_SA1100_PLEB is not set
+# CONFIG_SA1100_SHANNON is not set
 # CONFIG_SA1100_SHERMAN is not set
+# CONFIG_SA1100_SIMPAD is not set
 # CONFIG_SA1100_PFS168 is not set
 # CONFIG_SA1100_VICTOR is not set
 # CONFIG_SA1100_XP860 is not set
 # CONFIG_SA1100_YOPY is not set
 CONFIG_SA1111=y
+CONFIG_FORCE_MAX_ZONEORDER=9
 # CONFIG_SA1100_USB is not set
 # CONFIG_SA1100_USB_NETLINK is not set
 # CONFIG_SA1100_USB_CHAR is not set
-# CONFIG_SA1100_FREQUENCY_SCALE is not set
-# CONFIG_SA1100_VOLTAGE_SCALE is not set
+# CONFIG_REGISTERS is not set
 
 #
 # CLPS711X/EP721X Implementations
 #
+# CONFIG_ARCH_AUTCPU12 is not set
+# CONFIG_ARCH_CDB89712 is not set
+# CONFIG_ARCH_CLEP7312 is not set
+# CONFIG_ARCH_EDB7211 is not set
 # CONFIG_ARCH_P720T is not set
+# CONFIG_ARCH_EP7211 is not set
+# CONFIG_ARCH_EP7212 is not set
 # CONFIG_ARCH_ACORN is not set
 # CONFIG_FOOTBRIDGE is not set
 # CONFIG_FOOTBRIDGE_HOST is not set
 # CONFIG_FOOTBRIDGE_ADDIN is not set
 CONFIG_CPU_32=y
 # CONFIG_CPU_26 is not set
-
-#
-# Processor Type
-#
 # CONFIG_CPU_32v3 is not set
 CONFIG_CPU_32v4=y
 # CONFIG_CPU_ARM610 is not set
 # CONFIG_CPU_ARM710 is not set
 # CONFIG_CPU_ARM720T is not set
 # CONFIG_CPU_ARM920T is not set
+# CONFIG_CPU_ARM922T is not set
+# CONFIG_CPU_ARM926T is not set
 # CONFIG_CPU_ARM1020 is not set
 # CONFIG_CPU_SA110 is not set
 CONFIG_CPU_SA1100=y
+# CONFIG_ARM_THUMB is not set
 CONFIG_DISCONTIGMEM=y
 
 #
 # General setup
 #
-
-#
-# Please ensure that you have read the help on the next option
-#
-# CONFIG_ANGELBOOT is not set
 # CONFIG_PCI is not set
-# CONFIG_ISA is not set
+CONFIG_ISA=y
 # CONFIG_ISA_DMA is not set
+# CONFIG_CPU_FREQ is not set
 CONFIG_HOTPLUG=y
 
 #
 # PCMCIA/CardBus support
 #
 CONFIG_PCMCIA=y
+# CONFIG_I82092 is not set
 # CONFIG_I82365 is not set
 # CONFIG_TCIC is not set
 # CONFIG_PCMCIA_CLPS6700 is not set
 CONFIG_PCMCIA_SA1100=y
+# CONFIG_MERCURY_BACKPAQ is not set
 CONFIG_NET=y
 CONFIG_SYSVIPC=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 CONFIG_SYSCTL=y
 CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_FASTFPE is not set
+CONFIG_FPE_FASTFPE=y
 CONFIG_KCORE_ELF=y
 # CONFIG_KCORE_AOUT is not set
 CONFIG_BINFMT_AOUT=m
@@ -145,10 +159,8 @@
 # CONFIG_APM is not set
 # CONFIG_ARTHUR is not set
 CONFIG_CMDLINE="keepinitrd"
-# CONFIG_PFS168_CMDLINE is not set
 # CONFIG_LEDS is not set
-# CONFIG_ALIGNMENT_TRAP is not set
-# CONFIG_UCB1200 is not set
+CONFIG_ALIGNMENT_TRAP=y
 
 #
 # Parallel port support
@@ -159,63 +171,72 @@
 # Memory Technology Devices (MTD)
 #
 CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC1000 is not set
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOCPROBE is not set
-
-#
-# RAM/ROM Device Drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_BOOTLDR_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
 
 #
-# Linearly Mapped Flash Device Drivers
+# RAM/ROM/Flash chip drivers
 #
 CONFIG_MTD_CFI=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+# CONFIG_MTD_CFI_B1 is not set
+CONFIG_MTD_CFI_B2=y
+CONFIG_MTD_CFI_B4=y
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
 CONFIG_MTD_CFI_INTELEXT=y
 # CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_OBSOLETE_CHIPS is not set
 # CONFIG_MTD_AMDSTD is not set
 # CONFIG_MTD_SHARP is not set
+# CONFIG_MTD_JEDEC is not set
+
+#
+# Mapping drivers for chip access
+#
 # CONFIG_MTD_PHYSMAP is not set
 # CONFIG_MTD_NORA is not set
-# CONFIG_MTD_PNC2000 is not set
-# CONFIG_MTD_RPXLITE is not set
-# CONFIG_MTD_SC520CDP is not set
-# CONFIG_MTD_SBC_MEDIAGX is not set
-# CONFIG_MTD_ELAN_104NC is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_CDB89712 is not set
 CONFIG_MTD_SA1100=y
+# CONFIG_MTD_H3600_BACKPAQ is not set
 # CONFIG_MTD_DC21285 is not set
 # CONFIG_MTD_IQ80310 is not set
-# CONFIG_MTD_CSTM_CFI_JEDEC is not set
-# CONFIG_MTD_JEDEC is not set
-# CONFIG_MTD_MIXMEM is not set
-# CONFIG_MTD_OCTAGON is not set
-# CONFIG_MTD_VMAX is not set
 
 #
-# NAND Flash Device Drivers
+# Self-contained MTD device drivers
 #
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_NAND_SPIA is not set
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLKMTD is not set
+# CONFIG_MTD_DOC1000 is not set
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOCPROBE is not set
 
 #
-# User Modules And Translation Layers
+# NAND Flash Device Drivers
 #
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
+# CONFIG_MTD_NAND is not set
 
 #
 # Plug and Play configuration
@@ -246,6 +267,7 @@
 # CONFIG_MD_RAID0 is not set
 # CONFIG_MD_RAID1 is not set
 # CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
 # CONFIG_BLK_DEV_LVM is not set
 
 #
@@ -258,7 +280,7 @@
 # CONFIG_NETLINK_DEV is not set
 CONFIG_NETFILTER=y
 # CONFIG_NETFILTER_DEBUG is not set
-# CONFIG_FILTER is not set
+CONFIG_FILTER=y
 CONFIG_UNIX=y
 CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
@@ -282,10 +304,7 @@
 # CONFIG_IPV6 is not set
 # CONFIG_KHTTPD is not set
 # CONFIG_ATM is not set
-
-#
-#
-#
+# CONFIG_VLAN_8021Q is not set
 # CONFIG_IPX is not set
 # CONFIG_ATALK is not set
 # CONFIG_DECNET is not set
@@ -318,7 +337,6 @@
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_ETHERTAP is not set
-# CONFIG_NET_SB1000 is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -329,18 +347,44 @@
 # Ethernet (1000 Mbit)
 #
 # CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
-# CONFIG_PPP is not set
+# CONFIG_PLIP is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+# CONFIG_PPPOE is not set
 # CONFIG_SLIP is not set
 
 #
 # Wireless LAN (non-hamradio)
 #
-# CONFIG_NET_RADIO is not set
+CONFIG_NET_RADIO=y
+# CONFIG_STRIP is not set
+CONFIG_WAVELAN=m
+CONFIG_ARLAN=m
+CONFIG_AIRONET4500=m
+CONFIG_AIRONET4500_NONCS=m
+# CONFIG_AIRONET4500_PNP is not set
+# CONFIG_AIRONET4500_PCI is not set
+# CONFIG_AIRONET4500_ISA is not set
+# CONFIG_AIRONET4500_I365 is not set
+# CONFIG_AIRONET4500_PROC is not set
+# CONFIG_AIRO is not set
+CONFIG_HERMES=m
+CONFIG_PCMCIA_HERMES=m
+CONFIG_AIRO_CS=m
+CONFIG_NET_WIRELESS=y
 
 #
 # Token Ring devices
@@ -366,11 +410,11 @@
 CONFIG_PCMCIA_NMCLAN=m
 CONFIG_PCMCIA_SMC91C92=m
 CONFIG_PCMCIA_XIRC2PS=m
+# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_ARCNET_COM20020_CS is not set
 # CONFIG_PCMCIA_IBMTR is not set
 CONFIG_NET_PCMCIA_RADIO=y
 # CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_PCMCIA_HERMES is not set
 # CONFIG_PCMCIA_NETWAVE is not set
 CONFIG_PCMCIA_WAVELAN=m
 CONFIG_AIRONET4500_CS=m
@@ -384,10 +428,6 @@
 # IrDA (infrared) support
 #
 CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
 CONFIG_IRLAN=m
 # CONFIG_IRNET is not set
 CONFIG_IRCOMM=m
@@ -397,28 +437,19 @@
 #
 # Infrared-port device drivers
 #
-
-#
-# SIR device drivers
-#
 # CONFIG_IRTTY_SIR is not set
 # CONFIG_IRPORT_SIR is not set
-
-#
-# FIR device drivers
-#
+# CONFIG_DONGLE is not set
+# CONFIG_USB_IRDA is not set
 # CONFIG_NSC_FIR is not set
 # CONFIG_WINBOND_FIR is not set
 # CONFIG_TOSHIBA_FIR is not set
 # CONFIG_SMC_IRCC_FIR is not set
+# CONFIG_ALI_FIR is not set
+# CONFIG_VLSI_FIR is not set
 CONFIG_SA1100_FIR=m
 
 #
-# Dongle support
-#
-# CONFIG_DONGLE is not set
-
-#
 # ATA/IDE/MFM/RLL support
 #
 CONFIG_IDE=m
@@ -427,10 +458,6 @@
 # IDE, ATA and ATAPI Block devices
 #
 CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
 # CONFIG_BLK_DEV_HD_IDE is not set
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_BLK_DEV_IDEDISK=m
@@ -445,14 +472,10 @@
 # CONFIG_BLK_DEV_COMMERIAL is not set
 # CONFIG_BLK_DEV_TIVO is not set
 CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_IDECD is not set
+CONFIG_BLK_DEV_IDECD=m
 # CONFIG_BLK_DEV_IDETAPE is not set
 # CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_BLK_DEV_IDESCSI is not set
-
-#
-# IDE chipset support/bugfixes
-#
 # CONFIG_BLK_DEV_CMD640 is not set
 # CONFIG_BLK_DEV_CMD640_ENHANCED is not set
 # CONFIG_BLK_DEV_ISAPNP is not set
@@ -460,6 +483,9 @@
 # CONFIG_IDEDMA_AUTO is not set
 # CONFIG_DMA_NONPCI is not set
 # CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
 
 #
 # SCSI support
@@ -483,7 +509,13 @@
 #
 # Input core support
 #
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
+# CONFIG_INPUT_KEYBDEV is not set
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
 
 #
 # Character devices
@@ -493,19 +525,37 @@
 CONFIG_SERIAL=m
 # CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_ANAKIN is not set
+# CONFIG_SERIAL_ANAKIN_CONSOLE is not set
+# CONFIG_SERIAL_AMBA is not set
+# CONFIG_SERIAL_AMBA_CONSOLE is not set
+# CONFIG_SERIAL_CLPS711X is not set
+# CONFIG_SERIAL_CLPS711X_CONSOLE is not set
+# CONFIG_SERIAL_21285 is not set
+# CONFIG_SERIAL_21285_OLD is not set
+# CONFIG_SERIAL_21285_CONSOLE is not set
+# CONFIG_SERIAL_UART00 is not set
+# CONFIG_SERIAL_UART00_CONSOLE is not set
 CONFIG_SERIAL_SA1100=y
 CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SA1100_DEFAULT_BAUDRATE=115200
-# CONFIG_TOUCHSCREEN_UCB1200 is not set
-# CONFIG_TOUCHSCREEN_BITSY is not set
-CONFIG_PROFILER=m
-# CONFIG_PFS168_SPI is not set
-# CONFIG_PFS168_DTMF is not set
-# CONFIG_PFS168_MISC is not set
+# CONFIG_SERIAL_8250 is not set
+# CONFIG_SERIAL_8250_CONSOLE is not set
+# CONFIG_SERIAL_8250_EXTENDED is not set
+# CONFIG_SERIAL_8250_MANY_PORTS is not set
+# CONFIG_SERIAL_8250_SHARE_IRQ is not set
+# CONFIG_SERIAL_8250_DETECT_IRQ is not set
+# CONFIG_SERIAL_8250_MULTIPORT is not set
+# CONFIG_SERIAL_8250_HUB6 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
 CONFIG_UNIX98_PTY_COUNT=32
+# CONFIG_NEWTONKBD is not set
 
 #
 # I2C support
@@ -513,6 +563,15 @@
 # CONFIG_I2C is not set
 
 #
+# L3 serial bus support
+#
+# CONFIG_L3 is not set
+# CONFIG_L3_ALGOBIT is not set
+# CONFIG_L3_BIT_SA1100_GPIO is not set
+# CONFIG_L3_SA1111 is not set
+# CONFIG_BIT_SA1100_GPIO is not set
+
+#
 # Mice
 #
 # CONFIG_BUSMOUSE is not set
@@ -524,11 +583,33 @@
 #
 # Joysticks
 #
-# CONFIG_JOYSTICK is not set
-
-#
-# Input core support is needed for joysticks
-#
+# CONFIG_INPUT_GAMEPORT is not set
+# CONFIG_INPUT_NS558 is not set
+# CONFIG_INPUT_LIGHTNING is not set
+# CONFIG_INPUT_PCIGAME is not set
+# CONFIG_INPUT_CS461X is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_INPUT_SERIO is not set
+# CONFIG_INPUT_SERPORT is not set
+# CONFIG_INPUT_ANALOG is not set
+# CONFIG_INPUT_A3D is not set
+# CONFIG_INPUT_ADI is not set
+# CONFIG_INPUT_COBRA is not set
+# CONFIG_INPUT_GF2K is not set
+# CONFIG_INPUT_GRIP is not set
+# CONFIG_INPUT_INTERACT is not set
+# CONFIG_INPUT_TMDC is not set
+# CONFIG_INPUT_SIDEWINDER is not set
+# CONFIG_INPUT_IFORCE_USB is not set
+# CONFIG_INPUT_IFORCE_232 is not set
+# CONFIG_INPUT_WARRIOR is not set
+# CONFIG_INPUT_MAGELLAN is not set
+# CONFIG_INPUT_SPACEORB is not set
+# CONFIG_INPUT_SPACEBALL is not set
+# CONFIG_INPUT_STINGER is not set
+# CONFIG_INPUT_DB9 is not set
+# CONFIG_INPUT_GAMECON is not set
+# CONFIG_INPUT_TURBOGRAFX is not set
 # CONFIG_QIC02_TAPE is not set
 
 #
@@ -553,12 +634,13 @@
 #
 # PCMCIA character devices
 #
-CONFIG_PCMCIA_SERIAL_CS=m
+# CONFIG_PCMCIA_SERIAL_CS is not set
 
 #
 # Multimedia devices
 #
 # CONFIG_VIDEO_DEV is not set
+# CONFIG_V4L2_DEV is not set
 
 #
 # File systems
@@ -568,37 +650,45 @@
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
 # CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
+# CONFIG_EXT3_FS is not set
+# CONFIG_JBD is not set
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
 # CONFIG_UMSDOS_FS is not set
-CONFIG_VFAT_FS=m
+# CONFIG_VFAT_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_JFFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_CRAMFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=2
+# CONFIG_CRAMFS is not set
+# CONFIG_TMPFS is not set
 CONFIG_RAMFS=y
-# CONFIG_ISO9660_FS is not set
+CONFIG_ISO9660_FS=m
 # CONFIG_JOLIET is not set
+# CONFIG_ZISOFS is not set
 # CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
 # CONFIG_NTFS_RW is not set
 # CONFIG_HPFS_FS is not set
 CONFIG_PROC_FS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVFS_MOUNT is not set
-# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+# CONFIG_DRIVERFS_FS is not set
 CONFIG_DEVPTS_FS=y
 # CONFIG_QNX4FS_FS is not set
 # CONFIG_QNX4FS_RW is not set
 # CONFIG_ROMFS_FS is not set
 CONFIG_EXT2_FS=y
 # CONFIG_SYSV_FS is not set
-# CONFIG_SYSV_FS_WRITE is not set
 # CONFIG_UDF_FS is not set
 # CONFIG_UDF_RW is not set
 # CONFIG_UFS_FS is not set
@@ -608,6 +698,7 @@
 # Network File Systems
 #
 # CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=m
 CONFIG_NFS_V3=y
 # CONFIG_ROOT_NFS is not set
@@ -616,8 +707,7 @@
 CONFIG_SUNRPC=m
 CONFIG_LOCKD=m
 CONFIG_LOCKD_V4=y
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_SMB_FS is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_NCPFS_PACKET_SIGNING is not set
 # CONFIG_NCPFS_IOCTL_LOCKING is not set
@@ -627,59 +717,22 @@
 # CONFIG_NCPFS_SMALLDOS is not set
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
+# CONFIG_ZISOFS_FS is not set
+# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
 #
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
-CONFIG_SMB_NLS=y
-CONFIG_NLS=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_UTF8 is not set
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
 
 #
 # Console drivers
 #
 CONFIG_PC_KEYMAP=y
 # CONFIG_VGA_CONSOLE is not set
-CONFIG_FB=y
 
 #
 # Frame-buffer support
@@ -687,16 +740,17 @@
 CONFIG_FB=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_FB_ACORN is not set
+# CONFIG_FB_ANAKIN is not set
 # CONFIG_FB_CLPS711X is not set
+# CONFIG_FB_SA1100 is not set
 CONFIG_FB_EPSON1356=y
 # CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_SA1100 is not set
 # CONFIG_FB_VIRTUAL is not set
 CONFIG_FBCON_ADVANCED=y
 # CONFIG_FBCON_MFB is not set
 # CONFIG_FBCON_CFB2 is not set
 # CONFIG_FBCON_CFB4 is not set
-CONFIG_FBCON_CFB8=y
+# CONFIG_FBCON_CFB8 is not set
 CONFIG_FBCON_CFB16=y
 # CONFIG_FBCON_CFB24 is not set
 # CONFIG_FBCON_CFB32 is not set
@@ -721,10 +775,10 @@
 # Sound
 #
 CONFIG_SOUND=m
-CONFIG_SOUND_UDA1341=m
-# CONFIG_SOUND_SA1100_SSP is not set
+# CONFIG_SOUND_BT878 is not set
 # CONFIG_SOUND_CMPCI is not set
 # CONFIG_SOUND_EMU10K1 is not set
+# CONFIG_MIDI_EMU10K1 is not set
 # CONFIG_SOUND_FUSION is not set
 # CONFIG_SOUND_CS4281 is not set
 # CONFIG_SOUND_ES1370 is not set
@@ -733,28 +787,121 @@
 # CONFIG_SOUND_MAESTRO is not set
 # CONFIG_SOUND_MAESTRO3 is not set
 # CONFIG_SOUND_ICH is not set
+# CONFIG_SOUND_RME96XX is not set
 # CONFIG_SOUND_SONICVIBES is not set
 # CONFIG_SOUND_TRIDENT is not set
 # CONFIG_SOUND_MSNDCLAS is not set
 # CONFIG_SOUND_MSNDPIN is not set
 # CONFIG_SOUND_VIA82CXXX is not set
+# CONFIG_MIDI_VIA82CXXX is not set
+CONFIG_SOUND_SA1100=m
+# CONFIG_SOUND_UDA1341 is not set
+# CONFIG_SOUND_ASSABET_UDA1341 is not set
+# CONFIG_SOUND_H3600_UDA1341 is not set
+# CONFIG_SOUND_PANGOLIN_UDA1341 is not set
+# CONFIG_SOUND_SA1111_UDA1341 is not set
+# CONFIG_SOUND_SA1100SSP is not set
 # CONFIG_SOUND_OSS is not set
+# CONFIG_SOUND_WAVEARTIST is not set
 # CONFIG_SOUND_TVMIXER is not set
 
 #
+# Multimedia Capabilities Port drivers
+#
+# CONFIG_MCP is not set
+# CONFIG_MCP_SA1100 is not set
+# CONFIG_MCP_UCB1200 is not set
+# CONFIG_MCP_UCB1200_AUDIO is not set
+# CONFIG_MCP_UCB1200_TS is not set
+
+#
 # USB support
 #
 # CONFIG_USB is not set
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+# CONFIG_USB_OHCI_SA1111 is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_HID is not set
+# CONFIG_USB_HIDDEV is not set
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+# CONFIG_USB_WACOM is not set
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_RIO500 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
 
 #
 # Kernel hacking
 #
 # CONFIG_NO_FRAME_POINTER is not set
-CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_INFO is not set
-# CONFIG_MAGIC_SYSRQ is not set
 # CONFIG_NO_PGT_CACHE is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_WAITQ is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 # CONFIG_DEBUG_DC21285_PORT is not set
 # CONFIG_DEBUG_CLPS711X_UART2 is not set
+# CONFIG_DEBUG_LL_SER3 is not set
diff -Nru a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c
--- a/arch/arm/kernel/dma.c	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/kernel/dma.c	Fri Mar 15 17:51:03 2002
@@ -286,3 +286,5 @@
 EXPORT_SYMBOL(get_dma_residue);
 EXPORT_SYMBOL(set_dma_sg);
 EXPORT_SYMBOL(set_dma_speed);
+
+EXPORT_SYMBOL(dma_spin_lock);
diff -Nru a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
--- a/arch/arm/kernel/entry-armv.S	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/kernel/entry-armv.S	Fri Mar 15 17:51:02 2002
@@ -16,6 +16,7 @@
 #include <linux/config.h>
 #include "entry-header.S"
 #include <asm/thread_info.h>
+#include <asm/glue.h>
 
 
 #ifdef IOC_BASE
@@ -681,12 +682,12 @@
 /*
  * This routine must not corrupt r9
  */
-#ifdef MULTI_CPU
+#ifdef MULTI_ABORT
 		ldr	r4, .LCprocfns			@ pass r0, r3 to
 		mov	lr, pc				@ processor code
 		ldr	pc, [r4]			@ call processor specific code
 #else
-		bl	cpu_data_abort
+		bl	CPU_ABORT_HANDLER
 #endif
 		msr	cpsr_c, r9
 		mov	r2, sp
@@ -799,7 +800,7 @@
 .LCirq:		.word	__temp_irq
 .LCund:		.word	__temp_und
 .LCabt:		.word	__temp_abt
-#ifdef MULTI_CPU
+#ifdef MULTI_ABORT
 .LCprocfns:	.word	SYMBOL_NAME(processor)
 #endif
 .LCfp:		.word	SYMBOL_NAME(fp_enter)
@@ -823,12 +824,12 @@
 		alignment_trap r7, r7, __temp_abt
 		zero_fp
 		mov	r0, r2				@ remove once everyones in sync
-#ifdef MULTI_CPU
+#ifdef MULTI_ABORT
 		ldr	r4, .LCprocfns			@ pass r0, r3 to
 		mov	lr, pc				@ processor code
 		ldr	pc, [r4]			@ call processor specific code
 #else
-		bl	cpu_data_abort
+		bl	CPU_ABORT_HANDLER
 #endif
 		set_cpsr_c r2, #MODE_SVC		@ Enable interrupts
 		mov	r2, sp
diff -Nru a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
--- a/arch/arm/kernel/setup.c	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/kernel/setup.c	Fri Mar 15 17:51:01 2002
@@ -76,6 +76,9 @@
 #ifdef MULTI_TLB
 struct cpu_tlb_fns cpu_tlb;
 #endif
+#ifdef MULTI_USER
+struct cpu_user_fns cpu_user;
+#endif
 
 unsigned char aux_device_present;
 char elf_platform[ELF_PLATFORM_SIZE];
@@ -247,6 +250,9 @@
 #endif
 #ifdef MULTI_TLB
 	cpu_tlb = *list->tlb;
+#endif
+#ifdef MULTI_USER
+	cpu_user = *list->user;
 #endif
 
 	printk("Processor: %s %s revision %d\n",
diff -Nru a/arch/arm/mach-integrator/pci.c b/arch/arm/mach-integrator/pci.c
--- a/arch/arm/mach-integrator/pci.c	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mach-integrator/pci.c	Fri Mar 15 17:51:03 2002
@@ -113,7 +113,6 @@
 extern void pci_v3_init(void *);
 
 struct hw_pci integrator_pci __initdata = {
-	mem_offset:		0x40000000,
 	swizzle:		integrator_swizzle,
 	map_irq:		integrator_map_irq,
 	setup:			pci_v3_setup,
diff -Nru a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
--- a/arch/arm/mach-integrator/pci_v3.c	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mach-integrator/pci_v3.c	Fri Mar 15 17:51:01 2002
@@ -435,7 +435,7 @@
 	resource[1] = &non_mem;
 	resource[2] = &pre_mem;
 
-	return 0;
+	return 1;
 }
 
 /*
@@ -529,8 +529,10 @@
 {
 	int ret = 0;
 
-	if (nr == 0)
+	if (nr == 0) {
+		sys->mem_offset = 0x40000000;
 		ret = pci_v3_setup_resources(sys->resource);
+	}
 
 	return ret;
 }
@@ -634,7 +636,6 @@
 void __init pci_v3_postinit(void)
 {
 	unsigned int pci_cmd;
-	int ret;
 
 	pci_cmd = PCI_COMMAND_MEMORY |
 		  PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
diff -Nru a/arch/arm/mach-iop310/iq80310-time.c b/arch/arm/mach-iop310/iq80310-time.c
--- a/arch/arm/mach-iop310/iq80310-time.c	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mach-iop310/iq80310-time.c	Fri Mar 15 17:51:01 2002
@@ -47,23 +47,44 @@
 	u_long b0, b1, b2, b3, val;
 
 	b0 = *la0; b1 = *la1; b2 = *la2; b3 = *la3;
-	b0 = (((b0 & 0x20) >> 1) | (b0 & 0x1f));
-	b1 = (((b1 & 0x20) >> 1) | (b1 & 0x1f));
-	b2 = (((b2 & 0x20) >> 1) | (b2 & 0x1f));
+	b0 = (((b0 & 0x40) >> 1) | (b0 & 0x1f));
+	b1 = (((b1 & 0x40) >> 1) | (b1 & 0x1f));
+	b2 = (((b2 & 0x40) >> 1) | (b2 & 0x1f));
 	b3 = (b3 & 0x0f);
 	val = ((b0 << 0) | (b1 << 6) | (b2 << 12) | (b3 << 18));
 	return val;
 }
 
-/* IRQs are disabled before entering here from do_gettimeofday() */
+/*
+ * IRQs are disabled before entering here from do_gettimeofday().
+ * Note that the counter may wrap.  When it does, 'elapsed' will
+ * be small, but we will have a pending interrupt.
+ */
 static unsigned long iq80310_gettimeoffset (void)
 {
-	unsigned long elapsed, usec;
+	unsigned long elapsed, usec, tmp1;
+	unsigned int stat1, stat2;
 
-	/* We need elapsed timer ticks since last interrupt */
+	stat1 = *(volatile u8 *)IQ80310_INT_STAT;
 	elapsed = iq80310_read_timer();
+	stat2 = *(volatile u8 *)IQ80310_INT_STAT;
 
-	/* Now convert them to usec */
+	/*
+	 * If an interrupt was pending before we read the timer,
+	 * we've already wrapped.  Factor this into the time.
+	 * If an interrupt was pending after we read the timer,
+	 * it may have wrapped between checking the interrupt
+	 * status and reading the timer.  Re-read the timer to
+	 * be sure its value is after the wrap.
+	 */
+	if (stat1 & 1)
+		elapsed += LATCH;
+	else if (stat2 & 1)
+		elapsed = LATCH + iq80310_read_timer();
+
+	/*
+	 * Now convert them to usec.
+	 */
 	usec = (unsigned long)(elapsed*tick)/LATCH;
 
 	return usec;
@@ -92,9 +113,7 @@
 	 *
 	 * -DS
 	 */
-	irq_exit(smp_processor_id(), irq);
 	do_timer(regs);
-	irq_enter(smp_processor_id(), irq);
 }
 
 extern unsigned long (*gettimeoffset)(void);
@@ -116,4 +135,3 @@
 	*timer_en |= 2;
 	*timer_en |= 1;
 }
-
diff -Nru a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
--- a/arch/arm/mach-sa1100/Makefile	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mach-sa1100/Makefile	Fri Mar 15 17:51:03 2002
@@ -14,69 +14,105 @@
 obj-m :=
 obj-n :=
 obj-  :=
+led-y := leds.o
 
-export-objs :=	assabet.o dma.o flexanet.o freebird.o generic.o h3600.o \
-		huw_webpanel.o irq.o pcipool.o sa1111.o sa1111-pcibuf.o \
-		yopy.o usb_ctl.o usb_recv.o usb_send.o
+export-objs :=	dma.o generic.o irq.o pcipool.o sa1111.o sa1111-pcibuf.o \
+		usb_ctl.o usb_recv.o usb_send.o pm.o
 
 # This needs to be cleaned up.  We probably need to have SA1100
 # and SA1110 config symbols.
 #
 # We link the CPU support next, so that RAM timings can be tuned.
 ifeq ($(CONFIG_CPU_FREQ),y)
-obj-$(CONFIG_SA1100_ASSABET) += cpu-sa1110.o
-obj-$(CONFIG_SA1100_CERF) += cpu-sa1110.o
-obj-$(CONFIG_SA1100_PT_SYSTEM3) += cpu-sa1110.o
-obj-$(CONFIG_SA1100_LART) += cpu-sa1100.o
+obj-$(CONFIG_SA1100_ASSABET)		+= cpu-sa1110.o
+obj-$(CONFIG_SA1100_CERF)		+= cpu-sa1110.o
+obj-$(CONFIG_SA1100_LART)		+= cpu-sa1100.o
+obj-$(CONFIG_SA1100_PT_SYSTEM3)		+= cpu-sa1110.o
 endif
 
 # Next, the SA1111 stuff.
-obj-$(CONFIG_SA1111) += sa1111.o
-obj-$(CONFIG_USB_OHCI_SA1111) += sa1111-pcibuf.o pcipool.o
+obj-$(CONFIG_SA1111)		+= sa1111.o
+obj-$(CONFIG_USB_OHCI_SA1111)	+= sa1111-pcibuf.o pcipool.o
 
 # Specific board support
-obj-$(CONFIG_SA1100_ADSBITSY) += adsbitsy.o
-obj-$(CONFIG_SA1100_ASSABET) += assabet.o
-obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o
-obj-$(CONFIG_SA1100_BRUTUS) += brutus.o
-obj-$(CONFIG_SA1100_CERF) += cerf.o
-obj-$(CONFIG_SA1100_EMPEG) += empeg.o
-obj-$(CONFIG_SA1100_FLEXANET) += flexanet.o
-obj-$(CONFIG_SA1100_FREEBIRD) += freebird.o
-obj-$(CONFIG_SA1100_GRAPHICSCLIENT) += graphicsclient.o
-obj-$(CONFIG_SA1100_GRAPHICSMASTER) += graphicsmaster.o
-obj-$(CONFIG_SA1100_H3600) += h3600.o
-obj-$(CONFIG_SA1100_HUW_WEBPANEL) += huw_webpanel.o
-obj-$(CONFIG_SA1100_ITSY) += itsy.o
-obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o
-obj-$(CONFIG_SA1100_LART) += lart.o
-obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o
-obj-$(CONFIG_SA1100_OMNIMETER) += omnimeter.o
-obj-$(CONFIG_SA1100_PANGOLIN) += pangolin.o
-obj-$(CONFIG_SA1100_PFS168) += pfs168.o
-obj-$(CONFIG_SA1100_PLEB) += pleb.o
-obj-$(CONFIG_SA1100_SHANNON) += shannon.o
-obj-$(CONFIG_SA1100_SHERMAN) += sherman.o
-obj-$(CONFIG_SA1100_PT_SYSTEM3) += system3.o
-obj-$(CONFIG_SA1100_SIMPAD) += simpad.o
-obj-$(CONFIG_SA1100_VICTOR) += victor.o
-obj-$(CONFIG_SA1100_XP860) += xp860.o
-obj-$(CONFIG_SA1100_YOPY) += yopy.o
+obj-$(CONFIG_SA1100_ADSBITSY)		+= adsbitsy.o
+led-$(CONFIG_SA1100_ADSBITSY)		+= leds-adsbitsy.o
+
+obj-$(CONFIG_SA1100_ASSABET)		+= assabet.o
+export-objs				+= assabet.o
+led-$(CONFIG_SA1100_ASSABET)		+= leds-assabet.o
+obj-$(CONFIG_ASSABET_NEPONSET)		+= neponset.o
+
+obj-$(CONFIG_SA1100_BADGE4)		+= badge4.o
+export-objs				+= badge4.o
+
+obj-$(CONFIG_SA1100_BRUTUS)		+= brutus.o
+led-$(CONFIG_SA1100_BRUTUS)		+= leds-brutus.o
+
+obj-$(CONFIG_SA1100_CERF)		+= cerf.o
+led-$(CONFIG_SA1100_CERF)		+= leds-cerf.o
+
+obj-$(CONFIG_SA1100_EMPEG)		+= empeg.o
+
+obj-$(CONFIG_SA1100_FLEXANET)		+= flexanet.o
+export-objs				+= flexanet.o
+led-$(CONFIG_SA1100_FLEXANET)		+= leds-flexanet.o
+
+obj-$(CONFIG_SA1100_FREEBIRD)		+= freebird.o
+export-objs				+= freebird.o
+
+obj-$(CONFIG_SA1100_GRAPHICSCLIENT)	+= graphicsclient.o
+led-$(CONFIG_SA1100_GRAPHICSCLIENT)	+= leds-graphicsclient.o
+
+obj-$(CONFIG_SA1100_GRAPHICSMASTER)	+= graphicsmaster.o
+led-$(CONFIG_SA1100_GRAPHICSMASTER)	+= leds-graphicsmaster.o
+
+obj-$(CONFIG_SA1100_H3600)		+= h3600.o
+export-objs				+= h3600.o
+
+obj-$(CONFIG_SA1100_HUW_WEBPANEL)	+= huw_webpanel.o
+export-objs				+= huw_webpanel.o
+
+obj-$(CONFIG_SA1100_ITSY)		+= itsy.o
+
+obj-$(CONFIG_SA1100_JORNADA720)		+= jornada720.o
+
+obj-$(CONFIG_SA1100_LART)		+= lart.o
+led-$(CONFIG_SA1100_LART)		+= leds-lart.o
+
+obj-$(CONFIG_SA1100_NANOENGINE)		+= nanoengine.o
+
+obj-$(CONFIG_SA1100_OMNIMETER)		+= omnimeter.o
+
+obj-$(CONFIG_SA1100_PANGOLIN)		+= pangolin.o
+
+obj-$(CONFIG_SA1100_PFS168)		+= pfs168.o
+led-$(CONFIG_SA1100_PFS168)		+= leds-pfs168.o
+
+obj-$(CONFIG_SA1100_PLEB)		+= pleb.o
+
+obj-$(CONFIG_SA1100_PT_SYSTEM3)		+= system3.o
+led-$(CONFIG_SA1100_PT_SYSTEM3)		+= leds-system3.o
+
+obj-$(CONFIG_SA1100_SHANNON)		+= shannon.o
+
+obj-$(CONFIG_SA1100_SHERMAN)		+= sherman.o
+
+obj-$(CONFIG_SA1100_SIMPAD)		+= simpad.o
+led-$(CONFIG_SA1100_SIMPAD)		+= leds-simpad.o  
+
+obj-$(CONFIG_SA1100_STORK)		+= stork.o
+export-objs				+= stork.o
+
+obj-$(CONFIG_SA1100_VICTOR)		+= victor.o
+
+obj-$(CONFIG_SA1100_XP860)		+= xp860.o
+
+obj-$(CONFIG_SA1100_YOPY)		+= yopy.o
+export-objs				+= yopy.o
 
 # LEDs support
-leds-y := leds.o
-leds-$(CONFIG_SA1100_ADSBITSY) += leds-adsbitsy.o
-leds-$(CONFIG_SA1100_ASSABET) += leds-assabet.o
-leds-$(CONFIG_SA1100_BRUTUS) += leds-brutus.o
-leds-$(CONFIG_SA1100_CERF) += leds-cerf.o
-leds-$(CONFIG_SA1100_FLEXANET) += leds-flexanet.o
-leds-$(CONFIG_SA1100_GRAPHICSCLIENT) += leds-graphicsclient.o
-leds-$(CONFIG_SA1100_GRAPHICSMASTER) += leds-graphicsmaster.o
-leds-$(CONFIG_SA1100_LART) += leds-lart.o
-leds-$(CONFIG_SA1100_PFS168) += leds-pfs168.o
-leds-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o  
-leds-$(CONFIG_SA1100_PT_SYSTEM3) += leds-system3.o
-obj-$(CONFIG_LEDS) += $(leds-y)
+obj-$(CONFIG_LEDS) += $(led-y)
 
 # SA1110 USB client support
 list-multi += sa1100usb_core.o
diff -Nru a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
--- a/arch/arm/mach-sa1100/cpu-sa1110.c	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c	Fri Mar 15 17:51:01 2002
@@ -3,7 +3,7 @@
  *
  *  Copyright (C) 2001 Russell King
  *
- *  $Id: cpu-sa1110.c,v 1.6 2001/10/22 11:53:47 rmk Exp $
+ *  $Id: cpu-sa1110.c,v 1.8 2002/01/09 17:13:27 rmk Exp $
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -69,13 +69,23 @@
 };
 
 static struct sdram_params samsung_k4s641632d_tc75 __initdata = {
-	rows:		14,
-	tck:		9,
-	trcd:		27,
-	trp:		20,
-	twr:		9,
-	refresh:	64000,
-	cas_latency:	3,
+	rows:		    14,
+	tck:		     9,
+	trcd:		    27,
+	trp:		    20,
+	twr:		     9,
+	refresh:	 64000,
+	cas_latency:	     3,
+};
+
+static struct sdram_params samsung_km416s4030ct __initdata = {
+	rows:		    13,
+	tck:		     8,
+	trcd:		    24,	/* 3 CLKs */
+	trp:		    24,	/* 3 CLKs */
+	twr:		    16,	/* Trdl: 2 CLKs */
+	refresh:	 64000,
+	cas_latency:	     3,
 };
 
 static struct sdram_params sdram_params;
@@ -273,6 +283,8 @@
 	if (machine_is_pt_system3())
 		sdram = &samsung_k4s641632d_tc75;
 
+	if (machine_is_h3100())
+		sdram = &samsung_km416s4030ct;
 
 	if (sdram) {
 		printk(KERN_DEBUG "SDRAM: tck: %d trcd: %d trp: %d"
diff -Nru a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
--- a/arch/arm/mach-sa1100/pm.c	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mach-sa1100/pm.c	Fri Mar 15 17:51:02 2002
@@ -20,6 +20,7 @@
  * 			in the platform specific files.
  */
 #include <linux/config.h>
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/pm.h>
 #include <linux/slab.h>
@@ -27,6 +28,7 @@
 #include <linux/interrupt.h>
 #include <linux/sysctl.h>
 #include <linux/errno.h>
+#include <linux/cpufreq.h>
 
 #include <asm/hardware.h>
 #include <asm/memory.h>
@@ -210,3 +212,5 @@
 __initcall(pm_init);
 
 #endif
+
+EXPORT_SYMBOL(pm_do_suspend);
diff -Nru a/arch/arm/mach-sa1100/system3.c b/arch/arm/mach-sa1100/system3.c
--- a/arch/arm/mach-sa1100/system3.c	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mach-sa1100/system3.c	Fri Mar 15 17:51:02 2002
@@ -99,10 +99,9 @@
  */
 
 static struct map_desc system3_io_desc[] __initdata = {
- /* virtual     physical    length      domain     r  w  c  b */
-  { 0xe8000000, 0x00000000,		0x01000000, DOMAIN_IO, 0, 1, 0, 0 }, /* Flash bank 0 */
-  { 0xf3000000, PT_CPLD_BASE,	0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
-  { 0xf4000000, PT_SA1111_BASE,	0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
+ /* virtual     physical        length      domain     r  w  c  b */
+  { 0xf3000000, PT_CPLD_BASE,   0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* System Registers */
+  { 0xf4000000, PT_SA1111_BASE, 0x00100000, DOMAIN_IO, 0, 1, 0, 0 }, /* SA-1111 */
   LAST_DESC
 };
 
diff -Nru a/arch/arm/mm/abort-ev4.S b/arch/arm/mm/abort-ev4.S
--- a/arch/arm/mm/abort-ev4.S	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mm/abort-ev4.S	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 /*
- * Function: armv4_early_abort
+ * Function: v4_early_abort
  *
  * Params  : r2 = address of aborted instruction
  *         : r3 = saved SPSR
@@ -18,7 +18,7 @@
  * picture.  Unfortunately, this does happen.  We live with it.
  */
 	.align	5
-ENTRY(armv4_early_abort)
+ENTRY(v4_early_abort)
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 	ldr	r3, [r2]			@ read aborted ARM instruction
diff -Nru a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
--- a/arch/arm/mm/abort-ev4t.S	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mm/abort-ev4t.S	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 /*
- * Function: armv4t_early_abort
+ * Function: v4t_early_abort
  *
  * Params  : r2 = address of aborted instruction
  *         : r3 = saved SPSR
@@ -18,7 +18,7 @@
  * picture.  Unfortunately, this does happen.  We live with it.
  */
 	.align	5
-ENTRY(armv4t_early_abort)
+ENTRY(v4t_early_abort)
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 	tst	r3, #PSR_T_BIT
diff -Nru a/arch/arm/mm/abort-ev5ej.S b/arch/arm/mm/abort-ev5ej.S
--- a/arch/arm/mm/abort-ev5ej.S	Fri Mar 15 17:51:00 2002
+++ b/arch/arm/mm/abort-ev5ej.S	Fri Mar 15 17:51:00 2002
@@ -1,7 +1,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 /*
- * Function: armv5ej_early_abort
+ * Function: v5ej_early_abort
  *
  * Params  : r2 = address of aborted instruction
  *         : r3 = saved SPSR
@@ -18,7 +18,7 @@
  * picture.  Unfortunately, this does happen.  We live with it.
  */
 	.align	5
-ENTRY(armv5ej_early_abort)
+ENTRY(v5ej_early_abort)
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
 	tst	r3, #PSR_J_BIT
diff -Nru a/arch/arm/mm/abort-lv4t.S b/arch/arm/mm/abort-lv4t.S
--- a/arch/arm/mm/abort-lv4t.S	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mm/abort-lv4t.S	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 /*
- * Function: armv4t_late_abort
+ * Function: v4t_late_abort
  *
  * Params  : r2 = address of aborted instruction
  *         : r3 = saved SPSR
@@ -17,7 +17,7 @@
  * abort here if the I-TLB and D-TLB aren't seeing the same
  * picture.  Unfortunately, this does happen.  We live with it.
  */
-ENTRY(armv4t_late_abort)
+ENTRY(v4t_late_abort)
 	tst	r3, #PSR_T_BIT			@ check for thumb mode
 	mrc	p15, 0, r1, c5, c0, 0		@ get FSR
 	mrc	p15, 0, r0, c6, c0, 0		@ get FAR
diff -Nru a/arch/arm/mm/copypage-v3.S b/arch/arm/mm/copypage-v3.S
--- a/arch/arm/mm/copypage-v3.S	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/copypage-v3.S	Fri Mar 15 17:51:01 2002
@@ -20,7 +20,7 @@
  *
  * FIXME: do we need to handle cache stuff...
  */
-ENTRY(armv3_copy_user_page)
+ENTRY(v3_copy_user_page)
 	stmfd	sp!, {r4, lr}			@	2
 	mov	r2, #PAGE_SZ/64			@	1
 	ldmia	r1!, {r3, r4, ip, lr}		@	4+1
@@ -42,7 +42,7 @@
  *
  * FIXME: do we need to handle cache stuff...
  */
-ENTRY(armv3_clear_user_page)
+ENTRY(v3_clear_user_page)
 	str	lr, [sp, #-4]!
 	mov	r1, #PAGE_SZ/64			@ 1
 	mov	r2, #0				@ 1
@@ -57,3 +57,8 @@
 	bne	1b				@ 1
 	ldr	pc, [sp], #4
 
+	.section ".text.init", #alloc, #execinstr
+
+ENTRY(v3_user_fns)
+	.long	v3_clear_user_page
+	.long	v3_copy_user_page
diff -Nru a/arch/arm/mm/copypage-v4.S b/arch/arm/mm/copypage-v4.S
--- a/arch/arm/mm/copypage-v4.S	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/copypage-v4.S	Fri Mar 15 17:51:01 2002
@@ -26,7 +26,7 @@
  * instruction.  If your processor does not supply this, you have to write your
  * own copy_user_page that does the right thing.
  */
-ENTRY(armv4_copy_user_page)
+ENTRY(v4_copy_user_page)
 	stmfd	sp!, {r4, lr}			@ 2
 	mov	r2, #PAGE_SZ/64			@ 1
 	ldmia	r1!, {r3, r4, ip, lr}		@ 4
@@ -51,7 +51,7 @@
  *
  * Same story as above.
  */
-ENTRY(armv4_clear_user_page)
+ENTRY(v4_clear_user_page)
 	str	lr, [sp, #-4]!
 	mov	r1, #PAGE_SZ/64			@ 1
 	mov	r2, #0				@ 1
@@ -68,3 +68,10 @@
 	bne	1b				@ 1
 	mcr	p15, 0, r1, c7, c10, 4		@ 1   drain WB
 	ldr	pc, [sp], #4
+
+	.section ".text.init", #alloc, #execinstr
+
+ENTRY(v4_user_fns)
+	.long	v4_clear_user_page
+	.long	v4_copy_user_page
+
diff -Nru a/arch/arm/mm/copypage-v4mc.S b/arch/arm/mm/copypage-v4mc.S
--- a/arch/arm/mm/copypage-v4mc.S	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mm/copypage-v4mc.S	Fri Mar 15 17:51:03 2002
@@ -26,7 +26,7 @@
  * instruction.  If your processor does not supply this, you have to write your
  * own copy_user_page that does the right thing.
  */
-ENTRY(armv4_mc_copy_user_page)
+ENTRY(v4_mc_copy_user_page)
 	stmfd	sp!, {r4, lr}			@ 2
 	mov	r4, r0
 	mov	r0, r1
@@ -53,7 +53,7 @@
  *
  * Same story as above.
  */
-ENTRY(armv4_mc_clear_user_page)
+ENTRY(v4_mc_clear_user_page)
 	str	lr, [sp, #-4]!
 	mov	r1, #PAGE_SZ/64			@ 1
 	mov	r2, #0				@ 1
@@ -69,3 +69,10 @@
 	subs	r1, r1, #1			@ 1
 	bne	1b				@ 1
 	ldr	pc, [sp], #4
+
+	.section ".text.init", #alloc, #execinstr
+
+ENTRY(v4_mc_user_fns)
+	.long	v4_mc_clear_user_page
+	.long	v4_mc_copy_user_page
+
diff -Nru a/arch/arm/mm/copypage-v5te.S b/arch/arm/mm/copypage-v5te.S
--- a/arch/arm/mm/copypage-v5te.S	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mm/copypage-v5te.S	Fri Mar 15 17:51:02 2002
@@ -32,7 +32,7 @@
  * page.  We rely on the mini-cache being smaller than one page, so we'll
  * cycle through the complete cache anyway.
  */
-ENTRY(armv5te_copy_user_page)
+ENTRY(v5te_mc_copy_user_page)
 	stmfd	sp!, {r4, r5, lr}
 	mov	r5, r0
 	mov	r0, r1
@@ -62,7 +62,7 @@
  *  r0 = destination
  *  r1 = virtual user address of ultimate destination page
  */
-ENTRY(armv5te_clear_user_page)
+ENTRY(v5te_mc_clear_user_page)
 	str	lr, [sp, #-4]!
 	mov	r1, #PAGE_SZ/32
 	mov	r2, #0
@@ -77,3 +77,9 @@
 	subs	r1, r1, #1
 	bne	1b
 	ldr	pc, [sp], #4
+
+	.section ".text.init", #alloc, #execinstr
+
+ENTRY(v5te_mc_user_fns)
+	.long	v5te_mc_clear_user_page
+	.long	v5te_mc_copy_user_page
diff -Nru a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
--- a/arch/arm/mm/fault-armv.c	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mm/fault-armv.c	Fri Mar 15 17:51:02 2002
@@ -181,7 +181,7 @@
 static void
 make_coherent(struct vm_area_struct *vma, unsigned long addr, struct page *page)
 {
-	struct vm_area_struct *mpnt;
+	struct list_head *l;
 	struct mm_struct *mm = vma->vm_mm;
 	unsigned long pgoff = (addr - vma->vm_start) >> PAGE_SHIFT;
 	int aliases = 0;
@@ -191,9 +191,11 @@
 	 * space, then we need to handle them specially to maintain
 	 * cache coherency.
 	 */
-	for (mpnt = page->mapping->i_mmap_shared; mpnt;
-	     mpnt = mpnt->vm_next_share) {
+	list_for_each(l, &page->mapping->i_mmap_shared) {
+		struct vm_area_struct *mpnt;
 		unsigned long off;
+
+		mpnt = list_entry(l, struct vm_area_struct, shared);
 
 		/*
 		 * If this VMA is not in our MM, we can ignore it.
diff -Nru a/arch/arm/mm/init.c b/arch/arm/mm/init.c
--- a/arch/arm/mm/init.c	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/init.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mm/init.c
  *
- *  Copyright (C) 1995-2000 Russell King
+ *  Copyright (C) 1995-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -46,7 +46,7 @@
 #define TABLE_OFFSET	0
 #endif
 
-#define TABLE_SIZE	((TABLE_OFFSET + PTRS_PER_PTE) * sizeof(void *))
+#define TABLE_SIZE	((TABLE_OFFSET + PTRS_PER_PTE) * sizeof(pte_t))
 
 static unsigned long totalram_pages;
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
@@ -319,7 +319,7 @@
 	 * and can only be in node 0.
 	 */
 	reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
-			     PTRS_PER_PGD * sizeof(void *));
+			     PTRS_PER_PGD * sizeof(pgd_t));
 #endif
 	/*
 	 * And don't forget to reserve the allocator bitmap,
diff -Nru a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
--- a/arch/arm/mm/mm-armv.c	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/mm-armv.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mm/mm-armv.c
  *
- *  Copyright (C) 1998-2000 Russell King
+ *  Copyright (C) 1998-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -82,9 +82,6 @@
 	init_pgd = pgd_offset_k(0);
 
 	if (vectors_base() == 0) {
-		init_pmd = pmd_offset(init_pgd, 0);
-		init_pte = pte_offset(init_pmd, 0);
-
 		/*
 		 * This lock is here just to satisfy pmd_alloc and pte_lock
 		 */
@@ -172,11 +169,14 @@
 static inline void
 alloc_init_section(unsigned long virt, unsigned long phys, int prot)
 {
-	pmd_t pmd;
+	pmd_t *pmdp, pmd;
 
-	pmd_val(pmd) = phys | prot;
+	pmdp = pmd_offset(pgd_offset_k(virt), virt);
+	if (virt & (1 << PMD_SHIFT))
+		pmdp++;
 
-	set_pmd(pmd_offset(pgd_offset_k(virt), virt), pmd);
+	pmd_val(pmd) = phys | prot;
+	set_pmd(pmdp, pmd);
 }
 
 /*
@@ -189,18 +189,19 @@
 static inline void
 alloc_init_page(unsigned long virt, unsigned long phys, int domain, int prot)
 {
-	pmd_t *pmdp;
+	pmd_t *pmdp, pmd;
 	pte_t *ptep;
 
 	pmdp = pmd_offset(pgd_offset_k(virt), virt);
 
 	if (pmd_none(*pmdp)) {
-		pte_t *ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
-						      sizeof(pte_t));
+		ptep = alloc_bootmem_low_pages(2 * PTRS_PER_PTE *
+					       sizeof(pte_t));
 
-		ptep += PTRS_PER_PTE;
-
-		set_pmd(pmdp, __mk_pmd(ptep, PMD_TYPE_TABLE | PMD_DOMAIN(domain)));
+		pmd_val(pmd) = __pa(ptep) | PMD_TYPE_TABLE | PMD_DOMAIN(domain);
+		set_pmd(pmdp, pmd);
+		pmd_val(pmd) += 256 * sizeof(pte_t);
+		set_pmd(pmdp + 1, pmd);
 	}
 	ptep = pte_offset_kernel(pmdp, virt);
 
@@ -266,11 +267,11 @@
 		length -= PAGE_SIZE;
 	}
 
-	while (length >= PGDIR_SIZE) {
+	while (length >= (PGDIR_SIZE / 2)) {
 		alloc_init_section(virt, virt + off, prot_sect);
 
-		virt   += PGDIR_SIZE;
-		length -= PGDIR_SIZE;
+		virt   += (PGDIR_SIZE / 2);
+		length -= (PGDIR_SIZE / 2);
 	}
 
 	while (length >= PAGE_SIZE) {
@@ -462,42 +463,4 @@
 
 	for (node = 0; node < numnodes; node++)
 		free_unused_memmap_node(node, mi);
-}
-
-/*
- * PTE table allocation cache.
- *
- * This is a move away from our custom 2K page allocator.  We now use the
- * slab cache to keep track of these objects.
- *
- * With this, it is questionable as to whether the PGT cache gains us
- * anything.  We may be better off dropping the PTE stuff from our PGT
- * cache implementation.
- */
-kmem_cache_t *pte_cache;
-
-/*
- * The constructor gets called for each object within the cache when the
- * cache page is created.  Note that if slab tries to misalign the blocks,
- * we BUG() loudly.
- */
-static void pte_cache_ctor(void *pte, kmem_cache_t *cache, unsigned long flags)
-{
-	unsigned long block = (unsigned long)pte;
-
-	if (block & 2047)
-		BUG();
-
-	memzero(pte, 2 * PTRS_PER_PTE * sizeof(pte_t));
-	cpu_cache_clean_invalidate_range(block, block +
-			PTRS_PER_PTE * sizeof(pte_t), 0);
-}
-
-void __init pgtable_cache_init(void)
-{
-	pte_cache = kmem_cache_create("pte-cache",
-				2 * PTRS_PER_PTE * sizeof(pte_t), 0, 0,
-				pte_cache_ctor, NULL);
-	if (!pte_cache)
-		BUG();
 }
diff -Nru a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
--- a/arch/arm/mm/proc-arm1020.S	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/proc-arm1020.S	Fri Mar 15 17:51:01 2002
@@ -499,7 +499,9 @@
  */
 	.align	5
 ENTRY(cpu_arm1020_set_pte)
-	str	r1, [r0], #-1024		@ linux version
+	tst	r0, #2048
+	streq	r0, [r0, -r0]			@ BUG_ON
+	str	r1, [r0], #-2048		@ linux version
 
 	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
@@ -608,7 +610,7 @@
  */
 	.type	arm1020_processor_functions, #object
 arm1020_processor_functions:
-	.word	armv4t_early_abort
+	.word	v4t_early_abort
 	.word	cpu_arm1020_check_bugs
 	.word	cpu_arm1020_proc_init
 	.word	cpu_arm1020_proc_fin
@@ -635,10 +637,6 @@
 	.word	cpu_arm1020_set_pmd
 	.word	cpu_arm1020_set_pte
 
-	/* misc */
-	.word	armv4_clear_user_page
-	.word	armv4_copy_user_page
-
 	.size	arm1020_processor_functions, . - arm1020_processor_functions
 
 	.type	cpu_arm1020_info, #object
@@ -672,4 +670,5 @@
 	.long	cpu_arm1020_info
 	.long	arm1020_processor_functions
 	.long	v4wbi_tlb_fns
+	.long	v4_user_fns
 	.size	__arm1020_proc_info, . - __arm1020_proc_info
diff -Nru a/arch/arm/mm/proc-arm2,3.S b/arch/arm/mm/proc-arm2,3.S
--- a/arch/arm/mm/proc-arm2,3.S	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mm/proc-arm2,3.S	Fri Mar 15 17:51:03 2002
@@ -342,6 +342,7 @@
 		.long	cpu_arm2_info
 		.long	SYMBOL_NAME(arm2_processor_functions)
 		.long	0
+		.long	0
 
 		.long	0x41560250
 		.long	0xfffffff0
@@ -353,6 +354,7 @@
 		.long	cpu_arm250_info
 		.long	SYMBOL_NAME(arm250_processor_functions)
 		.long	0
+		.long	0
 
 		.long	0x41560300
 		.long	0xfffffff0
@@ -364,3 +366,5 @@
 		.long	cpu_arm3_info
 		.long	SYMBOL_NAME(arm3_processor_functions)
 		.long	0
+		.long	0
+
diff -Nru a/arch/arm/mm/proc-arm6,7.S b/arch/arm/mm/proc-arm6,7.S
--- a/arch/arm/mm/proc-arm6,7.S	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mm/proc-arm6,7.S	Fri Mar 15 17:51:03 2002
@@ -274,7 +274,9 @@
 		.align	5
 ENTRY(cpu_arm6_set_pte)
 ENTRY(cpu_arm7_set_pte)
-		str	r1, [r0], #-1024		@ linux version
+		tst	r0, #2048
+		streq	r0, [r0, -r0]			@ BUG_ON
+		str	r1, [r0], #-2048		@ linux version
 
 		eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
@@ -373,10 +375,6 @@
 		.word	cpu_arm6_set_pmd
 		.word	cpu_arm6_set_pte
 
-		/* other */
-		.word	armv3_clear_user_page
-		.word	armv3_copy_user_page
-
 		.size	arm6_processor_functions, . - arm6_processor_functions
 
 /*
@@ -412,10 +410,6 @@
 		.word	cpu_arm7_set_pmd
 		.word	cpu_arm7_set_pte
 
-		/* other */
-		.word	armv3_clear_user_page
-		.word	armv3_copy_user_page
-
 		.size	arm7_processor_functions, . - arm7_processor_functions
 
 		.type	cpu_arm6_info, #object
@@ -465,6 +459,7 @@
 		.long	cpu_arm6_info
 		.long	arm6_processor_functions
 		.long	v3_tlb_fns
+		.long	v3_user_fns
 		.size	__arm6_proc_info, . - __arm6_proc_info
 
 		.type	__arm610_proc_info, #object
@@ -479,6 +474,7 @@
 		.long	cpu_arm610_info
 		.long	arm6_processor_functions
 		.long	v3_tlb_fns
+		.long	v3_user_fns
 		.size	__arm610_proc_info, . - __arm610_proc_info
 
 		.type	__arm7_proc_info, #object
@@ -493,6 +489,7 @@
 		.long	cpu_arm7_info
 		.long	arm7_processor_functions
 		.long	v3_tlb_fns
+		.long	v3_user_fns
 		.size	__arm7_proc_info, . - __arm7_proc_info
 
 		.type	__arm710_proc_info, #object
@@ -507,4 +504,5 @@
 		.long	cpu_arm710_info
 		.long	arm7_processor_functions
 		.long	v3_tlb_fns
+		.long	v3_user_fns
 		.size	__arm710_proc_info, . - __arm710_proc_info
diff -Nru a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
--- a/arch/arm/mm/proc-arm720.S	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/proc-arm720.S	Fri Mar 15 17:51:01 2002
@@ -136,7 +136,9 @@
  */
 		.align	5
 ENTRY(cpu_arm720_set_pte)
-		str	r1, [r0], #-1024		@ linux version
+		tst	r0, #2048
+		streq	r0, [r0, -r0]			@ BUG_ON
+		str	r1, [r0], #-2048		@ linux version
 
 		eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
@@ -199,7 +201,7 @@
  */
 		.type	arm720_processor_functions, #object
 ENTRY(arm720_processor_functions)
-		.word	armv4t_late_abort
+		.word	v4t_late_abort
 		.word	cpu_arm720_check_bugs
 		.word	cpu_arm720_proc_init
 		.word	cpu_arm720_proc_fin
@@ -226,10 +228,6 @@
 		.word	cpu_arm720_set_pmd
 		.word	cpu_arm720_set_pte
 
-		/* misc */
-		.word	armv4_clear_user_page
-		.word	armv4_copy_user_page
-
 		.size	arm720_processor_functions, . - arm720_processor_functions
 
 		.type	cpu_arm720_info, #object
@@ -265,4 +263,5 @@
 		.long	cpu_arm720_info				@ info
 		.long	arm720_processor_functions
 		.long	v4_tlb_fns
+		.long	v4_user_fns
 		.size	__arm720_proc_info, . - __arm720_proc_info
diff -Nru a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
--- a/arch/arm/mm/proc-arm920.S	Fri Mar 15 17:51:01 2002
+++ b/arch/arm/mm/proc-arm920.S	Fri Mar 15 17:51:01 2002
@@ -420,7 +420,9 @@
  */
 	.align	5
 ENTRY(cpu_arm920_set_pte)
-	str	r1, [r0], #-1024		@ linux version
+	tst	r0, #2048
+	streq	r0, [r0, -r0]			@ BUG_ON
+	str	r1, [r0], #-2048		@ linux version
 
 	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
@@ -511,7 +513,7 @@
  */
 	.type	arm920_processor_functions, #object
 arm920_processor_functions:
-	.word	armv4t_early_abort
+	.word	v4t_early_abort
 	.word	cpu_arm920_check_bugs
 	.word	cpu_arm920_proc_init
 	.word	cpu_arm920_proc_fin
@@ -538,10 +540,6 @@
 	.word	cpu_arm920_set_pmd
 	.word	cpu_arm920_set_pte
 
-	/* misc */
-	.word	armv4_clear_user_page
-	.word	armv4_copy_user_page
-
 	.size	arm920_processor_functions, . - arm920_processor_functions
 
 	.type	cpu_arm920_info, #object
@@ -575,4 +573,5 @@
 	.long	cpu_arm920_info
 	.long	arm920_processor_functions
 	.long	v4wbi_tlb_fns
+	.long	v4_user_fns
 	.size	__arm920_proc_info, . - __arm920_proc_info
diff -Nru a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
--- a/arch/arm/mm/proc-arm922.S	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mm/proc-arm922.S	Fri Mar 15 17:51:02 2002
@@ -421,7 +421,9 @@
  */
 	.align	5
 ENTRY(cpu_arm922_set_pte)
-	str	r1, [r0], #-1024		@ linux version
+	tst	r0, #2048
+	streq	r0, [r0, -r0]			@ BUG_ON
+	str	r1, [r0], #-2048		@ linux version
 
 	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
@@ -512,7 +514,7 @@
  */
 	.type	arm922_processor_functions, #object
 arm922_processor_functions:
-	.word	armv4t_early_abort
+	.word	v4t_early_abort
 	.word	cpu_arm922_check_bugs
 	.word	cpu_arm922_proc_init
 	.word	cpu_arm922_proc_fin
@@ -539,10 +541,6 @@
 	.word	cpu_arm922_set_pmd
 	.word	cpu_arm922_set_pte
 
-	/* misc */
-	.word	armv4_clear_user_page
-	.word	armv4_copy_user_page
-
 	.size	arm922_processor_functions, . - arm922_processor_functions
 
 	.type	cpu_arm922_info, #object
@@ -576,4 +574,5 @@
 	.long	cpu_arm922_info
 	.long	arm922_processor_functions
 	.long	v4wbi_tlb_fns
+	.long	v4_user_fns
 	.size	__arm922_proc_info, . - __arm922_proc_info
diff -Nru a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
--- a/arch/arm/mm/proc-arm926.S	Fri Mar 15 17:51:00 2002
+++ b/arch/arm/mm/proc-arm926.S	Fri Mar 15 17:51:00 2002
@@ -443,7 +443,9 @@
  */
 	.align	5
 ENTRY(cpu_arm926_set_pte)
-	str	r1, [r0], #-1024		@ linux version
+	tst	r0, #2048
+	streq	r0, [r0, -r0]			@ BUG_ON
+	str	r1, [r0], #-2048		@ linux version
 
 	eor	r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
@@ -549,7 +551,7 @@
  */
 	.type	arm926_processor_functions, #object
 arm926_processor_functions:
-	.word	armv5ej_early_abort
+	.word	v5ej_early_abort
 	.word	cpu_arm926_check_bugs
 	.word	cpu_arm926_proc_init
 	.word	cpu_arm926_proc_fin
@@ -576,10 +578,6 @@
 	.word	cpu_arm926_set_pmd
 	.word	cpu_arm926_set_pte
 
-	/* misc */
-	.word	armv4_clear_user_page
-	.word	armv4_copy_user_page
-
 	.size	arm926_processor_functions, . - arm926_processor_functions
 
 	.type	cpu_arm926_info, #object
@@ -613,4 +611,5 @@
 	.long	cpu_arm926_info
 	.long	arm926_processor_functions
 	.long	v4wbi_tlb_fns
+	.long	v4_user_fns
 	.size	__arm926_proc_info, . - __arm926_proc_info
diff -Nru a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
--- a/arch/arm/mm/proc-sa110.S	Fri Mar 15 17:51:03 2002
+++ b/arch/arm/mm/proc-sa110.S	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/arch/arm/mm/proc-sa110.S
  *
- *  Copyright (C) 1997-2000 Russell King
+ *  Copyright (C) 1997-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -468,7 +468,9 @@
 	.align	5
 ENTRY(cpu_sa110_set_pte)
 ENTRY(cpu_sa1100_set_pte)
-	str	r1, [r0], #-1024		@ linux version
+	tst	r0, #2048
+	streq	r0, [r0, -r0]			@ BUG_ON
+	str	r1, [r0], #-2048		@ linux version
 
 	eor	r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
 
@@ -538,7 +540,7 @@
 
 	.type	sa110_processor_functions, #object
 ENTRY(sa110_processor_functions)
-	.word	armv4_early_abort
+	.word	v4_early_abort
 	.word	cpu_sa110_check_bugs
 	.word	cpu_sa110_proc_init
 	.word	cpu_sa110_proc_fin
@@ -565,10 +567,6 @@
 	.word	cpu_sa110_set_pmd
 	.word	cpu_sa110_set_pte
 
-	/* misc */
-	.word	armv4_clear_user_page
-	.word	armv4_copy_user_page
-
 	.size	sa110_processor_functions, . - sa110_processor_functions
 
 	.type	cpu_sa110_info, #object
@@ -610,10 +608,6 @@
 	.word	cpu_sa1100_set_pmd
 	.word	cpu_sa1100_set_pte
 
-	/* misc */
-	.word	armv4_mc_clear_user_page
-	.word	armv4_mc_copy_user_page
-
 	.size	sa1100_processor_functions, . - sa1100_processor_functions
 
 cpu_sa1100_info:
@@ -651,6 +645,7 @@
 	.long	cpu_sa110_info
 	.long	sa110_processor_functions
 	.long	v4wb_tlb_fns
+	.long	v4_user_fns
 	.size	__sa110_proc_info, . - __sa110_proc_info
 
 	.type	__sa1100_proc_info,#object
@@ -665,6 +660,7 @@
 	.long	cpu_sa1100_info
 	.long	sa1100_processor_functions
 	.long	v4wb_tlb_fns
+	.long	v4_mc_user_fns
 	.size	__sa1100_proc_info, . - __sa1100_proc_info
 
 	.type	__sa1110_proc_info,#object
@@ -679,4 +675,5 @@
 	.long	cpu_sa1110_info
 	.long	sa1100_processor_functions
 	.long	v4wb_tlb_fns
+	.long	v4_mc_user_fns
 	.size	__sa1110_proc_info, . - __sa1110_proc_info
diff -Nru a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
--- a/arch/arm/mm/proc-xscale.S	Fri Mar 15 17:51:02 2002
+++ b/arch/arm/mm/proc-xscale.S	Fri Mar 15 17:51:02 2002
@@ -602,7 +602,9 @@
  */
 	.align	5
 ENTRY(cpu_xscale_set_pte)
-	str	r1, [r0], #-1024		@ linux version
+	tst	r0, #2048
+	streq	r0, [r0, -r0]			@ BUG_ON
+	str	r1, [r0], #-2048		@ linux version
 
 	bic	r2, r1, #0xff0
 	orr	r2, r2, #PTE_TYPE_EXT		@ extended page
@@ -695,7 +697,7 @@
 
 	.type	xscale_processor_functions, #object
 ENTRY(xscale_processor_functions)
-	.word	armv4t_early_abort
+	.word	v4t_early_abort
 	.word	cpu_xscale_check_bugs
 	.word	cpu_xscale_proc_init
 	.word	cpu_xscale_proc_fin
@@ -722,10 +724,6 @@
 	.word	cpu_xscale_set_pmd
 	.word	cpu_xscale_set_pte
 
-	/* misc */
-	.word	armv5te_clear_user_page
-	.word	armv5te_copy_user_page
-
 	.size	xscale_processor_functions, . - xscale_processor_functions
 
 	.type	cpu_80200_info, #object
@@ -765,6 +763,7 @@
 	.long	cpu_80200_info
 	.long	xscale_processor_functions
 	.long	v4wbi_tlb_fns
+	.long	v5te_mc_user_fns
 	.size	__80200_proc_info, . - __80200_proc_info
 
 	.type	__pxa250_proc_info,#object
@@ -779,6 +778,7 @@
 	.long	cpu_pxa250_info
 	.long	xscale_processor_functions
 	.long	v4wbi_tlb_fns
+	.long	v5te_mc_user_fns
 	.size	__cotulla_proc_info, . - __cotulla_proc_info
 	.size	__pxa250_proc_info, . - __pxa250_proc_info
 
diff -Nru a/arch/cris/drivers/ide.c b/arch/cris/drivers/ide.c
--- a/arch/cris/drivers/ide.c	Fri Mar 15 17:51:02 2002
+++ b/arch/cris/drivers/ide.c	Fri Mar 15 17:51:02 2002
@@ -2,7 +2,7 @@
  *
  * Etrax specific IDE functions, like init and PIO-mode setting etc.
  * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
- * Copyright (c) 2000, 2001 Axis Communications AB 
+ * Copyright (c) 2000, 2001 Axis Communications AB
  *
  * Authors:    Bjorn Wesen        (initial version)
  *             Mikael Starvik     (pio setup stuff)
@@ -895,7 +895,14 @@
 
 /* ide.c calls this, but we don't need to do anything particular */
 
-int ide_release_dma (ide_hwif_t *hwif)
+/* Dear maintainer of this architecture please note that it would be a little
+ * more clever :-) to put this up into some header as static inline, so the
+ * spurious code below would just vanish.
+ *
+ * --- Marcin Dalecki
+ */
+
+void ide_release_dma (ide_hwif_t *hwif)
 {
-	return 1;
+	/* empty */
 }
diff -Nru a/arch/i386/Config.help b/arch/i386/Config.help
--- a/arch/i386/Config.help	Fri Mar 15 17:51:01 2002
+++ b/arch/i386/Config.help	Fri Mar 15 17:51:01 2002
@@ -649,33 +649,32 @@
   sending the processor to sleep and saving power.
 
 CONFIG_ACPI
-  ACPI/OSPM support for Linux is currently under development. As such,
-  this support is preliminary and EXPERIMENTAL.  Configuring ACPI
-  support enables kernel interfaces that allow higher level software
-  (OSPM) to manipulate ACPI defined hardware and software interfaces,
-  including the evaluation of ACPI control methods.  If unsure, choose
-  N here.  Note, this option will enlarge your kernel by about 120K.
+  Advanced Configuration and Power Interface (ACPI) support for 
+  Linux requires an ACPI compliant platform (hardware/firmware),
+  and assumes the presence of OS-directed configuration and power
+  management (OSPM) software.  This option will enlarge your 
+  kernel by about 70K.
 
-  This support requires an ACPI compliant platform (hardware/firmware).
-  If both ACPI and Advanced Power Management (APM) support are
-  configured, whichever is loaded first shall be used.
+  Linux ACPI provides a robust functional replacement for several 
+  legacy configuration and power management intefaces, including 
+  the Plug-and-Play BIOS specification (PnP BIOS), the 
+  MultiProcessor Specification (MPS), and the Advanced Power 
+  Management (APM) specification.  If both ACPI and APM support 
+  are configured, whichever is loaded first shall be used.
+  
+  The ACPI SourceForge project contains the latest source code, 
+  documentation, tools, mailing list subscription, and other 
+  information.  This project is available at:
+    <http://sourceforge.net/projects/acpi>
 
-  This code DOES NOT currently provide a complete OSPM implementation
-  -- it has not yet reached APM's level of functionality.  When fully
-  implemented, Linux ACPI/OSPM will provide a more robust functional
-  replacement for legacy configuration and power management
-  interfaces, including the Plug-and-Play BIOS specification (PnP
-  BIOS), the Multi-Processor Specification (MPS), and the Advanced
-  Power Management specification (APM).
+  Linux support for ACPI is based on Intel Corporation's ACPI
+  Component Architecture (ACPI CA).  For more information see:
+    <http://developer.intel.com/technology/iapc/acpi>
 
-  Linux support for ACPI/OSPM is based on Intel Corporation's ACPI
-  Component Architecture (ACPI CA). The latest ACPI CA source code,
-  documentation, debug builds, and implementation status information
-  can be downloaded from:
-  <http://developer.intel.com/technology/iapc/acpi/downloads.htm>.
-
-  The ACPI Sourceforge project may also be of interest:
-  <http://sf.net/projects/acpi/>
+  ACPI is an open industry specification co-developed by Compaq, 
+  Intel, Microsoft, Phoenix, and Toshiba.  The specification is 
+  available at:
+    <http://www.acpi.info>
 
 CONFIG_APM
   APM is a BIOS specification for saving power using several different
diff -Nru a/arch/i386/config.in b/arch/i386/config.in
--- a/arch/i386/config.in	Fri Mar 15 17:51:02 2002
+++ b/arch/i386/config.in	Fri Mar 15 17:51:02 2002
@@ -41,6 +41,7 @@
    define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y
    define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
    define_bool CONFIG_X86_PPRO_FENCE y
+   define_bool CONFIG_X86_F00F_BUG y
 else
    define_bool CONFIG_X86_WP_WORKS_OK y
    define_bool CONFIG_X86_INVLPG y
@@ -56,12 +57,14 @@
    define_bool CONFIG_X86_USE_STRING_486 y
    define_bool CONFIG_X86_ALIGNMENT_16 y
    define_bool CONFIG_X86_PPRO_FENCE y
+   define_bool CONFIG_X86_F00F_BUG y
 fi
 if [ "$CONFIG_M586" = "y" ]; then
    define_int  CONFIG_X86_L1_CACHE_SHIFT 5
    define_bool CONFIG_X86_USE_STRING_486 y
    define_bool CONFIG_X86_ALIGNMENT_16 y
    define_bool CONFIG_X86_PPRO_FENCE y
+   define_bool CONFIG_X86_F00F_BUG y
 fi
 if [ "$CONFIG_M586TSC" = "y" ]; then
    define_int  CONFIG_X86_L1_CACHE_SHIFT 5
@@ -69,6 +72,7 @@
    define_bool CONFIG_X86_ALIGNMENT_16 y
    define_bool CONFIG_X86_TSC y
    define_bool CONFIG_X86_PPRO_FENCE y
+   define_bool CONFIG_X86_F00F_BUG y
 fi
 if [ "$CONFIG_M586MMX" = "y" ]; then
    define_int  CONFIG_X86_L1_CACHE_SHIFT 5
@@ -77,6 +81,7 @@
    define_bool CONFIG_X86_TSC y
    define_bool CONFIG_X86_GOOD_APIC y
    define_bool CONFIG_X86_PPRO_FENCE y
+   define_bool CONFIG_X86_F00F_BUG y
 fi
 if [ "$CONFIG_M686" = "y" ]; then
    define_int  CONFIG_X86_L1_CACHE_SHIFT 5
@@ -203,6 +208,8 @@
 mainmenu_option next_comment
 comment 'General options'
 
+source drivers/acpi/Config.in
+
 # Visual Workstation support is utterly broken.
 # If you want to see it working mail an VW540 to hch@infradead.org 8)
 #bool 'SGI Visual Workstation support' CONFIG_VISWS
@@ -260,14 +267,6 @@
 tristate 'Kernel support for MISC binaries' CONFIG_BINFMT_MISC
 
 bool 'Power Management support' CONFIG_PM
-
-if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
-   dep_bool '  ACPI support' CONFIG_ACPI $CONFIG_PM
-   
-   if [ "$CONFIG_ACPI" != "n" ]; then
-      source drivers/acpi/Config.in
-   fi
-fi
 
 dep_tristate '  Advanced Power Management BIOS support' CONFIG_APM $CONFIG_PM
 if [ "$CONFIG_APM" != "n" ]; then
diff -Nru a/arch/i386/defconfig b/arch/i386/defconfig
--- a/arch/i386/defconfig	Fri Mar 15 17:51:01 2002
+++ b/arch/i386/defconfig	Fri Mar 15 17:51:01 2002
@@ -77,6 +77,11 @@
 #
 # General options
 #
+
+#
+# ACPI Support
+#
+# CONFIG_ACPI is not set
 CONFIG_X86_IO_APIC=y
 CONFIG_X86_LOCAL_APIC=y
 CONFIG_PCI=y
@@ -187,6 +192,7 @@
 # CONFIG_IP_MROUTE is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
+# CONFIG_VLAN_8021Q is not set
 
 #
 #  
@@ -214,7 +220,7 @@
 CONFIG_IDE=y
 
 #
-# IDE, ATA and ATAPI Block devices
+# ATA and ATAPI Block devices
 #
 CONFIG_BLK_DEV_IDE=y
 
@@ -249,16 +255,14 @@
 # CONFIG_BLK_DEV_ISAPNP is not set
 CONFIG_BLK_DEV_RZ1000=y
 CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEDMA_PCI_AUTO=y
 # CONFIG_IDEDMA_ONLYDISK is not set
 CONFIG_BLK_DEV_IDEDMA=y
 # CONFIG_IDEDMA_PCI_WIP is not set
-# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
 # CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_AEC62XX_TUNING is not set
 # CONFIG_BLK_DEV_ALI15X3 is not set
@@ -285,8 +289,8 @@
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_IDE_CHIPSETS is not set
-CONFIG_IDEDMA_AUTO=y
 # CONFIG_IDEDMA_IVB is not set
+CONFIG_IDEDMA_AUTO=y
 # CONFIG_DMA_NONPCI is not set
 CONFIG_BLK_DEV_IDE_MODES=y
 # CONFIG_BLK_DEV_ATARAID is not set
@@ -831,6 +835,7 @@
 # USB Device Class drivers
 #
 # CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
 # CONFIG_USB_BLUETOOTH is not set
 CONFIG_USB_STORAGE=y
 # CONFIG_USB_STORAGE_DEBUG is not set
diff -Nru a/arch/i386/kernel/Makefile b/arch/i386/kernel/Makefile
--- a/arch/i386/kernel/Makefile	Fri Mar 15 17:51:01 2002
+++ b/arch/i386/kernel/Makefile	Fri Mar 15 17:51:01 2002
@@ -36,9 +36,11 @@
 obj-$(CONFIG_X86_CPUID)		+= cpuid.o
 obj-$(CONFIG_MICROCODE)		+= microcode.o
 obj-$(CONFIG_APM)		+= apm.o
+obj-$(CONFIG_ACPI)		+= acpi.o
+obj-$(CONFIG_ACPI_SLEEP)	+= acpi_wakeup.o
 obj-$(CONFIG_SMP)		+= smp.o smpboot.o trampoline.o
 obj-$(CONFIG_X86_LOCAL_APIC)	+= mpparse.o apic.o nmi.o
-obj-$(CONFIG_X86_IO_APIC)	+= io_apic.o acpitable.o
+obj-$(CONFIG_X86_IO_APIC)	+= io_apic.o
 ifdef CONFIG_VISWS
 obj-y += setup-visws.o
 obj-$(CONFIG_X86_VISWS_APIC)	+= visws_apic.o
diff -Nru a/arch/i386/kernel/acpi.c b/arch/i386/kernel/acpi.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/i386/kernel/acpi.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,437 @@
+/*
+ *  acpi.c - Architecture-Specific Low-Level ACPI Support
+ *
+ *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
+ *  Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/stddef.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/bootmem.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <linux/acpi.h>
+#include <asm/mpspec.h>
+#include <asm/io.h>
+#include <asm/apic.h>
+#include <asm/apicdef.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+#include <asm/io_apic.h>
+
+
+#define PREFIX			"ACPI: "
+
+
+/* --------------------------------------------------------------------------
+                              Boot-time Configuration
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_ACPI_BOOT
+
+/*
+ * Use reserved fixmap pages for physical-to-virtual mappings of ACPI tables.
+ * Note that the same range is used for each table, so tables that need to
+ * persist should be memcpy'd.
+ */
+char *
+__acpi_map_table (
+	unsigned long	phys_addr,
+	unsigned long	size)
+{
+	unsigned long	base = 0;
+	unsigned long	mapped_phys = phys_addr;
+	unsigned long	offset = phys_addr & (PAGE_SIZE - 1);
+	unsigned long	mapped_size = PAGE_SIZE - offset;
+	unsigned long	avail_size = mapped_size + (PAGE_SIZE * FIX_ACPI_PAGES);
+	int		idx = FIX_ACPI_BEGIN;
+
+	if (!phys_addr || !size)
+		return NULL;
+
+	base = fix_to_virt(FIX_ACPI_BEGIN);
+
+	set_fixmap(idx, mapped_phys);
+
+	if (size > avail_size)
+		return NULL;
+
+	/* If the table doesn't map completely into the fist page... */
+	if (size > mapped_size) {
+		do {
+			/* Make sure we don't go past our range */
+			if (idx++ == FIX_ACPI_END)
+				return NULL;
+			mapped_phys = mapped_phys + PAGE_SIZE;
+			set_fixmap(idx, mapped_phys);
+			mapped_size = mapped_size + PAGE_SIZE;
+		} while (mapped_size < size);
+	}
+
+	return ((unsigned char *) base + offset);
+}
+
+
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static int total_cpus __initdata = 0;
+
+/* From mpparse.c */
+extern void __init MP_processor_info(struct mpc_config_processor *);
+
+int __init
+acpi_parse_lapic (
+	acpi_table_entry_header *header)
+{
+	struct acpi_table_lapic	*cpu = NULL;
+	struct mpc_config_processor proc_entry;
+
+	cpu = (struct acpi_table_lapic*) header;
+	if (!cpu)
+		return -EINVAL;
+
+	acpi_table_print_madt_entry(header);
+
+	if (!cpu->flags.enabled) {
+		printk(KERN_INFO "Processor #%d disabled\n", cpu->id);
+		return 0;
+	}
+
+	if (cpu->id >= MAX_APICS) {
+		printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
+			cpu->id, MAX_APICS);
+		return -ENODEV;
+	}
+
+	/*
+	 * Fill in the info we want to save.  Not concerned about
+	 * the processor ID.  Processor features aren't present in
+	 * the table.
+	 */
+	proc_entry.mpc_type = MP_PROCESSOR;
+	proc_entry.mpc_apicid = cpu->id;
+	proc_entry.mpc_cpuflag = CPU_ENABLED;
+	if (cpu->id == boot_cpu_physical_apicid) {
+		/* TBD: Circular reference trying to establish BSP */
+		proc_entry.mpc_cpuflag |= CPU_BOOTPROCESSOR;
+	}
+	proc_entry.mpc_cpufeature = (boot_cpu_data.x86 << 8)
+		| (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
+	proc_entry.mpc_featureflag = boot_cpu_data.x86_capability[0];
+	proc_entry.mpc_reserved[0] = 0;
+	proc_entry.mpc_reserved[1] = 0;
+	proc_entry.mpc_apicver = 0x10;	/* integrated APIC */
+
+	MP_processor_info(&proc_entry);
+
+	total_cpus++;
+
+	return 0;
+}
+
+
+int __init
+acpi_parse_lapic_addr_ovr (
+	acpi_table_entry_header *header)
+{
+	struct acpi_table_lapic_addr_ovr *lapic_addr_ovr = NULL;
+
+	lapic_addr_ovr = (struct acpi_table_lapic_addr_ovr*) header;
+	if (!lapic_addr_ovr)
+		return -EINVAL;
+
+	/* TBD: Support local APIC address override entries */
+
+	return 0;
+}
+
+
+int __init
+acpi_parse_lapic_nmi (
+	acpi_table_entry_header *header)
+{
+	struct acpi_table_lapic_nmi *lacpi_nmi = NULL;
+
+	lacpi_nmi = (struct acpi_table_lapic_nmi*) header;
+	if (!lacpi_nmi)
+		return -EINVAL;
+
+	acpi_table_print_madt_entry(header);
+
+	/* TBD: Support local APIC NMI entries */
+
+	return 0;
+}
+
+#endif /*CONFIG_X86_LOCAL_APIC*/
+
+
+#ifdef CONFIG_X86_IO_APIC
+
+int __init
+acpi_parse_ioapic (
+	acpi_table_entry_header *header)
+{
+	struct acpi_table_ioapic *ioapic = NULL;
+	
+	ioapic = (struct acpi_table_ioapic*) header;
+	if (!ioapic)
+		return -EINVAL;
+
+	acpi_table_print_madt_entry(header);
+
+	/* TBD: Support ioapic entries */
+
+	return 0;
+}
+
+#endif /*CONFIG_X86_IO_APIC*/
+
+
+int __init
+acpi_parse_madt (
+	unsigned long		phys_addr,
+	unsigned long		size)
+{
+	struct acpi_table_madt	*madt = NULL;
+
+	if (!phys_addr || !size)
+		return -EINVAL;
+
+	madt = (struct acpi_table_madt *) __acpi_map_table(phys_addr, size);
+	if (!madt) {
+		printk(KERN_WARNING PREFIX "Unable to map MADT\n");
+		return -ENODEV;
+	}
+
+#ifdef CONFIG_X86_LOCAL_APIC
+	if (madt->lapic_address)
+		mp_lapic_addr = madt->lapic_address;
+	else
+		mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
+#endif /*CONFIG_X86_LOCAL_APIC*/
+
+	printk(KERN_INFO PREFIX "Local APIC address 0x%08x\n",
+		madt->lapic_address);
+
+	return 0;
+}
+
+
+static unsigned long __init
+acpi_scan_rsdp (
+	unsigned long		start,
+	unsigned long		length)
+{
+	unsigned long		offset = 0;
+	unsigned long		sig_len = sizeof("RSD PTR ") - 1;
+
+	/*
+	 * Scan all 16-byte boundaries of the physical memory region for the
+	 * RSDP signature.
+	 */
+	for (offset = 0; offset < length; offset += 16) {
+		if (0 != strncmp((char *) (start + offset), "RSD PTR ", sig_len))
+			continue;
+		return (start + offset);
+	}
+
+	return 0;
+}
+
+
+int __init
+acpi_find_rsdp (
+	unsigned long		*rsdp_phys)
+{
+	if (!rsdp_phys)
+		return -EINVAL;
+
+	/*
+	 * Scan memory looking for the RSDP signature. First search EBDA (low
+	 * memory) paragraphs and then search upper memory (E0000-FFFFF).
+	 */
+	(*rsdp_phys) = acpi_scan_rsdp (0, 0x400);
+	if (!(*rsdp_phys))
+		(*rsdp_phys) = acpi_scan_rsdp (0xE0000, 0xFFFFF);
+
+	if (!(*rsdp_phys))
+		return -ENODEV;
+
+	return 0;
+}
+
+
+#endif /*CONFIG_ACPI_BOOT*/
+
+
+/* --------------------------------------------------------------------------
+                            PCI Interrupt Routing Support
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_ACPI_PCI
+int __init
+acpi_get_interrupt_model (
+	int		*type)
+{
+	if (!type)
+		return -EINVAL;
+
+#ifdef CONFIG_X86_IO_APIC
+	if (io_apic_assign_pci_irqs)
+		*type = ACPI_PCI_ROUTING_IOAPIC;
+	else
+#endif
+		*type = ACPI_PCI_ROUTING_PIC;
+
+	return 0;
+}
+#endif
+
+
+/* --------------------------------------------------------------------------
+                              Low-Level Sleep Support
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_ACPI_SLEEP
+
+#define DEBUG
+
+#ifdef DEBUG
+#include <linux/serial.h>
+#endif
+
+/* address in low memory of the wakeup routine. */
+unsigned long acpi_wakeup_address = 0;
+
+/* new page directory that we will be using */
+static pmd_t *pmd;
+
+/* saved page directory */
+static pmd_t saved_pmd;
+
+/* page which we'll use for the new page directory */
+static pte_t *ptep;
+
+extern unsigned long FASTCALL(acpi_copy_wakeup_routine(unsigned long));
+
+/*
+ * acpi_create_identity_pmd
+ *
+ * Create a new, identity mapped pmd.
+ *
+ * Do this by creating new page directory, and marking all the pages as R/W
+ * Then set it as the new Page Middle Directory.
+ * And, of course, flush the TLB so it takes effect.
+ *
+ * We save the address of the old one, for later restoration.
+ */
+static void acpi_create_identity_pmd (void)
+{
+	pgd_t *pgd;
+	int i;
+
+	ptep = (pte_t*)__get_free_page(GFP_KERNEL);
+
+	/* fill page with low mapping */
+	for (i = 0; i < PTRS_PER_PTE; i++)
+		set_pte(ptep + i, mk_pte_phys(i << PAGE_SHIFT, PAGE_SHARED));
+
+	pgd = pgd_offset(current->active_mm, 0);
+	pmd = pmd_alloc(current->mm,pgd, 0);
+
+	/* save the old pmd */
+	saved_pmd = *pmd;
+
+	/* set the new one */
+	set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(ptep)));
+
+	/* flush the TLB */
+	local_flush_tlb();
+}
+
+/*
+ * acpi_restore_pmd
+ *
+ * Restore the old pmd saved by acpi_create_identity_pmd and
+ * free the page that said function alloc'd
+ */
+static void acpi_restore_pmd (void)
+{
+	set_pmd(pmd, saved_pmd);
+	local_flush_tlb();
+	free_page((unsigned long)ptep);
+}
+
+/**
+ * acpi_save_state_mem - save kernel state
+ *
+ * Create an identity mapped page table and copy the wakeup routine to
+ * low memory.
+ */
+int acpi_save_state_mem (void)
+{
+	acpi_create_identity_pmd();
+	acpi_copy_wakeup_routine(acpi_wakeup_address);
+
+	return 0;
+}
+
+/**
+ * acpi_save_state_disk - save kernel state to disk
+ *
+ */
+int acpi_save_state_disk (void)
+{
+	return 1;
+}
+
+/*
+ * acpi_restore_state
+ */
+void acpi_restore_state_mem (void)
+{
+	acpi_restore_pmd();
+}
+
+/**
+ * acpi_reserve_bootmem - do _very_ early ACPI initialisation
+ *
+ * We allocate a page in low memory for the wakeup
+ * routine for when we come back from a sleep state. The
+ * runtime allocator allows specification of <16M pages, but not
+ * <1M pages.
+ */
+void __init acpi_reserve_bootmem(void)
+{
+	acpi_wakeup_address = (unsigned long)alloc_bootmem_low(PAGE_SIZE);
+	printk(KERN_DEBUG "ACPI: have wakeup address 0x%8.8lx\n", acpi_wakeup_address);
+}
+
+#endif /*CONFIG_ACPI_SLEEP*/
+
diff -Nru a/arch/i386/kernel/acpi_wakeup.S b/arch/i386/kernel/acpi_wakeup.S
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/i386/kernel/acpi_wakeup.S	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,137 @@
+
+.text
+#include <linux/linkage.h>
+#include <asm/segment.h>
+
+
+ALIGN
+wakeup_start:
+wakeup_code:
+	wakeup_code_start = .
+	.code16
+
+	cli
+	cld
+
+	# setup data segment
+	movw	%cs, %ax
+
+	addw	$(wakeup_data - wakeup_code) >> 4, %ax
+	movw	%ax, %ds
+
+	# set up page table
+	movl	(real_save_cr3 - wakeup_data), %eax
+	movl	%eax, %cr3
+
+	# make sure %cr4 is set correctly (features, etc)
+	movl	(real_save_cr4 - wakeup_data), %eax
+	movl	%eax, %cr4
+
+	# need a gdt
+	lgdt	real_save_gdt - wakeup_data
+
+	movl	%cr0, %eax
+	orl     $0x80000001, %eax
+	movl	%eax, %cr0
+
+	ljmpl	$__KERNEL_CS,$SYMBOL_NAME(wakeup_pmode_return)
+
+	.code32
+	ALIGN
+
+.org	0x100
+wakeup_data:
+		.word 0
+real_save_gdt:	.word 0
+		.long 0
+real_save_cr3:	.long 0
+real_save_cr4:	.long 0
+
+.org	0x300
+wakeup_stack:
+wakeup_end:
+
+wakeup_pmode_return:
+	# restore data segment
+	movl	$__KERNEL_DS, %eax
+	movw	%ax, %ds
+	movw	%ax, %es
+
+	# and restore the stack
+	movw	%ax, %ss
+	movl	saved_esp, %esp
+
+	# restore other segment registers
+	xorl	%eax, %eax
+	movw	%ax, %fs
+	movw	%ax, %gs
+
+	# reload the gdt, as we need the full 32 bit address
+	lgdt	saved_gdt
+	lidt	saved_idt
+	lldt	saved_ldt
+
+	# restore the other general registers
+	movl	saved_ebx, %ebx
+	movl	saved_edi, %edi
+	movl	saved_esi, %esi
+	movl	saved_ebp, %ebp
+
+	# jump to place where we left off
+	movl	saved_eip,%eax
+	jmp	*%eax
+
+##
+# acpi_copy_wakeup_routine
+#
+# Copy the above routine to low memory.
+#
+# Parameters:
+# %eax:	place to copy wakeup routine to
+#
+# Returned address is location of code in low memory (past data and stack)
+#
+ENTRY(acpi_copy_wakeup_routine)
+
+	pushl	%esi
+	pushl	%edi
+
+	sgdt	saved_gdt
+	sidt	saved_idt
+	sldt	saved_ldt
+	str	saved_tss
+
+	movl	%eax, %edi
+	leal	wakeup_start, %esi
+	movl	$(wakeup_end - wakeup_start) >> 2, %ecx
+
+	rep ;  movsl
+
+	movl    %cr3, %edx
+	movl    %edx, real_save_cr3 - wakeup_start (%eax)
+	movl    %cr4, %edx
+	movl    %edx, real_save_cr4 - wakeup_start (%eax)
+	sgdt    real_save_gdt - wakeup_start (%eax)
+
+	# restore the regs we used
+	popl	%edi
+	popl	%esi
+	ret
+
+
+.data
+ALIGN
+# saved registers
+saved_gdt:	.long	0,0
+saved_idt:	.long	0,0
+saved_ldt:	.long	0
+saved_tss:	.long	0
+saved_cr0:	.long	0
+
+ENTRY(saved_ebp)	.long	0
+ENTRY(saved_esi)	.long	0
+ENTRY(saved_edi)	.long	0
+ENTRY(saved_ebx)	.long	0
+
+ENTRY(saved_eip)	.long	0
+ENTRY(saved_esp)	.long	0
diff -Nru a/arch/i386/kernel/acpitable.c b/arch/i386/kernel/acpitable.c
--- a/arch/i386/kernel/acpitable.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,550 +0,0 @@
-/*
- *  acpitable.c - IA32-specific ACPI boot-time initialization (Revision: 1)
- *
- *  Copyright (C) 1999 Andrew Henroid
- *  Copyright (C) 2001 Richard Schaal
- *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
- *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
- *  Copyright (C) 2001 Arjan van de Ven <arjanv@redhat.com>
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- * $Id: acpitable.c,v 1.7 2001/11/04 12:21:18 fenrus Exp $
- */
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/stddef.h>
-#include <linux/slab.h>
-#include <linux/pci.h>
-#include <asm/mpspec.h>
-#include <asm/io.h>
-#include <asm/apic.h>
-#include <asm/apicdef.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-
-#include "acpitable.h"
-
-static acpi_table_handler acpi_boot_ops[ACPI_TABLE_COUNT];
-
-
-static unsigned char __init
-acpi_checksum(void *buffer, int length)
-{
-	int i;
-	unsigned char *bytebuffer;
-	unsigned char sum = 0;
-
-	if (!buffer || length <= 0)
-		return 0;
-
-	bytebuffer = (unsigned char *) buffer;
-
-	for (i = 0; i < length; i++)
-		sum += *(bytebuffer++);
-
-	return sum;
-}
-
-static void __init
-acpi_print_table_header(acpi_table_header * header)
-{
-	if (!header)
-		return;
-
-	printk(KERN_INFO "ACPI table found: %.4s v%d [%.6s %.8s %d.%d]\n",
-	       header->signature, header->revision, header->oem_id,
-	       header->oem_table_id, header->oem_revision >> 16,
-	       header->oem_revision & 0xffff);
-
-	return;
-}
-
-/*******************************************************************************
- *
- * FUNCTION:    acpi_tb_scan_memory_for_rsdp
- *
- * PARAMETERS:  address       - Starting pointer for search
- *              length        - Maximum length to search
- *
- * RETURN:      Pointer to the RSDP if found and valid, otherwise NULL.
- *
- * DESCRIPTION: Search a block of memory for the RSDP signature
- *
- ******************************************************************************/
-
-static void *__init
-acpi_tb_scan_memory_for_rsdp(void *address, int length)
-{
-	u32 offset;
-
-	if (length <= 0)
-		return NULL;
-
-	/* Search from given start addr for the requested length  */
-
-	offset = 0;
-
-	while (offset < length) {
-		/* The signature must match and the checksum must be correct */
-		if (strncmp(address, RSDP_SIG, sizeof(RSDP_SIG) - 1) == 0 &&
-		    acpi_checksum(address, RSDP_CHECKSUM_LENGTH) == 0) {
-			/* If so, we have found the RSDP */
-			printk(KERN_INFO "ACPI: RSDP located at physical address %p\n",
-			       address);
-			return address;
-		}
-		offset += RSDP_SCAN_STEP;
-		address += RSDP_SCAN_STEP;
-	}
-
-	/* Searched entire block, no RSDP was found */
-	printk(KERN_INFO "ACPI: Searched entire block, no RSDP was found.\n");
-	return NULL;
-}
-
-/*******************************************************************************
- *
- * FUNCTION:    acpi_find_root_pointer
- *
- * PARAMETERS:  none
- *
- * RETURN:      physical address of the RSDP 
- *
- * DESCRIPTION: Search lower 1_mbyte of memory for the root system descriptor
- *              pointer structure.  If it is found, set *RSDP to point to it.
- *
- *              NOTE: The RSDP must be either in the first 1_k of the Extended
- *              BIOS Data Area or between E0000 and FFFFF (ACPI 1.0 section
- *              5.2.2; assertion #421).
- *
- ******************************************************************************/
-
-static struct acpi_table_rsdp * __init
-acpi_find_root_pointer(void)
-{
-	struct acpi_table_rsdp * rsdp;
-
-	/*
-	 * Physical address is given
-	 */
-	/*
-	 * Region 1) Search EBDA (low memory) paragraphs
-	 */
-	rsdp = acpi_tb_scan_memory_for_rsdp(__va(LO_RSDP_WINDOW_BASE),
-					 LO_RSDP_WINDOW_SIZE);
-
-	if (rsdp)
-		return rsdp;
-
-	/*
-	 * Region 2) Search upper memory: 16-byte boundaries in E0000h-F0000h
-	 */
-	rsdp = acpi_tb_scan_memory_for_rsdp(__va(HI_RSDP_WINDOW_BASE),
-					       HI_RSDP_WINDOW_SIZE);
-
-	
-					     
-	if (rsdp)
-		return rsdp;
-
-	printk(KERN_ERR "ACPI: System description tables not found\n");
-	return NULL;
-}
-
-
-/*
- * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_0,
- * to map the target physical address. The problem is that set_fixmap()
- * provides a single page, and it is possible that the page is not
- * sufficient.
- * By using this area, we can map up to MAX_IO_APICS pages temporarily,
- * i.e. until the next __va_range() call.
- */
-static __inline__ char *
-__va_range(unsigned long phys, unsigned long size)
-{
-	unsigned long base, offset, mapped_size, mapped_phys = phys;
-	int idx = FIX_IO_APIC_BASE_0;
-
-	offset = phys & (PAGE_SIZE - 1);
-	mapped_size = PAGE_SIZE - offset;
-	set_fixmap(idx, mapped_phys);
-	base = fix_to_virt(FIX_IO_APIC_BASE_0);
-
-	/*
-	 * Most cases can be covered by the below.
-	 */
-	if (mapped_size >= size)
-		return ((unsigned char *) base + offset);
-
-	dprintk("__va_range: mapping more than a single page, size = 0x%lx\n",
-		size);
-
-	do {
-		if (idx++ == FIX_IO_APIC_BASE_END)
-			return 0;	/* cannot handle this */
-		mapped_phys = mapped_phys + PAGE_SIZE;
-		set_fixmap(idx, mapped_phys);
-		mapped_size = mapped_size + PAGE_SIZE;
-	} while (mapped_size < size);
-
-	return ((unsigned char *) base + offset);
-}
-
-static int __init acpi_tables_init(void)
-{
-	int result = -ENODEV;
-	acpi_table_header *header = NULL;
-	struct acpi_table_rsdp *rsdp = NULL;
-	struct acpi_table_rsdt *rsdt = NULL;
-	struct acpi_table_rsdt saved_rsdt;
-	int tables = 0;
-	int type = 0;
-	int i = 0;
-
-
-	rsdp = (struct acpi_table_rsdp *) acpi_find_root_pointer();
-
-	if (!rsdp)
-		return -ENODEV;
-		
-	printk(KERN_INFO "%.8s v%d [%.6s]\n", rsdp->signature, rsdp->revision,
-	       rsdp->oem_id);
-	       
-	if (strncmp(rsdp->signature, RSDP_SIG,strlen(RSDP_SIG))) {
-		printk(KERN_WARNING "RSDP table signature incorrect\n");
-		return -EINVAL;
-	}
-
-	rsdt = (struct acpi_table_rsdt *)
-	    __va_range(rsdp->rsdt_address, sizeof(struct acpi_table_rsdt));
-
-	if (!rsdt) {
-		printk(KERN_WARNING "ACPI: Invalid root system description tables (RSDT)\n");
-		return -ENODEV;
-	}
-	
-	header = & rsdt->header;
-	acpi_print_table_header(header);
-	
-	if (strncmp(header->signature, RSDT_SIG, strlen(RSDT_SIG))) {
-		printk(KERN_WARNING "ACPI: RSDT signature incorrect\n");
-		return -ENODEV;
-	}
-		
-	/* 
-	 * The number of tables is computed by taking the 
-	 * size of all entries (header size minus total 
-	 * size of RSDT) divided by the size of each entry
-	 * (4-byte table pointers).
-	 */
-	tables = (header->length - sizeof(acpi_table_header)) / 4;
-		    
-	memcpy(&saved_rsdt, rsdt, sizeof(saved_rsdt));
-
-	if (saved_rsdt.header.length > sizeof(saved_rsdt)) {
-		printk(KERN_WARNING "ACPI: Too big length in RSDT: %d\n", saved_rsdt.header.length);
-		return -ENODEV;
-	}
-
-	for (i = 0; i < tables; i++) {
-
-		header = (acpi_table_header *)
-			    __va_range(saved_rsdt.entry[i],
-				       sizeof(acpi_table_header));
-
-		if (!header)
-			break;
-
-		acpi_print_table_header(header);
-		
-		if (acpi_checksum(header,header->length)) {
-			printk(KERN_WARNING "ACPI %s has invalid checksum\n", 
-				acpi_table_signatures[i]);
-			continue;
-		}
-		
-		for (type = 0; type < ACPI_TABLE_COUNT; type++)
-			if (!strncmp((char *) &header->signature,
-			     acpi_table_signatures[type],strlen(acpi_table_signatures[type])))
-				break;
-
-		if (type >= ACPI_TABLE_COUNT) {
-			printk(KERN_WARNING "ACPI: Unsupported table %.4s\n",
-			       header->signature);
-			continue;
-		}
-
-
-		if (!acpi_boot_ops[type])
-			continue;
-			
-		result = acpi_boot_ops[type] (header,
-						 (unsigned long) saved_rsdt.
-						 entry[i]);
-	}
-
-	return result;
-}
-
-static int total_cpus __initdata = 0;
-int have_acpi_tables;
-
-extern void __init MP_processor_info(struct mpc_config_processor *);
-
-static void __init
-acpi_parse_lapic(struct acpi_table_lapic *local_apic)
-{
-	struct mpc_config_processor proc_entry;
-	int ix = 0;
-
-	if (!local_apic)
-		return;
-
-	printk(KERN_INFO "LAPIC (acpi_id[0x%04x] id[0x%x] enabled[%d])\n",
-		local_apic->acpi_id, local_apic->id, local_apic->flags.enabled);
-
-	printk(KERN_INFO "CPU %d (0x%02x00)", total_cpus, local_apic->id);
-
-	if (local_apic->flags.enabled) {
-		printk(" enabled");
-		ix = local_apic->id;
-		if (ix >= MAX_APICS) {
-			printk(KERN_WARNING
-			       "Processor #%d INVALID - (Max ID: %d).\n", ix,
-			       MAX_APICS);
-			return;
-		}
-		/* 
-		 * Fill in the info we want to save.  Not concerned about 
-		 * the processor ID.  Processor features aren't present in 
-		 * the table.
-		 */
-		proc_entry.mpc_type = MP_PROCESSOR;
-		proc_entry.mpc_apicid = local_apic->id;
-		proc_entry.mpc_cpuflag = CPU_ENABLED;
-		if (proc_entry.mpc_apicid == boot_cpu_physical_apicid) {
-			printk(" (BSP)");
-			proc_entry.mpc_cpuflag |= CPU_BOOTPROCESSOR;
-		}
-		proc_entry.mpc_cpufeature =
-		    (boot_cpu_data.x86 << 8) | 
-		    (boot_cpu_data.x86_model << 4) | 
-		     boot_cpu_data.x86_mask;
-		proc_entry.mpc_featureflag = boot_cpu_data.x86_capability[0];
-		proc_entry.mpc_reserved[0] = 0;
-		proc_entry.mpc_reserved[1] = 0;
-		proc_entry.mpc_apicver = 0x10;	/* integrated APIC */
-		MP_processor_info(&proc_entry);
-	} else {
-		printk(" disabled");
-	}
-	printk("\n");
-
-	total_cpus++;
-	return;
-}
-
-static void __init
-acpi_parse_ioapic(struct acpi_table_ioapic *ioapic)
-{
-
-	if (!ioapic)
-		return;
-
-	printk(KERN_INFO
-	       "IOAPIC (id[0x%x] address[0x%x] global_irq_base[0x%x])\n",
-	       ioapic->id, ioapic->address, ioapic->global_irq_base);
-
-	if (nr_ioapics >= MAX_IO_APICS) {
-		printk(KERN_WARNING
-		       "Max # of I/O APICs (%d) exceeded (found %d).\n",
-		       MAX_IO_APICS, nr_ioapics);
-/*		panic("Recompile kernel with bigger MAX_IO_APICS!\n");   */
-	}
-}
-
-
-/* Interrupt source overrides inform the machine about exceptions
-   to the normal "PIC" mode interrupt routing */
-   
-static void __init
-acpi_parse_int_src_ovr(struct acpi_table_int_src_ovr *intsrc)
-{
-	if (!intsrc)
-		return;
-
-	printk(KERN_INFO
-	       "INT_SRC_OVR (bus[%d] irq[0x%x] global_irq[0x%x] polarity[0x%x] trigger[0x%x])\n",
-	       intsrc->bus, intsrc->bus_irq, intsrc->global_irq,
-	       intsrc->flags.polarity, intsrc->flags.trigger);
-}
-
-/*
- * At this point, we look at the interrupt assignment entries in the MPS
- * table.
- */ 
- 
-static void __init acpi_parse_nmi_src(struct acpi_table_nmi_src *nmisrc)
-{
-	if (!nmisrc)
-		return;
-
-	printk(KERN_INFO
-	       "NMI_SRC (polarity[0x%x] trigger[0x%x] global_irq[0x%x])\n",
-	       nmisrc->flags.polarity, nmisrc->flags.trigger,
-	       nmisrc->global_irq);
-
-}
-static void __init
-acpi_parse_lapic_nmi(struct acpi_table_lapic_nmi *localnmi)
-{
-	if (!localnmi)
-		return;
-
-	printk(KERN_INFO
-	       "LAPIC_NMI (acpi_id[0x%04x] polarity[0x%x] trigger[0x%x] lint[0x%x])\n",
-	       localnmi->acpi_id, localnmi->flags.polarity,
-	       localnmi->flags.trigger, localnmi->lint);
-}
-static void __init
-acpi_parse_lapic_addr_ovr(struct acpi_table_lapic_addr_ovr *lapic_addr_ovr)
-{
-	if (!lapic_addr_ovr)
-		return;
-
-	printk(KERN_INFO "LAPIC_ADDR_OVR (address[0x%lx])\n",
-	       (unsigned long) lapic_addr_ovr->address);
-
-}
-
-static void __init
-acpi_parse_plat_int_src(struct acpi_table_plat_int_src *plintsrc)
-{
-	if (!plintsrc)
-		return;
-
-	printk(KERN_INFO
-	       "PLAT_INT_SRC (polarity[0x%x] trigger[0x%x] type[0x%x] id[0x%04x] eid[0x%x] iosapic_vector[0x%x] global_irq[0x%x]\n",
-	       plintsrc->flags.polarity, plintsrc->flags.trigger,
-	       plintsrc->type, plintsrc->id, plintsrc->eid,
-	       plintsrc->iosapic_vector, plintsrc->global_irq);
-}
-static int __init
-acpi_parse_madt(acpi_table_header * header, unsigned long phys)
-{
-
-	struct acpi_table_madt *madt;	    
-	acpi_madt_entry_header *entry_header;
-	int table_size;
-	
-	madt = (struct acpi_table_madt *) __va_range(phys, header->length);
-
-	if (!madt)
-		return -EINVAL;
-
-	table_size = (int) (header->length - sizeof(*madt));
-	entry_header =
-	    (acpi_madt_entry_header *) ((void *) madt + sizeof(*madt));
-
-	while (entry_header && (table_size > 0)) {
-		switch (entry_header->type) {
-		case ACPI_MADT_LAPIC:
-			acpi_parse_lapic((struct acpi_table_lapic *)
-					 entry_header);
-			break;
-		case ACPI_MADT_IOAPIC:
-			acpi_parse_ioapic((struct acpi_table_ioapic *)
-					  entry_header);
-			break;
-		case ACPI_MADT_INT_SRC_OVR:
-			acpi_parse_int_src_ovr((struct acpi_table_int_src_ovr *)
-					       entry_header);
-			break;
-		case ACPI_MADT_NMI_SRC:
-			acpi_parse_nmi_src((struct acpi_table_nmi_src *)
-					   entry_header);
-			break;
-		case ACPI_MADT_LAPIC_NMI:
-			acpi_parse_lapic_nmi((struct acpi_table_lapic_nmi *)
-					     entry_header);
-			break;
-		case ACPI_MADT_LAPIC_ADDR_OVR:
-			acpi_parse_lapic_addr_ovr((struct
-						   acpi_table_lapic_addr_ovr *)
-						  entry_header);
-			break;
-		case ACPI_MADT_PLAT_INT_SRC:
-			acpi_parse_plat_int_src((struct acpi_table_plat_int_src
-						 *) entry_header);
-			break;
-		default:
-			printk(KERN_WARNING
-			       "Unsupported MADT entry type 0x%x\n",
-			       entry_header->type);
-			break;
-		}
-		table_size -= entry_header->length;
-		entry_header =
-		    (acpi_madt_entry_header *) ((void *) entry_header +
-						entry_header->length);
-	}
-
-	if (!total_cpus) {
-		printk("ACPI: No Processors found in the APCI table.\n");
-		return -EINVAL;
-	}
-
-	printk(KERN_INFO "%d CPUs total\n", total_cpus);
-
-	if (madt->lapic_address)
-		mp_lapic_addr = madt->lapic_address;
-	else
-		mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
-
-	printk(KERN_INFO "Local APIC address %x\n", madt->lapic_address);
-
-	return 0;
-}
-
-extern int enable_acpi_smp_table;
-
-/*
- * Configure the processor info using MADT in the ACPI tables. If we fail to
- * configure that, then we use the MPS tables.
- */
-void __init
-config_acpi_tables(void)
-{
-
-	memset(&acpi_boot_ops, 0, sizeof(acpi_boot_ops));
-	acpi_boot_ops[ACPI_APIC] = acpi_parse_madt;
-
-	/*
-	 * Only do this when requested, either because of CPU/Bios type or from the command line
-	 */
-
-	if (enable_acpi_smp_table && !acpi_tables_init()) {
-		have_acpi_tables = 1;
-		printk("Enabling the CPU's according to the ACPI table\n");
-	}
-}
diff -Nru a/arch/i386/kernel/acpitable.h b/arch/i386/kernel/acpitable.h
--- a/arch/i386/kernel/acpitable.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,260 +0,0 @@
-/*
- *  acpitable.c - IA32-specific ACPI boot-time initialization (Revision: 1)
- *
- *  Copyright (C) 1999 Andrew Henroid
- *  Copyright (C) 2001 Richard Schaal
- *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
- *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
- *  Copyright (C) 2001 Arjan van de Ven <arjanv@redhat.com>
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- *
- * $Id: acpitable.h,v 1.3 2001/11/03 22:41:34 fenrus Exp $
- */
-
-/*
- * The following codes are cut&pasted from drivers/acpi. Part of the code
- * there can be not updated or delivered yet.
- * To avoid conflicts when CONFIG_ACPI is defined, the following codes are
- * modified so that they are self-contained in this file.
- * -- jun
- */
- 
-#ifndef _HEADER_ACPITABLE_H_
-#define _HEADER_ACPITABLE_H_
-
-#define dprintk printk
-typedef unsigned int ACPI_TBLPTR;
-
-typedef struct {		/* ACPI common table header */
-	char signature[4];	/* identifies type of table */
-	u32 length;		/* length of table,
-				   in bytes, * including header */
-	u8 revision;		/* specification minor version # */
-	u8 checksum;		/* to make sum of entire table == 0 */
-	char oem_id[6];		/* OEM identification */
-	char oem_table_id[8];	/* OEM table identification */
-	u32 oem_revision;	/* OEM revision number */
-	char asl_compiler_id[4];	/* ASL compiler vendor ID */
-	u32 asl_compiler_revision;	/* ASL compiler revision number */
-} acpi_table_header __attribute__ ((packed));;
-
-enum {
-	ACPI_APIC = 0,
-	ACPI_BOOT,
-	ACPI_DBGP,
-	ACPI_DSDT,
-	ACPI_ECDT,
-	ACPI_ETDT,
-	ACPI_FACP,
-	ACPI_FACS,
-	ACPI_OEMX,
-	ACPI_PSDT,
-	ACPI_SBST,
-	ACPI_SLIT,
-	ACPI_SPCR,
-	ACPI_SRAT,
-	ACPI_SSDT,
-	ACPI_SPMI,
-	ACPI_XSDT,
-	ACPI_TABLE_COUNT
-};
-
-static char *acpi_table_signatures[ACPI_TABLE_COUNT] = {
-	"APIC",
-	"BOOT",
-	"DBGP",
-	"DSDT",
-	"ECDT",
-	"ETDT",
-	"FACP",
-	"FACS",
-	"OEM",
-	"PSDT",
-	"SBST",
-	"SLIT",
-	"SPCR",
-	"SRAT",
-	"SSDT",
-	"SPMI",
-	"XSDT"
-};
-
-struct acpi_table_madt {
-	acpi_table_header header;
-	u32 lapic_address;
-	struct {
-		u32 pcat_compat:1;
-		u32 reserved:31;
-	} flags __attribute__ ((packed));
-} __attribute__ ((packed));;
-
-enum {
-	ACPI_MADT_LAPIC = 0,
-	ACPI_MADT_IOAPIC,
-	ACPI_MADT_INT_SRC_OVR,
-	ACPI_MADT_NMI_SRC,
-	ACPI_MADT_LAPIC_NMI,
-	ACPI_MADT_LAPIC_ADDR_OVR,
-	ACPI_MADT_IOSAPIC,
-	ACPI_MADT_LSAPIC,
-	ACPI_MADT_PLAT_INT_SRC,
-	ACPI_MADT_ENTRY_COUNT
-};
-
-#define RSDP_SIG			"RSD PTR "
-#define RSDT_SIG 			"RSDT"
-
-#define ACPI_DEBUG_PRINT(pl)
-
-#define ACPI_MEMORY_MODE                0x01
-#define ACPI_LOGICAL_ADDRESSING         0x00
-#define ACPI_PHYSICAL_ADDRESSING        0x01
-
-#define LO_RSDP_WINDOW_BASE         	0	/* Physical Address */
-#define HI_RSDP_WINDOW_BASE         	0xE0000	/* Physical Address */
-#define LO_RSDP_WINDOW_SIZE         	0x400
-#define HI_RSDP_WINDOW_SIZE         	0x20000
-#define RSDP_SCAN_STEP			16
-#define RSDP_CHECKSUM_LENGTH		20
-
-typedef int (*acpi_table_handler) (acpi_table_header * header, unsigned long);
-
-struct acpi_table_rsdp {
-	char signature[8];
-	u8 checksum;
-	char oem_id[6];
-	u8 revision;
-	u32 rsdt_address;
-} __attribute__ ((packed));
-
-struct acpi_table_rsdt {
-	acpi_table_header header;
-	u32 entry[ACPI_TABLE_COUNT];
-} __attribute__ ((packed));
-
-typedef struct {
-	u8 type;
-	u8 length;
-} acpi_madt_entry_header __attribute__ ((packed));
-
-typedef struct {
-	u16 polarity:2;
-	u16 trigger:2;
-	u16 reserved:12;
-} acpi_madt_int_flags __attribute__ ((packed));
-
-struct acpi_table_lapic {
-	acpi_madt_entry_header header;
-	u8 acpi_id;
-	u8 id;
-	struct {
-		u32 enabled:1;
-		u32 reserved:31;
-	} flags __attribute__ ((packed));
-} __attribute__ ((packed));
-
-struct acpi_table_ioapic {
-	acpi_madt_entry_header header;
-	u8 id;
-	u8 reserved;
-	u32 address;
-	u32 global_irq_base;
-} __attribute__ ((packed));
-
-struct acpi_table_int_src_ovr {
-	acpi_madt_entry_header header;
-	u8 bus;
-	u8 bus_irq;
-	u32 global_irq;
-	acpi_madt_int_flags flags;
-} __attribute__ ((packed));
-
-struct acpi_table_nmi_src {
-	acpi_madt_entry_header header;
-	acpi_madt_int_flags flags;
-	u32 global_irq;
-} __attribute__ ((packed));
-
-struct acpi_table_lapic_nmi {
-	acpi_madt_entry_header header;
-	u8 acpi_id;
-	acpi_madt_int_flags flags;
-	u8 lint;
-} __attribute__ ((packed));
-
-struct acpi_table_lapic_addr_ovr {
-	acpi_madt_entry_header header;
-	u8 reserved[2];
-	u64 address;
-} __attribute__ ((packed));
-
-struct acpi_table_iosapic {
-	acpi_madt_entry_header header;
-	u8 id;
-	u8 reserved;
-	u32 global_irq_base;
-	u64 address;
-} __attribute__ ((packed));
-
-struct acpi_table_lsapic {
-	acpi_madt_entry_header header;
-	u8 acpi_id;
-	u8 id;
-	u8 eid;
-	u8 reserved[3];
-	struct {
-		u32 enabled:1;
-		u32 reserved:31;
-	} flags;
-} __attribute__ ((packed));
-
-struct acpi_table_plat_int_src {
-	acpi_madt_entry_header header;
-	acpi_madt_int_flags flags;
-	u8 type;
-	u8 id;
-	u8 eid;
-	u8 iosapic_vector;
-	u32 global_irq;
-	u32 reserved;
-} __attribute__ ((packed));
-
-/*
- * ACPI Table Descriptor.  One per ACPI table
- */
-typedef struct acpi_table_desc {
-	struct acpi_table_desc *prev;
-	struct acpi_table_desc *next;
-	struct acpi_table_desc *installed_desc;
-	acpi_table_header *pointer;
-	void *base_pointer;
-	u8 *aml_pointer;
-	u64 physical_address;
-	u32 aml_length;
-	u32 length;
-	u32 count;
-	u16 table_id;
-	u8 type;
-	u8 allocation;
-	u8 loaded_into_namespace;
-
-} acpi_table_desc __attribute__ ((packed));;
-
-#endif
diff -Nru a/arch/i386/kernel/apm.c b/arch/i386/kernel/apm.c
--- a/arch/i386/kernel/apm.c	Fri Mar 15 17:51:01 2002
+++ b/arch/i386/kernel/apm.c	Fri Mar 15 17:51:01 2002
@@ -275,10 +275,11 @@
  */
 
 /*
- * Define to always call the APM BIOS busy routine even if the clock was
- * not slowed by the idle routine.
+ * Define as 1 to make the driver always call the APM BIOS busy
+ * routine even if the clock was not reported as slowed by the
+ * idle routine.  Otherwise, define as 0.
  */
-#define ALWAYS_CALL_BUSY
+#define ALWAYS_CALL_BUSY   1
 
 /*
  * Define to make the APM BIOS calls zero all data segment registers (so
@@ -380,7 +381,7 @@
 static int			set_pm_idle;
 static int			suspends_pending;
 static int			standbys_pending;
-static int			waiting_for_resume;
+static int			ignore_sys_suspend;
 static int			ignore_normal_resume;
 static int			bounce_interval = DEFAULT_BOUNCE_INTERVAL;
 
@@ -471,6 +472,28 @@
 };
 #define ERROR_COUNT	(sizeof(error_table)/sizeof(lookup_t))
 
+/**
+ *	apm_error	-	display an APM error
+ *	@str: information string
+ *	@err: APM BIOS return code
+ *
+ *	Write a meaningful log entry to the kernel log in the event of
+ *	an APM error.
+ */
+ 
+static void apm_error(char *str, int err)
+{
+	int	i;
+
+	for (i = 0; i < ERROR_COUNT; i++)
+		if (error_table[i].key == err) break;
+	if (i < ERROR_COUNT)
+		printk(KERN_NOTICE "apm: %s: %s\n", str, error_table[i].msg);
+	else
+		printk(KERN_NOTICE "apm: %s: unknown error code %#2.2x\n",
+			str, err);
+}
+
 /*
  * These are the actual BIOS calls.  Depending on APM_ZERO_SEGS and
  * apm_info.allow_ints, we are being really paranoid here!  Not only
@@ -702,13 +725,13 @@
 }
 
 /**
- *	apm_set_power_state - set system wide power state
+ *	set_system_power_state - set system wide power state
  *	@state: which state to enter
  *
  *	Transition the entire system into a new APM power state.
  */
  
-static int apm_set_power_state(u_short state)
+static int set_system_power_state(u_short state)
 {
 	return set_power_state(APM_DEVICE_ALL, state);
 }
@@ -725,7 +748,6 @@
 static int apm_do_idle(void)
 {
 	u32	eax;
-	int	slowed;
 
 	if (apm_bios_call_simple(APM_FUNC_IDLE, 0, 0, &eax)) {
 		static unsigned long t;
@@ -737,13 +759,8 @@
 		}
 		return -1;
 	}
-	slowed = (apm_info.bios.flags & APM_IDLE_SLOWS_CLOCK) != 0;
-#ifdef ALWAYS_CALL_BUSY
-	clock_slowed = 1;
-#else
-	clock_slowed = slowed;
-#endif
-	return slowed;
+	clock_slowed = (apm_info.bios.flags & APM_IDLE_SLOWS_CLOCK) != 0;
+	return clock_slowed;
 }
 
 /**
@@ -756,7 +773,7 @@
 {
 	u32	dummy;
 
-	if (clock_slowed) {
+	if (clock_slowed || ALWAYS_CALL_BUSY) {
 		(void) apm_bios_call_simple(APM_FUNC_BUSY, 0, 0, &dummy);
 		clock_slowed = 0;
 	}
@@ -771,7 +788,7 @@
 #define IDLE_CALC_LIMIT   (HZ * 100)
 #define IDLE_LEAKY_MAX    16
 
-static void (*sys_idle)(void);
+static void (*original_pm_idle)(void);
 
 extern void default_idle(void);
 
@@ -785,14 +802,13 @@
 
 static void apm_cpu_idle(void)
 {
-	static int use_apm_idle = 0;
-	static unsigned int last_jiffies = 0;
-	static unsigned int last_stime = 0;
+	static int use_apm_idle; /* = 0 */
+	static unsigned int last_jiffies; /* = 0 */
+	static unsigned int last_stime; /* = 0 */
 
-	int apm_is_idle = 0;
+	int apm_idle_done = 0;
 	unsigned int jiffies_since_last_check = jiffies - last_jiffies;
-	unsigned int t1;
-
+	unsigned int bucket;
 
 recalc:
 	if (jiffies_since_last_check > IDLE_CALC_LIMIT) {
@@ -810,7 +826,7 @@
 		last_stime = current->times.tms_stime;
 	}
 
-	t1 = IDLE_LEAKY_MAX;
+	bucket = IDLE_LEAKY_MAX;
 
 	while (!need_resched()) {
 		if (use_apm_idle) {
@@ -818,23 +834,24 @@
 
 			t = jiffies;
 			switch (apm_do_idle()) {
-			case 0: apm_is_idle = 1;
+			case 0: apm_idle_done = 1;
 				if (t != jiffies) {
-					if (t1) {
-						t1 = IDLE_LEAKY_MAX;
+					if (bucket) {
+						bucket = IDLE_LEAKY_MAX;
 						continue;
 					}
-				} else if (t1) {
-					t1--;
+				} else if (bucket) {
+					bucket--;
 					continue;
 				}
 				break;
-			case 1: apm_is_idle = 1;
+			case 1: apm_idle_done = 1;
 				break;
+			default: /* BIOS refused */
 			}
 		}
-		if (sys_idle)
-			sys_idle();
+		if (original_pm_idle)
+			original_pm_idle();
 		else
 			default_idle();
 		jiffies_since_last_check = jiffies - last_jiffies;
@@ -842,7 +859,7 @@
 			goto recalc;
 	}
 
-	if (apm_is_idle)
+	if (apm_idle_done)
 		apm_do_busy();
 }
 
@@ -890,7 +907,7 @@
 	if (apm_info.realmode_power_off)
 		machine_real_restart(po_bios_call, sizeof(po_bios_call));
 	else
-		(void) apm_set_power_state(APM_STATE_OFF);
+		(void) set_system_power_state(APM_STATE_OFF);
 }
 
 /**
@@ -1035,28 +1052,6 @@
 	return APM_SUCCESS;
 }
 
-/**
- *	apm_error	-	display an APM error
- *	@str: information string
- *	@err: APM BIOS return code
- *
- *	Write a meaningful log entry to the kernel log in the event of
- *	an APM error.
- */
- 
-static void apm_error(char *str, int err)
-{
-	int	i;
-
-	for (i = 0; i < ERROR_COUNT; i++)
-		if (error_table[i].key == err) break;
-	if (i < ERROR_COUNT)
-		printk(KERN_NOTICE "apm: %s: %s\n", str, error_table[i].msg);
-	else
-		printk(KERN_NOTICE "apm: %s: unknown error code %#2.2x\n",
-			str, err);
-}
-
 #if defined(CONFIG_APM_DISPLAY_BLANK) && defined(CONFIG_VT)
 
 /**
@@ -1198,9 +1193,9 @@
 		/* Vetoed */
 		if (vetoable) {
 			if (apm_info.connection_version > 0x100)
-				apm_set_power_state(APM_STATE_REJECT);
+				set_system_power_state(APM_STATE_REJECT);
 			err = -EBUSY;
-			waiting_for_resume = 0;
+			ignore_sys_suspend = 0;
 			printk(KERN_WARNING "apm: suspend was vetoed.\n");
 			goto out;
 		}
@@ -1208,9 +1203,10 @@
 	}
 	get_time_diff();
 	cli();
-	err = apm_set_power_state(APM_STATE_SUSPEND);
+	err = set_system_power_state(APM_STATE_SUSPEND);
 	reinit_timer();
 	set_time();
+	ignore_normal_resume = 1;
 	sti();
 	if (err == APM_NO_ERROR)
 		err = APM_SUCCESS;
@@ -1219,7 +1215,6 @@
 	err = (err == APM_SUCCESS) ? 0 : -EIO;
 	pm_send_all(PM_RESUME, (void *)0);
 	queue_event(APM_NORMAL_RESUME, NULL);
-	ignore_normal_resume = 1;
  out:
 	spin_lock(&user_list_lock);
 	for (as = user_list; as != NULL; as = as->next) {
@@ -1237,7 +1232,7 @@
 
 	/* If needed, notify drivers here */
 	get_time_diff();
-	err = apm_set_power_state(APM_STATE_STANDBY);
+	err = set_system_power_state(APM_STATE_STANDBY);
 	if ((err != APM_SUCCESS) && (err != APM_NO_ERROR))
 		apm_error("standby", err);
 }
@@ -1291,13 +1286,13 @@
 		case APM_USER_SUSPEND:
 #ifdef CONFIG_APM_IGNORE_USER_SUSPEND
 			if (apm_info.connection_version > 0x100)
-				apm_set_power_state(APM_STATE_REJECT);
+				set_system_power_state(APM_STATE_REJECT);
 			break;
 #endif
 		case APM_SYS_SUSPEND:
 			if (ignore_bounce) {
 				if (apm_info.connection_version > 0x100)
-					apm_set_power_state(APM_STATE_REJECT);
+					set_system_power_state(APM_STATE_REJECT);
 				break;
 			}
 			/*
@@ -1308,9 +1303,9 @@
 			 * sending a SUSPEND event until something else
 			 * happens!
 			 */
-			if (waiting_for_resume)
+			if (ignore_sys_suspend)
 				return;
-			waiting_for_resume = 1;
+			ignore_sys_suspend = 1;
 			queue_event(event, NULL);
 			if (suspends_pending <= 0)
 				(void) suspend(1);
@@ -1319,7 +1314,7 @@
 		case APM_NORMAL_RESUME:
 		case APM_CRITICAL_RESUME:
 		case APM_STANDBY_RESUME:
-			waiting_for_resume = 0;
+			ignore_sys_suspend = 0;
 			last_resume = jiffies;
 			ignore_bounce = 1;
 			if ((event != APM_NORMAL_RESUME)
@@ -1363,7 +1358,7 @@
 			pending_count = 4;
 			if (debug)
 				printk(KERN_DEBUG "apm: setting state busy\n");
-			err = apm_set_power_state(APM_STATE_BUSY);
+			err = set_system_power_state(APM_STATE_BUSY);
 			if (err)
 				apm_error("busy", err);
 		}
@@ -1972,7 +1967,7 @@
 	if (HZ != 100)
 		idle_period = (idle_period * HZ) / 100;
 	if (idle_threshold < 100) {
-		sys_idle = pm_idle;
+		original_pm_idle = pm_idle;
 		pm_idle  = apm_cpu_idle;
 		set_pm_idle = 1;
 	}
@@ -1985,7 +1980,7 @@
 	int	error;
 
 	if (set_pm_idle)
-		pm_idle = sys_idle;
+		pm_idle = original_pm_idle;
 	if (((apm_info.bios.flags & APM_BIOS_DISENGAGED) == 0)
 	    && (apm_info.connection_version > 0x0100)) {
 		error = apm_engage_power_management(APM_DEVICE_ALL, 0);
diff -Nru a/arch/i386/kernel/dmi_scan.c b/arch/i386/kernel/dmi_scan.c
--- a/arch/i386/kernel/dmi_scan.c	Fri Mar 15 17:51:02 2002
+++ b/arch/i386/kernel/dmi_scan.c	Fri Mar 15 17:51:02 2002
@@ -492,6 +492,11 @@
 			MATCH(DMI_BIOS_VERSION, "A04"),
 			MATCH(DMI_BIOS_DATE, "08/24/2000"), NO_MATCH
 			} },
+	{ broken_apm_power, "Dell Inspiron 2500", {	/* Handle problems with APM on Inspiron 2500 */
+			MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies LTD"),
+			MATCH(DMI_BIOS_VERSION, "A12"),
+			MATCH(DMI_BIOS_DATE, "02/04/2002"), NO_MATCH
+			} },
 	{ set_realmode_power_off, "Award Software v4.60 PGMA", {	/* broken PM poweroff bios */
 			MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
 			MATCH(DMI_BIOS_VERSION, "4.60 PGMA"),
diff -Nru a/arch/i386/kernel/entry.S b/arch/i386/kernel/entry.S
--- a/arch/i386/kernel/entry.S	Fri Mar 15 17:51:02 2002
+++ b/arch/i386/kernel/entry.S	Fri Mar 15 17:51:02 2002
@@ -717,6 +717,7 @@
 	.long SYMBOL_NAME(sys_fremovexattr)
 	.long SYMBOL_NAME(sys_tkill)
 	.long SYMBOL_NAME(sys_sendfile64)
+	.long SYMBOL_NAME(sys_futex)		/* 240 */
 
 	.rept NR_syscalls-(.-sys_call_table)/4
 		.long SYMBOL_NAME(sys_ni_syscall)
diff -Nru a/arch/i386/kernel/head.S b/arch/i386/kernel/head.S
--- a/arch/i386/kernel/head.S	Fri Mar 15 17:51:01 2002
+++ b/arch/i386/kernel/head.S	Fri Mar 15 17:51:01 2002
@@ -178,7 +178,7 @@
  * we don't need to preserve eflags.
  */
 
-	movl $3,X86		# at least 386
+	movb $3,X86		# at least 386
 	pushfl			# push EFLAGS
 	popl %eax		# get EFLAGS
 	movl %eax,%ecx		# save original EFLAGS
@@ -191,7 +191,7 @@
 	andl $0x40000,%eax	# check if AC bit changed
 	je is386
 
-	movl $4,X86		# at least 486
+	movb $4,X86		# at least 486
 	movl %ecx,%eax
 	xorl $0x200000,%eax	# check ID flag
 	pushl %eax
diff -Nru a/arch/i386/kernel/mpparse.c b/arch/i386/kernel/mpparse.c
--- a/arch/i386/kernel/mpparse.c	Fri Mar 15 17:51:02 2002
+++ b/arch/i386/kernel/mpparse.c	Fri Mar 15 17:51:02 2002
@@ -14,6 +14,7 @@
 
 #include <linux/mm.h>
 #include <linux/irq.h>
+#include <linux/acpi.h>
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/config.h>
@@ -30,6 +31,9 @@
 /* Have we found an MP table */
 int smp_found_config;
 
+/* Have we found an ACPI MADT table */
+int acpi_found_madt = 0;
+
 /*
  * Various Linux-internal data structures created from the
  * MP-table.
@@ -65,6 +69,19 @@
 /* Bitmask of physically existing CPUs */
 unsigned long phys_cpu_present_map;
 
+/* ACPI MADT entry parsing functions */
+#ifdef CONFIG_ACPI_BOOT
+extern struct acpi_boot_flags acpi_boot;
+#ifdef CONFIG_X86_LOCAL_APIC
+extern int acpi_parse_lapic (acpi_table_entry_header *header);
+extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
+extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
+#endif /*CONFIG_X86_LOCAL_APIC*/
+#ifdef CONFIG_X86_IO_APIC
+extern int acpi_parse_ioapic (acpi_table_entry_header *header);
+#endif /*CONFIG_X86_IO_APIC*/
+#endif /*CONFIG_ACPI_BOOT*/
+
 /*
  * Intel MP BIOS table parsing routines:
  */
@@ -122,13 +139,7 @@
 	return n;
 }
 
-#ifdef CONFIG_X86_IO_APIC
-extern int have_acpi_tables;	/* set by acpitable.c */
-#else
-#define have_acpi_tables (0)
-#endif
-
-/* 
+/*
  * Have to match translation table entries to main table entries by counter
  * hence the mpc_record variable .... can't see a less disgusting way of
  * doing this ....
@@ -427,10 +438,11 @@
 
 	printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
 
-	/* save the local APIC address, it might be non-default,
+	/*
+	 * Save the local APIC address, it might be non-default,
 	 * but only if we're not using the ACPI tables
 	 */
-	if (!have_acpi_tables)
+	if (!acpi_found_madt)
 		mp_lapic_addr = mpc->mpc_lapic;
 
 	if (clustered_apic_mode && mpc->mpc_oemptr) {
@@ -451,7 +463,7 @@
 					(struct mpc_config_processor *)mpt;
 
 				/* ACPI may already have provided this one for us */
-				if (!have_acpi_tables)
+				if (!acpi_found_madt)
 					MP_processor_info(m);
 				mpt += sizeof(*m);
 				count += sizeof(*m);
@@ -665,7 +677,6 @@
 }
 
 static struct intel_mp_floating *mpf_found;
-extern void 	config_acpi_tables(void);
 
 /*
  * Scan the memory blocks for an SMP configuration block.
@@ -674,16 +685,19 @@
 {
 	struct intel_mp_floating *mpf = mpf_found;
 
-#ifdef CONFIG_X86_IO_APIC
+#ifdef CONFIG_ACPI_BOOT
 	/*
-	 * Check if the ACPI tables are provided. Use them only to get
-	 * the processor information, mainly because it provides
-	 * the info on the logical processor(s), rather than the physical
-	 * processor(s) that are provided by the MPS. We attempt to 
-	 * check only if the user provided a commandline override
+	 * Check if the MADT exists, and if so, use it to get processor
+	 * information (ACPI_MADT_LAPIC).  The MADT supports the concept
+	 * of both logical (e.g. HT) and physical processor(s); where the
+	 * MPS only supports physical.
 	 */
-	config_acpi_tables();
-#endif
+	if (acpi_boot.madt) {
+		acpi_found_madt = acpi_table_parse(ACPI_APIC, acpi_parse_madt);
+		if (acpi_found_madt > 0)
+			acpi_table_parse_madt(ACPI_MADT_LAPIC, acpi_parse_lapic);
+	}
+#endif /*CONFIG_ACPI_BOOT*/
 	
 	printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
 	if (mpf->mpf_feature2 & (1<<7)) {
diff -Nru a/arch/i386/kernel/pci-i386.h b/arch/i386/kernel/pci-i386.h
--- a/arch/i386/kernel/pci-i386.h	Fri Mar 15 17:51:03 2002
+++ b/arch/i386/kernel/pci-i386.h	Fri Mar 15 17:51:03 2002
@@ -18,9 +18,11 @@
 #define PCI_NO_SORT		0x0100
 #define PCI_BIOS_SORT		0x0200
 #define PCI_NO_CHECKS		0x0400
+#define PCI_USE_PIRQ_MASK	0x0800
 #define PCI_ASSIGN_ROMS		0x1000
 #define PCI_BIOS_IRQ_SCAN	0x2000
 #define PCI_ASSIGN_ALL_BUSSES	0x4000
+#define PCI_NO_ACPI_ROUTING	0x8000
 
 extern unsigned int pci_probe;
 
@@ -63,6 +65,8 @@
 } __attribute__((packed));
 
 extern unsigned int pcibios_irq_mask;
+
+extern int pci_use_acpi_routing;
 
 void pcibios_irq_init(void);
 void pcibios_fixup_irqs(void);
diff -Nru a/arch/i386/kernel/pci-irq.c b/arch/i386/kernel/pci-irq.c
--- a/arch/i386/kernel/pci-irq.c	Fri Mar 15 17:51:03 2002
+++ b/arch/i386/kernel/pci-irq.c	Fri Mar 15 17:51:03 2002
@@ -12,7 +12,7 @@
 #include <linux/slab.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-
+#include <linux/acpi.h>
 #include <asm/io.h>
 #include <asm/smp.h>
 #include <asm/io_apic.h>
@@ -22,6 +22,8 @@
 #define PIRQ_SIGNATURE	(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
 #define PIRQ_VERSION 0x0100
 
+int pci_use_acpi_routing = 0;
+
 static struct irq_routing_table *pirq_table;
 
 /*
@@ -512,6 +514,41 @@
 		pirq_router_dev->slot_name);
 }
 
+static void pcibios_test_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+}
+
+#ifdef CONFIG_ACPI_PCI
+
+static int acpi_lookup_irq (
+	struct pci_dev		*dev,
+	u8			pin,
+	int			assign)
+{
+	int			result = 0;
+	int			irq = 0;
+
+	/* TBD: Select IRQ from possible to improve routing performance. */
+
+	result = acpi_prt_get_irq(dev, pin, &irq);
+	if ((0 != result) || !irq) {
+		printk(KERN_ERR "PCI: Unable to resolve IRQ for device %s\n",
+			dev->slot_name);
+		return result;
+	}
+
+	printk(KERN_INFO "PCI: Found IRQ %d for device %s\n", irq, 
+		dev->slot_name);
+
+	dev->irq = irq;
+
+	pirq_penalty[irq]++;
+
+	return 1;
+}
+
+#endif /* CONFIG_ACPI_PCI */
+
 static struct irq_info *pirq_get_info(struct pci_dev *dev)
 {
 	struct irq_routing_table *rt = pirq_table;
@@ -524,38 +561,25 @@
 	return NULL;
 }
 
-static void pcibios_test_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
-{
-}
-
-static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
+static int pirq_lookup_irq(struct pci_dev *dev, u8 pin, int assign)
 {
-	u8 pin;
-	struct irq_info *info;
-	int i, pirq, newirq;
-	int irq = 0;
-	u32 mask;
 	struct irq_router *r = pirq_router;
+	struct irq_info *info;
+	int  newirq, pirq, i, irq = 0;
 	struct pci_dev *dev2;
 	char *msg = NULL;
+	u32 mask;
 
 	if (!pirq_table)
 		return 0;
 
-	/* Find IRQ routing entry */
-	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
-	if (!pin) {
-		DBG(" -> no interrupt pin\n");
-		return 0;
-	}
-	pin = pin - 1;
-	
 	DBG("IRQ for %s:%d", dev->slot_name, pin);
 	info = pirq_get_info(dev);
 	if (!info) {
 		DBG(" -> not found in routing table\n");
 		return 0;
 	}
+
 	pirq = info->irq[pin].link;
 	mask = info->irq[pin].bitmap;
 	if (!pirq) {
@@ -570,6 +594,10 @@
 	 * reported by the device if possible.
 	 */
 	newirq = dev->irq;
+	if (!((1 << newirq) & mask)) {
+		if ( pci_probe & PCI_USE_PIRQ_MASK) newirq = 0;
+		else printk(KERN_WARNING "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n", newirq, dev->slot_name);
+	}
 	if (!newirq && assign) {
 		for (i = 0; i < 16; i++) {
 			if (!(mask & (1 << i)))
@@ -588,7 +616,8 @@
 		irq = pirq & 0xf;
 		DBG(" -> hardcoded IRQ %d\n", irq);
 		msg = "Hardcoded";
-	} else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq))) {
+	} else if ( r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \
+	((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask)) ) {
 		DBG(" -> got IRQ %d\n", irq);
 		msg = "Found";
 	} else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) {
@@ -622,7 +651,9 @@
 			continue;
 		if (info->irq[pin].link == pirq) {
 			/* We refuse to override the dev->irq information. Give a warning! */
-		    	if (dev2->irq && dev2->irq != irq) {
+		    	if ( dev2->irq && dev2->irq != irq && \
+			(!(pci_probe & PCI_USE_PIRQ_MASK) || \
+			((1 << dev2->irq) & mask)) ) {
 		    		printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n",
 				       dev2->slot_name, dev2->irq, irq);
 		    		continue;
@@ -636,10 +667,42 @@
 	return 1;
 }
 
+static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
+{
+	u8 pin;
+
+	/* Find IRQ routing entry */
+	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
+	if (!pin) {
+		DBG("PCI: %s: no interrupt pin\n", dev->slot_name);
+		return 0;
+	}
+	pin -= 1;
+
+#ifdef CONFIG_ACPI_PCI
+	if (pci_use_acpi_routing)
+		return acpi_lookup_irq(dev, pin, assign);
+	else
+#endif
+		return pirq_lookup_irq(dev, pin, assign);
+}
+
 void __init pcibios_irq_init(void)
 {
 	DBG("PCI: IRQ init\n");
+
+#ifdef CONFIG_ACPI_PCI
+	if (acpi_prts.count && !(pci_probe & PCI_NO_ACPI_ROUTING)) {
+		printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
+		pci_use_acpi_routing = 1;
+		return;
+	}
+	if (!acpi_prts.count)
+		printk(KERN_INFO "PCI: Invalid acpi_prts [%d]\n", acpi_prts.count);
+#endif
+
 	pirq_table = pirq_find_routing_table();
+
 #ifdef CONFIG_PCI_BIOS
 	if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN))
 		pirq_table = pcibios_get_irq_routing_table();
diff -Nru a/arch/i386/kernel/pci-pc.c b/arch/i386/kernel/pci-pc.c
--- a/arch/i386/kernel/pci-pc.c	Fri Mar 15 17:51:02 2002
+++ b/arch/i386/kernel/pci-pc.c	Fri Mar 15 17:51:02 2002
@@ -1239,6 +1239,24 @@
 }
 
 
+struct pci_bus * __devinit pcibios_scan_root(int busnum)
+{
+	struct list_head *list;
+	struct pci_bus *bus;
+
+	list_for_each(list, &pci_root_buses) {
+		bus = pci_bus_b(list);
+		if (bus->number == busnum) {
+			/* Already scanned */
+			return bus;
+		}
+	}
+
+	printk("PCI: Probing PCI hardware (bus %02x)\n", busnum);
+
+	return pci_scan_bus(busnum, pci_root_ops, NULL);
+}
+
 void __devinit pcibios_config_init(void)
 {
 	/*
@@ -1285,7 +1303,7 @@
 	}
 
 	printk("PCI: Probing PCI hardware\n");
-	pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
+	pci_root_bus = pcibios_scan_root(0);
 	if (clustered_apic_mode && (numnodes > 1)) {
 		for (quad = 1; quad < numnodes; ++quad) {
 			printk("Scanning PCI bus %d for quad %d\n", 
@@ -1296,7 +1314,10 @@
 	}
 
 	pcibios_irq_init();
-	pcibios_fixup_peer_bridges();
+
+	if (!pci_use_acpi_routing)
+		pcibios_fixup_peer_bridges();
+
 	pcibios_fixup_irqs();
 	pcibios_resource_survey();
 
@@ -1337,11 +1358,20 @@
 		return NULL;
 	}
 #endif
+#ifdef CONFIG_ACPI_PCI
+	else if (!strcmp(str, "noacpi")) {
+		pci_probe |= PCI_NO_ACPI_ROUTING;
+		return NULL;
+	}
+#endif
 	else if (!strcmp(str, "rom")) {
 		pci_probe |= PCI_ASSIGN_ROMS;
 		return NULL;
 	} else if (!strcmp(str, "assign-busses")) {
 		pci_probe |= PCI_ASSIGN_ALL_BUSSES;
+		return NULL;
+	} else if (!strcmp(str, "usepirqmask")) {
+		pci_probe |= PCI_USE_PIRQ_MASK;
 		return NULL;
 	} else if (!strncmp(str, "irqmask=", 8)) {
 		pcibios_irq_mask = simple_strtol(str+8, NULL, 0);
diff -Nru a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c
--- a/arch/i386/kernel/setup.c	Fri Mar 15 17:51:03 2002
+++ b/arch/i386/kernel/setup.c	Fri Mar 15 17:51:03 2002
@@ -92,6 +92,7 @@
 #include <linux/delay.h>
 #include <linux/config.h>
 #include <linux/init.h>
+#include <linux/acpi.h>
 #include <linux/apm_bios.h>
 #ifdef CONFIG_BLK_DEV_RAM
 #include <linux/blk.h>
@@ -168,8 +169,6 @@
 static int disable_x86_serial_nr __initdata = 1;
 static int disable_x86_fxsr __initdata = 0;
 
-int enable_acpi_smp_table;
-
 /*
  * This is set up by the setup-routine at boot-time
  */
@@ -642,9 +641,6 @@
 				add_memory_region(start_at, mem_size, E820_RAM);
 			}
 		}
-		/* acpismp=force forces parsing and use of the ACPI SMP table */
-		if (c == ' ' && !memcmp(from, "acpismp=force", 13))
-			 enable_acpi_smp_table = 1;
 		/*
 		 * highmem=size forces highmem to be exactly 'size' bytes.
 		 * This works even on boxes that have no highmem otherwise.
@@ -869,7 +865,12 @@
 	 */
 	reserve_bootmem(PAGE_SIZE, PAGE_SIZE);
 #endif
-
+#ifdef CONFIG_ACPI_SLEEP
+	/*
+	 * Reserve low memory region for sleep support.
+	 */
+	acpi_reserve_bootmem();
+#endif
 #ifdef CONFIG_X86_LOCAL_APIC
 	/*
 	 * Find and reserve possible boot-time SMP configuration:
@@ -903,6 +904,15 @@
 	smp_alloc_memory(); /* AP processor realmode stacks in low memory*/
 #endif
 	paging_init();
+#ifdef CONFIG_ACPI_BOOT
+	/*
+	 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
+	 * Must do this after paging_init (due to reliance on fixmap, and thus
+	 * the bootmem allocator) but before get_smp_config (to allow parsing
+	 * of MADT).
+	 */
+	acpi_table_init(*cmdline_p);
+#endif
 #ifdef CONFIG_X86_LOCAL_APIC
 	/*
 	 * get boot-time SMP configuration:
@@ -1961,13 +1971,10 @@
 
 static void __init init_intel(struct cpuinfo_x86 *c)
 {
-#ifndef CONFIG_M686
-	static int f00f_workaround_enabled = 0;
-#endif
 	char *p = NULL;
 	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
 
-#ifndef CONFIG_M686
+#ifdef CONFIG_X86_F00F_BUG
 	/*
 	 * All current models of Pentium and Pentium with MMX technology CPUs
 	 * have the F0 0F bug, which lets nonpriviledged users lock up the system.
@@ -1975,6 +1982,8 @@
 	 */
 	c->f00f_bug = 0;
 	if ( c->x86 == 5 ) {
+		static int f00f_workaround_enabled = 0;
+
 		c->f00f_bug = 1;
 		if ( !f00f_workaround_enabled ) {
 			trap_init_f00f_bug();
diff -Nru a/arch/i386/kernel/signal.c b/arch/i386/kernel/signal.c
--- a/arch/i386/kernel/signal.c	Fri Mar 15 17:51:03 2002
+++ b/arch/i386/kernel/signal.c	Fri Mar 15 17:51:03 2002
@@ -630,8 +630,8 @@
 				info.si_signo = signr;
 				info.si_errno = 0;
 				info.si_code = SI_USER;
-				info.si_pid = current->p_pptr->pid;
-				info.si_uid = current->p_pptr->uid;
+				info.si_pid = current->parent->pid;
+				info.si_uid = current->parent->uid;
 			}
 
 			/* If the (new) signal is now blocked, requeue it.  */
@@ -670,7 +670,7 @@
 			case SIGSTOP: {
 				struct signal_struct *sig;
 				current->exit_code = signr;
-				sig = current->p_pptr->sig;
+				sig = current->parent->sig;
 				preempt_disable();
 				current->state = TASK_STOPPED;
 				if (sig && !(sig->action[SIGCHLD-1].sa.sa_flags & SA_NOCLDSTOP))
diff -Nru a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c
--- a/arch/i386/kernel/smpboot.c	Fri Mar 15 17:51:03 2002
+++ b/arch/i386/kernel/smpboot.c	Fri Mar 15 17:51:03 2002
@@ -828,7 +828,7 @@
 	 * We remove it from the pidhash and the runqueue
 	 * once we got the process:
 	 */
-	idle = init_task.prev_task;
+	idle = prev_task(&init_task);
 	if (!idle)
 		panic("No idle process for CPU %d", cpu);
 
diff -Nru a/arch/i386/kernel/traps.c b/arch/i386/kernel/traps.c
--- a/arch/i386/kernel/traps.c	Fri Mar 15 17:51:01 2002
+++ b/arch/i386/kernel/traps.c	Fri Mar 15 17:51:01 2002
@@ -775,35 +775,17 @@
 
 #endif /* CONFIG_MATH_EMULATION */
 
-#ifndef CONFIG_M686
+#ifdef CONFIG_X86_F00F_BUG
 void __init trap_init_f00f_bug(void)
 {
-	unsigned long page;
-	pgd_t * pgd;
-	pmd_t * pmd;
-	pte_t * pte;
-
-	/*
-	 * Allocate a new page in virtual address space, 
-	 * move the IDT into it and write protect this page.
-	 */
-	page = (unsigned long) vmalloc(PAGE_SIZE);
-	pgd = pgd_offset(&init_mm, page);
-	pmd = pmd_offset(pgd, page);
-	pte = pte_offset_kernel(pmd, page);
-	__free_page(pte_page(*pte));
-	*pte = mk_pte_phys(__pa(&idt_table), PAGE_KERNEL_RO);
-	/*
-	 * Not that any PGE-capable kernel should have the f00f bug ...
-	 */
-	__flush_tlb_all();
+	__set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
 
 	/*
 	 * "idt" is magic - it overlaps the idt_descr
 	 * variable so that updating idt will automatically
 	 * update the idt descriptor..
 	 */
-	idt = (struct desc_struct *)page;
+	idt = (struct desc_struct *) fix_to_virt(FIX_F00F_IDT);
 	__asm__ __volatile__("lidt %0": "=m" (idt_descr));
 }
 #endif
diff -Nru a/arch/i386/mm/fault.c b/arch/i386/mm/fault.c
--- a/arch/i386/mm/fault.c	Fri Mar 15 17:51:00 2002
+++ b/arch/i386/mm/fault.c	Fri Mar 15 17:51:00 2002
@@ -282,6 +282,7 @@
 		return;
 	}
 
+#ifdef CONFIG_X86_F00F_BUG
 	/*
 	 * Pentium F0 0F C7 C8 bug workaround.
 	 */
@@ -295,6 +296,7 @@
 			return;
 		}
 	}
+#endif
 
 no_context:
 	/* Are we prepared to handle this kernel fault?  */
diff -Nru a/arch/ia64/Makefile b/arch/ia64/Makefile
--- a/arch/ia64/Makefile	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/Makefile	Fri Mar 15 17:51:01 2002
@@ -25,7 +25,7 @@
 GCC_VERSION=$(shell $(CROSS_COMPILE)$(HOSTCC) -v 2>&1 | fgrep 'gcc version' | cut -f3 -d' ' | cut -f1 -d'.')
 
 ifneq ($(GCC_VERSION),2)
-	CFLAGS += -frename-registers --param max-inline-insns=400
+	CFLAGS += -frename-registers --param max-inline-insns=2000
 endif
 
 ifeq ($(CONFIG_ITANIUM_BSTEP_SPECIFIC),y)
@@ -58,7 +58,7 @@
 	CFLAGS		+= -DBRINGUP
         SUBDIRS         :=      arch/$(ARCH)/sn/kernel	\
 				arch/$(ARCH)/sn/io	\
-				arch/$(ARCH)/sn/fprom	\
+				arch/$(ARCH)/sn/fakeprom	\
 				$(SUBDIRS)
         CORE_FILES      :=      arch/$(ARCH)/sn/kernel/sn.o	\
 				arch/$(ARCH)/sn/io/sgiio.o	\
diff -Nru a/arch/ia64/config.in b/arch/ia64/config.in
--- a/arch/ia64/config.in	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/config.in	Fri Mar 15 17:51:03 2002
@@ -1,9 +1,9 @@
-mainmenu_name "Kernel configuration of Linux for IA-64 machines"
+mainmenu_name "IA-64 Linux Kernel Configuration"
 
 source init/Config.in
 
 mainmenu_option next_comment
-comment 'General setup'
+comment 'Processor type and features'
 
 define_bool CONFIG_IA64 y
 
@@ -14,13 +14,6 @@
 define_bool CONFIG_RWSEM_GENERIC_SPINLOCK y
 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
 
-if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then
-  define_bool CONFIG_ACPI y
-  define_bool CONFIG_ACPI_EFI y
-  define_bool CONFIG_ACPI_INTERPRETER y
-  define_bool CONFIG_ACPI_KERNEL_CONFIG y
-fi
-
 choice 'IA-64 processor type' \
 	"Itanium			CONFIG_ITANIUM \
 	 McKinley			CONFIG_MCKINLEY" Itanium
@@ -38,6 +31,13 @@
 	 16KB			CONFIG_IA64_PAGE_SIZE_16KB		\
 	 64KB			CONFIG_IA64_PAGE_SIZE_64KB" 16KB
 
+if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then
+  define_bool CONFIG_ACPI y
+  define_bool CONFIG_ACPI_EFI y
+  define_bool CONFIG_ACPI_INTERPRETER y
+  define_bool CONFIG_ACPI_KERNEL_CONFIG y
+fi
+
 if [ "$CONFIG_ITANIUM" = "y" ]; then
 	define_bool CONFIG_IA64_BRL_EMU y
 	bool '  Enable Itanium B-step specific code' CONFIG_ITANIUM_BSTEP_SPECIFIC
@@ -119,6 +119,7 @@
 source drivers/mtd/Config.in
 source drivers/pnp/Config.in
 source drivers/block/Config.in
+source drivers/ieee1394/Config.in
 source drivers/message/i2o/Config.in
 source drivers/md/Config.in
 
@@ -135,6 +136,17 @@
 fi
 endmenu
 
+else # ! HP_SIM
+mainmenu_option next_comment
+comment 'Block devices'
+tristate 'Loopback device support' CONFIG_BLK_DEV_LOOP
+dep_tristate 'Network block device support' CONFIG_BLK_DEV_NBD $CONFIG_NET
+
+tristate 'RAM disk support' CONFIG_BLK_DEV_RAM
+if [ "$CONFIG_BLK_DEV_RAM" = "y" -o "$CONFIG_BLK_DEV_RAM" = "m" ]; then
+   int '  Default RAM disk size' CONFIG_BLK_DEV_RAM_SIZE 4096
+fi
+endmenu
 fi # !HP_SIM
 
 mainmenu_option next_comment
@@ -227,15 +239,7 @@
 fi # !HP_SIM
 
 if [ "$CONFIG_IA64_HP_SIM" != "n" -o "$CONFIG_IA64_GENERIC" != "n" ]; then
-  mainmenu_option next_comment
-  comment 'Simulated drivers'
-
-  tristate 'Simulated Ethernet ' CONFIG_SIMETH
-  bool 'Simulated serial driver support' CONFIG_SIM_SERIAL
-  if [ "$CONFIG_SCSI" != "n" ]; then
-    bool 'Simulated SCSI disk' CONFIG_SCSI_SIM
-  fi
-  endmenu
+  source arch/ia64/hp/Config.in
 fi
 
 
@@ -252,9 +256,7 @@
    bool '  Disable VHPT' CONFIG_DISABLE_VHPT
    bool '  Magic SysRq key' CONFIG_MAGIC_SYSRQ
 
-# early printk is currently broken for SMP: the secondary processors get stuck...
-#   bool '  Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK
-
+   bool '  Early printk support (requires VGA!)' CONFIG_IA64_EARLY_PRINTK
    bool '  Debug memory allocations' CONFIG_DEBUG_SLAB
    bool '  Spinlock debugging' CONFIG_DEBUG_SPINLOCK
    bool '  Turn on compare-and-exchange bug checking (slow!)' CONFIG_IA64_DEBUG_CMPXCHG
diff -Nru a/arch/ia64/defconfig b/arch/ia64/defconfig
--- a/arch/ia64/defconfig	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/defconfig	Fri Mar 15 17:51:01 2002
@@ -8,6 +8,14 @@
 CONFIG_EXPERIMENTAL=y
 
 #
+# General setup
+#
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+
+#
 # Loadable module support
 #
 CONFIG_MODULES=y
@@ -50,21 +58,17 @@
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
 CONFIG_EFI_VARS=y
-CONFIG_NET=y
-CONFIG_SYSVIPC=y
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
 CONFIG_BINFMT_ELF=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_BUSMGR is not set
-# CONFIG_ACPI_SYS is not set
-# CONFIG_ACPI_CPU is not set
-# CONFIG_ACPI_BUTTON is not set
-# CONFIG_ACPI_AC is not set
-# CONFIG_ACPI_EC is not set
-# CONFIG_ACPI_CMBATT is not set
-# CONFIG_ACPI_THERMAL is not set
+CONFIG_ACPI_BUSMGR=y
+CONFIG_ACPI_SYS=y
+CONFIG_ACPI_CPU=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_AC=y
+CONFIG_ACPI_EC=y
+CONFIG_ACPI_CMBATT=y
+CONFIG_ACPI_THERMAL=y
 CONFIG_PCI=y
 CONFIG_PCI_NAMES=y
 # CONFIG_HOTPLUG is not set
@@ -80,7 +84,7 @@
 #
 CONFIG_PACKET=y
 CONFIG_PACKET_MMAP=y
-# CONFIG_NETLINK is not set
+# CONFIG_NETLINK_DEV is not set
 # CONFIG_NETFILTER is not set
 CONFIG_FILTER=y
 CONFIG_UNIX=y
@@ -90,6 +94,7 @@
 # CONFIG_IP_PNP is not set
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
 # CONFIG_INET_ECN is not set
 # CONFIG_SYN_COOKIES is not set
 # CONFIG_IPV6 is not set
@@ -128,6 +133,7 @@
 #
 # CONFIG_PNP is not set
 # CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
 
 #
 # Block devices
@@ -137,6 +143,7 @@
 # CONFIG_PARIDE is not set
 # CONFIG_BLK_CPQ_DA is not set
 # CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_CISS_SCSI_TAPE is not set
 # CONFIG_BLK_DEV_DAC960 is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_NBD is not set
@@ -144,6 +151,11 @@
 # CONFIG_BLK_DEV_INITRD is not set
 
 #
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
 # I2O device support
 #
 # CONFIG_I2O is not set
@@ -171,7 +183,7 @@
 CONFIG_IDE=y
 
 #
-# IDE, ATA and ATAPI Block devices
+# ATA and ATAPI Block devices
 #
 CONFIG_BLK_DEV_IDE=y
 
@@ -182,6 +194,7 @@
 # CONFIG_BLK_DEV_HD is not set
 CONFIG_BLK_DEV_IDEDISK=y
 CONFIG_IDEDISK_MULTI_MODE=y
+# CONFIG_IDEDISK_STROKE is not set
 # CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
 # CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
 # CONFIG_BLK_DEV_IDEDISK_IBM is not set
@@ -198,18 +211,18 @@
 CONFIG_BLK_DEV_IDESCSI=y
 
 #
-# IDE chipset support/bugfixes
+# IDE chipset support
 #
 # CONFIG_BLK_DEV_CMD640 is not set
 # CONFIG_BLK_DEV_CMD640_ENHANCED is not set
 # CONFIG_BLK_DEV_ISAPNP is not set
 # CONFIG_BLK_DEV_RZ1000 is not set
 CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
-# CONFIG_BLK_DEV_OFFBOARD is not set
 # CONFIG_IDEDMA_PCI_AUTO is not set
+# CONFIG_IDEDMA_ONLYDISK is not set
 CONFIG_BLK_DEV_IDEDMA=y
 # CONFIG_IDEDMA_PCI_WIP is not set
 # CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
@@ -229,6 +242,7 @@
 # CONFIG_PIIX_TUNING is not set
 # CONFIG_BLK_DEV_NS87415 is not set
 # CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC_ADMA is not set
 # CONFIG_BLK_DEV_PDC202XX is not set
 # CONFIG_PDC202XX_BURST is not set
 # CONFIG_PDC202XX_FORCE is not set
@@ -238,8 +252,8 @@
 # CONFIG_BLK_DEV_TRM290 is not set
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_IDE_CHIPSETS is not set
-# CONFIG_IDEDMA_AUTO is not set
 # CONFIG_IDEDMA_IVB is not set
+# CONFIG_IDEDMA_AUTO is not set
 # CONFIG_DMA_NONPCI is not set
 CONFIG_BLK_DEV_IDE_MODES=y
 # CONFIG_BLK_DEV_ATARAID is not set
@@ -264,7 +278,6 @@
 #
 # Some SCSI devices (e.g. CD jukebox) support multiple LUNs
 #
-CONFIG_SCSI_DEBUG_QUEUES=y
 # CONFIG_SCSI_MULTI_LUN is not set
 CONFIG_SCSI_CONSTANTS=y
 CONFIG_SCSI_LOGGING=y
@@ -299,6 +312,7 @@
 # CONFIG_SCSI_INIA100 is not set
 # CONFIG_SCSI_NCR53C406A is not set
 # CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
 # CONFIG_SCSI_NCR53C8XX is not set
 # CONFIG_SCSI_SYM53C8XX is not set
 # CONFIG_SCSI_PAS16 is not set
@@ -330,6 +344,7 @@
 # CONFIG_BONDING is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
 
 #
 # Ethernet (10 or 100Mbit)
@@ -339,7 +354,6 @@
 # CONFIG_HAPPYMEAL is not set
 # CONFIG_SUNBMAC is not set
 # CONFIG_SUNQE is not set
-# CONFIG_SUNLANCE is not set
 # CONFIG_SUNGEM is not set
 # CONFIG_NET_VENDOR_3COM is not set
 # CONFIG_LANCE is not set
@@ -352,11 +366,9 @@
 # CONFIG_ADAPTEC_STARFIRE is not set
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
-# CONFIG_TULIP is not set
-# CONFIG_DE4X5 is not set
 # CONFIG_DGRS is not set
-# CONFIG_DM9102 is not set
 CONFIG_EEPRO100=y
+# CONFIG_E100 is not set
 # CONFIG_LNE390 is not set
 # CONFIG_FEALNX is not set
 # CONFIG_NATSEMI is not set
@@ -368,12 +380,13 @@
 # CONFIG_8139TOO_PIO is not set
 # CONFIG_8139TOO_TUNE_TWISTER is not set
 # CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_NEW_RX_RESET is not set
 # CONFIG_SIS900 is not set
 # CONFIG_EPIC100 is not set
 # CONFIG_SUNDANCE is not set
 # CONFIG_TLAN is not set
 # CONFIG_VIA_RHINE is not set
-# CONFIG_WINBOND_840 is not set
+# CONFIG_VIA_RHINE_MMIO is not set
 # CONFIG_NET_POCKET is not set
 
 #
@@ -381,11 +394,13 @@
 #
 # CONFIG_ACENIC is not set
 # CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
 # CONFIG_MYRI_SBUS is not set
 # CONFIG_NS83820 is not set
 # CONFIG_HAMACHI is not set
 # CONFIG_YELLOWFIN is not set
 # CONFIG_SK98LIN is not set
+# CONFIG_TIGON3 is not set
 # CONFIG_FDDI is not set
 # CONFIG_HIPPI is not set
 # CONFIG_PLIP is not set
@@ -411,6 +426,11 @@
 # CONFIG_WAN is not set
 
 #
+# "Tulip" family network device support
+#
+# CONFIG_NET_TULIP is not set
+
+#
 # Amateur Radio support
 #
 # CONFIG_HAMRADIO is not set
@@ -426,7 +446,7 @@
 # CONFIG_CD_NO_IDESCSI is not set
 
 #
-# Input core support
+# Input device support
 #
 CONFIG_INPUT=y
 CONFIG_INPUT_KEYBDEV=y
@@ -435,6 +455,36 @@
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
 CONFIG_INPUT_EVDEV=y
+# CONFIG_GAMEPORT is not set
+CONFIG_SOUND_GAMEPORT=y
+# CONFIG_GAMEPORT_NS558 is not set
+# CONFIG_GAMEPORT_L4 is not set
+# CONFIG_INPUT_EMU10K1 is not set
+# CONFIG_GAMEPORT_PCIGAME is not set
+# CONFIG_GAMEPORT_FM801 is not set
+# CONFIG_GAMEPORT_CS461x is not set
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_JOYSTICK_ANALOG is not set
+# CONFIG_JOYSTICK_A3D is not set
+# CONFIG_JOYSTICK_ADI is not set
+# CONFIG_JOYSTICK_COBRA is not set
+# CONFIG_JOYSTICK_GF2K is not set
+# CONFIG_JOYSTICK_GRIP is not set
+# CONFIG_JOYSTICK_INTERACT is not set
+# CONFIG_JOYSTICK_SIDEWINDER is not set
+# CONFIG_JOYSTICK_TMDC is not set
+# CONFIG_JOYSTICK_IFORCE_USB is not set
+# CONFIG_JOYSTICK_IFORCE_232 is not set
+# CONFIG_JOYSTICK_WARRIOR is not set
+# CONFIG_JOYSTICK_MAGELLAN is not set
+# CONFIG_JOYSTICK_SPACEORB is not set
+# CONFIG_JOYSTICK_SPACEBALL is not set
+# CONFIG_JOYSTICK_STINGER is not set
+# CONFIG_JOYSTICK_DB9 is not set
+# CONFIG_JOYSTICK_GAMECON is not set
+# CONFIG_JOYSTICK_TURBOGRAFX is not set
 
 #
 # Character devices
@@ -443,7 +493,7 @@
 CONFIG_VT_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_SERIAL_CONSOLE=y
-# CONFIG_SERIAL_ACPI is not set
+CONFIG_SERIAL_ACPI=y
 # CONFIG_SERIAL_EXTENDED is not set
 # CONFIG_SERIAL_NONSTANDARD is not set
 CONFIG_UNIX98_PTYS=y
@@ -452,7 +502,14 @@
 #
 # I2C support
 #
-# CONFIG_I2C is not set
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+# CONFIG_I2C_PHILIPSPAR is not set
+# CONFIG_I2C_ELV is not set
+# CONFIG_I2C_VELLEMAN is not set
+# CONFIG_I2C_ALGOPCF is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PROC=y
 
 #
 # Mice
@@ -462,41 +519,6 @@
 CONFIG_PSMOUSE=y
 # CONFIG_82C710_MOUSE is not set
 # CONFIG_PC110_PAD is not set
-
-#
-# Joysticks
-#
-# CONFIG_INPUT_GAMEPORT is not set
-# CONFIG_INPUT_NS558 is not set
-# CONFIG_INPUT_LIGHTNING is not set
-# CONFIG_INPUT_PCIGAME is not set
-# CONFIG_INPUT_CS461X is not set
-# CONFIG_INPUT_EMU10K1 is not set
-CONFIG_INPUT_SERIO=y
-CONFIG_INPUT_SERPORT=y
-
-#
-# Joysticks
-#
-# CONFIG_INPUT_ANALOG is not set
-# CONFIG_INPUT_A3D is not set
-# CONFIG_INPUT_ADI is not set
-# CONFIG_INPUT_COBRA is not set
-# CONFIG_INPUT_GF2K is not set
-# CONFIG_INPUT_GRIP is not set
-# CONFIG_INPUT_INTERACT is not set
-# CONFIG_INPUT_TMDC is not set
-# CONFIG_INPUT_SIDEWINDER is not set
-# CONFIG_INPUT_IFORCE_USB is not set
-# CONFIG_INPUT_IFORCE_232 is not set
-# CONFIG_INPUT_WARRIOR is not set
-# CONFIG_INPUT_MAGELLAN is not set
-# CONFIG_INPUT_SPACEORB is not set
-# CONFIG_INPUT_SPACEBALL is not set
-# CONFIG_INPUT_STINGER is not set
-# CONFIG_INPUT_DB9 is not set
-# CONFIG_INPUT_GAMECON is not set
-# CONFIG_INPUT_TURBOGRAFX is not set
 # CONFIG_QIC02_TAPE is not set
 
 #
@@ -524,15 +546,12 @@
 # CONFIG_AGP_SIS is not set
 # CONFIG_AGP_ALI is not set
 # CONFIG_AGP_SWORKS is not set
-CONFIG_DRM=y
-# CONFIG_DRM_NEW is not set
-CONFIG_DRM_OLD=y
-CONFIG_DRM40_TDFX=y
-# CONFIG_DRM40_GAMMA is not set
-# CONFIG_DRM40_R128 is not set
-# CONFIG_DRM40_RADEON is not set
-# CONFIG_DRM40_I810 is not set
-# CONFIG_DRM40_MGA is not set
+CONFIG_DRM_TDFX=y
+# CONFIG_DRM_GAMMA is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_I810 is not set
+# CONFIG_DRM_MGA is not set
 
 #
 # Multimedia devices
@@ -548,12 +567,16 @@
 #
 # Video Adapters
 #
+# CONFIG_VIDEO_BT848 is not set
 # CONFIG_VIDEO_PMS is not set
 # CONFIG_VIDEO_CPIA is not set
 # CONFIG_VIDEO_SAA5249 is not set
 # CONFIG_TUNER_3036 is not set
 # CONFIG_VIDEO_STRADIS is not set
 # CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIDEO_ZORAN_BUZ is not set
+# CONFIG_VIDEO_ZORAN_DC10 is not set
+# CONFIG_VIDEO_ZORAN_LML33 is not set
 # CONFIG_VIDEO_ZR36120 is not set
 # CONFIG_VIDEO_MEYE is not set
 
@@ -584,11 +607,15 @@
 # CONFIG_AUTOFS4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
 # CONFIG_ADFS_FS is not set
 # CONFIG_ADFS_FS_RW is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
 # CONFIG_BFS_FS is not set
+CONFIG_EXT3_FS=m
+CONFIG_JBD=m
+CONFIG_JBD_DEBUG=y
 CONFIG_FAT_FS=y
 CONFIG_MSDOS_FS=y
 # CONFIG_UMSDOS_FS is not set
@@ -598,10 +625,13 @@
 # CONFIG_JFFS2_FS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_TMPFS is not set
-# CONFIG_RAMFS is not set
+CONFIG_RAMFS=y
 CONFIG_ISO9660_FS=y
 # CONFIG_JOLIET is not set
 # CONFIG_ZISOFS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
@@ -626,11 +656,13 @@
 # Network File Systems
 #
 # CONFIG_CODA_FS is not set
+# CONFIG_INTERMEZZO_FS is not set
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
 # CONFIG_ROOT_NFS is not set
 CONFIG_NFSD=y
 CONFIG_NFSD_V3=y
+# CONFIG_NFSD_TCP is not set
 CONFIG_SUNRPC=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
@@ -645,7 +677,6 @@
 # CONFIG_NCPFS_NLS is not set
 # CONFIG_NCPFS_EXTRAS is not set
 # CONFIG_ZISOFS_FS is not set
-# CONFIG_ZLIB_FS_INFLATE is not set
 
 #
 # Partition Types
@@ -667,6 +698,7 @@
 # CONFIG_SGI_PARTITION is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_SUN_PARTITION is not set
+CONFIG_EFI_PARTITION=y
 # CONFIG_SMB_NLS is not set
 CONFIG_NLS=y
 
@@ -725,6 +757,11 @@
 # Sound
 #
 CONFIG_SOUND=y
+
+#
+# Open Sound System
+#
+CONFIG_SOUND_PRIME=y
 # CONFIG_SOUND_BT878 is not set
 # CONFIG_SOUND_CMPCI is not set
 # CONFIG_SOUND_EMU10K1 is not set
@@ -748,6 +785,11 @@
 # CONFIG_SOUND_TVMIXER is not set
 
 #
+# Advanced Linux Sound Architecture
+#
+# CONFIG_SND is not set
+
+#
 # USB support
 #
 CONFIG_USB=y
@@ -761,8 +803,10 @@
 # CONFIG_USB_LONG_TIMEOUT is not set
 
 #
-# USB Controllers
+# USB Host Controller Drivers
 #
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
 CONFIG_USB_UHCI=m
 # CONFIG_USB_UHCI_ALT is not set
 # CONFIG_USB_OHCI is not set
@@ -771,6 +815,7 @@
 # USB Device Class drivers
 #
 # CONFIG_USB_AUDIO is not set
+# CONFIG_USB_EMI26 is not set
 # CONFIG_USB_BLUETOOTH is not set
 # CONFIG_USB_STORAGE is not set
 # CONFIG_USB_STORAGE_DEBUG is not set
@@ -809,8 +854,11 @@
 # CONFIG_USB_OV511 is not set
 # CONFIG_USB_PWC is not set
 # CONFIG_USB_SE401 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_VICAM is not set
 # CONFIG_USB_DSBR is not set
 # CONFIG_USB_DABUSB is not set
+# CONFIG_USB_KONICAWC is not set
 
 #
 # USB Network adaptors
@@ -837,6 +885,7 @@
 # CONFIG_USB_SERIAL_EMPEG is not set
 # CONFIG_USB_SERIAL_FTDI_SIO is not set
 # CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
 # CONFIG_USB_SERIAL_IR is not set
 # CONFIG_USB_SERIAL_EDGEPORT is not set
 # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
@@ -850,6 +899,7 @@
 # CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
 # CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
 # CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_KLSI is not set
 # CONFIG_USB_SERIAL_PL2303 is not set
 # CONFIG_USB_SERIAL_CYBERJACK is not set
 # CONFIG_USB_SERIAL_XIRCOM is not set
@@ -859,6 +909,14 @@
 # USB Miscellaneous drivers
 #
 # CONFIG_USB_RIO500 is not set
+# CONFIG_USB_AUERSWALD is not set
+
+#
+# Library routines
+#
+# CONFIG_CRC32 is not set
+# CONFIG_ZLIB_INFLATE is not set
+# CONFIG_ZLIB_DEFLATE is not set
 
 #
 # Bluetooth support
@@ -874,7 +932,16 @@
 CONFIG_IA64_PRINT_HAZARDS=y
 # CONFIG_DISABLE_VHPT is not set
 CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
 # CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_SPINLOCK is not set
 # CONFIG_IA64_DEBUG_CMPXCHG is not set
 # CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/dig/setup.c b/arch/ia64/dig/setup.c
--- a/arch/ia64/dig/setup.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/dig/setup.c	Fri Mar 15 17:51:02 2002
@@ -33,6 +33,7 @@
  * is sufficient (the IDE driver will autodetect the drive geometry).
  */
 char drive_info[4*16];
+extern int pcat_compat;
 
 unsigned char aux_device_present = 0xaa;	/* XXX remove this when legacy I/O is gone */
 
@@ -81,13 +82,19 @@
 	screen_info.orig_video_ega_bx = 3;	/* XXX fake */
 }
 
-void
+void __init
 dig_irq_init (void)
 {
-	/*
-	 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
-	 * enabled.
-	 */
-	outb(0xff, 0xA1);
-	outb(0xff, 0x21);
+	if (pcat_compat) {
+		/*
+		 * Disable the compatibility mode interrupts (8259 style), needs IN/OUT support
+		 * enabled.
+		 */
+		printk("%s: Disabling PC-AT compatible 8259 interrupts\n", __FUNCTION__);
+		outb(0xff, 0xA1);
+		outb(0xff, 0x21);
+	} else {
+		printk("%s: System doesn't have PC-AT compatible dual-8259 setup. "
+		       "Nothing to be done\n", __FUNCTION__);
+	}
 }
diff -Nru a/arch/ia64/hp/Makefile b/arch/ia64/hp/Makefile
--- a/arch/ia64/hp/Makefile	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/hp/Makefile	Fri Mar 15 17:51:03 2002
@@ -1,6 +1,8 @@
 #
 # ia64/platform/hp/Makefile
 #
+# Copyright (C) 2002 Hewlett-Packard Co.
+#	David Mosberger-Tang <davidm@hpl.hp.com>
 # Copyright (C) 1999 Silicon Graphics, Inc.
 # Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
 #
@@ -11,6 +13,10 @@
 
 obj-y := hpsim_console.o hpsim_irq.o hpsim_setup.o
 obj-$(CONFIG_IA64_GENERIC) += hpsim_machvec.o
+
+obj-$(CONFIG_SIMETH)	+= simeth.o
+obj-$(CONFIG_SIM_SERIAL) += simserial.o
+obj-$(CONFIG_SCSI_SIM)	+= simscsi.o
 
 clean::
 
diff -Nru a/arch/ia64/hp/hpsim_console.c b/arch/ia64/hp/hpsim_console.c
--- a/arch/ia64/hp/hpsim_console.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/hp/hpsim_console.c	Fri Mar 15 17:51:02 2002
@@ -1,15 +1,18 @@
 /*
  * Platform dependent support for HP simulator.
  *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Vijay Chander <vijay@engr.sgi.com>
  */
+#include <linux/config.h>
+
 #include <linux/init.h>
 #include <linux/kernel.h>
 #include <linux/param.h>
 #include <linux/string.h>
 #include <linux/types.h>
+#include <linux/tty.h>
 #include <linux/kdev_t.h>
 #include <linux/console.h>
 
@@ -57,5 +60,5 @@
 static kdev_t
 simcons_console_device (struct console *c)
 {
-	return MKDEV(TTY_MAJOR, 64 + c->index);
+	return mk_kdev(TTY_MAJOR, 64 + c->index);
 }
diff -Nru a/arch/ia64/hp/simeth.c b/arch/ia64/hp/simeth.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/hp/simeth.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,533 @@
+/*
+ * Simulated Ethernet Driver
+ *
+ * Copyright (C) 1999-2001 Hewlett-Packard Co
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/in.h>
+#include <linux/string.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/inetdevice.h>
+#include <linux/if_ether.h>
+#include <linux/if_arp.h>
+#include <linux/skbuff.h>
+#include <linux/notifier.h>
+#include <asm/bitops.h>
+#include <asm/system.h>
+#include <asm/irq.h>
+
+#define SIMETH_RECV_MAX	10
+
+/*
+ * Maximum possible received frame for Ethernet.
+ * We preallocate an sk_buff of that size to avoid costly
+ * memcpy for temporary buffer into sk_buff. We do basically
+ * what's done in other drivers, like eepro with a ring.
+ * The difference is, of course, that we don't have real DMA !!!
+ */
+#define SIMETH_FRAME_SIZE	ETH_FRAME_LEN
+
+
+#define SSC_NETDEV_PROBE		100
+#define SSC_NETDEV_SEND			101
+#define SSC_NETDEV_RECV			102
+#define SSC_NETDEV_ATTACH		103
+#define SSC_NETDEV_DETACH		104
+
+#define NETWORK_INTR			8
+
+struct simeth_local {
+	struct net_device_stats stats;
+	int 			simfd;	 /* descriptor in the simulator */
+};
+
+static int simeth_probe1(void);
+static int simeth_open(struct net_device *dev);
+static int simeth_close(struct net_device *dev);
+static int simeth_tx(struct sk_buff *skb, struct net_device *dev);
+static int simeth_rx(struct net_device *dev);
+static struct net_device_stats *simeth_get_stats(struct net_device *dev);
+static void simeth_interrupt(int irq, void *dev_id, struct pt_regs * regs);
+static void set_multicast_list(struct net_device *dev);
+static int simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr);
+
+static char *simeth_version="0.3";
+
+/*
+ * This variable is used to establish a mapping between the Linux/ia64 kernel
+ * and the host linux kernel.
+ *
+ * As of today, we support only one card, even though most of the code
+ * is ready for many more. The mapping is then:
+ *	linux/ia64 -> linux/x86
+ * 	   eth0    -> eth1
+ *
+ * In the future, we some string operations, we could easily support up
+ * to 10 cards (0-9).
+ *
+ * The default mapping can be changed on the kernel command line by
+ * specifying simeth=ethX (or whatever string you want).
+ */
+static char *simeth_device="eth0";	 /* default host interface to use */
+
+
+
+static volatile unsigned int card_count; /* how many cards "found" so far */
+static int simeth_debug;		/* set to 1 to get debug information */
+
+/*
+ * Used to catch IFF_UP & IFF_DOWN events
+ */
+static struct notifier_block simeth_dev_notifier = {
+	simeth_device_event,
+	0
+};
+
+
+/*
+ * Function used when using a kernel command line option.
+ *
+ * Format: simeth=interface_name (like eth0)
+ */
+static int __init
+simeth_setup(char *str)
+{
+	simeth_device = str;
+	return 1;
+}
+
+__setup("simeth=", simeth_setup);
+
+/*
+ * Function used to probe for simeth devices when not installed
+ * as a loadable module
+ */
+
+int __init
+simeth_probe (void)
+{
+	int r;
+
+	printk("simeth: v%s\n", simeth_version);
+
+	r = simeth_probe1();
+
+	if (r == 0) register_netdevice_notifier(&simeth_dev_notifier);
+
+	return r;
+}
+
+extern long ia64_ssc (long, long, long, long, int);
+extern void ia64_ssc_connect_irq (long intr, long irq);
+
+static inline int
+netdev_probe(char *name, unsigned char *ether)
+{
+	return ia64_ssc(__pa(name), __pa(ether), 0,0, SSC_NETDEV_PROBE);
+}
+
+
+static inline int
+netdev_connect(int irq)
+{
+	/* XXX Fix me
+	 * this does not support multiple cards
+	 * also no return value
+	 */
+	ia64_ssc_connect_irq(NETWORK_INTR, irq);
+	return 0;
+}
+
+static inline int
+netdev_attach(int fd, int irq, unsigned int ipaddr)
+{
+	/* this puts the host interface in the right mode (start interupting) */
+	return ia64_ssc(fd, ipaddr, 0,0, SSC_NETDEV_ATTACH);
+}
+
+
+static inline int
+netdev_detach(int fd)
+{
+	/*
+	 * inactivate the host interface (don't interrupt anymore) */
+	return ia64_ssc(fd, 0,0,0, SSC_NETDEV_DETACH);
+}
+
+static inline int
+netdev_send(int fd, unsigned char *buf, unsigned int len)
+{
+	return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_SEND);
+}
+
+static inline int
+netdev_read(int fd, unsigned char *buf, unsigned int len)
+{
+	return ia64_ssc(fd, __pa(buf), len, 0, SSC_NETDEV_RECV);
+}
+
+/*
+ * Function shared with module code, so cannot be in init section
+ *
+ * So far this function "detects" only one card (test_&_set) but could
+ * be extended easily.
+ *
+ * Return:
+ * 	- -ENODEV is no device found
+ *	- -ENOMEM is no more memory
+ *	- 0 otherwise
+ */
+static int
+simeth_probe1(void)
+{
+	unsigned char mac_addr[ETH_ALEN];
+	struct simeth_local *local;
+	struct net_device *dev;
+	int fd, i;
+
+	/*
+	 * XXX Fix me
+	 * let's support just one card for now
+	 */
+	if (test_and_set_bit(0, &card_count))
+		return -ENODEV;
+
+	/*
+	 * check with the simulator for the device
+	 */
+	fd = netdev_probe(simeth_device, mac_addr);
+	if (fd == -1)
+		return -ENODEV;
+
+	dev = init_etherdev(NULL, sizeof(struct simeth_local));
+	if (!dev)
+		return -ENOMEM;
+
+	memcpy(dev->dev_addr, mac_addr, sizeof(mac_addr));
+
+	dev->irq = ia64_alloc_irq();
+
+	/*
+	 * attach the interrupt in the simulator, this does enable interrupts
+	 * until a netdev_attach() is called
+	 */
+	netdev_connect(dev->irq);
+
+	memset(dev->priv, 0, sizeof(struct simeth_local));
+
+	local = dev->priv;
+	local->simfd = fd; /* keep track of underlying file descriptor */
+
+	dev->open		= simeth_open;
+	dev->stop		= simeth_close;
+	dev->hard_start_xmit	= simeth_tx;
+	dev->get_stats		= simeth_get_stats;
+	dev->set_multicast_list = set_multicast_list; /* no yet used */
+
+	/* Fill in the fields of the device structure with ethernet-generic values. */
+	ether_setup(dev);
+
+	printk("%s: hosteth=%s simfd=%d, HwAddr", dev->name, simeth_device, local->simfd);
+	for(i = 0; i < ETH_ALEN; i++) {
+		printk(" %2.2x", dev->dev_addr[i]);
+	}
+	printk(", IRQ %d\n", dev->irq);
+
+		return 0;
+}
+
+/*
+ * actually binds the device to an interrupt vector
+ */
+static int
+simeth_open(struct net_device *dev)
+{
+	if (request_irq(dev->irq, simeth_interrupt, 0, "simeth", dev)) {
+		printk ("simeth: unable to get IRQ %d.\n", dev->irq);
+		return -EAGAIN;
+	}
+
+	netif_start_queue(dev);
+
+	return 0;
+}
+
+/* copied from lapbether.c */
+static __inline__ int dev_is_ethdev(struct net_device *dev)
+{
+       return ( dev->type == ARPHRD_ETHER && strncmp(dev->name, "dummy", 5));
+}
+
+
+/*
+ * Handler for IFF_UP or IFF_DOWN
+ *
+ * The reason for that is that we don't want to be interrupted when the
+ * interface is down. There is no way to unconnect in the simualtor. Instead
+ * we use this function to shutdown packet processing in the frame filter
+ * in the simulator. Thus no interrupts are generated
+ *
+ *
+ * That's also the place where we pass the IP address of this device to the
+ * simulator so that that we can start filtering packets for it
+ *
+ * There may be a better way of doing this, but I don't know which yet.
+ */
+static int
+simeth_device_event(struct notifier_block *this,unsigned long event, void *ptr)
+{
+	struct net_device *dev = (struct net_device *)ptr;
+	struct simeth_local *local;
+	struct in_device *in_dev;
+	struct in_ifaddr **ifap = NULL;
+	struct in_ifaddr *ifa = NULL;
+	int r;
+
+
+	if ( ! dev ) {
+		printk(KERN_WARNING "simeth_device_event dev=0\n");
+		return NOTIFY_DONE;
+	}
+
+	if ( event != NETDEV_UP && event != NETDEV_DOWN ) return NOTIFY_DONE;
+
+	/*
+	 * Check whether or not it's for an ethernet device
+	 *
+	 * XXX Fixme: This works only as long as we support one
+	 * type of ethernet device.
+	 */
+	if ( !dev_is_ethdev(dev) ) return NOTIFY_DONE;
+
+	if ((in_dev=dev->ip_ptr) != NULL) {
+		for (ifap=&in_dev->ifa_list; (ifa=*ifap) != NULL; ifap=&ifa->ifa_next)
+			if (strcmp(dev->name, ifa->ifa_label) == 0) break;
+	}
+	if ( ifa == NULL ) {
+		printk("simeth_open: can't find device %s's ifa\n", dev->name);
+		return NOTIFY_DONE;
+	}
+
+	printk("simeth_device_event: %s ipaddr=0x%x\n", dev->name, htonl(ifa->ifa_local));
+
+	/*
+	 * XXX Fix me
+	 * if the device was up, and we're simply reconfiguring it, not sure
+	 * we get DOWN then UP.
+	 */
+
+	local = dev->priv;
+	/* now do it for real */
+	r = event == NETDEV_UP ?
+		netdev_attach(local->simfd, dev->irq, htonl(ifa->ifa_local)):
+		netdev_detach(local->simfd);
+
+	printk("simeth: netdev_attach/detach: event=%s ->%d\n", event == NETDEV_UP ? "attach":"detach", r);
+
+	return NOTIFY_DONE;
+}
+
+static int
+simeth_close(struct net_device *dev)
+{
+	netif_stop_queue(dev);
+
+	free_irq(dev->irq, dev);
+
+	return 0;
+}
+
+/*
+ * Only used for debug
+ */
+static void
+frame_print(unsigned char *from, unsigned char *frame, int len)
+{
+	int i;
+
+	printk("%s: (%d) %02x", from, len, frame[0] & 0xff);
+	for(i=1; i < 6; i++ ) {
+		printk(":%02x", frame[i] &0xff);
+	}
+	printk(" %2x", frame[6] &0xff);
+	for(i=7; i < 12; i++ ) {
+		printk(":%02x", frame[i] &0xff);
+	}
+	printk(" [%02x%02x]\n", frame[12], frame[13]);
+
+	for(i=14; i < len; i++ ) {
+		printk("%02x ", frame[i] &0xff);
+		if ( (i%10)==0) printk("\n");
+	}
+	printk("\n");
+}
+
+
+/*
+ * Function used to transmit of frame, very last one on the path before
+ * going to the simulator.
+ */
+static int
+simeth_tx(struct sk_buff *skb, struct net_device *dev)
+{
+	struct simeth_local *local = (struct simeth_local *)dev->priv;
+
+#if 0
+	/* ensure we have at least ETH_ZLEN bytes (min frame size) */
+	unsigned int length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
+	/* Where do the extra padding bytes comes from inthe skbuff ? */
+#else
+	/* the real driver in the host system is going to take care of that
+	 * or maybe it's the NIC itself.
+	 */
+	unsigned int length = skb->len;
+#endif
+
+	local->stats.tx_bytes += skb->len;
+	local->stats.tx_packets++;
+
+
+	if (simeth_debug > 5) frame_print("simeth_tx", skb->data, length);
+
+	netdev_send(local->simfd, skb->data, length);
+
+	/*
+	 * we are synchronous on write, so we don't simulate a
+	 * trasnmit complete interrupt, thus we don't need to arm a tx
+	 */
+
+	dev_kfree_skb(skb);
+	return 0;
+}
+
+static inline struct sk_buff *
+make_new_skb(struct net_device *dev)
+{
+	struct sk_buff *nskb;
+
+	/*
+	 * The +2 is used to make sure that the IP header is nicely
+	 * aligned (on 4byte boundary I assume 14+2=16)
+	 */
+	nskb = dev_alloc_skb(SIMETH_FRAME_SIZE + 2);
+	if ( nskb == NULL ) {
+		printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name);
+		return NULL;
+	}
+	nskb->dev = dev;
+
+	skb_reserve(nskb, 2);	/* Align IP on 16 byte boundaries */
+
+	skb_put(nskb,SIMETH_FRAME_SIZE);
+
+	return nskb;
+}
+
+/*
+ * called from interrupt handler to process a received frame
+ */
+static int
+simeth_rx(struct net_device *dev)
+{
+	struct simeth_local	*local;
+	struct sk_buff		*skb;
+	int			len;
+	int			rcv_count = SIMETH_RECV_MAX;
+
+	local = (struct simeth_local *)dev->priv;
+	/*
+	 * the loop concept has been borrowed from other drivers
+	 * looks to me like it's a throttling thing to avoid pushing to many
+	 * packets at one time into the stack. Making sure we can process them
+	 * upstream and make forward progress overall
+	 */
+	do {
+		if ( (skb=make_new_skb(dev)) == NULL ) {
+			printk(KERN_NOTICE "%s: memory squeeze. dropping packet.\n", dev->name);
+			local->stats.rx_dropped++;
+			return 0;
+		}
+		/*
+		 * Read only one frame at a time
+		 */
+		len = netdev_read(local->simfd, skb->data, SIMETH_FRAME_SIZE);
+		if ( len == 0 ) {
+			if ( simeth_debug > 0 ) printk(KERN_WARNING "%s: count=%d netdev_read=0\n", dev->name, SIMETH_RECV_MAX-rcv_count);
+			break;
+		}
+#if 0
+		/*
+		 * XXX Fix me
+		 * Should really do a csum+copy here
+		 */
+		memcpy(skb->data, frame, len);
+#endif
+		skb->protocol = eth_type_trans(skb, dev);
+
+		if ( simeth_debug > 6 ) frame_print("simeth_rx", skb->data, len);
+
+		/*
+		 * push the packet up & trigger software interrupt
+		 */
+		netif_rx(skb);
+
+		local->stats.rx_packets++;
+		local->stats.rx_bytes += len;
+
+	} while ( --rcv_count );
+
+	return len; /* 0 = nothing left to read, otherwise, we can try again */
+}
+
+/*
+ * Interrupt handler (Yes, we can do it too !!!)
+ */
+static void
+simeth_interrupt(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct net_device *dev = dev_id;
+
+	if ( dev == NULL ) {
+		printk(KERN_WARNING "simeth: irq %d for unknown device\n", irq);
+		return;
+	}
+
+	/*
+	 * very simple loop because we get interrupts only when receving
+	 */
+	while (simeth_rx(dev));
+}
+
+static struct net_device_stats *
+simeth_get_stats(struct net_device *dev)
+{
+	struct simeth_local  *local = (struct simeth_local *) dev->priv;
+
+	return &local->stats;
+}
+
+/* fake multicast ability */
+static void
+set_multicast_list(struct net_device *dev)
+{
+	printk(KERN_WARNING "%s: set_multicast_list called\n", dev->name);
+}
+
+#ifdef CONFIG_NET_FASTROUTE
+static int
+simeth_accept_fastpath(struct net_device *dev, struct dst_entry *dst)
+{
+	printk(KERN_WARNING "%s: simeth_accept_fastpath called\n", dev->name);
+	return -1;
+}
+#endif
+
+__initcall(simeth_probe);
diff -Nru a/arch/ia64/hp/simscsi.c b/arch/ia64/hp/simscsi.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/hp/simscsi.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,368 @@
+/*
+ * Simulated SCSI driver.
+ *
+ * Copyright (C) 1999, 2001-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * 02/01/15 David Mosberger	Updated for v2.5.1
+ * 99/12/18 David Mosberger	Added support for READ10/WRITE10 needed by linux v2.3.33
+ */
+#include <linux/config.h>
+#include <linux/blk.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/timer.h>
+
+#include <scsi/scsi.h>
+
+#include <asm/irq.h>
+
+#include "../drivers/scsi/scsi.h"
+#include "../drivers/scsi/sd.h"
+#include "../drivers/scsi/hosts.h"
+#include "simscsi.h"
+
+#define DEBUG_SIMSCSI	1
+
+/* Simulator system calls: */
+
+#define SSC_OPEN			50
+#define SSC_CLOSE			51
+#define SSC_READ			52
+#define SSC_WRITE			53
+#define SSC_GET_COMPLETION		54
+#define SSC_WAIT_COMPLETION		55
+
+#define SSC_WRITE_ACCESS		2
+#define SSC_READ_ACCESS			1
+
+#if DEBUG_SIMSCSI
+  int simscsi_debug;
+# define DBG	simscsi_debug
+#else
+# define DBG	0
+#endif
+
+static struct Scsi_Host *host;
+
+static void simscsi_interrupt (unsigned long val);
+DECLARE_TASKLET(simscsi_tasklet, simscsi_interrupt, 0);
+
+struct disk_req {
+	unsigned long addr;
+	unsigned len;
+};
+
+struct disk_stat {
+	int fd;
+	unsigned count;
+};
+
+extern long ia64_ssc (long arg0, long arg1, long arg2, long arg3, int nr);
+
+static int desc[8] = { -1, -1, -1, -1, -1, -1, -1, -1 };
+
+static struct queue_entry {
+	Scsi_Cmnd *sc;
+} queue[SIMSCSI_REQ_QUEUE_LEN];
+
+static int rd, wr;
+static atomic_t num_reqs = ATOMIC_INIT(0);
+
+/* base name for default disks */
+static char *simscsi_root = DEFAULT_SIMSCSI_ROOT;
+
+#define MAX_ROOT_LEN	128
+
+/*
+ * used to setup a new base for disk images
+ * to use /foo/bar/disk[a-z] as disk images
+ * you have to specify simscsi=/foo/bar/disk on the command line
+ */
+static int __init
+simscsi_setup (char *s)
+{
+	/* XXX Fix me we may need to strcpy() ? */
+	if (strlen(s) > MAX_ROOT_LEN) {
+		printk("simscsi_setup: prefix too long---using default %s\n", simscsi_root);
+	}
+	simscsi_root = s;
+	return 1;
+}
+
+__setup("simscsi=", simscsi_setup);
+
+static void
+simscsi_interrupt (unsigned long val)
+{
+	Scsi_Cmnd *sc;
+
+	while ((sc = queue[rd].sc) != 0) {
+		atomic_dec(&num_reqs);
+		queue[rd].sc = 0;
+		if (DBG)
+			printk("simscsi_interrupt: done with %ld\n", sc->serial_number);
+		(*sc->scsi_done)(sc);
+		rd = (rd + 1) % SIMSCSI_REQ_QUEUE_LEN;
+	}
+}
+
+int
+simscsi_detect (Scsi_Host_Template *templ)
+{
+	templ->proc_name = "simscsi";
+	host = scsi_register(templ, 0);
+	return 1;	/* fake one SCSI host adapter */
+}
+
+int
+simscsi_release (struct Scsi_Host *host)
+{
+	return 0;	/* this is easy...  */
+}
+
+const char *
+simscsi_info (struct Scsi_Host *host)
+{
+	return "simulated SCSI host adapter";
+}
+
+int
+simscsi_abort (Scsi_Cmnd *cmd)
+{
+	printk ("simscsi_abort: unimplemented\n");
+	return SCSI_ABORT_SUCCESS;
+}
+
+int
+simscsi_reset (Scsi_Cmnd *cmd, unsigned int reset_flags)
+{
+	printk ("simscsi_reset: unimplemented\n");
+	return SCSI_RESET_SUCCESS;
+}
+
+int
+simscsi_biosparam (Disk *disk, kdev_t n, int ip[])
+{
+	int size = disk->capacity;
+
+	ip[0] = 64;
+	ip[1] = 32;
+	ip[2] = size >> 11;
+	return 0;
+}
+
+static void
+simscsi_readwrite (Scsi_Cmnd *sc, int mode, unsigned long offset, unsigned long len)
+{
+	struct disk_stat stat;
+	struct disk_req req;
+
+	req.addr = __pa(sc->request_buffer);
+	req.len  = len;			/* # of bytes to transfer */
+
+	if (sc->request_bufflen < req.len)
+		return;
+
+	stat.fd = desc[sc->target];
+	if (DBG)
+		printk("simscsi_%s @ %lx (off %lx)\n",
+		       mode == SSC_READ ? "read":"write", req.addr, offset);
+	ia64_ssc(stat.fd, 1, __pa(&req), offset, mode);
+	ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
+
+	if (stat.count == req.len) {
+		sc->result = GOOD;
+	} else {
+		sc->result = DID_ERROR << 16;
+	}
+}
+
+static void
+simscsi_sg_readwrite (Scsi_Cmnd *sc, int mode, unsigned long offset)
+{
+	int list_len = sc->use_sg;
+	struct scatterlist *sl = (struct scatterlist *)sc->buffer;
+	struct disk_stat stat;
+	struct disk_req req;
+
+	stat.fd = desc[sc->target];
+
+	while (list_len) {
+		req.addr = __pa(page_address(sl->page) + sl->offset);
+		req.len  = sl->length;
+		if (DBG)
+			printk("simscsi_sg_%s @ %lx (off %lx) use_sg=%d len=%d\n",
+			       mode == SSC_READ ? "read":"write", req.addr, offset,
+			       list_len, sl->length);
+		ia64_ssc(stat.fd, 1, __pa(&req), offset, mode);
+		ia64_ssc(__pa(&stat), 0, 0, 0, SSC_WAIT_COMPLETION);
+
+		/* should not happen in our case */
+		if (stat.count != req.len) {
+			sc->result = DID_ERROR << 16;
+			return;
+		}
+		offset +=  sl->length;
+		sl++;
+		list_len--;
+	}
+	sc->result = GOOD;
+}
+
+/*
+ * function handling both READ_6/WRITE_6 (non-scatter/gather mode)
+ * commands.
+ * Added 02/26/99 S.Eranian
+ */
+static void
+simscsi_readwrite6 (Scsi_Cmnd *sc, int mode)
+{
+	unsigned long offset;
+
+	offset = (((sc->cmnd[1] & 0x1f) << 16) | (sc->cmnd[2] << 8) | sc->cmnd[3])*512;
+	if (sc->use_sg > 0)
+		simscsi_sg_readwrite(sc, mode, offset);
+	else
+		simscsi_readwrite(sc, mode, offset, sc->cmnd[4]*512);
+}
+
+
+static void
+simscsi_readwrite10 (Scsi_Cmnd *sc, int mode)
+{
+	unsigned long offset;
+
+	offset = (  (sc->cmnd[2] << 24) | (sc->cmnd[3] << 16)
+		  | (sc->cmnd[4] <<  8) | (sc->cmnd[5] <<  0))*512;
+	if (sc->use_sg > 0)
+		simscsi_sg_readwrite(sc, mode, offset);
+	else
+		simscsi_readwrite(sc, mode, offset, ((sc->cmnd[7] << 8) | sc->cmnd[8])*512);
+}
+
+int
+simscsi_queuecommand (Scsi_Cmnd *sc, void (*done)(Scsi_Cmnd *))
+{
+	char fname[MAX_ROOT_LEN+16];
+	char *buf;
+#if DEBUG_SIMSCSI
+	register long sp asm ("sp");
+
+	if (DBG)
+		printk("simscsi_queuecommand: target=%d,cmnd=%u,sc=%lu,sp=%lx,done=%p\n",
+		       sc->target, sc->cmnd[0], sc->serial_number, sp, done);
+#endif
+
+	sc->result = DID_BAD_TARGET << 16;
+	sc->scsi_done = done;
+	if (sc->target <= 7 && sc->lun == 0) {
+		switch (sc->cmnd[0]) {
+		      case INQUIRY:
+			if (sc->request_bufflen < 35) {
+				break;
+			}
+			sprintf (fname, "%s%c", simscsi_root, 'a' + sc->target);
+			desc[sc->target] = ia64_ssc (__pa(fname), SSC_READ_ACCESS|SSC_WRITE_ACCESS,
+						     0, 0, SSC_OPEN);
+			if (desc[sc->target] < 0) {
+				/* disk doesn't exist... */
+				break;
+			}
+			buf = sc->request_buffer;
+			buf[0] = 0;	/* magnetic disk */
+			buf[1] = 0;	/* not a removable medium */
+			buf[2] = 2;	/* SCSI-2 compliant device */
+			buf[3] = 2;	/* SCSI-2 response data format */
+			buf[4] = 31;	/* additional length (bytes) */
+			buf[5] = 0;	/* reserved */
+			buf[6] = 0;	/* reserved */
+			buf[7] = 0;	/* various flags */
+			memcpy(buf + 8, "HP      SIMULATED DISK  0.00",  28);
+			sc->result = GOOD;
+			break;
+
+		      case TEST_UNIT_READY:
+			sc->result = GOOD;
+			break;
+
+		      case READ_6:
+			if (desc[sc->target] < 0 )
+				break;
+			simscsi_readwrite6(sc, SSC_READ);
+			break;
+
+		      case READ_10:
+			if (desc[sc->target] < 0 )
+				break;
+			simscsi_readwrite10(sc, SSC_READ);
+			break;
+
+		      case WRITE_6:
+			if (desc[sc->target] < 0)
+				break;
+			simscsi_readwrite6(sc, SSC_WRITE);
+			break;
+
+		      case WRITE_10:
+			if (desc[sc->target] < 0)
+				break;
+			simscsi_readwrite10(sc, SSC_WRITE);
+			break;
+
+
+		      case READ_CAPACITY:
+			if (desc[sc->target] < 0 || sc->request_bufflen < 8) {
+				break;
+			}
+			buf = sc->request_buffer;
+
+			/* pretend to be a 1GB disk (partition table contains real stuff): */
+			buf[0] = 0x00;
+			buf[1] = 0x1f;
+			buf[2] = 0xff;
+			buf[3] = 0xff;
+			/* set block size of 512 bytes: */
+			buf[4] = 0;
+			buf[5] = 0;
+			buf[6] = 2;
+			buf[7] = 0;
+			sc->result = GOOD;
+			break;
+
+		      case MODE_SENSE:
+			printk("MODE_SENSE\n");
+			break;
+
+		      case START_STOP:
+			printk("START_STOP\n");
+			break;
+
+		      default:
+			panic("simscsi: unknown SCSI command %u\n", sc->cmnd[0]);
+		}
+	}
+	if (sc->result == DID_BAD_TARGET) {
+		sc->result |= DRIVER_SENSE << 24;
+		sc->sense_buffer[0] = 0x70;
+		sc->sense_buffer[2] = 0x00;
+	}
+	if (atomic_read(&num_reqs) >= SIMSCSI_REQ_QUEUE_LEN) {
+		panic("Attempt to queue command while command is pending!!");
+	}
+	atomic_inc(&num_reqs);
+	queue[wr].sc = sc;
+	wr = (wr + 1) % SIMSCSI_REQ_QUEUE_LEN;
+
+	tasklet_schedule(&simscsi_tasklet);
+	return 0;
+}
+
+
+static Scsi_Host_Template driver_template = SIMSCSI;
+
+#define __initcall(fn)	late_initcall(fn)
+
+#include "../drivers/scsi/scsi_module.c"
diff -Nru a/arch/ia64/hp/simscsi.h b/arch/ia64/hp/simscsi.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/hp/simscsi.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,39 @@
+/*
+ * Simulated SCSI driver.
+ *
+ * Copyright (C) 1999 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#ifndef SIMSCSI_H
+#define SIMSCSI_H
+
+#define SIMSCSI_REQ_QUEUE_LEN	64
+
+#define DEFAULT_SIMSCSI_ROOT	"/var/ski-disks/sd"
+
+extern int simscsi_detect (Scsi_Host_Template *);
+extern int simscsi_release (struct Scsi_Host *);
+extern const char *simscsi_info (struct Scsi_Host *);
+extern int simscsi_queuecommand (Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
+extern int simscsi_abort (Scsi_Cmnd *);
+extern int simscsi_reset (Scsi_Cmnd *, unsigned int);
+extern int simscsi_biosparam (Disk *, kdev_t, int[]);
+
+#define SIMSCSI {					\
+	detect:			simscsi_detect,		\
+	release:		simscsi_release,	\
+	info:			simscsi_info,		\
+	queuecommand:		simscsi_queuecommand,	\
+	abort:			simscsi_abort,		\
+	reset:			simscsi_reset,		\
+	bios_param:		simscsi_biosparam,	\
+	can_queue:		SIMSCSI_REQ_QUEUE_LEN,	\
+	this_id:		-1,			\
+	sg_tablesize:		SG_ALL,			\
+	cmd_per_lun:		SIMSCSI_REQ_QUEUE_LEN,	\
+	present:		0,			\
+	unchecked_isa_dma:	0,			\
+	use_clustering:		DISABLE_CLUSTERING	\
+}
+
+#endif /* SIMSCSI_H */
diff -Nru a/arch/ia64/hp/simserial.c b/arch/ia64/hp/simserial.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/hp/simserial.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1104 @@
+/*
+ * Simulated Serial Driver (fake serial)
+ *
+ * This driver is mostly used for bringup purposes and will go away.
+ * It has a strong dependency on the system console. All outputs
+ * are rerouted to the same facility as the one used by printk which, in our
+ * case means sys_sim.c console (goes via the simulator). The code hereafter
+ * is completely leveraged from the serial.c driver.
+ *
+ * Copyright (C) 1999-2000 Hewlett-Packard Co
+ * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * 02/04/00 D. Mosberger	Merged in serial.c bug fixes in rs_close().
+ * 02/25/00 D. Mosberger	Synced up with 2.3.99pre-5 version of serial.c.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/major.h>
+#include <linux/fcntl.h>
+#include <linux/mm.h>
+#include <linux/malloc.h>
+#include <linux/console.h>
+#include <linux/module.h>
+#include <linux/serial.h>
+#include <linux/serialP.h>
+
+#include <asm/irq.h>
+#include <asm/uaccess.h>
+
+#ifdef CONFIG_KDB
+# include <linux/kdb.h>
+#endif
+
+#undef SIMSERIAL_DEBUG	/* define this to get some debug information */
+
+#define KEYBOARD_INTR	3	/* must match with simulator! */
+
+#define NR_PORTS	1	/* only one port for now */
+#define SERIAL_INLINE	1
+
+#ifdef SERIAL_INLINE
+#define _INLINE_ inline
+#endif
+
+#ifndef MIN
+#define MIN(a,b)	((a) < (b) ? (a) : (b))
+#endif
+
+#define IRQ_T(info) ((info->flags & ASYNC_SHARE_IRQ) ? SA_SHIRQ : SA_INTERRUPT)
+
+#define SSC_GETCHAR	21
+
+extern long ia64_ssc (long, long, long, long, int);
+extern void ia64_ssc_connect_irq (long intr, long irq);
+
+static char *serial_name = "SimSerial driver";
+static char *serial_version = "0.6";
+
+/*
+ * This has been extracted from asm/serial.h. We need one eventually but
+ * I don't know exactly what we're going to put in it so just fake one
+ * for now.
+ */
+#define BASE_BAUD ( 1843200 / 16 )
+
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+/*
+ * Most of the values here are meaningless to this particular driver.
+ * However some values must be preserved for the code (leveraged from serial.c
+ * to work correctly).
+ * port must not be 0
+ * type must not be UNKNOWN
+ * So I picked arbitrary (guess from where?) values instead
+ */
+static struct serial_state rs_table[NR_PORTS]={
+  /* UART CLK   PORT IRQ     FLAGS        */
+  { 0, BASE_BAUD, 0x3F8, 0, STD_COM_FLAGS,0,PORT_16550 }  /* ttyS0 */
+};
+
+/*
+ * Just for the fun of it !
+ */
+static struct serial_uart_config uart_config[] = {
+	{ "unknown", 1, 0 },
+	{ "8250", 1, 0 },
+	{ "16450", 1, 0 },
+	{ "16550", 1, 0 },
+	{ "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
+	{ "cirrus", 1, 0 },
+	{ "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
+	{ "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO |
+		  UART_STARTECH },
+	{ "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO},
+	{ 0, 0}
+};
+
+static struct tty_driver serial_driver, callout_driver;
+static int serial_refcount;
+
+static struct async_struct *IRQ_ports[NR_IRQS];
+static struct tty_struct *serial_table[NR_PORTS];
+static struct termios *serial_termios[NR_PORTS];
+static struct termios *serial_termios_locked[NR_PORTS];
+
+static struct console *console;
+
+static unsigned char *tmp_buf;
+static DECLARE_MUTEX(tmp_buf_sem);
+
+extern struct console *console_drivers; /* from kernel/printk.c */
+
+/*
+ * ------------------------------------------------------------
+ * rs_stop() and rs_start()
+ *
+ * This routines are called before setting or resetting tty->stopped.
+ * They enable or disable transmitter interrupts, as necessary.
+ * ------------------------------------------------------------
+ */
+static void rs_stop(struct tty_struct *tty)
+{
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_stop: tty->stopped=%d tty->hw_stopped=%d tty->flow_stopped=%d\n",
+		tty->stopped, tty->hw_stopped, tty->flow_stopped);
+#endif
+
+}
+
+static void rs_start(struct tty_struct *tty)
+{
+#if SIMSERIAL_DEBUG
+	printk("rs_start: tty->stopped=%d tty->hw_stopped=%d tty->flow_stopped=%d\n",
+		tty->stopped, tty->hw_stopped, tty->flow_stopped);
+#endif
+}
+
+static  void receive_chars(struct tty_struct *tty, struct pt_regs *regs)
+{
+	unsigned char ch;
+	static unsigned char seen_esc = 0;
+
+	while ( (ch = ia64_ssc(0, 0, 0, 0, SSC_GETCHAR)) ) {
+		if ( ch == 27 && seen_esc == 0 ) {
+			seen_esc = 1;
+			continue;
+		} else {
+			if ( seen_esc==1 && ch == 'O' ) {
+				seen_esc = 2;
+				continue;
+			} else if ( seen_esc == 2 ) {
+				if ( ch == 'P' ) show_state();		/* F1 key */
+				if ( ch == 'Q' ) show_buffers();	/* F2 key */
+#ifdef CONFIG_KDB
+				if ( ch == 'S' )
+					kdb(KDB_REASON_KEYBOARD, 0, (kdb_eframe_t) regs);
+#endif
+
+				seen_esc = 0;
+				continue;
+			}
+		}
+		seen_esc = 0;
+		if (tty->flip.count >= TTY_FLIPBUF_SIZE) break;
+
+		*tty->flip.char_buf_ptr = ch;
+
+		*tty->flip.flag_buf_ptr = 0;
+
+		tty->flip.flag_buf_ptr++;
+		tty->flip.char_buf_ptr++;
+		tty->flip.count++;
+	}
+	tty_flip_buffer_push(tty);
+}
+
+/*
+ * This is the serial driver's interrupt routine for a single port
+ */
+static void rs_interrupt_single(int irq, void *dev_id, struct pt_regs * regs)
+{
+	struct async_struct * info;
+
+	/*
+	 * I don't know exactly why they don't use the dev_id opaque data
+	 * pointer instead of this extra lookup table
+	 */
+	info = IRQ_ports[irq];
+	if (!info || !info->tty) {
+		printk("simrs_interrupt_single: info|tty=0 info=%p problem\n", info);
+		return;
+	}
+	/*
+	 * pretty simple in our case, because we only get interrupts
+	 * on inbound traffic
+	 */
+	receive_chars(info->tty, regs);
+}
+
+/*
+ * -------------------------------------------------------------------
+ * Here ends the serial interrupt routines.
+ * -------------------------------------------------------------------
+ */
+
+#if 0
+/*
+ * not really used in our situation so keep them commented out for now
+ */
+static DECLARE_TASK_QUEUE(tq_serial); /* used to be at the top of the file */
+static void do_serial_bh(void)
+{
+	run_task_queue(&tq_serial);
+	printk("do_serial_bh: called\n");
+}
+#endif
+
+static void do_softint(void *private_)
+{
+	printk("simserial: do_softint called\n");
+}
+
+static void rs_put_char(struct tty_struct *tty, unsigned char ch)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+	unsigned long flags;
+
+	if (!tty || !info->xmit.buf) return;
+
+	save_flags(flags); cli();
+	if (CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE) == 0) {
+		restore_flags(flags);
+		return;
+	}
+	info->xmit.buf[info->xmit.head] = ch;
+	info->xmit.head = (info->xmit.head + 1) & (SERIAL_XMIT_SIZE-1);
+	restore_flags(flags);
+}
+
+static _INLINE_ void transmit_chars(struct async_struct *info, int *intr_done)
+{
+	int count;
+	unsigned long flags;
+
+	save_flags(flags); cli();
+
+	if (info->x_char) {
+		char c = info->x_char;
+
+		console->write(console, &c, 1);
+
+		info->state->icount.tx++;
+		info->x_char = 0;
+
+		goto out;
+	}
+
+	if (info->xmit.head == info->xmit.tail || info->tty->stopped || info->tty->hw_stopped) {
+#ifdef SIMSERIAL_DEBUG
+		printk("transmit_chars: head=%d, tail=%d, stopped=%d\n",
+		       info->xmit.head, info->xmit.tail, info->tty->stopped);
+#endif
+		goto out;
+	}
+	/*
+	 * We removed the loop and try to do it in to chunks. We need
+	 * 2 operations maximum because it's a ring buffer.
+	 *
+	 * First from current to tail if possible.
+	 * Then from the beginning of the buffer until necessary
+	 */
+
+	count = MIN(CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE),
+		    SERIAL_XMIT_SIZE - info->xmit.tail);
+	console->write(console, info->xmit.buf+info->xmit.tail, count);
+
+	info->xmit.tail = (info->xmit.tail+count) & (SERIAL_XMIT_SIZE-1);
+
+	/*
+	 * We have more at the beginning of the buffer
+	 */
+	count = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+	if (count) {
+		console->write(console, info->xmit.buf, count);
+		info->xmit.tail += count;
+	}
+out:
+	restore_flags(flags);
+}
+
+static void rs_flush_chars(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	if (info->xmit.head == info->xmit.tail || tty->stopped || tty->hw_stopped ||
+	    !info->xmit.buf)
+		return;
+
+	transmit_chars(info, NULL);
+}
+
+
+static int rs_write(struct tty_struct * tty, int from_user,
+		    const unsigned char *buf, int count)
+{
+	int	c, ret = 0;
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+	unsigned long flags;
+
+	if (!tty || !info->xmit.buf || !tmp_buf) return 0;
+
+	save_flags(flags);
+	if (from_user) {
+		down(&tmp_buf_sem);
+		while (1) {
+			int c1;
+			c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+			if (count < c)
+				c = count;
+			if (c <= 0)
+				break;
+
+			c -= copy_from_user(tmp_buf, buf, c);
+			if (!c) {
+				if (!ret)
+					ret = -EFAULT;
+				break;
+			}
+			cli();
+			c1 = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+			if (c1 < c)
+				c = c1;
+			memcpy(info->xmit.buf + info->xmit.head, tmp_buf, c);
+			info->xmit.head = ((info->xmit.head + c) &
+					   (SERIAL_XMIT_SIZE-1));
+			restore_flags(flags);
+			buf += c;
+			count -= c;
+			ret += c;
+		}
+		up(&tmp_buf_sem);
+	} else {
+		cli();
+		while (1) {
+			c = CIRC_SPACE_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+			if (count < c)
+				c = count;
+			if (c <= 0) {
+				break;
+			}
+			memcpy(info->xmit.buf + info->xmit.head, buf, c);
+			info->xmit.head = ((info->xmit.head + c) &
+					   (SERIAL_XMIT_SIZE-1));
+			buf += c;
+			count -= c;
+			ret += c;
+		}
+		restore_flags(flags);
+	}
+	/*
+	 * Hey, we transmit directly from here in our case
+	 */
+	if (CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE)
+	    && !tty->stopped && !tty->hw_stopped) {
+		transmit_chars(info, NULL);
+	}
+	return ret;
+}
+
+static int rs_write_room(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+}
+
+static int rs_chars_in_buffer(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
+}
+
+static void rs_flush_buffer(struct tty_struct *tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+	unsigned long flags;
+
+	save_flags(flags); cli();
+	info->xmit.head = info->xmit.tail = 0;
+	restore_flags(flags);
+
+	wake_up_interruptible(&tty->write_wait);
+
+	if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
+	    tty->ldisc.write_wakeup)
+		(tty->ldisc.write_wakeup)(tty);
+}
+
+/*
+ * This function is used to send a high-priority XON/XOFF character to
+ * the device
+ */
+static void rs_send_xchar(struct tty_struct *tty, char ch)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	info->x_char = ch;
+	if (ch) {
+		/*
+		 * I guess we could call console->write() directly but
+		 * let's do that for now.
+		 */
+		transmit_chars(info, NULL);
+	}
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_throttle()
+ *
+ * This routine is called by the upper-layer tty layer to signal that
+ * incoming characters should be throttled.
+ * ------------------------------------------------------------
+ */
+static void rs_throttle(struct tty_struct * tty)
+{
+	if (I_IXOFF(tty)) rs_send_xchar(tty, STOP_CHAR(tty));
+
+	printk("simrs_throttle called\n");
+}
+
+static void rs_unthrottle(struct tty_struct * tty)
+{
+	struct async_struct *info = (struct async_struct *)tty->driver_data;
+
+	if (I_IXOFF(tty)) {
+		if (info->x_char)
+			info->x_char = 0;
+		else
+			rs_send_xchar(tty, START_CHAR(tty));
+	}
+	printk("simrs_unthrottle called\n");
+}
+
+/*
+ * rs_break() --- routine which turns the break handling on or off
+ */
+static void rs_break(struct tty_struct *tty, int break_state)
+{
+}
+
+static int rs_ioctl(struct tty_struct *tty, struct file * file,
+		    unsigned int cmd, unsigned long arg)
+{
+	if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
+	    (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGSTRUCT) &&
+	    (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
+		if (tty->flags & (1 << TTY_IO_ERROR))
+		    return -EIO;
+	}
+
+	switch (cmd) {
+		case TIOCMGET:
+			printk("rs_ioctl: TIOCMGET called\n");
+			return -EINVAL;
+		case TIOCMBIS:
+		case TIOCMBIC:
+		case TIOCMSET:
+			printk("rs_ioctl: TIOCMBIS/BIC/SET called\n");
+			return -EINVAL;
+		case TIOCGSERIAL:
+			printk("simrs_ioctl TIOCGSERIAL called\n");
+			return 0;
+		case TIOCSSERIAL:
+			printk("simrs_ioctl TIOCSSERIAL called\n");
+			return 0;
+		case TIOCSERCONFIG:
+			printk("rs_ioctl: TIOCSERCONFIG called\n");
+			return -EINVAL;
+
+		case TIOCSERGETLSR: /* Get line status register */
+			printk("rs_ioctl: TIOCSERGETLSR called\n");
+			return  -EINVAL;
+
+		case TIOCSERGSTRUCT:
+			printk("rs_ioctl: TIOCSERGSTRUCT called\n");
+#if 0
+			if (copy_to_user((struct async_struct *) arg,
+					 info, sizeof(struct async_struct)))
+				return -EFAULT;
+#endif
+			return 0;
+
+		/*
+		 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
+		 * - mask passed in arg for lines of interest
+		 *   (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
+		 * Caller should use TIOCGICOUNT to see which one it was
+		 */
+		case TIOCMIWAIT:
+			printk("rs_ioctl: TIOCMIWAIT: called\n");
+			return 0;
+		/*
+		 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
+		 * Return: write counters to the user passed counter struct
+		 * NB: both 1->0 and 0->1 transitions are counted except for
+		 *     RI where only 0->1 is counted.
+		 */
+		case TIOCGICOUNT:
+			printk("rs_ioctl: TIOCGICOUNT called\n");
+			return 0;
+
+		case TIOCSERGWILD:
+		case TIOCSERSWILD:
+			/* "setserial -W" is called in Debian boot */
+			printk ("TIOCSER?WILD ioctl obsolete, ignored.\n");
+			return 0;
+
+		default:
+			return -ENOIOCTLCMD;
+		}
+	return 0;
+}
+
+#define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
+
+static void rs_set_termios(struct tty_struct *tty, struct termios *old_termios)
+{
+	unsigned int cflag = tty->termios->c_cflag;
+
+	if (   (cflag == old_termios->c_cflag)
+	    && (   RELEVANT_IFLAG(tty->termios->c_iflag)
+		== RELEVANT_IFLAG(old_termios->c_iflag)))
+	  return;
+
+
+	/* Handle turning off CRTSCTS */
+	if ((old_termios->c_cflag & CRTSCTS) &&
+	    !(tty->termios->c_cflag & CRTSCTS)) {
+		tty->hw_stopped = 0;
+		rs_start(tty);
+	}
+}
+/*
+ * This routine will shutdown a serial port; interrupts are disabled, and
+ * DTR is dropped if the hangup on close termio flag is on.
+ */
+static void shutdown(struct async_struct * info)
+{
+	unsigned long	flags;
+	struct serial_state *state;
+	int		retval;
+
+	if (!(info->flags & ASYNC_INITIALIZED)) return;
+
+	state = info->state;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("Shutting down serial port %d (irq %d)....", info->line,
+	       state->irq);
+#endif
+
+	save_flags(flags); cli(); /* Disable interrupts */
+
+	/*
+	 * First unlink the serial port from the IRQ chain...
+	 */
+	if (info->next_port)
+		info->next_port->prev_port = info->prev_port;
+	if (info->prev_port)
+		info->prev_port->next_port = info->next_port;
+	else
+		IRQ_ports[state->irq] = info->next_port;
+
+	/*
+	 * Free the IRQ, if necessary
+	 */
+	if (state->irq && (!IRQ_ports[state->irq] ||
+			  !IRQ_ports[state->irq]->next_port)) {
+		if (IRQ_ports[state->irq]) {
+			free_irq(state->irq, NULL);
+			retval = request_irq(state->irq, rs_interrupt_single,
+					     IRQ_T(info), "serial", NULL);
+
+			if (retval)
+				printk("serial shutdown: request_irq: error %d"
+				       "  Couldn't reacquire IRQ.\n", retval);
+		} else
+			free_irq(state->irq, NULL);
+	}
+
+	if (info->xmit.buf) {
+		free_page((unsigned long) info->xmit.buf);
+		info->xmit.buf = 0;
+	}
+
+	if (info->tty) set_bit(TTY_IO_ERROR, &info->tty->flags);
+
+	info->flags &= ~ASYNC_INITIALIZED;
+	restore_flags(flags);
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_close()
+ *
+ * This routine is called when the serial port gets closed.  First, we
+ * wait for the last remaining data to be sent.  Then, we unlink its
+ * async structure from the interrupt chain if necessary, and we free
+ * that IRQ if nothing is left in the chain.
+ * ------------------------------------------------------------
+ */
+static void rs_close(struct tty_struct *tty, struct file * filp)
+{
+	struct async_struct * info = (struct async_struct *)tty->driver_data;
+	struct serial_state *state;
+	unsigned long flags;
+
+	if (!info ) return;
+
+	state = info->state;
+
+	save_flags(flags); cli();
+
+	if (tty_hung_up_p(filp)) {
+#ifdef SIMSERIAL_DEBUG
+		printk("rs_close: hung_up\n");
+#endif
+		MOD_DEC_USE_COUNT;
+		restore_flags(flags);
+		return;
+	}
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_close ttys%d, count = %d\n", info->line, state->count);
+#endif
+	if ((tty->count == 1) && (state->count != 1)) {
+		/*
+		 * Uh, oh.  tty->count is 1, which means that the tty
+		 * structure will be freed.  state->count should always
+		 * be one in these conditions.  If it's greater than
+		 * one, we've got real problems, since it means the
+		 * serial port won't be shutdown.
+		 */
+		printk("rs_close: bad serial port count; tty->count is 1, "
+		       "state->count is %d\n", state->count);
+		state->count = 1;
+	}
+	if (--state->count < 0) {
+		printk("rs_close: bad serial port count for ttys%d: %d\n",
+		       info->line, state->count);
+		state->count = 0;
+	}
+	if (state->count) {
+		MOD_DEC_USE_COUNT;
+		restore_flags(flags);
+		return;
+	}
+	info->flags |= ASYNC_CLOSING;
+	restore_flags(flags);
+
+	/*
+	 * Now we wait for the transmit buffer to clear; and we notify
+	 * the line discipline to only process XON/XOFF characters.
+	 */
+	shutdown(info);
+	if (tty->driver.flush_buffer) tty->driver.flush_buffer(tty);
+	if (tty->ldisc.flush_buffer) tty->ldisc.flush_buffer(tty);
+	info->event = 0;
+	info->tty = 0;
+	if (info->blocked_open) {
+		if (info->close_delay) {
+			current->state = TASK_INTERRUPTIBLE;
+			schedule_timeout(info->close_delay);
+		}
+		wake_up_interruptible(&info->open_wait);
+	}
+	info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE|ASYNC_CLOSING);
+	wake_up_interruptible(&info->close_wait);
+	MOD_DEC_USE_COUNT;
+}
+
+/*
+ * rs_wait_until_sent() --- wait until the transmitter is empty
+ */
+static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
+{
+}
+
+
+/*
+ * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
+ */
+static void rs_hangup(struct tty_struct *tty)
+{
+	struct async_struct * info = (struct async_struct *)tty->driver_data;
+	struct serial_state *state = info->state;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_hangup: called\n");
+#endif
+
+	state = info->state;
+
+	rs_flush_buffer(tty);
+	if (info->flags & ASYNC_CLOSING)
+		return;
+	shutdown(info);
+
+	info->event = 0;
+	state->count = 0;
+	info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CALLOUT_ACTIVE);
+	info->tty = 0;
+	wake_up_interruptible(&info->open_wait);
+}
+
+
+static int get_async_struct(int line, struct async_struct **ret_info)
+{
+	struct async_struct *info;
+	struct serial_state *sstate;
+
+	sstate = rs_table + line;
+	sstate->count++;
+	if (sstate->info) {
+		*ret_info = sstate->info;
+		return 0;
+	}
+	info = kmalloc(sizeof(struct async_struct), GFP_KERNEL);
+	if (!info) {
+		sstate->count--;
+		return -ENOMEM;
+	}
+	memset(info, 0, sizeof(struct async_struct));
+	init_waitqueue_head(&info->open_wait);
+	init_waitqueue_head(&info->close_wait);
+	init_waitqueue_head(&info->delta_msr_wait);
+	info->magic = SERIAL_MAGIC;
+	info->port = sstate->port;
+	info->flags = sstate->flags;
+	info->xmit_fifo_size = sstate->xmit_fifo_size;
+	info->line = line;
+	info->tqueue.routine = do_softint;
+	info->tqueue.data = info;
+	info->state = sstate;
+	if (sstate->info) {
+		kfree(info);
+		*ret_info = sstate->info;
+		return 0;
+	}
+	*ret_info = sstate->info = info;
+	return 0;
+}
+
+static int
+startup(struct async_struct *info)
+{
+	unsigned long flags;
+	int	retval=0;
+	void (*handler)(int, void *, struct pt_regs *);
+	struct serial_state *state= info->state;
+	unsigned long page;
+
+	page = get_free_page(GFP_KERNEL);
+	if (!page)
+		return -ENOMEM;
+
+	save_flags(flags); cli();
+
+	if (info->flags & ASYNC_INITIALIZED) {
+		free_page(page);
+		goto errout;
+	}
+
+	if (!state->port || !state->type) {
+		if (info->tty) set_bit(TTY_IO_ERROR, &info->tty->flags);
+		free_page(page);
+		goto errout;
+	}
+	if (info->xmit.buf)
+		free_page(page);
+	else
+		info->xmit.buf = (unsigned char *) page;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("startup: ttys%d (irq %d)...", info->line, state->irq);
+#endif
+
+	/*
+	 * Allocate the IRQ if necessary
+	 */
+	if (state->irq && (!IRQ_ports[state->irq] ||
+			  !IRQ_ports[state->irq]->next_port)) {
+		if (IRQ_ports[state->irq]) {
+			retval = -EBUSY;
+			goto errout;
+		} else
+			handler = rs_interrupt_single;
+
+		retval = request_irq(state->irq, handler, IRQ_T(info),
+				     "simserial", NULL);
+		if (retval) {
+			if (capable(CAP_SYS_ADMIN)) {
+				if (info->tty)
+					set_bit(TTY_IO_ERROR,
+						&info->tty->flags);
+				retval = 0;
+			}
+			goto errout;
+		}
+	}
+
+	/*
+	 * Insert serial port into IRQ chain.
+	 */
+	info->prev_port = 0;
+	info->next_port = IRQ_ports[state->irq];
+	if (info->next_port)
+		info->next_port->prev_port = info;
+	IRQ_ports[state->irq] = info;
+
+	if (info->tty) clear_bit(TTY_IO_ERROR, &info->tty->flags);
+
+	info->xmit.head = info->xmit.tail = 0;
+
+#if 0
+	/*
+	 * Set up serial timers...
+	 */
+	timer_table[RS_TIMER].expires = jiffies + 2*HZ/100;
+	timer_active |= 1 << RS_TIMER;
+#endif
+
+	/*
+	 * Set up the tty->alt_speed kludge
+	 */
+	if (info->tty) {
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_HI)
+			info->tty->alt_speed = 57600;
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_VHI)
+			info->tty->alt_speed = 115200;
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_SHI)
+			info->tty->alt_speed = 230400;
+		if ((info->flags & ASYNC_SPD_MASK) == ASYNC_SPD_WARP)
+			info->tty->alt_speed = 460800;
+	}
+
+	info->flags |= ASYNC_INITIALIZED;
+	restore_flags(flags);
+	return 0;
+
+errout:
+	restore_flags(flags);
+	return retval;
+}
+
+
+/*
+ * This routine is called whenever a serial port is opened.  It
+ * enables interrupts for a serial port, linking in its async structure into
+ * the IRQ chain.   It also performs the serial-specific
+ * initialization for the tty structure.
+ */
+static int rs_open(struct tty_struct *tty, struct file * filp)
+{
+	struct async_struct	*info;
+	int			retval, line;
+	unsigned long		page;
+
+	MOD_INC_USE_COUNT;
+	line = minor(tty->device) - tty->driver.minor_start;
+	if ((line < 0) || (line >= NR_PORTS)) {
+		MOD_DEC_USE_COUNT;
+		return -ENODEV;
+	}
+	retval = get_async_struct(line, &info);
+	if (retval) {
+		MOD_DEC_USE_COUNT;
+		return retval;
+	}
+	tty->driver_data = info;
+	info->tty = tty;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_open %s%d, count = %d\n", tty->driver.name, info->line,
+	       info->state->count);
+#endif
+	info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
+
+	if (!tmp_buf) {
+		page = get_free_page(GFP_KERNEL);
+		if (!page) {
+			/* MOD_DEC_USE_COUNT; "info->tty" will cause this? */
+			return -ENOMEM;
+		}
+		if (tmp_buf)
+			free_page(page);
+		else
+			tmp_buf = (unsigned char *) page;
+	}
+
+	/*
+	 * If the port is the middle of closing, bail out now
+	 */
+	if (tty_hung_up_p(filp) ||
+	    (info->flags & ASYNC_CLOSING)) {
+		if (info->flags & ASYNC_CLOSING)
+			interruptible_sleep_on(&info->close_wait);
+		/* MOD_DEC_USE_COUNT; "info->tty" will cause this? */
+#ifdef SERIAL_DO_RESTART
+		return ((info->flags & ASYNC_HUP_NOTIFY) ?
+			-EAGAIN : -ERESTARTSYS);
+#else
+		return -EAGAIN;
+#endif
+	}
+
+	/*
+	 * Start up serial port
+	 */
+	retval = startup(info);
+	if (retval) {
+		/* MOD_DEC_USE_COUNT; "info->tty" will cause this? */
+		return retval;
+	}
+
+	if ((info->state->count == 1) &&
+	    (info->flags & ASYNC_SPLIT_TERMIOS)) {
+		if (tty->driver.subtype == SERIAL_TYPE_NORMAL)
+			*tty->termios = info->state->normal_termios;
+		else
+			*tty->termios = info->state->callout_termios;
+	}
+
+	/*
+	 * figure out which console to use (should be one already)
+	 */
+	console = console_drivers;
+	while (console) {
+		if ((console->flags & CON_ENABLED) && console->write) break;
+		console = console->next;
+	}
+
+	info->session = current->session;
+	info->pgrp = current->pgrp;
+
+#ifdef SIMSERIAL_DEBUG
+	printk("rs_open ttys%d successful\n", info->line);
+#endif
+	return 0;
+}
+
+/*
+ * /proc fs routines....
+ */
+
+static inline int line_info(char *buf, struct serial_state *state)
+{
+	return sprintf(buf, "%d: uart:%s port:%lX irq:%d\n",
+		       state->line, uart_config[state->type].name,
+		       state->port, state->irq);
+}
+
+static int rs_read_proc(char *page, char **start, off_t off, int count,
+		 int *eof, void *data)
+{
+	int i, len = 0, l;
+	off_t	begin = 0;
+
+	len += sprintf(page, "simserinfo:1.0 driver:%s\n", serial_version);
+	for (i = 0; i < NR_PORTS && len < 4000; i++) {
+		l = line_info(page + len, &rs_table[i]);
+		len += l;
+		if (len+begin > off+count)
+			goto done;
+		if (len+begin < off) {
+			begin += len;
+			len = 0;
+		}
+	}
+	*eof = 1;
+done:
+	if (off >= len+begin)
+		return 0;
+	*start = page + (begin-off);
+	return ((count < begin+len-off) ? count : begin+len-off);
+}
+
+/*
+ * ---------------------------------------------------------------------
+ * rs_init() and friends
+ *
+ * rs_init() is called at boot-time to initialize the serial driver.
+ * ---------------------------------------------------------------------
+ */
+
+/*
+ * This routine prints out the appropriate serial driver version
+ * number, and identifies which options were configured into this
+ * driver.
+ */
+static inline void show_serial_version(void)
+{
+	printk(KERN_INFO "%s version %s with", serial_name, serial_version);
+	printk(" no serial options enabled\n");
+}
+
+/*
+ * The serial driver boot-time initialization code!
+ */
+static int __init
+simrs_init (void)
+{
+	int			i;
+	struct serial_state	*state;
+
+	show_serial_version();
+
+	/* Initialize the tty_driver structure */
+
+	memset(&serial_driver, 0, sizeof(struct tty_driver));
+	serial_driver.magic = TTY_DRIVER_MAGIC;
+	serial_driver.driver_name = "simserial";
+	serial_driver.name = "ttyS";
+	serial_driver.major = TTY_MAJOR;
+	serial_driver.minor_start = 64;
+	serial_driver.num = 1;
+	serial_driver.type = TTY_DRIVER_TYPE_SERIAL;
+	serial_driver.subtype = SERIAL_TYPE_NORMAL;
+	serial_driver.init_termios = tty_std_termios;
+	serial_driver.init_termios.c_cflag =
+		B9600 | CS8 | CREAD | HUPCL | CLOCAL;
+	serial_driver.flags = TTY_DRIVER_REAL_RAW;
+	serial_driver.refcount = &serial_refcount;
+	serial_driver.table = serial_table;
+	serial_driver.termios = serial_termios;
+	serial_driver.termios_locked = serial_termios_locked;
+
+	serial_driver.open = rs_open;
+	serial_driver.close = rs_close;
+	serial_driver.write = rs_write;
+	serial_driver.put_char = rs_put_char;
+	serial_driver.flush_chars = rs_flush_chars;
+	serial_driver.write_room = rs_write_room;
+	serial_driver.chars_in_buffer = rs_chars_in_buffer;
+	serial_driver.flush_buffer = rs_flush_buffer;
+	serial_driver.ioctl = rs_ioctl;
+	serial_driver.throttle = rs_throttle;
+	serial_driver.unthrottle = rs_unthrottle;
+	serial_driver.send_xchar = rs_send_xchar;
+	serial_driver.set_termios = rs_set_termios;
+	serial_driver.stop = rs_stop;
+	serial_driver.start = rs_start;
+	serial_driver.hangup = rs_hangup;
+	serial_driver.break_ctl = rs_break;
+	serial_driver.wait_until_sent = rs_wait_until_sent;
+	serial_driver.read_proc = rs_read_proc;
+
+	/*
+	 * Let's have a little bit of fun !
+	 */
+	for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
+
+		if (state->type == PORT_UNKNOWN) continue;
+
+		if (!state->irq) {
+			state->irq = ia64_alloc_irq();
+			ia64_ssc_connect_irq(KEYBOARD_INTR, state->irq);
+		}
+
+		printk(KERN_INFO "ttyS%02d at 0x%04lx (irq = %d) is a %s\n",
+		       state->line,
+		       state->port, state->irq,
+		       uart_config[state->type].name);
+	}
+	/*
+	 * The callout device is just like normal device except for
+	 * major number and the subtype code.
+	 */
+	callout_driver = serial_driver;
+	callout_driver.name = "cua";
+	callout_driver.major = TTYAUX_MAJOR;
+	callout_driver.subtype = SERIAL_TYPE_CALLOUT;
+	callout_driver.read_proc = 0;
+	callout_driver.proc_entry = 0;
+
+	if (tty_register_driver(&serial_driver))
+		panic("Couldn't register simserial driver\n");
+
+	if (tty_register_driver(&callout_driver))
+		panic("Couldn't register callout driver\n");
+
+	return 0;
+}
+
+#ifndef MODULE
+__initcall(simrs_init);
+#endif
diff -Nru a/arch/ia64/ia32/binfmt_elf32.c b/arch/ia64/ia32/binfmt_elf32.c
--- a/arch/ia64/ia32/binfmt_elf32.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/ia32/binfmt_elf32.c	Fri Mar 15 17:51:03 2002
@@ -142,10 +142,11 @@
 	/*
 	 * Setup GDTD.  Note: GDTD is the descrambled version of the pseudo-descriptor
 	 * format defined by Figure 3-11 "Pseudo-Descriptor Format" in the IA-32
-	 * architecture manual.
+	 * architecture manual. Also note that the only fields that are not ignored are
+	 * `base', `limit', 'G', `P' (must be 1) and `S' (must be 0).
 	 */
-	regs->r31 = IA32_SEG_UNSCRAMBLE(IA32_SEG_DESCRIPTOR(IA32_GDT_OFFSET, IA32_PAGE_SIZE - 1, 0,
-							    0, 0, 0, 0, 0, 0));
+	regs->r31 = IA32_SEG_UNSCRAMBLE(IA32_SEG_DESCRIPTOR(IA32_GDT_OFFSET, IA32_PAGE_SIZE - 1,
+							    0, 0, 0, 1, 0, 0, 0));
 	/* Setup the segment selectors */
 	regs->r16 = (__USER_DS << 16) | __USER_DS; /* ES == DS, GS, FS are zero */
 	regs->r17 = (__USER_DS << 16) | __USER_CS; /* SS, CS; ia32_load_state() sets TSS and LDT */
@@ -206,6 +207,7 @@
 	set_personality(PER_LINUX32);
 	current->thread.map_base  = IA32_PAGE_OFFSET/3;
 	current->thread.task_size = IA32_PAGE_OFFSET;	/* use what Linux/x86 uses... */
+	current->thread.flags |= IA64_THREAD_XSTACK;	/* data must be executable */
 	set_fs(USER_DS);				/* set addr limit for new TASK_SIZE */
 }
 
diff -Nru a/arch/ia64/ia32/ia32_entry.S b/arch/ia64/ia32/ia32_entry.S
--- a/arch/ia64/ia32/ia32_entry.S	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/ia32/ia32_entry.S	Fri Mar 15 17:51:01 2002
@@ -1,6 +1,7 @@
 #include <asm/asmmacro.h>
 #include <asm/offsets.h>
 #include <asm/signal.h>
+#include <asm/thread_info.h>
 
 #include "../kernel/minstate.h"
 
@@ -37,7 +38,7 @@
 	mov loc1=r16				// save ar.pfs across do_fork
 	.body
 	zxt4 out1=in1				// newsp
-	mov out3=0				// stacksize
+	mov out3=16				// stacksize (compensates for 16-byte scratch area)
 	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
 	zxt4 out0=in0				// out0 = clone_flags
 	br.call.sptk.many rp=do_fork
@@ -87,18 +88,21 @@
 
 GLOBAL_ENTRY(ia32_ret_from_clone)
 	PT_REGS_UNWIND_INFO(0)
+#if defined(CONFIG_SMP) || defined(CONFIG_PREEMPT)
 	/*
 	 * We need to call schedule_tail() to complete the scheduling process.
 	 * Called by ia64_switch_to after do_fork()->copy_thread().  r8 contains the
 	 * address of the previously executing task.
 	 */
 	br.call.sptk.many rp=ia64_invoke_schedule_tail
-.ret1:	adds r2=IA64_TASK_PTRACE_OFFSET,r13
+.ret1:
+#endif
+	adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
 	;;
-	ld8 r2=[r2]
+	ld4 r2=[r2]
 	;;
 	mov r8=0
-	tbit.nz p6,p0=r2,PT_TRACESYS_BIT
+	tbit.nz p6,p0=r2,TIF_SYSCALL_TRACE
 (p6)	br.cond.spnt .ia32_strace_check_retval
 	;;					// prevent RAW on r8
 END(ia32_ret_from_clone)
@@ -220,7 +224,7 @@
 	data8 sys32_pipe
 	data8 sys32_times
 	data8 sys32_ni_syscall	  /* old prof syscall holder */
-	data8 sys_brk		  /* 45 */
+	data8 sys32_brk		  /* 45 */
 	data8 sys_setgid	/* 16-bit version */
 	data8 sys_getgid	/* 16-bit version */
 	data8 sys32_signal
diff -Nru a/arch/ia64/ia32/ia32_ioctl.c b/arch/ia64/ia32/ia32_ioctl.c
--- a/arch/ia64/ia32/ia32_ioctl.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/ia32/ia32_ioctl.c	Fri Mar 15 17:51:03 2002
@@ -3,12 +3,14 @@
  *
  * Copyright (C) 2000 VA Linux Co
  * Copyright (C) 2000 Don Dugger <n0ano@valinux.com>
- * Copyright (C) 2001 Hewlett-Packard Co
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/types.h>
 #include <linux/dirent.h>
+#include <linux/fs.h>		/* argh, msdos_fs.h isn't self-contained... */
+
 #include <linux/msdos_fs.h>
 #include <linux/mtio.h>
 #include <linux/ncp_fs.h>
@@ -79,6 +81,38 @@
 
 		      return ret;
 	      }
+		case IOCTL_NR(SIOCGIFCONF):
+		{
+			struct ifconf32 {
+				int		ifc_len;
+				unsigned int	ifc_ptr;
+			} ifconf32;
+			struct ifconf ifconf;
+			int i, n;
+			char *p32, *p64;
+			char buf[32];	/* sizeof IA32 ifreq structure */
+
+			if (copy_from_user(&ifconf32, P(arg), sizeof(ifconf32)))
+				return -EFAULT;
+			ifconf.ifc_len = ifconf32.ifc_len;
+			ifconf.ifc_req = P(ifconf32.ifc_ptr);
+			ret = DO_IOCTL(fd, SIOCGIFCONF, &ifconf);
+			ifconf32.ifc_len = ifconf.ifc_len;
+			if (copy_to_user(P(arg), &ifconf32, sizeof(ifconf32)))
+				return -EFAULT;
+			n = ifconf.ifc_len / sizeof(struct ifreq);
+			p32 = P(ifconf32.ifc_ptr);
+			p64 = P(ifconf32.ifc_ptr);
+			for (i = 0; i < n; i++) {
+				if (copy_from_user(buf, p64, sizeof(struct ifreq)))
+					return -EFAULT;
+				if (copy_to_user(p32, buf, sizeof(buf)))
+					return -EFAULT;
+				p32 += sizeof(buf);
+				p64 += sizeof(struct ifreq);
+			}
+			return ret;
+		}
 
 	      case IOCTL_NR(DRM_IOCTL_VERSION):
 	      {
diff -Nru a/arch/ia64/ia32/ia32_signal.c b/arch/ia64/ia32/ia32_signal.c
--- a/arch/ia64/ia32/ia32_signal.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/ia32/ia32_signal.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * IA32 Architecture-specific signal handling support.
  *
- * Copyright (C) 1999, 2001 Hewlett-Packard Co
+ * Copyright (C) 1999, 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 2000 VA Linux Co
@@ -522,6 +522,7 @@
 static int
 setup_frame_ia32 (int sig, struct k_sigaction *ka, sigset_t *set, struct pt_regs * regs)
 {
+	struct exec_domain *ed = current_thread_info()->exec_domain;
 	struct sigframe_ia32 *frame;
 	int err = 0;
 
@@ -530,12 +531,8 @@
 	if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
 		goto give_sigsegv;
 
-	err |= __put_user((current->exec_domain
-			   && current->exec_domain->signal_invmap
-			   && sig < 32
-			   ? (int)(current->exec_domain->signal_invmap[sig])
-			   : sig),
-			  &frame->sig);
+	err |= __put_user((ed && ed->signal_invmap && sig < 32
+			   ? (int)(ed->signal_invmap[sig]) : sig), &frame->sig);
 
 	err |= setup_sigcontext_ia32(&frame->sc, &frame->fpstate, regs, set->sig[0]);
 
@@ -590,6 +587,7 @@
 setup_rt_frame_ia32 (int sig, struct k_sigaction *ka, siginfo_t *info,
 		     sigset_t *set, struct pt_regs * regs)
 {
+	struct exec_domain *ed = current_thread_info()->exec_domain;
 	struct rt_sigframe_ia32 *frame;
 	int err = 0;
 
@@ -598,12 +596,8 @@
 	if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
 		goto give_sigsegv;
 
-	err |= __put_user((current->exec_domain
-			   && current->exec_domain->signal_invmap
-			   && sig < 32
-			   ? current->exec_domain->signal_invmap[sig]
-			   : sig),
-			  &frame->sig);
+	err |= __put_user((ed && ed->signal_invmap
+			   && sig < 32 ? ed->signal_invmap[sig] : sig), &frame->sig);
 	err |= __put_user((long)&frame->info, &frame->pinfo);
 	err |= __put_user((long)&frame->uc, &frame->puc);
 	err |= copy_siginfo_to_user32(&frame->info, info);
diff -Nru a/arch/ia64/ia32/ia32_support.c b/arch/ia64/ia32/ia32_support.c
--- a/arch/ia64/ia32/ia32_support.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/ia32/ia32_support.c	Fri Mar 15 17:51:01 2002
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 2000 Asit K. Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 2001 Hewlett-Packard Co
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 06/16/00	A. Mallick	added csd/ssd/tssd for ia32 thread context
@@ -153,10 +153,12 @@
 	/* We never change the TSS and LDT descriptors, so we can share them across all CPUs.  */
 	ldt_size = PAGE_ALIGN(IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE);
 	for (nr = 0; nr < NR_CPUS; ++nr) {
-		ia32_gdt[_TSS(nr)] = IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235,
-							 0xb, 0, 3, 1, 1, 1, 0);
-		ia32_gdt[_LDT(nr)] = IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1,
-							 0x2, 0, 3, 1, 1, 1, 0);
+		ia32_gdt[_TSS(nr) >> IA32_SEGSEL_INDEX_SHIFT]
+			= IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235,
+					      0xb, 0, 3, 1, 1, 1, 0);
+		ia32_gdt[_LDT(nr) >> IA32_SEGSEL_INDEX_SHIFT]
+			= IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1,
+					      0x2, 0, 3, 1, 1, 1, 0);
 	}
 }
 
@@ -172,6 +174,10 @@
 
 	siginfo.si_signo = SIGTRAP;
 	siginfo.si_errno = int_num;	/* XXX is it OK to abuse si_errno like this? */
+	siginfo.si_flags = 0;
+	siginfo.si_isr = 0;
+	siginfo.si_addr = 0;
+	siginfo.si_imm = 0;
 	siginfo.si_code = TRAP_BRKPT;
 	force_sig_info(SIGTRAP, &siginfo, current);
 }
diff -Nru a/arch/ia64/ia32/ia32_traps.c b/arch/ia64/ia32/ia32_traps.c
--- a/arch/ia64/ia32/ia32_traps.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/ia32/ia32_traps.c	Fri Mar 15 17:51:02 2002
@@ -2,7 +2,7 @@
  * IA-32 exception handlers
  *
  * Copyright (C) 2000 Asit K. Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 2001 Hewlett-Packard Co
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 06/16/00	A. Mallick	added siginfo for most cases (close to IA32)
@@ -20,7 +20,7 @@
 {
 	switch ((isr >> 16) & 0xff) {
 	      case 0:	/* Instruction intercept fault */
-	      case 3:	/* Locked Data reference fault */
+	      case 4:	/* Locked Data reference fault */
 	      case 1:	/* Gate intercept trap */
 		return -1;
 
@@ -40,7 +40,11 @@
 {
 	struct siginfo siginfo;
 
+	/* initialize these fields to avoid leaking kernel bits to user space: */
 	siginfo.si_errno = 0;
+	siginfo.si_flags = 0;
+	siginfo.si_isr = 0;
+	siginfo.si_imm = 0;
 	switch ((isr >> 16) & 0xff) {
 	      case 1:
 	      case 2:
@@ -103,6 +107,8 @@
 			 * and it will suffer the consequences since we won't be able to
 			 * fully reproduce the context of the exception
 			 */
+			siginfo.si_isr = isr;
+			siginfo.si_flags = __ISR_VALID;
 			switch(((~fcr) & (fsr & 0x3f)) | (fsr & 0x240)) {
 				case 0x000:
 				default:
diff -Nru a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c
--- a/arch/ia64/ia32/sys_ia32.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/ia32/sys_ia32.c	Fri Mar 15 17:51:01 2002
@@ -6,7 +6,7 @@
  * Copyright (C) 1999		Arun Sharma <arun.sharma@intel.com>
  * Copyright (C) 1997,1998	Jakub Jelinek (jj@sunsite.mff.cuni.cz)
  * Copyright (C) 1997		David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2000-2001 Hewlett-Packard Co
+ * Copyright (C) 2000-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * These routines maintain argument size conversion between 32bit and 64bit
@@ -74,6 +74,9 @@
 #define PAGE_START(addr)	((addr) & PAGE_MASK)
 #define PAGE_OFF(addr)		((addr) & ~PAGE_MASK)
 
+#define high2lowuid(uid) ((uid) > 65535 ? 65534 : (uid))
+#define high2lowgid(gid) ((gid) > 65535 ? 65534 : (gid))
+
 extern asmlinkage long sys_execve (char *, char **, char **, struct pt_regs *);
 extern asmlinkage long sys_mprotect (unsigned long, size_t, unsigned long);
 extern asmlinkage long sys_munmap (unsigned long, size_t);
@@ -82,6 +85,7 @@
 
 /* forward declaration: */
 asmlinkage long sys32_mprotect (unsigned int, unsigned int, int);
+asmlinkage unsigned long sys_brk(unsigned long);
 
 /*
  * Anything that modifies or inspects ia32 user virtual memory must hold this semaphore
@@ -400,7 +404,7 @@
 			return -EINVAL;
 		}
 		if (!(prot & PROT_WRITE) && sys_mprotect(pstart, pend - pstart, prot) < 0)
-			return EINVAL;
+			return -EINVAL;
 	}
 	return start;
 }
@@ -2578,6 +2582,7 @@
 	      default:
 		return -EINVAL;
 	}
+	return -EINVAL;
 }
 
 /*
@@ -3780,6 +3785,19 @@
 	ret = sys_personality(personality);
 	if (ret == PER_LINUX32)
 		ret = PER_LINUX;
+	return ret;
+}
+
+asmlinkage unsigned long
+sys32_brk (unsigned int brk)
+{
+	unsigned long ret, obrk;
+	struct mm_struct *mm = current->mm;
+
+	obrk = mm->brk;
+	ret = sys_brk(brk);
+	if (ret < obrk)
+		clear_user((void *) ret, PAGE_ALIGN(ret) - ret);
 	return ret;
 }
 
diff -Nru a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
--- a/arch/ia64/kernel/acpi.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/acpi.c	Fri Mar 15 17:51:03 2002
@@ -5,11 +5,11 @@
  * 'IA-64 Extensions to ACPI Specification' Revision 0.6
  *
  * Copyright (C) 1999 VA Linux Systems
- * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
- * Copyright (C) 2000 Hewlett-Packard Co.
- * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999, 2000 Walt Drummond <drummond@valinux.com>
+ * Copyright (C) 2000, 2002 Hewlett-Packard Co.
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 2000 Intel Corp.
- * Copyright (C) 2000,2001 J.I. Lee <jung-ik.lee@intel.com>
+ * Copyright (C) 2000, 2001 J.I. Lee <jung-ik.lee@intel.com>
  *      ACPI based kernel configuration manager.
  *      ACPI 2.0 & IA64 ext 0.71
  */
@@ -44,6 +44,8 @@
 int __initdata available_cpus;
 int __initdata total_cpus;
 
+int __initdata pcat_compat;
+
 void (*pm_idle) (void);
 void (*pm_power_off) (void);
 
@@ -293,6 +295,16 @@
 	} else
 		printk("Lapic address set to default 0x%lx\n", ipi_base_addr);
 
+	/*
+	 * The PCAT_COMPAT flag indicates that the system has a dual-8259 compatible
+	 * setup.
+	 */
+#ifdef CONFIG_ITANIUM
+	pcat_compat = 1; /* fw on some Itanium systems is broken... */
+#else
+	pcat_compat = (madt->flags & MADT_PCAT_COMPAT);
+#endif
+
 	p = (char *) (madt + 1);
 	end = p + (madt->header.length - sizeof(acpi_madt_t));
 
@@ -319,17 +331,7 @@
 		      case ACPI20_ENTRY_IO_SAPIC:
 			iosapic = (acpi_entry_iosapic_t *) p;
 			if (iosapic_init)
-				/*
-				 * The PCAT_COMPAT flag indicates that the system has a
-				 * dual-8259 compatible setup.
-				 */
-				iosapic_init(iosapic->address, iosapic->irq_base,
-#ifdef CONFIG_ITANIUM
-					     1 /* fw on some Itanium systems is broken... */
-#else
-					     (madt->flags & MADT_PCAT_COMPAT)
-#endif
-					);
+				iosapic_init(iosapic->address, iosapic->irq_base, pcat_compat);
 			break;
 
 		      case ACPI20_ENTRY_PLATFORM_INT_SOURCE:
@@ -401,7 +403,7 @@
 # ifdef CONFIG_ACPI
 	acpi_xsdt_t *xsdt;
 	acpi_desc_table_hdr_t *hdrp;
-	acpi_madt_t *madt;
+	acpi_madt_t *madt = NULL;
 	int tables, i;
 
 	if (strncmp(rsdp20->signature, ACPI_RSDP_SIG, ACPI_RSDP_SIG_LEN)) {
diff -Nru a/arch/ia64/kernel/brl_emu.c b/arch/ia64/kernel/brl_emu.c
--- a/arch/ia64/kernel/brl_emu.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/brl_emu.c	Fri Mar 15 17:51:03 2002
@@ -2,6 +2,9 @@
  *  Emulation of the "brl" instruction for IA64 processors that
  *  don't support it in hardware.
  *  Author: Stephan Zeisset, Intel Corp. <Stephan.Zeisset@intel.com>
+ *
+ *    02/22/02	D. Mosberger	Clear si_flgs, si_isr, and si_imm to avoid
+ *				leaking kernel bits.
  */
 
 #include <linux/kernel.h>
@@ -195,6 +198,9 @@
 		printk("Woah! Unimplemented Instruction Address Trap!\n");
 		siginfo.si_signo = SIGILL;
 		siginfo.si_errno = 0;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_imm = 0;
 		siginfo.si_code = ILL_BADIADDR;
 		force_sig_info(SIGILL, &siginfo, current);
 	} else if (ia64_psr(regs)->tb) {
@@ -205,6 +211,10 @@
 		siginfo.si_signo = SIGTRAP;
 		siginfo.si_errno = 0;
 		siginfo.si_code = TRAP_BRANCH;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_addr = 0;
+		siginfo.si_imm = 0;
 		force_sig_info(SIGTRAP, &siginfo, current);
 	} else if (ia64_psr(regs)->ss) {
 		/*
@@ -214,6 +224,10 @@
 		siginfo.si_signo = SIGTRAP;
 		siginfo.si_errno = 0;
 		siginfo.si_code = TRAP_TRACE;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_addr = 0;
+		siginfo.si_imm = 0;
 		force_sig_info(SIGTRAP, &siginfo, current);
 	}
 	return rv;
diff -Nru a/arch/ia64/kernel/efivars.c b/arch/ia64/kernel/efivars.c
--- a/arch/ia64/kernel/efivars.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/efivars.c	Fri Mar 15 17:51:03 2002
@@ -29,6 +29,11 @@
  *
  * Changelog:
  *
+ *  12 Feb 2002 - Matt Domsch <Matt_Domsch@dell.com>
+ *   use list_for_each_safe when deleting vars.
+ *   remove ifdef CONFIG_SMP around include <linux/smp.h>
+ *   v0.04 release to linux-ia64@linuxia64.org
+ *
  *  20 April 2001 - Matt Domsch <Matt_Domsch@dell.com>
  *   Moved vars from /proc/efi to /proc/efi/vars, and made
  *   efi.c own the /proc/efi directory.
@@ -56,18 +61,16 @@
 #include <linux/sched.h>		/* for capable() */
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/smp.h>
 
 #include <asm/efi.h>
 #include <asm/uaccess.h>
-#ifdef CONFIG_SMP
-#include <linux/smp.h>
-#endif
 
 MODULE_AUTHOR("Matt Domsch <Matt_Domsch@Dell.com>");
 MODULE_DESCRIPTION("/proc interface to EFI Variables");
 MODULE_LICENSE("GPL");
 
-#define EFIVARS_VERSION "0.03 2001-Apr-20"
+#define EFIVARS_VERSION "0.04 2002-Feb-12"
 
 static int
 efivar_read(char *page, char **start, off_t off,
@@ -265,7 +268,7 @@
 {
 	unsigned long strsize1, strsize2;
 	int found=0;
-	struct list_head *pos;
+	struct list_head *pos, *n;
 	unsigned long size = sizeof(efi_variable_t);
 	efi_status_t status;
 	efivar_entry_t *efivar = data, *search_efivar = NULL;
@@ -297,7 +300,7 @@
 	   This allows any properly formatted data structure to
 	   be written to any of the files in /proc/efi/vars and it will work.
 	*/
-	list_for_each(pos, &efivar_list) {
+	list_for_each_safe(pos, n, &efivar_list) {
 		search_efivar = efivar_entry(pos);
 		strsize1 = utf8_strsize(search_efivar->var.VariableName, 1024);
 		strsize2 = utf8_strsize(var_data->VariableName, 1024);
@@ -413,12 +416,12 @@
 static void __exit
 efivars_exit(void)
 {
-	struct list_head *pos;
+	struct list_head *pos, *n;
 	efivar_entry_t *efivar;
 
 	spin_lock(&efivars_lock);
 
-	list_for_each(pos, &efivar_list) {
+	list_for_each_safe(pos, n, &efivar_list) {
 		efivar = efivar_entry(pos);
 		remove_proc_entry(efivar->entry->name, efi_vars_dir);
 		list_del(&efivar->list);
diff -Nru a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
--- a/arch/ia64/kernel/entry.S	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/entry.S	Fri Mar 15 17:51:02 2002
@@ -3,7 +3,7 @@
  *
  * Kernel entry points.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
@@ -30,14 +30,15 @@
 
 #include <linux/config.h>
 
+#include <asm/asmmacro.h>
 #include <asm/cache.h>
 #include <asm/errno.h>
 #include <asm/kregs.h>
 #include <asm/offsets.h>
+#include <asm/pgtable.h>
 #include <asm/processor.h>
+#include <asm/thread_info.h>
 #include <asm/unistd.h>
-#include <asm/asmmacro.h>
-#include <asm/pgtable.h>
 
 #include "minstate.h"
 
@@ -115,7 +116,7 @@
 	mov loc1=r16				// save ar.pfs across do_fork
 	.body
 	mov out1=in1
-	mov out3=0
+	mov out3=16				// stacksize (compensates for 16-byte scratch area)
 	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
 	mov out0=in0				// out0 = clone_flags
 	br.call.sptk.many rp=do_fork
@@ -128,6 +129,9 @@
 
 /*
  * prev_task <- ia64_switch_to(struct task_struct *next)
+ *	With Ingo's new scheduler, interrupts are disabled when this routine gets
+ *	called.  The code starting at .map relies on this.  The rest of the code
+ *	doesn't care about the interrupt masking status.
  */
 GLOBAL_ENTRY(ia64_switch_to)
 	.prologue
@@ -158,10 +162,8 @@
 (p6)	srlz.d
 	ld8 sp=[r21]			// load kernel stack pointer of new task
 	mov IA64_KR(CURRENT)=r20	// update "current" application register
-	mov r8=r13			// return pointer to previously running task
 	mov r13=in0			// set "current" pointer
 	;;
-(p6)	ssm psr.i			// renable psr.i AFTER the ic bit is serialized
 	DO_LOAD_SWITCH_STACK
 
 #ifdef CONFIG_SMP
@@ -170,7 +172,7 @@
 	br.ret.sptk.many rp		// boogie on out in new context
 
 .map:
-	rsm psr.i | psr.ic
+	rsm psr.ic			// interrupts (psr.i) are already disabled here
 	movl r25=PAGE_KERNEL
 	;;
 	srlz.d
@@ -433,7 +435,7 @@
 	.body
 	mov loc2=b6
 	;;
-#error	br.call.sptk.many rp=syscall_trace
+	br.call.sptk.many rp=syscall_trace
 .ret3:	mov rp=loc0
 	mov ar.pfs=loc1
 	mov b6=loc2
@@ -454,7 +456,7 @@
 
 GLOBAL_ENTRY(ia64_trace_syscall)
 	PT_REGS_UNWIND_INFO(0)
-#error	br.call.sptk.many rp=invoke_syscall_trace // give parent a chance to catch syscall args
+	br.call.sptk.many rp=invoke_syscall_trace // give parent a chance to catch syscall args
 .ret6:	br.call.sptk.many rp=b6			// do the syscall
 strace_check_retval:
 	cmp.lt p6,p0=r8,r0			// syscall failed?
@@ -467,7 +469,7 @@
 .mem.offset 0,0;	st8.spill [r2]=r8	// store return value in slot for r8
 .mem.offset 8,0;	st8.spill [r3]=r10	// clear error indication in slot for r10
 ia64_strace_leave_kernel:
-#error	br.call.sptk.many rp=invoke_syscall_trace // give parent a chance to catch return value
+	br.call.sptk.many rp=invoke_syscall_trace // give parent a chance to catch return value
 .rety:	br.cond.sptk ia64_leave_kernel
 
 strace_error:
@@ -484,6 +486,7 @@
 
 GLOBAL_ENTRY(ia64_ret_from_clone)
 	PT_REGS_UNWIND_INFO(0)
+#if defined(CONFIG_SMP) || defined(CONFIG_PREEMPT)
 	/*
 	 * We need to call schedule_tail() to complete the scheduling process.
 	 * Called by ia64_switch_to after do_fork()->copy_thread().  r8 contains the
@@ -491,12 +494,13 @@
 	 */
 	br.call.sptk.many rp=ia64_invoke_schedule_tail
 .ret8:
-	adds r2=IA64_TASK_PTRACE_OFFSET,r13
+#endif
+	adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
 	;;
-	ld8 r2=[r2]
+	ld4 r2=[r2]
 	;;
 	mov r8=0
-	tbit.nz p6,p0=r2,PT_TRACESYS_BIT
+	tbit.nz p6,p0=r2,TIF_SYSCALL_TRACE
 (p6)	br.cond.spnt strace_check_retval
 	;;					// added stop bits to prevent r8 dependency
 END(ia64_ret_from_clone)
@@ -516,50 +520,29 @@
 	// fall through
 GLOBAL_ENTRY(ia64_leave_kernel)
 	PT_REGS_UNWIND_INFO(0)
-	lfetch.fault [sp]
-	movl r14=.restart
+	// work.need_resched etc. mustn't get changed by this CPU before it returns to userspace:
+(pUser)	cmp.eq.unc p6,p0=r0,r0			// p6 <- pUser
+(pUser)	rsm psr.i
 	;;
-	mov.ret.sptk rp=r14,.restart
-.restart:
-	adds r17=IA64_TASK_NEED_RESCHED_OFFSET,r13
-	adds r18=IA64_TASK_SIGPENDING_OFFSET,r13
-#ifdef CONFIG_PERFMON
-	adds r19=IA64_TASK_PFM_MUST_BLOCK_OFFSET,r13
-#endif
-	;;
-#ifdef CONFIG_PERFMON
-(pUser)	ld8 r19=[r19]				// load current->thread.pfm_must_block
-#endif
-#error (pUser)	ld8 r17=[r17]				// load current->need_resched
-#error (pUser)	ld4 r18=[r18]				// load current->sigpending
-	;;
-#ifdef CONFIG_PERFMON
-(pUser)	cmp.ne.unc p9,p0=r19,r0			// current->thread.pfm_must_block != 0?
-#endif
-#error (pUser)	cmp.ne.unc p7,p0=r17,r0			// current->need_resched != 0?
-#errror (pUser)	cmp.ne.unc p8,p0=r18,r0			// current->sigpending != 0?
+(pUser)	adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
 	;;
+.work_processed:
+(p6)	ld4 r18=[r17]				// load current_thread_info()->flags
 	adds r2=PT(R8)+16,r12
 	adds r3=PT(R9)+16,r12
-#ifdef CONFIG_PERFMON
-(p9)	br.call.spnt.many b7=pfm_block_on_overflow
-#endif
-#if __GNUC__ < 3
-(p7)	br.call.spnt.many b7=invoke_schedule
-#else
-(p7)	br.call.spnt.many b7=schedule
-#endif
-(p8)	br.call.spnt.many b7=handle_signal_delivery	// check & deliver pending signals
 	;;
 	// start restoring the state saved on the kernel stack (struct pt_regs):
 	ld8.fill r8=[r2],16
 	ld8.fill r9=[r3],16
+(p6)	and r19=TIF_WORK_MASK,r18		// any work other than TIF_SYSCALL_TRACE?
 	;;
 	ld8.fill r10=[r2],16
 	ld8.fill r11=[r3],16
+(p6)	cmp4.ne.unc p6,p0=r19, r0		// any special work pending?
 	;;
 	ld8.fill r16=[r2],16
 	ld8.fill r17=[r3],16
+(p6)	br.cond.spnt .work_pending
 	;;
 	ld8.fill r18=[r2],16
 	ld8.fill r19=[r3],16
@@ -582,7 +565,7 @@
 	ld8.fill r30=[r2],16
 	ld8.fill r31=[r3],16
 	;;
-	rsm psr.i | psr.ic	// initiate turning off of interrupts & interruption collection
+	rsm psr.i | psr.ic	// initiate turning off of interrupt and interruption collection
 	invala			// invalidate ALAT
 	;;
 	ld8 r1=[r2],16		// ar.ccv
@@ -601,7 +584,7 @@
 	mov ar.fpsr=r13
 	mov b0=r14
 	;;
-	srlz.i			// ensure interrupts & interruption collection are off
+	srlz.i			// ensure interruption collection is off
 	mov b7=r15
 	;;
 	bsw.0			// switch back to bank 0
@@ -639,7 +622,7 @@
 	shr.u r18=r19,16	// get byte size of existing "dirty" partition
 	;;
 	mov r16=ar.bsp		// get existing backing store pointer
-	movl r17=PERCPU_ADDR+IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET
+	movl r17=THIS_CPU(ia64_phys_stacked_size_p8)
 	;;
 	ld4 r17=[r17]		// r17 = cpu_data->phys_stacked_size_p8
 (pKern)	br.cond.dpnt skip_rbs_switch
@@ -729,6 +712,25 @@
 	mov ar.unat=rARUNAT
 	mov pr=rARPR,-1
 	rfi
+
+.work_pending:
+	tbit.z p6,p0=r18,TIF_NEED_RESCHED		// current_thread_info()->need_resched==0?
+(p6)	br.cond.sptk.few .notify
+#if __GNUC__ < 3
+	br.call.spnt.many rp=invoke_schedule
+#else
+	br.call.spnt.many rp=schedule
+#endif
+.ret9:	cmp.eq p6,p0=r0,r0				// p6 <- 1
+	rsm psr.i
+	;;
+	adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
+	br.cond.sptk.many .work_processed		// re-check
+
+.notify:
+	br.call.spnt.many rp=notify_resume_user
+.ret10:	cmp.ne p6,p0=r0,r0				// p6 <- 0
+	br.cond.sptk.many .work_processed		// don't re-check
 END(ia64_leave_kernel)
 
 ENTRY(handle_syscall_error)
@@ -756,6 +758,7 @@
 	br.cond.sptk ia64_leave_kernel
 END(handle_syscall_error)
 
+#ifdef CONFIG_SMP
 	/*
 	 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
 	 * in case a system call gets restarted.
@@ -772,6 +775,8 @@
 	br.ret.sptk.many rp
 END(ia64_invoke_schedule_tail)
 
+#endif /* CONFIG_SMP */
+
 #if __GNUC__ < 3
 
 	/*
@@ -802,7 +807,7 @@
 	 * be set up by the caller.  We declare 8 input registers so the system call
 	 * args get preserved, in case we need to restart a system call.
 	 */
-ENTRY(handle_signal_delivery)
+ENTRY(notify_resume_user)
 	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
 	alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
 	mov r9=ar.unat
@@ -816,17 +821,17 @@
 	.spillpsp ar.unat, 16			// (note that offset is relative to psp+0x10!)
 	st8 [sp]=r9,-16				// allocate space for ar.unat and save it
 	.body
-#error	br.call.sptk.many rp=ia64_do_signal
+	br.call.sptk.many rp=do_notify_resume_user
 .ret15:	.restore sp
 	adds sp=16,sp				// pop scratch stack space
 	;;
-	ld8 r9=[sp]				// load new unat from sw->caller_unat
+	ld8 r9=[sp]				// load new unat from sigscratch->scratch_unat
 	mov rp=loc0
 	;;
 	mov ar.unat=r9
 	mov ar.pfs=loc1
 	br.ret.sptk.many rp
-END(handle_signal_delivery)
+END(do_notify_resume_user)
 
 GLOBAL_ENTRY(sys_rt_sigsuspend)
 	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
@@ -1033,9 +1038,9 @@
 	data8 sys_syslog
 	data8 sys_setitimer
 	data8 sys_getitimer
-	data8 ia64_oldstat			// 1120
-	data8 ia64_oldlstat
-	data8 ia64_oldfstat
+	data8 ia64_ni_syscall			// 1120		/* was: ia64_oldstat */
+	data8 ia64_ni_syscall					/* was: ia64_oldlstat */
+	data8 ia64_ni_syscall					/* was: ia64_oldfstat */
 	data8 sys_vhangup
 	data8 sys_lchown
 	data8 sys_vm86				// 1125
@@ -1130,19 +1135,23 @@
 	data8 sys_getdents64
 	data8 sys_getunwind			// 1215
 	data8 sys_readahead
+	data8 sys_setxattr
+	data8 sys_lsetxattr
+	data8 sys_fsetxattr
+	data8 sys_getxattr			// 1220
+	data8 sys_lgetxattr
+	data8 sys_fgetxattr
+	data8 sys_listxattr
+	data8 sys_llistxattr
+	data8 sys_flistxattr			// 1225
+	data8 sys_removexattr
+	data8 sys_lremovexattr
+	data8 sys_fremovexattr
+#if 0
 	data8 sys_tkill
+#else
 	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall			// 1220
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall			// 1225
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
-	data8 ia64_ni_syscall
+#endif
 	data8 ia64_ni_syscall			// 1230
 	data8 ia64_ni_syscall
 	data8 ia64_ni_syscall
diff -Nru a/arch/ia64/kernel/gate.S b/arch/ia64/kernel/gate.S
--- a/arch/ia64/kernel/gate.S	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/gate.S	Fri Mar 15 17:51:02 2002
@@ -90,7 +90,7 @@
 (p8)	br.cond.spnt setup_rbs		// yup -> (clobbers r14, r15, and r16)
 back_from_setup_rbs:
 
-	.save ar.pfs, r8
+	.spillreg ar.pfs, r8
 	alloc r8=ar.pfs,0,0,3,0		// get CFM0, EC0, and CPL0 into r8
 	ld8 out0=[base0],16		// load arg0 (signum)
 	adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
diff -Nru a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
--- a/arch/ia64/kernel/head.S	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/head.S	Fri Mar 15 17:51:03 2002
@@ -127,23 +127,21 @@
 #ifdef CONFIG_SMP
 	/*
 	 * Find the init_task for the currently booting CPU.  At poweron, and in
-	 * UP mode, cpucount is 0.
+	 * UP mode, task_for_booting_cpu is NULL.
 	 */
-	movl r3=cpucount
+	movl r3=task_for_booting_cpu
  	;;
-	ld4 r3=[r3]		// r3 <- smp_processor_id()
-	movl r2=init_tasks
+	ld8 r3=[r3]
+	movl r2=init_thread_union
 	;;
-	shladd r2=r3,3,r2
+	cmp.eq isBP,isAP=r3,r0
 	;;
-	ld8 r2=[r2]
+(isAP)	mov r2=r3
 #else
-	mov r3=0
-	movl r2=init_task_union
-	;;
+	movl r2=init_thread_union
+	cmp.eq isBP,isAP=r0,r0
 #endif
-	cmp4.ne isAP,isBP=r3,r0
-	;;			// RAW on r2
+	;;
 	extr r3=r2,0,61		// r3 == phys addr of task struct
 	mov r16=KERNEL_TR_PAGE_NUM
 	;;
@@ -180,10 +178,12 @@
 	.rodata
 alive_msg:
 	stringz "I'm alive and well\n"
+alive_msg_end:
 	.previous
 
 	alloc r2=ar.pfs,0,0,2,0
 	movl out0=alive_msg
+	movl out1=alive_msg_end-alive_msg-1
 	;;
 	br.call.sptk.many rp=early_printk
 1:	// force new bundle
diff -Nru a/arch/ia64/kernel/ia64_ksyms.c b/arch/ia64/kernel/ia64_ksyms.c
--- a/arch/ia64/kernel/ia64_ksyms.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/ia64_ksyms.c	Fri Mar 15 17:51:03 2002
@@ -24,6 +24,7 @@
 EXPORT_SYMBOL(strrchr);
 EXPORT_SYMBOL(strstr);
 EXPORT_SYMBOL(strtok);
+EXPORT_SYMBOL(strpbrk);
 
 #include <linux/irq.h>
 EXPORT_SYMBOL(isa_irq_to_vector_map);
@@ -58,7 +59,7 @@
 
 #include <asm/processor.h>
 # ifndef CONFIG_NUMA
-EXPORT_SYMBOL(_cpu_data);
+EXPORT_SYMBOL(cpu_info);
 # endif
 EXPORT_SYMBOL(kernel_thread);
 
diff -Nru a/arch/ia64/kernel/init_task.c b/arch/ia64/kernel/init_task.c
--- a/arch/ia64/kernel/init_task.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/init_task.c	Fri Mar 15 17:51:03 2002
@@ -2,8 +2,8 @@
  * This is where we statically allocate and initialize the initial
  * task.
  *
- * Copyright (C) 1999 Hewlett-Packard Co
- * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/init.h>
@@ -22,10 +22,20 @@
 /*
  * Initial task structure.
  *
- * We need to make sure that this is page aligned due to the way
- * process stacks are handled. This is done by having a special
- * "init_task" linker map entry..
+ * We need to make sure that this is properly aligned due to the way process stacks are
+ * handled. This is done by having a special ".data.init_task" section...
  */
-union task_union init_task_union
-	__attribute__((section("init_task"))) =
-		{ INIT_TASK(init_task_union.task) };
+#define init_thread_info	init_thread_union.s.thread_info
+
+union init_thread {
+	struct {
+		struct task_struct task;
+		struct thread_info thread_info;
+	} s;
+	unsigned long stack[KERNEL_STACK_SIZE/sizeof (unsigned long)];
+} init_thread_union __attribute__((section(".data.init_task"))) = {{
+	task: INIT_TASK(init_thread_union.s.task),
+	thread_info: INIT_THREAD_INFO(init_thread_union.s.thread_info)
+}};
+
+asm (".global init_task; init_task = init_thread_union");
diff -Nru a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
--- a/arch/ia64/kernel/iosapic.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/iosapic.c	Fri Mar 15 17:51:03 2002
@@ -3,8 +3,9 @@
  *
  * Copyright (C) 1999 Intel Corp.
  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 1999-2000 Hewlett-Packard Co.
- * Copyright (C) 1999-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
+ * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co.
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  *
@@ -15,6 +16,12 @@
  *				PCI to vector mapping, shared PCI interrupts.
  * 00/10/27	D. Mosberger	Document things a bit more to make them more understandable.
  *				Clean up much of the old IOSAPIC cruft.
+ * 01/07/27	J.I. Lee	PCI irq routing, Platform/Legacy interrupts and fixes for
+ *				ACPI S5(SoftOff) support.
+ * 02/01/23	J.I. Lee	iosapic pgm fixes for PCI irq routing from _PRT
+ * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt vectors in
+ *                              iosapic_set_affinity(), initializations for
+ *                              /proc/irq/#/smp_affinity
  */
 /*
  * Here is what the interrupt logic between a PCI device and the CPU looks like:
@@ -63,6 +70,7 @@
 
 
 #undef DEBUG_IRQ_ROUTING
+#undef	OVERRIDE_DEBUG
 
 static spinlock_t iosapic_lock = SPIN_LOCK_UNLOCKED;
 
@@ -88,7 +96,7 @@
  * Translate IOSAPIC irq number to the corresponding IA-64 interrupt vector.  If no
  * entry exists, return -1.
  */
-static int
+int
 iosapic_irq_to_vector (int irq)
 {
 	int vector;
@@ -121,6 +129,7 @@
 	u32 low32, high32;
 	char *addr;
 	int pin;
+	char redir;
 
 	pin = iosapic_irq[vector].pin;
 	if (pin < 0)
@@ -131,6 +140,11 @@
 	trigger = iosapic_irq[vector].trigger;
 	dmode   = iosapic_irq[vector].dmode;
 
+	redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
+#ifdef CONFIG_SMP
+	set_irq_affinity_info(vector, (int)(dest & 0xffff), redir);
+#endif
+
 	low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 		 (trigger << IOSAPIC_TRIGGER_SHIFT) |
 		 (dmode << IOSAPIC_DELIVERY_SHIFT) |
@@ -211,6 +225,7 @@
 	u32 high32, low32;
 	int dest, pin;
 	char *addr;
+	int redir = (irq & (1<<31)) ? 1 : 0;
 
 	mask &= (1UL << smp_num_cpus) - 1;
 
@@ -225,6 +240,8 @@
 	if (pin < 0)
 		return;			/* not an IOSAPIC interrupt */
 
+	set_irq_affinity_info(irq,dest,redir);
+
 	/* dest contains both id and eid */
 	high32 = dest << IOSAPIC_DEST_SHIFT;
 
@@ -234,9 +251,13 @@
 		writel(IOSAPIC_RTE_LOW(pin), addr + IOSAPIC_REG_SELECT);
 		low32 = readl(addr + IOSAPIC_WINDOW);
 
-		/* change delivery mode to fixed */
 		low32 &= ~(7 << IOSAPIC_DELIVERY_SHIFT);
-		low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
+		if (redir)
+		        /* change delivery mode to lowest priority */
+			low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
+		else
+		        /* change delivery mode to fixed */
+			low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 
 		writel(IOSAPIC_RTE_HIGH(pin), addr + IOSAPIC_REG_SELECT);
 		writel(high32, addr + IOSAPIC_WINDOW);
@@ -343,29 +364,64 @@
 }
 
 /*
- * ACPI can describe IOSAPIC interrupts via static tables and namespace
- * methods.  This provides an interface to register those interrupts and
- * program the IOSAPIC RTE.
+ * if the given vector is already owned by other,
+ *  assign a new vector for the other and make the vector available
  */
-int
-iosapic_register_irq (u32 global_vector, unsigned long polarity, unsigned long
-                      edge_triggered, u32 base_irq, char *iosapic_address)
+static void
+iosapic_reassign_vector (int vector)
+{
+	int new_vector;
+
+	if (iosapic_irq[vector].pin >= 0 || iosapic_irq[vector].addr
+	    || iosapic_irq[vector].base_irq || iosapic_irq[vector].dmode
+	    || iosapic_irq[vector].polarity || iosapic_irq[vector].trigger)
+	{
+		new_vector = ia64_alloc_irq();
+		printk("Reassigning Vector 0x%x to 0x%x\n", vector, new_vector);
+		memcpy (&iosapic_irq[new_vector], &iosapic_irq[vector],
+			sizeof(struct iosapic_irq));
+		memset (&iosapic_irq[vector], 0, sizeof(struct iosapic_irq));
+		iosapic_irq[vector].pin = -1;
+	}
+}
+
+static void
+register_irq (u32 global_vector, int vector, int pin, unsigned char delivery,
+	      unsigned long polarity, unsigned long edge_triggered,
+	      u32 base_irq, char *iosapic_address)
 {
 	irq_desc_t *idesc;
 	struct hw_interrupt_type *irq_type;
-	int vector;
 
-	vector = iosapic_irq_to_vector(global_vector);
-	if (vector < 0)
-		vector = ia64_alloc_irq();
-
-	/* fill in information from this vector's IOSAPIC */
-	iosapic_irq[vector].addr = iosapic_address;
-	iosapic_irq[vector].base_irq = base_irq;
-	iosapic_irq[vector].pin	= global_vector - iosapic_irq[vector].base_irq;
+	iosapic_irq[vector].pin	= pin;
 	iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
-	iosapic_irq[vector].dmode    = IOSAPIC_LOWEST_PRIORITY;
+	iosapic_irq[vector].dmode    = delivery;
 
+	/*
+	 * In override, it does not provide addr/base_irq.  global_vector is enough to
+	 * locate iosapic addr, base_irq and pin by examining base_irq and max_pin of
+	 * registered iosapics (tbd)
+	 */
+#ifndef	OVERRIDE_DEBUG
+	if (iosapic_address) {
+		iosapic_irq[vector].addr = iosapic_address;
+		iosapic_irq[vector].base_irq = base_irq;
+	}
+#else
+	if (iosapic_address) {
+		if (iosapic_irq[vector].addr && (iosapic_irq[vector].addr != iosapic_address))
+			printk("WARN: register_irq: diff IOSAPIC ADDRESS for gv %x, v %x\n",
+			       global_vector, vector);
+		iosapic_irq[vector].addr = iosapic_address;
+		if (iosapic_irq[vector].base_irq && (iosapic_irq[vector].base_irq != base_irq)) {
+			printk("WARN: register_irq: diff BASE IRQ %x for gv %x, v %x\n",
+			       base_irq, global_vector, vector);
+		}
+		iosapic_irq[vector].base_irq = base_irq;
+	} else if (!iosapic_irq[vector].addr)
+		printk("WARN: register_irq: invalid override for gv %x, v %x\n",
+		       global_vector, vector);
+#endif
 	if (edge_triggered) {
 		iosapic_irq[vector].trigger = IOSAPIC_EDGE;
 		irq_type = &irq_type_iosapic_edge;
@@ -377,12 +433,32 @@
 	idesc = irq_desc(vector);
 	if (idesc->handler != irq_type) {
 		if (idesc->handler != &no_irq_type)
-			printk("iosapic_register_irq(): changing vector 0x%02x from"
+			printk("register_irq(): changing vector 0x%02x from "
 			       "%s to %s\n", vector, idesc->handler->typename, irq_type->typename);
 		idesc->handler = irq_type;
 	}
+}
+
+/*
+ * ACPI can describe IOSAPIC interrupts via static tables and namespace
+ * methods.  This provides an interface to register those interrupts and
+ * program the IOSAPIC RTE.
+ */
+int
+iosapic_register_irq (u32 global_vector, unsigned long polarity, unsigned long
+                      edge_triggered, u32 base_irq, char *iosapic_address)
+{
+	int vector;
 
-	printk("IOSAPIC %x(%s,%s) -> Vector %x\n", global_vector,
+	vector = iosapic_irq_to_vector(global_vector);
+	if (vector < 0)
+		vector = ia64_alloc_irq();
+
+	register_irq (global_vector, vector, global_vector - base_irq,
+			IOSAPIC_LOWEST_PRIORITY, polarity, edge_triggered,
+			base_irq, iosapic_address);
+
+	printk("IOSAPIC 0x%x(%s,%s) -> Vector 0x%x\n", global_vector,
 	       (polarity ? "high" : "low"), (edge_triggered ? "edge" : "level"), vector);
 
 	/* program the IOSAPIC routing table */
@@ -395,51 +471,40 @@
  * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
  */
 int
-iosapic_register_platform_irq (u32 int_type, u32 global_vector, u32 iosapic_vector,
-			       u16 eid, u16 id, unsigned long polarity,
+iosapic_register_platform_irq (u32 int_type, u32 global_vector,
+			       u32 iosapic_vector, u16 eid, u16 id, unsigned long polarity,
 			       unsigned long edge_triggered, u32 base_irq, char *iosapic_address)
 {
-	struct hw_interrupt_type *irq_type;
-	irq_desc_t *idesc;
+	unsigned char delivery;
 	int vector;
 
 	switch (int_type) {
-	      case ACPI20_ENTRY_PIS_CPEI:
+	case ACPI20_ENTRY_PIS_PMI:
+		vector = iosapic_vector;
+		/*
+		 * since PMI vector is alloc'd by FW(ACPI) not by kernel,
+		 * we need to make sure the vector is available
+		 */
+		iosapic_reassign_vector(vector);
+		delivery = IOSAPIC_PMI;
+		break;
+	case ACPI20_ENTRY_PIS_CPEI:
 		vector = IA64_PCE_VECTOR;
-		iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
+		delivery = IOSAPIC_LOWEST_PRIORITY;
 		break;
-	      case ACPI20_ENTRY_PIS_INIT:
+	case ACPI20_ENTRY_PIS_INIT:
 		vector = ia64_alloc_irq();
-		iosapic_irq[vector].dmode = IOSAPIC_INIT;
+		delivery = IOSAPIC_INIT;
 		break;
-	      default:
+	default:
 		printk("iosapic_register_platform_irq(): invalid int type\n");
 		return -1;
 	}
 
-	/* fill in information from this vector's IOSAPIC */
-	iosapic_irq[vector].addr = iosapic_address;
-	iosapic_irq[vector].base_irq = base_irq;
-	iosapic_irq[vector].pin	= global_vector - iosapic_irq[vector].base_irq;
-	iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
-
-	if (edge_triggered) {
-		iosapic_irq[vector].trigger = IOSAPIC_EDGE;
-		irq_type = &irq_type_iosapic_edge;
-	} else {
-		iosapic_irq[vector].trigger = IOSAPIC_LEVEL;
-		irq_type = &irq_type_iosapic_level;
-	}
-
-	idesc = irq_desc(vector);
-	if (idesc->handler != irq_type) {
-		if (idesc->handler != &no_irq_type)
-			printk("iosapic_register_platform_irq(): changing vector 0x%02x from"
-			       "%s to %s\n", vector, idesc->handler->typename, irq_type->typename);
-		idesc->handler = irq_type;
-	}
+	register_irq(global_vector, vector, global_vector - base_irq, delivery, polarity,
+		     edge_triggered, base_irq, iosapic_address);
 
-	printk("PLATFORM int %x: IOSAPIC %x(%s,%s) -> Vector %x CPU %.02u:%.02u\n",
+	printk("PLATFORM int 0x%x: IOSAPIC 0x%x(%s,%s) -> Vector 0x%x CPU %.02u:%.02u\n",
 	       int_type, global_vector, (polarity ? "high" : "low"),
 	       (edge_triggered ? "edge" : "level"), vector, eid, id);
 
@@ -450,15 +515,18 @@
 
 
 /*
- * ACPI calls this when it finds an entry for a legacy ISA interrupt.  Note that the
- * irq_base and IOSAPIC address must be set in iosapic_init().
+ * ACPI calls this when it finds an entry for a legacy ISA interrupt.
+ * Note that the irq_base and IOSAPIC address must be set in iosapic_init().
  */
 void
 iosapic_register_legacy_irq (unsigned long irq,
 			     unsigned long pin, unsigned long polarity,
 			     unsigned long edge_triggered)
 {
-	unsigned int vector = isa_irq_to_vector(irq);
+	int vector = isa_irq_to_vector(irq);
+
+	register_irq(irq, vector, (int)pin, IOSAPIC_LOWEST_PRIORITY, polarity, edge_triggered,
+		     0, NULL);		/* ignored for override */
 
 #ifdef DEBUG_IRQ_ROUTING
 	printk("ISA: IRQ %u -> IOSAPIC irq 0x%02x (%s, %s) -> vector %02x\n",
@@ -467,18 +535,14 @@
 	       vector);
 #endif
 
-	iosapic_irq[vector].pin = pin;
-	iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
-	iosapic_irq[vector].polarity = polarity ? IOSAPIC_POL_HIGH : IOSAPIC_POL_LOW;
-	iosapic_irq[vector].trigger = edge_triggered ? IOSAPIC_EDGE : IOSAPIC_LEVEL;
+	/* program the IOSAPIC routing table */
+	set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 }
 
 void __init
 iosapic_init (unsigned long phys_addr, unsigned int base_irq, int pcat_compat)
 {
-	struct hw_interrupt_type *irq_type;
-	int i, irq, max_pin, vector;
-	irq_desc_t *idesc;
+	int i, irq, max_pin, vector, pin;
 	unsigned int ver;
 	char *addr;
 	static int first_time = 1;
@@ -496,7 +560,6 @@
 	}
 
 	addr = ioremap(phys_addr, 0);
-
 	ver = iosapic_version(addr);
 	max_pin = (ver >> 16) & 0xff;
 
@@ -511,27 +574,18 @@
 		 */
 		for (irq = 0; irq < 16; ++irq) {
 			vector = isa_irq_to_vector(irq);
-			iosapic_irq[vector].addr = addr;
-			iosapic_irq[vector].base_irq = 0;
-			if (iosapic_irq[vector].pin == -1)
-				iosapic_irq[vector].pin = irq;
-			iosapic_irq[vector].dmode = IOSAPIC_LOWEST_PRIORITY;
-			iosapic_irq[vector].trigger  = IOSAPIC_EDGE;
-			iosapic_irq[vector].polarity = IOSAPIC_POL_HIGH;
+			if ((pin = iosapic_irq[vector].pin) == -1)
+				pin = irq;
+
+			register_irq(irq, vector, pin,
+				     /* IOSAPIC_POL_HIGH, IOSAPIC_EDGE */
+				     IOSAPIC_LOWEST_PRIORITY, 1, 1, base_irq, addr);
+
 #ifdef DEBUG_IRQ_ROUTING
 			printk("ISA: IRQ %u -> IOSAPIC irq 0x%02x (high, edge) -> vector 0x%02x\n",
 			       irq, iosapic_irq[vector].base_irq + iosapic_irq[vector].pin,
 			       vector);
 #endif
-			irq_type = &irq_type_iosapic_edge;
-			idesc = irq_desc(vector);
-			if (idesc->handler != irq_type) {
-				if (idesc->handler != &no_irq_type)
-					printk("iosapic_init: changing vector 0x%02x from %s to "
-					       "%s\n", irq, idesc->handler->typename,
-					       irq_type->typename);
-				idesc->handler = irq_type;
-			}
 
 			/* program the IOSAPIC routing table: */
 			set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
@@ -540,7 +594,7 @@
 	for (i = 0; i < pci_irq.num_routes; i++) {
 		irq = pci_irq.route[i].irq;
 
-		if ((unsigned) (irq - base_irq) > max_pin)
+		if ((irq < (int)base_irq) || (irq > (int)(base_irq + max_pin)))
 			/* the interrupt route is for another controller... */
 			continue;
 
@@ -553,29 +607,18 @@
 				vector = ia64_alloc_irq();
 		}
 
-		iosapic_irq[vector].addr     = addr;
-		iosapic_irq[vector].base_irq = base_irq;
-		iosapic_irq[vector].pin	     = (irq - base_irq);
-		iosapic_irq[vector].dmode    = IOSAPIC_LOWEST_PRIORITY;
-		iosapic_irq[vector].trigger  = IOSAPIC_LEVEL;
-		iosapic_irq[vector].polarity = IOSAPIC_POL_LOW;
+		register_irq(irq, vector, irq - base_irq,
+			     /* IOSAPIC_POL_LOW, IOSAPIC_LEVEL */
+			     IOSAPIC_LOWEST_PRIORITY, 0, 0, base_irq, addr);
 
 # ifdef DEBUG_IRQ_ROUTING
 		printk("PCI: (B%d,I%d,P%d) -> IOSAPIC irq 0x%02x -> vector 0x%02x\n",
 		       pci_irq.route[i].bus, pci_irq.route[i].pci_id>>16, pci_irq.route[i].pin,
 		       iosapic_irq[vector].base_irq + iosapic_irq[vector].pin, vector);
 # endif
-		irq_type = &irq_type_iosapic_level;
-		idesc = irq_desc(vector);
-		if (idesc->handler != irq_type){
-			if (idesc->handler != &no_irq_type)
-				printk("iosapic_init: changing vector 0x%02x from %s to %s\n",
-				       vector, idesc->handler->typename, irq_type->typename);
-			idesc->handler = irq_type;
-		}
 
-		/* program the IOSAPIC routing table: */
-		set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
+			/* program the IOSAPIC routing table: */
+			set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 	}
 }
 
@@ -585,6 +628,8 @@
 	struct	pci_dev	*dev;
 	unsigned char pin;
 	int vector;
+	struct hw_interrupt_type *irq_type;
+	irq_desc_t *idesc;
 
 	if (phase != 1)
 		return;
@@ -611,19 +656,28 @@
 				if (vector >= 0)
 					printk(KERN_WARNING
 					       "PCI: using PPB(B%d,I%d,P%d) to get vector %02x\n",
-					       bridge->bus->number, PCI_SLOT(bridge->devfn),
+					       dev->bus->number, PCI_SLOT(dev->devfn),
 					       pin, vector);
 				else
 					printk(KERN_WARNING
-					       "PCI: Couldn't map irq for (B%d,I%d,P%d)o\n",
-					       bridge->bus->number, PCI_SLOT(bridge->devfn),
-					       pin);
+					       "PCI: Couldn't map irq for (B%d,I%d,P%d)\n",
+					       dev->bus->number, PCI_SLOT(dev->devfn), pin);
 			}
 			if (vector >= 0) {
 				printk("PCI->APIC IRQ transform: (B%d,I%d,P%d) -> 0x%02x\n",
 				       dev->bus->number, PCI_SLOT(dev->devfn), pin, vector);
 				dev->irq = vector;
 
+				irq_type = &irq_type_iosapic_level;
+				idesc = irq_desc(vector);
+				if (idesc->handler != irq_type){
+					if (idesc->handler != &no_irq_type)
+						printk("iosapic_pci_fixup: changing vector 0x%02x from "
+						       "%s to %s\n", vector,
+						       idesc->handler->typename,
+						       irq_type->typename);
+					idesc->handler = irq_type;
+				}
 #ifdef CONFIG_SMP
 				/*
 				 * For platforms that do not support interrupt redirect
@@ -638,7 +692,16 @@
 					cpu_index++;
 					if (cpu_index >= smp_num_cpus)
 						cpu_index = 0;
+				} else {
+					/*
+					 * Direct the interrupt vector to the current cpu,
+					 * platform redirection will distribute them.
+					 */
+					set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 				}
+#else
+				/* direct the interrupt vector to the running cpu id */
+				set_rte(vector, (ia64_get_lid() >> 16) & 0xffff);
 #endif
 			}
 		}
diff -Nru a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
--- a/arch/ia64/kernel/irq.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/irq.c	Fri Mar 15 17:51:02 2002
@@ -161,7 +161,7 @@
 
 		for (action=action->next; action; action = action->next)
 			seq_printf(p, ", %s", action->name);
-		seq_putc('\n');
+		seq_putc(p, '\n');
 	}
 	seq_puts(p, "NMI: ");
 	for (j = 0; j < smp_num_cpus; j++)
@@ -287,10 +287,11 @@
 		 * already executing in one..
 		 */
 		if (!irqs_running())
-			if (local_bh_count() || !spin_is_locked(&global_bh_lock))
+			if (really_local_bh_count() || !spin_is_locked(&global_bh_lock))
 				break;
 
 		/* Duh, we have to loop. Release the lock to avoid deadlocks */
+		smp_mb__before_clear_bit();	/* need barrier before releasing lock... */
 		clear_bit(0,&global_irq_lock);
 
 		for (;;) {
@@ -305,7 +306,7 @@
 				continue;
 			if (global_irq_lock)
 				continue;
-			if (!local_bh_count() && spin_is_locked(&global_bh_lock))
+			if (!really_local_bh_count() && spin_is_locked(&global_bh_lock))
 				continue;
 			if (!test_and_set_bit(0,&global_irq_lock))
 				break;
@@ -378,14 +379,14 @@
 	__save_flags(flags);
 	if (flags & IA64_PSR_I) {
 		__cli();
-		if (!local_irq_count())
+		if (!really_local_irq_count())
 			get_irqlock();
 	}
 #else
 	__save_flags(flags);
 	if (flags & (1 << EFLAGS_IF_SHIFT)) {
 		__cli();
-		if (!local_irq_count())
+		if (!really_local_irq_count())
 			get_irqlock();
 	}
 #endif
@@ -393,7 +394,7 @@
 
 void __global_sti(void)
 {
-	if (!local_irq_count())
+	if (!really_local_irq_count())
 		release_irqlock(smp_processor_id());
 	__sti();
 }
@@ -422,7 +423,7 @@
 	retval = 2 + local_enabled;
 
 	/* check for global flags if we're not in an interrupt */
-	if (!local_irq_count()) {
+	if (!really_local_irq_count()) {
 		if (local_enabled)
 			retval = 1;
 		if (global_irq_holder == cpu)
@@ -529,7 +530,7 @@
 	disable_irq_nosync(irq);
 
 #ifdef CONFIG_SMP
-	if (!local_irq_count()) {
+	if (!really_local_irq_count()) {
 		do {
 			barrier();
 		} while (irq_desc(irq)->status & IRQ_INPROGRESS);
@@ -1009,6 +1010,11 @@
 		rand_initialize_irq(irq);
 	}
 
+	if (new->flags & SA_PERCPU_IRQ) {
+		desc->status |= IRQ_PER_CPU;
+		desc->handler = &irq_type_ia64_lsapic;
+	}
+
 	/*
 	 * The following block of code has to be executed atomically
 	 */
@@ -1089,13 +1095,25 @@
 static struct proc_dir_entry * smp_affinity_entry [NR_IRQS];
 
 static unsigned long irq_affinity [NR_IRQS] = { [0 ... NR_IRQS-1] = ~0UL };
+static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
+
+void set_irq_affinity_info(int irq, int hwid, int redir)
+{
+	unsigned long mask = 1UL<<cpu_logical_id(hwid);
+
+	if (irq >= 0 && irq < NR_IRQS) {
+		irq_affinity[irq] = mask;
+		irq_redir[irq] = (char) (redir & 0xff);
+	}
+}
 
 static int irq_affinity_read_proc (char *page, char **start, off_t off,
 			int count, int *eof, void *data)
 {
-	if (count < HEX_DIGITS+1)
+	if (count < HEX_DIGITS+3)
 		return -EINVAL;
-	return sprintf (page, "%08lx\n", irq_affinity[(long)data]);
+	return sprintf (page, "%s%08lx\n", irq_redir[(long)data] ? "r " : "",
+			irq_affinity[(long)data]);
 }
 
 static int irq_affinity_write_proc (struct file *file, const char *buffer,
@@ -1103,11 +1121,20 @@
 {
 	int irq = (long) data, full_count = count, err;
 	unsigned long new_value;
+	const char *buf = buffer;
+	int redir;
 
 	if (!irq_desc(irq)->handler->set_affinity)
 		return -EIO;
 
-	err = parse_hex_value(buffer, count, &new_value);
+	if (buf[0] == 'r' || buf[0] == 'R') {
+		++buf;
+		while (*buf == ' ') ++buf;
+		redir = 1;
+	} else
+		redir = 0;
+
+	err = parse_hex_value(buf, count, &new_value);
 
 	/*
 	 * Do not allow disabling IRQs completely - it's a too easy
@@ -1117,8 +1144,7 @@
 	if (!(new_value & cpu_online_map))
 		return -EINVAL;
 
-	irq_affinity[irq] = new_value;
-	irq_desc(irq)->handler->set_affinity(irq, new_value);
+	irq_desc(irq)->handler->set_affinity(irq | (redir?(1<<31):0), new_value);
 
 	return full_count;
 }
diff -Nru a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
--- a/arch/ia64/kernel/ivt.S	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/kernel/ivt.S	Fri Mar 15 17:51:01 2002
@@ -43,6 +43,7 @@
 #include <asm/processor.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
+#include <asm/thread_info.h>
 #include <asm/unistd.h>
 
 #if 1
@@ -275,6 +276,7 @@
 	mov r16=cr.ifa		// get address that caused the TLB miss
 	movl r17=PAGE_KERNEL
 	mov r21=cr.ipsr
+	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
 	mov r31=pr
 	;;
 #ifdef CONFIG_DISABLE_VHPT
@@ -289,12 +291,12 @@
 (p8)	br.cond.dptk itlb_fault
 #endif
 	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
+	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
 	shr.u r18=r16,57	// move address bit 61 to bit 4
-	dep r19=0,r16,IA64_MAX_PHYS_BITS,(64-IA64_MAX_PHYS_BITS)	// clear ed & reserved bits
 	;;
 	andcm r18=0x10,r18	// bit 4=~address-bit(61)
 	cmp.ne p8,p0=r0,r23	// psr.cpl != 0?
-	dep r19=r17,r19,0,12	// insert PTE control bits into r19
+	or r19=r17,r19		// insert PTE control bits into r19
 	;;
 	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
 (p8)	br.cond.spnt page_fault
@@ -312,6 +314,7 @@
 	mov r16=cr.ifa		// get address that caused the TLB miss
 	movl r17=PAGE_KERNEL
 	mov r20=cr.isr
+	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
 	mov r21=cr.ipsr
 	mov r31=pr
 	;;
@@ -328,15 +331,15 @@
 #endif
 	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
 	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
+	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
 	shr.u r18=r16,57	// move address bit 61 to bit 4
-	dep r19=0,r16,IA64_MAX_PHYS_BITS,(64-IA64_MAX_PHYS_BITS) // clear ed & reserved bits
 	;;
 	andcm r18=0x10,r18	// bit 4=~address-bit(61)
 	cmp.ne p8,p0=r0,r23
 (p8)	br.cond.spnt page_fault
 
 	dep r21=-1,r21,IA64_PSR_ED_BIT,1
-	dep r19=r17,r19,0,12	// insert PTE control bits into r19
+	or r19=r19,r17		// insert PTE control bits into r19
 	;;
 	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
 (p6)	mov cr.ipsr=r21
@@ -642,7 +645,6 @@
 
 	mov r3=255
 	adds r15=-1024,r15			// r15 contains the syscall number---subtract 1024
-	adds r2=IA64_TASK_PTRACE_OFFSET,r13	// r2 = &current->ptrace
 	;;
 	cmp.geu p6,p7=r3,r15		// (syscall > 0 && syscall <= 1024+255) ?
 	movl r16=sys_call_table
@@ -654,16 +656,16 @@
 	ld8 r16=[r16]				// load address of syscall entry point
 	mov rp=r15				// set the real return addr
 	;;
-	ld8 r2=[r2]				// r2 = current->ptrace
 	mov b6=r16
 
 	// arrange things so we skip over break instruction when returning:
 
 	adds r16=16,sp				// get pointer to cr_ipsr
 	adds r17=24,sp				// get pointer to cr_iip
+	add r2=TI_FLAGS+IA64_TASK_SIZE,r13
 	;;
 	ld8 r18=[r16]				// fetch cr_ipsr
-	tbit.z p8,p0=r2,PT_TRACESYS_BIT		// (current->ptrace & PF_TRACESYS) == 0?
+	ld4 r2=[r2]				// r2 = current_thread_info()->flags
 	;;
 	ld8 r19=[r17]				// fetch cr_iip
 	extr.u r20=r18,41,2			// extract ei field
@@ -676,6 +678,7 @@
 	;;
 (p6)	st8 [r17]=r19				// store new cr.iip if cr.isr.ei wrapped around
 	dep r18=r20,r18,41,2			// insert new ei into cr.isr
+	tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
 	;;
 	st8 [r16]=r18				// store new value for cr.isr
 
@@ -855,16 +858,16 @@
 	ld4 out5=[r14],8	// r13 == ebp
 	;;
 	ld4 out3=[r14],8	// r14 == esi
-	adds r2=IA64_TASK_PTRACE_OFFSET,r13	// r2 = &current->ptrace
+	adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
 	;;
 	ld4 out4=[r14]		// r15 == edi
 	movl r16=ia32_syscall_table
 	;;
 (p6)    shladd r16=r8,3,r16	// force ni_syscall if not valid syscall number
-	ld8 r2=[r2]		// r2 = current->ptrace
+	ld4 r2=[r2]		// r2 = current_thread_info()->flags
 	;;
 	ld8 r16=[r16]
-	tbit.z p8,p0=r2,PT_TRACESYS_BIT	// (current->ptrace & PT_TRACESYS) == 0?
+	tbit.z p8,p0=r2,TIF_SYSCALL_TRACE
 	;;
 	mov b6=r16
 	movl r15=ia32_ret_from_syscall
diff -Nru a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
--- a/arch/ia64/kernel/mca.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/mca.c	Fri Mar 15 17:51:03 2002
@@ -3,6 +3,9 @@
  * Purpose:	Generic MCA handling layer
  *
  * Updated for latest kernel
+ * Copyright (C) 2002 Intel
+ * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
+ *
  * Copyright (C) 2001 Intel
  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
  *
@@ -12,6 +15,11 @@
  * Copyright (C) 1999 Silicon Graphics, Inc.
  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
  *
+ * 02/01/04 J. Hall	Aligned MCA stack to 16 bytes, added platform vs. CPU
+ *			error flag, set SAL default return values, changed
+ *			error record structure to linked list, added init call
+ *			to sal_get_state_info_size().
+ *
  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
  *                      platform errors, completed code for logging of
  *                      corrected & uncorrected machine check errors, and
@@ -27,6 +35,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/smp_lock.h>
+#include <linux/bootmem.h>
 
 #include <asm/machvec.h>
 #include <asm/page.h>
@@ -50,18 +59,22 @@
 ia64_mca_sal_to_os_state_t	ia64_sal_to_os_handoff_state;
 ia64_mca_os_to_sal_state_t	ia64_os_to_sal_handoff_state;
 u64				ia64_mca_proc_state_dump[512];
-u64				ia64_mca_stack[1024];
+u64				ia64_mca_stack[1024] __attribute__((aligned(16)));
 u64				ia64_mca_stackframe[32];
 u64				ia64_mca_bspstore[1024];
-u64				ia64_init_stack[INIT_TASK_SIZE] __attribute__((aligned(16)));
+u64				ia64_init_stack[KERNEL_STACK_SIZE] __attribute__((aligned(16)));
+u64				ia64_mca_sal_data_area[1356];
+u64				ia64_mca_min_state_save_info;
+u64				ia64_tlb_functional;
+u64				ia64_os_mca_recovery_successful;
 
 static void			ia64_mca_wakeup_ipi_wait(void);
 static void			ia64_mca_wakeup(int cpu);
 static void			ia64_mca_wakeup_all(void);
 static void			ia64_log_init(int);
-extern void		        ia64_monarch_init_handler (void);
-extern void		        ia64_slave_init_handler (void);
-extern struct hw_interrupt_type irq_type_iosapic_level;
+extern void			ia64_monarch_init_handler (void);
+extern void			ia64_slave_init_handler (void);
+extern struct hw_interrupt_type	irq_type_iosapic_level;
 
 static struct irqaction cmci_irqaction = {
 	handler:    ia64_mca_cmc_int_handler,
@@ -95,25 +108,31 @@
  *  memory.
  *
  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE/INIT)
- *  Outputs :   None
+ *  Outputs :   platform error status
  */
-void
+int
 ia64_mca_log_sal_error_record(int sal_info_type)
 {
+	int platform_err = 0;
+
 	/* Get the MCA error record */
 	if (!ia64_log_get(sal_info_type, (prfunc_t)printk))
-		return;                 // no record retrieved
+		return platform_err;                 // no record retrieved
 
-	/* Log the error record */
-	ia64_log_print(sal_info_type, (prfunc_t)printk);
+	/* TODO:
+	 * 1. analyze error logs to determine recoverability
+	 * 2. perform error recovery procedures, if applicable
+	 * 3. set ia64_os_mca_recovery_successful flag, if applicable
+	 */
 
-	/* Clear the CMC SAL logs now that they have been logged */
+	platform_err = ia64_log_print(sal_info_type, (prfunc_t)printk);
 	ia64_sal_clear_state_info(sal_info_type);
+
+	return platform_err;
 }
 
 /*
- * hack for now, add platform dependent handlers
- * here
+ * platform dependent error handling
  */
 #ifndef PLATFORM_MCA_HANDLERS
 void
@@ -275,8 +294,8 @@
 	cmcv_reg_t	cmcv;
 
 	cmcv.cmcv_regval	= 0;
-	cmcv.cmcv_mask      = 0;        /* Unmask/enable interrupt */
-	cmcv.cmcv_vector    = IA64_CMC_VECTOR;
+	cmcv.cmcv_mask		= 0;        /* Unmask/enable interrupt */
+	cmcv.cmcv_vector	= IA64_CMC_VECTOR;
 	ia64_set_cmcv(cmcv.cmcv_regval);
 
 	IA64_MCA_DEBUG("ia64_mca_platform_init: CPU %d corrected "
@@ -374,6 +393,9 @@
 
 	IA64_MCA_DEBUG("ia64_mca_init: begin\n");
 
+	/* initialize recovery success indicator */
+	ia64_os_mca_recovery_successful = 0;
+
 	/* Clear the Rendez checkin flag for all cpus */
 	for(i = 0 ; i < NR_CPUS; i++)
 		ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
@@ -459,7 +481,7 @@
 
 	/*
 	 *  Configure the CMCI vector and handler. Interrupts for CMC are
-	 *  per-processor, so AP CMC interrupts are setup in smp_callin() (smp.c).
+	 *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
 	 */
 	register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
 	ia64_mca_cmc_vector_setup();       /* Setup vector on BSP & enable */
@@ -498,6 +520,9 @@
 	ia64_log_init(SAL_INFO_TYPE_CMC);
 	ia64_log_init(SAL_INFO_TYPE_CPE);
 
+	/* Zero the min state save info */
+	ia64_mca_min_state_save_info = 0;
+
 #if defined(MCA_TEST)
 	mca_test();
 #endif /* #if defined(MCA_TEST) */
@@ -576,7 +601,7 @@
 	int cpu;
 
 	/* Clear the Rendez checkin flag for all cpus */
-	for(cpu = 0 ; cpu < smp_num_cpus; cpu++)
+	for(cpu = 0; cpu < smp_num_cpus; cpu++)
 		if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
 			ia64_mca_wakeup(cpu);
 
@@ -668,6 +693,13 @@
 
 	/* Cold Boot for uncorrectable MCA */
 	ia64_os_to_sal_handoff_state.imots_os_status = IA64_MCA_COLD_BOOT;
+
+	/* Default = tell SAL to return to same context */
+	ia64_os_to_sal_handoff_state.imots_context = IA64_MCA_SAME_CONTEXT;
+
+	/* Register pointer to new min state values */
+	/* NOTE: need to do something with this during recovery phase */
+	ia64_os_to_sal_handoff_state.imots_new_min_state = &ia64_mca_min_state_save_info;
 }
 
 /*
@@ -678,10 +710,10 @@
  *	This is the place where the core of OS MCA handling is done.
  *	Right now the logs are extracted and displayed in a well-defined
  *	format. This handler code is supposed to be run only on the
- *	monarch processor. Once the  monarch is done with MCA handling
+ *	monarch processor. Once the monarch is done with MCA handling
  *	further MCA logging is enabled by clearing logs.
  *	Monarch also has the duty of sending wakeup-IPIs to pull the
- *  slave processors out of rendezvous spinloop.
+ *	slave processors out of rendezvous spinloop.
  *
  *  Inputs  :   None
  *  Outputs :   None
@@ -689,20 +721,16 @@
 void
 ia64_mca_ucmc_handler(void)
 {
-#if 0   /* stubbed out @FVL */
-	/*
-	 *  Attempting to log a DBE error Causes "reserved register/field panic"
-	 *  in printk.
-	 */
+	int platform_err = 0;
 
 	/* Get the MCA error record and log it */
-	ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
-#endif  /* stubbed out @FVL */
+	platform_err = ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
 
 	/*
 	 *  Do Platform-specific mca error handling if required.
 	 */
-	mca_handler_platform() ;
+	if (platform_err)
+		mca_handler_platform();
 
 	/*
 	 *  Wakeup all the processors which are spinning in the rendezvous
@@ -749,13 +777,16 @@
 {
 	spinlock_t	isl_lock;
 	int		isl_index;
-	ia64_err_rec_t  isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
+	ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
 } ia64_state_log_t;
 
 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
 
-/* Note:  Some of these macros assume IA64_MAX_LOGS is always 2.  Should be */
-/* fixed. @FVL                                                              */
+#define IA64_LOG_ALLOCATE(it, size) \
+	{ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
+		(ia64_err_rec_t *)alloc_bootmem(size); \
+	ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
+		(ia64_err_rec_t *)alloc_bootmem(size);}
 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
@@ -765,13 +796,13 @@
     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
 #define IA64_LOG_INDEX_DEC(it) \
     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
-#define IA64_LOG_NEXT_BUFFER(it)   (void *)(&(ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
-#define IA64_LOG_CURR_BUFFER(it)   (void *)(&(ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
+#define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
+#define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
 
 /*
  * C portion of the OS INIT handler
  *
- * Called from ia64_<monarch/slave>_init_handler
+ * Called from ia64_monarch_init_handler
  *
  * Inputs: pointer to pt_regs where processor info was saved.
  *
@@ -885,10 +916,18 @@
 void
 ia64_log_init(int sal_info_type)
 {
-	IA64_LOG_LOCK_INIT(sal_info_type);
+	u64	max_size = 0;
+
 	IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
-	memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0,
-	       sizeof(ia64_err_rec_t) * IA64_MAX_LOGS);
+	IA64_LOG_LOCK_INIT(sal_info_type);
+
+	// SAL will tell us the maximum size of any error record of this type
+	max_size = ia64_sal_get_state_info_size(sal_info_type);
+
+	// set up OS data structures to hold error info
+	IA64_LOG_ALLOCATE(sal_info_type, max_size);
+	memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
+	memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
 }
 
 /*
@@ -923,8 +962,7 @@
 		return total_len;
 	} else {
 		IA64_LOG_UNLOCK(sal_info_type);
-		prfunc("ia64_log_get: Failed to retrieve SAL error record type %d\n",
-		       sal_info_type);
+		prfunc("ia64_log_get: No SAL error record available for type %d\n", sal_info_type);
 		return 0;
 	}
 }
@@ -1268,7 +1306,7 @@
 	}
 
 	if (mdei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)mdei->header.len,
+		platform_mem_dev_err_print((int)mdei->header.len,
 				      (int)sizeof(sal_log_mem_dev_err_info_t) - 1,
 				      &(mdei->oem_data[0]), prfunc);
 	}
@@ -1357,7 +1395,7 @@
 		prfunc("\n");
 
 	if (pbei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)pbei->header.len,
+		platform_pci_bus_err_print((int)pbei->header.len,
 				      (int)sizeof(sal_log_pci_bus_err_info_t) - 1,
 				      &(pbei->oem_data[0]), prfunc);
 	}
@@ -1456,7 +1494,7 @@
 		}
 	}
 	if (pcei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)pcei->header.len, n_pci_data,
+		platform_pci_comp_err_print((int)pcei->header.len, n_pci_data,
 				      p_oem_data, prfunc);
 		prfunc("\n");
 	}
@@ -1485,7 +1523,7 @@
 		ia64_log_prt_guid(&psei->guid, prfunc);
 	}
 	if (psei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)psei->header.len,
+		platform_plat_specific_err_print((int)psei->header.len,
 				      (int)sizeof(sal_log_plat_specific_err_info_t) - 1,
 				      &(psei->oem_data[0]), prfunc);
 	}
@@ -1519,7 +1557,7 @@
 	if (hcei->valid.bus_spec_data)
 		prfunc(" Bus Specific Data: %#lx", hcei->bus_spec_data);
 	if (hcei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)hcei->header.len,
+		platform_host_ctlr_err_print((int)hcei->header.len,
 				      (int)sizeof(sal_log_host_ctlr_err_info_t) - 1,
 				      &(hcei->oem_data[0]), prfunc);
 	}
@@ -1553,7 +1591,7 @@
 	if (pbei->valid.bus_spec_data)
 		prfunc(" Bus Specific Data: %#lx", pbei->bus_spec_data);
 	if (pbei->valid.oem_data) {
-		ia64_log_prt_oem_data((int)pbei->header.len,
+		platform_plat_bus_err_print((int)pbei->header.len,
 				      (int)sizeof(sal_log_plat_bus_err_info_t) - 1,
 				      &(pbei->oem_data[0]), prfunc);
 	}
@@ -1745,17 +1783,18 @@
  *  Inputs  :   lh      (Pointer to the sal error record header with format
  *                       specified by the SAL spec).
  *              prfunc  (fn ptr of log output function to use)
- *  Outputs :   None
+ *  Outputs :	platform error status
  */
-void
+int
 ia64_log_platform_info_print (sal_log_record_header_t *lh, prfunc_t prfunc)
 {
-	sal_log_section_hdr_t       *slsh;
-	int                         n_sects;
-	int                         ercd_pos;
+	sal_log_section_hdr_t	*slsh;
+	int			n_sects;
+	int			ercd_pos;
+	int			platform_err = 0;
 
 	if (!lh)
-		return;
+		return platform_err;
 
 #ifdef MCA_PRT_XTRA_DATA    // for test only @FVL
 	ia64_log_prt_record_header(lh, prfunc);
@@ -1765,7 +1804,7 @@
 		IA64_MCA_DEBUG("ia64_mca_log_print: "
 			       "truncated SAL error record. len = %d\n",
 			       lh->len);
-		return;
+		return platform_err;
 	}
 
 	/* Print record header info */
@@ -1796,35 +1835,43 @@
 			ia64_log_proc_dev_err_info_print((sal_log_processor_info_t *)slsh,
 							 prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_MEM_DEV_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Memory Device Error Info Section\n");
 			ia64_log_mem_dev_err_info_print((sal_log_mem_dev_err_info_t *)slsh,
 							prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_SEL_DEV_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform SEL Device Error Info Section\n");
 			ia64_log_sel_dev_err_info_print((sal_log_sel_dev_err_info_t *)slsh,
 							prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_PCI_BUS_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform PCI Bus Error Info Section\n");
 			ia64_log_pci_bus_err_info_print((sal_log_pci_bus_err_info_t *)slsh,
 							prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform SMBIOS Device Error Info Section\n");
 			ia64_log_smbios_dev_err_info_print((sal_log_smbios_dev_err_info_t *)slsh,
 							   prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_PCI_COMP_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform PCI Component Error Info Section\n");
 			ia64_log_pci_comp_err_info_print((sal_log_pci_comp_err_info_t *)slsh,
 							 prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_SPECIFIC_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Specific Error Info Section\n");
 			ia64_log_plat_specific_err_info_print((sal_log_plat_specific_err_info_t *)
 							      slsh,
 							      prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_HOST_CTLR_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Host Controller Error Info Section\n");
 			ia64_log_host_ctlr_err_info_print((sal_log_host_ctlr_err_info_t *)slsh,
 							  prfunc);
 		} else if (efi_guidcmp(slsh->guid, SAL_PLAT_BUS_ERR_SECT_GUID) == 0) {
+			platform_err = 1;
 			prfunc("+Platform Bus Error Info Section\n");
 			ia64_log_plat_bus_err_info_print((sal_log_plat_bus_err_info_t *)slsh,
 							 prfunc);
@@ -1838,8 +1885,9 @@
 		       n_sects, lh->len);
 	if (!n_sects) {
 		prfunc("No Platform Error Info Sections found\n");
-		return;
+		return platform_err;
 	}
+	return platform_err;
 }
 
 /*
@@ -1849,15 +1897,17 @@
  *
  *  Inputs   :  info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
  *              prfunc      (fn ptr of log output function to use)
- * Outputs	:	None
+ * Outputs	:	platform error status
  */
-void
+int
 ia64_log_print(int sal_info_type, prfunc_t prfunc)
 {
+	int platform_err = 0;
+
 	switch(sal_info_type) {
 	      case SAL_INFO_TYPE_MCA:
 		prfunc("+BEGIN HARDWARE ERROR STATE AT MCA\n");
-		ia64_log_platform_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc);
+		platform_err = ia64_log_platform_info_print(IA64_LOG_CURR_BUFFER(sal_info_type), prfunc);
 		prfunc("+END HARDWARE ERROR STATE AT MCA\n");
 		break;
 	      case SAL_INFO_TYPE_INIT:
@@ -1877,4 +1927,5 @@
 		prfunc("+MCA UNKNOWN ERROR LOG (UNIMPLEMENTED)\n");
 		break;
 	}
+	return platform_err;
 }
diff -Nru a/arch/ia64/kernel/mca_asm.S b/arch/ia64/kernel/mca_asm.S
--- a/arch/ia64/kernel/mca_asm.S	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/mca_asm.S	Fri Mar 15 17:51:02 2002
@@ -7,6 +7,12 @@
 // 00/03/29 cfleck Added code to save INIT handoff state in pt_regs format, switch to temp
 //		   kstack, switch modes, jump to C INIT handler
 //
+// 02/01/04 J.Hall <jenna.s.hall@intel.com>
+//		   Before entering virtual mode code:
+//		   1. Check for TLB CPU error
+//		   2. Restore current thread pointer to kr6
+//		   3. Move stack ptr 16 bytes to conform to C calling convention
+//
 #include <linux/config.h>
 
 #include <asm/asmmacro.h>
@@ -21,10 +27,21 @@
  */
 #define	MINSTATE_PHYS	/* Make sure stack access is physical for MINSTATE */
 
+/*
+ * Needed for ia64_sal call
+ */
+#define SAL_GET_STATE_INFO      0x01000001
+
+/*
+ * Needed for return context to SAL
+ */
+#define IA64_MCA_SAME_CONTEXT	0x0
+#define IA64_MCA_COLD_BOOT	-2
+
 #include "minstate.h"
 
 /*
- *  SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
+ * SAL_TO_OS_MCA_HANDOFF_STATE (SAL 3.0 spec)
  *		1. GR1 = OS GP
  *		2. GR8 = PAL_PROC physical address
  *		3. GR9 = SAL_PROC physical address
@@ -40,26 +57,34 @@
 	st8	[_tmp]=r9,0x08;;			\
 	st8	[_tmp]=r10,0x08;;			\
 	st8	[_tmp]=r11,0x08;;			\
-	st8	[_tmp]=r12,0x08;;
+	st8	[_tmp]=r12,0x08
 
 /*
- *  OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
- *      1. GR8 = OS_MCA return status
+ * OS_MCA_TO_SAL_HANDOFF_STATE (SAL 3.0 spec)
+ * (p6) is executed if we never entered virtual mode (TLB error)
+ * (p7) is executed if we entered virtual mode as expected (normal case)
+ *	1. GR8 = OS_MCA return status
  *	2. GR9 = SAL GP (physical)
- *      3. GR10 = 0/1 returning same/new context
- *      4. GR22 = New min state save area pointer
- *      returns ptr to SAL rtn save loc in _tmp
+ *	3. GR10 = 0/1 returning same/new context
+ *	4. GR22 = New min state save area pointer
+ *	returns ptr to SAL rtn save loc in _tmp
  */
-#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp)				\
-	movl	_tmp=ia64_os_to_sal_handoff_state;;				\
-	DATA_VA_TO_PA(_tmp);;							\
-	ld8	r8=[_tmp],0x08;;						\
-	ld8	r9=[_tmp],0x08;;						\
-	ld8     r10=[_tmp],0x08;;						\
-	ld8     r22=[_tmp],0x08;;						\
-	movl    _tmp=ia64_sal_to_os_handoff_state;;				\
-	DATA_VA_TO_PA(_tmp);;							\
-	add     _tmp=0x28,_tmp;;            // point to SAL rtn save location
+#define OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(_tmp)	\
+(p6)	movl	_tmp=ia64_sal_to_os_handoff_state;;	\
+(p7)	movl	_tmp=ia64_os_to_sal_handoff_state;;	\
+	DATA_VA_TO_PA(_tmp);;				\
+(p6)	movl	r8=IA64_MCA_COLD_BOOT;			\
+(p6)	movl	r10=IA64_MCA_SAME_CONTEXT;		\
+(p6)	add     _tmp=0x18,_tmp;;			\
+(p6)	ld8	r9=[_tmp],0x10;				\
+(p6)	movl	r22=ia64_mca_min_state_save_info;;	\
+(p7)	ld8	r8=[_tmp],0x08;;			\
+(p7)	ld8	r9=[_tmp],0x08;;			\
+(p7)	ld8     r10=[_tmp],0x08;;			\
+(p7)	ld8     r22=[_tmp],0x08;;			\
+	DATA_VA_TO_PA(r22)
+	// now _tmp is pointing to SAL rtn save location
+
 
 	.global ia64_os_mca_dispatch
 	.global ia64_os_mca_dispatch_end
@@ -70,6 +95,9 @@
 	.global	ia64_mca_stackframe
 	.global	ia64_mca_bspstore
 	.global ia64_init_stack
+	.global ia64_mca_sal_data_area
+	.global ia64_tlb_functional
+	.global ia64_mca_min_state_save_info
 
 	.text
 	.align 16
@@ -90,26 +118,34 @@
 	//	  for ia64_mca_sal_to_os_state_t has been
 	//	  defined in include/asm/mca.h
 	SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
+	;;
 
 	// LOG PROCESSOR STATE INFO FROM HERE ON..
-	;;
 begin_os_mca_dump:
 	br	ia64_os_mca_proc_state_dump;;
 
 ia64_os_mca_done_dump:
 
 	// Setup new stack frame for OS_MCA handling
-	movl    r2=ia64_mca_bspstore;;      // local bspstore area location in r2
+	movl	r2=ia64_mca_bspstore;;	// local bspstore area location in r2
 	DATA_VA_TO_PA(r2);;
-	movl    r3=ia64_mca_stackframe;;    // save stack frame to memory in r3
+	movl	r3=ia64_mca_stackframe;; // save stack frame to memory in r3
 	DATA_VA_TO_PA(r3);;
-	rse_switch_context(r6,r3,r2);;                  // RSC management in this new context
-	movl        r12=ia64_mca_stack;;
-	mov     r2=8*1024;;                 // stack size must be same as c array
-	add     r12=r2,r12;;                // stack base @ bottom of array
+	rse_switch_context(r6,r3,r2);;	// RSC management in this new context
+	movl	r12=ia64_mca_stack
+	mov	r2=8*1024;;		// stack size must be same as C array
+	add	r12=r2,r12;;		// stack base @ bottom of array
+	adds	r12=-16,r12;;		// allow 16 bytes of scratch
+					// (C calling convention)
 	DATA_VA_TO_PA(r12);;
 
-	// Enter virtual mode from physical mode
+	// Check to see if the MCA resulted from a TLB error
+begin_tlb_error_check:
+        br      ia64_os_mca_tlb_error_check;;
+
+done_tlb_error_check:
+
+        // If TLB is functional, enter virtual mode from physical mode
 	VIRTUAL_MODE_ENTER(r2, r3, ia64_os_mca_virtual_begin, r4)
 ia64_os_mca_virtual_begin:
 
@@ -130,25 +166,28 @@
 #endif	/* #if defined(MCA_TEST) */
 
 	// restore the original stack frame here
-	movl    r2=ia64_mca_stackframe               // restore stack frame from memory at r2
+	movl    r2=ia64_mca_stackframe	// restore stack frame from memory at r2
 	;;
 	DATA_VA_TO_PA(r2)
 	movl    r4=IA64_PSR_MC
 	;;
-	rse_return_context(r4,r3,r2)                 // switch from interrupt context for RSE
+	rse_return_context(r4,r3,r2)	// switch from interrupt context for RSE
 
 	// let us restore all the registers from our PSI structure
-	mov		r8=gp
+	mov	r8=gp
 	;;
 begin_os_mca_restore:
 	br	ia64_os_mca_proc_state_restore;;
 
 ia64_os_mca_done_restore:
-	;;
+	movl	r3=ia64_tlb_functional;;
+	DATA_VA_TO_PA(r3);;
+	ld8	r3=[r3];;
+	cmp.eq	p6,p7=r0,r3;;
+	OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2);;
 	// branch back to SALE_CHECK
-	OS_MCA_TO_SAL_HANDOFF_STATE_RESTORE(r2)
 	ld8		r3=[r2];;
-	mov		b0=r3;;			      // SAL_CHECK return address
+	mov		b0=r3;;		// SAL_CHECK return address
 	br		b0
 	;;
 ia64_os_mca_dispatch_end:
@@ -405,7 +444,7 @@
 	movl		r2=ia64_mca_proc_state_dump	// Convert virtual address
 	;;						// of OS state dump area
 	DATA_VA_TO_PA(r2)				// to physical address
-	;;
+
 restore_GRs:                                    // restore bank-1 GRs 16-31
 	bsw.1;;
 	add		r3=16*8,r2;;                // to get to NaT of GR 16-31
@@ -621,6 +660,80 @@
 
 //EndStub//////////////////////////////////////////////////////////////////////
 
+//++
+// Name:
+//	ia64_os_mca_tlb_error_check()
+//
+// Stub Description:
+//
+//	This stub checks to see if the MCA resulted from a TLB error
+//
+//--
+
+ia64_os_mca_tlb_error_check:
+
+	// Retrieve sal data structure for uncorrected MCA
+
+	// Make the ia64_sal_get_state_info() call
+	movl	r4=ia64_mca_sal_data_area;;
+	movl	r7=ia64_sal;;
+	mov	r6=r1			// save gp
+	DATA_VA_TO_PA(r4)		// convert to physical address
+	DATA_VA_TO_PA(r7);;		// convert to physical address
+	ld8	r7=[r7]			// get addr of pdesc from ia64_sal
+	movl	r3=SAL_GET_STATE_INFO;;
+	DATA_VA_TO_PA(r7);;		// convert to physical address
+	ld8	r8=[r7],8;;		// get pdesc function pointer
+	DATA_VA_TO_PA(r8)		// convert to physical address
+	ld8	r1=[r7];;		// set new (ia64_sal) gp
+	DATA_VA_TO_PA(r1)		// convert to physical address
+	mov	b6=r8
+
+	alloc	r5=ar.pfs,8,0,8,0;;	// allocate stack frame for SAL call
+	mov	out0=r3			// which SAL proc to call
+	mov	out1=r0			// error type == MCA
+	mov	out2=r0			// null arg
+	mov	out3=r4			// data copy area
+	mov	out4=r0			// null arg
+	mov	out5=r0			// null arg
+	mov	out6=r0			// null arg
+	mov	out7=r0;;		// null arg
+
+	br.call.sptk.few	b0=b6;;
+
+	mov	r1=r6			// restore gp
+	mov	ar.pfs=r5;;		// restore ar.pfs
+
+	movl	r6=ia64_tlb_functional;;
+	DATA_VA_TO_PA(r6)		// needed later
+
+	cmp.eq	p6,p7=r0,r8;;		// check SAL call return address
+(p7)	st8	[r6]=r0			// clear tlb_functional flag
+(p7)    br	tlb_failure		// error; return to SAL
+
+	// examine processor error log for type of error
+	add	r4=40+24,r4;;		// parse past record header (length=40)
+					// and section header (length=24)
+	ld4	r4=[r4]			// get valid field of processor log
+	mov	r5=0xf00;;
+	and	r5=r4,r5;;		// read bits 8-11 of valid field
+					// to determine if we have a TLB error
+	movl	r3=0x1
+	cmp.eq	p6,p7=r0,r5;;
+	// if no TLB failure, set tlb_functional flag
+(p6)	st8	[r6]=r3
+	// else clear flag
+(p7)	st8	[r6]=r0
+
+	// if no TLB failure, continue with normal virtual mode logging
+(p6)    br	done_tlb_error_check
+	// else no point in entering virtual mode for logging
+tlb_failure:
+	br      ia64_os_mca_virtual_end
+
+//EndStub//////////////////////////////////////////////////////////////////////
+
+
 // ok, the issue here is that we need to save state information so
 // it can be useable by the kernel debugger and show regs routines.
 // In order to do this, our best bet is save the current state (plus
@@ -633,7 +746,7 @@
 // This has been defined for registration purposes with SAL
 // as a part of ia64_mca_init.
 //
-// When we get here, the follow registers have been
+// When we get here, the following registers have been
 // set by the SAL for our use
 //
 //		1. GR1 = OS INIT GP
@@ -649,42 +762,10 @@
 
 
 GLOBAL_ENTRY(ia64_monarch_init_handler)
-#if defined(CONFIG_SMP) && defined(SAL_MPINIT_WORKAROUND)
-	//
-	// work around SAL bug that sends all processors to monarch entry
-	//
-	mov	r17=cr.lid
-	// XXX fix me: this is wrong: hard_smp_processor_id() is a pair of lid/eid
-	movl	r18=ia64_cpu_to_sapicid
-	;;
-	dep	r18=0,r18,61,3		// convert to physical address
-	;;
-	shr.u	r17=r17,16
-	ld4	r18=[r18]		// get the BSP ID
-	;;
-	dep	r17=0,r17,16,48
-	;;
-	cmp4.ne	p6,p0=r17,r18		// Am I the BSP ?
-(p6)	br.cond.spnt slave_init_spin_me
-	;;
-#endif
-
 
-//
-// ok, the first thing we do is stash the information
-// the SAL passed to os
-//
-_tmp = r2
-	movl	_tmp=ia64_sal_to_os_handoff_state
-	;;
-	dep	_tmp=0,_tmp, 61, 3	// get physical address
+	// stash the information the SAL passed to os
+	SAL_TO_OS_MCA_HANDOFF_STATE_SAVE(r2)
 	;;
-	st8	[_tmp]=r1,0x08;;
-	st8	[_tmp]=r8,0x08;;
-	st8	[_tmp]=r9,0x08;;
-	st8	[_tmp]=r10,0x08;;
-	st8	[_tmp]=r11,0x08;;
-	st8	[_tmp]=r12,0x08;;
 
 // now we want to save information so we can dump registers
 	SAVE_MIN_WITH_COVER
@@ -695,12 +776,10 @@
 	;;
 	SAVE_REST
 
-// ok, enough should be saved at this point to be dangerous, and  supply
+// ok, enough should be saved at this point to be dangerous, and supply
 // information for a dump
 // We need to switch to Virtual mode before hitting the C functions.
-//
-//
-//
+
 	movl	r2=IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN
 	mov	r3=psr	// get the current psr, minimum enabled at this point
 	;;
@@ -708,8 +787,8 @@
 	;;
 	movl	r3=IVirtual_Switch
 	;;
-	mov	cr.iip=r3		// short return to set the appropriate bits
-	mov	cr.ipsr=r2		// need to do an rfi to set appropriate bits
+	mov	cr.iip=r3	// short return to set the appropriate bits
+	mov	cr.ipsr=r2	// need to do an rfi to set appropriate bits
 	;;
 	rfi
 	;;
@@ -717,7 +796,7 @@
 	//
 	// We should now be running virtual
 	//
-	// Lets call the C handler to get the rest of the state info
+	// Let's call the C handler to get the rest of the state info
 	//
 	alloc r14=ar.pfs,0,0,1,0		// now it's safe (must be first in insn group!)
 	;;					//
diff -Nru a/arch/ia64/kernel/minstate.h b/arch/ia64/kernel/minstate.h
--- a/arch/ia64/kernel/minstate.h	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/minstate.h	Fri Mar 15 17:51:02 2002
@@ -92,7 +92,6 @@
  *
  * Assumed state upon entry:
  *	psr.ic: off
- *	psr.dt: off
  *	r31:	contains saved predicates (pr)
  *
  * Upon exit, the state is as follows:
@@ -186,7 +185,6 @@
  *
  * Assumed state upon entry:
  *	psr.ic: on
- *	psr.dt: on
  *	r2:	points to &pt_regs.r16
  *	r3:	points to &pt_regs.r17
  */
diff -Nru a/arch/ia64/kernel/palinfo.c b/arch/ia64/kernel/palinfo.c
--- a/arch/ia64/kernel/palinfo.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/kernel/palinfo.c	Fri Mar 15 17:51:01 2002
@@ -724,7 +724,7 @@
 
 		status = ia64_pal_tr_read(j, i, tr_buffer, &tr_valid);
 		if (status != 0) {
-			printk(__FUNCTION__ " pal call failed on tr[%d:%d]=%ld\n", i, j, status);
+			printk("palinfo: pal call failed on tr[%d:%d]=%ld\n", i, j, status);
 			continue;
 		}
 
@@ -842,9 +842,8 @@
 palinfo_smp_call(void *info)
 {
 	palinfo_smp_data_t *data = (palinfo_smp_data_t *)info;
-	/* printk(__FUNCTION__" called on CPU %d\n", smp_processor_id());*/
 	if (data == NULL) {
-		printk(KERN_ERR __FUNCTION__" data pointer is NULL\n");
+		printk("%s palinfo: data pointer is NULL\n", KERN_ERR);
 		data->ret = 0; /* no output */
 		return;
 	}
@@ -868,11 +867,10 @@
 	ptr.page = page;
 	ptr.ret  = 0; /* just in case */
 
-	/*printk(__FUNCTION__" calling CPU %d from CPU %d for function %d\n", f->req_cpu,smp_processor_id(), f->func_id);*/
 
 	/* will send IPI to other CPU and wait for completion of remote call */
 	if ((ret=smp_call_function_single(f->req_cpu, palinfo_smp_call, &ptr, 0, 1))) {
-		printk(__FUNCTION__" remote CPU call from %d to %d on function %d: error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
+		printk("palinfo: remote CPU call from %d to %d on function %d: error %d\n", smp_processor_id(), f->req_cpu, f->func_id, ret);
 		return 0;
 	}
 	return ptr.ret;
@@ -881,7 +879,7 @@
 static
 int palinfo_handle_smp(pal_func_cpu_u_t *f, char *page)
 {
-	printk(__FUNCTION__" should not be called with non SMP kernel\n");
+	printk("palinfo: should not be called with non SMP kernel\n");
 	return 0;
 }
 #endif /* CONFIG_SMP */
diff -Nru a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
--- a/arch/ia64/kernel/perfmon.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/perfmon.c	Fri Mar 15 17:51:02 2002
@@ -1,13 +1,16 @@
 /*
- * This file contains the code to configure and read/write the ia64 performance
- * monitoring stuff.
+ * This file implements the perfmon subsystem which is used
+ * to program the IA-64 Performance Monitoring Unit (PMU).
  *
  * Originaly Written by Ganesh Venkitachalam, IBM Corp.
- * Modifications by David Mosberger-Tang, Hewlett-Packard Co.
- * Modifications by Stephane Eranian, Hewlett-Packard Co.
  * Copyright (C) 1999 Ganesh Venkitachalam <venkitac@us.ibm.com>
- * Copyright (C) 1999 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 2000-2001 Stephane Eranian <eranian@hpl.hp.com>
+ *
+ * Modifications by Stephane Eranian, Hewlett-Packard Co.
+ * Modifications by David Mosberger-Tang, Hewlett-Packard Co.
+ *
+ * Copyright (C) 1999-2002  Hewlett Packard Co
+ *               Stephane Eranian <eranian@hpl.hp.com>
+ *               David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/config.h>
@@ -22,151 +25,137 @@
 #include <linux/mm.h>
 
 #include <asm/bitops.h>
-#include <asm/efi.h>
 #include <asm/errno.h>
-#include <asm/hw_irq.h>
 #include <asm/page.h>
 #include <asm/pal.h>
 #include <asm/perfmon.h>
-#include <asm/pgtable.h>
 #include <asm/processor.h>
 #include <asm/signal.h>
 #include <asm/system.h>
-#include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/delay.h> /* for ia64_get_itc() */
 
 #ifdef CONFIG_PERFMON
 
-#define PFM_VERSION		"0.3"
-#define PFM_SMPL_HDR_VERSION	1
-
-#define PMU_FIRST_COUNTER	4	/* first generic counter */
-
-#define PFM_WRITE_PMCS		0xa0
-#define PFM_WRITE_PMDS		0xa1
-#define PFM_READ_PMDS		0xa2
-#define PFM_STOP		0xa3
-#define PFM_START		0xa4
-#define PFM_ENABLE		0xa5	/* unfreeze only */
-#define PFM_DISABLE		0xa6	/* freeze only */
-#define PFM_RESTART		0xcf
-#define PFM_CREATE_CONTEXT	0xa7
-#define PFM_DESTROY_CONTEXT	0xa8
 /*
- * Those 2 are just meant for debugging. I considered using sysctl() for
- * that but it is a little bit too pervasive. This solution is at least
- * self-contained.
+ * For PMUs which rely on the debug registers for some features, you
+ * must enable the following flag to activate the support for
+ * accessing the registers via the perfmonctl() interface.
  */
-#define PFM_DEBUG_ON		0xe0
-#define PFM_DEBUG_OFF		0xe1
-
-#define PFM_DEBUG_BASE		PFM_DEBUG_ON
-
+#ifdef CONFIG_ITANIUM
+#define PFM_PMU_USES_DBR	1
+#endif
 
 /*
- * perfmon API flags
+ * perfmon context states
  */
-#define PFM_FL_INHERIT_NONE	 0x00	/* never inherit a context across fork (default) */
-#define PFM_FL_INHERIT_ONCE	 0x01	/* clone pfm_context only once across fork() */
-#define PFM_FL_INHERIT_ALL	 0x02	/* always clone pfm_context across fork() */
-#define PFM_FL_SMPL_OVFL_NOBLOCK 0x04	/* do not block on sampling buffer overflow */
-#define PFM_FL_SYSTEM_WIDE	 0x08	/* create a system wide context */
-#define PFM_FL_EXCL_INTR	 0x10	/* exclude interrupt from system wide monitoring */
+#define PFM_CTX_DISABLED	0
+#define PFM_CTX_ENABLED		1
 
 /*
- * PMC API flags
+ * Reset register flags
  */
-#define PFM_REGFL_OVFL_NOTIFY	1		/* send notification on overflow */
+#define PFM_RELOAD_LONG_RESET	1
+#define PFM_RELOAD_SHORT_RESET	2
 
 /*
- * Private flags and masks
+ * Misc macros and definitions
  */
+#define PMU_FIRST_COUNTER	4
+
+#define PFM_IS_DISABLED() pmu_conf.pfm_is_disabled
+
+#define PMC_OVFL_NOTIFY(ctx, i)	((ctx)->ctx_soft_pmds[i].flags &  PFM_REGFL_OVFL_NOTIFY)
 #define PFM_FL_INHERIT_MASK	(PFM_FL_INHERIT_NONE|PFM_FL_INHERIT_ONCE|PFM_FL_INHERIT_ALL)
 
-#ifdef CONFIG_SMP
-#define cpu_is_online(i) (cpu_online_map & (1UL << i))
-#else
-#define cpu_is_online(i)	1
-#endif
+#define PMC_IS_IMPL(i)	  (i<pmu_conf.num_pmcs && pmu_conf.impl_regs[i>>6] & (1UL<< (i) %64))
+#define PMD_IS_IMPL(i)	  (i<pmu_conf.num_pmds &&  pmu_conf.impl_regs[4+(i>>6)] & (1UL<<(i) % 64))
+
+#define PMD_IS_COUNTING(i) (i >=0  && i < 256 && pmu_conf.counter_pmds[i>>6] & (1UL <<(i) % 64))
+#define PMC_IS_COUNTING(i) PMD_IS_COUNTING(i)
+
+#define IBR_IS_IMPL(k)	  (k<pmu_conf.num_ibrs)
+#define DBR_IS_IMPL(k)	  (k<pmu_conf.num_dbrs)
+
+#define PMC_IS_BTB(a)	  (((pfm_monitor_t *)(a))->pmc_es == PMU_BTB_EVENT)
 
-#define PMC_IS_IMPL(i)		(i < pmu_conf.num_pmcs && pmu_conf.impl_regs[i>>6] & (1<< (i&~(64-1))))
-#define PMD_IS_IMPL(i)		(i < pmu_conf.num_pmds &&  pmu_conf.impl_regs[4+(i>>6)] & (1<< (i&~(64-1))))
-#define PMD_IS_COUNTER(i)	(i>=PMU_FIRST_COUNTER && i < (PMU_FIRST_COUNTER+pmu_conf.max_counters))
-#define PMC_IS_COUNTER(i)	(i>=PMU_FIRST_COUNTER && i < (PMU_FIRST_COUNTER+pmu_conf.max_counters))
+#define LSHIFT(x)		(1UL<<(x))
+#define PMM(x)			LSHIFT(x)
+#define PMC_IS_MONITOR(c)	((pmu_conf.monitor_pmcs[0] & PMM((c))) != 0)
 
-/* This is the Itanium-specific PMC layout for counter config */
+#define CTX_IS_ENABLED(c) 	((c)->ctx_flags.state == PFM_CTX_ENABLED)
+#define CTX_OVFL_NOBLOCK(c)	((c)->ctx_fl_block == 0)
+#define CTX_INHERIT_MODE(c)	((c)->ctx_fl_inherit)
+#define CTX_HAS_SMPL(c)		((c)->ctx_psb != NULL)
+#define CTX_USED_PMD(ctx,n) 	(ctx)->ctx_used_pmds[(n)>>6] |= 1UL<< ((n) % 64)
+
+#define CTX_USED_IBR(ctx,n) 	(ctx)->ctx_used_ibrs[(n)>>6] |= 1UL<< ((n) % 64)
+#define CTX_USED_DBR(ctx,n) 	(ctx)->ctx_used_dbrs[(n)>>6] |= 1UL<< ((n) % 64)
+#define CTX_USES_DBREGS(ctx)	(((pfm_context_t *)(ctx))->ctx_fl_using_dbreg==1)
+
+#define LOCK_CTX(ctx)	spin_lock(&(ctx)->ctx_lock)
+#define UNLOCK_CTX(ctx)	spin_unlock(&(ctx)->ctx_lock)
+
+#define SET_PMU_OWNER(t)    do { pmu_owners[smp_processor_id()].owner = (t); } while(0)
+#define PMU_OWNER()	    pmu_owners[smp_processor_id()].owner
+
+#define LOCK_PFS()	    spin_lock(&pfm_sessions.pfs_lock)
+#define UNLOCK_PFS()	    spin_unlock(&pfm_sessions.pfs_lock)
+
+#define PFM_REG_RETFLAG_SET(flags, val)	do { flags &= ~PFM_REG_RETFL_MASK; flags |= (val); } while(0)
+
+/*
+ * debugging
+ */
+#define DBprintk(a) \
+	do { \
+		if (pfm_debug_mode >0) { printk("%s.%d: CPU%d ", __FUNCTION__, __LINE__, smp_processor_id()); printk a; } \
+	} while (0)
+
+
+/* 
+ * These are some helpful architected PMC and IBR/DBR register layouts
+ */
 typedef struct {
 	unsigned long pmc_plm:4;	/* privilege level mask */
 	unsigned long pmc_ev:1;		/* external visibility */
 	unsigned long pmc_oi:1;		/* overflow interrupt */
 	unsigned long pmc_pm:1;		/* privileged monitor */
 	unsigned long pmc_ig1:1;	/* reserved */
-	unsigned long pmc_es:7;		/* event select */
-	unsigned long pmc_ig2:1;	/* reserved */
-	unsigned long pmc_umask:4;	/* unit mask */
-	unsigned long pmc_thres:3;	/* threshold */
-	unsigned long pmc_ig3:1;	/* reserved (missing from table on p6-17) */
-	unsigned long pmc_ism:2;	/* instruction set mask */
-	unsigned long pmc_ig4:38;	/* reserved */
-} pmc_counter_reg_t;
-
-/* test for EAR/BTB configuration */
-#define PMU_DEAR_EVENT	0x67
-#define PMU_IEAR_EVENT	0x23
-#define PMU_BTB_EVENT	0x11
-
-#define PMC_IS_DEAR(a)		(((pmc_counter_reg_t *)(a))->pmc_es == PMU_DEAR_EVENT)
-#define PMC_IS_IEAR(a)		(((pmc_counter_reg_t *)(a))->pmc_es == PMU_IEAR_EVENT)
-#define PMC_IS_BTB(a)		(((pmc_counter_reg_t *)(a))->pmc_es == PMU_BTB_EVENT)
-
-/*
- * This header is at the beginning of the sampling buffer returned to the user.
- * It is exported as Read-Only at this point. It is directly followed with the
- * first record.
- */
-typedef struct {
-	int		hdr_version;		/* could be used to differentiate formats */
-	int		hdr_reserved;
-	unsigned long	hdr_entry_size;		/* size of one entry in bytes */
-	unsigned long	hdr_count;		/* how many valid entries */
-	unsigned long	hdr_pmds;		/* which pmds are recorded */
-} perfmon_smpl_hdr_t;
-
-/*
- * Header entry in the buffer as a header as follows.
- * The header is directly followed with the PMDS to saved in increasing index order:
- * PMD4, PMD5, .... How many PMDs are present is determined by the tool which must
- * keep track of it when generating the final trace file.
- */
-typedef struct {
-	int		pid;		/* identification of process */
-	int		cpu;		/* which cpu was used */
-	unsigned long	rate;		/* initial value of this counter */
-	unsigned long	stamp;		/* timestamp */
-	unsigned long	ip;		/* where did the overflow interrupt happened */
-	unsigned long	regs;		/* which registers overflowed (up to 64)*/
-} perfmon_smpl_entry_t;
+	unsigned long pmc_es:8;		/* event select */
+	unsigned long pmc_ig2:48;	/* reserved */
+} pfm_monitor_t;
 
 /*
  * There is one such data structure per perfmon context. It is used to describe the
- * sampling buffer. It is to be shared among siblings whereas the pfm_context isn't.
+ * sampling buffer. It is to be shared among siblings whereas the pfm_context 
+ * is not.
  * Therefore we maintain a refcnt which is incremented on fork().
- * This buffer is private to the kernel only the actual sampling buffer including its
- * header are exposed to the user. This construct allows us to export the buffer read-write,
- * if needed, without worrying about security problems.
- */
-typedef struct {
-	atomic_t		psb_refcnt;	/* how many users for the buffer */
-	int			reserved;
+ * This buffer is private to the kernel only the actual sampling buffer 
+ * including its header are exposed to the user. This construct allows us to 
+ * export the buffer read-write, if needed, without worrying about security 
+ * problems.
+ */
+typedef struct _pfm_smpl_buffer_desc {
+	spinlock_t		psb_lock;	/* protection lock */
+	unsigned long		psb_refcnt;	/* how many users for the buffer */
+	int			psb_flags;	/* bitvector of flags */
+
 	void			*psb_addr;	/* points to location of first entry */
 	unsigned long		psb_entries;	/* maximum number of entries */
 	unsigned long		psb_size;	/* aligned size of buffer */
-	unsigned long		psb_index;	/* next free entry slot */
+	unsigned long		psb_index;	/* next free entry slot XXX: must use the one in buffer */
 	unsigned long		psb_entry_size;	/* size of each entry including entry header */
 	perfmon_smpl_hdr_t	*psb_hdr;	/* points to sampling buffer header */
+
+	struct _pfm_smpl_buffer_desc *psb_next;	/* next psb, used for rvfreeing of psb_hdr */
+
 } pfm_smpl_buffer_desc_t;
 
+#define LOCK_PSB(p)	spin_lock(&(p)->psb_lock)
+#define UNLOCK_PSB(p)	spin_unlock(&(p)->psb_lock)
+
+#define PFM_PSB_VMA	0x1			/* a VMA is describing the buffer */
 
 /*
  * This structure is initialized at boot time and contains
@@ -180,126 +169,192 @@
 	unsigned long num_pmcs ;	/* highest PMC implemented (may have holes) */
 	unsigned long num_pmds;		/* highest PMD implemented (may have holes) */
 	unsigned long impl_regs[16];	/* buffer used to hold implememted PMC/PMD mask */
+	unsigned long num_ibrs;		/* number of instruction debug registers */
+	unsigned long num_dbrs;		/* number of data debug registers */
+	unsigned long monitor_pmcs[4];	/* which pmc are controlling monitors */
+	unsigned long counter_pmds[4];	/* which pmd are used as counters */
 } pmu_config_t;
 
-#define PERFMON_IS_DISABLED() pmu_conf.pfm_is_disabled
-
+/*
+ * 64-bit software counter structure
+ */
 typedef struct {
-	__u64		val;		/* virtual 64bit counter value */
-	__u64		ival;		/* initial value from user */
-	__u64		smpl_rval;	/* reset value on sampling overflow */
-	__u64		ovfl_rval;	/* reset value on overflow */
-	int		flags;		/* notify/do not notify */
+	u64 val;	/* virtual 64bit counter value */
+	u64 ival;	/* initial value from user */
+	u64 long_reset;	/* reset value on sampling overflow */
+	u64 short_reset;/* reset value on overflow */
+	u64 reset_pmds[4]; /* which other pmds to reset when this counter overflows */
+	int flags;	/* notify/do not notify */
 } pfm_counter_t;
-#define PMD_OVFL_NOTIFY(ctx, i)	((ctx)->ctx_pmds[i].flags &  PFM_REGFL_OVFL_NOTIFY)
 
 /*
- * perfmon context. One per process, is cloned on fork() depending on inheritance flags
+ * perfmon context. One per process, is cloned on fork() depending on 
+ * inheritance flags
  */
 typedef struct {
-	unsigned int inherit:2;	/* inherit mode */
-	unsigned int noblock:1;	/* block/don't block on overflow with notification */
-	unsigned int system:1;	/* do system wide monitoring */
-	unsigned int frozen:1;	/* pmu must be kept frozen on ctxsw in */
-	unsigned int exclintr:1;/* exlcude interrupts from system wide monitoring */
-	unsigned int reserved:26;
+	unsigned int state:1;		/* 0=disabled, 1=enabled */
+	unsigned int inherit:2;		/* inherit mode */
+	unsigned int block:1;		/* when 1, task will blocked on user notifications */
+	unsigned int system:1;		/* do system wide monitoring */
+	unsigned int frozen:1;		/* pmu must be kept frozen on ctxsw in */
+	unsigned int protected:1;	/* allow access to creator of context only */
+	unsigned int using_dbreg:1;	/* using range restrictions (debug registers) */
+	unsigned int reserved:24;
 } pfm_context_flags_t;
 
+/*
+ * perfmon context: encapsulates all the state of a monitoring session
+ * XXX: probably need to change layout
+ */
 typedef struct pfm_context {
+	pfm_smpl_buffer_desc_t	*ctx_psb;		/* sampling buffer, if any */
+	unsigned long		ctx_smpl_vaddr;		/* user level virtual address of smpl buffer */
 
-	pfm_smpl_buffer_desc_t	*ctx_smpl_buf;		/* sampling buffer descriptor, if any */
-	unsigned long		ctx_dear_counter;	/* which PMD holds D-EAR */
-	unsigned long		ctx_iear_counter;	/* which PMD holds I-EAR */
-	unsigned long		ctx_btb_counter;	/* which PMD holds BTB */
-
-	spinlock_t		ctx_notify_lock;
+	spinlock_t		ctx_lock;
 	pfm_context_flags_t	ctx_flags;		/* block/noblock */
-	int			ctx_notify_sig;		/* XXX: SIGPROF or other */
+
 	struct task_struct	*ctx_notify_task;	/* who to notify on overflow */
-	struct task_struct	*ctx_creator;		/* pid of creator (debug) */
+	struct task_struct	*ctx_owner;		/* pid of creator (debug) */
+
+	unsigned long		ctx_ovfl_regs[4];	/* which registers overflowed (notification) */
+	unsigned long		ctx_smpl_regs[4];	/* which registers to record on overflow */
 
-	unsigned long		ctx_ovfl_regs;		/* which registers just overflowed (notification) */
-	unsigned long		ctx_smpl_regs;		/* which registers to record on overflow */
+	struct semaphore	ctx_restart_sem;   	/* use for blocking notification mode */
 
-	struct semaphore	ctx_restart_sem; 	/* use for blocking notification mode */
+	unsigned long		ctx_used_pmds[4];	/* bitmask of used PMD (speedup ctxsw) */
+	unsigned long		ctx_saved_pmcs[4];	/* bitmask of PMC to save on ctxsw */
+	unsigned long		ctx_reload_pmcs[4];	/* bitmask of PMC to reload on ctxsw (SMP) */
 
-	unsigned long		ctx_used_pmds[4]; 	/* bitmask of used PMD (speedup ctxsw) */
-	unsigned long		ctx_used_pmcs[4]; 	/* bitmask of used PMC (speedup ctxsw) */
+	unsigned long		ctx_used_ibrs[4];	/* bitmask of used IBR (speedup ctxsw) */
+	unsigned long		ctx_used_dbrs[4];	/* bitmask of used DBR (speedup ctxsw) */
 
-	pfm_counter_t		ctx_pmds[IA64_NUM_PMD_COUNTERS]; /* XXX: size should be dynamic */
+	pfm_counter_t		ctx_soft_pmds[IA64_NUM_PMD_REGS]; /* XXX: size should be dynamic */
 
+	u64			ctx_saved_psr;		/* copy of psr used for lazy ctxsw */
+	unsigned long		ctx_saved_cpus_allowed;	/* copy of the task cpus_allowed (system wide) */
+	unsigned long		ctx_cpu;		/* cpu to which perfmon is applied (system wide) */
+
+	atomic_t		ctx_saving_in_progress;	/* flag indicating actual save in progress */
+	atomic_t		ctx_last_cpu;		/* CPU id of current or last CPU used */
 } pfm_context_t;
 
-#define CTX_USED_PMD(ctx,n) (ctx)->ctx_used_pmds[(n)>>6] |= 1<< ((n) % 64)
-#define CTX_USED_PMC(ctx,n) (ctx)->ctx_used_pmcs[(n)>>6] |= 1<< ((n) % 64)
+#define ctx_fl_inherit		ctx_flags.inherit
+#define ctx_fl_block		ctx_flags.block
+#define ctx_fl_system		ctx_flags.system
+#define ctx_fl_frozen		ctx_flags.frozen
+#define ctx_fl_protected	ctx_flags.protected
+#define ctx_fl_using_dbreg	ctx_flags.using_dbreg
 
-#define ctx_fl_inherit	ctx_flags.inherit
-#define ctx_fl_noblock	ctx_flags.noblock
-#define ctx_fl_system	ctx_flags.system
-#define ctx_fl_frozen	ctx_flags.frozen
-#define ctx_fl_exclintr	ctx_flags.exclintr
+/*
+ * global information about all sessions
+ * mostly used to synchronize between system wide and per-process
+ */
+typedef struct {
+	spinlock_t		pfs_lock;		/* lock the structure */
 
-#define CTX_OVFL_NOBLOCK(c)	((c)->ctx_fl_noblock == 1)
-#define CTX_INHERIT_MODE(c)	((c)->ctx_fl_inherit)
-#define CTX_HAS_SMPL(c)		((c)->ctx_smpl_buf != NULL)
+	unsigned long		pfs_task_sessions;	/* number of per task sessions */
+	unsigned long		pfs_sys_sessions;	/* number of per system wide sessions */
+	unsigned long   	pfs_sys_use_dbregs;	  	/* incremented when a system wide session uses debug regs */
+	unsigned long   	pfs_ptrace_use_dbregs;	  /* incremented when a process uses debug regs */
+	struct task_struct	*pfs_sys_session[NR_CPUS];  /* point to task owning a system-wide session */
+} pfm_session_t;
 
-static pmu_config_t pmu_conf;
+/*
+ * structure used to pass argument to/from remote CPU 
+ * using IPI to check and possibly save the PMU context on SMP systems.
+ *
+ * not used in UP kernels
+ */
+typedef struct {
+	struct task_struct *task;	/* which task we are interested in */
+	int retval;			/* return value of the call: 0=you can proceed, 1=need to wait for completion */
+} pfm_smp_ipi_arg_t;
 
-/* for debug only */
-static int pfm_debug=0;	/* 0= nodebug, >0= debug output on */
+/*
+ * perfmon command descriptions
+ */
+typedef struct {
+	int		(*cmd_func)(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs);
+	int		cmd_flags;
+	unsigned int	cmd_narg;
+	size_t		cmd_argsize;
+} pfm_cmd_desc_t;
 
-#define DBprintk(a) \
-	do { \
-		if (pfm_debug >0) { printk(__FUNCTION__" %d: ", __LINE__); printk a; } \
-	} while (0);
+#define PFM_CMD_PID		0x1	/* command requires pid argument */
+#define PFM_CMD_ARG_READ	0x2	/* command must read argument(s) */
+#define PFM_CMD_ARG_WRITE	0x4	/* command must write argument(s) */
+#define PFM_CMD_CTX		0x8	/* command needs a perfmon context */
+#define PFM_CMD_NOCHK		0x10	/* command does not need to check task's state */
+
+#define PFM_CMD_IDX(cmd)	(cmd)
+
+#define PFM_CMD_IS_VALID(cmd)	((PFM_CMD_IDX(cmd) >= 0) && (PFM_CMD_IDX(cmd) < PFM_CMD_COUNT) \
+				  && pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_func != NULL)
+
+#define PFM_CMD_USE_PID(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_PID) != 0)
+#define PFM_CMD_READ_ARG(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_ARG_READ) != 0)
+#define PFM_CMD_WRITE_ARG(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_ARG_WRITE) != 0)
+#define PFM_CMD_USE_CTX(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_CTX) != 0)
+#define PFM_CMD_CHK(cmd)	((pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_flags & PFM_CMD_NOCHK) == 0)
+
+#define PFM_CMD_ARG_MANY	-1 /* cannot be zero */
+#define PFM_CMD_NARG(cmd)	(pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_narg)
+#define PFM_CMD_ARG_SIZE(cmd)	(pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_argsize)
 
-static void ia64_reset_pmu(void);
 
 /*
- * structure used to pass information between the interrupt handler
- * and the tasklet.
+ * perfmon internal variables
  */
-typedef struct {
-	pid_t		to_pid;		/* which process to notify */
-	pid_t		from_pid;	/* which process is source of overflow */
-	int		sig;		/* with which signal */
-	unsigned long	bitvect;	/* which counters have overflowed */
-} notification_info_t;
+static pmu_config_t	pmu_conf; 	/* PMU configuration */
+static int		pfm_debug_mode;	/* 0= nodebug, >0= debug output on */
+static pfm_session_t	pfm_sessions;	/* global sessions information */
+static struct proc_dir_entry *perfmon_dir; /* for debug only */
+static unsigned long pfm_spurious_ovfl_intr_count; /* keep track of spurious ovfl interrupts */
+static unsigned long pfm_ovfl_intr_count; /* keep track of spurious ovfl interrupts */
+static unsigned long pfm_recorded_samples_count;
 
 
-typedef struct {
-	unsigned long pfs_proc_sessions;
-	unsigned long pfs_sys_session; /* can only be 0/1 */
-	unsigned long pfs_dfl_dcr;	/* XXX: hack */
-	unsigned int  pfs_pp;
-} pfm_session_t;
+static unsigned long reset_pmcs[IA64_NUM_PMC_REGS];	/* contains PAL reset values for PMCS */
+
+static void pfm_vm_close(struct vm_area_struct * area);
+static struct vm_operations_struct pfm_vm_ops={
+	close: pfm_vm_close
+};
 
-struct {
+/*
+ * keep track of task owning the PMU per CPU.
+ */
+static struct {
 	struct task_struct *owner;
 } ____cacheline_aligned pmu_owners[NR_CPUS];
 
 
-/* 
- * helper macros
- */
-#define SET_PMU_OWNER(t)	do { pmu_owners[smp_processor_id()].owner = (t); } while(0);
-#define PMU_OWNER()		pmu_owners[smp_processor_id()].owner
 
+/*
+ * forward declarations
+ */
+static void ia64_reset_pmu(struct task_struct *);
 #ifdef CONFIG_SMP
-#define PFM_CAN_DO_LAZY()	(smp_num_cpus==1 && pfs_info.pfs_sys_session==0)
-#else
-#define PFM_CAN_DO_LAZY()	(pfs_info.pfs_sys_session==0)
+static void pfm_fetch_regs(int cpu, struct task_struct *task, pfm_context_t *ctx);
 #endif
-
 static void pfm_lazy_save_regs (struct task_struct *ta);
 
-/* for debug only */
-static struct proc_dir_entry *perfmon_dir;
+static inline unsigned long
+pfm_read_soft_counter(pfm_context_t *ctx, int i)
+{
+	return ctx->ctx_soft_pmds[i].val + (ia64_get_pmd(i) & pmu_conf.perf_ovfl_val);
+}
 
-/*
- * XXX: hack to indicate that a system wide monitoring session is active
- */
-static pfm_session_t pfs_info;
+static inline void
+pfm_write_soft_counter(pfm_context_t *ctx, int i, unsigned long val)
+{
+	ctx->ctx_soft_pmds[i].val = val  & ~pmu_conf.perf_ovfl_val;
+	/*
+	 * writing to unimplemented part is ignore, so we do not need to
+	 * mask off top part
+	 */
+	ia64_set_pmd(i, val);
+}
 
 /*
  * finds the number of PM(C|D) registers given
@@ -324,10 +379,10 @@
  * Generates a unique (per CPU) timestamp
  */
 static inline unsigned long
-perfmon_get_stamp(void)
+pfm_get_stamp(void)
 {
 	/*
-	 * XXX: maybe find something more efficient
+	 * XXX: must find something more efficient
 	 */
 	return ia64_get_itc();
 }
@@ -336,15 +391,16 @@
  * This is used when initializing the contents of the area.
  */
 static inline unsigned long
-kvirt_to_pa(unsigned long adr)
+pfm_kvirt_to_pa(unsigned long adr)
 {
 	__u64 pa = ia64_tpa(adr);
-	DBprintk(("kv2pa(%lx-->%lx)\n", adr, pa));
+	//DBprintk(("kv2pa(%lx-->%lx)\n", adr, pa));
 	return pa;
 }
 
+
 static void *
-rvmalloc(unsigned long size)
+pfm_rvmalloc(unsigned long size)
 {
 	void *mem;
 	unsigned long adr;
@@ -352,6 +408,7 @@
 	size=PAGE_ALIGN(size);
 	mem=vmalloc(size);
 	if (mem) {
+		//printk("perfmon: CPU%d pfm_rvmalloc(%ld)=%p\n", smp_processor_id(), size, mem);
 		memset(mem, 0, size); /* Clear the ram out, no junk to the user */
 		adr=(unsigned long) mem;
 		while (size > 0) {
@@ -364,37 +421,145 @@
 }
 
 static void
-rvfree(void *mem, unsigned long size)
+pfm_rvfree(void *mem, unsigned long size)
 {
 	unsigned long adr;
 
 	if (mem) {
 		adr=(unsigned long) mem;
 		while ((long) size > 0) {
-			mem_map_unreserve(vmalloc_to_page((void *)adr));
+			mem_map_unreserve(vmalloc_to_page((void*)adr));
 			adr+=PAGE_SIZE;
 			size-=PAGE_SIZE;
 		}
 		vfree(mem);
 	}
+	return;
+}
+
+/*
+ * This function gets called from mm/mmap.c:exit_mmap() only when there is a sampling buffer
+ * attached to the context AND the current task has a mapping for it, i.e., it is the original
+ * creator of the context.
+ *
+ * This function is used to remember the fact that the vma describing the sampling buffer
+ * has now been removed. It can only be called when no other tasks share the same mm context.
+ *
+ */
+static void 
+pfm_vm_close(struct vm_area_struct *vma)
+{
+	pfm_smpl_buffer_desc_t *psb = (pfm_smpl_buffer_desc_t *)vma->vm_private_data;
+
+	if (psb == NULL) {
+		printk("perfmon: psb is null in [%d]\n", current->pid);
+		return;
+	}
+	/*
+	 * Add PSB to list of buffers to free on release_thread() when no more users
+	 *
+	 * This call is safe because, once the count is zero is cannot be modified anymore.
+	 * This is not because there is no more user of the mm context, that the sampling
+	 * buffer is not being used anymore outside of this task. In fact, it can still
+	 * be accessed from within the kernel by another task (such as the monitored task).
+	 *
+	 * Therefore, we only move the psb into the list of buffers to free when we know
+	 * nobody else is using it.
+	 * The linked list if independent of the perfmon context, because in the case of
+	 * multi-threaded processes, the last thread may not have been involved with
+	 * monitoring however it will be the one removing the vma and it should therefore
+	 * also remove the sampling buffer. This buffer cannot be removed until the vma
+	 * is removed.
+	 *
+	 * This function cannot remove the buffer from here, because exit_mmap() must first
+	 * complete. Given that there is no other vma related callback in the generic code,
+	 * we have created on own with the linked list of sampling buffer to free which
+	 * is part of the thread structure. In release_thread() we check if the list is
+	 * empty. If not we call into perfmon to free the buffer and psb. That is the only
+	 * way to ensure a safe deallocation of the sampling buffer which works when
+	 * the buffer is shared between distinct processes or with multi-threaded programs.
+	 *
+	 * We need to lock the psb because the refcnt test and flag manipulation must
+	 * looked like an atomic operation vis a vis pfm_context_exit()
+	 */
+	LOCK_PSB(psb);
+
+	if (psb->psb_refcnt == 0) {
+
+		psb->psb_next = current->thread.pfm_smpl_buf_list;
+		current->thread.pfm_smpl_buf_list = psb;
+
+		DBprintk(("psb for [%d] smpl @%p size %ld inserted into list\n", 
+			current->pid, psb->psb_hdr, psb->psb_size));
+	}
+	DBprintk(("psb vma flag cleared for [%d] smpl @%p size %ld inserted into list\n", 
+			current->pid, psb->psb_hdr, psb->psb_size));
+
+	/*
+	 * indicate to pfm_context_exit() that the vma has been removed. 
+	 */
+	psb->psb_flags &= ~PFM_PSB_VMA;
+
+	UNLOCK_PSB(psb);
+}
+
+/*
+ * This function is called from pfm_destroy_context() and also from pfm_inherit()
+ * to explicitely remove the sampling buffer mapping from the user level address space.
+ */
+static int
+pfm_remove_smpl_mapping(struct task_struct *task)
+{
+	pfm_context_t *ctx = task->thread.pfm_context;
+	pfm_smpl_buffer_desc_t *psb;
+	int r;
+
+	/*
+	 * some sanity checks first
+	 */
+	if (ctx == NULL || task->mm == NULL || ctx->ctx_smpl_vaddr == 0 || ctx->ctx_psb == NULL) {
+		printk("perfmon: invalid context mm=%p\n", task->mm);
+		return -1;
+	}
+	psb = ctx->ctx_psb;	
+
+	down_write(&task->mm->mmap_sem);
+
+	r = do_munmap(task->mm, ctx->ctx_smpl_vaddr, psb->psb_size);
+
+	up_write(&task->mm->mmap_sem);
+	if (r !=0) {
+		printk("perfmon: pid %d unable to unmap sampling buffer @0x%lx size=%ld\n", 
+				task->pid, ctx->ctx_smpl_vaddr, psb->psb_size);
+	}
+	DBprintk(("[%d] do_unmap(0x%lx, %ld)=%d\n", 
+		task->pid, ctx->ctx_smpl_vaddr, psb->psb_size, r));
+
+	/* 
+	 * make sure we suppress all traces of this buffer
+	 * (important for pfm_inherit)
+	 */
+	ctx->ctx_smpl_vaddr = 0;
+
+	return 0;
 }
 
 static pfm_context_t *
 pfm_context_alloc(void)
 {
-	pfm_context_t *pfc;
+	pfm_context_t *ctx;
 
 	/* allocate context descriptor */
-	pfc = vmalloc(sizeof(*pfc));
-	if (pfc) memset(pfc, 0, sizeof(*pfc));
-
-	return pfc;
+	ctx = kmalloc(sizeof(pfm_context_t), GFP_KERNEL);
+	if (ctx) memset(ctx, 0, sizeof(pfm_context_t));
+	
+	return ctx;
 }
 
 static void
-pfm_context_free(pfm_context_t *pfc)
+pfm_context_free(pfm_context_t *ctx)
 {
-	if (pfc) vfree(pfc);
+	if (ctx) kfree(ctx);
 }
 
 static int
@@ -402,11 +567,13 @@
 {
 	unsigned long page;
 
+	DBprintk(("CPU%d buf=0x%lx addr=0x%lx size=%ld\n", smp_processor_id(), buf, addr, size));
+
 	while (size > 0) {
-		page = kvirt_to_pa(buf);
+		page = pfm_kvirt_to_pa(buf);
 
 		if (remap_page_range(vma, addr, page, PAGE_SIZE, PAGE_SHARED)) return -ENOMEM;
-
+		
 		addr  += PAGE_SIZE;
 		buf   += PAGE_SIZE;
 		size  -= PAGE_SIZE;
@@ -426,7 +593,7 @@
 
 	for (i=0; i < size; i++, which++) res += hweight64(*which);
 
-	DBprintk((" res=%ld\n", res));
+	DBprintk(("weight=%ld\n", res));
 
 	return res;
 }
@@ -435,15 +602,16 @@
  * Allocates the sampling buffer and remaps it into caller's address space
  */
 static int
-pfm_smpl_buffer_alloc(pfm_context_t *ctx, unsigned long which_pmds, unsigned long entries, void **user_addr)
+pfm_smpl_buffer_alloc(pfm_context_t *ctx, unsigned long *which_pmds, unsigned long entries, 
+		      void **user_vaddr)
 {
 	struct mm_struct *mm = current->mm;
-	struct vm_area_struct *vma;
-	unsigned long addr, size, regcount;
+	struct vm_area_struct *vma = NULL;
+	unsigned long size, regcount;
 	void *smpl_buf;
 	pfm_smpl_buffer_desc_t *psb;
 
-	regcount = pfm_smpl_entry_size(&which_pmds, 1);
+	regcount = pfm_smpl_entry_size(which_pmds, 1);
 
 	/* note that regcount might be 0, in this case only the header for each
 	 * entry will be recorded.
@@ -456,132 +624,206 @@
 			  + entries * (sizeof(perfmon_smpl_entry_t) + regcount*sizeof(u64)));
 	/*
 	 * check requested size to avoid Denial-of-service attacks
-	 * XXX: may have to refine this test
+	 * XXX: may have to refine this test	
+	 * Check against address space limit.
+	 *
+	 * if ((mm->total_vm << PAGE_SHIFT) + len> current->rlim[RLIMIT_AS].rlim_cur) 
+	 * 	return -ENOMEM;
 	 */
 	if (size > current->rlim[RLIMIT_MEMLOCK].rlim_cur) return -EAGAIN;
 
-	/* find some free area in address space */
-	addr = get_unmapped_area(NULL, 0, size, 0, MAP_PRIVATE);
-	if (!addr) goto no_addr;
+	/*
+	 * We do the easy to undo allocations first.
+ 	 *
+	 * pfm_rvmalloc(), clears the buffer, so there is no leak
+	 */
+	smpl_buf = pfm_rvmalloc(size);
+	if (smpl_buf == NULL) {
+		DBprintk(("Can't allocate sampling buffer\n"));
+		return -ENOMEM;
+	}
+
+	DBprintk(("smpl_buf @%p\n", smpl_buf));
 
-	DBprintk((" entries=%ld aligned size=%ld, unmapped @0x%lx\n", entries, size, addr));
+	/* allocate sampling buffer descriptor now */
+	psb = kmalloc(sizeof(*psb), GFP_KERNEL);
+	if (psb == NULL) {
+		DBprintk(("Can't allocate sampling buffer descriptor\n"));
+		pfm_rvfree(smpl_buf, size);
+		return -ENOMEM;
+	}
 
 	/* allocate vma */
 	vma = kmem_cache_alloc(vm_area_cachep, SLAB_KERNEL);
-	if (!vma) goto no_vma;
-
+	if (!vma) {
+		DBprintk(("Cannot allocate vma\n"));
+		goto error;
+	}
 	/*
-	 * initialize the vma for the sampling buffer
+	 * partially initialize the vma for the sampling buffer
 	 */
-	vma->vm_mm	  = mm;
-	vma->vm_start	  = addr;
-	vma->vm_end	  = addr + size;
-	vma->vm_flags	  = VM_READ|VM_MAYREAD;
-	vma->vm_page_prot = PAGE_READONLY; /* XXX may need to change */
-	vma->vm_ops	  = NULL;
-	vma->vm_pgoff	  = 0;
-	vma->vm_file	  = NULL;
-	vma->vm_raend	  = 0;
-
-	smpl_buf = rvmalloc(size);
-	if (smpl_buf == NULL) goto no_buffer;
+	vma->vm_flags	     = VM_READ| VM_MAYREAD |VM_RESERVED;
+	vma->vm_page_prot    = PAGE_READONLY; /* XXX may need to change */
+	vma->vm_ops	     = &pfm_vm_ops; /* necesarry to get the close() callback */
+	vma->vm_pgoff	     = 0;
+	vma->vm_file	     = NULL;
+	vma->vm_raend	     = 0;
+	vma->vm_private_data = psb;	/* information needed by the pfm_vm_close() function */
 
-	DBprintk((" smpl_buf @%p\n", smpl_buf));
-
-	if (pfm_remap_buffer(vma, (unsigned long)smpl_buf, addr, size)) goto cant_remap;
-
-	/* allocate sampling buffer descriptor now */
-	psb = vmalloc(sizeof(*psb));
-	if (psb == NULL) goto no_buffer_desc;
-
-	/* start with something clean */
-	memset(smpl_buf, 0x0, size);
+	/*
+	 * Now we have everything we need and we can initialize
+	 * and connect all the data structures
+	 */
 
 	psb->psb_hdr	 = smpl_buf;
-	psb->psb_addr    = (char *)smpl_buf+sizeof(perfmon_smpl_hdr_t); /* first entry */
+	psb->psb_addr    = ((char *)smpl_buf)+sizeof(perfmon_smpl_hdr_t); /* first entry */
 	psb->psb_size    = size; /* aligned size */
 	psb->psb_index   = 0;
 	psb->psb_entries = entries;
+	psb->psb_flags   = PFM_PSB_VMA; /* remember that there is a vma describing the buffer */
+	psb->psb_refcnt  = 1;
 
-	atomic_set(&psb->psb_refcnt, 1);
+	spin_lock_init(&psb->psb_lock);
 
+	/*
+	 * XXX: will need to do cacheline alignment to avoid false sharing in SMP mode and
+	 * multitask monitoring.
+	 */
 	psb->psb_entry_size = sizeof(perfmon_smpl_entry_t) + regcount*sizeof(u64);
 
-	DBprintk((" psb @%p entry_size=%ld hdr=%p addr=%p\n", (void *)psb,psb->psb_entry_size, (void *)psb->psb_hdr, (void *)psb->psb_addr));
+	DBprintk(("psb @%p entry_size=%ld hdr=%p addr=%p\n", 
+		  (void *)psb,psb->psb_entry_size, (void *)psb->psb_hdr, 
+		  (void *)psb->psb_addr));
 
-	/* initialize some of the fields of header */
-	psb->psb_hdr->hdr_version    = PFM_SMPL_HDR_VERSION;
-	psb->psb_hdr->hdr_entry_size = sizeof(perfmon_smpl_entry_t)+regcount*sizeof(u64);
-	psb->psb_hdr->hdr_pmds	     = which_pmds;
+	/* initialize some of the fields of user visible buffer header */
+	psb->psb_hdr->hdr_version    = PFM_SMPL_VERSION;
+	psb->psb_hdr->hdr_entry_size = psb->psb_entry_size;
+	psb->psb_hdr->hdr_pmds[0]    = which_pmds[0];
 
-	/* store which PMDS to record */
-	ctx->ctx_smpl_regs = which_pmds;
+	/*
+	 * Let's do the difficult operations next.
+	 *
+	 * now we atomically find some area in the address space and
+	 * remap the buffer in it.
+	 */
+	down_write(&current->mm->mmap_sem);
 
-	/* link to perfmon context */
-	ctx->ctx_smpl_buf  = psb;
 
-	vma->vm_private_data = ctx;	/* link to pfm_context(not yet used) */
+	/* find some free area in address space, must have mmap sem held */
+	vma->vm_start = get_unmapped_area(NULL, 0, size, 0, MAP_PRIVATE|MAP_ANONYMOUS);
+	if (vma->vm_start == 0UL) {
+		DBprintk(("Cannot find unmapped area for size %ld\n", size));
+		up_write(&current->mm->mmap_sem);
+		goto error;
+	}
+	vma->vm_end = vma->vm_start + size;
+
+	DBprintk(("entries=%ld aligned size=%ld, unmapped @0x%lx\n", entries, size, vma->vm_start));
+		
+	/* can only be applied to current, need to have the mm semaphore held when called */
+	if (pfm_remap_buffer(vma, (unsigned long)smpl_buf, vma->vm_start, size)) {
+		DBprintk(("Can't remap buffer\n"));
+		up_write(&current->mm->mmap_sem);
+		goto error;
+	}
 
 	/*
-	 * now insert the vma in the vm list for the process
+	 * now insert the vma in the vm list for the process, must be
+	 * done with mmap lock held
 	 */
 	insert_vm_struct(mm, vma);
 
 	mm->total_vm  += size >> PAGE_SHIFT;
 
+	up_write(&current->mm->mmap_sem);
+
+	/* store which PMDS to record */
+	ctx->ctx_smpl_regs[0] = which_pmds[0];
+
+
+	/* link to perfmon context */
+	ctx->ctx_psb        = psb;
+
 	/*
-	 * that's the address returned to the user
+	 * keep track of user level virtual address 
 	 */
-	*user_addr = (void *)addr;
+	ctx->ctx_smpl_vaddr = *(unsigned long *)user_vaddr = vma->vm_start;
 
 	return 0;
 
-	/* outlined error handling */
-no_addr:
-	DBprintk(("Cannot find unmapped area for size %ld\n", size));
-	return -ENOMEM;
-no_vma:
-	DBprintk(("Cannot allocate vma\n"));
-	return -ENOMEM;
-cant_remap:
-	DBprintk(("Can't remap buffer\n"));
-	rvfree(smpl_buf, size);
-no_buffer:
-	DBprintk(("Can't allocate sampling buffer\n"));
-	kmem_cache_free(vm_area_cachep, vma);
-	return -ENOMEM;
-no_buffer_desc:
-	DBprintk(("Can't allocate sampling buffer descriptor\n"));
-	kmem_cache_free(vm_area_cachep, vma);
-	rvfree(smpl_buf, size);
+error:
+	pfm_rvfree(smpl_buf, size);
+	kfree(psb);
 	return -ENOMEM;
 }
 
+/*
+ * XXX: do something better here
+ */
 static int
-pfx_is_sane(pfreq_context_t *pfx)
+pfm_bad_permissions(struct task_struct *task)
+{
+	/* stolen from bad_signal() */
+	return (current->session != task->session)
+	    && (current->euid ^ task->suid) && (current->euid ^ task->uid)
+	    && (current->uid ^ task->suid) && (current->uid ^ task->uid);
+}
+
+
+static int
+pfx_is_sane(struct task_struct *task, pfarg_context_t *pfx)
 {
 	int ctx_flags;
+	int cpu;
 
 	/* valid signal */
-	//if (pfx->notify_sig < 1 || pfx->notify_sig >= _NSIG) return -EINVAL;
-	if (pfx->notify_sig !=0 && pfx->notify_sig != SIGPROF) return -EINVAL;
 
 	/* cannot send to process 1, 0 means do not notify */
-	if (pfx->notify_pid < 0 || pfx->notify_pid == 1) return -EINVAL;
-
-	ctx_flags = pfx->flags;
+	if (pfx->ctx_notify_pid == 1) {
+		DBprintk(("invalid notify_pid %d\n", pfx->ctx_notify_pid));
+		return -EINVAL;
+	}
+	ctx_flags = pfx->ctx_flags;
 
 	if (ctx_flags & PFM_FL_SYSTEM_WIDE) {
-#ifdef CONFIG_SMP
-		if (smp_num_cpus > 1) {
-			printk("perfmon: system wide monitoring on SMP not yet supported\n");
+		DBprintk(("cpu_mask=0x%lx\n", pfx->ctx_cpu_mask));
+		/*
+		 * cannot block in this mode 
+		 */
+		if (ctx_flags & PFM_FL_NOTIFY_BLOCK) {
+			DBprintk(("cannot use blocking mode when in system wide monitoring\n"));
 			return -EINVAL;
 		}
-#endif
-		if ((ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) == 0) {
-			printk("perfmon: system wide monitoring cannot use blocking notification mode\n");
+		/*
+		 * must only have one bit set in the CPU mask
+		 */
+		if (hweight64(pfx->ctx_cpu_mask) != 1UL) {
+			DBprintk(("invalid CPU mask specified\n"));
 			return -EINVAL;
 		}
+		/*
+		 * and it must be a valid CPU
+		 */
+		cpu = ffs(pfx->ctx_cpu_mask);
+		if (cpu > smp_num_cpus) {
+			DBprintk(("CPU%d is not online\n", cpu));
+			return -EINVAL;
+		}
+		/*
+		 * check for pre-existing pinning, if conflicting reject
+		 */
+		if (task->cpus_allowed != ~0UL && (task->cpus_allowed & (1UL<<cpu)) == 0) {
+			DBprintk(("[%d] pinned on 0x%lx, mask for CPU%d \n", task->pid, 
+				task->cpus_allowed, cpu));
+			return -EINVAL;
+		}
+
+	} else {
+		/*
+		 * must provide a target for the signal in blocking mode even when
+		 * no counter is configured with PFM_FL_REG_OVFL_NOTIFY
+		 */
+		if ((ctx_flags & PFM_FL_NOTIFY_BLOCK) && pfx->ctx_notify_pid == 0) return -EINVAL;
 	}
 	/* probably more to add here */
 
@@ -589,68 +831,97 @@
 }
 
 static int
-pfm_context_create(int flags, perfmon_req_t *req)
+pfm_create_context(struct task_struct *task, pfm_context_t *ctx, void *req, int count, 
+		   struct pt_regs *regs)
 {
-	pfm_context_t *ctx;
-	struct task_struct *task = NULL;
-	perfmon_req_t tmp;
+	pfarg_context_t tmp;
 	void *uaddr = NULL;
-	int ret;
+	int ret, cpu = 0;
 	int ctx_flags;
-	pid_t pid;
+	pid_t notify_pid;
 
-	/* to go away */
-	if (flags) {
-		printk("perfmon: use context flags instead of perfmon() flags. Obsoleted API\n");
-	}
+	/* a context has already been defined */
+	if (ctx) return -EBUSY;
+
+	/*
+	 * not yet supported
+	 */
+	if (task != current) return -EINVAL;
 
 	if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-	ret = pfx_is_sane(&tmp.pfr_ctx);
+	ret = pfx_is_sane(task, &tmp);
 	if (ret < 0) return ret;
 
-	ctx_flags = tmp.pfr_ctx.flags;
+	ctx_flags = tmp.ctx_flags;
+
+	ret =  -EBUSY;
+
+	LOCK_PFS();
 
 	if (ctx_flags & PFM_FL_SYSTEM_WIDE) {
+
+		/* at this point, we know there is at least one bit set */
+		cpu = ffs(tmp.ctx_cpu_mask) - 1;
+
+		DBprintk(("requesting CPU%d currently on CPU%d\n",cpu, smp_processor_id()));
+
+		if (pfm_sessions.pfs_task_sessions > 0) {
+			DBprintk(("system wide not possible, task_sessions=%ld\n", pfm_sessions.pfs_task_sessions));
+			goto abort;
+		}
+
+		if (pfm_sessions.pfs_sys_session[cpu]) {
+			DBprintk(("system wide not possible, conflicting session [%d] on CPU%d\n",pfm_sessions.pfs_sys_session[cpu]->pid, cpu));
+			goto abort;
+		}
+		pfm_sessions.pfs_sys_session[cpu] = task;
 		/*
-		 * XXX: This is not AT ALL SMP safe
+		 * count the number of system wide sessions
 		 */
-		if (pfs_info.pfs_proc_sessions > 0) return -EBUSY;
-		if (pfs_info.pfs_sys_session > 0) return -EBUSY;
+		pfm_sessions.pfs_sys_sessions++;
 
-		pfs_info.pfs_sys_session = 1;
-
-	} else if (pfs_info.pfs_sys_session >0) {
+	} else if (pfm_sessions.pfs_sys_sessions == 0) {
+		pfm_sessions.pfs_task_sessions++;
+	} else {
 		/* no per-process monitoring while there is a system wide session */
-		return -EBUSY;
-	} else
-		pfs_info.pfs_proc_sessions++;
+		goto abort;
+	}
+
+	UNLOCK_PFS();
+
+	ret = -ENOMEM;
 
 	ctx = pfm_context_alloc();
 	if (!ctx) goto error;
 
-	/* record the creator (debug only) */
-	ctx->ctx_creator = current;
+	/* record the creator (important for inheritance) */
+	ctx->ctx_owner = current;
 
-	pid = tmp.pfr_ctx.notify_pid;
+	notify_pid = tmp.ctx_notify_pid;
 
-	spin_lock_init(&ctx->ctx_notify_lock);
+	spin_lock_init(&ctx->ctx_lock);
+
+	if (notify_pid == current->pid) {
 
-	if (pid == current->pid) {
 		ctx->ctx_notify_task = task = current;
 		current->thread.pfm_context = ctx;
 
-		atomic_set(&current->thread.pfm_notifiers_check, 1);
+	} else if (notify_pid!=0) {
+		struct task_struct *notify_task;
 
-	} else if (pid!=0) {
 		read_lock(&tasklist_lock);
 
-		task = find_task_by_pid(pid);
-		if (task) {
+		notify_task = find_task_by_pid(notify_pid);
+
+		if (notify_task) {
+
+			ret = -EPERM;
+
 			/*
-		 	 * record who to notify
-		 	 */
-			ctx->ctx_notify_task = task;
+			 * check if we can send this task a signal
+			 */
+			if (pfm_bad_permissions(notify_task)) goto buffer_error;
 
 			/* 
 		 	 * make visible
@@ -669,7 +940,9 @@
 			 * task has been detached from the tasklist otherwise you are
 			 * exposed to race conditions.
 			 */
-			atomic_add(1, &task->thread.pfm_notifiers_check);
+			atomic_add(1, &ctx->ctx_notify_task->thread.pfm_notifiers_check);
+
+			ctx->ctx_notify_task = notify_task;
 		}
 		read_unlock(&tasklist_lock);
 	}
@@ -677,37 +950,48 @@
 	/*
 	 * notification process does not exist
 	 */
-	if (pid != 0 && task == NULL) {
+	if (notify_pid != 0 && ctx->ctx_notify_task == NULL) {
 		ret = -EINVAL;
 		goto buffer_error;
 	}
 
-	ctx->ctx_notify_sig = SIGPROF;	/* siginfo imposes a fixed signal */
-
-	if (tmp.pfr_ctx.smpl_entries) {
-		DBprintk((" sampling entries=%ld\n",tmp.pfr_ctx.smpl_entries));
+	if (tmp.ctx_smpl_entries) {
+		DBprintk(("sampling entries=%ld\n",tmp.ctx_smpl_entries));
 
-		ret = pfm_smpl_buffer_alloc(ctx, tmp.pfr_ctx.smpl_regs, 
-						 tmp.pfr_ctx.smpl_entries, &uaddr);
+		ret = pfm_smpl_buffer_alloc(ctx, tmp.ctx_smpl_regs, 
+						 tmp.ctx_smpl_entries, &uaddr);
 		if (ret<0) goto buffer_error;
 
-		tmp.pfr_ctx.smpl_vaddr = uaddr;
+		tmp.ctx_smpl_vaddr = uaddr;
 	}
 	/* initialization of context's flags */
-	ctx->ctx_fl_inherit  = ctx_flags & PFM_FL_INHERIT_MASK;
-	ctx->ctx_fl_noblock  = (ctx_flags & PFM_FL_SMPL_OVFL_NOBLOCK) ? 1 : 0;
-	ctx->ctx_fl_system   = (ctx_flags & PFM_FL_SYSTEM_WIDE) ? 1: 0;
-	ctx->ctx_fl_exclintr = (ctx_flags & PFM_FL_EXCL_INTR) ? 1: 0;
-	ctx->ctx_fl_frozen   = 0;
+	ctx->ctx_fl_inherit   = ctx_flags & PFM_FL_INHERIT_MASK;
+	ctx->ctx_fl_block     = (ctx_flags & PFM_FL_NOTIFY_BLOCK) ? 1 : 0;
+	ctx->ctx_fl_system    = (ctx_flags & PFM_FL_SYSTEM_WIDE) ? 1: 0;
+	ctx->ctx_fl_frozen    = 0;
+	/*
+	 * setting this flag to 0 here means, that the creator or the task that the
+	 * context is being attached are granted access. Given that a context can only
+	 * be created for the calling process this, in effect only allows the creator
+	 * to access the context. See pfm_protect() for more.
+	 */
+	ctx->ctx_fl_protected = 0;
+
+	/* for system wide mode only (only 1 bit set) */
+	ctx->ctx_cpu         = cpu;
+
+	atomic_set(&ctx->ctx_last_cpu,-1); /* SMP only, means no CPU */
 
 	/* 
 	 * Keep track of the pmds we want to sample
 	 * XXX: may be we don't need to save/restore the DEAR/IEAR pmds
 	 * but we do need the BTB for sure. This is because of a hardware
 	 * buffer of 1 only for non-BTB pmds.
+	 *
+	 * We ignore the unimplemented pmds specified by the user
 	 */
-	ctx->ctx_used_pmds[0] = tmp.pfr_ctx.smpl_regs;
-	ctx->ctx_used_pmcs[0] = 1; /* always save/restore PMC[0] */
+	ctx->ctx_used_pmds[0]  = tmp.ctx_smpl_regs[0] & pmu_conf.impl_regs[4];
+	ctx->ctx_saved_pmcs[0] = 1; /* always save/restore PMC[0] */
 
 	sema_init(&ctx->ctx_restart_sem, 0); /* init this semaphore to locked */
 
@@ -717,31 +1001,27 @@
 		goto buffer_error;
 	}
 
-	DBprintk((" context=%p, pid=%d notify_sig %d notify_task=%p\n",(void *)ctx, current->pid, ctx->ctx_notify_sig, ctx->ctx_notify_task));
-	DBprintk((" context=%p, pid=%d flags=0x%x inherit=%d noblock=%d system=%d\n",(void *)ctx, current->pid, ctx_flags, ctx->ctx_fl_inherit, ctx->ctx_fl_noblock, ctx->ctx_fl_system));
+	DBprintk(("context=%p, pid=%d notify_task=%p\n",
+			(void *)ctx, task->pid, ctx->ctx_notify_task));
+
+	DBprintk(("context=%p, pid=%d flags=0x%x inherit=%d block=%d system=%d\n", 
+			(void *)ctx, task->pid, ctx_flags, ctx->ctx_fl_inherit, 
+			ctx->ctx_fl_block, ctx->ctx_fl_system));
 
 	/*
 	 * when no notification is required, we can make this visible at the last moment
 	 */
-	if (pid == 0) current->thread.pfm_context = ctx;
-
+	if (notify_pid == 0) task->thread.pfm_context = ctx;
 	/*
-	 * by default, we always include interrupts for system wide
-	 * DCR.pp is set by default to zero by kernel  in cpu_init()
+	 * pin task to CPU and force reschedule on exit to ensure
+	 * that when back to user level the task runs on the designated
+	 * CPU.
 	 */
 	if (ctx->ctx_fl_system) {
-		if (ctx->ctx_fl_exclintr == 0) {
-			unsigned long dcr = ia64_get_dcr();
-
-			ia64_set_dcr(dcr|IA64_DCR_PP);
-			/*
-			* keep track of the kernel default value
-			 */
-			pfs_info.pfs_dfl_dcr = dcr;
-
-			DBprintk((" dcr.pp is set\n"));
-		}
-	} 
+		ctx->ctx_saved_cpus_allowed = task->cpus_allowed;
+		set_cpus_allowed(task, 1UL << cpu);
+		DBprintk(("[%d] rescheduled allowed=0x%lx\n", task->pid,task->cpus_allowed));
+	}
 
 	return 0;
 
@@ -751,225 +1031,493 @@
 	/*
 	 * undo session reservation
 	 */
+	LOCK_PFS();
+
 	if (ctx_flags & PFM_FL_SYSTEM_WIDE) {
-		pfs_info.pfs_sys_session = 0;
+		pfm_sessions.pfs_sys_session[cpu] = NULL;
+		pfm_sessions.pfs_sys_sessions--;
 	} else {
-		pfs_info.pfs_proc_sessions--;
+		pfm_sessions.pfs_task_sessions--;
 	}
+abort:
+	UNLOCK_PFS();
+
 	return ret;
 }
 
 static void
-pfm_reset_regs(pfm_context_t *ctx)
+pfm_reset_regs(pfm_context_t *ctx, unsigned long *ovfl_regs, int flag)
 {
-	unsigned long mask = ctx->ctx_ovfl_regs;
-	int i, cnum;
+	unsigned long mask = ovfl_regs[0];
+	unsigned long reset_others = 0UL;
+	unsigned long val;
+	int i;
+
+	DBprintk(("masks=0x%lx\n", mask));
 
-	DBprintk((" ovfl_regs=0x%lx\n", mask));
 	/*
 	 * now restore reset value on sampling overflowed counters
 	 */
-	for(i=0, cnum=PMU_FIRST_COUNTER; i < pmu_conf.max_counters; i++, cnum++, mask >>= 1) {
+	mask >>= PMU_FIRST_COUNTER;
+	for(i = PMU_FIRST_COUNTER; mask; i++, mask >>= 1) {
 		if (mask & 0x1) {
-			DBprintk((" reseting PMD[%d]=%lx\n", cnum, ctx->ctx_pmds[i].smpl_rval & pmu_conf.perf_ovfl_val));
+			val  = flag == PFM_RELOAD_LONG_RESET ? 
+					ctx->ctx_soft_pmds[i].long_reset:
+					ctx->ctx_soft_pmds[i].short_reset;
+
+			reset_others |= ctx->ctx_soft_pmds[i].reset_pmds[0];
+
+			DBprintk(("[%d] %s reset soft_pmd[%d]=%lx\n", 
+			  	current->pid, 
+				flag == PFM_RELOAD_LONG_RESET ? "long" : "short", i, val));
 
 			/* upper part is ignored on rval */
-			ia64_set_pmd(cnum, ctx->ctx_pmds[i].smpl_rval);
+			pfm_write_soft_counter(ctx, i, val);
+		}
+	}
 
-			/*
-			 * we must reset BTB index (clears pmd16.full to make
-			 * sure we do not report the same branches twice.
-			 * The non-blocking case in handled in update_counters()
-			 */
-			if (cnum == ctx->ctx_btb_counter) {
-				DBprintk(("reseting PMD16\n"));
-				ia64_set_pmd(16, 0);
-			}
+	/*
+	 * Now take care of resetting the other registers
+	 */
+	for(i = 0; reset_others; i++, reset_others >>= 1) {
+
+		if ((reset_others & 0x1) == 0) continue;
+
+		val  = flag == PFM_RELOAD_LONG_RESET ? 
+					ctx->ctx_soft_pmds[i].long_reset:
+					ctx->ctx_soft_pmds[i].short_reset;
+
+		if (PMD_IS_COUNTING(i)) {
+			pfm_write_soft_counter(ctx, i, val);
+		} else {
+			ia64_set_pmd(i, val);
 		}
+
+		DBprintk(("[%d] %s reset_others pmd[%d]=%lx\n", 
+			  	current->pid, 
+				flag == PFM_RELOAD_LONG_RESET ? "long" : "short", i, val));
 	}
 	/* just in case ! */
-	ctx->ctx_ovfl_regs = 0;
+	ctx->ctx_ovfl_regs[0] = 0UL;
 }
 
 static int
-pfm_write_pmcs(struct task_struct *ta, perfmon_req_t *req, int count)
+pfm_write_pmcs(struct task_struct *ta, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
 {
 	struct thread_struct *th = &ta->thread;
-	pfm_context_t *ctx = th->pfm_context;
-	perfmon_req_t tmp;
-	unsigned long cnum;
+	pfarg_reg_t tmp, *req = (pfarg_reg_t *)arg;
+	unsigned int cnum;
 	int i;
+	int ret = 0, reg_retval = 0;
+
+	/* we don't quite support this right now */
+	if (ta != current) return -EINVAL;
+
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
 	/* XXX: ctx locking may be required here */
 
 	for (i = 0; i < count; i++, req++) {
 
+
 		if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-		cnum = tmp.pfr_reg.reg_num;
+		cnum = tmp.reg_num;
 
-		/* XXX needs to check validity of the data maybe */
-		if (!PMC_IS_IMPL(cnum)) {
-			DBprintk((" invalid pmc[%ld]\n", cnum));
-			return -EINVAL;
+		/* 
+		 * we reject all non implemented PMC as well
+		 * as attempts to modify PMC[0-3] which are used
+		 * as status registers by the PMU
+		 */
+		if (!PMC_IS_IMPL(cnum) || cnum < 4) {
+			DBprintk(("pmc[%u] is unimplemented or invalid\n", cnum));
+			ret = -EINVAL;
+			goto abort_mission;
 		}
+		/*
+		 * A PMC used to configure monitors must be:
+		 * 	- system-wide session: privileged monitor
+		 * 	- per-task : user monitor
+		 * any other configuration is rejected.
+		 */
+		if (PMC_IS_MONITOR(cnum)) {
+			pfm_monitor_t *p = (pfm_monitor_t *)&tmp.reg_value;
 
-		if (PMC_IS_COUNTER(cnum)) {
+			DBprintk(("pmc[%u].pm = %d\n", cnum, p->pmc_pm));
 
+			if (ctx->ctx_fl_system ^ p->pmc_pm) {
+			//if ((ctx->ctx_fl_system == 1 && p->pmc_pm == 0)
+			 //  ||(ctx->ctx_fl_system == 0 && p->pmc_pm == 1)) {
+				ret = -EINVAL;
+				goto abort_mission;
+			}
 			/*
-			 * we keep track of EARS/BTB to speed up sampling later
+			 * enforce generation of overflow interrupt. Necessary on all
+			 * CPUs which do not implement 64-bit hardware counters.
 			 */
-			if (PMC_IS_DEAR(&tmp.pfr_reg.reg_value)) {
-				ctx->ctx_dear_counter = cnum;
-			} else if (PMC_IS_IEAR(&tmp.pfr_reg.reg_value)) {
-				ctx->ctx_iear_counter = cnum;
-			} else if (PMC_IS_BTB(&tmp.pfr_reg.reg_value)) {
-				ctx->ctx_btb_counter = cnum;
+			p->pmc_oi = 1;
+		}
+
+		if (PMC_IS_COUNTING(cnum)) {
+			if (tmp.reg_flags & PFM_REGFL_OVFL_NOTIFY) {
+				/*
+				 * must have a target for the signal
+				 */
+				if (ctx->ctx_notify_task == NULL) {
+					ret = -EINVAL;
+					goto abort_mission;
+				}
+
+				ctx->ctx_soft_pmds[cnum].flags |= PFM_REGFL_OVFL_NOTIFY;
 			}
-#if 0
-			if (tmp.pfr_reg.reg_flags & PFM_REGFL_OVFL_NOTIFY)
-				ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags |= PFM_REGFL_OVFL_NOTIFY;
-#endif
+			/*
+			 * copy reset vector
+			 */
+			ctx->ctx_soft_pmds[cnum].reset_pmds[0] = tmp.reg_reset_pmds[0];
+			ctx->ctx_soft_pmds[cnum].reset_pmds[1] = tmp.reg_reset_pmds[1];
+			ctx->ctx_soft_pmds[cnum].reset_pmds[2] = tmp.reg_reset_pmds[2];
+			ctx->ctx_soft_pmds[cnum].reset_pmds[3] = tmp.reg_reset_pmds[3];
+
+			/*
+			 * needed in case the user does not initialize the equivalent
+			 * PMD. Clearing is done in reset_pmu() so there is no possible
+			 * leak here.
+			 */
+			CTX_USED_PMD(ctx, cnum);
 		}
-		/* keep track of what we use */
-		CTX_USED_PMC(ctx, cnum);
-		ia64_set_pmc(cnum, tmp.pfr_reg.reg_value);
+abort_mission:
+		if (ret == -EINVAL) reg_retval = PFM_REG_RETFL_EINVAL;
 
-		DBprintk((" setting PMC[%ld]=0x%lx flags=0x%x used_pmcs=0%lx\n", cnum, tmp.pfr_reg.reg_value, ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags, ctx->ctx_used_pmcs[0]));
+		PFM_REG_RETFLAG_SET(tmp.reg_flags, reg_retval);
 
-	}
-	/*
-	 * we have to set this here event hough we haven't necessarily started monitoring
-	 * because we may be context switched out
-	 */
-	if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
+		/*
+		 * update register return value, abort all if problem during copy.
+		 */
+		if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT;
 
-	return 0;
+		/*
+		 * if there was something wrong on this register, don't touch
+		 * the hardware at all and abort write request for others.
+		 *
+		 * On error, the user mut sequentially scan the table and the first
+		 * entry which has a return flag set is the one that caused the error.
+		 */
+		if (ret != 0) {
+			DBprintk(("[%d] pmc[%u]=0x%lx error %d\n",
+				  ta->pid, cnum, tmp.reg_value, reg_retval));
+			break;
+		}
+
+		/* 
+		 * We can proceed with this register!
+		 */
+		
+		/* 
+		 * keep copy the pmc, used for register reload
+		 */
+		th->pmc[cnum] = tmp.reg_value;
+
+		ia64_set_pmc(cnum, tmp.reg_value);
+
+		DBprintk(("[%d] pmc[%u]=0x%lx flags=0x%x save_pmcs=0%lx reload_pmcs=0x%lx\n", 
+			  ta->pid, cnum, tmp.reg_value, 
+			  ctx->ctx_soft_pmds[cnum].flags, 
+			  ctx->ctx_saved_pmcs[0], ctx->ctx_reload_pmcs[0]));
+
+	}
+	return ret;
 }
 
 static int
-pfm_write_pmds(struct task_struct *ta, perfmon_req_t *req, int count)
+pfm_write_pmds(struct task_struct *ta, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
 {
-	struct thread_struct *th = &ta->thread;
-	pfm_context_t *ctx = th->pfm_context;
-	perfmon_req_t tmp;
-	unsigned long cnum;
+	pfarg_reg_t tmp, *req = (pfarg_reg_t *)arg;
+	unsigned int cnum;
 	int i;
+	int ret = 0, reg_retval = 0;
+
+	/* we don't quite support this right now */
+	if (ta != current) return -EINVAL;
+
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
 
 	/* XXX: ctx locking may be required here */
 
 	for (i = 0; i < count; i++, req++) {
-		int k;
 
 		if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-		cnum = tmp.pfr_reg.reg_num;
-
-		k = cnum - PMU_FIRST_COUNTER;
+		cnum = tmp.reg_num;
 
-		if (!PMD_IS_IMPL(cnum)) return -EINVAL;
+		if (!PMD_IS_IMPL(cnum)) {
+			ret = -EINVAL;
+			goto abort_mission;
+		}
 
 		/* update virtualized (64bits) counter */
-		if (PMD_IS_COUNTER(cnum)) {
-			ctx->ctx_pmds[k].ival = tmp.pfr_reg.reg_value;
-			ctx->ctx_pmds[k].val  = tmp.pfr_reg.reg_value & ~pmu_conf.perf_ovfl_val;
-			ctx->ctx_pmds[k].smpl_rval = tmp.pfr_reg.reg_smpl_reset;
-			ctx->ctx_pmds[k].ovfl_rval = tmp.pfr_reg.reg_ovfl_reset;
+		if (PMD_IS_COUNTING(cnum)) {
+			ctx->ctx_soft_pmds[cnum].ival = tmp.reg_value;
+			ctx->ctx_soft_pmds[cnum].val  = tmp.reg_value & ~pmu_conf.perf_ovfl_val;
+			ctx->ctx_soft_pmds[cnum].long_reset = tmp.reg_long_reset;
+			ctx->ctx_soft_pmds[cnum].short_reset = tmp.reg_short_reset;
+
+		}
+abort_mission:
+		if (ret == -EINVAL) reg_retval = PFM_REG_RETFL_EINVAL;
+
+		PFM_REG_RETFLAG_SET(tmp.reg_flags, reg_retval);
+
+		if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT;
 
-			if (tmp.pfr_reg.reg_flags & PFM_REGFL_OVFL_NOTIFY)
-				ctx->ctx_pmds[cnum - PMU_FIRST_COUNTER].flags |= PFM_REGFL_OVFL_NOTIFY;
+		/*
+		 * if there was something wrong on this register, don't touch
+		 * the hardware at all and abort write request for others.
+		 *
+		 * On error, the user mut sequentially scan the table and the first
+		 * entry which has a return flag set is the one that caused the error.
+		 */
+		if (ret != 0) {
+			DBprintk(("[%d] pmc[%u]=0x%lx error %d\n",
+				  ta->pid, cnum, tmp.reg_value, reg_retval));
+			break;
 		}
+
 		/* keep track of what we use */
 		CTX_USED_PMD(ctx, cnum);
 
 		/* writes to unimplemented part is ignored, so this is safe */
-		ia64_set_pmd(cnum, tmp.pfr_reg.reg_value);
+		ia64_set_pmd(cnum, tmp.reg_value);
 
 		/* to go away */
 		ia64_srlz_d();
-		DBprintk((" setting PMD[%ld]:  ovfl_notify=%d pmd.val=0x%lx pmd.ovfl_rval=0x%lx pmd.smpl_rval=0x%lx pmd=%lx used_pmds=0%lx\n",
-					cnum,
-					PMD_OVFL_NOTIFY(ctx, cnum - PMU_FIRST_COUNTER),
-					ctx->ctx_pmds[k].val,
-					ctx->ctx_pmds[k].ovfl_rval,
-					ctx->ctx_pmds[k].smpl_rval,
-					ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val,
-					ctx->ctx_used_pmds[0]));
+		DBprintk(("[%d] pmd[%u]: soft_pmd=0x%lx  short_reset=0x%lx "
+			  "long_reset=0x%lx hw_pmd=%lx notify=%c used_pmds=0x%lx reset_pmds=0x%lx\n",
+				ta->pid, cnum,
+				ctx->ctx_soft_pmds[cnum].val,
+				ctx->ctx_soft_pmds[cnum].short_reset,
+				ctx->ctx_soft_pmds[cnum].long_reset,
+				ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val,
+				PMC_OVFL_NOTIFY(ctx, cnum) ? 'Y':'N',
+				ctx->ctx_used_pmds[0],
+				ctx->ctx_soft_pmds[cnum].reset_pmds[0]));
 	}
-	/*
-	 * we have to set this here event hough we haven't necessarily started monitoring
-	 * because we may be context switched out
-	 */
-	if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
-
-	return 0;
+	return ret;
 }
 
 static int
-pfm_read_pmds(struct task_struct *ta, perfmon_req_t *req, int count)
+pfm_read_pmds(struct task_struct *ta, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
 {
 	struct thread_struct *th = &ta->thread;
-	pfm_context_t *ctx = th->pfm_context;
 	unsigned long val=0;
-	perfmon_req_t tmp;
+	pfarg_reg_t tmp, *req = (pfarg_reg_t *)arg;
 	int i;
 
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
 	/*
 	 * XXX: MUST MAKE SURE WE DON"T HAVE ANY PENDING OVERFLOW BEFORE READING
-	 * This is required when the monitoring has been stoppped by user of kernel.
-	 * If ity is still going on, then that's fine because we a re not gauranteed
-	 * to return an accurate value in this case
+	 * This is required when the monitoring has been stoppped by user or kernel.
+	 * If it is still going on, then that's fine because we a re not guaranteed
+	 * to return an accurate value in this case.
 	 */
 
 	/* XXX: ctx locking may be required here */
 
+	DBprintk(("ctx_last_cpu=%d for [%d]\n", atomic_read(&ctx->ctx_last_cpu), ta->pid));
+
 	for (i = 0; i < count; i++, req++) {
-		unsigned long reg_val = ~0, ctx_val = ~0;
+		unsigned long reg_val = ~0UL, ctx_val = ~0UL;
 
 		if (copy_from_user(&tmp, req, sizeof(tmp))) return -EFAULT;
 
-		if (!PMD_IS_IMPL(tmp.pfr_reg.reg_num)) return -EINVAL;
+		if (!PMD_IS_IMPL(tmp.reg_num)) goto abort_mission;
 
-		if (PMD_IS_COUNTER(tmp.pfr_reg.reg_num)) {
-			if (ta == current){
-				val = ia64_get_pmd(tmp.pfr_reg.reg_num);
-			} else {
-				val = reg_val = th->pmd[tmp.pfr_reg.reg_num];
+		/*
+		 * If the task is not the current one, then we check if the
+		 * PMU state is still in the local live register due to lazy ctxsw.
+		 * If true, then we read directly from the registers.
+		 */
+		if (atomic_read(&ctx->ctx_last_cpu) == smp_processor_id()){
+			ia64_srlz_d();
+			val = reg_val = ia64_get_pmd(tmp.reg_num);
+			DBprintk(("reading pmd[%u]=0x%lx from hw\n", tmp.reg_num, val));
+		} else {
+#ifdef CONFIG_SMP
+			int cpu;
+			/*
+			 * for SMP system, the context may still be live on another
+			 * CPU so we need to fetch it before proceeding with the read
+			 * This call we only be made once for the whole loop because
+			 * of ctx_last_cpu becoming == -1.
+			 *
+			 * We cannot reuse ctx_last_cpu as it may change before we get to the
+			 * actual IPI call. In this case, we will do the call for nothing but
+			 * there is no way around it. The receiving side will simply do nothing.
+			 */
+			cpu = atomic_read(&ctx->ctx_last_cpu);
+			if (cpu != -1) {
+				DBprintk(("must fetch on CPU%d for [%d]\n", cpu, ta->pid));
+				pfm_fetch_regs(cpu, ta, ctx);
 			}
-			val &= pmu_conf.perf_ovfl_val;
+#endif
+			/* context has been saved */
+			val = reg_val = th->pmd[tmp.reg_num];
+		}
+		if (PMD_IS_COUNTING(tmp.reg_num)) {
 			/*
-			 * lower part of .val may not be zero, so we must be an addition because of
-			 * residual count (see update_counters).
+			 * XXX: need to check for overflow
 			 */
-			val += ctx_val = ctx->ctx_pmds[tmp.pfr_reg.reg_num - PMU_FIRST_COUNTER].val;
+
+			val &= pmu_conf.perf_ovfl_val;
+			val += ctx_val = ctx->ctx_soft_pmds[tmp.reg_num].val;
 		} else {
-			/* for now */
-			if (ta != current) return -EINVAL;
 
-			ia64_srlz_d();
-			val = ia64_get_pmd(tmp.pfr_reg.reg_num);
+			val = reg_val = ia64_get_pmd(tmp.reg_num);
 		}
-		tmp.pfr_reg.reg_value = val;
+		PFM_REG_RETFLAG_SET(tmp.reg_flags, 0);
+		tmp.reg_value = val;
 
-		DBprintk((" reading PMD[%ld]=0x%lx reg=0x%lx ctx_val=0x%lx pmc=0x%lx\n", 
-					tmp.pfr_reg.reg_num, val, reg_val, ctx_val, ia64_get_pmc(tmp.pfr_reg.reg_num)));
+		DBprintk(("read pmd[%u] soft_pmd=0x%lx reg=0x%lx pmc=0x%lx\n", 
+					tmp.reg_num, ctx_val, reg_val, 
+					ia64_get_pmc(tmp.reg_num)));
 
 		if (copy_to_user(req, &tmp, sizeof(tmp))) return -EFAULT;
 	}
 	return 0;
+abort_mission:
+	PFM_REG_RETFLAG_SET(tmp.reg_flags, PFM_REG_RETFL_EINVAL);
+	/* 
+	 * XXX: if this fails, we stick we the original failure, flag not updated!
+	 */
+	copy_to_user(req, &tmp, sizeof(tmp));
+	return -EINVAL;
+
 }
 
+#ifdef PFM_PMU_USES_DBR
+/*
+ * Only call this function when a process it trying to
+ * write the debug registers (reading is always allowed)
+ */
+int
+pfm_use_debug_registers(struct task_struct *task)
+{
+	pfm_context_t *ctx = task->thread.pfm_context;
+	int ret = 0;
+
+	DBprintk(("called for [%d]\n", task->pid));
+
+	/*
+	 * do it only once
+	 */
+	if (task->thread.flags & IA64_THREAD_DBG_VALID) return 0;
+
+	/*
+	 * Even on SMP, we do not need to use an atomic here because
+	 * the only way in is via ptrace() and this is possible only when the
+	 * process is stopped. Even in the case where the ctxsw out is not totally
+	 * completed by the time we come here, there is no way the 'stopped' process
+	 * could be in the middle of fiddling with the pfm_write_ibr_dbr() routine.
+	 * So this is always safe.
+	 */
+	if (ctx && ctx->ctx_fl_using_dbreg == 1) return -1;
+
+	/*
+	 * XXX: not pretty
+	 */
+	LOCK_PFS();
+
+	/*
+	 * We only allow the use of debug registers when there is no system
+	 * wide monitoring 
+	 * XXX: we could relax this by 
+	 */
+	if (pfm_sessions.pfs_sys_use_dbregs> 0)
+		ret = -1;
+	else
+		pfm_sessions.pfs_ptrace_use_dbregs++;
+
+	DBprintk(("ptrace_use_dbregs=%lu  sys_use_dbregs=%lu by [%d] ret = %d\n", 
+		  pfm_sessions.pfs_ptrace_use_dbregs, 
+		  pfm_sessions.pfs_sys_use_dbregs, 
+		  task->pid, ret));
+
+	UNLOCK_PFS();
+
+	return ret;
+}
+
+/*
+ * This function is called for every task that exits with the
+ * IA64_THREAD_DBG_VALID set. This indicates a task which was
+ * able to use the debug registers for debugging purposes via
+ * ptrace(). Therefore we know it was not using them for
+ * perfmormance monitoring, so we only decrement the number
+ * of "ptraced" debug register users to keep the count up to date
+ */
+int
+pfm_release_debug_registers(struct task_struct *task)
+{
+	int ret;
+
+	LOCK_PFS();
+	if (pfm_sessions.pfs_ptrace_use_dbregs == 0) {
+		printk("perfmon: invalid release for [%d] ptrace_use_dbregs=0\n", task->pid);
+		ret = -1;
+	}  else {
+		pfm_sessions.pfs_ptrace_use_dbregs--;
+		ret = 0;
+	}
+	UNLOCK_PFS();
+
+	return ret;
+}
+#else /* PFM_PMU_USES_DBR is true */
+/*
+ * in case, the PMU does not use the debug registers, these two functions are nops.
+ * The first function is called from arch/ia64/kernel/ptrace.c.
+ * The second function is called from arch/ia64/kernel/process.c.
+ */
+int
+pfm_use_debug_registers(struct task_struct *task)
+{
+	return 0;
+}
+int
+pfm_release_debug_registers(struct task_struct *task)
+{
+	return 0;
+}
+#endif /* PFM_PMU_USES_DBR */
+
 static int
-pfm_do_restart(struct task_struct *task)
+pfm_restart(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
 {
-	struct thread_struct *th = &task->thread;
-	pfm_context_t *ctx = th->pfm_context;
 	void *sem = &ctx->ctx_restart_sem;
 
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+#if 0
+	if (ctx->ctx_fl_frozen==0) {
+		printk("task %d without pmu_frozen set\n", task->pid);
+		return -EINVAL;
+	}
+#endif
+
 	if (task == current) {
-		DBprintk((" restarting self %d frozen=%d \n", current->pid, ctx->ctx_fl_frozen));
+		DBprintk(("restarting self %d frozen=%d \n", current->pid, ctx->ctx_fl_frozen));
+
+		pfm_reset_regs(ctx, ctx->ctx_ovfl_regs, PFM_RELOAD_LONG_RESET);
 
-		pfm_reset_regs(ctx);
+		ctx->ctx_ovfl_regs[0] = 0UL;
 
 		/*
 		 * We ignore block/don't block because we never block
@@ -978,26 +1526,37 @@
 		ctx->ctx_fl_frozen = 0;
 
 		if (CTX_HAS_SMPL(ctx)) {
-			ctx->ctx_smpl_buf->psb_hdr->hdr_count = 0;
-			ctx->ctx_smpl_buf->psb_index = 0;
+			ctx->ctx_psb->psb_hdr->hdr_count = 0;
+			ctx->ctx_psb->psb_index = 0;
 		}
 
-		/* pfm_reset_smpl_buffers(ctx,th->pfm_ovfl_regs);*/
-
 		/* simply unfreeze */
 		ia64_set_pmc(0, 0);
 		ia64_srlz_d();
 
 		return 0;
-	}
+	} 
+	/* restart on another task */
 
-	/* check if blocking */
+	/*
+	 * if blocking, then post the semaphore.
+	 * if non-blocking, then we ensure that the task will go into
+	 * pfm_overflow_must_block() before returning to user mode. 
+	 * We cannot explicitely reset another task, it MUST always
+	 * be done by the task itself. This works for system wide because
+	 * the tool that is controlling the session is doing "self-monitoring".
+	 *
+	 * XXX: what if the task never goes back to user?
+	 *
+	 */
 	if (CTX_OVFL_NOBLOCK(ctx) == 0) {
-		DBprintk((" unblocking %d \n", task->pid));
+		DBprintk(("unblocking %d \n", task->pid));
 		up(sem);
-		return 0;
+	} else {
+		task->thread.pfm_ovfl_block_reset = 1;
+		set_tsk_thread_flag(current, TIF_NOTIFY_RESUME);
 	}
-
+#if 0
 	/*
 	 * in case of non blocking mode, then it's just a matter of
 	 * of reseting the sampling buffer (if any) index. The PMU
@@ -1008,314 +1567,735 @@
 	 * must reset the header count first
 	 */
 	if (CTX_HAS_SMPL(ctx)) {
-		DBprintk((" resetting sampling indexes for %d \n", task->pid));
-		ctx->ctx_smpl_buf->psb_hdr->hdr_count = 0;
-		ctx->ctx_smpl_buf->psb_index = 0;
+		DBprintk(("resetting sampling indexes for %d \n", task->pid));
+		ctx->ctx_psb->psb_hdr->hdr_count = 0;
+		ctx->ctx_psb->psb_index = 0;
 	}
-
+#endif
 	return 0;
 }
 
+#ifndef CONFIG_SMP
 /*
- * system-wide mode: propagate activation/desactivation throughout the tasklist
- *
- * XXX: does not work for SMP, of course
+ * On UP kernels, we do not need to constantly set the psr.pp bit
+ * when a task is scheduled. The psr.pp bit can only be changed in
+ * the kernel because of a user request. Given we are on a UP non preeemptive 
+ * kernel we know that no other task is running, so we cna simply update their
+ * psr.pp from their saved state. There is this no impact on the context switch
+ * code compared to the SMP case.
  */
 static void
-pfm_process_tasklist(int cmd)
+pfm_tasklist_toggle_pp(unsigned int val)
 {
 	struct task_struct *p;
 	struct pt_regs *regs;
 
+	DBprintk(("invoked by [%d] pp=%u\n", current->pid, val));
+
+	read_lock(&tasklist_lock);
+
 	for_each_task(p) {
-		regs = (struct pt_regs *)((unsigned long)p + IA64_STK_OFFSET);
+       		regs = (struct pt_regs *)((unsigned long) p + IA64_STK_OFFSET);
+
+		/*
+		 * position on pt_regs saved on stack on 1st entry into the kernel
+		 */
 		regs--;
-		ia64_psr(regs)->pp = cmd;
+
+		/*
+		 * update psr.pp
+		 */
+		ia64_psr(regs)->pp = val;
 	}
+	read_unlock(&tasklist_lock);
 }
+#endif
+
+
 
 static int
-do_perfmonctl (struct task_struct *task, int cmd, int flags, perfmon_req_t *req, int count, struct pt_regs *regs)
+pfm_stop(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
 {
-	perfmon_req_t tmp;
-	struct thread_struct *th = &task->thread;
-	pfm_context_t *ctx = th->pfm_context;
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-	memset(&tmp, 0, sizeof(tmp));
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
-	if (ctx == NULL && cmd != PFM_CREATE_CONTEXT && cmd < PFM_DEBUG_BASE) {
-		DBprintk((" PFM_WRITE_PMCS: no context for task %d\n", task->pid));
-		return -EINVAL;
+	DBprintk(("[%d] fl_system=%d owner=%p current=%p\n",
+				current->pid,
+				ctx->ctx_fl_system, PMU_OWNER(),
+				current));
+	/* simply stop monitoring but not the PMU */
+	if (ctx->ctx_fl_system) {
+
+		__asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
+
+		/* disable dcr pp */
+		ia64_set_dcr(ia64_get_dcr() & ~IA64_DCR_PP);
+
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_dcr_pp  = 0;
+#else
+		pfm_tasklist_toggle_pp(0);
+#endif
+
+		ia64_psr(regs)->pp = 0;
+
+	} else {
+		__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+
+		ia64_psr(regs)->up = 0;
 	}
+	return 0;
+}
 
-	switch (cmd) {
-		case PFM_CREATE_CONTEXT:
-			/* a context has already been defined */
-			if (ctx) return -EBUSY;
+static int
+pfm_disable(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	   struct pt_regs *regs)
+{	
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-			/*
-			 * cannot directly create a context in another process
-			 */
-			if (task != current) return -EINVAL;
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+	/*
+	 * stop monitoring, freeze PMU, and save state in context
+	 * this call will clear IA64_THREAD_PM_VALID for per-task sessions.
+	 */
+	pfm_flush_regs(task);
+
+	if (ctx->ctx_fl_system) {	
+		ia64_psr(regs)->pp = 0;
+	} else {
+		ia64_psr(regs)->up = 0;
+	}
+	/* 
+	 * goes back to default behavior 
+	 * no need to change live psr.sp because useless at the kernel level
+	 */
+	ia64_psr(regs)->sp = 1;
+
+	DBprintk(("enabling psr.sp for [%d]\n", current->pid));
+
+	ctx->ctx_flags.state = PFM_CTX_DISABLED;
+
+	return 0;
+}
+
+
+
+static int
+pfm_destroy_context(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	/*
+	 * if context was never enabled, then there is not much
+	 * to do
+	 */
+	if (!CTX_IS_ENABLED(ctx)) goto skipped_stop;
+
+	/*
+	 * Disable context: stop monitoring, flush regs to software state (useless here), 
+	 * and freeze PMU
+	 * 
+	 * The IA64_THREAD_PM_VALID is cleared by pfm_flush_regs() called from pfm_disable()
+	 */
+	pfm_disable(task, ctx, arg, count, regs);
+
+	if (ctx->ctx_fl_system) {	
+		ia64_psr(regs)->pp = 0;
+	} else {
+		ia64_psr(regs)->up = 0;
+	}
+
+	/* restore security level */
+	ia64_psr(regs)->sp = 1;
+
+skipped_stop:
+	/*
+	 * remove sampling buffer mapping, if any
+	 */
+	if (ctx->ctx_smpl_vaddr) pfm_remove_smpl_mapping(task);
 
-			if (req == NULL || count != 1) return -EINVAL;
+	/* now free context and related state */
+	pfm_context_exit(task);
 
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
+	return 0;
+}
+
+/*
+ * does nothing at the moment
+ */
+static int
+pfm_unprotect_context(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	return 0;
+}
+
+static int
+pfm_protect_context(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	DBprintk(("context from [%d] is protected\n", task->pid));
+	/*
+	 * from now on, only the creator of the context has access to it
+	 */
+	ctx->ctx_fl_protected = 1;
+
+	/*
+	 * reinforce secure monitoring: cannot toggle psr.up
+	 */
+	ia64_psr(regs)->sp = 1;
+
+	return 0;
+}
+
+static int
+pfm_debug(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{
+	unsigned int mode = *(unsigned int *)arg;
 
-			return pfm_context_create(flags, req);
+	pfm_debug_mode = mode == 0 ? 0 : 1;
 
-		case PFM_WRITE_PMCS:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+	printk("perfmon debugging %s\n", pfm_debug_mode ? "on" : "off");
 
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
+	return 0;
+}
 
-			return pfm_write_pmcs(task, req, count);
+#ifdef PFM_PMU_USES_DBR
 
-		case PFM_WRITE_PMDS:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+typedef struct {
+	unsigned long ibr_mask:56;
+	unsigned long ibr_plm:4;
+	unsigned long ibr_ig:3;
+	unsigned long ibr_x:1;
+} ibr_mask_reg_t;
 
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
+typedef struct {
+	unsigned long dbr_mask:56;
+	unsigned long dbr_plm:4;
+	unsigned long dbr_ig:2;
+	unsigned long dbr_w:1;
+	unsigned long dbr_r:1;
+} dbr_mask_reg_t;
+
+typedef union {
+	unsigned long  val;
+	ibr_mask_reg_t ibr;
+	dbr_mask_reg_t dbr;
+} dbreg_t;
 
-			return pfm_write_pmds(task, req, count);
 
-		case PFM_START:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+static int
+pfm_write_ibr_dbr(int mode, struct task_struct *task, void *arg, int count, struct pt_regs *regs)
+{
+	struct thread_struct *thread = &task->thread;
+	pfm_context_t *ctx = task->thread.pfm_context;
+	pfarg_dbreg_t tmp, *req = (pfarg_dbreg_t *)arg;
+	dbreg_t dbreg;
+	unsigned int rnum;
+	int first_time;
+	int i, ret = 0;
 
-			if (PMU_OWNER()  && PMU_OWNER() != current && PFM_CAN_DO_LAZY()) pfm_lazy_save_regs(PMU_OWNER());
+	/*
+	 * for range restriction: psr.db must be cleared or the
+	 * the PMU will ignore the debug registers.
+	 *
+	 * XXX: may need more in system wide mode,
+	 * no task can have this bit set?
+	 */
+	if (ia64_psr(regs)->db == 1) return -EINVAL;
+
+
+	first_time = ctx->ctx_fl_using_dbreg == 0;
 
-			SET_PMU_OWNER(current);
+	/*
+	 * check for debug registers in system wide mode
+	 *
+	 */
+	LOCK_PFS();
+	if (ctx->ctx_fl_system && first_time) {
+		if (pfm_sessions.pfs_ptrace_use_dbregs) 
+			ret = -EBUSY;
+		else
+			pfm_sessions.pfs_sys_use_dbregs++;
+	}
+	UNLOCK_PFS();
 
-			/* will start monitoring right after rfi */
-			ia64_psr(regs)->up = 1;
-			ia64_psr(regs)->pp = 1;
+	if (ret != 0) return ret;
 
-			if (ctx->ctx_fl_system) {
-				pfm_process_tasklist(1);
-				pfs_info.pfs_pp = 1;
+	if (ctx->ctx_fl_system) {
+		/* we mark ourselves as owner  of the debug registers */
+		ctx->ctx_fl_using_dbreg = 1;
+	} else {
+       		if (ctx->ctx_fl_using_dbreg == 0) {
+			ret= -EBUSY;
+			if ((thread->flags & IA64_THREAD_DBG_VALID) != 0) {
+				DBprintk(("debug registers already in use for [%d]\n", task->pid));
+				goto abort_mission;
 			}
+			/* we mark ourselves as owner  of the debug registers */
+			ctx->ctx_fl_using_dbreg = 1;
+
+			/* 
+			 * Given debug registers cannot be used for both debugging 
+			 * and performance monitoring at the same time, we reuse
+			 * the storage area to save and restore the registers on ctxsw.
+			 */
+			memset(task->thread.dbr, 0, sizeof(task->thread.dbr));
+			memset(task->thread.ibr, 0, sizeof(task->thread.ibr));
 
 			/*
-			 * mark the state as valid.
-			 * this will trigger save/restore at context switch
+			 * clear hardware registers to make sure we don't leak
+			 * information and pick up stale state
 			 */
-			if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
+			for (i=0; i < pmu_conf.num_ibrs; i++) {
+				ia64_set_ibr(i, 0UL);
+			}
+			for (i=0; i < pmu_conf.num_dbrs; i++) {
+				ia64_set_dbr(i, 0UL);
+			}
+		}
+	}
 
-			ia64_set_pmc(0, 0);
-			ia64_srlz_d();
+	ret = -EFAULT;
 
-			break;
+	/*
+	 * Now install the values into the registers
+	 */
+	for (i = 0; i < count; i++, req++) {
 
-		case PFM_ENABLE:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+		
+		if (copy_from_user(&tmp, req, sizeof(tmp))) goto abort_mission;
+		
+		rnum      = tmp.dbreg_num;
+		dbreg.val = tmp.dbreg_value;
+		
+		ret = -EINVAL;
 
-			if (PMU_OWNER()  && PMU_OWNER() != current && PFM_CAN_DO_LAZY()) pfm_lazy_save_regs(PMU_OWNER());
+		if ((mode == 0 && !IBR_IS_IMPL(rnum)) || ((mode == 1) && !DBR_IS_IMPL(rnum))) {
+			DBprintk(("invalid register %u val=0x%lx mode=%d i=%d count=%d\n", 
+				  rnum, dbreg.val, mode, i, count));
 
-			/* reset all registers to stable quiet state */
-			ia64_reset_pmu();
+			goto abort_mission;
+		}
 
-			/* make sure nothing starts */
-			ia64_psr(regs)->up = 0;
-			ia64_psr(regs)->pp = 0;
+		/*
+		 * make sure we do not install enabled breakpoint
+		 */
+		if (rnum & 0x1) {
+			if (mode == 0) 
+				dbreg.ibr.ibr_x = 0;
+			else
+				dbreg.dbr.dbr_r = dbreg.dbr.dbr_w = 0;
+		}
 
-			/* do it on the live register as well */
-			__asm__ __volatile__ ("rsm psr.pp|psr.pp;;"::: "memory");
+		/*
+		 * clear return flags and copy back to user
+		 *
+		 * XXX: fix once EAGAIN is implemented
+		 */
+		ret = -EFAULT;
 
-			SET_PMU_OWNER(current);
+		PFM_REG_RETFLAG_SET(tmp.dbreg_flags, 0);
 
-			/*
-			 * mark the state as valid.
-			 * this will trigger save/restore at context switch
-			 */
-			if (ctx->ctx_fl_system==0) th->flags |= IA64_THREAD_PM_VALID;
+		if (copy_to_user(req, &tmp, sizeof(tmp))) goto abort_mission;
 
-			/* simply unfreeze */
-			ia64_set_pmc(0, 0);
-			ia64_srlz_d();
-			break;
+		/*
+		 * Debug registers, just like PMC, can only be modified
+		 * by a kernel call. Moreover, perfmon() access to those
+		 * registers are centralized in this routine. The hardware
+		 * does not modify the value of these registers, therefore,
+		 * if we save them as they are written, we can avoid having
+		 * to save them on context switch out. This is made possible
+		 * by the fact that when perfmon uses debug registers, ptrace()
+		 * won't be able to modify them concurrently.
+		 */
+		if (mode == 0) {
+			CTX_USED_IBR(ctx, rnum);
 
-		case PFM_DISABLE:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
+			ia64_set_ibr(rnum, dbreg.val);
 
-			/* simply freeze */
-			ia64_set_pmc(0, 1);
-			ia64_srlz_d();
-			/*
-			 * XXX: cannot really toggle IA64_THREAD_PM_VALID
-			 * but context is still considered valid, so any 
-			 * read request would return something valid. Same
-			 * thing when this task terminates (pfm_flush_regs()).
-			 */
-			break;
+			thread->ibr[rnum] = dbreg.val;
 
-		case PFM_READ_PMDS:
-			if (!access_ok(VERIFY_READ, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
-			if (!access_ok(VERIFY_WRITE, req, sizeof(struct perfmon_req_t)*count)) return -EFAULT;
-
-			return pfm_read_pmds(task, req, count);
-
-	      case PFM_STOP:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
-
-			/* simply stop monitors, not PMU */
-			ia64_psr(regs)->up = 0;
-			ia64_psr(regs)->pp = 0;
-
-			if (ctx->ctx_fl_system) {
-				pfm_process_tasklist(0);
-				pfs_info.pfs_pp = 0;
-			}
+			DBprintk(("write ibr%u=0x%lx used_ibrs=0x%lx\n", rnum, dbreg.val, ctx->ctx_used_ibrs[0]));
+		} else {
+			CTX_USED_DBR(ctx, rnum);
 
-			break;
+			ia64_set_dbr(rnum, dbreg.val);
 
-	      case PFM_RESTART: /* temporary, will most likely end up as a PFM_ENABLE */
+			thread->dbr[rnum] = dbreg.val;
 
-			if ((th->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system==0) {
-				printk(" PFM_RESTART not monitoring\n");
-				return -EINVAL;
-			}
-			if (CTX_OVFL_NOBLOCK(ctx) == 0 && ctx->ctx_fl_frozen==0) {
-				printk("task %d without pmu_frozen set\n", task->pid);
-				return -EINVAL;
-			}
+			DBprintk(("write dbr%u=0x%lx used_dbrs=0x%lx\n", rnum, dbreg.val, ctx->ctx_used_dbrs[0]));
+		}
+	}
 
-			return pfm_do_restart(task); /* we only look at first entry */
+	return 0;
 
-	      case PFM_DESTROY_CONTEXT:
-			/* we don't quite support this right now */
-			if (task != current) return -EINVAL;
-
-			/* first stop monitors */
-			ia64_psr(regs)->up = 0;
-			ia64_psr(regs)->pp = 0;
+abort_mission:
+	/*
+	 * in case it was our first attempt, we undo the global modifications
+	 */
+	if (first_time) {
+		LOCK_PFS();
+		if (ctx->ctx_fl_system) {
+			pfm_sessions.pfs_sys_use_dbregs--;
+		}
+		UNLOCK_PFS();
+		ctx->ctx_fl_using_dbreg = 0;
+	}
+	/*
+	 * install error return flag
+	 */
+	if (ret != -EFAULT) {
+		/*
+		 * XXX: for now we can only come here on EINVAL
+		 */
+		PFM_REG_RETFLAG_SET(tmp.dbreg_flags, PFM_REG_RETFL_EINVAL);
+		copy_to_user(req, &tmp, sizeof(tmp));
+	}
+	return ret;
+}
 
-			/* then freeze PMU */
-			ia64_set_pmc(0, 1);
-			ia64_srlz_d();
+static int
+pfm_write_ibrs(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{	
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-			/* don't save/restore on context switch */
-			if (ctx->ctx_fl_system ==0) task->thread.flags &= ~IA64_THREAD_PM_VALID;
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
-			SET_PMU_OWNER(NULL);
+	return pfm_write_ibr_dbr(0, task, arg, count, regs);
+}
 
-			/* now free context and related state */
-			pfm_context_exit(task);
-			break;
+static int
+pfm_write_dbrs(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	 struct pt_regs *regs)
+{	
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
 
-	      case PFM_DEBUG_ON:
-			printk("perfmon debugging on\n");
-			pfm_debug = 1;
-			break;
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
 
-	      case PFM_DEBUG_OFF:
-			printk("perfmon debugging off\n");
-			pfm_debug = 0;
-			break;
+	return pfm_write_ibr_dbr(1, task, arg, count, regs);
+}
+
+#endif /* PFM_PMU_USES_DBR */
+
+static int
+pfm_get_features(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
+{
+	pfarg_features_t tmp;
+
+	memset(&tmp, 0, sizeof(tmp));
+
+	tmp.ft_version      = PFM_VERSION;
+	tmp.ft_smpl_version = PFM_SMPL_VERSION;
+
+	if (copy_to_user(arg, &tmp, sizeof(tmp))) return -EFAULT;
+
+	return 0;
+}
+
+static int
+pfm_start(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	  struct pt_regs *regs)
+{
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	/* 
+	 * Cannot do anything before PMU is enabled 
+	 */
+	if (!CTX_IS_ENABLED(ctx)) return -EINVAL;
+
+	DBprintk(("[%d] fl_system=%d owner=%p current=%p\n",
+				current->pid,
+				ctx->ctx_fl_system, PMU_OWNER(),
+				current));
+
+	if (PMU_OWNER() != task) {
+		printk("perfmon: pfm_start task [%d] not pmu owner\n", task->pid);
+		return -EINVAL;
+	}
+
+	if (ctx->ctx_fl_system) {
+		
+		/* enable dcr pp */
+		ia64_set_dcr(ia64_get_dcr()|IA64_DCR_PP);
 
-	      default:
-			DBprintk((" UNknown command 0x%x\n", cmd));
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_dcr_pp  = 1;
+#else
+		pfm_tasklist_toggle_pp(1);
+#endif
+		ia64_psr(regs)->pp = 1;
+
+		__asm__ __volatile__ ("ssm psr.pp;;"::: "memory");
+
+	} else {
+		if ((task->thread.flags & IA64_THREAD_PM_VALID) == 0) {
+			printk("perfmon: pfm_start task flag not set for [%d]\n", task->pid);
 			return -EINVAL;
+		}
+		ia64_psr(regs)->up = 1;
+		__asm__ __volatile__ ("sum psr.up;;"::: "memory");
 	}
+	ia64_srlz_d();
+
+	return 0;
+}
+
+static int
+pfm_enable(struct task_struct *task, pfm_context_t *ctx, void *arg, int count, 
+	   struct pt_regs *regs)
+{
+	/* we don't quite support this right now */
+	if (task != current) return -EINVAL;
+
+	if (ctx->ctx_fl_system == 0 && PMU_OWNER()  && PMU_OWNER() != current) 
+		pfm_lazy_save_regs(PMU_OWNER());
+
+	/* reset all registers to stable quiet state */
+	ia64_reset_pmu(task);
+
+	/* make sure nothing starts */
+	if (ctx->ctx_fl_system) {
+		ia64_psr(regs)->pp = 0;
+		ia64_psr(regs)->up = 0; /* just to make sure! */
+
+		__asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
+
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_syst_wide = 1;
+		local_cpu_data->pfm_dcr_pp    = 0;
+#endif
+	} else {
+		/*
+		 * needed in case the task was a passive task during
+		 * a system wide session and now wants to have its own
+		 * session
+		 */
+		ia64_psr(regs)->pp = 0; /* just to make sure! */
+		ia64_psr(regs)->up = 0;
+
+		__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+		/*
+		 * allow user control (user monitors only)
+		if (task  == ctx->ctx_owner) {
+		 */
+		{
+			DBprintk(("clearing psr.sp for [%d]\n", current->pid));
+			ia64_psr(regs)->sp = 0;
+		}
+		task->thread.flags |= IA64_THREAD_PM_VALID;
+	}
+
+	SET_PMU_OWNER(task);
+
+
+	ctx->ctx_flags.state = PFM_CTX_ENABLED;
+	atomic_set(&ctx->ctx_last_cpu, smp_processor_id());
+
+	/* simply unfreeze */
+	ia64_set_pmc(0, 0);
+	ia64_srlz_d();
+
 	return 0;
 }
 
 /*
- * XXX: do something better here
+ * functions MUST be listed in the increasing order of their index (see permfon.h)
  */
+static pfm_cmd_desc_t pfm_cmd_tab[]={
+/* 0  */{ NULL, 0, 0, 0}, /* not used */
+/* 1  */{ pfm_write_pmcs, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_reg_t)}, 
+/* 2  */{ pfm_write_pmds, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ, PFM_CMD_ARG_MANY, sizeof(pfarg_reg_t)},
+/* 3  */{ pfm_read_pmds, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_reg_t)},
+/* 4  */{ pfm_stop, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 5  */{ pfm_start, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 6  */{ pfm_enable, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 7  */{ pfm_disable, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 8  */{ pfm_create_context, PFM_CMD_ARG_READ, 1, sizeof(pfarg_context_t)},
+/* 9  */{ pfm_destroy_context, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 10 */{ pfm_restart, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_NOCHK, 0, 0},
+/* 11 */{ pfm_protect_context, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 12 */{ pfm_get_features, PFM_CMD_ARG_WRITE, 0, 0},
+/* 13 */{ pfm_debug, 0, 1, sizeof(unsigned int)},
+/* 14 */{ pfm_unprotect_context, PFM_CMD_PID|PFM_CMD_CTX, 0, 0},
+/* 15 */{ NULL, 0, 0, 0}, /* not used */
+/* 16 */{ NULL, 0, 0, 0}, /* not used */
+/* 17 */{ NULL, 0, 0, 0}, /* not used */
+/* 18 */{ NULL, 0, 0, 0}, /* not used */
+/* 19 */{ NULL, 0, 0, 0}, /* not used */
+/* 20 */{ NULL, 0, 0, 0}, /* not used */
+/* 21 */{ NULL, 0, 0, 0}, /* not used */
+/* 22 */{ NULL, 0, 0, 0}, /* not used */
+/* 23 */{ NULL, 0, 0, 0}, /* not used */
+/* 24 */{ NULL, 0, 0, 0}, /* not used */
+/* 25 */{ NULL, 0, 0, 0}, /* not used */
+/* 26 */{ NULL, 0, 0, 0}, /* not used */
+/* 27 */{ NULL, 0, 0, 0}, /* not used */
+/* 28 */{ NULL, 0, 0, 0}, /* not used */
+/* 29 */{ NULL, 0, 0, 0}, /* not used */
+/* 30 */{ NULL, 0, 0, 0}, /* not used */
+/* 31 */{ NULL, 0, 0, 0}, /* not used */
+#ifdef PFM_PMU_USES_DBR
+/* 32 */{ pfm_write_ibrs, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_dbreg_t)},
+/* 33 */{ pfm_write_dbrs, PFM_CMD_PID|PFM_CMD_CTX|PFM_CMD_ARG_READ|PFM_CMD_ARG_WRITE, PFM_CMD_ARG_MANY, sizeof(pfarg_dbreg_t)}
+#endif
+};
+#define PFM_CMD_COUNT	(sizeof(pfm_cmd_tab)/sizeof(pfm_cmd_desc_t))
+
 static int
-perfmon_bad_permissions(struct task_struct *task)
+check_task_state(struct task_struct *task)
 {
-	/* stolen from bad_signal() */
-	return (current->session != task->session)
-	    && (current->euid ^ task->suid) && (current->euid ^ task->uid)
-	    && (current->uid ^ task->suid) && (current->uid ^ task->uid);
+	int ret = 0;
+#ifdef CONFIG_SMP
+	/* We must wait until the state has been completely
+	 * saved. There can be situations where the reader arrives before
+	 * after the task is marked as STOPPED but before pfm_save_regs()
+	 * is completed.
+	 */
+	for (;;) {
+
+		task_lock(task);
+		if (1 /*XXX !task_has_cpu(task)*/) break;
+		task_unlock(task);
+
+		do {
+			if (task->state != TASK_ZOMBIE && task->state != TASK_STOPPED) return -EBUSY;
+			barrier();
+			cpu_relax();
+		} while (0 /*task_has_cpu(task)*/);
+	}
+	task_unlock(task);
+#else
+	if (task->state != TASK_ZOMBIE && task->state != TASK_STOPPED) {
+		DBprintk(("warning [%d] not in stable state %ld\n", task->pid, task->state));
+		ret = -EBUSY;
+	}
+#endif
+	return ret;
 }
 
 asmlinkage int
-sys_perfmonctl (int pid, int cmd, int flags, perfmon_req_t *req, int count, long arg6, long arg7, long arg8, long stack)
+sys_perfmonctl (pid_t pid, int cmd, void *arg, int count, long arg5, long arg6, long arg7, 
+		long arg8, long stack)
 {
-	struct pt_regs *regs = (struct pt_regs *) &stack;
-	struct task_struct *child = current;
-	int ret = -ESRCH;
+	struct pt_regs *regs = (struct pt_regs *)&stack;
+	struct task_struct *task = current;
+	pfm_context_t *ctx = task->thread.pfm_context;
+	size_t sz;
+	int ret = -ESRCH, narg;
 
-	/* sanity check:
-	 *
-	 * ensures that we don't do bad things in case the OS
-	 * does not have enough storage to save/restore PMC/PMD
+	/* 
+	 * reject any call if perfmon was disabled at initialization time
 	 */
-	if (PERFMON_IS_DISABLED()) return -ENOSYS;
+	if (PFM_IS_DISABLED()) return -ENOSYS;
 
-	/* XXX: pid interface is going away in favor of pfm context */
-	if (pid != current->pid) {
-		read_lock(&tasklist_lock);
+	DBprintk(("cmd=%d idx=%d valid=%d narg=0x%x\n", cmd, PFM_CMD_IDX(cmd), 
+		  PFM_CMD_IS_VALID(cmd), PFM_CMD_NARG(cmd)));
 
-		child = find_task_by_pid(pid);
+	if (PFM_CMD_IS_VALID(cmd) == 0) return -EINVAL;
 
-		if (!child) goto abort_call;
+	/* ingore arguments when command has none */
+	narg = PFM_CMD_NARG(cmd);
+	if ((narg == PFM_CMD_ARG_MANY  && count == 0) || (narg > 0 && narg != count)) return -EINVAL;
 
-		ret = -EPERM;
+	sz = PFM_CMD_ARG_SIZE(cmd);
 
-		if (perfmon_bad_permissions(child)) goto abort_call;
+	if (PFM_CMD_READ_ARG(cmd) && !access_ok(VERIFY_READ, arg, sz*count)) return -EFAULT;
 
-		/*
-		 * XXX: need to do more checking here
+	if (PFM_CMD_WRITE_ARG(cmd) && !access_ok(VERIFY_WRITE, arg, sz*count)) return -EFAULT;
+
+	if (PFM_CMD_USE_PID(cmd))  {
+		/* 
+		 * XXX: may need to fine tune this one
 		 */
-		if (child->state != TASK_ZOMBIE && child->state != TASK_STOPPED) {
-			DBprintk((" warning process %d not in stable state %ld\n", pid, child->state));
+		if (pid < 2) return -EPERM;
+
+		if (pid != current->pid) {
+
+			read_lock(&tasklist_lock);
+
+			task = find_task_by_pid(pid);
+
+			if (!task) goto abort_call;
+
+			ret = -EPERM;
+
+			if (pfm_bad_permissions(task)) goto abort_call;
+
+			if (PFM_CMD_CHK(cmd)) {
+				ret = check_task_state(task);
+				if (ret != 0) goto abort_call;
+			}
+			ctx = task->thread.pfm_context;
 		}
+	} 
+
+	if (PFM_CMD_USE_CTX(cmd)) {
+		ret = -EINVAL;
+	       if (ctx == NULL) {
+			DBprintk(("no context for task %d\n", task->pid));
+			goto abort_call;
+	       }
+	       ret = -EPERM;
+	       /*
+		* we only grant access to the context if:
+		* 	- the caller is the creator of the context (ctx_owner)
+		*  OR   - the context is attached to the caller AND The context IS NOT 
+		*  	  in protected mode
+		*/
+	       if (ctx->ctx_owner != current && (ctx->ctx_fl_protected || task != current)) {
+				DBprintk(("context protected, no access for [%d]\n", task->pid));
+				goto abort_call;
+	       }
 	}
-	ret = do_perfmonctl(child, cmd, flags, req, count, regs);
+
+	ret = (*pfm_cmd_tab[PFM_CMD_IDX(cmd)].cmd_func)(task, ctx, arg, count, regs);
 
 abort_call:
-	if (child != current) read_unlock(&tasklist_lock);
+	if (task != current) read_unlock(&tasklist_lock);
 
 	return ret;
 }
 
-#if __GNUC__ >= 3
-void asmlinkage
-pfm_block_on_overflow(void)
-#else
-void asmlinkage
-pfm_block_on_overflow(u64 arg0, u64 arg1, u64 arg2, u64 arg3, u64 arg4, u64 arg5, u64 arg6, u64 arg7)
-#endif
+void
+pfm_ovfl_block_reset (void)
 {
 	struct thread_struct *th = &current->thread;
 	pfm_context_t *ctx = current->thread.pfm_context;
 	int ret;
 
 	/*
-	 * NO matter what notify_pid is,
-	 * we clear overflow, won't notify again
+	 * clear the flag, to make sure we won't get here
+	 * again
 	 */
-	th->pfm_must_block = 0;
+	th->pfm_ovfl_block_reset = 0;
 
 	/*
 	 * do some sanity checks first
 	 */
 	if (!ctx) {
-		printk("perfmon: process %d has no PFM context\n", current->pid);
+		printk("perfmon: [%d] has no PFM context\n", current->pid);
 		return;
 	}
-	if (ctx->ctx_notify_task == 0) {
-		printk("perfmon: process %d has no task to notify\n", current->pid);
-		return;
-	}
-
-	DBprintk((" current=%d task=%d\n", current->pid, ctx->ctx_notify_task->pid));
 
-	/* should not happen */
-	if (CTX_OVFL_NOBLOCK(ctx)) {
-		printk("perfmon: process %d non-blocking ctx should not be here\n", current->pid);
-		return;
-	}
+	if (CTX_OVFL_NOBLOCK(ctx)) goto non_blocking;
 
-	DBprintk((" CPU%d %d before sleep\n", smp_processor_id(), current->pid));
+	DBprintk(("[%d] before sleeping\n", current->pid));
 
 	/*
 	 * may go through without blocking on SMP systems
@@ -1323,12 +2303,14 @@
 	 */
 	ret = down_interruptible(&ctx->ctx_restart_sem);
 
-	DBprintk((" CPU%d %d after sleep ret=%d\n", smp_processor_id(), current->pid, ret));
+	DBprintk(("[%d] after sleeping ret=%d\n", current->pid, ret));
 
 	/*
 	 * in case of interruption of down() we don't restart anything
 	 */
 	if (ret >= 0) {
+
+non_blocking:
 		/* we reactivate on context switch */
 		ctx->ctx_fl_frozen = 0;
 		/*
@@ -1336,19 +2318,19 @@
 		 * use the local reference
 		 */
 
-		pfm_reset_regs(ctx);
+		pfm_reset_regs(ctx, ctx->ctx_ovfl_regs, PFM_RELOAD_LONG_RESET);
+
+		ctx->ctx_ovfl_regs[0] = 0UL;
 
 		/*
 		 * Unlock sampling buffer and reset index atomically
 		 * XXX: not really needed when blocking
 		 */
 		if (CTX_HAS_SMPL(ctx)) {
-			ctx->ctx_smpl_buf->psb_hdr->hdr_count = 0;
-			ctx->ctx_smpl_buf->psb_index = 0;
+			ctx->ctx_psb->psb_hdr->hdr_count = 0;
+			ctx->ctx_psb->psb_index = 0;
 		}
 
-		DBprintk((" CPU%d %d unfreeze PMU\n", smp_processor_id(), current->pid));
-
 		ia64_set_pmc(0, 0);
 		ia64_srlz_d();
 
@@ -1357,23 +2339,111 @@
 }
 
 /*
+ * This function will record an entry in the sampling if it is not full already.
+ * Return:
+ * 	0 : buffer is not full (did not BECOME full: still space or was already full)
+ * 	1 : buffer is full (recorded the last entry)
+ */
+static int
+pfm_record_sample(struct task_struct *task, pfm_context_t *ctx, unsigned long ovfl_mask, struct pt_regs *regs)
+{
+	pfm_smpl_buffer_desc_t *psb = ctx->ctx_psb;
+	unsigned long *e, m, idx;
+	perfmon_smpl_entry_t *h;
+	int j;
+
+
+pfm_recorded_samples_count++;
+	idx = ia64_fetch_and_add(1, &psb->psb_index);
+	DBprintk(("recording index=%ld entries=%ld\n", idx-1, psb->psb_entries));
+
+	/*
+	* XXX: there is a small chance that we could run out on index before resetting
+	* but index is unsigned long, so it will take some time.....
+	* We use > instead of == because fetch_and_add() is off by one (see below)
+	*
+	* This case can happen in non-blocking mode or with multiple processes.
+	* For non-blocking, we need to reload and continue.
+	 */
+	if (idx > psb->psb_entries) return 0;
+
+	/* first entry is really entry 0, not 1 caused by fetch_and_add */
+	idx--;
+
+	h = (perfmon_smpl_entry_t *)(((char *)psb->psb_addr) + idx*(psb->psb_entry_size));
+
+	/*
+	 * initialize entry header
+	 */
+	h->pid  = task->pid;
+	h->cpu  = smp_processor_id();
+	h->rate = 0; /* XXX: add the sampling rate used here */
+	h->ip   = regs ? regs->cr_iip : 0x0;	/* where did the fault happened */
+	h->regs = ovfl_mask; 			/* which registers overflowed */
+
+	/* guaranteed to monotonically increase on each cpu */
+	h->stamp  = pfm_get_stamp();
+	h->period = 0UL; /* not yet used */
+
+	/* position for first pmd */
+	e = (unsigned long *)(h+1);
+
+	/*
+	 * selectively store PMDs in increasing index number
+	 */
+	m = ctx->ctx_smpl_regs[0];
+	for (j=0; m; m >>=1, j++) {
+
+		if ((m & 0x1) == 0) continue;
+
+		if (PMD_IS_COUNTING(j)) {
+			*e  =  pfm_read_soft_counter(ctx, j);
+			/* check if this pmd overflowed as well */
+			*e +=  ovfl_mask & (1UL<<j) ? 1 + pmu_conf.perf_ovfl_val : 0;
+		} else {
+			*e = ia64_get_pmd(j); /* slow */
+		}
+		DBprintk(("e=%p pmd%d =0x%lx\n", (void *)e, j, *e));
+		e++;
+	}
+	/*
+	 * make the new entry visible to user, needs to be atomic
+	 */
+	ia64_fetch_and_add(1, &psb->psb_hdr->hdr_count);
+
+	DBprintk(("index=%ld entries=%ld hdr_count=%ld\n", 
+				idx, psb->psb_entries, psb->psb_hdr->hdr_count));
+	/* 
+	 * sampling buffer full ? 
+	 */
+	if (idx == (psb->psb_entries-1)) {
+		DBprintk(("sampling buffer full\n"));
+		/*
+		 * XXX: must reset buffer in blocking mode and lost notified
+		 */
+		return 1;
+	}
+	return 0;
+}
+
+/*
  * main overflow processing routine.
  * it can be called from the interrupt path or explicitely during the context switch code
  * Return:
  *	new value of pmc[0]. if 0x0 then unfreeze, else keep frozen
  */
-unsigned long
-update_counters (struct task_struct *task, u64 pmc0, struct pt_regs *regs)
+static unsigned long
+pfm_overflow_handler(struct task_struct *task, u64 pmc0, struct pt_regs *regs)
 {
-	unsigned long mask, i, cnum;
-	struct thread_struct *th;
+	unsigned long mask;
+	struct thread_struct *t;
 	pfm_context_t *ctx;
-	unsigned long bv = 0;
+	unsigned long old_val;
+	unsigned long ovfl_notify = 0UL, ovfl_pmds = 0UL;
+	int i;
 	int my_cpu = smp_processor_id();
-	int ret = 1, buffer_is_full = 0;
-	int ovfl_has_long_recovery, can_notify, need_reset_pmd16=0;
+	int ret = 1;
 	struct siginfo si;
-
 	/*
 	 * It is never safe to access the task for which the overflow interrupt is destinated
 	 * using the current variable as the interrupt may occur in the middle of a context switch
@@ -1388,233 +2458,151 @@
 	 */
 
 	if (task == NULL) {
-		DBprintk((" owners[%d]=NULL\n", my_cpu));
+		DBprintk(("owners[%d]=NULL\n", my_cpu));
 		return 0x1;
 	}
-	th  = &task->thread;
-	ctx = th->pfm_context;
+	t   = &task->thread;
+	ctx = task->thread.pfm_context;
+
+	if (!ctx) {
+		printk("perfmon: Spurious overflow interrupt: process %d has no PFM context\n", 
+			task->pid);
+		return 0;
+	}
 
 	/*
 	 * XXX: debug test
 	 * Don't think this could happen given upfront tests
 	 */
-	if ((th->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system == 0) {
-		printk("perfmon: Spurious overflow interrupt: process %d not using perfmon\n", task->pid);
+	if ((t->flags & IA64_THREAD_PM_VALID) == 0 && ctx->ctx_fl_system == 0) {
+		printk("perfmon: Spurious overflow interrupt: process %d not using perfmon\n", 
+			task->pid);
 		return 0x1;
 	}
-	if (!ctx) {
-		printk("perfmon: Spurious overflow interrupt: process %d has no PFM context\n", task->pid);
-		return 0;
-	}
-
 	/*
 	 * sanity test. Should never happen
 	 */
-	if ((pmc0 & 0x1 )== 0) {
-		printk("perfmon: pid %d pmc0=0x%lx assumption error for freeze bit\n", task->pid, pmc0);
+	if ((pmc0 & 0x1) == 0) {
+		printk("perfmon: pid %d pmc0=0x%lx assumption error for freeze bit\n", 
+			task->pid, pmc0);
 		return 0x0;
 	}
 
 	mask = pmc0 >> PMU_FIRST_COUNTER;
 
-	DBprintk(("pmc0=0x%lx pid=%d owner=%d iip=0x%lx, ctx is in %s mode used_pmds=0x%lx used_pmcs=0x%lx\n", 
-				pmc0, task->pid, PMU_OWNER()->pid, regs->cr_iip, 
-				CTX_OVFL_NOBLOCK(ctx) ? "NO-BLOCK" : "BLOCK",
-				ctx->ctx_used_pmds[0],
-				ctx->ctx_used_pmcs[0]));
+	DBprintk(("pmc0=0x%lx pid=%d iip=0x%lx, %s"
+		  " mode used_pmds=0x%lx save_pmcs=0x%lx reload_pmcs=0x%lx\n", 
+			pmc0, task->pid, (regs ? regs->cr_iip : 0), 
+			CTX_OVFL_NOBLOCK(ctx) ? "nonblocking" : "blocking",
+			ctx->ctx_used_pmds[0],
+			ctx->ctx_saved_pmcs[0],
+			ctx->ctx_reload_pmcs[0]));
 
 	/*
-	 * XXX: need to record sample only when an EAR/BTB has overflowed
+	 * First we update the virtual counters
 	 */
-	if (CTX_HAS_SMPL(ctx)) {
-		pfm_smpl_buffer_desc_t *psb = ctx->ctx_smpl_buf;
-		unsigned long *e, m, idx=0;
-		perfmon_smpl_entry_t *h;
-		int j;
-
-		idx = ia64_fetch_and_add(1, &psb->psb_index);
-		DBprintk((" recording index=%ld entries=%ld\n", idx, psb->psb_entries));
+	for (i = PMU_FIRST_COUNTER; mask ; i++, mask >>= 1) {
 
-		/*
-		 * XXX: there is a small chance that we could run out on index before resetting
-		 * but index is unsigned long, so it will take some time.....
-		 * We use > instead of == because fetch_and_add() is off by one (see below)
-		 *
-		 * This case can happen in non-blocking mode or with multiple processes.
-		 * For non-blocking, we need to reload and continue.
-		 */
-		if (idx > psb->psb_entries) {
-			buffer_is_full = 1;
-			goto reload_pmds;
-		}
-
-		/* first entry is really entry 0, not 1 caused by fetch_and_add */
-		idx--;
+		/* skip pmd which did not overflow */
+		if ((mask & 0x1) == 0) continue;
 
-		h = (perfmon_smpl_entry_t *)(((char *)psb->psb_addr) + idx*(psb->psb_entry_size));
+		DBprintk(("PMD[%d] overflowed hw_pmd=0x%lx soft_pmd=0x%lx\n", 
+			  i, ia64_get_pmd(i), ctx->ctx_soft_pmds[i].val));
 
-		h->pid  = task->pid;
-		h->cpu  = my_cpu;
-		h->rate = 0;
-		h->ip   = regs ? regs->cr_iip : 0x0; /* where did the fault happened */
-		h->regs = mask; /* which registers overflowed */
+		/*
+		 * Because we sometimes (EARS/BTB) reset to a specific value, we cannot simply use
+		 * val to count the number of times we overflowed. Otherwise we would loose the 
+		 * current value in the PMD (which can be >0). So to make sure we don't loose
+		 * the residual counts we set val to contain full 64bits value of the counter.
+		 */
+		old_val = ctx->ctx_soft_pmds[i].val;
+		ctx->ctx_soft_pmds[i].val = 1 + pmu_conf.perf_ovfl_val + pfm_read_soft_counter(ctx, i);
 
-		/* guaranteed to monotonically increase on each cpu */
-		h->stamp = perfmon_get_stamp();
 
-		e = (unsigned long *)(h+1);
+		DBprintk(("soft_pmd[%d].val=0x%lx old_val=0x%lx pmd=0x%lx\n", 
+			  i, ctx->ctx_soft_pmds[i].val, old_val, 
+			  ia64_get_pmd(i) & pmu_conf.perf_ovfl_val));
 
 		/*
-		 * selectively store PMDs in increasing index number
+		 * now that we have extracted the hardware counter, we can clear it to ensure
+		 * that a subsequent PFM_READ_PMDS will not include it again.
 		 */
-		for (j=0, m = ctx->ctx_smpl_regs; m; m >>=1, j++) {
-			if (m & 0x1) {
-				if (PMD_IS_COUNTER(j))
-					*e =  ctx->ctx_pmds[j-PMU_FIRST_COUNTER].val
-					    + (ia64_get_pmd(j) & pmu_conf.perf_ovfl_val);
-				else {
-					*e = ia64_get_pmd(j); /* slow */
-				}
-				DBprintk((" e=%p pmd%d =0x%lx\n", (void *)e, j, *e));
-				e++;
-			}
-		}
-		/*
-		 * make the new entry visible to user, needs to be atomic
-		 */
-		ia64_fetch_and_add(1, &psb->psb_hdr->hdr_count);
+		ia64_set_pmd(i, 0UL);
 
-		DBprintk((" index=%ld entries=%ld hdr_count=%ld\n", idx, psb->psb_entries, psb->psb_hdr->hdr_count));
-		/* 
-		 * sampling buffer full ? 
+		/*
+		 * check for overflow condition
 		 */
-		if (idx == (psb->psb_entries-1)) {
-			/*
-			 * will cause notification, cannot be 0
-			 */
-			bv = mask << PMU_FIRST_COUNTER;
+		if (old_val > ctx->ctx_soft_pmds[i].val) {
 
-			buffer_is_full = 1;
+			ovfl_pmds |= 1UL << i;
 
-			DBprintk((" sampling buffer full must notify bv=0x%lx\n", bv));
+			DBprintk(("soft_pmd[%d] overflowed flags=0x%x, ovfl=0x%lx\n", i, ctx->ctx_soft_pmds[i].flags, ovfl_pmds));
 
-			/*
-			 * we do not reload here, when context is blocking
-			 */
-			if (!CTX_OVFL_NOBLOCK(ctx)) goto no_reload;
-
-			/*
-			 * here, we have a full buffer but we are in non-blocking mode
-			 * so we need to reload overflowed PMDs with sampling reset values
-			 * and restart right away.
-			 */
+			if (PMC_OVFL_NOTIFY(ctx, i)) {
+				ovfl_notify |= 1UL << i;
+			}
 		}
-		/* FALL THROUGH */
 	}
-reload_pmds:
-
-	/*
-	 * in the case of a non-blocking context, we reload
-	 * with the ovfl_rval when no user notification is taking place (short recovery)
-	 * otherwise when the buffer is full which requires user interaction) then we use
-	 * smpl_rval which is the long_recovery path (disturbance introduce by user execution).
-	 *
-	 * XXX: implies that when buffer is full then there is always notification.
-	 */
-	ovfl_has_long_recovery = CTX_OVFL_NOBLOCK(ctx) && buffer_is_full;
 
 	/*
-	 * XXX: CTX_HAS_SMPL() should really be something like CTX_HAS_SMPL() and is activated,i.e.,
-	 * one of the PMC is configured for EAR/BTB.
+	 * check for sampling buffer
 	 *
-	 * When sampling, we can only notify when the sampling buffer is full.
+	 * if present, record sample. We propagate notification ONLY when buffer
+	 * becomes full.
 	 */
-	can_notify   = CTX_HAS_SMPL(ctx) == 0 && ctx->ctx_notify_task;
-
-	DBprintk((" ovfl_has_long_recovery=%d can_notify=%d\n", ovfl_has_long_recovery, can_notify));
-
-	for (i = 0, cnum = PMU_FIRST_COUNTER; mask ; cnum++, i++, mask >>= 1) {
-
-		if ((mask & 0x1) == 0) continue;
-
-		DBprintk((" PMD[%ld] overflowed pmd=0x%lx pmod.val=0x%lx\n", cnum, ia64_get_pmd(cnum), ctx->ctx_pmds[i].val));
-
-		/*
-		 * Because we sometimes (EARS/BTB) reset to a specific value, we cannot simply use
-		 * val to count the number of times we overflowed. Otherwise we would loose the current value
-		 * in the PMD (which can be >0). So to make sure we don't loose
-		 * the residual counts we set val to contain full 64bits value of the counter.
-		 *
-		 * XXX: is this needed for EARS/BTB ?
-		 */
-		ctx->ctx_pmds[i].val += 1 + pmu_conf.perf_ovfl_val
-				      + (ia64_get_pmd(cnum) & pmu_conf.perf_ovfl_val); /* slow */
-
-		DBprintk((" pmod[%ld].val=0x%lx pmd=0x%lx\n", i, ctx->ctx_pmds[i].val, ia64_get_pmd(cnum)&pmu_conf.perf_ovfl_val));
-
-		if (can_notify && PMD_OVFL_NOTIFY(ctx, i)) {
-			DBprintk((" CPU%d should notify task %p with signal %d\n", my_cpu, ctx->ctx_notify_task, ctx->ctx_notify_sig));
-			bv |= 1 << i;
-		} else {
-			DBprintk((" CPU%d PMD[%ld] overflow, no notification\n", my_cpu, cnum));
+	if(CTX_HAS_SMPL(ctx)) {
+		ret = pfm_record_sample(task, ctx, ovfl_pmds, regs);
+		if (ret == 1) {
 			/*
-			 * In case no notification is requested, we reload the reset value right away
-			 * otherwise we wait until the notify_pid process has been called and has
-			 * has finished processing data. Check out pfm_overflow_notify()
+			 * Sampling buffer became full
+			 * If no notication was requested, then we reset buffer index
+			 * and reset registers (done below) and resume.
+			 * If notification requested, then defer reset until pfm_restart()
 			 */
-
-			/* writes to upper part are ignored, so this is safe */
-			if (ovfl_has_long_recovery) {
-				DBprintk((" CPU%d PMD[%ld] reload with smpl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval));
-				ia64_set_pmd(cnum, ctx->ctx_pmds[i].smpl_rval);
-			} else {
-				DBprintk((" CPU%d PMD[%ld] reload with ovfl_val=%lx\n", my_cpu, cnum,ctx->ctx_pmds[i].smpl_rval));
-				ia64_set_pmd(cnum, ctx->ctx_pmds[i].ovfl_rval);
+			if (ovfl_notify == 0UL) {
+				ctx->ctx_psb->psb_hdr->hdr_count = 0UL;
+				ctx->ctx_psb->psb_index		 = 0UL;
 			}
+		} else {
+			/*
+			 * sample recorded in buffer, no need to notify user
+			 */
+			ovfl_notify = 0UL;
 		}
-		if (cnum == ctx->ctx_btb_counter) need_reset_pmd16=1;
-	}
-	/*
-	 * In case of BTB overflow we need to reset the BTB index.
-	 */
-	if (need_reset_pmd16) {
-		DBprintk(("reset PMD16\n"));
-		ia64_set_pmd(16, 0);
 	}
 
-no_reload:
-
 	/*
-	 * some counters overflowed, but they did not require
-	 * user notification, so after having reloaded them above
-	 * we simply restart
+	 * No overflow requiring a user level notification
 	 */
-	if (!bv) return 0x0;
+	if (ovfl_notify == 0UL) {
+		pfm_reset_regs(ctx, &ovfl_pmds, PFM_RELOAD_SHORT_RESET);
+		return 0x0;
+	}
 
-	ctx->ctx_ovfl_regs  = bv; /* keep track of what to reset when unblocking */
-	/*
-	 * Now we know that:
-	 * 	- we have some counters which overflowed (contains in bv)
-	 * 	- someone has asked to be notified on overflow. 
+	/* 
+	 * keep track of what to reset when unblocking 
 	 */
+	ctx->ctx_ovfl_regs[0]  = ovfl_pmds; 
 
-	
 	/*
-	 * If the notification task is still present, then notify_task is non
-	 * null. It is clean by that task if it ever exits before we do. 
+	 * we have come to this point because there was an overflow and that notification
+	 * was requested. The notify_task may have disappeared, in which case notify_task
+	 * is NULL.
 	 */
-
 	if (ctx->ctx_notify_task) {
 
 		si.si_errno    = 0;
 		si.si_addr     = NULL;
 		si.si_pid      = task->pid; /* who is sending */
 
-		si.si_signo    = ctx->ctx_notify_sig; /* is SIGPROF */
-		si.si_code     = PROF_OVFL; /* goes to user */
-		si.si_pfm_ovfl = bv;
-
-
+		si.si_signo    = SIGPROF;
+		si.si_code     = PROF_OVFL; /* indicates a perfmon SIGPROF signal */
+		/*
+		 * Shift the bitvector such that the user sees bit 4 for PMD4 and so on.
+		 * We only use smpl_ovfl[0] for now. It should be fine for quite a while
+		 * until we have more than 61 PMD available.
+		 */
+		si.si_pfm_ovfl[0] = ovfl_notify;
 	
 		/*
 		 * when the target of the signal is not ourself, we have to be more
@@ -1626,15 +2614,29 @@
 		if (ctx->ctx_notify_task != current) {
 			/*
 			 * grab the notification lock for this task
+			 * This guarantees that the sequence: test + send_signal
+			 * is atomic with regards to the ctx_notify_task field.
+			 *
+			 * We need a spinlock and not just an atomic variable for this.
+			 *
 			 */
-			spin_lock(&ctx->ctx_notify_lock);
+			spin_lock(&ctx->ctx_lock);
 
 			/*
 			 * now notify_task cannot be modified until we're done
 			 * if NULL, they it got modified while we were in the handler
 			 */
 			if (ctx->ctx_notify_task == NULL) {
-				spin_unlock(&ctx->ctx_notify_lock);
+
+				spin_unlock(&ctx->ctx_lock);
+
+				/*
+				 * If we've lost the notified task, then we will run
+				 * to completion wbut keep the PMU frozen. Results
+				 * will be incorrect anyway. We do not kill task
+				 * to leave it possible to attach perfmon context
+				 * to already running task.
+				 */
 				goto lost_notify;
 			}
 			/*
@@ -1648,20 +2650,23 @@
 	 	 * necessarily go to the signal handler (if any) when it goes back to
 	 	 * user mode.
 	 	 */
-		DBprintk((" %d sending %d notification to %d\n", task->pid, si.si_signo, ctx->ctx_notify_task->pid));
+		DBprintk(("[%d] sending notification to [%d]\n", 
+			  task->pid, ctx->ctx_notify_task->pid));
 
 
 		/* 
 		 * this call is safe in an interrupt handler, so does read_lock() on tasklist_lock
 		 */
-		ret = send_sig_info(ctx->ctx_notify_sig, &si, ctx->ctx_notify_task);
-		if (ret != 0) printk(" send_sig_info(process %d, SIGPROF)=%d\n",  ctx->ctx_notify_task->pid, ret);
+		ret = send_sig_info(SIGPROF, &si, ctx->ctx_notify_task);
+		if (ret != 0) 
+			printk("send_sig_info(process %d, SIGPROF)=%d\n",  
+			       ctx->ctx_notify_task->pid, ret);
 		/*
 		 * now undo the protections in order
 		 */
 		if (ctx->ctx_notify_task != current) {
 			read_unlock(&tasklist_lock);
-			spin_unlock(&ctx->ctx_notify_lock);
+			spin_unlock(&ctx->ctx_lock);
 		}
 
 		/*
@@ -1678,35 +2683,41 @@
 		 * before, changing it to NULL will still maintain this invariant.
 		 * Of course, when it is equal to current it cannot change at this point.
 		 */
-		if (!CTX_OVFL_NOBLOCK(ctx) && ctx->ctx_notify_task != current) {
-				th->pfm_must_block = 1; /* will cause blocking */
+		DBprintk(("block=%d notify [%d] current [%d]\n", 
+			ctx->ctx_fl_block,
+			ctx->ctx_notify_task ? ctx->ctx_notify_task->pid: -1, 
+			current->pid ));
+
+		if (!CTX_OVFL_NOBLOCK(ctx) && ctx->ctx_notify_task != task) {
+			t->pfm_ovfl_block_reset = 1; /* will cause blocking */
 		}
 	} else {
-lost_notify:
-		DBprintk((" notification task has disappeared !\n"));
+lost_notify: /* XXX: more to do here, to convert to non-blocking (reset values) */
+
+		DBprintk(("notification task has disappeared !\n"));
 		/*
-		 * for a non-blocking context, we make sure we do not fall into the pfm_overflow_notify()
-		 * trap. Also in the case of a blocking context with lost notify process, then we do not
-		 * want to block either (even though it is interruptible). In this case, the PMU will be kept
-		 * frozen and the process will run to completion without monitoring enabled.
+		 * for a non-blocking context, we make sure we do not fall into the 
+		 * pfm_overflow_notify() trap. Also in the case of a blocking context with lost 
+		 * notify process, then we do not want to block either (even though it is 
+		 * interruptible). In this case, the PMU will be kept frozen and the process will 
+		 * run to completion without monitoring enabled.
 		 *
 		 * Of course, we cannot loose notify process when self-monitoring.
 		 */
-		th->pfm_must_block = 0; 
+		t->pfm_ovfl_block_reset = 0; 
 
 	}
 	/*
-	 * if we block, we keep the PMU frozen. If non-blocking we restart.
-	 * in the case of non-blocking were the notify process is lost, we also 
-	 * restart. 
+	 * If notification was successful, then we rely on the pfm_restart()
+	 * call to unfreeze and reset (in both blocking or non-blocking mode).
+	 *
+	 * If notification failed, then we will keep the PMU frozen and run
+	 * the task to completion
 	 */
-	if (!CTX_OVFL_NOBLOCK(ctx)) 
-		ctx->ctx_fl_frozen  = 1;
-	else
-		ctx->ctx_fl_frozen = 0;
+	ctx->ctx_fl_frozen = 1;
 
-	DBprintk((" reload pmc0=0x%x must_block=%ld\n",
-				ctx->ctx_fl_frozen ? 0x1 : 0x0, th->pfm_must_block));
+	DBprintk(("reload pmc0=0x%x must_block=%ld\n",
+				ctx->ctx_fl_frozen ? 0x1 : 0x0, t->pfm_ovfl_block_reset));
 
 	return ctx->ctx_fl_frozen ? 0x1 : 0x0;
 }
@@ -1715,29 +2726,40 @@
 perfmon_interrupt (int irq, void *arg, struct pt_regs *regs)
 {
 	u64 pmc0;
-	struct task_struct *ta;
+	struct task_struct *task;
 
-	pmc0 = ia64_get_pmc(0); /* slow */
+	pfm_ovfl_intr_count++;
+
+	/* 
+	 * srlz.d done before arriving here
+	 *
+	 * This is slow
+	 */
+	pmc0 = ia64_get_pmc(0); 
 
 	/*
 	 * if we have some pending bits set
 	 * assumes : if any PM[0].bit[63-1] is set, then PMC[0].fr = 1
 	 */
-	if ((pmc0 & ~0x1) && (ta=PMU_OWNER())) {
-
-		/* assumes, PMC[0].fr = 1 at this point */
-		pmc0 = update_counters(ta, pmc0, regs);
+	if ((pmc0 & ~0x1UL)!=0UL && (task=PMU_OWNER())!= NULL) {
 
-		/*
-		 * if pmu_frozen = 0
-		 *	pmc0 = 0 and we resume monitoring right away
-		 * else
-		 *	pmc0 = 0x1 frozen but all pending bits are cleared
+		/* 
+		 * assumes, PMC[0].fr = 1 at this point 
+		 *
+		 * XXX: change protype to pass &pmc0
 		 */
-		ia64_set_pmc(0, pmc0);
-		ia64_srlz_d();
+		pmc0 = pfm_overflow_handler(task, pmc0, regs);
+
+		/* we never explicitely freeze PMU here */
+		if (pmc0 == 0) {
+			ia64_set_pmc(0, 0);
+			ia64_srlz_d();
+		}
 	} else {
-		printk("perfmon: Spurious PMU overflow interrupt: pmc0=0x%lx owner=%p\n", pmc0, (void *)PMU_OWNER());
+		pfm_spurious_ovfl_intr_count++;
+
+		DBprintk(("perfmon: Spurious PMU overflow interrupt on CPU%d: pmc0=0x%lx owner=%p\n", 
+			smp_processor_id(), pmc0, (void *)PMU_OWNER()));
 	}
 }
 
@@ -1745,14 +2767,39 @@
 static int
 perfmon_proc_info(char *page)
 {
+#ifdef CONFIG_SMP
+#define cpu_is_online(i) (cpu_online_map & (1UL << i))
+#else
+#define cpu_is_online(i)        1
+#endif
 	char *p = page;
 	u64 pmc0 = ia64_get_pmc(0);
 	int i;
 
-	p += sprintf(p, "CPU%d.pmc[0]=%lx\nPerfmon debug: %s\n", smp_processor_id(), pmc0, pfm_debug ? "On" : "Off");
-	p += sprintf(p, "proc_sessions=%lu sys_sessions=%lu\n", 
-			pfs_info.pfs_proc_sessions, 
-			pfs_info.pfs_sys_session);
+	p += sprintf(p, "perfmon enabled: %s\n", pmu_conf.pfm_is_disabled ? "No": "Yes");
+
+	p += sprintf(p, "monitors_pmcs0]=0x%lx\n", pmu_conf.monitor_pmcs[0]);
+	p += sprintf(p, "counter_pmcds[0]=0x%lx\n", pmu_conf.counter_pmds[0]);
+	p += sprintf(p, "overflow interrupts=%lu\n", pfm_ovfl_intr_count);
+	p += sprintf(p, "spurious overflow interrupts=%lu\n", pfm_spurious_ovfl_intr_count);
+	p += sprintf(p, "recorded samples=%lu\n", pfm_recorded_samples_count);
+
+	p += sprintf(p, "CPU%d.pmc[0]=%lx\nPerfmon debug: %s\n", 
+			smp_processor_id(), pmc0, pfm_debug_mode ? "On" : "Off");
+
+#ifdef CONFIG_SMP
+	p += sprintf(p, "CPU%d cpu_data.pfm_syst_wide=%d cpu_data.dcr_pp=%d\n", 
+			smp_processor_id(), local_cpu_data->pfm_syst_wide, local_cpu_data->pfm_dcr_pp);
+#endif
+
+	LOCK_PFS();
+	p += sprintf(p, "proc_sessions=%lu\nsys_sessions=%lu\nsys_use_dbregs=%lu\nptrace_use_dbregs=%lu\n", 
+			pfm_sessions.pfs_task_sessions, 
+			pfm_sessions.pfs_sys_sessions,
+			pfm_sessions.pfs_sys_use_dbregs,
+			pfm_sessions.pfs_ptrace_use_dbregs);
+
+	UNLOCK_PFS();
 
 	for(i=0; i < NR_CPUS; i++) {
 		if (cpu_is_online(i)) {
@@ -1761,10 +2808,11 @@
 					pmu_owners[i].owner ? pmu_owners[i].owner->pid: -1);
 		}
 	}
+
 	return p - page;
 }
 
-/* for debug only */
+/* /proc interface, for debug only */
 static int
 perfmon_read_entry(char *page, char **start, off_t off, int count, int *eof, void *data)
 {
@@ -1781,153 +2829,90 @@
 	return len;
 }
 
-static struct irqaction perfmon_irqaction = {
-	handler:	perfmon_interrupt,
-	flags:		SA_INTERRUPT,
-	name:		"perfmon"
-};
-
-void __init
-perfmon_init (void)
+#ifdef CONFIG_SMP
+void
+pfm_syst_wide_update_task(struct task_struct *task, int mode)
 {
-	pal_perf_mon_info_u_t pm_info;
-	s64 status;
-
-	register_percpu_irq(IA64_PERFMON_VECTOR, &perfmon_irqaction);
+	struct pt_regs *regs = (struct pt_regs *)((unsigned long) task + IA64_STK_OFFSET);
 
-	ia64_set_pmv(IA64_PERFMON_VECTOR);
-	ia64_srlz_d();
+	regs--;
 
-	pmu_conf.pfm_is_disabled = 1;
+	/*
+	 * propagate the value of the dcr_pp bit to the psr
+	 */
+	ia64_psr(regs)->pp = mode ? local_cpu_data->pfm_dcr_pp : 0;
+}
+#endif
 
-	printk("perfmon: version %s (sampling format v%d)\n", PFM_VERSION, PFM_SMPL_HDR_VERSION);
-	printk("perfmon: Interrupt vectored to %u\n", IA64_PERFMON_VECTOR);
 
-	if ((status=ia64_pal_perf_mon_info(pmu_conf.impl_regs, &pm_info)) != 0) {
-		printk("perfmon: PAL call failed (%ld)\n", status);
-		return;
-	}
-	pmu_conf.perf_ovfl_val = (1L << pm_info.pal_perf_mon_info_s.width) - 1;
-	pmu_conf.max_counters  = pm_info.pal_perf_mon_info_s.generic;
-	pmu_conf.num_pmcs      = find_num_pm_regs(pmu_conf.impl_regs);
-	pmu_conf.num_pmds      = find_num_pm_regs(&pmu_conf.impl_regs[4]);
+void
+pfm_save_regs (struct task_struct *task)
+{
+	pfm_context_t *ctx;
+	u64 psr;
 
-	printk("perfmon: %d bits counters (max value 0x%lx)\n", pm_info.pal_perf_mon_info_s.width, pmu_conf.perf_ovfl_val);
-	printk("perfmon: %ld PMC/PMD pairs, %ld PMCs, %ld PMDs\n", pmu_conf.max_counters, pmu_conf.num_pmcs, pmu_conf.num_pmds);
+	ctx = task->thread.pfm_context;
 
-	/* sanity check */
-	if (pmu_conf.num_pmds >= IA64_NUM_PMD_REGS || pmu_conf.num_pmcs >= IA64_NUM_PMC_REGS) {
-		printk(KERN_ERR "perfmon: ERROR not enough PMC/PMD storage in kernel, perfmon is DISABLED\n");
-		return; /* no need to continue anyway */
-	}
-	/* we are all set */
-	pmu_conf.pfm_is_disabled = 0;
 
 	/*
-	 * Insert the tasklet in the list.
-	 * It is still disabled at this point, so it won't run
-	printk(__FUNCTION__" tasklet is %p state=%d, count=%d\n", &perfmon_tasklet, perfmon_tasklet.state, perfmon_tasklet.count);
+	 * save current PSR: needed because we modify it
 	 */
+	__asm__ __volatile__ ("mov %0=psr;;": "=r"(psr) :: "memory");
 
 	/*
-	 * for now here for debug purposes
+	 * stop monitoring:
+	 * This is the last instruction which can generate an overflow
+	 *
+	 * We do not need to set psr.sp because, it is irrelevant in kernel.
+	 * It will be restored from ipsr when going back to user level
 	 */
-	perfmon_dir = create_proc_read_entry ("perfmon", 0, 0, perfmon_read_entry, NULL);
-}
+	__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+
+	ctx->ctx_saved_psr = psr;
+
+	//ctx->ctx_last_cpu  = smp_processor_id();
 
-void
-perfmon_init_percpu (void)
-{
-	ia64_set_pmv(IA64_PERFMON_VECTOR);
-	ia64_srlz_d();
 }
 
-void
-pfm_save_regs (struct task_struct *ta)
+static void
+pfm_lazy_save_regs (struct task_struct *task)
 {
-	struct task_struct *owner;
 	pfm_context_t *ctx;
 	struct thread_struct *t;
-	u64 pmc0, psr;
 	unsigned long mask;
 	int i;
 
-	t   = &ta->thread;
-	ctx = ta->thread.pfm_context;
+	DBprintk(("on [%d] by [%d]\n", task->pid, current->pid));
 
-	/*
-	 * We must make sure that we don't loose any potential overflow
-	 * interrupt while saving PMU context. In this code, external
-	 * interrupts are always enabled.
-	 */
+	t   = &task->thread;
+	ctx = task->thread.pfm_context;
 
-	/*
-	 * save current PSR: needed because we modify it
+#ifdef CONFIG_SMP
+	/* 
+	 * announce we are saving this PMU state
+	 * This will cause other CPU, to wait until we're done
+	 * before using the context.h
+	 *
+	 * must be an atomic operation
 	 */
-	__asm__ __volatile__ ("mov %0=psr;;": "=r"(psr) :: "memory");
+	atomic_set(&ctx->ctx_saving_in_progress, 1);
 
-	/*
-	 * stop monitoring:
-	 * This is the only way to stop monitoring without destroying overflow
-	 * information in PMC[0].
-	 * This is the last instruction which can cause overflow when monitoring
-	 * in kernel.
-	 * By now, we could still have an overflow interrupt in-flight.
-	 */
-	__asm__ __volatile__ ("rsm psr.up|psr.pp;;"::: "memory");
+	 /*
+	  * if owner is NULL, it means that the other CPU won the race
+	  * and the IPI has caused the context to be saved in pfm_handle_fectch_regs()
+	  * instead of here. We have nothing to do
+	  *
+	  * note that this is safe, because the other CPU NEVER modifies saving_in_progress.
+	  */
+	if (PMU_OWNER() == NULL) goto do_nothing;
+#endif
 
 	/*
-	 * Mark the PMU as not owned
-	 * This will cause the interrupt handler to do nothing in case an overflow
-	 * interrupt was in-flight
-	 * This also guarantees that pmc0 will contain the final state
-	 * It virtually gives us full control over overflow processing from that point
-	 * on.
-	 * It must be an atomic operation.
+	 * do not own the PMU
 	 */
-	owner = PMU_OWNER();
 	SET_PMU_OWNER(NULL);
 
-	/*
-	 * read current overflow status:
-	 *
-	 * we are guaranteed to read the final stable state
-	 */
 	ia64_srlz_d();
-	pmc0 = ia64_get_pmc(0); /* slow */
-
-	/*
-	 * freeze PMU:
-	 *
-	 * This destroys the overflow information. This is required to make sure
-	 * next process does not start with monitoring on if not requested
-	 */
-	ia64_set_pmc(0, 1);
-
-	/*
-	 * Check for overflow bits and proceed manually if needed
-	 *
-	 * It is safe to call the interrupt handler now because it does
-	 * not try to block the task right away. Instead it will set a
-	 * flag and let the task proceed. The blocking will only occur
-	 * next time the task exits from the kernel.
-	 */
-	if (pmc0 & ~0x1) {
-		update_counters(owner, pmc0, NULL);
-		/* we will save the updated version of pmc0 */
-	}
-	/*
-	 * restore PSR for context switch to save
-	 */
-	__asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory");
-
-	/*
-	 * we do not save registers if we can do lazy
-	 */
-	if (PFM_CAN_DO_LAZY()) {
-		SET_PMU_OWNER(owner);
-		return;
-	}
 
 	/*
 	 * XXX needs further optimization.
@@ -1937,30 +2922,75 @@
 	for (i=0; mask; i++, mask>>=1) {
 		if (mask & 0x1) t->pmd[i] =ia64_get_pmd(i);
 	}
-
-	/* skip PMC[0], we handle it separately */
-	mask = ctx->ctx_used_pmcs[0]>>1;
-	for (i=1; mask; i++, mask>>=1) {
+	/*
+	 * XXX: simplify to pmc0 only
+	 */
+	mask = ctx->ctx_saved_pmcs[0];
+	for (i=0; mask; i++, mask>>=1) {
 		if (mask & 0x1) t->pmc[i] = ia64_get_pmc(i);
 	}
+
+	/* not owned by this CPU */
+	atomic_set(&ctx->ctx_last_cpu, -1);
+
+#ifdef CONFIG_SMP
+do_nothing:
+#endif
 	/*
-	 * Throughout this code we could have gotten an overflow interrupt. It is transformed
-	 * into a spurious interrupt as soon as we give up pmu ownership.
+	 * declare we are done saving this context
+	 *
+	 * must be an atomic operation
 	 */
+	atomic_set(&ctx->ctx_saving_in_progress,0);
+
 }
 
-static void
-pfm_lazy_save_regs (struct task_struct *ta)
+#ifdef CONFIG_SMP
+/*
+ * Handles request coming from other CPUs
+ */
+static void 
+pfm_handle_fetch_regs(void *info)
 {
-	pfm_context_t *ctx;
+	pfm_smp_ipi_arg_t *arg = info;
 	struct thread_struct *t;
+	pfm_context_t *ctx;
 	unsigned long mask;
 	int i;
 
-	DBprintk(("  on [%d] by [%d]\n", ta->pid, current->pid));
+	ctx = arg->task->thread.pfm_context;
+	t   = &arg->task->thread;
+
+	DBprintk(("task=%d owner=%d saving=%d\n", 
+		  arg->task->pid,
+		  PMU_OWNER() ? PMU_OWNER()->pid: -1,
+		  atomic_read(&ctx->ctx_saving_in_progress)));
+
+	/* must wait if saving was interrupted */
+	if (atomic_read(&ctx->ctx_saving_in_progress)) {
+		arg->retval = 1;
+		return;
+	}
+
+	/* can proceed, done with context */
+	if (PMU_OWNER() != arg->task) {
+		arg->retval = 0;
+		return;
+	}
+
+	DBprintk(("saving state for [%d] save_pmcs=0x%lx all_pmcs=0x%lx used_pmds=0x%lx\n", 
+		arg->task->pid,
+		ctx->ctx_saved_pmcs[0],
+		ctx->ctx_reload_pmcs[0],
+		ctx->ctx_used_pmds[0]));
+
+	/*
+	 * XXX: will be replaced with pure assembly call
+	 */
+	SET_PMU_OWNER(NULL);
+
+	ia64_srlz_d();
 
-	t   = &ta->thread;
-	ctx = ta->thread.pfm_context;
 	/*
 	 * XXX needs further optimization.
 	 * Also must take holes into account
@@ -1970,84 +3000,295 @@
 		if (mask & 0x1) t->pmd[i] =ia64_get_pmd(i);
 	}
 	
-	/* skip PMC[0], we handle it separately */
-	mask = ctx->ctx_used_pmcs[0]>>1;
-	for (i=1; mask; i++, mask>>=1) {
+	mask = ctx->ctx_saved_pmcs[0];
+	for (i=0; mask; i++, mask>>=1) {
 		if (mask & 0x1) t->pmc[i] = ia64_get_pmc(i);
 	}
-	SET_PMU_OWNER(NULL);
+	/* not owned by this CPU */
+	atomic_set(&ctx->ctx_last_cpu, -1);
+
+	/* can proceed */
+	arg->retval = 0;
 }
 
+/*
+ * Function call to fetch PMU state from another CPU identified by 'cpu'.
+ * If the context is being saved on the remote CPU, then we busy wait until
+ * the saving is done and then we return. In this case, non IPI is sent.
+ * Otherwise, we send an IPI to the remote CPU, potentially interrupting 
+ * pfm_lazy_save_regs() over there.
+ *
+ * If the retval==1, then it means that we interrupted remote save and that we must
+ * wait until the saving is over before proceeding.
+ * Otherwise, we did the saving on the remote CPU, and it was done by the time we got there.
+ * in either case, we can proceed.
+ */
+static void
+pfm_fetch_regs(int cpu, struct task_struct *task, pfm_context_t *ctx)
+{
+	pfm_smp_ipi_arg_t  arg;
+	int ret;
+
+	arg.task   = task;
+	arg.retval = -1;
+
+	if (atomic_read(&ctx->ctx_saving_in_progress)) {
+		DBprintk(("no IPI, must wait for [%d] to be saved on [%d]\n", task->pid, cpu));
+
+		/* busy wait */
+		while (atomic_read(&ctx->ctx_saving_in_progress));
+		return;
+	}
+	DBprintk(("calling CPU %d from CPU %d\n", cpu, smp_processor_id()));
+
+	if (cpu == -1) {
+		printk("refusing to use -1 for [%d]\n", task->pid);
+		return;
+	}
+
+	/* will send IPI to other CPU and wait for completion of remote call */
+	if ((ret=smp_call_function_single(cpu, pfm_handle_fetch_regs, &arg, 0, 1))) {
+		printk("perfmon: remote CPU call from %d to %d error %d\n", smp_processor_id(), cpu, ret);
+		return;
+	}
+	/*
+	 * we must wait until saving is over on the other CPU
+	 * This is the case, where we interrupted the saving which started just at the time we sent the
+	 * IPI.
+	 */
+	if (arg.retval == 1) {
+		DBprintk(("must wait for [%d] to be saved on [%d]\n", task->pid, cpu));
+		while (atomic_read(&ctx->ctx_saving_in_progress));
+		DBprintk(("done saving for [%d] on [%d]\n", task->pid, cpu));
+	}
+}
+#endif /* CONFIG_SMP */
+
 void
-pfm_load_regs (struct task_struct *ta)
+pfm_load_regs (struct task_struct *task)
 {
-	struct thread_struct *t = &ta->thread;
-	pfm_context_t *ctx = ta->thread.pfm_context;
+	struct thread_struct *t;
+	pfm_context_t *ctx;
 	struct task_struct *owner;
 	unsigned long mask;
+	u64 psr;
 	int i;
+#ifdef CONFIG_SMP
+	int cpu;
+#endif
 
 	owner = PMU_OWNER();
-	if (owner == ta) goto skip_restore;
+	ctx   = task->thread.pfm_context;
+
+	/*
+	 * if we were the last user, then nothing to do except restore psr
+	 */
+	if (owner == task) {
+		if (atomic_read(&ctx->ctx_last_cpu) != smp_processor_id())
+			DBprintk(("invalid last_cpu=%d for [%d]\n", 
+				atomic_read(&ctx->ctx_last_cpu), task->pid));
+
+		psr = ctx->ctx_saved_psr;
+		__asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory");
+
+		return;
+	}
+	DBprintk(("load_regs: must reload for [%d] owner=%d\n", 
+		task->pid, owner ? owner->pid : -1 ));
+	/*
+	 * someone else is still using the PMU, first push it out and
+	 * then we'll be able to install our stuff !
+	 */
 	if (owner) pfm_lazy_save_regs(owner);
 
-	SET_PMU_OWNER(ta);
+#ifdef CONFIG_SMP
+	/* 
+	 * check if context on another CPU (-1 means saved)
+	 * We MUST use the variable, as last_cpu may change behind our 
+	 * back. If it changes to -1 (not on a CPU anymore), then in cpu
+	 * we have the last CPU the context was on. We may be sending the 
+	 * IPI for nothing, but we have no way of verifying this. 
+	 */
+	cpu = atomic_read(&ctx->ctx_last_cpu);
+	if (cpu != -1) {
+		pfm_fetch_regs(cpu, task, ctx);
+	}
+#endif
+	t   = &task->thread;
 
+	/*
+	 * XXX: will be replaced by assembly routine
+	 * We clear all unused PMDs to avoid leaking information
+	 */
 	mask = ctx->ctx_used_pmds[0];
 	for (i=0; mask; i++, mask>>=1) {
-		if (mask & 0x1) ia64_set_pmd(i, t->pmd[i]);
+		if (mask & 0x1) 
+			ia64_set_pmd(i, t->pmd[i]);
+		else
+			ia64_set_pmd(i, 0UL);
 	}
+	/* XXX: will need to clear all unused pmd, for security */
 
-	/* skip PMC[0] to avoid side effects */
-	mask = ctx->ctx_used_pmcs[0]>>1;
+	/* 
+	 * skip pmc[0] to avoid side-effects, 
+	 * all PMCs are systematically reloaded, unsued get default value
+	 * to avoid picking up stale configuration
+	 */	
+	mask = ctx->ctx_reload_pmcs[0]>>1;
 	for (i=1; mask; i++, mask>>=1) {
 		if (mask & 0x1) ia64_set_pmc(i, t->pmc[i]);
 	}
-skip_restore:
+
 	/*
-	 * unfreeze only when possible
+	 * restore debug registers when used for range restrictions.
+	 * We must restore the unused registers to avoid picking up
+	 * stale information.
+	 */
+	mask = ctx->ctx_used_ibrs[0];
+	for (i=0; mask; i++, mask>>=1) {
+		if (mask & 0x1) 
+			ia64_set_ibr(i, t->ibr[i]);
+		else
+			ia64_set_ibr(i, 0UL);
+	}
+
+	mask = ctx->ctx_used_dbrs[0];
+	for (i=0; mask; i++, mask>>=1) {
+		if (mask & 0x1) 
+			ia64_set_dbr(i, t->dbr[i]);
+		else
+			ia64_set_dbr(i, 0UL);
+	}
+
+	if (t->pmc[0] & ~0x1) {
+		ia64_srlz_d();
+		pfm_overflow_handler(task, t->pmc[0], NULL);
+	}
+
+	/*
+	 * fl_frozen==1 when we are in blocking mode waiting for restart
 	 */
 	if (ctx->ctx_fl_frozen == 0) {
 		ia64_set_pmc(0, 0);
 		ia64_srlz_d();
-		/* place where we potentially (kernel level) start monitoring again */
 	}
+	atomic_set(&ctx->ctx_last_cpu, smp_processor_id());
+
+	SET_PMU_OWNER(task);
+
+	/*
+	 * restore the psr we changed in pfm_save_regs()
+	 */
+	psr = ctx->ctx_saved_psr;
+	__asm__ __volatile__ ("mov psr.l=%0;; srlz.i;;"::"r"(psr): "memory");
+
 }
 
+/*
+ * XXX: make this routine able to work with non current context
+ */
+static void
+ia64_reset_pmu(struct task_struct *task)
+{
+	struct thread_struct *t = &task->thread;
+	pfm_context_t *ctx = t->pfm_context;
+	unsigned long mask;
+	int i;
+
+	if (task != current) {
+		printk("perfmon: invalid task in ia64_reset_pmu()\n");
+		return;
+	}
+
+	/* Let's make sure the PMU is frozen */
+	ia64_set_pmc(0,1);
+
+	/*
+	 * install reset values for PMC. We skip PMC0 (done above)
+	 * XX: good up to 64 PMCS
+	 */
+	mask = pmu_conf.impl_regs[0] >> 1;
+	for(i=1; mask; mask>>=1, i++) {
+		if (mask & 0x1) {
+			ia64_set_pmc(i, reset_pmcs[i]);
+			/*
+			 * When restoring context, we must restore ALL pmcs, even the ones 
+			 * that the task does not use to avoid leaks and possibly corruption
+			 * of the sesion because of configuration conflicts. So here, we 
+			 * initializaed the table used in the context switch restore routine.
+	 		 */
+			t->pmc[i] = reset_pmcs[i];
+			DBprintk((" pmc[%d]=0x%lx\n", i, reset_pmcs[i]));
+						 
+		}
+	}
+	/*
+	 * clear reset values for PMD. 
+	 * XX: good up to 64 PMDS. Suppose that zero is a valid value.
+	 */
+	mask = pmu_conf.impl_regs[4];
+	for(i=0; mask; mask>>=1, i++) {
+		if (mask & 0x1) ia64_set_pmd(i, 0UL);
+	}
+
+	/*
+	 * On context switched restore, we must restore ALL pmc even
+	 * when they are not actively used by the task. In UP, the incoming process 
+	 * may otherwise pick up left over PMC state from the previous process.
+	 * As opposed to PMD, stale PMC can cause harm to the incoming
+	 * process because they may change what is being measured. 
+	 * Therefore, we must systematically reinstall the entire
+	 * PMC state. In SMP, the same thing is possible on the 
+	 * same CPU but also on between 2 CPUs.
+	 *
+	 * There is unfortunately no easy way to avoid this problem
+	 * on either UP or SMP. This definitively slows down the 
+	 * pfm_load_regs(). 
+	 */
+	
+	 /*
+	  * We must include all the PMC in this mask to make sure we don't
+	  * see any side effect of the stale state, such as opcode matching
+	  * or range restrictions, for instance.
+	  */
+	ctx->ctx_reload_pmcs[0] = pmu_conf.impl_regs[0];
+
+	/*
+	 * useful in case of re-enable after disable
+	 */
+	ctx->ctx_used_pmds[0] = 0UL;
+	ctx->ctx_used_ibrs[0] = 0UL;
+	ctx->ctx_used_dbrs[0] = 0UL;
+
+	ia64_srlz_d();
+}
 
 /*
  * This function is called when a thread exits (from exit_thread()).
  * This is a simplified pfm_save_regs() that simply flushes the current
  * register state into the save area taking into account any pending
- * overflow. This time no notification is sent because the taks is dying
+ * overflow. This time no notification is sent because the task is dying
  * anyway. The inline processing of overflows avoids loosing some counts.
  * The PMU is frozen on exit from this call and is to never be reenabled
  * again for this task.
+ *
  */
 void
-pfm_flush_regs (struct task_struct *ta)
+pfm_flush_regs (struct task_struct *task)
 {
 	pfm_context_t *ctx;
-	u64 pmc0, psr, mask;
-	int i,j;
+	u64 pmc0;
+	unsigned long mask, mask2, val;
+	int i;
 
-	if (ta == NULL) {
-		panic(__FUNCTION__" task is NULL\n");
-	}
-	ctx = ta->thread.pfm_context;
-	if (ctx == NULL) {
-		panic(__FUNCTION__" no PFM ctx is NULL\n");
-	}
-	/*
-	 * We must make sure that we don't loose any potential overflow
-	 * interrupt while saving PMU context. In this code, external
-	 * interrupts are always enabled.
-	 */
+	ctx = task->thread.pfm_context;
 
-	/*
-	 * save current PSR: needed because we modify it
+	if (ctx == NULL) return;
+
+	/* 
+	 * that's it if context already disabled
 	 */
-	__asm__ __volatile__ ("mov %0=psr;;": "=r"(psr) :: "memory");
+	if (ctx->ctx_flags.state == PFM_CTX_DISABLED) return;
 
 	/*
 	 * stop monitoring:
@@ -2057,7 +3298,27 @@
 	 * in kernel.
 	 * By now, we could still have an overflow interrupt in-flight.
 	 */
-	__asm__ __volatile__ ("rsm psr.up;;"::: "memory");
+	if (ctx->ctx_fl_system) {
+
+		__asm__ __volatile__ ("rsm psr.pp;;"::: "memory");
+
+		/* disable dcr pp */
+		ia64_set_dcr(ia64_get_dcr() & ~IA64_DCR_PP);
+
+#ifdef CONFIG_SMP
+		local_cpu_data->pfm_syst_wide = 0;
+		local_cpu_data->pfm_dcr_pp    = 0;
+#else
+		pfm_tasklist_toggle_pp(0);
+#endif
+
+	} else  {
+
+		__asm__ __volatile__ ("rum psr.up;;"::: "memory");
+
+		/* no more save/restore on ctxsw */
+		current->thread.flags &= ~IA64_THREAD_PM_VALID;
+	}
 
 	/*
 	 * Mark the PMU as not owned
@@ -2088,85 +3349,69 @@
 	ia64_srlz_d();
 
 	/*
-	 * restore PSR for context switch to save
+	 * We don't need to restore psr, because we are on our way out anyway
 	 */
-	__asm__ __volatile__ ("mov psr.l=%0;;srlz.i;"::"r"(psr): "memory");
 
 	/*
 	 * This loop flushes the PMD into the PFM context.
-	 * IT also processes overflow inline.
+	 * It also processes overflow inline.
 	 *
 	 * IMPORTANT: No notification is sent at this point as the process is dying.
 	 * The implicit notification will come from a SIGCHILD or a return from a
 	 * waitpid().
 	 *
-	 * XXX: must take holes into account
 	 */
-	mask = pmc0 >> PMU_FIRST_COUNTER;
-	for (i=0,j=PMU_FIRST_COUNTER; i< pmu_conf.max_counters; i++,j++) {
-
-		/* collect latest results */
-		ctx->ctx_pmds[i].val += ia64_get_pmd(j) & pmu_conf.perf_ovfl_val;
 
-		/*
-		 * now everything is in ctx_pmds[] and we need
-		 * to clear the saved context from save_regs() such that
-		 * pfm_read_pmds() gets the correct value
-		 */
-		ta->thread.pmd[j] = 0;
-
-		/* take care of overflow inline */
-		if (mask & 0x1) {
-			ctx->ctx_pmds[i].val += 1 + pmu_conf.perf_ovfl_val;
-			DBprintk((" PMD[%d] overflowed pmd=0x%lx pmds.val=0x%lx\n",
-			j, ia64_get_pmd(j), ctx->ctx_pmds[i].val));
-		}
-		mask >>=1;
-	}
-}
+	if (atomic_read(&ctx->ctx_last_cpu) != smp_processor_id()) 
+		printk("perfmon: [%d] last_cpu=%d\n", task->pid, atomic_read(&ctx->ctx_last_cpu));
 
-/*
- * XXX: this routine is not very portable for PMCs
- * XXX: make this routine able to work with non current context
- */
-static void
-ia64_reset_pmu(void)
-{
-	int i;
+	mask  = pmc0 >> PMU_FIRST_COUNTER;
+	mask2 = ctx->ctx_used_pmds[0] >> PMU_FIRST_COUNTER;
 
-	/* PMU is frozen, no pending overflow bits */
-	ia64_set_pmc(0,1);
+	for (i = PMU_FIRST_COUNTER; mask2; i++, mask>>=1, mask2>>=1) {
 
-	/* extra overflow bits + counter configs cleared */
-	for(i=1; i< PMU_FIRST_COUNTER + pmu_conf.max_counters ; i++) {
-		ia64_set_pmc(i,0);
-	}
+		/* skip non used pmds */
+		if ((mask2 & 0x1) == 0) continue;
 
-	/* opcode matcher set to all 1s */
-	ia64_set_pmc(8,~0);
-	ia64_set_pmc(9,~0);
+		val = ia64_get_pmd(i);
 
-	/* I-EAR config cleared, plm=0 */
-	ia64_set_pmc(10,0);
+		if (PMD_IS_COUNTING(i)) {
 
-	/* D-EAR config cleared, PMC[11].pt must be 1 */
-	ia64_set_pmc(11,1 << 28);
+			DBprintk(("[%d] pmd[%d] soft_pmd=0x%lx hw_pmd=0x%lx\n", task->pid, i, ctx->ctx_soft_pmds[i].val, val & pmu_conf.perf_ovfl_val));
 
-	/* BTB config. plm=0 */
-	ia64_set_pmc(12,0);
+			/* collect latest results */
+			ctx->ctx_soft_pmds[i].val += val & pmu_conf.perf_ovfl_val;
 
-	/* Instruction address range, PMC[13].ta must be 1 */
-	ia64_set_pmc(13,1);
+			/*
+			 * now everything is in ctx_soft_pmds[] and we need
+			 * to clear the saved context from save_regs() such that
+			 * pfm_read_pmds() gets the correct value
+			 */
+			task->thread.pmd[i] = 0;
 
-	/* clears all PMD registers */
-	for(i=0;i< pmu_conf.num_pmds; i++) {
-		if (PMD_IS_IMPL(i))  ia64_set_pmd(i,0);
+			/* take care of overflow inline */
+			if (mask & 0x1) {
+				ctx->ctx_soft_pmds[i].val += 1 + pmu_conf.perf_ovfl_val;
+				DBprintk(("[%d] pmd[%d] overflowed soft_pmd=0x%lx\n",
+					task->pid, i, ctx->ctx_soft_pmds[i].val));
+			}
+		} else {
+			DBprintk(("[%d] pmd[%d] hw_pmd=0x%lx\n", task->pid, i, val));
+			/* not a counter, just save value as is */
+			task->thread.pmd[i] = val;
+		}
 	}
-	ia64_srlz_d();
+	/* 
+	 * indicates that context has been saved
+	 */
+	atomic_set(&ctx->ctx_last_cpu, -1);
+
 }
 
+
+
 /*
- * task is the newly created task
+ * task is the newly created task, pt_regs for new child
  */
 int
 pfm_inherit(struct task_struct *task, struct pt_regs *regs)
@@ -2174,25 +3419,29 @@
 	pfm_context_t *ctx = current->thread.pfm_context;
 	pfm_context_t *nctx;
 	struct thread_struct *th = &task->thread;
-	int i, cnum;
+	unsigned long m;
+	int i;
 
 	/*
-	 * bypass completely for system wide
+	 * make sure child cannot mess up the monitoring session
 	 */
-	if (pfs_info.pfs_sys_session) {
-		DBprintk((" enabling psr.pp for %d\n", task->pid));
-		ia64_psr(regs)->pp = pfs_info.pfs_pp;
-		return 0;
-	}
+	 ia64_psr(regs)->sp = 1;
+	 DBprintk(("enabling psr.sp for [%d]\n", task->pid));
+
+	 /*
+	  * remove any sampling buffer mapping from child user 
+	  * address space. Must be done for all cases of inheritance.
+	  */
+	 if (ctx->ctx_smpl_vaddr) pfm_remove_smpl_mapping(task);
 
 	/*
 	 * takes care of easiest case first
 	 */
 	if (CTX_INHERIT_MODE(ctx) == PFM_FL_INHERIT_NONE) {
-		DBprintk((" removing PFM context for %d\n", task->pid));
+		DBprintk(("removing PFM context for [%d]\n", task->pid));
 		task->thread.pfm_context     = NULL;
-		task->thread.pfm_must_block  = 0;
-		atomic_set(&task->thread.pfm_notifiers_check, 0);
+		task->thread.pfm_ovfl_block_reset  = 0;
+
 		/* copy_thread() clears IA64_THREAD_PM_VALID */
 		return 0;
 	}
@@ -2202,45 +3451,81 @@
 	/* copy content */
 	*nctx = *ctx;
 
+
 	if (CTX_INHERIT_MODE(ctx) == PFM_FL_INHERIT_ONCE) {
 		nctx->ctx_fl_inherit = PFM_FL_INHERIT_NONE;
-		atomic_set(&task->thread.pfm_notifiers_check, 0);
-		DBprintk((" downgrading to INHERIT_NONE for %d\n", task->pid));
-		pfs_info.pfs_proc_sessions++;
+		atomic_set(&nctx->ctx_last_cpu, -1);
+
+		/*
+		 * task is not yet visible in the tasklist, so we do 
+		 * not need to lock the newly created context.
+		 * However, we must grab the tasklist_lock to ensure
+		 * that the ctx_owner or ctx_notify_task do not disappear
+		 * while we increment their check counters.
+		 */
+		read_lock(&tasklist_lock);
+
+		if (nctx->ctx_notify_task) 
+			atomic_inc(&nctx->ctx_notify_task->thread.pfm_notifiers_check);
+
+		if (nctx->ctx_owner)
+			atomic_inc(&nctx->ctx_owner->thread.pfm_owners_check);
+
+		read_unlock(&tasklist_lock);
+
+		DBprintk(("downgrading to INHERIT_NONE for [%d]\n", task->pid));
+
+		LOCK_PFS();
+		pfm_sessions.pfs_task_sessions++;
+		UNLOCK_PFS();
 	}
 
 	/* initialize counters in new context */
-	for(i=0, cnum= PMU_FIRST_COUNTER; i < pmu_conf.max_counters; cnum++, i++) {
-		nctx->ctx_pmds[i].val = nctx->ctx_pmds[i].ival & ~pmu_conf.perf_ovfl_val;
-		th->pmd[cnum]	      = nctx->ctx_pmds[i].ival & pmu_conf.perf_ovfl_val;
+	m = pmu_conf.counter_pmds[0] >> PMU_FIRST_COUNTER;
+	for(i = PMU_FIRST_COUNTER ; m ; m>>=1, i++) {
+		if (m & 0x1) {
+			nctx->ctx_soft_pmds[i].val = nctx->ctx_soft_pmds[i].ival & ~pmu_conf.perf_ovfl_val;
+			th->pmd[i]	      	   = nctx->ctx_soft_pmds[i].ival & pmu_conf.perf_ovfl_val;
+		}
 
 	}
 	/* clear BTB index register */
 	th->pmd[16] = 0;
 
 	/* if sampling then increment number of users of buffer */
-	if (nctx->ctx_smpl_buf) {
-		atomic_inc(&nctx->ctx_smpl_buf->psb_refcnt);
+	if (nctx->ctx_psb) {
+
+		/*
+		 * XXX: nopt very pretty!
+		 */
+		LOCK_PSB(nctx->ctx_psb);
+		nctx->ctx_psb->psb_refcnt++;
+		UNLOCK_PSB(nctx->ctx_psb);
+		/*
+	 	 * remove any pointer to sampling buffer mapping
+	 	 */
+		nctx->ctx_smpl_vaddr = 0;
 	}
 
 	nctx->ctx_fl_frozen = 0;
-	nctx->ctx_ovfl_regs = 0;
+	nctx->ctx_ovfl_regs[0] = 0UL;
+
 	sema_init(&nctx->ctx_restart_sem, 0); /* reset this semaphore to locked */
 
 	/* clear pending notification */
-	th->pfm_must_block = 0;
+	th->pfm_ovfl_block_reset = 0;
 
 	/* link with new task */
-	th->pfm_context     = nctx;
+	th->pfm_context    = nctx;
 
-	DBprintk((" nctx=%p for process %d\n", (void *)nctx, task->pid));
+	DBprintk(("nctx=%p for process [%d]\n", (void *)nctx, task->pid));
 
 	/*
 	 * the copy_thread routine automatically clears
 	 * IA64_THREAD_PM_VALID, so we need to reenable it, if it was used by the caller
 	 */
 	if (current->thread.flags & IA64_THREAD_PM_VALID) {
-		DBprintk(("  setting PM_VALID for %d\n", task->pid));
+		DBprintk(("setting PM_VALID for [%d]\n", task->pid));
 		th->flags |= IA64_THREAD_PM_VALID;
 	}
 
@@ -2248,100 +3533,248 @@
 }
 
 /* 
- * called from release_thread(), at this point this task is not in the 
- * tasklist anymore
+ *
+ * We cannot touch any of the PMU registers at this point as we may
+ * not be running on the same CPU the task was last run on.  Therefore
+ * it is assumed that the PMU has been stopped appropriately in
+ * pfm_flush_regs() called from exit_thread(). 
+ *
+ * The function is called in the context of the parent via a release_thread()
+ * and wait4(). The task is not in the tasklist anymore.
  */
 void
 pfm_context_exit(struct task_struct *task)
 {
 	pfm_context_t *ctx = task->thread.pfm_context;
 
-	if (!ctx) {
-		DBprintk((" invalid context for %d\n", task->pid));
-		return;
-	}
+	/*
+	 * check sampling buffer
+	 */
+	if (ctx->ctx_psb) {
+		pfm_smpl_buffer_desc_t *psb = ctx->ctx_psb;
 
-	/* check is we have a sampling buffer attached */
-	if (ctx->ctx_smpl_buf) {
-		pfm_smpl_buffer_desc_t *psb = ctx->ctx_smpl_buf;
-
-		/* if only user left, then remove */
-		DBprintk((" [%d] [%d] psb->refcnt=%d\n", current->pid, task->pid, psb->psb_refcnt.counter));
-
-		if (atomic_dec_and_test(&psb->psb_refcnt) ) {
-			rvfree(psb->psb_hdr, psb->psb_size);
-			vfree(psb);
-			DBprintk((" [%d] cleaning [%d] sampling buffer\n", current->pid, task->pid ));
-		}
-	}
-	DBprintk((" [%d] cleaning [%d] pfm_context @%p\n", current->pid, task->pid, (void *)ctx));
-
-	/*
-	 * To avoid getting the notified task scan the entire process list
-	 * when it exits because it would have pfm_notifiers_check set, we 
-	 * decrease it by 1 to inform the task, that one less task is going
-	 * to send it notification. each new notifer increases this field by
-	 * 1 in pfm_context_create(). Of course, there is race condition between
-	 * decreasing the value and the notified task exiting. The danger comes
-	 * from the fact that we have a direct pointer to its task structure
-	 * thereby bypassing the tasklist. We must make sure that if we have 
-	 * notify_task!= NULL, the target task is still somewhat present. It may
-	 * already be detached from the tasklist but that's okay. Note that it is
-	 * okay if we 'miss the deadline' and the task scans the list for nothing,
-	 * it will affect performance but not correctness. The correctness is ensured
-	 * by using the notify_lock whic prevents the notify_task from changing on us.
-	 * Once holdhing this lock, if we see notify_task!= NULL, then it will stay like
+		LOCK_PSB(psb);
+
+		DBprintk(("sampling buffer from [%d] @%p size %ld vma_flag=0x%x\n",
+			task->pid,
+			psb->psb_hdr, psb->psb_size, psb->psb_flags));
+
+		/*
+		 * in the case where we are the last user, we may be able to free
+		 * the buffer
+		 */
+		psb->psb_refcnt--;
+
+		if (psb->psb_refcnt == 0) {
+
+			/*
+			 * The flag is cleared in pfm_vm_close(). which gets 
+			 * called from do_exit() via exit_mm(). 
+			 * By the time we come here, the task has no more mm context.
+			 *
+			 * We can only free the psb and buffer here after the vm area
+			 * describing the buffer has been removed. This normally happens 
+			 * as part of do_exit() but the entire mm context is ONLY removed
+			 * once its reference counts goes to zero. This is typically
+			 * the case except for multi-threaded (several tasks) processes.
+			 *
+			 * See pfm_vm_close() and pfm_cleanup_smpl_buf() for more details.
+			 */
+			if ((psb->psb_flags & PFM_PSB_VMA) == 0) {
+
+				DBprintk(("cleaning sampling buffer from [%d] @%p size %ld\n",
+					task->pid,
+					psb->psb_hdr, psb->psb_size));
+
+				/* 
+				 * free the buffer and psb 
+				 */
+				pfm_rvfree(psb->psb_hdr, psb->psb_size);
+				kfree(psb);
+				psb = NULL;
+			} 
+		} 
+		/* psb may have been deleted */
+		if (psb) UNLOCK_PSB(psb);
+	} 
+
+	DBprintk(("cleaning [%d] pfm_context @%p notify_task=%p check=%d mm=%p\n", 
+		task->pid, ctx, 
+		ctx->ctx_notify_task, 
+		atomic_read(&task->thread.pfm_notifiers_check), task->mm));
+
+	/*
+	 * To avoid getting the notified task or owner task scan the entire process 
+	 * list when they exit, we decrement notifiers_check and owners_check respectively.
+	 *
+	 * Of course, there is race condition between decreasing the value and the 
+	 * task exiting. The danger comes from the fact that, in both cases, we have a 
+	 * direct pointer to a task structure thereby bypassing the tasklist. 
+	 * We must make sure that, if we have task!= NULL, the target task is still 
+	 * present and is identical to the initial task specified 
+	 * during pfm_create_context(). It may already be detached from the tasklist but 
+	 * that's okay. Note that it is okay if we miss the deadline and the task scans 
+	 * the list for nothing, it will affect performance but not correctness. 
+	 * The correctness is ensured by using the ctx_lock which prevents the 
+	 * notify_task from changing the fields in our context.
+	 * Once holdhing this lock, if we see task!= NULL, then it will stay like
 	 * that until we release the lock. If it is NULL already then we came too late.
 	 */
-	spin_lock(&ctx->ctx_notify_lock);
+	LOCK_CTX(ctx);
 
-	if (ctx->ctx_notify_task) {
-		DBprintk((" [%d] [%d] atomic_sub on [%d] notifiers=%u\n", current->pid, task->pid,
-					ctx->ctx_notify_task->pid, 
-					atomic_read(&ctx->ctx_notify_task->thread.pfm_notifiers_check)));
+	if (ctx->ctx_notify_task != NULL) {
+		DBprintk(("[%d], [%d] atomic_sub on [%d] notifiers=%u\n", current->pid,
+			task->pid,
+			ctx->ctx_notify_task->pid, 
+			atomic_read(&ctx->ctx_notify_task->thread.pfm_notifiers_check)));
+
+		atomic_dec(&ctx->ctx_notify_task->thread.pfm_notifiers_check);
+	}
+
+	if (ctx->ctx_owner != NULL) {
+		DBprintk(("[%d], [%d] atomic_sub on [%d] owners=%u\n", 
+			 current->pid, 
+			 task->pid,
+			 ctx->ctx_owner->pid, 
+			 atomic_read(&ctx->ctx_owner->thread.pfm_owners_check)));
 
-		atomic_sub(1, &ctx->ctx_notify_task->thread.pfm_notifiers_check);
+		atomic_dec(&ctx->ctx_owner->thread.pfm_owners_check);
 	}
 
-	spin_unlock(&ctx->ctx_notify_lock);
+	UNLOCK_CTX(ctx);
+
+	LOCK_PFS();
 
 	if (ctx->ctx_fl_system) {
-		/*
-		 * if included interrupts (true by default), then reset
-		 * to get default value
-		 */
-		if (ctx->ctx_fl_exclintr == 0) {
-			/*
-			 * reload kernel default DCR value
-			 */
-			ia64_set_dcr(pfs_info.pfs_dfl_dcr);
-			DBprintk((" restored dcr to 0x%lx\n", pfs_info.pfs_dfl_dcr));
+
+		pfm_sessions.pfs_sys_session[ctx->ctx_cpu] = NULL;
+		pfm_sessions.pfs_sys_sessions--;
+		DBprintk(("freeing syswide session on CPU%ld\n", ctx->ctx_cpu));
+		/* update perfmon debug register counter */
+		if (ctx->ctx_fl_using_dbreg) {
+			if (pfm_sessions.pfs_sys_use_dbregs == 0) {
+				printk("perfmon: invalid release for [%d] sys_use_dbregs=0\n", task->pid);
+			} else
+				pfm_sessions.pfs_sys_use_dbregs--;
 		}
-		/* 
-		 * free system wide session slot
-		 */
-		pfs_info.pfs_sys_session = 0;
+
+		/*
+	 	 * remove any CPU pinning
+	 	 */
+		set_cpus_allowed(task, ctx->ctx_saved_cpus_allowed);
 	} else {
-		pfs_info.pfs_proc_sessions--;
+		pfm_sessions.pfs_task_sessions--;
 	}
+	UNLOCK_PFS();
 
 	pfm_context_free(ctx);
 	/* 
 	 *  clean pfm state in thread structure,
 	 */
-	task->thread.pfm_context    = NULL;
-	task->thread.pfm_must_block = 0;
+	task->thread.pfm_context          = NULL;
+	task->thread.pfm_ovfl_block_reset = 0;
+
 	/* pfm_notifiers is cleaned in pfm_cleanup_notifiers() */
+}
+
+/*
+ * function invoked from release_thread when pfm_smpl_buf_list is not NULL
+ */
+int
+pfm_cleanup_smpl_buf(struct task_struct *task)
+{
+	pfm_smpl_buffer_desc_t *tmp, *psb = task->thread.pfm_smpl_buf_list;
+
+	if (psb == NULL) {
+		printk("perfmon: psb is null in [%d]\n", current->pid);
+		return -1;
+	}
+	/*
+	 * Walk through the list and free the sampling buffer and psb
+	 */
+	while (psb) {
+		DBprintk(("[%d] freeing smpl @%p size %ld\n", current->pid, psb->psb_hdr, psb->psb_size));
+
+		pfm_rvfree(psb->psb_hdr, psb->psb_size);
+		tmp = psb->psb_next;
+		kfree(psb);
+		psb = tmp;
+	}
+
+	/* just in case */
+	task->thread.pfm_smpl_buf_list = NULL;
+
+	return 0;
+}
+
+/*
+ * function invoked from release_thread to make sure that the ctx_owner field does not
+ * point to an unexisting task.
+ */
+void
+pfm_cleanup_owners(struct task_struct *task)
+{
+	struct task_struct *p;
+	pfm_context_t *ctx;
+
+	DBprintk(("called by [%d] for [%d]\n", current->pid, task->pid));
+
+	read_lock(&tasklist_lock);
+
+	for_each_task(p) {
+		/*
+		 * It is safe to do the 2-step test here, because thread.ctx
+		 * is cleaned up only in release_thread() and at that point
+		 * the task has been detached from the tasklist which is an
+		 * operation which uses the write_lock() on the tasklist_lock
+		 * so it cannot run concurrently to this loop. So we have the
+		 * guarantee that if we find p and it has a perfmon ctx then
+		 * it is going to stay like this for the entire execution of this
+		 * loop.
+		 */
+		ctx = p->thread.pfm_context;
+
+		//DBprintk(("[%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx));
+
+		if (ctx && ctx->ctx_owner == task) {
+			DBprintk(("trying for owner [%d] in [%d]\n", task->pid, p->pid));
+			/*
+			 * the spinlock is required to take care of a race condition
+			 * with the send_sig_info() call. We must make sure that 
+			 * either the send_sig_info() completes using a valid task,
+			 * or the notify_task is cleared before the send_sig_info()
+			 * can pick up a stale value. Note that by the time this
+			 * function is executed the 'task' is already detached from the
+			 * tasklist. The problem is that the notifiers have a direct
+			 * pointer to it. It is okay to send a signal to a task in this
+			 * stage, it simply will have no effect. But it is better than sending
+			 * to a completely destroyed task or worse to a new task using the same
+			 * task_struct address.
+			 */
+			LOCK_CTX(ctx);
+
+			ctx->ctx_owner = NULL;
 
+			UNLOCK_CTX(ctx);
+
+			DBprintk(("done for notifier [%d] in [%d]\n", task->pid, p->pid));
+		}
+	}
+	read_unlock(&tasklist_lock);
 }
 
+
+/*
+ * function called from release_thread to make sure that the ctx_notify_task is not pointing
+ * to an unexisting task
+ */
 void
 pfm_cleanup_notifiers(struct task_struct *task)
 {
 	struct task_struct *p;
 	pfm_context_t *ctx;
 
-	DBprintk((" [%d] called\n", task->pid));
+	DBprintk(("called by [%d] for [%d]\n", current->pid, task->pid));
 
 	read_lock(&tasklist_lock);
 
@@ -2358,10 +3791,10 @@
 		 */
 		ctx = p->thread.pfm_context;
 
-		DBprintk((" [%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx));
+		//DBprintk(("[%d] scanning task [%d] ctx=%p\n", task->pid, p->pid, ctx));
 
 		if (ctx && ctx->ctx_notify_task == task) {
-			DBprintk((" trying for notifier %d in %d\n", task->pid, p->pid));
+			DBprintk(("trying for notifier [%d] in [%d]\n", task->pid, p->pid));
 			/*
 			 * the spinlock is required to take care of a race condition
 			 * with the send_sig_info() call. We must make sure that 
@@ -2375,23 +3808,146 @@
 			 * to a completely destroyed task or worse to a new task using the same
 			 * task_struct address.
 			 */
-			spin_lock(&ctx->ctx_notify_lock);
+			LOCK_CTX(ctx);
 
 			ctx->ctx_notify_task = NULL;
 
-			spin_unlock(&ctx->ctx_notify_lock);
+			UNLOCK_CTX(ctx);
 
-			DBprintk((" done for notifier %d in %d\n", task->pid, p->pid));
+			DBprintk(("done for notifier [%d] in [%d]\n", task->pid, p->pid));
 		}
 	}
 	read_unlock(&tasklist_lock);
+}
+
+static struct irqaction perfmon_irqaction = {
+	handler:	perfmon_interrupt,
+	flags:		SA_INTERRUPT,
+	name:		"perfmon"
+};
+
+
+static void
+pfm_pmu_snapshot(void)
+{
+	int i;
+
+	for (i=0; i < IA64_NUM_PMC_REGS; i++) {
+		if (i >= pmu_conf.num_pmcs) break;
+		if (PMC_IS_IMPL(i)) reset_pmcs[i] = ia64_get_pmc(i);
+	}
+}
+
+/*
+ * perfmon initialization routine, called from the initcall() table
+ */
+int __init
+perfmon_init (void)
+{
+	pal_perf_mon_info_u_t pm_info;
+	s64 status;
+
+	register_percpu_irq(IA64_PERFMON_VECTOR, &perfmon_irqaction);
+
+	ia64_set_pmv(IA64_PERFMON_VECTOR);
+	ia64_srlz_d();
+
+	pmu_conf.pfm_is_disabled = 1;
+
+	printk("perfmon: version %u.%u (sampling format v%u.%u) IRQ %u\n", 
+		PFM_VERSION_MAJ, 
+		PFM_VERSION_MIN, 
+		PFM_SMPL_VERSION_MAJ, 
+		PFM_SMPL_VERSION_MIN, 
+		IA64_PERFMON_VECTOR);
+
+	if ((status=ia64_pal_perf_mon_info(pmu_conf.impl_regs, &pm_info)) != 0) {
+		printk("perfmon: PAL call failed (%ld), perfmon disabled\n", status);
+		return -1;
+	}
+
+	pmu_conf.perf_ovfl_val = (1UL << pm_info.pal_perf_mon_info_s.width) - 1;
+	pmu_conf.max_counters  = pm_info.pal_perf_mon_info_s.generic;
+	pmu_conf.num_pmcs      = find_num_pm_regs(pmu_conf.impl_regs);
+	pmu_conf.num_pmds      = find_num_pm_regs(&pmu_conf.impl_regs[4]);
+
+	printk("perfmon: %u bits counters\n", pm_info.pal_perf_mon_info_s.width);
+
+	printk("perfmon: %lu PMC/PMD pairs, %lu PMCs, %lu PMDs\n", 
+	       pmu_conf.max_counters, pmu_conf.num_pmcs, pmu_conf.num_pmds);
+
+	/* sanity check */
+	if (pmu_conf.num_pmds >= IA64_NUM_PMD_REGS || pmu_conf.num_pmcs >= IA64_NUM_PMC_REGS) {
+		printk(KERN_ERR "perfmon: not enough pmc/pmd, perfmon is DISABLED\n");
+		return -1; /* no need to continue anyway */
+	}
+
+	if (ia64_pal_debug_info(&pmu_conf.num_ibrs, &pmu_conf.num_dbrs)) {
+		printk(KERN_WARNING "perfmon: unable to get number of debug registers\n");
+		pmu_conf.num_ibrs = pmu_conf.num_dbrs = 0;
+	}
+	/* PAL reports the number of pairs */
+	pmu_conf.num_ibrs <<=1;
+	pmu_conf.num_dbrs <<=1;
+
+	/*
+	 * take a snapshot of all PMU registers. PAL is supposed
+	 * to configure them with stable/safe values, i.e., not
+	 * capturing anything.
+	 * We take a snapshot now, before we make any modifications. This
+	 * will become our master copy. Then we will reuse the snapshot
+	 * to reset the PMU in pfm_enable(). Using this technique, perfmon
+	 * does NOT have to know about the specific values to program for
+	 * the PMC/PMD. The safe values may be different from one CPU model to
+	 * the other.
+	 */
+	pfm_pmu_snapshot();
+
+	/* 
+	 * list the pmc registers used to control monitors 
+	 * XXX: unfortunately this information is not provided by PAL
+	 *
+	 * We start with the architected minimum and then refine for each CPU model
+	 */
+	pmu_conf.monitor_pmcs[0] = PMM(4)|PMM(5)|PMM(6)|PMM(7);
+
+	/*
+	 * architected counters
+	 */
+	pmu_conf.counter_pmds[0] |= PMM(4)|PMM(5)|PMM(6)|PMM(7);
 
+#ifdef CONFIG_ITANIUM
+	pmu_conf.monitor_pmcs[0] |= PMM(10)|PMM(11)|PMM(12);
+	/* Itanium does not add more counters */
+#endif
+	/* we are all set */
+	pmu_conf.pfm_is_disabled = 0;
+
+	/*
+	 * for now here for debug purposes
+	 */
+	perfmon_dir = create_proc_read_entry ("perfmon", 0, 0, perfmon_read_entry, NULL);
+
+	spin_lock_init(&pfm_sessions.pfs_lock);
+
+	return 0;
+}
+
+__initcall(perfmon_init);
+
+void
+perfmon_init_percpu (void)
+{
+	ia64_set_pmv(IA64_PERFMON_VECTOR);
+	ia64_srlz_d();
 }
 
+
 #else /* !CONFIG_PERFMON */
 
 asmlinkage int
-sys_perfmonctl (int pid, int cmd, int flags, perfmon_req_t *req, int count, long arg6, long arg7, long arg8, long stack)
+sys_perfmonctl (int pid, int cmd, void *req, int count, long arg5, long arg6, 
+		long arg7, long arg8, long stack)
 {
 	return -ENOSYS;
 }
diff -Nru a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
--- a/arch/ia64/kernel/process.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/process.c	Fri Mar 15 17:51:03 2002
@@ -1,8 +1,8 @@
 /*
  * Architecture-specific setup.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #define __KERNEL_SYSCALLS__	/* see <asm/unistd.h> */
 #include <linux/config.h>
@@ -12,14 +12,17 @@
 #include <linux/errno.h>
 #include <linux/kernel.h>
 #include <linux/mm.h>
+#include <linux/personality.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/smp_lock.h>
 #include <linux/stddef.h>
+#include <linux/thread_info.h>
 #include <linux/unistd.h>
 
 #include <asm/delay.h>
 #include <asm/efi.h>
+#include <asm/elf.h>
 #include <asm/perfmon.h>
 #include <asm/pgtable.h>
 #include <asm/processor.h>
@@ -28,6 +31,16 @@
 #include <asm/unwind.h>
 #include <asm/user.h>
 
+#ifdef CONFIG_IA64_SGI_SN
+#include <asm/sn/idle.h>
+#endif
+
+#ifdef CONFIG_PERFMON
+# include <asm/perfmon.h>
+#endif
+
+#include "sigframe.h"
+
 static void
 do_show_stack (struct unw_frame_info *info, void *arg)
 {
@@ -46,6 +59,15 @@
 }
 
 void
+show_trace_task (struct task_struct *task)
+{
+	struct unw_frame_info info;
+
+	unw_init_from_blocked_task(&info, task);
+	do_show_stack(&info, 0);
+}
+
+void
 show_stack (struct task_struct *task)
 {
 	if (!task)
@@ -90,8 +112,8 @@
 	printk("r26 : %016lx r27 : %016lx r28 : %016lx\n", regs->r26, regs->r27, regs->r28);
 	printk("r29 : %016lx r30 : %016lx r31 : %016lx\n", regs->r29, regs->r30, regs->r31);
 
-	/* print the stacked registers if cr.ifs is valid: */
-	if (regs->cr_ifs & 0x8000000000000000) {
+	if (user_mode(regs)) {
+		/* print the stacked registers */
 		unsigned long val, sof, *bsp, ndirty;
 		int i, is_nat = 0;
 
@@ -103,32 +125,61 @@
 			printk("r%-3u:%c%016lx%s", 32 + i, is_nat ? '*' : ' ', val,
 			       ((i == sof - 1) || (i % 3) == 2) ? "\n" : " ");
 		}
-	}
-	if (!user_mode(regs))
+	} else
 		show_stack(0);
 }
 
+void
+do_notify_resume_user (sigset_t *oldset, struct sigscratch *scr, long in_syscall)
+{
+#ifdef CONFIG_PERFMON
+	if (current->thread.pfm_ovfl_block_reset)
+		pfm_ovfl_block_reset();
+#endif
+
+	/* deal with pending signal delivery */
+	if (test_thread_flag(TIF_SIGPENDING))
+		ia64_do_signal(oldset, scr, in_syscall);
+}
+
+/*
+ * We use this if we don't have any better idle routine..
+ */
+static void
+default_idle (void)
+{
+	/* may want to do PAL_LIGHT_HALT here... */
+}
+
 void __attribute__((noreturn))
 cpu_idle (void *unused)
 {
 	/* endless idle loop with no priority at all */
-	init_idle();
-	current->nice = 20;
-
 	while (1) {
 #ifdef CONFIG_SMP
 		if (!need_resched())
 			min_xtp();
 #endif
-		while (!need_resched())
-			continue;
+
+		while (!need_resched()) {
+#ifdef CONFIG_IA64_SGI_SN
+			snidle();
+#endif
+			if (pm_idle)
+				(*pm_idle)();
+			else
+				default_idle();
+		}
+
+#ifdef CONFIG_IA64_SGI_SN
+		snidleoff();
+#endif
+
 #ifdef CONFIG_SMP
 		normal_xtp();
 #endif
 		schedule();
 		check_pgt_cache();
-		if (pm_idle)
-			(*pm_idle)();
 	}
 }
 
@@ -137,10 +188,17 @@
 {
 	if ((task->thread.flags & IA64_THREAD_DBG_VALID) != 0)
 		ia64_save_debug_regs(&task->thread.dbr[0]);
+
 #ifdef CONFIG_PERFMON
 	if ((task->thread.flags & IA64_THREAD_PM_VALID) != 0)
 		pfm_save_regs(task);
+
+# ifdef CONFIG_SMP
+	if (local_cpu_data->pfm_syst_wide)
+		pfm_syst_wide_update_task(task, 0);
+# endif
 #endif
+
 	if (IS_IA32_PROCESS(ia64_task_regs(task)))
 		ia32_save_state(task);
 }
@@ -150,10 +208,16 @@
 {
 	if ((task->thread.flags & IA64_THREAD_DBG_VALID) != 0)
 		ia64_load_debug_regs(&task->thread.dbr[0]);
+
 #ifdef CONFIG_PERFMON
 	if ((task->thread.flags & IA64_THREAD_PM_VALID) != 0)
 		pfm_load_regs(task);
+
+# ifdef CONFIG_SMP
+	if (local_cpu_data->pfm_syst_wide) pfm_syst_wide_update_task(task, 1);
+# endif
 #endif
+
 	if (IS_IA32_PROCESS(ia64_task_regs(task)))
 		ia32_load_state(task);
 }
@@ -233,7 +297,7 @@
 
 	if (user_mode(child_ptregs)) {
 		if (user_stack_base) {
-			child_ptregs->r12 = user_stack_base + user_stack_size;
+			child_ptregs->r12 = user_stack_base + user_stack_size - 16;
 			child_ptregs->ar_bspstore = user_stack_base;
 			child_ptregs->ar_rnat = 0;
 			child_ptregs->loadrs = 0;
@@ -286,9 +350,15 @@
 	if (IS_IA32_PROCESS(ia64_task_regs(current)))
 		ia32_save_state(p);
 #endif
+
 #ifdef CONFIG_PERFMON
-	if (p->thread.pfm_context)
-		retval = pfm_inherit(p, child_ptregs);
+	/*
+	 * reset notifiers and owner check (may not have a perfmon context)
+	 */
+	atomic_set(&p->thread.pfm_notifiers_check, 0);
+	atomic_set(&p->thread.pfm_owners_check, 0);
+
+	if (current->thread.pfm_context) retval = pfm_inherit(p, child_ptregs);
 #endif
 	return retval;
 }
@@ -412,6 +482,16 @@
 	return error;
 }
 
+void
+ia64_set_personality (struct elf64_hdr *elf_ex, int ibcs2_interpreter)
+{
+	set_personality(PER_LINUX);
+	if (elf_ex->e_flags & EF_IA_64_LINUX_EXECUTABLE_STACK)
+		current->thread.flags |= IA64_THREAD_XSTACK;
+	else
+		current->thread.flags &= ~IA64_THREAD_XSTACK;
+}
+
 pid_t
 kernel_thread (int (*fn)(void *), void *arg, unsigned long flags)
 {
@@ -443,15 +523,15 @@
 
 #ifdef CONFIG_PERFMON
 /*
- * By the time we get here, the task is detached from the tasklist. This is important
- * because it means that no other tasks can ever find it as a notifiied task, therfore
- * there is no race condition between this code and let's say a pfm_context_create().
- * Conversely, the pfm_cleanup_notifiers() cannot try to access a task's pfm context if
- * this other task is in the middle of its own pfm_context_exit() because it would alreayd
- * be out of the task list. Note that this case is very unlikely between a direct child
- * and its parents (if it is the notified process) because of the way the exit is notified
- * via SIGCHLD.
+ * by the time we get here, the task is detached from the tasklist. This is important
+ * because it means that no other tasks can ever find it as a notified task, therfore there
+ * is no race condition between this code and let's say a pfm_context_create().
+ * Conversely, the pfm_cleanup_notifiers() cannot try to access a task's pfm context if this
+ * other task is in the middle of its own pfm_context_exit() because it would already be out of
+ * the task list. Note that this case is very unlikely between a direct child and its parents
+ * (if it is the notified process) because of the way the exit is notified via SIGCHLD.
  */
+
 void
 release_thread (struct task_struct *task)
 {
@@ -460,6 +540,12 @@
 
 	if (atomic_read(&task->thread.pfm_notifiers_check) > 0)
 		pfm_cleanup_notifiers(task);
+
+	if (atomic_read(&task->thread.pfm_owners_check) > 0)
+		pfm_cleanup_owners(task);
+
+	if (task->thread.pfm_smpl_buf_list)
+		pfm_cleanup_smpl_buf(task);
 }
 #endif
 
@@ -475,21 +561,13 @@
 		ia64_set_fpu_owner(0);
 #endif
 #ifdef CONFIG_PERFMON
-       /* stop monitoring */
-	if ((current->thread.flags & IA64_THREAD_PM_VALID) != 0) {
-		/*
-		 * we cannot rely on switch_to() to save the PMU
-		 * context for the last time. There is a possible race
-		 * condition in SMP mode between the child and the
-		 * parent.  by explicitly saving the PMU context here
-		 * we garantee no race.  this call we also stop
-		 * monitoring
-		 */
+       /* if needed, stop monitoring and flush state to perfmon context */
+	if (current->thread.pfm_context) 
 		pfm_flush_regs(current);
-		/*
-		 * make sure that switch_to() will not save context again
-		 */
-		current->thread.flags &= ~IA64_THREAD_PM_VALID;
+
+	/* free debug register resources */
+	if ((current->thread.flags & IA64_THREAD_DBG_VALID) != 0) {
+		pfm_release_debug_registers(current);
 	}
 #endif
 }
@@ -570,4 +648,30 @@
 	if (pm_power_off)
 		pm_power_off();
 	machine_halt();
+}
+
+void __init
+init_task_struct_cache (void)
+{
+}
+
+struct task_struct *
+dup_task_struct(struct task_struct *orig)
+{
+	struct task_struct *tsk;
+
+	tsk = __get_free_pages(GFP_KERNEL, KERNEL_STACK_SIZE_ORDER);
+	if (!tsk)
+		return NULL;
+
+	memcpy(tsk, orig, sizeof(struct task_struct) + sizeof(struct thread_info));
+	tsk->thread_info = (struct thread_info *) ((char *) tsk + IA64_TASK_SIZE);
+	atomic_set(&tsk->usage, 1);
+	return tsk;
+}
+
+void
+__put_task_struct (struct task_struct *tsk)
+{
+	free_pages((unsigned long) tsk, KERNEL_STACK_SIZE_ORDER);
 }
diff -Nru a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c
--- a/arch/ia64/kernel/ptrace.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/ptrace.c	Fri Mar 15 17:51:03 2002
@@ -23,6 +23,9 @@
 #include <asm/system.h>
 #include <asm/uaccess.h>
 #include <asm/unwind.h>
+#ifdef CONFIG_PERFMON
+#include <asm/perfmon.h>
+#endif
 
 /*
  * Bits in the PSR that we allow ptrace() to change:
@@ -755,11 +758,6 @@
 	} else {
 		/* access debug registers */
 
-		if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
-			child->thread.flags |= IA64_THREAD_DBG_VALID;
-			memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
-			memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
-		}
 		if (addr >= PT_IBR) {
 			regnum = (addr - PT_IBR) >> 3;
 			ptr = &child->thread.ibr[0];
@@ -772,6 +770,31 @@
 			dprintk("ptrace: rejecting access to register address 0x%lx\n", addr);
 			return -1;
 		}
+#ifdef CONFIG_PERFMON
+		/* 
+		 * Check if debug registers are used 
+		 * by perfmon. This test must be done once we know that we can
+		 * do the operation, i.e. the arguments are all valid, but before
+		 * we start modifying the state.
+		 *
+		 * Perfmon needs to keep a count of how many processes are
+		 * trying to modify the debug registers for system wide monitoring
+		 * sessions.
+		 *
+		 * We also include read access here, because they may cause 
+		 * the PMU-installed debug register state (dbr[], ibr[]) to
+		 * be reset. The two arrays are also used by perfmon, but
+		 * we do not use IA64_THREAD_DBG_VALID. The registers are restored
+		 * by the PMU context switch code.
+		 */
+		if (pfm_use_debug_registers(child)) return -1;
+#endif
+
+		if (!(child->thread.flags & IA64_THREAD_DBG_VALID)) {
+			child->thread.flags |= IA64_THREAD_DBG_VALID;
+			memset(child->thread.dbr, 0, sizeof(child->thread.dbr));
+			memset(child->thread.ibr, 0, sizeof(child->thread.ibr));
+		}
 
 		ptr += regnum;
 
@@ -789,6 +812,260 @@
 	return 0;
 }
 
+static long
+ptrace_getregs (struct task_struct *child, struct pt_all_user_regs *ppr)
+{
+	struct switch_stack *sw;
+	struct pt_regs *pt;
+	long ret, retval;
+	struct unw_frame_info info;
+	char nat = 0;
+	int i;
+
+	retval = verify_area(VERIFY_WRITE, ppr, sizeof(struct pt_all_user_regs));
+	if (retval != 0) {
+		return -EIO;
+	}
+
+	pt = ia64_task_regs(child);
+	sw = (struct switch_stack *) (child->thread.ksp + 16);
+	unw_init_from_blocked_task(&info, child);
+	if (unw_unwind_to_user(&info) < 0) {
+		return -EIO;
+	}
+
+	if (((unsigned long) ppr & 0x7) != 0) {
+		dprintk("ptrace:unaligned register address %p\n", ppr);
+		return -EIO;
+	}
+
+	retval = 0;
+
+	/* control regs */
+
+	retval |= __put_user(pt->cr_iip, &ppr->cr_iip);
+	retval |= access_uarea(child, PT_CR_IPSR, &ppr->cr_ipsr, 0);
+
+	/* app regs */
+
+	retval |= __put_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
+	retval |= __put_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
+	retval |= __put_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
+	retval |= __put_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
+	retval |= __put_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
+	retval |= __put_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
+
+	retval |= access_uarea(child, PT_AR_EC, &ppr->ar[PT_AUR_EC], 0);
+	retval |= access_uarea(child, PT_AR_LC, &ppr->ar[PT_AUR_LC], 0);
+	retval |= access_uarea(child, PT_AR_RNAT, &ppr->ar[PT_AUR_RNAT], 0);
+	retval |= access_uarea(child, PT_AR_BSP, &ppr->ar[PT_AUR_BSP], 0);
+	retval |= access_uarea(child, PT_CFM, &ppr->cfm, 0);
+
+	/* gr1-gr3 */
+
+	retval |= __copy_to_user(&ppr->gr[1], &pt->r1, sizeof(long) * 3);
+
+	/* gr4-gr7 */
+
+	for (i = 4; i < 8; i++) {
+		retval |= unw_access_gr(&info, i, &ppr->gr[i], &nat, 0);
+	}
+
+	/* gr8-gr11 */
+
+	retval |= __copy_to_user(&ppr->gr[8], &pt->r8, sizeof(long) * 4);
+
+	/* gr12-gr15 */
+
+	retval |= __copy_to_user(&ppr->gr[12], &pt->r12, sizeof(long) * 4);
+
+	/* gr16-gr31 */
+
+	retval |= __copy_to_user(&ppr->gr[16], &pt->r16, sizeof(long) * 16);
+
+	/* b0 */
+
+	retval |= __put_user(pt->b0, &ppr->br[0]);
+
+	/* b1-b5 */
+
+	for (i = 1; i < 6; i++) {
+		retval |= unw_access_br(&info, i, &ppr->br[i], 0);
+	}
+
+	/* b6-b7 */
+
+	retval |= __put_user(pt->b6, &ppr->br[6]);
+	retval |= __put_user(pt->b7, &ppr->br[7]);
+
+	/* fr2-fr5 */
+
+	for (i = 2; i < 6; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 0);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 0);
+	}
+
+	/* fr6-fr9 */
+
+	retval |= __copy_to_user(&ppr->fr[6], &pt->f6, sizeof(struct ia64_fpreg) * 4);
+
+	/* fp scratch regs(10-15) */
+
+	retval |= __copy_to_user(&ppr->fr[10], &sw->f10, sizeof(struct ia64_fpreg) * 6);
+
+	/* fr16-fr31 */
+
+	for (i = 16; i < 32; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 0);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 0);
+	}
+
+	/* fph */
+
+	ia64_flush_fph(child);
+	retval |= __copy_to_user(&ppr->fr[32], &child->thread.fph, sizeof(ppr->fr[32]) * 96);
+
+	/*  preds */
+
+	retval |= __put_user(pt->pr, &ppr->pr);
+
+	/* nat bits */
+
+	retval |= access_uarea(child, PT_NAT_BITS, &ppr->nat, 0);
+
+	ret = retval ? -EIO : 0;
+	return ret;
+}
+
+static long
+ptrace_setregs (struct task_struct *child, struct pt_all_user_regs *ppr)
+{
+	struct switch_stack *sw;
+	struct pt_regs *pt;
+	long ret, retval;
+	struct unw_frame_info info;
+	char nat = 0;
+	int i;
+
+	retval = verify_area(VERIFY_READ, ppr, sizeof(struct pt_all_user_regs));
+	if (retval != 0) {
+		return -EIO;
+	}
+
+	pt = ia64_task_regs(child);
+	sw = (struct switch_stack *) (child->thread.ksp + 16);
+	unw_init_from_blocked_task(&info, child);
+	if (unw_unwind_to_user(&info) < 0) {
+		return -EIO;
+	}
+
+	if (((unsigned long) ppr & 0x7) != 0) {
+		dprintk("ptrace:unaligned register address %p\n", ppr);
+		return -EIO;
+	}
+
+	retval = 0;
+
+	/* control regs */
+
+	retval |= __get_user(pt->cr_iip, &ppr->cr_iip);
+	retval |= access_uarea(child, PT_CR_IPSR, &ppr->cr_ipsr, 1);
+
+	/* app regs */
+
+	retval |= __get_user(pt->ar_pfs, &ppr->ar[PT_AUR_PFS]);
+	retval |= __get_user(pt->ar_rsc, &ppr->ar[PT_AUR_RSC]);
+	retval |= __get_user(pt->ar_bspstore, &ppr->ar[PT_AUR_BSPSTORE]);
+	retval |= __get_user(pt->ar_unat, &ppr->ar[PT_AUR_UNAT]);
+	retval |= __get_user(pt->ar_ccv, &ppr->ar[PT_AUR_CCV]);
+	retval |= __get_user(pt->ar_fpsr, &ppr->ar[PT_AUR_FPSR]);
+
+	retval |= access_uarea(child, PT_AR_EC, &ppr->ar[PT_AUR_EC], 1);
+	retval |= access_uarea(child, PT_AR_LC, &ppr->ar[PT_AUR_LC], 1);
+	retval |= access_uarea(child, PT_AR_RNAT, &ppr->ar[PT_AUR_RNAT], 1);
+	retval |= access_uarea(child, PT_AR_BSP, &ppr->ar[PT_AUR_BSP], 1);
+	retval |= access_uarea(child, PT_CFM, &ppr->cfm, 1);
+
+	/* gr1-gr3 */
+
+	retval |= __copy_from_user(&pt->r1, &ppr->gr[1], sizeof(long) * 3);
+
+	/* gr4-gr7 */
+
+	for (i = 4; i < 8; i++) {
+		long ret = unw_get_gr(&info, i, &ppr->gr[i], &nat);
+		if (ret < 0) {
+			return ret;
+		}
+		retval |= unw_access_gr(&info, i, &ppr->gr[i], &nat, 1);
+	}
+
+	/* gr8-gr11 */
+
+	retval |= __copy_from_user(&pt->r8, &ppr->gr[8], sizeof(long) * 4);
+
+	/* gr12-gr15 */
+
+	retval |= __copy_from_user(&pt->r12, &ppr->gr[12], sizeof(long) * 4);
+
+	/* gr16-gr31 */
+
+	retval |= __copy_from_user(&pt->r16, &ppr->gr[16], sizeof(long) * 16);
+
+	/* b0 */
+
+	retval |= __get_user(pt->b0, &ppr->br[0]);
+
+	/* b1-b5 */
+
+	for (i = 1; i < 6; i++) {
+		retval |= unw_access_br(&info, i, &ppr->br[i], 1);
+	}
+
+	/* b6-b7 */
+
+	retval |= __get_user(pt->b6, &ppr->br[6]);
+	retval |= __get_user(pt->b7, &ppr->br[7]);
+
+	/* fr2-fr5 */
+
+	for (i = 2; i < 6; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 1);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 1);
+	}
+
+	/* fr6-fr9 */
+
+	retval |= __copy_from_user(&pt->f6, &ppr->fr[6], sizeof(ppr->fr[6]) * 4);
+
+	/* fp scratch regs(10-15) */
+
+	retval |= __copy_from_user(&sw->f10, &ppr->fr[10], sizeof(ppr->fr[10]) * 6);
+
+	/* fr16-fr31 */
+
+	for (i = 16; i < 32; i++) {
+		retval |= access_fr(&info, i, 0, (unsigned long *) &ppr->fr[i], 1);
+		retval |= access_fr(&info, i, 1, (unsigned long *) &ppr->fr[i] + 1, 1);
+	}
+
+	/* fph */
+
+	ia64_sync_fph(child);
+	retval |= __copy_from_user(&child->thread.fph, &ppr->fr[32], sizeof(ppr->fr[32]) * 96);
+
+	/* preds */
+
+	retval |= __get_user(pt->pr, &ppr->pr);
+
+	/* nat bits */
+
+	retval |= access_uarea(child, PT_NAT_BITS, &ppr->nat, 1);
+
+	ret = retval ? -EIO : 0;
+	return ret;
+}
+
 /*
  * Called by kernel/ptrace.c when detaching..
  *
@@ -916,9 +1193,9 @@
 		if (data > _NSIG)
 			goto out_tsk;
 		if (request == PTRACE_SYSCALL)
-			child->ptrace |= PT_TRACESYS;
+			set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
 		else
-			child->ptrace &= ~PT_TRACESYS;
+			clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
 		child->exit_code = data;
 
 		/* make sure the single step/taken-branch trap bits are not set: */
@@ -959,7 +1236,7 @@
 		if (data > _NSIG)
 			goto out_tsk;
 
-		child->ptrace &= ~PT_TRACESYS;
+		clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
 		if (request == PTRACE_SINGLESTEP) {
 			ia64_psr(pt)->ss = 1;
 		} else {
@@ -979,12 +1256,28 @@
 		ret = ptrace_detach(child, data);
 		goto out_tsk;
 
+	      case PTRACE_GETREGS:
+		ret = ptrace_getregs(child, (struct pt_all_user_regs*) data);
+		goto out_tsk;
+
+	      case PTRACE_SETREGS:
+		ret = ptrace_setregs(child, (struct pt_all_user_regs*) data);
+		goto out_tsk;
+
+	      case PTRACE_SETOPTIONS:
+		if (data & PTRACE_O_TRACESYSGOOD)
+			child->ptrace |= PT_TRACESYSGOOD;
+		else
+			child->ptrace &= ~PT_TRACESYSGOOD;
+		ret = 0;
+		break;
+
 	      default:
 		ret = -EIO;
 		goto out_tsk;
 	}
   out_tsk:
-	free_task_struct(child);
+	put_task_struct(child);
   out:
 	unlock_kernel();
 	return ret;
@@ -993,9 +1286,16 @@
 void
 syscall_trace (void)
 {
-	if ((current->ptrace & (PT_PTRACED|PT_TRACESYS)) != (PT_PTRACED|PT_TRACESYS))
+	if (!test_thread_flag(TIF_SYSCALL_TRACE))
+		return;
+	if (!(current->ptrace & PT_PTRACED))
 		return;
-	current->exit_code = SIGTRAP;
+	/*
+	 * The 0x80 provides a way for the tracing parent to distinguish between a syscall
+	 * stop and SIGTRAP delivery.
+	 */
+	current->exit_code = SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
+					? 0x80 : 0);
 	set_current_state(TASK_STOPPED);
 	notify_parent(current, SIGCHLD);
 	schedule();
diff -Nru a/arch/ia64/kernel/sal.c b/arch/ia64/kernel/sal.c
--- a/arch/ia64/kernel/sal.c	Fri Mar 15 17:51:04 2002
+++ b/arch/ia64/kernel/sal.c	Fri Mar 15 17:51:04 2002
@@ -18,7 +18,8 @@
 #include <asm/sal.h>
 #include <asm/pal.h>
 
-spinlock_t sal_lock = SPIN_LOCK_UNLOCKED;
+spinlock_t sal_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
+unsigned long sal_platform_features;
 
 static struct {
 	void *addr;	/* function entry point */
@@ -76,7 +77,7 @@
 	return str;
 }
 
-static void __init 
+static void __init
 ia64_sal_handler_init (void *entry_point, void *gpval)
 {
 	/* fill in the SAL procedure descriptor and point ia64_sal to it: */
@@ -102,7 +103,7 @@
 	if (strncmp(systab->signature, "SST_", 4) != 0)
 		printk("bad signature in system table!");
 
-	/* 
+	/*
 	 * revisions are coded in BCD, so %x does the job for us
 	 */
 	printk("SAL v%x.%02x: oem=%.32s, product=%.32s\n",
@@ -152,12 +153,12 @@
 		      case SAL_DESC_PLATFORM_FEATURE:
 		      {
 			      struct ia64_sal_desc_platform_feature *pf = (void *) p;
+			      sal_platform_features = pf->feature_mask;
 			      printk("SAL: Platform features ");
 
-			      if (pf->feature_mask & (1 << 0))
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_BUS_LOCK)
 				      printk("BusLock ");
-
-			      if (pf->feature_mask & (1 << 1)) {
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT) {
 				      printk("IRQ_Redirection ");
 #ifdef CONFIG_SMP
 				      if (no_int_routing)
@@ -166,15 +167,17 @@
 					      smp_int_redirect |= SMP_IRQ_REDIRECTION;
 #endif
 			      }
-			      if (pf->feature_mask & (1 << 2)) {
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT) {
 				      printk("IPI_Redirection ");
 #ifdef CONFIG_SMP
-				      if (no_int_routing) 
+				      if (no_int_routing)
 					      smp_int_redirect &= ~SMP_IPI_REDIRECTION;
 				      else
 					      smp_int_redirect |= SMP_IPI_REDIRECTION;
 #endif
 			      }
+			      if (pf->feature_mask & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)
+				      printk("ITC_Drift ");
 			      printk("\n");
 			      break;
  		      }
diff -Nru a/arch/ia64/kernel/salinfo.c b/arch/ia64/kernel/salinfo.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/kernel/salinfo.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,105 @@
+/*
+ * salinfo.c
+ *
+ * Creates entries in /proc/sal for various system features.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * 10/30/2001	jbarnes@sgi.com		copied much of Stephane's palinfo
+ *					code to create this file
+ */
+
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/module.h>
+
+#include <asm/sal.h>
+
+MODULE_AUTHOR("Jesse Barnes <jbarnes@sgi.com>");
+MODULE_DESCRIPTION("/proc interface to IA-64 SAL features");
+MODULE_LICENSE("GPL");
+
+static int salinfo_read(char *page, char **start, off_t off, int count, int *eof, void *data);
+
+typedef struct {
+	const char		*name;		/* name of the proc entry */
+	unsigned long           feature;        /* feature bit */
+	struct proc_dir_entry	*entry;		/* registered entry (removal) */
+} salinfo_entry_t;
+
+/*
+ * List {name,feature} pairs for every entry in /proc/sal/<feature>
+ * that this module exports
+ */
+static salinfo_entry_t salinfo_entries[]={
+	{ "bus_lock",           IA64_SAL_PLATFORM_FEATURE_BUS_LOCK, },
+	{ "irq_redirection",	IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT, },
+	{ "ipi_redirection",	IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT, },
+	{ "itc_drift",		IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT, },
+};
+
+#define NR_SALINFO_ENTRIES (sizeof(salinfo_entries)/sizeof(salinfo_entry_t))
+
+/*
+ * One for each feature and one more for the directory entry...
+ */
+static struct proc_dir_entry *salinfo_proc_entries[NR_SALINFO_ENTRIES + 1];
+
+static int __init
+salinfo_init(void)
+{
+	struct proc_dir_entry *salinfo_dir; /* /proc/sal dir entry */
+	struct proc_dir_entry **sdir = salinfo_proc_entries; /* keeps track of every entry */
+	int i;
+
+	salinfo_dir = proc_mkdir("sal", NULL);
+
+	for (i=0; i < NR_SALINFO_ENTRIES; i++) {
+		/* pass the feature bit in question as misc data */
+		*sdir++ = create_proc_read_entry (salinfo_entries[i].name, 0, salinfo_dir,
+						  salinfo_read, (void *)salinfo_entries[i].feature);
+	}
+	*sdir++ = salinfo_dir;
+
+	return 0;
+}
+
+static void __exit
+salinfo_exit(void)
+{
+	int i = 0;
+
+	for (i = 0; i < NR_SALINFO_ENTRIES ; i++) {
+		if (salinfo_proc_entries[i])
+			remove_proc_entry (salinfo_proc_entries[i]->name, NULL);
+	}
+}
+
+/*
+ * 'data' contains an integer that corresponds to the feature we're
+ * testing
+ */
+static int
+salinfo_read(char *page, char **start, off_t off, int count, int *eof, void *data)
+{
+	int len = 0;
+
+	MOD_INC_USE_COUNT;
+
+	len = sprintf(page, (sal_platform_features & (unsigned long)data) ? "1\n" : "0\n");
+
+	if (len <= off+count) *eof = 1;
+
+	*start = page + off;
+	len   -= off;
+
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	MOD_DEC_USE_COUNT;
+
+	return len;
+}
+
+module_init(salinfo_init);
+module_exit(salinfo_exit);
diff -Nru a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
--- a/arch/ia64/kernel/setup.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/kernel/setup.c	Fri Mar 15 17:51:01 2002
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1998-2001 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998, 1999, 2001 Stephane Eranian <eranian@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
  * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
@@ -20,6 +20,7 @@
 #include <linux/init.h>
 
 #include <linux/bootmem.h>
+#include <linux/console.h>
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/reboot.h>
@@ -27,7 +28,7 @@
 #include <linux/seq_file.h>
 #include <linux/string.h>
 #include <linux/threads.h>
-#include <linux/console.h>
+#include <linux/tty.h>
 
 #include <asm/acpi-ext.h>
 #include <asm/ia32.h>
@@ -53,12 +54,10 @@
 
 extern char _end;
 
-#ifdef CONFIG_NUMA
- struct cpuinfo_ia64 *boot_cpu_data;
-#else
- struct cpuinfo_ia64 _cpu_data[NR_CPUS] __attribute__ ((section ("__special_page_section")));
-#endif
+unsigned long __per_cpu_offset[NR_CPUS];
+struct cpuinfo_ia64 cpu_info __per_cpu_data;
 
+unsigned long ia64_phys_stacked_size_p8;
 unsigned long ia64_cycles_per_usec;
 struct ia64_boot_param *ia64_boot_param;
 struct screen_info screen_info;
@@ -147,6 +146,10 @@
 }
 
 
+/*
+ * Find a place to put the bootmap and return its starting address in bootmap_start.
+ * This address must be page-aligned.
+ */
 static int
 find_bootmap_location (unsigned long start, unsigned long end, void *arg)
 {
@@ -165,7 +168,7 @@
 
 	for (i = 0; i < num_rsvd_regions; i++) {
 		range_start = MAX(start, free_start);
-		range_end   = MIN(end, rsvd_region[i].start);
+		range_end   = MIN(end, rsvd_region[i].start & PAGE_MASK);
 
 		if (range_end <= range_start) continue;	/* skip over empty range */
 
@@ -177,7 +180,7 @@
 		/* nothing more available in this segment */
 		if (range_end == end) return 0;
 
-		free_start = rsvd_region[i].end;
+		free_start = PAGE_ALIGN(rsvd_region[i].end);
 	}
 	return 0;
 }
@@ -306,6 +309,10 @@
 	/* process SAL system table: */
 	ia64_sal_init(efi.sal_systab);
 
+#ifdef CONFIG_IA64_GENERIC
+	machvec_init(acpi_get_sysname());
+#endif
+
 	/*
 	 *  Set `iobase' to the appropriate address in region 6
 	 *    (uncached access range)
@@ -332,10 +339,6 @@
 
 	cpu_init();	/* initialize the bootstrap CPU */
 
-#ifdef CONFIG_IA64_GENERIC
-	machvec_init(acpi_get_sysname());
-#endif
-
 	if (efi.acpi20) {
 		/* Parse the ACPI 2.0 tables */
 		acpi20_parse(efi.acpi20);
@@ -371,17 +374,14 @@
 {
 #ifdef CONFIG_SMP
 #	define lpj	c->loops_per_jiffy
+#	define cpunum	c->cpu
 #else
 #	define lpj	loops_per_jiffy
+#	define cpunum	0
 #endif
 	char family[32], features[128], *cp;
 	struct cpuinfo_ia64 *c = v;
-	unsigned long mask, cpu = c - cpu_data(0);
-
-#ifdef CONFIG_SMP
-	if (!(cpu_online_map & (1 << cpu)))
-		return 0;
-#endif
+	unsigned long mask;
 
 	mask = c->features;
 
@@ -403,7 +403,7 @@
 		sprintf(cp, " 0x%lx", mask);
 
 	seq_printf(m,
-		   "processor  : %lu\n"
+		   "processor  : %d\n"
 		   "vendor     : %s\n"
 		   "arch       : IA-64\n"
 		   "family     : %s\n"
@@ -416,7 +416,7 @@
 		   "cpu MHz    : %lu.%06lu\n"
 		   "itc MHz    : %lu.%06lu\n"
 		   "BogoMIPS   : %lu.%02lu\n\n",
-		   cpu, c->vendor, family, c->model, c->revision, c->archrev,
+		   cpunum, c->vendor, family, c->model, c->revision, c->archrev,
 		   features, c->ppn, c->number,
 		   c->proc_freq / 1000000, c->proc_freq % 1000000,
 		   c->itc_freq / 1000000, c->itc_freq % 1000000,
@@ -427,6 +427,10 @@
 static void *
 c_start (struct seq_file *m, loff_t *pos)
 {
+#ifdef CONFIG_SMP
+	while (*pos < NR_CPUS && !(cpu_online_map & (1 << *pos)))
+		++*pos;
+#endif
 	return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
 }
 
@@ -483,6 +487,9 @@
 		cpuid.bits[i] = ia64_get_cpuid(i);
 
 	memcpy(c->vendor, cpuid.field.vendor, 16);
+#ifdef CONFIG_SMP
+	c->cpu = smp_processor_id();
+#endif
 	c->ppn = cpuid.field.ppn;
 	c->number = cpuid.field.number;
 	c->revision = cpuid.field.revision;
@@ -502,6 +509,12 @@
 	c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
 }
 
+void
+setup_per_cpu_areas (void)
+{
+	/* start_kernel() requires this... */
+}
+
 /*
  * cpu_init() initializes state that is per-CPU.  This function acts
  * as a 'CPU state barrier', nothing should get across.
@@ -509,46 +522,21 @@
 void
 cpu_init (void)
 {
+	extern char __per_cpu_start[], __phys_per_cpu_start[], __per_cpu_end[];
 	extern void __init ia64_mmu_init (void *);
 	unsigned long num_phys_stacked;
 	pal_vm_info_2_u_t vmi;
 	unsigned int max_ctx;
-	struct cpuinfo_ia64 *my_cpu_data;
-#ifdef CONFIG_NUMA
-	int cpu, order;
+	struct cpuinfo_ia64 *my_cpu_info;
+	void *my_cpu_data;
+	int cpu = smp_processor_id();
 
-	/*
-	 * If NUMA is configured, the cpu_data array is not preallocated. The boot cpu
-	 * allocates entries for every possible cpu. As the remaining cpus come online,
-	 * they reallocate a new cpu_data structure on their local node. This extra work
-	 * is required because some boot code references all cpu_data structures
-	 * before the cpus are actually started.
-	 */
-	if (!boot_cpu_data) {
-		my_cpu_data = alloc_bootmem_pages_node(NODE_DATA(numa_node_id()),
-						       sizeof(struct cpuinfo_ia64));
-		boot_cpu_data = my_cpu_data;
-		my_cpu_data->cpu_data[0] = my_cpu_data;
-		for (cpu = 1; cpu < NR_CPUS; ++cpu)
-			my_cpu_data->cpu_data[cpu]
-				= alloc_bootmem_pages_node(NODE_DATA(numa_node_id()),
-							   sizeof(struct cpuinfo_ia64));
-		for (cpu = 1; cpu < NR_CPUS; ++cpu)
-			memcpy(my_cpu_data->cpu_data[cpu]->cpu_data_ptrs,
-			       my_cpu_data->cpu_data, sizeof(my_cpu_data->cpu_data));
-	} else {
-		order = get_order(sizeof(struct cpuinfo_ia64));
-		my_cpu_data = page_address(alloc_pages_node(numa_node_id(), GFP_KERNEL, order));
-		memcpy(my_cpu_data, boot_cpu_data->cpu_data[smp_processor_id()],
-		       sizeof(struct cpuinfo_ia64));
-		__free_pages(virt_to_page(boot_cpu_data->cpu_data[smp_processor_id()]),
-			     order);
-		for (cpu = 0; cpu < NR_CPUS; ++cpu)
-			boot_cpu_data->cpu_data[cpu]->cpu_data[smp_processor_id()] = my_cpu_data;
-	}
-#else
-	my_cpu_data = cpu_data(smp_processor_id());
-#endif
+	my_cpu_data = alloc_bootmem_pages(__per_cpu_end - __per_cpu_start);
+	memcpy(my_cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start);
+
+	__per_cpu_offset[cpu] = (char *) my_cpu_data - __per_cpu_start;
+
+	my_cpu_info = my_cpu_data + ((char *) &cpu_info - __per_cpu_start);
 
 	/*
 	 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
@@ -556,7 +544,7 @@
 	 * depends on the data returned by identify_cpu().  We break the dependency by
 	 * accessing cpu_data() the old way, through identity mapped space.
 	 */
-	identify_cpu(my_cpu_data);
+	identify_cpu(my_cpu_info);
 
 	/* Clear the stack memory reserved for pt_regs: */
 	memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
@@ -577,6 +565,8 @@
 
 	atomic_inc(&init_mm.mm_count);
 	current->active_mm = &init_mm;
+	if (current->mm)
+		BUG();
 
 	ia64_mmu_init(my_cpu_data);
 
@@ -615,5 +605,7 @@
 		printk ("cpu_init: PAL RSE info failed, assuming 96 physical stacked regs\n");
 		num_phys_stacked = 96;
 	}
-	local_cpu_data->phys_stacked_size_p8 = num_phys_stacked*8 + 8;
+	/* size of physical stacked register partition plus 8 bytes: */
+	ia64_phys_stacked_size_p8 = num_phys_stacked*8 + 8;
+	platform_cpu_init();
 }
diff -Nru a/arch/ia64/kernel/sigframe.h b/arch/ia64/kernel/sigframe.h
--- a/arch/ia64/kernel/sigframe.h	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/sigframe.h	Fri Mar 15 17:51:02 2002
@@ -21,3 +21,5 @@
 	struct siginfo info;
 	struct sigcontext sc;
 };
+
+extern long ia64_do_signal (sigset_t *, struct sigscratch *, long);
diff -Nru a/arch/ia64/kernel/signal.c b/arch/ia64/kernel/signal.c
--- a/arch/ia64/kernel/signal.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/kernel/signal.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * Architecture-specific signal handling support.
  *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Derived from i386 and Alpha versions.
@@ -17,6 +17,8 @@
 #include <linux/smp.h>
 #include <linux/smp_lock.h>
 #include <linux/stddef.h>
+#include <linux/tty.h>
+#include <linux/binfmts.h>
 #include <linux/unistd.h>
 #include <linux/wait.h>
 
@@ -39,8 +41,6 @@
 # define GET_SIGSET(k,u)	__get_user((k)->sig[0], &(u)->sig[0])
 #endif
 
-extern long ia64_do_signal (sigset_t *, struct sigscratch *, long);	/* forward decl */
-
 long
 ia64_rt_sigsuspend (sigset_t *uset, size_t sigsetsize, struct sigscratch *scr)
 {
@@ -160,6 +160,7 @@
 		err |= __put_user((short)from->si_code, &to->si_code);
 		switch (from->si_code >> 16) {
 		      case __SI_FAULT >> 16:
+			err |= __put_user(from->si_flags, &to->si_flags);
 			err |= __put_user(from->si_isr, &to->si_isr);
 		      case __SI_POLL >> 16:
 			err |= __put_user(from->si_addr, &to->si_addr);
@@ -172,7 +173,12 @@
 		      case __SI_PROF >> 16:
 			err |= __put_user(from->si_uid, &to->si_uid);
 			err |= __put_user(from->si_pid, &to->si_pid);
-			err |= __put_user(from->si_pfm_ovfl, &to->si_pfm_ovfl);
+			if (from->si_code == PROF_OVFL) {
+				err |= __put_user(from->si_pfm_ovfl[0], &to->si_pfm_ovfl[0]);
+				err |= __put_user(from->si_pfm_ovfl[1], &to->si_pfm_ovfl[1]);
+				err |= __put_user(from->si_pfm_ovfl[2], &to->si_pfm_ovfl[2]);
+				err |= __put_user(from->si_pfm_ovfl[3], &to->si_pfm_ovfl[3]);
+			}
 			break;
 		      default:
 			err |= __put_user(from->si_uid, &to->si_uid);
@@ -239,7 +245,7 @@
 	 * could be corrupted.
 	 */
 	retval = (long) &ia64_leave_kernel;
-	if (current->ptrace & PT_TRACESYS)
+	if (test_thread_flag(TIF_SYSCALL_TRACE))
 		/*
 		 * strace expects to be notified after sigreturn returns even though the
 		 * context to which we return may not be in the middle of a syscall.
diff -Nru a/arch/ia64/kernel/smp.c b/arch/ia64/kernel/smp.c
--- a/arch/ia64/kernel/smp.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/smp.c	Fri Mar 15 17:51:03 2002
@@ -29,6 +29,7 @@
 #include <linux/smp.h>
 #include <linux/kernel_stat.h>
 #include <linux/mm.h>
+#include <linux/cache.h>
 #include <linux/delay.h>
 #include <linux/cache.h>
 
@@ -38,7 +39,6 @@
 #include <asm/delay.h>
 #include <asm/efi.h>
 #include <asm/machvec.h>
-
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/page.h>
@@ -51,14 +51,19 @@
 #include <asm/unistd.h>
 #include <asm/mca.h>
 
-/* The 'big kernel lock' */
-spinlock_t kernel_flag __cacheline_aligned_in_smp = SPIN_LOCK_UNLOCKED;
+/*
+ * The Big Kernel Lock.  It's not supposed to be used for performance critical stuff
+ * anymore.  But we still need to align it because certain workloads are still affected by
+ * it.  For example, llseek() and various other filesystem related routines still use the
+ * BKL.
+ */
+spinlock_t kernel_flag __cacheline_aligned = SPIN_LOCK_UNLOCKED;
 
 /*
  * Structure and data for smp_call_function(). This is designed to minimise static memory
  * requirements. It also looks cleaner.
  */
-static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
+static spinlock_t call_lock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
 
 struct call_data_struct {
 	void (*func) (void *info);
@@ -73,6 +78,9 @@
 #define IPI_CALL_FUNC		0
 #define IPI_CPU_STOP		1
 
+/* This needs to be cacheline aligned because it is written to by *other* CPUs.  */
+static __u64 ipi_operation __per_cpu_data ____cacheline_aligned;
+
 static void
 stop_this_cpu (void)
 {
@@ -90,7 +98,7 @@
 handle_IPI (int irq, void *dev_id, struct pt_regs *regs)
 {
 	int this_cpu = smp_processor_id();
-	unsigned long *pending_ipis = &local_cpu_data->ipi_operation;
+	unsigned long *pending_ipis = &this_cpu(ipi_operation);
 	unsigned long ops;
 
 	/* Count this now; we may make a call that never returns. */
@@ -98,58 +106,59 @@
 
 	mb();	/* Order interrupt and bit testing. */
 	while ((ops = xchg(pending_ipis, 0)) != 0) {
-	  mb();	/* Order bit clearing and data access. */
-	  do {
-		unsigned long which;
-
-		which = ffz(~ops);
-		ops &= ~(1 << which);
-
-		switch (which) {
-		case IPI_CALL_FUNC:
-			{
-				struct call_data_struct *data;
-				void (*func)(void *info);
-				void *info;
-				int wait;
-
-				/* release the 'pointer lock' */
-				data = (struct call_data_struct *) call_data;
-				func = data->func;
-				info = data->info;
-				wait = data->wait;
-
-				mb();
-				atomic_inc(&data->started);
-
-				/* At this point the structure may be gone unless wait is true.  */
-				(*func)(info);
-
-				/* Notify the sending CPU that the task is done.  */
-				mb();
-				if (wait)
-					atomic_inc(&data->finished);
+		mb();	/* Order bit clearing and data access. */
+		do {
+			unsigned long which;
+
+			which = ffz(~ops);
+			ops &= ~(1 << which);
+
+			switch (which) {
+			      case IPI_CALL_FUNC:
+			      {
+				      struct call_data_struct *data;
+				      void (*func)(void *info);
+				      void *info;
+				      int wait;
+
+				      /* release the 'pointer lock' */
+				      data = (struct call_data_struct *) call_data;
+				      func = data->func;
+				      info = data->info;
+				      wait = data->wait;
+
+				      mb();
+				      atomic_inc(&data->started);
+				      /*
+				       * At this point the structure may be gone unless
+				       * wait is true.
+				       */
+				      (*func)(info);
+
+				      /* Notify the sending CPU that the task is done.  */
+				      mb();
+				      if (wait)
+					      atomic_inc(&data->finished);
+			      }
+			      break;
+
+			      case IPI_CPU_STOP:
+				stop_this_cpu();
+				break;
+
+			      default:
+				printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n", this_cpu, which);
+				break;
 			}
-			break;
-
-		case IPI_CPU_STOP:
-			stop_this_cpu();
-			break;
-
-		default:
-			printk(KERN_CRIT "Unknown IPI on CPU %d: %lu\n", this_cpu, which);
-			break;
-		} /* Switch */
-	  } while (ops);
-
-	  mb();	/* Order data access and bit testing. */
+		} while (ops);
+		mb();	/* Order data access and bit testing. */
 	}
 }
 
 static inline void
 send_IPI_single (int dest_cpu, int op)
 {
-	set_bit(op, &cpu_data(dest_cpu)->ipi_operation);
+	set_bit(op, &per_cpu(ipi_operation, dest_cpu));
 	platform_send_ipi(dest_cpu, IA64_IPI_VECTOR, IA64_IPI_DM_INT, 0);
 }
 
@@ -185,10 +194,25 @@
 	platform_send_ipi(cpu, IA64_IPI_RESCHEDULE, IA64_IPI_DM_INT, 0);
 }
 
+/*
+ * This function sends a reschedule IPI to all (other) CPUs.  This should only be used if
+ * some 'global' task became runnable, such as a RT task, that must be handled now. The
+ * first CPU that manages to grab the task will run it.
+ */
+void
+smp_send_reschedule_all (void)
+{
+	int i;
+
+	for (i = 0; i < smp_num_cpus; i++)
+		if (i != smp_processor_id())
+			smp_send_reschedule(i);
+}
+
 void
 smp_flush_tlb_all (void)
 {
-	smp_call_function ((void (*)(void *))__flush_tlb_all,0,1,1);
+	smp_call_function((void (*)(void *))__flush_tlb_all, 0, 1, 1);
 	__flush_tlb_all();
 }
 
diff -Nru a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
--- a/arch/ia64/kernel/smpboot.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/kernel/smpboot.c	Fri Mar 15 17:51:02 2002
@@ -70,6 +70,7 @@
 extern void start_ap(void);
 
 int cpucount;
+task_t *task_for_booting_cpu;
 
 /* Setup configured maximum number of CPUs to activate */
 static int max_cpus = -1;
@@ -378,7 +379,7 @@
 	smp_callin();
 	Dprintk("CPU %d is set to go.\n", smp_processor_id());
 	while (!atomic_read(&smp_commenced))
-		;
+		cpu_relax();
 
 	Dprintk("CPU %d is starting idle.\n", smp_processor_id());
 	return cpu_idle();
@@ -412,17 +413,17 @@
 	 * We remove it from the pidhash and the runqueue
 	 * once we got the process:
 	 */
-	idle = init_task.prev_task;
+	idle = prev_task(&init_task);
 	if (!idle)
 		panic("No idle process for CPU %d", cpu);
 
-	idle->processor = cpu;
+	init_idle(idle, cpu);
+
 	ia64_cpu_to_sapicid[cpu] = sapicid;
-	idle->cpus_runnable = 1 << cpu; /* we schedule the first task manually */
 
-	del_from_runqueue(idle);
 	unhash_process(idle);
-	init_tasks[cpu] = idle;
+
+	task_for_booting_cpu = idle;
 
 	Dprintk("Sending wakeup vector %u to AP 0x%x/0x%x.\n", ap_wakeup_vector, cpu, sapicid);
 
@@ -451,6 +452,17 @@
 	}
 }
 
+unsigned long cache_decay_ticks;	/* # of ticks an idle task is considered cache-hot */
+
+static void
+smp_tune_scheduling (void)
+{
+	cache_decay_ticks = 10;	/* XXX base this on PAL info and cache-bandwidth estimate */
+
+	printk("task migration cache decay timeout: %ld msecs.\n",
+	       (cache_decay_ticks + 1) * 1000 / HZ);
+}
+
 /*
  * Cycle through the APs sending Wakeup IPIs to boot each.
  */
@@ -470,8 +482,8 @@
 	smp_setup_percpu_timer();
 
 	/*
-	* We have the boot CPU online for sure.
-	*/
+	 * We have the boot CPU online for sure.
+	 */
 	set_bit(0, &cpu_online_map);
 	set_bit(0, &cpu_callin_map);
 
@@ -480,9 +492,9 @@
 
 	printk("Boot processor id 0x%x/0x%x\n", 0, boot_cpu_id);
 
-	global_irq_holder = 0;
-	current->processor = 0;
-	init_idle();
+	global_irq_holder = NO_PROC_ID;
+	current_thread_info()->cpu = 0;
+	smp_tune_scheduling();
 
 	/*
 	 * If SMP should be disabled, then really disable it!
@@ -493,7 +505,7 @@
 		smp_num_cpus = 1;
 		goto smp_done;
 	}
-	if  (max_cpus != -1)
+	if (max_cpus != -1)
 		printk (KERN_INFO "Limiting CPUs to %d\n", max_cpus);
 
 	if (smp_boot_data.cpu_count > 1) {
diff -Nru a/arch/ia64/kernel/sys_ia64.c b/arch/ia64/kernel/sys_ia64.c
--- a/arch/ia64/kernel/sys_ia64.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/sys_ia64.c	Fri Mar 15 17:51:03 2002
@@ -2,8 +2,8 @@
  * This file contains various system calls that have different calling
  * conventions on different platforms.
  *
- * Copyright (C) 1999-2000 Hewlett-Packard Co
- * Copyright (C) 1999-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #include <linux/config.h>
 #include <linux/errno.h>
@@ -201,15 +201,13 @@
 	if (len == 0)
 		goto out;
 
-	/* don't permit mappings into unmapped space or the virtual page table of a region: */
+	/*
+	 * Don't permit mappings into unmapped space, the virtual page table of a region,
+	 * or across a region boundary.  Note: RGN_MAP_LIMIT is equal to 2^n-PAGE_SIZE
+	 * (for some integer n <= 61) and len > 0.
+	 */
 	roff = rgn_offset(addr);
-	if ((len | roff | (roff + len)) >= RGN_MAP_LIMIT) {
-		addr = -EINVAL;
-		goto out;
-	}
-
-	/* don't permit mappings that would cross a region boundary: */
-	if (rgn_index(addr) != rgn_index(addr + len)) {
+	if ((len > RGN_MAP_LIMIT) || (roff > (RGN_MAP_LIMIT - len))) {
 		addr = -EINVAL;
 		goto out;
 	}
@@ -275,74 +273,6 @@
 		regs->r8 = 0;	/* ensure large addresses are not mistaken as failures... */
 	return addr;
 }
-
-#if 1
-/*
- * This is here for a while to keep compatibillity with the old stat()
- * call - it will be removed later once everybody migrates to the new
- * kernel stat structure that matches the glibc one - Jes
- */
-
-static int
-cp_ia64_old_stat (struct kstat *stat, struct ia64_oldstat *statbuf)
-{
-	struct ia64_oldstat tmp;
-	unsigned int blocks, indirect;
-
-	memset(&tmp, 0, sizeof(tmp));
-	tmp.st_dev = stat->dev;
-	tmp.st_ino = stat->ino;
-	tmp.st_mode = stat->mode;
-	tmp.st_nlink = stat->nlink;
-	SET_STAT_UID(tmp, stat->uid);
-	SET_STAT_GID(tmp, stat->gid);
-	tmp.st_rdev = stat->rdev;
-	tmp.st_size = stat->size;
-	tmp.st_atime = stat->atime;
-	tmp.st_mtime = stat->mtime;
-	tmp.st_ctime = stat->ctime;
-	tmp.st_blocks = stat->i_blocks;
-	tmp.st_blksize = stat->i_blksize;
-	return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0;
-}
-
-asmlinkage long
-ia64_oldstat (char *filename, struct ia64_oldstat *statbuf)
-{
-	struct kstat stat;
-	int error = vfs_stat(filename, &stat);
-
-	if (!error)
-		error = cp_ia64_old_stat(&stat, statbuf);
-
-	return error;
-}
-
-asmlinkage long
-ia64_oldlstat (char *filename, struct ia64_oldstat *statbuf)
-{
-	struct kstat stat;
-	int error = vfs_lstat(filename, &stat);
-
-	if (!error)
-		error = cp_ia64_old_stat(&stat, statbuf);
-
-	return error;
-}
-
-asmlinkage long
-ia64_oldfstat (unsigned int fd, struct ia64_oldstat *statbuf)
-{
-	struct kstat stat;
-	int error = vfs_fstat(fd, &stat);
-
-	if (!error)
-		error = cp_ia64_old_stat(&stat, statbuf);
-
-	return error;
-}
-
-#endif
 
 #ifndef CONFIG_PCI
 
diff -Nru a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c
--- a/arch/ia64/kernel/traps.c	Fri Mar 15 17:51:04 2002
+++ b/arch/ia64/kernel/traps.c	Fri Mar 15 17:51:04 2002
@@ -1,7 +1,7 @@
 /*
  * Architecture-specific trap handling.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 05/12/00 grao <goutham.rao@intel.com> : added isr in siginfo for SIGFPE
@@ -32,6 +32,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/tty.h>
 #include <linux/vt_kern.h>		/* For unblank_screen() */
 
 #include <asm/hardirq.h>
@@ -133,6 +134,8 @@
 	/* SIGILL, SIGFPE, SIGSEGV, and SIGBUS want these field initialized: */
 	siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
 	siginfo.si_imm = break_num;
+	siginfo.si_flags = 0;		/* clear __ISR_VALID */
+	siginfo.si_isr = 0;
 
 	switch (break_num) {
 	      case 0: /* unknown error */
@@ -352,6 +355,8 @@
 				siginfo.si_code = FPE_FLTDIV;
 			}
 			siginfo.si_isr = isr;
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_imm = 0;
 			force_sig_info(SIGFPE, &siginfo, current);
 		}
 	} else {
@@ -372,6 +377,8 @@
 				siginfo.si_code = FPE_FLTRES;
 			}
 			siginfo.si_isr = isr;
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_imm = 0;
 			force_sig_info(SIGFPE, &siginfo, current);
 		}
 	}
@@ -490,6 +497,8 @@
 			siginfo.si_errno = 0;
 			siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
 			siginfo.si_imm = vector;
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_isr = isr;
 			force_sig_info(SIGILL, &siginfo, current);
 			return;
 		}
@@ -517,6 +526,10 @@
 		}
 		siginfo.si_signo = SIGTRAP;
 		siginfo.si_errno = 0;
+		siginfo.si_flags = 0;
+		siginfo.si_isr = 0;
+		siginfo.si_addr = 0;
+		siginfo.si_imm = 0;
 		force_sig_info(SIGTRAP, &siginfo, current);
 		return;
 
@@ -528,6 +541,9 @@
 			siginfo.si_errno = 0;
 			siginfo.si_code = FPE_FLTINV;
 			siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
+			siginfo.si_flags = __ISR_VALID;
+			siginfo.si_isr = isr;
+			siginfo.si_imm = 0;
 			force_sig_info(SIGFPE, &siginfo, current);
 		}
 		return;
@@ -537,6 +553,9 @@
 			siginfo.si_signo = SIGILL;
 			siginfo.si_code = ILL_BADIADDR;
 			siginfo.si_errno = 0;
+			siginfo.si_flags = 0;
+			siginfo.si_isr = 0;
+			siginfo.si_imm = 0;
 			siginfo.si_addr = (void *) (regs->cr_iip + ia64_psr(regs)->ri);
 			force_sig_info(SIGILL, &siginfo, current);
 			return;
diff -Nru a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c
--- a/arch/ia64/kernel/unaligned.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/unaligned.c	Fri Mar 15 17:51:03 2002
@@ -1,9 +1,9 @@
 /*
  * Architecture-specific unaligned trap handling.
  *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999-2000 Stephane Eranian <eranian@hpl.hp.com>
- * Copyright (C) 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * 2001/10/11	Fix unaligned access to rotating registers in s/w pipelined loops.
  * 2001/08/13	Correct size of extended floats (float_fsz) from 16 to 10 bytes.
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/sched.h>
 #include <linux/smp_lock.h>
+#include <linux/tty.h>
 
 #include <asm/uaccess.h>
 #include <asm/rse.h>
@@ -23,7 +24,7 @@
 #undef DEBUG_UNALIGNED_TRAP
 
 #ifdef DEBUG_UNALIGNED_TRAP
-# define DPRINT(a...)	do { printk("%s.%u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
+# define DPRINT(a...)	do { printk("%s %u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
 # define DDUMP(str,vp,len)	dump(str, vp, len)
 
 static void
@@ -650,7 +651,7 @@
 	 * just in case.
 	 */
 	if (ld.x6_op == 1 || ld.x6_op == 3) {
-		printk(KERN_ERR __FUNCTION__": register update on speculative load, error\n");
+		printk("%s %s: register update on speculative load, error\n", KERN_ERR, __FUNCTION__);
 		die_if_kernel("unaligned reference on specualtive load with register update\n",
 			      regs, 30);
 	}
@@ -1080,8 +1081,8 @@
 		 * For this reason we keep this sanity check
 		 */
 		if (ld.x6_op == 1 || ld.x6_op == 3)
-			printk(KERN_ERR __FUNCTION__": register update on speculative load pair, "
-			       "error\n");
+			printk("%s %s: register update on speculative load pair, "
+			       "error\n",KERN_ERR, __FUNCTION__);
 
 		setreg(ld.r3, ifa, 0, regs);
 	}
@@ -1304,11 +1305,7 @@
 	 * handler into reading an arbitrary kernel addresses...
 	 */
 	if (!user_mode(regs)) {
-#ifdef GAS_HAS_LOCAL_TAGS
-		fix = search_exception_table(regs->cr_iip + ia64_psr(regs)->ri);
-#else
-		fix = search_exception_table(regs->cr_iip);
-#endif
+		fix = SEARCH_EXCEPTION_TABLE(regs);
 	}
 	if (user_mode(regs) || fix.cont) {
 		if ((current->thread.flags & IA64_THREAD_UAC_SIGBUS) != 0)
@@ -1488,6 +1485,9 @@
 	si.si_errno = 0;
 	si.si_code = BUS_ADRALN;
 	si.si_addr = (void *) ifa;
+	si.si_flags = 0;
+	si.si_isr = 0;
+	si.si_imm = 0;
 	force_sig_info(SIGBUS, &si, current);
 	goto done;
 }
diff -Nru a/arch/ia64/kernel/unwind.c b/arch/ia64/kernel/unwind.c
--- a/arch/ia64/kernel/unwind.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/unwind.c	Fri Mar 15 17:51:03 2002
@@ -1,6 +1,6 @@
 /*
- * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 /*
  * This file implements call frame unwind support for the Linux
@@ -72,6 +72,8 @@
 
 #define alloc_reg_state()	kmalloc(sizeof(struct unw_state_record), GFP_ATOMIC)
 #define free_reg_state(usr)	kfree(usr)
+#define alloc_labeled_state()	kmalloc(sizeof(struct unw_labeled_state), GFP_ATOMIC)
+#define free_labeled_state(usr)	kfree(usr)
 
 typedef unsigned long unw_word;
 typedef unsigned char unw_hash_index_t;
@@ -521,7 +523,7 @@
 }
 
 
-/* Unwind decoder routines */
+/* Routines to manipulate the state stack.  */
 
 static inline void
 push (struct unw_state_record *sr)
@@ -534,24 +536,60 @@
 		return;
 	}
 	memcpy(rs, &sr->curr, sizeof(*rs));
-	rs->next = sr->stack;
-	sr->stack = rs;
+	sr->curr.next = rs;
 }
 
 static void
 pop (struct unw_state_record *sr)
 {
-	struct unw_reg_state *rs;
+	struct unw_reg_state *rs = sr->curr.next;
 
-	if (!sr->stack) {
-		printk ("unwind: stack underflow!\n");
+	if (!rs) {
+		printk("unwind: stack underflow!\n");
 		return;
 	}
-	rs = sr->stack;
-	sr->stack = rs->next;
+	memcpy(&sr->curr, rs, sizeof(*rs));
 	free_reg_state(rs);
 }
 
+/* Make a copy of the state stack.  Non-recursive to avoid stack overflows.  */
+static struct unw_reg_state *
+dup_state_stack (struct unw_reg_state *rs)
+{
+	struct unw_reg_state *copy, *prev = NULL, *first = NULL;
+
+	while (rs) {
+		copy = alloc_reg_state();
+		if (!copy) {
+			printk ("unwind.dup_state_stack: out of memory\n");
+			return NULL;
+		}
+		memcpy(copy, rs, sizeof(*copy));
+		if (first)
+			prev->next = copy;
+		else
+			first = copy;
+		rs = rs->next;
+		prev = copy;
+	}
+	return first;
+}
+
+/* Free all stacked register states (but not RS itself).  */
+static void
+free_state_stack (struct unw_reg_state *rs)
+{
+	struct unw_reg_state *p, *next;
+
+	for (p = rs->next; p != NULL; p = next) {
+		next = p->next;
+		free_reg_state(p);
+	}
+	rs->next = NULL;
+}
+
+/* Unwind decoder routines */
+
 static enum unw_register_index __attribute__((const))
 decode_abreg (unsigned char abreg, int memory)
 {
@@ -689,7 +727,7 @@
 	sr->first_region = 0;
 
 	/* check if we're done: */
-	if (body && sr->when_target < sr->region_start + sr->region_len) {
+	if (sr->when_target < sr->region_start + sr->region_len) {
 		sr->done = 1;
 		return;
 	}
@@ -902,31 +940,36 @@
 static inline void
 desc_copy_state (unw_word label, struct unw_state_record *sr)
 {
-	struct unw_reg_state *rs;
+	struct unw_labeled_state *ls;
 
-	for (rs = sr->reg_state_list; rs; rs = rs->next) {
-		if (rs->label == label) {
-			memcpy (&sr->curr, rs, sizeof(sr->curr));
+	for (ls = sr->labeled_states; ls; ls = ls->next) {
+		if (ls->label == label) {
+			free_state_stack(&sr->curr);
+			memcpy(&sr->curr, &ls->saved_state, sizeof(sr->curr));
+			sr->curr.next = dup_state_stack(ls->saved_state.next);
 			return;
 		}
 	}
-	printk("unwind: failed to find state labelled 0x%lx\n", label);
+	printk("unwind: failed to find state labeled 0x%lx\n", label);
 }
 
 static inline void
 desc_label_state (unw_word label, struct unw_state_record *sr)
 {
-	struct unw_reg_state *rs;
+	struct unw_labeled_state *ls;
 
-	rs = alloc_reg_state();
-	if (!rs) {
-		printk("unwind: cannot stack!\n");
+	ls = alloc_labeled_state();
+	if (!ls) {
+		printk("unwind.desc_label_state(): out of memory\n");
 		return;
 	}
-	memcpy(rs, &sr->curr, sizeof(*rs));
-	rs->label = label;
-	rs->next = sr->reg_state_list;
-	sr->reg_state_list = rs;
+	ls->label = label;
+	memcpy(&ls->saved_state, &sr->curr, sizeof(ls->saved_state));
+	ls->saved_state.next = dup_state_stack(sr->curr.next);
+
+	/* insert into list of labeled states: */
+	ls->next = sr->labeled_states;
+	sr->labeled_states = ls;
 }
 
 /*
@@ -1378,6 +1421,8 @@
 		else
 			break;
 	}
+	if (rel_ip < e->start_offset || rel_ip >= e->end_offset)
+		return NULL;
 	return e;
 }
 
@@ -1388,9 +1433,9 @@
 static inline struct unw_script *
 build_script (struct unw_frame_info *info)
 {
-	struct unw_reg_state *rs, *next;
 	const struct unw_table_entry *e = 0;
 	struct unw_script *script = 0;
+	struct unw_labeled_state *ls, *next;
 	unsigned long ip = info->ip;
 	struct unw_state_record sr;
 	struct unw_table *table;
@@ -1535,15 +1580,15 @@
 	for (i = UNW_REG_BSP; i < UNW_NUM_REGS; ++i)
 		compile_reg(&sr, i, script);
 
-	/* free labelled register states & stack: */
+	/* free labeled register states & stack: */
 
 	STAT(parse_start = ia64_get_itc());
-	for (rs = sr.reg_state_list; rs; rs = next) {
-		next = rs->next;
-		free_reg_state(rs);
+	for (ls = sr.labeled_states; ls; ls = next) {
+		next = ls->next;
+		free_state_stack(&ls->saved_state);
+		free_labeled_state(ls);
 	}
-	while (sr.stack)
-		pop(&sr);
+	free_state_stack(&sr.curr);
 	STAT(unw.stat.script.parse_time += ia64_get_itc() - parse_start);
 
 	script_finalize(script, &sr);
diff -Nru a/arch/ia64/kernel/unwind_i.h b/arch/ia64/kernel/unwind_i.h
--- a/arch/ia64/kernel/unwind_i.h	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/kernel/unwind_i.h	Fri Mar 15 17:51:03 2002
@@ -1,6 +1,6 @@
 /*
- * Copyright (C) 2000 Hewlett-Packard Co
- * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2000, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Kernel unwind support.
  */
@@ -85,6 +85,17 @@
 	int when;			/* when the register gets saved */
 };
 
+struct unw_reg_state {
+	struct unw_reg_state *next;		/* next (outer) element on state stack */
+	struct unw_reg_info reg[UNW_NUM_REGS];	/* register save locations */
+};
+
+struct unw_labeled_state {
+	struct unw_labeled_state *next;		/* next labeled state (or NULL) */
+	unsigned long label;			/* label for this state */
+	struct unw_reg_state saved_state;
+};
+
 struct unw_state_record {
 	unsigned int first_region : 1;	/* is this the first region? */
 	unsigned int done : 1;		/* are we done scanning descriptors? */
@@ -105,11 +116,8 @@
 	u8 gr_save_loc;			/* next general register to use for saving a register */
 	u8 return_link_reg;		/* branch register in which the return link is passed */
 
-	struct unw_reg_state {
-		struct unw_reg_state *next;
-		unsigned long label;		/* label of this state record */
-		struct unw_reg_info reg[UNW_NUM_REGS];
-	} curr, *stack, *reg_state_list;
+	struct unw_labeled_state *labeled_states;	/* list of all labeled states */
+	struct unw_reg_state curr;	/* current state */
 };
 
 enum unw_nat_type {
@@ -139,7 +147,7 @@
 };
 
 /*
- * Preserved general static registers (r2-r5) give rise to two script
+ * Preserved general static registers (r4-r7) give rise to two script
  * instructions; everything else yields at most one instruction; at
  * the end of the script, the psp gets popped, accounting for one more
  * instruction.
diff -Nru a/arch/ia64/lib/clear_page.S b/arch/ia64/lib/clear_page.S
--- a/arch/ia64/lib/clear_page.S	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/lib/clear_page.S	Fri Mar 15 17:51:01 2002
@@ -1,51 +1,77 @@
 /*
- *
- * Optimized function to clear a page of memory.
- *
- * Inputs:
- *	in0:	address of page
- *
- * Output:
- * 	none
- *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
- * Copyright (C) 1999-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2002 Ken Chen <kenneth.w.chen@intel.com>
  *
  * 1/06/01 davidm	Tuned for Itanium.
+ * 2/12/02 kchen	Tuned for both Itanium and McKinley
+ * 3/08/02 davidm	Some more tweaking
  */
+#include <linux/config.h>
+
 #include <asm/asmmacro.h>
 #include <asm/page.h>
 
+#ifdef CONFIG_ITANIUM
+# define L3_LINE_SIZE	64	// Itanium L3 line size
+# define PREFETCH_LINES	9	// magic number
+#else
+# define L3_LINE_SIZE	128	// McKinley L3 line size
+# define PREFETCH_LINES	12	// magic number
+#endif
+
 #define saved_lc	r2
-#define dst0		in0
+#define dst_fetch	r3
 #define dst1		r8
 #define dst2		r9
 #define dst3		r10
-#define dst_fetch	r11
+#define dst4		r11
+
+#define dst_last	r31
 
 GLOBAL_ENTRY(clear_page)
 	.prologue
 	.regstk 1,0,0,0
-	mov r16 = PAGE_SIZE/64-1	// -1 = repeat/until
-	;;
+	mov r16 = PAGE_SIZE/L3_LINE_SIZE-1	// main loop count, -1=repeat/until
 	.save ar.lc, saved_lc
 	mov saved_lc = ar.lc
+
 	.body
-	mov ar.lc = r16
-	adds dst1 = 16, dst0
-	adds dst2 = 32, dst0
-	adds dst3 = 48, dst0
-	adds dst_fetch = 512, dst0
+	mov ar.lc = (PREFETCH_LINES - 1)
+	mov dst_fetch = in0
+	adds dst1 = 16, in0
+	adds dst2 = 32, in0
+	;;
+.fetch:	stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
+	adds dst3 = 48, in0		// executing this multiple times is harmless
+	br.cloop.sptk.few .fetch
+	;;
+	addl dst_last = (PAGE_SIZE - PREFETCH_LINES*L3_LINE_SIZE), dst_fetch
+	mov ar.lc = r16			// one L3 line per iteration
+	adds dst4 = 64, in0
+	;;
+#ifdef CONFIG_ITANIUM
+	// Optimized for Itanium
+1:	stf.spill.nta [dst1] = f0, 64
+	stf.spill.nta [dst2] = f0, 64
+	cmp.lt p8,p0=dst_fetch, dst_last
+	;;
+#else
+	// Optimized for McKinley
+1:	stf.spill.nta [dst1] = f0, 64
+	stf.spill.nta [dst2] = f0, 64
+	stf.spill.nta [dst3] = f0, 64
+	stf.spill.nta [dst4] = f0, 128
+	cmp.lt p8,p0=dst_fetch, dst_last
 	;;
-1:	stf.spill.nta [dst0] = f0, 64
 	stf.spill.nta [dst1] = f0, 64
 	stf.spill.nta [dst2] = f0, 64
+#endif
 	stf.spill.nta [dst3] = f0, 64
-
-	lfetch [dst_fetch], 64
-	br.cloop.dptk.few 1b
+(p8)	stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
+	br.cloop.sptk.few 1b
 	;;
-	mov ar.lc = r2		// restore lc
+	mov ar.lc = saved_lc		// restore lc
 	br.ret.sptk.many rp
 END(clear_page)
diff -Nru a/arch/ia64/lib/copy_page.S b/arch/ia64/lib/copy_page.S
--- a/arch/ia64/lib/copy_page.S	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/lib/copy_page.S	Fri Mar 15 17:51:03 2002
@@ -9,8 +9,8 @@
  *	no return value
  *
  * Copyright (C) 1999, 2001 Hewlett-Packard Co
- * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
- * Copyright (C) 2001 David Mosberger <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
+ *	David Mosberger <davidm@hpl.hp.com>
  *
  * 4/06/01 davidm	Tuned to make it perform well both for cached and uncached copies.
  */
diff -Nru a/arch/ia64/lib/swiotlb.c b/arch/ia64/lib/swiotlb.c
--- a/arch/ia64/lib/swiotlb.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/lib/swiotlb.c	Fri Mar 15 17:51:01 2002
@@ -27,11 +27,20 @@
 #define ALIGN(val, align) ((unsigned long)	\
 	(((unsigned long) (val) + ((align) - 1)) & ~((align) - 1)))
 
-#define SG_ENT_VIRT_ADDRESS(sg)	((sg)->address ? (sg)->address			\
-				 : page_address((sg)->page) + (sg)->offset)
+#define OFFSET(val,align) ((unsigned long)	\
+	                   ( (val) & ( (align) - 1)))
+
+#define SG_ENT_VIRT_ADDRESS(sg)	(page_address((sg)->page) + (sg)->offset)
 #define SG_ENT_PHYS_ADDRESS(SG)	virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
 
 /*
+ * Maximum allowable number of contiguous slabs to map,
+ * must be a power of 2.  What is the appropriate value ?
+ * The complexity of {map,unmap}_single is linearly dependent on this value.
+ */
+#define IO_TLB_SEGSIZE	128
+
+/*
  * log of the size of each IO TLB slab.  The number of slabs is command line controllable.
  */
 #define IO_TLB_SHIFT 11
@@ -69,10 +78,15 @@
 setup_io_tlb_npages (char *str)
 {
 	io_tlb_nslabs = simple_strtoul(str, NULL, 0) << (PAGE_SHIFT - IO_TLB_SHIFT);
+
+	/* avoid tail segment of size < IO_TLB_SEGSIZE */
+	io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
+
 	return 1;
 }
 __setup("swiotlb=", setup_io_tlb_npages);
 
+
 /*
  * Statically reserve bounce buffer space and initialize bounce buffer data structures for
  * the software IO TLB used to implement the PCI DMA API.
@@ -92,12 +106,12 @@
 
 	/*
 	 * Allocate and initialize the free list array.  This array is used
-	 * to find contiguous free memory regions of size 2^IO_TLB_SHIFT between
-	 * io_tlb_start and io_tlb_end.
+	 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
+	 * between io_tlb_start and io_tlb_end.
 	 */
 	io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int));
 	for (i = 0; i < io_tlb_nslabs; i++)
-		io_tlb_list[i] = io_tlb_nslabs - i;
+ 		io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
 	io_tlb_index = 0;
 	io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(char *));
 
@@ -124,7 +138,7 @@
 	if (size > (1 << PAGE_SHIFT))
 		stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
 	else
-		stride = nslots;
+		stride = 1;
 
 	if (!nslots)
 		BUG();
@@ -151,7 +165,8 @@
 
 				for (i = index; i < index + nslots; i++)
 					io_tlb_list[i] = 0;
-				for (i = index - 1; (i >= 0) && io_tlb_list[i]; i--)
+				for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1)
+				       && io_tlb_list[i]; i--)
 					io_tlb_list[i] = ++count;
 				dma_addr = io_tlb_start + (index << IO_TLB_SHIFT);
 
@@ -217,7 +232,8 @@
 	 */
 	spin_lock_irqsave(&io_tlb_lock, flags);
 	{
-		int count = ((index + nslots) < io_tlb_nslabs ? io_tlb_list[index + nslots] : 0);
+		int count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ?
+			     io_tlb_list[index + nslots] : 0);
 		/*
 		 * Step 1: return the slots to the free list, merging the slots with
 		 * superceeding slots
@@ -228,7 +244,8 @@
 		 * Step 2: merge the returned slots with the preceeding slots, if
 		 * available (non zero)
 		 */
-		for (i = index - 1; (i >= 0) && io_tlb_list[i]; i--)
+		for (i = index - 1;  (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) &&
+		       io_tlb_list[i]; i--)
 			io_tlb_list[i] = ++count;
 	}
 	spin_unlock_irqrestore(&io_tlb_lock, flags);
@@ -405,11 +422,9 @@
 	for (i = 0; i < nelems; i++, sg++) {
 		sg->orig_address = SG_ENT_VIRT_ADDRESS(sg);
 		if ((SG_ENT_PHYS_ADDRESS(sg) & ~hwdev->dma_mask) != 0) {
-			addr = map_single(hwdev, sg->address, sg->length, direction);
-			if (sg->address)
-				sg->address = addr;
-			else
-				sg->page = virt_to_page(addr);
+			addr = map_single(hwdev, sg->orig_address, sg->length, direction);
+			sg->page = virt_to_page(addr);
+			sg->offset = (u64) addr & ~PAGE_MASK;
 		}
 	}
 	return nelems;
@@ -430,12 +445,10 @@
 	for (i = 0; i < nelems; i++, sg++)
 		if (sg->orig_address != SG_ENT_VIRT_ADDRESS(sg)) {
 			unmap_single(hwdev, SG_ENT_VIRT_ADDRESS(sg), sg->length, direction);
-			if (sg->address)
-				sg->address = sg->orig_address;
-			else
-				sg->page = virt_to_page(sg->orig_address);
+			sg->page = virt_to_page(sg->orig_address);
+			sg->offset = (u64) sg->orig_address & ~PAGE_MASK;
 		} else if (direction == PCI_DMA_FROMDEVICE)
-			mark_clean(sg->address, sg->length);
+			mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->length);
 }
 
 /*
diff -Nru a/arch/ia64/mm/extable.c b/arch/ia64/mm/extable.c
--- a/arch/ia64/mm/extable.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/mm/extable.c	Fri Mar 15 17:51:02 2002
@@ -1,8 +1,8 @@
 /*
  * Kernel exception handling table support.  Derived from arch/alpha/mm/extable.c.
  *
- * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
- * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998, 1999, 2001-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/config.h>
@@ -55,10 +55,12 @@
 	struct module *mp;
 
 	/* The kernel is the last "module" -- no need to treat it special. */
-	for (mp = module_list; mp ; mp = mp->next) {
+	for (mp = module_list; mp; mp = mp->next) {
 		if (!mp->ex_table_start)
 			continue;
 		archdata = (struct archdata *) mp->archdata_start;
+		if (!archdata)
+			continue;
 		entry = search_one_table(mp->ex_table_start, mp->ex_table_end - 1,
 					 addr, (unsigned long) archdata->gp);
 		if (entry) {
diff -Nru a/arch/ia64/mm/fault.c b/arch/ia64/mm/fault.c
--- a/arch/ia64/mm/fault.c	Fri Mar 15 17:51:04 2002
+++ b/arch/ia64/mm/fault.c	Fri Mar 15 17:51:04 2002
@@ -1,7 +1,7 @@
 /*
  * MMU fault handling support.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #include <linux/sched.h>
@@ -49,7 +49,6 @@
 	int signal = SIGSEGV, code = SEGV_MAPERR;
 	struct vm_area_struct *vma, *prev_vma;
 	struct mm_struct *mm = current->mm;
-	struct exception_fixup fix;
 	struct siginfo si;
 	unsigned long mask;
 
@@ -96,7 +95,7 @@
 	 * sure we exit gracefully rather than endlessly redo the
 	 * fault.
 	 */
-	switch (handle_mm_fault(mm, vma, address, mask)) {
+	switch (handle_mm_fault(mm, vma, address, (mask & VM_WRITE) != 0)) {
 	      case 1:
 		++current->min_flt;
 		break;
@@ -151,6 +150,8 @@
 		si.si_errno = 0;
 		si.si_code = code;
 		si.si_addr = (void *) address;
+		si.si_isr = isr;
+		si.si_flags = __ISR_VALID;
 		force_sig_info(signal, &si, current);
 		return;
 	}
@@ -165,15 +166,8 @@
 		return;
 	}
 
-#ifdef GAS_HAS_LOCAL_TAGS
-	fix = search_exception_table(regs->cr_iip + ia64_psr(regs)->ri);
-#else
-	fix = search_exception_table(regs->cr_iip);
-#endif
-	if (fix.cont) {
-		handle_exception(regs, fix);
+	if (done_with_exception(regs))
 		return;
-	}
 
 	/*
 	 * Oops. The kernel tried to access some bad page. We'll have to terminate things
@@ -194,9 +188,7 @@
   out_of_memory:
 	up_read(&mm->mmap_sem);
 	if (current->pid == 1) {
-		current->policy |= SCHED_YIELD;
-		schedule();
-		down_read(&mm->mmap_sem);
+		yield();
 		goto survive;
 	}
 	printk("VM: killing process %s\n", current->comm);
diff -Nru a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
--- a/arch/ia64/mm/init.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/mm/init.c	Fri Mar 15 17:51:03 2002
@@ -1,8 +1,8 @@
 /*
  * Initialize MMU support.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #include <linux/config.h>
 #include <linux/kernel.h>
@@ -14,6 +14,7 @@
 #include <linux/slab.h>
 #include <linux/swap.h>
 
+#include <asm/a.out.h>
 #include <asm/bitops.h>
 #include <asm/dma.h>
 #include <asm/efi.h>
@@ -37,10 +38,15 @@
 
 static unsigned long totalram_pages;
 
+static int pgt_cache_water[2] = { 25, 50 };
+
 int
-do_check_pgt_cache (int low, int high)
+check_pgt_cache (void)
 {
-	int freed = 0;
+	int low, high, freed = 0;
+
+	low = pgt_cache_water[0];
+	high = pgt_cache_water[1];
 
 	if (pgtable_cache_size > high) {
 		do {
@@ -48,8 +54,6 @@
 				free_page((unsigned long)pgd_alloc_one_fast(0)), ++freed;
 			if (pmd_quicklist)
 				free_page((unsigned long)pmd_alloc_one_fast(0, 0)), ++freed;
-			if (pte_quicklist)
-				free_page((unsigned long)pte_alloc_one_fast(0, 0)), ++freed;
 		} while (pgtable_cache_size > low);
 	}
 	return freed;
@@ -99,12 +103,12 @@
 		free_page(addr);
 		++totalram_pages;
 	}
-	printk ("Freeing unused kernel memory: %ldkB freed\n",
-		(&__init_end - &__init_begin) >> 10);
+	printk(KERN_INFO "Freeing unused kernel memory: %ldkB freed\n",
+	       (&__init_end - &__init_begin) >> 10);
 }
 
 void
-free_initrd_mem(unsigned long start, unsigned long end)
+free_initrd_mem (unsigned long start, unsigned long end)
 {
 	/*
 	 * EFI uses 4KB pages while the kernel can use 4KB  or bigger.
@@ -141,7 +145,7 @@
 	end = end & PAGE_MASK;
 
 	if (start < end)
-		printk ("Freeing initrd memory: %ldkB freed\n", (end - start) >> 10);
+		printk(KERN_INFO "Freeing initrd memory: %ldkB freed\n", (end - start) >> 10);
 
 	for (; start < end; start += PAGE_SIZE) {
 		if (!VALID_PAGE(virt_to_page(start)))
@@ -243,15 +247,16 @@
 		pmd = pmd_alloc(&init_mm, pgd, address);
 		if (!pmd)
 			goto out;
-		pte = pte_alloc(&init_mm, pmd, address);
+		pte = pte_alloc_map(&init_mm, pmd, address);
 		if (!pte)
 			goto out;
 		if (!pte_none(*pte)) {
-			pte_ERROR(*pte);
+			pte_unmap(pte);
 			goto out;
 		}
 		flush_page_to_ram(page);
 		set_pte(pte, mk_pte(page, PAGE_GATE));
+		pte_unmap(pte);
 	}
   out:	spin_unlock(&init_mm.page_table_lock);
 	/* no need for flush_tlb */
diff -Nru a/arch/ia64/sn/Makefile b/arch/ia64/sn/Makefile
--- a/arch/ia64/sn/Makefile	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,19 +0,0 @@
-#
-# ia64/sn/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
-all: sn.a
-
-O_TARGET        = sn.a
-obj-y           = sn1/sn1.a
-
-clean::
-
-include $(TOPDIR)/Rules.make
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp b/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-bigsur-mp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,777 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_PIIX_TUNING is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+CONFIG_EEPRO100=y
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp b/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-bigsur-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,772 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDETAPE is not set
+CONFIG_BLK_DEV_IDEFLOPPY=y
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+# CONFIG_IDEPCI_SHARE_IRQ is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+CONFIG_BLK_DEV_ADMA=y
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_IDEDMA_PCI_AUTO is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_PCI_WIP is not set
+# CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_AEC62XX_TUNING is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_WDC_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_AMD74XX_OVERRIDE is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_HPT34X_AUTODMA is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_PIIX_TUNING is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_PDC202XX is not set
+# CONFIG_PDC202XX_BURST is not set
+# CONFIG_PDC202XX_FORCE is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+# CONFIG_SCSI_QLOGIC_FC is not set
+CONFIG_SCSI_QLOGIC_1280=y
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_APRICOT is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_TULIP is not set
+# CONFIG_DE4X5 is not set
+# CONFIG_DGRS is not set
+# CONFIG_DM9102 is not set
+CONFIG_EEPRO100=y
+# CONFIG_LNE390 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_NE3210 is not set
+# CONFIG_ES3210 is not set
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_8139TOO_PIO is not set
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_WINBOND_840 is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_SERIAL_CONSOLE=y
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+CONFIG_MOUSE=y
+CONFIG_PSMOUSE=y
+# CONFIG_82C710_MOUSE is not set
+# CONFIG_PC110_PAD is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="iso8859-1"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-dig-mp b/arch/ia64/sn/configs/sn1/defconfig-dig-mp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-dig-mp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-dig-sp b/arch/ia64/sn/configs/sn1/defconfig-dig-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-dig-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-generic-mp b/arch/ia64/sn/configs/sn1/defconfig-generic-mp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-generic-mp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+CONFIG_IA64_GENERIC=y
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Simulated drivers
+#
+# CONFIG_SIMETH is not set
+# CONFIG_SIM_SERIAL is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-generic-sp b/arch/ia64/sn/configs/sn1/defconfig-generic-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-generic-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+CONFIG_IA64_GENERIC=y
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Simulated drivers
+#
+# CONFIG_SIMETH is not set
+# CONFIG_SIM_SERIAL is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-hp-sp b/arch/ia64/sn/configs/sn1/defconfig-hp-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-hp-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,334 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+CONFIG_IA64_HP_SIM=y
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_NETLINK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_FILTER is not set
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_INET_ECN is not set
+# CONFIG_SYN_COOKIES is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_PPA is not set
+# CONFIG_SCSI_IMM is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+# CONFIG_PRINTER is not set
+# CONFIG_PPDEV is not set
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+# CONFIG_NFS_FS is not set
+# CONFIG_NFS_V3 is not set
+# CONFIG_ROOT_NFS is not set
+# CONFIG_NFSD is not set
+# CONFIG_NFSD_V3 is not set
+# CONFIG_SUNRPC is not set
+# CONFIG_LOCKD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Simulated drivers
+#
+CONFIG_SIMETH=y
+CONFIG_SIM_SERIAL=y
+CONFIG_SCSI_SIM=y
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-prom-medusa b/arch/ia64/sn/configs/sn1/defconfig-prom-medusa
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-prom-medusa	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,529 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-modules	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,738 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0 b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-sn1-mp-syn1-0	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn1/defconfig-sn1-sp b/arch/ia64/sn/configs/sn1/defconfig-sn1-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn1/defconfig-sn1-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,736 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+CONFIG_IA64_SGI_SN1=y
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_SGI_IOC3_ETH=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+CONFIG_KDB=y
+CONFIG_KDB_MODULES=y
+# CONFIG_KDB_OFF is not set
+
+#
+#   Load all symbols for debugging is required for KDB
+#
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-dig-numa b/arch/ia64/sn/configs/sn2/defconfig-dig-numa
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-dig-numa	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,460 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+CONFIG_NUMA=y
+CONFIG_DISCONTIGMEM=y
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp b/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-mp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp b/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-sn2-dig-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,459 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+# CONFIG_EXPERIMENTAL is not set
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+CONFIG_ITANIUM=y
+# CONFIG_MCKINLEY is not set
+# CONFIG_IA64_GENERIC is not set
+CONFIG_IA64_DIG=y
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+# CONFIG_IA64_SGI_SN2 is not set
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_BRL_EMU=y
+CONFIG_ITANIUM_BSTEP_SPECIFIC=y
+CONFIG_IA64_L1_CACHE_SHIFT=6
+# CONFIG_NUMA is not set
+# CONFIG_IA64_MCA is not set
+CONFIG_PM=y
+CONFIG_IA64_HAVE_SYNCRONIZED_ITC=y
+# CONFIG_DEVFS_FS is not set
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+# CONFIG_IA32_SUPPORT is not set
+# CONFIG_PERFMON is not set
+# CONFIG_IA64_PALINFO is not set
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_SYSCTL is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+# CONFIG_XSCSI is not set
+
+#
+# SCSI support
+#
+# CONFIG_SCSI is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+# CONFIG_SERIAL is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+# CONFIG_DEVFS_FS is not set
+# CONFIG_DEVFS_MOUNT is not set
+# CONFIG_DEVFS_DEBUG is not set
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+# CONFIG_XFS_SUPPORT is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Console drivers
+#
+CONFIG_VGA_CONSOLE=y
+
+#
+# Frame-buffer support
+#
+# CONFIG_FB is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-mp b/arch/ia64/sn/configs/sn2/defconfig-sn2-mp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-sn2-mp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,730 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules b/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-sn2-mp-modules	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,732 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+# CONFIG_MODVERSIONS is not set
+CONFIG_KMOD=y
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+# CONFIG_SERIAL_SGI_L1_PROTOCOL is not set
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa b/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-sn2-prom-medusa	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,537 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+CONFIG_SMP=y
+# CONFIG_IA32_SUPPORT is not set
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+# CONFIG_NET is not set
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+# CONFIG_EFI_RTC is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_FAT_FS is not set
+# CONFIG_MSDOS_FS is not set
+# CONFIG_UMSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+# CONFIG_ISO9660_FS is not set
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_SMB_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+# CONFIG_NLS is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+
+#
+#   Networking support is needed for USB Networking device support
+#
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+# CONFIG_KALLSYMS is not set
diff -Nru a/arch/ia64/sn/configs/sn2/defconfig-sn2-sp b/arch/ia64/sn/configs/sn2/defconfig-sn2-sp
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/configs/sn2/defconfig-sn2-sp	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,730 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+
+#
+# Loadable module support
+#
+# CONFIG_MODULES is not set
+
+#
+# General setup
+#
+CONFIG_IA64=y
+# CONFIG_ISA is not set
+# CONFIG_EISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SBUS is not set
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_RWSEM_XCHGADD_ALGORITHM is not set
+CONFIG_ACPI=y
+CONFIG_ACPI_EFI=y
+CONFIG_ACPI_INTERPRETER=y
+CONFIG_ACPI_KERNEL_CONFIG=y
+# CONFIG_ITANIUM is not set
+CONFIG_MCKINLEY=y
+# CONFIG_IA64_GENERIC is not set
+# CONFIG_IA64_DIG is not set
+# CONFIG_IA64_HP_SIM is not set
+# CONFIG_IA64_SGI_SN1 is not set
+CONFIG_IA64_SGI_SN2=y
+# CONFIG_IA64_PAGE_SIZE_4KB is not set
+# CONFIG_IA64_PAGE_SIZE_8KB is not set
+CONFIG_IA64_PAGE_SIZE_16KB=y
+# CONFIG_IA64_PAGE_SIZE_64KB is not set
+CONFIG_IA64_L1_CACHE_SHIFT=7
+CONFIG_MCKINLEY_ASTEP_SPECIFIC=y
+CONFIG_MCKINLEY_A0_SPECIFIC=y
+CONFIG_IA64_SGI_SN=y
+CONFIG_IA64_SGI_SN_DEBUG=y
+CONFIG_IA64_SGI_SN_SIM=y
+CONFIG_IA64_SGI_AUTOTEST=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_SERIAL_SGI_L1_PROTOCOL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_IA64_MCA=y
+CONFIG_NUMA=y
+CONFIG_PERCPU_IRQ=y
+CONFIG_PCIBA=y
+CONFIG_KCORE_ELF=y
+# CONFIG_SMP is not set
+CONFIG_IA32_SUPPORT=y
+CONFIG_PERFMON=y
+CONFIG_IA64_PALINFO=y
+# CONFIG_EFI_VARS is not set
+CONFIG_NET=y
+CONFIG_SYSVIPC=y
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_SYSCTL=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_BUSMGR is not set
+# CONFIG_ACPI_SYS is not set
+# CONFIG_ACPI_CPU is not set
+# CONFIG_ACPI_BUTTON is not set
+# CONFIG_ACPI_AC is not set
+# CONFIG_ACPI_EC is not set
+# CONFIG_ACPI_CMBATT is not set
+# CONFIG_ACPI_THERMAL is not set
+CONFIG_PCI=y
+# CONFIG_PCI_NAMES is not set
+# CONFIG_HOTPLUG is not set
+# CONFIG_PCMCIA is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_NETLINK=y
+CONFIG_RTNETLINK=y
+CONFIG_NETLINK_DEV=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_DEBUG=y
+CONFIG_FILTER=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_INET_ECN is not set
+CONFIG_SYN_COOKIES=y
+
+#
+#   IP: Netfilter Configuration
+#
+# CONFIG_IP_NF_CONNTRACK is not set
+# CONFIG_IP_NF_QUEUE is not set
+# CONFIG_IP_NF_IPTABLES is not set
+# CONFIG_IP_NF_COMPAT_IPCHAINS is not set
+# CONFIG_IP_NF_COMPAT_IPFWADM is not set
+# CONFIG_IPV6 is not set
+# CONFIG_KHTTPD is not set
+# CONFIG_ATM is not set
+
+#
+#  
+#
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_DECNET is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_LLC is not set
+# CONFIG_NET_DIVERT is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_FASTROUTE is not set
+# CONFIG_NET_HW_FLOWCONTROL is not set
+
+#
+# QoS and/or fair queueing
+#
+# CONFIG_NET_SCHED is not set
+
+#
+# Memory Technology Devices (MTD)
+#
+# CONFIG_MTD is not set
+
+#
+# Plug and Play configuration
+#
+# CONFIG_PNP is not set
+# CONFIG_ISAPNP is not set
+# CONFIG_PNPBIOS is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_DEV_XD is not set
+# CONFIG_PARIDE is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_BLK_DEV_INITRD is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_I2O_PCI is not set
+# CONFIG_I2O_BLOCK is not set
+# CONFIG_I2O_LAN is not set
+# CONFIG_I2O_SCSI is not set
+# CONFIG_I2O_PROC is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+# CONFIG_BLK_DEV_MD is not set
+# CONFIG_MD_LINEAR is not set
+# CONFIG_MD_RAID0 is not set
+# CONFIG_MD_RAID1 is not set
+# CONFIG_MD_RAID5 is not set
+# CONFIG_MD_MULTIPATH is not set
+# CONFIG_BLK_DEV_LVM is not set
+
+#
+# ATA/IDE/MFM/RLL support
+#
+CONFIG_IDE=y
+
+#
+# IDE, ATA and ATAPI Block devices
+#
+CONFIG_BLK_DEV_IDE=y
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_HD_IDE is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_BLK_DEV_IDEDISK=y
+# CONFIG_IDEDISK_MULTI_MODE is not set
+# CONFIG_BLK_DEV_IDEDISK_VENDOR is not set
+# CONFIG_BLK_DEV_IDEDISK_FUJITSU is not set
+# CONFIG_BLK_DEV_IDEDISK_IBM is not set
+# CONFIG_BLK_DEV_IDEDISK_MAXTOR is not set
+# CONFIG_BLK_DEV_IDEDISK_QUANTUM is not set
+# CONFIG_BLK_DEV_IDEDISK_SEAGATE is not set
+# CONFIG_BLK_DEV_IDEDISK_WD is not set
+# CONFIG_BLK_DEV_COMMERIAL is not set
+# CONFIG_BLK_DEV_TIVO is not set
+# CONFIG_BLK_DEV_IDECS is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_CMD640 is not set
+# CONFIG_BLK_DEV_CMD640_ENHANCED is not set
+# CONFIG_BLK_DEV_ISAPNP is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+# CONFIG_BLK_DEV_IDEPCI is not set
+# CONFIG_IDE_CHIPSETS is not set
+# CONFIG_IDEDMA_AUTO is not set
+# CONFIG_DMA_NONPCI is not set
+# CONFIG_BLK_DEV_IDE_MODES is not set
+# CONFIG_BLK_DEV_ATARAID is not set
+# CONFIG_BLK_DEV_ATARAID_PDC is not set
+# CONFIG_BLK_DEV_ATARAID_HPT is not set
+
+#
+# Alternate 1394 support
+#
+# CONFIG_X1394 is not set
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI=y
+
+#
+# Alternate SCSI support
+#
+CONFIG_XSCSI_DKSC=y
+# CONFIG_XSCSI_QLFC is not set
+# CONFIG_XSCSI_QL is not set
+# CONFIG_XSCSI_SBP2 is not set
+
+#
+# SCSI support
+#
+CONFIG_SCSI=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+CONFIG_SD_EXTRA_DEVS=40
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+# CONFIG_SCSI_DEBUG_QUEUES is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_7000FASST is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AHA1542 is not set
+# CONFIG_SCSI_AHA1740 is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_AM53C974 is not set
+# CONFIG_SCSI_MEGARAID is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_CPQFCTS is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_EATA_DMA is not set
+# CONFIG_SCSI_EATA_PIO is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_NCR53C7xx is not set
+# CONFIG_SCSI_NCR53C8XX is not set
+# CONFIG_SCSI_SYM53C8XX is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_PCI2000 is not set
+# CONFIG_SCSI_PCI2220I is not set
+# CONFIG_SCSI_PSI240I is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_ISP is not set
+CONFIG_SCSI_QLOGIC_FC=y
+# CONFIG_SCSI_QLOGIC_FC_FIRMWARE is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLOGIC_QLA2100 is not set
+# CONFIG_SCSI_SIM710 is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_U14_34F is not set
+# CONFIG_SCSI_DEBUG is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+
+#
+# ARCnet devices
+#
+# CONFIG_ARCNET is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_ETHERTAP is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+# CONFIG_SUNLANCE is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNBMAC is not set
+# CONFIG_SUNQE is not set
+# CONFIG_SUNLANCE is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_LANCE is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_NET_POCKET is not set
+
+#
+# Ethernet (1000 Mbit)
+#
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_MYRI_SBUS is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PLIP is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+
+#
+# Wireless LAN (non-hamradio)
+#
+# CONFIG_NET_RADIO is not set
+
+#
+# Token Ring devices
+#
+# CONFIG_TR is not set
+# CONFIG_NET_FC is not set
+# CONFIG_RCPCI is not set
+# CONFIG_SHAPER is not set
+
+#
+# Wan interfaces
+#
+# CONFIG_WAN is not set
+
+#
+# Amateur Radio support
+#
+# CONFIG_HAMRADIO is not set
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# CD-ROM drivers (not for SCSI or IDE/ATAPI drives)
+#
+# CONFIG_CD_NO_IDESCSI is not set
+
+#
+# Input core support
+#
+# CONFIG_INPUT is not set
+# CONFIG_INPUT_KEYBDEV is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_SERIAL=y
+# CONFIG_SERIAL_CONSOLE is not set
+# CONFIG_SERIAL_EXTENDED is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+CONFIG_UNIX98_PTYS=y
+CONFIG_UNIX98_PTY_COUNT=256
+
+#
+# I2C support
+#
+# CONFIG_I2C is not set
+
+#
+# Mice
+#
+# CONFIG_BUSMOUSE is not set
+# CONFIG_MOUSE is not set
+
+#
+# Joysticks
+#
+# CONFIG_INPUT_GAMEPORT is not set
+
+#
+# Input core support is needed for gameports
+#
+
+#
+# Input core support is needed for joysticks
+#
+# CONFIG_QIC02_TAPE is not set
+
+#
+# Watchdog Cards
+#
+# CONFIG_WATCHDOG is not set
+# CONFIG_INTEL_RNG is not set
+# CONFIG_NVRAM is not set
+# CONFIG_RTC is not set
+CONFIG_EFI_RTC=y
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# Ftape, the floppy tape device driver
+#
+# CONFIG_FTAPE is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+
+#
+# Multimedia devices
+#
+# CONFIG_VIDEO_DEV is not set
+
+#
+# File systems
+#
+CONFIG_QUOTA=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_ADFS_FS is not set
+# CONFIG_ADFS_FS_RW is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_BFS_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+# CONFIG_UMSDOS_FS is not set
+CONFIG_VFAT_FS=y
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_TMPFS=y
+# CONFIG_RAMFS is not set
+CONFIG_ISO9660_FS=y
+# CONFIG_JOLIET is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_NTFS_FS is not set
+# CONFIG_NTFS_RW is not set
+# CONFIG_HPFS_FS is not set
+CONFIG_PROC_FS=y
+CONFIG_DEVFS_FS=y
+CONFIG_DEVFS_MOUNT=y
+CONFIG_DEVFS_DEBUG=y
+CONFIG_DEVPTS_FS=y
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX4FS_RW is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UDF_FS is not set
+# CONFIG_UDF_RW is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_UFS_FS_WRITE is not set
+CONFIG_XFS_SUPPORT=y
+
+#
+# Network File Systems
+#
+# CONFIG_CODA_FS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_ROOT_NFS is not set
+CONFIG_NFSD=y
+CONFIG_NFSD_V3=y
+CONFIG_SUNRPC=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+# CONFIG_SMB_FS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_NCPFS_PACKET_SIGNING is not set
+# CONFIG_NCPFS_IOCTL_LOCKING is not set
+# CONFIG_NCPFS_STRONG is not set
+# CONFIG_NCPFS_NFS_NS is not set
+# CONFIG_NCPFS_OS2_NS is not set
+# CONFIG_NCPFS_SMALLDOS is not set
+# CONFIG_NCPFS_NLS is not set
+# CONFIG_NCPFS_EXTRAS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_SMB_NLS is not set
+CONFIG_NLS=y
+
+#
+# Native Language Support
+#
+CONFIG_NLS_DEFAULT="n"
+# CONFIG_NLS_CODEPAGE_437 is not set
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Sound
+#
+# CONFIG_SOUND is not set
+
+#
+# USB support
+#
+# CONFIG_USB is not set
+
+#
+# USB Controllers
+#
+# CONFIG_USB_UHCI is not set
+# CONFIG_USB_UHCI_ALT is not set
+# CONFIG_USB_OHCI is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_BLUETOOTH is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_DPCM is not set
+# CONFIG_USB_STORAGE_HP8200e is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+
+#
+# USB Human Interface Devices (HID)
+#
+
+#
+#   Input core support is needed for USB HID
+#
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_DC2XX is not set
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_SCANNER is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_HPUSBSCSI is not set
+
+#
+# USB Multimedia devices
+#
+
+#
+#   Video4Linux support is needed for USB Multimedia device support
+#
+
+#
+# USB Network adaptors
+#
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_CDCETHER is not set
+# CONFIG_USB_USBNET is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_USS720 is not set
+
+#
+# USB Serial Converter support
+#
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
+# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_RIO500 is not set
+
+#
+# IEEE 1394 (FireWire) support (EXPERIMENTAL)
+#
+# CONFIG_IEEE1394 is not set
+
+#
+# Bluetooth support
+#
+# CONFIG_BLUEZ is not set
+
+#
+# Kernel hacking
+#
+CONFIG_DEBUG_KERNEL=y
+CONFIG_IA64_PRINT_HAZARDS=y
+# CONFIG_DISABLE_VHPT is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_IA64_EARLY_PRINTK=y
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_IA64_DEBUG_CMPXCHG is not set
+# CONFIG_IA64_DEBUG_IRQ is not set
+# CONFIG_KDB is not set
+# CONFIG_KDB_MODULES is not set
+CONFIG_KALLSYMS=y
diff -Nru a/arch/ia64/sn/fakeprom/Makefile b/arch/ia64/sn/fakeprom/Makefile
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/Makefile	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,30 @@
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+#  Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+#
+
+TOPDIR=../../../..
+HPATH           = $(TOPDIR)/include
+
+LIB     = ../../lib/lib.a
+
+OBJ=fpromasm.o main.o  fw-emu.o fpmem.o klgraph_init.o
+obj-y=fprom
+
+fprom: $(OBJ)
+	$(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB)
+
+.S.o:
+	$(CC)  -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+.c.o:
+	$(CC)  $(CFLAGS) $(CFLAGS_KERNEL) -c -o $*.o $<
+
+clean:
+	rm -f *.o fprom
+
+
+include $(TOPDIR)/Rules.make
+
diff -Nru a/arch/ia64/sn/fakeprom/README b/arch/ia64/sn/fakeprom/README
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/README	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,85 @@
+This directory contains the files required to build
+the fake PROM image that is currently being used to
+boot IA64 kernels running under the SGI Medusa kernel.
+
+The FPROM currently provides the following functions:
+
+	- PAL emulation for all PAL calls we've made so far.
+	- SAL emulation for all SAL calls we've made so far.
+	- EFI emulation for all EFI calls we've made so far.
+	- builds the "ia64_bootparam" structure that is
+	  passed to the kernel from SAL. This structure 
+	  shows the cpu & memory configurations.
+	- supports medusa boottime options for changing
+	  the number of cpus present
+	- supports medusa boottime options for changing
+	  the memory configuration.
+
+
+
+At some point, this fake PROM will be replaced by the
+real PROM.
+
+
+
+
+To build a fake PROM, cd to this directory & type:
+
+	make
+
+This will (or should) build a fake PROM named "fprom".
+
+
+
+
+Use this fprom image when booting the Medusa simulator. The
+control file used to boot Medusa should include the 
+following lines:
+
+	load fprom
+	load vmlinux
+	sr pc 0x100000
+	sr g 9 <address of kernel _start function> #(currently 0xe000000000520000)
+
+NOTE: There is a script "runsim" in this directory that can be used to
+simplify setting up an environment for running under Medusa.
+
+
+
+
+The following parameters may be passed to the fake PROM to
+control the PAL/SAL/EFI parameters passed to the kernel:
+
+	GR[8] = # of cpus
+	GR[9] = address of primary entry point into the kernel
+	GR[20] = memory configuration for node 0
+	GR[21] = memory configuration for node 1
+	GR[22] = memory configuration for node 2
+	GR[23] = memory configuration for node 3
+
+
+Registers GR[20] - GR[23] contain information to specify the
+amount of memory present on nodes 0-3.
+
+  - if nothing is specified (all registers are 0), the configuration
+    defaults to 8 MB on node 0.
+
+  - a mem config entry for node N is passed in GR[20+N]
+
+  - a mem config entry consists of 8 hex digits. Each digit gives the
+    amount of physical memory available on the node starting at
+    1GB*<dn>, where dn is the digit number. The amount of memory
+    is 8MB*2**<d>. (If <d> = 0, the memory size is 0).
+
+    SN1 doesnt support dimms this small but small memory systems 
+    boot faster on Medusa.
+
+
+
+An example helps a lot. The following specifies that node 0 has
+physical memory 0 to 8MB and 1GB to 1GB+32MB, and that node 1 has
+64MB starting at address 0 of the node which is 8GB.
+
+      gr[20] = 0x21           # 0 to 8MB, 1GB to 1GB+32MB
+      gr[21] = 0x4            # 8GB to 8GB+64MB
+
diff -Nru a/arch/ia64/sn/fakeprom/fpmem.c b/arch/ia64/sn/fakeprom/fpmem.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/fpmem.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,257 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+/*
+ * FPROM EFI memory descriptor build routines
+ *
+ * 	- Routines to build the EFI memory descriptor map
+ * 	- Should also be usable by the SGI SN1 prom to convert
+ * 	  klconfig to efi_memmap
+ */
+
+#include <linux/config.h>
+#include <asm/efi.h>
+#include "fpmem.h"
+
+/*
+ * args points to a layout in memory like this
+ *
+ *		32 bit		32 bit
+ *
+ * 		numnodes	numcpus
+ *
+ *		16 bit   16 bit		   32 bit
+ *		nasid0	cpuconf		membankdesc0
+ *		nasid1	cpuconf		membankdesc1
+ *			   .
+ *			   .
+ *			   .
+ *			   .
+ *			   .
+ */
+
+sn_memmap_t	*sn_memmap ;
+sn_config_t	*sn_config ;
+
+/*
+ * There is a hole in the node 0 address space. Dont put it
+ * in the memory map
+ */
+#define NODE0_HOLE_SIZE         (20*MB)
+#define NODE0_HOLE_END          (4UL*GB)
+
+#define	MB			(1024*1024)
+#define GB			(1024*MB)
+#define KERNEL_SIZE		(4*MB)
+#define PROMRESERVED_SIZE	(1*MB)
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define PHYS_ADDRESS(_n, _x)		(((long)_n<<33L) | (long)_x)
+#define MD_BANK_SHFT 30
+#else
+#define PHYS_ADDRESS(_n, _x)		(((long)_n<<38L) | (long)_x | 0x3000000000UL)
+#define MD_BANK_SHFT 34
+#endif
+
+/*
+ * For SN, this may not take an arg and gets the numnodes from 
+ * the prom variable or by traversing klcfg or promcfg
+ */
+int
+GetNumNodes(void)
+{
+	return sn_config->nodes;
+}
+
+int
+GetNumCpus(void)
+{
+	return sn_config->cpus;
+}
+
+/* For SN1, get the index th nasid */
+
+int
+GetNasid(int index)
+{
+	return sn_memmap[index].nasid ;
+}
+
+node_memmap_t
+GetMemBankInfo(int index)
+{
+	return sn_memmap[index].node_memmap ;
+}
+
+int
+IsCpuPresent(int cnode, int cpu)
+{
+	return  sn_memmap[cnode].cpuconfig & (1<<cpu);
+}
+
+
+/*
+ * Made this into an explicit case statement so that
+ * we can assign specific properties to banks like bank0
+ * actually disabled etc.
+ */
+
+#ifdef CONFIG_IA64_SGI_SN1
+int
+IsBankPresent(int index, node_memmap_t nmemmap)
+{
+	switch (index) {
+		case 0:return nmemmap.b0;
+		case 1:return nmemmap.b1;
+		case 2:return nmemmap.b2;
+		case 3:return nmemmap.b3;
+		case 4:return nmemmap.b4;
+		case 5:return nmemmap.b5;
+		case 6:return nmemmap.b6;
+		case 7:return nmemmap.b7;
+		default:return -1 ;
+	}
+}
+
+int
+GetBankSize(int index, node_memmap_t nmemmap)
+{
+        switch (index) {
+                case 0:
+                case 1:return nmemmap.b01size;
+                case 2:
+                case 3:return nmemmap.b23size;
+                case 4:
+                case 5:return nmemmap.b45size;
+                case 6:
+                case 7:return nmemmap.b67size;
+                default:return -1 ;
+        }
+}
+
+#else
+int
+IsBankPresent(int index, node_memmap_t nmemmap)
+{
+	switch (index) {
+		case 0:return nmemmap.ena0;
+		case 1:return nmemmap.ena1;
+		case 2:return nmemmap.ena2;
+		case 3:return nmemmap.ena3;
+		default:return -1 ;
+	}
+}
+
+int
+GetBankSize(int index, node_memmap_t nmemmap)
+{
+        switch (index) {
+                case 0:return (long)nmemmap.b0size + nmemmap.b0dou;
+                case 1:return (long)nmemmap.b1size + nmemmap.b1dou;
+                case 2:return (long)nmemmap.b2size + nmemmap.b2dou;
+                case 3:return (long)nmemmap.b3size + nmemmap.b3dou;
+                default:return -1 ;
+        }
+}
+
+#endif
+
+void
+build_mem_desc(efi_memory_desc_t *md, int type, long paddr, long numbytes)
+{
+        md->type = type;
+        md->phys_addr = paddr;
+        md->virt_addr = 0;
+        md->num_pages = numbytes >> 12;
+        md->attribute = EFI_MEMORY_WB;
+}
+
+int
+build_efi_memmap(void *md, int mdsize)
+{
+	int		numnodes = GetNumNodes() ;
+	int		cnode,bank ;
+	int		nasid ;
+	node_memmap_t	membank_info ;
+	int		bsize;
+	int		count = 0 ;
+	long		paddr, hole, numbytes;
+
+
+	for (cnode=0;cnode<numnodes;cnode++) {
+		nasid = GetNasid(cnode) ;
+		membank_info = GetMemBankInfo(cnode) ;
+		for (bank=0;bank<PLAT_CLUMPS_PER_NODE;bank++) {
+			if (IsBankPresent(bank, membank_info)) {
+				bsize = GetBankSize(bank, membank_info) ;
+                                paddr = PHYS_ADDRESS(nasid, (long)bank<<MD_BANK_SHFT);
+                                numbytes = BankSizeBytes(bsize);
+#ifdef CONFIG_IA64_SGI_SN2
+				numbytes = numbytes * 31 / 32;
+#endif
+
+                                /*
+                                 * Check for the node 0 hole. Since banks cant
+                                 * span the hole, we only need to check if the end of
+                                 * the range is the end of the hole.
+                                 */
+                                if (paddr+numbytes == NODE0_HOLE_END)
+                                        numbytes -= NODE0_HOLE_SIZE;
+                                /*
+                                 * UGLY hack - we must skip overr the kernel and
+                                 * PROM runtime services but we dont exactly where it is.
+                                 * So lets just reserve:
+				 *	node 0
+				 *		0-1MB for PAL
+				 *		1-4MB for SAL
+				 *	node 1-N
+				 *		0-1 for SAL
+                                 */
+                                if (bank == 0) {
+					if (cnode == 0) {
+						hole = 1*1024*1024;
+						build_mem_desc(md, EFI_PAL_CODE, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+						hole = 3*1024*1024;
+						build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+					} else {
+						hole = PROMRESERVED_SIZE;
+                                        	build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
+						numbytes -= hole;
+                                        	paddr += hole;
+			        		count++ ;
+                                        	md += mdsize;
+					}
+                                }
+                                build_mem_desc(md, EFI_CONVENTIONAL_MEMORY, paddr, numbytes);
+
+			        md += mdsize ;
+			        count++ ;
+			}
+		}
+	}
+	return count ;
+}
+
+void
+build_init(unsigned long args)
+{
+	sn_config = (sn_config_t *) (args);	
+	sn_memmap = (sn_memmap_t *)(args + 8) ; /* SN equiv for this is */
+						/* init to klconfig start */
+}
diff -Nru a/arch/ia64/sn/fakeprom/fpmem.h b/arch/ia64/sn/fakeprom/fpmem.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/fpmem.h	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,98 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Structure of the mem config of the node as a SN1 MI reg
+ * Medusa supports this reg config.
+ *
+ * BankSize nibble to bank size mapping
+ *
+ *      1 - 64 MB
+ *      2 - 128 MB
+ *      3 - 256 MB
+ *      4 - 512 MB
+ *      5 - 1024 MB (1GB)
+ */
+
+#define MBSHIFT				20
+
+#ifdef CONFIG_IA64_SGI_SN1
+typedef struct node_memmap_s
+{
+        unsigned int    b0      :1,     /* 0 bank 0 present */
+                        b1      :1,     /* 1 bank 1 present */
+                        r01     :2,     /* 2-3 reserved */
+                        b01size :4,     /* 4-7 Size of bank 0 and 1 */
+                        b2      :1,     /* 8 bank 2 present */
+                        b3      :1,     /* 9 bank 3 present */
+                        r23     :2,     /* 10-11 reserved */
+                        b23size :4,     /* 12-15 Size of bank 2 and 3 */
+                        b4      :1,     /* 16 bank 4 present */
+                        b5      :1,     /* 17 bank 5 present */
+                        r45     :2,     /* 18-19 reserved */
+                        b45size :4,     /* 20-23 Size of bank 4 and 5 */
+                        b6      :1,     /* 24 bank 6 present */
+                        b7      :1,     /* 25 bank 7 present */
+                        r67     :2,     /* 26-27 reserved */
+                        b67size :4;     /* 28-31 Size of bank 6 and 7 */
+} node_memmap_t ;
+
+/* Support the medusa hack for 8M/16M/32M nodes */
+#define SN1_BANK_SIZE_SHIFT		(MBSHIFT+6)     /* 64 MB */
+#define BankSizeBytes(bsize)            ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
+                                         (1<<((bsize-9)+MBSHIFT)))
+#else
+typedef struct node_memmap_s
+{
+        unsigned int    b0size  :3,     /* 0-2   bank 0 size */
+                        b0dou   :1,     /* 3     bank 0 is 2-sided */
+                        ena0    :1,     /* 4     bank 0 enabled */
+                        r0      :3,     /* 5-7   reserved */
+        		b1size  :3,     /* 8-10  bank 1 size */
+                        b1dou   :1,     /* 11    bank 1 is 2-sided */
+                        ena1    :1,     /* 12    bank 1 enabled */
+                        r1      :3,     /* 13-15 reserved */
+        		b2size  :3,     /* 16-18 bank 2 size */
+                        b2dou   :1,     /* 19    bank 1 is 2-sided */
+                        ena2    :1,     /* 20    bank 2 enabled */
+                        r2      :3,     /* 21-23 reserved */
+        		b3size  :3,     /* 24-26 bank 3 size */
+                        b3dou   :1,     /* 27    bank 3 is 2-sided */
+                        ena3    :1,     /* 28    bank 3 enabled */
+                        r3      :3;     /* 29-31 reserved */
+} node_memmap_t ;
+
+#define SN2_BANK_SIZE_SHIFT		(MBSHIFT+6)     /* 64 MB */
+#define BankSizeBytes(bsize)            (1UL<<((bsize)+SN2_BANK_SIZE_SHIFT))
+#endif
+
+typedef struct sn_memmap_s
+{
+	short		nasid ;
+	short		cpuconfig;
+	node_memmap_t 	node_memmap ;
+} sn_memmap_t ;
+
+typedef struct sn_config_s
+{
+	int		cpus;
+	int		nodes;
+	sn_memmap_t	memmap[1];		/* start of array */
+} sn_config_t;
+
+
+
+extern void build_init(unsigned long);
+extern int build_efi_memmap(void *, int);
+extern int GetNumNodes(void);
+extern int GetNumCpus(void);
+extern int IsCpuPresent(int, int);
+extern int GetNasid(int);
diff -Nru a/arch/ia64/sn/fakeprom/fprom.lds b/arch/ia64/sn/fakeprom/fprom.lds
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/fprom.lds	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,96 @@
+
+OUTPUT_FORMAT("elf64-ia64-little")
+OUTPUT_ARCH(ia64)
+ENTRY(_start)
+SECTIONS
+{
+  v = 0x0000000000000000 ;	/* this symbol is here to make debugging with kdb easier... */
+
+  . = (0x000000000000000  + 0x100000) ;
+
+  _text = .;
+  .text : AT(ADDR(.text) - 0x0000000000000000 )
+    {
+	*(__ivt_section)
+	/* these are not really text pages, but the zero page needs to be in a fixed location: */
+	*(__special_page_section)
+	__start_gate_section = .;
+	*(__gate_section)
+	__stop_gate_section = .;
+	*(.text)
+    }
+
+  /* Global data */
+  _data = .;
+
+  .rodata : AT(ADDR(.rodata) - 0x0000000000000000 )
+	{ *(.rodata) *(.rodata.*) }
+  .opd : AT(ADDR(.opd) - 0x0000000000000000 )
+	{ *(.opd) }
+  .data : AT(ADDR(.data) - 0x0000000000000000 )
+	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
+
+  __gp = ALIGN (8) + 0x200000;
+
+  .got : AT(ADDR(.got) - 0x0000000000000000 )
+	{ *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata : AT(ADDR(.sdata) - 0x0000000000000000 )
+	{ *(.sdata) }
+  _edata  =  .;
+  _bss = .;
+  .sbss : AT(ADDR(.sbss) - 0x0000000000000000 )
+	{ *(.sbss) *(.scommon) }
+  .bss : AT(ADDR(.bss) - 0x0000000000000000 )
+	{ *(.bss) *(COMMON) }
+  . = ALIGN(64 / 8);
+  _end = .;
+
+  /* Sections to be discarded */
+  /DISCARD/ : {
+	*(.text.exit)
+	*(.data.exit)
+	}
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* These must appear regardless of  .  */
+  /* Discard them for now since Intel SoftSDV cannot handle them.
+  .comment 0 : { *(.comment) }
+  .note 0 : { *(.note) }
+  */
+  /DISCARD/ : { *(.comment) }
+  /DISCARD/ : { *(.note) }
+}
diff -Nru a/arch/ia64/sn/fakeprom/fpromasm.S b/arch/ia64/sn/fakeprom/fpromasm.S
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/fpromasm.S	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,403 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *   (Code copied from or=ther files)
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+
+#define __ASSEMBLY__ 1
+#include <linux/config.h>
+#include <asm/processor.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+
+/*
+ * This file contains additional set up code that is needed to get going on
+ * Medusa.  This code should disappear once real hw is available.
+ *
+ * On entry to this routine, the following register values are assumed:
+ *
+ *	gr[8]	- BSP cpu
+ *	pr[9]	- kernel entry address
+ *	pr[10]	- cpu number on the node
+ *
+ * NOTE:
+ *   This FPROM may be loaded/executed at an address different from the
+ *   address that it was linked at. The FPROM is linked to run on node 0
+ *   at address 0x100000. If the code in loaded into another node, it
+ *   must be loaded at offset 0x100000 of the node. In addition, the
+ *   FPROM does the following things:
+ *		- determine the base address of the node it is loaded on
+ *		- add the node base to _gp.
+ *		- add the node base to all addresses derived from "movl" 
+ *		  instructions. (I couldnt get GPREL addressing to work)
+ *		  (maybe newer versions of the tools will support this)
+ *		- scan the .got section and add the node base to all
+ *		  pointers in this section.
+ *		- add the node base to all physical addresses in the
+ *		  SAL/PAL/EFI table built by the C code. (This is done
+ *		  in the C code - not here)
+ *		- add the node base to the TLB entries for vmlinux
+ */
+
+#define KERNEL_BASE	0xe000000000000000
+#define BOOT_PARAM_ADDR 0x40000
+
+
+/* 
+ * ar.k0 gets set to IOPB_PA value, on 460gx chipset it should 
+ * be 0x00000ffffc000000, but on snia we use the (inverse swizzled)
+ * IOSPEC_BASE value
+ */
+#ifdef CONFIG_IA64_SGI_SN1
+#define IOPB_PA		0xc0000FFFFC000000
+#else
+#define IOPB_PA		0xc000000fcc000000
+#endif
+
+#define RR_RID		8
+
+
+
+// ====================================================================================	
+        .text
+        .align 16
+	.global _start
+	.proc _start
+_start:
+
+// Setup psr and rse for system init
+	mov		psr.l = r0;;
+	srlz.d;;
+	invala
+	mov		ar.rsc = r0;;
+	loadrs
+	;;
+
+// Isolate node number we are running on.
+	mov		r6 = ip;;
+#ifdef CONFIG_IA64_SGI_SN1
+	shr		r5 = r6,33;;			// r5 = node number
+	shl		r6 = r5,33			// r6 = base memory address of node
+#else
+	shr		r5 = r6,38			// r5 = node number
+	dep		r6 = 0,r6,0,36			// r6 = base memory address of node
+
+#endif
+
+
+// Set & relocate gp.
+	movl		r1= __gp;;			// Add base memory address
+	or 		r1 = r1,r6			// Relocate to boot node
+
+// Lets figure out who we are & put it in the LID register.
+#ifdef CONFIG_IA64_SGI_SN2
+// On SN2, we (currently) pass the cpu number in r10 at boot
+	and		r25=3,r10;;
+	movl		r16=0x8000008110000400		// Allow IPIs
+	mov		r17=-1;;
+	st8		[r16]=r17
+	movl		r16=0x8000008110060580;;	// SHUB_ID
+	ld8		r27=[r16];;
+	extr.u		r27=r27,32,11;;
+	shl 		r26=r25,28;;			// Align local cpu# to lid.eid
+	shl 		r27=r27,16;;			// Align NASID to lid.id
+	or  		r26=r26,r27;;			// build the LID
+#else
+// The BR_PI_SELF_CPU_NUM register gives us a value of 0-3.
+// This identifies the cpu on the node. 
+// Merge the cpu number with the NASID to generate the LID.
+	movl		r24=0x80000a0001000020;;	// BR_PI_SELF_CPU_NUM
+	ld8 		r25=[r24]			// Fetch PI_SELF
+	movl		r27=0x80000a0001600000;;	// Fetch REVID to get local NASID
+	ld8 		r27=[r27];;
+	extr.u		r27=r27,32,8;;
+	shl 		r26=r25,16;;			// Align local cpu# to lid.eid
+	shl 		r27=r27,24;;			// Align NASID to lid.id
+	or  		r26=r26,r27;;			// build the LID
+#endif
+	mov 		cr.lid=r26			// Now put in in the LID register
+
+	movl		r2=FPSR_DEFAULT;;
+	mov 		ar.fpsr=r2
+	movl		sp = bootstacke-16;;
+	or 		sp = sp,r6			// Relocate to boot node			
+
+// Save the NASID that we are loaded on.
+	movl		r2=base_nasid;;			// Save base_nasid for C code
+	or 		r2 = r2,r6;;			// Relocate to boot node
+  	st8 		[r2]=r5				// Uncond st8 - same on all cpus
+
+// Save the kernel entry address. It is passed in r9 on one of
+// the cpus.
+	movl		r2=bsp_entry_pc
+	cmp.ne		p6,p0=r9,r0;;
+	or 		r2 = r2,r6;;			// Relocate to boot node
+(p6)  	st8 		[r2]=r9				// Uncond st8 - same on all cpus
+
+
+// The following can ONLY be done by 1 cpu. Lets set a lock - the
+// cpu that gets it does the initilization. The rest just spin waiting
+// til initilization is complete.
+	movl		r22 = initlock;;
+	or		r22 = r22,r6			// Relocate to boot node
+	mov		r23 = 1;;
+	xchg8		r23 = [r22],r23;;
+	cmp.eq 		p6,p0 = 0,r23
+(p6)	br.cond.spnt.few init
+1:	ld4		r23 = [r22];;
+	cmp.eq		p6,p0 = 1,r23
+(p6)	br.cond.sptk	1b
+	br		initx
+
+// Add base address of node memory to each pointer in the .got section.
+init:	movl		r16 = _GLOBAL_OFFSET_TABLE_;;
+	or		r16 = r16,r6;;			// Relocate to boot node
+1: 	ld8		r17 = [r16];;
+	cmp.eq		p6,p7=0,r17
+(p6)	br.cond.sptk.few.clr 2f;;
+	or		r17 = r17,r6;;			// Relocate to boot node
+	st8		[r16] = r17,8
+	br		1b
+2:
+	mov		r23 = 2;;			// All done, release the spinning cpus
+	st4		[r22] = r23
+initx:
+
+//
+//	I/O-port space base address:
+//
+	movl		r2 = IOPB_PA;;
+	mov		ar.k0 = r2
+
+
+// Now call main & pass it the current LID value.
+	alloc 		r0=ar.pfs,0,0,2,0
+	mov    		r32=r26
+	mov   		r33=r8;;
+	br.call.sptk.few rp=fmain
+	
+// Initialize Region Registers
+//
+        mov             r10 = r0
+        mov             r2 = (13<<2)
+        mov             r3 = r0;;
+1:      cmp4.gtu        p6,p7 = 7, r3
+        dep             r10 = r3, r10, 61, 3
+        dep             r2 = r3, r2, RR_RID, 4;;
+(p7)    dep             r2 = 0, r2, 0, 1;;
+(p6)    dep             r2 = -1, r2, 0, 1;;
+        mov             rr[r10] = r2
+        add             r3 = 1, r3;;
+        srlz.d;;
+        cmp4.gtu        p6,p0 = 8, r3
+(p6)    br.cond.sptk.few.clr 1b
+
+//
+// Return value indicates if we are the BSP or AP.
+// 	   1 = BSP, 0 = AP
+	mov             cr.tpr=r0;;
+	cmp.eq		p6,p0=r8,r0
+(p6)	br.cond.spnt	slave
+
+//
+// Go to kernel C startup routines
+//	Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
+//	This is the only way to set them.
+
+	movl		r28=BOOT_PARAM_ADDR
+	movl		r2=bsp_entry_pc;;
+	or 		r28 = r28,r6;;			// Relocate to boot node
+	or 		r2 = r2,r6;;			// Relocate to boot node
+	ld8		r2=[r2];;
+	or		r2=r2,r6;;
+	dep		r2=0,r2,61,3;;			// convert to phys mode
+
+//
+// Turn on address translation, interrupt collection, psr.ed, protection key.
+// Interrupts (PSR.i) are still off here.
+//
+
+        movl            r3 = (  IA64_PSR_BN | \
+                                IA64_PSR_AC | \
+                                IA64_PSR_DB | \
+                                IA64_PSR_DA | \
+                                IA64_PSR_IC   \
+                             )
+        ;;
+        mov             cr.ipsr = r3
+
+//
+// Go to kernel C startup routines
+//      Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
+//      This is the only way to set them.
+
+	mov		r8=r28;;
+	bsw.1		;;
+	mov		r28=r8;;
+	bsw.0		;;
+        mov             cr.iip = r2
+        srlz.d;;
+        rfi;;
+
+	.endp		_start
+
+
+
+// Slave processors come here to spin til they get an interrupt. Then they launch themselves to
+// the place ap_entry points. No initialization is necessary - the kernel makes no
+// assumptions about state on this entry.
+//	Note: should verify that the interrupt we got was really the ap_wakeup
+//	      interrupt but this should not be an issue on medusa
+slave:
+	nop.i		0x8beef				// Medusa - put cpu to sleep til interrupt occurs
+	mov		r8=cr.irr0;;			// Check for interrupt pending.
+	cmp.eq		p6,p0=r8,r0
+(p6)	br.cond.sptk	slave;;
+
+	mov		r8=cr.ivr;;			// Got one. Must read ivr to accept it
+	srlz.d;;
+	mov		cr.eoi=r0;;			// must write eoi to clear
+	movl		r8=ap_entry;;			// now jump to kernel entry
+	or 		r8 = r8,r6;;			// Relocate to boot node
+	ld8		r9=[r8],8;;
+	ld8		r1=[r8]
+	mov		b0=r9;;
+	br		b0
+
+// Here is the kernel stack used for the fake PROM
+	.bss
+	.align		16384
+bootstack:
+	.skip		16384
+bootstacke:
+initlock:
+	data4
+
+
+
+//////////////////////////////////////////////////////////////////////////////////////////////////////////
+// This code emulates the PAL. Only essential interfaces are emulated.
+
+
+	.text
+	.global	pal_emulator
+	.proc	pal_emulator
+pal_emulator:
+	mov	r8=-1
+
+	mov	r9=256
+	;;
+	cmp.gtu p6,p7=r9,r28		/* r28 <= 255? */
+(p6)	br.cond.sptk.few static
+	;;
+	mov	r9=512
+	;;
+	cmp.gtu p6,p7=r9,r28
+(p6)	br.cond.sptk.few stacked
+	;;
+
+static:	cmp.eq	p6,p7=6,r28		/* PAL_PTCE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9=0x100000000			/* tc.base */
+	movl	r10=0x0000000200000003		/* count[0], count[1] */
+	movl	r11=0x1000000000002000		/* stride[0], stride[1] */
+	;;
+
+1:	cmp.eq	p6,p7=14,r28		/* PAL_FREQ_RATIOS */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9 =0x100000064			/* proc_ratio (1/100) */
+	movl	r10=0x100000100			/* bus_ratio<<32 (1/256) */
+	movl	r11=0x10000000a			/* itc_ratio<<32 (1/100) */
+	;;
+
+1:	cmp.eq	p6,p7=8,r28		/* PAL_VM_SUMMARY */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+#ifdef CONFIG_IA64_SGI_SN1
+	movl	r9=0x0203083001151059
+	movl	r10=0x1232
+#else
+	movl	r9=0x0203083001151065
+	movl	r10=0x183f
+#endif
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=19,r28		/* PAL_RSE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+	movl	r9=0x60
+	movl	r10=0x0
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=15,r28		/* PAL_PERF_MON_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0
+	movl	r9=0x08122004
+	movl	r10=0x0
+	movl	r11=0
+	mov	r2=ar.lc
+	mov	r3=16;;
+	mov	ar.lc=r3
+	mov	r3=r29;;
+5:	st8	[r3]=r0,8
+	br.cloop.sptk.few 5b;;
+	mov	ar.lc=r2
+	mov	r3=r29
+	movl	r2=0x1fff;;			/* PMC regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0x3ffff;;			/* PMD regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0xf0;;			/* cycle regs */
+	st8	[r3]=r2
+	add	r3=32,r3
+	movl	r2=0x10;;			/* retired regs */
+	st8	[r3]=r2
+	;;
+
+1:	cmp.eq	p6,p7=19,r28		/* PAL_RSE_INFO */
+(p7)	br.cond.sptk.few 1f
+	movl	r8=0				/* status = 0 */
+	movl	r9=96				/* num phys stacked */
+	movl	r10=0				/* hints */
+	movl	r11=0
+	;;
+
+1:	cmp.eq	p6,p7=1,r28		/* PAL_CACHE_FLUSH */
+(p7)	br.cond.sptk.few 1f
+	mov	r9=ar.lc
+	movl	r8=524288				/* flush 512k million cache lines (16MB) */
+	;;
+	mov	ar.lc=r8
+	movl	r8=0xe000000000000000
+	;;
+.loop:	fc	r8
+	add	r8=32,r8
+	br.cloop.sptk.few .loop
+	sync.i
+	;;
+	srlz.i
+	;;
+	mov	ar.lc=r9
+	mov	r8=r0
+1:	br.cond.sptk.few rp
+
+stacked:
+	br.ret.sptk.few rp
+
+	.endp pal_emulator
+
diff -Nru a/arch/ia64/sn/fakeprom/fw-emu.c b/arch/ia64/sn/fakeprom/fw-emu.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/fw-emu.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,829 @@
+/*
+ * PAL & SAL emulation.
+ *
+ * Copyright (C) 1998-2000 Hewlett-Packard Co
+ * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+#include <linux/config.h>
+#include <asm/efi.h>
+#include <asm/pal.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/processor.h>
+#include <asm/sn/sn_cpuid.h>
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+#endif
+#include <asm/acpi-ext.h>
+#include "fpmem.h"
+
+#define zzACPI_1_0	1		/* Include ACPI 1.0 tables */
+
+#define OEMID			"SGI"
+#ifdef CONFIG_IA64_SGI_SN1
+#define PRODUCT			"SN1"
+#define PROXIMITY_DOMAIN(nasid)	(nasid)
+#else
+#define PRODUCT			"SN2"
+#define PROXIMITY_DOMAIN(nasid)	(((nasid)>>1) & 255)
+#endif
+
+#define MB	(1024*1024UL)
+#define GB	(MB*1024UL)
+#define BOOT_PARAM_ADDR 0x40000
+#define MAX(i,j)		((i) > (j) ? (i) : (j))
+#define MIN(i,j)		((i) < (j) ? (i) : (j))
+#define ABS(i)			((i) > 0   ? (i) : -(i))
+#define ALIGN8(p)		(((long)(p) +7) & ~7)
+
+#define FPROM_BUG()		do {while (1);} while (0)
+#define MAX_SN_NODES		128
+#define MAX_LSAPICS		512
+#define MAX_CPUS		512
+#define MAX_CPUS_NODE		4
+#define CPUS_PER_NODE		4
+#define CPUS_PER_FSB		2
+#define CPUS_PER_FSB_MASK	(CPUS_PER_FSB-1)
+
+#ifdef ACPI_1_0
+#define NUM_EFI_DESCS		3
+#else
+#define NUM_EFI_DESCS		2
+#endif
+
+#define RSDP_CHECKSUM_LENGTH	20
+
+typedef union ia64_nasid_va {
+        struct {
+#if defined(CONFIG_IA64_SGI_SN1)
+                unsigned long off   : 33;       /* intra-region offset */
+		unsigned long nasid :  7;	/* NASID */
+		unsigned long off2  : 21;	/* fill */
+                unsigned long reg   :  3;       /* region number */
+#elif defined(CONFIG_IA64_SGI_SN2)
+                unsigned long off   : 36;       /* intra-region offset */
+		unsigned long attr  :  2;
+		unsigned long nasid : 11;	/* NASID */
+		unsigned long off2  : 12;	/* fill */
+                unsigned long reg   :  3;       /* region number */
+#endif
+        } f;
+        unsigned long l;
+        void *p;
+} ia64_nasid_va;
+
+typedef struct {
+	unsigned long	pc;
+	unsigned long	gp;
+} func_ptr_t;
+ 
+#define IS_VIRTUAL_MODE() 	 ({struct ia64_psr psr; asm("mov %0=psr" : "=r"(psr)); psr.dt;})
+#define ADDR_OF(p)		(IS_VIRTUAL_MODE() ? ((void*)((long)(p)+PAGE_OFFSET)) : ((void*) (p)))
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.l;})
+#elif defined(CONFIG_IA64_SGI_SN2)
+#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.f.attr = 3; _v.l;})
+#endif
+
+/*
+ * The following variables are passed thru registersfrom the configuration file and
+ * are set via the _start function.
+ */
+long		base_nasid;
+long		num_cpus;
+long		bsp_entry_pc=0;
+long		num_nodes;
+long		app_entry_pc;
+int		bsp_lid;
+func_ptr_t	ap_entry;
+
+
+extern void pal_emulator(void);
+static efi_runtime_services_t    *efi_runtime_p;
+static char fw_mem[(  sizeof(efi_system_table_t)
+		    + sizeof(efi_runtime_services_t)
+		    + NUM_EFI_DESCS*sizeof(efi_config_table_t)
+		    + sizeof(struct ia64_sal_systab)
+		    + sizeof(struct ia64_sal_desc_entry_point)
+		    + sizeof(struct ia64_sal_desc_ap_wakeup)
+#ifdef ACPI_1_0
+		    + sizeof(acpi_rsdp_t)
+		    + sizeof(acpi_rsdt_t)
+		    + sizeof(acpi_sapic_t)
+		    + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t))
+#endif
+		    + sizeof(acpi20_rsdp_t)
+		    + sizeof(acpi_xsdt_t)
+		    + sizeof(acpi_slit_t)
+		    +   MAX_SN_NODES*MAX_SN_NODES+8
+		    + sizeof(acpi_madt_t)
+		    +   16*MAX_CPUS
+		    + (1+8*MAX_SN_NODES)*(sizeof(efi_memory_desc_t))
+		    + sizeof(acpi_srat_t)
+		    +   MAX_CPUS*sizeof(srat_cpu_affinity_t)
+		    +   MAX_SN_NODES*sizeof(srat_memory_affinity_t)
+		    + sizeof(ia64_sal_desc_ptc_t) +
+		    + MAX_SN_NODES*sizeof(ia64_sal_ptc_domain_info_t) +
+		    + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) +
+		    + 1024)] __attribute__ ((aligned (8)));
+
+
+static efi_status_t
+efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
+{
+	if (tm) {
+		memset(tm, 0, sizeof(*tm));
+		tm->year = 2000;
+		tm->month = 2;
+		tm->day = 13;
+		tm->hour = 10;
+		tm->minute = 11;
+		tm->second = 12;
+	}
+
+	if (tc) {
+		tc->resolution = 10;
+		tc->accuracy = 12;
+		tc->sets_to_zero = 1;
+	}
+
+	return EFI_SUCCESS;
+}
+
+static void
+efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
+{
+	while(1);	/* Is there a pseudo-op to stop medusa */
+}
+
+static efi_status_t
+efi_success (void)
+{
+	return EFI_SUCCESS;
+}
+
+static efi_status_t
+efi_unimplemented (void)
+{
+	return EFI_UNSUPPORTED;
+}
+
+#ifdef CONFIG_IA64_SGI_SN2
+
+#undef cpu_physical_id
+#define cpu_physical_id(cpuid)                  ((ia64_get_lid() >> 16) & 0xffff)
+
+void
+fprom_send_cpei(void) {
+        long            *p, val;
+        long            physid;
+        long            nasid, slice;
+
+        physid = cpu_physical_id(0);
+        nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+        p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT);
+        val =   (1UL<<SH_IPI_INT_SEND_SHFT) |
+                (physid<<SH_IPI_INT_PID_SHFT) |
+                ((long)0<<SH_IPI_INT_TYPE_SHFT) |
+                ((long)0x1e<<SH_IPI_INT_IDX_SHFT) |
+                (0x000feeUL<<SH_IPI_INT_BASE_SHFT);
+        *p = val;
+
+}
+#endif
+
+
+static long
+sal_emulator (long index, unsigned long in1, unsigned long in2,
+	      unsigned long in3, unsigned long in4, unsigned long in5,
+	      unsigned long in6, unsigned long in7)
+{
+	register long r9 asm ("r9") = 0;
+	register long r10 asm ("r10") = 0;
+	register long r11 asm ("r11") = 0;
+	long status;
+
+	/*
+	 * Don't do a "switch" here since that gives us code that
+	 * isn't self-relocatable.
+	 */
+	status = 0;
+	if (index == SAL_FREQ_BASE) {
+		switch (in1) {
+		      case SAL_FREQ_BASE_PLATFORM:
+			r9 = 500000000;
+			break;
+
+		      case SAL_FREQ_BASE_INTERVAL_TIMER:
+			/*
+			 * Is this supposed to be the cr.itc frequency
+			 * or something platform specific?  The SAL
+			 * doc ain't exactly clear on this...
+			 */
+			r9 = 700000000;
+			break;
+
+		      case SAL_FREQ_BASE_REALTIME_CLOCK:
+			r9 = 50000000;
+			break;
+
+		      default:
+			status = -1;
+			break;
+		}
+	} else if (index == SAL_SET_VECTORS) {
+		if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
+			func_ptr_t	*fp;
+			fp = ADDR_OF(&ap_entry);
+			fp->pc = in2;
+			fp->gp = in3;
+		} else if (in1 == SAL_VECTOR_OS_MCA || in1 == SAL_VECTOR_OS_INIT) {
+		} else {
+			status = -1;
+		}
+		;
+	} else if (index == SAL_GET_STATE_INFO) {
+		;
+	} else if (index == SAL_GET_STATE_INFO_SIZE) {
+		;
+	} else if (index == SAL_CLEAR_STATE_INFO) {
+		;
+	} else if (index == SAL_MC_RENDEZ) {
+		;
+	} else if (index == SAL_MC_SET_PARAMS) {
+		;
+	} else if (index == SAL_CACHE_FLUSH) {
+		;
+	} else if (index == SAL_CACHE_INIT) {
+		;
+	} else if (index == SAL_UPDATE_PAL) {
+		;
+#ifdef CONFIG_IA64_SGI_SN2
+	} else if (index == SN_SAL_LOG_CE) {
+#ifdef ajmtestcpei
+		fprom_send_cpei();
+#else /* ajmtestcpei */
+		;
+#endif /* ajmtestcpei */
+#endif
+	} else if (index == SN_SAL_PROBE) {
+		r9 = 0UL;
+		if (in2 == 4) {
+			r9 = *(unsigned *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 2) {
+			r9 = *(unsigned short *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 1) {
+			r9 = *(unsigned char *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else if (in2 == 8) {
+			r9 = *(unsigned long *)in1;
+			if (r9 == -1) {
+				status = 1;
+			}
+		} else {
+			status = 2;
+		}
+	} else if (index == SN_SAL_GET_KLCONFIG_ADDR) {
+		r9 = 0x30000;
+	} else {
+		status = -1;
+	}
+
+	asm volatile ("" :: "r"(r9), "r"(r10), "r"(r11));
+	return status;
+}
+
+
+/*
+ * This is here to work around a bug in egcs-1.1.1b that causes the
+ * compiler to crash (seems like a bug in the new alias analysis code.
+ */
+void *
+id (long addr)
+{
+	return (void *) addr;
+}
+
+
+/*
+ * Fix the addresses in a function pointer by adding base node address
+ * to pc & gp.
+ */
+void
+fix_function_pointer(void *fp)
+{
+	func_ptr_t	*_fp;
+
+	_fp = fp;
+	_fp->pc = __fwtab_pa(base_nasid, _fp->pc);
+	_fp->gp = __fwtab_pa(base_nasid, _fp->gp);
+}
+
+void
+fix_virt_function_pointer(void **fptr)
+{
+        func_ptr_t      *fp;
+	long		*p;
+
+	p = (long*)fptr;
+        fp = *fptr;
+        fp->pc = fp->pc | PAGE_OFFSET;
+        fp->gp = fp->gp | PAGE_OFFSET;
+	*p |= PAGE_OFFSET;
+}
+
+
+int
+efi_set_virtual_address_map(void)
+{
+        efi_runtime_services_t            *runtime;
+
+        runtime = efi_runtime_p;
+        fix_virt_function_pointer((void**)&runtime->get_time);
+        fix_virt_function_pointer((void**)&runtime->set_time);
+        fix_virt_function_pointer((void**)&runtime->get_wakeup_time);
+        fix_virt_function_pointer((void**)&runtime->set_wakeup_time);
+        fix_virt_function_pointer((void**)&runtime->set_virtual_address_map);
+        fix_virt_function_pointer((void**)&runtime->get_variable);
+        fix_virt_function_pointer((void**)&runtime->get_next_variable);
+        fix_virt_function_pointer((void**)&runtime->set_variable);
+        fix_virt_function_pointer((void**)&runtime->get_next_high_mono_count);
+        fix_virt_function_pointer((void**)&runtime->reset_system);
+        return EFI_SUCCESS;;
+}
+
+void
+acpi_table_init(acpi_desc_table_hdr_t *p, char *sig, int siglen, int revision, int oem_revision)
+{
+	memcpy(p->signature, sig, siglen);
+	memcpy(p->oem_id, OEMID, 6);
+	memcpy(p->oem_table_id, sig, 4);
+	memcpy(p->oem_table_id+4, PRODUCT, 4);
+	p->revision = revision;
+	p->oem_revision = (revision<<16) + oem_revision;
+	p->creator_id = 1;
+	p->creator_revision = 1;
+}
+
+void
+acpi_checksum(acpi_desc_table_hdr_t *p, int length)
+{
+	u8	*cp, *cpe, checksum;
+
+	p->checksum = 0;
+	p->length = length;
+	checksum = 0;
+	for (cp=(u8*)p, cpe=cp+p->length; cp<cpe; cp++)
+		checksum += *cp;
+	p->checksum = -checksum;
+}
+
+void
+acpi_checksum_rsdp20(acpi20_rsdp_t *p, int length)
+{
+	u8	*cp, *cpe, checksum;
+
+	p->checksum = 0;
+	p->length = length;
+	checksum = 0;
+	for (cp=(u8*)p, cpe=cp+RSDP_CHECKSUM_LENGTH; cp<cpe; cp++)
+		checksum += *cp;
+	p->checksum = -checksum;
+}
+
+int
+nasid_present(int nasid)
+{
+	int	cnode;
+	for (cnode=0; cnode<num_nodes; cnode++)
+		if (GetNasid(cnode) == nasid)
+			return 1;
+	return 0;
+}
+
+void
+sys_fw_init (const char *args, int arglen, int bsp)
+{
+	/*
+	 * Use static variables to keep from overflowing the RSE stack
+	 */
+	static efi_system_table_t *efi_systab;
+	static efi_runtime_services_t *efi_runtime;
+	static efi_config_table_t *efi_tables;
+	static ia64_sal_desc_ptc_t *sal_ptc;
+	static ia64_sal_ptc_domain_info_t *sal_ptcdi;
+	static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid;
+#ifdef ACPI_1_0
+	static acpi_rsdp_t *acpi_rsdp;
+	static acpi_rsdt_t *acpi_rsdt;
+	static acpi_sapic_t *acpi_sapic;
+	static acpi_entry_lsapic_t *acpi_lsapic;
+#endif
+	static acpi20_rsdp_t *acpi20_rsdp;
+	static acpi_xsdt_t *acpi_xsdt;
+	static acpi_slit_t *acpi_slit;
+	static acpi_madt_t *acpi_madt;
+	static acpi20_entry_lsapic_t *lsapic20;
+	static struct ia64_sal_systab *sal_systab;
+	static acpi_srat_t *acpi_srat;
+	static srat_cpu_affinity_t *srat_cpu_affinity;
+	static srat_memory_affinity_t *srat_memory_affinity;
+	static efi_memory_desc_t *efi_memmap, *md;
+	static unsigned long *pal_desc, *sal_desc;
+	static struct ia64_sal_desc_entry_point *sal_ed;
+	static struct ia64_boot_param *bp;
+	static struct ia64_sal_desc_ap_wakeup *sal_apwake;
+	static unsigned char checksum;
+	static char *cp, *cmd_line, *vendor;
+	static void *ptr;
+	static int mdsize, domain, last_domain ;
+	static int i, j, cnode, max_nasid, nasid, cpu, num_memmd, cpus_found;
+
+	/*
+	 * Pass the parameter base address to the build_efi_xxx routines.
+	 */
+#if defined(CONFIG_IA64_SGI_SN1)
+	build_init(8LL*GB*base_nasid);
+#else
+	build_init(0x3000000000UL | ((long)base_nasid<<38));
+#endif
+
+	num_nodes = GetNumNodes();
+	num_cpus = GetNumCpus();
+	for (max_nasid=0, cnode=0; cnode<num_nodes; cnode++)
+		max_nasid = MAX(max_nasid, GetNasid(cnode));
+
+
+	memset(fw_mem, 0, sizeof(fw_mem));
+
+	pal_desc = (unsigned long *) &pal_emulator;
+	sal_desc = (unsigned long *) &sal_emulator;
+	fix_function_pointer(&pal_emulator);
+	fix_function_pointer(&sal_emulator);
+
+	/* Align this to 16 bytes, probably EFI does this  */
+	mdsize = (sizeof(efi_memory_desc_t) + 15) & ~15 ;
+
+	cp = fw_mem;
+	efi_systab  = (void *) cp; cp += ALIGN8(sizeof(*efi_systab));
+	efi_runtime_p = efi_runtime = (void *) cp; cp += ALIGN8(sizeof(*efi_runtime));
+	efi_tables  = (void *) cp; cp += ALIGN8(NUM_EFI_DESCS*sizeof(*efi_tables));
+	sal_systab  = (void *) cp; cp += ALIGN8(sizeof(*sal_systab));
+	sal_ed      = (void *) cp; cp += ALIGN8(sizeof(*sal_ed));
+	sal_ptc     = (void *) cp; cp += ALIGN8(sizeof(*sal_ptc));
+	sal_apwake  = (void *) cp; cp += ALIGN8(sizeof(*sal_apwake));
+	acpi20_rsdp = (void *) cp; cp += ALIGN8(sizeof(*acpi20_rsdp));
+	acpi_xsdt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_xsdt) + 64); 
+			/* save space for more OS defined table pointers. */
+
+#ifdef ACPI_1_0
+	acpi_rsdp   = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdp));
+	acpi_rsdt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_rsdt));
+	acpi_sapic  = (void *) cp; cp += sizeof(*acpi_sapic);
+	acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic);
+#endif
+	acpi_slit   = (void *) cp; cp += ALIGN8(sizeof(*acpi_slit) + 8 + (max_nasid+1)*(max_nasid+1));
+	acpi_madt   = (void *) cp; cp += ALIGN8(sizeof(*acpi_madt) + 8 * num_cpus+ 8);
+	acpi_srat   = (void *) cp; cp += ALIGN8(sizeof(acpi_srat_t));
+	cp         += sizeof(srat_cpu_affinity_t)*num_cpus + sizeof(srat_memory_affinity_t)*num_nodes;
+	vendor 	    = (char *) cp; cp += ALIGN8(40);
+	efi_memmap  = (void *) cp; cp += ALIGN8(8*32*sizeof(*efi_memmap));
+	sal_ptcdi   = (void *) cp; cp += ALIGN8(CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi));
+	sal_ptclid  = (void *) cp; cp += ALIGN8(((3+num_cpus)*sizeof(*sal_ptclid)+7)/8*8);
+	cmd_line    = (void *) cp;
+
+	if (args) {
+		if (arglen >= 1024)
+			arglen = 1023;
+		memcpy(cmd_line, args, arglen);
+	} else {
+		arglen = 0;
+	}
+	cmd_line[arglen] = '\0';
+	/* 
+	 * For now, just bring up bash.
+	 * If you want to execute all the startup scripts, delete the "init=..".
+	 * You can also edit this line to pass other arguments to the kernel.
+	 */
+	strcpy(cmd_line, "init=/bin/bash");
+
+	memset(efi_systab, 0, sizeof(efi_systab));
+	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
+	efi_systab->hdr.revision  = EFI_SYSTEM_TABLE_REVISION;
+	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
+	efi_systab->fw_vendor = __fwtab_pa(base_nasid, vendor);
+	efi_systab->fw_revision = 1;
+	efi_systab->runtime = __fwtab_pa(base_nasid, efi_runtime);
+	efi_systab->nr_tables = 2;
+	efi_systab->tables = __fwtab_pa(base_nasid, efi_tables);
+	memcpy(vendor, "S\0i\0l\0i\0c\0o\0n\0-\0G\0r\0a\0p\0h\0i\0c\0s\0\0", 40);
+
+	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
+	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
+	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
+	efi_runtime->get_time = __fwtab_pa(base_nasid, &efi_get_time);
+	efi_runtime->set_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_virtual_address_map = __fwtab_pa(base_nasid, &efi_set_virtual_address_map);
+	efi_runtime->get_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_next_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->set_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->get_next_high_mono_count = __fwtab_pa(base_nasid, &efi_unimplemented);
+	efi_runtime->reset_system = __fwtab_pa(base_nasid, &efi_reset_system);
+
+	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, sal_systab);
+	efi_tables++;
+#ifdef ACPI_1_0
+	efi_tables->guid = ACPI_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, acpi_rsdp);
+	efi_tables++;
+#endif
+	efi_tables->guid = ACPI_20_TABLE_GUID;
+	efi_tables->table = __fwtab_pa(base_nasid, acpi20_rsdp);
+	efi_tables++;
+
+	fix_function_pointer(&efi_unimplemented);
+	fix_function_pointer(&efi_get_time);
+	fix_function_pointer(&efi_success);
+	fix_function_pointer(&efi_reset_system);
+	fix_function_pointer(&efi_set_virtual_address_map);
+
+#ifdef ACPI_1_0
+	/* fill in the ACPI system table - has a pointer to the ACPI table header */
+	memcpy(acpi_rsdp->signature, "RSD PTR ", 8);
+	acpi_rsdp->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt);
+
+	acpi_table_init(&acpi_rsdt->header, ACPI_RSDT_SIG, ACPI_RSDT_SIG_LEN, 1, 1);
+	acpi_rsdt->header.length = sizeof(acpi_rsdt_t);
+	acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic);
+
+	memcpy(acpi_sapic->header.signature, "SPIC ", 4);
+	acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t);
+
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			acpi_lsapic->type = ACPI_ENTRY_LOCAL_SAPIC;
+			acpi_lsapic->length = sizeof(acpi_entry_lsapic_t);
+			acpi_lsapic->acpi_processor_id = cnode*4+cpu;
+			acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
+#if defined(CONFIG_IA64_SGI_SN1)
+			acpi_lsapic->eid = cpu;
+			acpi_lsapic->id = nasid;
+#else
+			acpi_lsapic->eid = nasid&0xffff;
+			acpi_lsapic->id = (cpu<<4) | (nasid>>16);
+#endif
+			acpi_lsapic++;
+		}
+	}
+#endif
+
+
+	/* fill in the ACPI20 system table - has a pointer to the ACPI table header */
+	memcpy(acpi20_rsdp->signature, "RSD PTR ", 8);
+	acpi20_rsdp->xsdt = (struct acpi_xsdt*)__fwtab_pa(base_nasid, acpi_xsdt);
+	acpi20_rsdp->revision = 2;
+	acpi_checksum_rsdp20(acpi20_rsdp, sizeof(acpi20_rsdp_t));
+
+	/* Set up the XSDT table  - contains pointers to the other ACPI tables */
+	acpi_table_init(&acpi_xsdt->header, ACPI_XSDT_SIG, ACPI_XSDT_SIG_LEN, 1, 1);
+	acpi_xsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_madt);
+	acpi_xsdt->entry_ptrs[1] = __fwtab_pa(base_nasid, acpi_slit);
+	acpi_xsdt->entry_ptrs[2] = __fwtab_pa(base_nasid, acpi_srat);
+	acpi_checksum(&acpi_xsdt->header, sizeof(acpi_xsdt_t) + 16);
+
+	/* Set up the MADT table */
+	acpi_table_init(&acpi_madt->header, ACPI_MADT_SIG, ACPI_MADT_SIG_LEN, 1, 1);
+	lsapic20 = (acpi20_entry_lsapic_t*) (acpi_madt + 1);
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			lsapic20->type = ACPI20_ENTRY_LOCAL_SAPIC;
+			lsapic20->length = sizeof(acpi_entry_lsapic_t);
+			lsapic20->acpi_processor_id = cnode*4+cpu;
+			lsapic20->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
+#if defined(CONFIG_IA64_SGI_SN1)
+			lsapic20->eid = cpu;
+			lsapic20->id = nasid;
+#else
+			lsapic20->eid = nasid&0xffff;
+			lsapic20->id = (cpu<<4) | (nasid>>16);
+#endif
+			lsapic20 = (acpi20_entry_lsapic_t*) ((long)lsapic20+sizeof(acpi_entry_lsapic_t));
+		}
+	}
+	acpi_checksum(&acpi_madt->header, (char*)lsapic20 - (char*)acpi_madt);
+
+	/* Set up the SRAT table */
+	acpi_table_init(&acpi_srat->header, ACPI_SRAT_SIG, ACPI_SRAT_SIG_LEN, ACPI_SRAT_REVISION, 1);
+	ptr = acpi_srat+1;
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		srat_memory_affinity = ptr;
+		ptr = srat_memory_affinity+1;
+		srat_memory_affinity->type = SRAT_MEMORY_STRUCTURE;
+		srat_memory_affinity->length = sizeof(srat_memory_affinity_t);
+		srat_memory_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid);
+		srat_memory_affinity->base_addr_lo = 0;
+		srat_memory_affinity->length_lo = 0;
+#if defined(CONFIG_IA64_SGI_SN1)
+		srat_memory_affinity->base_addr_hi = nasid<<1;
+		srat_memory_affinity->length_hi = SN1_NODE_SIZE>>32;
+#else
+		srat_memory_affinity->base_addr_hi = (nasid<<6) | (3<<4);
+		srat_memory_affinity->length_hi = SN2_NODE_SIZE>>32;
+#endif
+		srat_memory_affinity->memory_type = ACPI_ADDRESS_RANGE_MEMORY;
+		srat_memory_affinity->flags = SRAT_MEMORY_FLAGS_ENABLED;
+	}
+
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+			srat_cpu_affinity = ptr;
+			ptr = srat_cpu_affinity + 1;
+			srat_cpu_affinity->type = SRAT_CPU_STRUCTURE;
+			srat_cpu_affinity->length = sizeof(srat_cpu_affinity_t);
+			srat_cpu_affinity->proximity_domain = PROXIMITY_DOMAIN(nasid);
+			srat_cpu_affinity->flags = SRAT_CPU_FLAGS_ENABLED;
+#if defined(CONFIG_IA64_SGI_SN1)
+			srat_cpu_affinity->apic_id = nasid;
+			srat_cpu_affinity->local_sapic_eid = cpu;
+#else
+			srat_cpu_affinity->local_sapic_eid = nasid&0xffff;
+			srat_cpu_affinity->apic_id = (cpu<<4) | (nasid>>16);
+#endif
+		}
+	}
+	acpi_checksum(&acpi_srat->header, (char*)ptr - (char*)acpi_srat);
+
+
+	/* Set up the SLIT table */
+	acpi_table_init(&acpi_slit->header, ACPI_SLIT_SIG, ACPI_SLIT_SIG_LEN, ACPI_SLIT_REVISION, 1);
+	acpi_slit->localities = PROXIMITY_DOMAIN(max_nasid)+1;
+	cp=acpi_slit->entries;
+	memset(cp, 255, acpi_slit->localities*acpi_slit->localities);
+
+	for (i=0; i<=max_nasid; i++)
+		for (j=0; j<=max_nasid; j++)
+			if (nasid_present(i) && nasid_present(j))
+				*(cp+PROXIMITY_DOMAIN(i)*acpi_slit->localities+PROXIMITY_DOMAIN(j)) = 10 + MIN(254, 5*ABS(i-j));
+
+	cp = acpi_slit->entries + acpi_slit->localities*acpi_slit->localities;
+	acpi_checksum(&acpi_slit->header, cp - (char*)acpi_slit);
+
+
+	/* fill in the SAL system table: */
+	memcpy(sal_systab->signature, "SST_", 4);
+	sal_systab->size = sizeof(*sal_systab);
+	sal_systab->sal_rev_minor = 1;
+	sal_systab->sal_rev_major = 0;
+	sal_systab->entry_count = 3;
+
+	strcpy(sal_systab->oem_id, "SGI");
+	strcpy(sal_systab->product_id, "SN1");
+
+	/* fill in an entry point: */	
+	sal_ed->type = SAL_DESC_ENTRY_POINT;
+	sal_ed->pal_proc = __fwtab_pa(base_nasid, pal_desc[0]);
+	sal_ed->sal_proc = __fwtab_pa(base_nasid, sal_desc[0]);
+	sal_ed->gp = __fwtab_pa(base_nasid, sal_desc[1]);
+
+	/* kludge the PTC domain info */
+	sal_ptc->type = SAL_DESC_PTC;
+	sal_ptc->num_domains = 0;
+	sal_ptc->domain_info = __fwtab_pa(base_nasid, sal_ptcdi);
+	cpus_found = 0;
+	last_domain = -1;
+	sal_ptcdi--;
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		nasid = GetNasid(cnode);
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (IsCpuPresent(cnode, cpu)) {
+				domain = cnode*CPUS_PER_NODE + cpu/CPUS_PER_FSB;
+				if (domain != last_domain) {
+					sal_ptc->num_domains++;
+					sal_ptcdi++;
+					sal_ptcdi->proc_count = 0;
+					sal_ptcdi->proc_list = __fwtab_pa(base_nasid, sal_ptclid);
+					last_domain = domain;
+				}
+				sal_ptcdi->proc_count++;
+				sal_ptclid->id = nasid;
+				sal_ptclid->eid = cpu;
+				sal_ptclid++;
+				cpus_found++;
+			}
+		}
+	}
+
+	if (cpus_found != num_cpus)
+		FPROM_BUG();
+
+	/* Make the AP WAKEUP entry */
+	sal_apwake->type = SAL_DESC_AP_WAKEUP;
+	sal_apwake->mechanism = IA64_SAL_AP_EXTERNAL_INT;
+	sal_apwake->vector = 18;
+
+	for (checksum=0, cp=(char*)sal_systab; cp < (char *)efi_memmap; ++cp)
+		checksum += *cp;
+	sal_systab->checksum = -checksum;
+
+	/* If the checksum is correct, the kernel tries to use the
+	 * table. We dont build enough table & the kernel aborts.
+	 * Note that the PROM hasd thhhe same problem!!
+	 */
+#ifdef DOESNT_WORK
+	for (checksum=0, cp=(char*)acpi_rsdp, cpe=cp+RSDP_CHECKSUM_LENGTH; cp<cpe; ++cp)
+		checksum += *cp;
+	acpi_rsdp->checksum = -checksum;
+#endif
+
+	md = &efi_memmap[0];
+	num_memmd = build_efi_memmap((void *)md, mdsize) ;
+
+	bp = (struct ia64_boot_param*) __fwtab_pa(base_nasid, BOOT_PARAM_ADDR);
+	bp->efi_systab = __fwtab_pa(base_nasid, &fw_mem);
+	bp->efi_memmap = __fwtab_pa(base_nasid, efi_memmap);
+	bp->efi_memmap_size = num_memmd*mdsize;
+	bp->efi_memdesc_size = mdsize;
+	bp->efi_memdesc_version = 0x101;
+	bp->command_line = __fwtab_pa(base_nasid, cmd_line);
+	bp->console_info.num_cols = 80;
+	bp->console_info.num_rows = 25;
+	bp->console_info.orig_x = 0;
+	bp->console_info.orig_y = 24;
+	bp->fpswa = 0;
+
+	/*
+	 * Now pick the BSP & store it LID value in
+	 * a global variable. Note if BSP is greater than last cpu,
+	 * pick the last cpu.
+	 */
+	for (cnode=0; cnode<num_nodes; cnode++) {
+		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
+			if (!IsCpuPresent(cnode, cpu))
+				continue;
+#ifdef CONFIG_IA64_SGI_SN1
+			bsp_lid = (GetNasid(cnode)<<24) | (cpu<<16);
+#else
+			bsp_lid = (GetNasid(cnode)<<16) | (cpu<<28);
+#endif
+			if (bsp-- > 0)
+				continue;
+			return;
+		}
+	}
+}
diff -Nru a/arch/ia64/sn/fakeprom/klgraph_init.c b/arch/ia64/sn/fakeprom/klgraph_init.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/klgraph_init.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,287 @@
+/* $Id: klgraph_init.c,v 1.2 2001/12/05 16:58:41 jh Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+
+/*
+ * This is a temporary file that statically initializes the expected 
+ * initial klgraph information that is normally provided by prom.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+
+#define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
+#define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
+#define HUBREG                  ((char *)0xc0000a0001e00000)
+#define WIDGET0                 ((char *)0xc0000a0000000000)
+#define WIDGET4                 ((char *)0xc0000a0000000004)
+
+#define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
+#define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
+#define HUBREG                  ((char *)0xc0000a0001e00000)
+#define WIDGET0                 ((char *)0xc0000a0000000000)
+
+#define convert(a,b,c) temp = (u64 *)a; *temp = b; temp++; *temp = c
+void
+klgraph_init(void)
+{
+
+	u64	*temp;
+
+	/*
+	 * Initialize some hub/xbow registers that allows access to 
+	 * Xbridge etc.  These are normally done in PROM.
+	 */
+
+        /* Write IOERR clear to clear the CRAZY bit in the status */
+#ifdef CONFIG_IA64_SGI_SN1
+        *(volatile uint64_t *)0xc0000a0001c001f8 = (uint64_t)0xffffffff;
+
+        /* set widget control register...setting bedrock widget id to b */
+        *(volatile uint64_t *)0xc0000a0001c00020 = (uint64_t)0x801b;
+
+        /* set io outbound widget access...allow all */
+        *(volatile uint64_t *)0xc0000a0001c00110 = (uint64_t)0xff01;
+
+        /* set io inbound widget access...allow all */
+        *(volatile uint64_t *)0xc0000a0001c00118 = (uint64_t)0xff01;
+
+        /* set io crb timeout to max */
+        *(volatile uint64_t *)0xc0000a0001c003c0 = (uint64_t)0xffffff;
+        *(volatile uint64_t *)0xc0000a0001c003c0 = (uint64_t)0xffffff;
+
+        /* set local block io permission...allow all */
+        *(volatile uint64_t *)0xc0000a0001e04010 = (uint64_t)0xfffffffffffffff;
+
+        /* clear any errors */
+        /* clear_ii_error(); medusa should have cleared these */
+
+        /* set default read response buffers in bridge */
+        *(volatile u32 *)0xc0000a000f000280L = 0xba98;
+        *(volatile u32 *)0xc0000a000f000288L = 0xba98;
+#elif CONFIG_IA64_SGI_SN2
+        *(volatile uint64_t *)0xc000000801c001f8 = (uint64_t)0xffffffff;
+
+        /* set widget control register...setting bedrock widget id to a */
+        *(volatile uint64_t *)0xc000000801c00020 = (uint64_t)0x801a;
+
+        /* set io outbound widget access...allow all */
+        *(volatile uint64_t *)0xc000000801c00110 = (uint64_t)0xff01;
+
+        /* set io inbound widget access...allow all */
+        *(volatile uint64_t *)0xc000000801c00118 = (uint64_t)0xff01;
+
+        /* set io crb timeout to max */
+        *(volatile uint64_t *)0xc000000801c003c0 = (uint64_t)0xffffff;
+        *(volatile uint64_t *)0xc000000801c003c0 = (uint64_t)0xffffff;
+
+        /* set local block io permission...allow all */
+// [LB]        *(volatile uint64_t *)0xc000000801e04010 = (uint64_t)0xfffffffffffffff;
+
+        /* clear any errors */
+        /* clear_ii_error(); medusa should have cleared these */
+
+        /* set default read response buffers in bridge */
+// [PI]       *(volatile u32 *)0xc00000080f000280L = 0xba98;
+// [PI]       *(volatile u32 *)0xc00000080f000288L = 0xba98;
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+	/*
+	 * kldir entries initialization - mankato
+	 */
+	convert(0x8000000000002000, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002010, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002020, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002030, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002040, 0x434d5f53505f5357, 0x0000000000030000);
+	convert(0x8000000000002050, 0x0000000000000000, 0x0000000000010000);
+	convert(0x8000000000002060, 0x0000000000000001, 0x0000000000000000);
+	convert(0x8000000000002070, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002080, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002090, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020a0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020b0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x80000000000020c0, 0x434d5f53505f5357, 0x0000000000000000);
+	convert(0x80000000000020d0, 0x0000000000002400, 0x0000000000000400);
+	convert(0x80000000000020e0, 0x0000000000000001, 0x0000000000000000);
+	convert(0x80000000000020f0, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002100, 0x434d5f53505f5357, 0x0000000000040000);
+	convert(0x8000000000002110, 0x0000000000000000, 0xffffffffffffffff);
+	convert(0x8000000000002120, 0x0000000000000001, 0x0000000000000000);
+	convert(0x8000000000002130, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002140, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002150, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002160, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002170, 0x0000000000000000, 0x0000000000000000);
+	convert(0x8000000000002180, 0x434d5f53505f5357, 0x0000000000020000);
+	convert(0x8000000000002190, 0x0000000000000000, 0x0000000000010000);
+	convert(0x80000000000021a0, 0x0000000000000001, 0x0000000000000000); 
+
+	/*
+	 * klconfig entries initialization - mankato
+	 */
+	convert(0x0000000000030000, 0x00000000beedbabe, 0x0000004800000000);
+	convert(0x0000000000030010, 0x0003007000000018, 0x800002000f820178);
+	convert(0x0000000000030020, 0x80000a000f024000, 0x800002000f800000);
+	convert(0x0000000000030030, 0x0300fafa00012580, 0x00000000040f0000);
+	convert(0x0000000000030040, 0x0000000000000000, 0x0003097000030070);
+	convert(0x0000000000030050, 0x00030970000303b0, 0x0003181000033f70);
+	convert(0x0000000000030060, 0x0003d51000037570, 0x0000000000038330);
+	convert(0x0000000000030070, 0x0203110100030140, 0x0001000000000101);
+	convert(0x0000000000030080, 0x0900000000000000, 0x000000004e465e67);
+	convert(0x0000000000030090, 0x0003097000000000, 0x00030b1000030a40);
+	convert(0x00000000000300a0, 0x00030cb000030be0, 0x000315a0000314d0);
+	convert(0x00000000000300b0, 0x0003174000031670, 0x0000000000000000);
+	convert(0x0000000000030100, 0x000000000000001a, 0x3350490000000000);
+	convert(0x0000000000030110, 0x0000000000000037, 0x0000000000000000);
+	convert(0x0000000000030140, 0x0002420100030210, 0x0001000000000101);
+	convert(0x0000000000030150, 0x0100000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030160, 0x00030d8000000000, 0x0000000000030e50);
+	convert(0x00000000000301c0, 0x0000000000000000, 0x0000000000030070);
+	convert(0x00000000000301d0, 0x0000000000000025, 0x424f490000000000);
+	convert(0x00000000000301e0, 0x000000004b434952, 0x0000000000000000);
+	convert(0x0000000000030210, 0x00027101000302e0, 0x00010000000e4101);
+	convert(0x0000000000030220, 0x0200000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030230, 0x00030f2000000000, 0x0000000000030ff0);
+	convert(0x0000000000030290, 0x0000000000000000, 0x0000000000030140);
+	convert(0x00000000000302a0, 0x0000000000000026, 0x7262490000000000);
+	convert(0x00000000000302b0, 0x00000000006b6369, 0x0000000000000000);
+	convert(0x00000000000302e0, 0x0002710100000000, 0x00010000000f3101);
+	convert(0x00000000000302f0, 0x0500000000000000, 0xffffffffffffffff);
+	convert(0x0000000000030300, 0x000310c000000000, 0x0003126000031190);
+	convert(0x0000000000030310, 0x0003140000031330, 0x0000000000000000);
+	convert(0x0000000000030360, 0x0000000000000000, 0x0000000000030140);
+	convert(0x0000000000030370, 0x0000000000000029, 0x7262490000000000);
+	convert(0x0000000000030380, 0x00000000006b6369, 0x0000000000000000);
+	convert(0x0000000000030970, 0x0000000002010102, 0x0000000000000000);
+	convert(0x0000000000030980, 0x000000004e465e67, 0xffffffff00000000);
+	/* convert(0x00000000000309a0, 0x0000000000037570, 0x0000000100000000); */
+	convert(0x00000000000309a0, 0x0000000000037570, 0xffffffff00000000);
+	convert(0x00000000000309b0, 0x0000000000030070, 0x0000000000000000);
+	convert(0x00000000000309c0, 0x000000000003f420, 0x0000000000000000);
+	convert(0x0000000000030a40, 0x0000000002010125, 0x0000000000000000);
+	convert(0x0000000000030a50, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000030a70, 0x0000000000037b78, 0x0000000000000000);
+	convert(0x0000000000030b10, 0x0000000002010125, 0x0000000000000000);
+	convert(0x0000000000030b20, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000030b40, 0x0000000000037d30, 0x0000000000000001);
+	convert(0x0000000000030be0, 0x00000000ff010203, 0x0000000000000000);
+	convert(0x0000000000030bf0, 0xffffffffffffffff, 0xffffffff000000ff);
+	convert(0x0000000000030c10, 0x0000000000037ee8, 0x0100010000000200);
+	convert(0x0000000000030cb0, 0x00000000ff310111, 0x0000000000000000);
+	convert(0x0000000000030cc0, 0xffffffffffffffff, 0x0000000000000000);
+	convert(0x0000000000030d80, 0x0000000002010104, 0x0000000000000000);
+	convert(0x0000000000030d90, 0xffffffffffffffff, 0x00000000000000ff);
+	convert(0x0000000000030db0, 0x0000000000037f18, 0x0000000000000000);
+	convert(0x0000000000030dc0, 0x0000000000000000, 0x0003007000060000);
+	convert(0x0000000000030de0, 0x0000000000000000, 0x0003021000050000);
+	convert(0x0000000000030df0, 0x000302e000050000, 0x0000000000000000);
+	convert(0x0000000000030e30, 0x0000000000000000, 0x000000000000000a);
+	convert(0x0000000000030e50, 0x00000000ff00011a, 0x0000000000000000);
+	convert(0x0000000000030e60, 0xffffffffffffffff, 0x0000000000000000);
+	convert(0x0000000000030e80, 0x0000000000037fe0, 0x9e6e9e9e9e9e9e9e);
+	convert(0x0000000000030e90, 0x000000000000bc6e, 0x0000000000000000);
+	convert(0x0000000000030f20, 0x0000000002010205, 0x00000000d0020000);
+	convert(0x0000000000030f30, 0xffffffffffffffff, 0x0000000e0000000e);
+	convert(0x0000000000030f40, 0x000000000000000e, 0x0000000000000000);
+	convert(0x0000000000030f50, 0x0000000000038010, 0x00000000000007ff);
+	convert(0x0000000000030f70, 0x0000000000000000, 0x0000000022001077);
+	convert(0x0000000000030fa0, 0x0000000000000000, 0x000000000003f4a8);
+	convert(0x0000000000030ff0, 0x0000000000310120, 0x0000000000000000);
+	convert(0x0000000000031000, 0xffffffffffffffff, 0xffffffff00000002);
+	convert(0x0000000000031010, 0x000000000000000e, 0x0000000000000000);
+	convert(0x0000000000031020, 0x0000000000038088, 0x0000000000000000);
+	convert(0x00000000000310c0, 0x0000000002010205, 0x00000000d0020000);
+	convert(0x00000000000310d0, 0xffffffffffffffff, 0x0000000f0000000f);
+	convert(0x00000000000310e0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000310f0, 0x00000000000380b8, 0x00000000000007ff);
+	convert(0x0000000000031120, 0x0000000022001077, 0x00000000000310a9);
+	convert(0x0000000000031130, 0x00000000580211c1, 0x000000008009104c);
+	convert(0x0000000000031140, 0x0000000000000000, 0x000000000003f4c0);
+	convert(0x0000000000031190, 0x0000000000310120, 0x0000000000000000);
+	convert(0x00000000000311a0, 0xffffffffffffffff, 0xffffffff00000003);
+	convert(0x00000000000311b0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000311c0, 0x0000000000038130, 0x0000000000000000);
+	convert(0x0000000000031260, 0x0000000000110106, 0x0000000000000000);
+	convert(0x0000000000031270, 0xffffffffffffffff, 0xffffffff00000004);
+	convert(0x0000000000031280, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000312a0, 0x00000000ff110013, 0x0000000000000000);
+	convert(0x00000000000312b0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x00000000000312c0, 0x000000000000000f, 0x0000000000000000);
+	convert(0x00000000000312e0, 0x0000000000110012, 0x0000000000000000);
+	convert(0x00000000000312f0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000031300, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031310, 0x0000000000038160, 0x0000000000000000);
+	convert(0x0000000000031330, 0x00000000ff310122, 0x0000000000000000);
+	convert(0x0000000000031340, 0xffffffffffffffff, 0xffffffff00000005);
+	convert(0x0000000000031350, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031360, 0x0000000000038190, 0x0000000000000000);
+	convert(0x0000000000031400, 0x0000000000310121, 0x0000000000000000);
+	convert(0x0000000000031400, 0x0000000000310121, 0x0000000000000000);
+	convert(0x0000000000031410, 0xffffffffffffffff, 0xffffffff00000006);
+	convert(0x0000000000031420, 0x000000000000000f, 0x0000000000000000);
+	convert(0x0000000000031430, 0x00000000000381c0, 0x0000000000000000);
+	convert(0x00000000000314d0, 0x00000000ff010201, 0x0000000000000000);
+	convert(0x00000000000314e0, 0xffffffffffffffff, 0xffffffff00000000);
+	convert(0x0000000000031500, 0x00000000000381f0, 0x000030430000ffff);
+	convert(0x0000000000031510, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x00000000000315a0, 0x00000020ff000201, 0x0000000000000000);
+	convert(0x00000000000315b0, 0xffffffffffffffff, 0xffffffff00000001);
+	convert(0x00000000000315d0, 0x0000000000038240, 0x00003f3f0000ffff);
+	convert(0x00000000000315e0, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x0000000000031670, 0x00000000ff010201, 0x0000000000000000);
+	convert(0x0000000000031680, 0xffffffffffffffff, 0x0000000100000002);
+	convert(0x00000000000316a0, 0x0000000000038290, 0x000030430000ffff);
+	convert(0x00000000000316b0, 0x000000000000ffff, 0x0000000000000000);
+	convert(0x0000000000031740, 0x00000020ff000201, 0x0000000000000000);
+	convert(0x0000000000031750, 0xffffffffffffffff, 0x0000000500000003);
+	convert(0x0000000000031770, 0x00000000000382e0, 0x00003f3f0000ffff);
+	convert(0x0000000000031780, 0x000000000000ffff, 0x0000000000000000);
+
+	/*
+	 * GDA initialization - mankato
+	 */
+	convert(0x8000000000002400, 0x0000000258464552, 0x000000000ead0000);
+	convert(0x8000000000002480, 0xffffffff00010000, 0xffffffffffffffff);
+	convert(0x8000000000002490, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024a0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024b0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024c0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024d0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024e0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x80000000000024f0, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002500, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002510, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002520, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002530, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002540, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002550, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002560, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002570, 0xffffffffffffffff, 0xffffffffffffffff);
+	convert(0x8000000000002580, 0x000000000000ffff, 0x0000000000000000);
+	
+}
+
diff -Nru a/arch/ia64/sn/fakeprom/main.c b/arch/ia64/sn/fakeprom/main.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/main.c	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,125 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/bitops.h>
+
+extern void klgraph_init(void);
+void bedrock_init(int);
+void synergy_init(int, int);
+void sys_fw_init (const char *args, int arglen, int bsp);
+
+volatile int	bootmaster=0;		/* Used to pick bootmaster */
+volatile int	nasidmaster[128]={0};	/* Used to pick node/synergy masters */
+int		init_done=0;
+extern int	bsp_lid;
+
+#define get_bit(b,p)	(((*p)>>(b))&1)
+
+int
+fmain(int lid, int bsp) {
+	int	syn, nasid, cpu;
+
+	/*
+	 * First lets figure out who we are. This is done from the
+	 * LID passed to us.
+	 */
+
+#ifdef CONFIG_IA64_SGI_SN1
+	nasid = (lid>>24);
+	syn = (lid>>17)&1;
+	cpu = (lid>>16)&1;
+
+	/*
+	 * Now pick a synergy master to initialize synergy registers.
+	 */
+	if (test_and_set_bit(syn, &nasidmaster[nasid]) == 0) {
+		synergy_init(nasid, syn);
+		test_and_set_bit(syn+2, &nasidmaster[nasid]);
+	} else
+		while (get_bit(syn+2, &nasidmaster[nasid]) == 0);
+#else
+	nasid = (lid>>16)&0xfff;
+	cpu = (lid>>28)&3;
+	syn = 0;
+#endif
+	
+	/*
+	 * Now pick a nasid master to initialize Bedrock registers.
+	 */
+	if (test_and_set_bit(8, &nasidmaster[nasid]) == 0) {
+		bedrock_init(nasid);
+		test_and_set_bit(9, &nasidmaster[nasid]);
+	} else
+		while (get_bit(9, &nasidmaster[nasid]) == 0);
+	
+
+	/*
+	 * Now pick a BSP & finish init.
+	 */
+	if (test_and_set_bit(0, &bootmaster) == 0) {
+		sys_fw_init(0, 0, bsp);
+		test_and_set_bit(1, &bootmaster);
+	} else
+		while (get_bit(1, &bootmaster) == 0);
+
+	return (lid == bsp_lid);
+}
+
+
+void
+bedrock_init(int nasid)
+{
+	nasid = nasid;		/* to quiet gcc */
+#if 0
+	/*
+	 * Undef if you need fprom to generate a 1 node klgraph
+	 * information .. only works for 1 node for nasid 0.
+	 */
+	klgraph_init();
+#endif
+}
+
+
+void
+synergy_init(int nasid, int syn)
+{
+	long	*base;
+	long	off;
+
+	/*
+	 * Enable all FSB flashed interrupts.
+	 * ZZZ - I'd really like defines for this......
+	 */
+	base = (long*)0x80000e0000000000LL;		/* base of synergy regs */
+	for (off = 0x2a0; off < 0x2e0; off+=8)		/* offset for VEC_MASK_{0-3}_A/B */
+		*(base+off/8) = -1LL;
+
+	/*
+	 * Set the NASID in the FSB_CONFIG register.
+	 */
+	base = (long*)0x80000e0000000450LL;
+	*base = (long)((nasid<<16)|(syn<<9));
+}
+
+
+/* Why isnt there a bcopy/memcpy in lib64.a */
+
+void* 
+memcpy(void * dest, const void *src, size_t count)
+{
+	char *s, *se, *d;
+
+	for(d=dest, s=(char*)src, se=s+count; s<se; s++, d++)
+		*d = *s;
+	return dest;
+}
diff -Nru a/arch/ia64/sn/fakeprom/runsim b/arch/ia64/sn/fakeprom/runsim
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/fakeprom/runsim	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,387 @@
+#!/bin/sh
+
+# Script for running PROMs and LINUX kernwls on medusa. 
+# Type "sim -H" for instructions.
+
+MEDUSA=${MEDUSA:-/home/rickc/official_medusa/medusa}
+
+# ------------------ err -----------------------
+err() {
+	echo "ERROR - $1"
+	exit 1
+}
+
+# ----------------  help ----------------------
+help() {
+cat <<END
+Script for running a PROM or LINUX kernel under medusa.
+This script creates a control file, creates links to the appropriate
+linux/prom files, and/or calls medusa to make simulation runs.
+
+Usage:  
+   Initial setup:
+   	sim [-c <config_file>] <-p> | <-k>  [<work_dir>]
+		-p	Create PROM control file & links
+		-k	Create LINUX control file & links
+		-c<cf>	Control file name				[Default: cf]
+		<work_dir> Path to directory that contains the linux or PROM files.
+		    The directory can be any of the following:
+		       (linux simulations)
+		       		worktree
+				worktree/linux
+				any directory with vmlinux, vmlinux.sym & fprom files
+			(prom simulations)
+				worktree
+				worktree/stand/arcs/IP37prom/dev
+				any directory with fw.bin & fw.sim files
+
+    Simulations:
+	sim  [-X <n>] [-o <output>] [-M] [<config_file>]
+		-c<cf>	Control file name				[Default: cf]
+		-M	Pipe output thru fmtmedusa
+		-o	Output filename (copy of all commands/output)	[Default: simout]
+		-X	Specifies number of instructions to execute	[Default: 0]
+			(Used only in auto test mode - not described here)
+
+Examples:
+	sim -p <promtree>	# create control file (cf) & links for prom simulations
+	sim -k <linuxtree>	# create control file (cf) & links for linux simulations
+	sim -p -c cfprom	# create a prom control file (cfprom) only. No links are made.
+
+	sim			# run medusa using previously created links &
+				#   control file (cf).
+END
+exit 1
+}
+
+# ----------------------- create control file header --------------------
+create_cf_header() {
+cat <<END >>$CF
+#
+# Template for a control file for running linux kernels under medusa. 
+# You probably want to make mods here but this is a good starting point.
+#
+
+# Preferences
+setenv cpu_stepping A
+setenv exceptionPrint off
+setenv interrupt_messages off
+setenv lastPCsize 100000
+setenv low_power_mode on
+setenv partialIntelChipSet on
+setenv printIntelMessages off
+setenv prom_write_action halt
+setenv prom_write_messages on
+setenv step_quantum 100
+setenv swizzling on
+setenv tsconsole on
+setenv uart_echo on
+symbols on
+
+# IDE disk params
+setenv diskCylinders 611
+setenv bootDrive C
+setenv diskHeads 16
+setenv diskPath idedisk
+setenv diskPresent 1
+setenv diskSpt 63
+
+# Hardware config
+setenv coherency_type nasid
+setenv cpu_cache_type default
+setenv synergy_cache_type syn_cac_64m_8w
+setenv l4_uc_snoop off
+
+# Numalink config
+setenv route_enable on
+setenv network_type router		# Select [xbar|router]
+setenv network_warning 0xff
+
+END
+}
+
+
+# ------------------ create control file entries for linux simulations -------------
+create_cf_linux() {
+cat <<END >>$CF
+# Kernel specific options
+setenv calias_size 0
+setenv mca_on_memory_failure off
+setenv LOADPC 0x00100000		# FPROM load address/entry point (8 digits!)
+setenv symbol_table vmlinux.sym
+load fprom
+load vmlinux
+
+# Useful breakpoints to always have set. Add more if desired.
+break 0xe000000000505e00	all	# dispatch_to_fault_handler
+break panic			all	# stop on panic
+break die_if_kernel		all	# may as well stop
+
+END
+}
+
+# ------------------ create control file entries for prom simulations ---------------
+create_cf_prom() {
+	SYM2=""
+	ADDR="0x80000000ff800000"
+	[ "$EMBEDDED_LINUX" != "0" ] || SYM2="setenv symbol_table2 vmlinux.sym"
+	[ "$SIZE" = "8MB" ] || ADDR="0x80000000ffc00000"
+	cat <<END >>$CF
+# PROM specific options
+setenv mca_on_memory_failure on
+setenv LOADPC 0x80000000ffffffb0
+setenv promFile fw.bin
+setenv promAddr $ADDR
+setenv symbol_table fw.sym
+$SYM2
+
+# Useful breakpoints to always have set. Add more if desired.
+break ivt_gexx 		all
+break ivt_brk		all
+break PROM_Panic_Spin	all
+break PROM_Panic	all
+break PROM_C_Panic	all
+break fled_die		all
+break ResetNow		all
+break zzzbkpt		all
+
+END
+}
+
+
+# ------------------ create control file entries for memory configuration -------------
+create_cf_memory() {
+cat <<END >>$CF
+# CPU/Memory map format:
+#	setenv nodeN_memory_config 0xBSBSBSBS
+#		B=banksize (0=unused, 1=64M, 2=128M, .., 5-1G, c=8M, d=16M, e=32M)
+#		S=bank enable (0=both disable, 3=both enable, 2=bank1 enable, 1=bank0 enable)
+#		  rightmost digits are for bank 0, the lowest address.
+#	setenv nodeN_nasid <nasid>
+#		specifies the NASID for the node. This is used ONLY if booting the kernel.
+#		On PROM configurations, set to 0 - PROM will change it later.
+#	setenv nodeN_cpu_config <cpu_mask>
+#		Set bit number N to 1 to enable cpu N. Ex., a value of 5 enables cpu 0 & 2.
+#
+# Repeat the above 3 commands for each node.
+#
+# For kernel, default to 32MB. Although this is not a valid hardware configuration,
+# it runs faster on medusa. For PROM, 64MB is smallest allowed value.
+
+setenv node0_cpu_config		0x1	# Enable only cpu 0 on the node
+END
+
+if [ $LINUX -eq 1 ] ; then
+cat <<END >>$CF
+setenv node0_nasid		0	# cnode 0 has NASID 0
+setenv node0_memory_config 	0xe1	# 32MB
+END
+else
+cat <<END >>$CF
+setenv node0_memory_config 	0x31	# 256MB
+END
+fi
+}
+
+# -------------------- set links to linux files -------------------------
+set_linux_links() {
+	if [ -d $D/linux/arch ] ; then
+		D=$D/linux
+	elif [ -d $D/arch -o -e vmlinux.sym -o -e $D/vmlinux ] ; then
+		D=$D
+	else
+		err "cant determine directory for linux binaries"
+	fi
+	rm -rf vmlinux vmlinux.sym fprom
+	ln -s $D/vmlinux vmlinux
+	if [ -f $D/vmlinux.sym ] ; then
+		ln -s $D/vmlinux.sym vmlinux.sym
+	elif  [ -f $D/System.map ] ; then
+		ln -s $D/System.map vmlinux.sym
+	fi
+	if [ -d $D/arch ] ; then
+		ln -s $D/arch/ia64/sn/fprom/fprom fprom
+	else
+		ln -s $D/fprom fprom
+	fi
+	echo "  .. Created links to linux files"	
+}
+
+# -------------------- set links to prom files -------------------------
+set_prom_links() {
+	if [ -d $D/stand ] ; then
+		D=$D/stand/arcs/IP37prom/dev
+	elif [ -d $D/sal ] ; then
+		D=$D
+	else
+		err "cant determine directory for PROM binaries"
+	fi
+	SETUP="/tmp/tmp.$$"
+	rm -r -f $SETUP
+	sed 's/export/setenv/' < $D/../../../../.setup | sed 's/=/ /' >$SETUP
+	egrep -q '^ *setenv *PROMSIZE *8MB|^ *export' $SETUP
+	if [ $? -eq 0 ] ; then
+		SIZE="8MB"
+	else
+		SIZE="4MB"
+	fi
+	grep -q '^ *setenv *LAUNCH_VMLINUX' $SETUP
+	EMBEDDED_LINUX=$?
+	PRODUCT=`grep '^ *setenv *PRODUCT' $SETUP | cut -d" " -f3`
+	rm -f fw.bin fw.map fw.sym vmlinux vmlinux.sym fprom $SETUP
+	SDIR="${PRODUCT}${SIZE}.O"
+	BIN="${PRODUCT}ip37prom${SIZE}"
+	ln -s $D/$SDIR/$BIN.bin fw.bin
+	ln -s $D/$SDIR/$BIN.map fw.map
+	ln -s $D/$SDIR/$BIN.sym fw.sym
+	echo "  .. Created links to $SIZE prom files"
+	if [ $EMBEDDED_LINUX -eq 0 ] ; then
+		ln -s $D/linux/vmlinux vmlinux
+		ln -s $D/linux/vmlinux.sym vmlinux.sym
+		if [ -d linux/arch ] ; then
+			ln -s $D/linux/arch/ia64/sn/fprom/fprom fprom
+		else
+			ln -s $D/linux/fprom fprom
+		fi
+		echo "  .. Created links to embedded linux files in prom tree"
+	fi
+}
+
+# --------------- start of shell script --------------------------------
+OUT="simout"
+FMTMED=0
+STEPCNT=0
+PROM=0
+LINUX=0
+NCF="cf"
+while getopts "HMX:c:o:pk" c ; do
+        case ${c} in
+                H) help;;
+		M) FMTMED=1;;
+		X) STEPCNT=${OPTARG};;
+		c) NCF=${OPTARG};;
+		k) PROM=0;LINUX=1;;
+		p) PROM=1;LINUX=0;;
+		o) OUT=${OPTARG};;
+                \?) exit 1;;
+        esac
+done
+shift `expr ${OPTIND} - 1`
+
+# Check if command is for creating control file and/or links to images.
+if [ $PROM -eq 1 -o $LINUX -eq 1 ] ; then
+	CF=$NCF
+	[ ! -f $CF ] || err "wont overwrite an existing control file ($CF)"
+	if [ $# -gt 0 ] ; then
+		D=$1
+		[ -d $D ] || err "cannot find directory $D"
+		[ $PROM -eq 0 ]  || set_prom_links
+		[ $LINUX -eq 0 ] || set_linux_links
+	fi
+	create_cf_header
+	[ $PROM -eq 0 ]  || create_cf_prom
+	[ $LINUX -eq 0 ] || create_cf_linux
+	[ ! -f ../idedisk ] || ln -s ../idedisk .
+	create_cf_memory
+	echo "  .. Basic control file created (in $CF). You might want to edit"
+	echo "     this file (at least, look at it)."
+	exit 0
+fi
+
+# Verify that the control file exists
+CF=${1:-$NCF}
+[ -f $CF ] || err "No control file exists. For help, type: $0 -H"
+
+# Build the .cf files from the user control file. The .cf file is
+# identical except that the actual start & load addresses are inserted
+# into the file. In addition, the FPROM commands for configuring memory
+# and LIDs are generated. 
+
+rm -f .cf .cf1 .cf2
+awk '
+function strtonum(n) {
+	 if (substr(n,1,2) != "0x")
+	 	return int(n)
+	 n = substr(n,3)
+	 r=0
+	 while (length(n) > 0) {
+	 	r = r*16+(index("0123456789abcdef", substr(n,1,1))-1)
+		n = substr(n,2)
+	 }
+	 return r
+	}
+/^#/   	{next}
+/^$/	{next}
+/^setenv *LOADPC/               {loadpc = $3; next}
+/^setenv *node.._cpu_config/	{n=int(substr($2,5,2)); cpuconf[n] = strtonum($3); print; next}
+/^setenv *node.._memory_config/	{n=int(substr($2,5,2)); memconf[n] = strtonum($3); print; next}
+/^setenv *node.._nasid/		{n=int(substr($2,5,2)); nasid[n] = strtonum($3); print; next}
+/^setenv *node._cpu_config/	{n=int(substr($2,5,1)); cpuconf[n] = strtonum($3); print; next}
+/^setenv *node._memory_config/	{n=int(substr($2,5,1)); memconf[n] = strtonum($3); print; next}
+/^setenv *node._nasid/		{n=int(substr($2,5,1)); nasid[n] = strtonum($3); print; next}
+		{print}
+END	{
+	 # Generate the memmap info that starts at the beginning of
+	 # the node the kernel was loaded on.
+	 loadnasid = nasid[0]
+	 cnode = 0
+	 for (i=0; i<128; i++) {
+		if (memconf[i] != "") {
+			printf "sm 0x%x%08x 0x%x%04x%04x\n", 
+				2*loadnasid, 8*cnodes+8, memconf[i], cpuconf[i], nasid[i]
+			cnodes++
+			cpus += substr("0112122312232334", cpuconf[i]+1,1)
+		}
+	 }
+	 printf "sm 0x%x00000000 0x%x%08x\n", 2*loadnasid, cnodes, cpus
+	 printf "setenv number_of_nodes %d\n", cnodes
+
+	 # Now set the starting PC for each cpu.
+	 cnode = 0
+	 lowcpu=-1
+	 for (i=0; i<128; i++) {
+		if (memconf[i] != "") {
+			printf "setnode %d\n", cnode
+			conf = cpuconf[i]
+			for (j=0; j<4; j++) {
+				if (conf != int(conf/2)*2) {
+	 				printf "setcpu %d\n", j
+					if (length(loadpc) == 18)
+						printf "sr pc %s\n", loadpc
+					else
+						printf "sr pc 0x%x%s\n", 2*loadnasid, substr(loadpc,3)
+					if (lowcpu == -1)
+						lowcpu = j
+				}
+				conf = int(conf/2)
+			}
+			cnode++
+		}
+	 }
+	 printf "setnode 0\n"
+	 printf "setcpu %d\n", lowcpu
+	}
+' <$CF >.cf
+
+# Now build the .cf1 & .cf2 control files.
+CF2_LINES="^sm |^break |^run |^si |^quit |^symbols "
+egrep  "$CF2_LINES" .cf >.cf2
+egrep -v "$CF2_LINES" .cf >.cf1
+if [ $STEPCNT -ne 0 ] ; then
+	echo "s $STEPCNT" >>.cf2
+	echo "lastpc 1000" >>.cf2
+	echo "q" >>.cf2
+fi
+if [ -f vmlinux.sym ] ; then
+	awk '/ _start$/ {print "sr g 9 0x" $3}' < vmlinux.sym >> .cf2
+fi
+echo "script-on $OUT" >>.cf2
+
+# Now start medusa....
+if [ $FMTMED -ne 0 ] ; then
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 |  fmtmedusa
+elif [ $STEPCNT -eq 0 ] ; then
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 
+else
+	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 2>&1 
+fi
diff -Nru a/arch/ia64/sn/fprom/Makefile b/arch/ia64/sn/fprom/Makefile
--- a/arch/ia64/sn/fprom/Makefile	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,33 +0,0 @@
-#
-# This file is subject to the terms and conditions of the GNU General Public
-# License.  See the file "COPYING" in the main directory of this archive
-# for more details.
-#
-# Copyright (C) 2000 Silicon Graphics, Inc.
-# Copyright (C) Jack Steiner (steiner@sgi.com)
-#
-
-TOPDIR=../../../..
-HPATH           = $(TOPDIR)/include
-
-LIB     = ../../lib/lib.a
-
-OBJ=fpromasm.o main.o  fw-emu.o fpmem.o
-obj-y=fprom
-
-fprom: $(OBJ)
-	$(LD) -static -Tfprom.lds -o fprom $(OBJ) $(LIB)
-
-comma	:= ,
-
-.S.o:
-	$(CC)  -D__ASSEMBLY__ $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
-.c.o:
-	$(CC)  $(CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) $(CFLAGS_KERNEL) -c -o $*.o $<
-
-clean:
-	rm -f *.o fprom
-
-
-include $(TOPDIR)/Rules.make
-
diff -Nru a/arch/ia64/sn/fprom/README b/arch/ia64/sn/fprom/README
--- a/arch/ia64/sn/fprom/README	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,85 +0,0 @@
-This directory contains the files required to build
-the fake PROM image that is currently being used to
-boot IA64 kernels running under the SGI Medusa kernel.
-
-The FPROM currently provides the following functions:
-
-	- PAL emulation for all PAL calls we've made so far.
-	- SAL emulation for all SAL calls we've made so far.
-	- EFI emulation for all EFI calls we've made so far.
-	- builds the "ia64_bootparam" structure that is
-	  passed to the kernel from SAL. This structure 
-	  shows the cpu & memory configurations.
-	- supports medusa boottime options for changing
-	  the number of cpus present
-	- supports medusa boottime options for changing
-	  the memory configuration.
-
-
-
-At some point, this fake PROM will be replaced by the
-real PROM.
-
-
-
-
-To build a fake PROM, cd to this directory & type:
-
-	make
-
-This will (or should) build a fake PROM named "fprom".
-
-
-
-
-Use this fprom image when booting the Medusa simulator. The
-control file used to boot Medusa should include the 
-following lines:
-
-	load fprom
-	load vmlinux
-	sr pc 0x100000
-	sr g 9 <address of kernel _start function> #(currently 0xe000000000520000)
-
-NOTE: There is a script "runsim" in this directory that can be used to
-simplify setting up an environment for running under Medusa.
-
-
-
-
-The following parameters may be passed to the fake PROM to
-control the PAL/SAL/EFI parameters passed to the kernel:
-
-	GR[8] = # of cpus
-	GR[9] = address of primary entry point into the kernel
-	GR[20] = memory configuration for node 0
-	GR[21] = memory configuration for node 1
-	GR[22] = memory configuration for node 2
-	GR[23] = memory configuration for node 3
-
-
-Registers GR[20] - GR[23] contain information to specify the
-amount of memory present on nodes 0-3.
-
-  - if nothing is specified (all registers are 0), the configuration
-    defaults to 8 MB on node 0.
-
-  - a mem config entry for node N is passed in GR[20+N]
-
-  - a mem config entry consists of 8 hex digits. Each digit gives the
-    amount of physical memory available on the node starting at
-    1GB*<dn>, where dn is the digit number. The amount of memory
-    is 8MB*2**<d>. (If <d> = 0, the memory size is 0).
-
-    SN1 doesnt support dimms this small but small memory systems 
-    boot faster on Medusa.
-
-
-
-An example helps a lot. The following specifies that node 0 has
-physical memory 0 to 8MB and 1GB to 1GB+32MB, and that node 1 has
-64MB starting at address 0 of the node which is 8GB.
-
-      gr[20] = 0x21           # 0 to 8MB, 1GB to 1GB+32MB
-      gr[21] = 0x4            # 8GB to 8GB+64MB
-
diff -Nru a/arch/ia64/sn/fprom/fpmem.c b/arch/ia64/sn/fprom/fpmem.c
--- a/arch/ia64/sn/fprom/fpmem.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,200 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-/*
- * FPROM EFI memory descriptor build routines
- *
- * 	- Routines to build the EFI memory descriptor map
- * 	- Should also be usable by the SGI SN1 prom to convert
- * 	  klconfig to efi_memmap
- */
-
-#include <asm/efi.h>
-#include "fpmem.h"
-
-/*
- * args points to a layout in memory like this
- *
- *		32 bit		32 bit
- *
- * 		numnodes	numcpus
- *
- *		16 bit   16 bit		   32 bit
- *		nasid0	cpuconf		membankdesc0
- *		nasid1	cpuconf		membankdesc1
- *			   .
- *			   .
- *			   .
- *			   .
- *			   .
- */
-
-sn_memmap_t	*sn_memmap ;
-sn_config_t	*sn_config ;
-
-/*
- * There is a hole in the node 0 address space. Dont put it
- * in the memory map
- */
-#define NODE0_HOLE_SIZE         (20*MB)
-#define NODE0_HOLE_END          (4UL*GB)
-
-#define	MB			(1024*1024)
-#define GB			(1024*MB)
-#define KERNEL_SIZE		(4*MB)
-#define PROMRESERVED_SIZE	(1*MB)
-#define MD_BANK_SHFT 30
-
-#define TO_NODE(_n, _x)		(((long)_n<<33L) | (long)_x)
-
-/*
- * For SN, this may not take an arg and gets the numnodes from 
- * the prom variable or by traversing klcfg or promcfg
- */
-int
-GetNumNodes(void)
-{
-	return sn_config->nodes;
-}
-
-int
-GetNumCpus(void)
-{
-	return sn_config->cpus;
-}
-
-/* For SN1, get the index th nasid */
-
-int
-GetNasid(int index)
-{
-	return sn_memmap[index].nasid ;
-}
-
-node_memmap_t
-GetMemBankInfo(int index)
-{
-	return sn_memmap[index].node_memmap ;
-}
-
-int
-IsCpuPresent(int cnode, int cpu)
-{
-	return  sn_memmap[cnode].cpuconfig & (1<<cpu);
-}
-
-
-/*
- * Made this into an explicit case statement so that
- * we can assign specific properties to banks like bank0
- * actually disabled etc.
- */
-
-int
-IsBankPresent(int index, node_memmap_t nmemmap)
-{
-	switch (index) {
-		case 0:return nmemmap.b0;
-		case 1:return nmemmap.b1;
-		case 2:return nmemmap.b2;
-		case 3:return nmemmap.b3;
-		case 4:return nmemmap.b4;
-		case 5:return nmemmap.b5;
-		case 6:return nmemmap.b6;
-		case 7:return nmemmap.b7;
-		default:return -1 ;
-	}
-}
-
-int
-GetBankSize(int index, node_memmap_t nmemmap)
-{
-        switch (index) {
-                case 0:
-                case 1:return nmemmap.b01size;
-                case 2:
-                case 3:return nmemmap.b23size;
-                case 4:
-                case 5:return nmemmap.b45size;
-                case 6:
-                case 7:return nmemmap.b67size;
-                default:return -1 ;
-        }
-}
-
-void
-build_mem_desc(efi_memory_desc_t *md, int type, long paddr, long numbytes)
-{
-        md->type = type;
-        md->phys_addr = paddr;
-        md->virt_addr = 0;
-        md->num_pages = numbytes >> 12;
-        md->attribute = EFI_MEMORY_WB;
-}
-
-int
-build_efi_memmap(void *md, int mdsize)
-{
-	int		numnodes = GetNumNodes() ;
-	int		cnode,bank ;
-	int		nasid ;
-	node_memmap_t	membank_info ;
-	int		bsize;
-	int		count = 0 ;
-	long		paddr, hole, numbytes;
-
-
-	for (cnode=0;cnode<numnodes;cnode++) {
-		nasid = GetNasid(cnode) ;
-		membank_info = GetMemBankInfo(cnode) ;
-		for (bank=0;bank<SN1_MAX_BANK_PER_NODE;bank++) {
-			if (IsBankPresent(bank, membank_info)) {
-				bsize = GetBankSize(bank, membank_info) ;
-                                paddr = TO_NODE(nasid, (long)bank<<MD_BANK_SHFT);
-                                numbytes = BankSizeBytes(bsize);
-
-                                /*
-                                 * Check for the node 0 hole. Since banks cant
-                                 * span the hole, we only need to check if the end of
-                                 * the range is the end of the hole.
-                                 */
-                                if (paddr+numbytes == NODE0_HOLE_END)
-                                        numbytes -= NODE0_HOLE_SIZE;
-                                /*
-                                 * UGLY hack - we must skip overr the kernel and
-                                 * PROM runtime services but we dont exactly where it is.
-                                 * So lets just reserve 0-12MB.
-                                 */
-                                if (bank == 0) {
-					hole = (cnode == 0) ? KERNEL_SIZE : PROMRESERVED_SIZE;
-					numbytes -= hole;
-                                        build_mem_desc(md, EFI_RUNTIME_SERVICES_DATA, paddr, hole);
-                                        paddr += hole;
-			        	count++ ;
-                                        md += mdsize;
-                                }
-                                build_mem_desc(md, EFI_CONVENTIONAL_MEMORY, paddr, numbytes);
-
-			        md += mdsize ;
-			        count++ ;
-			}
-		}
-	}
-	return count ;
-}
-
-void
-build_init(unsigned long args)
-{
-	sn_config = (sn_config_t *) (args);	
-	sn_memmap = (sn_memmap_t *)(args + 8) ; /* SN equiv for this is */
-						/* init to klconfig start */
-}
diff -Nru a/arch/ia64/sn/fprom/fpmem.h b/arch/ia64/sn/fprom/fpmem.h
--- a/arch/ia64/sn/fprom/fpmem.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,35 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#include <asm/sn/mmzone_sn1.h>
-
-typedef struct sn_memmap_s
-{
-	short		nasid ;
-	short		cpuconfig;
-	node_memmap_t 	node_memmap ;
-} sn_memmap_t ;
-
-typedef struct sn_config_s
-{
-	int		cpus;
-	int		nodes;
-	sn_memmap_t	memmap[1];		/* start of array */
-} sn_config_t;
-
-
-extern void build_init(unsigned long);
-extern int build_efi_memmap(void *, int);
-extern int GetNumNodes(void);
-extern int GetNumCpus(void);
-extern int IsCpuPresent(int, int);
-extern int GetNasid(int);
diff -Nru a/arch/ia64/sn/fprom/fprom.lds b/arch/ia64/sn/fprom/fprom.lds
--- a/arch/ia64/sn/fprom/fprom.lds	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,96 +0,0 @@
-
-OUTPUT_FORMAT("elf64-ia64-little")
-OUTPUT_ARCH(ia64)
-ENTRY(_start)
-SECTIONS
-{
-  v = 0x0000000000000000 ;	/* this symbol is here to make debugging with kdb easier... */
-
-  . = (0x000000000000000  + 0x100000) ;
-
-  _text = .;
-  .text : AT(ADDR(.text) - 0x0000000000000000 )
-    {
-	*(__ivt_section)
-	/* these are not really text pages, but the zero page needs to be in a fixed location: */
-	*(__special_page_section)
-	__start_gate_section = .;
-	*(__gate_section)
-	__stop_gate_section = .;
-	*(.text)
-    }
-
-  /* Global data */
-  _data = .;
-
-  .rodata : AT(ADDR(.rodata) - 0x0000000000000000 )
-	{ *(.rodata) *(.rodata.*) }
-  .opd : AT(ADDR(.opd) - 0x0000000000000000 )
-	{ *(.opd) }
-  .data : AT(ADDR(.data) - 0x0000000000000000 )
-	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
-
-  __gp = ALIGN (8) + 0x200000;
-
-  .got : AT(ADDR(.got) - 0x0000000000000000 )
-	{ *(.got.plt) *(.got) }
-  /* We want the small data sections together, so single-instruction offsets
-     can access them all, and initialized data all before uninitialized, so
-     we can shorten the on-disk segment size.  */
-  .sdata : AT(ADDR(.sdata) - 0x0000000000000000 )
-	{ *(.sdata) }
-  _edata  =  .;
-  _bss = .;
-  .sbss : AT(ADDR(.sbss) - 0x0000000000000000 )
-	{ *(.sbss) *(.scommon) }
-  .bss : AT(ADDR(.bss) - 0x0000000000000000 )
-	{ *(.bss) *(COMMON) }
-  . = ALIGN(64 / 8);
-  _end = .;
-
-  /* Sections to be discarded */
-  /DISCARD/ : {
-	*(.text.exit)
-	*(.data.exit)
-	}
-
-  /* Stabs debugging sections.  */
-  .stab 0 : { *(.stab) }
-  .stabstr 0 : { *(.stabstr) }
-  .stab.excl 0 : { *(.stab.excl) }
-  .stab.exclstr 0 : { *(.stab.exclstr) }
-  .stab.index 0 : { *(.stab.index) }
-  .stab.indexstr 0 : { *(.stab.indexstr) }
-  /* DWARF debug sections.
-     Symbols in the DWARF debugging sections are relative to the beginning
-     of the section so we begin them at 0.  */
-  /* DWARF 1 */
-  .debug          0 : { *(.debug) }
-  .line           0 : { *(.line) }
-  /* GNU DWARF 1 extensions */
-  .debug_srcinfo  0 : { *(.debug_srcinfo) }
-  .debug_sfnames  0 : { *(.debug_sfnames) }
-  /* DWARF 1.1 and DWARF 2 */
-  .debug_aranges  0 : { *(.debug_aranges) }
-  .debug_pubnames 0 : { *(.debug_pubnames) }
-  /* DWARF 2 */
-  .debug_info     0 : { *(.debug_info) }
-  .debug_abbrev   0 : { *(.debug_abbrev) }
-  .debug_line     0 : { *(.debug_line) }
-  .debug_frame    0 : { *(.debug_frame) }
-  .debug_str      0 : { *(.debug_str) }
-  .debug_loc      0 : { *(.debug_loc) }
-  .debug_macinfo  0 : { *(.debug_macinfo) }
-  /* SGI/MIPS DWARF 2 extensions */
-  .debug_weaknames 0 : { *(.debug_weaknames) }
-  .debug_funcnames 0 : { *(.debug_funcnames) }
-  .debug_typenames 0 : { *(.debug_typenames) }
-  .debug_varnames  0 : { *(.debug_varnames) }
-  /* These must appear regardless of  .  */
-  /* Discard them for now since Intel SoftSDV cannot handle them.
-  .comment 0 : { *(.comment) }
-  .note 0 : { *(.note) }
-  */
-  /DISCARD/ : { *(.comment) }
-  /DISCARD/ : { *(.note) }
-}
diff -Nru a/arch/ia64/sn/fprom/fpromasm.S b/arch/ia64/sn/fprom/fpromasm.S
--- a/arch/ia64/sn/fprom/fpromasm.S	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,314 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- *   (Code copied from or=ther files)
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#define __ASSEMBLY__ 1
-#include "asm/processor.h"
-
-/*
- * This file contains additional set up code that is needed to get going on
- * Medusa.  This code should disappear once real hw is available.
- *
- * On entry to this routine, the following register values are assumed:
- *
- *	gr[8]	- BSP cpu
- *	pr[9]	- kernel entry address
- *
- * NOTE:
- *   This FPROM may be loaded/executed at an address different from the
- *   address that it was linked at. The FPROM is linked to run on node 0
- *   at address 0x100000. If the code in loaded into another node, it
- *   must be loaded at offset 0x100000 of the node. In addition, the
- *   FPROM does the following things:
- *		- determine the base address of the node it is loaded on
- *		- add the node base to _gp.
- *		- add the node base to all addresses derived from "movl" 
- *		  instructions. (I couldnt get GPREL addressing to work)
- *		  (maybe newer versions of the tools will support this)
- *		- scan the .got section and add the node base to all
- *		  pointers in this section.
- *		- add the node base to all physical addresses in the
- *		  SAL/PAL/EFI table built by the C code. (This is done
- *		  in the C code - not here)
- *		- add the node base to the TLB entries for vmlinux
- */
-
-#define KERNEL_BASE	0xe000000000000000
-#define PAGESIZE_256M	28
-
-/* 
- * ar.k0 gets set to IOPB_PA value, on 460gx chipset it should 
- * be 0x00000ffffc000000, but on snia we use the (inverse swizzled)
- * IOSPEC_BASE value
- */
-#define IOPB_PA		0x00000a0000000000 /* inv swizzle IOSPEC_BASE */
-
-#define RR_RID		8
-
-
-
-// ====================================================================================	
-        .text
-        .align 16
-	.global _start
-	.proc _start
-_start:
-
-// Setup psr and rse for system init
-	mov		psr.l = r0;;
-	srlz.d;;
-	invala
-	mov		ar.rsc = r0;;
-	loadrs
-	;;
-
-// Set CALIAS size to zero. We dont use it.
-	movl		r24=0x80000a0001000028;;	// BR_PI_CALIAS_SIZE
-	st8 		[r24]=r0
-
-// Isolate node number we are running on.
-	mov		r6 = ip;;
-	shr		r5 = r6,33;;			// r5 = node number
-	shl		r6 = r5,33			// r6 = base memory address of node
-
-// Set & relocate gp.
-	movl		r1= __gp;;			// Add base memory address
-	add 		r1 = r1,r6			// Relocate to boot node
-
-// Lets figure out who we are & put it in the LID register.
-// The BR_PI_SELF_CPU_NUM register gives us a value of 0-3.
-// This identifies the cpu on the node. 
-// Merge the cpu number with the NASID to generate the LID.
-	movl		r24=0x80000a0001000020;;	// BR_PI_SELF_CPU_NUM
-	ld8 		r25=[r24]			// Fetch PI_SELF
-	movl		r27=0x80000a0001600000;;	// Fetch REVID to get local NASID
-	ld8 		r27=[r27];;
-	extr.u		r27=r27,32,8
-	shl 		r26=r25,16;;			// Align local cpu# to lid.eid
-	shl 		r27=r27,24;;			// Align NASID to lid.id
-	or  		r26=r26,r27;;			// build the LID
-	mov 		cr.lid=r26			// Now put in in the LID register
-	
-	movl		r2=FPSR_DEFAULT;;
-	mov 		ar.fpsr=r2
-	movl		sp = bootstacke-16;;
-	add 		sp = sp,r6			// Relocate to boot node			
-
-// Save the NASID that we are loaded on.
-	movl		r2=base_nasid;;			// Save base_nasid for C code
-	add 		r2 = r2,r6;;			// Relocate to boot node
-  	st8 		[r2]=r5				// Uncond st8 - same on all cpus
-
-// Save the kernel entry address. It is passed in r9 on one of
-// the cpus.
-	movl		r2=bsp_entry_pc
-	cmp.ne		p6,p0=r9,r0;;
-	add 		r2 = r2,r6;;			// Relocate to boot node
-(p6)  	st8 		[r2]=r9				// Uncond st8 - same on all cpus
-
-
-// The following can ONLY be done by 1 cpu. Lets set a lock - the
-// cpu that gets it does the initilization. The rest just spin waiting
-// til initilization is complete.
-	movl		r22 = initlock;;
-	add		r22 = r22,r6			// Relocate to boot node
-	mov		r23 = 1;;
-	xchg8		r23 = [r22],r23;;
-	cmp.eq 		p6,p0 = 0,r23
-(p6)	br.cond.spnt.few init
-1:	ld4		r23 = [r22];;
-	cmp.eq		p6,p0 = 1,r23
-(p6)	br.cond.sptk	1b
-	br		initx
-
-// Add base address of node memory to each pointer in the .got section.
-init:	movl		r16 = _GLOBAL_OFFSET_TABLE_;;
-	add		r16 = r16,r6;;			// Relocate to boot node
-1: 	ld8		r17 = [r16];;
-	cmp.eq		p6,p7=0,r17
-(p6)	br.cond.sptk.few.clr 2f;;
-	add		r17 = r17,r6;;			// Relocate to boot node
-	st8		[r16] = r17,8
-	br		1b
-2:
-	mov		r23 = 2;;			// All done, release the spinning cpus
-	st4		[r22] = r23
-initx:
-
-//
-//	I/O-port space base address:
-//
-	movl		r2 = IOPB_PA;;
-	mov		ar.k0 = r2
-
-
-// Now call main & pass it the current LID value.
-	alloc 		r0=ar.pfs,0,0,2,0
-	mov    		r32=r26
-	mov   		r33=r8;;
-	br.call.sptk.few rp=fmain
-	
-// Initialize Region Registers
-//
-	mov		r10 = r0
-	mov		r2 = (13<<2) 
-	mov		r3 = r0;;
-1:	cmp4.gtu	p6,p7 = 7, r3
-	dep		r10 = r3, r10, 61, 3
-	dep		r2 = r3, r2, RR_RID, 4;;
-(p7)	dep		r2 = 0, r2, 0, 1;;
-(p6)	dep		r2 = -1, r2, 0, 1;;
-	mov		rr[r10] = r2
-	add		r3 = 1, r3;;
-	srlz.d;;
-	cmp4.gtu	p6,p0 = 8, r3
-(p6)	br.cond.sptk.few.clr 1b
-
-//
-// Return value indicates if we are the BSP or AP.
-// 	   1 = BSP, 0 = AP
-	mov             cr.tpr=r0;;
-	cmp.eq		p6,p0=r8,r0
-(p6)	br.cond.spnt	slave
-
-//
-// Initialize the protection key registers with only pkr[0] = valid.
-//
-// Should be initialized in accordance with the OS.
-//
-	mov		r2 = 1
-	mov		r3 = r0;;
-	mov		pkr[r3] = r2;;
-	srlz.d;;
-	mov		r2 = r0
-
-1:	add		r3 = r3, r0, 1;;		// increment PKR
-	cmp.gtu		p6, p0 = 16, r3;;
-(p6)	mov		pkr[r3] = r2
-(p6)	br.cond.sptk.few.clr 1b
-
-	mov		ar.rnat = r0			// clear RNAT register
-
-//
-// Setup system address translation for kernel
-//
-// Note: The setup of Kernel Virtual address space can be done by the
-// C code of the boot loader.
-//
-//
-
-#define LINUX_PAGE_OFFSET       0xe000000000000000
-#define ITIR(key, ps)           ((key<<8) | (ps<<2))
-#define ITRGR(ed,ar,ma)         ((ed<<52) | (ar<<9) | (ma<<2) | 0x61)
-
-#define AR_RX                   1                       // RX permission
-#define AR_RW                   4                       // RW permission
-#define MA_WB                   0                       // WRITEBACK memory attribute
-
-#define TLB_PAGESIZE		28			// Use 256MB pages for now.
-	mov		r16=r5
-
-//
-//     text section
-//
-        movl            r2 = LINUX_PAGE_OFFSET;;        // Set up IFA with VPN of linux
-        mov             cr.ifa = r2
-        movl            r3 = ITIR(0,TLB_PAGESIZE);;     // Set ITIR to default pagesize
-        mov             cr.itir = r3
-
-        shl             r4 = r16,33;;                   // physical addr of start of node
-        movl            r5 = ITRGR(1,AR_RX,MA_WB);;     // TLB attributes
-        or              r10=r4,r5;;
-
-        itr.i           itr[r0] = r10;;                   // Dropin ITR entry
-	srlz.i;;
-
-//
-//     data section
-//
-        movl            r2 = LINUX_PAGE_OFFSET;;        // Set up IFA with VPN of linux
-        mov             cr.ifa = r2
-        movl            r3 = ITIR(0,TLB_PAGESIZE);;     // Set ITIR to default pagesize
-        mov             cr.itir = r3
-
-        shl             r4 = r16,33;;                   // physical addr of start of node
-        movl            r5 = ITRGR(1,AR_RW,MA_WB);;     // TLB attributes
-        or              r10=r4,r5;;
-
-        itr.d           dtr[r0] = r10;;                 // Dropin DTR entry
-	srlz.d;;
-
-
-
-
-//
-// Turn on address translation, interrupt collection, psr.ed, protection key.
-// Interrupts (PSR.i) are still off here.
-//
-
-	movl		r3 = (	IA64_PSR_BN | \
-				IA64_PSR_AC | \
-				IA64_PSR_IT | \
-				IA64_PSR_DB | \
-				IA64_PSR_DA | \
-				IA64_PSR_RT | \
-				IA64_PSR_DT | \
-				IA64_PSR_IC   \
-			     )
-	;;
-	mov		cr.ipsr = r3
-
-//
-// Go to kernel C startup routines
-//	Need to do a "rfi" in order set "it" and "ed" bits in the PSR.
-//	This is the only way to set them.
-
-	movl		r2=bsp_entry_pc;;
-	add 		r2 = r2,r6;;			// Relocate to boot node
-	ld8		r2=[r2];;
-	mov		cr.iip = r2
-	srlz.d;;
-	rfi;;
-	.endp		_start
-
-// Slave processors come here to spin til they get an interrupt. Then they launch themselves to
-// the place ap_entry points. No initialization is necessary - the kernel makes no
-// assumptions about state on this entry.
-//	Note: should verify that the interrupt we got was really the ap_wakeup
-//	      interrupt but this should not be an issue on medusa
-slave:
-	nop.i		0x8beef				// Medusa - put cpu to sleep til interrupt occurs
-	mov		r8=cr.irr0;;			// Check for interrupt pending.
-	cmp.eq		p6,p0=r8,r0
-(p6)	br.cond.sptk	slave;;
-
-	mov		r8=cr.ivr;;			// Got one. Must read ivr to accept it
-	srlz.d;;
-	mov		cr.eoi=r0;;			// must write eoi to clear
-	movl		r8=ap_entry;;			// now jump to kernel entry
-	add 		r8 = r8,r6;;			// Relocate to boot node
-	ld8		r9=[r8],8;;
-	ld8		r1=[r8]
-	mov		b0=r9;;
-	br		b0
-
-// Here is the kernel stack used for the fake PROM
-	.bss
-	.align		16384
-bootstack:
-	.skip		16384
-bootstacke:
-initlock:
-	data4
diff -Nru a/arch/ia64/sn/fprom/fw-emu.c b/arch/ia64/sn/fprom/fw-emu.c
--- a/arch/ia64/sn/fprom/fw-emu.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,524 +0,0 @@
-/*
- * PAL & SAL emulation.
- *
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- *
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-#include <asm/efi.h>
-#include <asm/pal.h>
-#include <asm/sal.h>
-#include <asm/processor.h>
-#include <asm/acpi-ext.h>
-#include "fpmem.h"
-
-#define MB	(1024*1024UL)
-#define GB	(MB*1024UL)
-
-#define FPROM_BUG()		do {while (1);} while (0)
-#define MAX_NODES		128
-#define MAX_LSAPICS		512
-#define MAX_CPUS		512
-#define MAX_CPUS_NODE		4
-#define CPUS_PER_NODE		4
-#define CPUS_PER_FSB		2
-#define CPUS_PER_FSB_MASK	(CPUS_PER_FSB-1)
-
-#define NUM_EFI_DESCS		2
-
-typedef union ia64_nasid_va {
-        struct {
-                unsigned long off   : 33;       /* intra-region offset */
-		unsigned long nasid :  7;	/* NASID */
-		unsigned long off2  : 21;	/* fill */
-                unsigned long reg   :  3;       /* region number */
-        } f;
-        unsigned long l;
-        void *p;
-} ia64_nasid_va;
-
-typedef struct {
-	unsigned long	pc;
-	unsigned long	gp;
-} func_ptr_t;
- 
-#define IS_VIRTUAL_MODE() 	 ({struct ia64_psr psr; asm("mov %0=psr" : "=r"(psr)); psr.dt;})
-#define ADDR_OF(p)		(IS_VIRTUAL_MODE() ? ((void*)((long)(p)+PAGE_OFFSET)) : ((void*) (p)))
-#define __fwtab_pa(n,x)		({ia64_nasid_va _v; _v.l = (long) (x); _v.f.nasid = (x) ? (n) : 0; _v.f.reg = 0; _v.l;})
-
-/*
- * The following variables are passed thru registersfrom the configuration file and
- * are set via the _start function.
- */
-long		base_nasid;
-long		num_cpus;
-long		bsp_entry_pc=0;
-long		num_nodes;
-long		app_entry_pc;
-int		bsp_lid;
-func_ptr_t	ap_entry;
-
-
-static efi_runtime_services_t    *efi_runtime_p;
-static char fw_mem[(  sizeof(efi_system_table_t)
-		    + sizeof(efi_runtime_services_t)
-		    + NUM_EFI_DESCS*sizeof(efi_config_table_t)
-		    + sizeof(struct ia64_sal_systab)
-		    + sizeof(struct ia64_sal_desc_entry_point)
-		    + sizeof(struct ia64_sal_desc_ap_wakeup)
-		    + sizeof(acpi_rsdp_t)
-		    + sizeof(acpi_rsdt_t)
-		    + sizeof(acpi_sapic_t)
-		    + MAX_LSAPICS*(sizeof(acpi_entry_lsapic_t))
-		    + (1+8*MAX_NODES)*(sizeof(efi_memory_desc_t))
-		    + sizeof(ia64_sal_desc_ptc_t) +
-		    + MAX_NODES*sizeof(ia64_sal_ptc_domain_info_t) +
-		    + MAX_CPUS*sizeof(ia64_sal_ptc_domain_proc_entry_t) +
-		    + 1024)] __attribute__ ((aligned (8)));
-
-/*
- * Very ugly, but we need this in the simulator only.  Once we run on
- * real hw, this can all go away.
- */
-extern void pal_emulator_static (void);
-
-asm ("
-	.text
-	.proc pal_emulator_static
-pal_emulator_static:
-	mov r8=-1;;
-	cmp.eq p6,p7=6,r28;;		/* PAL_PTCE_INFO */
-(p7)	br.cond.sptk.few 1f
-	;;
-	mov r8=0			/* status = 0 */
-	movl r9=0x500000000		/* tc.base */
-	movl r10=0x0000000200000003	/* count[0], count[1] */
-	movl r11=0x1000000000002000	/* stride[0], stride[1] */
-	br.cond.sptk.few rp
-
-1:	cmp.eq p6,p7=14,r28;;		/* PAL_FREQ_RATIOS */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0			/* status = 0 */
-	movl r9 =0x100000064		/* proc_ratio (1/100) */
-	movl r10=0x100000100		/* bus_ratio<<32 (1/256) */
-	movl r11=0x10000000a		/* itc_ratio<<32 (1/100) */
-
-1:	cmp.eq p6,p7=22,r28;;		/* PAL_MC_DRAIN */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0
-	br.cond.sptk.few rp
-
-1:	cmp.eq p6,p7=23,r28;;		/* PAL_MC_EXPECTED */
-(p7)	br.cond.sptk.few 1f;;
-	mov r8=0
-	br.cond.sptk.few rp
-
-1:	br.cond.sptk.few rp
-	.endp pal_emulator_static\n");
-
-
-static efi_status_t
-efi_get_time (efi_time_t *tm, efi_time_cap_t *tc)
-{
-	if (tm) {
-		memset(tm, 0, sizeof(*tm));
-		tm->year = 2000;
-		tm->month = 2;
-		tm->day = 13;
-		tm->hour = 10;
-		tm->minute = 11;
-		tm->second = 12;
-	}
-
-	if (tc) {
-		tc->resolution = 10;
-		tc->accuracy = 12;
-		tc->sets_to_zero = 1;
-	}
-
-	return EFI_SUCCESS;
-}
-
-static void
-efi_reset_system (int reset_type, efi_status_t status, unsigned long data_size, efi_char16_t *data)
-{
-	while(1);	/* Is there a pseudo-op to stop medusa */
-}
-
-static efi_status_t
-efi_success (void)
-{
-	return EFI_SUCCESS;
-}
-
-static efi_status_t
-efi_unimplemented (void)
-{
-	return EFI_UNSUPPORTED;
-}
-
-static long
-sal_emulator (long index, unsigned long in1, unsigned long in2,
-	      unsigned long in3, unsigned long in4, unsigned long in5,
-	      unsigned long in6, unsigned long in7)
-{
-	register long r9 asm ("r9") = 0;
-	register long r10 asm ("r10") = 0;
-	register long r11 asm ("r11") = 0;
-	long status;
-
-	/*
-	 * Don't do a "switch" here since that gives us code that
-	 * isn't self-relocatable.
-	 */
-	status = 0;
-	if (index == SAL_FREQ_BASE) {
-		switch (in1) {
-		      case SAL_FREQ_BASE_PLATFORM:
-			r9 = 500000000;
-			break;
-
-		      case SAL_FREQ_BASE_INTERVAL_TIMER:
-			/*
-			 * Is this supposed to be the cr.itc frequency
-			 * or something platform specific?  The SAL
-			 * doc ain't exactly clear on this...
-			 */
-			r9 = 700000000;
-			break;
-
-		      case SAL_FREQ_BASE_REALTIME_CLOCK:
-			r9 = 1;
-			break;
-
-		      default:
-			status = -1;
-			break;
-		}
-	} else if (index == SAL_SET_VECTORS) {
-		if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
-			func_ptr_t	*fp;
-			fp = ADDR_OF(&ap_entry);
-			fp->pc = in2;
-			fp->gp = in3;
-		} else {
-			status = -1;
-		}
-		;
-	} else if (index == SAL_GET_STATE_INFO) {
-		;
-	} else if (index == SAL_GET_STATE_INFO_SIZE) {
-		;
-	} else if (index == SAL_CLEAR_STATE_INFO) {
-		;
-	} else if (index == SAL_MC_RENDEZ) {
-		;
-	} else if (index == SAL_MC_SET_PARAMS) {
-		;
-	} else if (index == SAL_CACHE_FLUSH) {
-		;
-	} else if (index == SAL_CACHE_INIT) {
-		;
-	} else if (index == SAL_UPDATE_PAL) {
-		;
-	} else {
-		status = -1;
-	}
-	asm volatile ("" :: "r"(r9), "r"(r10), "r"(r11));
-	return status;
-}
-
-
-/*
- * This is here to work around a bug in egcs-1.1.1b that causes the
- * compiler to crash (seems like a bug in the new alias analysis code.
- */
-void *
-id (long addr)
-{
-	return (void *) addr;
-}
-
-
-/*
- * Fix the addresses in a function pointer by adding base node address
- * to pc & gp.
- */
-void
-fix_function_pointer(void *fp)
-{
-	func_ptr_t	*_fp;
-
-	_fp = fp;
-	_fp->pc = __fwtab_pa(base_nasid, _fp->pc);
-	_fp->gp = __fwtab_pa(base_nasid, _fp->gp);
-}
-
-void
-fix_virt_function_pointer(void *fptr)
-{
-        func_ptr_t      *fp;
-
-        fp = fptr;
-        fp->pc = fp->pc | PAGE_OFFSET;
-        fp->gp = fp->gp | PAGE_OFFSET;
-}
-
-
-int
-efi_set_virtual_address_map(void)
-{
-        efi_runtime_services_t            *runtime;
-
-        runtime = efi_runtime_p;
-        fix_virt_function_pointer((void*)runtime->get_time);
-        fix_virt_function_pointer((void*)runtime->set_time);
-        fix_virt_function_pointer((void*)runtime->get_wakeup_time);
-        fix_virt_function_pointer((void*)runtime->set_wakeup_time);
-        fix_virt_function_pointer((void*)runtime->set_virtual_address_map);
-        fix_virt_function_pointer((void*)runtime->get_variable);
-        fix_virt_function_pointer((void*)runtime->get_next_variable);
-        fix_virt_function_pointer((void*)runtime->set_variable);
-        fix_virt_function_pointer((void*)runtime->get_next_high_mono_count);
-        fix_virt_function_pointer((void*)runtime->reset_system);
-        return EFI_SUCCESS;;
-}
-
-
-void
-sys_fw_init (const char *args, int arglen, int bsp)
-{
-	/*
-	 * Use static variables to keep from overflowing the RSE stack
-	 */
-	static efi_system_table_t *efi_systab;
-	static efi_runtime_services_t *efi_runtime;
-	static efi_config_table_t *efi_tables;
-	static ia64_sal_desc_ptc_t *sal_ptc;
-	static ia64_sal_ptc_domain_info_t *sal_ptcdi;
-	static ia64_sal_ptc_domain_proc_entry_t *sal_ptclid;
-	static acpi_rsdp_t *acpi_systab;
-	static acpi_rsdt_t *acpi_rsdt;
-	static acpi_sapic_t *acpi_sapic;
-	static acpi_entry_lsapic_t *acpi_lsapic;
-	static struct ia64_sal_systab *sal_systab;
-	static efi_memory_desc_t *efi_memmap, *md;
-	static unsigned long *pal_desc, *sal_desc;
-	static struct ia64_sal_desc_entry_point *sal_ed;
-	static struct ia64_boot_param *bp;
-	static struct ia64_sal_desc_ap_wakeup *sal_apwake;
-	static unsigned char checksum = 0;
-	static char *cp, *cmd_line, *vendor;
-	static int mdsize, domain, last_domain ;
-	static int cnode, nasid, cpu, num_memmd, cpus_found;
-
-	/*
-	 * Pass the parameter base address to the build_efi_xxx routines.
-	 */
-	build_init(8LL*GB*base_nasid);
-
-	num_nodes = GetNumNodes();
-	num_cpus = GetNumCpus();
-
-
-	memset(fw_mem, 0, sizeof(fw_mem));
-
-	pal_desc = (unsigned long *) &pal_emulator_static;
-	sal_desc = (unsigned long *) &sal_emulator;
-	fix_function_pointer(&pal_emulator_static);
-	fix_function_pointer(&sal_emulator);
-
-	/* Align this to 16 bytes, probably EFI does this  */
-	mdsize = (sizeof(efi_memory_desc_t) + 15) & ~15 ;
-
-	cp = fw_mem;
-	efi_systab  = (void *) cp; cp += sizeof(*efi_systab);
-	efi_runtime_p = efi_runtime = (void *) cp; cp += sizeof(*efi_runtime);
-	efi_tables  = (void *) cp; cp += NUM_EFI_DESCS*sizeof(*efi_tables);
-	sal_systab  = (void *) cp; cp += sizeof(*sal_systab);
-	sal_ed      = (void *) cp; cp += sizeof(*sal_ed);
-	sal_ptc     = (void *) cp; cp += sizeof(*sal_ptc);
-	sal_apwake  = (void *) cp; cp += sizeof(*sal_apwake);
-	acpi_systab = (void *) cp; cp += sizeof(*acpi_systab);
-	acpi_rsdt   = (void *) cp; cp += sizeof(*acpi_rsdt);
-	acpi_sapic  = (void *) cp; cp += sizeof(*acpi_sapic);
-	acpi_lsapic = (void *) cp; cp += num_cpus*sizeof(*acpi_lsapic);
-	vendor 	    = (char *) cp; cp += 32;
-	efi_memmap  = (void *) cp; cp += 8*32*sizeof(*efi_memmap);
-	sal_ptcdi   = (void *) cp; cp += CPUS_PER_FSB*(1+num_nodes)*sizeof(*sal_ptcdi);
-	sal_ptclid  = (void *) cp; cp += ((3+num_cpus)*sizeof(*sal_ptclid)+7)/8*8;
-	cmd_line    = (void *) cp;
-
-	if (args) {
-		if (arglen >= 1024)
-			arglen = 1023;
-		memcpy(cmd_line, args, arglen);
-	} else {
-		arglen = 0;
-	}
-	cmd_line[arglen] = '\0';
-#ifdef BRINGUP
-	/* for now, just bring up bash */
-	strcpy(cmd_line, "init=/bin/bash");
-#else
-	strcpy(cmd_line, "");
-#endif
-
-	memset(efi_systab, 0, sizeof(efi_systab));
-	efi_systab->hdr.signature = EFI_SYSTEM_TABLE_SIGNATURE;
-	efi_systab->hdr.revision  = EFI_SYSTEM_TABLE_REVISION;
-	efi_systab->hdr.headersize = sizeof(efi_systab->hdr);
-	efi_systab->fw_vendor = __fwtab_pa(base_nasid, vendor);
-	efi_systab->fw_revision = 1;
-	efi_systab->runtime = __fwtab_pa(base_nasid, efi_runtime);
-	efi_systab->nr_tables = 2;
-	efi_systab->tables = __fwtab_pa(base_nasid, efi_tables);
-	memcpy(vendor, "S\0i\0l\0i\0c\0o\0n\0-\0G\0r\0a\0p\0h\0i\0c\0s\0\0", 32);
-
-	efi_runtime->hdr.signature = EFI_RUNTIME_SERVICES_SIGNATURE;
-	efi_runtime->hdr.revision = EFI_RUNTIME_SERVICES_REVISION;
-	efi_runtime->hdr.headersize = sizeof(efi_runtime->hdr);
-	efi_runtime->get_time = __fwtab_pa(base_nasid, &efi_get_time);
-	efi_runtime->set_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_wakeup_time = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_virtual_address_map = __fwtab_pa(base_nasid, &efi_set_virtual_address_map);
-	efi_runtime->get_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_next_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->set_variable = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->get_next_high_mono_count = __fwtab_pa(base_nasid, &efi_unimplemented);
-	efi_runtime->reset_system = __fwtab_pa(base_nasid, &efi_reset_system);
-
-	efi_tables->guid = SAL_SYSTEM_TABLE_GUID;
-	efi_tables->table = __fwtab_pa(base_nasid, sal_systab);
-	efi_tables++;
-	efi_tables->guid = ACPI_TABLE_GUID;
-	efi_tables->table = __fwtab_pa(base_nasid, acpi_systab);
-	fix_function_pointer(&efi_unimplemented);
-	fix_function_pointer(&efi_get_time);
-	fix_function_pointer(&efi_success);
-	fix_function_pointer(&efi_reset_system);
-	fix_function_pointer(&efi_set_virtual_address_map);
-
-	/* fill in the ACPI system table: */
-	memcpy(acpi_systab->signature, "RSD PTR ", 8);
-	acpi_systab->rsdt = (struct acpi_rsdt*)__fwtab_pa(base_nasid, acpi_rsdt);
-
-	memcpy(acpi_rsdt->header.signature, "RSDT",4);
-	acpi_rsdt->header.length = sizeof(acpi_rsdt_t);
-	memcpy(acpi_rsdt->header.oem_id, "SGI", 3);
-	memcpy(acpi_rsdt->header.oem_table_id, "SN1", 3);
-	acpi_rsdt->header.oem_revision = 0x00010001;
-	acpi_rsdt->entry_ptrs[0] = __fwtab_pa(base_nasid, acpi_sapic);
-
-	memcpy(acpi_sapic->header.signature, "SPIC ", 4);
-	acpi_sapic->header.length = sizeof(acpi_sapic_t)+num_cpus*sizeof(acpi_entry_lsapic_t);
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		nasid = GetNasid(cnode);
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (!IsCpuPresent(cnode, cpu))
-				continue;
-			acpi_lsapic->type = ACPI_ENTRY_LOCAL_SAPIC;
-			acpi_lsapic->length = sizeof(acpi_entry_lsapic_t);
-			acpi_lsapic->acpi_processor_id = cnode*4+cpu;
-			acpi_lsapic->flags = LSAPIC_ENABLED|LSAPIC_PRESENT;
-			acpi_lsapic->eid = cpu;
-			acpi_lsapic->id = nasid;
-			acpi_lsapic++;
-		}
-	}
-
-
-	/* fill in the SAL system table: */
-	memcpy(sal_systab->signature, "SST_", 4);
-	sal_systab->size = sizeof(*sal_systab);
-	sal_systab->sal_rev_minor = 1;
-	sal_systab->sal_rev_major = 0;
-	sal_systab->entry_count = 3;
-
-	strcpy(sal_systab->oem_id, "SGI");
-	strcpy(sal_systab->product_id, "SN1");
-
-	/* fill in an entry point: */	
-	sal_ed->type = SAL_DESC_ENTRY_POINT;
-	sal_ed->pal_proc = __fwtab_pa(base_nasid, pal_desc[0]);
-	sal_ed->sal_proc = __fwtab_pa(base_nasid, sal_desc[0]);
-	sal_ed->gp = __fwtab_pa(base_nasid, sal_desc[1]);
-
-	/* kludge the PTC domain info */
-	sal_ptc->type = SAL_DESC_PTC;
-	sal_ptc->num_domains = 0;
-	sal_ptc->domain_info = __fwtab_pa(base_nasid, sal_ptcdi);
-	cpus_found = 0;
-	last_domain = -1;
-	sal_ptcdi--;
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		nasid = GetNasid(cnode);
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (IsCpuPresent(cnode, cpu)) {
-				domain = cnode*CPUS_PER_NODE + cpu/CPUS_PER_FSB;
-				if (domain != last_domain) {
-					sal_ptc->num_domains++;
-					sal_ptcdi++;
-					sal_ptcdi->proc_count = 0;
-					sal_ptcdi->proc_list = __fwtab_pa(base_nasid, sal_ptclid);
-					last_domain = domain;
-				}
-				sal_ptcdi->proc_count++;
-				sal_ptclid->id = nasid;
-				sal_ptclid->eid = cpu;
-				sal_ptclid++;
-				cpus_found++;
-			}
-		}
-	}
-
-	if (cpus_found != num_cpus)
-		FPROM_BUG();
-
-	/* Make the AP WAKEUP entry */
-	sal_apwake->type = SAL_DESC_AP_WAKEUP;
-	sal_apwake->mechanism = IA64_SAL_AP_EXTERNAL_INT;
-	sal_apwake->vector = 18;
-
-	for (cp = (char *) sal_systab; cp < (char *) efi_memmap; ++cp)
-		checksum += *cp;
-
-	sal_systab->checksum = -checksum;
-
-	md = &efi_memmap[0];
-	num_memmd = build_efi_memmap((void *)md, mdsize) ;
-
-	bp = id(ZERO_PAGE_ADDR + (((long)base_nasid)<<33));
-	bp->efi_systab = __fwtab_pa(base_nasid, &fw_mem);
-	bp->efi_memmap = __fwtab_pa(base_nasid, efi_memmap);
-	bp->efi_memmap_size = num_memmd*mdsize;
-	bp->efi_memdesc_size = mdsize;
-	bp->efi_memdesc_version = 0x101;
-	bp->command_line = __fwtab_pa(base_nasid, cmd_line);
-	bp->console_info.num_cols = 80;
-	bp->console_info.num_rows = 25;
-	bp->console_info.orig_x = 0;
-	bp->console_info.orig_y = 24;
-	bp->num_pci_vectors = 0;
-	bp->fpswa = 0;
-
-	/*
-	 * Now pick the BSP & store it LID value in
-	 * a global variable. Note if BSP is greater than last cpu,
-	 * pick the last cpu.
-	 */
-	for (cnode=0; cnode<num_nodes; cnode++) {
-		for(cpu=0; cpu<CPUS_PER_NODE; cpu++) {
-			if (!IsCpuPresent(cnode, cpu))
-				continue;
-			bsp_lid = (GetNasid(cnode)<<24) | (cpu<<16);
-			if (bsp-- > 0)
-				continue;
-			return;
-		}
-	}
-}
diff -Nru a/arch/ia64/sn/fprom/main.c b/arch/ia64/sn/fprom/main.c
--- a/arch/ia64/sn/fprom/main.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,110 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-
-
-#include <linux/types.h>
-#include <asm/bitops.h>
-
-void bedrock_init(int);
-void synergy_init(int, int);
-void sys_fw_init (const char *args, int arglen, int bsp);
-
-volatile int	bootmaster=0;		/* Used to pick bootmaster */
-volatile int	nasidmaster[128]={0};	/* Used to pick node/synergy masters */
-int		init_done=0;
-extern int	bsp_lid;
-
-#define get_bit(b,p)	(((*p)>>(b))&1)
-
-int
-fmain(int lid, int bsp) {
-	int	syn, nasid, cpu;
-
-	/*
-	 * First lets figure out who we are. This is done from the
-	 * LID passed to us.
-	 */
-	nasid = (lid>>24);
-	syn = (lid>>17)&1;
-	cpu = (lid>>16)&1;
-
-	/*
-	 * Now pick a synergy master to initialize synergy registers.
-	 */
-	if (test_and_set_bit(syn, &nasidmaster[nasid]) == 0) {
-		synergy_init(nasid, syn);
-		test_and_set_bit(syn+2, &nasidmaster[nasid]);
-	} else
-		while (get_bit(syn+2, &nasidmaster[nasid]) == 0);
-	
-	/*
-	 * Now pick a nasid master to initialize Bedrock registers.
-	 */
-	if (test_and_set_bit(8, &nasidmaster[nasid]) == 0) {
-		bedrock_init(nasid);
-		test_and_set_bit(9, &nasidmaster[nasid]);
-	} else
-		while (get_bit(9, &nasidmaster[nasid]) == 0);
-	
-
-	/*
-	 * Now pick a BSP & finish init.
-	 */
-	if (test_and_set_bit(0, &bootmaster) == 0) {
-		sys_fw_init(0, 0, bsp);
-		test_and_set_bit(1, &bootmaster);
-	} else
-		while (get_bit(1, &bootmaster) == 0);
-
-	return (lid == bsp_lid);
-}
-
-
-void
-bedrock_init(int nasid)
-{
-	nasid = nasid;		/* to quiet gcc */
-}
-
-
-void
-synergy_init(int nasid, int syn)
-{
-	long	*base;
-	long	off;
-
-	/*
-	 * Enable all FSB flashed interrupts.
-	 * ZZZ - I'd really like defines for this......
-	 */
-	base = (long*)0x80000e0000000000LL;		/* base of synergy regs */
-	for (off = 0x2a0; off < 0x2e0; off+=8)		/* offset for VEC_MASK_{0-3}_A/B */
-		*(base+off/8) = -1LL;
-
-	/*
-	 * Set the NASID in the FSB_CONFIG register.
-	 */
-	base = (long*)0x80000e0000000450LL;
-	*base = (long)((nasid<<16)|(syn<<9));
-}
-
-
-/* Why isnt there a bcopy/memcpy in lib64.a */
-
-void* 
-memcpy(void * dest, const void *src, size_t count)
-{
-	char *s, *se, *d;
-
-	for(d=dest, s=(char*)src, se=s+count; s<se; s++, d++)
-		*d = *s;
-	return dest;
-}
diff -Nru a/arch/ia64/sn/fprom/runsim b/arch/ia64/sn/fprom/runsim
--- a/arch/ia64/sn/fprom/runsim	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,372 +0,0 @@
-#!/bin/sh
-
-# Script for running PROMs and LINUX kernwls on medusa. 
-# Type "sim -H" for instructions.
-
-MEDUSA=${MEDUSA:-/home/rickc/official_medusa/medusa}
-
-# ------------------ err -----------------------
-err() {
-	echo "ERROR - $1"
-	exit 1
-}
-
-# ----------------  help ----------------------
-help() {
-cat <<END
-Script for running a PROM or LINUX kernel under medusa.
-This script creates a control file, creates links to the appropriate
-linux/prom files, and/or calls medusa to make simulation runs.
-
-Usage:  
-   Initial setup:
-   	sim [-c <config_file>] <-p> | <-k>  [<work_dir>]
-		-p	Create PROM control file & links
-		-k	Create LINUX control file & links
-		-c<cf>	Control file name				[Default: cf]
-		<work_dir> Path to directory that contains the linux or PROM files.
-		    The directory can be any of the following:
-		       (linux simulations)
-		       		worktree
-				worktree/linux
-				any directory with vmlinux, vmlinux.sym & fprom files
-			(prom simulations)
-				worktree
-				worktree/stand/arcs/IP37prom/dev
-				any directory with fw.bin & fw.sim files
-
-    Simulations:
-	sim  [-X <n>] [-o <output>] [-M] [<config_file>]
-		-c<cf>	Control file name				[Default: cf]
-		-M	Pipe output thru fmtmedusa
-		-o	Output filename (copy of all commands/output)	[Default: simout]
-		-X	Specifies number of instructions to execute	[Default: 0]
-			(Used only in auto test mode - not described here)
-
-Examples:
-	sim -p <promtree>	# create control file (cf) & links for prom simulations
-	sim -k <linuxtree>	# create control file (cf) & links for linux simulations
-	sim -p -c cfprom	# create a prom control file (cfprom) only. No links are made.
-
-	sim			# run medusa using previously created links &
-				#   control file (cf).
-END
-exit 1
-}
-
-# ----------------------- create control file header --------------------
-create_cf_header() {
-cat <<END >>$CF
-#
-# Template for a control file for running linux kernels under medusa. 
-# You probably want to make mods here but this is a good starting point.
-#
-
-# Preferences
-setenv cpu_stepping A
-setenv exceptionPrint off
-setenv interrupt_messages off
-setenv lastPCsize 100000
-setenv low_power_mode on
-setenv partialIntelChipSet on
-setenv printIntelMessages off
-setenv prom_write_action halt
-setenv prom_write_messages on
-setenv step_quantum 100
-setenv swizzling on
-setenv tsconsole on
-setenv uart_echo on
-symbols on
-
-# IDE disk params
-setenv diskCylinders 611
-setenv bootDrive C
-setenv diskHeads 16
-setenv diskPath idedisk
-setenv diskPresent 1
-setenv diskSpt 63
-
-# Hardware config
-setenv coherency_type nasid
-setenv cpu_cache_type default
-setenv synergy_cache_type syn_cac_64m_8w
-
-# Numalink config
-setenv route_enable on
-setenv network_type xbar		# Select [xbar|router]
-setenv network_warning 0xff
-
-END
-}
-
-
-# ------------------ create control file entries for linux simulations -------------
-create_cf_linux() {
-cat <<END >>$CF
-# Kernel specific options
-setenv mca_on_memory_failure off
-setenv LOADPC 0x00100000		# FPROM load address/entry point (8 digits!)
-sr g 9 0xe000000000520000		# Kernel entry point
-setenv symbol_table vmlinux.sym
-load fprom
-load vmlinux
-
-# Useful breakpoints to always have set. Add more if desired.
-break 0xe000000000505e00	all	# dispatch_to_fault_handler
-break panic			all	# stop on panic
-break die_if_kernel		all	# may as well stop
-
-END
-}
-
-# ------------------ create control file entries for prom simulations ---------------
-create_cf_prom() {
-	SYM2=""
-	ADDR="0x80000000ff800000"
-	[ "$EMBEDDED_LINUX" != "0" ] || SYM2="setenv symbol_table2 vmlinux.sym"
-	[ "$SIZE" = "8MB" ] || ADDR="0x80000000ffc00000"
-	cat <<END >>$CF
-# PROM specific options
-setenv mca_on_memory_failure on
-setenv LOADPC 0x80000000ffffffb0
-setenv promFile fw.bin
-setenv promAddr $ADDR
-setenv symbol_table fw.sym
-$SYM2
-
-# Useful breakpoints to always have set. Add more if desired.
-break Pr_ivt_gexx 		all
-break Pr_ivt_brk		all
-break Pr_PROM_Panic_Spin	all
-break Pr_PROM_Panic		all
-break Pr_PROM_C_Panic		all
-break Pr_fled_die		all
-break Pr_ResetNow		all
-break Pr_zzzbkpt		all
-
-END
-}
-
-
-# ------------------ create control file entries for memory configuration -------------
-create_cf_memory() {
-cat <<END >>$CF
-# CPU/Memory map format:
-#	setenv nodeN_memory_config 0xBSBSBSBS
-#		B=banksize (0=unused, 1=64M, 2=128M, .., 5-1G, c=8M, d=16M, e=32M)
-#		S=bank enable (0=both disable, 3=both enable, 2=bank1 enable, 1=bank0 enable)
-#		  rightmost digits are for bank 0, the lowest address.
-#	setenv nodeN_nasid <nasid>
-#		specifies the NASID for the node. This is used ONLY if booting the kernel.
-#		On PROM configurations, set to 0 - PROM will change it later.
-#	setenv nodeN_cpu_config <cpu_mask>
-#		Set bit number N to 1 to enable cpu N. Ex., a value of 5 enables cpu 0 & 2.
-#
-# Repeat the above 3 commands for each node.
-#
-# For kernel, default to 32MB. Although this is not a valid hardware configuration,
-# it runs faster on medusa. For PROM, 64MB is smallest allowed value.
-
-setenv node0_cpu_config		0x1	# Enable only cpu 0 on the node
-END
-
-if [ $LINUX -eq 1 ] ; then
-cat <<END >>$CF
-setenv node0_nasid		0	# cnode 0 has NASID 0
-setenv node0_memory_config 	0xe1	# 32MB
-END
-else
-cat <<END >>$CF
-setenv node0_memory_config 	0x11	# 64MB
-END
-fi
-}
-
-# -------------------- set links to linux files -------------------------
-set_linux_links() {
-	if [ -d $D/linux/arch ] ; then
-		D=$D/linux
-	elif [ -d $D/arch -o -e vmlinux.sym ] ; then
-		D=$D
-	else
-		err "cant determine directory for linux binaries"
-	fi
-	rm -rf vmlinux vmlinux.sym fprom
-	ln -s $D/vmlinux vmlinux
-	ln -s $D/vmlinux.sym vmlinux.sym
-	if [ -d $D/arch ] ; then
-		ln -s $D/arch/ia64/sn/fprom/fprom fprom
-	else
-		ln -s $D/fprom fprom
-	fi
-	echo "  .. Created links to linux files"	
-}
-
-# -------------------- set links to prom files -------------------------
-set_prom_links() {
-	if [ -d $D/stand ] ; then
-		D=$D/stand/arcs/IP37prom/dev
-	elif [ -d $D/sal ] ; then
-		D=$D
-	else
-		err "cant determine directory for PROM binaries"
-	fi
-	SETUP="$D/../../../../.setup"
-	grep -q '^ *setenv *PROMSIZE *8MB' $SETUP
-	if [ $? -eq 0 ] ; then
-		SIZE="8MB"
-	else
-		SIZE="4MB"
-	fi
-	grep -q '^ *setenv *LAUNCH_VMLINUX' $SETUP
-	EMBEDDED_LINUX=$?
-	rm -f fw.bin fw.map fw.sym vmlinux vmlinux.sym fprom
-	SDIR="SN1IA${SIZE}.O"
-	BIN="SN1IAip37prom${SIZE}"
-	ln -s $D/$SDIR/$BIN.bin fw.bin
-	ln -s $D/$SDIR/$BIN.map fw.map
-	ln -s $D/$SDIR/$BIN.sym fw.sym
-	echo "  .. Created links to $SIZE prom files"
-	if [ $EMBEDDED_LINUX -eq 0 ] ; then
-		ln -s $D/linux/vmlinux vmlinux
-		ln -s $D/linux/vmlinux.sym vmlinux.sym
-		if [ -d linux/arch ] ; then
-			ln -s $D/linux/arch/ia64/sn/fprom/fprom fprom
-		else
-			ln -s $D/linux/fprom fprom
-		fi
-		echo "  .. Created links to embedded linux files in prom tree"
-	fi
-}
-
-# --------------- start of shell script --------------------------------
-OUT="simout"
-FMTMED=0
-STEPCNT=0
-PROM=0
-LINUX=0
-NCF="cf"
-while getopts "HMX:c:o:pk" c ; do
-        case ${c} in
-                H) help;;
-		M) FMTMED=1;;
-		X) STEPCNT=${OPTARG};;
-		c) NCF=${OPTARG};;
-		k) PROM=0;LINUX=1;;
-		p) PROM=1;LINUX=0;;
-		o) OUT=${OPTARG};;
-                \?) exit 1;;
-        esac
-done
-shift `expr ${OPTIND} - 1`
-
-# Check if command is for creating control file and/or links to images.
-if [ $PROM -eq 1 -o $LINUX -eq 1 ] ; then
-	CF=$NCF
-	[ ! -f $CF ] || err "wont overwrite an existing control file ($CF)"
-	if [ $# -gt 0 ] ; then
-		D=$1
-		[ -d $D ] || err "cannot find directory $D"
-		[ $PROM -eq 0 ]  || set_prom_links
-		[ $LINUX -eq 0 ] || set_linux_links
-	fi
-	create_cf_header
-	[ $PROM -eq 0 ]  || create_cf_prom
-	[ $LINUX -eq 0 ] || create_cf_linux
-	create_cf_memory
-	echo "  .. Basic control file created (in $CF). You might want to edit"
-	echo "     this file (at least, look at it)."
-	exit 0
-fi
-
-# Verify that the control file exists
-CF=${1:-$NCF}
-[ -f $CF ] || err "No control file exists. For help, type: $0 -H"
-
-# Build the .cf files from the user control file. The .cf file is
-# identical except that the actual start & load addresses are inserted
-# into the file. In addition, the FPROM commands for configuring memory
-# and LIDs are generated. 
-
-rm -f .cf .cf1 .cf2
-awk '
-function strtonum(n) {
-	 if (substr(n,1,2) != "0x")
-	 	return int(n)
-	 n = substr(n,3)
-	 r=0
-	 while (length(n) > 0) {
-	 	r = r*16+(index("0123456789abcdef", substr(n,1,1))-1)
-		n = substr(n,2)
-	 }
-	 return r
-	}
-/^#/   	{next}
-/^$/	{next}
-/^setenv *LOADPC/               {loadpc = $3; next}
-/^setenv *node._cpu_config/	{n=int(substr($2,5,1)); cpuconf[n] = strtonum($3); print; next}
-/^setenv *node._memory_config/	{n=int(substr($2,5,1)); memconf[n] = strtonum($3); print; next}
-/^setenv *node._nasid/		{n=int(substr($2,5,1)); nasid[n] = strtonum($3); print; next}
-		{print}
-END	{
-	 # Generate the memmap info that starts at the beginning of
-	 # the node the kernel was loaded on.
-	 loadnasid = nasid[0]
-	 cnode = 0
-	 for (i=0; i<128; i++) {
-		if (memconf[i] != "") {
-			printf "sm 0x%x%08x 0x%x%04x%04x\n", 
-				2*loadnasid, 8*cnodes+8, memconf[i], cpuconf[i], nasid[i]
-			cnodes++
-			cpus += substr("0112122312232334", cpuconf[i]+1,1)
-		}
-	 }
-	 printf "sm 0x%x00000000 0x%x%08x\n", 2*loadnasid, cnodes, cpus
-	 printf "setenv number_of_nodes %d\n", cnodes
-
-	 # Now set the starting PC for each cpu.
-	 cnode = 0
-	 lowcpu=-1
-	 for (i=0; i<128; i++) {
-		if (memconf[i] != "") {
-			printf "setnode %d\n", cnode
-			conf = cpuconf[i]
-			for (j=0; j<4; j++) {
-				if (conf != int(conf/2)*2) {
-	 				printf "setcpu %d\n", j
-					if (length(loadpc) == 18)
-						printf "sr pc %s\n", loadpc
-					else
-						printf "sr pc 0x%x%s\n", 2*loadnasid, substr(loadpc,3)
-					if (lowcpu == -1)
-						lowcpu = j
-				}
-				conf = int(conf/2)
-			}
-			cnode++
-		}
-	 }
-	 printf "setnode 0\n"
-	 printf "setcpu %d\n", lowcpu
-	}
-' <$CF >.cf
-
-# Now build the .cf1 & .cf2 control files.
-CF2_LINES="^sm |^break |^run |^si |^quit |^symbols "
-egrep  "$CF2_LINES" .cf >.cf2
-egrep -v "$CF2_LINES" .cf >.cf1
-if [ $STEPCNT -ne 0 ] ; then
-	echo "s $STEPCNT" >>.cf2
-	echo "lastpc 1000" >>.cf2
-	echo "q" >>.cf2
-fi
-echo "script-on $OUT" >>.cf2
-
-# Now start medusa....
-if [ $FMTMED -ne 0 ] ; then
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 |  fmtmedusa
-elif [ $STEPCNT -eq 0 ] ; then
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 
-else
-	$MEDUSA -system mpsn1 -c .cf1 -i .cf2 2>&1 
-fi
diff -Nru a/arch/ia64/sn/io/Makefile b/arch/ia64/sn/io/Makefile
--- a/arch/ia64/sn/io/Makefile	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/Makefile	Fri Mar 15 17:51:02 2002
@@ -3,8 +3,7 @@
 # License.  See the file "COPYING" in the main directory of this archive
 # for more details.
 #
-# Copyright (C) 2000 Silicon Graphics, Inc.
-# Copyright (C) Jack Steiner (steiner@sgi.com)
+# Copyright (C) 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
 #
 #
 # Makefile for the linux kernel.
@@ -13,20 +12,34 @@
 # removes any old dependencies. DON'T put your own dependencies here
 # unless it's something special (ie not a .c file).
 #
-# Note 2! The CFLAGS definitions are now in the main makefile...
 
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
 O_TARGET := sgiio.o
-obj-y   := stubs.o sgi_if.o pciio.o pcibr.o xtalk.o xbow.o xswitch.o hubspc.o \
-		klgraph_hack.o io.o hubdev.o huberror.o \
+
+ifeq ($(CONFIG_MODULES),y)
+export-objs = pciio.o hcl.o
+endif
+
+obj-y  := stubs.o sgi_if.o pciio.o xtalk.o xbow.o xswitch.o klgraph_hack.o \
 		hcl.o labelcl.o invent.o klgraph.o klconflib.o sgi_io_sim.o \
 		module.o sgi_io_init.o klgraph_hack.o ml_SN_init.o \
-		ml_SN_intr.o ip37.o pciba.o \
-		ml_iograph.o hcl_util.o cdl.o \
-		mem_refcnt.o devsupport.o alenlist.o pci_bus_cvlink.o \
-		eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o
+		ml_iograph.o hcl_util.o cdl.o hubdev.o hubspc.o \
+		alenlist.o pci_bus_cvlink.o \
+		eeprom.o pci.o pci_dma.o l1.o l1_command.o ate_utils.o \
+		ifconfig_net.o efi-rtc.o io.o
+
+obj-$(CONFIG_IA64_SGI_SN1)   += sn1/ml_SN_intr.o sn1/mem_refcnt.o sn1/hubcounters.o \
+				sn1/ip37.o sn1/huberror.o sn1/hub_intr.o sn1/pcibr.o
+
+obj-$(CONFIG_IA64_SGI_SN2)   += sn2/ml_SN_intr.o sn2/shub_intr.o sn2/shuberror.o \
+				sn2/bte_error.o \
+				sn2/pcibr/pcibr_dvr.o sn2/pcibr/pcibr_ate.o \
+				sn2/pcibr/pcibr_config.o sn2/pcibr/pcibr_dvr.o \
+				sn2/pcibr/pcibr_hints.o \
+				sn2/pcibr/pcibr_idbg.o sn2/pcibr/pcibr_intr.o \
+				sn2/pcibr/pcibr_rrb.o sn2/pcibr/pcibr_slot.o 
+
+obj-$(CONFIG_PCIBA) += pciba.o
 
 include $(TOPDIR)/Rules.make
diff -Nru a/arch/ia64/sn/io/alenlist.c b/arch/ia64/sn/io/alenlist.c
--- a/arch/ia64/sn/io/alenlist.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/alenlist.c	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /* Implementation of Address/Length Lists. */
@@ -13,9 +12,9 @@
 
 #include <linux/types.h>
 #include <linux/slab.h>
+#include <linux/mmzone.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/alenlist.h>
-#include <asm/sn/mmzone_sn1.h>
 
 /*
  * Logically, an Address/Length List is a list of Pairs, where each pair
@@ -218,9 +217,9 @@
 void
 alenlist_init(void)
 {
-	alenlist_zone = kmem_zone_init(sizeof(struct alenlist_s), "alenlist");
-	alenlist_chunk_zone = kmem_zone_init(sizeof(struct alenlist_chunk_s), "alchunk");
-	alenlist_cursor_zone = kmem_zone_init(sizeof(struct alenlist_cursor_s), "alcursor");
+	alenlist_zone = snia_kmem_zone_init(sizeof(struct alenlist_s), "alenlist");
+	alenlist_chunk_zone = snia_kmem_zone_init(sizeof(struct alenlist_chunk_s), "alchunk");
+	alenlist_cursor_zone = snia_kmem_zone_init(sizeof(struct alenlist_cursor_s), "alcursor");
 #if DEBUG
 	idbg_addfunc("alenshow", alenlist_show);
 #endif /* DEBUG */
@@ -250,7 +249,7 @@
 {
 	alenlist_t alenlist;
 
-	alenlist = kmem_zone_alloc(alenlist_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
+	alenlist = snia_kmem_zone_alloc(alenlist_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 	if (alenlist) {
 		INCR_COUNT(&alenlist_count);
 
@@ -334,7 +333,7 @@
 		while (chunk) {
 			freechunk = chunk;
 			chunk = chunk->alc_next;
-			kmem_zone_free(alenlist_chunk_zone, freechunk);
+			snia_kmem_zone_free(alenlist_chunk_zone, freechunk);
 			DECR_COUNT(&alenlist_chunk_count);
 		}
 		alenlist->al_actual_size = ALEN_CHUNK_SZ;
@@ -407,7 +406,7 @@
 		alenlist_clear(alenlist);
 
 	/* Now, free the alenlist itself */
-	kmem_zone_free(alenlist_zone, alenlist);
+	snia_kmem_zone_free(alenlist_zone, alenlist);
 	DECR_COUNT(&alenlist_count);
 }
 
@@ -473,7 +472,7 @@
 			} else {
 				alenlist_chunk_t new_chunk;
 
-				new_chunk = kmem_zone_alloc(alenlist_chunk_zone, 
+				new_chunk = snia_kmem_zone_alloc(alenlist_chunk_zone, 
 							flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 
 				if (new_chunk == NULL)
@@ -656,7 +655,7 @@
 	alenlist_cursor_t cursorp;
 
 	ASSERT(alenlist != NULL);
-	cursorp = kmem_zone_alloc(alenlist_cursor_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
+	cursorp = snia_kmem_zone_alloc(alenlist_cursor_zone, flags & AL_NOSLEEP ? VM_NOSLEEP : 0);
 	if (cursorp) {
 		INCR_COUNT(&alenlist_cursor_count);
 		alenlist_cursor_init(alenlist, 0, cursorp);
@@ -671,7 +670,7 @@
 alenlist_cursor_destroy(alenlist_cursor_t cursorp)
 {
 	DECR_COUNT(&alenlist_cursor_count);
-	kmem_zone_free(alenlist_cursor_zone, cursorp);
+	snia_kmem_zone_free(alenlist_cursor_zone, cursorp);
 }
 
 
@@ -752,7 +751,7 @@
 			maxlength -= 
 			   ((alenp->al_addr + cursorp->al_bcount) & maxlen1);
 
-		length = MIN(maxlength, length);
+		length = min(maxlength, length);
 	}
 
 	/* Update the cursor, if desired. */
@@ -842,7 +841,7 @@
 	offset = poff(kvaddr);
 
 	/* Handle first page */
-	piece_length = MIN(NBPP - offset, length);
+	piece_length = min((size_t)(NBPP - offset), length);
 	if (alenlist_append(alenlist, paddr, piece_length, flags) == ALENLIST_FAILURE)
 		goto failure;
 	length -= piece_length;
diff -Nru a/arch/ia64/sn/io/ate_utils.c b/arch/ia64/sn/io/ate_utils.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/ate_utils.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,205 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/io.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/ioerror_handling.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/sn_private.h>
+
+#include <asm/sn/ate_utils.h>
+
+/*
+ * Allocate the map needed to allocate the ATE entries.
+ */
+struct map *
+atemapalloc(ulong_t mapsiz)
+{
+	struct map *mp;
+	ulong_t size;
+	struct a {
+		spinlock_t lock;
+		sv_t 	sema;
+	} *sync;
+
+	if (mapsiz == 0)
+		return(NULL);
+	size = sizeof(struct map) * (mapsiz + 2);
+	if ((mp = (struct map *) kmalloc(size, GFP_KERNEL)) == NULL)
+		return(NULL);
+	memset(mp, 0x0, size);
+
+	sync = kmalloc(sizeof(struct a), GFP_KERNEL);
+	if (sync == NULL) {
+		kfree(mp);
+		return(NULL);
+	}
+	memset(sync, 0x0, sizeof(struct a));
+
+	mutex_spinlock_init(&sync->lock);
+	sv_init( &(sync->sema), &(sync->lock), SV_MON_SPIN | SV_ORDER_FIFO /*| SV_INTS*/);
+	mp[1].m_size = (unsigned long) &sync->lock;
+	mp[1].m_addr = (unsigned long) &sync->sema;
+	mapsize(mp) = mapsiz - 1;
+	return(mp);
+}
+
+/*
+ * free a map structure previously allocated via rmallocmap().
+ */
+void
+atemapfree(struct map *mp)
+{
+	struct a {
+		spinlock_t lock;
+		sv_t 	sema;
+	};
+	/* ASSERT(sv_waitq(mapout(mp)) == 0); */
+	/* sv_destroy(mapout(mp)); */
+	spin_lock_destroy(maplock(mp));
+	kfree((void *)mp[1].m_size);
+	kfree(mp);
+}
+
+/*
+ * Allocate 'size' units from the given map.
+ * Return the base of the allocated space.
+ * In a map, the addresses are increasing and the
+ * list is terminated by a 0 size.
+ * Algorithm is first-fit.
+ */
+
+ulong_t
+atealloc(
+	struct map *mp,
+	size_t size)
+{
+	register unsigned int a;
+	register struct map *bp;
+	register unsigned long s;
+
+	ASSERT(size >= 0);
+
+	if (size == 0)
+		return((ulong_t) NULL);
+
+	s = mutex_spinlock(maplock(mp));
+
+	for (bp = mapstart(mp); bp->m_size; bp++) {
+		if (bp->m_size >= size) {
+			a = bp->m_addr;
+			bp->m_addr += size;
+			if ((bp->m_size -= size) == 0) {
+				do {
+					bp++;
+					(bp-1)->m_addr = bp->m_addr;
+				} while ((((bp-1)->m_size) = (bp->m_size)));
+				mapsize(mp)++;
+			}
+
+			ASSERT(bp->m_size < 0x80000000);
+			mutex_spinunlock(maplock(mp), s);
+			return(a);
+		}
+	}
+
+	/*
+	 * We did not get what we need .. we cannot sleep .. 
+	 */
+	mutex_spinunlock(maplock(mp), s);
+	return(0);
+}
+
+/*
+ * Free the previously allocated space a of size units into the specified map.
+ * Sort ``a'' into map and combine on one or both ends if possible.
+ * Returns 0 on success, 1 on failure.
+ */
+void
+atefree(struct map *mp, size_t size, ulong_t a)
+{
+	register struct map *bp;
+	register unsigned int t;
+	register unsigned long s;
+
+	ASSERT(size >= 0);
+
+	if (size == 0)
+		return;
+
+	bp = mapstart(mp);
+	s = mutex_spinlock(maplock(mp));
+
+	for ( ; bp->m_addr<=a && bp->m_size!=0; bp++)
+		;
+	if (bp>mapstart(mp) && (bp-1)->m_addr+(bp-1)->m_size == a) {
+		(bp-1)->m_size += size;
+		if (bp->m_addr) {	
+			/* m_addr==0 end of map table */
+			ASSERT(a+size <= bp->m_addr);
+			if (a+size == bp->m_addr) { 
+
+				/* compress adjacent map addr entries */
+				(bp-1)->m_size += bp->m_size;
+				while (bp->m_size) {
+					bp++;
+					(bp-1)->m_addr = bp->m_addr;
+					(bp-1)->m_size = bp->m_size;
+				}
+				mapsize(mp)++;
+			}
+		}
+	} else {
+		if (a+size == bp->m_addr && bp->m_size) {
+			bp->m_addr -= size;
+			bp->m_size += size;
+		} else {
+			ASSERT(size);
+			if (mapsize(mp) == 0) {
+				mutex_spinunlock(maplock(mp), s);
+				printk("atefree : map overflow 0x%p Lost 0x%lx items at 0x%lx",
+						(void *)mp, size, a) ;
+				return ;
+			}
+			do {
+				t = bp->m_addr;
+				bp->m_addr = a;
+				a = t;
+				t = bp->m_size;
+				bp->m_size = size;
+				bp++;
+			} while ((size = t));
+			mapsize(mp)--;
+		}
+	}
+	mutex_spinunlock(maplock(mp), s);
+	/*
+	 * wake up everyone waiting for space
+	 */
+	if (mapout(mp))
+		;
+		/* sv_broadcast(mapout(mp)); */
+}
diff -Nru a/arch/ia64/sn/io/cdl.c b/arch/ia64/sn/io/cdl.c
--- a/arch/ia64/sn/io/cdl.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/cdl.c	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -17,11 +16,9 @@
 #include "asm/sn/ioerror_handling.h"
 #include <asm/sn/xtalk/xbow.h>
 
-#ifdef BRINGUP
 /* these get called directly in cdl_add_connpt in fops bypass hack */
 extern int pcibr_attach(devfs_handle_t);
 extern int xbow_attach(devfs_handle_t);
-#endif /* BRINGUP */
 
 /*
  *    cdl: Connection and Driver List
@@ -37,8 +34,6 @@
     int		mfg_num;
     int (*attach) (devfs_handle_t);
 } dummy_reg;
-
-typedef struct cdl     *cdl_p;
 
 #define MAX_SGI_IO_INFRA_DRVR 4
 struct cdl sgi_infrastructure_drivers[MAX_SGI_IO_INFRA_DRVR] =
diff -Nru a/arch/ia64/sn/io/devsupport.c b/arch/ia64/sn/io/devsupport.c
--- a/arch/ia64/sn/io/devsupport.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,1289 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/iobus.h>
-#include <asm/sn/iograph.h>
-
-/* 
- * Interfaces in this file are all platform-independent AND IObus-independent.
- * Be aware that there may be macro equivalents to each of these hiding in
- * header files which supercede these functions.
- */
-
-/* =====Generic iobus support===== */
-
-/* String table to hold names of interrupts. */
-#ifdef LATER
-static struct string_table device_desc_string_table;
-#endif
-
-/* One time initialization for device descriptor support. */
-static void
-device_desc_init(void)
-{
-#ifdef LATER
-	string_table_init(&device_desc_string_table);
-#endif
-	FIXME("device_desc_init");
-}
-
-
-/* Drivers use these interfaces to manage device descriptors */
-static device_desc_t
-device_desc_alloc(void)
-{
-#ifdef LATER
-	device_desc_t device_desc;
-
-	device_desc = (device_desc_t)kmem_zalloc(sizeof(struct device_desc_s), 0);
-	device_desc->intr_target = GRAPH_VERTEX_NONE;
-
-	ASSERT(device_desc->intr_policy == 0);
-	device_desc->intr_swlevel = -1;
-	ASSERT(device_desc->intr_name == NULL);
-	ASSERT(device_desc->flags == 0);
-
-	ASSERT(!(device_desc->flags & D_IS_ASSOC));
-	return(device_desc);
-#else
-	FIXME("device_desc_alloc");
-	return((device_desc_t)0);
-#endif
-}
-
-void
-device_desc_free(device_desc_t device_desc)
-{
-#ifdef LATER
-	if (!(device_desc->flags & D_IS_ASSOC)) /* sanity */
-		kfree(device_desc);
-#endif
-	FIXME("device_desc_free");
-}
-
-device_desc_t
-device_desc_dup(devfs_handle_t dev)
-{
-#ifdef LATER
-	device_desc_t orig_device_desc, new_device_desc;
-
-
-	new_device_desc = device_desc_alloc();
-	orig_device_desc = device_desc_default_get(dev);
-	if (orig_device_desc)
-		*new_device_desc = *orig_device_desc;/* small structure copy */
-	else {
-		device_driver_t		driver;
-		ilvl_t			pri;		
-		/* 
-		 * Use the driver's thread priority in 
-		 * case the device thread priority has not
-		 * been given.
-		 */
-		if (driver = device_driver_getbydev(dev)) {
-			pri = device_driver_thread_pri_get(driver);
-			device_desc_intr_swlevel_set(new_device_desc,pri);
-		}
-	}		
-	new_device_desc->flags &= ~D_IS_ASSOC;
-	return(new_device_desc);
-#else
-	FIXME("device_desc_dup");
-	return((device_desc_t)0);
-#endif
-}
-
-device_desc_t	
-device_desc_default_get(devfs_handle_t dev)
-{
-#ifdef LATER
-	graph_error_t rc;
-	device_desc_t device_desc;
-
-	rc = hwgraph_info_get_LBL(dev, INFO_LBL_DEVICE_DESC, (arbitrary_info_t *)&device_desc);
-
-	if (rc == GRAPH_SUCCESS)
-		return(device_desc);
-	else
-		return(NULL);
-#else
-	FIXME("device_desc_default_get");
-	return((device_desc_t)0);
-#endif
-}
-
-void		
-device_desc_default_set(devfs_handle_t dev, device_desc_t new_device_desc)
-{
-#ifdef LATER
-	graph_error_t rc;
-	device_desc_t old_device_desc = NULL;
-
-	if (new_device_desc) {
-		new_device_desc->flags |= D_IS_ASSOC;
-		rc = hwgraph_info_add_LBL(dev, INFO_LBL_DEVICE_DESC, 
-						(arbitrary_info_t)new_device_desc);
-		if (rc == GRAPH_DUP) {
-			rc = hwgraph_info_replace_LBL(dev, INFO_LBL_DEVICE_DESC, 
-				(arbitrary_info_t)new_device_desc, 
-				(arbitrary_info_t *)&old_device_desc);
-
-			ASSERT(rc == GRAPH_SUCCESS);
-		}
-		hwgraph_info_export_LBL(dev, INFO_LBL_DEVICE_DESC,
-					sizeof(struct device_desc_s));
-	} else {
-		rc = hwgraph_info_remove_LBL(dev, INFO_LBL_DEVICE_DESC,
-					(arbitrary_info_t *)&old_device_desc);
-	}
-
-	if (old_device_desc) {
-		ASSERT(old_device_desc->flags & D_IS_ASSOC);
-		old_device_desc->flags &= ~D_IS_ASSOC;
-		device_desc_free(old_device_desc);
-	}
-#endif
-	FIXME("device_desc_default_set");
-}
-
-devfs_handle_t
-device_desc_intr_target_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_target);
-#else
-	FIXME("device_desc_intr_target_get");
-	return((devfs_handle_t)0);
-#endif
-}
-
-int
-device_desc_intr_policy_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_policy);
-#else
-	FIXME("device_desc_intr_policy_get");
-	return(0);
-#endif
-}
-
-ilvl_t
-device_desc_intr_swlevel_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_swlevel);
-#else
-	FIXME("device_desc_intr_swlevel_get");
-	return((ilvl_t)0);
-#endif
-}
-
-char *
-device_desc_intr_name_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->intr_name);
-#else
-	FIXME("device_desc_intr_name_get");
-	return(NULL);
-#endif
-}
-
-int
-device_desc_flags_get(device_desc_t device_desc)
-{
-#ifdef LATER
-	return(device_desc->flags);
-#else
-	FIXME("device_desc_flags_get");
-	return(0);
-#endif
-}
-
-void
-device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_target = target;
-}
-
-void
-device_desc_intr_policy_set(device_desc_t device_desc, int policy)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_policy = policy;
-}
-
-void
-device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_swlevel = swlevel;
-}
-
-void
-device_desc_intr_name_set(device_desc_t device_desc, char *name)
-{
-#ifdef LATER
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->intr_name = string_table_insert(&device_desc_string_table, name);
-#else
-	FIXME("device_desc_intr_name_set");
-#endif
-}
-
-void
-device_desc_flags_set(device_desc_t device_desc, int flags)
-{
-	if ( device_desc != (device_desc_t)0 )
-		device_desc->flags = flags;
-}
-
-
-
-/*============= device admin registry routines ===================== */
-
-/* Linked list of <admin-name,admin-val> pairs */
-typedef struct dev_admin_list_s {
-	struct dev_admin_list_s		*admin_next; 	/* next entry in the
-							 * list 
-							 */
-	char				*admin_name;	/* info label */
-	char				*admin_val;	/* actual info */
-} dev_admin_list_t;
-
-/* Device/Driver administration registry */
-typedef struct dev_admin_registry_s {
-	mrlock_t			reg_lock;	/* To allow
-							 * exclusive
-							 * access
-							 */
-	dev_admin_list_t		*reg_first;	/* first entry in 
-							 * the list
-							 */
-	dev_admin_list_t		**reg_last;	/* pointer to the
-							 * next to last entry
-							 * in the last which 
-							 * is also the place
-							 * where the new
-							 * entry gets
-							 * inserted
-							 */
-} dev_admin_registry_t;
-
-/*
-** device_driver_s associates a device driver prefix with device switch entries.
-*/
-struct device_driver_s {
-	struct device_driver_s	*dd_next;	/* next element on hash chain */
-	struct device_driver_s	*dd_prev;	/* previous element on hash chain */
-	char			*dd_prefix;	/* driver prefix string */
-	struct bdevsw		*dd_bdevsw;	/* driver's bdevsw */
-	struct cdevsw		*dd_cdevsw;	/* driver's cdevsw */
-	
-	/* driver administration specific data structures need to
-	 * maintain the list of <driver-paramater,value> pairs
-	 */
-	dev_admin_registry_t	dd_dev_admin_registry;
-	ilvl_t			dd_thread_pri;	/* default thread priority for
-						 *  all this driver's
-						 * threads.
-						 */
-
-};
-
-#define	NEW(_p)		(_p = kmalloc(sizeof(*_p), GFP_KERNEL))
-#define FREE(_p)	(kmem_free(_p))
-	
-/*
- * helpful lock macros
- */
-
-#define DEV_ADMIN_REGISTRY_INITLOCK(lockp,name)	mrinit(lockp,name)
-#define DEV_ADMIN_REGISTRY_RDLOCK(lockp)	mraccess(lockp)	       
-#define DEV_ADMIN_REGISTRY_WRLOCK(lockp)	mrupdate(lockp)	       
-#define DEV_ADMIN_REGISTRY_UNLOCK(lockp)	mrunlock(lockp)
-
-/* Initialize the registry 
- */
-static void
-dev_admin_registry_init(dev_admin_registry_t *registry)
-{
-#ifdef LATER
-	if ( registry != (dev_admin_registry_t *)0 )
-		DEV_ADMIN_REGISTRY_INITLOCK(&registry->reg_lock,
-				    "dev_admin_registry_lock");
-		registry->reg_first = NULL;
-		registry->reg_last = &registry->reg_first;
-	}
-#else
-	FIXME("dev_admin_registry_init");
-#endif
-}
-
-/*
- * add an <name , value > entry to the dev admin registry.
- * if the name already exists in the registry then change the
- * value iff the new value differs from the old value.
- * if the name doesn't exist a new list entry is created and put
- * at the end.
- */
-static void
-dev_admin_registry_add(dev_admin_registry_t	*registry,
-		       char			*name,
-		       char			*val)
-{
-#ifdef LATER
-	dev_admin_list_t	*reg_entry;
-	dev_admin_list_t	*scan = 0;
-
-	DEV_ADMIN_REGISTRY_WRLOCK(&registry->reg_lock);
-
-	/* check if the name already exists in the registry */
-	scan = registry->reg_first;
-
-	while (scan) {
-		if (strcmp(scan->admin_name,name) == 0) {
-			/* name is there in the registry */
-			if (strcmp(scan->admin_val,val)) {
-				/* old value != new value 
-				 * reallocate  memory and copy the new value
-				 */
-				FREE(scan->admin_val);
-				scan->admin_val = 
-					(char *)kern_calloc(1,strlen(val)+1);
-				strcpy(scan->admin_val,val);
-				goto out;
-			}
-			goto out;	/* old value == new value */
-		}
-		scan = scan->admin_next;
-	}
-
-	/* name is not there in the registry.
-	 * allocate memory for the new registry entry 
-	 */
-	NEW(reg_entry);
-	
-	reg_entry->admin_next   	= 0;
-	reg_entry->admin_name	= (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(reg_entry->admin_name,name);
-	reg_entry->admin_val	= (char *)kern_calloc(1,strlen(val)+1);
-	strcpy(reg_entry->admin_val,val);
-
-	/* add the entry at the end of the registry */
-
-	*(registry->reg_last)	= reg_entry;
-	registry->reg_last	= &reg_entry->admin_next;
-
-out:	DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-#endif
-	FIXME("dev_admin_registry_add");
-}
-/*
- * check if there is an info corr. to a particular
- * name starting from the cursor position in the 
- * registry
- */
-static char *
-dev_admin_registry_find(dev_admin_registry_t *registry,char *name)
-{
-#ifdef LATER
-	dev_admin_list_t	*scan = 0;
-	
-	DEV_ADMIN_REGISTRY_RDLOCK(&registry->reg_lock);
-	scan = registry->reg_first;
-
-	while (scan) {
-		if (strcmp(scan->admin_name,name) == 0) {
-			DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-			return scan->admin_val;
-		}
-		scan = scan->admin_next;
-	}
-	DEV_ADMIN_REGISTRY_UNLOCK(&registry->reg_lock);
-	return 0;
-#else
-	FIXME("dev_admin_registry_find");
-	return(NULL);
-#endif
-}
-/*============= MAIN DEVICE/ DRIVER ADMINISTRATION INTERFACE================ */
-/*
- * return any labelled info associated with a device.
- * called by any kernel code including device drivers.
- */
-char *
-device_admin_info_get(devfs_handle_t	dev_vhdl,
-		      char		*info_lbl)
-{
-#ifdef LATER
-	char		*info = 0;
-
-	/* return value need not be GRAPH_SUCCESS as the labelled
-	 * info may not be present
-	 */
-	(void)hwgraph_info_get_LBL(dev_vhdl,info_lbl,
-				   (arbitrary_info_t *)&info);
-
-	
-	return info;
-#else
-	FIXME("device_admin_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * set labelled info associated with a device.
- * called by hwgraph infrastructure . may also be called
- * by device drivers etc.
- */
-int
-device_admin_info_set(devfs_handle_t	dev_vhdl,
-		      char		*dev_info_lbl,
-		      char		*dev_info_val)
-{
-#ifdef LATER
-	graph_error_t		rv;
-	arbitrary_info_t	old_info;
-
-	/* Handle the labelled info
-	 *		intr_target
-	 *		sw_level 
-	 * in a special way. These are part of device_desc_t
-	 * Right now this is the only case where we have 
-	 * a set of related device_admin attributes which 
-	 * are grouped together.
-	 * In case there is a need for another set we need to
-	 * take a more generic approach to solving this.
-	 * Basically a registry should be implemented. This
-	 * registry is initialized with the callbacks for the
-	 * attributes which need to handled in a special way
-	 * For example:
-	 * Consider
-	 * 		device_desc
-	 *			intr_target
-	 *			intr_swlevel
-	 * register "do_intr_target" for intr_target
-	 * register "do_intr_swlevel" for intr_swlevel.
-	 * When the device_admin interface layer gets an <attr,val> pair
-	 * it looks in the registry to see if there is a function registered to
-	 * handle "attr. If not follow the default path of setting the <attr,val>
-	 * as labelled information hanging off the vertex.
-	 * In the above example:
-	 * "do_intr_target" does what is being done below for the ADMIN_LBL_INTR_TARGET
-	 * case
-	 */		
-	if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_TARGET) ||
-	    !strcmp(dev_info_lbl,ADMIN_LBL_INTR_SWLEVEL)) {
-
-		device_desc_t	device_desc;
-		
-		/* Check if there is a default device descriptor
-		 * information for this vertex. If not dup one .
-		 */
-		if (!(device_desc = device_desc_default_get(dev_vhdl))) {
-			device_desc = device_desc_dup(dev_vhdl);
-			device_desc_default_set(dev_vhdl,device_desc);
-
-		}
-		if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_TARGET)) {
-			/* Check if a target cpu has been specified
-			 * for this device by a device administration
-			 * directive
-			 */
-#ifdef DEBUG	
-			printf(ADMIN_LBL_INTR_TARGET
-			       " dev = 0x%x "
-			       "dev_admin_info = %s"
-			       " target = 0x%x\n",
-			       dev_vhdl,
-			       dev_info_lbl,
-			       hwgraph_path_to_vertex(dev_info_val));
-#endif	
-
-			device_desc->intr_target = 
-				hwgraph_path_to_vertex(dev_info_val);
-		} else if (!strcmp(dev_info_lbl,ADMIN_LBL_INTR_SWLEVEL)) {
-			/* Check if the ithread priority level  has been 
-			 * specified for this device by a device administration
-			 * directive
-			 */
-#ifdef DEBUG	
-			printf(ADMIN_LBL_INTR_SWLEVEL
-			       " dev = 0x%x "
-			       "dev_admin_info = %s"
-			       " sw level = 0x%x\n",
-			       dev_vhdl,
-			       dev_info_lbl,
-			       atoi(dev_info_val));
-#endif	
-			device_desc->intr_swlevel = atoi(dev_info_val);
-		}
-
-	}
-	if (!dev_info_val)
-		rv = hwgraph_info_remove_LBL(dev_vhdl,
-					     dev_info_lbl,
-					     &old_info);
-	else {
-
-		rv = hwgraph_info_add_LBL(dev_vhdl,
-					  dev_info_lbl,
-					  (arbitrary_info_t)dev_info_val);
-	
-		if (rv == GRAPH_DUP)  {
-			rv = hwgraph_info_replace_LBL(dev_vhdl,
-					      dev_info_lbl,
-					      (arbitrary_info_t)dev_info_val,
-					      &old_info);
-		}
-	}
-	ASSERT(rv == GRAPH_SUCCESS);
-#endif
-	FIXME("device_admin_info_set");
-	return 0;
-}
-
-/*
- * return labelled info associated with a device driver
- * called by kernel code including device drivers
- */
-char *
-device_driver_admin_info_get(char		*driver_prefix,
-			     char		*driver_info_lbl)
-{
-#ifdef LATER
-	device_driver_t driver;
-
-	driver = device_driver_get(driver_prefix);
-	return (dev_admin_registry_find(&driver->dd_dev_admin_registry,
-					driver_info_lbl));
-#else
-	FIXME("device_driver_admin_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * set labelled info associated with a device driver.
- * called by hwgraph infrastructure . may also be called
- * from drivers etc.
- */
-int
-device_driver_admin_info_set(char		*driver_prefix,
-			     char		*driver_info_lbl,
-			     char		*driver_info_val)
-{
-#ifdef LATER
-	device_driver_t driver;
-
-	driver = device_driver_get(driver_prefix);
-	dev_admin_registry_add(&driver->dd_dev_admin_registry,	
-			       driver_info_lbl,
-			       driver_info_val);
-#endif
-	FIXME("device_driver_admin_info_set");
-	return 0;
-}
-/*================== device / driver  admin support routines================*/
-
-/* static tables created by lboot */
-extern dev_admin_info_t	dev_admin_table[];
-extern dev_admin_info_t	drv_admin_table[];
-extern int		dev_admin_table_size;
-extern int		drv_admin_table_size;
-
-/* Extend the device admin table to allow the kernel startup code to 
- * provide some device specific administrative hints
- */
-#define ADMIN_TABLE_CHUNK	100
-static dev_admin_info_t extended_dev_admin_table[ADMIN_TABLE_CHUNK];	
-static int		extended_dev_admin_table_size = 0;
-static mrlock_t		extended_dev_admin_table_lock;
-
-/* Initialize the extended device admin table */
-void
-device_admin_table_init(void)
-{
-#ifdef LATER
-	extended_dev_admin_table_size = 0;
-	mrinit(&extended_dev_admin_table_lock,
-	       "extended_dev_admin_table_lock");
-#endif
-	FIXME("device_admin_table_init");
-}
-/* Add <device-name , parameter-name , parameter-value> triple to
- * the extended device administration info table. This is helpful
- * for kernel startup code to put some hints before the hwgraph
- * is setup 
- */
-void
-device_admin_table_update(char *name,char *label,char *value)
-{
-#ifdef LATER
-	dev_admin_info_t	*p;
-
-	mrupdate(&extended_dev_admin_table_lock);
-
-	/* Safety check that we haven't exceeded array limits */
-	ASSERT(extended_dev_admin_table_size < ADMIN_TABLE_CHUNK);
-
-	if (extended_dev_admin_table_size == ADMIN_TABLE_CHUNK)
-		goto out;
-	
-	/* Get the pointer to the entry in the table where we are
-	 * going to put the new information 
-	 */
-	p = &extended_dev_admin_table[extended_dev_admin_table_size++];
-
-	/* Allocate memory for the strings and copy them in */
-	p->dai_name = (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(p->dai_name,name);
-	p->dai_param_name = (char *)kern_calloc(1,strlen(label)+1);
-	strcpy(p->dai_param_name,label);
-	p->dai_param_val = (char *)kern_calloc(1,strlen(value)+1);
-	strcpy(p->dai_param_val,value);
-
-out:	mrunlock(&extended_dev_admin_table_lock);
-#endif
-	FIXME("device_admin_table_update");
-}
-/* Extend the device driver  admin table to allow the kernel startup code to 
- * provide some device driver specific administrative hints
- */
-
-static dev_admin_info_t extended_drv_admin_table[ADMIN_TABLE_CHUNK];	
-static int		extended_drv_admin_table_size = 0;
-mrlock_t		extended_drv_admin_table_lock;
-
-/* Initialize the extended device driver admin table */
-void
-device_driver_admin_table_init(void)
-{
-#ifdef LATER
-	extended_drv_admin_table_size = 0;
-	mrinit(&extended_drv_admin_table_lock,
-	       "extended_drv_admin_table_lock");
-#endif
-	FIXME("device_driver_admin_table_init");
-}
-/* Add <device-driver prefix , parameter-name , parameter-value> triple to
- * the extended device administration info table. This is helpful
- * for kernel startup code to put some hints before the hwgraph
- * is setup 
- */
-void
-device_driver_admin_table_update(char *name,char *label,char *value)
-{
-#ifdef LATER
-	dev_admin_info_t	*p;
-
-	mrupdate(&extended_dev_admin_table_lock);
-
-	/* Safety check that we haven't exceeded array limits */
-	ASSERT(extended_drv_admin_table_size < ADMIN_TABLE_CHUNK);
-
-	if (extended_drv_admin_table_size == ADMIN_TABLE_CHUNK)
-		goto out;
-	
-	/* Get the pointer to the entry in the table where we are
-	 * going to put the new information 
-	 */
-	p = &extended_drv_admin_table[extended_drv_admin_table_size++];
-
-	/* Allocate memory for the strings and copy them in */
-	p->dai_name = (char *)kern_calloc(1,strlen(name)+1);
-	strcpy(p->dai_name,name);
-	p->dai_param_name = (char *)kern_calloc(1,strlen(label)+1);
-	strcpy(p->dai_param_name,label);
-	p->dai_param_val = (char *)kern_calloc(1,strlen(value)+1);
-	strcpy(p->dai_param_val,value);
-
-out:	mrunlock(&extended_drv_admin_table_lock);
-#endif
-	FIXME("device_driver_admin_table_update");
-}
-/*
- * keeps on adding the labelled info for each new (lbl,value) pair
- * that it finds in the static dev admin table (  created by lboot)
- * and the extended dev admin table ( created if at all by the kernel startup
- *  code) corresponding to a device in the hardware graph.
- */
-void
-device_admin_info_update(devfs_handle_t	dev_vhdl)
-{
-#ifdef LATER
-	int			i = 0;
-	dev_admin_info_t	*scan;
-	devfs_handle_t		scan_vhdl;
-	
-	/* Check the static device administration info table */
-	scan = dev_admin_table;
-	while (i < dev_admin_table_size) {
-		
-		scan_vhdl = hwgraph_path_to_dev(scan->dai_name);
-		if (scan_vhdl == dev_vhdl) {
-			device_admin_info_set(dev_vhdl,
-					      scan->dai_param_name,
-					      scan->dai_param_val);
-		}
-		if (scan_vhdl != NODEV)
-			hwgraph_vertex_unref(scan_vhdl);
-		scan++;i++;
-
-	}
-	i = 0;
-	/* Check the extended device administration info table */
-	scan = extended_dev_admin_table;
-	while (i < extended_dev_admin_table_size) {
-		scan_vhdl = hwgraph_path_to_dev(scan->dai_name);
-		if (scan_vhdl == dev_vhdl) {
-			device_admin_info_set(dev_vhdl,
-					      scan->dai_param_name,
-					      scan->dai_param_val);
-		}
-		if (scan_vhdl != NODEV)
-			hwgraph_vertex_unref(scan_vhdl);
-		scan++;i++;
-
-	}
-
-
-#endif
-	FIXME("device_admin_info_update");
-}
-
-/* looks up the static drv admin table ( created by the lboot) and the extended
- * drv admin table (created if at all by the kernel startup code) 
- * for this driver specific administration info and adds it to the admin info 
- * associated with this device driver's object
- */
-void
-device_driver_admin_info_update(device_driver_t	driver)
-{
-#ifdef LATER
-	int			i = 0;
-	dev_admin_info_t	*scan;
-
-	/* Check the static device driver administration info table */
-	scan = drv_admin_table;
-	while (i < drv_admin_table_size) {
-
-		if (strcmp(scan->dai_name,driver->dd_prefix) == 0) {
-			dev_admin_registry_add(&driver->dd_dev_admin_registry,
-						scan->dai_param_name,
-					 	scan->dai_param_val);
-		}
-		scan++;i++;
-	}
-	i = 0;
-	/* Check the extended device driver administration info table */
-	scan = extended_drv_admin_table;
-	while (i < extended_drv_admin_table_size) {
-
-		if (strcmp(scan->dai_name,driver->dd_prefix) == 0) {
-			dev_admin_registry_add(&driver->dd_dev_admin_registry,
-						scan->dai_param_name,
-					 	scan->dai_param_val);
-		}
-		scan++;i++;
-	}
-#endif
-	FIXME("device_driver_admin_info_update");
-}
-
-/* =====Device Driver Support===== */
-
-
-
-/*
-** Generic device driver support routines for use by kernel modules that
-** deal with device drivers (but NOT for use by the drivers themselves).
-** EVERY registered driver currently in the system -- static or loadable --
-** has an entry in the device_driver_hash table.  A pointer to such an entry
-** serves as a generic device driver handle.
-*/
-
-#define DEVICE_DRIVER_HASH_SIZE 32
-#ifdef LATER
-lock_t device_driver_lock[DEVICE_DRIVER_HASH_SIZE];
-device_driver_t device_driver_hash[DEVICE_DRIVER_HASH_SIZE];
-static struct string_table driver_prefix_string_table;
-#endif
-
-/*
-** Initialize device driver infrastructure.
-*/
-void
-device_driver_init(void)
-{
-#ifdef LATER
-	int i;
-	extern void alenlist_init(void);
-	extern void hwgraph_init(void);
-	extern void device_desc_init(void);
-
-	ASSERT(DEVICE_DRIVER_NONE == NULL);
-	alenlist_init();
-	hwgraph_init();
-	device_desc_init();
-
-	string_table_init(&driver_prefix_string_table);
-
-	for (i=0; i<DEVICE_DRIVER_HASH_SIZE; i++) {
-		spin_lock_init(&device_driver_lock[i]);
-		device_driver_hash[i] = NULL;
-	}
-
-	/* Initialize static drivers from master.c table */
-	for (i=0; i<static_devsw_count; i++) {
-		device_driver_t driver;
-		static_device_driver_desc_t desc;
-		int pri;
-
-		desc = &static_device_driver_table[i];
-		driver = device_driver_get(desc->sdd_prefix);
-		if (!driver)
-			driver = device_driver_alloc(desc->sdd_prefix);
-		pri = device_driver_sysgen_thread_pri_get(desc->sdd_prefix);
-		device_driver_thread_pri_set(driver, pri);
-		device_driver_devsw_put(driver, desc->sdd_bdevsw, desc->sdd_cdevsw);
-	}
-#endif
-	FIXME("device_driver_init");
-}
-
-/*
-** Hash a prefix string into a hash table chain.
-*/
-static int
-driver_prefix_hash(char *prefix)
-{
-#ifdef LATER
-	int accum = 0;
-	char nextchar;
-
-	while (nextchar = *prefix++)
-		accum = accum ^ nextchar;
-
-	return(accum % DEVICE_DRIVER_HASH_SIZE);
-#else
-	FIXME("driver_prefix_hash");
-	return(0);
-#endif
-}
-
-
-/*
-** Allocate a driver handle.
-** Returns the driver handle, or NULL if the driver prefix 
-** already has a handle.
-** 
-** Upper layers prevent races among device_driver_alloc,
-** device_driver_free, and device_driver_get*.
-*/
-device_driver_t
-device_driver_alloc(char *prefix)
-{
-#ifdef LATER
-	int which_hash;
-	device_driver_t new_driver;
-	unsigned long s;
-		
-	which_hash = driver_prefix_hash(prefix);
-
-	new_driver = kern_calloc(1, sizeof(*new_driver));
-	ASSERT(new_driver != NULL);
-	new_driver->dd_prev = NULL;
-	new_driver->dd_prefix = string_table_insert(&driver_prefix_string_table, prefix);
-	new_driver->dd_bdevsw = NULL;
-	new_driver->dd_cdevsw = NULL;
-
-	dev_admin_registry_init(&new_driver->dd_dev_admin_registry);
-	device_driver_admin_info_update(new_driver);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-#if DEBUG
-	{
-		device_driver_t drvscan;
-
-		/* Make sure we haven't already added a driver with this prefix */
-		drvscan = device_driver_hash[which_hash];
-		while (drvscan && 
-		        strcmp(drvscan->dd_prefix, prefix)) {
-			drvscan = drvscan->dd_next;
-		}
-
-		ASSERT(!drvscan);
-	}
-#endif /* DEBUG */
-
-
-	/* Add new_driver to front of hash chain. */
-	new_driver->dd_next = device_driver_hash[which_hash];
-	if (new_driver->dd_next)
-		new_driver->dd_next->dd_prev = new_driver;
-	device_driver_hash[which_hash] = new_driver;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	return(new_driver);
-#else
-	FIXME("device_driver_alloc");
-	return((device_driver_t)0);
-#endif
-}
-
-/*
-** Free a driver handle.
-**
-** Statically loaded drivers should never device_driver_free.
-** Dynamically loaded drivers device_driver_free when either an
-** unloaded driver is unregistered, or when an unregistered driver
-** is unloaded.
-*/
-void
-device_driver_free(device_driver_t driver)
-{
-#ifdef LATER
-	int which_hash;
-	unsigned long s;
-
-	if (!driver)
-		return;
-
-	which_hash = driver_prefix_hash(driver->dd_prefix);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-#if DEBUG
-	{
-		device_driver_t drvscan;
-
-		/* Make sure we're dealing with the right list */
-		drvscan = device_driver_hash[which_hash];
-		while (drvscan && (drvscan != driver))
-			drvscan = drvscan->dd_next;
-
-		ASSERT(drvscan);
-	}
-#endif /* DEBUG */
-
-	if (driver->dd_next)
-		driver->dd_next->dd_prev = driver->dd_prev;
-
-	if (driver->dd_prev)
-		driver->dd_prev->dd_next = driver->dd_next;
-	else
-		device_driver_hash[which_hash] = driver->dd_next;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	driver->dd_next = NULL;		/* sanity */
-	driver->dd_prev = NULL;		/* sanity */
-	driver->dd_prefix = NULL;	/* sanity */
-
-	if (driver->dd_bdevsw) {
-		driver->dd_bdevsw->d_driver = NULL;
-		driver->dd_bdevsw = NULL;
-	}
-
-	if (driver->dd_cdevsw) {
-		if (driver->dd_cdevsw->d_str) {
-			str_free_mux_node(driver);
-		}
-		driver->dd_cdevsw->d_driver = NULL;
-		driver->dd_cdevsw = NULL;
-	}
-
-	kern_free(driver);
-#endif
-	FIXME("device_driver_free");
-}
-
-
-/*
-** Given a device driver prefix, return a handle to the caller.
-*/
-device_driver_t
-device_driver_get(char *prefix)
-{
-#ifdef LATER
-	int which_hash;
-	device_driver_t drvscan;
-	unsigned long s;
-
-	if (prefix == NULL)
-		return(NULL);
-		
-	which_hash = driver_prefix_hash(prefix);
-
-	s = mutex_spinlock(&device_driver_lock[which_hash]);
-
-	drvscan = device_driver_hash[which_hash];
-	while (drvscan && strcmp(drvscan->dd_prefix, prefix))
-		drvscan = drvscan->dd_next;
-
-	mutex_spinunlock(&device_driver_lock[which_hash], s);
-
-	return(drvscan);
-#else
-	FIXME("device_driver_get");
-	return((device_driver_t)0);
-#endif
-}
-
-
-/*
-** Given a block or char special file devfs_handle_t, find the 
-** device driver that controls it.
-*/
-device_driver_t
-device_driver_getbydev(devfs_handle_t device)
-{
-#ifdef LATER
-	struct bdevsw *my_bdevsw;
-	struct cdevsw *my_cdevsw;
-
-	my_cdevsw = get_cdevsw(device);
-	if (my_cdevsw != NULL)
-		return(my_cdevsw->d_driver);
-
-	my_bdevsw = get_bdevsw(device);
-	if (my_bdevsw != NULL)
-		return(my_bdevsw->d_driver);
-
-#endif
-	FIXME("device_driver_getbydev");
-	return((device_driver_t)0);
-}
-
-
-/*
-** Associate a driver with bdevsw/cdevsw pointers.
-**
-** Statically loaded drivers are permanently and automatically associated
-** with the proper bdevsw/cdevsw.  Dynamically loaded drivers associate
-** themselves when the driver is registered, and disassociate when the
-** driver unregisters.
-**
-** Returns 0 on success, -1 on failure (devsw already associated with driver)
-*/
-int
-device_driver_devsw_put(device_driver_t driver,
-			struct bdevsw *my_bdevsw,
-			struct cdevsw *my_cdevsw)
-{
-#ifdef LATER
-	int i;
-
-	if (!driver)
-		return(-1);
-
-	/* Trying to re-register data?  */
-	if (((my_bdevsw != NULL) && (driver->dd_bdevsw != NULL)) ||
-	    ((my_cdevsw != NULL) && (driver->dd_cdevsw != NULL)))
-		return(-1);
-
-	if (my_bdevsw != NULL) {
-		driver->dd_bdevsw = my_bdevsw;
-		my_bdevsw->d_driver = driver;
-		for (i = 0; i < bdevmax; i++) {
-			if (driver->dd_bdevsw->d_flags == bdevsw[i].d_flags) {
-				bdevsw[i].d_driver = driver;
-				break;
-			}
-		}
-	}
-
-	if (my_cdevsw != NULL) {
-		driver->dd_cdevsw = my_cdevsw;
-		my_cdevsw->d_driver = driver;
-		for (i = 0; i < cdevmax; i++) {
-			if (driver->dd_cdevsw->d_flags == cdevsw[i].d_flags) {
-				cdevsw[i].d_driver = driver;
-				break;
-			}
-		}
-	}
-#endif
-	FIXME("device_driver_devsw_put");
-	return(0);
-}
-
-
-/*
-** Given a driver, return the corresponding bdevsw and cdevsw pointers.
-*/
-void
-device_driver_devsw_get(	device_driver_t driver, 
-				struct bdevsw **bdevswp,
-				struct cdevsw **cdevswp)
-{
-	if (!driver) {
-		*bdevswp = NULL;
-		*cdevswp = NULL;
-	} else {
-		*bdevswp = driver->dd_bdevsw;
-		*cdevswp = driver->dd_cdevsw;
-	}
-}
-
-/*
- * device_driver_thread_pri_set
- *	Given a driver try to set its thread priority.
- *	Returns 0 on success , -1 on failure.
- */ 
-int
-device_driver_thread_pri_set(device_driver_t driver,ilvl_t pri)
-{
-	if (!driver)
-		return(-1);
-	driver->dd_thread_pri = pri;
-	return(0);
-}
-/*
- * device_driver_thread_pri_get
- * 	Given a driver return the driver thread priority.
- * 	If the driver is NULL return invalid driver thread
- * 	priority.
- */
-ilvl_t
-device_driver_thread_pri_get(device_driver_t driver)
-{
-	if (driver)
-		return(driver->dd_thread_pri);
-	else
-		return(DRIVER_THREAD_PRI_INVALID);
-}
-/*
-** Given a device driver, return it's handle (prefix).
-*/
-void
-device_driver_name_get(device_driver_t driver, char *buffer, int length)
-{
-	if (driver == NULL)
-		return;
-
-	strncpy(buffer, driver->dd_prefix, length);
-}
-
-
-/*
-** Associate a pointer-sized piece of information with a device.
-*/
-void 
-device_info_set(devfs_handle_t device, void *info)
-{
-#ifdef LATER
-	hwgraph_fastinfo_set(device, (arbitrary_info_t)info);
-#endif
-	FIXME("device_info_set");
-}
-
-
-/*
-** Retrieve a pointer-sized piece of information associated with a device.
-*/
-void *
-device_info_get(devfs_handle_t device)
-{
-#ifdef LATER
-	return((void *)hwgraph_fastinfo_get(device));
-#else
-	FIXME("device_info_get");
-	return(NULL);
-#endif
-}
-
-/*
- * Find the thread priority for a device, from the various
- * sysgen files.
- */
-int
-device_driver_sysgen_thread_pri_get(char *dev_prefix)
-{
-#ifdef LATER
-	int pri;
-	char *pri_s;
-	char *class;
-
-	extern default_intr_pri;
-	extern disk_intr_pri;
-	extern serial_intr_pri;
-	extern parallel_intr_pri;
-	extern tape_intr_pri;
-	extern graphics_intr_pri;
-	extern network_intr_pri;
-	extern scsi_intr_pri;
-	extern audio_intr_pri;
-	extern video_intr_pri;
-	extern external_intr_pri;
-	extern tserialio_intr_pri;
-
-	/* Check if there is a thread priority specified for
-	 * this driver's thread thru admin hints. If so 
-	 * use that value. Otherwise set it to its default
-	 * class value, otherwise set it to the default
-	 * value.
-	 */
-
-	if (pri_s = device_driver_admin_info_get(dev_prefix,
-						ADMIN_LBL_THREAD_PRI)) {
-		pri = atoi(pri_s);
-	} else if (class = device_driver_admin_info_get(dev_prefix,
-						ADMIN_LBL_THREAD_CLASS)) {
-		if (strcmp(class, "disk") == 0)
-			pri = disk_intr_pri;
-		else if (strcmp(class, "serial") == 0)
-			pri = serial_intr_pri;
-		else if (strcmp(class, "parallel") == 0)
-			pri = parallel_intr_pri;
-		else if (strcmp(class, "tape") == 0)
-			pri = tape_intr_pri;
-		else if (strcmp(class, "graphics") == 0)
-			pri = graphics_intr_pri;
-		else if (strcmp(class, "network") == 0)
-			pri = network_intr_pri;
-		else if (strcmp(class, "scsi") == 0)
-			pri = scsi_intr_pri;
-		else if (strcmp(class, "audio") == 0)
-			pri = audio_intr_pri;
-		else if (strcmp(class, "video") == 0)
-			pri = video_intr_pri;
-		else if (strcmp(class, "external") == 0)
-			pri = external_intr_pri;
-		else if (strcmp(class, "tserialio") == 0)
-			pri = tserialio_intr_pri;
-		else
-			pri = default_intr_pri;
-	} else
-		pri = default_intr_pri;
-
-	if (pri > 255)
-		pri = 255;
-	else if (pri < 0)
-		pri = 0;
-	return pri;
-#else
-	FIXME("device_driver_sysgen_thread_pri_get");
-	return(-1);
-#endif
-}
diff -Nru a/arch/ia64/sn/io/eeprom.c b/arch/ia64/sn/io/eeprom.c
--- a/arch/ia64/sn/io/eeprom.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/eeprom.c	Fri Mar 15 17:51:01 2002
@@ -1,14 +1,11 @@
 /*
- *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 1999-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-
 /*
  * WARNING:     There is more than one copy of this file in different isms.
  *              All copies must be kept exactly in sync.
@@ -28,37 +25,24 @@
  *
  */
 
-/**************************************************************************
- *                                                                        *
- *  Copyright (C) 1999 Silicon Graphics, Inc.                             *
- *                                                                        *
- *  These coded instructions, statements, and computer programs  contain  *
- *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
- *  are protected by Federal copyright law.  They  may  not be disclosed  *
- *  to  third  parties  or copied or duplicated in any form, in whole or  *
- *  in part, without the prior written consent of Silicon Graphics, Inc.  *
- *                                                                        *
- **************************************************************************
- */
-
-
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
-/* #include <sys/SN/SN1/ip27log.h> */
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/clksupport.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/simulator.h>
 
 #if defined(EEPROM_DEBUG)
 #define db_printf(x) printk x
@@ -421,7 +405,7 @@
     }
     else {
 	scp = &sc;
-	sc_init( &sc, nasid, BRL1_LOCALUART );
+	sc_init( &sc, nasid, BRL1_LOCALHUB_UART );
     }
 
     /* fill in msg with the opcode & params */
@@ -472,14 +456,12 @@
     if ( IS_RUNNING_ON_SIMULATOR() )
 	return EEP_L1;
 
-#ifdef BRINGUP
 #define FAIL								\
     {									\
 	*uid = rtc_time();						\
 	printk( "rbrick_uid_get failed; using current time as uid\n" );	\
 	return EEP_OK;							\
     }
-#endif /* BRINGUP */
 
     ROUTER_LOCK(path);
     sc_init( &sc, nasid, path );
@@ -593,12 +575,10 @@
 
 extern char *nic_vertex_info_get( devfs_handle_t );
 extern void nic_vmc_check( devfs_handle_t, char * );
-#ifdef BRINGUP
 /* the following were lifted from nic.c - change later? */
 #define MAX_INFO 2048
 #define NEWSZ(ptr,sz)   ((ptr) = kern_malloc((sz)))
 #define DEL(ptr) (kern_free((ptr)))
-#endif /* BRINGUP */
 
 char *eeprom_vertex_info_set( int component, int nasid, devfs_handle_t v,
                               net_vec_t path )
@@ -1068,7 +1048,7 @@
     if( (checksum & 0xff) != 0 )
     {
 	db_printf(( "read_chassis_ia: bad checksum\n" ));
-	db_printf(( "read_chassis_ia: target 0x%x  uart 0x%x\n",
+	db_printf(( "read_chassis_ia: target 0x%x  uart 0x%lx\n",
 			   sc->subch[subch].target, sc->uart ));
 	return EEP_BAD_CHECKSUM;
     }
@@ -1199,7 +1179,7 @@
     if( (checksum & 0xff) != 0 )
     {
 	db_printf(( "read_board_ia: bad checksum\n" ));
-	db_printf(( "read_board_ia: target 0x%x  uart 0x%x\n",
+	db_printf(( "read_board_ia: target 0x%x  uart 0x%lx\n",
 		    sc->subch[subch].target, sc->uart ));
 	return EEP_BAD_CHECKSUM;
     }
diff -Nru a/arch/ia64/sn/io/efi-rtc.c b/arch/ia64/sn/io/efi-rtc.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/efi-rtc.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,185 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc.
+ * Copyright (C) 2001 by Ralf Baechle
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/errno.h>
+#include <asm/efi.h>
+#include <asm/sn/klclock.h>
+
+/*
+ * No locking necessary when this is called from efirtc which protects us
+ * from racing by efi_rtc_lock.
+ */
+#define __swizzle(addr) ((u8 *)((unsigned long)(addr) ^ 3))
+#define read_io_port(addr) (*(volatile u8 *) __swizzle(addr))
+#define write_io_port(addr, data) (*(volatile u8 *) __swizzle(addr) = (data))
+
+#define TOD_SGS_M48T35		1
+#define TOD_DALLAS_DS1386	2
+
+static unsigned long nvram_base = 0;
+static int tod_chip_type;
+
+static int
+get_tod_chip_type(void)
+{
+	unsigned char testval;
+
+	write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+	write_io_port(RTC_DAL_DAY_ADDR, 0xff);
+	write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+
+	testval = read_io_port(RTC_DAL_DAY_ADDR);
+	if (testval == 0xff)
+		return TOD_SGS_M48T35;
+
+	return TOD_DALLAS_DS1386;
+}
+
+efi_status_t
+ioc3_get_time(efi_time_t *time, efi_time_cap_t *caps)
+{
+	if (!nvram_base) {
+		printk(KERN_CRIT "nvram_base is zero\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	memset(time, 0, sizeof(*time));
+
+	switch (tod_chip_type) {
+	case TOD_SGS_M48T35:
+		write_io_port(RTC_SGS_CONTROL_ADDR, RTC_SGS_READ_PROTECT);
+
+		time->year = BCD_TO_INT(read_io_port(RTC_SGS_YEAR_ADDR)) + YRREF;
+		time->month = BCD_TO_INT(read_io_port(RTC_SGS_MONTH_ADDR));
+		time->day = BCD_TO_INT(read_io_port(RTC_SGS_DATE_ADDR));
+		time->hour = BCD_TO_INT(read_io_port(RTC_SGS_HOUR_ADDR));
+		time->minute = BCD_TO_INT(read_io_port(RTC_SGS_MIN_ADDR));
+		time->second = BCD_TO_INT(read_io_port(RTC_SGS_SEC_ADDR));
+		time->nanosecond = 0;
+
+		write_io_port(RTC_SGS_CONTROL_ADDR, 0);
+		break;
+
+	case TOD_DALLAS_DS1386:
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+
+		time->nanosecond = 0;
+		time->second = BCD_TO_INT(read_io_port(RTC_DAL_SEC_ADDR));
+		time->minute = BCD_TO_INT(read_io_port(RTC_DAL_MIN_ADDR));
+		time->hour = BCD_TO_INT(read_io_port(RTC_DAL_HOUR_ADDR));
+		time->day = BCD_TO_INT(read_io_port(RTC_DAL_DATE_ADDR));
+		time->month = BCD_TO_INT(read_io_port(RTC_DAL_MONTH_ADDR));
+		time->year = BCD_TO_INT(read_io_port(RTC_DAL_YEAR_ADDR)) + YRREF;
+
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+		break;
+
+	default:
+		break;
+	}
+
+	if (caps) {
+		caps->resolution = 50000000;	/*  50PPM */
+		caps->accuracy = 1000;		/*  1ms */
+		caps->sets_to_zero = 0;
+	}
+
+	return EFI_SUCCESS;
+}
+
+static efi_status_t ioc3_set_time (efi_time_t *t)
+{
+	if (!nvram_base) {
+		printk(KERN_CRIT "nvram_base is zero\n");
+		return EFI_UNSUPPORTED;
+	}
+
+	switch (tod_chip_type) {
+	case TOD_SGS_M48T35:
+		write_io_port(RTC_SGS_CONTROL_ADDR, RTC_SGS_WRITE_ENABLE);
+        	write_io_port(RTC_SGS_YEAR_ADDR, INT_TO_BCD((t->year - YRREF)));
+		write_io_port(RTC_SGS_MONTH_ADDR,INT_TO_BCD(t->month));
+		write_io_port(RTC_SGS_DATE_ADDR, INT_TO_BCD(t->day));
+		write_io_port(RTC_SGS_HOUR_ADDR, INT_TO_BCD(t->hour));
+		write_io_port(RTC_SGS_MIN_ADDR,  INT_TO_BCD(t->minute));
+		write_io_port(RTC_SGS_SEC_ADDR,  INT_TO_BCD(t->second));
+		write_io_port(RTC_SGS_CONTROL_ADDR, 0);
+		break;
+
+	case TOD_DALLAS_DS1386:
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_DISABLE);
+		write_io_port(RTC_DAL_SEC_ADDR,  INT_TO_BCD(t->second));
+		write_io_port(RTC_DAL_MIN_ADDR,  INT_TO_BCD(t->minute));
+		write_io_port(RTC_DAL_HOUR_ADDR, INT_TO_BCD(t->hour));
+		write_io_port(RTC_DAL_DATE_ADDR, INT_TO_BCD(t->day));
+		write_io_port(RTC_DAL_MONTH_ADDR,INT_TO_BCD(t->month));
+		write_io_port(RTC_DAL_YEAR_ADDR, INT_TO_BCD((t->year - YRREF)));
+		write_io_port(RTC_DAL_CONTROL_ADDR, RTC_DAL_UPDATE_ENABLE);
+		break;
+
+	default:
+		break;
+	}
+
+	return EFI_SUCCESS;
+}
+
+/* The following two are not supported atm.  */
+static efi_status_t
+ioc3_get_wakeup_time (efi_bool_t *enabled, efi_bool_t *pending, efi_time_t *tm)
+{
+	return EFI_UNSUPPORTED;
+}
+
+static efi_status_t
+ioc3_set_wakeup_time (efi_bool_t enabled, efi_time_t *tm)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/*
+ * It looks like the master IOC3 is usually on bus 0, device 4.  Hope
+ * that's right
+ */
+static __init int efi_ioc3_time_init(void)
+{
+	struct pci_dev *dev;
+	static struct ioc3 *ioc3;
+
+	dev = pci_find_slot(0, PCI_DEVFN(4, 0));
+	if (!dev) {
+		printk(KERN_CRIT "Couldn't find master IOC3\n");
+
+		return -ENODEV;
+	}
+
+	ioc3 = ioremap(pci_resource_start(dev, 0), pci_resource_len(dev, 0));
+	nvram_base = (unsigned long) ioc3 + IOC3_BYTEBUS_DEV0;
+
+	tod_chip_type = get_tod_chip_type();
+	if (tod_chip_type == 1)
+		printk(KERN_NOTICE "TOD type is SGS M48T35\n");
+	else if (tod_chip_type == 2)
+		printk(KERN_NOTICE "TOD type is Dallas DS1386\n");
+	else
+		printk(KERN_CRIT "No or unknown TOD\n");
+
+	efi.get_time = ioc3_get_time;
+	efi.set_time = ioc3_set_time;
+	efi.get_wakeup_time = ioc3_get_wakeup_time;
+	efi.set_wakeup_time = ioc3_set_wakeup_time;
+
+	return 0;
+}
+
+module_init(efi_ioc3_time_init);
diff -Nru a/arch/ia64/sn/io/hcl.c b/arch/ia64/sn/io/hcl.c
--- a/arch/ia64/sn/io/hcl.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/hcl.c	Fri Mar 15 17:51:02 2002
@@ -6,8 +6,7 @@
  *
  *  hcl - SGI's Hardware Graph compatibility layer.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -49,7 +48,6 @@
 /*
  * Some Global definitions.
  */
-spinlock_t hcl_spinlock;
 devfs_handle_t hcl_handle = NULL;
 
 invplace_t invplace_none = {
@@ -142,6 +140,7 @@
 {
 	extern void string_table_init(struct string_table *);
 	extern struct string_table label_string_table;
+	extern int init_ifconfig_net(void);
 	int rv = 0;
 
 #if defined(CONFIG_HCL_DEBUG) && !defined(MODULE)
@@ -153,8 +152,6 @@
 	printk ("\n%s: boot_options: 0x%0x\n", HCL_NAME, boot_options);
 #endif
 
-	spin_lock_init(&hcl_spinlock);
-
 	/*
 	 * Create the hwgraph_root on devfs.
 	 */
@@ -192,6 +189,12 @@
 		return(0);
 	}
 
+	/*
+	 * Initialize the ifconfgi_net driver that does network devices 
+	 * Persistent Naming.
+	 */
+	init_ifconfig_net();
+
 	return(0);
 
 }
@@ -238,8 +241,7 @@
 {
 
 	if (hcl_debug) {
-		printk("HCL: hwgraph_fastinfo_set handle 0x%p fastinfo %ld\n",
-			de, fastinfo);
+		printk("HCL: hwgraph_fastinfo_set handle 0x%p fastinfo %ld\n", (void *)de, fastinfo);
 	}
 		
 	labelcl_info_replace_IDX(de, HWGRAPH_FASTINFO, fastinfo, NULL);
@@ -466,7 +468,7 @@
 		 * We need to clean up!
 		 */
 		printk(KERN_WARNING "HCL: Unable to set the connect point to it's parent 0x%p\n",
-			new_devfs_handle);
+			(void *)new_devfs_handle);
 	}
 
         /*
@@ -1044,30 +1046,6 @@
 }
 
 /*
- * hwgraph_cdevsw_get - returns the fops of the given devfs entry.
- */
-struct file_operations *
-hwgraph_cdevsw_get(devfs_handle_t de)
-{
-	struct file_operations *fops = devfs_get_ops(de);
-
-	devfs_put_ops(de); /*  FIXME: this may need to be moved to callers  */
-	return(fops);
-}
-
-/*
- * hwgraph_bdevsw_get - returns the fops of the given devfs entry.
-*/
-struct file_operations *    /*  FIXME: shouldn't this be a blkdev?  */
-hwgraph_bdevsw_get(devfs_handle_t de)
-{
-	struct file_operations *fops = devfs_get_ops(de);
-
-	devfs_put_ops(de); /*  FIXME: this may need to be moved to callers  */
-	return(fops);
-}
-
-/*
 ** Inventory is now associated with a vertex in the graph.  For items that
 ** belong in the inventory but have no vertex 
 ** (e.g. old non-graph-aware drivers), we create a bogus vertex under the 
@@ -1550,6 +1528,4 @@
 EXPORT_SYMBOL(hwgraph_path_to_dev);
 EXPORT_SYMBOL(hwgraph_block_device_get);
 EXPORT_SYMBOL(hwgraph_char_device_get);
-EXPORT_SYMBOL(hwgraph_cdevsw_get);
-EXPORT_SYMBOL(hwgraph_bdevsw_get);
 EXPORT_SYMBOL(hwgraph_vertex_name_get);
diff -Nru a/arch/ia64/sn/io/hcl_util.c b/arch/ia64/sn/io/hcl_util.c
--- a/arch/ia64/sn/io/hcl_util.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/hcl_util.c	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -14,6 +13,7 @@
 #include <linux/devfs_fs_kernel.h>
 #include <asm/sn/sgi.h>
 #include <asm/io.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
diff -Nru a/arch/ia64/sn/io/hubdev.c b/arch/ia64/sn/io/hubdev.c
--- a/arch/ia64/sn/io/hubdev.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/hubdev.c	Fri Mar 15 17:51:03 2002
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/sn1/hubdev.h>
 #include <asm/sn/sn_private.h>
@@ -42,7 +43,7 @@
         
         ASSERT(attach_method);
 
-        callout =  (hubdev_callout_t *)kmem_zalloc(sizeof(hubdev_callout_t), KM_SLEEP);
+        callout =  (hubdev_callout_t *)snia_kmem_zalloc(sizeof(hubdev_callout_t), KM_SLEEP);
         ASSERT(callout);
         
 	mutex_lock(&hubdev_callout_mutex);
@@ -104,6 +105,9 @@
  * Given a hub vertex, return the base address of the Hspec space
  * for that hub.
  */
+
+#if defined(CONFIG_IA64_SGI_SN1)
+
 caddr_t
 hubdev_prombase_get(devfs_handle_t hub)
 {
@@ -124,3 +128,5 @@
 
 	return hinfo->h_cnodeid;
 }
+
+#endif	/* CONFIG_IA64_SGI_SN1 */
diff -Nru a/arch/ia64/sn/io/huberror.c b/arch/ia64/sn/io/huberror.c
--- a/arch/ia64/sn/io/huberror.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,475 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Alan Mayer
- */
-
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <asm/smp.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
-#include <asm/sn/sn_private.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/synergy.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/xtalk/xtalk.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/intr.h>
-
-extern void hubni_eint_init(cnodeid_t cnode);
-extern void hubii_eint_init(cnodeid_t cnode);
-extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
-extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
-
-extern int maxcpus;
-
-#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
-
-
-void
-hub_error_clear(nasid_t nasid)
-{
-	int i;
-	hubreg_t idsr;
-	int sn;
-
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_PEND, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_A_CLR, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_B_CLR, -1);
-		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_0, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_1, 0);
-	}
-
-	REMOTE_HUB_L(nasid, MD_DIR_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_MEM_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_MISC1_ERROR_CLR);
-	REMOTE_HUB_L(nasid, MD_PROTOCOL_ERR_CLR);
-
-    /*
-     * Make sure spurious write response errors are cleared
-     * (values are from hub_set_prb())
-     */
-    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
-        iprb_t prb;
-
-	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
-
-        /* Clear out some fields */
-        prb.iprb_ovflow = 1;
-        prb.iprb_bnakctr = 0;
-        prb.iprb_anakctr = 0;
-
-	/*
-	 * PIO reads in fire-and-forget mode on bedrock 1.0 don't
-	 * frob the credit count properly, making the responses appear
-	 * spurious.  So don't use fire-and-forget mode.  Bug 761802.
-	 */
-        prb.iprb_ff = 0;        /* disable fire-and-forget mode by default */
-
-        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
-
-        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
-    }
-
-    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
-    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
-    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
-
-    REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
-    /* No need to clear NI_PORT_HEADER regs; they are continually overwritten*/
-
-    REMOTE_HUB_S(nasid, LB_ERROR_MASK_CLR, -1);
-    REMOTE_HUB_S(nasid, LB_ERROR_HDR1, 0);
-
-    /* Clear XB error regs, in order */
-    for (i = 0;
-         i <= XB_FIRST_ERROR_CLEAR - XB_POQ0_ERROR_CLEAR;
-         i += sizeof(hubreg_t)) {
-        REMOTE_HUB_S(nasid, XB_POQ0_ERROR_CLEAR + i, 0);
-    }
-}
-
-
-/*
- * Function	: hub_error_init
- * Purpose	: initialize the error handling requirements for a given hub.
- * Parameters	: cnode, the compact nodeid.
- * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
- *			remote cpu, when this hub is headless.(cpuless)
- * Returns	: None
- */
-
-void
-hub_error_init(cnodeid_t cnode)
-{
-	nasid_t nasid;
-
-    nasid = cnodeid_to_nasid(cnode);
-    hub_error_clear(nasid);
-
-#ifdef ajm
-    if (cnode == 0) {
-	/*
-	 * Allocate log for storing the node specific error info
-	 */
-	for (i = 0; i < numnodes; i++) {
-	    kl_error_log[i]  = kmem_zalloc_node(sizeof(sn0_error_log_t), 
-						KM_NOSLEEP, i);
-	    hub_err_count[i] = kmem_zalloc_node(sizeof(hub_errcnt_t),
-						VM_DIRECT | KM_NOSLEEP, i);
-	    ASSERT_ALWAYS(kl_error_log[i] && hub_err_count[i]);
-	}
-    }
-
-    /*
-     * Assumption: There will be only one cpu who will initialize
-     * a hub. we need to setup the ii and each pi error interrupts.
-     * The SN1 hub (bedrock) has two PI, one for up to two processors.
-     */
-
-    if (cpuid_to_cnodeid(smp_processor_id()) == cnode) { 
-	int generic_intr_mask = PI_ERR_GENERIC; /* These interrupts are sent to only 1 CPU per NODE */
-
-	ASSERT_ALWAYS(kl_error_log[cnode]);
-	ASSERT_ALWAYS(hub_err_count[cnode]);
-	MD_ERR_LOG_INIT(kl_error_log[cnode]);
-
-	/* One for each CPU */
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 0));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 1));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 2));
-	recover_error_init(RECOVER_ERROR_TABLE(cnode, 3));
-
-	/*
-	 * Setup error intr masks.
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		int cpuA_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_A);
-		int cpuB_present = REMOTE_HUB_PI_L(nasid, sn, PI_CPU_ENABLE_B);
-
-		if (cpuA_present) {
-			if (cpuB_present) {		/* A && B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
-					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_A|generic_intr_mask));
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
-					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_B));
-
-			} else {			/* A && !B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A,
-					(PI_FATAL_ERR_CPU_A | PI_MISC_ERR_CPU_A|generic_intr_mask));
-			}
-			generic_intr_mask = 0;
-		} else {
-			if (cpuB_present) {		/* !A && B */
-	    			REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B,
-					(PI_FATAL_ERR_CPU_B | PI_MISC_ERR_CPU_B|generic_intr_mask));
-				generic_intr_mask = 0;
-
-			} else {			/* !A && !B */
-				/* nothing to set up */
-			}
-		}
-	}
-
-	/*
-	 * Turn off UNCAC_UNCORR interrupt in the masks. Anyone interested
-	 * in these errors will peek at the int pend register to see if its
-	 * set.
-	 */ 
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_A);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, (misc & ~PI_ERR_UNCAC_UNCORR_A));
-		misc = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_INT_MASK_B);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, (misc & ~PI_ERR_UNCAC_UNCORR_B));
-	}
-
-	/*
-	 * enable all error indicators to turn on, in case of errors.
-	 *
-	 * This is not good on single cpu node boards.
-	 **** LOCAL_HUB_S(PI_SYSAD_ERRCHK_EN, PI_SYSAD_CHECK_ALL);
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_A_CLR, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS1_B_CLR, 0);
-	}
-
-	/* Set up stack for each present processor */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_A)) {
-	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[0] =
-			SN0_ERROR_LOG(cnode)->el_spool_last_addr[0] =
-		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
-		}
-	    
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
-	    	SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
-			SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
-		    	REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-		}
-	}
-
-
-	PI_SPOOL_SIZE_BYTES = 
-	    ERR_STACK_SIZE_BYTES(REMOTE_HUB_L(nasid, PI_ERR_STACK_SIZE));
-
-#ifdef BRINGUP
-/* BRINGUP: The following code looks like a check to make sure
-the prom set up the error spool correctly for 2 processors.  I
-don't think it is needed.  */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		if (REMOTE_HUB_PI_L(nasid, sn, PI_CPU_PRESENT_B)) {
-			__psunsigned_t addr_a = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_A);
-			__psunsigned_t addr_b = REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-			if ((addr_a & ~0xff) == (addr_b & ~0xff)) {
-			    REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STACK_ADDR_B, 	
-					addr_b + PI_SPOOL_SIZE_BYTES);
-	
-			    SN0_ERROR_LOG(cnode)->el_spool_cur_addr[1] =
-				SN0_ERROR_LOG(cnode)->el_spool_last_addr[1] =
-				    REMOTE_HUB_PI_L(nasid, sn, PI_ERR_STACK_ADDR_B);
-	
-		    }
-		}
-	}
-#endif /* BRINGUP */
-
-	/* programming our own hub. Enable error_int_pend intr.
-	 * If both present, CPU A takes CPU b's error interrupts and any
-	 * generic ones. CPU B takes CPU A error ints.
-	 */
-	if (cause_intr_connect (SRB_ERR_IDX,
-				(intr_func_t)(hubpi_eint_handler),
-				SR_ALL_MASK|SR_IE)) {
-	    cmn_err(ERR_WARN, 
-		    "hub_error_init: cause_intr_connect failed on %d", cnode);
-	}
-    }
-    else {
-	/* programming remote hub. The only valid reason that this
-	 * is called will be on headless hubs. No interrupts 
-	 */
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_A, 0); /* not necessary */
-		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_MASK_B, 0); /* not necessary */
-	}
-    }
-#endif /* ajm */
-    /*
-     * Now setup the hub ii and ni error interrupt handler.
-     */
-
-    hubii_eint_init(cnode);
-    hubni_eint_init(cnode);
-
-#ifdef ajm
-    /*** XXX FIXME XXX resolve the following***/
-    /* INT_PEND1 bits set up for one hub only:
-     *	SHUTDOWN_INTR
-     *	MD_COR_ERR_INTR
-     *  COR_ERR_INTR_A and COR_ERR_INTR_B should be sent to the
-     *  appropriate CPU only.
-     */
-
-    if (cnode == 0) {
-	    error_consistency_check.eps_state = 0;
-	    error_consistency_check.eps_cpuid = -1;
-	    spinlock_init(&error_consistency_check.eps_lock, "error_dump_lock");
-    }
-#endif
-
-    nodepda->huberror_ticks = HUB_ERROR_PERIOD;
-    return;
-}
-
-/*
- * Function	: hubii_eint_init
- * Parameters	: cnode
- * Purpose	: to initialize the hub iio error interrupt.
- * Assumptions	: Called once per hub, by the cpu which will ultimately
- *			handle this interrupt.
- * Returns	: None.
- */
-
-
-void
-hubii_eint_init(cnodeid_t cnode)
-{
-    int			bit, rv;
-    ii_iidsr_u_t    	hubio_eint;
-    hubinfo_t		hinfo; 
-    cpuid_t		intr_cpu;
-    devfs_handle_t 	hub_v;
-    ii_ilcsr_u_t	ilcsr;
-
-    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
-    ASSERT_ALWAYS(hub_v);
-    hubinfo_get(hub_v, &hinfo);
-
-    ASSERT(hinfo);
-    ASSERT(hinfo->h_cnodeid == cnode);
-
-    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
-
-    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
-	/* 
-	 * HUB II link is not up. 
-	 * Just disable LLP, and don't connect any interrupts.
-	 */
-	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
-	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
-	return;
-    }
-    /* Select a possible interrupt target where there is a free interrupt
-     * bit and also reserve the interrupt bit for this IO error interrupt
-     */
-    intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
-			      "HUB IO error interrupt",&bit);
-    if (intr_cpu == CPU_NONE) {
-	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
-	return;
-    }
-	
-    rv = intr_connect_level(intr_cpu, bit, 0,(intr_func_t)(NULL),
-			    (void *)(long)hub_v, NULL);
-    synergy_intr_connect(bit, intr_cpu);
-    request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, NULL, (void *)hub_v);
-    ASSERT_ALWAYS(rv >= 0);
-    hubio_eint.ii_iidsr_regval = 0;
-    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
-    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
-    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
-    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
-
-}
-
-void
-hubni_eint_init(cnodeid_t cnode)
-{
-    int intr_bit;
-    cpuid_t targ;
-
-
-    if ((targ = cnodeid_to_cpuid(cnode)) == CPU_NONE)
-	return;
-
-	/* The prom chooses which cpu gets these interrupts, but we
-	*  don't know which one it chose.  We will register all of the 
-	*  cpus to be sure.  This only costs us an irqaction per cpu.
-	*/
-    for (; targ < CPUS_PER_NODE; targ++) {
-	if (!cpu_enabled(targ) ) continue;
-	/* connect the INTEND1 bits. */
-	for (intr_bit = XB_ERROR; intr_bit <= MSC_PANIC_INTR; intr_bit++) {
-		intr_connect_level(targ, intr_bit, II_ERRORINT, NULL, NULL, NULL);
-	}
-	request_irq(SGI_HUB_ERROR_IRQ + (targ << 8), snia_error_intr_handler, 0, NULL, NULL);
-	/* synergy masks are initialized in the prom to enable all interrupts. */
-	/* We'll just leave them that way, here, for these interrupts. */
-    }
-}
-
-
-/*ARGSUSED*/
-void
-hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
-{
-    devfs_handle_t	hub_v;
-    hubinfo_t		hinfo; 
-    ii_wstat_u_t	wstat;
-    hubreg_t		idsr;
-
-	panic("Hubii interrupt\n");
-#ifdef ajm
-    /*
-     * If the NI has a problem, everyone has a problem.  We shouldn't
-     * even attempt to handle other errors when an NI error is present.
-     */
-    if (check_ni_errors()) {
-	hubni_error_handler("II interrupt", 1);
-	/* NOTREACHED */
-    }
-
-    /* two levels of casting avoids compiler warning.!! */
-    hub_v = (devfs_handle_t)(long)(arg); 
-    ASSERT(hub_v);
-
-    hubinfo_get(hub_v, &hinfo);
-    
-    /* 
-     * Identify the reason for error. 
-     */
-    wstat.ii_wstat_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_WSTAT);
-
-    if (wstat.ii_wstat_fld_s.w_crazy) {
-	char	*reason;
-	/*
-	 * We can do a couple of things here. 
-	 * Look at the fields TX_MX_RTY/XT_TAIL_TO/XT_CRD_TO to check
-	 * which of these caused the CRAZY bit to be set. 
-	 * You may be able to check if the Link is up really.
-	 */
-	if (wstat.ii_wstat_fld_s.w_tx_mx_rty)
-		reason = "Micro Packet Retry Timeout";
-	else if (wstat.ii_wstat_fld_s.w_xt_tail_to)
-		reason = "Crosstalk Tail Timeout";
-	else if (wstat.ii_wstat_fld_s.w_xt_crd_to)
-		reason = "Crosstalk Credit Timeout";
-	else {
-		hubreg_t	hubii_imem;
-		/*
-		 * Check if widget 0 has been marked as shutdown, or
-		 * if BTE 0/1 has been marked.
-		 */
-		hubii_imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
-		if (hubii_imem & IIO_IMEM_W0ESD)
-			reason = "Hub Widget 0 has been Shutdown";
-		else if (hubii_imem & IIO_IMEM_B0ESD)
-			reason = "BTE 0 has been shutdown";
-		else if (hubii_imem & IIO_IMEM_B1ESD)
-			reason = "BTE 1 has been shutdown";
-		else	reason = "Unknown";
-	
-	}
-	/*
-	 * Note: we may never be able to print this, if the II talking
-	 * to Xbow which hosts the console is dead. 
-	 */
-	printk("Hub %d to Xtalk Link failed (II_ECRAZY) Reason: %s", 
-		hinfo->h_cnodeid, reason);
-    }
-
-    /* 
-     * It's a toss as to which one among PRB/CRB to check first. 
-     * Current decision is based on the severity of the errors. 
-     * IO CRB errors tend to be more severe than PRB errors.
-     *
-     * It is possible for BTE errors to have been handled already, so we
-     * may not see any errors handled here. 
-     */
-    (void)hubiio_crb_error_handler(hub_v, hinfo);
-    (void)hubiio_prb_error_handler(hub_v, hinfo);
-    /*
-     * If we reach here, it indicates crb/prb handlers successfully
-     * handled the error. So, re-enable II to send more interrupt
-     * and return.
-     */
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, 0xffffff);
-    idsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR) & ~IIO_IIDSR_SENT_MASK;
-    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, idsr);
-#endif /* ajm */
-}
diff -Nru a/arch/ia64/sn/io/hubspc.c b/arch/ia64/sn/io/hubspc.c
--- a/arch/ia64/sn/io/hubspc.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/hubspc.c	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /*
@@ -19,6 +18,8 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <linux/devfs_fs.h>
 #include <linux/devfs_fs_kernel.h>
 #include <asm/io.h>
@@ -26,18 +27,12 @@
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-#include <asm/sn/mem_refcnt.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/sn1/mem_refcnt.h>
 #include <asm/sn/addrs.h>
-
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/ip27config.h>
-#include <asm/sn/sn1/hubdev.h>
+#include <asm/sn/snconfig.h>
+#include <asm/sn/sn1/hubspc.h>
 #include <asm/sn/ksys/elsc.h>
-#endif
-
-#include <asm/sn/hubspc.h>
+#include <asm/sn/simulator.h>
 
 
 /* Uncomment the following line for tracing */
@@ -45,10 +40,6 @@
 
 int hubspc_devflag = D_MP;
 
-extern void *device_info_get(devfs_handle_t device);
-extern void device_info_set(devfs_handle_t device, void *info);
-
-
 
 /***********************************************************************/
 /* CPU Prom Space 						       */
@@ -61,7 +52,7 @@
 }cpuprom_info_t;
 
 static cpuprom_info_t	*cpuprom_head;
-static spinlock_t	cpuprom_spinlock;
+spinlock_t	cpuprom_spinlock;
 #define	PROM_LOCK()	mutex_spinlock(&cpuprom_spinlock)
 #define	PROM_UNLOCK(s)	mutex_spinunlock(&cpuprom_spinlock, (s))
 
@@ -127,9 +118,8 @@
 	return 0;
 }
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1)
 #define	SN_PROMVERSION		INV_IP35PROM
-#endif
 
 /* Add "detailed" labelled inventory information to the
  * prom vertex 
@@ -159,7 +149,6 @@
 	cpuprom_inventory_info->im_rev = IP27CONFIG.pvers_rev;
 	cpuprom_inventory_info->im_version = IP27CONFIG.pvers_vers;
 
-
 	/* Store this info as labelled information hanging off the
 	 * prom device vertex
 	 */
@@ -172,41 +161,17 @@
 				sizeof(invent_miscinfo_t));
 }
 
-int
-cpuprom_attach(devfs_handle_t node)
-{
-        devfs_handle_t prom_dev;
-
-        hwgraph_char_device_add(node, EDGE_LBL_PROM, "hubspc_", &prom_dev);
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc: prom_attach hub: 0x%x prom: 0x%x\n", node, prom_dev);
-#endif	/* HUBSPC_DEBUG */
-	device_inventory_add(prom_dev, INV_PROM, SN_PROMVERSION,
-				(major_t)0, (minor_t)0, 0);
-
-	/* Add additional inventory info about the cpu prom like
-	 * revision & version numbers etc.
-	 */
-	cpuprom_detailed_inventory_info_add(prom_dev,node);
-        device_info_set(prom_dev, (void*)(ulong)HUBSPC_PROM);
-	prominfo_add(node, prom_dev);
-
-        return (0);
-}
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #define FPROM_CONFIG_ADDR	MD_JUNK_BUS_TIMING
 #define FPROM_ENABLE_MASK	MJT_FPROM_ENABLE_MASK
 #define FPROM_ENABLE_SHFT	MJT_FPROM_ENABLE_SHFT
 #define FPROM_SETUP_MASK	MJT_FPROM_SETUP_MASK
 #define FPROM_SETUP_SHFT	MJT_FPROM_SETUP_SHFT
-#endif
 
 /*ARGSUSED*/
 int
 cpuprom_map(devfs_handle_t dev, vhandl_t *vt, off_t addr, size_t len)
 {
-        int 		errcode;
+        int 		errcode = 0;
 	caddr_t 	kvaddr;
 	devfs_handle_t		node;
 	cnodeid_t 	cnode;
@@ -220,7 +185,7 @@
 	kvaddr = hubdev_prombase_get(node);
 	cnode  = hubdev_cnodeid_get(node);
 #ifdef	HUBSPC_DEBUG
-	printf("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr);
+	printk("cpuprom_map: hubnode %d kvaddr 0x%x\n", node, kvaddr);
 #endif
 
 	if (len > RBOOT_SIZE)
@@ -251,6 +216,7 @@
 	}
         return (errcode);
 }
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 /*ARGSUSED*/
 int
@@ -263,8 +229,6 @@
 /* Base Hub Space Driver                                               */
 /***********************************************************************/
 
-// extern int l1_attach( devfs_handle_t );
-
 /*
  * hubspc_init
  * Registration of the hubspc devices with the hub manager
@@ -277,24 +241,21 @@
          */
 
         /* The reference counters */
+#if defined(CONFIG_IA64_SGI_SN1)
         hubdev_register(mem_refcnt_attach);
-
-	/* Prom space */
-	hubdev_register(cpuprom_attach);
+#endif
 
 #if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
 	/* L1 system controller link */
 	if ( !IS_RUNNING_ON_SIMULATOR() ) {
 		/* initialize the L1 link */
-		void l1_cons_init( l1sc_t *sc );
-		elsc_t *get_elsc(void);
-
-		l1_cons_init((l1sc_t *)get_elsc());
+		extern void l1_init(void);
+		l1_init();
 	}
 #endif
 
 #ifdef	HUBSPC_DEBUG
-	printf("hubspc_init: Completed\n");
+	printk("hubspc_init: Completed\n");
 #endif	/* HUBSPC_DEBUG */
 	/* Initialize spinlocks */
 	mutex_spinlock_init(&cpuprom_spinlock);
@@ -304,26 +265,7 @@
 int
 hubspc_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(*devp)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_open(devp, oflag, otyp, crp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_open: Completed open for type %d\n",
-               (hubspc_subdevice_t)(ulong)device_info_get(*devp));
-#endif	/* HUBSPC_DEBUG */
-
-        return (errcode);
+        return (0);
 }
 
 
@@ -331,25 +273,7 @@
 int
 hubspc_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_close(dev, oflag, otyp, crp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_close: Completed close for type %d\n",
-               (hubspc_subdevice_t)(ulong)device_info_get(dev));
-#endif	/* HUBSPC_DEBUG */
-
-        return (errcode);
+        return (0);
 }
 
 /* ARGSUSED */
@@ -357,7 +281,6 @@
 hubspc_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
 {
 	/*REFERENCED*/
-        hubspc_subdevice_t subdevice;
         int errcode = 0;
 
 	/* check validity of request */
@@ -365,30 +288,6 @@
 		return ENXIO;
         }
 
-        subdevice = (hubspc_subdevice_t)(ulong)device_info_get(dev);
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_map: subdevice: %d vaddr: 0x%x phyaddr: 0x%x len: 0x%x\n",
-	       subdevice, v_getaddr(vt), off, len);
-#endif /* HUBSPC_DEBUG */
-
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_mmap(dev, vt, off, len, prot);
-                break;
-
-        case HUBSPC_PROM:
-		errcode = cpuprom_map(dev, vt, off, len);
-                break;
-        default:
-                errcode = ENODEV;
-        }
-
-#ifdef	HUBSPC_DEBUG
-	printf("hubspc_map finished: spctype: %d vaddr: 0x%x len: 0x%x\n",
-	       (hubspc_subdevice_t)(ulong)device_info_get(dev), v_getaddr(vt), len);
-#endif /* HUBSPC_DEBUG */
-
 	return errcode;
 }
 
@@ -396,21 +295,7 @@
 int
 hubspc_unmap(devfs_handle_t dev, vhandl_t *vt)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_unmap(dev, vt);
-                break;
-
-        case HUBSPC_PROM:
-                errcode = cpuprom_unmap(dev, vt);
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-	return errcode;
+	return (0);
 
 }
 
@@ -423,19 +308,6 @@
              cred_t *cred_p,
              int *rvalp)
 {
-        int errcode = 0;
-        
-        switch ((hubspc_subdevice_t)(ulong)device_info_get(dev)) {
-        case HUBSPC_REFCOUNTERS:
-                errcode = mem_refcnt_ioctl(dev, cmd, arg, mode, cred_p, rvalp);
-                break;
-
-        case HUBSPC_PROM:
-                break;
-
-        default:
-                errcode = ENODEV;
-        }
-	return errcode;
+	return (0);
 
 }
diff -Nru a/arch/ia64/sn/io/ifconfig_net.c b/arch/ia64/sn/io/ifconfig_net.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/ifconfig_net.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,298 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ *  ifconfig_net - SGI's Persistent Network Device names.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <linux/pci.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/skbuff.h>
+
+#include <asm/sn/sgi.h>
+#include <linux/devfs_fs.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/ifconfig_net.h>
+
+#define SGI_IFCONFIG_NET "SGI-PERSISTENT NETWORK DEVICE NAME DRIVER"
+#define SGI_IFCONFIG_NET_VERSION "1.0"
+
+/*
+ * Some Global definitions.
+ */
+devfs_handle_t ifconfig_net_handle = NULL;
+unsigned long ifconfig_net_debug = 0;
+
+/*
+ * ifconfig_net_open - Opens the special device node "/devhw/.ifconfig_net".
+ */
+static int ifconfig_net_open(struct inode * inode, struct file * filp)
+{
+	if (ifconfig_net_debug) {
+        	printk("ifconfig_net_open called.\n");
+	}
+
+        return(0);
+
+}
+
+/*
+ * ifconfig_net_close - Closes the special device node "/devhw/.ifconfig_net".
+ */
+static int ifconfig_net_close(struct inode * inode, struct file * filp)
+{
+
+	if (ifconfig_net_debug) {
+        	printk("ifconfig_net_close called.\n");
+	}
+
+        return(0);
+}
+
+/*
+ * assign_ifname - Assign the next available interface name from the persistent list.
+ */
+void
+assign_ifname(struct net_device *dev,
+		  struct ifname_num *ifname_num)
+
+{
+
+	/*
+	 * Handle eth devices.
+	 */
+        if ( (memcmp(dev->name, "eth", 3) == 0) ) {
+		if (ifname_num->next_eth != -1) {
+			/*
+			 * Assign it the next available eth interface number. 
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "eth%d", (int)ifname_num->next_eth);
+			ifname_num->next_eth++;
+		} 
+
+                return;
+        }
+
+	/*
+	 * Handle fddi devices.
+	 */
+	if ( (memcmp(dev->name, "fddi", 4) == 0) ) {
+		if (ifname_num->next_fddi != -1) {
+			/*
+			 * Assign it the next available fddi interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "fddi%d", (int)ifname_num->next_fddi);
+			ifname_num->next_fddi++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle hip devices.
+	 */
+	if ( (memcmp(dev->name, "hip", 3) == 0) ) {
+		if (ifname_num->next_hip != -1) {
+			/*
+			 * Assign it the next available hip interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "hip%d", (int)ifname_num->next_hip);
+			ifname_num->next_hip++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle tr devices.
+	 */
+	if ( (memcmp(dev->name, "tr", 2) == 0) ) {
+		if (ifname_num->next_tr != -1) {
+			/*
+			 * Assign it the next available tr interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "tr%d", (int)ifname_num->next_tr);
+			ifname_num->next_tr++;
+		}
+
+		return;
+	}
+
+	/*
+	 * Handle fc devices.
+	 */
+	if ( (memcmp(dev->name, "fc", 2) == 0) ) {
+		if (ifname_num->next_fc != -1) {
+			/*
+			 * Assign it the next available fc interface number.
+			 */
+			memset(dev->name, 0, strlen(dev->name));
+			sprintf(dev->name, "fc%d", (int)ifname_num->next_fc);
+			ifname_num->next_fc++;
+		}
+
+		return;
+	}
+}
+
+/*
+ * find_persistent_ifname: Returns the entry that was seen in previous boot.
+ */
+struct ifname_MAC *
+find_persistent_ifname(struct net_device *dev,
+	struct ifname_MAC *ifname_MAC)
+
+{
+
+	while (ifname_MAC->addr_len) {
+		if (memcmp(dev->dev_addr, ifname_MAC->dev_addr, dev->addr_len) == 0)
+			return(ifname_MAC);
+
+		ifname_MAC++;
+	}
+
+	return(NULL);
+}
+
+/*
+ * ifconfig_net_ioctl: ifconfig_net driver ioctl interface.
+ */
+static int ifconfig_net_ioctl(struct inode * inode, struct file * file,
+        unsigned int cmd, unsigned long arg)
+{
+
+	extern struct net_device *__dev_get_by_name(const char *);
+#ifdef CONFIG_NET
+	struct net_device *dev;
+	struct ifname_MAC *found;
+	char temp[64];
+#endif
+	struct ifname_MAC *ifname_MAC;
+	struct ifname_MAC *new_devices, *temp_new_devices;
+	struct ifname_num *ifname_num;
+	unsigned long size;
+
+
+	if (ifconfig_net_debug) {
+		printk("HCL: hcl_ioctl called.\n");
+	}
+
+	/*
+	 * Read in the header and see how big of a buffer we really need to 
+	 * allocate.
+	 */
+	ifname_num = (struct ifname_num *) kmalloc(sizeof(struct ifname_num), 
+			GFP_KERNEL);
+	copy_from_user( ifname_num, (char *) arg, sizeof(struct ifname_num));
+	size = ifname_num->size;
+	kfree(ifname_num);
+	ifname_num = (struct ifname_num *) kmalloc(size, GFP_KERNEL);
+	ifname_MAC = (struct ifname_MAC *) ((char *)ifname_num + (sizeof(struct ifname_num)) );
+
+	copy_from_user( ifname_num, (char *) arg, size);
+	new_devices =  kmalloc(size - sizeof(struct ifname_num), GFP_KERNEL);
+	temp_new_devices = new_devices;
+
+	memset(new_devices, 0, size - sizeof(struct ifname_num));
+
+#ifdef CONFIG_NET
+	/*
+	 * Go through the net device entries and make them persistent!
+	 */
+	for (dev = dev_base; dev != NULL; dev = dev->next) {
+		/*
+		 * Skip NULL entries or "lo"
+		 */
+		if ( (dev->addr_len == 0) || ( !strncmp(dev->name, "lo", strlen(dev->name))) ){
+			continue;
+		}
+
+		/*
+		 * See if we have a persistent interface name for this device.
+		 */
+		found = NULL;
+		found = find_persistent_ifname(dev, ifname_MAC);
+		if (found) {
+			strcpy(dev->name, found->name);
+		} else {
+			/* Never seen this before .. */
+			assign_ifname(dev, ifname_num);
+
+			/* 
+			 * Save the information for the next boot.
+			 */
+ 			sprintf(temp,"%s %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
+				dev->dev_addr[0],  dev->dev_addr[1],  dev->dev_addr[2],
+				dev->dev_addr[3],  dev->dev_addr[4],  dev->dev_addr[5]);
+			strcpy(temp_new_devices->name, dev->name);
+			temp_new_devices->addr_len = dev->addr_len;
+			memcpy(temp_new_devices->dev_addr, dev->dev_addr, dev->addr_len);
+			temp_new_devices++;
+		}
+		
+	}
+#endif
+
+	/*
+	 * Copy back to the User Buffer area any new devices encountered.
+	 */
+	copy_to_user((char *)arg + (sizeof(struct ifname_num)), new_devices, 
+			size - sizeof(struct ifname_num));
+
+	return(0);
+
+}
+
+struct file_operations ifconfig_net_fops = {
+	ioctl:ifconfig_net_ioctl,	/* ioctl */
+	open:ifconfig_net_open,		/* open */
+	release:ifconfig_net_close	/* release */
+};
+
+
+/*
+ * init_ifconfig_net() - Boot time initialization.  Ensure that it is called 
+ *	after devfs has been initialized.
+ *
+ */
+#ifdef MODULE
+int init_module (void)
+#else
+int __init init_ifconfig_net(void)
+#endif
+{
+	ifconfig_net_handle = NULL;
+	ifconfig_net_handle = hwgraph_register(hwgraph_root, ".ifconfig_net",
+			0, DEVFS_FL_AUTO_DEVNUM,
+			0, 0,
+			S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+			&ifconfig_net_fops, NULL);
+
+	if (ifconfig_net_handle == NULL) {
+		panic("Unable to create SGI PERSISTENT NETWORK DEVICE Name Driver.\n");
+	}
+
+	return(0);
+
+}
diff -Nru a/arch/ia64/sn/io/invent.c b/arch/ia64/sn/io/invent.c
--- a/arch/ia64/sn/io/invent.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/invent.c	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /*
diff -Nru a/arch/ia64/sn/io/io.c b/arch/ia64/sn/io/io.c
--- a/arch/ia64/sn/io/io.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/io.c	Fri Mar 15 17:51:03 2002
@@ -1,36 +1,50 @@
-/* $Id$
+/* $Id: io.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 
 #include <linux/types.h>
-#include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
 #include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/addrs.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
-#include <asm/sn/agent.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 #include <asm/sn/klconfig.h>
-#include <asm/sn/io.h>
 #include <asm/sn/sn_cpuid.h>
 
 extern xtalk_provider_t hub_provider;
+extern void hub_intr_init(devfs_handle_t hubv);
+
+
+/*      
+ * hub_device_desc_update               
+ *      Update the passed in device descriptor with the actual the
+ *      target cpu number and interrupt priority level.
+ *      NOTE : These might be the same as the ones passed in thru
+ *      the descriptor.
+ */     
+void
+hub_device_desc_update(device_desc_t    dev_desc,
+                       ilvl_t           intr_swlevel, 
+                       cpuid_t          cpu)
+{       
+}
+
 
 /*
  * Perform any initializations needed to support hub-based I/O.
@@ -63,7 +77,7 @@
 /*
  * Setup pio structures needed for a particular hub.
  */
-static void
+void
 hub_pio_init(devfs_handle_t hubv)
 {
 	xwidgetnum_t widget;
@@ -386,7 +400,7 @@
 
 
 /* ARGSUSED */
-static void
+void
 hub_dma_init(devfs_handle_t hubv)
 {
 }
@@ -411,7 +425,7 @@
 	xwidgetnum_t widget = xwidget_info_id_get(widget_info);
 	devfs_handle_t hubv = xwidget_info_master_get(widget_info);
 
-	dmamap = kern_malloc(sizeof(struct hub_dmamap_s));
+	dmamap = kmalloc(sizeof(struct hub_dmamap_s), GFP_ATOMIC);
 	dmamap->hdma_xtalk_info.xd_dev = dev;
 	dmamap->hdma_xtalk_info.xd_target = widget;
 	dmamap->hdma_hub = hubv;
@@ -454,9 +468,9 @@
 	    if (!(dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_addr re-uses dmamap.\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_addr re-uses dmamap.\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_addr re-uses dmamap.\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_addr re-uses dmamap.\n", (void *)vhdl);
 #endif
 	    }
 	} else {
@@ -487,9 +501,9 @@
 	    if (!(hub_dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = hub_dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_list re-uses dmamap\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_list re-uses dmamap\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_list re-uses dmamap\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_list re-uses dmamap\n", (void *)vhdl);
 #endif
 	    }
 	} else {
@@ -516,9 +530,9 @@
 	    if (!(hub_dmamap->hdma_flags & HUB_DMAMAP_IS_FIXED)) {
 		vhdl = hub_dmamap->hdma_xtalk_info.xd_dev;
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v: hub_dmamap_done already done with dmamap\n",vhdl);
+		printk(KERN_WARNING  "%v: hub_dmamap_done already done with dmamap\n",vhdl);
 #else
-		PRINT_WARNING("0x%x: hub_dmamap_done already done with dmamap\n", vhdl);
+		printk(KERN_WARNING  "%p: hub_dmamap_done already done with dmamap\n", (void *)vhdl);
 #endif
 	    }
 	}
@@ -581,329 +595,6 @@
 
 
 
-/* INTERRUPT MANAGEMENT */
-
-/* ARGSUSED */
-static void
-hub_intr_init(devfs_handle_t hubv)
-{
-}
-
-/*
- * hub_device_desc_update
- *	Update the passed in device descriptor with the actual the
- * 	target cpu number and interrupt priority level.
- *	NOTE : These might be the same as the ones passed in thru
- *	the descriptor.
- */
-static void
-hub_device_desc_update(device_desc_t 	dev_desc, 
-		       ilvl_t 		intr_swlevel,
-		       cpuid_t		cpu)
-{
-	char	cpuname[40];
-	
-	/* Store the interrupt priority level in the device descriptor */
-	device_desc_intr_swlevel_set(dev_desc, intr_swlevel);
-
-	/* Convert the cpuid to the vertex handle in the hwgraph and
-	 * save it in the device descriptor.
-	 */
-	sprintf(cpuname,"/hw/cpunum/%ld",cpu);
-	device_desc_intr_target_set(dev_desc, 
-				    hwgraph_path_to_dev(cpuname));
-}
-
-int allocate_my_bit = INTRCONNECT_ANYBIT;
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-static hub_intr_t
-do_hub_intr_alloc(devfs_handle_t dev,		/* which crosstalk device */
-		  device_desc_t dev_desc,	/* device descriptor */
-		  devfs_handle_t owner_dev,	/* owner of this interrupt, if known */
-		  int uncond_nothread)		/* unconditionally non-threaded */
-{
-	cpuid_t cpu = (cpuid_t)0;			/* cpu to receive interrupt */
-        int cpupicked = 0;
-	int bit;			/* interrupt vector */
-	/*REFERENCED*/
-	int intr_resflags = 0;
-	hub_intr_t intr_hdl;
-	cnodeid_t nodeid;		/* node to receive interrupt */
-	/*REFERENCED*/
-	nasid_t nasid;			/* nasid to receive interrupt */
-	struct xtalk_intr_s *xtalk_info;
-	iopaddr_t xtalk_addr;		/* xtalk addr on hub to set intr */
-	xwidget_info_t xwidget_info;	/* standard crosstalk widget info handle */
-	char *intr_name = NULL;
-	ilvl_t intr_swlevel;
-	extern int default_intr_pri;
-#ifdef CONFIG_IA64_SGI_SN1 
-	extern void synergy_intr_alloc(int, int);
-#endif
-	
-	/*
-	 * If caller didn't explicily specify a device descriptor, see if there's
-	 * a default descriptor associated with the device.
-	 */
-	if (!dev_desc) 
-		dev_desc = device_desc_default_get(dev);
-
-	if (dev_desc) {
-		intr_name = device_desc_intr_name_get(dev_desc);
-		intr_swlevel = device_desc_intr_swlevel_get(dev_desc);
-		if (dev_desc->flags & D_INTR_ISERR) {
-			intr_resflags = II_ERRORINT;
-		} else if (!uncond_nothread && !(dev_desc->flags & D_INTR_NOTHREAD)) {
-			intr_resflags = II_THREADED;
-		} else {
-			/* Neither an error nor a thread. */
-			intr_resflags = 0;
-		}
-	} else {
-		intr_swlevel = default_intr_pri;
-		if (!uncond_nothread)
-			intr_resflags = II_THREADED;
-	}
-
-	/* XXX - Need to determine if the interrupt should be threaded. */
-
-	/* If the cpu has not been picked already then choose a candidate 
-	 * interrupt target and reserve the interrupt bit 
-	 */
-#if defined(NEW_INTERRUPTS)
-	if (!cpupicked) {
-		cpu = intr_heuristic(dev,dev_desc,allocate_my_bit,
-				     intr_resflags,owner_dev,
-				     intr_name,&bit);
-	}
-#endif
-
-	/* At this point we SHOULD have a valid cpu */
-	if (cpu == CPU_NONE) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("%v hub_intr_alloc could not allocate interrupt\n",
-			owner_dev);
-#else
-		PRINT_WARNING("0x%x hub_intr_alloc could not allocate interrupt\n",
-			owner_dev);
-#endif
-		return(0);
-
-	}
-
-	/* If the cpu has been picked already (due to the bridge data 
-	 * corruption bug) then try to reserve an interrupt bit .
-	 */
-#if defined(NEW_INTERRUPTS)
-	if (cpupicked) {
-		bit = intr_reserve_level(cpu, allocate_my_bit, 
-					 intr_resflags, 
-					 owner_dev, intr_name);
-		if (bit < 0) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Could not reserve an interrupt bit for cpu "
-				" %d and dev %v\n",
-				cpu,owner_dev);
-#else
-			PRINT_WARNING("Could not reserve an interrupt bit for cpu "
-				" %d and dev 0x%x\n",
-				cpu, owner_dev);
-#endif
-				
-			return(0);
-		}
-	}
-#endif	/* NEW_INTERRUPTS */
-
-	nodeid = cpuid_to_cnodeid(cpu);
-	nasid = cpuid_to_nasid(cpu);
-	xtalk_addr = HUBREG_AS_XTALKADDR(nasid, PIREG(PI_INT_PEND_MOD, cpuid_to_subnode(cpu)));
-
-	/*
-	 * Allocate an interrupt handle, and fill it in.  There are two
-	 * pieces to an interrupt handle: the piece needed by generic
-	 * xtalk code which is used by crosstalk device drivers, and
-	 * the piece needed by low-level IP27 hardware code.
-	 */
-	intr_hdl = kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, nodeid);
-	ASSERT_ALWAYS(intr_hdl);
-
-	/* 
-	 * Fill in xtalk information for generic xtalk interfaces that
-	 * operate on xtalk_intr_hdl's.
-	 */
-	xtalk_info = &intr_hdl->i_xtalk_info;
-	xtalk_info->xi_dev = dev;
-	xtalk_info->xi_vector = bit;
-	xtalk_info->xi_addr = xtalk_addr;
-
-	/*
-	 * Regardless of which CPU we ultimately interrupt, a given crosstalk
-	 * widget always handles interrupts (and PIO and DMA) through its 
-	 * designated "master" crosstalk provider.
-	 */
-	xwidget_info = xwidget_info_get(dev);
-	if (xwidget_info)
-		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
-
-	/* Fill in low level hub information for hub_* interrupt interface */
-	intr_hdl->i_swlevel = intr_swlevel;
-	intr_hdl->i_cpuid = cpu;
-	intr_hdl->i_bit = bit;
-	intr_hdl->i_flags = HUB_INTR_IS_ALLOCED;
-
-	/* Store the actual interrupt priority level & interrupt target
-	 * cpu back in the device descriptor.
-	 */
-	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
-#ifdef CONFIG_IA64_SGI_SN1
-	synergy_intr_alloc((int)bit, (int)cpu);
-#endif
-	return(intr_hdl);
-}
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-hub_intr_t
-hub_intr_alloc(	devfs_handle_t dev,		/* which crosstalk device */
-		device_desc_t dev_desc,		/* device descriptor */
-		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
-{
-	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
-}
-
-/*
- * Allocate resources required for an interrupt as specified in dev_desc.
- * Uncondtionally request non-threaded, regardless of what the device
- * descriptor might say.
- * Returns a hub interrupt handle on success, or 0 on failure.
- */
-hub_intr_t
-hub_intr_alloc_nothd(devfs_handle_t dev,		/* which crosstalk device */
-		device_desc_t dev_desc,		/* device descriptor */
-		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
-{
-	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
-}
-
-/*
- * Free resources consumed by intr_alloc.
- */
-void
-hub_intr_free(hub_intr_t intr_hdl)
-{
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-	xtalk_intr_t xtalk_info;
-
-	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
-		/* Setting the following fields in the xtalk interrupt info
-	 	 * clears the interrupt target register in the xtalk user
-	 	 */
-		xtalk_info = &intr_hdl->i_xtalk_info;
-		xtalk_info->xi_dev = NODEV;
-		xtalk_info->xi_vector = 0;
-		xtalk_info->xi_addr = 0;
-		hub_intr_disconnect(intr_hdl);
-	}
-
-	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED)
-		kfree(intr_hdl);
-
-#if defined(NEW_INTERRUPTS)
-	intr_unreserve_level(cpu, bit);
-#endif
-}
-
-
-/*
- * Associate resources allocated with a previous hub_intr_alloc call with the
- * described handler, arg, name, etc.
- */
-/*ARGSUSED*/
-int
-hub_intr_connect(	hub_intr_t intr_hdl,		/* xtalk intr resource handle */
-			intr_func_t intr_func,		/* xtalk intr handler */
-			void *intr_arg,			/* arg to intr handler */
-			xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
-			void *setfunc_arg,		/* arg to setfunc */
-			void *thread)			/* intr thread to use */
-{
-	int rv;
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-#ifdef CONFIG_IA64_SGI_SN1
-	extern int synergy_intr_connect(int, int);
-#endif
-
-	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
-
-#if defined(NEW_INTERRUPTS)
-	rv = intr_connect_level(cpu, bit, intr_hdl->i_swlevel, 
-					intr_func, intr_arg, NULL);
-	if (rv < 0)
-		return(rv);
-
-#endif
-	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
-	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
-
-	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
-
-	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
-#ifdef CONFIG_IA64_SGI_SN1
-	return(synergy_intr_connect((int)bit, (int)cpu));
-#endif
-}
-
-
-/*
- * Disassociate handler with the specified interrupt.
- */
-void
-hub_intr_disconnect(hub_intr_t intr_hdl)
-{
-	/*REFERENCED*/
-	int rv;
-	cpuid_t cpu = intr_hdl->i_cpuid;
-	int bit = intr_hdl->i_bit;
-	xtalk_intr_setfunc_t setfunc;
-
-	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
-
-	/* TBD: send disconnected interrupts somewhere harmless */
-	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
-
-#if defined(NEW_INTERRUPTS)
-	rv = intr_disconnect_level(cpu, bit);
-	ASSERT(rv == 0);
-#endif
-
-	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
-}
-
-
-/*
- * Return a hwgraph vertex that represents the CPU currently
- * targeted by an interrupt.
- */
-devfs_handle_t
-hub_intr_cpu_get(hub_intr_t intr_hdl)
-{
-	cpuid_t cpuid = intr_hdl->i_cpuid;
-	ASSERT(cpuid != CPU_NONE);
-
-	return(cpuid_to_vertex(cpuid));
-}
-
-
-
 /* CONFIGURATION MANAGEMENT */
 
 /*
@@ -912,6 +603,9 @@
 void
 hub_provider_startup(devfs_handle_t hubv)
 {
+	extern void hub_dma_init(devfs_handle_t hubv);
+	extern void hub_pio_init(devfs_handle_t hubv);
+
 	hub_pio_init(hubv);
 	hub_dma_init(hubv);
 	hub_intr_init(hubv);
@@ -1170,58 +864,6 @@
 	return rv;
 }
 
-#if ((defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP))
-/* BRINGUP:  This ought to be useful for IP27 too but, for now,
- * make it SN1 only because `ii_ixtt_u_t' is not in IP27/hubio.h
- * (or anywhere else :-).
- */
-int
-hubii_ixtt_set(devfs_handle_t widget_vhdl, ii_ixtt_u_t *ixtt)
-{
-	xwidget_info_t		widget_info = xwidget_info_get(widget_vhdl);
-	devfs_handle_t		hub_vhdl    = xwidget_info_master_get(widget_info);
-	hubinfo_t		hub_info = 0;
-	nasid_t			nasid;
-	unsigned long			s;
-
-	/* Use the nasid from the hub info hanging off the hub vertex
-	 * and widget number from the widget vertex
-	 */
-	hubinfo_get(hub_vhdl, &hub_info);
-	/* Being over cautious by grabbing a lock */
-	s 	= mutex_spinlock(&hub_info->h_bwlock);
-	nasid 	= hub_info->h_nasid;
-
-	REMOTE_HUB_S(nasid, IIO_IXTT, ixtt->ii_ixtt_regval);
-
-	mutex_spinunlock(&hub_info->h_bwlock, s);
-	return 0;
-}
-
-int
-hubii_ixtt_get(devfs_handle_t widget_vhdl, ii_ixtt_u_t *ixtt)
-{
-	xwidget_info_t		widget_info = xwidget_info_get(widget_vhdl);
-	devfs_handle_t		hub_vhdl    = xwidget_info_master_get(widget_info);
-	hubinfo_t		hub_info = 0;
-	nasid_t			nasid;
-	unsigned long		s;
-
-	/* Use the nasid from the hub info hanging off the hub vertex
-	 * and widget number from the widget vertex
-	 */
-	hubinfo_get(hub_vhdl, &hub_info);
-	/* Being over cautious by grabbing a lock */
-	s 	= mutex_spinlock(&hub_info->h_bwlock);
-	nasid 	= hub_info->h_nasid;
-
-	ixtt->ii_ixtt_regval = REMOTE_HUB_L(nasid, IIO_IXTT);
-
-	mutex_spinunlock(&hub_info->h_bwlock, s);
-	return 0;
-}
-#endif /* CONFIG_IA64_SGI_SN1 */
-
 /*
  * hub_device_inquiry
  *	Find out the xtalk widget related information stored in this 
@@ -1259,7 +901,7 @@
 #if defined(SUPPORT_PRINTING_V_FORMAT)
 	printk("Inquiry Info for %v\n", xconn);
 #else
-	printk("Inquiry Info for 0x%x\n", xconn);
+	printk("Inquiry Info for %p\n", (void *)xconn);
 #endif
 
 	printk("\tDevices shutdown [ ");
diff -Nru a/arch/ia64/sn/io/ip37.c b/arch/ia64/sn/io/ip37.c
--- a/arch/ia64/sn/io/ip37.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,121 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-/*
- * ip37.c
- *	Support for IP35/IP37 machines
- */
-
-#include <linux/types.h>
-#include <linux/config.h>
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sgi.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/sn1/hubdev.h>
-#include <asm/sn/pci/bridge.h>     /* for bridge_t */
-
-
-xwidgetnum_t
-hub_widget_id(nasid_t nasid)
-{
-	hubii_wcr_t	ii_wcr;	/* the control status register */
-		
-	ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
-
-	return ii_wcr.wcr_fields_s.wcr_widget_id;
-}
-
-/*
- * get_nasid() returns the physical node id number of the caller.
- */
-nasid_t
-get_nasid(void)
-{
-	return (nasid_t)((LOCAL_HUB_L(LB_REV_ID) & LRI_NODEID_MASK) >> LRI_NODEID_SHFT);
-}
-
-int
-get_slice(void)
-{
-	return LOCAL_HUB_L(PI_CPU_NUM);
-}
-
-int
-is_fine_dirmode(void)
-{
-	return (((LOCAL_HUB_L(LB_REV_ID) & LRI_SYSTEM_SIZE_MASK)
-		>> LRI_SYSTEM_SIZE_SHFT) == SYSTEM_SIZE_SMALL);
-
-}
-
-hubreg_t
-get_hub_chiprev(nasid_t nasid)
-{
-
-	return ((REMOTE_HUB_L(nasid, LB_REV_ID) & LRI_REV_MASK)
-		                                         >> LRI_REV_SHFT);
-}
-
-int
-verify_snchip_rev(void)
-{
-	int hub_chip_rev;
-	int i;
-	static int min_hub_rev = 0;
-	nasid_t nasid;
-	static int first_time = 1;
-	extern int maxnodes;
-
-        
-	if (first_time) {
-	    for (i = 0; i < maxnodes; i++) {	
-		nasid = COMPACT_TO_NASID_NODEID(i);
-		hub_chip_rev = get_hub_chiprev(nasid);
-
-		if ((hub_chip_rev < min_hub_rev) || (i == 0))
-		    min_hub_rev = hub_chip_rev;
-	    }
-
-	
-	    first_time = 0;
-	}
-
-	return min_hub_rev;
-	
-}
-
-#ifdef SN1_USE_POISON_BITS
-int
-hub_bte_poison_ok(void)
-{
-	/*
-	 * For now, assume poisoning is ok. If it turns out there are chip
-	 * bugs that prevent its use in early revs, there is some neat code
-	 * to steal from the IP27 equivalent of this code.
-	 */
-
-#ifdef BRINGUP	/* temp disable BTE poisoning - might be sw bugs in this area */
-	return 0;
-#else
-	return 1;
-#endif
-}
-#endif /* SN1_USE_POISON_BITS */
-                
-
-void
-ni_reset_port(void)
-{
-	LOCAL_HUB_S(NI_RESET_ENABLE, NRE_RESETOK);
-	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
-}
-
-#endif	/* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
diff -Nru a/arch/ia64/sn/io/klconflib.c b/arch/ia64/sn/io/klconflib.c
--- a/arch/ia64/sn/io/klconflib.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/klconflib.c	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -13,12 +12,13 @@
 #include <linux/config.h>
 #include <linux/ctype.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-
-#include <asm/sn/agent.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/module.h>
@@ -40,6 +40,8 @@
 
 static void sort_nic_names(lboard_t *) ;
 
+u64 klgraph_addr[MAX_COMPACT_NODES];
+
 lboard_t *
 find_lboard(lboard_t *start, unsigned char brd_type)
 {
@@ -213,14 +215,13 @@
 {
 	lboard_t	*board;
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-/* BRINGUP: If this works then look for callers of is_master_baseio()
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+/* If this works then look for callers of is_master_baseio()
  * (e.g. iograph.c) and let them pass in a slot if they want
  */
 	board = find_lboard_module((lboard_t *)KL_CONFIG_INFO(nasid), module);
 #else
-	board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid),
-				    module, slot);
+	board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid), module, slot);
 #endif
 
 #ifndef _STANDALONE
@@ -228,7 +229,7 @@
 		cnodeid_t cnode = NASID_TO_COMPACT_NODEID(nasid);
 
 		if (!board && (NODEPDA(cnode)->xbow_peer != INVALID_NASID))
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 			board = find_lboard_module((lboard_t *)
 				    KL_CONFIG_INFO(NODEPDA(cnode)->xbow_peer),
 				    module);
@@ -300,16 +301,6 @@
 	return(brd);
 }
 
-int
-get_cpu_slice(cpuid_t cpu)
-{
-	klcpu_t *acpu;
-	if ((acpu = get_cpuinfo(cpu)) == NULL)
-	    return -1;
-	return acpu->cpu_info.physid;
-}
-
-
 /*
  * get_actual_nasid
  *
@@ -366,10 +357,6 @@
 {
 	moduleid_t modnum;
 	char *board_name;
-#if !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-	slotid_t slot;
-	char slot_name[SLOTNUM_MAXLENGTH];
-#endif
 
 	ASSERT(brd);
 
@@ -431,7 +418,7 @@
 {
 	lboard_t *brd;
 
-	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27);
+	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 
 	if (!brd)
 		return INVALID_MODULE;
@@ -569,8 +556,8 @@
 		if (component_serial_number_get(board,
 						hub->hub_mfg_nic,
 						serial_number,
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-						"IP35"))
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+						"IP37"))
 #else
 						"IP27"))
 			/* Try with IP31 key if IP27 key fails */
@@ -578,7 +565,7 @@
 							hub->hub_mfg_nic,
 							serial_number,
 							"IP31"))
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 				return(1);
 		break;
 	}
@@ -875,10 +862,11 @@
 }
 
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 
 char brick_types[MAX_BRICK_TYPES + 1] = "crikxdp789012345";
 
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+
 /*
  * Format a module id for printing.
  */
@@ -1009,7 +997,7 @@
 	return (int)(unsigned short)m;
 }
 
-#else /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#else /* CONFIG_IA64_SGI_SN1 */
 
 /*
  * Format a module id for printing.
@@ -1038,8 +1026,8 @@
     if (strstr(buffer, EDGE_LBL_MODULE "/") == buffer)
 	buffer += strlen(EDGE_LBL_MODULE "/");
 
-    m = 0;
-    while(c = *buffer++) {
+    for (m = 0; *buffer; buffer++) {
+	c = *buffer;
 	if (!isdigit(c))
 	    return -1;
 	m = 10 * m + (c - '0');
@@ -1049,6 +1037,6 @@
     return (int)(unsigned short)m;
 }
 
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
 
diff -Nru a/arch/ia64/sn/io/klgraph.c b/arch/ia64/sn/io/klgraph.c
--- a/arch/ia64/sn/io/klgraph.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/klgraph.c	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 /*
@@ -18,12 +17,12 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-
-#include <asm/sn/agent.h>
 #include <asm/sn/kldir.h>
 #include <asm/sn/gda.h> 
 #include <asm/sn/klconfig.h>
@@ -43,8 +42,7 @@
 #include <asm/sn/sn_private.h>
 
 extern char arg_maxnodes[];
-extern int maxnodes;
-
+extern u64 klgraph_addr[];
 
 /*
  * Support for verbose inventory via hardware graph. 
@@ -139,193 +137,63 @@
 void
 klhwg_add_hub(devfs_handle_t node_vertex, klhub_t *hub, cnodeid_t cnode)
 {
+#if defined(CONFIG_IA64_SGI_SN1)
 	devfs_handle_t myhubv;
+	devfs_handle_t hub_mon;
+	devfs_handle_t synergy;
+	devfs_handle_t fsb0;
+	devfs_handle_t fsb1;
 	int rc;
+	extern struct file_operations hub_mon_fops;
 
 	GRPRINTF(("klhwg_add_hub: adding %s\n", EDGE_LBL_HUB));
 
 	(void) hwgraph_path_add(node_vertex, EDGE_LBL_HUB, &myhubv);
 	rc = device_master_set(myhubv, node_vertex);
 
-#ifdef	LATER
 	/*
-	 * Activate when we support hub stats.
+	 * hub perf stats.
 	 */
 	rc = hwgraph_info_add_LBL(myhubv, INFO_LBL_HUB_INFO,
                         (arbitrary_info_t)(&NODEPDA(cnode)->hubstats));
-#endif
 
 	if (rc != GRAPH_SUCCESS) {
-		PRINT_WARNING("klhwg_add_hub: Can't add hub info label 0x%p, code %d",
-			myhubv, rc);
+		printk(KERN_WARNING  "klhwg_add_hub: Can't add hub info label 0x%p, code %d",
+			(void *)myhubv, rc);
 	}
 
 	klhwg_hub_invent_info(myhubv, cnode, hub);
 
-#ifndef BRINGUP
+	hub_mon = hwgraph_register(myhubv, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &hub_mon_fops,
+	    (void *)(long)cnode);
+
 	init_hub_stats(cnode, NODEPDA(cnode));
-	sndrv_attach(myhubv);
-#else
+
 	/*
-	 * Need to call our driver to do the attach?
+	 * synergy perf
 	 */
-	FIXME("klhwg_add_hub: Need to add code to do the attach.\n");
-#endif
+	(void) hwgraph_path_add(myhubv, EDGE_LBL_SYNERGY, &synergy);
+	(void) hwgraph_path_add(synergy, "0", &fsb0);
+	(void) hwgraph_path_add(synergy, "1", &fsb1);
+
+	fsb0 = hwgraph_register(fsb0, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &synergy_mon_fops, (void *)SYNERGY_PERF_INFO(cnode, 0));
+
+	fsb1 = hwgraph_register(fsb1, EDGE_LBL_PERFMON,
+	    0, DEVFS_FL_AUTO_DEVNUM,
+	    0, 0,
+	    S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+	    &synergy_mon_fops, (void *)SYNERGY_PERF_INFO(cnode, 1));
+#endif /* CONFIG_IA64_SGI_SN1 */
 }
 
-#ifndef BRINGUP
-
-void
-klhwg_add_rps(devfs_handle_t node_vertex, cnodeid_t cnode, int flag)
-{
-	devfs_handle_t myrpsv;
-	invent_rpsinfo_t *rps_invent;
-	int rc;
-
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-	
-	GRPRINTF(("klhwg_add_rps: adding %s to vertex 0x%x\n", EDGE_LBL_RPS,
-		node_vertex));
-
-	rc = hwgraph_path_add(node_vertex, EDGE_LBL_RPS, &myrpsv);
-	if (rc != GRAPH_SUCCESS)
-		return;
-
-	device_master_set(myrpsv, node_vertex);
-
-        rps_invent = (invent_rpsinfo_t *)
-            klhwg_invent_alloc(cnode, INV_RPS, sizeof(invent_rpsinfo_t));
-
-        if (!rps_invent)
-            return;
-
-	rps_invent->ir_xbox = 0;	/* not an xbox RPS */
-
-        if (flag)
-            rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-        else
-            rps_invent->ir_gen.ig_flag = 0x0;                                  
-
-        hwgraph_info_add_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                             (arbitrary_info_t) rps_invent);
-        hwgraph_info_export_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                                sizeof(invent_rpsinfo_t));                     
-	
-}
-
-/*
- * klhwg_update_rps gets invoked when the system controller sends an 
- * interrupt indicating the power supply has lost/regained the redundancy.
- * It's responsible for updating the Hardware graph information.
- *	rps_state = 0 -> if the rps lost the redundancy
- *		  = 1 -> If it is redundant. 
- */
-void 
-klhwg_update_rps(cnodeid_t cnode, int rps_state)
-{
-        devfs_handle_t node_vertex;
-        devfs_handle_t rpsv;
-        invent_rpsinfo_t *rps_invent;                                          
-        int rc;
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-
-        node_vertex = cnodeid_to_vertex(cnode);                                
-	rc = hwgraph_edge_get(node_vertex, EDGE_LBL_RPS, &rpsv);
-        if (rc != GRAPH_SUCCESS)  {
-		return;
-	}
-
-	rc = hwgraph_info_get_LBL(rpsv, INFO_LBL_DETAIL_INVENT, 
-				  (arbitrary_info_t *)&rps_invent);
-        if (rc != GRAPH_SUCCESS)  {
-                return;
-        }                                                                      
-
-	if (rps_state == 0 ) 
-		rps_invent->ir_gen.ig_flag = 0;
-	else 
-		rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-}
-
-void
-klhwg_add_xbox_rps(devfs_handle_t node_vertex, cnodeid_t cnode, int flag)
-{
-	devfs_handle_t myrpsv;
-	invent_rpsinfo_t *rps_invent;
-	int rc;
-
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-	
-	GRPRINTF(("klhwg_add_rps: adding %s to vertex 0x%x\n", 
-		  EDGE_LBL_XBOX_RPS, node_vertex));
-
-	rc = hwgraph_path_add(node_vertex, EDGE_LBL_XBOX_RPS, &myrpsv);
-	if (rc != GRAPH_SUCCESS)
-		return;
-
-	device_master_set(myrpsv, node_vertex);
-
-        rps_invent = (invent_rpsinfo_t *)
-            klhwg_invent_alloc(cnode, INV_RPS, sizeof(invent_rpsinfo_t));
-
-        if (!rps_invent)
-            return;
-
-	rps_invent->ir_xbox = 1;	/* xbox RPS */
-
-        if (flag)
-            rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-        else
-            rps_invent->ir_gen.ig_flag = 0x0;                                  
-
-        hwgraph_info_add_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                             (arbitrary_info_t) rps_invent);
-        hwgraph_info_export_LBL(myrpsv, INFO_LBL_DETAIL_INVENT,
-                                sizeof(invent_rpsinfo_t));                     
-	
-}
-
-/*
- * klhwg_update_xbox_rps gets invoked when the xbox system controller
- * polls the status register and discovers that the power supply has 
- * lost/regained the redundancy.
- * It's responsible for updating the Hardware graph information.
- *	rps_state = 0 -> if the rps lost the redundancy
- *		  = 1 -> If it is redundant. 
- */
-void 
-klhwg_update_xbox_rps(cnodeid_t cnode, int rps_state)
-{
-        devfs_handle_t node_vertex;
-        devfs_handle_t rpsv;
-        invent_rpsinfo_t *rps_invent;                                          
-        int rc;
-        if(cnode == CNODEID_NONE)
-                return;                                                        
-
-        node_vertex = cnodeid_to_vertex(cnode);                                
-	rc = hwgraph_edge_get(node_vertex, EDGE_LBL_XBOX_RPS, &rpsv);
-        if (rc != GRAPH_SUCCESS)  {
-		return;
-	}
-
-	rc = hwgraph_info_get_LBL(rpsv, INFO_LBL_DETAIL_INVENT, 
-				  (arbitrary_info_t *)&rps_invent);
-        if (rc != GRAPH_SUCCESS)  {
-                return;
-        }                                                                      
-
-	if (rps_state == 0 ) 
-		rps_invent->ir_gen.ig_flag = 0;
-	else 
-		rps_invent->ir_gen.ig_flag = INVENT_ENABLED;
-}
-
-#endif /* BRINGUP */
-
 void
 klhwg_add_xbow(cnodeid_t cnode, nasid_t nasid)
 {
@@ -338,11 +206,8 @@
 	/*REFERENCED*/
 	graph_error_t err;
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || defined(CONFIG_IA64_GENERIC)
-	if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
-				KLTYPE_IOBRICK_XBOW)) == NULL)
+	if ((brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IOBRICK_XBOW)) == NULL)
 			return;
-#endif
 
 	if (KL_CONFIG_DUPLICATE_BOARD(brd))
 	    return;
@@ -372,7 +237,7 @@
 
 		hub_nasid = XBOW_PORT_NASID(xbow_p, widgetnum);
 		if (hub_nasid == INVALID_NASID) {
-			PRINT_WARNING("hub widget %d, skipping xbow graph\n", widgetnum);
+			printk(KERN_WARNING  "hub widget %d, skipping xbow graph\n", widgetnum);
 			continue;
 		}
 
@@ -387,13 +252,13 @@
 		err = hwgraph_path_add(hubv, EDGE_LBL_XTALK, &xbow_v);
                 if (err != GRAPH_SUCCESS) {
                         if (err == GRAPH_DUP)
-                                PRINT_WARNING("klhwg_add_xbow: Check for "
+                                printk(KERN_WARNING  "klhwg_add_xbow: Check for "
                                         "working routers and router links!");
 
                         PRINT_PANIC("klhwg_add_xbow: Failed to add "
-                                "edge: vertex 0x%p (0x%p) to vertex 0x%p (0x%p),"
+                                "edge: vertex 0x%p to vertex 0x%p,"
                                 "error %d\n",
-                                hubv, hubv, xbow_v, xbow_v, err);
+                                (void *)hubv, (void *)xbow_v, err);
                 }
 		xswitch_vertex_init(xbow_v); 
 
@@ -416,7 +281,7 @@
 		err = hwgraph_edge_add(hubv, xbow_v, EDGE_LBL_XTALK);
 		if (err != GRAPH_SUCCESS) {
 			if (err == GRAPH_DUP)
-				PRINT_WARNING("klhwg_add_xbow: Check for "
+				printk(KERN_WARNING  "klhwg_add_xbow: Check for "
 					"working routers and router links!");
 
 			PRINT_PANIC("klhwg_add_xbow: Failed to add "
@@ -443,7 +308,7 @@
 	int board_disabled = 0;
 
 	nasid = COMPACT_TO_NASID_NODEID(cnode);
-	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_IP27);
+	brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 	GRPRINTF(("klhwg_add_node: Adding cnode %d, nasid %d, brd 0x%p\n",
                 cnode, nasid, brd));
 	ASSERT(brd);
@@ -495,7 +360,7 @@
 		
 		brd = KLCF_NEXT(brd);
 		if (brd)
-			brd = find_lboard(brd, KLTYPE_IP27);
+			brd = find_lboard(brd, KLTYPE_SNIA);
 		else
 			break;
 	} while(brd);
@@ -513,7 +378,7 @@
 	char path_buffer[100];
 	int rv;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_add_all_routers: adding router on cnode %d\n",
@@ -594,7 +459,7 @@
 			return;
 
 	if (rc != GRAPH_SUCCESS)
-		PRINT_WARNING("Can't find router: %s", path_buffer);
+		printk(KERN_WARNING  "Can't find router: %s", path_buffer);
 
 	/* We don't know what to do with multiple router components */
 	if (brd->brd_numcompts != 1) {
@@ -650,7 +515,7 @@
 
 		if (rc != GRAPH_SUCCESS && !is_specified(arg_maxnodes))
 			PRINT_PANIC("Can't create edge: %s/%s to vertex 0x%p error 0x%x\n",
-				path_buffer, dest_path, dest_hndl, rc);
+				path_buffer, dest_path, (void *)dest_hndl, rc);
 		
 	}
 }
@@ -663,7 +528,7 @@
 	cnodeid_t cnode;
 	lboard_t *brd;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_connect_routers: Connecting routers on cnode %d\n",
@@ -703,14 +568,13 @@
 	char dest_path[50];
 	graph_error_t rc;
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		nasid = COMPACT_TO_NASID_NODEID(cnode);
 
 		GRPRINTF(("klhwg_connect_hubs: Connecting hubs on cnode %d\n",
 			cnode));
 
-		brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid),
-				KLTYPE_IP27);
+		brd = find_lboard((lboard_t *)KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 		ASSERT(brd);
 
 		hub = (klhub_t *)find_first_component(brd, KLSTRUCT_HUB);
@@ -732,7 +596,7 @@
 		rc = hwgraph_traverse(hwgraph_root, path_buffer, &hub_hndl);
 
 		if (rc != GRAPH_SUCCESS)
-			PRINT_WARNING("Can't find hub: %s", path_buffer);
+			printk(KERN_WARNING  "Can't find hub: %s", path_buffer);
 
 		dest_brd = (lboard_t *)NODE_OFFSET_TO_K0(
 				hub->hub_port.port_nasid,
@@ -757,7 +621,7 @@
 
 			if (rc != GRAPH_SUCCESS)
 				PRINT_PANIC("Can't create edge: %s/%s to vertex 0x%p, error 0x%x\n",
-				path_buffer, dest_path, dest_hndl, rc);
+				path_buffer, dest_path, (void *)dest_hndl, rc);
 
 		}
 	}
diff -Nru a/arch/ia64/sn/io/klgraph_hack.c b/arch/ia64/sn/io/klgraph_hack.c
--- a/arch/ia64/sn/io/klgraph_hack.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/klgraph_hack.c	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -18,6 +17,7 @@
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/klconfig.h>
 
 void * real_port;
@@ -28,11 +28,11 @@
 
 kl_config_hdr_t *linux_klcfg;
 
-#ifdef BRINGUP
+#ifdef DEFINE_DUMP_RTNS
 /* forward declarations */
-extern void dump_ii(void), dump_lb(void), dump_crossbow(void);
-extern void clear_ii_error(void);
-#endif /* BRINGUP */
+static void dump_ii(void), dump_crossbow(void);
+static void clear_ii_error(void);
+#endif /* DEFINE_DUMP_RTNS */
 
 #define SYNERGY_WIDGET          ((char *)0xc0000e0000000000)
 #define SYNERGY_SWIZZLE         ((char *)0xc0000e0000000400)
@@ -45,115 +45,10 @@
 #define HUBREG                  ((char *)0xc0000a0001e00000)
 #define WIDGET0                 ((char *)0xc0000a0000000000)
 
-int test = 0;
-
-/*
- * Hack to loop for test.
- */
-void
-test_io_regs(void)
-{
-
-	uint32_t reg_32bits;
-	uint64_t reg_64bits;
-
-	while (test) {
-
-		reg_32bits = (uint32_t)(*(volatile uint32_t *) SYNERGY_WIDGET);
-		reg_64bits = (uint64_t) (*(volatile uint64_t *) SYNERGY_WIDGET);
-
-	}
-
-        printk("Synergy Widget Address = 0x%p, Value = 0x%lx\n", SYNERGY_WIDGET, (uint64_t)*(SYNERGY_WIDGET));
-
-        printk("Synergy swizzle Address = 0x%p, Value = 0x%lx\n", SYNERGY_SWIZZLE, (uint64_t)*(SYNERGY_SWIZZLE));
-        printk("HUBREG  Address = 0x%p, Value = 0x%lx\n",  HUBREG, (uint64_t)*(HUBREG));
-        printk("WIDGET0 Address = 0x%p, Value = 0x%lx\n", WIDGET0, (uint64_t)*(WIDGET0));
-        printk("WIDGET4 Address = 0x%p, Value = 0x%x\n", WIDGET4, (uint32_t)*(WIDGET4));
-
-}
-
 void
 klgraph_hack_init(void)
 {
 
-	kl_config_hdr_t *kl_hdr_ptr;
-	lboard_t	*lb_ptr;
-	lboard_t	*temp_ptr;
-	klhub_t		*klhub_ptr;
-	klioc3_t	*klioc3_ptr;
-	klbri_t		*klbri_ptr;
-	klxbow_t	*klxbow_ptr;
-	klinfo_t	*klinfo_ptr;
-	klcomp_t	*klcomp_ptr;
-#if 0
-	uint64_t	*tmp;
-	volatile u32	*tmp32;
-
-	/* Preset some values */
-	/* Write IOERR clear to clear the CRAZY bit in the status */
-	tmp = (uint64_t *)0xc0000a0001c001f8; *tmp = (uint64_t)0xffffffff;
-	/* set widget control register...setting bedrock widget id to b */
-	/* tmp = (uint64_t *)0xc0000a0001c00020; *tmp = (uint64_t)0x801b; */
-	/* set io outbound widget access...allow all */
-	tmp = (uint64_t *)0xc0000a0001c00110; *tmp = (uint64_t)0xff01;
-	/* set io inbound widget access...allow all */
-	tmp = (uint64_t *)0xc0000a0001c00118; *tmp = (uint64_t)0xff01;
-	/* set io crb timeout to max */
-	tmp = (uint64_t *)0xc0000a0001c003c0; *tmp = (uint64_t)0xffffff;
-	tmp = (uint64_t *)0xc0000a0001c003c0; *tmp = (uint64_t)0xffffff;
-	
-	/* set local block io permission...allow all */
-	tmp = (uint64_t *)0xc0000a0001e04010; *tmp = (uint64_t)0xfffffffffffffff;
-
-	/* clear any errors */
-	clear_ii_error();
-
-	/* set default read response buffers in bridge */
-	tmp32 = (volatile u32 *)0xc0000a000f000280L;
-	*tmp32 = 0xba98;
-	tmp32 = (volatile u32 *)0xc0000a000f000288L;
-	*tmp32 = 0xba98;
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001e00000, *( (volatile uint64_t *)0xc0000a0001e00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001c00000, *( (volatile uint64_t *)0xc0000a0001c00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc000020001e00000, *( (volatile uint64_t *)0xc000020001e00000) );
-
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc000020001c00000, *( (volatile uint64_t *)0xc000020001c00000) );
-
-printk("Widget ID Address 0x%p Value 0x%lx\n", (uint64_t *)0xc0000a0001e00000, *( (volatile uint64_t *)0xc0000a0001e00000) );
-
-printk("Xbow ID Address 0x%p Value 0x%x\n", (uint64_t *)0xc0000a0000000000, *( (volatile uint32_t *)0xc0000a0000000000) );
-
-printk("Xbow ID Address 0x%p Value 0x%x\n", (uint64_t *)0xc000020000000004, *( (volatile uint32_t *)0xc000020000000004) );
-
-#endif
-
-	if ( test )
-		test_io_regs();
-	/*
-	 * Klconfig header.
-	 */
-	kl_hdr_ptr = kmalloc(sizeof(kl_config_hdr_t), GFP_KERNEL);
-        kl_hdr_ptr->ch_magic = 0xbeedbabe;
-        kl_hdr_ptr->ch_version = 0x0;
-        kl_hdr_ptr->ch_malloc_hdr_off = 0x48;
-        kl_hdr_ptr->ch_cons_off = 0x18;
-        kl_hdr_ptr->ch_board_info = 0x0;
-        kl_hdr_ptr->ch_cons_info.uart_base = 0x920000000f820178;
-        kl_hdr_ptr->ch_cons_info.config_base = 0x920000000f024000;
-        kl_hdr_ptr->ch_cons_info.memory_base = 0x920000000f800000;
-        kl_hdr_ptr->ch_cons_info.baud = 0x2580;
-        kl_hdr_ptr->ch_cons_info.flag = 0x1;
-        kl_hdr_ptr->ch_cons_info.type = 0x300fafa;
-        kl_hdr_ptr->ch_cons_info.nasid = 0x0;
-        kl_hdr_ptr->ch_cons_info.wid = 0xf;
-        kl_hdr_ptr->ch_cons_info.npci = 0x4;
-        kl_hdr_ptr->ch_cons_info.baseio_nic = 0x0;
-
 	/*
 	 * We need to know whether we are booting from PROM or 
 	 * boot from disk.
@@ -162,520 +57,44 @@
 	if (linux_klcfg->ch_magic == 0xbeedbabe) {
 		return;
 	} else {
-		linux_klcfg = kl_hdr_ptr;
+		panic("klgraph_hack_init: Unable to locate KLCONFIG TABLE\n");
 	}
 
-	/*
-	 * lboard KLTYPE_IP35
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	kl_hdr_ptr->ch_board_info = (klconf_off_t) lb_ptr;
-	temp_ptr = lb_ptr;
-	printk("First Lboard = %p\n", temp_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x11;
-        lb_ptr->brd_sversion = 0x3;
-        lb_ptr->brd_brevision = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_slot = 0x0;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x0;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x5;
-        lb_ptr->brd_nic = 0x2a0aed35;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = 0x0;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0x26;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-	/*
-	 * Hub Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klhub_ptr = (klhub_t *)klcomp_ptr;
-	klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-	printk("hub info = %p lboard = %p\n", klhub_ptr, lb_ptr);
-
-	klinfo_ptr = (klinfo_t *)klhub_ptr;
-        klinfo_ptr->struct_type = 0x2;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0x2a0aed35;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-        klhub_ptr->hub_flags = 0x0;
-        klhub_ptr->hub_port.port_nasid = (nasid_t)0x0ffffffff;
-        klhub_ptr->hub_port.port_flag = 0x0;
-        klhub_ptr->hub_port.port_offset = 0x0;
-        klhub_ptr->hub_box_nic = 0x0;
-        klhub_ptr->hub_mfg_nic = 0x3f420;
-        klhub_ptr->hub_speed = 0xbebc200;
-
-	/*
-	 * Memory Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[1] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x3;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0xff;
-        klinfo_ptr->virtid = 0xffffffff;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_HUB_UART Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[2] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x11;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_CPU Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[3] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x1;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x0;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_CPU Component
-	 */
-	klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-	lb_ptr->brd_compts[4] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x1;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x1;
-        klinfo_ptr->virtid = 0x1;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-	lb_ptr->brd_compts[5] = 0; /* Set the next one to 0 .. end */
-	lb_ptr->brd_numcompts = 5; /* 0 to 4 */
-
-	/*
-	 * lboard(0x42) KLTYPE_PBRICK_XBOW
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Second Lboard = %p\n", temp_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x42;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_slot = 0x0;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x1;
-        lb_ptr->brd_nic = 0xffffffffffffffff;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030070;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-        memcpy(&lb_ptr->brd_name[0], "IOBRICK", 7);
-
-	/*
-	 * KLSTRUCT_XBOW Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	memset(klcomp_ptr, 0, sizeof(klcomp_t));
-        klxbow_ptr = (klxbow_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-	printk("xbow_p 0x%p\n", klcomp_ptr);
-
-        klinfo_ptr->struct_type = 0x4;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0xff;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0x0;
-        klinfo_ptr->nasid = 0x0;
-
-        klxbow_ptr->xbow_master_hub_link = 0xb;
-        klxbow_ptr->xbow_port_info[0].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[0].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[0].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[1].port_nasid = 0x401;
-        klxbow_ptr->xbow_port_info[1].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[1].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[2].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[2].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[2].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[3].port_nasid = 0x0; /* ffffffff */
-        klxbow_ptr->xbow_port_info[3].port_flag = 0x6;
-        klxbow_ptr->xbow_port_info[3].port_offset = 0x30070;
-
-        klxbow_ptr->xbow_port_info[4].port_nasid = 0x0; /* ffffff00; */
-        klxbow_ptr->xbow_port_info[4].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[4].port_offset = 0x0;
-
-        klxbow_ptr->xbow_port_info[5].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[5].port_flag = 0x0;
-        klxbow_ptr->xbow_port_info[5].port_offset = 0x0;
-        klxbow_ptr->xbow_port_info[6].port_nasid = 0x0;
-        klxbow_ptr->xbow_port_info[6].port_flag = 0x5;
-        klxbow_ptr->xbow_port_info[6].port_offset = 0x30210;
-        klxbow_ptr->xbow_port_info[7].port_nasid = 0x3;
-        klxbow_ptr->xbow_port_info[7].port_flag = 0x5;
-        klxbow_ptr->xbow_port_info[7].port_offset = 0x302e0;
-	
-	lb_ptr->brd_compts[1] = 0;
-        lb_ptr->brd_numcompts = 1;
-
-
-	/*
-	 * lboard KLTYPE_PBRICK
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Third Lboard %p\n", lb_ptr);
-
-        lb_ptr->brd_next = 0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x72;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x41;
-        lb_ptr->brd_slot = 0xe;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x1;
-        lb_ptr->brd_nic = 0x30e3fd;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030140;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-	/*
-	 * KLSTRUCT_BRI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klbri_ptr = (klbri_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x5;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0xd002;
-        klinfo_ptr->nic = 0x30e3fd;
-        klinfo_ptr->physid = 0xe;
-        klinfo_ptr->virtid = 0xe;
-        klinfo_ptr->widid = 0xe;
-        klinfo_ptr->nasid = 0x0;
-
-        klbri_ptr->bri_eprominfo = 0xff;
-        klbri_ptr->bri_bustype = 0x7;
-        klbri_ptr->bri_mfg_nic = 0x3f4a8;
-
-        lb_ptr->brd_compts[1] = 0;
-        lb_ptr->brd_numcompts = 1;
-
-	/*
-	 * lboard KLTYPE_PBRICK
-	 */
-	lb_ptr = kmalloc(sizeof(lboard_t), GFP_KERNEL);
-	temp_ptr->brd_next = (klconf_off_t)lb_ptr; /* Let the previous point at the new .. */
-	temp_ptr = lb_ptr;
-	printk("Fourth Lboard %p\n", lb_ptr);
-
-        lb_ptr->brd_next = 0x0;
-        lb_ptr->struct_type = 0x1;
-        lb_ptr->brd_type  = 0x72;
-        lb_ptr->brd_sversion = 0x2;
-        lb_ptr->brd_brevision = 0x0;
-        lb_ptr->brd_promver = 0x1;
-        lb_ptr->brd_promver = 0x31;
-        lb_ptr->brd_slot = 0xf;
-        lb_ptr->brd_debugsw = 0x0;
-        lb_ptr->brd_module = 0x145;
-        lb_ptr->brd_partition = 0x1;
-        lb_ptr->brd_diagval = 0x0;
-        lb_ptr->brd_diagparm = 0x0;
-        lb_ptr->brd_inventory = 0x0;
-        lb_ptr->brd_numcompts = 0x6;
-        lb_ptr->brd_nic = 0x30e3fd;
-        lb_ptr->brd_nasid = 0x0;
-        lb_ptr->brd_errinfo = 0x0;
-        lb_ptr->brd_parent = (struct lboard_s *)0x9600000000030140;
-        lb_ptr->brd_graph_link  = (devfs_handle_t)0xffffffff;
-        lb_ptr->brd_owner = 0x0;
-        lb_ptr->brd_nic_flags = 0x0;
-	memcpy(&lb_ptr->brd_name[0], "IP35", 4);
-
-
-	/*
-	 * KLSTRUCT_BRI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-	klbri_ptr = (klbri_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[0] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x5;
-        klinfo_ptr->struct_version = 0x2;
-        klinfo_ptr->flags = 0x1;
-        klinfo_ptr->revision = 0x2;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0xd002;
-        klinfo_ptr->nic = 0x30e3fd;
-        klinfo_ptr->physid = 0xf;
-        klinfo_ptr->virtid = 0xf;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-        klbri_ptr->bri_eprominfo = 0xff;
-        klbri_ptr->bri_bustype = 0x7;
-        klbri_ptr->bri_mfg_nic = 0x3f528;
-
-	/*
-	 * KLSTRUCT_SCSI component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[1] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0xb;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x5;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x1;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_IOC3 Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klioc3_ptr = (klioc3_t *)klcomp_ptr;
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[2] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x6;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x4;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-        klioc3_ptr->ioc3_ssram = 0x0;
-        klioc3_ptr->ioc3_nvram = 0x0;
-
-	/*
-	 * KLSTRUCT_UNKNOWN Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[3] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x0;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x5;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_SCSI Component
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[4] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0xb;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0x1;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x6;
-        klinfo_ptr->virtid = 0x5;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	/*
-	 * KLSTRUCT_UNKNOWN
-	 */
-        klcomp_ptr = kmalloc(sizeof(klcomp_t), GFP_KERNEL);
-        klinfo_ptr = (klinfo_t *)klcomp_ptr;
-        lb_ptr->brd_compts[5] = (klconf_off_t)klcomp_ptr;
-
-        klinfo_ptr->struct_type = 0x0;
-        klinfo_ptr->struct_version = 0x1;
-        klinfo_ptr->flags = 0x31;
-        klinfo_ptr->revision = 0xff;
-        klinfo_ptr->diagval = 0x0;
-        klinfo_ptr->diagparm = 0x0;
-        klinfo_ptr->inventory = 0x0;
-        klinfo_ptr->partid = 0x0;
-        klinfo_ptr->nic = 0xffffffffffffffff;
-        klinfo_ptr->physid = 0x7;
-        klinfo_ptr->virtid = 0x0;
-        klinfo_ptr->widid = 0xf;
-        klinfo_ptr->nasid = 0x0;
-
-	lb_ptr->brd_compts[6] = 0;
-	lb_ptr->brd_numcompts = 6;
-
 }
 
 
 
 
 	
-#ifdef BRINGUP
+#ifdef DEFINE_DUMP_RTNS
 /* 
  * these were useful for printing out registers etc
  * during bringup  
  */
 
-void
+static void
 xdump(long long *addr, int count)
 {
 	int ii;
 	volatile long long *xx = addr;
 
 	for ( ii = 0; ii < count; ii++, xx++ ) {
-		printk("0x%p : 0x%p\n", xx, *xx);
+		printk("0x%p : 0x%p\n", (void *)xx, (void *)*xx);
 	}
 }
 
-void
+static void
 xdump32(unsigned int *addr, int count)
 {
 	int ii;
 	volatile unsigned int *xx = addr;
 
 	for ( ii = 0; ii < count; ii++, xx++ ) {
-		printk("0x%p : 0x%0x\n", xx, *xx);
+		printk("0x%p : 0x%0x\n", (void *)xx, (int)*xx);
 	}
 }
 
-
-
-void
+static void
 clear_ii_error(void)
 {
 	volatile long long *tmp;
@@ -716,8 +135,8 @@
 }
 
 
-void
-dump_ii()
+static void
+dump_ii(void)
 {
 	printk("===== Dump the II regs =====\n");
 	xdump((long long *)0xc0000a0001c00000, 2);
@@ -746,23 +165,8 @@
 	xdump((long long *)0xc0000a000f000000, 1);
 }
 
-void
-dump_lb()
-{
-	printk("===== Dump the LB regs =====\n");
-	xdump((long long *)0xc0000a0001e00000, 1);
-	xdump((long long *)0xc0000a0001e04000, 13);
-	xdump((long long *)0xc0000a0001e04100, 2);
-	xdump((long long *)0xc0000a0001e04200, 2);
-	xdump((long long *)0xc0000a0001e08000, 5);
-	xdump((long long *)0xc0000a0001e08040, 2);
-	xdump((long long *)0xc0000a0001e08050, 3);
-	xdump((long long *)0xc0000a0001e0c000, 3);
-	xdump((long long *)0xc0000a0001e0c020, 4);
-}
-
-void
-dump_crossbow()
+static void
+dump_crossbow(void)
 {
 	printk("===== Dump the Crossbow regs =====\n");
 	clear_ii_error();
@@ -793,4 +197,4 @@
 
 
 }
-#endif /* BRINGUP */
+#endif /* DEFINE_DUMP_RTNS */
diff -Nru a/arch/ia64/sn/io/l1.c b/arch/ia64/sn/io/l1.c
--- a/arch/ia64/sn/io/l1.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/l1.c	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 /* In general, this file is organized in a hierarchy from lower-level
@@ -16,18 +15,12 @@
  *	System controller "message" interface (allows multiplexing
  *		of various kinds of requests and responses with
  *		console I/O)
- *	Console interfaces (there are two):
- *	  (1) "elscuart", used in the IP35prom and (maybe) some
- *		debugging situations elsewhere, and
- *	  (2) "l1_cons", the glue that allows the L1 to act
+ *	Console interface:
+ *	  "l1_cons", the glue that allows the L1 to act
  *		as the system console for the stdio libraries
  *
  * Routines making use of the system controller "message"-style interface
- * can be found in l1_command.c.  Their names are leftover from early SN0, 
- * when the "module system controller" (msc) was known as the "entry level
- * system controller" (elsc).  The names and signatures of those functions 
- * remain unchanged in order to keep the SN0 -> SN1 system controller
- * changes fairly localized.
+ * can be found in l1_command.c.
  */
 
 
@@ -35,45 +28,29 @@
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
+#include <linux/delay.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/clksupport.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/uart16550.h>
+#include <asm/sn/simulator.h>
 
-#include <asm/sn/sn1/uart16550.h>
 
-/*
- * Delete this when atomic_clear is part of atomic.h.
- */
-static __inline__ int
-atomic_clear (int i, atomic_t *v)
-{
-	__s32 old, new;
-
-	do {
-		old = atomic_read(v);
-		new = old & ~i;
-	} while (ia64_cmpxchg("acq", v, old, new, sizeof(atomic_t)) != old);
-	return new;
-}
-
-#if defined(EEPROM_DEBUG)
-#define db_printf(x) printk x
-#else
-#define db_printf(x)
-#endif
+/* Make all console writes atomic */
+#define SYNC_CONSOLE_WRITE	1
 
-// From irix/kern/sys/SN/SN1/bdrkhspecregs.h
-#define    HSPEC_UART_0              0x00000080    /* UART Registers         */
 
 /*********************************************************************
  * Hardware-level (UART) driver routines.
@@ -81,28 +58,33 @@
 
 /* macros for reading/writing registers */
 
-#define LD(x)		(*(volatile uint64_t *)(x))
-#define SD(x, v)        (LD(x) = (uint64_t) (v))
+#define LD(x)			(*(volatile uint64_t *)(x))
+#define SD(x, v)        	(LD(x) = (uint64_t) (v))
 
 /* location of uart receive/xmit data register */
-#define L1_UART_BASE(n)	((ulong)REMOTE_HSPEC_ADDR((n), HSPEC_UART_0))
-#define LOCAL_HUB	LOCAL_HUB_ADDR
-#define LOCK_HUB	REMOTE_HUB_ADDR
-
-#define ADDR_L1_REG(n, r)	\
-    (L1_UART_BASE(n) | ( (r) << 3 ))
+#if defined(CONFIG_IA64_SGI_SN1)
+#define L1_UART_BASE(n)		((ulong)REMOTE_HSPEC_ADDR((n), 0x00000080))
+#define LOCK_HUB		REMOTE_HUB_ADDR
+#elif defined(CONFIG_IA64_SGI_SN2)
+#define L1_UART_BASE(n)		((ulong)REMOTE_HUB((n), SH_JUNK_BUS_UART0))
+#define LOCK_HUB		REMOTE_HUB
+typedef u64 rtc_time_t;
+#endif
 
-#define READ_L1_UART_REG(n, r) \
-    ( LD(ADDR_L1_REG((n), (r))) )
 
-#define WRITE_L1_UART_REG(n, r, v) \
-    ( SD(ADDR_L1_REG((n), (r)), (v)) )
+#define ADDR_L1_REG(n, r)	( L1_UART_BASE(n) | ( (r) << 3 ) )
+#define READ_L1_UART_REG(n, r)	( LD(ADDR_L1_REG((n), (r))) )
+#define WRITE_L1_UART_REG(n, r, v) ( SD(ADDR_L1_REG((n), (r)), (v)) )
+
+/* upper layer interface calling methods */
+#define SERIAL_INTERRUPT_MODE	0
+#define SERIAL_POLLED_MODE	1
 
 
 /* UART-related #defines */
 
 #define UART_BAUD_RATE		57600
-#define UART_FIFO_DEPTH		0xf0
+#define UART_FIFO_DEPTH		16
 #define UART_DELAY_SPAN		10
 #define UART_PUTC_TIMEOUT	50000
 #define UART_INIT_TIMEOUT	100000
@@ -114,17 +96,32 @@
 #define UART_NO_CHAR		(-3)
 #define UART_VECTOR		(-4)
 
-#ifdef BRINGUP
-#define UART_DELAY(x)	{ int i; i = x * 1000; while (--i); }
-#else
-#define UART_DELAY(x)	us_delay(x)
-#endif
+#define UART_DELAY(x)		udelay(x)
+
+/* Some debug counters */
+#define L1C_INTERRUPTS		0
+#define L1C_OUR_R_INTERRUPTS	1
+#define L1C_OUR_X_INTERRUPTS	2
+#define L1C_SEND_CALLUPS	3
+#define L1C_RECEIVE_CALLUPS	4
+#define L1C_SET_BAUD		5
+#define L1C_ALREADY_LOCKED	L1C_SET_BAUD
+#define L1C_R_IRQ		6
+#define L1C_R_IRQ_RET		7
+#define L1C_LOCK_TIMEOUTS	8
+#define L1C_LOCK_COUNTER	9
+#define L1C_UNLOCK_COUNTER	10
+#define L1C_REC_STALLS		11
+#define L1C_CONNECT_CALLS	12
+#define L1C_SIZE		L1C_CONNECT_CALLS	/* Set to the last one */
+
+uint64_t L1_collectibles[L1C_SIZE + 1];
+
 
 /*
  *	Some macros for handling Endian-ness
  */
 
-#ifdef	LITTLE_ENDIAN
 #define COPY_INT_TO_BUFFER(_b, _i, _n)		\
 	{					\
 		_b[_i++] = (_n >> 24) & 0xff;	\
@@ -149,41 +146,61 @@
 	    _xyz[1] = _b[_i++];			\
 	    _xyz[0] = _b[_i++];			\
 	}
-#else	/* BIG_ENDIAN */
 
-extern char *bcopy(const char * src, char * dest, int count);
+void snia_kmem_free(void *where, int size);
 
-#define COPY_INT_TO_BUFFER(_b, _i, _n)			\
-	{						\
-		bcopy((char *)&_n, _b, sizeof(_n));	\
-		_i += sizeof(_n);			\
-	}
+#define ALREADY_LOCKED		1
+#define NOT_LOCKED		0
+static int early_l1_serial_out(nasid_t, char *, int, int /* defines above*/ );
 
-#define COPY_BUFFER_TO_INT(_b, _i, _n)			\
-	{						\
-		bcopy(&_b[_i], &_n, sizeof(_n));	\
-		_i += sizeof(_n);			\
-	}
-
-#define COPY_BUFFER_TO_BUFFER(_b, _i, _bn)		\
-	{						\
-            bcopy(&(_b[_i]), _bn, sizeof(int));		\
-            _i += sizeof(int);				\
-	}
-#endif	/* LITTLE_ENDIAN */
+#define BCOPY(x,y,z)	memcpy(y,x,z)
 
-void kmem_free(void *where, int size);
+uint8_t L1_interrupts_connected;		/* Non-zero when we are in interrupt mode */
 
-#define BCOPY(x,y,z)	memcpy(y,x,z)
 
 /*
  * Console locking defines and functions.
  *
  */
 
-#ifdef BRINGUP
-#define FORCE_CONSOLE_NASID
-#endif
+uint8_t L1_cons_is_inited = 0;			/* non-zero when console is init'd */
+nasid_t Master_console_nasid = (nasid_t)-1;
+extern nasid_t console_nasid;
+
+u64 ia64_sn_get_console_nasid(void);
+
+inline nasid_t
+get_master_nasid(void)
+{
+#if defined(CONFIG_IA64_SGI_SN1)
+	nasid_t nasid = Master_console_nasid;
+
+	if ( nasid == (nasid_t)-1 ) {
+		nasid = (nasid_t)ia64_sn_get_console_nasid();
+		if ( (nasid < 0) || (nasid >= MAX_NASIDS) ) {
+			/* Out of bounds, use local */
+			console_nasid = nasid = get_nasid();
+		}
+		else {
+			/* Got a valid nasid, set the console_nasid */
+			char xx[100];
+/* zzzzzz - force nasid to 0 for now */
+			sprintf(xx, "Master console is set to nasid %d (%d)\n", 0, (int)nasid);
+nasid = 0;
+/* end zzzzzz */
+			xx[99] = (char)0;
+			early_l1_serial_out(nasid, xx, strlen(xx), NOT_LOCKED);
+			Master_console_nasid = console_nasid = nasid;
+		}
+	}
+	return(nasid);
+#else
+	return((nasid_t)0);
+#endif	/* CONFIG_IA64_SGI_SN1 */
+}
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
 
 #define HUB_LOCK		16
 
@@ -199,7 +216,6 @@
 
 #define RTC_TIME_MAX		((rtc_time_t) ~0ULL)
 
-
 /*
  * primary_lock
  *
@@ -295,26 +311,37 @@
 
 #define LOCK_TIMEOUT	(0x1500000 * 1) /* 0x1500000 is ~30 sec */
 
-inline void
+void
 lock_console(nasid_t nasid)
 {
 	int ret;
 
+	/* If we already have it locked, just return */
+	L1_collectibles[L1C_LOCK_COUNTER]++;
+
 	ret = hub_lock_timeout(nasid, HUB_LOCK, (rtc_time_t)LOCK_TIMEOUT);
 	if ( ret != 0 ) {
+		L1_collectibles[L1C_LOCK_TIMEOUTS]++;
 		/* timeout */
 		hub_unlock(nasid, HUB_LOCK);
 		/* If the 2nd lock fails, just pile ahead.... */
 		hub_lock_timeout(nasid, HUB_LOCK, (rtc_time_t)LOCK_TIMEOUT);
+		L1_collectibles[L1C_LOCK_TIMEOUTS]++;
 	}
 }
 
 inline void
 unlock_console(nasid_t nasid)
 {
+	L1_collectibles[L1C_UNLOCK_COUNTER]++;
 	hub_unlock(nasid, HUB_LOCK);
 }
 
+#else /* SN2 */
+inline void lock_console(nasid_t n)	{}
+inline void unlock_console(nasid_t n)	{}
+
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 int 
 get_L1_baud(void)
@@ -325,27 +352,18 @@
 
 /* uart driver functions */
 
-static void
+static inline void
 uart_delay( rtc_time_t delay_span )
 {
     UART_DELAY( delay_span );
 }
 
-#define UART_PUTC_READY(n)      ( (READ_L1_UART_REG((n), REG_LSR) & LSR_XHRE) && (READ_L1_UART_REG((n), REG_MSR) & MSR_CTS) )
+#define UART_PUTC_READY(n)      (READ_L1_UART_REG((n), REG_LSR) & LSR_XHRE)
 
 static int
 uart_putc( l1sc_t *sc ) 
 {
-#ifdef BRINGUP
-    /* need a delay to avoid dropping chars */
-    UART_DELAY(57);
-#endif
-#ifdef FORCE_CONSOLE_NASID
-    /* We need this for the console write path _elscuart_flush() -> brl1_send() */
-    sc->nasid = 0;
-#endif
-    WRITE_L1_UART_REG( sc->nasid, REG_DAT,
-		       sc->send[sc->sent] );
+    WRITE_L1_UART_REG( sc->nasid, REG_DAT, sc->send[sc->sent] );
     return UART_SUCCESS;
 }
 
@@ -356,10 +374,6 @@
     u_char lsr_reg = 0;
     nasid_t nasid = sc->nasid;
 
-#ifdef FORCE_CONSOLE_NASID
-    nasid = sc->nasid = 0;
-#endif
-
     if( (lsr_reg = READ_L1_UART_REG( nasid, REG_LSR )) & 
 	(LSR_RCA | LSR_PARERR | LSR_FRMERR) ) 
     {
@@ -396,9 +410,10 @@
 	}
     }
 
-    if ( sc->uart == BRL1_LOCALUART )
+    if ( sc->uart == BRL1_LOCALHUB_UART )
 	lock_console(nasid);
 
+    /* Setup for the proper baud rate */
     WRITE_L1_UART_REG( nasid, REG_LCR, LCR_DLAB );
 	uart_delay( UART_DELAY_SPAN );
     WRITE_L1_UART_REG( nasid, REG_DLH, (clkdiv >> 8) & 0xff );
@@ -407,6 +422,8 @@
 	uart_delay( UART_DELAY_SPAN );
 
     /* set operating parameters and set DLAB to 0 */
+
+    /* 8bit, one stop, clear request to send, auto flow control */
     WRITE_L1_UART_REG( nasid, REG_LCR, LCR_BITS8 | LCR_STOP1 );
 	uart_delay( UART_DELAY_SPAN );
     WRITE_L1_UART_REG( nasid, REG_MCR, MCR_RTS | MCR_AFE );
@@ -416,23 +433,28 @@
     WRITE_L1_UART_REG( nasid, REG_ICR, 0x0 );
 	uart_delay( UART_DELAY_SPAN );
 
-    /* enable FIFO mode and reset both FIFOs */
+    /* enable FIFO mode and reset both FIFOs, trigger on 1 */
     WRITE_L1_UART_REG( nasid, REG_FCR, FCR_FIFOEN );
 	uart_delay( UART_DELAY_SPAN );
-    WRITE_L1_UART_REG( nasid, REG_FCR,
-	FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO );
+    WRITE_L1_UART_REG( nasid, REG_FCR, FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL0);
 
-    if ( sc->uart == BRL1_LOCALUART )
+    if ( sc->uart == BRL1_LOCALHUB_UART )
 	unlock_console(nasid);
 }
 
 /* This requires the console lock */
+
+#if	defined(CONFIG_IA64_SGI_SN1)
+
 static void
 uart_intr_enable( l1sc_t *sc, u_char mask )
 {
     u_char lcr_reg, icr_reg;
     nasid_t nasid = sc->nasid;
 
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(nasid);
+
     /* make sure that the DLAB bit in the LCR register is 0
      */
     lcr_reg = READ_L1_UART_REG( nasid, REG_LCR );
@@ -444,6 +466,9 @@
     icr_reg = READ_L1_UART_REG( nasid, REG_ICR );
     icr_reg |= mask;
     WRITE_L1_UART_REG( nasid, REG_ICR, icr_reg /*(ICR_RIEN | ICR_TIEN)*/ );
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(nasid);
 }
 
 /* This requires the console lock */
@@ -453,6 +478,9 @@
     u_char lcr_reg, icr_reg;
     nasid_t nasid = sc->nasid;
 
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(nasid);
+
     /* make sure that the DLAB bit in the LCR register is 0
      */
     lcr_reg = READ_L1_UART_REG( nasid, REG_LCR );
@@ -464,7 +492,11 @@
     icr_reg = READ_L1_UART_REG( nasid, REG_ICR );
     icr_reg &= mask;
     WRITE_L1_UART_REG( nasid, REG_ICR, icr_reg /*(ICR_RIEN | ICR_TIEN)*/ );
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(nasid);
 }
+#endif	/* CONFIG_IA64_SGI_SN1 */
 
 #define uart_enable_xmit_intr(sc) \
 	uart_intr_enable((sc), ICR_TIEN)
@@ -511,10 +543,6 @@
     net_vec_t path = sc->uart;
     rtc_time_t expire = rtc_time() + RTR_UART_PUTC_TIMEOUT;
 
-#ifdef FORCE_CONSOLE_NASID
-    /* We need this for the console write path _elscuart_flush() -> brl1_send() */
-    nasid = sc->nasid = 0;
-#endif
     c = (sc->send[sc->sent] & 0xffULL);
     
     while( 1 ) 
@@ -543,10 +571,6 @@
     nasid_t nasid = sc->nasid;
     net_vec_t path = sc->uart;
 
-#ifdef FORCE_CONSOLE_NASID
-    nasid = sc->nasid = 0;
-#endif
-
     READ_RTR_L1_UART_REG( path, nasid, REG_LSR, &regval );
     if( regval & (LSR_RCA | LSR_PARERR | LSR_FRMERR) )
     {
@@ -617,6 +641,15 @@
     return 0;
 }
 
+/*********************************************************************
+ * locking macros 
+ */
+
+#define L1SC_SEND_LOCK(l,p)   { if ((l)->uart == BRL1_LOCALHUB_UART) spin_lock_irqsave(&((l)->send_lock),p); }
+#define L1SC_SEND_UNLOCK(l,p) { if ((l)->uart == BRL1_LOCALHUB_UART) spin_unlock_irqrestore(&((l)->send_lock), p); }
+#define L1SC_RECV_LOCK(l,p)   { if ((l)->uart == BRL1_LOCALHUB_UART) spin_lock_irqsave(&((l)->recv_lock), p); } 
+#define L1SC_RECV_UNLOCK(l,p) { if ((l)->uart == BRL1_LOCALHUB_UART) spin_unlock_irqrestore(&((l)->recv_lock), p); }
+
 
 /*********************************************************************
  * subchannel manipulation 
@@ -626,31 +659,43 @@
  * associated with particular subchannels (e.g., receive queues).
  *
  */
+#define SUBCH_LOCK(sc, p)		spin_lock_irqsave( &((sc)->subch_lock), p )
+#define SUBCH_UNLOCK(sc, p)		spin_unlock_irqrestore( &((sc)->subch_lock), p )
+#define SUBCH_DATA_LOCK(sbch, p) 	spin_lock_irqsave( &((sbch)->data_lock), p )
+#define SUBCH_DATA_UNLOCK(sbch, p)	spin_unlock_irqrestore( &((sbch)->data_lock), p )
 
-#ifdef SPINLOCKS_WORK
-#define SUBCH_LOCK(sc)			spin_lock_irq( &((sc)->subch_lock) )
-#define SUBCH_UNLOCK(sc)		spin_unlock_irq( &((sc)->subch_lock) )
-#define SUBCH_DATA_LOCK(sbch) 		spin_lock_irq( &((sbch)->data_lock) )
-#define SUBCH_DATA_UNLOCK(sbch)		spin_unlock_irq( &((sbch)->data_lock) )
-#else
-#define SUBCH_LOCK(sc)
-#define SUBCH_UNLOCK(sc)
-#define SUBCH_DATA_LOCK(sbch)
-#define SUBCH_DATA_UNLOCK(sbch)
-#endif
 
-
-/* get_myid is an internal function that reads the PI_CPU_NUM
- * register of the local bedrock to determine which of the
- * four possible CPU's "this" one is
+/*
+ * set a function to be called for subchannel ch in the event of
+ * a transmission low-water interrupt from the uart
  */
-static int
-get_myid( void )
+void
+subch_set_tx_notify( l1sc_t *sc, int ch, brl1_notif_t func )
 {
-    return( LD(LOCAL_HUB(PI_CPU_NUM)) );
+    unsigned long pl = 0;
+
+    L1SC_SEND_LOCK( sc, pl );
+#if	!defined(SYNC_CONSOLE_WRITE)
+    if ( func && !sc->send_in_use )
+	uart_enable_xmit_intr( sc );
+#endif
+    sc->subch[ch].tx_notify = func;
+    L1SC_SEND_UNLOCK(sc, pl );
 }
 
+/*
+ * set a function to be called for subchannel ch when data is received
+ */
+void
+subch_set_rx_notify( l1sc_t *sc, int ch, brl1_notif_t func )
+{
+    unsigned long pl = 0;
+    brl1_sch_t *subch = &(sc->subch[ch]);
 
+    SUBCH_DATA_LOCK( subch, pl );
+    sc->subch[ch].rx_notify = func;
+    SUBCH_DATA_UNLOCK( subch, pl );
+}
 
 /*********************************************************************
  * Queue manipulation macros
@@ -767,14 +812,16 @@
  * brl1_discard_packet is a dummy "receive callback" used to get rid
  * of packets we don't want
  */
-void brl1_discard_packet( l1sc_t *sc, int ch )
+void brl1_discard_packet( int dummy0, void *dummy1, struct pt_regs *dummy2, l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
     brl1_sch_t *subch = &sc->subch[ch];
+
     sc_cq_t *q = subch->iqp;
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     q->opos = q->ipos;
-    atomic_clear( &(subch->packet_arrived), ~((unsigned)0) );
-    SUBCH_DATA_UNLOCK( subch );
+    atomic_set(&(subch->packet_arrived), 0);
+    SUBCH_DATA_UNLOCK( subch, pl );
 }
 
 
@@ -789,17 +836,15 @@
 static int
 brl1_send_chars( l1sc_t *sc )
 {
-    /* In the kernel, we track the depth of the C brick's UART's
+    /* We track the depth of the C brick's UART's
      * fifo in software, and only check if the UART is accepting
      * characters when our count indicates that the fifo should
      * be full.
      *
-     * For remote (router) UARTs, and also for the local (C brick)
-     * UART in the prom, we check with the UART before sending every
+     * For remote (router) UARTs, we check with the UART before sending every
      * character.
      */
-    if( sc->uart == BRL1_LOCALUART ) 
-    {
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
 	if( !(sc->fifo_space) && UART_PUTC_READY( sc->nasid ) )
 	    sc->fifo_space = UART_FIFO_DEPTH;
 	
@@ -809,16 +854,10 @@
 	    sc->sent++;
 	}
     }
+    else {
 
-    else
-
-    /* The following applies to all UARTs in the prom, and to remote
-     * (router) UARTs in the kernel...
-     */
-
-#define TIMEOUT_RETRIES	30
+	/* remote (router) UARTs */
 
-    {
 	int result;
 	int tries = 0;
 
@@ -831,7 +870,7 @@
 	    if( result == UART_TIMEOUT ) {
 		tries++;
 		/* send this character in TIMEOUT_RETRIES... */
-		if( tries < TIMEOUT_RETRIES ) {
+		if( tries < 30 /* TIMEOUT_RETRIES */ ) {
 		    continue;
 		}
 		/* ...or else... */
@@ -864,33 +903,39 @@
 static int
 brl1_send( l1sc_t *sc, char *msg, int len, u_char type_and_subch, int wait )
 {
+    unsigned long pl = 0;
     int index;
     int pkt_len = 0;
     unsigned short crc = INIT_CRC;
     char *send_ptr = sc->send;
 
-#ifdef BRINGUP
-    /* We want to be sure that we are sending the entire packet before returning */
-    wait = 1;
-#endif
-    if ( sc->uart == BRL1_LOCALUART )
-	lock_console(sc->nasid);
 
-    if( sc->send_in_use ) {
-	if( !wait ) {
-    	    if ( sc->uart == BRL1_LOCALUART )
-	    	unlock_console(sc->nasid);
-	    return 0; /* couldn't send anything; wait for buffer to drain */
-	}
-	else {
-	    /* buffer's in use, but we're synchronous I/O, so we're going
-	     * to send whatever's in there right now and take the buffer
-	     */
-	    while( sc->sent < sc->send_len )
+    if( sc->send_in_use && !(wait) ) {
+	/* We are in the middle of sending, but can wait until done */
+	return 0;
+    }
+    else if( sc->send_in_use ) {
+	/* buffer's in use, but we're synchronous I/O, so we're going
+	 * to send whatever's in there right now and take the buffer
+	 */
+	int counter = 0;
+
+	if ( sc->uart == BRL1_LOCALHUB_UART )
+		lock_console(sc->nasid);
+	L1SC_SEND_LOCK(sc, pl);
+	while( sc->sent < sc->send_len ) {
 		brl1_send_chars( sc );
+		if ( counter++ > 0xfffff ) {
+			char *str = "Looping waiting for uart to clear (1)\n";
+			early_l1_serial_out(sc->nasid, str, strlen(str), ALREADY_LOCKED);
+			break;
+		}
 	}
     }
     else {
+	if ( sc->uart == BRL1_LOCALHUB_UART )
+		lock_console(sc->nasid);
+	L1SC_SEND_LOCK(sc, pl);
 	sc->send_in_use = 1;
     }
     *send_ptr++ = BRL1_FLAG_CH;
@@ -948,23 +993,100 @@
     sc->send_len = pkt_len;
     sc->sent = 0;
 
-    do {
-	brl1_send_chars( sc );
-    } while( (sc->sent < sc->send_len) && wait );
+    {
+	int counter = 0;
+	do {
+		brl1_send_chars( sc );
+		if ( counter++ > 0xfffff ) {
+			char *str = "Looping waiting for uart to clear (2)\n";
+			early_l1_serial_out(sc->nasid, str, strlen(str), ALREADY_LOCKED);
+			break;
+		}
+	} while( (sc->sent < sc->send_len) && wait );
+    }
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(sc->nasid);
 
     if( sc->sent == sc->send_len ) {
-	/* success! release the send buffer */
+	/* success! release the send buffer and call the callup */
+#if	!defined(SYNC_CONSOLE_WRITE)
+	brl1_notif_t callup;
+#endif
+
 	sc->send_in_use = 0;
+	/* call any upper layer that's asked for notification */
+#if	defined(XX_SYNC_CONSOLE_WRITE)
+	/*
+	 * This is probably not a good idea - since the l1_ write func can be called multiple
+	 * time within the callup function.
+	 */
+	callup = subch->tx_notify;
+	if( callup && (SUBCH(type_and_subch) == SC_CONS_SYSTEM) ) {
+		L1_collectibles[L1C_SEND_CALLUPS]++;
+		(*callup)(sc->subch[SUBCH(type_and_subch)].irq_frame.bf_irq,
+				sc->subch[SUBCH(type_and_subch)].irq_frame.bf_dev_id,
+				sc->subch[SUBCH(type_and_subch)].irq_frame.bf_regs, sc, SUBCH(type_and_subch));
+	}
+#endif	/* SYNC_CONSOLE_WRITE */
     }
-    else if( !wait ) {
+#if	!defined(SYNC_CONSOLE_WRITE)
+    else if ( !wait ) {
 	/* enable low-water interrupts so buffer will be drained */
 	uart_enable_xmit_intr(sc);
     }
-    if ( sc->uart == BRL1_LOCALUART )
-	unlock_console(sc->nasid);
+#endif
+
+    L1SC_SEND_UNLOCK(sc, pl);
+
     return len;
 }
 
+/* brl1_send_cont is intended to be called as an interrupt service
+ * routine.  It sends until the UART won't accept any more characters,
+ * or until an error is encountered (in which case we surrender the
+ * send buffer and give up trying to send the packet).  Once the
+ * last character in the packet has been sent, this routine releases
+ * the send buffer and calls any previously-registered "low-water"
+ * output routines.
+ */
+
+#if	!defined(SYNC_CONSOLE_WRITE)
+
+int
+brl1_send_cont( l1sc_t *sc )
+{
+    unsigned long pl = 0;
+    int done = 0;
+    brl1_notif_t callups[BRL1_NUM_SUBCHANS];
+    brl1_notif_t *callup;
+    brl1_sch_t *subch;
+    int index;
+
+    /*
+     * I'm not sure how I think this is to be handled - whether the lock is held
+     * over the interrupt - but it seems like it is a bad idea....
+     */
+
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	lock_console(sc->nasid);
+    L1SC_SEND_LOCK(sc, pl);
+    brl1_send_chars( sc );
+    done = (sc->sent == sc->send_len);
+    if( done ) {
+	sc->send_in_use = 0;
+#if	!defined(SYNC_CONSOLE_WRITE)
+	uart_disable_xmit_intr(sc);
+#endif
+    }
+    if ( sc->uart == BRL1_LOCALHUB_UART )
+	unlock_console(sc->nasid);
+    /* Release the lock */
+    L1SC_SEND_UNLOCK(sc, pl);
+
+    return 0;
+}
+#endif	/* SYNC_CONSOLE_WRITE */
 
 /* internal function -- used by brl1_receive to read a character 
  * from the uart and check whether errors occurred in the process.
@@ -1046,40 +1168,33 @@
  * error (parity error, bad header, bad CRC, etc.).
  */
 
-#define STATE_SET(l,s)	((l)->brl1_state = (s))
-#define STATE_GET(l)	((l)->brl1_state)
+#define STATE_SET(l,s)		((l)->brl1_state = (s))
+#define STATE_GET(l)		((l)->brl1_state)
 
 #define LAST_HDR_SET(l,h)	((l)->brl1_last_hdr = (h))
 #define LAST_HDR_GET(l)		((l)->brl1_last_hdr)
 
-#define SEQSTAMP_INCR(l)
-#define SEQSTAMP_GET(l)
-
 #define VALID_HDR(c)				\
     ( SUBCH((c)) <= SC_CONS_SYSTEM		\
 	? PKT_TYPE((c)) == BRL1_REQUEST		\
 	: ( PKT_TYPE((c)) == BRL1_RESPONSE ||	\
 	    PKT_TYPE((c)) == BRL1_EVENT ) )
 
-#define IS_TTY_PKT(l) \
-         ( SUBCH(LAST_HDR_GET(l)) <= SC_CONS_SYSTEM ? 1 : 0 )
+#define IS_TTY_PKT(l)		( SUBCH(LAST_HDR_GET(l)) <= SC_CONS_SYSTEM ? 1 : 0 )
 
 
 int
-brl1_receive( l1sc_t *sc )
+brl1_receive( l1sc_t *sc, int mode )
 {
     int result;		/* value to be returned by brl1_receive */
     int c;		/* most-recently-read character	     	*/
     int done;		/* set done to break out of recv loop	*/
+    unsigned long pl = 0, cpl = 0;
     sc_cq_t *q;		/* pointer to queue we're working with	*/
 
     result = BRL1_NO_MESSAGE;
 
-#ifdef FORCE_CONSOLE_NASID
-    sc->nasid = 0;
-#endif
-    if ( sc->uart == BRL1_LOCALUART )
-	lock_console(sc->nasid);
+    L1SC_RECV_LOCK(sc, cpl);
 
     done = 0;
     while( !done )
@@ -1210,8 +1325,7 @@
 		 * starting a new packet
 		 */
 		STATE_SET( sc, BRL1_FLAG );
-		SEQSTAMP_INCR(sc); /* bump the packet sequence counter */
-		
+
 		/* if the packet body has less than 2 characters,
 		 * it can't be a well-formed packet.  Discard it.
 		 */
@@ -1258,7 +1372,7 @@
 
 		/* get the subchannel and lock it */
 		subch = &(sc->subch[SUBCH( LAST_HDR_GET(sc) )]);
-		SUBCH_DATA_LOCK( subch );
+		SUBCH_DATA_LOCK( subch, pl );
 		
 		/* if this isn't a console packet, we need to record
 		 * a length byte
@@ -1276,14 +1390,16 @@
 		 */
 		atomic_inc(&(subch->packet_arrived));
 		callup = subch->rx_notify;
-		SUBCH_DATA_UNLOCK( subch );
+		SUBCH_DATA_UNLOCK( subch, pl );
 
-		if( callup ) {
-		    if ( sc->uart == BRL1_LOCALUART )
-			unlock_console(sc->nasid);
-		    (*callup)( sc, SUBCH(LAST_HDR_GET(sc)) );
-		    if ( sc->uart == BRL1_LOCALUART )
-			lock_console(sc->nasid);
+		if( callup && (mode == SERIAL_INTERRUPT_MODE) ) {
+		    L1SC_RECV_UNLOCK( sc, cpl );
+		    L1_collectibles[L1C_RECEIVE_CALLUPS]++;
+		    (*callup)( sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_irq,
+				sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_dev_id,
+				sc->subch[SUBCH(LAST_HDR_GET(sc))].irq_frame.bf_regs,
+				sc, SUBCH(LAST_HDR_GET(sc)) );
+		    L1SC_RECV_LOCK( sc, cpl );
 		}
 		continue;	/* go back for more! */
 	    }
@@ -1351,9 +1467,8 @@
 
 	} /* end of switch( STATE_GET(sc) ) */
     } /* end of while(!done) */
-    
-    if ( sc->uart == BRL1_LOCALUART )
-	unlock_console(sc->nasid);
+
+    L1SC_RECV_UNLOCK( sc, cpl );
 
     return result;
 }	    
@@ -1370,13 +1485,10 @@
     brl1_sch_t *subch;
 
     bzero( sc, sizeof( *sc ) );
-#ifdef FORCE_CONSOLE_NASID
-    nasid = (nasid_t)0;
-#endif
     sc->nasid = nasid;
     sc->uart = uart;
-    sc->getc_f = (uart == BRL1_LOCALUART ? uart_getc : rtr_uart_getc);
-    sc->putc_f = (uart == BRL1_LOCALUART ? uart_putc : rtr_uart_putc);
+    sc->getc_f = (uart == BRL1_LOCALHUB_UART ? uart_getc : rtr_uart_getc);
+    sc->putc_f = (uart == BRL1_LOCALHUB_UART ? uart_putc : rtr_uart_putc);
     sc->sol = 1;
     subch = sc->subch;
 
@@ -1403,9 +1515,8 @@
     spin_lock_init( &(subch->data_lock) );
     sv_init( &(subch->arrive_sv), &subch->data_lock, SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */ );
     subch->tx_notify = NULL;
-    if( sc->uart == BRL1_LOCALUART ) {
-	subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
-				       NASID_TO_COMPACT_NODEID(nasid) );
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
+	subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP, NASID_TO_COMPACT_NODEID(nasid) );
 	ASSERT( subch->iqp );
 	cq_init( subch->iqp );
 	subch->rx_notify = NULL;
@@ -1440,8 +1551,10 @@
     /* initialize synchronization structures
      */
     spin_lock_init( &(sc->subch_lock) );
+    spin_lock_init( &(sc->send_lock) );
+    spin_lock_init( &(sc->recv_lock) );
 
-    if( sc->uart == BRL1_LOCALUART ) {
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
 	uart_init( sc, UART_BAUD_RATE );
     }
     else {
@@ -1461,23 +1574,397 @@
     }
 }
 
+/*********************************************************************
+ * These are interrupt-related functions used in the kernel to service
+ * the L1.
+ */
+
+/*
+ * brl1_intrd is the function which is called on a console interrupt.
+ */
+
+#if defined(CONFIG_IA64_SGI_SN1)
+
+static void
+brl1_intrd(int irq, void *dev_id, struct pt_regs *stuff)
+{
+    u_char isr_reg;
+    l1sc_t *sc = get_elsc();
+    int ret;
+
+    L1_collectibles[L1C_INTERRUPTS]++;
+    isr_reg = READ_L1_UART_REG(sc->nasid, REG_ISR);
+
+    /* Save for callup args in console */
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_irq = irq;
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_dev_id = dev_id;
+    sc->subch[SC_CONS_SYSTEM].irq_frame.bf_regs = stuff;
+
+#if	defined(SYNC_CONSOLE_WRITE)
+    while( isr_reg & ISR_RxRDY )
+#else
+    while( isr_reg & (ISR_RxRDY | ISR_TxRDY) )
+#endif
+    {
+	if( isr_reg & ISR_RxRDY ) {
+	    L1_collectibles[L1C_OUR_R_INTERRUPTS]++;
+	    ret = brl1_receive(sc, SERIAL_INTERRUPT_MODE);
+	    if ( (ret != BRL1_VALID) && (ret != BRL1_NO_MESSAGE) && (ret != BRL1_PROTOCOL) && (ret != BRL1_CRC) )
+		L1_collectibles[L1C_REC_STALLS] = ret;
+	}
+#if	!defined(SYNC_CONSOLE_WRITE)
+	if( (isr_reg & ISR_TxRDY) || (sc->send_in_use && UART_PUTC_READY(sc->nasid)) ) {
+	    L1_collectibles[L1C_OUR_X_INTERRUPTS]++;
+	    brl1_send_cont(sc);
+	}
+#endif	/* SYNC_CONSOLE_WRITE */
+	isr_reg = READ_L1_UART_REG(sc->nasid, REG_ISR);
+    }
+}
+#endif	/* CONFIG_IA64_SGI_SN1 */
+
+
+/*
+ * Install a callback function for the system console subchannel 
+ * to allow an upper layer to be notified when the send buffer 
+ * has been emptied.
+ */
+static inline void
+l1_tx_notif( brl1_notif_t func )
+{
+	subch_set_tx_notify( &NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid()))->module->elsc,
+			SC_CONS_SYSTEM, func );
+}
+
+
+/*
+ * Install a callback function for the system console subchannel
+ * to allow an upper layer to be notified when a packet has been
+ * received.
+ */
+static inline void
+l1_rx_notif( brl1_notif_t func )
+{
+	subch_set_rx_notify( &NODEPDA(NASID_TO_COMPACT_NODEID(get_master_nasid()))->module->elsc,
+				SC_CONS_SYSTEM, func );
+}
+
+
+/* brl1_intr is called directly from the uart interrupt; after it runs, the
+ * interrupt "daemon" xthread is signalled to continue.
+ */
+void
+brl1_intr( void )
+{
+}
+
+#define BRL1_INTERRUPT_LEVEL	65	/* linux request_irq() value */
+
+/* Return the current interrupt level */
+
+//#define CONSOLE_POLLING_ALSO
+
+int
+l1_get_intr_value( void )
+{
+#ifdef	CONSOLE_POLLING_ALSO
+	return(0);
+#else
+	return(BRL1_INTERRUPT_LEVEL);
+#endif
+}
+
+/* Disconnect the callup functions - throw away interrupts */
+
+void
+l1_unconnect_intr(void)
+{
+	/* UnRegister the upper-level callup functions */
+	l1_rx_notif((brl1_notif_t)NULL);
+	l1_tx_notif((brl1_notif_t)NULL);
+	/* We do NOT unregister the interrupts */
+}
+
+/* Set up uart interrupt handling for this node's uart */
+
+void
+l1_connect_intr(void *rx_notify, void *tx_notify)
+{
+	l1sc_t *sc;
+	nasid_t nasid;
+#if defined(CONFIG_IA64_SGI_SN1)
+	int tmp;
+#endif
+	nodepda_t *console_nodepda;
+	int intr_connect_level(cpuid_t, int, ilvl_t, intr_func_t);
+
+	if ( L1_interrupts_connected ) {
+		/* Interrupts are connected, so just register the callups */
+		l1_rx_notif((brl1_notif_t)rx_notify);
+		l1_tx_notif((brl1_notif_t)tx_notify);
+
+		L1_collectibles[L1C_CONNECT_CALLS]++;
+		return;
+	}
+	else
+		L1_interrupts_connected = 1;
+
+	nasid = get_master_nasid();
+	console_nodepda = NODEPDA(NASID_TO_COMPACT_NODEID(nasid));
+	sc = &console_nodepda->module->elsc;
+	sc->intr_cpu = console_nodepda->node_first_cpu;
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	if ( intr_connect_level(sc->intr_cpu, UART_INTR, INTPEND0_MAXMASK, (intr_func_t)brl1_intr) ) {
+		L1_interrupts_connected = 0; /* FAILS !! */
+	}
+	else {
+		void synergy_intr_connect(int, int);
+
+		synergy_intr_connect(UART_INTR, sc->intr_cpu);
+		L1_collectibles[L1C_R_IRQ]++;
+		tmp = request_irq(BRL1_INTERRUPT_LEVEL, brl1_intrd, SA_INTERRUPT | SA_SHIRQ, "l1_protocol_driver", (void *)sc);
+		L1_collectibles[L1C_R_IRQ_RET] = (uint64_t)tmp;
+		if ( tmp ) {
+			L1_interrupts_connected = 0; /* FAILS !! */
+		}
+		else {
+			/* Register the upper-level callup functions */
+			l1_rx_notif((brl1_notif_t)rx_notify);
+			l1_tx_notif((brl1_notif_t)tx_notify);
+
+			/* Set the uarts the way we like it */
+			uart_enable_recv_intr( sc );
+			uart_disable_xmit_intr( sc );
+		}
+	}
+#endif	/* CONFIG_IA64_SGI_SN1 */
+}
+
+
+/* Set the line speed */
+
+void
+l1_set_baud(int baud)
+{
+#if 0
+	nasid_t nasid;
+	static void uart_init(l1sc_t *, int);
+#endif
+
+	L1_collectibles[L1C_SET_BAUD]++;
+
+#if 0
+	if ( L1_cons_is_inited ) {
+		nasid = get_master_nasid();
+		if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 )
+			uart_init(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, baud);
+	}
+#endif
+	return;
+}
+
 
 /* These are functions to use from serial_in/out when in protocol
  * mode to send and receive uart control regs. These are external
  * interfaces into the protocol driver.
  */
+
 void
 l1_control_out(int offset, int value)
 {
-	nasid_t nasid = 0; //(get_elsc())->nasid;
+	nasid_t nasid = get_master_nasid();
 	WRITE_L1_UART_REG(nasid, offset, value); 
 }
 
+/* Console input exported interface. Return a register value.  */
+
+int
+l1_control_in_polled(int offset)
+{
+	static int l1_control_in_local(int, int);
+
+	return(l1_control_in_local(offset, SERIAL_POLLED_MODE));
+}
+
 int
 l1_control_in(int offset)
 {
-	nasid_t nasid = 0; //(get_elsc())->nasid;
-	return(READ_L1_UART_REG(nasid, offset)); 
+	static int l1_control_in_local(int, int);
+
+	return(l1_control_in_local(offset, SERIAL_INTERRUPT_MODE));
+}
+
+static int
+l1_control_in_local(int offset, int mode)
+{
+	nasid_t nasid;
+	int ret, input;
+	static int l1_poll(l1sc_t *, int);
+
+	nasid = get_master_nasid();
+	ret = READ_L1_UART_REG(nasid, offset); 
+
+	if ( offset == REG_LSR ) {
+		ret |= (LSR_XHRE | LSR_XSRE);	/* can send anytime */
+		if ( L1_cons_is_inited ) {
+			if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 ) {
+				input = l1_poll(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, mode);
+				if ( input ) {
+					ret |= LSR_RCA;
+				}
+			}
+		}
+	}
+	return(ret);
+}
+
+/*
+ * Console input exported interface. Return a character (if one is available)
+ */
+
+int
+l1_serial_in_polled(void)
+{
+	static int l1_serial_in_local(int mode);
+
+	return(l1_serial_in_local(SERIAL_POLLED_MODE));
+}
+
+int
+l1_serial_in(void)
+{
+	static int l1_serial_in_local(int mode);
+
+	return(l1_serial_in_local(SERIAL_INTERRUPT_MODE));
+}
+
+static int
+l1_serial_in_local(int mode)
+{
+	nasid_t nasid;
+	l1sc_t *sc;
+	int value;
+	static int l1_getc( l1sc_t *, int );
+	static inline l1sc_t *early_sc_init(nasid_t);
+
+	nasid = get_master_nasid();
+	sc = early_sc_init(nasid);
+	if ( L1_cons_is_inited ) {
+		if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 ) {
+			sc = &NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc;
+		}
+	}
+	value = l1_getc(sc, mode);
+	return(value);
+}
+
+/* Console output exported interface. Write message to the console.  */
+
+int
+l1_serial_out( char *str, int len )
+{
+	nasid_t nasid = get_master_nasid();
+	int l1_write(l1sc_t *, char *, int, int);
+
+	if ( L1_cons_is_inited ) {
+		if ( NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module != (module_t *)0 )
+			return(l1_write(&NODEPDA(NASID_TO_COMPACT_NODEID(nasid))->module->elsc, str, len,
+#if	defined(SYNC_CONSOLE_WRITE)
+					1
+#else
+					!L1_interrupts_connected
+#endif
+							));
+	}
+	return(early_l1_serial_out(nasid, str, len, NOT_LOCKED));
+}
+
+
+/*
+ * These are the 'early' functions - when we need to do things before we have
+ * all the structs setup.
+ */
+
+static l1sc_t Early_console;		/* fake l1sc_t */
+static int Early_console_inited = 0;
+
+static void
+early_brl1_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart )
+{
+    int i;
+    brl1_sch_t *subch;
+
+    bzero( sc, sizeof( *sc ) );
+    sc->nasid = nasid;
+    sc->uart = uart;
+    sc->getc_f = (uart == BRL1_LOCALHUB_UART ? uart_getc : rtr_uart_getc);
+    sc->putc_f = (uart == BRL1_LOCALHUB_UART ? uart_putc : rtr_uart_putc);
+    sc->sol = 1;
+    subch = sc->subch;
+
+    /* initialize L1 subchannels
+     */
+
+    /* assign processor TTY channels */
+    for( i = 0; i < CPUS_PER_NODE; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_RSVD;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+
+    /* assign system TTY channel (first free subchannel after each
+     * processor's individual TTY channel has been assigned)
+     */
+    subch->use = BRL1_SUBCH_RSVD;
+    subch->packet_arrived = ATOMIC_INIT(0);
+    subch->tx_notify = NULL;
+    subch->rx_notify = NULL;
+    if( sc->uart == BRL1_LOCALHUB_UART ) {
+	static sc_cq_t x_iqp;
+
+	subch->iqp = &x_iqp;
+	ASSERT( subch->iqp );
+	cq_init( subch->iqp );
+    }
+    else {
+	/* we shouldn't be getting console input from remote UARTs */
+	subch->iqp = &sc->garbage_q;
+    }
+    subch++; i++;
+
+    /* "reserved" subchannels (0x05-0x0F); for now, throw away
+     * incoming packets
+     */
+    for( ; i < 0x10; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_FREE;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+
+    /* remaining subchannels are free */
+    for( ; i < BRL1_NUM_SUBCHANS; i++, subch++ ) {
+	subch->use = BRL1_SUBCH_FREE;
+	subch->packet_arrived = ATOMIC_INIT(0);
+	subch->tx_notify = NULL;
+	subch->rx_notify = NULL;
+	subch->iqp = &sc->garbage_q;
+    }
+}
+
+static inline l1sc_t *
+early_sc_init(nasid_t nasid)
+{
+	/* This is for early I/O */
+	if ( Early_console_inited == 0 ) {
+    		early_brl1_init(&Early_console, nasid,  BRL1_LOCALHUB_UART);
+		Early_console_inited = 1;
+	}
+	return(&Early_console);
 }
 
 #define PUTCHAR(ch) \
@@ -1487,15 +1974,34 @@
         WRITE_L1_UART_REG( nasid, REG_DAT, (ch) ); \
     }
 
-int
-l1_serial_out( char *str, int len )
+static int
+early_l1_serial_out( nasid_t nasid, char *str, int len, int lock_state )
 {
-    int sent = len;
+	int ret, sent = 0;
+	char *msg = str;
+	static int early_l1_send( nasid_t nasid, char *str, int len, int lock_state );
+
+	while ( sent < len ) {
+		ret = early_l1_send(nasid, msg, len - sent, lock_state);
+		sent += ret;
+		msg += ret;
+	}
+	return(len);
+}
+
+static inline int
+early_l1_send( nasid_t nasid, char *str, int len, int lock_state )
+{
+    int sent;
     char crc_char;
     unsigned short crc = INIT_CRC;
-    nasid_t nasid = 0; //(get_elsc())->nasid;
 
-    lock_console(nasid);
+    if( len > (BRL1_QSIZE - 1) )
+	len = (BRL1_QSIZE - 1);
+
+    sent = len;
+    if ( lock_state == NOT_LOCKED )
+    	lock_console(nasid);
 
     PUTCHAR( BRL1_FLAG_CH );
     PUTCHAR( BRL1_EVENT | SC_CONS_SYSTEM );
@@ -1531,16 +2037,9 @@
     PUTCHAR( crc_char );
     PUTCHAR( BRL1_FLAG_CH );
 
-    unlock_console(nasid);
-    return sent - len;
-}
-
-int
-l1_serial_in(void)
-{
-	static int l1_cons_getc( l1sc_t *sc );
-
-	return(l1_cons_getc(get_elsc()));
+    if ( lock_state == NOT_LOCKED )
+    	unlock_console(nasid);
+    return sent;
 }
 
 
@@ -1555,12 +2054,16 @@
  */
 
 static int
-l1_cons_poll( l1sc_t *sc )
+l1_poll( l1sc_t *sc, int mode )
 {
+    int ret;
+
     /* in case this gets called before the l1sc_t structure for the module_t
      * struct for this node is initialized (i.e., if we're called with a
      * zero l1sc_t pointer)...
      */
+
+
     if( !sc ) {
 	return 0;
     }
@@ -1569,7 +2072,9 @@
 	return 1;
     }
 
-    brl1_receive( sc );
+    ret = brl1_receive( sc, mode );
+    if ( (ret != BRL1_VALID) && (ret != BRL1_NO_MESSAGE) && (ret != BRL1_PROTOCOL) && (ret != BRL1_CRC) )
+	L1_collectibles[L1C_REC_STALLS] = ret;
 
     if( atomic_read(&sc->subch[SC_CONS_SYSTEM].packet_arrived) ) {
 	return 1;
@@ -1581,43 +2086,65 @@
 /* pull a character off of the system console queue (if one is available)
  */
 static int
-l1_cons_getc( l1sc_t *sc )
+l1_getc( l1sc_t *sc, int mode )
 {
+    unsigned long pl = 0;
     int c;
 
     brl1_sch_t *subch = &(sc->subch[SC_CONS_SYSTEM]);
     sc_cq_t *q = subch->iqp;
 
-    if( !l1_cons_poll( sc ) ) {
+    if( !l1_poll( sc, mode ) ) {
 	return 0;
     }
 
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     if( cq_empty( q ) ) {
 	atomic_set(&subch->packet_arrived, 0);
-	SUBCH_DATA_UNLOCK( subch );
+	SUBCH_DATA_UNLOCK( subch, pl );
 	return 0;
     }
     cq_rem( q, c );
     if( cq_empty( q ) )
 	atomic_set(&subch->packet_arrived, 0);
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return c;
 }
 
+/*
+ * Write a message to the L1 on the system console subchannel.
+ *
+ * Danger: don't use a non-zero value for the wait parameter unless you're
+ * someone important (like a kernel error message).
+ */
+
+int
+l1_write( l1sc_t *sc, char *msg, int len, int wait )
+{
+	int sent = 0, ret = 0;
+
+	if ( wait ) {
+		while ( sent < len ) {
+			ret = brl1_send( sc, msg, len - sent, (SC_CONS_SYSTEM | BRL1_EVENT), wait );
+			sent += ret;
+			msg += ret;
+		}
+		ret = len;
+	}
+	else {
+		ret = brl1_send( sc, msg, len, (SC_CONS_SYSTEM | BRL1_EVENT), wait );
+	}
+	return(ret);
+}
 
 /* initialize the system console subchannel
  */
 void
-l1_cons_init( l1sc_t *sc )
+l1_init(void)
 {
-    brl1_sch_t *subch = &(sc->subch[SC_CONS_SYSTEM]);
-
-    SUBCH_DATA_LOCK( subch );
-    atomic_set(&subch->packet_arrived, 0);
-    cq_init( subch->iqp );
-    SUBCH_DATA_UNLOCK( subch );
+	/* All we do now is remember that we have been called */
+	L1_cons_is_inited = 1;
 }
 
 
@@ -1637,16 +2164,18 @@
 #define L1_DBG_PRF(x)
 #endif
 
-/* sc_data_ready is called to signal threads that are blocked on 
- * l1 input.
+/*
+ * sc_data_ready is called to signal threads that are blocked on l1 input.
  */
 void
-sc_data_ready( l1sc_t *sc, int ch )
+sc_data_ready( int dummy0, void *dummy1, struct pt_regs *dummy2, l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
+
     brl1_sch_t *subch = &(sc->subch[ch]);
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     sv_signal( &(subch->arrive_sv) );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 }
 
 /* sc_open reserves a subchannel to send a request to the L1 (the
@@ -1661,9 +2190,10 @@
      * subchannel assignment.
      */
     int ch;
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
 
     /* Look for a free subchannel. Subchannels 0-15 are reserved
      * for other purposes.
@@ -1676,12 +2206,12 @@
 
     if( ch == BRL1_NUM_SUBCHANS ) {
         /* there were no subchannels available! */
-        SUBCH_UNLOCK( sc );
+        SUBCH_UNLOCK( sc, pl );
         return SC_NSUBCH;
     }
 
     subch->use = BRL1_SUBCH_RSVD;
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     atomic_set(&subch->packet_arrived, 0);
     subch->target = target;
@@ -1689,7 +2219,7 @@
     sv_init( &(subch->arrive_sv), &(subch->data_lock), SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */);
     subch->tx_notify = NULL;
     subch->rx_notify = sc_data_ready;
-    subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
+    subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
 				   NASID_TO_COMPACT_NODEID(sc->nasid) );
     ASSERT( subch->iqp );
     cq_init( subch->iqp );
@@ -1703,29 +2233,31 @@
 int
 sc_close( l1sc_t *sc, int ch )
 {
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
     subch = &(sc->subch[ch]);
     if( subch->use != BRL1_SUBCH_RSVD ) {
         /* we're trying to close a subchannel that's not open */
+	SUBCH_UNLOCK( sc, pl );
         return SC_NOPEN;
     }
 
     atomic_set(&subch->packet_arrived, 0);
     subch->use = BRL1_SUBCH_FREE;
 
-    SUBCH_DATA_LOCK( subch );
     sv_broadcast( &(subch->arrive_sv) );
     sv_destroy( &(subch->arrive_sv) );
-    SUBCH_DATA_UNLOCK( subch );
     spin_lock_destroy( &(subch->data_lock) );
 
     ASSERT( subch->iqp && (subch->iqp != &sc->garbage_q) );
-    kmem_free( subch->iqp, sizeof(sc_cq_t) );
+    snia_kmem_free( subch->iqp, sizeof(sc_cq_t) );
     subch->iqp = &sc->garbage_q;
+    subch->tx_notify = NULL;
+    subch->rx_notify = brl1_discard_packet;
 
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     return SC_SUCCESS;
 }
@@ -2033,11 +2565,10 @@
 
     /* Verify that this is an open subchannel
      */
-    if( sc->subch[ch].use == BRL1_SUBCH_FREE )
-    {
+    if( sc->subch[ch].use == BRL1_SUBCH_FREE ) {
         return SC_NOPEN;
     }
-       
+
     type_and_subch = (BRL1_REQUEST | ((u_char)ch));
     result = brl1_send( sc, msg, len, type_and_subch, wait );
 
@@ -2115,6 +2646,7 @@
 sc_recv_poll( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block )
 {
     int is_msg = 0;
+    unsigned long pl = 0;
     brl1_sch_t *subch = &(sc->subch[ch]);
 
     rtc_time_t exp_time = rtc_time() + block;
@@ -2127,7 +2659,7 @@
 
         /* kick the next lower layer and see if it pulls anything in
          */
-	brl1_receive( sc );
+	brl1_receive( sc, SERIAL_POLLED_MODE );
 	is_msg = atomic_read(&subch->packet_arrived);
 
     } while( block && !is_msg && (rtc_time() < exp_time) );
@@ -2137,9 +2669,9 @@
 	return( SC_NMSG );
     }
 
-    SUBCH_DATA_LOCK( subch );
+    SUBCH_DATA_LOCK( subch, pl );
     subch_pull_msg( subch, msg, len );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return( SC_SUCCESS );
 }
@@ -2156,10 +2688,11 @@
 sc_recv_intr( l1sc_t *sc, int ch, char *msg, int *len, uint64_t block )
 {
     int is_msg = 0;
+    unsigned long pl = 0;
     brl1_sch_t *subch = &(sc->subch[ch]);
 
     do {
-	SUBCH_DATA_LOCK(subch);
+	SUBCH_DATA_LOCK(subch, pl);
 	is_msg = atomic_read(&subch->packet_arrived);
 	if( !is_msg && block ) {
 	    /* wake me when you've got something */
@@ -2178,12 +2711,12 @@
 
     if( !is_msg ) {
 	/* no message and we didn't care to wait for one */
-	SUBCH_DATA_UNLOCK( subch );
+	SUBCH_DATA_UNLOCK( subch, pl );
 	return( SC_NMSG );
     }
 
     subch_pull_msg( subch, msg, len );
-    SUBCH_DATA_UNLOCK( subch );
+    SUBCH_DATA_UNLOCK( subch, pl );
 
     return( SC_SUCCESS );
 }
@@ -2206,7 +2739,7 @@
  * rewriting of the L1 command interface anyway.)
  */
 #define __RETRIES	50
-#define __WAIT_SEND	( sc->uart != BRL1_LOCALUART )
+#define __WAIT_SEND	1	// ( sc->uart != BRL1_LOCALHUB_UART )
 #define __WAIT_RECV	10000000
 
 
@@ -2237,13 +2770,10 @@
     }
     
     /* block on sc_recv_* */
-#ifdef LATER
-    if( sc->uart == BRL1_LOCALUART ) {
+    if( (sc->uart == BRL1_LOCALHUB_UART) && L1_interrupts_connected ) {
 	return( sc_recv_intr( sc, ch, resp, len, __WAIT_RECV ) );
     }
-    else
-#endif	/* LATER */
-    {
+    else {
 	return( sc_recv_poll( sc, ch, resp, len, __WAIT_RECV ) );
     }
 #endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
@@ -2254,6 +2784,7 @@
  * delayed until the send buffer clears.  sc_command should be used instead
  * under most circumstances.
  */
+
 int
 sc_command_kern( l1sc_t *sc, int ch, char *cmd, char *resp, int *len )
 {
@@ -2282,6 +2813,7 @@
  * Returns 1 if input is available on the given queue,
  * 0 otherwise.
  */
+
 int
 sc_poll( l1sc_t *sc, int ch )
 {
@@ -2290,7 +2822,7 @@
     if( atomic_read(&subch->packet_arrived) )
 	return 1;
 
-    brl1_receive( sc );
+    brl1_receive( sc, SERIAL_POLLED_MODE );
 
     if( atomic_read(&subch->packet_arrived) )
 	return 1;
@@ -2298,8 +2830,8 @@
     return 0;
 }
 
-/* for now, sc_init just calls brl1_init
- */
+/* for now, sc_init just calls brl1_init */
+
 void
 sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart )
 {
@@ -2311,7 +2843,7 @@
  * network's environmental monitor tasks.
  */
 
-#ifdef LINUX_KERNEL_THREADS
+#if	defined(LINUX_KERNEL_THREADS)
 
 static void
 sc_dispatch_env_event( uint code, int argc, char *args, int maxlen )
@@ -2366,14 +2898,12 @@
 	     i++ );
     }
 }
-#endif	/* LINUX_KERNEL_THREADS */
 
 
 /* sc_event waits for events to arrive from the system controller, and
  * prints appropriate messages to the syslog.
  */
 
-#ifdef LINUX_KERNEL_THREADS
 static void
 sc_event( l1sc_t *sc, int ch )
 {
@@ -2394,7 +2924,7 @@
 	 */
 	result = sc_recv_intr( sc, ch, event, &event_len, 1 );
 	if( result != SC_SUCCESS ) {
-	    PRINT_WARNING("Error receiving sysctl event on nasid %d\n",
+	    printk(KERN_WARNING  "Error receiving sysctl event on nasid %d\n",
 		     sc->nasid );
 	}
 	else {
@@ -2438,53 +2968,50 @@
 	
     }			
 }
-#endif	/* LINUX_KERNEL_THREADS */
 
 /* sc_listen sets up a service thread to listen for incoming events.
  */
+
 void
 sc_listen( l1sc_t *sc )
 {
     int result;
+    unsigned long pl = 0;
     brl1_sch_t *subch;
 
     char        msg[BRL1_QSIZE];
     int         len;    /* length of message being sent */
     int         ch;     /* system controller subchannel used */
 
-#ifdef LINUX_KERNEL_THREADS
     extern int msc_shutdown_pri;
-#endif
 
     /* grab the designated "event subchannel" */
-    SUBCH_LOCK( sc );
+    SUBCH_LOCK( sc, pl );
     subch = &(sc->subch[BRL1_EVENT_SUBCH]);
     if( subch->use != BRL1_SUBCH_FREE ) {
-	SUBCH_UNLOCK( sc );
-	PRINT_WARNING("sysctl event subchannel in use! "
+	SUBCH_UNLOCK( sc, pl );
+	printk(KERN_WARNING  "sysctl event subchannel in use! "
 		 "Not monitoring sysctl events.\n" );
 	return;
     }
     subch->use = BRL1_SUBCH_RSVD;
-    SUBCH_UNLOCK( sc );
+    SUBCH_UNLOCK( sc, pl );
 
     atomic_set(&subch->packet_arrived, 0);
-    subch->target = BRL1_LOCALUART;
+    subch->target = BRL1_LOCALHUB_UART;
     spin_lock_init( &(subch->data_lock) );
     sv_init( &(subch->arrive_sv), &(subch->data_lock), SV_MON_SPIN | SV_ORDER_FIFO /* | SV_INTS */);
     subch->tx_notify = NULL;
     subch->rx_notify = sc_data_ready;
-    subch->iqp = kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
+    subch->iqp = snia_kmem_zalloc_node( sizeof(sc_cq_t), KM_NOSLEEP,
 				   NASID_TO_COMPACT_NODEID(sc->nasid) );
     ASSERT( subch->iqp );
     cq_init( subch->iqp );
 
-#ifdef LINUX_KERNEL_THREADS
     /* set up a thread to listen for events */
     sthread_create( "sysctl event handler", 0, 0, 0, msc_shutdown_pri,
 		    KT_PS, (st_func_t *) sc_event,
 		    (void *)sc, (void *)(uint64_t)BRL1_EVENT_SUBCH, 0, 0 );
-#endif
 
     /* signal the L1 to begin sending events */
     bzero( msg, BRL1_QSIZE );
@@ -2522,276 +3049,8 @@
 	
 err_return:
     /* there was a problem; complain */
-    PRINT_WARNING("failed to set sysctl event-monitoring subchannel.  "
+    printk(KERN_WARNING  "failed to set sysctl event-monitoring subchannel.  "
 	     "Sysctl events will not be monitored.\n" );
 }
 
-
-/*********************************************************************
- * elscuart functions.  These provide a uart-like interface to the
- * bedrock/l1 protocol console channels.  They are similar in form
- * and intent to the elscuart_* functions defined for SN0 in elsc.c.
- *
- */
-
-int _elscuart_flush( l1sc_t *sc );
-
-/* Leave room in queue for CR/LF */
-#define ELSCUART_LINE_MAX       (BRL1_QSIZE - 2)
-
-
-/*
- * _elscuart_putc provides an entry point to the L1 interface driver;
- * writes a single character to the output queue.  Flushes at the
- * end of each line, and translates newlines into CR/LF.
- *
- * The kernel should generally use l1_cons_write instead, since it assumes
- * buffering, translation, prefixing, etc. are done at a higher
- * level.
- *
- */
-int
-_elscuart_putc( l1sc_t *sc, int c )
-{
-    sc_cq_t *q;
-    
-    q = &(sc->oq[ MAP_OQ(L1_ELSCUART_SUBCH(get_myid())) ]);
-
-    if( c != '\n' && c != '\r' && cq_used(q) >= ELSCUART_LINE_MAX ) {
-        cq_add( q, '\r' );
-        cq_add( q, '\n' );
-         _elscuart_flush( sc );
-        sc->sol = 1;
-    }
-
-    if( sc->sol && c != '\r' ) {
-        char            prefix[16], *s;
-
-        if( cq_room( q ) < 8 && _elscuart_flush(sc) < 0 )
-        {
-            return -1;
-        }
-	
-	if( sc->verbose )
-	{
-#ifdef  SUPPORT_PRINTING_M_FORMAT
-	    sprintf( prefix,
-		     "%c %d%d%d %M:",
-		     'A' + get_myid(),
-		     sc->nasid / 100,
-		     (sc->nasid / 10) % 10,
-		     sc->nasid / 10,
-		     sc->modid );
-#else
-	    sprintf( prefix,
-		     "%c %d%d%d 0x%x:",
-		     'A' + get_myid(),
-		     sc->nasid / 100,
-		     (sc->nasid / 10) % 10,
-		     sc->nasid / 10,
-		     sc->modid );
-#endif
-	    
-	    for( s = prefix; *s; s++ )
-		cq_add( q, *s );
-	}	    
-	sc->sol = 0;
-
-    }
-
-    if( cq_room( q ) < 2 && _elscuart_flush(sc) < 0 )
-    {
-        return -1;
-    }
-
-    if( c == '\n' ) {
-        cq_add( q, '\r' );
-        sc->sol = 1;
-    }
-
-    cq_add( q, (u_char) c );
-
-    if( c == '\n' ) {
-        /* flush buffered line */
-        if( _elscuart_flush( sc ) < 0 )
-        {
-            return -1;
-        }
-    }
-
-    if( c== '\r' )
-    {
-        sc->sol = 1;
-    }
-
-    return 0;
-}
-
-
-/*
- * _elscuart_getc reads a character from the input queue.  This
- * routine blocks.
- */
-int
-_elscuart_getc( l1sc_t *sc )
-{
-    int r;
-
-    while( (r = _elscuart_poll( sc )) == 0 );
-
-    if( r < 0 ) {
-	/* some error occurred */
-	return r;
-    }
-
-    return _elscuart_readc( sc );
-}
-
-
-
-/*
- * _elscuart_poll returns 1 if characters are ready for the
- * calling processor, 0 if they are not
- */
-int
-_elscuart_poll( l1sc_t *sc )
-{
-    int result;
-
-    if( sc->cons_listen ) {
-        result = l1_cons_poll( sc );
-        if( result )
-            return result;
-    }
-
-    return sc_poll( sc, L1_ELSCUART_SUBCH(get_myid()) );
-}
-
-
-
-/* _elscuart_readc is to be used only when _elscuart_poll has
- * indicated that a character is waiting.  Pulls a character
- * of this processor's console queue and returns it.
- *
- */
-int
-_elscuart_readc( l1sc_t *sc )
-{
-    int c;
-    sc_cq_t *q;
-    brl1_sch_t *subch;
-
-    if( sc->cons_listen ) {
-	subch = &(sc->subch[ SC_CONS_SYSTEM ]);
-	q = subch->iqp;
-	
-	SUBCH_DATA_LOCK( subch );
-        if( !cq_empty( q ) ) {
-            cq_rem( q, c );
-	    if( cq_empty( q ) ) {
-		atomic_set(&subch->packet_arrived, 0);
-	    }
-	    SUBCH_DATA_UNLOCK( subch );
-            return c;
-        }
-	SUBCH_DATA_UNLOCK( subch );
-    }
-
-    subch = &(sc->subch[ L1_ELSCUART_SUBCH(get_myid()) ]);
-    q = subch->iqp;
-
-    SUBCH_DATA_LOCK( subch );
-    if( cq_empty( q ) ) {
-	SUBCH_DATA_UNLOCK( subch );
-        return -1;
-    }
-
-    cq_rem( q, c );
-    if( cq_empty ( q ) ) {
-	atomic_set(&subch->packet_arrived, 0);
-    }
-    SUBCH_DATA_UNLOCK( subch );
-
-    return c;
-}
-
-
-/*
- * _elscuart_flush flushes queued output to the L1.
- * This routine blocks until the queue is flushed.
- */
-int
-_elscuart_flush( l1sc_t *sc )
-{
-    int r, n;
-    char buf[BRL1_QSIZE];
-    sc_cq_t *q = &(sc->oq[ MAP_OQ(L1_ELSCUART_SUBCH(get_myid())) ]);
-
-    while( (n = cq_used(q)) ) {
-
-        /* buffer queue contents */
-        r = BRL1_QSIZE - q->opos;
-
-        if( n > r ) {
-            BCOPY( q->buf + q->opos, buf, r  );
-            BCOPY( q->buf, buf + r, n - r  );
-        } else {
-            BCOPY( q->buf + q->opos, buf, n  );
-        }
-
-        /* attempt to send buffer contents */
-        r = brl1_send( sc, buf, cq_used( q ), 
-		       (BRL1_EVENT | L1_ELSCUART_SUBCH(get_myid())), 1 );
-
-        /* if no error, dequeue the sent characters; otherwise,
-         * return the error
-         */
-        if( r >= SC_SUCCESS ) {
-            q->opos = (q->opos + r) % BRL1_QSIZE;
-        }
-        else {
-            return r;
-        }
-    }
-
-    return 0;
-}
-
-
-
-/* _elscuart_probe returns non-zero if the L1 (and
- * consequently the elscuart) can be accessed
- */
-int
-_elscuart_probe( l1sc_t *sc )
-{
-#ifndef CONFIG_SERIAL_SGI_L1_PROTOCOL
-    return 0;
-#else
-    char ver[BRL1_QSIZE];
-    extern int elsc_version( l1sc_t *, char * );
-
-    if ( IS_RUNNING_ON_SIMULATOR() )
-    	return 0;
-    return( elsc_version(sc, ver) >= 0 );
-#endif /* CONFIG_SERIAL_SGI_L1_PROTOCOL */
-}
-
-
-
-/* _elscuart_init zeroes out the l1sc_t console
- * queues for this processor's console subchannel.
- */
-void
-_elscuart_init( l1sc_t *sc )
-{
-    brl1_sch_t *subch = &sc->subch[L1_ELSCUART_SUBCH(get_myid())];
-
-    SUBCH_DATA_LOCK(subch);
-
-    atomic_set(&subch->packet_arrived, 0);
-    cq_init( subch->iqp );
-    cq_init( &sc->oq[MAP_OQ(L1_ELSCUART_SUBCH(get_myid()))] );
-
-    SUBCH_DATA_UNLOCK(subch);
-}
+#endif	/* LINUX_KERNEL_THREADS */
diff -Nru a/arch/ia64/sn/io/l1_command.c b/arch/ia64/sn/io/l1_command.c
--- a/arch/ia64/sn/io/l1_command.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/l1_command.c	Fri Mar 15 17:51:03 2002
@@ -4,20 +4,20 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
  */ 
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/eeprom.h>
-#include <asm/sn/ksys/i2c.h>
 #include <asm/sn/router.h>
 #include <asm/sn/module.h>
 #include <asm/sn/ksys/l1.h>
@@ -27,7 +27,6 @@
 #define ELSC_TIMEOUT	1000000		/* ELSC response timeout (usec) */
 #define LOCK_TIMEOUT	5000000		/* Hub lock timeout (usec) */
 
-#define LOCAL_HUB	LOCAL_HUB_ADDR
 #define LD(x)		(*(volatile uint64_t *)(x))
 #define SD(x, v)	(LD(x) = (uint64_t) (v))
 
@@ -75,7 +74,7 @@
 
 void elsc_init(elsc_t *e, nasid_t nasid)
 {
-    sc_init((l1sc_t *)e, nasid, BRL1_LOCALUART);
+    sc_init((l1sc_t *)e, nasid, BRL1_LOCALHUB_UART);
 }
 
 
@@ -1376,85 +1375,4 @@
     sprintf( result, "%d.%d.%d", major, minor, bugfix );
 
     return 0;
-}
-
-
-
-/* elscuart routines 
- *
- * Most of the elscuart functionality is implemented in l1.c.  The following
- * is directly "recycled" from elsc.c.
- */
-
-
-/*
- * _elscuart_puts
- */
-
-int _elscuart_puts(elsc_t *e, char *s)
-{
-    int			c;
-
-    if (s == 0)
-	s = "<NULL>";
-
-    while ((c = LBYTE(s)) != 0) {
-	if (_elscuart_putc(e, c) < 0)
-	    return -1;
-	s++;
-    }
-
-    return 0;
-}
-
-
-/*
- * elscuart wrapper routines
- *
- *   The following routines are similar to their counterparts in l1.c,
- *   except instead of taking an elsc_t pointer directly, they call
- *   a global routine "get_elsc" to obtain the pointer.
- *   This is useful when the elsc is employed for stdio.
- */
-
-int elscuart_probe(void)
-{
-    return _elscuart_probe(get_elsc());
-}
-
-void elscuart_init(void *init_data)
-{
-    _elscuart_init(get_elsc());
-    /* dummy variable included for driver compatability */
-    init_data = init_data;
-}
-
-int elscuart_poll(void)
-{
-    return _elscuart_poll(get_elsc());
-}
-
-int elscuart_readc(void)
-{
-    return _elscuart_readc(get_elsc());
-}
-
-int elscuart_getc(void)
-{
-    return _elscuart_getc(get_elsc());
-}
-
-int elscuart_puts(char *s)
-{
-    return _elscuart_puts(get_elsc(), s);
-}
-
-int elscuart_putc(int c)
-{
-    return _elscuart_putc(get_elsc(), c);
-}
-
-int elscuart_flush(void)
-{
-    return _elscuart_flush(get_elsc());
 }
diff -Nru a/arch/ia64/sn/io/labelcl.c b/arch/ia64/sn/io/labelcl.c
--- a/arch/ia64/sn/io/labelcl.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/labelcl.c	Fri Mar 15 17:51:02 2002
@@ -1,21 +1,10 @@
 /*  labelcl - SGI's Hwgraph Compatibility Layer.
-
-    This library is free software; you can redistribute it and/or
-    modify it under the terms of the GNU Library General Public
-    License as published by the Free Software Foundation; either
-    version 2 of the License, or (at your option) any later version.
-
-    This library is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-    Library General Public License for more details.
-
-    You should have received a copy of the GNU Library General Public
-    License along with this library; if not, write to the Free
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
-
-    Colin Ngam may be reached by email at cngam@sgi.com
-
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
 */
 
 #include <linux/types.h>
@@ -286,7 +275,7 @@
 		if (!strcmp(info_name, old_label_list[i].name)) {
 			/* Not allowed to add duplicate labelled info names. */
 			kfree(new_label_list);
-			printk(KERN_WARNING "labelcl_info_add_LBL: Duplicate label name %s for vertex 0x%p\n", info_name, de);
+			printk(KERN_WARNING "labelcl_info_add_LBL: Duplicate label name %s for vertex 0x%p\n", info_name, (void *)de);
 			return(-1);
 		}
 		new_label_list[i] = old_label_list[i]; /* structure copy */
diff -Nru a/arch/ia64/sn/io/mem_refcnt.c b/arch/ia64/sn/io/mem_refcnt.c
--- a/arch/ia64/sn/io/mem_refcnt.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,222 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#include <linux/types.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/hcl_util.h>
-#include <asm/sn/nodepda.h>
-#include <asm/sn/hubspc.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/mem_refcnt.h>
-#include <asm/sn/hwcntrs.h>
-// From numa_hw.h
-
-#define MIGR_COUNTER_MAX_GET(nodeid) \
-        (NODEPDA_MCD((nodeid))->migr_system_kparms.migr_threshold_reference)
-/*
- * Get the Absolute Theshold
- */
-#define MIGR_THRESHOLD_ABS_GET(nodeid) ( \
-        MD_MIG_VALUE_THRESH_GET(COMPACT_TO_NASID_NODEID(nodeid)))
-/*
- * Get the current Differential Threshold
- */
-#define MIGR_THRESHOLD_DIFF_GET(nodeid) \
-        (NODEPDA_MCD(nodeid)->migr_as_kparms.migr_base_threshold)
-
-#define NUM_OF_HW_PAGES_PER_SW_PAGE()   (NBPP / MD_PAGE_SIZE)
-
-// #include "migr_control.h"
-
-int
-mem_refcnt_attach(devfs_handle_t hub)
-{
-        devfs_handle_t refcnt_dev;
-        
-        hwgraph_char_device_add(hub,
-                                "refcnt",
-                                "hubspc_", 
-				&refcnt_dev);
-        device_info_set(refcnt_dev, (void*)(ulong)HUBSPC_REFCOUNTERS);
-
-        return (0);
-}
-
-
-/*ARGSUSED*/
-int
-mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
-{
-        cnodeid_t node;
-
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(*devp) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(*devp);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        if (NODEPDA(node)->migr_refcnt_counterbuffer == NULL) {
-                return (ENODEV);
-        }
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != (size_t)0 );
-
-        return (0);
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
-{
-        return 0;
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
-{
-        cnodeid_t node;
-        int errcode;
-        char* buffer;
-        size_t blen;
-        
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(dev) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(dev);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
-
-        /*
-         * XXXX deal with prot's somewhere around here....
-         */
-
-        buffer = NODEPDA(node)->migr_refcnt_counterbuffer;
-        blen = NODEPDA(node)->migr_refcnt_cbsize;
-
-        /*
-         * Force offset to be a multiple of sizeof(refcnt_t)
-         * We round up.
-         */
-
-        off = (((off - 1)/sizeof(refcnt_t)) + 1) * sizeof(refcnt_t);
-
-        if ( ((buffer + blen) - (buffer + off + len)) < 0 ) {
-                return (EPERM);
-        }
-
-        errcode = v_mapphys(vt,
-                            buffer + off,
-                            len);
-
-        return errcode;
-}
-
-/*ARGSUSED*/
-int
-mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt)
-{
-        return 0;
-}
-
-/* ARGSUSED */
-int
-mem_refcnt_ioctl(devfs_handle_t dev,
-                 int cmd,
-                 void *arg,
-                 int mode,
-                 cred_t *cred_p,
-                 int *rvalp)
-{
-        cnodeid_t node;
-        int errcode;
-	extern int numnodes;
-        
-        ASSERT( (hubspc_subdevice_t)(ulong)device_info_get(dev) == HUBSPC_REFCOUNTERS );
-
-        node = master_node_get(dev);
-
-        ASSERT( (node >= 0) && (node < numnodes) );
-
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
-        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
-        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
-
-        errcode = 0;
-        
-        switch (cmd) {
-        case RCB_INFO_GET:
-        {
-                rcb_info_t rcb;
-                
-                rcb.rcb_len = NODEPDA(node)->migr_refcnt_cbsize;
-                
-                rcb.rcb_sw_sets = NODEPDA(node)->migr_refcnt_numsets;
-                rcb.rcb_sw_counters_per_set = numnodes;
-                rcb.rcb_sw_counter_size = sizeof(refcnt_t);
-
-                rcb.rcb_base_pages = NODEPDA(node)->migr_refcnt_numsets /
-                                     NUM_OF_HW_PAGES_PER_SW_PAGE();  
-                rcb.rcb_base_page_size = NBPP;
-                rcb.rcb_base_paddr = ctob(slot_getbasepfn(node, 0));
-                
-                rcb.rcb_cnodeid = node;
-                rcb.rcb_granularity = MD_PAGE_SIZE;
-#ifdef LATER
-                rcb.rcb_hw_counter_max = MIGR_COUNTER_MAX_GET(node);
-                rcb.rcb_diff_threshold = MIGR_THRESHOLD_DIFF_GET(node);
-#endif
-                rcb.rcb_abs_threshold = MIGR_THRESHOLD_ABS_GET(node);
-                rcb.rcb_num_slots = node_getnumslots(node);
-
-                if (COPYOUT(&rcb, arg, sizeof(rcb_info_t))) {
-                        errcode = EFAULT;
-                }
-
-                break;
-        }
-        case RCB_SLOT_GET:
-        {
-                rcb_slot_t slot[MAX_MEM_SLOTS];
-                int s;
-                int nslots;
-
-                nslots = node_getnumslots(node);
-                ASSERT(nslots <= MAX_MEM_SLOTS);
-                for (s = 0; s < nslots; s++) {
-                        slot[s].base = (uint64_t)ctob(slot_getbasepfn(node, s));
-#ifdef LATER
-                        slot[s].size  = (uint64_t)ctob(slot_getsize(node, s));
-#else
-                        slot[s].size  = (uint64_t)1;
-#endif
-                }
-                if (COPYOUT(&slot[0], arg, nslots * sizeof(rcb_slot_t))) {
-                        errcode = EFAULT;
-                }
-                
-                *rvalp = nslots;
-                break;
-        }
-                
-        default:
-                errcode = EINVAL;
-                break;
-
-        }
-        
-        return errcode;
-}
diff -Nru a/arch/ia64/sn/io/ml_SN_init.c b/arch/ia64/sn/io/ml_SN_init.c
--- a/arch/ia64/sn/io/ml_SN_init.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/ml_SN_init.c	Fri Mar 15 17:51:01 2002
@@ -4,37 +4,30 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
+#include <linux/bootmem.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
 #include <asm/sn/sn_private.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_cpuid.h>
-#include <asm/sn/synergy.h>
-
-
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/ip27config.h>
-#include <asm/sn/sn1/hubdev.h>
-#include <asm/sn/sn1/sn1.h>
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
+#include <asm/sn/snconfig.h>
 
 extern int numcpus;
 extern char arg_maxnodes[];
 extern cpuid_t master_procid;
-extern void * kmem_alloc_node(register size_t, register int , cnodeid_t);
+#if defined(CONFIG_IA64_SGI_SN1)
 extern synergy_da_t    *Synergy_da_indr[];
+#endif
 
 extern int hasmetarouter;
 
@@ -45,18 +38,8 @@
 
 extern xwidgetnum_t hub_widget_id(nasid_t);
 
-static int	fine_mode = 0;
-
-static cnodemask_t	hub_init_mask;	/* Mask of cpu in a node doing init */
-static volatile cnodemask_t hub_init_done_mask;
-					/* Node mask where we wait for
-					 * per hub initialization
-					 */
-spinlock_t		hub_mask_lock;  /* Lock for hub_init_mask above. */
-
 extern int valid_icache_reasons;	/* Reasons to flush the icache */
 extern int valid_dcache_reasons;	/* Reasons to flush the dcache */
-extern int numnodes;
 extern u_char miniroot;
 extern volatile int	need_utlbmiss_patch;
 extern void iograph_early_init(void);
@@ -83,20 +66,6 @@
 		 */ 
 		master_nasid = get_nasid();
 		set_master_bridge_base();
-		FIXME("mlreset: Enable when we support ioc3 ..");
-#ifdef	LATER
-		if (get_console_nasid() == master_nasid) 
-			/* Set up the IOC3 */
-			ioc3_mlreset((ioc3_cfg_t *)KL_CONFIG_CH_CONS_INFO(master_nasid)->config_base,
-				     (ioc3_mem_t *)KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base);
-
-		/*
-		 * Initialize Master nvram base.
-		 */
-		nvram_baseinit();
-
-		fine_mode = is_fine_dirmode();
-#endif /* LATER */
 
 		/* We're the master processor */
 		master_procid = smp_processor_id();
@@ -108,75 +77,12 @@
 		 */
 		ASSERT_ALWAYS(master_nasid == get_nasid());
 
-#ifdef	LATER
-
-	/*
-	 * Activate when calias is implemented.
-	 */
-		/* Set all nodes' calias sizes to 8k */
-		for (i = 0; i < maxnodes; i++) {
-			nasid_t nasid;
-			int	sn;
-
-			nasid = COMPACT_TO_NASID_NODEID(i);
-
-			/*
-			 * Always have node 0 in the region mask, otherwise CALIAS accesses
-			 * get exceptions since the hub thinks it is a node 0 address.
-			 */
-			for (sn=0; sn<NUM_SUBNODES; sn++) {
-				REMOTE_HUB_PI_S(nasid, sn, PI_REGION_PRESENT, (region_mask | 1));
-				REMOTE_HUB_PI_S(nasid, sn, PI_CALIAS_SIZE, PI_CALIAS_SIZE_8K);
-			}
-
-			/*
-			 * Set up all hubs to havew a big window pointing at
-			 * widget 0.
-			 * Memory mode, widget 0, offset 0
-			 */
-			REMOTE_HUB_S(nasid, IIO_ITTE(SWIN0_BIGWIN),
-				((HUB_PIO_MAP_TO_MEM << IIO_ITTE_IOSP_SHIFT) |
-				(0 << IIO_ITTE_WIDGET_SHIFT)));
-		}
-#endif /* LATER */
-
-		/* Set up the hub initialization mask and init the lock */
-		CNODEMASK_CLRALL(hub_init_mask);
-		CNODEMASK_CLRALL(hub_init_done_mask);
-
-		spin_lock_init(&hub_mask_lock);
-
 		/* early initialization of iograph */
 		iograph_early_init();
 
 		/* Initialize Hub Pseudodriver Management */
 		hubdev_init();
 
-#ifdef	LATER
-		/*
-		 * Our IO system doesn't require cache writebacks.  Set some
-		 * variables appropriately.
-		 */
-		cachewrback = 0;
-		valid_icache_reasons &= ~(CACH_AVOID_VCES | CACH_IO_COHERENCY);
-		valid_dcache_reasons &= ~(CACH_AVOID_VCES | CACH_IO_COHERENCY);
-
-		/*
-		 * make sure we are running with the right rev of chips
-		 */
-		verify_snchip_rev();
-
-		/*
-                 * Since we've wiped out memory at this point, we
-                 * need to reset the ARCS vector table so that it
-                 * points to appropriate functions in the kernel
-                 * itself.  In this way, we can maintain the ARCS
-                 * vector table conventions without having to actually
-                 * keep redundant PROM code in memory.
-                 */
-		he_arcs_set_vectors();
-#endif /* LATER */
-
 	} else { /* slave != 0 */
 		/*
 		 * This code is performed ONLY by slave processors.
@@ -193,34 +99,17 @@
 void init_platform_nodepda(nodepda_t *npda, cnodeid_t node)
 {
 	hubinfo_t hubinfo;
+#ifdef CONFIG_IA64_SGI_SN1
 	int	  sn;
-	cnodeid_t i;
-	ushort *numcpus_p;
+#endif
 
 	extern void router_map_init(nodepda_t *);
 	extern void router_queue_init(nodepda_t *,cnodeid_t);
 	extern void intr_init_vecblk(nodepda_t *, cnodeid_t, int);
 
-#if defined(DEBUG)
-	extern spinlock_t	intr_dev_targ_map_lock;
-	extern uint64_t 	intr_dev_targ_map_size;
-
-	/* Initialize the lock to access the device - target cpu mapping
-	 * table. This table is explicitly for debugging purposes only and
-	 * to aid the "intrmap" idbg command
-	 */
-	if (node == 0) {
-		/* Make sure we do this only once .
-		 * There is always a cnode 0 present.
-		 */
-		intr_dev_targ_map_size = 0;
-		spin_lock_init(&intr_dev_targ_map_lock);
-	}
-#endif	/* DEBUG */
 	/* Allocate per-node platform-dependent data */
-	hubinfo = (hubinfo_t)kmem_alloc_node(sizeof(struct hubinfo_s), GFP_ATOMIC, node);
+	hubinfo = (hubinfo_t)alloc_bootmem_node(NODE_DATA(node), sizeof(struct hubinfo_s));
 
-	ASSERT_ALWAYS(hubinfo);
 	npda->pdinfo = (void *)hubinfo;
 	hubinfo->h_nodepda = npda;
 	hubinfo->h_cnodeid = node;
@@ -230,92 +119,37 @@
 
 	hubinfo->h_widgetid = hub_widget_id(hubinfo->h_nasid);
 	npda->xbow_peer = INVALID_NASID;
-	/* Initialize the linked list of
+
+	/* 
+	 * Initialize the linked list of
 	 * router info pointers to the dependent routers
 	 */
 	npda->npda_rip_first = NULL;
-	/* npda_rip_last always points to the place
+
+	/*
+	 * npda_rip_last always points to the place
 	 * where the next element is to be inserted
 	 * into the list 
 	 */
 	npda->npda_rip_last = &npda->npda_rip_first;
-	npda->dependent_routers = 0;
 	npda->module_id = INVALID_MODULE;
 
+#ifdef CONFIG_IA64_SGI_SN1
 	/*
-	 * Initialize the subnodePDA.
-	 */
+	* Initialize the interrupts.
+	* On sn2, this is done at pci init time,
+	* because sn2 needs the cpus checked in
+	* when it initializes interrupts.  This is
+	* so we don't see all the nodes as headless.
+	*/
 	for (sn=0; sn<NUM_SUBNODES; sn++) {
-		SNPDA(npda,sn)->prof_count = 0;
-		SNPDA(npda,sn)->next_prof_timeout = 0;
 		intr_init_vecblk(npda, node, sn);
 	}
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-	npda->vector_unit_busy = 0;
-
-	spin_lock_init(&npda->vector_lock);
 	mutex_init_locked(&npda->xbow_sema); /* init it locked? */
-	spin_lock_init(&npda->fprom_lock);
 
-	spin_lock_init(&npda->node_utlbswitchlock);
-	npda->ni_error_print = 0;
 #ifdef	LATER
-	if (need_utlbmiss_patch) {
-		npda->node_need_utlbmiss_patch = 1;
-		npda->node_utlbmiss_patched = 1;
-	}
-#endif
-
-	/*
-	 * Clear out the nasid mask.
-	 */
-	for (i = 0; i < NASID_MASK_BYTES; i++)
-		npda->nasid_mask[i] = 0;
-
-	for (i = 0; i < numnodes; i++) {
-		nasid_t nasid = COMPACT_TO_NASID_NODEID(i);
-
-		/* Set my mask bit */
-		npda->nasid_mask[nasid / 8] |= (1 << nasid % 8);
-	}
-
-#ifdef	LATER
-	npda->node_first_cpu = get_cnode_cpu(node);
-#endif
-
-	if (npda->node_first_cpu != CPU_NONE) {
-		/*
-		 * Count number of cpus only if first CPU is valid.
-		 */
-		numcpus_p = &npda->node_num_cpus;
-		*numcpus_p = 0;
-		for (i = npda->node_first_cpu; i < MAXCPUS; i++) {
-			if (CPUID_TO_COMPACT_NODEID(i) != node)
-			    break;
-			else
-			    (*numcpus_p)++;
-		}
-	} else {
-		npda->node_num_cpus = 0; 
-	}
-
-	/* Allocate memory for the dump stack on each node 
-	 * This is useful during nmi handling since we
-	 * may not be guaranteed shared memory at that time
-	 * which precludes depending on a global dump stack
-	 */
-#ifdef	LATER
-	npda->dump_stack = (uint64_t *)kmem_zalloc_node(DUMP_STACK_SIZE,VM_NOSLEEP,
-							  node);
-	ASSERT_ALWAYS(npda->dump_stack);
-	ASSERT(npda->dump_stack);
-#endif
-	/* Initialize the counter which prevents
-	 * both the cpus on a node to proceed with nmi
-	 * handling.
-	 */
-#ifdef	LATER
-	npda->dump_count = 0;
 
 	/* Setup the (module,slot) --> nic mapping for all the routers
 	 * in the system. This is useful during error handling when
@@ -325,17 +159,9 @@
 
 	/* Allocate memory for the per-node router traversal queue */
 	router_queue_init(npda,node);
-	npda->sbe_info = kmem_zalloc_node_hint(sizeof (sbe_info_t), 0, node);
+	npda->sbe_info = alloc_bootmem_node(NODE_DATA(node), sizeof (sbe_info_t));
 	ASSERT(npda->sbe_info);
 
-#ifdef CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-	/*
-	 * Initialize bte info pointers to NULL
-	 */
-	for (i = 0; i < BTES_PER_NODE; i++) {
-		npda->node_bte_info[i] = (bteinfo_t *)NULL;
-	}
-#endif
 #endif /* LATER */
 }
 
@@ -345,260 +171,44 @@
  * Must be done _after_ init_platform_nodepda().
  * If we need a lock here, something else is wrong!
  */
-// void init_platform_pda(pda_t *ppda, cpuid_t cpu)
 void init_platform_pda(cpuid_t cpu)
 {
+#if defined(CONFIG_IA64_SGI_SN1)
 	hub_intmasks_t *intmasks;
-#ifdef	LATER
-	cpuinfo_t cpuinfo;
-#endif
-	int i;
+	int i, subnode;
 	cnodeid_t	cnode;
 	synergy_da_t	*sda;
 	int	which_synergy;
 
-#ifdef	LATER
-	/* Allocate per-cpu platform-dependent data */
-	cpuinfo = (cpuinfo_t)kmem_alloc_node(sizeof(struct cpuinfo_s), GFP_ATOMIC, cputocnode(cpu));
-	ASSERT_ALWAYS(cpuinfo);
-	ppda->pdinfo = (void *)cpuinfo;
-	cpuinfo->ci_cpupda = ppda;
-	cpuinfo->ci_cpuid = cpu;
-#endif
 
 	cnode = cpuid_to_cnodeid(cpu);
 	which_synergy = cpuid_to_synergy(cpu);
+
 	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-	// intmasks = &ppda->p_intmasks;
 	intmasks = &sda->s_intmasks;
 
-#ifdef	LATER
-	ASSERT_ALWAYS(&ppda->p_nodepda);
-#endif
-
 	/* Clear INT_PEND0 masks. */
 	for (i = 0; i < N_INTPEND0_MASKS; i++)
 		intmasks->intpend0_masks[i] = 0;
 
 	/* Set up pointer to the vector block in the nodepda. */
 	/* (Cant use SUBNODEPDA - not working yet) */
-	intmasks->dispatch0 = &Nodepdaindr[cnode]->snpda[cpuid_to_subnode(cpu)].intr_dispatch0;
-	intmasks->dispatch1 = &Nodepdaindr[cnode]->snpda[cpuid_to_subnode(cpu)].intr_dispatch1;
+	subnode = cpuid_to_subnode(cpu);
+	intmasks->dispatch0 = &NODEPDA(cnode)->snpda[cpuid_to_subnode(cpu)].intr_dispatch0;
+	intmasks->dispatch1 = &NODEPDA(cnode)->snpda[cpuid_to_subnode(cpu)].intr_dispatch1;
+	if (intmasks->dispatch0 !=  &SUBNODEPDA(cnode, subnode)->intr_dispatch0 ||
+	   intmasks->dispatch1 !=  &SUBNODEPDA(cnode, subnode)->intr_dispatch1)
+	   	panic("xxx");
+	intmasks->dispatch0 = &SUBNODEPDA(cnode, subnode)->intr_dispatch0;
+	intmasks->dispatch1 = &SUBNODEPDA(cnode, subnode)->intr_dispatch1;
 
 	/* Clear INT_PEND1 masks. */
 	for (i = 0; i < N_INTPEND1_MASKS; i++)
 		intmasks->intpend1_masks[i] = 0;
-
-
-#ifdef	LATER
-	/* Don't read the routers unless we're the master. */
-	ppda->p_routertick = 0;
-#endif
-
+#endif	/* CONFIG_IA64_SGI_SN1 */
 }
 
-#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && !defined(BRINGUP)	/* protect low mem for IP35/7 */
-#error "need protect_hub_calias, protect_nmi_handler_data"
-#endif
-
-#ifdef	LATER
-/*
- * For now, just protect the first page (exception handlers). We
- * may want to protect more stuff later.
- */
 void
-protect_hub_calias(nasid_t nasid)
-{
-	paddr_t pa = NODE_OFFSET(nasid) + 0; /* page 0 on node nasid */
-	int i;
-
-	for (i = 0; i < MAX_REGIONS; i++) {
-		if (i == nasid_to_region(nasid))
-			continue;
-	}
-}
-
-/*
- * Protect the page of low memory used to communicate with the NMI handler.
- */
-void
-protect_nmi_handler_data(nasid_t nasid, int slice)
-{
-	paddr_t pa = NODE_OFFSET(nasid) + NMI_OFFSET(nasid, slice);
-	int i;
-
-	for (i = 0; i < MAX_REGIONS; i++) {
-		if (i == nasid_to_region(nasid))
-			continue;
-	}
-}
-#endif /* LATER */
-
-
-#ifdef LATER
-/*
- * Protect areas of memory that we access uncached by marking them as
- * poisoned so the T5 can't read them speculatively and erroneously
- * mark them dirty in its cache only to write them back with old data
- * later.
- */
-static void
-protect_low_memory(nasid_t nasid)
-{
-	/* Protect low memory directory */
-	poison_state_alter_range(KLDIR_ADDR(nasid), KLDIR_SIZE, 1);
-
-	/* Protect klconfig area */
-	poison_state_alter_range(KLCONFIG_ADDR(nasid), KLCONFIG_SIZE(nasid), 1);
-
-	/* Protect the PI error spool area. */
-	poison_state_alter_range(PI_ERROR_ADDR(nasid), PI_ERROR_SIZE(nasid), 1);
-
-	/* Protect CPU A's cache error eframe area. */
-	poison_state_alter_range(TO_NODE_UNCAC(nasid, CACHE_ERR_EFRAME),
-				CACHE_ERR_AREA_SIZE, 1);
-
-	/* Protect CPU B's area */
-	poison_state_alter_range(TO_NODE_UNCAC(nasid, CACHE_ERR_EFRAME)
-				^ UALIAS_FLIP_BIT,
-				CACHE_ERR_AREA_SIZE, 1);
-#error "SN1 not handled correctly"
-}
-#endif	/* LATER */
-
-/*
- * per_hub_init
- *
- * 	This code is executed once for each Hub chip.
- */
-void
-per_hub_init(cnodeid_t cnode)
-{
-	uint64_t	done;
-	nasid_t		nasid;
-	nodepda_t	*npdap;
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)	/* SN1 specific */
-	ii_icmr_u_t	ii_icmr;
-	ii_ibcr_u_t	ii_ibcr;
-#endif
-#ifdef	LATER
-	int i;
-#endif
-
-	nasid = COMPACT_TO_NASID_NODEID(cnode);
-
-	ASSERT(nasid != INVALID_NASID);
-	ASSERT(NASID_TO_COMPACT_NODEID(nasid) == cnode);
-
-	/* Grab the hub_mask lock. */
-	spin_lock(&hub_mask_lock);
-
-	/* Test our bit. */
-	if (!(done = CNODEMASK_TSTB(hub_init_mask, cnode))) {
-
-		/* Turn our bit on in the mask. */
-		CNODEMASK_SETB(hub_init_mask, cnode);
-	}
-
-#if defined(SN0_HWDEBUG)
-	hub_config_setup();
-#endif
-	/* Release the hub_mask lock. */
-	spin_unlock(&hub_mask_lock);
-
-	/*
-	 * Do the actual initialization if it hasn't been done yet.
-	 * We don't need to hold a lock for this work.
-	 */
-	if (!done) {
-		npdap = NODEPDA(cnode);
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-		/* initialize per-node synergy perf instrumentation */
-		npdap->synergy_perf_enabled = 0; /* off by default */
-		npdap->synergy_perf_lock = SPIN_LOCK_UNLOCKED;
-		npdap->synergy_perf_freq = SYNERGY_PERF_FREQ_DEFAULT;
-		npdap->synergy_inactive_intervals = 0;
-		npdap->synergy_active_intervals = 0;
-		npdap->synergy_perf_data = NULL;
-		npdap->synergy_perf_first = NULL;
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
-		npdap->hub_chip_rev = get_hub_chiprev(nasid);
-
-#ifdef	LATER
-		for (i = 0; i < CPUS_PER_NODE; i++) {
-			cpu = cnode_slice_to_cpuid(cnode, i);
-			if (!cpu_enabled(cpu))
-			    SET_CPU_LEDS(nasid, i, 0xf);
-		}
-#endif /* LATER */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC) /* SN1 specific */
-
-		/*
-		 * Set the total number of CRBs that can be used.
-		 */
-		ii_icmr.ii_icmr_regval= 0x0;
-		ii_icmr.ii_icmr_fld_s.i_c_cnt = 0xF;
-		REMOTE_HUB_S(nasid, IIO_ICMR, ii_icmr.ii_icmr_regval);
-
-		/*
-		 * Set the number of CRBs that both of the BTEs combined
-		 * can use minus 1.
-		 */
-		ii_ibcr.ii_ibcr_regval= 0x0;
-		ii_ibcr.ii_ibcr_fld_s.i_count = 0x8;
-		REMOTE_HUB_S(nasid, IIO_IBCR, ii_ibcr.ii_ibcr_regval);
-
-		/*
-		 * Set CRB timeout to be 10ms.
-		 */
-		REMOTE_HUB_S(nasid, IIO_ICTP, 0x1000 );
-		REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
-
-#endif /* SN0_HWDEBUG */
-
-
-
-		/* Reserve all of the hardwired interrupt levels. */
-		intr_reserve_hardwired(cnode);
-
-		/* Initialize error interrupts for this hub. */
-		hub_error_init(cnode);
-
-#ifdef LATER
-		/* Set up correctable memory/directory ECC error interrupt. */
-		install_eccintr(cnode);
-
-		/* Protect our exception vectors from accidental corruption. */
-		protect_hub_calias(nasid);
-
-		/* Enable RT clock interrupts */
-		hub_rtc_init(cnode);
-		hub_migrintr_init(cnode); /* Enable migration interrupt */
-#endif	/* LATER */
-
-		spin_lock(&hub_mask_lock);
-		CNODEMASK_SETB(hub_init_done_mask, cnode);
-		spin_unlock(&hub_mask_lock);
-
-	} else {
-		/*
-		 * Wait for the other CPU to complete the initialization.
-		 */
-		while (CNODEMASK_TSTB(hub_init_done_mask, cnode) == 0) {
-			/*
-			 * On SNIA64 we should never get here ..
-			 */
-			printk("WARNING: per_hub_init: Should NEVER get here!\n");
-			/* LOOP */
-			;
-		}
-	}
-}
-
-extern void
 update_node_information(cnodeid_t cnodeid)
 {
 	nodepda_t *npda = NODEPDA(cnodeid);
@@ -623,22 +233,3 @@
 		npda_rip = npda_rip->router_next;
 	}
 }
-
-hubreg_t
-get_region(cnodeid_t cnode)
-{
-	if (fine_mode)
-		return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_FINEREG_SHFT;
-	else
-		return COMPACT_TO_NASID_NODEID(cnode) >> NASID_TO_COARSEREG_SHFT;
-}
-
-hubreg_t
-nasid_to_region(nasid_t nasid)
-{
-	if (fine_mode)
-		return nasid >> NASID_TO_FINEREG_SHFT;
-	else
-		return nasid >> NASID_TO_COARSEREG_SHFT;
-}
-
diff -Nru a/arch/ia64/sn/io/ml_SN_intr.c b/arch/ia64/sn/io/ml_SN_intr.c
--- a/arch/ia64/sn/io/ml_SN_intr.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,1728 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Alan Mayer
- */
-
-/*
- * intr.c-
- *	This file contains all of the routines necessary to set up and
- *	handle interrupts on an IP27 board.
- */
-
-#ident  "$Revision: 1.167 $"
-
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <asm/smp.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/nodemask.h>
-#include <asm/sn/sn_private.h>
-#include <asm/sn/klconfig.h>
-#include <asm/sn/synergy.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/xtalk/xtalk.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/intr.h>
-
-#if DEBUG_INTR_TSTAMP_DEBUG
-#include <sys/debug.h>
-#include <sys/idbg.h>
-#include <sys/inst.h>
-void do_splx_log(int, int);
-void spldebug_log_event(int);
-#endif
-
-// FIXME - BRINGUP
-#ifdef CONFIG_SMP
-extern unsigned long cpu_online_map;
-#endif
-#define cpu_allows_intr(cpu)	(1)
-// If I understand what's going on with this, 32 should work.
-// physmem_maxradius seems to be the maximum number of router
-// hops to get from one end of the system to the other.  With
-// a maximally configured machine, with the dumbest possible
-// topology, we would make 32 router hops.  For what we're using
-// it for, the dumbest possible should suffice.
-#define physmem_maxradius()	32
-
-#define SUBNODE_ANY -1
-
-extern int	nmied;
-extern int	hub_intr_wakeup_cnt;
-extern synergy_da_t	*Synergy_da_indr[];
-extern cpuid_t         master_procid;
-
-extern cnodeid_t master_node_get(devfs_handle_t vhdl);
-
-extern snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
-
-
-#define INTR_LOCK(vecblk) \
-     (s = mutex_spinlock(&(vecblk)->vector_lock))
-#define INTR_UNLOCK(vecblk) \
-      mutex_spinunlock(&(vecblk)->vector_lock, s)
-
-/*
- * REACT/Pro
- */
-
-
-
-/* 
- * Find first bit set 
- * Used outside this file also 
- */
-int ms1bit(unsigned long x)
-{
-    int			b;
-
-    if (x >> 32)	b  = 32, x >>= 32;
-    else		b  =  0;
-    if (x >> 16)	b += 16, x >>= 16;
-    if (x >>  8)	b +=  8, x >>=  8;
-    if (x >>  4)	b +=  4, x >>=  4;
-    if (x >>  2)	b +=  2, x >>=  2;
-
-    return b + (int) (x >> 1);
-}
-
-/* ARGSUSED */
-void
-intr_stray(void *lvl)
-{
-    PRINT_WARNING("Stray Interrupt - level %ld to cpu %d", (long)lvl, cpuid());
-}
-
-#if defined(DEBUG)
-
-/* Infrastructure  to gather the device - target cpu mapping info */
-#define MAX_DEVICES	1000	/* Reasonable large number . Need not be 
-				 * the exact maximum # devices possible.
-				 */
-#define MAX_NAME	100	
-typedef struct {
-	dev_t		dev;	/* device */
-	cpuid_t		cpuid;	/* target cpu */
-	cnodeid_t	cnodeid;/* node on which the target cpu is present */
-	int		bit;	/* intr bit reserved */
-	char		intr_name[MAX_NAME]; /* name of the interrupt */
-} intr_dev_targ_map_t;
-
-intr_dev_targ_map_t 	intr_dev_targ_map[MAX_DEVICES];
-uint64_t		intr_dev_targ_map_size;
-spinlock_t		intr_dev_targ_map_lock;
-
-/* Print out the device - target cpu mapping.
- * This routine is used only in the idbg command
- * "intrmap" 
- */
-void
-intr_dev_targ_map_print(cnodeid_t cnodeid)
-{
-	int  i,j,size = 0;
-	int  print_flag = 0,verbose = 0;	
-	char node_name[10];
-	
-	if (cnodeid != CNODEID_NONE) {
-		nodepda_t 	*npda;
-
-		npda = NODEPDA(cnodeid);
-		for (j=0; j<NUM_SUBNODES; j++) {
-			qprintf("\n SUBNODE %d\n INT_PEND0: ", j);
-			for(i = 0 ; i < N_INTPEND_BITS ; i++)
-				qprintf("%d",SNPDA(npda,j)->intr_dispatch0.info[i].ii_flags);
-			qprintf("\n INT_PEND1: ");
-			for(i = 0 ; i < N_INTPEND_BITS ; i++)
-				qprintf("%d",SNPDA(npda,j)->intr_dispatch1.info[i].ii_flags);
-		}
-		verbose = 1;
-	}
-	qprintf("\n Device - Target Map [Interrupts: %s Node%s]\n\n",
-		(verbose ? "All" : "Non-hardwired"),
-		(cnodeid == CNODEID_NONE) ? "s: All" : node_name); 
-		
-	qprintf("Device\tCpu\tCnode\tIntr_bit\tIntr_name\n");
-	for (i = 0 ; i < intr_dev_targ_map_size ; i++) {
-
-		print_flag = 0;
-		if (verbose) {
-			if (cnodeid != CNODEID_NONE) {
-				if (cnodeid == intr_dev_targ_map[i].cnodeid)
-					print_flag = 1;
-			} else {
-				print_flag = 1;
-			}
-		} else {
-			if (intr_dev_targ_map[i].dev != 0) {
-				if (cnodeid != CNODEID_NONE) {
-					if (cnodeid == 
-					    intr_dev_targ_map[i].cnodeid)
-						print_flag = 1;
-				} else {
-					print_flag = 1;
-				}
-			}
-		}
-		if (print_flag) {
-			size++;
-			qprintf("%d\t%d\t%d\t%d\t%s\n",
-				intr_dev_targ_map[i].dev,
-				intr_dev_targ_map[i].cpuid,
-				intr_dev_targ_map[i].cnodeid,
-				intr_dev_targ_map[i].bit,
-				intr_dev_targ_map[i].intr_name);
-		}
-
-	}
-	qprintf("\nTotal : %d\n",size);
-}
-#endif /* DEBUG */
-
-/*
- * The spinlocks have already been initialized.  Now initialize the interrupt
- * vectors.  One processor on each hub does the work.
- */
-void
-intr_init_vecblk(nodepda_t *npda, cnodeid_t node, int sn)
-{
-    int			i, ip=0;
-    intr_vecblk_t	*vecblk;
-    subnode_pda_t	*snpda;
-
-
-    snpda = SNPDA(npda,sn);
-    do {
-	if (ip == 0) {
-	    vecblk = &snpda->intr_dispatch0;
-	} else {
-	    vecblk = &snpda->intr_dispatch1;
-	}
-
-	/* Initialize this vector. */
-	for (i = 0; i < N_INTPEND_BITS; i++) {
-		vecblk->vectors[i].iv_func = intr_stray;
-		vecblk->vectors[i].iv_prefunc = NULL;
-		vecblk->vectors[i].iv_arg = (void *)(__psint_t)(ip * N_INTPEND_BITS + i);
-
-		vecblk->info[i].ii_owner_dev = 0;
-		strcpy(vecblk->info[i].ii_name, "Unused");
-		vecblk->info[i].ii_flags = 0;	/* No flags */
-		vecblk->vectors[i].iv_mustruncpu = -1; /* No CPU yet. */
-
-	    }
-
-	mutex_spinlock_init(&vecblk->vector_lock);
-
-	vecblk->vector_count = 0;    
-	for (i = 0; i < CPUS_PER_SUBNODE; i++)
-		vecblk->cpu_count[i] = 0;
-
-	vecblk->vector_state = VECTOR_UNINITED;
-
-    } while (++ip < 2);
-
-}
-
-
-/*
- * do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
- *					devfs_handle_t owner_dev, char *name)
- *	Internal work routine to reserve or unreserve an interrupt level.
- *		cpu is the CPU to which the interrupt will be sent.
- *		bit is the level bit to reserve.  -1 means any level
- *		resflags should include II_ERRORINT if this is an
- *			error interrupt, II_THREADED if the interrupt handler
- *			will be threaded, or 0 otherwise.
- *		reserve should be set to II_RESERVE or II_UNRESERVE
- *			to get or clear a reservation.
- *		owner_dev is the device that "owns" this interrupt, if supplied
- *		name is a human-readable name for this interrupt, if supplied
- *	intr_reserve_level returns the bit reserved or -1 to indicate an error
- */
-static int
-do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
-					devfs_handle_t owner_dev, char *name)
-{
-    intr_vecblk_t	*vecblk;
-    hub_intmasks_t 	*hub_intmasks;
-    unsigned long s;
-    int rv = 0;
-    int ip;
-    synergy_da_t	*sda;
-    int		which_synergy;
-    cnodeid_t	cnode;
-
-    ASSERT(bit < N_INTPEND_BITS * 2);
-
-    cnode = cpuid_to_cnodeid(cpu);
-    which_synergy = cpuid_to_synergy(cpu);
-    sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-    hub_intmasks = &sda->s_intmasks;
-    // hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
-
-    // if (pdaindr[cpu].pda == NULL) return -1;
-    if ((bit < N_INTPEND_BITS) && !(resflags & II_ERRORINT)) {
-	vecblk = hub_intmasks->dispatch0;
-	ip = 0;
-    } else {
-	ASSERT((bit >= N_INTPEND_BITS) || (bit == -1));
-	bit -= N_INTPEND_BITS;	/* Get position relative to INT_PEND1 reg. */
-	vecblk = hub_intmasks->dispatch1;
-	ip = 1;
-    }
-
-    INTR_LOCK(vecblk);
-
-    if (bit <= -1) {
-	bit = 0;
-	ASSERT(reserve == II_RESERVE);
-	/* Choose any available level */
-	for (; bit < N_INTPEND_BITS; bit++) {
-	    if (!(vecblk->info[bit].ii_flags & II_RESERVE)) {
-		rv = bit;
-		break;
-	    }
-	}
-
-	/* Return -1 if all interrupt levels int this register are taken. */
-	if (bit == N_INTPEND_BITS)
-	    rv = -1;
-
-    } else {
-	/* Reserve a particular level if it's available. */
-	if ((vecblk->info[bit].ii_flags & II_RESERVE) == reserve) {
-	    /* Can't (un)reserve a level that's already (un)reserved. */
-	    rv = -1;
-	} else {
-	    rv = bit;
-	}
-    }
-
-    /* Reserve the level and bump the count. */
-    if (rv != -1) {
-	if (reserve) {
-	    int maxlen = sizeof(vecblk->info[bit].ii_name) - 1;
-	    int namelen;
-	    vecblk->info[bit].ii_flags |= (II_RESERVE | resflags);
-	    vecblk->info[bit].ii_owner_dev = owner_dev;
-	    /* Copy in the name. */
-	    namelen = name ? strlen(name) : 0;
-	    strncpy(vecblk->info[bit].ii_name, name, MIN(namelen, maxlen)); 
-	    vecblk->info[bit].ii_name[maxlen] = '\0';
-	    vecblk->vector_count++;
-	} else {
-	    vecblk->info[bit].ii_flags = 0;	/* Clear all the flags */
-	    vecblk->info[bit].ii_owner_dev = 0;
-	    /* Clear the name. */
-	    vecblk->info[bit].ii_name[0] = '\0';
-	    vecblk->vector_count--;
-	}
-    }
-
-    INTR_UNLOCK(vecblk);
-
-#if defined(DEBUG)
-    if (rv >= 0) {
-	    int namelen = name ? strlen(name) : 0;
-	    /* Gather this device - target cpu mapping information
-	     * in a table which can be used later by the idbg "intrmap"
-	     * command
-	     */
-	    s = mutex_spinlock(&intr_dev_targ_map_lock);
-	    if (intr_dev_targ_map_size < MAX_DEVICES) {
-		    intr_dev_targ_map_t	*p;
-
-		    p 		= &intr_dev_targ_map[intr_dev_targ_map_size];
-		    p->dev  	= owner_dev;
-		    p->cpuid 	= cpu; 
-		    p->cnodeid 	= cputocnode(cpu); 
-		    p->bit 	= ip * N_INTPEND_BITS + rv;
-		    strncpy(p->intr_name,
-			    name,
-			    MIN(MAX_NAME,namelen));
-		    intr_dev_targ_map_size++;
-	    }
-	    mutex_spinunlock(&intr_dev_targ_map_lock,s);
-    }
-#endif /* DEBUG */
-
-    return (((rv == -1) ? rv : (ip * N_INTPEND_BITS) + rv)) ;
-}
-
-
-/*
- * WARNING:  This routine should only be called from within ml/SN.
- *	Reserve an interrupt level.
- */
-int
-intr_reserve_level(cpuid_t cpu, int bit, int resflags, devfs_handle_t owner_dev, char *name)
-{
-	return(do_intr_reserve_level(cpu, bit, resflags, II_RESERVE, owner_dev, name));
-}
-
-
-/*
- * WARNING:  This routine should only be called from within ml/SN.
- *	Unreserve an interrupt level.
- */
-void
-intr_unreserve_level(cpuid_t cpu, int bit)
-{
-	(void)do_intr_reserve_level(cpu, bit, 0, II_UNRESERVE, 0, NULL);
-}
-
-/*
- * Get values that vary depending on which CPU and bit we're operating on
- */
-static hub_intmasks_t *
-intr_get_ptrs(cpuid_t cpu, int bit,
-	      int *new_bit,		/* Bit relative to the register */
-	      hubreg_t **intpend_masks, /* Masks for this register */
-	      intr_vecblk_t **vecblk,	/* Vecblock for this interrupt */
-	      int *ip)			/* Which intpend register */
-{
-	hub_intmasks_t *hub_intmasks;
-	synergy_da_t	*sda;
-	int		which_synergy;
-	cnodeid_t	cnode;
-
-	ASSERT(bit < N_INTPEND_BITS * 2);
-
-	cnode = cpuid_to_cnodeid(cpu);
-	which_synergy = cpuid_to_synergy(cpu);
-	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
-	hub_intmasks = &sda->s_intmasks;
-
-	// hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
-
-	if (bit < N_INTPEND_BITS) {
-		*intpend_masks = hub_intmasks->intpend0_masks;
-		*vecblk = hub_intmasks->dispatch0;
-		*ip = 0;
-		*new_bit = bit;
-	} else {
-		*intpend_masks = hub_intmasks->intpend1_masks;
-		*vecblk = hub_intmasks->dispatch1;
-		*ip = 1;
-		*new_bit = bit - N_INTPEND_BITS;
-	}
-
-	return hub_intmasks;
-}
-
-
-/*
- * intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
- *		intr_func_t intr_func, void *intr_arg);
- *	This is the lowest-level interface to the interrupt code.  It shouldn't
- *	be called from outside the ml/SN directory.
- *	intr_connect_level hooks up an interrupt to a particular bit in
- *	the INT_PEND0/1 masks.  Returns 0 on success.
- *		cpu is the CPU to which the interrupt will be sent.
- *		bit is the level bit to connect to
- *		intr_swlevel tells which software level to use
- *		intr_func is the interrupt handler
- *		intr_arg is an arbitrary argument interpreted by the handler
- *		intr_prefunc is a prologue function, to be called
- *			with interrupts disabled, to disable
- *			the interrupt at source.  It is called
- *			with the same argument.  Should be NULL for
- *			typical interrupts, which can be masked
- *			by the infrastructure at the level bit.
- *	intr_connect_level returns 0 on success or nonzero on an error
- */
-/* ARGSUSED */
-int
-intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
-		intr_func_t intr_func, void *intr_arg,
-		intr_func_t intr_prefunc)
-{
-    intr_vecblk_t	*vecblk;
-    hubreg_t		*intpend_masks;
-    int rv = 0;
-    int ip;
-    unsigned long s;
-
-    ASSERT(bit < N_INTPEND_BITS * 2);
-
-    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
-				 &vecblk, &ip);
-
-    INTR_LOCK(vecblk);
-
-    if ((vecblk->info[bit].ii_flags & II_INUSE) ||
-	(!(vecblk->info[bit].ii_flags & II_RESERVE))) {
-	/* Can't assign to a level that's in use or isn't reserved. */
-	rv = -1;
-    } else {
-	/* Stuff parameters into vector and info */
-	vecblk->vectors[bit].iv_func = intr_func;
-	vecblk->vectors[bit].iv_prefunc = intr_prefunc;
-	vecblk->vectors[bit].iv_arg = intr_arg;
-	vecblk->info[bit].ii_flags |= II_INUSE;
-    }
-
-    /* Now stuff the masks if everything's okay. */
-    if (!rv) {
-	int lslice;
-	volatile hubreg_t *mask_reg;
-	// nasid_t nasid = COMPACT_TO_NASID_NODEID(cputocnode(cpu));
-	nasid_t nasid = cpuid_to_nasid(cpu);
-	int	subnode = cpuid_to_subnode(cpu);
-
-	/* Make sure it's not already pending when we connect it. */
-	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit + ip * N_INTPEND_BITS);
-
-	intpend_masks[0] |= (1ULL << (uint64_t)bit);
-
-	lslice = cputolocalslice(cpu);
-	vecblk->cpu_count[lslice]++;
-#if SN1
-	/*
-	 * On SN1, there are 8 interrupt mask registers per node:
-	 * 	PI_0 MASK_0 A
-	 * 	PI_0 MASK_1 A
-	 * 	PI_0 MASK_0 B
-	 * 	PI_0 MASK_1 B
-	 * 	PI_1 MASK_0 A
-	 * 	PI_1 MASK_1 A
-	 * 	PI_1 MASK_0 B
-	 * 	PI_1 MASK_1 B
-	 */
-#endif
-	if (ip == 0) {
-		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode, 
-		        PI_INT_MASK0_A + PI_INT_MASK_OFFSET * lslice);
-	} else {
-		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode,
-			PI_INT_MASK1_A + PI_INT_MASK_OFFSET * lslice);
-	}
-
-	HUB_S(mask_reg, intpend_masks[0]);
-    }
-
-    INTR_UNLOCK(vecblk);
-
-    return rv;
-}
-
-
-/*
- * intr_disconnect_level(cpuid_t cpu, int bit)
- *
- *	This is the lowest-level interface to the interrupt code.  It should
- *	not be called from outside the ml/SN directory.
- *	intr_disconnect_level removes a particular bit from an interrupt in
- * 	the INT_PEND0/1 masks.  Returns 0 on success or nonzero on failure.
- */
-int
-intr_disconnect_level(cpuid_t cpu, int bit)
-{
-    intr_vecblk_t	*vecblk;
-    hubreg_t		*intpend_masks;
-    unsigned long s;
-    int rv = 0;
-    int ip;
-
-    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
-				 &vecblk, &ip);
-
-    INTR_LOCK(vecblk);
-
-    if ((vecblk->info[bit].ii_flags & (II_RESERVE | II_INUSE)) !=
-	((II_RESERVE | II_INUSE))) {
-	/* Can't remove a level that's not in use or isn't reserved. */
-	rv = -1;
-    } else {
-	/* Stuff parameters into vector and info */
-	vecblk->vectors[bit].iv_func = (intr_func_t)NULL;
-	vecblk->vectors[bit].iv_prefunc = (intr_func_t)NULL;
-	vecblk->vectors[bit].iv_arg = 0;
-	vecblk->info[bit].ii_flags &= ~II_INUSE;
-#ifdef BASE_ITHRTEAD
-	vecblk->vectors[bit].iv_mustruncpu = -1; /* No mustrun CPU any more. */
-#endif
-    }
-
-    /* Now clear the masks if everything's okay. */
-    if (!rv) {
-	int lslice;
-	volatile hubreg_t *mask_reg;
-
-	intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
-	lslice = cputolocalslice(cpu);
-	vecblk->cpu_count[lslice]--;
-	mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-				   cpuid_to_subnode(cpu),
-				   ip == 0 ? PI_INT_MASK0_A : PI_INT_MASK1_A);
-	mask_reg = (volatile hubreg_t *)((__psunsigned_t)mask_reg +
-					(PI_INT_MASK_OFFSET * lslice));
-	*mask_reg = intpend_masks[0];
-    }
-
-    INTR_UNLOCK(vecblk);
-
-    return rv;
-}
-
-/*
- * Actually block or unblock an interrupt
- */
-void
-do_intr_block_bit(cpuid_t cpu, int bit, int block)
-{
-	intr_vecblk_t *vecblk;
-	int ip;
-	unsigned long s;
-	hubreg_t *intpend_masks;
-	volatile hubreg_t mask_value;
-	volatile hubreg_t *mask_reg;
-
-	intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &vecblk, &ip);
-
-	INTR_LOCK(vecblk);
-
-	if (block)
-		/* Block */
-		intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
-	else
-		/* Unblock */
-		intpend_masks[0] |= (1ULL << (uint64_t)bit);
-
-	if (ip == 0) {
-		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-		        cpuid_to_subnode(cpu), PI_INT_MASK0_A);
-	} else {
-		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(cpu)), 
-			cpuid_to_subnode(cpu), PI_INT_MASK1_A);
-	}
-
-	HUB_S(mask_reg, intpend_masks[0]);
-
-	/*
-	 * Wait for it to take effect.  (One read should suffice.)
-	 * This is only necessary when blocking an interrupt
-	 */
-	if (block)
-		while ((mask_value = HUB_L(mask_reg)) != intpend_masks[0])
-			;
-
-	INTR_UNLOCK(vecblk);
-}
-
-
-/*
- * Block a particular interrupt (cpu/bit pair).
- */
-/* ARGSUSED */
-void
-intr_block_bit(cpuid_t cpu, int bit)
-{
-	do_intr_block_bit(cpu, bit, 1);
-}
-
-
-/*
- * Unblock a particular interrupt (cpu/bit pair).
- */
-/* ARGSUSED */
-void
-intr_unblock_bit(cpuid_t cpu, int bit)
-{
-	do_intr_block_bit(cpu, bit, 0);
-}
-
-
-/* verifies that the specified CPUID is on the specified SUBNODE (if any) */
-#define cpu_on_subnode(cpuid, which_subnode) \
-	   (((which_subnode) == SUBNODE_ANY) || (cpuid_to_subnode(cpuid) == (which_subnode)))
-
-
-/*
- * Choose one of the CPUs on a specified node or subnode to receive
- * interrupts. Don't pick a cpu which has been specified as a NOINTR cpu.
- *
- * Among all acceptable CPUs, the CPU that has the fewest total number
- * of interrupts targetted towards it is chosen.  Note that we never
- * consider how frequent each of these interrupts might occur, so a rare
- * hardware error interrupt is weighted equally with a disk interrupt.
- */
-static cpuid_t
-do_intr_cpu_choose(cnodeid_t cnode, int which_subnode)
-{
-	cpuid_t 	cpu, best_cpu = CPU_NONE;
-	int		slice, min_count=1000;
-
-	min_count = 1000;
-	for (slice=0; slice < CPUS_PER_NODE; slice++) {
-		intr_vecblk_t 	*vecblk0, *vecblk1;
-		int total_intrs_to_slice;
-		subnode_pda_t *snpda;
-		int local_cpu_num;
-
-		cpu = cnode_slice_to_cpuid(cnode, slice);
-		if (cpu == CPU_NONE)
-			continue;
-
-		/* If this cpu isn't enabled for interrupts, skip it */
-		if (!cpu_enabled(cpu) || !cpu_allows_intr(cpu))
-			continue;
-
-		/* If this isn't the right subnode, skip it */
-		if (!cpu_on_subnode(cpu, which_subnode))
-			continue;
-
-		/* OK, this one's a potential CPU for interrupts */
-		snpda = SUBNODEPDA(cnode,SUBNODE(slice));
-		vecblk0 = &snpda->intr_dispatch0;
-		vecblk1 = &snpda->intr_dispatch1;
-		local_cpu_num = LOCALCPU(slice);
-		total_intrs_to_slice = vecblk0->cpu_count[local_cpu_num] +
-		              vecblk1->cpu_count[local_cpu_num];
-
-		if (min_count > total_intrs_to_slice) {
-			min_count = total_intrs_to_slice;
-			best_cpu = cpu;
-		}
-	}
-	return best_cpu;
-}
-
-/*
- * Choose an appropriate interrupt target CPU on a specified node.
- * If which_subnode is SUBNODE_ANY, then subnode is not considered.
- * Otherwise, the chosen CPU must be on the specified subnode.
- */
-static cpuid_t
-intr_cpu_choose_from_node(cnodeid_t cnode, int which_subnode)
-{
-	return(do_intr_cpu_choose(cnode, which_subnode));
-}
-
-
-#ifdef	LATER
-/*
- * Convert a subnode vertex into a (cnodeid, which_subnode) pair.
- * Return 0 on success, non-zero on failure.
- */
-static int
-subnodevertex_to_subnode(devfs_handle_t vhdl, cnodeid_t *cnodeidp, int *which_subnodep)
-{
-	arbitrary_info_t which_subnode;
-	cnodeid_t cnodeid;
-
-	/* Try to grab subnode information */
-	if (hwgraph_info_get_LBL(vhdl, INFO_LBL_CPUBUS, &which_subnode) != GRAPH_SUCCESS)
-		return(-1);
-
-	/* On which node? */
-	cnodeid = master_node_get(vhdl);
-	if (cnodeid == CNODEID_NONE)
-		return(-1);
-
-	*which_subnodep = (int)which_subnode;
-	*cnodeidp = cnodeid;
-	return(0); /* success */
-}
-
-#endif /* LATER */
-
-/* Make it easy to identify subnode vertices in the hwgraph */
-void
-mark_subnodevertex_as_subnode(devfs_handle_t vhdl, int which_subnode)
-{
-	graph_error_t rv;
-
-	ASSERT(0 <= which_subnode);
-	ASSERT(which_subnode < NUM_SUBNODES);
-
-	rv = hwgraph_info_add_LBL(vhdl, INFO_LBL_CPUBUS, (arbitrary_info_t)which_subnode);
-	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
-
-	rv = hwgraph_info_export_LBL(vhdl, INFO_LBL_CPUBUS, sizeof(arbitrary_info_t));
-	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
-}
-
-
-/*
- * Given a device descriptor, extract interrupt target information and
- * choose an appropriate CPU.  Return CPU_NONE if we can't make sense
- * out of the target information.
- * TBD: Should this be considered platform-independent code?
- */
-
-#ifdef	LATER
-static cpuid_t
-intr_target_from_desc(device_desc_t dev_desc, int favor_subnode)
-{
-	cpuid_t cpuid = CPU_NONE;
-	cnodeid_t cnodeid;
-	int which_subnode;
-	devfs_handle_t intr_target_dev;
-
-	if ((intr_target_dev = device_desc_intr_target_get(dev_desc)) != GRAPH_VERTEX_NONE) {
-		/* 
-		 * A valid device was specified.  If it's a particular
-		 * CPU, then use that CPU as target.  
-		 */
-		cpuid = cpuvertex_to_cpuid(intr_target_dev);
-		if (cpuid != CPU_NONE)
-			goto cpuchosen;
-
-		/* If a subnode vertex was specified, pick a CPU on that subnode. */
-		if (subnodevertex_to_subnode(intr_target_dev, &cnodeid, &which_subnode) == 0) {
-			cpuid = intr_cpu_choose_from_node(cnodeid, which_subnode);
-			goto cpuchosen;
-		}
-
-		/*
-		 * Otherwise, pick a CPU on the node that owns the 
-		 * specified target.  Favor "favor_subnode", if specified.
-		 */
-		cnodeid = master_node_get(intr_target_dev);
-		if (cnodeid != CNODEID_NONE) {
-			cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
-			goto cpuchosen;
-		}
-	}
-
-cpuchosen:
-	return(cpuid);
-}
-#endif	/* LATER */
-
-
-#ifdef	LATER
-/*
- * Check if we had already visited this candidate cnode
- */
-static void *
-intr_cnode_seen(cnodeid_t 	candidate,
-		void 		*arg1,
-		void 		*arg2)
-{
-	int		i;
-	cnodeid_t	*visited_cnodes = (cnodeid_t *)arg1;
-	int		*num_visited_cnodes = (int *)arg2;
-
-	ASSERT(visited_cnodes);
-	ASSERT(*num_visited_cnodes <= numnodes);
-	for(i = 0 ; i < *num_visited_cnodes; i++) {
-		if (candidate == visited_cnodes[i])
-			return(NULL);
-	}
-	return(visited_cnodes);
-}
-
-#endif /* LATER */
-
-
-
-/*
- * intr_bit_reserve_test(cpuid,which_subnode,cnode,req_bit,intr_resflags,
- *		owner_dev,intr_name,*resp_bit)
- *	Either cpuid is not CPU_NONE or cnodeid not CNODE_NONE but
- * 	not both.
- * 1. 	If cpuid is specified, this routine tests if this cpu can be a valid
- * 	interrupt target candidate.
- * 2. 	If cnodeid is specified, this routine tests if there is a cpu on 
- *	this node which can be a valid interrupt target candidate.
- * 3.	If a valid interrupt target cpu candidate is found then an attempt at 
- * 	reserving an interrupt bit on the corresponding cnode is made.
- *
- * If steps 1 & 2 both fail or step 3 fails then we are not able to get a valid
- * interrupt target cpu then routine returns CPU_NONE (failure)
- * Otherwise routine returns cpuid of interrupt target (success)
- */
-static cpuid_t
-intr_bit_reserve_test(cpuid_t 		cpuid,
-		      int		favor_subnode,
-		      cnodeid_t 	cnodeid,
-		      int		req_bit,
-		      int 		intr_resflags,
-		      devfs_handle_t 	owner_dev,
-		      char		*intr_name,
-		      int		*resp_bit)
-{
-
-	ASSERT((cpuid==CPU_NONE) || (cnodeid==CNODEID_NONE));
-
-	if (cnodeid != CNODEID_NONE) {
-		/* Try to choose a interrupt cpu candidate */
-		cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
-	}
-
-	if (cpuid != CPU_NONE) {
-		/* Try to reserve an interrupt bit on the hub 
-		 * corresponding to the canidate cnode. If we
-		 * are successful then we got a cpu which can
-		 * act as an interrupt target for the io device.
-		 * Otherwise we need to continue the search
-		 * further.
-		 */
-		*resp_bit = do_intr_reserve_level(cpuid, 
-						  req_bit,
-						  intr_resflags,
-						  II_RESERVE,
-						  owner_dev, 
-						  intr_name);
-
-		if (*resp_bit >= 0)
-			/* The interrupt target  specified was fine */
-			return(cpuid);
-	}
-	return(CPU_NONE);
-}
-/*
- * intr_heuristic(dev_t dev,device_desc_t dev_desc,
- *		  int req_bit,int intr_resflags,dev_t owner_dev,
- *		  char *intr_name,int *resp_bit)
- *
- * Choose an interrupt destination for an interrupt.
- *	dev is the device for which the interrupt is being set up
- *	dev_desc is a description of hardware and policy that could
- *		help determine where this interrupt should go
- *	req_bit is the interrupt bit requested 
- *		(can be INTRCONNECT_ANY_BIT in which the first available
- * 		 interrupt bit is used)
- *	intr_resflags indicates whether we want to (un)reserve bit
- *	owner_dev is the owner device
- *	intr_name is the readable interrupt name	
- * 	resp_bit indicates whether we succeeded in getting the required
- *		 action  { (un)reservation} done	
- *		 negative value indicates failure
- *
- */
-/* ARGSUSED */
-cpuid_t
-intr_heuristic(devfs_handle_t 		dev,
-	       device_desc_t 	dev_desc,
-	       int		req_bit,
-	       int 		intr_resflags,
-	       devfs_handle_t 		owner_dev,
-	       char		*intr_name,
-	       int		*resp_bit)
-{
-	cpuid_t		cpuid;				/* possible intr targ*/
-	cnodeid_t 	candidate;			/* possible canidate */
-#ifdef LATER
-	cnodeid_t	visited_cnodes[MAX_NASIDS], 	/* nodes seen so far */
-		        center,				/* node we are on */
-		        candidate;			/* possible canidate */
-	int		num_visited_cnodes = 0;		/* # nodes seen */
-
-	int		radius = 1,			/* start looking at the
-							 * current node
-							 */
-		        maxradius = physmem_maxradius();
-	void		*rv;
-#endif /* LATER */
-	int		which_subnode = SUBNODE_ANY;
-
-/* SN1 + pcibr Addressing Limitation */
-	{
-	devfs_handle_t pconn_vhdl;
-	pcibr_soft_t pcibr_soft;
-
-	/*
-	 * This combination of SN1 and Bridge hardware has an odd "limitation".
-	 * Due to the choice of addresses for PI0 and PI1 registers on SN1
-	 * and historical limitations in Bridge, Bridge is unable to
-	 * send interrupts to both PI0 CPUs and PI1 CPUs -- we have
-	 * to choose one set or the other.  That choice is implicitly
-	 * made when Bridge first attaches its error interrupt.  After
-	 * that point, all subsequent interrupts are restricted to the
-	 * same PI number (though it's possible to send interrupts to
-	 * the same PI number on a different node).
-	 *
-	 * Since neither SN1 nor Bridge designers are willing to admit a
-	 * bug, we can't really call this a "workaround".  It's a permanent
-	 * solution for an SN1-specific and Bridge-specific hardware
-	 * limitation that won't ever be lifted.
-	 */
-        if ((hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
-	   ((pcibr_soft = pcibr_soft_get(pconn_vhdl)) != NULL)) {
-		/*
-		 * We "know" that the error interrupt is the first
-		 * interrupt set up by pcibr_attach.  Send all interrupts
-		 * on this bridge to the same subnode number.
-		 */
-		if (pcibr_soft->bsi_err_intr) {
-			which_subnode = cpuid_to_subnode(((hub_intr_t) pcibr_soft->bsi_err_intr)->i_cpuid);
-		}
-	}
-	}
-
-#ifdef	LATER
-	/* 
-	 * If an interrupt target was specified for this
-	 * interrupt allocation, try to use it.
-	 */
-	if (dev_desc) {
-
-		/* Try to see if the interrupt target specified in the
-		 * device descriptor is a legal candidate.
-		 */
-		cpuid = intr_bit_reserve_test(intr_target_from_desc(dev_desc, which_subnode),
-					      which_subnode,
-					      CNODEID_NONE,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-		if (cpuid != CPU_NONE) {
-			if (cpu_on_subnode(cpuid, which_subnode))
-				return(cpuid);	/* got a valid interrupt target */
-
-			printk("Override explicit interrupt targetting: %v (0x%x)\n",
-				owner_dev, owner_dev);
-
-			intr_unreserve_level(cpuid, *resp_bit);
-		}
-
-		/* Fall through on to the next step in the search for
-		 * the interrupt candidate.
-		 */
-
-	}
-#endif  /* LATER */
-	
-	/* Check if we can find a valid interrupt target candidate on
-	 * the master node for the device.
-	 */
-	cpuid = intr_bit_reserve_test(CPU_NONE,
-				      which_subnode,	
-				      master_node_get(dev),
-				      req_bit,
-				      intr_resflags,
-				      owner_dev,
-				      intr_name,
-				      resp_bit);
-
-	if (cpuid != CPU_NONE) {
-		if (cpu_on_subnode(cpuid, which_subnode))
-			return(cpuid);	/* got a valid interrupt target */
-		else
-			intr_unreserve_level(cpuid, *resp_bit);
-	}
-
-	PRINT_WARNING("Cannot target interrupts to closest node(%d): %ld (0x%lx)\n",
-		master_node_get(dev),(long) owner_dev, (unsigned long)owner_dev);
-
-	/* Fall through into the default algorithm
-	 * (exhaustive-search-for-the-nearest-possible-interrupt-target)
-	 * for finding the interrupt target
-	 */
-
-#ifndef BRINGUP
-	// Use of this algorithm is deferred until the supporting
-	// code has been implemented.
-	/* 
-	 * No valid interrupt specification exists.
-	 * Try to find a node which is closest to the current node
-	 * which can process interrupts from a device
-	 */
-
-	center = cpuid_to_cnodeid(smp_processor_id());
-	while (radius <= maxradius) {
-
-		/* Try to find a node at the given radius and which
-		 * we haven't seen already.
-		 */
-		rv = physmem_select_neighbor_node(center,radius,&candidate,
-						  intr_cnode_seen,
-						  (void *)visited_cnodes,
-						  (void *)&num_visited_cnodes);
-		if (!rv) {
-			/* We have seen all the nodes at this particular radius
-			 * Go on to the next radius level.
-			 */
-			radius++;
-			continue;
-		}			      
-		/* We are seeing this candidate  cnode for the first time
-		 */
-		visited_cnodes[num_visited_cnodes++] = candidate;
-
-		cpuid = intr_bit_reserve_test(CPU_NONE,
-					      which_subnode,
-					      candidate,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-		if (cpuid != CPU_NONE) {
-			if (cpu_on_subnode(cpuid, which_subnode))
-				return(cpuid);	/* got a valid interrupt target */
-			else
-				intr_unreserve_level(cpuid, *resp_bit);
-		}
-	}
-#else  /* BRINGUP */
-	{
-	// Do a stupid round-robin assignment of the node.
-		static cnodeid_t last_node = -1;
-
-		if (last_node >= numnodes) last_node = 0;
-		for (candidate = last_node + 1; candidate != last_node; candidate++) {
-			if (candidate == numnodes) candidate = 0;
-			cpuid = intr_bit_reserve_test(CPU_NONE,
-					      which_subnode,
-					      candidate,
-					      req_bit,
-					      intr_resflags,
-					      owner_dev,
-					      intr_name,
-					      resp_bit);
-
-			if (cpuid != CPU_NONE) {
-				if (cpu_on_subnode(cpuid, which_subnode)) {
-					last_node = candidate;
-					return(cpuid);	/* got a valid interrupt target */
-				}
-				else
-					intr_unreserve_level(cpuid, *resp_bit);
-			}
-		}
-		last_node = candidate;
-	}
-#endif
-
-	PRINT_WARNING("Cannot target interrupts to any close node: %ld (0x%lx)\n",
-		(long)owner_dev, (unsigned long)owner_dev);
-
-	/* In the worst case try to allocate interrupt bits on the
-	 * master processor's node. We may get here during error interrupt
-	 * allocation phase when the topology matrix is not yet setup
-	 * and hence cannot do an exhaustive search.
-	 */
-	ASSERT(cpu_allows_intr(master_procid));
-	cpuid = intr_bit_reserve_test(master_procid,
-				      which_subnode,
-				      CNODEID_NONE,
-				      req_bit,
-				      intr_resflags,
-				      owner_dev,
-				      intr_name,
-				      resp_bit);
-
-	if (cpuid != CPU_NONE) {
-		if (cpu_on_subnode(cpuid, which_subnode))
-			return(cpuid);
-		else
-			intr_unreserve_level(cpuid, *resp_bit);
-	}
-
-	PRINT_WARNING("Cannot target interrupts: %ld (0x%lx)\n",
-		(long)owner_dev, (unsigned long)owner_dev);
-
-	return(CPU_NONE);	/* Should never get here */
-}
-
-
-
-
-#ifndef BRINGUP
-/*
- * Should never receive an exception while running on the idle 
- * stack.  It IS possible to handle *interrupts* while on the
- * idle stack, but a non-interrupt *exception* is a problem.
- */
-void
-idle_err(inst_t *epc, uint cause, void *fep, void *sp)
-{
-	eframe_t *ep = (eframe_t *)fep;
-
-    if ((cause & CAUSE_EXCMASK) == EXC_IBE ||
-	(cause & CAUSE_EXCMASK) == EXC_DBE) {
-	(void)dobuserre((eframe_t *)ep, epc, 0);
-    }
-
-    /* XXX - This will have to change to deal with various SN errors. */
-    panic( "exception on IDLE stack "
-	    "ep:0x%x epc:0x%x cause:0x%w32x sp:0x%x badvaddr:0x%x",
-	    ep, epc, cause, sp, getbadvaddr());
-    /* NOTREACHED */
-}
-
-
-/*
- * earlynofault - handle very early global faults - usually just while
- *      sizing memory
- * Returns: 1 if should do nofault
- *          0 if not
- */
-/* ARGSUSED */
-int
-earlynofault(eframe_t *ep, uint code)
-{
-	switch(code) {
-	case EXC_DBE:
-		return(1);
-	default:
-		return(0);
-	}
-}
-
-
-
-/* ARGSUSED */
-static void
-cpuintr(void *arg1, void *arg2)
-{
-#if RTE
-	static int rte_intrdebug = 1;
-#endif
-	/*
-	 * Frame Scheduler
-	 */
-	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_CPUINTR, NULL, NULL,
-			 NULL, NULL);
-
-	/*
-	 * Hardware clears the IO interrupts, but we need to clear software-
-	 * generated interrupts.
-	 */
-	LOCAL_HUB_CLR_INTR(CPU_ACTION_A + cputolocalslice(cpuid()));
-
-#if 0
-	/* XXX - Handle error interrupts. */
-	if (error_intr_reason)
-		error_intr();
-#endif /* 0 */
-
-	/*
-	 * If we're headed for panicspin and it is due to a NMI, save the
-	 * eframe in the NMI area
-	 */
-	if (private.p_va_panicspin && nmied) {
-		caddr_t	nmi_save_area;
-
-		nmi_save_area = (caddr_t) (TO_UNCAC(TO_NODE(
-			cputonasid(cpuid()), IP27_NMI_EFRAME_OFFSET)) + 
-			cputoslice(cpuid()) * IP27_NMI_EFRAME_SIZE);
-		bcopy((caddr_t) arg2, nmi_save_area, sizeof(eframe_t));
-	}
-
-	doacvec();
-#if RTE
-	if (private.p_flags & PDAF_ISOLATED && !rte_intrdebug)
-		goto end_cpuintr;
-#endif
-	doactions();
-#if RTE
-end_cpuintr:
-#endif
-	LOG_TSTAMP_EVENT(RTMON_INTR, TSTAMP_EV_INTREXIT, TSTAMP_EV_CPUINTR, NULL, NULL, NULL);
-}
-
-void
-install_cpuintr(cpuid_t cpu)
-{
-	int		intr_bit = CPU_ACTION_A + cputolocalslice(cpu);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
-				(intr_func_t) cpuintr, NULL, NULL))
-		panic("install_cpuintr: Can't connect interrupt.");
-}
-#endif /* BRINGUP */
-
-#ifdef DEBUG_INTR_TSTAMP
-/* We allocate an array, but only use element number 64.  This guarantees that
- * the entry is in a cacheline by itself.
- */
-#define DINTR_CNTIDX	32
-#define DINTR_TSTAMP1	48
-#define	DINTR_TSTAMP2	64
-volatile long long dintr_tstamp_cnt[128];
-int dintr_debug_output=0;
-extern void idbg_tstamp_debug(void);
-#ifdef SPLDEBUG
-extern void idbg_splx_log(int);
-#endif
-#if DEBUG_INTR_TSTAMP_DEBUG
-int dintr_enter_symmon=1000;	/* 1000 microseconds is 1 millisecond */
-#endif
-
-#ifndef BRINGUP
-/* ARGSUSED */
-static void
-cpulatintr(void *arg)
-{
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(CPU_INTRLAT_A + cputolocalslice(cpuid()));
-
-#if DEBUG_INTR_TSTAMP_DEBUG
-	dintr_tstamp_cnt[DINTR_TSTAMP2] =  GET_LOCAL_RTC;
-	if ((dintr_tstamp_cnt[DINTR_TSTAMP2] - dintr_tstamp_cnt[DINTR_TSTAMP1])
-	    > dintr_enter_symmon) {
-#ifdef SPLDEBUG
-		extern int spldebug_log_off;
-
-		spldebug_log_off = 1;
-#endif /* SPLDEBUG */
-		debug("ring");
-#ifdef SPLDEBUG
-		spldebug_log_off = 0;
-#endif /* SPLDEBUG */
-	}
-#endif
-	dintr_tstamp_cnt[DINTR_CNTIDX]++;
-
-	return;
-}
-
-static int install_cpulat_first=0;
-
-void
-install_cpulatintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = CPU_INTRLAT_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, II_THREADED,
-					   cpuv, "intrlat"))
-		panic( "install_cpulatintr: Can't reserve interrupt.");
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND0_MAXMASK,
-				cpulatintr, NULL, NULL))
-		panic( "install_cpulatintr: Can't connect interrupt.");
-
-	if (!install_cpulat_first) {
-		install_cpulat_first++;
-		idbg_addfunc("tstamp_debug", (void (*)())idbg_tstamp_debug);
-#if defined(SPLDEBUG) || defined(SPLDEBUG_CPU_EVENTS)
-		idbg_addfunc("splx_log", (void (*)())idbg_splx_log);
-#endif /* SPLDEBUG || SPLDEBUG_CPU_EVENTS */
-	}
-}
-#endif /* BRINGUP */
-
-#endif /* DEBUG_INTR_TSTAMP */
-
-#ifndef BRINGUP
-/* ARGSUSED */
-static void
-dbgintr(void *arg)
-{
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + DEBUG_INTR_A + cputolocalslice(cpuid()));
-
-	debug("zing");
-	return;
-}
-
-
-void
-install_dbgintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = N_INTPEND_BITS + DEBUG_INTR_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
-		panic("install_dbgintr: Can't reserve interrupt. "
-			" intr_bit %d" ,intr_bit);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
-				dbgintr, NULL, NULL))
-		panic("install_dbgintr: Can't connect interrupt.");
-
-#ifdef DEBUG_INTR_TSTAMP
-	/* Set up my interrupt latency test interrupt */
-	install_cpulatintr(cpu);
-#endif
-}
-
-/* ARGSUSED */
-static void
-tlbintr(void *arg)
-{
-	extern void tlbflush_rand(void);
-
-	/*
-	 * Hardware only clears IO interrupts so we have to clear our level
-	 * here.
-	 */
-	LOCAL_HUB_CLR_INTR(N_INTPEND_BITS + TLB_INTR_A + cputolocalslice(cpuid()));
-
-	tlbflush_rand();
-	return;
-}
-
-
-void
-install_tlbintr(cpuid_t cpu)
-{
-	int		intr_bit;
-	devfs_handle_t	cpuv = cpuid_to_vertex(cpu);
-
-	intr_bit = N_INTPEND_BITS + TLB_INTR_A + cputolocalslice(cpu);
-	if (intr_bit != intr_reserve_level(cpu, intr_bit, 1, cpuv, "DEBUG"))
-		panic("install_tlbintr: Can't reserve interrupt. "
-			" intr_bit %d" ,intr_bit);
-
-	if (intr_connect_level(cpu, intr_bit, INTPEND1_MAXMASK,
-				tlbintr, NULL, NULL))
-		panic("install_tlbintr: Can't connect interrupt.");
-
-}
-
-
-/*
- * Send an interrupt to all nodes.  Don't panic if we get an error.
- * Returns 1 if any exceptions occurred.
- */
-int
-protected_broadcast(hubreg_t intrbit)
-{
-	nodepda_t *npdap = private.p_nodepda;
-	int byte, bit, sn;
-	int error = 0;
-
-	extern int _wbadaddr_val(volatile void *, int, volatile int *);
-
-	/* Send rather than clear an interrupt. */
-	intrbit |= 0x100;
-	
-	for (byte = 0; byte < NASID_MASK_BYTES; byte++) {
-		for (bit = 0; bit < 8; bit++) {
-			if (npdap->nasid_mask[byte] & (1 << bit)) {
-				nasid_t nasid = byte * 8 + bit;
-				for (sn=0; sn<NUM_SUBNODES; sn++) {
-					error += _wbadaddr_val(REMOTE_HUB_PI_ADDR(nasid,
-					      sn, PI_INT_PEND_MOD),
-					      sizeof(hubreg_t),
-					      (volatile int *)&intrbit);
-				}
-			}
-		}
-	}
-
-	return error;
-}
-
-
-/*
- * Poll the interrupt register to see if another cpu has asked us
- * to drop into the debugger (without lowering spl).
- */
-void
-chkdebug(void)
-{
-	if (LOCAL_HUB_L(PI_INT_PEND1) & (1L << (DEBUG_INTR_A + cputolocalslice(cpuid()))))
-		dbgintr((void *)NULL);
-}
-
-
-/*
- * Install special graphics interrupt.
- */
-void
-install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg)
-{
-	int intr_bit = GFX_INTR_A + cputolocalslice(cpu);
-
-	if (intr_connect_level(cpu, intr_bit, swlevel,
-				intr_func, intr_arg, NULL))
-		panic("install_gfxintr: Can't connect interrupt.");
-}
-
-
-/*
- * Install page migration interrupt handler.
- */
-void
-hub_migrintr_init(cnodeid_t cnode)
-{
-	cpuid_t cpu = cnodetocpu(cnode);
-	int intr_bit = INT_PEND0_BASELVL + PG_MIG_INTR;
-
-	if (numnodes == 1){
-		/* 
-		 * No migration with just one node..
-		 */
-		return;
-	}
-	
-	if (cpu != -1) {
-		if (intr_connect_level(cpu, intr_bit, 0,
-			       (intr_func_t) migr_intr_handler, 0, (intr_func_t) migr_intr_prologue_handler))
-			panic( "hub_migrintr_init: Can't connect interrupt.");
-	}
-}
-
-
-/*
- * Cause all CPUs to stop by sending them each a DEBUG interrupt.
- * Parameter is actually a (cpumask_t *).
- */
-void
-debug_stop_all_cpus(void *stoplist)
-{
-	int cpu;
-	ulong level;
-
-	for (cpu=0; cpu<maxcpus; cpu++) {
-		if (cpu == cpuid())
-			continue;
-		if (!cpu_enabled(cpu))
-		        continue;
-		/* "-1" is the old style parameter OR could be the new style
-		 * if no-one is currently stopped.  We only stop the
-		 * requested cpus, the others are already stopped (probably
-		 * at a breakpoint).
-		 */
-
-		if (((cpumask_t *)stoplist != (cpumask_t *)-1LL) &&
-		    (!CPUMASK_TSTB(*(cpumask_t*)stoplist, cpu)))
-			continue;
-
-		/*
-		 * CPU lslice A gets level DEBUG_INTR_A
-		 * CPU lslice B gets level DEBUG_INTR_B
-		 */
-		level = DEBUG_INTR_A + LOCALCPU(get_cpu_slice(cpu));
-		/*
-		 * Convert the compact hub number to the NASID to get the
-		 * correct part of the address space.  Then set the interrupt
-		 * bit associated with the CPU we want to send the interrupt
-		 * to.
-		 */
-		REMOTE_CPU_SEND_INTR(cpu, N_INTPEND_BITS + level);
-
-	}
-}
-
-#endif /* BRINGUP */
-
-struct hardwired_intr_s {
-	signed char level;
-	int flags;
-	char *name;
-} const hardwired_intr[] = {
-	{ INT_PEND0_BASELVL + RESERVED_INTR,	0,	"Reserved" },
-	{ INT_PEND0_BASELVL + GFX_INTR_A,	0, 	"Gfx A" },
-	{ INT_PEND0_BASELVL + GFX_INTR_B,	0, 	"Gfx B" },
-	{ INT_PEND0_BASELVL + PG_MIG_INTR,	II_THREADED, "Migration" },
-	{ INT_PEND0_BASELVL + UART_INTR,	II_THREADED, "Bedrock/L1" },
-	{ INT_PEND0_BASELVL + CC_PEND_A,	0,	"Crosscall A" },
-	{ INT_PEND0_BASELVL + CC_PEND_B,	0,	"Crosscall B" },
-	{ INT_PEND1_BASELVL + CLK_ERR_INTR,	II_ERRORINT, "Clock Error" },
-	{ INT_PEND1_BASELVL + COR_ERR_INTR_A,	II_ERRORINT, "Correctable Error A" },
-	{ INT_PEND1_BASELVL + COR_ERR_INTR_B,	II_ERRORINT, "Correctable Error B" },
-	{ INT_PEND1_BASELVL + MD_COR_ERR_INTR,	II_ERRORINT, "MD Correct. Error" },
-	{ INT_PEND1_BASELVL + NI_ERROR_INTR,	II_ERRORINT, "NI Error" },
-	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_A,	II_ERRORINT, "Remote NI Error"},
-	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_B,	II_ERRORINT, "Remote NI Error"},
-	{ INT_PEND1_BASELVL + MSC_PANIC_INTR,	II_ERRORINT, "MSC Panic" },
-	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_A,	II_ERRORINT, "LLP Pfail WAR" },
-	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_B,	II_ERRORINT, "LLP Pfail WAR" },
-	{ INT_PEND1_BASELVL + NACK_INT_A,	0, "CPU A Nack count == NACK_CMP" },
-	{ INT_PEND1_BASELVL + NACK_INT_B,	0, "CPU B Nack count == NACK_CMP" },
-	{ INT_PEND1_BASELVL + LB_ERROR,		0, "Local Block Error" },
-	{ INT_PEND1_BASELVL + XB_ERROR,		0, "Local XBar Error" },
-	{ -1, 0, (char *)NULL},
-};
-
-/*
- * Reserve all of the hardwired interrupt levels so they're not used as
- * general purpose bits later.
- */
-void
-intr_reserve_hardwired(cnodeid_t cnode)
-{
-	cpuid_t cpu;
-	int level;
-	int i;
-	char subnode_done[NUM_SUBNODES];
-
-	// cpu = cnodetocpu(cnode);
-	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
-		if (cpuid_to_cnodeid(cpu) == cnode) {
-			break;
-		}
-	}
-	if (cpu == smp_num_cpus) cpu = CPU_NONE;
-	if (cpu == CPU_NONE) {
-		printk("Node %d has no CPUs", cnode);
-		return;
-	}
-
-	for (i=0; i<NUM_SUBNODES; i++)
-		subnode_done[i] = 0;
-
-	for (; cpu<smp_num_cpus && cpu_enabled(cpu) && cpuid_to_cnodeid(cpu) == cnode; cpu++) {
-		int which_subnode = cpuid_to_subnode(cpu);
-		if (subnode_done[which_subnode])
-			continue;
-		subnode_done[which_subnode] = 1;
-
-		for (i = 0; hardwired_intr[i].level != -1; i++) {
-			level = hardwired_intr[i].level;
-
-			if (level != intr_reserve_level(cpu, level,
-						hardwired_intr[i].flags,
-						(devfs_handle_t) NULL,
-						hardwired_intr[i].name))
-				panic("intr_reserve_hardwired: Can't reserve level %d.", level);
-		}
-	}
-}
-
-
-/*
- * Check and clear interrupts.
- */
-/*ARGSUSED*/
-static void
-intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level,
-		char *name)
-{
-	volatile hubreg_t bits;
-	int i;
-
-	/* Check pending interrupts */
-	if ((bits = HUB_L(pend)) != 0) {
-		for (i = 0; i < N_INTPEND_BITS; i++) {
-			if (bits & (1 << i)) {
-#ifdef INTRDEBUG
-				PRINT_WARNING("Nasid %d interrupt bit %d set in %s",
-					nasid, i, name);
-#endif
-				LOCAL_HUB_CLR_INTR(base_level + i);
-			}
-		}
-	}
-}
-
-/*
- * Clear out our interrupt registers.
- */
-void
-intr_clear_all(nasid_t nasid)
-{
-	int	sn;
-
-	for(sn=0; sn<NUM_SUBNODES; sn++) {
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_A, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_B, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_A, 0);
-		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_B, 0);
-	
-		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND0),
-				INT_PEND0_BASELVL, "INT_PEND0");
-		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND1),
-				INT_PEND1_BASELVL, "INT_PEND1");
-	}
-}
-
-/* 
- * Dump information about a particular interrupt vector.
- */
-static void
-dump_vector(intr_info_t *info, intr_vector_t *vector, int bit, hubreg_t ip,
-		hubreg_t ima, hubreg_t imb, void (*pf)(char *, ...))
-{
-	hubreg_t value = 1LL << bit;
-
-	pf("  Bit %02d: %s: func 0x%x arg 0x%x prefunc 0x%x\n",
-		bit, info->ii_name,
-		vector->iv_func, vector->iv_arg, vector->iv_prefunc);
-	pf("   vertex 0x%x %s%s",
-		info->ii_owner_dev,
-		((info->ii_flags) & II_RESERVE) ? "R" : "U",
-		((info->ii_flags) & II_INUSE) ? "C" : "-");
-	pf("%s%s%s%s",
-		ip & value ? "P" : "-",
-		ima & value ? "A" : "-",
-		imb & value ? "B" : "-",
-		((info->ii_flags) & II_ERRORINT) ? "E" : "-");
-	pf("\n");
-}
-
-
-/*
- * Dump information about interrupt vector assignment.
- */
-void
-intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...))
-{
-	nodepda_t *npda;
-	int ip, sn, bit;
-	intr_vecblk_t *dispatch;
-	hubreg_t ipr, ima, imb;
-	nasid_t nasid;
-
-	if ((cnode < 0) || (cnode >= numnodes)) {
-		pf("intr_dumpvec: cnodeid out of range: %d\n", cnode);
-		return ;
-	}
-
-	nasid = COMPACT_TO_NASID_NODEID(cnode);
-
-	if (nasid == INVALID_NASID) {
-		pf("intr_dumpvec: Bad cnodeid: %d\n", cnode);
-		return ;
-	}
-		
-
-	npda = NODEPDA(cnode);
-
-	for (sn = 0; sn < NUM_SUBNODES; sn++) {
-		for (ip = 0; ip < 2; ip++) {
-			dispatch = ip ? &(SNPDA(npda,sn)->intr_dispatch1) : &(SNPDA(npda,sn)->intr_dispatch0);
-			ipr = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_PEND1 : PI_INT_PEND0);
-			ima = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_A : PI_INT_MASK0_A);
-			imb = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_B : PI_INT_MASK0_B);
-	
-			pf("Node %d INT_PEND%d:\n", cnode, ip);
-	
-			if (dispatch->ithreads_enabled)
-				pf(" Ithreads enabled\n");
-			else
-				pf(" Ithreads disabled\n");
-			pf(" vector_count = %d, vector_state = %d\n",
-				dispatch->vector_count,
-				dispatch->vector_state);
-			pf(" CPU A count %d, CPU B count %d\n",
- 		   	dispatch->cpu_count[0],
- 		   	dispatch->cpu_count[1]);
-			pf(" &vector_lock = 0x%x\n",
-				&(dispatch->vector_lock));
-			for (bit = 0; bit < N_INTPEND_BITS; bit++) {
-				if ((dispatch->info[bit].ii_flags & II_RESERVE) ||
-			    	(ipr & (1L << bit))) {
-					dump_vector(&(dispatch->info[bit]),
-					    	&(dispatch->vectors[bit]),
-					    	bit, ipr, ima, imb, pf);
-				}
-			}
-			pf("\n");
-		}
-	}
-}
-
diff -Nru a/arch/ia64/sn/io/ml_iograph.c b/arch/ia64/sn/io/ml_iograph.c
--- a/arch/ia64/sn/io/ml_iograph.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/ml_iograph.c	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -13,6 +12,9 @@
 #include <linux/slab.h>
 #include <linux/ctype.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
@@ -30,8 +32,6 @@
 #include <asm/sn/xtalk/xtalk_private.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 
-extern int maxnodes;
-
 /* #define IOGRAPH_DEBUG */
 #ifdef IOGRAPH_DEBUG
 #define DBG(x...) printk(x)
@@ -107,10 +107,10 @@
 #ifdef LATER
 	    if (!is_headless_node_vertex(master)) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("volunteer for widgets: vertex %v has no info label",
+		printk(KERN_WARNING  "volunteer for widgets: vertex %v has no info label",
 			xswitch);
 #else
-		PRINT_WARNING("volunteer for widgets: vertex 0x%x has no info label",
+		printk(KERN_WARNING  "volunteer for widgets: vertex 0x%x has no info label",
 			xswitch);
 #endif
 	    }
@@ -155,11 +155,11 @@
 #ifdef LATER
 	    if (!is_headless_node_vertex(hubv)) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("assign_widgets_to_volunteers:vertex %v has "
+		printk(KERN_WARNING  "assign_widgets_to_volunteers:vertex %v has "
 			" no info label",
 			xswitch);
 #else
-		PRINT_WARNING("assign_widgets_to_volunteers:vertex 0x%x has "
+		printk(KERN_WARNING  "assign_widgets_to_volunteers:vertex 0x%x has "
 			" no info label",
 			xswitch);
 #endif
@@ -184,9 +184,6 @@
 	 */
 	for (widgetnum=HUB_WIDGET_ID_MIN; widgetnum <= HUB_WIDGET_ID_MAX; widgetnum++) {
 
-#ifndef BRINGUP
-		int i;
-#endif
 		/*
 		 * Ignore disabled/empty ports.
 		 */
@@ -244,7 +241,7 @@
 	cnodeid_t cnode;
 	nasid_t nasid;
 	lboard_t *board;
-
+	
 	/*
 	 * Init. the board-to-hwgraph link early, so FRU analyzer
 	 * doesn't trip on leftover values if we panic early on.
@@ -267,55 +264,6 @@
 	hubio_init();
 }
 
-#ifdef LATER
-/* There is an identical definition of this in os/scheduler/runq.c */
-#define INIT_COOKIE(cookie) cookie.must_run = 0; cookie.cpu = PDA_RUNANYWHERE
-/*
- * These functions absolutely doesn't belong here.  It's  here, though, 
- * until the scheduler provides a platform-independent version
- * that works the way it should.  The interface will definitely change, 
- * too.  Currently used only in this file and by io/cdl.c in order to
- * bind various I/O threads to a CPU on the proper node.
- */
-cpu_cookie_t
-setnoderun(cnodeid_t cnodeid)
-{
-	int i;
-	cpuid_t cpunum;
-	cpu_cookie_t cookie;
-
-	INIT_COOKIE(cookie);
-	if (cnodeid == CNODEID_NONE)
-		return(cookie);
-
-	/*
-	 * Do a setmustrun to one of the CPUs on the specified
-	 * node.
-	 */
-	if ((cpunum = CNODE_TO_CPU_BASE(cnodeid)) == CPU_NONE) {
-		return(cookie);
-	}
-
-	cpunum += CNODE_NUM_CPUS(cnodeid) - 1;
-
-	for (i = 0; i < CNODE_NUM_CPUS(cnodeid); i++, cpunum--) {
-
-		if (cpu_enabled(cpunum)) {
-			cookie = setmustrun(cpunum);
-			break;
-		}
-	}
-
-	return(cookie);
-}
-
-void
-restorenoderun(cpu_cookie_t cookie)
-{
-	restoremustrun(cookie);
-}
-#endif	/* LATER */
-
 #ifdef LINUX_KERNEL_THREADS
 static struct semaphore io_init_sema;
 #endif
@@ -445,6 +393,7 @@
 	slotid_t		slot;
 	lboard_t		*board = NULL;
 	char			buffer[16];
+	slotid_t get_widget_slotnum(int xbow, int widget);
 	
 	DBG("\nio_xswitch_widget_init: hubv 0x%p, xswitchv 0x%p, widgetnum 0x%x\n", hubv, xswitchv, widgetnum);
 	/*
@@ -507,6 +456,7 @@
 {
 		lboard_t dummy;
 
+
 			if (board) {
 				DBG("io_xswitch_widget_init: Found KLTYPE_IOBRICK Board 0x%p brd_type 0x%x\n", board, board->brd_type);
 			} else {
@@ -517,7 +467,6 @@
 }
 
 			/*
-			 * BRINGUP
 	 		 * Make sure we really want to say xbrick, pbrick,
 			 * etc. rather than XIO, graphics, etc.
 	 		 */
@@ -534,14 +483,10 @@
 				"%cbrick" "/%s/%d",
 				buffer,
 #endif
-#ifdef BRINGUP
 
 				(board->brd_type == KLTYPE_IBRICK) ? 'I' :
 				(board->brd_type == KLTYPE_PBRICK) ? 'P' :
 				(board->brd_type == KLTYPE_XBRICK) ? 'X' : '?',
-#else
-				toupper(MODULE_GET_BTCHAR(NODEPDA(cnode)->module_id)),
-#endif /* BRINGUP */
 				EDGE_LBL_XTALK, widgetnum);
 		} 
 		
@@ -563,11 +508,7 @@
 		 */
 		if (is_master_baseio(nasid,
 				     NODEPDA(cnode)->module_id,
-#ifdef BRINGUP
  				     get_widget_slotnum(0,widgetnum))) {
-#else
-	<<< BOMB! >>> Need a new way to get slot numbers on IP35/IP37
-#endif
 			extern void klhwg_baseio_inventory_add(devfs_handle_t,
 							       cnodeid_t);
 			module 	= NODEPDA(cnode)->module_id;
@@ -582,7 +523,6 @@
 					(lboard_t *)KL_CONFIG_INFO(nasid),
 					module);
 				/*
-			 	 * BRINGUP
 				 * Change iobrick to correct i/o brick
 				 */
 #ifdef SUPPORT_PRINTING_M_FORMAT
@@ -594,11 +534,7 @@
 					NODEPDA(cnode)->module_id,
 					EDGE_LBL_XTALK, widgetnum);
 			} else {
-#ifdef BRINGUP
 				slot = get_widget_slotnum(0, widgetnum);
-#else
-	<<< BOMB! Need a new way to get slot numbers on IP35/IP37
-#endif
 				board = get_board_name(nasid, module, slot,
 								new_name);
 				/*
@@ -729,41 +665,25 @@
 		    GRAPH_SUCCESS)
 			continue;
 
-#if defined (CONFIG_SGI_IP35) || defined (CONFIG_IA64_SGI_SN1) || defined (CONFIG_IA64_GENERIC)
 		board = find_lboard_module((lboard_t *)KL_CONFIG_INFO(nasid),
 				NODEPDA(cnodeid)->module_id);
-#else
-		{
-		slotid_t	slot;
-		slot = get_widget_slotnum(xbow_num, widgetnum);
-		board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(nasid),
-				    NODEPDA(cnodeid)->module_id, slot);
-		}
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
 		if (board == NULL && peer_nasid != INVALID_NASID) {
 			/*
 			 * Try to find the board on our peer
 			 */
-#if defined (CONFIG_SGI_IP35) || defined (CONFIG_IA64_SGI_SN1) || defined (CONFIG_IA64_GENERIC)
 			board = find_lboard_module(
 				(lboard_t *)KL_CONFIG_INFO(peer_nasid),
 				NODEPDA(cnodeid)->module_id);
-
-#else
-			board = find_lboard_modslot((lboard_t *)KL_CONFIG_INFO(peer_nasid),
-						    NODEPDA(cnodeid)->module_id, slot);
-
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
 		}
 		if (board == NULL) {
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Could not find PROM info for vertex %v, "
+			printk(KERN_WARNING  "Could not find PROM info for vertex %v, "
 				"FRU analyzer may fail",
 				vhdl);
 #else
-			PRINT_WARNING("Could not find PROM info for vertex 0x%x, "
+			printk(KERN_WARNING  "Could not find PROM info for vertex 0x%p, "
 				"FRU analyzer may fail",
-				vhdl);
+				(void *)vhdl);
 #endif
 			return;
 		}
@@ -918,7 +838,6 @@
 		DBG("io_init_node: Found XBOW widget_partnum= 0x%x\n", widget_partnum);
 		npdap->basew_id = 0;
 
-#if defined(BRINGUP)
 	} else if (widget_partnum == XG_WIDGET_PART_NUM) {
 		/* 
 		 * OK, WTF do we do here if we have an XG direct connected to a HUB/Bedrock???
@@ -926,11 +845,10 @@
 		 */
 		npdap->basew_id = 0;
 		npdap->basew_id = (((*(volatile int32_t *)(NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0) + BRIDGE_WID_CONTROL))) & WIDGET_WIDGET_ID);
-#endif
 	} else { 
 		npdap->basew_id = (((*(volatile int32_t *)(NODE_SWIN_BASE(COMPACT_TO_NASID_NODEID(cnodeid), 0) + BRIDGE_WID_CONTROL))) & WIDGET_WIDGET_ID);
 
-		panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widgt ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, hubv);
+		panic(" ****io_init_node: Unknown Widget Part Number 0x%x Widgt ID 0x%x attached to Hubv 0x%p ****\n", widget_partnum, npdap->basew_id, (void *)hubv);
 
 		/*NOTREACHED*/
 	}
@@ -1037,7 +955,7 @@
 #define __DEVSTR3 	"/lun/0/disk/partition/"
 #define	__DEVSTR4	"/../ef"
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1)
 /*
  * Currently, we need to allow for 5 IBrick slots with 1 FC each
  * plus an internal 1394.
@@ -1045,6 +963,8 @@
  * ioconfig starts numbering SCSI's at NUM_BASE_IO_SCSI_CTLR.
  */
 #define NUM_BASE_IO_SCSI_CTLR 6
+#else
+#define NUM_BASE_IO_SCSI_CTLR 6
 #endif
 /*
  * This tells ioconfig where it can start numbering scsi controllers.
@@ -1072,7 +992,6 @@
 		for (i=0; i<NUM_BASE_IO_SCSI_CTLR; i++)
 			base_io_scsi_ctlr_vhdl[i] = GRAPH_VERTEX_NONE;
 	}
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
 	{
 	/*
 	 * May want to consider changing the SN0 code, above, to work more like
@@ -1129,14 +1048,10 @@
 
 	hwgraph_vertex_unref(base_ibrick_xbridge_vhdl);
 	}
-#else
-#pragma error Bomb!
-#endif
 }
 
 
 #include <asm/sn/ioerror_handling.h>
-extern devfs_handle_t 	ioc3_console_vhdl_get(void);
 devfs_handle_t		sys_critical_graph_root = GRAPH_VERTEX_NONE;
 
 /* Define the system critical vertices and connect them through
@@ -1251,6 +1166,7 @@
 {
 	char 			name[MAXDEVNAME];
 	devfs_handle_t		console_vhdl, pci_vhdl, enet_vhdl;
+	devfs_handle_t		ioc3_console_vhdl_get(void);
 
 
 	DBG("baseio_ctlr_num_set; FIXME\n");
@@ -1335,7 +1251,7 @@
 		rtn_val = pcibr_alloc_all_rrbs(vhdl, 0, 4,1, 4,0, 0,0, 0,0);
 	}
 	if (rtn_val)
-		PRINT_WARNING("sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
+		printk(KERN_WARNING  "sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
 
 	if ((vendor_list[5] != PCIIO_VENDOR_ID_NONE) && 
 	    (vendor_list[7] != PCIIO_VENDOR_ID_NONE)) {
@@ -1355,7 +1271,7 @@
 		rtn_val = pcibr_alloc_all_rrbs(vhdl, 1, 4,1, 4,0, 0,0, 0,0);
 	}
 	if (rtn_val)
-		PRINT_WARNING("sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
+		printk(KERN_WARNING  "sn00_rrb_alloc: pcibr_alloc_all_rrbs failed");
 }
 
 
@@ -1379,7 +1295,7 @@
 #endif
 
 	active = 0;
-	for (cnodeid = 0; cnodeid < maxnodes; cnodeid++) {
+	for (cnodeid = 0; cnodeid < numnodes; cnodeid++) {
 #ifdef LINUX_KERNEL_THREADS
 		char thread_name[16];
 		extern int io_init_pri;
@@ -1428,7 +1344,7 @@
 
 #endif /* LINUX_KERNEL_THREADS */
 
-	for (cnodeid = 0; cnodeid < maxnodes; cnodeid++)
+	for (cnodeid = 0; cnodeid < numnodes; cnodeid++)
 		/*
 	 	 * Update information generated by IO init.
 		 */
diff -Nru a/arch/ia64/sn/io/module.c b/arch/ia64/sn/io/module.c
--- a/arch/ia64/sn/io/module.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/module.c	Fri Mar 15 17:51:02 2002
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
@@ -25,7 +26,7 @@
 #include <asm/sn/sn_cpuid.h>
 
 
-/* #define LDEBUG	1	*/
+/* #define LDEBUG	1 */
 
 #ifdef LDEBUG
 #define DPRINTF		printk
@@ -173,9 +174,35 @@
     lboard_t	       *board;
     klmod_serial_num_t *comp;
     char * bcopy(const char * src, char * dest, int count);
+    char serial_number[16];
+
+    /*
+     * record brick serial number
+     */
+    board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
+
+    if (! board || KL_CONFIG_DUPLICATE_BOARD(board))
+    {
+#if	LDEBUG
+	printf ("module_probe_snum: no IP35 board found!\n");
+#endif
+	return 0;
+    }
+
+    board_serial_number_get( board, serial_number );
+    if( serial_number[0] != '\0' ) {
+	encode_str_serial( serial_number, m->snum.snum_str );
+	m->snum_valid = 1;
+    }
+#if	LDEBUG
+    else {
+	printf("module_probe_snum: brick serial number is null!\n");
+    }
+    printf("module_probe_snum: brick serial number == %s\n", serial_number);
+#endif /* DEBUG */
 
     board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid),
-			KLTYPE_MIDPLANE8);
+			KLTYPE_IOBRICK_XBOW);
 
     if (! board || KL_CONFIG_DUPLICATE_BOARD(board))
 	return 0;
@@ -196,13 +223,13 @@
 
 	    if (comp->snum.snum_str[0] != '\0') {
 		bcopy(comp->snum.snum_str,
-		      m->snum.snum_str,
+		      m->sys_snum,
 		      MAX_SERIAL_NUM_SIZE);
-		m->snum_valid = 1;
+		m->sys_snum_valid = 1;
 	    }
     }
 
-    if (m->snum_valid)
+    if (m->sys_snum_valid)
 	return 1;
     else {
 	DPRINTF("Invalid serial number for module %d, "
@@ -227,8 +254,7 @@
     for (node = 0; node < numnodes; node++) {
 	nasid = COMPACT_TO_NASID_NODEID(node);
 
-	board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid),
-			    KLTYPE_IP27);
+	board = find_lboard((lboard_t *) KL_CONFIG_INFO(nasid), KLTYPE_SNIA);
 	ASSERT(board);
 
 	m = module_add_node(board->brd_module, node);
@@ -241,7 +267,7 @@
 	    nserial);
 
     if (nserial == 0)
-	PRINT_WARNING("io_module_init: No serial number found.\n");
+	printk(KERN_WARNING  "io_module_init: No serial number found.\n");
 }
 
 elsc_t *get_elsc(void)
diff -Nru a/arch/ia64/sn/io/pci.c b/arch/ia64/sn/io/pci.c
--- a/arch/ia64/sn/io/pci.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/pci.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /* 
  *
+ * SNI64 specific PCI support for SNI IO.
+ *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * SNI64 specific PCI support for SNI IO.
- *
- * Copyright (C) 1997, 1998, 2000 Colin Ngam
+ * Copyright (c) 1997, 1998, 2000-2001 Silicon Graphics, Inc.  All rights reserved.
  */
 #include <linux/init.h>
 #include <linux/types.h>
@@ -14,7 +14,8 @@
 #include <linux/pci.h>
 #include <asm/sn/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
@@ -237,10 +238,6 @@
 
 	sgi_master_io_infr_init();
 
-#ifdef BRINGUP
-	if ( IS_RUNNING_ON_SIMULATOR() )
-		return;
-#endif
 	/* sn1_io_infrastructure_init(); */
 	pci_conf = snia64_pci_ops;
 }
@@ -251,8 +248,6 @@
         int 		i;
 	unsigned int 	size;
 
-	devfs_handle_t	bridge_vhdl = pci_bus_to_vertex(d->bus->number);
-
         /* IOC3 only decodes 0x20 bytes of the config space, reading
 	 * beyond that is relatively benign but writing beyond that
 	 * (especially the base address registers) will shut down the
@@ -294,5 +289,12 @@
         d->subsystem_device = 0;
 
 }
+
+#else
+void sn1_pci_find_bios(void) {}
+void pci_fixup_ioc3(struct pci_dev *d) {}
+struct list_head pci_root_buses;
+struct list_head pci_root_buses;
+struct list_head pci_devices;
 
 #endif /* CONFIG_PCI */
diff -Nru a/arch/ia64/sn/io/pci_bus_cvlink.c b/arch/ia64/sn/io/pci_bus_cvlink.c
--- a/arch/ia64/sn/io/pci_bus_cvlink.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/pci_bus_cvlink.c	Fri Mar 15 17:51:03 2002
@@ -4,19 +4,21 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/pci.h>
+#include <linux/pci_ids.h>
 #include <linux/sched.h>
 #include <linux/ioport.h>
 #include <asm/sn/types.h>
 #include <asm/sn/hack.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/io.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/param.h>
 #include <asm/sn/pio.h>
@@ -26,20 +28,19 @@
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/hcl_util.h>
-#include <asm/sn/agent.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/xtalk/xtalkaddrs.h>
 #include <asm/sn/klconfig.h>
-#include <asm/sn/io.h>
-
+#include <asm/sn/nodepda.h>
 #include <asm/sn/pci/pciio.h>
-// #include <sys/ql.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>
-extern int bridge_rev_b_data_check_disable;
 #include <asm/sn/pci/pci_bus_cvlink.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern int bridge_rev_b_data_check_disable;
 
-#define MAX_PCI_XWIDGET 256
 devfs_handle_t busnum_to_pcibr_vhdl[MAX_PCI_XWIDGET];
 nasid_t busnum_to_nid[MAX_PCI_XWIDGET];
 void * busnum_to_atedmamaps[MAX_PCI_XWIDGET];
@@ -55,6 +56,8 @@
 struct ioports_to_tlbs_s ioports_to_tlbs[MAX_IOPORTS_CHUNKS];
 unsigned long sn1_allocate_ioports(unsigned long pci_address);
 
+extern void sn1_init_irq_desc(void);
+
 
 
 /*
@@ -104,7 +107,7 @@
 	int func = 0;
 	char	name[16];
 	devfs_handle_t  pci_bus = NULL;
-	devfs_handle_t	device_vertex = NULL;
+	devfs_handle_t	device_vertex = (devfs_handle_t)NULL;
 
 	/*
 	 * Go get the pci bus vertex.
@@ -129,11 +132,25 @@
 	slot = PCI_SLOT(devfn);
 	func = PCI_FUNC(devfn);
 
-	if (func == 0)
+	/*
+	 * For a NON Multi-function card the name of the device looks like:
+	 * ../pci/1, ../pci/2 ..
+	 */
+	if (func == 0) {
         	sprintf(name, "%d", slot);
-	else
-		sprintf(name, "%d%c", slot, 'a'+func);
-
+		if (hwgraph_traverse(pci_bus, name, &device_vertex) == 
+			GRAPH_SUCCESS) {
+			if (device_vertex) {
+				return(device_vertex);
+			}
+		}
+	}
+			
+	/*
+	 * This maybe a multifunction card.  It's names look like:
+	 * ../pci/1a, ../pci/1b, etc.
+	 */
+	sprintf(name, "%d%c", slot, 'a'+func);
 	if (hwgraph_traverse(pci_bus, name, &device_vertex) != GRAPH_SUCCESS) {
 		if (!device_vertex) {
 			return(NULL);
@@ -144,6 +161,36 @@
 }
 
 /*
+ * For the given device, initialize the addresses for both the Device(x) Flush 
+ * Write Buffer register and the Xbow Flush Register for the port the PCI bus 
+ * is connected.
+ */
+static void
+set_flush_addresses(struct pci_dev *device_dev, 
+	struct sn1_device_sysdata *device_sysdata)
+{
+	pciio_info_t pciio_info = pciio_info_get(device_sysdata->vhdl);
+	pciio_slot_t pciio_slot = pciio_info_slot_get(pciio_info);
+	pcibr_soft_t pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	device_sysdata->dma_buf_sync = (volatile unsigned int *) 
+		&(bridge->b_wr_req_buf[pciio_slot].reg);
+	device_sysdata->xbow_buf_sync = (volatile unsigned int *)
+		XBOW_PRIO_LINKREGS_PTR(NODE_SWIN_BASE(get_nasid(), 0), 
+		pcibr_soft->bs_xid);
+#ifdef DEBUG
+
+	printk("set_flush_addresses: dma_buf_sync %p xbow_buf_sync %p\n", 
+		device_sysdata->dma_buf_sync, device_sysdata->xbow_buf_sync);
+
+	while((volatile unsigned int )*device_sysdata->dma_buf_sync);
+	while((volatile unsigned int )*device_sysdata->xbow_buf_sync);
+#endif
+
+}
+
+/*
  * Most drivers currently do not properly tell the arch specific pci dma
  * interfaces whether they can handle A64. Here is where we privately
  * keep track of this.
@@ -189,7 +236,7 @@
  *	Address.  This address via the tlb entries generates the PCI Address 
  *	allocated by the SN1 IO Infrastructure Layer.
  */
-static unsigned long sn1_ioport_num = 0x100; /* Reserve room for Legacy stuff */
+static unsigned long sn1_ioport_num = 0x1000; /* Reserve room for Legacy stuff */
 unsigned long
 sn1_allocate_ioports(unsigned long pci_address)
 {
@@ -209,17 +256,19 @@
 	 * Manual for details.
 	 */
 	ioport_index = sn1_ioport_num / SN1_IOPORTS_UNIT;
-	ioports_to_tlbs[ioport_index].ppn = pci_address;
+
 	ioports_to_tlbs[ioport_index].p = 1; /* Present Bit */
-	ioports_to_tlbs[ioport_index].ma = 5; /* Memory Attributes */
-	ioports_to_tlbs[ioport_index].a = 0; /* Set Data Access Bit Fault */
-	ioports_to_tlbs[ioport_index].d = 0; /* Dirty Bit */
-	ioports_to_tlbs[ioport_index].pl = 3;/* Privilege Level - All levels can R/W*/
-	ioports_to_tlbs[ioport_index].ar = 2; /* Access Rights - R/W only*/
+	ioports_to_tlbs[ioport_index].rv_1 = 0; /* 1 Bit */
+	ioports_to_tlbs[ioport_index].ma = 4; /* Memory Attributes 3 bits*/
+	ioports_to_tlbs[ioport_index].a = 1; /* Set Data Access Bit Fault 1 Bit*/
+	ioports_to_tlbs[ioport_index].d = 1; /* Dirty Bit */
+	ioports_to_tlbs[ioport_index].pl = 0;/* Privilege Level - All levels can R/W*/
+	ioports_to_tlbs[ioport_index].ar = 3; /* Access Rights - R/W only*/
+	ioports_to_tlbs[ioport_index].ppn = pci_address >> 12; /* 4K page size */
 	ioports_to_tlbs[ioport_index].ed = 0; /* Exception Deferral Bit */
 	ioports_to_tlbs[ioport_index].ig = 0; /* Ignored */
 
-	printk("sn1_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index].ppn);
+	/* printk("sn1_allocate_ioports: ioport_index 0x%x ioports_to_tlbs 0x%p\n", ioport_index, ioports_to_tlbs[ioport_index]); */
 	
 	sn1_ioport_num += SN1_IOPORTS_UNIT;
 
@@ -241,18 +290,29 @@
 	struct pci_dev *device_dev = NULL;
 	struct sn1_widget_sysdata *widget_sysdata;
 	struct sn1_device_sysdata *device_sysdata;
+#ifdef SN1_IOPORTS
 	unsigned long ioport;
+#endif
 	pciio_intr_t intr_handle;
 	int cpuid, bit;
-	devfs_handle_t *device_vertex;
+	devfs_handle_t device_vertex;
 	pciio_intr_line_t lines;
 	extern void sn1_pci_find_bios(void);
+#ifdef CONFIG_IA64_SGI_SN2
+	extern int numnodes;
+	int cnode;
+#endif /* CONFIG_IA64_SGI_SN2 */
 
 
-unsigned long   res;
-
 	if (arg == 0) {
+		sn1_init_irq_desc();
 		sn1_pci_find_bios();
+#ifdef CONFIG_IA64_SGI_SN2
+		for (cnode = 0; cnode < numnodes; cnode++) {
+				extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
+				intr_init_vecblk(NODEPDA(cnode), cnode, 0);
+		} 
+#endif /* CONFIG_IA64_SGI_SN2 */
 		return;
 	}
 
@@ -274,13 +334,6 @@
 #endif
 	done_probing = 1;
 
-	if ( IS_RUNNING_ON_SIMULATOR() ) {
-		printk("sn1_pci_fixup not supported on simulator.\n");
-		return;
-	}
-
-#ifdef REAL_HARDWARE
-
 	/*
 	 * Initialize the pci bus vertex in the pci_bus struct.
 	 */
@@ -296,8 +349,35 @@
  	 * set the root start and end so that drivers calling check_region()
 	 * won't see a conflict
 	 */
-	ioport_resource.start |= IO_SWIZ_BASE;
-	ioport_resource.end |= (HSPEC_SWIZ_BASE-1);
+#ifdef SN1_IOPORTS
+	ioport_resource.start  = sn1_ioport_num;
+	ioport_resource.end = 0xffff;
+#else
+#if defined(CONFIG_IA64_SGI_SN1)
+	if ( IS_RUNNING_ON_SIMULATOR() ) {
+		/*
+		 * IDE legacy IO PORTs are supported in Medusa.
+		 * Just open up IO PORTs from 0 .. ioport_resource.end.
+		 */
+		ioport_resource.start = 0;
+	} else {
+		/*
+		 * We do not support Legacy IO PORT numbers.
+		 */
+		ioport_resource.start |= IO_SWIZ_BASE | __IA64_UNCACHED_OFFSET;
+	}
+	ioport_resource.end |= (HSPEC_SWIZ_BASE-1) | __IA64_UNCACHED_OFFSET;
+#else
+	// Need something here for sn2.... ZXZXZX
+#endif
+#endif
+
+	/*
+	 * Set the root start and end for Mem Resource.
+	 */
+	iomem_resource.start = 0;
+	iomem_resource.end = 0xffffffffffffffff;
+
 	/*
 	 * Initialize the device vertex in the pci_dev struct.
 	 */
@@ -307,6 +387,7 @@
 		u16 cmd;
 		devfs_handle_t vhdl;
 		unsigned long size;
+		extern int bit_pos_to_irq(int);
 
 		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 				device_dev->device == PCI_DEVICE_ID_SGI_IOC3) {
@@ -320,6 +401,12 @@
 					GFP_KERNEL);
 		device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
 		device_sysdata->isa64 = 0;
+		/*
+		 * Set the xbridge Device(X) Write Buffer Flush and Xbow Flush 
+		 * register addresses.
+		 */
+		(void) set_flush_addresses(device_dev, device_sysdata);
+
 		device_dev->sysdata = (void *) device_sysdata;
 		set_sn1_pci64(device_dev);
 		pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
@@ -336,11 +423,8 @@
 			size = device_dev->resource[idx].end -
 				device_dev->resource[idx].start;
 			if (size) {
-				res = 0;
-				res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
 				device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM);
-
-/* printk("sn1_pci_fixup: Mapped Address = 0x%p size = 0x%x\n", device_dev->resource[idx].start, size); */
+				device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
 			}
 			else
 				continue;
@@ -348,6 +432,7 @@
 			device_dev->resource[idx].end = 
 				device_dev->resource[idx].start + size;
 
+#ifdef CONFIG_IA64_SGI_SN1
 			/*
 			 * Adjust the addresses to go to the SWIZZLE ..
 			 */
@@ -355,15 +440,25 @@
 				device_dev->resource[idx].start & 0xfffff7ffffffffff;
 			device_dev->resource[idx].end = 
 				device_dev->resource[idx].end & 0xfffff7ffffffffff;
-			res = 0;
-			res = pciio_config_get(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + idx, 4);
+#endif
+
 			if (device_dev->resource[idx].flags & IORESOURCE_IO) {
 				cmd |= PCI_COMMAND_IO;
+#ifdef SN1_IOPORTS
 				ioport = sn1_allocate_ioports(device_dev->resource[idx].start);
-				/* device_dev->resource[idx].start = ioport; */
-				/* device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT */
+				if (ioport < 0) {
+					printk("sn1_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number);
+					continue;
+				}
+				pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff)));
+
+printk("sn1_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff)));
+
+				device_dev->resource[idx].start = ioport;
+				device_dev->resource[idx].end = ioport + SN1_IOPORTS_UNIT;
+#endif
 			}
-			else if (device_dev->resource[idx].flags & IORESOURCE_MEM)
+			if (device_dev->resource[idx].flags & IORESOURCE_MEM)
 				cmd |= PCI_COMMAND_MEMORY;
 		}
 		/*
@@ -371,17 +466,24 @@
 		 */
 		size = device_dev->resource[PCI_ROM_RESOURCE].end -
 			device_dev->resource[PCI_ROM_RESOURCE].start;
-		device_dev->resource[PCI_ROM_RESOURCE].start =
+
+		if (size) {
+			device_dev->resource[PCI_ROM_RESOURCE].start =
 			(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0, 
 				size, 0, PCIIO_BYTE_STREAM);
-		device_dev->resource[PCI_ROM_RESOURCE].end =
+			device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET;
+			device_dev->resource[PCI_ROM_RESOURCE].end =
 			device_dev->resource[PCI_ROM_RESOURCE].start + size;
 
-                /*
-                 * go through synergy swizzled space
-                 */
-		device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
-		device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
+#ifdef CONFIG_IA64_SGI_SN1
+                	/*
+                 	 * go through synergy swizzled space
+                 	 */
+			device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
+			device_dev->resource[PCI_ROM_RESOURCE].end   &= 0xfffff7ffffffffffUL;
+#endif
+
+		}
 
 		/*
 		 * Update the Command Word on the Card.
@@ -390,14 +492,11 @@
 					   /* bit gets dropped .. no harm */
 		pci_write_config_word(device_dev, PCI_COMMAND, cmd);
 
-		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, &lines);
-#ifdef BRINGUP
+		pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
 		if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
 			device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
 				lines = 1;
 		}
-
-#endif
  
 		device_sysdata = (struct sn1_device_sysdata *)device_dev->sysdata;
 		device_vertex = device_sysdata->vhdl;
@@ -406,13 +505,33 @@
 
 		bit = intr_handle->pi_irq;
 		cpuid = intr_handle->pi_cpu;
+#ifdef CONFIG_IA64_SGI_SN1
 		irq = bit_pos_to_irq(bit);
+#else /* SN2 */
+		irq = bit;
+#endif
 		irq = irq + (cpuid << 8);
-		pciio_intr_connect(intr_handle, NULL, NULL, NULL);
+		pciio_intr_connect(intr_handle);
 		device_dev->irq = irq;
+#ifdef ajmtestintr
+		{
+			int slot = PCI_SLOT(device_dev->devfn);
+			static int timer_set = 0;
+			pcibr_intr_t	pcibr_intr = (pcibr_intr_t)intr_handle;
+			pcibr_soft_t	pcibr_soft = pcibr_intr->bi_soft;
+			extern void intr_test_handle_intr(int, void*, struct pt_regs *);
+
+			if (!timer_set) {
+				intr_test_set_timer();
+				timer_set = 1;
+			}
+			intr_test_register_irq(irq, pcibr_soft, slot);
+			request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
+		}
+#endif
 
 	}
-#endif	/* REAL_HARDWARE */
+
 #if 0
 
 {
@@ -430,6 +549,10 @@
         printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
         printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
 }
+
+printk("testing Big Window: 0xC0000200c0000000 %p\n", *( (volatile uint64_t *)0xc0000200a0000000));
+printk("testing Big Window: 0xC0000200c0000008 %p\n", *( (volatile uint64_t *)0xc0000200a0000008));
+
 #endif
 
 }
@@ -472,12 +595,14 @@
 	 * Loop throught this vertex and get the Xwidgets ..
 	 */
 	for (widgetnum = HUB_WIDGET_ID_MAX; widgetnum >= HUB_WIDGET_ID_MIN; widgetnum--) {
+#if 0
         {
                 int pos;
                 char dname[256];
                 pos = devfs_generate_path(xtalk, dname, 256);
                 printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
         }
+#endif
 
 		sprintf(pathname, "%d", widgetnum);
 		xwidget = NULL;
@@ -512,12 +637,12 @@
 		 */
 		master_node_vertex = device_master_get(xwidget);
 		if (!master_node_vertex) {
-			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", xwidget);
+			printk("WARNING: pci_bus_map_create: Unable to get .master for vertex 0x%p\n", (void *)xwidget);
 		}
 	
 		hubinfo_get(master_node_vertex, &hubinfo);
 		if (!hubinfo) {
-			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", master_node_vertex);
+			printk("WARNING: pci_bus_map_create: Unable to get hubinfo for master node vertex 0x%p\n", (void *)master_node_vertex);
 			return(1);
 		} else {
 			busnum_to_nid[num_bridges - 1] = hubinfo->h_nasid;
@@ -527,12 +652,12 @@
 		 * Pre assign DMA maps needed for 32 Bits Page Map DMA.
 		 */
 		busnum_to_atedmamaps[num_bridges - 1] = (void *) kmalloc(
-			sizeof(struct sn1_dma_maps_s) * 512, GFP_KERNEL);
+			sizeof(struct sn1_dma_maps_s) * MAX_ATE_MAPS, GFP_KERNEL);
 		if (!busnum_to_atedmamaps[num_bridges - 1])
-			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, xwidget);
+			printk("WARNING: pci_bus_map_create: Unable to precreate ATE DMA Maps for busnum %d vertex 0x%p\n", num_bridges - 1, (void *)xwidget);
 
 		memset(busnum_to_atedmamaps[num_bridges - 1], 0x0, 
-			sizeof(struct sn1_dma_maps_s) * 512);
+			sizeof(struct sn1_dma_maps_s) * MAX_ATE_MAPS);
 
 	}
 
@@ -552,14 +677,10 @@
 {
 
 	devfs_handle_t devfs_hdl = NULL;
-	devfs_handle_t module_comp = NULL;
-	devfs_handle_t node = NULL;
 	devfs_handle_t xtalk = NULL;
-	graph_vertex_place_t placeptr = EDGE_PLACE_WANT_REAL_EDGES;
 	int rv = 0;
 	char name[256];
 	int master_iobrick;
-	moduleid_t iobrick_id;
 	int i;
 
 	/*
@@ -619,66 +740,4 @@
 	}
 
 	return(0);
-}
-
-/*
- * sgi_pci_intr_support -
- */
-int
-sgi_pci_intr_support (unsigned int requested_irq, device_desc_t *dev_desc,
-	devfs_handle_t *bus_vertex, pciio_intr_line_t *lines,
-	devfs_handle_t *device_vertex)
-
-{
-
-	unsigned int bus;
-	unsigned int devfn;
-	struct pci_dev *pci_dev;
-	unsigned char intr_pin = 0;
-	struct sn1_widget_sysdata *widget_sysdata;
-	struct sn1_device_sysdata *device_sysdata;
-
-	if (!dev_desc || !bus_vertex || !device_vertex) {
-		printk("WARNING: sgi_pci_intr_support: Invalid parameter dev_desc 0x%p, bus_vertex 0x%p, device_vertex 0x%p\n", dev_desc, bus_vertex, device_vertex);
-		return(-1);
-	}
-
-	devfn = (requested_irq >> 8) & 0xff;
-	bus = (requested_irq >> 16) & 0xffff;
-	pci_dev = pci_find_slot(bus, devfn);
-	widget_sysdata = (struct sn1_widget_sysdata *)pci_dev->bus->sysdata;
-	*bus_vertex = widget_sysdata->vhdl;
-	device_sysdata = (struct sn1_device_sysdata *)pci_dev->sysdata;
-	*device_vertex = device_sysdata->vhdl;
-#if 0
-	{
-		int pos;
-		char dname[256];
-		pos = devfs_generate_path(*device_vertex, dname, 256);
-		printk("%s : path= %s pos %d\n", __FUNCTION__, &dname[pos], pos);
-	}
-#endif /* BRINGUP */
-
-
-	/*
-	 * Get the Interrupt PIN.
-	 */
-	pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intr_pin);
-	*lines = (pciio_intr_line_t)intr_pin;
-
-#ifdef BRINGUP
-	/*
-	 * ioc3 can't decode the PCI_INTERRUPT_PIN field of its config
-	 * space so we have to set it here
-	 */
-	if (pci_dev->vendor == PCI_VENDOR_ID_SGI &&
-	    pci_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
-		*lines = 1;
-	}
-#endif /* BRINGUP */
-
-	/* Not supported currently */
-	*dev_desc = NULL;
-	return(0);
-
 }
diff -Nru a/arch/ia64/sn/io/pci_dma.c b/arch/ia64/sn/io/pci_dma.c
--- a/arch/ia64/sn/io/pci_dma.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/pci_dma.c	Fri Mar 15 17:51:02 2002
@@ -3,11 +3,9 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Leo Dagum
+ * Copyright (C) 2000,2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-#include <linux/config.h>
 #include <linux/types.h>
 #include <linux/mm.h>
 #include <linux/string.h>
@@ -15,36 +13,22 @@
 #include <linux/slab.h>
 #include <linux/devfs_fs_kernel.h>
 
-#ifndef LANGUAGE_C 
-#define LANGUAGE_C 99
-#endif
-#ifndef _LANGUAGE_C
-#define _LANGUAGE_C 99
-#endif
-
+#include <asm/delay.h>
 #include <asm/io.h>
 #include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/types.h>
 #include <asm/sn/alenlist.h>
 #include <asm/sn/pci/pci_bus_cvlink.h>
-
-/*
- * this is REALLY ugly, blame it on gcc's lame inlining that we
- * have to put procedures in header files
- */
-#if LANGUAGE_C == 99
-#undef LANGUAGE_C
-#endif
-#if CONFIG_IA64_SGI_IO == 99
-#undef CONFIG_IA64_SGI_IO
-#endif
+#include <asm/sn/nag.h>
 
 pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
+void free_pciio_dmamap(pcibr_dmamap_t);
 struct sn1_dma_maps_s *find_sn1_dma_map(dma_addr_t, unsigned char);
 extern devfs_handle_t busnum_to_pcibr_vhdl[];
 extern nasid_t busnum_to_nid[];
@@ -62,7 +46,7 @@
 	/*
 	 * Darn, we need to get the maps allocated for this bus.
 	 */
-	for (i=0; i<512; i++) {
+	for (i=0; i<MAX_PCI_XWIDGET; i++) {
 		if (busnum_to_pcibr_vhdl[i] == pci_bus) {
 			sn1_dma_map = busnum_to_atedmamaps[i];
 		}
@@ -71,18 +55,61 @@
 	/*
 	 * Now get a free dmamap entry from this list.
 	 */
-	for (i=0; i<512; i++, sn1_dma_map++) {
+	for (i=0; i<MAX_ATE_MAPS; i++, sn1_dma_map++) {
 		if (!sn1_dma_map->dma_addr) {
 			sn1_dma_map->dma_addr = -1;
 			return( (pciio_dmamap_t) sn1_dma_map );
 		}
 	}
 
-printk("get_pciio_dmamap: Unable to find a free dmamap\n");
 	return(NULL);
 
 }
 
+/*
+ * Free pciio_dmamap_t entry.
+ */
+void
+free_pciio_dmamap(pcibr_dmamap_t dma_map)
+{
+	struct sn1_dma_maps_s *sn1_dma_map;
+
+	sn1_dma_map = (struct sn1_dma_maps_s *) dma_map;
+	sn1_dma_map->dma_addr = 0;
+
+}
+
+/*
+ * sn_dma_sync: This routine flushes all DMA buffers for the device into the II.
+ *	This does not mean that the data is in the "Coherence Domain".  But it 
+ *	is very close.
+ */
+void
+sn_dma_sync( struct pci_dev *hwdev )
+{
+
+	struct sn1_device_sysdata *device_sysdata;
+	volatile unsigned long dummy;
+
+	/*
+	 * It is expected that on IA64 platform, a DMA sync ensures that all 
+	 * the DMA (dma_handle) are complete and coherent.
+	 *	1. Flush Write Buffers from Bridge.
+	 *	2. Flush Xbow Port.
+	 */
+	device_sysdata = (struct sn1_device_sysdata *)hwdev->sysdata;
+	dummy = (volatile unsigned long ) *device_sysdata->dma_buf_sync;
+
+	/*
+	 * For the Xbow Port flush, we maybe denied the request because 
+	 * someone else may be flushing the Port .. try again.
+	 */
+	while((volatile unsigned long ) *device_sysdata->xbow_buf_sync) {
+		udelay(2);
+	}
+}
+
+
 struct sn1_dma_maps_s *
 find_sn1_dma_map(dma_addr_t dma_addr, unsigned char busnum)
 {
@@ -92,13 +119,14 @@
 
 	sn1_dma_map = busnum_to_atedmamaps[busnum];
 
-	for (i=0; i<512; i++, sn1_dma_map++) {
+	for (i=0; i<MAX_ATE_MAPS; i++, sn1_dma_map++) {
 		if (sn1_dma_map->dma_addr == dma_addr) {
 			return( sn1_dma_map );
 		}
 	}
 
 printk("find_pciio_dmamap: Unable find the corresponding dma map\n");
+
 	return(NULL);
 
 }
@@ -139,9 +167,15 @@
 		/*
 		 * This device supports 64bits DMA addresses.
 		 */
+#ifdef CONFIG_IA64_SGI_SN1
 		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
 			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD
 			| PCIIO_DMA_A64 );
+#else /* SN2 */
+		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
+			PCIBR_BARRIER | PCIIO_DMA_CMD | PCIIO_DMA_A64 );
+#endif
+
 		return (ret);
 	}
 
@@ -152,8 +186,14 @@
 	 * First try to get 32 Bit Direct Map Support.
 	 */
 	if (IS_PCI32G(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
 			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
+#else /* SN2 */
+		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
+			PCIBR_BARRIER | PCIIO_DMA_CMD);
+#endif
+
 		if (dma_handle) {
 			return (ret);
 		} else {
@@ -182,7 +222,7 @@
 }
 
 /*
- * On sn1 we use the orig_address entry of the scatterlist to store
+ * On sn1 we use the page entry of the scatterlist to store
  * the physical address corresponding to the given virtual address
  */
 int
@@ -208,18 +248,48 @@
 	device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata;
 	vhdl = device_sysdata->vhdl;
 	for (i = 0; i < nents; i++, sg++) {
-		sg->orig_address = (char *)NULL;
+		/* this catches incorrectly written drivers that
+                   attempt to map scatterlists that they have
+                   previously mapped.  we print a warning and
+                   continue, but the driver should be fixed */
+		switch (((u64)sg->address) >> 60) {
+		case 0xa:
+		case 0xb:
+#ifdef DEBUG
+/* This needs to be cleaned up at some point. */
+			NAG("A PCI driver (for device at%8s) has attempted to "
+			    "map a scatterlist that was previously mapped at "
+			    "%p - this is currently being worked around.\n",
+			    hwdev->slot_name, (void *)sg->address);
+#endif
+			temp_ptr = (u64)sg->address & TO_PHYS_MASK;
+			break;
+		case 0xe: /* a good address, we now map it. */
+			temp_ptr = (paddr_t) __pa(sg->address);
+			break;
+		default:
+			printk(KERN_ERR
+			       "Very bad address (%p) passed to sn1_pci_map_sg\n",
+			       (void *)sg->address);
+			BUG();
+		}
+		sg->page = (char *)NULL;
 		dma_addr = 0;
-		temp_ptr = (paddr_t) __pa(sg->address);
 
 		/*
 		 * Handle the most common case 64Bit cards.
 		 */
 		if (IS_PCIA64(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 				temp_ptr, sg->length,
-				PCIBR_BARRIER | PCIIO_BYTE_STREAM |
-				PCIIO_DMA_CMD | PCIIO_DMA_A64 );
+				PCIIO_BYTE_STREAM | PCIIO_DMA_DATA |
+				PCIIO_DMA_A64 );
+#else
+			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+				temp_ptr, sg->length,
+				PCIIO_DMA_DATA | PCIIO_DMA_A64 );
+#endif
 			sg->address = (char *)dma_addr;
 			continue;
 		}
@@ -228,10 +298,14 @@
 		 * Handle 32Bits and greater cards.
 		 */
 		if (IS_PCI32G(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 				temp_ptr, sg->length,
-				PCIBR_BARRIER | PCIIO_BYTE_STREAM |
-				PCIIO_DMA_CMD);
+				PCIIO_BYTE_STREAM | PCIIO_DMA_DATA);
+#else
+			dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+				temp_ptr, sg->length, PCIIO_DMA_DATA);
+#endif
 			if (dma_addr) {
 				sg->address = (char *)dma_addr;
 				continue;
@@ -244,9 +318,12 @@
 		 * Let's 32Bit Page map the request.
 		 */
 		dma_map = NULL;
+#ifdef CONFIG_IA64_SGI_SN1
 		dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, 
-				PCIBR_BARRIER | PCIIO_BYTE_STREAM |
-				PCIIO_DMA_CMD);
+				PCIIO_BYTE_STREAM | PCIIO_DMA_DATA);
+#else
+		dma_map = pciio_dmamap_alloc(vhdl, NULL, sg->length, PCIIO_DMA_DATA);
+#endif
 		if (!dma_map) {
 			printk("pci_map_sg: Unable to allocate anymore 32Bits Page Map entries.\n");
 			BUG();
@@ -254,7 +331,7 @@
 		dma_addr = (dma_addr_t)pciio_dmamap_addr(dma_map, temp_ptr, sg->length);
 		/* printk("pci_map_sg: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, temp_ptr, dma_addr); */
 		sg->address = (char *)dma_addr;
-		sg->orig_address = (char *)dma_map;
+		sg->page = (char *)dma_map;
 		
 	}
 
@@ -278,20 +355,21 @@
 		BUG();
 
 	for (i = 0; i < nelems; i++, sg++)
-		if (sg->orig_address) {
+		if (sg->page) {
 			/*
-			 * We maintain the DMA Map pointer in sg->orig_address if 
+			 * We maintain the DMA Map pointer in sg->page if 
 			 * it is ever allocated.
 			 */
 			/* phys_to_virt((dma_addr_t)sg->address | ~0x80000000); */
-			/* sg->address = sg->orig_address; */
+			/* sg->address = sg->page; */
 			sg->address = (char *)-1;
-			sn1_dma_map = (struct sn1_dma_maps_s *)sg->orig_address;
+			sn1_dma_map = (struct sn1_dma_maps_s *)sg->page;
 			pciio_dmamap_done((pciio_dmamap_t)sn1_dma_map);
 			pciio_dmamap_free((pciio_dmamap_t)sn1_dma_map);
 			sn1_dma_map->dma_addr = 0;
-			sg->orig_address = 0;
+			sg->page = 0;
 		}
+
 }
 
 /*
@@ -335,10 +413,14 @@
 		/*
 		 * This device supports 64bits DMA addresses.
 		 */
+#ifdef CONFIG_IA64_SGI_SN1
 		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 			temp_ptr, size,
-			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD
-			| PCIIO_DMA_A64 );
+			PCIIO_BYTE_STREAM | PCIIO_DMA_DATA | PCIIO_DMA_A64 );
+#else
+		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+			temp_ptr, size, PCIIO_DMA_DATA | PCIIO_DMA_A64 );
+#endif
 		return (dma_addr);
 	}
 
@@ -349,9 +431,14 @@
 	 * First try to get 32 Bit Direct Map Support.
 	 */
 	if (IS_PCI32G(hwdev)) {
+#ifdef CONFIG_IA64_SGI_SN1
 		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
 			temp_ptr, size,
-			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
+			PCIIO_BYTE_STREAM | PCIIO_DMA_DATA);
+#else
+		dma_addr = (dma_addr_t) pciio_dmatrans_addr(vhdl, NULL,
+			temp_ptr, size, PCIIO_DMA_DATA);
+#endif
 		if (dma_addr) {
 			return (dma_addr);
 		}
@@ -369,15 +456,19 @@
 	 * Let's 32Bit Page map the request.
 	 */
 	dma_map = NULL;
-	dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIBR_BARRIER | 
-			PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
+#ifdef CONFIG_IA64_SGI_SN1
+	dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_BYTE_STREAM | 
+				     PCIIO_DMA_DATA);
+#else
+	dma_map = pciio_dmamap_alloc(vhdl, NULL, size, PCIIO_DMA_DATA);
+#endif
 	if (!dma_map) {
 		printk("pci_map_single: Unable to allocate anymore 32Bits Page Map entries.\n");
 		BUG();
 	}
 
 	dma_addr = (dma_addr_t) pciio_dmamap_addr(dma_map, temp_ptr, size);
-	/* printk("pci_map_single: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map, 
+	/* printk("pci_map_single: dma_map 0x%p Phys Addr 0x%p dma_addr 0x%p\n", dma_map,
 		temp_ptr, dma_addr); */
 	sn1_dma_map = (struct sn1_dma_maps_s *)dma_map;
 	sn1_dma_map->dma_addr = dma_addr;
@@ -414,7 +505,9 @@
 	
         if (direction == PCI_DMA_NONE)
                 BUG();
-        /* Nothing to do */
+
+	sn_dma_sync(hwdev);
+
 }
 
 void
@@ -422,7 +515,9 @@
 {
         if (direction == PCI_DMA_NONE)
                 BUG();
-        /* Nothing to do */
+
+	sn_dma_sync(hwdev);
+
 }
 
 unsigned long
diff -Nru a/arch/ia64/sn/io/pciba.c b/arch/ia64/sn/io/pciba.c
--- a/arch/ia64/sn/io/pciba.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/pciba.c	Fri Mar 15 17:51:01 2002
@@ -1,1716 +1,958 @@
-/* $Id$
+/*
+ * arch/ia64/sn/io/pciba.c
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * IRIX PCIBA-inspired user mode PCI interface
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * requires: devfs
+ *
+ * device nodes show up in /dev/pci/BB/SS.F (where BB is the bus the
+ * device is on, SS is the slot the device is in, and F is the
+ * device's function on a multi-function card).
+ *
+ * when compiled into the kernel, it will only be initialized by the
+ * sgi sn1 specific initialization code.  in this case, device nodes
+ * are under /dev/hw/..../
+ *
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * 03262001 - Initial version by Chad Talbott
  */
 
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/xtalk/xwidget.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/pci/pci_defs.h>
-#include <asm/sn/prio.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/xtalk/xbow.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/eeprom.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/sn_private.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/hubio.h>
-#include <asm/sn/sn1/hubio_next.h>
-#endif
 
-#define copyin(_a, _b, _c)	copy_from_user(_b, _a, _c)
+/* jesse's beefs:
+
+   register_pci_device should be documented
+   
+   grossness with do_swap should be documented
+   
+   big, gross union'ized node_data should be replaced with independent
+   structures
+
+   replace global list of nodes with global lists of resources.  could
+   use object oriented approach of allocating and cleaning up
+   resources.
+   
+*/
+
 
-#ifndef	DEBUG_PCIBA
-#define	DEBUG_PCIBA		0
+#include <linux/config.h>
+#ifndef CONFIG_DEVFS_FS
+#  error PCIBA requires devfs
 #endif
 
-/* v_mapphys does not percolate page offset back. */
-#define	PCIBA_ALIGN_CHECK	1
+#include <linux/module.h>
+#include <linux/devfs_fs_kernel.h>
+#include <linux/pci.h>
+#include <linux/list.h>
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+#include <linux/mman.h>
+#include <linux/init.h>
+#include <linux/raw.h>
+#include <linux/capability.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/pgalloc.h>
+#include <asm/page.h>
 
 #include <asm/sn/pci/pciba.h>
 
-/* grab an unused space code for "User DMA" space */
-#ifndef	PCIBA_SPACE_UDMA
-#define	PCIBA_SPACE_UDMA	(14)
+
+MODULE_DESCRIPTION("User mode PCI interface");
+MODULE_AUTHOR("Chad Talbott");
+
+
+#undef DEBUG_PCIBA
+/* #define DEBUG_PCIBA */
+
+#undef TRACE_PCIBA
+/* #define TRACE_PCIBA */
+
+#if defined(DEBUG_PCIBA)
+#  define DPRINTF(x...) printk(KERN_DEBUG x)
+#else
+#  define DPRINTF(x...)
 #endif
 
-#if DEBUG_REFCT
-extern int		hwgraph_vertex_refct(vertex_hdl_t);
+#if defined(TRACE_PCIBA)
+#  if defined(__GNUC__)
+#    define TRACE()	printk(KERN_DEBUG "%s:%d:%s\n", \
+			       __FILE__, __LINE__, __FUNCTION__)
+#  else
+#    define TRACE()	printk(KERN_DEBUG "%s:%d\n", __LINE__, __FILE__)
+#  endif
+#else
+#  define TRACE()
 #endif
-extern int		pci_user_dma_max_pages;
 
-#define NEW(ptr)	(ptr = kmem_zalloc(sizeof (*(ptr)), KM_SLEEP))
-#define DEL(ptr)	(kfree(ptr))
 
-/* Oops -- no standard "pci address" type! */
-typedef uint64_t        pciaddr_t;
+typedef enum { failure, success } status;
+typedef enum { false, true } boolean;
 
-/* ================================================================
- *            driver types
- */
-typedef struct pciba_slot_s *pciba_slot_t;
-typedef struct pciba_comm_s *pciba_comm_t;
-typedef struct pciba_soft_s *pciba_soft_t;
-typedef struct pciba_map_s *pciba_map_t, **pciba_map_h;
-typedef struct pciba_dma_s *pciba_dma_t, **pciba_dma_h;
-typedef struct pciba_bus_s *pciba_bus_t;
-
-#define	TRACKED_SPACES	16
-struct pciba_comm_s {
-    devfs_handle_t	    conn;
-    pciba_bus_t             bus;
-    int			    refct;
-    pciba_soft_t	    soft[TRACKED_SPACES][2];
-    struct semaphore        lock;
-    pciba_dma_t             dmap;
+
+/* major data structures:
+
+   struct node_data -
+   
+   	one for each file registered with devfs.  contains everything
+   	that any file's fops would need to know about.
+
+   struct dma_allocation -
+
+   	a single DMA allocation.  only the 'dma' nodes care about
+   	these.  they are there primarily to allow the driver to look
+   	up the kernel virtual address of dma buffers allocated by
+   	pci_alloc_consistent, as the application is only given the
+   	physical address (to program the device's dma, presumably) and
+   	cannot supply the kernel virtual address when freeing the
+   	buffer.
+
+	it's also useful to maintain a list of buffers allocated
+	through a specific node to allow some sanity checking by this
+	driver.  this prevents (for example) a broken application from
+	freeing buffers that it didn't allocate, or buffers allocated
+	on another node.
+   
+   global_node_list -
+
+   	a list of all nodes allocated.  this allows the driver to free
+   	all the memory it has 'kmalloc'd in case of an error, or on
+   	module removal.
+
+   global_dma_list -
+
+        a list of all dma buffers allocated by this driver.  this
+	allows the driver to 'pci_free_consistent' all buffers on
+	module removal or error.
+
+*/
+
+
+struct node_data {
+	/* flat list of all the device nodes.  makes it easy to free
+	   them all when we're unregistered */
+	struct list_head global_node_list;
+	devfs_handle_t devfs_handle;
+
+	void (* cleanup)(struct node_data *);
+
+	union {
+		struct {
+			struct pci_dev * dev;
+			struct list_head dma_allocs;
+			boolean mmapped;
+		} dma;
+		struct {
+			struct pci_dev * dev;
+			u32 saved_rom_base_reg;
+			boolean mmapped;
+		} rom;
+		struct {
+			struct resource * res;
+		} base;
+		struct {
+			struct pci_dev * dev;
+		} config;
+	} u;
 };
 
-/* pciba_soft: device_info() for all openables */
-struct pciba_soft_s {
-    pciba_comm_t	    comm;
-    devfs_handle_t          vhdl;
-    int			    refct;
-    pciio_space_t           space;
-    size_t                  size;
-    pciio_space_t           iomem;
-    pciaddr_t               base;
-    unsigned		    flags;
+struct dma_allocation {
+	struct list_head list;
+
+	dma_addr_t handle;
+	void * va;
+	size_t size;
 };
 
-#define	pciba_soft_get(v)	(pciba_soft_t)hwgraph_fastinfo_get(v)
-#define	pciba_soft_set(v,i)	hwgraph_fastinfo_set(v,(arbitrary_info_t)(i))
 
-#define	pciba_soft_lock(soft)	down(&soft->comm->lock)
-#define	pciba_soft_unlock(soft)	up(&soft->comm->lock)
+static LIST_HEAD(global_node_list);
+static LIST_HEAD(global_dma_list);
 
-/* pciba_map: data describing a mapping.
- * (ie. a user mmap request)
- */
-struct pciba_map_s {
-    pciba_map_t             next;
-#ifdef LATER
-    uthread_t              *uthread;
-#endif
-    __psunsigned_t          handle;
-    uvaddr_t                uvaddr;
-    size_t                  size;
-    pciio_piomap_t          map;
-    pciio_space_t           space;
-    pciaddr_t               base;
-    unsigned		    flags;
-};
 
-/* pciba_dma: data describing a DMA mapping.
- */
-struct pciba_dma_s {
-    pciba_dma_t             next;
-    iopaddr_t               paddr;	/* starting phys addr */
-    caddr_t                 kaddr;	/* starting kern addr */
-    pciio_dmamap_t          map;	/* mapping resources (ugh!) */
-    pciaddr_t               daddr;	/* starting pci addr */
-    size_t                  pages;	/* size of block in pages */
-    size_t                  bytes;	/* size of block in bytes */
-    __psunsigned_t          handle;	/* mapping handle */
+/* module entry points */
+int __init pciba_init(void);
+void __exit pciba_exit(void);
+
+static status __init register_with_devfs(void);
+static void __exit unregister_with_devfs(void);
+
+static status __init register_pci_device(devfs_handle_t device_dir_handle,
+					 struct pci_dev * dev);
+
+/* file operations */
+static int generic_open(struct inode * inode, struct file * file);
+static int rom_mmap(struct file * file, struct vm_area_struct * vma);
+static int rom_release(struct inode * inode, struct file * file);
+static int base_mmap(struct file * file, struct vm_area_struct * vma);
+static int config_ioctl(struct inode * inode, struct file * file, 
+			unsigned int cmd, 
+			unsigned long arg);
+static int dma_ioctl(struct inode * inode, struct file * file, 
+		     unsigned int cmd, 
+		     unsigned long arg);
+static int dma_mmap(struct file * file, struct vm_area_struct * vma);
+
+/* support routines */
+static int mmap_pci_address(struct vm_area_struct * vma, unsigned long pci_va);
+static int mmap_kernel_address(struct vm_area_struct * vma, void * kernel_va);
+
+#ifdef DEBUG_PCIBA
+static void dump_nodes(struct list_head * nodes);
+static void dump_allocations(struct list_head * dalp);
+#endif
+
+/* file operations for each type of node */
+static struct file_operations rom_fops = {
+	owner:		THIS_MODULE,
+	mmap:		rom_mmap,
+	open:		generic_open,
+	release:	rom_release
 };
+ 
 
-/* pciba_bus: common bus info for all openables
- * descended from the same master vertex.
- */
-struct pciba_bus_s {
-    struct semaphore        lock;
-    pciba_map_t             maps;	/* stack of mappings */
-    int			    refct;
+static struct file_operations base_fops = {
+	owner:		THIS_MODULE,
+	mmap:		base_mmap,
+	open:		generic_open
 };
 
-#define	pciba_bus_lock(bus)	down(&bus->lock)
-#define	pciba_bus_unlock(bus)	up(&bus->lock)
 
-typedef union ioctl_arg_buffer_u {
-    char                    data[IOCPARM_MASK + 1];
-    uint8_t                 uc;
-    uint16_t                us;
-    uint32_t                ui;
-    uint64_t                ud;
-    caddr_t                 ca;
-#if ULI
-    struct uliargs          uli;
-    struct uliargs32	    uli32;
-#endif
-} ioctl_arg_buffer_t;
+static struct file_operations config_fops = {
+	owner:		THIS_MODULE,
+	ioctl:		config_ioctl,
+	open:		generic_open
+};	
 
-/* ================================================================
- *            driver variables
- */
-char                   *pciba_mversion = "mload version 7.0";
-int                     pciba_devflag = 0x1 |
-                                        0x200 |
-                                        0x400;
+static struct file_operations dma_fops = {
+	owner:		THIS_MODULE,
+	ioctl:		dma_ioctl,
+	mmap:		dma_mmap,
+	open:		generic_open
+};	
 
-/* this counts the reasons why we can not
- * currently unload this driver.
- */
-atomic_t                pciba_prevent_unload = ATOMIC_INIT(0);
 
-#if DEBUG_PCIBA
-static struct reg_values space_v[] =
-{
-    {PCIIO_SPACE_NONE, "none"},
-    {PCIIO_SPACE_ROM, "ROM"},
-    {PCIIO_SPACE_IO, "I/O"},
-    {PCIIO_SPACE_MEM, "MEM"},
-    {PCIIO_SPACE_MEM32, "MEM(32)"},
-    {PCIIO_SPACE_MEM64, "MEM(64)"},
-    {PCIIO_SPACE_CFG, "CFG"},
-    {PCIIO_SPACE_WIN(0), "WIN(0)"},
-    {PCIIO_SPACE_WIN(1), "WIN(1)"},
-    {PCIIO_SPACE_WIN(2), "WIN(2)"},
-    {PCIIO_SPACE_WIN(3), "WIN(3)"},
-    {PCIIO_SPACE_WIN(4), "WIN(4)"},
-    {PCIIO_SPACE_WIN(5), "WIN(5)"},
-    {PCIBA_SPACE_UDMA, "UDMA"},
-    {PCIIO_SPACE_BAD, "BAD"},
-    {0}
-};
+module_init(pciba_init);
+module_exit(pciba_exit);
+
 
-static struct reg_desc  space_desc[] =
+int __init
+pciba_init(void)
 {
-    {0xFF, 0, "space", 0, space_v},
-    {0}
-};
-#endif
+	TRACE();
 
-char                    pciba_edge_lbl_base[] = "base";
-char                    pciba_edge_lbl_cfg[] = "config";
-char                    pciba_edge_lbl_dma[] = "dma";
-char                    pciba_edge_lbl_intr[] = "intr";
-char                    pciba_edge_lbl_io[] = "io";
-char                    pciba_edge_lbl_mem[] = "mem";
-char                    pciba_edge_lbl_rom[] = "rom";
-char                   *pciba_edge_lbl_win[6] =
-{"0", "1", "2", "3", "4", "5"};
-
-#define	PCIBA_EDGE_LBL_BASE	pciba_edge_lbl_base
-#define	PCIBA_EDGE_LBL_CFG	pciba_edge_lbl_cfg
-#define	PCIBA_EDGE_LBL_DMA	pciba_edge_lbl_dma
-#define	PCIBA_EDGE_LBL_INTR	pciba_edge_lbl_intr
-#define	PCIBA_EDGE_LBL_IO	pciba_edge_lbl_io
-#define	PCIBA_EDGE_LBL_MEM	pciba_edge_lbl_mem
-#define	PCIBA_EDGE_LBL_ROM	pciba_edge_lbl_rom
-#define	PCIBA_EDGE_LBL_WIN(n)	pciba_edge_lbl_win[n]
-
-#define	PCIBA_EDGE_LBL_FLIP	pciba_edge_lbl_flip
-
-static char             pciba_info_lbl_bus[] = "pciba_bus";
-
-#define	PCIBA_INFO_LBL_BUS	pciba_info_lbl_bus
-
-struct file_operations pciba_fops = {
-	owner:	THIS_MODULE,
-	llseek: NULL,
-	read: NULL,
-	write: NULL,
-	readdir: NULL,
-	poll: NULL,
-	ioctl: NULL,
-	mmap: NULL,
-	open: NULL,
-	flush: NULL,
-	release: NULL,
-	fsync: NULL,
-	fasync: NULL,
-	lock: NULL,
-	readv: NULL,
-	writev: NULL
-};
-	
-/* ================================================================
- *            function table of contents
- */
+	if (register_with_devfs() == failure)
+		return 1; /* failure */
 
-void                    pciba_init(void);
-int                     pciba_attach(devfs_handle_t);
+	printk("PCIBA (a user mode PCI interface) initialized.\n");
 
-static void		pciba_sub_attach(pciba_comm_t,
-					 pciio_space_t, pciio_space_t, pciaddr_t,
-					 devfs_handle_t, devfs_handle_t, char *);
-
-static pciba_bus_t      pciba_find_bus(devfs_handle_t, int);
-#ifdef LATER
-static void             pciba_map_push(pciba_bus_t, pciba_map_t);
-static pciba_map_t      pciba_map_pop_hdl(pciba_bus_t, __psunsigned_t);
-static void             pciba_sub_detach(devfs_handle_t, char *);
-static pciio_iter_f     pciba_unload_me;
-#endif
+	return 0; /* success */
+}
 
-int                     pciba_unload(void);
-int                     pciba_unreg(void);
-int                     pciba_detach(devfs_handle_t);
-
-int                     pciba_open(dev_t *, int, int, struct cred *);
-int                     pciba_close(dev_t);
-int                     pciba_read(dev_t, cred_t *);
-int                     pciba_write(dev_t, cred_t *);
-int                     pciba_ioctl(dev_t, int, void *, int, cred_t *, int *);
-
-int                     pciba_map(dev_t, vhandl_t *, off_t, size_t, uint32_t);
-int                     pciba_unmap(dev_t, vhandl_t *);
-
-#if ULI
-void                    pciba_clearuli(struct uli *);
-static intr_func_f      pciba_intr;
-#endif /* Undef as it gets implemented */
 
-/* ================================================================
- *            driver load, register, and setup
- */
-void
-pciba_init(void)
+void __exit
+pciba_exit(void)
 {
+	TRACE();
 
-	/*
-	 * What do we need to do here?
-	 */
-#if DEBUG_PCIBA
-    printk("pciba_init()\n");
-#endif
+	/* FIXME: should also free all that memory that we allocated
+           ;) */
+	unregister_with_devfs();
 }
 
-#ifdef LATER
-#if HWG_PERF_CHECK && IP30 && !DEBUG
-void
-pciba_timeout(void *arg1, void *arg2)
-{
-    struct semaphore       *semap = (sema_t *) arg1;
-    unsigned long          *cvalp = (unsigned long *) arg2;
-
-    if (cvalp)
-	cvalp[0] = RAW_COUNT();
-    if (semap)
-	up(semap);
-}
-
-volatile unsigned long  cNval[1];
-struct semaphore        tsema;
-
-void
-pciba_timeout_test(void)
-{
-    unsigned long           c0val, cval;
-    toid_t                  tid;
-
-    extern void             hwg_hprint(unsigned long, char *);
-
-    sema_init(&tsema, 0);
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) 0, 1, (void *) cNval);
-    DELAY(1000000);
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_ALERT("pciba: one-tick timeout did not happen in a second\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(1)");
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) &tsema, 2, (void *) cNval);
-
-    /* FIXME : this probably needs to be down_interruptible() */
-
-    if (down(&tsema) < 0) {	/* wait for the pciba_timeout */
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(2) time check aborted\n");
-	return;
-    }
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(2) time not logged\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(2)");
-
-    cNval[0] = 0;
-    c0val = RAW_COUNT();
-    tid = timeout((void (*)()) pciba_timeout, (void *) &tsema, HZ, (void *) cNval);
-
-    /* FIXME : this probably needs to be down_interruptible() */
-
-    if (down(&tsema) < 0) {	/* wait for the pciba_timeout */
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(HZ) time check aborted\n");
-	return;
-    }
-    cval = cNval[0];
-    if (cval == 0) {
-	untimeout(tid);
-	PRINT_WARNING("pciba: timeout(HZ) time not logged\n");
-	return;
-    }
-    cval = cval - c0val;
-    hwg_hprint(cval, "timeout(HZ)");
-
-    printk("verifying untimeout() cancells ...\n");
-    cNval[0] = 0;
-    tid = timeout((void (*)()) pciba_timeout, (void *) 0, 2, (void *) cNval);
-    untimeout(tid);
-    DELAY(1000000);
-    cval = cNval[0];
-    if (cval != 0) {
-	PRINT_ALERT("pciba: unable to cancel two-tick timeout\n");
-	cval -= c0val;
-	hwg_hprint(cval, "CANCELLED timeout(2)");
-    }
-}
-#endif
 
-int
-pciba_reg(void)
+# if 0
+static void __exit
+free_nodes(void)
 {
-#if DEBUG_PCIBA
-    printk("pciba_reg()\n");
-#endif
-    pciio_driver_register(-1, -1, "pciba_", 0);
-
-#if HWG_PERF_CHECK && IP30 && !DEBUG
-    printk("%s %d\n", __FUNCTION__, __LINE__);
-pciba_timeout_test();
-#endif
+	struct node_data * nd;
+	
+	TRACE();
 
-#if DEBUG_REFCT
-    {
-	char	       *cname = "pciba";
-	char	       *dname = "ptv";
-	char           *cpath0 = "node/xtalk/15";
-	char           *uname0 = "0";
-	char           *cpath1 = "node/xtalk/13";
-	char           *uname1 = "1";
-	devfs_handle_t conn;
-	devfs_handle_t conv;
-	devfs_handle_t vhdl;
-	int		ret;
-
-	printk("pciba refct tests:\n");
-
-#define	SHOWREF(vhdl,func)	printk("ref=%d\t%s\t(%d) %v\n", hwgraph_vertex_refct(vhdl), #func, vhdl, vhdl);
-
-	if (GRAPH_SUCCESS != (ret = hwgraph_path_add(hwgraph_root, cname, &conv)))
-	    printk("\tunable to create conv (ret=%d)\n", ret);
-	else {						SHOWREF(conv, hwgraph_path_add);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath0, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath0, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_char_device_add(conn, dname, "pciba_", &vhdl)))
-		    printk("unable to create %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_char_device_add);
-		    hwgraph_chmod(vhdl, 0666);		SHOWREF(vhdl, hwgraph_chmod);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_add(conv, vhdl, uname0)))
-			printk("unable to create %v/%s (ret=%d)\n", conn, uname0, vhdl, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_add);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
- 
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath1, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath1, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_char_device_add(conn, dname, "pciba_", &vhdl)))
-		    printk("unable to create %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_char_device_add);
-		    hwgraph_chmod(vhdl, 0666);		SHOWREF(vhdl, hwgraph_chmod);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_add(conv, vhdl, uname1)))
-			printk("unable to create %v/%s (ret=%d)\n", conn, uname1, vhdl, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_add);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
- 
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath0, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath0, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_traverse(conn, dname, &vhdl)))
-		    printk("\tunable to find %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_traverse);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conv, uname0, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conv, uname0, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conn, dname, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conn, dname, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(vhdl)))
-			printk("\tvertex %d destroyed OK\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_destroy);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
-
-	    if (GRAPH_SUCCESS != (ret = hwgraph_traverse(hwgraph_root, cpath1, &conn)))
-		printk("\tunable to find %s (ret=%d)\n", cpath1, ret);
-	    else {					SHOWREF(conn, hwgraph_traverse);
-		if (GRAPH_SUCCESS != (ret = hwgraph_traverse(conn, dname, &vhdl)))
-		    printk("\tunable to find %v/%s (ret=%d)\n", conn, dname, ret);
-		else {					SHOWREF(vhdl, hwgraph_traverse);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conv, uname1, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conv, uname1, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(conn, dname, NULL)))
-			printk("\tunable to remove edge %v/%s (ret=%d)\n", conn, dname, ret);
-		    else				SHOWREF(vhdl, hwgraph_edge_remove);
-		    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(vhdl)))
-			printk("unable to unref %v\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_unref);
-		    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(vhdl)))
-			printk("\tvertex %d destroyed OK\n", vhdl);
-		    else				SHOWREF(vhdl, hwgraph_vertex_destroy);
-		}
-		if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conn)))
-		    printk("unable to unref %v\n", conn);
-		else					SHOWREF(conn, hwgraph_vertex_unref);
-	    }
-
-	    if (GRAPH_SUCCESS != (ret = hwgraph_edge_remove(hwgraph_root, cname, NULL)))
-		printk("\tunable to remove edge %v/%s (ret=%d)\n", hwgraph_root, cname, ret);
-	    else				SHOWREF(conv, hwgraph_edge_remove);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_unref(conv)))
-		printk("unable to unref %v\n", conv);
-	    else					SHOWREF(conv, hwgraph_vertex_unref);
-	    if (GRAPH_SUCCESS == (ret = hwgraph_vertex_destroy(conv)))
-		printk("\tvertex %d destroyed OK\n", conv);
-	    else					SHOWREF(conv, hwgraph_vertex_destroy);
+	list_for_each(nd, &node_list) {
+		kfree(list_entry(nd, struct nd, node_list));
 	}
-    }
-#endif
-
-    return 0;
 }
-
-#endif
-int
-pciba_attach(devfs_handle_t hconn)
-{
-#if defined(PCIIO_SLOT_NONE)
-    pciio_info_t            info = pciio_info_get(hconn);
-    pciio_slot_t            slot = pciio_info_slot_get(info);
 #endif
-    pciba_comm_t	    comm;
-    pciba_bus_t             bus;
-    int                     ht;
-    devfs_handle_t	    hbase;
-    devfs_handle_t          gconn;
-    devfs_handle_t          gbase;
-    int                     win;
-    int                     wins;
-    pciio_space_t           space;
-    pciaddr_t               base;
 
-    int                     iwins;
-    int                     mwins;
 
-#if DEBUG_PCIBA
-    printk("pciba_attach(%p)\n", hconn);
-#endif
+static devfs_handle_t pciba_devfs_handle;
 
-    /* Pick up "dualslot guest" vertex,
-     * which gets all functionality except
-     * config space access.
-     */
-    if ((GRAPH_SUCCESS !=
-	 hwgraph_traverse(hconn, ".guest", &gconn)) ||
-	(hconn == gconn))
-	gconn = GRAPH_VERTEX_NONE;
-
-    bus = pciba_find_bus(hconn, 1);
-    bus->refct ++;
-
-    /* set up data common to all pciba openables
-     * on this connection point.
-     */
-    NEW(comm);
-    comm->conn = hconn;
-    comm->bus = bus;
-    comm->refct = 0;
-    sema_init(&comm->lock, 1);
 
-#if !defined(PCIIO_SLOT_NONE)
-    if (bus->refct == 1)
-#else
-    if (slot == PCIIO_SLOT_NONE)
-#endif
-    {
-	pciio_info_t            pciio_info;
-	devfs_handle_t          master;
-
-	pciio_info = pciio_info_get(hconn);
-	master = pciio_info_master_get(pciio_info);
-
-	pciba_sub_attach(comm, PCIIO_SPACE_IO, PCIIO_SPACE_IO, 0, master, master, PCIBA_EDGE_LBL_IO);
-	pciba_sub_attach(comm, PCIIO_SPACE_MEM, PCIIO_SPACE_MEM, 0, master, master, PCIBA_EDGE_LBL_MEM);
-#if defined(PCIIO_SLOT_NONE)
-	return 0;
-#endif
-    }
+#if !defined(CONFIG_IA64_SGI_SN1)
 
-    ht = 0x7F & pciio_config_get(hconn, PCI_CFG_HEADER_TYPE, 1);
+static status __init
+register_with_devfs(void)
+{
+	struct pci_dev * dev;
+	devfs_handle_t device_dir_handle;
+	char devfs_path[40];
 
-    wins = ((ht == 0x00) ? 6 :
-	    (ht == 0x01) ? 2 :
-	    0);
-
-    mwins = iwins = 0;
-
-    hbase = GRAPH_VERTEX_NONE;
-    gbase = GRAPH_VERTEX_NONE;
-
-    for (win = 0; win < wins; win++) {
-
-	base = pciio_config_get(hconn, PCI_CFG_BASE_ADDR(win), 4);
-	if (base & 1) {
-	    space = PCIIO_SPACE_IO;
-	    base &= 0xFFFFFFFC;
-	} else if ((base & 7) == 4) {
-	    space = PCIIO_SPACE_MEM;
-	    base &= 0xFFFFFFF0;
-	    base |= ((pciaddr_t) pciio_config_get(hconn, PCI_CFG_BASE_ADDR(win + 1), 4)) << 32;
-	} else {
-	    space = PCIIO_SPACE_MEM;
-	    base &= 0xFFFFFFF0;
-	}
+	TRACE();
 
-	if (!base)
-	    break;
+	pciba_devfs_handle = devfs_mk_dir(NULL, "pci", NULL);
+	if (pciba_devfs_handle == NULL)
+		return failure;
 
-#if PCIBA_ALIGN_CHECK
-	if (base & (_PAGESZ - 1)) {
-#if DEBUG_PCIBA
-	    PRINT_WARNING("%p pciba: BASE%d not page aligned!\n"
-		    "\tmmap this window at offset 0x%x via \".../pci/%s\"\n",
-		    hconn, win, base,
-		    (space == PCIIO_SPACE_IO) ? "io" : "mem");
-#endif
-	    continue;			/* next window */
-	}
-#endif
+	/* FIXME: don't forget /dev/pci/mem & /dev/pci/io */
+
+	pci_for_each_dev(dev) {
+		sprintf(devfs_path, "%02x/%02x.%x",
+			dev->bus->number,
+			PCI_SLOT(dev->devfn),
+			PCI_FUNC(dev->devfn));
+    
+		device_dir_handle =
+			devfs_mk_dir(pciba_devfs_handle, devfs_path, NULL);
+		if (device_dir_handle == NULL)
+			return failure;
 
-	if ((hbase == GRAPH_VERTEX_NONE) &&
-	    ((GRAPH_SUCCESS !=
-	      hwgraph_path_add(hconn, PCIBA_EDGE_LBL_BASE, &hbase)) ||
-	     (hbase == GRAPH_VERTEX_NONE)))
-	    break;			/* no base vertex, no more windows. */
-
-	if ((gconn != GRAPH_VERTEX_NONE) &&
-	    (gbase == GRAPH_VERTEX_NONE) &&
-	    ((GRAPH_SUCCESS !=
-	      hwgraph_path_add(gconn, PCIBA_EDGE_LBL_BASE, &gbase)) ||
-	     (gbase == GRAPH_VERTEX_NONE)))
-	    break;			/* no base vertex, no more windows. */
-
-	pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hbase, gbase, PCIBA_EDGE_LBL_WIN(win));
-
-	if (space == PCIIO_SPACE_IO) {
-	    if (!iwins++) {
-		pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hconn, gconn, PCIBA_EDGE_LBL_IO);
-	    }
-	} else {
-	    if (!mwins++) {
-		pciba_sub_attach(comm, PCIIO_SPACE_WIN(win), space, base, hconn, gconn, PCIBA_EDGE_LBL_MEM);
-	    }
+		if (register_pci_device(device_dir_handle, dev) == failure) {
+			devfs_unregister(pciba_devfs_handle);
+			return failure;
+		}
 	}
 
-	if ((base & 7) == 4)
-	    win++;
-    }
-
-    pciba_sub_attach(comm, PCIIO_SPACE_CFG, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_CFG);
-    pciba_sub_attach(comm, PCIBA_SPACE_UDMA, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_DMA);
-#if ULI
-    pciba_sub_attach(comm, PCIIO_SPACE_NONE, PCIIO_SPACE_NONE, 0, hconn, gconn, PCIBA_EDGE_LBL_INTR);
-#endif
+	return success;
+}
 
-    /* XXX should ignore if device is an IOC3 */
-    if (ht == 0x01)
-	base = pciio_config_get(hconn, PCI_EXPANSION_ROM+8, 4);
-    else
-	base = pciio_config_get(hconn, PCI_EXPANSION_ROM, 4);
-
-    base &= 0xFFFFF000;
-
-    if (base) {
-	if (base & (_PAGESZ - 1))
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    PRINT_WARNING("%v pciba: ROM is 0x%x\n"
-		    "\tnot page aligned, mmap will be difficult\n",
-		    hconn, base);
 #else
-	    PRINT_WARNING("0x%x pciba: ROM is 0x%x\n"
-		    "\tnot page aligned, mmap will be difficult\n",
-		    hconn, base);
-#endif
-	pciba_sub_attach(comm, PCIIO_SPACE_ROM, PCIIO_SPACE_MEM, base, hconn, gconn, PCIBA_EDGE_LBL_ROM);
-    }
 
-#if !FICUS	/* FICUS shorts the refct by one on path_add */
-    if (hbase != GRAPH_VERTEX_NONE)
-	hwgraph_vertex_unref(hbase);
+extern devfs_handle_t
+devfn_to_vertex(unsigned char busnum, unsigned int devfn);
 
-    if (gbase != GRAPH_VERTEX_NONE)
-	hwgraph_vertex_unref(gbase);
-#endif
+static status __init
+register_with_devfs(void)
+{
+	struct pci_dev * dev;
+	devfs_handle_t device_dir_handle;
 
-    return 0;
-}
+	TRACE();
 
-static void
-pciba_sub_attach2(pciba_comm_t comm,
-		  pciio_space_t space,
-		  pciio_space_t iomem,
-		  pciaddr_t base,
-		  devfs_handle_t from,
-		  char *name,
-		  char *suf,
-		  unsigned bigend)
-{
-    char		nbuf[128];
-    pciba_soft_t            soft;
-    devfs_handle_t	handle = NULL;
-
-    if (suf && *suf) {
-	strcpy(nbuf, name);
-	name = nbuf;
-	strcat(name, suf);
-    }
-
-#if DEBUG_PCIBA
-    printk("pciba_sub_attach2 %p/%s %p at %p[%x]\n",
-	   from, name, space, space_desc, iomem, space_desc, base, from, name);
-#endif
+	/* FIXME: don't forget /dev/.../pci/mem & /dev/.../pci/io */
 
-    if (space < TRACKED_SPACES)
-	if ((soft = comm->soft[space][bigend]) != NULL) {
-	    soft->refct ++;
-	    hwgraph_edge_add(from, soft->vhdl, name);
-	    return;
+	pci_for_each_dev(dev) {
+		device_dir_handle = devfn_to_vertex(dev->bus->number,
+						    dev->devfn);
+		if (device_dir_handle == NULL)
+			return failure;
+	
+		if (register_pci_device(device_dir_handle, dev) == failure) {
+			devfs_unregister(pciba_devfs_handle);
+			return failure;
+		}
 	}
 
-    NEW(soft);
-    if (!soft)
-	return;
-
-    soft->comm = comm;
-    soft->space = space;
-    soft->size = 0;
-    soft->iomem = iomem;
-    soft->base = base;
-    soft->refct = 1;
-
-    if (space == PCIIO_SPACE_NONE)
-	soft->flags = 0;
-    else if (bigend)
-	soft->flags = PCIIO_BYTE_STREAM;
-    else
-	soft->flags = PCIIO_WORD_VALUES;
-
-    handle = hwgraph_register(from, name,
-		0, DEVFS_FL_AUTO_DEVNUM,
-		0, 0,
-		S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-		&pciba_fops, NULL);
-    soft->vhdl = handle;
-    pciba_soft_set(soft->vhdl, soft);
-    if (space < TRACKED_SPACES)
-	comm->soft[space][bigend] = soft;
-    comm->refct ++;
+	return success;
 }
 
-static void
-pciba_sub_attach1(pciba_comm_t comm,
-		  pciio_space_t space,
-		  pciio_space_t iomem,
-		  pciaddr_t base,
-		  devfs_handle_t hfrom,
-		  devfs_handle_t gfrom,
-		  char *name,
-		  char *suf,
-		  unsigned bigend)
-{
-    pciba_sub_attach2(comm, space, iomem, base, hfrom, name, suf, bigend);
-    if ((gfrom != GRAPH_VERTEX_NONE) && (gfrom != hfrom))
-	pciba_sub_attach2(comm, space, iomem, base, gfrom, name, suf, bigend);
-}
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
+static void __exit
+unregister_with_devfs(void)
+{
+	struct list_head * lhp;
+	struct node_data * nd;
+	
+	TRACE();
+
+	list_for_each(lhp, &global_node_list) {
+		nd = list_entry(lhp, struct node_data, global_node_list);
+		devfs_unregister(nd->devfs_handle);
+	}
 
-static void
-pciba_sub_attach(pciba_comm_t comm,
-		 pciio_space_t space,
-		 pciio_space_t iomem,
-		 pciaddr_t base,
-		 devfs_handle_t hfrom,
-		 devfs_handle_t gfrom,
-		 char *name)
-{
-    pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, NULL, 0);
-    if (iomem != PCIIO_SPACE_NONE) {
-	pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, "_le", 0);
-	pciba_sub_attach1(comm, space, iomem, base, hfrom, gfrom, name, "_be", 1);
-    }
 }
 
-#ifdef LATER
-static void
-pciba_reload_me(devfs_handle_t pconn_vhdl)
+
+struct node_data * new_node(void)
 {
-    devfs_handle_t            vhdl;
+	struct node_data * node;
+	
+	TRACE();
+	
+	node = kmalloc(sizeof(struct node_data), GFP_KERNEL);
+	if (node == NULL)
+		return NULL;
+	list_add(&node->global_node_list, &global_node_list);
+	return node;
+}
 
-#if DEBUG_PCIBA
-    printf("pciba_reload_me(%v)\n", pconn_vhdl);
-#endif
 
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, PCIBA_EDGE_LBL_CFG, &vhdl))
-	return;
+void dma_cleanup(struct node_data * dma_node)
+{
+	TRACE();
 
-    hwgraph_vertex_unref(vhdl);
+	/* FIXME: should free these allocations */
+#ifdef DEBUG_PCIBA
+	dump_allocations(&dma_node->u.dma.dma_allocs);
+#endif
+	devfs_unregister(dma_node->devfs_handle);
 }
-#endif	/* LATER */
 
-static                  pciba_bus_t
-pciba_find_bus(devfs_handle_t pconn, int cflag)
+
+void init_dma_node(struct node_data * node,
+		   struct pci_dev * dev, devfs_handle_t dh)
 {
-    pciio_info_t            pciio_info;
-    devfs_handle_t          master;
-    arbitrary_info_t        ainfo;
-    pciba_bus_t             bus;
+	TRACE();
 
-    pciio_info = pciio_info_get(pconn);
-    master = pciio_info_master_get(pciio_info);
+	node->devfs_handle = dh;
+	node->u.dma.dev = dev;
+	node->cleanup = dma_cleanup;
+	INIT_LIST_HEAD(&node->u.dma.dma_allocs);
+}
 
-    if (GRAPH_SUCCESS ==
-	hwgraph_info_get_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo))
-	return (pciba_bus_t) ainfo;
 
-    if (!cflag)
-	return 0;
+void rom_cleanup(struct node_data * rom_node)
+{
+	TRACE();
 
-    NEW(bus);
-    if (!bus)
-	return 0;
+	if (rom_node->u.rom.mmapped)
+		pci_write_config_dword(rom_node->u.rom.dev,
+				       PCI_ROM_ADDRESS,
+				       rom_node->u.rom.saved_rom_base_reg);
+	devfs_unregister(rom_node->devfs_handle);
+}
 
-    sema_init(&bus->lock, 1);
 
-    ainfo = (arbitrary_info_t) bus;
-    hwgraph_info_add_LBL(master, PCIBA_INFO_LBL_BUS, ainfo);
-    hwgraph_info_get_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo);
-    if ((pciba_bus_t) ainfo != bus)
-	DEL(bus);
-#if DEBUG_PCIBA
-    else
-	printk("pcbia_find_bus: new bus at %p\n", master);
-#endif
+void init_rom_node(struct node_data * node,
+		   struct pci_dev * dev, devfs_handle_t dh)
+{
+	TRACE();
 
-    return (pciba_bus_t) ainfo;
+	node->devfs_handle = dh;
+	node->u.rom.dev = dev;
+	node->cleanup = rom_cleanup;
+	node->u.rom.mmapped = false;
 }
 
-#ifdef LATER
-static void
-pciba_map_push(pciba_bus_t bus, pciba_map_t map)
+
+static status __init
+register_pci_device(devfs_handle_t device_dir_handle, struct pci_dev * dev)
 {
-#if DEBUG_PCIBA
-    printk("pciba_map_push(bus=0x%x, map=0x%x, hdl=0x%x\n",
-	   bus, map, map->handle);
-#endif
-    pciba_bus_lock(bus);
-    map->next = bus->maps;
-    bus->maps = map;
-    pciba_bus_unlock(bus);
-}
-
-static                  pciba_map_t
-pciba_map_pop_hdl(pciba_bus_t bus, __psunsigned_t handle)
-{
-    pciba_map_h             hdl;
-    pciba_map_t             map;
-
-    pciba_bus_lock(bus);
-    for (hdl = &bus->maps; map = *hdl; hdl = &map->next)
-	if (map->handle == handle) {
-	    *hdl = map->next;
-	    break;
+	struct node_data * nd;
+	char devfs_path[20];
+	devfs_handle_t node_devfs_handle;
+	int ri;
+
+	TRACE();
+
+
+	/* register nodes for all the device's base address registers */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (pci_resource_len(dev, ri) != 0) {
+			sprintf(devfs_path, "base/%d", ri);
+			if (devfs_register(device_dir_handle, devfs_path,
+					   DEVFS_FL_NONE,
+					   0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+		}
 	}
-    pciba_bus_unlock(bus);
-#if DEBUG_PCIBA
-    printk("pciba_map_pop_va(bus=0x%x, handle=0x%x) returns map=0x%x\n",
-	   bus, handle, map);
+	
+	/* register a node corresponding to the first MEM resource on
+           the device */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (dev->resource[ri].flags & IORESOURCE_MEM &&
+		    pci_resource_len(dev, ri) != 0) {
+			if (devfs_register(device_dir_handle, "mem",
+					   DEVFS_FL_NONE, 0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+			break;
+		}
+	}
+
+	/* also register a node corresponding to the first IO resource
+           on the device */
+	for (ri = 0; ri < PCI_ROM_RESOURCE; ri++) {
+		if (dev->resource[ri].flags & IORESOURCE_IO &&
+		    pci_resource_len(dev, ri) != 0) {
+			if (devfs_register(device_dir_handle, "io",
+					   DEVFS_FL_NONE, 0, 0,
+					   S_IFREG | S_IRUSR | S_IWUSR,
+					   &base_fops, 
+					   &dev->resource[ri]) == NULL)
+				return failure;
+			break;
+		}
+	}
+
+	/* register a node corresponding to the device's ROM resource,
+           if present */
+	if (pci_resource_len(dev, PCI_ROM_RESOURCE) != 0) {
+		nd = new_node();
+		if (nd == NULL)
+			return failure;
+		node_devfs_handle = devfs_register(device_dir_handle, "rom",
+						   DEVFS_FL_NONE, 0, 0,
+						   S_IFREG | S_IRUSR,
+						   &rom_fops, nd);
+		if (node_devfs_handle == NULL)
+			return failure;
+		init_rom_node(nd, dev, node_devfs_handle);
+	}
+
+	/* register a node that allows ioctl's to read and write to
+           the device's config space */
+	if (devfs_register(device_dir_handle, "config", DEVFS_FL_NONE,
+			   0, 0, S_IFREG | S_IRUSR | S_IWUSR,
+			   &config_fops, dev) == NULL)
+		return failure;
+
+
+	/* finally, register a node that allows ioctl's to allocate
+           and free DMA buffers, as well as memory map those
+           buffers. */
+	nd = new_node();
+	if (nd == NULL)
+		return failure;
+	node_devfs_handle =
+		devfs_register(device_dir_handle, "dma", DEVFS_FL_NONE,
+			       0, 0, S_IFREG | S_IRUSR | S_IWUSR,
+			       &dma_fops, nd);
+	if (node_devfs_handle == NULL)
+		return failure;
+	init_dma_node(nd, dev, node_devfs_handle);
+
+#ifdef DEBUG_PCIBA
+	dump_nodes(&global_node_list);
 #endif
-    return map;
+	
+	return success;
 }
 
-/* ================================================================
- *            driver teardown, unregister and unload
- */
-int
-pciba_unload(void)
-{
-#if DEBUG_PCIBA
-    printk("pciba_unload()\n");
-#endif
 
-    if (atomic_read(&pciba_prevent_unload))
-	return -1;
+static int
+generic_open(struct inode * inode, struct file * file)
+{
+	TRACE();
 
-    pciio_iterate("pciba_", pciba_unload_me);
+	/* FIXME: should check that they're not trying to open the ROM
+           writable */
 
-    return 0;
+	return 0; /* success */
 }
 
-int
-pciba_unreg(void)
+
+static int
+rom_mmap(struct file * file, struct vm_area_struct * vma)
 {
+	unsigned long pci_pa;
+	struct node_data * nd;
 
-#if DEBUG_PCIBA
-    printf("pciba_unreg()\n");
-#endif
+	TRACE();
 
-    if (atomic_read(&pciba_prevent_unload))
-	return -1;
+	nd = (struct node_data * )file->private_data;
 
-    pciio_driver_unregister("pciba_");
-    return 0;
+	pci_pa = pci_resource_start(nd->u.rom.dev, PCI_ROM_RESOURCE);
+
+	if (!nd->u.rom.mmapped) {
+		nd->u.rom.mmapped = true;
+		DPRINTF("Enabling ROM address decoder.\n");
+		DPRINTF(
+"rom_mmap: FIXME: some cards do not allow both ROM and memory addresses to\n"
+"rom_mmap: FIXME: be enabled simultaneously, as they share a decoder.\n");
+		pci_read_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				      &nd->u.rom.saved_rom_base_reg);
+		DPRINTF("ROM base address contains %x\n",
+			nd->u.rom.saved_rom_base_reg);
+		pci_write_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				       nd->u.rom.saved_rom_base_reg |
+				       PCI_ROM_ADDRESS_ENABLE);
+	}
+	
+	return mmap_pci_address(vma, pci_pa);
 }
 
-int
-pciba_detach(devfs_handle_t conn)
+
+static int
+rom_release(struct inode * inode, struct file * file)
 {
-    devfs_handle_t          base;
-    pciba_bus_t             bus;
-    devfs_handle_t          gconn;
-    devfs_handle_t          gbase;
+	struct node_data * nd;
 
-    pciio_info_t            pciio_info;
-    devfs_handle_t          master;
-    arbitrary_info_t        ainfo;
-    int			    ret;
+	TRACE();
 
-#if DEBUG_PCIBA
-    printf("pciba_detach(%v)\n", conn);
-#endif
+	nd = (struct node_data * )file->private_data;
 
-    if ((GRAPH_SUCCESS !=
-	 hwgraph_traverse(conn, ".guest", &gconn)) ||
-	(conn == gconn))
-	gconn = GRAPH_VERTEX_NONE;
-
-    if (gconn != GRAPH_VERTEX_NONE) {
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_CFG);
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_DMA);
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_ROM);
-#if ULI
-	pciba_sub_detach(gconn, PCIBA_EDGE_LBL_INTR);
-#endif
-	if (GRAPH_SUCCESS == hwgraph_edge_remove(conn, PCIBA_EDGE_LBL_BASE, &gbase)) {
-	    pciba_sub_detach(gconn, PCIBA_EDGE_LBL_MEM);
-	    pciba_sub_detach(gconn, PCIBA_EDGE_LBL_IO);
-	    pciba_sub_detach(gbase, "0");
-	    pciba_sub_detach(gbase, "1");
-	    pciba_sub_detach(gbase, "2");
-	    pciba_sub_detach(gbase, "3");
-	    pciba_sub_detach(gbase, "4");
-	    pciba_sub_detach(gbase, "5");
-	    hwgraph_vertex_unref(gbase);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(gbase))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(%v/base) failed (%d)",
-			conn, ret);
-#else
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(0x%x/base) failed (%d)",
-			conn, ret);
-#endif
-#if DEBUG_REFCT
-		printk("\tretained refct %d\n", hwgraph_vertex_refct(gbase));
-#endif
-	    }
+	if (nd->u.rom.mmapped) {
+		nd->u.rom.mmapped = false;
+		DPRINTF("Disabling ROM address decoder.\n");
+		pci_write_config_dword(nd->u.rom.dev, PCI_ROM_ADDRESS,
+				       nd->u.rom.saved_rom_base_reg);
 	}
-    }
+	return 0; /* indicate success */
+}
 
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_CFG);
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_DMA);
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_ROM);
-#if ULI
-    pciba_sub_detach(conn, PCIBA_EDGE_LBL_INTR);
-#endif
 
-    if (GRAPH_SUCCESS == hwgraph_edge_remove(conn, PCIBA_EDGE_LBL_BASE, &base)) {
-	pciba_sub_detach(conn, PCIBA_EDGE_LBL_MEM);
-	pciba_sub_detach(conn, PCIBA_EDGE_LBL_IO);
-	pciba_sub_detach(base, "0");
-	pciba_sub_detach(base, "1");
-	pciba_sub_detach(base, "2");
-	pciba_sub_detach(base, "3");
-	pciba_sub_detach(base, "4");
-	pciba_sub_detach(base, "5");
-	hwgraph_vertex_unref(base);
-	if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(base))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    PRINT_WARNING(CE_WARN, "pciba: hwgraph_vertex_destroy(%v/base) failed (%d)",
-		    conn, ret);
-#else
-	    PRINT_WARNING(CE_WARN, "pciba: hwgraph_vertex_destroy(0x%x/base) failed (%d)",
-		    conn, ret);
-#endif
-#if DEBUG_REFCT
-	    printk("\tretained refct %d\n", hwgraph_vertex_refct(base));
-#endif
-	}
-    }
+static int
+base_mmap(struct file * file, struct vm_area_struct * vma)
+{
+	struct resource * resource;
 
-    bus = pciba_find_bus(conn, 0);
-    if (bus && !--(bus->refct)) {
+	TRACE();
 
-	pciio_info = pciio_info_get(conn);
+	resource = (struct resource *)file->private_data;
 
-	master = pciio_info_master_get(pciio_info);
+	return mmap_pci_address(vma, resource->start);
+}
 
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_IO);
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_MEM);
-	pciba_sub_detach(master, PCIBA_EDGE_LBL_CFG);
-	hwgraph_info_remove_LBL(master, PCIBA_INFO_LBL_BUS, &ainfo);
 
-#if DEBUG_PCIBA
-	printf("pcbia_detach: DEL(bus) at %v\n", master);
-#endif
-	DEL(bus);
-    } 
+static int
+config_ioctl(struct inode * inode, struct file * file, 
+	     unsigned int cmd, 
+	     unsigned long arg)
+{
+	struct pci_dev * dev;
 
-    return 0;
-}
+	union cfg_data {
+		uint8_t byte;
+		uint16_t word;
+		uint32_t dword;
+	} read_data, write_data;
 
-static void
-pciba_sub_detach1(devfs_handle_t conn,
-		  char *name,
-		  char *suf)
-{
-    devfs_handle_t         vhdl;
-    pciba_soft_t            soft;
-    pciba_comm_t	    comm;
-    int			    ret;
-    char		nbuf[128];
-
-    if (suf && *suf) {
-	strcpy(nbuf, name);
-	name = nbuf;
-	strcat(name, suf);
-    }
-
-    if ((GRAPH_SUCCESS == hwgraph_edge_remove(conn, name, &vhdl)) &&
-	((soft = pciba_soft_get(vhdl)) != NULL)) {
-#if DEBUG_PCIBA
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	prink("pciba_sub_detach(%v,%s)\n", conn, name);
-#else
-	prink("pciba_sub_detach(0x%x,%s)\n", conn, name);
-#endif
-#endif
+	int dir, size, offset;
 
-	hwgraph_vertex_unref(soft->vhdl);
-#if DEBUG_REFCT
-	printk("\tadjusted refct %d (soft ref: %d)\n",
-		hwgraph_vertex_refct(vhdl),
-		soft->refct);
-#endif
-	if (!--(soft->refct)) {
-	    comm = soft->comm;
-	    if (!--(comm->refct)) {
-		DEL(comm);
-	    }
-	    pciba_soft_set(vhdl, 0);
-	    DEL(soft);
-
-	    hwgraph_vertex_unref(vhdl);
-	    if (GRAPH_SUCCESS != (ret = hwgraph_vertex_destroy(vhdl))) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(0x%x/%s) failed (%d)",
-			conn, name, ret);
-#else
-		PRINT_WARNING("pciba: hwgraph_vertex_destroy(%v/%s) failed (%d)",
-			conn, name, ret);
-#endif
-#if DEBUG_REFCT
-		printk("\tretained refct %d\n", hwgraph_vertex_refct(vhdl));
-#endif
-	    }
-	}
-    }
-}
+	TRACE();
 
-static void
-pciba_sub_detach(devfs_handle_t conn,
-		 char *name)
-{
-    pciba_sub_detach1(conn, name, "");
-    pciba_sub_detach1(conn, name, "_le");
-    pciba_sub_detach1(conn, name, "_be");
-}
+	DPRINTF("cmd = %x (DIR = %x, TYPE = %x, NR = %x, SIZE = %x)\n", 
+		cmd, 
+		_IOC_DIR(cmd), _IOC_TYPE(cmd), _IOC_NR(cmd), _IOC_SIZE(cmd));
+	DPRINTF("arg = %lx\n", arg);
 
-static void
-pciba_unload_me(devfs_handle_t pconn_vhdl)
-{
-    devfs_handle_t         c_vhdl;
+	dev = (struct pci_dev *)file->private_data;
 
-#if DEBUG_PCIBA
-    printf("pciba_unload_me(%v)\n", pconn_vhdl);
-#endif
+	/* PCIIOCCFG{RD,WR}: read and/or write PCI configuration
+	   space. If both, the read happens first (this becomes a swap
+	   operation, atomic with respect to other updates through
+	   this path).  */
 
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, PCIBA_EDGE_LBL_CFG, &c_vhdl))
-	return;
+	dir = _IOC_DIR(cmd);
 
-    hwgraph_vertex_unref(c_vhdl);
-}
+#define do_swap(suffix, type)	 					\
+	do {								\
+		if (dir & _IOC_READ) {					\
+			pci_read_config_##suffix(dev, _IOC_NR(cmd), 	\
+						 &read_data.suffix);	\
+		}							\
+		if (dir & _IOC_WRITE) {					\
+			get_user(write_data.suffix, (type)arg);		\
+			pci_write_config_##suffix(dev, _IOC_NR(cmd), 	\
+						  write_data.suffix);	\
+		}							\
+		if (dir & _IOC_READ) {					\
+			put_user(read_data.suffix, (type)arg);		\
+		}							\
+	} while (0)
 
-/* ================================================================
- *            standard unix entry points
- */
+	size = _IOC_SIZE(cmd);
+	offset = _IOC_NR(cmd);
 
-/*ARGSUSED */
-int
-pciba_open(dev_t *devp, int flag, int otyp, struct cred *crp)
-{
+	DPRINTF("sanity check\n");
+	if (((size > 0) || (size <= 4)) &&
+	    ((offset + size) <= 256) &&
+	    (dir & (_IOC_READ | _IOC_WRITE))) {
 
-#if DEBUG_PCIBA
-    printf("pciba_open(%V)\n", *devp);
-#endif
-    return 0;
+		switch (size)
+		{
+		case 1:
+			do_swap(byte, uint8_t *);
+			break;
+		case 2:
+			do_swap(word, uint16_t *);
+			break;
+		case 4:
+			do_swap(dword, uint32_t *);
+			break;
+		default:
+			DPRINTF("invalid ioctl\n");
+			return -EINVAL;
+		}
+	} else
+		return -EINVAL;
+		
+	return 0;
 }
 
-/*ARGSUSED */
-int
-pciba_close(dev_t dev)
-{
-    devfs_handle_t         vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-
-#if DEBUG_PCIBA
-    printf("pciba_close(%V)\n", dev);
-#endif
 
-    /* if there is pending DMA for this device, hit the
-     * device over the head with a baseball bat and
-     * release the system memory resources.
-     */
-    if (soft && soft->comm->dmap) {
-	pciba_dma_t             next;
-	pciba_dma_t             dmap;
-
-	pciba_soft_lock(soft);
-	if (dmap = soft->comm->dmap) {
-	    soft->comm->dmap = 0;
-
-	    pciio_reset(soft->comm->conn);
-
-	    do {
-		if (!dmap->kaddr)
-		    break;
-		if (!dmap->paddr)
-		    break;
-		if (dmap->bytes < NBPP)
-		    break;
-		next = dmap->next;
-		kvpfree(dmap->kaddr, dmap->bytes / NBPP);
-		dmap->paddr = 0;
-		dmap->bytes = 0;
-		DEL(dmap);
-	    } while (dmap = next);
+#ifdef DEBUG_PCIBA
+static void
+dump_allocations(struct list_head * dalp)
+{
+	struct dma_allocation * dap;
+	struct list_head * p;
+	
+	printk("{\n");
+	list_for_each(p, dalp) {
+		dap = list_entry(p, struct dma_allocation, 
+				 list);
+		printk("  handle = %lx, va = %p\n",
+		       dap->handle, dap->va);
 	}
-	pciba_soft_unlock(soft);
-    }
-    return 0;
+	printk("}\n");
 }
 
-/* ARGSUSED */
-int
-pciba_read(dev_t dev, cred_t *crp)
+static void
+dump_nodes(struct list_head * nodes)
 {
-#if DEBUG_PCIBA
-    printf("pciba_read(%V)\n", dev);
-#endif
-
-    return EINVAL;
+	struct node_data * ndp;
+	struct list_head * p;
+	
+	printk("{\n");
+	list_for_each(p, nodes) {
+		ndp = list_entry(p, struct node_data, 
+				 global_node_list);
+		printk("  %p\n", (void *)ndp);
+	}
+	printk("}\n");
 }
 
-/* ARGSUSED */
-int
-pciba_write(dev_t dev, cred_t *crp)
+
+#if 0
+#define NEW(ptr) (ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
+
+static void
+test_list(void)
 {
-#if DEBUG_PCIBA
-    printf("pciba_write(%V)\n", dev);
-#endif
+	u64 i;
+	LIST_HEAD(the_list);
 
-    return EINVAL;
+	for (i = 0; i < 5; i++) {
+		struct dma_allocation * new_alloc;
+		NEW(new_alloc);
+		new_alloc->va = (void *)i;
+		new_alloc->handle = 5*i;
+		printk("%d - the_list->next = %lx\n", i, the_list.next);
+		list_add(&new_alloc->list, &the_list);
+	}
+	dump_allocations(&the_list);
 }
-
-/*ARGSUSED */
-int
-pciba_ioctl(dev_t dev, int cmd, void *uarg, int mode, cred_t *crp, int *rvalp)
-{
-    devfs_handle_t          vhdl;
-    pciba_soft_t            soft;
-    pciio_space_t           space;
-    ioctl_arg_buffer_t      arg;
-    int                     psize;
-    int                     err = 0;
-
-#if ULI
-    char		    abi = get_current_abi();
-    pciio_intr_t            intr=0;
-    device_desc_t           desc;
-    cpuid_t                 intrcpu;
-    unsigned                lines;
-    struct uli             *uli = 0;
 #endif
-    unsigned                flags;
-    void                   *kaddr = 0;
-    iopaddr_t               paddr;
-    pciba_dma_h             dmah;
-    pciba_dma_t             dmap = 0;
-    pciio_dmamap_t          dmamap = 0;
-    size_t                  bytes;
-    int                     pages;
-    pciaddr_t               daddr;
-
-#if DEBUG_PCIBA
-    printf("pciba_ioctl(%V,0x%x)\n", dev, cmd);
 #endif
 
-    psize = (cmd >> 16) & IOCPARM_MASK;
-
-#if ULI
-    ASSERT(sizeof(struct uliargs) > 8);	/* prevent CFG access conflict */
-    ASSERT(sizeof(struct uliargs) <= IOCPARM_MASK);
-#endif
 
-    arg.ca = uarg;
+static LIST_HEAD(dma_buffer_list);
 
-    if ((psize > 0) && (cmd & (IOC_OUT | IOC_IN))) {
-	if (psize > sizeof(arg))
-	    err = EINVAL;		/* "bad parameter size */
-	else {
-	    if (cmd & IOC_OUT)
-		bzero(arg.data, psize);
-	    if ((cmd & IOC_IN) &&
-		(copyin(uarg, arg.data, psize) < 0))
-		err = EFAULT;		/* "parameter copyin failed" */
-	}
-    }
-    vhdl = dev_to_vhdl(dev);
-    soft = pciba_soft_get(vhdl);
-    space = soft->space;
-
-    if (err == 0) {
-	err = EINVAL;			/* "invalid ioctl for this vertex" */
-	switch (space) {
-#if ULI
-	case PCIIO_SPACE_NONE:		/* the "intr" vertex */
-	    /* PCIIOCSETULI: set up user interrupts.
-	     */
-	    lines = cmd & 15;
-	    if (ABI_IS_64BIT(abi)) {
-		if (cmd != PCIIOCSETULI(lines)) {
-		    err = EINVAL;		/* "invalid ioctl for this vertex" */
-		    break;
-		}
-	    }
-	    else {
-		struct uliargs uliargs;
-
-		if (cmd != PCIIOCSETULI32(lines)) {
-		    err = EINVAL;		/* "invalid ioctl for this vertex" */
-		    break;
-		}
-		
-		uliargs32_to_uliargs(&arg.uli32, &uliargs);
-		arg.uli = uliargs;
-	    }
-	    desc = device_desc_dup(soft->comm->conn);
-	    device_desc_flags_set(desc, (device_desc_flags_get(desc) |
-					 D_INTR_NOTHREAD));
-	    device_desc_intr_swlevel_set(desc, INTR_SWLEVEL_NOTHREAD_DEFAULT);
-	    device_desc_intr_name_set(desc, "PCIBA");
-	    device_desc_default_set(soft->comm->conn, desc);
-
-	    /* When designating interrupts, the slot number
-	     * is taken from the connection point.
-	     * Bits 0..3 are used to select INTA..INTD; more
-	     * than one bit can be specified. These should
-	     * be constructed using PCIIO_INTR_LINE_[ABCD].
-	     */
-	    intr = pciio_intr_alloc
-		(soft->comm->conn, desc, lines, soft->vhdl);
-	    if (intr == 0) {
-		err = ENOMEM;		/* "insufficient resources" */
-		break;
-	    }
-	    intrcpu = cpuvertex_to_cpuid(pciio_intr_cpu_get(intr));
 
-	    if (err = new_uli(&arg.uli, &uli, intrcpu)) {
-		break;			/* "unable to set up ULI" */
-	    }
-	    atomic_inc(&pciba_prevent_unload);
-
-	    pciio_intr_connect(intr, pciba_intr, uli, (void *) 0);
-
-	    /* NOTE: don't set the teardown function
-	     * until the interrupt is connected.
-	     */
-	    uli->teardownarg1 = (__psint_t) intr;
-	    uli->teardown = pciba_clearuli;
-
-	    arg.uli.id = uli->index;
-
-	    if (!ABI_IS_64BIT(abi)) {
-		struct uliargs32 uliargs32;
-		uliargs_to_uliargs32(&arg.uli, &uliargs32);
-		arg.uli32 = uliargs32;
-	    }
+static int
+dma_ioctl(struct inode * inode, struct file * file, 
+	  unsigned int cmd, 
+	  unsigned long arg)
+{
+	struct node_data * nd;
+	uint64_t argv;
+	int result;
+	struct dma_allocation * dma_alloc;
+	struct list_head * iterp;
 
-	    err = 0;
-	    break;
-#endif
+	TRACE();
 
-	case PCIBA_SPACE_UDMA:		/* the "dma" vertex */
+	DPRINTF("cmd = %x\n", cmd);
+	DPRINTF("arg = %lx\n", arg);
 
-	    switch (cmd) {
+	nd = (struct node_data *)file->private_data;
 
-	    case PCIIOCDMAALLOC:
-		/* PCIIOCDMAALLOC: allocate a chunk of physical
-		 * memory and set it up for DMA. Return the
-		 * PCI address that gets to it.
-		 * NOTE: this allocates memory local to the
-		 * CPU doing the ioctl, not local to the
-		 * device that will be doing the DMA.
-		 */
-
-		if (!_CAP_ABLE(CAP_DEVICE_MGT)) {
-		    err = EPERM;
-		    break;
-		}
-		/* separate the halves of the incoming parameter */
-		flags = arg.ud >> 32;
-		bytes = arg.ud & 0xFFFFFFFF;
-
-#if DEBUG_PCIBA
-		printf("pciba: user wants 0x%x bytes of DMA, flags 0x%x\n",
-		       bytes, flags);
+#ifdef DEBUG_PCIBA
+	DPRINTF("at dma_ioctl entry\n");
+	dump_allocations(&nd->u.dma.dma_allocs);
 #endif
 
-		/* round up the requested size to the next highest page */
-		pages = (bytes + NBPP - 1) / NBPP;
-
-		/* make sure the requested size is something reasonable */
-		if (pages > pci_user_dma_max_pages) {
-#if DEBUG_PCIBA
-		    printf("pciba: request for too much buffer space\n");
+	switch (cmd) {
+	case PCIIOCDMAALLOC:
+		/* PCIIOCDMAALLOC: allocate a chunk of physical memory
+		   and set it up for DMA. Return the PCI address that
+		   gets to it.  */
+		DPRINTF("case PCIIOCDMAALLOC (%lx)\n", PCIIOCDMAALLOC);
+		
+		if ( (result = get_user(argv, (uint64_t *)arg)) )
+			return result;
+		DPRINTF("argv (size of buffer) = %lx\n", argv);
+
+		dma_alloc = (struct dma_allocation *)
+			kmalloc(sizeof(struct dma_allocation), GFP_KERNEL);
+		if (dma_alloc == NULL)
+			return -ENOMEM;
+
+		dma_alloc->size = (size_t)argv;
+		dma_alloc->va = pci_alloc_consistent(nd->u.dma.dev,
+						     dma_alloc->size,
+						     &dma_alloc->handle);
+		DPRINTF("dma_alloc->va = %p, dma_alloc->handle = %lx\n",
+			dma_alloc->va, dma_alloc->handle);
+		if (dma_alloc->va == NULL) {
+			kfree(dma_alloc);
+			return -ENOMEM;
+		}
+
+		list_add(&dma_alloc->list, &nd->u.dma.dma_allocs);
+		if ( (result = put_user((uint64_t)dma_alloc->handle, 
+				      (uint64_t *)arg)) ) {
+			DPRINTF("put_user failed\n");
+			pci_free_consistent(nd->u.dma.dev, (size_t)argv,
+					    dma_alloc->va, dma_alloc->handle);
+			kfree(dma_alloc);
+			return result;
+		}
+
+#ifdef DEBUG_PCIBA
+		DPRINTF("after insertion\n");
+		dump_allocations(&nd->u.dma.dma_allocs);
 #endif
-		    err = EINVAL;
-		    break;		/* "request for too much buffer space" */
-		}
-		/* "correct" number of bytes */
-		bytes = pages * NBPP;
+		break;
 
-		/* allocate the space */
-		/* XXX- force to same node as the device? */
-		/* XXX- someday, we want to handle user buffers,
-		 *    and noncontiguous pages, but this will
-		 *      require either fancy mapping or handing
-		 *      a list of blocks back to the user. For
-		 *      now, just tell users to allocate a lot of
-		 *      individual single-pages and manage their
-		 *      scatter-gather manually.
-		 */
-		kaddr = kvpalloc(pages, VM_DIRECT | KM_NOSLEEP, 0);
-		if (kaddr == 0) {
-#if DEBUG_PCIBA
-		    printf("pciba: unable to get %d contiguous pages\n", pages);
-#endif
-		    err = EAGAIN;	/* "insufficient resources, try again later" */
-		    break;
-		}
-#if DEBUG_PCIBA
-		printf("pciba: kaddr is 0x%x\n", kaddr);
-#endif
-		paddr = kvtophys(kaddr);
+	case PCIIOCDMAFREE:
+		DPRINTF("case PCIIOCDMAFREE (%lx)\n", PCIIOCDMAFREE);
 
-		daddr = pciio_dmatrans_addr
-		    (soft->comm->conn, 0, paddr, bytes, flags);
-		if (daddr == 0) {	/* "no direct path available" */
-#if DEBUG_PCIBA
-		    printf("pciba: dmatrans failed, trying dmamap\n");
-#endif
-		    dmamap = pciio_dmamap_alloc
-			(soft->comm->conn, 0, bytes, flags);
-		    if (dmamap == 0) {
-#if DEBUG_PCIBA
-			printf("pciba: unable to allocate dmamap\n");
-#endif
-			err = ENOMEM;
-			break;		/* "out of mapping resources" */
-		    }
-		    daddr = pciio_dmamap_addr
-			(dmamap, paddr, bytes);
-		    if (daddr == 0) {
-#if DEBUG_PCIBA
-			printf("pciba: dmamap_addr failed\n");
-#endif
-			err = EINVAL;
-			break;		/* "can't get there from here" */
-		    }
-		}
-#if DEBUG_PCIBA
-		printf("pciba: daddr is 0x%x\n", daddr);
+		if ( (result = get_user(argv, (uint64_t *)arg)) ) {
+			DPRINTF("get_user failed\n");
+			return result;
+		}
+
+		DPRINTF("argv (physical address of DMA buffer) = %lx\n", argv);
+		list_for_each(iterp, &nd->u.dma.dma_allocs) {
+			struct dma_allocation * da =
+				list_entry(iterp, struct dma_allocation, list);
+			if (da->handle == argv) {
+				pci_free_consistent(nd->u.dma.dev, da->size,
+						    da->va, da->handle);
+				list_del(&da->list);
+				kfree(da);
+#ifdef DEBUG_PCIBA
+				DPRINTF("after deletion\n");
+				dump_allocations(&nd->u.dma.dma_allocs);
 #endif
-		NEW(dmap);
-		if (!dmap) {
-		    err = ENOMEM;
-		    break;		/* "no memory available" */
+				return 0; /* success */
+			}
 		}
-		dmap->bytes = bytes;
-		dmap->pages = pages;
-		dmap->paddr = paddr;
-		dmap->kaddr = kaddr;
-		dmap->map = dmamap;
-		dmap->daddr = daddr;
-		dmap->handle = 0;
-
-#if DEBUG_PCIBA
-		printf("pciba: dmap 0x%x contains va 0x%x bytes 0x%x pa 0x%x pages 0x%x daddr 0x%x\n",
-		       dmap, kaddr, bytes, paddr, pages, daddr);
-#endif
+		/* previously allocated dma buffer wasn't found */
+		DPRINTF("attempt to free invalid dma handle\n");
+		return -EINVAL;
 
-		arg.ud = dmap->daddr;
+	default:
+		DPRINTF("undefined ioctl\n");
+		return -EINVAL;
+	}
 
-		err = 0;
-		break;
+	DPRINTF("success\n");
+	return 0;
+}
+		
 
-	    case PCIIOCDMAFREE:
-		/* PCIIOCDMAFREE: Find the chunk of
-		 * User DMA memory, and release its
-		 * resources back to the system.
-		 */
-
-		if (!_CAP_ABLE(CAP_DEVICE_MGT)) {
-		    err = EPERM;	/* "you can't do that" */
-		    break;
-		}
-		if (soft->comm->dmap == NULL) {
-		    err = EINVAL;	/* "no User DMA to free" */
-		    break;
-		}
-		/* find the request. */
-		daddr = arg.ud;
-		err = EINVAL;		/* "block not found" */
-		pciba_soft_lock(soft);
-		for (dmah = &soft->comm->dmap; dmap = *dmah; dmah = &dmap->next) {
-		    if (dmap->daddr == daddr) {
-			if (dmap->handle != 0) {
-			    dmap = 0;	/* don't DEL this dmap! */
-			    err = EINVAL;	/* "please unmap first" */
-			    break;		/* break outa for loop. */
-			}
-			*dmah = dmap->next;
+static int
+dma_mmap(struct file * file, struct vm_area_struct * vma)
+{
+	struct node_data * nd;
+	struct list_head * iterp;
+	int result;
+	
+	TRACE();
 
-			if (dmamap = dmap->map) {
-			    pciio_dmamap_free(dmamap);
-			    dmamap = 0;	/* don't free it twice! */
+	nd = (struct node_data *)file->private_data;
+	
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
+	DPRINTF("offset = %lx\n", vma->vm_pgoff);
+
+	/* get kernel virtual address for the dma buffer (necessary
+	 * for the mmap). */
+	list_for_each(iterp, &nd->u.dma.dma_allocs) {
+		struct dma_allocation * da =
+			list_entry(iterp, struct dma_allocation, list);
+		/* why does mmap shift its offset argument? */
+		if (da->handle == vma->vm_pgoff << PAGE_SHIFT) {
+			DPRINTF("found dma handle\n");
+			if ( (result = mmap_kernel_address(vma,
+							   da->va)) ) {
+				return result; /* failure */
+			} else {
+				/* it seems like at least one of these
+				   should show up in user land....
+				   I'm missing something */
+				*(char *)da->va = 0xaa;
+				strncpy(da->va, "        Toastie!", da->size);
+				if (put_user(0x18badbeeful,
+					     (u64 *)vma->vm_start))
+					DPRINTF("put_user failed?!\n");
+				return 0; /* success */
 			}
-			kvpfree(dmap->kaddr, dmap->bytes / NBPP);
-			DEL(dmap);
-			dmap = 0;	/* don't link this back into the list! */
-			err = 0;	/* "all done" */
-			break;		/* break outa for loop. */
-		    }
-		}
-		pciba_soft_unlock(soft);
-		break;		/* break outa case PCIIOCDMAFREE: */
-	    }
-	    break;		/* break outa case PCIBA_SPACE_UDMA: */
-
-	case PCIIO_SPACE_CFG:
-
-	    /* PCIIOCCFG{RD,WR}: read and/or write
-	     * PCI configuration space. If both,
-	     * the read happens first (this becomes
-	     * a swap operation, atomic with respect
-	     * to other updates through this path).
-	     *
-	     * Should be *last* IOCTl command checked,
-	     * so other patterns can nip useless codes
-	     * out of the space this decodes.
-	     */
-	    err = EINVAL;
-	    if ((psize > 0) || (psize <= 8) &&
-		(((cmd & 0xFF) + psize) <= 256) &&
-		(cmd & (IOC_IN | IOC_OUT))) {
-
-		uint64_t                rdata;
-		uint64_t                wdata;
-		int                     shft;
-
-		shft = 64 - (8 * psize);
-
-		wdata = arg.ud >> shft;
-
-		pciba_soft_lock(soft);
-
-		if (cmd & IOC_OUT)
-		    rdata = pciio_config_get(soft->comm->conn, cmd & 0xFFFF, psize);
-		if (cmd & IOC_IN)
-		    pciio_config_set(soft->comm->conn, cmd & 0xFFFF, psize, wdata);
-
-		pciba_soft_unlock(soft);
 
-		arg.ud = rdata << shft;
-		err = 0;
-		break;
-	    }
-	    break;
-	}
-    }
-    /* done: come here if all went OK.
-     */
-    if ((err == 0) &&
-	((cmd & IOC_OUT) && (psize > 0)) &&
-	copyout(arg.data, uarg, psize))
-	err = EFAULT;
-
-    /* This gets delayed until after the copyout so we
-     * do not free the dmap on a copyout error, or
-     * alternately end up with a dangling allocated
-     * buffer that the user never got back.
-     */
-    if ((err == 0) && dmap) {
-	pciba_soft_lock(soft);
-	dmap->next = soft->comm->dmap;
-	soft->comm->dmap = dmap;
-	pciba_soft_unlock(soft);
-    }
-    if (err) {
-	/* Things went badly. Clean up.
-	 */
-#if ULI
-	if (intr) {
-	    pciio_intr_disconnect(intr);
-	    pciio_intr_free(intr);
-	}
-	if (uli)
-	    free_uli(uli);
-#endif
-	if (dmap) {
-	    if (dmap->map && (dmap->map != dmamap))
-		pciio_dmamap_free(dmap->map);
-	    DEL(dmap);
+		}
 	}
-	if (dmamap)
-	    pciio_dmamap_free(dmamap);
-	if (kaddr)
-	    kvpfree(kaddr, pages);
-    }
-    return *rvalp = err;
+	DPRINTF("attempt to mmap an invalid dma handle\n");
+	return -EINVAL;
 }
 
-/* ================================================================
- *            mapping support
- */
-
-/*ARGSUSED */
-int
-pciba_map(dev_t dev, vhandl_t *vt,
-	  off_t off, size_t len, uint32_t prot)
-{
-    devfs_handle_t          vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-    devfs_handle_t          conn = soft->comm->conn;
-    pciio_space_t           space = soft->space;
-    size_t                  pages = (len + NBPP - 1) / NBPP;
-    pciio_piomap_t          pciio_piomap = 0;
-    caddr_t                 kaddr;
-    pciba_map_t             map;
-    pciba_dma_t             dmap;
 
-#if DEBUG_PCIBA
-    printf("pciba_map(%V,vt=0x%x)\n", dev, vt);
-#endif
+static int
+mmap_pci_address(struct vm_area_struct * vma, unsigned long pci_va)
+{
+	unsigned long pci_pa;
 
-    if (space == PCIBA_SPACE_UDMA) {
-	pciba_soft_lock(soft);
+	TRACE();
 
-	for (dmap = soft->comm->dmap; dmap != NULL; dmap = dmap->next) {
-	    if (off == dmap->daddr) {
-		if (pages != dmap->pages) {
-		    pciba_soft_unlock(soft);
-		    return EINVAL;	/* "size mismatch" */
-		}
-		v_mapphys(vt, dmap->kaddr, dmap->bytes);
-		dmap->handle = v_gethandle(vt);
-		pciba_soft_unlock(soft);
-#if DEBUG_PCIBA
-		printf("pciba: mapped dma at kaddr 0x%x via handle 0x%x\n",
-		       dmap->kaddr, dmap->handle);
-#endif
-		return 0;
-	    }
-	}
-	pciba_soft_unlock(soft);
-	return EINVAL;			/* "block not found" */
-    }
-    if (soft->iomem == PCIIO_SPACE_NONE)
-	return EINVAL;			/* "mmap not supported" */
-
-    kaddr = (caddr_t) pciio_pio_addr
-	(conn, 0, space, off, len, &pciio_piomap, soft->flags | PCIIO_FIXED );
-
-#if DEBUG_PCIBA
-    printf("pciba: mapped %R[0x%x..0x%x] via map 0x%x to kaddr 0x%x\n",
-	   space, space_desc, off, off + len - 1, pciio_piomap, kaddr);
-#endif
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
 
-    if (kaddr == NULL)
-	return EINVAL;			/* "you can't get there from here" */
+	/* the size of the vma doesn't necessarily correspond to the
+           size specified in the mmap call.  So we can't really do any
+           kind of sanity check here.  This is a dangerous driver, and
+           it's very easy for a user process to kill the machine.  */
 
-    NEW(map);
-    if (map == NULL) {
-	if (pciio_piomap)
-	    pciio_piomap_free(pciio_piomap);
-	return ENOMEM;			/* "unable to get memory resources */
-    }
-#ifdef LATER
-    map->uthread = curuthread;
-#endif
-    map->handle = v_gethandle(vt);
-    map->uvaddr = v_getaddr(vt);
-    map->map = pciio_piomap;
-    map->space = soft->iomem;
-    map->base = soft->base + off;
-    map->size = len;
-    pciba_map_push(soft->comm->bus, map);
-
-    /* Inform the system of the correct
-     * kvaddr corresponding to the thing
-     * that is being mapped.
-     */
-    v_mapphys(vt, kaddr, len);
-
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pciba_unmap(dev_t dev, vhandl_t *vt)
-{
-    devfs_handle_t         vhdl = dev_to_vhdl(dev);
-    pciba_soft_t            soft = pciba_soft_get(vhdl);
-    pciba_bus_t             bus = soft->comm->bus;
-    pciba_map_t             map;
-    __psunsigned_t          handle = v_gethandle(vt);
+	DPRINTF("PCI base at virtual address %lx\n", pci_va);
+	/* the __pa macro is intended for region 7 on IA64, so it
+	   doesn't work for region 6 */
+  	/* pci_pa = __pa(pci_va); */
+	/* should be replaced by __tpa or equivalent (preferably a
+	   generic equivalent) */
+	pci_pa = pci_va & ~0xe000000000000000ul;
+	DPRINTF("PCI base at physical address %lx\n", pci_pa);
 
-#if DEBUG_PCIBA
-    printf("pciba_unmap(%V,vt=%x)\n", dev, vt);
-#endif
+	/* there are various arch-specific versions of this function
+           defined in linux/drivers/char/mem.c, but it would be nice
+           if all architectures put it in pgtable.h.  it's defined
+           there for ia64.... */
+	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
 
-    /* If this is a userDMA buffer,
-     * make a note that it has been unmapped
-     * so it can be released.
-     */
-    if (soft->comm->dmap) {
-	pciba_dma_t             dmap;
-
-	pciba_soft_lock(soft);
-	for (dmap = soft->comm->dmap; dmap != NULL; dmap = dmap->next)
-	    if (handle == dmap->handle) {
-		dmap->handle = 0;
-		pciba_soft_unlock(soft);
-#if DEBUG_PCIBA
-		printf("pciba: unmapped dma at kaddr 0x%x via handle 0x%x\n",
-		       dmap->kaddr, handle);
-#endif
-		return 0;		/* found userPCI */
-	    }
-	pciba_soft_unlock(soft);
-    }
-    map = pciba_map_pop_hdl(bus, handle);
-    if (map == NULL)
-	return EINVAL;			/* no match */
+	vma->vm_flags |= VM_NONCACHED | VM_RESERVED | VM_IO;
 
-    if (map->map)
-	pciio_piomap_free(map->map);
-    DEL(map);
-
-    return (0);				/* all done OK */
+	return io_remap_page_range(vma->vm_start, pci_pa, 
+				   vma->vm_end-vma->vm_start,
+				   vma->vm_page_prot);
 }
 
-#if ULI
-void
-pciba_clearuli(struct uli *uli)
+
+static int
+mmap_kernel_address(struct vm_area_struct * vma, void * kernel_va)
 {
-    pciio_intr_t            intr = (pciio_intr_t) uli->teardownarg1;
+	unsigned long kernel_pa;
 
-#if DEBUG_PCIBA
-    printf("pciba_clearuli(0x%x)\n", uli);
-#endif
+	TRACE();
 
-    pciio_intr_disconnect(intr);
-    pciio_intr_free(intr);
-    atomic_dec(&pciba_prevent_unload);
-}
+	DPRINTF("vma->vm_start is %lx\n", vma->vm_start);
+	DPRINTF("vma->vm_end is %lx\n", vma->vm_end);
 
-void
-pciba_intr(intr_arg_t arg)
-{
-    struct uli             *uli = (struct uli *) arg;
-    int                     ulinum = uli->index;
+	/* the size of the vma doesn't necessarily correspond to the
+           size specified in the mmap call.  So we can't really do any
+           kind of sanity check here.  This is a dangerous driver, and
+           it's very easy for a user process to kill the machine.  */
 
-    extern void frs_handle_uli(void);
+	DPRINTF("mapping virtual address %p\n", kernel_va);
+	kernel_pa = __pa(kernel_va);
+	DPRINTF("mapping physical address %lx\n", kernel_pa);
 
-    if (ulinum >= 0 && ulinum < MAX_ULIS) {
-	    uli_callup(ulinum);
+	vma->vm_flags |= VM_NONCACHED | VM_RESERVED | VM_IO;
 
-	    if (private.p_frs_flags)
-		    frs_handle_uli();
-    }
-}
-#endif
-#endif /* LATER - undef as we implement each routine */
+	return remap_page_range(vma->vm_start, kernel_pa, 
+				vma->vm_end-vma->vm_start,
+				vma->vm_page_prot);
+}	
diff -Nru a/arch/ia64/sn/io/pcibr.c b/arch/ia64/sn/io/pcibr.c
--- a/arch/ia64/sn/io/pcibr.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,9824 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifdef BRINGUP
-int NeedXbridgeSwap = 0;
-#endif
-
-#include <linux/types.h>
-#include <linux/config.h>
-#include <linux/slab.h>
-#include <linux/module.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/labelcl.h>
-#include <asm/sn/xtalk/xwidget.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pcibr.h>
-#include <asm/sn/pci/pcibr_private.h>
-#include <asm/sn/pci/pci_defs.h>
-#include <asm/sn/prio.h>
-#include <asm/sn/ioerror_handling.h>
-#include <asm/sn/xtalk/xbow.h>
-#include <asm/sn/ioc3.h>
-#include <asm/sn/eeprom.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/sn_private.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/hubio.h>
-#include <asm/sn/sn1/hubio_next.h>
-#endif
-
-#ifdef __ia64
-#define rmallocmap atemapalloc
-#define rmfreemap atemapfree
-#define rmfree atefree
-#define rmalloc atealloc
-#endif
-
-#undef PCIBR_ATE_DEBUG
-#if defined(BRINGUP)
-#if 0
-#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */
-#endif
-#define PCI_DEBUG 1
-#define ATTACH_DEBUG 1
-#define PCIBR_SOFT_LIST 1
-#endif
-
-#ifndef	LOCAL
-#define	LOCAL		static
-#endif
-
-/*
- * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
- * appears that if the lucent part can get into a retry loop if it sees a
- * DAC on the bus during a pio read retry.  The loop is broken after about
- * 1ms, so we need to set up bridges holding this part to allow at least
- * 1ms for pio.
- */
-
-#define USS302_TIMEOUT_WAR
-
-#ifdef USS302_TIMEOUT_WAR
-#include <asm/sn/io.h>
-#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
-#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
-#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
-#define USS302_BRIDGE_TIMEOUT_HLD	4
-#endif
-
-#define PCIBR_LLP_CONTROL_WAR
-#if defined (PCIBR_LLP_CONTROL_WAR)
-int                     pcibr_llp_control_war_cnt;
-#endif				/* PCIBR_LLP_CONTROL_WAR */
-
-#define	NEWAf(ptr,n,f)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP))
-#define NEWA(ptr,n)	(ptr = kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP))
-#define DELA(ptr,n)	(kfree(ptr))
-
-#define NEWf(ptr,f)	NEWAf(ptr,1,f)
-#define NEW(ptr)	NEWA(ptr,1)
-#define DEL(ptr)	DELA(ptr,1)
-
-int                     pcibr_devflag = D_MP;
-
-#ifdef LATER
-#define F(s,n)		{ 1l<<(s),-(s), n }
-
-struct reg_desc         bridge_int_status_desc[] =
-{
-    F(31, "MULTI_ERR"),
-    F(30, "PMU_ESIZE_EFAULT"),
-    F(29, "UNEXPECTED_RESP"),
-    F(28, "BAD_XRESP_PACKET"),
-    F(27, "BAD_XREQ_PACKET"),
-    F(26, "RESP_XTALK_ERROR"),
-    F(25, "REQ_XTALK_ERROR"),
-    F(24, "INVALID_ADDRESS"),
-    F(23, "UNSUPPORTED_XOP"),
-    F(22, "XREQ_FIFO_OFLOW"),
-    F(21, "LLP_REC_SNERROR"),
-    F(20, "LLP_REC_CBERROR"),
-    F(19, "LLP_RCTY"),
-    F(18, "LLP_TX_RETRY"),
-    F(17, "LLP_TCTY"),
-    F(16, "SSRAM_PERR"),
-    F(15, "PCI_ABORT"),
-    F(14, "PCI_PARITY"),
-    F(13, "PCI_SERR"),
-    F(12, "PCI_PERR"),
-    F(11, "PCI_MASTER_TOUT"),
-    F(10, "PCI_RETRY_CNT"),
-    F(9, "XREAD_REQ_TOUT"),
-    F(8, "GIO_BENABLE_ERR"),
-    F(7, "INT7"),
-    F(6, "INT6"),
-    F(5, "INT5"),
-    F(4, "INT4"),
-    F(3, "INT3"),
-    F(2, "INT2"),
-    F(1, "INT1"),
-    F(0, "INT0"),
-    {0}
-};
-
-struct reg_values       space_v[] =
-{
-    {PCIIO_SPACE_NONE, "none"},
-    {PCIIO_SPACE_ROM, "ROM"},
-    {PCIIO_SPACE_IO, "I/O"},
-    {PCIIO_SPACE_MEM, "MEM"},
-    {PCIIO_SPACE_MEM32, "MEM(32)"},
-    {PCIIO_SPACE_MEM64, "MEM(64)"},
-    {PCIIO_SPACE_CFG, "CFG"},
-    {PCIIO_SPACE_WIN(0), "WIN(0)"},
-    {PCIIO_SPACE_WIN(1), "WIN(1)"},
-    {PCIIO_SPACE_WIN(2), "WIN(2)"},
-    {PCIIO_SPACE_WIN(3), "WIN(3)"},
-    {PCIIO_SPACE_WIN(4), "WIN(4)"},
-    {PCIIO_SPACE_WIN(5), "WIN(5)"},
-    {PCIIO_SPACE_BAD, "BAD"},
-    {0}
-};
-
-struct reg_desc         space_desc[] =
-{
-    {0xFF, 0, "space", 0, space_v},
-    {0}
-};
-
-#if DEBUG
-#define	device_desc	device_bits
-LOCAL struct reg_desc   device_bits[] =
-{
-    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
-    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
-    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
-    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
-    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
-    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
-    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
-    {BRIDGE_DEV_RT, 0, "RT"},
-    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
-    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
-    {BRIDGE_DEV_PREF, 0, "PREF"},
-    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
-    {BRIDGE_DEV_COH, 0, "COH"},
-    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
-    {BRIDGE_DEV_GBR, 0, "GBR"},
-    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
-    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
-    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
-    {0}
-};
-#endif	/* DEBUG */
-
-#ifdef SUPPORT_PRINTING_R_FORMAT
-LOCAL struct reg_values xio_cmd_pactyp[] =
-{
-    {0x0, "RdReq"},
-    {0x1, "RdResp"},
-    {0x2, "WrReqWithResp"},
-    {0x3, "WrResp"},
-    {0x4, "WrReqNoResp"},
-    {0x5, "Reserved(5)"},
-    {0x6, "FetchAndOp"},
-    {0x7, "Reserved(7)"},
-    {0x8, "StoreAndOp"},
-    {0x9, "Reserved(9)"},
-    {0xa, "Reserved(a)"},
-    {0xb, "Reserved(b)"},
-    {0xc, "Reserved(c)"},
-    {0xd, "Reserved(d)"},
-    {0xe, "SpecialReq"},
-    {0xf, "SpecialResp"},
-    {0}
-};
-
-LOCAL struct reg_desc   xio_cmd_bits[] =
-{
-    {WIDGET_DIDN, -28, "DIDN", "%x"},
-    {WIDGET_SIDN, -24, "SIDN", "%x"},
-    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
-    {WIDGET_TNUM, -15, "TNUM", "%x"},
-    {WIDGET_COHERENT, 0, "COHERENT"},
-    {WIDGET_DS, 0, "DS"},
-    {WIDGET_GBR, 0, "GBR"},
-    {WIDGET_VBPM, 0, "VBPM"},
-    {WIDGET_ERROR, 0, "ERROR"},
-    {WIDGET_BARRIER, 0, "BARRIER"},
-    {0}
-};
-#endif	/* SUPPORT_PRINTING_R_FORMAT */
-
-#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUG
-LOCAL struct reg_desc   ate_bits[] =
-{
-    {0xFFFF000000000000ull, -48, "RMF", "%x"},
-    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
-     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
-    {0x0000000000000F00ull, -8, "port", "%x"},
-    {0x0000000000000010ull, 0, "Barrier"},
-    {0x0000000000000008ull, 0, "Prefetch"},
-    {0x0000000000000004ull, 0, "Precise"},
-    {0x0000000000000002ull, 0, "Coherent"},
-    {0x0000000000000001ull, 0, "Valid"},
-    {0}
-};
-#endif
-
-#if PCIBR_ATE_DEBUG
-LOCAL struct reg_values ssram_sizes[] =
-{
-    {BRIDGE_CTRL_SSRAM_512K, "512k"},
-    {BRIDGE_CTRL_SSRAM_128K, "128k"},
-    {BRIDGE_CTRL_SSRAM_64K, "64k"},
-    {BRIDGE_CTRL_SSRAM_1K, "1k"},
-    {0}
-};
-
-LOCAL struct reg_desc   control_bits[] =
-{
-    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
-    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
-    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
-    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
-    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
-    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
-    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
-    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
-    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
-    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
-    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
-    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
-    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
-    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
-    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
-    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
-    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},
-    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
-    {0}
-};
-#endif
-#endif	/* LATER */
-
-/* kbrick widgetnum-to-bus layout */
-int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
-        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
-        2,                                      /* 0x8          */
-        1,                                      /* 0x9          */
-        0, 0,                                   /* 0xa - 0xb    */
-        5,                                      /* 0xc          */
-        6,                                      /* 0xd          */
-        4,                                      /* 0xe          */
-        3,                                      /* 0xf          */
-};
-
-/*
- * Additional PIO spaces per slot are
- * recorded in this structure.
- */
-struct pciio_piospace_s {
-    pciio_piospace_t        next;	/* another space for this device */
-    char                    free;	/* 1 if free, 0 if in use               */
-    pciio_space_t           space;	/* Which space is in use                */
-    iopaddr_t               start;	/* Starting address of the PIO space    */
-    size_t                  count;	/* size of PIO space                    */
-};
-
-/* Use io spin locks. This ensures that all the PIO writes from a particular
- * CPU to a particular IO device are synched before the start of the next
- * set of PIO operations to the same device.
- */
-#define pcibr_lock(pcibr_soft)		io_splock(&pcibr_soft->bs_lock)
-#define pcibr_unlock(pcibr_soft,s)	io_spunlock(&pcibr_soft->bs_lock,s)
-
-#if PCIBR_SOFT_LIST
-typedef struct pcibr_list_s *pcibr_list_p;
-struct pcibr_list_s {
-    pcibr_list_p            bl_next;
-    pcibr_soft_t            bl_soft;
-    devfs_handle_t            bl_vhdl;
-};
-pcibr_list_p            pcibr_list = 0;
-#endif
-
-typedef volatile unsigned *cfg_p;
-typedef volatile bridgereg_t *reg_p;
-
-#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"
-
-#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)
-#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)
-
-#define PCIBR_VALID_SLOT(s)	(s < 8)
-
-#ifdef SN_XXX
-extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
-                                     hub_widget_flags_t flags);
-#endif
-extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
-
-/*
- * This is the file operation table for the pcibr driver.
- * As each of the functions are implemented, put the 
- * appropriate function name below.
- */
-struct file_operations pcibr_fops = {
-        owner:  THIS_MODULE,
-        llseek: NULL,
-        read: NULL,
-        write: NULL,
-        readdir: NULL,
-        poll: NULL,
-        ioctl: NULL,
-        mmap: NULL,
-        open: NULL,
-        flush: NULL,
-        release: NULL,
-        fsync: NULL,
-        fasync: NULL,
-        lock: NULL,
-        readv: NULL,
-        writev: NULL
-};
-
-extern devfs_handle_t hwgraph_root;
-extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);
-extern int cap_able(uint64_t x);
-extern uint64_t rmalloc(struct map *mp, size_t size);
-extern void rmfree(struct map *mp, size_t size, uint64_t a);
-extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
-extern long atoi(register char *p);
-extern void *swap_ptr(void **loc, void *new);
-extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
-extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);
-extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);
-extern struct map *rmallocmap(uint64_t mapsiz);
-extern void rmfreemap(struct map *mp);
-extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);
-extern int io_path_map_widget(devfs_handle_t vertex);
-
-
-
-/* =====================================================================
- *    Function Table of Contents
- *
- *      The order of functions in this file has stopped
- *      making much sense. We might want to take a look
- *      at it some time and bring back some sanity, or
- *      perhaps bust this file into smaller chunks.
- */
-
-LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);
-LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);
-LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
-LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
-LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
-LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
-
-LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
-
-int			pcibr_wrb_flush(devfs_handle_t);
-int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);
-int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
-int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
-void                    pcibr_rrb_flush(devfs_handle_t);
-
-LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
-void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
-
-LOCAL void              pcibr_clearwidint(bridge_t *);
-LOCAL void              pcibr_setwidint(xtalk_intr_t);
-LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);
-
-void                    pcibr_init(void);
-int                     pcibr_attach(devfs_handle_t);
-int			pcibr_detach(devfs_handle_t);
-int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);
-int                     pcibr_close(devfs_handle_t, int, int, cred_t *);
-int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
-int                     pcibr_unmap(devfs_handle_t, vhandl_t *);
-int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
-
-void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
-
-LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);
-LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);
-LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);
-
-LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);
-LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
-LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
-LOCAL iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-
-pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
-void                    pcibr_piomap_free(pcibr_piomap_t);
-caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
-void                    pcibr_piomap_done(pcibr_piomap_t);
-caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
-iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
-void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
-
-LOCAL iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
-LOCAL bridge_ate_t      pcibr_flags_to_ate(unsigned);
-
-pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
-void                    pcibr_dmamap_free(pcibr_dmamap_t);
-LOCAL bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
-LOCAL iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
-iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
-alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
-void                    pcibr_dmamap_done(pcibr_dmamap_t);
-cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
-iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
-alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
-void                    pcibr_dmamap_drain(pcibr_dmamap_t);
-void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
-void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
-iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
-
-static unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
-pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
-void                    pcibr_intr_free(pcibr_intr_t);
-LOCAL void              pcibr_setpciint(xtalk_intr_t);
-int                     pcibr_intr_connect(pcibr_intr_t, intr_func_t, intr_arg_t, void *);
-void                    pcibr_intr_disconnect(pcibr_intr_t);
-
-devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
-void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
-void                    pcibr_intr_func(intr_arg_t);
-
-LOCAL void              print_bridge_errcmd(uint32_t, char *);
-
-void                    pcibr_error_dump(pcibr_soft_t);
-uint32_t              pcibr_errintr_group(uint32_t);
-LOCAL void		pcibr_pioerr_check(pcibr_soft_t);
-LOCAL void              pcibr_error_intr_handler(intr_arg_t);
-
-LOCAL int               pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *);
-LOCAL void              pcibr_error_cleanup(pcibr_soft_t, int);
-void                    pcibr_device_disable(pcibr_soft_t, int);
-LOCAL int               pcibr_pioerror(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
-LOCAL int               pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *);
-int                     pcibr_error_devenable(devfs_handle_t, int);
-
-void                    pcibr_provider_startup(devfs_handle_t);
-void                    pcibr_provider_shutdown(devfs_handle_t);
-
-int                     pcibr_reset(devfs_handle_t);
-pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
-int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
-pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
-int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
-
-LOCAL cfg_p             pcibr_config_addr(devfs_handle_t, unsigned);
-uint64_t                pcibr_config_get(devfs_handle_t, unsigned, unsigned);
-LOCAL uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
-void                    pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
-LOCAL void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
-
-LOCAL pcibr_hints_t     pcibr_hints_get(devfs_handle_t, int);
-void                    pcibr_hints_fix_rrbs(devfs_handle_t);
-void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
-void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
-void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
-void                    pcibr_hints_handsoff(devfs_handle_t);
-void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
-
-LOCAL int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
-
-#ifdef LATER
-LOCAL int	        pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t,
-                                               pcibr_slot_info_resp_t);
-LOCAL void       	pcibr_slot_func_info_return(pcibr_info_h, int,
-                                                    pcibr_slot_func_info_resp_t);
-#endif	/* LATER */
-
-LOCAL int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
-LOCAL int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
-LOCAL int		pcibr_slot_call_device_attach(devfs_handle_t,
-						      pciio_slot_t, int);
-LOCAL int		pcibr_slot_call_device_detach(devfs_handle_t,
-						      pciio_slot_t, int);
-
-LOCAL int               pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
-LOCAL int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
-#ifdef LATER
-LOCAL int		pcibr_slot_query(devfs_handle_t, pcibr_slot_info_req_t);
-#endif
-
-/* =====================================================================
- *    RRB management
- */
-
-#define LSBIT(word)		((word) &~ ((word)-1))
-
-#define PCIBR_RRB_SLOT_VIRTUAL	8
-
-LOCAL void
-do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
-{
-    bridgereg_t             status;
-
-    /* bridge_lock must be held;
-     * this RRB must be disabled.
-     */
-
-    /* wait until RRB has no outstanduing XIO packets. */
-    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
-	;				/* XXX- beats on bridge. bad idea? */
-    }
-
-    /* if the RRB has data, drain it. */
-    if (status & BRIDGE_RRB_VALID(rrb)) {
-	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
-
-	/* wait until RRB is no longer valid. */
-	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
-	    ;				/* XXX- beats on bridge. bad idea? */
-	}
-    }
-}
-
-LOCAL void
-do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
-{
-    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
-    bridgereg_t             rrbv;
-    int                     shft = 4 * (rrbn >> 1);
-    unsigned                ebit = BRIDGE_RRB_EN << shft;
-
-    rrbv = *rrbp;
-    if (rrbv & ebit)
-	*rrbp = rrbv & ~ebit;
-
-    do_pcibr_rrb_clear(bridge, rrbn);
-
-    if (rrbv & ebit)
-	*rrbp = rrbv;
-}
-
-/*
- *    pcibr_rrb_count_valid: count how many RRBs are
- *      marked valid for the specified PCI slot on this
- *      bridge.
- *
- *      NOTE: The "slot" parameter for all pcibr_rrb
- *      management routines must include the "virtual"
- *      bit; when manageing both the normal and the
- *      virtual channel, separate calls to these
- *      routines must be made. To denote the virtual
- *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
- *      number.
- *
- *      IMPL NOTE: The obvious algorithm is to iterate
- *      through the RRB fields, incrementing a count if
- *      the RRB is valid and matches the slot. However,
- *      it is much simpler to use an algorithm derived
- *      from the "partitioned add" idea. First, XOR in a
- *      pattern such that the fields that match this
- *      slot come up "all ones" and all other fields
- *      have zeros in the mismatching bits. Then AND
- *      together the bits in the field, so we end up
- *      with one bit turned on for each field that
- *      matched. Now we need to count these bits. This
- *      can be done either with a series of shift/add
- *      instructions or by using "tmp % 15"; I expect
- *      that the cascaded shift/add will be faster.
- */
-
-LOCAL int
-do_pcibr_rrb_count_valid(bridge_t *bridge,
-			 pciio_slot_t slot)
-{
-    bridgereg_t             tmp;
-
-    tmp = bridge->b_rrb_map[slot & 1].reg;
-    tmp ^= 0x11111111 * (7 - slot / 2);
-    tmp &= (0xCCCCCCCC & tmp) >> 2;
-    tmp &= (0x22222222 & tmp) >> 1;
-    tmp += tmp >> 4;
-    tmp += tmp >> 8;
-    tmp += tmp >> 16;
-    return tmp & 15;
-}
-
-/*
- *    do_pcibr_rrb_count_avail: count how many RRBs are
- *      available to be allocated for the specified slot.
- *
- *      IMPL NOTE: similar to the above, except we are
- *      just counting how many fields have the valid bit
- *      turned off.
- */
-LOCAL int
-do_pcibr_rrb_count_avail(bridge_t *bridge,
-			 pciio_slot_t slot)
-{
-    bridgereg_t             tmp;
-
-    tmp = bridge->b_rrb_map[slot & 1].reg;
-    tmp = (0x88888888 & ~tmp) >> 3;
-    tmp += tmp >> 4;
-    tmp += tmp >> 8;
-    tmp += tmp >> 16;
-    return tmp & 15;
-}
-
-/*
- *    do_pcibr_rrb_alloc: allocate some additional RRBs
- *      for the specified slot. Returns -1 if there were
- *      insufficient free RRBs to satisfy the request,
- *      or 0 if the request was fulfilled.
- *
- *      Note that if a request can be partially filled,
- *      it will be, even if we return failure.
- *
- *      IMPL NOTE: again we avoid iterating across all
- *      the RRBs; instead, we form up a word containing
- *      one bit for each free RRB, then peel the bits
- *      off from the low end.
- */
-LOCAL int
-do_pcibr_rrb_alloc(bridge_t *bridge,
-		   pciio_slot_t slot,
-		   int more)
-{
-    int                     rv = 0;
-    bridgereg_t             reg, tmp, bit;
-
-    reg = bridge->b_rrb_map[slot & 1].reg;
-    tmp = (0x88888888 & ~reg) >> 3;
-    while (more-- > 0) {
-	bit = LSBIT(tmp);
-	if (!bit) {
-	    rv = -1;
-	    break;
-	}
-	tmp &= ~bit;
-	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
-    }
-    bridge->b_rrb_map[slot & 1].reg = reg;
-    return rv;
-}
-
-/*
- *    do_pcibr_rrb_free: release some of the RRBs that
- *      have been allocated for the specified
- *      slot. Returns zero for success, or negative if
- *      it was unable to free that many RRBs.
- *
- *      IMPL NOTE: We form up a bit for each RRB
- *      allocated to the slot, aligned with the VALID
- *      bitfield this time; then we peel bits off one at
- *      a time, releasing the corresponding RRB.
- */
-LOCAL int
-do_pcibr_rrb_free(bridge_t *bridge,
-		  pciio_slot_t slot,
-		  int less)
-{
-    int                     rv = 0;
-    bridgereg_t             reg, tmp, clr, bit;
-    int                     i;
-
-    clr = 0;
-    reg = bridge->b_rrb_map[slot & 1].reg;
-
-    /* This needs to be done otherwise the rrb's on the virtual channel
-     * for this slot won't be freed !!
-     */
-    tmp = reg & 0xbbbbbbbb;
-
-    tmp ^= (0x11111111 * (7 - slot / 2));
-    tmp &= (0x33333333 & tmp) << 2;
-    tmp &= (0x44444444 & tmp) << 1;
-    while (less-- > 0) {
-	bit = LSBIT(tmp);
-	if (!bit) {
-	    rv = -1;
-	    break;
-	}
-	tmp &= ~bit;
-	reg &= ~bit;
-	clr |= bit;
-    }
-    bridge->b_rrb_map[slot & 1].reg = reg;
-
-    for (i = 0; i < 8; i++)
-	if (clr & (8 << (4 * i)))
-	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
-
-    return rv;
-}
-
-LOCAL void
-do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
-		       int slot,
-		       int more_rrbs)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     got;
-
-    for (got = 0; got < more_rrbs; ++got) {
-	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
-	    pcibr_soft->bs_rrb_res[slot & 7]--;
-	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
-	    pcibr_soft->bs_rrb_avail[slot & 1]--;
-	else
-	    break;
-	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
-	    break;
-#if PCIBR_RRB_DEBUG
-	printk( "do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
-		slot & 7, slot & 8 ? "v" : "");
-#endif
-	pcibr_soft->bs_rrb_valid[slot]++;
-    }
-#if PCIBR_RRB_DEBUG
-    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
-	    pcibr_soft->bs_rrb_avail[0],
-	    pcibr_soft->bs_rrb_avail[1]);
-    for (slot = 0; slot < 8; ++slot)
-	printk("\t%d+%d+%d",
-		0xFFF & pcibr_soft->bs_rrb_valid[slot],
-		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-		pcibr_soft->bs_rrb_res[slot]);
-	printk("\n");
-#endif
-}
-
-/*
- * Device driver interface to flush the write buffers for a specified
- * device hanging off the bridge.
- */
-int
-pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    volatile bridgereg_t   *wrb_flush;
-
-    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
-    while (*wrb_flush);
-
-    return(0);
-}
-/*
- * Device driver interface to request RRBs for a specified device
- * hanging off a Bridge.  The driver requests the total number of
- * RRBs it would like for the normal channel (vchan0) and for the
- * "virtual channel" (vchan1).  The actual number allocated to each
- * channel is returned.
- *
- * If we cannot allocate at least one RRB to a channel that needs
- * at least one, return -1 (failure).  Otherwise, satisfy the request
- * as best we can and return 0.
- */
-int
-pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
-		int *count_vchan0,
-		int *count_vchan1)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     desired_vchan0;
-    int                     desired_vchan1;
-    int                     orig_vchan0;
-    int                     orig_vchan1;
-    int                     delta_vchan0;
-    int                     delta_vchan1;
-    int                     final_vchan0;
-    int                     final_vchan1;
-    int                     avail_rrbs;
-    unsigned long           s;
-    int                     error;
-
-    /*
-     * TBD: temper request with admin info about RRB allocation,
-     * and according to demand from other devices on this Bridge.
-     *
-     * One way of doing this would be to allocate two RRBs
-     * for each device on the bus, before any drivers start
-     * asking for extras. This has the weakness that one
-     * driver might not give back an "extra" RRB until after
-     * another driver has already failed to get one that
-     * it wanted.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-
-    /* How many RRBs do we own? */
-    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
-    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
-
-    /* How many RRBs do we want? */
-    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
-    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
-
-    /* How many RRBs are free? */
-    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
-	+ pcibr_soft->bs_rrb_res[pciio_slot];
-
-    /* Figure desired deltas */
-    delta_vchan0 = desired_vchan0 - orig_vchan0;
-    delta_vchan1 = desired_vchan1 - orig_vchan1;
-
-    /* Trim back deltas to something
-     * that we can actually meet, by
-     * decreasing the ending allocation
-     * for whichever channel wants
-     * more RRBs. If both want the same
-     * number, cut the second channel.
-     * NOTE: do not change the allocation for
-     * a channel that was passed as NULL.
-     */
-    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
-	if (count_vchan0 &&
-	    (!count_vchan1 ||
-	     ((orig_vchan0 + delta_vchan0) >
-	      (orig_vchan1 + delta_vchan1))))
-	    delta_vchan0--;
-	else
-	    delta_vchan1--;
-    }
-
-    /* Figure final RRB allocations
-     */
-    final_vchan0 = orig_vchan0 + delta_vchan0;
-    final_vchan1 = orig_vchan1 + delta_vchan1;
-
-    /* If either channel wants RRBs but our actions
-     * would leave it with none, declare an error,
-     * but DO NOT change any RRB allocations.
-     */
-    if ((desired_vchan0 && !final_vchan0) ||
-	(desired_vchan1 && !final_vchan1)) {
-
-	error = -1;
-
-    } else {
-
-	/* Commit the allocations: free, then alloc.
-	 */
-	if (delta_vchan0 < 0)
-	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
-	if (delta_vchan1 < 0)
-	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
-
-	if (delta_vchan0 > 0)
-	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
-	if (delta_vchan1 > 0)
-	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
-
-	/* Return final values to caller.
-	 */
-	if (count_vchan0)
-	    *count_vchan0 = final_vchan0;
-	if (count_vchan1)
-	    *count_vchan1 = final_vchan1;
-
-	/* prevent automatic changes to this slot's RRBs
-	 */
-	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
-
-	/* Track the actual allocations, release
-	 * any further reservations, and update the
-	 * number of available RRBs.
-	 */
-
-	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
-	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
-	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
-	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
-	    + pcibr_soft->bs_rrb_res[pciio_slot]
-	    - delta_vchan0
-	    - delta_vchan1;
-	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
-
-#if PCIBR_RRB_DEBUG
-	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
-		pciio_slot, final_vchan0, final_vchan1,
-		pcibr_soft->bs_rrb_avail[0],
-		pcibr_soft->bs_rrb_avail[1]);
-	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
-	    printk("\t%d+%d+%d",
-		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
-		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
-		    pcibr_soft->bs_rrb_res[pciio_slot]);
-	printk("\n");
-#endif
-
-	error = 0;
-    }
-
-    pcibr_unlock(pcibr_soft, s);
-    return error;
-}
-
-/*
- * Device driver interface to check the current state
- * of the RRB allocations.
- *
- *   pconn_vhdl is your PCI connection point (specifies which
- *      PCI bus and which slot).
- *
- *   count_vchan0 points to where to return the number of RRBs
- *      assigned to the primary DMA channel, used by all DMA
- *      that does not explicitly ask for the alternate virtual
- *      channel.
- *
- *   count_vchan1 points to where to return the number of RRBs
- *      assigned to the secondary DMA channel, used when
- *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
- *
- *   count_reserved points to where to return the number of RRBs
- *      that have been automatically reserved for your device at
- *      startup, but which have not been assigned to a
- *      channel. RRBs must be assigned to a channel to be used;
- *      this can be done either with an explicit pcibr_rrb_alloc
- *      call, or automatically by the infrastructure when a DMA
- *      translation is constructed. Any call to pcibr_rrb_alloc
- *      will release any unassigned reserved RRBs back to the
- *      free pool.
- *
- *   count_pool points to where to return the number of RRBs
- *      that are currently unassigned and unreserved. This
- *      number can (and will) change as other drivers make calls
- *      to pcibr_rrb_alloc, or automatically allocate RRBs for
- *      DMA beyond their initial reservation.
- *
- * NULL may be passed for any of the return value pointers
- * the caller is not interested in.
- *
- * The return value is "0" if all went well, or "-1" if
- * there is a problem. Additionally, if the wrong vertex
- * is passed in, one of the subsidiary support functions
- * could panic with a "bad pciio fingerprint."
- */
-
-int
-pcibr_rrb_check(devfs_handle_t pconn_vhdl,
-		int *count_vchan0,
-		int *count_vchan1,
-		int *count_reserved,
-		int *count_pool)
-{
-    pciio_info_t            pciio_info;
-    pciio_slot_t            pciio_slot;
-    pcibr_soft_t            pcibr_soft;
-    unsigned long           s;
-    int                     error = -1;
-
-    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
-	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
-	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
-
-	s = pcibr_lock(pcibr_soft);
-
-	if (count_vchan0)
-	    *count_vchan0 =
-		pcibr_soft->bs_rrb_valid[pciio_slot];
-
-	if (count_vchan1)
-	    *count_vchan1 =
-		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
-
-	if (count_reserved)
-	    *count_reserved =
-		pcibr_soft->bs_rrb_res[pciio_slot];
-
-	if (count_pool)
-	    *count_pool =
-		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
-
-	error = 0;
-
-	pcibr_unlock(pcibr_soft, s);
-    }
-    return error;
-}
-
-/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
- * requested for each of the devies.  The evn_odd argument indicates whether
- * allcoation for the odd or even rrbs is requested and next group of four pairse
- * are the amount to assign to each device (they should sum to <= 8) and
- * whether to set the viritual bit for that device (1 indictaes yes, 0 indicates no)
- * the devices in order are either 0, 2, 4, 6 or 1, 3, 5, 7
- * if even_odd is even we alloc even rrbs else we allocate odd rrbs
- * returns 0 if no errors else returns -1
- */
-
-int
-pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
-		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
-		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
-{
-    devfs_handle_t            pcibr_vhdl;
-    pcibr_soft_t            pcibr_soft = NULL;
-    bridge_t               *bridge = NULL;
-
-    uint32_t              rrb_setting = 0;
-    int                     rrb_shift = 7;
-    uint32_t              cur_rrb;
-    int                     dev_rrbs[4];
-    int                     virt[4];
-    int                     i, j;
-    unsigned long           s;
-
-    if (GRAPH_SUCCESS ==
-	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
-	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-	if (pcibr_soft)
-	    bridge = pcibr_soft->bs_base;
-	hwgraph_vertex_unref(pcibr_vhdl);
-    }
-    if (bridge == NULL)
-	bridge = (bridge_t *) xtalk_piotrans_addr
-	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
-
-    even_odd &= 1;
-
-    dev_rrbs[0] = dev_1_rrbs;
-    dev_rrbs[1] = dev_2_rrbs;
-    dev_rrbs[2] = dev_3_rrbs;
-    dev_rrbs[3] = dev_4_rrbs;
-
-    virt[0] = virt1;
-    virt[1] = virt2;
-    virt[2] = virt3;
-    virt[3] = virt4;
-
-    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
-	return -1;
-    }
-    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
-	return -1;
-    }
-    /* walk through rrbs */
-    for (i = 0; i < 4; i++) {
-	if (virt[i]) {
-	    cur_rrb = i | 0xc;
-	    cur_rrb = cur_rrb << (rrb_shift * 4);
-	    rrb_shift--;
-	    rrb_setting = rrb_setting | cur_rrb;
-	    dev_rrbs[i] = dev_rrbs[i] - 1;
-	}
-	for (j = 0; j < dev_rrbs[i]; j++) {
-	    cur_rrb = i | 0x8;
-	    cur_rrb = cur_rrb << (rrb_shift * 4);
-	    rrb_shift--;
-	    rrb_setting = rrb_setting | cur_rrb;
-	}
-    }
-
-    if (pcibr_soft)
-	s = pcibr_lock(pcibr_soft);
-
-    bridge->b_rrb_map[even_odd].reg = rrb_setting;
-
-    if (pcibr_soft) {
-
-	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
-
-	/* since we've "FIXED" the allocations
-	 * for these slots, we probably can dispense
-	 * with tracking avail/res/valid data, but
-	 * keeping it up to date helps debugging.
-	 */
-
-	pcibr_soft->bs_rrb_avail[even_odd] =
-	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
-
-	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
-	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
-
-	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
-	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
-	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
-	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
-
-	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
-	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
-	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
-	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
-
-	pcibr_unlock(pcibr_soft, s);
-    }
-    return 0;
-}
-
-/*
- *    pcibr_rrb_flush: chase down all the RRBs assigned
- *      to the specified connection point, and flush
- *      them.
- */
-void
-pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned long           s;
-    reg_p                   rrbp;
-    unsigned                rrbm;
-    int                     i;
-    int                     rrbn;
-    unsigned                sval;
-    unsigned                mask;
-
-    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
-    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
-    rrbn = pciio_slot & 1;
-    rrbp = &bridge->b_rrb_map[rrbn].reg;
-
-    s = pcibr_lock(pcibr_soft);
-    rrbm = *rrbp;
-    for (i = 0; i < 8; ++i) {
-	if ((rrbm & mask) == sval)
-	    do_pcibr_rrb_flush(bridge, rrbn);
-	rrbm >>= 4;
-	rrbn += 2;
-    }
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/* =====================================================================
- *    Device(x) register management
- */
-
-/* pcibr_try_set_device: attempt to modify Device(x)
- * for the specified slot on the specified bridge
- * as requested in flags, limited to the specified
- * bits. Returns which BRIDGE bits were in conflict,
- * or ZERO if everything went OK.
- *
- * Caller MUST hold pcibr_lock when calling this function.
- */
-LOCAL int
-pcibr_try_set_device(pcibr_soft_t pcibr_soft,
-		     pciio_slot_t slot,
-		     unsigned flags,
-		     bridgereg_t mask)
-{
-    bridge_t               *bridge;
-    pcibr_soft_slot_t       slotp;
-    bridgereg_t             old;
-    bridgereg_t             new;
-    bridgereg_t             chg;
-    bridgereg_t             bad;
-    bridgereg_t             badpmu;
-    bridgereg_t             badd32;
-    bridgereg_t             badd64;
-    bridgereg_t             fix;
-    unsigned long           s;
-    bridgereg_t             xmask;
-
-    xmask = mask;
-    if (pcibr_soft->bs_xbridge) {
-    	if (mask == BRIDGE_DEV_PMU_BITS)
-		xmask = XBRIDGE_DEV_PMU_BITS;
-	if (mask == BRIDGE_DEV_D64_BITS)
-		xmask = XBRIDGE_DEV_D64_BITS;
-    }
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    s = pcibr_lock(pcibr_soft);
-
-    bridge = pcibr_soft->bs_base;
-
-    old = slotp->bss_device;
-
-    /* figure out what the desired
-     * Device(x) bits are based on
-     * the flags specified.
-     */
-
-    new = old;
-
-    /* Currently, we inherit anything that
-     * the new caller has not specified in
-     * one way or another, unless we take
-     * action here to not inherit.
-     *
-     * This is needed for the "swap" stuff,
-     * since it could have been set via
-     * pcibr_endian_set -- altho note that
-     * any explicit PCIBR_BYTE_STREAM or
-     * PCIBR_WORD_VALUES will freely override
-     * the effect of that call (and vice
-     * versa, no protection either way).
-     *
-     * I want to get rid of pcibr_endian_set
-     * in favor of tracking DMA endianness
-     * using the flags specified when DMA
-     * channels are created.
-     */
-
-#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
-#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
-
-    /* Do not use Barrier, Write Gather,
-     * or Prefetch unless asked.
-     * Leave everything else as it
-     * was from the last time.
-     */
-    new = new
-	& ~BRIDGE_DEV_BARRIER
-	& ~BRIDGE_DEV_WRGA_BITS
-	& ~BRIDGE_DEV_PREF
-	;
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {
-	new = (new
-            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
-            | BRIDGE_DEV_PREF;          /* prefetch on */
-
-    }
-    if (flags & PCIIO_DMA_CMD) {
-        new = ((new
-            & ~BRIDGE_DEV_PREF)         /* prefetch off */
-            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
-            | BRIDGE_DEV_BARRIER;       /* barrier on */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_WRITE_GATHER)
-	new |= BRIDGE_DEV_WRGA_BITS;
-    if (flags & PCIIO_NOWRITE_GATHER)
-	new &= ~BRIDGE_DEV_WRGA_BITS;
-
-    if (flags & PCIIO_PREFETCH)
-	new |= BRIDGE_DEV_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	new &= ~BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_WRITE_GATHER)
-	new |= BRIDGE_DEV_WRGA_BITS;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	new &= ~BRIDGE_DEV_WRGA_BITS;
-
-    if (flags & PCIIO_BYTE_STREAM)
-	new |= (pcibr_soft->bs_xbridge) ? 
-			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
-    if (flags & PCIIO_WORD_VALUES)
-	new &= (pcibr_soft->bs_xbridge) ? 
-			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_PREFETCH)
-	new |= BRIDGE_DEV_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	new &= ~BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	new |= BRIDGE_DEV_PRECISE;
-    if (flags & PCIBR_NOPRECISE)
-	new &= ~BRIDGE_DEV_PRECISE;
-
-    if (flags & PCIBR_BARRIER)
-	new |= BRIDGE_DEV_BARRIER;
-    if (flags & PCIBR_NOBARRIER)
-	new &= ~BRIDGE_DEV_BARRIER;
-
-    if (flags & PCIBR_64BIT)
-	new |= BRIDGE_DEV_DEV_SIZE;
-    if (flags & PCIBR_NO64BIT)
-	new &= ~BRIDGE_DEV_DEV_SIZE;
-
-    chg = old ^ new;				/* what are we changing, */
-    chg &= xmask;				/* of the interesting bits */
-
-    if (chg) {
-
-	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
-	if (pcibr_soft->bs_xbridge) {
-		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
-	} else {
-		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
-		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
-	}
-	bad = badpmu | badd32 | badd64;
-
-	if (bad) {
-
-	    /* some conflicts can be resolved by
-	     * forcing the bit on. this may cause
-	     * some performance degredation in
-	     * the stream(s) that want the bit off,
-	     * but the alternative is not allowing
-	     * the new stream at all.
-	     */
-            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
-                             BRIDGE_DEV_BARRIER)) ){
-		bad &= ~fix;
-		/* don't change these bits if
-		 * they are already set in "old"
-		 */
-		chg &= ~(fix & old);
-	    }
-	    /* some conflicts can be resolved by
-	     * forcing the bit off. this may cause
-	     * some performance degredation in
-	     * the stream(s) that want the bit on,
-	     * but the alternative is not allowing
-	     * the new stream at all.
-	     */
-	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
-			     BRIDGE_DEV_PREF)) ) {
-		bad &= ~fix;
-		/* don't change these bits if
-		 * we wanted to turn them on.
-		 */
-		chg &= ~(fix & new);
-	    }
-	    /* conflicts in other bits mean
-	     * we can not establish this DMA
-	     * channel while the other(s) are
-	     * still present.
-	     */
-	    if (bad) {
-		pcibr_unlock(pcibr_soft, s);
-#if (DEBUG && PCIBR_DEV_DEBUG)
-		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
-#endif
-		return bad;
-	    }
-	}
-    }
-    if (mask == BRIDGE_DEV_PMU_BITS)
-	slotp->bss_pmu_uctr++;
-    if (mask == BRIDGE_DEV_D32_BITS)
-	slotp->bss_d32_uctr++;
-    if (mask == BRIDGE_DEV_D64_BITS)
-	slotp->bss_d64_uctr++;
-
-    /* the value we want to write is the
-     * original value, with the bits for
-     * our selected changes flipped, and
-     * with any disabled features turned off.
-     */
-    new = old ^ chg;			/* only change what we want to change */
-
-    if (slotp->bss_device == new) {
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-    bridge->b_device[slot].reg = new;
-    slotp->bss_device = new;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-#if DEBUG && PCIBR_DEV_DEBUG
-    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
-#endif
-
-    return 0;
-}
-
-void
-pcibr_release_device(pcibr_soft_t pcibr_soft,
-		     pciio_slot_t slot,
-		     bridgereg_t mask)
-{
-    pcibr_soft_slot_t       slotp;
-    unsigned long           s;
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    s = pcibr_lock(pcibr_soft);
-
-    if (mask == BRIDGE_DEV_PMU_BITS)
-	slotp->bss_pmu_uctr--;
-    if (mask == BRIDGE_DEV_D32_BITS)
-	slotp->bss_d32_uctr--;
-    if (mask == BRIDGE_DEV_D64_BITS)
-	slotp->bss_d64_uctr--;
-
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/*
- * flush write gather buffer for slot
- */
-LOCAL void
-pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
-              pciio_slot_t slot)
-{
-    bridge_t               *bridge;
-    unsigned long          s;
-    volatile uint32_t     wrf;
-    s = pcibr_lock(pcibr_soft);
-    bridge = pcibr_soft->bs_base;
-    wrf = bridge->b_wr_req_buf[slot].reg;
-    pcibr_unlock(pcibr_soft, s);
-}
-
-/* =====================================================================
- *    Bridge (pcibr) "Device Driver" entry points
- */
-
-/*
- * pcibr_probe_slot: read a config space word
- * while trapping any errors; reutrn zero if
- * all went OK, or nonzero if there was an error.
- * The value read, if any, is passed back
- * through the valp parameter.
- */
-LOCAL int
-pcibr_probe_slot(bridge_t *bridge,
-		 cfg_p cfg,
-		 unsigned *valp)
-{
-    int                     rv;
-    bridgereg_t             old_enable, new_enable;
-    int badaddr_val(volatile void *, int, volatile void *);
-
-
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-
-    bridge->b_int_enable = new_enable;
-
-	/*
-	 * The xbridge doesn't clear b_err_int_view unless
-	 * multi-err is cleared...
-	 */
-	if (is_xbridge(bridge))
-	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
-		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
-	    }
-
-    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
-	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
-	(void) bridge->b_wid_tflush;	/* flushbus */
-    }
-    rv = badaddr_val((void *) cfg, 4, valp);
-
-	/*
-	 * The xbridge doesn't set master timeout in b_int_status
-	 * here.  Fortunately it's in error_interrupt_view.
-	 */
-	if (is_xbridge(bridge))
-	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
-		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
-		rv = 1;		/* unoccupied slot */
-	    }
-
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    return rv;
-}
-
-/*
- *    pcibr_init: called once during system startup or
- *      when a loadable driver is loaded.
- *
- *      The driver_register function should normally
- *      be in _reg, not _init.  But the pcibr driver is
- *      required by devinit before the _reg routines
- *      are called, so this is an exception.
- */
-void
-pcibr_init(void)
-{
-#if DEBUG && ATTACH_DEBUG
-    printk("pcibr_init\n");
-#endif
-
-    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
-			    XBRIDGE_WIDGET_MFGR_NUM,
-			    "pcibr_",
-			    0);
-    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
-			    BRIDGE_WIDGET_MFGR_NUM,
-			    "pcibr_",
-			    0);
-}
-
-/*
- * open/close mmap/munmap interface would be used by processes
- * that plan to map the PCI bridge, and muck around with the
- * registers. This is dangerous to do, and will be allowed
- * to a select brand of programs. Typically these are
- * diagnostics programs, or some user level commands we may
- * write to do some weird things.
- * To start with expect them to have root priveleges.
- * We will ask for more later.
- */
-/* ARGSUSED */
-int
-pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
-{
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
-{
-    return 0;
-}
-
-/*ARGSUSED */
-int
-pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
-{
-    int                     error;
-    devfs_handle_t            vhdl = dev_to_vhdl(dev);
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    ASSERT(pcibr_soft);
-    len = ctob(btoc(len));		/* Make len page aligned */
-    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
-
-    /*
-     * If the offset being mapped corresponds to the flash prom
-     * base, and if the mapping succeeds, and if the user
-     * has requested the protections to be WRITE, enable the
-     * flash prom to be written.
-     *
-     * XXX- deprecate this in favor of using the
-     * real flash driver ...
-     */
-    if (!error &&
-	((off == BRIDGE_EXTERNAL_FLASH) ||
-	 (len > BRIDGE_EXTERNAL_FLASH))) {
-	int                     s;
-
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	s = splhi();
-	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(s);
-    }
-    return error;
-}
-
-/*ARGSUSED */
-int
-pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
-{
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    /*
-     * If flashprom write was enabled, disable it, as
-     * this is the last unmap.
-     */
-    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
-	int                     s;
-
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	s = splhi();
-	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(s);
-    }
-    return 0;
-}
-
-/* This is special case code used by grio. There are plans to make
- * this a bit more general in the future, but till then this should
- * be sufficient.
- */
-pciio_slot_t
-pcibr_device_slot_get(devfs_handle_t dev_vhdl)
-{
-    char                    devname[MAXDEVNAME];
-    devfs_handle_t            tdev;
-    pciio_info_t            pciio_info;
-    pciio_slot_t            slot = PCIIO_SLOT_NONE;
-
-    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
-
-    /* run back along the canonical path
-     * until we find a PCI connection point.
-     */
-    tdev = hwgraph_connectpt_get(dev_vhdl);
-    while (tdev != GRAPH_VERTEX_NONE) {
-	pciio_info = pciio_info_chk(tdev);
-	if (pciio_info) {
-	    slot = pciio_info_slot_get(pciio_info);
-	    break;
-	}
-	hwgraph_vertex_unref(tdev);
-	tdev = hwgraph_connectpt_get(tdev);
-    }
-    hwgraph_vertex_unref(tdev);
-
-    return slot;
-}
-
-/*==========================================================================
- *	BRIDGE PCI SLOT RELATED IOCTLs
- */
-char *pci_space_name[] = {"NONE", 
-			  "ROM",
-			  "IO",
-			  "",
-			  "MEM",
-			  "MEM32",
-			  "MEM64",
-			  "CFG",
-			  "WIN0",
-			  "WIN1",
-			  "WIN2",
-			  "WIN3",
-			  "WIN4",
-			  "WIN5",
-			  "",
-			  "BAD"};
-
-
-#ifdef LATER
-
-void
-pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
-                            int func,
-                            pcibr_slot_func_info_resp_t funcp)
-{
-    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
-    int                          win;
-
-    funcp->resp_f_status = 0;
-
-    if (!pcibr_info) {
-        return;
-    }
-
-    funcp->resp_f_status |= FUNC_IS_VALID;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
-#else
-    sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex);
-#endif
-
-    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
-        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
-    }
-
-    funcp->resp_f_bus = pcibr_info->f_bus;
-    funcp->resp_f_slot = pcibr_info->f_slot;
-    funcp->resp_f_func = pcibr_info->f_func;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
-#else
-    sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master);
-#endif
-    funcp->resp_f_pops = pcibr_info->f_pops;
-    funcp->resp_f_efunc = pcibr_info->f_efunc;
-    funcp->resp_f_einfo = pcibr_info->f_einfo;
-
-    funcp->resp_f_vendor = pcibr_info->f_vendor;
-    funcp->resp_f_device = pcibr_info->f_device;
-
-    for(win = 0 ; win < 6 ; win++) {
-        funcp->resp_f_window[win].resp_w_base =
-                                  pcibr_info->f_window[win].w_base;
-        funcp->resp_f_window[win].resp_w_size =
-                                  pcibr_info->f_window[win].w_size;
-        sprintf(funcp->resp_f_window[win].resp_w_space,
-                "%s",
-                pci_space_name[pcibr_info->f_window[win].w_space]);
-    }
-
-    funcp->resp_f_rbase = pcibr_info->f_rbase;
-    funcp->resp_f_rsize = pcibr_info->f_rsize;
-
-    for (win = 0 ; win < 4; win++) {
-        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
-    }
-
-    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
-
-}
-
-int
-pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
-                       pciio_slot_t             slot,
-                       pcibr_slot_info_resp_t   respp)
-{
-    pcibr_soft_slot_t            pss;
-    int                          func;
-    bridge_t                    *bridge = pcibr_soft->bs_base;
-    reg_p                        b_respp;
-    pcibr_slot_info_resp_t       slotp;
-    pcibr_slot_func_info_resp_t  funcp;
-
-    slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP);
-    if (slotp == NULL) {
-        return(ENOMEM);
-    }
-
-    pss = &pcibr_soft->bs_slot[slot];
-    
-    printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot);
-
-    slotp->resp_has_host = pss->has_host;
-    slotp->resp_host_slot = pss->host_slot;
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
-#else
-    sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn);
-#endif
-    slotp->resp_slot_status = pss->slot_status;
-    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
-
-    if (is_sys_critical_vertex(pss->slot_conn)) {
-        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
-    }
-
-    slotp->resp_bss_ninfo = pss->bss_ninfo;
-
-    for (func = 0; func < pss->bss_ninfo; func++) {
-        funcp = &(slotp->resp_func[func]);
-        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
-    }
-
-    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
-            pci_space_name[pss->bss_devio.bssd_space]);
-    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
-    slotp->resp_bss_device = pss->bss_device;
-
-    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
-    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
-    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
-
-    slotp->resp_bss_d64_base = pss->bss_d64_base;
-    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
-    slotp->resp_bss_d32_base = pss->bss_d32_base;
-    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
-
-    slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active);
-
-    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
-    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
-
-    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
-    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
-                                                      PCIBR_RRB_SLOT_VIRTUAL];
-    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
-
-    if (slot & 1) {
-        b_respp = &bridge->b_odd_resp;
-    } else {
-        b_respp = &bridge->b_even_resp;
-    }
-
-    slotp->resp_b_resp = *b_respp;
-
-    slotp->resp_b_int_device = bridge->b_int_device;
-    slotp->resp_b_int_enable = bridge->b_int_enable;
-    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
-
-    if (COPYOUT(slotp, respp, sizeof(*respp))) {
-        return(EFAULT);
-    }
-
-    kmem_free(slotp, sizeof(*slotp));
-
-    return(0);
-}
-
-/*
- * pcibr_slot_query
- *	Return information about the PCI slot maintained by the infrastructure.
- *	Information is requested in the request structure.
- *
- *      Information returned in the response structure:
- *		Slot hwgraph name
- *		Vendor/Device info
- *		Base register info
- *		Interrupt mapping from device pins to the bridge pins
- *		Devio register
- *		Software RRB info
- *		RRB register info
- *		Host/Gues info
- *		PCI Bus #,slot #, function #
- *		Slot provider hwgraph name
- *		Provider Functions
- *		Error handler
- *		DMA mapping usage counters
- *		DMA direct translation info
- *		External SSRAM workaround info
- */
-int
-pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    pciio_slot_t            slot = reqp->req_slot;
-    pciio_slot_t            tmp_slot;
-    pcibr_slot_info_resp_t  respp = (pcibr_slot_info_resp_t) reqp->req_respp;
-    int                     size = reqp->req_size;
-    int                     error;
-
-    /* Make sure that we are dealing with a bridge device vertex */
-    if (!pcibr_soft) {
-        return(EINVAL);
-    }
-
-    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
-    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
-        return(EINVAL);
-    }
-
-#ifdef LATER
-    /* Do not allow a query of a slot in a shoehorn */
-    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
-       return(EPERM);
-    }
-#endif
-
-    /* Return information for the requested PCI slot */
-    if (slot != PCIIO_SLOT_NONE) {
-        if (size < sizeof(*respp)) {
-            return(EINVAL);
-        }
-
-        /* Acquire read access to the slot */
-        mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO);
-
-        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
-
-        /* Release the slot lock */
-        mrunlock(pcibr_soft->bs_slot[slot].slot_lock);
-
-        return(error);
-    }
-
-    /* Return information for all the slots */
-    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
-
-        if (size < sizeof(*respp)) {
-            return(EINVAL);
-        }
-
-        /* Acquire read access to the slot */
-        mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO);
-
-        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
-
-        /* Release the slot lock */
-        mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock);
-
-        if (error) {
-            return(error);
-        }
-
-        ++respp;
-        size -= sizeof(*respp);
-    }
-
-    return(error);
-}
-#endif	/* LATER */
-
-
-/*ARGSUSED */
-int
-pcibr_ioctl(devfs_handle_t dev,
-	    int cmd,
-	    void *arg,
-	    int flag,
-	    struct cred *cr,
-	    int *rvalp)
-{
-    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
-#ifdef LATER
-    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-#endif
-    int                     error = 0;
-
-    hwgraph_vertex_unref(pcibr_vhdl);
-
-    switch (cmd) {
-#ifdef LATER
-    case GIOCSETBW:
-	{
-	    grio_ioctl_info_t       info;
-	    pciio_slot_t            slot = 0;
-
-	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
-		error = EFAULT;
-		break;
-	    }
-#ifdef GRIO_DEBUG
-	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
-		    info.prev_vhdl, info.reqbw);
-#endif				/* GRIO_DEBUG */
-
-	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
-		PCIIO_SLOT_NONE) {
-		error = EIO;
-		break;
-	    }
-	    if (info.reqbw)
-		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
-	    break;
-	}
-
-    case GIOCRELEASEBW:
-	{
-	    grio_ioctl_info_t       info;
-	    pciio_slot_t            slot = 0;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
-		error = EFAULT;
-		break;
-	    }
-#ifdef GRIO_DEBUG
-	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
-		    info.prev_vhdl, info.reqbw);
-#endif				/* GRIO_DEBUG */
-
-	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
-		PCIIO_SLOT_NONE) {
-		error = EIO;
-		break;
-	    }
-	    if (info.reqbw)
-		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
-	    break;
-	}
-
-    case PCIBR_SLOT_POWERUP:
-	{
-	    pciio_slot_t	slot;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-	    slot = (pciio_slot_t)(uint64_t)arg;
-	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
-	    break;
-	}
-    case PCIBR_SLOT_SHUTDOWN:
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-	    slot = (pciio_slot_t)(uint64_t)arg;
-	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
-	    break;
-	}
-    case PCIBR_SLOT_QUERY:
-	{
-	    struct pcibr_slot_info_req_s        req;
-
-	    if (!cap_able(CAP_DEVICE_MGT)) {
-		error = EPERM;
-		break;
-	    }
-
-            if (COPYIN(arg, &req, sizeof(req))) {
-                error = EFAULT;
-                break;
-            }
-
-            error = pcibr_slot_query(pcibr_vhdl, &req);
-	    break;
-	}
-#endif	/* LATER */
-    default:
-	break;
-
-    }
-
-    return error;
-}
-
-void
-pcibr_freeblock_sub(iopaddr_t *free_basep,
-		    iopaddr_t *free_lastp,
-		    iopaddr_t base,
-		    size_t size)
-{
-    iopaddr_t               free_base = *free_basep;
-    iopaddr_t               free_last = *free_lastp;
-    iopaddr_t               last = base + size - 1;
-
-    if ((last < free_base) || (base > free_last));	/* free block outside arena */
-
-    else if ((base <= free_base) && (last >= free_last))
-	/* free block contains entire arena */
-	*free_basep = *free_lastp = 0;
-
-    else if (base <= free_base)
-	/* free block is head of arena */
-	*free_basep = last + 1;
-
-    else if (last >= free_last)
-	/* free block is tail of arena */
-	*free_lastp = base - 1;
-
-    /*
-     * We are left with two regions: the free area
-     * in the arena "below" the block, and the free
-     * area in the arena "above" the block. Keep
-     * the one that is bigger.
-     */
-
-    else if ((base - free_base) > (free_last - last))
-	*free_lastp = base - 1;		/* keep lower chunk */
-    else
-	*free_basep = last + 1;		/* keep upper chunk */
-}
-
-/* Convert from ssram_bits in control register to number of SSRAM entries */
-#define ATE_NUM_ENTRIES(n) _ate_info[n]
-
-/* Possible choices for number of ATE entries in Bridge's SSRAM */
-LOCAL int               _ate_info[] =
-{
-    0,					/* 0 entries */
-    8 * 1024,				/* 8K entries */
-    16 * 1024,				/* 16K entries */
-    64 * 1024				/* 64K entries */
-};
-
-#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
-#define ATE_PROBE_VALUE 0x0123456789abcdefULL
-
-/*
- * Determine the size of this bridge's external mapping SSRAM, and set
- * the control register appropriately to reflect this size, and initialize
- * the external SSRAM.
- */
-LOCAL int
-pcibr_init_ext_ate_ram(bridge_t *bridge)
-{
-    int                     largest_working_size = 0;
-    int                     num_entries, entry;
-    int                     i, j;
-    bridgereg_t             old_enable, new_enable;
-    int                     s;
-
-    /* Probe SSRAM to determine its size. */
-    old_enable = bridge->b_int_enable;
-    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
-    bridge->b_int_enable = new_enable;
-
-    for (i = 1; i < ATE_NUM_SIZES; i++) {
-	/* Try writing a value */
-	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
-
-	/* Guard against wrap */
-	for (j = 1; j < i; j++)
-	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
-
-	/* See if value was written */
-	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
-	    largest_working_size = i;
-    }
-    bridge->b_int_enable = old_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    /*
-     * ensure that we write and read without any interruption.
-     * The read following the write is required for the Bridge war
-     */
-
-    s = splhi();
-    bridge->b_wid_control = (bridge->b_wid_control
-	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
-	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
-    bridge->b_wid_control;		/* inval addr bug war */
-    splx(s);
-
-    num_entries = ATE_NUM_ENTRIES(largest_working_size);
-
-#if PCIBR_ATE_DEBUG
-    if (num_entries)
-	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
-    else
-	printk("bridge at 0x%x: no externa9422l ATE RAM found\n", bridge);
-#endif
-
-    /* Initialize external mapping entries */
-    for (entry = 0; entry < num_entries; entry++)
-	bridge->b_ext_ate_ram[entry] = 0;
-
-    return (num_entries);
-}
-
-/*
- * Allocate "count" contiguous Bridge Address Translation Entries
- * on the specified bridge to be used for PCI to XTALK mappings.
- * Indices in rm map range from 1..num_entries.  Indicies returned
- * to caller range from 0..num_entries-1.
- *
- * Return the start index on success, -1 on failure.
- */
-LOCAL int
-pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
-{
-    int                     index = 0;
-
-    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
-/* printk("Colin: pcibr_ate_alloc - index %d count %d \n", index, count); */
-
-    if (!index && pcibr_soft->bs_ext_ate_map)
-	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
-
-    /* rmalloc manages resources in the 1..n
-     * range, with 0 being failure.
-     * pcibr_ate_alloc manages resources
-     * in the 0..n-1 range, with -1 being failure.
-     */
-    return index - 1;
-}
-
-LOCAL void
-pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
-/* Who says there's no such thing as a free meal? :-) */
-{
-    /* note the "+1" since rmalloc handles 1..n but
-     * we start counting ATEs at zero.
-     */
-/* printk("Colin: pcibr_ate_free - index %d count %d\n", index, count); */
-
-    rmfree((index < pcibr_soft->bs_int_ate_size)
-	   ? pcibr_soft->bs_int_ate_map
-	   : pcibr_soft->bs_ext_ate_map,
-	   count, index + 1);
-}
-
-LOCAL pcibr_info_t
-pcibr_info_get(devfs_handle_t vhdl)
-{
-    return (pcibr_info_t) pciio_info_get(vhdl);
-}
-
-pcibr_info_t
-pcibr_device_info_new(
-			 pcibr_soft_t pcibr_soft,
-			 pciio_slot_t slot,
-			 pciio_function_t rfunc,
-			 pciio_vendor_id_t vendor,
-			 pciio_device_id_t device)
-{
-    pcibr_info_t            pcibr_info;
-    pciio_function_t        func;
-    int                     ibit;
-
-    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
-
-    NEW(pcibr_info);
-    pciio_device_info_new(&pcibr_info->f_c,
-			  pcibr_soft->bs_vhdl,
-			  slot, rfunc,
-			  vendor, device);
-
-    if (slot != PCIIO_SLOT_NONE) {
-
-	/*
-	 * Currently favored mapping from PCI
-	 * slot number and INTA/B/C/D to Bridge
-	 * PCI Interrupt Bit Number:
-	 *
-	 *     SLOT     A B C D
-	 *      0       0 4 0 4
-	 *      1       1 5 1 5
-	 *      2       2 6 2 6
-	 *      3       3 7 3 7
-	 *      4       4 0 4 0
-	 *      5       5 1 5 1
-	 *      6       6 2 6 2
-	 *      7       7 3 7 3
-	 *
-	 * XXX- allow pcibr_hints to override default
-	 * XXX- allow ADMIN to override pcibr_hints
-	 */
-	for (ibit = 0; ibit < 4; ++ibit)
-	    pcibr_info->f_ibit[ibit] =
-		(slot + 4 * ibit) & 7;
-
-	/*
-	 * Record the info in the sparse func info space.
-	 */
-	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
-	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
-    }
-    return pcibr_info;
-}
-
-void
-pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    pcibr_info_t	pcibr_info;
-    pciio_function_t	func;
-    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
-    int			nfunc = slotp->bss_ninfo;
-
-
-    for (func = 0; func < nfunc; func++) {
-	pcibr_info = slotp->bss_infos[func];
-
-	if (!pcibr_info) 
-	    continue;
-
-	slotp->bss_infos[func] = 0;
-	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
-	pciio_device_info_free(&pcibr_info->f_c);
-	DEL(pcibr_info);
-    }
-
-    /* Clear the DEVIO(x) for this slot */
-    slotp->bss_devio.bssd_space = PCIIO_SPACE_NONE;
-    slotp->bss_devio.bssd_base = PCIBR_D32_BASE_UNSET;
-    slotp->bss_device  = 0;
-
-    
-    /* Reset the mapping usage counters */
-    slotp->bss_pmu_uctr = 0;
-    slotp->bss_d32_uctr = 0;
-    slotp->bss_d64_uctr = 0;
-
-    /* Clear the Direct translation info */
-    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
-    slotp->bss_d64_flags = 0;
-    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
-    slotp->bss_d32_flags = 0;
-
-    /* Clear out shadow info necessary for the external SSRAM workaround */
-    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
-    slotp->bss_cmd_pointer = 0;
-    slotp->bss_cmd_shadow = 0;
-
-}
-
-/* 
- * PCI_ADDR_SPACE_LIMITS_LOAD
- *	Gets the current values of 
- *		pci io base, 
- *		pci io last,
- *		pci low memory base,
- *		pci low memory last,
- *		pci high memory base,
- * 		pci high memory last
- */
-#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
-    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
-    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
-    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
-    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
-    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
-    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
-/*
- * PCI_ADDR_SPACE_LIMITS_STORE
- *	Sets the current values of
- *		pci io base, 
- *		pci io last,
- *		pci low memory base,
- *		pci low memory last,
- *		pci high memory base,
- * 		pci high memory last
- */
-#define PCI_ADDR_SPACE_LIMITS_STORE()			\
-    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
-    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
-    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
-    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
-    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
-    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
-
-#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
-    printf("+++++++++++++++++++++++\n"			\
-	   "IO base 0x%x last 0x%x\n"			\
-	   "SWIN base 0x%x last 0x%x\n"			\
-	   "MEM base 0x%x last 0x%x\n"			\
-	   "+++++++++++++++++++++++\n",			\
-	   pcibr_soft->bs_spinfo.pci_io_base,		\
-	   pcibr_soft->bs_spinfo.pci_io_last,		\
-	   pcibr_soft->bs_spinfo.pci_swin_base,		\
-	   pcibr_soft->bs_spinfo.pci_swin_last,		\
-	   pcibr_soft->bs_spinfo.pci_mem_base,		\
-	   pcibr_soft->bs_spinfo.pci_mem_last);
-
-/*
- * pcibr_slot_info_init
- *	Probe for this slot and see if it is populated.
- *	If it is populated initialize the generic PCI infrastructural
- * 	information associated with this particular PCI device.
- */
-int
-pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
-		     pciio_slot_t 	slot)
-{
-    pcibr_soft_t	    pcibr_soft;
-    pcibr_info_h	    pcibr_infoh;
-    pcibr_info_t	    pcibr_info;
-    bridge_t		   *bridge;
-    cfg_p                   cfgw;
-    unsigned                idword;
-    unsigned                pfail;
-    unsigned                idwords[8];
-    pciio_vendor_id_t       vendor;
-    pciio_device_id_t       device;
-    unsigned                htype;
-#if !defined(CONFIG_IA64_SGI_SN1)
-    int			    nbars;
-#endif
-    cfg_p                   wptr;
-    int                     win;
-    pciio_space_t           space;
-    iopaddr_t		    pci_io_fb,	pci_io_fl;
-    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
-    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
-    int			    nfunc;
-    pciio_function_t	    rfunc;
-    int			    func;
-    devfs_handle_t	    conn_vhdl;
-    pcibr_soft_slot_t	    slotp;
-    
-    /* Get the basic software information required to proceed */
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (!pcibr_soft)
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-    if (!PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
-     * is done by the host slot then we are done.
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	return(0);    
-    }
-
-    /* Check for a slot with any system critical functions */
-    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
-        return(EPERM);
-
-    /* Load the current values of allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_LOAD();
-    
-    /* Try to read the device-id/vendor-id from the config space */
-    cfgw = bridge->b_type0_cfg_dev[slot].l;
-
-    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
-	return(ENODEV);
-
-    slotp = &pcibr_soft->bs_slot[slot];
-    slotp->slot_status |= SLOT_POWER_UP;
-
-    vendor = 0xFFFF & idword;
-    /* If the vendor id is not valid then the slot is not populated
-     * and we are done.
-     */
-    if (vendor == 0xFFFF) 
-	return(ENODEV);			
-    
-    device = 0xFFFF & (idword >> 16);
-    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
-
-    nfunc = 1;
-    rfunc = PCIIO_FUNC_NONE;
-    pfail = 0;
-
-    /* NOTE: if a card claims to be multifunction
-     * but only responds to config space 0, treat
-     * it as a unifunction card.
-     */
-
-    if (htype & 0x80) {		/* MULTIFUNCTION */
-	for (func = 1; func < 8; ++func) {
-	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
-		pfail |= 1 << func;
-		continue;
-	    }
-	    vendor = 0xFFFF & idwords[func];
-	    if (vendor == 0xFFFF) {
-		pfail |= 1 << func;
-		continue;
-	    }
-	    nfunc = func + 1;
-	    rfunc = 0;
-	}
-	cfgw = bridge->b_type0_cfg_dev[slot].l;
-    }
-    NEWA(pcibr_infoh, nfunc);
-    
-    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
-    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
-
-    for (func = 0; func < nfunc; ++func) {
-	unsigned                cmd_reg;
-	
-	if (func) {
-	    if (pfail & (1 << func))
-		continue;
-	    
-	    idword = idwords[func];
-	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	    
-	    device = 0xFFFF & (idword >> 16);
-	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
-	    rfunc = func;
-	}
-	htype &= 0x7f;
-	if (htype != 0x00) {
-	    PRINT_WARNING("%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
-		    pcibr_soft->bs_name, slot, func, htype);
-#if defined(CONFIG_IA64_SGI_SN1)
-	    continue;
-#else
-	    nbars = 2;
-	} else {
-	    nbars = PCI_CFG_BASE_ADDRS;
-#endif
-	}
-#if DEBUG && ATTACH_DEBUG
-	PRINT_NOTICE( 
-		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
-		pcibr_soft->bs_name, slot, func, vendor, device);
-#endif	
-
-	pcibr_info = pcibr_device_info_new
-	    (pcibr_soft, slot, rfunc, vendor, device);
-	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
-	if (func == 0)
-	    slotp->slot_conn = conn_vhdl;
-
-	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
-	
-	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-
-#if defined(CONFIG_IA64_SGI_SN1)
-	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win)
-#else
-	for (win = 0; win < nbars; ++win)
-#endif
-	{
-	    iopaddr_t               base, mask, code;
-	    size_t                  size;
-
-	    /*
-	     * GET THE BASE & SIZE OF THIS WINDOW:
-	     *
-	     * The low two or four bits of the BASE register
-	     * determines which address space we are in; the
-	     * rest is a base address. BASE registers
-	     * determine windows that are power-of-two sized
-	     * and naturally aligned, so we can get the size
-	     * of a window by writing all-ones to the
-	     * register, reading it back, and seeing which
-	     * bits are used for decode; the least
-	     * significant nonzero bit is also the size of
-	     * the window.
-	     *
-	     * WARNING: someone may already have allocated
-	     * some PCI space to this window, and in fact
-	     * PIO may be in process at this very moment
-	     * from another processor (or even from this
-	     * one, if we get interrupted)! So, if the BASE
-	     * already has a nonzero address, be generous
-	     * and use the LSBit of that address as the
-	     * size; this could overstate the window size.
-	     * Usually, when one card is set up, all are set
-	     * up; so, since we don't bitch about
-	     * overlapping windows, we are ok.
-	     *
-	     * UNFORTUNATELY, some cards do not clear their
-	     * BASE registers on reset. I have two heuristics
-	     * that can detect such cards: first, if the
-	     * decode enable is turned off for the space
-	     * that the window uses, we can disregard the
-	     * initial value. second, if the address is
-	     * outside the range that we use, we can disregard
-	     * it as well.
-	     *
-	     * This is looking very PCI generic. Except for
-	     * knowing how many slots and where their config
-	     * spaces are, this window loop and the next one
-	     * could probably be shared with other PCI host
-	     * adapters. It would be interesting to see if
-	     * this could be pushed up into pciio, when we
-	     * start supporting more PCI providers.
-	     */
-#ifdef LITTLE_ENDIAN
-	    base = wptr[((win*4)^4)/4];
-#else
-	    base = wptr[win];
-#endif
-
-	    if (base & PCI_BA_IO_SPACE) {
-		/* BASE is in I/O space. */
-		space = PCIIO_SPACE_IO;
-		mask = -4;
-		code = base & 3;
-		base = base & mask;
-		if (base == 0) {
-		    ;		/* not assigned */
-		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
-		    base = 0;	/* decode not enabled */
-		}
-	    } else {
-		/* BASE is in MEM space. */
-		space = PCIIO_SPACE_MEM;
-		mask = -16;
-		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
-		base = base & mask;
-		if (base == 0) {
-		    ;		/* not assigned */
-		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
-		    base = 0;	/* decode not enabled */
-		} else if (base & 0xC0000000) {
-		    base = 0;	/* outside permissable range */
-		} else if ((code == PCI_BA_MEM_64BIT) &&
-#ifdef LITTLE_ENDIAN
-			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
-#else 
-			   (wptr[win + 1] != 0)) {
-#endif /* LITTLE_ENDIAN */
-		    base = 0;	/* outside permissable range */
-		}
-	    }
-
-	    if (base != 0) {	/* estimate size */
-		size = base & -base;
-	    } else {		/* calculate size */
-#ifdef LITTLE_ENDIAN
-		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
-		size = wptr[((win*4)^4)/4];	/* get stored bits */
-#else 
-		wptr[win] = ~0;	/* turn on all bits */
-		size = wptr[win];	/* get stored bits */
-#endif /* LITTLE_ENDIAN */
-		size &= mask;	/* keep addr */
-		size &= -size;	/* keep lsbit */
-		if (size == 0)
-		    continue;
-	    }	
-
-	    pcibr_info->f_window[win].w_space = space;
-	    pcibr_info->f_window[win].w_base = base;
-	    pcibr_info->f_window[win].w_size = size;
-
-	    /*
-	     * If this window already has PCI space
-	     * allocated for it, "subtract" that space from
-	     * our running freeblocks. Don't worry about
-	     * overlaps in existing allocated windows; we
-	     * may be overstating their sizes anyway.
-	     */
-
-	    if (base && size) {
-		if (space == PCIIO_SPACE_IO) {
-		    pcibr_freeblock_sub(&pci_io_fb,
-					&pci_io_fl,
-					base, size);
-		} else {
-		    pcibr_freeblock_sub(&pci_lo_fb,
-					&pci_lo_fl,
-					base, size);
-		    pcibr_freeblock_sub(&pci_hi_fb,
-					&pci_hi_fl,
-					base, size);
-		}	
-	    }
-#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
-	    /*
-	     * IOC3 BASE_ADDR* BUG WORKAROUND
-	     *
-	     
-	     * If we write to BASE1 on the IOC3, the
-	     * data in BASE0 is replaced. The
-	     * original workaround was to remember
-	     * the value of BASE0 and restore it
-	     * when we ran off the end of the BASE
-	     * registers; however, a later
-	     * workaround was added (I think it was
-	     * rev 1.44) to avoid setting up
-	     * anything but BASE0, with the comment
-	     * that writing all ones to BASE1 set
-	     * the enable-parity-error test feature
-	     * in IOC3's SCR bit 14.
-	     *
-	     * So, unless we defer doing any PCI
-	     * space allocation until drivers
-	     * attach, and set up a way for drivers
-	     * (the IOC3 in paricular) to tell us
-	     * generically to keep our hands off
-	     * BASE registers, we gotta "know" about
-	     * the IOC3 here.
-	     *
-	     * Too bad the PCI folks didn't reserve the
-	     * all-zero value for 'no BASE here' (it is a
-	     * valid code for an uninitialized BASE in
-	     * 32-bit PCI memory space).
-	     */
-	    
-	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
-		(device == IOC3_DEVICE_ID_NUM))
-		break;
-#endif
-	    if (code == PCI_BA_MEM_64BIT) {
-		win++;		/* skip upper half */
-#ifdef LITTLE_ENDIAN
-		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
-#else 
-		wptr[win] = 0;	/* which must be zero */
-#endif /* LITTLE_ENDIAN */
-	    }
-	}				/* next win */
-    }				/* next func */
-
-    /* Store back the values for allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_STORE();
-    return(0);
-}					
-
-/*
- * pcibr_slot_info_free
- *	Remove all the PCI infrastructural information associated
- * 	with a particular PCI device.
- */
-int
-pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
-                     pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    int			nfunc;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-#if !defined(CONFIG_IA64_SGI_SN1)
-    /* Clean out all the base registers */
-    bridge = pcibr_soft->bs_base;
-    cfgw = bridge->b_type0_cfg_dev[slot].l;
-    wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-    
-    for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) 
-#ifdef LITTLE_ENDIAN
-	wptr[((win*4)^4)/4] = 0;
-#else
-	wptr[win] = 0;
-#endif  /* LITTLE_ENDIAN */
-#endif	/* !CONFIG_IA64_SGI_SN1 */
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-
-    pcibr_device_info_free(pcibr_vhdl, slot);
-
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    DELA(pcibr_infoh,nfunc);
-    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
-
-    return(0);
-}
-
-int as_debug = 0;
-/*
- * pcibr_slot_addr_space_init
- *	Reserve chunks of PCI address space as required by 
- * 	the base registers in the card.
- */
-int
-pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
-			   pciio_slot_t	slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    bridge_t		*bridge;
-    iopaddr_t		pci_io_fb, pci_io_fl;
-    iopaddr_t		pci_lo_fb, pci_lo_fl;
-    iopaddr_t		pci_hi_fb, pci_hi_fl;
-    size_t              align;
-    iopaddr_t           mask;
-    int		    	nbars;
-    int		       	nfunc;
-    int			func;
-    int			win;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /* Get the current values for the allocated PCI address spaces */
-    PCI_ADDR_SPACE_LIMITS_LOAD();
-
-    if (as_debug)
-#ifdef LATER
-    PCI_ADDR_SPACE_LIMITS_PRINT();
-#endif
-    /* allocate address space,
-     * for windows that have not been
-     * previously assigned.
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	return(0);
-    }
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    if (nfunc < 1)
-	return(EINVAL);
-
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    if (!pcibr_infoh)
-	return(EINVAL);
-
-    /*
-     * Try to make the DevIO windows not
-     * overlap by pushing the "io" and "hi"
-     * allocation areas up to the next one
-     * or two megabyte bound. This also
-     * keeps them from being zero.
-     *
-     * DO NOT do this with "pci_lo" since
-     * the entire "lo" area is only a
-     * megabyte, total ...
-     */
-    align = (slot < 2) ? 0x200000 : 0x100000;
-    mask = -align;
-    pci_io_fb = (pci_io_fb + align - 1) & mask;
-    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
-
-    for (func = 0; func < nfunc; ++func) {
-	cfg_p                   cfgw;
-	cfg_p                   wptr;
-	pciio_space_t           space;
-	iopaddr_t               base;
-	size_t                  size;
-	cfg_p                   pci_cfg_cmd_reg_p;
-	unsigned                pci_cfg_cmd_reg;
-	unsigned                pci_cfg_cmd_reg_add = 0;
-
-	pcibr_info = pcibr_infoh[func];
-
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-	
-	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
-	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
-
-#if defined(CONFIG_IA64_SGI_SN1)
-	nbars = PCI_CFG_BASE_ADDRS;
-#else
-	if ((do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1) & 0x7f) != 0)
-	    nbars = 2;
-	else
-	    nbars = PCI_CFG_BASE_ADDRS;
-#endif
-
-	for (win = 0; win < nbars; ++win) {
-
-	    space = pcibr_info->f_window[win].w_space;
-	    base = pcibr_info->f_window[win].w_base;
-	    size = pcibr_info->f_window[win].w_size;
-	    
-	    if (size < 1)
-		continue;
-
-	    if (base >= size) {
-#if DEBUG && PCI_DEBUG
-		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
-			slot, func, win, space, base, base + size - 1);
-#endif
-		continue;		/* already allocated */
-	    }
-	    align = size;		/* ie. 0x00001000 */
-	    if (align < _PAGESZ)
-		align = _PAGESZ;	/* ie. 0x00004000 */
-	    mask = -align;		/* ie. 0xFFFFC000 */
-
-	    switch (space) {
-	    case PCIIO_SPACE_IO:
-		base = (pci_io_fb + align - 1) & mask;
-		if ((base + size) > pci_io_fl) {
-		    base = 0;
-		    break;
-		}
-		pci_io_fb = base + size;
-		break;
-		
-	    case PCIIO_SPACE_MEM:
-#ifdef LITTLE_ENDIAN
-		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
-#else
-		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
-#endif  /* LITTLE_ENDIAN */
-		    PCI_BA_MEM_1MEG) {
-		    /* allocate from 20-bit PCI space */
-		    base = (pci_lo_fb + align - 1) & mask;
-		    if ((base + size) > pci_lo_fl) {
-			base = 0;
-			break;
-		    }
-		    pci_lo_fb = base + size;
-		} else {
-		    /* allocate from 32-bit or 64-bit PCI space */
-		    base = (pci_hi_fb + align - 1) & mask;
-		    if ((base + size) > pci_hi_fl) {
-			base = 0;
-			break;
-		    }
-		    pci_hi_fb = base + size;
-		}
-		break;
-		
-	    default:
-		base = 0;
-#if DEBUG && PCI_DEBUG
-		printk("pcibr: slot %d window %d had bad space code %d\n",
-			slot, win, space);
-#endif
-	    }
-	    pcibr_info->f_window[win].w_base = base;
-#ifdef LITTLE_ENDIAN
-	    wptr[((win*4)^4)/4] = base;
-#if DEBUG && PCI_DEBUG
-		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
-#endif
-#else
-	    wptr[win] = base;
-#endif  /* LITTLE_ENDIAN */
-
-#if DEBUG && PCI_DEBUG
-	    if (base >= size)
-		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
-			slot, func, win, space, base, base + size - 1);
-	    else
-		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
-			slot, func, win, size, space);
-#endif
-	}				/* next base */
-
-	/*
-	 * Allocate space for the EXPANSION ROM
-	 * NOTE: DO NOT DO THIS ON AN IOC3,
-	 * as it blows the system away.
-	 */
-	base = size = 0;
-	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
-	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
-
-	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
-#ifdef LITTLE_ENDIAN
-	    wptr[1] = 0xFFFFF000;
-	    mask = wptr[1];
-#else
-	    *wptr = 0xFFFFF000;
-	    mask = *wptr;
-#endif  /* LITTLE_ENDIAN */
-	    if (mask & 0xFFFFF000) {
-		size = mask & -mask;
-		align = size;
-		if (align < _PAGESZ)
-		    align = _PAGESZ;
-		mask = -align;
-		base = (pci_hi_fb + align - 1) & mask;
-		if ((base + size) > pci_hi_fl)
-		    base = size = 0;
-		else {
-		    pci_hi_fb = base + size;
-#ifdef LITTLE_ENDIAN
-		    wptr[1] = base;
-#else
-		    *wptr = base;
-#endif  /* LITTLE_ENDIAN */
-#if DEBUG && PCI_DEBUG
-		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
-			    pcibr_soft->bs_name, slot,
-			    base, base + size - 1);
-#endif
-		}
-	    }
-	}
-	pcibr_info->f_rbase = base;
-	pcibr_info->f_rsize = size;
-	
-	/*
-	 * if necessary, update the board's
-	 * command register to enable decoding
-	 * in the windows we added.
-	 *
-	 * There are some bits we always want to
-	 * be sure are set.
-	 */
-	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
-
-	/*
-	 * The Adaptec 1160 FC Controller WAR #767995:
-	 * The part incorrectly ignores the upper 32 bits of a 64 bit
-	 * address when decoding references to it's registers so to
-	 * keep it from responding to a bus cycle that it shouldn't
-	 * we only use I/O space to get at it's registers.  Don't
-	 * enable memory space accesses on that PCI device.
-	 */
-	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
-	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
-
-	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
-	    (pcibr_info->f_device != FCADP_DEVID))
-	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
-
-	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
-
-	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
-	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
-#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
-	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
-	    fast_back_to_back_enable = 0;
-#endif
-	pci_cfg_cmd_reg &= 0xFFFF;
-	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
-	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
-	
-    }				/* next func */
-
-    /* Now that we have allocated new chunks of PCI address spaces to this
-     * card we need to update the bookkeeping values which indicate
-     * the current PCI address space allocations.
-     */
-    PCI_ADDR_SPACE_LIMITS_STORE();
-    return(0);
-}
-
-/*
- * pcibr_slot_device_init
- * 	Setup the device register in the bridge for this PCI slot.
- */
-int
-pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
-		       pciio_slot_t slot)
-{
-    pcibr_soft_t	 pcibr_soft;
-    bridge_t		*bridge;
-    bridgereg_t		 devreg;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /*
-     * Adjustments to Device(x)
-     * and init of bss_device shadow
-     */
-    devreg = bridge->b_device[slot].reg;
-    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
-    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
-#ifdef LITTLE_ENDIAN
-    devreg |= BRIDGE_DEV_DEV_SWAP;
-#endif
-    pcibr_soft->bs_slot[slot].bss_device = devreg;
-    bridge->b_device[slot].reg = devreg;
-
-#if DEBUG && PCI_DEBUG
-	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
-#endif
-
-#if DEBUG && PCI_DEBUG
-    printk("pcibr: PCI space allocation done.\n");
-#endif
-
-    return(0);
-}
-
-/*
- * pcibr_slot_guest_info_init
- *	Setup the host/guest relations for a PCI slot.
- */
-int
-pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
-			   pciio_slot_t	slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    pcibr_soft_slot_t	slotp;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    slotp = &pcibr_soft->bs_slot[slot];
-
-    /* create info and verticies for guest slots;
-     * for compatibilitiy macros, create info
-     * for even unpopulated slots (but do not
-     * build verticies for them).
-     */
-    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
-	NEWA(pcibr_infoh, 1);
-	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
-	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
-
-	pcibr_info = pcibr_device_info_new
-	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
-	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
-
-	if (pcibr_soft->bs_slot[slot].has_host) {
-	    slotp->slot_conn = pciio_device_info_register
-		(pcibr_vhdl, &pcibr_info->f_c);
-	}
-    }
-
-    /* generate host/guest relations
-     */
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	int  host = pcibr_soft->bs_slot[slot].host_slot;
-	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
-
-	hwgraph_edge_add(slotp->slot_conn,
-			 host_slotp->slot_conn,
-			 EDGE_LBL_HOST);
-
-	/* XXX- only gives us one guest edge per
-	 * host. If/when we have a host with more than
-	 * one guest, we will need to figure out how
-	 * the host finds all its guests, and sorts
-	 * out which one is which.
-	 */
-	hwgraph_edge_add(host_slotp->slot_conn,
-			 slotp->slot_conn,
-			 EDGE_LBL_GUEST);
-    }
-
-    return(0);
-}
-
-/*
- * pcibr_slot_initial_rrb_alloc
- *	Allocate a default number of rrbs for this slot on 
- * 	the two channels.  This is dictated by the rrb allocation
- * 	strategy routine defined per platform.
- */
-
-int
-pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
-			     pciio_slot_t slot)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    bridge_t		*bridge;
-    int                 c0, c1;
-    int			r;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    bridge = pcibr_soft->bs_base;
-
-    /* How may RRBs are on this slot?
-     */
-    c0 = do_pcibr_rrb_count_valid(bridge, slot);
-    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
-
-#if PCIBR_RRB_DEBUG
-    printk("pcibr_attach: slot %d started with %d+%d\n", slot, c0, c1);
-#endif
-
-    /* Do we really need any?
-     */
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-    pcibr_info = pcibr_infoh[0];
-    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
-	!pcibr_soft->bs_slot[slot].has_host) {
-	if (c0 > 0)
-	    do_pcibr_rrb_free(bridge, slot, c0);
-	if (c1 > 0)
-	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
-	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
-	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
-	return(ENODEV);
-    }
-
-    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
-    pcibr_soft->bs_rrb_valid[slot] = c0;
-    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
-
-    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
-    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
-
-    r = 3 - (c0 + c1);
-
-    if (r > 0) {
-	pcibr_soft->bs_rrb_res[slot] = r;
-	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
-    }
-
-#if PCIBR_RRB_DEBUG
-    printk("\t%d+%d+%d",
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-    printk("\n");
-#endif
-
-    return(0);
-}
-
-/*
- * pcibr_slot_call_device_attach
- *	This calls the associated driver attach routine for the PCI
- * 	card in this slot.
- */
-int
-pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
-			      pciio_slot_t slot,
-			      int          drv_flags)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    async_attach_t	aa = NULL;
-    int			func;
-    devfs_handle_t	xconn_vhdl,conn_vhdl;
-    int			nfunc;
-    int                 error_func;
-    int                 error_slot = 0;
-    int                 error = ENODEV;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-
-    if (pcibr_soft->bs_slot[slot].has_host) {
-        return(EPERM);
-    }
-    
-    xconn_vhdl = pcibr_soft->bs_conn;
-    aa = async_attach_get_info(xconn_vhdl);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-	pcibr_info = pcibr_infoh[func];
-	
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-
-	conn_vhdl = pcibr_info->f_vertex;
-
-	/* If the PCI device has been disabled in the prom,
-	 * do not set it up for driver attach. NOTE: usrpci
-	 * and pciba will not "see" this connection point!
-	 */
-	if (device_admin_info_get(conn_vhdl, ADMIN_LBL_DISABLED)) {
-#ifdef SUPPORT_PRINTING_V_FORMAT
-	    PRINT_WARNING("pcibr_slot_call_device_attach: %v disabled\n", 
-		    conn_vhdl);
-#endif
-	    continue;
-	}
-#ifdef LATER
-	/*
-	 * Activate if and when we support cdl.
-	 */
-	if (aa)
-	    async_attach_add_info(conn_vhdl, aa);
-#endif	/* LATER */
-
-	error_func = pciio_device_attach(conn_vhdl, drv_flags);
-
-        pcibr_info->f_att_det_error = error_func;
-
-	if (error_func)
-	    error_slot = error_func;
-
-        error = error_slot;
-
-    }				/* next func */
-
-    if (error) {
-	if ((error != ENODEV) && (error != EUNATCH))
-	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
-    } else {
-        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
-    }
-        
-    return(error);
-}
-
-/*
- * pcibr_slot_call_device_detach
- *	This calls the associated driver detach routine for the PCI
- * 	card in this slot.
- */
-int
-pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
-			      pciio_slot_t slot,
-			      int          drv_flags)
-{
-    pcibr_soft_t	pcibr_soft;
-    pcibr_info_h	pcibr_infoh;
-    pcibr_info_t	pcibr_info;
-    int			func;
-    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
-    int			nfunc;
-    int                 error_func;
-    int                 error_slot = 0;
-    int                 error = ENODEV;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-	return(EINVAL);
-
-    if (pcibr_soft->bs_slot[slot].has_host)
-        return(EPERM);
-
-    /* Make sure that we do not detach a system critical function vertex */
-    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
-        return(EPERM);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-	pcibr_info = pcibr_infoh[func];
-	
-	if (!pcibr_info)
-	    continue;
-
-	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-	    continue;
-
-	conn_vhdl = pcibr_info->f_vertex;
-
-	error_func = pciio_device_detach(conn_vhdl, drv_flags);
-
-        pcibr_info->f_att_det_error = error_func;
-
-	if (error_func)
-	    error_slot = error_func;
-
-	error = error_slot;
-
-    }				/* next func */
-
-    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
-
-    if (error) {
-	if ((error != ENODEV) && (error != EUNATCH))
-            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
-    } else {
-        if (conn_vhdl != GRAPH_VERTEX_NONE) 
-            pcibr_device_unregister(conn_vhdl);
-        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
-    }
-        
-    return(error);
-}
-
-/*
- * pcibr_slot_detach
- *	This is a place holder routine to keep track of all the
- *	slot-specific freeing that needs to be done.
- */
-int
-pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
-		  pciio_slot_t slot,
-		  int          drv_flags)
-{
-    int		  error;
-    
-    /* Call the device detach function */
-    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
-    return (error);
-
-}
-
-/*
- * pcibr_is_slot_sys_critical
- *      Check slot for any functions that are system critical.
- *      Return 1 if any are system critical or 0 otherwise.
- *
- *      This function will always return 0 when called by 
- *      pcibr_attach() because the system critical vertices 
- *      have not yet been set in the hwgraph.
- */
-int
-pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
-                      pciio_slot_t slot)
-{
-    pcibr_soft_t        pcibr_soft;
-    pcibr_info_h        pcibr_infoh;
-    pcibr_info_t        pcibr_info;
-    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
-    int                 nfunc;
-    int                 func;
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
-        return(0);
-
-    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
-    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
-
-    for (func = 0; func < nfunc; ++func) {
-
-        pcibr_info = pcibr_infoh[func];
-        if (!pcibr_info)
-            continue;
-
-        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
-            continue;
-
-        conn_vhdl = pcibr_info->f_vertex;
-        if (is_sys_critical_vertex(conn_vhdl)) { 
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-            PRINT_WARNING("%v is a system critical device vertex\n", conn_vhdl);
-#else
-            PRINT_WARNING("%p is a system critical device vertex\n", conn_vhdl);
-#endif
-            return(1); 
-        }
-
-    }
-
-    return(0);
-}
-
-/*
- * pcibr_device_unregister
- *	This frees up any hardware resources reserved for this PCI device
- * 	and removes any PCI infrastructural information setup for it.
- *	This is usually used at the time of shutting down of the PCI card.
- */
-int
-pcibr_device_unregister(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t	 pciio_info;
-    devfs_handle_t	 pcibr_vhdl;
-    pciio_slot_t	 slot;
-    pcibr_soft_t	 pcibr_soft;
-    bridge_t		*bridge;
-    int			 error_call;
-    int			 error = 0;
-
-    pciio_info = pciio_info_get(pconn_vhdl);
-
-    pcibr_vhdl = pciio_info_master_get(pciio_info);
-    slot = pciio_info_slot_get(pciio_info);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge = pcibr_soft->bs_base;
-
-    /* Clear all the hardware xtalk resources for this device */
-    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
-
-    /* Flush all the rrbs */
-    pcibr_rrb_flush(pconn_vhdl);
-
-    /* Free the rrbs allocated to this slot */
-    error_call = do_pcibr_rrb_free(bridge, slot, 
-		                   pcibr_soft->bs_rrb_valid[slot] +
-		                   pcibr_soft->bs_rrb_valid[slot + 
-                                   PCIBR_RRB_SLOT_VIRTUAL]);
-
-    if (error_call)
-        error = ERANGE;
-
-    pcibr_soft->bs_rrb_valid[slot] = 0;
-    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0;
-    pcibr_soft->bs_rrb_res[slot] = 0;
-
-    /* Flush the write buffers !! */
-    error_call = pcibr_wrb_flush(pconn_vhdl);
-
-    if (error_call)
-        error = error_call;
-
-    /* Clear the information specific to the slot */
-    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
-
-    if (error_call)
-        error = error_call;
-
-    return(error);
-    
-}
-
-/* 
- * build a convenience link path in the
- * form of ".../<iobrick>/bus/<busnum>"
- * 
- * returns 1 on success, 0 otherwise
- *
- * depends on hwgraph separator == '/'
- */
-int
-pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
-{
-        char dst[MAXDEVNAME];
-	char *dp = dst;
-        char *cp, *xp;
-        int widgetnum;
-        char pcibus[8];
-	devfs_handle_t nvtx, svtx;
-	int rv;
-
-#if DEBUG
-	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
-		slot, f_c);
-	{
-		int pos;
-		char dname[256];
-		pos = devfs_generate_path(f_c, dname, 256);
-		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
-	}
-#endif
-
-	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
-		return 0;
-
-	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
-
-	/* find the widget number */
-	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
-	if (xp == NULL)
-		return 0;
-	widgetnum = atoi(xp+7);
-	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
-		return 0;
-
-	/* remove "/pci/direct" from path */
-	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
-	if (cp == NULL)
-		return 0;
-	*cp = (char)NULL;
-
-	/* get the vertex for the widget */
-	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
-		return 0;
-
-	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
-
-	/* dst example now == /hw/module/001c02/Pbrick */
-
-	/* get the bus number */
-        strcat(dst, "/bus");
-        sprintf(pcibus, "%d", p_busnum[widgetnum]);
-
-	/* link to bus to widget */
-	rv = hwgraph_path_add(NULL, dp, &nvtx);
-	if (GRAPH_SUCCESS == rv)
-		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
-
-	return (rv == GRAPH_SUCCESS);
-}
-
-
-/*
- *    pcibr_attach: called every time the crosstalk
- *      infrastructure is asked to initialize a widget
- *      that matches the part number we handed to the
- *      registration routine above.
- */
-/*ARGSUSED */
-int
-pcibr_attach(devfs_handle_t xconn_vhdl)
-{
-    /* REFERENCED */
-    graph_error_t           rc;
-    devfs_handle_t            pcibr_vhdl;
-    devfs_handle_t            ctlr_vhdl;
-    bridge_t               *bridge = NULL;
-    bridgereg_t             id;
-    int                     rev;
-    pcibr_soft_t            pcibr_soft;
-    pcibr_info_t            pcibr_info;
-    xwidget_info_t          info;
-    xtalk_intr_t            xtalk_intr;
-    device_desc_t           dev_desc;
-    int                     slot;
-    int                     ibit;
-    devfs_handle_t            noslot_conn;
-    char                    devnm[MAXDEVNAME], *s;
-    pcibr_hints_t           pcibr_hints;
-    bridgereg_t             b_int_enable;
-    unsigned                rrb_fixed = 0;
-
-    iopaddr_t               pci_io_fb, pci_io_fl;
-    iopaddr_t               pci_lo_fb, pci_lo_fl;
-    iopaddr_t               pci_hi_fb, pci_hi_fl;
-
-    int                     spl_level;
-#ifdef LATER
-    char		    *nicinfo = (char *)0;
-#endif
-
-#if PCI_FBBE
-    int                     fast_back_to_back_enable;
-#endif
-    l1sc_t		    *scp;
-    nasid_t		    nasid;
-
-    async_attach_t          aa = NULL;
-
-    aa = async_attach_get_info(xconn_vhdl);
-
-#if DEBUG && ATTACH_DEBUG
-    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
-    {
-	int pos;
-	char dname[256];
-	pos = devfs_generate_path(xconn_vhdl, dname, 256);
-	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
-    }
-#endif
-
-    /* Setup the PRB for the bridge in CONVEYOR BELT
-     * mode. PRBs are setup in default FIRE-AND-FORGET
-     * mode during the initialization.
-     */
-    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
-
-    bridge = (bridge_t *)
-	xtalk_piotrans_addr(xconn_vhdl, NULL,
-			    0, sizeof(bridge_t), 0);
-
-#ifndef MEDUSA_HACK
-    if ((bridge->b_wid_stat & BRIDGE_STAT_PCI_GIO_N) == 0)
-	return -1;			/* someone else handles GIO bridges. */
-#endif
-
-#ifdef BRINGUP
-    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
-	NeedXbridgeSwap = 1;
-#endif
-
-    /*
-     * Create the vertex for the PCI bus, which we
-     * will also use to hold the pcibr_soft and
-     * which will be the "master" vertex for all the
-     * pciio connection points we will hang off it.
-     * This needs to happen before we call nic_bridge_vertex_info
-     * as we are some of the *_vmc functions need access to the edges.
-     *
-     * Opening this vertex will provide access to
-     * the Bridge registers themselves.
-     */
-    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
-    ASSERT(rc == GRAPH_SUCCESS);
-
-    ctlr_vhdl = NULL;
-    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
-                0, DEVFS_FL_AUTO_DEVNUM,
-                0, 0,
-                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
-                &pcibr_fops, NULL);
-
-    ASSERT(ctlr_vhdl != NULL);
-
-    /*
-     * decode the nic, and hang its stuff off our
-     * connection point where other drivers can get
-     * at it.
-     */
-#ifdef LATER
-    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
-#endif
-
-    /*
-     * Get the hint structure; if some NIC callback
-     * marked this vertex as "hands-off" then we
-     * just return here, before doing anything else.
-     */
-    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
-
-    if (pcibr_hints && pcibr_hints->ph_hands_off)
-	return -1;			/* generic operations disabled */
-
-    id = bridge->b_wid_id;
-    rev = XWIDGET_PART_REV_NUM(id);
-
-    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
-
-    /*
-     * allocate soft state structure, fill in some
-     * fields, and hook it up to our vertex.
-     */
-    NEW(pcibr_soft);
-    BZERO(pcibr_soft, sizeof *pcibr_soft);
-    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
-
-    pcibr_soft->bs_conn = xconn_vhdl;
-    pcibr_soft->bs_vhdl = pcibr_vhdl;
-    pcibr_soft->bs_base = bridge;
-    pcibr_soft->bs_rev_num = rev;
-    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
-    if (is_xbridge(bridge)) {
-	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
-	pcibr_soft->bs_xbridge = 1;
-    } else {
-	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
-	pcibr_soft->bs_xbridge = 0;
-    }
-
-    nasid = NASID_GET(bridge);
-    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
-    pcibr_soft->bs_l1sc = scp;
-    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
-    pcibr_soft->bsi_err_intr = 0;
-
-    /* Bridges up through REV C
-     * are unable to set the direct
-     * byteswappers to BYTE_STREAM.
-     */
-    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
-	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
-	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
-    }
-#if PCIBR_SOFT_LIST
-    {
-	pcibr_list_p            self;
-
-	NEW(self);
-	self->bl_soft = pcibr_soft;
-	self->bl_vhdl = pcibr_vhdl;
-	self->bl_next = pcibr_list;
-	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
-    }
-#endif
-
-    /*
-     * get the name of this bridge vertex and keep the info. Use this
-     * only where it is really needed now: like error interrupts.
-     */
-    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
-    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
-    strcpy(pcibr_soft->bs_name, s);
-
-#if SHOW_REVS || DEBUG
-#if !DEBUG
-    if (kdebug)
-#endif
-	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
-		is_xbridge(bridge) ? "X" : "",
-		(rev == BRIDGE_PART_REV_A) ? "A" :
-		(rev == BRIDGE_PART_REV_B) ? "B" :
-		(rev == BRIDGE_PART_REV_C) ? "C" :
-		(rev == BRIDGE_PART_REV_D) ? "D" :
-		(rev == XBRIDGE_PART_REV_A) ? "A" :
-		(rev == XBRIDGE_PART_REV_B) ? "B" :
-		"unknown",
-		rev, pcibr_soft->bs_name);
-#endif
-
-    info = xwidget_info_get(xconn_vhdl);
-    pcibr_soft->bs_xid = xwidget_info_id_get(info);
-    pcibr_soft->bs_master = xwidget_info_master_get(info);
-    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
-
-    /*
-     * Init bridge lock.
-     */
-    spin_lock_init(&pcibr_soft->bs_lock);
-
-    /*
-     * If we have one, process the hints structure.
-     */
-    if (pcibr_hints) {
-	rrb_fixed = pcibr_hints->ph_rrb_fixed;
-
-	pcibr_soft->bs_rrb_fixed = rrb_fixed;
-
-	if (pcibr_hints->ph_intr_bits)
-	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
-
-	for (slot = 0; slot < 8; ++slot) {
-	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
-
-	    if (hslot < 0) {
-		pcibr_soft->bs_slot[slot].host_slot = slot;
-	    } else {
-		pcibr_soft->bs_slot[slot].has_host = 1;
-		pcibr_soft->bs_slot[slot].host_slot = hslot;
-	    }
-	}
-    }
-    /*
-     * set up initial values for state fields
-     */
-    for (slot = 0; slot < 8; ++slot) {
-	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
-	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
-	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
-	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
-    }
-
-    for (ibit = 0; ibit < 8; ++ibit) {
-	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
-							&(bridge->b_int_status);
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
-	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
-    }
-
-    /*
-     * connect up our error handler
-     */
-    xwidget_error_register(xconn_vhdl, pcibr_error_handler, pcibr_soft);
-
-    /*
-     * Initialize various Bridge registers.
-     */
-
-    /*
-     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
-     * to zero to avoid dropping stores. (#475347)
-     */
-    if (rev < BRIDGE_PART_REV_D)
-	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
-
-    /*
-     * Clear all pending interrupts.
-     */
-    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
-
-    /*
-     * Until otherwise set up,
-     * assume all interrupts are
-     * from slot 7.
-     */
-    bridge->b_int_device = (uint32_t) 0xffffffff;
-
-    {
-	bridgereg_t             dirmap;
-	paddr_t                 paddr;
-	iopaddr_t               xbase;
-	xwidgetnum_t            xport;
-	iopaddr_t               offset;
-	int                     num_entries = 0;
-	int                     entry;
-	cnodeid_t		cnodeid;
-	nasid_t			nasid;
-	char		       *node_val;
-	devfs_handle_t		node_vhdl;
-	char			vname[MAXDEVNAME];
-
-	/* Set the Bridge's 32-bit PCI to XTalk
-	 * Direct Map register to the most useful
-	 * value we can determine.  Note that we
-	 * must use a single xid for all of:
-	 *      direct-mapped 32-bit DMA accesses
-	 *      direct-mapped 64-bit DMA accesses
-	 *      DMA accesses through the PMU
-	 *      interrupts
-	 * This is the only way to guarantee that
-	 * completion interrupts will reach a CPU
-	 * after all DMA data has reached memory.
-	 * (Of course, there may be a few special
-	 * drivers/controllers that explicitly manage
-	 * this ordering problem.)
-	 */
-
-	cnodeid = 0;  /* default node id */
-	/*
-	 * Determine the base address node id to be used for all 32-bit
-	 * Direct Mapping I/O. The default is node 0, but this can be changed
-	 * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE
-	 * attribute in the irix.sm config file. A device driver can obtain
-	 * this node value via a call to pcibr_get_dmatrans_node().
-	 */
-	node_val = device_admin_info_get(pcibr_vhdl, ADMIN_LBL_DMATRANS_NODE);
-	if (node_val != NULL) {
-	    node_vhdl = hwgraph_path_to_vertex(node_val);
-	    if (node_vhdl != GRAPH_VERTEX_NONE) {
-		cnodeid = nodevertex_to_cnodeid(node_vhdl);
-	    }
-	    if ((node_vhdl == GRAPH_VERTEX_NONE) || (cnodeid == CNODEID_NONE)) {
-		cnodeid = 0;
-		vertex_to_name(pcibr_vhdl, vname, sizeof(vname));
-		PRINT_WARNING( "Invalid hwgraph node path specified:\n     DEVICE_ADMIN: %s %s=%s\n",
-			vname, ADMIN_LBL_DMATRANS_NODE, node_val);
-	    }
-	}
-	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
-	paddr = NODE_OFFSET(nasid) + 0;
-
-	/* currently, we just assume that if we ask
-	 * for a DMA mapping to "zero" the XIO
-	 * host will transmute this into a request
-	 * for the lowest hunk of memory.
-	 */
-	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
-				    paddr, _PAGESZ, 0);
-
-	if (xbase != XIO_NOWHERE) {
-	    if (XIO_PACKED(xbase)) {
-		xport = XIO_PORT(xbase);
-		xbase = XIO_ADDR(xbase);
-	    } else
-		xport = pcibr_soft->bs_mxid;
-
-	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
-	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
-
-	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
-
-	    if (xbase)
-		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
-	    else if (offset >= (512 << 20))
-		dirmap |= BRIDGE_DIRMAP_ADD512;
-
-	    bridge->b_dir_map = dirmap;
-	}
-	/*
-	 * Set bridge's idea of page size according to the system's
-	 * idea of "IO page size".  TBD: The idea of IO page size
-	 * should really go away.
-	 */
-	/*
-	 * ensure that we write and read without any interruption.
-	 * The read following the write is required for the Bridge war
-	 */
-	spl_level = splhi();
-#if IOPGSIZE == 4096
-	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
-#elif IOPGSIZE == 16384
-	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
-#else
-	<<<Unable to deal with IOPGSIZE >>>;
-#endif
-	bridge->b_wid_control;		/* inval addr bug war */
-	splx(spl_level);
-
-	/* Initialize internal mapping entries */
-	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++)
-	    bridge->b_int_ate_ram[entry].wr = 0;
-
-	/*
-	 * Determine if there's external mapping SSRAM on this
-	 * bridge.  Set up Bridge control register appropriately,
-	 * inititlize SSRAM, and set software up to manage RAM
-	 * entries as an allocatable resource.
-	 *
-	 * Currently, we just use the rm* routines to manage ATE
-	 * allocation.  We should probably replace this with a
-	 * Best Fit allocator.
-	 *
-	 * For now, if we have external SSRAM, avoid using
-	 * the internal ssram: we can't turn PREFETCH on
-	 * when we use the internal SSRAM; and besides,
-	 * this also guarantees that no allocation will
-	 * straddle the internal/external line, so we
-	 * can increment ATE write addresses rather than
-	 * recomparing against BRIDGE_INTERNAL_ATES every
-	 * time.
-	 */
-	if (is_xbridge(bridge))
-		num_entries = 0;
-	else
-		num_entries = pcibr_init_ext_ate_ram(bridge);
-
-	/* we always have 128 ATEs (512 for Xbridge) inside the chip
-	 * even if disabled for debugging.
-	 */
-	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
-	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
-#endif
-
-	if (num_entries > pcibr_soft->bs_int_ate_size) {
-#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
-	    printk("pcibr_attach: disabling internal ATEs.\n");
-	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
-#endif
-	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
-	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
-			   num_entries - pcibr_soft->bs_int_ate_size);
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
-		    num_entries - pcibr_soft->bs_int_ate_size);
-#endif
-	}
-    }
-
-    {
-	bridgereg_t             dirmap;
-	iopaddr_t               xbase;
-
-	/*
-	 * now figure the *real* xtalk base address
-	 * that dirmap sends us to.
-	 */
-	dirmap = bridge->b_dir_map;
-	if (dirmap & BRIDGE_DIRMAP_OFF)
-	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
-			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
-	else if (dirmap & BRIDGE_DIRMAP_ADD512)
-	    xbase = 512 << 20;
-	else
-	    xbase = 0;
-
-	pcibr_soft->bs_dir_xbase = xbase;
-
-	/* it is entirely possible that we may, at this
-	 * point, have our dirmap pointing somewhere
-	 * other than our "master" port.
-	 */
-	pcibr_soft->bs_dir_xport =
-	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
-    }
-
-    /* pcibr sources an error interrupt;
-     * figure out where to send it.
-     *
-     * If any interrupts are enabled in bridge,
-     * then the prom set us up and our interrupt
-     * has already been reconnected in mlreset
-     * above.
-     *
-     * Need to set the D_INTR_ISERR flag
-     * in the dev_desc used for allocating the
-     * error interrupt, so our interrupt will
-     * be properly routed and prioritized.
-     *
-     * If our crosstalk provider wants to
-     * fix widget error interrupts to specific
-     * destinations, D_INTR_ISERR is how it
-     * knows to do this.
-     */
-
-    dev_desc = device_desc_dup(pcibr_vhdl);
-    device_desc_flags_set(dev_desc,
-			  device_desc_flags_get(dev_desc) | D_INTR_ISERR);
-    device_desc_intr_name_set(dev_desc, "Bridge error");
-
-    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
-    ASSERT(xtalk_intr != NULL);
-
-    device_desc_free(dev_desc);
-
-    pcibr_soft->bsi_err_intr = xtalk_intr;
-
-    /*
-     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
-     * in order to work around some addressing limitations.  In order
-     * for that fire wall to work properly, we need to make sure we
-     * start from a known clean state.
-     */
-    pcibr_clearwidint(bridge);
-
-    xtalk_intr_connect(xtalk_intr,
-		       (intr_func_t) pcibr_error_intr_handler,
-		       (intr_arg_t) pcibr_soft,
-		       (xtalk_intr_setfunc_t) pcibr_setwidint,
-		       (void *) bridge,
-		       (void *) 0);
-
-    /*
-     * now we can start handling error interrupts;
-     * enable all of them.
-     * NOTE: some PCI ints may already be enabled.
-     */
-    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
-
-
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
-
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-
-    /*
-     * Depending on the rev of bridge, disable certain features.
-     * Easiest way seems to be to force the PCIBR_NOwhatever
-     * flag to be on for all DMA calls, which overrides any
-     * PCIBR_whatever flag or even the setting of whatever
-     * from the PCIIO_DMA_class flags (or even from the other
-     * PCIBR flags, since NO overrides YES).
-     */
-    pcibr_soft->bs_dma_flags = 0;
-
-    /* PREFETCH:
-     * Always completely disabled for REV.A;
-     * at "pcibr_prefetch_enable_rev", anyone
-     * asking for PCIIO_PREFETCH gets it.
-     * Between these two points, you have to ask
-     * for PCIBR_PREFETCH, which promises that
-     * your driver knows about known Bridge WARs.
-     */
-    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
-	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
-    else if (pcibr_soft->bs_rev_num < 
-		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
-	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
-
-    /* WRITE_GATHER:
-     * Disabled up to but not including the
-     * rev number in pcibr_wg_enable_rev. There
-     * is no "WAR range" as with prefetch.
-     */
-    if (pcibr_soft->bs_rev_num < 
-		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
-	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
-
-    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
-    pciio_provider_startup(pcibr_vhdl);
-
-    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
-    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
-
-    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
-    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
-
-    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
-    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
-
-
-    PCI_ADDR_SPACE_LIMITS_STORE();
-
-    /* build "no-slot" connection point
-     */
-    pcibr_info = pcibr_device_info_new
-	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
-	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
-    noslot_conn = pciio_device_info_register
-	(pcibr_vhdl, &pcibr_info->f_c);
-
-    /* Remember the no slot connection point info for tearing it
-     * down during detach.
-     */
-    pcibr_soft->bs_noslot_conn = noslot_conn;
-    pcibr_soft->bs_noslot_info = pcibr_info;
-#if PCI_FBBE
-    fast_back_to_back_enable = 1;
-#endif
-
-#if PCI_FBBE
-    if (fast_back_to_back_enable) {
-	/*
-	 * All devices on the bus are capable of fast back to back, so
-	 * we need to set the fast back to back bit in all devices on
-	 * the bus that are capable of doing such accesses.
-	 */
-    }
-#endif
-
-#ifdef LATER
-    /* If the bridge has been reset then there is no need to reset
-     * the individual PCI slots.
-     */
-    for (slot = 0; slot < 8; ++slot)  
-	/* Reset all the slots */
-	(void)pcibr_slot_reset(pcibr_vhdl, slot);
-#endif
-
-    for (slot = 0; slot < 8; ++slot)
-	/* Find out what is out there */
-	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Set up the address space for this slot in the pci land */
-	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Setup the device register */
-	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
-
-#ifndef __ia64
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-    for (slot = 0; slot < 8; ++slot)  
-	/* Set up convenience links */
-	if (is_xbridge(bridge))
-		if (pcibr_soft->bs_slot[slot].bss_ninfo > 0) /* if occupied */
-			pcibr_bus_cnvlink(pcibr_info->f_vertex, slot);
-#endif
-#endif
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Setup host/guest relations */
-	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
-
-    for (slot = 0; slot < 8; ++slot)  
-	/* Initial RRB management */
-	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
-
-    /* driver attach routines should be called out from generic linux code */
-    for (slot = 0; slot < 8; ++slot)  
-	/* Call the device attach */
-	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
-
-    /*
-     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
-     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
-     */
-    if (pcibr_soft->bs_moduleid > 0) {
-	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
-	case 'p':		/* Pbrick */
-		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
-		break;
-	case 'i':		/* Ibrick */
-	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
-		if (pcibr_soft->bs_xid == 0xe) {
-			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
-		}
-		else {
-		    	/* allocate one RRB for the serial port */
-			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
-		}
-		break;
-	} /* switch */
-    }
-
-#ifdef LATER
-    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
-	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
-#if PCIBR_RRB_DEBUG
-	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
-
-	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
-		pcibr_vhdl,
-		pcibr_soft->bs_rrb_avail[0],
-		pcibr_soft->bs_rrb_avail[1]);
-
-	for (slot = 0; slot < 8; ++slot)
-	    printf("\t%d+%d+%d",
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
-	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-
-	printf("\n");
-#endif
-    }
-#else
-	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
-#endif
-
-    if (aa)
-	    async_attach_add_info(noslot_conn, aa);
-
-    pciio_device_attach(noslot_conn, 0);
-
-
-    /* 
-     * Tear down pointer to async attach info -- async threads for
-     * bridge's descendants may be running but the bridge's work is done.
-     */
-    if (aa)
-	    async_attach_del_info(xconn_vhdl);
-
-    return 0;
-}
-/*
- * pcibr_detach:
- *	Detach the bridge device from the hwgraph after cleaning out all the 
- *	underlying vertices.
- */
-int
-pcibr_detach(devfs_handle_t xconn)
-{
-    pciio_slot_t	slot;
-    devfs_handle_t	pcibr_vhdl;
-    pcibr_soft_t	pcibr_soft;
-    bridge_t		*bridge;
-
-    /* Get the bridge vertex from its xtalk connection point */
-    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
-	return(1);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    bridge = pcibr_soft->bs_base;
-
-    /* Disable the interrupts from the bridge */
-    bridge->b_int_enable = 0;
-
-    /* Detach all the PCI devices talking to this bridge */
-    for(slot = 0; slot < 8; slot++) {
-#ifdef DEBUG
-	printk("pcibr_device_detach called for %p/%d\n",
-		pcibr_vhdl,slot);
-#endif
-	pcibr_slot_detach(pcibr_vhdl, slot, 0);
-    }
-
-    /* Unregister the no-slot connection point */
-    pciio_device_info_unregister(pcibr_vhdl,
-				 &(pcibr_soft->bs_noslot_info->f_c));
-
-    spin_lock_destroy(&pcibr_soft->bs_lock);
-    kfree(pcibr_soft->bs_name);
-    
-    /* Error handler gets unregistered when the widget info is 
-     * cleaned 
-     */
-    /* Free the soft ATE maps */
-    if (pcibr_soft->bs_int_ate_map)
-	rmfreemap(pcibr_soft->bs_int_ate_map);
-    if (pcibr_soft->bs_ext_ate_map)
-	rmfreemap(pcibr_soft->bs_ext_ate_map);
-
-    /* Disconnect the error interrupt and free the xtalk resources 
-     * associated with it.
-     */
-    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
-    xtalk_intr_free(pcibr_soft->bsi_err_intr);
-
-    /* Clear the software state maintained by the bridge driver for this
-     * bridge.
-     */
-    DEL(pcibr_soft);
-    /* Remove the Bridge revision labelled info */
-    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
-    /* Remove the character device associated with this bridge */
-    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
-    /* Remove the PCI bridge vertex */
-    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
-
-    return(0);
-}
-
-int
-pcibr_asic_rev(devfs_handle_t pconn_vhdl)
-{
-    devfs_handle_t            pcibr_vhdl;
-    arbitrary_info_t        ainfo;
-
-    if (GRAPH_SUCCESS !=
-	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
-	return -1;
-
-    if (GRAPH_SUCCESS !=
-	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
-	return -1;
-
-    return (int) ainfo;
-}
-
-int
-pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    pciio_slot_t  slot;
-    slot = pciio_info_slot_get(pciio_info);
-    pcibr_device_write_gather_flush(pcibr_soft, slot);
-    return 0;
-}
-
-/* =====================================================================
- *    PIO MANAGEMENT
- */
-
-LOCAL iopaddr_t
-pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
-		      pciio_slot_t slot,
-		      pciio_space_t space,
-		      iopaddr_t pci_addr,
-		      size_t req_size,
-		      unsigned flags)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    unsigned                bar;	/* which BASE reg on device is decoding */
-    iopaddr_t               xio_addr = XIO_NOWHERE;
-
-    pciio_space_t           wspace;	/* which space device is decoding */
-    iopaddr_t               wbase;	/* base of device decode on PCI */
-    size_t                  wsize;	/* size of device decode on PCI */
-
-    int                     try;	/* DevIO(x) window scanning order control */
-    int                     win;	/* which DevIO(x) window is being used */
-    pciio_space_t           mspace;	/* target space for devio(x) register */
-    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
-    size_t                  msize;	/* size of devio(x) mapped area on PCI */
-    size_t                  mmask;	/* addr bits stored in Device(x) */
-
-    unsigned long           s;
-
-    s = pcibr_lock(pcibr_soft);
-
-    if (pcibr_soft->bs_slot[slot].has_host) {
-	slot = pcibr_soft->bs_slot[slot].host_slot;
-	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
-    }
-    if (space == PCIIO_SPACE_NONE)
-	goto done;
-
-    if (space == PCIIO_SPACE_CFG) {
-	/*
-	 * Usually, the first mapping
-	 * established to a PCI device
-	 * is to its config space.
-	 *
-	 * In any case, we definitely
-	 * do NOT need to worry about
-	 * PCI BASE registers, and
-	 * MUST NOT attempt to point
-	 * the DevIO(x) window at
-	 * this access ...
-	 */
-	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
-	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
-	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
-
-	goto done;
-    }
-    if (space == PCIIO_SPACE_ROM) {
-	/* PIO to the Expansion Rom.
-	 * Driver is responsible for
-	 * enabling and disabling
-	 * decodes properly.
-	 */
-	wbase = pcibr_info->f_rbase;
-	wsize = pcibr_info->f_rsize;
-
-	/*
-	 * While the driver should know better
-	 * than to attempt to map more space
-	 * than the device is decoding, he might
-	 * do it; better to bail out here.
-	 */
-	if ((pci_addr + req_size) > wsize)
-	    goto done;
-
-	pci_addr += wbase;
-	space = PCIIO_SPACE_MEM;
-    }
-    /*
-     * reduce window mappings to raw
-     * space mappings (maybe allocating
-     * windows), and try for DevIO(x)
-     * usage (setting it if it is available).
-     */
-    bar = space - PCIIO_SPACE_WIN0;
-    if (bar < 6) {
-	wspace = pcibr_info->f_window[bar].w_space;
-	if (wspace == PCIIO_SPACE_NONE)
-	    goto done;
-
-	/* get PCI base and size */
-	wbase = pcibr_info->f_window[bar].w_base;
-	wsize = pcibr_info->f_window[bar].w_size;
-
-	/*
-	 * While the driver should know better
-	 * than to attempt to map more space
-	 * than the device is decoding, he might
-	 * do it; better to bail out here.
-	 */
-	if ((pci_addr + req_size) > wsize)
-	    goto done;
-
-	/* shift from window relative to
-	 * decoded space relative.
-	 */
-	pci_addr += wbase;
-	space = wspace;
-    } else
-	bar = -1;
-
-    /* Scan all the DevIO(x) windows twice looking for one
-     * that can satisfy our request. The first time through,
-     * only look at assigned windows; the second time, also
-     * look at PCIIO_SPACE_NONE windows. Arrange the order
-     * so we always look at our own window first.
-     *
-     * We will not attempt to satisfy a single request
-     * by concatinating multiple windows.
-     */
-    for (try = 0; try < 16; ++try) {
-	bridgereg_t             devreg;
-	unsigned                offset;
-
-	win = (try + slot) % 8;
-
-	/* If this DevIO(x) mapping area can provide
-	 * a mapping to this address, use it.
-	 */
-	msize = (win < 2) ? 0x200000 : 0x100000;
-	mmask = -msize;
-	if (space != PCIIO_SPACE_IO)
-	    mmask &= 0x3FFFFFFF;
-
-	offset = pci_addr & (msize - 1);
-
-	/* If this window can't possibly handle that request,
-	 * go on to the next window.
-	 */
-	if (((pci_addr & (msize - 1)) + req_size) > msize)
-	    continue;
-
-	devreg = pcibr_soft->bs_slot[win].bss_device;
-
-	/* Is this window "nailed down"?
-	 * If not, maybe we can use it.
-	 * (only check this the second time through)
-	 */
-	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
-	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
-
-	    /* If this is the primary DevIO(x) window
-	     * for some other device, skip it.
-	     */
-	    if ((win != slot) &&
-		(PCIIO_VENDOR_ID_NONE !=
-		 pcibr_soft->bs_slot[win].bss_vendor_id))
-		continue;
-
-	    /* It's a free window, and we fit in it.
-	     * Set up Device(win) to our taste.
-	     */
-	    mbase = pci_addr & mmask;
-
-	    /* check that we would really get from
-	     * here to there.
-	     */
-	    if ((mbase | offset) != pci_addr)
-		continue;
-
-	    devreg &= ~BRIDGE_DEV_OFF_MASK;
-	    if (space != PCIIO_SPACE_IO)
-		devreg |= BRIDGE_DEV_DEV_IO_MEM;
-	    else
-		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
-	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
-
-	    /* default is WORD_VALUES.
-	     * if you specify both,
-	     * operation is undefined.
-	     */
-	    if (flags & PCIIO_BYTE_STREAM)
-		devreg |= BRIDGE_DEV_DEV_SWAP;
-	    else
-		devreg &= ~BRIDGE_DEV_DEV_SWAP;
-
-	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
-		bridge->b_device[win].reg = devreg;
-		pcibr_soft->bs_slot[win].bss_device = devreg;
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-
-#if DEBUG && PCI_DEBUG
-		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
-#endif
-	    }
-	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
-	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
-	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
-
-#if DEBUG && PCI_DEBUG
-	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
-		    __FUNCTION__, __LINE__, space, space_desc,
-		    pci_addr, pci_addr + req_size - 1,
-		    slot, win, devreg);
-#endif
-
-	    goto done;
-	}				/* endif DevIO(x) not pointed */
-	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
-
-	/* Now check for request incompat with DevIO(x)
-	 */
-	if ((mspace != space) ||
-	    (pci_addr < mbase) ||
-	    ((pci_addr + req_size) > (mbase + msize)) ||
-	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
-	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
-	    continue;
-
-	/* DevIO(x) window is pointed at PCI space
-	 * that includes our target. Calculate the
-	 * final XIO address, release the lock and
-	 * return.
-	 */
-	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
-
-#if DEBUG && PCI_DEBUG
-	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
-		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
-#endif
-	goto done;
-    }
-
-    switch (space) {
-	/*
-	 * Accesses to device decode
-	 * areas that do a not fit
-	 * within the DevIO(x) space are
-	 * modified to be accesses via
-	 * the direct mapping areas.
-	 *
-	 * If necessary, drivers can
-	 * explicitly ask for mappings
-	 * into these address spaces,
-	 * but this should never be needed.
-	 */
-    case PCIIO_SPACE_MEM:		/* "mem space" */
-    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
-	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
-	    BRIDGE_PCI_MEM32_LIMIT)
-	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
-	break;
-
-    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
-	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
-	    BRIDGE_PCI_MEM64_LIMIT)
-	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
-	break;
-
-    case PCIIO_SPACE_IO:		/* "i/o space" */
-	/* Bridge Hardware Bug WAR #482741:
-	 * The 4G area that maps directly from
-	 * XIO space to PCI I/O space is busted
-	 * until Bridge Rev D.
-	 */
-	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
-	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
-	     BRIDGE_PCI_IO_LIMIT))
-	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
-	break;
-    }
-
-    /* Check that "Direct PIO" byteswapping matches,
-     * try to change it if it does not.
-     */
-    if (xio_addr != XIO_NOWHERE) {
-	unsigned                bst;	/* nonzero to set bytestream */
-	unsigned               *bfp;	/* addr of record of how swapper is set */
-	unsigned                swb;	/* which control bit to mung */
-	unsigned                bfo;	/* current swapper setting */
-	unsigned                bfn;	/* desired swapper setting */
-
-	bfp = ((space == PCIIO_SPACE_IO)
-	       ? (&pcibr_soft->bs_pio_end_io)
-	       : (&pcibr_soft->bs_pio_end_mem));
-
-	bfo = *bfp;
-
-	bst = flags & PCIIO_BYTE_STREAM;
-
-	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
-
-	if (bfn == bfo) {		/* we already match. */
-	    ;
-	} else if (bfo != 0) {		/* we have a conflict. */
-#if DEBUG && PCI_DEBUG
-	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
-		    space, 
-		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
-		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
-#endif
-	    xio_addr = XIO_NOWHERE;
-	} else {			/* OK to make the change. */
-	    bridgereg_t             octl, nctl;
-
-	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
-	    octl = bridge->b_wid_control;
-	    nctl = bst ? octl | swb : octl & ~swb;
-
-	    if (octl != nctl)		/* make the change if any */
-		bridge->b_wid_control = nctl;
-
-	    *bfp = bfn;			/* record the assignment */
-
-#if DEBUG && PCI_DEBUG
-	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
-		    space, 
-		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
-		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
-#endif
-	}
-    }
-  done:
-    pcibr_unlock(pcibr_soft, s);
-    return xio_addr;
-}
-
-/*ARGSUSED6 */
-pcibr_piomap_t
-pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
-		   device_desc_t dev_desc,
-		   pciio_space_t space,
-		   iopaddr_t pci_addr,
-		   size_t req_size,
-		   size_t req_size_max,
-		   unsigned flags)
-{
-    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    pcibr_piomap_t         *mapptr;
-    pcibr_piomap_t          maplist;
-    pcibr_piomap_t          pcibr_piomap;
-    iopaddr_t               xio_addr;
-    xtalk_piomap_t          xtalk_piomap;
-    unsigned long           s;
-
-    /* Make sure that the req sizes are non-zero */
-    if ((req_size < 1) || (req_size_max < 1))
-	return NULL;
-
-    /*
-     * Code to translate slot/space/addr
-     * into xio_addr is common between
-     * this routine and pcibr_piotrans_addr.
-     */
-    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
-
-    if (xio_addr == XIO_NOWHERE)
-	return NULL;
-
-    /* Check the piomap list to see if there is already an allocated
-     * piomap entry but not in use. If so use that one. Otherwise
-     * allocate a new piomap entry and add it to the piomap list
-     */
-    mapptr = &(pcibr_info->f_piomap);
-
-    s = pcibr_lock(pcibr_soft);
-    for (pcibr_piomap = *mapptr;
-	 pcibr_piomap != NULL;
-	 pcibr_piomap = pcibr_piomap->bp_next) {
-	if (pcibr_piomap->bp_mapsz == 0)
-	    break;
-    }
-
-    if (pcibr_piomap)
-	mapptr = NULL;
-    else {
-	pcibr_unlock(pcibr_soft, s);
-	NEW(pcibr_piomap);
-    }
-
-    pcibr_piomap->bp_dev = pconn_vhdl;
-    pcibr_piomap->bp_slot = pciio_slot;
-    pcibr_piomap->bp_flags = flags;
-    pcibr_piomap->bp_space = space;
-    pcibr_piomap->bp_pciaddr = pci_addr;
-    pcibr_piomap->bp_mapsz = req_size;
-    pcibr_piomap->bp_soft = pcibr_soft;
-    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
-
-    if (mapptr) {
-	s = pcibr_lock(pcibr_soft);
-	maplist = *mapptr;
-	pcibr_piomap->bp_next = maplist;
-	*mapptr = pcibr_piomap;
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-
-    if (pcibr_piomap) {
-	xtalk_piomap =
-	    xtalk_piomap_alloc(xconn_vhdl, 0,
-			       xio_addr,
-			       req_size, req_size_max,
-			       flags & PIOMAP_FLAGS);
-	if (xtalk_piomap) {
-	    pcibr_piomap->bp_xtalk_addr = xio_addr;
-	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
-	} else {
-	    pcibr_piomap->bp_mapsz = 0;
-	    pcibr_piomap = 0;
-	}
-    }
-    return pcibr_piomap;
-}
-
-/*ARGSUSED */
-void
-pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
-{
-    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
-    pcibr_piomap->bp_xtalk_pio = 0;
-    pcibr_piomap->bp_mapsz = 0;
-}
-
-/*ARGSUSED */
-caddr_t
-pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
-		  iopaddr_t pci_addr,
-		  size_t req_size)
-{
-    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
-			     pcibr_piomap->bp_xtalk_addr +
-			     pci_addr - pcibr_piomap->bp_pciaddr,
-			     req_size);
-}
-
-/*ARGSUSED */
-void
-pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
-{
-    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
-}
-
-/*ARGSUSED */
-caddr_t
-pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    pciio_space_t space,
-		    iopaddr_t pci_addr,
-		    size_t req_size,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    iopaddr_t               xio_addr;
-
-    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
-
-    if (xio_addr == XIO_NOWHERE)
-	return NULL;
-
-    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
-}
-
-/*
- * PIO Space allocation and management.
- *      Allocate and Manage the PCI PIO space (mem and io space)
- *      This routine is pretty simplistic at this time, and
- *      does pretty trivial management of allocation and freeing..
- *      The current scheme is prone for fragmentation..
- *      Change the scheme to use bitmaps.
- */
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
-		     device_desc_t dev_desc,
-		     pciio_space_t space,
-		     size_t req_size,
-		     size_t alignment)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_info_t            pciio_info = &pcibr_info->f_c;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    pciio_piospace_t        piosp;
-    unsigned long           s;
-
-    iopaddr_t              *pciaddr, *pcilast;
-    iopaddr_t               start_addr;
-    size_t                  align_mask;
-
-    /*
-     * Check for proper alignment
-     */
-    ASSERT(alignment >= NBPP);
-    ASSERT((alignment & (alignment - 1)) == 0);
-
-    align_mask = alignment - 1;
-    s = pcibr_lock(pcibr_soft);
-
-    /*
-     * First look if a previously allocated chunk exists.
-     */
-    if ((piosp = pcibr_info->f_piospace)) {
-	/*
-	 * Look through the list for a right sized free chunk.
-	 */
-	do {
-	    if (piosp->free &&
-		(piosp->space == space) &&
-		(piosp->count >= req_size) &&
-		!(piosp->start & align_mask)) {
-		piosp->free = 0;
-		pcibr_unlock(pcibr_soft, s);
-		return piosp->start;
-	    }
-	    piosp = piosp->next;
-	} while (piosp);
-    }
-    ASSERT(!piosp);
-
-    switch (space) {
-    case PCIIO_SPACE_IO:
-	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
-	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
-	break;
-    case PCIIO_SPACE_MEM:
-    case PCIIO_SPACE_MEM32:
-	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
-	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
-	break;
-    default:
-	ASSERT(0);
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-
-    start_addr = *pciaddr;
-
-    /*
-     * Align start_addr.
-     */
-    if (start_addr & align_mask)
-	start_addr = (start_addr + align_mask) & ~align_mask;
-
-    if ((start_addr + req_size) > *pcilast) {
-	/*
-	 * If too big a request, reject it.
-	 */
-	pcibr_unlock(pcibr_soft, s);
-	return 0;
-    }
-    *pciaddr = (start_addr + req_size);
-
-    NEW(piosp);
-    piosp->free = 0;
-    piosp->space = space;
-    piosp->start = start_addr;
-    piosp->count = req_size;
-    piosp->next = pcibr_info->f_piospace;
-    pcibr_info->f_piospace = piosp;
-
-    pcibr_unlock(pcibr_soft, s);
-    return start_addr;
-}
-
-/*ARGSUSED */
-void
-pcibr_piospace_free(devfs_handle_t pconn_vhdl,
-		    pciio_space_t space,
-		    iopaddr_t pciaddr,
-		    size_t req_size)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-
-    pciio_piospace_t        piosp;
-    unsigned long           s;
-    char                    name[1024];
-
-    /*
-     * Look through the bridge data structures for the pciio_piospace_t
-     * structure corresponding to  'pciaddr'
-     */
-    s = pcibr_lock(pcibr_soft);
-    piosp = pcibr_info->f_piospace;
-    while (piosp) {
-	/*
-	 * Piospace free can only be for the complete
-	 * chunk and not parts of it..
-	 */
-	if (piosp->start == pciaddr) {
-	    if (piosp->count == req_size)
-		break;
-	    /*
-	     * Improper size passed for freeing..
-	     * Print a message and break;
-	     */
-	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
-	    PRINT_WARNING("pcibr_piospace_free: error");
-	    PRINT_WARNING("Device %s freeing size (0x%lx) different than allocated (0x%lx)",
-					name, req_size, piosp->count);
-	    PRINT_WARNING("Freeing 0x%lx instead", piosp->count);
-	    break;
-	}
-	piosp = piosp->next;
-    }
-
-    if (!piosp) {
-	PRINT_WARNING(
-		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
-		pciaddr, req_size);
-	pcibr_unlock(pcibr_soft, s);
-	return;
-    }
-    piosp->free = 1;
-    pcibr_unlock(pcibr_soft, s);
-    return;
-}
-
-/* =====================================================================
- *    DMA MANAGEMENT
- *
- *      The Bridge ASIC provides three methods of doing
- *      DMA: via a "direct map" register available in
- *      32-bit PCI space (which selects a contiguous 2G
- *      address space on some other widget), via
- *      "direct" addressing via 64-bit PCI space (all
- *      destination information comes from the PCI
- *      address, including transfer attributes), and via
- *      a "mapped" region that allows a bunch of
- *      different small mappings to be established with
- *      the PMU.
- *
- *      For efficiency, we most prefer to use the 32-bit
- *      direct mapping facility, since it requires no
- *      resource allocations. The advantage of using the
- *      PMU over the 64-bit direct is that single-cycle
- *      PCI addressing can be used; the advantage of
- *      using 64-bit direct over PMU addressing is that
- *      we do not have to allocate entries in the PMU.
- */
-
-/*
- * Convert PCI-generic software flags and Bridge-specific software flags
- * into Bridge-specific Direct Map attribute bits.
- */
-LOCAL iopaddr_t
-pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
-{
-    iopaddr_t               attributes = 0;
-
-    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
-#ifdef LATER
-    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
-#endif
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
-	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
-	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
-    }
-    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
-	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
-	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_PREFETCH)
-	attributes |= PCI64_ATTR_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	attributes &= ~PCI64_ATTR_PREF;
-
-    /* the swap bit is in the address attributes for xbridge */
-    if (pcibr_soft->bs_xbridge) {
-    	if (flags & PCIIO_BYTE_STREAM)
-        	attributes |= PCI64_ATTR_SWAP;
-    	if (flags & PCIIO_WORD_VALUES)
-        	attributes &= ~PCI64_ATTR_SWAP;
-    }
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_BARRIER)
-	attributes |= PCI64_ATTR_BAR;
-    if (flags & PCIBR_NOBARRIER)
-	attributes &= ~PCI64_ATTR_BAR;
-
-    if (flags & PCIBR_PREFETCH)
-	attributes |= PCI64_ATTR_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	attributes &= ~PCI64_ATTR_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	attributes |= PCI64_ATTR_PREC;
-    if (flags & PCIBR_NOPRECISE)
-	attributes &= ~PCI64_ATTR_PREC;
-
-    if (flags & PCIBR_VCHAN1)
-	attributes |= PCI64_ATTR_VIRTUAL;
-    if (flags & PCIBR_VCHAN0)
-	attributes &= ~PCI64_ATTR_VIRTUAL;
-
-    return (attributes);
-}
-
-/*
- * Convert PCI-generic software flags and Bridge-specific software flags
- * into Bridge-specific Address Translation Entry attribute bits.
- */
-LOCAL bridge_ate_t
-pcibr_flags_to_ate(unsigned flags)
-{
-    bridge_ate_t            attributes;
-
-    /* default if nothing specified:
-     * NOBARRIER
-     * NOPREFETCH
-     * NOPRECISE
-     * COHERENT
-     * Plus the valid bit
-     */
-    attributes = ATE_CO | ATE_V;
-
-    /* Generic macro flags
-     */
-    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
-	attributes &= ~ATE_BAR;		/* no barrier */
-	attributes |= ATE_PREF;		/* prefetch on */
-    }
-    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
-	attributes |= ATE_BAR;		/* barrier bit on */
-	attributes &= ~ATE_PREF;	/* disable prefetch */
-    }
-    /* Generic detail flags
-     */
-    if (flags & PCIIO_PREFETCH)
-	attributes |= ATE_PREF;
-    if (flags & PCIIO_NOPREFETCH)
-	attributes &= ~ATE_PREF;
-
-    /* Provider-specific flags
-     */
-    if (flags & PCIBR_BARRIER)
-	attributes |= ATE_BAR;
-    if (flags & PCIBR_NOBARRIER)
-	attributes &= ~ATE_BAR;
-
-    if (flags & PCIBR_PREFETCH)
-	attributes |= ATE_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	attributes &= ~ATE_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	attributes |= ATE_PREC;
-    if (flags & PCIBR_NOPRECISE)
-	attributes &= ~ATE_PREC;
-
-    return (attributes);
-}
-
-/*ARGSUSED */
-pcibr_dmamap_t
-pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
-		   device_desc_t dev_desc,
-		   size_t req_size_max,
-		   unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            slot;
-    xwidgetnum_t            xio_port;
-
-    xtalk_dmamap_t          xtalk_dmamap;
-    pcibr_dmamap_t          pcibr_dmamap;
-    int                     ate_count;
-    int                     ate_index;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-#ifdef IRIX
-    NEWf(pcibr_dmamap, flags);
-#else
-    /*
-     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
-     * can be called within an interrupt thread.
-     */
-    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
-#endif
-
-    if (!pcibr_dmamap)
-	return 0;
-
-    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
-				      flags & DMAMAP_FLAGS);
-    if (!xtalk_dmamap) {
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
-#endif
-	DEL(pcibr_dmamap);
-	return 0;
-    }
-    xio_port = pcibr_soft->bs_mxid;
-    slot = pciio_info_slot_get(pciio_info);
-
-    pcibr_dmamap->bd_dev = pconn_vhdl;
-    pcibr_dmamap->bd_slot = slot;
-    pcibr_dmamap->bd_soft = pcibr_soft;
-    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
-    pcibr_dmamap->bd_max_size = req_size_max;
-    pcibr_dmamap->bd_xio_port = xio_port;
-
-    if (flags & PCIIO_DMA_A64) {
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
-	    iopaddr_t               pci_addr;
-	    int                     have_rrbs;
-	    int                     min_rrbs;
-
-	    /* Device is capable of A64 operations,
-	     * and the attributes of the DMA are
-	     * consistant with any previous DMA
-	     * mappings using shared resources.
-	     */
-
-	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
-
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_xio_addr = 0;
-	    pcibr_dmamap->bd_pci_addr = pci_addr;
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
-		if (flags & PCIBR_VCHAN1)
-		    slot += PCIBR_RRB_SLOT_VIRTUAL;
-		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
-		if (have_rrbs < 2) {
-		    if (pci_addr & PCI64_ATTR_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
-		}
-	    }
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using direct64\n");
-#endif
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use direct64\n");
-#endif
-	flags &= ~PCIIO_DMA_A64;
-    }
-    if (flags & PCIIO_FIXED) {
-	/* warning: mappings may fail later,
-	 * if direct32 can't get to the address.
-	 */
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
-	    /* User desires DIRECT A32 operations,
-	     * and the attributes of the DMA are
-	     * consistant with any previous DMA
-	     * mappings using shared resources.
-	     * Mapping calls may fail if target
-	     * is outside the direct32 range.
-	     */
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using direct32\n");
-#endif
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
-	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use direct32\n");
-#endif
-	/* If the user demands FIXED and we can't
-	 * give it to him, fail.
-	 */
-	xtalk_dmamap_free(xtalk_dmamap);
-	DEL(pcibr_dmamap);
-	return 0;
-    }
-    /*
-     * Allocate Address Translation Entries from the mapping RAM.
-     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
-     * the maximum number of ATEs is based on the worst-case
-     * scenario, where the requested target is in the
-     * last byte of an ATE; thus, mapping IOPGSIZE+2
-     * does end up requiring three ATEs.
-     */
-    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
-	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
-		     +req_size_max	/* max mapping bytes */
-		     - 1) + 1;		/* round UP */
-    } else {	/* assume requested target is page aligned */
-	ate_count = IOPG(req_size_max   /* max mapping bytes */
-		     - 1) + 1;		/* round UP */
-    }
-
-    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
-
-    if (ate_index != -1) {
-	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
-	    bridge_ate_t            ate_proto;
-	    int                     have_rrbs;
-	    int                     min_rrbs;
-
-#if PCIBR_ATE_DEBUG
-	    printk("pcibr_dmamap_alloc: using PMU\n");
-#endif
-
-	    ate_proto = pcibr_flags_to_ate(flags);
-
-	    pcibr_dmamap->bd_flags = flags;
-	    pcibr_dmamap->bd_pci_addr =
-		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
-	    /*
-	     * for xbridge the byte-swap bit == bit 29 of PCI address
-	     */
-	    if (pcibr_soft->bs_xbridge) {
-		    if (flags & PCIIO_BYTE_STREAM)
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-		    /*
-		     * If swap was set in bss_device in pcibr_endian_set()
-		     * we need to change the address bit.
-		     */
-		    if (pcibr_soft->bs_slot[slot].bss_device & 
-							BRIDGE_DEV_SWAP_PMU)
-			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
-		    if (flags & PCIIO_WORD_VALUES)
-			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
-	    }
-	    pcibr_dmamap->bd_xio_addr = 0;
-	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
-	    pcibr_dmamap->bd_ate_index = ate_index;
-	    pcibr_dmamap->bd_ate_count = ate_count;
-	    pcibr_dmamap->bd_ate_proto = ate_proto;
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
-		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
-		if (have_rrbs < 2) {
-		    if (ate_proto & ATE_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
-		}
-	    }
-	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
-				!pcibr_soft->bs_xbridge) {
-		bridge_t               *bridge = pcibr_soft->bs_base;
-		volatile unsigned      *cmd_regp;
-		unsigned                cmd_reg;
-		unsigned long           s;
-
-		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
-
-		s = pcibr_lock(pcibr_soft);
-		cmd_regp = &(bridge->
-			     b_type0_cfg_dev[slot].
-			     l[PCI_CFG_COMMAND / 4]);
-		cmd_reg = *cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
-		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
-		pcibr_unlock(pcibr_soft, s);
-	    }
-	    return pcibr_dmamap;
-	}
-#if PCIBR_ATE_DEBUG
-	printk("pcibr_dmamap_alloc: unable to use PMU\n");
-#endif
-	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
-    }
-    /* total failure: sorry, you just can't
-     * get from here to there that way.
-     */
-#if PCIBR_ATE_DEBUG
-    printk("pcibr_dmamap_alloc: complete failure.\n");
-#endif
-    xtalk_dmamap_free(xtalk_dmamap);
-    DEL(pcibr_dmamap);
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
-
-    unsigned                flags = pcibr_dmamap->bd_flags;
-
-    /* Make sure that bss_ext_ates_active
-     * is properly kept up to date.
-     */
-
-    if (PCIBR_DMAMAP_BUSY & flags)
-	if (PCIBR_DMAMAP_SSRAM & flags)
-	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
-
-    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
-
-    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
-	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
-    }
-    if (pcibr_dmamap->bd_ate_count) {
-	pcibr_ate_free(pcibr_dmamap->bd_soft,
-		       pcibr_dmamap->bd_ate_index,
-		       pcibr_dmamap->bd_ate_count);
-	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
-    }
-#ifdef IRIX
-    DEL(pcibr_dmamap);
-#endif
-}
-
-/*
- * Setup an Address Translation Entry as specified.  Use either the Bridge
- * internal maps or the external map RAM, as appropriate.
- */
-LOCAL bridge_ate_p
-pcibr_ate_addr(pcibr_soft_t pcibr_soft,
-	       int ate_index)
-{
-    bridge_t *bridge = pcibr_soft->bs_base;
-
-    return (ate_index < pcibr_soft->bs_int_ate_size)
-	? &(bridge->b_int_ate_ram[ate_index].wr)
-	: &(bridge->b_ext_ate_ram[ate_index]);
-}
-
-/*
- *    pcibr_addr_xio_to_pci: given a PIO range, hand
- *      back the corresponding base PCI MEM address;
- *      this is used to short-circuit DMA requests that
- *      loop back onto this PCI bus.
- */
-LOCAL iopaddr_t
-pcibr_addr_xio_to_pci(pcibr_soft_t soft,
-		      iopaddr_t xio_addr,
-		      size_t req_size)
-{
-    iopaddr_t               xio_lim = xio_addr + req_size - 1;
-    iopaddr_t               pci_addr;
-    pciio_slot_t            slot;
-
-    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
-	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
-	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
-	return pci_addr;
-    }
-    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
-	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
-	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
-	return pci_addr;
-    }
-    for (slot = 0; slot < 8; ++slot)
-	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
-	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
-	    bridgereg_t             dev;
-
-	    dev = soft->bs_slot[slot].bss_device;
-	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
-	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
-	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
-	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
-	}
-    return 0;
-}
-
-/* We are starting to get more complexity
- * surrounding writing ATEs, so pull
- * the writing code into this new function.
- */
-
-#if PCIBR_FREEZE_TIME
-#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
-#else
-#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
-#endif
-
-LOCAL unsigned
-ate_freeze(pcibr_dmamap_t pcibr_dmamap,
-#if PCIBR_FREEZE_TIME
-	   unsigned *freeze_time_ptr,
-#endif
-	   unsigned *cmd_regs)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-#ifdef LATER
-    int                     dma_slot = pcibr_dmamap->bd_slot;
-#endif
-    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
-    int                     slot;
-
-    unsigned long           s;
-    unsigned                cmd_reg;
-    volatile unsigned      *cmd_lwa;
-    unsigned                cmd_lwd;
-
-    if (!ext_ates)
-	return 0;
-
-    /* Bridge Hardware Bug WAR #484930:
-     * Bridge can't handle updating External ATEs
-     * while DMA is occuring that uses External ATEs,
-     * even if the particular ATEs involved are disjoint.
-     */
-
-    /* need to prevent anyone else from
-     * unfreezing the grant while we
-     * are working; also need to prevent
-     * this thread from being interrupted
-     * to keep PCI grant freeze time
-     * at an absolute minimum.
-     */
-    s = pcibr_lock(pcibr_soft);
-
-#ifdef LATER
-    /* just in case pcibr_dmamap_done was not called */
-    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
-	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
-	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
-	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
-	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
-    }
-#endif	/* LATER */
-#if PCIBR_FREEZE_TIME
-    *freeze_time_ptr = get_timestamp();
-#endif
-
-    cmd_lwa = 0;
-    for (slot = 0; slot < 8; ++slot)
-	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
-	    cmd_reg = pcibr_soft->
-		bs_slot[slot].
-		bss_cmd_shadow;
-	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
-		cmd_lwa = pcibr_soft->
-		    bs_slot[slot].
-		    bss_cmd_pointer;
-		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
-		cmd_lwa[0] = cmd_lwd;
-	    }
-	    cmd_regs[slot] = cmd_reg;
-	} else
-	    cmd_regs[slot] = 0;
-
-    if (cmd_lwa) {
-	    bridge_t	*bridge = pcibr_soft->bs_base;
-
-	    /* Read the last master bit that has been cleared. This PIO read
-	     * on the PCI bus is to ensure the completion of any DMAs that
-	     * are due to bus requests issued by PCI devices before the
-	     * clearing of master bits.
-	     */
-	    cmd_lwa[0];
-
-	    /* Flush all the write buffers in the bridge */
-	    for (slot = 0; slot < 8; ++slot)
-		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
-			    /* Flush the write buffer associated with this
-			     * PCI device which might be using dma map RAM.
-			     */
-			    bridge->b_wr_req_buf[slot].reg;
-		    }
-    }
-    return s;
-}
-
-#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
-
-LOCAL void
-ate_write(bridge_ate_p ate_ptr,
-	  int ate_count,
-	  bridge_ate_t ate)
-{
-    while (ate_count-- > 0) {
-	*ate_ptr++ = ate;
-	ate += IOPGSIZE;
-    }
-}
-
-
-#if PCIBR_FREEZE_TIME
-#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
-#else
-#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
-#endif
-
-LOCAL void
-ate_thaw(pcibr_dmamap_t pcibr_dmamap,
-	 int ate_index,
-#if PCIBR_FREEZE_TIME
-	 bridge_ate_t ate,
-	 int ate_total,
-	 unsigned freeze_time_start,
-#endif
-	 unsigned *cmd_regs,
-	 unsigned s)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
-    int                     dma_slot = pcibr_dmamap->bd_slot;
-    int                     slot;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
-
-    unsigned                cmd_reg;
-
-#if PCIBR_FREEZE_TIME
-    unsigned                freeze_time;
-    static unsigned         max_freeze_time = 0;
-    static unsigned         max_ate_total;
-#endif
-
-    if (!ext_ates)
-	return;
-
-    /* restore cmd regs */
-    for (slot = 0; slot < 8; ++slot)
-	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
-	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
-
-    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
-    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
-
-#if PCIBR_FREEZE_TIME
-    freeze_time = get_timestamp() - freeze_time_start;
-
-    if ((max_freeze_time < freeze_time) ||
-	(max_ate_total < ate_total)) {
-	if (max_freeze_time < freeze_time)
-	    max_freeze_time = freeze_time;
-	if (max_ate_total < ate_total)
-	    max_ate_total = ate_total;
-	pcibr_unlock(pcibr_soft, s);
-	printk("%s: pci freeze time %d usec for %d ATEs\n"
-		"\tfirst ate: %R\n",
-		pcibr_soft->bs_name,
-		freeze_time * 1000 / 1250,
-		ate_total,
-		ate, ate_bits);
-    } else
-#endif
-	pcibr_unlock(pcibr_soft, s);
-}
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
-		  paddr_t paddr,
-		  size_t req_size)
-{
-    pcibr_soft_t            pcibr_soft;
-    iopaddr_t               xio_addr;
-    xwidgetnum_t            xio_port;
-    iopaddr_t               pci_addr;
-    unsigned                flags;
-
-    ASSERT(pcibr_dmamap != NULL);
-    ASSERT(req_size > 0);
-    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
-
-    pcibr_soft = pcibr_dmamap->bd_soft;
-
-    flags = pcibr_dmamap->bd_flags;
-
-    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
-    if (XIO_PACKED(xio_addr)) {
-	xio_port = XIO_PORT(xio_addr);
-	xio_addr = XIO_ADDR(xio_addr);
-    } else
-	xio_port = pcibr_dmamap->bd_xio_port;
-
-    /* If this DMA is to an address that
-     * refers back to this Bridge chip,
-     * reduce it back to the correct
-     * PCI MEM address.
-     */
-    if (xio_port == pcibr_soft->bs_xid) {
-	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
-    } else if (flags & PCIIO_DMA_A64) {
-	/* A64 DMA:
-	 * always use 64-bit direct mapping,
-	 * which always works.
-	 * Device(x) was set up during
-	 * dmamap allocation.
-	 */
-
-	/* attributes are already bundled up into bd_pci_addr.
-	 */
-	pci_addr = pcibr_dmamap->bd_pci_addr
-	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
-	    | xio_addr;
-
-	/* Bridge Hardware WAR #482836:
-	 * If the transfer is not cache aligned
-	 * and the Bridge Rev is <= B, force
-	 * prefetch to be off.
-	 */
-	if (flags & PCIBR_NOPREFETCH)
-	    pci_addr &= ~PCI64_ATTR_PREF;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-	printk("pcibr_dmamap_addr (direct64):\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\tXIO port 0x%x offset 0x%x\n"
-		"\treturning PCI 0x%x\n",
-		paddr, paddr + req_size - 1,
-		xio_port, xio_addr, pci_addr);
-#endif
-    } else if (flags & PCIIO_FIXED) {
-	/* A32 direct DMA:
-	 * always use 32-bit direct mapping,
-	 * which may fail.
-	 * Device(x) was set up during
-	 * dmamap allocation.
-	 */
-
-	if (xio_port != pcibr_soft->bs_dir_xport)
-	    pci_addr = 0;		/* wrong DIDN */
-	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
-	    pci_addr = 0;		/* out of range */
-	else if ((xio_addr + req_size) >
-		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
-	    pci_addr = 0;		/* out of range */
-	else
-	    pci_addr = pcibr_dmamap->bd_pci_addr +
-		xio_addr - pcibr_dmamap->bd_xio_addr;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-	printk("pcibr_dmamap_addr (direct32):\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\tXIO port 0x%x offset 0x%x\n"
-		"\treturning PCI 0x%x\n",
-		paddr, paddr + req_size - 1,
-		xio_port, xio_addr, pci_addr);
-#endif
-    } else {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-	iopaddr_t               offset = IOPGOFF(xio_addr);
-	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
-	int                     ate_count = IOPG(offset + req_size - 1) + 1;
-
-	int                     ate_index = pcibr_dmamap->bd_ate_index;
-	unsigned                cmd_regs[8];
-	unsigned                s;
-
-#if PCIBR_FREEZE_TIME
-	int                     ate_total = ate_count;
-	unsigned                freeze_time;
-#endif
-
-#if PCIBR_ATE_DEBUG
-	bridge_ate_t            ate_cmp;
-	bridge_ate_p            ate_cptr;
-	unsigned                ate_lo, ate_hi;
-	int                     ate_bad = 0;
-	int                     ate_rbc = 0;
-#endif
-	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
-	bridge_ate_t            ate;
-
-	/* Bridge Hardware WAR #482836:
-	 * If the transfer is not cache aligned
-	 * and the Bridge Rev is <= B, force
-	 * prefetch to be off.
-	 */
-	if (flags & PCIBR_NOPREFETCH)
-	    ate_proto &= ~ATE_PREF;
-
-	ate = ate_proto
-	    | (xio_port << ATE_TIDSHIFT)
-	    | (xio_addr - offset);
-
-	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
-
-	/* Fill in our mapping registers
-	 * with the appropriate xtalk data,
-	 * and hand back the PCI address.
-	 */
-
-	ASSERT(ate_count > 0);
-	if (ate_count <= pcibr_dmamap->bd_ate_count) {
-		ATE_FREEZE();
-		ATE_WRITE();
-		ATE_THAW();
-		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	} else {
-		/* The number of ATE's required is greater than the number
-		 * allocated for this map. One way this can happen is if
-		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
-		 * flag, and then when that map is used (right now), the
-		 * target address tells us we really did need to roundup.
-		 * The other possibility is that the map is just plain too
-		 * small to handle the requested target area.
-		 */
-#if PCIBR_ATE_DEBUG
-		PRINT_WARNING( "pcibr_dmamap_addr :\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\tate_count 0x%x bd_ate_count 0x%x\n"
-			"\tATE's required > number allocated\n",
-			paddr, paddr + req_size - 1,
-			ate_count, pcibr_dmamap->bd_ate_count);
-#endif
-		pci_addr = 0;
-	}
-
-    }
-    return pci_addr;
-}
-
-/*ARGSUSED */
-alenlist_t
-pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
-		  alenlist_t palenlist,
-		  unsigned flags)
-{
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge=NULL;
-
-    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
-    int                     inplace = flags & PCIIO_INPLACE;
-
-    alenlist_t              pciio_alenlist = 0;
-    alenlist_t              xtalk_alenlist;
-    size_t                  length;
-    iopaddr_t               offset;
-    unsigned                direct64;
-    int                     ate_index = 0;
-    int                     ate_count = 0;
-    int                     ate_total = 0;
-    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
-    bridge_ate_t            ate_proto = (bridge_ate_t)0;
-    bridge_ate_t            ate_prev;
-    bridge_ate_t            ate;
-    alenaddr_t              xio_addr;
-    xwidgetnum_t            xio_port;
-    iopaddr_t               pci_addr;
-    alenaddr_t              new_addr;
-
-    unsigned                cmd_regs[8];
-    unsigned                s = 0;
-
-#if PCIBR_FREEZE_TIME
-    unsigned                freeze_time;
-#endif
-    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
-							 * with an ATE_FREEZE
-							 */
-
-    pcibr_soft = pcibr_dmamap->bd_soft;
-
-    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
-				       flags & DMAMAP_FLAGS);
-    if (!xtalk_alenlist)
-	goto fail;
-
-    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
-
-    if (inplace) {
-	pciio_alenlist = xtalk_alenlist;
-    } else {
-	pciio_alenlist = alenlist_create(al_flags);
-	if (!pciio_alenlist)
-	    goto fail;
-    }
-
-    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
-    if (!direct64) {
-	bridge = pcibr_soft->bs_base;
-	ate_ptr = pcibr_dmamap->bd_ate_ptr;
-	ate_index = pcibr_dmamap->bd_ate_index;
-	ate_proto = pcibr_dmamap->bd_ate_proto;
-	ATE_FREEZE();
-	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
-    }
-    pci_addr = pcibr_dmamap->bd_pci_addr;
-
-    ate_prev = 0;			/* matches no valid ATEs */
-    while (ALENLIST_SUCCESS ==
-	   alenlist_get(xtalk_alenlist, NULL, 0,
-			&xio_addr, &length, al_flags)) {
-	if (XIO_PACKED(xio_addr)) {
-	    xio_port = XIO_PORT(xio_addr);
-	    xio_addr = XIO_ADDR(xio_addr);
-	} else
-	    xio_port = pcibr_dmamap->bd_xio_port;
-
-	if (xio_port == pcibr_soft->bs_xid) {
-	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
-	    if (new_addr == PCI_NOWHERE)
-		goto fail;
-	} else if (direct64) {
-	    new_addr = pci_addr | xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-	    /* Bridge Hardware WAR #482836:
-	     * If the transfer is not cache aligned
-	     * and the Bridge Rev is <= B, force
-	     * prefetch to be off.
-	     */
-	    if (flags & PCIBR_NOPREFETCH)
-		new_addr &= ~PCI64_ATTR_PREF;
-
-	} else {
-	    /* calculate the ate value for
-	     * the first address. If it
-	     * matches the previous
-	     * ATE written (ie. we had
-	     * multiple blocks in the
-	     * same IOPG), then back up
-	     * and reuse that ATE.
-	     *
-	     * We are NOT going to
-	     * aggressively try to
-	     * reuse any other ATEs.
-	     */
-	    offset = IOPGOFF(xio_addr);
-	    ate = ate_proto
-		| (xio_port << ATE_TIDSHIFT)
-		| (xio_addr - offset);
-	    if (ate == ate_prev) {
-#if PCIBR_ATE_DEBUG
-		printk("pcibr_dmamap_list: ATE share\n");
-#endif
-		ate_ptr--;
-		ate_index--;
-		pci_addr -= IOPGSIZE;
-	    }
-	    new_addr = pci_addr + offset;
-
-	    /* Fill in the hardware ATEs
-	     * that contain this block.
-	     */
-	    ate_count = IOPG(offset + length - 1) + 1;
-	    ate_total += ate_count;
-
-	    /* Ensure that this map contains enough ATE's */
-	    if (ate_total > pcibr_dmamap->bd_ate_count) {
-#if PCIBR_ATE_DEBUG
-		PRINT_WARNING( "pcibr_dmamap_list :\n"
-			"\twanted xio_addr [0x%x..0x%x]\n"
-			"\tate_total 0x%x bd_ate_count 0x%x\n"
-			"\tATE's required > number allocated\n",
-			xio_addr, xio_addr + length - 1,
-			ate_total, pcibr_dmamap->bd_ate_count);
-#endif
-		goto fail;
-	    }
-
-	    ATE_WRITE();
-
-	    ate_index += ate_count;
-	    ate_ptr += ate_count;
-
-	    ate_count <<= IOPFNSHIFT;
-	    ate += ate_count;
-	    pci_addr += ate_count;
-	}
-
-	/* write the PCI DMA address
-	 * out to the scatter-gather list.
-	 */
-	if (inplace) {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_replace(pciio_alenlist, NULL,
-				 &new_addr, &length, al_flags))
-		goto fail;
-	} else {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_append(pciio_alenlist,
-				new_addr, length, al_flags))
-		goto fail;
-	}
-    }
-    if (!inplace)
-	alenlist_done(xtalk_alenlist);
-
-    /* Reset the internal cursor of the alenlist to be returned back
-     * to the caller.
-     */
-    alenlist_cursor_init(pciio_alenlist, 0, NULL);
-
-
-    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
-     * changes that ATE_FREEZE has done to implement the external SSRAM
-     * bug workaround.
-     */
-    if (ate_freeze_done) {
-	ATE_THAW();
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    return pciio_alenlist;
-
-  fail:
-    /* There are various points of failure after doing an ATE_FREEZE
-     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
-     * The decision to do an ATE_THAW needs to be based on whether a
-     * an ATE_FREEZE was done before.
-     */
-    if (ate_freeze_done) {
-	ATE_THAW();
-	bridge->b_wid_tflush;
-    }
-    if (pciio_alenlist && !inplace)
-	alenlist_destroy(pciio_alenlist);
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
-{
-    /*
-     * We could go through and invalidate ATEs here;
-     * for performance reasons, we don't.
-     * We also don't enforce the strict alternation
-     * between _addr/_list and _done, but Hub does.
-     */
-
-    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
-	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
-
-	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
-	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
-    }
-
-    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
-}
-
-
-/*
- * For each bridge, the DIR_OFF value in the Direct Mapping Register
- * determines the PCI to Crosstalk memory mapping to be used for all
- * 32-bit Direct Mapping memory accesses. This mapping can be to any
- * node in the system. This function will return that compact node id.
- */
-
-/*ARGSUSED */
-cnodeid_t
-pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
-{
-
-	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
-	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
-}
-
-/*ARGSUSED */
-iopaddr_t
-pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    paddr_t paddr,
-		    size_t req_size,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
-
-    xwidgetnum_t            xio_port;
-    iopaddr_t               xio_addr;
-    iopaddr_t               pci_addr;
-
-    int                     have_rrbs;
-    int                     min_rrbs;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
-				   flags & DMAMAP_FLAGS);
-
-    if (!xio_addr) {
-#if PCIBR_DMA_DEBUG
-	printk("pcibr_dmatrans_addr:\n"
-		"\tpciio connection point %v\n"
-		"\txtalk connection point %v\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\txtalk_dmatrans_addr returned 0x%x\n",
-		pconn_vhdl, xconn_vhdl,
-		paddr, paddr + req_size - 1,
-		xio_addr);
-#endif
-	return 0;
-    }
-    /*
-     * find which XIO port this goes to.
-     */
-    if (XIO_PACKED(xio_addr)) {
-	if (xio_addr == XIO_NOWHERE) {
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	    return 0;
-	}
-	xio_port = XIO_PORT(xio_addr);
-	xio_addr = XIO_ADDR(xio_addr);
-
-    } else
-	xio_port = pcibr_soft->bs_mxid;
-
-    /*
-     * If this DMA comes back to us,
-     * return the PCI MEM address on
-     * which it would land, or NULL
-     * if the target is something
-     * on bridge other than PCI MEM.
-     */
-    if (xio_port == pcibr_soft->bs_xid) {
-	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
-	return pci_addr;
-    }
-    /* If the caller can use A64, try to
-     * satisfy the request with the 64-bit
-     * direct map. This can fail if the
-     * configuration bits in Device(x)
-     * conflict with our flags.
-     */
-
-    if (flags & PCIIO_DMA_A64) {
-	pci_addr = slotp->bss_d64_base;
-	if (!(flags & PCIBR_VCHAN1))
-	    flags |= PCIBR_VCHAN0;
-	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
-	    (flags == slotp->bss_d64_flags)) {
-
-	    pci_addr |= xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-#if DEBUG && PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-	    if (xio_addr != 0x20000000)
-#endif
-		printk("pcibr_dmatrans_addr: [reuse]\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tdirect 64bit address is 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, pci_addr);
-#endif
-	    return (pci_addr);
-	}
-	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
-	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
-	    slotp->bss_d64_flags = flags;
-	    slotp->bss_d64_base = pci_addr;
-	    pci_addr |= xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-
-	    /* Make sure we have an RRB (or two).
-	     */
-	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
-		if (flags & PCIBR_VCHAN1)
-		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
-		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
-		if (have_rrbs < 2) {
-		    if (pci_addr & PCI64_ATTR_PREF)
-			min_rrbs = 2;
-		    else
-			min_rrbs = 1;
-		    if (have_rrbs < min_rrbs)
-			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
-		}
-	    }
-#if PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-	    if (xio_addr != 0x20000000)
-#endif
-		printk("pcibr_dmatrans_addr:\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tdirect 64bit address is 0x%x\n"
-			"\tnew flags: 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, pci_addr, (uint64_t) flags);
-#endif
-	    return (pci_addr);
-	}
-	/* our flags conflict with Device(x).
-	 */
-	flags = flags
-	    & ~PCIIO_DMA_A64
-	    & ~PCIBR_VCHAN0
-	    ;
-
-#if PCIBR_DMA_DEBUG
-	printk("pcibr_dmatrans_addr:\n"
-		"\tpciio connection point %v\n"
-		"\txtalk connection point %v\n"
-		"\twanted paddr [0x%x..0x%x]\n"
-		"\txtalk_dmatrans_addr returned 0x%x\n"
-		"\tUnable to set Device(x) bits for Direct-64\n",
-		pconn_vhdl, xconn_vhdl,
-		paddr, paddr + req_size - 1,
-		xio_addr);
-#endif
-    }
-    /* Try to satisfy the request with the 32-bit direct
-     * map. This can fail if the configuration bits in
-     * Device(x) conflict with our flags, or if the
-     * target address is outside where DIR_OFF points.
-     */
-    {
-	size_t                  map_size = 1ULL << 31;
-	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
-	iopaddr_t               offset = xio_addr - xio_base;
-	iopaddr_t               endoff = req_size + offset;
-
-	if ((req_size > map_size) ||
-	    (xio_addr < xio_base) ||
-	    (xio_port != pcibr_soft->bs_dir_xport) ||
-	    (endoff > map_size)) {
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n"
-		    "\txio region outside direct32 target\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	} else {
-	    pci_addr = slotp->bss_d32_base;
-	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
-		(flags == slotp->bss_d32_flags)) {
-
-		pci_addr |= offset;
-
-#if DEBUG && PCIBR_DMA_DEBUG
-		printk("pcibr_dmatrans_addr: [reuse]\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n"
-			"\tmapped via direct32 offset 0x%x\n"
-			"\twill DMA via pci addr 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr, offset, pci_addr);
-#endif
-		return (pci_addr);
-	    }
-	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
-
-		pci_addr = PCI32_DIRECT_BASE;
-		slotp->bss_d32_flags = flags;
-		slotp->bss_d32_base = pci_addr;
-		pci_addr |= offset;
-
-		/* Make sure we have an RRB (or two).
-		 */
-		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
-		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
-		    if (have_rrbs < 2) {
-			if (slotp->bss_device & BRIDGE_DEV_PREF)
-			    min_rrbs = 2;
-			else
-			    min_rrbs = 1;
-			if (have_rrbs < min_rrbs)
-			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
-		    }
-		}
-#if PCIBR_DMA_DEBUG
-#if HWG_PERF_CHECK
-		if (xio_addr != 0x20000000)
-#endif
-		    printk("pcibr_dmatrans_addr:\n"
-			    "\tpciio connection point %v\n"
-			    "\txtalk connection point %v\n"
-			    "\twanted paddr [0x%x..0x%x]\n"
-			    "\txtalk_dmatrans_addr returned 0x%x\n"
-			    "\tmapped via direct32 offset 0x%x\n"
-			    "\twill DMA via pci addr 0x%x\n"
-			    "\tnew flags: 0x%x\n",
-			    pconn_vhdl, xconn_vhdl,
-			    paddr, paddr + req_size - 1,
-			    xio_addr, offset, pci_addr, (uint64_t) flags);
-#endif
-		return (pci_addr);
-	    }
-	    /* our flags conflict with Device(x).
-	     */
-#if PCIBR_DMA_DEBUG
-	    printk("pcibr_dmatrans_addr:\n"
-		    "\tpciio connection point %v\n"
-		    "\txtalk connection point %v\n"
-		    "\twanted paddr [0x%x..0x%x]\n"
-		    "\txtalk_dmatrans_addr returned 0x%x\n"
-		    "\tUnable to set Device(x) bits for Direct-32\n",
-		    pconn_vhdl, xconn_vhdl,
-		    paddr, paddr + req_size - 1,
-		    xio_addr);
-#endif
-	}
-    }
-
-#if PCIBR_DMA_DEBUG
-    printk("pcibr_dmatrans_addr:\n"
-	    "\tpciio connection point %v\n"
-	    "\txtalk connection point %v\n"
-	    "\twanted paddr [0x%x..0x%x]\n"
-	    "\txtalk_dmatrans_addr returned 0x%x\n"
-	    "\tno acceptable PCI address found or constructable\n",
-	    pconn_vhdl, xconn_vhdl,
-	    paddr, paddr + req_size - 1,
-	    xio_addr);
-#endif
-
-    return 0;
-}
-
-/*ARGSUSED */
-alenlist_t
-pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
-		    device_desc_t dev_desc,
-		    alenlist_t palenlist,
-		    unsigned flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
-    xwidgetnum_t            xio_port;
-
-    alenlist_t              pciio_alenlist = 0;
-    alenlist_t              xtalk_alenlist = 0;
-
-    int                     inplace;
-    unsigned                direct64;
-    unsigned                al_flags;
-
-    iopaddr_t               xio_base;
-    alenaddr_t              xio_addr;
-    size_t                  xio_size;
-
-    size_t                  map_size;
-    iopaddr_t               pci_base;
-    alenaddr_t              pci_addr;
-
-    unsigned                relbits = 0;
-
-    /* merge in forced flags */
-    flags |= pcibr_soft->bs_dma_flags;
-
-    inplace = flags & PCIIO_INPLACE;
-    direct64 = flags & PCIIO_DMA_A64;
-    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
-
-    if (direct64) {
-	map_size = 1ull << 48;
-	xio_base = 0;
-	pci_base = slotp->bss_d64_base;
-	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
-	    (flags == slotp->bss_d64_flags)) {
-	    /* reuse previous base info */
-	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
-	    /* DMA configuration conflict */
-	    goto fail;
-	} else {
-	    relbits = BRIDGE_DEV_D64_BITS;
-	    pci_base =
-		pcibr_flags_to_d64(flags, pcibr_soft);
-	}
-    } else {
-	xio_base = pcibr_soft->bs_dir_xbase;
-	map_size = 1ull << 31;
-	pci_base = slotp->bss_d32_base;
-	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
-	    (flags == slotp->bss_d32_flags)) {
-	    /* reuse previous base info */
-	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
-	    /* DMA configuration conflict */
-	    goto fail;
-	} else {
-	    relbits = BRIDGE_DEV_D32_BITS;
-	    pci_base = PCI32_DIRECT_BASE;
-	}
-    }
-
-    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
-					 flags & DMAMAP_FLAGS);
-    if (!xtalk_alenlist)
-	goto fail;
-
-    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
-
-    if (inplace) {
-	pciio_alenlist = xtalk_alenlist;
-    } else {
-	pciio_alenlist = alenlist_create(al_flags);
-	if (!pciio_alenlist)
-	    goto fail;
-    }
-
-    while (ALENLIST_SUCCESS ==
-	   alenlist_get(xtalk_alenlist, NULL, 0,
-			&xio_addr, &xio_size, al_flags)) {
-
-	/*
-	 * find which XIO port this goes to.
-	 */
-	if (XIO_PACKED(xio_addr)) {
-	    if (xio_addr == XIO_NOWHERE) {
-#if PCIBR_DMA_DEBUG
-		printk("pcibr_dmatrans_addr:\n"
-			"\tpciio connection point %v\n"
-			"\txtalk connection point %v\n"
-			"\twanted paddr [0x%x..0x%x]\n"
-			"\txtalk_dmatrans_addr returned 0x%x\n",
-			pconn_vhdl, xconn_vhdl,
-			paddr, paddr + req_size - 1,
-			xio_addr);
-#endif
-		return 0;
-	    }
-	    xio_port = XIO_PORT(xio_addr);
-	    xio_addr = XIO_ADDR(xio_addr);
-	} else
-	    xio_port = pcibr_soft->bs_mxid;
-
-	/*
-	 * If this DMA comes back to us,
-	 * return the PCI MEM address on
-	 * which it would land, or NULL
-	 * if the target is something
-	 * on bridge other than PCI MEM.
-	 */
-	if (xio_port == pcibr_soft->bs_xid) {
-	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
-	    if ( (pci_addr == (alenaddr_t)NULL) )
-		goto fail;
-	} else if (direct64) {
-	    ASSERT(xio_port != 0);
-	    pci_addr = pci_base | xio_addr
-		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
-	} else {
-	    iopaddr_t               offset = xio_addr - xio_base;
-	    iopaddr_t               endoff = xio_size + offset;
-
-	    if ((xio_size > map_size) ||
-		(xio_addr < xio_base) ||
-		(xio_port != pcibr_soft->bs_dir_xport) ||
-		(endoff > map_size))
-		goto fail;
-
-	    pci_addr = pci_base + (xio_addr - xio_base);
-	}
-
-	/* write the PCI DMA address
-	 * out to the scatter-gather list.
-	 */
-	if (inplace) {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_replace(pciio_alenlist, NULL,
-				 &pci_addr, &xio_size, al_flags))
-		goto fail;
-	} else {
-	    if (ALENLIST_SUCCESS !=
-		alenlist_append(pciio_alenlist,
-				pci_addr, xio_size, al_flags))
-		goto fail;
-	}
-    }
-
-    if (relbits) {
-	if (direct64) {
-	    slotp->bss_d64_flags = flags;
-	    slotp->bss_d64_base = pci_base;
-	} else {
-	    slotp->bss_d32_flags = flags;
-	    slotp->bss_d32_base = pci_base;
-	}
-    }
-    if (!inplace)
-	alenlist_done(xtalk_alenlist);
-
-    /* Reset the internal cursor of the alenlist to be returned back
-     * to the caller.
-     */
-    alenlist_cursor_init(pciio_alenlist, 0, NULL);
-    return pciio_alenlist;
-
-  fail:
-    if (relbits)
-	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
-    if (pciio_alenlist && !inplace)
-	alenlist_destroy(pciio_alenlist);
-    return 0;
-}
-
-void
-pcibr_dmamap_drain(pcibr_dmamap_t map)
-{
-    xtalk_dmamap_drain(map->bd_xtalk);
-}
-
-void
-pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
-		    paddr_t paddr,
-		    size_t bytes)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
-}
-
-void
-pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
-		    alenlist_t list)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-
-    xtalk_dmalist_drain(xconn_vhdl, list);
-}
-
-/*
- * Get the starting PCIbus address out of the given DMA map.
- * This function is supposed to be used by a close friend of PCI bridge
- * since it relies on the fact that the starting address of the map is fixed at
- * the allocation time in the current implementation of PCI bridge.
- */
-iopaddr_t
-pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
-{
-    return (pcibr_dmamap->bd_pci_addr);
-}
-
-/* =====================================================================
- *    INTERRUPT MANAGEMENT
- */
-
-static unsigned
-pcibr_intr_bits(pciio_info_t info,
-		pciio_intr_line_t lines)
-{
-    pciio_slot_t            slot = pciio_info_slot_get(info);
-    unsigned		    bbits = 0;
-
-    /*
-     * Currently favored mapping from PCI
-     * slot number and INTA/B/C/D to Bridge
-     * PCI Interrupt Bit Number:
-     *
-     *     SLOT     A B C D
-     *      0       0 4 0 4
-     *      1       1 5 1 5
-     *      2       2 6 2 6
-     *      3       3 7 3 7
-     *      4       4 0 4 0
-     *      5       5 1 5 1
-     *      6       6 2 6 2
-     *      7       7 3 7 3
-     */
-
-    if (slot < 8) {
-	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
-	    bbits |= 1 << slot;
-	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
-	    bbits |= 1 << (slot ^ 4);
-    }
-    return bbits;
-}
-
-
-/*
- *	Get the next wrapper pointer queued in the interrupt circular buffer.
- */
-#ifdef KERNEL_THREADS
-pcibr_intr_wrap_t
-pcibr_wrap_get(pcibr_intr_cbuf_t cbuf)
-{
-    pcibr_intr_wrap_t	wrap;
-
-	if (cbuf->ib_in == cbuf->ib_out)
-	    PRINT_PANIC("pcibr intr circular buffer empty, cbuf=0x%x, ib_in=ib_out=%d\n",
-		cbuf, cbuf->ib_out);
-
-	wrap = cbuf->ib_cbuf[cbuf->ib_out++];
-	cbuf->ib_out = cbuf->ib_out % IBUFSIZE;
-	return(wrap);
-}
-
-/* 
- *	Queue a wrapper pointer in the interrupt circular buffer.
- */
-void
-pcibr_wrap_put(pcibr_intr_wrap_t wrap, pcibr_intr_cbuf_t cbuf)
-{
-	int	in;
-	unsigned long	s;
-
-	/*
-	 * Multiple CPUs could be executing this code simultaneously
-	 * if a handler has registered multiple interrupt lines and
-	 * the interrupts are directed to different CPUs.
-	 */
-	s = mutex_spinlock(&cbuf->ib_lock);
-	in = (cbuf->ib_in + 1) % IBUFSIZE;
-	if (in == cbuf->ib_out) 
-	    PRINT_PANIC("pcibr intr circular buffer full, cbuf=0x%x, ib_in=%d\n",
-		cbuf, cbuf->ib_in);
-
-	cbuf->ib_cbuf[cbuf->ib_in] = wrap;
-	cbuf->ib_in = in;
-	mutex_spinunlock(&cbuf->ib_lock, s);
-	return;
-}
-#endif	/* KERNEL_THREADS */
-
-/*
- *	There are end cases where a deadlock can occur if interrupt 
- *	processing completes and the Bridge b_int_status bit is still set.
- *
- *	One scenerio is if a second PCI interrupt occurs within 60ns of
- *	the previous interrupt being cleared. In this case the Bridge
- *	does not detect the transition, the Bridge b_int_status bit
- *	remains set, and because no transition was detected no interrupt
- *	packet is sent to the Hub/Heart.
- *
- *	A second scenerio is possible when a b_int_status bit is being
- *	shared by multiple devices:
- *						Device #1 generates interrupt
- *						Bridge b_int_status bit set
- *						Device #2 generates interrupt
- *		interrupt processing begins
- *		  ISR for device #1 runs and
- *			clears interrupt
- *						Device #1 generates interrupt
- *		  ISR for device #2 runs and
- *			clears interrupt
- *						(b_int_status bit still set)
- *		interrupt processing completes
- *		  
- *	Interrupt processing is now complete, but an interrupt is still
- *	outstanding for Device #1. But because there was no transition of
- *	the b_int_status bit, no interrupt packet will be generated and
- *	a deadlock will occur.
- *
- *	To avoid these deadlock situations, this function is used
- *	to check if a specific Bridge b_int_status bit is set, and if so,
- *	cause the setting of the corresponding interrupt bit.
- *
- *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
- *	Interrupt register.
- */
-void
-pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
-{
-	unsigned	bit;
-	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
-	bridge_t       *bridge = pcibr_soft->bs_base;
-	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
-
-	bit = wrap->iw_intr;
-
-	if (pcibr_soft->bs_xbridge) {
-	    bridge->b_force_pin[bit].intr = 1;
-	} else if ((1 << bit) & *wrap->iw_stat) {
-	    cpuid_t	    cpu;
-	    unsigned        intr_bit;
-	    xtalk_intr_t    xtalk_intr =
-				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
-
-	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
-	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
-	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
-	}
-}
-
-/* Wrapper for pcibr interrupt threads. */
-#ifdef KERNEL_THREADS
-static void
-pcibr_intrd(pcibr_intr_t intr)
-{
-    pcibr_intr_wrap_t	wrap;
-
-	/* Called on each restart */
-	ASSERT(cpuid() == intr->bi_mustruncpu);
-
-#ifdef ITHREAD_LATENCY
-	xthread_update_latstats(intr->bi_tinfo.thd_latstats);
-#endif /* ITHREAD_LATENCY */
-
-	ASSERT(intr->bi_func != NULL);
-	intr->bi_func(intr->bi_arg);		/* Invoke the interrupt handler */
-
-	/*
-	 * The pcibr_intrd thread needs access to the wrapper struct
-	 * specific to the current interrupt it is processing. Because
-	 * multiple calls/wakeups to the thread could be queued, each
-	 * potentially from a different interrupt line (PCIIO_INTR_LINE_A,
-	 * etc), multiple wrapper struct pointers need to be queued. This 
-	 * is done via a circular buffer of wrapper struct pointers. 
-	 */
-	wrap = pcibr_wrap_get(&intr->bi_ibuf);
-
-	/* 
-	 * The interrupt handler has completed. Now decrement the running
-	 * count tracking the number of handlers still running for this line.
-	 * If this was the last handler to complete (i.e., iw_hdlrcnt == 0),
-	 * avoid a potential deadlock condition and ensure that another
-	 * interrupt will occur if the Bridge b_int_status bit is still
-	 * set. 
-	 */
-	atomicAddInt(&(wrap->iw_hdlrcnt), -1);
-	if (wrap->iw_hdlrcnt == 0)
-		pcibr_force_interrupt(wrap);
-
-	ipsema(&intr->bi_tinfo.thd_isync);	/* Sleep 'till next interrupt */
-	/* NOTREACHED */
-}
-
-static void
-pcibr_intrd_start(pcibr_intr_t intr)
-{
-	ASSERT(intr->bi_mustruncpu >= 0);
-	setmustrun(intr->bi_mustruncpu);
-
-	xthread_set_func(KT_TO_XT(curthreadp), (xt_func_t *)pcibr_intrd, (void *)intr);
-	atomicSetInt(&intr->bi_tinfo.thd_flags, THD_INIT);
-	ipsema(&intr->bi_tinfo.thd_isync);  /* Comes out in pcibr_intrd */
-	/* NOTREACHED */
-}
-
-
-static void
-pcibr_thread_setup(pcibr_intr_t intr, int bridge_levels, ilvl_t intr_swlevel)
-{
-	char thread_name[32];
-
-	sprintf(thread_name, "pcibr_intrd[0x%x]", bridge_levels);
-	thread_name[IT_NAMELEN-1] = '\0';
-
-	/* XXX need to adjust priority whenever an interrupt is connected */
-	intr->bi_tinfo.thd_pri = intr_swlevel;
-	atomicSetInt(&intr->bi_tinfo.thd_flags, THD_ISTHREAD | THD_REG);
-	xthread_setup(thread_name, intr_swlevel, &intr->bi_tinfo,
-			(xt_func_t *)pcibr_intrd_start,
-			(void *)intr);
-}
-#endif	/* KERNEL_THREADS */
-
-
-
-/*ARGSUSED */
-pcibr_intr_t
-pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
-		 device_desc_t dev_desc,
-		 pciio_intr_line_t lines,
-		 devfs_handle_t owner_dev)
-{
-    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    int                     is_threaded = 0;
-#ifdef KERNEL_THREADS
-    cpuid_t		    mustruncpu = CPU_NONE;
-    cpuid_t		    old_intrcpu = CPU_NONE;
-#endif
-    int                     thread_swlevel;
-
-    xtalk_intr_t           *xtalk_intr_p;
-    pcibr_intr_t           *pcibr_intr_p;
-    pcibr_intr_list_t      *intr_list_p;
-
-    unsigned                pcibr_int_bits;
-    unsigned                pcibr_int_bit;
-    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
-    hub_intr_t		    hub_intr;
-    pcibr_intr_t            pcibr_intr;
-    pcibr_intr_list_t       intr_entry;
-    pcibr_intr_list_t       intr_list;
-    bridgereg_t             int_dev;
-
-#if DEBUG && INTR_DEBUG
-    printk("%v: pcibr_intr_alloc\n"
-	    "%v:%s%s%s%s%s\n",
-	    owner_dev, pconn_vhdl,
-	    !(lines & 15) ? " No INTs?" : "",
-	    lines & 1 ? " INTA" : "",
-	    lines & 2 ? " INTB" : "",
-	    lines & 4 ? " INTC" : "",
-	    lines & 8 ? " INTD" : "");
-#endif
-
-    NEW(pcibr_intr);
-    if (!pcibr_intr)
-	return NULL;
-
-    if (dev_desc) {
-	cpuid_t intr_target_from_desc(device_desc_t, int);
-
-#ifdef KERNEL_THREADS
-	is_threaded = !(device_desc_flags_get(dev_desc) & D_INTR_NOTHREAD);
-	if (is_threaded) {
-	    /*
-	     * If the device descriptor contains interrupt target info,
-	     * save the CPU requested. This is the CPU the pcibr_intrd
-	     * thread will be set to run on. 
-	     *
-	     * We need to get the interrupt target info at this time, because
-	     * the original intr_target value can be overwritten, as part of
-	     * the xtalk_intr_alloc_nothd() call, with the actual interrupt CPU.
-	     * This can be different than the requested CPU if the lower layers
-	     * could not direct the hardware interrupt to the requested CPU. 
-	     * Regardless of which CPU processes the hardware interrupt, the 
-	     * ISR thread will still be setup to run on the CPU originally 
-	     * requested.
-	     */
-		mustruncpu = intr_target_from_desc(dev_desc, SUBNODE_ANY);
-		thread_swlevel = device_desc_intr_swlevel_get(dev_desc);
-	}
-#endif	/* KERNEL_THREADS */
-    } else {
-	extern int default_intr_pri;
-
-	is_threaded = 1; /* PCI interrupts are threaded, by default */
-	thread_swlevel = default_intr_pri;
-    }
-
-    pcibr_intr->bi_dev = pconn_vhdl;
-    pcibr_intr->bi_lines = lines;
-    pcibr_intr->bi_soft = pcibr_soft;
-    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
-    pcibr_intr->bi_func = 0;		/* unset until connect */
-    pcibr_intr->bi_arg = 0;		/* unset until connect */
-    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
-    pcibr_intr->bi_mustruncpu = CPU_NONE;
-#ifdef KERNEL_THREADS
-    pcibr_intr->bi_ibuf.ib_in = 0;
-    pcibr_intr->bi_ibuf.ib_out = 0;
-#endif
-    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
-
-    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
-
-
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and make sure there are xtalk resources
-     * allocated for it.
-     */
-#if DEBUG && INTR_DEBUG
-    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
-#endif 
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    xtalk_intr = *xtalk_intr_p;
-
-	    if (xtalk_intr == NULL) {
-		/*
-		 * This xtalk_intr_alloc is constrained for two reasons:
-		 * 1) Normal interrupts and error interrupts need to be delivered
-		 *    through a single xtalk target widget so that there aren't any
-		 *    ordering problems with DMA, completion interrupts, and error
-		 *    interrupts. (Use of xconn_vhdl forces this.)
-		 *
-		 * 2) On IP35, addressing constraints on IP35 and Bridge force
-		 *    us to use a single PI number for all interrupts from a
-		 *    single Bridge. (IP35-specific code forces this, and we
-		 *    verify in pcibr_setwidint.)
-		 */
-
-		/*
-		 * All code dealing with threaded PCI interrupt handlers
-		 * is located at the pcibr level. Because of this,
-		 * we always want the lower layers (hub/heart_intr_alloc, 
-		 * intr_level_connect) to treat us as non-threaded so we
-		 * don't set up a duplicate threaded environment. We make
-		 * this happen by calling a special xtalk interface.
-		 */
-		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
-			owner_dev);
-#if DEBUG && INTR_DEBUG
-		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
-#endif
-
-		/* both an assert and a runtime check on this:
-		 * we need to check in non-DEBUG kernels, and
-		 * the ASSERT gets us more information when
-		 * we use DEBUG kernels.
-		 */
-		ASSERT(xtalk_intr != NULL);
-		if (xtalk_intr == NULL) {
-		    /* it is quite possible that our
-		     * xtalk_intr_alloc failed because
-		     * someone else got there first,
-		     * and we can find their results
-		     * in xtalk_intr_p.
-		     */
-		    if (!*xtalk_intr_p) {
-#ifdef SUPPORT_PRINTING_V_FORMAT
-			PRINT_ALERT(
-				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
-				xconn_vhdl);
-#endif
-			/* yes, we leak resources here. */
-			return 0;
-		    }
-		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
-		    /*
-		     * now tell the bridge which slot is
-		     * using this interrupt line.
-		     */
-		    int_dev = bridge->b_int_device;
-		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
-		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
-		    bridge->b_int_device = int_dev;	/* XXXMP */
-
-#if DEBUG && INTR_DEBUG
-		    printk("%v: bridge intr bit %d clears my wrb\n",
-			    pconn_vhdl, pcibr_int_bit);
-#endif
-		} else {
-		    /* someone else got one allocated first;
-		     * free the one we just created, and
-		     * retrieve the one they allocated.
-		     */
-		    xtalk_intr_free(xtalk_intr);
-		    xtalk_intr = *xtalk_intr_p;
-#if PARANOID
-		    /* once xtalk_intr is set, we never clear it,
-		     * so if the CAS fails above, this condition
-		     * can "never happen" ...
-		     */
-		    if (!xtalk_intr) {
-			PRINT_ALERT(
-				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
-				xconn_vhdl);
-			/* yes, we leak resources here. */
-			return 0;
-		    }
-#endif
-		}
-	    }
-
-#ifdef KERNEL_THREADS
-	    if (is_threaded) {
-		cpuid_t intrcpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
-
-		/*
-		 * It is possible that 2 (or more) interrupts originating on a
-		 * single Bridge and used by a single device were assigned to
-		 * different CPUs. If this occurs issue a warning message for
-		 * this sub-optimal configuration. There are two ways this 
-		 * could happen:
-		 *
-		 *  - There were insufficient xtalk interrupt resources to
-		 *    allow all interrupts to be assigned to the same CPU.
-		 *    This is an unlikely case, but could happen if someone
-		 *    tries to target a lot of interrupts to a single CPU.
-		 *
-		 * - If there is no device descriptor associated with this
-		 *   device, the xtalk/hub/heart layers will not know to
-		 *   assign the same CPU to any additional interrupts this
-		 *   driver has specified, and will perform the normal load
-		 *   leveling of interrupts across CPUs.
-		 *   (The lower layers store the CPU assigned to the first
-		 *   interrupt in the device desc, if present, and then when
-		 *   called again for additional interrupts for the same device,
-		 *   use this information to assign the same CPU to these
-		 *   interrupts.)
-		 */
-		if ((old_intrcpu != CPU_NONE) && (old_intrcpu != intrcpu)) {
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-			PRINT_WARNING("Conflict on where to schedule interrupts for %v\n", pconn_vhdl);
-#else
-			PRINT_WARNING("Conflict on where to schedule interrupts for 0x%x\n", pconn_vhdl);
-#endif
-			PRINT_WARNING("(on cpu %d or on cpu %d), cpu %d used\n", old_intrcpu, intrcpu, intrcpu);
-		}
-		if (old_intrcpu == CPU_NONE)
-			old_intrcpu = intrcpu;
-	    /*
-	     * For threaded drivers, set the interrupt thread to run wherever
-	     * the interrupt is targeted, or where requested in the dev_desc.
-	     */
-		if (mustruncpu != CPU_NONE) {
-			pcibr_intr->bi_mustruncpu = mustruncpu;
-			if (mustruncpu != intrcpu) {
-				PRINT_WARNING("Request to target PCI interrupts to CPU %d could not\n"
-                		"      be satisfied, CPU %d used. However, interrupt thread\n"
-                		"      pcibr_intrd will run on CPU %d as requested.\n"
-                		"      %v (0x%x)\n",
-                		mustruncpu, intrcpu, mustruncpu, owner_dev,
-				owner_dev);
-			}
-		} else {
-			pcibr_intr->bi_mustruncpu = intrcpu;
-		}
-		ASSERT(pcibr_intr->bi_mustruncpu >= 0);
-
-	    }
-#endif	/* KERNEL_THREADS */
-
-	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
-
-	    NEW(intr_entry);
-	    intr_entry->il_next = NULL;
-	    intr_entry->il_intr = pcibr_intr;
-	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
-	    intr_list_p = 
-		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
-#if DEBUG && INTR_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
-		pconn_vhdl, pcibr_int_bit,
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
-#else
-	    printk("%v: Bridge bit %d wrap=0x%x\n",
-		pconn_vhdl, pcibr_int_bit,
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
-#endif
-#endif
-
-	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		/* we are the first interrupt on this bridge bit.
-		 */
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    intr_list = *intr_list_p;
-	    pcibr_intr_p = &intr_list->il_intr;
-	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
-		/* first entry on list was erased,
-		 * and we replaced it, so we
-		 * don't need our intr_entry.
-		 */
-		DEL(intr_entry);
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    intr_list_p = &intr_list->il_next;
-	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		/* we are the new second interrupt on this bit.
-		 */
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
-#if DEBUG && INTR_DEBUG
-		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
-			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		continue;
-	    }
-	    while (1) {
-		pcibr_intr_p = &intr_list->il_intr;
-		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
-		    /* an entry on list was erased,
-		     * and we replaced it, so we
-		     * don't need our intr_entry.
-		     */
-		    DEL(intr_entry);
-#if DEBUG && INTR_DEBUG
-		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
-			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		    break;
-		}
-		intr_list_p = &intr_list->il_next;
-		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
-		    /* entry appended to share list
-		     */
-#if DEBUG && INTR_DEBUG
-		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
-			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
-#endif
-		    break;
-		}
-		/* step to next record in chain
-		 */
-		intr_list = *intr_list_p;
-	    }
-	}
-    }
-
-#ifdef KERNEL_THREADS
-    if (is_threaded) {
-	/* Set pcibr_intr->bi_tinfo */
-	pcibr_thread_setup(pcibr_intr, pcibr_int_bits, thread_swlevel);
-	ASSERT(!(pcibr_intr->bi_flags & PCIIO_INTR_CONNECTED));
-    }
-#endif	/* KERNEL_THREADS */
-
-#if DEBUG && INTR_DEBUG
-    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
-#endif
-    hub_intr = (hub_intr_t)xtalk_intr;
-    pcibr_intr->bi_irq = hub_intr->i_bit;
-    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
-    return pcibr_intr;
-}
-
-/*ARGSUSED */
-void
-pcibr_intr_free(pcibr_intr_t pcibr_intr)
-{
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    unsigned                pcibr_int_bit;
-    pcibr_intr_list_t       intr_list;
-    int			    intr_shared;
-    xtalk_intr_t	    *xtalk_intrp;
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    for (intr_list = 
-		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
-		 intr_list != NULL;
-		 intr_list = intr_list->il_next)
-		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
-					 pcibr_intr, 
-					 NULL)) {
-#if DEBUG && INTR_DEBUG
-		    printk("%s: cleared a handler from bit %d\n",
-			    pcibr_soft->bs_name, pcibr_int_bit);
-#endif
-		}
-	    /* If this interrupt line is not being shared between multiple
-	     * devices release the xtalk interrupt resources.
-	     */
-	    intr_shared = 
-		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
-	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    if ((!intr_shared) && (*xtalk_intrp)) {
-
-		bridge_t 	*bridge = pcibr_soft->bs_base;
-		bridgereg_t	int_dev;
-
-		xtalk_intr_free(*xtalk_intrp);
-		*xtalk_intrp = 0;
-
-		/* Clear the PCI device interrupt to bridge interrupt pin
-		 * mapping.
-		 */
-		int_dev = bridge->b_int_device;
-		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
-		bridge->b_int_device = int_dev;
-
-	    }
-	}
-    }
-    DEL(pcibr_intr);
-}
-
-LOCAL void
-pcibr_setpciint(xtalk_intr_t xtalk_intr)
-{
-    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
-    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
-    bridgereg_t            *int_addr = (bridgereg_t *)
-    xtalk_intr_sfarg_get(xtalk_intr);
-
-    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
-		 (BRIDGE_INT_ADDR_FLD & vect));
-}
-
-/*ARGSUSED */
-int
-pcibr_intr_connect(pcibr_intr_t pcibr_intr,
-		   intr_func_t intr_func,
-		   intr_arg_t intr_arg,
-		   void *thread)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-    bridgereg_t             b_int_enable;
-    unsigned long           s;
-
-    if (pcibr_intr == NULL)
-	return -1;
-
-#if DEBUG && INTR_DEBUG
-    printk("%v: pcibr_intr_connect 0x%X(0x%X)\n",
-	    pcibr_intr->bi_dev, intr_func, intr_arg);
-#endif
-
-    pcibr_intr->bi_func = intr_func;
-    pcibr_intr->bi_arg = intr_arg;
-    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
-
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and make sure there are xtalk resources
-     * allocated for it.
-     */
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    pcibr_intr_wrap_t       intr_wrap;
-	    xtalk_intr_t            xtalk_intr;
-
-	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
-
-	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
-	    /*
-	     * If this interrupt line is being shared and the connect has
-	     * already been done, no need to do it again.
-	     */
-	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
-		continue;
-
-
-	    /*
-	     * Use the pcibr wrapper function to handle all Bridge interrupts
-	     * regardless of whether the interrupt line is shared or not.
-	     */
-	    xtalk_intr_connect(xtalk_intr,
-				pcibr_intr_func,
-			       (intr_arg_t) intr_wrap,
-			       (xtalk_intr_setfunc_t) pcibr_setpciint,
-			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr),
-			       0);
-	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
-
-#if DEBUG && INTR_DEBUG
-	    printk("%v bridge bit %d wrapper connected\n",
-		    pcibr_intr->bi_dev, pcibr_int_bit);
-#endif
-	}
-    s = pcibr_lock(pcibr_soft);
-    b_int_enable = bridge->b_int_enable;
-    b_int_enable |= pcibr_int_bits;
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-
-    return 0;
-}
-
-/*ARGSUSED */
-void
-pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-    pcibr_intr_wrap_t	    intr_wrap;
-    bridgereg_t             b_int_enable;
-    unsigned long           s;
-
-    /* Stop calling the function. Now.
-     */
-    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
-    pcibr_intr->bi_func = 0;
-    pcibr_intr->bi_arg = 0;
-    /*
-     * For each PCI interrupt line requested, figure
-     * out which Bridge PCI Interrupt Line it maps
-     * to, and disconnect the interrupt.
-     */
-
-    /* don't disable interrupts for lines that
-     * are shared between devices.
-     */
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
-	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
-	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
-    if (!pcibr_int_bits)
-	return;
-
-    s = pcibr_lock(pcibr_soft);
-    b_int_enable = bridge->b_int_enable;
-    b_int_enable &= ~pcibr_int_bits;
-    bridge->b_int_enable = b_int_enable;
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    pcibr_unlock(pcibr_soft, s);
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
-	    /* if the interrupt line is now shared,
-	     * do not disconnect it.
-	     */
-	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
-		continue;
-
-	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
-	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
-
-#if DEBUG && INTR_DEBUG
-	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
-		pcibr_soft->bs_name, pcibr_int_bit);
-#endif
-
-	    /* if we are sharing the interrupt line,
-	     * connect us up; this closes the hole
-	     * where the another pcibr_intr_alloc()
-	     * was in progress as we disconnected.
-	     */
-	    intr_wrap = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap;
-	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
-		continue;
-
-
-	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
-			       pcibr_intr_func,
-			       (intr_arg_t) intr_wrap,
-			       (xtalk_intr_setfunc_t) pcibr_setpciint,
-			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr),
-			       0);
-	}
-}
-
-/*ARGSUSED */
-devfs_handle_t
-pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
-{
-    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
-    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
-    unsigned                pcibr_int_bit;
-
-    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
-	if (pcibr_int_bits & (1 << pcibr_int_bit))
-	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
-    return 0;
-}
-
-/* =====================================================================
- *    INTERRUPT HANDLING
- */
-LOCAL void
-pcibr_clearwidint(bridge_t *bridge)
-{
-    bridge->b_wid_int_upper = 0;
-    bridge->b_wid_int_lower = 0;
-}
-
-
-LOCAL void
-pcibr_setwidint(xtalk_intr_t intr)
-{
-    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
-    iopaddr_t               addr = xtalk_intr_addr_get(intr);
-    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
-    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
-    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
-
-    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
-
-    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
-			       XTALK_ADDR_TO_UPPER(addr));
-    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
-
-    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
-    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-    /* Verify that all interrupts from this Bridge are using a single PI */
-    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
-	/*
-	 * Once set, these registers shouldn't change; they should
-	 * be set multiple times with the same values.
-	 *
-	 * If we're attempting to change these registers, it means
-	 * that our heuristics for allocating interrupts in a way
-	 * appropriate for IP35 have failed, and the admin needs to
-	 * explicitly direct some interrupts (or we need to make the
-	 * heuristics more clever).
-	 *
-	 * In practice, we hope this doesn't happen very often, if
-	 * at all.
-	 */
-	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
-	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
-		PRINT_WARNING("Interrupt allocation is too complex.\n");
-		PRINT_WARNING("Use explicit administrative interrupt targetting.\n");
-		PRINT_WARNING("bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
-		PRINT_WARNING("NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
-			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
-			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
-		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
-	}
-    }
-#endif /* CONFIG_SGI_IP35 */
-
-    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
-    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
-    bridge->b_int_host_err = vect;
-}
-
-/*
- * pcibr_intr_preset: called during mlreset time
- * if the platform specific code needs to route
- * one of the Bridge's xtalk interrupts before the
- * xtalk infrastructure is available.
- */
-void
-pcibr_xintr_preset(void *which_widget,
-		   int which_widget_intr,
-		   xwidgetnum_t targ,
-		   iopaddr_t addr,
-		   xtalk_intr_vector_t vect)
-{
-    bridge_t               *bridge = (bridge_t *) which_widget;
-
-    if (which_widget_intr == -1) {
-	/* bridge widget error interrupt */
-	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
-				   XTALK_ADDR_TO_UPPER(addr));
-	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
-	bridge->b_int_host_err = vect;
-
-	/* turn on all interrupts except
-	 * the PCI interrupt requests,
-	 * at least at heart.
-	 */
-	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
-
-    } else {
-	/* routing a PCI device interrupt.
-	 * targ and low 38 bits of addr must
-	 * be the same as the already set
-	 * value for the widget error interrupt.
-	 */
-	bridge->b_int_addr[which_widget_intr].addr =
-	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
-	     (BRIDGE_INT_ADDR_FLD & vect));
-	/*
-	 * now bridge can let it through;
-	 * NB: still should be blocked at
-	 * xtalk provider end, until the service
-	 * function is set.
-	 */
-	bridge->b_int_enable |= 1 << vect;
-    }
-    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-}
-
-
-/*
- * pcibr_intr_func()
- *
- * This is the pcibr interrupt "wrapper" function that is called,
- * in interrupt context, to initiate the interrupt handler(s) registered
- * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
- * handlers will be called directly, and threaded handlers will have their 
- * thread woken up.
- */
-void
-pcibr_intr_func(intr_arg_t arg)
-{
-    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
-    reg_p                   wrbf;
-    intr_func_t             func;
-    pcibr_intr_t            intr;
-    pcibr_intr_list_t       list;
-    int                     clearit;
-#ifdef KERNEL_THREADS
-    int			    do_nonthreaded = 0;
-    int			    do_threaded = 1;
-    int			    is_threaded = 0;
-#else
-    int			    do_nonthreaded = 1;
-    int			    do_threaded = 0;
-    int			    is_threaded = 0;
-#endif
-    int			    nonthreaded_count = 0;
-    int			    x = 0;
-
-	/*
-	 * If any handler is still running from a previous interrupt
-	 * just return. If there's a need to call the handler(s) again,
-	 * another interrupt will be generated either by the device or by
-	 * pcibr_force_interrupt().
-	 */
-
-	if (wrap->iw_hdlrcnt) {
-		return;
-	}
-
-    /*
-     * Call all interrupt handlers registered.
-     * First, the pcibr_intrd threads for any threaded handlers will be
-     * awoken, then any non-threaded handlers will be called sequentially.
-     */
-	
-	clearit = 1;
-	while (do_threaded || do_nonthreaded) {
-	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
-		if ((intr = list->il_intr) &&
-		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
-
-		    ASSERT(intr->bi_func);
-
-		/*
-		 * This device may have initiated write
-		 * requests since the bridge last saw
-		 * an edge on this interrupt input; flushing
-		 * the buffer prior to invoking the handler
-		 * should help but may not be sufficient if we 
-		 * get more requests after the flush, followed
-		 * by the card deciding it wants service, before
-		 * the interrupt handler checks to see if things need
-		 * to be done.
-		 *
-		 * There is a similar race condition if
-		 * an interrupt handler loops around and
-		 * notices further service is requred.
-		 * Perhaps we need to have an explicit
-		 * call that interrupt handlers need to
-		 * do between noticing that DMA to memory
-		 * has completed, but before observing the
-		 * contents of memory?
-		 */
-
-#ifdef KERNEL_THREADS
-		    is_threaded = !(intr->bi_flags & PCIIO_INTR_NOTHREAD);
-		    if (!is_threaded) {
-			nonthreaded_count++;
-		    }
-
-		    if ((do_threaded) && (is_threaded)) {
-			/* Only need to flush write buffers if sharing */
-
-			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
-			    if (x = *wrbf)	/* write request buffer flush */
-#ifdef SUPPORT_PRINTING_V_FORMAT
-				PRINT_ALERT("pcibr_intr_func %v: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#else
-				PRINT_ALERT("pcibr_intr_func 0x%x: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#endif
-			}
-
-			/*
-			 * Keep a running count of the number of interrupt
-			 * handlers that have yet to complete. 
-			 */
-			atomicAddInt(&(wrap->iw_hdlrcnt), 1);
-
-			/* 
-			 * Prior to waking up pcibr_intrd, a pointer to the 
-			 * wrapper struct corresponding to the interrupt taken
-			 * needs to be queued in the interrupt circular buffer.
-			 * The pcibr_intrd thread needs the wrapper pointer in
-			 * order to decrement the handler count (iw_hdlrcnt).
-			 */
-			pcibr_wrap_put(wrap, &intr->bi_ibuf);
-#ifdef ITHREAD_LATENCY
-			xthread_set_istamp(intr->bi_tinfo.thd_latstats);
-#endif /* ITHREAD_LATENCY */
-		     	up(&intr->bi_tinfo.thd_isync); 
-		    } else
-#endif	/* KERNEL_THREADS */
-			if ((do_nonthreaded) && (!is_threaded)) {
-			/* Non-threaded. 
-			 * Call the interrupt handler at interrupt level
-			 */
-
-			/* Only need to flush write buffers if sharing */
-
-			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
-			    if ((x = *wrbf))	/* write request buffer flush */
-#ifdef SUPPORT_PRINTING_V_FORMAT
-				PRINT_ALERT("pcibr_intr_func %v: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#else
-				PRINT_ALERT("pcibr_intr_func %p: \n"
-				    "write buffer flush failed, wrbf=0x%x\n", 
-				    list->il_intr->bi_dev, wrbf);
-#endif
-			}
-
-			func = intr->bi_func;
-			func(intr->bi_arg);
-		    }
-
-		    clearit = 0;
-		}
-	    }
-
-	    if (do_threaded) {
-		/* 
-		 * All threaded handlers have been called;
-		 * next do non-threaded, if any.
-		 */
-		do_threaded = 0;
-
-		if (nonthreaded_count)
-			do_nonthreaded = 1;
-	    } else {
-		do_nonthreaded = 0;
-		/*
-		 * If the non-threaded handler was the last to complete,
-		 * (i.e., no threaded handlers still running) force an
-		 * interrupt to avoid a potential deadlock situation.
-		 */
-		if (wrap->iw_hdlrcnt == 0) {
-			pcibr_force_interrupt(wrap);
-		}
-	    }
-	}
-
-	/* If there were no handlers,
-	 * disable the interrupt and return.
-	 * It will get enabled again after
-	 * a handler is connected.
-	 * If we don't do this, we would
-	 * sit here and spin through the
-	 * list forever.
-	 */
-	if (clearit) {
-	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
-	    bridge_t               *bridge = pcibr_soft->bs_base;
-	    bridgereg_t             b_int_enable;
-	    bridgereg_t		    mask = 1 << wrap->iw_intr;
-	    unsigned long           s;
-
-	    s = pcibr_lock(pcibr_soft);
-	    b_int_enable = bridge->b_int_enable;
-	    b_int_enable &= ~mask;
-	    bridge->b_int_enable = b_int_enable;
-	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	    pcibr_unlock(pcibr_soft, s);
-	    return;
-	}
-}
-
-/* =====================================================================
- *    ERROR HANDLING
- */
-
-#ifdef	DEBUG
-#ifdef	ERROR_DEBUG
-#define BRIDGE_PIOERR_TIMEOUT	100	/* Timeout with ERROR_DEBUG defined */
-#else
-#define BRIDGE_PIOERR_TIMEOUT	40	/* Timeout in debug mode  */
-#endif
-#else
-#define BRIDGE_PIOERR_TIMEOUT	1	/* Timeout in non-debug mode                            */
-#endif
-
-LOCAL void
-print_bridge_errcmd(uint32_t cmdword, char *errtype)
-{
-#ifdef SUPPORT_PRINTING_R_FORMAT
-    PRINT_WARNING(
-	    "	Bridge %s error command word register %R",
-	    errtype, cmdword, xio_cmd_bits);
-#else
-    PRINT_WARNING(
-	    "	Bridge %s error command word register 0x%x",
-	    errtype, cmdword);
-#endif
-}
-
-LOCAL char             *pcibr_isr_errs[] =
-{
-    "", "", "", "", "", "", "", "",
-    "08: GIO non-contiguous byte enable in crosstalk packet",
-    "09: PCI to Crosstalk read request timeout",
-    "10: PCI retry operation count exhausted.",
-    "11: PCI bus device select timeout",
-    "12: PCI device reported parity error",
-    "13: PCI Address/Cmd parity error ",
-    "14: PCI Bridge detected parity error",
-    "15: PCI abort condition",
-    "16: SSRAM parity error",
-    "17: LLP Transmitter Retry count wrapped",
-    "18: LLP Transmitter side required Retry",
-    "19: LLP Receiver retry count wrapped",
-    "20: LLP Receiver check bit error",
-    "21: LLP Receiver sequence number error",
-    "22: Request packet overflow",
-    "23: Request operation not supported by bridge",
-    "24: Request packet has invalid address for bridge widget",
-    "25: Incoming request xtalk command word error bit set or invalid sideband",
-    "26: Incoming response xtalk command word error bit set or invalid sideband",
-    "27: Framing error, request cmd data size does not match actual",
-    "28: Framing error, response cmd data size does not match actual",
-    "29: Unexpected response arrived",
-    "30: Access to SSRAM beyond device limits",
-    "31: Multiple errors occurred",
-};
-
-/*
- * PCI Bridge Error interrupt handling.
- * This routine gets invoked from system interrupt dispatcher
- * and is responsible for invoking appropriate error handler,
- * depending on the type of error.
- * This IS a duplicate of bridge_errintr defined specfic to IP30.
- * There are some minor differences in terms of the return value and
- * parameters passed. One of these two should be removed at some point
- * of time.
- */
-/*ARGSUSED */
-void
-pcibr_error_dump(pcibr_soft_t pcibr_soft)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             int_status;
-    int                     i;
-
-    int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
-
-    PRINT_ALERT( "%s PCI BRIDGE ERROR: int_status is 0x%X",
-	    pcibr_soft->bs_name, int_status);
-
-    for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
-	if (int_status & (1 << i)) {
-	    PRINT_WARNING( "%s", pcibr_isr_errs[i]);
-	}
-    }
-
-    if (int_status & BRIDGE_ISR_XTALK_ERROR) {
-	print_bridge_errcmd(bridge->b_wid_err_cmdword, "");
-
-	PRINT_WARNING("   Bridge error address 0x%lx",
-		(((uint64_t) bridge->b_wid_err_upper << 32) |
-		 bridge->b_wid_err_lower));
-
-	print_bridge_errcmd(bridge->b_wid_aux_err, "Aux");
-
-	if (int_status & (BRIDGE_ISR_BAD_XRESP_PKT | BRIDGE_ISR_RESP_XTLK_ERR)) {
-	    PRINT_WARNING("	Bridge response buffer: dev-num %d buff-num %d addr 0x%lx\n",
-		    ((bridge->b_wid_resp_upper >> 20) & 0x3),
-		    ((bridge->b_wid_resp_upper >> 16) & 0xF),
-		    (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32) |
-		     bridge->b_wid_resp_lower));
-	}
-    }
-    if (int_status & BRIDGE_ISR_SSRAM_PERR)
-	PRINT_WARNING("   Bridge SSRAM parity error register 0x%x",
-		bridge->b_ram_perr);
-
-    if (int_status & BRIDGE_ISR_PCIBUS_ERROR) {
-	PRINT_WARNING("   PCI/GIO error upper address register 0x%x",
-		bridge->b_pci_err_upper);
-
-	PRINT_WARNING("   PCI/GIO error lower address register 0x%x",
-		bridge->b_pci_err_lower);
-    }
-    if (int_status & BRIDGE_ISR_ERROR_FATAL) {
-	PRINT_PANIC("PCI Bridge Error interrupt killed the system");
-	/*NOTREACHED */
-    } else {
-	PRINT_ALERT( "Non-fatal Error in Bridge..");
-    }
-}
-
-#define PCIBR_ERRINTR_GROUP(error)	\
-		(( error & (BRIDGE_IRR_PCI_GRP|BRIDGE_IRR_GIO_GRP)
-
-uint32_t
-pcibr_errintr_group(uint32_t error)
-{
-    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
-
-    if (error & BRIDGE_IRR_PCI_GRP)
-	group |= BRIDGE_IRR_PCI_GRP_CLR;
-    if (error & BRIDGE_IRR_SSRAM_GRP)
-	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
-    if (error & BRIDGE_IRR_LLP_GRP)
-	group |= BRIDGE_IRR_LLP_GRP_CLR;
-    if (error & BRIDGE_IRR_REQ_DSP_GRP)
-	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
-    if (error & BRIDGE_IRR_RESP_BUF_GRP)
-	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
-    if (error & BRIDGE_IRR_CRP_GRP)
-	group |= BRIDGE_IRR_CRP_GRP_CLR;
-
-    return group;
-
-}
-
-
-/* pcibr_pioerr_check():
- *	Check to see if this pcibr has a PCI PIO
- *	TIMEOUT error; if so, clear it and bump
- *	the timeout-count on any piomaps that
- *	could cover the address.
- */
-static void
-pcibr_pioerr_check(pcibr_soft_t soft)
-{
-    bridge_t		   *bridge;
-    bridgereg_t		    b_int_status;
-    bridgereg_t		    b_pci_err_lower;
-    bridgereg_t		    b_pci_err_upper;
-    iopaddr_t		    pci_addr;
-    pciio_slot_t	    slot;
-    pcibr_piomap_t	    map;
-    iopaddr_t		    base;
-    size_t		    size;
-    unsigned		    win;
-    int			    func;
-
-    bridge = soft->bs_base;
-    b_int_status = bridge->b_int_status;
-    if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	b_pci_err_lower = bridge->b_pci_err_lower;
-	b_pci_err_upper = bridge->b_pci_err_upper;
-	b_int_status = bridge->b_int_status;
-	if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	    bridge->b_int_rst_stat = (BRIDGE_IRR_PCI_GRP_CLR|
-				      BRIDGE_IRR_MULTI_CLR);
-
-	    pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
-	    pci_addr = (pci_addr << 32) | b_pci_err_lower;
-
-	    slot = 8;
-	    while (slot-- > 0) {
-		int 		nfunc = soft->bs_slot[slot].bss_ninfo;
-		pcibr_info_h	pcibr_infoh = soft->bs_slot[slot].bss_infos;
-
-		for (func = 0; func < nfunc; func++) {
-		    pcibr_info_t 	pcibr_info = pcibr_infoh[func];
-
-		    if (!pcibr_info)
-			continue;
-
-		    for (map = pcibr_info->f_piomap;
-			 map != NULL; map = map->bp_next) {
-			base = map->bp_pciaddr;
-			size = map->bp_mapsz;
-			win = map->bp_space - PCIIO_SPACE_WIN(0);
-			if (win < 6)
-			    base += 
-				soft->bs_slot[slot].bss_window[win].bssw_base;
-			else if (map->bp_space == PCIIO_SPACE_ROM)
-			    base += pcibr_info->f_rbase;
-			if ((pci_addr >= base) && (pci_addr < (base + size)))
-			    atomic_inc(map->bp_toc);
-		    }
-		}
-	    }
-	}
-    }
-}
-
-/*
- * PCI Bridge Error interrupt handler.
- *      This gets invoked, whenever a PCI bridge sends an error interrupt.
- *      Primarily this servers two purposes.
- *              - If an error can be handled (typically a PIO read/write
- *                error, we try to do it silently.
- *              - If an error cannot be handled, we die violently.
- *      Interrupt due to PIO errors:
- *              - Bridge sends an interrupt, whenever a PCI operation
- *                done by the bridge as the master fails. Operations could
- *                be either a PIO read or a PIO write.
- *                PIO Read operation also triggers a bus error, and it's
- *                We primarily ignore this interrupt in that context..
- *                For PIO write errors, this is the only indication.
- *                and we have to handle with the info from here.
- *
- *                So, there is no way to distinguish if an interrupt is
- *                due to read or write error!.
- */
-
-
-LOCAL void
-pcibr_error_intr_handler(intr_arg_t arg)
-{
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge;
-    bridgereg_t             int_status;
-    bridgereg_t             err_status;
-    int                     i;
-
-    /* REFERENCED */
-    bridgereg_t             disable_errintr_mask = 0;
-
-#if PCIBR_SOFT_LIST
-    /* IP27 seems to be handing us junk.
-     */
-    {
-	pcibr_list_p            entry;
-
-	entry = pcibr_list;
-	while (1) {
-	    if (entry == NULL) {
-		printk("pcibr_error_intr_handler:\n"
-			"\tparameter (0x%p) is not a pcibr_soft!",
-			arg);
-		PRINT_PANIC("Invalid parameter to pcibr_error_intr_handler");
-	    }
-	    if ((intr_arg_t) entry->bl_soft == arg)
-		break;
-	    entry = entry->bl_next;
-	}
-    }
-#endif
-    pcibr_soft = (pcibr_soft_t) arg;
-    bridge = pcibr_soft->bs_base;
-
-    /*
-     * pcibr_error_intr_handler gets invoked whenever bridge encounters
-     * an error situation, and the interrupt for that error is enabled.
-     * This routine decides if the error is fatal or not, and takes
-     * action accordingly.
-     *
-     * In one case there is a need for special action.
-     * In case of PIO read/write timeouts due to user level, we do
-     * get an error interrupt. In this case, way to handle would
-     * be to start a timeout. If the error was due to "read", bus
-     * error handling code takes care of it. If error is due to write,
-     * it's handled at timeout
-     */
-
-    /* int_status is which bits we have to clear;
-     * err_status is the bits we haven't handled yet.
-     */
-
-    int_status = bridge->b_int_status &  ~BRIDGE_ISR_INT_MSK;
-    err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
-
-    if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
-	/*
-	 * No error bit set!!.
-	 */
-	return;
-    }
-    /* If we have a PCIBUS_PIOERR,
-     * hand it to the logger but otherwise
-     * ignore the event.
-     */
-    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
-	pcibr_pioerr_check(pcibr_soft);
-	err_status &= ~BRIDGE_ISR_PCIBUS_PIOERR;
-	int_status &= ~BRIDGE_ISR_PCIBUS_PIOERR;
-    }
-
-
-    if (err_status) {
-	struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
-
-	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) {
-	    if (err_status & (1 << i)) {
-		uint32_t              errrate = 0;
-		uint32_t              errcount = 0;
-		uint32_t              errinterval = 0, current_tick = 0;
-		int                     panic_on_llp_tx_retry = 0;
-		int                     is_llp_tx_retry_intr = 0;
-
-		bs_estat->bs_errcount_total++;
-
-#ifdef LATER
-		current_tick = lbolt;
-#else
-		current_tick = 0;
-#endif
-		errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
-		errcount = (bs_estat->bs_errcount_total -
-			    bs_estat->bs_lasterr_snapshot);
-
-		is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i));
-
-		/* On a non-zero error rate (which is equivalent to
-		 * to 100 errors /sec at least) for the LLP transmitter
-		 * retry interrupt we need to panic the system
-		 * to prevent potential data corruption .
-		 * NOTE : errcount is being compared to PCIBR_ERRTIME_THRESHOLD
-		 * to make sure that we are not seing cases like x error
-		 * interrupts per y ticks for very low x ,y (x > y ) which
-		 * makes error rate be > 100 /sec.
-		 */
-
-		/* Check for the divide by zero condition while
-		 * calculating the error rates.
-		 */
-
-		if (errinterval) {
-		    errrate = errcount / errinterval;
-		    /* If able to calculate error rate
-		     * on a LLP transmitter retry interrupt check
-		     * if the error rate is nonzero and we have seen
-		     * a certain minimum number of errors.
-		     */
-		    if (is_llp_tx_retry_intr &&
-			errrate &&
-			(errcount >= PCIBR_ERRTIME_THRESHOLD)) {
-			panic_on_llp_tx_retry = 1;
-		    }
-		} else {
-		    errrate = 0;
-		    /* Since we are not able to calculate the
-		     * error rate check if we exceeded a certain
-		     * minimum number of errors for LLP transmitter
-		     * retries. Note that this can only happen
-		     * within the first tick after the last snapshot.
-		     */
-		    if (is_llp_tx_retry_intr &&
-			(errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
-			panic_on_llp_tx_retry = 1;
-		    }
-		}
-		if (panic_on_llp_tx_retry) {
-		    static uint32_t       last_printed_rate;
-
-		    if (errrate > last_printed_rate) {
-			last_printed_rate = errrate;
-			/* Print the warning only if the error rate
-			 * for the transmitter retry interrupt
-			 * exceeded the previously printed rate.
-			 */
-			PRINT_WARNING(
-				"%s: %s, Excessive error interrupts : %d/tick\n",
-				pcibr_soft->bs_name,
-				pcibr_isr_errs[i],
-				errrate);
-
-		    }
-		    /*
-		     * Update snapshot, and time
-		     */
-		    bs_estat->bs_lasterr_timestamp = current_tick;
-		    bs_estat->bs_lasterr_snapshot =
-			bs_estat->bs_errcount_total;
-
-		}
-		/*
-		 * If the error rate is high enough, print the error rate.
-		 */
-		if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
-
-		    if (errrate > PCIBR_ERRRATE_THRESHOLD) {
-			PRINT_NOTICE( "%s: %s, Error rate %d/tick",
-				pcibr_soft->bs_name,
-				pcibr_isr_errs[i],
-				errrate);
-			/*
-			 * Update snapshot, and time
-			 */
-			bs_estat->bs_lasterr_timestamp = current_tick;
-			bs_estat->bs_lasterr_snapshot =
-			    bs_estat->bs_errcount_total;
-		    }
-		}
-		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
-		    /*
-		     * We have seen a fairly large number of errors of
-		     * this type. Let's disable the interrupt. But flash
-		     * a message about the interrupt being disabled.
-		     */
-		    PRINT_NOTICE(
-			    "%s Disabling error interrupt type %s. Error count %d",
-			    pcibr_soft->bs_name,
-			    pcibr_isr_errs[i],
-			    bs_estat->bs_errcount_total);
-		    disable_errintr_mask |= (1 << i);
-		}
-	    }
-	}
-    }
-
-    if (disable_errintr_mask) {
-	/*
-	 * Disable some high frequency errors as they
-	 * could eat up too much cpu time.
-	 */
-	bridge->b_int_enable &= ~disable_errintr_mask;
-    }
-    /*
-     * If we leave the PROM cacheable, T5 might
-     * try to do a cache line sized writeback to it,
-     * which will cause a BRIDGE_ISR_INVLD_ADDR.
-     */
-    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
-	(0x00000000 == bridge->b_wid_err_upper) &&
-	(0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
-	(0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
-	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
-    }
-#if defined (PCIBR_LLP_CONTROL_WAR)
-    /*
-     * The bridge bug, where the llp_config or control registers
-     * need to be read back after being written, affects an MP
-     * system since there could be small windows between writing
-     * the register and reading it back on one cpu while another
-     * cpu is fielding an interrupt. If we run into this scenario,
-     * workaround the problem by ignoring the error. (bug 454474)
-     * pcibr_llp_control_war_cnt keeps an approximate number of
-     * times we saw this problem on a system.
-     */
-
-    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
-	((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
-	 == (BRIDGE_INT_RST_STAT & 0xff0))) {
-#ifdef LATER
-	if (kdebug)
-	    PRINT_NOTICE( "%s bridge: ignoring llp/control address interrupt",
-		    pcibr_soft->bs_name);
-#endif
-	pcibr_llp_control_war_cnt++;
-	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
-    }
-#endif				/* PCIBR_LLP_CONTROL_WAR */
-
-#ifdef	DEBUG
-	if (err_status & BRIDGE_ISR_ERROR_DUMP)
-	    pcibr_error_dump(pcibr_soft);
-#else	
-	if (err_status & BRIDGE_ISR_ERROR_FATAL) {
-	    printk("BRIDGE ERR STATUS 0x%x\n", err_status);
-	    pcibr_error_dump(pcibr_soft);
-	}
-#endif
-
-    /*
-     * We can't return without re-enabling the interrupt, since
-     * it would cause problems for devices like IOC3 (Lost
-     * interrupts ?.). So, just cleanup the interrupt, and
-     * use saved values later..
-     */
-    bridge->b_int_rst_stat = pcibr_errintr_group(int_status);
-}
-
-/*
- * pcibr_addr_toslot
- *      Given the 'pciaddr' find out which slot this address is
- *      allocated to, and return the slot number.
- *      While we have the info handy, construct the
- *      function number, space code and offset as well.
- *
- * NOTE: if this routine is called, we don't know whether
- * the address is in CFG, MEM, or I/O space. We have to guess.
- * This will be the case on PIO stores, where the only way
- * we have of getting the address is to check the Bridge, which
- * stores the PCI address but not the space and not the xtalk
- * address (from which we could get it).
- */
-LOCAL int
-pcibr_addr_toslot(pcibr_soft_t pcibr_soft,
-		  iopaddr_t pciaddr,
-		  pciio_space_t *spacep,
-		  iopaddr_t *offsetp,
-		  pciio_function_t *funcp)
-{
-    int                     s, f=0, w;
-    iopaddr_t               base;
-    size_t                  size;
-    pciio_piospace_t        piosp;
-
-    /*
-     * Check if the address is in config space
-     */
-
-    if ((pciaddr >= BRIDGE_CONFIG_BASE) && (pciaddr < BRIDGE_CONFIG_END)) {
-
-	if (pciaddr >= BRIDGE_CONFIG1_BASE)
-	    pciaddr -= BRIDGE_CONFIG1_BASE;
-	else
-	    pciaddr -= BRIDGE_CONFIG_BASE;
-
-	s = pciaddr / BRIDGE_CONFIG_SLOT_SIZE;
-	pciaddr %= BRIDGE_CONFIG_SLOT_SIZE;
-
-	if (funcp) {
-	    f = pciaddr / 0x100;
-	    pciaddr %= 0x100;
-	}
-	if (spacep)
-	    *spacep = PCIIO_SPACE_CFG;
-	if (offsetp)
-	    *offsetp = pciaddr;
-	if (funcp)
-	    *funcp = f;
-
-	return s;
-    }
-    for (s = 0; s < 8; s++) {
-	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
-	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
-
-	for (f = 0; f < nf; f++) {
-	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
-
-	    if (!pcibr_info)
-		continue;
-	    for (w = 0; w < 6; w++) {
-		if (pcibr_info->f_window[w].w_space
-		    == PCIIO_SPACE_NONE) {
-		    continue;
-		}
-		base = pcibr_info->f_window[w].w_base;
-		size = pcibr_info->f_window[w].w_size;
-
-		if ((pciaddr >= base) && (pciaddr < (base + size))) {
-		    if (spacep)
-			*spacep = PCIIO_SPACE_WIN(w);
-		    if (offsetp)
-			*offsetp = pciaddr - base;
-		    if (funcp)
-			*funcp = f;
-		    return s;
-		}			/* endif match */
-	    }				/* next window */
-	}				/* next func */
-    }					/* next slot */
-
-    /*
-     * Check if the address was allocated as part of the
-     * pcibr_piospace_alloc calls.
-     */
-    for (s = 0; s < 8; s++) {
-	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
-	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
-
-	for (f = 0; f < nf; f++) {
-	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
-
-	    if (!pcibr_info)
-		continue;
-	    piosp = pcibr_info->f_piospace;
-	    while (piosp) {
-		if ((piosp->start <= pciaddr) &&
-		    ((piosp->count + piosp->start) > pciaddr)) {
-		    if (spacep)
-			*spacep = piosp->space;
-		    if (offsetp)
-			*offsetp = pciaddr - piosp->start;
-		    return s;
-		}			/* endif match */
-		piosp = piosp->next;
-	    }				/* next piosp */
-	}				/* next func */
-    }					/* next slot */
-
-    /*
-     * Some other random address on the PCI bus ...
-     * we have no way of knowing whether this was
-     * a MEM or I/O access; so, for now, we just
-     * assume that the low 1G is MEM, the next
-     * 3G is I/O, and anything above the 4G limit
-     * is obviously MEM.
-     */
-
-    if (spacep)
-	*spacep = ((pciaddr < (1ul << 30)) ? PCIIO_SPACE_MEM :
-		   (pciaddr < (4ul << 30)) ? PCIIO_SPACE_IO :
-		   PCIIO_SPACE_MEM);
-    if (offsetp)
-	*offsetp = pciaddr;
-
-    return PCIIO_SLOT_NONE;
-
-}
-
-LOCAL void
-pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
-{
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    ASSERT(error_code & IOECODE_PIO);
-    error_code = error_code;
-
-    bridge->b_int_rst_stat =
-	(BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR);
-    (void) bridge->b_wid_tflush;	/* flushbus */
-}
-
-/*
- * pcibr_error_extract
- *      Given the 'pcibr vertex handle' find out which slot
- *      the bridge status error address (from pcibr_soft info
- *      hanging off the vertex)
- *      allocated to, and return the slot number.
- *      While we have the info handy, construct the
- *      space code and offset as well.
- *
- * NOTE: if this routine is called, we don't know whether
- * the address is in CFG, MEM, or I/O space. We have to guess.
- * This will be the case on PIO stores, where the only way
- * we have of getting the address is to check the Bridge, which
- * stores the PCI address but not the space and not the xtalk
- * address (from which we could get it).
- *
- * XXX- this interface has no way to return the function
- * number on a multifunction card, even though that data
- * is available.
- */
-
-pciio_slot_t
-pcibr_error_extract(devfs_handle_t pcibr_vhdl,
-		    pciio_space_t *spacep,
-		    iopaddr_t *offsetp)
-{
-    pcibr_soft_t            pcibr_soft = 0;
-    iopaddr_t               bserr_addr;
-    bridge_t               *bridge;
-    pciio_slot_t            slot = PCIIO_SLOT_NONE;
-    arbitrary_info_t	    rev;
-
-    /* Do a sanity check as to whether we really got a 
-     * bridge vertex handle.
-     */
-    if (hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &rev) !=
-	GRAPH_SUCCESS) 
-	return(slot);
-
-    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
-    if (pcibr_soft) {
-	bridge = pcibr_soft->bs_base;
-	bserr_addr =
-	    bridge->b_pci_err_lower |
-	    ((uint64_t) (bridge->b_pci_err_upper &
-			   BRIDGE_ERRUPPR_ADDRMASK) << 32);
-
-	slot = pcibr_addr_toslot(pcibr_soft, bserr_addr,
-				 spacep, offsetp, NULL);
-    }
-    return slot;
-}
-
-/*ARGSUSED */
-void
-pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
-{
-    /*
-     * XXX
-     * Device failed to handle error. Take steps to
-     * disable this device ? HOW TO DO IT ?
-     *
-     * If there are any Read response buffers associated
-     * with this device, it's time to get them back!!
-     *
-     * We can disassociate any interrupt level associated
-     * with this device, and disable that interrupt level
-     *
-     * For now it's just a place holder
-     */
-}
-
-/*
- * pcibr_pioerror
- *      Handle PIO error that happened at the bridge pointed by pcibr_soft.
- *
- *      Queries the Bus interface attached to see if the device driver
- *      mapping the device-number that caused error can handle the
- *      situation. If so, it will clean up any error, and return
- *      indicating the error was handled. If the device driver is unable
- *      to handle the error, it expects the bus-interface to disable that
- *      device, and takes any steps needed here to take away any resources
- *      associated with this device.
- */
-
-#define BEM_ADD_STR(s)	printk("%s", (s))
-#ifdef SUPPORT_SGI_CMN_ERR_STUFF
-#define BEM_ADD_VAR(v)	printk("\t%20s: 0x%x\n", #v, (v))
-#define BEM_ADD_REG(r)	printk("\t%20s: %R\n", #r, (r), r ## _desc)
-
-#define BEM_ADD_NSPC(n,s)	printk("\t%20s: %R\n", n, s, space_desc)
-#else
-#define BEM_ADD_VAR(v)	
-#define BEM_ADD_REG(r)	
-#define BEM_ADD_NSPC(n,s)
-#endif
-#define BEM_ADD_SPC(s)		BEM_ADD_NSPC(#s, s)
-
-/* BEM_ADD_IOE doesn't dump the whole ioerror, it just
- * decodes the PCI specific portions -- we count on our
- * callers to dump the raw IOE data.
- */
-#ifdef LATER
-#define BEM_ADD_IOE(ioe)						\
-	do {								\
-	    if (IOERROR_FIELDVALID(ioe, busspace)) {			\
-		unsigned		spc;				\
-		unsigned		win;				\
-									\
-		spc = IOERROR_GETVALUE(ioe, busspace);			\
-		win = spc - PCIIO_SPACE_WIN(0);				\
-									\
-		switch (spc) {						\
-		case PCIIO_SPACE_CFG:					\
-		    printk("\tPCI Slot %d Func %d CFG space Offset 0x%x\n",	\
-	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		case PCIIO_SPACE_IO:					\
-		    printk("\tPCI I/O space  Offset 0x%x\n",		\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		case PCIIO_SPACE_MEM:					\
-		case PCIIO_SPACE_MEM32:					\
-		case PCIIO_SPACE_MEM64:					\
-		    printk("\tPCI MEM space Offset 0x%x\n",		\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    break;						\
-		default:						\
-		    if (win < 6) {					\
-		    printk("\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\
-	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
-			    win,					\
-			    IOERROR_GETVALUE(ioe, busaddr));		\
-		    }							\
-		    break;						\
-		}							\
-	    }								\
-	} while (0)
-#else
-#define BEM_ADD_IOE(ioe)
-#endif
-
-/*ARGSUSED */
-LOCAL int
-pcibr_pioerror(
-		  pcibr_soft_t pcibr_soft,
-		  int error_code,
-		  ioerror_mode_t mode,
-		  ioerror_t *ioe)
-{
-    int                     retval = IOERROR_HANDLED;
-
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-
-    bridgereg_t             bridge_int_status;
-    bridgereg_t             bridge_pci_err_lower;
-    bridgereg_t             bridge_pci_err_upper;
-    bridgereg_t             bridge_pci_err_addr;
-
-    iopaddr_t               bad_xaddr;
-
-    pciio_space_t           raw_space;	/* raw PCI space */
-    iopaddr_t               raw_paddr;	/* raw PCI address */
-
-    pciio_space_t           space;	/* final PCI space */
-    pciio_slot_t            slot;	/* final PCI slot, if appropriate */
-    pciio_function_t        func;	/* final PCI func, if appropriate */
-    iopaddr_t               offset;	/* final PCI offset */
-    
-    int                     cs, cw, cf;
-    pciio_space_t           wx;
-    iopaddr_t               wb;
-    size_t                  ws;
-    iopaddr_t               wl;
-
-
-    /*
-     * We expect to have an "xtalkaddr" coming in,
-     * and need to construct the slot/space/offset.
-     */
-
-#ifdef LATER
-    bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr);
-#else
-    bad_xaddr = -1;
-#endif
-
-    slot = PCIIO_SLOT_NONE;
-    func = PCIIO_FUNC_NONE;
-    raw_space = PCIIO_SPACE_NONE;
-    raw_paddr = 0;
-
-    if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) &&
-	(bad_xaddr < BRIDGE_TYPE1_CFG)) {
-	raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0;
-	slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
-	raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
-	raw_space = PCIIO_SPACE_CFG;
-    }
-    if ((bad_xaddr >= BRIDGE_TYPE1_CFG) &&
-	(bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) {
-	/* Type 1 config space:
-	 * slot and function numbers not known.
-	 * Perhaps we can read them back?
-	 */
-	raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG;
-	raw_space = PCIIO_SPACE_CFG;
-    }
-    if ((bad_xaddr >= BRIDGE_DEVIO0) &&
-	(bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) {
-	int                     x;
-
-	raw_paddr = bad_xaddr - BRIDGE_DEVIO0;
-	x = raw_paddr / BRIDGE_DEVIO_OFF;
-	raw_paddr %= BRIDGE_DEVIO_OFF;
-	/* first two devio windows are double-sized */
-	if ((x == 1) || (x == 3))
-	    raw_paddr += BRIDGE_DEVIO_OFF;
-	if (x > 0)
-	    x--;
-	if (x > 1)
-	    x--;
-	/* x is which devio reg; no guarantee
-	 * PCI slot x will be responding.
-	 * still need to figure out who decodes
-	 * space/offset on the bus.
-	 */
-	raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
-	if (raw_space == PCIIO_SPACE_NONE) {
-	    /* Someone got an error because they
-	     * accessed the PCI bus via a DevIO(x)
-	     * window that pcibr has not yet assigned
-	     * to any specific PCI address. It is
-	     * quite possible that the Device(x)
-	     * register has been changed since they
-	     * made their access, but we will give it
-	     * our best decode shot.
-	     */
-	    raw_space = pcibr_soft->bs_slot[x].bss_device
-		& BRIDGE_DEV_DEV_IO_MEM
-		? PCIIO_SPACE_MEM
-		: PCIIO_SPACE_IO;
-	    raw_paddr +=
-		(pcibr_soft->bs_slot[x].bss_device &
-		 BRIDGE_DEV_OFF_MASK) <<
-		BRIDGE_DEV_OFF_ADDR_SHFT;
-	} else
-	    raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
-	raw_space = PCIIO_SPACE_MEM32;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
-	raw_space = PCIIO_SPACE_MEM64;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
-    }
-    if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
-	(bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
-	raw_space = PCIIO_SPACE_IO;
-	raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
-    }
-    space = raw_space;
-    offset = raw_paddr;
-
-    if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
-	/* we've got a space/offset but not which
-	 * PCI slot decodes it. Check through our
-	 * notions of which devices decode where.
-	 *
-	 * Yes, this "duplicates" some logic in
-	 * pcibr_addr_toslot; the difference is,
-	 * this code knows which space we are in,
-	 * and can really really tell what is
-	 * going on (no guessing).
-	 */
-
-	for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) {
-	    int                     nf = pcibr_soft->bs_slot[cs].bss_ninfo;
-	    pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
-
-	    for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
-		pcibr_info_t            pcibr_info = pcibr_infoh[cf];
-
-		if (!pcibr_info)
-		    continue;
-		for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
-		    if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
-			((wb = pcibr_info->f_window[cw].w_base) != 0) &&
-			((ws = pcibr_info->f_window[cw].w_size) != 0) &&
-			((wl = wb + ws) > wb) &&
-			((wb <= offset) && (wl > offset))) {
-			/* MEM, MEM32 and MEM64 need to
-			 * compare as equal ...
-			 */
-			if ((wx == space) ||
-			    (((wx == PCIIO_SPACE_MEM) ||
-			      (wx == PCIIO_SPACE_MEM32) ||
-			      (wx == PCIIO_SPACE_MEM64)) &&
-			     ((space == PCIIO_SPACE_MEM) ||
-			      (space == PCIIO_SPACE_MEM32) ||
-			      (space == PCIIO_SPACE_MEM64)))) {
-			    slot = cs;
-			    func = cf;
-			    space = PCIIO_SPACE_WIN(cw);
-			    offset -= wb;
-			}		/* endif window space match */
-		    }			/* endif window valid and addr match */
-		}			/* next window unless slot set */
-	    }				/* next func unless slot set */
-	}				/* next slot unless slot set */
-	/* XXX- if slot is still -1, no PCI devices are
-	 * decoding here using their standard PCI BASE
-	 * registers. This would be a really good place
-	 * to cross-coordinate with the pciio PCI
-	 * address space allocation routines, to find
-	 * out if this address is "allocated" by any of
-	 * our subsidiary devices.
-	 */
-    }
-    /* Scan all piomap records on this PCI bus to update
-     * the TimeOut Counters on all matching maps. If we
-     * don't already know the slot number, take it from
-     * the first matching piomap. Note that we have to
-     * compare maps against raw_space and raw_paddr
-     * since space and offset could already be
-     * window-relative.
-     *
-     * There is a chance that one CPU could update
-     * through this path, and another CPU could also
-     * update due to an interrupt. Closing this hole
-     * would only result in the possibility of some
-     * errors never getting logged at all, and since the
-     * use for bp_toc is as a logical test rather than a
-     * strict count, the excess counts are not a
-     * problem.
-     */
-    for (cs = 0; cs < 8; ++cs) {
-	int 		nf = pcibr_soft->bs_slot[cs].bss_ninfo;
-	pcibr_info_h	pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
-
-	for (cf = 0; cf < nf; cf++) {
-	    pcibr_info_t 	pcibr_info = pcibr_infoh[cf];
-	    pcibr_piomap_t	map;    
-
-	    if (!pcibr_info)
-		continue;
-
-	    for (map = pcibr_info->f_piomap;
-	     map != NULL; map = map->bp_next) {
-	    wx = map->bp_space;
-	    wb = map->bp_pciaddr;
-	    ws = map->bp_mapsz;
-	    cw = wx - PCIIO_SPACE_WIN(0);
-	    if (cw < 6) {
-		wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
-		wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
-	    }
-	    if (wx == PCIIO_SPACE_ROM) {
-		wb += pcibr_info->f_rbase;
-		wx = PCIIO_SPACE_MEM;
-	    }
-	    if ((wx == PCIIO_SPACE_MEM32) ||
-		(wx == PCIIO_SPACE_MEM64))
-		wx = PCIIO_SPACE_MEM;
-	    wl = wb + ws;
-	    if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
-		atomic_inc(map->bp_toc);
-		if (slot == PCIIO_SLOT_NONE) {
-		    slot = cs;
-		    space = map->bp_space;
-		    if (cw < 6)
-			offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
-		}
-	    }
-	    }
-	}
-    }
-
-    if (space != PCIIO_SPACE_NONE) {
-	if (slot != PCIIO_SLOT_NONE) {
-#ifdef LATER
-	    if (func != PCIIO_FUNC_NONE)
-		IOERROR_SETVALUE(ioe, widgetdev, 
-				 pciio_widgetdev_create(slot,func));
-	    else
-    		IOERROR_SETVALUE(ioe, widgetdev, 
-				 pciio_widgetdev_create(slot,0));
-#else
-            if (func != PCIIO_FUNC_NONE) {
-                IOERROR_SETVALUE(ioe, widgetdev,
-                                 pciio_widgetdev_create(slot,func));
-            } else {
-                IOERROR_SETVALUE(ioe, widgetdev,
-                                 pciio_widgetdev_create(slot,0));
-	    }
-#endif
-	}
-
-	IOERROR_SETVALUE(ioe, busspace, space);
-	IOERROR_SETVALUE(ioe, busaddr, offset);
-    }
-    if (mode == MODE_DEVPROBE) {
-	/*
-	 * During probing, we don't really care what the
-	 * error is. Clean up the error in Bridge, notify
-	 * subsidiary devices, and return success.
-	 */
-	pcibr_error_cleanup(pcibr_soft, error_code);
-
-	/* if appropriate, give the error handler for this slot
-	 * a shot at this probe access as well.
-	 */
-	return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
-	    pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-    }
-    /*
-     * If we don't know what "PCI SPACE" the access
-     * was targeting, we may have problems at the
-     * Bridge itself. Don't touch any bridge registers,
-     * and do complain loudly.
-     */
-
-    if (space == PCIIO_SPACE_NONE) {
-	printk("XIO Bus Error at %s\n"
-		"\taccess to XIO bus offset 0x%lx\n"
-		"\tdoes not correspond to any PCI address\n",
-		pcibr_soft->bs_name, bad_xaddr);
-
-	/* caller will dump contents of ioe struct */
-	return IOERROR_XTALKLEVEL;
-    }
-    /*
-     * Read the PCI Bridge error log registers.
-     */
-    bridge_int_status = bridge->b_int_status;
-    bridge_pci_err_upper = bridge->b_pci_err_upper;
-    bridge_pci_err_lower = bridge->b_pci_err_lower;
-
-    bridge_pci_err_addr =
-	bridge_pci_err_lower
-	| (((iopaddr_t) bridge_pci_err_upper
-	    & BRIDGE_ERRUPPR_ADDRMASK) << 32);
-
-    /*
-     * Actual PCI Error handling situation.
-     * Typically happens when a user level process accesses
-     * PCI space, and it causes some error.
-     *
-     * Due to PCI Bridge implementation, we get two indication
-     * for a read error: an interrupt and a Bus error.
-     * We like to handle read error in the bus error context.
-     * But the interrupt comes and goes before bus error
-     * could make much progress. (NOTE: interrupd does
-     * come in _after_ bus error processing starts. But it's
-     * completed by the time bus error code reaches PCI PIO
-     * error handling.
-     * Similarly write error results in just an interrupt,
-     * and error handling has to be done at interrupt level.
-     * There is no way to distinguish at interrupt time, if an
-     * error interrupt is due to read/write error..
-     */
-
-    /* We know the xtalk addr, the raw PCI bus space,
-     * the raw PCI bus address, the decoded PCI bus
-     * space, the offset within that space, and the
-     * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
-     * is known to be involved).
-     */
-
-    /*
-     * Hand the error off to the handler registered
-     * for the slot that should have decoded the error,
-     * or to generic PCI handling (if pciio decides that
-     * such is appropriate).
-     */
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-
-    if (retval != IOERROR_HANDLED) {
-
-	/* Generate a generic message for IOERROR_UNHANDLED
-	 * since the subsidiary handlers were silent, and
-	 * did no recovery.
-	 */
-	if (retval == IOERROR_UNHANDLED) {
-	    retval = IOERROR_PANIC;
-
-	    /* we may or may not want to print some of this,
-	     * depending on debug level and which error code.
-	     */
-
-	    PRINT_ALERT(
-		    "PIO Error on PCI Bus %s",
-		    pcibr_soft->bs_name);
-	    /* this decodes part of the ioe; our caller
-	     * will dump the raw details in DEBUG and
-	     * kdebug kernels.
-	     */
-	    BEM_ADD_IOE(ioe);
-	}
-#if defined(FORCE_ERRORS)
-	if (0) {
-#elif !DEBUG
-	if (kdebug) {
-#endif
-	    /*
-	       * dump raw data from bridge
-	     */
-
-	    BEM_ADD_STR("DEBUG DATA -- raw info from Bridge ASIC:\n");
-	    BEM_ADD_REG(bridge_int_status);
-	    BEM_ADD_VAR(bridge_pci_err_upper);
-	    BEM_ADD_VAR(bridge_pci_err_lower);
-	    BEM_ADD_VAR(bridge_pci_err_addr);
-	    BEM_ADD_SPC(raw_space);
-	    BEM_ADD_VAR(raw_paddr);
-	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {
-
-#ifdef LATER
-		slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, 
-								 widgetdev));
-		func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, 
-								 widgetdev));
-#else
-		slot = -1;
-		func = -1;
-#endif
-		if (slot < 8) {
-#ifdef SUPPORT_SGI_CMN_ERR_STUFF
-		    bridgereg_t             device = bridge->b_device[slot].reg;
-#endif
-
-		    BEM_ADD_VAR(slot);
-		    BEM_ADD_VAR(func);
-		    BEM_ADD_REG(device);
-		}
-	    }
-#if !DEBUG || defined(FORCE_ERRORS)
-	}
-#endif
-
-	/*
-	 * Since error could not be handled at lower level,
-	 * error data logged has not  been cleared.
-	 * Clean up errors, and
-	 * re-enable bridge to interrupt on error conditions.
-	 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
-	 * dependent on INT_ENABLE register. This write just makes sure
-	 * that if the interrupt was enabled, we do get the interrupt.
-	 *
-	 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
-	 *      a group of interrupts. If while handling this error,
-	 *      some other error has occurred, that would be
-	 *      implicitly cleared by this write.
-	 *      Need a way to ensure we don't inadvertently clear some
-	 *      other errors.
-	 */
-#ifdef LATER
-	if (IOERROR_FIELDVALID(ioe, widgetdev))
-	    pcibr_device_disable(pcibr_soft, 
-				 pciio_widgetdev_slot_get(
-					  IOERROR_GETVALUE(ioe, widgetdev)));
-#endif
-
-	if (mode == MODE_DEVUSERERROR)
-	    pcibr_error_cleanup(pcibr_soft, error_code);
-    }
-    return retval;
-}
-
-/*
- * bridge_dmaerror
- *      Some error was identified in a DMA transaction.
- *      This routine will identify the <device, address> that caused the error,
- *      and try to invoke the appropriate bus service to handle this.
- */
-
-#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT)
-
-int
-pcibr_dmard_error(
-		     pcibr_soft_t pcibr_soft,
-		     int error_code,
-		     ioerror_mode_t mode,
-		     ioerror_t *ioe)
-{
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             bus_lowaddr, bus_uppraddr;
-    int                     retval = 0;
-    int                     bufnum;
-
-    /*
-     * In case of DMA errors, bridge should have logged the
-     * address that caused the error.
-     * Look up the address, in the bridge error registers, and
-     * take appropriate action
-     */
-#ifdef LATER
-    ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid);
-    ASSERT(bridge);
-#endif
-
-    /*
-     * read error log registers
-     */
-    bus_lowaddr = bridge->b_wid_resp_lower;
-    bus_uppraddr = bridge->b_wid_resp_upper;
-
-    bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
-    IOERROR_SETVALUE(ioe, widgetdev, 
-		     pciio_widgetdev_create(
-				    BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
-				    0));
-    IOERROR_SETVALUE(ioe, busaddr,
-		     (bus_lowaddr |
-		      ((iopaddr_t)
-		       (bus_uppraddr &
-			BRIDGE_ERRUPPR_ADDRMASK) << 32)));
-
-    /*
-     * need to ensure that the xtalk address in ioe
-     * maps to PCI error address read from bridge.
-     * How to convert PCI address back to Xtalk address ?
-     * (better idea: convert XTalk address to PCI address
-     * and then do the compare!)
-     */
-
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-    if (retval != IOERROR_HANDLED)
-#ifdef LATER
-	pcibr_device_disable(pcibr_soft, 
-			     pciio_widgetdev_slot_get(
-				      IOERROR_GETVALUE(ioe,widgetdev)));
-#else
-	pcibr_device_disable(pcibr_soft,
-			     pciio_widgetdev_slot_get(-1));
-#endif
-
-    /*
-     * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
-     * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
-     * not is dependent on INT_ENABLE register. This write just makes sure
-     * that if the interrupt was enabled, we do get the interrupt.
-     */
-    bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
-
-    /*
-     * Also, release the "bufnum" back to buffer pool that could be re-used.
-     * This is done by "disabling" the buffer for a moment, then restoring
-     * the original assignment.
-     */
-
-    {
-	reg_p                   regp;
-	bridgereg_t             regv;
-	bridgereg_t             mask;
-
-	regp = (bufnum & 1)
-	    ? &bridge->b_odd_resp
-	    : &bridge->b_even_resp;
-
-	mask = 0xF << ((bufnum >> 1) * 4);
-
-	regv = *regp;
-	*regp = regv & ~mask;
-	*regp = regv;
-    }
-
-    return retval;
-}
-
-/*
- * pcibr_dmawr_error:
- *      Handle a dma write error caused by a device attached to this bridge.
- *
- *      ioe has the widgetnum, widgetdev, and memaddr fields updated
- *      But we don't know the PCI address that corresponds to "memaddr"
- *      nor do we know which device driver is generating this address.
- *
- *      There is no easy way to find out the PCI address(es) that map
- *      to a specific system memory address. Bus handling code is also
- *      of not much help, since they don't keep track of the DMA mapping
- *      that have been handed out.
- *      So it's a dead-end at this time.
- *
- *      If translation is available, we could invoke the error handling
- *      interface of the device driver.
- */
-/*ARGSUSED */
-int
-pcibr_dmawr_error(
-		     pcibr_soft_t pcibr_soft,
-		     int error_code,
-		     ioerror_mode_t mode,
-		     ioerror_t *ioe)
-{
-    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
-    int                     retval;
-
-    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
-
-#ifdef LATER
-    if (retval != IOERROR_HANDLED) {
-	pcibr_device_disable(pcibr_soft, 
-			     pciio_widgetdev_slot_get(
-				      IOERROR_GETVALUE(ioe, widgetdev)));
-
-    }
-#endif
-    return retval;
-}
-
-/*
- * Bridge error handler.
- *      Interface to handle all errors that involve bridge in some way.
- *
- *      This normally gets called from xtalk error handler.
- *      ioe has different set of fields set depending on the error that
- *      was encountered. So, we have a bit field indicating which of the
- *      fields are valid.
- *
- * NOTE: This routine could be operating in interrupt context. So,
- *      don't try to sleep here (till interrupt threads work!!)
- */
-LOCAL int
-pcibr_error_handler(
-		       error_handler_arg_t einfo,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioe)
-{
-    pcibr_soft_t            pcibr_soft;
-    int                     retval = IOERROR_BADERRORCODE;
-
-    pcibr_soft = (pcibr_soft_t) einfo;
-
-    /* If we are in the action handling phase clean out the error state
-     * on the xswitch.
-     */
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-    if (e_state == ERROR_STATE_ACTION)
-	(void)error_state_set(xconn_vhdl, ERROR_STATE_NONE);
-#endif
-
-#if DEBUG && ERROR_DEBUG
-    printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name);
-#endif
-
-    ASSERT(pcibr_soft != NULL);
-
-    if (error_code & IOECODE_PIO)
-	retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
-
-    if (error_code & IOECODE_DMA) {
-	if (error_code & IOECODE_READ) {
-	    /*
-	     * DMA read error occurs when a device attached to the bridge
-	     * tries to read some data from system memory, and this
-	     * either results in a timeout or access error.
-	     * First case is indicated by the bit "XREAD_REQ_TOUT"
-	     * and second case by "RESP_XTALK_ERROR" bit in bridge error
-	     * interrupt status register.
-	     *
-	     * pcibr_error_intr_handler would get invoked first, and it has
-	     * the responsibility of calling pcibr_error_handler with
-	     * suitable parameters.
-	     */
-
-	    retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
-	}
-	if (error_code & IOECODE_WRITE) {
-	    /*
-	     * A device attached to this bridge has been generating
-	     * bad DMA writes. Find out the device attached, and
-	     * slap on it's wrist.
-	     */
-
-	    retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
-	}
-    }
-    return retval;
-
-}
-
-/*
- * Reenable a device after handling the error.
- * This is called by the lower layers when they wish to be reenabled
- * after an error.
- * Note that each layer would be calling the previous layer to reenable
- * first, before going ahead with their own re-enabling.
- */
-
-int
-pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    ASSERT(error_code & IOECODE_PIO);
-
-    /* If the error is not known to be a write,
-     * we have to call devenable.
-     * write errors are isolated to the bridge.
-     */
-    if (!(error_code & IOECODE_WRITE)) {
-	devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
-	int                     rc;
-
-	rc = xtalk_error_devenable(xconn_vhdl, pciio_slot, error_code);
-	if (rc != IOERROR_HANDLED)
-	    return rc;
-    }
-    pcibr_error_cleanup(pcibr_soft, error_code);
-    return IOERROR_HANDLED;
-}
-
-/* =====================================================================
- *    CONFIGURATION MANAGEMENT
- */
-/*ARGSUSED */
-void
-pcibr_provider_startup(devfs_handle_t pcibr)
-{
-}
-
-/*ARGSUSED */
-void
-pcibr_provider_shutdown(devfs_handle_t pcibr)
-{
-}
-
-int
-pcibr_reset(devfs_handle_t conn)
-{
-    pciio_info_t            pciio_info = pciio_info_get(conn);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridge_t               *bridge = pcibr_soft->bs_base;
-    bridgereg_t             ctlreg;
-    unsigned                cfgctl[8];
-    unsigned long           s;
-    int                     f, nf;
-    pcibr_info_h            pcibr_infoh;
-    pcibr_info_t            pcibr_info;
-    int                     win;
-
-    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
-	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
-	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
-    }
-    if (pciio_slot < 4) {
-	s = pcibr_lock(pcibr_soft);
-	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
-	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
-	for (f = 0; f < nf; ++f)
-	    if (pcibr_infoh[f])
-		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
-
-	ctlreg = bridge->b_wid_control;
-	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
-	/* XXX delay? */
-	bridge->b_wid_control = ctlreg;
-	/* XXX delay? */
-
-	for (f = 0; f < nf; ++f)
-	    if ((pcibr_info = pcibr_infoh[f]))
-		for (win = 0; win < 6; ++win)
-		    if (pcibr_info->f_window[win].w_base != 0)
-			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
-			    pcibr_info->f_window[win].w_base;
-	for (f = 0; f < nf; ++f)
-	    if (pcibr_infoh[f])
-		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
-	pcibr_unlock(pcibr_soft, s);
-
-	return 0;
-    }
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    PRINT_WARNING( "%v: pcibr_reset unimplemented for slot %d\n",
-	    conn, pciio_slot);
-#endif
-    return -1;
-}
-
-pciio_endian_t
-pcibr_endian_set(devfs_handle_t pconn_vhdl,
-		 pciio_endian_t device_end,
-		 pciio_endian_t desired_end)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridgereg_t             devreg;
-    unsigned long           s;
-
-    /*
-     * Bridge supports hardware swapping; so we can always
-     * arrange for the caller's desired endianness.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-    if (device_end != desired_end)
-	devreg |= BRIDGE_DEV_SWAP_BITS;
-    else
-	devreg &= ~BRIDGE_DEV_SWAP_BITS;
-
-    /* NOTE- if we ever put SWAP bits
-     * onto the disabled list, we will
-     * have to change the logic here.
-     */
-    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-
-	bridge->b_device[pciio_slot].reg = devreg;
-	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-#if DEBUG && PCIBR_DEV_DEBUG
-    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
-#endif
-
-    return desired_end;
-}
-
-/* This (re)sets the GBR and REALTIME bits and also keeps track of how
- * many sets are outstanding. Reset succeeds only if the number of outstanding
- * sets == 1.
- */
-int
-pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
-			pciio_slot_t pciio_slot,
-			pciio_priority_t device_prio)
-{
-    unsigned long           s;
-    int                    *counter;
-    bridgereg_t             rtbits = 0;
-    bridgereg_t             devreg;
-    int                     rc = PRIO_SUCCESS;
-
-    /* in dual-slot configurations, the host and the
-     * guest have separate DMA resources, so they
-     * have separate requirements for priority bits.
-     */
-
-    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
-
-    /*
-     * Bridge supports PCI notions of LOW and HIGH priority
-     * arbitration rings via a "REAL_TIME" bit in the per-device
-     * Bridge register. The "GBR" bit controls access to the GBR
-     * ring on the xbow. These two bits are (re)set together.
-     *
-     * XXX- Bug in Rev B Bridge Si:
-     * Symptom: Prefetcher starts operating incorrectly. This happens
-     * due to corruption of the address storage ram in the prefetcher
-     * when a non-real time PCI request is pulled and a real-time one is
-     * put in it's place. Workaround: Use only a single arbitration ring
-     * on PCI bus. GBR and RR can still be uniquely used per
-     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
-     */
-
-    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
-	rtbits |= BRIDGE_DEV_RT;
-
-    /* NOTE- if we ever put DEV_RT or DEV_GBR on
-     * the disabled list, we will have to take
-     * it into account here.
-     */
-
-    s = pcibr_lock(pcibr_soft);
-    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-    if (device_prio == PCI_PRIO_HIGH) {
-	if ((++*counter == 1)) {
-	    if (rtbits)
-		devreg |= rtbits;
-	    else
-		rc = PRIO_FAIL;
-	}
-    } else if (device_prio == PCI_PRIO_LOW) {
-	if (*counter <= 0)
-	    rc = PRIO_FAIL;
-	else if (--*counter == 0)
-	    if (rtbits)
-		devreg &= ~rtbits;
-    }
-    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	bridge_t               *bridge = pcibr_soft->bs_base;
-
-	bridge->b_device[pciio_slot].reg = devreg;
-	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
-    }
-    pcibr_unlock(pcibr_soft, s);
-
-    return rc;
-}
-
-pciio_priority_t
-pcibr_priority_set(devfs_handle_t pconn_vhdl,
-		   pciio_priority_t device_prio)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-
-    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
-
-    return device_prio;
-}
-
-/*
- * Interfaces to allow special (e.g. SGI) drivers to set/clear
- * Bridge-specific device flags.  Many flags are modified through
- * PCI-generic interfaces; we don't allow them to be directly
- * manipulated here.  Only flags that at this point seem pretty
- * Bridge-specific can be set through these special interfaces.
- * We may add more flags as the need arises, or remove flags and
- * create PCI-generic interfaces as the need arises.
- *
- * Returns 0 on failure, 1 on success
- */
-int
-pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
-		       pcibr_device_flags_t flags)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-    bridgereg_t             set = 0;
-    bridgereg_t             clr = 0;
-
-    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
-
-    if (flags & PCIBR_WRITE_GATHER)
-	set |= BRIDGE_DEV_PMU_WRGA_EN;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	clr |= BRIDGE_DEV_PMU_WRGA_EN;
-
-    if (flags & PCIBR_WRITE_GATHER)
-	set |= BRIDGE_DEV_DIR_WRGA_EN;
-    if (flags & PCIBR_NOWRITE_GATHER)
-	clr |= BRIDGE_DEV_DIR_WRGA_EN;
-
-    if (flags & PCIBR_PREFETCH)
-	set |= BRIDGE_DEV_PREF;
-    if (flags & PCIBR_NOPREFETCH)
-	clr |= BRIDGE_DEV_PREF;
-
-    if (flags & PCIBR_PRECISE)
-	set |= BRIDGE_DEV_PRECISE;
-    if (flags & PCIBR_NOPRECISE)
-	clr |= BRIDGE_DEV_PRECISE;
-
-    if (flags & PCIBR_BARRIER)
-	set |= BRIDGE_DEV_BARRIER;
-    if (flags & PCIBR_NOBARRIER)
-	clr |= BRIDGE_DEV_BARRIER;
-
-    if (flags & PCIBR_64BIT)
-	set |= BRIDGE_DEV_DEV_SIZE;
-    if (flags & PCIBR_NO64BIT)
-	clr |= BRIDGE_DEV_DEV_SIZE;
-
-    if (set || clr) {
-	bridgereg_t             devreg;
-	unsigned long           s;
-
-	s = pcibr_lock(pcibr_soft);
-	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
-	devreg = (devreg & ~clr) | set;
-	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
-	    bridge_t               *bridge = pcibr_soft->bs_base;
-
-	    bridge->b_device[pciio_slot].reg = devreg;
-	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
-	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
-	}
-	pcibr_unlock(pcibr_soft, s);
-#if DEBUG && PCIBR_DEV_DEBUG
-	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
-#endif
-    }
-    return (1);
-}
-
-#ifdef LITTLE_ENDIAN
-/*
- * on sn-ia we need to twiddle the addresses going out
- * the pci bus because we use the unswizzled synergy space
- * (the alternative is to use the swizzled synergy space
- * and byte swap the data)
- */
-#define	CB(b,r)	(((volatile uint8_t *) b)[((r)^4)])
-#define	CS(b,r)	(((volatile uint16_t *) b)[((r^4)/2)])
-#define	CW(b,r)	(((volatile uint32_t *) b)[((r^4)/4)])
-#else
-#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
-#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
-#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
-#endif /* LITTLE_ENDIAN */
-
-
-LOCAL                   cfg_p
-pcibr_config_addr(devfs_handle_t conn,
-		  unsigned reg)
-{
-    pcibr_info_t            pcibr_info;
-    pciio_slot_t            pciio_slot;
-    pciio_function_t        pciio_func;
-    pcibr_soft_t            pcibr_soft;
-    bridge_t               *bridge;
-    cfg_p                   cfgbase = (cfg_p)0;
-
-    pcibr_info = pcibr_info_get(conn);
-
-    pciio_slot = pcibr_info->f_slot;
-    if (pciio_slot == PCIIO_SLOT_NONE)
-	pciio_slot = PCI_TYPE1_SLOT(reg);
-
-    pciio_func = pcibr_info->f_func;
-    if (pciio_func == PCIIO_FUNC_NONE)
-	pciio_func = PCI_TYPE1_FUNC(reg);
-
-    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
-
-    bridge = pcibr_soft->bs_base;
-
-    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
-
-    return cfgbase;
-}
-
-uint64_t
-pcibr_config_get(devfs_handle_t conn,
-		 unsigned reg,
-		 unsigned size)
-{
-    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
-			       PCI_TYPE1_REG(reg), size);
-}
-
-LOCAL uint64_t
-do_pcibr_config_get(
-		       cfg_p cfgbase,
-		       unsigned reg,
-		       unsigned size)
-{
-    unsigned                value;
-
-   
-    value = CW(cfgbase, reg);
-
-    if (reg & 3)
-	value >>= 8 * (reg & 3);
-    if (size < 4)
-	value &= (1 << (8 * size)) - 1;
-
-    return value;
-}
-
-void
-pcibr_config_set(devfs_handle_t conn,
-		 unsigned reg,
-		 unsigned size,
-		 uint64_t value)
-{
-    do_pcibr_config_set(pcibr_config_addr(conn, reg),
-			PCI_TYPE1_REG(reg), size, value);
-}
-
-LOCAL void
-do_pcibr_config_set(cfg_p cfgbase,
-		    unsigned reg,
-		    unsigned size,
-		    uint64_t value)
-{
-    switch (size) {
-    case 1:
-	CB(cfgbase, reg) = value;
-	break;
-    case 2:
-	if (reg & 1) {
-	    CB(cfgbase, reg) = value;
-	    CB(cfgbase, reg + 1) = value >> 8;
-	} else
-	    CS(cfgbase, reg) = value;
-	break;
-    case 3:
-	if (reg & 1) {
-	    CB(cfgbase, reg) = value;
-	    CS(cfgbase, (reg + 1)) = value >> 8;
-	} else {
-	    CS(cfgbase, reg) = value;
-	    CB(cfgbase, reg + 2) = value >> 16;
-	}
-	break;
-
-    case 4:
-	CW(cfgbase, reg) = value;
-	break;
-    }
-}
-
-pciio_provider_t        pcibr_provider =
-{
-    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
-    (pciio_piomap_free_f *) pcibr_piomap_free,
-    (pciio_piomap_addr_f *) pcibr_piomap_addr,
-    (pciio_piomap_done_f *) pcibr_piomap_done,
-    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
-    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
-    (pciio_piospace_free_f *) pcibr_piospace_free,
-
-    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
-    (pciio_dmamap_free_f *) pcibr_dmamap_free,
-    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
-    (pciio_dmamap_list_f *) pcibr_dmamap_list,
-    (pciio_dmamap_done_f *) pcibr_dmamap_done,
-    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
-    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
-    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
-    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
-    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
-
-    (pciio_intr_alloc_f *) pcibr_intr_alloc,
-    (pciio_intr_free_f *) pcibr_intr_free,
-    (pciio_intr_connect_f *) pcibr_intr_connect,
-    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
-    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
-
-    (pciio_provider_startup_f *) pcibr_provider_startup,
-    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
-    (pciio_reset_f *) pcibr_reset,
-    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
-    (pciio_endian_set_f *) pcibr_endian_set,
-    (pciio_priority_set_f *) pcibr_priority_set,
-    (pciio_config_get_f *) pcibr_config_get,
-    (pciio_config_set_f *) pcibr_config_set,
-
-    (pciio_error_devenable_f *) pcibr_error_devenable,
-    (pciio_error_extract_f *) pcibr_error_extract,
-
-#ifdef LATER
-    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
-    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
-#else
-    (pciio_driver_reg_callback_f *) 0,
-    (pciio_driver_unreg_callback_f *) 0,
-#endif
-    (pciio_device_unregister_f 	*) pcibr_device_unregister,
-    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
-};
-
-LOCAL                   pcibr_hints_t
-pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
-{
-    arbitrary_info_t        ainfo = 0;
-    graph_error_t	    rv;
-    pcibr_hints_t           hint;
-
-    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
-
-    if (alloc && (rv != GRAPH_SUCCESS)) {
-
-	NEW(hint);
-	hint->rrb_alloc_funct = NULL;
-	hint->ph_intr_bits = NULL;
-	rv = hwgraph_info_add_LBL(xconn_vhdl, 
-				  INFO_LBL_PCIBR_HINTS, 	
-				  (arbitrary_info_t) hint);
-	if (rv != GRAPH_SUCCESS)
-	    goto abnormal_exit;
-
-	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
-	
-	if (rv != GRAPH_SUCCESS)
-	    goto abnormal_exit;
-
-	if (ainfo != (arbitrary_info_t) hint)
-	    goto abnormal_exit;
-    }
-    return (pcibr_hints_t) ainfo;
-
-abnormal_exit:
-#ifdef LATER
-    printf("SHOULD NOT BE HERE\n");
-#endif
-    DEL(hint);
-    return(NULL);
-
-}
-
-void
-pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_rrb_fixed = mask;
-#if DEBUG
-    else
-	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
-{
-    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
-}
-
-void
-pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
-		     pciio_slot_t host,
-		     pciio_slot_t guest)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_host_slot[guest] = host + 1;
-#if DEBUG
-    else
-	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
-		      pcibr_intr_bits_f *xxx_intr_bits)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_intr_bits = xxx_intr_bits;
-#if DEBUG
-    else
-	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
-	       "\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->rrb_alloc_funct = rrb_alloc_funct;
-}
-
-void
-pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
-{
-    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
-
-    if (hint)
-	hint->ph_hands_off = 1;
-#if DEBUG
-    else
-	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
-		"\t%p\n", xconn_vhdl);
-#endif
-}
-
-void
-pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
-		    pciio_slot_t slot,
-		    uint64_t subdevs)
-{
-    arbitrary_info_t        ainfo = 0;
-    char                    sdname[16];
-    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
-
-    sprintf(sdname, "pci/%d", slot);
-    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
-    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
-#if DEBUG
-	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
-		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
-#endif
-	return;
-    }
-    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
-    if (ainfo == 0) {
-	uint64_t                *subdevp;
-
-	NEW(subdevp);
-	if (!subdevp) {
-#if DEBUG
-	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
-		    "\t%p\n", pconn_vhdl);
-#endif
-	    return;
-	}
-	*subdevp = subdevs;
-	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
-	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
-	if (ainfo == (arbitrary_info_t) subdevp)
-	    return;
-	DEL(subdevp);
-	if (ainfo == (arbitrary_info_t) NULL) {
-#if DEBUG
-	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
-		    "\t%p\n", pconn_vhdl);
-#endif
-	    return;
-	}
-#if DEBUG
-	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
-		"\t%p\n", pconn_vhdl);
-#endif
-    }
-    *(uint64_t *) ainfo = subdevs;
-}
-
-
-#ifdef LATER
-
-#include <sys/idbg.h>
-#include <sys/idbgentry.h>
-
-char *pci_space[] = {"NONE", 
-		     "ROM",
-		     "IO",
-		     "",
-		     "MEM",
-		     "MEM32",
-		     "MEM64",
-		     "CFG",
-		     "WIN0",
-		     "WIN1",
-		     "WIN2",
-		     "WIN3",
-		     "WIN4",
-		     "WIN5",
-		     "",
-		     "BAD"};
-
-void
-idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
-{
-    pcibr_info_t	pcibr_info = pcibr_infoh[func];
-    char		name[MAXDEVNAME];
-    int			win;
-    
-    if (!pcibr_info)
-	return;
-    qprintf("Per-slot Function Info\n");
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(name, "%v", pcibr_info->f_vertex);
-#endif
-    qprintf("\tSlot Name : %s\n",name);
-    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
-    qprintf("Slot : %d ", pcibr_info->f_slot);
-    qprintf("Function : %d ", pcibr_info->f_func);
-    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
-    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    sprintf(name, "%v", pcibr_info->f_master);
-#endif
-    qprintf("\tBus provider : %s\n",name);
-    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
-    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
-	    pcibr_info->f_efunc,pcibr_info->f_einfo);
-    for(win = 0 ; win < 6 ; win++) 
-	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
-		win,pci_space[pcibr_info->f_window[win].w_space],
-		pcibr_info->f_window[win].w_base,
-		pcibr_info->f_window[win].w_size);
-
-    qprintf("\tRom base 0x%x size 0x%x\n", 
-	    pcibr_info->f_rbase,pcibr_info->f_rsize);
-
-    qprintf("\tInterrupt Bit Map\n");
-    qprintf("\t\tPCI Int#\tBridge Pin#\n");
-    for (win = 0 ; win < 4; win++)
-	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
-    qprintf("\n");
-}
-
-
-void
-idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
-{
-    pcibr_soft_slot_t	pss;
-    char		slot_conn_name[MAXDEVNAME];
-    int			func;
-
-    pss = &pcibr_soft->bs_slot[slot];
-    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
-    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
-    qprintf("\tHost Slot : %d\n",pss->host_slot);
-    sprintf(slot_conn_name, "%v", pss->slot_conn);
-    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
-    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
-    for (func = 0; func < pss->bss_ninfo; func++)
-	idbg_pss_func(pss->bss_infos,func);
-    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
-    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
-    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
-    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
-	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
-    
-    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
-	    "d32_base 0x%x d32_flags 0x%x\n",
-	    pss->bss_d64_base, pss->bss_d64_flags,
-	    pss->bss_d32_base, pss->bss_d32_flags);
-    
-    qprintf("\tExt ATEs active ? %s", 
-	    atomic_read(&pss->bss_ext_ates_active) ? "yes" : "no");
-    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
-    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
-
-    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
-	    pcibr_soft->bs_rrb_valid[slot],
-	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
-	    pcibr_soft->bs_rrb_res[slot]);
-		
-}
-
-int	ips = 0;
-
-void
-idbg_pss(pcibr_soft_t pcibr_soft)
-{
-    pciio_slot_t	slot;
-
-    
-    if (ips >= 0 && ips < 8)
-	idbg_pss_info(pcibr_soft,ips);
-    else if (ips < 0)
-	for (slot = 0; slot < 8; slot++) 
-	    idbg_pss_info(pcibr_soft,slot);
-    else
-	qprintf("Invalid ips %d\n",ips);
-}
-
-#endif /* LATER */
-
-int
-pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
-{
-    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
-    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
-	
-
-    return xtalk_dma_enabled(pcibr_soft->bs_conn);
-}
diff -Nru a/arch/ia64/sn/io/pciio.c b/arch/ia64/sn/io/pciio.c
--- a/arch/ia64/sn/io/pciio.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/pciio.c	Fri Mar 15 17:51:03 2002
@@ -4,14 +4,18 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #define	USRPCI	0
 
+#include <linux/init.h>
 #include <linux/types.h>
 #include <linux/config.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
 #include <asm/sn/xtalk/xbow.h>	/* Must be before iograph.h to get MAX_PORT_NUM */
@@ -25,13 +29,16 @@
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/pci/pciio_private.h>
 #include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/pci/pci_bus_cvlink.h>
+#include <asm/sn/simulator.h>
 
 #define DEBUG_PCIIO
 #undef DEBUG_PCIIO	/* turn this on for yet more console output */
 
 
-#define NEW(ptr)	(ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
-#define DEL(ptr)	(kfree(ptr))
+#define GET_NEW(ptr)	(ptr = kmalloc(sizeof (*(ptr)), GFP_KERNEL))
+#define DO_DEL(ptr)	(kfree(ptr))
 
 char                    pciio_info_fingerprint[] = "pciio_info";
 
@@ -63,6 +70,14 @@
 get_console_nasid(void)
 {
 	extern nasid_t console_nasid;
+	if (console_nasid < 0) {
+		console_nasid = ia64_sn_get_console_nasid();
+		if (console_nasid < 0) {
+// ZZZ What do we do if we don't get a console nasid on the hardware????
+			if (IS_RUNNING_ON_SIMULATOR() )
+				console_nasid = master_nasid;
+		}
+	} 
 	return console_nasid;
 }
 
@@ -105,7 +120,7 @@
  * completely disappear.
  */
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
+#if defined(CONFIG_IA64_SGI_SN1)
 /*
  *    For the moment, we will assume that IP27
  *      only use Bridge ASICs to provide PCI support.
@@ -115,7 +130,7 @@
 #define CAST_PIOMAP(x)		((pcibr_piomap_t)(x))
 #define CAST_DMAMAP(x)		((pcibr_dmamap_t)(x))
 #define CAST_INTR(x)		((pcibr_intr_t)(x))
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
 /* =====================================================================
  *    Function Table of Contents
@@ -150,14 +165,11 @@
 
 pciio_intr_t            pciio_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
 void                    pciio_intr_free(pciio_intr_t);
-int                     pciio_intr_connect(pciio_intr_t, intr_func_t, intr_arg_t, void *thread);
+int                     pciio_intr_connect(pciio_intr_t);
 void                    pciio_intr_disconnect(pciio_intr_t);
 devfs_handle_t            pciio_intr_cpu_get(pciio_intr_t);
 
 void			pciio_slot_func_to_name(char *, pciio_slot_t, pciio_function_t);
-static pciio_info_t     pciio_cardinfo_get(devfs_handle_t, pciio_slot_t);
-int                     pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
-int                     pciio_error_devenable(devfs_handle_t, int);
 
 void                    pciio_provider_startup(devfs_handle_t);
 void                    pciio_provider_shutdown(devfs_handle_t);
@@ -257,7 +269,7 @@
 #if defined(SUPPORT_PRINTING_V_FORMAT)
 	PRINT_PANIC("%v: provider_fns == NULL", dev);
 #else
-	PRINT_PANIC("0x%x: provider_fns == NULL", dev);
+	PRINT_PANIC("0x%p: provider_fns == NULL", (void *)dev);
 #endif
 
     return provider_fns;
@@ -575,13 +587,10 @@
  * Returns 0 on success, returns <0 on failure.
  */
 int
-pciio_intr_connect(pciio_intr_t intr_hdl,	/* pciio intr resource handle */
-		   intr_func_t intr_func,	/* pciio intr handler */
-		   intr_arg_t intr_arg,	/* arg to intr handler */
-		   void *thread)
-{					/* intr thread to use */
+pciio_intr_connect(pciio_intr_t intr_hdl)	/* pciio intr resource handle */
+{
     return INTR_FUNC(intr_hdl, intr_connect)
-	(CAST_INTR(intr_hdl), intr_func, intr_arg, thread);
+	(CAST_INTR(intr_hdl));
 }
 
 /*
@@ -605,10 +614,6 @@
 	(CAST_INTR(intr_hdl));
 }
 
-/* =====================================================================
- *          ERROR MANAGEMENT
- */
-
 void
 pciio_slot_func_to_name(char		       *name,
 			pciio_slot_t		slot,
@@ -630,193 +635,6 @@
 	sprintf(name, "%d%c", slot, 'a'+func);
 }
 
-/*
- * pciio_cardinfo_get
- *
- * Get the pciio info structure corresponding to the
- * specified PCI "slot" (we like it when the same index
- * number is used for the PCI IDSEL, the REQ/GNT pair,
- * and the interrupt line being used for INTA. We like
- * it so much we call it the slot number).
- */
-static pciio_info_t
-pciio_cardinfo_get(
-		      devfs_handle_t pciio_vhdl,
-		      pciio_slot_t pci_slot)
-{
-    char                    namebuf[16];
-    pciio_info_t	    info = 0;
-    devfs_handle_t	    conn;
-
-    pciio_slot_func_to_name(namebuf, pci_slot, PCIIO_FUNC_NONE);
-    if (GRAPH_SUCCESS ==
-	hwgraph_traverse(pciio_vhdl, namebuf, &conn)) {
-	info = pciio_info_chk(conn);
-	hwgraph_vertex_unref(conn);
-    }
-
-    return info;
-}
-
-/*
- * pciio_error_handler:
- * dispatch an error to the appropriate
- * pciio connection point, or process
- * it as a generic pci error.
- * Yes, the first parameter is the
- * provider vertex at the middle of
- * the bus; we get to the pciio connect
- * point using the ioerror widgetdev field.
- *
- * This function is called by the
- * specific PCI provider, after it has figured
- * out where on the PCI bus (including which slot,
- * if it can tell) the error came from.
- */
-/*ARGSUSED */
-int
-pciio_error_handler(
-		       devfs_handle_t pciio_vhdl,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioerror)
-{
-    pciio_info_t            pciio_info;
-    devfs_handle_t            pconn_vhdl;
-#if USRPCI
-    devfs_handle_t            usrpci_v;
-#endif
-    pciio_slot_t            slot;
-
-    int                     retval;
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-    error_state_t	    e_state;
-#endif
-
-#if DEBUG && ERROR_DEBUG
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-    printk("%v: pciio_error_handler\n", pciio_vhdl);
-#else
-    printk("0x%x: pciio_error_handler\n", pciio_vhdl);
-#endif
-#endif
-
-#if defined(SUPPORT_PRINTING_V_FORMAT)
-    IOERR_PRINTF(printk("%v: PCI Bus Error: Error code: %d Error mode: %d\n",
-			 pciio_vhdl, error_code, mode));
-#else
-    IOERR_PRINTF(printk("0x%x: PCI Bus Error: Error code: %d Error mode: %d\n",
-			 pciio_vhdl, error_code, mode));
-#endif
-
-    /* If there is an error handler sitting on
-     * the "no-slot" connection point, give it
-     * first crack at the error. NOTE: it is
-     * quite possible that this function may
-     * do further refining of the ioerror.
-     */
-    pciio_info = pciio_cardinfo_get(pciio_vhdl, PCIIO_SLOT_NONE);
-    if (pciio_info && pciio_info->c_efunc) {
-	pconn_vhdl = pciio_info_dev_get(pciio_info);
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-	e_state = error_state_get(pciio_vhdl);
-
-	if (e_state == ERROR_STATE_ACTION)
-	    (void)error_state_set(pciio_vhdl, ERROR_STATE_NONE);
-
-	if (error_state_set(pconn_vhdl,e_state) ==
-	    ERROR_RETURN_CODE_CANNOT_SET_STATE)
-	    return(IOERROR_UNHANDLED);
-#endif
-	retval = pciio_info->c_efunc
-	    (pciio_info->c_einfo, error_code, mode, ioerror);
-	if (retval != IOERROR_UNHANDLED)
-	    return retval;
-    }
-
-    /* Is the error associated with a particular slot?
-     */
-    if (IOERROR_FIELDVALID(ioerror, widgetdev)) {
-	/*
-	 * NOTE : 
-	 * widgetdev is a 4byte value encoded as slot in the higher order
-	 * 2 bytes and function in the lower order 2 bytes.
-	 */
-#ifdef LATER
-	slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioerror, widgetdev));
-#else
-	slot = 0;
-#endif
-
-	/* If this slot has an error handler,
-	 * deliver the error to it.
-	 */
-	pciio_info = pciio_cardinfo_get(pciio_vhdl, slot);
-	if (pciio_info != NULL) {
-	    if (pciio_info->c_efunc != NULL) {
-
-		pconn_vhdl = pciio_info_dev_get(pciio_info);
-#if defined(CONFIG_SGI_IO_ERROR_HANDLING)
-		e_state = error_state_get(pciio_vhdl);
-
-
-		if (e_state == ERROR_STATE_ACTION)
-		    (void)error_state_set(pciio_vhdl, ERROR_STATE_NONE);
-
-
-
-		if (error_state_set(pconn_vhdl,e_state) ==
-		    ERROR_RETURN_CODE_CANNOT_SET_STATE)
-		    return(IOERROR_UNHANDLED);
-#endif
-		retval = pciio_info->c_efunc
-		    (pciio_info->c_einfo, error_code, mode, ioerror);
-		if (retval != IOERROR_UNHANDLED)
-		    return retval;
-	    }
-
-#if USRPCI
-	    /* If the USRPCI driver is available and
-	     * knows about this connection point,
-	     * deliver the error to it.
-	     *
-	     * OK to use pconn_vhdl here, even though we
-	     * have already UNREF'd it, since we know that
-	     * it is not going away.
-	     */
-	    pconn_vhdl = pciio_info_dev_get(pciio_info);
-	    if (GRAPH_SUCCESS ==
-		hwgraph_traverse(pconn_vhdl, EDGE_LBL_USRPCI, &usrpci_v)) {
-		retval = usrpci_error_handler
-		    (usrpci_v, error_code, IOERROR_GETVALUE(ioerror, busaddr));
-		hwgraph_vertex_unref(usrpci_v);
-		if (retval != IOERROR_UNHANDLED) {
-		    /*
-		     * This unref is not needed.  If this code is called often enough,
-		     * the system will crash, due to vertex reference count reaching 0,
-		     * causing vertex to be unallocated.  -jeremy
-		     * hwgraph_vertex_unref(pconn_vhdl);
-		     */
-		    return retval;
-		}
-	    }
-#endif
-	}
-    }
-
-    return (mode == MODE_DEVPROBE)
-	? IOERROR_HANDLED	/* probes are OK */
-	: IOERROR_UNHANDLED;	/* otherwise, foo! */
-}
-
-int
-pciio_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
-{
-    return DEV_FUNC(pconn_vhdl, error_devenable)
-	(pconn_vhdl, error_code);
-    /* no cleanup specific to this layer. */
-}
-
 /* =====================================================================
  *          CONFIGURATION MANAGEMENT
  */
@@ -856,12 +674,12 @@
 
 #if DEBUG
 #if defined(SUPPORT_PRINTING_V_FORMAT)
-    PRINT_ALERT("%v: pciio_endian_set is going away.\n"
+    printk(KERN_ALERT  "%v: pciio_endian_set is going away.\n"
 	    "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
 	    "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
 	    dev);
 #else
-    PRINT_ALERT("0x%x: pciio_endian_set is going away.\n"
+    printk(KERN_ALERT  "0x%x: pciio_endian_set is going away.\n"
 	    "\tplease use PCIIO_BYTE_STREAM or PCIIO_WORD_VALUES in your\n"
 	    "\tpciio_dmamap_alloc and pciio_dmatrans calls instead.\n",
 	    dev);
@@ -944,14 +762,6 @@
 /* =====================================================================
  *          GENERIC PCI SUPPORT FUNCTIONS
  */
-pciio_slot_t
-pciio_error_extract(devfs_handle_t 	dev,
-		   pciio_space_t 	*space,
-		   iopaddr_t		*offset)
-{
-	ASSERT(dev != NODEV);
-	return DEV_FUNC(dev,error_extract)(dev,space,offset);
-}
 
 /*
  * Issue a hardware reset to a card.
@@ -1054,14 +864,9 @@
     }
 #endif /* DEBUG_PCIIO */
 
-#ifdef BRINGUP
     if ((pciio_info != NULL) &&
 	(pciio_info->c_fingerprint != pciio_info_fingerprint)
 	&& (pciio_info->c_fingerprint != NULL)) {
-#else
-    if ((pciio_info != NULL) &&
-	(pciio_info->c_fingerprint != pciio_info_fingerprint)) {
-#endif /* BRINGUP */
 
 	return((pciio_info_t)-1); /* Should panic .. */
     }
@@ -1388,7 +1193,7 @@
 		pciio_device_id_t device_id)
 {
     if (!pciio_info)
-	NEW(pciio_info);
+	GET_NEW(pciio_info);
     ASSERT(pciio_info != NULL);
 
     pciio_info->c_slot = slot;
@@ -1420,6 +1225,7 @@
 {
     char		name[32];
     devfs_handle_t	pconn;
+    int device_master_set(devfs_handle_t, devfs_handle_t);
 
     pciio_slot_func_to_name(name,
 			    pciio_info->c_slot,
@@ -1431,16 +1237,14 @@
 
     pciio_info->c_vertex = pconn;
     pciio_info_set(pconn, pciio_info);
-#ifdef BRINGUP
+#ifdef DEBUG_PCIIO
     {
 	int pos;
 	char dname[256];
 	pos = devfs_generate_path(pconn, dname, 256);
-#ifdef DEBUG_PCIIO
 	printk("%s : pconn path= %s \n", __FUNCTION__, &dname[pos]);
-#endif
     }
-#endif /* BRINGUP */
+#endif /* DEBUG_PCIIO */
 
     /*
      * create link to our pci provider
@@ -1520,7 +1324,6 @@
     pciio_info_t            pciio_info;
     pciio_vendor_id_t       vendor_id;
     pciio_device_id_t       device_id;
-    int pciba_attach(devfs_handle_t);
 
 
     pciio_device_inventory_add(pconn);
@@ -1536,11 +1339,6 @@
      */
     ASSERT(pciio_registry != NULL);
 
-    /*
-     * Since pciba is not called from cdl routines .. call it here.
-     */
-    pciba_attach(pconn);
-
     return(cdl_add_connpt(pciio_registry, vendor_id, device_id, pconn, drv_flags));
 }
 
@@ -1625,3 +1423,85 @@
 {
 	return DEV_FUNC(pconn_vhdl, dma_enabled)(pconn_vhdl);
 }
+
+/*
+ * These are complementary Linux interfaces that takes in a pci_dev * as the 
+ * first arguement instead of devfs_handle_t.
+ */
+iopaddr_t               snia_pciio_dmatrans_addr(struct pci_dev *, device_desc_t, paddr_t, size_t, unsigned);
+pciio_dmamap_t          snia_pciio_dmamap_alloc(struct pci_dev *, device_desc_t, size_t, unsigned);
+void                    snia_pciio_dmamap_free(pciio_dmamap_t);
+iopaddr_t               snia_pciio_dmamap_addr(pciio_dmamap_t, paddr_t, size_t);
+void                    snia_pciio_dmamap_done(pciio_dmamap_t);
+pciio_endian_t          snia_pciio_endian_set(struct pci_dev *pci_dev, pciio_endian_t device_end,
+					      pciio_endian_t desired_end);
+
+#include <linux/module.h>
+EXPORT_SYMBOL(snia_pciio_dmatrans_addr);
+EXPORT_SYMBOL(snia_pciio_dmamap_alloc);
+EXPORT_SYMBOL(snia_pciio_dmamap_free);
+EXPORT_SYMBOL(snia_pciio_dmamap_addr);
+EXPORT_SYMBOL(snia_pciio_dmamap_done);
+EXPORT_SYMBOL(snia_pciio_endian_set);
+
+pciio_endian_t
+snia_pciio_endian_set(struct pci_dev *pci_dev,
+	pciio_endian_t device_end,
+	pciio_endian_t desired_end)
+{
+	devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+	
+	return DEV_FUNC(dev, endian_set)
+		(dev, device_end, desired_end);
+}
+
+iopaddr_t
+snia_pciio_dmatrans_addr(struct pci_dev *pci_dev, /* translate for this device */
+                    device_desc_t dev_desc,     /* device descriptor */
+                    paddr_t paddr,      /* system physical address */
+                    size_t byte_count,  /* length */
+                    unsigned flags)
+{                                       /* defined in dma.h */
+
+    devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+
+    return DEV_FUNC(dev, dmatrans_addr)
+        (dev, dev_desc, paddr, byte_count, flags);
+}
+
+pciio_dmamap_t
+snia_pciio_dmamap_alloc(struct pci_dev *pci_dev,  /* set up mappings for this device */
+                   device_desc_t dev_desc,      /* device descriptor */
+                   size_t byte_count_max,       /* max size of a mapping */
+                   unsigned flags)
+{                                       /* defined in dma.h */
+
+    devfs_handle_t dev = PCIDEV_VERTEX(pci_dev);
+
+    return (pciio_dmamap_t) DEV_FUNC(dev, dmamap_alloc)
+        (dev, dev_desc, byte_count_max, flags);
+}
+
+void
+snia_pciio_dmamap_free(pciio_dmamap_t pciio_dmamap)
+{
+    DMAMAP_FUNC(pciio_dmamap, dmamap_free)
+        (CAST_DMAMAP(pciio_dmamap));
+}
+
+iopaddr_t
+snia_pciio_dmamap_addr(pciio_dmamap_t pciio_dmamap,  /* use these mapping resources */
+                  paddr_t paddr,        /* map for this address */
+                  size_t byte_count)
+{                                       /* map this many bytes */
+    return DMAMAP_FUNC(pciio_dmamap, dmamap_addr)
+        (CAST_DMAMAP(pciio_dmamap), paddr, byte_count);
+}
+
+void
+snia_pciio_dmamap_done(pciio_dmamap_t pciio_dmamap)
+{
+    DMAMAP_FUNC(pciio_dmamap, dmamap_done)
+        (CAST_DMAMAP(pciio_dmamap));
+}
+
diff -Nru a/arch/ia64/sn/io/sgi_if.c b/arch/ia64/sn/io/sgi_if.c
--- a/arch/ia64/sn/io/sgi_if.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/sn/io/sgi_if.c	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -22,7 +21,7 @@
 #include <asm/sn/slotnum.h>
 
 void *
-kmem_zalloc(size_t size, int flag)
+snia_kmem_zalloc(size_t size, int flag)
 {
         void *ptr = kmalloc(size, GFP_KERNEL);
         BZERO(ptr, size);
diff -Nru a/arch/ia64/sn/io/sgi_io_init.c b/arch/ia64/sn/io/sgi_io_init.c
--- a/arch/ia64/sn/io/sgi_io_init.c	Fri Mar 15 17:51:00 2002
+++ b/arch/ia64/sn/io/sgi_io_init.c	Fri Mar 15 17:51:00 2002
@@ -4,26 +4,24 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/config.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/sn_private.h>
-#include <asm/sn/synergy.h>
+#include <asm/sn/pci/pciba.h>
 #include <linux/smp.h>
 
 extern void mlreset(int );
 extern int init_hcl(void);
 extern void klgraph_hack_init(void);
-extern void per_hub_init(cnodeid_t);
 extern void hubspc_init(void);
-extern void pciba_init(void);
 extern void pciio_init(void);
 extern void pcibr_init(void);
 extern void xtalk_init(void);
@@ -33,23 +31,21 @@
 extern void usrpci_init(void);
 extern void ioc3_init(void);
 extern void initialize_io(void);
-extern void init_platform_nodepda(nodepda_t *, cnodeid_t );
+#if defined(CONFIG_IA64_SGI_SN1)
 extern void intr_clear_all(nasid_t);
+#endif
 extern void klhwg_add_all_modules(devfs_handle_t);
 extern void klhwg_add_all_nodes(devfs_handle_t);
 
 void sn_mp_setup(void);
 extern devfs_handle_t hwgraph_root;
 extern void io_module_init(void);
-extern cnodeid_t nasid_to_compact_node[];
 extern void pci_bus_cvlink_init(void);
 extern void temp_hack(void);
-extern void init_platform_pda(cpuid_t cpu);
 
 extern int pci_bus_to_hcl_cvlink(void);
-extern synergy_da_t	*Synergy_da_indr[];
 
-#define DEBUG_IO_INIT
+/* #define DEBUG_IO_INIT */
 #ifdef DEBUG_IO_INIT
 #define DBG(x...) printk(x)
 #else
@@ -57,20 +53,73 @@
 #endif /* DEBUG_IO_INIT */
 
 /*
- * kern/ml/csu.s calls mlsetup
- *   mlsetup calls mlreset(master) - kern/os/startup.c
- *   j main
- *
- 
- * SN/slave.s start_slave_loop calls slave_entry
- * SN/slave.s slave_entry calls slave_loop
- * SN/slave.s slave_loop calls bootstrap
- * bootstrap in SN1/SN1asm.s calls cboot
- * cboot calls mlreset(slave) - ml/SN/mp.c
+ * per_hub_init
  *
- * sgi_io_infrastructure_init() gets called right before pci_init() 
- * in Linux mainline.  This routine actually mirrors the IO Infrastructure 
- * call sequence in IRIX, ofcourse, nicely modified for Linux.
+ * 	This code is executed once for each Hub chip.
+ */
+static void
+per_hub_init(cnodeid_t cnode)
+{
+	nasid_t		nasid;
+	nodepda_t	*npdap;
+	ii_icmr_u_t	ii_icmr;
+	ii_ibcr_u_t	ii_ibcr;
+
+	nasid = COMPACT_TO_NASID_NODEID(cnode);
+
+	ASSERT(nasid != INVALID_NASID);
+	ASSERT(NASID_TO_COMPACT_NODEID(nasid) == cnode);
+
+	npdap = NODEPDA(cnode);
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	/* initialize per-node synergy perf instrumentation */
+	npdap->synergy_perf_enabled = 0; /* off by default */
+	npdap->synergy_perf_lock = SPIN_LOCK_UNLOCKED;
+	npdap->synergy_perf_freq = SYNERGY_PERF_FREQ_DEFAULT;
+	npdap->synergy_inactive_intervals = 0;
+	npdap->synergy_active_intervals = 0;
+	npdap->synergy_perf_data = NULL;
+	npdap->synergy_perf_first = NULL;
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
+	/*
+	 * Set the total number of CRBs that can be used.
+	 */
+	ii_icmr.ii_icmr_regval= 0x0;
+	ii_icmr.ii_icmr_fld_s.i_c_cnt = 0xF;
+	REMOTE_HUB_S(nasid, IIO_ICMR, ii_icmr.ii_icmr_regval);
+
+	/*
+	 * Set the number of CRBs that both of the BTEs combined
+	 * can use minus 1.
+	 */
+	ii_ibcr.ii_ibcr_regval= 0x0;
+	ii_ibcr.ii_ibcr_fld_s.i_count = 0x8;
+	REMOTE_HUB_S(nasid, IIO_IBCR, ii_ibcr.ii_ibcr_regval);
+
+	/*
+	 * Set CRB timeout to be 10ms.
+	 */
+	REMOTE_HUB_S(nasid, IIO_ICTP, 0x1000 );
+	REMOTE_HUB_S(nasid, IIO_ICTO, 0xff);
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	/* Reserve all of the hardwired interrupt levels. */
+	intr_reserve_hardwired(cnode);
+#endif
+
+	/* Initialize error interrupts for this hub. */
+	hub_error_init(cnode);
+}
+
+/*
+ * This routine is responsible for the setup of all the IRIX hwgraph style
+ * stuff that's been pulled into linux.  It's called by sn1_pci_find_bios which
+ * is called just before the generic Linux PCI layer does its probing (by 
+ * platform_pci_fixup aka sn1_pci_fixup).
  *
  * It is very IMPORTANT that this call is only made by the Master CPU!
  *
@@ -80,7 +129,6 @@
 sgi_master_io_infr_init(void)
 {
 	int cnode;
-	extern int maxnodes;
 
 	/*
 	 * Do any early init stuff .. einit_tbl[] etc.
@@ -94,11 +142,15 @@
 	DBG("--> sgi_master_io_infr_init: calling pci_bus_cvlink_init().\n");
 	pci_bus_cvlink_init();
 
+#ifdef BRINGUP
+#ifdef CONFIG_IA64_SGI_SN1
 	/*
 	 * Hack to provide statically initialzed klgraph entries.
 	 */
 	DBG("--> sgi_master_io_infr_init: calling klgraph_hack_init()\n");
 	klgraph_hack_init();
+#endif /* CONFIG_IA64_SGI_SN1 */
+#endif /* BRINGUP */
 
 	/*
 	 * This is the Master CPU.  Emulate mlsetup and main.c in Irix.
@@ -117,7 +169,7 @@
 	sn_mp_setup();
 
 	DBG("--> sgi_master_io_infr_init: calling per_hub_init(0).\n");
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 		per_hub_init(cnode);
 	}
 
@@ -133,9 +185,6 @@
 	DBG("--> sgi_master_io_infr_init: calling hubspc_init()\n");
 	hubspc_init();
 
-	DBG("--> sgi_master_io_infr_init: calling pciba_init()\n");
-	pciba_init();
-
 	DBG("--> sgi_master_io_infr_init: calling pciio_init()\n");
 	pciio_init();
 
@@ -172,6 +221,11 @@
 	DBG("--> sgi_master_io_infr_init: Setting up SGI IO Links for Linux PCI\n");
 	pci_bus_to_hcl_cvlink();
 
+#ifdef CONFIG_PCIBA
+	DBG("--> sgi_master_io_infr_init: calling pciba_init()\n");
+	pciba_init();
+#endif
+
 	DBG("--> Leave sgi_master_io_infr_init: DONE setting up SGI Links for PCI\n");
 }
 
@@ -199,76 +253,15 @@
 sn_mp_setup(void)
 {
 	cnodeid_t	cnode;
-	extern int	maxnodes;
 	cpuid_t		cpu;
 
-	DBG("sn_mp_setup: Entered.\n");
-	/*
-	 * NODEPDA(x) Macro depends on nodepda
-	 * subnodepda is also statically set to calias space which we 
-	 * do not currently support yet .. just a hack for now.
-	 */
-#ifdef NUMA_BASE
-        maxnodes = numnodes;
-	DBG("sn_mp_setup(): maxnodes= %d  numnodes= %d\n", maxnodes,numnodes);
-        printk("sn_mp_setup(): Allocating backing store for *Nodepdaindr[%2d] \n",
-                maxnodes);
-
-        /*
-         * Initialize Nodpdaindr and per-node nodepdaindr array
-         */
-        *Nodepdaindr = (nodepda_t *) kmalloc(sizeof(nodepda_t *)*numnodes, GFP_KERNEL);
-        for (cnode=0; cnode<maxnodes; cnode++) {
-            Nodepdaindr[cnode] = (nodepda_t *) kmalloc(sizeof(struct nodepda_s),
-                                                                GFP_KERNEL);
-	    Synergy_da_indr[cnode * 2] = (synergy_da_t *) kmalloc(
-		sizeof(synergy_da_t), GFP_KERNEL);
-	    Synergy_da_indr[(cnode * 2) + 1] = (synergy_da_t *) kmalloc(
-		sizeof(synergy_da_t), GFP_KERNEL);
-            Nodepdaindr[cnode]->pernode_pdaindr = Nodepdaindr;
-            subnodepda = &Nodepdaindr[cnode]->snpda[cnode];
-        }
-        nodepda = Nodepdaindr[0];
-#else
-        Nodepdaindr = (nodepda_t *) kmalloc(sizeof(struct nodepda_s), GFP_KERNEL);
-        nodepda = Nodepdaindr[0];
-        subnodepda = &Nodepdaindr[0]->snpda[0];
-
-#endif /* NUMA_BASE */
-
-	/*
-	 * Before we let the other processors run, set up the platform specific
-	 * stuff in the nodepda.
-	 *
-	 * ???? maxnodes set in mlreset .. who sets it now ????
-	 * ???? cpu_node_probe() called in mlreset to set up the following:
-	 *      compact_to_nasid_node[] - cnode id gives nasid
-	 *      nasid_to_compact_node[] - nasid gives cnode id
-	 *
-	 *	do_cpumask() sets the following:
-	 *      cpuid_to_compact_node[] - cpuid gives cnode id
-	 *
-	 *      nasid comes from gdap->g_nasidtable[]
-	 *      ml/SN/promif.c
-	 */
-
-#ifdef CONFIG_IA64_SGI_SN1
 	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
 		/* Skip holes in CPU space */
 		if (cpu_enabled(cpu)) {
 			init_platform_pda(cpu);
 		}
 	}
-#endif
-	for (cnode = 0; cnode < maxnodes; cnode++) {
-		/*
-		 * Set up platform-dependent nodepda fields.
-		 * The following routine actually sets up the hubinfo struct
-		 * in nodepda.
-		 */
-		DBG("sn_mp_io_setup: calling init_platform_nodepda(%2d)\n",cnode);
-		init_platform_nodepda(Nodepdaindr[cnode], cnode);
-	}
+
 	/*
 	 * Initialize platform-dependent vertices in the hwgraph:
 	 *	module
@@ -290,24 +283,26 @@
 	klhwg_add_all_nodes(hwgraph_root);
 
 
-	for (cnode = 0; cnode < maxnodes; cnode++) {
+	for (cnode = 0; cnode < numnodes; cnode++) {
 
 		/*
 		 * This routine clears the Hub's Interrupt registers.
 		 */
-#ifdef CONFIG_IA64_SGI_SN1
 		/*
 		 * We need to move this intr_clear_all() routine 
 		 * from SN/intr.c to a more appropriate file.
 		 * Talk to Al Mayer.
 		 */
+#if defined(CONFIG_IA64_SGI_SN1)
                 intr_clear_all(COMPACT_TO_NASID_NODEID(cnode));
+#endif
 		/* now init the hub */
 	//	per_hub_init(cnode);
-#endif
+
 	}
 
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
+#if defined(CONFIG_IA64_SGI_SN1)
 	synergy_perf_init();
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
+#endif
+
 }
diff -Nru a/arch/ia64/sn/io/sgi_io_sim.c b/arch/ia64/sn/io/sgi_io_sim.c
--- a/arch/ia64/sn/io/sgi_io_sim.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/sgi_io_sim.c	Fri Mar 15 17:51:02 2002
@@ -4,31 +4,28 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/agent.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/module.h>
 #include <asm/sn/nic.h>
 #include <asm/sn/sn_private.h>
-#include <asm/sn/synergy.h>
 
 cpuid_t         master_procid = 0;
-int maxnodes;
 char arg_maxnodes[4];
 
-nodepda_t       *Nodepdaindr[MAX_COMPACT_NODES];
-nodepda_t        *nodepda;
-subnode_pda_t    *subnodepda;
-
-synergy_da_t	*Synergy_da_indr[MAX_COMPACT_NODES * 2];
-
 extern void init_all_devices(void);
 
+#if defined(CONFIG_IA64_SGI_SN1)
+synergy_da_t	*Synergy_da_indr[MAX_COMPACT_NODES * 2];
+#endif
 
 /*
  * Return non-zero if the given variable was specified
@@ -73,27 +70,23 @@
  * Routines provided by ml/SN/promif.c.
  */
 static __psunsigned_t master_bridge_base = (__psunsigned_t)NULL;
-nasid_t console_nasid;
+nasid_t console_nasid = (nasid_t)-1;
 static char console_wid;
 static char console_pcislot;
 
 void
 set_master_bridge_base(void)
 {
-
-        console_nasid = KL_CONFIG_CH_CONS_INFO(master_nasid)->nasid;
         console_wid = WIDGETID_GET(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base);
         console_pcislot = KL_CONFIG_CH_CONS_INFO(master_nasid)->npci;
-        master_bridge_base = (__psunsigned_t)NODE_SWIN_BASE(console_nasid,
-                                                            console_wid);
-	FIXME("WARNING: set_master_bridge_base: NON NASID 0 DOES NOT WORK\n");
+        master_bridge_base = (__psunsigned_t)NODE_SWIN_BASE(console_nasid, console_wid);
+	// FIXME("WARNING: set_master_bridge_base: NON NASID 0 DOES NOT WORK\n");
 }
 
 int
 check_nasid_equiv(nasid_t nasida, nasid_t nasidb)
 {
-        if ((nasida == nasidb) ||
-            (nasida == NODEPDA(NASID_TO_COMPACT_NODEID(nasidb))->xbow_peer))
+        if ((nasida == nasidb) || (nasida == NODEPDA(NASID_TO_COMPACT_NODEID(nasidb))->xbow_peer))
                 return 1;
         else
                 return 0;
diff -Nru a/arch/ia64/sn/io/sn1/hub_intr.c b/arch/ia64/sn/io/sn1/hub_intr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/hub_intr.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,307 @@
+/* $Id: io.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern xtalk_provider_t hub_provider;
+
+/* ARGSUSED */
+void
+hub_intr_init(devfs_handle_t hubv)
+{
+}
+
+/*
+ * hub_device_desc_update
+ *	Update the passed in device descriptor with the actual the
+ * 	target cpu number and interrupt priority level.
+ *	NOTE : These might be the same as the ones passed in thru
+ *	the descriptor.
+ */
+static void
+hub_device_desc_update(device_desc_t 	dev_desc, 
+		       ilvl_t 		intr_swlevel,
+		       cpuid_t		cpu)
+{
+}
+
+int allocate_my_bit = INTRCONNECT_ANYBIT;
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+static hub_intr_t
+do_hub_intr_alloc(devfs_handle_t dev,		/* which crosstalk device */
+		  device_desc_t dev_desc,	/* device descriptor */
+		  devfs_handle_t owner_dev,	/* owner of this interrupt, if known */
+		  int uncond_nothread)		/* unconditionally non-threaded */
+{
+	cpuid_t cpu = (cpuid_t)0;			/* cpu to receive interrupt */
+        int cpupicked = 0;
+	int bit;			/* interrupt vector */
+	/*REFERENCED*/
+	int intr_resflags = 0;
+	hub_intr_t intr_hdl;
+	cnodeid_t nodeid;		/* node to receive interrupt */
+	/*REFERENCED*/
+	nasid_t nasid;			/* nasid to receive interrupt */
+	struct xtalk_intr_s *xtalk_info;
+	iopaddr_t xtalk_addr;		/* xtalk addr on hub to set intr */
+	xwidget_info_t xwidget_info;	/* standard crosstalk widget info handle */
+	char *intr_name = NULL;
+	ilvl_t intr_swlevel = (ilvl_t)0;
+	extern int default_intr_pri;
+	extern void synergy_intr_alloc(int, int);
+
+
+	if (dev_desc) {
+		if (dev_desc->flags & D_INTR_ISERR) {
+			intr_resflags = II_ERRORINT;
+		} else if (!uncond_nothread && !(dev_desc->flags & D_INTR_NOTHREAD)) {
+			intr_resflags = II_THREADED;
+		} else {
+			/* Neither an error nor a thread. */
+			intr_resflags = 0;
+		}
+	} else {
+		intr_swlevel = default_intr_pri;
+		if (!uncond_nothread)
+			intr_resflags = II_THREADED;
+	}
+
+	/* XXX - Need to determine if the interrupt should be threaded. */
+
+	/* If the cpu has not been picked already then choose a candidate 
+	 * interrupt target and reserve the interrupt bit 
+	 */
+	if (!cpupicked) {
+		cpu = intr_heuristic(dev,dev_desc,allocate_my_bit,
+				     intr_resflags,owner_dev,
+				     intr_name,&bit);
+	}
+
+	/* At this point we SHOULD have a valid cpu */
+	if (cpu == CPU_NONE) {
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+		printk(KERN_WARNING  "%v hub_intr_alloc could not allocate interrupt\n",
+			owner_dev);
+#else
+		printk(KERN_WARNING  "%p hub_intr_alloc could not allocate interrupt\n",
+			(void *)owner_dev);
+#endif
+		return(0);
+
+	}
+
+	/* If the cpu has been picked already (due to the bridge data 
+	 * corruption bug) then try to reserve an interrupt bit .
+	 */
+	if (cpupicked) {
+		bit = intr_reserve_level(cpu, allocate_my_bit, 
+					 intr_resflags, 
+					 owner_dev, intr_name);
+		if (bit < 0) {
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+			printk(KERN_WARNING  "Could not reserve an interrupt bit for cpu "
+				" %d and dev %v\n",
+				cpu,owner_dev);
+#else
+			printk(KERN_WARNING  "Could not reserve an interrupt bit for cpu "
+				" %d and dev %p\n",
+				(int)cpu, (void *)owner_dev);
+#endif
+				
+			return(0);
+		}
+	}
+
+	nodeid = cpuid_to_cnodeid(cpu);
+	nasid = cpuid_to_nasid(cpu);
+	xtalk_addr = HUBREG_AS_XTALKADDR(nasid, PIREG(PI_INT_PEND_MOD, cpuid_to_subnode(cpu)));
+
+	/*
+	 * Allocate an interrupt handle, and fill it in.  There are two
+	 * pieces to an interrupt handle: the piece needed by generic
+	 * xtalk code which is used by crosstalk device drivers, and
+	 * the piece needed by low-level IP27 hardware code.
+	 */
+	intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, nodeid);
+	ASSERT_ALWAYS(intr_hdl);
+
+	/* 
+	 * Fill in xtalk information for generic xtalk interfaces that
+	 * operate on xtalk_intr_hdl's.
+	 */
+	xtalk_info = &intr_hdl->i_xtalk_info;
+	xtalk_info->xi_dev = dev;
+	xtalk_info->xi_vector = bit;
+	xtalk_info->xi_addr = xtalk_addr;
+
+	/*
+	 * Regardless of which CPU we ultimately interrupt, a given crosstalk
+	 * widget always handles interrupts (and PIO and DMA) through its 
+	 * designated "master" crosstalk provider.
+	 */
+	xwidget_info = xwidget_info_get(dev);
+	if (xwidget_info)
+		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
+
+	/* Fill in low level hub information for hub_* interrupt interface */
+	intr_hdl->i_swlevel = intr_swlevel;
+	intr_hdl->i_cpuid = cpu;
+	intr_hdl->i_bit = bit;
+	intr_hdl->i_flags = HUB_INTR_IS_ALLOCED;
+
+	/* Store the actual interrupt priority level & interrupt target
+	 * cpu back in the device descriptor.
+	 */
+	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
+	synergy_intr_alloc((int)bit, (int)cpu);
+	return(intr_hdl);
+}
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+hub_intr_t
+hub_intr_alloc(	devfs_handle_t dev,		/* which crosstalk device */
+		device_desc_t dev_desc,		/* device descriptor */
+		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
+}
+
+/*
+ * Allocate resources required for an interrupt as specified in dev_desc.
+ * Uncondtionally request non-threaded, regardless of what the device
+ * descriptor might say.
+ * Returns a hub interrupt handle on success, or 0 on failure.
+ */
+hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,		/* which crosstalk device */
+		device_desc_t dev_desc,		/* device descriptor */
+		devfs_handle_t owner_dev)		/* owner of this interrupt, if known */
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
+}
+
+/*
+ * Free resources consumed by intr_alloc.
+ */
+void
+hub_intr_free(hub_intr_t intr_hdl)
+{
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_t xtalk_info;
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
+		/* Setting the following fields in the xtalk interrupt info
+	 	 * clears the interrupt target register in the xtalk user
+	 	 */
+		xtalk_info = &intr_hdl->i_xtalk_info;
+		xtalk_info->xi_dev = NODEV;
+		xtalk_info->xi_vector = 0;
+		xtalk_info->xi_addr = 0;
+		hub_intr_disconnect(intr_hdl);
+	}
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED)
+		kfree(intr_hdl);
+
+	intr_unreserve_level(cpu, bit);
+}
+
+
+/*
+ * Associate resources allocated with a previous hub_intr_alloc call with the
+ * described handler, arg, name, etc.
+ */
+/*ARGSUSED*/
+int
+hub_intr_connect(	hub_intr_t intr_hdl,		/* xtalk intr resource handle */
+			xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
+			void *setfunc_arg)		/* arg to setfunc */
+{
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	extern int synergy_intr_connect(int, int);
+
+	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
+
+	rv = intr_connect_level(cpu, bit, intr_hdl->i_swlevel, NULL);
+	if (rv < 0)
+		return(rv);
+
+	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
+	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
+
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
+	return(synergy_intr_connect((int)bit, (int)cpu));
+}
+
+
+/*
+ * Disassociate handler with the specified interrupt.
+ */
+void
+hub_intr_disconnect(hub_intr_t intr_hdl)
+{
+	/*REFERENCED*/
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_setfunc_t setfunc;
+
+	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
+
+	/* TBD: send disconnected interrupts somewhere harmless */
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	rv = intr_disconnect_level(cpu, bit);
+	ASSERT(rv == 0);
+	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
+}
+
+
+/*
+ * Return a hwgraph vertex that represents the CPU currently
+ * targeted by an interrupt.
+ */
+devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl)
+{
+	cpuid_t cpuid = intr_hdl->i_cpuid;
+	ASSERT(cpuid != CPU_NONE);
+
+	return(cpuid_to_vertex(cpuid));
+}
diff -Nru a/arch/ia64/sn/io/sn1/hubcounters.c b/arch/ia64/sn/io/sn1/hubcounters.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/hubcounters.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,283 @@
+/* $Id:$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000 - 2001 Silicon Graphics, Inc.
+ * All rights reserved.
+ */
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <asm/types.h>
+#include <asm/sn/io.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/router.h>
+#include <asm/sn/snconfig.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/clksupport.h>
+#include <asm/sn/sndrv.h>
+
+extern void hubni_error_handler(char *, int); /* huberror.c */
+
+static int hubstats_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+struct file_operations hub_mon_fops = {
+        ioctl:          hubstats_ioctl,
+};
+
+#define HUB_CAPTURE_TICKS	(2 * HZ)
+
+#define HUB_ERR_THRESH		500
+#define USEC_PER_SEC		1000000
+#define NSEC_PER_SEC		USEC_PER_SEC*1000
+
+volatile int hub_print_usecs = 600 * USEC_PER_SEC;
+
+/* Return success if the hub's crosstalk link is working */
+int
+hub_xtalk_link_up(nasid_t nasid)
+{
+	hubreg_t	llp_csr_reg;
+
+	/* Read the IO LLP control status register */
+	llp_csr_reg = REMOTE_HUB_L(nasid, IIO_LLP_CSR);
+
+	/* Check if the xtalk link is working */
+	if (llp_csr_reg & IIO_LLP_CSR_IS_UP) 
+		return(1);
+
+	return(0);
+
+	
+}
+
+static char *error_flag_to_type(unsigned char error_flag)
+{
+    switch(error_flag) {
+    case 0x1: return ("NI retries");
+    case 0x2: return ("NI SN errors");
+    case 0x4: return ("NI CB errors");
+    case 0x8: return ("II CB errors");
+    case 0x10: return ("II SN errors");
+    default: return ("Errors");
+    }
+}
+
+int
+print_hub_error(hubstat_t *hsp, hubreg_t reg,
+		int64_t delta, unsigned char error_flag)
+{
+	int64_t rate;
+
+	reg *= hsp->hs_per_minute;	/* Convert to minutes */
+	rate = reg / delta;
+
+	if (rate > HUB_ERR_THRESH) {
+		
+		if(hsp->hs_maint & error_flag) 
+		{
+		printk( "Excessive %s (%ld/min) on %s",
+			error_flag_to_type(error_flag), rate, hsp->hs_name); 
+		}
+		else 
+		{
+		   hsp->hs_maint |= error_flag;
+		printk( "Excessive %s (%ld/min) on %s",
+			error_flag_to_type(error_flag), rate, hsp->hs_name); 
+		}
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+
+int
+check_hub_error_rates(hubstat_t *hsp)
+{
+	int64_t delta = hsp->hs_timestamp - hsp->hs_timebase;
+	int printed = 0;
+
+	printed += print_hub_error(hsp, hsp->hs_ni_retry_errors,
+				   delta, 0x1);
+
+#if 0
+	printed += print_hub_error(hsp, hsp->hs_ni_sn_errors,
+				   delta, 0x2);
+#endif
+
+	printed += print_hub_error(hsp, hsp->hs_ni_cb_errors,
+				   delta, 0x4);
+
+
+	/* If the hub's xtalk link is not working there is 
+	 * no need to print the "Excessive..." warning 
+	 * messages
+	 */
+	if (!hub_xtalk_link_up(hsp->hs_nasid))
+		return(printed);
+
+
+	printed += print_hub_error(hsp, hsp->hs_ii_cb_errors,
+				   delta, 0x8);
+
+	printed += print_hub_error(hsp, hsp->hs_ii_sn_errors,
+				   delta, 0x10);
+
+	return printed;
+}
+
+
+void
+capture_hub_stats(cnodeid_t cnodeid, struct nodepda_s *npda)
+{
+	nasid_t nasid;
+	hubstat_t *hsp = &(npda->hubstats);
+	hubreg_t port_error;
+	ii_illr_u_t illr;
+	int count;
+	int overflow = 0;
+
+	/*
+	 * If our link wasn't up at boot time, don't worry about error rates.
+	 */
+	if (!(hsp->hs_ni_port_status & NPS_LINKUP_MASK)) {
+		printk("capture_hub_stats: cnode=%d hs_ni_port_status=0x%016lx : link is not up\n",
+		cnodeid, hsp->hs_ni_port_status);
+		return;
+	}
+
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+
+	hsp->hs_timestamp = GET_RTC_COUNTER();
+
+	port_error = REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+	count = ((port_error & NPE_RETRYCOUNT_MASK) >> NPE_RETRYCOUNT_SHFT);
+	hsp->hs_ni_retry_errors += count;
+	if (count == NPE_COUNT_MAX)
+		overflow = 1;
+	count = ((port_error & NPE_SNERRCOUNT_MASK) >> NPE_SNERRCOUNT_SHFT);
+	hsp->hs_ni_sn_errors += count;
+	if (count == NPE_COUNT_MAX)
+		overflow = 1;
+	count = ((port_error & NPE_CBERRCOUNT_MASK) >> NPE_CBERRCOUNT_SHFT);
+	hsp->hs_ni_cb_errors += count;
+	if (overflow || count == NPE_COUNT_MAX)
+		hsp->hs_ni_overflows++;
+
+	if (port_error & NPE_FATAL_ERRORS) {
+#ifdef ajm
+		hubni_error_handler("capture_hub_stats", 1);
+#else
+		printk("Error: hubni_error_handler in capture_hub_stats");
+#endif
+	}
+
+	illr.ii_illr_regval = REMOTE_HUB_L(nasid, IIO_LLP_LOG);
+	REMOTE_HUB_S(nasid, IIO_LLP_LOG, 0);
+
+	hsp->hs_ii_sn_errors += illr.ii_illr_fld_s.i_sn_cnt;
+	hsp->hs_ii_cb_errors += illr.ii_illr_fld_s.i_cb_cnt;
+	if ((illr.ii_illr_fld_s.i_sn_cnt == IIO_LLP_SN_MAX) ||
+	    (illr.ii_illr_fld_s.i_cb_cnt == IIO_LLP_CB_MAX))
+		hsp->hs_ii_overflows++;
+
+	if (hsp->hs_print) {
+		if (check_hub_error_rates(hsp)) {
+			hsp->hs_last_print = GET_RTC_COUNTER();
+			hsp->hs_print = 0;
+		}
+	} else {
+		if ((GET_RTC_COUNTER() -
+		    hsp->hs_last_print) > hub_print_usecs)
+			hsp->hs_print = 1;
+	}
+		
+	npda->hubticks = HUB_CAPTURE_TICKS;
+}
+
+
+void
+init_hub_stats(cnodeid_t cnodeid, struct nodepda_s *npda)
+{
+	hubstat_t *hsp = &(npda->hubstats);
+	nasid_t nasid = cnodeid_to_nasid(cnodeid);
+	bzero(&(npda->hubstats), sizeof(hubstat_t));
+
+	hsp->hs_version = HUBSTAT_VERSION;
+	hsp->hs_cnode = cnodeid;
+	hsp->hs_nasid = nasid;
+	hsp->hs_timebase = GET_RTC_COUNTER();
+	hsp->hs_ni_port_status = REMOTE_HUB_L(nasid, NI_PORT_STATUS);
+
+	/* Clear the II error counts. */
+	REMOTE_HUB_S(nasid, IIO_LLP_LOG, 0);
+
+	/* Clear the NI counts. */
+	REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+
+	hsp->hs_per_minute = (long long)RTC_CYCLES_PER_SEC * 60LL;
+
+	npda->hubticks = HUB_CAPTURE_TICKS;
+
+	/* XX should use kmem_alloc_node */
+	hsp->hs_name = (char *)kmalloc(MAX_HUB_PATH, GFP_KERNEL);
+	ASSERT_ALWAYS(hsp->hs_name);
+
+	sprintf(hsp->hs_name, "/dev/hw/" EDGE_LBL_MODULE "/%03d/"
+	        EDGE_LBL_NODE "/" EDGE_LBL_HUB,
+		npda->module_id);
+
+	hsp->hs_last_print = 0;
+	hsp->hs_print = 1;
+
+	hub_print_usecs = hub_print_usecs;
+
+#if 0
+	printk("init_hub_stats: cnode=%d nasid=%d hs_version=%d hs_ni_port_status=0x%016lx\n",
+		cnodeid, nasid, hsp->hs_version, hsp->hs_ni_port_status);
+#endif
+}
+
+static int
+hubstats_ioctl(struct inode *inode, struct file *file,
+        unsigned int cmd, unsigned long arg)
+{
+        cnodeid_t       cnode;
+        nodepda_t       *npdap;
+        uint64_t        longarg;
+        devfs_handle_t  d;
+
+        if ((d = devfs_get_handle_from_inode(inode)) == NULL)
+                return -ENODEV;
+        cnode = (cnodeid_t)hwgraph_fastinfo_get(d);
+        npdap = NODEPDA(cnode);
+
+	if (npdap->hubstats.hs_version != HUBSTAT_VERSION) {
+		init_hub_stats(cnode, npdap);
+	}
+
+        switch (cmd) {
+	case SNDRV_GET_INFOSIZE:
+		longarg = sizeof(hubstat_t);
+		if (copy_to_user((void *)arg, &longarg, sizeof(longarg))) {
+		    return -EFAULT;
+		}
+		break;
+
+	case SNDRV_GET_HUBINFO:
+		/* refresh npda->hubstats */
+		capture_hub_stats(cnode, npdap);
+		if (copy_to_user((void *)arg, &npdap->hubstats, sizeof(hubstat_t))) {
+		    return -EFAULT;
+		}
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff -Nru a/arch/ia64/sn/io/sn1/huberror.c b/arch/ia64/sn/io/sn1/huberror.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/huberror.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,228 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+
+extern void hubni_eint_init(cnodeid_t cnode);
+extern void hubii_eint_init(cnodeid_t cnode);
+extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
+extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
+
+extern int maxcpus;
+
+#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
+
+
+void
+hub_error_clear(nasid_t nasid)
+{
+	int i;
+	hubreg_t idsr;
+	int sn;
+
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_INT_PEND, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_A_CLR, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_ERR_STATUS0_B_CLR, -1);
+		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_0, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_SPURIOUS_HDR_1, 0);
+	}
+
+	REMOTE_HUB_L(nasid, MD_DIR_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_MEM_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_MISC1_ERROR_CLR);
+	REMOTE_HUB_L(nasid, MD_PROTOCOL_ERR_CLR);
+
+    /*
+     * Make sure spurious write response errors are cleared
+     * (values are from hub_set_prb())
+     */
+    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
+        iprb_t prb;
+
+	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
+
+        /* Clear out some fields */
+        prb.iprb_ovflow = 1;
+        prb.iprb_bnakctr = 0;
+        prb.iprb_anakctr = 0;
+
+	/*
+	 * PIO reads in fire-and-forget mode on bedrock 1.0 don't
+	 * frob the credit count properly, making the responses appear
+	 * spurious.  So don't use fire-and-forget mode.  Bug 761802.
+	 */
+        prb.iprb_ff = 0;        /* disable fire-and-forget mode by default */
+
+        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
+
+        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
+    }
+
+    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
+    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
+    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
+
+    REMOTE_HUB_L(nasid, NI_PORT_ERROR_CLEAR);
+    /* No need to clear NI_PORT_HEADER regs; they are continually overwritten*/
+
+    REMOTE_HUB_S(nasid, LB_ERROR_MASK_CLR, -1);
+    REMOTE_HUB_S(nasid, LB_ERROR_HDR1, 0);
+
+    /* Clear XB error regs, in order */
+    for (i = 0;
+         i <= XB_FIRST_ERROR_CLEAR - XB_POQ0_ERROR_CLEAR;
+         i += sizeof(hubreg_t)) {
+        REMOTE_HUB_S(nasid, XB_POQ0_ERROR_CLEAR + i, 0);
+    }
+}
+
+
+/*
+ * Function	: hub_error_init
+ * Purpose	: initialize the error handling requirements for a given hub.
+ * Parameters	: cnode, the compact nodeid.
+ * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
+ *			remote cpu, when this hub is headless.(cpuless)
+ * Returns	: None
+ */
+
+void
+hub_error_init(cnodeid_t cnode)
+{
+	nasid_t nasid;
+
+    nasid = cnodeid_to_nasid(cnode);
+    hub_error_clear(nasid);
+
+    /*
+     * Now setup the hub ii and ni error interrupt handler.
+     */
+
+    hubii_eint_init(cnode);
+    hubni_eint_init(cnode);
+
+    return;
+}
+
+/*
+ * Function	: hubii_eint_init
+ * Parameters	: cnode
+ * Purpose	: to initialize the hub iio error interrupt.
+ * Assumptions	: Called once per hub, by the cpu which will ultimately
+ *			handle this interrupt.
+ * Returns	: None.
+ */
+
+
+void
+hubii_eint_init(cnodeid_t cnode)
+{
+    int			bit, rv;
+    ii_iidsr_u_t    	hubio_eint;
+    hubinfo_t		hinfo; 
+    cpuid_t		intr_cpu;
+    devfs_handle_t 	hub_v;
+    ii_ilcsr_u_t	ilcsr;
+    int bit_pos_to_irq(int bit);
+    int synergy_intr_connect(int bit, int cpuid);
+
+
+    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
+    ASSERT_ALWAYS(hub_v);
+    hubinfo_get(hub_v, &hinfo);
+
+    ASSERT(hinfo);
+    ASSERT(hinfo->h_cnodeid == cnode);
+
+    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
+
+    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
+	/* 
+	 * HUB II link is not up. 
+	 * Just disable LLP, and don't connect any interrupts.
+	 */
+	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
+	return;
+    }
+    /* Select a possible interrupt target where there is a free interrupt
+     * bit and also reserve the interrupt bit for this IO error interrupt
+     */
+    intr_cpu = intr_heuristic(hub_v,0,INTRCONNECT_ANYBIT,II_ERRORINT,hub_v,
+			      "HUB IO error interrupt",&bit);
+    if (intr_cpu == CPU_NONE) {
+	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
+	return;
+    }
+	
+    rv = intr_connect_level(intr_cpu, bit, 0, NULL);
+    synergy_intr_connect(bit, intr_cpu);
+    request_irq(bit_pos_to_irq(bit) + (intr_cpu << 8), hubii_eint_handler, 0, "SN hub error", (void *)hub_v);
+    ASSERT_ALWAYS(rv >= 0);
+    hubio_eint.ii_iidsr_regval = 0;
+    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
+    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
+    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
+    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
+
+}
+
+void
+hubni_eint_init(cnodeid_t cnode)
+{
+    int intr_bit;
+    cpuid_t targ;
+
+
+    if ((targ = cnodeid_to_cpuid(cnode)) == CPU_NONE)
+	return;
+
+	/* The prom chooses which cpu gets these interrupts, but we
+	*  don't know which one it chose.  We will register all of the 
+	*  cpus to be sure.  This only costs us an irqaction per cpu.
+	*/
+    for (; targ < CPUS_PER_NODE; targ++) {
+	if (!cpu_enabled(targ) ) continue;
+	/* connect the INTEND1 bits. */
+	for (intr_bit = XB_ERROR; intr_bit <= MSC_PANIC_INTR; intr_bit++) {
+		intr_connect_level(targ, intr_bit, II_ERRORINT, NULL);
+	}
+	request_irq(SGI_HUB_ERROR_IRQ + (targ << 8), snia_error_intr_handler, 0, "SN hub error", NULL);
+	/* synergy masks are initialized in the prom to enable all interrupts. */
+	/* We'll just leave them that way, here, for these interrupts. */
+    }
+}
+
+
+/*ARGSUSED*/
+void
+hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
+{
+
+	panic("Hubii interrupt\n");
+}
diff -Nru a/arch/ia64/sn/io/sn1/ip37.c b/arch/ia64/sn/io/sn1/ip37.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/ip37.c	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,47 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * ip37.c
+ *	Support for IP35/IP37 machines
+ */
+
+#include <linux/types.h>
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/pci/bridge.h>     /* for bridge_t */
+
+
+xwidgetnum_t
+hub_widget_id(nasid_t nasid)
+{
+	hubii_wcr_t	ii_wcr;	/* the control status register */
+		
+	ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
+
+	return ii_wcr.wcr_fields_s.wcr_widget_id;
+}
+
+int
+is_fine_dirmode(void)
+{
+	return (((LOCAL_HUB_L(LB_REV_ID) & LRI_SYSTEM_SIZE_MASK)
+		>> LRI_SYSTEM_SIZE_SHFT) == SYSTEM_SIZE_SMALL);
+
+}
+
+
+void
+ni_reset_port(void)
+{
+	LOCAL_HUB_S(NI_RESET_ENABLE, NRE_RESETOK);
+	LOCAL_HUB_S(NI_PORT_RESET, NPR_PORTRESET | NPR_LOCALRESET);
+}
diff -Nru a/arch/ia64/sn/io/sn1/mem_refcnt.c b/arch/ia64/sn/io/sn1/mem_refcnt.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/mem_refcnt.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,221 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/sn1/mem_refcnt.h>
+#include <asm/sn/sn1/hwcntrs.h>
+#include <asm/sn/sn1/hubspc.h>
+// From numa_hw.h
+
+#define MIGR_COUNTER_MAX_GET(nodeid) \
+        (NODEPDA_MCD((nodeid))->migr_system_kparms.migr_threshold_reference)
+/*
+ * Get the Absolute Theshold
+ */
+#define MIGR_THRESHOLD_ABS_GET(nodeid) ( \
+        MD_MIG_VALUE_THRESH_GET(COMPACT_TO_NASID_NODEID(nodeid)))
+/*
+ * Get the current Differential Threshold
+ */
+#define MIGR_THRESHOLD_DIFF_GET(nodeid) \
+        (NODEPDA_MCD(nodeid)->migr_as_kparms.migr_base_threshold)
+
+#define NUM_OF_HW_PAGES_PER_SW_PAGE()   (NBPP / MD_PAGE_SIZE)
+
+// #include "migr_control.h"
+
+int
+mem_refcnt_attach(devfs_handle_t hub)
+{
+#ifndef CONFIG_IA64_SGI_SN
+        devfs_handle_t refcnt_dev;
+        
+        hwgraph_char_device_add(hub,
+                                "refcnt",
+                                "hubspc_", 
+				&refcnt_dev);
+        device_info_set(refcnt_dev, (void*)(ulong)HUBSPC_REFCOUNTERS);
+#endif
+
+        return (0);
+}
+
+
+/*ARGSUSED*/
+int
+mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp)
+{
+        cnodeid_t node;
+
+        node = master_node_get(*devp);
+
+        ASSERT( (node >= 0) && (node < numnodes) );
+
+        if (NODEPDA(node)->migr_refcnt_counterbuffer == NULL) {
+                return (ENODEV);
+        }
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != (size_t)0 );
+
+        return (0);
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+        return 0;
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+        cnodeid_t node;
+        int errcode;
+        char* buffer;
+        size_t blen;
+        
+        node = master_node_get(dev);
+
+        ASSERT( (node >= 0) && (node < numnodes) );
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
+
+        /*
+         * XXXX deal with prot's somewhere around here....
+         */
+
+        buffer = NODEPDA(node)->migr_refcnt_counterbuffer;
+        blen = NODEPDA(node)->migr_refcnt_cbsize;
+
+        /*
+         * Force offset to be a multiple of sizeof(refcnt_t)
+         * We round up.
+         */
+
+        off = (((off - 1)/sizeof(refcnt_t)) + 1) * sizeof(refcnt_t);
+
+        if ( ((buffer + blen) - (buffer + off + len)) < 0 ) {
+                return (EPERM);
+        }
+
+        errcode = v_mapphys(vt,
+                            buffer + off,
+                            len);
+
+        return errcode;
+}
+
+/*ARGSUSED*/
+int
+mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+        return 0;
+}
+
+/* ARGSUSED */
+int
+mem_refcnt_ioctl(devfs_handle_t dev,
+                 int cmd,
+                 void *arg,
+                 int mode,
+                 cred_t *cred_p,
+                 int *rvalp)
+{
+        cnodeid_t node;
+        int errcode;
+	extern int numnodes;
+        
+        node = master_node_get(dev);
+
+        ASSERT( (node >= 0) && (node < numnodes) );
+
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbuffer != NULL);
+        ASSERT( NODEPDA(node)->migr_refcnt_counterbase != NULL );
+        ASSERT( NODEPDA(node)->migr_refcnt_cbsize != 0 );
+
+        errcode = 0;
+        
+        switch (cmd) {
+        case RCB_INFO_GET:
+        {
+                rcb_info_t rcb;
+                
+                rcb.rcb_len = NODEPDA(node)->migr_refcnt_cbsize;
+                
+                rcb.rcb_sw_sets = NODEPDA(node)->migr_refcnt_numsets;
+                rcb.rcb_sw_counters_per_set = numnodes;
+                rcb.rcb_sw_counter_size = sizeof(refcnt_t);
+
+                rcb.rcb_base_pages = NODEPDA(node)->migr_refcnt_numsets /
+                                     NUM_OF_HW_PAGES_PER_SW_PAGE();  
+                rcb.rcb_base_page_size = NBPP;
+                rcb.rcb_base_paddr = ctob(slot_getbasepfn(node, 0));
+                
+                rcb.rcb_cnodeid = node;
+                rcb.rcb_granularity = MD_PAGE_SIZE;
+#ifdef LATER
+                rcb.rcb_hw_counter_max = MIGR_COUNTER_MAX_GET(node);
+                rcb.rcb_diff_threshold = MIGR_THRESHOLD_DIFF_GET(node);
+#endif
+                rcb.rcb_abs_threshold = MIGR_THRESHOLD_ABS_GET(node);
+                rcb.rcb_num_slots = MAX_MEM_SLOTS;
+
+                if (COPYOUT(&rcb, arg, sizeof(rcb_info_t))) {
+                        errcode = EFAULT;
+                }
+
+                break;
+        }
+        case RCB_SLOT_GET:
+        {
+                rcb_slot_t slot[MAX_MEM_SLOTS];
+                int s;
+                int nslots;
+
+                nslots = MAX_MEM_SLOTS;
+                ASSERT(nslots <= MAX_MEM_SLOTS);
+                for (s = 0; s < nslots; s++) {
+                        slot[s].base = (uint64_t)ctob(slot_getbasepfn(node, s));
+#ifdef LATER
+                        slot[s].size  = (uint64_t)ctob(slot_getsize(node, s));
+#else
+                        slot[s].size  = (uint64_t)1;
+#endif
+                }
+                if (COPYOUT(&slot[0], arg, nslots * sizeof(rcb_slot_t))) {
+                        errcode = EFAULT;
+                }
+                
+                *rvalp = nslots;
+                break;
+        }
+                
+        default:
+                errcode = EINVAL;
+                break;
+
+        }
+        
+        return errcode;
+}
diff -Nru a/arch/ia64/sn/io/sn1/ml_SN_intr.c b/arch/ia64/sn/io/sn1/ml_SN_intr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/ml_SN_intr.c	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,1154 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ * intr.c-
+ *	This file contains all of the routines necessary to set up and
+ *	handle interrupts on an IP27 board.
+ */
+
+#ident  "$Revision: 1.167 $"
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+
+
+#if DEBUG_INTR_TSTAMP_DEBUG
+#include <sys/debug.h>
+#include <sys/idbg.h>
+#include <sys/inst.h>
+void do_splx_log(int, int);
+void spldebug_log_event(int);
+#endif
+
+#ifdef CONFIG_SMP
+extern unsigned long cpu_online_map;
+#endif
+#define cpu_allows_intr(cpu)	(1)
+// If I understand what's going on with this, 32 should work.
+// physmem_maxradius seems to be the maximum number of router
+// hops to get from one end of the system to the other.  With
+// a maximally configured machine, with the dumbest possible
+// topology, we would make 32 router hops.  For what we're using
+// it for, the dumbest possible should suffice.
+#define physmem_maxradius()	32
+
+#define SUBNODE_ANY (-1)
+
+extern int	nmied;
+extern int	hub_intr_wakeup_cnt;
+extern synergy_da_t	*Synergy_da_indr[];
+extern cpuid_t         master_procid;
+
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+
+extern void snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs);
+
+
+#define INTR_LOCK(vecblk) \
+     (s = mutex_spinlock(&(vecblk)->vector_lock))
+#define INTR_UNLOCK(vecblk) \
+      mutex_spinunlock(&(vecblk)->vector_lock, s)
+
+/*
+ * REACT/Pro
+ */
+
+
+
+/* 
+ * Find first bit set 
+ * Used outside this file also 
+ */
+int ms1bit(unsigned long x)
+{
+    int			b;
+
+    if (x >> 32)	b  = 32, x >>= 32;
+    else		b  =  0;
+    if (x >> 16)	b += 16, x >>= 16;
+    if (x >>  8)	b +=  8, x >>=  8;
+    if (x >>  4)	b +=  4, x >>=  4;
+    if (x >>  2)	b +=  2, x >>=  2;
+
+    return b + (int) (x >> 1);
+}
+
+/* ARGSUSED */
+void
+intr_stray(void *lvl)
+{
+    printk(KERN_WARNING  "Stray Interrupt - level %ld to cpu %d", (long)lvl, smp_processor_id());
+}
+
+#if defined(DEBUG)
+
+/* Infrastructure  to gather the device - target cpu mapping info */
+#define MAX_DEVICES	1000	/* Reasonable large number . Need not be 
+				 * the exact maximum # devices possible.
+				 */
+#define MAX_NAME	100	
+typedef struct {
+	dev_t		dev;	/* device */
+	cpuid_t		cpuid;	/* target cpu */
+	cnodeid_t	cnodeid;/* node on which the target cpu is present */
+	int		bit;	/* intr bit reserved */
+	char		intr_name[MAX_NAME]; /* name of the interrupt */
+} intr_dev_targ_map_t;
+
+intr_dev_targ_map_t 	intr_dev_targ_map[MAX_DEVICES];
+uint64_t		intr_dev_targ_map_size;
+spinlock_t		intr_dev_targ_map_lock;
+
+/* Print out the device - target cpu mapping.
+ * This routine is used only in the idbg command
+ * "intrmap" 
+ */
+void
+intr_dev_targ_map_print(cnodeid_t cnodeid)
+{
+	int  i,j,size = 0;
+	int  print_flag = 0,verbose = 0;	
+	char node_name[10];
+	
+	if (cnodeid != CNODEID_NONE) {
+		nodepda_t 	*npda;
+
+		npda = NODEPDA(cnodeid);
+		for (j=0; j<NUM_SUBNODES; j++) {
+			qprintf("\n SUBNODE %d\n INT_PEND0: ", j);
+			for(i = 0 ; i < N_INTPEND_BITS ; i++)
+				qprintf("%d",SNPDA(npda,j)->intr_dispatch0.info[i].ii_flags);
+			qprintf("\n INT_PEND1: ");
+			for(i = 0 ; i < N_INTPEND_BITS ; i++)
+				qprintf("%d",SNPDA(npda,j)->intr_dispatch1.info[i].ii_flags);
+		}
+		verbose = 1;
+	}
+	qprintf("\n Device - Target Map [Interrupts: %s Node%s]\n\n",
+		(verbose ? "All" : "Non-hardwired"),
+		(cnodeid == CNODEID_NONE) ? "s: All" : node_name); 
+		
+	qprintf("Device\tCpu\tCnode\tIntr_bit\tIntr_name\n");
+	for (i = 0 ; i < intr_dev_targ_map_size ; i++) {
+
+		print_flag = 0;
+		if (verbose) {
+			if (cnodeid != CNODEID_NONE) {
+				if (cnodeid == intr_dev_targ_map[i].cnodeid)
+					print_flag = 1;
+			} else {
+				print_flag = 1;
+			}
+		} else {
+			if (intr_dev_targ_map[i].dev != 0) {
+				if (cnodeid != CNODEID_NONE) {
+					if (cnodeid == 
+					    intr_dev_targ_map[i].cnodeid)
+						print_flag = 1;
+				} else {
+					print_flag = 1;
+				}
+			}
+		}
+		if (print_flag) {
+			size++;
+			qprintf("%d\t%d\t%d\t%d\t%s\n",
+				intr_dev_targ_map[i].dev,
+				intr_dev_targ_map[i].cpuid,
+				intr_dev_targ_map[i].cnodeid,
+				intr_dev_targ_map[i].bit,
+				intr_dev_targ_map[i].intr_name);
+		}
+
+	}
+	qprintf("\nTotal : %d\n",size);
+}
+#endif /* DEBUG */
+
+/*
+ * The spinlocks have already been initialized.  Now initialize the interrupt
+ * vectors.  One processor on each hub does the work.
+ */
+void
+intr_init_vecblk(nodepda_t *npda, cnodeid_t node, int sn)
+{
+    int			i, ip=0;
+    intr_vecblk_t	*vecblk;
+    subnode_pda_t	*snpda;
+
+
+    snpda = SNPDA(npda,sn);
+    do {
+	if (ip == 0) {
+	    vecblk = &snpda->intr_dispatch0;
+	} else {
+	    vecblk = &snpda->intr_dispatch1;
+	}
+
+	/* Initialize this vector. */
+	for (i = 0; i < N_INTPEND_BITS; i++) {
+		vecblk->vectors[i].iv_func = intr_stray;
+		vecblk->vectors[i].iv_prefunc = NULL;
+		vecblk->vectors[i].iv_arg = (void *)(__psint_t)(ip * N_INTPEND_BITS + i);
+
+		vecblk->info[i].ii_owner_dev = 0;
+		strcpy(vecblk->info[i].ii_name, "Unused");
+		vecblk->info[i].ii_flags = 0;	/* No flags */
+		vecblk->vectors[i].iv_mustruncpu = -1; /* No CPU yet. */
+
+	    }
+
+	mutex_spinlock_init(&vecblk->vector_lock);
+
+	vecblk->vector_count = 0;    
+	for (i = 0; i < CPUS_PER_SUBNODE; i++)
+		vecblk->cpu_count[i] = 0;
+
+	vecblk->vector_state = VECTOR_UNINITED;
+
+    } while (++ip < 2);
+
+}
+
+
+/*
+ * do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
+ *					devfs_handle_t owner_dev, char *name)
+ *	Internal work routine to reserve or unreserve an interrupt level.
+ *		cpu is the CPU to which the interrupt will be sent.
+ *		bit is the level bit to reserve.  -1 means any level
+ *		resflags should include II_ERRORINT if this is an
+ *			error interrupt, II_THREADED if the interrupt handler
+ *			will be threaded, or 0 otherwise.
+ *		reserve should be set to II_RESERVE or II_UNRESERVE
+ *			to get or clear a reservation.
+ *		owner_dev is the device that "owns" this interrupt, if supplied
+ *		name is a human-readable name for this interrupt, if supplied
+ *	intr_reserve_level returns the bit reserved or -1 to indicate an error
+ */
+static int
+do_intr_reserve_level(cpuid_t cpu, int bit, int resflags, int reserve, 
+					devfs_handle_t owner_dev, char *name)
+{
+    intr_vecblk_t	*vecblk;
+    hub_intmasks_t 	*hub_intmasks;
+    unsigned long s;
+    int rv = 0;
+    int ip;
+    synergy_da_t	*sda;
+    int		which_synergy;
+    cnodeid_t	cnode;
+
+    ASSERT(bit < N_INTPEND_BITS * 2);
+
+    cnode = cpuid_to_cnodeid(cpu);
+    which_synergy = cpuid_to_synergy(cpu);
+    sda = Synergy_da_indr[(cnode * 2) + which_synergy];
+    hub_intmasks = &sda->s_intmasks;
+    // hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
+
+    // if (pdaindr[cpu].pda == NULL) return -1;
+    if ((bit < N_INTPEND_BITS) && !(resflags & II_ERRORINT)) {
+	vecblk = hub_intmasks->dispatch0;
+	ip = 0;
+    } else {
+	ASSERT((bit >= N_INTPEND_BITS) || (bit == -1));
+	bit -= N_INTPEND_BITS;	/* Get position relative to INT_PEND1 reg. */
+	vecblk = hub_intmasks->dispatch1;
+	ip = 1;
+    }
+
+    INTR_LOCK(vecblk);
+
+    if (bit <= -1) {
+	bit = 0;
+	ASSERT(reserve == II_RESERVE);
+	/* Choose any available level */
+	for (; bit < N_INTPEND_BITS; bit++) {
+	    if (!(vecblk->info[bit].ii_flags & II_RESERVE)) {
+		rv = bit;
+		break;
+	    }
+	}
+
+	/* Return -1 if all interrupt levels int this register are taken. */
+	if (bit == N_INTPEND_BITS)
+	    rv = -1;
+
+    } else {
+	/* Reserve a particular level if it's available. */
+	if ((vecblk->info[bit].ii_flags & II_RESERVE) == reserve) {
+	    /* Can't (un)reserve a level that's already (un)reserved. */
+	    rv = -1;
+	} else {
+	    rv = bit;
+	}
+    }
+
+    /* Reserve the level and bump the count. */
+    if (rv != -1) {
+	if (reserve) {
+	    int maxlen = sizeof(vecblk->info[bit].ii_name) - 1;
+	    int namelen;
+	    vecblk->info[bit].ii_flags |= (II_RESERVE | resflags);
+	    vecblk->info[bit].ii_owner_dev = owner_dev;
+	    /* Copy in the name. */
+	    namelen = name ? strlen(name) : 0;
+	    strncpy(vecblk->info[bit].ii_name, name, min(namelen, maxlen)); 
+	    vecblk->info[bit].ii_name[maxlen] = '\0';
+	    vecblk->vector_count++;
+	} else {
+	    vecblk->info[bit].ii_flags = 0;	/* Clear all the flags */
+	    vecblk->info[bit].ii_owner_dev = 0;
+	    /* Clear the name. */
+	    vecblk->info[bit].ii_name[0] = '\0';
+	    vecblk->vector_count--;
+	}
+    }
+
+    INTR_UNLOCK(vecblk);
+
+#if defined(DEBUG)
+    if (rv >= 0) {
+	    int namelen = name ? strlen(name) : 0;
+	    /* Gather this device - target cpu mapping information
+	     * in a table which can be used later by the idbg "intrmap"
+	     * command
+	     */
+	    s = mutex_spinlock(&intr_dev_targ_map_lock);
+	    if (intr_dev_targ_map_size < MAX_DEVICES) {
+		    intr_dev_targ_map_t	*p;
+
+		    p 		= &intr_dev_targ_map[intr_dev_targ_map_size];
+		    p->dev  	= owner_dev;
+		    p->cpuid 	= cpu; 
+		    p->cnodeid 	= cpuid_to_cnodeid(cpu); 
+		    p->bit 	= ip * N_INTPEND_BITS + rv;
+		    strncpy(p->intr_name,
+			    name,
+			    min(MAX_NAME,namelen));
+		    intr_dev_targ_map_size++;
+	    }
+	    mutex_spinunlock(&intr_dev_targ_map_lock,s);
+    }
+#endif /* DEBUG */
+
+    return (((rv == -1) ? rv : (ip * N_INTPEND_BITS) + rv)) ;
+}
+
+
+/*
+ * WARNING:  This routine should only be called from within ml/SN.
+ *	Reserve an interrupt level.
+ */
+int
+intr_reserve_level(cpuid_t cpu, int bit, int resflags, devfs_handle_t owner_dev, char *name)
+{
+	return(do_intr_reserve_level(cpu, bit, resflags, II_RESERVE, owner_dev, name));
+}
+
+
+/*
+ * WARNING:  This routine should only be called from within ml/SN.
+ *	Unreserve an interrupt level.
+ */
+void
+intr_unreserve_level(cpuid_t cpu, int bit)
+{
+	(void)do_intr_reserve_level(cpu, bit, 0, II_UNRESERVE, 0, NULL);
+}
+
+/*
+ * Get values that vary depending on which CPU and bit we're operating on
+ */
+static hub_intmasks_t *
+intr_get_ptrs(cpuid_t cpu, int bit,
+	      int *new_bit,		/* Bit relative to the register */
+	      hubreg_t **intpend_masks, /* Masks for this register */
+	      intr_vecblk_t **vecblk,	/* Vecblock for this interrupt */
+	      int *ip)			/* Which intpend register */
+{
+	hub_intmasks_t *hub_intmasks;
+	synergy_da_t	*sda;
+	int		which_synergy;
+	cnodeid_t	cnode;
+
+	ASSERT(bit < N_INTPEND_BITS * 2);
+
+	cnode = cpuid_to_cnodeid(cpu);
+	which_synergy = cpuid_to_synergy(cpu);
+	sda = Synergy_da_indr[(cnode * 2) + which_synergy];
+	hub_intmasks = &sda->s_intmasks;
+
+	// hub_intmasks = &pdaindr[cpu].pda->p_intmasks;
+
+	if (bit < N_INTPEND_BITS) {
+		*intpend_masks = hub_intmasks->intpend0_masks;
+		*vecblk = hub_intmasks->dispatch0;
+		*ip = 0;
+		*new_bit = bit;
+	} else {
+		*intpend_masks = hub_intmasks->intpend1_masks;
+		*vecblk = hub_intmasks->dispatch1;
+		*ip = 1;
+		*new_bit = bit - N_INTPEND_BITS;
+	}
+
+	return hub_intmasks;
+}
+
+
+/*
+ * intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, 
+ *		intr_func_t intr_func, void *intr_arg);
+ *	This is the lowest-level interface to the interrupt code.  It shouldn't
+ *	be called from outside the ml/SN directory.
+ *	intr_connect_level hooks up an interrupt to a particular bit in
+ *	the INT_PEND0/1 masks.  Returns 0 on success.
+ *		cpu is the CPU to which the interrupt will be sent.
+ *		bit is the level bit to connect to
+ *		intr_swlevel tells which software level to use
+ *		intr_func is the interrupt handler
+ *		intr_arg is an arbitrary argument interpreted by the handler
+ *		intr_prefunc is a prologue function, to be called
+ *			with interrupts disabled, to disable
+ *			the interrupt at source.  It is called
+ *			with the same argument.  Should be NULL for
+ *			typical interrupts, which can be masked
+ *			by the infrastructure at the level bit.
+ *	intr_connect_level returns 0 on success or nonzero on an error
+ */
+/* ARGSUSED */
+int
+intr_connect_level(cpuid_t cpu, int bit, ilvl_t intr_swlevel, intr_func_t intr_prefunc)
+{
+    intr_vecblk_t	*vecblk;
+    hubreg_t		*intpend_masks;
+    int rv = 0;
+    int ip;
+    unsigned long s;
+
+    ASSERT(bit < N_INTPEND_BITS * 2);
+
+    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
+				 &vecblk, &ip);
+
+    INTR_LOCK(vecblk);
+
+    if ((vecblk->info[bit].ii_flags & II_INUSE) ||
+	(!(vecblk->info[bit].ii_flags & II_RESERVE))) {
+	/* Can't assign to a level that's in use or isn't reserved. */
+	rv = -1;
+    } else {
+	/* Stuff parameters into vector and info */
+	vecblk->vectors[bit].iv_prefunc = intr_prefunc;
+	vecblk->info[bit].ii_flags |= II_INUSE;
+    }
+
+    /* Now stuff the masks if everything's okay. */
+    if (!rv) {
+	int lslice;
+	volatile hubreg_t *mask_reg;
+	// nasid_t nasid = COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu));
+	nasid_t nasid = cpuid_to_nasid(cpu);
+	int	subnode = cpuid_to_subnode(cpu);
+
+	/* Make sure it's not already pending when we connect it. */
+	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit + ip * N_INTPEND_BITS);
+
+	if (bit >= GFX_INTR_A && bit <= CC_PEND_B) {
+		intpend_masks[0] |= (1ULL << (uint64_t)bit);
+	}
+
+	lslice = cpuid_to_localslice(cpu);
+	vecblk->cpu_count[lslice]++;
+#if SN1
+	/*
+	 * On SN1, there are 8 interrupt mask registers per node:
+	 * 	PI_0 MASK_0 A
+	 * 	PI_0 MASK_1 A
+	 * 	PI_0 MASK_0 B
+	 * 	PI_0 MASK_1 B
+	 * 	PI_1 MASK_0 A
+	 * 	PI_1 MASK_1 A
+	 * 	PI_1 MASK_0 B
+	 * 	PI_1 MASK_1 B
+	 */
+#endif
+	if (ip == 0) {
+		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode, 
+		        PI_INT_MASK0_A + PI_INT_MASK_OFFSET * lslice);
+	} else {
+		mask_reg = REMOTE_HUB_PI_ADDR(nasid, subnode,
+			PI_INT_MASK1_A + PI_INT_MASK_OFFSET * lslice);
+	}
+
+	HUB_S(mask_reg, intpend_masks[0]);
+    }
+
+    INTR_UNLOCK(vecblk);
+
+    return rv;
+}
+
+
+/*
+ * intr_disconnect_level(cpuid_t cpu, int bit)
+ *
+ *	This is the lowest-level interface to the interrupt code.  It should
+ *	not be called from outside the ml/SN directory.
+ *	intr_disconnect_level removes a particular bit from an interrupt in
+ * 	the INT_PEND0/1 masks.  Returns 0 on success or nonzero on failure.
+ */
+int
+intr_disconnect_level(cpuid_t cpu, int bit)
+{
+    intr_vecblk_t	*vecblk;
+    hubreg_t		*intpend_masks;
+    unsigned long s;
+    int rv = 0;
+    int ip;
+
+    (void)intr_get_ptrs(cpu, bit, &bit, &intpend_masks,
+				 &vecblk, &ip);
+
+    INTR_LOCK(vecblk);
+
+    if ((vecblk->info[bit].ii_flags & (II_RESERVE | II_INUSE)) !=
+	((II_RESERVE | II_INUSE))) {
+	/* Can't remove a level that's not in use or isn't reserved. */
+	rv = -1;
+    } else {
+	/* Stuff parameters into vector and info */
+	vecblk->vectors[bit].iv_func = (intr_func_t)NULL;
+	vecblk->vectors[bit].iv_prefunc = (intr_func_t)NULL;
+	vecblk->vectors[bit].iv_arg = 0;
+	vecblk->info[bit].ii_flags &= ~II_INUSE;
+#ifdef BASE_ITHRTEAD
+	vecblk->vectors[bit].iv_mustruncpu = -1; /* No mustrun CPU any more. */
+#endif
+    }
+
+    /* Now clear the masks if everything's okay. */
+    if (!rv) {
+	int lslice;
+	volatile hubreg_t *mask_reg;
+
+	intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
+	lslice = cpuid_to_localslice(cpu);
+	vecblk->cpu_count[lslice]--;
+	mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+				   cpuid_to_subnode(cpu),
+				   ip == 0 ? PI_INT_MASK0_A : PI_INT_MASK1_A);
+	mask_reg = (volatile hubreg_t *)((__psunsigned_t)mask_reg +
+					(PI_INT_MASK_OFFSET * lslice));
+	*mask_reg = intpend_masks[0];
+    }
+
+    INTR_UNLOCK(vecblk);
+
+    return rv;
+}
+
+/*
+ * Actually block or unblock an interrupt
+ */
+void
+do_intr_block_bit(cpuid_t cpu, int bit, int block)
+{
+	intr_vecblk_t *vecblk;
+	int ip;
+	unsigned long s;
+	hubreg_t *intpend_masks;
+	volatile hubreg_t mask_value;
+	volatile hubreg_t *mask_reg;
+
+	intr_get_ptrs(cpu, bit, &bit, &intpend_masks, &vecblk, &ip);
+
+	INTR_LOCK(vecblk);
+
+	if (block)
+		/* Block */
+		intpend_masks[0] &= ~(1ULL << (uint64_t)bit);
+	else
+		/* Unblock */
+		intpend_masks[0] |= (1ULL << (uint64_t)bit);
+
+	if (ip == 0) {
+		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+		        cpuid_to_subnode(cpu), PI_INT_MASK0_A);
+	} else {
+		mask_reg = REMOTE_HUB_PI_ADDR(COMPACT_TO_NASID_NODEID(cpuid_to_cnodeid(cpu)), 
+			cpuid_to_subnode(cpu), PI_INT_MASK1_A);
+	}
+
+	HUB_S(mask_reg, intpend_masks[0]);
+
+	/*
+	 * Wait for it to take effect.  (One read should suffice.)
+	 * This is only necessary when blocking an interrupt
+	 */
+	if (block)
+		while ((mask_value = HUB_L(mask_reg)) != intpend_masks[0])
+			;
+
+	INTR_UNLOCK(vecblk);
+}
+
+
+/*
+ * Block a particular interrupt (cpu/bit pair).
+ */
+/* ARGSUSED */
+void
+intr_block_bit(cpuid_t cpu, int bit)
+{
+	do_intr_block_bit(cpu, bit, 1);
+}
+
+
+/*
+ * Unblock a particular interrupt (cpu/bit pair).
+ */
+/* ARGSUSED */
+void
+intr_unblock_bit(cpuid_t cpu, int bit)
+{
+	do_intr_block_bit(cpu, bit, 0);
+}
+
+
+/* verifies that the specified CPUID is on the specified SUBNODE (if any) */
+#define cpu_on_subnode(cpuid, which_subnode) \
+	   (((which_subnode) == SUBNODE_ANY) || (cpuid_to_subnode(cpuid) == (which_subnode)))
+
+
+/*
+ * Choose one of the CPUs on a specified node or subnode to receive
+ * interrupts. Don't pick a cpu which has been specified as a NOINTR cpu.
+ *
+ * Among all acceptable CPUs, the CPU that has the fewest total number
+ * of interrupts targetted towards it is chosen.  Note that we never
+ * consider how frequent each of these interrupts might occur, so a rare
+ * hardware error interrupt is weighted equally with a disk interrupt.
+ */
+static cpuid_t
+do_intr_cpu_choose(cnodeid_t cnode, int which_subnode)
+{
+	cpuid_t 	cpu, best_cpu = CPU_NONE;
+	int		slice, min_count=1000;
+
+	min_count = 1000;
+	for (slice=0; slice < CPUS_PER_NODE; slice++) {
+		intr_vecblk_t 	*vecblk0, *vecblk1;
+		int total_intrs_to_slice;
+		subnode_pda_t *snpda;
+		int local_cpu_num;
+
+		cpu = cnode_slice_to_cpuid(cnode, slice);
+		if (cpu == CPU_NONE)
+			continue;
+
+		/* If this cpu isn't enabled for interrupts, skip it */
+		if (!cpu_enabled(cpu) || !cpu_allows_intr(cpu))
+			continue;
+
+		/* If this isn't the right subnode, skip it */
+		if (!cpu_on_subnode(cpu, which_subnode))
+			continue;
+
+		/* OK, this one's a potential CPU for interrupts */
+		snpda = SUBNODEPDA(cnode,SUBNODE(slice));
+		vecblk0 = &snpda->intr_dispatch0;
+		vecblk1 = &snpda->intr_dispatch1;
+		local_cpu_num = LOCALCPU(slice);
+		total_intrs_to_slice = vecblk0->cpu_count[local_cpu_num] +
+		              vecblk1->cpu_count[local_cpu_num];
+
+		if (min_count > total_intrs_to_slice) {
+			min_count = total_intrs_to_slice;
+			best_cpu = cpu;
+		}
+	}
+	return best_cpu;
+}
+
+/*
+ * Choose an appropriate interrupt target CPU on a specified node.
+ * If which_subnode is SUBNODE_ANY, then subnode is not considered.
+ * Otherwise, the chosen CPU must be on the specified subnode.
+ */
+static cpuid_t
+intr_cpu_choose_from_node(cnodeid_t cnode, int which_subnode)
+{
+	return(do_intr_cpu_choose(cnode, which_subnode));
+}
+
+
+/* Make it easy to identify subnode vertices in the hwgraph */
+void
+mark_subnodevertex_as_subnode(devfs_handle_t vhdl, int which_subnode)
+{
+	graph_error_t rv;
+
+	ASSERT(0 <= which_subnode);
+	ASSERT(which_subnode < NUM_SUBNODES);
+
+	rv = hwgraph_info_add_LBL(vhdl, INFO_LBL_CPUBUS, (arbitrary_info_t)which_subnode);
+	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
+
+	rv = hwgraph_info_export_LBL(vhdl, INFO_LBL_CPUBUS, sizeof(arbitrary_info_t));
+	ASSERT_ALWAYS(rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ * Given a device descriptor, extract interrupt target information and
+ * choose an appropriate CPU.  Return CPU_NONE if we can't make sense
+ * out of the target information.
+ * TBD: Should this be considered platform-independent code?
+ */
+
+
+/*
+ * intr_bit_reserve_test(cpuid,which_subnode,cnode,req_bit,intr_resflags,
+ *		owner_dev,intr_name,*resp_bit)
+ *	Either cpuid is not CPU_NONE or cnodeid not CNODE_NONE but
+ * 	not both.
+ * 1. 	If cpuid is specified, this routine tests if this cpu can be a valid
+ * 	interrupt target candidate.
+ * 2. 	If cnodeid is specified, this routine tests if there is a cpu on 
+ *	this node which can be a valid interrupt target candidate.
+ * 3.	If a valid interrupt target cpu candidate is found then an attempt at 
+ * 	reserving an interrupt bit on the corresponding cnode is made.
+ *
+ * If steps 1 & 2 both fail or step 3 fails then we are not able to get a valid
+ * interrupt target cpu then routine returns CPU_NONE (failure)
+ * Otherwise routine returns cpuid of interrupt target (success)
+ */
+static cpuid_t
+intr_bit_reserve_test(cpuid_t 		cpuid,
+		      int		favor_subnode,
+		      cnodeid_t 	cnodeid,
+		      int		req_bit,
+		      int 		intr_resflags,
+		      devfs_handle_t 	owner_dev,
+		      char		*intr_name,
+		      int		*resp_bit)
+{
+
+	ASSERT((cpuid==CPU_NONE) || (cnodeid==CNODEID_NONE));
+
+	if (cnodeid != CNODEID_NONE) {
+		/* Try to choose a interrupt cpu candidate */
+		cpuid = intr_cpu_choose_from_node(cnodeid, favor_subnode);
+	}
+
+	if (cpuid != CPU_NONE) {
+		/* Try to reserve an interrupt bit on the hub 
+		 * corresponding to the canidate cnode. If we
+		 * are successful then we got a cpu which can
+		 * act as an interrupt target for the io device.
+		 * Otherwise we need to continue the search
+		 * further.
+		 */
+		*resp_bit = do_intr_reserve_level(cpuid, 
+						  req_bit,
+						  intr_resflags,
+						  II_RESERVE,
+						  owner_dev, 
+						  intr_name);
+
+		if (*resp_bit >= 0)
+			/* The interrupt target  specified was fine */
+			return(cpuid);
+	}
+	return(CPU_NONE);
+}
+/*
+ * intr_heuristic(dev_t dev,device_desc_t dev_desc,
+ *		  int req_bit,int intr_resflags,dev_t owner_dev,
+ *		  char *intr_name,int *resp_bit)
+ *
+ * Choose an interrupt destination for an interrupt.
+ *	dev is the device for which the interrupt is being set up
+ *	dev_desc is a description of hardware and policy that could
+ *		help determine where this interrupt should go
+ *	req_bit is the interrupt bit requested 
+ *		(can be INTRCONNECT_ANY_BIT in which the first available
+ * 		 interrupt bit is used)
+ *	intr_resflags indicates whether we want to (un)reserve bit
+ *	owner_dev is the owner device
+ *	intr_name is the readable interrupt name	
+ * 	resp_bit indicates whether we succeeded in getting the required
+ *		 action  { (un)reservation} done	
+ *		 negative value indicates failure
+ *
+ */
+/* ARGSUSED */
+cpuid_t
+intr_heuristic(devfs_handle_t 		dev,
+	       device_desc_t 	dev_desc,
+	       int		req_bit,
+	       int 		intr_resflags,
+	       devfs_handle_t 		owner_dev,
+	       char		*intr_name,
+	       int		*resp_bit)
+{
+	cpuid_t		cpuid;				/* possible intr targ*/
+	cnodeid_t 	candidate;			/* possible canidate */
+	int		which_subnode = SUBNODE_ANY;
+
+/* SN1 + pcibr Addressing Limitation */
+	{
+	devfs_handle_t pconn_vhdl;
+	pcibr_soft_t pcibr_soft;
+
+	/*
+	 * This combination of SN1 and Bridge hardware has an odd "limitation".
+	 * Due to the choice of addresses for PI0 and PI1 registers on SN1
+	 * and historical limitations in Bridge, Bridge is unable to
+	 * send interrupts to both PI0 CPUs and PI1 CPUs -- we have
+	 * to choose one set or the other.  That choice is implicitly
+	 * made when Bridge first attaches its error interrupt.  After
+	 * that point, all subsequent interrupts are restricted to the
+	 * same PI number (though it's possible to send interrupts to
+	 * the same PI number on a different node).
+	 *
+	 * Since neither SN1 nor Bridge designers are willing to admit a
+	 * bug, we can't really call this a "workaround".  It's a permanent
+	 * solution for an SN1-specific and Bridge-specific hardware
+	 * limitation that won't ever be lifted.
+	 */
+        if ((hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
+	   ((pcibr_soft = pcibr_soft_get(pconn_vhdl)) != NULL)) {
+		/*
+		 * We "know" that the error interrupt is the first
+		 * interrupt set up by pcibr_attach.  Send all interrupts
+		 * on this bridge to the same subnode number.
+		 */
+		if (pcibr_soft->bsi_err_intr) {
+			which_subnode = cpuid_to_subnode(((hub_intr_t) pcibr_soft->bsi_err_intr)->i_cpuid);
+		}
+	}
+	}
+
+	/* Check if we can find a valid interrupt target candidate on
+	 * the master node for the device.
+	 */
+	cpuid = intr_bit_reserve_test(CPU_NONE,
+				      which_subnode,	
+				      master_node_get(dev),
+				      req_bit,
+				      intr_resflags,
+				      owner_dev,
+				      intr_name,
+				      resp_bit);
+
+	if (cpuid != CPU_NONE) {
+		if (cpu_on_subnode(cpuid, which_subnode))
+			return(cpuid);	/* got a valid interrupt target */
+		else
+			intr_unreserve_level(cpuid, *resp_bit);
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts to closest node(%d): (0x%lx)\n",
+		master_node_get(dev),(unsigned long)owner_dev);
+
+	/* Fall through into the default algorithm
+	 * (exhaustive-search-for-the-nearest-possible-interrupt-target)
+	 * for finding the interrupt target
+	 */
+
+	{
+	/*
+	 * Do a stupid round-robin assignment of the node.
+	 *  (Should do a "nearest neighbor" but not for SN1.
+	 */
+		static cnodeid_t last_node = -1;
+
+		if (last_node >= numnodes) last_node = 0;
+		for (candidate = last_node + 1; candidate != last_node; candidate++) {
+			if (candidate == numnodes) candidate = 0;
+			cpuid = intr_bit_reserve_test(CPU_NONE,
+					      which_subnode,
+					      candidate,
+					      req_bit,
+					      intr_resflags,
+					      owner_dev,
+					      intr_name,
+					      resp_bit);
+
+			if (cpuid != CPU_NONE) {
+				if (cpu_on_subnode(cpuid, which_subnode)) {
+					last_node = candidate;
+					return(cpuid);	/* got a valid interrupt target */
+				}
+				else
+					intr_unreserve_level(cpuid, *resp_bit);
+			}
+		}
+		last_node = candidate;
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts to any close node: %ld (0x%lx)\n",
+		(long)owner_dev, (unsigned long)owner_dev);
+
+	/* In the worst case try to allocate interrupt bits on the
+	 * master processor's node. We may get here during error interrupt
+	 * allocation phase when the topology matrix is not yet setup
+	 * and hence cannot do an exhaustive search.
+	 */
+	ASSERT(cpu_allows_intr(master_procid));
+	cpuid = intr_bit_reserve_test(master_procid,
+				      which_subnode,
+				      CNODEID_NONE,
+				      req_bit,
+				      intr_resflags,
+				      owner_dev,
+				      intr_name,
+				      resp_bit);
+
+	if (cpuid != CPU_NONE) {
+		if (cpu_on_subnode(cpuid, which_subnode))
+			return(cpuid);
+		else
+			intr_unreserve_level(cpuid, *resp_bit);
+	}
+
+	printk(KERN_WARNING  "Cannot target interrupts: (0x%lx)\n",
+		(unsigned long)owner_dev);
+
+	return(CPU_NONE);	/* Should never get here */
+}
+
+struct hardwired_intr_s {
+	signed char level;
+	int flags;
+	char *name;
+} const hardwired_intr[] = {
+	{ INT_PEND0_BASELVL + RESERVED_INTR,	0,	"Reserved" },
+	{ INT_PEND0_BASELVL + GFX_INTR_A,	0, 	"Gfx A" },
+	{ INT_PEND0_BASELVL + GFX_INTR_B,	0, 	"Gfx B" },
+	{ INT_PEND0_BASELVL + PG_MIG_INTR,	II_THREADED, "Migration" },
+	{ INT_PEND0_BASELVL + UART_INTR,	II_THREADED, "Bedrock/L1" },
+	{ INT_PEND0_BASELVL + CC_PEND_A,	0,	"Crosscall A" },
+	{ INT_PEND0_BASELVL + CC_PEND_B,	0,	"Crosscall B" },
+	{ INT_PEND1_BASELVL + CLK_ERR_INTR,	II_ERRORINT, "Clock Error" },
+	{ INT_PEND1_BASELVL + COR_ERR_INTR_A,	II_ERRORINT, "Correctable Error A" },
+	{ INT_PEND1_BASELVL + COR_ERR_INTR_B,	II_ERRORINT, "Correctable Error B" },
+	{ INT_PEND1_BASELVL + MD_COR_ERR_INTR,	II_ERRORINT, "MD Correct. Error" },
+	{ INT_PEND1_BASELVL + NI_ERROR_INTR,	II_ERRORINT, "NI Error" },
+	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_A,	II_ERRORINT, "Remote NI Error"},
+	{ INT_PEND1_BASELVL + NI_BRDCAST_ERR_B,	II_ERRORINT, "Remote NI Error"},
+	{ INT_PEND1_BASELVL + MSC_PANIC_INTR,	II_ERRORINT, "MSC Panic" },
+	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_A,	II_ERRORINT, "LLP Pfail WAR" },
+	{ INT_PEND1_BASELVL + LLP_PFAIL_INTR_B,	II_ERRORINT, "LLP Pfail WAR" },
+	{ INT_PEND1_BASELVL + NACK_INT_A,	0, "CPU A Nack count == NACK_CMP" },
+	{ INT_PEND1_BASELVL + NACK_INT_B,	0, "CPU B Nack count == NACK_CMP" },
+	{ INT_PEND1_BASELVL + LB_ERROR,		0, "Local Block Error" },
+	{ INT_PEND1_BASELVL + XB_ERROR,		0, "Local XBar Error" },
+	{ -1, 0, (char *)NULL},
+};
+
+/*
+ * Reserve all of the hardwired interrupt levels so they're not used as
+ * general purpose bits later.
+ */
+void
+intr_reserve_hardwired(cnodeid_t cnode)
+{
+	cpuid_t cpu;
+	int level;
+	int i;
+	char subnode_done[NUM_SUBNODES];
+
+	// cpu = cnodetocpu(cnode);
+	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
+		if (cpuid_to_cnodeid(cpu) == cnode) {
+			break;
+		}
+	}
+	if (cpu == smp_num_cpus) cpu = CPU_NONE;
+	if (cpu == CPU_NONE) {
+		printk("Node %d has no CPUs", cnode);
+		return;
+	}
+
+	for (i=0; i<NUM_SUBNODES; i++)
+		subnode_done[i] = 0;
+
+	for (; cpu<smp_num_cpus && cpu_enabled(cpu) && cpuid_to_cnodeid(cpu) == cnode; cpu++) {
+		int which_subnode = cpuid_to_subnode(cpu);
+		if (subnode_done[which_subnode])
+			continue;
+		subnode_done[which_subnode] = 1;
+
+		for (i = 0; hardwired_intr[i].level != -1; i++) {
+			level = hardwired_intr[i].level;
+
+			if (level != intr_reserve_level(cpu, level,
+						hardwired_intr[i].flags,
+						(devfs_handle_t) NULL,
+						hardwired_intr[i].name))
+				panic("intr_reserve_hardwired: Can't reserve level %d, cpu %ld.", level, cpu);
+		}
+	}
+}
+
+
+/*
+ * Check and clear interrupts.
+ */
+/*ARGSUSED*/
+static void
+intr_clear_bits(nasid_t nasid, volatile hubreg_t *pend, int base_level,
+		char *name)
+{
+	volatile hubreg_t bits;
+	int i;
+
+	/* Check pending interrupts */
+	if ((bits = HUB_L(pend)) != 0) {
+		for (i = 0; i < N_INTPEND_BITS; i++) {
+			if (bits & (1 << i)) {
+#ifdef INTRDEBUG
+				printk(KERN_WARNING  "Nasid %d interrupt bit %d set in %s",
+					nasid, i, name);
+#endif
+				LOCAL_HUB_CLR_INTR(base_level + i);
+			}
+		}
+	}
+}
+
+/*
+ * Clear out our interrupt registers.
+ */
+void
+intr_clear_all(nasid_t nasid)
+{
+	int	sn;
+
+	for(sn=0; sn<NUM_SUBNODES; sn++) {
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_A, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK0_B, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_A, 0);
+		REMOTE_HUB_PI_S(nasid, sn, PI_INT_MASK1_B, 0);
+	
+		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND0),
+				INT_PEND0_BASELVL, "INT_PEND0");
+		intr_clear_bits(nasid, REMOTE_HUB_PI_ADDR(nasid, sn, PI_INT_PEND1),
+				INT_PEND1_BASELVL, "INT_PEND1");
+	}
+}
+
+/* 
+ * Dump information about a particular interrupt vector.
+ */
+static void
+dump_vector(intr_info_t *info, intr_vector_t *vector, int bit, hubreg_t ip,
+		hubreg_t ima, hubreg_t imb, void (*pf)(char *, ...))
+{
+	hubreg_t value = 1LL << bit;
+
+	pf("  Bit %02d: %s: func 0x%x arg 0x%x prefunc 0x%x\n",
+		bit, info->ii_name,
+		vector->iv_func, vector->iv_arg, vector->iv_prefunc);
+	pf("   vertex 0x%x %s%s",
+		info->ii_owner_dev,
+		((info->ii_flags) & II_RESERVE) ? "R" : "U",
+		((info->ii_flags) & II_INUSE) ? "C" : "-");
+	pf("%s%s%s%s",
+		ip & value ? "P" : "-",
+		ima & value ? "A" : "-",
+		imb & value ? "B" : "-",
+		((info->ii_flags) & II_ERRORINT) ? "E" : "-");
+	pf("\n");
+}
+
+
+/*
+ * Dump information about interrupt vector assignment.
+ */
+void
+intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...))
+{
+	nodepda_t *npda;
+	int ip, sn, bit;
+	intr_vecblk_t *dispatch;
+	hubreg_t ipr, ima, imb;
+	nasid_t nasid;
+
+	if ((cnode < 0) || (cnode >= numnodes)) {
+		pf("intr_dumpvec: cnodeid out of range: %d\n", cnode);
+		return ;
+	}
+
+	nasid = COMPACT_TO_NASID_NODEID(cnode);
+
+	if (nasid == INVALID_NASID) {
+		pf("intr_dumpvec: Bad cnodeid: %d\n", cnode);
+		return ;
+	}
+		
+
+	npda = NODEPDA(cnode);
+
+	for (sn = 0; sn < NUM_SUBNODES; sn++) {
+		for (ip = 0; ip < 2; ip++) {
+			dispatch = ip ? &(SNPDA(npda,sn)->intr_dispatch1) : &(SNPDA(npda,sn)->intr_dispatch0);
+			ipr = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_PEND1 : PI_INT_PEND0);
+			ima = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_A : PI_INT_MASK0_A);
+			imb = REMOTE_HUB_PI_L(nasid, sn, ip ? PI_INT_MASK1_B : PI_INT_MASK0_B);
+	
+			pf("Node %d INT_PEND%d:\n", cnode, ip);
+	
+			if (dispatch->ithreads_enabled)
+				pf(" Ithreads enabled\n");
+			else
+				pf(" Ithreads disabled\n");
+			pf(" vector_count = %d, vector_state = %d\n",
+				dispatch->vector_count,
+				dispatch->vector_state);
+			pf(" CPU A count %d, CPU B count %d\n",
+ 		   	dispatch->cpu_count[0],
+ 		   	dispatch->cpu_count[1]);
+			pf(" &vector_lock = 0x%x\n",
+				&(dispatch->vector_lock));
+			for (bit = 0; bit < N_INTPEND_BITS; bit++) {
+				if ((dispatch->info[bit].ii_flags & II_RESERVE) ||
+			    	(ipr & (1L << bit))) {
+					dump_vector(&(dispatch->info[bit]),
+					    	&(dispatch->vectors[bit]),
+					    	bit, ipr, ima, imb, pf);
+				}
+			}
+			pf("\n");
+		}
+	}
+}
+
diff -Nru a/arch/ia64/sn/io/sn1/pcibr.c b/arch/ia64/sn/io/sn1/pcibr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn1/pcibr.c	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,7950 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+int NeedXbridgeSwap = 0;
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+extern boolean_t                is_sys_critical_vertex(devfs_handle_t);
+
+#undef PCIBR_ATE_DEBUG
+
+#if 0
+#define DEBUG 1	 /* To avoid lots of bad printk() formats leave off */
+#endif
+#define PCI_DEBUG 1
+#define ATTACH_DEBUG 1
+#define PCIBR_SOFT_LIST 1
+
+#ifndef	LOCAL
+#define	LOCAL		static
+#endif
+
+/*
+ * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
+ * appears that if the lucent part can get into a retry loop if it sees a
+ * DAC on the bus during a pio read retry.  The loop is broken after about
+ * 1ms, so we need to set up bridges holding this part to allow at least
+ * 1ms for pio.
+ */
+
+#define USS302_TIMEOUT_WAR
+
+#ifdef USS302_TIMEOUT_WAR
+#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
+#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
+#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
+#define USS302_BRIDGE_TIMEOUT_HLD	4
+#endif
+
+#define PCIBR_LLP_CONTROL_WAR
+#if defined (PCIBR_LLP_CONTROL_WAR)
+int                     pcibr_llp_control_war_cnt;
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+int                     pcibr_devflag = D_MP;
+
+#ifdef LATER
+#define F(s,n)		{ 1l<<(s),-(s), n }
+
+struct reg_desc         bridge_int_status_desc[] =
+{
+    F(31, "MULTI_ERR"),
+    F(30, "PMU_ESIZE_EFAULT"),
+    F(29, "UNEXPECTED_RESP"),
+    F(28, "BAD_XRESP_PACKET"),
+    F(27, "BAD_XREQ_PACKET"),
+    F(26, "RESP_XTALK_ERROR"),
+    F(25, "REQ_XTALK_ERROR"),
+    F(24, "INVALID_ADDRESS"),
+    F(23, "UNSUPPORTED_XOP"),
+    F(22, "XREQ_FIFO_OFLOW"),
+    F(21, "LLP_REC_SNERROR"),
+    F(20, "LLP_REC_CBERROR"),
+    F(19, "LLP_RCTY"),
+    F(18, "LLP_TX_RETRY"),
+    F(17, "LLP_TCTY"),
+    F(16, "SSRAM_PERR"),
+    F(15, "PCI_ABORT"),
+    F(14, "PCI_PARITY"),
+    F(13, "PCI_SERR"),
+    F(12, "PCI_PERR"),
+    F(11, "PCI_MASTER_TOUT"),
+    F(10, "PCI_RETRY_CNT"),
+    F(9, "XREAD_REQ_TOUT"),
+    F(8, "GIO_BENABLE_ERR"),
+    F(7, "INT7"),
+    F(6, "INT6"),
+    F(5, "INT5"),
+    F(4, "INT4"),
+    F(3, "INT3"),
+    F(2, "INT2"),
+    F(1, "INT1"),
+    F(0, "INT0"),
+    {0}
+};
+
+struct reg_values       space_v[] =
+{
+    {PCIIO_SPACE_NONE, "none"},
+    {PCIIO_SPACE_ROM, "ROM"},
+    {PCIIO_SPACE_IO, "I/O"},
+    {PCIIO_SPACE_MEM, "MEM"},
+    {PCIIO_SPACE_MEM32, "MEM(32)"},
+    {PCIIO_SPACE_MEM64, "MEM(64)"},
+    {PCIIO_SPACE_CFG, "CFG"},
+    {PCIIO_SPACE_WIN(0), "WIN(0)"},
+    {PCIIO_SPACE_WIN(1), "WIN(1)"},
+    {PCIIO_SPACE_WIN(2), "WIN(2)"},
+    {PCIIO_SPACE_WIN(3), "WIN(3)"},
+    {PCIIO_SPACE_WIN(4), "WIN(4)"},
+    {PCIIO_SPACE_WIN(5), "WIN(5)"},
+    {PCIIO_SPACE_BAD, "BAD"},
+    {0}
+};
+
+struct reg_desc         space_desc[] =
+{
+    {0xFF, 0, "space", 0, space_v},
+    {0}
+};
+
+#if DEBUG
+#define	device_desc	device_bits
+LOCAL struct reg_desc   device_bits[] =
+{
+    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
+    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
+    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
+    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
+    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
+    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
+    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
+    {BRIDGE_DEV_RT, 0, "RT"},
+    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
+    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
+    {BRIDGE_DEV_PREF, 0, "PREF"},
+    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
+    {BRIDGE_DEV_COH, 0, "COH"},
+    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
+    {BRIDGE_DEV_GBR, 0, "GBR"},
+    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
+    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
+    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
+    {0}
+};
+#endif	/* DEBUG */
+
+#ifdef SUPPORT_PRINTING_R_FORMAT
+LOCAL struct reg_values xio_cmd_pactyp[] =
+{
+    {0x0, "RdReq"},
+    {0x1, "RdResp"},
+    {0x2, "WrReqWithResp"},
+    {0x3, "WrResp"},
+    {0x4, "WrReqNoResp"},
+    {0x5, "Reserved(5)"},
+    {0x6, "FetchAndOp"},
+    {0x7, "Reserved(7)"},
+    {0x8, "StoreAndOp"},
+    {0x9, "Reserved(9)"},
+    {0xa, "Reserved(a)"},
+    {0xb, "Reserved(b)"},
+    {0xc, "Reserved(c)"},
+    {0xd, "Reserved(d)"},
+    {0xe, "SpecialReq"},
+    {0xf, "SpecialResp"},
+    {0}
+};
+
+LOCAL struct reg_desc   xio_cmd_bits[] =
+{
+    {WIDGET_DIDN, -28, "DIDN", "%x"},
+    {WIDGET_SIDN, -24, "SIDN", "%x"},
+    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
+    {WIDGET_TNUM, -15, "TNUM", "%x"},
+    {WIDGET_COHERENT, 0, "COHERENT"},
+    {WIDGET_DS, 0, "DS"},
+    {WIDGET_GBR, 0, "GBR"},
+    {WIDGET_VBPM, 0, "VBPM"},
+    {WIDGET_ERROR, 0, "ERROR"},
+    {WIDGET_BARRIER, 0, "BARRIER"},
+    {0}
+};
+#endif	/* SUPPORT_PRINTING_R_FORMAT */
+
+#if PCIBR_FREEZE_TIME || PCIBR_ATE_DEBUG
+LOCAL struct reg_desc   ate_bits[] =
+{
+    {0xFFFF000000000000ull, -48, "RMF", "%x"},
+    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
+     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
+    {0x0000000000000F00ull, -8, "port", "%x"},
+    {0x0000000000000010ull, 0, "Barrier"},
+    {0x0000000000000008ull, 0, "Prefetch"},
+    {0x0000000000000004ull, 0, "Precise"},
+    {0x0000000000000002ull, 0, "Coherent"},
+    {0x0000000000000001ull, 0, "Valid"},
+    {0}
+};
+#endif
+
+#if PCIBR_ATE_DEBUG
+LOCAL struct reg_values ssram_sizes[] =
+{
+    {BRIDGE_CTRL_SSRAM_512K, "512k"},
+    {BRIDGE_CTRL_SSRAM_128K, "128k"},
+    {BRIDGE_CTRL_SSRAM_64K, "64k"},
+    {BRIDGE_CTRL_SSRAM_1K, "1k"},
+    {0}
+};
+
+LOCAL struct reg_desc   control_bits[] =
+{
+    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
+    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
+    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
+    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
+    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
+    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
+    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
+    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
+    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
+    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
+    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
+    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
+    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
+    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
+    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
+    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
+    {BRIDGE_CTRL_MAX_TRANS_MASK, -4, "MAX_TRANS", "%d"},
+    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+/* kbrick widgetnum-to-bus layout */
+int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
+        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
+        2,                                      /* 0x8          */
+        1,                                      /* 0x9          */
+        0, 0,                                   /* 0xa - 0xb    */
+        5,                                      /* 0xc          */
+        6,                                      /* 0xd          */
+        4,                                      /* 0xe          */
+        3,                                      /* 0xf          */
+};
+
+/*
+ * Additional PIO spaces per slot are
+ * recorded in this structure.
+ */
+struct pciio_piospace_s {
+    pciio_piospace_t        next;	/* another space for this device */
+    char                    free;	/* 1 if free, 0 if in use               */
+    pciio_space_t           space;	/* Which space is in use                */
+    iopaddr_t               start;	/* Starting address of the PIO space    */
+    size_t                  count;	/* size of PIO space                    */
+};
+
+#if PCIBR_SOFT_LIST
+pcibr_list_p            pcibr_list = 0;
+#endif
+
+#define	INFO_LBL_PCIBR_ASIC_REV	"_pcibr_asic_rev"
+
+#define	PCIBR_D64_BASE_UNSET	(0xFFFFFFFFFFFFFFFF)
+#define	PCIBR_D32_BASE_UNSET	(0xFFFFFFFF)
+
+#define PCIBR_VALID_SLOT(s)	(s < 8)
+
+#ifdef SN_XXX
+extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
+                                     hub_widget_flags_t flags);
+#endif
+extern pciio_dmamap_t get_free_pciio_dmamap(devfs_handle_t);
+extern void free_pciio_dmamap(pcibr_dmamap_t);
+
+/*
+ * This is the file operation table for the pcibr driver.
+ * As each of the functions are implemented, put the 
+ * appropriate function name below.
+ */
+struct file_operations pcibr_fops = {
+        owner:  THIS_MODULE,
+        llseek: NULL,
+        read: NULL,
+        write: NULL,
+        readdir: NULL,
+        poll: NULL,
+        ioctl: NULL,
+        mmap: NULL,
+        open: NULL,
+        flush: NULL,
+        release: NULL,
+        fsync: NULL,
+        fasync: NULL,
+        lock: NULL,
+        readv: NULL,
+        writev: NULL
+};
+
+extern devfs_handle_t hwgraph_root;
+extern graph_error_t hwgraph_vertex_unref(devfs_handle_t vhdl);
+extern int cap_able(uint64_t x);
+extern uint64_t rmalloc(struct map *mp, size_t size);
+extern void rmfree(struct map *mp, size_t size, uint64_t a);
+extern int hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
+extern long atoi(register char *p);
+extern void *swap_ptr(void **loc, void *new);
+extern char *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
+extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t vhdl);
+extern graph_error_t hwgraph_edge_remove(devfs_handle_t from, char *name, devfs_handle_t *toptr);
+extern struct map *rmallocmap(uint64_t mapsiz);
+extern void rmfreemap(struct map *mp);
+extern int compare_and_swap_ptr(void **location, void *old_ptr, void *new_ptr);
+extern int io_path_map_widget(devfs_handle_t vertex);
+
+
+
+/* =====================================================================
+ *    Function Table of Contents
+ *
+ *      The order of functions in this file has stopped
+ *      making much sense. We might want to take a look
+ *      at it some time and bring back some sanity, or
+ *      perhaps bust this file into smaller chunks.
+ */
+
+LOCAL void              do_pcibr_rrb_clear(bridge_t *, int);
+LOCAL void              do_pcibr_rrb_flush(bridge_t *, int);
+LOCAL int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+LOCAL int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+LOCAL int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+LOCAL int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+LOCAL void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+int			pcibr_wrb_flush(devfs_handle_t);
+int                     pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+int                     pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+int                     pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+void                    pcibr_rrb_flush(devfs_handle_t);
+
+LOCAL int               pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
+void                    pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
+
+LOCAL void              pcibr_clearwidint(bridge_t *);
+LOCAL void              pcibr_setwidint(xtalk_intr_t);
+LOCAL int               pcibr_probe_slot(bridge_t *, cfg_p, unsigned *);
+
+void                    pcibr_init(void);
+int                     pcibr_attach(devfs_handle_t);
+int			pcibr_detach(devfs_handle_t);
+int                     pcibr_open(devfs_handle_t *, int, int, cred_t *);
+int                     pcibr_close(devfs_handle_t, int, int, cred_t *);
+int                     pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
+int                     pcibr_unmap(devfs_handle_t, vhandl_t *);
+int                     pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
+
+void                    pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+
+LOCAL int               pcibr_init_ext_ate_ram(bridge_t *);
+LOCAL int               pcibr_ate_alloc(pcibr_soft_t, int);
+LOCAL void              pcibr_ate_free(pcibr_soft_t, int, int);
+
+LOCAL pcibr_info_t      pcibr_info_get(devfs_handle_t);
+LOCAL pcibr_info_t      pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
+LOCAL void		pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
+LOCAL iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+
+pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
+void                    pcibr_piomap_free(pcibr_piomap_t);
+caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
+void                    pcibr_piomap_done(pcibr_piomap_t);
+caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
+void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
+
+LOCAL iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
+LOCAL bridge_ate_t      pcibr_flags_to_ate(unsigned);
+
+pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
+void                    pcibr_dmamap_free(pcibr_dmamap_t);
+LOCAL bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
+LOCAL iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
+iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
+alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_done(pcibr_dmamap_t);
+cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
+iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
+alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_drain(pcibr_dmamap_t);
+void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
+void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
+iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+static unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+void                    pcibr_intr_free(pcibr_intr_t);
+LOCAL void              pcibr_setpciint(xtalk_intr_t);
+int                     pcibr_intr_connect(pcibr_intr_t);
+void                    pcibr_intr_disconnect(pcibr_intr_t);
+
+devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
+void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+void                    pcibr_intr_func(intr_arg_t);
+
+void                    pcibr_provider_startup(devfs_handle_t);
+void                    pcibr_provider_shutdown(devfs_handle_t);
+
+int                     pcibr_reset(devfs_handle_t);
+pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
+int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
+pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
+int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
+
+LOCAL cfg_p             pcibr_config_addr(devfs_handle_t, unsigned);
+uint64_t                pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+LOCAL uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
+void                    pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+LOCAL void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+LOCAL pcibr_hints_t     pcibr_hints_get(devfs_handle_t, int);
+void                    pcibr_hints_fix_rrbs(devfs_handle_t);
+void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+void                    pcibr_hints_handsoff(devfs_handle_t);
+void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, ulong);
+
+LOCAL int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
+
+#ifdef LATER
+LOCAL int	        pcibr_slot_info_return(pcibr_soft_t, pciio_slot_t,
+                                               pcibr_slot_info_resp_t);
+LOCAL void       	pcibr_slot_func_info_return(pcibr_info_h, int,
+                                                    pcibr_slot_func_info_resp_t);
+#endif	/* LATER */
+
+LOCAL int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
+LOCAL int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+LOCAL int		pcibr_slot_call_device_attach(devfs_handle_t,
+						      pciio_slot_t, int);
+LOCAL int		pcibr_slot_call_device_detach(devfs_handle_t,
+						      pciio_slot_t, int);
+
+LOCAL int               pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
+LOCAL int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
+#ifdef LATER
+LOCAL int		pcibr_slot_query(devfs_handle_t, pcibr_slot_info_req_t);
+#endif
+
+/* =====================================================================
+ *    RRB management
+ */
+
+#define LSBIT(word)		((word) &~ ((word)-1))
+
+#define PCIBR_RRB_SLOT_VIRTUAL	8
+
+LOCAL void
+do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
+{
+    bridgereg_t             status;
+
+    /* bridge_lock must be held;
+     * this RRB must be disabled.
+     */
+
+    /* wait until RRB has no outstanduing XIO packets. */
+    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
+	;				/* XXX- beats on bridge. bad idea? */
+    }
+
+    /* if the RRB has data, drain it. */
+    if (status & BRIDGE_RRB_VALID(rrb)) {
+	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
+
+	/* wait until RRB is no longer valid. */
+	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
+	    ;				/* XXX- beats on bridge. bad idea? */
+	}
+    }
+}
+
+LOCAL void
+do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
+{
+    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
+    bridgereg_t             rrbv;
+    int                     shft = 4 * (rrbn >> 1);
+    unsigned                ebit = BRIDGE_RRB_EN << shft;
+
+    rrbv = *rrbp;
+    if (rrbv & ebit)
+	*rrbp = rrbv & ~ebit;
+
+    do_pcibr_rrb_clear(bridge, rrbn);
+
+    if (rrbv & ebit)
+	*rrbp = rrbv;
+}
+
+/*
+ *    pcibr_rrb_count_valid: count how many RRBs are
+ *      marked valid for the specified PCI slot on this
+ *      bridge.
+ *
+ *      NOTE: The "slot" parameter for all pcibr_rrb
+ *      management routines must include the "virtual"
+ *      bit; when manageing both the normal and the
+ *      virtual channel, separate calls to these
+ *      routines must be made. To denote the virtual
+ *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
+ *      number.
+ *
+ *      IMPL NOTE: The obvious algorithm is to iterate
+ *      through the RRB fields, incrementing a count if
+ *      the RRB is valid and matches the slot. However,
+ *      it is much simpler to use an algorithm derived
+ *      from the "partitioned add" idea. First, XOR in a
+ *      pattern such that the fields that match this
+ *      slot come up "all ones" and all other fields
+ *      have zeros in the mismatching bits. Then AND
+ *      together the bits in the field, so we end up
+ *      with one bit turned on for each field that
+ *      matched. Now we need to count these bits. This
+ *      can be done either with a series of shift/add
+ *      instructions or by using "tmp % 15"; I expect
+ *      that the cascaded shift/add will be faster.
+ */
+
+LOCAL int
+do_pcibr_rrb_count_valid(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp ^= 0x11111111 * (7 - slot / 2);
+    tmp &= (0xCCCCCCCC & tmp) >> 2;
+    tmp &= (0x22222222 & tmp) >> 1;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_count_avail: count how many RRBs are
+ *      available to be allocated for the specified slot.
+ *
+ *      IMPL NOTE: similar to the above, except we are
+ *      just counting how many fields have the valid bit
+ *      turned off.
+ */
+LOCAL int
+do_pcibr_rrb_count_avail(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~tmp) >> 3;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_alloc: allocate some additional RRBs
+ *      for the specified slot. Returns -1 if there were
+ *      insufficient free RRBs to satisfy the request,
+ *      or 0 if the request was fulfilled.
+ *
+ *      Note that if a request can be partially filled,
+ *      it will be, even if we return failure.
+ *
+ *      IMPL NOTE: again we avoid iterating across all
+ *      the RRBs; instead, we form up a word containing
+ *      one bit for each free RRB, then peel the bits
+ *      off from the low end.
+ */
+LOCAL int
+do_pcibr_rrb_alloc(bridge_t *bridge,
+		   pciio_slot_t slot,
+		   int more)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, bit;
+
+    reg = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~reg) >> 3;
+    while (more-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+    return rv;
+}
+
+/*
+ *    do_pcibr_rrb_free: release some of the RRBs that
+ *      have been allocated for the specified
+ *      slot. Returns zero for success, or negative if
+ *      it was unable to free that many RRBs.
+ *
+ *      IMPL NOTE: We form up a bit for each RRB
+ *      allocated to the slot, aligned with the VALID
+ *      bitfield this time; then we peel bits off one at
+ *      a time, releasing the corresponding RRB.
+ */
+LOCAL int
+do_pcibr_rrb_free(bridge_t *bridge,
+		  pciio_slot_t slot,
+		  int less)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, clr, bit;
+    int                     i;
+
+    clr = 0;
+    reg = bridge->b_rrb_map[slot & 1].reg;
+
+    /* This needs to be done otherwise the rrb's on the virtual channel
+     * for this slot won't be freed !!
+     */
+    tmp = reg & 0xbbbbbbbb;
+
+    tmp ^= (0x11111111 * (7 - slot / 2));
+    tmp &= (0x33333333 & tmp) << 2;
+    tmp &= (0x44444444 & tmp) << 1;
+    while (less-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg &= ~bit;
+	clr |= bit;
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+
+    for (i = 0; i < 8; i++)
+	if (clr & (8 << (4 * i)))
+	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
+
+    return rv;
+}
+
+LOCAL void
+do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
+		       int slot,
+		       int more_rrbs)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     got;
+
+    for (got = 0; got < more_rrbs; ++got) {
+	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
+	    pcibr_soft->bs_rrb_res[slot & 7]--;
+	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
+	    pcibr_soft->bs_rrb_avail[slot & 1]--;
+	else
+	    break;
+	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
+	    break;
+#if PCIBR_RRB_DEBUG
+	printk( "do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
+		slot & 7, slot & 8 ? "v" : "");
+#endif
+	pcibr_soft->bs_rrb_valid[slot]++;
+    }
+#if PCIBR_RRB_DEBUG
+    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
+	    pcibr_soft->bs_rrb_avail[0],
+	    pcibr_soft->bs_rrb_avail[1]);
+    for (slot = 0; slot < 8; ++slot)
+	printk("\t%d+%d+%d",
+		0xFFF & pcibr_soft->bs_rrb_valid[slot],
+		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+		pcibr_soft->bs_rrb_res[slot]);
+	printk("\n");
+#endif
+}
+
+/*
+ * Device driver interface to flush the write buffers for a specified
+ * device hanging off the bridge.
+ */
+int
+pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    volatile bridgereg_t   *wrb_flush;
+
+    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
+    while (*wrb_flush);
+
+    return(0);
+}
+/*
+ * Device driver interface to request RRBs for a specified device
+ * hanging off a Bridge.  The driver requests the total number of
+ * RRBs it would like for the normal channel (vchan0) and for the
+ * "virtual channel" (vchan1).  The actual number allocated to each
+ * channel is returned.
+ *
+ * If we cannot allocate at least one RRB to a channel that needs
+ * at least one, return -1 (failure).  Otherwise, satisfy the request
+ * as best we can and return 0.
+ */
+int
+pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     desired_vchan0;
+    int                     desired_vchan1;
+    int                     orig_vchan0;
+    int                     orig_vchan1;
+    int                     delta_vchan0;
+    int                     delta_vchan1;
+    int                     final_vchan0;
+    int                     final_vchan1;
+    int                     avail_rrbs;
+    unsigned long           s;
+    int                     error;
+
+    /*
+     * TBD: temper request with admin info about RRB allocation,
+     * and according to demand from other devices on this Bridge.
+     *
+     * One way of doing this would be to allocate two RRBs
+     * for each device on the bus, before any drivers start
+     * asking for extras. This has the weakness that one
+     * driver might not give back an "extra" RRB until after
+     * another driver has already failed to get one that
+     * it wanted.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+
+    /* How many RRBs do we own? */
+    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
+    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+    /* How many RRBs do we want? */
+    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
+    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
+
+    /* How many RRBs are free? */
+    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	+ pcibr_soft->bs_rrb_res[pciio_slot];
+
+    /* Figure desired deltas */
+    delta_vchan0 = desired_vchan0 - orig_vchan0;
+    delta_vchan1 = desired_vchan1 - orig_vchan1;
+
+    /* Trim back deltas to something
+     * that we can actually meet, by
+     * decreasing the ending allocation
+     * for whichever channel wants
+     * more RRBs. If both want the same
+     * number, cut the second channel.
+     * NOTE: do not change the allocation for
+     * a channel that was passed as NULL.
+     */
+    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
+	if (count_vchan0 &&
+	    (!count_vchan1 ||
+	     ((orig_vchan0 + delta_vchan0) >
+	      (orig_vchan1 + delta_vchan1))))
+	    delta_vchan0--;
+	else
+	    delta_vchan1--;
+    }
+
+    /* Figure final RRB allocations
+     */
+    final_vchan0 = orig_vchan0 + delta_vchan0;
+    final_vchan1 = orig_vchan1 + delta_vchan1;
+
+    /* If either channel wants RRBs but our actions
+     * would leave it with none, declare an error,
+     * but DO NOT change any RRB allocations.
+     */
+    if ((desired_vchan0 && !final_vchan0) ||
+	(desired_vchan1 && !final_vchan1)) {
+
+	error = -1;
+
+    } else {
+
+	/* Commit the allocations: free, then alloc.
+	 */
+	if (delta_vchan0 < 0)
+	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
+	if (delta_vchan1 < 0)
+	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
+
+	if (delta_vchan0 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
+	if (delta_vchan1 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
+
+	/* Return final values to caller.
+	 */
+	if (count_vchan0)
+	    *count_vchan0 = final_vchan0;
+	if (count_vchan1)
+	    *count_vchan1 = final_vchan1;
+
+	/* prevent automatic changes to this slot's RRBs
+	 */
+	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
+
+	/* Track the actual allocations, release
+	 * any further reservations, and update the
+	 * number of available RRBs.
+	 */
+
+	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
+	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
+	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	    + pcibr_soft->bs_rrb_res[pciio_slot]
+	    - delta_vchan0
+	    - delta_vchan1;
+	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
+
+#if PCIBR_RRB_DEBUG
+	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
+		pciio_slot, final_vchan0, final_vchan1,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
+	    printk("\t%d+%d+%d",
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
+		    pcibr_soft->bs_rrb_res[pciio_slot]);
+	printk("\n");
+#endif
+
+	error = 0;
+    }
+
+    pcibr_unlock(pcibr_soft, s);
+    return error;
+}
+
+/*
+ * Device driver interface to check the current state
+ * of the RRB allocations.
+ *
+ *   pconn_vhdl is your PCI connection point (specifies which
+ *      PCI bus and which slot).
+ *
+ *   count_vchan0 points to where to return the number of RRBs
+ *      assigned to the primary DMA channel, used by all DMA
+ *      that does not explicitly ask for the alternate virtual
+ *      channel.
+ *
+ *   count_vchan1 points to where to return the number of RRBs
+ *      assigned to the secondary DMA channel, used when
+ *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
+ *
+ *   count_reserved points to where to return the number of RRBs
+ *      that have been automatically reserved for your device at
+ *      startup, but which have not been assigned to a
+ *      channel. RRBs must be assigned to a channel to be used;
+ *      this can be done either with an explicit pcibr_rrb_alloc
+ *      call, or automatically by the infrastructure when a DMA
+ *      translation is constructed. Any call to pcibr_rrb_alloc
+ *      will release any unassigned reserved RRBs back to the
+ *      free pool.
+ *
+ *   count_pool points to where to return the number of RRBs
+ *      that are currently unassigned and unreserved. This
+ *      number can (and will) change as other drivers make calls
+ *      to pcibr_rrb_alloc, or automatically allocate RRBs for
+ *      DMA beyond their initial reservation.
+ *
+ * NULL may be passed for any of the return value pointers
+ * the caller is not interested in.
+ *
+ * The return value is "0" if all went well, or "-1" if
+ * there is a problem. Additionally, if the wrong vertex
+ * is passed in, one of the subsidiary support functions
+ * could panic with a "bad pciio fingerprint."
+ */
+
+int
+pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1,
+		int *count_reserved,
+		int *count_pool)
+{
+    pciio_info_t            pciio_info;
+    pciio_slot_t            pciio_slot;
+    pcibr_soft_t            pcibr_soft;
+    unsigned long           s;
+    int                     error = -1;
+
+    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
+	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
+	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
+
+	s = pcibr_lock(pcibr_soft);
+
+	if (count_vchan0)
+	    *count_vchan0 =
+		pcibr_soft->bs_rrb_valid[pciio_slot];
+
+	if (count_vchan1)
+	    *count_vchan1 =
+		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+	if (count_reserved)
+	    *count_reserved =
+		pcibr_soft->bs_rrb_res[pciio_slot];
+
+	if (count_pool)
+	    *count_pool =
+		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
+
+	error = 0;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return error;
+}
+
+/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
+ * requested for each of the devies.  The evn_odd argument indicates whether
+ * allcoation for the odd or even rrbs is requested and next group of four pairse
+ * are the amount to assign to each device (they should sum to <= 8) and
+ * whether to set the viritual bit for that device (1 indictaes yes, 0 indicates no)
+ * the devices in order are either 0, 2, 4, 6 or 1, 3, 5, 7
+ * if even_odd is even we alloc even rrbs else we allocate odd rrbs
+ * returns 0 if no errors else returns -1
+ */
+
+int
+pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
+		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
+{
+    devfs_handle_t            pcibr_vhdl;
+    pcibr_soft_t            pcibr_soft = NULL;
+    bridge_t               *bridge = NULL;
+
+    uint32_t              rrb_setting = 0;
+    int                     rrb_shift = 7;
+    uint32_t              cur_rrb;
+    int                     dev_rrbs[4];
+    int                     virt[4];
+    int                     i, j;
+    unsigned long           s;
+
+    if (GRAPH_SUCCESS ==
+	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
+	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+	if (pcibr_soft)
+	    bridge = pcibr_soft->bs_base;
+	hwgraph_vertex_unref(pcibr_vhdl);
+    }
+    if (bridge == NULL)
+	bridge = (bridge_t *) xtalk_piotrans_addr
+	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
+
+    even_odd &= 1;
+
+    dev_rrbs[0] = dev_1_rrbs;
+    dev_rrbs[1] = dev_2_rrbs;
+    dev_rrbs[2] = dev_3_rrbs;
+    dev_rrbs[3] = dev_4_rrbs;
+
+    virt[0] = virt1;
+    virt[1] = virt2;
+    virt[2] = virt3;
+    virt[3] = virt4;
+
+    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
+	return -1;
+    }
+    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
+	return -1;
+    }
+    /* walk through rrbs */
+    for (i = 0; i < 4; i++) {
+	if (virt[i]) {
+	    cur_rrb = i | 0xc;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	    dev_rrbs[i] = dev_rrbs[i] - 1;
+	}
+	for (j = 0; j < dev_rrbs[i]; j++) {
+	    cur_rrb = i | 0x8;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	}
+    }
+
+    if (pcibr_soft)
+	s = pcibr_lock(pcibr_soft);
+
+    bridge->b_rrb_map[even_odd].reg = rrb_setting;
+
+    if (pcibr_soft) {
+
+	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
+
+	/* since we've "FIXED" the allocations
+	 * for these slots, we probably can dispense
+	 * with tracking avail/res/valid data, but
+	 * keeping it up to date helps debugging.
+	 */
+
+	pcibr_soft->bs_rrb_avail[even_odd] =
+	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
+
+	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return 0;
+}
+
+/*
+ *    pcibr_rrb_flush: chase down all the RRBs assigned
+ *      to the specified connection point, and flush
+ *      them.
+ */
+void
+pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned long           s;
+    reg_p                   rrbp;
+    unsigned                rrbm;
+    int                     i;
+    int                     rrbn;
+    unsigned                sval;
+    unsigned                mask;
+
+    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
+    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
+    rrbn = pciio_slot & 1;
+    rrbp = &bridge->b_rrb_map[rrbn].reg;
+
+    s = pcibr_lock(pcibr_soft);
+    rrbm = *rrbp;
+    for (i = 0; i < 8; ++i) {
+	if ((rrbm & mask) == sval)
+	    do_pcibr_rrb_flush(bridge, rrbn);
+	rrbm >>= 4;
+	rrbn += 2;
+    }
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Device(x) register management
+ */
+
+/* pcibr_try_set_device: attempt to modify Device(x)
+ * for the specified slot on the specified bridge
+ * as requested in flags, limited to the specified
+ * bits. Returns which BRIDGE bits were in conflict,
+ * or ZERO if everything went OK.
+ *
+ * Caller MUST hold pcibr_lock when calling this function.
+ */
+LOCAL int
+pcibr_try_set_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     unsigned flags,
+		     bridgereg_t mask)
+{
+    bridge_t               *bridge;
+    pcibr_soft_slot_t       slotp;
+    bridgereg_t             old;
+    bridgereg_t             new;
+    bridgereg_t             chg;
+    bridgereg_t             bad;
+    bridgereg_t             badpmu;
+    bridgereg_t             badd32;
+    bridgereg_t             badd64;
+    bridgereg_t             fix;
+    unsigned long           s;
+    bridgereg_t             xmask;
+
+    xmask = mask;
+    if (pcibr_soft->bs_xbridge) {
+    	if (mask == BRIDGE_DEV_PMU_BITS)
+		xmask = XBRIDGE_DEV_PMU_BITS;
+	if (mask == BRIDGE_DEV_D64_BITS)
+		xmask = XBRIDGE_DEV_D64_BITS;
+    }
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    bridge = pcibr_soft->bs_base;
+
+    old = slotp->bss_device;
+
+    /* figure out what the desired
+     * Device(x) bits are based on
+     * the flags specified.
+     */
+
+    new = old;
+
+    /* Currently, we inherit anything that
+     * the new caller has not specified in
+     * one way or another, unless we take
+     * action here to not inherit.
+     *
+     * This is needed for the "swap" stuff,
+     * since it could have been set via
+     * pcibr_endian_set -- altho note that
+     * any explicit PCIBR_BYTE_STREAM or
+     * PCIBR_WORD_VALUES will freely override
+     * the effect of that call (and vice
+     * versa, no protection either way).
+     *
+     * I want to get rid of pcibr_endian_set
+     * in favor of tracking DMA endianness
+     * using the flags specified when DMA
+     * channels are created.
+     */
+
+#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
+#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
+
+    /* Do not use Barrier, Write Gather,
+     * or Prefetch unless asked.
+     * Leave everything else as it
+     * was from the last time.
+     */
+    new = new
+	& ~BRIDGE_DEV_BARRIER
+	& ~BRIDGE_DEV_WRGA_BITS
+	& ~BRIDGE_DEV_PREF
+	;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {
+	new = (new
+            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
+            | BRIDGE_DEV_PREF;          /* prefetch on */
+
+    }
+    if (flags & PCIIO_DMA_CMD) {
+        new = ((new
+            & ~BRIDGE_DEV_PREF)         /* prefetch off */
+            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
+            | BRIDGE_DEV_BARRIER;       /* barrier on */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIIO_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_BYTE_STREAM)
+	new |= (pcibr_soft->bs_xbridge) ? 
+			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
+    if (flags & PCIIO_WORD_VALUES)
+	new &= (pcibr_soft->bs_xbridge) ? 
+			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	new |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	new &= ~BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	new |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	new &= ~BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	new |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	new &= ~BRIDGE_DEV_DEV_SIZE;
+
+    chg = old ^ new;				/* what are we changing, */
+    chg &= xmask;				/* of the interesting bits */
+
+    if (chg) {
+
+	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
+	if (pcibr_soft->bs_xbridge) {
+		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
+	} else {
+		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
+	}
+	bad = badpmu | badd32 | badd64;
+
+	if (bad) {
+
+	    /* some conflicts can be resolved by
+	     * forcing the bit on. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit off,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
+                             BRIDGE_DEV_BARRIER)) ){
+		bad &= ~fix;
+		/* don't change these bits if
+		 * they are already set in "old"
+		 */
+		chg &= ~(fix & old);
+	    }
+	    /* some conflicts can be resolved by
+	     * forcing the bit off. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit on,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
+			     BRIDGE_DEV_PREF)) ) {
+		bad &= ~fix;
+		/* don't change these bits if
+		 * we wanted to turn them on.
+		 */
+		chg &= ~(fix & new);
+	    }
+	    /* conflicts in other bits mean
+	     * we can not establish this DMA
+	     * channel while the other(s) are
+	     * still present.
+	     */
+	    if (bad) {
+		pcibr_unlock(pcibr_soft, s);
+#if (DEBUG && PCIBR_DEV_DEBUG)
+		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
+#endif
+		return bad;
+	    }
+	}
+    }
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr++;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr++;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr++;
+
+    /* the value we want to write is the
+     * original value, with the bits for
+     * our selected changes flipped, and
+     * with any disabled features turned off.
+     */
+    new = old ^ chg;			/* only change what we want to change */
+
+    if (slotp->bss_device == new) {
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
+#endif
+
+    return 0;
+}
+
+void
+pcibr_release_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     bridgereg_t mask)
+{
+    pcibr_soft_slot_t       slotp;
+    unsigned long           s;
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr--;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr--;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr--;
+
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * flush write gather buffer for slot
+ */
+LOCAL void
+pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
+              pciio_slot_t slot)
+{
+    bridge_t               *bridge;
+    unsigned long          s;
+    volatile uint32_t     wrf;
+    s = pcibr_lock(pcibr_soft);
+    bridge = pcibr_soft->bs_base;
+    wrf = bridge->b_wr_req_buf[slot].reg;
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Bridge (pcibr) "Device Driver" entry points
+ */
+
+/*
+ * pcibr_probe_slot: read a config space word
+ * while trapping any errors; reutrn zero if
+ * all went OK, or nonzero if there was an error.
+ * The value read, if any, is passed back
+ * through the valp parameter.
+ */
+LOCAL int
+pcibr_probe_slot(bridge_t *bridge,
+		 cfg_p cfg,
+		 unsigned *valp)
+{
+    int                     rv;
+    bridgereg_t             old_enable, new_enable;
+    int badaddr_val(volatile void *, int, volatile void *);
+
+
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+
+    bridge->b_int_enable = new_enable;
+
+	/*
+	 * The xbridge doesn't clear b_err_int_view unless
+	 * multi-err is cleared...
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+	    }
+
+    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
+	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
+	(void) bridge->b_wid_tflush;	/* flushbus */
+    }
+    rv = badaddr_val((void *) cfg, 4, valp);
+
+	/*
+	 * The xbridge doesn't set master timeout in b_int_status
+	 * here.  Fortunately it's in error_interrupt_view.
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+		rv = 1;		/* unoccupied slot */
+	    }
+
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    return rv;
+}
+
+/*
+ *    pcibr_init: called once during system startup or
+ *      when a loadable driver is loaded.
+ *
+ *      The driver_register function should normally
+ *      be in _reg, not _init.  But the pcibr driver is
+ *      required by devinit before the _reg routines
+ *      are called, so this is an exception.
+ */
+void
+pcibr_init(void)
+{
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_init\n");
+#endif
+
+    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
+			    XBRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
+			    BRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+}
+
+/*
+ * open/close mmap/munmap interface would be used by processes
+ * that plan to map the PCI bridge, and muck around with the
+ * registers. This is dangerous to do, and will be allowed
+ * to a select brand of programs. Typically these are
+ * diagnostics programs, or some user level commands we may
+ * write to do some weird things.
+ * To start with expect them to have root priveleges.
+ * We will ask for more later.
+ */
+/* ARGSUSED */
+int
+pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+    int                     error;
+    devfs_handle_t            vhdl = dev_to_vhdl(dev);
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    ASSERT(pcibr_soft);
+    len = ctob(btoc(len));		/* Make len page aligned */
+    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
+
+    /*
+     * If the offset being mapped corresponds to the flash prom
+     * base, and if the mapping succeeds, and if the user
+     * has requested the protections to be WRITE, enable the
+     * flash prom to be written.
+     *
+     * XXX- deprecate this in favor of using the
+     * real flash driver ...
+     */
+    if (!error &&
+	((off == BRIDGE_EXTERNAL_FLASH) ||
+	 (len > BRIDGE_EXTERNAL_FLASH))) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return error;
+}
+
+/*ARGSUSED */
+int
+pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    /*
+     * If flashprom write was enabled, disable it, as
+     * this is the last unmap.
+     */
+    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return 0;
+}
+
+/* This is special case code used by grio. There are plans to make
+ * this a bit more general in the future, but till then this should
+ * be sufficient.
+ */
+pciio_slot_t
+pcibr_device_slot_get(devfs_handle_t dev_vhdl)
+{
+    char                    devname[MAXDEVNAME];
+    devfs_handle_t            tdev;
+    pciio_info_t            pciio_info;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+
+    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
+
+    /* run back along the canonical path
+     * until we find a PCI connection point.
+     */
+    tdev = hwgraph_connectpt_get(dev_vhdl);
+    while (tdev != GRAPH_VERTEX_NONE) {
+	pciio_info = pciio_info_chk(tdev);
+	if (pciio_info) {
+	    slot = pciio_info_slot_get(pciio_info);
+	    break;
+	}
+	hwgraph_vertex_unref(tdev);
+	tdev = hwgraph_connectpt_get(tdev);
+    }
+    hwgraph_vertex_unref(tdev);
+
+    return slot;
+}
+
+/*==========================================================================
+ *	BRIDGE PCI SLOT RELATED IOCTLs
+ */
+char *pci_space_name[] = {"NONE", 
+			  "ROM",
+			  "IO",
+			  "",
+			  "MEM",
+			  "MEM32",
+			  "MEM64",
+			  "CFG",
+			  "WIN0",
+			  "WIN1",
+			  "WIN2",
+			  "WIN3",
+			  "WIN4",
+			  "WIN5",
+			  "",
+			  "BAD"};
+
+
+#ifdef LATER
+
+void
+pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
+                            int func,
+                            pcibr_slot_func_info_resp_t funcp)
+{
+    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
+    int                          win;
+
+    funcp->resp_f_status = 0;
+
+    if (!pcibr_info) {
+        return;
+    }
+
+    funcp->resp_f_status |= FUNC_IS_VALID;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
+#else
+    sprintf(funcp->resp_f_slot_name, "%x", pcibr_info->f_vertex);
+#endif
+
+    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
+        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
+    }
+
+    funcp->resp_f_bus = pcibr_info->f_bus;
+    funcp->resp_f_slot = pcibr_info->f_slot;
+    funcp->resp_f_func = pcibr_info->f_func;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
+#else
+    sprintf(funcp->resp_f_master_name, "%x", pcibr_info->f_master);
+#endif
+    funcp->resp_f_pops = pcibr_info->f_pops;
+    funcp->resp_f_efunc = pcibr_info->f_efunc;
+    funcp->resp_f_einfo = pcibr_info->f_einfo;
+
+    funcp->resp_f_vendor = pcibr_info->f_vendor;
+    funcp->resp_f_device = pcibr_info->f_device;
+
+    for(win = 0 ; win < 6 ; win++) {
+        funcp->resp_f_window[win].resp_w_base =
+                                  pcibr_info->f_window[win].w_base;
+        funcp->resp_f_window[win].resp_w_size =
+                                  pcibr_info->f_window[win].w_size;
+        sprintf(funcp->resp_f_window[win].resp_w_space,
+                "%s",
+                pci_space_name[pcibr_info->f_window[win].w_space]);
+    }
+
+    funcp->resp_f_rbase = pcibr_info->f_rbase;
+    funcp->resp_f_rsize = pcibr_info->f_rsize;
+
+    for (win = 0 ; win < 4; win++) {
+        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
+    }
+
+    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
+
+}
+
+int
+pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
+                       pciio_slot_t             slot,
+                       pcibr_slot_info_resp_t   respp)
+{
+    pcibr_soft_slot_t            pss;
+    int                          func;
+    bridge_t                    *bridge = pcibr_soft->bs_base;
+    reg_p                        b_respp;
+    pcibr_slot_info_resp_t       slotp;
+    pcibr_slot_func_info_resp_t  funcp;
+
+    slotp = snia_kmem_zalloc(sizeof(*slotp), KM_SLEEP);
+    if (slotp == NULL) {
+        return(ENOMEM);
+    }
+
+    pss = &pcibr_soft->bs_slot[slot];
+    
+    printk("\nPCI INFRASTRUCTURAL INFO FOR SLOT %d\n\n", slot);
+
+    slotp->resp_has_host = pss->has_host;
+    slotp->resp_host_slot = pss->host_slot;
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
+#else
+    sprintf(slotp->resp_slot_conn_name, "%x", pss->slot_conn);
+#endif
+    slotp->resp_slot_status = pss->slot_status;
+    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (is_sys_critical_vertex(pss->slot_conn)) {
+        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
+    }
+
+    slotp->resp_bss_ninfo = pss->bss_ninfo;
+
+    for (func = 0; func < pss->bss_ninfo; func++) {
+        funcp = &(slotp->resp_func[func]);
+        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
+    }
+
+    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
+            pci_space_name[pss->bss_devio.bssd_space]);
+    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
+    slotp->resp_bss_device = pss->bss_device;
+
+    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
+    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
+    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
+
+    slotp->resp_bss_d64_base = pss->bss_d64_base;
+    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
+    slotp->resp_bss_d32_base = pss->bss_d32_base;
+    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
+
+    slotp->resp_bss_ext_ates_active = atomic_read(&pss->bss_ext_ates_active);
+
+    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
+    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
+
+    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
+    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
+                                                      PCIBR_RRB_SLOT_VIRTUAL];
+    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
+
+    if (slot & 1) {
+        b_respp = &bridge->b_odd_resp;
+    } else {
+        b_respp = &bridge->b_even_resp;
+    }
+
+    slotp->resp_b_resp = *b_respp;
+
+    slotp->resp_b_int_device = bridge->b_int_device;
+    slotp->resp_b_int_enable = bridge->b_int_enable;
+    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
+
+    if (COPYOUT(slotp, respp, sizeof(*respp))) {
+        return(EFAULT);
+    }
+
+    snia_kmem_free(slotp, sizeof(*slotp));
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_query
+ *	Return information about the PCI slot maintained by the infrastructure.
+ *	Information is requested in the request structure.
+ *
+ *      Information returned in the response structure:
+ *		Slot hwgraph name
+ *		Vendor/Device info
+ *		Base register info
+ *		Interrupt mapping from device pins to the bridge pins
+ *		Devio register
+ *		Software RRB info
+ *		RRB register info
+ *		Host/Gues info
+ *		PCI Bus #,slot #, function #
+ *		Slot provider hwgraph name
+ *		Provider Functions
+ *		Error handler
+ *		DMA mapping usage counters
+ *		DMA direct translation info
+ *		External SSRAM workaround info
+ */
+int
+pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_info_req_t reqp)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t            slot = reqp->req_slot;
+    pciio_slot_t            tmp_slot;
+    pcibr_slot_info_resp_t  respp = (pcibr_slot_info_resp_t) reqp->req_respp;
+    int                     size = reqp->req_size;
+    int                     error;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(EINVAL);
+    }
+
+    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
+    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
+        return(EINVAL);
+    }
+
+    /* Return information for the requested PCI slot */
+    if (slot != PCIIO_SLOT_NONE) {
+        if (size < sizeof(*respp)) {
+            return(EINVAL);
+        }
+
+        /* Acquire read access to the slot */
+        mrlock(pcibr_soft->bs_slot[slot].slot_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
+
+        /* Release the slot lock */
+        mrunlock(pcibr_soft->bs_slot[slot].slot_lock);
+
+        return(error);
+    }
+
+    /* Return information for all the slots */
+    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
+
+        if (size < sizeof(*respp)) {
+            return(EINVAL);
+        }
+
+        /* Acquire read access to the slot */
+        mrlock(pcibr_soft->bs_slot[tmp_slot].slot_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
+
+        /* Release the slot lock */
+        mrunlock(pcibr_soft->bs_slot[tmp_slot].slot_lock);
+
+        if (error) {
+            return(error);
+        }
+
+        ++respp;
+        size -= sizeof(*respp);
+    }
+
+    return(error);
+}
+#endif	/* LATER */
+
+
+/*ARGSUSED */
+int
+pcibr_ioctl(devfs_handle_t dev,
+	    int cmd,
+	    void *arg,
+	    int flag,
+	    struct cred *cr,
+	    int *rvalp)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
+#ifdef LATER
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+#endif
+    int                     error = 0;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    switch (cmd) {
+#ifdef LATER
+    case GIOCSETBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
+	    break;
+	}
+
+    case GIOCRELEASEBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
+	    break;
+	}
+
+    case PCIBR_SLOT_POWERUP:
+	{
+	    pciio_slot_t	slot;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+	    slot = (pciio_slot_t)(uint64_t)arg;
+	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
+	    break;
+	}
+    case PCIBR_SLOT_SHUTDOWN:
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+	    slot = (pciio_slot_t)(uint64_t)arg;
+	    error = pcibr_slot_powerup(pcibr_vhdl,slot);
+	    break;
+	}
+    case PCIBR_SLOT_QUERY:
+	{
+	    struct pcibr_slot_info_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+            error = pcibr_slot_query(pcibr_vhdl, &req);
+	    break;
+	}
+#endif	/* LATER */
+    default:
+	break;
+
+    }
+
+    return error;
+}
+
+void
+pcibr_freeblock_sub(iopaddr_t *free_basep,
+		    iopaddr_t *free_lastp,
+		    iopaddr_t base,
+		    size_t size)
+{
+    iopaddr_t               free_base = *free_basep;
+    iopaddr_t               free_last = *free_lastp;
+    iopaddr_t               last = base + size - 1;
+
+    if ((last < free_base) || (base > free_last));	/* free block outside arena */
+
+    else if ((base <= free_base) && (last >= free_last))
+	/* free block contains entire arena */
+	*free_basep = *free_lastp = 0;
+
+    else if (base <= free_base)
+	/* free block is head of arena */
+	*free_basep = last + 1;
+
+    else if (last >= free_last)
+	/* free block is tail of arena */
+	*free_lastp = base - 1;
+
+    /*
+     * We are left with two regions: the free area
+     * in the arena "below" the block, and the free
+     * area in the arena "above" the block. Keep
+     * the one that is bigger.
+     */
+
+    else if ((base - free_base) > (free_last - last))
+	*free_lastp = base - 1;		/* keep lower chunk */
+    else
+	*free_basep = last + 1;		/* keep upper chunk */
+}
+
+/* Convert from ssram_bits in control register to number of SSRAM entries */
+#define ATE_NUM_ENTRIES(n) _ate_info[n]
+
+/* Possible choices for number of ATE entries in Bridge's SSRAM */
+LOCAL int               _ate_info[] =
+{
+    0,					/* 0 entries */
+    8 * 1024,				/* 8K entries */
+    16 * 1024,				/* 16K entries */
+    64 * 1024				/* 64K entries */
+};
+
+#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
+#define ATE_PROBE_VALUE 0x0123456789abcdefULL
+
+/*
+ * Determine the size of this bridge's external mapping SSRAM, and set
+ * the control register appropriately to reflect this size, and initialize
+ * the external SSRAM.
+ */
+LOCAL int
+pcibr_init_ext_ate_ram(bridge_t *bridge)
+{
+    int                     largest_working_size = 0;
+    int                     num_entries, entry;
+    int                     i, j;
+    bridgereg_t             old_enable, new_enable;
+    int                     s;
+
+    /* Probe SSRAM to determine its size. */
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+    bridge->b_int_enable = new_enable;
+
+    for (i = 1; i < ATE_NUM_SIZES; i++) {
+	/* Try writing a value */
+	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+
+	/* Guard against wrap */
+	for (j = 1; j < i; j++)
+	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
+
+	/* See if value was written */
+	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+	    largest_working_size = i;
+    }
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * ensure that we write and read without any interruption.
+     * The read following the write is required for the Bridge war
+     */
+
+    s = splhi();
+    bridge->b_wid_control = (bridge->b_wid_control
+	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+    bridge->b_wid_control;		/* inval addr bug war */
+    splx(s);
+
+    num_entries = ATE_NUM_ENTRIES(largest_working_size);
+
+#if PCIBR_ATE_DEBUG
+    if (num_entries)
+	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
+    else
+	printk("bridge at 0x%x: no externa9422l ATE RAM found\n", bridge);
+#endif
+
+    /* Initialize external mapping entries */
+    for (entry = 0; entry < num_entries; entry++)
+	bridge->b_ext_ate_ram[entry] = 0;
+
+    return (num_entries);
+}
+
+/*
+ * Allocate "count" contiguous Bridge Address Translation Entries
+ * on the specified bridge to be used for PCI to XTALK mappings.
+ * Indices in rm map range from 1..num_entries.  Indicies returned
+ * to caller range from 0..num_entries-1.
+ *
+ * Return the start index on success, -1 on failure.
+ */
+LOCAL int
+pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
+{
+    int                     index = 0;
+
+    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
+/* printk("Colin: pcibr_ate_alloc - index %d count %d \n", index, count); */
+
+    if (!index && pcibr_soft->bs_ext_ate_map)
+	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
+
+    /* rmalloc manages resources in the 1..n
+     * range, with 0 being failure.
+     * pcibr_ate_alloc manages resources
+     * in the 0..n-1 range, with -1 being failure.
+     */
+    return index - 1;
+}
+
+LOCAL void
+pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
+/* Who says there's no such thing as a free meal? :-) */
+{
+    /* note the "+1" since rmalloc handles 1..n but
+     * we start counting ATEs at zero.
+     */
+/* printk("Colin: pcibr_ate_free - index %d count %d\n", index, count); */
+
+    rmfree((index < pcibr_soft->bs_int_ate_size)
+	   ? pcibr_soft->bs_int_ate_map
+	   : pcibr_soft->bs_ext_ate_map,
+	   count, index + 1);
+}
+
+LOCAL pcibr_info_t
+pcibr_info_get(devfs_handle_t vhdl)
+{
+    return (pcibr_info_t) pciio_info_get(vhdl);
+}
+
+pcibr_info_t
+pcibr_device_info_new(
+			 pcibr_soft_t pcibr_soft,
+			 pciio_slot_t slot,
+			 pciio_function_t rfunc,
+			 pciio_vendor_id_t vendor,
+			 pciio_device_id_t device)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_function_t        func;
+    int                     ibit;
+
+    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
+
+    NEW(pcibr_info);
+    pciio_device_info_new(&pcibr_info->f_c,
+			  pcibr_soft->bs_vhdl,
+			  slot, rfunc,
+			  vendor, device);
+
+    if (slot != PCIIO_SLOT_NONE) {
+
+	/*
+	 * Currently favored mapping from PCI
+	 * slot number and INTA/B/C/D to Bridge
+	 * PCI Interrupt Bit Number:
+	 *
+	 *     SLOT     A B C D
+	 *      0       0 4 0 4
+	 *      1       1 5 1 5
+	 *      2       2 6 2 6
+	 *      3       3 7 3 7
+	 *      4       4 0 4 0
+	 *      5       5 1 5 1
+	 *      6       6 2 6 2
+	 *      7       7 3 7 3
+	 *
+	 * XXX- allow pcibr_hints to override default
+	 * XXX- allow ADMIN to override pcibr_hints
+	 */
+	for (ibit = 0; ibit < 4; ++ibit)
+	    pcibr_info->f_ibit[ibit] =
+		(slot + 4 * ibit) & 7;
+
+	/*
+	 * Record the info in the sparse func info space.
+	 */
+	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
+	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
+    }
+    return pcibr_info;
+}
+
+void
+pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pcibr_info_t	pcibr_info;
+    pciio_function_t	func;
+    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
+    int			nfunc = slotp->bss_ninfo;
+
+
+    for (func = 0; func < nfunc; func++) {
+	pcibr_info = slotp->bss_infos[func];
+
+	if (!pcibr_info) 
+	    continue;
+
+	slotp->bss_infos[func] = 0;
+	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
+	pciio_device_info_free(&pcibr_info->f_c);
+	DEL(pcibr_info);
+    }
+
+    /* Clear the DEVIO(x) for this slot */
+    slotp->bss_devio.bssd_space = PCIIO_SPACE_NONE;
+    slotp->bss_devio.bssd_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_device  = 0;
+
+    
+    /* Reset the mapping usage counters */
+    slotp->bss_pmu_uctr = 0;
+    slotp->bss_d32_uctr = 0;
+    slotp->bss_d64_uctr = 0;
+
+    /* Clear the Direct translation info */
+    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
+    slotp->bss_d64_flags = 0;
+    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_d32_flags = 0;
+
+    /* Clear out shadow info necessary for the external SSRAM workaround */
+    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
+    slotp->bss_cmd_pointer = 0;
+    slotp->bss_cmd_shadow = 0;
+
+}
+
+/* 
+ * PCI_ADDR_SPACE_LIMITS_LOAD
+ *	Gets the current values of 
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
+    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
+    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
+    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
+    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
+    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
+    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
+    printf("+++++++++++++++++++++++\n"			\
+	   "IO base 0x%x last 0x%x\n"			\
+	   "SWIN base 0x%x last 0x%x\n"			\
+	   "MEM base 0x%x last 0x%x\n"			\
+	   "+++++++++++++++++++++++\n",			\
+	   pcibr_soft->bs_spinfo.pci_io_base,		\
+	   pcibr_soft->bs_spinfo.pci_io_last,		\
+	   pcibr_soft->bs_spinfo.pci_swin_base,		\
+	   pcibr_soft->bs_spinfo.pci_swin_last,		\
+	   pcibr_soft->bs_spinfo.pci_mem_base,		\
+	   pcibr_soft->bs_spinfo.pci_mem_last);
+
+/*
+ * pcibr_slot_info_init
+ *	Probe for this slot and see if it is populated.
+ *	If it is populated initialize the generic PCI infrastructural
+ * 	information associated with this particular PCI device.
+ */
+int
+pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
+		     pciio_slot_t 	slot)
+{
+    pcibr_soft_t	    pcibr_soft;
+    pcibr_info_h	    pcibr_infoh;
+    pcibr_info_t	    pcibr_info;
+    bridge_t		   *bridge;
+    cfg_p                   cfgw;
+    unsigned                idword;
+    unsigned                pfail;
+    unsigned                idwords[8];
+    pciio_vendor_id_t       vendor;
+    pciio_device_id_t       device;
+    unsigned                htype;
+    cfg_p                   wptr;
+    int                     win;
+    pciio_space_t           space;
+    iopaddr_t		    pci_io_fb,	pci_io_fl;
+    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
+    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
+    int			    nfunc;
+    pciio_function_t	    rfunc;
+    int			    func;
+    devfs_handle_t	    conn_vhdl;
+    pcibr_soft_slot_t	    slotp;
+    
+    /* Get the basic software information required to proceed */
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft)
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+    if (!PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
+     * is done by the host slot then we are done.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);    
+    }
+
+    /* Check for a slot with any system critical functions */
+    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    /* Load the current values of allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+    
+    /* Try to read the device-id/vendor-id from the config space */
+    cfgw = bridge->b_type0_cfg_dev[slot].l;
+
+    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
+	return(ENODEV);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+    slotp->slot_status |= SLOT_POWER_UP;
+
+    vendor = 0xFFFF & idword;
+    /* If the vendor id is not valid then the slot is not populated
+     * and we are done.
+     */
+    if (vendor == 0xFFFF) 
+	return(ENODEV);			
+    
+    device = 0xFFFF & (idword >> 16);
+    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+
+    nfunc = 1;
+    rfunc = PCIIO_FUNC_NONE;
+    pfail = 0;
+
+    /* NOTE: if a card claims to be multifunction
+     * but only responds to config space 0, treat
+     * it as a unifunction card.
+     */
+
+    if (htype & 0x80) {		/* MULTIFUNCTION */
+	for (func = 1; func < 8; ++func) {
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    vendor = 0xFFFF & idwords[func];
+	    if (vendor == 0xFFFF) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    nfunc = func + 1;
+	    rfunc = 0;
+	}
+	cfgw = bridge->b_type0_cfg_dev[slot].l;
+    }
+    NEWA(pcibr_infoh, nfunc);
+    
+    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
+    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+    for (func = 0; func < nfunc; ++func) {
+	unsigned                cmd_reg;
+	
+	if (func) {
+	    if (pfail & (1 << func))
+		continue;
+	    
+	    idword = idwords[func];
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    
+	    device = 0xFFFF & (idword >> 16);
+	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+	    rfunc = func;
+	}
+	htype &= 0x7f;
+	if (htype != 0x00) {
+	    printk(KERN_WARNING  "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
+		    pcibr_soft->bs_name, slot, func, htype);
+	    continue;
+	}
+#if DEBUG && ATTACH_DEBUG
+	printk(KERN_NOTICE   
+		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
+		pcibr_soft->bs_name, slot, func, vendor, device);
+#endif	
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, rfunc, vendor, device);
+	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
+	if (func == 0)
+	    slotp->slot_conn = conn_vhdl;
+
+#ifdef LITTLE_ENDIAN
+	cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4];
+#else
+	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
+#endif
+	
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) {
+	    iopaddr_t               base, mask, code;
+	    size_t                  size;
+
+	    /*
+	     * GET THE BASE & SIZE OF THIS WINDOW:
+	     *
+	     * The low two or four bits of the BASE register
+	     * determines which address space we are in; the
+	     * rest is a base address. BASE registers
+	     * determine windows that are power-of-two sized
+	     * and naturally aligned, so we can get the size
+	     * of a window by writing all-ones to the
+	     * register, reading it back, and seeing which
+	     * bits are used for decode; the least
+	     * significant nonzero bit is also the size of
+	     * the window.
+	     *
+	     * WARNING: someone may already have allocated
+	     * some PCI space to this window, and in fact
+	     * PIO may be in process at this very moment
+	     * from another processor (or even from this
+	     * one, if we get interrupted)! So, if the BASE
+	     * already has a nonzero address, be generous
+	     * and use the LSBit of that address as the
+	     * size; this could overstate the window size.
+	     * Usually, when one card is set up, all are set
+	     * up; so, since we don't bitch about
+	     * overlapping windows, we are ok.
+	     *
+	     * UNFORTUNATELY, some cards do not clear their
+	     * BASE registers on reset. I have two heuristics
+	     * that can detect such cards: first, if the
+	     * decode enable is turned off for the space
+	     * that the window uses, we can disregard the
+	     * initial value. second, if the address is
+	     * outside the range that we use, we can disregard
+	     * it as well.
+	     *
+	     * This is looking very PCI generic. Except for
+	     * knowing how many slots and where their config
+	     * spaces are, this window loop and the next one
+	     * could probably be shared with other PCI host
+	     * adapters. It would be interesting to see if
+	     * this could be pushed up into pciio, when we
+	     * start supporting more PCI providers.
+	     */
+#ifdef LITTLE_ENDIAN
+	    base = wptr[((win*4)^4)/4];
+#else
+	    base = wptr[win];
+#endif
+
+	    if (base & PCI_BA_IO_SPACE) {
+		/* BASE is in I/O space. */
+		space = PCIIO_SPACE_IO;
+		mask = -4;
+		code = base & 3;
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		}
+	    } else {
+		/* BASE is in MEM space. */
+		space = PCIIO_SPACE_MEM;
+		mask = -16;
+		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		} else if (base & 0xC0000000) {
+		    base = 0;	/* outside permissable range */
+		} else if ((code == PCI_BA_MEM_64BIT) &&
+#ifdef LITTLE_ENDIAN
+			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
+#else 
+			   (wptr[win + 1] != 0)) {
+#endif /* LITTLE_ENDIAN */
+		    base = 0;	/* outside permissable range */
+		}
+	    }
+
+	    if (base != 0) {	/* estimate size */
+		size = base & -base;
+	    } else {		/* calculate size */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
+		size = wptr[((win*4)^4)/4];	/* get stored bits */
+#else 
+		wptr[win] = ~0;	/* turn on all bits */
+		size = wptr[win];	/* get stored bits */
+#endif /* LITTLE_ENDIAN */
+		size &= mask;	/* keep addr */
+		size &= -size;	/* keep lsbit */
+		if (size == 0)
+		    continue;
+	    }	
+
+	    pcibr_info->f_window[win].w_space = space;
+	    pcibr_info->f_window[win].w_base = base;
+	    pcibr_info->f_window[win].w_size = size;
+
+	    /*
+	     * If this window already has PCI space
+	     * allocated for it, "subtract" that space from
+	     * our running freeblocks. Don't worry about
+	     * overlaps in existing allocated windows; we
+	     * may be overstating their sizes anyway.
+	     */
+
+	    if (base && size) {
+		if (space == PCIIO_SPACE_IO) {
+		    pcibr_freeblock_sub(&pci_io_fb,
+					&pci_io_fl,
+					base, size);
+		} else {
+		    pcibr_freeblock_sub(&pci_lo_fb,
+					&pci_lo_fl,
+					base, size);
+		    pcibr_freeblock_sub(&pci_hi_fb,
+					&pci_hi_fl,
+					base, size);
+		}	
+	    }
+#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
+	    /*
+	     * IOC3 BASE_ADDR* BUG WORKAROUND
+	     *
+	     
+	     * If we write to BASE1 on the IOC3, the
+	     * data in BASE0 is replaced. The
+	     * original workaround was to remember
+	     * the value of BASE0 and restore it
+	     * when we ran off the end of the BASE
+	     * registers; however, a later
+	     * workaround was added (I think it was
+	     * rev 1.44) to avoid setting up
+	     * anything but BASE0, with the comment
+	     * that writing all ones to BASE1 set
+	     * the enable-parity-error test feature
+	     * in IOC3's SCR bit 14.
+	     *
+	     * So, unless we defer doing any PCI
+	     * space allocation until drivers
+	     * attach, and set up a way for drivers
+	     * (the IOC3 in paricular) to tell us
+	     * generically to keep our hands off
+	     * BASE registers, we gotta "know" about
+	     * the IOC3 here.
+	     *
+	     * Too bad the PCI folks didn't reserve the
+	     * all-zero value for 'no BASE here' (it is a
+	     * valid code for an uninitialized BASE in
+	     * 32-bit PCI memory space).
+	     */
+	    
+	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
+		(device == IOC3_DEVICE_ID_NUM))
+		break;
+#endif
+	    if (code == PCI_BA_MEM_64BIT) {
+		win++;		/* skip upper half */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
+#else 
+		wptr[win] = 0;	/* which must be zero */
+#endif /* LITTLE_ENDIAN */
+	    }
+	}				/* next win */
+    }				/* next func */
+
+    /* Store back the values for allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}					
+
+/*
+ * pcibr_slot_info_free
+ *	Remove all the PCI infrastructural information associated
+ * 	with a particular PCI device.
+ */
+int
+pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
+                     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    int			nfunc;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+
+    pcibr_device_info_free(pcibr_vhdl, slot);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    DELA(pcibr_infoh,nfunc);
+    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
+
+    return(0);
+}
+
+int as_debug = 0;
+/*
+ * pcibr_slot_addr_space_init
+ *	Reserve chunks of PCI address space as required by 
+ * 	the base registers in the card.
+ */
+int
+pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    iopaddr_t		pci_io_fb, pci_io_fl;
+    iopaddr_t		pci_lo_fb, pci_lo_fl;
+    iopaddr_t		pci_hi_fb, pci_hi_fl;
+    size_t              align;
+    iopaddr_t           mask;
+    int		    	nbars;
+    int		       	nfunc;
+    int			func;
+    int			win;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Get the current values for the allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+
+    if (as_debug)
+#ifdef LATER
+    PCI_ADDR_SPACE_LIMITS_PRINT();
+#endif
+    /* allocate address space,
+     * for windows that have not been
+     * previously assigned.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);
+    }
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    if (nfunc < 1)
+	return(EINVAL);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    if (!pcibr_infoh)
+	return(EINVAL);
+
+    /*
+     * Try to make the DevIO windows not
+     * overlap by pushing the "io" and "hi"
+     * allocation areas up to the next one
+     * or two megabyte bound. This also
+     * keeps them from being zero.
+     *
+     * DO NOT do this with "pci_lo" since
+     * the entire "lo" area is only a
+     * megabyte, total ...
+     */
+    align = (slot < 2) ? 0x200000 : 0x100000;
+    mask = -align;
+    pci_io_fb = (pci_io_fb + align - 1) & mask;
+    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
+
+    for (func = 0; func < nfunc; ++func) {
+	cfg_p                   cfgw;
+	cfg_p                   wptr;
+	pciio_space_t           space;
+	iopaddr_t               base;
+	size_t                  size;
+	cfg_p                   pci_cfg_cmd_reg_p;
+	unsigned                pci_cfg_cmd_reg;
+	unsigned                pci_cfg_cmd_reg_add = 0;
+
+	pcibr_info = pcibr_infoh[func];
+
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+	
+	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	nbars = PCI_CFG_BASE_ADDRS;
+
+	for (win = 0; win < nbars; ++win) {
+
+	    space = pcibr_info->f_window[win].w_space;
+	    base = pcibr_info->f_window[win].w_base;
+	    size = pcibr_info->f_window[win].w_size;
+	    
+	    if (size < 1)
+		continue;
+
+	    if (base >= size) {
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
+			slot, func, win, space, base, base + size - 1);
+#endif
+		continue;		/* already allocated */
+	    }
+	    align = size;		/* ie. 0x00001000 */
+	    if (align < _PAGESZ)
+		align = _PAGESZ;	/* ie. 0x00004000 */
+	    mask = -align;		/* ie. 0xFFFFC000 */
+
+	    switch (space) {
+	    case PCIIO_SPACE_IO:
+		base = (pci_io_fb + align - 1) & mask;
+		if ((base + size) > pci_io_fl) {
+		    base = 0;
+		    break;
+		}
+		pci_io_fb = base + size;
+		break;
+		
+	    case PCIIO_SPACE_MEM:
+#ifdef LITTLE_ENDIAN
+		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
+#else
+		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
+#endif  /* LITTLE_ENDIAN */
+		    PCI_BA_MEM_1MEG) {
+		    /* allocate from 20-bit PCI space */
+		    base = (pci_lo_fb + align - 1) & mask;
+		    if ((base + size) > pci_lo_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_lo_fb = base + size;
+		} else {
+		    /* allocate from 32-bit or 64-bit PCI space */
+		    base = (pci_hi_fb + align - 1) & mask;
+		    if ((base + size) > pci_hi_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_hi_fb = base + size;
+		}
+		break;
+		
+	    default:
+		base = 0;
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d window %d had bad space code %d\n",
+			slot, win, space);
+#endif
+	    }
+	    pcibr_info->f_window[win].w_base = base;
+#ifdef LITTLE_ENDIAN
+	    wptr[((win*4)^4)/4] = base;
+#if DEBUG && PCI_DEBUG
+		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
+#endif
+#else
+	    wptr[win] = base;
+#endif  /* LITTLE_ENDIAN */
+
+#if DEBUG && PCI_DEBUG
+	    if (base >= size)
+		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
+			slot, func, win, space, base, base + size - 1);
+	    else
+		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
+			slot, func, win, size, space);
+#endif
+	}				/* next base */
+
+	/*
+	 * Allocate space for the EXPANSION ROM
+	 * NOTE: DO NOT DO THIS ON AN IOC3,
+	 * as it blows the system away.
+	 */
+	base = size = 0;
+	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
+	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
+
+	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
+#ifdef LITTLE_ENDIAN
+	    wptr[1] = 0xFFFFF000;
+	    mask = wptr[1];
+#else
+	    *wptr = 0xFFFFF000;
+	    mask = *wptr;
+#endif  /* LITTLE_ENDIAN */
+	    if (mask & 0xFFFFF000) {
+		size = mask & -mask;
+		align = size;
+		if (align < _PAGESZ)
+		    align = _PAGESZ;
+		mask = -align;
+		base = (pci_hi_fb + align - 1) & mask;
+		if ((base + size) > pci_hi_fl)
+		    base = size = 0;
+		else {
+		    pci_hi_fb = base + size;
+#ifdef LITTLE_ENDIAN
+		    wptr[1] = base;
+#else
+		    *wptr = base;
+#endif  /* LITTLE_ENDIAN */
+#if DEBUG && PCI_DEBUG
+		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
+			    pcibr_soft->bs_name, slot,
+			    base, base + size - 1);
+#endif
+		}
+	    }
+	}
+	pcibr_info->f_rbase = base;
+	pcibr_info->f_rsize = size;
+	
+	/*
+	 * if necessary, update the board's
+	 * command register to enable decoding
+	 * in the windows we added.
+	 *
+	 * There are some bits we always want to
+	 * be sure are set.
+	 */
+	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
+
+	/*
+	 * The Adaptec 1160 FC Controller WAR #767995:
+	 * The part incorrectly ignores the upper 32 bits of a 64 bit
+	 * address when decoding references to it's registers so to
+	 * keep it from responding to a bus cycle that it shouldn't
+	 * we only use I/O space to get at it's registers.  Don't
+	 * enable memory space accesses on that PCI device.
+	 */
+	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
+	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
+
+	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
+	    (pcibr_info->f_device != FCADP_DEVID))
+	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
+
+	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
+
+	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
+	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
+#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
+	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
+	    fast_back_to_back_enable = 0;
+#endif
+	pci_cfg_cmd_reg &= 0xFFFF;
+	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
+	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
+	
+    }				/* next func */
+
+    /* Now that we have allocated new chunks of PCI address spaces to this
+     * card we need to update the bookkeeping values which indicate
+     * the current PCI address space allocations.
+     */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}
+
+/*
+ * pcibr_slot_device_init
+ * 	Setup the device register in the bridge for this PCI slot.
+ */
+int
+pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
+		       pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    bridgereg_t		 devreg;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * Adjustments to Device(x)
+     * and init of bss_device shadow
+     */
+    devreg = bridge->b_device[slot].reg;
+    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
+    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
+#ifdef LITTLE_ENDIAN
+    devreg |= BRIDGE_DEV_DEV_SWAP;
+#endif
+    pcibr_soft->bs_slot[slot].bss_device = devreg;
+    bridge->b_device[slot].reg = devreg;
+
+#if DEBUG && PCI_DEBUG
+	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
+#endif
+
+#if DEBUG && PCI_DEBUG
+    printk("pcibr: PCI space allocation done.\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_guest_info_init
+ *	Setup the host/guest relations for a PCI slot.
+ */
+int
+pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    pcibr_soft_slot_t	slotp;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    /* create info and verticies for guest slots;
+     * for compatibilitiy macros, create info
+     * for even unpopulated slots (but do not
+     * build verticies for them).
+     */
+    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
+	NEWA(pcibr_infoh, 1);
+	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
+	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
+	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+
+	if (pcibr_soft->bs_slot[slot].has_host) {
+	    slotp->slot_conn = pciio_device_info_register
+		(pcibr_vhdl, &pcibr_info->f_c);
+	}
+    }
+
+    /* generate host/guest relations
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	int  host = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
+
+	hwgraph_edge_add(slotp->slot_conn,
+			 host_slotp->slot_conn,
+			 EDGE_LBL_HOST);
+
+	/* XXX- only gives us one guest edge per
+	 * host. If/when we have a host with more than
+	 * one guest, we will need to figure out how
+	 * the host finds all its guests, and sorts
+	 * out which one is which.
+	 */
+	hwgraph_edge_add(host_slotp->slot_conn,
+			 slotp->slot_conn,
+			 EDGE_LBL_GUEST);
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_initial_rrb_alloc
+ *	Allocate a default number of rrbs for this slot on 
+ * 	the two channels.  This is dictated by the rrb allocation
+ * 	strategy routine defined per platform.
+ */
+
+int
+pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    int                 c0, c1;
+    int			r;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* How may RRBs are on this slot?
+     */
+    c0 = do_pcibr_rrb_count_valid(bridge, slot);
+    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
+
+#if PCIBR_RRB_DEBUG
+    printk("pcibr_attach: slot %d started with %d+%d\n", slot, c0, c1);
+#endif
+
+    /* Do we really need any?
+     */
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    pcibr_info = pcibr_infoh[0];
+    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
+	!pcibr_soft->bs_slot[slot].has_host) {
+	if (c0 > 0)
+	    do_pcibr_rrb_free(bridge, slot, c0);
+	if (c1 > 0)
+	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
+	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
+	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
+	return(ENODEV);
+    }
+
+    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
+    pcibr_soft->bs_rrb_valid[slot] = c0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
+
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    r = 3 - (c0 + c1);
+
+    if (r > 0) {
+	pcibr_soft->bs_rrb_res[slot] = r;
+	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_call_device_attach
+ *	This calls the associated driver attach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    async_attach_t	aa = NULL;
+    int			func;
+    devfs_handle_t	xconn_vhdl,conn_vhdl;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+        return(EPERM);
+    }
+    
+    xconn_vhdl = pcibr_soft->bs_conn;
+    aa = async_attach_get_info(xconn_vhdl);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+#ifdef LATER
+	/*
+	 * Activate if and when we support cdl.
+	 */
+	if (aa)
+	    async_attach_add_info(conn_vhdl, aa);
+#endif	/* LATER */
+
+	error_func = pciio_device_attach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+        error = error_slot;
+
+    }				/* next func */
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_call_device_detach
+ *	This calls the associated driver detach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    int			func;
+    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    if (pcibr_soft->bs_slot[slot].has_host)
+        return(EPERM);
+
+    /* Make sure that we do not detach a system critical function vertex */
+    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+	error_func = pciio_device_detach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+	error = error_slot;
+
+    }				/* next func */
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        if (conn_vhdl != GRAPH_VERTEX_NONE) 
+            pcibr_device_unregister(conn_vhdl);
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_detach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific freeing that needs to be done.
+ */
+int
+pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags)
+{
+    int		  error;
+    
+    /* Call the device detach function */
+    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
+    return (error);
+
+}
+
+/*
+ * pcibr_is_slot_sys_critical
+ *      Check slot for any functions that are system critical.
+ *      Return 1 if any are system critical or 0 otherwise.
+ *
+ *      This function will always return 0 when called by 
+ *      pcibr_attach() because the system critical vertices 
+ *      have not yet been set in the hwgraph.
+ */
+int
+pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
+                      pciio_slot_t slot)
+{
+    pcibr_soft_t        pcibr_soft;
+    pcibr_info_h        pcibr_infoh;
+    pcibr_info_t        pcibr_info;
+    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
+    int                 nfunc;
+    int                 func;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+        return(0);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+        pcibr_info = pcibr_infoh[func];
+        if (!pcibr_info)
+            continue;
+
+        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+            continue;
+
+        conn_vhdl = pcibr_info->f_vertex;
+        if (is_sys_critical_vertex(conn_vhdl)) { 
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+            printk(KERN_WARNING  "%v is a system critical device vertex\n", conn_vhdl);
+#else
+            printk(KERN_WARNING  "%p is a system critical device vertex\n", (void *)conn_vhdl);
+#endif
+            return(1); 
+        }
+
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_device_unregister
+ *	This frees up any hardware resources reserved for this PCI device
+ * 	and removes any PCI infrastructural information setup for it.
+ *	This is usually used at the time of shutting down of the PCI card.
+ */
+int
+pcibr_device_unregister(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t	 pciio_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    int			 error_call;
+    int			 error = 0;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Clear all the hardware xtalk resources for this device */
+    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
+
+    /* Flush all the rrbs */
+    pcibr_rrb_flush(pconn_vhdl);
+
+    /* Free the rrbs allocated to this slot */
+    error_call = do_pcibr_rrb_free(bridge, slot, 
+		                   pcibr_soft->bs_rrb_valid[slot] +
+		                   pcibr_soft->bs_rrb_valid[slot + 
+                                   PCIBR_RRB_SLOT_VIRTUAL]);
+
+    if (error_call)
+        error = ERANGE;
+
+    pcibr_soft->bs_rrb_valid[slot] = 0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0;
+    pcibr_soft->bs_rrb_res[slot] = 0;
+
+    /* Flush the write buffers !! */
+    error_call = pcibr_wrb_flush(pconn_vhdl);
+
+    if (error_call)
+        error = error_call;
+
+    /* Clear the information specific to the slot */
+    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
+
+    if (error_call)
+        error = error_call;
+
+    return(error);
+    
+}
+
+/* 
+ * build a convenience link path in the
+ * form of ".../<iobrick>/bus/<busnum>"
+ * 
+ * returns 1 on success, 0 otherwise
+ *
+ * depends on hwgraph separator == '/'
+ */
+int
+pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
+{
+        char dst[MAXDEVNAME];
+	char *dp = dst;
+        char *cp, *xp;
+        int widgetnum;
+        char pcibus[8];
+	devfs_handle_t nvtx, svtx;
+	int rv;
+
+#if DEBUG
+	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
+		slot, f_c);
+	{
+		int pos;
+		char dname[256];
+		pos = devfs_generate_path(f_c, dname, 256);
+		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
+	}
+#endif
+
+	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
+		return 0;
+
+	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
+
+	/* find the widget number */
+	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
+	if (xp == NULL)
+		return 0;
+	widgetnum = atoi(xp+7);
+	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
+		return 0;
+
+	/* remove "/pci/direct" from path */
+	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
+	if (cp == NULL)
+		return 0;
+	*cp = (char)NULL;
+
+	/* get the vertex for the widget */
+	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
+		return 0;
+
+	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
+
+	/* dst example now == /hw/module/001c02/Pbrick */
+
+	/* get the bus number */
+        strcat(dst, "/bus");
+        sprintf(pcibus, "%d", p_busnum[widgetnum]);
+
+	/* link to bus to widget */
+	rv = hwgraph_path_add(NULL, dp, &nvtx);
+	if (GRAPH_SUCCESS == rv)
+		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
+
+	return (rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ *    pcibr_attach: called every time the crosstalk
+ *      infrastructure is asked to initialize a widget
+ *      that matches the part number we handed to the
+ *      registration routine above.
+ */
+/*ARGSUSED */
+int
+pcibr_attach(devfs_handle_t xconn_vhdl)
+{
+    /* REFERENCED */
+    graph_error_t           rc;
+    devfs_handle_t            pcibr_vhdl;
+    devfs_handle_t            ctlr_vhdl;
+    bridge_t               *bridge = NULL;
+    bridgereg_t             id;
+    int                     rev;
+    pcibr_soft_t            pcibr_soft;
+    pcibr_info_t            pcibr_info;
+    xwidget_info_t          info;
+    xtalk_intr_t            xtalk_intr;
+    device_desc_t           dev_desc = (device_desc_t)0;
+    int                     slot;
+    int                     ibit;
+    devfs_handle_t            noslot_conn;
+    char                    devnm[MAXDEVNAME], *s;
+    pcibr_hints_t           pcibr_hints;
+    bridgereg_t             b_int_enable;
+    unsigned                rrb_fixed = 0;
+
+    iopaddr_t               pci_io_fb, pci_io_fl;
+    iopaddr_t               pci_lo_fb, pci_lo_fl;
+    iopaddr_t               pci_hi_fb, pci_hi_fl;
+
+    int                     spl_level;
+#ifdef LATER
+    char		    *nicinfo = (char *)0;
+#endif
+
+#if PCI_FBBE
+    int                     fast_back_to_back_enable;
+#endif
+    l1sc_t		    *scp;
+    nasid_t		    nasid;
+
+    async_attach_t          aa = NULL;
+
+    aa = async_attach_get_info(xconn_vhdl);
+
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
+    {
+	int pos;
+	char dname[256];
+	pos = devfs_generate_path(xconn_vhdl, dname, 256);
+	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
+    }
+#endif
+
+    /* Setup the PRB for the bridge in CONVEYOR BELT
+     * mode. PRBs are setup in default FIRE-AND-FORGET
+     * mode during the initialization.
+     */
+    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
+
+    bridge = (bridge_t *)
+	xtalk_piotrans_addr(xconn_vhdl, NULL,
+			    0, sizeof(bridge_t), 0);
+
+#ifndef MEDUSA_HACK
+    if ((bridge->b_wid_stat & BRIDGE_STAT_PCI_GIO_N) == 0)
+	return -1;			/* someone else handles GIO bridges. */
+#endif
+
+    if (XWIDGET_PART_REV_NUM(bridge->b_wid_id) == XBRIDGE_PART_REV_A)
+	NeedXbridgeSwap = 1;
+
+    /*
+     * Create the vertex for the PCI bus, which we
+     * will also use to hold the pcibr_soft and
+     * which will be the "master" vertex for all the
+     * pciio connection points we will hang off it.
+     * This needs to happen before we call nic_bridge_vertex_info
+     * as we are some of the *_vmc functions need access to the edges.
+     *
+     * Opening this vertex will provide access to
+     * the Bridge registers themselves.
+     */
+    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
+    ASSERT(rc == GRAPH_SUCCESS);
+
+    ctlr_vhdl = NULL;
+    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
+                0, DEVFS_FL_AUTO_DEVNUM,
+                0, 0,
+                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+                &pcibr_fops, NULL);
+
+    ASSERT(ctlr_vhdl != NULL);
+
+    /*
+     * decode the nic, and hang its stuff off our
+     * connection point where other drivers can get
+     * at it.
+     */
+#ifdef LATER
+    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
+#endif
+
+    /*
+     * Get the hint structure; if some NIC callback
+     * marked this vertex as "hands-off" then we
+     * just return here, before doing anything else.
+     */
+    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
+
+    if (pcibr_hints && pcibr_hints->ph_hands_off)
+	return -1;			/* generic operations disabled */
+
+    id = bridge->b_wid_id;
+    rev = XWIDGET_PART_REV_NUM(id);
+
+    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
+
+    /*
+     * allocate soft state structure, fill in some
+     * fields, and hook it up to our vertex.
+     */
+    NEW(pcibr_soft);
+    BZERO(pcibr_soft, sizeof *pcibr_soft);
+    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
+
+    pcibr_soft->bs_conn = xconn_vhdl;
+    pcibr_soft->bs_vhdl = pcibr_vhdl;
+    pcibr_soft->bs_base = bridge;
+    pcibr_soft->bs_rev_num = rev;
+    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
+    if (is_xbridge(bridge)) {
+	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 1;
+    } else {
+	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 0;
+    }
+
+    nasid = NASID_GET(bridge);
+    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
+    pcibr_soft->bs_l1sc = scp;
+    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
+    pcibr_soft->bsi_err_intr = 0;
+
+    /* Bridges up through REV C
+     * are unable to set the direct
+     * byteswappers to BYTE_STREAM.
+     */
+    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
+	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
+	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
+    }
+#if PCIBR_SOFT_LIST
+    {
+	pcibr_list_p            self;
+
+	NEW(self);
+	self->bl_soft = pcibr_soft;
+	self->bl_vhdl = pcibr_vhdl;
+	self->bl_next = pcibr_list;
+	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
+    }
+#endif
+
+    /*
+     * get the name of this bridge vertex and keep the info. Use this
+     * only where it is really needed now: like error interrupts.
+     */
+    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
+    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    strcpy(pcibr_soft->bs_name, s);
+
+#if SHOW_REVS || DEBUG
+#if !DEBUG
+    if (kdebug)
+#endif
+	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
+		is_xbridge(bridge) ? "X" : "",
+		(rev == BRIDGE_PART_REV_A) ? "A" :
+		(rev == BRIDGE_PART_REV_B) ? "B" :
+		(rev == BRIDGE_PART_REV_C) ? "C" :
+		(rev == BRIDGE_PART_REV_D) ? "D" :
+		(rev == XBRIDGE_PART_REV_A) ? "A" :
+		(rev == XBRIDGE_PART_REV_B) ? "B" :
+		"unknown",
+		rev, pcibr_soft->bs_name);
+#endif
+
+    info = xwidget_info_get(xconn_vhdl);
+    pcibr_soft->bs_xid = xwidget_info_id_get(info);
+    pcibr_soft->bs_master = xwidget_info_master_get(info);
+    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
+
+    /*
+     * Init bridge lock.
+     */
+    spin_lock_init(&pcibr_soft->bs_lock);
+
+    /*
+     * If we have one, process the hints structure.
+     */
+    if (pcibr_hints) {
+	rrb_fixed = pcibr_hints->ph_rrb_fixed;
+
+	pcibr_soft->bs_rrb_fixed = rrb_fixed;
+
+	if (pcibr_hints->ph_intr_bits)
+	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
+
+	for (slot = 0; slot < 8; ++slot) {
+	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
+
+	    if (hslot < 0) {
+		pcibr_soft->bs_slot[slot].host_slot = slot;
+	    } else {
+		pcibr_soft->bs_slot[slot].has_host = 1;
+		pcibr_soft->bs_slot[slot].host_slot = hslot;
+	    }
+	}
+    }
+    /*
+     * set up initial values for state fields
+     */
+    for (slot = 0; slot < 8; ++slot) {
+	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
+	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
+    }
+
+    for (ibit = 0; ibit < 8; ++ibit) {
+	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
+							&(bridge->b_int_status);
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
+    }
+
+    /*
+     * Initialize various Bridge registers.
+     */
+
+    /*
+     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
+     * to zero to avoid dropping stores. (#475347)
+     */
+    if (rev < BRIDGE_PART_REV_D)
+	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
+
+    /*
+     * Clear all pending interrupts.
+     */
+    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
+
+    /*
+     * Until otherwise set up,
+     * assume all interrupts are
+     * from slot 7.
+     */
+    bridge->b_int_device = (uint32_t) 0xffffffff;
+
+    {
+	bridgereg_t             dirmap;
+	paddr_t                 paddr;
+	iopaddr_t               xbase;
+	xwidgetnum_t            xport;
+	iopaddr_t               offset;
+	int                     num_entries = 0;
+	int                     entry;
+	cnodeid_t		cnodeid;
+	nasid_t			nasid;
+
+	/* Set the Bridge's 32-bit PCI to XTalk
+	 * Direct Map register to the most useful
+	 * value we can determine.  Note that we
+	 * must use a single xid for all of:
+	 *      direct-mapped 32-bit DMA accesses
+	 *      direct-mapped 64-bit DMA accesses
+	 *      DMA accesses through the PMU
+	 *      interrupts
+	 * This is the only way to guarantee that
+	 * completion interrupts will reach a CPU
+	 * after all DMA data has reached memory.
+	 * (Of course, there may be a few special
+	 * drivers/controlers that explicitly manage
+	 * this ordering problem.)
+	 */
+
+	cnodeid = 0;  /* default node id */
+	/*
+	 * Determine the base address node id to be used for all 32-bit
+	 * Direct Mapping I/O. The default is node 0, but this can be changed
+	 * via a DEVICE_ADMIN directive and the PCIBUS_DMATRANS_NODE
+	 * attribute in the irix.sm config file. A device driver can obtain
+	 * this node value via a call to pcibr_get_dmatrans_node().
+	 */
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+	paddr = NODE_OFFSET(nasid) + 0;
+
+	/* currently, we just assume that if we ask
+	 * for a DMA mapping to "zero" the XIO
+	 * host will transmute this into a request
+	 * for the lowest hunk of memory.
+	 */
+	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
+				    paddr, _PAGESZ, 0);
+
+	if (xbase != XIO_NOWHERE) {
+	    if (XIO_PACKED(xbase)) {
+		xport = XIO_PORT(xbase);
+		xbase = XIO_ADDR(xbase);
+	    } else
+		xport = pcibr_soft->bs_mxid;
+
+	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
+	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
+
+	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
+
+	    if (xbase)
+		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
+	    else if (offset >= (512 << 20))
+		dirmap |= BRIDGE_DIRMAP_ADD512;
+
+	    bridge->b_dir_map = dirmap;
+	}
+	/*
+	 * Set bridge's idea of page size according to the system's
+	 * idea of "IO page size".  TBD: The idea of IO page size
+	 * should really go away.
+	 */
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	spl_level = splhi();
+#if IOPGSIZE == 4096
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#elif IOPGSIZE == 16384
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#else
+	<<<Unable to deal with IOPGSIZE >>>;
+#endif
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(spl_level);
+
+	/* Initialize internal mapping entries */
+	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++)
+	    bridge->b_int_ate_ram[entry].wr = 0;
+
+	/*
+	 * Determine if there's external mapping SSRAM on this
+	 * bridge.  Set up Bridge control register appropriately,
+	 * inititlize SSRAM, and set software up to manage RAM
+	 * entries as an allocatable resource.
+	 *
+	 * Currently, we just use the rm* routines to manage ATE
+	 * allocation.  We should probably replace this with a
+	 * Best Fit allocator.
+	 *
+	 * For now, if we have external SSRAM, avoid using
+	 * the internal ssram: we can't turn PREFETCH on
+	 * when we use the internal SSRAM; and besides,
+	 * this also guarantees that no allocation will
+	 * straddle the internal/external line, so we
+	 * can increment ATE write addresses rather than
+	 * recomparing against BRIDGE_INTERNAL_ATES every
+	 * time.
+	 */
+	if (is_xbridge(bridge))
+		num_entries = 0;
+	else
+		num_entries = pcibr_init_ext_ate_ram(bridge);
+
+	/* we always have 128 ATEs (512 for Xbridge) inside the chip
+	 * even if disabled for debugging.
+	 */
+	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
+	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
+#endif
+
+	if (num_entries > pcibr_soft->bs_int_ate_size) {
+#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
+	    printk("pcibr_attach: disabling internal ATEs.\n");
+	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
+#endif
+	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
+	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
+			   num_entries - pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
+		    num_entries - pcibr_soft->bs_int_ate_size);
+#endif
+	}
+    }
+
+    {
+	bridgereg_t             dirmap;
+	iopaddr_t               xbase;
+
+	/*
+	 * now figure the *real* xtalk base address
+	 * that dirmap sends us to.
+	 */
+	dirmap = bridge->b_dir_map;
+	if (dirmap & BRIDGE_DIRMAP_OFF)
+	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
+			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
+	else if (dirmap & BRIDGE_DIRMAP_ADD512)
+	    xbase = 512 << 20;
+	else
+	    xbase = 0;
+
+	pcibr_soft->bs_dir_xbase = xbase;
+
+	/* it is entirely possible that we may, at this
+	 * point, have our dirmap pointing somewhere
+	 * other than our "master" port.
+	 */
+	pcibr_soft->bs_dir_xport =
+	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
+    }
+
+    /* pcibr sources an error interrupt;
+     * figure out where to send it.
+     *
+     * If any interrupts are enabled in bridge,
+     * then the prom set us up and our interrupt
+     * has already been reconnected in mlreset
+     * above.
+     *
+     * Need to set the D_INTR_ISERR flag
+     * in the dev_desc used for allocating the
+     * error interrupt, so our interrupt will
+     * be properly routed and prioritized.
+     *
+     * If our crosstalk provider wants to
+     * fix widget error interrupts to specific
+     * destinations, D_INTR_ISERR is how it
+     * knows to do this.
+     */
+
+    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
+    ASSERT(xtalk_intr != NULL);
+
+    pcibr_soft->bsi_err_intr = xtalk_intr;
+
+    /*
+     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
+     * in order to work around some addressing limitations.  In order
+     * for that fire wall to work properly, we need to make sure we
+     * start from a known clean state.
+     */
+    pcibr_clearwidint(bridge);
+
+    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge);
+
+    /*
+     * now we can start handling error interrupts;
+     * enable all of them.
+     * NOTE: some PCI ints may already be enabled.
+     */
+    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
+
+
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
+
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * Depending on the rev of bridge, disable certain features.
+     * Easiest way seems to be to force the PCIBR_NOwhatever
+     * flag to be on for all DMA calls, which overrides any
+     * PCIBR_whatever flag or even the setting of whatever
+     * from the PCIIO_DMA_class flags (or even from the other
+     * PCIBR flags, since NO overrides YES).
+     */
+    pcibr_soft->bs_dma_flags = 0;
+
+    /* PREFETCH:
+     * Always completely disabled for REV.A;
+     * at "pcibr_prefetch_enable_rev", anyone
+     * asking for PCIIO_PREFETCH gets it.
+     * Between these two points, you have to ask
+     * for PCIBR_PREFETCH, which promises that
+     * your driver knows about known Bridge WARs.
+     */
+    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
+	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
+    else if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
+
+    /* WRITE_GATHER:
+     * Disabled up to but not including the
+     * rev number in pcibr_wg_enable_rev. There
+     * is no "WAR range" as with prefetch.
+     */
+    if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
+
+    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
+    pciio_provider_startup(pcibr_vhdl);
+
+    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
+    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
+
+    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
+    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
+
+    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
+    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
+
+
+    PCI_ADDR_SPACE_LIMITS_STORE();
+
+    /* build "no-slot" connection point
+     */
+    pcibr_info = pcibr_device_info_new
+	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
+	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+    noslot_conn = pciio_device_info_register
+	(pcibr_vhdl, &pcibr_info->f_c);
+
+    /* Remember the no slot connection point info for tearing it
+     * down during detach.
+     */
+    pcibr_soft->bs_noslot_conn = noslot_conn;
+    pcibr_soft->bs_noslot_info = pcibr_info;
+#if PCI_FBBE
+    fast_back_to_back_enable = 1;
+#endif
+
+#if PCI_FBBE
+    if (fast_back_to_back_enable) {
+	/*
+	 * All devices on the bus are capable of fast back to back, so
+	 * we need to set the fast back to back bit in all devices on
+	 * the bus that are capable of doing such accesses.
+	 */
+    }
+#endif
+
+#ifdef LATER
+    /* If the bridge has been reset then there is no need to reset
+     * the individual PCI slots.
+     */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Reset all the slots */
+	(void)pcibr_slot_reset(pcibr_vhdl, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)
+	/* Find out what is out there */
+	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up the address space for this slot in the pci land */
+	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup the device register */
+	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
+
+#ifndef __ia64
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up convenience links */
+	if (is_xbridge(bridge))
+		if (pcibr_soft->bs_slot[slot].bss_ninfo > 0) /* if occupied */
+			pcibr_bus_cnvlink(pcibr_info->f_vertex, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup host/guest relations */
+	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Initial RRB management */
+	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
+
+    /* driver attach routines should be called out from generic linux code */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Call the device attach */
+	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
+
+    /*
+     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
+     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
+     */
+    if (pcibr_soft->bs_moduleid > 0) {
+	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
+	case 'p':		/* Pbrick */
+		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		break;
+	case 'i':		/* Ibrick */
+	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
+		if (pcibr_soft->bs_xid == 0xe) {
+			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		}
+		else {
+		    	/* allocate one RRB for the serial port */
+			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
+		}
+		break;
+	} /* switch */
+    }
+
+#ifdef LATER
+    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
+	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+#if PCIBR_RRB_DEBUG
+	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
+
+	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
+		pcibr_vhdl,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+
+	for (slot = 0; slot < 8; ++slot)
+	    printf("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+
+	printf("\n");
+#endif
+    }
+#else
+	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
+#endif
+
+    if (aa)
+	    async_attach_add_info(noslot_conn, aa);
+
+    pciio_device_attach(noslot_conn, 0);
+
+
+    /* 
+     * Tear down pointer to async attach info -- async threads for
+     * bridge's descendants may be running but the bridge's work is done.
+     */
+    if (aa)
+	    async_attach_del_info(xconn_vhdl);
+
+    return 0;
+}
+/*
+ * pcibr_detach:
+ *	Detach the bridge device from the hwgraph after cleaning out all the 
+ *	underlying vertices.
+ */
+int
+pcibr_detach(devfs_handle_t xconn)
+{
+    pciio_slot_t	slot;
+    devfs_handle_t	pcibr_vhdl;
+    pcibr_soft_t	pcibr_soft;
+    bridge_t		*bridge;
+
+    /* Get the bridge vertex from its xtalk connection point */
+    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
+	return(1);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Disable the interrupts from the bridge */
+    bridge->b_int_enable = 0;
+
+    /* Detach all the PCI devices talking to this bridge */
+    for(slot = 0; slot < 8; slot++) {
+#ifdef DEBUG
+	printk("pcibr_device_detach called for %p/%d\n",
+		pcibr_vhdl,slot);
+#endif
+	pcibr_slot_detach(pcibr_vhdl, slot, 0);
+    }
+
+    /* Unregister the no-slot connection point */
+    pciio_device_info_unregister(pcibr_vhdl,
+				 &(pcibr_soft->bs_noslot_info->f_c));
+
+    spin_lock_destroy(&pcibr_soft->bs_lock);
+    kfree(pcibr_soft->bs_name);
+    
+    /* Error handler gets unregistered when the widget info is 
+     * cleaned 
+     */
+    /* Free the soft ATE maps */
+    if (pcibr_soft->bs_int_ate_map)
+	rmfreemap(pcibr_soft->bs_int_ate_map);
+    if (pcibr_soft->bs_ext_ate_map)
+	rmfreemap(pcibr_soft->bs_ext_ate_map);
+
+    /* Disconnect the error interrupt and free the xtalk resources 
+     * associated with it.
+     */
+    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
+    xtalk_intr_free(pcibr_soft->bsi_err_intr);
+
+    /* Clear the software state maintained by the bridge driver for this
+     * bridge.
+     */
+    DEL(pcibr_soft);
+    /* Remove the Bridge revision labelled info */
+    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
+    /* Remove the character device associated with this bridge */
+    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
+    /* Remove the PCI bridge vertex */
+    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
+
+    return(0);
+}
+
+int
+pcibr_asic_rev(devfs_handle_t pconn_vhdl)
+{
+    devfs_handle_t            pcibr_vhdl;
+    arbitrary_info_t        ainfo;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
+	return -1;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
+	return -1;
+
+    return (int) ainfo;
+}
+
+int
+pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t  slot;
+    slot = pciio_info_slot_get(pciio_info);
+    pcibr_device_write_gather_flush(pcibr_soft, slot);
+    return 0;
+}
+
+/* =====================================================================
+ *    PIO MANAGEMENT
+ */
+
+LOCAL iopaddr_t
+pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
+		      pciio_slot_t slot,
+		      pciio_space_t space,
+		      iopaddr_t pci_addr,
+		      size_t req_size,
+		      unsigned flags)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    unsigned                bar;	/* which BASE reg on device is decoding */
+    iopaddr_t               xio_addr = XIO_NOWHERE;
+
+    pciio_space_t           wspace;	/* which space device is decoding */
+    iopaddr_t               wbase;	/* base of device decode on PCI */
+    size_t                  wsize;	/* size of device decode on PCI */
+
+    int                     try;	/* DevIO(x) window scanning order control */
+    int                     win;	/* which DevIO(x) window is being used */
+    pciio_space_t           mspace;	/* target space for devio(x) register */
+    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
+    size_t                  msize;	/* size of devio(x) mapped area on PCI */
+    size_t                  mmask;	/* addr bits stored in Device(x) */
+
+    unsigned long           s;
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	slot = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
+    }
+    if (space == PCIIO_SPACE_NONE)
+	goto done;
+
+    if (space == PCIIO_SPACE_CFG) {
+	/*
+	 * Usually, the first mapping
+	 * established to a PCI device
+	 * is to its config space.
+	 *
+	 * In any case, we definitely
+	 * do NOT need to worry about
+	 * PCI BASE registers, and
+	 * MUST NOT attempt to point
+	 * the DevIO(x) window at
+	 * this access ...
+	 */
+	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
+	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
+	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
+
+	goto done;
+    }
+    if (space == PCIIO_SPACE_ROM) {
+	/* PIO to the Expansion Rom.
+	 * Driver is responsible for
+	 * enabling and disabling
+	 * decodes properly.
+	 */
+	wbase = pcibr_info->f_rbase;
+	wsize = pcibr_info->f_rsize;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	pci_addr += wbase;
+	space = PCIIO_SPACE_MEM;
+    }
+    /*
+     * reduce window mappings to raw
+     * space mappings (maybe allocating
+     * windows), and try for DevIO(x)
+     * usage (setting it if it is available).
+     */
+    bar = space - PCIIO_SPACE_WIN0;
+    if (bar < 6) {
+	wspace = pcibr_info->f_window[bar].w_space;
+	if (wspace == PCIIO_SPACE_NONE)
+	    goto done;
+
+	/* get PCI base and size */
+	wbase = pcibr_info->f_window[bar].w_base;
+	wsize = pcibr_info->f_window[bar].w_size;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	/* shift from window relative to
+	 * decoded space relative.
+	 */
+	pci_addr += wbase;
+	space = wspace;
+    } else
+	bar = -1;
+
+    /* Scan all the DevIO(x) windows twice looking for one
+     * that can satisfy our request. The first time through,
+     * only look at assigned windows; the second time, also
+     * look at PCIIO_SPACE_NONE windows. Arrange the order
+     * so we always look at our own window first.
+     *
+     * We will not attempt to satisfy a single request
+     * by concatinating multiple windows.
+     */
+    for (try = 0; try < 16; ++try) {
+	bridgereg_t             devreg;
+	unsigned                offset;
+
+	win = (try + slot) % 8;
+
+	/* If this DevIO(x) mapping area can provide
+	 * a mapping to this address, use it.
+	 */
+	msize = (win < 2) ? 0x200000 : 0x100000;
+	mmask = -msize;
+	if (space != PCIIO_SPACE_IO)
+	    mmask &= 0x3FFFFFFF;
+
+	offset = pci_addr & (msize - 1);
+
+	/* If this window can't possibly handle that request,
+	 * go on to the next window.
+	 */
+	if (((pci_addr & (msize - 1)) + req_size) > msize)
+	    continue;
+
+	devreg = pcibr_soft->bs_slot[win].bss_device;
+
+	/* Is this window "nailed down"?
+	 * If not, maybe we can use it.
+	 * (only check this the second time through)
+	 */
+	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
+	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
+
+	    /* If this is the primary DevIO(x) window
+	     * for some other device, skip it.
+	     */
+	    if ((win != slot) &&
+		(PCIIO_VENDOR_ID_NONE !=
+		 pcibr_soft->bs_slot[win].bss_vendor_id))
+		continue;
+
+	    /* It's a free window, and we fit in it.
+	     * Set up Device(win) to our taste.
+	     */
+	    mbase = pci_addr & mmask;
+
+	    /* check that we would really get from
+	     * here to there.
+	     */
+	    if ((mbase | offset) != pci_addr)
+		continue;
+
+	    devreg &= ~BRIDGE_DEV_OFF_MASK;
+	    if (space != PCIIO_SPACE_IO)
+		devreg |= BRIDGE_DEV_DEV_IO_MEM;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
+	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	    /* default is WORD_VALUES.
+	     * if you specify both,
+	     * operation is undefined.
+	     */
+	    if (flags & PCIIO_BYTE_STREAM)
+		devreg |= BRIDGE_DEV_DEV_SWAP;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_SWAP;
+
+	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
+		bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+
+#if DEBUG && PCI_DEBUG
+		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
+#endif
+	    }
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
+	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
+		    __FUNCTION__, __LINE__, space, space_desc,
+		    pci_addr, pci_addr + req_size - 1,
+		    slot, win, devreg);
+#endif
+
+	    goto done;
+	}				/* endif DevIO(x) not pointed */
+	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
+
+	/* Now check for request incompat with DevIO(x)
+	 */
+	if ((mspace != space) ||
+	    (pci_addr < mbase) ||
+	    ((pci_addr + req_size) > (mbase + msize)) ||
+	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
+	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
+	    continue;
+
+	/* DevIO(x) window is pointed at PCI space
+	 * that includes our target. Calculate the
+	 * final XIO address, release the lock and
+	 * return.
+	 */
+	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
+		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
+#endif
+	goto done;
+    }
+
+    switch (space) {
+	/*
+	 * Accesses to device decode
+	 * areas that do a not fit
+	 * within the DevIO(x) space are
+	 * modified to be accesses via
+	 * the direct mapping areas.
+	 *
+	 * If necessary, drivers can
+	 * explicitly ask for mappings
+	 * into these address spaces,
+	 * but this should never be needed.
+	 */
+    case PCIIO_SPACE_MEM:		/* "mem space" */
+    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM32_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
+	break;
+
+    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM64_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
+	break;
+
+    case PCIIO_SPACE_IO:		/* "i/o space" */
+	/* Bridge Hardware Bug WAR #482741:
+	 * The 4G area that maps directly from
+	 * XIO space to PCI I/O space is busted
+	 * until Bridge Rev D.
+	 */
+	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
+	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
+	     BRIDGE_PCI_IO_LIMIT))
+	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
+	break;
+    }
+
+    /* Check that "Direct PIO" byteswapping matches,
+     * try to change it if it does not.
+     */
+    if (xio_addr != XIO_NOWHERE) {
+	unsigned                bst;	/* nonzero to set bytestream */
+	unsigned               *bfp;	/* addr of record of how swapper is set */
+	unsigned                swb;	/* which control bit to mung */
+	unsigned                bfo;	/* current swapper setting */
+	unsigned                bfn;	/* desired swapper setting */
+
+	bfp = ((space == PCIIO_SPACE_IO)
+	       ? (&pcibr_soft->bs_pio_end_io)
+	       : (&pcibr_soft->bs_pio_end_mem));
+
+	bfo = *bfp;
+
+	bst = flags & PCIIO_BYTE_STREAM;
+
+	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
+
+	if (bfn == bfo) {		/* we already match. */
+	    ;
+	} else if (bfo != 0) {		/* we have a conflict. */
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
+		    space, 
+		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	    xio_addr = XIO_NOWHERE;
+	} else {			/* OK to make the change. */
+	    bridgereg_t             octl, nctl;
+
+	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
+	    octl = bridge->b_wid_control;
+	    nctl = bst ? octl | swb : octl & ~swb;
+
+	    if (octl != nctl)		/* make the change if any */
+		bridge->b_wid_control = nctl;
+
+	    *bfp = bfn;			/* record the assignment */
+
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
+		    space, 
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	}
+    }
+  done:
+    pcibr_unlock(pcibr_soft, s);
+    return xio_addr;
+}
+
+/*ARGSUSED6 */
+pcibr_piomap_t
+pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   pciio_space_t space,
+		   iopaddr_t pci_addr,
+		   size_t req_size,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    pcibr_piomap_t         *mapptr;
+    pcibr_piomap_t          maplist;
+    pcibr_piomap_t          pcibr_piomap;
+    iopaddr_t               xio_addr;
+    xtalk_piomap_t          xtalk_piomap;
+    unsigned long           s;
+
+    /* Make sure that the req sizes are non-zero */
+    if ((req_size < 1) || (req_size_max < 1))
+	return NULL;
+
+    /*
+     * Code to translate slot/space/addr
+     * into xio_addr is common between
+     * this routine and pcibr_piotrans_addr.
+     */
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    /* Check the piomap list to see if there is already an allocated
+     * piomap entry but not in use. If so use that one. Otherwise
+     * allocate a new piomap entry and add it to the piomap list
+     */
+    mapptr = &(pcibr_info->f_piomap);
+
+    s = pcibr_lock(pcibr_soft);
+    for (pcibr_piomap = *mapptr;
+	 pcibr_piomap != NULL;
+	 pcibr_piomap = pcibr_piomap->bp_next) {
+	if (pcibr_piomap->bp_mapsz == 0)
+	    break;
+    }
+
+    if (pcibr_piomap)
+	mapptr = NULL;
+    else {
+	pcibr_unlock(pcibr_soft, s);
+	NEW(pcibr_piomap);
+    }
+
+    pcibr_piomap->bp_dev = pconn_vhdl;
+    pcibr_piomap->bp_slot = pciio_slot;
+    pcibr_piomap->bp_flags = flags;
+    pcibr_piomap->bp_space = space;
+    pcibr_piomap->bp_pciaddr = pci_addr;
+    pcibr_piomap->bp_mapsz = req_size;
+    pcibr_piomap->bp_soft = pcibr_soft;
+    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
+
+    if (mapptr) {
+	s = pcibr_lock(pcibr_soft);
+	maplist = *mapptr;
+	pcibr_piomap->bp_next = maplist;
+	*mapptr = pcibr_piomap;
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+
+    if (pcibr_piomap) {
+	xtalk_piomap =
+	    xtalk_piomap_alloc(xconn_vhdl, 0,
+			       xio_addr,
+			       req_size, req_size_max,
+			       flags & PIOMAP_FLAGS);
+	if (xtalk_piomap) {
+	    pcibr_piomap->bp_xtalk_addr = xio_addr;
+	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
+	} else {
+	    pcibr_piomap->bp_mapsz = 0;
+	    pcibr_piomap = 0;
+	}
+    }
+    return pcibr_piomap;
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
+    pcibr_piomap->bp_xtalk_pio = 0;
+    pcibr_piomap->bp_mapsz = 0;
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
+		  iopaddr_t pci_addr,
+		  size_t req_size)
+{
+    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
+			     pcibr_piomap->bp_xtalk_addr +
+			     pci_addr - pcibr_piomap->bp_pciaddr,
+			     req_size);
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    pciio_space_t space,
+		    iopaddr_t pci_addr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    iopaddr_t               xio_addr;
+
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
+}
+
+/*
+ * PIO Space allocation and management.
+ *      Allocate and Manage the PCI PIO space (mem and io space)
+ *      This routine is pretty simplistic at this time, and
+ *      does pretty trivial management of allocation and freeing..
+ *      The current scheme is prone for fragmentation..
+ *      Change the scheme to use bitmaps.
+ */
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
+		     device_desc_t dev_desc,
+		     pciio_space_t space,
+		     size_t req_size,
+		     size_t alignment)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+
+    iopaddr_t              *pciaddr, *pcilast;
+    iopaddr_t               start_addr;
+    size_t                  align_mask;
+
+    /*
+     * Check for proper alignment
+     */
+    ASSERT(alignment >= NBPP);
+    ASSERT((alignment & (alignment - 1)) == 0);
+
+    align_mask = alignment - 1;
+    s = pcibr_lock(pcibr_soft);
+
+    /*
+     * First look if a previously allocated chunk exists.
+     */
+    if ((piosp = pcibr_info->f_piospace)) {
+	/*
+	 * Look through the list for a right sized free chunk.
+	 */
+	do {
+	    if (piosp->free &&
+		(piosp->space == space) &&
+		(piosp->count >= req_size) &&
+		!(piosp->start & align_mask)) {
+		piosp->free = 0;
+		pcibr_unlock(pcibr_soft, s);
+		return piosp->start;
+	    }
+	    piosp = piosp->next;
+	} while (piosp);
+    }
+    ASSERT(!piosp);
+
+    switch (space) {
+    case PCIIO_SPACE_IO:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
+	break;
+    case PCIIO_SPACE_MEM:
+    case PCIIO_SPACE_MEM32:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
+	break;
+    default:
+	ASSERT(0);
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+
+    start_addr = *pciaddr;
+
+    /*
+     * Align start_addr.
+     */
+    if (start_addr & align_mask)
+	start_addr = (start_addr + align_mask) & ~align_mask;
+
+    if ((start_addr + req_size) > *pcilast) {
+	/*
+	 * If too big a request, reject it.
+	 */
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    *pciaddr = (start_addr + req_size);
+
+    NEW(piosp);
+    piosp->free = 0;
+    piosp->space = space;
+    piosp->start = start_addr;
+    piosp->count = req_size;
+    piosp->next = pcibr_info->f_piospace;
+    pcibr_info->f_piospace = piosp;
+
+    pcibr_unlock(pcibr_soft, s);
+    return start_addr;
+}
+
+/*ARGSUSED */
+void
+pcibr_piospace_free(devfs_handle_t pconn_vhdl,
+		    pciio_space_t space,
+		    iopaddr_t pciaddr,
+		    size_t req_size)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+    char                    name[1024];
+
+    /*
+     * Look through the bridge data structures for the pciio_piospace_t
+     * structure corresponding to  'pciaddr'
+     */
+    s = pcibr_lock(pcibr_soft);
+    piosp = pcibr_info->f_piospace;
+    while (piosp) {
+	/*
+	 * Piospace free can only be for the complete
+	 * chunk and not parts of it..
+	 */
+	if (piosp->start == pciaddr) {
+	    if (piosp->count == req_size)
+		break;
+	    /*
+	     * Improper size passed for freeing..
+	     * Print a message and break;
+	     */
+	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
+	    printk(KERN_WARNING  "pcibr_piospace_free: error");
+	    printk(KERN_WARNING  "Device %s freeing size (0x%lx) different than allocated (0x%lx)",
+					name, req_size, piosp->count);
+	    printk(KERN_WARNING  "Freeing 0x%lx instead", piosp->count);
+	    break;
+	}
+	piosp = piosp->next;
+    }
+
+    if (!piosp) {
+	printk(KERN_WARNING  
+		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
+		pciaddr, req_size);
+	pcibr_unlock(pcibr_soft, s);
+	return;
+    }
+    piosp->free = 1;
+    pcibr_unlock(pcibr_soft, s);
+    return;
+}
+
+/* =====================================================================
+ *    DMA MANAGEMENT
+ *
+ *      The Bridge ASIC provides three methods of doing
+ *      DMA: via a "direct map" register available in
+ *      32-bit PCI space (which selects a contiguous 2G
+ *      address space on some other widget), via
+ *      "direct" addressing via 64-bit PCI space (all
+ *      destination information comes from the PCI
+ *      address, including transfer attributes), and via
+ *      a "mapped" region that allows a bunch of
+ *      different small mappings to be established with
+ *      the PMU.
+ *
+ *      For efficiency, we most prefer to use the 32-bit
+ *      direct mapping facility, since it requires no
+ *      resource allocations. The advantage of using the
+ *      PMU over the 64-bit direct is that single-cycle
+ *      PCI addressing can be used; the advantage of
+ *      using 64-bit direct over PMU addressing is that
+ *      we do not have to allocate entries in the PMU.
+ */
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Direct Map attribute bits.
+ */
+LOCAL iopaddr_t
+pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
+{
+    iopaddr_t               attributes = 0;
+
+    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
+#ifdef LATER
+    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
+#endif
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
+	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
+	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    /* the swap bit is in the address attributes for xbridge */
+    if (pcibr_soft->bs_xbridge) {
+    	if (flags & PCIIO_BYTE_STREAM)
+        	attributes |= PCI64_ATTR_SWAP;
+    	if (flags & PCIIO_WORD_VALUES)
+        	attributes &= ~PCI64_ATTR_SWAP;
+    }
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= PCI64_ATTR_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~PCI64_ATTR_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= PCI64_ATTR_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~PCI64_ATTR_PREC;
+
+    if (flags & PCIBR_VCHAN1)
+	attributes |= PCI64_ATTR_VIRTUAL;
+    if (flags & PCIBR_VCHAN0)
+	attributes &= ~PCI64_ATTR_VIRTUAL;
+
+    return (attributes);
+}
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Address Translation Entry attribute bits.
+ */
+LOCAL bridge_ate_t
+pcibr_flags_to_ate(unsigned flags)
+{
+    bridge_ate_t            attributes;
+
+    /* default if nothing specified:
+     * NOBARRIER
+     * NOPREFETCH
+     * NOPRECISE
+     * COHERENT
+     * Plus the valid bit
+     */
+    attributes = ATE_CO | ATE_V;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~ATE_BAR;		/* no barrier */
+	attributes |= ATE_PREF;		/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= ATE_BAR;		/* barrier bit on */
+	attributes &= ~ATE_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= ATE_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~ATE_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= ATE_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~ATE_PREC;
+
+    return (attributes);
+}
+
+/*ARGSUSED */
+pcibr_dmamap_t
+pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            slot;
+    xwidgetnum_t            xio_port;
+
+    xtalk_dmamap_t          xtalk_dmamap;
+    pcibr_dmamap_t          pcibr_dmamap;
+    int                     ate_count;
+    int                     ate_index;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+#ifdef IRIX
+    NEWf(pcibr_dmamap, flags);
+#else
+    /*
+     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
+     * can be called within an interrupt thread.
+     */
+    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
+#endif
+
+    if (!pcibr_dmamap)
+	return 0;
+
+    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
+				      flags & DMAMAP_FLAGS);
+    if (!xtalk_dmamap) {
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
+#endif
+#ifdef IRIX
+	DEL(pcibr_dmamap);
+#else
+	free_pciio_dmamap(pcibr_dmamap);
+#endif
+	return 0;
+    }
+    xio_port = pcibr_soft->bs_mxid;
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_dmamap->bd_dev = pconn_vhdl;
+    pcibr_dmamap->bd_slot = slot;
+    pcibr_dmamap->bd_soft = pcibr_soft;
+    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
+    pcibr_dmamap->bd_max_size = req_size_max;
+    pcibr_dmamap->bd_xio_port = xio_port;
+
+    if (flags & PCIIO_DMA_A64) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    iopaddr_t               pci_addr;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+	    /* Device is capable of A64 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     */
+
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_pci_addr = pci_addr;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct64\n");
+#endif
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct64\n");
+#endif
+	flags &= ~PCIIO_DMA_A64;
+    }
+    if (flags & PCIIO_FIXED) {
+	/* warning: mappings may fail later,
+	 * if direct32 can't get to the address.
+	 */
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
+	    /* User desires DIRECT A32 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     * Mapping calls may fail if target
+	     * is outside the direct32 range.
+	     */
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct32\n");
+#endif
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
+	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct32\n");
+#endif
+	/* If the user demands FIXED and we can't
+	 * give it to him, fail.
+	 */
+	xtalk_dmamap_free(xtalk_dmamap);
+#ifdef IRIX
+	DEL(pcibr_dmamap);
+#else
+	free_pciio_dmamap(pcibr_dmamap);
+#endif
+	return 0;
+    }
+    /*
+     * Allocate Address Translation Entries from the mapping RAM.
+     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
+     * the maximum number of ATEs is based on the worst-case
+     * scenario, where the requested target is in the
+     * last byte of an ATE; thus, mapping IOPGSIZE+2
+     * does end up requiring three ATEs.
+     */
+    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
+	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
+		     +req_size_max	/* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    } else {	/* assume requested target is page aligned */
+	ate_count = IOPG(req_size_max   /* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    }
+
+    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
+
+    if (ate_index != -1) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
+	    bridge_ate_t            ate_proto;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using PMU\n");
+#endif
+
+	    ate_proto = pcibr_flags_to_ate(flags);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_pci_addr =
+		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
+	    /*
+	     * for xbridge the byte-swap bit == bit 29 of PCI address
+	     */
+	    if (pcibr_soft->bs_xbridge) {
+		    if (flags & PCIIO_BYTE_STREAM)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    /*
+		     * If swap was set in bss_device in pcibr_endian_set()
+		     * we need to change the address bit.
+		     */
+		    if (pcibr_soft->bs_slot[slot].bss_device & 
+							BRIDGE_DEV_SWAP_PMU)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    if (flags & PCIIO_WORD_VALUES)
+			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
+	    }
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
+	    pcibr_dmamap->bd_ate_index = ate_index;
+	    pcibr_dmamap->bd_ate_count = ate_count;
+	    pcibr_dmamap->bd_ate_proto = ate_proto;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (ate_proto & ATE_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
+				!pcibr_soft->bs_xbridge) {
+		bridge_t               *bridge = pcibr_soft->bs_base;
+		volatile unsigned      *cmd_regp;
+		unsigned                cmd_reg;
+		unsigned long           s;
+
+		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
+
+		s = pcibr_lock(pcibr_soft);
+		cmd_regp = &(bridge->
+			     b_type0_cfg_dev[slot].
+			     l[PCI_CFG_COMMAND / 4]);
+		cmd_reg = *cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
+		pcibr_unlock(pcibr_soft, s);
+	    }
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use PMU\n");
+#endif
+	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
+    }
+    /* total failure: sorry, you just can't
+     * get from here to there that way.
+     */
+#if PCIBR_ATE_DEBUG
+    printk("pcibr_dmamap_alloc: complete failure.\n");
+#endif
+    xtalk_dmamap_free(xtalk_dmamap);
+#ifdef IRIX
+    DEL(pcibr_dmamap);
+#else
+    free_pciio_dmamap(pcibr_dmamap);
+#endif
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
+
+    unsigned                flags = pcibr_dmamap->bd_flags;
+
+    /* Make sure that bss_ext_ates_active
+     * is properly kept up to date.
+     */
+
+    if (PCIBR_DMAMAP_BUSY & flags)
+	if (PCIBR_DMAMAP_SSRAM & flags)
+	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
+
+    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
+
+    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
+    }
+    if (pcibr_dmamap->bd_ate_count) {
+	pcibr_ate_free(pcibr_dmamap->bd_soft,
+		       pcibr_dmamap->bd_ate_index,
+		       pcibr_dmamap->bd_ate_count);
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
+    }
+#ifdef IRIX
+    DEL(pcibr_dmamap);
+#else
+    free_pciio_dmamap(pcibr_dmamap);
+#endif
+}
+
+/*
+ * Setup an Address Translation Entry as specified.  Use either the Bridge
+ * internal maps or the external map RAM, as appropriate.
+ */
+LOCAL bridge_ate_p
+pcibr_ate_addr(pcibr_soft_t pcibr_soft,
+	       int ate_index)
+{
+    bridge_t *bridge = pcibr_soft->bs_base;
+
+    return (ate_index < pcibr_soft->bs_int_ate_size)
+	? &(bridge->b_int_ate_ram[ate_index].wr)
+	: &(bridge->b_ext_ate_ram[ate_index]);
+}
+
+/*
+ *    pcibr_addr_xio_to_pci: given a PIO range, hand
+ *      back the corresponding base PCI MEM address;
+ *      this is used to short-circuit DMA requests that
+ *      loop back onto this PCI bus.
+ */
+LOCAL iopaddr_t
+pcibr_addr_xio_to_pci(pcibr_soft_t soft,
+		      iopaddr_t xio_addr,
+		      size_t req_size)
+{
+    iopaddr_t               xio_lim = xio_addr + req_size - 1;
+    iopaddr_t               pci_addr;
+    pciio_slot_t            slot;
+
+    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
+	return pci_addr;
+    }
+    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
+	return pci_addr;
+    }
+    for (slot = 0; slot < 8; ++slot)
+	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
+	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
+	    bridgereg_t             dev;
+
+	    dev = soft->bs_slot[slot].bss_device;
+	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
+	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
+	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
+	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
+	}
+    return 0;
+}
+
+/* We are starting to get more complexity
+ * surrounding writing ATEs, so pull
+ * the writing code into this new function.
+ */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif
+
+LOCAL unsigned
+ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   unsigned *freeze_time_ptr,
+#endif
+	   unsigned *cmd_regs)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+#ifdef LATER
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+#endif
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+    int                     slot;
+
+    unsigned long           s;
+    unsigned                cmd_reg;
+    volatile unsigned      *cmd_lwa;
+    unsigned                cmd_lwd;
+
+    if (!ext_ates)
+	return 0;
+
+    /* Bridge Hardware Bug WAR #484930:
+     * Bridge can't handle updating External ATEs
+     * while DMA is occuring that uses External ATEs,
+     * even if the particular ATEs involved are disjoint.
+     */
+
+    /* need to prevent anyone else from
+     * unfreezing the grant while we
+     * are working; also need to prevent
+     * this thread from being interrupted
+     * to keep PCI grant freeze time
+     * at an absolute minimum.
+     */
+    s = pcibr_lock(pcibr_soft);
+
+#ifdef LATER
+    /* just in case pcibr_dmamap_done was not called */
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+    }
+#endif	/* LATER */
+#if PCIBR_FREEZE_TIME
+    *freeze_time_ptr = get_timestamp();
+#endif
+
+    cmd_lwa = 0;
+    for (slot = 0; slot < 8; ++slot)
+	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+	    cmd_reg = pcibr_soft->
+		bs_slot[slot].
+		bss_cmd_shadow;
+	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
+		cmd_lwa = pcibr_soft->
+		    bs_slot[slot].
+		    bss_cmd_pointer;
+		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
+		cmd_lwa[0] = cmd_lwd;
+	    }
+	    cmd_regs[slot] = cmd_reg;
+	} else
+	    cmd_regs[slot] = 0;
+
+    if (cmd_lwa) {
+	    bridge_t	*bridge = pcibr_soft->bs_base;
+
+	    /* Read the last master bit that has been cleared. This PIO read
+	     * on the PCI bus is to ensure the completion of any DMAs that
+	     * are due to bus requests issued by PCI devices before the
+	     * clearing of master bits.
+	     */
+	    cmd_lwa[0];
+
+	    /* Flush all the write buffers in the bridge */
+	    for (slot = 0; slot < 8; ++slot)
+		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+			    /* Flush the write buffer associated with this
+			     * PCI device which might be using dma map RAM.
+			     */
+			    bridge->b_wr_req_buf[slot].reg;
+		    }
+    }
+    return s;
+}
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+
+LOCAL void
+ate_write(bridge_ate_p ate_ptr,
+	  int ate_count,
+	  bridge_ate_t ate)
+{
+    while (ate_count-- > 0) {
+	*ate_ptr++ = ate;
+	ate += IOPGSIZE;
+    }
+}
+
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+LOCAL void
+ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 int ate_index,
+#if PCIBR_FREEZE_TIME
+	 bridge_ate_t ate,
+	 int ate_total,
+	 unsigned freeze_time_start,
+#endif
+	 unsigned *cmd_regs,
+	 unsigned s)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+    int                     slot;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+
+    unsigned                cmd_reg;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+    static unsigned         max_freeze_time = 0;
+    static unsigned         max_ate_total;
+#endif
+
+    if (!ext_ates)
+	return;
+
+    /* restore cmd regs */
+    for (slot = 0; slot < 8; ++slot)
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
+	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+
+    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
+    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+
+#if PCIBR_FREEZE_TIME
+    freeze_time = get_timestamp() - freeze_time_start;
+
+    if ((max_freeze_time < freeze_time) ||
+	(max_ate_total < ate_total)) {
+	if (max_freeze_time < freeze_time)
+	    max_freeze_time = freeze_time;
+	if (max_ate_total < ate_total)
+	    max_ate_total = ate_total;
+	pcibr_unlock(pcibr_soft, s);
+	printk("%s: pci freeze time %d usec for %d ATEs\n"
+		"\tfirst ate: %R\n",
+		pcibr_soft->bs_name,
+		freeze_time * 1000 / 1250,
+		ate_total,
+		ate, ate_bits);
+    } else
+#endif
+	pcibr_unlock(pcibr_soft, s);
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
+		  paddr_t paddr,
+		  size_t req_size)
+{
+    pcibr_soft_t            pcibr_soft;
+    iopaddr_t               xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    unsigned                flags;
+
+    ASSERT(pcibr_dmamap != NULL);
+    ASSERT(req_size > 0);
+    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    flags = pcibr_dmamap->bd_flags;
+
+    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
+    if (XIO_PACKED(xio_addr)) {
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+    } else
+	xio_port = pcibr_dmamap->bd_xio_port;
+
+    /* If this DMA is to an address that
+     * refers back to this Bridge chip,
+     * reduce it back to the correct
+     * PCI MEM address.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+    } else if (flags & PCIIO_DMA_A64) {
+	/* A64 DMA:
+	 * always use 64-bit direct mapping,
+	 * which always works.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	/* attributes are already bundled up into bd_pci_addr.
+	 */
+	pci_addr = pcibr_dmamap->bd_pci_addr
+	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
+	    | xio_addr;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    pci_addr &= ~PCI64_ATTR_PREF;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct64):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else if (flags & PCIIO_FIXED) {
+	/* A32 direct DMA:
+	 * always use 32-bit direct mapping,
+	 * which may fail.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	if (xio_port != pcibr_soft->bs_dir_xport)
+	    pci_addr = 0;		/* wrong DIDN */
+	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
+	    pci_addr = 0;		/* out of range */
+	else if ((xio_addr + req_size) >
+		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
+	    pci_addr = 0;		/* out of range */
+	else
+	    pci_addr = pcibr_dmamap->bd_pci_addr +
+		xio_addr - pcibr_dmamap->bd_xio_addr;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct32):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+	iopaddr_t               offset = IOPGOFF(xio_addr);
+	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
+	int                     ate_count = IOPG(offset + req_size - 1) + 1;
+
+	int                     ate_index = pcibr_dmamap->bd_ate_index;
+	unsigned                cmd_regs[8];
+	unsigned                s;
+
+#if PCIBR_FREEZE_TIME
+	int                     ate_total = ate_count;
+	unsigned                freeze_time;
+#endif
+
+#if PCIBR_ATE_DEBUG
+	bridge_ate_t            ate_cmp;
+	bridge_ate_p            ate_cptr;
+	unsigned                ate_lo, ate_hi;
+	int                     ate_bad = 0;
+	int                     ate_rbc = 0;
+#endif
+	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	bridge_ate_t            ate;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    ate_proto &= ~ATE_PREF;
+
+	ate = ate_proto
+	    | (xio_port << ATE_TIDSHIFT)
+	    | (xio_addr - offset);
+
+	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
+
+	/* Fill in our mapping registers
+	 * with the appropriate xtalk data,
+	 * and hand back the PCI address.
+	 */
+
+	ASSERT(ate_count > 0);
+	if (ate_count <= pcibr_dmamap->bd_ate_count) {
+		ATE_FREEZE();
+		ATE_WRITE();
+		ATE_THAW();
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	} else {
+		/* The number of ATE's required is greater than the number
+		 * allocated for this map. One way this can happen is if
+		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
+		 * flag, and then when that map is used (right now), the
+		 * target address tells us we really did need to roundup.
+		 * The other possibility is that the map is just plain too
+		 * small to handle the requested target area.
+		 */
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING   "pcibr_dmamap_addr :\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\tate_count 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			paddr, paddr + req_size - 1,
+			ate_count, pcibr_dmamap->bd_ate_count);
+#endif
+		pci_addr = 0;
+	}
+
+    }
+    return pci_addr;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
+		  alenlist_t palenlist,
+		  unsigned flags)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge=NULL;
+
+    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+    int                     inplace = flags & PCIIO_INPLACE;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist;
+    size_t                  length;
+    iopaddr_t               offset;
+    unsigned                direct64;
+    int                     ate_index = 0;
+    int                     ate_count = 0;
+    int                     ate_total = 0;
+    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
+    bridge_ate_t            ate_proto = (bridge_ate_t)0;
+    bridge_ate_t            ate_prev;
+    bridge_ate_t            ate;
+    alenaddr_t              xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    alenaddr_t              new_addr;
+
+    unsigned                cmd_regs[8];
+    unsigned                s = 0;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+#endif
+    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
+							 * with an ATE_FREEZE
+							 */
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
+				       flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
+    if (!direct64) {
+	bridge = pcibr_soft->bs_base;
+	ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	ate_index = pcibr_dmamap->bd_ate_index;
+	ate_proto = pcibr_dmamap->bd_ate_proto;
+	ATE_FREEZE();
+	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
+    }
+    pci_addr = pcibr_dmamap->bd_pci_addr;
+
+    ate_prev = 0;			/* matches no valid ATEs */
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &length, al_flags)) {
+	if (XIO_PACKED(xio_addr)) {
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_dmamap->bd_xio_port;
+
+	if (xio_port == pcibr_soft->bs_xid) {
+	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
+	    if (new_addr == PCI_NOWHERE)
+		goto fail;
+	} else if (direct64) {
+	    new_addr = pci_addr | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Bridge Hardware WAR #482836:
+	     * If the transfer is not cache aligned
+	     * and the Bridge Rev is <= B, force
+	     * prefetch to be off.
+	     */
+	    if (flags & PCIBR_NOPREFETCH)
+		new_addr &= ~PCI64_ATTR_PREF;
+
+	} else {
+	    /* calculate the ate value for
+	     * the first address. If it
+	     * matches the previous
+	     * ATE written (ie. we had
+	     * multiple blocks in the
+	     * same IOPG), then back up
+	     * and reuse that ATE.
+	     *
+	     * We are NOT going to
+	     * aggressively try to
+	     * reuse any other ATEs.
+	     */
+	    offset = IOPGOFF(xio_addr);
+	    ate = ate_proto
+		| (xio_port << ATE_TIDSHIFT)
+		| (xio_addr - offset);
+	    if (ate == ate_prev) {
+#if PCIBR_ATE_DEBUG
+		printk("pcibr_dmamap_list: ATE share\n");
+#endif
+		ate_ptr--;
+		ate_index--;
+		pci_addr -= IOPGSIZE;
+	    }
+	    new_addr = pci_addr + offset;
+
+	    /* Fill in the hardware ATEs
+	     * that contain this block.
+	     */
+	    ate_count = IOPG(offset + length - 1) + 1;
+	    ate_total += ate_count;
+
+	    /* Ensure that this map contains enough ATE's */
+	    if (ate_total > pcibr_dmamap->bd_ate_count) {
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING   "pcibr_dmamap_list :\n"
+			"\twanted xio_addr [0x%x..0x%x]\n"
+			"\tate_total 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			xio_addr, xio_addr + length - 1,
+			ate_total, pcibr_dmamap->bd_ate_count);
+#endif
+		goto fail;
+	    }
+
+	    ATE_WRITE();
+
+	    ate_index += ate_count;
+	    ate_ptr += ate_count;
+
+	    ate_count <<= IOPFNSHIFT;
+	    ate += ate_count;
+	    pci_addr += ate_count;
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &new_addr, &length, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				new_addr, length, al_flags))
+		goto fail;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+
+
+    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
+     * changes that ATE_FREEZE has done to implement the external SSRAM
+     * bug workaround.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    return pciio_alenlist;
+
+  fail:
+    /* There are various points of failure after doing an ATE_FREEZE
+     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
+     * The decision to do an ATE_THAW needs to be based on whether a
+     * an ATE_FREEZE was done before.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;
+    }
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
+{
+    /*
+     * We could go through and invalidate ATEs here;
+     * for performance reasons, we don't.
+     * We also don't enforce the strict alternation
+     * between _addr/_list and _done, but Hub does.
+     */
+
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
+    }
+
+    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+}
+
+
+/*
+ * For each bridge, the DIR_OFF value in the Direct Mapping Register
+ * determines the PCI to Crosstalk memory mapping to be used for all
+ * 32-bit Direct Mapping memory accesses. This mapping can be to any
+ * node in the system. This function will return that compact node id.
+ */
+
+/*ARGSUSED */
+cnodeid_t
+pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
+{
+
+	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
+	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    paddr_t paddr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+
+    xwidgetnum_t            xio_port;
+    iopaddr_t               xio_addr;
+    iopaddr_t               pci_addr;
+
+    int                     have_rrbs;
+    int                     min_rrbs;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
+				   flags & DMAMAP_FLAGS);
+
+    if (!xio_addr) {
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+	return 0;
+    }
+    /*
+     * find which XIO port this goes to.
+     */
+    if (XIO_PACKED(xio_addr)) {
+	if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	    return 0;
+	}
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+
+    } else
+	xio_port = pcibr_soft->bs_mxid;
+
+    /*
+     * If this DMA comes back to us,
+     * return the PCI MEM address on
+     * which it would land, or NULL
+     * if the target is something
+     * on bridge other than PCI MEM.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+	return pci_addr;
+    }
+    /* If the caller can use A64, try to
+     * satisfy the request with the 64-bit
+     * direct map. This can fail if the
+     * configuration bits in Device(x)
+     * conflict with our flags.
+     */
+
+    if (flags & PCIIO_DMA_A64) {
+	pci_addr = slotp->bss_d64_base;
+	if (!(flags & PCIBR_VCHAN1))
+	    flags |= PCIBR_VCHAN0;
+	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+#if DEBUG && PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr);
+#endif
+	    return (pci_addr);
+	}
+	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_addr;
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n"
+			"\tnew flags: 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr, (uint64_t) flags);
+#endif
+	    return (pci_addr);
+	}
+	/* our flags conflict with Device(x).
+	 */
+	flags = flags
+	    & ~PCIIO_DMA_A64
+	    & ~PCIBR_VCHAN0
+	    ;
+
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n"
+		"\tUnable to set Device(x) bits for Direct-64\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+    }
+    /* Try to satisfy the request with the 32-bit direct
+     * map. This can fail if the configuration bits in
+     * Device(x) conflict with our flags, or if the
+     * target address is outside where DIR_OFF points.
+     */
+    {
+	size_t                  map_size = 1ULL << 31;
+	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
+	iopaddr_t               offset = xio_addr - xio_base;
+	iopaddr_t               endoff = req_size + offset;
+
+	if ((req_size > map_size) ||
+	    (xio_addr < xio_base) ||
+	    (xio_port != pcibr_soft->bs_dir_xport) ||
+	    (endoff > map_size)) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\txio region outside direct32 target\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	} else {
+	    pci_addr = slotp->bss_d32_base;
+	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
+		(flags == slotp->bss_d32_flags)) {
+
+		pci_addr |= offset;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tmapped via direct32 offset 0x%x\n"
+			"\twill DMA via pci addr 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, offset, pci_addr);
+#endif
+		return (pci_addr);
+	    }
+	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
+
+		pci_addr = PCI32_DIRECT_BASE;
+		slotp->bss_d32_flags = flags;
+		slotp->bss_d32_base = pci_addr;
+		pci_addr |= offset;
+
+		/* Make sure we have an RRB (or two).
+		 */
+		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		    if (have_rrbs < 2) {
+			if (slotp->bss_device & BRIDGE_DEV_PREF)
+			    min_rrbs = 2;
+			else
+			    min_rrbs = 1;
+			if (have_rrbs < min_rrbs)
+			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		    }
+		}
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+		if (xio_addr != 0x20000000)
+#endif
+		    printk("pcibr_dmatrans_addr:\n"
+			    "\tpciio connection point %v\n"
+			    "\txtalk connection point %v\n"
+			    "\twanted paddr [0x%x..0x%x]\n"
+			    "\txtalk_dmatrans_addr returned 0x%x\n"
+			    "\tmapped via direct32 offset 0x%x\n"
+			    "\twill DMA via pci addr 0x%x\n"
+			    "\tnew flags: 0x%x\n",
+			    pconn_vhdl, xconn_vhdl,
+			    paddr, paddr + req_size - 1,
+			    xio_addr, offset, pci_addr, (uint64_t) flags);
+#endif
+		return (pci_addr);
+	    }
+	    /* our flags conflict with Device(x).
+	     */
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\tUnable to set Device(x) bits for Direct-32\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	}
+    }
+
+#if PCIBR_DMA_DEBUG
+    printk("pcibr_dmatrans_addr:\n"
+	    "\tpciio connection point %v\n"
+	    "\txtalk connection point %v\n"
+	    "\twanted paddr [0x%x..0x%x]\n"
+	    "\txtalk_dmatrans_addr returned 0x%x\n"
+	    "\tno acceptable PCI address found or constructable\n",
+	    pconn_vhdl, xconn_vhdl,
+	    paddr, paddr + req_size - 1,
+	    xio_addr);
+#endif
+
+    return 0;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    alenlist_t palenlist,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+    xwidgetnum_t            xio_port;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist = 0;
+
+    int                     inplace;
+    unsigned                direct64;
+    unsigned                al_flags;
+
+    iopaddr_t               xio_base;
+    alenaddr_t              xio_addr;
+    size_t                  xio_size;
+
+    size_t                  map_size;
+    iopaddr_t               pci_base;
+    alenaddr_t              pci_addr;
+
+    unsigned                relbits = 0;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    inplace = flags & PCIIO_INPLACE;
+    direct64 = flags & PCIIO_DMA_A64;
+    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+
+    if (direct64) {
+	map_size = 1ull << 48;
+	xio_base = 0;
+	pci_base = slotp->bss_d64_base;
+	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D64_BITS;
+	    pci_base =
+		pcibr_flags_to_d64(flags, pcibr_soft);
+	}
+    } else {
+	xio_base = pcibr_soft->bs_dir_xbase;
+	map_size = 1ull << 31;
+	pci_base = slotp->bss_d32_base;
+	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
+	    (flags == slotp->bss_d32_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D32_BITS;
+	    pci_base = PCI32_DIRECT_BASE;
+	}
+    }
+
+    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
+					 flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &xio_size, al_flags)) {
+
+	/*
+	 * find which XIO port this goes to.
+	 */
+	if (XIO_PACKED(xio_addr)) {
+	    if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr);
+#endif
+		return 0;
+	    }
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_soft->bs_mxid;
+
+	/*
+	 * If this DMA comes back to us,
+	 * return the PCI MEM address on
+	 * which it would land, or NULL
+	 * if the target is something
+	 * on bridge other than PCI MEM.
+	 */
+	if (xio_port == pcibr_soft->bs_xid) {
+	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
+	    if ( (pci_addr == (alenaddr_t)NULL) )
+		goto fail;
+	} else if (direct64) {
+	    ASSERT(xio_port != 0);
+	    pci_addr = pci_base | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+	} else {
+	    iopaddr_t               offset = xio_addr - xio_base;
+	    iopaddr_t               endoff = xio_size + offset;
+
+	    if ((xio_size > map_size) ||
+		(xio_addr < xio_base) ||
+		(xio_port != pcibr_soft->bs_dir_xport) ||
+		(endoff > map_size))
+		goto fail;
+
+	    pci_addr = pci_base + (xio_addr - xio_base);
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &pci_addr, &xio_size, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				pci_addr, xio_size, al_flags))
+		goto fail;
+	}
+    }
+
+    if (relbits) {
+	if (direct64) {
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_base;
+	} else {
+	    slotp->bss_d32_flags = flags;
+	    slotp->bss_d32_base = pci_base;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+    return pciio_alenlist;
+
+  fail:
+    if (relbits)
+	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+void
+pcibr_dmamap_drain(pcibr_dmamap_t map)
+{
+    xtalk_dmamap_drain(map->bd_xtalk);
+}
+
+void
+pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
+		    paddr_t paddr,
+		    size_t bytes)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
+}
+
+void
+pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
+		    alenlist_t list)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmalist_drain(xconn_vhdl, list);
+}
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+iopaddr_t
+pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
+{
+    return (pcibr_dmamap->bd_pci_addr);
+}
+
+/*
+ *	There are end cases where a deadlock can occur if interrupt 
+ *	processing completes and the Bridge b_int_status bit is still set.
+ *
+ *	One scenerio is if a second PCI interrupt occurs within 60ns of
+ *	the previous interrupt being cleared. In this case the Bridge
+ *	does not detect the transition, the Bridge b_int_status bit
+ *	remains set, and because no transition was detected no interrupt
+ *	packet is sent to the Hub/Heart.
+ *
+ *	A second scenerio is possible when a b_int_status bit is being
+ *	shared by multiple devices:
+ *						Device #1 generates interrupt
+ *						Bridge b_int_status bit set
+ *						Device #2 generates interrupt
+ *		interrupt processing begins
+ *		  ISR for device #1 runs and
+ *			clears interrupt
+ *						Device #1 generates interrupt
+ *		  ISR for device #2 runs and
+ *			clears interrupt
+ *						(b_int_status bit still set)
+ *		interrupt processing completes
+ *		  
+ *	Interrupt processing is now complete, but an interrupt is still
+ *	outstanding for Device #1. But because there was no transition of
+ *	the b_int_status bit, no interrupt packet will be generated and
+ *	a deadlock will occur.
+ *
+ *	To avoid these deadlock situations, this function is used
+ *	to check if a specific Bridge b_int_status bit is set, and if so,
+ *	cause the setting of the corresponding interrupt bit.
+ *
+ *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
+ *	Interrupt register.
+ */
+void
+pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
+{
+	unsigned	bit;
+	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
+	bridge_t       *bridge = pcibr_soft->bs_base;
+	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
+
+	bit = wrap->iw_intr;
+
+	if (pcibr_soft->bs_xbridge) {
+	    bridge->b_force_pin[bit].intr = 1;
+	} else if ((1 << bit) & *wrap->iw_stat) {
+	    cpuid_t	    cpu;
+	    unsigned        intr_bit;
+	    xtalk_intr_t    xtalk_intr =
+				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
+
+	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
+	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
+#endif
+	}
+}
+
+/* =====================================================================
+ *    INTERRUPT MANAGEMENT
+ */
+
+static unsigned
+pcibr_intr_bits(pciio_info_t info,
+		pciio_intr_line_t lines)
+{
+    pciio_slot_t            slot = pciio_info_slot_get(info);
+    unsigned		    bbits = 0;
+
+    /*
+     * Currently favored mapping from PCI
+     * slot number and INTA/B/C/D to Bridge
+     * PCI Interrupt Bit Number:
+     *
+     *     SLOT     A B C D
+     *      0       0 4 0 4
+     *      1       1 5 1 5
+     *      2       2 6 2 6
+     *      3       3 7 3 7
+     *      4       4 0 4 0
+     *      5       5 1 5 1
+     *      6       6 2 6 2
+     *      7       7 3 7 3
+     */
+
+    if (slot < 8) {
+	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
+	    bbits |= 1 << slot;
+	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
+	    bbits |= 1 << (slot ^ 4);
+    }
+    return bbits;
+}
+
+
+/*ARGSUSED */
+pcibr_intr_t
+pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
+		 device_desc_t dev_desc,
+		 pciio_intr_line_t lines,
+		 devfs_handle_t owner_dev)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     is_threaded = 0;
+    int                     thread_swlevel;
+
+    xtalk_intr_t           *xtalk_intr_p;
+    pcibr_intr_t           *pcibr_intr_p;
+    pcibr_intr_list_t      *intr_list_p;
+
+    unsigned                pcibr_int_bits;
+    unsigned                pcibr_int_bit;
+    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
+    hub_intr_t		    hub_intr;
+    pcibr_intr_t            pcibr_intr;
+    pcibr_intr_list_t       intr_entry;
+    pcibr_intr_list_t       intr_list;
+    bridgereg_t             int_dev;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_alloc\n"
+	    "%v:%s%s%s%s%s\n",
+	    owner_dev, pconn_vhdl,
+	    !(lines & 15) ? " No INTs?" : "",
+	    lines & 1 ? " INTA" : "",
+	    lines & 2 ? " INTB" : "",
+	    lines & 4 ? " INTC" : "",
+	    lines & 8 ? " INTD" : "");
+#endif
+
+    NEW(pcibr_intr);
+    if (!pcibr_intr)
+	return NULL;
+
+    if (dev_desc) {
+	cpuid_t intr_target_from_desc(device_desc_t, int);
+    } else {
+	extern int default_intr_pri;
+
+	is_threaded = 1; /* PCI interrupts are threaded, by default */
+	thread_swlevel = default_intr_pri;
+    }
+
+    pcibr_intr->bi_dev = pconn_vhdl;
+    pcibr_intr->bi_lines = lines;
+    pcibr_intr->bi_soft = pcibr_soft;
+    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
+    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
+    pcibr_intr->bi_mustruncpu = CPU_NONE;
+    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
+
+    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
+
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+#if DEBUG && INTR_DEBUG
+    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
+#endif 
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    xtalk_intr = *xtalk_intr_p;
+
+	    if (xtalk_intr == NULL) {
+		/*
+		 * This xtalk_intr_alloc is constrained for two reasons:
+		 * 1) Normal interrupts and error interrupts need to be delivered
+		 *    through a single xtalk target widget so that there aren't any
+		 *    ordering problems with DMA, completion interrupts, and error
+		 *    interrupts. (Use of xconn_vhdl forces this.)
+		 *
+		 * 2) On IP35, addressing constraints on IP35 and Bridge force
+		 *    us to use a single PI number for all interrupts from a
+		 *    single Bridge. (IP35-specific code forces this, and we
+		 *    verify in pcibr_setwidint.)
+		 */
+
+		/*
+		 * All code dealing with threaded PCI interrupt handlers
+		 * is located at the pcibr level. Because of this,
+		 * we always want the lower layers (hub/heart_intr_alloc, 
+		 * intr_level_connect) to treat us as non-threaded so we
+		 * don't set up a duplicate threaded environment. We make
+		 * this happen by calling a special xtalk interface.
+		 */
+		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
+			owner_dev);
+#if DEBUG && INTR_DEBUG
+		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
+#endif
+
+		/* both an assert and a runtime check on this:
+		 * we need to check in non-DEBUG kernels, and
+		 * the ASSERT gets us more information when
+		 * we use DEBUG kernels.
+		 */
+		ASSERT(xtalk_intr != NULL);
+		if (xtalk_intr == NULL) {
+		    /* it is quite possible that our
+		     * xtalk_intr_alloc failed because
+		     * someone else got there first,
+		     * and we can find their results
+		     * in xtalk_intr_p.
+		     */
+		    if (!*xtalk_intr_p) {
+#ifdef SUPPORT_PRINTING_V_FORMAT
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
+				xconn_vhdl);
+#else
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc 0x%p: unable to get xtalk interrupt resources",
+				(void *)xconn_vhdl);
+#endif
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
+		    /*
+		     * now tell the bridge which slot is
+		     * using this interrupt line.
+		     */
+		    int_dev = bridge->b_int_device;
+		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
+		    bridge->b_int_device = int_dev;	/* XXXMP */
+
+#if DEBUG && INTR_DEBUG
+		    printk("%v: bridge intr bit %d clears my wrb\n",
+			    pconn_vhdl, pcibr_int_bit);
+#endif
+		} else {
+		    /* someone else got one allocated first;
+		     * free the one we just created, and
+		     * retrieve the one they allocated.
+		     */
+		    xtalk_intr_free(xtalk_intr);
+		    xtalk_intr = *xtalk_intr_p;
+#if PARANOID
+		    /* once xtalk_intr is set, we never clear it,
+		     * so if the CAS fails above, this condition
+		     * can "never happen" ...
+		     */
+		    if (!xtalk_intr) {
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
+				xconn_vhdl);
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+#endif
+		}
+	    }
+
+	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
+
+	    NEW(intr_entry);
+	    intr_entry->il_next = NULL;
+	    intr_entry->il_intr = pcibr_intr;
+	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
+	    intr_list_p = 
+		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+#if DEBUG && INTR_DEBUG
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#else
+	    printk("%v: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#endif
+#endif
+
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the first interrupt on this bridge bit.
+		 */
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list = *intr_list_p;
+	    pcibr_intr_p = &intr_list->il_intr;
+	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		/* first entry on list was erased,
+		 * and we replaced it, so we
+		 * don't need our intr_entry.
+		 */
+		DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list_p = &intr_list->il_next;
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the new second interrupt on this bit.
+		 */
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    while (1) {
+		pcibr_intr_p = &intr_list->il_intr;
+		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		    /* an entry on list was erased,
+		     * and we replaced it, so we
+		     * don't need our intr_entry.
+		     */
+		    DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		intr_list_p = &intr_list->il_next;
+		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		    /* entry appended to share list
+		     */
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		/* step to next record in chain
+		 */
+		intr_list = *intr_list_p;
+	    }
+	}
+    }
+
+#if DEBUG && INTR_DEBUG
+    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
+#endif
+    hub_intr = (hub_intr_t)xtalk_intr;
+    pcibr_intr->bi_irq = hub_intr->i_bit;
+    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
+    return pcibr_intr;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_free(pcibr_intr_t pcibr_intr)
+{
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bit;
+    pcibr_intr_list_t       intr_list;
+    int			    intr_shared;
+    xtalk_intr_t	    *xtalk_intrp;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    for (intr_list = 
+		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+		 intr_list != NULL;
+		 intr_list = intr_list->il_next)
+		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
+					 pcibr_intr, 
+					 NULL)) {
+#if DEBUG && INTR_DEBUG
+		    printk("%s: cleared a handler from bit %d\n",
+			    pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+		}
+	    /* If this interrupt line is not being shared between multiple
+	     * devices release the xtalk interrupt resources.
+	     */
+	    intr_shared = 
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
+	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    if ((!intr_shared) && (*xtalk_intrp)) {
+
+		bridge_t 	*bridge = pcibr_soft->bs_base;
+		bridgereg_t	int_dev;
+
+		xtalk_intr_free(*xtalk_intrp);
+		*xtalk_intrp = 0;
+
+		/* Clear the PCI device interrupt to bridge interrupt pin
+		 * mapping.
+		 */
+		int_dev = bridge->b_int_device;
+		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		bridge->b_int_device = int_dev;
+
+	    }
+	}
+    }
+    DEL(pcibr_intr);
+}
+
+LOCAL void
+pcibr_setpciint(xtalk_intr_t xtalk_intr)
+{
+    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
+    bridgereg_t            *int_addr = (bridgereg_t *)
+    xtalk_intr_sfarg_get(xtalk_intr);
+
+#ifdef CONFIG_IA64_SGI_SN2
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 26)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+#elif CONFIG_IA64_SGI_SN1
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+#endif
+}
+
+/*ARGSUSED */
+int
+pcibr_intr_connect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    if (pcibr_intr == NULL)
+	return -1;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_connect\n",
+	    pcibr_intr->bi_dev);
+#endif
+
+    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_t            xtalk_intr;
+
+	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    /*
+	     * If this interrupt line is being shared and the connect has
+	     * already been done, no need to do it again.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
+		continue;
+
+
+	    /*
+	     * Use the pcibr wrapper function to handle all Bridge interrupts
+	     * regardless of whether the interrupt line is shared or not.
+	     */
+	    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint,
+			       (void *)&(bridge->b_int_addr[pcibr_int_bit].addr));
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%v bridge bit %d wrapper connected\n",
+		    pcibr_intr->bi_dev, pcibr_int_bit);
+#endif
+	}
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable |= pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    /* Stop calling the function. Now.
+     */
+    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and disconnect the interrupt.
+     */
+
+    /* don't disable interrupts for lines that
+     * are shared between devices.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
+	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
+	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
+    if (!pcibr_int_bits)
+	return;
+
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable &= ~pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    /* if the interrupt line is now shared,
+	     * do not disconnect it.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
+		pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+
+	    /* if we are sharing the interrupt line,
+	     * connect us up; this closes the hole
+	     * where the another pcibr_intr_alloc()
+	     * was in progress as we disconnected.
+	     */
+	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
+			       (xtalk_intr_setfunc_t)pcibr_setpciint,
+			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr));
+	}
+}
+
+/*ARGSUSED */
+devfs_handle_t
+pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit))
+	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+    return 0;
+}
+
+/* =====================================================================
+ *    INTERRUPT HANDLING
+ */
+LOCAL void
+pcibr_clearwidint(bridge_t *bridge)
+{
+    bridge->b_wid_int_upper = 0;
+    bridge->b_wid_int_lower = 0;
+}
+
+LOCAL void
+pcibr_setwidint(xtalk_intr_t intr)
+{
+    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
+    iopaddr_t               addr = xtalk_intr_addr_get(intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
+    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
+    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
+
+    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
+
+    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+			       XTALK_ADDR_TO_UPPER(addr));
+    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+
+    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
+    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
+
+    /* Verify that all interrupts from this Bridge are using a single PI */
+    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
+	/*
+	 * Once set, these registers shouldn't change; they should
+	 * be set multiple times with the same values.
+	 *
+	 * If we're attempting to change these registers, it means
+	 * that our heuristics for allocating interrupts in a way
+	 * appropriate for IP35 have failed, and the admin needs to
+	 * explicitly direct some interrupts (or we need to make the
+	 * heuristics more clever).
+	 *
+	 * In practice, we hope this doesn't happen very often, if
+	 * at all.
+	 */
+	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
+	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
+		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
+		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
+		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
+		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
+			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
+			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
+		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
+	}
+    }
+
+    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
+    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
+    bridge->b_int_host_err = vect;
+}
+
+/*
+ * pcibr_intr_preset: called during mlreset time
+ * if the platform specific code needs to route
+ * one of the Bridge's xtalk interrupts before the
+ * xtalk infrastructure is available.
+ */
+void
+pcibr_xintr_preset(void *which_widget,
+		   int which_widget_intr,
+		   xwidgetnum_t targ,
+		   iopaddr_t addr,
+		   xtalk_intr_vector_t vect)
+{
+    bridge_t               *bridge = (bridge_t *) which_widget;
+
+    if (which_widget_intr == -1) {
+	/* bridge widget error interrupt */
+	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+				   XTALK_ADDR_TO_UPPER(addr));
+	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+	bridge->b_int_host_err = vect;
+
+	/* turn on all interrupts except
+	 * the PCI interrupt requests,
+	 * at least at heart.
+	 */
+	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
+
+    } else {
+	/* routing a PCI device interrupt.
+	 * targ and low 38 bits of addr must
+	 * be the same as the already set
+	 * value for the widget error interrupt.
+	 */
+	bridge->b_int_addr[which_widget_intr].addr =
+	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+	     (BRIDGE_INT_ADDR_FLD & vect));
+	/*
+	 * now bridge can let it through;
+	 * NB: still should be blocked at
+	 * xtalk provider end, until the service
+	 * function is set.
+	 */
+	bridge->b_int_enable |= 1 << vect;
+    }
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+}
+
+
+/*
+ * pcibr_intr_func()
+ *
+ * This is the pcibr interrupt "wrapper" function that is called,
+ * in interrupt context, to initiate the interrupt handler(s) registered
+ * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
+ * handlers will be called directly, and threaded handlers will have their 
+ * thread woken up.
+ */
+void
+pcibr_intr_func(intr_arg_t arg)
+{
+    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
+    reg_p                   wrbf;
+    pcibr_intr_t            intr;
+    pcibr_intr_list_t       list;
+    int                     clearit;
+    int			    do_nonthreaded = 1;
+    int			    is_threaded = 0;
+    int			    x = 0;
+
+	/*
+	 * If any handler is still running from a previous interrupt
+	 * just return. If there's a need to call the handler(s) again,
+	 * another interrupt will be generated either by the device or by
+	 * pcibr_force_interrupt().
+	 */
+
+	if (wrap->iw_hdlrcnt) {
+		return;
+	}
+
+    /*
+     * Call all interrupt handlers registered.
+     * First, the pcibr_intrd threads for any threaded handlers will be
+     * awoken, then any non-threaded handlers will be called sequentially.
+     */
+	
+	clearit = 1;
+	while (do_nonthreaded) {
+	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
+		if ((intr = list->il_intr) &&
+		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
+
+		/*
+		 * This device may have initiated write
+		 * requests since the bridge last saw
+		 * an edge on this interrupt input; flushing
+		 * the buffer prior to invoking the handler
+		 * should help but may not be sufficient if we 
+		 * get more requests after the flush, followed
+		 * by the card deciding it wants service, before
+		 * the interrupt handler checks to see if things need
+		 * to be done.
+		 *
+		 * There is a similar race condition if
+		 * an interrupt handler loops around and
+		 * notices further service is required.
+		 * Perhaps we need to have an explicit
+		 * call that interrupt handlers need to
+		 * do between noticing that DMA to memory
+		 * has completed, but before observing the
+		 * contents of memory?
+		 */
+
+			if ((do_nonthreaded) && (!is_threaded)) {
+			/* Non-threaded. 
+			 * Call the interrupt handler at interrupt level
+			 */
+
+			/* Only need to flush write buffers if sharing */
+
+			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
+			    if ((x = *wrbf))	/* write request buffer flush */
+#ifdef SUPPORT_PRINTING_V_FORMAT
+				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
+				    "write buffer flush failed, wrbf=0x%x\n", 
+				    list->il_intr->bi_dev, wrbf);
+#else
+				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
+				    "write buffer flush failed, wrbf=0x%lx\n", 
+				    (void *)list->il_intr->bi_dev, (long) wrbf);
+#endif
+			}
+		    }
+
+		    clearit = 0;
+		}
+	    }
+
+		do_nonthreaded = 0;
+		/*
+		 * If the non-threaded handler was the last to complete,
+		 * (i.e., no threaded handlers still running) force an
+		 * interrupt to avoid a potential deadlock situation.
+		 */
+		if (wrap->iw_hdlrcnt == 0) {
+			pcibr_force_interrupt(wrap);
+		}
+	}
+
+	/* If there were no handlers,
+	 * disable the interrupt and return.
+	 * It will get enabled again after
+	 * a handler is connected.
+	 * If we don't do this, we would
+	 * sit here and spin through the
+	 * list forever.
+	 */
+	if (clearit) {
+	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+	    bridgereg_t             b_int_enable;
+	    bridgereg_t		    mask = 1 << wrap->iw_intr;
+	    unsigned long           s;
+
+	    s = pcibr_lock(pcibr_soft);
+	    b_int_enable = bridge->b_int_enable;
+	    b_int_enable &= ~mask;
+	    bridge->b_int_enable = b_int_enable;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	    pcibr_unlock(pcibr_soft, s);
+	    return;
+	}
+}
+
+/* =====================================================================
+ *    CONFIGURATION MANAGEMENT
+ */
+/*ARGSUSED */
+void
+pcibr_provider_startup(devfs_handle_t pcibr)
+{
+}
+
+/*ARGSUSED */
+void
+pcibr_provider_shutdown(devfs_handle_t pcibr)
+{
+}
+
+int
+pcibr_reset(devfs_handle_t conn)
+{
+    pciio_info_t            pciio_info = pciio_info_get(conn);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             ctlreg;
+    unsigned                cfgctl[8];
+    unsigned long           s;
+    int                     f, nf;
+    pcibr_info_h            pcibr_infoh;
+    pcibr_info_t            pcibr_info;
+    int                     win;
+
+    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
+	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
+    }
+    if (pciio_slot < 4) {
+	s = pcibr_lock(pcibr_soft);
+	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
+	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
+
+	ctlreg = bridge->b_wid_control;
+	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
+	/* XXX delay? */
+	bridge->b_wid_control = ctlreg;
+	/* XXX delay? */
+
+	for (f = 0; f < nf; ++f)
+	    if ((pcibr_info = pcibr_infoh[f]))
+		for (win = 0; win < 6; ++win)
+		    if (pcibr_info->f_window[win].w_base != 0)
+			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
+			    pcibr_info->f_window[win].w_base;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
+	pcibr_unlock(pcibr_soft, s);
+
+	return 0;
+    }
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    printk(KERN_WARNING   "%v: pcibr_reset unimplemented for slot %d\n",
+	    conn, pciio_slot);
+#endif
+    return -1;
+}
+
+pciio_endian_t
+pcibr_endian_set(devfs_handle_t pconn_vhdl,
+		 pciio_endian_t device_end,
+		 pciio_endian_t desired_end)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             devreg;
+    unsigned long           s;
+
+    /*
+     * Bridge supports hardware swapping; so we can always
+     * arrange for the caller's desired endianness.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_end != desired_end)
+	devreg |= BRIDGE_DEV_SWAP_BITS;
+    else
+	devreg &= ~BRIDGE_DEV_SWAP_BITS;
+
+    /* NOTE- if we ever put SWAP bits
+     * onto the disabled list, we will
+     * have to change the logic here.
+     */
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
+#endif
+
+    return desired_end;
+}
+
+/* This (re)sets the GBR and REALTIME bits and also keeps track of how
+ * many sets are outstanding. Reset succeeds only if the number of outstanding
+ * sets == 1.
+ */
+int
+pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
+			pciio_slot_t pciio_slot,
+			pciio_priority_t device_prio)
+{
+    unsigned long           s;
+    int                    *counter;
+    bridgereg_t             rtbits = 0;
+    bridgereg_t             devreg;
+    int                     rc = PRIO_SUCCESS;
+
+    /* in dual-slot configurations, the host and the
+     * guest have separate DMA resources, so they
+     * have separate requirements for priority bits.
+     */
+
+    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
+
+    /*
+     * Bridge supports PCI notions of LOW and HIGH priority
+     * arbitration rings via a "REAL_TIME" bit in the per-device
+     * Bridge register. The "GBR" bit controls access to the GBR
+     * ring on the xbow. These two bits are (re)set together.
+     *
+     * XXX- Bug in Rev B Bridge Si:
+     * Symptom: Prefetcher starts operating incorrectly. This happens
+     * due to corruption of the address storage ram in the prefetcher
+     * when a non-real time PCI request is pulled and a real-time one is
+     * put in it's place. Workaround: Use only a single arbitration ring
+     * on PCI bus. GBR and RR can still be uniquely used per
+     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
+     */
+
+    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
+	rtbits |= BRIDGE_DEV_RT;
+
+    /* NOTE- if we ever put DEV_RT or DEV_GBR on
+     * the disabled list, we will have to take
+     * it into account here.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_prio == PCI_PRIO_HIGH) {
+	if ((++*counter == 1)) {
+	    if (rtbits)
+		devreg |= rtbits;
+	    else
+		rc = PRIO_FAIL;
+	}
+    } else if (device_prio == PCI_PRIO_LOW) {
+	if (*counter <= 0)
+	    rc = PRIO_FAIL;
+	else if (--*counter == 0)
+	    if (rtbits)
+		devreg &= ~rtbits;
+    }
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+    return rc;
+}
+
+pciio_priority_t
+pcibr_priority_set(devfs_handle_t pconn_vhdl,
+		   pciio_priority_t device_prio)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
+
+    return device_prio;
+}
+
+/*
+ * Interfaces to allow special (e.g. SGI) drivers to set/clear
+ * Bridge-specific device flags.  Many flags are modified through
+ * PCI-generic interfaces; we don't allow them to be directly
+ * manipulated here.  Only flags that at this point seem pretty
+ * Bridge-specific can be set through these special interfaces.
+ * We may add more flags as the need arises, or remove flags and
+ * create PCI-generic interfaces as the need arises.
+ *
+ * Returns 0 on failure, 1 on success
+ */
+int
+pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
+		       pcibr_device_flags_t flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             set = 0;
+    bridgereg_t             clr = 0;
+
+    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_PMU_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_PMU_WRGA_EN;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_DIR_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_DIR_WRGA_EN;
+
+    if (flags & PCIBR_PREFETCH)
+	set |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	clr |= BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	set |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	clr |= BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	set |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	clr |= BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	set |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	clr |= BRIDGE_DEV_DEV_SIZE;
+
+    if (set || clr) {
+	bridgereg_t             devreg;
+	unsigned long           s;
+
+	s = pcibr_lock(pcibr_soft);
+	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+	devreg = (devreg & ~clr) | set;
+	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+
+	    bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	}
+	pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
+#endif
+    }
+    return (1);
+}
+
+#ifdef LITTLE_ENDIAN
+/*
+ * on sn-ia we need to twiddle the the addresses going out
+ * the pci bus because we use the unswizzled synergy space
+ * (the alternative is to use the swizzled synergy space
+ * and byte swap the data)
+ */
+#define	CB(b,r)	(((volatile uint8_t *) b)[((r)^4)])
+#define	CS(b,r)	(((volatile uint16_t *) b)[((r^4)/2)])
+#define	CW(b,r)	(((volatile uint32_t *) b)[((r^4)/4)])
+#else
+#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
+#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
+#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
+#endif /* LITTLE_ENDIAN */
+
+
+LOCAL                   cfg_p
+pcibr_config_addr(devfs_handle_t conn,
+		  unsigned reg)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_slot_t            pciio_slot;
+    pciio_function_t        pciio_func;
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    cfg_p                   cfgbase = (cfg_p)0;
+
+    pcibr_info = pcibr_info_get(conn);
+
+    pciio_slot = pcibr_info->f_slot;
+    if (pciio_slot == PCIIO_SLOT_NONE)
+	pciio_slot = PCI_TYPE1_SLOT(reg);
+
+    pciio_func = pcibr_info->f_func;
+    if (pciio_func == PCIIO_FUNC_NONE)
+	pciio_func = PCI_TYPE1_FUNC(reg);
+
+    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    bridge = pcibr_soft->bs_base;
+
+    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
+
+    return cfgbase;
+}
+
+uint64_t
+pcibr_config_get(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size)
+{
+    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
+			       PCI_TYPE1_REG(reg), size);
+}
+
+LOCAL uint64_t
+do_pcibr_config_get(
+		       cfg_p cfgbase,
+		       unsigned reg,
+		       unsigned size)
+{
+    unsigned                value;
+
+   
+    value = CW(cfgbase, reg);
+
+    if (reg & 3)
+	value >>= 8 * (reg & 3);
+    if (size < 4)
+	value &= (1 << (8 * size)) - 1;
+
+    return value;
+}
+
+void
+pcibr_config_set(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size,
+		 uint64_t value)
+{
+    do_pcibr_config_set(pcibr_config_addr(conn, reg),
+			PCI_TYPE1_REG(reg), size, value);
+}
+
+LOCAL void
+do_pcibr_config_set(cfg_p cfgbase,
+		    unsigned reg,
+		    unsigned size,
+		    uint64_t value)
+{
+    switch (size) {
+    case 1:
+	CB(cfgbase, reg) = value;
+	break;
+    case 2:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 1) = value >> 8;
+	} else
+	    CS(cfgbase, reg) = value;
+	break;
+    case 3:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CS(cfgbase, (reg + 1)) = value >> 8;
+	} else {
+	    CS(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 2) = value >> 16;
+	}
+	break;
+
+    case 4:
+	CW(cfgbase, reg) = value;
+	break;
+    }
+}
+
+pciio_provider_t        pcibr_provider =
+{
+    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
+    (pciio_piomap_free_f *) pcibr_piomap_free,
+    (pciio_piomap_addr_f *) pcibr_piomap_addr,
+    (pciio_piomap_done_f *) pcibr_piomap_done,
+    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
+    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
+    (pciio_piospace_free_f *) pcibr_piospace_free,
+
+    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
+    (pciio_dmamap_free_f *) pcibr_dmamap_free,
+    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
+    (pciio_dmamap_list_f *) pcibr_dmamap_list,
+    (pciio_dmamap_done_f *) pcibr_dmamap_done,
+    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
+    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
+    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
+    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
+    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
+
+    (pciio_intr_alloc_f *) pcibr_intr_alloc,
+    (pciio_intr_free_f *) pcibr_intr_free,
+    (pciio_intr_connect_f *) pcibr_intr_connect,
+    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
+    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
+
+    (pciio_provider_startup_f *) pcibr_provider_startup,
+    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
+    (pciio_reset_f *) pcibr_reset,
+    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
+    (pciio_endian_set_f *) pcibr_endian_set,
+    (pciio_priority_set_f *) pcibr_priority_set,
+    (pciio_config_get_f *) pcibr_config_get,
+    (pciio_config_set_f *) pcibr_config_set,
+
+    (pciio_error_devenable_f *) 0,
+    (pciio_error_extract_f *) 0,
+
+#ifdef LATER
+    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
+    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
+#else
+    (pciio_driver_reg_callback_f *) 0,
+    (pciio_driver_unreg_callback_f *) 0,
+#endif
+    (pciio_device_unregister_f 	*) pcibr_device_unregister,
+    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
+};
+
+LOCAL                   pcibr_hints_t
+pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
+{
+    arbitrary_info_t        ainfo = 0;
+    graph_error_t	    rv;
+    pcibr_hints_t           hint;
+
+    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+
+    if (alloc && (rv != GRAPH_SUCCESS)) {
+
+	NEW(hint);
+	hint->rrb_alloc_funct = NULL;
+	hint->ph_intr_bits = NULL;
+	rv = hwgraph_info_add_LBL(xconn_vhdl, 
+				  INFO_LBL_PCIBR_HINTS, 	
+				  (arbitrary_info_t) hint);
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+	
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	if (ainfo != (arbitrary_info_t) hint)
+	    goto abnormal_exit;
+    }
+    return (pcibr_hints_t) ainfo;
+
+abnormal_exit:
+#ifdef LATER
+    printf("SHOULD NOT BE HERE\n");
+#endif
+    DEL(hint);
+    return(NULL);
+
+}
+
+void
+pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_rrb_fixed = mask;
+#if DEBUG
+    else
+	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
+}
+
+void
+pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
+		     pciio_slot_t host,
+		     pciio_slot_t guest)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_host_slot[guest] = host + 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
+		      pcibr_intr_bits_f *xxx_intr_bits)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_intr_bits = xxx_intr_bits;
+#if DEBUG
+    else
+	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
+	       "\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->rrb_alloc_funct = rrb_alloc_funct;
+}
+
+void
+pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_hands_off = 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
+		    pciio_slot_t slot,
+		    uint64_t subdevs)
+{
+    arbitrary_info_t        ainfo = 0;
+    char                    sdname[16];
+    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
+
+    sprintf(sdname, "pci/%d", slot);
+    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
+    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
+#if DEBUG
+	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
+		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
+#endif
+	return;
+    }
+    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+    if (ainfo == 0) {
+	uint64_t                *subdevp;
+
+	NEW(subdevp);
+	if (!subdevp) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+	*subdevp = subdevs;
+	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
+	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+	if (ainfo == (arbitrary_info_t) subdevp)
+	    return;
+	DEL(subdevp);
+	if (ainfo == (arbitrary_info_t) NULL) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+#if DEBUG
+	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
+		"\t%p\n", pconn_vhdl);
+#endif
+    }
+    *(uint64_t *) ainfo = subdevs;
+}
+
+
+#ifdef LATER
+
+#include <sys/idbg.h>
+#include <sys/idbgentry.h>
+
+char *pci_space[] = {"NONE", 
+		     "ROM",
+		     "IO",
+		     "",
+		     "MEM",
+		     "MEM32",
+		     "MEM64",
+		     "CFG",
+		     "WIN0",
+		     "WIN1",
+		     "WIN2",
+		     "WIN3",
+		     "WIN4",
+		     "WIN5",
+		     "",
+		     "BAD"};
+
+void
+idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
+{
+    pcibr_info_t	pcibr_info = pcibr_infoh[func];
+    char		name[MAXDEVNAME];
+    int			win;
+    
+    if (!pcibr_info)
+	return;
+    qprintf("Per-slot Function Info\n");
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(name, "%v", pcibr_info->f_vertex);
+#endif
+    qprintf("\tSlot Name : %s\n",name);
+    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
+    qprintf("Slot : %d ", pcibr_info->f_slot);
+    qprintf("Function : %d ", pcibr_info->f_func);
+    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
+    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    sprintf(name, "%v", pcibr_info->f_master);
+#endif
+    qprintf("\tBus provider : %s\n",name);
+    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
+    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
+	    pcibr_info->f_efunc,pcibr_info->f_einfo);
+    for(win = 0 ; win < 6 ; win++) 
+	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
+		win,pci_space[pcibr_info->f_window[win].w_space],
+		pcibr_info->f_window[win].w_base,
+		pcibr_info->f_window[win].w_size);
+
+    qprintf("\tRom base 0x%x size 0x%x\n", 
+	    pcibr_info->f_rbase,pcibr_info->f_rsize);
+
+    qprintf("\tInterrupt Bit Map\n");
+    qprintf("\t\tPCI Int#\tBridge Pin#\n");
+    for (win = 0 ; win < 4; win++)
+	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
+    qprintf("\n");
+}
+
+
+void
+idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
+{
+    pcibr_soft_slot_t	pss;
+    char		slot_conn_name[MAXDEVNAME];
+    int			func;
+
+    pss = &pcibr_soft->bs_slot[slot];
+    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
+    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
+    qprintf("\tHost Slot : %d\n",pss->host_slot);
+    sprintf(slot_conn_name, "%v", pss->slot_conn);
+    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
+    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
+    for (func = 0; func < pss->bss_ninfo; func++)
+	idbg_pss_func(pss->bss_infos,func);
+    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
+    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
+    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
+    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
+	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
+    
+    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
+	    "d32_base 0x%x d32_flags 0x%x\n",
+	    pss->bss_d64_base, pss->bss_d64_flags,
+	    pss->bss_d32_base, pss->bss_d32_flags);
+    
+    qprintf("\tExt ATEs active ? %s", 
+	    atomic_read(&pss->bss_ext_ates_active) ? "yes" : "no");
+    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
+    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
+
+    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
+	    pcibr_soft->bs_rrb_valid[slot],
+	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+		
+}
+
+int	ips = 0;
+
+void
+idbg_pss(pcibr_soft_t pcibr_soft)
+{
+    pciio_slot_t	slot;
+
+    
+    if (ips >= 0 && ips < 8)
+	idbg_pss_info(pcibr_soft,ips);
+    else if (ips < 0)
+	for (slot = 0; slot < 8; slot++) 
+	    idbg_pss_info(pcibr_soft,slot);
+    else
+	qprintf("Invalid ips %d\n",ips);
+}
+
+#endif /* LATER */
+
+int
+pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+	
+
+    return xtalk_dma_enabled(pcibr_soft->bs_conn);
+}
diff -Nru a/arch/ia64/sn/io/sn2/bte_error.c b/arch/ia64/sn/io/sn2/bte_error.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/bte_error.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,190 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000,2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/ioerror.h>
+#include <asm/sn/sn2/shubio.h>
+#include <asm/sn/bte.h>
+
+/************************************************************************
+ *									*
+ * 			 BTE ERROR RECOVERY				*
+ *									*
+ * Given a BTE error, the node causing the error must do the following: *
+ *    a) Clear all crbs relating to that BTE				*
+ *		1) Read CRBA value for crb in question			*
+ *		2) Mark CRB as VALID, store local physical 		*
+ *		   address known to be good in the address field	*
+ *		   (bte_notification_targ is a known good local		*
+ *		    address).						*
+ *		3) Write CRBA						*
+ *		4) Using ICCR, FLUSH the CRB, and wait for it to 	*
+ *		   complete.						*
+ *		... BTE BUSY bit should now be clear (or at least 	*
+ *		    should be after ALL CRBs associated with the 	*
+ *		    transfer are complete.				*
+ *									*
+ *    b) Re-enable BTE							*
+ *		1) Write IMEM with BTE Enable + XXX bits
+ *		2) Write IECLR with BTE clear bits
+ *		3) Clear IIDSR INT_SENT bits.
+ *									*
+ ************************************************************************/
+
+#ifdef BTE_ERROR
+// This routine is not called.  Yet.  It may be someday.  It probably
+// *should* be someday.  Until then, ifdef it out.
+bte_result_t
+bte_error_handler(bte_handle_t *bh)
+/*
+ * Function: 	bte_error_handler
+ * Purpose:	Process a BTE error after a transfer has failed.
+ * Parameters:	bh - bte handle of bte that failed.
+ * Returns:	The BTE error type.
+ * Notes:
+ */
+{
+    devfs_handle_t	hub_v;
+    hubinfo_t		hinfo;
+    int			il;
+    hubreg_t		iidsr, imem, ieclr;
+    hubreg_t		bte_status;
+
+    bh->bh_bte->bte_error_count++;
+
+    /* 
+     * Process any CRB logs - we know that the bte_context contains
+     * the BTE completion status, but to avoid a race with error
+     * processing, we force a call to pick up any CRB errors pending. 
+     * After this call, we know that we have any CRB errors related to 
+     * this BTE transfer in the context.
+     */
+    hub_v = cnodeid_to_vertex(bh->bh_bte->bte_cnode);
+    hubinfo_get(hub_v, &hinfo);
+    (void)hubiio_crb_error_handler(hub_v, hinfo);
+
+    /* Be sure BTE is stopped */
+
+    (void)BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_CTRL);
+
+    /*	
+     * Now clear up the rest of the error - be sure to hold crblock 
+     * to avoid race with other cpu on this node.
+     */
+    imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
+    ieclr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IECLR);
+    if (bh->bh_bte->bte_num == 0) {
+	imem |= IIO_IMEM_W0ESD | IIO_IMEM_B0ESD;
+	ieclr|= IECLR_BTE0;
+    } else {
+	imem |= IIO_IMEM_W0ESD | IIO_IMEM_B1ESD;
+	ieclr|= IECLR_BTE1;
+    }
+
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IMEM, imem);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, ieclr);
+
+    iidsr  = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR);
+    iidsr &= ~IIO_IIDSR_SENT_MASK;
+    iidsr |= IIO_IIDSR_ENB_MASK;
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, iidsr);
+    mutex_spinunlock(&hinfo->h_crblock, il);
+
+    bte_status = BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_STAT);
+    BTE_STORE(bh->bh_bte->bte_base, BTEOFF_STAT, bte_status & ~IBLS_BUSY);
+    ASSERT(!BTE_IS_BUSY(BTE_LOAD(bh->bh_bte->bte_base, BTEOFF_STAT)));
+
+    switch(bh->bh_error) {
+    case IIO_ICRB_ECODE_PERR:
+	return(BTEFAIL_POISON);
+    case IIO_ICRB_ECODE_WERR:
+	return(BTEFAIL_PROT);
+    case IIO_ICRB_ECODE_AERR:
+	return(BTEFAIL_ACCESS);
+    case IIO_ICRB_ECODE_TOUT:
+	return(BTEFAIL_TOUT);
+    case IIO_ICRB_ECODE_XTERR:
+	return(BTEFAIL_ERROR);
+    case IIO_ICRB_ECODE_DERR:
+	return(BTEFAIL_DIR);
+    case IIO_ICRB_ECODE_PWERR:
+    case IIO_ICRB_ECODE_PRERR:
+	/* NO BREAK */
+    default:
+	printk("BTE failure (%d) unexpected\n", 
+		bh->bh_error);
+	return(BTEFAIL_ERROR);
+    }
+}
+#endif // BTE_ERROR
+
+void
+bte_crb_error_handler(devfs_handle_t hub_v, int btenum, 
+		      int crbnum, ioerror_t *ioe)
+/*
+ * Function: 	bte_crb_error_handler
+ * Purpose:	Process a CRB for a specific HUB/BTE
+ * Parameters:	hub_v	- vertex of hub in HW graph
+ *		btenum	- bte number on hub (0 == a, 1 == b)
+ *		crbnum	- crb number being processed
+ * Notes: 
+ *	This routine assumes serialization at a higher level. A CRB 
+ *	should not be processed more than once. The error recovery 
+ *	follows the following sequence - if you change this, be real
+ *	sure about what you are doing. 
+ *
+ */
+{
+        hubinfo_t	hinfo;
+	icrba_t		crba; 
+	icrbb_t		crbb; 
+	nasid_t		n;
+
+	hubinfo_get(hub_v, &hinfo);
+
+
+	n = hinfo->h_nasid;
+	
+	/* Step 1 */
+	crba.ii_icrb0_a_regval = REMOTE_HUB_L(n, IIO_ICRB_A(crbnum));
+	crbb.ii_icrb0_b_regval = REMOTE_HUB_L(n, IIO_ICRB_B(crbnum));
+
+
+	/* Zero error and error code to prevent error_dump complaining
+	 * about these CRBs. 
+	 */
+	crbb.b_error=0;
+	crbb.b_ecode=0;
+
+	/* Step 2 */
+	REMOTE_HUB_S(n, IIO_ICRB_A(crbnum), crba.ii_icrb0_a_regval);
+	/* Step 3 */
+	REMOTE_HUB_S(n, IIO_ICCR, 
+		     IIO_ICCR_PENDING | IIO_ICCR_CMD_FLUSH | crbnum);
+	while (REMOTE_HUB_L(n, IIO_ICCR) & IIO_ICCR_PENDING)
+	    ;
+}
+
diff -Nru a/arch/ia64/sn/io/sn2/ml_SN_intr.c b/arch/ia64/sn/io/sn2/ml_SN_intr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/ml_SN_intr.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,469 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+/*
+ * intr.c-
+ *	This file contains all of the routines necessary to set up and
+ *	handle interrupts on an IPXX board.
+ */
+
+#ident  "$Revision: 1.167 $"
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/interrupt.h>
+#include <asm/smp.h>
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/sn2/shub_mmr_t.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+
+extern irqpda_t	*irqpdaindr[];
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+extern nasid_t master_nasid;
+
+//  Initialize some shub registers for interrupts, both IO and error.
+
+void
+intr_init_vecblk( nodepda_t *npda,
+		cnodeid_t node,
+		int sn)
+{
+	int 			nasid = cnodeid_to_nasid(node);
+	nasid_t			console_nasid;
+	sh_ii_int0_config_u_t	ii_int_config;
+	cpuid_t			cpu;
+	cpuid_t			cpu0, cpu1;
+	nodepda_t		*lnodepda;
+	sh_ii_int0_enable_u_t	ii_int_enable;
+	sh_local_int0_config_u_t	local_int_config;
+	sh_local_int0_enable_u_t	local_int_enable;
+	sh_fsb_system_agent_config_u_t	fsb_system_agent;
+	sh_int_node_id_config_u_t	node_id_config;
+	int is_console;
+
+	console_nasid = get_console_nasid();
+	if (console_nasid < 0) {
+		console_nasid = master_nasid;
+	}
+
+	is_console = nasid == console_nasid;
+
+	if (is_headless_node(node) ) {
+		int cnode;
+		struct ia64_sal_retval ret_stuff;
+
+		// retarget all interrupts on this node to the master node.
+		node_id_config.sh_int_node_id_config_regval = 0;
+		node_id_config.sh_int_node_id_config_s.node_id = master_nasid;
+		node_id_config.sh_int_node_id_config_s.id_sel = 1;
+		HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_INT_NODE_ID_CONFIG),
+			node_id_config.sh_int_node_id_config_regval);
+		cnode = nasid_to_cnodeid(master_nasid);
+		lnodepda = NODEPDA(cnode);
+		cpu = lnodepda->node_first_cpu;
+		cpu = cpu_physical_id(cpu);
+		SAL_CALL(ret_stuff, SN_SAL_REGISTER_CE, nasid, cpu, master_nasid,0,0,0,0);
+		if (ret_stuff.status < 0) {
+			printk("%s: SN_SAL_REGISTER_CE SAL_CALL failed\n",__FUNCTION__);
+		}
+	} else {
+		lnodepda = NODEPDA(node);
+		cpu = lnodepda->node_first_cpu;
+		cpu = cpu_physical_id(cpu);
+	}
+
+	// Get the physical id's of the cpu's on this node.
+	cpu0 = id_eid_to_cpu_physical_id(nasid, 0);
+	cpu1 = id_eid_to_cpu_physical_id(nasid, 1);
+
+	HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_ERROR_MASK), 0);
+	HUB_S( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_PI_CRBP_ERROR_MASK), 0);
+
+	// The II_INT_CONFIG register for cpu 0.
+	ii_int_config.sh_ii_int0_config_s.type = 0;
+	ii_int_config.sh_ii_int0_config_s.agt = 0;
+	ii_int_config.sh_ii_int0_config_s.pid = cpu0;
+	ii_int_config.sh_ii_int0_config_s.base = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_CONFIG),
+		ii_int_config.sh_ii_int0_config_regval);
+
+	// The II_INT_CONFIG register for cpu 1.
+	ii_int_config.sh_ii_int0_config_s.type = 0;
+	ii_int_config.sh_ii_int0_config_s.agt = 0;
+	ii_int_config.sh_ii_int0_config_s.pid = cpu1;
+	ii_int_config.sh_ii_int0_config_s.base = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_CONFIG),
+		ii_int_config.sh_ii_int0_config_regval);
+
+	// Enable interrupts for II_INT0 and 1.
+	ii_int_enable.sh_ii_int0_enable_s.ii_enable = 1;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT0_ENABLE),
+		ii_int_enable.sh_ii_int0_enable_regval);
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_II_INT1_ENABLE),
+		ii_int_enable.sh_ii_int0_enable_regval);
+
+	// init error regs
+	// LOCAL_INT0 is for the UART only.
+
+	local_int_config.sh_local_int0_config_s.type = 0;
+	local_int_config.sh_local_int0_config_s.agt = 0;
+	local_int_config.sh_local_int0_config_s.pid = cpu;
+	local_int_config.sh_local_int0_config_s.base = 0;
+	local_int_config.sh_local_int0_config_s.idx = SGI_UART_VECTOR;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	// LOCAL_INT1 is for all hardware errors.
+	// It will send a BERR, which will result in an MCA.
+	local_int_config.sh_local_int0_config_s.idx = 0;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	// Clear the LOCAL_INT_ENABLE register.
+	local_int_enable.sh_local_int0_enable_regval = 0;
+
+	if (is_console) {
+		// Enable the UART interrupt.  Only applies to the console nasid.
+		local_int_enable.sh_local_int0_enable_s.uart_int = 1;
+
+		HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT0_ENABLE),
+			local_int_enable.sh_local_int0_enable_regval);
+	}
+
+	// Enable all the error interrupts.
+	local_int_enable.sh_local_int0_enable_s.uart_int = 0;
+	local_int_enable.sh_local_int0_enable_s.pi_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.lb_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.ii_hw_int = 1;
+	local_int_enable.sh_local_int0_enable_s.pi_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_uce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.system_shutdown_int = 1;
+	local_int_enable.sh_local_int0_enable_s.l1_nmi_int = 1;
+	local_int_enable.sh_local_int0_enable_s.stop_clock = 1;
+
+
+	// Send BERR, rather than an interrupt, for shub errors.
+	local_int_config.sh_local_int0_config_s.agt = 1;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT1_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	// Make sure BERR is enabled.
+	fsb_system_agent.sh_fsb_system_agent_config_regval = 
+		HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG) );
+	fsb_system_agent.sh_fsb_system_agent_config_s.berr_assert_en = 1;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_FSB_SYSTEM_AGENT_CONFIG),
+		fsb_system_agent.sh_fsb_system_agent_config_regval);
+
+	// Set LOCAL_INT2 to field CEs
+
+	local_int_enable.sh_local_int0_enable_regval = 0;
+
+	local_int_config.sh_local_int0_config_s.agt = 0;
+	local_int_config.sh_local_int0_config_s.idx = SGI_SHUB_ERROR_VECTOR;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_CONFIG),
+		local_int_config.sh_local_int0_config_regval);
+
+	local_int_enable.sh_local_int0_enable_s.pi_ce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.md_ce_int = 1;
+	local_int_enable.sh_local_int0_enable_s.xn_ce_int = 1;
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT2_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	// Make sure all the rest of the LOCAL_INT regs are disabled.
+	local_int_enable.sh_local_int0_enable_regval = 0;
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT3_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT4_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_LOCAL_INT5_ENABLE),
+		local_int_enable.sh_local_int0_enable_regval);
+
+}
+
+// (Un)Reserve an irq on this cpu.
+
+static int
+do_intr_reserve_level(cpuid_t cpu,
+			int bit,
+			int reserve)
+{
+	int i;
+	irqpda_t	*irqs = irqpdaindr[cpu];
+
+	if (reserve) {
+		if (bit < 0) {
+			for (i = IA64_SN2_FIRST_DEVICE_VECTOR; i <= IA64_SN2_LAST_DEVICE_VECTOR; i++) {
+				if (irqs->irq_flags[i] == 0) {
+					bit = i;
+					break;
+				}
+			}
+		}
+		if (bit < 0) {
+			return -1;
+		}
+		if (irqs->irq_flags[bit] & SN2_IRQ_RESERVED) {
+			return -1;
+		} else {
+			irqs->num_irq_used++;
+			irqs->irq_flags[bit] |= SN2_IRQ_RESERVED;
+			return bit;
+		}
+	} else {
+		if (irqs->irq_flags[bit] & SN2_IRQ_RESERVED) {
+			irqs->num_irq_used--;
+			irqs->irq_flags[bit] &= ~SN2_IRQ_RESERVED;
+			return bit;
+		} else {
+			return -1;
+		}
+	}
+}
+
+int
+intr_reserve_level(cpuid_t cpu,
+		int bit,
+		int resflags,
+		devfs_handle_t owner_dev,
+		char *name)
+{
+	return(do_intr_reserve_level(cpu, bit, 1));
+}
+
+void
+intr_unreserve_level(cpuid_t cpu,
+		int bit)
+{
+	(void)do_intr_reserve_level(cpu, bit, 0);
+}
+
+// Mark an irq on this cpu as (dis)connected.
+
+static int
+do_intr_connect_level(cpuid_t cpu,
+			int bit,
+			int connect)
+{
+	irqpda_t	*irqs = irqpdaindr[cpu];
+
+	if (connect) {
+		if (irqs->irq_flags[bit] & SN2_IRQ_CONNECTED) {
+			return -1;
+		} else {
+			irqs->irq_flags[bit] |= SN2_IRQ_CONNECTED;
+			return bit;
+		}
+	} else {
+		if (irqs->irq_flags[bit] & SN2_IRQ_CONNECTED) {
+			irqs->irq_flags[bit] &= ~SN2_IRQ_CONNECTED;
+			return bit;
+		} else {
+			return -1;
+		}
+	}
+	return(bit);
+}
+
+int
+intr_connect_level(cpuid_t cpu,
+		int bit,
+		ilvl_t is,
+		intr_func_t intr_prefunc)
+{
+	return(do_intr_connect_level(cpu, bit, 1));
+}
+
+int
+intr_disconnect_level(cpuid_t cpu,
+		int bit)
+{
+	return(do_intr_connect_level(cpu, bit, 0));
+}
+
+// Choose a cpu on this node.
+// We choose the one with the least number of int's assigned to it.
+
+static cpuid_t
+do_intr_cpu_choose(cnodeid_t cnode) {
+	cpuid_t		cpu, best_cpu = CPU_NONE;
+	int		slice, min_count = 1000;
+	irqpda_t	*irqs;
+
+	for (slice = 0; slice < CPUS_PER_NODE; slice++) {
+		int intrs;
+
+		cpu = cnode_slice_to_cpuid(cnode, slice);
+		if (cpu == CPU_NONE) {
+			continue;
+		}
+
+		if (!cpu_enabled(cpu)) {
+			continue;
+		}
+
+		irqs = irqpdaindr[cpu];
+		intrs = irqs->num_irq_used;
+
+		if (min_count > intrs) {
+			min_count = intrs;
+			best_cpu = cpu;
+		}
+	}
+	return best_cpu;
+}
+
+static cpuid_t
+intr_cpu_choose_from_node(cnodeid_t cnode)
+{
+	return(do_intr_cpu_choose(cnode));
+}
+
+// See if we can use this cpu/vect.
+
+static cpuid_t
+intr_bit_reserve_test(cpuid_t cpu,
+			int favor_subnode,
+			cnodeid_t cnode,
+			int req_bit,
+			int resflags,
+			devfs_handle_t owner_dev,
+			char *name,
+			int *resp_bit)
+{
+	ASSERT( (cpu == CPU_NONE) || (cnode == CNODEID_NONE) );
+
+	if (cnode != CNODEID_NONE) {
+		cpu = intr_cpu_choose_from_node(cnode);
+	}
+
+	if (cpu != CPU_NONE) {
+		*resp_bit = do_intr_reserve_level(cpu, req_bit, 1);
+		if (*resp_bit >= 0) {
+			return(cpu);
+		}
+	}
+	return CPU_NONE;
+}
+
+// Find the node to assign for this interrupt.
+
+cpuid_t
+intr_heuristic(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		int	req_bit,
+		int resflags,
+		devfs_handle_t owner_dev,
+		char *name,
+		int *resp_bit)
+{
+	cpuid_t		cpuid;
+	cnodeid_t	candidate = -1;
+	devfs_handle_t	pconn_vhdl;
+	pcibr_soft_t	pcibr_soft;
+
+/* SN2 + pcibr addressing limitation */
+/* Due to this limitation, all interrupts from a given bridge must go to the name node.*/
+/* This limitation does not exist on PIC. */
+
+	if ( (hwgraph_edge_get(dev, EDGE_LBL_PCI, &pconn_vhdl) == GRAPH_SUCCESS) &&
+		( (pcibr_soft = pcibr_soft_get(pconn_vhdl) ) != NULL) ) {
+			if (pcibr_soft->bsi_err_intr) {
+				candidate = cpuid_to_cnodeid( ((hub_intr_t)pcibr_soft->bsi_err_intr)->i_cpuid);
+			}
+	}
+
+	if (candidate >= 0) {
+		// The node was chosen already when we assigned the error interrupt.
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+						0,
+						candidate,
+						req_bit,
+						0,
+						owner_dev,
+						name,
+						resp_bit);
+	} else {
+		// Need to choose one.  Try the controlling c-brick first.
+		cpuid = intr_bit_reserve_test(CPU_NONE,
+						0,
+						master_node_get(dev),
+						req_bit,
+						0,
+						owner_dev,
+						name,
+						resp_bit);
+	}
+
+	if (cpuid != CPU_NONE) {
+		return cpuid;
+	}
+
+	if (candidate >= 0) {
+		printk("Cannot target interrupt to target node (%d).\n",candidate);
+		return CPU_NONE;
+	} else {
+		printk("Cannot target interrupt to closest node (%d) 0x%p\n",
+			master_node_get(dev), (void *)owner_dev);
+	}
+
+	// We couldn't put it on the closest node.  Try to find another one.
+	// Do a stupid round-robin assignment of the node.
+
+	{
+		static cnodeid_t last_node = -1;
+		if (last_node >= numnodes) last_node = 0;
+		for (candidate = last_node + 1; candidate != last_node; candidate++) {
+			if (candidate == numnodes) candidate = 0;
+			cpuid = intr_bit_reserve_test(CPU_NONE,
+							0,
+							candidate,
+							req_bit,
+							0,
+							owner_dev,
+							name,
+							resp_bit);
+			if (cpuid != CPU_NONE) {
+				return cpuid;
+			}
+		}
+	}
+
+	printk("cannot target interrupt: 0x%p\n",(void *)owner_dev);
+	return CPU_NONE;
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_ate.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,454 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+uint64_t atealloc(struct map *mp, size_t size);
+void atefree(struct map *mp, size_t size, uint64_t a);
+void atemapfree(struct map *mp);
+struct map *atemapalloc(uint64_t mapsiz);
+
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+
+#ifdef LATER
+#if (PCIBR_FREEZE_TIME) || PCIBR_ATE_DEBUG
+LOCAL struct reg_desc   ate_bits[] =
+{
+    {0xFFFF000000000000ull, -48, "RMF", "%x"},
+    {~(IOPGSIZE - 1) &			/* may trim off some low bits */
+     0x0000FFFFFFFFF000ull, 0, "XIO", "%x"},
+    {0x0000000000000F00ull, -8, "port", "%x"},
+    {0x0000000000000010ull, 0, "Barrier"},
+    {0x0000000000000008ull, 0, "Prefetch"},
+    {0x0000000000000004ull, 0, "Precise"},
+    {0x0000000000000002ull, 0, "Coherent"},
+    {0x0000000000000001ull, 0, "Valid"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+#ifndef LOCAL
+#define LOCAL           static
+#endif
+
+/*
+ * functions
+ */
+int               pcibr_init_ext_ate_ram(bridge_t *);
+int               pcibr_ate_alloc(pcibr_soft_t, int);
+void              pcibr_ate_free(pcibr_soft_t, int, int);
+bridge_ate_t      pcibr_flags_to_ate(unsigned);
+bridge_ate_p      pcibr_ate_addr(pcibr_soft_t, int);
+unsigned 	  ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   			unsigned *freeze_time_ptr,
+#endif
+	   			unsigned *cmd_regs);
+void 	  ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+void ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 			int ate_index,
+#if PCIBR_FREEZE_TIME
+	 			bridge_ate_t ate,
+	 			int ate_total,
+	 			unsigned freeze_time_start,
+#endif
+	 			unsigned *cmd_regs,
+	 			unsigned s);
+
+
+/* Convert from ssram_bits in control register to number of SSRAM entries */
+#define ATE_NUM_ENTRIES(n) _ate_info[n]
+
+/* Possible choices for number of ATE entries in Bridge's SSRAM */
+LOCAL int               _ate_info[] =
+{
+    0,					/* 0 entries */
+    8 * 1024,				/* 8K entries */
+    16 * 1024,				/* 16K entries */
+    64 * 1024				/* 64K entries */
+};
+
+#define ATE_NUM_SIZES (sizeof(_ate_info) / sizeof(int))
+#define ATE_PROBE_VALUE 0x0123456789abcdefULL
+
+/*
+ * Determine the size of this bridge's external mapping SSRAM, and set
+ * the control register appropriately to reflect this size, and initialize
+ * the external SSRAM.
+ */
+int
+pcibr_init_ext_ate_ram(bridge_t *bridge)
+{
+    int                     largest_working_size = 0;
+    int                     num_entries, entry;
+    int                     i, j;
+    bridgereg_t             old_enable, new_enable;
+    int                     s;
+
+    /* Probe SSRAM to determine its size. */
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+    bridge->b_int_enable = new_enable;
+
+    for (i = 1; i < ATE_NUM_SIZES; i++) {
+	/* Try writing a value */
+	bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] = ATE_PROBE_VALUE;
+
+	/* Guard against wrap */
+	for (j = 1; j < i; j++)
+	    bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(j) - 1] = 0;
+
+	/* See if value was written */
+	if (bridge->b_ext_ate_ram[ATE_NUM_ENTRIES(i) - 1] == ATE_PROBE_VALUE)
+	    largest_working_size = i;
+    }
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * ensure that we write and read without any interruption.
+     * The read following the write is required for the Bridge war
+     */
+
+    s = splhi();
+    bridge->b_wid_control = (bridge->b_wid_control
+	& ~BRIDGE_CTRL_SSRAM_SIZE_MASK)
+	| BRIDGE_CTRL_SSRAM_SIZE(largest_working_size);
+    bridge->b_wid_control;		/* inval addr bug war */
+    splx(s);
+
+    num_entries = ATE_NUM_ENTRIES(largest_working_size);
+
+#if PCIBR_ATE_DEBUG
+    if (num_entries)
+	printk("bridge at 0x%x: clearing %d external ATEs\n", bridge, num_entries);
+    else
+	printk("bridge at 0x%x: no external ATE RAM found\n", bridge);
+#endif
+
+    /* Initialize external mapping entries */
+    for (entry = 0; entry < num_entries; entry++)
+	bridge->b_ext_ate_ram[entry] = 0;
+
+    return (num_entries);
+}
+
+/*
+ * Allocate "count" contiguous Bridge Address Translation Entries
+ * on the specified bridge to be used for PCI to XTALK mappings.
+ * Indices in rm map range from 1..num_entries.  Indicies returned
+ * to caller range from 0..num_entries-1.
+ *
+ * Return the start index on success, -1 on failure.
+ */
+int
+pcibr_ate_alloc(pcibr_soft_t pcibr_soft, int count)
+{
+    int                     index = 0;
+
+    index = (int) rmalloc(pcibr_soft->bs_int_ate_map, (size_t) count);
+
+    if (!index && pcibr_soft->bs_ext_ate_map)
+	index = (int) rmalloc(pcibr_soft->bs_ext_ate_map, (size_t) count);
+
+    /* rmalloc manages resources in the 1..n
+     * range, with 0 being failure.
+     * pcibr_ate_alloc manages resources
+     * in the 0..n-1 range, with -1 being failure.
+     */
+    return index - 1;
+}
+
+void
+pcibr_ate_free(pcibr_soft_t pcibr_soft, int index, int count)
+/* Who says there's no such thing as a free meal? :-) */
+{
+    /* note the "+1" since rmalloc handles 1..n but
+     * we start counting ATEs at zero.
+     */
+    rmfree((index < pcibr_soft->bs_int_ate_size)
+	   ? pcibr_soft->bs_int_ate_map
+	   : pcibr_soft->bs_ext_ate_map,
+	   count, index + 1);
+}
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Address Translation Entry attribute bits.
+ */
+bridge_ate_t
+pcibr_flags_to_ate(unsigned flags)
+{
+    bridge_ate_t            attributes;
+
+    /* default if nothing specified:
+     * NOBARRIER
+     * NOPREFETCH
+     * NOPRECISE
+     * COHERENT
+     * Plus the valid bit
+     */
+    attributes = ATE_CO | ATE_V;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~ATE_BAR;		/* no barrier */
+	attributes |= ATE_PREF;		/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= ATE_BAR;		/* barrier bit on */
+	attributes &= ~ATE_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= ATE_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~ATE_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= ATE_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~ATE_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= ATE_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~ATE_PREC;
+
+    return (attributes);
+}
+
+/*
+ * Setup an Address Translation Entry as specified.  Use either the Bridge
+ * internal maps or the external map RAM, as appropriate.
+ */
+bridge_ate_p
+pcibr_ate_addr(pcibr_soft_t pcibr_soft,
+	       int ate_index)
+{
+    bridge_t *bridge = pcibr_soft->bs_base;
+
+    return (ate_index < pcibr_soft->bs_int_ate_size)
+	? &(bridge->b_int_ate_ram[ate_index].wr)
+	: &(bridge->b_ext_ate_ram[ate_index]);
+}
+
+/* We are starting to get more complexity
+ * surrounding writing ATEs, so pull
+ * the writing code into this new function.
+ */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif
+
+unsigned
+ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   unsigned *freeze_time_ptr,
+#endif
+	   unsigned *cmd_regs)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+#ifdef LATER
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+#endif
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+    int                     slot;
+
+    unsigned long           s;
+    unsigned                cmd_reg;
+    volatile unsigned      *cmd_lwa;
+    unsigned                cmd_lwd;
+
+    if (!ext_ates)
+	return 0;
+
+    /* Bridge Hardware Bug WAR #484930:
+     * Bridge can't handle updating External ATEs
+     * while DMA is occuring that uses External ATEs,
+     * even if the particular ATEs involved are disjoint.
+     */
+
+    /* need to prevent anyone else from
+     * unfreezing the grant while we
+     * are working; also need to prevent
+     * this thread from being interrupted
+     * to keep PCI grant freeze time
+     * at an absolute minimum.
+     */
+    s = pcibr_lock(pcibr_soft);
+
+#ifdef LATER
+    /* just in case pcibr_dmamap_done was not called */
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+	xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+    }
+#endif	/* LATER */
+#if PCIBR_FREEZE_TIME
+    *freeze_time_ptr = get_timestamp();
+#endif
+
+    cmd_lwa = 0;
+    for (slot = 0; slot < 8; ++slot)
+	if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+	    cmd_reg = pcibr_soft->
+		bs_slot[slot].
+		bss_cmd_shadow;
+	    if (cmd_reg & PCI_CMD_BUS_MASTER) {
+		cmd_lwa = pcibr_soft->
+		    bs_slot[slot].
+		    bss_cmd_pointer;
+		cmd_lwd = cmd_reg ^ PCI_CMD_BUS_MASTER;
+		cmd_lwa[0] = cmd_lwd;
+	    }
+	    cmd_regs[slot] = cmd_reg;
+	} else
+	    cmd_regs[slot] = 0;
+
+    if (cmd_lwa) {
+	    bridge_t	*bridge = pcibr_soft->bs_base;
+
+	    /* Read the last master bit that has been cleared. This PIO read
+	     * on the PCI bus is to ensure the completion of any DMAs that
+	     * are due to bus requests issued by PCI devices before the
+	     * clearing of master bits.
+	     */
+	    cmd_lwa[0];
+
+	    /* Flush all the write buffers in the bridge */
+	    for (slot = 0; slot < 8; ++slot)
+		    if (atomic_read(&pcibr_soft->bs_slot[slot].bss_ext_ates_active)) {
+			    /* Flush the write buffer associated with this
+			     * PCI device which might be using dma map RAM.
+			     */
+			    bridge->b_wr_req_buf[slot].reg;
+		    }
+    }
+    return s;
+}
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+
+void
+ate_write(bridge_ate_p ate_ptr,
+	  int ate_count,
+	  bridge_ate_t ate)
+{
+    while (ate_count-- > 0) {
+	*ate_ptr++ = ate;
+	ate += IOPGSIZE;
+    }
+}
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+void
+ate_thaw(pcibr_dmamap_t pcibr_dmamap,
+	 int ate_index,
+#if PCIBR_FREEZE_TIME
+	 bridge_ate_t ate,
+	 int ate_total,
+	 unsigned freeze_time_start,
+#endif
+	 unsigned *cmd_regs,
+	 unsigned s)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    int                     dma_slot = pcibr_dmamap->bd_slot;
+    int                     slot;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     ext_ates = pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM;
+
+    unsigned                cmd_reg;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+    static unsigned         max_freeze_time = 0;
+    static unsigned         max_ate_total;
+#endif
+
+    if (!ext_ates)
+	return;
+
+    /* restore cmd regs */
+    for (slot = 0; slot < 8; ++slot)
+	if ((cmd_reg = cmd_regs[slot]) & PCI_CMD_BUS_MASTER)
+	    bridge->b_type0_cfg_dev[slot].l[PCI_CFG_COMMAND / 4] = cmd_reg;
+
+    pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_BUSY;
+    atomic_inc(&(pcibr_soft->bs_slot[dma_slot]. bss_ext_ates_active));
+
+#if PCIBR_FREEZE_TIME
+    freeze_time = get_timestamp() - freeze_time_start;
+
+    if ((max_freeze_time < freeze_time) ||
+	(max_ate_total < ate_total)) {
+	if (max_freeze_time < freeze_time)
+	    max_freeze_time = freeze_time;
+	if (max_ate_total < ate_total)
+	    max_ate_total = ate_total;
+	pcibr_unlock(pcibr_soft, s);
+	printk("%s: pci freeze time %d usec for %d ATEs\n"
+		"\tfirst ate: %R\n",
+		pcibr_soft->bs_name,
+		freeze_time * 1000 / 1250,
+		ate_total,
+		ate, ate_bits);
+    } else
+#endif
+	pcibr_unlock(pcibr_soft, s);
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_config.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,143 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+extern pcibr_info_t      pcibr_info_get(devfs_handle_t);
+
+uint64_t          pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+uint64_t          do_pcibr_config_get(cfg_p, unsigned, unsigned);
+void              pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+void              do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+#define	CB(b,r)	(((volatile uint8_t *) cfgbase)[(r)^3])
+#define	CS(b,r)	(((volatile uint16_t *) cfgbase)[((r)/2)^1])
+#define	CW(b,r)	(((volatile uint32_t *) cfgbase)[(r)/4])
+
+
+cfg_p
+pcibr_config_addr(devfs_handle_t conn,
+		  unsigned reg)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_slot_t            pciio_slot;
+    pciio_function_t        pciio_func;
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    cfg_p                   cfgbase = (cfg_p)0;
+
+    pcibr_info = pcibr_info_get(conn);
+
+    pciio_slot = pcibr_info->f_slot;
+    if (pciio_slot == PCIIO_SLOT_NONE)
+	pciio_slot = PCI_TYPE1_SLOT(reg);
+
+    pciio_func = pcibr_info->f_func;
+    if (pciio_func == PCIIO_FUNC_NONE)
+	pciio_func = PCI_TYPE1_FUNC(reg);
+
+    pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    bridge = pcibr_soft->bs_base;
+
+    cfgbase = bridge->b_type0_cfg_dev[pciio_slot].f[pciio_func].l;
+
+    return cfgbase;
+}
+
+uint64_t
+pcibr_config_get(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size)
+{
+    return do_pcibr_config_get(pcibr_config_addr(conn, reg),
+			       PCI_TYPE1_REG(reg), size);
+}
+
+uint64_t
+do_pcibr_config_get(
+		       cfg_p cfgbase,
+		       unsigned reg,
+		       unsigned size)
+{
+    unsigned                value;
+
+    value = CW(cfgbase, reg);
+
+    if (reg & 3)
+	value >>= 8 * (reg & 3);
+    if (size < 4)
+	value &= (1 << (8 * size)) - 1;
+    return value;
+}
+
+void
+pcibr_config_set(devfs_handle_t conn,
+		 unsigned reg,
+		 unsigned size,
+		 uint64_t value)
+{
+    do_pcibr_config_set(pcibr_config_addr(conn, reg),
+			PCI_TYPE1_REG(reg), size, value);
+}
+
+void
+do_pcibr_config_set(cfg_p cfgbase,
+		    unsigned reg,
+		    unsigned size,
+		    uint64_t value)
+{
+    switch (size) {
+    case 1:
+	CB(cfgbase, reg) = value;
+	break;
+    case 2:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 1) = value >> 8;
+	} else
+	    CS(cfgbase, reg) = value;
+	break;
+    case 3:
+	if (reg & 1) {
+	    CB(cfgbase, reg) = value;
+	    CS(cfgbase, (reg + 1)) = value >> 8;
+	} else {
+	    CS(cfgbase, reg) = value;
+	    CB(cfgbase, reg + 2) = value >> 16;
+	}
+	break;
+
+    case 4:
+	CW(cfgbase, reg) = value;
+	break;
+    }
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_dvr.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,4279 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+/*
+ * Macros related to the Lucent USS 302/312 usb timeout workaround.  It
+ * appears that if the lucent part can get into a retry loop if it sees a
+ * DAC on the bus during a pio read retry.  The loop is broken after about
+ * 1ms, so we need to set up bridges holding this part to allow at least
+ * 1ms for pio.
+ */
+
+#define USS302_TIMEOUT_WAR
+
+#ifdef USS302_TIMEOUT_WAR
+#define LUCENT_USBHC_VENDOR_ID_NUM	0x11c1
+#define LUCENT_USBHC302_DEVICE_ID_NUM	0x5801
+#define LUCENT_USBHC312_DEVICE_ID_NUM	0x5802
+#define USS302_BRIDGE_TIMEOUT_HLD	4
+#endif
+
+int                     pcibr_devflag = D_MP;
+
+/*
+ * This is the file operation table for the pcibr driver.
+ * As each of the functions are implemented, put the
+ * appropriate function name below.
+ */
+struct file_operations pcibr_fops = {
+	owner:  THIS_MODULE,
+	llseek: NULL,
+	read: NULL,
+	write: NULL,
+	readdir: NULL,
+	poll: NULL,
+	ioctl: NULL,
+	mmap: NULL,
+	open: NULL,
+	flush: NULL,
+	release: NULL,
+	fsync: NULL,
+	fasync: NULL,
+	lock: NULL,
+	readv: NULL,
+	writev: NULL
+};
+
+#ifdef LATER
+
+#if PCIBR_ATE_DEBUG
+static struct reg_values ssram_sizes[] =
+{
+    {BRIDGE_CTRL_SSRAM_512K, "512k"},
+    {BRIDGE_CTRL_SSRAM_128K, "128k"},
+    {BRIDGE_CTRL_SSRAM_64K, "64k"},
+    {BRIDGE_CTRL_SSRAM_1K, "1k"},
+    {0}
+};
+
+static struct reg_desc   control_bits[] =
+{
+    {BRIDGE_CTRL_FLASH_WR_EN, 0, "FLASH_WR_EN"},
+    {BRIDGE_CTRL_EN_CLK50, 0, "EN_CLK50"},
+    {BRIDGE_CTRL_EN_CLK40, 0, "EN_CLK40"},
+    {BRIDGE_CTRL_EN_CLK33, 0, "EN_CLK33"},
+    {BRIDGE_CTRL_RST_MASK, -24, "RST", "%x"},
+    {BRIDGE_CTRL_IO_SWAP, 0, "IO_SWAP"},
+    {BRIDGE_CTRL_MEM_SWAP, 0, "MEM_SWAP"},
+    {BRIDGE_CTRL_PAGE_SIZE, 0, "PAGE_SIZE"},
+    {BRIDGE_CTRL_SS_PAR_BAD, 0, "SS_PAR_BAD"},
+    {BRIDGE_CTRL_SS_PAR_EN, 0, "SS_PAR_EN"},
+    {BRIDGE_CTRL_SSRAM_SIZE_MASK, 0, "SSRAM_SIZE", 0, ssram_sizes},
+    {BRIDGE_CTRL_F_BAD_PKT, 0, "F_BAD_PKT"},
+    {BRIDGE_CTRL_LLP_XBAR_CRD_MASK, -12, "LLP_XBAR_CRD", "%d"},
+    {BRIDGE_CTRL_CLR_RLLP_CNT, 0, "CLR_RLLP_CNT"},
+    {BRIDGE_CTRL_CLR_TLLP_CNT, 0, "CLR_TLLP_CNT"},
+    {BRIDGE_CTRL_SYS_END, 0, "SYS_END"},
+
+    {BRIDGE_CTRL_BUS_SPEED_MASK, -4, "BUS_SPEED", "%d"},
+    {BRIDGE_CTRL_WIDGET_ID_MASK, 0, "WIDGET_ID", "%x"},
+    {0}
+};
+#endif
+#endif	/* LATER */
+
+/* kbrick widgetnum-to-bus layout */
+int p_busnum[MAX_PORT_NUM] = {                  /* widget#      */
+        0, 0, 0, 0, 0, 0, 0, 0,                 /* 0x0 - 0x7    */
+        2,                                      /* 0x8          */
+        1,                                      /* 0x9          */
+        0, 0,                                   /* 0xa - 0xb    */
+        5,                                      /* 0xc          */
+        6,                                      /* 0xd          */
+        4,                                      /* 0xe          */
+        3,                                      /* 0xf          */
+};
+
+/*
+ * Additional PIO spaces per slot are
+ * recorded in this structure.
+ */
+struct pciio_piospace_s {
+    pciio_piospace_t        next;       /* another space for this device */
+    char                    free;       /* 1 if free, 0 if in use               */
+    pciio_space_t           space;      /* Which space is in use                */
+    iopaddr_t               start;      /* Starting address of the PIO space    */
+    size_t                  count;      /* size of PIO space                    */
+};
+
+#if PCIBR_SOFT_LIST
+pcibr_list_p            pcibr_list = 0;
+#endif
+
+extern int              hwgraph_vertex_name_get(devfs_handle_t vhdl, char *buf, uint buflen);
+extern int              hub_device_flags_set(devfs_handle_t widget_dev, hub_widget_flags_t flags);
+extern long             atoi(register char *p);
+extern cnodeid_t        nodevertex_to_cnodeid(devfs_handle_t vhdl);
+extern void             *swap_ptr(void **loc, void *new);
+extern char             *dev_to_name(devfs_handle_t dev, char *buf, uint buflen);
+extern struct map       *atemapalloc(uint64_t);
+extern void             atefree(struct map *, size_t, uint64_t);
+extern void             atemapfree(struct map *);
+extern pciio_dmamap_t   get_free_pciio_dmamap(devfs_handle_t);
+extern void		free_pciio_dmamap(pcibr_dmamap_t);
+
+#define	ATE_WRITE()    ate_write(ate_ptr, ate_count, ate)
+#if PCIBR_FREEZE_TIME
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, &freeze_time, cmd_regs)
+#else
+#define	ATE_FREEZE()	s = ate_freeze(pcibr_dmamap, cmd_regs)
+#endif /* PCIBR_FREEZE_TIME */
+
+#if PCIBR_FREEZE_TIME
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, ate, ate_total, freeze_time, cmd_regs, s)
+#else
+#define	ATE_THAW()	ate_thaw(pcibr_dmamap, ate_index, cmd_regs, s)
+#endif
+
+
+/* =====================================================================
+ *    Function Table of Contents
+ *
+ *      The order of functions in this file has stopped
+ *      making much sense. We might want to take a look
+ *      at it some time and bring back some sanity, or
+ *      perhaps bust this file into smaller chunks.
+ */
+
+extern void              do_pcibr_rrb_clear(bridge_t *, int);
+extern void              do_pcibr_rrb_flush(bridge_t *, int);
+extern int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+extern int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+extern int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+extern int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+extern void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+extern int  		 pcibr_wrb_flush(devfs_handle_t);
+extern int               pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+extern int               pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+extern int               pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+extern void              pcibr_rrb_flush(devfs_handle_t);
+
+static int                pcibr_try_set_device(pcibr_soft_t, pciio_slot_t, unsigned, bridgereg_t);
+void                     pcibr_release_device(pcibr_soft_t, pciio_slot_t, bridgereg_t);
+
+extern void              pcibr_clearwidint(bridge_t *);
+extern void              pcibr_setwidint(xtalk_intr_t);
+
+void                     pcibr_init(void);
+int                      pcibr_attach(devfs_handle_t);
+int			 pcibr_detach(devfs_handle_t);
+int                      pcibr_open(devfs_handle_t *, int, int, cred_t *);
+int                      pcibr_close(devfs_handle_t, int, int, cred_t *);
+int                      pcibr_map(devfs_handle_t, vhandl_t *, off_t, size_t, uint);
+int                      pcibr_unmap(devfs_handle_t, vhandl_t *);
+int                      pcibr_ioctl(devfs_handle_t, int, void *, int, struct cred *, int *);
+
+void                     pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+
+extern int               pcibr_init_ext_ate_ram(bridge_t *);
+extern int               pcibr_ate_alloc(pcibr_soft_t, int);
+extern void              pcibr_ate_free(pcibr_soft_t, int, int);
+
+extern unsigned          ate_freeze(pcibr_dmamap_t pcibr_dmamap,
+#if PCIBR_FREEZE_TIME
+	   		 unsigned *freeze_time_ptr,
+#endif
+						unsigned *cmd_regs);
+extern void              ate_write(bridge_ate_p ate_ptr, int ate_count, bridge_ate_t ate);
+extern void              ate_thaw(pcibr_dmamap_t pcibr_dmamap, int ate_index,
+#if PCIBR_FREEZE_TIME
+	 				bridge_ate_t ate,
+	 				int ate_total,
+	 				unsigned freeze_time_start,
+#endif
+	 				unsigned *cmd_regs,
+	 				unsigned s);
+
+pcibr_info_t             pcibr_info_get(devfs_handle_t);
+
+static iopaddr_t         pcibr_addr_pci_to_xio(devfs_handle_t, pciio_slot_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+
+pcibr_piomap_t          pcibr_piomap_alloc(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, size_t, unsigned);
+void                    pcibr_piomap_free(pcibr_piomap_t);
+caddr_t                 pcibr_piomap_addr(pcibr_piomap_t, iopaddr_t, size_t);
+void                    pcibr_piomap_done(pcibr_piomap_t);
+caddr_t                 pcibr_piotrans_addr(devfs_handle_t, device_desc_t, pciio_space_t, iopaddr_t, size_t, unsigned);
+iopaddr_t               pcibr_piospace_alloc(devfs_handle_t, device_desc_t, pciio_space_t, size_t, size_t);
+void                    pcibr_piospace_free(devfs_handle_t, pciio_space_t, iopaddr_t, size_t);
+
+static iopaddr_t         pcibr_flags_to_d64(unsigned, pcibr_soft_t);
+extern bridge_ate_t     pcibr_flags_to_ate(unsigned);
+
+pcibr_dmamap_t          pcibr_dmamap_alloc(devfs_handle_t, device_desc_t, size_t, unsigned);
+void                    pcibr_dmamap_free(pcibr_dmamap_t);
+extern bridge_ate_p     pcibr_ate_addr(pcibr_soft_t, int);
+static iopaddr_t         pcibr_addr_xio_to_pci(pcibr_soft_t, iopaddr_t, size_t);
+iopaddr_t               pcibr_dmamap_addr(pcibr_dmamap_t, paddr_t, size_t);
+alenlist_t              pcibr_dmamap_list(pcibr_dmamap_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_done(pcibr_dmamap_t);
+cnodeid_t		pcibr_get_dmatrans_node(devfs_handle_t);
+iopaddr_t               pcibr_dmatrans_addr(devfs_handle_t, device_desc_t, paddr_t, size_t, unsigned);
+alenlist_t              pcibr_dmatrans_list(devfs_handle_t, device_desc_t, alenlist_t, unsigned);
+void                    pcibr_dmamap_drain(pcibr_dmamap_t);
+void                    pcibr_dmaaddr_drain(devfs_handle_t, paddr_t, size_t);
+void                    pcibr_dmalist_drain(devfs_handle_t, alenlist_t);
+iopaddr_t               pcibr_dmamap_pciaddr_get(pcibr_dmamap_t);
+
+extern unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+extern pcibr_intr_t     pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+extern void             pcibr_intr_free(pcibr_intr_t);
+extern void             pcibr_setpciint(xtalk_intr_t);
+extern int              pcibr_intr_connect(pcibr_intr_t);
+extern void             pcibr_intr_disconnect(pcibr_intr_t);
+
+extern devfs_handle_t     pcibr_intr_cpu_get(pcibr_intr_t);
+extern void             pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+extern void             pcibr_intr_func(intr_arg_t);
+
+extern void             print_bridge_errcmd(uint32_t, char *);
+
+extern void             pcibr_error_dump(pcibr_soft_t);
+extern uint32_t         pcibr_errintr_group(uint32_t);
+extern void	        pcibr_pioerr_check(pcibr_soft_t);
+extern void             pcibr_error_intr_handler(intr_arg_t);
+
+extern int              pcibr_addr_toslot(pcibr_soft_t, iopaddr_t, pciio_space_t *, iopaddr_t *, pciio_function_t *);
+extern void             pcibr_error_cleanup(pcibr_soft_t, int);
+extern void                    pcibr_device_disable(pcibr_soft_t, int);
+extern int              pcibr_pioerror(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_dmard_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_dmawr_error(pcibr_soft_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_error_handler(error_handler_arg_t, int, ioerror_mode_t, ioerror_t *);
+extern int              pcibr_error_devenable(devfs_handle_t, int);
+
+void                    pcibr_provider_startup(devfs_handle_t);
+void                    pcibr_provider_shutdown(devfs_handle_t);
+
+int                     pcibr_reset(devfs_handle_t);
+pciio_endian_t          pcibr_endian_set(devfs_handle_t, pciio_endian_t, pciio_endian_t);
+int                     pcibr_priority_bits_set(pcibr_soft_t, pciio_slot_t, pciio_priority_t);
+pciio_priority_t        pcibr_priority_set(devfs_handle_t, pciio_priority_t);
+int                     pcibr_device_flags_set(devfs_handle_t, pcibr_device_flags_t);
+
+extern cfg_p            pcibr_config_addr(devfs_handle_t, unsigned);
+extern uint64_t         pcibr_config_get(devfs_handle_t, unsigned, unsigned);
+extern void             pcibr_config_set(devfs_handle_t, unsigned, unsigned, uint64_t);
+extern void             do_pcibr_config_set(cfg_p, unsigned, unsigned, uint64_t);
+
+extern pcibr_hints_t    pcibr_hints_get(devfs_handle_t, int);
+extern void             pcibr_hints_fix_rrbs(devfs_handle_t);
+extern void             pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+extern void	 	pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+extern void             pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+extern void             pcibr_hints_handsoff(devfs_handle_t);
+extern void             pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+
+#ifdef BRIDGE_B_DATACORR_WAR
+extern int              ql_bridge_rev_b_war(devfs_handle_t);
+extern int              bridge_rev_b_data_check_disable;
+char                   *rev_b_datacorr_warning =
+"***************************** WARNING! ******************************\n";
+char                   *rev_b_datacorr_mesg =
+"UNRECOVERABLE IO LINK ERROR. CONTACT SERVICE PROVIDER\n";
+#endif
+
+extern int		pcibr_slot_reset(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_info_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_info_free(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_addr_space_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_device_init(devfs_handle_t, pciio_slot_t);
+extern int		pcibr_slot_guest_info_init(devfs_handle_t,pciio_slot_t);
+extern int		pcibr_slot_call_device_attach(devfs_handle_t, pciio_slot_t, int);
+extern int		pcibr_slot_call_device_detach(devfs_handle_t, pciio_slot_t, int);
+extern int              pcibr_slot_attach(devfs_handle_t, pciio_slot_t, int, char *, int *);
+extern int              pcibr_slot_detach(devfs_handle_t, pciio_slot_t, int);
+extern int 		pcibr_is_slot_sys_critical(devfs_handle_t, pciio_slot_t);
+
+#ifdef LATER
+extern int		pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t);
+extern int		pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t);
+extern int		pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t);
+#endif
+
+extern int		pcibr_slot_initial_rrb_alloc(devfs_handle_t, pciio_slot_t);
+extern int		pcibr_initial_rrb(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+
+
+
+/* =====================================================================
+ *    Device(x) register management
+ */
+
+/* pcibr_try_set_device: attempt to modify Device(x)
+ * for the specified slot on the specified bridge
+ * as requested in flags, limited to the specified
+ * bits. Returns which BRIDGE bits were in conflict,
+ * or ZERO if everything went OK.
+ *
+ * Caller MUST hold pcibr_lock when calling this function.
+ */
+static int
+pcibr_try_set_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     unsigned flags,
+		     bridgereg_t mask)
+{
+    bridge_t               *bridge;
+    pcibr_soft_slot_t       slotp;
+    bridgereg_t             old;
+    bridgereg_t             new;
+    bridgereg_t             chg;
+    bridgereg_t             bad;
+    bridgereg_t             badpmu;
+    bridgereg_t             badd32;
+    bridgereg_t             badd64;
+    bridgereg_t             fix;
+    unsigned long           s;
+    bridgereg_t             xmask;
+
+    xmask = mask;
+    if (pcibr_soft->bs_xbridge) {
+    	if (mask == BRIDGE_DEV_PMU_BITS)
+		xmask = XBRIDGE_DEV_PMU_BITS;
+	if (mask == BRIDGE_DEV_D64_BITS)
+		xmask = XBRIDGE_DEV_D64_BITS;
+    }
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    bridge = pcibr_soft->bs_base;
+
+    old = slotp->bss_device;
+
+    /* figure out what the desired
+     * Device(x) bits are based on
+     * the flags specified.
+     */
+
+    new = old;
+
+    /* Currently, we inherit anything that
+     * the new caller has not specified in
+     * one way or another, unless we take
+     * action here to not inherit.
+     *
+     * This is needed for the "swap" stuff,
+     * since it could have been set via
+     * pcibr_endian_set -- altho note that
+     * any explicit PCIBR_BYTE_STREAM or
+     * PCIBR_WORD_VALUES will freely override
+     * the effect of that call (and vice
+     * versa, no protection either way).
+     *
+     * I want to get rid of pcibr_endian_set
+     * in favor of tracking DMA endianness
+     * using the flags specified when DMA
+     * channels are created.
+     */
+
+#define	BRIDGE_DEV_WRGA_BITS	(BRIDGE_DEV_PMU_WRGA_EN | BRIDGE_DEV_DIR_WRGA_EN)
+#define	BRIDGE_DEV_SWAP_BITS	(BRIDGE_DEV_SWAP_PMU | BRIDGE_DEV_SWAP_DIR)
+
+    /* Do not use Barrier, Write Gather,
+     * or Prefetch unless asked.
+     * Leave everything else as it
+     * was from the last time.
+     */
+    new = new
+	& ~BRIDGE_DEV_BARRIER
+	& ~BRIDGE_DEV_WRGA_BITS
+	& ~BRIDGE_DEV_PREF
+	;
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {
+	new = (new
+            & ~BRIDGE_DEV_BARRIER)      /* barrier off */
+            | BRIDGE_DEV_PREF;          /* prefetch on */
+
+    }
+    if (flags & PCIIO_DMA_CMD) {
+        new = ((new
+            & ~BRIDGE_DEV_PREF)         /* prefetch off */
+            & ~BRIDGE_DEV_WRGA_BITS)    /* write gather off */
+            | BRIDGE_DEV_BARRIER;       /* barrier on */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIIO_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	new |= BRIDGE_DEV_WRGA_BITS;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	new &= ~BRIDGE_DEV_WRGA_BITS;
+
+    if (flags & PCIIO_BYTE_STREAM)
+	new |= (pcibr_soft->bs_xbridge) ? 
+			BRIDGE_DEV_SWAP_DIR : BRIDGE_DEV_SWAP_BITS;
+    if (flags & PCIIO_WORD_VALUES)
+	new &= (pcibr_soft->bs_xbridge) ? 
+			~BRIDGE_DEV_SWAP_DIR : ~BRIDGE_DEV_SWAP_BITS;
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_PREFETCH)
+	new |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	new &= ~BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	new |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	new &= ~BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	new |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	new &= ~BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	new |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	new &= ~BRIDGE_DEV_DEV_SIZE;
+
+    chg = old ^ new;				/* what are we changing, */
+    chg &= xmask;				/* of the interesting bits */
+
+    if (chg) {
+
+	badd32 = slotp->bss_d32_uctr ? (BRIDGE_DEV_D32_BITS & chg) : 0;
+	if (pcibr_soft->bs_xbridge) {
+		badpmu = slotp->bss_pmu_uctr ? (XBRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (XBRIDGE_DEV_D64_BITS & chg) : 0;
+	} else {
+		badpmu = slotp->bss_pmu_uctr ? (BRIDGE_DEV_PMU_BITS & chg) : 0;
+		badd64 = slotp->bss_d64_uctr ? (BRIDGE_DEV_D64_BITS & chg) : 0;
+	}
+	bad = badpmu | badd32 | badd64;
+
+	if (bad) {
+
+	    /* some conflicts can be resolved by
+	     * forcing the bit on. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit off,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+            if ( (fix = bad & (BRIDGE_DEV_PRECISE |
+                             BRIDGE_DEV_BARRIER)) ){
+		bad &= ~fix;
+		/* don't change these bits if
+		 * they are already set in "old"
+		 */
+		chg &= ~(fix & old);
+	    }
+	    /* some conflicts can be resolved by
+	     * forcing the bit off. this may cause
+	     * some performance degredation in
+	     * the stream(s) that want the bit on,
+	     * but the alternative is not allowing
+	     * the new stream at all.
+	     */
+	    if ( (fix = bad & (BRIDGE_DEV_WRGA_BITS |
+			     BRIDGE_DEV_PREF)) ) {
+		bad &= ~fix;
+		/* don't change these bits if
+		 * we wanted to turn them on.
+		 */
+		chg &= ~(fix & new);
+	    }
+	    /* conflicts in other bits mean
+	     * we can not establish this DMA
+	     * channel while the other(s) are
+	     * still present.
+	     */
+	    if (bad) {
+		pcibr_unlock(pcibr_soft, s);
+#if (DEBUG && PCIBR_DEV_DEBUG)
+		printk("pcibr_try_set_device: mod blocked by %R\n", bad, device_bits);
+#endif
+		return bad;
+	    }
+	}
+    }
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr++;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr++;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr++;
+
+    /* the value we want to write is the
+     * original value, with the bits for
+     * our selected changes flipped, and
+     * with any disabled features turned off.
+     */
+    new = old ^ chg;			/* only change what we want to change */
+
+    if (slotp->bss_device == new) {
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    bridge->b_device[slot].reg = new;
+    slotp->bss_device = new;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", slot, bridge->b_device[slot].reg);
+#endif
+
+    return 0;
+}
+
+void
+pcibr_release_device(pcibr_soft_t pcibr_soft,
+		     pciio_slot_t slot,
+		     bridgereg_t mask)
+{
+    pcibr_soft_slot_t       slotp;
+    unsigned long           s;
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (mask == BRIDGE_DEV_PMU_BITS)
+	slotp->bss_pmu_uctr--;
+    if (mask == BRIDGE_DEV_D32_BITS)
+	slotp->bss_d32_uctr--;
+    if (mask == BRIDGE_DEV_D64_BITS)
+	slotp->bss_d64_uctr--;
+
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * flush write gather buffer for slot
+ */
+static void
+pcibr_device_write_gather_flush(pcibr_soft_t pcibr_soft,
+              pciio_slot_t slot)
+{
+    bridge_t               *bridge;
+    unsigned long          s;
+    volatile uint32_t     wrf;
+    s = pcibr_lock(pcibr_soft);
+    bridge = pcibr_soft->bs_base;
+    wrf = bridge->b_wr_req_buf[slot].reg;
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/* =====================================================================
+ *    Bridge (pcibr) "Device Driver" entry points
+ */
+
+
+/*
+ *    pcibr_init: called once during system startup or
+ *      when a loadable driver is loaded.
+ *
+ *      The driver_register function should normally
+ *      be in _reg, not _init.  But the pcibr driver is
+ *      required by devinit before the _reg routines
+ *      are called, so this is an exception.
+ */
+void
+pcibr_init(void)
+{
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_init\n");
+#endif
+
+    xwidget_driver_register(XBRIDGE_WIDGET_PART_NUM,
+			    XBRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+    xwidget_driver_register(BRIDGE_WIDGET_PART_NUM,
+			    BRIDGE_WIDGET_MFGR_NUM,
+			    "pcibr_",
+			    0);
+}
+
+/*
+ * open/close mmap/munmap interface would be used by processes
+ * that plan to map the PCI bridge, and muck around with the
+ * registers. This is dangerous to do, and will be allowed
+ * to a select brand of programs. Typically these are
+ * diagnostics programs, or some user level commands we may
+ * write to do some weird things.
+ * To start with expect them to have root priveleges.
+ * We will ask for more later.
+ */
+/* ARGSUSED */
+int
+pcibr_open(devfs_handle_t *devp, int oflag, int otyp, cred_t *credp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp)
+{
+    return 0;
+}
+
+/*ARGSUSED */
+int
+pcibr_map(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot)
+{
+    int                     error;
+    devfs_handle_t            vhdl = dev_to_vhdl(dev);
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get(vhdl);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    ASSERT(pcibr_soft);
+    len = ctob(btoc(len));		/* Make len page aligned */
+    error = v_mapphys(vt, (void *) ((__psunsigned_t) bridge + off), len);
+
+    /*
+     * If the offset being mapped corresponds to the flash prom
+     * base, and if the mapping succeeds, and if the user
+     * has requested the protections to be WRITE, enable the
+     * flash prom to be written.
+     *
+     * XXX- deprecate this in favor of using the
+     * real flash driver ...
+     */
+    if (!error &&
+	((off == BRIDGE_EXTERNAL_FLASH) ||
+	 (len > BRIDGE_EXTERNAL_FLASH))) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control |= BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+
+    return error;
+}
+
+/*ARGSUSED */
+int
+pcibr_unmap(devfs_handle_t dev, vhandl_t *vt)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t) dev);
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    /*
+     * If flashprom write was enabled, disable it, as
+     * this is the last unmap.
+     */
+    if (bridge->b_wid_control & BRIDGE_CTRL_FLASH_WR_EN) {
+	int                     s;
+
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	s = splhi();
+	bridge->b_wid_control &= ~BRIDGE_CTRL_FLASH_WR_EN;
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(s);
+    }
+    return 0;
+}
+
+/* This is special case code used by grio. There are plans to make
+ * this a bit more general in the future, but till then this should
+ * be sufficient.
+ */
+pciio_slot_t
+pcibr_device_slot_get(devfs_handle_t dev_vhdl)
+{
+    char                    devname[MAXDEVNAME];
+    devfs_handle_t            tdev;
+    pciio_info_t            pciio_info;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+
+    vertex_to_name(dev_vhdl, devname, MAXDEVNAME);
+
+    /* run back along the canonical path
+     * until we find a PCI connection point.
+     */
+    tdev = hwgraph_connectpt_get(dev_vhdl);
+    while (tdev != GRAPH_VERTEX_NONE) {
+	pciio_info = pciio_info_chk(tdev);
+	if (pciio_info) {
+	    slot = pciio_info_slot_get(pciio_info);
+	    break;
+	}
+	hwgraph_vertex_unref(tdev);
+	tdev = hwgraph_connectpt_get(tdev);
+    }
+    hwgraph_vertex_unref(tdev);
+
+    return slot;
+}
+
+/*ARGSUSED */
+int
+pcibr_ioctl(devfs_handle_t dev,
+	    int cmd,
+	    void *arg,
+	    int flag,
+	    struct cred *cr,
+	    int *rvalp)
+{
+    devfs_handle_t            pcibr_vhdl = hwgraph_connectpt_get((devfs_handle_t)dev);
+#ifdef LATER
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+#endif
+    int                     error = 0;
+
+    hwgraph_vertex_unref(pcibr_vhdl);
+
+    switch (cmd) {
+#ifdef LATER
+    case GIOCSETBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able((uint64_t)CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_HIGH);
+	    break;
+	}
+
+    case GIOCRELEASEBW:
+	{
+	    grio_ioctl_info_t       info;
+	    pciio_slot_t            slot = 0;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+	    if (COPYIN(arg, &info, sizeof(grio_ioctl_info_t))) {
+		error = EFAULT;
+		break;
+	    }
+#ifdef GRIO_DEBUG
+	    printk("pcibr:: prev_vhdl: %d reqbw: %lld\n",
+		    info.prev_vhdl, info.reqbw);
+#endif				/* GRIO_DEBUG */
+
+	    if ((slot = pcibr_device_slot_get(info.prev_vhdl)) ==
+		PCIIO_SLOT_NONE) {
+		error = EIO;
+		break;
+	    }
+	    if (info.reqbw)
+		pcibr_priority_bits_set(pcibr_soft, slot, PCI_PRIO_LOW);
+	    break;
+	}
+
+    case PCIBR_SLOT_STARTUP:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+	    error = pcibr_slot_startup(pcibr_vhdl, &req);
+	    break;
+	}
+    case PCIBR_SLOT_SHUTDOWN:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+	    error = pcibr_slot_shutdown(pcibr_vhdl, &req);
+	    break;
+	}
+    case PCIBR_SLOT_QUERY:
+	{
+	    struct pcibr_slot_req_s        req;
+
+	    if (!cap_able(CAP_DEVICE_MGT)) {
+		error = EPERM;
+		break;
+	    }
+
+            if (COPYIN(arg, &req, sizeof(req))) {
+                error = EFAULT;
+                break;
+            }
+
+            error = pcibr_slot_query(pcibr_vhdl, &req);
+	    break;
+	}
+#endif	/* LATER */
+    default:
+	break;
+
+    }
+
+    return error;
+}
+
+void
+pcibr_freeblock_sub(iopaddr_t *free_basep,
+		    iopaddr_t *free_lastp,
+		    iopaddr_t base,
+		    size_t size)
+{
+    iopaddr_t               free_base = *free_basep;
+    iopaddr_t               free_last = *free_lastp;
+    iopaddr_t               last = base + size - 1;
+
+    if ((last < free_base) || (base > free_last));	/* free block outside arena */
+
+    else if ((base <= free_base) && (last >= free_last))
+	/* free block contains entire arena */
+	*free_basep = *free_lastp = 0;
+
+    else if (base <= free_base)
+	/* free block is head of arena */
+	*free_basep = last + 1;
+
+    else if (last >= free_last)
+	/* free block is tail of arena */
+	*free_lastp = base - 1;
+
+    /*
+     * We are left with two regions: the free area
+     * in the arena "below" the block, and the free
+     * area in the arena "above" the block. Keep
+     * the one that is bigger.
+     */
+
+    else if ((base - free_base) > (free_last - last))
+	*free_lastp = base - 1;		/* keep lower chunk */
+    else
+	*free_basep = last + 1;		/* keep upper chunk */
+}
+
+pcibr_info_t
+pcibr_info_get(devfs_handle_t vhdl)
+{
+    return (pcibr_info_t) pciio_info_get(vhdl);
+}
+
+pcibr_info_t
+pcibr_device_info_new(
+			 pcibr_soft_t pcibr_soft,
+			 pciio_slot_t slot,
+			 pciio_function_t rfunc,
+			 pciio_vendor_id_t vendor,
+			 pciio_device_id_t device)
+{
+    pcibr_info_t            pcibr_info;
+    pciio_function_t        func;
+    int                     ibit;
+
+    func = (rfunc == PCIIO_FUNC_NONE) ? 0 : rfunc;
+
+    NEW(pcibr_info);
+
+    pciio_device_info_new(&pcibr_info->f_c,
+			  pcibr_soft->bs_vhdl,
+			  slot, rfunc,
+			  vendor, device);
+
+/* pfg - this is new ..... */
+    /* Set PCI bus number */
+    pcibr_info->f_bus = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (slot != PCIIO_SLOT_NONE) {
+
+	/*
+	 * Currently favored mapping from PCI
+	 * slot number and INTA/B/C/D to Bridge
+	 * PCI Interrupt Bit Number:
+	 *
+	 *     SLOT     A B C D
+	 *      0       0 4 0 4
+	 *      1       1 5 1 5
+	 *      2       2 6 2 6
+	 *      3       3 7 3 7
+	 *      4       4 0 4 0
+	 *      5       5 1 5 1
+	 *      6       6 2 6 2
+	 *      7       7 3 7 3
+	 *
+	 * XXX- allow pcibr_hints to override default
+	 * XXX- allow ADMIN to override pcibr_hints
+	 */
+	for (ibit = 0; ibit < 4; ++ibit)
+	    pcibr_info->f_ibit[ibit] =
+		(slot + 4 * ibit) & 7;
+
+	/*
+	 * Record the info in the sparse func info space.
+	 */
+	if (func < pcibr_soft->bs_slot[slot].bss_ninfo)
+	    pcibr_soft->bs_slot[slot].bss_infos[func] = pcibr_info;
+    }
+    return pcibr_info;
+}
+
+
+/* FIXME:  for now this is needed by both pcibr.c and
+ * pcibr_slot.c.  Need to find a better way, the least
+ * of which would be to move it to pcibr_private.h
+ */
+
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+
+/*
+ * pcibr_device_unregister
+ *	This frees up any hardware resources reserved for this PCI device
+ * 	and removes any PCI infrastructural information setup for it.
+ *	This is usually used at the time of shutting down of the PCI card.
+ */
+int
+pcibr_device_unregister(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t	 pciio_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    int                  count_vchan0, count_vchan1;
+    unsigned             s;
+    int			 error_call;
+    int			 error = 0;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Clear all the hardware xtalk resources for this device */
+    xtalk_widgetdev_shutdown(pcibr_soft->bs_conn, slot);
+
+    /* Flush all the rrbs */
+    pcibr_rrb_flush(pconn_vhdl);
+
+    /*
+     * If the RRB configuration for this slot has changed, set it 
+     * back to the boot-time default
+     */
+    if (pcibr_soft->bs_rrb_valid_dflt[slot] >= 0) {
+
+        s = pcibr_lock(pcibr_soft);
+
+        /* Free the rrbs allocated to this slot */
+        error_call = do_pcibr_rrb_free(bridge, slot, 
+		                       pcibr_soft->bs_rrb_valid[slot] +
+		                       pcibr_soft->bs_rrb_valid[slot + 
+                                       PCIBR_RRB_SLOT_VIRTUAL]);
+
+        if (error_call)
+            error = ERANGE;
+   
+         pcibr_soft->bs_rrb_res[slot] = pcibr_soft->bs_rrb_res[slot] +
+                                        pcibr_soft->bs_rrb_valid[slot] +
+                                        pcibr_soft->bs_rrb_valid[slot +
+                                        PCIBR_RRB_SLOT_VIRTUAL];
+
+        count_vchan0 = pcibr_soft->bs_rrb_valid_dflt[slot];
+        count_vchan1 = pcibr_soft->bs_rrb_valid_dflt[slot +
+                                                     PCIBR_RRB_SLOT_VIRTUAL];
+
+        pcibr_unlock(pcibr_soft, s);
+
+        pcibr_rrb_alloc(pconn_vhdl, &count_vchan0, &count_vchan1);
+
+    }
+
+    /* Flush the write buffers !! */
+    error_call = pcibr_wrb_flush(pconn_vhdl);
+
+    if (error_call)
+        error = error_call;
+
+    /* Clear the information specific to the slot */
+    error_call = pcibr_slot_info_free(pcibr_vhdl, slot);
+
+    if (error_call)
+        error = error_call;
+
+    return(error);
+    
+}
+
+/*
+ * pcibr_driver_reg_callback
+ *      CDL will call this function for each device found in the PCI
+ *      registry that matches the vendor/device IDs supported by 
+ *      the driver being registered.  The device's connection vertex
+ *      and the driver's attach function return status enable the
+ *      slot's device status to be set.
+ */
+void
+pcibr_driver_reg_callback(devfs_handle_t pconn_vhdl,
+			  int key1, int key2, int error)
+{
+    pciio_info_t	 pciio_info;
+    pcibr_info_t         pcibr_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+
+    /* Do not set slot status for vendor/device ID wildcard drivers */
+    if ((key1 == -1) || (key2 == -1))
+        return;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_info = pcibr_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    /* This may be a loadable driver so lock out any pciconfig actions */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    pcibr_info->f_att_det_error = error;
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+}
+
+/*
+ * pcibr_driver_unreg_callback
+ *      CDL will call this function for each device found in the PCI
+ *      registry that matches the vendor/device IDs supported by 
+ *      the driver being unregistered.  The device's connection vertex
+ *      and the driver's detach function return status enable the
+ *      slot's device status to be set.
+ */
+void
+pcibr_driver_unreg_callback(devfs_handle_t pconn_vhdl, 
+                            int key1, int key2, int error)
+{
+    pciio_info_t	 pciio_info;
+    pcibr_info_t         pcibr_info;
+    devfs_handle_t	 pcibr_vhdl;
+    pciio_slot_t	 slot;
+    pcibr_soft_t	 pcibr_soft;
+
+    /* Do not set slot status for vendor/device ID wildcard drivers */
+    if ((key1 == -1) || (key2 == -1))
+        return;
+
+    pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_info = pcibr_info_get(pconn_vhdl);
+
+    pcibr_vhdl = pciio_info_master_get(pciio_info);
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    /* This may be a loadable driver so lock out any pciconfig actions */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    pcibr_info->f_att_det_error = error;
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+}
+
+/* 
+ * build a convenience link path in the
+ * form of ".../<iobrick>/bus/<busnum>"
+ * 
+ * returns 1 on success, 0 otherwise
+ *
+ * depends on hwgraph separator == '/'
+ */
+int
+pcibr_bus_cnvlink(devfs_handle_t f_c, int slot)
+{
+        char dst[MAXDEVNAME];
+	char *dp = dst;
+        char *cp, *xp;
+        int widgetnum;
+        char pcibus[8];
+	devfs_handle_t nvtx, svtx;
+	int rv;
+
+#if DEBUG
+	printk("pcibr_bus_cnvlink: slot= %d f_c= %p\n", 
+		slot, f_c);
+	{
+		int pos;
+		char dname[256];
+		pos = devfs_generate_path(f_c, dname, 256);
+		printk("%s : path= %s\n", __FUNCTION__, &dname[pos]);
+	}
+#endif
+
+	if (GRAPH_SUCCESS != hwgraph_vertex_name_get(f_c, dst, MAXDEVNAME))
+		return 0;
+
+	/* dst example == /hw/module/001c02/Pbrick/xtalk/8/pci/direct */
+
+	/* find the widget number */
+	xp = strstr(dst, "/"EDGE_LBL_XTALK"/");
+	if (xp == NULL)
+		return 0;
+	widgetnum = atoi(xp+7);
+	if (widgetnum < XBOW_PORT_8 || widgetnum > XBOW_PORT_F)
+		return 0;
+
+	/* remove "/pci/direct" from path */
+	cp = strstr(dst, "/" EDGE_LBL_PCI "/" "direct");
+	if (cp == NULL)
+		return 0;
+	*cp = (char)NULL;
+
+	/* get the vertex for the widget */
+	if (GRAPH_SUCCESS != hwgraph_traverse(NULL, dp, &svtx))	
+		return 0;
+
+	*xp = (char)NULL;		/* remove "/xtalk/..." from path */
+
+	/* dst example now == /hw/module/001c02/Pbrick */
+
+	/* get the bus number */
+        strcat(dst, "/bus");
+        sprintf(pcibus, "%d", p_busnum[widgetnum]);
+
+	/* link to bus to widget */
+	rv = hwgraph_path_add(NULL, dp, &nvtx);
+	if (GRAPH_SUCCESS == rv)
+		rv = hwgraph_edge_add(nvtx, svtx, pcibus);
+
+	return (rv == GRAPH_SUCCESS);
+}
+
+
+/*
+ *    pcibr_attach: called every time the crosstalk
+ *      infrastructure is asked to initialize a widget
+ *      that matches the part number we handed to the
+ *      registration routine above.
+ */
+/*ARGSUSED */
+int
+pcibr_attach(devfs_handle_t xconn_vhdl)
+{
+    /* REFERENCED */
+    graph_error_t           rc;
+    devfs_handle_t            pcibr_vhdl;
+    devfs_handle_t            ctlr_vhdl;
+    bridge_t               *bridge = NULL;
+    bridgereg_t             id;
+    int                     rev;
+    pcibr_soft_t            pcibr_soft;
+    pcibr_info_t            pcibr_info;
+    xwidget_info_t          info;
+    xtalk_intr_t            xtalk_intr;
+    device_desc_t           dev_desc = (device_desc_t)0;
+    int                     slot;
+    int                     ibit;
+    devfs_handle_t            noslot_conn;
+    char                    devnm[MAXDEVNAME], *s;
+    pcibr_hints_t           pcibr_hints;
+    bridgereg_t             b_int_enable;
+    unsigned                rrb_fixed = 0;
+
+    iopaddr_t               pci_io_fb, pci_io_fl;
+    iopaddr_t               pci_lo_fb, pci_lo_fl;
+    iopaddr_t               pci_hi_fb, pci_hi_fl;
+
+    int                     spl_level;
+#ifdef LATER
+    char		    *nicinfo = (char *)0;
+#endif
+
+#if PCI_FBBE
+    int                     fast_back_to_back_enable;
+#endif
+    l1sc_t		    *scp;
+    nasid_t		    nasid;
+
+    async_attach_t          aa = NULL;
+
+    aa = async_attach_get_info(xconn_vhdl);
+
+#if DEBUG && ATTACH_DEBUG
+    printk("pcibr_attach: xconn_vhdl=  %p\n", xconn_vhdl);
+    {
+	int pos;
+	char dname[256];
+	pos = devfs_generate_path(xconn_vhdl, dname, 256);
+	printk("%s : path= %s \n", __FUNCTION__, &dname[pos]);
+    }
+#endif
+
+    /* Setup the PRB for the bridge in CONVEYOR BELT
+     * mode. PRBs are setup in default FIRE-AND-FORGET
+     * mode during the initialization.
+     */
+    hub_device_flags_set(xconn_vhdl, HUB_PIO_CONVEYOR);
+
+    bridge = (bridge_t *)
+	xtalk_piotrans_addr(xconn_vhdl, NULL,
+			    0, sizeof(bridge_t), 0);
+
+    /*
+     * Create the vertex for the PCI bus, which we
+     * will also use to hold the pcibr_soft and
+     * which will be the "master" vertex for all the
+     * pciio connection points we will hang off it.
+     * This needs to happen before we call nic_bridge_vertex_info
+     * as we are some of the *_vmc functions need access to the edges.
+     *
+     * Opening this vertex will provide access to
+     * the Bridge registers themselves.
+     */
+    rc = hwgraph_path_add(xconn_vhdl, EDGE_LBL_PCI, &pcibr_vhdl);
+    ASSERT(rc == GRAPH_SUCCESS);
+
+    ctlr_vhdl = NULL;
+    ctlr_vhdl = hwgraph_register(pcibr_vhdl, EDGE_LBL_CONTROLLER,
+                0, DEVFS_FL_AUTO_DEVNUM,
+                0, 0,
+                S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, 0, 0,
+                &pcibr_fops, NULL);
+
+    ASSERT(ctlr_vhdl != NULL);
+
+    /*
+     * decode the nic, and hang its stuff off our
+     * connection point where other drivers can get
+     * at it.
+     */
+#ifdef LATER
+    nicinfo = BRIDGE_VERTEX_MFG_INFO(xconn_vhdl, (nic_data_t) & bridge->b_nic);
+#endif
+
+    /*
+     * Get the hint structure; if some NIC callback
+     * marked this vertex as "hands-off" then we
+     * just return here, before doing anything else.
+     */
+    pcibr_hints = pcibr_hints_get(xconn_vhdl, 0);
+
+    if (pcibr_hints && pcibr_hints->ph_hands_off)
+	return -1;			/* generic operations disabled */
+
+    id = bridge->b_wid_id;
+    rev = XWIDGET_PART_REV_NUM(id);
+
+    hwgraph_info_add_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, (arbitrary_info_t) rev);
+
+    /*
+     * allocate soft state structure, fill in some
+     * fields, and hook it up to our vertex.
+     */
+    NEW(pcibr_soft);
+    BZERO(pcibr_soft, sizeof *pcibr_soft);
+    pcibr_soft_set(pcibr_vhdl, pcibr_soft);
+
+    pcibr_soft->bs_conn = xconn_vhdl;
+    pcibr_soft->bs_vhdl = pcibr_vhdl;
+    pcibr_soft->bs_base = bridge;
+    pcibr_soft->bs_rev_num = rev;
+    pcibr_soft->bs_intr_bits = pcibr_intr_bits;
+    if (is_xbridge(bridge)) {
+	pcibr_soft->bs_int_ate_size = XBRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 1;
+    } else {
+	pcibr_soft->bs_int_ate_size = BRIDGE_INTERNAL_ATES;
+	pcibr_soft->bs_xbridge = 0;
+    }
+
+    nasid = NASID_GET(bridge);
+    scp = &NODEPDA( NASID_TO_COMPACT_NODEID(nasid) )->module->elsc;
+    pcibr_soft->bs_l1sc = scp;
+    pcibr_soft->bs_moduleid = iobrick_module_get(scp);
+    pcibr_soft->bsi_err_intr = 0;
+
+    /* Bridges up through REV C
+     * are unable to set the direct
+     * byteswappers to BYTE_STREAM.
+     */
+    if (pcibr_soft->bs_rev_num <= BRIDGE_PART_REV_C) {
+	pcibr_soft->bs_pio_end_io = PCIIO_WORD_VALUES;
+	pcibr_soft->bs_pio_end_mem = PCIIO_WORD_VALUES;
+    }
+#if PCIBR_SOFT_LIST
+    {
+	pcibr_list_p            self;
+
+	NEW(self);
+	self->bl_soft = pcibr_soft;
+	self->bl_vhdl = pcibr_vhdl;
+	self->bl_next = pcibr_list;
+	self->bl_next = swap_ptr((void **) &pcibr_list, (void *)self);
+    }
+#endif
+
+    /*
+     * get the name of this bridge vertex and keep the info. Use this
+     * only where it is really needed now: like error interrupts.
+     */
+    s = dev_to_name(pcibr_vhdl, devnm, MAXDEVNAME);
+    pcibr_soft->bs_name = kmalloc(strlen(s) + 1, GFP_KERNEL);
+    strcpy(pcibr_soft->bs_name, s);
+
+#if SHOW_REVS || DEBUG
+#if !DEBUG
+    if (kdebug)
+#endif
+	printk("%sBridge ASIC: rev %s (code=0x%x) at %s\n",
+		is_xbridge(bridge) ? "X" : "",
+		(rev == BRIDGE_PART_REV_A) ? "A" :
+		(rev == BRIDGE_PART_REV_B) ? "B" :
+		(rev == BRIDGE_PART_REV_C) ? "C" :
+		(rev == BRIDGE_PART_REV_D) ? "D" :
+		(rev == XBRIDGE_PART_REV_A) ? "A" :
+		(rev == XBRIDGE_PART_REV_B) ? "B" :
+		"unknown",
+		rev, pcibr_soft->bs_name);
+#endif
+
+    info = xwidget_info_get(xconn_vhdl);
+    pcibr_soft->bs_xid = xwidget_info_id_get(info);
+    pcibr_soft->bs_master = xwidget_info_master_get(info);
+    pcibr_soft->bs_mxid = xwidget_info_masterid_get(info);
+
+    /*
+     * Init bridge lock.
+     */
+    spin_lock_init(&pcibr_soft->bs_lock);
+
+    /*
+     * If we have one, process the hints structure.
+     */
+    if (pcibr_hints) {
+	rrb_fixed = pcibr_hints->ph_rrb_fixed;
+
+	pcibr_soft->bs_rrb_fixed = rrb_fixed;
+
+	if (pcibr_hints->ph_intr_bits)
+	    pcibr_soft->bs_intr_bits = pcibr_hints->ph_intr_bits;
+
+	for (slot = 0; slot < 8; ++slot) {
+	    int                     hslot = pcibr_hints->ph_host_slot[slot] - 1;
+
+	    if (hslot < 0) {
+		pcibr_soft->bs_slot[slot].host_slot = slot;
+	    } else {
+		pcibr_soft->bs_slot[slot].has_host = 1;
+		pcibr_soft->bs_slot[slot].host_slot = hslot;
+	    }
+	}
+    }
+    /*
+     * set up initial values for state fields
+     */
+    for (slot = 0; slot < 8; ++slot) {
+	pcibr_soft->bs_slot[slot].bss_devio.bssd_space = PCIIO_SPACE_NONE;
+	pcibr_soft->bs_slot[slot].bss_d64_base = PCIBR_D64_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_d32_base = PCIBR_D32_BASE_UNSET;
+	pcibr_soft->bs_slot[slot].bss_ext_ates_active = ATOMIC_INIT(0);
+    }
+
+    for (ibit = 0; ibit < 8; ++ibit) {
+	pcibr_soft->bs_intr[ibit].bsi_xtalk_intr = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_soft = pcibr_soft;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_list = NULL;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_stat = 
+							&(bridge->b_int_status);
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_hdlrcnt = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_shared = 0;
+	pcibr_soft->bs_intr[ibit].bsi_pcibr_intr_wrap.iw_connected = 0;
+    }
+
+    /*
+     * Initialize various Bridge registers.
+     */
+
+    /*
+     * On pre-Rev.D bridges, set the PCI_RETRY_CNT
+     * to zero to avoid dropping stores. (#475347)
+     */
+    if (rev < BRIDGE_PART_REV_D)
+	bridge->b_bus_timeout &= ~BRIDGE_BUS_PCI_RETRY_MASK;
+
+    /*
+     * Clear all pending interrupts.
+     */
+    bridge->b_int_rst_stat = (BRIDGE_IRR_ALL_CLR);
+
+    /*
+     * Until otherwise set up,
+     * assume all interrupts are
+     * from slot 7.
+     */
+    bridge->b_int_device = (uint32_t) 0xffffffff;
+
+    {
+	bridgereg_t             dirmap;
+	paddr_t                 paddr;
+	iopaddr_t               xbase;
+	xwidgetnum_t            xport;
+	iopaddr_t               offset;
+	int                     num_entries = 0;
+	int                     entry;
+	cnodeid_t		cnodeid;
+	nasid_t			nasid;
+
+	/* Set the Bridge's 32-bit PCI to XTalk
+	 * Direct Map register to the most useful
+	 * value we can determine.  Note that we
+	 * must use a single xid for all of:
+	 *      direct-mapped 32-bit DMA accesses
+	 *      direct-mapped 64-bit DMA accesses
+	 *      DMA accesses through the PMU
+	 *      interrupts
+	 * This is the only way to guarantee that
+	 * completion interrupts will reach a CPU
+	 * after all DMA data has reached memory.
+	 * (Of course, there may be a few special
+	 * drivers/controlers that explicitly manage
+	 * this ordering problem.)
+	 */
+
+	cnodeid = 0;  /* default node id */
+	nasid = COMPACT_TO_NASID_NODEID(cnodeid);
+	paddr = NODE_OFFSET(nasid) + 0;
+
+	/* currently, we just assume that if we ask
+	 * for a DMA mapping to "zero" the XIO
+	 * host will transmute this into a request
+	 * for the lowest hunk of memory.
+	 */
+	xbase = xtalk_dmatrans_addr(xconn_vhdl, 0,
+				    paddr, _PAGESZ, 0);
+
+	if (xbase != XIO_NOWHERE) {
+	    if (XIO_PACKED(xbase)) {
+		xport = XIO_PORT(xbase);
+		xbase = XIO_ADDR(xbase);
+	    } else
+		xport = pcibr_soft->bs_mxid;
+
+	    offset = xbase & ((1ull << BRIDGE_DIRMAP_OFF_ADDRSHFT) - 1ull);
+	    xbase >>= BRIDGE_DIRMAP_OFF_ADDRSHFT;
+
+	    dirmap = xport << BRIDGE_DIRMAP_W_ID_SHFT;
+
+	    if (xbase)
+		dirmap |= BRIDGE_DIRMAP_OFF & xbase;
+	    else if (offset >= (512 << 20))
+		dirmap |= BRIDGE_DIRMAP_ADD512;
+
+	    bridge->b_dir_map = dirmap;
+	}
+	/*
+	 * Set bridge's idea of page size according to the system's
+	 * idea of "IO page size".  TBD: The idea of IO page size
+	 * should really go away.
+	 */
+	/*
+	 * ensure that we write and read without any interruption.
+	 * The read following the write is required for the Bridge war
+	 */
+	spl_level = splhi();
+#if IOPGSIZE == 4096
+	bridge->b_wid_control &= ~BRIDGE_CTRL_PAGE_SIZE;
+#elif IOPGSIZE == 16384
+	bridge->b_wid_control |= BRIDGE_CTRL_PAGE_SIZE;
+#else
+	<<<Unable to deal with IOPGSIZE >>>;
+#endif
+	bridge->b_wid_control;		/* inval addr bug war */
+	splx(spl_level);
+
+	/* Initialize internal mapping entries */
+	for (entry = 0; entry < pcibr_soft->bs_int_ate_size; entry++) {
+	    bridge->b_int_ate_ram[entry].wr = 0;
+	}
+
+	/*
+	 * Determine if there's external mapping SSRAM on this
+	 * bridge.  Set up Bridge control register appropriately,
+	 * inititlize SSRAM, and set software up to manage RAM
+	 * entries as an allocatable resource.
+	 *
+	 * Currently, we just use the rm* routines to manage ATE
+	 * allocation.  We should probably replace this with a
+	 * Best Fit allocator.
+	 *
+	 * For now, if we have external SSRAM, avoid using
+	 * the internal ssram: we can't turn PREFETCH on
+	 * when we use the internal SSRAM; and besides,
+	 * this also guarantees that no allocation will
+	 * straddle the internal/external line, so we
+	 * can increment ATE write addresses rather than
+	 * recomparing against BRIDGE_INTERNAL_ATES every
+	 * time.
+	 */
+	if (is_xbridge(bridge))
+		num_entries = 0;
+	else
+		num_entries = pcibr_init_ext_ate_ram(bridge);
+
+	/* we always have 128 ATEs (512 for Xbridge) inside the chip
+	 * even if disabled for debugging.
+	 */
+	pcibr_soft->bs_int_ate_map = rmallocmap(pcibr_soft->bs_int_ate_size);
+	pcibr_ate_free(pcibr_soft, 0, pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: %d INTERNAL ATEs\n", pcibr_soft->bs_int_ate_size);
+#endif
+
+	if (num_entries > pcibr_soft->bs_int_ate_size) {
+#if PCIBR_ATE_NOTBOTH			/* for debug -- forces us to use external ates */
+	    printk("pcibr_attach: disabling internal ATEs.\n");
+	    pcibr_ate_alloc(pcibr_soft, pcibr_soft->bs_int_ate_size);
+#endif
+	    pcibr_soft->bs_ext_ate_map = rmallocmap(num_entries);
+	    pcibr_ate_free(pcibr_soft, pcibr_soft->bs_int_ate_size,
+			   num_entries - pcibr_soft->bs_int_ate_size);
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_attach: %d EXTERNAL ATEs\n",
+		    num_entries - pcibr_soft->bs_int_ate_size);
+#endif
+	}
+    }
+
+    {
+	bridgereg_t             dirmap;
+	iopaddr_t               xbase;
+
+	/*
+	 * now figure the *real* xtalk base address
+	 * that dirmap sends us to.
+	 */
+	dirmap = bridge->b_dir_map;
+	if (dirmap & BRIDGE_DIRMAP_OFF)
+	    xbase = (iopaddr_t)(dirmap & BRIDGE_DIRMAP_OFF)
+			<< BRIDGE_DIRMAP_OFF_ADDRSHFT;
+	else if (dirmap & BRIDGE_DIRMAP_ADD512)
+	    xbase = 512 << 20;
+	else
+	    xbase = 0;
+
+	pcibr_soft->bs_dir_xbase = xbase;
+
+	/* it is entirely possible that we may, at this
+	 * point, have our dirmap pointing somewhere
+	 * other than our "master" port.
+	 */
+	pcibr_soft->bs_dir_xport =
+	    (dirmap & BRIDGE_DIRMAP_W_ID) >> BRIDGE_DIRMAP_W_ID_SHFT;
+    }
+
+    /* pcibr sources an error interrupt;
+     * figure out where to send it.
+     *
+     * If any interrupts are enabled in bridge,
+     * then the prom set us up and our interrupt
+     * has already been reconnected in mlreset
+     * above.
+     *
+     * Need to set the D_INTR_ISERR flag
+     * in the dev_desc used for allocating the
+     * error interrupt, so our interrupt will
+     * be properly routed and prioritized.
+     *
+     * If our crosstalk provider wants to
+     * fix widget error interrupts to specific
+     * destinations, D_INTR_ISERR is how it
+     * knows to do this.
+     */
+
+    xtalk_intr = xtalk_intr_alloc(xconn_vhdl, dev_desc, pcibr_vhdl);
+    ASSERT(xtalk_intr != NULL);
+
+    pcibr_soft->bsi_err_intr = xtalk_intr;
+
+    /*
+     * On IP35 with XBridge, we do some extra checks in pcibr_setwidint
+     * in order to work around some addressing limitations.  In order
+     * for that fire wall to work properly, we need to make sure we
+     * start from a known clean state.
+     */
+    pcibr_clearwidint(bridge);
+
+    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t)pcibr_setwidint, (void *)bridge);
+
+    /*
+     * now we can start handling error interrupts;
+     * enable all of them.
+     * NOTE: some PCI ints may already be enabled.
+     */
+    b_int_enable = bridge->b_int_enable | BRIDGE_ISR_ERRORS;
+
+
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_int_mode = 0;		/* do not send "clear interrupt" packets */
+
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    /*
+     * Depending on the rev of bridge, disable certain features.
+     * Easiest way seems to be to force the PCIBR_NOwhatever
+     * flag to be on for all DMA calls, which overrides any
+     * PCIBR_whatever flag or even the setting of whatever
+     * from the PCIIO_DMA_class flags (or even from the other
+     * PCIBR flags, since NO overrides YES).
+     */
+    pcibr_soft->bs_dma_flags = 0;
+
+    /* PREFETCH:
+     * Always completely disabled for REV.A;
+     * at "pcibr_prefetch_enable_rev", anyone
+     * asking for PCIIO_PREFETCH gets it.
+     * Between these two points, you have to ask
+     * for PCIBR_PREFETCH, which promises that
+     * your driver knows about known Bridge WARs.
+     */
+    if (pcibr_soft->bs_rev_num < BRIDGE_PART_REV_B)
+	pcibr_soft->bs_dma_flags |= PCIBR_NOPREFETCH;
+    else if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_prefetch_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIIO_NOPREFETCH;
+
+    /* WRITE_GATHER:
+     * Disabled up to but not including the
+     * rev number in pcibr_wg_enable_rev. There
+     * is no "WAR range" as with prefetch.
+     */
+    if (pcibr_soft->bs_rev_num < 
+		(BRIDGE_WIDGET_PART_NUM << 4 | pcibr_wg_enable_rev))
+	pcibr_soft->bs_dma_flags |= PCIBR_NOWRITE_GATHER;
+
+    pciio_provider_register(pcibr_vhdl, &pcibr_provider);
+    pciio_provider_startup(pcibr_vhdl);
+
+    pci_io_fb = 0x00000004;		/* I/O FreeBlock Base */
+    pci_io_fl = 0xFFFFFFFF;		/* I/O FreeBlock Last */
+
+    pci_lo_fb = 0x00000010;		/* Low Memory FreeBlock Base */
+    pci_lo_fl = 0x001FFFFF;		/* Low Memory FreeBlock Last */
+
+    pci_hi_fb = 0x00200000;		/* High Memory FreeBlock Base */
+    pci_hi_fl = 0x3FFFFFFF;		/* High Memory FreeBlock Last */
+
+
+    PCI_ADDR_SPACE_LIMITS_STORE();
+
+    /* build "no-slot" connection point
+     */
+    pcibr_info = pcibr_device_info_new
+	(pcibr_soft, PCIIO_SLOT_NONE, PCIIO_FUNC_NONE,
+	 PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+    noslot_conn = pciio_device_info_register
+	(pcibr_vhdl, &pcibr_info->f_c);
+
+    /* Remember the no slot connection point info for tearing it
+     * down during detach.
+     */
+    pcibr_soft->bs_noslot_conn = noslot_conn;
+    pcibr_soft->bs_noslot_info = pcibr_info;
+#if PCI_FBBE
+    fast_back_to_back_enable = 1;
+#endif
+
+#if PCI_FBBE
+    if (fast_back_to_back_enable) {
+	/*
+	 * All devices on the bus are capable of fast back to back, so
+	 * we need to set the fast back to back bit in all devices on
+	 * the bus that are capable of doing such accesses.
+	 */
+    }
+#endif
+
+#ifdef LATER
+    /* If the bridge has been reset then there is no need to reset
+     * the individual PCI slots.
+     */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Reset all the slots */
+	(void)pcibr_slot_reset(pcibr_vhdl, slot);
+#endif
+
+    for (slot = 0; slot < 8; ++slot)
+	/* Find out what is out there */
+	(void)pcibr_slot_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Set up the address space for this slot in the pci land */
+	(void)pcibr_slot_addr_space_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup the device register */
+	(void)pcibr_slot_device_init(pcibr_vhdl, slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Setup host/guest relations */
+	(void)pcibr_slot_guest_info_init(pcibr_vhdl,slot);
+
+    for (slot = 0; slot < 8; ++slot)  
+	/* Initial RRB management */
+	(void)pcibr_slot_initial_rrb_alloc(pcibr_vhdl,slot);
+
+    /* driver attach routines should be called out from generic linux code */
+    for (slot = 0; slot < 8; ++slot)  
+	/* Call the device attach */
+	(void)pcibr_slot_call_device_attach(pcibr_vhdl, slot, 0);
+
+    /*
+     * Each Pbrick PCI bus only has slots 1 and 2.   Similarly for
+     * widget 0xe on Ibricks.  Allocate RRB's accordingly.
+     */
+    if (pcibr_soft->bs_moduleid > 0) {
+	switch (MODULE_GET_BTCHAR(pcibr_soft->bs_moduleid)) {
+	case 'p':		/* Pbrick */
+		do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+		do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		break;
+	case 'i':		/* Ibrick */
+	  	/* port 0xe on the Ibrick only has slots 1 and 2 */
+		if (pcibr_soft->bs_xid == 0xe) {
+			do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+			do_pcibr_rrb_autoalloc(pcibr_soft, 2, 8);
+		}
+		else {
+		    	/* allocate one RRB for the serial port */
+			do_pcibr_rrb_autoalloc(pcibr_soft, 0, 1);
+		}
+		break;
+	} /* switch */
+    }
+
+#ifdef LATER
+    if (strstr(nicinfo, XTALK_PCI_PART_NUM)) {
+	do_pcibr_rrb_autoalloc(pcibr_soft, 1, 8);
+#if PCIBR_RRB_DEBUG
+	printf("\n\nFound XTALK_PCI (030-1275) at %v\n", xconn_vhdl);
+
+	printf("pcibr_attach: %v Shoebox RRB MANAGEMENT: %d+%d free\n",
+		pcibr_vhdl,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+
+	for (slot = 0; slot < 8; ++slot)
+	    printf("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+
+	printf("\n");
+#endif
+    }
+#else
+	FIXME("pcibr_attach: Call do_pcibr_rrb_autoalloc nicinfo\n");
+#endif
+
+    if (aa)
+	    async_attach_add_info(noslot_conn, aa);
+
+    pciio_device_attach(noslot_conn, 0);
+
+
+    /* 
+     * Tear down pointer to async attach info -- async threads for
+     * bridge's descendants may be running but the bridge's work is done.
+     */
+    if (aa)
+	    async_attach_del_info(xconn_vhdl);
+
+    return 0;
+}
+/*
+ * pcibr_detach:
+ *	Detach the bridge device from the hwgraph after cleaning out all the 
+ *	underlying vertices.
+ */
+int
+pcibr_detach(devfs_handle_t xconn)
+{
+    pciio_slot_t	slot;
+    devfs_handle_t	pcibr_vhdl;
+    pcibr_soft_t	pcibr_soft;
+    bridge_t		*bridge;
+
+    /* Get the bridge vertex from its xtalk connection point */
+    if (hwgraph_traverse(xconn, EDGE_LBL_PCI, &pcibr_vhdl) != GRAPH_SUCCESS)
+	return(1);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge = pcibr_soft->bs_base;
+
+    /* Disable the interrupts from the bridge */
+    bridge->b_int_enable = 0;
+
+    /* Detach all the PCI devices talking to this bridge */
+    for(slot = 0; slot < 8; slot++) {
+#ifdef DEBUG
+	printk("pcibr_device_detach called for %p/%d\n",
+		pcibr_vhdl,slot);
+#endif
+	pcibr_slot_detach(pcibr_vhdl, slot, 0);
+    }
+
+    /* Unregister the no-slot connection point */
+    pciio_device_info_unregister(pcibr_vhdl,
+				 &(pcibr_soft->bs_noslot_info->f_c));
+
+    spin_lock_destroy(&pcibr_soft->bs_lock);
+    kfree(pcibr_soft->bs_name);
+    
+    /* Error handler gets unregistered when the widget info is 
+     * cleaned 
+     */
+    /* Free the soft ATE maps */
+    if (pcibr_soft->bs_int_ate_map)
+	rmfreemap(pcibr_soft->bs_int_ate_map);
+    if (pcibr_soft->bs_ext_ate_map)
+	rmfreemap(pcibr_soft->bs_ext_ate_map);
+
+    /* Disconnect the error interrupt and free the xtalk resources 
+     * associated with it.
+     */
+    xtalk_intr_disconnect(pcibr_soft->bsi_err_intr);
+    xtalk_intr_free(pcibr_soft->bsi_err_intr);
+
+    /* Clear the software state maintained by the bridge driver for this
+     * bridge.
+     */
+    DEL(pcibr_soft);
+    /* Remove the Bridge revision labelled info */
+    (void)hwgraph_info_remove_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, NULL);
+    /* Remove the character device associated with this bridge */
+    (void)hwgraph_edge_remove(pcibr_vhdl, EDGE_LBL_CONTROLLER, NULL);
+    /* Remove the PCI bridge vertex */
+    (void)hwgraph_edge_remove(xconn, EDGE_LBL_PCI, NULL);
+
+    return(0);
+}
+
+int
+pcibr_asic_rev(devfs_handle_t pconn_vhdl)
+{
+    devfs_handle_t            pcibr_vhdl;
+    arbitrary_info_t        ainfo;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_traverse(pconn_vhdl, EDGE_LBL_MASTER, &pcibr_vhdl))
+	return -1;
+
+    if (GRAPH_SUCCESS !=
+	hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &ainfo))
+	return -1;
+
+    return (int) ainfo;
+}
+
+int
+pcibr_write_gather_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t  pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t  pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t  slot;
+    slot = pciio_info_slot_get(pciio_info);
+    pcibr_device_write_gather_flush(pcibr_soft, slot);
+    return 0;
+}
+
+/* =====================================================================
+ *    PIO MANAGEMENT
+ */
+
+static iopaddr_t
+pcibr_addr_pci_to_xio(devfs_handle_t pconn_vhdl,
+		      pciio_slot_t slot,
+		      pciio_space_t space,
+		      iopaddr_t pci_addr,
+		      size_t req_size,
+		      unsigned flags)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    unsigned                bar;	/* which BASE reg on device is decoding */
+    iopaddr_t               xio_addr = XIO_NOWHERE;
+
+    pciio_space_t           wspace;	/* which space device is decoding */
+    iopaddr_t               wbase;	/* base of device decode on PCI */
+    size_t                  wsize;	/* size of device decode on PCI */
+
+    int                     try;	/* DevIO(x) window scanning order control */
+    int                     win;	/* which DevIO(x) window is being used */
+    pciio_space_t           mspace;	/* target space for devio(x) register */
+    iopaddr_t               mbase;	/* base of devio(x) mapped area on PCI */
+    size_t                  msize;	/* size of devio(x) mapped area on PCI */
+    size_t                  mmask;	/* addr bits stored in Device(x) */
+
+    unsigned long           s;
+
+    s = pcibr_lock(pcibr_soft);
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	slot = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[slot].bss_infos[0];
+    }
+    if (space == PCIIO_SPACE_NONE)
+	goto done;
+
+    if (space == PCIIO_SPACE_CFG) {
+	/*
+	 * Usually, the first mapping
+	 * established to a PCI device
+	 * is to its config space.
+	 *
+	 * In any case, we definitely
+	 * do NOT need to worry about
+	 * PCI BASE registers, and
+	 * MUST NOT attempt to point
+	 * the DevIO(x) window at
+	 * this access ...
+	 */
+	if (((flags & PCIIO_BYTE_STREAM) == 0) &&
+	    ((pci_addr + req_size) <= BRIDGE_TYPE0_CFG_FUNC_OFF))
+	    xio_addr = pci_addr + BRIDGE_TYPE0_CFG_DEV(slot);
+
+	goto done;
+    }
+    if (space == PCIIO_SPACE_ROM) {
+	/* PIO to the Expansion Rom.
+	 * Driver is responsible for
+	 * enabling and disabling
+	 * decodes properly.
+	 */
+	wbase = pcibr_info->f_rbase;
+	wsize = pcibr_info->f_rsize;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	pci_addr += wbase;
+	space = PCIIO_SPACE_MEM;
+    }
+    /*
+     * reduce window mappings to raw
+     * space mappings (maybe allocating
+     * windows), and try for DevIO(x)
+     * usage (setting it if it is available).
+     */
+    bar = space - PCIIO_SPACE_WIN0;
+    if (bar < 6) {
+	wspace = pcibr_info->f_window[bar].w_space;
+	if (wspace == PCIIO_SPACE_NONE)
+	    goto done;
+
+	/* get PCI base and size */
+	wbase = pcibr_info->f_window[bar].w_base;
+	wsize = pcibr_info->f_window[bar].w_size;
+
+	/*
+	 * While the driver should know better
+	 * than to attempt to map more space
+	 * than the device is decoding, he might
+	 * do it; better to bail out here.
+	 */
+	if ((pci_addr + req_size) > wsize)
+	    goto done;
+
+	/* shift from window relative to
+	 * decoded space relative.
+	 */
+	pci_addr += wbase;
+	space = wspace;
+    } else
+	bar = -1;
+
+    /* Scan all the DevIO(x) windows twice looking for one
+     * that can satisfy our request. The first time through,
+     * only look at assigned windows; the second time, also
+     * look at PCIIO_SPACE_NONE windows. Arrange the order
+     * so we always look at our own window first.
+     *
+     * We will not attempt to satisfy a single request
+     * by concatinating multiple windows.
+     */
+    for (try = 0; try < 16; ++try) {
+	bridgereg_t             devreg;
+	unsigned                offset;
+
+	win = (try + slot) % 8;
+
+	/* If this DevIO(x) mapping area can provide
+	 * a mapping to this address, use it.
+	 */
+	msize = (win < 2) ? 0x200000 : 0x100000;
+	mmask = -msize;
+	if (space != PCIIO_SPACE_IO)
+	    mmask &= 0x3FFFFFFF;
+
+	offset = pci_addr & (msize - 1);
+
+	/* If this window can't possibly handle that request,
+	 * go on to the next window.
+	 */
+	if (((pci_addr & (msize - 1)) + req_size) > msize)
+	    continue;
+
+	devreg = pcibr_soft->bs_slot[win].bss_device;
+
+	/* Is this window "nailed down"?
+	 * If not, maybe we can use it.
+	 * (only check this the second time through)
+	 */
+	mspace = pcibr_soft->bs_slot[win].bss_devio.bssd_space;
+	if ((try > 7) && (mspace == PCIIO_SPACE_NONE)) {
+
+	    /* If this is the primary DevIO(x) window
+	     * for some other device, skip it.
+	     */
+	    if ((win != slot) &&
+		(PCIIO_VENDOR_ID_NONE !=
+		 pcibr_soft->bs_slot[win].bss_vendor_id))
+		continue;
+
+	    /* It's a free window, and we fit in it.
+	     * Set up Device(win) to our taste.
+	     */
+	    mbase = pci_addr & mmask;
+
+	    /* check that we would really get from
+	     * here to there.
+	     */
+	    if ((mbase | offset) != pci_addr)
+		continue;
+
+	    devreg &= ~BRIDGE_DEV_OFF_MASK;
+	    if (space != PCIIO_SPACE_IO)
+		devreg |= BRIDGE_DEV_DEV_IO_MEM;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_IO_MEM;
+	    devreg |= (mbase >> 20) & BRIDGE_DEV_OFF_MASK;
+
+	    /* default is WORD_VALUES.
+	     * if you specify both,
+	     * operation is undefined.
+	     */
+	    if (flags & PCIIO_BYTE_STREAM)
+		devreg |= BRIDGE_DEV_DEV_SWAP;
+	    else
+		devreg &= ~BRIDGE_DEV_DEV_SWAP;
+
+	    if (pcibr_soft->bs_slot[win].bss_device != devreg) {
+		bridge->b_device[win].reg = devreg;
+		pcibr_soft->bs_slot[win].bss_device = devreg;
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+
+#if DEBUG && PCI_DEBUG
+		printk("pcibr Device(%d): 0x%lx\n", win, bridge->b_device[win].reg);
+#endif
+	    }
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_space = space;
+	    pcibr_soft->bs_slot[win].bss_devio.bssd_base = mbase;
+	    xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	    printk("%s LINE %d map to space %d space desc 0x%x[%lx..%lx] for slot %d allocates DevIO(%d) devreg 0x%x\n", 
+		    __FUNCTION__, __LINE__, space, space_desc,
+		    pci_addr, pci_addr + req_size - 1,
+		    slot, win, devreg);
+#endif
+
+	    goto done;
+	}				/* endif DevIO(x) not pointed */
+	mbase = pcibr_soft->bs_slot[win].bss_devio.bssd_base;
+
+	/* Now check for request incompat with DevIO(x)
+	 */
+	if ((mspace != space) ||
+	    (pci_addr < mbase) ||
+	    ((pci_addr + req_size) > (mbase + msize)) ||
+	    ((flags & PCIIO_BYTE_STREAM) && !(devreg & BRIDGE_DEV_DEV_SWAP)) ||
+	    (!(flags & PCIIO_BYTE_STREAM) && (devreg & BRIDGE_DEV_DEV_SWAP)))
+	    continue;
+
+	/* DevIO(x) window is pointed at PCI space
+	 * that includes our target. Calculate the
+	 * final XIO address, release the lock and
+	 * return.
+	 */
+	xio_addr = BRIDGE_DEVIO(win) + (pci_addr - mbase);
+
+#if DEBUG && PCI_DEBUG
+	printk("%s LINE %d map to space %d [0x%p..0x%p] for slot %d uses DevIO(%d)\n",
+		__FUNCTION__, __LINE__, space,  pci_addr, pci_addr + req_size - 1, slot, win);
+#endif
+	goto done;
+    }
+
+    switch (space) {
+	/*
+	 * Accesses to device decode
+	 * areas that do a not fit
+	 * within the DevIO(x) space are
+	 * modified to be accesses via
+	 * the direct mapping areas.
+	 *
+	 * If necessary, drivers can
+	 * explicitly ask for mappings
+	 * into these address spaces,
+	 * but this should never be needed.
+	 */
+    case PCIIO_SPACE_MEM:		/* "mem space" */
+    case PCIIO_SPACE_MEM32:		/* "mem, use 32-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM32_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM32_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM32_BASE;
+	break;
+
+    case PCIIO_SPACE_MEM64:		/* "mem, use 64-bit-wide bus" */
+	if ((pci_addr + BRIDGE_PCI_MEM64_BASE + req_size - 1) <=
+	    BRIDGE_PCI_MEM64_LIMIT)
+	    xio_addr = pci_addr + BRIDGE_PCI_MEM64_BASE;
+	break;
+
+    case PCIIO_SPACE_IO:		/* "i/o space" */
+	/* Bridge Hardware Bug WAR #482741:
+	 * The 4G area that maps directly from
+	 * XIO space to PCI I/O space is busted
+	 * until Bridge Rev D.
+	 */
+	if ((pcibr_soft->bs_rev_num > BRIDGE_PART_REV_C) &&
+	    ((pci_addr + BRIDGE_PCI_IO_BASE + req_size - 1) <=
+	     BRIDGE_PCI_IO_LIMIT))
+	    xio_addr = pci_addr + BRIDGE_PCI_IO_BASE;
+	break;
+    }
+
+    /* Check that "Direct PIO" byteswapping matches,
+     * try to change it if it does not.
+     */
+    if (xio_addr != XIO_NOWHERE) {
+	unsigned                bst;	/* nonzero to set bytestream */
+	unsigned               *bfp;	/* addr of record of how swapper is set */
+	unsigned                swb;	/* which control bit to mung */
+	unsigned                bfo;	/* current swapper setting */
+	unsigned                bfn;	/* desired swapper setting */
+
+	bfp = ((space == PCIIO_SPACE_IO)
+	       ? (&pcibr_soft->bs_pio_end_io)
+	       : (&pcibr_soft->bs_pio_end_mem));
+
+	bfo = *bfp;
+
+	bst = flags & PCIIO_BYTE_STREAM;
+
+	bfn = bst ? PCIIO_BYTE_STREAM : PCIIO_WORD_VALUES;
+
+	if (bfn == bfo) {		/* we already match. */
+	    ;
+	} else if (bfo != 0) {		/* we have a conflict. */
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap conflict in space %d , was%s%s, want%s%s\n",
+		    space, 
+		    bfo & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfo & PCIIO_WORD_VALUES ? " WORD_VALUES" : "",
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	    xio_addr = XIO_NOWHERE;
+	} else {			/* OK to make the change. */
+	    bridgereg_t             octl, nctl;
+
+	    swb = (space == PCIIO_SPACE_IO) ? BRIDGE_CTRL_IO_SWAP : BRIDGE_CTRL_MEM_SWAP;
+	    octl = bridge->b_wid_control;
+	    nctl = bst ? octl | swb : octl & ~swb;
+
+	    if (octl != nctl)		/* make the change if any */
+		bridge->b_wid_control = nctl;
+
+	    *bfp = bfn;			/* record the assignment */
+
+#if DEBUG && PCI_DEBUG
+	    printk("pcibr_addr_pci_to_xio: swap for space %d  set to%s%s\n",
+		    space, 
+		    bfn & PCIIO_BYTE_STREAM ? " BYTE_STREAM" : "",
+		    bfn & PCIIO_WORD_VALUES ? " WORD_VALUES" : "");
+#endif
+	}
+    }
+  done:
+    pcibr_unlock(pcibr_soft, s);
+    return xio_addr;
+}
+
+/*ARGSUSED6 */
+pcibr_piomap_t
+pcibr_piomap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   pciio_space_t space,
+		   iopaddr_t pci_addr,
+		   size_t req_size,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pcibr_info_t	    pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    pcibr_piomap_t         *mapptr;
+    pcibr_piomap_t          maplist;
+    pcibr_piomap_t          pcibr_piomap;
+    iopaddr_t               xio_addr;
+    xtalk_piomap_t          xtalk_piomap;
+    unsigned long           s;
+
+    /* Make sure that the req sizes are non-zero */
+    if ((req_size < 1) || (req_size_max < 1))
+	return NULL;
+
+    /*
+     * Code to translate slot/space/addr
+     * into xio_addr is common between
+     * this routine and pcibr_piotrans_addr.
+     */
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    /* Check the piomap list to see if there is already an allocated
+     * piomap entry but not in use. If so use that one. Otherwise
+     * allocate a new piomap entry and add it to the piomap list
+     */
+    mapptr = &(pcibr_info->f_piomap);
+
+    s = pcibr_lock(pcibr_soft);
+    for (pcibr_piomap = *mapptr;
+	 pcibr_piomap != NULL;
+	 pcibr_piomap = pcibr_piomap->bp_next) {
+	if (pcibr_piomap->bp_mapsz == 0)
+	    break;
+    }
+
+    if (pcibr_piomap)
+	mapptr = NULL;
+    else {
+	pcibr_unlock(pcibr_soft, s);
+	NEW(pcibr_piomap);
+    }
+
+    pcibr_piomap->bp_dev = pconn_vhdl;
+    pcibr_piomap->bp_slot = pciio_slot;
+    pcibr_piomap->bp_flags = flags;
+    pcibr_piomap->bp_space = space;
+    pcibr_piomap->bp_pciaddr = pci_addr;
+    pcibr_piomap->bp_mapsz = req_size;
+    pcibr_piomap->bp_soft = pcibr_soft;
+    pcibr_piomap->bp_toc[0] = ATOMIC_INIT(0);
+
+    if (mapptr) {
+	s = pcibr_lock(pcibr_soft);
+	maplist = *mapptr;
+	pcibr_piomap->bp_next = maplist;
+	*mapptr = pcibr_piomap;
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+
+    if (pcibr_piomap) {
+	xtalk_piomap =
+	    xtalk_piomap_alloc(xconn_vhdl, 0,
+			       xio_addr,
+			       req_size, req_size_max,
+			       flags & PIOMAP_FLAGS);
+	if (xtalk_piomap) {
+	    pcibr_piomap->bp_xtalk_addr = xio_addr;
+	    pcibr_piomap->bp_xtalk_pio = xtalk_piomap;
+	} else {
+	    pcibr_piomap->bp_mapsz = 0;
+	    pcibr_piomap = 0;
+	}
+    }
+    return pcibr_piomap;
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_free(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_free(pcibr_piomap->bp_xtalk_pio);
+    pcibr_piomap->bp_xtalk_pio = 0;
+    pcibr_piomap->bp_mapsz = 0;
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piomap_addr(pcibr_piomap_t pcibr_piomap,
+		  iopaddr_t pci_addr,
+		  size_t req_size)
+{
+    return xtalk_piomap_addr(pcibr_piomap->bp_xtalk_pio,
+			     pcibr_piomap->bp_xtalk_addr +
+			     pci_addr - pcibr_piomap->bp_pciaddr,
+			     req_size);
+}
+
+/*ARGSUSED */
+void
+pcibr_piomap_done(pcibr_piomap_t pcibr_piomap)
+{
+    xtalk_piomap_done(pcibr_piomap->bp_xtalk_pio);
+}
+
+/*ARGSUSED */
+caddr_t
+pcibr_piotrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    pciio_space_t space,
+		    iopaddr_t pci_addr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    iopaddr_t               xio_addr;
+
+    xio_addr = pcibr_addr_pci_to_xio(pconn_vhdl, pciio_slot, space, pci_addr, req_size, flags);
+
+    if (xio_addr == XIO_NOWHERE)
+	return NULL;
+
+    return xtalk_piotrans_addr(xconn_vhdl, 0, xio_addr, req_size, flags & PIOMAP_FLAGS);
+}
+
+/*
+ * PIO Space allocation and management.
+ *      Allocate and Manage the PCI PIO space (mem and io space)
+ *      This routine is pretty simplistic at this time, and
+ *      does pretty trivial management of allocation and freeing..
+ *      The current scheme is prone for fragmentation..
+ *      Change the scheme to use bitmaps.
+ */
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_piospace_alloc(devfs_handle_t pconn_vhdl,
+		     device_desc_t dev_desc,
+		     pciio_space_t space,
+		     size_t req_size,
+		     size_t alignment)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_info_t            pciio_info = &pcibr_info->f_c;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+
+    iopaddr_t              *pciaddr, *pcilast;
+    iopaddr_t               start_addr;
+    size_t                  align_mask;
+
+    /*
+     * Check for proper alignment
+     */
+    ASSERT(alignment >= NBPP);
+    ASSERT((alignment & (alignment - 1)) == 0);
+
+    align_mask = alignment - 1;
+    s = pcibr_lock(pcibr_soft);
+
+    /*
+     * First look if a previously allocated chunk exists.
+     */
+    if ((piosp = pcibr_info->f_piospace)) {
+	/*
+	 * Look through the list for a right sized free chunk.
+	 */
+	do {
+	    if (piosp->free &&
+		(piosp->space == space) &&
+		(piosp->count >= req_size) &&
+		!(piosp->start & align_mask)) {
+		piosp->free = 0;
+		pcibr_unlock(pcibr_soft, s);
+		return piosp->start;
+	    }
+	    piosp = piosp->next;
+	} while (piosp);
+    }
+    ASSERT(!piosp);
+
+    switch (space) {
+    case PCIIO_SPACE_IO:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_io_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_io_last;
+	break;
+    case PCIIO_SPACE_MEM:
+    case PCIIO_SPACE_MEM32:
+	pciaddr = &pcibr_soft->bs_spinfo.pci_mem_base;
+	pcilast = &pcibr_soft->bs_spinfo.pci_mem_last;
+	break;
+    default:
+	ASSERT(0);
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+
+    start_addr = *pciaddr;
+
+    /*
+     * Align start_addr.
+     */
+    if (start_addr & align_mask)
+	start_addr = (start_addr + align_mask) & ~align_mask;
+
+    if ((start_addr + req_size) > *pcilast) {
+	/*
+	 * If too big a request, reject it.
+	 */
+	pcibr_unlock(pcibr_soft, s);
+	return 0;
+    }
+    *pciaddr = (start_addr + req_size);
+
+    NEW(piosp);
+    piosp->free = 0;
+    piosp->space = space;
+    piosp->start = start_addr;
+    piosp->count = req_size;
+    piosp->next = pcibr_info->f_piospace;
+    pcibr_info->f_piospace = piosp;
+
+    pcibr_unlock(pcibr_soft, s);
+    return start_addr;
+}
+
+/*ARGSUSED */
+void
+pcibr_piospace_free(devfs_handle_t pconn_vhdl,
+		    pciio_space_t space,
+		    iopaddr_t pciaddr,
+		    size_t req_size)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+
+    pciio_piospace_t        piosp;
+    unsigned long           s;
+    char                    name[1024];
+
+    /*
+     * Look through the bridge data structures for the pciio_piospace_t
+     * structure corresponding to  'pciaddr'
+     */
+    s = pcibr_lock(pcibr_soft);
+    piosp = pcibr_info->f_piospace;
+    while (piosp) {
+	/*
+	 * Piospace free can only be for the complete
+	 * chunk and not parts of it..
+	 */
+	if (piosp->start == pciaddr) {
+	    if (piosp->count == req_size)
+		break;
+	    /*
+	     * Improper size passed for freeing..
+	     * Print a message and break;
+	     */
+	    hwgraph_vertex_name_get(pconn_vhdl, name, 1024);
+	    printk(KERN_WARNING  "pcibr_piospace_free: error");
+	    printk(KERN_WARNING  "Device %s freeing size (0x%lx) different than allocated (0x%lx)",
+					name, req_size, piosp->count);
+	    printk(KERN_WARNING  "Freeing 0x%lx instead", piosp->count);
+	    break;
+	}
+	piosp = piosp->next;
+    }
+
+    if (!piosp) {
+	printk(KERN_WARNING  
+		"pcibr_piospace_free: Address 0x%lx size 0x%lx - No match\n",
+		pciaddr, req_size);
+	pcibr_unlock(pcibr_soft, s);
+	return;
+    }
+    piosp->free = 1;
+    pcibr_unlock(pcibr_soft, s);
+    return;
+}
+
+/* =====================================================================
+ *    DMA MANAGEMENT
+ *
+ *      The Bridge ASIC provides three methods of doing
+ *      DMA: via a "direct map" register available in
+ *      32-bit PCI space (which selects a contiguous 2G
+ *      address space on some other widget), via
+ *      "direct" addressing via 64-bit PCI space (all
+ *      destination information comes from the PCI
+ *      address, including transfer attributes), and via
+ *      a "mapped" region that allows a bunch of
+ *      different small mappings to be established with
+ *      the PMU.
+ *
+ *      For efficiency, we most prefer to use the 32-bit
+ *      direct mapping facility, since it requires no
+ *      resource allocations. The advantage of using the
+ *      PMU over the 64-bit direct is that single-cycle
+ *      PCI addressing can be used; the advantage of
+ *      using 64-bit direct over PMU addressing is that
+ *      we do not have to allocate entries in the PMU.
+ */
+
+/*
+ * Convert PCI-generic software flags and Bridge-specific software flags
+ * into Bridge-specific Direct Map attribute bits.
+ */
+static iopaddr_t
+pcibr_flags_to_d64(unsigned flags, pcibr_soft_t pcibr_soft)
+{
+    iopaddr_t               attributes = 0;
+
+    /* Sanity check: Bridge only allows use of VCHAN1 via 64-bit addrs */
+#ifdef LATER
+    ASSERT_ALWAYS(!(flags & PCIBR_VCHAN1) || (flags & PCIIO_DMA_A64));
+#endif
+
+    /* Generic macro flags
+     */
+    if (flags & PCIIO_DMA_DATA) {	/* standard data channel */
+	attributes &= ~PCI64_ATTR_BAR;	/* no barrier bit */
+	attributes |= PCI64_ATTR_PREF;	/* prefetch on */
+    }
+    if (flags & PCIIO_DMA_CMD) {	/* standard command channel */
+	attributes |= PCI64_ATTR_BAR;	/* barrier bit on */
+	attributes &= ~PCI64_ATTR_PREF;	/* disable prefetch */
+    }
+    /* Generic detail flags
+     */
+    if (flags & PCIIO_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIIO_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    /* the swap bit is in the address attributes for xbridge */
+    if (pcibr_soft->bs_xbridge) {
+    	if (flags & PCIIO_BYTE_STREAM)
+        	attributes |= PCI64_ATTR_SWAP;
+    	if (flags & PCIIO_WORD_VALUES)
+        	attributes &= ~PCI64_ATTR_SWAP;
+    }
+
+    /* Provider-specific flags
+     */
+    if (flags & PCIBR_BARRIER)
+	attributes |= PCI64_ATTR_BAR;
+    if (flags & PCIBR_NOBARRIER)
+	attributes &= ~PCI64_ATTR_BAR;
+
+    if (flags & PCIBR_PREFETCH)
+	attributes |= PCI64_ATTR_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	attributes &= ~PCI64_ATTR_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	attributes |= PCI64_ATTR_PREC;
+    if (flags & PCIBR_NOPRECISE)
+	attributes &= ~PCI64_ATTR_PREC;
+
+    if (flags & PCIBR_VCHAN1)
+	attributes |= PCI64_ATTR_VIRTUAL;
+    if (flags & PCIBR_VCHAN0)
+	attributes &= ~PCI64_ATTR_VIRTUAL;
+
+    return (attributes);
+}
+
+/*ARGSUSED */
+pcibr_dmamap_t
+pcibr_dmamap_alloc(devfs_handle_t pconn_vhdl,
+		   device_desc_t dev_desc,
+		   size_t req_size_max,
+		   unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            slot;
+    xwidgetnum_t            xio_port;
+
+    xtalk_dmamap_t          xtalk_dmamap;
+    pcibr_dmamap_t          pcibr_dmamap;
+    int                     ate_count;
+    int                     ate_index;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    /*
+     * On SNIA64, these maps are pre-allocated because pcibr_dmamap_alloc()
+     * can be called within an interrupt thread.
+     */
+    pcibr_dmamap = (pcibr_dmamap_t)get_free_pciio_dmamap(pcibr_soft->bs_vhdl);
+
+    if (!pcibr_dmamap)
+	return 0;
+
+    xtalk_dmamap = xtalk_dmamap_alloc(xconn_vhdl, dev_desc, req_size_max,
+				      flags & DMAMAP_FLAGS);
+    if (!xtalk_dmamap) {
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_attach: xtalk_dmamap_alloc failed\n");
+#endif
+	free_pciio_dmamap(pcibr_dmamap);
+	return 0;
+    }
+    xio_port = pcibr_soft->bs_mxid;
+    slot = pciio_info_slot_get(pciio_info);
+
+    pcibr_dmamap->bd_dev = pconn_vhdl;
+    pcibr_dmamap->bd_slot = slot;
+    pcibr_dmamap->bd_soft = pcibr_soft;
+    pcibr_dmamap->bd_xtalk = xtalk_dmamap;
+    pcibr_dmamap->bd_max_size = req_size_max;
+    pcibr_dmamap->bd_xio_port = xio_port;
+
+    if (flags & PCIIO_DMA_A64) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    iopaddr_t               pci_addr;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+	    /* Device is capable of A64 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     */
+
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_pci_addr = pci_addr;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct64\n");
+#endif
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct64\n");
+#endif
+	flags &= ~PCIIO_DMA_A64;
+    }
+    if (flags & PCIIO_FIXED) {
+	/* warning: mappings may fail later,
+	 * if direct32 can't get to the address.
+	 */
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_D32_BITS)) {
+	    /* User desires DIRECT A32 operations,
+	     * and the attributes of the DMA are
+	     * consistant with any previous DMA
+	     * mappings using shared resources.
+	     * Mapping calls may fail if target
+	     * is outside the direct32 range.
+	     */
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using direct32\n");
+#endif
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_xio_addr = pcibr_soft->bs_dir_xbase;
+	    pcibr_dmamap->bd_pci_addr = PCI32_DIRECT_BASE;
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use direct32\n");
+#endif
+	/* If the user demands FIXED and we can't
+	 * give it to him, fail.
+	 */
+	xtalk_dmamap_free(xtalk_dmamap);
+	free_pciio_dmamap(pcibr_dmamap);
+	return 0;
+    }
+    /*
+     * Allocate Address Translation Entries from the mapping RAM.
+     * Unless the PCIBR_NO_ATE_ROUNDUP flag is specified,
+     * the maximum number of ATEs is based on the worst-case
+     * scenario, where the requested target is in the
+     * last byte of an ATE; thus, mapping IOPGSIZE+2
+     * does end up requiring three ATEs.
+     */
+    if (!(flags & PCIBR_NO_ATE_ROUNDUP)) {
+	ate_count = IOPG((IOPGSIZE - 1)	/* worst case start offset */
+		     +req_size_max	/* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    } else {	/* assume requested target is page aligned */
+	ate_count = IOPG(req_size_max   /* max mapping bytes */
+		     - 1) + 1;		/* round UP */
+    }
+
+    ate_index = pcibr_ate_alloc(pcibr_soft, ate_count);
+
+    if (ate_index != -1) {
+	if (!pcibr_try_set_device(pcibr_soft, slot, flags, BRIDGE_DEV_PMU_BITS)) {
+	    bridge_ate_t            ate_proto;
+	    int                     have_rrbs;
+	    int                     min_rrbs;
+
+#if PCIBR_ATE_DEBUG
+	    printk("pcibr_dmamap_alloc: using PMU\n");
+#endif
+
+	    ate_proto = pcibr_flags_to_ate(flags);
+
+	    pcibr_dmamap->bd_flags = flags;
+	    pcibr_dmamap->bd_pci_addr =
+		PCI32_MAPPED_BASE + IOPGSIZE * ate_index;
+	    /*
+	     * for xbridge the byte-swap bit == bit 29 of PCI address
+	     */
+	    if (pcibr_soft->bs_xbridge) {
+		    if (flags & PCIIO_BYTE_STREAM)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    /*
+		     * If swap was set in bss_device in pcibr_endian_set()
+		     * we need to change the address bit.
+		     */
+		    if (pcibr_soft->bs_slot[slot].bss_device & 
+							BRIDGE_DEV_SWAP_PMU)
+			    ATE_SWAP_ON(pcibr_dmamap->bd_pci_addr);
+		    if (flags & PCIIO_WORD_VALUES)
+			    ATE_SWAP_OFF(pcibr_dmamap->bd_pci_addr);
+	    }
+	    pcibr_dmamap->bd_xio_addr = 0;
+	    pcibr_dmamap->bd_ate_ptr = pcibr_ate_addr(pcibr_soft, ate_index);
+	    pcibr_dmamap->bd_ate_index = ate_index;
+	    pcibr_dmamap->bd_ate_count = ate_count;
+	    pcibr_dmamap->bd_ate_proto = ate_proto;
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << slot))) {
+		have_rrbs = pcibr_soft->bs_rrb_valid[slot];
+		if (have_rrbs < 2) {
+		    if (ate_proto & ATE_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, slot, min_rrbs - have_rrbs);
+		}
+	    }
+	    if (ate_index >= pcibr_soft->bs_int_ate_size && 
+				!pcibr_soft->bs_xbridge) {
+		bridge_t               *bridge = pcibr_soft->bs_base;
+		volatile unsigned      *cmd_regp;
+		unsigned                cmd_reg;
+		unsigned long           s;
+
+		pcibr_dmamap->bd_flags |= PCIBR_DMAMAP_SSRAM;
+
+		s = pcibr_lock(pcibr_soft);
+		cmd_regp = &(bridge->
+			     b_type0_cfg_dev[slot].
+			     l[PCI_CFG_COMMAND / 4]);
+		cmd_reg = *cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_pointer = cmd_regp;
+		pcibr_soft->bs_slot[slot].bss_cmd_shadow = cmd_reg;
+		pcibr_unlock(pcibr_soft, s);
+	    }
+	    return pcibr_dmamap;
+	}
+#if PCIBR_ATE_DEBUG
+	printk("pcibr_dmamap_alloc: unable to use PMU\n");
+#endif
+	pcibr_ate_free(pcibr_soft, ate_index, ate_count);
+    }
+    /* total failure: sorry, you just can't
+     * get from here to there that way.
+     */
+#if PCIBR_ATE_DEBUG
+    printk("pcibr_dmamap_alloc: complete failure.\n");
+#endif
+    xtalk_dmamap_free(xtalk_dmamap);
+    free_pciio_dmamap(pcibr_dmamap);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_free(pcibr_dmamap_t pcibr_dmamap)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_dmamap->bd_soft;
+    pciio_slot_t            slot = pcibr_dmamap->bd_slot;
+
+    unsigned                flags = pcibr_dmamap->bd_flags;
+
+    /* Make sure that bss_ext_ates_active
+     * is properly kept up to date.
+     */
+
+    if (PCIBR_DMAMAP_BUSY & flags)
+	if (PCIBR_DMAMAP_SSRAM & flags)
+	    atomic_dec(&(pcibr_soft->bs_slot[slot]. bss_ext_ates_active));
+
+    xtalk_dmamap_free(pcibr_dmamap->bd_xtalk);
+
+    if (pcibr_dmamap->bd_flags & PCIIO_DMA_A64) {
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_D64_BITS);
+    }
+    if (pcibr_dmamap->bd_ate_count) {
+	pcibr_ate_free(pcibr_dmamap->bd_soft,
+		       pcibr_dmamap->bd_ate_index,
+		       pcibr_dmamap->bd_ate_count);
+	pcibr_release_device(pcibr_soft, slot, BRIDGE_DEV_PMU_BITS);
+    }
+
+    free_pciio_dmamap(pcibr_dmamap);
+}
+
+/*
+ *    pcibr_addr_xio_to_pci: given a PIO range, hand
+ *      back the corresponding base PCI MEM address;
+ *      this is used to short-circuit DMA requests that
+ *      loop back onto this PCI bus.
+ */
+static iopaddr_t
+pcibr_addr_xio_to_pci(pcibr_soft_t soft,
+		      iopaddr_t xio_addr,
+		      size_t req_size)
+{
+    iopaddr_t               xio_lim = xio_addr + req_size - 1;
+    iopaddr_t               pci_addr;
+    pciio_slot_t            slot;
+
+    if ((xio_addr >= BRIDGE_PCI_MEM32_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM32_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM32_BASE;
+	return pci_addr;
+    }
+    if ((xio_addr >= BRIDGE_PCI_MEM64_BASE) &&
+	(xio_lim <= BRIDGE_PCI_MEM64_LIMIT)) {
+	pci_addr = xio_addr - BRIDGE_PCI_MEM64_BASE;
+	return pci_addr;
+    }
+    for (slot = 0; slot < 8; ++slot)
+	if ((xio_addr >= BRIDGE_DEVIO(slot)) &&
+	    (xio_lim < BRIDGE_DEVIO(slot + 1))) {
+	    bridgereg_t             dev;
+
+	    dev = soft->bs_slot[slot].bss_device;
+	    pci_addr = dev & BRIDGE_DEV_OFF_MASK;
+	    pci_addr <<= BRIDGE_DEV_OFF_ADDR_SHFT;
+	    pci_addr += xio_addr - BRIDGE_DEVIO(slot);
+	    return (dev & BRIDGE_DEV_DEV_IO_MEM) ? pci_addr : PCI_NOWHERE;
+	}
+    return 0;
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmamap_addr(pcibr_dmamap_t pcibr_dmamap,
+		  paddr_t paddr,
+		  size_t req_size)
+{
+    pcibr_soft_t            pcibr_soft;
+    iopaddr_t               xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    unsigned                flags;
+
+    ASSERT(pcibr_dmamap != NULL);
+    ASSERT(req_size > 0);
+    ASSERT(req_size <= pcibr_dmamap->bd_max_size);
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    flags = pcibr_dmamap->bd_flags;
+
+    xio_addr = xtalk_dmamap_addr(pcibr_dmamap->bd_xtalk, paddr, req_size);
+    if (XIO_PACKED(xio_addr)) {
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+    } else
+	xio_port = pcibr_dmamap->bd_xio_port;
+
+    /* If this DMA is to an address that
+     * refers back to this Bridge chip,
+     * reduce it back to the correct
+     * PCI MEM address.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+    } else if (flags & PCIIO_DMA_A64) {
+	/* A64 DMA:
+	 * always use 64-bit direct mapping,
+	 * which always works.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	/* attributes are already bundled up into bd_pci_addr.
+	 */
+	pci_addr = pcibr_dmamap->bd_pci_addr
+	    | ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT)
+	    | xio_addr;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    pci_addr &= ~PCI64_ATTR_PREF;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct64):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else if (flags & PCIIO_FIXED) {
+	/* A32 direct DMA:
+	 * always use 32-bit direct mapping,
+	 * which may fail.
+	 * Device(x) was set up during
+	 * dmamap allocation.
+	 */
+
+	if (xio_port != pcibr_soft->bs_dir_xport)
+	    pci_addr = 0;		/* wrong DIDN */
+	else if (xio_addr < pcibr_dmamap->bd_xio_addr)
+	    pci_addr = 0;		/* out of range */
+	else if ((xio_addr + req_size) >
+		 (pcibr_dmamap->bd_xio_addr + BRIDGE_DMA_DIRECT_SIZE))
+	    pci_addr = 0;		/* out of range */
+	else
+	    pci_addr = pcibr_dmamap->bd_pci_addr +
+		xio_addr - pcibr_dmamap->bd_xio_addr;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+	printk("pcibr_dmamap_addr (direct32):\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\tXIO port 0x%x offset 0x%x\n"
+		"\treturning PCI 0x%x\n",
+		paddr, paddr + req_size - 1,
+		xio_port, xio_addr, pci_addr);
+#endif
+    } else {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+	iopaddr_t               offset = IOPGOFF(xio_addr);
+	bridge_ate_t            ate_proto = pcibr_dmamap->bd_ate_proto;
+	int                     ate_count = IOPG(offset + req_size - 1) + 1;
+
+	int                     ate_index = pcibr_dmamap->bd_ate_index;
+	unsigned                cmd_regs[8];
+	unsigned                s;
+
+#if PCIBR_FREEZE_TIME
+	int                     ate_total = ate_count;
+	unsigned                freeze_time;
+#endif
+
+#if PCIBR_ATE_DEBUG
+	bridge_ate_t            ate_cmp;
+	bridge_ate_p            ate_cptr;
+	unsigned                ate_lo, ate_hi;
+	int                     ate_bad = 0;
+	int                     ate_rbc = 0;
+#endif
+	bridge_ate_p            ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	bridge_ate_t            ate;
+
+	/* Bridge Hardware WAR #482836:
+	 * If the transfer is not cache aligned
+	 * and the Bridge Rev is <= B, force
+	 * prefetch to be off.
+	 */
+	if (flags & PCIBR_NOPREFETCH)
+	    ate_proto &= ~ATE_PREF;
+
+	ate = ate_proto
+	    | (xio_port << ATE_TIDSHIFT)
+	    | (xio_addr - offset);
+
+	pci_addr = pcibr_dmamap->bd_pci_addr + offset;
+
+	/* Fill in our mapping registers
+	 * with the appropriate xtalk data,
+	 * and hand back the PCI address.
+	 */
+
+	ASSERT(ate_count > 0);
+	if (ate_count <= pcibr_dmamap->bd_ate_count) {
+		ATE_FREEZE();
+		ATE_WRITE();
+		ATE_THAW();
+		bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	} else {
+		/* The number of ATE's required is greater than the number
+		 * allocated for this map. One way this can happen is if
+		 * pcibr_dmamap_alloc() was called with the PCIBR_NO_ATE_ROUNDUP
+		 * flag, and then when that map is used (right now), the
+		 * target address tells us we really did need to roundup.
+		 * The other possibility is that the map is just plain too
+		 * small to handle the requested target area.
+		 */
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING "pcibr_dmamap_addr :\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\tate_count 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			paddr, paddr + req_size - 1,
+			ate_count, pcibr_dmamap->bd_ate_count);
+#endif
+		pci_addr = 0;
+	}
+
+    }
+    return pci_addr;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmamap_list(pcibr_dmamap_t pcibr_dmamap,
+		  alenlist_t palenlist,
+		  unsigned flags)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge=NULL;
+
+    unsigned                al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+    int                     inplace = flags & PCIIO_INPLACE;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist;
+    size_t                  length;
+    iopaddr_t               offset;
+    unsigned                direct64;
+    int                     ate_index = 0;
+    int                     ate_count = 0;
+    int                     ate_total = 0;
+    bridge_ate_p            ate_ptr = (bridge_ate_p)0;
+    bridge_ate_t            ate_proto = (bridge_ate_t)0;
+    bridge_ate_t            ate_prev;
+    bridge_ate_t            ate;
+    alenaddr_t              xio_addr;
+    xwidgetnum_t            xio_port;
+    iopaddr_t               pci_addr;
+    alenaddr_t              new_addr;
+    unsigned                cmd_regs[8];
+    unsigned                s = 0;
+
+#if PCIBR_FREEZE_TIME
+    unsigned                freeze_time;
+#endif
+    int			    ate_freeze_done = 0;	/* To pair ATE_THAW
+							 * with an ATE_FREEZE
+							 */
+
+    pcibr_soft = pcibr_dmamap->bd_soft;
+
+    xtalk_alenlist = xtalk_dmamap_list(pcibr_dmamap->bd_xtalk, palenlist,
+				       flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    direct64 = pcibr_dmamap->bd_flags & PCIIO_DMA_A64;
+    if (!direct64) {
+	bridge = pcibr_soft->bs_base;
+	ate_ptr = pcibr_dmamap->bd_ate_ptr;
+	ate_index = pcibr_dmamap->bd_ate_index;
+	ate_proto = pcibr_dmamap->bd_ate_proto;
+	ATE_FREEZE();
+	ate_freeze_done = 1;	/* Remember that we need to do an ATE_THAW */
+    }
+    pci_addr = pcibr_dmamap->bd_pci_addr;
+
+    ate_prev = 0;			/* matches no valid ATEs */
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &length, al_flags)) {
+	if (XIO_PACKED(xio_addr)) {
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_dmamap->bd_xio_port;
+
+	if (xio_port == pcibr_soft->bs_xid) {
+	    new_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, length);
+	    if (new_addr == PCI_NOWHERE)
+		goto fail;
+	} else if (direct64) {
+	    new_addr = pci_addr | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Bridge Hardware WAR #482836:
+	     * If the transfer is not cache aligned
+	     * and the Bridge Rev is <= B, force
+	     * prefetch to be off.
+	     */
+	    if (flags & PCIBR_NOPREFETCH)
+		new_addr &= ~PCI64_ATTR_PREF;
+
+	} else {
+	    /* calculate the ate value for
+	     * the first address. If it
+	     * matches the previous
+	     * ATE written (ie. we had
+	     * multiple blocks in the
+	     * same IOPG), then back up
+	     * and reuse that ATE.
+	     *
+	     * We are NOT going to
+	     * aggressively try to
+	     * reuse any other ATEs.
+	     */
+	    offset = IOPGOFF(xio_addr);
+	    ate = ate_proto
+		| (xio_port << ATE_TIDSHIFT)
+		| (xio_addr - offset);
+	    if (ate == ate_prev) {
+#if PCIBR_ATE_DEBUG
+		printk("pcibr_dmamap_list: ATE share\n");
+#endif
+		ate_ptr--;
+		ate_index--;
+		pci_addr -= IOPGSIZE;
+	    }
+	    new_addr = pci_addr + offset;
+
+	    /* Fill in the hardware ATEs
+	     * that contain this block.
+	     */
+	    ate_count = IOPG(offset + length - 1) + 1;
+	    ate_total += ate_count;
+
+	    /* Ensure that this map contains enough ATE's */
+	    if (ate_total > pcibr_dmamap->bd_ate_count) {
+#if PCIBR_ATE_DEBUG
+		printk(KERN_WARNING "pcibr_dmamap_list :\n"
+			"\twanted xio_addr [0x%x..0x%x]\n"
+			"\tate_total 0x%x bd_ate_count 0x%x\n"
+			"\tATE's required > number allocated\n",
+			xio_addr, xio_addr + length - 1,
+			ate_total, pcibr_dmamap->bd_ate_count);
+#endif
+		goto fail;
+	    }
+
+	    ATE_WRITE();
+
+	    ate_index += ate_count;
+	    ate_ptr += ate_count;
+
+	    ate_count <<= IOPFNSHIFT;
+	    ate += ate_count;
+	    pci_addr += ate_count;
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &new_addr, &length, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				new_addr, length, al_flags))
+		goto fail;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+
+
+    /* In case an ATE_FREEZE was done do the ATE_THAW to unroll all the
+     * changes that ATE_FREEZE has done to implement the external SSRAM
+     * bug workaround.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    return pciio_alenlist;
+
+  fail:
+    /* There are various points of failure after doing an ATE_FREEZE
+     * We need to do an ATE_THAW. Otherwise the ATEs are locked forever.
+     * The decision to do an ATE_THAW needs to be based on whether a
+     * an ATE_FREEZE was done before.
+     */
+    if (ate_freeze_done) {
+	ATE_THAW();
+	bridge->b_wid_tflush;
+    }
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_dmamap_done(pcibr_dmamap_t pcibr_dmamap)
+{
+    /*
+     * We could go through and invalidate ATEs here;
+     * for performance reasons, we don't.
+     * We also don't enforce the strict alternation
+     * between _addr/_list and _done, but Hub does.
+     */
+
+    if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_BUSY) {
+	pcibr_dmamap->bd_flags &= ~PCIBR_DMAMAP_BUSY;
+
+	if (pcibr_dmamap->bd_flags & PCIBR_DMAMAP_SSRAM)
+	    atomic_dec(&(pcibr_dmamap->bd_soft->bs_slot[pcibr_dmamap->bd_slot]. bss_ext_ates_active));
+    }
+    xtalk_dmamap_done(pcibr_dmamap->bd_xtalk);
+}
+
+
+/*
+ * For each bridge, the DIR_OFF value in the Direct Mapping Register
+ * determines the PCI to Crosstalk memory mapping to be used for all
+ * 32-bit Direct Mapping memory accesses. This mapping can be to any
+ * node in the system. This function will return that compact node id.
+ */
+
+/*ARGSUSED */
+cnodeid_t
+pcibr_get_dmatrans_node(devfs_handle_t pconn_vhdl)
+{
+
+	pciio_info_t	pciio_info = pciio_info_get(pconn_vhdl);
+	pcibr_soft_t	pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+	return(NASID_TO_COMPACT_NODEID(NASID_GET(pcibr_soft->bs_dir_xbase)));
+}
+
+/*ARGSUSED */
+iopaddr_t
+pcibr_dmatrans_addr(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    paddr_t paddr,
+		    size_t req_size,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+
+    xwidgetnum_t            xio_port;
+    iopaddr_t               xio_addr;
+    iopaddr_t               pci_addr;
+
+    int                     have_rrbs;
+    int                     min_rrbs;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    xio_addr = xtalk_dmatrans_addr(xconn_vhdl, 0, paddr, req_size,
+				   flags & DMAMAP_FLAGS);
+
+    if (!xio_addr) {
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+	return 0;
+    }
+    /*
+     * find which XIO port this goes to.
+     */
+    if (XIO_PACKED(xio_addr)) {
+	if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	    return 0;
+	}
+	xio_port = XIO_PORT(xio_addr);
+	xio_addr = XIO_ADDR(xio_addr);
+
+    } else
+	xio_port = pcibr_soft->bs_mxid;
+
+    /*
+     * If this DMA comes back to us,
+     * return the PCI MEM address on
+     * which it would land, or NULL
+     * if the target is something
+     * on bridge other than PCI MEM.
+     */
+    if (xio_port == pcibr_soft->bs_xid) {
+	pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, req_size);
+	return pci_addr;
+    }
+    /* If the caller can use A64, try to
+     * satisfy the request with the 64-bit
+     * direct map. This can fail if the
+     * configuration bits in Device(x)
+     * conflict with our flags.
+     */
+
+    if (flags & PCIIO_DMA_A64) {
+	pci_addr = slotp->bss_d64_base;
+	if (!(flags & PCIBR_VCHAN1))
+	    flags |= PCIBR_VCHAN0;
+	if ((pci_addr != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+#if DEBUG && PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr);
+#endif
+	    return (pci_addr);
+	}
+	if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS)) {
+	    pci_addr = pcibr_flags_to_d64(flags, pcibr_soft);
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_addr;
+	    pci_addr |= xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+
+	    /* Make sure we have an RRB (or two).
+	     */
+	    if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		if (flags & PCIBR_VCHAN1)
+		    pciio_slot += PCIBR_RRB_SLOT_VIRTUAL;
+		have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		if (have_rrbs < 2) {
+		    if (pci_addr & PCI64_ATTR_PREF)
+			min_rrbs = 2;
+		    else
+			min_rrbs = 1;
+		    if (have_rrbs < min_rrbs)
+			do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		}
+	    }
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+	    if (xio_addr != 0x20000000)
+#endif
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tdirect 64bit address is 0x%x\n"
+			"\tnew flags: 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, pci_addr, (uint64_t) flags);
+#endif
+	    return (pci_addr);
+	}
+	/* our flags conflict with Device(x).
+	 */
+	flags = flags
+	    & ~PCIIO_DMA_A64
+	    & ~PCIBR_VCHAN0
+	    ;
+
+#if PCIBR_DMA_DEBUG
+	printk("pcibr_dmatrans_addr:\n"
+		"\tpciio connection point %v\n"
+		"\txtalk connection point %v\n"
+		"\twanted paddr [0x%x..0x%x]\n"
+		"\txtalk_dmatrans_addr returned 0x%x\n"
+		"\tUnable to set Device(x) bits for Direct-64\n",
+		pconn_vhdl, xconn_vhdl,
+		paddr, paddr + req_size - 1,
+		xio_addr);
+#endif
+    }
+    /* Try to satisfy the request with the 32-bit direct
+     * map. This can fail if the configuration bits in
+     * Device(x) conflict with our flags, or if the
+     * target address is outside where DIR_OFF points.
+     */
+    {
+	size_t                  map_size = 1ULL << 31;
+	iopaddr_t               xio_base = pcibr_soft->bs_dir_xbase;
+	iopaddr_t               offset = xio_addr - xio_base;
+	iopaddr_t               endoff = req_size + offset;
+
+	if ((req_size > map_size) ||
+	    (xio_addr < xio_base) ||
+	    (xio_port != pcibr_soft->bs_dir_xport) ||
+	    (endoff > map_size)) {
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\txio region outside direct32 target\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	} else {
+	    pci_addr = slotp->bss_d32_base;
+	    if ((pci_addr != PCIBR_D32_BASE_UNSET) &&
+		(flags == slotp->bss_d32_flags)) {
+
+		pci_addr |= offset;
+
+#if DEBUG && PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr: [reuse]\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n"
+			"\tmapped via direct32 offset 0x%x\n"
+			"\twill DMA via pci addr 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr, offset, pci_addr);
+#endif
+		return (pci_addr);
+	    }
+	    if (!pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS)) {
+
+		pci_addr = PCI32_DIRECT_BASE;
+		slotp->bss_d32_flags = flags;
+		slotp->bss_d32_base = pci_addr;
+		pci_addr |= offset;
+
+		/* Make sure we have an RRB (or two).
+		 */
+		if (!(pcibr_soft->bs_rrb_fixed & (1 << pciio_slot))) {
+		    have_rrbs = pcibr_soft->bs_rrb_valid[pciio_slot];
+		    if (have_rrbs < 2) {
+			if (slotp->bss_device & BRIDGE_DEV_PREF)
+			    min_rrbs = 2;
+			else
+			    min_rrbs = 1;
+			if (have_rrbs < min_rrbs)
+			    do_pcibr_rrb_autoalloc(pcibr_soft, pciio_slot, min_rrbs - have_rrbs);
+		    }
+		}
+#if PCIBR_DMA_DEBUG
+#if HWG_PERF_CHECK
+		if (xio_addr != 0x20000000)
+#endif
+		    printk("pcibr_dmatrans_addr:\n"
+			    "\tpciio connection point %v\n"
+			    "\txtalk connection point %v\n"
+			    "\twanted paddr [0x%x..0x%x]\n"
+			    "\txtalk_dmatrans_addr returned 0x%x\n"
+			    "\tmapped via direct32 offset 0x%x\n"
+			    "\twill DMA via pci addr 0x%x\n"
+			    "\tnew flags: 0x%x\n",
+			    pconn_vhdl, xconn_vhdl,
+			    paddr, paddr + req_size - 1,
+			    xio_addr, offset, pci_addr, (uint64_t) flags);
+#endif
+		return (pci_addr);
+	    }
+	    /* our flags conflict with Device(x).
+	     */
+#if PCIBR_DMA_DEBUG
+	    printk("pcibr_dmatrans_addr:\n"
+		    "\tpciio connection point %v\n"
+		    "\txtalk connection point %v\n"
+		    "\twanted paddr [0x%x..0x%x]\n"
+		    "\txtalk_dmatrans_addr returned 0x%x\n"
+		    "\tUnable to set Device(x) bits for Direct-32\n",
+		    pconn_vhdl, xconn_vhdl,
+		    paddr, paddr + req_size - 1,
+		    xio_addr);
+#endif
+	}
+    }
+
+#if PCIBR_DMA_DEBUG
+    printk("pcibr_dmatrans_addr:\n"
+	    "\tpciio connection point %v\n"
+	    "\txtalk connection point %v\n"
+	    "\twanted paddr [0x%x..0x%x]\n"
+	    "\txtalk_dmatrans_addr returned 0x%x\n"
+	    "\tno acceptable PCI address found or constructable\n",
+	    pconn_vhdl, xconn_vhdl,
+	    paddr, paddr + req_size - 1,
+	    xio_addr);
+#endif
+
+    return 0;
+}
+
+/*ARGSUSED */
+alenlist_t
+pcibr_dmatrans_list(devfs_handle_t pconn_vhdl,
+		    device_desc_t dev_desc,
+		    alenlist_t palenlist,
+		    unsigned flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_slot_t       slotp = &pcibr_soft->bs_slot[pciio_slot];
+    xwidgetnum_t            xio_port;
+
+    alenlist_t              pciio_alenlist = 0;
+    alenlist_t              xtalk_alenlist = 0;
+
+    int                     inplace;
+    unsigned                direct64;
+    unsigned                al_flags;
+
+    iopaddr_t               xio_base;
+    alenaddr_t              xio_addr;
+    size_t                  xio_size;
+
+    size_t                  map_size;
+    iopaddr_t               pci_base;
+    alenaddr_t              pci_addr;
+
+    unsigned                relbits = 0;
+
+    /* merge in forced flags */
+    flags |= pcibr_soft->bs_dma_flags;
+
+    inplace = flags & PCIIO_INPLACE;
+    direct64 = flags & PCIIO_DMA_A64;
+    al_flags = (flags & PCIIO_NOSLEEP) ? AL_NOSLEEP : 0;
+
+    if (direct64) {
+	map_size = 1ull << 48;
+	xio_base = 0;
+	pci_base = slotp->bss_d64_base;
+	if ((pci_base != PCIBR_D64_BASE_UNSET) &&
+	    (flags == slotp->bss_d64_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D64_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D64_BITS;
+	    pci_base =
+		pcibr_flags_to_d64(flags, pcibr_soft);
+	}
+    } else {
+	xio_base = pcibr_soft->bs_dir_xbase;
+	map_size = 1ull << 31;
+	pci_base = slotp->bss_d32_base;
+	if ((pci_base != PCIBR_D32_BASE_UNSET) &&
+	    (flags == slotp->bss_d32_flags)) {
+	    /* reuse previous base info */
+	} else if (pcibr_try_set_device(pcibr_soft, pciio_slot, flags, BRIDGE_DEV_D32_BITS) < 0) {
+	    /* DMA configuration conflict */
+	    goto fail;
+	} else {
+	    relbits = BRIDGE_DEV_D32_BITS;
+	    pci_base = PCI32_DIRECT_BASE;
+	}
+    }
+
+    xtalk_alenlist = xtalk_dmatrans_list(xconn_vhdl, 0, palenlist,
+					 flags & DMAMAP_FLAGS);
+    if (!xtalk_alenlist)
+	goto fail;
+
+    alenlist_cursor_init(xtalk_alenlist, 0, NULL);
+
+    if (inplace) {
+	pciio_alenlist = xtalk_alenlist;
+    } else {
+	pciio_alenlist = alenlist_create(al_flags);
+	if (!pciio_alenlist)
+	    goto fail;
+    }
+
+    while (ALENLIST_SUCCESS ==
+	   alenlist_get(xtalk_alenlist, NULL, 0,
+			&xio_addr, &xio_size, al_flags)) {
+
+	/*
+	 * find which XIO port this goes to.
+	 */
+	if (XIO_PACKED(xio_addr)) {
+	    if (xio_addr == XIO_NOWHERE) {
+#if PCIBR_DMA_DEBUG
+		printk("pcibr_dmatrans_addr:\n"
+			"\tpciio connection point %v\n"
+			"\txtalk connection point %v\n"
+			"\twanted paddr [0x%x..0x%x]\n"
+			"\txtalk_dmatrans_addr returned 0x%x\n",
+			pconn_vhdl, xconn_vhdl,
+			paddr, paddr + req_size - 1,
+			xio_addr);
+#endif
+		return 0;
+	    }
+	    xio_port = XIO_PORT(xio_addr);
+	    xio_addr = XIO_ADDR(xio_addr);
+	} else
+	    xio_port = pcibr_soft->bs_mxid;
+
+	/*
+	 * If this DMA comes back to us,
+	 * return the PCI MEM address on
+	 * which it would land, or NULL
+	 * if the target is something
+	 * on bridge other than PCI MEM.
+	 */
+	if (xio_port == pcibr_soft->bs_xid) {
+	    pci_addr = pcibr_addr_xio_to_pci(pcibr_soft, xio_addr, xio_size);
+	    if ( (pci_addr == (alenaddr_t)NULL) )
+		goto fail;
+	} else if (direct64) {
+	    ASSERT(xio_port != 0);
+	    pci_addr = pci_base | xio_addr
+		| ((uint64_t) xio_port << PCI64_ATTR_TARG_SHFT);
+	} else {
+	    iopaddr_t               offset = xio_addr - xio_base;
+	    iopaddr_t               endoff = xio_size + offset;
+
+	    if ((xio_size > map_size) ||
+		(xio_addr < xio_base) ||
+		(xio_port != pcibr_soft->bs_dir_xport) ||
+		(endoff > map_size))
+		goto fail;
+
+	    pci_addr = pci_base + (xio_addr - xio_base);
+	}
+
+	/* write the PCI DMA address
+	 * out to the scatter-gather list.
+	 */
+	if (inplace) {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_replace(pciio_alenlist, NULL,
+				 &pci_addr, &xio_size, al_flags))
+		goto fail;
+	} else {
+	    if (ALENLIST_SUCCESS !=
+		alenlist_append(pciio_alenlist,
+				pci_addr, xio_size, al_flags))
+		goto fail;
+	}
+    }
+
+    if (relbits) {
+	if (direct64) {
+	    slotp->bss_d64_flags = flags;
+	    slotp->bss_d64_base = pci_base;
+	} else {
+	    slotp->bss_d32_flags = flags;
+	    slotp->bss_d32_base = pci_base;
+	}
+    }
+    if (!inplace)
+	alenlist_done(xtalk_alenlist);
+
+    /* Reset the internal cursor of the alenlist to be returned back
+     * to the caller.
+     */
+    alenlist_cursor_init(pciio_alenlist, 0, NULL);
+    return pciio_alenlist;
+
+  fail:
+    if (relbits)
+	pcibr_release_device(pcibr_soft, pciio_slot, relbits);
+    if (pciio_alenlist && !inplace)
+	alenlist_destroy(pciio_alenlist);
+    return 0;
+}
+
+void
+pcibr_dmamap_drain(pcibr_dmamap_t map)
+{
+    xtalk_dmamap_drain(map->bd_xtalk);
+}
+
+void
+pcibr_dmaaddr_drain(devfs_handle_t pconn_vhdl,
+		    paddr_t paddr,
+		    size_t bytes)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmaaddr_drain(xconn_vhdl, paddr, bytes);
+}
+
+void
+pcibr_dmalist_drain(devfs_handle_t pconn_vhdl,
+		    alenlist_t list)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+
+    xtalk_dmalist_drain(xconn_vhdl, list);
+}
+
+/*
+ * Get the starting PCIbus address out of the given DMA map.
+ * This function is supposed to be used by a close friend of PCI bridge
+ * since it relies on the fact that the starting address of the map is fixed at
+ * the allocation time in the current implementation of PCI bridge.
+ */
+iopaddr_t
+pcibr_dmamap_pciaddr_get(pcibr_dmamap_t pcibr_dmamap)
+{
+    return (pcibr_dmamap->bd_pci_addr);
+}
+
+/* =====================================================================
+ *    CONFIGURATION MANAGEMENT
+ */
+/*ARGSUSED */
+void
+pcibr_provider_startup(devfs_handle_t pcibr)
+{
+}
+
+/*ARGSUSED */
+void
+pcibr_provider_shutdown(devfs_handle_t pcibr)
+{
+}
+
+int
+pcibr_reset(devfs_handle_t conn)
+{
+    pciio_info_t            pciio_info = pciio_info_get(conn);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             ctlreg;
+    unsigned                cfgctl[8];
+    unsigned long           s;
+    int                     f, nf;
+    pcibr_info_h            pcibr_infoh;
+    pcibr_info_t            pcibr_info;
+    int                     win;
+
+    if (pcibr_soft->bs_slot[pciio_slot].has_host) {
+	pciio_slot = pcibr_soft->bs_slot[pciio_slot].host_slot;
+	pcibr_info = pcibr_soft->bs_slot[pciio_slot].bss_infos[0];
+    }
+    if (pciio_slot < 4) {
+	s = pcibr_lock(pcibr_soft);
+	nf = pcibr_soft->bs_slot[pciio_slot].bss_ninfo;
+	pcibr_infoh = pcibr_soft->bs_slot[pciio_slot].bss_infos;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		cfgctl[f] = bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4];
+
+	ctlreg = bridge->b_wid_control;
+	bridge->b_wid_control = ctlreg | BRIDGE_CTRL_RST(pciio_slot);
+	/* XXX delay? */
+	bridge->b_wid_control = ctlreg;
+	/* XXX delay? */
+
+	for (f = 0; f < nf; ++f)
+	    if ((pcibr_info = pcibr_infoh[f]))
+		for (win = 0; win < 6; ++win)
+		    if (pcibr_info->f_window[win].w_base != 0)
+			bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_BASE_ADDR(win) / 4] =
+			    pcibr_info->f_window[win].w_base;
+	for (f = 0; f < nf; ++f)
+	    if (pcibr_infoh[f])
+		bridge->b_type0_cfg_dev[pciio_slot].f[f].l[PCI_CFG_COMMAND / 4] = cfgctl[f];
+	pcibr_unlock(pcibr_soft, s);
+
+	return 0;
+    }
+#ifdef SUPPORT_PRINTING_V_FORMAT
+    printk(KERN_WARNING   "%v: pcibr_reset unimplemented for slot %d\n",
+	    conn, pciio_slot);
+#endif
+    return -1;
+}
+
+pciio_endian_t
+pcibr_endian_set(devfs_handle_t pconn_vhdl,
+		 pciio_endian_t device_end,
+		 pciio_endian_t desired_end)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             devreg;
+    unsigned long           s;
+
+    /*
+     * Bridge supports hardware swapping; so we can always
+     * arrange for the caller's desired endianness.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_end != desired_end)
+	devreg |= BRIDGE_DEV_SWAP_BITS;
+    else
+	devreg &= ~BRIDGE_DEV_SWAP_BITS;
+
+    /* NOTE- if we ever put SWAP bits
+     * onto the disabled list, we will
+     * have to change the logic here.
+     */
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+#if DEBUG && PCIBR_DEV_DEBUG
+    printk("pcibr Device(%d): 0x%p\n", pciio_slot, bridge->b_device[pciio_slot].reg);
+#endif
+
+    return desired_end;
+}
+
+/* This (re)sets the GBR and REALTIME bits and also keeps track of how
+ * many sets are outstanding. Reset succeeds only if the number of outstanding
+ * sets == 1.
+ */
+int
+pcibr_priority_bits_set(pcibr_soft_t pcibr_soft,
+			pciio_slot_t pciio_slot,
+			pciio_priority_t device_prio)
+{
+    unsigned long           s;
+    int                    *counter;
+    bridgereg_t             rtbits = 0;
+    bridgereg_t             devreg;
+    int                     rc = PRIO_SUCCESS;
+
+    /* in dual-slot configurations, the host and the
+     * guest have separate DMA resources, so they
+     * have separate requirements for priority bits.
+     */
+
+    counter = &(pcibr_soft->bs_slot[pciio_slot].bss_pri_uctr);
+
+    /*
+     * Bridge supports PCI notions of LOW and HIGH priority
+     * arbitration rings via a "REAL_TIME" bit in the per-device
+     * Bridge register. The "GBR" bit controls access to the GBR
+     * ring on the xbow. These two bits are (re)set together.
+     *
+     * XXX- Bug in Rev B Bridge Si:
+     * Symptom: Prefetcher starts operating incorrectly. This happens
+     * due to corruption of the address storage ram in the prefetcher
+     * when a non-real time PCI request is pulled and a real-time one is
+     * put in it's place. Workaround: Use only a single arbitration ring
+     * on PCI bus. GBR and RR can still be uniquely used per
+     * device. NETLIST MERGE DONE, WILL BE FIXED IN REV C.
+     */
+
+    if (pcibr_soft->bs_rev_num != BRIDGE_PART_REV_B)
+	rtbits |= BRIDGE_DEV_RT;
+
+    /* NOTE- if we ever put DEV_RT or DEV_GBR on
+     * the disabled list, we will have to take
+     * it into account here.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+    devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+    if (device_prio == PCI_PRIO_HIGH) {
+	if ((++*counter == 1)) {
+	    if (rtbits)
+		devreg |= rtbits;
+	    else
+		rc = PRIO_FAIL;
+	}
+    } else if (device_prio == PCI_PRIO_LOW) {
+	if (*counter <= 0)
+	    rc = PRIO_FAIL;
+	else if (--*counter == 0)
+	    if (rtbits)
+		devreg &= ~rtbits;
+    }
+    if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	bridge_t               *bridge = pcibr_soft->bs_base;
+
+	bridge->b_device[pciio_slot].reg = devreg;
+	pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    }
+    pcibr_unlock(pcibr_soft, s);
+
+    return rc;
+}
+
+pciio_priority_t
+pcibr_priority_set(devfs_handle_t pconn_vhdl,
+		   pciio_priority_t device_prio)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    (void) pcibr_priority_bits_set(pcibr_soft, pciio_slot, device_prio);
+
+    return device_prio;
+}
+
+/*
+ * Interfaces to allow special (e.g. SGI) drivers to set/clear
+ * Bridge-specific device flags.  Many flags are modified through
+ * PCI-generic interfaces; we don't allow them to be directly
+ * manipulated here.  Only flags that at this point seem pretty
+ * Bridge-specific can be set through these special interfaces.
+ * We may add more flags as the need arises, or remove flags and
+ * create PCI-generic interfaces as the need arises.
+ *
+ * Returns 0 on failure, 1 on success
+ */
+int
+pcibr_device_flags_set(devfs_handle_t pconn_vhdl,
+		       pcibr_device_flags_t flags)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridgereg_t             set = 0;
+    bridgereg_t             clr = 0;
+
+    ASSERT((flags & PCIBR_DEVICE_FLAGS) == flags);
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_PMU_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_PMU_WRGA_EN;
+
+    if (flags & PCIBR_WRITE_GATHER)
+	set |= BRIDGE_DEV_DIR_WRGA_EN;
+    if (flags & PCIBR_NOWRITE_GATHER)
+	clr |= BRIDGE_DEV_DIR_WRGA_EN;
+
+    if (flags & PCIBR_PREFETCH)
+	set |= BRIDGE_DEV_PREF;
+    if (flags & PCIBR_NOPREFETCH)
+	clr |= BRIDGE_DEV_PREF;
+
+    if (flags & PCIBR_PRECISE)
+	set |= BRIDGE_DEV_PRECISE;
+    if (flags & PCIBR_NOPRECISE)
+	clr |= BRIDGE_DEV_PRECISE;
+
+    if (flags & PCIBR_BARRIER)
+	set |= BRIDGE_DEV_BARRIER;
+    if (flags & PCIBR_NOBARRIER)
+	clr |= BRIDGE_DEV_BARRIER;
+
+    if (flags & PCIBR_64BIT)
+	set |= BRIDGE_DEV_DEV_SIZE;
+    if (flags & PCIBR_NO64BIT)
+	clr |= BRIDGE_DEV_DEV_SIZE;
+
+    if (set || clr) {
+	bridgereg_t             devreg;
+	unsigned long           s;
+
+	s = pcibr_lock(pcibr_soft);
+	devreg = pcibr_soft->bs_slot[pciio_slot].bss_device;
+	devreg = (devreg & ~clr) | set;
+	if (pcibr_soft->bs_slot[pciio_slot].bss_device != devreg) {
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+
+	    bridge->b_device[pciio_slot].reg = devreg;
+	    pcibr_soft->bs_slot[pciio_slot].bss_device = devreg;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	}
+	pcibr_unlock(pcibr_soft, s);
+#if DEBUG && PCIBR_DEV_DEBUG
+	printk("pcibr Device(%d): %R\n", pciio_slot, bridge->b_device[pciio_slot].regbridge->b_device[pciio_slot].reg, device_bits);
+#endif
+    }
+    return (1);
+}
+
+pciio_provider_t        pcibr_provider =
+{
+    (pciio_piomap_alloc_f *) pcibr_piomap_alloc,
+    (pciio_piomap_free_f *) pcibr_piomap_free,
+    (pciio_piomap_addr_f *) pcibr_piomap_addr,
+    (pciio_piomap_done_f *) pcibr_piomap_done,
+    (pciio_piotrans_addr_f *) pcibr_piotrans_addr,
+    (pciio_piospace_alloc_f *) pcibr_piospace_alloc,
+    (pciio_piospace_free_f *) pcibr_piospace_free,
+
+    (pciio_dmamap_alloc_f *) pcibr_dmamap_alloc,
+    (pciio_dmamap_free_f *) pcibr_dmamap_free,
+    (pciio_dmamap_addr_f *) pcibr_dmamap_addr,
+    (pciio_dmamap_list_f *) pcibr_dmamap_list,
+    (pciio_dmamap_done_f *) pcibr_dmamap_done,
+    (pciio_dmatrans_addr_f *) pcibr_dmatrans_addr,
+    (pciio_dmatrans_list_f *) pcibr_dmatrans_list,
+    (pciio_dmamap_drain_f *) pcibr_dmamap_drain,
+    (pciio_dmaaddr_drain_f *) pcibr_dmaaddr_drain,
+    (pciio_dmalist_drain_f *) pcibr_dmalist_drain,
+
+    (pciio_intr_alloc_f *) pcibr_intr_alloc,
+    (pciio_intr_free_f *) pcibr_intr_free,
+    (pciio_intr_connect_f *) pcibr_intr_connect,
+    (pciio_intr_disconnect_f *) pcibr_intr_disconnect,
+    (pciio_intr_cpu_get_f *) pcibr_intr_cpu_get,
+
+    (pciio_provider_startup_f *) pcibr_provider_startup,
+    (pciio_provider_shutdown_f *) pcibr_provider_shutdown,
+    (pciio_reset_f *) pcibr_reset,
+    (pciio_write_gather_flush_f *) pcibr_write_gather_flush,
+    (pciio_endian_set_f *) pcibr_endian_set,
+    (pciio_priority_set_f *) pcibr_priority_set,
+    (pciio_config_get_f *) pcibr_config_get,
+    (pciio_config_set_f *) pcibr_config_set,
+
+    (pciio_error_devenable_f *) 0,
+    (pciio_error_extract_f *) 0,
+
+#ifdef LATER
+    (pciio_driver_reg_callback_f *) pcibr_driver_reg_callback,
+    (pciio_driver_unreg_callback_f *) pcibr_driver_unreg_callback,
+#else
+    (pciio_driver_reg_callback_f *) 0,
+    (pciio_driver_unreg_callback_f *) 0,
+#endif
+    (pciio_device_unregister_f 	*) pcibr_device_unregister,
+    (pciio_dma_enabled_f		*) pcibr_dma_enabled,
+};
+
+int
+pcibr_dma_enabled(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+	
+
+    return xtalk_dma_enabled(pcibr_soft->bs_conn);
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_error.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1737 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+extern int	hubii_check_widget_disabled(nasid_t, int);
+
+/* =====================================================================
+ *    ERROR HANDLING
+ */
+
+#ifdef	DEBUG
+#ifdef	ERROR_DEBUG
+#define BRIDGE_PIOERR_TIMEOUT	100	/* Timeout with ERROR_DEBUG defined */
+#else
+#define BRIDGE_PIOERR_TIMEOUT	40	/* Timeout in debug mode  */
+#endif
+#else
+#define BRIDGE_PIOERR_TIMEOUT	1	/* Timeout in non-debug mode                            */
+#endif
+
+#ifdef  DEBUG
+#ifdef ERROR_DEBUG
+bridgereg_t bridge_errors_to_dump = ~BRIDGE_ISR_INT_MSK;
+#else
+bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_DUMP;
+#endif
+#else
+bridgereg_t bridge_errors_to_dump = BRIDGE_ISR_ERROR_FATAL |
+                                BRIDGE_ISR_PCIBUS_PIOERR;
+#endif
+
+#if defined (PCIBR_LLP_CONTROL_WAR)
+int                     pcibr_llp_control_war_cnt;
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+/* FIXME: can these arrays be local ? */
+
+#ifdef LATER
+
+struct reg_values xio_cmd_pactyp[] =
+{
+    {0x0, "RdReq"},
+    {0x1, "RdResp"},
+    {0x2, "WrReqWithResp"},
+    {0x3, "WrResp"},
+    {0x4, "WrReqNoResp"},
+    {0x5, "Reserved(5)"},
+    {0x6, "FetchAndOp"},
+    {0x7, "Reserved(7)"},
+    {0x8, "StoreAndOp"},
+    {0x9, "Reserved(9)"},
+    {0xa, "Reserved(a)"},
+    {0xb, "Reserved(b)"},
+    {0xc, "Reserved(c)"},
+    {0xd, "Reserved(d)"},
+    {0xe, "SpecialReq"},
+    {0xf, "SpecialResp"},
+    {0}
+};
+
+struct reg_desc   xio_cmd_bits[] =
+{
+    {WIDGET_DIDN, -28, "DIDN", "%x"},
+    {WIDGET_SIDN, -24, "SIDN", "%x"},
+    {WIDGET_PACTYP, -20, "PACTYP", 0, xio_cmd_pactyp},
+    {WIDGET_TNUM, -15, "TNUM", "%x"},
+    {WIDGET_COHERENT, 0, "COHERENT"},
+    {WIDGET_DS, 0, "DS"},
+    {WIDGET_GBR, 0, "GBR"},
+    {WIDGET_VBPM, 0, "VBPM"},
+    {WIDGET_ERROR, 0, "ERROR"},
+    {WIDGET_BARRIER, 0, "BARRIER"},
+    {0}
+};
+
+#define F(s,n)          { 1l<<(s),-(s), n }
+
+struct reg_desc         bridge_int_status_desc[] =
+{
+    F(31, "MULTI_ERR"),
+    F(30, "PMU_ESIZE_EFAULT"),
+    F(29, "UNEXPECTED_RESP"),
+    F(28, "BAD_XRESP_PACKET"),
+    F(27, "BAD_XREQ_PACKET"),
+    F(26, "RESP_XTALK_ERROR"),
+    F(25, "REQ_XTALK_ERROR"),
+    F(24, "INVALID_ADDRESS"),
+    F(23, "UNSUPPORTED_XOP"),
+    F(22, "XREQ_FIFO_OFLOW"),
+    F(21, "LLP_REC_SNERROR"),
+    F(20, "LLP_REC_CBERROR"),
+    F(19, "LLP_RCTY"),
+    F(18, "LLP_TX_RETRY"),
+    F(17, "LLP_TCTY"),
+    F(16, "SSRAM_PERR"),
+    F(15, "PCI_ABORT"),
+    F(14, "PCI_PARITY"),
+    F(13, "PCI_SERR"),
+    F(12, "PCI_PERR"),
+    F(11, "PCI_MASTER_TOUT"),
+    F(10, "PCI_RETRY_CNT"),
+    F(9, "XREAD_REQ_TOUT"),
+    F(8, "GIO_BENABLE_ERR"),
+    F(7, "INT7"),
+    F(6, "INT6"),
+    F(5, "INT5"),
+    F(4, "INT4"),
+    F(3, "INT3"),
+    F(2, "INT2"),
+    F(1, "INT1"),
+    F(0, "INT0"),
+    {0}
+};
+
+struct reg_values       space_v[] =
+{
+    {PCIIO_SPACE_NONE, "none"},
+    {PCIIO_SPACE_ROM, "ROM"},
+    {PCIIO_SPACE_IO, "I/O"},
+    {PCIIO_SPACE_MEM, "MEM"},
+    {PCIIO_SPACE_MEM32, "MEM(32)"},
+    {PCIIO_SPACE_MEM64, "MEM(64)"},
+    {PCIIO_SPACE_CFG, "CFG"},
+    {PCIIO_SPACE_WIN(0), "WIN(0)"},
+    {PCIIO_SPACE_WIN(1), "WIN(1)"},
+    {PCIIO_SPACE_WIN(2), "WIN(2)"},
+    {PCIIO_SPACE_WIN(3), "WIN(3)"},
+    {PCIIO_SPACE_WIN(4), "WIN(4)"},
+    {PCIIO_SPACE_WIN(5), "WIN(5)"},
+    {PCIIO_SPACE_BAD, "BAD"},
+    {0}
+};
+struct reg_desc         space_desc[] =
+{
+    {0xFF, 0, "space", 0, space_v},
+    {0}
+};
+#define	device_desc	device_bits
+struct reg_desc   device_bits[] =
+{
+    {BRIDGE_DEV_ERR_LOCK_EN, 0, "ERR_LOCK_EN"},
+    {BRIDGE_DEV_PAGE_CHK_DIS, 0, "PAGE_CHK_DIS"},
+    {BRIDGE_DEV_FORCE_PCI_PAR, 0, "FORCE_PCI_PAR"},
+    {BRIDGE_DEV_VIRTUAL_EN, 0, "VIRTUAL_EN"},
+    {BRIDGE_DEV_PMU_WRGA_EN, 0, "PMU_WRGA_EN"},
+    {BRIDGE_DEV_DIR_WRGA_EN, 0, "DIR_WRGA_EN"},
+    {BRIDGE_DEV_DEV_SIZE, 0, "DEV_SIZE"},
+    {BRIDGE_DEV_RT, 0, "RT"},
+    {BRIDGE_DEV_SWAP_PMU, 0, "SWAP_PMU"},
+    {BRIDGE_DEV_SWAP_DIR, 0, "SWAP_DIR"},
+    {BRIDGE_DEV_PREF, 0, "PREF"},
+    {BRIDGE_DEV_PRECISE, 0, "PRECISE"},
+    {BRIDGE_DEV_COH, 0, "COH"},
+    {BRIDGE_DEV_BARRIER, 0, "BARRIER"},
+    {BRIDGE_DEV_GBR, 0, "GBR"},
+    {BRIDGE_DEV_DEV_SWAP, 0, "DEV_SWAP"},
+    {BRIDGE_DEV_DEV_IO_MEM, 0, "DEV_IO_MEM"},
+    {BRIDGE_DEV_OFF_MASK, BRIDGE_DEV_OFF_ADDR_SHFT, "DEV_OFF", "%x"},
+    {0}
+};
+
+#endif	/* LATER */
+
+void
+print_bridge_errcmd(uint32_t cmdword, char *errtype)
+{
+    printk(
+	    "\t    Bridge %s Error Command Word Register %R\n",
+	    errtype, cmdword, xio_cmd_bits);
+}
+
+char             *pcibr_isr_errs[] =
+{
+    "", "", "", "", "", "", "", "",
+    "08: GIO non-contiguous byte enable in crosstalk packet",
+    "09: PCI to Crosstalk read request timeout",
+    "10: PCI retry operation count exhausted.",
+    "11: PCI bus device select timeout",
+    "12: PCI device reported parity error",
+    "13: PCI Address/Cmd parity error ",
+    "14: PCI Bridge detected parity error",
+    "15: PCI abort condition",
+    "16: SSRAM parity error",
+    "17: LLP Transmitter Retry count wrapped",
+    "18: LLP Transmitter side required Retry",
+    "19: LLP Receiver retry count wrapped",
+    "20: LLP Receiver check bit error",
+    "21: LLP Receiver sequence number error",
+    "22: Request packet overflow",
+    "23: Request operation not supported by bridge",
+    "24: Request packet has invalid address for bridge widget",
+    "25: Incoming request xtalk command word error bit set or invalid sideband",
+    "26: Incoming response xtalk command word error bit set or invalid sideband",
+    "27: Framing error, request cmd data size does not match actual",
+    "28: Framing error, response cmd data size does not match actual",
+    "29: Unexpected response arrived",
+    "30: PMU Access Fault",
+    "31: Multiple errors occurred",
+};
+
+#define BEM_ADD_STR(s)  printk("%s", (s))
+#define BEM_ADD_VAR(v)  printk("\t%20s: 0x%x\n", #v, (v))
+#define BEM_ADD_REG(r)  printk("\t%20s: %R\n", #r, (r), r ## _desc)
+#define BEM_ADD_NSPC(n,s)       printk("\t%20s: %R\n", n, s, space_desc)
+#define BEM_ADD_SPC(s)          BEM_ADD_NSPC(#s, s)
+
+/*
+ * display memory directory state
+ */
+void
+pcibr_show_dir_state(paddr_t paddr, char *prefix)
+{
+	int state;
+	uint64_t vec_ptr;
+	hubreg_t elo;
+	extern char *dir_state_str[];
+	extern void get_dir_ent(paddr_t, int *, uint64_t *, hubreg_t *);
+
+	get_dir_ent(paddr, &state, &vec_ptr, &elo);
+
+	printf("%saddr 0x%x: state 0x%x owner 0x%x (%s)\n", 
+		prefix, paddr, state, vec_ptr, dir_state_str[state]);
+}
+
+
+/*
+ *	Dump relevant error information for Bridge error interrupts.
+ */
+/*ARGSUSED */
+void
+pcibr_error_dump(pcibr_soft_t pcibr_soft)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             int_status;
+    bridgereg_t             mult_int;
+    int			    bit;
+    int                     i;
+    char		    *reg_desc;
+    paddr_t		    addr;
+
+    int_status = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK);
+    if (!int_status) {
+	/* No error bits set */
+	return;
+    }
+
+    /* Check if dumping the same error information multiple times */
+    if (test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat,
+	    int_status) == int_status) {
+	return;
+    }
+
+    printk(KERN_ALERT "PCI BRIDGE ERROR: int_status is 0x%X for %s\n"
+	"    Dumping relevant %sBridge registers for each bit set...\n",
+	    int_status, pcibr_soft->bs_name,
+	    (is_xbridge(bridge) ? "X" : ""));
+
+    for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
+	bit = 1 << i;
+
+	/*
+	 * A number of int_status bits are only defined for Bridge.
+	 * Ignore them in the case of an XBridge.
+	 */
+	if (is_xbridge(bridge) && ((bit == BRIDGE_ISR_MULTI_ERR) ||
+		(bit == BRIDGE_ISR_SSRAM_PERR) ||
+		(bit == BRIDGE_ISR_GIO_B_ENBL_ERR))) {
+	    continue;
+	}
+
+	if (int_status & bit) {
+	    printk("\t%s\n", pcibr_isr_errs[i]);
+
+	    switch (bit) {
+	    case BRIDGE_ISR_PAGE_FAULT:		/* PMU_PAGE_FAULT  (XBridge) */
+/*	    case BRIDGE_ISR_PMU_ESIZE_FAULT:	   PMU_ESIZE_FAULT (Bridge) */
+		if (is_xbridge(bridge))
+		    reg_desc = "Map Fault Address";
+		else
+		    reg_desc = "SSRAM Parity Error";
+
+		printk("\t    %s Register: 0x%x\n", reg_desc,
+		    bridge->b_ram_perr_or_map_fault);
+		break;
+
+	    case BRIDGE_ISR_UNEXP_RESP:		/* UNEXPECTED_RESP */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "Aux");
+		break;
+
+	    case BRIDGE_ISR_BAD_XRESP_PKT:		/* BAD_RESP_PACKET */
+	    case BRIDGE_ISR_RESP_XTLK_ERR:		/* RESP_XTALK_ERROR */
+	    case BRIDGE_ISR_XREAD_REQ_TIMEOUT:		/* XREAD_REQ_TOUT */
+
+		addr = (((uint64_t) (bridge->b_wid_resp_upper & 0xFFFF) << 32)
+			| bridge->b_wid_resp_lower);
+		printk(
+		    "\t    Bridge Response Buffer Error Upper Address Register: 0x%x\n"
+		    "\t    Bridge Response Buffer Error Lower Address Register: 0x%x\n"
+		    "\t    dev-num %d buff-num %d addr 0x%x\n",
+		    bridge->b_wid_resp_upper, bridge->b_wid_resp_lower,
+		    ((bridge->b_wid_resp_upper >> 20) & 0x3),
+		    ((bridge->b_wid_resp_upper >> 16) & 0xF),
+		    addr);
+		if (bit == BRIDGE_ISR_RESP_XTLK_ERR) {
+			/* display memory directory associated with cacheline */
+			pcibr_show_dir_state(addr, "\t    ");
+		}
+		break;
+
+	    case BRIDGE_ISR_BAD_XREQ_PKT:		/* BAD_XREQ_PACKET */
+	    case BRIDGE_ISR_REQ_XTLK_ERR:		/* REQ_XTALK_ERROR */
+	    case BRIDGE_ISR_INVLD_ADDR:			/* INVALID_ADDRESS */
+	    case BRIDGE_ISR_UNSUPPORTED_XOP:		/* UNSUPPORTED_XOP */
+		print_bridge_errcmd(bridge->b_wid_aux_err, "");
+		printk("\t    Bridge Error Upper Address Register: 0x%x\n"
+		    "\t    Bridge Error Lower Address Register: 0x%x\n"
+		    "\t    Bridge Error Address: 0x%x\n",
+		    (uint64_t) bridge->b_wid_err_upper,
+		    (uint64_t) bridge->b_wid_err_lower,
+		    (((uint64_t) bridge->b_wid_err_upper << 32) |
+		    bridge->b_wid_err_lower));
+		break;
+
+	    case BRIDGE_ISR_SSRAM_PERR:			/* SSRAM_PERR */
+		if (!is_xbridge(bridge)) {	/* only defined on Bridge */
+		    printk(
+			"\t    Bridge SSRAM Parity Error Register: 0x%x\n",
+			bridge->b_ram_perr);
+		}
+		break;
+
+	    case BRIDGE_ISR_PCI_ABORT:			/* PCI_ABORT */
+	    case BRIDGE_ISR_PCI_PARITY:			/* PCI_PARITY */
+	    case BRIDGE_ISR_PCI_SERR:			/* PCI_SERR */
+	    case BRIDGE_ISR_PCI_PERR:			/* PCI_PERR */
+	    case BRIDGE_ISR_PCI_MST_TIMEOUT:		/* PCI_MASTER_TOUT */
+	    case BRIDGE_ISR_PCI_RETRY_CNT:		/* PCI_RETRY_CNT */
+	    case BRIDGE_ISR_GIO_B_ENBL_ERR:		/* GIO BENABLE_ERR */
+		printk("\t    PCI Error Upper Address Register: 0x%x\n"
+		    "\t    PCI Error Lower Address Register: 0x%x\n"
+		    "\t    PCI Error Address: 0x%x\n",
+		    (uint64_t) bridge->b_pci_err_upper,
+		    (uint64_t) bridge->b_pci_err_lower,
+		    (((uint64_t) bridge->b_pci_err_upper << 32) |
+		    bridge->b_pci_err_lower));
+		break;
+	    }
+	}
+    }
+
+    if (is_xbridge(bridge) && (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK)) {
+	mult_int = bridge->b_mult_int;
+	printk("    XBridge Multiple Interrupt Register is 0x%x\n",
+		mult_int);
+	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++) {
+	    if (mult_int & (1 << i))
+		printk("\t%s\n", pcibr_isr_errs[i]);
+	    }
+	}
+}
+
+#define PCIBR_ERRINTR_GROUP(error)	\
+		(( error & (BRIDGE_IRR_PCI_GRP|BRIDGE_IRR_GIO_GRP)
+
+uint32_t
+pcibr_errintr_group(uint32_t error)
+{
+    uint32_t              group = BRIDGE_IRR_MULTI_CLR;
+
+    if (error & BRIDGE_IRR_PCI_GRP)
+	group |= BRIDGE_IRR_PCI_GRP_CLR;
+    if (error & BRIDGE_IRR_SSRAM_GRP)
+	group |= BRIDGE_IRR_SSRAM_GRP_CLR;
+    if (error & BRIDGE_IRR_LLP_GRP)
+	group |= BRIDGE_IRR_LLP_GRP_CLR;
+    if (error & BRIDGE_IRR_REQ_DSP_GRP)
+	group |= BRIDGE_IRR_REQ_DSP_GRP_CLR;
+    if (error & BRIDGE_IRR_RESP_BUF_GRP)
+	group |= BRIDGE_IRR_RESP_BUF_GRP_CLR;
+    if (error & BRIDGE_IRR_CRP_GRP)
+	group |= BRIDGE_IRR_CRP_GRP_CLR;
+
+    return group;
+
+}
+
+
+/* pcibr_pioerr_check():
+ *	Check to see if this pcibr has a PCI PIO
+ *	TIMEOUT error; if so, bump the timeout-count
+ *	on any piomaps that could cover the address.
+ */
+static void
+pcibr_pioerr_check(pcibr_soft_t soft)
+{
+    bridge_t		   *bridge;
+    bridgereg_t		    b_int_status;
+    bridgereg_t		    b_pci_err_lower;
+    bridgereg_t		    b_pci_err_upper;
+    iopaddr_t		    pci_addr;
+    pciio_slot_t	    slot;
+    pcibr_piomap_t	    map;
+    iopaddr_t		    base;
+    size_t		    size;
+    unsigned		    win;
+    int			    func;
+
+    bridge = soft->bs_base;
+    b_int_status = bridge->b_int_status;
+    if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+	b_pci_err_lower = bridge->b_pci_err_lower;
+	b_pci_err_upper = bridge->b_pci_err_upper;
+	b_int_status = bridge->b_int_status;
+	if (b_int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+
+	    pci_addr = b_pci_err_upper & BRIDGE_ERRUPPR_ADDRMASK;
+	    pci_addr = (pci_addr << 32) | b_pci_err_lower;
+
+	    slot = 8;
+	    while (slot-- > 0) {
+		int 		nfunc = soft->bs_slot[slot].bss_ninfo;
+		pcibr_info_h	pcibr_infoh = soft->bs_slot[slot].bss_infos;
+
+		for (func = 0; func < nfunc; func++) {
+		    pcibr_info_t 	pcibr_info = pcibr_infoh[func];
+
+		    if (!pcibr_info)
+			continue;
+
+		    for (map = pcibr_info->f_piomap;
+			 map != NULL; map = map->bp_next) {
+			base = map->bp_pciaddr;
+			size = map->bp_mapsz;
+			win = map->bp_space - PCIIO_SPACE_WIN(0);
+			if (win < 6)
+			    base += 
+				soft->bs_slot[slot].bss_window[win].bssw_base;
+			else if (map->bp_space == PCIIO_SPACE_ROM)
+			    base += pcibr_info->f_rbase;
+			if ((pci_addr >= base) && (pci_addr < (base + size)))
+			    atomicAddInt(map->bp_toc, 1);
+		    }
+		}
+	    }
+	}
+    }
+}
+
+/*
+ * PCI Bridge Error interrupt handler.
+ *      This gets invoked, whenever a PCI bridge sends an error interrupt.
+ *      Primarily this servers two purposes.
+ *              - If an error can be handled (typically a PIO read/write
+ *                error, we try to do it silently.
+ *              - If an error cannot be handled, we die violently.
+ *      Interrupt due to PIO errors:
+ *              - Bridge sends an interrupt, whenever a PCI operation
+ *                done by the bridge as the master fails. Operations could
+ *                be either a PIO read or a PIO write.
+ *                PIO Read operation also triggers a bus error, and it's
+ *                We primarily ignore this interrupt in that context..
+ *                For PIO write errors, this is the only indication.
+ *                and we have to handle with the info from here.
+ *
+ *                So, there is no way to distinguish if an interrupt is
+ *                due to read or write error!.
+ */
+
+
+void
+pcibr_error_intr_handler(intr_arg_t arg)
+{
+    pcibr_soft_t            pcibr_soft;
+    bridge_t               *bridge;
+    bridgereg_t             int_status;
+    bridgereg_t             err_status;
+    int                     i;
+
+    /* REFERENCED */
+    bridgereg_t             disable_errintr_mask = 0;
+    int 		    rv;
+    int 		    error_code = IOECODE_DMA | IOECODE_READ;
+    ioerror_mode_t 	    mode = MODE_DEVERROR;
+    ioerror_t 	            ioe;
+    nasid_t		    nasid;
+
+#if PCIBR_SOFT_LIST
+    {
+	extern pcibr_list_p	pcibr_list;
+	pcibr_list_p            entry;
+
+	entry = pcibr_list;
+	while (1) {
+	    if (entry == NULL) {
+		PRINT_PANIC(
+			"pcibr_error_intr_handler:\n"
+			"\tmy parameter (0x%x) is not a pcibr_soft!",
+			arg);
+	    }
+	    if ((intr_arg_t) entry->bl_soft == arg)
+		break;
+	    entry = entry->bl_next;
+	}
+    }
+#endif
+    pcibr_soft = (pcibr_soft_t) arg;
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * pcibr_error_intr_handler gets invoked whenever bridge encounters
+     * an error situation, and the interrupt for that error is enabled.
+     * This routine decides if the error is fatal or not, and takes
+     * action accordingly.
+     *
+     * In the case of PIO read/write timeouts, there is no way
+     * to know if it was a read or write request that timed out.
+     * If the error was due to a "read", a bus error will also occur
+     * and the bus error handling code takes care of it. 
+     * If the error is due to a "write", the error is currently logged 
+     * by this routine. For SN1 and SN0, if fire-and-forget mode is 
+     * disabled, a write error response xtalk packet will be sent to 
+     * the II, which will cause an II error interrupt. No write error 
+     * recovery actions of any kind currently take place at the pcibr 
+     * layer! (e.g., no panic on unrecovered write error)
+     *
+     * Prior to reading the Bridge int_status register we need to ensure
+     * that there are no error bits set in the lower layers (hubii)
+     * that have disabled PIO access to the widget. If so, there is nothing
+     * we can do until the bits clear, so we setup a timeout and try again
+     * later.
+     */
+
+    nasid = NASID_GET(bridge);
+    if (hubii_check_widget_disabled(nasid, pcibr_soft->bs_xid)) {
+	timeout(pcibr_error_intr_handler, pcibr_soft, BRIDGE_PIOERR_TIMEOUT);
+	pcibr_soft->bs_errinfo.bserr_toutcnt++;
+	return;
+    }
+
+    /* int_status is which bits we have to clear;
+     * err_status is the bits we haven't handled yet.
+     */
+
+    int_status = bridge->b_int_status &  ~BRIDGE_ISR_INT_MSK;
+    err_status = int_status & ~BRIDGE_ISR_MULTI_ERR;
+
+    if (!(int_status & ~BRIDGE_ISR_INT_MSK)) {
+	/*
+	 * No error bit set!!.
+	 */
+	return;
+    }
+    /*
+     * If we have a PCIBUS_PIOERR, hand it to the logger.
+     */
+    if (int_status & BRIDGE_ISR_PCIBUS_PIOERR) {
+	pcibr_pioerr_check(pcibr_soft);
+    }
+
+    if (err_status) {
+	struct bs_errintr_stat_s *bs_estat = pcibr_soft->bs_errintr_stat;
+
+	for (i = PCIBR_ISR_ERR_START; i < PCIBR_ISR_MAX_ERRS; i++, bs_estat++) {
+	    if (err_status & (1 << i)) {
+		uint32_t              errrate = 0;
+		uint32_t              errcount = 0;
+		uint32_t              errinterval = 0, current_tick = 0;
+		int                     llp_tx_retry_errors = 0;
+		int                     is_llp_tx_retry_intr = 0;
+
+		bs_estat->bs_errcount_total++;
+
+		current_tick = lbolt;
+		errinterval = (current_tick - bs_estat->bs_lasterr_timestamp);
+		errcount = (bs_estat->bs_errcount_total -
+			    bs_estat->bs_lasterr_snapshot);
+
+		is_llp_tx_retry_intr = (BRIDGE_ISR_LLP_TX_RETRY == (1 << i));
+
+		/* Check for the divide by zero condition while
+		 * calculating the error rates.
+		 */
+
+		if (errinterval) {
+		    errrate = errcount / errinterval;
+		    /* If able to calculate error rate
+		     * on a LLP transmitter retry interrupt, check
+		     * if the error rate is nonzero and we have seen
+		     * a certain minimum number of errors.
+		     *
+		     * NOTE : errcount is being compared to
+		     * PCIBR_ERRTIME_THRESHOLD to make sure that we are not
+		     * seeing cases like x error interrupts per y ticks for
+		     * very low x ,y (x > y ) which could result in a
+		     * rate > 100/tick.
+		     */
+		    if (is_llp_tx_retry_intr &&
+			errrate &&
+			(errcount >= PCIBR_ERRTIME_THRESHOLD)) {
+			llp_tx_retry_errors = 1;
+		    }
+		} else {
+		    errrate = 0;
+		    /* Since we are not able to calculate the
+		     * error rate check if we exceeded a certain
+		     * minimum number of errors for LLP transmitter
+		     * retries. Note that this can only happen
+		     * within the first tick after the last snapshot.
+		     */
+		    if (is_llp_tx_retry_intr &&
+			(errcount >= PCIBR_ERRINTR_DISABLE_LEVEL)) {
+			llp_tx_retry_errors = 1;
+		    }
+		}
+
+		/*
+		 * If a non-zero error rate (which is equivalent to
+		 * to 100 errors/tick at least) for the LLP transmitter
+		 * retry interrupt was seen, check if we should print
+		 * a warning message.
+		 */
+
+		if (llp_tx_retry_errors) {
+		    static uint32_t       last_printed_rate;
+
+		    if (errrate > last_printed_rate) {
+			last_printed_rate = errrate;
+			/* Print the warning only if the error rate
+			 * for the transmitter retry interrupt
+			 * exceeded the previously printed rate.
+			 */
+			printk(KERN_WARNING
+				"%s: %s, Excessive error interrupts : %d/tick\n",
+				pcibr_soft->bs_name,
+				pcibr_isr_errs[i],
+				errrate);
+
+		    }
+		    /*
+		     * Update snapshot, and time
+		     */
+		    bs_estat->bs_lasterr_timestamp = current_tick;
+		    bs_estat->bs_lasterr_snapshot =
+			bs_estat->bs_errcount_total;
+
+		}
+		/*
+		 * If the error rate is high enough, print the error rate.
+		 */
+		if (errinterval > PCIBR_ERRTIME_THRESHOLD) {
+
+		    if (errrate > PCIBR_ERRRATE_THRESHOLD) {
+			printk(KERN_NOTICE "%s: %s, Error rate %d/tick",
+				pcibr_soft->bs_name,
+				pcibr_isr_errs[i],
+				errrate);
+			/*
+			 * Update snapshot, and time
+			 */
+			bs_estat->bs_lasterr_timestamp = current_tick;
+			bs_estat->bs_lasterr_snapshot =
+			    bs_estat->bs_errcount_total;
+		    }
+		}
+		if (bs_estat->bs_errcount_total > PCIBR_ERRINTR_DISABLE_LEVEL) {
+		    /*
+		     * We have seen a fairly large number of errors of
+		     * this type. Let's disable the interrupt. But flash
+		     * a message about the interrupt being disabled.
+		     */
+		    printk(KERN_NOTICE
+			    "%s Disabling error interrupt type %s. Error count %d",
+			    pcibr_soft->bs_name,
+			    pcibr_isr_errs[i],
+			    bs_estat->bs_errcount_total);
+		    disable_errintr_mask |= (1 << i);
+		}
+	    }
+	}
+    }
+
+    if (disable_errintr_mask) {
+	/*
+	 * Disable some high frequency errors as they
+	 * could eat up too much cpu time.
+	 */
+	bridge->b_int_enable &= ~disable_errintr_mask;
+    }
+    /*
+     * If we leave the PROM cacheable, T5 might
+     * try to do a cache line sized writeback to it,
+     * which will cause a BRIDGE_ISR_INVLD_ADDR.
+     */
+    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
+	(0x00000000 == bridge->b_wid_err_upper) &&
+	(0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) &&
+	(0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) {
+	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
+    }
+#if defined (PCIBR_LLP_CONTROL_WAR)
+    /*
+     * The bridge bug, where the llp_config or control registers
+     * need to be read back after being written, affects an MP
+     * system since there could be small windows between writing
+     * the register and reading it back on one cpu while another
+     * cpu is fielding an interrupt. If we run into this scenario,
+     * workaround the problem by ignoring the error. (bug 454474)
+     * pcibr_llp_control_war_cnt keeps an approximate number of
+     * times we saw this problem on a system.
+     */
+
+    if ((err_status & BRIDGE_ISR_INVLD_ADDR) &&
+	((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower))
+	 == (BRIDGE_INT_RST_STAT & 0xff0))) {
+#if 0
+	if (kdebug)
+	    printk(KERN_NOTICE "%s bridge: ignoring llp/control address interrupt",
+		    pcibr_soft->bs_name);
+#endif
+	pcibr_llp_control_war_cnt++;
+	err_status &= ~BRIDGE_ISR_INVLD_ADDR;
+    }
+#endif				/* PCIBR_LLP_CONTROL_WAR */
+
+#ifdef EHE_ENABLE
+    /* Check if this is the RESP_XTALK_ERROR interrupt. 
+     * This can happen due to a failed DMA READ operation.
+     */
+    if (err_status & BRIDGE_ISR_RESP_XTLK_ERR) {
+	/* Phase 1 : Look at the error state in the bridge and further
+	 * down in the device layers.
+	 */
+	(void)error_state_set(pcibr_soft->bs_conn, ERROR_STATE_LOOKUP);
+	IOERROR_SETVALUE(&ioe, widgetnum, pcibr_soft->bs_xid);
+	(void)pcibr_error_handler((error_handler_arg_t)pcibr_soft,
+				  error_code,
+				  mode,
+				  &ioe);
+	/* Phase 2 : Perform the action agreed upon in phase 1.
+	 */
+	(void)error_state_set(pcibr_soft->bs_conn, ERROR_STATE_ACTION);
+	rv = pcibr_error_handler((error_handler_arg_t)pcibr_soft,
+				 error_code,
+				 mode,
+				 &ioe);
+    }
+    if (rv != IOERROR_HANDLED) {
+#endif /* EHE_ENABLE */
+
+    /* Dump/Log Bridge error interrupt info */
+    if (err_status & bridge_errors_to_dump) {
+	printk("BRIDGE ERR_STATUS 0x%x\n", err_status);
+	pcibr_error_dump(pcibr_soft);
+    }
+
+    if (err_status & BRIDGE_ISR_ERROR_FATAL) {
+	machine_error_dump("");
+	cmn_err_tag(14, CE_PANIC, "PCI Bridge Error interrupt killed the system");
+	    /*NOTREACHED */
+    }
+
+#ifdef EHE_ENABLE
+    }
+#endif
+
+    /*
+     * We can't return without re-enabling the interrupt, since
+     * it would cause problems for devices like IOC3 (Lost
+     * interrupts ?.). So, just cleanup the interrupt, and
+     * use saved values later..
+     */
+    bridge->b_int_rst_stat = pcibr_errintr_group(int_status);
+
+    /* Zero out bserr_intstat field */
+    test_and_set_int((int *) &pcibr_soft->bs_errinfo.bserr_intstat, 0);
+}
+
+/*
+ * pcibr_addr_toslot
+ *      Given the 'pciaddr' find out which slot this address is
+ *      allocated to, and return the slot number.
+ *      While we have the info handy, construct the
+ *      function number, space code and offset as well.
+ *
+ * NOTE: if this routine is called, we don't know whether
+ * the address is in CFG, MEM, or I/O space. We have to guess.
+ * This will be the case on PIO stores, where the only way
+ * we have of getting the address is to check the Bridge, which
+ * stores the PCI address but not the space and not the xtalk
+ * address (from which we could get it).
+ */
+int
+pcibr_addr_toslot(pcibr_soft_t pcibr_soft,
+		  iopaddr_t pciaddr,
+		  pciio_space_t *spacep,
+		  iopaddr_t *offsetp,
+		  pciio_function_t *funcp)
+{
+    int                     s, f, w;
+    iopaddr_t               base;
+    size_t                  size;
+    pciio_piospace_t        piosp;
+
+    /*
+     * Check if the address is in config space
+     */
+
+    if ((pciaddr >= BRIDGE_CONFIG_BASE) && (pciaddr < BRIDGE_CONFIG_END)) {
+
+	if (pciaddr >= BRIDGE_CONFIG1_BASE)
+	    pciaddr -= BRIDGE_CONFIG1_BASE;
+	else
+	    pciaddr -= BRIDGE_CONFIG_BASE;
+
+	s = pciaddr / BRIDGE_CONFIG_SLOT_SIZE;
+	pciaddr %= BRIDGE_CONFIG_SLOT_SIZE;
+
+	if (funcp) {
+	    f = pciaddr / 0x100;
+	    pciaddr %= 0x100;
+	}
+	if (spacep)
+	    *spacep = PCIIO_SPACE_CFG;
+	if (offsetp)
+	    *offsetp = pciaddr;
+	if (funcp)
+	    *funcp = f;
+
+	return s;
+    }
+    for (s = 0; s < 8; s++) {
+	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
+	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
+
+	for (f = 0; f < nf; f++) {
+	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
+
+	    if (!pcibr_info)
+		continue;
+	    for (w = 0; w < 6; w++) {
+		if (pcibr_info->f_window[w].w_space
+		    == PCIIO_SPACE_NONE) {
+		    continue;
+		}
+		base = pcibr_info->f_window[w].w_base;
+		size = pcibr_info->f_window[w].w_size;
+
+		if ((pciaddr >= base) && (pciaddr < (base + size))) {
+		    if (spacep)
+			*spacep = PCIIO_SPACE_WIN(w);
+		    if (offsetp)
+			*offsetp = pciaddr - base;
+		    if (funcp)
+			*funcp = f;
+		    return s;
+		}			/* endif match */
+	    }				/* next window */
+	}				/* next func */
+    }					/* next slot */
+
+    /*
+     * Check if the address was allocated as part of the
+     * pcibr_piospace_alloc calls.
+     */
+    for (s = 0; s < 8; s++) {
+	int                     nf = pcibr_soft->bs_slot[s].bss_ninfo;
+	pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[s].bss_infos;
+
+	for (f = 0; f < nf; f++) {
+	    pcibr_info_t            pcibr_info = pcibr_infoh[f];
+
+	    if (!pcibr_info)
+		continue;
+	    piosp = pcibr_info->f_piospace;
+	    while (piosp) {
+		if ((piosp->start <= pciaddr) &&
+		    ((piosp->count + piosp->start) > pciaddr)) {
+		    if (spacep)
+			*spacep = piosp->space;
+		    if (offsetp)
+			*offsetp = pciaddr - piosp->start;
+		    return s;
+		}			/* endif match */
+		piosp = piosp->next;
+	    }				/* next piosp */
+	}				/* next func */
+    }					/* next slot */
+
+    /*
+     * Some other random address on the PCI bus ...
+     * we have no way of knowing whether this was
+     * a MEM or I/O access; so, for now, we just
+     * assume that the low 1G is MEM, the next
+     * 3G is I/O, and anything above the 4G limit
+     * is obviously MEM.
+     */
+
+    if (spacep)
+	*spacep = ((pciaddr < (1ul << 30)) ? PCIIO_SPACE_MEM :
+		   (pciaddr < (4ul << 30)) ? PCIIO_SPACE_IO :
+		   PCIIO_SPACE_MEM);
+    if (offsetp)
+	*offsetp = pciaddr;
+
+    return PCIIO_SLOT_NONE;
+
+}
+
+void
+pcibr_error_cleanup(pcibr_soft_t pcibr_soft, int error_code)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    ASSERT(error_code & IOECODE_PIO);
+    error_code = error_code;
+
+    bridge->b_int_rst_stat =
+	(BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR);
+    (void) bridge->b_wid_tflush;	/* flushbus */
+}
+
+/*
+ * pcibr_error_extract
+ *      Given the 'pcibr vertex handle' find out which slot
+ *      the bridge status error address (from pcibr_soft info
+ *      hanging off the vertex)
+ *      allocated to, and return the slot number.
+ *      While we have the info handy, construct the
+ *      space code and offset as well.
+ *
+ * NOTE: if this routine is called, we don't know whether
+ * the address is in CFG, MEM, or I/O space. We have to guess.
+ * This will be the case on PIO stores, where the only way
+ * we have of getting the address is to check the Bridge, which
+ * stores the PCI address but not the space and not the xtalk
+ * address (from which we could get it).
+ *
+ * XXX- this interface has no way to return the function
+ * number on a multifunction card, even though that data
+ * is available.
+ */
+
+pciio_slot_t
+pcibr_error_extract(devfs_handle_t pcibr_vhdl,
+		    pciio_space_t *spacep,
+		    iopaddr_t *offsetp)
+{
+    pcibr_soft_t            pcibr_soft = 0;
+    iopaddr_t               bserr_addr;
+    bridge_t               *bridge;
+    pciio_slot_t            slot = PCIIO_SLOT_NONE;
+    arbitrary_info_t	    rev;
+
+    /* Do a sanity check as to whether we really got a 
+     * bridge vertex handle.
+     */
+    if (hwgraph_info_get_LBL(pcibr_vhdl, INFO_LBL_PCIBR_ASIC_REV, &rev) !=
+	GRAPH_SUCCESS) 
+	return(slot);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (pcibr_soft) {
+	bridge = pcibr_soft->bs_base;
+	bserr_addr =
+	    bridge->b_pci_err_lower |
+	    ((uint64_t) (bridge->b_pci_err_upper &
+			   BRIDGE_ERRUPPR_ADDRMASK) << 32);
+
+	slot = pcibr_addr_toslot(pcibr_soft, bserr_addr,
+				 spacep, offsetp, NULL);
+    }
+    return slot;
+}
+
+/*ARGSUSED */
+void
+pcibr_device_disable(pcibr_soft_t pcibr_soft, int devnum)
+{
+    /*
+     * XXX
+     * Device failed to handle error. Take steps to
+     * disable this device ? HOW TO DO IT ?
+     *
+     * If there are any Read response buffers associated
+     * with this device, it's time to get them back!!
+     *
+     * We can disassociate any interrupt level associated
+     * with this device, and disable that interrupt level
+     *
+     * For now it's just a place holder
+     */
+}
+
+/*
+ * pcibr_pioerror
+ *      Handle PIO error that happened at the bridge pointed by pcibr_soft.
+ *
+ *      Queries the Bus interface attached to see if the device driver
+ *      mapping the device-number that caused error can handle the
+ *      situation. If so, it will clean up any error, and return
+ *      indicating the error was handled. If the device driver is unable
+ *      to handle the error, it expects the bus-interface to disable that
+ *      device, and takes any steps needed here to take away any resources
+ *      associated with this device.
+ */
+
+#define BEM_ADD_STR(s)	printk("%s", (s))
+#define BEM_ADD_VAR(v)	printk("\t%20s: 0x%x\n", #v, (v))
+#define BEM_ADD_REG(r)	printk("\t%20s: %R\n", #r, (r), r ## _desc)
+
+#define BEM_ADD_NSPC(n,s)	printk("\t%20s: %R\n", n, s, space_desc)
+#define BEM_ADD_SPC(s)		BEM_ADD_NSPC(#s, s)
+
+/* BEM_ADD_IOE doesn't dump the whole ioerror, it just
+ * decodes the PCI specific portions -- we count on our
+ * callers to dump the raw IOE data.
+ */
+#define BEM_ADD_IOE(ioe)						\
+	do {								\
+	    if (IOERROR_FIELDVALID(ioe, busspace)) {			\
+		unsigned		spc;				\
+		unsigned		win;				\
+									\
+		spc = IOERROR_GETVALUE(ioe, busspace);			\
+		win = spc - PCIIO_SPACE_WIN(0);				\
+									\
+		switch (spc) {						\
+		case PCIIO_SPACE_CFG:					\
+		    printk(					\
+			    "\tPCI Slot %d Func %d CFG space Offset 0x%x\n",	\
+	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		case PCIIO_SPACE_IO:					\
+		    printk(					\
+			    "\tPCI I/O space  Offset 0x%x\n",		\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		case PCIIO_SPACE_MEM:					\
+		case PCIIO_SPACE_MEM32:					\
+		case PCIIO_SPACE_MEM64:					\
+		    printk(					\
+			    "\tPCI MEM space Offset 0x%x\n",		\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    break;						\
+		default:						\
+		    if (win < 6) {					\
+		    printk(					\
+			    "\tPCI Slot %d Func %d Window %d Offset 0x%x\n",\
+	    pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+	    pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, widgetdev)),	\
+			    win,					\
+			    IOERROR_GETVALUE(ioe, busaddr));		\
+		    }							\
+		    break;						\
+		}							\
+	    }								\
+	} while (0)
+
+/*ARGSUSED */
+int
+pcibr_pioerror(
+		  pcibr_soft_t pcibr_soft,
+		  int error_code,
+		  ioerror_mode_t mode,
+		  ioerror_t *ioe)
+{
+    int                     retval = IOERROR_HANDLED;
+
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+
+    iopaddr_t               bad_xaddr;
+
+    pciio_space_t           raw_space;	/* raw PCI space */
+    iopaddr_t               raw_paddr;	/* raw PCI address */
+
+    pciio_space_t           space;	/* final PCI space */
+    pciio_slot_t            slot;	/* final PCI slot, if appropriate */
+    pciio_function_t        func;	/* final PCI func, if appropriate */
+    iopaddr_t               offset;	/* final PCI offset */
+    
+    int                     cs, cw, cf;
+    pciio_space_t           wx;
+    iopaddr_t               wb;
+    size_t                  ws;
+    iopaddr_t               wl;
+
+
+    /*
+     * We expect to have an "xtalkaddr" coming in,
+     * and need to construct the slot/space/offset.
+     */
+
+    bad_xaddr = IOERROR_GETVALUE(ioe, xtalkaddr);
+
+    slot = PCIIO_SLOT_NONE;
+    func = PCIIO_FUNC_NONE;
+    raw_space = PCIIO_SPACE_NONE;
+    raw_paddr = 0;
+
+    if ((bad_xaddr >= BRIDGE_TYPE0_CFG_DEV0) &&
+	(bad_xaddr < BRIDGE_TYPE1_CFG)) {
+	raw_paddr = bad_xaddr - BRIDGE_TYPE0_CFG_DEV0;
+	slot = raw_paddr / BRIDGE_TYPE0_CFG_SLOT_OFF;
+	raw_paddr = raw_paddr % BRIDGE_TYPE0_CFG_SLOT_OFF;
+	raw_space = PCIIO_SPACE_CFG;
+    }
+    if ((bad_xaddr >= BRIDGE_TYPE1_CFG) &&
+	(bad_xaddr < (BRIDGE_TYPE1_CFG + 0x1000))) {
+	/* Type 1 config space:
+	 * slot and function numbers not known.
+	 * Perhaps we can read them back?
+	 */
+	raw_paddr = bad_xaddr - BRIDGE_TYPE1_CFG;
+	raw_space = PCIIO_SPACE_CFG;
+    }
+    if ((bad_xaddr >= BRIDGE_DEVIO0) &&
+	(bad_xaddr < BRIDGE_DEVIO(BRIDGE_DEV_CNT))) {
+	int                     x;
+
+	raw_paddr = bad_xaddr - BRIDGE_DEVIO0;
+	x = raw_paddr / BRIDGE_DEVIO_OFF;
+	raw_paddr %= BRIDGE_DEVIO_OFF;
+	/* first two devio windows are double-sized */
+	if ((x == 1) || (x == 3))
+	    raw_paddr += BRIDGE_DEVIO_OFF;
+	if (x > 0)
+	    x--;
+	if (x > 1)
+	    x--;
+	/* x is which devio reg; no guarantee
+	 * PCI slot x will be responding.
+	 * still need to figure out who decodes
+	 * space/offset on the bus.
+	 */
+	raw_space = pcibr_soft->bs_slot[x].bss_devio.bssd_space;
+	if (raw_space == PCIIO_SPACE_NONE) {
+	    /* Someone got an error because they
+	     * accessed the PCI bus via a DevIO(x)
+	     * window that pcibr has not yet assigned
+	     * to any specific PCI address. It is
+	     * quite possible that the Device(x)
+	     * register has been changed since they
+	     * made their access, but we will give it
+	     * our best decode shot.
+	     */
+	    raw_space = pcibr_soft->bs_slot[x].bss_device
+		& BRIDGE_DEV_DEV_IO_MEM
+		? PCIIO_SPACE_MEM
+		: PCIIO_SPACE_IO;
+	    raw_paddr +=
+		(pcibr_soft->bs_slot[x].bss_device &
+		 BRIDGE_DEV_OFF_MASK) <<
+		BRIDGE_DEV_OFF_ADDR_SHFT;
+	} else
+	    raw_paddr += pcibr_soft->bs_slot[x].bss_devio.bssd_base;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_MEM32_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_MEM32_LIMIT)) {
+	raw_space = PCIIO_SPACE_MEM32;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM32_BASE;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_MEM64_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_MEM64_LIMIT)) {
+	raw_space = PCIIO_SPACE_MEM64;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_MEM64_BASE;
+    }
+    if ((bad_xaddr >= BRIDGE_PCI_IO_BASE) &&
+	(bad_xaddr <= BRIDGE_PCI_IO_LIMIT)) {
+	raw_space = PCIIO_SPACE_IO;
+	raw_paddr = bad_xaddr - BRIDGE_PCI_IO_BASE;
+    }
+    space = raw_space;
+    offset = raw_paddr;
+
+    if ((slot == PCIIO_SLOT_NONE) && (space != PCIIO_SPACE_NONE)) {
+	/* we've got a space/offset but not which
+	 * PCI slot decodes it. Check through our
+	 * notions of which devices decode where.
+	 *
+	 * Yes, this "duplicates" some logic in
+	 * pcibr_addr_toslot; the difference is,
+	 * this code knows which space we are in,
+	 * and can really really tell what is
+	 * going on (no guessing).
+	 */
+
+	for (cs = 0; (cs < 8) && (slot == PCIIO_SLOT_NONE); cs++) {
+	    int                     nf = pcibr_soft->bs_slot[cs].bss_ninfo;
+	    pcibr_info_h            pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
+
+	    for (cf = 0; (cf < nf) && (slot == PCIIO_SLOT_NONE); cf++) {
+		pcibr_info_t            pcibr_info = pcibr_infoh[cf];
+
+		if (!pcibr_info)
+		    continue;
+		for (cw = 0; (cw < 6) && (slot == PCIIO_SLOT_NONE); ++cw) {
+		    if (((wx = pcibr_info->f_window[cw].w_space) != PCIIO_SPACE_NONE) &&
+			((wb = pcibr_info->f_window[cw].w_base) != 0) &&
+			((ws = pcibr_info->f_window[cw].w_size) != 0) &&
+			((wl = wb + ws) > wb) &&
+			((wb <= offset) && (wl > offset))) {
+			/* MEM, MEM32 and MEM64 need to
+			 * compare as equal ...
+			 */
+			if ((wx == space) ||
+			    (((wx == PCIIO_SPACE_MEM) ||
+			      (wx == PCIIO_SPACE_MEM32) ||
+			      (wx == PCIIO_SPACE_MEM64)) &&
+			     ((space == PCIIO_SPACE_MEM) ||
+			      (space == PCIIO_SPACE_MEM32) ||
+			      (space == PCIIO_SPACE_MEM64)))) {
+			    slot = cs;
+			    func = cf;
+			    space = PCIIO_SPACE_WIN(cw);
+			    offset -= wb;
+			}		/* endif window space match */
+		    }			/* endif window valid and addr match */
+		}			/* next window unless slot set */
+	    }				/* next func unless slot set */
+	}				/* next slot unless slot set */
+	/* XXX- if slot is still -1, no PCI devices are
+	 * decoding here using their standard PCI BASE
+	 * registers. This would be a really good place
+	 * to cross-coordinate with the pciio PCI
+	 * address space allocation routines, to find
+	 * out if this address is "allocated" by any of
+	 * our subsidiary devices.
+	 */
+    }
+    /* Scan all piomap records on this PCI bus to update
+     * the TimeOut Counters on all matching maps. If we
+     * don't already know the slot number, take it from
+     * the first matching piomap. Note that we have to
+     * compare maps against raw_space and raw_paddr
+     * since space and offset could already be
+     * window-relative.
+     *
+     * There is a chance that one CPU could update
+     * through this path, and another CPU could also
+     * update due to an interrupt. Closing this hole
+     * would only result in the possibility of some
+     * errors never getting logged at all, and since the
+     * use for bp_toc is as a logical test rather than a
+     * strict count, the excess counts are not a
+     * problem.
+     */
+    for (cs = 0; cs < 8; ++cs) {
+	int 		nf = pcibr_soft->bs_slot[cs].bss_ninfo;
+	pcibr_info_h	pcibr_infoh = pcibr_soft->bs_slot[cs].bss_infos;
+
+	for (cf = 0; cf < nf; cf++) {
+	    pcibr_info_t 	pcibr_info = pcibr_infoh[cf];
+	    pcibr_piomap_t	map;    
+
+	    if (!pcibr_info)
+		continue;
+
+	    for (map = pcibr_info->f_piomap;
+	     map != NULL; map = map->bp_next) {
+	    wx = map->bp_space;
+	    wb = map->bp_pciaddr;
+	    ws = map->bp_mapsz;
+	    cw = wx - PCIIO_SPACE_WIN(0);
+	    if (cw < 6) {
+		wb += pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
+		wx = pcibr_soft->bs_slot[cs].bss_window[cw].bssw_space;
+	    }
+	    if (wx == PCIIO_SPACE_ROM) {
+		wb += pcibr_info->f_rbase;
+		wx = PCIIO_SPACE_MEM;
+	    }
+	    if ((wx == PCIIO_SPACE_MEM32) ||
+		(wx == PCIIO_SPACE_MEM64))
+		wx = PCIIO_SPACE_MEM;
+	    wl = wb + ws;
+	    if ((wx == raw_space) && (raw_paddr >= wb) && (raw_paddr < wl)) {
+		atomicAddInt(map->bp_toc, 1);
+		if (slot == PCIIO_SLOT_NONE) {
+		    slot = cs;
+		    space = map->bp_space;
+		    if (cw < 6)
+			offset -= pcibr_soft->bs_slot[cs].bss_window[cw].bssw_base;
+		}
+	    }
+	    }
+	}
+    }
+
+    if (space != PCIIO_SPACE_NONE) {
+	if (slot != PCIIO_SLOT_NONE) 
+	    if (func != PCIIO_FUNC_NONE)
+		IOERROR_SETVALUE(ioe, widgetdev, 
+				 pciio_widgetdev_create(slot,func));
+	    else
+    		IOERROR_SETVALUE(ioe, widgetdev, 
+				 pciio_widgetdev_create(slot,0));
+
+	IOERROR_SETVALUE(ioe, busspace, space);
+	IOERROR_SETVALUE(ioe, busaddr, offset);
+    }
+    if (mode == MODE_DEVPROBE) {
+	/*
+	 * During probing, we don't really care what the
+	 * error is. Clean up the error in Bridge, notify
+	 * subsidiary devices, and return success.
+	 */
+	pcibr_error_cleanup(pcibr_soft, error_code);
+
+	/* if appropriate, give the error handler for this slot
+	 * a shot at this probe access as well.
+	 */
+	return (slot == PCIIO_SLOT_NONE) ? IOERROR_HANDLED :
+	    pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+    }
+    /*
+     * If we don't know what "PCI SPACE" the access
+     * was targeting, we may have problems at the
+     * Bridge itself. Don't touch any bridge registers,
+     * and do complain loudly.
+     */
+
+    if (space == PCIIO_SPACE_NONE) {
+	printk("XIO Bus Error at %s\n"
+		"\taccess to XIO bus offset 0x%x\n"
+		"\tdoes not correspond to any PCI address\n",
+		pcibr_soft->bs_name, bad_xaddr);
+
+	/* caller will dump contents of ioe struct */
+	return IOERROR_XTALKLEVEL;
+    }
+
+    /*
+     * Actual PCI Error handling situation.
+     * Typically happens when a user level process accesses
+     * PCI space, and it causes some error.
+     *
+     * Due to PCI Bridge implementation, we get two indication
+     * for a read error: an interrupt and a Bus error.
+     * We like to handle read error in the bus error context.
+     * But the interrupt comes and goes before bus error
+     * could make much progress. (NOTE: interrupd does
+     * come in _after_ bus error processing starts. But it's
+     * completed by the time bus error code reaches PCI PIO
+     * error handling.
+     * Similarly write error results in just an interrupt,
+     * and error handling has to be done at interrupt level.
+     * There is no way to distinguish at interrupt time, if an
+     * error interrupt is due to read/write error..
+     */
+
+    /* We know the xtalk addr, the raw PCI bus space,
+     * the raw PCI bus address, the decoded PCI bus
+     * space, the offset within that space, and the
+     * decoded PCI slot (which may be "PCIIO_SLOT_NONE" if no slot
+     * is known to be involved).
+     */
+
+    /*
+     * Hand the error off to the handler registered
+     * for the slot that should have decoded the error,
+     * or to generic PCI handling (if pciio decides that
+     * such is appropriate).
+     */
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+
+    if (retval != IOERROR_HANDLED) {
+
+	/* Generate a generic message for IOERROR_UNHANDLED
+	 * since the subsidiary handlers were silent, and
+	 * did no recovery.
+	 */
+	if (retval == IOERROR_UNHANDLED) {
+	    retval = IOERROR_PANIC;
+
+	    /* we may or may not want to print some of this,
+	     * depending on debug level and which error code.
+	     */
+
+	    printk(KERN_ALERT
+		    "PIO Error on PCI Bus %s",
+		    pcibr_soft->bs_name);
+	    /* this decodes part of the ioe; our caller
+	     * will dump the raw details in DEBUG and
+	     * kdebug kernels.
+	     */
+	    BEM_ADD_IOE(ioe);
+	}
+#if defined(FORCE_ERRORS)
+	if (0) {
+#elif !DEBUG
+	if (kdebug) {
+#endif
+	    /*
+	     * Dump raw data from Bridge/PCI layer.
+	     */
+
+	    BEM_ADD_STR("Raw info from Bridge/PCI layer:\n");
+	    if (bridge->b_int_status & BRIDGE_ISR_PCIBUS_PIOERR)
+		pcibr_error_dump(pcibr_soft);
+	    BEM_ADD_SPC(raw_space);
+	    BEM_ADD_VAR(raw_paddr);
+	    if (IOERROR_FIELDVALID(ioe, widgetdev)) {
+
+		slot = pciio_widgetdev_slot_get(IOERROR_GETVALUE(ioe, 
+								 widgetdev));
+		func = pciio_widgetdev_func_get(IOERROR_GETVALUE(ioe, 
+								 widgetdev));
+		if (slot < 8) {
+		    bridgereg_t             device = bridge->b_device[slot].reg;
+
+		    BEM_ADD_VAR(slot);
+		    BEM_ADD_VAR(func);
+		    BEM_ADD_REG(device);
+		}
+	    }
+#if !DEBUG || defined(FORCE_ERRORS)
+	}
+#endif
+
+	/*
+	 * Since error could not be handled at lower level,
+	 * error data logged has not  been cleared.
+	 * Clean up errors, and
+	 * re-enable bridge to interrupt on error conditions.
+	 * NOTE: Wheather we get the interrupt on PCI_ABORT or not is
+	 * dependent on INT_ENABLE register. This write just makes sure
+	 * that if the interrupt was enabled, we do get the interrupt.
+	 *
+	 * CAUTION: Resetting bit BRIDGE_IRR_PCI_GRP_CLR, acknowledges
+	 *      a group of interrupts. If while handling this error,
+	 *      some other error has occured, that would be
+	 *      implicitly cleared by this write.
+	 *      Need a way to ensure we don't inadvertently clear some
+	 *      other errors.
+	 */
+	if (IOERROR_FIELDVALID(ioe, widgetdev))
+	    pcibr_device_disable(pcibr_soft, 
+				 pciio_widgetdev_slot_get(
+					  IOERROR_GETVALUE(ioe, widgetdev)));
+
+	if (mode == MODE_DEVUSERERROR)
+	    pcibr_error_cleanup(pcibr_soft, error_code);
+    }
+    return retval;
+}
+
+/*
+ * bridge_dmaerror
+ *      Some error was identified in a DMA transaction.
+ *      This routine will identify the <device, address> that caused the error,
+ *      and try to invoke the appropriate bus service to handle this.
+ */
+
+#define BRIDGE_DMA_READ_ERROR (BRIDGE_ISR_RESP_XTLK_ERR|BRIDGE_ISR_XREAD_REQ_TIMEOUT)
+
+int
+pcibr_dmard_error(
+		     pcibr_soft_t pcibr_soft,
+		     int error_code,
+		     ioerror_mode_t mode,
+		     ioerror_t *ioe)
+{
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    bridgereg_t             bus_lowaddr, bus_uppraddr;
+    int                     retval = 0;
+    int                     bufnum;
+
+    /*
+     * In case of DMA errors, bridge should have logged the
+     * address that caused the error.
+     * Look up the address, in the bridge error registers, and
+     * take appropriate action
+     */
+    ASSERT(IOERROR_GETVALUE(ioe, widgetnum) == pcibr_soft->bs_xid);
+    ASSERT(bridge);
+
+    /*
+     * read error log registers
+     */
+    bus_lowaddr = bridge->b_wid_resp_lower;
+    bus_uppraddr = bridge->b_wid_resp_upper;
+
+    bufnum = BRIDGE_RESP_ERRUPPR_BUFNUM(bus_uppraddr);
+    IOERROR_SETVALUE(ioe, widgetdev, 
+		     pciio_widgetdev_create(
+				    BRIDGE_RESP_ERRUPPR_DEVICE(bus_uppraddr),
+				    0));
+    IOERROR_SETVALUE(ioe, busaddr,
+		     (bus_lowaddr |
+		      ((iopaddr_t)
+		       (bus_uppraddr &
+			BRIDGE_ERRUPPR_ADDRMASK) << 32)));
+
+    /*
+     * need to ensure that the xtalk adress in ioe
+     * maps to PCI error address read from bridge.
+     * How to convert PCI address back to Xtalk address ?
+     * (better idea: convert XTalk address to PCI address
+     * and then do the compare!)
+     */
+
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+    if (retval != IOERROR_HANDLED)
+	pcibr_device_disable(pcibr_soft, 
+			     pciio_widgetdev_slot_get(
+				      IOERROR_GETVALUE(ioe,widgetdev)));
+
+    /*
+     * Re-enable bridge to interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR
+     * NOTE: Wheather we get the interrupt on BRIDGE_IRR_RESP_BUF_GRP_CLR or
+     * not is dependent on INT_ENABLE register. This write just makes sure
+     * that if the interrupt was enabled, we do get the interrupt.
+     */
+    bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR;
+
+    /*
+     * Also, release the "bufnum" back to buffer pool that could be re-used.
+     * This is done by "disabling" the buffer for a moment, then restoring
+     * the original assignment.
+     */
+
+    {
+	reg_p                   regp;
+	bridgereg_t             regv;
+	bridgereg_t             mask;
+
+	regp = (bufnum & 1)
+	    ? &bridge->b_odd_resp
+	    : &bridge->b_even_resp;
+
+	mask = 0xF << ((bufnum >> 1) * 4);
+
+	regv = *regp;
+	*regp = regv & ~mask;
+	*regp = regv;
+    }
+
+    return retval;
+}
+
+/*
+ * pcibr_dmawr_error:
+ *      Handle a dma write error caused by a device attached to this bridge.
+ *
+ *      ioe has the widgetnum, widgetdev, and memaddr fields updated
+ *      But we don't know the PCI address that corresponds to "memaddr"
+ *      nor do we know which device driver is generating this address.
+ *
+ *      There is no easy way to find out the PCI address(es) that map
+ *      to a specific system memory address. Bus handling code is also
+ *      of not much help, since they don't keep track of the DMA mapping
+ *      that have been handed out.
+ *      So it's a dead-end at this time.
+ *
+ *      If translation is available, we could invoke the error handling
+ *      interface of the device driver.
+ */
+/*ARGSUSED */
+int
+pcibr_dmawr_error(
+		     pcibr_soft_t pcibr_soft,
+		     int error_code,
+		     ioerror_mode_t mode,
+		     ioerror_t *ioe)
+{
+    devfs_handle_t            pcibr_vhdl = pcibr_soft->bs_vhdl;
+    int                     retval;
+
+    retval = pciio_error_handler(pcibr_vhdl, error_code, mode, ioe);
+
+    if (retval != IOERROR_HANDLED) {
+	pcibr_device_disable(pcibr_soft, 
+			     pciio_widgetdev_slot_get(
+				      IOERROR_GETVALUE(ioe, widgetdev)));
+
+    }
+    return retval;
+}
+
+/*
+ * Bridge error handler.
+ *      Interface to handle all errors that involve bridge in some way.
+ *
+ *      This normally gets called from xtalk error handler.
+ *      ioe has different set of fields set depending on the error that
+ *      was encountered. So, we have a bit field indicating which of the
+ *      fields are valid.
+ *
+ * NOTE: This routine could be operating in interrupt context. So,
+ *      don't try to sleep here (till interrupt threads work!!)
+ */
+int
+pcibr_error_handler(
+		       error_handler_arg_t einfo,
+		       int error_code,
+		       ioerror_mode_t mode,
+		       ioerror_t *ioe)
+{
+    pcibr_soft_t            pcibr_soft;
+    int                     retval = IOERROR_BADERRORCODE;
+
+#ifdef EHE_ENABLE
+    devfs_handle_t	    xconn_vhdl,pcibr_vhdl;
+    error_state_t	    e_state;
+#endif /* EHE_ENABLE */
+
+    pcibr_soft = (pcibr_soft_t) einfo;
+
+#ifdef EHE_ENABLE
+    xconn_vhdl = pcibr_soft->bs_conn;
+    pcibr_vhdl = pcibr_soft->bs_vhdl;
+
+    e_state = error_state_get(xconn_vhdl);
+    
+    if (error_state_set(pcibr_vhdl, e_state) == 
+	ERROR_RETURN_CODE_CANNOT_SET_STATE)
+	return(IOERROR_UNHANDLED);
+
+    /* If we are in the action handling phase clean out the error state
+     * on the xswitch.
+     */
+    if (e_state == ERROR_STATE_ACTION)
+	(void)error_state_set(xconn_vhdl, ERROR_STATE_NONE);
+#endif /* EHE_ENABLE */
+
+#if DEBUG && ERROR_DEBUG
+    printk("%s: pcibr_error_handler\n", pcibr_soft->bs_name);
+#endif
+
+    ASSERT(pcibr_soft != NULL);
+
+    if (error_code & IOECODE_PIO)
+	retval = pcibr_pioerror(pcibr_soft, error_code, mode, ioe);
+
+    if (error_code & IOECODE_DMA) {
+	if (error_code & IOECODE_READ) {
+	    /*
+	     * DMA read error occurs when a device attached to the bridge
+	     * tries to read some data from system memory, and this
+	     * either results in a timeout or access error.
+	     * First case is indicated by the bit "XREAD_REQ_TOUT"
+	     * and second case by "RESP_XTALK_ERROR" bit in bridge error
+	     * interrupt status register.
+	     *
+	     * pcibr_error_intr_handler would get invoked first, and it has
+	     * the responsibility of calling pcibr_error_handler with
+	     * suitable parameters.
+	     */
+
+	    retval = pcibr_dmard_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
+	}
+	if (error_code & IOECODE_WRITE) {
+	    /*
+	     * A device attached to this bridge has been generating
+	     * bad DMA writes. Find out the device attached, and
+	     * slap on it's wrist.
+	     */
+
+	    retval = pcibr_dmawr_error(pcibr_soft, error_code, MODE_DEVERROR, ioe);
+	}
+    }
+    return retval;
+
+}
+
+/*
+ * Reenable a device after handling the error.
+ * This is called by the lower layers when they wish to be reenabled
+ * after an error.
+ * Note that each layer would be calling the previous layer to reenable
+ * first, before going ahead with their own re-enabling.
+ */
+
+int
+pcibr_error_devenable(devfs_handle_t pconn_vhdl, int error_code)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+
+    ASSERT(error_code & IOECODE_PIO);
+
+    /* If the error is not known to be a write,
+     * we have to call devenable.
+     * write errors are isolated to the bridge.
+     */
+    if (!(error_code & IOECODE_WRITE)) {
+	devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+	int                     rc;
+
+	rc = xtalk_error_devenable(xconn_vhdl, pciio_slot, error_code);
+	if (rc != IOERROR_HANDLED)
+	    return rc;
+    }
+    pcibr_error_cleanup(pcibr_soft, error_code);
+    return IOERROR_HANDLED;
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_hints.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,204 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+pcibr_hints_t           pcibr_hints_get(devfs_handle_t, int);
+void                    pcibr_hints_fix_rrbs(devfs_handle_t);
+void                    pcibr_hints_dualslot(devfs_handle_t, pciio_slot_t, pciio_slot_t);
+void			pcibr_hints_intr_bits(devfs_handle_t, pcibr_intr_bits_f *);
+void                    pcibr_set_rrb_callback(devfs_handle_t, rrb_alloc_funct_t);
+void                    pcibr_hints_handsoff(devfs_handle_t);
+void                    pcibr_hints_subdevs(devfs_handle_t, pciio_slot_t, uint64_t);
+
+pcibr_hints_t
+pcibr_hints_get(devfs_handle_t xconn_vhdl, int alloc)
+{
+    arbitrary_info_t        ainfo = 0;
+    graph_error_t	    rv;
+    pcibr_hints_t           hint;
+
+    rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+
+    if (alloc && (rv != GRAPH_SUCCESS)) {
+
+	NEW(hint);
+	hint->rrb_alloc_funct = NULL;
+	hint->ph_intr_bits = NULL;
+	rv = hwgraph_info_add_LBL(xconn_vhdl, 
+				  INFO_LBL_PCIBR_HINTS, 	
+				  (arbitrary_info_t) hint);
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	rv = hwgraph_info_get_LBL(xconn_vhdl, INFO_LBL_PCIBR_HINTS, &ainfo);
+	
+	if (rv != GRAPH_SUCCESS)
+	    goto abnormal_exit;
+
+	if (ainfo != (arbitrary_info_t) hint)
+	    goto abnormal_exit;
+    }
+    return (pcibr_hints_t) ainfo;
+
+abnormal_exit:
+#ifdef LATER
+    printf("SHOULD NOT BE HERE\n");
+#endif
+    DEL(hint);
+    return(NULL);
+
+}
+
+void
+pcibr_hints_fix_some_rrbs(devfs_handle_t xconn_vhdl, unsigned mask)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_rrb_fixed = mask;
+#if DEBUG
+    else
+	printk("pcibr_hints_fix_rrbs: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_fix_rrbs(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_fix_some_rrbs(xconn_vhdl, 0xFF);
+}
+
+void
+pcibr_hints_dualslot(devfs_handle_t xconn_vhdl,
+		     pciio_slot_t host,
+		     pciio_slot_t guest)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_host_slot[guest] = host + 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_dualslot: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_intr_bits(devfs_handle_t xconn_vhdl,
+		      pcibr_intr_bits_f *xxx_intr_bits)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_intr_bits = xxx_intr_bits;
+#if DEBUG
+    else
+	printk("pcibr_hints_intr_bits: pcibr_hints_get failed at\n"
+	       "\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_set_rrb_callback(devfs_handle_t xconn_vhdl, rrb_alloc_funct_t rrb_alloc_funct)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->rrb_alloc_funct = rrb_alloc_funct;
+}
+
+void
+pcibr_hints_handsoff(devfs_handle_t xconn_vhdl)
+{
+    pcibr_hints_t           hint = pcibr_hints_get(xconn_vhdl, 1);
+
+    if (hint)
+	hint->ph_hands_off = 1;
+#if DEBUG
+    else
+	printk("pcibr_hints_handsoff: pcibr_hints_get failed at\n"
+		"\t%p\n", xconn_vhdl);
+#endif
+}
+
+void
+pcibr_hints_subdevs(devfs_handle_t xconn_vhdl,
+		    pciio_slot_t slot,
+		    uint64_t subdevs)
+{
+    arbitrary_info_t        ainfo = 0;
+    char                    sdname[16];
+    devfs_handle_t            pconn_vhdl = GRAPH_VERTEX_NONE;
+
+    sprintf(sdname, "pci/%d", slot);
+    (void) hwgraph_path_add(xconn_vhdl, sdname, &pconn_vhdl);
+    if (pconn_vhdl == GRAPH_VERTEX_NONE) {
+#if DEBUG
+	printk("pcibr_hints_subdevs: hwgraph_path_create failed at\n"
+		"\t%p (seeking %s)\n", xconn_vhdl, sdname);
+#endif
+	return;
+    }
+    hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+    if (ainfo == 0) {
+	uint64_t                *subdevp;
+
+	NEW(subdevp);
+	if (!subdevp) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: subdev ptr alloc failed at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+	*subdevp = subdevs;
+	hwgraph_info_add_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, (arbitrary_info_t) subdevp);
+	hwgraph_info_get_LBL(pconn_vhdl, INFO_LBL_SUBDEVS, &ainfo);
+	if (ainfo == (arbitrary_info_t) subdevp)
+	    return;
+	DEL(subdevp);
+	if (ainfo == (arbitrary_info_t) NULL) {
+#if DEBUG
+	    printk("pcibr_hints_subdevs: null subdevs ptr at\n"
+		    "\t%p\n", pconn_vhdl);
+#endif
+	    return;
+	}
+#if DEBUG
+	printk("pcibr_subdevs_get: dup subdev add_LBL at\n"
+		"\t%p\n", pconn_vhdl);
+#endif
+    }
+    *(uint64_t *) ainfo = subdevs;
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_idbg.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,147 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef LATER
+
+char *pci_space[] = {"NONE", 
+		     "ROM",
+		     "IO",
+		     "",
+		     "MEM",
+		     "MEM32",
+		     "MEM64",
+		     "CFG",
+		     "WIN0",
+		     "WIN1",
+		     "WIN2",
+		     "WIN3",
+		     "WIN4",
+		     "WIN5",
+		     "",
+		     "BAD"};
+
+void
+idbg_pss_func(pcibr_info_h pcibr_infoh, int func)
+{
+    pcibr_info_t	pcibr_info = pcibr_infoh[func];
+    char		name[MAXDEVNAME];
+    int			win;
+    
+    if (!pcibr_info)
+	return;
+    qprintf("Per-slot Function Info\n");
+    sprintf(name, "%v", pcibr_info->f_vertex);
+    qprintf("\tSlot Name : %s\n",name);
+    qprintf("\tPCI Bus : %d ",pcibr_info->f_bus);
+    qprintf("Slot : %d ", pcibr_info->f_slot);
+    qprintf("Function : %d ", pcibr_info->f_func);
+    qprintf("VendorId : 0x%x " , pcibr_info->f_vendor);
+    qprintf("DeviceId : 0x%x\n", pcibr_info->f_device);
+    sprintf(name, "%v", pcibr_info->f_master);
+    qprintf("\tBus provider : %s\n",name);
+    qprintf("\tProvider Fns : 0x%x ", pcibr_info->f_pops);
+    qprintf("Error Handler : 0x%x Arg 0x%x\n", 
+	    pcibr_info->f_efunc,pcibr_info->f_einfo);
+    for(win = 0 ; win < 6 ; win++) 
+	qprintf("\tBase Reg #%d space %s base 0x%x size 0x%x\n",
+		win,pci_space[pcibr_info->f_window[win].w_space],
+		pcibr_info->f_window[win].w_base,
+		pcibr_info->f_window[win].w_size);
+
+    qprintf("\tRom base 0x%x size 0x%x\n", 
+	    pcibr_info->f_rbase,pcibr_info->f_rsize);
+
+    qprintf("\tInterrupt Bit Map\n");
+    qprintf("\t\tPCI Int#\tBridge Pin#\n");
+    for (win = 0 ; win < 4; win++)
+	qprintf("\t\tINT%c\t\t%d\n",win+'A',pcibr_info->f_ibit[win]);
+    qprintf("\n");
+}
+
+
+void
+idbg_pss_info(pcibr_soft_t pcibr_soft, pciio_slot_t slot)
+{
+    pcibr_soft_slot_t	pss;
+    char		slot_conn_name[MAXDEVNAME];
+    int			func;
+
+    pss = &pcibr_soft->bs_slot[slot];
+    qprintf("PCI INFRASTRUCTURAL INFO FOR SLOT %d\n", slot);
+    qprintf("\tHost Present ? %s ", pss->has_host ? "yes" : "no");
+    qprintf("\tHost Slot : %d\n",pss->host_slot);
+    sprintf(slot_conn_name, "%v", pss->slot_conn);
+    qprintf("\tSlot Conn : %s\n",slot_conn_name);	
+    qprintf("\t#Functions : %d\n",pss->bss_ninfo);
+    for (func = 0; func < pss->bss_ninfo; func++)
+	idbg_pss_func(pss->bss_infos,func);
+    qprintf("\tSpace : %s ",pci_space[pss->bss_devio.bssd_space]);
+    qprintf("\tBase : 0x%x ", pss->bss_devio.bssd_base);
+    qprintf("\tShadow Devreg : 0x%x\n", pss->bss_device);
+    qprintf("\tUsage counts : pmu %d d32 %d d64 %d\n",
+	    pss->bss_pmu_uctr,pss->bss_d32_uctr,pss->bss_d64_uctr);
+    
+    qprintf("\tDirect Trans Info : d64_base 0x%x d64_flags 0x%x"
+	    "d32_base 0x%x d32_flags 0x%x\n",
+	    pss->bss_d64_base, pss->bss_d64_flags,
+	    pss->bss_d32_base, pss->bss_d32_flags);
+    
+    qprintf("\tExt ATEs active ? %s", 
+	    pss->bss_ext_ates_active ? "yes" : "no");
+    qprintf(" Command register : 0x%x ", pss->bss_cmd_pointer);
+    qprintf(" Shadow command val : 0x%x\n", pss->bss_cmd_shadow);
+
+    qprintf("\tRRB Info : Valid %d+%d Reserved %d\n",
+	    pcibr_soft->bs_rrb_valid[slot],
+	    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+		
+}
+
+int	ips = 0;
+
+void
+idbg_pss(pcibr_soft_t pcibr_soft)
+{
+    pciio_slot_t	slot;
+
+    
+    if (ips >= 0 && ips < 8)
+	idbg_pss_info(pcibr_soft,ips);
+    else if (ips < 0)
+	for (slot = 0; slot < 8; slot++) 
+	    idbg_pss_info(pcibr_soft,slot);
+    else
+	qprintf("Invalid ips %d\n",ips);
+}
+#endif	/* LATER */
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_intr.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,907 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+#ifdef __ia64
+#define rmallocmap atemapalloc
+#define rmfreemap atemapfree
+#define rmfree atefree
+#define rmalloc atealloc
+#endif
+
+unsigned		pcibr_intr_bits(pciio_info_t info, pciio_intr_line_t lines);
+pcibr_intr_t            pcibr_intr_alloc(devfs_handle_t, device_desc_t, pciio_intr_line_t, devfs_handle_t);
+void                    pcibr_intr_free(pcibr_intr_t);
+void              pcibr_setpciint(xtalk_intr_t);
+int                     pcibr_intr_connect(pcibr_intr_t);
+void                    pcibr_intr_disconnect(pcibr_intr_t);
+
+devfs_handle_t            pcibr_intr_cpu_get(pcibr_intr_t);
+void                    pcibr_xintr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
+void                    pcibr_intr_func(intr_arg_t);
+
+extern pcibr_info_t      pcibr_info_get(devfs_handle_t);
+
+/* =====================================================================
+ *    INTERRUPT MANAGEMENT
+ */
+
+unsigned
+pcibr_intr_bits(pciio_info_t info,
+		pciio_intr_line_t lines)
+{
+    pciio_slot_t            slot = pciio_info_slot_get(info);
+    unsigned		    bbits = 0;
+
+    /*
+     * Currently favored mapping from PCI
+     * slot number and INTA/B/C/D to Bridge
+     * PCI Interrupt Bit Number:
+     *
+     *     SLOT     A B C D
+     *      0       0 4 0 4
+     *      1       1 5 1 5
+     *      2       2 6 2 6
+     *      3       3 7 3 7
+     *      4       4 0 4 0
+     *      5       5 1 5 1
+     *      6       6 2 6 2
+     *      7       7 3 7 3
+     */
+
+    if (slot < 8) {
+	if (lines & (PCIIO_INTR_LINE_A| PCIIO_INTR_LINE_C))
+	    bbits |= 1 << slot;
+	if (lines & (PCIIO_INTR_LINE_B| PCIIO_INTR_LINE_D))
+	    bbits |= 1 << (slot ^ 4);
+    }
+    return bbits;
+}
+
+
+/*
+ *	Get the next wrapper pointer queued in the interrupt circular buffer.
+ */
+pcibr_intr_wrap_t
+pcibr_wrap_get(pcibr_intr_cbuf_t cbuf)
+{
+    pcibr_intr_wrap_t	wrap;
+
+	if (cbuf->ib_in == cbuf->ib_out)
+	    PRINT_PANIC( "pcibr intr circular buffer empty, cbuf=0x%p, ib_in=ib_out=%d\n",
+		(void *)cbuf, cbuf->ib_out);
+
+	wrap = cbuf->ib_cbuf[cbuf->ib_out++];
+	cbuf->ib_out = cbuf->ib_out % IBUFSIZE;
+	return(wrap);
+}
+
+/* 
+ *	Queue a wrapper pointer in the interrupt circular buffer.
+ */
+void
+pcibr_wrap_put(pcibr_intr_wrap_t wrap, pcibr_intr_cbuf_t cbuf)
+{
+	int	in;
+	int	s;
+
+	/*
+	 * Multiple CPUs could be executing this code simultaneously
+	 * if a handler has registered multiple interrupt lines and
+	 * the interrupts are directed to different CPUs.
+	 */
+	s = mutex_spinlock(&cbuf->ib_lock);
+	in = (cbuf->ib_in + 1) % IBUFSIZE;
+	if (in == cbuf->ib_out) 
+	    PRINT_PANIC( "pcibr intr circular buffer full, cbuf=0x%p, ib_in=%d\n",
+		(void *)cbuf, cbuf->ib_in);
+
+	cbuf->ib_cbuf[cbuf->ib_in] = wrap;
+	cbuf->ib_in = in;
+	mutex_spinunlock(&cbuf->ib_lock, s);
+	return;
+}
+
+/*
+ *	There are end cases where a deadlock can occur if interrupt 
+ *	processing completes and the Bridge b_int_status bit is still set.
+ *
+ *	One scenerio is if a second PCI interrupt occurs within 60ns of
+ *	the previous interrupt being cleared. In this case the Bridge
+ *	does not detect the transition, the Bridge b_int_status bit
+ *	remains set, and because no transition was detected no interrupt
+ *	packet is sent to the Hub/Heart.
+ *
+ *	A second scenerio is possible when a b_int_status bit is being
+ *	shared by multiple devices:
+ *						Device #1 generates interrupt
+ *						Bridge b_int_status bit set
+ *						Device #2 generates interrupt
+ *		interrupt processing begins
+ *		  ISR for device #1 runs and
+ *			clears interrupt
+ *						Device #1 generates interrupt
+ *		  ISR for device #2 runs and
+ *			clears interrupt
+ *						(b_int_status bit still set)
+ *		interrupt processing completes
+ *		  
+ *	Interrupt processing is now complete, but an interrupt is still
+ *	outstanding for Device #1. But because there was no transition of
+ *	the b_int_status bit, no interrupt packet will be generated and
+ *	a deadlock will occur.
+ *
+ *	To avoid these deadlock situations, this function is used
+ *	to check if a specific Bridge b_int_status bit is set, and if so,
+ *	cause the setting of the corresponding interrupt bit.
+ *
+ *	On a XBridge (IP35), we do this by writing the appropriate Bridge Force 
+ *	Interrupt register.
+ */
+void
+pcibr_force_interrupt(pcibr_intr_wrap_t wrap)
+{
+	unsigned	bit;
+	pcibr_soft_t    pcibr_soft = wrap->iw_soft;
+	bridge_t       *bridge = pcibr_soft->bs_base;
+	cpuid_t cpuvertex_to_cpuid(devfs_handle_t vhdl);
+
+	bit = wrap->iw_intr;
+
+	if (pcibr_soft->bs_xbridge) {
+	    bridge->b_force_pin[bit].intr = 1;
+	} else if ((1 << bit) & *wrap->iw_stat) {
+	    cpuid_t	    cpu;
+	    unsigned        intr_bit;
+	    xtalk_intr_t    xtalk_intr =
+				pcibr_soft->bs_intr[bit].bsi_xtalk_intr;
+
+	    intr_bit = (short) xtalk_intr_vector_get(xtalk_intr);
+	    cpu = cpuvertex_to_cpuid(xtalk_intr_cpu_get(xtalk_intr));
+#if defined(CONFIG_IA64_SGI_SN1)
+	    REMOTE_CPU_SEND_INTR(cpu, intr_bit);
+#endif
+	}
+}
+
+/*ARGSUSED */
+pcibr_intr_t
+pcibr_intr_alloc(devfs_handle_t pconn_vhdl,
+		 device_desc_t dev_desc,
+		 pciio_intr_line_t lines,
+		 devfs_handle_t owner_dev)
+{
+    pcibr_info_t            pcibr_info = pcibr_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pcibr_info->f_slot;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pcibr_info->f_mfast;
+    devfs_handle_t            xconn_vhdl = pcibr_soft->bs_conn;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     is_threaded = 0;
+    int                     thread_swlevel;
+
+    xtalk_intr_t           *xtalk_intr_p;
+    pcibr_intr_t           *pcibr_intr_p;
+    pcibr_intr_list_t      *intr_list_p;
+
+    unsigned                pcibr_int_bits;
+    unsigned                pcibr_int_bit;
+    xtalk_intr_t            xtalk_intr = (xtalk_intr_t)0;
+    hub_intr_t		    hub_intr;
+    pcibr_intr_t            pcibr_intr;
+    pcibr_intr_list_t       intr_entry;
+    pcibr_intr_list_t       intr_list;
+    bridgereg_t             int_dev;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_alloc\n"
+	    "%v:%s%s%s%s%s\n",
+	    owner_dev, pconn_vhdl,
+	    !(lines & 15) ? " No INTs?" : "",
+	    lines & 1 ? " INTA" : "",
+	    lines & 2 ? " INTB" : "",
+	    lines & 4 ? " INTC" : "",
+	    lines & 8 ? " INTD" : "");
+#endif
+
+    NEW(pcibr_intr);
+    if (!pcibr_intr)
+	return NULL;
+
+    if (dev_desc) {
+	cpuid_t intr_target_from_desc(device_desc_t, int);
+    } else {
+	extern int default_intr_pri;
+
+	is_threaded = 1; /* PCI interrupts are threaded, by default */
+	thread_swlevel = default_intr_pri;
+    }
+
+    pcibr_intr->bi_dev = pconn_vhdl;
+    pcibr_intr->bi_lines = lines;
+    pcibr_intr->bi_soft = pcibr_soft;
+    pcibr_intr->bi_ibits = 0;		/* bits will be added below */
+    pcibr_intr->bi_flags = is_threaded ? 0 : PCIIO_INTR_NOTHREAD;
+    pcibr_intr->bi_mustruncpu = CPU_NONE;
+    pcibr_intr->bi_ibuf.ib_in = 0;
+    pcibr_intr->bi_ibuf.ib_out = 0;
+    mutex_spinlock_init(&pcibr_intr->bi_ibuf.ib_lock);
+
+    pcibr_int_bits = pcibr_soft->bs_intr_bits((pciio_info_t)pcibr_info, lines);
+
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+#if DEBUG && INTR_DEBUG
+    printk("pcibr_int_bits: 0x%X\n", pcibr_int_bits);
+#endif 
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit ++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_p = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    xtalk_intr = *xtalk_intr_p;
+
+	    if (xtalk_intr == NULL) {
+		/*
+		 * This xtalk_intr_alloc is constrained for two reasons:
+		 * 1) Normal interrupts and error interrupts need to be delivered
+		 *    through a single xtalk target widget so that there aren't any
+		 *    ordering problems with DMA, completion interrupts, and error
+		 *    interrupts. (Use of xconn_vhdl forces this.)
+		 *
+		 * 2) On IP35, addressing constraints on IP35 and Bridge force
+		 *    us to use a single PI number for all interrupts from a
+		 *    single Bridge. (IP35-specific code forces this, and we
+		 *    verify in pcibr_setwidint.)
+		 */
+
+		/*
+		 * All code dealing with threaded PCI interrupt handlers
+		 * is located at the pcibr level. Because of this,
+		 * we always want the lower layers (hub/heart_intr_alloc, 
+		 * intr_level_connect) to treat us as non-threaded so we
+		 * don't set up a duplicate threaded environment. We make
+		 * this happen by calling a special xtalk interface.
+		 */
+		xtalk_intr = xtalk_intr_alloc_nothd(xconn_vhdl, dev_desc, 
+			owner_dev);
+#if DEBUG && INTR_DEBUG
+		printk("%v: xtalk_intr=0x%X\n", xconn_vhdl, xtalk_intr);
+#endif
+
+		/* both an assert and a runtime check on this:
+		 * we need to check in non-DEBUG kernels, and
+		 * the ASSERT gets us more information when
+		 * we use DEBUG kernels.
+		 */
+		ASSERT(xtalk_intr != NULL);
+		if (xtalk_intr == NULL) {
+		    /* it is quite possible that our
+		     * xtalk_intr_alloc failed because
+		     * someone else got there first,
+		     * and we can find their results
+		     * in xtalk_intr_p.
+		     */
+		    if (!*xtalk_intr_p) {
+#ifdef SUPPORT_PRINTING_V_FORMAT
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to get xtalk interrupt resources",
+				xconn_vhdl);
+#else
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc 0x%p: unable to get xtalk interrupt resources",
+				(void *)xconn_vhdl);
+#endif
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+		} else if (compare_and_swap_ptr((void **) xtalk_intr_p, NULL, xtalk_intr)) {
+		    /*
+		     * now tell the bridge which slot is
+		     * using this interrupt line.
+		     */
+		    int_dev = bridge->b_int_device;
+		    int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		    int_dev |= pciio_slot << BRIDGE_INT_DEV_SHFT(pcibr_int_bit);
+		    bridge->b_int_device = int_dev;	/* XXXMP */
+
+#if DEBUG && INTR_DEBUG
+		    printk("%v: bridge intr bit %d clears my wrb\n",
+			    pconn_vhdl, pcibr_int_bit);
+#endif
+		} else {
+		    /* someone else got one allocated first;
+		     * free the one we just created, and
+		     * retrieve the one they allocated.
+		     */
+		    xtalk_intr_free(xtalk_intr);
+		    xtalk_intr = *xtalk_intr_p;
+#if PARANOID
+		    /* once xtalk_intr is set, we never clear it,
+		     * so if the CAS fails above, this condition
+		     * can "never happen" ...
+		     */
+		    if (!xtalk_intr) {
+			printk(KERN_ALERT  
+				"pcibr_intr_alloc %v: unable to set xtalk interrupt resources",
+				xconn_vhdl);
+			/* yes, we leak resources here. */
+			return 0;
+		    }
+#endif
+		}
+	    }
+
+	    pcibr_intr->bi_ibits |= 1 << pcibr_int_bit;
+
+	    NEW(intr_entry);
+	    intr_entry->il_next = NULL;
+	    intr_entry->il_intr = pcibr_intr;
+	    intr_entry->il_wrbf = &(bridge->b_wr_req_buf[pciio_slot].reg);
+	    intr_list_p = 
+		&pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+#if DEBUG && INTR_DEBUG
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+	    printk("0x%x: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#else
+	    printk("%v: Bridge bit %d wrap=0x%x\n",
+		pconn_vhdl, pcibr_int_bit,
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap);
+#endif
+#endif
+
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the first interrupt on this bridge bit.
+		 */
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) allocated [FIRST]\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list = *intr_list_p;
+	    pcibr_intr_p = &intr_list->il_intr;
+	    if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		/* first entry on list was erased,
+		 * and we replaced it, so we
+		 * don't need our intr_entry.
+		 */
+		DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) replaces erased first\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    intr_list_p = &intr_list->il_next;
+	    if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		/* we are the new second interrupt on this bit.
+		 */
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared = 1;
+#if DEBUG && INTR_DEBUG
+		printk("%v INT 0x%x (bridge bit %d) is new SECOND\n",
+			pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		continue;
+	    }
+	    while (1) {
+		pcibr_intr_p = &intr_list->il_intr;
+		if (compare_and_swap_ptr((void **) pcibr_intr_p, NULL, pcibr_intr)) {
+		    /* an entry on list was erased,
+		     * and we replaced it, so we
+		     * don't need our intr_entry.
+		     */
+		    DEL(intr_entry);
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) replaces erased Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		intr_list_p = &intr_list->il_next;
+		if (compare_and_swap_ptr((void **) intr_list_p, NULL, intr_entry)) {
+		    /* entry appended to share list
+		     */
+#if DEBUG && INTR_DEBUG
+		    printk("%v INT 0x%x (bridge bit %d) is new Nth\n",
+			    pconn_vhdl, pcibr_int_bits, pcibr_int_bit);
+#endif
+		    break;
+		}
+		/* step to next record in chain
+		 */
+		intr_list = *intr_list_p;
+	    }
+	}
+    }
+
+#if DEBUG && INTR_DEBUG
+    printk("%v pcibr_intr_alloc complete\n", pconn_vhdl);
+#endif
+    hub_intr = (hub_intr_t)xtalk_intr;
+    pcibr_intr->bi_irq = hub_intr->i_bit;
+    pcibr_intr->bi_cpu = hub_intr->i_cpuid;
+    return pcibr_intr;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_free(pcibr_intr_t pcibr_intr)
+{
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bit;
+    pcibr_intr_list_t       intr_list;
+    int			    intr_shared;
+    xtalk_intr_t	    *xtalk_intrp;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++) {
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    for (intr_list = 
+		     pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_list;
+		 intr_list != NULL;
+		 intr_list = intr_list->il_next)
+		if (compare_and_swap_ptr((void **) &intr_list->il_intr, 
+					 pcibr_intr, 
+					 NULL)) {
+#if DEBUG && INTR_DEBUG
+		    printk("%s: cleared a handler from bit %d\n",
+			    pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+		}
+	    /* If this interrupt line is not being shared between multiple
+	     * devices release the xtalk interrupt resources.
+	     */
+	    intr_shared = 
+		pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared;
+	    xtalk_intrp = &pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    if ((!intr_shared) && (*xtalk_intrp)) {
+
+		bridge_t 	*bridge = pcibr_soft->bs_base;
+		bridgereg_t	int_dev;
+
+		xtalk_intr_free(*xtalk_intrp);
+		*xtalk_intrp = 0;
+
+		/* Clear the PCI device interrupt to bridge interrupt pin
+		 * mapping.
+		 */
+		int_dev = bridge->b_int_device;
+		int_dev &= ~BRIDGE_INT_DEV_MASK(pcibr_int_bit);
+		bridge->b_int_device = int_dev;
+
+	    }
+	}
+    }
+    DEL(pcibr_intr);
+}
+
+void
+pcibr_setpciint(xtalk_intr_t xtalk_intr)
+{
+    iopaddr_t               addr = xtalk_intr_addr_get(xtalk_intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(xtalk_intr);
+    bridgereg_t            *int_addr = (bridgereg_t *)
+    xtalk_intr_sfarg_get(xtalk_intr);
+
+    *int_addr = ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+		 (BRIDGE_INT_ADDR_FLD & vect));
+}
+
+/*ARGSUSED */
+int
+pcibr_intr_connect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    if (pcibr_intr == NULL)
+	return -1;
+
+#if DEBUG && INTR_DEBUG
+    printk("%v: pcibr_intr_connect\n",
+	    pcibr_intr->bi_dev);
+#endif
+
+    *((volatile unsigned *)&pcibr_intr->bi_flags) |= PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and make sure there are xtalk resources
+     * allocated for it.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    xtalk_intr_t            xtalk_intr;
+
+	    xtalk_intr = pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr;
+
+	    /*
+	     * If this interrupt line is being shared and the connect has
+	     * already been done, no need to do it again.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected)
+		continue;
+
+
+	    /*
+	     * Use the pcibr wrapper function to handle all Bridge interrupts
+	     * regardless of whether the interrupt line is shared or not.
+	     */
+	    xtalk_intr_connect(xtalk_intr, (xtalk_intr_setfunc_t) pcibr_setpciint,
+			       (void *)&(bridge->b_int_addr[pcibr_int_bit].addr));
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 1;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%v bridge bit %d wrapper connected\n",
+		    pcibr_intr->bi_dev, pcibr_int_bit);
+#endif
+	}
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable |= pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    return 0;
+}
+
+/*ARGSUSED */
+void
+pcibr_intr_disconnect(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+    bridgereg_t             b_int_enable;
+    unsigned long           s;
+
+    /* Stop calling the function. Now.
+     */
+    *((volatile unsigned *)&pcibr_intr->bi_flags) &= ~PCIIO_INTR_CONNECTED;
+
+    /*
+     * For each PCI interrupt line requested, figure
+     * out which Bridge PCI Interrupt Line it maps
+     * to, and disconnect the interrupt.
+     */
+
+    /* don't disable interrupts for lines that
+     * are shared between devices.
+     */
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if ((pcibr_int_bits & (1 << pcibr_int_bit)) &&
+	    (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared))
+	    pcibr_int_bits &= ~(1 << pcibr_int_bit);
+    if (!pcibr_int_bits)
+	return;
+
+    s = pcibr_lock(pcibr_soft);
+    b_int_enable = bridge->b_int_enable;
+    b_int_enable &= ~pcibr_int_bits;
+    bridge->b_int_enable = b_int_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+    pcibr_unlock(pcibr_soft, s);
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit)) {
+	    /* if the interrupt line is now shared,
+	     * do not disconnect it.
+	     */
+	    if (pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_disconnect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+	    pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_connected = 0;
+
+#if DEBUG && INTR_DEBUG
+	    printk("%s: xtalk disconnect done for Bridge bit %d\n",
+		pcibr_soft->bs_name, pcibr_int_bit);
+#endif
+
+	    /* if we are sharing the interrupt line,
+	     * connect us up; this closes the hole
+	     * where the another pcibr_intr_alloc()
+	     * was in progress as we disconnected.
+	     */
+	    if (!pcibr_soft->bs_intr[pcibr_int_bit].bsi_pcibr_intr_wrap.iw_shared)
+		continue;
+
+	    xtalk_intr_connect(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr,
+			       (xtalk_intr_setfunc_t)pcibr_setpciint,
+			       (void *) &(bridge->b_int_addr[pcibr_int_bit].addr));
+	}
+}
+
+/*ARGSUSED */
+devfs_handle_t
+pcibr_intr_cpu_get(pcibr_intr_t pcibr_intr)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_intr->bi_soft;
+    unsigned                pcibr_int_bits = pcibr_intr->bi_ibits;
+    unsigned                pcibr_int_bit;
+
+    for (pcibr_int_bit = 0; pcibr_int_bit < 8; pcibr_int_bit++)
+	if (pcibr_int_bits & (1 << pcibr_int_bit))
+	    return xtalk_intr_cpu_get(pcibr_soft->bs_intr[pcibr_int_bit].bsi_xtalk_intr);
+    return 0;
+}
+
+/* =====================================================================
+ *    INTERRUPT HANDLING
+ */
+void
+pcibr_clearwidint(bridge_t *bridge)
+{
+    bridge->b_wid_int_upper = 0;
+    bridge->b_wid_int_lower = 0;
+}
+
+
+void
+pcibr_setwidint(xtalk_intr_t intr)
+{
+    xwidgetnum_t            targ = xtalk_intr_target_get(intr);
+    iopaddr_t               addr = xtalk_intr_addr_get(intr);
+    xtalk_intr_vector_t     vect = xtalk_intr_vector_get(intr);
+    widgetreg_t		    NEW_b_wid_int_upper, NEW_b_wid_int_lower;
+    widgetreg_t		    OLD_b_wid_int_upper, OLD_b_wid_int_lower;
+
+    bridge_t               *bridge = (bridge_t *)xtalk_intr_sfarg_get(intr);
+
+    NEW_b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+			       XTALK_ADDR_TO_UPPER(addr));
+    NEW_b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+
+    OLD_b_wid_int_upper = bridge->b_wid_int_upper;
+    OLD_b_wid_int_lower = bridge->b_wid_int_lower;
+
+    /* Verify that all interrupts from this Bridge are using a single PI */
+    if ((OLD_b_wid_int_upper != 0) && (OLD_b_wid_int_lower != 0)) {
+	/*
+	 * Once set, these registers shouldn't change; they should
+	 * be set multiple times with the same values.
+	 *
+	 * If we're attempting to change these registers, it means
+	 * that our heuristics for allocating interrupts in a way
+	 * appropriate for IP35 have failed, and the admin needs to
+	 * explicitly direct some interrupts (or we need to make the
+	 * heuristics more clever).
+	 *
+	 * In practice, we hope this doesn't happen very often, if
+	 * at all.
+	 */
+	if ((OLD_b_wid_int_upper != NEW_b_wid_int_upper) ||
+	    (OLD_b_wid_int_lower != NEW_b_wid_int_lower)) {
+		printk(KERN_WARNING  "Interrupt allocation is too complex.\n");
+		printk(KERN_WARNING  "Use explicit administrative interrupt targetting.\n");
+		printk(KERN_WARNING  "bridge=0x%lx targ=0x%x\n", (unsigned long)bridge, targ);
+		printk(KERN_WARNING  "NEW=0x%x/0x%x  OLD=0x%x/0x%x\n",
+			NEW_b_wid_int_upper, NEW_b_wid_int_lower,
+			OLD_b_wid_int_upper, OLD_b_wid_int_lower);
+		PRINT_PANIC("PCI Bridge interrupt targetting error\n");
+	}
+    }
+
+    bridge->b_wid_int_upper = NEW_b_wid_int_upper;
+    bridge->b_wid_int_lower = NEW_b_wid_int_lower;
+    bridge->b_int_host_err = vect;
+}
+
+/*
+ * pcibr_intr_preset: called during mlreset time
+ * if the platform specific code needs to route
+ * one of the Bridge's xtalk interrupts before the
+ * xtalk infrastructure is available.
+ */
+void
+pcibr_xintr_preset(void *which_widget,
+		   int which_widget_intr,
+		   xwidgetnum_t targ,
+		   iopaddr_t addr,
+		   xtalk_intr_vector_t vect)
+{
+    bridge_t               *bridge = (bridge_t *) which_widget;
+
+    if (which_widget_intr == -1) {
+	/* bridge widget error interrupt */
+	bridge->b_wid_int_upper = ( (0x000F0000 & (targ << 16)) |
+				   XTALK_ADDR_TO_UPPER(addr));
+	bridge->b_wid_int_lower = XTALK_ADDR_TO_LOWER(addr);
+	bridge->b_int_host_err = vect;
+
+	/* turn on all interrupts except
+	 * the PCI interrupt requests,
+	 * at least at heart.
+	 */
+	bridge->b_int_enable |= ~BRIDGE_IMR_INT_MSK;
+
+    } else {
+	/* routing a PCI device interrupt.
+	 * targ and low 38 bits of addr must
+	 * be the same as the already set
+	 * value for the widget error interrupt.
+	 */
+	bridge->b_int_addr[which_widget_intr].addr =
+	    ((BRIDGE_INT_ADDR_HOST & (addr >> 30)) |
+	     (BRIDGE_INT_ADDR_FLD & vect));
+	/*
+	 * now bridge can let it through;
+	 * NB: still should be blocked at
+	 * xtalk provider end, until the service
+	 * function is set.
+	 */
+	bridge->b_int_enable |= 1 << vect;
+    }
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+}
+
+
+/*
+ * pcibr_intr_func()
+ *
+ * This is the pcibr interrupt "wrapper" function that is called,
+ * in interrupt context, to initiate the interrupt handler(s) registered
+ * (via pcibr_intr_alloc/connect) for the occuring interrupt. Non-threaded 
+ * handlers will be called directly, and threaded handlers will have their 
+ * thread woken up.
+ */
+void
+pcibr_intr_func(intr_arg_t arg)
+{
+    pcibr_intr_wrap_t       wrap = (pcibr_intr_wrap_t) arg;
+    reg_p                   wrbf;
+    pcibr_intr_t            intr;
+    pcibr_intr_list_t       list;
+    int                     clearit;
+    int			    do_nonthreaded = 1;
+    int			    is_threaded = 0;
+    int			    x = 0;
+
+	/*
+	 * If any handler is still running from a previous interrupt
+	 * just return. If there's a need to call the handler(s) again,
+	 * another interrupt will be generated either by the device or by
+	 * pcibr_force_interrupt().
+	 */
+
+	if (wrap->iw_hdlrcnt) {
+		return;
+	}
+
+    /*
+     * Call all interrupt handlers registered.
+     * First, the pcibr_intrd threads for any threaded handlers will be
+     * awoken, then any non-threaded handlers will be called sequentially.
+     */
+	
+	clearit = 1;
+	while (do_nonthreaded) {
+	    for (list = wrap->iw_list; list != NULL; list = list->il_next) {
+		if ((intr = list->il_intr) &&
+		    (intr->bi_flags & PCIIO_INTR_CONNECTED)) {
+
+		/*
+		 * This device may have initiated write
+		 * requests since the bridge last saw
+		 * an edge on this interrupt input; flushing
+		 * the buffer prior to invoking the handler
+		 * should help but may not be sufficient if we 
+		 * get more requests after the flush, followed
+		 * by the card deciding it wants service, before
+		 * the interrupt handler checks to see if things need
+		 * to be done.
+		 *
+		 * There is a similar race condition if
+		 * an interrupt handler loops around and
+		 * notices further service is required.
+		 * Perhaps we need to have an explicit
+		 * call that interrupt handlers need to
+		 * do between noticing that DMA to memory
+		 * has completed, but before observing the
+		 * contents of memory?
+		 */
+
+			if ((do_nonthreaded) && (!is_threaded)) {
+			/* Non-threaded. 
+			 * Call the interrupt handler at interrupt level
+			 */
+
+			/* Only need to flush write buffers if sharing */
+
+			if ((wrap->iw_shared) && (wrbf = list->il_wrbf)) {
+			    if ((x = *wrbf))	/* write request buffer flush */
+#ifdef SUPPORT_PRINTING_V_FORMAT
+				printk(KERN_ALERT  "pcibr_intr_func %v: \n"
+				    "write buffer flush failed, wrbf=0x%x\n", 
+				    list->il_intr->bi_dev, wrbf);
+#else
+				printk(KERN_ALERT  "pcibr_intr_func %p: \n"
+				    "write buffer flush failed, wrbf=0x%lx\n", 
+				    (void *)list->il_intr->bi_dev, (long) wrbf);
+#endif
+			}
+		    }
+
+		    clearit = 0;
+		}
+	    }
+
+		do_nonthreaded = 0;
+		/*
+		 * If the non-threaded handler was the last to complete,
+		 * (i.e., no threaded handlers still running) force an
+		 * interrupt to avoid a potential deadlock situation.
+		 */
+		if (wrap->iw_hdlrcnt == 0) {
+			pcibr_force_interrupt(wrap);
+		}
+	}
+
+	/* If there were no handlers,
+	 * disable the interrupt and return.
+	 * It will get enabled again after
+	 * a handler is connected.
+	 * If we don't do this, we would
+	 * sit here and spin through the
+	 * list forever.
+	 */
+	if (clearit) {
+	    pcibr_soft_t            pcibr_soft = wrap->iw_soft;
+	    bridge_t               *bridge = pcibr_soft->bs_base;
+	    bridgereg_t             b_int_enable;
+	    bridgereg_t		    mask = 1 << wrap->iw_intr;
+	    unsigned long           s;
+
+	    s = pcibr_lock(pcibr_soft);
+	    b_int_enable = bridge->b_int_enable;
+	    b_int_enable &= ~mask;
+	    bridge->b_int_enable = b_int_enable;
+	    bridge->b_wid_tflush;	/* wait until Bridge PIO complete */
+	    pcibr_unlock(pcibr_soft, s);
+	    return;
+	}
+}
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_rrb.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,896 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+void              do_pcibr_rrb_clear(bridge_t *, int);
+void              do_pcibr_rrb_flush(bridge_t *, int);
+int               do_pcibr_rrb_count_valid(bridge_t *, pciio_slot_t);
+int               do_pcibr_rrb_count_avail(bridge_t *, pciio_slot_t);
+int               do_pcibr_rrb_alloc(bridge_t *, pciio_slot_t, int);
+int               do_pcibr_rrb_free(bridge_t *, pciio_slot_t, int);
+
+void              do_pcibr_rrb_autoalloc(pcibr_soft_t, int, int);
+
+int		  pcibr_wrb_flush(devfs_handle_t);
+int               pcibr_rrb_alloc(devfs_handle_t, int *, int *);
+int               pcibr_rrb_check(devfs_handle_t, int *, int *, int *, int *);
+int               pcibr_alloc_all_rrbs(devfs_handle_t, int, int, int, int, int, int, int, int, int);
+void              pcibr_rrb_flush(devfs_handle_t);
+int		  pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+
+/* 
+ *    RRB Management
+ */
+
+#define LSBIT(word)		((word) &~ ((word)-1))
+
+void
+do_pcibr_rrb_clear(bridge_t *bridge, int rrb)
+{
+    bridgereg_t             status;
+
+    /* bridge_lock must be held;
+     * this RRB must be disabled.
+     */
+
+    /* wait until RRB has no outstanduing XIO packets. */
+    while ((status = bridge->b_resp_status) & BRIDGE_RRB_INUSE(rrb)) {
+	;				/* XXX- beats on bridge. bad idea? */
+    }
+
+    /* if the RRB has data, drain it. */
+    if (status & BRIDGE_RRB_VALID(rrb)) {
+	bridge->b_resp_clear = BRIDGE_RRB_CLEAR(rrb);
+
+	/* wait until RRB is no longer valid. */
+	while ((status = bridge->b_resp_status) & BRIDGE_RRB_VALID(rrb)) {
+	    ;				/* XXX- beats on bridge. bad idea? */
+	}
+    }
+}
+
+void
+do_pcibr_rrb_flush(bridge_t *bridge, int rrbn)
+{
+    reg_p                   rrbp = &bridge->b_rrb_map[rrbn & 1].reg;
+    bridgereg_t             rrbv;
+    int                     shft = 4 * (rrbn >> 1);
+    unsigned                ebit = BRIDGE_RRB_EN << shft;
+
+    rrbv = *rrbp;
+    if (rrbv & ebit)
+	*rrbp = rrbv & ~ebit;
+
+    do_pcibr_rrb_clear(bridge, rrbn);
+
+    if (rrbv & ebit)
+	*rrbp = rrbv;
+}
+
+/*
+ *    pcibr_rrb_count_valid: count how many RRBs are
+ *      marked valid for the specified PCI slot on this
+ *      bridge.
+ *
+ *      NOTE: The "slot" parameter for all pcibr_rrb
+ *      management routines must include the "virtual"
+ *      bit; when manageing both the normal and the
+ *      virtual channel, separate calls to these
+ *      routines must be made. To denote the virtual
+ *      channel, add PCIBR_RRB_SLOT_VIRTUAL to the slot
+ *      number.
+ *
+ *      IMPL NOTE: The obvious algorithm is to iterate
+ *      through the RRB fields, incrementing a count if
+ *      the RRB is valid and matches the slot. However,
+ *      it is much simpler to use an algorithm derived
+ *      from the "partitioned add" idea. First, XOR in a
+ *      pattern such that the fields that match this
+ *      slot come up "all ones" and all other fields
+ *      have zeros in the mismatching bits. Then AND
+ *      together the bits in the field, so we end up
+ *      with one bit turned on for each field that
+ *      matched. Now we need to count these bits. This
+ *      can be done either with a series of shift/add
+ *      instructions or by using "tmp % 15"; I expect
+ *      that the cascaded shift/add will be faster.
+ */
+
+int
+do_pcibr_rrb_count_valid(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp ^= 0x11111111 * (7 - slot / 2);
+    tmp &= (0xCCCCCCCC & tmp) >> 2;
+    tmp &= (0x22222222 & tmp) >> 1;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_count_avail: count how many RRBs are
+ *      available to be allocated for the specified slot.
+ *
+ *      IMPL NOTE: similar to the above, except we are
+ *      just counting how many fields have the valid bit
+ *      turned off.
+ */
+int
+do_pcibr_rrb_count_avail(bridge_t *bridge,
+			 pciio_slot_t slot)
+{
+    bridgereg_t             tmp;
+
+    tmp = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~tmp) >> 3;
+    tmp += tmp >> 4;
+    tmp += tmp >> 8;
+    tmp += tmp >> 16;
+    return tmp & 15;
+}
+
+/*
+ *    do_pcibr_rrb_alloc: allocate some additional RRBs
+ *      for the specified slot. Returns -1 if there were
+ *      insufficient free RRBs to satisfy the request,
+ *      or 0 if the request was fulfilled.
+ *
+ *      Note that if a request can be partially filled,
+ *      it will be, even if we return failure.
+ *
+ *      IMPL NOTE: again we avoid iterating across all
+ *      the RRBs; instead, we form up a word containing
+ *      one bit for each free RRB, then peel the bits
+ *      off from the low end.
+ */
+int
+do_pcibr_rrb_alloc(bridge_t *bridge,
+		   pciio_slot_t slot,
+		   int more)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, bit;
+
+    reg = bridge->b_rrb_map[slot & 1].reg;
+    tmp = (0x88888888 & ~reg) >> 3;
+    while (more-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg = ((reg & ~(bit * 15)) | (bit * (8 + slot / 2)));
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+    return rv;
+}
+
+/*
+ *    do_pcibr_rrb_free: release some of the RRBs that
+ *      have been allocated for the specified
+ *      slot. Returns zero for success, or negative if
+ *      it was unable to free that many RRBs.
+ *
+ *      IMPL NOTE: We form up a bit for each RRB
+ *      allocated to the slot, aligned with the VALID
+ *      bitfield this time; then we peel bits off one at
+ *      a time, releasing the corresponding RRB.
+ */
+int
+do_pcibr_rrb_free(bridge_t *bridge,
+		  pciio_slot_t slot,
+		  int less)
+{
+    int                     rv = 0;
+    bridgereg_t             reg, tmp, clr, bit;
+    int                     i;
+
+    clr = 0;
+    reg = bridge->b_rrb_map[slot & 1].reg;
+
+    /* This needs to be done otherwise the rrb's on the virtual channel
+     * for this slot won't be freed !!
+     */
+    tmp = reg & 0xbbbbbbbb;
+
+    tmp ^= (0x11111111 * (7 - slot / 2));
+    tmp &= (0x33333333 & tmp) << 2;
+    tmp &= (0x44444444 & tmp) << 1;
+    while (less-- > 0) {
+	bit = LSBIT(tmp);
+	if (!bit) {
+	    rv = -1;
+	    break;
+	}
+	tmp &= ~bit;
+	reg &= ~bit;
+	clr |= bit;
+    }
+    bridge->b_rrb_map[slot & 1].reg = reg;
+
+    for (i = 0; i < 8; i++)
+	if (clr & (8 << (4 * i)))
+	    do_pcibr_rrb_clear(bridge, (2 * i) + (slot & 1));
+
+    return rv;
+}
+
+void
+do_pcibr_rrb_autoalloc(pcibr_soft_t pcibr_soft,
+		       int slot,
+		       int more_rrbs)
+{
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     got;
+
+    for (got = 0; got < more_rrbs; ++got) {
+	if (pcibr_soft->bs_rrb_res[slot & 7] > 0)
+	    pcibr_soft->bs_rrb_res[slot & 7]--;
+	else if (pcibr_soft->bs_rrb_avail[slot & 1] > 0)
+	    pcibr_soft->bs_rrb_avail[slot & 1]--;
+	else
+	    break;
+	if (do_pcibr_rrb_alloc(bridge, slot, 1) < 0)
+	    break;
+#if PCIBR_RRB_DEBUG
+	printk("do_pcibr_rrb_autoalloc: add one to slot %d%s\n",
+		slot & 7, slot & 8 ? "v" : "");
+#endif
+	pcibr_soft->bs_rrb_valid[slot]++;
+    }
+#if PCIBR_RRB_DEBUG
+    printk("%s: %d+%d free RRBs. Allocation list:\n", pcibr_soft->bs_name,
+	    pcibr_soft->bs_rrb_avail[0],
+	    pcibr_soft->bs_rrb_avail[1]);
+    for (slot = 0; slot < 8; ++slot)
+	printk("\t%d+%d+%d",
+		0xFFF & pcibr_soft->bs_rrb_valid[slot],
+		0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+		pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+}
+
+/*
+ * Device driver interface to flush the write buffers for a specified
+ * device hanging off the bridge.
+ */
+int
+pcibr_wrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    volatile bridgereg_t   *wrb_flush;
+
+    wrb_flush = &(bridge->b_wr_req_buf[pciio_slot].reg);
+    while (*wrb_flush);
+
+    return(0);
+}
+
+/*
+ * Device driver interface to request RRBs for a specified device
+ * hanging off a Bridge.  The driver requests the total number of
+ * RRBs it would like for the normal channel (vchan0) and for the
+ * "virtual channel" (vchan1).  The actual number allocated to each
+ * channel is returned.
+ *
+ * If we cannot allocate at least one RRB to a channel that needs
+ * at least one, return -1 (failure).  Otherwise, satisfy the request
+ * as best we can and return 0.
+ */
+int
+pcibr_rrb_alloc(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    int                     desired_vchan0;
+    int                     desired_vchan1;
+    int                     orig_vchan0;
+    int                     orig_vchan1;
+    int                     delta_vchan0;
+    int                     delta_vchan1;
+    int                     final_vchan0;
+    int                     final_vchan1;
+    int                     avail_rrbs;
+    int                     res_rrbs;
+    unsigned long           s;
+    int                     error;
+
+    /*
+     * TBD: temper request with admin info about RRB allocation,
+     * and according to demand from other devices on this Bridge.
+     *
+     * One way of doing this would be to allocate two RRBs
+     * for each device on the bus, before any drivers start
+     * asking for extras. This has the weakness that one
+     * driver might not give back an "extra" RRB until after
+     * another driver has already failed to get one that
+     * it wanted.
+     */
+
+    s = pcibr_lock(pcibr_soft);
+
+    /* Save the boot-time RRB configuration for this slot */
+    if (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] < 0) {
+        pcibr_soft->bs_rrb_valid_dflt[pciio_slot] =
+                pcibr_soft->bs_rrb_valid[pciio_slot]; 
+        pcibr_soft->bs_rrb_valid_dflt[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] =
+                pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+        pcibr_soft->bs_rrb_res_dflt[pciio_slot] =
+                pcibr_soft->bs_rrb_res[pciio_slot];
+                  
+    }
+
+    /* How many RRBs do we own? */
+    orig_vchan0 = pcibr_soft->bs_rrb_valid[pciio_slot];
+    orig_vchan1 = pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+    /* How many RRBs do we want? */
+    desired_vchan0 = count_vchan0 ? *count_vchan0 : orig_vchan0;
+    desired_vchan1 = count_vchan1 ? *count_vchan1 : orig_vchan1;
+
+    /* How many RRBs are free? */
+    avail_rrbs = pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	+ pcibr_soft->bs_rrb_res[pciio_slot];
+
+    /* Figure desired deltas */
+    delta_vchan0 = desired_vchan0 - orig_vchan0;
+    delta_vchan1 = desired_vchan1 - orig_vchan1;
+
+    /* Trim back deltas to something
+     * that we can actually meet, by
+     * decreasing the ending allocation
+     * for whichever channel wants
+     * more RRBs. If both want the same
+     * number, cut the second channel.
+     * NOTE: do not change the allocation for
+     * a channel that was passed as NULL.
+     */
+    while ((delta_vchan0 + delta_vchan1) > avail_rrbs) {
+	if (count_vchan0 &&
+	    (!count_vchan1 ||
+	     ((orig_vchan0 + delta_vchan0) >
+	      (orig_vchan1 + delta_vchan1))))
+	    delta_vchan0--;
+	else
+	    delta_vchan1--;
+    }
+
+    /* Figure final RRB allocations
+     */
+    final_vchan0 = orig_vchan0 + delta_vchan0;
+    final_vchan1 = orig_vchan1 + delta_vchan1;
+
+    /* If either channel wants RRBs but our actions
+     * would leave it with none, declare an error,
+     * but DO NOT change any RRB allocations.
+     */
+    if ((desired_vchan0 && !final_vchan0) ||
+	(desired_vchan1 && !final_vchan1)) {
+
+	error = -1;
+
+    } else {
+
+	/* Commit the allocations: free, then alloc.
+	 */
+	if (delta_vchan0 < 0)
+	    (void) do_pcibr_rrb_free(bridge, pciio_slot, -delta_vchan0);
+	if (delta_vchan1 < 0)
+	    (void) do_pcibr_rrb_free(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, -delta_vchan1);
+
+	if (delta_vchan0 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, pciio_slot, delta_vchan0);
+	if (delta_vchan1 > 0)
+	    (void) do_pcibr_rrb_alloc(bridge, PCIBR_RRB_SLOT_VIRTUAL + pciio_slot, delta_vchan1);
+
+	/* Return final values to caller.
+	 */
+	if (count_vchan0)
+	    *count_vchan0 = final_vchan0;
+	if (count_vchan1)
+	    *count_vchan1 = final_vchan1;
+
+	/* prevent automatic changes to this slot's RRBs
+	 */
+	pcibr_soft->bs_rrb_fixed |= 1 << pciio_slot;
+
+	/* Track the actual allocations, release
+	 * any further reservations, and update the
+	 * number of available RRBs.
+	 */
+
+	pcibr_soft->bs_rrb_valid[pciio_slot] = final_vchan0;
+	pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL] = final_vchan1;
+	pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+	    pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+	    + pcibr_soft->bs_rrb_res[pciio_slot]
+	    - delta_vchan0
+	    - delta_vchan1;
+	pcibr_soft->bs_rrb_res[pciio_slot] = 0;
+
+        /*
+         * Reserve enough RRBs so this slot's RRB configuration can be
+         * reset to its boot-time default following a hot-plug shut-down
+         */
+        res_rrbs =   (pcibr_soft->bs_rrb_valid_dflt[pciio_slot] -
+                      pcibr_soft->bs_rrb_valid[pciio_slot]) 
+                   + (pcibr_soft->bs_rrb_valid_dflt[pciio_slot +
+                                                    PCIBR_RRB_SLOT_VIRTUAL] -
+                      pcibr_soft->bs_rrb_valid[pciio_slot +
+                                               PCIBR_RRB_SLOT_VIRTUAL])
+                   + (pcibr_soft->bs_rrb_res_dflt[pciio_slot] -
+                      pcibr_soft->bs_rrb_res[pciio_slot]);
+
+         if (res_rrbs > 0) {
+             pcibr_soft->bs_rrb_res[pciio_slot] = res_rrbs;
+             pcibr_soft->bs_rrb_avail[pciio_slot & 1] =
+                 pcibr_soft->bs_rrb_avail[pciio_slot & 1]
+                 - res_rrbs;
+         }
+ 
+#if PCIBR_RRB_DEBUG
+	printk("pcibr_rrb_alloc: slot %d set to %d+%d; %d+%d free\n",
+		pciio_slot, final_vchan0, final_vchan1,
+		pcibr_soft->bs_rrb_avail[0],
+		pcibr_soft->bs_rrb_avail[1]);
+	for (pciio_slot = 0; pciio_slot < 8; ++pciio_slot)
+	    printk("\t%d+%d+%d",
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot],
+		    0xFFF & pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL],
+		    pcibr_soft->bs_rrb_res[pciio_slot]);
+	printk("\n");
+#endif
+
+	error = 0;
+    }
+
+    pcibr_unlock(pcibr_soft, s);
+
+    return error;
+}
+
+/*
+ * Device driver interface to check the current state
+ * of the RRB allocations.
+ *
+ *   pconn_vhdl is your PCI connection point (specifies which
+ *      PCI bus and which slot).
+ *
+ *   count_vchan0 points to where to return the number of RRBs
+ *      assigned to the primary DMA channel, used by all DMA
+ *      that does not explicitly ask for the alternate virtual
+ *      channel.
+ *
+ *   count_vchan1 points to where to return the number of RRBs
+ *      assigned to the secondary DMA channel, used when
+ *      PCIBR_VCHAN1 and PCIIO_DMA_A64 are specified.
+ *
+ *   count_reserved points to where to return the number of RRBs
+ *      that have been automatically reserved for your device at
+ *      startup, but which have not been assigned to a
+ *      channel. RRBs must be assigned to a channel to be used;
+ *      this can be done either with an explicit pcibr_rrb_alloc
+ *      call, or automatically by the infrastructure when a DMA
+ *      translation is constructed. Any call to pcibr_rrb_alloc
+ *      will release any unassigned reserved RRBs back to the
+ *      free pool.
+ *
+ *   count_pool points to where to return the number of RRBs
+ *      that are currently unassigned and unreserved. This
+ *      number can (and will) change as other drivers make calls
+ *      to pcibr_rrb_alloc, or automatically allocate RRBs for
+ *      DMA beyond their initial reservation.
+ *
+ * NULL may be passed for any of the return value pointers
+ * the caller is not interested in.
+ *
+ * The return value is "0" if all went well, or "-1" if
+ * there is a problem. Additionally, if the wrong vertex
+ * is passed in, one of the subsidiary support functions
+ * could panic with a "bad pciio fingerprint."
+ */
+
+int
+pcibr_rrb_check(devfs_handle_t pconn_vhdl,
+		int *count_vchan0,
+		int *count_vchan1,
+		int *count_reserved,
+		int *count_pool)
+{
+    pciio_info_t            pciio_info;
+    pciio_slot_t            pciio_slot;
+    pcibr_soft_t            pcibr_soft;
+    unsigned long           s;
+    int                     error = -1;
+
+    if ((pciio_info = pciio_info_get(pconn_vhdl)) &&
+	(pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info)) &&
+	((pciio_slot = pciio_info_slot_get(pciio_info)) < 8)) {
+
+	s = pcibr_lock(pcibr_soft);
+
+	if (count_vchan0)
+	    *count_vchan0 =
+		pcibr_soft->bs_rrb_valid[pciio_slot];
+
+	if (count_vchan1)
+	    *count_vchan1 =
+		pcibr_soft->bs_rrb_valid[pciio_slot + PCIBR_RRB_SLOT_VIRTUAL];
+
+	if (count_reserved)
+	    *count_reserved =
+		pcibr_soft->bs_rrb_res[pciio_slot];
+
+	if (count_pool)
+	    *count_pool =
+		pcibr_soft->bs_rrb_avail[pciio_slot & 1];
+
+	error = 0;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return error;
+}
+
+/* pcibr_alloc_all_rrbs allocates all the rrbs available in the quantities
+ * requested for each of the devices.  The evn_odd argument indicates whether
+ * allocation is for the odd or even rrbs. The next group of four argument
+ * pairs indicate the amount of rrbs to be assigned to each device. The first
+ * argument of each pair indicate the total number of rrbs to allocate for that
+ * device. The second argument of each pair indicates how many rrb's from the
+ * first argument should be assigned to the virtual channel. The total of all
+ * of the first arguments should be <= 8. The second argument should be <= the
+ * first argument.
+ * if even_odd = 0 the devices in order are 0, 2, 4, 6 
+ * if even_odd = 1 the devices in order are 1, 3, 5, 7
+ * returns 0 if no errors else returns -1
+ */
+
+int
+pcibr_alloc_all_rrbs(devfs_handle_t vhdl, int even_odd,
+		     int dev_1_rrbs, int virt1, int dev_2_rrbs, int virt2,
+		     int dev_3_rrbs, int virt3, int dev_4_rrbs, int virt4)
+{
+    devfs_handle_t          pcibr_vhdl;
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t)0;
+    bridge_t               *bridge = NULL;
+
+    uint32_t                rrb_setting = 0;
+    int                     rrb_shift = 7;
+    uint32_t                cur_rrb;
+    int                     dev_rrbs[4];
+    int                     virt[4];
+    int                     i, j;
+    unsigned long           s;
+
+    if (GRAPH_SUCCESS ==
+	hwgraph_traverse(vhdl, EDGE_LBL_PCI, &pcibr_vhdl)) {
+	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+	if (pcibr_soft)
+	    bridge = pcibr_soft->bs_base;
+	hwgraph_vertex_unref(pcibr_vhdl);
+    }
+    if (bridge == NULL)
+	bridge = (bridge_t *) xtalk_piotrans_addr
+	    (vhdl, NULL, 0, sizeof(bridge_t), 0);
+
+    even_odd &= 1;
+
+    dev_rrbs[0] = dev_1_rrbs;
+    dev_rrbs[1] = dev_2_rrbs;
+    dev_rrbs[2] = dev_3_rrbs;
+    dev_rrbs[3] = dev_4_rrbs;
+
+    virt[0] = virt1;
+    virt[1] = virt2;
+    virt[2] = virt3;
+    virt[3] = virt4;
+
+    if ((dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs) > 8) {
+	return -1;
+    }
+    if ((dev_1_rrbs < 0) || (dev_2_rrbs < 0) || (dev_3_rrbs < 0) || (dev_4_rrbs < 0)) {
+	return -1;
+    }
+    /* walk through rrbs */
+    for (i = 0; i < 4; i++) {
+	if (virt[i]) {
+		for( j = 0; j < virt[i]; j++) {
+			cur_rrb = i | 0xc;
+			cur_rrb = cur_rrb << (rrb_shift * 4);
+			rrb_shift--;
+			rrb_setting = rrb_setting | cur_rrb;
+			dev_rrbs[i] = dev_rrbs[i] - 1;
+		}
+	}
+	for (j = 0; j < dev_rrbs[i]; j++) {
+	    cur_rrb = i | 0x8;
+	    cur_rrb = cur_rrb << (rrb_shift * 4);
+	    rrb_shift--;
+	    rrb_setting = rrb_setting | cur_rrb;
+	}
+    }
+
+    if (pcibr_soft)
+	s = pcibr_lock(pcibr_soft);
+
+    bridge->b_rrb_map[even_odd].reg = rrb_setting;
+
+    if (pcibr_soft) {
+
+	pcibr_soft->bs_rrb_fixed |= 0x55 << even_odd;
+
+	/* since we've "FIXED" the allocations
+	 * for these slots, we probably can dispense
+	 * with tracking avail/res/valid data, but
+	 * keeping it up to date helps debugging.
+	 */
+
+	pcibr_soft->bs_rrb_avail[even_odd] =
+	    8 - (dev_1_rrbs + dev_2_rrbs + dev_3_rrbs + dev_4_rrbs);
+
+	pcibr_soft->bs_rrb_res[even_odd + 0] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 2] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 4] = 0;
+	pcibr_soft->bs_rrb_res[even_odd + 6] = 0;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0] = dev_1_rrbs - virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2] = dev_2_rrbs - virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4] = dev_3_rrbs - virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6] = dev_4_rrbs - virt4;
+
+	pcibr_soft->bs_rrb_valid[even_odd + 0 + PCIBR_RRB_SLOT_VIRTUAL] = virt1;
+	pcibr_soft->bs_rrb_valid[even_odd + 2 + PCIBR_RRB_SLOT_VIRTUAL] = virt2;
+	pcibr_soft->bs_rrb_valid[even_odd + 4 + PCIBR_RRB_SLOT_VIRTUAL] = virt3;
+	pcibr_soft->bs_rrb_valid[even_odd + 6 + PCIBR_RRB_SLOT_VIRTUAL] = virt4;
+
+	pcibr_unlock(pcibr_soft, s);
+    }
+    return 0;
+}
+
+/*
+ *    pcibr_rrb_flush: chase down all the RRBs assigned
+ *      to the specified connection point, and flush
+ *      them.
+ */
+void
+pcibr_rrb_flush(devfs_handle_t pconn_vhdl)
+{
+    pciio_info_t            pciio_info = pciio_info_get(pconn_vhdl);
+    pcibr_soft_t            pcibr_soft = (pcibr_soft_t) pciio_info_mfast_get(pciio_info);
+    pciio_slot_t            pciio_slot = pciio_info_slot_get(pciio_info);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    unsigned long           s;
+    reg_p                   rrbp;
+    unsigned                rrbm;
+    int                     i;
+    int                     rrbn;
+    unsigned                sval;
+    unsigned                mask;
+
+    sval = BRIDGE_RRB_EN | (pciio_slot >> 1);
+    mask = BRIDGE_RRB_EN | BRIDGE_RRB_PDEV;
+    rrbn = pciio_slot & 1;
+    rrbp = &bridge->b_rrb_map[rrbn].reg;
+
+    s = pcibr_lock(pcibr_soft);
+    rrbm = *rrbp;
+    for (i = 0; i < 8; ++i) {
+	if ((rrbm & mask) == sval)
+	    do_pcibr_rrb_flush(bridge, rrbn);
+	rrbm >>= 4;
+	rrbn += 2;
+    }
+    pcibr_unlock(pcibr_soft, s);
+}
+
+/*
+ * pcibr_slot_initial_rrb_alloc
+ *	Allocate a default number of rrbs for this slot on 
+ * 	the two channels.  This is dictated by the rrb allocation
+ * 	strategy routine defined per platform.
+ */
+
+int
+pcibr_slot_initial_rrb_alloc(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    pcibr_info_h	 pcibr_infoh;
+    pcibr_info_t	 pcibr_info;
+    bridge_t		*bridge;
+    int                  c0, c1, r;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* How may RRBs are on this slot?
+     */
+    c0 = do_pcibr_rrb_count_valid(bridge, slot);
+    c1 = do_pcibr_rrb_count_valid(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL);
+
+#if PCIBR_RRB_DEBUG
+    printk(
+	    "pcibr_slot_initial_rrb_alloc: slot %d started with %d+%d\n",
+            slot, c0, c1);
+#endif
+
+    /* Do we really need any?
+     */
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    pcibr_info = pcibr_infoh[0];
+    if ((pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE) &&
+	!pcibr_soft->bs_slot[slot].has_host) {
+	if (c0 > 0)
+	    do_pcibr_rrb_free(bridge, slot, c0);
+	if (c1 > 0)
+	    do_pcibr_rrb_free(bridge, slot + PCIBR_RRB_SLOT_VIRTUAL, c1);
+	pcibr_soft->bs_rrb_valid[slot] = 0x1000;
+	pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = 0x1000;
+	return(ENODEV);
+    }
+
+    pcibr_soft->bs_rrb_avail[slot & 1] -= c0 + c1;
+    pcibr_soft->bs_rrb_valid[slot] = c0;
+    pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL] = c1;
+
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    r = 3 - (c0 + c1);
+
+    if (r > 0) {
+	pcibr_soft->bs_rrb_res[slot] = r;
+	pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("\t%d+%d+%d",
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot],
+	    0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+	    pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_initial_rrb
+ *      Assign an equal total number of RRBs to all candidate slots, 
+ *      where the total is the sum of the number of RRBs assigned to
+ *      the normal channel, the number of RRBs assigned to the virtual
+ *      channel, and the number of RRBs assigned as reserved. 
+ *
+ *      A candidate slot is a populated slot on a non-SN1 system or 
+ *      any existing (populated or empty) slot on an SN1 system.
+ *      Empty SN1 slots need RRBs to support hot-plug operations.
+ */
+
+int
+pcibr_initial_rrb(devfs_handle_t pcibr_vhdl,
+			     pciio_slot_t first, pciio_slot_t last)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t               *bridge = pcibr_soft->bs_base;
+    pciio_slot_t            slot;
+    int                     c0, c1;
+    int                     have[2][3];
+    int                     res[2];
+    int                     eo;
+
+    have[0][0] = have[0][1] = have[0][2] = 0;
+    have[1][0] = have[1][1] = have[1][2] = 0;
+    res[0] = res[1] = 0;
+
+    for (slot = 0; slot < 8; ++slot) {
+        /* Initial RRB management; give back RRBs in all non-existent slots */
+        (void) pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
+
+        /* Base calculations only on existing slots */
+        if ((slot >= first) && (slot <= last)) {
+            c0 = pcibr_soft->bs_rrb_valid[slot];
+            c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL];
+            if ((c0 + c1) < 3)
+                have[slot & 1][c0 + c1]++;
+        }
+    }
+
+    /* Initialize even/odd slot available RRB counts */
+    pcibr_soft->bs_rrb_avail[0] = do_pcibr_rrb_count_avail(bridge, 0);
+    pcibr_soft->bs_rrb_avail[1] = do_pcibr_rrb_count_avail(bridge, 1);
+
+    /*
+     * Calculate reserved RRBs for slots based on current RRB usage
+     */
+    for (eo = 0; eo < 2; eo++) {
+        if ((3 * have[eo][0] + 2 * have[eo][1] + have[eo][2]) <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 3;
+        else if ((2 * have[eo][0] + have[eo][1]) <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 2;
+        else if (have[eo][0] <= pcibr_soft->bs_rrb_avail[eo])
+            res[eo] = 1;
+        else
+            res[eo] = 0;
+
+    }
+
+    /* Assign reserved RRBs to existing slots */
+    for (slot = first; slot <= last; ++slot) {
+        int                     r;
+
+        c0 = pcibr_soft->bs_rrb_valid[slot];
+        c1 = pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL];
+        r = res[slot & 1] - (c0 + c1);
+
+        if (r > 0) {
+            pcibr_soft->bs_rrb_res[slot] = r;
+            pcibr_soft->bs_rrb_avail[slot & 1] -= r;
+            }
+    }
+
+#if PCIBR_RRB_DEBUG
+    printk("%v RRB MANAGEMENT: %d+%d free\n",
+            pcibr_vhdl,
+            pcibr_soft->bs_rrb_avail[0],
+            pcibr_soft->bs_rrb_avail[1]);
+    for (slot = first; slot <= last; ++slot)
+        printk("\tslot %d: %d+%d+%d", slot,
+                0xFFF & pcibr_soft->bs_rrb_valid[slot],
+                0xFFF & pcibr_soft->bs_rrb_valid[slot + PCIBR_RRB_SLOT_VIRTUAL],
+                pcibr_soft->bs_rrb_res[slot]);
+    printk("\n");
+#endif
+
+    return 0;
+
+}
+
diff -Nru a/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/pcibr/pcibr_slot.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1692 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/pci/pci_defs.h>
+#include <asm/sn/prio.h>
+#include <asm/sn/xtalk/xbow.h>
+#include <asm/sn/ioc3.h>
+#include <asm/sn/eeprom.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+
+extern pcibr_info_t     pcibr_info_get(devfs_handle_t);
+extern int              pcibr_widget_to_bus(int);
+extern pcibr_info_t     pcibr_device_info_new(pcibr_soft_t, pciio_slot_t, pciio_function_t, pciio_vendor_id_t, pciio_device_id_t);
+extern void             pcibr_freeblock_sub(iopaddr_t *, iopaddr_t *, iopaddr_t, size_t);
+extern int		pcibr_slot_initial_rrb_alloc(devfs_handle_t,pciio_slot_t);
+#if 0
+int pcibr_slot_reset(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+#endif
+
+int pcibr_slot_info_init(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_slot_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,  pciio_slot_t slot);
+int pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+		 pciio_slot_t slot, int drv_flags);
+int pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+		 pciio_slot_t slot, int drv_flags);
+int pcibr_slot_detach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot, int drv_flags);
+int pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl, pciio_slot_t slot);
+int pcibr_probe_slot(bridge_t *, cfg_p, unsigned int *);
+void		 pcibr_device_info_free(devfs_handle_t, pciio_slot_t);
+extern uint64_t  do_pcibr_config_get(cfg_p, unsigned, unsigned);
+
+#ifdef LATER
+int pcibr_slot_attach(devfs_handle_t pcibr_vhdl, pciio_slot_t slot,
+                int drv_flags, char *l1_msg, int *sub_errorp);
+int pcibr_slot_pwr(devfs_handle_t, pciio_slot_t, int, char *);
+int pcibr_slot_startup(devfs_handle_t, pcibr_slot_req_t);
+int pcibr_slot_shutdown(devfs_handle_t, pcibr_slot_req_t);
+void pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh, int func,
+                 pcibr_slot_func_info_resp_t funcp);
+int pcibr_slot_info_return(pcibr_soft_t pcibr_soft, pciio_slot_t slot,
+                 pcibr_slot_info_resp_t respp);
+int pcibr_slot_query(devfs_handle_t, pcibr_slot_req_t);
+#endif	/* LATER */
+
+extern devfs_handle_t baseio_pci_vhdl;
+int scsi_ctlr_nums_add(devfs_handle_t, devfs_handle_t);
+
+/* For now .... */
+/*
+ * PCI Hot-Plug Capability Flags
+ */
+#define D_PCI_HOT_PLUG_ATTACH  0x200  /* Driver supports PCI hot-plug attach */
+#define D_PCI_HOT_PLUG_DETACH  0x400  /* Driver supports PCI hot-plug detach */
+
+
+/*==========================================================================
+ *	BRIDGE PCI SLOT RELATED IOCTLs
+ */
+
+#ifdef LATER
+
+/*
+ * pcibr_slot_startup
+ *	Software start-up the PCI slot.
+ */
+int
+pcibr_slot_startup(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t                   pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t                   slot = reqp->req_slot;
+    int                            error = 0;
+    char                           l1_msg[BRL1_QSIZE+1];
+    struct pcibr_slot_up_resp_s    tmp_up_resp;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    /* Do not allow start-up of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+ 
+    /* Check for the valid slot */
+    if (!PCIBR_VALID_SLOT(slot))
+        return(PCI_NOT_A_SLOT);
+
+    /* Acquire update access to the bus */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    if (pcibr_soft->bs_slot[slot].slot_status & SLOT_STARTUP_CMPLT) {
+        error = PCI_SLOT_ALREADY_UP;
+        goto startup_unlock;
+    }
+
+    error = pcibr_slot_attach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_ATTACH,
+                              l1_msg, &tmp_up_resp.resp_sub_errno);
+
+    strncpy(tmp_up_resp.resp_l1_msg, l1_msg, L1_QSIZE);
+    tmp_up_resp.resp_l1_msg[L1_QSIZE] = '\0';
+
+    if (COPYOUT(&tmp_up_resp, reqp->req_respp.up, reqp->req_size)) {
+        return(EFAULT);
+    }
+
+    startup_unlock:
+
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+    return(error);
+}
+
+/*
+ * pcibr_slot_shutdown
+ *	Software shut-down the PCI slot
+ */
+int
+pcibr_slot_shutdown(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t                   pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    bridge_t                      *bridge;
+    pciio_slot_t                   slot = reqp->req_slot;
+    int                            error = 0;
+    char                           l1_msg[BRL1_QSIZE+1];
+    struct pcibr_slot_down_resp_s  tmp_down_resp;
+    pciio_slot_t                   tmp_slot;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Check for valid slot */
+    if (!PCIBR_VALID_SLOT(slot))
+        return(PCI_NOT_A_SLOT);
+
+    /* Do not allow shut-down of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+
+    /* Acquire update access to the bus */
+    mrlock(pcibr_soft->bs_bus_lock, MR_UPDATE, PZERO);
+
+    if ((pcibr_soft->bs_slot[slot].slot_status & SLOT_SHUTDOWN_CMPLT) ||
+        ((pcibr_soft->bs_slot[slot].slot_status & SLOT_STATUS_MASK) == 0)) {
+        error = PCI_SLOT_ALREADY_DOWN;
+        /*
+         * RJR - Should we invoke an L1 slot power-down command just in case
+         *       a previous shut-down failed to power-down the slot?
+         */
+        goto shutdown_unlock;
+    }
+
+    /* Do not allow the last 33 MHz card to be removed */
+    if ((bridge->b_wid_control & BRIDGE_CTRL_BUS_SPEED_MASK) ==
+         BRIDGE_CTRL_BUS_SPEED_33) {
+        for (tmp_slot = pcibr_soft->bs_first_slot;
+             tmp_slot <= pcibr_soft->bs_last_slot; tmp_slot++)
+            if (tmp_slot != slot)
+                if (pcibr_soft->bs_slot[tmp_slot].slot_status & SLOT_POWER_UP) {
+                    error++;
+                    break;
+                }
+        if (!error) {
+            error = PCI_EMPTY_33MHZ;
+            goto shutdown_unlock;
+        }
+    }
+
+    error = pcibr_slot_detach(pcibr_vhdl, slot, D_PCI_HOT_PLUG_DETACH,
+                              l1_msg, &tmp_down_resp.resp_sub_errno);
+
+    strncpy(tmp_down_resp.resp_l1_msg, l1_msg, L1_QSIZE);
+    tmp_down_resp.resp_l1_msg[L1_QSIZE] = '\0';
+
+    if (COPYOUT(&tmp_down_resp, reqp->req_respp.down, reqp->req_size)) {
+        return(EFAULT);
+    }
+
+    shutdown_unlock:
+
+    /* Release the bus lock */
+    mrunlock(pcibr_soft->bs_bus_lock);
+
+    return(error);
+}
+
+char *pci_space_name[] = {"NONE", 
+			  "ROM",
+			  "IO",
+			  "",
+			  "MEM",
+			  "MEM32",
+			  "MEM64",
+			  "CFG",
+			  "WIN0",
+			  "WIN1",
+			  "WIN2",
+			  "WIN3",
+			  "WIN4",
+			  "WIN5",
+			  "",
+			  "BAD"};
+
+void
+pcibr_slot_func_info_return(pcibr_info_h pcibr_infoh,
+                            int func,
+                            pcibr_slot_func_info_resp_t funcp)
+{
+    pcibr_info_t                 pcibr_info = pcibr_infoh[func];
+    int                          win;
+
+    funcp->resp_f_status = 0;
+
+    if (!pcibr_info) {
+        return;
+    }
+
+    funcp->resp_f_status |= FUNC_IS_VALID;
+    sprintf(funcp->resp_f_slot_name, "%v", pcibr_info->f_vertex);
+
+    if(is_sys_critical_vertex(pcibr_info->f_vertex)) {
+        funcp->resp_f_status |= FUNC_IS_SYS_CRITICAL;
+    }
+
+    funcp->resp_f_bus = pcibr_info->f_bus;
+    funcp->resp_f_slot = pcibr_info->f_slot;
+    funcp->resp_f_func = pcibr_info->f_func;
+    sprintf(funcp->resp_f_master_name, "%v", pcibr_info->f_master);
+    funcp->resp_f_pops = pcibr_info->f_pops;
+    funcp->resp_f_efunc = pcibr_info->f_efunc;
+    funcp->resp_f_einfo = pcibr_info->f_einfo;
+
+    funcp->resp_f_vendor = pcibr_info->f_vendor;
+    funcp->resp_f_device = pcibr_info->f_device;
+
+    for(win = 0 ; win < 6 ; win++) {
+        funcp->resp_f_window[win].resp_w_base =
+                                  pcibr_info->f_window[win].w_base;
+        funcp->resp_f_window[win].resp_w_size =
+                                  pcibr_info->f_window[win].w_size;
+        sprintf(funcp->resp_f_window[win].resp_w_space,
+                "%s",
+                pci_space_name[pcibr_info->f_window[win].w_space]);
+    }
+
+    funcp->resp_f_rbase = pcibr_info->f_rbase;
+    funcp->resp_f_rsize = pcibr_info->f_rsize;
+
+    for (win = 0 ; win < 4; win++) {
+        funcp->resp_f_ibit[win] = pcibr_info->f_ibit[win];
+    }
+
+    funcp->resp_f_att_det_error = pcibr_info->f_att_det_error;
+
+}
+
+int
+pcibr_slot_info_return(pcibr_soft_t             pcibr_soft,
+                       pciio_slot_t             slot,
+                       pcibr_slot_info_resp_t   respp)
+{
+    pcibr_soft_slot_t            pss;
+    int                          func;
+    bridge_t                    *bridge = pcibr_soft->bs_base;
+    reg_p                        b_respp;
+    pcibr_slot_info_resp_t       slotp;
+    pcibr_slot_func_info_resp_t  funcp;
+
+    slotp = kmem_zalloc(sizeof(*slotp), KM_SLEEP);
+    if (slotp == NULL) {
+        return(ENOMEM);
+    }
+
+    pss = &pcibr_soft->bs_slot[slot];
+
+    slotp->resp_has_host = pss->has_host;
+    slotp->resp_host_slot = pss->host_slot;
+    sprintf(slotp->resp_slot_conn_name, "%v", pss->slot_conn);
+    slotp->resp_slot_status = pss->slot_status;
+
+    slotp->resp_l1_bus_num = io_path_map_widget(pcibr_soft->bs_vhdl);
+
+    if (is_sys_critical_vertex(pss->slot_conn)) {
+        slotp->resp_slot_status |= SLOT_IS_SYS_CRITICAL;
+    }
+
+    slotp->resp_bss_ninfo = pss->bss_ninfo;
+
+    for (func = 0; func < pss->bss_ninfo; func++) {
+        funcp = &(slotp->resp_func[func]);
+        pcibr_slot_func_info_return(pss->bss_infos, func, funcp);
+    }
+
+    sprintf(slotp->resp_bss_devio_bssd_space, "%s",
+            pci_space_name[pss->bss_devio.bssd_space]);
+    slotp->resp_bss_devio_bssd_base = pss->bss_devio.bssd_base;
+    slotp->resp_bss_device = pss->bss_device;
+
+    slotp->resp_bss_pmu_uctr = pss->bss_pmu_uctr;
+    slotp->resp_bss_d32_uctr = pss->bss_d32_uctr;
+    slotp->resp_bss_d64_uctr = pss->bss_d64_uctr;
+
+    slotp->resp_bss_d64_base = pss->bss_d64_base;
+    slotp->resp_bss_d64_flags = pss->bss_d64_flags;
+    slotp->resp_bss_d32_base = pss->bss_d32_base;
+    slotp->resp_bss_d32_flags = pss->bss_d32_flags;
+
+    slotp->resp_bss_ext_ates_active = pss->bss_ext_ates_active;
+
+    slotp->resp_bss_cmd_pointer = pss->bss_cmd_pointer;
+    slotp->resp_bss_cmd_shadow = pss->bss_cmd_shadow;
+
+    slotp->resp_bs_rrb_valid = pcibr_soft->bs_rrb_valid[slot];
+    slotp->resp_bs_rrb_valid_v = pcibr_soft->bs_rrb_valid[slot +
+                                                      PCIBR_RRB_SLOT_VIRTUAL];
+    slotp->resp_bs_rrb_res = pcibr_soft->bs_rrb_res[slot];
+
+    if (slot & 1) {
+        b_respp = &bridge->b_odd_resp;
+    } else {
+        b_respp = &bridge->b_even_resp;
+    }
+
+    slotp->resp_b_resp = *b_respp;
+
+    slotp->resp_b_wid_control = bridge->b_wid_control;
+    slotp->resp_b_int_device = bridge->b_int_device;
+    slotp->resp_b_int_enable = bridge->b_int_enable;
+    slotp->resp_b_int_host = bridge->b_int_addr[slot].addr;
+
+    if (COPYOUT(slotp, respp, sizeof(*respp))) {
+        return(EFAULT);
+    }
+
+    kmem_free(slotp, sizeof(*slotp));
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_query
+ *	Return information about the PCI slot maintained by the infrastructure.
+ *	Information is requested in the request structure.
+ *
+ *      Information returned in the response structure:
+ *		Slot hwgraph name
+ *		Vendor/Device info
+ *		Base register info
+ *		Interrupt mapping from device pins to the bridge pins
+ *		Devio register
+ *		Software RRB info
+ *		RRB register info
+ *		Host/Gues info
+ *		PCI Bus #,slot #, function #
+ *		Slot provider hwgraph name
+ *		Provider Functions
+ *		Error handler
+ *		DMA mapping usage counters
+ *		DMA direct translation info
+ *		External SSRAM workaround info
+ */
+int
+pcibr_slot_query(devfs_handle_t pcibr_vhdl, pcibr_slot_req_t reqp)
+{
+    pcibr_soft_t            pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pciio_slot_t            slot = reqp->req_slot;
+    pciio_slot_t            tmp_slot;
+    pcibr_slot_info_resp_t  respp = reqp->req_respp.query;
+    int                     size = reqp->req_size;
+    int                     error;
+
+    /* Make sure that we are dealing with a bridge device vertex */
+    if (!pcibr_soft) {
+        return(PCI_NOT_A_BRIDGE);
+    }
+
+    /* Make sure that we have a valid PCI slot number or PCIIO_SLOT_NONE */
+    if ((!PCIBR_VALID_SLOT(slot)) && (slot != PCIIO_SLOT_NONE)) {
+        return(PCI_NOT_A_SLOT);
+    }
+
+    /* Do not allow a query of a slot in a shoehorn */
+    if(nic_vertex_info_match(pcibr_soft->bs_conn, XTALK_PCI_PART_NUM)) {
+       return(PCI_SLOT_IN_SHOEHORN);
+    }
+
+    /* Return information for the requested PCI slot */
+    if (slot != PCIIO_SLOT_NONE) {
+        if (size < sizeof(*respp)) {
+            return(PCI_RESP_AREA_TOO_SMALL);
+        }
+
+        /* Acquire read access to the bus */
+        mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, slot, respp);
+
+        /* Release the bus lock */
+        mrunlock(pcibr_soft->bs_bus_lock);
+
+        return(error);
+    }
+
+    /* Return information for all the slots */
+    for (tmp_slot = 0; tmp_slot < 8; tmp_slot++) {
+
+        if (size < sizeof(*respp)) {
+            return(PCI_RESP_AREA_TOO_SMALL);
+        }
+
+        /* Acquire read access to the bus */
+        mrlock(pcibr_soft->bs_bus_lock, MR_ACCESS, PZERO);
+
+        error = pcibr_slot_info_return(pcibr_soft, tmp_slot, respp);
+
+        /* Release the bus lock */
+        mrunlock(pcibr_soft->bs_bus_lock);
+
+        if (error) {
+            return(error);
+        }
+
+        ++respp;
+        size -= sizeof(*respp);
+    }
+
+    return(error);
+}
+#endif	/* LATER */
+
+/* FIXME: there should be a better way to do this.
+ * pcibr_attach() needs PCI_ADDR_SPACE_LIMITS_STORE
+ */
+
+/* 
+ * PCI_ADDR_SPACE_LIMITS_LOAD
+ *	Gets the current values of 
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_LOAD()			\
+    pci_io_fb = pcibr_soft->bs_spinfo.pci_io_base;	\
+    pci_io_fl = pcibr_soft->bs_spinfo.pci_io_last;	\
+    pci_lo_fb = pcibr_soft->bs_spinfo.pci_swin_base;	\
+    pci_lo_fl = pcibr_soft->bs_spinfo.pci_swin_last;	\
+    pci_hi_fb = pcibr_soft->bs_spinfo.pci_mem_base;	\
+    pci_hi_fl = pcibr_soft->bs_spinfo.pci_mem_last;
+/*
+ * PCI_ADDR_SPACE_LIMITS_STORE
+ *	Sets the current values of
+ *		pci io base, 
+ *		pci io last,
+ *		pci low memory base,
+ *		pci low memory last,
+ *		pci high memory base,
+ * 		pci high memory last
+ */
+#define PCI_ADDR_SPACE_LIMITS_STORE()			\
+    pcibr_soft->bs_spinfo.pci_io_base = pci_io_fb;	\
+    pcibr_soft->bs_spinfo.pci_io_last = pci_io_fl;	\
+    pcibr_soft->bs_spinfo.pci_swin_base = pci_lo_fb;	\
+    pcibr_soft->bs_spinfo.pci_swin_last = pci_lo_fl;	\
+    pcibr_soft->bs_spinfo.pci_mem_base = pci_hi_fb;	\
+    pcibr_soft->bs_spinfo.pci_mem_last = pci_hi_fl;
+
+#define PCI_ADDR_SPACE_LIMITS_PRINT()			\
+    printf("+++++++++++++++++++++++\n"			\
+	   "IO base 0x%x last 0x%x\n"			\
+	   "SWIN base 0x%x last 0x%x\n"			\
+	   "MEM base 0x%x last 0x%x\n"			\
+	   "+++++++++++++++++++++++\n",			\
+	   pcibr_soft->bs_spinfo.pci_io_base,		\
+	   pcibr_soft->bs_spinfo.pci_io_last,		\
+	   pcibr_soft->bs_spinfo.pci_swin_base,		\
+	   pcibr_soft->bs_spinfo.pci_swin_last,		\
+	   pcibr_soft->bs_spinfo.pci_mem_base,		\
+	   pcibr_soft->bs_spinfo.pci_mem_last);
+
+
+/*
+ * pcibr_slot_info_init
+ *	Probe for this slot and see if it is populated.
+ *	If it is populated initialize the generic PCI infrastructural
+ * 	information associated with this particular PCI device.
+ */
+int
+pcibr_slot_info_init(devfs_handle_t 	pcibr_vhdl,
+		     pciio_slot_t 	slot)
+{
+    pcibr_soft_t	    pcibr_soft;
+    pcibr_info_h	    pcibr_infoh;
+    pcibr_info_t	    pcibr_info;
+    bridge_t		   *bridge;
+    cfg_p                   cfgw;
+    unsigned                idword;
+    unsigned                pfail;
+    unsigned                idwords[8];
+    pciio_vendor_id_t       vendor;
+    pciio_device_id_t       device;
+    unsigned                htype;
+    cfg_p                   wptr;
+    int                     win;
+    pciio_space_t           space;
+    iopaddr_t		    pci_io_fb,	pci_io_fl;
+    iopaddr_t		    pci_lo_fb,  pci_lo_fl;
+    iopaddr_t		    pci_hi_fb,  pci_hi_fl;
+    int			    nfunc;
+    pciio_function_t	    rfunc;
+    int			    func;
+    devfs_handle_t	    conn_vhdl;
+    pcibr_soft_slot_t	    slotp;
+    
+    /* Get the basic software information required to proceed */
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft)
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+    if (!PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    /* If we have a host slot (eg:- IOC3 has 2 PCI slots and the initialization
+     * is done by the host slot then we are done.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);    
+    }
+
+    /* Check for a slot with any system critical functions */
+    if (pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    /* Load the current values of allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+    
+    /* Try to read the device-id/vendor-id from the config space */
+    cfgw = bridge->b_type0_cfg_dev[slot].l;
+
+    if (pcibr_probe_slot(bridge, cfgw, &idword)) 
+	return(ENODEV);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+    slotp->slot_status |= SLOT_POWER_UP;
+
+    vendor = 0xFFFF & idword;
+    /* If the vendor id is not valid then the slot is not populated
+     * and we are done.
+     */
+    if (vendor == 0xFFFF) 
+	return(ENODEV);			
+    
+    device = 0xFFFF & (idword >> 16);
+    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+
+    nfunc = 1;
+    rfunc = PCIIO_FUNC_NONE;
+    pfail = 0;
+
+    /* NOTE: if a card claims to be multifunction
+     * but only responds to config space 0, treat
+     * it as a unifunction card.
+     */
+
+    if (htype & 0x80) {		/* MULTIFUNCTION */
+	for (func = 1; func < 8; ++func) {
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    if (pcibr_probe_slot(bridge, cfgw, &idwords[func])) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    vendor = 0xFFFF & idwords[func];
+	    if (vendor == 0xFFFF) {
+		pfail |= 1 << func;
+		continue;
+	    }
+	    nfunc = func + 1;
+	    rfunc = 0;
+	}
+	cfgw = bridge->b_type0_cfg_dev[slot].l;
+    }
+    NEWA(pcibr_infoh, nfunc);
+    
+    pcibr_soft->bs_slot[slot].bss_ninfo = nfunc;
+    pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+    for (func = 0; func < nfunc; ++func) {
+	unsigned                cmd_reg;
+	
+	if (func) {
+	    if (pfail & (1 << func))
+		continue;
+	    
+	    idword = idwords[func];
+	    cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	    
+	    device = 0xFFFF & (idword >> 16);
+	    htype = do_pcibr_config_get(cfgw, PCI_CFG_HEADER_TYPE, 1);
+	    rfunc = func;
+	}
+	htype &= 0x7f;
+	if (htype != 0x00) {
+	    printk(KERN_WARNING  "%s pcibr: pci slot %d func %d has strange header type 0x%x\n",
+		    pcibr_soft->bs_name, slot, func, htype);
+	    continue;
+	}
+#if DEBUG && ATTACH_DEBUG
+	printk(KERN_NOTICE   
+		"%s pcibr: pci slot %d func %d: vendor 0x%x device 0x%x",
+		pcibr_soft->bs_name, slot, func, vendor, device);
+#endif	
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, rfunc, vendor, device);
+	conn_vhdl = pciio_device_info_register(pcibr_vhdl, &pcibr_info->f_c);
+	if (func == 0)
+	    slotp->slot_conn = conn_vhdl;
+
+#ifdef LITTLE_ENDIAN
+	cmd_reg = cfgw[(PCI_CFG_COMMAND ^ 4) / 4];
+#else
+	cmd_reg = cfgw[PCI_CFG_COMMAND / 4];
+#endif
+	
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	for (win = 0; win < PCI_CFG_BASE_ADDRS; ++win) {
+	    iopaddr_t               base, mask, code;
+	    size_t                  size;
+
+	    /*
+	     * GET THE BASE & SIZE OF THIS WINDOW:
+	     *
+	     * The low two or four bits of the BASE register
+	     * determines which address space we are in; the
+	     * rest is a base address. BASE registers
+	     * determine windows that are power-of-two sized
+	     * and naturally aligned, so we can get the size
+	     * of a window by writing all-ones to the
+	     * register, reading it back, and seeing which
+	     * bits are used for decode; the least
+	     * significant nonzero bit is also the size of
+	     * the window.
+	     *
+	     * WARNING: someone may already have allocated
+	     * some PCI space to this window, and in fact
+	     * PIO may be in process at this very moment
+	     * from another processor (or even from this
+	     * one, if we get interrupted)! So, if the BASE
+	     * already has a nonzero address, be generous
+	     * and use the LSBit of that address as the
+	     * size; this could overstate the window size.
+	     * Usually, when one card is set up, all are set
+	     * up; so, since we don't bitch about
+	     * overlapping windows, we are ok.
+	     *
+	     * UNFORTUNATELY, some cards do not clear their
+	     * BASE registers on reset. I have two heuristics
+	     * that can detect such cards: first, if the
+	     * decode enable is turned off for the space
+	     * that the window uses, we can disregard the
+	     * initial value. second, if the address is
+	     * outside the range that we use, we can disregard
+	     * it as well.
+	     *
+	     * This is looking very PCI generic. Except for
+	     * knowing how many slots and where their config
+	     * spaces are, this window loop and the next one
+	     * could probably be shared with other PCI host
+	     * adapters. It would be interesting to see if
+	     * this could be pushed up into pciio, when we
+	     * start supporting more PCI providers.
+	     */
+#ifdef LITTLE_ENDIAN
+	    base = wptr[((win*4)^4)/4];
+#else
+	    base = wptr[win];
+#endif
+
+	    if (base & PCI_BA_IO_SPACE) {
+		/* BASE is in I/O space. */
+		space = PCIIO_SPACE_IO;
+		mask = -4;
+		code = base & 3;
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_IO_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		}
+	    } else {
+		/* BASE is in MEM space. */
+		space = PCIIO_SPACE_MEM;
+		mask = -16;
+		code = base & PCI_BA_MEM_LOCATION;	/* extract BAR type */
+		base = base & mask;
+		if (base == 0) {
+		    ;		/* not assigned */
+		} else if (!(cmd_reg & PCI_CMD_MEM_SPACE)) {
+		    base = 0;	/* decode not enabled */
+		} else if (base & 0xC0000000) {
+		    base = 0;	/* outside permissable range */
+		} else if ((code == PCI_BA_MEM_64BIT) &&
+#ifdef LITTLE_ENDIAN
+			   (wptr[(((win + 1)*4)^4)/4] != 0)) {
+#else 
+			   (wptr[win + 1] != 0)) {
+#endif /* LITTLE_ENDIAN */
+		    base = 0;	/* outside permissable range */
+		}
+	    }
+
+	    if (base != 0) {	/* estimate size */
+		size = base & -base;
+	    } else {		/* calculate size */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = ~0;	/* turn on all bits */
+		size = wptr[((win*4)^4)/4];	/* get stored bits */
+#else 
+		wptr[win] = ~0;	/* turn on all bits */
+		size = wptr[win];	/* get stored bits */
+#endif /* LITTLE_ENDIAN */
+		size &= mask;	/* keep addr */
+		size &= -size;	/* keep lsbit */
+		if (size == 0)
+		    continue;
+	    }	
+
+	    pcibr_info->f_window[win].w_space = space;
+	    pcibr_info->f_window[win].w_base = base;
+	    pcibr_info->f_window[win].w_size = size;
+
+	    /*
+	     * If this window already has PCI space
+	     * allocated for it, "subtract" that space from
+	     * our running freeblocks. Don't worry about
+	     * overlaps in existing allocated windows; we
+	     * may be overstating their sizes anyway.
+	     */
+
+	    if (base && size) {
+		if (space == PCIIO_SPACE_IO) {
+		    pcibr_freeblock_sub(&pci_io_fb,
+					&pci_io_fl,
+					base, size);
+		} else {
+		    pcibr_freeblock_sub(&pci_lo_fb,
+					&pci_lo_fl,
+					base, size);
+		    pcibr_freeblock_sub(&pci_hi_fb,
+					&pci_hi_fl,
+					base, size);
+		}	
+	    }
+#if defined(IOC3_VENDOR_ID_NUM) && defined(IOC3_DEVICE_ID_NUM)
+	    /*
+	     * IOC3 BASE_ADDR* BUG WORKAROUND
+	     *
+	     
+	     * If we write to BASE1 on the IOC3, the
+	     * data in BASE0 is replaced. The
+	     * original workaround was to remember
+	     * the value of BASE0 and restore it
+	     * when we ran off the end of the BASE
+	     * registers; however, a later
+	     * workaround was added (I think it was
+	     * rev 1.44) to avoid setting up
+	     * anything but BASE0, with the comment
+	     * that writing all ones to BASE1 set
+	     * the enable-parity-error test feature
+	     * in IOC3's SCR bit 14.
+	     *
+	     * So, unless we defer doing any PCI
+	     * space allocation until drivers
+	     * attach, and set up a way for drivers
+	     * (the IOC3 in paricular) to tell us
+	     * generically to keep our hands off
+	     * BASE registers, we gotta "know" about
+	     * the IOC3 here.
+	     *
+	     * Too bad the PCI folks didn't reserve the
+	     * all-zero value for 'no BASE here' (it is a
+	     * valid code for an uninitialized BASE in
+	     * 32-bit PCI memory space).
+	     */
+	    
+	    if ((vendor == IOC3_VENDOR_ID_NUM) &&
+		(device == IOC3_DEVICE_ID_NUM))
+		break;
+#endif
+	    if (code == PCI_BA_MEM_64BIT) {
+		win++;		/* skip upper half */
+#ifdef LITTLE_ENDIAN
+		wptr[((win*4)^4)/4] = 0;	/* which must be zero */
+#else 
+		wptr[win] = 0;	/* which must be zero */
+#endif /* LITTLE_ENDIAN */
+	    }
+	}				/* next win */
+    }				/* next func */
+
+    /* Store back the values for allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}					
+
+/*
+ * pcibr_slot_info_free
+ *	Remove all the PCI infrastructural information associated
+ * 	with a particular PCI device.
+ */
+int
+pcibr_slot_info_free(devfs_handle_t pcibr_vhdl,
+                     pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    int			nfunc;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+
+    pcibr_device_info_free(pcibr_vhdl, slot);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    DELA(pcibr_infoh,nfunc);
+    pcibr_soft->bs_slot[slot].bss_ninfo = 0;
+
+    return(0);
+}
+
+int as_debug = 0;
+/*
+ * pcibr_slot_addr_space_init
+ *	Reserve chunks of PCI address space as required by 
+ * 	the base registers in the card.
+ */
+int
+pcibr_slot_addr_space_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    bridge_t		*bridge;
+    iopaddr_t		pci_io_fb, pci_io_fl;
+    iopaddr_t		pci_lo_fb, pci_lo_fl;
+    iopaddr_t		pci_hi_fb, pci_hi_fl;
+    size_t              align;
+    iopaddr_t           mask;
+    int		    	nbars;
+    int		       	nfunc;
+    int			func;
+    int			win;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /* Get the current values for the allocated PCI address spaces */
+    PCI_ADDR_SPACE_LIMITS_LOAD();
+
+    if (as_debug)
+#ifdef LATER
+    PCI_ADDR_SPACE_LIMITS_PRINT();
+#endif
+
+    /* allocate address space,
+     * for windows that have not been
+     * previously assigned.
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	return(0);
+    }
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    if (nfunc < 1)
+	return(EINVAL);
+
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+    if (!pcibr_infoh)
+	return(EINVAL);
+
+    /*
+     * Try to make the DevIO windows not
+     * overlap by pushing the "io" and "hi"
+     * allocation areas up to the next one
+     * or two megabyte bound. This also
+     * keeps them from being zero.
+     *
+     * DO NOT do this with "pci_lo" since
+     * the entire "lo" area is only a
+     * megabyte, total ...
+     */
+    align = (slot < 2) ? 0x200000 : 0x100000;
+    mask = -align;
+    pci_io_fb = (pci_io_fb + align - 1) & mask;
+    pci_hi_fb = (pci_hi_fb + align - 1) & mask;
+
+    for (func = 0; func < nfunc; ++func) {
+	cfg_p                   cfgw;
+	cfg_p                   wptr;
+	pciio_space_t           space;
+	iopaddr_t               base;
+	size_t                  size;
+	cfg_p                   pci_cfg_cmd_reg_p;
+	unsigned                pci_cfg_cmd_reg;
+	unsigned                pci_cfg_cmd_reg_add = 0;
+
+	pcibr_info = pcibr_infoh[func];
+
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+	
+	cfgw = bridge->b_type0_cfg_dev[slot].f[func].l;
+	wptr = cfgw + PCI_CFG_BASE_ADDR_0 / 4;
+
+	nbars = PCI_CFG_BASE_ADDRS;
+
+	for (win = 0; win < nbars; ++win) {
+
+	    space = pcibr_info->f_window[win].w_space;
+	    base = pcibr_info->f_window[win].w_base;
+	    size = pcibr_info->f_window[win].w_size;
+	    
+	    if (size < 1)
+		continue;
+
+	    if (base >= size) {
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d func %d window %d is in %d[0x%x..0x%x], alloc by prom\n",
+			slot, func, win, space, base, base + size - 1);
+#endif
+		continue;		/* already allocated */
+	    }
+	    align = size;		/* ie. 0x00001000 */
+	    if (align < _PAGESZ)
+		align = _PAGESZ;	/* ie. 0x00004000 */
+	    mask = -align;		/* ie. 0xFFFFC000 */
+
+	    switch (space) {
+	    case PCIIO_SPACE_IO:
+		base = (pci_io_fb + align - 1) & mask;
+		if ((base + size) > pci_io_fl) {
+		    base = 0;
+		    break;
+		}
+		pci_io_fb = base + size;
+		break;
+		
+	    case PCIIO_SPACE_MEM:
+#ifdef LITTLE_ENDIAN
+		if ((wptr[((win*4)^4)/4] & PCI_BA_MEM_LOCATION) ==
+#else
+		if ((wptr[win] & PCI_BA_MEM_LOCATION) ==
+#endif  /* LITTLE_ENDIAN */
+		    PCI_BA_MEM_1MEG) {
+		    /* allocate from 20-bit PCI space */
+		    base = (pci_lo_fb + align - 1) & mask;
+		    if ((base + size) > pci_lo_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_lo_fb = base + size;
+		} else {
+		    /* allocate from 32-bit or 64-bit PCI space */
+		    base = (pci_hi_fb + align - 1) & mask;
+		    if ((base + size) > pci_hi_fl) {
+			base = 0;
+			break;
+		    }
+		    pci_hi_fb = base + size;
+		}
+		break;
+		
+	    default:
+		base = 0;
+#if DEBUG && PCI_DEBUG
+		printk("pcibr: slot %d window %d had bad space code %d\n",
+			slot, win, space);
+#endif
+	    }
+	    pcibr_info->f_window[win].w_base = base;
+#ifdef LITTLE_ENDIAN
+	    wptr[((win*4)^4)/4] = base;
+#if DEBUG && PCI_DEBUG
+		printk("Setting base address 0x%p base 0x%x\n", &(wptr[((win*4)^4)/4]), base);
+#endif
+#else
+	    wptr[win] = base;
+#endif  /* LITTLE_ENDIAN */
+
+#if DEBUG && PCI_DEBUG
+	    if (base >= size)
+		printk("pcibr: slot %d func %d window %d is in %d [0x%x..0x%x], alloc by pcibr\n",
+			slot, func, win, space, base, base + size - 1);
+	    else
+		printk("pcibr: slot %d func %d window %d, unable to alloc 0x%x in 0x%p\n",
+			slot, func, win, size, space);
+#endif
+	}				/* next base */
+
+	/*
+	 * Allocate space for the EXPANSION ROM
+	 * NOTE: DO NOT DO THIS ON AN IOC3,
+	 * as it blows the system away.
+	 */
+	base = size = 0;
+	if ((pcibr_soft->bs_slot[slot].bss_vendor_id != IOC3_VENDOR_ID_NUM) ||
+	    (pcibr_soft->bs_slot[slot].bss_device_id != IOC3_DEVICE_ID_NUM)) {
+
+	    wptr = cfgw + PCI_EXPANSION_ROM / 4;
+#ifdef LITTLE_ENDIAN
+	    wptr[1] = 0xFFFFF000;
+	    mask = wptr[1];
+#else
+	    *wptr = 0xFFFFF000;
+	    mask = *wptr;
+#endif  /* LITTLE_ENDIAN */
+	    if (mask & 0xFFFFF000) {
+		size = mask & -mask;
+		align = size;
+		if (align < _PAGESZ)
+		    align = _PAGESZ;
+		mask = -align;
+		base = (pci_hi_fb + align - 1) & mask;
+		if ((base + size) > pci_hi_fl)
+		    base = size = 0;
+		else {
+		    pci_hi_fb = base + size;
+#ifdef LITTLE_ENDIAN
+		    wptr[1] = base;
+#else
+		    *wptr = base;
+#endif  /* LITTLE_ENDIAN */
+#if DEBUG && PCI_DEBUG
+		    printk("%s/%d ROM in 0x%lx..0x%lx (alloc by pcibr)\n",
+			    pcibr_soft->bs_name, slot,
+			    base, base + size - 1);
+#endif
+		}
+	    }
+	}
+	pcibr_info->f_rbase = base;
+	pcibr_info->f_rsize = size;
+	
+	/*
+	 * if necessary, update the board's
+	 * command register to enable decoding
+	 * in the windows we added.
+	 *
+	 * There are some bits we always want to
+	 * be sure are set.
+	 */
+	pci_cfg_cmd_reg_add |= PCI_CMD_IO_SPACE;
+
+	/*
+	 * The Adaptec 1160 FC Controller WAR #767995:
+	 * The part incorrectly ignores the upper 32 bits of a 64 bit
+	 * address when decoding references to it's registers so to
+	 * keep it from responding to a bus cycle that it shouldn't
+	 * we only use I/O space to get at it's registers.  Don't
+	 * enable memory space accesses on that PCI device.
+	 */
+	#define FCADP_VENDID 0x9004 /* Adaptec Vendor ID from fcadp.h */
+	#define FCADP_DEVID 0x1160  /* Adaptec 1160 Device ID from fcadp.h */
+
+	if ((pcibr_info->f_vendor != FCADP_VENDID) ||
+	    (pcibr_info->f_device != FCADP_DEVID))
+	    pci_cfg_cmd_reg_add |= PCI_CMD_MEM_SPACE;
+
+	pci_cfg_cmd_reg_add |= PCI_CMD_BUS_MASTER;
+
+	pci_cfg_cmd_reg_p = cfgw + PCI_CFG_COMMAND / 4;
+	pci_cfg_cmd_reg = *pci_cfg_cmd_reg_p;
+#if PCI_FBBE	/* XXX- check here to see if dev can do fast-back-to-back */
+	if (!((pci_cfg_cmd_reg >> 16) & PCI_STAT_F_BK_BK_CAP))
+	    fast_back_to_back_enable = 0;
+#endif
+	pci_cfg_cmd_reg &= 0xFFFF;
+	if (pci_cfg_cmd_reg_add & ~pci_cfg_cmd_reg)
+	    *pci_cfg_cmd_reg_p = pci_cfg_cmd_reg | pci_cfg_cmd_reg_add;
+	
+    }				/* next func */
+
+    /* Now that we have allocated new chunks of PCI address spaces to this
+     * card we need to update the bookkeeping values which indicate
+     * the current PCI address space allocations.
+     */
+    PCI_ADDR_SPACE_LIMITS_STORE();
+    return(0);
+}
+
+/*
+ * pcibr_slot_device_init
+ * 	Setup the device register in the bridge for this PCI slot.
+ */
+int
+pcibr_slot_device_init(devfs_handle_t pcibr_vhdl,
+		       pciio_slot_t slot)
+{
+    pcibr_soft_t	 pcibr_soft;
+    bridge_t		*bridge;
+    bridgereg_t		 devreg;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    bridge = pcibr_soft->bs_base;
+
+    /*
+     * Adjustments to Device(x)
+     * and init of bss_device shadow
+     */
+    devreg = bridge->b_device[slot].reg;
+    devreg &= ~BRIDGE_DEV_PAGE_CHK_DIS;
+    devreg |= BRIDGE_DEV_COH | BRIDGE_DEV_VIRTUAL_EN;
+#ifdef LITTLE_ENDIAN
+    devreg |= BRIDGE_DEV_DEV_SWAP;
+#endif
+    pcibr_soft->bs_slot[slot].bss_device = devreg;
+    bridge->b_device[slot].reg = devreg;
+
+#if DEBUG && PCI_DEBUG
+	printk("pcibr Device(%d): 0x%lx\n", slot, bridge->b_device[slot].reg);
+#endif
+
+#if DEBUG && PCI_DEBUG
+    printk("pcibr: PCI space allocation done.\n");
+#endif
+
+    return(0);
+}
+
+/*
+ * pcibr_slot_guest_info_init
+ *	Setup the host/guest relations for a PCI slot.
+ */
+int
+pcibr_slot_guest_info_init(devfs_handle_t pcibr_vhdl,
+			   pciio_slot_t	slot)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    pcibr_soft_slot_t	slotp;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    slotp = &pcibr_soft->bs_slot[slot];
+
+    /* create info and verticies for guest slots;
+     * for compatibilitiy macros, create info
+     * for even unpopulated slots (but do not
+     * build verticies for them).
+     */
+    if (pcibr_soft->bs_slot[slot].bss_ninfo < 1) {
+	NEWA(pcibr_infoh, 1);
+	pcibr_soft->bs_slot[slot].bss_ninfo = 1;
+	pcibr_soft->bs_slot[slot].bss_infos = pcibr_infoh;
+
+	pcibr_info = pcibr_device_info_new
+	    (pcibr_soft, slot, PCIIO_FUNC_NONE,
+	     PCIIO_VENDOR_ID_NONE, PCIIO_DEVICE_ID_NONE);
+
+	if (pcibr_soft->bs_slot[slot].has_host) {
+	    slotp->slot_conn = pciio_device_info_register
+		(pcibr_vhdl, &pcibr_info->f_c);
+	}
+    }
+
+    /* generate host/guest relations
+     */
+    if (pcibr_soft->bs_slot[slot].has_host) {
+	int  host = pcibr_soft->bs_slot[slot].host_slot;
+	pcibr_soft_slot_t host_slotp = &pcibr_soft->bs_slot[host];
+
+	hwgraph_edge_add(slotp->slot_conn,
+			 host_slotp->slot_conn,
+			 EDGE_LBL_HOST);
+
+	/* XXX- only gives us one guest edge per
+	 * host. If/when we have a host with more than
+	 * one guest, we will need to figure out how
+	 * the host finds all its guests, and sorts
+	 * out which one is which.
+	 */
+	hwgraph_edge_add(host_slotp->slot_conn,
+			 slotp->slot_conn,
+			 EDGE_LBL_GUEST);
+    }
+
+    return(0);
+}
+
+
+/*
+ * pcibr_slot_call_device_attach
+ *	This calls the associated driver attach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_attach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    async_attach_t	aa = NULL;
+    int			func;
+    devfs_handle_t	xconn_vhdl,conn_vhdl;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+
+    if (pcibr_soft->bs_slot[slot].has_host) {
+        return(EPERM);
+    }
+    
+    xconn_vhdl = pcibr_soft->bs_conn;
+    aa = async_attach_get_info(xconn_vhdl);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+#ifdef LATER
+	/*
+	 * Activate if and when we support cdl.
+	 */
+	if (aa)
+	    async_attach_add_info(conn_vhdl, aa);
+#endif	/* LATER */
+
+	error_func = pciio_device_attach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+        error = error_slot;
+
+    }				/* next func */
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+	    pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_INCMPLT;
+    } else {
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_STARTUP_CMPLT;
+    }
+        
+    return(error);
+}
+
+/*
+ * pcibr_slot_call_device_detach
+ *	This calls the associated driver detach routine for the PCI
+ * 	card in this slot.
+ */
+int
+pcibr_slot_call_device_detach(devfs_handle_t pcibr_vhdl,
+			      pciio_slot_t slot,
+			      int          drv_flags)
+{
+    pcibr_soft_t	pcibr_soft;
+    pcibr_info_h	pcibr_infoh;
+    pcibr_info_t	pcibr_info;
+    int			func;
+    devfs_handle_t	conn_vhdl = GRAPH_VERTEX_NONE;
+    int			nfunc;
+    int                 error_func;
+    int                 error_slot = 0;
+    int                 error = ENODEV;
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+	return(EINVAL);
+
+    if (pcibr_soft->bs_slot[slot].has_host)
+        return(EPERM);
+
+    /* Make sure that we do not detach a system critical function vertex */
+    if(pcibr_is_slot_sys_critical(pcibr_vhdl, slot))
+        return(EPERM);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+	pcibr_info = pcibr_infoh[func];
+	
+	if (!pcibr_info)
+	    continue;
+
+	if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+	    continue;
+
+	conn_vhdl = pcibr_info->f_vertex;
+
+	error_func = pciio_device_detach(conn_vhdl, drv_flags);
+
+        pcibr_info->f_att_det_error = error_func;
+
+	if (error_func)
+	    error_slot = error_func;
+
+	error = error_slot;
+
+    }				/* next func */
+
+    pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_STATUS_MASK;
+
+    if (error) {
+	if ((error != ENODEV) && (error != EUNATCH))
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_INCMPLT;
+    } else {
+        if (conn_vhdl != GRAPH_VERTEX_NONE) 
+            pcibr_device_unregister(conn_vhdl);
+        pcibr_soft->bs_slot[slot].slot_status |= SLOT_SHUTDOWN_CMPLT;
+    }
+        
+    return(error);
+}
+
+#ifdef LATER
+
+/*
+ * pcibr_slot_attach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific initialization that needs to be done.
+ *	This is usually called when we want to initialize a new
+ * 	PCI card on the bus.
+ */
+int
+pcibr_slot_attach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags,
+		  char        *l1_msg,
+                  int         *sub_errorp)
+{
+    pcibr_soft_t  pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    timespec_t    ts;
+    int		  error;
+
+    if (!(pcibr_soft->bs_slot[slot].slot_status & SLOT_POWER_UP)) { 
+        /* Power-up the slot */
+        error = pcibr_slot_pwr(pcibr_vhdl, slot, L1_REQ_PCI_UP, l1_msg);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_L1_ERR);
+        } else {
+            pcibr_soft->bs_slot[slot].slot_status &= ~SLOT_POWER_MASK;
+            pcibr_soft->bs_slot[slot].slot_status |= SLOT_POWER_UP;
+        }
+
+#ifdef LATER
+        /*
+         * Allow cards like the Alteon Gigabit Ethernet Adapter to complete
+         * on-card initialization following the slot reset
+         */
+         ts.tv_sec = 0;                      /* 0 secs */
+         ts.tv_nsec = 500 * (1000 * 1000);   /* 500 msecs */
+         nano_delay(&ts);
+#else
+#endif
+#if 0
+        /* Reset the slot */
+        error = pcibr_slot_reset(pcibr_vhdl, slot)
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_RESET_ERR);
+        }
+#endif
+
+        /* Find out what is out there */
+        error = pcibr_slot_info_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_INFO_INIT_ERR);
+        }
+
+        /* Set up the address space for this slot in the PCI land */
+        error = pcibr_slot_addr_space_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_ADDR_INIT_ERR);
+        }
+
+        /* Setup the device register */
+        error = pcibr_slot_device_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_DEV_INIT_ERR);
+        }
+
+        /* Setup host/guest relations */
+        error = pcibr_slot_guest_info_init(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_GUEST_INIT_ERR);
+        }
+
+        /* Initial RRB management */
+        error = pcibr_slot_initial_rrb_alloc(pcibr_vhdl, slot);
+        if (error) {
+            if (sub_errorp)
+                *sub_errorp = error;
+            return(PCI_SLOT_RRB_ALLOC_ERR);
+        }
+
+    }
+
+    /* Call the device attach */
+    error = pcibr_slot_call_device_attach(pcibr_vhdl, slot, drv_flags);
+    if (error) {
+        if (sub_errorp)
+            *sub_errorp = error;
+        if (error == EUNATCH)
+            return(PCI_NO_DRIVER);
+        else
+            return(PCI_SLOT_DRV_ATTACH_ERR);
+    }
+
+    return(0);
+}
+#endif	/* LATER */
+
+/*
+ * pcibr_slot_detach
+ *	This is a place holder routine to keep track of all the
+ *	slot-specific freeing that needs to be done.
+ */
+int
+pcibr_slot_detach(devfs_handle_t pcibr_vhdl,
+		  pciio_slot_t slot,
+		  int          drv_flags)
+{
+    int		  error;
+    
+    /* Call the device detach function */
+    error = (pcibr_slot_call_device_detach(pcibr_vhdl, slot, drv_flags));
+    return (error);
+
+}
+
+/*
+ * pcibr_is_slot_sys_critical
+ *      Check slot for any functions that are system critical.
+ *      Return 1 if any are system critical or 0 otherwise.
+ *
+ *      This function will always return 0 when called by 
+ *      pcibr_attach() because the system critical vertices 
+ *      have not yet been set in the hwgraph.
+ */
+int
+pcibr_is_slot_sys_critical(devfs_handle_t pcibr_vhdl,
+                      pciio_slot_t slot)
+{
+    pcibr_soft_t        pcibr_soft;
+    pcibr_info_h        pcibr_infoh;
+    pcibr_info_t        pcibr_info;
+    devfs_handle_t        conn_vhdl = GRAPH_VERTEX_NONE;
+    int                 nfunc;
+    int                 func;
+    boolean_t		is_sys_critical_vertex(devfs_handle_t);
+
+    pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    if (!pcibr_soft || !PCIBR_VALID_SLOT(slot))
+        return(0);
+
+    nfunc = pcibr_soft->bs_slot[slot].bss_ninfo;
+    pcibr_infoh = pcibr_soft->bs_slot[slot].bss_infos;
+
+    for (func = 0; func < nfunc; ++func) {
+
+        pcibr_info = pcibr_infoh[func];
+        if (!pcibr_info)
+            continue;
+
+        if (pcibr_info->f_vendor == PCIIO_VENDOR_ID_NONE)
+            continue;
+
+        conn_vhdl = pcibr_info->f_vertex;
+        if (is_sys_critical_vertex(conn_vhdl)) { 
+#if defined(SUPPORT_PRINTING_V_FORMAT)
+            printk(KERN_WARNING  "%v is a system critical device vertex\n", conn_vhdl);
+#else
+            printk(KERN_WARNING  "%p is a system critical device vertex\n", (void *)conn_vhdl);
+#endif
+            return(1); 
+        }
+
+    }
+
+    return(0);
+}
+
+/*
+ * pcibr_probe_slot: read a config space word
+ * while trapping any errors; reutrn zero if
+ * all went OK, or nonzero if there was an error.
+ * The value read, if any, is passed back
+ * through the valp parameter.
+ */
+int
+pcibr_probe_slot(bridge_t *bridge,
+		 cfg_p cfg,
+		 unsigned *valp)
+{
+    int                     rv;
+    bridgereg_t             old_enable, new_enable;
+    int badaddr_val(volatile void *, int, volatile void *);
+
+    old_enable = bridge->b_int_enable;
+    new_enable = old_enable & ~BRIDGE_IMR_PCI_MST_TIMEOUT;
+
+    bridge->b_int_enable = new_enable;
+
+	/*
+	 * The xbridge doesn't clear b_err_int_view unless
+	 * multi-err is cleared...
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+	    }
+
+    if (bridge->b_int_status & BRIDGE_IRR_PCI_GRP) {
+	bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR;
+	(void) bridge->b_wid_tflush;	/* flushbus */
+    }
+    rv = badaddr_val((void *) cfg, 4, valp);
+
+	/*
+	 * The xbridge doesn't set master timeout in b_int_status
+	 * here.  Fortunately it's in error_interrupt_view.
+	 */
+	if (is_xbridge(bridge))
+	    if (bridge->b_err_int_view & BRIDGE_ISR_PCI_MST_TIMEOUT) {
+		bridge->b_int_rst_stat = BRIDGE_IRR_MULTI_CLR;
+		rv = 1;		/* unoccupied slot */
+	    }
+
+    bridge->b_int_enable = old_enable;
+    bridge->b_wid_tflush;		/* wait until Bridge PIO complete */
+
+    return rv;
+}
+
+void
+pcibr_device_info_free(devfs_handle_t pcibr_vhdl, pciio_slot_t slot)
+{
+    pcibr_soft_t	pcibr_soft = pcibr_soft_get(pcibr_vhdl);
+    pcibr_info_t	pcibr_info;
+    pciio_function_t	func;
+    pcibr_soft_slot_t	slotp = &pcibr_soft->bs_slot[slot];
+    int			nfunc = slotp->bss_ninfo;
+    int                 bar;
+    int                 devio_index;
+    int                 s;
+
+
+    for (func = 0; func < nfunc; func++) {
+	pcibr_info = slotp->bss_infos[func];
+
+	if (!pcibr_info) 
+	    continue;
+
+        s = pcibr_lock(pcibr_soft);
+
+        for (bar = 0; bar < PCI_CFG_BASE_ADDRS; bar++) {
+            if (pcibr_info->f_window[bar].w_space == PCIIO_SPACE_NONE)
+                continue;
+
+            /* Get index of the DevIO(x) register used to access this BAR */
+            devio_index = pcibr_info->f_window[bar].w_devio_index;
+
+ 
+            /* On last use, clear the DevIO(x) used to access this BAR */
+            if (! --pcibr_soft->bs_slot[devio_index].bss_devio.bssd_ref_cnt) {
+               pcibr_soft->bs_slot[devio_index].bss_devio.bssd_space =
+                                                       PCIIO_SPACE_NONE; 
+               pcibr_soft->bs_slot[devio_index].bss_devio.bssd_base =
+                                                       PCIBR_D32_BASE_UNSET;
+               pcibr_soft->bs_slot[devio_index].bss_device = 0;
+            }
+        }
+
+        pcibr_unlock(pcibr_soft, s);
+
+	slotp->bss_infos[func] = 0;
+	pciio_device_info_unregister(pcibr_vhdl, &pcibr_info->f_c);
+	pciio_device_info_free(&pcibr_info->f_c);
+
+	DEL(pcibr_info);
+    }
+
+    /* Reset the mapping usage counters */
+    slotp->bss_pmu_uctr = 0;
+    slotp->bss_d32_uctr = 0;
+    slotp->bss_d64_uctr = 0;
+
+    /* Clear the Direct translation info */
+    slotp->bss_d64_base = PCIBR_D64_BASE_UNSET;
+    slotp->bss_d64_flags = 0;
+    slotp->bss_d32_base = PCIBR_D32_BASE_UNSET;
+    slotp->bss_d32_flags = 0;
+
+    /* Clear out shadow info necessary for the external SSRAM workaround */
+    slotp->bss_ext_ates_active = ATOMIC_INIT(0);
+    slotp->bss_cmd_pointer = 0;
+    slotp->bss_cmd_shadow = 0;
+
+}
diff -Nru a/arch/ia64/sn/io/sn2/shub_intr.c b/arch/ia64/sn/io/sn2/shub_intr.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/shub_intr.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,215 @@
+/* $Id: shub_intr.c,v 1.2 2001/06/26 14:02:43 pfg Exp $
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/sn/types.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/io.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+
+extern void hub_device_desc_update(device_desc_t, ilvl_t, cpuid_t);
+
+/* ARGSUSED */
+void
+hub_intr_init(devfs_handle_t hubv)
+{
+	extern void sn_cpei_handler(int, void *, struct pt_regs *);
+	extern void sn_init_cpei_timer(void);
+
+	if (request_irq(SGI_SHUB_ERROR_VECTOR, sn_cpei_handler, 0, "SN hub error", NULL) ) {
+		printk("hub_intr_init: Couldn't register SGI_SHUB_ERROR_VECTOR = %x\n",SGI_SHUB_ERROR_VECTOR);
+	}
+	sn_init_cpei_timer();
+}
+
+xwidgetnum_t
+hub_widget_id(nasid_t nasid)
+{
+        hubii_wcr_t     ii_wcr; /* the control status register */
+        
+        ii_wcr.wcr_reg_value = REMOTE_HUB_L(nasid,IIO_WCR);
+        
+        return ii_wcr.wcr_fields_s.wcr_widget_id;
+}
+
+static hub_intr_t
+do_hub_intr_alloc(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev,
+		int uncond_nothread)
+{
+	cpuid_t		cpu = 0;
+	int		vector;
+	hub_intr_t	intr_hdl;
+	cnodeid_t	cnode;
+	int		cpuphys, slice;
+	int		nasid;
+	iopaddr_t	xtalk_addr;
+	struct xtalk_intr_s	*xtalk_info;
+	xwidget_info_t	xwidget_info;
+	ilvl_t		intr_swlevel = 0;
+
+	cpu = intr_heuristic(dev, dev_desc, -1, 0, owner_dev, NULL, &vector);
+
+	if (cpu == CPU_NONE) {
+		printk("Unable to allocate interrupt for 0x%p\n", (void *)owner_dev);
+		return(0);
+	}
+
+	cpuphys = cpu_physical_id(cpu);
+	slice = cpu_physical_id_to_slice(cpuphys);
+	nasid = cpu_physical_id_to_nasid(cpuphys);
+	cnode = cpuid_to_cnodeid(cpu);
+
+	if (slice) {
+		xtalk_addr = SH_II_INT1 | GLOBAL_MMR_SPACE |
+			((unsigned long)nasid << 36) | (1UL << 47);
+	} else {
+		xtalk_addr = SH_II_INT0 | GLOBAL_MMR_SPACE |
+			((unsigned long)nasid << 36) | (1UL << 47);
+	}
+
+	intr_hdl = snia_kmem_alloc_node(sizeof(struct hub_intr_s), KM_NOSLEEP, cnode);
+	ASSERT_ALWAYS(intr_hdl);
+
+	xtalk_info = &intr_hdl->i_xtalk_info;
+	xtalk_info->xi_dev = dev;
+	xtalk_info->xi_vector = vector;
+	xtalk_info->xi_addr = xtalk_addr;
+
+	xwidget_info = xwidget_info_get(dev);
+	if (xwidget_info) {
+		xtalk_info->xi_target = xwidget_info_masterid_get(xwidget_info);
+	}
+
+	intr_hdl->i_swlevel = intr_swlevel;
+	intr_hdl->i_cpuid = cpu;
+	intr_hdl->i_bit = vector;
+	intr_hdl->i_flags |= HUB_INTR_IS_ALLOCED;
+
+	hub_device_desc_update(dev_desc, intr_swlevel, cpu);
+	return(intr_hdl);
+}
+
+hub_intr_t
+hub_intr_alloc(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev)
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 0));
+}
+
+hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,
+		device_desc_t dev_desc,
+		devfs_handle_t owner_dev)
+{
+	return(do_hub_intr_alloc(dev, dev_desc, owner_dev, 1));
+}
+
+void
+hub_intr_free(hub_intr_t intr_hdl)
+{
+	cpuid_t		cpu = intr_hdl->i_cpuid;
+	int		vector = intr_hdl->i_bit;
+	xtalk_intr_t	xtalk_info;
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_CONNECTED) {
+		xtalk_info = &intr_hdl->i_xtalk_info;
+		xtalk_info->xi_dev = NODEV;
+		xtalk_info->xi_vector = 0;
+		xtalk_info->xi_addr = 0;
+		hub_intr_disconnect(intr_hdl);
+	}
+
+	if (intr_hdl->i_flags & HUB_INTR_IS_ALLOCED) {
+		kfree(intr_hdl);
+	}
+	intr_unreserve_level(cpu, vector);
+}
+
+int
+hub_intr_connect(hub_intr_t intr_hdl,
+		xtalk_intr_setfunc_t setfunc,
+		void *setfunc_arg)
+{
+	int		rv;
+	cpuid_t		cpu = intr_hdl->i_cpuid;
+	int 		vector = intr_hdl->i_bit;
+
+	ASSERT(intr_hdl->i_flags & HUB_INTR_IS_ALLOCED);
+
+	rv = intr_connect_level(cpu, vector, intr_hdl->i_swlevel, NULL);
+
+	if (rv < 0) {
+		return rv;
+	}
+
+	intr_hdl->i_xtalk_info.xi_setfunc = setfunc;
+	intr_hdl->i_xtalk_info.xi_sfarg = setfunc_arg;
+
+	if (setfunc) {
+		(*setfunc)((xtalk_intr_t)intr_hdl);
+	}
+
+	intr_hdl->i_flags |= HUB_INTR_IS_CONNECTED;
+
+	return 0;
+}
+
+/*
+ * Disassociate handler with the specified interrupt.
+ */
+void
+hub_intr_disconnect(hub_intr_t intr_hdl)
+{
+	/*REFERENCED*/
+	int rv;
+	cpuid_t cpu = intr_hdl->i_cpuid;
+	int bit = intr_hdl->i_bit;
+	xtalk_intr_setfunc_t setfunc;
+
+	setfunc = intr_hdl->i_xtalk_info.xi_setfunc;
+
+	/* TBD: send disconnected interrupts somewhere harmless */
+	if (setfunc) (*setfunc)((xtalk_intr_t)intr_hdl);
+
+	rv = intr_disconnect_level(cpu, bit);
+	ASSERT(rv == 0);
+	intr_hdl->i_flags &= ~HUB_INTR_IS_CONNECTED;
+}
+
+
+/*
+ * Return a hwgraph vertex that represents the CPU currently
+ * targeted by an interrupt.
+ */
+devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl)
+{
+	cpuid_t cpuid = intr_hdl->i_cpuid;
+
+	ASSERT(cpuid != CPU_NONE);
+
+	return(cpuid_to_vertex(cpuid));
+}
diff -Nru a/arch/ia64/sn/io/sn2/shuberror.c b/arch/ia64/sn/io/sn2/shuberror.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/io/sn2/shuberror.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,478 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000,2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <asm/smp.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/labelcl.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/pci/pcibr_private.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/ioerror.h>
+#include <asm/sn/sn2/shubio.h>
+#include <asm/sn/bte.h>
+
+extern void hubni_eint_init(cnodeid_t cnode);
+extern void hubii_eint_init(cnodeid_t cnode);
+extern void hubii_eint_handler (int irq, void *arg, struct pt_regs *ep);
+int hubiio_crb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo);
+int hubiio_prb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo);
+extern void bte_crb_error_handler(devfs_handle_t hub_v, int btenum, int crbnum, ioerror_t *ioe);
+
+extern int maxcpus;
+
+#define HUB_ERROR_PERIOD        (120 * HZ)      /* 2 minutes */
+
+
+void
+hub_error_clear(nasid_t nasid)
+{
+	int i;
+	hubreg_t idsr;
+
+    /*
+     * Make sure spurious write response errors are cleared
+     * (values are from hub_set_prb())
+     */
+    for (i = 0; i <= HUB_WIDGET_ID_MAX - HUB_WIDGET_ID_MIN + 1; i++) {
+        iprb_t prb;
+
+	prb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)));
+
+        /* Clear out some fields */
+        prb.iprb_ovflow = 1;
+        prb.iprb_bnakctr = 0;
+        prb.iprb_anakctr = 0;
+
+        prb.iprb_xtalkctr = 3;  /* approx. PIO credits for the widget */
+
+        REMOTE_HUB_S(nasid, IIO_IOPRB_0 + (i * sizeof(hubreg_t)), prb.iprb_regval);
+    }
+
+    REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, -1);
+    idsr = REMOTE_HUB_L(nasid, IIO_IIDSR);
+    REMOTE_HUB_S(nasid, IIO_IIDSR, (idsr & ~(IIO_IIDSR_SENT_MASK)));
+
+}
+
+
+/*
+ * Function	: hub_error_init
+ * Purpose	: initialize the error handling requirements for a given hub.
+ * Parameters	: cnode, the compact nodeid.
+ * Assumptions	: Called only once per hub, either by a local cpu. Or by a 
+ *			remote cpu, when this hub is headless.(cpuless)
+ * Returns	: None
+ */
+
+void
+hub_error_init(cnodeid_t cnode)
+{
+	nasid_t nasid;
+
+    nasid = cnodeid_to_nasid(cnode);
+    hub_error_clear(nasid);
+
+
+    /*
+     * Now setup the hub ii error interrupt handler.
+     */
+
+    hubii_eint_init(cnode);
+
+    return;
+}
+
+/*
+ * Function	: hubii_eint_init
+ * Parameters	: cnode
+ * Purpose	: to initialize the hub iio error interrupt.
+ * Assumptions	: Called once per hub, by the cpu which will ultimately
+ *			handle this interrupt.
+ * Returns	: None.
+ */
+
+
+void
+hubii_eint_init(cnodeid_t cnode)
+{
+    int			bit, rv;
+    ii_iidsr_u_t    	hubio_eint;
+    hubinfo_t		hinfo; 
+    cpuid_t		intr_cpu;
+    devfs_handle_t 	hub_v;
+    ii_ilcsr_u_t	ilcsr;
+    int bit_pos_to_irq(int bit);
+    int synergy_intr_connect(int bit, int cpuid);
+
+
+    hub_v = (devfs_handle_t)cnodeid_to_vertex(cnode);
+    ASSERT_ALWAYS(hub_v);
+    hubinfo_get(hub_v, &hinfo);
+
+    ASSERT(hinfo);
+    ASSERT(hinfo->h_cnodeid == cnode);
+
+    ilcsr.ii_ilcsr_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ILCSR);
+
+    if ((ilcsr.ii_ilcsr_fld_s.i_llp_stat & 0x2) == 0) {
+	/* 
+	 * HUB II link is not up. 
+	 * Just disable LLP, and don't connect any interrupts.
+	 */
+	ilcsr.ii_ilcsr_fld_s.i_llp_en = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ILCSR, ilcsr.ii_ilcsr_regval);
+	return;
+    }
+    /* Select a possible interrupt target where there is a free interrupt
+     * bit and also reserve the interrupt bit for this IO error interrupt
+     */
+    intr_cpu = intr_heuristic(hub_v,0,-1,0,hub_v,
+			      "HUB IO error interrupt",&bit);
+    if (intr_cpu == CPU_NONE) {
+	printk("hubii_eint_init: intr_reserve_level failed, cnode %d", cnode);
+	return;
+    }
+	
+    rv = intr_connect_level(intr_cpu, bit, 0, NULL);
+    request_irq(bit + (intr_cpu << 8), hubii_eint_handler, 0, "SN hub error", (void *)hub_v);
+    ASSERT_ALWAYS(rv >= 0);
+    hubio_eint.ii_iidsr_regval = 0;
+    hubio_eint.ii_iidsr_fld_s.i_enable = 1;
+    hubio_eint.ii_iidsr_fld_s.i_level = bit;/* Take the least significant bits*/
+    hubio_eint.ii_iidsr_fld_s.i_node = COMPACT_TO_NASID_NODEID(cnode);
+    hubio_eint.ii_iidsr_fld_s.i_pi_id = cpuid_to_subnode(intr_cpu);
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, hubio_eint.ii_iidsr_regval);
+
+}
+
+
+/*ARGSUSED*/
+void
+hubii_eint_handler (int irq, void *arg, struct pt_regs *ep)
+{
+    devfs_handle_t	hub_v;
+    hubinfo_t		hinfo; 
+    ii_wstat_u_t	wstat;
+    hubreg_t		idsr;
+
+
+    /* two levels of casting avoids compiler warning.!! */
+    hub_v = (devfs_handle_t)(long)(arg); 
+    ASSERT(hub_v);
+
+    hubinfo_get(hub_v, &hinfo);
+    
+    /* 
+     * Identify the reason for error. 
+     */
+    wstat.ii_wstat_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_WSTAT);
+
+    if (wstat.ii_wstat_fld_s.w_crazy) {
+	char	*reason;
+	/*
+	 * We can do a couple of things here. 
+	 * Look at the fields TX_MX_RTY/XT_TAIL_TO/XT_CRD_TO to check
+	 * which of these caused the CRAZY bit to be set. 
+	 * You may be able to check if the Link is up really.
+	 */
+	if (wstat.ii_wstat_fld_s.w_tx_mx_rty)
+		reason = "Micro Packet Retry Timeout";
+	else if (wstat.ii_wstat_fld_s.w_xt_tail_to)
+		reason = "Crosstalk Tail Timeout";
+	else if (wstat.ii_wstat_fld_s.w_xt_crd_to)
+		reason = "Crosstalk Credit Timeout";
+	else {
+		hubreg_t	hubii_imem;
+		/*
+		 * Check if widget 0 has been marked as shutdown, or
+		 * if BTE 0/1 has been marked.
+		 */
+		hubii_imem = REMOTE_HUB_L(hinfo->h_nasid, IIO_IMEM);
+		if (hubii_imem & IIO_IMEM_W0ESD)
+			reason = "Hub Widget 0 has been Shutdown";
+		else if (hubii_imem & IIO_IMEM_B0ESD)
+			reason = "BTE 0 has been shutdown";
+		else if (hubii_imem & IIO_IMEM_B1ESD)
+			reason = "BTE 1 has been shutdown";
+		else	reason = "Unknown";
+	
+	}
+	/*
+	 * Note: we may never be able to print this, if the II talking
+	 * to Xbow which hosts the console is dead. 
+	 */
+	printk("Hub %d to Xtalk Link failed (II_ECRAZY) Reason: %s", 
+		hinfo->h_cnodeid, reason);
+    }
+
+    /* 
+     * It's a toss as to which one among PRB/CRB to check first. 
+     * Current decision is based on the severity of the errors. 
+     * IO CRB errors tend to be more severe than PRB errors.
+     *
+     * It is possible for BTE errors to have been handled already, so we
+     * may not see any errors handled here. 
+     */
+    (void)hubiio_crb_error_handler(hub_v, hinfo);
+    (void)hubiio_prb_error_handler(hub_v, hinfo);
+    /*
+     * If we reach here, it indicates crb/prb handlers successfully
+     * handled the error. So, re-enable II to send more interrupt
+     * and return.
+     */
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IECLR, 0xffffff);
+    idsr = REMOTE_HUB_L(hinfo->h_nasid, IIO_IIDSR) & ~IIO_IIDSR_SENT_MASK;
+    REMOTE_HUB_S(hinfo->h_nasid, IIO_IIDSR, idsr);
+}
+
+/*
+ * Free the hub CRB "crbnum" which encountered an error.
+ * Assumption is, error handling was successfully done,
+ * and we now want to return the CRB back to Hub for normal usage.
+ *
+ * In order to free the CRB, all that's needed is to de-allocate it
+ *
+ * Assumption:
+ *      No other processor is mucking around with the hub control register.
+ *      So, upper layer has to single thread this.
+ */
+void
+hubiio_crb_free(hubinfo_t hinfo, int crbnum)
+{
+	ii_icrb0_a_u_t         icrba;
+
+	/*
+	* The hardware does NOT clear the mark bit, so it must get cleared
+	* here to be sure the error is not processed twice.
+	*/
+	icrba.ii_icrb0_a_regval = REMOTE_HUB_L(hinfo->h_nasid, IIO_ICRB_A(crbnum));
+	icrba.a_valid   = 0;
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ICRB_A(crbnum), icrba.ii_icrb0_a_regval);
+	/*
+	* Deallocate the register.
+	*/
+
+	REMOTE_HUB_S(hinfo->h_nasid, IIO_ICDR, (IIO_ICDR_PND | crbnum));
+
+	/*
+	* Wait till hub indicates it's done.
+	*/
+	while (REMOTE_HUB_L(hinfo->h_nasid, IIO_ICDR) & IIO_ICDR_PND)
+		us_delay(1);
+
+}
+
+
+/*
+ * Array of error names  that get logged in CRBs
+ */ 
+char *hubiio_crb_errors[] = {
+	"Directory Error",
+	"CRB Poison Error",
+	"I/O Write Error",
+	"I/O Access Error",
+	"I/O Partial Write Error",
+	"I/O Partial Read Error",
+	"I/O Timeout Error",
+	"Xtalk Error Packet"
+};
+
+/*
+ * hubiio_crb_error_handler
+ *
+ *	This routine gets invoked when a hub gets an error 
+ *	interrupt. So, the routine is running in interrupt context
+ *	at error interrupt level.
+ * Action:
+ *	It's responsible for identifying ALL the CRBs that are marked
+ *	with error, and process them. 
+ *	
+ * 	If you find the CRB that's marked with error, map this to the
+ *	reason it caused error, and invoke appropriate error handler.
+ *
+ *	XXX Be aware of the information in the context register.
+ *
+ * NOTE:
+ *	Use REMOTE_HUB_* macro instead of LOCAL_HUB_* so that the interrupt
+ *	handler can be run on any node. (not necessarily the node 
+ *	corresponding to the hub that encountered error).
+ */
+
+int
+hubiio_crb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo)
+{
+	cnodeid_t	cnode;
+	nasid_t		nasid;
+	ii_icrb0_a_u_t		icrba;		/* II CRB Register A */
+	ii_icrb0_b_u_t		icrbb;		/* II CRB Register B */
+	ii_icrb0_c_u_t		icrbc;		/* II CRB Register C */
+	ii_icrb0_d_u_t		icrbd;		/* II CRB Register D */
+	int		i;
+	int		num_errors = 0;	/* Num of errors handled */
+	ioerror_t	ioerror;
+
+	nasid = hinfo->h_nasid;
+	cnode = NASID_TO_COMPACT_NODEID(nasid);
+
+	/*
+	 * Scan through all CRBs in the Hub, and handle the errors
+	 * in any of the CRBs marked.
+	 */
+	for (i = 0; i < IIO_NUM_CRBS; i++) {
+		icrba.ii_icrb0_a_regval = REMOTE_HUB_L(nasid, IIO_ICRB_A(i));
+
+		IOERROR_INIT(&ioerror);
+
+		/* read other CRB error registers. */
+		icrbb.ii_icrb0_b_regval = REMOTE_HUB_L(nasid, IIO_ICRB_B(i));
+		icrbc.ii_icrb0_c_regval = REMOTE_HUB_L(nasid, IIO_ICRB_C(i));
+		icrbd.ii_icrb0_d_regval = REMOTE_HUB_L(nasid, IIO_ICRB_D(i));
+
+		IOERROR_SETVALUE(&ioerror,errortype,icrbb.b_ecode);
+		/* Check if this error is due to BTE operation,
+		* and handle it separately.
+		*/
+		if (icrbd.d_bteop ||
+			((icrbb.b_initiator == IIO_ICRB_INIT_BTE0 ||
+			icrbb.b_initiator == IIO_ICRB_INIT_BTE1) &&
+			(icrbb.b_imsgtype == IIO_ICRB_IMSGT_BTE ||
+			icrbb.b_imsgtype == IIO_ICRB_IMSGT_SN1NET))){
+
+			int bte_num;
+
+			if (icrbd.d_bteop)
+				bte_num = icrbc.c_btenum;
+			else /* b_initiator bit 2 gives BTE number */
+				bte_num = (icrbb.b_initiator & 0x4) >> 2;
+
+			bte_crb_error_handler(hub_v, bte_num,
+					i, &ioerror);
+			hubiio_crb_free(hinfo, i);
+			num_errors++;
+			continue;
+		}
+
+		/*
+		 * XXX
+		 * Assuming the only other error that would reach here is
+		 * crosstalk errors. 
+		 * If CRB times out on a message from Xtalk, it changes 
+		 * the message type to CRB. 
+		 *
+		 * If we get here due to other errors (SN0net/CRB)
+		 * what's the action ?
+		 */
+
+		/*
+		 * Pick out the useful fields in CRB, and
+		 * tuck them away into ioerror structure.
+		 */
+		IOERROR_SETVALUE(&ioerror,xtalkaddr,icrba.a_addr << IIO_ICRB_ADDR_SHFT);
+		IOERROR_SETVALUE(&ioerror,widgetnum,icrba.a_sidn);
+
+
+		if (icrba.a_iow){
+			/*
+			 * XXX We shouldn't really have BRIDGE-specific code
+			 * here, but alas....
+			 *
+			 * The BRIDGE (or XBRIDGE) sets the upper bit of TNUM
+			 * to indicate a WRITE operation.  It sets the next
+			 * bit to indicate an INTERRUPT operation.  The bottom
+			 * 3 bits of TNUM indicate which device was responsible.
+			 */
+			IOERROR_SETVALUE(&ioerror,widgetdev,
+					 TNUM_TO_WIDGET_DEV(icrba.a_tnum));
+
+		}
+
+	}
+	return	num_errors;
+}
+
+/*ARGSUSED*/
+/*
+ * hubii_prb_handler
+ *      Handle the error reported in the PRB for wiget number wnum.
+ *      This typically happens on a PIO write error.
+ *      There is nothing much we can do in this interrupt context for
+ *      PIO write errors. For e.g. QL scsi controller has the
+ *      habit of flaking out on PIO writes.
+ *      Print a message and try to continue for now
+ *      Cleanup involes freeing the PRB register
+ */
+static void
+hubii_prb_handler(devfs_handle_t hub_v, hubinfo_t hinfo, int wnum)
+{
+        nasid_t         nasid;
+
+        nasid = hinfo->h_nasid;
+        /*
+         * Clear error bit by writing to IECLR register.
+         */
+        REMOTE_HUB_S(nasid, IIO_IO_ERR_CLR, (1 << wnum));
+        /*
+         * PIO Write to Widget 'i' got into an error.
+         * Invoke hubiio_error_handler with this information.
+         */
+        printk( "Hub nasid %d got a PIO Write error from widget %d, cleaning up and continuing",
+                        nasid, wnum);
+        /*
+         * XXX
+         * It may be necessary to adjust IO PRB counter
+         * to account for any lost credits.
+         */
+}
+
+int
+hubiio_prb_error_handler(devfs_handle_t hub_v, hubinfo_t hinfo)
+{
+        int             wnum;
+        nasid_t         nasid;
+        int             num_errors = 0;
+        iprb_t          iprb;
+
+        nasid = hinfo->h_nasid;
+        /*
+         * Check if IPRB0 has any error first.
+         */
+        iprb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB(0));
+        if (iprb.iprb_error) {
+                num_errors++;
+                hubii_prb_handler(hub_v, hinfo, 0);
+        }
+        /*
+         * Look through PRBs 8 - F to see if any of them has error bit set.
+         * If true, invoke hub iio error handler for this widget.
+         */
+        for (wnum = HUB_WIDGET_ID_MIN; wnum <= HUB_WIDGET_ID_MAX; wnum++) {
+                iprb.iprb_regval = REMOTE_HUB_L(nasid, IIO_IOPRB(wnum));
+
+                if (!iprb.iprb_error)
+                        continue;
+
+                num_errors++;
+                hubii_prb_handler(hub_v, hinfo, wnum);
+        }
+
+        return num_errors;
+}
+
diff -Nru a/arch/ia64/sn/io/stubs.c b/arch/ia64/sn/io/stubs.c
--- a/arch/ia64/sn/io/stubs.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/stubs.c	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -21,6 +20,7 @@
 #include <asm/sn/pci/pciio.h>
 #include <asm/sn/slotnum.h>
 #include <asm/sn/vector.h>
+#include <asm/sn/nic.h>
 
 /******
  ****** hack defines ......
@@ -61,45 +61,45 @@
 }
 
 void *
-kmem_alloc_node(register size_t size, register int flags, cnodeid_t node)
+snia_kmem_alloc_node(register size_t size, register int flags, cnodeid_t node)
 {
         /* Allocates on node 'node' */
-	FIXME("kmem_alloc_node : use kmalloc");
+	FIXME("snia_kmem_alloc_node : use kmalloc");
 	return(kmalloc(size, GFP_KERNEL));
 }
 
 void *
-kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node)
+snia_kmem_zalloc_node(register size_t size, register int flags, cnodeid_t node)
 {
-	FIXME("kmem_zalloc_node : use kmalloc");
+	FIXME("snia_kmem_zalloc_node : use kmalloc");
 	return(kmalloc(size, GFP_KERNEL));
 }
 
 void
-kmem_free(void *where, int size)
+snia_kmem_free(void *where, int size)
 {
-	FIXME("kmem_free : use kfree");
+	FIXME("snia_kmem_free : use kfree");
 	return(kfree(where));
 }
 
 
 void *
-kmem_zone_alloc(register zone_t *zone, int flags)
+snia_kmem_zone_alloc(register zone_t *zone, int flags)
 {
-	FIXME("kmem_zone_alloc : return null");
+	FIXME("snia_kmem_zone_alloc : return null");
 	return((void *)0);
 }
 
 void
-kmem_zone_free(register zone_t *zone, void *ptr)
+snia_kmem_zone_free(register zone_t *zone, void *ptr)
 {
-	FIXME("kmem_zone_free : no-op");
+	FIXME("snia_kmem_zone_free : no-op");
 }
 
 zone_t *
-kmem_zone_init(register int size, char *zone_name)
+snia_kmem_zone_init(register int size, char *zone_name)
 {
-	FIXME("kmem_zone_free : returns NULL");
+	FIXME("snia_kmem_zone_free : returns NULL");
 	return((zone_t *)0);
 }
 
diff -Nru a/arch/ia64/sn/io/xbow.c b/arch/ia64/sn/io/xbow.c
--- a/arch/ia64/sn/io/xbow.c	Fri Mar 15 17:51:00 2002
+++ b/arch/ia64/sn/io/xbow.c	Fri Mar 15 17:51:00 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
@@ -19,6 +18,7 @@
 #include <asm/sn/hack.h>
 #include <asm/sn/pci/bridge.h>
 #include <asm/sn/xtalk/xtalk_private.h>
+#include <asm/sn/simulator.h>
 
 /* #define DEBUG		1 */
 /* #define XBOW_DEBUG	1 */
@@ -102,7 +102,6 @@
 #ifdef LATER
 static void             xbow_setwidint(xtalk_intr_t);
 static void             xbow_errintr_handler(intr_arg_t);
-static error_handler_f  xbow_error_handler;
 #endif
 void                    xbow_intr_preset(void *, int, xwidgetnum_t, iopaddr_t, xtalk_intr_vector_t);
 
@@ -281,7 +280,7 @@
                         /* &hcl_fops */ (void *)&vhdl, NULL);
     if (!vhdl) {
         printk(KERN_WARNING "xbow_attach: Unable to create char device for xbow conn %p\n",
-                conn);
+                (void *)conn);
     }
 
     /*
@@ -306,7 +305,7 @@
 
     /*
      * get the name of this xbow vertex and keep the info.
-     * This is needed during errors and interrupts, but as
+     * This is needed during errors and interupts, but as
      * long as we have it, we can use it elsewhere.
      */
     s = dev_to_name(vhdl, devnm, MAXDEVNAME);
@@ -371,36 +370,9 @@
     }
 
     /*
-     * attach the crossbow error interrupt.
-     */
-#ifdef LATER
-    dev_desc = device_desc_dup(vhdl);
-    device_desc_flags_set(dev_desc,
-			  device_desc_flags_get(dev_desc) | D_INTR_ISERR);
-    device_desc_intr_name_set(dev_desc, "Crossbow error");
-
-    intr_hdl = xtalk_intr_alloc(conn, dev_desc, vhdl);
-    ASSERT(intr_hdl != NULL);
-
-    xtalk_intr_connect(intr_hdl,
-		       (intr_func_t) xbow_errintr_handler,
-		       (intr_arg_t) soft,
-		       (xtalk_intr_setfunc_t) xbow_setwidint,
-		       (void *) xbow,
-		       (void *) 0);
-    device_desc_free(dev_desc);
-
-    xwidget_error_register(conn, xbow_error_handler, soft);
-
-#else
-    FIXME("xbow_attach: Fixme: we bypassed attaching xbow error interrupt.\n");
-#endif /* LATER */
-
-    /*
      * Enable xbow error interrupts
      */
-    xbow->xb_wid_control = (XB_WID_CTRL_REG_ACC_IE |
-			    XB_WID_CTRL_XTALK_IE);
+    xbow->xb_wid_control = (XB_WID_CTRL_REG_ACC_IE | XB_WID_CTRL_XTALK_IE);
 
     /*
      * take a census of the widgets present,
@@ -918,460 +890,6 @@
     return 1;
 }
 
-/*
- * xbow_errintr_handler will be called if the xbow
- * sends an interrupt request to report an error.
- */
-
-#ifdef LATER
-static void
-xbow_errintr_handler(intr_arg_t arg)
-{
-    ioerror_t               ioe[1];
-    xbow_soft_t             soft = (xbow_soft_t) arg;
-    xbow_t                 *xbow = soft->base;
-    xbowreg_t               wid_control;
-    xbowreg_t               wid_stat;
-    xbowreg_t               wid_err_cmdword;
-    xbowreg_t               wid_err_upper;
-    xbowreg_t               wid_err_lower;
-    w_err_cmd_word_u        wid_err;
-    uint64_t                 wid_err_addr;
-
-    int                     fatal = 0;
-    int                     dump_ioe = 0;
-
-    wid_control = xbow->xb_wid_control;
-    wid_stat = xbow->xb_wid_stat_clr;
-    wid_err_cmdword = xbow->xb_wid_err_cmdword;
-    wid_err_upper = xbow->xb_wid_err_upper;
-    wid_err_lower = xbow->xb_wid_err_lower;
-    xbow->xb_wid_err_cmdword = 0;
-
-    wid_err_addr =
-	wid_err_lower
-	| (((iopaddr_t) wid_err_upper
-	    & WIDGET_ERR_UPPER_ADDR_ONLY)
-	   << 32);
-
-    if (wid_stat & XB_WID_STAT_LINK_INTR_MASK) {
-	int                     port;
-
-	wid_err.r = wid_err_cmdword;
-
-	for (port = MAX_PORT_NUM - MAX_XBOW_PORTS;
-	     port < MAX_PORT_NUM; port++) {
-	    if (wid_stat & XB_WID_STAT_LINK_INTR(port)) {
-		xb_linkregs_t          *link = &(xbow->xb_link(port));
-		xbowreg_t               link_control = link->link_control;
-		xbowreg_t               link_status = link->link_status_clr;
-		xbowreg_t               link_aux_status = link->link_aux_status;
-		xbowreg_t               link_pend;
-
-		link_pend = link_status & link_control &
-		    (XB_STAT_ILLEGAL_DST_ERR
-		     | XB_STAT_OALLOC_IBUF_ERR
-		     | XB_STAT_RCV_CNT_OFLOW_ERR
-		     | XB_STAT_XMT_CNT_OFLOW_ERR
-		     | XB_STAT_XMT_MAX_RTRY_ERR
-		     | XB_STAT_RCV_ERR
-		     | XB_STAT_XMT_RTRY_ERR
-		     | XB_STAT_MAXREQ_TOUT_ERR
-		     | XB_STAT_SRC_TOUT_ERR
-		    );
-
-		if (link_pend & XB_STAT_ILLEGAL_DST_ERR) {
-		    if (wid_err.f.sidn == port) {
-			IOERROR_INIT(ioe);
-			IOERROR_SETVALUE(ioe, widgetnum, port);
-			IOERROR_SETVALUE(ioe, xtalkaddr, wid_err_addr);
-			if (IOERROR_HANDLED ==
-			    xbow_error_handler(soft,
-					       IOECODE_DMA,
-					       MODE_DEVERROR,
-					       ioe)) {
-			    link_pend &= ~XB_STAT_ILLEGAL_DST_ERR;
-			} else {
-			    dump_ioe++;
-			}
-		    }
-		}
-		/* Xbow/Bridge WAR:
-		 * if the bridge signals an LLP Transmitter Retry,
-		 * rewrite its control register.
-		 * If someone else triggers this interrupt,
-		 * ignore (and disable) the interrupt.
-		 */
-		if (link_pend & XB_STAT_XMT_RTRY_ERR) {
-		    if (!xbow_xmit_retry_error(soft, port)) {
-			link_control &= ~XB_CTRL_XMT_RTRY_IE;
-			link->link_control = link_control;
-			link->link_control;	/* stall until written */
-		    }
-		    link_pend &= ~XB_STAT_XMT_RTRY_ERR;
-		}
-		if (link_pend) {
-		    devfs_handle_t	xwidget_vhdl;
-		    char		*xwidget_name;
-		    
-		    /* Get the widget name corresponding to the current
-		     * xbow link.
-		     */
-		    xwidget_vhdl = xbow_widget_lookup(soft->busv,port);
-		    xwidget_name = xwidget_name_get(xwidget_vhdl);
-
-#ifdef	LATER
-		    printk("%s port %X[%s] XIO Bus Error",
-			    soft->name, port, xwidget_name);
-		    if (link_status & XB_STAT_MULTI_ERR)
-			XEM_ADD_STR("\tMultiple Errors\n");
-		    if (link_status & XB_STAT_ILLEGAL_DST_ERR)
-			XEM_ADD_STR("\tInvalid Packet Destination\n");
-		    if (link_status & XB_STAT_OALLOC_IBUF_ERR)
-			XEM_ADD_STR("\tInput Overallocation Error\n");
-		    if (link_status & XB_STAT_RCV_CNT_OFLOW_ERR)
-			XEM_ADD_STR("\tLLP receive error counter overflow\n");
-		    if (link_status & XB_STAT_XMT_CNT_OFLOW_ERR)
-			XEM_ADD_STR("\tLLP transmit retry counter overflow\n");
-		    if (link_status & XB_STAT_XMT_MAX_RTRY_ERR)
-			XEM_ADD_STR("\tLLP Max Transmitter Retry\n");
-		    if (link_status & XB_STAT_RCV_ERR)
-			XEM_ADD_STR("\tLLP Receiver error\n");
-		    if (link_status & XB_STAT_XMT_RTRY_ERR)
-			XEM_ADD_STR("\tLLP Transmitter Retry\n");
-		    if (link_status & XB_STAT_MAXREQ_TOUT_ERR)
-			XEM_ADD_STR("\tMaximum Request Timeout\n");
-		    if (link_status & XB_STAT_SRC_TOUT_ERR)
-			XEM_ADD_STR("\tSource Timeout Error\n");
-#endif	/* LATER */
-		    {
-			int                     other_port;
-
-			for (other_port = 8; other_port < 16; ++other_port) {
-			    if (link_aux_status & (1 << other_port)) {
-				/* XXX- need to go to "other_port"
-				 * and clean up after the timeout?
-				 */
-				XEM_ADD_VAR(other_port);
-			    }
-			}
-		    }
-
-#if !DEBUG
-		    if (kdebug) {
-#endif
-			XEM_ADD_VAR(link_control);
-			XEM_ADD_VAR(link_status);
-			XEM_ADD_VAR(link_aux_status);
-
-			if (dump_ioe) {
-			    XEM_ADD_IOE();
-			    dump_ioe = 0;
-			}
-#if !DEBUG
-		    }
-#endif
-		    fatal++;
-		}
-	    }
-	}
-    }
-    if (wid_stat & wid_control & XB_WID_STAT_WIDGET0_INTR) {
-	/* we have a "widget zero" problem */
-
-	if (wid_stat & (XB_WID_STAT_MULTI_ERR
-			| XB_WID_STAT_XTALK_ERR
-			| XB_WID_STAT_REG_ACC_ERR)) {
-
-	    printk("%s Port 0 XIO Bus Error",
-		    soft->name);
-	    if (wid_stat & XB_WID_STAT_MULTI_ERR)
-		XEM_ADD_STR("\tMultiple Error\n");
-	    if (wid_stat & XB_WID_STAT_XTALK_ERR)
-		XEM_ADD_STR("\tXIO Error\n");
-	    if (wid_stat & XB_WID_STAT_REG_ACC_ERR)
-		XEM_ADD_STR("\tRegister Access Error\n");
-
-	    fatal++;
-	}
-    }
-    if (fatal) {
-	XEM_ADD_VAR(wid_stat);
-	XEM_ADD_VAR(wid_control);
-	XEM_ADD_VAR(wid_err_cmdword);
-	XEM_ADD_VAR(wid_err_upper);
-	XEM_ADD_VAR(wid_err_lower);
-	XEM_ADD_VAR(wid_err_addr);
-	PRINT_PANIC("XIO Bus Error");
-    }
-}
-#endif	/* LATER */
-
-/*
- * XBOW ERROR Handling routines.
- * These get invoked as part of walking down the error handling path
- * from hub/heart towards the I/O device that caused the error.
- */
-
-/*
- * xbow_error_handler
- *      XBow error handling dispatch routine.
- *      This is the primary interface used by external world to invoke
- *      in case of an error related to a xbow.
- *      Only functionality in this layer is to identify the widget handle
- *      given the widgetnum. Otherwise, xbow does not gathers any error
- *      data.
- */
-
-#ifdef LATER
-static int
-xbow_error_handler(
-		      void *einfo,
-		      int error_code,
-		      ioerror_mode_t mode,
-		      ioerror_t *ioerror)
-{
-    int                     retval = IOERROR_WIDGETLEVEL;
-
-    xbow_soft_t             soft = (xbow_soft_t) einfo;
-    int                     port;
-    devfs_handle_t            conn;
-    devfs_handle_t            busv;
-
-    xbow_t                 *xbow = soft->base;
-    xbowreg_t               wid_stat;
-    xbowreg_t               wid_err_cmdword;
-    xbowreg_t               wid_err_upper;
-    xbowreg_t               wid_err_lower;
-    uint64_t                 wid_err_addr;
-
-    xb_linkregs_t          *link;
-    xbowreg_t               link_control;
-    xbowreg_t               link_status;
-    xbowreg_t               link_aux_status;
-
-    ASSERT(soft != 0);
-    busv = soft->busv;
-
-#if DEBUG && ERROR_DEBUG
-    printk("%s: xbow_error_handler\n", soft->name, busv);
-#endif
-
-    port = IOERROR_GETVALUE(ioerror, widgetnum);
-
-    if (port == 0) {
-	/* error during access to xbow:
-	 * do NOT attempt to access xbow regs.
-	 */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on Crossbow at %s\n"
-		    "\tbut Crosbow never initiates DMA!",
-		    soft->name);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERt("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO controller\n"
-		    "\twith offset 0x%X",
-		    soft->name,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-	/* caller will dump contents of ioerror
-	 * in DEBUG and kdebug kernels.
-	 */
-
-	return retval;
-    }
-    /*
-     * error not on port zero:
-     * safe to read xbow registers.
-     */
-    wid_stat = xbow->xb_wid_stat;
-    wid_err_cmdword = xbow->xb_wid_err_cmdword;
-    wid_err_upper = xbow->xb_wid_err_upper;
-    wid_err_lower = xbow->xb_wid_err_lower;
-
-    wid_err_addr =
-	wid_err_lower
-	| (((iopaddr_t) wid_err_upper
-	    & WIDGET_ERR_UPPER_ADDR_ONLY)
-	   << 32);
-
-    if ((port < BASE_XBOW_PORT) ||
-	(port >= MAX_PORT_NUM)) {
-
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on XIO port at %s/%d\n"
-		    "\tbut Crossbow does not support that port",
-		    soft->name, port);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERT("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO port %d\n"
-		    "\t(which Crossbow does not support)"
-		    "\twith offset 0x%X",
-		    soft->name, port,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-#if !DEBUG
-	if (kdebug) {
-#endif
-	    XEM_ADD_STR("Raw status values for Crossbow:\n");
-	    XEM_ADD_VAR(wid_stat);
-	    XEM_ADD_VAR(wid_err_cmdword);
-	    XEM_ADD_VAR(wid_err_upper);
-	    XEM_ADD_VAR(wid_err_lower);
-	    XEM_ADD_VAR(wid_err_addr);
-#if !DEBUG
-	}
-#endif
-
-	/* caller will dump contents of ioerror
-	 * in DEBUG and kdebug kernels.
-	 */
-
-	return retval;
-    }
-    /* access to valid port:
-     * ok to check port status.
-     */
-
-    link = &(xbow->xb_link(port));
-    link_control = link->link_control;
-    link_status = link->link_status;
-    link_aux_status = link->link_aux_status;
-
-    /* Check that there is something present
-     * in that XIO port.
-     */
-    if (!(link_aux_status & XB_AUX_STAT_PRESENT)) {
-	/* nobody connected. */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	if (error_code & IOECODE_DMA) {
-	    PRINT_ALERT("DMA error blamed on XIO port at %s/%d\n"
-		    "\tbut there is no device connected there.",
-		    soft->name, port);
-	}
-	if (error_code & IOECODE_PIO) {
-	    PRINT_ALERT("PIO Error on XIO Bus %s\n"
-		    "\tattempting to access XIO port %d\n"
-		    "\t(which has no device connected)"
-		    "\twith offset 0x%X",
-		    soft->name, port,
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-#if !DEBUG
-	if (kdebug) {
-#endif
-	    XEM_ADD_STR("Raw status values for Crossbow:\n");
-	    XEM_ADD_VAR(wid_stat);
-	    XEM_ADD_VAR(wid_err_cmdword);
-	    XEM_ADD_VAR(wid_err_upper);
-	    XEM_ADD_VAR(wid_err_lower);
-	    XEM_ADD_VAR(wid_err_addr);
-	    XEM_ADD_VAR(port);
-	    XEM_ADD_VAR(link_control);
-	    XEM_ADD_VAR(link_status);
-	    XEM_ADD_VAR(link_aux_status);
-#if !DEBUG
-	}
-#endif
-	return retval;
-
-    }
-    /* Check that the link is alive.
-     */
-    if (!(link_status & XB_STAT_LINKALIVE)) {
-	/* nobody connected. */
-	if (mode == MODE_DEVPROBE)
-	    return IOERROR_HANDLED;
-
-	PRINT_ALERT("%s%sError on XIO Bus %s port %d",
-		(error_code & IOECODE_DMA) ? "DMA " : "",
-		(error_code & IOECODE_PIO) ? "PIO " : "",
-		soft->name, port);
-
-	if ((error_code & IOECODE_PIO) &&
-	    (IOERROR_FIELDVALID(ioerror, xtalkaddr))) {
-	    printk("\tAccess attempted to offset 0x%X\n",
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-	if (link_aux_status & XB_AUX_LINKFAIL_RST_BAD)
-	    XEM_ADD_STR("\tLink never came out of reset\n");
-	else
-	    XEM_ADD_STR("\tLink failed while transferring data\n");
-
-    }
-    /* get the connection point for the widget
-     * involved in this error; if it exists and
-     * is not our connectpoint, cycle back through
-     * xtalk_error_handler to deliver control to
-     * the proper handler (or to report a generic
-     * crosstalk error).
-     *
-     * If the downstream handler won't handle
-     * the problem, we let our upstream caller
-     * deal with it, after (in DEBUG and kdebug
-     * kernels) dumping the xbow state for this
-     * port.
-     */
-    conn = xbow_widget_lookup(busv, port);
-    if ((conn != GRAPH_VERTEX_NONE) &&
-	(conn != soft->conn)) {
-	retval = xtalk_error_handler(conn, error_code, mode, ioerror);
-	if (retval == IOERROR_HANDLED)
-	    return IOERROR_HANDLED;
-    }
-    if (mode == MODE_DEVPROBE)
-	return IOERROR_HANDLED;
-
-    if (retval == IOERROR_UNHANDLED) {
-	retval = IOERROR_PANIC;
-
-	PRINT_ALERT("%s%sError on XIO Bus %s port %d",
-		(error_code & IOECODE_DMA) ? "DMA " : "",
-		(error_code & IOECODE_PIO) ? "PIO " : "",
-		soft->name, port);
-
-	if ((error_code & IOECODE_PIO) &&
-	    (IOERROR_FIELDVALID(ioerror, xtalkaddr))) {
-	    printk("\tAccess attempted to offset 0x%X\n",
-		    IOERROR_GETVALUE(ioerror, xtalkaddr));
-	}
-    }
-
-#if !DEBUG
-    if (kdebug) {
-#endif
-	XEM_ADD_STR("Raw status values for Crossbow:\n");
-	XEM_ADD_VAR(wid_stat);
-	XEM_ADD_VAR(wid_err_cmdword);
-	XEM_ADD_VAR(wid_err_upper);
-	XEM_ADD_VAR(wid_err_lower);
-	XEM_ADD_VAR(wid_err_addr);
-	XEM_ADD_VAR(port);
-	XEM_ADD_VAR(link_control);
-	XEM_ADD_VAR(link_status);
-	XEM_ADD_VAR(link_aux_status);
-#if !DEBUG
-    }
-#endif
-    /* caller will dump raw ioerror data
-     * in DEBUG and kdebug kernels.
-     */
-
-    return retval;
-}
-
-#endif	/* LATER */
-
 void
 xbow_update_perf_counters(devfs_handle_t vhdl)
 {
@@ -1520,7 +1038,7 @@
 
 	if (lnk_sts.linkstatus & ~(XB_STAT_RCV_ERR | XB_STAT_XMT_RTRY_ERR | XB_STAT_LINKALIVE)) {
 #ifdef	LATER
-	    PRINT_WARNING("link %d[%s]: bad status 0x%x\n",
+	    printk(KERN_WARNING  "link %d[%s]: bad status 0x%x\n",
 		    link, xwidget_name, lnk_sts.linkstatus);
 #endif
 	}
diff -Nru a/arch/ia64/sn/io/xswitch.c b/arch/ia64/sn/io/xswitch.c
--- a/arch/ia64/sn/io/xswitch.c	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/sn/io/xswitch.c	Fri Mar 15 17:51:02 2002
@@ -4,14 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
diff -Nru a/arch/ia64/sn/io/xtalk.c b/arch/ia64/sn/io/xtalk.c
--- a/arch/ia64/sn/io/xtalk.c	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/io/xtalk.c	Fri Mar 15 17:51:01 2002
@@ -4,24 +4,22 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/io.h>
 #include <asm/sn/iograph.h>
 #include <asm/sn/invent.h>
 #include <asm/sn/hcl.h>
 #include <asm/sn/labelcl.h>
 #include <asm/sn/hcl_util.h>
-
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/xtalk/xswitch.h>
 #include <asm/sn/xtalk/xwidget.h>
-
 #include <asm/sn/xtalk/xtalk_private.h>
 
 /*
@@ -41,7 +39,6 @@
 
 cdl_p                   xtalk_registry = NULL;
 
-#include <asm/sn/agent.h>
 #define	DEV_FUNC(dev,func)	hub_##func
 #define	CAST_PIOMAP(x)		((hub_piomap_t)(x))
 #define	CAST_DMAMAP(x)		((hub_dmamap_t)(x))
@@ -72,7 +69,7 @@
 xtalk_intr_t            xtalk_intr_alloc(devfs_handle_t, device_desc_t, devfs_handle_t);
 xtalk_intr_t            xtalk_intr_alloc_nothd(devfs_handle_t, device_desc_t, devfs_handle_t);
 void                    xtalk_intr_free(xtalk_intr_t);
-int                     xtalk_intr_connect(xtalk_intr_t, intr_func_t, intr_arg_t, xtalk_intr_setfunc_t, void *, void *);
+int                     xtalk_intr_connect(xtalk_intr_t, xtalk_intr_setfunc_t, void *);
 void                    xtalk_intr_disconnect(xtalk_intr_t);
 devfs_handle_t            xtalk_intr_cpu_get(xtalk_intr_t);
 int                     xtalk_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
@@ -113,8 +110,6 @@
 					 xwidgetnum_t, devfs_handle_t, 
 					 xwidgetnum_t, async_attach_t);
 int			xwidget_unregister(devfs_handle_t);
-void                    xwidget_error_register(devfs_handle_t, error_handler_f *,
-					       error_handler_arg_t);
 void                    xwidget_reset(devfs_handle_t);
 char			*xwidget_name_get(devfs_handle_t);
 #if !defined(DEV_FUNC)
@@ -472,14 +467,11 @@
  */
 int
 xtalk_intr_connect(xtalk_intr_t intr_hdl,	/* xtalk intr resource handle */
-		   intr_func_t intr_func,	/* xtalk intr handler */
-		   intr_arg_t intr_arg,		/* arg to intr handler */
 		   xtalk_intr_setfunc_t setfunc,	/* func to set intr hw */
-		   void *setfunc_arg,	/* arg to setfunc */
-		   void *thread)
-{				/* intr thread to use */
+		   void *setfunc_arg)	/* arg to setfunc */
+{
     return INTR_FUNC(intr_hdl, intr_connect)
-	(CAST_INTR(intr_hdl), intr_func, intr_arg, setfunc, setfunc_arg, thread);
+	(CAST_INTR(intr_hdl), setfunc, setfunc_arg);
 }
 
 
@@ -506,85 +498,6 @@
 }
 
 
-/*
- * =====================================================================
- *                      ERROR MANAGEMENT
- */
-
-/*
- * xtalk_error_handler:
- * pass this error on to the handler registered
- * at the specified xtalk connecdtion point,
- * or complain about it here if there is no handler.
- *
- * This routine plays two roles during error delivery
- * to most widgets: first, the external agent (heart,
- * hub, or whatever) calls in with the error and the
- * connect point representing the crosstalk switch,
- * or whatever crosstalk device is directly connected
- * to the agent.
- *
- * If there is a switch, it will generally look at the
- * widget number stashed in the ioerror structure; and,
- * if the error came from some widget other than the
- * switch, it will call back into xtalk_error_handler
- * with the connection point of the offending port.
- */
-int
-xtalk_error_handler(
-		       devfs_handle_t xconn,
-		       int error_code,
-		       ioerror_mode_t mode,
-		       ioerror_t *ioerror)
-{
-    xwidget_info_t          xwidget_info;
-
-#if DEBUG && ERROR_DEBUG
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    printk("%v: xtalk_error_handler\n", xconn);
-#else
-    printk("%x: xtalk_error_handler\n", xconn);
-#endif
-#endif
-
-    xwidget_info = xwidget_info_get(xconn);
-    /* Make sure that xwidget_info is a valid pointer before derefencing it.
-     * We could come in here during very early initialization. 
-     */
-    if (xwidget_info && xwidget_info->w_efunc)
-	return xwidget_info->w_efunc
-	    (xwidget_info->w_einfo,
-	     error_code, mode, ioerror);
-    /*
-     * no error handler registered for
-     * the offending port. it's not clear
-     * what needs to be done, but reporting
-     * it would be a good thing, unless it
-     * is a mode that requires nothing.
-     */
-    if ((mode == MODE_DEVPROBE) || (mode == MODE_DEVUSERERROR) ||
-	(mode == MODE_DEVREENABLE))
-	return IOERROR_HANDLED;
-
-#ifdef	LATER
-#ifdef SUPPORT_PRINTING_V_FORMAT
-    PRINT_WARNING("Xbow at %v encountered Fatal error", xconn);
-#else
-    PRINT_WARNING("Xbow at %x encountered Fatal error", xconn);
-#endif
-#endif	/* LATER */
-    ioerror_dump("xtalk", error_code, mode, ioerror);
-
-    return IOERROR_UNHANDLED;
-}
-
-int
-xtalk_error_devenable(devfs_handle_t xconn_vhdl, int devnum, int error_code)
-{
-    return DEV_FUNC(xconn_vhdl, error_devenable) (xconn_vhdl, devnum, error_code);
-}
-
-
 /* =====================================================================
  *                    CONFIGURATION MANAGEMENT
  */
@@ -977,7 +890,7 @@
     widget_info->w_einfo = 0;
     /*
      * get the name of this xwidget vertex and keep the info.
-     * This is needed during errors and interrupts, but as
+     * This is needed during errors and interupts, but as
      * long as we have it, we can use it elsewhere.
      */
     s = dev_to_name(widget,devnm,MAXDEVNAME);
@@ -1038,19 +951,6 @@
     return(0);
 }
 
-void
-xwidget_error_register(devfs_handle_t xwidget,
-		       error_handler_f *efunc,
-		       error_handler_arg_t einfo)
-{
-    xwidget_info_t          xwidget_info;
-
-    xwidget_info = xwidget_info_get(xwidget);
-    ASSERT(xwidget_info != NULL);
-    xwidget_info->w_efunc = efunc;
-    xwidget_info->w_einfo = einfo;
-}
-
 /*
  * Issue a link reset to a widget.
  */
@@ -1120,17 +1020,5 @@
 
 	xwidget_unregister(widget_vhdl);
 	
-	return(0);
-}
-/*
- * xtalk_device_inquiry
- *	Find out hardware information about the xtalk widget.
- */
-int
-xtalk_device_inquiry(devfs_handle_t xbus_vhdl, xwidgetnum_t widget)
-{
-
-	extern void hub_device_inquiry(devfs_handle_t, xwidgetnum_t);
-	hub_device_inquiry(xbus_vhdl, widget);
 	return(0);
 }
diff -Nru a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/Makefile	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,62 @@
+# arch/ia64/sn/Makefile
+#
+# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
+#
+# This program is free software; you can redistribute it and/or modify it 
+# under the terms of version 2 of the GNU General Public License 
+# as published by the Free Software Foundation.
+# 
+# This program is distributed in the hope that it would be useful, but 
+# WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+# 
+# Further, this software is distributed without any warranty that it is 
+# free of the rightful claim of any third person regarding infringement 
+# or the like.  Any license provided herein, whether implied or 
+# otherwise, applies only to this software file.  Patent licenses, if 
+# any, provided herein do not apply to combinations of this program with 
+# other software, or any other product whatsoever.
+# 
+# You should have received a copy of the GNU General Public 
+# License along with this program; if not, write the Free Software 
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+# 
+# Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+# Mountain View, CA  94043, or:
+# 
+# http://www.sgi.com 
+# 
+# For further information regarding this notice, see: 
+# 
+# http://oss.sgi.com/projects/GenInfo/NoticeExplan
+#
+
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+O_TARGET        = sn.o
+
+ifeq ($(CONFIG_MODULES),y)
+export-objs = sn_ksyms.o
+endif
+
+subdir-$(CONFIG_IA64_SGI_SN1)	= sn1
+subdir-$(CONFIG_IA64_SGI_SN2)	= sn2
+
+obj-y		= probe.o setup.o sn_asm.o sv.o bte.o
+obj-$(CONFIG_IA64_SGI_SN1)      += irq.o mca.o
+obj-$(CONFIG_IA64_SGI_SN2)      += irq.o mca.o
+
+obj-$(CONFIG_IA64_SGI_SN1)      += sn1/sn1.a  
+obj-$(CONFIG_IA64_SGI_SN2)      += sn2/sn2.a  
+
+obj-$(CONFIG_IA64_SGI_AUTOTEST) += llsc4.o misctest.o
+obj-$(CONFIG_IA64_GENERIC)      += machvec.o
+obj-$(CONFIG_MODULES)           += sn_ksyms.o
+
+
+include $(TOPDIR)/Rules.make
diff -Nru a/arch/ia64/sn/kernel/bte.c b/arch/ia64/sn/kernel/bte.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/bte.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,244 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <asm/sn/nodepda.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pda.h>
+#include <asm/nodedata.h>
+
+#include <linux/string.h>
+#include <linux/sched.h>
+
+#include <asm/sn/bte_copy.h>
+
+int bte_offsets[] = { IIO_IBLS0, IIO_IBLS1 };
+
+/*
+ * bte_init_node(nodepda, cnode)
+ *
+ * Initialize the nodepda structure with BTE base addresses and
+ * spinlocks.
+ *
+ */
+void
+bte_init_node(nodepda_t * mynodepda, cnodeid_t cNode)
+{
+	int i;
+
+	/*
+	 * Indicate that all the block transfer engines on this node
+	 * are available.
+	 */
+	for (i = 0; i < BTES_PER_NODE; i++) {
+#ifdef CONFIG_IA64_SGI_SN2
+		/* >>> Don't know why the 0x1800000L is here.  Robin */
+		mynodepda->node_bte_info[i].bte_base_addr =
+		    (char *)LOCAL_MMR_ADDR(bte_offsets[i] | 0x1800000L);
+#elif CONFIG_IA64_SGI_SN1
+		mynodepda->node_bte_info[i].bte_base_addr =
+		    (char *)LOCAL_HUB_ADDR(bte_offsets[i]);
+#else
+#error BTE Not defined for this hardware platform.
+#endif
+
+#ifdef CONFIG_IA64_SGI_BTE_LOCKING
+		/* Initialize the notification and spinlock */
+		/* so the first transfer can occur. */
+		mynodepda->node_bte_info[i].mostRecentNotification =
+		    &(mynodepda->node_bte_info[i].notify);
+		mynodepda->node_bte_info[i].notify = 0L;
+		spin_lock_init(&mynodepda->node_bte_info[i].spinlock);
+#endif				/* CONFIG_IA64_SGI_BTE_LOCKING */
+
+	}
+}
+
+/*
+ * bte_init_cpu()
+ *
+ * Initialize the cpupda structure with pointers to the
+ * nodepda bte blocks.
+ *
+ */
+void
+bte_init_cpu(void)
+{
+	/* Called by setup.c as each cpu is being added to the nodepda */
+	if (local_node_data->active_cpu_count & 0x1) {
+		pda.cpubte[0] = &(nodepda->node_bte_info[0]);
+		pda.cpubte[1] = &(nodepda->node_bte_info[1]);
+	} else {
+		pda.cpubte[0] = &(nodepda->node_bte_info[1]);
+		pda.cpubte[1] = &(nodepda->node_bte_info[0]);
+	}
+}
+
+
+/*
+ * bte_unaligned_copy(src, dest, len, mode)
+ *
+ * use the block transfer engine to move kernel
+ * memory from src to dest using the assigned mode.
+ *
+ * Paramaters:
+ *   src - physical address of the transfer source.
+ *   dest - physical address of the transfer destination.
+ *   len - number of bytes to transfer from source to dest.
+ *   mode - hardware defined.  See reference information
+ *          for IBCT0/1 in the SGI documentation.
+ *   bteBlock - kernel virtual address of a temporary
+ *              buffer used during unaligned transfers.
+ *
+ * NOTE: If the source, dest, and len are all cache line aligned,
+ * then it would be _FAR_ preferrable to use bte_copy instead.
+ */
+bte_result_t
+bte_unaligned_copy(u64 src, u64 dest, u64 len, u64 mode, char *bteBlock)
+{
+	int destFirstCacheOffset;
+	u64 headBteSource;
+	u64 headBteLen;
+	u64 headBcopySrcOffset;
+	u64 headBcopyDest;
+	u64 headBcopyLen;
+	u64 footBteSource;
+	u64 footBteLen;
+	u64 footBcopyDest;
+	u64 footBcopyLen;
+	bte_result_t rv;
+
+	if (len == 0) {
+		return (BTE_SUCCESS);
+	}
+
+	headBcopySrcOffset = src & L1_CACHE_MASK;
+	destFirstCacheOffset = dest & L1_CACHE_MASK;
+
+	/*
+	 * At this point, the transfer is broken into
+	 * (up to) three sections.  The first section is
+	 * from the start address to the first physical
+	 * cache line, the second is from the first physical
+	 * cache line to the last complete cache line,
+	 * and the third is from the last cache line to the
+	 * end of the buffer.  The first and third sections
+	 * are handled by bte copying into a temporary buffer
+	 * and then bcopy'ing the necessary section into the
+	 * final location.  The middle section is handled with
+	 * a standard bte copy.
+	 *
+	 * One nasty exception to the above rule is when the
+	 * source and destination are not symetrically
+	 * mis-aligned.  If the source offset from the first
+	 * cache line is different from the destination offset,
+	 * we make the first section be the entire transfer
+	 * and the bcopy the entire block into place.
+	 */
+	if (headBcopySrcOffset == destFirstCacheOffset) {
+
+		/*
+		 * Both the source and destination are the same
+		 * distance from a cache line boundary so we can
+		 * use the bte to transfer the bulk of the
+		 * data.
+		 */
+		headBteSource = src & ~L1_CACHE_MASK;
+		headBcopyDest = dest;
+		if (headBcopySrcOffset) {
+			headBcopyLen =
+			    (len >
+			     (L1_CACHE_BYTES -
+			      headBcopySrcOffset) ? L1_CACHE_BYTES
+			     - headBcopySrcOffset : len);
+			headBteLen = L1_CACHE_BYTES;
+		} else {
+			headBcopyLen = 0;
+			headBteLen = 0;
+		}
+
+		if (len > headBcopyLen) {
+			footBcopyLen =
+			    (len - headBcopyLen) & L1_CACHE_MASK;
+			footBteLen = L1_CACHE_BYTES;
+
+			footBteSource = src + len - footBcopyLen;
+			footBcopyDest = dest + len - footBcopyLen;
+
+			if (footBcopyDest ==
+			    (headBcopyDest + headBcopyLen)) {
+				/*
+				 * We have two contigous bcopy
+				 * blocks.  Merge them.
+				 */
+				headBcopyLen += footBcopyLen;
+				headBteLen += footBteLen;
+			} else if (footBcopyLen > 0) {
+				rv = bte_copy(footBteSource,
+					      __pa(bteBlock),
+					      footBteLen, mode, NULL);
+				if (rv != BTE_SUCCESS) {
+					return (rv);
+				}
+
+
+				memcpy(__va(footBcopyDest),
+				       (char *)bteBlock, footBcopyLen);
+			}
+		} else {
+			footBcopyLen = 0;
+			footBteLen = 0;
+		}
+
+		if (len > (headBcopyLen + footBcopyLen)) {
+			/* now transfer the middle. */
+			rv = bte_copy((src + headBcopyLen),
+				      (dest +
+				       headBcopyLen),
+				      (len - headBcopyLen -
+				       footBcopyLen), mode, NULL);
+			if (rv != BTE_SUCCESS) {
+				return (rv);
+			}
+
+		}
+	} else {
+
+
+		/*
+		 * The transfer is not symetric, we will
+		 * allocate a buffer large enough for all the
+		 * data, bte_copy into that buffer and then
+		 * bcopy to the destination.
+		 */
+
+		/* Add the leader from source */
+		headBteLen = len + (src & L1_CACHE_MASK);
+		/* Add the trailing bytes from footer. */
+		headBteLen +=
+		    L1_CACHE_BYTES - (headBteLen & L1_CACHE_MASK);
+		headBteSource = src & ~L1_CACHE_MASK;
+		headBcopySrcOffset = src & L1_CACHE_MASK;
+		headBcopyDest = dest;
+		headBcopyLen = len;
+	}
+
+	if (headBcopyLen > 0) {
+		rv = bte_copy(headBteSource,
+			      __pa(bteBlock), headBteLen, mode, NULL);
+		if (rv != BTE_SUCCESS) {
+			return (rv);
+		}
+
+		memcpy(__va(headBcopyDest), ((char *)bteBlock +
+					     headBcopySrcOffset),
+		       headBcopyLen);
+	}
+	return (BTE_SUCCESS);
+}
diff -Nru a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/irq.c	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,343 @@
+/*
+ * Platform dependent support for SGI SN1
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <asm/current.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/iograph.h>
+#include <asm/sn/invent.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/types.h>
+#include <asm/sn/pci/bridge.h>
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pciio_private.h>
+#ifdef ajmtestintr
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+#endif /* ajmtestintr */
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/io.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/arch.h>
+
+int irq_to_bit_pos(int irq);
+
+
+
+static unsigned int
+sn1_startup_irq(unsigned int irq)
+{
+        return(0);
+}
+
+static void
+sn1_shutdown_irq(unsigned int irq)
+{
+}
+
+static void
+sn1_disable_irq(unsigned int irq)
+{
+}
+
+static void
+sn1_enable_irq(unsigned int irq)
+{
+}
+
+static void
+sn1_ack_irq(unsigned int irq)
+{
+#ifdef CONFIG_IA64_SGI_SN1
+	int bit = -1;
+	unsigned long long intpend_val;
+	int subnode;
+#endif
+#ifdef CONFIG_IA64_SGI_SN2
+	unsigned long event_occurred, mask = 0;
+#endif
+	int nasid;
+
+	irq = irq & 0xff;
+	nasid = smp_physical_node_id();
+#ifdef CONFIG_IA64_SGI_SN1
+	subnode = cpuid_to_subnode(smp_processor_id());
+	if (irq == SGI_UART_IRQ) {
+		intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
+		if (intpend_val & (1L<<GFX_INTR_A) ) {
+			bit = GFX_INTR_A;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if ( intpend_val & (1L<<GFX_INTR_B) ) {
+			bit = GFX_INTR_B;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<PG_MIG_INTR) ) {
+			bit = PG_MIG_INTR;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<CC_PEND_A)) {
+			bit = CC_PEND_A;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		if (intpend_val & (1L<<CC_PEND_B)) {
+			bit = CC_PEND_B;
+			REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+		}
+		return;
+	}
+	bit = irq_to_bit_pos(irq);
+	REMOTE_HUB_PI_CLR_INTR(nasid, subnode, bit);
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN2
+	event_occurred = HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid,SH_EVENT_OCCURRED) );
+	if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_UART_INT_SHFT);
+	}
+	if (event_occurred & SH_EVENT_OCCURRED_IPI_INT_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_IPI_INT_SHFT);
+	}
+	if (event_occurred & SH_EVENT_OCCURRED_II_INT0_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_II_INT0_SHFT);
+	}
+	if (event_occurred & SH_EVENT_OCCURRED_II_INT1_MASK) {
+		mask |= (1 << SH_EVENT_OCCURRED_II_INT1_SHFT);
+	}
+	HUB_S((unsigned long *)GLOBAL_MMR_ADDR(nasid, SH_EVENT_OCCURRED_ALIAS), mask );
+#endif
+}
+
+static void
+sn1_end_irq(unsigned int irq)
+{
+#ifdef CONFIG_IA64_SGI_SN1
+	unsigned long long intpend_val, mask = 0x70L;
+	int subnode;
+#endif
+	int nasid;
+#ifdef CONFIG_IA64_SGI_SN2
+	unsigned long event_occurred;
+#endif
+
+	irq = irq & 0xff;
+#ifdef CONFIG_IA64_SGI_SN1
+	if (irq == SGI_UART_IRQ) {
+		nasid = smp_physical_node_id();
+		subnode = cpuid_to_subnode(smp_processor_id());
+		intpend_val = REMOTE_HUB_PI_L(nasid, subnode, PI_INT_PEND0);
+		if (intpend_val & mask) {
+			platform_send_ipi(smp_processor_id(), SGI_UART_IRQ, IA64_IPI_DM_INT, 0);
+		}
+	}
+#endif
+#ifdef CONFIG_IA64_SGI_SN2
+	if (irq == SGI_UART_VECTOR) {
+		nasid = smp_physical_node_id();
+		event_occurred = HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(nasid,SH_EVENT_OCCURRED) );
+		// If the UART bit is set here, we may have received an interrupt from the
+		// UART that the driver missed.  To make sure, we IPI ourselves to force us
+		// to look again.
+		if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
+				platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR, IA64_IPI_DM_INT, 0);
+		}
+	}
+#endif
+
+}
+
+static void
+sn1_set_affinity_irq(unsigned int irq, unsigned long mask)
+{
+}
+
+
+struct hw_interrupt_type irq_type_iosapic_level = {
+	"SN hub",
+	sn1_startup_irq,
+	sn1_shutdown_irq,
+	sn1_enable_irq,
+	sn1_disable_irq,
+	sn1_ack_irq, 
+	sn1_end_irq,
+	sn1_set_affinity_irq
+};
+
+
+#define irq_type_sn1 irq_type_iosapic_level
+struct irq_desc *_sn1_irq_desc[NR_CPUS];
+
+struct irq_desc *
+sn1_irq_desc(unsigned int irq) {
+	int cpu = irq >> 8;
+
+	irq = irq & 0xff;
+
+	return(_sn1_irq_desc[cpu] + irq);
+}
+
+u8
+sn1_irq_to_vector(u8 irq) {
+	return(irq & 0xff);
+}
+
+unsigned int
+sn1_local_vector_to_irq(u8 vector) {
+	return ( (smp_processor_id() << 8) + vector);
+}
+
+int
+sn1_valid_irq(u8 irq) {
+
+	return( ((irq & 0xff) < NR_IRQS) && ((irq >> 8) < NR_CPUS) );
+}
+
+void *kmalloc(size_t, int);
+
+void
+sn1_irq_init (void)
+{
+	int i;
+	irq_desc_t *base_desc = _irq_desc;
+
+	for (i=IA64_FIRST_DEVICE_VECTOR; i<NR_IRQS; i++) {
+		if (base_desc[i].handler == &no_irq_type) {
+			base_desc[i].handler = &irq_type_sn1;
+		}
+	}
+}
+
+void
+sn1_init_irq_desc(void) {
+	int i;
+	irq_desc_t *base_desc = _irq_desc, *p;
+
+	for (i=0; i < NR_CPUS; i++) {
+		p =  page_address(alloc_pages_node(local_cnodeid(), GFP_KERNEL,
+			get_order(sizeof(struct irq_desc) * NR_IRQS) ) );
+		ASSERT(p);
+		memcpy(p, base_desc, sizeof(struct irq_desc) * NR_IRQS);
+		_sn1_irq_desc[i] = p;
+	}
+}
+
+
+#if !defined(CONFIG_IA64_SGI_SN)
+void
+sn1_pci_fixup(void)
+{
+}
+#endif
+
+int
+bit_pos_to_irq(int bit) {
+#define BIT_TO_IRQ 64
+	if (bit > 118) bit = 118;
+
+#ifdef CONFIG_IA64_SGI_SN1
+	if (bit >= GFX_INTR_A && bit <= CC_PEND_B) {
+		return SGI_UART_IRQ;
+	}
+#endif
+
+        return bit + BIT_TO_IRQ;
+}
+
+int
+irq_to_bit_pos(int irq) {
+#define IRQ_TO_BIT 64
+	int bit = irq - IRQ_TO_BIT;
+
+        return bit;
+}
+
+#ifdef ajmtestintr
+
+#include <linux/timer.h>
+struct timer_list intr_test_timer;
+int intr_test_icount[NR_IRQS];
+struct intr_test_reg_struct {
+	pcibr_soft_t pcibr_soft;
+	int slot;
+};
+struct intr_test_reg_struct intr_test_registered[NR_IRQS];
+
+void
+intr_test_handle_timer(unsigned long data) {
+	int i;
+	bridge_t	*bridge;
+
+	for (i=0;i<NR_IRQS;i++) {
+		if (intr_test_registered[i].pcibr_soft) {
+			pcibr_soft_t pcibr_soft = intr_test_registered[i].pcibr_soft;
+			xtalk_intr_t intr = pcibr_soft->bs_intr[intr_test_registered[i].slot].bsi_xtalk_intr;
+			/* send interrupt */
+			bridge = pcibr_soft->bs_base;
+			bridge->b_force_always[intr_test_registered[i].slot].intr = 1;
+		}
+	}
+	del_timer(&intr_test_timer);
+	intr_test_timer.expires = jiffies + HZ/100;
+	add_timer(&intr_test_timer);
+}
+
+void
+intr_test_set_timer(void) {
+	intr_test_timer.expires = jiffies + HZ/100;
+	intr_test_timer.function = intr_test_handle_timer;
+	add_timer(&intr_test_timer);
+}
+
+void
+intr_test_register_irq(int irq, pcibr_soft_t pcibr_soft, int slot) {
+	irq = irq & 0xff;
+	intr_test_registered[irq].pcibr_soft = pcibr_soft;
+	intr_test_registered[irq].slot = slot;
+}
+
+void
+intr_test_handle_intr(int irq, void *junk, struct pt_regs *morejunk) {
+	intr_test_icount[irq]++;
+	printk("RECEIVED %d INTERRUPTS ON IRQ %d\n",intr_test_icount[irq], irq);
+}
+#endif /* ajmtestintr */
diff -Nru a/arch/ia64/sn/kernel/llsc4.c b/arch/ia64/sn/kernel/llsc4.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/llsc4.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,1037 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/kernel_stat.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <asm/efi.h>
+#include <asm/page.h>
+#include <linux/threads.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/leds.h>
+
+#include "llsc4.h"
+
+
+#ifdef STANDALONE
+#include "lock.h"
+#endif
+
+#ifdef INTTEST
+static int	inttest=0;
+#endif
+
+#ifdef IA64_SEMFIX_INSN
+#undef IA64_SEMFIX_INSN
+#endif
+#ifdef IA64_SEMFIX
+#undef IA64_SEMFIX
+#endif
+# define IA64_SEMFIX_INSN
+# define IA64_SEMFIX    ""
+
+#define NOLOCK		0xdead
+#define BGUARD(linei)	(0xbbbb0000 | (linei));
+#define EGUARD(linei)	(0xeeee0000 | (linei));
+#define GUARDLINE(v)	((v)&0xffff)
+
+/*
+ * Test parameter table for AUTOTEST
+ */
+typedef struct {
+	int	passes;
+	int	linecount;
+	int	linepad;
+} autotest_table_t;
+
+autotest_table_t autotest_table[] = {
+	{50000000,	2,	0x2b4		},
+	{50000000,	16,	0,		},
+	{50000000,	16,	4,		},
+	{50000000,	128,	0x44		},
+	{50000000,	128,	0x84		},
+	{50000000,	128,	0x200		},
+	{50000000,	128,	0x204		},
+	{50000000,	128,	0x2b4		},
+	{50000000,	2,	8*MB+0x2b4	},
+	{50000000,	16,	8*MB+0		},
+	{50000000,	16,	8*MB+4		},
+	{50000000,	128,	8*MB+0x44	},
+	{50000000,	128,	8*MB+0x84	},
+	{50000000,	128,	8*MB+0x200	},
+	{50000000,	128,	8*MB+0x204	},
+	{50000000,	128,	8*MB+0x2b4	},
+	{0}};
+
+/*
+ * Array of virtual addresses available for test purposes.
+ */
+
+typedef struct {
+	long	vstart;
+	long	vend;
+	long	nextaddr;
+	long	nextinit;
+	int	wrapcount;
+} memmap_t;
+
+#define MAPCHUNKS		128
+memmap_t 	memmap[MAPCHUNKS];
+int		memmapx=0;
+
+typedef struct {
+	void	*addr;
+	long	data[16];
+	long	data_fc[16];
+} capture_line_t;
+
+typedef struct {
+	int	size;
+	void	*blockaddr;
+	void	*shadaddr;
+	long	blockdata[48];
+	long	shaddata[48];
+	long	blockdata_fc[48];
+	long	shaddata_fc[48];
+	long	synerr;
+} capture_t;
+
+/*
+ * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and
+ * the rest of the tables have to start at 1MB to skip PROM tables.
+ */
+#define THREADPRIVATE(t)	((threadprivate_t*)(((long)mbase)+1024*1024+t*((sizeof(threadprivate_t)+511)/512*512)))
+
+#define k_capture		mbase->sk_capture
+#define k_go			mbase->sk_go
+#define k_linecount		mbase->sk_linecount
+#define k_passes		mbase->sk_passes
+#define k_napticks		mbase->sk_napticks
+#define k_stop_on_error		mbase->sk_stop_on_error
+#define k_verbose		mbase->sk_verbose
+#define k_threadprivate		mbase->sk_threadprivate
+#define k_blocks		mbase->sk_blocks
+#define k_iter_msg		mbase->sk_iter_msg
+#define k_vv			mbase->sk_vv
+#define k_linepad		mbase->sk_linepad
+#define k_options		mbase->sk_options
+#define k_testnumber		mbase->sk_testnumber
+#define k_currentpass		mbase->sk_currentpass
+
+static long		blocks[MAX_LINECOUNT];		/* addresses of data blocks */
+static control_t	*mbase;
+static vint		initialized=0;
+
+static unsigned int ran_conf_llsc(int);
+static int  rerr(capture_t *, char *, void *, void *, int, int, int, int, int, int);
+static void dumpline(void *, char *, char *, void *, void *, int);
+static int  checkstop(int, int, uint);
+static void spin(int);
+static void capturedata(capture_t *, uint, void *, void *, int);
+static int  randn(uint max, uint *seed);
+static uint zrandom (uint *zranseed);
+static int  set_lock(uint *, uint);
+static int  clr_lock(uint *, uint);
+static void Speedo(void);
+
+int autotest_enabled=0;
+static int llsctest_number=-1;
+static int errstop_enabled=0;
+static int fail_enabled=0;
+static int l4_opt=0;
+static int selective_trigger=0;
+static int dump_block_addrs_opt=0;
+static lock_t errlock=NOLOCK;
+static private_t init_private[LLSC_MAXCPUS];
+
+static int __init autotest_enable(char *str)
+{
+        autotest_enabled = 1;
+	return 1;
+}
+static int __init set_llscblkadr(char *str)
+{
+	dump_block_addrs_opt = 1;
+	return 1;
+}
+static int __init set_llscselt(char *str)
+{
+	selective_trigger = 1;
+	return 1;
+}
+static int __init set_llsctest(char *str)
+{
+        llsctest_number = simple_strtol(str, &str, 10);
+	if (llsctest_number < 0 || llsctest_number > 15)
+		llsctest_number = -1;
+	return 1;
+}
+static int __init set_llscerrstop(char *str)
+{
+        errstop_enabled = 1;
+	return 1;
+}
+static int __init set_llscfail(char *str)
+{
+        fail_enabled = 8;
+	return 1;
+}
+static int __init set_llscl4(char *str)
+{
+        l4_opt = 1;
+	return 1;
+}
+
+static void print_params(void)
+{
+	printk ("********* Enter AUTOTEST facility on master cpu *************\n");
+	printk ("  Test options:\n");
+	printk ("     llsctest=<n>\t%d\tTest number to run (all = -1)\n", llsctest_number);
+	printk ("     llscerrstop \t%s\tStop on error\n", errstop_enabled ? "on" : "off");
+	printk ("     llscfail    \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off");
+	printk ("     llscselt    \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off");
+	printk ("     llscblkadr  \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off");
+	printk ("     llscl4      \t%s\tRun only tests that evict from L4\n", l4_opt ? "on" : "off");
+	printk ("  SEMFIX: %s\n", IA64_SEMFIX);
+	printk ("\n");
+}
+__setup("autotest", autotest_enable);
+__setup("llsctest=", set_llsctest);
+__setup("llscerrstop", set_llscerrstop);
+__setup("llscfail", set_llscfail);
+__setup("llscselt", set_llscselt);
+__setup("llscblkadr", set_llscblkadr);
+__setup("llscl4", set_llscl4);
+
+
+
+static inline int
+set_lock(uint *lock, uint id)
+{
+	uint	old;
+	old = cmpxchg_acq(lock, NOLOCK, id);
+	return (old == NOLOCK);
+}
+
+static inline int
+clr_lock(uint *lock, uint id)
+{
+	uint	old;
+	old = cmpxchg_rel(lock, id, NOLOCK);
+	return (old == id);
+}
+
+static inline void
+init_lock(uint *lock)
+{
+	*lock = NOLOCK;
+}
+
+/*------------------------------------------------------------------------+
+| Routine  :  ran_conf_llsc - ll/sc shared data test                      |
+| Description: This test checks the coherency of shared data              |
++------------------------------------------------------------------------*/
+static unsigned int
+ran_conf_llsc(int thread)
+{
+	private_t	pval;
+	share_t		sval, sval2;
+	uint		vv, linei, slinei, sharei, pass;
+	long		t;
+	lock_t		lockpat;
+	share_t		*sharecopy;
+	long		verbose, napticks, passes, linecount, lcount;
+	dataline_t	*linep, *slinep;
+	int		s, seed;
+	threadprivate_t	*tp;
+	uint		iter_msg, iter_msg_i=0;
+	int		vv_mask;
+	int		correct_errors;
+	int		errs=0;
+	int		stillbad;
+	capture_t	capdata;
+	private_t	*privp;
+	share_t		*sharep;
+
+
+	linecount = k_linecount;
+	napticks = k_napticks;
+	verbose = k_verbose;
+	passes = k_passes;
+	iter_msg = k_iter_msg;
+	seed = (thread + 1) * 647;
+	tp = THREADPRIVATE(thread);
+	vv_mask = (k_vv>>((thread%16)*4)) & 0xf;
+	correct_errors = k_options&0xff;
+
+	memset (&capdata, 0, sizeof(capdata));
+	for (linei=0; linei<linecount; linei++)
+		tp->private[linei] = thread;	
+
+	for (pass = 1; passes == 0 || pass < passes; pass++) {
+		lockpat = (pass & 0x0fffffff) + (thread <<28);
+		if (lockpat == NOLOCK)
+			continue;
+		tp->threadpasses = pass;
+		if (checkstop(thread, pass, lockpat))
+			return 0;
+		iter_msg_i++;
+		if (iter_msg && iter_msg_i > iter_msg) {
+			printk("Thread %d, Pass %d\n", thread, pass);
+			iter_msg_i = 0;
+		}
+		lcount = 0;
+
+		/*
+		 * Select line to perform operations on.
+		 */
+		linei = randn(linecount, &seed);
+		sharei = randn(2, &seed);
+		slinei = (linei + (linecount/2))%linecount;		/* I dont like this - fix later */
+
+		linep = (dataline_t *)blocks[linei];
+		slinep = (dataline_t *)blocks[slinei];
+		if (sharei == 0)
+			sharecopy = &slinep->share0;
+		else
+			sharecopy = &slinep->share1;
+
+
+		vv = randn(4, &seed);
+		if ((vv_mask & (1<<vv)) == 0)
+			continue;
+
+		if (napticks) {
+			t = randn(napticks, &seed);
+			udelay(t);
+		}
+		privp = &linep->private[thread];
+		sharep = &linep->share[sharei];
+		
+		switch(vv) {
+		case 0:
+			/* Read and verify private count on line. */
+			pval = *privp;
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
+			if (pval != tp->private[linei]) {
+				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
+				stillbad = (*privp != tp->private[linei]);
+				if (rerr(&capdata, "Private count", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
+					return 1;
+				}
+				if (correct_errors) {
+					tp->private[linei] = *privp;
+				}
+				errs++;
+			}
+			break;
+
+		case 1:
+			/* Read, verify, and increment private count on line. */
+			pval = *privp;
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
+			if (pval != tp->private[linei]) {
+				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
+				stillbad = (*privp != tp->private[linei]);
+				if (rerr(&capdata, "Private count & inc", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
+					return 1;
+				}
+				errs++;
+			}
+			pval = (pval==255) ? 0 : pval+1;
+			*privp = pval;
+			tp->private[linei] = pval;
+			break;
+
+		case 2:
+			/* Lock line, read and verify shared data. */
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
+			lcount = 0;
+			while (LOCK(sharei) != 1) {
+				if (checkstop(thread, pass, lockpat))
+					return 0;
+				if (lcount++>1000000) {
+					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
+					stillbad = (GETLOCK(sharei) != 0);
+					rerr(&capdata, "Shared data lock", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
+					return 1;
+				}
+				if ((lcount&0x3fff) == 0)
+					udelay(1000);
+			}
+
+			sval = *sharep;
+			sval2 = *sharecopy;
+			if (pass > 12 && thread == 0 && fail_enabled == 1)
+				sval++;
+			if (sval != sval2) {
+				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
+				stillbad = (*sharep != *sharecopy);
+				if (!stillbad && *sharep != sval && *sharecopy == sval2)
+					stillbad = 2;
+				if (rerr(&capdata, "Shared data", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
+					return 1;
+				}
+				if (correct_errors)
+					*sharep = *sharecopy;
+				errs++;
+			}
+
+
+			if ( (s=UNLOCK(sharei)) != 1) {
+				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
+				stillbad = (GETLOCK(sharei) != lockpat);
+				if (rerr(&capdata, "Shared data unlock", linep, slinep, thread, pass, linei, lockpat, GETLOCK(sharei), stillbad))
+					return 1;
+				if (correct_errors)
+					ZEROLOCK(sharei);	
+				errs++;
+			}
+			break;
+
+		case 3:
+			/* Lock line, read and verify shared data, modify shared data. */
+			if (verbose)
+				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
+			lcount = 0;
+			while (LOCK(sharei) != 1) {
+				if (checkstop(thread, pass, lockpat))
+					return 0;
+				if (lcount++>1000000) {
+					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
+					stillbad = (GETLOCK(sharei) != 0);
+					rerr(&capdata, "Shared data lock & inc", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
+					return 1;
+				}
+				if ((lcount&0x3fff) == 0)
+					udelay(1000);
+			}
+			sval = *sharep;
+			sval2 = *sharecopy;
+			if (sval != sval2) {
+				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
+				stillbad = (*sharep != *sharecopy);
+				if (!stillbad && *sharep != sval && *sharecopy == sval2)
+					stillbad = 2;
+				if (rerr(&capdata, "Shared data & inc", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
+					return 1;
+				}
+				errs++;
+			}
+
+			*sharep = lockpat;
+			*sharecopy = lockpat;
+
+
+			if ( (s=UNLOCK(sharei)) != 1) {
+				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
+				stillbad = (GETLOCK(sharei) != lockpat);
+				if (rerr(&capdata, "Shared data & inc unlock", linep, slinep, thread, pass, linei, thread, GETLOCK(sharei), stillbad))
+					return 1;
+				if (correct_errors)
+					ZEROLOCK(sharei);	
+				errs++;
+			}
+			break;
+		}
+	}
+
+	return (errs > 0);
+}
+
+static void
+trigger_la(long val)
+{
+	long	*p;
+
+	p = (long*)0xc0000a0001000020L; /* PI_CPU_NUM */
+	*p = val;
+}
+
+static long
+getsynerr(void)
+{
+	long	err, *errp;
+
+	errp = (long*)0xc0000e0000000340L;	/* SYN_ERR */
+	err = *errp;
+	if (err)
+		*errp = -1L;
+	return (err & ~0x60);
+}
+
+static int
+rerr(capture_t *cap, char *msg, void *lp, void *slp, int thread, int pass, int badlinei, int exp, int found, int stillbad)
+{
+	int		cpu, i, linei;
+	long 		synerr;
+	int		selt;
+
+
+	selt = selective_trigger && stillbad > 1 && 
+			memcmp(cap->blockdata, cap->blockdata_fc, 128) != 0 &&
+			memcmp(cap->shaddata, cap->shaddata_fc, 128) == 0;
+	if (selt) {
+		trigger_la(pass);
+	} else if (selective_trigger) {
+		k_go = ST_STOP;
+		return k_stop_on_error;;
+	}
+
+	spin(1);
+	i = 100;
+	while (i && set_lock(&errlock, 1) != 1) {
+		spin(1);
+		i--;
+	}
+	printk ("\nDataError!: %-20s, test %ld, thread %d, line:%d, pass %d (0x%x), time %ld expected:%x, found:%x\n",
+	    msg, k_testnumber, thread, badlinei, pass, pass, jiffies, exp, found);
+
+	dumpline (lp, "Corrupted data", "D ", cap->blockaddr, cap->blockdata, cap->size);
+#ifdef ZZZ
+	if (memcmp(cap->blockdata, cap->blockdata_fc, 128))
+		dumpline (lp, "Corrupted data", "DF", cap->blockaddr, cap->blockdata_fc, cap->size);
+#endif
+
+	if (cap->shadaddr) {
+		dumpline (slp, "Shadow    data", "S ", cap->shadaddr, cap->shaddata, cap->size);
+#ifdef ZZZ
+		if (memcmp(cap->shaddata, cap->shaddata_fc, 128))
+			dumpline (slp, "Shadow    data", "SF", cap->shadaddr, cap->shaddata_fc, cap->size);
+#endif
+	}
+	
+	printk("Threadpasses: ");
+	for (cpu=0,i=0; cpu<LLSC_MAXCPUS; cpu++)
+		if (k_threadprivate[cpu]->threadpasses) {
+			if (i && (i%8) == 0)
+				printk("\n            : ");
+			printk("  %d:0x%x", cpu, k_threadprivate[cpu]->threadpasses);
+			i++;
+		}
+	printk("\n");
+	
+	for (linei=0; linei<k_linecount; linei++) {
+		int		slinei, g1linei, g2linei, g1err, g2err, sh0err, sh1err;
+		dataline_t	*linep, *slinep;
+
+		slinei = (linei + (k_linecount/2))%k_linecount;
+		linep = (dataline_t *)blocks[linei];
+		slinep = (dataline_t *)blocks[slinei];
+
+		g1linei = GUARDLINE(linep->guard1);
+		g2linei = GUARDLINE(linep->guard2);
+		g1err = (g1linei != linei);
+		g2err = (g2linei != linei);
+		sh0err = (linep->share[0] != slinep->share0);
+		sh1err = (linep->share[1] != slinep->share1);
+
+		if (g1err || g2err || sh0err || sh1err) {
+			printk("Line 0x%lx (%03d), %sG1 0x%lx (%03d), %sG2 0x%lx (%03d), %sSH0 %08x (%08x), %sSH1 %08x (%08x)\n",
+				blocks[linei], linei, 
+				g1err ? "*" : " ", blocks[g1linei], g1linei,
+				g2err ? "*" : " ", blocks[g2linei], g2linei,
+				sh0err ? "*" : " ", linep->share[0], slinep->share0,
+				sh1err ? "*" : " ", linep->share[1], slinep->share1);
+
+
+		}
+	}
+
+	printk("\nData was %sfixed by flushcache\n", (stillbad == 1 ? "**** NOT **** " : " "));
+	synerr = getsynerr();
+	if (synerr)
+		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
+	spin(2);
+	printk("\n\n");
+	clr_lock(&errlock, 1);
+
+	if (errstop_enabled) {
+		local_irq_disable();
+		while(1);
+	}
+	return k_stop_on_error;
+}
+
+
+static void
+dumpline(void *lp, char *str1, char *str2, void *addr, void *data, int size)
+{
+	long *p;
+	int i, off;
+
+	printk("%s at 0x%lx, size %d, block starts at 0x%lx\n", str1, (long)addr, size, (long)lp);
+	p = (long*) data;
+	for (i=0; i<48; i++, p++) {
+		if (i%8 == 0) printk("%2s", i==16 ? str2 : "  ");
+		printk(" %016lx", *p);
+		if ((i&7)==7) printk("\n");
+	}
+	printk("   ");
+	off = (((long)addr) ^ size) & 63L;
+	for (i=0; i<off+size; i++) {
+		printk("%s", (i>=off) ? "--" : "  ");
+		if ((i%8) == 7)
+			printk(" ");
+	}
+
+	off = ((long)addr) & 127;
+	printk(" (line %d)\n", 2+off/64+1);
+}
+
+
+static int
+randn(uint max, uint *seedp)
+{
+	if (max == 1)
+		return(0);
+	else
+		return((int)(zrandom(seedp)>>10) % max);
+}
+
+
+static int
+checkstop(int thread, int pass, uint lockpat)
+{
+	long	synerr;
+
+	if (k_go == ST_RUN)
+		return 0;
+	if (k_go == ST_STOP)
+		return 1;
+
+	if (errstop_enabled) {
+		local_irq_disable();
+		while(1);
+	}
+	synerr = getsynerr();
+	spin(2);
+	if (k_go == ST_STOP)
+		return 1;
+	if (synerr)
+		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
+	return 1;
+}
+
+
+static void
+spin(int j)
+{
+	udelay(j * 500000);
+}
+
+static void
+capturedata(capture_t *cap, uint pass, void *blockaddr, void *shadaddr, int size)
+{
+
+	if (!selective_trigger)
+		trigger_la (pass);
+
+	memcpy (cap->blockdata, CACHEALIGN(blockaddr)-128, 3*128);
+	if (shadaddr) 
+		memcpy (cap->shaddata, CACHEALIGN(shadaddr)-128, 3*128);
+
+	if (k_stop_on_error) {
+		k_go = ST_ERRSTOP;
+	}
+
+ 	cap->size = size;
+	cap->blockaddr = blockaddr;
+	cap->shadaddr = shadaddr;
+
+	asm volatile ("fc %0" :: "r"(blockaddr) : "memory");
+	ia64_sync_i();
+	ia64_srlz_d();
+	memcpy (cap->blockdata_fc, CACHEALIGN(blockaddr)-128, 3*128);
+
+	if (shadaddr) {
+		asm volatile ("fc %0" :: "r"(shadaddr) : "memory");
+		ia64_sync_i();
+		ia64_srlz_d();
+		memcpy (cap->shaddata_fc, CACHEALIGN(shadaddr)-128, 3*128);
+	}
+}
+
+int             zranmult = 0x48c27395;
+
+static uint  
+zrandom (uint *seedp)
+{
+        *seedp = (*seedp * zranmult) & 0x7fffffff;
+        return (*seedp);
+}
+
+
+void
+set_autotest_params(void)
+{
+	static int	testnumber=-1;
+
+	if (llsctest_number >= 0) {
+		testnumber = llsctest_number;
+	} else {
+		testnumber++;
+		if (autotest_table[testnumber].passes == 0) {
+			testnumber = 0;
+			dump_block_addrs_opt = 0;
+		}
+	}
+	if (testnumber == 0 && l4_opt) testnumber = 9;
+
+	k_passes = autotest_table[testnumber].passes;
+	k_linepad = autotest_table[testnumber].linepad;
+	k_linecount = autotest_table[testnumber].linecount;
+	k_testnumber = testnumber;
+
+	if (IS_RUNNING_ON_SIMULATOR()) {
+		printk ("llsc start test %ld\n", k_testnumber);
+		k_passes = 1000;
+	}
+}
+
+
+static void
+set_leds(int errs)
+{
+	unsigned char	leds=0;
+
+	/*
+	 * Leds are:
+	 * 	ppppeee-  
+	 *   where
+	 *      pppp = test number
+	 *       eee = error count but top bit is stick
+	 */
+
+	leds =  ((errs&7)<<1) | ((k_testnumber&15)<<4) | (errs ? 0x08 : 0);
+	set_led_bits(leds, LED_MASK_AUTOTEST);
+}
+
+static void
+setup_block_addresses(void)
+{
+	int			i, stride, memmapi;
+	dataline_t		*dp;
+	long			*ip, *ipe;
+
+
+	stride = k_linepad + sizeof(dataline_t);
+	memmapi = 0;
+	for (i=0; i<memmapx; i++) {
+		memmap[i].nextaddr = memmap[i].vstart;
+		memmap[i].nextinit = memmap[i].vstart;
+		memmap[i].wrapcount = 0;
+	}
+
+	for (i=0; i<k_linecount; i++) {
+		blocks[i] = memmap[memmapi].nextaddr;
+		dp = (dataline_t*)blocks[i];
+		memmap[memmapi].nextaddr += (stride & 0xffff);
+		if (memmap[memmapi].nextaddr + sizeof(dataline_t) >= memmap[memmapi].vend) {
+			memmap[memmapi].wrapcount++;
+			memmap[memmapi].nextaddr = memmap[memmapi].vstart + 
+					memmap[memmapi].wrapcount * sizeof(dataline_t);
+		}
+
+		ip = (long*)((memmap[memmapi].nextinit+7)&~7);
+		ipe = (long*)(memmap[memmapi].nextaddr+2*sizeof(dataline_t)+8);
+		while(ip <= ipe && ip < ((long*)memmap[memmapi].vend-8))
+			*ip++ = (long)ip;
+		memmap[memmapi].nextinit = (long) ipe;
+		dp->guard1 = BGUARD(i);
+		dp->guard2 = EGUARD(i);
+		dp->lock[0] = dp->lock[1] = NOLOCK;
+		dp->share[0] = dp->share0 = 0x1111;
+		dp->share[1] = dp->share1 = 0x2222;
+		memcpy(dp->private, init_private, LLSC_MAXCPUS*sizeof(private_t));
+
+
+		if (stride > 16384) {
+			memmapi++;
+			if (memmapi == memmapx)
+				memmapi = 0;
+		}
+	}
+
+}
+
+static void
+dump_block_addrs(void)
+{
+	int	i;
+
+	printk("LLSC TestNumber %ld\n", k_testnumber);
+
+	for (i=0; i<k_linecount; i++) {
+		printk("  %lx", blocks[i]);
+		if (i%4 == 3)
+			printk("\n");
+	}
+	printk("\n");
+}
+
+
+static void
+set_thread_state(int cpuid, int state)
+{
+	if (k_threadprivate[cpuid]->threadstate == TS_KILLED) {
+		set_led_bits(LED_MASK_AUTOTEST, LED_MASK_AUTOTEST);
+		while(1);
+	}
+	k_threadprivate[cpuid]->threadstate = state;
+}
+
+static int
+build_mem_map(unsigned long start, unsigned long end, void *arg)
+{
+	long	lstart;
+	long	align = 8*MB;
+
+	/*
+	 * HACK - skip the kernel on the first node 
+	 */
+
+	printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", 
+		start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE));
+
+	if (memmapx >= MAPCHUNKS)
+		return 0;
+	while (end > start && (PageReserved(virt_to_page(end-PAGE_SIZE)) || virt_to_page(end-PAGE_SIZE)->count.counter > 0))
+		end -= PAGE_SIZE;
+
+	lstart = end;
+	while (lstart > start && (!PageReserved(virt_to_page(lstart-PAGE_SIZE)) && virt_to_page(lstart-PAGE_SIZE)->count.counter == 0))
+		lstart -= PAGE_SIZE;
+
+	lstart = (lstart + align -1) /align * align;
+	end = end / align * align;
+	if (lstart >= end)
+		return 0;
+	printk ("     memmap: start 0x%lx, end 0x%lx\n", lstart, end);
+
+	memmap[memmapx].vstart = lstart;
+	memmap[memmapx].vend = end;
+	memmapx++;
+	return 0;
+}
+
+void int_test(void);
+
+int
+llsc_main (int cpuid, long mbasex)
+{
+	int		i, cpu, is_master, repeatcnt=0;
+	unsigned int	preverr=0, errs=0, pass=0;
+	int		automode=0;
+
+#ifdef INTTEST
+	if (inttest)
+		int_test();
+#endif
+
+	if (!autotest_enabled)
+		return 0;
+
+#ifdef CONFIG_SMP
+	is_master = !smp_processor_id();
+#else
+	is_master = 1;
+#endif
+
+
+	if (is_master) {
+		print_params();
+		if(!IS_RUNNING_ON_SIMULATOR())
+			spin(10);
+		mbase = (control_t*)mbasex;
+		k_currentpass = 0;
+		k_go = ST_IDLE;
+		k_passes = DEF_PASSES;
+		k_napticks = DEF_NAPTICKS;
+		k_stop_on_error = DEF_STOP_ON_ERROR;
+		k_verbose = DEF_VERBOSE;
+		k_linecount = DEF_LINECOUNT;
+		k_iter_msg = DEF_ITER_MSG;
+		k_vv = DEF_VV;
+		k_linepad = DEF_LINEPAD;
+		k_blocks = (void*)blocks;
+		efi_memmap_walk(build_mem_map, 0);
+	
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+		automode = 1;
+#endif
+
+		for (i=0; i<LLSC_MAXCPUS; i++) {
+			k_threadprivate[i] = THREADPRIVATE(i);
+			memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i]));
+			init_private[i] = i;
+		}
+		initialized = 1;
+	} else {
+		while (initialized == 0)
+			udelay(100);
+	}
+
+loop:
+	if (is_master) {
+		if (automode) {
+			if (!preverr || repeatcnt++ > 5) {
+				set_autotest_params();
+				repeatcnt = 0;
+			}
+		} else {
+			while (k_go == ST_IDLE);
+		}
+
+		k_go = ST_INIT;
+		if (k_linecount > MAX_LINECOUNT) k_linecount = MAX_LINECOUNT;
+		k_linecount = k_linecount & ~1;
+		setup_block_addresses();
+		if (!preverr && dump_block_addrs_opt)
+			dump_block_addrs();
+
+		k_currentpass = pass++;
+		k_go = ST_RUN;
+		if (fail_enabled)
+			fail_enabled--;
+
+	} else {
+		while (k_go != ST_RUN || k_currentpass != pass);
+		pass++;
+	}
+
+
+	set_leds(errs);
+	set_thread_state(cpuid, TS_RUNNING);
+
+	errs += ran_conf_llsc(cpuid);
+	preverr = (k_go == ST_ERRSTOP);
+
+	set_leds(errs);
+	set_thread_state(cpuid, TS_STOPPED);
+
+	if (is_master) {
+		Speedo();
+		for (i=0, cpu=0; cpu<LLSC_MAXCPUS; cpu++) {
+			while (k_threadprivate[cpu]->threadstate == TS_RUNNING) {
+				i++;
+				if (i == 10000) { 
+					k_go = ST_STOP;
+					printk ("  llsc master stopping test number %ld\n", k_testnumber);
+				}
+				if (i > 100000) {
+					k_threadprivate[cpu]->threadstate = TS_KILLED;
+					printk ("  llsc: master killing cpuid %d, running test number %ld\n", 
+							cpu, k_testnumber);
+				}
+				udelay(1000);
+			}
+		}
+	}
+
+	goto loop;
+}
+
+
+static void
+Speedo(void)
+{
+	static int i = 0;
+
+	switch (++i%4) {
+	case 0:
+		printk("|\b");
+		break;
+	case 1:
+		printk("\\\b");
+		break;
+	case 2:
+		printk("-\b");
+		break;
+	case 3:
+		printk("/\b");
+		break;
+	}
+}
+
+#ifdef INTTEST
+
+/* ======================================================================================================== 
+ *
+ * Some test code to verify that interrupts work
+ *
+ * Add the following to the arch/ia64/kernel/smp.c after the comment "Reschedule callback"
+ * 		if (zzzprint_resched) printk("  cpu %d got interrupt\n", smp_processor_id());
+ *
+ * Enable the code in arch/ia64/sn/sn1/smp.c to print sending IPIs.
+ *
+ */
+
+static int __init set_inttest(char *str)
+{
+        inttest = 1;
+	autotest_enabled = 1;
+
+	return 1;
+}	
+
+__setup("inttest=", set_inttest);
+
+int	zzzprint_resched=0;
+
+void
+int_test() {
+	int			mycpu, cpu;
+	static volatile int	control_cpu=0;
+
+	mycpu = smp_processor_id();
+	zzzprint_resched = 2;
+
+	printk("Testing cross interrupts\n");
+	
+	while (control_cpu != smp_num_cpus) {
+		if (mycpu == cpu_logical_map(control_cpu)) {
+			for (cpu=0; cpu<smp_num_cpus; cpu++) {
+				printk("Sending interrupt from %d to %d\n", mycpu, cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+				smp_send_reschedule(cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+				smp_send_reschedule(cpu_logical_map(cpu));
+				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
+			}
+			control_cpu++;
+		}
+	}
+
+	zzzprint_resched = 1;
+
+	if (mycpu == cpu_logical_map(smp_num_cpus-1)) {
+		printk("\nTight loop of cpu %d sending ints to cpu 0 (every 100 us)\n", mycpu);
+		udelay(IS_RUNNING_ON_SIMULATOR ? 1000 : 1000000);
+		__cli();
+		while (1) {
+			smp_send_reschedule(0);
+			udelay(100);
+		}
+
+	}
+
+	while(1);
+}
+#endif
diff -Nru a/arch/ia64/sn/kernel/llsc4.h b/arch/ia64/sn/kernel/llsc4.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/llsc4.h	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,107 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifdef STANDALONE
+#include "lock.h"
+#endif
+
+
+#define DEF_NAPTICKS		0
+#define DEF_PASSES		0
+#define DEF_AUTO_PASSES		1000000
+#define DEF_STOP_ON_ERROR	1
+#define DEF_VERBOSE		0
+#define DEF_LINECOUNT		2
+#define DEF_ITER_MSG		0
+#define DEF_VV			0xffffffff
+#define DEF_LINEPAD		0x234
+
+
+
+#define LLSC_MAXCPUS		64
+#define CACHELINE		64
+#define MAX_LINECOUNT		1024
+#define K			1024
+#define	MB			(K*K)
+
+
+#define	uint 		unsigned int
+#define	ushort		unsigned short
+#define	uchar		unsigned char
+#define vint		volatile int
+#define vlong		volatile long
+
+#define LOCKADDR(i)	&linep->lock[(i)]
+#define LOCK(i)		set_lock(LOCKADDR(i), lockpat)
+#define UNLOCK(i)	clr_lock(LOCKADDR(i), lockpat)
+#define GETLOCK(i)	*LOCKADDR(i)
+#define ZEROLOCK(i)	init_lock(LOCKADDR(i))
+
+#define CACHEALIGN(a)	((char*)((long)(a) & ~127L))
+
+typedef uint		guard_t;
+typedef uint		lock_t;
+typedef uint		share_t;
+typedef uchar		private_t;
+
+typedef struct {
+	guard_t		guard1;
+	lock_t		lock[2];
+	share_t		share[2];
+	private_t	private[LLSC_MAXCPUS];
+	share_t		share0;
+	share_t		share1;
+	guard_t		guard2;
+} dataline_t ;
+
+
+#define LINEPAD			k_linepad
+#define LINESTRIDE		(((sizeof(dataline_t)+CACHELINE-1)/CACHELINE)*CACHELINE + LINEPAD)
+
+
+typedef struct {
+	vint		threadstate;
+	uint		threadpasses;
+	private_t	private[MAX_LINECOUNT];
+} threadprivate_t;
+
+typedef struct {
+	vlong		sk_go;		/* 0=idle, 1=init, 2=run */
+	long		sk_linecount;
+	long		sk_passes;
+	long		sk_napticks;
+	long		sk_stop_on_error;
+	long		sk_verbose;
+	long		sk_iter_msg;
+	long		sk_vv;
+	long		sk_linepad;
+	long		sk_options;
+	long		sk_testnumber;
+	vlong		sk_currentpass;
+	void 		*sk_blocks;
+	threadprivate_t	*sk_threadprivate[LLSC_MAXCPUS];
+} control_t;
+
+/* Run state (k_go) constants */
+#define ST_IDLE		0
+#define ST_INIT		1
+#define ST_RUN		2
+#define ST_STOP		3
+#define ST_ERRSTOP	4
+
+
+/* Threadstate constants */
+#define TS_STOPPED	0
+#define	TS_RUNNING	1
+#define TS_KILLED	2
+
+
+
+int llsc_main (int cpuid, long mbasex);
+
diff -Nru a/arch/ia64/sn/kernel/machvec.c b/arch/ia64/sn/kernel/machvec.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/machvec.c	Fri Mar 15 17:51:00 2002
@@ -0,0 +1,18 @@
+#define MACHVEC_PLATFORM_NAME	sn1
+#include <asm/machvec_init.h>
+#include <asm/io.h>
+#include <linux/pci.h>
+void*
+sn1_mk_io_addr_MACRO
+
+dma_addr_t
+sn1_pci_map_single_MACRO
+
+int
+sn1_pci_map_sg_MACRO
+
+unsigned long
+sn1_virt_to_phys_MACRO
+
+void *
+sn1_phys_to_virt_MACRO
diff -Nru a/arch/ia64/sn/kernel/mca.c b/arch/ia64/sn/kernel/mca.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/mca.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,278 @@
+/*
+ * File:	mca.c
+ * Purpose:	SN specific MCA code.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/smp_lock.h>
+#include <linux/kdb.h>
+
+#include <asm/machvec.h>
+#include <asm/page.h>
+#include <asm/ptrace.h>
+#include <asm/system.h>
+#include <asm/sal.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/mca.h>
+#include <asm/sn/mca.h>
+
+#include <asm/irq.h>
+#include <asm/hw_irq.h>
+#include <asm/acpi-ext.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+
+static char *shub_mmr_names[] = {
+	"sh_event_occurred",
+	"sh_first_error",
+	"sh_event_overflow",
+
+/* PI */
+	"sh_pi_first_error",
+	"sh_pi_error_summary",
+	"sh_pi_error_overflow",
+
+/* PI HW */
+	"sh_pi_error_detail_1",
+	"sh_pi_error_detail_2",
+	"sh_pi_hw_time_stamp",
+
+/* PI UCE */
+	"sh_pi_uncorrected_detail_1",
+	"sh_pi_uncorrected_detail_2",
+	"sh_pi_uncorrected_detail_3",
+	"sh_pi_uncorrected_detail_4",
+	"sh_pi_uncor_time_stamp",
+
+/* PI CE */
+	"sh_pi_corrected_detail_1",
+	"sh_pi_corrected_detail_2",
+	"sh_pi_corrected_detail_3",
+	"sh_pi_corrected_detail_4",
+	"sh_pi_cor_time_stamp",
+
+/* MD */
+	"sh_mem_error_summary",
+	"sh_mem_error_overflow",
+/* MD HW */
+	"sh_misc_err_hdr_upper",
+	"sh_misc_err_hdr_lower",
+	"sh_md_dqlp_mmr_xperr_val",
+	"sh_md_dqlp_mmr_yperr_val",
+	"sh_md_dqrp_mmr_xperr_val",
+	"sh_md_dqrp_mmr_yperr_val",
+	"sh_md_hw_time_stamp",
+
+/* MD UCE */
+	"sh_dir_uc_err_hdr_lower",
+	"sh_dir_uc_err_hdr_upper",
+	"sh_md_dqlp_mmr_xuerr1",
+	"sh_md_dqlp_mmr_xuerr2",
+	"sh_md_dqlp_mmr_yuerr1",
+	"sh_md_dqlp_mmr_yuerr2",
+	"sh_md_dqrp_mmr_xuerr1",
+	"sh_md_dqrp_mmr_xuerr2",
+	"sh_md_dqrp_mmr_yuerr1",
+	"sh_md_dqrp_mmr_yuerr2",
+	"sh_md_uncor_time_stamp",
+
+/* MD CE */
+	"sh_dir_cor_err_hdr_lower",
+	"sh_dir_cor_err_hdr_upper",
+	"sh_md_dqlp_mmr_xcerr1",
+	"sh_md_dqlp_mmr_xcerr2",
+	"sh_md_dqlp_mmr_ycerr1",
+	"sh_md_dqlp_mmr_ycerr2",
+	"sh_md_dqrp_mmr_xcerr1",
+	"sh_md_dqrp_mmr_xcerr2",
+	"sh_md_dqrp_mmr_ycerr1",
+	"sh_md_dqrp_mmr_ycerr2",
+	"sh_md_cor_time_stamp",
+
+/* MD CE, UCE */
+	"sh_md_dqls_mmr_xamopw_err",
+	"sh_md_dqrs_mmr_yamopw_err",
+
+/* XN */
+	"sh_xn_error_summary",
+	"sh_xn_first_error",
+	"sh_xn_error_overflow",
+
+/* XN HW */
+	"sh_xniilb_error_summary",
+	"sh_xniilb_first_error",
+	"sh_xniilb_error_overflow",
+	"sh_xniilb_error_detail_1",
+	"sh_xniilb_error_detail_2",
+	"sh_xniilb_error_detail_3",
+
+	"sh_ni0_error_summary_1",
+	"sh_ni0_first_error_1",
+	"sh_ni0_error_overflow_1",
+
+	"sh_ni0_error_summary_2",
+	"sh_ni0_first_error_2",
+	"sh_ni0_error_overflow_2",
+	"sh_ni0_error_detail_1",
+	"sh_ni0_error_detail_2",
+	"sh_ni0_error_detail_3",
+
+	"sh_ni1_error_summary_1",
+	"sh_ni1_first_error_1",
+	"sh_ni1_error_overflow_1",
+
+	"sh_ni1_error_summary_2",
+	"sh_ni1_first_error_2",
+	"sh_ni1_error_overflow_2",
+
+	"sh_ni1_error_detail_1",
+	"sh_ni1_error_detail_2",
+	"sh_ni1_error_detail_3",
+
+	"sh_xn_hw_time_stamp",
+
+/* XN HW & UCE & SBE */
+	"sh_xnpi_error_summary",
+	"sh_xnpi_first_error",
+	"sh_xnpi_error_overflow",
+	"sh_xnpi_error_detail_1",
+
+	"sh_xnmd_error_summary",
+	"sh_xnmd_first_error",
+	"sh_xnmd_error_overflow",
+	"sh_xnmd_ecc_err_report",
+	"sh_xnmd_error_detail_1",
+
+/* XN UCE */
+	"sh_xn_uncorrected_detail_1",
+	"sh_xn_uncorrected_detail_2",
+	"sh_xn_uncorrected_detail_3",
+	"sh_xn_uncorrected_detail_4",
+	"sh_xn_uncor_time_stamp",
+
+/* XN CE */
+	"sh_xn_corrected_detail_1",
+	"sh_xn_corrected_detail_2",
+	"sh_xn_corrected_detail_3",
+	"sh_xn_corrected_detail_4",
+	"sh_xn_cor_time_stamp",
+
+/* LB HW */
+	"sh_lb_error_summary",
+	"sh_lb_first_error",
+	"sh_lb_error_overflow",
+	"sh_lb_error_detail_1",
+	"sh_lb_error_detail_2",
+	"sh_lb_error_detail_3",
+	"sh_lb_error_detail_4",
+	"sh_lb_error_detail_5",
+	"sh_junk_error_status",
+};
+
+void 
+sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc) 
+{
+	sal_log_plat_info_t *sh_info = (sal_log_plat_info_t *) p_data;
+	u64 *mmr_val = (u64 *)&(sh_info->shub_state);
+	char **mmr_name = shub_mmr_names;
+	int mmr_count = sizeof(sal_log_shub_state_t)>>3;
+
+	while(mmr_count) {
+		if(*mmr_val) {
+			prfunc("%-40s: %#016lx\n",*mmr_name, *mmr_val);
+		}
+		mmr_name++;
+		mmr_val++;
+		mmr_count--;
+	}
+
+}
+
+void
+sn_cpei_handler(int irq, void *devid, struct pt_regs *regs) {
+
+        struct ia64_sal_retval isrv;
+// this function's sole purpose is to call SAL when we receive
+// a CE interrupt from SHUB or when the timer routine decides
+// we need to call SAL to check for CEs.
+
+        // CALL SAL_LOG_CE
+        SAL_CALL(isrv, SN_SAL_LOG_CE, irq, 0, 0, 0, 0, 0, 0);
+}
+
+#include <linux/timer.h>
+
+#define CPEI_INTERVAL   (HZ/100)
+struct timer_list sn_cpei_timer;
+void sn_init_cpei_timer(void);
+
+void
+sn_cpei_timer_handler(unsigned long dummy) {
+        sn_cpei_handler(-1, NULL, NULL);
+        del_timer(&sn_cpei_timer);
+        sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
+        add_timer(&sn_cpei_timer);
+}
+
+void
+sn_init_cpei_timer() {
+        sn_cpei_timer.expires = jiffies + CPEI_INTERVAL;
+        sn_cpei_timer.function = sn_cpei_timer_handler;
+        add_timer(&sn_cpei_timer);
+}
+
+#ifdef ajmtestceintr
+
+struct timer_list sn_ce_timer;
+
+void
+sn_ce_timer_handler(long dummy) {
+        unsigned long *pi_ce_error_inject_reg = 0xc00000092fffff00;
+
+        *pi_ce_error_inject_reg = 0x0000000000000100;
+        del_timer(&sn_ce_timer);
+        sn_ce_timer.expires = jiffies + CPEI_INTERVAL;
+        add_timer(&sn_ce_timer);
+}
+
+sn_init_ce_timer() {
+        sn_ce_timer.expires = jiffies + CPEI_INTERVAL;
+        sn_ce_timer.function = sn_ce_timer_handler;
+        add_timer(&sn_ce_timer);
+}
+#endif /* ajmtestceintr */
diff -Nru a/arch/ia64/sn/kernel/misctest.c b/arch/ia64/sn/kernel/misctest.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/misctest.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,122 @@
+/* 
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/sn/sn_sal.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/processor.h>
+#include <asm/pgtable.h>
+
+
+extern	int autotest_enabled;
+int	mcatest=0;
+
+
+
+/* 
+ * mcatest
+ *	1 = expected MCA
+ *	2 = unexpected MCA
+ *	3 = expected MCA + unexpected MCA
+ *	4 = INIT
+ *	5 = speculative load to garbage memory address
+ *	6 = speculative load with ld8.s (needs poison hack in PROM)
+ *	7 = speculative load from mis-predicted branch (needs poison hack in PROM)
+ */
+static int __init set_mcatest(char *str)
+{
+	get_option(&str, &mcatest);
+	return 1;
+}
+
+__setup("mcatest=", set_mcatest);
+
+void
+sgi_mcatest(void)
+{
+	if (mcatest == 1 || mcatest == 3) {
+		long	*p, result, adrs[] = {0xc0000a000f021004UL, 0xc0000a000f026004UL, 0x800000000, 0x500000, 0};
+		long	size[] = {1,2,4,8};
+		int	r, i, j;
+		p = (long*)0xc000000000000000UL;
+		ia64_fc(p);
+		*p = 0x0123456789abcdefL;
+		for (i=0; i<5; i++) {
+			for (j=0; j<4; j++) {
+				printk("Probing 0x%lx, size %ld\n", adrs[i], size[j]);
+				result = -1;
+				r = ia64_sn_probe_io_slot (adrs[i], size[j], &result);
+				printk("    status %d, val 0x%lx\n", r, result); 
+			}
+		}
+	}
+	if (mcatest == 2 || mcatest == 3) {
+		void zzzmca(int, int, int);
+		printk("About to cause unexpected MCA\n");
+		zzzmca(mcatest, 0x32dead, 0x33dead);
+	}
+	if (mcatest == 4) {
+		long	*p;
+		int	delivery_mode = 5;
+		printk("About to try to cause an INIT on cpu 0\n");
+		p = (long*)((0xc0000a0000000000LL | ((long)get_nasid())<<33) | 0x1800080);
+		*p = (delivery_mode << 8);
+		udelay(10000);
+		printk("Returned from INIT\n");
+	}
+	if (mcatest == 5) {
+		int zzzspec(long);
+		int	i;
+		long	flags, dcr, res, val, addr=0xff00000000UL;
+
+		dcr = ia64_get_dcr();
+		for (i=0; i<5; i++) {
+			printk("Default DCR: 0x%lx\n", ia64_get_dcr());
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(0);
+			printk("New     DCR: 0x%lx\n", ia64_get_dcr());
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(dcr);
+			res = ia64_sn_probe_io_slot(0xff00000000UL, 8, &val);
+			printk("zzzspec: probe %ld, 0x%lx\n", res, val);
+			ia64_clear_ic(flags);
+			ia64_itc(0x2, 0xe00000ff00000000UL,
+			          pte_val(mk_pte_phys(0xff00000000UL,
+				  __pgprot(__DIRTY_BITS|_PAGE_PL_0|_PAGE_AR_RW))), _PAGE_SIZE_256M);
+			local_irq_restore(flags);
+			ia64_srlz_i ();
+		}
+
+	}
+	if (mcatest == 6) {
+		int zzzspec(long);
+		int	i;
+		long	dcr, addr=0xe000000008000000UL;
+
+		dcr = ia64_get_dcr();
+		for (i=0; i<5; i++) {
+			printk("zzzspec: 0x%x\n", zzzspec(addr));
+			ia64_set_dcr(0);
+		}
+		ia64_set_dcr(dcr);
+	}
+	if (mcatest == 7) {
+		int zzzspec2(long, long);
+		int	i;
+		long	addr=0xe000000008000000UL;
+		long	addr2=0xe000000007000000UL;
+
+		for (i=0; i<5; i++) {
+			printk("zzzspec2\n");
+			zzzspec2(addr, addr2);
+		}
+	}
+}
diff -Nru a/arch/ia64/sn/kernel/probe.c b/arch/ia64/sn/kernel/probe.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/probe.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,81 @@
+/*
+ * Platform dependent support for IO probing.
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <asm/sn/sn_sal.h>
+
+/**
+ * ia64_sn_probe_io_slot - test a memory location for readability
+ * @paddr: physical address to probe
+ * @size: number bytes to read (1,2,4,8)
+ * @data_ptr: address to store value read by probe (-1 returned if probe fails)
+ *
+ * This function will probe a physical address to determine if
+ * the address can be read. If reading the address causes a BUS
+ * error, an error is returned. If the probe succeeds, the contents 
+ * of the memory location is returned.
+ *
+ * Return values:
+ *  0 - probe successful
+ *  1 - probe failed (generated MCA)
+ *  2 - Bad arg
+ * <0 - PAL error
+ */
+u64
+ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr)
+{
+	struct ia64_sal_retval isrv;
+
+	SAL_CALL(isrv, SN_SAL_PROBE, paddr, size, 0, 0, 0, 0, 0);
+
+	if (data_ptr) {
+		switch (size) {
+			case 1:
+				*((u8*)data_ptr) = (u8)isrv.v0;
+				break;
+			case 2:
+				*((u16*)data_ptr) = (u16)isrv.v0;
+				break;
+			case 4:
+				*((u32*)data_ptr) = (u32)isrv.v0;
+				break;
+			case 8:
+				*((u64*)data_ptr) = (u64)isrv.v0;
+				break;
+			default:
+				isrv.status = 2;	
+		}
+	}
+
+	return isrv.status;
+}
diff -Nru a/arch/ia64/sn/kernel/setup.c b/arch/ia64/sn/kernel/setup.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/setup.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,437 @@
+/*
+ * Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/kdev_t.h>
+#include <linux/string.h>
+#include <linux/tty.h>
+#include <linux/console.h>
+#include <linux/timex.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/serial.h>
+#include <linux/irq.h>
+#include <linux/bootmem.h>
+#include <linux/mmzone.h>
+#include <linux/interrupt.h>
+
+#include <asm/io.h>
+#include <asm/sal.h>
+#include <asm/machvec.h>
+#include <asm/system.h>
+#ifdef CONFIG_IA64_MCA
+#include <asm/acpi-ext.h>
+#endif
+#include <asm/processor.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/io.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/pda.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/simulator.h>
+#include <asm/sn/leds.h>
+#include <asm/sn/bte.h>
+
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/shub.h>
+#endif
+
+extern void bte_init_node (nodepda_t *, cnodeid_t);
+extern void bte_init_cpu (void);
+
+long sn_rtc_cycles_per_second;   
+
+/*
+ * This is the address of the RRegs in the HSpace of the global
+ * master.  It is used by a hack in serial.c (serial_[in|out],
+ * printk.c (early_printk), and kdb_io.c to put console output on that
+ * node's Bedrock UART.  It is initialized here to 0, so that
+ * early_printk won't try to access the UART before
+ * master_node_bedrock_address is properly calculated.
+ */
+u64 master_node_bedrock_address = 0UL;
+
+static void sn_init_pdas(void);
+
+extern struct irq_desc *_sn1_irq_desc[];
+
+#if defined(CONFIG_IA64_SGI_SN1)
+extern synergy_da_t	*Synergy_da_indr[];
+#endif
+
+static nodepda_t	*nodepdaindr[MAX_COMPACT_NODES];
+
+#ifdef CONFIG_IA64_SGI_SN2
+irqpda_t		*irqpdaindr[NR_CPUS];
+#endif /* CONFIG_IA64_SGI_SN2 */
+
+
+/*
+ * The format of "screen_info" is strange, and due to early i386-setup
+ * code. This is just enough to make the console code think we're on a
+ * VGA color display.
+ */
+struct screen_info sn1_screen_info = {
+	orig_x:			 0,
+	orig_y:			 0,
+	orig_video_mode:	 3,
+	orig_video_cols:	80,
+	orig_video_ega_bx:	 3,
+	orig_video_lines:	25,
+	orig_video_isVGA:	 1,
+	orig_video_points:	16
+};
+
+/*
+ * This is here so we can use the CMOS detection in ide-probe.c to
+ * determine what drives are present.  In theory, we don't need this
+ * as the auto-detection could be done via ide-probe.c:do_probe() but
+ * in practice that would be much slower, which is painful when
+ * running in the simulator.  Note that passing zeroes in DRIVE_INFO
+ * is sufficient (the IDE driver will autodetect the drive geometry).
+ */
+char drive_info[4*16];
+
+/**
+ * sn1_map_nr - return the mem_map entry for a given kernel address
+ * @addr: kernel address to query
+ *
+ * Finds the mem_map entry for the kernel address given.  Used by
+ * virt_to_page() (asm-ia64/page.h), among other things.
+ */
+unsigned long
+sn1_map_nr (unsigned long addr)
+{
+	return MAP_NR_DISCONTIG(addr);
+}
+
+/**
+ * early_sn1_setup - early setup routine for SN platforms
+ *
+ * Sets up an intial console to aid debugging.  Intended primarily
+ * for bringup, it's only called if %BRINGUP and %CONFIG_IA64_EARLY_PRINTK
+ * are turned on.  See start_kernel() in init/main.c.
+ */
+#if defined(CONFIG_IA64_EARLY_PRINTK)
+void __init
+early_sn1_setup(void)
+{
+#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	if ( IS_RUNNING_ON_SIMULATOR() )
+#endif
+	{
+#ifdef CONFIG_IA64_SGI_SN2
+		master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0);
+#else
+		master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
+#endif
+		printk(KERN_DEBUG "early_sn1_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address);
+	}
+}
+#endif /* CONFIG_IA64_EARLY_PRINTK */
+
+#ifdef NOT_YET_CONFIG_IA64_MCA
+extern void ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs);
+static struct irqaction mca_cpe_irqaction = { 
+	handler:    ia64_mca_cpe_int_handler,
+	flags:      SA_INTERRUPT,
+	name:       "cpe_hndlr"
+};
+#endif
+#ifdef CONFIG_IA64_MCA
+extern int platform_irq_list[];
+#endif
+
+extern nasid_t master_nasid;
+
+/**
+ * sn1_setup - SN platform setup routine
+ * @cmdline_p: kernel command line
+ *
+ * Handles platform setup for SN machines.  This includes determining
+ * the RTC frequency (via a SAL call), initializing secondary CPUs, and
+ * setting up per-node data areas.  The console is also initialized here.
+ */
+void __init
+sn1_setup(char **cmdline_p)
+{
+	long status, ticks_per_sec, drift;
+	int i;
+
+#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	struct serial_struct req;
+#endif
+
+	master_nasid = get_nasid();
+	(void)get_console_nasid();
+
+	status = ia64_sal_freq_base(SAL_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec, &drift);
+	if (status != 0 || ticks_per_sec < 100000)
+		printk(KERN_WARNING "unable to determine platform RTC clock frequency\n");
+	else
+		sn_rtc_cycles_per_second = ticks_per_sec;
+		
+	for (i=0;i<NR_CPUS;i++)
+		_sn1_irq_desc[i] = _irq_desc;
+
+#ifdef CONFIG_IA64_MCA
+	platform_irq_list[ACPI20_ENTRY_PIS_CPEI] = IA64_PCE_VECTOR;
+#endif
+
+
+#if defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	if ( IS_RUNNING_ON_SIMULATOR() )
+#endif
+	{
+#ifdef CONFIG_IA64_SGI_SN2
+		master_node_bedrock_address = (u64)REMOTE_HUB(get_nasid(), SH_JUNK_BUS_UART0);
+#else
+		master_node_bedrock_address = (u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
+#endif
+		printk(KERN_DEBUG "sn1_setup: setting master_node_bedrock_address to 0x%lx\n",
+		       master_node_bedrock_address);
+	}
+
+#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
+	/*
+	 * We do early_serial_setup() to clean out the rs-table[] from the
+	 * statically compiled in version.
+	 */
+	memset(&req, 0, sizeof(struct serial_struct));
+	req.line = 0;
+	req.baud_base = 124800;
+	req.port = 0;
+	req.port_high = 0;
+	req.irq = 0;
+	req.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST);
+	req.io_type = SERIAL_IO_MEM;
+	req.hub6 = 0;
+#ifdef CONFIG_IA64_SGI_SN2
+	req.iomem_base = (u8 *)(master_node_bedrock_address);
+#else
+	req.iomem_base = (u8 *)(master_node_bedrock_address + 0x80);
+#endif
+	req.iomem_reg_shift = 3;
+	req.type = 0;
+	req.xmit_fifo_size = 0;
+	req.custom_divisor = 0;
+	req.closing_wait = 0;
+	early_serial_setup(&req);
+#endif /* CONFIG_SERIAL && !CONFIG_SERIAL_SGI_L1_PROTOCOL */
+
+	/*
+	 * we set the default root device to /dev/hda
+	 * to make simulation easy
+	 */
+	ROOT_DEV = to_kdev_t(0x0301);
+
+	/*
+	 * Create the PDAs and NODEPDAs for all the cpus.
+	 */
+	sn_init_pdas();
+
+
+	/* 
+	 * For the bootcpu, we do this here. All other cpus will make the
+	 * call as part of cpu_init in slave cpu initialization.
+	 */
+	sn_cpu_init();
+
+
+#ifdef CONFIG_SMP
+	init_smp_config();
+#endif
+	screen_info = sn1_screen_info;
+
+	/*
+	 * Turn off "floating-point assist fault" warnings by default.
+	 */
+	current->thread.flags |= IA64_THREAD_FPEMU_NOPRINT;
+}
+
+/**
+ * sn_init_pdas - setup node data areas
+ *
+ * One time setup for Node Data Area.  Called by sn1_setup().
+ */
+void
+sn_init_pdas(void)
+{
+	cnodeid_t	cnode;
+
+	/*
+	 * Make sure that the PDA fits entirely in the same page as the 
+	 * cpu_data area.
+	 */
+	if ((PDAADDR&~PAGE_MASK)+sizeof(pda_t) > PAGE_SIZE)
+		panic("overflow of cpu_data page");
+
+        /*
+         * Allocate & initalize the nodepda for each node.
+         */
+        for (cnode=0; cnode < numnodes; cnode++) {
+		nodepdaindr[cnode] = alloc_bootmem_node(NODE_DATA(cnode), sizeof(nodepda_t));
+		memset(nodepdaindr[cnode], 0, sizeof(nodepda_t));
+
+#if defined(CONFIG_IA64_SGI_SN1)
+		Synergy_da_indr[cnode * 2] = (synergy_da_t *) alloc_bootmem_node(NODE_DATA(cnode), sizeof(synergy_da_t));
+		Synergy_da_indr[cnode * 2 + 1] = (synergy_da_t *) alloc_bootmem_node(NODE_DATA(cnode), sizeof(synergy_da_t));
+		memset(Synergy_da_indr[cnode * 2], 0, sizeof(synergy_da_t));
+		memset(Synergy_da_indr[cnode * 2 + 1], 0, sizeof(synergy_da_t));
+#endif
+        }
+
+	/*
+	 * Now copy the array of nodepda pointers to each nodepda.
+	 */
+        for (cnode=0; cnode < numnodes; cnode++)
+		memcpy(nodepdaindr[cnode]->pernode_pdaindr, nodepdaindr, sizeof(nodepdaindr));
+
+
+	/*
+	 * Set up IO related platform-dependent nodepda fields.
+	 * The following routine actually sets up the hubinfo struct
+	 * in nodepda.
+	 */
+	for (cnode = 0; cnode < numnodes; cnode++) {
+		init_platform_nodepda(nodepdaindr[cnode], cnode);
+		bte_init_node (nodepdaindr[cnode], cnode);
+	}
+}
+
+/**
+ * sn_cpu_init - initialize per-cpu data areas
+ * @cpuid: cpuid of the caller
+ *
+ * Called during cpu initialization on each cpu as it starts.
+ * Currently, initializes the per-cpu data area for SNIA.
+ * Also sets up a few fields in the nodepda.  Also known as
+ * platform_cpu_init() by the ia64 machvec code.
+ */
+void __init
+sn_cpu_init(void)
+{
+	int	cpuid;
+	int	cpuphyid;
+	int	nasid;
+	int	slice;
+	int	cnode;
+
+	/*
+	 * The boot cpu makes this call again after platform initialization is
+	 * complete.
+	 */
+	if (nodepdaindr[0] == NULL)
+		return;
+
+	cpuid = smp_processor_id();
+	cpuphyid = ((ia64_get_lid() >> 16) & 0xffff);
+	nasid = cpu_physical_id_to_nasid(cpuphyid);
+	cnode = nasid_to_cnodeid(nasid);
+	slice = cpu_physical_id_to_slice(cpuphyid);
+
+	pda.p_nodepda = nodepdaindr[cnode];
+	pda.led_address = (long*) (LED0 + (slice<<LED_CPU_SHIFT));
+	pda.led_state = 0;
+	pda.hb_count = HZ/2;
+	pda.hb_state = 0;
+	pda.idle_flag = 0;
+	
+	if (local_node_data->active_cpu_count == 1)
+		nodepda->node_first_cpu = cpuid;
+
+#ifdef CONFIG_IA64_SGI_SN1
+	{
+		int	synergy;
+		synergy = cpu_physical_id_to_synergy(cpuphyid);
+		pda.p_subnodepda = &nodepdaindr[cnode]->snpda[synergy];
+	}
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN2
+
+	/*
+	 * We must use different memory allocators for first cpu (bootmem 
+	 * allocator) than for the other cpus (regular allocator).
+	 */
+	if (cpuid == 0)
+		irqpdaindr[cpuid] = alloc_bootmem_node(NODE_DATA(cpuid_to_cnodeid(cpuid)),sizeof(irqpda_t));
+	else
+		irqpdaindr[cpuid] = page_address(alloc_pages_node(local_cnodeid(), GFP_KERNEL, get_order(sizeof(irqpda_t))));
+	memset(irqpdaindr[cpuid], 0, sizeof(irqpda_t));
+	pda.p_irqpda = irqpdaindr[cpuid];
+	pda.pio_write_status_addr = (volatile unsigned long *)LOCAL_MMR_ADDR((slice < 2 ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ) );
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN1
+	pda.bedrock_rev_id = (volatile unsigned long *) LOCAL_HUB(LB_REV_ID);
+	if (cpuid_to_synergy(cpuid))
+		/* CPU B */
+		pda.pio_write_status_addr = (volatile unsigned long *) GBL_PERF_B_ADDR;
+	else
+		/* CPU A */
+		pda.pio_write_status_addr = (volatile unsigned long *) GBL_PERF_A_ADDR;
+#endif
+
+
+	bte_init_cpu();
+}
+
+
+/**
+ * cnodeid_to_cpuid - convert a cnode to a cpuid of a cpu on the node.
+ * @cnode: node to get a cpuid from
+ *	
+ * Returns -1 if no cpus exist on the node.
+ * NOTE:BRINGUP ZZZ This is NOT a good way to find cpus on the node.
+ * Need a better way!!
+ */
+int
+cnodeid_to_cpuid(int cnode) {
+	int cpu;
+
+	for (cpu = 0; cpu < smp_num_cpus; cpu++)
+		if (cpuid_to_cnodeid(cpu) == cnode)
+			break;
+
+	if (cpu == smp_num_cpus) 
+		cpu = -1;
+
+	return cpu;
+}
diff -Nru a/arch/ia64/sn/kernel/sn1/Makefile b/arch/ia64/sn/kernel/sn1/Makefile
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn1/Makefile	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,51 @@
+#
+# ia64/platform/sn/sn1/Makefile
+#
+# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it 
+# under the terms of version 2 of the GNU General Public License 
+# as published by the Free Software Foundation.
+# 
+# This program is distributed in the hope that it would be useful, but 
+# WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+# 
+# Further, this software is distributed without any warranty that it is 
+# free of the rightful claim of any third person regarding infringement 
+# or the like.  Any license provided herein, whether implied or 
+# otherwise, applies only to this software file.  Patent licenses, if 
+# any, provided herein do not apply to combinations of this program with 
+# other software, or any other product whatsoever.
+# 
+# You should have received a copy of the GNU General Public 
+# License along with this program; if not, write the Free Software 
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+# 
+# Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+# Mountain View, CA  94043, or:
+# 
+# http://www.sgi.com 
+# 
+# For further information regarding this notice, see: 
+# 
+# http://oss.sgi.com/projects/GenInfo/NoticeExplan
+#
+
+
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+all: sn1.a
+
+O_TARGET        = sn1.a
+
+obj-y          = cache.o error.o iomv.o synergy.o sn1_smp.o
+
+clean::
+
+include $(TOPDIR)/Rules.make
diff -Nru a/arch/ia64/sn/kernel/sn1/cache.c b/arch/ia64/sn/kernel/sn1/cache.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn1/cache.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,81 @@
+/*
+ * 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <asm/pgalloc.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/synergy.h>
+#include <asm/delay.h>
+
+#ifndef MB
+#define	MB	(1024*1024)
+#endif
+
+/*
+ * Lock for protecting SYN_TAG_DISABLE_WAY.
+ * Consider making this a per-FSB lock. 
+ */
+static spinlock_t flush_lock = SPIN_LOCK_UNLOCKED;
+
+/**
+ * sn_flush_all_caches - flush a range of addresses from all caches (incl. L4)
+ * @flush_addr: identity mapped region 7 address to start flushing
+ * @bytes: number of bytes to flush
+ *
+ * Flush a range of addresses from all caches including L4.  All addresses 
+ * fully or partially contained within @flush_addr to @flush_addr + @bytes 
+ * are flushed from the all caches.
+ */
+void
+sn_flush_all_caches(long flush_addr, long bytes)
+{
+	ulong 	addr, baddr, eaddr, bitbucket;
+	int	way, alias;
+
+	/*
+	 * Because of the way synergy implements "fc", this flushes the
+	 * data from all caches on all cpus & L4's on OTHER FSBs. It also
+	 * flushes both cpus on the local FSB. It does NOT flush it from 
+	 * the local FSB.
+	 */
+	flush_icache_range(flush_addr, flush_addr+bytes);
+
+	/*
+	 * Memory DIMMs are a minimum of 256MB and start on 256MB
+	 * boundaries. Convert the start address to an address
+	 * that is between +0MB & +128 of the same DIMM. 
+	 * Then add 8MB to skip the uncached MinState areas if the address
+	 * is on the master node.
+	 */
+	if (bytes > SYNERGY_L4_BYTES_PER_WAY)
+		bytes = SYNERGY_L4_BYTES_PER_WAY;
+	baddr = TO_NODE(smp_physical_node_id(), PAGE_OFFSET + (flush_addr & (128*MB-1)) + 8*MB); 
+	eaddr = (baddr+bytes+SYNERGY_BLOCK_SIZE-1) & ~(SYNERGY_BLOCK_SIZE-1);
+	baddr = baddr & ~(SYNERGY_BLOCK_SIZE-1);
+
+	/*
+	 * Now flush the local synergy.
+	 */
+	spin_lock(&flush_lock);
+	for(way=0; way<SYNERGY_L4_WAYS; way++) {
+		WRITE_LOCAL_SYNERGY_REG(SYN_TAG_DISABLE_WAY, 0xffL ^ (1L<<way));
+		mb();
+		for(alias=0; alias < 9; alias++)
+			for(addr=baddr; addr<eaddr; addr+=SYNERGY_BLOCK_SIZE)
+				bitbucket = *(volatile ulong *)(addr+alias*8*MB);
+		mb();
+	}
+	WRITE_LOCAL_SYNERGY_REG(SYN_TAG_DISABLE_WAY, 0);
+	spin_unlock(&flush_lock);
+
+}
+
+
diff -Nru a/arch/ia64/sn/kernel/sn1/error.c b/arch/ia64/sn/kernel/sn1/error.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn1/error.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,187 @@
+/*
+ * SN1 Platform specific error Support
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/ptrace.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+
+/**
+ * snia_error_intr_handler - handle SN specific error interrupts
+ * @irq: error interrupt received
+ * @devid: device causing the interrupt
+ * @pt_regs: saved register state
+ *
+ * This routine is called when certain interrupts occur on SN systems.
+ * It will either recover from the situations that caused the interrupt
+ * or panic.
+ */
+void
+snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs)
+{
+	unsigned long long intpend_val;
+	unsigned long long bit;
+
+	switch (irq) {
+	case SGI_UART_IRQ:
+		/*
+		 * This isn't really an error interrupt.  We're just
+		 * here because we have to do something with them.
+		 * This is probably wrong, and this code will be
+		 * removed.
+		 */
+		intpend_val = LOCAL_HUB_L(PI_INT_PEND0);
+		if ( (bit = ~(1L<<GFX_INTR_A)) ==
+			(intpend_val & ~(1L<<GFX_INTR_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<GFX_INTR_B)) ==
+			(intpend_val & ~(1L<<GFX_INTR_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<PG_MIG_INTR)) ==
+			(intpend_val & ~(1L<<PG_MIG_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<UART_INTR)) ==
+			(intpend_val & ~(1L<<UART_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<CC_PEND_A)) ==
+			(intpend_val & ~(1L<<CC_PEND_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		if ( (bit = ~(1L<<CC_PEND_B)) ==
+			(intpend_val & ~(1L<<CC_PEND_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			return;
+		}
+		printk("Received SGI_UART_IRQ (65), but no intpend0 bits were set???\n");
+		return;
+	case SGI_HUB_ERROR_IRQ:
+		/*
+		 * These are mostly error interrupts of various
+		 * sorts.  We need to do more than panic here, but
+		 * what the heck, this is bring up.
+		 */
+		intpend_val = LOCAL_HUB_L(PI_INT_PEND1);
+		
+		if ( (bit = ~(1L<<XB_ERROR)) ==
+			(intpend_val & ~(1L<<XB_ERROR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED XB_ERROR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<LB_ERROR)) ==
+			(intpend_val & ~(1L<<LB_ERROR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED LB_ERROR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NACK_INT_A)) ==
+			(intpend_val & ~(1L<<NACK_INT_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NACK_INT_A on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NACK_INT_B)) ==
+			(intpend_val & ~(1L<<NACK_INT_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NACK_INT_B on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<CLK_ERR_INTR)) ==
+			(intpend_val & ~(1L<<CLK_ERR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED CLK_ERR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<COR_ERR_INTR_A)) ==
+			(intpend_val & ~(1L<<COR_ERR_INTR_A)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED COR_ERR_INTR_A on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<COR_ERR_INTR_B)) ==
+			(intpend_val & ~(1L<<COR_ERR_INTR_B)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED COR_ERR_INTR_B on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<MD_COR_ERR_INTR)) ==
+			(intpend_val & ~(1L<<MD_COR_ERR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED MD_COR_ERR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<NI_ERROR_INTR)) ==
+			(intpend_val & ~(1L<<NI_ERROR_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED NI_ERROR_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		if ( (bit = ~(1L<<MSC_PANIC_INTR)) ==
+			(intpend_val & ~(1L<<MSC_PANIC_INTR)) ) {
+			LOCAL_HUB_CLR_INTR(bit);
+			panic("RECEIVED MSC_PANIC_INTR on cpu %d, cnode %d\n",
+				smp_processor_id(), 
+				cpuid_to_cnodeid(smp_processor_id()));
+		}
+		printk("Received SGI_XB_ERROR_IRQ (182) but no intpend1 bits are set???\n");
+		return;
+	default:
+		printk("Received invalid irq in snia_error_intr_handler()\n");
+	}
+}
diff -Nru a/arch/ia64/sn/kernel/sn1/iomv.c b/arch/ia64/sn/kernel/sn1/iomv.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn1/iomv.c	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,219 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <asm/io.h>
+#include <linux/pci.h>
+#include <asm/sn/simulator.h>
+#include <asm/pio_flush.h>
+#include <asm/delay.h>
+
+static inline void *
+sn1_io_addr(unsigned long port)
+{
+	if (!IS_RUNNING_ON_SIMULATOR()) {
+		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
+	} else {
+		unsigned long io_base;
+		unsigned long addr;
+ 
+		/*
+ 		 * word align port, but need more than 10 bits
+ 		 * for accessing registers in bedrock local block
+ 		 * (so we don't do port&0xfff)
+ 		 */
+		if ((port >= 0x1f0 && port <= 0x1f7) ||
+			port == 0x3f6 || port == 0x3f7) {
+			io_base = __IA64_UNCACHED_OFFSET | 0x00000FFFFC000000;
+			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
+		} else {
+			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
+		}
+		return(void *) addr;
+	}
+}
+
+/**
+ * sn1_inb - read a byte from a port
+ * @port: port to read from
+ *
+ * Reads a byte from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inb (unsigned long port)
+{
+return __ia64_inb ( port );
+}
+
+/**
+ * sn1_inw - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inw (unsigned long port)
+{
+return __ia64_inw ( port );
+}
+
+/**
+ * sn1_inl - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inl (unsigned long port)
+{
+return __ia64_inl ( port );
+}
+
+/**
+ * sn1_outb - write a byte to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+return __ia64_outb ( val, port );
+}
+
+/**
+ * sn1_outw - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+return __ia64_outw ( val, port );
+}
+
+/**
+ * sn1_outl - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+return __ia64_outl ( val, port );
+}
+
+/**
+ * sn1_inb - read a byte from a port
+ * @port: port to read from
+ *
+ * Reads a byte from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inb (unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+	unsigned char ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn1_inw - read a word from a port
+ * 2port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inw (unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+	unsigned short ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn1_inl - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inl (unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+	unsigned int ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn1_outb - write a byte to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+/**
+ * sn1_outw - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+/**
+ * sn1_outl - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+#endif /* SN1_IOPORTS */
+
+void
+sn_mmiob ()
+{
+	PIO_FLUSH();
+}
diff -Nru a/arch/ia64/sn/kernel/sn1/sn1_smp.c b/arch/ia64/sn/kernel/sn1/sn1_smp.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn1/sn1_smp.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,449 @@
+/*
+ * SN1 Platform specific SMP Support
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mmzone.h>
+
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/sal.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/hw_irq.h>
+#include <asm/current.h>
+#include <asm/delay.h>
+#include <asm/sn/sn_cpuid.h>
+
+/*
+ * The following structure is used to pass params thru smp_call_function
+ * to other cpus for flushing TLB ranges.
+ */
+typedef struct {
+	unsigned long	start;
+	unsigned long	end;
+	unsigned long	nbits;
+	unsigned int	rid;
+	atomic_t	unfinished_count;
+} ptc_params_t;
+
+#define NUMPTC	512
+
+static ptc_params_t	ptcParamArray[NUMPTC] __attribute__((__aligned__(128)));
+
+/* use separate cache lines on ptcParamsNextByCpu to avoid false sharing */
+static ptc_params_t	*ptcParamsNextByCpu[NR_CPUS*16] __attribute__((__aligned__(128)));
+static volatile ptc_params_t	*ptcParamsEmpty __cacheline_aligned;
+
+/*REFERENCED*/
+static spinlock_t ptcParamsLock __cacheline_aligned = SPIN_LOCK_UNLOCKED;
+
+static int ptcInit = 0;
+#ifdef PTCDEBUG
+static int ptcParamsAllBusy = 0;		/* debugging/statistics */
+static int ptcCountBacklog = 0;
+static int ptcBacklog[NUMPTC+1];
+static char ptcParamsCounts[NR_CPUS][NUMPTC] __attribute__((__aligned__(128)));
+static char ptcParamsResults[NR_CPUS][NUMPTC] __attribute__((__aligned__(128)));
+#endif
+
+/*
+ * Make smp_send_flush_tlbsmp_send_flush_tlb() a weak reference,
+ * so that we get a clean compile with the ia64 patch without the
+ * actual SN1 specific code in arch/ia64/kernel/smp.c.
+ */
+extern void smp_send_flush_tlb (void) __attribute((weak));
+
+/*
+ * The following table/struct is for remembering PTC coherency domains. It
+ * is also used to translate sapicid into cpuids. We dont want to start 
+ * cpus unless we know their cache domain.
+ */
+#ifdef PTC_NOTYET
+sn_sapicid_info_t	sn_sapicid_info[NR_CPUS];
+#endif
+
+/**
+ * sn1_ptc_l_range - purge local translation cache
+ * @start: start of virtual address range
+ * @end: end of virtual address range
+ * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
+ *
+ * Purges the range specified from the local processor's translation cache
+ * (as opposed to the translation registers).  Note that more than the specified
+ * range *may* be cleared from the cache by some processors.
+ *
+ * This is probably not good enough, but I don't want to try to make it better 
+ * until I get some statistics on a running system. At a minimum, we should only 
+ * send IPIs to 1 processor in each TLB domain & have it issue a ptc.g on it's 
+ * own FSB. Also, we only have to serialize per FSB, not globally.
+ *
+ * More likely, we will have to do some work to reduce the frequency of calls to
+ * this routine.
+ */
+static inline void
+sn1_ptc_l_range(unsigned long start, unsigned long end, unsigned long nbits)
+{
+	do {
+		__asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
+		start += (1UL << nbits);
+	} while (start < end);
+	ia64_srlz_d();
+}
+
+/**
+ * sn1_received_flush_tlb - cpu tlb flush routine
+ *
+ * Flushes the TLB of a given processor.
+ */
+void
+sn1_received_flush_tlb(void)
+{
+	unsigned long	start, end, nbits;
+	unsigned int	rid, saved_rid;
+	int		cpu = smp_processor_id();
+	int		result;
+	ptc_params_t	*ptcParams;
+
+	ptcParams = ptcParamsNextByCpu[cpu*16];
+	if (ptcParams == ptcParamsEmpty)
+		return;
+
+	do {
+		start = ptcParams->start;
+		saved_rid = (unsigned int) ia64_get_rr(start);
+		end = ptcParams->end;
+		nbits = ptcParams->nbits;
+		rid = ptcParams->rid;
+
+		if (saved_rid != rid) {
+			ia64_set_rr(start, (unsigned long)rid);
+			ia64_srlz_d();
+		}
+
+		sn1_ptc_l_range(start, end, nbits);
+
+		if (saved_rid != rid) 
+			ia64_set_rr(start, (unsigned long)saved_rid);
+
+		ia64_srlz_i();
+
+		result = atomic_dec(&ptcParams->unfinished_count);
+#ifdef PTCDEBUG
+		{
+		    int i = ptcParams-&ptcParamArray[0];
+		    ptcParamsResults[cpu][i] = (char) result;
+		    ptcParamsCounts[cpu][i]++;
+		}
+#endif /* PTCDEBUG */
+
+		if (++ptcParams == &ptcParamArray[NUMPTC])
+			ptcParams = &ptcParamArray[0];
+
+	} while (ptcParams != ptcParamsEmpty);
+
+	ptcParamsNextByCpu[cpu*16] = ptcParams;
+}
+
+/**
+ * sn1_global_tlb_purge - flush a translation cache range on all processors
+ * @start: start of virtual address range to flush
+ * @end: end of virtual address range
+ * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
+ *
+ * Flushes the translation cache of all processors from @start to @end.
+ */
+void
+sn1_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
+{
+	ptc_params_t	*params;
+	ptc_params_t	*next;
+	unsigned long	irqflags;
+#ifdef PTCDEBUG
+	ptc_params_t	*nextnext;
+	int		backlog = 0;
+#endif
+
+	if (smp_num_cpus == 1) {
+		sn1_ptc_l_range(start, end, nbits);
+		return;
+	}
+
+	if (in_interrupt()) {
+		/*
+		 *  If at interrupt level and cannot get spinlock, 
+		 *  then do something useful by flushing own tlbflush queue
+		 *  so as to avoid a possible deadlock.
+		 */
+		while (!spin_trylock(&ptcParamsLock)) {
+			local_irq_save(irqflags);
+			sn1_received_flush_tlb();
+			local_irq_restore(irqflags);
+			udelay(10);	/* take it easier on the bus */	
+		}
+	} else {
+		spin_lock(&ptcParamsLock);
+	}
+
+	if (!ptcInit) {
+		int cpu;
+		ptcInit = 1;
+		memset(ptcParamArray, 0, sizeof(ptcParamArray));
+		ptcParamsEmpty = &ptcParamArray[0];
+		for (cpu=0; cpu<NR_CPUS; cpu++)
+			ptcParamsNextByCpu[cpu*16] = &ptcParamArray[0];
+
+#ifdef PTCDEBUG
+		memset(ptcBacklog, 0, sizeof(ptcBacklog));
+		memset(ptcParamsCounts, 0, sizeof(ptcParamsCounts));
+		memset(ptcParamsResults, 0, sizeof(ptcParamsResults));
+#endif	/* PTCDEBUG */
+	}
+
+	params = (ptc_params_t *) ptcParamsEmpty;
+	next = (ptc_params_t *) ptcParamsEmpty + 1;
+	if (next == &ptcParamArray[NUMPTC])
+		next = &ptcParamArray[0];
+
+#ifdef PTCDEBUG
+	nextnext = next + 1;
+	if (nextnext == &ptcParamArray[NUMPTC])
+		nextnext = &ptcParamArray[0];
+
+	if (ptcCountBacklog) {
+		/* quick count of backlog */
+		ptc_params_t *ptr;
+
+		/* check the current pointer to the beginning */
+		ptr = params;
+		while(--ptr >= &ptcParamArray[0]) {
+			if (atomic_read(&ptr->unfinished_count) == 0)
+				break;
+			++backlog;
+		}
+
+		if (backlog) {
+			/* check the end of the array */
+			ptr = &ptcParamArray[NUMPTC];
+			while (--ptr > params) {
+				if (atomic_read(&ptr->unfinished_count) == 0)
+					break;
+				++backlog;
+			}
+		}
+		ptcBacklog[backlog]++;
+	}
+#endif	/* PTCDEBUG */
+
+	/* wait for the next entry to clear...should be rare */
+	if (atomic_read(&next->unfinished_count) > 0) {
+#ifdef PTCDEBUG
+		ptcParamsAllBusy++;
+
+		if (atomic_read(&nextnext->unfinished_count) == 0) {
+		    if (atomic_read(&next->unfinished_count) > 0) {
+			panic("\nnonzero next zero nextnext %lx %lx\n",
+			    (long)next, (long)nextnext);
+		    }
+		}
+#endif
+
+		/* it could be this cpu that is behind */
+		local_irq_save(irqflags);
+		sn1_received_flush_tlb();
+		local_irq_restore(irqflags);
+
+		/* now we know it's not this cpu, so just wait */
+		while (atomic_read(&next->unfinished_count) > 0) {
+			barrier();
+		}
+	}
+
+	params->start = start;
+	params->end = end;
+	params->nbits = nbits;
+	params->rid = (unsigned int) ia64_get_rr(start);
+	atomic_set(&params->unfinished_count, smp_num_cpus);
+
+	/* The atomic_set above can hit memory *after* the update
+	 * to ptcParamsEmpty below, which opens a timing window
+	 * that other cpus can squeeze into!
+	 */
+	mb();
+
+	/* everything is ready to process:
+	 *	-- global lock is held
+	 *	-- new entry + 1 is free
+	 *	-- new entry is set up
+	 * so now:
+	 *	-- update the global next pointer
+	 *	-- unlock the global lock
+	 *	-- send IPI to notify other cpus
+	 *	-- process the data ourselves
+	 */
+	ptcParamsEmpty = next;
+	spin_unlock(&ptcParamsLock);
+	smp_send_flush_tlb();
+
+	local_irq_save(irqflags);
+	sn1_received_flush_tlb();
+	local_irq_restore(irqflags);
+
+	/* Currently we don't think global TLB purges need to be atomic.
+	 * All CPUs get sent IPIs, so if they haven't done the purge,
+	 * they're busy with interrupts that are at the IPI level, which is
+	 * priority 15.  We're asserting that any code at that level
+	 * shouldn't be using user TLB entries.  To change this to wait
+	 * for all the flushes to complete, enable the following code.
+	 */
+#ifdef SN1_SYNCHRONOUS_GLOBAL_TLB_PURGE
+	/* this code is not tested */
+	/* wait for the flush to complete */
+	while (atomic_read(&params.unfinished_count) > 1)
+		barrier();
+
+	atomic_set(&params->unfinished_count, 0);
+#endif
+}
+
+/**
+ * sn1_send_IPI - send an IPI to a processor
+ * @cpuid: target of the IPI
+ * @vector: command to send
+ * @delivery_mode: delivery mechanism
+ * @redirect: redirect the IPI?
+ *
+ * Sends an IPI (interprocessor interrupt) to the processor specified by
+ * @cpuid.  @delivery_mode can be one of the following
+ *
+ * %IA64_IPI_DM_INT - pend an interrupt
+ * %IA64_IPI_DM_PMI - pend a PMI
+ * %IA64_IPI_DM_NMI - pend an NMI
+ * %IA64_IPI_DM_INIT - pend an INIT interrupt
+ */
+void
+sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
+{
+	long		*p, nasid, slice;
+	static int 	off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
+
+	/*
+	 * ZZZ - Replace with standard macros when available.
+	 */
+	nasid = cpuid_to_nasid(cpuid);
+	slice = cpuid_to_slice(cpuid);
+	p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
+
+#if defined(ZZZBRINGUP)
+	{
+	static int count=0;
+	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
+		smp_processor_id(), cpuid, vector, nasid, slice, (long)p);
+	}
+#endif
+	mb();
+	*p = (delivery_mode << 8) | (vector & 0xff);
+}
+
+
+#ifdef CONFIG_SMP
+
+#ifdef PTC_NOTYET
+static void __init
+process_sal_ptc_domain_info(ia64_sal_ptc_domain_info_t *di, int domain)
+{
+	ia64_sal_ptc_domain_proc_entry_t	*pe;
+	int 					i, sapicid, cpuid;
+
+	pe = __va(di->proc_list);
+	for (i=0; i<di->proc_count; i++, pe++) {
+		sapicid = id_eid_to_sapicid(pe->id, pe->eid);
+		cpuid = cpu_logical_id(sapicid);
+		sn_sapicid_info[cpuid].domain = domain;
+		sn_sapicid_info[cpuid].sapicid = sapicid;
+	}
+}
+
+
+static void __init
+process_sal_desc_ptc(ia64_sal_desc_ptc_t *ptc)
+{
+	ia64_sal_ptc_domain_info_t	*di;
+	int i;
+
+	di = __va(ptc->domain_info);
+	for (i=0; i<ptc->num_domains; i++, di++) {
+		process_sal_ptc_domain_info(di, i);	
+	}
+}
+#endif /* PTC_NOTYET */
+
+/**
+ * init_sn1_smp_config - setup PTC domains per processor
+ */
+void __init
+init_sn1_smp_config(void)
+{
+	if (!ia64_ptc_domain_info)  {
+		printk("SMP: Can't find PTC domain info. Forcing UP mode\n");
+		smp_num_cpus = 1;
+		return;
+	}
+
+#ifdef PTC_NOTYET
+	memset (sn_sapicid_info, -1, sizeof(sn_sapicid_info));
+	process_sal_desc_ptc(ia64_ptc_domain_info);
+#endif
+}
+
+#else /* CONFIG_SMP */
+
+void __init
+init_sn1_smp_config(void)
+{
+
+#ifdef PTC_NOTYET
+	sn_sapicid_info[0].sapicid = hard_smp_processor_id();
+#endif
+}
+
+#endif /* CONFIG_SMP */
diff -Nru a/arch/ia64/sn/kernel/sn1/synergy.c b/arch/ia64/sn/kernel/sn1/synergy.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn1/synergy.c	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,532 @@
+/*
+ * SN1 Platform specific synergy Support
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/spinlock.h>
+#include <linux/proc_fs.h>
+
+#include <asm/ptrace.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/smp.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/nodepda.h>
+#include <asm/sn/sn1/synergy.h>
+#include <asm/sn/sndrv.h>
+
+int bit_pos_to_irq(int bit);
+void setclear_mask_b(int irq, int cpuid, int set);
+void setclear_mask_a(int irq, int cpuid, int set);
+void * kmalloc(size_t size, int flags);
+
+static int synergy_perf_initialized = 0;
+
+void
+synergy_intr_alloc(int bit, int cpuid) {
+	return;
+}
+
+int
+synergy_intr_connect(int bit, 
+		int cpuid)
+{
+	int irq;
+	unsigned is_b;
+
+	irq = bit_pos_to_irq(bit);
+
+	is_b = (cpuid_to_slice(cpuid)) & 1;
+	if (is_b) {
+		setclear_mask_b(irq,cpuid,1);
+		setclear_mask_a(irq,cpuid, 0);
+	} else {
+		setclear_mask_a(irq, cpuid, 1);
+		setclear_mask_b(irq, cpuid, 0);
+	}
+	return 0;
+}
+void
+setclear_mask_a(int irq, int cpuid, int set)
+{
+	int synergy;
+	int nasid;
+	int reg_num;
+	unsigned long mask;
+	unsigned long addr;
+	unsigned long reg;
+	unsigned long val;
+	int my_cnode, my_synergy;
+	int target_cnode, target_synergy;
+
+        /*
+         * Perform some idiot checks ..
+         */
+        if ( (irq < 0) || (irq > 255) ||
+                (cpuid < 0) || (cpuid > 512) ) {
+                printk("clear_mask_a: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
+		return;
+	}
+
+	target_cnode = cpuid_to_cnodeid(cpuid);
+	target_synergy = cpuid_to_synergy(cpuid);
+	my_cnode = cpuid_to_cnodeid(smp_processor_id());
+	my_synergy = cpuid_to_synergy(smp_processor_id());
+
+	reg_num = irq / 64;
+	mask = 1;
+	mask <<= (irq % 64);
+	switch (reg_num) {
+		case 0: 
+			reg = VEC_MASK0A;
+			addr = VEC_MASK0A_ADDR;
+			break;
+		case 1: 
+			reg = VEC_MASK1A;
+			addr = VEC_MASK1A_ADDR;
+			break;
+		case 2: 
+			reg = VEC_MASK2A;
+			addr = VEC_MASK2A_ADDR;
+			break;
+		case 3: 
+			reg = VEC_MASK3A;
+			addr = VEC_MASK3A_ADDR;
+			break;
+		default:
+			reg = addr = 0;
+			break;
+	}
+	if (my_cnode == target_cnode && my_synergy == target_synergy) {
+		// local synergy
+		val = READ_LOCAL_SYNERGY_REG(addr);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		WRITE_LOCAL_SYNERGY_REG(addr, val);
+		val = READ_LOCAL_SYNERGY_REG(addr);
+	} else { /* remote synergy */
+		synergy = cpuid_to_synergy(cpuid);
+		nasid = cpuid_to_nasid(cpuid);
+		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
+	}
+}
+
+void
+setclear_mask_b(int irq, int cpuid, int set)
+{
+	int synergy;
+	int nasid;
+	int reg_num;
+	unsigned long mask;
+	unsigned long addr;
+	unsigned long reg;
+	unsigned long val;
+	int my_cnode, my_synergy;
+	int target_cnode, target_synergy;
+
+	/*
+	 * Perform some idiot checks ..
+	 */
+	if ( (irq < 0) || (irq > 255) ||
+		(cpuid < 0) || (cpuid > 512) ) {
+		printk("clear_mask_b: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
+		return;
+	}
+
+	target_cnode = cpuid_to_cnodeid(cpuid);
+	target_synergy = cpuid_to_synergy(cpuid);
+	my_cnode = cpuid_to_cnodeid(smp_processor_id());
+	my_synergy = cpuid_to_synergy(smp_processor_id());
+
+	reg_num = irq / 64;
+	mask = 1;
+	mask <<= (irq % 64);
+	switch (reg_num) {
+		case 0: 
+			reg = VEC_MASK0B;
+			addr = VEC_MASK0B_ADDR;
+			break;
+		case 1: 
+			reg = VEC_MASK1B;
+			addr = VEC_MASK1B_ADDR;
+			break;
+		case 2: 
+			reg = VEC_MASK2B;
+			addr = VEC_MASK2B_ADDR;
+			break;
+		case 3: 
+			reg = VEC_MASK3B;
+			addr = VEC_MASK3B_ADDR;
+			break;
+		default:
+			reg = addr = 0;
+			break;
+	}
+	if (my_cnode == target_cnode && my_synergy == target_synergy) {
+		// local synergy
+		val = READ_LOCAL_SYNERGY_REG(addr);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		WRITE_LOCAL_SYNERGY_REG(addr, val);
+		val = READ_LOCAL_SYNERGY_REG(addr);
+	} else { /* remote synergy */
+		synergy = cpuid_to_synergy(cpuid);
+		nasid = cpuid_to_nasid(cpuid);
+		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
+		if (set) {
+			val |= mask;
+		} else {
+			val &= ~mask;
+		}
+		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
+	}
+}
+
+/*
+ * Synergy perf stats. Multiplexed via timer_interrupt.
+ */
+
+static int
+synergy_perf_append(uint64_t modesel)
+{
+	int		cnode;
+	nodepda_t       *npdap;
+	synergy_perf_t	*p;
+	int		checked = 0;
+	int		err = 0;
+
+	/* bit 45 is enable */
+	modesel |= (1UL << 45);
+
+	for (cnode=0; cnode < numnodes; cnode++) {
+		/* for each node, insert a new synergy_perf entry */
+		if ((npdap = NODEPDA(cnode)) == NULL) {
+			printk("synergy_perf_append: cnode=%d NODEPDA(cnode)==NULL, nodepda=%p\n", cnode, (void *)nodepda);
+			continue;
+		}
+
+		if (npdap->synergy_perf_enabled) {
+			/* user must disable counting to append new events */
+			err = -EBUSY;
+			break;
+		}
+
+		if (!checked && npdap->synergy_perf_data != NULL) {
+			checked = 1;
+			for (p = npdap->synergy_perf_first; ;) {
+				if (p->modesel == modesel)
+					return 0; /* event already registered */
+				if ((p = p->next) == npdap->synergy_perf_first)
+					break;
+			}
+		}
+
+		/* XX use kmem_alloc_node() when it is implemented */
+		p = (synergy_perf_t *)kmalloc(sizeof(synergy_perf_t), GFP_KERNEL);
+		if ((((uint64_t)p) & 7UL) != 0)
+			BUG(); /* bad alignment */
+		if (p == NULL) {
+			err = -ENOMEM;
+			break;
+		}
+		else {
+			memset(p, 0, sizeof(synergy_perf_t));
+			p->modesel = modesel;
+
+			spin_lock_irq(&npdap->synergy_perf_lock);
+			if (npdap->synergy_perf_data == NULL) {
+				/* circular list */
+				p->next = p;
+				npdap->synergy_perf_first = p;
+				npdap->synergy_perf_data = p;
+			}
+			else {
+				p->next = npdap->synergy_perf_data->next;
+				npdap->synergy_perf_data->next = p;
+			}
+			spin_unlock_irq(&npdap->synergy_perf_lock);
+		}
+	}
+
+	return err;
+}
+
+static void
+synergy_perf_set_freq(int freq)
+{
+	int		cnode;
+	nodepda_t	*npdap;
+
+	for (cnode=0; cnode < numnodes; cnode++) {
+		if ((npdap = NODEPDA(cnode)) != NULL)
+			npdap->synergy_perf_freq = freq;
+	}
+}
+
+static void
+synergy_perf_set_enable(int enable)
+{
+	int		cnode;
+	nodepda_t	*npdap;
+
+	for (cnode=0; cnode < numnodes; cnode++) {
+		if ((npdap = NODEPDA(cnode)) != NULL)
+			npdap->synergy_perf_enabled = enable;
+	}
+	printk("NOTICE: synergy perf counting %sabled on all nodes\n", enable ? "en" : "dis");
+}
+
+static int
+synergy_perf_size(nodepda_t *npdap)
+{
+	synergy_perf_t	*p;
+	int		n;
+
+	if (npdap->synergy_perf_enabled == 0) {
+		/* no stats to return */
+		return 0;
+	}
+
+	spin_lock_irq(&npdap->synergy_perf_lock);
+	for (n=0, p = npdap->synergy_perf_first; p;) {
+		n++;
+		p = p->next;
+		if (p == npdap->synergy_perf_first)
+			break;
+	}
+	spin_unlock_irq(&npdap->synergy_perf_lock);
+
+	/* bytes == n pairs of {event,counter} */
+	return n * 2 * sizeof(uint64_t);
+}
+
+static int
+synergy_perf_ioctl(struct inode *inode, struct file *file,
+        unsigned int cmd, unsigned long arg)
+{
+	int             cnode;
+	nodepda_t       *npdap;
+	synergy_perf_t	*p;
+	int		intarg;
+	int		fsb;
+	uint64_t	longarg;
+	uint64_t	*stats;
+	int		n;
+	devfs_handle_t	d;
+	arbitrary_info_t info;
+	
+	if ((d = devfs_get_handle_from_inode(inode)) == NULL)
+		return -ENODEV;
+	info = hwgraph_fastinfo_get(d);
+
+	cnode = SYNERGY_PERF_INFO_CNODE(info);
+	fsb = SYNERGY_PERF_INFO_FSB(info);
+	npdap = NODEPDA(cnode);
+
+	switch (cmd) {
+	case SNDRV_GET_SYNERGY_VERSION:
+		/* return int, version of data structure for SNDRV_GET_SYNERGYINFO */
+		intarg = 1; /* version 1 */
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_GET_INFOSIZE:
+		/* return int, sizeof buf needed for SYNERGY_PERF_GET_STATS */
+		intarg = synergy_perf_size(npdap);
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_GET_SYNERGYINFO:
+		/* return array of event/value pairs, this node only */
+		if ((intarg = synergy_perf_size(npdap)) <= 0)
+			return -ENODATA;
+		if ((stats = (uint64_t *)kmalloc(intarg, GFP_KERNEL)) == NULL)
+			return -ENOMEM;
+		spin_lock_irq(&npdap->synergy_perf_lock);
+		for (n=0, p = npdap->synergy_perf_first; p;) {
+			stats[n++] = p->modesel;
+			if (p->intervals > 0)
+			    stats[n++] = p->counts[fsb] * p->total_intervals / p->intervals;
+			else
+			    stats[n++] = 0;
+			p = p->next;
+			if (p == npdap->synergy_perf_first)
+				break;
+		}
+		spin_unlock_irq(&npdap->synergy_perf_lock);
+
+		if (copy_to_user((void *)arg, stats, intarg)) {
+		    kfree(stats);
+		    return -EFAULT;
+		}
+
+		kfree(stats);
+		break;
+
+	case SNDRV_SYNERGY_APPEND:
+		/* reads 64bit event, append synergy perf event to all nodes  */
+		if (copy_from_user(&longarg, (void *)arg, sizeof(longarg)))
+		    return -EFAULT;
+		return synergy_perf_append(longarg);
+		break;
+
+	case SNDRV_GET_SYNERGY_STATUS:
+		/* return int, 1 if enabled else 0 */
+		intarg = npdap->synergy_perf_enabled;
+		if (copy_to_user((void *)arg, &intarg, sizeof(intarg)))
+		    return -EFAULT;
+		break;
+
+	case SNDRV_SYNERGY_ENABLE:
+		/* read int, if true enable counting else disable */
+		if (copy_from_user(&intarg, (void *)arg, sizeof(intarg)))
+		    return -EFAULT;
+		synergy_perf_set_enable(intarg);
+		break;
+
+	case SNDRV_SYNERGY_FREQ:
+		/* read int, set jiffies per update */ 
+		if (copy_from_user(&intarg, (void *)arg, sizeof(intarg)))
+		    return -EFAULT;
+		if (intarg < 0 || intarg >= HZ)
+			return -EINVAL;
+		synergy_perf_set_freq(intarg);
+		break;
+
+	default:
+		printk("Warning: invalid ioctl %d on synergy mon for cnode=%d fsb=%d\n", cmd, cnode, fsb);
+		return -EINVAL;
+	}
+	return(0);
+}
+
+struct file_operations synergy_mon_fops = {
+        ioctl:		synergy_perf_ioctl,
+};
+
+void
+synergy_perf_update(int cpu)
+{
+	nasid_t		nasid;
+	cnodeid_t       cnode;
+	struct nodepda_s *npdap;
+
+	/*
+	 * synergy_perf_initialized is set by synergy_perf_init()
+	 * which is called last thing by sn_mp_setup(), i.e. well
+	 * after nodepda has been initialized.
+	 */
+	if (!synergy_perf_initialized)
+		return;
+
+	cnode = cpuid_to_cnodeid(cpu);
+	npdap = NODEPDA(cnode);
+
+	if (npdap == NULL || cnode < 0 || cnode >= numnodes)
+		/* this should not happen: still in early io init */
+		return;
+
+#if 0
+	/* use this to check nodepda initialization */
+	if (((uint64_t)npdap) & 0x7) {
+		printk("\nERROR on cpu %d : cnode=%d, npdap == %p, not aligned\n", cpu, cnode, npdap);
+		BUG();
+	}
+#endif
+
+	if (npdap->synergy_perf_enabled == 0 || npdap->synergy_perf_data == NULL) {
+		/* Not enabled, or no events to monitor */
+		return;
+	}
+
+	if (npdap->synergy_inactive_intervals++ % npdap->synergy_perf_freq != 0) {
+		/* don't multiplex on every timer interrupt */
+		return;
+	}
+
+	/*
+	 * Read registers for last interval and increment counters.
+	 * Hold the per-node synergy_perf_lock so concurrent readers get
+	 * consistent values.
+	 */
+	spin_lock_irq(&npdap->synergy_perf_lock);
+
+	nasid = cpuid_to_nasid(cpu);
+	npdap->synergy_active_intervals++;
+	npdap->synergy_perf_data->intervals++;
+	npdap->synergy_perf_data->total_intervals = npdap->synergy_active_intervals;
+
+	npdap->synergy_perf_data->counts[0] += 0xffffffffffUL &
+		REMOTE_SYNERGY_LOAD(nasid, 0, PERF_CNTR0_A);
+
+	npdap->synergy_perf_data->counts[1] += 0xffffffffffUL &
+		REMOTE_SYNERGY_LOAD(nasid, 1, PERF_CNTR0_B);
+
+	/* skip to next in circular list */
+	npdap->synergy_perf_data = npdap->synergy_perf_data->next;
+
+	spin_unlock_irq(&npdap->synergy_perf_lock);
+
+	/* set the counter 0 selection modes for both A and B */
+	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTL0_A, npdap->synergy_perf_data->modesel);
+	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTL0_B, npdap->synergy_perf_data->modesel);
+
+	/* and reset the counter registers to zero */
+	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTR0_A, 0UL);
+	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTR0_B, 0UL);
+}
+
+void
+synergy_perf_init(void)
+{
+	printk("synergy_perf_init(), counting is initially disabled\n");
+	synergy_perf_initialized++;
+}
diff -Nru a/arch/ia64/sn/kernel/sn2/Makefile b/arch/ia64/sn/kernel/sn2/Makefile
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn2/Makefile	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,51 @@
+#
+# ia64/platform/sn/sn1/Makefile
+#
+# Copyright (C) 1999,2001-2002 Silicon Graphics, Inc. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify it 
+# under the terms of version 2 of the GNU General Public License 
+# as published by the Free Software Foundation.
+# 
+# This program is distributed in the hope that it would be useful, but 
+# WITHOUT ANY WARRANTY; without even the implied warranty of 
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+# 
+# Further, this software is distributed without any warranty that it is 
+# free of the rightful claim of any third person regarding infringement 
+# or the like.  Any license provided herein, whether implied or 
+# otherwise, applies only to this software file.  Patent licenses, if 
+# any, provided herein do not apply to combinations of this program with 
+# other software, or any other product whatsoever.
+# 
+# You should have received a copy of the GNU General Public 
+# License along with this program; if not, write the Free Software 
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+# 
+# Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+# Mountain View, CA  94043, or:
+# 
+# http://www.sgi.com 
+# 
+# For further information regarding this notice, see: 
+# 
+# http://oss.sgi.com/projects/GenInfo/NoticeExplan
+#
+
+
+EXTRA_CFLAGS    := -DLITTLE_ENDIAN
+
+.S.s:
+	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
+.S.o:
+	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
+
+all: sn2.a
+
+O_TARGET        = sn2.a
+
+obj-y          = cache.o iomv.o sn2_smp.o
+
+clean::
+
+include $(TOPDIR)/Rules.make
diff -Nru a/arch/ia64/sn/kernel/sn2/cache.c b/arch/ia64/sn/kernel/sn2/cache.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn2/cache.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,29 @@
+/*
+ * 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ *
+ */
+
+#include <asm/pgalloc.h>
+
+/**
+ * sn_flush_all_caches - flush a range of address from all caches (incl. L4)
+ * @flush_addr: identity mapped region 7 address to start flushing
+ * @bytes: number of bytes to flush
+ *
+ * Flush a range of addresses from all caches including L4. 
+ * All addresses fully or partially contained within 
+ * @flush_addr to @flush_addr + @bytes are flushed
+ * from the all caches.
+ */
+void
+sn_flush_all_caches(long flush_addr, long bytes)
+{
+	flush_icache_range(flush_addr, flush_addr+bytes);
+}
+
+
diff -Nru a/arch/ia64/sn/kernel/sn2/iomv.c b/arch/ia64/sn/kernel/sn2/iomv.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn2/iomv.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,222 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <asm/io.h>
+#include <linux/pci.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/simulator.h>
+
+#ifdef Colin /* Use the same calls as Generic IA64 defined in io.h */
+/**
+ * sn1_io_addr - convert a in/out port to an i/o address
+ * @port: port to convert
+ *
+ * Legacy in/out instructions are converted to ld/st instructions
+ * on IA64.  This routine will convert a port number into a valid 
+ * SN i/o address.  Used by sn1_in*() and sn1_out*().
+ */
+static inline void *
+sn1_io_addr(unsigned long port)
+{
+	if (!IS_RUNNING_ON_SIMULATOR()) {
+		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
+	} else {
+		unsigned long io_base;
+		unsigned long addr;
+ 
+		/*
+ 		 * word align port, but need more than 10 bits
+ 		 * for accessing registers in bedrock local block
+ 		 * (so we don't do port&0xfff)
+ 		 */
+		if ((port >= 0x1f0 && port <= 0x1f7) ||
+			port == 0x3f6 || port == 0x3f7) {
+			io_base = (0xc000000fcc000000 | ((unsigned long)get_nasid() << 38));
+			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
+		} else {
+			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
+		}
+		return(void *) addr;
+	}
+}
+
+/**
+ * sn1_inb - read a byte from a port
+ * @port: port to read from
+ *
+ * Reads a byte from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inb (unsigned long port)
+{
+return __ia64_inb ( port );
+}
+
+/**
+ * sn1_inw - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inw (unsigned long port)
+{
+return __ia64_inw ( port );
+}
+
+/**
+ * sn1_inl - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inl (unsigned long port)
+{
+return __ia64_inl ( port );
+}
+
+/**
+ * sn1_outb - write a byte to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+return __ia64_outb ( val, port );
+}
+
+/**
+ * sn1_outw - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+return __ia64_outw ( val, port );
+}
+
+/**
+ * sn1_outl - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+return __ia64_outl ( val, port );
+}
+
+/**
+ * sn1_inb - read a byte from a port
+ * @port: port to read from
+ *
+ * Reads a byte from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inb (unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+	unsigned char ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn1_inw - read a word from a port
+ * 2port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inw (unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+	unsigned short ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn1_inl - read a word from a port
+ * @port: port to read from
+ *
+ * Reads a word from @port and returns it to the caller.
+ */
+unsigned int
+sn1_inl (unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+	unsigned int ret;
+
+	ret = *addr;
+	__ia64_mf_a();
+	return ret;
+}
+
+/**
+ * sn1_outb - write a byte to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outb (unsigned char val, unsigned long port)
+{
+	volatile unsigned char *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+/**
+ * sn1_outw - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outw (unsigned short val, unsigned long port)
+{
+	volatile unsigned short *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+/**
+ * sn1_outl - write a word to a port
+ * @port: port to write to
+ * @val: value to write
+ *
+ * Writes @val to @port.
+ */
+void
+sn1_outl (unsigned int val, unsigned long port)
+{
+	volatile unsigned int *addr = sn1_io_addr(port);
+
+	*addr = val;
+	__ia64_mf_a();
+}
+
+#endif
diff -Nru a/arch/ia64/sn/kernel/sn2/sn2_smp.c b/arch/ia64/sn/kernel/sn2/sn2_smp.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn2/sn2_smp.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,159 @@
+/*
+ * SN2 Platform specific SMP Support
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/threads.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mmzone.h>
+
+#include <asm/processor.h>
+#include <asm/irq.h>
+#include <asm/sal.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/smp.h>
+#include <asm/hw_irq.h>
+#include <asm/current.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+
+/**
+ * sn2_global_tlb_purge - globally purge translation cache of virtual address range
+ * @start: start of virtual address range
+ * @end: end of virtual address range
+ * @nbits: specifies number of bytes to purge per instruction (num = 1<<(nbits & 0xfc))
+ *
+ * Purges the translation caches of all processors of the given virtual address
+ * range.
+ */
+void
+sn2_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
+{
+	int		cnode, nasid;
+	volatile long	*ptc0, *ptc1, *piows;
+	unsigned long	ws, next, data0, data1;
+
+	piows = (long*)LOCAL_MMR_ADDR(get_slice() ? SH_PIO_WRITE_STATUS_1 : SH_PIO_WRITE_STATUS_0);
+	data0 = (1UL<<SH_PTC_0_A_SHFT) |
+		(nbits<<SH_PTC_0_PS_SHFT) |
+		((ia64_get_rr(start)>>8)<<SH_PTC_0_RID_SHFT) |
+		(1UL<<SH_PTC_0_START_SHFT);
+
+	ptc0 = (long*)GLOBAL_MMR_ADDR(0, SH_PTC_0);
+	ptc1 = (long*)GLOBAL_MMR_ADDR(0, SH_PTC_1);
+	do {
+		*(piows+1) = -1;	/* use alias address to clear bits*/
+		next = start;
+		do {
+			for (cnode = 0; cnode < numnodes; cnode++) {
+				nasid = cnodeid_to_nasid(cnode);
+				ptc0 = CHANGE_NASID(nasid, ptc0);
+				ptc1 = CHANGE_NASID(nasid, ptc1);
+				data1 = next | (1UL<<SH_PTC_1_START_SHFT);
+				*ptc0 = data0;
+				*ptc1 = data1;
+			}
+			next += (1UL << nbits);
+		} while (next < end);
+
+		while ((ws = *piows) & SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK)
+			;
+
+	} while (ws & SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK);
+
+	
+}
+
+/**
+ * sn2_send_IPI - send an IPI to a processor
+ * @cpuid: target of the IPI
+ * @vector: command to send
+ * @delivery_mode: delivery mechanism
+ * @redirect: redirect the IPI?
+ *
+ * Sends an IPI (InterProcessor Interrupt) to the processor specified by
+ * @cpuid.  @vector specifies the command to send, while @delivery_mode can 
+ * be one of the following
+ *
+ * %IA64_IPI_DM_INT - pend an interrupt
+ * %IA64_IPI_DM_PMI - pend a PMI
+ * %IA64_IPI_DM_NMI - pend an NMI
+ * %IA64_IPI_DM_INIT - pend an INIT interrupt
+ */
+void
+sn2_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
+{
+	long		*p, val;
+	long		physid;
+	long		nasid, slice;
+
+	physid = cpu_physical_id(cpuid);
+	nasid = cpu_physical_id_to_nasid(physid);
+        slice = cpu_physical_id_to_slice(physid);
+
+	p = (long*)GLOBAL_MMR_ADDR(nasid, SH_IPI_INT);
+	val =   (1UL<<SH_IPI_INT_SEND_SHFT) | 
+		(physid<<SH_IPI_INT_PID_SHFT) | 
+	        ((long)delivery_mode<<SH_IPI_INT_TYPE_SHFT) | 
+		((long)vector<<SH_IPI_INT_IDX_SHFT) |
+		(0x000feeUL<<SH_IPI_INT_BASE_SHFT);
+
+#if defined(BRINGUP)
+	{
+	static int count=0;
+	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx, val 0x%lx\n",
+		smp_processor_id(), cpuid, vector, nasid, slice, (long)p, val);
+	}
+#endif
+	mb();
+	*p = val;
+	
+}
+
+/**
+ * init_sn2_smp_config - initialize SN2 smp configuration
+ *
+ * currently a NOP.
+ */
+void __init
+init_sn2_smp_config(void)
+{
+
+}
diff -Nru a/arch/ia64/sn/kernel/sn_asm.S b/arch/ia64/sn/kernel/sn_asm.S
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn_asm.S	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,148 @@
+
+/*
+ * Copyright (c) 2000-2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+
+// Testing only.
+// Routine will cause MCAs
+//   zzzmsa(n)
+//      n=0 MCA via duplicate TLB dropin
+//      n=0 MCA via read of garbage address
+//
+
+#define ITIR(key, ps)           ((key<<8) | (ps<<2))
+#define TLB_PAGESIZE            28                      // Use 256MB pages for now.
+
+                        .global zzzmca
+                        .proc   zzzmca
+zzzmca:
+                        alloc   loc4       = ar.pfs,2,8,1,0;;
+                        cmp.ne  p6,p0=r32,r0;;
+                        movl    r2=0x2dead
+                        movl    r3=0x3dead
+                        movl    r15=0x15dead
+                        movl    r16=0x16dead
+                        movl    r31=0x31dead
+                        movl    loc0=0x34beef
+                        movl    loc1=0x35beef
+                        movl    loc2=0x36beef
+                        movl    loc3=0x37beef
+                        movl    out0=0x42beef
+
+                        movl    r20=0x32feed;;
+                        mov     ar32=r20
+                        movl    r20=0x36feed;;
+                        mov     ar36=r20
+                        movl    r20=0x65feed;;
+                        mov     ar65=r20
+                        movl    r20=0x66feed;;
+                        mov     ar66=r20
+
+(p6)                    br.cond.sptk    1f
+
+                        rsm      0x2000;;
+                        srlz.d;
+                        mov      r11      = 1
+                        mov      r3       = ITIR(0,TLB_PAGESIZE);;
+                        mov      cr.itir  = r3
+                        mov      r10      = 0;;
+                        itr.d    dtr[r11] = r10;;
+                        mov      r11      = 2
+
+                        itr.d    dtr[r11] = r10;;
+                        br      9f
+
+1:                      movl    r8=0xfe00000048;;
+                        ld8     r9=[r8];;
+                        mf
+                        mf.a
+                        srlz.d
+
+9:                      mov     ar.pfs=loc4
+                        br.ret.sptk     rp
+
+                        .endp   zzzmca
+
+                        .global zzzspec
+                        .proc   zzzspec
+zzzspec:
+			mov	r8=r32
+			movl	r9=0xe000000000000000
+			movl	r10=0x4000;;
+			ld8.s	r16=[r8];;
+			ld8.s	r17=[r9];;
+			add	r8=r8,r10;;
+			ld8.s	r18=[r8];;
+			add	r8=r8,r10;;
+			ld8.s	r19=[r8];;
+			add	r8=r8,r10;;
+			ld8.s	r20=[r8];;
+			mov	r8=r0
+			tnat.nz	p6,p0=r16
+			tnat.nz	p7,p0=r17
+			tnat.nz	p8,p0=r18
+			tnat.nz	p9,p0=r19
+			tnat.nz	p10,p0=r20;;
+		(p6)	dep	r8=-1,r8,0,1;;
+		(p7)	dep	r8=-1,r8,1,1;;
+		(p8)	dep	r8=-1,r8,2,1;;
+		(p9)	dep	r8=-1,r8,3,1;;
+		(p10)	dep	r8=-1,r8,4,1;;
+                        br.ret.sptk     rp
+                        .endp   zzzspec
+
+                        .global zzzspec2
+                        .proc   zzzspec2
+zzzspec2:
+			cmp.eq	p6,p7=r2,r2
+			movl	r16=0xc0000a0001000020
+			;;
+			mf
+			;;
+			ld8	r9=[r16]
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			ld8	r9=[r16];;
+			cmp.ne	p6,p7=r9,r16
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			ld8	r9=[r33];;
+			cmp.ne	p6,p7=r9,r33
+		(p6)	br.spnt	1f
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+
+			tpa	r23=r32
+			add	r20=512,r33
+			add	r21=1024,r33;;
+			ld8	r9=[r20]
+			ld8	r10=[r21];;
+			nop.i	0
+			{ .mib
+			nop.m 0
+			cmp.ne	p6,p7=r10,r33
+		(p6)	br.spnt	1f
+			}
+			ld8	r10=[r32]
+			;;
+		1:	mf.a
+			mf
+			br.ret.sptk     rp
+
+                        .endp   zzzspec
+
+#endif
+
diff -Nru a/arch/ia64/sn/kernel/sn_ksyms.c b/arch/ia64/sn/kernel/sn_ksyms.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sn_ksyms.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,64 @@
+/* 
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+/*
+ * Architecture-specific kernel symbols
+ */
+
+#include <linux/config.h>
+#include <linux/module.h>
+
+#include <asm/machvec.h>
+
+/*
+ * other stuff (more to be added later, cleanup then)
+ */
+EXPORT_SYMBOL(sn1_pci_map_sg);
+EXPORT_SYMBOL(sn1_pci_unmap_sg);
+EXPORT_SYMBOL(sn1_pci_alloc_consistent);
+EXPORT_SYMBOL(sn1_pci_free_consistent);
+EXPORT_SYMBOL(sn1_dma_address);
+
+#include <linux/mm.h>
+#include <linux/devfs_fs_kernel.h>
+extern devfs_handle_t          base_io_scsi_ctlr_vhdl[];
+#include <asm/sn/types.h>
+extern cnodeid_t master_node_get(devfs_handle_t vhdl);
+#include <asm/sn/arch.h>
+EXPORT_SYMBOL(base_io_scsi_ctlr_vhdl);
+EXPORT_SYMBOL(master_node_get);
+
+
+/*
+ * symbols referenced by the PCIBA module
+ */
+#include <asm/sn/invent.h>
+#include <asm/sn/hack.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/pci/pciio.h>
+
+devfs_handle_t
+devfn_to_vertex(unsigned char busnum, unsigned int devfn);
+EXPORT_SYMBOL(devfn_to_vertex);
+EXPORT_SYMBOL(hwgraph_vertex_unref);
+EXPORT_SYMBOL(pciio_config_get);
+EXPORT_SYMBOL(pciio_info_slot_get);
+EXPORT_SYMBOL(hwgraph_edge_add);
+EXPORT_SYMBOL(pciio_info_master_get);
+EXPORT_SYMBOL(pciio_info_get);
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+EXPORT_SYMBOL(__pa_debug);
+EXPORT_SYMBOL(__va_debug);
+#endif
+
+/* added by tduffy 04.08.01 to fix depmod issues */
+#include <linux/mmzone.h>
+EXPORT_SYMBOL(sn1_pci_unmap_single);
+EXPORT_SYMBOL(sn1_pci_map_single);
+EXPORT_SYMBOL(sn1_pci_dma_sync_single);
diff -Nru a/arch/ia64/sn/kernel/sv.c b/arch/ia64/sn/kernel/sv.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/ia64/sn/kernel/sv.c	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,552 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved
+ *
+ * This implemenation of synchronization variables is heavily based on
+ * one done by Steve Lord <lord@sgi.com>
+ *
+ * Paul Cassella <pwc@sgi.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/semaphore.h>
+#include <asm/hardirq.h>
+#include <asm/softirq.h>
+#include <asm/current.h>
+
+#include <asm/sn/sv.h>
+
+/* Define this to have sv_test() run some simple tests.
+   kernel_thread() must behave as expected when this is called.  */
+#undef RUN_SV_TEST
+
+#define DEBUG
+
+/* Set up some macros so sv_wait(), sv_signal(), and sv_broadcast()
+   can sanity check interrupt state on architectures where we know
+   how. */
+#ifdef DEBUG
+ #define SV_DEBUG_INTERRUPT_STATE
+ #ifdef __mips64
+  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x1) != 0)
+  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x1) == 0)
+  #define SV_INTERRUPT_TEST_WORKERS 31
+ #elif defined(__ia64)
+  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x4000) != 0)
+  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x4000) == 0)
+  #define SV_INTERRUPT_TEST_WORKERS 4 /* simulator's slow */
+ #else
+  #undef  SV_DEBUG_INTERRUPT_STATE
+  #define SV_INTERRUPT_TEST_WORKERS 4 /* reasonable? default. */
+ #endif /* __mips64 */
+#endif /* DEBUG */
+
+
+/* XXX FIXME hack hack hack.  Our mips64 tree is from before the
+   switch to WQ_FLAG_EXCLUSIVE, and our ia64 tree is from after it. */
+#ifdef TASK_EXCLUSIVE
+  #undef EXCLUSIVE_IN_QUEUE
+#else
+  #define EXCLUSIVE_IN_QUEUE
+  #define TASK_EXCLUSIVE 0 /* for the set_current_state() in sv_wait() */
+#endif
+
+
+static inline void sv_lock(sv_t *sv) {
+	spin_lock(&sv->sv_lock);
+}
+
+static inline void sv_unlock(sv_t *sv) {
+	spin_unlock(&sv->sv_lock);
+}
+
+/* up() is "extern inline", so we can't pass its address to sv_wait.
+   Use this function's address instead. */
+static void up_wrapper(struct semaphore *sem) {
+	up(sem);
+}
+
+/* spin_unlock() is sometimes a macro. */
+static void spin_unlock_wrapper(spinlock_t *s) {
+	spin_unlock(s);
+}
+
+/* XXX Perhaps sv_wait() should do the switch() each time and avoid
+   the extra indirection and the need for the _wrapper functions? */
+
+static inline void sv_set_mon_type(sv_t *sv, int type) {
+	switch (type) {
+	case SV_MON_SPIN:
+		sv->sv_mon_unlock_func =
+		  (sv_mon_unlock_func_t)spin_unlock_wrapper;
+		break;
+	case SV_MON_SEMA:
+		sv->sv_mon_unlock_func =
+		  (sv_mon_unlock_func_t)up_wrapper;
+		if(sv->sv_flags & SV_INTS) {
+			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
+			       "cannot be shared with interrupts if it is a "
+			       "semaphore!\n");
+			BUG();
+		}
+		if(sv->sv_flags & SV_BHS) {
+			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
+			       "cannot be shared with bottom-halves if it is "
+			       "a semaphore!\n");
+			BUG();
+		}
+		break;
+#if 0 
+	/*
+	 * If needed, and will need to think about interrupts.  This
+	 * may be needed, for example, if someone wants to use sv's
+	 * with something like dev_base; writers need to hold two
+	 * locks. 
+	 */
+	case SV_MON_CUSTOM: 
+		{
+		struct sv_mon_custom *c = lock;
+		sv->sv_mon_unlock_func = c->sv_mon_unlock_func;
+		sv->sv_mon_lock        = c->sv_mon_lock;
+		break;
+		}
+#endif
+		
+	default:
+		printk(KERN_ERR "sv_set_mon_type: unknown type %d (0x%x)! "
+		       "(flags 0x%x)\n", type, type, sv->sv_flags);
+		BUG();
+		break;
+	}
+	sv->sv_flags |= type;
+}
+
+static inline void sv_set_ord(sv_t *sv, int ord) {
+	if (!ord)
+		ord = SV_ORDER_DEFAULT;
+
+	if (ord != SV_ORDER_FIFO && ord != SV_ORDER_LIFO) {
+		printk(KERN_EMERG "sv_set_ord: unknown order %d (0x%x)! ",
+		       ord, ord);
+		BUG();
+	}
+
+	sv->sv_flags |= ord;
+}
+
+void sv_init(sv_t *sv, sv_mon_lock_t *lock, int flags) 
+{
+	int ord = flags & SV_ORDER_MASK;
+	int type = flags & SV_MON_MASK;
+
+	/* Copy all non-order, non-type flags */
+	sv->sv_flags = (flags & ~(SV_ORDER_MASK | SV_MON_MASK));
+
+	if((sv->sv_flags & (SV_INTS | SV_BHS)) == (SV_INTS | SV_BHS)) {
+	  printk(KERN_ERR "sv_init: do not set both SV_INTS and SV_BHS, only SV_INTS.\n");
+	  BUG();
+	}
+
+	sv_set_ord(sv, ord);
+	sv_set_mon_type(sv, type);
+
+	/* If lock is NULL, we'll get it from sv_wait_compat() (and
+           ignore it in sv_signal() and sv_broadcast()). */
+	sv->sv_mon_lock = lock;
+
+	spin_lock_init(&sv->sv_lock);
+	init_waitqueue_head(&sv->sv_waiters);
+}
+
+/*
+ * The associated lock must be locked on entry.  It is unlocked on return.
+ *
+ * Return values:
+ *
+ * n < 0 : interrupted,  -n jiffies remaining on timeout, or -1 if timeout == 0
+ * n = 0 : timeout expired
+ * n > 0 : sv_signal()'d, n jiffies remaining on timeout, or 1 if timeout == 0
+ */
+signed long sv_wait(sv_t *sv, int sv_wait_flags, unsigned long timeout) 
+{
+	DECLARE_WAITQUEUE( wait, current );
+	unsigned long flags;
+	signed long ret = 0;
+
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	{
+	unsigned long flags;
+	__save_flags(flags);
+
+	if(sv->sv_flags & SV_INTS) {
+		if(SV_TEST_INTERRUPTS_ENABLED(flags)) {
+			printk(KERN_ERR "sv_wait: SV_INTS and interrupts "
+			       "enabled (flags: 0x%lx)\n", flags);
+			BUG();
+		}
+	} else {
+		if (SV_TEST_INTERRUPTS_DISABLED(flags)) {
+			printk(KERN_WARNING "sv_wait: !SV_INTS and interrupts "
+			       "disabled! (flags: 0x%lx)\n", flags);
+		}
+	}
+	}
+#endif  /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+
+	sv->sv_mon_unlock_func(sv->sv_mon_lock);
+
+	/* Add ourselves to the wait queue and set the state before
+	 * releasing the sv_lock so as to avoid racing with the
+	 * wake_up() in sv_signal() and sv_broadcast(). 
+	 */
+
+	/* don't need the _irqsave part, but there is no wq_write_lock() */
+	wq_write_lock_irqsave(&sv->sv_waiters.lock, flags);
+
+#ifdef EXCLUSIVE_IN_QUEUE
+	wait.flags |= WQ_FLAG_EXCLUSIVE;
+#endif
+
+	switch(sv->sv_flags & SV_ORDER_MASK) {
+	case SV_ORDER_FIFO:
+		__add_wait_queue_tail(&sv->sv_waiters, &wait);
+		break;
+	case SV_ORDER_FILO:
+		__add_wait_queue(&sv->sv_waiters, &wait);
+		break;
+	default:
+		printk(KERN_ERR "sv_wait: unknown order!  (sv: 0x%p, flags: 0x%x)\n",
+					(void *)sv, sv->sv_flags);
+		BUG();
+	}
+	wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags);
+
+	if(sv_wait_flags & SV_WAIT_SIG)
+		set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE  );
+	else
+		set_current_state(TASK_EXCLUSIVE | TASK_UNINTERRUPTIBLE);
+
+	spin_unlock(&sv->sv_lock);
+
+	if(sv->sv_flags & SV_INTS)
+		local_irq_enable();
+	else if(sv->sv_flags & SV_BHS)
+		local_bh_enable();
+
+	if (timeout)
+		ret = schedule_timeout(timeout);
+	else
+		schedule();
+
+	if(current->state != TASK_RUNNING) /* XXX Is this possible? */ {
+		printk(KERN_ERR "sv_wait: state not TASK_RUNNING after "
+		       "schedule().\n");
+		set_current_state(TASK_RUNNING);
+	}
+
+	remove_wait_queue(&sv->sv_waiters, &wait);
+
+	/* Return cases:
+	   - woken by a sv_signal/sv_broadcast
+	   - woken by a signal
+	   - woken by timeout expiring
+	*/
+
+	/* XXX This isn't really accurate; we may have been woken
+           before the signal anyway.... */
+	if(signal_pending(current))
+		return timeout ? -ret : -1;
+	return timeout ? ret : 1;
+}
+
+
+void sv_signal(sv_t *sv) 
+{
+	/* If interrupts can acquire this lock, they can also acquire the
+	   sv_mon_lock, which we must already have to have called this, so
+	   interrupts must be disabled already.  If interrupts cannot
+	   contend for this lock, we don't have to worry about it. */
+
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	if(sv->sv_flags & SV_INTS) {
+		unsigned long flags;
+		__save_flags(flags);
+		if(SV_TEST_INTERRUPTS_ENABLED(flags))
+			printk(KERN_ERR "sv_signal: SV_INTS and "
+			"interrupts enabled! (flags: 0x%lx)\n", flags);
+	}
+#endif /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+	wake_up(&sv->sv_waiters);
+	sv_unlock(sv);
+}
+
+void sv_broadcast(sv_t *sv) 
+{
+#ifdef SV_DEBUG_INTERRUPT_STATE
+	if(sv->sv_flags & SV_INTS) {
+		unsigned long flags;
+		__save_flags(flags);
+		if(SV_TEST_INTERRUPTS_ENABLED(flags))
+			printk(KERN_ERR "sv_broadcast: SV_INTS and "
+			       "interrupts enabled! (flags: 0x%lx)\n", flags);
+	}
+#endif /* SV_DEBUG_INTERRUPT_STATE */
+
+	sv_lock(sv);
+	wake_up_all(&sv->sv_waiters);
+	sv_unlock(sv);
+}
+
+void sv_destroy(sv_t *sv) 
+{
+	if(!spin_trylock(&sv->sv_lock)) {
+		printk(KERN_ERR "sv_destroy: someone else has sv 0x%p locked!\n", (void *)sv);
+		BUG();
+	}
+
+	/* XXX Check that the waitqueue is empty? 
+	       Mark the sv destroyed?
+	*/
+}
+
+
+#ifdef RUN_SV_TEST
+
+static DECLARE_MUTEX_LOCKED(talkback);
+static DECLARE_MUTEX_LOCKED(sem);
+sv_t sv;
+sv_t sv_filo;
+
+static int sv_test_1_w(void *arg) 
+{
+	printk("sv_test_1_w: acquiring spinlock 0x%p...\n", arg);
+
+	spin_lock((spinlock_t*)arg);
+	printk("sv_test_1_w: spinlock acquired, waking sv_test_1_s.\n");
+
+	up(&sem);
+
+	printk("sv_test_1_w: sv_spin_wait()'ing.\n");
+
+	sv_spin_wait(&sv, arg);
+
+	printk("sv_test_1_w: talkback.\n");
+	up(&talkback);
+
+	printk("sv_test_1_w: exiting.\n");
+	return 0;
+}
+
+static int sv_test_1_s(void *arg) 
+{
+	printk("sv_test_1_s: waiting for semaphore.\n");
+	down(&sem);
+	printk("sv_test_1_s: semaphore acquired.  Acquiring spinlock.\n");
+	spin_lock((spinlock_t*)arg);
+	printk("sv_test_1_s: spinlock acquired.  sv_signaling.\n");
+	sv_signal(&sv);
+	printk("sv_test_1_s: talkback.\n");
+	up(&talkback);
+	printk("sv_test_1_s: exiting.\n");
+	return 0;
+
+}
+
+static int count;
+static DECLARE_MUTEX(monitor);
+
+static int sv_test_2_w(void *arg) 
+{
+	int dummy = count++;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	up(&talkback);
+	printk("sv_test_2_w: thread %d started, sv_waiting.\n", dummy);
+	sv_sema_wait(sv, &monitor);
+	printk("sv_test_2_w: thread %d woken, exiting.\n", dummy);
+	up(&sem);
+	return 0;
+}
+
+static int sv_test_2_s_1(void *arg) 
+{
+	int i;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	for(i = 0; i < 3; i++) {
+		printk("sv_test_2_s_1: waking one thread.\n");
+		sv_signal(sv);
+		down(&sem);
+	}
+
+	printk("sv_test_2_s_1: signaling and broadcasting again.  Nothing should happen.\n");
+	sv_signal(sv);
+	sv_broadcast(sv);
+	sv_signal(sv);
+	sv_broadcast(sv);
+
+	printk("sv_test_2_s_1: talkbacking.\n");
+	up(&talkback);
+	up(&monitor);
+	return 0;
+}
+
+static int sv_test_2_s(void *arg) 
+{
+	int i;
+	sv_t *sv = (sv_t *)arg;
+
+	down(&monitor);
+	for(i = 0; i < 3; i++) {
+		printk("sv_test_2_s: waking one thread (should be %d.)\n", i);
+		sv_signal(sv);
+		down(&sem);
+	}
+
+	printk("sv_test_3_s: waking remaining threads with broadcast.\n");
+	sv_broadcast(sv);
+	for(; i < 10; i++)
+		down(&sem);
+
+	printk("sv_test_3_s: sending talkback.\n");
+	up(&talkback);
+
+	printk("sv_test_3_s: exiting.\n");
+	up(&monitor);
+	return 0;
+}
+
+
+static void big_test(sv_t *sv) 
+{
+	int i;
+
+	count = 0;
+
+	for(i = 0; i < 3; i++) {
+		printk("big_test: spawning thread %d.\n", i);
+		kernel_thread(sv_test_2_w, sv, 0);
+		down(&talkback);
+	}
+
+	printk("big_test: spawning first wake-up thread.\n");
+	kernel_thread(sv_test_2_s_1, sv, 0);
+
+	down(&talkback);
+	printk("big_test: talkback happened.\n");
+
+
+	for(i = 3; i < 13; i++) {
+		printk("big_test: spawning thread %d.\n", i);
+		kernel_thread(sv_test_2_w, sv, 0);
+		down(&talkback);
+	}
+
+	printk("big_test: spawning wake-up thread.\n");
+	kernel_thread(sv_test_2_s, sv, 0);
+
+	down(&talkback);
+}
+
+sv_t int_test_sv;
+spinlock_t int_test_spin = SPIN_LOCK_UNLOCKED;
+int int_test_ready;
+static int irqtestcount;
+
+static int interrupt_test_worker(void *unused) 
+{
+	int id = ++irqtestcount;
+	int it = 0;
+			unsigned long flags, flags2;
+
+	printk("ITW: thread %d started.\n", id);
+
+	while(1) {
+		__save_flags(flags2);
+		if(jiffies % 3) {
+			printk("ITW %2d %5d: irqsaving          (%lx)\n", id, it, flags2);
+			spin_lock_irqsave(&int_test_spin, flags);
+		} else {
+			printk("ITW %2d %5d: spin_lock_irqing   (%lx)\n", id, it, flags2);
+			spin_lock_irq(&int_test_spin);
+		}
+
+		__save_flags(flags2);
+		printk("ITW %2d %5d: locked, sv_waiting (%lx).\n", id, it, flags2);
+		sv_wait(&int_test_sv, 0, 0);
+
+		__save_flags(flags2);
+		printk("ITW %2d %5d: wait finished      (%lx), pausing\n", id, it, flags2);
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(jiffies & 0xf);
+		if(current->state != TASK_RUNNING)
+		  printk("ITW:  current->state isn't RUNNING after schedule!\n");
+		it++;
+	}
+}
+
+static void interrupt_test(void) 
+{
+	int i;
+
+	printk("interrupt_test: initing sv.\n");
+	sv_init(&int_test_sv, &int_test_spin, SV_MON_SPIN | SV_INTS);
+
+	for(i = 0; i < SV_INTERRUPT_TEST_WORKERS; i++) {
+		printk("interrupt_test: starting test thread %d.\n", i);
+		kernel_thread(interrupt_test_worker, 0, 0);
+	}
+	printk("interrupt_test: done with init part.\n");
+	int_test_ready = 1;
+}
+
+int sv_test(void) 
+{
+	spinlock_t s = SPIN_LOCK_UNLOCKED;
+
+	sv_init(&sv, &s, SV_MON_SPIN);
+	printk("sv_test: starting sv_test_1_w.\n");
+	kernel_thread(sv_test_1_w, &s, 0);
+	printk("sv_test: starting sv_test_1_s.\n");
+	kernel_thread(sv_test_1_s, &s, 0);
+
+	printk("sv_test: waiting for talkback.\n");
+	down(&talkback); down(&talkback);
+	printk("sv_test: talkback happened, sv_destroying.\n");
+	sv_destroy(&sv);
+
+	count = 0;
+
+	printk("sv_test: beginning big_test on sv.\n");
+
+	sv_init(&sv, &monitor, SV_MON_SEMA);
+	big_test(&sv);
+	sv_destroy(&sv);
+
+	printk("sv_test: beginning big_test on sv_filo.\n");
+	sv_init(&sv_filo, &monitor, SV_MON_SEMA | SV_ORDER_FILO);
+	big_test(&sv_filo);
+	sv_destroy(&sv_filo);
+
+	interrupt_test();
+
+	printk("sv_test: done.\n");
+	return 0;
+}
+
+__initcall(sv_test);
+
+#endif /* RUN_SV_TEST */
diff -Nru a/arch/ia64/sn/sn1/Makefile b/arch/ia64/sn/sn1/Makefile
--- a/arch/ia64/sn/sn1/Makefile	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,31 +0,0 @@
-#
-# ia64/platform/sn/sn1/Makefile
-#
-# Copyright (C) 1999 Silicon Graphics, Inc.
-# Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
-#
-
-EXTRA_CFLAGS	:= -DSN -DLANGUAGE_C=1 -D_LANGUAGE_C=1 -I. -DBRINGUP \
-		   -DDIRECT_L1_CONSOLE -DNUMA_BASE -DSIMULATED_KLGRAPH \
-		   -DNUMA_MIGR_CONTROL -DLITTLE_ENDIAN -DREAL_HARDWARE \
-		   -DNEW_INTERRUPTS
-
-.S.s:
-	$(CPP) $(AFLAGS) $(AFLAGS_KERNEL) -o $*.s $<
-.S.o:
-	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $*.o $<
-
-all: sn1.a
-
-O_TARGET        = sn1.a
-
-obj-y          = irq.o setup.o iomv.o mm.o smp.o synergy.o sn1_asm.o \
-		discontig.o probe.o error.o sv.o
-
-obj-$(CONFIG_IA64_SGI_AUTOTEST)	+= llsc4.o
-obj-$(CONFIG_IA64_GENERIC)	+= machvec.o
-obj-$(CONFIG_MODULES)		+= sn1_ksyms.o
-
-clean::
-
-include $(TOPDIR)/Rules.make
diff -Nru a/arch/ia64/sn/sn1/discontig.c b/arch/ia64/sn/sn1/discontig.c
--- a/arch/ia64/sn/sn1/discontig.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,159 +0,0 @@
-/*
- * Copyright 2000, Silicon Graphics, sprasad@engr.sgi.com
- * Copyright 2000, Kanoj Sarcar, kanoj@sgi.com
- */
-
-/*
- * Contains common definitions and globals for NUMA platform
- * support. For now, SN-IA64 and SN-MIPS are the NUMA platforms.
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/sn/mmzone.h>
-#include <asm/efi.h>
-
-extern int numnodes ;
-
-plat_pg_data_t plat_node_data[MAXNODES];
-bootmem_data_t bdata[MAXNODES];
-int chunktonid[MAXCHUNKS];
-int nasid_map[MAXNASIDS];
-
-void __init
-init_chunktonid(void)
-{
-	memset(chunktonid, -1, sizeof(chunktonid)) ;
-}
-
-void __init
-init_nodeidmap(void)
-{
-	memset(nasid_map, -1, sizeof(nasid_map)) ;
-}
-
-int		cnodeid_map[MAXNODES] ;
-void __init
-init_cnodeidmap(void)
-{
-	memset(cnodeid_map, -1, sizeof(cnodeid_map)) ;
-}
-
-int
-numa_debug(void)
-{
-       panic("NUMA debug\n");
-       return(0);
-}
-
-int __init
-build_cnodeid_map(void)
-{
-	int	i,j ;
-
-	for (i=0,j=0;i<MAXNASIDS;i++) {
-		if (nasid_map[i] >= 0)
-			cnodeid_map[j++] = i ;
-	}
-	return j ;
-}
-
-/*
- * Since efi_memmap_walk merges contiguous banks, this code will need
- * to find all the nasids covered by the input memory descriptor.
- */
-static int __init
-build_nasid_map(unsigned long start, unsigned long end, void *arg)
-{
-	unsigned long vaddr = start;
-	int nasid = GetNasId(__pa(vaddr));
-
-	while (vaddr < end) {
-		if (nasid < MAXNASIDS)
-			nasid_map[nasid] = 0;
-		else
-			panic("build_nasid_map");
-		vaddr = (unsigned long)__va((unsigned long)(++nasid) << 
-							SN1_NODE_ADDR_SHIFT);
-	}
-	return 0;
-}
-
-void __init
-fix_nasid_map(void)
-{
-	int	i ;
-	int		j ;
-
-	/* For every nasid */
-	for (j=0;j<MAXNASIDS;j++) {
-		for (i=0;i<MAXNODES;i++) {
-			if (CNODEID_TO_NASID(i) == j)
-				break ;
-		}
-		if (i<MAXNODES)
-			nasid_map[j] = i ;
-	}
-}
-
-static void __init
-dump_bootmem_info(void)
-{
-        int     i;
-        struct bootmem_data *bdata ;
-
-	printk("CNODE INFO ....\n") ;
-        for (i=0;i<numnodes;i++) {
-		printk("%d ", CNODEID_TO_NASID(i)) ;
-	}
-	printk("\n") ;
-
-	printk("BOOT MEM INFO ....\n") ;
-        printk("Node   Start                LowPfn               BootmemMap\n") ;
-        for (i=0;i<numnodes;i++) {
-                bdata = NODE_DATA(i)->bdata ;
-                printk("%d      0x%016lx   0x%016lx   0x%016lx\n", i,
-                        bdata->node_boot_start, bdata->node_low_pfn,
-                        (unsigned long)bdata->node_bootmem_map) ;
-        }
-}
-
-void __init
-discontig_mem_init(void)
-{
-	extern void setup_sn1_bootmem(int);
-	int		maxnodes ;
-
-        init_chunktonid() ;
-	init_nodeidmap() ;
-	init_cnodeidmap() ;
-	efi_memmap_walk(build_nasid_map, 0) ;
-	maxnodes = build_cnodeid_map() ;
-	fix_nasid_map() ;
-#ifdef CONFIG_DISCONTIGMEM
-	setup_sn1_bootmem(maxnodes) ;
-#endif
-	numnodes = maxnodes;
-	dump_bootmem_info() ;
-}
-
-void
-dump_node_data(void)
-{
-        int     i;
-
-	printk("NODE DATA ....\n") ;
-	printk("Node, Start, Size, MemMap, BitMap, StartP, Mapnr, Size, Id\n") ;
-        for (i=0;i<numnodes;i++) {
-		printk("%d, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx, %d\n", 
-			CNODEID_TO_NASID(i), NODE_START(i), NODE_SIZE(i), 
-			(long)NODE_MEM_MAP(i), (long)NODE_DATA(i)->valid_addr_bitmap, 
-			NODE_DATA(i)->node_start_paddr, 
-			NODE_DATA(i)->node_start_mapnr,
-			NODE_DATA(i)->node_size,
-			NODE_DATA(i)->node_id)  ;
-	}
-}
-
diff -Nru a/arch/ia64/sn/sn1/error.c b/arch/ia64/sn/sn1/error.c
--- a/arch/ia64/sn/sn1/error.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,149 +0,0 @@
-
-
-/*
- * SN1 Platform specific error Support
- *
- * Copyright (C) 2001 Silicon Graphics, Inc.
- * Copyright (C) 2001 Alan Mayer (ajm@sgi.com)
- */
-
-
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-
-#include <asm/ptrace.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/smp.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-
-void
-snia_error_intr_handler(int irq, void *devid, struct pt_regs *pt_regs) {
-	unsigned long long intpend_val;
-	unsigned long long bit;
-
-	switch (irq) {
-	case SGI_UART_IRQ:
-		// This isn't really an error interrupt.  We're just
-		// here because we have to do something with them.
-		// This is probably wrong, and this code will be
-		// removed.
-		intpend_val = LOCAL_HUB_L(PI_INT_PEND0);
-		if ( (bit = ~(1L<<GFX_INTR_A)) ==
-			(intpend_val & ~(1L<<GFX_INTR_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<GFX_INTR_B)) ==
-			(intpend_val & ~(1L<<GFX_INTR_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<PG_MIG_INTR)) ==
-			(intpend_val & ~(1L<<PG_MIG_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<UART_INTR)) ==
-			(intpend_val & ~(1L<<UART_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<CC_PEND_A)) ==
-			(intpend_val & ~(1L<<CC_PEND_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		if ( (bit = ~(1L<<CC_PEND_B)) ==
-			(intpend_val & ~(1L<<CC_PEND_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			return;
-		}
-		printk("Received SGI_UART_IRQ (65), but no intpend0 bits were set???\n");
-		return;
-	case SGI_HUB_ERROR_IRQ:
-		// These are mostly error interrupts of various
-		// sorts.  We need to do more than panic here, but
-		// what the heck, this is bring up.
-		intpend_val = LOCAL_HUB_L(PI_INT_PEND1);
-		
-		if ( (bit = ~(1L<<XB_ERROR)) ==
-			(intpend_val & ~(1L<<XB_ERROR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED XB_ERROR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<LB_ERROR)) ==
-			(intpend_val & ~(1L<<LB_ERROR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED LB_ERROR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NACK_INT_A)) ==
-			(intpend_val & ~(1L<<NACK_INT_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NACK_INT_A on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NACK_INT_B)) ==
-			(intpend_val & ~(1L<<NACK_INT_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NACK_INT_B on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<CLK_ERR_INTR)) ==
-			(intpend_val & ~(1L<<CLK_ERR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED CLK_ERR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<COR_ERR_INTR_A)) ==
-			(intpend_val & ~(1L<<COR_ERR_INTR_A)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED COR_ERR_INTR_A on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<COR_ERR_INTR_B)) ==
-			(intpend_val & ~(1L<<COR_ERR_INTR_B)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED COR_ERR_INTR_B on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<MD_COR_ERR_INTR)) ==
-			(intpend_val & ~(1L<<MD_COR_ERR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED MD_COR_ERR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<NI_ERROR_INTR)) ==
-			(intpend_val & ~(1L<<NI_ERROR_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED NI_ERROR_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		if ( (bit = ~(1L<<MSC_PANIC_INTR)) ==
-			(intpend_val & ~(1L<<MSC_PANIC_INTR)) ) {
-			LOCAL_HUB_CLR_INTR(bit);
-			panic("RECEIVED MSC_PANIC_INTR on cpu %d, cnode %d\n",
-				smp_processor_id(), 
-				cpuid_to_cnodeid(smp_processor_id()));
-		}
-		printk("Received SGI_XB_ERROR_IRQ (182) but no intpend1 bits are set???\n");
-		return;
-	default:
-		printk("Received invalid irq in snia_error_intr_handler()/n");
-	}
-}
diff -Nru a/arch/ia64/sn/sn1/iomv.c b/arch/ia64/sn/sn1/iomv.c
--- a/arch/ia64/sn/sn1/iomv.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,97 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- * Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <asm/io.h>
-#include <linux/pci.h>
-
-static inline void *
-sn1_io_addr(unsigned long port)
-{
-	if (!IS_RUNNING_ON_SIMULATOR()) {
-		return( (void *)  (port | __IA64_UNCACHED_OFFSET));
-	} else {
-		unsigned long io_base;
-		unsigned long addr;
- 
-		/*
- 		 * word align port, but need more than 10 bits
- 		 * for accessing registers in bedrock local block
- 		 * (so we don't do port&0xfff)
- 		 */
-		if (port >= 0x1f0 && port <= 0x1f7 ||
-			port == 0x3f6 || port == 0x3f7) {
-			io_base = __IA64_UNCACHED_OFFSET | 0x00000FFFFC000000;
-			addr = io_base | ((port >> 2) << 12) | (port & 0xfff);
-		} else {
-			addr = __ia64_get_io_port_base() | ((port >> 2) << 2);
-		}
-		return(void *) addr;
-	}
-}
-
-unsigned int
-sn1_inb (unsigned long port)
-{
-	volatile unsigned char *addr = sn1_io_addr(port);
-	unsigned char ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-unsigned int
-sn1_inw (unsigned long port)
-{
-	volatile unsigned short *addr = sn1_io_addr(port);
-	unsigned short ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-unsigned int
-sn1_inl (unsigned long port)
-{
-	volatile unsigned int *addr = sn1_io_addr(port);
-	unsigned int ret;
-
-	ret = *addr;
-	__ia64_mf_a();
-	return ret;
-}
-
-void
-sn1_outb (unsigned char val, unsigned long port)
-{
-	volatile unsigned char *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
-
-void
-sn1_outw (unsigned short val, unsigned long port)
-{
-	volatile unsigned short *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
-
-void
-sn1_outl (unsigned int val, unsigned long port)
-{
-	volatile unsigned int *addr = sn1_io_addr(port);
-
-	*addr = val;
-	__ia64_mf_a();
-}
diff -Nru a/arch/ia64/sn/sn1/irq.c b/arch/ia64/sn/sn1/irq.c
--- a/arch/ia64/sn/sn1/irq.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,183 +0,0 @@
-/*
- * Platform dependent support for SGI SN1
- *
- * Copyright (C) 2000   Silicon Graphics
- * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
- * Copyright (C) 2000   Alan Mayer (ajm@sgi.com)
- * Copyright (C) 2000   Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <asm/current.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-#include <asm/sn/sgi.h>
-#include <asm/sn/iograph.h>
-#include <asm/sn/invent.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/sn/hcl.h>
-#include <asm/sn/types.h>
-#include <asm/sn/pci/bridge.h>
-#include <asm/sn/pci/pciio.h>
-#include <asm/sn/pci/pciio_private.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn1/addrs.h>
-#include <asm/sn/iobus.h>
-#include <asm/sn/sn1/arch.h>
-#include <asm/sn/synergy.h>
-
-#define IRQ_BIT_OFFSET 64
-
-int bit_pos_to_irq(int bit)
-{
-	if (bit > 118)
-		bit = 118;
-	return (bit + IRQ_BIT_OFFSET);
-}
-
-static inline int irq_to_bit_pos(int irq)
-{
-	int bit = irq - IRQ_BIT_OFFSET;
-
-	if (bit > 63)
-		bit -= 64;
-	return bit;
-}
-
-static unsigned int
-sn1_startup_irq(unsigned int irq)
-{
-        return(0);
-}
-
-static void
-sn1_shutdown_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_disable_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_enable_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_ack_irq(unsigned int irq)
-{
-}
-
-static void
-sn1_end_irq(unsigned int irq)
-{
-	int bit;
-
-	bit = irq_to_bit_pos(irq);
-	LOCAL_HUB_CLR_INTR(bit);
-}
-
-static void
-sn1_set_affinity_irq(unsigned int irq, unsigned long mask)
-{
-}
-
-struct hw_interrupt_type irq_type_sn1 = {
-        "sn1_irq",
-        sn1_startup_irq,
-        sn1_shutdown_irq,
-        sn1_enable_irq,
-        sn1_disable_irq,
-        sn1_ack_irq,
-        sn1_end_irq,
-        sn1_set_affinity_irq
-};
-
-
-void
-sn1_irq_init (void)
-{
-	int i;
-
-	for (i = 0; i <= NR_IRQS; ++i) {
-		if (idesc_from_vector(i)->handler == &no_irq_type) {
-			idesc_from_vector(i)->handler = &irq_type_sn1;
-		}
-	}
-}
-
-
-
-#if !defined(CONFIG_IA64_SGI_SN1)
-void
-sn1_pci_fixup(int arg)
-{
-}
-#endif
-
-#ifdef CONFIG_PERCPU_IRQ
-
-extern irq_desc_t irq_descX[NR_IRQS];
-irq_desc_t *irq_desc_ptr[NR_CPUS] = { irq_descX };
-
-/*
- * Each slave AP allocates its own irq table.
- */
-int __init cpu_irq_init(void)
-{
-	irq_desc_ptr[smp_processor_id()] = (irq_desc_t *)kmalloc(sizeof(irq_descX), GFP_KERNEL);
-	if (irq_desc_ptr[smp_processor_id()] == 0)
-		return(-1);
-	memcpy(irq_desc_ptr[smp_processor_id()], irq_desc_ptr[0], 
-							sizeof(irq_descX));
-	return(0);
-}
-
-/*
- * This can also allocate the irq tables for the other cpus, specifically
- * on their nodes.
- */
-int __init master_irq_init(void)
-{
-	return(0);
-}
-
-/*
- * The input is an ivt level.
- */
-irq_desc_t *idesc_from_vector(unsigned int ivnum)
-{
-	return(irq_desc_ptr[smp_processor_id()] + ivnum);
-}
-
-/*
- * The input is a "soft" level, that we encoded in.
- */
-irq_desc_t *idesc_from_irq(unsigned int irq)
-{
-	return(irq_desc_ptr[irq >> 8] + (irq & 0xff));
-}
-
-unsigned int ivector_from_irq(unsigned int irq)
-{
-	return(irq & 0xff);
-}
-
-/*
- * This should return the Linux irq # for the i/p vector on the
- * i/p cpu. We currently do not track this.
- */
-unsigned int irq_from_cpuvector(int cpunum, unsigned int vector)
-{
-	return (vector);
-}
-
-#endif /* CONFIG_PERCPU_IRQ */
diff -Nru a/arch/ia64/sn/sn1/llsc4.c b/arch/ia64/sn/sn1/llsc4.c
--- a/arch/ia64/sn/sn1/llsc4.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,952 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/smp.h>
-#include <linux/kernel_stat.h>
-#include <linux/mm.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <asm/efi.h>
-#include <asm/page.h>
-#include <linux/threads.h>
-
-extern void bringup_set_led_bits(u8 bits, u8 mask);
-
-#include "llsc4.h"
-
-
-#ifdef STANDALONE
-#include "lock.h"
-#endif
-
-#ifdef INTTEST
-static int	inttest=0;
-#endif
-
-/*
- * Test parameter table for AUTOTEST
- */
-typedef struct {
-	int	passes;
-	int	linecount;
-	int	linepad;
-} autotest_table_t;
-
-autotest_table_t autotest_table[] = {
-	{5000000,	2,	0x2b4		},
-	{5000000,	16,	0,		},
-	{5000000,	16,	4,		},
-	{5000000,	128,	0x44		},
-	{5000000,	128,	0x84		},
-	{5000000,	128,	0x200		},
-	{5000000,	128,	0x204		},
-	{5000000,	128,	0x2b4		},
-	{5000000,	2,	8*MB+0x2b4	},
-	{5000000,	16,	8*MB+0		},
-	{5000000,	16,	8*MB+4		},
-	{5000000,	128,	8*MB+0x44	},
-	{5000000,	128,	8*MB+0x84	},
-	{5000000,	128,	8*MB+0x200	},
-	{5000000,	128,	8*MB+0x204	},
-	{5000000,	128,	8*MB+0x2b4	},
-	{0}};
-
-/*
- * Array of virtual addresses available for test purposes.
- */
-
-typedef struct {
-	long	vstart;
-	long	vend;
-	long	nextaddr;
-	int	wrapcount;
-} memmap_t;
-
-memmap_t 	memmap[MAXCHUNKS];
-int		memmapx=0;
-
-typedef struct {
-	void	*addr;
-	long	data[16];
-	long	data_fc[16];
-} capture_line_t;
-
-typedef struct {
-	int	size;
-	void	*blockaddr;
-	void	*shadaddr;
-	long	blockdata[16];
-	long	shaddata[16];
-	long	blockdata_fc[16];
-	long	shaddata_fc[16];
-	long	synerr;
-} capture_t;
-
-/*
- * PORTING NOTE: revisit this statement. On hardware we put mbase at 0 and
- * the rest of the tables have to start at 1MB to skip PROM tables.
- */
-#define THREADPRIVATE(t)	((threadprivate_t*)(((long)mbase)+1024*1024+t*((sizeof(threadprivate_t)+511)/512*512)))
-
-#define k_capture		mbase->sk_capture
-#define k_go			mbase->sk_go
-#define k_linecount		mbase->sk_linecount
-#define k_passes		mbase->sk_passes
-#define k_napticks		mbase->sk_napticks
-#define k_stop_on_error		mbase->sk_stop_on_error
-#define k_verbose		mbase->sk_verbose
-#define k_threadprivate		mbase->sk_threadprivate
-#define k_blocks		mbase->sk_blocks
-#define k_iter_msg		mbase->sk_iter_msg
-#define k_vv			mbase->sk_vv
-#define k_linepad		mbase->sk_linepad
-#define k_options		mbase->sk_options
-#define k_testnumber		mbase->sk_testnumber
-#define k_currentpass		mbase->sk_currentpass
-
-static long		blocks[MAX_LINECOUNT];		/* addresses of data blocks */
-static control_t	*mbase;
-static vint		initialized=0;
-
-static unsigned int ran_conf_llsc(int);
-static int  rerr(capture_t *, char *, void *, void *, int, int, int, int, int, int);
-static void dumpline(void *, char *, char *, void *, void *, int);
-static int  checkstop(int, int, uint);
-static void spin(int);
-static void capturedata(capture_t *, uint, void *, void *, int);
-static int  randn(uint max, uint *seed);
-static uint zrandom (uint *zranseed);
-static int  set_lock(uint *, uint);
-static int  clr_lock(uint *, uint);
-static void Speedo(void);
-
-int autotest_enabled=0;
-static int llsctest_number=-1;
-static int errstop_enabled=0;
-static int fail_enabled=0;
-static int selective_trigger=0;
-static int dump_block_addrs_opt=0;
-static uint errlock=0;
-
-static int __init autotest_enable(char *str)
-{
-        autotest_enabled = 1;
-	return 1;
-}
-static int __init set_llscblkadr(char *str)
-{
-	dump_block_addrs_opt = 1;
-	return 1;
-}
-static int __init set_llscselt(char *str)
-{
-	selective_trigger = 1;
-	return 1;
-}
-static int __init set_llsctest(char *str)
-{
-        llsctest_number = simple_strtol(str, &str, 10);
-	if (llsctest_number < 0 || llsctest_number > 15)
-		llsctest_number = -1;
-	return 1;
-}
-static int __init set_llscerrstop(char *str)
-{
-        errstop_enabled = 1;
-	return 1;
-}
-static int __init set_llscfail(char *str)
-{
-        fail_enabled = 8;
-	return 1;
-}
-
-static void print_params(void)
-{
-	printk ("********* Enter AUTOTEST facility on master cpu *************\n");
-	printk ("  Test options:\n");
-	printk ("     llsctest=<n>\t%d\tTest number to run (all = -1)\n", llsctest_number);
-	printk ("     llscerrstop \t%s\tStop on error\n", errstop_enabled ? "on" : "off");
-	printk ("     llscfail    \t%s\tForce a failure to test the trigger & error messages\n", fail_enabled ? "on" : "off");
-	printk ("     llscselt    \t%s\tSelective triger on failures\n", selective_trigger ? "on" : "off");
-	printk ("     llscblkadr  \t%s\tDump data block addresses\n", dump_block_addrs_opt ? "on" : "off");
-	printk ("\n");
-}
-__setup("autotest", autotest_enable);
-__setup("llsctest=", set_llsctest);
-__setup("llscerrstop", set_llscerrstop);
-__setup("llscfail", set_llscfail);
-__setup("llscselt", set_llscselt);
-__setup("llscblkadr", set_llscblkadr);
-
-
-extern inline int
-set_lock(uint *lock, uint id)
-{
-	uint	old;
-	old = cmpxchg_acq(lock, 0, id);
-	return (old == 0);
-}
-
-extern inline int
-clr_lock(uint *lock, uint id)
-{
-	uint	old;
-	old = cmpxchg_rel(lock, id, 0);
-	return (old == id);
-}
-
-extern inline void
-zero_lock(uint *lock)
-{
-	*lock = 0;
-}
-
-/*------------------------------------------------------------------------+
-| Routine  :  ran_conf_llsc - ll/sc shared data test                      |
-| Description: This test checks the coherency of shared data              |
-+------------------------------------------------------------------------*/
-static unsigned int
-ran_conf_llsc(int thread)
-{
-	private_t	pval;
-	share_t		sval, sval2;
-	uint		vv, linei, slinei, sharei, pass;
-	long		t;
-	lock_t		lockpat;
-	share_t		*sharecopy;
-	long		verbose, napticks, passes, linecount, lcount;
-	dataline_t	*linep, *slinep;
-	int		s, seed;
-	threadprivate_t	*tp;
-	uint		iter_msg, iter_msg_i=0;
-	int		vv_mask;
-	int		correct_errors;
-	int		errs=0;
-	int		stillbad;
-	capture_t	capdata;
-	private_t	*privp;
-	share_t		*sharep;
-
-
-	linecount = k_linecount;
-	napticks = k_napticks;
-	verbose = k_verbose;
-	passes = k_passes;
-	iter_msg = k_iter_msg;
-	seed = (thread + 1) * 647;
-	tp = THREADPRIVATE(thread);
-	vv_mask = (k_vv>>((thread%16)*4)) & 0xf;
-	correct_errors = k_options&0xff;
-
-	memset (&tp->private, 0, sizeof(tp->private));
-	memset (&capdata, 0, sizeof(capdata));
-
-	for (pass = 1; passes == 0 || pass < passes; pass++) {
-		lockpat = (pass & 0x0fffffff) + (thread <<28);
-		tp->threadpasses = pass;
-		if (checkstop(thread, pass, lockpat))
-			return 0;
-		iter_msg_i++;
-		if (iter_msg && iter_msg_i > iter_msg) {
-			printk("Thread %d, Pass %d\n", thread, pass);
-			iter_msg_i = 0;
-		}
-		lcount = 0;
-
-		/*
-		 * Select line to perform operations on.
-		 */
-		linei = randn(linecount, &seed);
-		sharei = randn(2, &seed);
-		slinei = (linei + (linecount/2))%linecount;		/* I dont like this - fix later */
-
-		linep = (dataline_t *)blocks[linei];
-		slinep = (dataline_t *)blocks[slinei];
-		if (sharei == 0)
-			sharecopy = &slinep->share0;
-		else
-			sharecopy = &slinep->share1;
-
-
-		vv = randn(4, &seed);
-		if ((vv_mask & (1<<vv)) == 0)
-			continue;
-
-		if (napticks) {
-			t = randn(napticks, &seed);
-			udelay(t);
-		}
-		privp = &linep->private[thread];
-		sharep = &linep->share[sharei];
-		
-		switch(vv) {
-		case 0:
-			/* Read and verify private count on line. */
-			pval = *privp;
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
-			if (pval != tp->private[linei]) {
-				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
-				stillbad = (*privp != tp->private[linei]);
-				if (rerr(&capdata, "Private count", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
-					return 1;
-				}
-				if (correct_errors) {
-					tp->private[linei] = *privp;
-				}
-				errs++;
-			}
-			break;
-
-		case 1:
-			/* Read, verify, and increment private count on line. */
-			pval = *privp;
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, tp->private[linei]);
-			if (pval != tp->private[linei]) {
-				capturedata(&capdata, pass, privp, NULL, sizeof(*privp));
-				stillbad = (*privp != tp->private[linei]);
-				if (rerr(&capdata, "Private count & inc", linep, slinep, thread, pass, linei, tp->private[linei], pval, stillbad)) {
-					return 1;
-				}
-				errs++;
-			}
-			pval++;
-			*privp = pval;
-			tp->private[linei] = pval;
-			break;
-
-		case 2:
-			/* Lock line, read and verify shared data. */
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
-			lcount = 0;
-			while (LOCK(sharei) != 1) {
-				if (checkstop(thread, pass, lockpat))
-					return 0;
-				if (lcount++>1000000) {
-					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
-					stillbad = (GETLOCK(sharei) != 0);
-					rerr(&capdata, "Shared data lock", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
-					return 1;
-				}
-				if ((lcount&0x3fff) == 0)
-					udelay(1000);
-			}
-
-			sval = *sharep;
-			sval2 = *sharecopy;
-			if (pass > 12 && thread == 0 && fail_enabled == 1)
-				sval++;
-			if (sval != sval2) {
-				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
-				stillbad = (*sharep != *sharecopy);
-				if (!stillbad && *sharep != sval && *sharecopy == sval2)
-					stillbad = 2;
-				if (rerr(&capdata, "Shared data", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
-					return 1;
-				}
-				if (correct_errors)
-					*sharep = *sharecopy;
-				errs++;
-			}
-
-
-			if ( (s=UNLOCK(sharei)) != 1) {
-				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
-				stillbad = (GETLOCK(sharei) != lockpat);
-				if (rerr(&capdata, "Shared data unlock", linep, slinep, thread, pass, linei, lockpat, GETLOCK(sharei), stillbad))
-					return 1;
-				if (correct_errors)
-					ZEROLOCK(sharei);	
-				errs++;
-			}
-			break;
-
-		case 3:
-			/* Lock line, read and verify shared data, modify shared data. */
-			if (verbose)
-				printk("Line:%3d, Thread:%d:%d. Val: %x\n", linei, thread, vv, *sharecopy);
-			lcount = 0;
-			while (LOCK(sharei) != 1) {
-				if (checkstop(thread, pass, lockpat))
-					return 0;
-				if (lcount++>1000000) {
-					capturedata(&capdata, pass, LOCKADDR(sharei), NULL, sizeof(lock_t));
-					stillbad = (GETLOCK(sharei) != 0);
-					rerr(&capdata, "Shared data lock & inc", linep, slinep, thread, pass, linei, 0, GETLOCK(sharei), stillbad);
-					return 1;
-				}
-				if ((lcount&0x3fff) == 0)
-					udelay(1000);
-			}
-			sval = *sharep;
-			sval2 = *sharecopy;
-			if (sval != sval2) {
-				capturedata(&capdata, pass, sharep, sharecopy, sizeof(*sharecopy));
-				stillbad = (*sharep != *sharecopy);
-				if (!stillbad && *sharep != sval && *sharecopy == sval2)
-					stillbad = 2;
-				if (rerr(&capdata, "Shared data & inc", linep, slinep, thread, pass, linei, sval2, sval, stillbad)) {
-					return 1;
-				}
-				errs++;
-			}
-
-			*sharep = lockpat;
-			*sharecopy = lockpat;
-
-
-			if ( (s=UNLOCK(sharei)) != 1) {
-				capturedata(&capdata, pass, LOCKADDR(sharei), NULL, 4);
-				stillbad = (GETLOCK(sharei) != lockpat);
-				if (rerr(&capdata, "Shared data & inc unlock", linep, slinep, thread, pass, linei, thread, GETLOCK(sharei), stillbad))
-					return 1;
-				if (correct_errors)
-					ZEROLOCK(sharei);	
-				errs++;
-			}
-			break;
-		}
-	}
-
-	return (errs > 0);
-}
-
-static void
-trigger_la(long val)
-{
-	long	*p;
-
-	p = (long*)0xc0000a0001000020L; /* PI_CPU_NUM */
-	*p = val;
-}
-
-static long
-getsynerr(void)
-{
-	long	err, *errp;
-
-	errp = (long*)0xc0000e0000000340L;	/* SYN_ERR */
-	err = *errp;
-	if (err)
-		*errp = -1L;
-	return (err & ~0x60);
-}
-
-static int
-rerr(capture_t *cap, char *msg, void *lp, void *slp, int thread, int pass, int linei, int exp, int found, int stillbad)
-{
-	int		cpu, i;
-	long 		synerr;
-	int		selt;
-
-
-	selt = selective_trigger && stillbad > 1 && 
-			memcmp(cap->blockdata, cap->blockdata_fc, 128) != 0 &&
-			memcmp(cap->shaddata, cap->shaddata_fc, 128) == 0;
-	if (selt) {
-		trigger_la(pass);
-	} else if (selective_trigger) {
-		k_go = ST_STOP;
-		return k_stop_on_error;;
-	}
-
-	spin(1);
-	i = 100;
-	while (i && set_lock(&errlock, 1) != 1) {
-		spin(1);
-		i--;
-	}
-	printk ("\nDataError!: %-20s, test %ld, thread %d, line:%d, pass %d (0x%x), time %ld expected:%x, found:%x\n",
-	    msg, k_testnumber, thread, linei, pass, pass, jiffies, exp, found);
-
-	dumpline (lp, "Corrupted data", "D ", cap->blockaddr, cap->blockdata, cap->size);
-	if (memcmp(cap->blockdata, cap->blockdata_fc, 128))
-		dumpline (lp, "Corrupted data", "DF", cap->blockaddr, cap->blockdata_fc, cap->size);
-
-	if (cap->shadaddr) {
-		dumpline (slp, "Shadow    data", "S ", cap->shadaddr, cap->shaddata, cap->size);
-		if (memcmp(cap->shaddata, cap->shaddata_fc, 128))
-			dumpline (slp, "Shadow    data", "SF", cap->shadaddr, cap->shaddata_fc, cap->size);
-	}
-	
-	printk("Threadpasses: ");
-	for (cpu=0; cpu<MAXCPUS; cpu++)
-		if (k_threadprivate[cpu]->threadpasses)
-			printk("  %d:0x%x", cpu, k_threadprivate[cpu]->threadpasses);
-
-
-	printk("\nData was %sfixed by flushcache\n", (stillbad == 1 ? "**** NOT **** " : " "));
-	synerr = getsynerr();
-	if (synerr)
-		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
-	spin(2);
-	printk("\n\n");
-	clr_lock(&errlock, 1);
-
-	if (errstop_enabled) {
-		local_irq_disable();
-		while(1);
-	}
-	return k_stop_on_error;
-}
-
-
-static void
-dumpline(void *lp, char *str1, char *str2, void *addr, void *data, int size)
-{
-	long *p;
-	int i, off;
-
-	printk("%s at 0x%lx, size %d, block starts at 0x%lx\n", str1, (long)addr, size, (long)lp);
-	p = (long*) data;
-	for (i=0; i<16; i++, p++) {
-		if (i==0) printk("%2s", str2);
-		if (i==8) printk("  ");
-		printk(" %016lx", *p);
-		if ((i&7)==7) printk("\n");
-	}
-	printk("   ");
-	off = (((long)addr) ^ size) & 63L;
-	for (i=0; i<off+size; i++) {
-		printk("%s", (i>=off) ? "--" : "  ");
-		if ((i%8) == 7)
-			printk(" ");
-	}
-
-	off = ((long)addr) & 127;
-	printk(" (line %d)\n", off/64+1);
-}
-
-
-static int
-randn(uint max, uint *seedp)
-{
-	if (max == 1)
-		return(0);
-	else
-		return((int)(zrandom(seedp)>>10) % max);
-}
-
-
-static int
-checkstop(int thread, int pass, uint lockpat)
-{
-	long	synerr;
-
-	if (k_go == ST_RUN)
-		return 0;
-	if (k_go == ST_STOP)
-		return 1;
-
-	if (errstop_enabled) {
-		local_irq_disable();
-		while(1);
-	}
-	synerr = getsynerr();
-	spin(2);
-	if (k_go == ST_STOP)
-		return 1;
-	if (synerr)
-		printk("SYNERR: Thread %d, Synerr: 0x%lx\n", thread, synerr);
-	return 1;
-}
-
-
-static void
-spin(int j)
-{
-	udelay(j * 500000);
-}
-
-static void
-capturedata(capture_t *cap, uint pass, void *blockaddr, void *shadaddr, int size)
-{
-
-	if (!selective_trigger)
-		trigger_la (pass);
-
-	memcpy (cap->blockdata, CACHEALIGN(blockaddr), 128);
-	if (shadaddr) 
-		memcpy (cap->shaddata, CACHEALIGN(shadaddr), 128);
-
-	if (k_stop_on_error) {
-		k_go = ST_ERRSTOP;
-	}
-
- 	cap->size = size;
-	cap->blockaddr = blockaddr;
-	cap->shadaddr = shadaddr;
-
-	asm volatile ("fc %0" :: "r"(blockaddr) : "memory");
-	ia64_sync_i();
-	ia64_srlz_d();
-	memcpy (cap->blockdata_fc, CACHEALIGN(blockaddr), 128);
-
-	if (shadaddr) {
-		asm volatile ("fc %0" :: "r"(shadaddr) : "memory");
-		ia64_sync_i();
-		ia64_srlz_d();
-		memcpy (cap->shaddata_fc, CACHEALIGN(shadaddr), 128);
-	}
-}
-
-int             zranmult = 0x48c27395;
-
-static uint  
-zrandom (uint *seedp)
-{
-        *seedp = (*seedp * zranmult) & 0x7fffffff;
-        return (*seedp);
-}
-
-
-void
-set_autotest_params(void)
-{
-	static int	testnumber=-1;
-
-	if (llsctest_number >= 0) {
-		testnumber = llsctest_number;
-	} else {
-		testnumber++;
-		if (autotest_table[testnumber].passes == 0) {
-			testnumber = 0;
-			dump_block_addrs_opt = 0;
-		}
-	}
-	k_passes = autotest_table[testnumber].passes;
-	k_linepad = autotest_table[testnumber].linepad;
-	k_linecount = autotest_table[testnumber].linecount;
-	k_testnumber = testnumber;
-
-	if (IS_RUNNING_ON_SIMULATOR()) {
-		printk ("llsc start test %ld\n", k_testnumber);
-		k_passes = 1000;
-	}
-}
-
-
-static void
-set_leds(int errs)
-{
-	unsigned char	leds=0;
-
-	/*
-	 * Leds are:
-	 * 	ppppeee-  
-	 *   where
-	 *      pppp = test number
-	 *       eee = error count but top bit is stick
-	 */
-
-	leds =  ((errs&7)<<1) | ((k_testnumber&15)<<4) | (errs ? 0x08 : 0);
-	bringup_set_led_bits(leds, 0xfe);
-}
-
-static void
-setup_block_addresses(void)
-{
-	int		i, stride, memmapi;
-
-	stride = LINESTRIDE;
-	memmapi = 0;
-	for (i=0; i<memmapx; i++) {
-		memmap[i].nextaddr = memmap[i].vstart;
-		memmap[i].wrapcount = 0;
-	}
-
-	for (i=0; i<k_linecount; i++) {
-		blocks[i] = memmap[memmapi].nextaddr;
-		memmap[memmapi].nextaddr += stride;
-		if (memmap[memmapi].nextaddr + sizeof(dataline_t) >= memmap[memmapi].vend) {
-			memmap[memmapi].wrapcount++;
-			memmap[memmapi].nextaddr = memmap[memmapi].vstart + 
-					memmap[memmapi].wrapcount * sizeof(dataline_t);
-		}
-
-		memset((void*)blocks[i], 0, sizeof(dataline_t));
-
-		if (stride > 16384) {
-			memmapi++;
-			if (memmapi == memmapx)
-				memmapi = 0;
-		}
-	}
-
-}
-
-static void
-dump_block_addrs(void)
-{
-	int	i;
-
-	printk("LLSC TestNumber %ld\n", k_testnumber);
-
-	for (i=0; i<k_linecount; i++) {
-		printk("  %lx", blocks[i]);
-		if (i%4 == 3)
-			printk("\n");
-	}
-	printk("\n");
-}
-
-
-static void
-set_thread_state(int cpuid, int state)
-{
-	if (k_threadprivate[cpuid]->threadstate == TS_KILLED) {
-		bringup_set_led_bits(0xfe, 0xfe);
-		while(1);
-	}
-	k_threadprivate[cpuid]->threadstate = state;
-}
-
-static int
-build_mem_map(unsigned long start, unsigned long end, void *arg)
-{
-	long	lstart;
-	long	align = 8*MB;
-	/*
-	 * HACK - skip the kernel on the first node 
-	 */
-
-	printk ("LLSC memmap: start 0x%lx, end 0x%lx, (0x%lx - 0x%lx)\n", 
-		start, end, (long) virt_to_page(start), (long) virt_to_page(end-PAGE_SIZE));
-
-	while (end > start && (PageReserved(virt_to_page(end-PAGE_SIZE)) || virt_to_page(end-PAGE_SIZE)->count.counter > 0))
-		end -= PAGE_SIZE;
-
-	lstart = end;
-	while (lstart > start && (!PageReserved(virt_to_page(lstart-PAGE_SIZE)) && virt_to_page(lstart-PAGE_SIZE)->count.counter == 0))
-		lstart -= PAGE_SIZE;
-
-	lstart = (lstart + align -1) /align * align;
-	end = end / align * align;
-	if (lstart >= end)
-		return 0;
-	printk ("     memmap: start 0x%lx, end 0x%lx\n", lstart, end);
-
-	memmap[memmapx].vstart = lstart;
-	memmap[memmapx].vend = end;
-	memmapx++;
-	return 0;
-}
-
-void int_test(void);
-
-int
-llsc_main (int cpuid, long mbasex)
-{
-	int		i, cpu, is_master, repeatcnt=0;
-	unsigned int	preverr=0, errs=0, pass=0;
-	int		automode=0;
-
-#ifdef INTTEST
-	if (inttest)
-		int_test();
-#endif
-
-	if (!autotest_enabled)
-		return 0;
-
-#ifdef CONFIG_SMP
-	is_master = !smp_processor_id();
-#else
-	is_master = 1;
-#endif
-
-
-	if (is_master) {
-		print_params();
-		if(!IS_RUNNING_ON_SIMULATOR())
-			spin(10);
-		mbase = (control_t*)mbasex;
-		k_currentpass = 0;
-		k_go = ST_IDLE;
-		k_passes = DEF_PASSES;
-		k_napticks = DEF_NAPTICKS;
-		k_stop_on_error = DEF_STOP_ON_ERROR;
-		k_verbose = DEF_VERBOSE;
-		k_linecount = DEF_LINECOUNT;
-		k_iter_msg = DEF_ITER_MSG;
-		k_vv = DEF_VV;
-		k_linepad = DEF_LINEPAD;
-		k_blocks = (void*)blocks;
-		efi_memmap_walk(build_mem_map, 0);
-	
-#ifdef CONFIG_IA64_SGI_AUTOTEST
-		automode = 1;
-#endif
-
-		for (i=0; i<MAXCPUS; i++) {
-			k_threadprivate[i] = THREADPRIVATE(i);
-			memset(k_threadprivate[i], 0, sizeof(*k_threadprivate[i]));
-		}
-		initialized = 1;
-	} else {
-		while (initialized == 0)
-			udelay(100);
-	}
-
-loop:
-	if (is_master) {
-		if (automode) {
-			if (!preverr || repeatcnt++ > 5) {
-				set_autotest_params();
-				repeatcnt = 0;
-			}
-		} else {
-			while (k_go == ST_IDLE);
-		}
-
-		k_go = ST_INIT;
-		if (k_linecount > MAX_LINECOUNT) k_linecount = MAX_LINECOUNT;
-		k_linecount = k_linecount & ~1;
-		setup_block_addresses();
-		if (dump_block_addrs_opt)
-			dump_block_addrs();
-
-		k_currentpass = pass++;
-		k_go = ST_RUN;
-		if (fail_enabled)
-			fail_enabled--;
-
-	} else {
-		while (k_go != ST_RUN || k_currentpass != pass);
-		pass++;
-	}
-
-
-	set_leds(errs);
-	set_thread_state(cpuid, TS_RUNNING);
-
-	errs += ran_conf_llsc(cpuid);
-	preverr = (k_go == ST_ERRSTOP);
-
-	set_leds(errs);
-	set_thread_state(cpuid, TS_STOPPED);
-
-	if (is_master) {
-		Speedo();
-		for (i=0, cpu=0; cpu<MAXCPUS; cpu++) {
-			while (k_threadprivate[cpu]->threadstate == TS_RUNNING) {
-				i++;
-				if (i == 10000) { 
-					k_go = ST_STOP;
-					printk ("  llsc master stopping test number %ld\n", k_testnumber);
-				}
-				if (i > 100000) {
-					k_threadprivate[cpu]->threadstate = TS_KILLED;
-					printk ("  llsc: master killing cpuid %d, running test number %ld\n", 
-							cpu, k_testnumber);
-				}
-				udelay(1000);
-			}
-		}
-	}
-
-	goto loop;
-}
-
-
-static void
-Speedo(void)
-{
-	static int i = 0;
-
-	switch (++i%4) {
-	case 0:
-		printk("|\b");
-		break;
-	case 1:
-		printk("\\\b");
-		break;
-	case 2:
-		printk("-\b");
-		break;
-	case 3:
-		printk("/\b");
-		break;
-	}
-}
-
-#ifdef INTTEST
-
-/* ======================================================================================================== 
- *
- * Some test code to verify that interrupts work
- *
- * Add the following to the arch/ia64/kernel/smp.c after the comment "Reschedule callback"
- * 		if (zzzprint_resched) printk("  cpu %d got interrupt\n", smp_processor_id());
- *
- * Enable the code in arch/ia64/sn/sn1/smp.c to print sending IPIs.
- *
- */
-
-static int __init set_inttest(char *str)
-{
-        inttest = 1;
-	autotest_enabled = 1;
-
-	return 1;
-}	
-
-__setup("inttest=", set_inttest);
-
-int	zzzprint_resched=0;
-
-void
-int_test() {
-	int			mycpu, cpu;
-	static volatile int	control_cpu=0;
-
-	mycpu = smp_processor_id();
-	zzzprint_resched = 2;
-
-	printk("Testing cross interrupts\n");
-	
-	while (control_cpu != smp_num_cpus) {
-		if (mycpu == cpu_logical_map(control_cpu)) {
-			for (cpu=0; cpu<smp_num_cpus; cpu++) {
-				printk("Sending interrupt from %d to %d\n", mycpu, cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-				smp_send_reschedule(cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-				smp_send_reschedule(cpu_logical_map(cpu));
-				udelay(IS_RUNNING_ON_SIMULATOR ? 10000 : 400000);
-			}
-			control_cpu++;
-		}
-	}
-
-	zzzprint_resched = 1;
-
-	if (mycpu == cpu_logical_map(smp_num_cpus-1)) {
-		printk("\nTight loop of cpu %d sending ints to cpu 0 (every 100 us)\n", mycpu);
-		udelay(IS_RUNNING_ON_SIMULATOR ? 1000 : 1000000);
-		__cli();
-		while (1) {
-			smp_send_reschedule(0);
-			udelay(100);
-		}
-
-	}
-
-	while(1);
-}
-#endif
diff -Nru a/arch/ia64/sn/sn1/llsc4.h b/arch/ia64/sn/sn1/llsc4.h
--- a/arch/ia64/sn/sn1/llsc4.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,104 +0,0 @@
-/* 
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
- */
-
-#ifdef STANDALONE
-#include "lock.h"
-#endif
-
-
-#define DEF_NAPTICKS		0
-#define DEF_PASSES		0
-#define DEF_AUTO_PASSES		1000000
-#define DEF_STOP_ON_ERROR	1
-#define DEF_VERBOSE		0
-#define DEF_LINECOUNT		2
-#define DEF_ITER_MSG		0
-#define DEF_VV			0xffffffff
-#define DEF_LINEPAD		0x234
-
-
-
-#define MAXCPUS			16
-#define CACHELINE		64
-#define MAX_LINECOUNT		1024
-#define K			1024
-#define	MB			(K*K)
-
-
-#define	uint 		unsigned int
-#define	ushort		unsigned short
-#define vint		volatile int
-#define vlong		volatile long
-
-#define LOCKADDR(i)	&linep->lock[(i)]
-#define LOCK(i)		set_lock(LOCKADDR(i), lockpat)
-#define UNLOCK(i)	clr_lock(LOCKADDR(i), lockpat)
-#define GETLOCK(i)	*LOCKADDR(i)
-#define ZEROLOCK(i)	zero_lock(LOCKADDR(i))
-
-#define CACHEALIGN(a)	((void*)((long)(a) & ~127L))
-
-typedef uint		lock_t;
-typedef uint		share_t;
-typedef uint		private_t;
-
-typedef struct {
-	lock_t		lock[2];
-	share_t		share[2];
-	private_t	private[MAXCPUS];
-	share_t		share0;
-	share_t		share1;
-} dataline_t ;
-
-
-#define LINEPAD			k_linepad
-#define LINESTRIDE		(((sizeof(dataline_t)+CACHELINE-1)/CACHELINE)*CACHELINE + LINEPAD)
-
-
-typedef struct {
-	vint		threadstate;
-	uint		threadpasses;
-	private_t	private[MAX_LINECOUNT];
-} threadprivate_t;
-
-typedef struct {
-	vlong		sk_go;		/* 0=idle, 1=init, 2=run */
-	long		sk_linecount;
-	long		sk_passes;
-	long		sk_napticks;
-	long		sk_stop_on_error;
-	long		sk_verbose;
-	long		sk_iter_msg;
-	long		sk_vv;
-	long		sk_linepad;
-	long		sk_options;
-	long		sk_testnumber;
-	vlong		sk_currentpass;
-	void 		*sk_blocks;
-	threadprivate_t	*sk_threadprivate[MAXCPUS];
-} control_t;
-
-/* Run state (k_go) constants */
-#define ST_IDLE		0
-#define ST_INIT		1
-#define ST_RUN		2
-#define ST_STOP		3
-#define ST_ERRSTOP	4
-
-
-/* Threadstate constants */
-#define TS_STOPPED	0
-#define	TS_RUNNING	1
-#define TS_KILLED	2
-
-
-
-int llsc_main (int cpuid, long mbasex);
-
diff -Nru a/arch/ia64/sn/sn1/machvec.c b/arch/ia64/sn/sn1/machvec.c
--- a/arch/ia64/sn/sn1/machvec.c	Fri Mar 15 17:51:00 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,18 +0,0 @@
-#define MACHVEC_PLATFORM_NAME	sn1
-#include <asm/machvec_init.h>
-#include <asm/io.h>
-#include <linux/pci.h>
-void*
-sn1_mk_io_addr_MACRO
-
-dma_addr_t
-sn1_pci_map_single_MACRO
-
-int
-sn1_pci_map_sg_MACRO
-
-unsigned long
-sn1_virt_to_phys_MACRO
-
-void *
-sn1_phys_to_virt_MACRO
diff -Nru a/arch/ia64/sn/sn1/mm.c b/arch/ia64/sn/sn1/mm.c
--- a/arch/ia64/sn/sn1/mm.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,394 +0,0 @@
-/*
- * Copyright, 2000-2001, Silicon Graphics.
- * Copyright Srinivasa Thirumalachar (sprasad@engr.sgi.com)
- * Copyright 2000-2001 Kanoj Sarcar (kanoj@sgi.com)
- */
-
-#include <linux/config.h>
-#include <linux/mm.h>
-#include <linux/bootmem.h>
-#include <asm/page.h>
-#include <asm/efi.h>
-#include <asm/sn/mmzone_sn1.h>
-
-#define MIN(a,b)	((a) < (b) ? (a) : (b))
-#define MAX(a,b)	((a) > (b) ? (a) : (b))
-
-#define DONE_NOTHING	0
-#define DONE_FINDING	1
-#define DONE_BUILDING	2
-
-struct nodemem_s {
-        u64     start;	/* start of kernel usable memory */
-        u64     end;	/* end of kernel usable memory */
-	u64	mtot;	/* total kernel usable memory */
-	u64	done;	/* state of bootmem initialization */
-	u64	bstart;	/* where should the bootmem area be */
-	u64	bsize;	/* bootmap size */
-        u64 	hole[SN1_MAX_BANK_PER_NODE];
-} nodemem[MAXNODES];
-
-static int nodemem_valid = 0;
-
-static int __init
-free_unused_memmap_hole(int nid, unsigned long start, unsigned long end)
-{
-        struct page * page, *pageend;
-        unsigned long count = 0;
-
-	if (start >= end)
-		return 0;
-
-	/*
-	 * Get the memmap ptrs to the start and end of the holes.
-	 * virt_to_page(start) will panic, if start is in hole.
-	 * Can we do virt_to_page(end), if end is on the next node?
-	 */
-
-	page = virt_to_page(start - 1);
-	page++;
-	pageend = virt_to_page(end);
-
-	printk("hpage=0x%lx, hpageend=0x%lx\n", (u64)page, (u64)pageend) ;
-	free_bootmem_node(NODE_DATA(nid), __pa(page), (u64)pageend - (u64)page);
-
-	return count;
-}
-
-static void __init
-free_unused_memmap_node(int nid)
-{
-	u64	i = 0;
-	u64	holestart = -1;
-	u64	start = nodemem[nid].start;
-
-	start = ((start >> SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	do {
-		holestart = nodemem[nid].hole[i];
-		i++;
-		while ((i < SN1_MAX_BANK_PER_NODE) && 
-					(nodemem[nid].hole[i] == (u64)-1))
-			i++;
-		if (i < SN1_MAX_BANK_PER_NODE)
-			free_unused_memmap_hole(nid, holestart, 
-				start + (i<<SN1_BANK_ADDR_SHIFT));
-	} while (i<SN1_MAX_BANK_PER_NODE);
-}
-
-/*
- * Since efi_memmap_walk merges contiguous banks, this code will need
- * to find all the nasid/banks covered by the input memory descriptor.
- */
-static int __init
-build_nodemem_map(unsigned long start, unsigned long end, void *arg)
-{
-	unsigned long vaddr = start;
-	unsigned long nvaddr;
-	int nasid = GetNasId(__pa(vaddr));
-	int cnodeid, bankid;
-
-	while (vaddr < end) {
-		cnodeid = NASID_TO_CNODEID(nasid);
-		bankid = GetBankId(__pa(vaddr));
-		nodemem[cnodeid].start = MIN(nodemem[cnodeid].start, vaddr);
-		nvaddr = (unsigned long)__va((unsigned long)(++nasid) << 
-							SN1_NODE_ADDR_SHIFT);
-		nodemem[cnodeid].end = MAX(nodemem[cnodeid].end, MIN(end, nvaddr));
-		while ((bankid < SN1_MAX_BANK_PER_NODE) && 
-					(vaddr < nodemem[cnodeid].end)) {
-			nvaddr = nodemem[cnodeid].start + 
-			  ((unsigned long)(bankid + 1) << SN1_BANK_ADDR_SHIFT);
-			nodemem[cnodeid].hole[bankid++] = MIN(nvaddr, end);
-			vaddr = nvaddr;
-		}
-	}
-
-	return 0;
-}
-
-static int __init
-pgtbl_size_ok(int nid)
-{
-	unsigned long numpfn, bank0size, nodesize ;
-	unsigned long start = nodemem[nid].start;
-
-	start = ((start >> SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	
-	nodesize 	= nodemem[nid].end - start ;
-	numpfn 		= nodesize >> PAGE_SHIFT;
-
-	bank0size 	= nodemem[nid].hole[0] - start ;
-	/* If nid == master node && no kernel text replication */
-	bank0size      -= 0xA00000 ;	/* Kernel text + stuff */
-	bank0size      -= ((numpfn + 7) >> 3);
-
-	if ((numpfn * sizeof(mem_map_t)) > bank0size) {
-		printk("nid = %d, ns=0x%lx, npfn=0x%lx, bank0size=0x%lx\n", 
-			nid, nodesize, numpfn, bank0size) ;
-		return 0 ;
-	}
-
-	return 1 ;
-}
-
-static void __init
-check_pgtbl_size(int nid)
-{
-	int	bank = SN1_MAX_BANK_PER_NODE - 1 ;
-
-	/* Find highest bank with valid memory */
-        while ((nodemem[nid].hole[bank] == -1) && (bank))
-               bank-- ;
-
-	while (!pgtbl_size_ok(nid)) {
-		/* Remove that bank of memory */
-		/* Collect some numbers later */
-		printk("Ignoring node %d bank %d\n", nid, bank) ;
-		nodemem[nid].hole[bank--] = -1 ;
-		/* Get to the next populated bank */
-		while ((nodemem[nid].hole[bank] == -1) && (bank))
-			bank-- ;
-		printk("Using only upto bank %d on node %d\n", bank,nid) ;
-		nodemem[nid].end = nodemem[nid].hole[bank] ; 
-		if (!bank) break ;
-	}
-}
-
-void dump_nodemem_map(int) ;
-
-#ifdef CONFIG_DISCONTIGMEM
-
-extern bootmem_data_t bdata[];
-
-/*
- * This assumes there will be a hole in kernel-usable memory between nodes
- * (due to prom). The memory descriptors invoked via efi_memmap_walk are 
- * in increasing order. It tries to identify first suitable free area to 
- * put the bootmem for the node in. When presented with the md holding
- * the kernel, it only searches at the end of the kernel area.
- */
-static int __init
-find_node_bootmem(unsigned long start, unsigned long end, void *arg)
-{
-	int nasid = GetNasId(__pa(start));
-	int cnodeid = NASID_TO_CNODEID(nasid);
-	unsigned long nodesize;
-	extern char _end;
-	unsigned long kaddr = (unsigned long)&_end;
-
-	/*
-	 * Track memory available to kernel.
-	 */
-	nodemem[cnodeid].mtot += ((end - start) >> PAGE_SHIFT);
-	if (nodemem[cnodeid].done != DONE_NOTHING)
-		return(0);
-	nodesize = nodemem[cnodeid].end - ((nodemem[cnodeid].start >> 
-				SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-	nodesize >>= PAGE_SHIFT;
-
-	/*
-	 * Adjust limits for the md holding the kernel.
-	 */
-	if ((start < kaddr) && (end > kaddr))
-		start = PAGE_ALIGN(kaddr);
-
-	/*
-	 * We need space for mem_map, bootmem map plus a few more pages
-	 * to satisfy alloc_bootmems out of node 0.
-	 */
-	if ((end - start) > ((nodesize * sizeof(struct page)) + (nodesize/8)
-						+ (10 * PAGE_SIZE))) {
-		nodemem[cnodeid].bstart = start;
-		nodemem[cnodeid].done = DONE_FINDING;
-	}
-	return(0);
-}
-
-/*
- * This assumes there will be a hole in kernel-usable memory between nodes
- * (due to prom). The memory descriptors invoked via efi_memmap_walk are 
- * in increasing order.
- */
-static int __init
-build_node_bootmem(unsigned long start, unsigned long end, void *arg)
-{
-	int nasid = GetNasId(__pa(start));
-	int curnodeid = NASID_TO_CNODEID(nasid);
-	int i;
-	unsigned long pstart, pend;
-	extern char _end, _stext;
-	unsigned long kaddr = (unsigned long)&_end;
-
-	if (nodemem[curnodeid].done == DONE_FINDING) {
-		/*
-		 * This is where we come to know the node is present.
-		 * Do node wide tasks.
-		 */
-		nodemem[curnodeid].done = DONE_BUILDING;
-		NODE_DATA(curnodeid)->bdata = &(bdata[curnodeid]);
-
-		/*
-	 	 * Update the chunktonid array as a node wide task. There
-		 * are too many smalls mds on first node to do this per md.
-	 	 */
-		pstart = __pa(nodemem[curnodeid].start);
-		pend = __pa(nodemem[curnodeid].end);
-		pstart &= CHUNKMASK;
-		pend = (pend + CHUNKSZ - 1) & CHUNKMASK;
-		/* Possible check point to enforce minimum node size */
-		if (nodemem[curnodeid].bstart == -1) {
-			printk("No valid bootmem area on node %d\n", curnodeid);
-			while(1);
-		}
-		for (i = PCHUNKNUM(pstart); i <= PCHUNKNUM(pend - 1); i++)
-			chunktonid[i] = curnodeid;
-		if ((CHUNKTONID(PCHUNKNUM(pend)) > MAXCHUNKS) || 
-				(PCHUNKNUM(pstart) >= PCHUNKNUM(pend))) {
-			printk("Ign 0x%lx-0x%lx, ", __pa(start), __pa(end));
-			return(0);
-		}
-
-		/*
-		 * NODE_START and NODE_SIZE determine the physical range
-		 * on the node that mem_map array needs to be set up for.
-		 */
-		NODE_START(curnodeid) = ((nodemem[curnodeid].start >> 
-				SN1_NODE_ADDR_SHIFT) << SN1_NODE_ADDR_SHIFT);
-		NODE_SIZE(curnodeid) = (nodemem[curnodeid].end - 
-							NODE_START(curnodeid));
-
-        	nodemem[curnodeid].bsize = 
-			init_bootmem_node(NODE_DATA(curnodeid),
-			(__pa(nodemem[curnodeid].bstart) >> PAGE_SHIFT),
-			(__pa((nodemem[curnodeid].start >> SN1_NODE_ADDR_SHIFT)
-			<< SN1_NODE_ADDR_SHIFT) >> PAGE_SHIFT),
-			(__pa(nodemem[curnodeid].end) >> PAGE_SHIFT));
-
-	} else if (nodemem[curnodeid].done == DONE_NOTHING) {
-		printk("build_node_bootmem: node %d weirdness\n", curnodeid);
-		while(1);		/* Paranoia */
-	}
-
-	/*
-	 * Free the entire md.
-	 */
-	free_bootmem_node(NODE_DATA(curnodeid), __pa(start), (end - start));
-
-	/*
-	 * Reclaim back the bootmap and kernel areas.
-	 */
-	if ((start <= nodemem[curnodeid].bstart) && (end >
-						nodemem[curnodeid].bstart))
-		reserve_bootmem_node(NODE_DATA(curnodeid),
-		    __pa(nodemem[curnodeid].bstart), nodemem[curnodeid].bsize);
-	if ((start <= kaddr) && (end > kaddr))
-		reserve_bootmem_node(NODE_DATA(curnodeid),
-		    __pa(&_stext), (&_end - &_stext));
-
-	return(0);
-}
-
-void __init
-setup_sn1_bootmem(int maxnodes)
-{
-        int     i;
-
-        for (i = 0; i < MAXNODES; i++) {
-                nodemem[i].start = nodemem[i].bstart = -1;
-                nodemem[i].end = nodemem[i].bsize = nodemem[i].mtot = 0;
-		nodemem[i].done = DONE_NOTHING;
-		memset(&nodemem[i].hole, -1, sizeof(nodemem[i].hole));
-        }
-        efi_memmap_walk(build_nodemem_map, 0);
-
-	nodemem_valid = 1;
-
-	/* 
-	 * After building the nodemem map, check if the node memmap
-	 * will fit in the first bank of each node. If not change
-	 * the node end addr till it fits.
- 	 */
-
-        for (i = 0; i < maxnodes; i++)
-		check_pgtbl_size(i);
-
-	dump_nodemem_map(maxnodes);
-
-	efi_memmap_walk(find_node_bootmem, 0);
-	efi_memmap_walk(build_node_bootmem, 0);
-}
-#endif
-
-void __init
-discontig_paging_init(void)
-{
-	int i;
-	unsigned long max_dma, zones_size[MAX_NR_ZONES], holes_size[MAX_NR_ZONES];
-	extern void dump_node_data(void);
-
-	max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT;
-	for (i = 0; i < numnodes; i++) {
-		unsigned long startpfn = __pa((void *)NODE_START(i)) >> PAGE_SHIFT;
-		unsigned long numpfn = NODE_SIZE(i) >> PAGE_SHIFT;
-		memset(zones_size, 0, sizeof(zones_size));
-		memset(holes_size, 0, sizeof(holes_size));
-		holes_size[ZONE_DMA] = numpfn - nodemem[i].mtot;
-
-		if ((startpfn + numpfn) < max_dma) {
-			zones_size[ZONE_DMA] = numpfn;
-		} else if (startpfn > max_dma) {
-			zones_size[ZONE_NORMAL] = numpfn;
-			panic("discontig_paging_init: %d\n", i);
-		} else {
-			zones_size[ZONE_DMA] = (max_dma - startpfn);
-			zones_size[ZONE_NORMAL] = numpfn - zones_size[ZONE_DMA];
-			panic("discontig_paging_init: %d\n", i);
-		}
-		free_area_init_node(i, NODE_DATA(i), NULL, zones_size, startpfn<<PAGE_SHIFT, holes_size);
-		free_unused_memmap_node(i);
-	}
-	dump_node_data();
-}
-
-/*
- * This used to be invoked from an SN1 specific hack in efi_memmap_walk.
- * It tries to ignore banks which the kernel is ignoring because bank 0 
- * is too small to hold the memmap entries for this bank.
- * The current SN1 efi_memmap_walk callbacks do not need this. That 
- * leaves the generic ia64 callbacks find_max_pfn, count_pages and
- * count_reserved_pages, of which the first can probably get by without
- * this, the last two probably need this, although they also can probably
- * get by. 
- */
-int
-sn1_bank_ignore(u64 start, u64 end)
-{
-	int 	nid = NASID_TO_CNODEID(GetNasId(__pa(end))) ;
-	int	bank = GetBankId(__pa(end)) ;
-
-	if (!nodemem_valid)
-		return 0 ;
-
-	if (nodemem[nid].hole[bank] == -1)
-		return 1 ;
-	else
-		return 0 ;
-}
-
-void
-dump_nodemem_map(int maxnodes)
-{
-	int	i,j;
-
-        printk("NODEMEM_S info ....\n") ;
-        printk("Node         start                end\n");
-        for (i=0;i<maxnodes;i++) {
-                printk("%d      0x%lx   0x%lx\n",
-                       i, nodemem[i].start, nodemem[i].end);
-                printk("Holes -> ") ;
-                for (j=0;j<SN1_MAX_BANK_PER_NODE;j++)
-                        printk("0x%lx ", nodemem[i].hole[j]) ;
-		printk("\n");
-        }
-}
-
diff -Nru a/arch/ia64/sn/sn1/probe.c b/arch/ia64/sn/sn1/probe.c
--- a/arch/ia64/sn/sn1/probe.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,62 +0,0 @@
-/*
- * Platform dependent support for IO probing.
- *
- * Copyright (C) 2000   Silicon Graphics
- * Copyright (C) 2000   Jack Steiner (steiner@sgi.com)
- */
-
-#include <asm/sn/sn_sal.h>
-
-/*
- * ia64_sn_probe_io_slot
- *	This function will probe a physical address to determine if
- *	the address can be read. If reading the address causes a BUS
- *	error, an error is returned. If the probe succeeds, the contents 
- *	of the memory location is returned.
- *
- *   Calling sequence:
- *		ia64_probe_io_slot(paddr, size, data_ptr)
- *
- *   Input:
- *	paddr		Physical address to probe
- *	size		Number bytes to read (1,2,4,8)
- *	data_ptr	Address to store value read by probe
- *		          (-1 returned if probe fails)
- *
- *   Output:
- *	Status
- *		 0 - probe successful
- *		 1 - probe failed (generated MCA)
- *		 2 - Bad arg
- *		<0 - PAL error
- */
-
-
-u64
-ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr)
-{
-	struct ia64_sal_retval isrv;
-
-	SAL_CALL(isrv, SN_SAL_PROBE, paddr, size, 0, 0, 0, 0, 0);
-
-	if (data_ptr) {
-		switch (size) {
-			case 1:
-				*((u8*)data_ptr) = (u8)isrv.v0;
-				break;
-			case 2:
-				*((u16*)data_ptr) = (u16)isrv.v0;
-				break;
-			case 4:
-				*((u32*)data_ptr) = (u32)isrv.v0;
-				break;
-			case 8:
-				*((u64*)data_ptr) = (u64)isrv.v0;
-				break;
-			default:
-				isrv.status = 2;	
-		}
-	}
-
-	return isrv.status;
-}
diff -Nru a/arch/ia64/sn/sn1/setup.c b/arch/ia64/sn/sn1/setup.c
--- a/arch/ia64/sn/sn1/setup.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,254 +0,0 @@
-/*
- *
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
- */
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/kdev_t.h>
-#include <linux/string.h>
-#include <linux/tty.h>
-#include <linux/console.h>
-#include <linux/timex.h>
-#include <linux/sched.h>
-#include <linux/ioport.h>
-#include <linux/mm.h>
-#include <linux/serial.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/io.h>
-#include <asm/dma.h>
-#include <asm/machvec.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <asm-ia64/sn/arch.h>
-#include <asm-ia64/sn/addrs.h>
-
-
-/*
- * This is the address of the RRegs in the HSpace of the global
- * master.  It is used by a hack in serial.c (serial_[in|out],
- * printk.c (early_printk), and kdb_io.c to put console output on that
- * node's Bedrock UART.  It is initialized here to 0, so that
- * early_printk won't try to access the UART before
- * master_node_bedrock_address is properly calculated.
- */
-u64 master_node_bedrock_address = 0UL;
-
-static void sn_fix_ivt_for_partitioned_system(void);
-
-
-/*
- * The format of "screen_info" is strange, and due to early i386-setup
- * code. This is just enough to make the console code think we're on a
- * VGA color display.
- */
-struct screen_info sn1_screen_info = {
-	orig_x:			 0,
-	orig_y:			 0,
-	orig_video_mode:	 3,
-	orig_video_cols:	80,
-	orig_video_ega_bx:	 3,
-	orig_video_lines:	25,
-	orig_video_isVGA:	 1,
-	orig_video_points:	16
-};
-
-/*
- * This is here so we can use the CMOS detection in ide-probe.c to
- * determine what drives are present.  In theory, we don't need this
- * as the auto-detection could be done via ide-probe.c:do_probe() but
- * in practice that would be much slower, which is painful when
- * running in the simulator.  Note that passing zeroes in DRIVE_INFO
- * is sufficient (the IDE driver will autodetect the drive geometry).
- */
-char drive_info[4*16];
-
-unsigned long
-sn1_map_nr (unsigned long addr)
-{
-#ifdef CONFIG_DISCONTIGMEM
-	return MAP_NR_SN1(addr);
-#else
-	return MAP_NR_DENSE(addr);
-#endif
-}
-
-#if defined(BRINGUP) && defined(CONFIG_IA64_EARLY_PRINTK)
-void __init
-early_sn1_setup(void)
-{
-	master_node_bedrock_address = 
-		(u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
-	printk("early_sn1_setup: setting master_node_bedrock_address to 0x%lx\n", master_node_bedrock_address);
-}
-#endif /* BRINGUP && CONFIG_IA64_EARLY_PRINTK */
-
-void __init
-sn1_setup(char **cmdline_p)
-{
-#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-	struct serial_struct req;
-#endif
-
-	MAX_DMA_ADDRESS = PAGE_OFFSET + 0x10000000000UL;
-	master_node_bedrock_address = 
-		(u64)REMOTE_HSPEC_ADDR(get_nasid(), 0);
-	printk("sn1_setup: setting master_node_bedrock_address to 0x%lx\n",
-		   master_node_bedrock_address);
-
-#if defined(CONFIG_SERIAL) && !defined(CONFIG_SERIAL_SGI_L1_PROTOCOL)
-	/*
-	 * We do early_serial_setup() to clean out the rs-table[] from the
-	 * statically compiled in version.
-	 */
-	memset(&req, 0, sizeof(struct serial_struct));
-	req.line = 0;
-	req.baud_base = 124800;
-	req.port = 0;
-	req.port_high = 0;
-	req.irq = 0;
-	req.flags = (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST);
-	req.io_type = SERIAL_IO_MEM;
-	req.hub6 = 0;
-	req.iomem_base = (u8 *)(master_node_bedrock_address + 0x80);
-	req.iomem_reg_shift = 3;
-	req.type = 0;
-	req.xmit_fifo_size = 0;
-	req.custom_divisor = 0;
-	req.closing_wait = 0;
-	early_serial_setup(&req);
-#endif /* CONFIG_SERIAL && !CONFIG_SERIAL_SGI_L1_PROTOCOL */
-
-	ROOT_DEV = to_kdev_t(0x0301);		/* default to first IDE drive */
-	sn_fix_ivt_for_partitioned_system();
-
-#ifdef CONFIG_SMP
-	init_smp_config();
-#endif
-	screen_info = sn1_screen_info;
-}
-
-
-/* 
- * sn_fix_ivt_for_partitioned_system
- *
- * This is an ugly hack that is needed for partitioned systems.
- *
- * On a partitioned system, most partitions do NOT have a physical address 0.
- * Unfortunately, the exception handling code in ivt.S has a couple of physical
- * addresses of kernel structures hardcoded into "movl" instructions.
- * These addresses are correct on partition 0 only. On all other partitions,
- * the addresses must be changed to reference the correct address.
- *
- * This routine scans the ivt code and replaces the hardcoded addresses with 
- * the correct address.
- *
- * Note that we could have made the ivt.S code dynamically determine the correct
- * address but this would add code to performance critical pathes. This option
- * was rejected.
- */
-
-#define TEMP_mlx	4		/* template type that contains movl instruction */
-#define TEMP_mlX	5		/* template type that contains movl instruction */
-
-typedef union {				/* Instruction encoding for movl instruction */
-	struct {
-		unsigned long	qp:6;
-		unsigned long	r1:7;
-		unsigned long	imm7b:7;
-		unsigned long	vc:1;
-		unsigned long	ic:1;
-		unsigned long	imm5c:5;
-		unsigned long	imm9d:9;
-		unsigned long	i:1;
-		unsigned long	op:4;
-		unsigned long	fill:23;
-	} b;
-	unsigned long	l;
-} movl_instruction_t;
-
-#define MOVL_OPCODE	6
-#define MOVL_ARG(a,b)	(((long)a.i<<63) | ((long)b<<22) | ((long)a.ic<<21) | \
-			((long)a.imm5c<<16) | ((long)a.imm9d<<7) | ((long)a.imm7b))
-
-typedef struct {				/* Instruction bundle */
-	unsigned long template:5;
-	unsigned long ins2:41;
-	unsigned long ins1l:18;
-	unsigned long ins1u:23;
-	unsigned long ins0:41;
-} instruction_bundle_t;
-
-
-static void __init
-sn_fix_ivt_for_partitioned_system(void)
-{
-	extern int		ia64_ivt;
-	instruction_bundle_t	*p, *pend;
-	movl_instruction_t	ins0, ins1, ins2;
-	long			new_ins1, phys_offset;
-	unsigned long		val;
-
-	/*
-	 * Setup to scan the ivt code.
-	 */
-	p = (instruction_bundle_t*)&ia64_ivt;
-	pend = p + 0x8000/sizeof(instruction_bundle_t);
-	phys_offset = __pa(p) & ~0x1ffffffffUL;
-
-	/*
-	 * Hunt for movl instructions that contain the node 0 physical address 
-	 * of "SWAPPER_PGD_ADDR".  These addresses must be relocated to reference the 
-	 * actual node that the kernel is loaded on.
-	 */
-	for (; p < pend; p++) {
-		if (p->template != TEMP_mlx && p->template != TEMP_mlX)
-			continue;
-		ins0.l =  p->ins0;
-		if (ins0.b.op != MOVL_OPCODE)
-			continue;
-		ins1.l =  ((long)p->ins1u<<18) | p->ins1l;
-		ins2.l =  p->ins2;
-		val = MOVL_ARG(ins0.b, ins1.l);
-
-		/*
-		 * Test for correct address. SWAPPER_PGD_ADDR will
-		 * always be a node 0 virtual address. Note that we cant
-		 * use the __pa or __va macros here since they may contain
-		 * debug code that gets fooled here.
-		 */
-		if ((PAGE_OFFSET | val)  != SWAPPER_PGD_ADDR)
-			continue;
-
-		/*
-		 * We found an instruction that needs to be fixed. The following
-		 * inserts the NASID of the ivt into the movl instruction.
-		 */
-		new_ins1 = ins1.l | (phys_offset>>22);
-		p->ins1l = new_ins1 & 0x3ffff;
-		p->ins1u = (new_ins1>>18) & 0x7fffff;
-		ia64_fc(p);
-	}
-
-	/*
-	 * Do necessary serialization.
-	 */
-	ia64_sync_i();
-	ia64_srlz_i();
-
-}
-
-int
-IS_RUNNING_ON_SIMULATOR(void)
-{
-#ifdef CONFIG_IA64_SGI_SN1_SIM
-	long sn;
-	asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2));
-	return(sn == SNMAGIC);
-#else
-	return(0);
-#endif
-}
diff -Nru a/arch/ia64/sn/sn1/smp.c b/arch/ia64/sn/sn1/smp.c
--- a/arch/ia64/sn/sn1/smp.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,186 +0,0 @@
-/*
- * SN1 Platform specific SMP Support
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Jack Steiner <steiner@sgi.com>
- */
-
-
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/threads.h>
-#include <linux/sched.h>
-#include <linux/smp.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/sal.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/smp.h>
-#include <asm/current.h>
-#include <asm/sn/sn_cpuid.h>
-
-
-
-
-/*
- * The following structure is used to pass params thru smp_call_function
- * to other cpus for flushing TLB ranges.
- */
-typedef struct {
-	unsigned long	start;
-	unsigned long	end;
-	unsigned long	nbits;
-} ptc_params_t;
-
-
-/*
- * The following table/struct is for remembering PTC coherency domains. It
- * is also used to translate sapicid into cpuids. We dont want to start 
- * cpus unless we know their cache domain.
- */
-#ifdef PTC_NOTYET
-sn_sapicid_info_t	sn_sapicid_info[NR_CPUS];
-#endif
-
-
-
-#ifdef PTC_NOTYET
-/*
- * NOTE: This is probably not good enough, but I dont want to try to make
- * it better until I get some statistics on a running system. 
- * At a minimum, we should only send IPIs to 1 processor in each TLB domain
- * & have it issue a ptc.g on it's own FSB. Also, serialize per FSB, not 
- * globally.
- *
- * More likely, we will have to do some work to reduce the frequency of calls to
- * this routine.
- */
-
-static void
-sn1_ptc_local(void *arg)
-{
-	ptc_params_t	*params = arg;
-	unsigned long	start, end, nbits;
-
-	start = params->start;
-	end = params->end;
-	nbits = params->nbits;
-
-	do {
-		__asm__ __volatile__ ("ptc.l %0,%1" :: "r"(start), "r"(nbits<<2) : "memory");
-		start += (1UL << nbits);
-	} while (start < end);
-}
-
-
-void
-sn1_ptc_global (unsigned long start, unsigned long end, unsigned long nbits)
-{
-	ptc_params_t	params;
-
-	params.start = start;
-	params.end = end;
-	params.nbits = nbits;
-
-	if (smp_call_function(sn1_ptc_local, &params, 1, 0) != 0)
-		panic("Unable to do ptc_global - timed out");
-
-	sn1_ptc_local(&params);
-}
-#endif
-
-
-
-
-void
-sn1_send_IPI(int cpuid, int vector, int delivery_mode, int redirect)
-{
-	long		*p, nasid, slice;
-	static int 	off[4] = {0x1800080, 0x1800088, 0x1a00080, 0x1a00088};
-
-	/*
-	 * ZZZ - Replace with standard macros when available.
-	 */
-	nasid = cpuid_to_nasid(cpuid);
-	slice = cpuid_to_slice(cpuid);
-	p = (long*)(0xc0000a0000000000LL | (nasid<<33) | off[slice]);
-
-#if defined(ZZZBRINGUP)
-	{
-	static int count=0;
-	if (count++ < 10) printk("ZZ sendIPI 0x%x->0x%x, vec %d, nasid 0x%lx, slice %ld, adr 0x%lx\n",
-		smp_processor_id(), cpuid, vector, nasid, slice, (long)p);
-	}
-#endif
-	mb();
-	*p = (delivery_mode << 8) | (vector & 0xff);
-	
-}
-
-
-#ifdef CONFIG_SMP
-
-#ifdef PTC_NOTYET
-static void __init
-process_sal_ptc_domain_info(ia64_sal_ptc_domain_info_t *di, int domain)
-{
-	ia64_sal_ptc_domain_proc_entry_t	*pe;
-	int 					i, sapicid, cpuid;
-
-	pe = __va(di->proc_list);
-	for (i=0; i<di->proc_count; i++, pe++) {
-		sapicid = id_eid_to_sapicid(pe->id, pe->eid);
-		cpuid = cpu_logical_id(sapicid);
-		sn_sapicid_info[cpuid].domain = domain;
-		sn_sapicid_info[cpuid].sapicid = sapicid;
-	}
-}
-
-
-static void __init
-process_sal_desc_ptc(ia64_sal_desc_ptc_t *ptc)
-{
-	ia64_sal_ptc_domain_info_t	*di;
-	int i;
-
-	di = __va(ptc->domain_info);
-	for (i=0; i<ptc->num_domains; i++, di++) {
-		process_sal_ptc_domain_info(di, i);	
-	}
-}
-#endif
-
-
-void __init
-init_sn1_smp_config(void)
-{
-
-	if (!ia64_ptc_domain_info)  {
-		printk("SMP: Can't find PTC domain info. Forcing UP mode\n");
-		smp_num_cpus = 1;
-		return;
-	}
-
-#ifdef PTC_NOTYET
-	memset (sn_sapicid_info, -1, sizeof(sn_sapicid_info));
-	process_sal_desc_ptc(ia64_ptc_domain_info);
-#endif
-
-}
-
-#else /* CONFIG_SMP */
-
-void __init
-init_sn1_smp_config(void)
-{
-
-#ifdef PTC_NOTYET
-	sn_sapicid_info[0].sapicid = hard_smp_processor_id();
-#endif
-}
-
-#endif /* CONFIG_SMP */
diff -Nru a/arch/ia64/sn/sn1/sn1_asm.S b/arch/ia64/sn/sn1/sn1_asm.S
--- a/arch/ia64/sn/sn1/sn1_asm.S	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,149 +0,0 @@
-
-/*
- * Copyright (C) 2000 Silicon Graphics
- * Copyright (C) 2000 Jack Steiner (steiner@sgi.com)
- */
-
-#include <linux/config.h>
-#ifdef CONFIG_IA64_SGI_AUTOTEST
-
-// Testing only.
-// Routine will cause MCAs
-//   zzzmsa(n)
-//      n=0 MCA via duplicate TLB dropin
-//      n=0 MCA via read of garbage address
-//
-
-#define ITIR(key, ps)           ((key<<8) | (ps<<2))
-#define TLB_PAGESIZE            28                      // Use 256MB pages for now.
-
-                        .global zzzmca
-                        .proc   zzzmca
-zzzmca:
-                        alloc   loc4       = ar.pfs,2,8,1,0;;
-                        cmp.ne  p6,p0=r32,r0;;
-                        movl    r2=0x2dead
-                        movl    r3=0x3dead
-                        movl    r15=0x15dead
-                        movl    r16=0x16dead
-                        movl    r31=0x31dead
-                        movl    loc0=0x34beef
-                        movl    loc1=0x35beef
-                        movl    loc2=0x36beef
-                        movl    loc3=0x37beef
-                        movl    out0=0x42beef
-
-                        movl    r20=0x32feed;;
-                        mov     ar32=r20
-                        movl    r20=0x36feed;;
-                        mov     ar36=r20
-                        movl    r20=0x65feed;;
-                        mov     ar65=r20
-                        movl    r20=0x66feed;;
-                        mov     ar66=r20
-
-(p6)                    br.cond.sptk    1f
-
-                        rsm      0x2000;;
-                        srlz.d;
-                        mov      r11      = 1
-                        mov      r3       = ITIR(0,TLB_PAGESIZE);;
-                        mov      cr.itir  = r3
-                        mov      r10      = 0;;
-                        itr.d    dtr[r11] = r10;;
-                        mov      r11      = 2
-
-                        itr.d    dtr[r11] = r10;;
-                        br      9f
-
-1:                      movl    r8=0xfe00000048;;
-                        ld8     r9=[r8];;
-                        mf
-                        mf.a
-                        srlz.d
-
-9:                      mov     ar.pfs=loc4
-                        br.ret.sptk     rp
-
-                        .endp   zzzmca
-
-                        .global zzzspec
-                        .proc   zzzspec
-zzzspec:
-			mov	r8=r32
-			movl	r9=0xe000000000000000
-			movl	r10=0x4000;;
-			ld8.s	r16=[r8];;
-			ld8.s	r17=[r9];;
-			add	r8=r8,r10;;
-			ld8.s	r18=[r8];;
-			add	r8=r8,r10;;
-			ld8.s	r19=[r8];;
-			add	r8=r8,r10;;
-			ld8.s	r20=[r8];;
-			mov	r8=r0
-			tnat.nz	p6,p0=r16
-			tnat.nz	p7,p0=r17
-			tnat.nz	p8,p0=r18
-			tnat.nz	p9,p0=r19
-			tnat.nz	p10,p0=r20;;
-		(p6)	dep	r8=-1,r8,0,1;;
-		(p7)	dep	r8=-1,r8,1,1;;
-		(p8)	dep	r8=-1,r8,2,1;;
-		(p9)	dep	r8=-1,r8,3,1;;
-		(p10)	dep	r8=-1,r8,4,1;;
-                        br.ret.sptk     rp
-                        .endp   zzzspec
-
-                        .global zzzspec2
-                        .proc   zzzspec2
-zzzspec2:
-			cmp.eq	p6,p7=r2,r2
-			movl	r16=0xc0000a0001000020
-			;;
-			mf
-			;;
-			ld8	r9=[r16]
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			ld8	r9=[r16];;
-			cmp.ne	p6,p7=r9,r16
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			ld8	r9=[r33];;
-			cmp.ne	p6,p7=r9,r33
-		(p6)	br.spnt	1f
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-
-			tpa	r23=r32
-			add	r20=512,r33
-			add	r21=1024,r33;;
-			ld8	r9=[r20]
-			ld8	r10=[r21];;
-			nop.i	0
-			{ .mib
-			nop.m 0
-			cmp.ne	p6,p7=r10,r33
-		(p6)	br.spnt	1f
-			}
-			ld8	r10=[r32]
-			;;
-		1:	mf.a
-			mf
-			br.ret.sptk     rp
-
-                        .endp   zzzspec
-
-#endif
-
diff -Nru a/arch/ia64/sn/sn1/sn1_ksyms.c b/arch/ia64/sn/sn1/sn1_ksyms.c
--- a/arch/ia64/sn/sn1/sn1_ksyms.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,39 +0,0 @@
-/* 
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Jesse Barnes (jbarnes@sgi.com)
- */
-
-
-/*
- * Architecture-specific kernel symbols
- */
-
-#include <linux/module.h>
-
-#include <asm/machvec.h>
-
-/*
- * I/O routines
- */
-EXPORT_SYMBOL(sn1_outb);
-EXPORT_SYMBOL(sn1_outl);
-EXPORT_SYMBOL(sn1_outw);
-EXPORT_SYMBOL(sn1_inw);
-EXPORT_SYMBOL(sn1_inb);
-EXPORT_SYMBOL(sn1_inl);
-
-/*
- * other stuff (more to be added later, cleanup then)
- */
-EXPORT_SYMBOL(sn1_pci_map_sg);
-EXPORT_SYMBOL(sn1_pci_unmap_sg);
-EXPORT_SYMBOL(sn1_pci_alloc_consistent);
-EXPORT_SYMBOL(sn1_pci_free_consistent);
-EXPORT_SYMBOL(sn1_dma_address);
-
-#include <linux/mm.h>
-EXPORT_SYMBOL(alloc_pages);
diff -Nru a/arch/ia64/sn/sn1/sv.c b/arch/ia64/sn/sn1/sv.c
--- a/arch/ia64/sn/sn1/sv.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,551 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.  All rights reserved
- *
- * This implemenation of synchronization variables is heavily based on
- * one done by Steve Lord <lord@sgi.com>
- *
- * Paul Cassella <pwc@sgi.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-
-#include <asm/semaphore.h>
-#include <asm/hardirq.h>
-#include <asm/softirq.h>
-#include <asm/current.h>
-
-#include <asm/sn/sv.h>
-
-/* Define this to have sv_test() run some simple tests.
-   kernel_thread() must behave as expected when this is called.  */
-#undef RUN_SV_TEST
-
-#define DEBUG
-
-/* Set up some macros so sv_wait(), sv_signal(), and sv_broadcast()
-   can sanity check interrupt state on architectures where we know
-   how. */
-#ifdef DEBUG
- #define SV_DEBUG_INTERRUPT_STATE
- #ifdef __mips64
-  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x1) != 0)
-  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x1) == 0)
-  #define SV_INTERRUPT_TEST_WORKERS 31
- #elif defined(__ia64)
-  #define SV_TEST_INTERRUPTS_ENABLED(flags) ((flags & 0x4000) != 0)
-  #define SV_TEST_INTERRUPTS_DISABLED(flags) ((flags & 0x4000) == 0)
-  #define SV_INTERRUPT_TEST_WORKERS 4 /* simulator's slow */
- #else
-  #undef  SV_DEBUG_INTERRUPT_STATE
-  #define SV_INTERRUPT_TEST_WORKERS 4 /* reasonable? default. */
- #endif /* __mips64 */
-#endif /* DEBUG */
-
-
-/* XXX FIXME hack hack hack.  Our mips64 tree is from before the
-   switch to WQ_FLAG_EXCLUSIVE, and our ia64 tree is from after it. */
-#ifdef TASK_EXCLUSIVE
-  #undef EXCLUSIVE_IN_QUEUE
-#else
-  #define EXCLUSIVE_IN_QUEUE
-  #define TASK_EXCLUSIVE 0 /* for the set_current_state() in sv_wait() */
-#endif
-
-
-static inline void sv_lock(sv_t *sv) {
-	spin_lock(&sv->sv_lock);
-}
-
-static inline void sv_unlock(sv_t *sv) {
-	spin_unlock(&sv->sv_lock);
-}
-
-/* up() is "extern inline", so we can't pass its address to sv_wait.
-   Use this function's address instead. */
-static void up_wrapper(struct semaphore *sem) {
-	up(sem);
-}
-
-/* spin_unlock() is sometimes a macro. */
-static void spin_unlock_wrapper(spinlock_t *s) {
-	spin_unlock(s);
-}
-
-/* XXX Perhaps sv_wait() should do the switch() each time and avoid
-   the extra indirection and the need for the _wrapper functions? */
-
-static inline void sv_set_mon_type(sv_t *sv, int type) {
-	switch (type) {
-	case SV_MON_SPIN:
-		sv->sv_mon_unlock_func =
-		  (sv_mon_unlock_func_t)spin_unlock_wrapper;
-		break;
-	case SV_MON_SEMA:
-		sv->sv_mon_unlock_func =
-		  (sv_mon_unlock_func_t)up_wrapper;
-		if(sv->sv_flags & SV_INTS) {
-			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
-			       "cannot be shared with interrupts if it is a "
-			       "semaphore!\n");
-			BUG();
-		}
-		if(sv->sv_flags & SV_BHS) {
-			printk(KERN_ERR "sv_set_mon_type: The monitor lock "
-			       "cannot be shared with bottom-halves if it is "
-			       "a semaphore!\n");
-			BUG();
-		}
-		break;
-#if 0 
-	/*
-	 * If needed, and will need to think about interrupts.  This
-	 * may be needed, for example, if someone wants to use sv's
-	 * with something like dev_base; writers need to hold two
-	 * locks. 
-	 */
-	case SV_MON_CUSTOM: 
-		{
-		struct sv_mon_custom *c = lock;
-		sv->sv_mon_unlock_func = c->sv_mon_unlock_func;
-		sv->sv_mon_lock        = c->sv_mon_lock;
-		break;
-		}
-#endif
-		
-	default:
-		printk(KERN_ERR "sv_set_mon_type: unknown type %d (0x%x)! "
-		       "(flags 0x%x)\n", type, type, sv->sv_flags);
-		BUG();
-		break;
-	}
-	sv->sv_flags |= type;
-}
-
-static inline void sv_set_ord(sv_t *sv, int ord) {
-	if (!ord)
-		ord = SV_ORDER_DEFAULT;
-
-	if (ord != SV_ORDER_FIFO && ord != SV_ORDER_LIFO) {
-		printk(KERN_EMERG "sv_set_ord: unknown order %d (0x%x)! ",
-		       ord, ord);
-		BUG();
-	}
-
-	sv->sv_flags |= ord;
-}
-
-void sv_init(sv_t *sv, sv_mon_lock_t *lock, int flags) 
-{
-	int ord = flags & SV_ORDER_MASK;
-	int type = flags & SV_MON_MASK;
-
-	/* Copy all non-order, non-type flags */
-	sv->sv_flags = (flags & ~(SV_ORDER_MASK | SV_MON_MASK));
-
-	if((sv->sv_flags & (SV_INTS | SV_BHS)) == (SV_INTS | SV_BHS)) {
-	  printk(KERN_ERR "sv_init: do not set both SV_INTS and SV_BHS, only SV_INTS.\n");
-	  BUG();
-	}
-
-	sv_set_ord(sv, ord);
-	sv_set_mon_type(sv, type);
-
-	/* If lock is NULL, we'll get it from sv_wait_compat() (and
-           ignore it in sv_signal() and sv_broadcast()). */
-	sv->sv_mon_lock = lock;
-
-	spin_lock_init(&sv->sv_lock);
-	init_waitqueue_head(&sv->sv_waiters);
-}
-
-/*
- * The associated lock must be locked on entry.  It is unlocked on return.
- *
- * Return values:
- *
- * n < 0 : interrupted,  -n jiffies remaining on timeout, or -1 if timeout == 0
- * n = 0 : timeout expired
- * n > 0 : sv_signal()'d, n jiffies remaining on timeout, or 1 if timeout == 0
- */
-signed long sv_wait(sv_t *sv, int sv_wait_flags, unsigned long timeout) 
-{
-	DECLARE_WAITQUEUE( wait, current );
-	unsigned long flags;
-	signed long ret = 0;
-
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	{
-	unsigned long flags;
-	__save_flags(flags);
-
-	if(sv->sv_flags & SV_INTS) {
-		if(SV_TEST_INTERRUPTS_ENABLED(flags)) {
-			printk(KERN_ERR "sv_wait: SV_INTS and interrupts "
-			       "enabled (flags: 0x%lx)\n", flags);
-			BUG();
-		}
-	} else {
-		if (SV_TEST_INTERRUPTS_DISABLED(flags)) {
-			printk(KERN_WARNING "sv_wait: !SV_INTS and interrupts "
-			       "disabled! (flags: 0x%lx)\n", flags);
-		}
-	}
-	}
-#endif  /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-
-	sv->sv_mon_unlock_func(sv->sv_mon_lock);
-
-	/* Add ourselves to the wait queue and set the state before
-	 * releasing the sv_lock so as to avoid racing with the
-	 * wake_up() in sv_signal() and sv_broadcast(). 
-	 */
-
-	/* don't need the _irqsave part, but there is no wq_write_lock() */
-	wq_write_lock_irqsave(&sv->sv_waiters.lock, flags);
-
-#ifdef EXCLUSIVE_IN_QUEUE
-	wait.flags |= WQ_FLAG_EXCLUSIVE;
-#endif
-
-	switch(sv->sv_flags & SV_ORDER_MASK) {
-	case SV_ORDER_FIFO:
-		__add_wait_queue_tail(&sv->sv_waiters, &wait);
-		break;
-	case SV_ORDER_FILO:
-		__add_wait_queue(&sv->sv_waiters, &wait);
-		break;
-	default:
-		printk(KERN_ERR "sv_wait: unknown order!  (sv: 0x%p, flags: 0x%x)\n",
-					sv, sv->sv_flags);
-		BUG();
-	}
-	wq_write_unlock_irqrestore(&sv->sv_waiters.lock, flags);
-
-	if(sv_wait_flags & SV_WAIT_SIG)
-		set_current_state(TASK_EXCLUSIVE | TASK_INTERRUPTIBLE  );
-	else
-		set_current_state(TASK_EXCLUSIVE | TASK_UNINTERRUPTIBLE);
-
-	spin_unlock(&sv->sv_lock);
-
-	if(sv->sv_flags & SV_INTS)
-		local_irq_enable();
-	else if(sv->sv_flags & SV_BHS)
-		local_bh_enable();
-
-	if (timeout)
-		ret = schedule_timeout(timeout);
-	else
-		schedule();
-
-	if(current->state != TASK_RUNNING) /* XXX Is this possible? */ {
-		printk(KERN_ERR "sv_wait: state not TASK_RUNNING after "
-		       "schedule().\n");
-		set_current_state(TASK_RUNNING);
-	}
-
-	remove_wait_queue(&sv->sv_waiters, &wait);
-
-	/* Return cases:
-	   - woken by a sv_signal/sv_broadcast
-	   - woken by a signal
-	   - woken by timeout expiring
-	*/
-
-	/* XXX This isn't really accurate; we may have been woken
-           before the signal anyway.... */
-	if(signal_pending(current))
-		return timeout ? -ret : -1;
-	return timeout ? ret : 1;
-}
-
-
-void sv_signal(sv_t *sv) 
-{
-	/* If interrupts can acquire this lock, they can also acquire the
-	   sv_mon_lock, which we must already have to have called this, so
-	   interrupts must be disabled already.  If interrupts cannot
-	   contend for this lock, we don't have to worry about it. */
-
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	if(sv->sv_flags & SV_INTS) {
-		unsigned long flags;
-		__save_flags(flags);
-		if(SV_TEST_INTERRUPTS_ENABLED(flags))
-			printk(KERN_ERR "sv_signal: SV_INTS and "
-			"interrupts enabled! (flags: 0x%lx)\n", flags);
-	}
-#endif /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-	wake_up(&sv->sv_waiters);
-	sv_unlock(sv);
-}
-
-void sv_broadcast(sv_t *sv) 
-{
-#ifdef SV_DEBUG_INTERRUPT_STATE
-	if(sv->sv_flags & SV_INTS) {
-		unsigned long flags;
-		__save_flags(flags);
-		if(SV_TEST_INTERRUPTS_ENABLED(flags))
-			printk(KERN_ERR "sv_broadcast: SV_INTS and "
-			       "interrupts enabled! (flags: 0x%lx)\n", flags);
-	}
-#endif /* SV_DEBUG_INTERRUPT_STATE */
-
-	sv_lock(sv);
-	wake_up_all(&sv->sv_waiters);
-	sv_unlock(sv);
-}
-
-void sv_destroy(sv_t *sv) 
-{
-	if(!spin_trylock(&sv->sv_lock)) {
-		printk(KERN_ERR "sv_destroy: someone else has sv 0x%p locked!\n", sv);
-		BUG();
-	}
-
-	/* XXX Check that the waitqueue is empty? 
-	       Mark the sv destroyed?
-	*/
-}
-
-
-#ifdef RUN_SV_TEST
-
-static DECLARE_MUTEX_LOCKED(talkback);
-static DECLARE_MUTEX_LOCKED(sem);
-sv_t sv;
-sv_t sv_filo;
-
-static int sv_test_1_w(void *arg) 
-{
-	printk("sv_test_1_w: acquiring spinlock 0x%p...\n", arg);
-
-	spin_lock((spinlock_t*)arg);
-	printk("sv_test_1_w: spinlock acquired, waking sv_test_1_s.\n");
-
-	up(&sem);
-
-	printk("sv_test_1_w: sv_spin_wait()'ing.\n");
-
-	sv_spin_wait(&sv, arg);
-
-	printk("sv_test_1_w: talkback.\n");
-	up(&talkback);
-
-	printk("sv_test_1_w: exiting.\n");
-	return 0;
-}
-
-static int sv_test_1_s(void *arg) 
-{
-	printk("sv_test_1_s: waiting for semaphore.\n");
-	down(&sem);
-	printk("sv_test_1_s: semaphore acquired.  Acquiring spinlock.\n");
-	spin_lock((spinlock_t*)arg);
-	printk("sv_test_1_s: spinlock acquired.  sv_signaling.\n");
-	sv_signal(&sv);
-	printk("sv_test_1_s: talkback.\n");
-	up(&talkback);
-	printk("sv_test_1_s: exiting.\n");
-	return 0;
-
-}
-
-static int count;
-static DECLARE_MUTEX(monitor);
-
-static int sv_test_2_w(void *arg) 
-{
-	int dummy = count++;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	up(&talkback);
-	printk("sv_test_2_w: thread %d started, sv_waiting.\n", dummy);
-	sv_sema_wait(sv, &monitor);
-	printk("sv_test_2_w: thread %d woken, exiting.\n", dummy);
-	up(&sem);
-	return 0;
-}
-
-static int sv_test_2_s_1(void *arg) 
-{
-	int i;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	for(i = 0; i < 3; i++) {
-		printk("sv_test_2_s_1: waking one thread.\n");
-		sv_signal(sv);
-		down(&sem);
-	}
-
-	printk("sv_test_2_s_1: signaling and broadcasting again.  Nothing should happen.\n");
-	sv_signal(sv);
-	sv_broadcast(sv);
-	sv_signal(sv);
-	sv_broadcast(sv);
-
-	printk("sv_test_2_s_1: talkbacking.\n");
-	up(&talkback);
-	up(&monitor);
-	return 0;
-}
-
-static int sv_test_2_s(void *arg) 
-{
-	int i;
-	sv_t *sv = (sv_t *)arg;
-
-	down(&monitor);
-	for(i = 0; i < 3; i++) {
-		printk("sv_test_2_s: waking one thread (should be %d.)\n", i);
-		sv_signal(sv);
-		down(&sem);
-	}
-
-	printk("sv_test_3_s: waking remaining threads with broadcast.\n");
-	sv_broadcast(sv);
-	for(; i < 10; i++)
-		down(&sem);
-
-	printk("sv_test_3_s: sending talkback.\n");
-	up(&talkback);
-
-	printk("sv_test_3_s: exiting.\n");
-	up(&monitor);
-	return 0;
-}
-
-
-static void big_test(sv_t *sv) 
-{
-	int i;
-
-	count = 0;
-
-	for(i = 0; i < 3; i++) {
-		printk("big_test: spawning thread %d.\n", i);
-		kernel_thread(sv_test_2_w, sv, 0);
-		down(&talkback);
-	}
-
-	printk("big_test: spawning first wake-up thread.\n");
-	kernel_thread(sv_test_2_s_1, sv, 0);
-
-	down(&talkback);
-	printk("big_test: talkback happened.\n");
-
-
-	for(i = 3; i < 13; i++) {
-		printk("big_test: spawning thread %d.\n", i);
-		kernel_thread(sv_test_2_w, sv, 0);
-		down(&talkback);
-	}
-
-	printk("big_test: spawning wake-up thread.\n");
-	kernel_thread(sv_test_2_s, sv, 0);
-
-	down(&talkback);
-}
-
-sv_t int_test_sv;
-spinlock_t int_test_spin = SPIN_LOCK_UNLOCKED;
-int int_test_ready;
-static int irqtestcount;
-
-static int interrupt_test_worker(void *unused) 
-{
-	int id = ++irqtestcount;
-	int it = 0;
-			unsigned long flags, flags2;
-
-	printk("ITW: thread %d started.\n", id);
-
-	while(1) {
-		__save_flags(flags2);
-		if(jiffies % 3) {
-			printk("ITW %2d %5d: irqsaving          (%lx)\n", id, it, flags2);
-			spin_lock_irqsave(&int_test_spin, flags);
-		} else {
-			printk("ITW %2d %5d: spin_lock_irqing   (%lx)\n", id, it, flags2);
-			spin_lock_irq(&int_test_spin);
-		}
-
-		__save_flags(flags2);
-		printk("ITW %2d %5d: locked, sv_waiting (%lx).\n", id, it, flags2);
-		sv_wait(&int_test_sv, 0, 0);
-
-		__save_flags(flags2);
-		printk("ITW %2d %5d: wait finished      (%lx), pausing\n", id, it, flags2);
-		set_current_state(TASK_INTERRUPTIBLE);
-		schedule_timeout(jiffies & 0xf);
-		if(current->state != TASK_RUNNING)
-		  printk("ITW:  current->state isn't RUNNING after schedule!\n");
-		it++;
-	}
-}
-
-static void interrupt_test(void) 
-{
-	int i;
-
-	printk("interrupt_test: initing sv.\n");
-	sv_init(&int_test_sv, &int_test_spin, SV_MON_SPIN | SV_INTS);
-
-	for(i = 0; i < SV_INTERRUPT_TEST_WORKERS; i++) {
-		printk("interrupt_test: starting test thread %d.\n", i);
-		kernel_thread(interrupt_test_worker, 0, 0);
-	}
-	printk("interrupt_test: done with init part.\n");
-	int_test_ready = 1;
-}
-
-int sv_test(void) 
-{
-	spinlock_t s = SPIN_LOCK_UNLOCKED;
-
-	sv_init(&sv, &s, SV_MON_SPIN);
-	printk("sv_test: starting sv_test_1_w.\n");
-	kernel_thread(sv_test_1_w, &s, 0);
-	printk("sv_test: starting sv_test_1_s.\n");
-	kernel_thread(sv_test_1_s, &s, 0);
-
-	printk("sv_test: waiting for talkback.\n");
-	down(&talkback); down(&talkback);
-	printk("sv_test: talkback happened, sv_destroying.\n");
-	sv_destroy(&sv);
-
-	count = 0;
-
-	printk("sv_test: beginning big_test on sv.\n");
-
-	sv_init(&sv, &monitor, SV_MON_SEMA);
-	big_test(&sv);
-	sv_destroy(&sv);
-
-	printk("sv_test: beginning big_test on sv_filo.\n");
-	sv_init(&sv_filo, &monitor, SV_MON_SEMA | SV_ORDER_FILO);
-	big_test(&sv_filo);
-	sv_destroy(&sv_filo);
-
-	interrupt_test();
-
-	printk("sv_test: done.\n");
-	return 0;
-}
-
-__initcall(sv_test);
-
-#endif /* RUN_SV_TEST */
diff -Nru a/arch/ia64/sn/sn1/synergy.c b/arch/ia64/sn/sn1/synergy.c
--- a/arch/ia64/sn/sn1/synergy.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,429 +0,0 @@
-
-/*
- * SN1 Platform specific synergy Support
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
- */
-
-
-
-#include <linux/config.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/spinlock.h>
-#include <linux/proc_fs.h>
-
-#include <asm/ptrace.h>
-#include <linux/devfs_fs_kernel.h>
-#include <asm/smp.h>
-#include <asm/sn/sn_cpuid.h>
-#include <asm/sn/sn1/bedrock.h>
-#include <asm/sn/intr.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/synergy.h>
-
-int bit_pos_to_irq(int bit);
-void setclear_mask_b(int irq, int cpuid, int set);
-void setclear_mask_a(int irq, int cpuid, int set);
-void * kmalloc(size_t size, int flags);
-
-
-void
-synergy_intr_alloc(int bit, int cpuid) {
-	return;
-}
-
-int
-synergy_intr_connect(int bit, 
-		int cpuid)
-{
-	int irq;
-	unsigned is_b;
-
-	irq = bit_pos_to_irq(bit);
-
-	is_b = (cpuid_to_slice(cpuid)) & 1;
-	if (is_b) {
-		setclear_mask_b(irq,cpuid,1);
-		setclear_mask_a(irq,cpuid, 0);
-	} else {
-		setclear_mask_a(irq, cpuid, 1);
-		setclear_mask_b(irq, cpuid, 0);
-	}
-	return 0;
-}
-void
-setclear_mask_a(int irq, int cpuid, int set)
-{
-	int synergy;
-	int nasid;
-	int reg_num;
-	unsigned long mask;
-	unsigned long addr;
-	unsigned long reg;
-	unsigned long val;
-	int my_cnode, my_synergy;
-	int target_cnode, target_synergy;
-
-        /*
-         * Perform some idiot checks ..
-         */
-        if ( (irq < 0) || (irq > 255) ||
-                (cpuid < 0) || (cpuid > 512) ) {
-                printk("clear_mask_a: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
-		return;
-	}
-
-	target_cnode = cpuid_to_cnodeid(cpuid);
-	target_synergy = cpuid_to_synergy(cpuid);
-	my_cnode = cpuid_to_cnodeid(smp_processor_id());
-	my_synergy = cpuid_to_synergy(smp_processor_id());
-
-	reg_num = irq / 64;
-	mask = 1;
-	mask <<= (irq % 64);
-	switch (reg_num) {
-		case 0: 
-			reg = VEC_MASK0A;
-			addr = VEC_MASK0A_ADDR;
-			break;
-		case 1: 
-			reg = VEC_MASK1A;
-			addr = VEC_MASK1A_ADDR;
-			break;
-		case 2: 
-			reg = VEC_MASK2A;
-			addr = VEC_MASK2A_ADDR;
-			break;
-		case 3: 
-			reg = VEC_MASK3A;
-			addr = VEC_MASK3A_ADDR;
-			break;
-		default:
-			reg = addr = 0;
-			break;
-	}
-	if (my_cnode == target_cnode && my_synergy == target_synergy) {
-		// local synergy
-		val = READ_LOCAL_SYNERGY_REG(addr);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		WRITE_LOCAL_SYNERGY_REG(addr, val);
-		val = READ_LOCAL_SYNERGY_REG(addr);
-	} else { /* remote synergy */
-		synergy = cpuid_to_synergy(cpuid);
-		nasid = cpuid_to_nasid(cpuid);
-		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
-	}
-}
-
-void
-setclear_mask_b(int irq, int cpuid, int set)
-{
-	int synergy;
-	int nasid;
-	int reg_num;
-	unsigned long mask;
-	unsigned long addr;
-	unsigned long reg;
-	unsigned long val;
-	int my_cnode, my_synergy;
-	int target_cnode, target_synergy;
-
-	/*
-	 * Perform some idiot checks ..
-	 */
-	if ( (irq < 0) || (irq > 255) ||
-		(cpuid < 0) || (cpuid > 512) ) {
-		printk("clear_mask_b: Invalid parameter irq %d cpuid %d\n", irq, cpuid);
-		return;
-	}
-
-	target_cnode = cpuid_to_cnodeid(cpuid);
-	target_synergy = cpuid_to_synergy(cpuid);
-	my_cnode = cpuid_to_cnodeid(smp_processor_id());
-	my_synergy = cpuid_to_synergy(smp_processor_id());
-
-	reg_num = irq / 64;
-	mask = 1;
-	mask <<= (irq % 64);
-	switch (reg_num) {
-		case 0: 
-			reg = VEC_MASK0B;
-			addr = VEC_MASK0B_ADDR;
-			break;
-		case 1: 
-			reg = VEC_MASK1B;
-			addr = VEC_MASK1B_ADDR;
-			break;
-		case 2: 
-			reg = VEC_MASK2B;
-			addr = VEC_MASK2B_ADDR;
-			break;
-		case 3: 
-			reg = VEC_MASK3B;
-			addr = VEC_MASK3B_ADDR;
-			break;
-		default:
-			reg = addr = 0;
-			break;
-	}
-	if (my_cnode == target_cnode && my_synergy == target_synergy) {
-		// local synergy
-		val = READ_LOCAL_SYNERGY_REG(addr);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		WRITE_LOCAL_SYNERGY_REG(addr, val);
-		val = READ_LOCAL_SYNERGY_REG(addr);
-	} else { /* remote synergy */
-		synergy = cpuid_to_synergy(cpuid);
-		nasid = cpuid_to_nasid(cpuid);
-		val = REMOTE_SYNERGY_LOAD(nasid, synergy, reg);
-		if (set) {
-			val |= mask;
-		} else {
-			val &= ~mask;
-		}
-		REMOTE_SYNERGY_STORE(nasid, synergy, reg, val);
-	}
-}
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-
-/*
- * Synergy perf registers. Multiplexed via timer_interrupt
- */
-static struct proc_dir_entry *synergy_perf_proc = NULL;
-
-/*
- * read handler for /proc/synergy
- */
-static int
-synergy_perf_read_proc (char *page, char **start, off_t off,
-                                 int count, int *eof, void *data)
-{
-	cnodeid_t       cnode;
-	nodepda_t       *npdap;
-	synergy_perf_t	*p;
-	int		len = 0;
-
-	len += sprintf(page+len, "# cnode module slot event synergy-A synergy-B\n");
-
-	/* walk the event list for each node */
-	for (cnode=0; cnode < numnodes; cnode++) {
-		npdap = NODEPDA(cnode);
-		if (npdap->synergy_perf_enabled == 0) {
-			len += sprintf(page+len, "# DISABLED\n");
-			break;
-		}
-
-		spin_lock_irq(&npdap->synergy_perf_lock);
-		for (p = npdap->synergy_perf_first; p;) {
-			uint64_t cnt_a=0, cnt_b=0;
-
-			if (p->intervals > 0) {
-				cnt_a = p->counts[0] * npdap->synergy_active_intervals / p->intervals;
-				cnt_b = p->counts[1] * npdap->synergy_active_intervals / p->intervals;
-			}
-
-			len += sprintf(page+len, "%d %d %d %12lx %lu %lu\n",
-				(int)cnode, (int)npdap->module_id, (int)npdap->slotdesc,
-				p->modesel, cnt_a, cnt_b);
-
-			p = p->next;
-			if (p == npdap->synergy_perf_first)
-				break;
-		}
-		spin_unlock_irq(&npdap->synergy_perf_lock);
-	}
-
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return len;
-}
-
-static int
-synergy_perf_append(uint64_t modesel)
-{
-	int		cnode;
-	nodepda_t       *npdap;
-	synergy_perf_t	*p;
-	int		err = 0;
-
-	/* bit 45 is enable */
-	modesel |= (1UL << 45);
-
-	for (cnode=0; cnode < numnodes; cnode++) {
-		/* for each node, insert a new synergy_perf entry */
-		if ((npdap = NODEPDA(cnode)) == NULL) {
-			printk("synergy_perf_append: cnode=%d NODEPDA(cnode)==NULL, nodepda=%p\n", cnode, nodepda);
-			continue;
-		}
-
-		/* XX use kmem_alloc_node() when it is implemented */
-		p = (synergy_perf_t *)kmalloc(sizeof(synergy_perf_t), GFP_KERNEL);
-		if (p == NULL)
-			err = -ENOMEM;
-		else {
-			memset(p, 0, sizeof(synergy_perf_t));
-			p->modesel = modesel;
-			if (npdap->synergy_perf_data == NULL) {
-				/* circular list */
-				p->next = p;
-				npdap->synergy_perf_data = p;
-				npdap->synergy_perf_first = p;
-			}
-			else {
-				/*
-				 * Jumble up the insertion order so we get better sampling.
-				 * Once the list is complete, "first" stays the same so the
-				 * reporting order is consistent.
-				 */
-				p->next = npdap->synergy_perf_first->next;
-				npdap->synergy_perf_first->next = p;
-				npdap->synergy_perf_first = p->next;
-			}
-		}
-	}
-
-	return err;
-}
-
-static int
-synergy_perf_write_proc (struct file *file, const char *buffer,
-                                unsigned long count, void *data)
-{
-	int		cnode;
-	nodepda_t       *npdap;
-	uint64_t	modesel;
-	char		cmd[64];
-	extern long	atoi(char *);
-    
-	if (count == sizeof(uint64_t)) {
-	    if (copy_from_user(&modesel, buffer, sizeof(uint64_t)))
-		    return -EFAULT;
-	    synergy_perf_append(modesel);
-	}
-	else {
-	    if (copy_from_user(cmd, buffer, count < sizeof(cmd) ? count : sizeof(cmd)))
-		    return -EFAULT;
-	    if (strncmp(cmd, "enable", 6) == 0) {
-		/* enable counting */
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_enabled = 1;
-		}
-		printk("NOTICE: synergy perf counting enabled\n");
-	    }
-	    else
-	    if (strncmp(cmd, "disable", 7) == 0) {
-		/* disable counting */
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_enabled = 0;
-		}
-		printk("NOTICE: synergy perf counting disabled\n");
-	    }
-	    else
-	    if (strncmp(cmd, "frequency", 9) == 0) {
-		/* set the update frequency (timer-interrupts per update) */
-		int freq;
-
-		if (count < 12)
-			return -EINVAL;
-		freq = atoi(cmd + 10);
-		if (freq <= 0 || freq > 100)
-			return -EINVAL;
-		for (cnode=0; cnode < numnodes; cnode++) {
-			npdap = NODEPDA(cnode);
-			npdap->synergy_perf_freq = (uint64_t)freq;
-		}
-		printk("NOTICE: synergy perf freq set to %d\n", freq);
-	    }
-	    else
-		return -EINVAL;
-	}
-	
-	return count;
-}
-
-void
-synergy_perf_update(int cpu)
-{
-	nasid_t		nasid;
-	cnodeid_t       cnode = cpuid_to_cnodeid(cpu);
-	struct nodepda_s *npdap;
-	extern struct nodepda_s *nodepda;
-
-	if (nodepda == NULL || (npdap=NODEPDA(cnode)) == NULL || npdap->synergy_perf_enabled == 0 ||
-		npdap->synergy_perf_data == NULL) {
-		/* I/O not initialized, or not enabled, or no events to monitor */
-		return;
-	}
-
-	if (npdap->synergy_inactive_intervals++ % npdap->synergy_perf_freq != 0) {
-		/* don't multiplex on every timer interrupt */
-		return;
-	}
-
-	/*
-	 * Read registers for last interval and increment counters.
-	 * Hold the per-node synergy_perf_lock so concurrent readers get
-	 * consistent values.
-	 */
-	spin_lock_irq(&npdap->synergy_perf_lock);
-
-	nasid = cpuid_to_nasid(cpu);
-	npdap->synergy_active_intervals++;
-	npdap->synergy_perf_data->intervals++;
-
-	npdap->synergy_perf_data->counts[0] += 0xffffffffffUL &
-		REMOTE_SYNERGY_LOAD(nasid, 0, PERF_CNTR0_A);
-
-	npdap->synergy_perf_data->counts[1] += 0xffffffffffUL &
-		REMOTE_SYNERGY_LOAD(nasid, 1, PERF_CNTR0_B);
-
-	/* skip to next in circular list */
-	npdap->synergy_perf_data = npdap->synergy_perf_data->next;
-
-	spin_unlock_irq(&npdap->synergy_perf_lock);
-
-	/* set the counter 0 selection modes for both A and B */
-	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTL0_A, npdap->synergy_perf_data->modesel);
-	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTL0_B, npdap->synergy_perf_data->modesel);
-
-	/* and reset the counter registers to zero */
-	REMOTE_SYNERGY_STORE(nasid, 0, PERF_CNTR0_A, 0UL);
-	REMOTE_SYNERGY_STORE(nasid, 1, PERF_CNTR0_B, 0UL);
-}
-
-void
-synergy_perf_init(void)
-{
-        if ((synergy_perf_proc = create_proc_entry("synergy", 0644, NULL)) != NULL) {
-                synergy_perf_proc->read_proc = synergy_perf_read_proc;
-                synergy_perf_proc->write_proc = synergy_perf_write_proc;
-                printk("markgw: synergy_perf_init()\n");
-        }
-}
-
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
diff -Nru a/arch/ia64/sn/tools/make_textsym b/arch/ia64/sn/tools/make_textsym
--- a/arch/ia64/sn/tools/make_textsym	Fri Mar 15 17:51:01 2002
+++ b/arch/ia64/sn/tools/make_textsym	Fri Mar 15 17:51:01 2002
@@ -1,5 +1,14 @@
 #!/bin/sh
+#
 # Build a textsym file for use in the Arium ITP probe.
+#
+#
+# This file is subject to the terms and conditions of the GNU General Public
+# License.  See the file "COPYING" in the main directory of this archive
+# for more details.
+#
+# Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+#
 
 help() {
 cat <<END
@@ -30,107 +39,131 @@
 
 LINUX=${1:-vmlinux}
 TEXTSYM=${2:-${LINUX}.sym}
+TMPSYM=${2:-${LINUX}.sym.tmp}
+trap "/bin/rm -f $TMPSYM" 0
 
 [ -f $VMLINUX ] || help
 
+$OBJDUMP -t $LINUX | sort > $TMPSYM
+SN1=`egrep "dig_setup|Synergy_da_indr" $TMPSYM|wc -l`
+
+# Dataprefix and textprefix correspond to the VGLOBAL_BASE and VPERNODE_BASE.
+# Eventually, these values should be:
+#	dataprefix	ffffffff
+#	textprefix	fffffffe
+# but right now they're still changing, so make them dynamic.
+dataprefix=`awk ' / \.data	/ { print substr($1, 0, 8) ; exit ; }' $TMPSYM`
+textprefix=`awk ' / \.text	/ { print substr($1, 0, 8) ; exit ; }' $TMPSYM`
 
 # pipe everything thru sort
 echo "TEXTSYM V1.0"
 (cat <<END 
-GLOBAL | e000000000500000 | CODE | VEC_VHPT_Translation_0000
-GLOBAL | e000000000500400 | CODE | VEC_ITLB_0400
-GLOBAL | e000000000500800 | CODE | VEC_DTLB_0800
-GLOBAL | e000000000500c00 | CODE | VEC_Alt_ITLB_0c00
-GLOBAL | e000000000501000 | CODE | VEC_Alt_DTLB_1000
-GLOBAL | e000000000501400 | CODE | VEC_Data_nested_TLB_1400
-GLOBAL | e000000000501800 | CODE | VEC_Instruction_Key_Miss_1800
-GLOBAL | e000000000501c00 | CODE | VEC_Data_Key_Miss_1c00
-GLOBAL | e000000000502000 | CODE | VEC_Dirty-bit_2000
-GLOBAL | e000000000502400 | CODE | VEC_Instruction_Access-bit_2400
-GLOBAL | e000000000502800 | CODE | VEC_Data_Access-bit_2800
-GLOBAL | e000000000502c00 | CODE | VEC_Break_instruction_2c00
-GLOBAL | e000000000503000 | CODE | VEC_External_Interrupt_3000
-GLOBAL | e000000000503400 | CODE | VEC_Reserved_3400
-GLOBAL | e000000000503800 | CODE | VEC_Reserved_3800
-GLOBAL | e000000000503c00 | CODE | VEC_Reserved_3c00
-GLOBAL | e000000000504000 | CODE | VEC_Reserved_4000
-GLOBAL | e000000000504400 | CODE | VEC_Reserved_4400
-GLOBAL | e000000000504800 | CODE | VEC_Reserved_4800
-GLOBAL | e000000000504c00 | CODE | VEC_Reserved_4c00
-GLOBAL | e000000000505000 | CODE | VEC_Page_Not_Present_5000
-GLOBAL | e000000000505100 | CODE | VEC_Key_Permission_5100
-GLOBAL | e000000000505200 | CODE | VEC_Instruction_Access_Rights_5200
-GLOBAL | e000000000505300 | CODE | VEC_Data_Access_Rights_5300
-GLOBAL | e000000000505400 | CODE | VEC_General_Exception_5400
-GLOBAL | e000000000505500 | CODE | VEC_Disabled_FP-Register_5500
-GLOBAL | e000000000505600 | CODE | VEC_Nat_Consumption_5600
-GLOBAL | e000000000505700 | CODE | VEC_Speculation_5700
-GLOBAL | e000000000505800 | CODE | VEC_Reserved_5800
-GLOBAL | e000000000505900 | CODE | VEC_Debug_5900
-GLOBAL | e000000000505a00 | CODE | VEC_Unaligned_Reference_5a00
-GLOBAL | e000000000505b00 | CODE | VEC_Unsupported_Data_Reference_5b00
-GLOBAL | e000000000505c00 | CODE | VEC_Floating-Point_Fault_5c00
-GLOBAL | e000000000505d00 | CODE | VEC_Floating_Point_Trap_5d00
-GLOBAL | e000000000505e00 | CODE | VEC_Lower_Privilege_Tranfer_Trap_5e00
-GLOBAL | e000000000505f00 | CODE | VEC_Taken_Branch_Trap_5f00
-GLOBAL | e000000000506000 | CODE | VEC_Single_Step_Trap_6000
-GLOBAL | e000000000506100 | CODE | VEC_Reserved_6100
-GLOBAL | e000000000506200 | CODE | VEC_Reserved_6200
-GLOBAL | e000000000506300 | CODE | VEC_Reserved_6300
-GLOBAL | e000000000506400 | CODE | VEC_Reserved_6400
-GLOBAL | e000000000506500 | CODE | VEC_Reserved_6500
-GLOBAL | e000000000506600 | CODE | VEC_Reserved_6600
-GLOBAL | e000000000506700 | CODE | VEC_Reserved_6700
-GLOBAL | e000000000506800 | CODE | VEC_Reserved_6800
-GLOBAL | e000000000506900 | CODE | VEC_IA-32_Exeception_6900
-GLOBAL | e000000000506a00 | CODE | VEC_IA-32_Intercept_6a00
-GLOBAL | e000000000506b00 | CODE | VEC_IA-32_Interrupt_6b00
-GLOBAL | e000000000506c00 | CODE | VEC_Reserved_6c00
-GLOBAL | e000000000506d00 | CODE | VEC_Reserved_6d00
-GLOBAL | e000000000506e00 | CODE | VEC_Reserved_6e00
-GLOBAL | e000000000506f00 | CODE | VEC_Reserved_6f00
-GLOBAL | e000000000507000 | CODE | VEC_Reserved_7000
-GLOBAL | e000000000507100 | CODE | VEC_Reserved_7100
-GLOBAL | e000000000507200 | CODE | VEC_Reserved_7200
-GLOBAL | e000000000507300 | CODE | VEC_Reserved_7300
-GLOBAL | e000000000507400 | CODE | VEC_Reserved_7400
-GLOBAL | e000000000507500 | CODE | VEC_Reserved_7500
-GLOBAL | e000000000507600 | CODE | VEC_Reserved_7600
-GLOBAL | e000000000507700 | CODE | VEC_Reserved_7700
-GLOBAL | e000000000507800 | CODE | VEC_Reserved_7800
-GLOBAL | e000000000507900 | CODE | VEC_Reserved_7900
-GLOBAL | e000000000507a00 | CODE | VEC_Reserved_7a00
-GLOBAL | e000000000507b00 | CODE | VEC_Reserved_7b00
-GLOBAL | e000000000507c00 | CODE | VEC_Reserved_7c00
-GLOBAL | e000000000507d00 | CODE | VEC_Reserved_7d00
-GLOBAL | e000000000507e00 | CODE | VEC_Reserved_7e00
-GLOBAL | e000000000507f00 | CODE | VEC_Reserved_7f00
+GLOBAL | ${textprefix}00400000 | CODE | VEC_VHPT_Translation_0000
+GLOBAL | ${textprefix}00400400 | CODE | VEC_ITLB_0400
+GLOBAL | ${textprefix}00400800 | CODE | VEC_DTLB_0800
+GLOBAL | ${textprefix}00400c00 | CODE | VEC_Alt_ITLB_0c00
+GLOBAL | ${textprefix}00401000 | CODE | VEC_Alt_DTLB_1000
+GLOBAL | ${textprefix}00401400 | CODE | VEC_Data_nested_TLB_1400
+GLOBAL | ${textprefix}00401800 | CODE | VEC_Instruction_Key_Miss_1800
+GLOBAL | ${textprefix}00401c00 | CODE | VEC_Data_Key_Miss_1c00
+GLOBAL | ${textprefix}00402000 | CODE | VEC_Dirty-bit_2000
+GLOBAL | ${textprefix}00402400 | CODE | VEC_Instruction_Access-bit_2400
+GLOBAL | ${textprefix}00402800 | CODE | VEC_Data_Access-bit_2800
+GLOBAL | ${textprefix}00402c00 | CODE | VEC_Break_instruction_2c00
+GLOBAL | ${textprefix}00403000 | CODE | VEC_External_Interrupt_3000
+GLOBAL | ${textprefix}00403400 | CODE | VEC_Reserved_3400
+GLOBAL | ${textprefix}00403800 | CODE | VEC_Reserved_3800
+GLOBAL | ${textprefix}00403c00 | CODE | VEC_Reserved_3c00
+GLOBAL | ${textprefix}00404000 | CODE | VEC_Reserved_4000
+GLOBAL | ${textprefix}00404400 | CODE | VEC_Reserved_4400
+GLOBAL | ${textprefix}00404800 | CODE | VEC_Reserved_4800
+GLOBAL | ${textprefix}00404c00 | CODE | VEC_Reserved_4c00
+GLOBAL | ${textprefix}00405000 | CODE | VEC_Page_Not_Present_5000
+GLOBAL | ${textprefix}00405100 | CODE | VEC_Key_Permission_5100
+GLOBAL | ${textprefix}00405200 | CODE | VEC_Instruction_Access_Rights_5200
+GLOBAL | ${textprefix}00405300 | CODE | VEC_Data_Access_Rights_5300
+GLOBAL | ${textprefix}00405400 | CODE | VEC_General_Exception_5400
+GLOBAL | ${textprefix}00405500 | CODE | VEC_Disabled_FP-Register_5500
+GLOBAL | ${textprefix}00405600 | CODE | VEC_Nat_Consumption_5600
+GLOBAL | ${textprefix}00405700 | CODE | VEC_Speculation_5700
+GLOBAL | ${textprefix}00405800 | CODE | VEC_Reserved_5800
+GLOBAL | ${textprefix}00405900 | CODE | VEC_Debug_5900
+GLOBAL | ${textprefix}00405a00 | CODE | VEC_Unaligned_Reference_5a00
+GLOBAL | ${textprefix}00405b00 | CODE | VEC_Unsupported_Data_Reference_5b00
+GLOBAL | ${textprefix}00405c00 | CODE | VEC_Floating-Point_Fault_5c00
+GLOBAL | ${textprefix}00405d00 | CODE | VEC_Floating_Point_Trap_5d00
+GLOBAL | ${textprefix}00405e00 | CODE | VEC_Lower_Privilege_Tranfer_Trap_5e00
+GLOBAL | ${textprefix}00405f00 | CODE | VEC_Taken_Branch_Trap_5f00
+GLOBAL | ${textprefix}00406000 | CODE | VEC_Single_Step_Trap_6000
+GLOBAL | ${textprefix}00406100 | CODE | VEC_Reserved_6100
+GLOBAL | ${textprefix}00406200 | CODE | VEC_Reserved_6200
+GLOBAL | ${textprefix}00406300 | CODE | VEC_Reserved_6300
+GLOBAL | ${textprefix}00406400 | CODE | VEC_Reserved_6400
+GLOBAL | ${textprefix}00406500 | CODE | VEC_Reserved_6500
+GLOBAL | ${textprefix}00406600 | CODE | VEC_Reserved_6600
+GLOBAL | ${textprefix}00406700 | CODE | VEC_Reserved_6700
+GLOBAL | ${textprefix}00406800 | CODE | VEC_Reserved_6800
+GLOBAL | ${textprefix}00406900 | CODE | VEC_IA-32_Exeception_6900
+GLOBAL | ${textprefix}00406a00 | CODE | VEC_IA-32_Intercept_6a00
+GLOBAL | ${textprefix}00406b00 | CODE | VEC_IA-32_Interrupt_6b00
+GLOBAL | ${textprefix}00406c00 | CODE | VEC_Reserved_6c00
+GLOBAL | ${textprefix}00406d00 | CODE | VEC_Reserved_6d00
+GLOBAL | ${textprefix}00406e00 | CODE | VEC_Reserved_6e00
+GLOBAL | ${textprefix}00406f00 | CODE | VEC_Reserved_6f00
+GLOBAL | ${textprefix}00407000 | CODE | VEC_Reserved_7000
+GLOBAL | ${textprefix}00407100 | CODE | VEC_Reserved_7100
+GLOBAL | ${textprefix}00407200 | CODE | VEC_Reserved_7200
+GLOBAL | ${textprefix}00407300 | CODE | VEC_Reserved_7300
+GLOBAL | ${textprefix}00407400 | CODE | VEC_Reserved_7400
+GLOBAL | ${textprefix}00407500 | CODE | VEC_Reserved_7500
+GLOBAL | ${textprefix}00407600 | CODE | VEC_Reserved_7600
+GLOBAL | ${textprefix}00407700 | CODE | VEC_Reserved_7700
+GLOBAL | ${textprefix}00407800 | CODE | VEC_Reserved_7800
+GLOBAL | ${textprefix}00407900 | CODE | VEC_Reserved_7900
+GLOBAL | ${textprefix}00407a00 | CODE | VEC_Reserved_7a00
+GLOBAL | ${textprefix}00407b00 | CODE | VEC_Reserved_7b00
+GLOBAL | ${textprefix}00407c00 | CODE | VEC_Reserved_7c00
+GLOBAL | ${textprefix}00407d00 | CODE | VEC_Reserved_7d00
+GLOBAL | ${textprefix}00407e00 | CODE | VEC_Reserved_7e00
+GLOBAL | ${textprefix}00407f00 | CODE | VEC_Reserved_7f00
 END
 
-$OBJDUMP -t $LINUX | sort | awk '
-/empty_zero_page/ {start=1}
-/e0000000/ {
+
+awk '
+/__start_gate_section/ {start=1}
+/^'${dataprefix}\|${textprefix}'/ {
 	if ($4 == ".kdb")
 		next
 	if (start && substr($NF,1,1) != "0") {
 		type = substr($0,26,5)
 		if (type == ".text")
 			printf "GLOBAL | %s | CODE | %s\n", $1, $NF
-		else
-			printf "GLOBAL | %s | DATA | %s | %d\n", $1, $NF, $(NF-1)
+		else {
+			n = 0
+			s = $(NF-1)
+			while (length(s) > 0) {
+				n = n*16 + substr(s,1,1)
+				s = substr(s,2)
+			}
+			printf "GLOBAL | %s | DATA | %s | %d\n", $1, $NF, n
+		}
 	}
 	if($NF == "_end") 
 		exit
 
 }
-' ) | egrep -v " __device| __vendor" | awk '
+' $TMPSYM ) | egrep -v " __device| __vendor" | awk -v sn1="$SN1" '
 /GLOBAL/ {
 	print $0
-	print substr($0,1,9) substr($0,18,18) "Phy_" substr($0,36)
+	if (sn1 != 0) {
+		/* 32 bits of sn1 physical addrs, */
+		print substr($0,1,9) substr($0,18,18) "Phy_" substr($0,36)
+	} else {
+		/* 38 bits of sn2 physical addrs, need addr space bits */
+		print substr($0,1,9) "30" substr($0,18,18) "Phy_" substr($0,36)
+	}
 
 } ' | sort -k3
-
-
 
 N=`wc -l $TEXTSYM|awk '{print $1}'`
 echo "Generated TEXTSYM file" >&2
diff -Nru a/arch/ia64/tools/Makefile b/arch/ia64/tools/Makefile
--- a/arch/ia64/tools/Makefile	Fri Mar 15 17:51:00 2002
+++ b/arch/ia64/tools/Makefile	Fri Mar 15 17:51:00 2002
@@ -2,7 +2,7 @@
 
 TARGET	= $(TOPDIR)/include/asm-ia64/offsets.h
 
-all: 
+all:
 
 mrproper:
 
@@ -34,7 +34,8 @@
 comma	:= ,
 
 print_offsets: print_offsets.c FORCE_RECOMPILE
-	$(CC) $(CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) print_offsets.c -o $@
+	$(CC) $(CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) \
+		print_offsets.c -o $@
 
 FORCE_RECOMPILE:
 
@@ -44,7 +45,8 @@
 	$(AWK) -f print_offsets.awk $^ > $@
 
 print_offsets.s: print_offsets.c
-	$(CC) $(CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) -S print_offsets.c -o $@
+	$(CC) $(CFLAGS) -DKBUILD_BASENAME=$(subst $(comma),_,$(subst -,_,$(*F))) -S \
+		print_offsets.c -o $@
 
 endif
 
diff -Nru a/arch/ia64/tools/print_offsets.awk b/arch/ia64/tools/print_offsets.awk
--- a/arch/ia64/tools/print_offsets.awk	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/tools/print_offsets.awk	Fri Mar 15 17:51:03 2002
@@ -7,12 +7,6 @@
 	print " * This file was generated by arch/ia64/tools/print_offsets.awk."
 	print " *"
 	print " */"
-	#
-	# This is a cheesy hack.  Make sure that
-	# PT_PTRACED == 1<<PT_PTRACED_BIT.
-	#
-	print "#define PT_PTRACED_BIT		0"
-	print "#define PT_TRACESYS_BIT		1"
 }
 
 # look for .tab:
diff -Nru a/arch/ia64/tools/print_offsets.c b/arch/ia64/tools/print_offsets.c
--- a/arch/ia64/tools/print_offsets.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ia64/tools/print_offsets.c	Fri Mar 15 17:51:03 2002
@@ -1,8 +1,8 @@
 /*
  * Utility to generate asm-ia64/offsets.h.
  *
- * Copyright (C) 1999-2001 Hewlett-Packard Co
- * Copyright (C) 1999-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1999-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  *
  * Note that this file has dual use: when building the kernel
  * natively, the file is translated into a binary and executed.  When
@@ -44,6 +44,7 @@
 tab[] =
   {
     { "IA64_TASK_SIZE",			sizeof (struct task_struct) },
+    { "IA64_THREAD_INFO_SIZE",		sizeof (struct thread_info) },
     { "IA64_PT_REGS_SIZE",		sizeof (struct pt_regs) },
     { "IA64_SWITCH_STACK_SIZE",		sizeof (struct switch_stack) },
     { "IA64_SIGINFO_SIZE",		sizeof (struct siginfo) },
@@ -51,17 +52,7 @@
     { "SIGFRAME_SIZE",			sizeof (struct sigframe) },
     { "UNW_FRAME_INFO_SIZE",		sizeof (struct unw_frame_info) },
     { "", 0 },			/* spacer */
-#error    { "IA64_TASK_PTRACE_OFFSET",	offsetof (struct task_struct, ptrace) },
-#error    { "IA64_TASK_SIGPENDING_OFFSET",	offsetof (struct task_struct, sigpending) },
-#error    { "IA64_TASK_NEED_RESCHED_OFFSET",	offsetof (struct task_struct, need_resched) },
-    { "IA64_TASK_PROCESSOR_OFFSET",	offsetof (struct task_struct, processor) },
-    { "IA64_TASK_THREAD_OFFSET",	offsetof (struct task_struct, thread) },
     { "IA64_TASK_THREAD_KSP_OFFSET",	offsetof (struct task_struct, thread.ksp) },
-#ifdef CONFIG_PERFMON
-    { "IA64_TASK_PFM_MUST_BLOCK_OFFSET",offsetof(struct task_struct, thread.pfm_must_block) },
-#endif
-    { "IA64_TASK_PID_OFFSET",		offsetof (struct task_struct, pid) },
-    { "IA64_TASK_MM_OFFSET",		offsetof (struct task_struct, mm) },
     { "IA64_PT_REGS_CR_IPSR_OFFSET",	offsetof (struct pt_regs, cr_ipsr) },
     { "IA64_PT_REGS_CR_IIP_OFFSET",	offsetof (struct pt_regs, cr_iip) },
     { "IA64_PT_REGS_CR_IFS_OFFSET",	offsetof (struct pt_regs, cr_ifs) },
@@ -171,9 +162,6 @@
     { "IA64_SIGFRAME_SIGCONTEXT_OFFSET",	offsetof (struct sigframe, sc) },
     { "IA64_CLONE_VFORK",		CLONE_VFORK },
     { "IA64_CLONE_VM",			CLONE_VM },
-    { "IA64_CPU_IRQ_COUNT_OFFSET",	offsetof (struct cpuinfo_ia64, irq_stat.f.irq_count) },
-    { "IA64_CPU_BH_COUNT_OFFSET",	offsetof (struct cpuinfo_ia64, irq_stat.f.bh_count) },
-    { "IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET",offsetof (struct cpuinfo_ia64, phys_stacked_size_p8)},
 };
 
 static const char *tabs = "\t\t\t\t\t\t\t\t\t\t";
@@ -190,14 +178,6 @@
 
   printf ("/*\n * DO NOT MODIFY\n *\n * This file was generated by "
 	  "arch/ia64/tools/print_offsets.\n *\n */\n\n");
-
-  /* This is stretching things a bit, but entry.S needs the bit number
-     for PT_PTRACED and it can't include <linux/sched.h> so this seems
-     like a reasonably solution.  At least the code won't break in
-     subtle ways should PT_PTRACED ever change.  Ditto for
-     PT_TRACESYS_BIT. */
-  printf ("#define PT_PTRACED_BIT\t\t\t%u\n", ffs (PT_PTRACED) - 1);
-  printf ("#define PT_TRACESYS_BIT\t\t\t%u\n\n", ffs (PT_TRACESYS) - 1);
 
   for (i = 0; i < sizeof (tab) / sizeof (tab[0]); ++i)
     {
diff -Nru a/arch/ia64/vmlinux.lds.S b/arch/ia64/vmlinux.lds.S
--- a/arch/ia64/vmlinux.lds.S	Fri Mar 15 17:51:02 2002
+++ b/arch/ia64/vmlinux.lds.S	Fri Mar 15 17:51:02 2002
@@ -1,6 +1,7 @@
 #include <linux/config.h>
 
-#include <asm/page.h>
+#include <asm/cache.h>
+#include <asm/ptrace.h>
 #include <asm/system.h>
 
 OUTPUT_FORMAT("elf64-ia64-little")
@@ -13,6 +14,8 @@
 	*(.text.exit)
 	*(.data.exit)
 	*(.exitcall.exit)
+	*(.IA_64.unwind.text.exit)
+	*(.IA_64.unwind_info.text.exit)
 	}
 
   v = PAGE_OFFSET;	/* this symbol is here to make debugging easier... */
@@ -68,11 +71,6 @@
 	{ *(__ksymtab) }
   __stop___ksymtab = .;
 
-  __start___kallsyms = .;	/* All kernel symbols for debugging */
-  __kallsyms : AT(ADDR(__kallsyms) - PAGE_OFFSET)
-	{ *(__kallsyms) }
-  __stop___kallsyms = .;
-
   /* Unwind info & table: */
   . = ALIGN(8);
   .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - PAGE_OFFSET)
@@ -104,28 +102,25 @@
         { *(.setup.init) }
   __setup_end = .;
   __initcall_start = .;
-  .initcall.init : AT(ADDR(.initcall1.init) - PAGE_OFFSET)
+  .initcall.init : AT(ADDR(.initcall.init) - PAGE_OFFSET)
 	{
-		 *(.initcall1.init) 
-		 *(.initcall2.init) 
-		 *(.initcall3.init) 
-		 *(.initcall4.init) 
-		 *(.initcall5.init) 
-		 *(.initcall6.init) 
-		 *(.initcall7.init) 
+		*(.initcall1.init)
+		*(.initcall2.init)
+		*(.initcall3.init)
+		*(.initcall4.init)
+		*(.initcall5.init)
+		*(.initcall6.init)
+		*(.initcall7.init)
 	}
   __initcall_end = .;
   . = ALIGN(PAGE_SIZE);
   __init_end = .;
 
   /* The initial task and kernel stack */
-  init_task : AT(ADDR(init_task) - PAGE_OFFSET)
-	{ *(init_task) }
-
-  .data.page_aligned : AT(ADDR(.data.page_aligned) - PAGE_OFFSET)
-        { *(.data.idt) }
+  .data.init_task : AT(ADDR(.data.init_task) - PAGE_OFFSET)
+	{ *(.data.init_task) }
 
-  . = ALIGN(64);
+  . = ALIGN(SMP_CACHE_BYTES);
   .data.cacheline_aligned : AT(ADDR(.data.cacheline_aligned) - PAGE_OFFSET)
         { *(.data.cacheline_aligned) }
 
@@ -133,6 +128,17 @@
   .kstrtab : AT(ADDR(.kstrtab) - PAGE_OFFSET)
 	{ *(.kstrtab) }
 
+  /* Per-cpu data: */
+  . = ALIGN(PAGE_SIZE);
+  __phys_per_cpu_start = .;
+  .data.percpu PERCPU_ADDR : AT(__phys_per_cpu_start - PAGE_OFFSET)
+	{
+		__per_cpu_start = .;
+		*(.data.percpu)
+		__per_cpu_end = .;
+	}
+  . = __phys_per_cpu_start + 4096;	/* ensure percpu fits into smallest page size (4KB) */
+
   .data : AT(ADDR(.data) - PAGE_OFFSET)
 	{ *(.data) *(.gnu.linkonce.d*) CONSTRUCTORS }
 
@@ -149,7 +155,7 @@
 	{ *(.sbss) *(.scommon) }
   .bss : AT(ADDR(.bss) - PAGE_OFFSET)
 	{ *(.bss) *(COMMON) }
-  . = ALIGN(64 / 8);
+
   _end = .;
 
   /* Stabs debugging sections.  */
diff -Nru a/arch/mips/defconfig-ddb5476 b/arch/mips/defconfig-ddb5476
--- a/arch/mips/defconfig-ddb5476	Fri Mar 15 17:51:03 2002
+++ b/arch/mips/defconfig-ddb5476	Fri Mar 15 17:51:03 2002
@@ -224,7 +224,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 # CONFIG_IDEPCI_SHARE_IRQ is not set
 # CONFIG_BLK_DEV_IDEDMA_PCI is not set
-# CONFIG_BLK_DEV_ADMA is not set
 # CONFIG_BLK_DEV_OFFBOARD is not set
 # CONFIG_IDEDMA_PCI_AUTO is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
diff -Nru a/arch/mips/defconfig-it8172 b/arch/mips/defconfig-it8172
--- a/arch/mips/defconfig-it8172	Fri Mar 15 17:51:02 2002
+++ b/arch/mips/defconfig-it8172	Fri Mar 15 17:51:02 2002
@@ -289,7 +289,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
--- a/arch/mips/kernel/smp.c	Fri Mar 15 17:51:01 2002
+++ b/arch/mips/kernel/smp.c	Fri Mar 15 17:51:01 2002
@@ -123,7 +123,7 @@
 		/* Spawn a new process normally.  Grab a pointer to
 		   its task struct so we can mess with it */
 		do_fork(CLONE_VM|CLONE_PID, 0, &regs, 0);
-		p = init_task.prev_task;
+		p = prev_task(&init_task);
 
 		/* Schedule the first task manually */
 		p->processor = i;
@@ -152,7 +152,7 @@
 		 * Linux can schedule processes on this slave.
 		 */
 		kernel_thread(0, NULL, CLONE_PID);
-		p = init_task.prev_task;
+		p = prev_task(&init_task);
 		sprintf(p->comm, "%s%d", "Idle", i);
 		init_tasks[i] = p;
 		p->processor = i;
diff -Nru a/arch/mips64/kernel/ioctl32.c b/arch/mips64/kernel/ioctl32.c
--- a/arch/mips64/kernel/ioctl32.c	Fri Mar 15 17:51:03 2002
+++ b/arch/mips64/kernel/ioctl32.c	Fri Mar 15 17:51:03 2002
@@ -739,7 +739,6 @@
 	IOCTL32_HANDLER(HDIO_GET_DMA, hdio_ioctl_trans),
 	IOCTL32_HANDLER(HDIO_GET_NICE, hdio_ioctl_trans),
 	IOCTL32_DEFAULT(HDIO_GET_IDENTITY),
-	IOCTL32_DEFAULT(HDIO_DRIVE_RESET),
 	// HDIO_TRISTATE_HWIF				/* not implemented */
 	// HDIO_DRIVE_TASK				/* To do, need specs */
 	IOCTL32_DEFAULT(HDIO_DRIVE_CMD),
@@ -750,9 +749,7 @@
 	IOCTL32_DEFAULT(HDIO_SET_NOWERR),
 	IOCTL32_DEFAULT(HDIO_SET_DMA),
 	IOCTL32_DEFAULT(HDIO_SET_PIO_MODE),
-	IOCTL32_DEFAULT(HDIO_SCAN_HWIF),
 	IOCTL32_DEFAULT(HDIO_SET_NICE),
-	//HDIO_UNREGISTER_HWIF
 
 	IOCTL32_DEFAULT(BLKROSET),			/* fs.h ioctls  */
 	IOCTL32_DEFAULT(BLKROGET),
diff -Nru a/arch/mips64/sgi-ip27/ip27-init.c b/arch/mips64/sgi-ip27/ip27-init.c
--- a/arch/mips64/sgi-ip27/ip27-init.c	Fri Mar 15 17:51:04 2002
+++ b/arch/mips64/sgi-ip27/ip27-init.c	Fri Mar 15 17:51:04 2002
@@ -491,7 +491,7 @@
 			 * Linux can schedule processes on this slave.
 			 */
 			kernel_thread(0, NULL, CLONE_PID);
-			p = init_task.prev_task;
+			p = prev_task(&init_task);
 			sprintf(p->comm, "%s%d", "Idle", num_cpus);
 			init_tasks[num_cpus] = p;
 			alloc_cpupda(cpu, num_cpus);
diff -Nru a/arch/ppc/configs/common_defconfig b/arch/ppc/configs/common_defconfig
--- a/arch/ppc/configs/common_defconfig	Fri Mar 15 17:51:02 2002
+++ b/arch/ppc/configs/common_defconfig	Fri Mar 15 17:51:02 2002
@@ -252,7 +252,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/ppc/configs/k2_defconfig b/arch/ppc/configs/k2_defconfig
--- a/arch/ppc/configs/k2_defconfig	Fri Mar 15 17:51:01 2002
+++ b/arch/ppc/configs/k2_defconfig	Fri Mar 15 17:51:01 2002
@@ -235,7 +235,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 # CONFIG_IDEDMA_PCI_AUTO is not set
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/ppc/configs/menf1_defconfig b/arch/ppc/configs/menf1_defconfig
--- a/arch/ppc/configs/menf1_defconfig	Fri Mar 15 17:51:00 2002
+++ b/arch/ppc/configs/menf1_defconfig	Fri Mar 15 17:51:00 2002
@@ -239,7 +239,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 # CONFIG_IDEPCI_SHARE_IRQ is not set
 # CONFIG_BLK_DEV_IDEDMA_PCI is not set
-# CONFIG_BLK_DEV_ADMA is not set
 # CONFIG_BLK_DEV_OFFBOARD is not set
 # CONFIG_IDEDMA_PCI_AUTO is not set
 # CONFIG_BLK_DEV_IDEDMA is not set
diff -Nru a/arch/ppc/configs/pmac_defconfig b/arch/ppc/configs/pmac_defconfig
--- a/arch/ppc/configs/pmac_defconfig	Fri Mar 15 17:51:03 2002
+++ b/arch/ppc/configs/pmac_defconfig	Fri Mar 15 17:51:03 2002
@@ -242,7 +242,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/ppc/configs/pplus_defconfig b/arch/ppc/configs/pplus_defconfig
--- a/arch/ppc/configs/pplus_defconfig	Fri Mar 15 17:51:03 2002
+++ b/arch/ppc/configs/pplus_defconfig	Fri Mar 15 17:51:03 2002
@@ -246,7 +246,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 # CONFIG_IDEDMA_PCI_AUTO is not set
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/ppc/configs/sandpoint_defconfig b/arch/ppc/configs/sandpoint_defconfig
--- a/arch/ppc/configs/sandpoint_defconfig	Fri Mar 15 17:51:03 2002
+++ b/arch/ppc/configs/sandpoint_defconfig	Fri Mar 15 17:51:03 2002
@@ -209,7 +209,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 # CONFIG_IDEDMA_PCI_AUTO is not set
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/ppc/defconfig b/arch/ppc/defconfig
--- a/arch/ppc/defconfig	Fri Mar 15 17:51:02 2002
+++ b/arch/ppc/defconfig	Fri Mar 15 17:51:02 2002
@@ -252,7 +252,6 @@
 CONFIG_BLK_DEV_IDEPCI=y
 CONFIG_IDEPCI_SHARE_IRQ=y
 CONFIG_BLK_DEV_IDEDMA_PCI=y
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_OFFBOARD is not set
 CONFIG_IDEDMA_PCI_AUTO=y
 CONFIG_BLK_DEV_IDEDMA=y
diff -Nru a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S
--- a/arch/ppc/kernel/misc.S	Fri Mar 15 17:51:02 2002
+++ b/arch/ppc/kernel/misc.S	Fri Mar 15 17:51:02 2002
@@ -1289,6 +1289,7 @@
 	.long sys_removexattr
 	.long sys_lremovexattr
 	.long sys_fremovexattr	/* 220 */
+	.long sys_futex
 	.rept NR_syscalls-(.-sys_call_table)/4
 		.long sys_ni_syscall
 	.endr
diff -Nru a/arch/ppc/kernel/smp.c b/arch/ppc/kernel/smp.c
--- a/arch/ppc/kernel/smp.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ppc/kernel/smp.c	Fri Mar 15 17:51:03 2002
@@ -344,7 +344,7 @@
 		memset(&regs, 0, sizeof(struct pt_regs));
 		if (do_fork(CLONE_VM|CLONE_PID, 0, &regs, 0) < 0)
 			panic("failed fork for CPU %d", i);
-		p = init_task.prev_task;
+		p = prev_task(&init_task);
 		if (!p)
 			panic("No idle task for CPU %d", i);
 		init_idle(p, i);
diff -Nru a/arch/ppc64/kernel/ioctl32.c b/arch/ppc64/kernel/ioctl32.c
--- a/arch/ppc64/kernel/ioctl32.c	Fri Mar 15 17:51:04 2002
+++ b/arch/ppc64/kernel/ioctl32.c	Fri Mar 15 17:51:04 2002
@@ -3713,7 +3713,6 @@
 COMPATIBLE_IOCTL(HDIO_SET_MULTCOUNT),
 COMPATIBLE_IOCTL(HDIO_DRIVE_CMD),
 COMPATIBLE_IOCTL(HDIO_SET_PIO_MODE),
-COMPATIBLE_IOCTL(HDIO_SCAN_HWIF),
 COMPATIBLE_IOCTL(HDIO_SET_NICE),
 /* 0x02 -- Floppy ioctls */
 COMPATIBLE_IOCTL(FDMSGON),
diff -Nru a/arch/ppc64/kernel/smp.c b/arch/ppc64/kernel/smp.c
--- a/arch/ppc64/kernel/smp.c	Fri Mar 15 17:51:03 2002
+++ b/arch/ppc64/kernel/smp.c	Fri Mar 15 17:51:03 2002
@@ -669,7 +669,7 @@
 
 		if (do_fork(CLONE_VM|CLONE_PID, 0, &regs, 0) < 0)
 			panic("failed fork for CPU %d", i);
-		p = init_task.prev_task;
+		p = prev_task(&init_task);
 		if (!p)
 			panic("No idle task for CPU %d", i);
 
diff -Nru a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
--- a/arch/s390/kernel/smp.c	Fri Mar 15 17:51:01 2002
+++ b/arch/s390/kernel/smp.c	Fri Mar 15 17:51:01 2002
@@ -528,7 +528,7 @@
          * We remove it from the pidhash and the runqueue
          * once we got the process:
          */
-        idle = init_task.prev_task;
+        idle = prev_task(&init_task);
         if (!idle)
                 panic("No idle process for CPU %d",cpu);
         idle->processor = cpu;
diff -Nru a/arch/s390x/kernel/smp.c b/arch/s390x/kernel/smp.c
--- a/arch/s390x/kernel/smp.c	Fri Mar 15 17:51:03 2002
+++ b/arch/s390x/kernel/smp.c	Fri Mar 15 17:51:03 2002
@@ -507,7 +507,7 @@
          * We remove it from the pidhash and the runqueue
          * once we got the process:
          */
-        idle = init_task.prev_task;
+        idle = prev_task(&init_task);
         if (!idle)
                 panic("No idle process for CPU %d",cpu);
         idle->processor = cpu;
diff -Nru a/arch/sparc/kernel/sun4d_smp.c b/arch/sparc/kernel/sun4d_smp.c
--- a/arch/sparc/kernel/sun4d_smp.c	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc/kernel/sun4d_smp.c	Fri Mar 15 17:51:01 2002
@@ -220,7 +220,7 @@
 
 			cpucount++;
 
-			p = init_task.prev_task;
+			p = prev_task(&init_task);
 
 			p->cpu = i;
 
diff -Nru a/arch/sparc/kernel/sun4m_smp.c b/arch/sparc/kernel/sun4m_smp.c
--- a/arch/sparc/kernel/sun4m_smp.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc/kernel/sun4m_smp.c	Fri Mar 15 17:51:02 2002
@@ -193,7 +193,7 @@
 
 			cpucount++;
 
-			p = init_task.prev_task;
+			p = prev_task(&init_task);
 
 			p->cpu = i;
 
diff -Nru a/arch/sparc/kernel/systbls.S b/arch/sparc/kernel/systbls.S
--- a/arch/sparc/kernel/systbls.S	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc/kernel/systbls.S	Fri Mar 15 17:51:03 2002
@@ -46,7 +46,7 @@
 /*125*/	.long sys_nis_syscall, sys_setreuid16, sys_setregid16, sys_rename, sys_truncate
 /*130*/	.long sys_ftruncate, sys_flock, sys_lstat64, sys_nis_syscall, sys_nis_syscall
 /*135*/	.long sys_nis_syscall, sys_mkdir, sys_rmdir, sys_utimes, sys_stat64
-/*140*/	.long sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_gettid, sys_getrlimit
+/*140*/	.long sys_sendfile64, sys_nis_syscall, sys_futex, sys_gettid, sys_getrlimit
 /*145*/	.long sys_setrlimit, sys_pivot_root, sys_prctl, sys_pciconfig_read, sys_pciconfig_write
 /*150*/	.long sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64
 /*155*/	.long sys_fcntl64, sys_nis_syscall, sys_statfs, sys_fstatfs, sys_oldumount
diff -Nru a/arch/sparc/vmlinux.lds b/arch/sparc/vmlinux.lds
--- a/arch/sparc/vmlinux.lds	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc/vmlinux.lds	Fri Mar 15 17:51:01 2002
@@ -55,6 +55,10 @@
 	*(.initcall7.init)
   }
   __initcall_end = .;
+  . = ALIGN(32);
+  __per_cpu_start = .;
+  .data.percpu  : { *(.data.percpu) }
+  __per_cpu_end = .;
   . = ALIGN(4096);
   __init_end = .;
   . = ALIGN(32);
diff -Nru a/arch/sparc64/Makefile b/arch/sparc64/Makefile
--- a/arch/sparc64/Makefile	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/Makefile	Fri Mar 15 17:51:03 2002
@@ -48,6 +48,11 @@
   AFLAGS += -m64 -mcpu=ultrasparc $(CC_UNDECL)
 endif
 
+ifeq ($(CONFIG_MCOUNT),y)
+  CFLAGS := $(subst -fomit-frame-pointer,,$(CFLAGS))
+  CFLAGS := $(CFLAGS) -pg
+endif
+
 LINKFLAGS = -T arch/sparc64/vmlinux.lds
 
 HEAD := arch/sparc64/kernel/head.o arch/sparc64/kernel/init_task.o
diff -Nru a/arch/sparc64/config.in b/arch/sparc64/config.in
--- a/arch/sparc64/config.in	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/config.in	Fri Mar 15 17:51:02 2002
@@ -289,6 +289,10 @@
    bool '  Verbose BUG() reporting (adds 70K)' CONFIG_DEBUG_BUGVERBOSE
    bool '  D-cache flush debugging' CONFIG_DEBUG_DCFLUSH
 fi
+bool 'Stack Overflow Detection Support' CONFIG_STACK_DEBUG
+if [ "$CONFIG_STACK_DEBUG" = "y" ] ; then
+   define_bool CONFIG_MCOUNT y
+fi
 
 endmenu
 
diff -Nru a/arch/sparc64/defconfig b/arch/sparc64/defconfig
--- a/arch/sparc64/defconfig	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/defconfig	Fri Mar 15 17:51:02 2002
@@ -29,6 +29,7 @@
 CONFIG_VT=y
 CONFIG_VT_CONSOLE=y
 CONFIG_SMP=y
+# CONFIG_PREEMPT is not set
 CONFIG_SPARC64=y
 CONFIG_HOTPLUG=y
 CONFIG_HAVE_DEC_LOCK=y
@@ -156,7 +157,7 @@
 #
 # Block devices
 #
-CONFIG_BLK_DEV_FD=y
+# CONFIG_BLK_DEV_FD is not set
 CONFIG_BLK_DEV_LOOP=m
 CONFIG_BLK_DEV_NBD=m
 
@@ -275,7 +276,7 @@
 # CONFIG_BLK_DEV_IDESCSI is not set
 
 #
-# IDE chipset support/bugfixes
+# IDE chipset support
 #
 # CONFIG_BLK_DEV_CMD640 is not set
 # CONFIG_BLK_DEV_CMD640_ENHANCED is not set
@@ -289,9 +290,7 @@
 CONFIG_IDEDMA_ONLYDISK=y
 CONFIG_BLK_DEV_IDEDMA=y
 # CONFIG_IDEDMA_PCI_WIP is not set
-# CONFIG_BLK_DEV_IDEDMA_TIMEOUT is not set
 # CONFIG_IDEDMA_NEW_DRIVE_LISTINGS is not set
-CONFIG_BLK_DEV_ADMA=y
 # CONFIG_BLK_DEV_AEC62XX is not set
 # CONFIG_AEC62XX_TUNING is not set
 CONFIG_BLK_DEV_ALI15X3=y
@@ -473,14 +472,9 @@
 CONFIG_ADAPTEC_STARFIRE=m
 # CONFIG_APRICOT is not set
 # CONFIG_CS89x0 is not set
-CONFIG_DE2104X=m
-CONFIG_TULIP=m
-# CONFIG_TULIP_MWI is not set
-# CONFIG_TULIP_MMIO is not set
-CONFIG_DE4X5=m
 CONFIG_DGRS=m
-# CONFIG_DM9102 is not set
 CONFIG_EEPRO100=m
+CONFIG_E100=m
 # CONFIG_LNE390 is not set
 CONFIG_FEALNX=m
 CONFIG_NATSEMI=m
@@ -500,7 +494,6 @@
 # CONFIG_TLAN is not set
 CONFIG_VIA_RHINE=m
 # CONFIG_VIA_RHINE_MMIO is not set
-CONFIG_WINBOND_840=m
 # CONFIG_NET_POCKET is not set
 
 #
@@ -509,12 +502,13 @@
 CONFIG_ACENIC=m
 # CONFIG_ACENIC_OMIT_TIGON_I is not set
 CONFIG_DL2K=m
+CONFIG_E1000=m
 CONFIG_MYRI_SBUS=m
 CONFIG_NS83820=m
 CONFIG_HAMACHI=m
 CONFIG_YELLOWFIN=m
 CONFIG_SK98LIN=m
-# CONFIG_TIGON3 is not set
+CONFIG_TIGON3=m
 CONFIG_FDDI=y
 # CONFIG_DEFXX is not set
 CONFIG_SKFP=m
@@ -554,6 +548,18 @@
 # CONFIG_WAN is not set
 
 #
+# "Tulip" family network device support
+#
+CONFIG_NET_TULIP=y
+CONFIG_DE2104X=m
+CONFIG_TULIP=m
+# CONFIG_TULIP_MWI is not set
+# CONFIG_TULIP_MMIO is not set
+CONFIG_DE4X5=m
+CONFIG_WINBOND_840=m
+# CONFIG_DM9102 is not set
+
+#
 # Unix 98 PTY support
 #
 CONFIG_UNIX98_PTYS=y
@@ -644,6 +650,9 @@
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 # CONFIG_ZISOFS is not set
+CONFIG_JFS_FS=m
+# CONFIG_JFS_DEBUG is not set
+# CONFIG_JFS_STATISTICS is not set
 CONFIG_MINIX_FS=m
 # CONFIG_VXFS_FS is not set
 # CONFIG_NTFS_FS is not set
@@ -674,6 +683,7 @@
 # CONFIG_ROOT_NFS is not set
 CONFIG_NFSD=m
 CONFIG_NFSD_V3=y
+CONFIG_NFSD_TCP=y
 CONFIG_SUNRPC=y
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
@@ -743,27 +753,16 @@
 # Sound
 #
 CONFIG_SOUND=m
-CONFIG_SOUND_BT878=m
-# CONFIG_SOUND_CMPCI is not set
-# CONFIG_SOUND_EMU10K1 is not set
-# CONFIG_MIDI_EMU10K1 is not set
-# CONFIG_SOUND_FUSION is not set
-# CONFIG_SOUND_CS4281 is not set
-# CONFIG_SOUND_ES1370 is not set
-CONFIG_SOUND_ES1371=m
-# CONFIG_SOUND_ESSSOLO1 is not set
-# CONFIG_SOUND_MAESTRO is not set
-# CONFIG_SOUND_MAESTRO3 is not set
-# CONFIG_SOUND_ICH is not set
-# CONFIG_SOUND_RME96XX is not set
-# CONFIG_SOUND_SONICVIBES is not set
-CONFIG_SOUND_TRIDENT=m
-# CONFIG_SOUND_MSNDCLAS is not set
-# CONFIG_SOUND_MSNDPIN is not set
-# CONFIG_SOUND_VIA82CXXX is not set
-# CONFIG_MIDI_VIA82CXXX is not set
-# CONFIG_SOUND_OSS is not set
-# CONFIG_SOUND_TVMIXER is not set
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+
+#
+# Advanced Linux Sound Architecture
+#
+# CONFIG_SND is not set
 
 #
 # USB support
@@ -831,6 +830,7 @@
 CONFIG_USB_VICAM=m
 CONFIG_USB_DSBR=m
 CONFIG_USB_DABUSB=m
+CONFIG_USB_KONICAWC=m
 
 #
 # USB Network adaptors
diff -Nru a/arch/sparc64/kernel/central.c b/arch/sparc64/kernel/central.c
--- a/arch/sparc64/kernel/central.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/central.c	Fri Mar 15 17:51:03 2002
@@ -247,6 +247,55 @@
 	       (central->clkver ? upa_readb(central->clkver) : 0x00));
 }
 
+static void init_all_fhc_hw(void)
+{
+	struct linux_fhc *fhc;
+
+	for(fhc = fhc_list; fhc != NULL; fhc = fhc->next) {
+		u32 tmp;
+
+		/* Clear all of the interrupt mapping registers
+		 * just in case OBP left them in a foul state.
+		 */
+#define ZAP(ICLR, IMAP) \
+do {	u32 imap_tmp; \
+	upa_writel(0, (ICLR)); \
+	upa_readl(ICLR); \
+	imap_tmp = upa_readl(IMAP); \
+	imap_tmp &= ~(0x80000000); \
+	upa_writel(imap_tmp, (IMAP)); \
+	upa_readl(IMAP); \
+} while (0)
+
+		ZAP(fhc->fhc_regs.ffregs + FHC_FFREGS_ICLR,
+		    fhc->fhc_regs.ffregs + FHC_FFREGS_IMAP);
+		ZAP(fhc->fhc_regs.sregs + FHC_SREGS_ICLR,
+		    fhc->fhc_regs.sregs + FHC_SREGS_IMAP);
+		ZAP(fhc->fhc_regs.uregs + FHC_UREGS_ICLR,
+		    fhc->fhc_regs.uregs + FHC_UREGS_IMAP);
+		ZAP(fhc->fhc_regs.tregs + FHC_TREGS_ICLR,
+		    fhc->fhc_regs.tregs + FHC_TREGS_IMAP);
+
+#undef ZAP
+
+		/* Setup FHC control register. */
+		tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
+
+		/* All non-central boards have this bit set. */
+		if(! IS_CENTRAL_FHC(fhc))
+			tmp |= FHC_CONTROL_IXIST;
+
+		/* For all FHCs, clear the firmware synchronization
+		 * line and both low power mode enables.
+		 */
+		tmp &= ~(FHC_CONTROL_AOFF | FHC_CONTROL_BOFF | FHC_CONTROL_SLINE);
+
+		upa_writel(tmp, fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
+		upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
+	}
+
+}
+
 void central_probe(void)
 {
 	struct linux_prom_registers fpregs[6];
@@ -341,6 +390,8 @@
 	       ((err & FHC_ID_MANUF) >> 1));
 
 	probe_other_fhcs();
+
+	init_all_fhc_hw();
 }
 
 static __inline__ void fhc_ledblink(struct linux_fhc *fhc, int on)
@@ -398,55 +449,11 @@
 void firetruck_init(void)
 {
 	struct linux_central *central = central_bus;
-	struct linux_fhc *fhc;
 	u8 ctrl;
 
 	/* No central bus, nothing to do. */
 	if (central == NULL)
 		return;
-
-	for(fhc = fhc_list; fhc != NULL; fhc = fhc->next) {
-		u32 tmp;
-
-		/* Clear all of the interrupt mapping registers
-		 * just in case OBP left them in a foul state.
-		 */
-#define ZAP(ICLR, IMAP) \
-do {	u32 imap_tmp; \
-	upa_writel(0, (ICLR)); \
-	upa_readl(ICLR); \
-	imap_tmp = upa_readl(IMAP); \
-	imap_tmp &= ~(0x80000000); \
-	upa_writel(imap_tmp, (IMAP)); \
-	upa_readl(IMAP); \
-} while (0)
-
-		ZAP(fhc->fhc_regs.ffregs + FHC_FFREGS_ICLR,
-		    fhc->fhc_regs.ffregs + FHC_FFREGS_IMAP);
-		ZAP(fhc->fhc_regs.sregs + FHC_SREGS_ICLR,
-		    fhc->fhc_regs.sregs + FHC_SREGS_IMAP);
-		ZAP(fhc->fhc_regs.uregs + FHC_UREGS_ICLR,
-		    fhc->fhc_regs.uregs + FHC_UREGS_IMAP);
-		ZAP(fhc->fhc_regs.tregs + FHC_TREGS_ICLR,
-		    fhc->fhc_regs.tregs + FHC_TREGS_IMAP);
-
-#undef ZAP
-
-		/* Setup FHC control register. */
-		tmp = upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
-
-		/* All non-central boards have this bit set. */
-		if(! IS_CENTRAL_FHC(fhc))
-			tmp |= FHC_CONTROL_IXIST;
-
-		/* For all FHCs, clear the firmware synchronization
-		 * line and both low power mode enables.
-		 */
-		tmp &= ~(FHC_CONTROL_AOFF | FHC_CONTROL_BOFF | FHC_CONTROL_SLINE);
-
-		upa_writel(tmp, fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
-		upa_readl(fhc->fhc_regs.pregs + FHC_PREGS_CTRL);
-	}
 
 	/* OBP leaves it on, turn it off so clock board timer LED
 	 * is in sync with FHC ones.
diff -Nru a/arch/sparc64/kernel/ebus.c b/arch/sparc64/kernel/ebus.c
--- a/arch/sparc64/kernel/ebus.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/ebus.c	Fri Mar 15 17:51:02 2002
@@ -208,7 +208,8 @@
 	dev->num_addrs = len / sizeof(struct linux_prom_registers);
 
 	for (i = 0; i < dev->num_addrs; i++) {
-		if (dev->bus->is_rio == 0)
+		/* XXX Learn how to interpret ebus ranges... -DaveM */
+		if (regs[i].which_io >= 0x10)
 			n = (regs[i].which_io - 0x10) >> 2;
 		else
 			n = regs[i].which_io;
diff -Nru a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
--- a/arch/sparc64/kernel/entry.S	Fri Mar 15 17:51:00 2002
+++ b/arch/sparc64/kernel/entry.S	Fri Mar 15 17:51:00 2002
@@ -1436,7 +1436,6 @@
 		 * %o7 for us.  Check performance counter stuff too.
 		 */
 		andn		%o7, _TIF_NEWCHILD, %l0
-		mov		%g5, %o0	/* 'prev' */
 		call		schedule_tail
 		 stx		%l0, [%g6 + TI_FLAGS]
 		andcc		%l0, _TIF_PERFCTR, %g0
diff -Nru a/arch/sparc64/kernel/etrap.S b/arch/sparc64/kernel/etrap.S
--- a/arch/sparc64/kernel/etrap.S	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/etrap.S	Fri Mar 15 17:51:02 2002
@@ -96,15 +96,15 @@
 		stx	%i2, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I2]		! Store		Group
 		stx	%i3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I3]		! Store		Group
 		stx	%i4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I4]		! Store		Group
-		sethi	%uhi(PAGE_OFFSET), %g4					! IEU0
 		stx	%i5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I5]		! Store		Group
 
 		stx	%i6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I6]		! Store		Group
-		sllx	%g4, 32, %g4						! IEU0
 		stx	%i7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I7]		! Store		Group
 		wrpr	%g0, ETRAP_PSTATE2, %pstate				! Single	Group+4bubbles
+		mov	%l6, %g6						! IEU0
 		jmpl	%l2 + 0x4, %g0						! CTI		Group
-		 mov	%l6, %g6						! IEU0
+		 ldx	[%g6 + TI_TASK], %g4					! Load
+		nop
 		nop
 		nop
 
@@ -187,13 +187,13 @@
 		stx	%i3, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I3]		! Store		Group
 		stx	%i4, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I4]		! Store		Group
 
-		sethi	%uhi(PAGE_OFFSET), %g4					! IEU0
 		stx	%i5, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I5]		! Store		Group
 		stx	%i6, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I6]		! Store		Group
-		sllx	%g4, 32, %g4						! IEU0
 		mov	%l6, %g6						! IEU1
 		stx	%i7, [%sp + STACK_BIAS + REGWIN_SZ + PT_V9_I7]		! Store		Group
+		ldx	[%g6 + TI_TASK], %g4					! Load		Group
 		done
+		nop
 		nop
 
 #undef TASK_REGOFF
diff -Nru a/arch/sparc64/kernel/head.S b/arch/sparc64/kernel/head.S
--- a/arch/sparc64/kernel/head.S	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/head.S	Fri Mar 15 17:51:02 2002
@@ -419,9 +419,6 @@
 	stxa	%g0, [%g7] ASI_DMMU
 	membar	#Sync
 
-	sethi	%uhi(PAGE_OFFSET), %g4
-	sllx	%g4, 32, %g4
-
 	/* We are now safely (we hope) in Nucleus context (0), rewrite
 	 * the KERNBASE TTE's so they no longer have the global bit set.
 	 * Don't forget to setup TAG_ACCESS first 8-)
@@ -493,6 +490,7 @@
 tlb_fixup_done:
 	sethi	%hi(init_thread_union), %g6
 	or	%g6, %lo(init_thread_union), %g6
+	ldx	[%g6 + TI_TASK], %g4
 	mov	%sp, %l6
 	mov	%o4, %l7
 
diff -Nru a/arch/sparc64/kernel/ioctl32.c b/arch/sparc64/kernel/ioctl32.c
--- a/arch/sparc64/kernel/ioctl32.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/ioctl32.c	Fri Mar 15 17:51:02 2002
@@ -32,6 +32,7 @@
 #include <linux/ppp_defs.h>
 #include <linux/if_ppp.h>
 #include <linux/if_pppox.h>
+#include <linux/if_tun.h>
 #include <linux/mtio.h>
 #include <linux/cdrom.h>
 #include <linux/loop.h>
@@ -96,6 +97,7 @@
 #include <linux/usb.h>
 #include <linux/usbdevice_fs.h>
 #include <linux/nbd.h>
+#include <linux/random.h>
 
 /* Use this to get at 32-bit user passed pointers. 
    See sys_sparc32.c for description about these. */
@@ -3973,7 +3975,6 @@
 COMPATIBLE_IOCTL(HDIO_SET_MULTCOUNT)
 COMPATIBLE_IOCTL(HDIO_DRIVE_CMD)
 COMPATIBLE_IOCTL(HDIO_SET_PIO_MODE)
-COMPATIBLE_IOCTL(HDIO_SCAN_HWIF)
 COMPATIBLE_IOCTL(HDIO_SET_NICE)
 /* 0x02 -- Floppy ioctls */
 COMPATIBLE_IOCTL(FDMSGON)
@@ -4076,6 +4077,12 @@
 COMPATIBLE_IOCTL(SCSI_IOCTL_TAGGED_DISABLE)
 COMPATIBLE_IOCTL(SCSI_IOCTL_GET_BUS_NUMBER)
 COMPATIBLE_IOCTL(SCSI_IOCTL_SEND_COMMAND)
+/* Big T */
+COMPATIBLE_IOCTL(TUNSETNOCSUM);
+COMPATIBLE_IOCTL(TUNSETDEBUG);
+COMPATIBLE_IOCTL(TUNSETIFF);
+COMPATIBLE_IOCTL(TUNSETPERSIST);
+COMPATIBLE_IOCTL(TUNSETOWNER);
 /* Big V */
 COMPATIBLE_IOCTL(VT_SETMODE)
 COMPATIBLE_IOCTL(VT_GETMODE)
@@ -4189,6 +4196,8 @@
 COMPATIBLE_IOCTL(SIOCGMIIPHY)
 COMPATIBLE_IOCTL(SIOCGMIIREG)
 COMPATIBLE_IOCTL(SIOCSMIIREG)
+COMPATIBLE_IOCTL(SIOCGIFVLAN)
+COMPATIBLE_IOCTL(SIOCSIFVLAN)
 /* SG stuff */
 COMPATIBLE_IOCTL(SG_SET_TIMEOUT)
 COMPATIBLE_IOCTL(SG_GET_TIMEOUT)
@@ -4527,6 +4536,13 @@
 COMPATIBLE_IOCTL(WIOCSTART)
 COMPATIBLE_IOCTL(WIOCSTOP)
 COMPATIBLE_IOCTL(WIOCGSTAT)
+/* Big R */
+COMPATIBLE_IOCTL(RNDGETENTCNT)
+COMPATIBLE_IOCTL(RNDADDTOENTCNT)
+COMPATIBLE_IOCTL(RNDGETPOOL)
+COMPATIBLE_IOCTL(RNDADDENTROPY)
+COMPATIBLE_IOCTL(RNDZAPENTCNT)
+COMPATIBLE_IOCTL(RNDCLEARPOOL)
 /* Bluetooth ioctls */
 COMPATIBLE_IOCTL(HCIDEVUP)
 COMPATIBLE_IOCTL(HCIDEVDOWN)
diff -Nru a/arch/sparc64/kernel/pci.c b/arch/sparc64/kernel/pci.c
--- a/arch/sparc64/kernel/pci.c	Fri Mar 15 17:51:00 2002
+++ b/arch/sparc64/kernel/pci.c	Fri Mar 15 17:51:00 2002
@@ -418,7 +418,7 @@
 				  enum pci_mmap_state mmap_state)
 {
 	unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
-	unsigned long user32 = user_offset & 0xffffffffUL;
+	unsigned long user32 = user_offset & pci_memspace_mask;
 	unsigned long largest_base, this_base, addr32;
 	int i;
 
@@ -448,7 +448,7 @@
 
 		this_base = rp->start;
 
-		addr32 = (this_base & PAGE_MASK) & 0xffffffffUL;
+		addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
 
 		if (mmap_state == pci_mmap_io)
 			addr32 &= 0xffffff;
@@ -464,7 +464,7 @@
 	if (mmap_state == pci_mmap_io)
 		vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
 	else
-		vma->vm_pgoff = (((largest_base & ~0xffffffffUL) | user32) >> PAGE_SHIFT);
+		vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
 
 	return 0;
 }
@@ -546,6 +546,15 @@
 	}
 
 	return ret;
+}
+
+int pcibios_prep_mwi(struct pci_dev *dev)
+{
+	/* We set correct PCI_CACHE_LINE_SIZE register values for every
+	 * device probed on this platform.  So there is nothing to check
+	 * and this always succeeds.
+	 */
+	return 0;
 }
 
 #endif /* !(CONFIG_PCI) */
diff -Nru a/arch/sparc64/kernel/pci_common.c b/arch/sparc64/kernel/pci_common.c
--- a/arch/sparc64/kernel/pci_common.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/pci_common.c	Fri Mar 15 17:51:02 2002
@@ -583,21 +583,45 @@
 	/* If we are underneath a PCI bridge, use PROM register
 	 * property of the parent bridge which is closest to
 	 * the PBM.
+	 *
+	 * However if that parent bridge has interrupt map/mask
+	 * properties of it's own we use the PROM register property
+	 * of the next child device on the path to PDEV.
+	 *
+	 * In detail the two cases are (note that the 'X' below is the
+	 * 'next child on the path to PDEV' mentioned above):
+	 *
+	 * 1) PBM --> PCI bus lacking int{map,mask} --> X ... PDEV
+	 *
+	 *    Here we use regs of 'PCI bus' device.
+	 *
+	 * 2) PBM --> PCI bus with int{map,mask} --> X ... PDEV
+	 *
+	 *    Here we use regs of 'X'.  Note that X can be PDEV.
 	 */
 	if (pdev->bus->number != pbm->pci_first_busno) {
-		struct pcidev_cookie *bus_pcp;
-		struct pci_dev *pwalk;
-		int offset, plen;
-
-		pwalk = pdev->bus->self;
-		while (pwalk->bus &&
-		       pwalk->bus->number != pbm->pci_first_busno)
-			pwalk = pwalk->bus->self;
+		struct pcidev_cookie *bus_pcp, *regs_pcp;
+		struct pci_dev *bus_dev, *regs_dev;
+		int plen;
+
+		bus_dev = pdev->bus->self;
+		regs_dev = pdev;
+
+		while (bus_dev->bus &&
+		       bus_dev->bus->number != pbm->pci_first_busno) {
+			regs_dev = bus_dev;
+			bus_dev = bus_dev->bus->self;
+		}
+
+		regs_pcp = regs_dev->sysdata;
+		pregs = regs_pcp->prom_regs;
 
-		bus_pcp = pwalk->sysdata;
+		bus_pcp = bus_dev->sysdata;
 
 		/* But if the PCI bridge has it's own interrupt map
-		 * and mask properties, use that and the device regs.
+		 * and mask properties, use that and the regs of the
+		 * PCI entity at the next level down on the path to the
+		 * device.
 		 */
 		plen = prom_getproperty(bus_pcp->prom_node, "interrupt-map",
 					(char *) &bridge_local_intmap[0],
@@ -605,38 +629,21 @@
 		if (plen != -1) {
 			intmap = &bridge_local_intmap[0];
 			num_intmap = plen / sizeof(struct linux_prom_pci_intmap);
-			plen = prom_getproperty(bus_pcp->prom_node, "interrupt-map-mask",
+			plen = prom_getproperty(bus_pcp->prom_node,
+						"interrupt-map-mask",
 						(char *) &bridge_local_intmask,
 						sizeof(bridge_local_intmask));
 			if (plen == -1) {
-				prom_printf("pbm_intmap_match: Bridge has intmap but "
-					    "no intmask.\n");
-				prom_halt();
+				printk("pci_intmap_match: Warning! Bridge has intmap "
+				       "but no intmask.\n");
+				printk("pci_intmap_match: Trying to recover.\n");
+				return 0;
 			}
-			goto check_intmap;
-		}
-
-		pregs = bus_pcp->prom_regs;
-
-		offset = prom_getint(dev_pcp->prom_node,
-				     "fcode-rom-offset");
-
-		/* Did PROM know better and assign an interrupt other
-		 * than #INTA to the device? - We test here for presence of
-		 * FCODE on the card, in this case we assume PROM has set
-		 * correct 'interrupts' property, unless it is quadhme.
-		 */
-		if (offset == -1 ||
-		    !strcmp(dev_pcp->prom_name, "SUNW,qfe") ||
-		    !strcmp(dev_pcp->prom_name, "qfe")) {
-			/*
-			 * No, use low slot number bits of child as IRQ line.
-			 */
-			*interrupt = ((*interrupt - 1 + PCI_SLOT(pdev->devfn)) & 3) + 1;
+		} else {
+			pregs = bus_pcp->prom_regs;
 		}
 	}
 
-check_intmap:
 	hi   = pregs->phys_hi & intmask->phys_hi;
 	mid  = pregs->phys_mid & intmask->phys_mid;
 	lo   = pregs->phys_lo & intmask->phys_lo;
@@ -652,12 +659,22 @@
 		}
 	}
 
-	prom_printf("pbm_intmap_match: bus %02x, devfn %02x: ",
+	/* Print it both to OBP console and kernel one so that if bootup
+	 * hangs here the user has the information to report.
+	 */
+	prom_printf("pci_intmap_match: bus %02x, devfn %02x: ",
 		    pdev->bus->number, pdev->devfn);
 	prom_printf("IRQ [%08x.%08x.%08x.%08x] not found in interrupt-map\n",
 		    pregs->phys_hi, pregs->phys_mid, pregs->phys_lo, *interrupt);
 	prom_printf("Please email this information to davem@redhat.com\n");
-	prom_halt();
+
+	printk("pci_intmap_match: bus %02x, devfn %02x: ",
+	       pdev->bus->number, pdev->devfn);
+	printk("IRQ [%08x.%08x.%08x.%08x] not found in interrupt-map\n",
+	       pregs->phys_hi, pregs->phys_mid, pregs->phys_lo, *interrupt);
+	printk("Please email this information to davem@redhat.com\n");
+
+	return 0;
 }
 
 static void __init pdev_fixup_irq(struct pci_dev *pdev)
@@ -703,6 +720,20 @@
 		goto have_irq;
 	}
 
+	/* Firmware gets quad-hme interrupts property totally
+	 * wrong.  It is 4 EBUS+HME devices behind a Digital bridge.
+	 * For each of the 4 instances the EBUS has interrupt property
+	 * '1' and the HME has interrupt property '2'.  So we have to
+	 * fix this up.
+	 */
+	if (!strcmp(pcp->prom_name, "SUNW,qfe") ||
+	    !strcmp(pcp->prom_name, "qfe")) {
+		if (PCI_SLOT(pdev->devfn) & ~3)
+			BUG();
+
+		prom_irq = PCI_SLOT(pdev->devfn) + 1;
+	}
+
 	/* Can we find a matching entry in the interrupt-map? */
 	if (pci_intmap_match(pdev, &prom_irq)) {
 		pdev->irq = p->irq_build(pbm, pdev, (portid << 6) | prom_irq);
@@ -738,12 +769,19 @@
 		 * ranges. -DaveM
  		 */
 		if (pdev->bus->number == pbm->pci_first_busno) {
-			slot = (pdev->devfn >> 3) - pbm->pci_first_slot;
+			slot = PCI_SLOT(pdev->devfn) - pbm->pci_first_slot;
 		} else {
+			struct pci_dev *bus_dev;
+
 			/* Underneath a bridge, use slot number of parent
-			 * bridge.
+			 * bridge which is closest to the PBM.
 			 */
-			slot = (pdev->bus->self->devfn >> 3) - pbm->pci_first_slot;
+			bus_dev = pdev->bus->self;
+			while (bus_dev->bus &&
+			       bus_dev->bus->number != pbm->pci_first_busno)
+				bus_dev = bus_dev->bus->self;
+
+			slot = PCI_SLOT(bus_dev->devfn) - pbm->pci_first_slot;
 		}
 		slot = slot << 2;
 
diff -Nru a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c
--- a/arch/sparc64/kernel/pci_psycho.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/pci_psycho.c	Fri Mar 15 17:51:03 2002
@@ -326,15 +326,15 @@
 /*0x14*/0, 0, 0, 0,	/* PCI B slot 1  Int A, B, C, D */
 /*0x18*/0, 0, 0, 0,	/* PCI B slot 2  Int A, B, C, D */
 /*0x1c*/0, 0, 0, 0,	/* PCI B slot 3  Int A, B, C, D */
-/*0x20*/3,		/* SCSI				*/
+/*0x20*/4,		/* SCSI				*/
 /*0x21*/5,		/* Ethernet			*/
 /*0x22*/8,		/* Parallel Port		*/
 /*0x23*/13,		/* Audio Record			*/
 /*0x24*/14,		/* Audio Playback		*/
 /*0x25*/15,		/* PowerFail			*/
-/*0x26*/3,		/* second SCSI			*/
+/*0x26*/4,		/* second SCSI			*/
 /*0x27*/11,		/* Floppy			*/
-/*0x28*/2,		/* Spare Hardware		*/
+/*0x28*/4,		/* Spare Hardware		*/
 /*0x29*/9,		/* Keyboard			*/
 /*0x2a*/4,		/* Mouse			*/
 /*0x2b*/12,		/* Serial			*/
@@ -353,7 +353,7 @@
 
 	ret = psycho_pil_table[ino];
 	if (ret == 0 && pdev == NULL) {
-		ret = 2;
+		ret = 4;
 	} else if (ret == 0) {
 		switch ((pdev->class >> 16) & 0xff) {
 		case PCI_BASE_CLASS_STORAGE:
@@ -376,7 +376,7 @@
 			break;
 
 		default:
-			ret = 2;
+			ret = 4;
 			break;
 		};
 	}
diff -Nru a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c
--- a/arch/sparc64/kernel/pci_sabre.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/pci_sabre.c	Fri Mar 15 17:51:03 2002
@@ -564,15 +564,15 @@
 /*0x14*/0, 0, 0, 0,	/* PCI B slot 1  Int A, B, C, D */
 /*0x18*/0, 0, 0, 0,	/* PCI B slot 2  Int A, B, C, D */
 /*0x1c*/0, 0, 0, 0,	/* PCI B slot 3  Int A, B, C, D */
-/*0x20*/3,		/* SCSI				*/
+/*0x20*/4,		/* SCSI				*/
 /*0x21*/5,		/* Ethernet			*/
 /*0x22*/8,		/* Parallel Port		*/
 /*0x23*/13,		/* Audio Record			*/
 /*0x24*/14,		/* Audio Playback		*/
 /*0x25*/15,		/* PowerFail			*/
-/*0x26*/3,		/* second SCSI			*/
+/*0x26*/4,		/* second SCSI			*/
 /*0x27*/11,		/* Floppy			*/
-/*0x28*/2,		/* Spare Hardware		*/
+/*0x28*/4,		/* Spare Hardware		*/
 /*0x29*/9,		/* Keyboard			*/
 /*0x2a*/4,		/* Mouse			*/
 /*0x2b*/12,		/* Serial			*/
@@ -596,7 +596,7 @@
 
 	ret = sabre_pil_table[ino];
 	if (ret == 0 && pdev == NULL) {
-		ret = 2;
+		ret = 4;
 	} else if (ret == 0) {
 		switch ((pdev->class >> 16) & 0xff) {
 		case PCI_BASE_CLASS_STORAGE:
@@ -619,7 +619,7 @@
 			break;
 
 		default:
-			ret = 2;
+			ret = 4;
 			break;
 		};
 	}
diff -Nru a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c
--- a/arch/sparc64/kernel/pci_schizo.c	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/kernel/pci_schizo.c	Fri Mar 15 17:51:01 2002
@@ -291,8 +291,8 @@
 /*0x0c*/0, 0, 0, 0,	/* PCI slot 3  Int A, B, C, D	*/
 /*0x10*/0, 0, 0, 0,	/* PCI slot 4  Int A, B, C, D	*/
 /*0x14*/0, 0, 0, 0,	/* PCI slot 5  Int A, B, C, D	*/
-/*0x18*/3,		/* SCSI				*/
-/*0x19*/3,		/* second SCSI			*/
+/*0x18*/4,		/* SCSI				*/
+/*0x19*/4,		/* second SCSI			*/
 /*0x1a*/0,		/* UNKNOWN			*/
 /*0x1b*/0,		/* UNKNOWN			*/
 /*0x1c*/8,		/* Parallel			*/
@@ -302,7 +302,7 @@
 /*0x20*/13,		/* Audio Record			*/
 /*0x21*/14,		/* Audio Playback		*/
 /*0x22*/12,		/* Serial			*/
-/*0x23*/2,		/* EBUS I2C 			*/
+/*0x23*/4,		/* EBUS I2C 			*/
 /*0x24*/10,		/* RTC Clock			*/
 /*0x25*/11,		/* Floppy			*/
 /*0x26*/0,		/* UNKNOWN			*/
@@ -344,7 +344,7 @@
 
 	ret = schizo_pil_table[ino];
 	if (ret == 0 && pdev == NULL) {
-		ret = 2;
+		ret = 4;
 	} else if (ret == 0) {
 		switch ((pdev->class >> 16) & 0xff) {
 		case PCI_BASE_CLASS_STORAGE:
@@ -367,7 +367,7 @@
 			break;
 
 		default:
-			ret = 2;
+			ret = 4;
 			break;
 		};
 	}
@@ -1082,15 +1082,22 @@
 
 #define SCHIZO_PCIA_CTRL	(SCHIZO_PBM_A_REGS_OFF + 0x2000UL)
 #define SCHIZO_PCIB_CTRL	(SCHIZO_PBM_B_REGS_OFF + 0x2000UL)
-#define SCHIZO_PCICTRL_BUNUS	(1UL << 63UL)
+#define SCHIZO_PCICTRL_BUS_UNUS	(1UL << 63UL)
 #define SCHIZO_PCICTRL_ESLCK	(1UL << 51UL)
+#define SCHIZO_PCICTRL_ERRSLOT	(7UL << 48UL)
 #define SCHIZO_PCICTRL_TTO_ERR	(1UL << 38UL)
 #define SCHIZO_PCICTRL_RTRY_ERR	(1UL << 37UL)
 #define SCHIZO_PCICTRL_DTO_ERR	(1UL << 36UL)
 #define SCHIZO_PCICTRL_SBH_ERR	(1UL << 35UL)
 #define SCHIZO_PCICTRL_SERR	(1UL << 34UL)
+#define SCHIZO_PCICTRL_PCISPD	(1UL << 33UL)
+#define SCHIZO_PCICTRL_PTO	(3UL << 24UL)
+#define SCHIZO_PCICTRL_DTO_INT	(1UL << 19UL)
 #define SCHIZO_PCICTRL_SBH_INT	(1UL << 18UL)
 #define SCHIZO_PCICTRL_EEN	(1UL << 17UL)
+#define SCHIZO_PCICTRL_PARK	(1UL << 16UL)
+#define SCHIZO_PCICTRL_PCIRST	(1UL <<  8UL)
+#define SCHIZO_PCICTRL_ARB	(0x3fUL << 0UL)
 
 static void __init schizo_register_error_handlers(struct pci_controller_info *p)
 {
@@ -1167,7 +1174,7 @@
 	 * bits for each PBM.
 	 */
 	tmp = schizo_read(base + SCHIZO_PCIA_CTRL);
-	tmp |= (SCHIZO_PCICTRL_BUNUS |
+	tmp |= (SCHIZO_PCICTRL_BUS_UNUS |
 		SCHIZO_PCICTRL_ESLCK |
 		SCHIZO_PCICTRL_TTO_ERR |
 		SCHIZO_PCICTRL_RTRY_ERR |
@@ -1179,7 +1186,7 @@
 	schizo_write(base + SCHIZO_PCIA_CTRL, tmp);
 
 	tmp = schizo_read(base + SCHIZO_PCIB_CTRL);
-	tmp |= (SCHIZO_PCICTRL_BUNUS |
+	tmp |= (SCHIZO_PCICTRL_BUS_UNUS |
 		SCHIZO_PCICTRL_ESLCK |
 		SCHIZO_PCICTRL_TTO_ERR |
 		SCHIZO_PCICTRL_RTRY_ERR |
@@ -1742,6 +1749,22 @@
 	schizo_pbm_strbuf_init(p, pbm, is_pbm_a);
 }
 
+#define SCHIZO_PCIA_IRQ_RETRY	(SCHIZO_PBM_A_REGS_OFF + 0x1a00UL)
+#define SCHIZO_PCIB_IRQ_RETRY	(SCHIZO_PBM_B_REGS_OFF + 0x1a00UL)
+#define  SCHIZO_IRQ_RETRY_INF	 0xffUL
+
+#define SCHIZO_PCIA_DIAG	(SCHIZO_PBM_A_REGS_OFF + 0x2020UL)
+#define SCHIZO_PCIB_DIAG	(SCHIZO_PBM_B_REGS_OFF + 0x2020UL)
+#define  SCHIZO_PCIDIAG_D_BADECC	(1UL << 10UL) /* Disable BAD ECC errors */
+#define  SCHIZO_PCIDIAG_D_BYPASS	(1UL <<  9UL) /* Disable MMU bypass mode */
+#define  SCHIZO_PCIDIAG_D_TTO		(1UL <<  8UL) /* Disable TTO errors */
+#define  SCHIZO_PCIDIAG_D_RTRYARB	(1UL <<  7UL) /* Disable retry arbitration */
+#define  SCHIZO_PCIDIAG_D_RETRY		(1UL <<  6UL) /* Disable retry limit */
+#define  SCHIZO_PCIDIAG_D_INTSYNC	(1UL <<  5UL) /* Disable interrupt/DMA synch */
+#define  SCHIZO_PCIDIAG_I_DMA_PARITY	(1UL <<  3UL) /* Invert DMA parity */
+#define  SCHIZO_PCIDIAG_I_PIOD_PARITY	(1UL <<  2UL) /* Invert PIO data parity */
+#define  SCHIZO_PCIDIAG_I_PIOA_PARITY	(1UL <<  1U)L /* Invert PIO address parity */
+
 static void schizo_controller_hwinit(struct pci_controller_info *p)
 {
 	unsigned long pbm_a_base, pbm_b_base;
@@ -1751,17 +1774,37 @@
 	pbm_b_base = p->controller_regs + SCHIZO_PBM_B_REGS_OFF;
 
 	/* Set IRQ retry to infinity. */
-	schizo_write(pbm_a_base + 0x1a00UL, 0xff);
-	schizo_write(pbm_b_base + 0x1a00UL, 0xff);
+	schizo_write(p->controller_regs + SCHIZO_PCIA_IRQ_RETRY,
+		     SCHIZO_IRQ_RETRY_INF);
+	schizo_write(p->controller_regs + SCHIZO_PCIB_IRQ_RETRY,
+		     SCHIZO_IRQ_RETRY_INF);
+
+	/* Enable arbiter for all PCI slots.  Also, disable PCI interval
+	 * timer so that DTO (Discard TimeOuts) are not reported because
+	 * some Schizo revisions report them erroneously.
+	 */
 
-	/* Enable arbiter for all PCI slots. */
-	tmp = schizo_read(pbm_a_base + 0x2000UL);
-	tmp |= 0x3fUL;
-	schizo_write(pbm_a_base + 0x2000UL, tmp);
-
-	tmp = schizo_read(pbm_b_base + 0x2000UL);
-	tmp |= 0x3fUL;
-	schizo_write(pbm_b_base + 0x2000UL, tmp);
+	tmp = schizo_read(p->controller_regs + SCHIZO_PCIA_CTRL);
+	tmp |= SCHIZO_PCICTRL_ARB;
+	tmp &= ~SCHIZO_PCICTRL_PTO;
+	schizo_write(p->controller_regs + SCHIZO_PCIA_CTRL, tmp);
+
+	tmp = schizo_read(p->controller_regs + SCHIZO_PCIB_CTRL);
+	tmp |= SCHIZO_PCICTRL_ARB;
+	tmp &= ~SCHIZO_PCICTRL_PTO;
+	schizo_write(p->controller_regs + SCHIZO_PCIB_CTRL, tmp);
+
+	/* Disable TTO error reporting (won't happen anyway since we
+	 * disabled the PCI interval timer above) and retry arbitration
+	 * (can cause hangs in some Schizo revisions).
+	 */
+	tmp = schizo_read(p->controller_regs + SCHIZO_PCIA_DIAG);
+	tmp |= (SCHIZO_PCIDIAG_D_TTO | SCHIZO_PCIDIAG_D_RTRYARB);
+	schizo_write(p->controller_regs + SCHIZO_PCIA_DIAG, tmp);
+
+	tmp = schizo_read(p->controller_regs + SCHIZO_PCIB_DIAG);
+	tmp |= (SCHIZO_PCIDIAG_D_TTO | SCHIZO_PCIDIAG_D_RTRYARB);
+	schizo_write(p->controller_regs + SCHIZO_PCIB_DIAG, tmp);
 }
 
 void __init schizo_init(int node, char *model_name)
diff -Nru a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
--- a/arch/sparc64/kernel/process.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/process.c	Fri Mar 15 17:51:03 2002
@@ -106,9 +106,11 @@
 	int cpu = smp_processor_id();
 
 	if (local_irq_count(cpu) == 0 &&
-	    local_bh_count(cpu) == 0)
-		preempt_schedule();
-	current_thread_info()->preempt_count--;
+	    local_bh_count(cpu) == 0 &&
+	    test_thread_flag(TIF_NEED_RESCHED)) {
+		current->state = TASK_RUNNING;
+		schedule();
+	}
 }
 #endif
 
@@ -625,6 +627,7 @@
 		       (void *)(regs->u_regs[UREG_FP] + STACK_BIAS),
 		       sizeof(struct reg_window));
 		t->kregs->u_regs[UREG_G6] = (unsigned long) t;
+		t->kregs->u_regs[UREG_G4] = (unsigned long) t->task;
 	} else {
 		if (t->flags & _TIF_32BIT) {
 			sp &= 0x00000000ffffffffUL;
diff -Nru a/arch/sparc64/kernel/ptrace.c b/arch/sparc64/kernel/ptrace.c
--- a/arch/sparc64/kernel/ptrace.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/ptrace.c	Fri Mar 15 17:51:03 2002
@@ -627,9 +627,11 @@
 	if (!(current->ptrace & PT_PTRACED))
 		return;
 	current->exit_code = SIGTRAP;
+	preempt_disable();
 	current->state = TASK_STOPPED;
 	notify_parent(current, SIGCHLD);
 	schedule();
+	preempt_enable();
 	/*
 	 * this isn't the same as continuing with a signal, but it will do
 	 * for normal use.  strace only continues with a signal if the
diff -Nru a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
--- a/arch/sparc64/kernel/rtrap.S	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/rtrap.S	Fri Mar 15 17:51:03 2002
@@ -15,7 +15,6 @@
 #include <asm/visasm.h>
 #include <asm/processor.h>
 
-#define		PTREGS_OFF		(STACK_BIAS + REGWIN_SZ)
 #define		RTRAP_PSTATE		(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
 #define		RTRAP_PSTATE_IRQOFF	(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV)
 #define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)
@@ -150,7 +149,7 @@
 		 andn			%l1, %l4, %l1
 
 		.align			64
-		.globl			rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme
+		.globl			rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall
 rtrap_irq:
 #ifdef CONFIG_PREEMPT
 		ldsw			[%g6 + TI_PRE_COUNT], %l0
@@ -165,9 +164,11 @@
 		lduw			[%l2 + %l0], %l1	! softirq_pending
 		cmp			%l1, 0
 
+		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
 		bne,pn			%icc, __handle_softirq
 		 ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 __handle_softirq_continue:
+rtrap_xcall:
 		sethi			%hi(0xf << 20), %l4
 		andcc			%l1, TSTATE_PRIV, %l3
 		and			%l1, %l4, %l4
@@ -276,9 +277,9 @@
 		 add			%l5, 1, %l6
 		stw			%l6, [%g6 + TI_PRE_COUNT]
 		call			kpreempt_maybe
-		 wrpr			%g0, RTRAP_PSTATE, %pstate
-		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate		
-		stw			%l5, [%g6 + TI_PRE_COUNT]
+		 nop
+		ba,pt			%xcc, rtrap
+		 stw			%l5, [%g6 + TI_PRE_COUNT]
 #endif
 kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
 		brz,pt			%l5, rt_continue
@@ -331,5 +332,3 @@
 		wr			%g0, FPRS_DU, %fprs
 		ba,pt			%xcc, rt_continue
 		 stb			%l5, [%g6 + TI_FPDEPTH]
-
-#undef PTREGS_OFF
diff -Nru a/arch/sparc64/kernel/sbus.c b/arch/sparc64/kernel/sbus.c
--- a/arch/sparc64/kernel/sbus.c	Fri Mar 15 17:51:04 2002
+++ b/arch/sparc64/kernel/sbus.c	Fri Mar 15 17:51:04 2002
@@ -628,11 +628,11 @@
 
 /* SBUS SYSIO INO number to Sparc PIL level. */
 static unsigned char sysio_ino_to_pil[] = {
-	0, 2, 2, 7, 5, 7, 8, 9,		/* SBUS slot 0 */
-	0, 2, 2, 7, 5, 7, 8, 9,		/* SBUS slot 1 */
-	0, 2, 2, 7, 5, 7, 8, 9,		/* SBUS slot 2 */
-	0, 2, 2, 7, 5, 7, 8, 9,		/* SBUS slot 3 */
-	3, /* Onboard SCSI */
+	0, 4, 4, 7, 5, 7, 8, 9,		/* SBUS slot 0 */
+	0, 4, 4, 7, 5, 7, 8, 9,		/* SBUS slot 1 */
+	0, 4, 4, 7, 5, 7, 8, 9,		/* SBUS slot 2 */
+	0, 4, 4, 7, 5, 7, 8, 9,		/* SBUS slot 3 */
+	4, /* Onboard SCSI */
 	5, /* Onboard Ethernet */
 /*XXX*/	8, /* Onboard BPP */
 	0, /* Bogon */
diff -Nru a/arch/sparc64/kernel/setup.c b/arch/sparc64/kernel/setup.c
--- a/arch/sparc64/kernel/setup.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/setup.c	Fri Mar 15 17:51:02 2002
@@ -160,11 +160,16 @@
 			pmdp = pmd_offset(pgdp, va);
 			if (pmd_none(*pmdp))
 				goto done;
-			ptep = pte_offset(pmdp, va);
-			if (!pte_present(*ptep))
-				goto done;
-			tte = pte_val(*ptep);
-			res = PROM_TRUE;
+
+			/* Preemption implicitly disabled by virtue of
+			 * being called from inside OBP.
+			 */
+			ptep = pte_offset_map(pmdp, va);
+			if (pte_present(*ptep)) {
+				tte = pte_val(*ptep);
+				res = PROM_TRUE;
+			}
+			pte_unmap(ptep);
 			goto done;
 		}
 
@@ -210,11 +215,15 @@
 			pmdp = pmd_offset(pgdp, va);
 			if (pmd_none(*pmdp))
 				goto done;
-			ptep = pte_offset(pmdp, va);
-			if (!pte_present(*ptep))
-				goto done;
-			tte = pte_val(*ptep);
-			res = PROM_TRUE;
+
+			/* Preemption implicitly disabled by virtue of
+			 * being called from inside OBP.
+			 */
+			ptep = pte_offset_kernel(pmdp, va);
+			if (pte_present(*ptep)) {
+				tte = pte_val(*ptep);
+				res = PROM_TRUE;
+			}
 			goto done;
 		}
 
@@ -530,7 +539,7 @@
 	if (!root_flags)
 		root_mountflags &= ~MS_RDONLY;
 	ROOT_DEV = to_kdev_t(root_dev);
-#ifdef CONFIG_BLK_DEV_RAM
+#ifdef CONFIG_BLK_DEV_INITRD
 	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
 	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
 	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);	
diff -Nru a/arch/sparc64/kernel/signal.c b/arch/sparc64/kernel/signal.c
--- a/arch/sparc64/kernel/signal.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/signal.c	Fri Mar 15 17:51:03 2002
@@ -713,9 +713,11 @@
 
 		if ((current->ptrace & PT_PTRACED) && signr != SIGKILL) {
 			current->exit_code = signr;
+			preempt_disable();
 			current->state = TASK_STOPPED;
 			notify_parent(current, SIGCHLD);
 			schedule();
+			preempt_enable();
 			if (!(signr = current->exit_code))
 				continue;
 			current->exit_code = 0;
@@ -766,16 +768,20 @@
 				if (is_orphaned_pgrp(current->pgrp))
 					continue;
 
-			case SIGSTOP:
-				if (current->ptrace & PT_PTRACED)
-					continue;
-				current->state = TASK_STOPPED;
+			case SIGSTOP: {
+				struct signal_struct *sig;
+
 				current->exit_code = signr;
-				if (!(current->p_pptr->sig->action[SIGCHLD-1].sa.sa_flags &
+				sig = current->p_pptr->sig;
+				preempt_disable();
+				current->state = TASK_STOPPED;
+				if (sig && !(sig->action[SIGCHLD-1].sa.sa_flags &
 				      SA_NOCLDSTOP))
 					notify_parent(current, SIGCHLD);
 				schedule();
+				preempt_enable();
 				continue;
+			}
 
 			case SIGQUIT: case SIGILL: case SIGTRAP:
 			case SIGABRT: case SIGFPE: case SIGSEGV:
diff -Nru a/arch/sparc64/kernel/signal32.c b/arch/sparc64/kernel/signal32.c
--- a/arch/sparc64/kernel/signal32.c	Fri Mar 15 17:51:00 2002
+++ b/arch/sparc64/kernel/signal32.c	Fri Mar 15 17:51:00 2002
@@ -776,7 +776,7 @@
 		unsigned long address = ((unsigned long)&(sf->insns[0]));
 		pgd_t *pgdp = pgd_offset(current->mm, address);
 		pmd_t *pmdp = pmd_offset(pgdp, address);
-		pte_t *ptep = pte_offset(pmdp, address);
+		pte_t *ptep;
 
 		regs->u_regs[UREG_I7] = (unsigned long) (&(sf->insns[0]) - 2);
 	
@@ -785,6 +785,8 @@
 		if (err)
 			goto sigsegv;
 
+		preempt_disable();
+		ptep = pte_offset_map(pmdp, address);
 		if (pte_present(*ptep)) {
 			unsigned long page = (unsigned long) page_address(pte_page(*ptep));
 
@@ -794,6 +796,8 @@
 			: : "r" (page), "r" (address & (PAGE_SIZE - 1))
 			: "memory");
 		}
+		pte_unmap(ptep);
+		preempt_enable();
 	}
 	return;
 
@@ -1225,7 +1229,7 @@
 		unsigned long address = ((unsigned long)&(sf->insns[0]));
 		pgd_t *pgdp = pgd_offset(current->mm, address);
 		pmd_t *pmdp = pmd_offset(pgdp, address);
-		pte_t *ptep = pte_offset(pmdp, address);
+		pte_t *ptep;
 
 		regs->u_regs[UREG_I7] = (unsigned long) (&(sf->insns[0]) - 2);
 	
@@ -1237,6 +1241,8 @@
 		if (err)
 			goto sigsegv;
 
+		preempt_disable();
+		ptep = pte_offset_map(pmdp, address);
 		if (pte_present(*ptep)) {
 			unsigned long page = (unsigned long) page_address(pte_page(*ptep));
 
@@ -1246,6 +1252,8 @@
 			: : "r" (page), "r" (address & (PAGE_SIZE - 1))
 			: "memory");
 		}
+		pte_unmap(ptep);
+		preempt_enable();
 	}
 	return;
 
@@ -1379,9 +1387,11 @@
 
 		if ((current->ptrace & PT_PTRACED) && signr != SIGKILL) {
 			current->exit_code = signr;
+			preempt_disable();
 			current->state = TASK_STOPPED;
 			notify_parent(current, SIGCHLD);
 			schedule();
+			preempt_enable();
 			if (!(signr = current->exit_code))
 				continue;
 			current->exit_code = 0;
@@ -1432,17 +1442,20 @@
 				if (is_orphaned_pgrp(current->pgrp))
 					continue;
 
-			case SIGSTOP:
-				if (current->ptrace & PT_PTRACED)
-					continue;
-				current->state = TASK_STOPPED;
+			case SIGSTOP: {
+				struct signal_struct *sig;
+
 				current->exit_code = signr;
-				if (!(current->p_pptr->sig->action[SIGCHLD-1].sa.sa_flags &
+				sig = current->p_pptr->sig;
+				preempt_disable();
+				current->state = TASK_STOPPED;
+				if (sig && !(sig->action[SIGCHLD-1].sa.sa_flags &
 				      SA_NOCLDSTOP))
 					notify_parent(current, SIGCHLD);
 				schedule();
+				preempt_enable();
 				continue;
-
+			}
 			case SIGQUIT: case SIGILL: case SIGTRAP:
 			case SIGABRT: case SIGFPE: case SIGSEGV:
 			case SIGBUS: case SIGSYS: case SIGXCPU: case SIGXFSZ:
diff -Nru a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
--- a/arch/sparc64/kernel/smp.c	Fri Mar 15 17:51:00 2002
+++ b/arch/sparc64/kernel/smp.c	Fri Mar 15 17:51:00 2002
@@ -270,7 +270,7 @@
 			kernel_thread(NULL, NULL, CLONE_PID);
 			cpucount++;
 
-			p = init_task.prev_task;
+			p = prev_task(&init_task);
 
 			init_idle(p, i);
 
@@ -594,11 +594,12 @@
 	return 0;
 }
 
-void smp_call_function_client(void)
+void smp_call_function_client(int irq, struct pt_regs *regs)
 {
 	void (*func) (void *info) = call_data->func;
 	void *info = call_data->info;
 
+	clear_softint(1 << irq);
 	if (call_data->wait) {
 		/* let initiator proceed only after completion */
 		func(info);
@@ -722,6 +723,12 @@
 	}
 }
 
+void smp_receive_signal_client(int irq, struct pt_regs *regs)
+{
+	/* Just return, rtrap takes care of the rest. */
+	clear_softint(1 << irq);
+}
+
 void smp_report_regs(void)
 {
 	smp_cross_call(&xcall_report_regs, 0, 0, 0);
@@ -885,48 +892,6 @@
 	}
 }
 
-/* Process migration IPIs. */
-
-extern unsigned long xcall_migrate_task;
-
-static spinlock_t migration_lock = SPIN_LOCK_UNLOCKED;
-static task_t *new_task;
-
-void smp_migrate_task(int cpu, task_t *p)
-{
-	unsigned long mask = 1UL << cpu;
-
-	if (cpu == smp_processor_id())
-		return;
-
-	if (smp_processors_ready && (cpu_present_map & mask) != 0) {
-		u64 data0 = (((u64)&xcall_migrate_task) & 0xffffffff);
-
-		_raw_spin_lock(&migration_lock);
-		new_task = p;
-
-		if (tlb_type == spitfire)
-			spitfire_xcall_deliver(data0, 0, 0, mask);
-		else
-			cheetah_xcall_deliver(data0, 0, 0, mask);
-	}
-}
-
-/* Called at PIL level 1. */
-asmlinkage void smp_task_migration_interrupt(int irq, struct pt_regs *regs)
-{
-	task_t *p;
-
-	if (irq != PIL_MIGRATE)
-		BUG();
-
-	clear_softint(1 << irq);
-
-	p = new_task;
-	_raw_spin_unlock(&migration_lock);
-	sched_task_migrated(p);
-}
-
 /* CPU capture. */
 /* #define CAPTURE_DEBUG */
 extern unsigned long xcall_capture;
@@ -982,10 +947,14 @@
 extern void prom_world(int);
 extern void save_alternate_globals(unsigned long *);
 extern void restore_alternate_globals(unsigned long *);
-void smp_penguin_jailcell(void)
+void smp_penguin_jailcell(int irq, struct pt_regs *regs)
 {
 	unsigned long global_save[24];
 
+	clear_softint(1 << irq);
+
+	preempt_disable();
+
 	__asm__ __volatile__("flushw");
 	save_alternate_globals(global_save);
 	prom_world(1);
@@ -996,6 +965,8 @@
 	restore_alternate_globals(global_save);
 	atomic_dec(&smp_capture_registry);
 	prom_world(0);
+
+	preempt_enable();
 }
 
 extern unsigned long xcall_promstop;
diff -Nru a/arch/sparc64/kernel/sparc64_ksyms.c b/arch/sparc64/kernel/sparc64_ksyms.c
--- a/arch/sparc64/kernel/sparc64_ksyms.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/sparc64_ksyms.c	Fri Mar 15 17:51:02 2002
@@ -139,6 +139,11 @@
 EXPORT_SYMBOL(__global_save_flags);
 EXPORT_SYMBOL(__global_restore_flags);
 
+#if defined(CONFIG_MCOUNT)
+extern void mcount(void);
+EXPORT_SYMBOL(mcount);
+#endif
+
 /* Per-CPU information table */
 EXPORT_SYMBOL(cpu_data);
 
@@ -249,7 +254,7 @@
 /* Should really be in linux/kernel/ksyms.c */
 EXPORT_SYMBOL(dump_thread);
 EXPORT_SYMBOL(dump_fpu);
-EXPORT_SYMBOL(pte_alloc_one);
+EXPORT_SYMBOL(pte_alloc_one_kernel);
 #ifndef CONFIG_SMP
 EXPORT_SYMBOL(pgt_quicklists);
 #endif
diff -Nru a/arch/sparc64/kernel/sys_sparc32.c b/arch/sparc64/kernel/sys_sparc32.c
--- a/arch/sparc64/kernel/sys_sparc32.c	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/kernel/sys_sparc32.c	Fri Mar 15 17:51:01 2002
@@ -50,6 +50,7 @@
 #include <linux/icmpv6.h>
 #include <linux/sysctl.h>
 #include <linux/binfmts.h>
+#include <linux/dnotify.h>
 
 #include <asm/types.h>
 #include <asm/ipc.h>
@@ -1067,16 +1068,20 @@
 	/* First get the "struct iovec" from user memory and
 	 * verify all the pointers
 	 */
+	retval = 0;
 	if (!count)
-		return 0;
+		goto out_nofree;
+	retval = -EFAULT;
 	if (verify_area(VERIFY_READ, vector, sizeof(struct iovec32)*count))
-		return -EFAULT;
+		goto out_nofree;
+	retval = -EINVAL;
 	if (count > UIO_MAXIOV)
-		return -EINVAL;
+		goto out_nofree;
 	if (count > UIO_FASTIOV) {
+		retval = -ENOMEM;
 		iov = kmalloc(count*sizeof(struct iovec), GFP_KERNEL);
 		if (!iov)
-			return -ENOMEM;
+			goto out_nofree;
 	}
 
 	tot_len = 0;
@@ -1136,6 +1141,11 @@
 out:
 	if (iov != iovstack)
 		kfree(iov);
+out_nofree:
+	/* VERIFY_WRITE actually means a read, as we write to user space */
+	if ((retval + (type == VERIFY_WRITE)) > 0)
+		dnotify_parent(file->f_dentry,
+			(type == VERIFY_WRITE) ? DN_MODIFY : DN_ACCESS);
 
 	return retval;
 }
@@ -3950,6 +3960,27 @@
 	set_fs(old_fs);
 	
 	if (offset && put_user(of, offset))
+		return -EFAULT;
+		
+	return ret;
+}
+
+extern asmlinkage ssize_t sys_sendfile64(int out_fd, int in_fd, loff_t *offset, size_t count);
+
+asmlinkage int sys32_sendfile64(int out_fd, int in_fd, __kernel_loff_t32 *offset, s32 count)
+{
+	mm_segment_t old_fs = get_fs();
+	int ret;
+	loff_t lof;
+	
+	if (offset && get_user(lof, offset))
+		return -EFAULT;
+		
+	set_fs(KERNEL_DS);
+	ret = sys_sendfile64(out_fd, in_fd, offset ? &lof : NULL, count);
+	set_fs(old_fs);
+	
+	if (offset && put_user(lof, offset))
 		return -EFAULT;
 		
 	return ret;
diff -Nru a/arch/sparc64/kernel/systbls.S b/arch/sparc64/kernel/systbls.S
--- a/arch/sparc64/kernel/systbls.S	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/systbls.S	Fri Mar 15 17:51:03 2002
@@ -47,7 +47,7 @@
 	.word sys_nis_syscall, sys32_setreuid16, sys32_setregid16, sys_rename, sys_truncate
 /*130*/	.word sys_ftruncate, sys_flock, sys_lstat64, sys_nis_syscall, sys_nis_syscall
 	.word sys_nis_syscall, sys_mkdir, sys_rmdir, sys32_utimes, sys_stat64
-/*140*/	.word sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_gettid, sys32_getrlimit
+/*140*/	.word sys32_sendfile64, sys_nis_syscall, sys_futex, sys_gettid, sys32_getrlimit
 	.word sys32_setrlimit, sys_pivot_root, sys32_prctl, sys32_pciconfig_read, sys32_pciconfig_write
 /*150*/	.word sys_nis_syscall, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64
 	.word sys32_fcntl64, sys_nis_syscall, sys32_statfs, sys32_fstatfs, sys_oldumount
@@ -106,7 +106,7 @@
 	.word sys_recvfrom, sys_setreuid, sys_setregid, sys_rename, sys_truncate
 /*130*/	.word sys_ftruncate, sys_flock, sys_nis_syscall, sys_sendto, sys_shutdown
 	.word sys_socketpair, sys_mkdir, sys_rmdir, sys_utimes, sys_nis_syscall
-/*140*/	.word sys_nis_syscall, sys_getpeername, sys_nis_syscall, sys_gettid, sys_getrlimit
+/*140*/	.word sys_sendfile64, sys_getpeername, sys_futex, sys_gettid, sys_getrlimit
 	.word sys_setrlimit, sys_pivot_root, sys_prctl, sys_pciconfig_read, sys_pciconfig_write
 /*150*/	.word sys_getsockname, sys_nis_syscall, sys_nis_syscall, sys_poll, sys_getdents64
 	.word sys_nis_syscall, sys_nis_syscall, sys_statfs, sys_fstatfs, sys_oldumount
diff -Nru a/arch/sparc64/kernel/time.c b/arch/sparc64/kernel/time.c
--- a/arch/sparc64/kernel/time.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/time.c	Fri Mar 15 17:51:03 2002
@@ -405,6 +405,7 @@
 	char model[128];
 	int node, busnd = -1, err;
 	unsigned long flags;
+	struct linux_central *cbus;
 #ifdef CONFIG_PCI
 	struct linux_ebus *ebus = NULL;
 	struct isa_bridge *isa_br = NULL;
@@ -431,21 +432,30 @@
 
 	__save_and_cli(flags);
 
-	if(central_bus != NULL) {
+	cbus = central_bus;
+	if (cbus != NULL)
 		busnd = central_bus->child->prom_node;
-	}
+
+	/* Check FHC Central then EBUSs then ISA bridges then SBUSs.
+	 * That way we handle the presence of multiple properly.
+	 *
+	 * As a special case, machines with Central must provide the
+	 * timer chip there.
+	 */
 #ifdef CONFIG_PCI
-	else if (ebus_chain != NULL) {
+	if (ebus_chain != NULL) {
 		ebus = ebus_chain;
-		busnd = ebus->prom_node;
-	} else if (isa_chain != NULL) {
+		if (busnd == -1)
+			busnd = ebus->prom_node;
+	}
+	if (isa_chain != NULL) {
 		isa_br = isa_chain;
-		busnd = isa_br->prom_node;
+		if (busnd == -1)
+			busnd = isa_br->prom_node;
 	}
 #endif
-	else if (sbus_root != NULL) {
+	if (sbus_root != NULL && busnd == -1)
 		busnd = sbus_root->prom_node;
-	}
 
 	if (busnd == -1) {
 		prom_printf("clock_probe: problem, cannot find bus to search.\n");
@@ -464,7 +474,12 @@
 		    strcmp(model, "mk48t59") &&
 		    strcmp(model, "m5819") &&
 		    strcmp(model, "ds1287")) {
-		   	if (node)
+			if (cbus != NULL) {
+				prom_printf("clock_probe: Central bus lacks timer chip.\n");
+				prom_halt();
+			}
+
+		   	if (node != 0)
 				node = prom_getsibling(node);
 #ifdef CONFIG_PCI
 			while ((node == 0) && ebus != NULL) {
@@ -496,12 +511,12 @@
 			prom_halt();
 		}
 
-		if(central_bus) {
+		if (cbus != NULL) {
 			apply_fhc_ranges(central_bus->child, clk_reg, 1);
 			apply_central_ranges(central_bus, clk_reg, 1);
 		}
 #ifdef CONFIG_PCI
-		else if (ebus_chain != NULL) {
+		else if (ebus != NULL) {
 			struct linux_ebus_device *edev;
 
 			for_each_ebusdev(edev, ebus)
@@ -523,7 +538,8 @@
 				mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
 			}
 			break;
-		} else if (isa_chain != NULL) {
+		}
+		else if (isa_br != NULL) {
 			struct isa_device *isadev;
 
 try_isa_clock:
diff -Nru a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
--- a/arch/sparc64/kernel/trampoline.S	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/kernel/trampoline.S	Fri Mar 15 17:51:02 2002
@@ -181,9 +181,6 @@
 	wrpr		%g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
 	wr		%g0, 0, %fprs
 
-	sethi		%uhi(PAGE_OFFSET), %g4
-	sllx		%g4, 32, %g4
-
 	/* XXX Buggy PROM... */
 	srl		%o0, 0, %o0
 	ldx		[%o0], %g6
@@ -257,6 +254,9 @@
 #undef KERN_LOWBITS
 #undef VPTE_BASE_SPITFIRE
 #undef VPTE_BASE_CHEETAH
+
+	wrpr		%o1, 0x0, %pstate
+	ldx		[%g6 + TI_TASK], %g4
 
 	/* Setup interrupt globals, we are always SMP. */
 	wrpr		%o1, PSTATE_IG, %pstate
diff -Nru a/arch/sparc64/kernel/ttable.S b/arch/sparc64/kernel/ttable.S
--- a/arch/sparc64/kernel/ttable.S	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/kernel/ttable.S	Fri Mar 15 17:51:01 2002
@@ -45,12 +45,15 @@
 tl0_resv038:	BTRAP(0x38) BTRAP(0x39) BTRAP(0x3a) BTRAP(0x3b) BTRAP(0x3c) BTRAP(0x3d)
 tl0_resv03e:	BTRAP(0x3e) BTRAP(0x3f) BTRAP(0x40)
 #ifdef CONFIG_SMP
-tl0_irq1:	TRAP_IRQ(smp_task_migration_interrupt, 1)
+tl0_irq1:	TRAP_IRQ(smp_call_function_client, 1)
+tl0_irq2:	TRAP_IRQ(smp_receive_signal_client, 2)
+tl0_irq3:	TRAP_IRQ(smp_penguin_jailcell, 3)
 #else
 tl0_irq1:	BTRAP(0x41)
+tl0_irq2:	BTRAP(0x42)
+tl0_irq3:	BTRAP(0x43)
 #endif
-tl0_irq2:	TRAP_IRQ(handler_irq, 2)
-tl0_irq3:	TRAP_IRQ(handler_irq, 3)  TRAP_IRQ(handler_irq, 4)
+tl0_irq4:	TRAP_IRQ(handler_irq, 4)
 tl0_irq5:	TRAP_IRQ(handler_irq, 5)  TRAP_IRQ(handler_irq, 6)
 tl0_irq7:	TRAP_IRQ(handler_irq, 7)  TRAP_IRQ(handler_irq, 8)
 tl0_irq9:	TRAP_IRQ(handler_irq, 9)  TRAP_IRQ(handler_irq, 10)
diff -Nru a/arch/sparc64/kernel/winfixup.S b/arch/sparc64/kernel/winfixup.S
--- a/arch/sparc64/kernel/winfixup.S	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/kernel/winfixup.S	Fri Mar 15 17:51:03 2002
@@ -73,9 +73,8 @@
 	stx		%g5, [%g6 + TI_FAULT_ADDR]
 	wrpr		%g0, 0x0, %tl			! Out of trap levels.
 	wrpr		%l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate
-	sethi		%uhi(PAGE_OFFSET), %g4		! Prepare page_offset global reg
 	mov		%o7, %g6
-	sllx		%g4, 32, %g4			! and finish it...
+	ldx		[%g6 + TI_TASK], %g4
 
 	/* This is the same as below, except we handle this a bit special
 	 * since we must preserve %l5 and %l6, see comment above.
@@ -195,9 +194,8 @@
 	mov		%g6, %o7			! Stash away current.
 	wrpr		%g0, 0x0, %tl			! Out of trap levels.
 	wrpr		%l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate
-	sethi		%uhi(PAGE_OFFSET), %g4		! Set page_offset global reg.
 	mov		%o7, %g6			! Get current back.
-	sllx		%g4, 32, %g4			! Finish it.
+	ldx		[%g6 + TI_TASK], %g4		! Finish it.
 	call		mem_address_unaligned
 	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0
 
@@ -302,9 +300,8 @@
 	mov		%g6, %o7			! Stash away current.
 	wrpr		%g0, 0x0, %tl			! Out of trap levels.
 	wrpr		%l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate
-	sethi		%uhi(PAGE_OFFSET), %g4		! Set page_offset global reg.
 	mov		%o7, %g6			! Get current back.
-	sllx		%g4, 32, %g4			! Finish it.
+	ldx		[%g6 + TI_TASK], %g4		! Finish it.
 	call		data_access_exception
 	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0
 
diff -Nru a/arch/sparc64/lib/Makefile b/arch/sparc64/lib/Makefile
--- a/arch/sparc64/lib/Makefile	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/lib/Makefile	Fri Mar 15 17:51:01 2002
@@ -16,6 +16,6 @@
 	 VIScopy.o VISbzero.o VISmemset.o VIScsum.o VIScsumcopy.o \
 	 VIScsumcopyusr.o VISsave.o atomic.o rwlock.o bitops.o \
 	 dec_and_lock.o U3memcpy.o U3copy_from_user.o U3copy_to_user.o \
-	 U3copy_in_user.o
+	 U3copy_in_user.o mcount.o
 
 include $(TOPDIR)/Rules.make
diff -Nru a/arch/sparc64/lib/VIScsumcopy.S b/arch/sparc64/lib/VIScsumcopy.S
--- a/arch/sparc64/lib/VIScsumcopy.S	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/lib/VIScsumcopy.S	Fri Mar 15 17:51:01 2002
@@ -28,6 +28,7 @@
 #include <asm/asi.h>
 #include <asm/page.h>
 #include <asm/visasm.h>
+#include <asm/thread_info.h>
 #define ASI_BLK_XOR	0
 #define ASI_BLK_XOR1	(ASI_BLK_P ^ (ASI_BLK_P >> 3) ^ ASI_P)
 #define ASI_BLK_OR	(ASI_BLK_P & ~ASI_P)
@@ -841,9 +842,8 @@
 1:	retl					/*  CTI		Group brk forced*/
 	 srl		%src, 0, %src		/*  IEU0			*/
 #else
-1:	sethi		%uhi(PAGE_OFFSET), %g4	/*  IEU0	Group		*/
-	retl					/*  CTI		Group brk forced*/
-	 sllx		%g4, 32, %g4		/*  IEU0			*/
+1:	retl					/*  CTI		Group brk forced*/
+	 ldx		[%g6 + TI_TASK], %g4	/*  Load			*/
 #endif
 26:	andcc		%len, 8, %g0		/*  IEU1	Group		*/
 	be,pn		%icc, 1f		/*  CTI				*/
diff -Nru a/arch/sparc64/lib/VIScsumcopyusr.S b/arch/sparc64/lib/VIScsumcopyusr.S
--- a/arch/sparc64/lib/VIScsumcopyusr.S	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/lib/VIScsumcopyusr.S	Fri Mar 15 17:51:02 2002
@@ -29,6 +29,7 @@
 #include <asm/asi.h>
 #include <asm/page.h>
 #include <asm/visasm.h>
+#include <asm/thread_info.h>
 #define ASI_BLK_XOR	0
 #define ASI_BLK_XOR1	(ASI_BLK_P ^ (ASI_BLK_P >> 3) ^ ASI_P)
 #define ASI_BLK_OR	(ASI_BLK_P & ~ASI_P)
@@ -860,9 +861,8 @@
 1:	retl					/*  CTI		Group brk forced*/
 	 srl		%src, 0, %src		/*  IEU0			*/
 #else
-1:	sethi		%uhi(PAGE_OFFSET), %g4	/*  IEU0	Group		*/
-	retl					/*  CTI		Group brk forced*/
-	 sllx		%g4, 32, %g4		/*  IEU0			*/
+1:	retl					/*  CTI		Group brk forced*/
+	 ldx		[%g6 + TI_TASK], %g4	/*  Load			*/
 #endif
 26:	andcc		%len, 8, %g0		/*  IEU1	Group		*/
 	be,pn		%icc, 1f		/*  CTI				*/
diff -Nru a/arch/sparc64/lib/blockops.S b/arch/sparc64/lib/blockops.S
--- a/arch/sparc64/lib/blockops.S	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/lib/blockops.S	Fri Mar 15 17:51:01 2002
@@ -38,11 +38,13 @@
 copy_user_page: /* %o0=dest, %o1=src, %o2=vaddr */
 	VISEntry
 	sethi		%hi(PAGE_SIZE), %g3
-	sub		%o0, %g4, %g1
+	sethi		%uhi(PAGE_OFFSET), %g2
+	sllx		%g2, 32, %g2
+	sub		%o0, %g2, %g1
 	and		%o2, %g3, %o0
 	sethi		%hi(TLBTEMP_BASE), %o3
 	sethi		%uhi(_PAGE_VALID | _PAGE_SZBITS), %g3
-	sub		%o1, %g4, %g2
+	sub		%o1, %g2, %g2
 	sllx		%g3, 32, %g3
 	mov		TLB_TAG_ACCESS, %o2
 	or		%g3, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W), %g3
@@ -337,7 +339,9 @@
 clear_user_page:	/* %o0=dest, %o1=vaddr */
 	VISEntryHalf
 	sethi		%hi(PAGE_SIZE), %g3
-	sub		%o0, %g4, %g1
+	sethi		%uhi(PAGE_OFFSET), %g2
+	sllx		%g2, 32, %g2
+	sub		%o0, %g2, %g1
 	and		%o1, %g3, %o0
 	mov		TLB_TAG_ACCESS, %o2
 	sethi		%uhi(_PAGE_VALID | _PAGE_SZBITS), %g3
diff -Nru a/arch/sparc64/lib/checksum.S b/arch/sparc64/lib/checksum.S
--- a/arch/sparc64/lib/checksum.S	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/lib/checksum.S	Fri Mar 15 17:51:01 2002
@@ -94,7 +94,7 @@
 	or		%o5, %o4, %o4		! IEU0	Group
 	addcc		%o4, %sum, %sum		! IEU1
 	bcc,pt		%xcc, ccfold		! CTI
-	 sethi		%uhi(PAGE_OFFSET), %g4	! IEU0	Group
+	 nop					! IEU0	Group
 	b,pt		%xcc, ccfold		! CTI
 	 add		%sum, 1, %sum		! IEU1
 
@@ -174,14 +174,14 @@
 12:
 	andcc		%len, 0xf, %g7		! IEU1	Group
 ccte:	bne,pn		%icc, cc_end_cruft	! CTI
-	 sethi		%uhi(PAGE_OFFSET), %g4	! IEU0
+	 nop					! IEU0
 ccfold:	sllx		%sum, 32, %o0		! IEU0	Group
 	addcc		%sum, %o0, %o0		! IEU1	Group (regdep)
 	srlx		%o0, 32, %o0		! IEU0	Group (regdep)
 	bcs,a,pn	%xcc, 1f		! CTI
 	 add		%o0, 1, %o0		! IEU1	4 clocks (mispredict)
 1:	retl					! CTI	Group brk forced
-	 sllx		%g4, 32, %g4		! IEU0	Group
+	 ldx		[%g6 + TI_TASK], %g4	! Load
 
 ccslow:	mov	0, %g5
 	brlez,pn %len, 4f
@@ -321,7 +321,7 @@
 	or		%o5, %o4, %o4		! IEU0	Group
 	addcc		%o4, %sum, %sum		! IEU1
 	bcc,pt		%xcc, ccuserfold	! CTI
-	 sethi		%uhi(PAGE_OFFSET), %g4	! IEU0	Group
+	 nop					! IEU0	Group
 	b,pt		%xcc, ccuserfold	! CTI
 	 add		%sum, 1, %sum		! IEU1
 
@@ -404,7 +404,7 @@
 	andcc		%len, 0xf, %g7		! IEU1	Group
 ccuserte:
 	bne,pn		%icc, cc_user_end_cruft	! CTI
-	 sethi		%uhi(PAGE_OFFSET), %g4	! IEU0
+	 nop					! IEU0
 ccuserfold:
 	sllx		%sum, 32, %o0		! IEU0	Group
 	addcc		%sum, %o0, %o0		! IEU1	Group (regdep)
@@ -412,7 +412,7 @@
 	bcs,a,pn	%xcc, 1f		! CTI
 	 add		%o0, 1, %o0		! IEU1	4 clocks (mispredict)
 1:	retl					! CTI	Group brk forced
-	 sllx		%g4, 32, %g4		! IEU0	Group
+	 ldx		[%g6 + TI_TASK], %g4	! IEU0	Group
 
 ccuserslow:
 	mov	0, %g5
@@ -502,10 +502,9 @@
 	sub	%g0, EFAULT, %g2
 	brnz,a,pt %g1, 1f
 	 st	%g2, [%g1]
-1:	sethi	%uhi(PAGE_OFFSET), %g4
-	wr	%g3, %g0, %asi
+1:	wr	%g3, %g0, %asi
 	retl
-	 sllx	%g4, 32, %g4
+	 ldx	[%g6 + TI_TASK], %g4
 
 	.section __ex_table
 	.align  4
diff -Nru a/arch/sparc64/lib/mcount.S b/arch/sparc64/lib/mcount.S
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/arch/sparc64/lib/mcount.S	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com)
+ *
+ * This file implements mcount(), which is used to collect profiling data.
+ * This can also be tweaked for kernel stack overflow detection.
+ */
+
+#include <linux/config.h>
+#include <linux/linkage.h>
+
+#include <asm/ptrace.h>
+#include <asm/thread_info.h>
+
+/*
+ * This is the main variant and is called by C code.  GCC's -pg option
+ * automatically instruments every C function with a call to this.
+ */
+
+#ifdef CONFIG_STACK_DEBUG
+
+#define OVSTACKSIZE	4096		/* lets hope this is enough */
+
+	.data
+	.align		8
+panicstring:
+	.asciz		"Stack overflow\n"
+	.align		8
+ovstack:
+	.skip		OVSTACKSIZE
+#endif
+	.text
+	.align 32
+	.globl mcount
+mcount:
+#ifdef CONFIG_STACK_DEBUG
+	/*
+	 * Check whether %sp is dangerously low.
+	 */
+	ldub		[%g6 + TI_FPDEPTH], %g1
+	srl		%g1, 1, %g5
+	add		%g5, 1, %g5
+	sllx		%g5, 8, %g5			! each fpregs frame is 256b
+	add		%g5, 192, %g5
+	add		%g6, %g5, %g5			! where does task_struct+frame end?
+	sub		%g5, STACK_BIAS, %g5
+	cmp		%sp, %g5
+	bg,pt		%xcc, 1f
+	 sethi		%hi(panicstring), %g5
+	sethi		%hi(ovstack), %g7		! cant move to panic stack fast enough
+	 or		%g7, %lo(ovstack), %g7
+	add		%g7, OVSTACKSIZE, %g7
+	sub		%g7, STACK_BIAS, %g7
+	mov		%g7, %sp
+	call		prom_printf
+	 or		%g5, %lo(panicstring), %o0
+	call		prom_halt
+	 nop
+#endif
+1:	retl
+	 nop
diff -Nru a/arch/sparc64/mm/fault.c b/arch/sparc64/mm/fault.c
--- a/arch/sparc64/mm/fault.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/mm/fault.c	Fri Mar 15 17:51:03 2002
@@ -55,13 +55,21 @@
  */
 void set_brkpt(unsigned long addr, unsigned char mask, int flags, int mode)
 {
-	unsigned long lsubits = LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM;
+	unsigned long lsubits;
+
+	__asm__ __volatile__("ldxa [%%g0] %1, %0"
+			     : "=r" (lsubits)
+			     : "i" (ASI_LSU_CONTROL));
+	lsubits &= ~(LSU_CONTROL_PM | LSU_CONTROL_VM |
+		     LSU_CONTROL_PR | LSU_CONTROL_VR |
+		     LSU_CONTROL_PW | LSU_CONTROL_VW);
 
 	__asm__ __volatile__("stxa	%0, [%1] %2\n\t"
 			     "membar	#Sync"
 			     : /* no outputs */
 			     : "r" (addr), "r" (mode ? VIRT_WATCHPOINT : PHYS_WATCHPOINT),
 			       "i" (ASI_DMMU));
+
 	lsubits |= ((unsigned long)mask << (mode ? 25 : 33));
 	if (flags & VM_READ)
 		lsubits |= (mode ? LSU_CONTROL_VR : LSU_CONTROL_PR);
@@ -160,10 +168,12 @@
 	pmdp = pmd_offset(pgdp, tpc);
 	if (pmd_none(*pmdp))
 		goto outret;
-	ptep = pte_offset(pmdp, tpc);
+
+	/* This disables preemption for us as well. */
 	__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 	__asm__ __volatile__("wrpr %0, %1, %%pstate"
 				: : "r" (pstate), "i" (PSTATE_IE));
+	ptep = pte_offset_map(pmdp, tpc);
 	pte = *ptep;
 	if (!pte_present(pte))
 		goto out;
@@ -177,6 +187,7 @@
 			     : "r" (pa), "i" (ASI_PHYS_USE_EC));
 
 out:
+	pte_unmap(ptep);
 	__asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
 outret:
 	return insn;
@@ -340,6 +351,20 @@
 		goto good_area;
 	if (!(vma->vm_flags & VM_GROWSDOWN))
 		goto bad_area;
+	if (!(fault_code & FAULT_CODE_WRITE)) {
+		/* Non-faulting loads shouldn't expand stack. */
+		insn = get_fault_insn(regs, insn);
+		if ((insn & 0xc0800000) == 0xc0800000) {
+			unsigned char asi;
+
+			if (insn & 0x2000)
+				asi = (regs->tstate >> 24);
+			else
+				asi = (insn >> 5);
+			if ((asi & 0xf2) == 0x82)
+				goto bad_area;
+		}
+	}
 	if (expand_stack(vma, address))
 		goto bad_area;
 	/*
diff -Nru a/arch/sparc64/mm/generic.c b/arch/sparc64/mm/generic.c
--- a/arch/sparc64/mm/generic.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/mm/generic.c	Fri Mar 15 17:51:02 2002
@@ -101,10 +101,11 @@
 		end = PGDIR_SIZE;
 	offset -= address;
 	do {
-		pte_t * pte = pte_alloc(current->mm, pmd, address);
+		pte_t * pte = pte_alloc_map(current->mm, pmd, address);
 		if (!pte)
 			return -ENOMEM;
 		io_remap_pte_range(pte, address, end - address, address + offset, prot, space);
+		pte_unmap(pte);
 		address = (address + PMD_SIZE) & PMD_MASK;
 		pmd++;
 	} while (address < end);
diff -Nru a/arch/sparc64/mm/init.c b/arch/sparc64/mm/init.c
--- a/arch/sparc64/mm/init.c	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/mm/init.c	Fri Mar 15 17:51:02 2002
@@ -65,24 +65,27 @@
 
 int bigkernel = 0;
 
-int do_check_pgt_cache(int low, int high)
-{
-        int freed = 0;
+/* XXX Tune this... */
+#define PGT_CACHE_LOW	25
+#define PGT_CACHE_HIGH	50
 
-	if (pgtable_cache_size > high) {
+void check_pgt_cache(void)
+{
+	preempt_disable();
+	if (pgtable_cache_size > PGT_CACHE_HIGH) {
 		do {
 #ifdef CONFIG_SMP
 			if (pgd_quicklist)
-				free_pgd_slow(get_pgd_fast()), freed++;
+				free_pgd_slow(get_pgd_fast());
 #endif
 			if (pte_quicklist[0])
-				free_pte_slow(pte_alloc_one_fast(NULL, 0)), freed++;
+				free_pte_slow(pte_alloc_one_fast(NULL, 0));
 			if (pte_quicklist[1])
-				free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10))), freed++;
-		} while (pgtable_cache_size > low);
+				free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
+		} while (pgtable_cache_size > PGT_CACHE_LOW);
 	}
-#ifndef CONFIG_SMP 
-        if (pgd_cache_size > high / 4) {
+#ifndef CONFIG_SMP
+        if (pgd_cache_size > PGT_CACHE_HIGH / 4) {
 		struct page *page, *page2;
                 for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) {
                         if ((unsigned long)page->pprev_hash == 3) {
@@ -94,12 +97,11 @@
                                 page->pprev_hash = NULL;
                                 pgd_cache_size -= 2;
                                 __free_page(page);
-                                freed++;
                                 if (page2)
                                         page = page2->next_hash;
                                 else
                                         page = (struct page *)pgd_quicklist;
-                                if (pgd_cache_size <= low / 4)
+                                if (pgd_cache_size <= PGT_CACHE_LOW / 4)
                                         break;
                                 continue;
                         }
@@ -108,7 +110,7 @@
                 }
         }
 #endif
-        return freed;
+	preempt_enable();
 }
 
 #ifdef CONFIG_DEBUG_DCFLUSH
@@ -143,7 +145,7 @@
 static __inline__ void set_dcache_dirty(struct page *page)
 {
 	unsigned long mask = smp_processor_id();
-	unsigned long non_cpu_bits = (1UL << 24UL) - 1UL;
+	unsigned long non_cpu_bits = ~((NR_CPUS - 1UL) << 24UL);
 	mask = (mask << 24) | (1UL << PG_dcache_dirty);
 	__asm__ __volatile__("1:\n\t"
 			     "ldx	[%2], %%g7\n\t"
@@ -166,6 +168,7 @@
 			     "1:\n\t"
 			     "ldx	[%2], %%g7\n\t"
 			     "srlx	%%g7, 24, %%g5\n\t"
+			     "and	%%g5, %3, %%g5\n\t"
 			     "cmp	%%g5, %0\n\t"
 			     "bne,pn	%%icc, 2f\n\t"
 			     " andn	%%g7, %1, %%g5\n\t"
@@ -175,7 +178,8 @@
 			     " membar	#StoreLoad | #StoreStore\n"
 			     "2:"
 			     : /* no outputs */
-			     : "r" (cpu), "r" (mask), "r" (&page->flags)
+			     : "r" (cpu), "r" (mask), "r" (&page->flags),
+			       "i" (NR_CPUS - 1UL)
 			     : "g5", "g7");
 }
 
@@ -189,7 +193,7 @@
 	if (VALID_PAGE(page) &&
 	    page->mapping &&
 	    ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
-		int cpu = (pg_flags >> 24);
+		int cpu = ((pg_flags >> 24) & (NR_CPUS - 1UL));
 
 		/* This is just to optimize away some function calls
 		 * in the SMP case.
@@ -212,8 +216,8 @@
 	int dirty_cpu = dcache_dirty_cpu(page);
 
 	if (page->mapping &&
-	    page->mapping->i_mmap == NULL &&
-	    page->mapping->i_mmap_shared == NULL) {
+	    list_empty(&page->mapping->i_mmap) &&
+	    list_empty(&page->mapping->i_mmap_shared)) {
 		if (dirty) {
 			if (dirty_cpu == smp_processor_id())
 				return;
@@ -244,7 +248,7 @@
 
 	if (pmd_none(*pmd))
 		return;
-	ptep = pte_offset(pmd, address);
+	ptep = pte_offset_map(pmd, address);
 	offset = address & ~PMD_MASK;
 	if (offset + size > PMD_SIZE)
 		size = PMD_SIZE - offset;
@@ -267,6 +271,7 @@
 				flush_dcache_page_all(mm, page);
 		}
 	}
+	pte_unmap(ptep - 1);
 }
 
 static inline void flush_cache_pmd_range(struct mm_struct *mm, pgd_t *dir, unsigned long address, unsigned long size)
@@ -389,7 +394,7 @@
 			*error = 1;
 		return(0);
 	}
-	ptep = (pte_t *)pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
+	ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 	if (!pte_present(*ptep)) {
 		if (error)
 			*error = 1;
@@ -466,7 +471,7 @@
 					memset(ptep, 0, BASE_PAGE_SIZE);
 					pmd_set(pmdp, ptep);
 				}
-				ptep = (pte_t *)pmd_page(*pmdp) +
+				ptep = (pte_t *)__pmd_page(*pmdp) +
 						((vaddr >> 13) & 0x3ff);
 
 				val = trans[i].data;
@@ -1133,11 +1138,20 @@
 #else
 #define DC_ALIAS_SHIFT	0
 #endif
-pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 {
-	struct page *page = alloc_pages(GFP_KERNEL, DC_ALIAS_SHIFT);
-	unsigned long color = VPTE_COLOR(address);
+	struct page *page;
+	unsigned long color;
+
+	{
+		pte_t *ptep = pte_alloc_one_fast(mm, address);
+
+		if (ptep)
+			return ptep;
+	}
 
+	color = VPTE_COLOR(address);
+	page = alloc_pages(GFP_KERNEL, DC_ALIAS_SHIFT);
 	if (page) {
 		unsigned long *to_free;
 		unsigned long paddr;
@@ -1159,9 +1173,11 @@
 
 #if (L1DCACHE_SIZE > PAGE_SIZE)			/* is there D$ aliasing problem */
 		/* Now free the other one up, adjust cache size. */
+		preempt_disable();
 		*to_free = (unsigned long) pte_quicklist[color ^ 0x1];
 		pte_quicklist[color ^ 0x1] = to_free;
 		pgtable_cache_size++;
+		preempt_enable();
 #endif
 
 		return pte;
diff -Nru a/arch/sparc64/mm/ultra.S b/arch/sparc64/mm/ultra.S
--- a/arch/sparc64/mm/ultra.S	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/mm/ultra.S	Fri Mar 15 17:51:03 2002
@@ -11,6 +11,8 @@
 #include <asm/spitfire.h>
 #include <asm/mmu_context.h>
 #include <asm/pil.h>
+#include <asm/head.h>
+#include <asm/thread_info.h>
 
 	/* Basically, all this madness has to do with the
 	 * fact that Cheetah does not support IMMU flushes
@@ -287,9 +289,8 @@
 	 addx		%g0, %g0, %g0
 	nop
 
-	sethi		%uhi(PAGE_OFFSET), %g4
 	retl
-	 sllx		%g4, 32, %g4
+	 ldx		[%g6 + TI_TASK], %g4
 
 iflush1:sub		%o1, 0x20, %g3
 	stxa		%g0, [%g3] ASI_IC_TAG
@@ -303,7 +304,9 @@
 	.align		64
 	.globl		__flush_dcache_page
 __flush_dcache_page:	/* %o0=kaddr, %o1=flush_icache */
-	sub		%o0, %g4, %o0
+	sethi		%uhi(PAGE_OFFSET), %g1
+	sllx		%g1, 32, %g1
+	sub		%o0, %g1, %o0
 	
 	rdpr		%ver, %g1
 	sethi		%hi(0x003e0014), %g2
@@ -482,6 +485,15 @@
 	nop
 	nop
 
+	/* NOTE: This is SPECIAL!!  We do etrap/rtrap however
+	 *       we choose to deal with the "BH's run with
+	 *       %pil==15" problem (described in asm/pil.h)
+	 *       by just invoking rtrap directly past where
+	 *       BH's are checked for.
+	 *
+	 *       We do it like this because we do not want %pil==15
+	 *       lockups to prevent regs being reported.
+	 */
 	.globl		xcall_report_regs
 xcall_report_regs:
 	rdpr		%pstate, %g2
@@ -489,12 +501,14 @@
 	rdpr		%pil, %g2
 	wrpr		%g0, 15, %pil
 	sethi		%hi(109f), %g7
-	b,pt		%xcc, etrap_irq
+	b,pt		%xcc, etrap
 109:	 or		%g7, %lo(109b), %g7
 	call		__show_regs
 	 add		%sp, STACK_BIAS + REGWIN_SZ, %o0
-	b,pt		%xcc, rtrap_irq
-	 nop
+	clr		%l6
+	/* Has to be a non-v9 branch due to the large distance. */
+	b		rtrap_xcall
+	 ldx		[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
 
 	.align		32
 	.globl		xcall_flush_dcache_page_cheetah
@@ -543,20 +557,6 @@
 	nop
 	nop
 
-	.globl		xcall_capture
-xcall_capture:
-	rdpr		%pstate, %g2
-	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate
-	rdpr		%pil, %g2
-	wrpr		%g0, 15, %pil
-	sethi		%hi(109f), %g7
-	b,pt		%xcc, etrap_irq
-109:	 or		%g7, %lo(109b), %g7
-	call		smp_penguin_jailcell
-	 nop
-	b,pt		%xcc, rtrap_irq
-	 nop
-
 	.globl		xcall_promstop
 xcall_promstop:
 	rdpr		%pstate, %g2
@@ -564,7 +564,7 @@
 	rdpr		%pil, %g2
 	wrpr		%g0, 15, %pil
 	sethi		%hi(109f), %g7
-	b,pt		%xcc, etrap_irq
+	b,pt		%xcc, etrap
 109:	 or		%g7, %lo(109b), %g7
 	flushw
 	call		prom_stopself
@@ -573,21 +573,6 @@
 1:	b,a,pt		%xcc, 1b
 	nop
 
-	.globl		xcall_receive_signal
-xcall_receive_signal:
-	rdpr		%pstate, %g2
-	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate
-	rdpr		%tstate, %g1
-	andcc		%g1, TSTATE_PRIV, %g0
-	/* If we did not trap from user space, just ignore. */
-	bne,pn		%xcc, 99f
-	 sethi		%hi(109f), %g7
-	b,pt		%xcc, etrap
-109:	 or		%g7, %lo(109b), %g7
-	b,pt		%xcc, rtrap
-	 clr		%l6
-99:	retry
-
 	.data
 
 errata32_hwbug:
@@ -670,25 +655,20 @@
 __cheetah_xcall_flush_cache_all:
 	retry
 
+	/* These just get rescheduled to PIL vectors. */
 	.globl		xcall_call_function
 xcall_call_function:
-	rdpr		%pstate, %g2
-	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate
-	rdpr		%pil, %g2
-	wrpr		%g0, 15, %pil
-	sethi		%hi(109f), %g7
-	b,pt		%xcc, etrap_irq
-109:	 or		%g7, %lo(109b), %g7
-	call		smp_call_function_client
-	 nop
-	b,pt		%xcc, rtrap_irq
-	 nop
+	wr		%g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
+	retry
 
-	.globl		xcall_migrate_task
-xcall_migrate_task:
-	mov		1, %g2
-	sllx		%g2, (PIL_MIGRATE), %g2
-	wr		%g2, 0x0, %set_softint
+	.globl		xcall_receive_signal
+xcall_receive_signal:
+	wr		%g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
+	retry
+
+	.globl		xcall_capture
+xcall_capture:
+	wr		%g0, (1 << PIL_SMP_CAPTURE), %set_softint
 	retry
 
 #endif /* CONFIG_SMP */
diff -Nru a/arch/sparc64/prom/Makefile b/arch/sparc64/prom/Makefile
--- a/arch/sparc64/prom/Makefile	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/prom/Makefile	Fri Mar 15 17:51:02 2002
@@ -19,3 +19,6 @@
 	$(CC) $(AFLAGS) -ansi -c $< -o $*.o
 
 include $(TOPDIR)/Rules.make
+
+%.o: %.c
+	$(CC) $(subst -pg,,$(CFLAGS)) -c $<
diff -Nru a/arch/sparc64/solaris/entry64.S b/arch/sparc64/solaris/entry64.S
--- a/arch/sparc64/solaris/entry64.S	Fri Mar 15 17:51:01 2002
+++ b/arch/sparc64/solaris/entry64.S	Fri Mar 15 17:51:01 2002
@@ -70,9 +70,8 @@
 	.align	32
 	.globl	solaris_sparc_syscall, entry64_personality_patch
 solaris_sparc_syscall:
-	ldx		[%g6 + TI_TASK], %l0
 entry64_personality_patch:
-	ldub		[%l0 + 0x0], %l0
+	ldub		[%g4 + 0x0], %l0
 	cmp		%g1, 255
 	bg,pn		%icc, solaris_unimplemented
 	 srl		%g1, 0, %g1
diff -Nru a/arch/sparc64/solaris/ioctl.c b/arch/sparc64/solaris/ioctl.c
--- a/arch/sparc64/solaris/ioctl.c	Fri Mar 15 17:51:03 2002
+++ b/arch/sparc64/solaris/ioctl.c	Fri Mar 15 17:51:03 2002
@@ -289,11 +289,15 @@
 {
 	struct inode *ino;
 	/* I wonder which of these tests are superfluous... --patrik */
+	read_lock(&current->files->file_lock);
 	if (! current->files->fd[fd] ||
 	    ! current->files->fd[fd]->f_dentry ||
 	    ! (ino = current->files->fd[fd]->f_dentry->d_inode) ||
-	    ! ino->i_sock)
+	    ! ino->i_sock) {
+		read_unlock(&current->files->file_lock);
 		return TBADF;
+	}
+	read_unlock(&current->files->file_lock);
 	
 	switch (cmd & 0xff) {
 	case 109: /* SI_SOCKPARAMS */
diff -Nru a/arch/sparc64/vmlinux.lds b/arch/sparc64/vmlinux.lds
--- a/arch/sparc64/vmlinux.lds	Fri Mar 15 17:51:02 2002
+++ b/arch/sparc64/vmlinux.lds	Fri Mar 15 17:51:02 2002
@@ -56,6 +56,10 @@
 	*(.initcall7.init)
   }
   __initcall_end = .;
+  . = ALIGN(32);
+  __per_cpu_start = .;
+  .data.percpu  : { *(.data.percpu) }
+  __per_cpu_end = .;
   . = ALIGN(8192);
   __init_end = .;
   . = ALIGN(64);
diff -Nru a/arch/x86_64/ia32/ia32_ioctl.c b/arch/x86_64/ia32/ia32_ioctl.c
--- a/arch/x86_64/ia32/ia32_ioctl.c	Fri Mar 15 17:51:00 2002
+++ b/arch/x86_64/ia32/ia32_ioctl.c	Fri Mar 15 17:51:00 2002
@@ -3059,7 +3059,6 @@
 COMPATIBLE_IOCTL(HDIO_SET_MULTCOUNT)
 COMPATIBLE_IOCTL(HDIO_DRIVE_CMD)
 COMPATIBLE_IOCTL(HDIO_SET_PIO_MODE)
-COMPATIBLE_IOCTL(HDIO_SCAN_HWIF)
 COMPATIBLE_IOCTL(HDIO_SET_NICE)
 /* 0x02 -- Floppy ioctls */
 COMPATIBLE_IOCTL(FDMSGON)
diff -Nru a/arch/x86_64/kernel/smpboot.c b/arch/x86_64/kernel/smpboot.c
--- a/arch/x86_64/kernel/smpboot.c	Fri Mar 15 17:51:03 2002
+++ b/arch/x86_64/kernel/smpboot.c	Fri Mar 15 17:51:03 2002
@@ -559,7 +559,7 @@
 	 * We remove it from the pidhash and the runqueue
 	 * once we got the process:
 	 */
-	idle = init_task.prev_task;
+	idle = prev_task(&init_task);
 	if (!idle)
 		panic("No idle process for CPU %d", cpu);
 
diff -Nru a/drivers/acorn/char/i2c.c b/drivers/acorn/char/i2c.c
--- a/drivers/acorn/char/i2c.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acorn/char/i2c.c	Fri Mar 15 17:51:03 2002
@@ -14,6 +14,9 @@
  */
 #include <linux/init.h>
 #include <linux/sched.h>
+#include <linux/time.h>
+#include <linux/miscdevice.h>
+#include <linux/rtc.h>
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
 
@@ -21,15 +24,19 @@
 #include <asm/io.h>
 #include <asm/hardware/ioc.h>
 #include <asm/system.h>
+#include <asm/uaccess.h>
 
 #include "pcf8583.h"
 
-extern unsigned long
-mktime(unsigned int year, unsigned int mon, unsigned int day,
-       unsigned int hour, unsigned int min, unsigned int sec);
 extern int (*set_rtc)(void);
 
 static struct i2c_client *rtc_client;
+static const unsigned char days_in_mon[] = 
+	{ 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
+static unsigned int rtc_epoch = 1900;
+
+#define CMOS_CHECKSUM	(63)
+#define CMOS_YEAR	(64 + 128)
 
 static inline int rtc_command(int cmd, void *data)
 {
@@ -44,12 +51,10 @@
 /*
  * Read the current RTC time and date, and update xtime.
  */
-static void get_rtc_time(void)
+static void get_rtc_time(struct rtc_tm *rtctm, unsigned int *year)
 {
-	unsigned char ctrl;
-	unsigned char year;
-	struct rtc_tm rtctm;
-	struct mem rtcmem = { 0xc0, 1, &year };
+	unsigned char ctrl, yr[2];
+	struct mem rtcmem = { CMOS_YEAR, sizeof(yr), yr };
 
 	/*
 	 * Ensure that the RTC is running.
@@ -73,22 +78,53 @@
 	if (rtc_command(MEM_READ, &rtcmem))
 		return;
 
-	if (rtc_command(RTC_GETDATETIME, &rtctm))
+	if (rtc_command(RTC_GETDATETIME, rtctm))
 		return;
 
-	if (year < 70)
-		year += 100;
+	*year = yr[1] * 100 + yr[0];
+}
+
+static int set_rtc_time(struct rtc_tm *rtctm, unsigned int year)
+{
+	unsigned char yr[2], leap, chk;
+	struct mem cmos_year  = { CMOS_YEAR, sizeof(yr), yr };
+	struct mem cmos_check = { CMOS_CHECKSUM, 1, &chk };
+	int ret;
+
+	leap = (!(year % 4) && (year % 100)) || !(year % 400);
+
+	if (rtctm->mon > 12 || rtctm->mday == 0)
+		return -EINVAL;
+
+	if (rtctm->mday > (days_in_mon[rtctm->mon] + (rtctm->mon == 2 && leap)))
+		return -EINVAL;
+
+	if (rtctm->hours >= 24 || rtctm->mins >= 60 || rtctm->secs >= 60)
+		return -EINVAL;
 
-	xtime.tv_usec = rtctm.cs * 10000;
-	xtime.tv_sec  = mktime(1900 + year, rtctm.mon, rtctm.mday,
-			       rtctm.hours, rtctm.mins, rtctm.secs);
+	ret = rtc_command(RTC_SETDATETIME, rtctm);
+	if (ret == 0) {
+		rtc_command(MEM_READ, &cmos_check);
+		rtc_command(MEM_READ, &cmos_year);
+
+		chk -= yr[1] + yr[0];
+
+		yr[1] = year / 100;
+		yr[0] = year % 100;
+
+		chk += yr[1] + yr[0];
+
+		rtc_command(MEM_WRITE, &cmos_year);
+		rtc_command(MEM_WRITE, &cmos_check);
+	}
+	return ret;
 }
 
 /*
  * Set the RTC time only.  Note that
  * we do not touch the date.
  */
-static int set_rtc_time(void)
+static int k_set_rtc_time(void)
 {
 	struct rtc_tm new_rtctm, old_rtctm;
 	unsigned long nowtime = xtime.tv_sec;
@@ -110,13 +146,70 @@
 	 * [ rtc: 1/1/2000 23:58:00, real 2/1/2000 00:01:00,
 	 *   rtc gets set to 1/1/2000 00:01:00 ]
 	 */
-	if ((old_rtctm.hours == 23 && old_rtctm.mins  == 59) ||
-	    (new_rtctm.hours == 23 && new_rtctm.mins  == 59))
+	if ((old_rtctm.hours == 23 && old_rtctm.mins == 59) ||
+	    (new_rtctm.hours == 23 && new_rtctm.mins == 59))
 		return 1;
 
 	return rtc_command(RTC_SETTIME, &new_rtctm);
 }
 
+static int rtc_ioctl(struct inode *inode, struct file *file,
+		     unsigned int cmd, unsigned long arg)
+{
+	unsigned int year;
+	struct rtc_time rtctm;
+	struct rtc_tm rtc_raw;
+
+	switch (cmd) {
+	case RTC_ALM_READ:
+	case RTC_ALM_SET:
+		break;
+
+	case RTC_RD_TIME:
+		get_rtc_time(&rtc_raw, &year);
+		rtctm.tm_sec  = rtc_raw.secs;
+		rtctm.tm_min  = rtc_raw.mins;
+		rtctm.tm_hour = rtc_raw.hours;
+		rtctm.tm_mday = rtc_raw.mday;
+		rtctm.tm_mon  = rtc_raw.mon - 1; /* month starts at 0 */
+		rtctm.tm_year = year - 1900; /* starts at 1900 */
+		return copy_to_user((void *)arg, &rtctm, sizeof(rtctm))
+				 ? -EFAULT : 0;
+
+	case RTC_SET_TIME:
+		if (!capable(CAP_SYS_TIME))
+			return -EACCES;
+
+		if (copy_from_user(&rtctm, (void *)arg, sizeof(rtctm)))
+			return -EFAULT;
+		rtc_raw.secs     = rtctm.tm_sec;
+		rtc_raw.mins     = rtctm.tm_min;
+		rtc_raw.hours    = rtctm.tm_hour;
+		rtc_raw.mday     = rtctm.tm_mday;
+		rtc_raw.mon      = rtctm.tm_mon + 1;
+		rtc_raw.year_off = 2;
+		year             = rtctm.tm_year + 1900;
+		return set_rtc_time(&rtc_raw, year);
+		break;
+
+	case RTC_EPOCH_READ:
+		return put_user(rtc_epoch, (unsigned long *)arg);
+
+	}
+	return -EINVAL;
+}
+
+static struct file_operations rtc_fops = {
+	ioctl:	rtc_ioctl,
+};
+
+static struct miscdevice rtc_dev = {
+	minor:	RTC_MINOR,
+	name:	"rtc",
+	fops:	&rtc_fops,
+};
+
+/* IOC / IOMD i2c driver */
 
 #define FORCE_ONES	0xdc
 #define SCL		0x02
@@ -184,9 +277,16 @@
 {
 	if (client->id == I2C_DRIVERID_PCF8583 &&
 	    client->addr == 0x50) {
+		struct rtc_tm rtctm;
+		unsigned int year;
+
 		rtc_client = client;
-		get_rtc_time();
-		set_rtc = set_rtc_time;
+		get_rtc_time(&rtctm, &year);
+
+		xtime.tv_usec = rtctm.cs * 10000;
+		xtime.tv_sec  = mktime(year, rtctm.mon, rtctm.mday,
+				       rtctm.hours, rtctm.mins, rtctm.secs);
+		set_rtc = k_set_rtc_time;
 	}
 
 	return 0;
@@ -212,9 +312,16 @@
 
 static int __init i2c_ioc_init(void)
 {
+	int ret;
+
 	force_ones = FORCE_ONES | SCL | SDA;
 
-	return i2c_bit_add_bus(&ioc_ops);
+	ret = i2c_bit_add_bus(&ioc_ops);
+
+	if (ret >= 0)
+		misc_register(&rtc_dev);
+
+	return ret;
 }
 
 __initcall(i2c_ioc_init);
diff -Nru a/drivers/acorn/char/serial-atomwide.c b/drivers/acorn/char/serial-atomwide.c
--- a/drivers/acorn/char/serial-atomwide.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acorn/char/serial-atomwide.c	Fri Mar 15 17:51:03 2002
@@ -20,7 +20,4 @@
 #define MY_PORT_ADDRESS(port,cardaddr) \
 	((cardaddr) + 0x200 - (port) * 0x100)
 
-#define INIT serial_card_atomwide_init
-#define EXIT serial_card_atomwide_exit
-
 #include "serial-card.c"
diff -Nru a/drivers/acorn/char/serial-card.c b/drivers/acorn/char/serial-card.c
--- a/drivers/acorn/char/serial-card.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acorn/char/serial-card.c	Fri Mar 15 17:51:03 2002
@@ -29,6 +29,7 @@
 #include <linux/types.h>
 #include <linux/serial.h>
 #include <linux/errno.h>
+#include <linux/ioport.h>
 #include <linux/init.h>
 
 #include <asm/ecard.h>
@@ -38,95 +39,84 @@
 #define NUM_SERIALS	MY_NUMPORTS * MAX_ECARDS
 #endif
 
-#ifdef MODULE
-static int __serial_ports[NUM_SERIALS];
-static int __serial_pcount;
-static int __serial_addr[NUM_SERIALS];
+static int serial_ports[NUM_SERIALS];
+static int serial_pcount;
+static int serial_addr[NUM_SERIALS];
 static struct expansion_card *expcard[MAX_ECARDS];
-#define ADD_ECARD(ec,card) expcard[(card)] = (ec)
-#define ADD_PORT(port,addr)					\
-	do {							\
-		__serial_ports[__serial_pcount] = (port);	\
-		__serial_addr[__serial_pcount] = (addr);	\
-		__serial_pcount += 1;				\
-	} while (0)
-#else
-#define ADD_ECARD(ec,card)
-#define ADD_PORT(port,addr)
-#endif
 
 static const card_ids serial_cids[] = { MY_CARD_LIST, { 0xffff, 0xffff } };
 
 static inline int serial_register_onedev (unsigned long port, int irq)
 {
-    struct serial_struct req;
+	struct serial_struct req;
 
-    memset(&req, 0, sizeof(req));
-    req.baud_base = MY_BAUD_BASE;
-    req.irq = irq;
-    req.port = port;
-    req.flags = 0;
+	memset(&req, 0, sizeof(req));
+	req.baud_base = MY_BAUD_BASE;
+	req.irq = irq;
+	req.port = port;
+	req.flags = 0;
 
-    return register_serial(&req);
+	return register_serial(&req);
 }
 
-static int __init INIT (void)
+static int __init serial_card_init(void)
 {
-    int card = 0;
-
-    ecard_startfind ();
-
-    do {
-	struct expansion_card *ec;
-	unsigned long cardaddr;
-	int port;
-
-	ec = ecard_find (0, serial_cids);
-	if (!ec)
-	    break;
-
-	cardaddr = MY_BASE_ADDRESS(ec);
-
-	for (port = 0; port < MY_NUMPORTS; port ++) {
-	    unsigned long address;
-	    int line;
+	int card = 0;
 
-	    address = MY_PORT_ADDRESS(port, cardaddr);
+	ecard_startfind ();
 
-	    line = serial_register_onedev (address, ec->irq);
-	    if (line < 0)
-		break;
-	    ADD_PORT(line, address);
-	}
-
-	if (port) {
-	    ecard_claim (ec);
-	    ADD_ECARD(ec, card);
-	} else
-	    break;
-    } while (++card < MAX_ECARDS);
-    return card ? 0 : -ENODEV;
+	do {
+		struct expansion_card *ec;
+		unsigned long cardaddr;
+		int port;
+
+		ec = ecard_find (0, serial_cids);
+		if (!ec)
+			break;
+
+		cardaddr = MY_BASE_ADDRESS(ec);
+
+		for (port = 0; port < MY_NUMPORTS; port ++) {
+			unsigned long address;
+			int line;
+
+			address = MY_PORT_ADDRESS(port, cardaddr);
+
+			line = serial_register_onedev (address, ec->irq);
+			if (line < 0)
+				break;
+			serial_ports[serial_pcount] = line;
+			serial_addr[serial_pcount] = address;
+			serial_pcount += 1;
+		}
+
+		if (port) {
+			ecard_claim (ec);
+			expcard[card] = ec;
+		} else
+			break;
+	} while (++card < MAX_ECARDS);
+	return card ? 0 : -ENODEV;
 }
 
-static void __exit EXIT (void)
+static void __exit serial_card_exit(void)
 {
-#ifdef MODULE
-    int i;
+	int i;
 
-    for (i = 0; i < __serial_pcount; i++) {
-	unregister_serial(__serial_ports[i]);
-	release_region(__serial_addr[i], 8);
-    }
-
-    for (i = 0; i < MAX_ECARDS; i++)
-	if (expcard[i])
-	    ecard_release (expcard[i]);
-#endif
+	for (i = 0; i < serial_pcount; i++) {
+		unregister_serial(serial_ports[i]);
+		release_region(serial_addr[i], 8);
+	}
+
+	for (i = 0; i < MAX_ECARDS; i++)
+		if (expcard[i])
+			ecard_release (expcard[i]);
 }
 
 EXPORT_NO_SYMBOLS;
 
+MODULE_AUTHOR("Russell King");
 MODULE_LICENSE("GPL");
 
-module_init(INIT);
-module_exit(EXIT);
+module_init(serial_card_init);
+module_exit(serial_card_exit);
diff -Nru a/drivers/acorn/char/serial-dualsp.c b/drivers/acorn/char/serial-dualsp.c
--- a/drivers/acorn/char/serial-dualsp.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acorn/char/serial-dualsp.c	Fri Mar 15 17:51:02 2002
@@ -18,7 +18,4 @@
 #define MY_PORT_ADDRESS(port,cardaddress) \
 	((cardaddress) + (port) * 8)
 
-#define INIT serial_card_dualsp_init
-#define EXIT serial_card_dualsp_exit
-
 #include "serial-card.c"
diff -Nru a/drivers/acorn/net/ether3.c b/drivers/acorn/net/ether3.c
--- a/drivers/acorn/net/ether3.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acorn/net/ether3.c	Fri Mar 15 17:51:03 2002
@@ -718,7 +718,7 @@
 	/*
 	 * Don't print this message too many times...
 	 */
-	if (jiffies - last_warned > 30 * HZ) {
+	if (time_after(jiffies, last_warned + 10 * HZ)) {
 		last_warned = jiffies;
 		printk("%s: memory squeeze, dropping packet.\n", dev->name);
 	}
diff -Nru a/drivers/acorn/net/etherh.c b/drivers/acorn/net/etherh.c
--- a/drivers/acorn/net/etherh.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acorn/net/etherh.c	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/drivers/acorn/net/etherh.c
  *
- *  Copyright (C) 2000 Russell King
+ *  Copyright (C) 2000-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -23,6 +23,7 @@
  *  12-10-1999  CK/TEW		EtherM driver first release
  *  21-12-2000	TTC		EtherH/EtherM integration
  *  25-12-2000	RMK	1.08	Clean integration of EtherM into this driver.
+ *  03-01-2002	RMK	1.09	Always enable IRQs if we're in the nic slot.
  */
 
 #include <linux/module.h>
@@ -64,13 +65,18 @@
 	{ 0xffff,   0xffff }
 };
 
+struct etherh_priv {
+	unsigned int	id;
+	unsigned int	ctrl_port;
+	unsigned int	ctrl;
+};
 
 MODULE_AUTHOR("Russell King");
 MODULE_DESCRIPTION("EtherH/EtherM driver");
 MODULE_LICENSE("GPL");
 
 static char version[] __initdata =
-	"EtherH/EtherM Driver (c) 2000 Russell King v1.08\n";
+	"EtherH/EtherM Driver (c) 2002 Russell King v1.09\n";
 
 #define ETHERH500_DATAPORT	0x200	/* MEMC */
 #define ETHERH500_NS8390	0x000	/* MEMC */
@@ -97,18 +103,61 @@
 #define ETHERM_TX_START_PAGE	64
 #define ETHERM_STOP_PAGE	127
 
-/* --------------------------------------------------------------------------- */
+/* ------------------------------------------------------------------------ */
+
+static inline void etherh_set_ctrl(struct etherh_priv *eh, unsigned int mask)
+{
+	eh->ctrl |= mask;
+	outb(eh->ctrl, eh->ctrl_port);
+}
+
+static inline void etherh_clr_ctrl(struct etherh_priv *eh, unsigned int mask)
+{
+	eh->ctrl &= ~mask;
+	outb(eh->ctrl, eh->ctrl_port);
+}
+
+static inline unsigned int etherh_get_stat(struct etherh_priv *eh)
+{
+	return inb(eh->ctrl_port);
+}
+
+
+
+
+static void etherh_irq_enable(ecard_t *ec, int irqnr)
+{
+	struct etherh_priv *eh = ec->irq_data;
+
+	etherh_set_ctrl(eh, ETHERH_CP_IE);
+}
+
+static void etherh_irq_disable(ecard_t *ec, int irqnr)
+{
+	struct etherh_priv *eh = ec->irq_data;
+
+	etherh_clr_ctrl(eh, ETHERH_CP_IE);
+}
+
+static expansioncard_ops_t etherh_ops = {
+	irqenable:	etherh_irq_enable,
+	irqdisable:	etherh_irq_disable,
+};
+
+
+
 
 static void
 etherh_setif(struct net_device *dev)
 {
 	struct ei_device *ei_local = (struct ei_device *) dev->priv;
+	struct etherh_priv *eh = (struct etherh_priv *)dev->rmem_start;
 	unsigned long addr, flags;
 
-	save_flags_cli(flags);
+	local_irq_save(flags);
 
 	/* set the interface type */
-	switch (dev->mem_end) {
+	switch (eh->id) {
 	case PROD_I3_ETHERLAN600:
 	case PROD_I3_ETHERLAN600A:
 		addr = dev->base_addr + EN0_RCNTHI;
@@ -124,14 +173,13 @@
 		break;
 
 	case PROD_I3_ETHERLAN500:
-		addr = dev->rmem_start;
-
 		switch (dev->if_port) {
 		case IF_PORT_10BASE2:
-			outb(inb(addr) & ~ETHERH_CP_IF, addr);
+			etherh_clr_ctrl(eh, ETHERH_CP_IF);
 			break;
+
 		case IF_PORT_10BASET:
-			outb(inb(addr) | ETHERH_CP_IF, addr);
+			etherh_set_ctrl(eh, ETHERH_CP_IF);
 			break;
 		}
 		break;
@@ -140,16 +188,17 @@
 		break;
 	}
 
-	restore_flags(flags);
+	local_irq_restore(flags);
 }
 
 static int
 etherh_getifstat(struct net_device *dev)
 {
 	struct ei_device *ei_local = (struct ei_device *) dev->priv;
+	struct etherh_priv *eh = (struct etherh_priv *)dev->rmem_start;
 	int stat = 0;
 
-	switch (dev->mem_end) {
+	switch (eh->id) {
 	case PROD_I3_ETHERLAN600:
 	case PROD_I3_ETHERLAN600A:
 		switch (dev->if_port) {
@@ -168,7 +217,7 @@
 			stat = 1;
 			break;
 		case IF_PORT_10BASET:
-			stat = inb(dev->rmem_start) & ETHERH_CP_HEARTBEAT;
+			stat = etherh_get_stat(eh) & ETHERH_CP_HEARTBEAT;
 			break;
 		}
 		break;
@@ -251,7 +300,13 @@
 		return;
 	}
 
-	ei_local->dmaing |= 1;
+	/*
+	 * Make sure we have a round number of bytes if we're in word mode.
+	 */
+	if (count & 1 && ei_local->word16)
+		count++;
+
+	ei_local->dmaing = 1;
 
 	addr = dev->base_addr;
 	dma_addr = dev->mem_start;
@@ -291,7 +346,7 @@
 		}
 
 	outb (ENISR_RDC, addr + EN0_ISR);
-	ei_local->dmaing &= ~1;
+	ei_local->dmaing = 0;
 }
 
 /*
@@ -311,7 +366,7 @@
 		return;
 	}
 
-	ei_local->dmaing |= 1;
+	ei_local->dmaing = 1;
 
 	addr = dev->base_addr;
 	dma_addr = dev->mem_start;
@@ -332,7 +387,7 @@
 		insb (dma_addr, buf, count);
 
 	outb (ENISR_RDC, addr + EN0_ISR);
-	ei_local->dmaing &= ~1;
+	ei_local->dmaing = 0;
 }
 
 /*
@@ -351,7 +406,7 @@
 		return;
 	}
 
-	ei_local->dmaing |= 1;
+	ei_local->dmaing = 1;
 
 	addr = dev->base_addr;
 	dma_addr = dev->mem_start;
@@ -369,7 +424,7 @@
 		insb (dma_addr, hdr, sizeof (*hdr));
 
 	outb (ENISR_RDC, addr + EN0_ISR);
-	ei_local->dmaing &= ~1;
+	ei_local->dmaing = 0;
 }
 
 /*
@@ -427,23 +482,6 @@
 	return 0;
 }
 
-static void etherh_irq_enable(ecard_t *ec, int irqnr)
-{
-	unsigned int ctrl_addr = (unsigned int)ec->irq_data;
-	outb(inb(ctrl_addr) | ETHERH_CP_IE, ctrl_addr);
-}
-
-static void etherh_irq_disable(ecard_t *ec, int irqnr)
-{
-	unsigned int ctrl_addr = (unsigned int)ec->irq_data;
-	outb(inb(ctrl_addr) & ~ETHERH_CP_IE, ctrl_addr);
-}
-
-static expansioncard_ops_t etherh_ops = {
-	irqenable:	etherh_irq_enable,
-	irqdisable:	etherh_irq_disable,
-};
-
 /*
  * Initialisation
  */
@@ -506,6 +544,7 @@
 {
 	struct ei_device *ei_local;
 	struct net_device *dev;
+	struct etherh_priv *eh;
 	const char *dev_type;
 	int i, size;
 
@@ -517,6 +556,10 @@
 	if (!dev)
 		goto out;
 
+	eh = kmalloc(sizeof(struct etherh_priv), GFP_KERNEL);
+	if (!eh)
+		goto out_nopriv;
+
 	SET_MODULE_OWNER(dev);
 
 	dev->open	= etherh_open;
@@ -524,8 +567,15 @@
 	dev->set_config	= etherh_set_config;
 	dev->irq	= ec->irq;
 	dev->base_addr	= ecard_address(ec, ECARD_MEMC, 0);
-	dev->mem_end	= ec->cid.product;
+	dev->rmem_start	= (unsigned long)eh;
+
+	/*
+	 * IRQ and control port handling
+	 */
 	ec->ops		= &etherh_ops;
+	ec->irq_data	= eh;
+	eh->ctrl	= 0;
+	eh->id		= ec->cid.product;
 
 	switch (ec->cid.product) {
 	case PROD_ANT_ETHERM:
@@ -533,7 +583,7 @@
 			goto free;
 		dev->base_addr += ETHERM_NS8390;
 		dev->mem_start  = dev->base_addr + ETHERM_DATAPORT;
-		ec->irq_data    = (void *)(dev->base_addr + ETHERM_CTRLPORT);
+		eh->ctrl_port   = dev->base_addr + ETHERM_CTRLPORT;
 		break;
 
 	case PROD_I3_ETHERLAN500:
@@ -541,8 +591,7 @@
 			goto free;
 		dev->base_addr += ETHERH500_NS8390;
 		dev->mem_start  = dev->base_addr + ETHERH500_DATAPORT;
-		dev->rmem_start = (unsigned long)
-		ec->irq_data    = (void *)ecard_address (ec, ECARD_IOC, ECARD_FAST)
+		eh->ctrl_port   = ecard_address (ec, ECARD_IOC, ECARD_FAST)
 				  + ETHERH500_CTRLPORT;
 		break;
 
@@ -551,8 +600,8 @@
 		if (etherh_addr(dev->dev_addr, ec))
 			goto free;
 		dev->base_addr += ETHERH600_NS8390;
-		dev->mem_start = dev->base_addr + ETHERH600_DATAPORT;
-		ec->irq_data   = (void *)(dev->base_addr + ETHERH600_CTRLPORT);
+		dev->mem_start  = dev->base_addr + ETHERH600_DATAPORT;
+		eh->ctrl_port   = dev->base_addr + ETHERH600_CTRLPORT;
 		break;
 
 	default:
@@ -572,6 +621,12 @@
 		goto release;
 
 	/*
+	 * If we're in the NIC slot, make sure the IRQ is enabled
+	 */
+	if (dev->irq == 11)
+		etherh_set_ctrl(eh, ETHERH_CP_IE);
+
+	/*
 	 * Unfortunately, ethdev_init eventually calls
 	 * ether_setup, which re-writes dev->flags.
 	 */
@@ -636,6 +691,8 @@
 release:
 	release_region(dev->base_addr, 16);
 free:
+	kfree(eh);
+out_nopriv:
 	unregister_netdev(dev);
 	kfree(dev);
 out:
@@ -696,6 +753,7 @@
 		}
 		if (e_card[i]) {
 			e_card[i]->ops = NULL;
+			kfree(e_card[i]->irq_data);
 			ecard_release(e_card[i]);
 			e_card[i] = NULL;
 		}
diff -Nru a/drivers/acorn/scsi/acornscsi.c b/drivers/acorn/scsi/acornscsi.c
--- a/drivers/acorn/scsi/acornscsi.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/acorn/scsi/acornscsi.c	Fri Mar 15 17:51:00 2002
@@ -2583,10 +2583,10 @@
 	    done(SCpnt);
 	    return 0;
 	}
-	save_flags_cli(flags);
+	local_irq_save(flags);
 	if (host->scsi.phase == PHASE_IDLE)
 	    acornscsi_kick(host);
-	restore_flags(flags);
+	local_irq_restore(flags);
     }
     return 0;
 }
diff -Nru a/drivers/acorn/scsi/fas216.c b/drivers/acorn/scsi/fas216.c
--- a/drivers/acorn/scsi/fas216.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acorn/scsi/fas216.c	Fri Mar 15 17:51:02 2002
@@ -2137,7 +2137,7 @@
 	 * However, we must re-enable interrupts, or else we'll be
 	 * waiting forever.
 	 */
-	spin_unlock_irq(&io_request_lock);
+	spin_unlock_irq(info->host->host_lock);
 
 	while (!info->internal_done) {
 		/*
@@ -2149,13 +2149,13 @@
 		 * to be some time (eg, disconnected).
 		 */
 		if (inb(REG_STAT(info)) & STAT_INT) {
-			spin_lock_irq(&io_request_lock);
+			spin_lock_irq(info->host->host_lock);
 			fas216_intr(info->host);
-			spin_unlock_irq(&io_request_lock);
+			spin_unlock_irq(info->host->host_lock);
 		}
 	}
 
-	spin_lock_irq(&io_request_lock);
+	spin_lock_irq(info->host->host_lock);
 
 	return SCpnt->result;
 }
@@ -2459,13 +2459,13 @@
 
 	/*
 	 * Ugly ugly ugly!
-	 * We need to release the io_request_lock and enable
+	 * We need to release the host_lock and enable
 	 * IRQs if we sleep, but we must relock and disable
 	 * IRQs after the sleep.
 	 */
-	spin_unlock_irq(&io_request_lock);
+	spin_unlock_irq(info->host->host_lock);
 	scsi_sleep(25*HZ/100);
-	spin_lock_irq(&io_request_lock);
+	spin_lock_irq(info->host->host_lock);
 
 	/*
 	 * Release the SCSI reset.
@@ -2628,9 +2628,9 @@
 	/*
 	 * scsi standard says wait 250ms
 	 */
-	spin_unlock_irq(&io_request_lock);
+	spin_unlock_irq(info->host->host_lock);
 	scsi_sleep(25*HZ/100);
-	spin_lock_irq(&io_request_lock);
+	spin_lock_irq(info->host->host_lock);
 
 	outb(info->scsi.cfg[0], REG_CNTL1(info));
 	inb(REG_INST(info));
diff -Nru a/drivers/acpi/Config.help b/drivers/acpi/Config.help
--- a/drivers/acpi/Config.help	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/Config.help	Fri Mar 15 17:51:03 2002
@@ -1,21 +1,76 @@
-CONFIG_ACPI_DEBUG
-  The ACPI driver can optionally report errors with a great deal
-  of verbosity. Saying Y enables these statements. This will increase
-  your kernel size by around 50K.
-
-CONFIG_ACPI_BUSMGR
-  The ACPI Bus Manager enumerates devices in the ACPI namespace, and
-  handles PnP messages.  All ACPI devices use its services, so using
-  them requires saying Y here.
+CONFIG_ACPI
+  Advanced Configuration and Power Interface (ACPI) support for 
+  Linux requires an ACPI compliant platform (hardware/firmware),
+  and assumes the presence of OS-directed configuration and power
+  management (OSPM) software.  This option will enlarge your 
+  kernel by about 70K.
+
+  Linux ACPI provides a robust functional replacement for several 
+  legacy configuration and power management intefaces, including 
+  the Plug-and-Play BIOS specification (PnP BIOS), the 
+  MultiProcessor Specification (MPS), and the Advanced Power 
+  Management (APM) specification.  If both ACPI and APM support 
+  are configured, whichever is loaded first shall be used.
+  
+  The ACPI SourceForge project contains the latest source code, 
+  documentation, tools, mailing list subscription, and other 
+  information.  This project is available at:
+    <http://sourceforge.net/projects/acpi>
+
+  Linux support for ACPI is based on Intel Corporation's ACPI
+  Component Architecture (ACPI CA).  For more information see:
+    <http://developer.intel.com/technology/iapc/acpi>
+
+  ACPI is an open industry specification co-developed by Compaq, 
+  Intel, Microsoft, Phoenix, and Toshiba.  The specification is 
+  available at:
+    <http://www.acpi.info>
+
+CONFIG_ACPI_BOOT
+  This option enables the use of ACPI tables for obtaining various
+  boot-time configuration information such as system processors, 
+  memory, and interrupt routing.  
+  
+  ACPI tables supercede legacy BIOS interfaces.  For example, the 
+  Multiple APIC Description Table (MADT) defined by the ACPI 
+  Specification is a replacement for the MP Configuration Table 
+  defined by the MultiProcessor Specification (MPS).
+  
+  You can disable this feature on IA32 systems by adding "acpi_boot=off" 
+  to your kernel command line. (Try "man bootparam" or see the 
+  documentation of your boot loader about how to pass options to the 
+  kernel at boot time.)
+
+  IA64 systems do not support legacy BIOS interfaces and thus rely
+  on ACPI tables to boot the system.  No kernel command line options
+  are supported.
+  
+CONFIG_ACPI_INTERPRETER
+  The ACPI Interpreter (a.k.a. ACPI Core Subsystem) provides the 
+  fundamental services required to parse the ACPI namespace, evaluate
+  control methods, and manage ACPI hardware and events.  This 
+  subsystem exposes kernel interfaces allowing higher level software
+  to manipulate ACPI defined hardware and software interfaces.
+
+  Add "acpi=off" to the kernel command line to disable this feature.
+  (Try "man bootparam" or see the documentation of your boot loader 
+  about how to pass options to the kernel at boot time.)
+
+  Note that this option will enlarge your kernel by about 100K.
+
+CONFIG_ACPI_BUS
+  The ACPI Bus driver enumerates and manages devices in the ACPI 
+  namespace in a manner similar to other bus drivers (e.g. PCI).
+  All ACPI device drivers rely on its services. 
 
-CONFIG_ACPI_SYS
-  This driver will enable your system to shut down using ACPI, and
-  dump your ACPI DSDT table using /proc/acpi/dsdt.
+CONFIG_ACPI_AC
+  This driver adds support for the AC Adapter object, which indicates
+  whether a system is on AC, or not.  Typically, only laptops have
+  this object, since desktops are always on AC.
 
-CONFIG_ACPI_CPU
-  This driver installs ACPI as the idle handler for Linux, and uses
-  ACPI C2 and C3 processor states to save power, on systems that
-  support it.
+CONFIG_ACPI_BATTERY
+  This driver adds support for battery information through
+  /proc/acpi/battery. If you have a laptop with a battery, say Y.
 
 CONFIG_ACPI_BUTTON
   This driver registers for events based on buttons, such as the
@@ -24,21 +79,44 @@
   down the system.  Until then, you can cat it, and see output when
   a button is pressed.
 
-CONFIG_ACPI_AC
-  This driver adds support for the AC Adapter object, which indicates
-  whether a system is on AC, or not.  Typically, only laptops have
-  this object, since desktops are always on AC.
+CONFIG_ACPI_DEBUG
+  The ACPI driver can optionally report errors with a great deal
+  of verbosity. Saying Y enables these statements. This will increase
+  your kernel size by around 50K.
 
 CONFIG_ACPI_EC
   This driver is required on some systems for the proper operation of
   the battery and thermal drivers.  If you are compiling for a laptop,
   say Y.
 
-CONFIG_ACPI_CMBATT
-  This driver adds support for battery information through
-  /proc/acpi/battery. If you have a laptop with a battery, say Y.
+CONFIG_ACPI_PCI
+  This option enables ACPI-based enumeration and configuration of PCI 
+  root bridge devices, including PCI interrupt routing (_PRT) support.  
+  This is required on platforms that no longer support legacy tables 
+  (e.g. MPS/PIR) or have erroneous table entries.
+
+CONFIG_ACPI_PROCESSOR
+  This driver installs ACPI as the idle handler for Linux, and uses
+  ACPI C2 and C3 processor states to save power, on systems that
+  support it.
 
 CONFIG_ACPI_THERMAL
-  This driver handles overheating conditions on laptops. It is HIGHLY
-  recommended, as your laptop CPU may be damaged without it.
+  This driver adds support for ACPI thermal zones.  Most mobile and
+  some desktop systems support ACPI thermal zones.  It is HIGHLY
+  recommended that this option be enabled, as your processor(s)
+  may be damaged without it.
+
+CONFIG_ACPI_FAN
+  This driver adds support for ACPI fan devices, allowing user-mode 
+  applications to perform basic fan control (on, off, status).
+
+CONFIG_ACPI_SYSTEM
+  This driver will enable your system to shut down using ACPI, and
+  dump your ACPI DSDT table using /proc/acpi/dsdt.
 
+CONFIG_ACPI_SLEEP
+  Enables low-level sleep support, allowing the platform to enter
+  and exit the S1-S4 states.  Note that although the platform may
+  support this capability, full sleep support will not be viable
+  until drivers properly save/restore hardware context.  (In other
+  words, use at your own risk!)
diff -Nru a/drivers/acpi/Config.in b/drivers/acpi/Config.in
--- a/drivers/acpi/Config.in	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/Config.in	Fri Mar 15 17:51:03 2002
@@ -1,17 +1,47 @@
 #
-# ACPI configuration
+# ACPI Configuration
 #
-#mainmenu_option next_comment
-#comment 'ACPI Configuration'
+if [ "$CONFIG_X86" = "y" ]; then
+  mainmenu_option next_comment
+  comment 'ACPI Support'
+  dep_bool       'ACPI Support' 	CONFIG_ACPI $CONFIG_PCI
+  if [ "$CONFIG_ACPI" = "y" ]; then
+    define_bool CONFIG_ACPI_BOOT 	y
+    define_bool CONFIG_ACPI_BUS 	y
+    define_bool CONFIG_ACPI_EC		y
+    define_bool CONFIG_ACPI_INTERPRETER y
+    define_bool CONFIG_ACPI_PCI 	y
+    define_bool CONFIG_ACPI_POWER 	y
+    define_bool CONFIG_ACPI_SLEEP 	y
+    define_bool CONFIG_ACPI_SYSTEM 	y
+    tristate     '  AC Adapter' 	CONFIG_ACPI_AC		
+    tristate     '  Battery'		CONFIG_ACPI_BATTERY	
+    tristate     '  Button'		CONFIG_ACPI_BUTTON
+    tristate     '  Fan'		CONFIG_ACPI_FAN
+    tristate     '  Processor'		CONFIG_ACPI_PROCESSOR
+    dep_tristate '  Thermal Zone' CONFIG_ACPI_THERMAL $CONFIG_ACPI_PROCESSOR
+    bool         '  Debug Statements' 	CONFIG_ACPI_DEBUG
+  fi
+  endmenu
+fi
 
-dep_bool     '    ACPI Debug Statements' CONFIG_ACPI_DEBUG $CONFIG_ACPI
-dep_tristate '    ACPI Bus Manager' CONFIG_ACPI_BUSMGR $CONFIG_ACPI
-
-dep_tristate '      System' CONFIG_ACPI_SYS $CONFIG_ACPI_BUSMGR $CONFIG_ACPI
-dep_tristate '      Processor' CONFIG_ACPI_CPU $CONFIG_ACPI_BUSMGR $CONFIG_ACPI
-dep_tristate '      Button' CONFIG_ACPI_BUTTON $CONFIG_ACPI_BUSMGR $CONFIG_ACPI
-dep_tristate '      AC Adapter' CONFIG_ACPI_AC $CONFIG_ACPI_BUSMGR $CONFIG_ACPI
-dep_tristate '      Embedded Controller' CONFIG_ACPI_EC $CONFIG_ACPI_BUSMGR $CONFIG_ACPI
-dep_tristate '      Control Method Battery' CONFIG_ACPI_CMBATT $CONFIG_ACPI_BUSMGR $CONFIG_ACPI $CONFIG_ACPI_EC
-dep_tristate '      Thermal' CONFIG_ACPI_THERMAL $CONFIG_ACPI_BUSMGR $CONFIG_ACPI  $CONFIG_ACPI_EC
-#endmenu
+if [ "$CONFIG_IA64" = "y" ]; then
+  if [ "$CONFIG_IA64_HP_SIM" = "n" ]; then
+    mainmenu_option next_comment
+    comment 'ACPI Support'
+    define_bool CONFIG_ACPI		y
+    define_bool CONFIG_ACPI_EFI		y
+    define_bool CONFIG_ACPI_BOOT	y
+    define_bool CONFIG_ACPI_BUS		y
+    define_bool CONFIG_ACPI_INTERPRETER y
+    define_bool CONFIG_ACPI_PCI		y
+    define_bool CONFIG_ACPI_POWER 	y
+    define_bool CONFIG_ACPI_SYSTEM 	y
+    tristate     '  Button'		CONFIG_ACPI_BUTTON
+    tristate     '  Fan'		CONFIG_ACPI_FAN
+    tristate     '  Processor'		CONFIG_ACPI_PROCESSOR
+    dep_tristate '  Thermal Zone' CONFIG_ACPI_THERMAL $CONFIG_ACPI_PROCESSOR
+    bool         '  Debug Statements' 	CONFIG_ACPI_DEBUG
+    endmenu
+  fi
+fi
diff -Nru a/drivers/acpi/Makefile b/drivers/acpi/Makefile
--- a/drivers/acpi/Makefile	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/Makefile	Fri Mar 15 17:51:03 2002
@@ -4,51 +4,52 @@
 
 O_TARGET := acpi.o
 
-export-objs := acpi_ksyms.o
-
 export ACPI_CFLAGS
 
-ACPI_CFLAGS := -D_LINUX -I$(CURDIR)/include
-
-#
-# CONFIG_ACPI_KERNEL_CONFIG is currently only IA64
-#
-ifdef CONFIG_ACPI_KERNEL_CONFIG
-  ACPI_CFLAGS += -DCONFIG_ACPI_KERNEL_CONFIG_ONLY
-endif
-
-acpi-subdirs := utilities dispatcher events hardware \
-		executer namespace parser resources tables
+ACPI_CFLAGS	:= -D_LINUX -I$(CURDIR)/include
 
 ifdef CONFIG_ACPI_DEBUG
-  ACPI_CFLAGS += -DACPI_DEBUG -Wno-unused
-endif
-
-ifdef CONFIG_ACPI_DEBUGGER
-  ACPI_CFLAGS += -DENABLE_DEBUGGER
-  acpi-subdirs += debugger
+  ACPI_CFLAGS	+= -DACPI_DEBUG -Wno-unused
 endif
 
-EXTRA_CFLAGS += $(ACPI_CFLAGS)
+EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
 
-mod-subdirs  := ospm
+export-objs 	:= acpi_ksyms.o
 
-subdir-$(CONFIG_ACPI) 		+= $(acpi-subdirs)
-subdir-$(CONFIG_ACPI_BUSMGR)	+= ospm
+obj-y		:= acpi_ksyms.o 
 
-obj-$(CONFIG_ACPI)	+= driver.o os.o acpi_ksyms.o
-obj-$(CONFIG_ACPI)	+= $(foreach dir,$(acpi-subdirs),$(dir)/$(dir).o) 
-ifdef CONFIG_ACPI_KERNEL_CONFIG
-   obj-$(CONFIG_ACPI) 	+= acpiconf.o osconf.o
+#
+# ACPI Boot-Time Table Parsing
+#
+ifeq ($(CONFIG_ACPI_BOOT),y)
+  obj-y		+= acpi_tables.o
 endif
 
-ifeq ($(CONFIG_ACPI_BUSMGR),y)
-	obj-y			+= ospm/ospm.o
+#
+# ACPI Core Subsystem (Interpreter)
+#
+ifeq ($(CONFIG_ACPI_INTERPRETER),y)
+  obj-y		+= acpi_osl.o acpi_utils.o
+  subdir-y	+= dispatcher events executer hardware namespace parser \
+		   resources tables utilities
+  obj-y 	+= $(foreach dir,$(subdir-y),$(dir)/$(dir).o)
 endif
 
-# commented out until we distribute it -ASG
-#ifeq ($(CONFIG_KDB),y)
-#	obj-m	+= kdb/kdbm_acpi.o
-#endif
+#
+# ACPI Bus and Device Drivers
+#
+ifeq ($(CONFIG_ACPI_BUS),y)
+  obj-y				+= acpi_bus.o 
+  obj-$(CONFIG_ACPI_AC) 	+= acpi_ac.o
+  obj-$(CONFIG_ACPI_BATTERY)	+= acpi_battery.o
+  obj-$(CONFIG_ACPI_BUTTON)	+= acpi_button.o
+  obj-$(CONFIG_ACPI_EC)		+= acpi_ec.o
+  obj-$(CONFIG_ACPI_FAN)	+= acpi_fan.o
+  obj-$(CONFIG_ACPI_PCI)	+= acpi_pci_root.o acpi_pci_link.o
+  obj-$(CONFIG_ACPI_POWER)	+= acpi_power.o
+  obj-$(CONFIG_ACPI_PROCESSOR)	+= acpi_processor.o
+  obj-$(CONFIG_ACPI_THERMAL)	+= acpi_thermal.o
+  obj-$(CONFIG_ACPI_SYSTEM)	+= acpi_system.o
+endif
 
 include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/acpi_ac.c b/drivers/acpi/acpi_ac.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_ac.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,351 @@
+/*
+ *  acpi_ac.c - ACPI AC Adapter Driver ($Revision: 22 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_AC_COMPONENT
+ACPI_MODULE_NAME		("acpi_ac")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_AC_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define PREFIX			"ACPI: "
+
+
+int acpi_ac_add (struct acpi_device *device);
+int acpi_ac_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_ac_driver = {
+	name:			ACPI_AC_DRIVER_NAME,
+	class:			ACPI_AC_CLASS,
+	ids:			ACPI_AC_HID,
+	ops:			{
+					add:	acpi_ac_add,
+					remove:	acpi_ac_remove,
+				},
+};
+
+struct acpi_ac {
+	acpi_handle		handle;
+	unsigned long		state;
+};
+
+
+/* --------------------------------------------------------------------------
+                               AC Adapter Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_ac_get_state (
+	struct acpi_ac		*ac)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_get_state");
+
+	if (!ac)
+		return_VALUE(-EINVAL);
+
+	status = acpi_evaluate_integer(ac->handle, "_PSR", NULL, &ac->state);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error reading AC Adapter state\n"));
+		ac->state = ACPI_AC_STATUS_UNKNOWN;
+		return_VALUE(-ENODEV);
+	}
+	
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_ac_dir = NULL;
+
+static int
+acpi_ac_read_state (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_ac		*ac = (struct acpi_ac *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_read_state");
+
+	if (!ac || (off != 0))
+		goto end;
+
+	if (0 != acpi_ac_get_state(ac)) {
+		p += sprintf(p, "ERROR: Unable to read AC Adapter state\n");
+		goto end;
+	}
+
+	p += sprintf(p, "state:                   ");
+	switch (ac->state) {
+	case ACPI_AC_STATUS_OFFLINE:
+		p += sprintf(p, "off-line\n");
+		break;
+	case ACPI_AC_STATUS_ONLINE:
+		p += sprintf(p, "on-line\n");
+		break;
+	default:
+		p += sprintf(p, "unknown\n");
+		break;
+	}
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_ac_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_add_fs");
+
+	if (!acpi_ac_dir) {
+		acpi_ac_dir = proc_mkdir(ACPI_AC_CLASS, acpi_root_dir);
+		if (!acpi_ac_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_ac_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'state' [R] */
+	entry = create_proc_entry(ACPI_AC_FILE_STATE,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_AC_FILE_STATE));
+	else {
+		entry->read_proc = acpi_ac_read_state;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_ac_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_ac_remove_fs");
+
+	if (!acpi_ac_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_ac_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                   Driver Model
+   -------------------------------------------------------------------------- */
+
+void
+acpi_ac_notify (
+	acpi_handle		handle,
+	u32			event,
+	void			*data)
+{
+	struct acpi_ac		*ac = (struct acpi_ac *) data;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_notify");
+
+	if (!ac)
+		return;
+
+	if (0 != acpi_bus_get_device(ac->handle, &device))
+		return_VOID;
+
+	switch (event) {
+	case ACPI_AC_NOTIFY_STATUS:
+		acpi_ac_get_state(ac);
+		acpi_bus_generate_event(device, event, (u32) ac->state);
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"Unsupported event [0x%x]\n", event));
+		break;
+	}
+
+	return_VOID;
+}
+
+
+int
+acpi_ac_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_ac		*ac = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	ac = kmalloc(sizeof(struct acpi_ac), GFP_KERNEL);
+	if (!ac)
+		return_VALUE(-ENOMEM);
+	memset(ac, 0, sizeof(struct acpi_ac));
+
+	ac->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_AC_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_AC_CLASS);
+	acpi_driver_data(device) = ac;
+
+	result = acpi_ac_get_state(ac);
+	if (0 != result)
+		goto end;
+
+	result = acpi_ac_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	status = acpi_install_notify_handler(ac->handle,
+		ACPI_DEVICE_NOTIFY, acpi_ac_notify, ac);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error installing notify handler\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	printk(KERN_INFO PREFIX "%s [%s] (%s)\n", 
+		acpi_device_name(device), acpi_device_bid(device), 
+		ac->state?"on-line":"off-line");
+
+end:
+	if (0 != result) {
+		acpi_ac_remove_fs(device);
+		kfree(ac);
+	}
+
+	return_VALUE(result);
+}
+
+
+int
+acpi_ac_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_ac		*ac = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_remove");
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	ac = (struct acpi_ac *) acpi_driver_data(device);
+
+	status = acpi_remove_notify_handler(ac->handle,
+		ACPI_DEVICE_NOTIFY, acpi_ac_notify);
+	if (ACPI_FAILURE(status))
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error removing notify handler\n"));
+
+	acpi_ac_remove_fs(device);
+
+	kfree(ac);
+
+	return_VALUE(0);
+}
+
+
+int __init
+acpi_ac_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_init");
+
+	result = acpi_bus_register_driver(&acpi_ac_driver);
+	if (0 > result) {
+		remove_proc_entry(ACPI_AC_CLASS, acpi_root_dir);
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_ac_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ac_exit");
+
+	result = acpi_bus_unregister_driver(&acpi_ac_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_AC_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
+
+
+module_init(acpi_ac_init);
+module_exit(acpi_ac_exit);
diff -Nru a/drivers/acpi/acpi_battery.c b/drivers/acpi/acpi_battery.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_battery.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,819 @@
+/*
+ *  acpi_battery.c - ACPI Battery Driver ($Revision: 31 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_BATTERY_COMPONENT
+ACPI_MODULE_NAME		("acpi_battery")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_BATTERY_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define PREFIX			"ACPI: "
+
+
+#define ACPI_BATTERY_VALUE_UNKNOWN 0xFFFFFFFF
+
+#define ACPI_BATTERY_FORMAT_BIF	"NNNNNNNNNSSSS"
+#define ACPI_BATTERY_FORMAT_BST	"NNNN"
+
+static int acpi_battery_add (struct acpi_device *device);
+static int acpi_battery_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_battery_driver = {
+	name:			ACPI_BATTERY_DRIVER_NAME,
+	class:			ACPI_BATTERY_CLASS,
+	ids:			ACPI_BATTERY_HID,
+	ops:			{
+					add:	acpi_battery_add,
+					remove:	acpi_battery_remove,
+				},
+};
+
+struct acpi_battery_status {
+	acpi_integer		state;
+	acpi_integer		present_rate;
+	acpi_integer		remaining_capacity;
+	acpi_integer		present_voltage;
+};
+
+struct acpi_battery_info {
+	acpi_integer		power_unit;
+	acpi_integer		design_capacity;
+	acpi_integer		last_full_capacity;
+	acpi_integer		battery_technology;
+	acpi_integer		design_voltage;
+	acpi_integer		design_capacity_warning;
+	acpi_integer		design_capacity_low;
+	acpi_integer		battery_capacity_granularity_1;
+	acpi_integer		battery_capacity_granularity_2;
+	acpi_string		model_number;
+	acpi_string		serial_number;
+	acpi_string		battery_type;
+	acpi_string		oem_info;
+};
+
+struct acpi_battery_flags {
+	u8			present:1;	/* Bay occupied? */
+	u8			power_unit:1;	/* 0=watts, 1=apms */
+	u8			alarm:1;	/* _BTP present? */
+	u8			reserved:5;
+};
+
+struct acpi_battery_trips {
+	unsigned long		warning;
+	unsigned long		low;
+};
+
+struct acpi_battery {
+	acpi_handle		handle;
+	struct acpi_battery_flags flags;
+	struct acpi_battery_trips trips;
+	unsigned long		alarm;
+	struct acpi_battery_info *info;
+};
+
+
+/* --------------------------------------------------------------------------
+                               Battery Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_battery_get_info (
+	struct acpi_battery	*battery,
+	struct acpi_battery_info **bif)
+{
+	acpi_status 		status = 0;
+	acpi_buffer 		buffer = {0, NULL};
+	acpi_buffer		format = {sizeof(ACPI_BATTERY_FORMAT_BIF),
+						ACPI_BATTERY_FORMAT_BIF};
+	acpi_buffer		data = {0, NULL};
+	acpi_object 		*package = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_get_info");
+
+	if (!battery || !bif)
+		return_VALUE(-EINVAL);
+
+	/* Evalute _BIF */
+
+	status = acpi_evaluate(battery->handle, "_BIF", NULL, &buffer);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	package = (acpi_object *) buffer.pointer;
+
+	/* Extract Package Data */
+
+	status = acpi_extract_package(package, &format, &data);
+	if (status != AE_BUFFER_OVERFLOW) {
+		kfree(buffer.pointer);
+		return_VALUE(-ENODEV);
+	}
+
+	data.pointer = kmalloc(data.length, GFP_KERNEL);
+	if (!data.pointer) {
+		kfree(buffer.pointer);
+		return_VALUE(-ENOMEM);
+	}
+	memset(data.pointer, 0, data.length);
+
+	status = acpi_extract_package(package, &format, &data);
+	if (ACPI_FAILURE(status)) {
+		kfree(buffer.pointer);
+		kfree(data.pointer);
+		return_VALUE(-ENODEV);
+	}
+
+	kfree(buffer.pointer);
+
+	(*bif) = data.pointer;
+
+	return_VALUE(0);
+}
+
+static int
+acpi_battery_get_status (
+	struct acpi_battery	*battery,
+	struct acpi_battery_status **bst)
+{
+	acpi_status 		status = 0;
+	acpi_buffer 		buffer = {0, NULL};
+	acpi_buffer		format = {sizeof(ACPI_BATTERY_FORMAT_BST),
+						ACPI_BATTERY_FORMAT_BST};
+	acpi_buffer		data = {0, NULL};
+	acpi_object 		*package = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_get_status");
+
+	if (!battery || !bst)
+		return_VALUE(-EINVAL);
+
+	/* Evalute _BST */
+
+	status = acpi_evaluate(battery->handle, "_BST", NULL, &buffer);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	package = (acpi_object *) buffer.pointer;
+
+	/* Extract Package Data */
+
+	status = acpi_extract_package(package, &format, &data);
+	if (status != AE_BUFFER_OVERFLOW) {
+		kfree(buffer.pointer);
+		return_VALUE(-ENODEV);
+	}
+
+	data.pointer = kmalloc(data.length, GFP_KERNEL);
+	if (!data.pointer) {
+		kfree(buffer.pointer);
+		return_VALUE(-ENOMEM);
+	}
+	memset(data.pointer, 0, data.length);
+
+	status = acpi_extract_package(package, &format, &data);
+	if (ACPI_FAILURE(status)) {
+		kfree(buffer.pointer);
+		kfree(data.pointer);
+		return_VALUE(-ENODEV);
+	}
+
+	kfree(buffer.pointer);
+
+	(*bst) = data.pointer;
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_battery_set_alarm (
+	struct acpi_battery	*battery,
+	unsigned long		alarm)
+{
+	acpi_status		status = 0;
+	acpi_object		arg0 = {ACPI_TYPE_INTEGER};
+	acpi_object_list	arg_list = {1, &arg0};
+
+	ACPI_FUNCTION_TRACE("acpi_battery_set_alarm");
+
+	if (!battery)
+		return_VALUE(-EINVAL);
+
+	if (!battery->flags.alarm)
+		return_VALUE(-ENODEV);
+
+	arg0.integer.value = alarm;
+
+	status = acpi_evaluate(battery->handle, "_BTP", &arg_list, NULL);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Alarm set to %d\n", (u32) alarm));
+
+	battery->alarm = alarm;
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_battery_check (
+	struct acpi_battery	*battery)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	acpi_handle		handle = NULL;
+	struct acpi_device	*device = NULL;
+	struct acpi_battery_info *bif = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_check");
+	
+	if (!battery)
+		return_VALUE(-EINVAL);
+
+	result = acpi_bus_get_device(battery->handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	result = acpi_bus_get_status(device);
+	if (0 != result)
+		return_VALUE(result);
+
+	/* Insertion? */
+
+	if (!battery->flags.present && device->status.battery_present) {
+
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Battery inserted\n"));
+
+		/* Evalute _BIF to get certain static information */
+
+		result = acpi_battery_get_info(battery, &bif);
+		if (0 != result)
+			return_VALUE(result);
+
+		battery->flags.power_unit = bif->power_unit;
+		battery->trips.warning = bif->design_capacity_warning;
+		battery->trips.low = bif->design_capacity_low;
+		kfree(bif);
+
+		/* See if alarms are supported, and if so, set default */
+
+		status = acpi_get_handle(battery->handle, "_BTP", &handle);
+		if (ACPI_SUCCESS(status)) {
+			battery->flags.alarm = 1;
+			acpi_battery_set_alarm(battery, battery->trips.warning);
+		}
+	}
+
+	/* Removal? */
+
+	else if (battery->flags.present && !device->status.battery_present) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Battery removed\n"));
+	}
+
+	battery->flags.present = device->status.battery_present;
+
+	return_VALUE(result);
+}
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_battery_dir = NULL;
+
+static int
+acpi_battery_read_info (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_battery	*battery = (struct acpi_battery *) data;
+	struct acpi_battery_info *bif = 0;
+	char			*units = "?";
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_read_info");
+
+	if (!battery)
+		goto end;
+
+	if (battery->flags.present)
+		p += sprintf(p, "present:                 yes\n");
+	else {
+		p += sprintf(p, "present:                 no\n");
+		goto end;
+	}
+
+	/* Battery Info (_BIF) */
+
+	result = acpi_battery_get_info(battery, &bif);
+	if ((0 != result) || !bif) {
+		p += sprintf(p, "ERROR: Unable to read battery information\n");
+		goto end;
+	}
+
+	units = bif->power_unit ? ACPI_BATTERY_UNITS_AMPS : ACPI_BATTERY_UNITS_WATTS;
+					
+	if (bif->design_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
+		p += sprintf(p, "design capacity:         unknown\n");
+	else
+		p += sprintf(p, "design capacity:         %d %sh\n",
+			(u32) bif->design_capacity, units);
+
+	if (bif->last_full_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
+		p += sprintf(p, "last full capacity:      unknown\n");
+	else
+		p += sprintf(p, "last full capacity:      %d %sh\n",
+			(u32) bif->last_full_capacity, units);
+
+	switch ((u32) bif->battery_technology) {
+	case 0:
+		p += sprintf(p, "battery technology:      non-rechargeable\n");
+		break;
+	case 1:
+		p += sprintf(p, "battery technology:      rechargeable\n");
+		break;
+	default:
+		p += sprintf(p, "battery technology:      unknown\n");
+		break;
+	}
+
+	if (bif->design_voltage == ACPI_BATTERY_VALUE_UNKNOWN)
+		p += sprintf(p, "design voltage:          unknown\n");
+	else
+		p += sprintf(p, "design voltage:          %d mV\n",
+			(u32) bif->design_voltage);
+	
+	p += sprintf(p, "design capacity warning: %d %sh\n",
+		(u32) bif->design_capacity_warning, units);
+	p += sprintf(p, "design capacity low:     %d %sh\n",
+		(u32) bif->design_capacity_low, units);
+	p += sprintf(p, "capacity granularity 1:  %d %sh\n",
+		(u32) bif->battery_capacity_granularity_1, units);
+	p += sprintf(p, "capacity granularity 2:  %d %sh\n",
+		(u32) bif->battery_capacity_granularity_2, units);
+	p += sprintf(p, "model number:            %s\n",
+		bif->model_number);
+	p += sprintf(p, "serial number:           %s\n",
+		bif->serial_number);
+	p += sprintf(p, "battery type:            %s\n",
+		bif->battery_type);
+	p += sprintf(p, "OEM info:                %s\n",
+		bif->oem_info);
+
+end:
+	if (bif)
+		kfree(bif);
+
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_battery_read_state (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_battery	*battery = (struct acpi_battery *) data;
+	struct acpi_battery_status *bst = NULL;
+	char			*units = "?";
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_read_state");
+
+	if (!battery)
+		goto end;
+
+	if (battery->flags.present)
+		p += sprintf(p, "present:                 yes\n");
+	else {
+		p += sprintf(p, "present:                 no\n");
+		goto end;
+	}
+
+	/* Battery Units */
+
+	units = battery->flags.power_unit ? ACPI_BATTERY_UNITS_AMPS : ACPI_BATTERY_UNITS_WATTS;
+
+	/* Battery Status (_BST) */
+
+	result = acpi_battery_get_status(battery, &bst);
+	if ((0 != result) || !bst) {
+		p += sprintf(p, "ERROR: Unable to read battery status\n");
+		goto end;
+	}
+
+	if (!(bst->state & 0x04))
+		p += sprintf(p, "capacity state:          ok\n");
+	else
+		p += sprintf(p, "capacity state:          critical\n");
+
+	if ((bst->state & 0x01) && (bst->state & 0x02))
+		p += sprintf(p, "charging state:          charging/discharging\n");
+	else if (bst->state & 0x01)
+		p += sprintf(p, "charging state:          discharging\n");
+	else if (bst->state & 0x02)
+		p += sprintf(p, "charging state:          charging\n");
+	else
+		p += sprintf(p, "charging state:          unknown\n");
+
+	if (bst->present_rate == ACPI_BATTERY_VALUE_UNKNOWN)
+		p += sprintf(p, "present rate:            unknown\n");
+	else
+		p += sprintf(p, "present rate:            %d %s\n",
+			(u32) bst->present_rate, units);
+
+	if (bst->remaining_capacity == ACPI_BATTERY_VALUE_UNKNOWN)
+		p += sprintf(p, "remaining capacity:      unknown\n");
+	else
+		p += sprintf(p, "remaining capacity:      %d %sh\n",
+			(u32) bst->remaining_capacity, units);
+
+	if (bst->present_voltage == ACPI_BATTERY_VALUE_UNKNOWN)
+		p += sprintf(p, "present voltage:         unknown\n");
+	else
+		p += sprintf(p, "present voltage:         %d mV\n",
+			(u32) bst->present_voltage);
+
+end:
+	if (bst)
+		kfree(bst);
+
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_battery_read_alarm (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_battery	*battery = (struct acpi_battery *) data;
+	char			*units = "?";
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_read_alarm");
+
+	if (!battery)
+		goto end;
+
+	if (!battery->flags.present) {
+		p += sprintf(p, "present:                 no\n");
+		goto end;
+	}
+
+	/* Battery Units */
+	
+	units = battery->flags.power_unit ? ACPI_BATTERY_UNITS_AMPS : ACPI_BATTERY_UNITS_WATTS;
+
+	/* Battery Alarm */
+
+	p += sprintf(p, "alarm:                   ");
+	if (!battery->alarm)
+		p += sprintf(p, "unsupported\n");
+	else
+		p += sprintf(p, "%d %sh\n", (u32) battery->alarm, units);
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_battery_write_alarm (
+	struct file		*file,
+	const char		*buffer,
+	unsigned long		count,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_battery	*battery = (struct acpi_battery *) data;
+	char			alarm_string[12] = {'\0'};
+
+	ACPI_FUNCTION_TRACE("acpi_battery_write_alarm");
+
+	if (!battery || (count > sizeof(alarm_string) - 1))
+		return_VALUE(-EINVAL);
+
+	if (!battery->flags.present)
+		return_VALUE(-ENODEV);
+
+	if (copy_from_user(alarm_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	alarm_string[count] = '\0';
+
+	result = acpi_battery_set_alarm(battery, 
+		simple_strtoul(alarm_string, NULL, 0));
+	if (0 != result)
+		return_VALUE(result);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_battery_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_add_fs");
+
+	if (!acpi_battery_dir) {
+		acpi_battery_dir = proc_mkdir(ACPI_BATTERY_CLASS, acpi_root_dir);
+		if (!acpi_battery_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_battery_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'info' [R] */
+	entry = create_proc_entry(ACPI_BATTERY_FILE_INFO,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_BATTERY_FILE_INFO));
+	else {
+		entry->read_proc = acpi_battery_read_info;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'status' [R] */
+	entry = create_proc_entry(ACPI_BATTERY_FILE_STATUS,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_BATTERY_FILE_STATUS));
+	else {
+		entry->read_proc = acpi_battery_read_state;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'alarm' [R/W] */
+	entry = create_proc_entry(ACPI_BATTERY_FILE_ALARM,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_BATTERY_FILE_ALARM));
+	else {
+		entry->read_proc = acpi_battery_read_alarm;
+		entry->write_proc = acpi_battery_write_alarm;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_battery_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_battery_remove_fs");
+
+	if (!acpi_battery_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_battery_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Interface
+   -------------------------------------------------------------------------- */
+
+static void
+acpi_battery_notify (
+	acpi_handle		handle,
+	u32			event,
+	void			*data)
+{
+	struct acpi_battery	*battery = (struct acpi_battery *) data;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_notify");
+
+	if (!battery)
+		return_VOID;
+
+	if (0 != acpi_bus_get_device(handle, &device))
+		return_VOID;
+
+	switch (event) {
+	case ACPI_BATTERY_NOTIFY_STATUS:
+	case ACPI_BATTERY_NOTIFY_INFO:
+		acpi_battery_check(battery);
+		acpi_bus_generate_event(device, event, battery->flags.present);
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"Unsupported event [0x%x]\n", event));
+		break;
+	}
+
+	return_VOID;
+}
+
+
+static int
+acpi_battery_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = 0;
+	struct acpi_battery	*battery = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_add");
+	
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	battery = kmalloc(sizeof(struct acpi_battery), GFP_KERNEL);
+	if (!battery)
+		return_VALUE(-ENOMEM);
+	memset(battery, 0, sizeof(struct acpi_battery));
+
+	battery->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_BATTERY_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_BATTERY_CLASS);
+	acpi_driver_data(device) = battery;
+
+	result = acpi_battery_check(battery);
+	if (0 != result)
+		goto end;
+
+	result = acpi_battery_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	status = acpi_install_notify_handler(battery->handle,
+		ACPI_DEVICE_NOTIFY, acpi_battery_notify, battery);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error installing notify handler\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	printk(KERN_INFO PREFIX "%s Slot [%s] (battery %s)\n",
+		ACPI_BATTERY_DEVICE_NAME, acpi_device_bid(device),
+		device->status.battery_present?"present":"absent");
+		
+end:
+	if (0 != result) {
+		acpi_battery_remove_fs(device);
+		kfree(battery);
+	}
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_battery_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	acpi_status		status = 0;
+	struct acpi_battery	*battery = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	battery = (struct acpi_battery *) acpi_driver_data(device);
+
+	status = acpi_remove_notify_handler(battery->handle,
+		ACPI_DEVICE_NOTIFY, acpi_battery_notify);
+	if (ACPI_FAILURE(status))
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error removing notify handler\n"));
+
+	acpi_battery_remove_fs(device);
+
+	kfree(battery);
+
+	return_VALUE(0);
+}
+
+
+static int __init
+acpi_battery_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_init");
+
+	result = acpi_bus_register_driver(&acpi_battery_driver);
+	if (0 > result) {
+		remove_proc_entry(ACPI_BATTERY_CLASS, acpi_root_dir);
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+static void __exit
+acpi_battery_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_battery_exit");
+
+	result = acpi_bus_unregister_driver(&acpi_battery_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_BATTERY_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
+
+
+module_init(acpi_battery_init);
+module_exit(acpi_battery_exit);
diff -Nru a/drivers/acpi/acpi_bus.c b/drivers/acpi/acpi_bus.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_bus.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,2145 @@
+/*
+ *  acpi_bus.c - ACPI Bus Driver ($Revision: 56 $)
+ *
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/version.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/sched.h>
+#include <linux/pm.h>
+#include <linux/proc_fs.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+#include "include/acinterp.h"	/* for acpi_ex_eisa_id_to_string() */
+
+
+#define _COMPONENT		ACPI_BUS_COMPONENT
+ACPI_MODULE_NAME		("acpi_bus")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_BUS_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define	PREFIX			"ACPI: "
+
+FADT_DESCRIPTOR			acpi_fadt;
+static u8			acpi_disabled = 0;
+struct acpi_device		*acpi_root = NULL;
+struct proc_dir_entry		*acpi_root_dir = NULL;
+
+#define STRUCT_TO_INT(s)	(*((int*)&s))
+
+/*
+ * POLICY: If *anything* doesn't work, put it on the blacklist.
+ *	   If they are critical errors, mark it critical, and abort driver load.
+ */
+static struct acpi_blacklist_item acpi_blacklist[] __initdata =
+{
+	/* Portege 7020, BIOS 8.10 */
+	{"TOSHIB", "7020CT  ", 0x19991112, ACPI_TABLE_DSDT, all_versions, "Implicit Return", 0},
+	/* Portege 4030 */
+	{"TOSHIB", "4030    ", 0x19991112, ACPI_TABLE_DSDT, all_versions, "Implicit Return", 0},
+	/* Portege 310/320, BIOS 7.1 */
+	{"TOSHIB", "310     ", 0x19990511, ACPI_TABLE_DSDT, all_versions, "Implicit Return", 0},
+	/* Seattle 2, old bios rev. */
+	{"INTEL ", "440BX   ", 0x00001000, ACPI_TABLE_DSDT, less_than_or_equal, "Field beyond end of region", 0},
+	/* ASUS K7M */
+	{"ASUS  ", "K7M     ", 0x00001000, ACPI_TABLE_DSDT, less_than_or_equal, "Field beyond end of region", 0},
+	/* Intel 810 Motherboard? */
+	{"MNTRAL", "MO81010A", 0x00000012, ACPI_TABLE_DSDT, less_than_or_equal, "Field beyond end of region", 0},
+	/* Compaq Presario 1700 */
+	{"PTLTD ", "  DSDT  ", 0x06040000, ACPI_TABLE_DSDT, less_than_or_equal, "Multiple problems", 1},
+	/* Sony FX120, FX140, FX150? */
+	{"SONY  ", "U0      ", 0x20010313, ACPI_TABLE_DSDT, less_than_or_equal, "ACPI driver problem", 1},
+	/* Compaq Presario 800, Insyde BIOS */
+	{"INT440", "SYSFexxx", 0x00001001, ACPI_TABLE_DSDT, less_than_or_equal, "Does not use _REG to protect EC OpRegions", 1},
+	{""}
+};
+
+
+/* --------------------------------------------------------------------------
+                          Linux Driver Model (LDM) Support
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_LDM
+
+static int acpi_device_probe(struct device *dev);
+static int acpi_device_remove(struct device *dev, u32 flags);
+static int acpi_device_suspend(struct device *dev, u32 state, u32 stage);
+static int acpi_device_resume(struct device *dev, u32 stage);
+
+static struct device_driver acpi_bus_driver = {
+	probe: acpi_device_probe,
+	remove: acpi_device_remove,	
+	suspend: acpi_device_suspend,
+	resume: acpi_device_resume,
+};
+
+
+static int
+acpi_device_probe (
+	struct device		*dev)
+{
+	ACPI_FUNCTION_TRACE("acpi_device_probe");
+
+	if (!dev)
+		return_VALUE(-EINVAL);
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_device_remove (
+	struct device		*dev,
+	u32			flags)
+{
+	ACPI_FUNCTION_TRACE("acpi_device_remove");
+
+	if (!dev)
+		return_VALUE(-EINVAL);
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_device_suspend (
+	struct device		*dev,
+	u32			state,
+	u32			stage)
+{
+	ACPI_FUNCTION_TRACE("acpi_device_suspend");
+
+	if (!dev)
+		return_VALUE(-EINVAL);
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_device_resume (
+	struct device		*dev,
+	u32			stage)
+{
+	ACPI_FUNCTION_TRACE("acpi_device_resume");
+
+	if (!dev)
+		return_VALUE(-EINVAL);
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+#if 0 /* not used ATM */
+static int
+acpi_platform_add (
+	struct device		*dev)
+{
+	ACPI_FUNCTION_TRACE("acpi_platform_add");
+
+	if (!dev)
+		return -EINVAL;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device %s (%s) added\n",
+		dev->name, dev->bus_id));
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_platform_remove (
+	struct device		*dev)
+{
+	ACPI_FUNCTION_TRACE("acpi_platform_add");
+
+	if (!dev)
+		return -EINVAL;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device %s (%s) removed\n",
+		dev->name, dev->bus_id));
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+#endif /* unused */
+
+
+#endif /*CONFIG_LDM*/
+
+
+static int
+acpi_device_register (
+	struct acpi_device	*device,
+	struct acpi_device	*parent)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_device_register");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+#ifdef CONFIG_LDM
+	sprintf(device->dev.name, "ACPI device %s:%s", 
+		device->pnp.hardware_id, device->pnp.unique_id);
+	strncpy(device->dev.bus_id, device->pnp.bus_id, sizeof(acpi_bus_id));
+	if (parent)
+		device->dev.parent = &parent->dev;
+	device->dev.driver = &acpi_bus_driver;
+
+	result = device_register(&device->dev);
+#endif /*CONFIG_LDM*/
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_device_unregister (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_device_unregister");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+#ifdef CONFIG_LDM
+	put_device(&device->dev);
+#endif /*CONFIG_LDM*/
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                Device Management
+   -------------------------------------------------------------------------- */
+
+static void
+acpi_bus_data_handler (
+	acpi_handle		handle,
+	u32			function,
+	void			*context)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_data_handler");
+
+	/* TBD */
+
+	return_VOID;
+}
+
+
+static void
+acpi_bus_data_handler_powerf (
+	acpi_handle		handle,
+	u32			function,
+	void			*context)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_data_handler_powerf");
+
+	/* TBD */
+
+	return_VOID;
+}
+
+
+static void
+acpi_bus_data_handler_sleepf (
+	acpi_handle		handle,
+	u32			function,
+	void			*context)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_data_handler_sleepf");
+
+	/* TBD */
+
+	return_VOID;
+}
+
+
+int
+acpi_bus_get_device (
+	acpi_handle		handle,
+	struct acpi_device	**device)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_get_device");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	/* TBD: Support fixed-feature devices */
+
+	status = acpi_get_data(handle, acpi_bus_data_handler, (void**) device);
+	if (ACPI_FAILURE(status) || !*device) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Error getting context for object [%p]\n",
+			handle));
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+int
+acpi_bus_get_status (
+	struct acpi_device	*device)
+{
+	acpi_status		status = AE_OK;
+	unsigned long		sta = 0;
+	
+	ACPI_FUNCTION_TRACE("acpi_bus_get_status");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	/*
+	 * Evaluate _STA if present.
+	 */
+	if (device->flags.dynamic_status) {
+		status = acpi_evaluate_integer(device->handle, "_STA", NULL, &sta);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+		STRUCT_TO_INT(device->status) = (int) sta;
+	}
+
+	/*
+	 * Otherwise we assume the status of our parent (unless we don't
+	 * have one, in which case status is implied).
+	 */
+	else if (device->parent)
+		device->status = device->parent->status;
+	else
+		STRUCT_TO_INT(device->status) = 0x0F;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] status [%08x]\n", 
+		device->pnp.bus_id, (u32) STRUCT_TO_INT(device->status)));
+
+	return_VALUE(0);
+}
+
+
+/*
+static int
+acpi_bus_create_device_fs (struct device *device)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_create_device_fs");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	if (device->dir.entry)
+		return_VALUE(-EEXIST);
+
+	if (!device->parent)
+		device->dir.entry = proc_mkdir(device->pnp.bus_id, NULL);
+	else
+		device->dir.entry = proc_mkdir(device->pnp.bus_id,
+			device->parent->fs.entry);
+
+	if (!device->dir.entry) {
+		printk(KERN_ERR PREFIX "Unable to create fs entry '%s'\n",
+			device->pnp.bus_id);
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_bus_remove_device_fs (struct device *device)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_create_device_fs");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	if (!device->dir.entry)
+		return_VALUE(-ENODEV);
+
+	if (!device->parent)
+		remove_proc_entry(device->pnp_bus_id, NULL);
+	else
+		remove_proc_entry(device->pnp.bus_id, device->parent->fs.entry);
+
+	device->dir.entry = NULL;
+
+	return_VALUE(0);
+}
+*/
+
+
+/* --------------------------------------------------------------------------
+                                 Power Management
+   -------------------------------------------------------------------------- */
+
+int
+acpi_bus_get_power (
+	acpi_handle		handle,
+	int			*state)
+{
+	int			result = 0;
+	acpi_status             status = 0;
+	struct acpi_device	*device = NULL;
+	unsigned long		psc = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_get_power");
+
+	result = acpi_bus_get_device(handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	*state = ACPI_STATE_UNKNOWN;
+
+	if (!device->flags.power_manageable) {
+		/* TBD: Non-recursive algorithm for walking up hierarchy */
+		if (device->parent)
+			*state = device->parent->power.state;
+		else
+			*state = ACPI_STATE_D0;
+	}
+	else {
+		/*
+		 * Get the device's power state either directly (via _PSC) or 
+		 * indirectly (via power resources).
+		 */
+		if (device->power.flags.explicit_get) {
+			status = acpi_evaluate_integer(device->handle, "_PSC", 
+				NULL, &psc);
+			if (ACPI_FAILURE(status))
+				return_VALUE(-ENODEV);
+			device->power.state = (int) psc;
+		}
+		else if (device->power.flags.power_resources) {
+			result = acpi_power_get_inferred_state(device);
+			if (0 != result)
+				return_VALUE(result);
+		}
+
+		*state = device->power.state;
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] power state is D%d\n",
+		device->pnp.bus_id, device->power.state));
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_bus_set_power (
+	acpi_handle		handle,
+	int			state)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_device	*device = NULL;
+	char			object_name[5] = {'_','P','S','0'+state,'\0'};
+
+	ACPI_FUNCTION_TRACE("acpi_bus_set_power");
+
+	result = acpi_bus_get_device(handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	if ((state < ACPI_STATE_D0) || (state > ACPI_STATE_D3))
+		return_VALUE(-EINVAL);
+
+	/* Make sure this is a valid target state */
+
+	if (!device->flags.power_manageable) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Device is not power manageable\n"));
+		return_VALUE(-ENODEV);
+	}
+	if (state == device->power.state) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device is already at D%d\n", state));
+		return_VALUE(0);
+	}
+	if (!device->power.states[state].flags.valid) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Device does not support D%d\n", state));
+		return_VALUE(-ENODEV);
+	}
+	if (device->parent && (state < device->parent->power.state)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Cannot set device to a higher-powered state than parent\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	/*
+	 * Transition Power
+	 * ----------------
+	 * On transitions to a high-powered state we first apply power (via
+	 * power resources) then evalute _PSx.  Conversly for transitions to
+	 * a lower-powered state.
+	 */ 
+	if (state < device->power.state) {
+		if (device->power.flags.power_resources) {
+			result = acpi_power_transition(device, state);
+			if (0 != result)
+				goto end;
+		}
+		if (device->power.states[state].flags.explicit_set) {
+			status = acpi_evaluate_object(device->handle, 
+				object_name, NULL, NULL);
+			if (ACPI_FAILURE(status)) {
+				result = -ENODEV;
+				goto end;
+			}
+		}
+	}
+	else {
+		if (device->power.states[state].flags.explicit_set) {
+			status = acpi_evaluate_object(device->handle, 
+				object_name, NULL, NULL);
+			if (ACPI_FAILURE(status)) {
+				result = -ENODEV;
+				goto end;
+			}
+		}
+		if (device->power.flags.power_resources) {
+			result = acpi_power_transition(device, state);
+			if (0 != result)
+				goto end;
+		}
+	}
+
+end:
+	if (0 != result)
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Error transitioning device [%s] to D%d\n",
+			device->pnp.bus_id, state));
+	else
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device [%s] transitioned to D%d\n",
+			device->pnp.bus_id, state));
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_bus_get_power_flags (
+	struct acpi_device	*device)
+{
+	acpi_status             status = 0;
+	acpi_handle		handle = 0;
+	u32                     i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_get_power_flags");
+
+	if (!device)
+		return -ENODEV;
+
+	/*
+	 * Power Management Flags
+	 */
+	status = acpi_get_handle(device->handle, "_PSC", &handle);
+	if (ACPI_SUCCESS(status))
+		device->power.flags.explicit_get = 1;
+	status = acpi_get_handle(device->handle, "_IRC", &handle);
+	if (ACPI_SUCCESS(status))
+		device->power.flags.inrush_current = 1;
+	status = acpi_get_handle(device->handle, "_PRW", &handle);
+	if (ACPI_SUCCESS(status))
+		device->power.flags.wake_capable = 1;
+
+	/*
+	 * Enumerate supported power management states
+	 */
+	for (i = ACPI_STATE_D0; i <= ACPI_STATE_D3; i++) {
+		struct acpi_device_power_state *ps = &device->power.states[i];
+		char		object_name[5] = {'_','P','R','0'+i,'\0'};
+
+		/* Evaluate "_PRx" to se if power resources are referenced */
+		acpi_evaluate_reference(device->handle, object_name, NULL,
+			&ps->resources);
+		if (ps->resources.count) {
+			device->power.flags.power_resources = 1;
+			ps->flags.valid = 1;
+		}
+
+		/* Evaluate "_PSx" to see if we can do explicit sets */
+		object_name[2] = 'S';
+		status = acpi_get_handle(device->handle, object_name, &handle);
+		if (ACPI_SUCCESS(status)) {
+			ps->flags.explicit_set = 1;
+			ps->flags.valid = 1;
+		}
+
+		/* State is valid if we have some power control */
+		if (ps->resources.count || ps->flags.explicit_set)
+			ps->flags.valid = 1;
+
+		ps->power = -1;		/* Unknown - driver assigned */
+		ps->latency = -1;	/* Unknown - driver assigned */
+	}
+
+	/* Set defaults for D0 and D3 states (always valid) */
+	device->power.states[ACPI_STATE_D0].flags.valid = 1;
+	device->power.states[ACPI_STATE_D0].power = 100;
+	device->power.states[ACPI_STATE_D3].flags.valid = 1;
+	device->power.states[ACPI_STATE_D3].power = 0;
+
+	/*
+	 * System Power States
+	 * -------------------
+	 */
+	/* TBD: S1-S4 power state support and resource requirements. */
+	/*
+	for (i=ACPI_STATE_S1; i<ACPI_STATE_S5; i++) {
+		char name[5] = {'_','S',('0'+i),'D','\0'};
+		status = acpi_evaluate_integer(device->handle, name, NULL,
+			&state);
+		if (ACPI_FAILURE(status))
+			continue;
+	}
+	*/
+
+	/* TBD: System wake support and resource requirements. */
+
+	device->power.state = ACPI_STATE_UNKNOWN;
+
+	return 0;
+}
+
+
+/* --------------------------------------------------------------------------
+                              Performance Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_bus_get_perf_flags (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_get_perf_flags");
+
+	if (!device)
+		return -ENODEV;
+
+	device->performance.state = ACPI_STATE_UNKNOWN;
+
+	return 0;
+}
+
+
+/* --------------------------------------------------------------------------
+                                Event Management
+   -------------------------------------------------------------------------- */
+
+static spinlock_t		acpi_bus_event_lock = SPIN_LOCK_UNLOCKED;
+
+LIST_HEAD(acpi_bus_event_list);
+DECLARE_WAIT_QUEUE_HEAD(acpi_bus_event_queue);
+
+extern int			event_is_open;
+
+int
+acpi_bus_generate_event (
+	struct acpi_device	*device,
+	u8			type,
+	int			data)
+{
+	struct acpi_bus_event	*event = NULL;
+	u32			flags = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_generate_event");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	/* drop event on the floor if no one's listening */
+	if (!event_is_open)
+		return_VALUE(0);
+
+	event = kmalloc(sizeof(struct acpi_bus_event), GFP_KERNEL);
+	if (!event)
+		return_VALUE(-ENOMEM);
+
+	sprintf(event->device_class, "%s", device->pnp.device_class);
+	sprintf(event->bus_id, "%s", device->pnp.bus_id);
+	event->type = type;
+	event->data = data;
+
+	spin_lock_irqsave(&acpi_bus_event_lock, flags);
+	list_add_tail(&event->node, &acpi_bus_event_list);
+	spin_unlock_irqrestore(&acpi_bus_event_lock, flags);
+
+	wake_up_interruptible(&acpi_bus_event_queue);
+
+	return_VALUE(0);
+}
+
+int
+acpi_bus_receive_event (
+	struct acpi_bus_event	*event)
+{
+	u32			flags = 0;
+	struct acpi_bus_event	*entry = NULL;
+
+	DECLARE_WAITQUEUE(wait, current);
+
+	ACPI_FUNCTION_TRACE("acpi_bus_receive_event");
+
+	if (!event)
+		return -EINVAL;
+
+	if (list_empty(&acpi_bus_event_list)) {
+
+		set_current_state(TASK_INTERRUPTIBLE);
+		add_wait_queue(&acpi_bus_event_queue, &wait);
+
+		if (list_empty(&acpi_bus_event_list))
+			schedule();
+
+		remove_wait_queue(&acpi_bus_event_queue, &wait);
+		set_current_state(TASK_RUNNING);
+
+		if (signal_pending(current))
+			return_VALUE(-ERESTARTSYS);
+	}
+
+	spin_lock_irqsave(&acpi_bus_event_lock, flags);
+	entry = list_entry(acpi_bus_event_list.next, struct acpi_bus_event, node);
+	if (entry)
+		list_del(&entry->node);
+	spin_unlock_irqrestore(&acpi_bus_event_lock, flags);
+
+	if (!entry)
+		return_VALUE(-ENODEV);
+
+	memcpy(event, entry, sizeof(struct acpi_bus_event));
+
+	kfree(entry);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                               Namespace Management
+   -------------------------------------------------------------------------- */
+
+#define WALK_UP			0
+#define WALK_DOWN		1
+
+typedef int (*acpi_bus_walk_callback)(struct acpi_device*, int, void*);
+
+#define HAS_CHILDREN(d)		((d)->children.next != &((d)->children))
+#define HAS_SIBLINGS(d)		(((d)->parent) && ((d)->node.next != &(d)->parent->children))
+#define NODE_TO_DEVICE(n)	(list_entry(n, struct acpi_device, node))
+
+
+/**
+ * acpi_bus_walk
+ * -------------
+ * Used to walk the ACPI Bus's device namespace.  Can walk down (depth-first)
+ * or up.  Able to parse starting at any node in the namespace.  Note that a
+ * callback return value of -ELOOP will terminate the walk.
+ *
+ * @start:	starting point
+ * callback:	function to call for every device encountered while parsing
+ * direction:	direction to parse (up or down)
+ * @data:	context for this search operation
+ */
+static int
+acpi_bus_walk (
+	struct acpi_device	*start, 
+	acpi_bus_walk_callback	callback, 
+	int			direction, 
+	void			*data)
+{
+	int			result = 0;
+	int			level = 0;
+	struct acpi_device	*device = NULL;
+
+	if (!start || !callback)
+		return -EINVAL;
+
+	device = start;
+
+	/*
+	 * Parse Namespace
+	 * ---------------
+	 * Parse a given subtree (specified by start) in the given direction.
+	 * Walking 'up' simply means that we execute the callback on leaf
+	 * devices prior to their parents (useful for things like removing
+	 * or powering down a subtree).
+	 */
+
+	while (device) {
+
+		if (direction == WALK_DOWN)
+			if (-ELOOP == callback(device, level, data))
+				break;
+
+		/* Depth First */
+
+		if (HAS_CHILDREN(device)) {
+			device = NODE_TO_DEVICE(device->children.next);
+			++level;
+			continue;
+		}
+
+		if (direction == WALK_UP)
+			if (-ELOOP == callback(device, level, data))
+				break;
+
+		/* Now Breadth */
+
+		if (HAS_SIBLINGS(device)) {
+			device = NODE_TO_DEVICE(device->node.next);
+			continue;
+		}
+
+		/* Scope Exhausted - Find Next */
+
+		while ((device = device->parent)) {
+			--level;
+			if (HAS_SIBLINGS(device)) {
+				device = NODE_TO_DEVICE(device->node.next);
+				break;
+			}
+		}
+	}
+
+	if ((direction == WALK_UP) && (result == 0))
+		callback(start, level, data);
+
+	return result;
+}
+
+
+/* --------------------------------------------------------------------------
+                             Notification Handling
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_bus_check_device (
+	struct acpi_device	*device,
+	int			*status_changed)
+{
+	acpi_status             status = 0;
+	struct acpi_device_status old_status;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_check_device");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	if (status_changed)
+		*status_changed = 0;
+
+	old_status = device->status;
+
+	/*
+	 * Make sure this device's parent is present before we go about
+	 * messing with the device.
+	 */
+	if (device->parent && !device->parent->status.present) {
+		device->status = device->parent->status;
+		if (STRUCT_TO_INT(old_status) != STRUCT_TO_INT(device->status)) {
+			if (status_changed)
+				*status_changed = 1;
+		}
+		return_VALUE(0);
+	}
+
+	status = acpi_bus_get_status(device);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	if (STRUCT_TO_INT(old_status) == STRUCT_TO_INT(device->status))
+		return_VALUE(0);
+
+	if (status_changed)
+		*status_changed = 1;
+	
+	/*
+	 * Device Insertion/Removal
+	 */
+	if ((device->status.present) && !(old_status.present)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device insertion detected\n"));
+		/* TBD: Handle device insertion */
+	}
+	else if (!(device->status.present) && (old_status.present)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Device removal detected\n"));
+		/* TBD: Handle device removal */
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_bus_check_scope (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	int			status_changed = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_check_scope");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	/* Status Change? */
+	result = acpi_bus_check_device(device, &status_changed);
+	if (0 != result)
+		return_VALUE(result);
+
+	if (!status_changed)
+		return_VALUE(0);
+
+	/*
+	 * TBD: Enumerate child devices within this device's scope and
+	 *       run acpi_bus_check_device()'s on them.
+	 */
+
+	return_VALUE(0);
+}
+
+
+/**
+ * acpi_bus_notify
+ * ---------------
+ * Callback for all 'system-level' device notifications (values 0x00-0x7F).
+ */
+static void 
+acpi_bus_notify (
+	acpi_handle             handle,
+	u32                     type,
+	void                    *data)
+{
+	int			result = 0;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_notify");
+
+	if (0 != acpi_bus_get_device(handle, &device))
+		return_VOID;
+
+	switch (type) {
+
+	case ACPI_NOTIFY_BUS_CHECK:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received BUS CHECK notification for device [%s]\n", 
+			device->pnp.bus_id));
+		result = acpi_bus_check_scope(device);
+		/* 
+		 * TBD: We'll need to outsource certain events to non-ACPI
+		 *	drivers via the device manager (device.c).
+		 */
+		break;
+
+	case ACPI_NOTIFY_DEVICE_CHECK:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received DEVICE CHECK notification for device [%s]\n", 
+			device->pnp.bus_id));
+		result = acpi_bus_check_device(device, NULL);
+		/* 
+		 * TBD: We'll need to outsource certain events to non-ACPI
+		 *	drivers via the device manager (device.c).
+		 */
+		break;
+
+	case ACPI_NOTIFY_DEVICE_WAKE:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received DEVICE WAKE notification for device [%s]\n", 
+			device->pnp.bus_id));
+		/* TBD */
+		break;
+
+	case ACPI_NOTIFY_EJECT_REQUEST:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received EJECT REQUEST notification for device [%s]\n", 
+			device->pnp.bus_id));
+		/* TBD */
+		break;
+
+	case ACPI_NOTIFY_DEVICE_CHECK_LIGHT:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received DEVICE CHECK LIGHT notification for device [%s]\n", 
+			device->pnp.bus_id));
+		/* TBD: Exactly what does 'light' mean? */
+		break;
+
+	case ACPI_NOTIFY_FREQUENCY_MISMATCH:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received FREQUENCY MISMATCH notification for device [%s]\n", 
+			device->pnp.bus_id));
+		/* TBD */
+		break;
+
+	case ACPI_NOTIFY_BUS_MODE_MISMATCH:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received BUS MODE MISMATCH notification for device [%s]\n", 
+			device->pnp.bus_id));
+		/* TBD */
+		break;
+
+	case ACPI_NOTIFY_POWER_FAULT:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received POWER FAULT notification for device [%s]\n", 
+			device->pnp.bus_id));
+		/* TBD */
+		break;
+
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Received unknown/unsupported notification [%08x]\n", 
+			type));
+		break;
+	}
+
+	return_VOID;
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Management
+   -------------------------------------------------------------------------- */
+
+static LIST_HEAD(acpi_bus_drivers);
+static DECLARE_MUTEX(acpi_bus_drivers_lock);
+
+
+/**
+ * acpi_bus_match 
+ * --------------
+ * Checks the device's hardware (_HID) or compatible (_CID) ids to see if it
+ * matches the specified driver's criteria.
+ */
+static int
+acpi_bus_match (
+	struct acpi_device	*device,
+	struct acpi_driver	*driver)
+{
+
+	if (!device || !driver)
+		return -EINVAL;
+
+	if (0 != strstr(driver->ids, device->pnp.hardware_id))
+		return 0;
+
+	if (device->flags.compatible_ids) {
+		acpi_status	status = AE_OK;
+		acpi_buffer	buffer = {ACPI_ALLOCATE_BUFFER, NULL};
+		acpi_object	*object = NULL;
+		char		cid[256];
+
+		memset(cid, 0, sizeof(cid));
+
+		status = acpi_evaluate_object(device->handle, "_CID", 
+			NULL, &buffer);
+		if (ACPI_FAILURE(status) || !buffer.pointer)
+			return -ENOENT;
+
+		object = (acpi_object *) buffer.pointer;
+
+		switch (object->type) {
+		case ACPI_TYPE_INTEGER:
+			acpi_ex_eisa_id_to_string((u32) object->integer.value, 
+				cid);
+			break;
+		case ACPI_TYPE_STRING:
+			strncpy(cid, object->string.pointer, sizeof(cid) - 1);
+			break;
+		case ACPI_TYPE_PACKAGE:
+			/* TBD: Support CID packages */
+		default:
+			return -ENOENT;
+		}
+
+		if (0 != strstr(cid, device->pnp.hardware_id))
+			return 0;
+	}
+
+	return -ENOENT;
+}
+
+
+/**
+ * acpi_bus_driver_init 
+ * --------------------
+ * Used to initialize a device via its device driver.  Called whenever a 
+ * driver is bound to a device.  Invokes the driver's add() and start() ops.
+ */
+static int
+acpi_bus_driver_init (
+	struct acpi_device	*device, 
+	struct acpi_driver	*driver)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_driver_init");
+
+	if (!device || !driver)
+		return_VALUE(-EINVAL);
+
+	if (!driver->ops.add)
+		return_VALUE(-ENOSYS);
+
+	result = driver->ops.add(device);
+	if (0 != result) {
+		device->driver = NULL;
+		acpi_driver_data(device) = NULL;
+		return_VALUE(result);
+	}
+
+	/*
+	 * TBD - Configuration Management: Assign resources to device based
+	 * upon possible configuration and currently allocated resources.
+	 */
+
+	if (driver->ops.start) {
+		result = driver->ops.start(device);
+		if ((0 != result) && (driver->ops.remove))
+			driver->ops.remove(device, ACPI_BUS_REMOVAL_NORMAL);
+		return_VALUE(result);
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Driver successfully bound to device\n"));
+
+#ifdef CONFIG_LDM
+	/* 
+	 * Update the device information (in the global device hierarchy) now
+	 * that there's a driver bound to it.
+	 */
+	strncpy(device->dev.name, device->pnp.device_name, 
+		sizeof(device->dev.name));
+#endif
+
+	if (driver->ops.scan) {
+		driver->ops.scan(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+/**
+ * acpi_bus_bind 
+ * -------------
+ * Callback for acpi_bus_walk() used to find devices that match a specific 
+ * driver's criteria and bind the driver to the device.
+ */
+static int
+acpi_bus_bind (
+	struct acpi_device	*device, 
+	int			level, 
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_driver	*driver = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_bind");
+
+	if (!device || !data)
+		return_VALUE(-EINVAL);
+
+	driver = (struct acpi_driver *) data;
+
+	if (device->driver)
+		return_VALUE(-EEXIST);
+
+	if (!device->status.present)
+		return_VALUE(-ENODEV);
+
+	result = acpi_bus_match(device, driver);
+	if (0 != result)
+		return_VALUE(result);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found driver [%s] for device [%s]\n",
+		driver->name, device->pnp.bus_id));
+	
+	result = acpi_bus_driver_init(device, driver);
+	if (0 != result)
+		return_VALUE(result);
+
+	down(&acpi_bus_drivers_lock);
+	++driver->references;
+	up(&acpi_bus_drivers_lock);
+
+	return_VALUE(0);
+}
+
+
+/**
+ * acpi_bus_unbind 
+ * ---------------
+ * Callback for acpi_bus_walk() used to find devices that match a specific 
+ * driver's criteria and unbind the driver from the device.
+ */
+static int
+acpi_bus_unbind (
+	struct acpi_device	*device, 
+	int			level, 
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_driver	*driver = (struct acpi_driver *) data;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_unbind");
+
+	if (!device || !driver)
+		return_VALUE(-EINVAL);
+
+	if (device->driver != driver)
+		return_VALUE(-ENOENT);
+
+	if (!driver->ops.remove)
+		return_VALUE(-ENOSYS);
+
+	result = driver->ops.remove(device, ACPI_BUS_REMOVAL_NORMAL);
+	if (0 != result)
+		return_VALUE(result);
+
+	device->driver = NULL;
+	acpi_driver_data(device) = NULL;
+
+	down(&acpi_bus_drivers_lock);
+	driver->references--;
+	up(&acpi_bus_drivers_lock);
+
+	return_VALUE(0);
+}
+
+
+/**
+ * acpi_bus_find_driver 
+ * --------------------
+ * Parses the list of registered drivers looking for a driver applicable for
+ * the specified device.
+ */
+static int
+acpi_bus_find_driver (
+	struct acpi_device	*device)
+{
+	int			result = -ENODEV;
+	struct list_head	*entry = NULL;
+	struct acpi_driver	*driver = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_find_driver");
+
+	if (!device || device->driver)
+		return_VALUE(-EINVAL);
+
+	down(&acpi_bus_drivers_lock);
+
+	list_for_each(entry, &acpi_bus_drivers) {
+
+		driver = list_entry(entry, struct acpi_driver, node);
+
+		if (0 != acpi_bus_match(device, driver))
+			continue;
+
+		result = acpi_bus_driver_init(device, driver);
+		if (0 == result)
+			++driver->references;
+
+		break;
+	}
+
+	up(&acpi_bus_drivers_lock);
+
+	return_VALUE(result);
+}
+
+
+/**
+ * acpi_bus_register_driver 
+ * ------------------------ 
+ * Registers a driver with the ACPI bus.  Searches the namespace for all
+ * devices that match the driver's criteria and binds.
+ */
+int
+acpi_bus_register_driver (
+	struct acpi_driver	*driver)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_register_driver");
+
+	if (!driver)
+		return_VALUE(-EINVAL);
+
+	down(&acpi_bus_drivers_lock);
+	list_add_tail(&driver->node, &acpi_bus_drivers);
+	up(&acpi_bus_drivers_lock);
+
+	acpi_bus_walk(acpi_root, acpi_bus_bind, 
+		WALK_DOWN, driver);
+
+	return_VALUE(driver->references);
+}
+
+
+/**
+ * acpi_bus_unregister_driver 
+ * --------------------------
+ * Unregisters a driver with the ACPI bus.  Searches the namespace for all
+ * devices that match the driver's criteria and unbinds.
+ */
+int
+acpi_bus_unregister_driver (
+	struct acpi_driver	*driver)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_unregister_driver");
+
+	if (!driver)
+		return_VALUE(-EINVAL);
+
+	acpi_bus_walk(acpi_root, acpi_bus_unbind, WALK_UP, driver);
+
+	if (driver->references)
+		return_VALUE(driver->references);
+
+	down(&acpi_bus_drivers_lock);
+	list_del(&driver->node);
+	up(&acpi_bus_drivers_lock);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Device Enumeration
+   -------------------------------------------------------------------------- */
+
+static int 
+acpi_bus_get_flags (
+	struct acpi_device	*device)
+{
+	acpi_status		status = AE_OK;
+	acpi_handle		temp = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_get_flags");
+
+	/* Presence of _STA indicates 'dynamic_status' */
+	status = acpi_get_handle(device->handle, "_STA", &temp);
+	if (ACPI_SUCCESS(status))
+		device->flags.dynamic_status = 1;
+
+	/* Presence of _CID indicates 'compatible_ids' */
+	status = acpi_get_handle(device->handle, "_CID", &temp);
+	if (ACPI_SUCCESS(status))
+		device->flags.compatible_ids = 1;
+
+	/* Presence of _RMV indicates 'removable' */
+	status = acpi_get_handle(device->handle, "_RMV", &temp);
+	if (ACPI_SUCCESS(status))
+		device->flags.removable = 1;
+
+	/* Presence of _EJD|_EJ0 indicates 'ejectable' */
+	status = acpi_get_handle(device->handle, "_EJD", &temp);
+	if (ACPI_SUCCESS(status))
+		device->flags.ejectable = 1;
+	else {
+		status = acpi_get_handle(device->handle, "_EJ0", &temp);
+		if (ACPI_SUCCESS(status))
+			device->flags.ejectable = 1;
+	}
+
+	/* Presence of _LCK indicates 'lockable' */
+	status = acpi_get_handle(device->handle, "_LCK", &temp);
+	if (ACPI_SUCCESS(status))
+		device->flags.lockable = 1;
+
+	/* Presence of _PS0|_PR0 indicates 'power manageable' */
+	status = acpi_get_handle(device->handle, "_PS0", &temp);
+	if (ACPI_FAILURE(status))
+		status = acpi_get_handle(device->handle, "_PR0", &temp);
+	if (ACPI_SUCCESS(status))
+		device->flags.power_manageable = 1;
+
+	/* TBD: Peformance management */
+
+	return_VALUE(0);
+}
+
+
+static int 
+acpi_bus_add (
+	struct acpi_device	**child,
+	struct acpi_device	*parent,
+	acpi_handle		handle,
+	int			type)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_device	*device = NULL;
+	char			bus_id[5] = {'?',0};
+	acpi_buffer		buffer = {sizeof(bus_id), bus_id};
+	acpi_device_info	info;
+	char			*hid = "?";
+	char			*uid = "0";
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_add");
+
+	if (!child)
+		return_VALUE(-EINVAL);
+
+	device = kmalloc(sizeof(struct acpi_device), GFP_KERNEL);
+	if (!device) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Memory allocation error\n"));
+		return_VALUE(-ENOMEM);
+	}
+	memset(device, 0, sizeof(struct acpi_device));
+
+	device->handle = handle;
+	device->parent = parent;
+
+	/*
+	 * Flags
+	 * -----
+	 * Get prior to calling acpi_bus_get_status() so we know whether
+	 * or not _STA is present.  Note that we only look for object
+	 * handles -- cannot evaluate objects until we know the device is
+	 * present and properly initialized.
+	 */
+	result = acpi_bus_get_flags(device);
+	if (0 != result)
+		goto end;
+
+	/*
+	 * Status
+	 * ------
+	 * See if the device is present.  We always assume that non-Device()
+	 * objects (e.g. thermal zones, power resources, processors, etc.) are
+	 * present, functioning, etc. (at least when parent object is present).
+	 * Note that _STA has a different meaning for some objects (e.g.
+	 * power resources) so we need to be careful how we use it.
+	 */
+	switch (type) {
+	case ACPI_BUS_TYPE_DEVICE:
+		result = acpi_bus_get_status(device);
+		if (0 != result)
+			goto end;
+		break;
+	default:
+		STRUCT_TO_INT(device->status) = 0x0F;
+		break;
+	}
+	if (!device->status.present) {
+		result = -ENOENT;
+		goto end;
+	}
+
+	/*
+	 * Initialize Device
+	 * -----------------
+	 * TBD: Synch with Core's enumeration/initialization process.
+	 */
+
+	/*
+	 * Bus ID
+	 * ------
+	 * The device's Bus ID is simply the object name.
+	 * TBD: Shouldn't this value be unique (within the ACPI namespace)?
+	 */
+	switch (type) {
+	case ACPI_BUS_TYPE_SYSTEM:
+		sprintf(device->pnp.bus_id, "%s", "root");
+		break;
+	case ACPI_BUS_TYPE_POWER_BUTTON:
+		sprintf(device->pnp.bus_id, "%s", "PWRF");
+		break;
+	case ACPI_BUS_TYPE_SLEEP_BUTTON:
+		sprintf(device->pnp.bus_id, "%s", "SLPF");
+		break;
+	default:
+		acpi_get_name(handle, ACPI_SINGLE_NAME, &buffer);
+		/* Clean up trailing underscores (if any) */
+		for (i = 3; i > 1; i--) {
+			if (bus_id[i] == '_')
+				bus_id[i] = '\0';
+			else
+				break;
+		}
+		sprintf(device->pnp.bus_id, "%s", bus_id);
+		break;
+	}
+
+	/*
+	 * Hardware ID, Unique ID, & Bus Address
+	 * -------------------------------------
+	 */
+	switch (type) {
+	case ACPI_BUS_TYPE_DEVICE:
+		status = acpi_get_object_info(handle, &info);
+		if (ACPI_FAILURE(status)) {
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+				"Error reading device info\n"));
+			result = -ENODEV;
+			goto end;
+		}
+		/* Clean up info strings (not NULL terminated) */
+		info.hardware_id[sizeof(info.hardware_id)-1] = '\0';
+		info.unique_id[sizeof(info.unique_id)-1] = '\0';
+		if (info.valid & ACPI_VALID_HID)
+			hid = info.hardware_id;
+		if (info.valid & ACPI_VALID_UID)
+			uid = info.unique_id;
+		if (info.valid & ACPI_VALID_ADR)
+			device->pnp.bus_address = info.address;
+		break;
+	case ACPI_BUS_TYPE_POWER:
+		hid = ACPI_POWER_HID;
+		break;
+	case ACPI_BUS_TYPE_PROCESSOR:
+		hid = ACPI_PROCESSOR_HID;
+		break;
+	case ACPI_BUS_TYPE_SYSTEM:
+		hid = ACPI_SYSTEM_HID;
+		break;
+	case ACPI_BUS_TYPE_THERMAL:
+		hid = ACPI_THERMAL_HID;
+		break;
+	case ACPI_BUS_TYPE_POWER_BUTTON:
+		hid = ACPI_BUTTON_HID_POWERF;
+		break;
+	case ACPI_BUS_TYPE_SLEEP_BUTTON:
+		hid = ACPI_BUTTON_HID_SLEEPF;
+		break;
+	}
+
+	sprintf(device->pnp.hardware_id, "%s", hid);
+	sprintf(device->pnp.unique_id, "%s", uid);
+
+	/*
+	 * Power Management
+	 * ----------------
+	 */
+	if (device->flags.power_manageable) {
+		result = acpi_bus_get_power_flags(device);
+		if (0 != result)
+			goto end;
+	}
+
+	/*
+	 * Performance Management
+	 * ----------------------
+	 */
+	if (device->flags.performance_manageable) {
+		result = acpi_bus_get_perf_flags(device);
+		if (0 != result)
+			goto end;
+	}
+
+	/*
+	 * Context
+	 * -------
+	 * Attach this 'struct acpi_device' to the ACPI object.  This makes
+	 * resolutions from handle->device very efficient.  Note that since we
+	 * attach multiple context to the root object (system device plus all
+	 * fixed-feature devices) we must use alternate handlers.
+	 */
+	switch (type) {
+	case ACPI_BUS_TYPE_POWER_BUTTON:
+		status = acpi_attach_data(device->handle,
+			acpi_bus_data_handler_powerf, device);
+		break;
+	case ACPI_BUS_TYPE_SLEEP_BUTTON:
+		status = acpi_attach_data(device->handle,
+			acpi_bus_data_handler_sleepf, device);
+		break;
+	default:
+		status = acpi_attach_data(device->handle,
+			acpi_bus_data_handler, device);
+		break;
+	}
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error attaching device data\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	/*
+	 * Linkage
+	 * -------
+	 * Link this device to its parent and siblings.
+	 */
+	INIT_LIST_HEAD(&device->children);
+	if (!device->parent)
+		INIT_LIST_HEAD(&device->node);
+	else
+		list_add_tail(&device->node, &device->parent->children);
+
+	/* 
+	 * \_SB
+	 * ----
+	 * Fix for the system root bus device -- the only root-level device.
+	 */
+	if ((type == ACPI_BUS_TYPE_DEVICE) && (parent == ACPI_ROOT_OBJECT)) {
+		sprintf(device->pnp.hardware_id, "%s", ACPI_BUS_HID);
+		sprintf(device->pnp.device_name, "%s", ACPI_BUS_DEVICE_NAME);
+		sprintf(device->pnp.device_class, "%s", ACPI_BUS_CLASS);
+	}
+
+#ifdef CONFIG_ACPI_DEBUG
+	{
+		char		*type_string = NULL;
+		char		*message = NULL;
+		char		name[80] = {'?','\0'};
+		acpi_buffer	buffer = {sizeof(name), name};
+
+		acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
+
+		switch (type) {
+		case ACPI_BUS_TYPE_DEVICE:
+			type_string = "Device";
+			break;
+		case ACPI_BUS_TYPE_POWER:
+			type_string = "Power Resource";
+			break;
+		case ACPI_BUS_TYPE_PROCESSOR:
+			type_string = "Processor";
+			break;
+		case ACPI_BUS_TYPE_SYSTEM:
+			type_string = "System";
+			break;
+		case ACPI_BUS_TYPE_THERMAL:
+			type_string = "Thermal Zone";
+			break;
+		case ACPI_BUS_TYPE_POWER_BUTTON:
+			type_string = "Power Button";
+			sprintf(name, "PWRB");
+			break;
+		case ACPI_BUS_TYPE_SLEEP_BUTTON:
+			type_string = "Sleep Button";
+			sprintf(name, "SLPB");
+			break;
+		}
+
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %s %s [%p]\n", 
+			type_string, name, handle));
+	}
+#endif
+
+	/*
+	 * Global Device Hierarchy:
+	 * ------------------------
+	 * Register this device with the global device hierarchy.
+	 */
+	acpi_device_register(device, parent);
+
+	/*
+	 * Find Driver
+	 * -----------
+	 * Check to see if there's a driver installed for this kind of device.
+	 */
+	acpi_bus_find_driver(device);
+
+end:
+
+	if (0 != result) {
+		kfree(device);
+		return_VALUE(result);
+	}
+
+	*child = device;
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_bus_remove (
+	struct acpi_device	*device, 
+	int			type)
+{
+	ACPI_FUNCTION_TRACE("acpi_bus_remove");
+
+	if (!device)
+		return_VALUE(-ENODEV);
+
+	acpi_device_unregister(device);
+
+	kfree(device);
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_bus_scan (
+	struct acpi_device	*start)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_device	*parent = NULL;
+	struct acpi_device	*child = NULL;
+	acpi_handle		phandle = 0;
+	acpi_handle		chandle = 0;
+	acpi_object_type	type = 0;
+	u32			level = 1;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_scan");
+
+	if (!start)
+		return_VALUE(-EINVAL);
+
+	parent = start;
+	phandle = start->handle;
+	
+	/*
+	 * Parse through the ACPI namespace, identify all 'devices', and
+	 * create a new 'struct acpi_device' for each.
+	 */
+	while ((level > 0) && parent) {
+
+		status = acpi_get_next_object(ACPI_TYPE_ANY, phandle,
+			chandle, &chandle);
+
+		/*
+		 * If this scope is exhausted then move our way back up.
+		 */
+		if (ACPI_FAILURE(status)) {
+			level--;
+			chandle = phandle;
+			acpi_get_parent(phandle, &phandle);
+			if (parent->parent)
+				parent = parent->parent;
+			continue;
+		}
+
+		status = acpi_get_type(chandle, &type);
+		if (ACPI_FAILURE(status))
+			continue;
+
+		/*
+		 * If this is a scope object then parse it (depth-first).
+		 */
+		if (type == ACPI_TYPE_ANY) {
+			/* Hack to get around scope identity problem */
+			status = acpi_get_next_object(ACPI_TYPE_ANY, chandle, 0, NULL);
+			if (ACPI_SUCCESS(status)) {
+				level++;
+				phandle = chandle;
+				chandle = 0;
+			}
+			continue;
+		}
+
+		/*
+		 * We're only interested in objects that we consider 'devices'.
+		 */
+		switch (type) {
+		case ACPI_TYPE_DEVICE:
+			type = ACPI_BUS_TYPE_DEVICE;
+			break;
+		case ACPI_TYPE_PROCESSOR:
+			type = ACPI_BUS_TYPE_PROCESSOR;
+			break;
+		case ACPI_TYPE_THERMAL:
+			type = ACPI_BUS_TYPE_THERMAL;
+			break;
+		case ACPI_TYPE_POWER:
+			type = ACPI_BUS_TYPE_POWER;
+			break;
+		default:
+			continue;
+		}
+
+		status = acpi_bus_add(&child, parent, chandle, type);
+		if (ACPI_FAILURE(status))
+			continue;
+
+		/*
+		 * If the device is present, enabled, and functioning then
+		 * parse its scope (depth-first).  Note that we need to
+		 * represent absent devices to facilitate PnP notifications
+		 * -- but we only the subtree head (not all of its children,
+		 * which will be enumerated when the parent is inserted).
+		 *
+		 * TBD: Need notifications and other detection mechanisms
+		 *	in place before we can fully implement this.
+		 *
+		 * if (STRUCT_TO_INT(child->status) & 0x0B) {
+		 */
+		if (child->status.present) {
+			status = acpi_get_next_object(ACPI_TYPE_ANY, chandle,
+				0, NULL);
+			if (ACPI_SUCCESS(status)) {
+				level++;
+				phandle = chandle;
+				chandle = 0;
+				parent = child;
+			}
+		}
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_bus_scan_fixed (
+	struct acpi_device	*root)
+{
+	int			result = 0;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_scan");
+
+	if (!root)
+		return_VALUE(-ENODEV);
+
+	/*
+	 * Enumerate all fixed-feature devices.
+	 */
+	if (acpi_fadt.pwr_button == 0)
+		result = acpi_bus_add(&device, acpi_root, 
+			ACPI_ROOT_OBJECT, ACPI_BUS_TYPE_POWER_BUTTON);
+
+	if (acpi_fadt.sleep_button == 0)
+		result = acpi_bus_add(&device, acpi_root, 
+			ACPI_ROOT_OBJECT, ACPI_BUS_TYPE_SLEEP_BUTTON);
+
+	return_VALUE(result);
+}
+
+
+/* --------------------------------------------------------------------------
+                             Initialization/Cleanup
+   -------------------------------------------------------------------------- */
+
+int __init
+acpi_blacklisted(void)
+{
+	int i = 0;
+	int blacklisted = 0;
+	acpi_table_header table_header;
+
+	while (acpi_blacklist[i].oem_id[0] != '\0')
+	{
+		if (!ACPI_SUCCESS(acpi_get_table_header(acpi_blacklist[i].table, 1, &table_header))) {
+			i++;
+			continue;
+		}
+
+		if (strncmp(acpi_blacklist[i].oem_id, table_header.oem_id, 6)) {
+			i++;
+			continue;
+		}
+
+		if (strncmp(acpi_blacklist[i].oem_table_id, table_header.oem_table_id, 8)) {
+			i++;
+			continue;
+		}
+
+		if ((acpi_blacklist[i].oem_revision_predicate == all_versions)
+		    || (acpi_blacklist[i].oem_revision_predicate == less_than_or_equal
+		        && table_header.oem_revision <= acpi_blacklist[i].oem_revision)
+		    || (acpi_blacklist[i].oem_revision_predicate == greater_than_or_equal
+		        && table_header.oem_revision >= acpi_blacklist[i].oem_revision)
+		    || (acpi_blacklist[i].oem_revision_predicate == equal
+		        && table_header.oem_revision == acpi_blacklist[i].oem_revision)) {
+
+			printk(KERN_ERR PREFIX "Vendor \"%6.6s\" System \"%8.8s\" "
+				"Revision 0x%x has a known ACPI BIOS problem.\n",
+				acpi_blacklist[i].oem_id,
+				acpi_blacklist[i].oem_table_id,
+				acpi_blacklist[i].oem_revision);
+
+			printk(KERN_ERR PREFIX "Reason: %s. This is a %s error\n",
+				acpi_blacklist[i].reason,
+				(acpi_blacklist[i].is_critical_error ? "non-recoverable" : "recoverable"));
+
+			blacklisted = acpi_blacklist[i].is_critical_error;
+			break;
+		}
+		else {
+			i++;
+		}
+	}
+
+	return blacklisted;
+}
+
+
+static int __init
+acpi_bus_init (void)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	acpi_buffer		buffer = {sizeof(acpi_fadt), &acpi_fadt};
+	int			progress = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_init");
+
+	/*
+	 * [0] Initailize the ACPI Core Subsystem.
+	 */
+	status = acpi_initialize_subsystem();
+	if (ACPI_FAILURE(status)) {
+		printk(KERN_ERR PREFIX "Unable to initialize the ACPI Interpreter\n");
+		result = -ENODEV;
+		goto end;
+	}
+
+	progress++;
+
+	/*
+	 * [1] Load the ACPI tables.
+	 */
+	status = acpi_load_tables();
+	if (ACPI_FAILURE(status)) {
+		printk(KERN_ERR PREFIX "Unable to load the System Description Tables\n");
+		result = -ENODEV;
+		goto end;
+	}
+
+	progress++;
+
+	/*
+	 * [2] Check the blacklist
+	 */
+	if (acpi_blacklisted()) {
+		result = -ENODEV;
+		goto end;
+	}
+
+	progress++;
+
+	/*
+	 * [2] Get a separate copy of the FADT for use by other drivers.
+	 */
+	status = acpi_get_table(ACPI_TABLE_FADT, 1, &buffer);
+	if (ACPI_FAILURE(status)) {
+		printk(KERN_ERR PREFIX "Unable to get the FADT\n");
+		result = -ENODEV;
+		goto end;
+	}
+
+	progress++;
+
+	/*
+	 * [3] Enable the ACPI Core Subsystem.
+	 */
+	status = acpi_enable_subsystem(ACPI_FULL_INITIALIZATION);
+	if (ACPI_FAILURE(status)) {
+		printk(KERN_ERR PREFIX "Unable to start the ACPI Interpreter\n");
+		result = -ENODEV;
+		goto end;
+	}
+
+	printk(KERN_INFO PREFIX "Interpreter enabled\n");
+
+	progress++;
+
+	/*
+	 * [4] Register for all standard device notifications.
+	 */
+	status = acpi_install_notify_handler(ACPI_ROOT_OBJECT, ACPI_SYSTEM_NOTIFY, &acpi_bus_notify, NULL);
+	if (ACPI_FAILURE(status)) {
+		printk(KERN_ERR PREFIX "Unable to register for device notifications\n");
+		result = -ENODEV;
+		goto end;
+	}
+
+	progress++;
+
+	/*
+	 * [5] Create the root device.
+	 */
+	result = acpi_bus_add(&acpi_root, NULL, ACPI_ROOT_OBJECT, 
+		ACPI_BUS_TYPE_SYSTEM);
+	if (0 != result)
+		goto end;
+
+	progress++;
+
+	/*
+	 * [6] Create the root file system.
+	 */
+	acpi_device_dir(acpi_root) = proc_mkdir(ACPI_BUS_FILE_ROOT, NULL);
+	if (!acpi_root) {
+		result = -ENODEV;
+		goto end;
+	}
+	acpi_root_dir = acpi_device_dir(acpi_root);
+
+	progress++;
+
+	/*
+	 * [7] Install drivers required for proper enumeration of the
+	 *     ACPI namespace.
+	 */
+	acpi_system_init();	/* ACPI System */
+	acpi_power_init();	/* ACPI Bus Power Management */
+#ifdef CONFIG_ACPI_EC
+	acpi_ec_init();		/* ACPI Embedded Controller */
+#endif
+#ifdef CONFIG_ACPI_PCI
+	acpi_pci_link_init();	/* ACPI PCI Interrupt Link */
+	acpi_pci_root_init();	/* ACPI PCI Root Bridge */
+#endif
+	progress++;
+
+	/*
+	 * [8] Enumerate devices in the ACPI namespace.
+	 */
+
+	result = acpi_bus_scan_fixed(acpi_root);
+	if (0 != result)
+		goto end;
+
+	result = acpi_bus_scan(acpi_root);
+	if (0 != result)
+		goto end;
+
+end:
+	if (0 != result) {
+		switch (progress) {
+		case 9:
+		case 8: remove_proc_entry("ACPI", NULL);
+		case 7: acpi_bus_remove(acpi_root, ACPI_BUS_REMOVAL_NORMAL);
+		case 6: acpi_remove_notify_handler(ACPI_ROOT_OBJECT,
+				ACPI_SYSTEM_NOTIFY, &acpi_bus_notify);
+		case 5:
+		case 4:
+		case 3:
+		case 2: acpi_terminate();
+		case 1:
+		case 0:
+		default: return_VALUE(-ENODEV);
+		}
+	}
+
+	return_VALUE(0);
+}
+
+
+static void __exit
+acpi_bus_exit (void)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_bus_exit");
+
+	status = acpi_remove_notify_handler(ACPI_ROOT_OBJECT,
+		ACPI_SYSTEM_NOTIFY, acpi_bus_notify);
+	if (ACPI_FAILURE(status))
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error removing notify handler\n"));
+
+#ifdef CONFIG_ACPI_PCI
+	acpi_pci_root_exit();
+	acpi_pci_link_exit();
+#endif
+#ifdef CONFIG_ACPI_EC
+	acpi_ec_exit();
+#endif
+	acpi_power_exit();
+	acpi_system_exit();
+
+	acpi_bus_remove(acpi_root, ACPI_BUS_REMOVAL_NORMAL);
+
+	remove_proc_entry(ACPI_BUS_FILE_ROOT, NULL);
+
+	status = acpi_terminate();
+	if (ACPI_FAILURE(status))
+		printk(KERN_ERR PREFIX "Unable to terminate the ACPI Interpreter\n");
+	else
+		printk(KERN_ERR PREFIX "Interpreter disabled\n");
+
+	return_VOID;
+}
+
+
+int __init
+acpi_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_init");
+
+	printk(KERN_INFO PREFIX "Bus Driver revision %08x\n",
+		ACPI_DRIVER_VERSION);
+	printk(KERN_INFO PREFIX "Core Subsystem revision %08x\n",
+		ACPI_CA_VERSION);
+
+	if (acpi_disabled) {
+		printk(KERN_INFO PREFIX "Disabled via command line (acpi=off)\n");
+		return -ENODEV;
+	}
+
+#ifdef CONFIG_PM
+	if (PM_IS_ACTIVE()) {
+		printk(KERN_INFO PREFIX "APM is already active, exiting\n");
+		return -ENODEV;
+	}
+#endif
+
+	result = acpi_bus_init();
+	if (0 != result)
+		return_VALUE(result);
+
+#ifdef CONFIG_PM
+	pm_active = 1;
+#endif
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_exit (void)
+{
+	ACPI_FUNCTION_TRACE("acpi_exit");
+
+#ifdef CONFIG_PM
+	pm_active = 0;
+#endif
+
+	acpi_bus_exit();
+
+	return_VOID;
+}
+
+
+int __init
+acpi_setup(char *str)
+{
+	while (str && *str) {
+		if (strncmp(str, "off", 3) == 0)
+			acpi_disabled = 1;
+		str = strchr(str, ',');
+		if (str)
+			str += strspn(str, ", \t");
+	}
+	return 1;
+}
+
+
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
+subsys_initcall(acpi_init);
+#endif
+
+__setup("acpi=", acpi_setup);
diff -Nru a/drivers/acpi/acpi_bus.h b/drivers/acpi/acpi_bus.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_bus.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,316 @@
+/*
+ *  acpi_bus.h - ACPI Bus Driver ($Revision: 17 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#ifndef __ACPI_BUS_H__
+#define __ACPI_BUS_H__
+
+#include <linux/version.h>
+
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,4))
+#include <linux/device.h>
+#define CONFIG_LDM
+#endif
+
+#include "include/acpi.h"
+
+
+/* TBD: Make dynamic */
+#define ACPI_MAX_HANDLES	10
+struct acpi_handle_list {
+	u32			count;
+	acpi_handle		handles[ACPI_MAX_HANDLES];
+};
+
+
+/* acpi_utils.h */
+acpi_status acpi_extract_package (acpi_object *, acpi_buffer *, acpi_buffer *);
+acpi_status acpi_evaluate (acpi_handle, acpi_string, acpi_object_list *, acpi_buffer *);
+acpi_status acpi_evaluate_integer (acpi_handle, acpi_string, acpi_object_list *, unsigned long *);
+acpi_status acpi_evaluate_reference (acpi_handle, acpi_string, acpi_object_list *, struct acpi_handle_list *);
+
+
+#ifdef CONFIG_ACPI_BUS
+
+#include <linux/proc_fs.h>
+
+#define ACPI_BUS_FILE_ROOT	"acpi"
+
+extern struct proc_dir_entry	*acpi_root_dir;
+
+extern FADT_DESCRIPTOR		acpi_fadt;
+
+enum acpi_bus_removal_type {
+	ACPI_BUS_REMOVAL_NORMAL	= 0,
+	ACPI_BUS_REMOVAL_EJECT,
+	ACPI_BUS_REMOVAL_SUPRISE,
+	ACPI_BUS_REMOVAL_TYPE_COUNT
+};
+
+enum acpi_bus_device_type {
+	ACPI_BUS_TYPE_DEVICE	= 0,
+	ACPI_BUS_TYPE_POWER,
+	ACPI_BUS_TYPE_PROCESSOR,
+	ACPI_BUS_TYPE_THERMAL,
+	ACPI_BUS_TYPE_SYSTEM,
+	ACPI_BUS_TYPE_POWER_BUTTON,
+	ACPI_BUS_TYPE_SLEEP_BUTTON,
+	ACPI_BUS_DEVICE_TYPE_COUNT
+};
+
+struct acpi_driver;
+struct acpi_device;
+
+
+/*
+ * ACPI Driver
+ * -----------
+ */
+
+typedef int (*acpi_op_add)	(struct acpi_device *device);
+typedef int (*acpi_op_remove)	(struct acpi_device *device, int type);
+typedef int (*acpi_op_lock)	(struct acpi_device *device, int type);
+typedef int (*acpi_op_start)	(struct acpi_device *device);
+typedef int (*acpi_op_stop)	(struct acpi_device *device, int type);
+typedef int (*acpi_op_suspend)	(struct acpi_device *device, int state);
+typedef int (*acpi_op_resume)	(struct acpi_device *device, int state);
+typedef int (*acpi_op_scan)	(struct acpi_device *device);
+
+struct acpi_driver_ops {
+	acpi_op_add		add;
+	acpi_op_remove		remove;
+	acpi_op_lock		lock;
+	acpi_op_start		start;
+	acpi_op_stop		stop;
+	acpi_op_suspend		suspend;
+	acpi_op_resume		resume;
+	acpi_op_scan		scan;
+};
+
+struct acpi_driver {
+	struct list_head	node;
+	char			name[80];
+	char			class[80];
+	int			references;
+	char			*ids;		/* Supported Hardware IDs */
+	struct acpi_driver_ops	ops;
+};
+
+enum acpi_blacklist_predicates
+{
+	all_versions,
+	less_than_or_equal,
+	equal,
+	greater_than_or_equal,
+};
+
+struct acpi_blacklist_item
+{
+	char		oem_id[7];
+	char		oem_table_id[9];
+	u32		oem_revision;
+	acpi_table_type table;
+	enum acpi_blacklist_predicates oem_revision_predicate;
+	char		*reason;
+	u32		is_critical_error;
+};
+
+
+/*
+ * ACPI Device
+ * -----------
+ */
+
+/* Status (_STA) */
+
+struct acpi_device_status {
+	u32			present:1;
+	u32			enabled:1;
+	u32			show_in_ui:1;
+	u32			functional:1;
+	u32			battery_present:1;
+	u32			reserved:27;
+};
+
+
+/* Flags */
+
+struct acpi_device_flags {
+	u8			dynamic_status:1;
+	u8			compatible_ids:1;
+	u8			removable:1;
+	u8			ejectable:1;
+	u8			lockable:1;
+	u8			suprise_removal_ok:1;
+	u8			power_manageable:1;
+	u8			performance_manageable:1;
+};
+
+
+/* File System */
+
+struct acpi_device_dir {
+	struct proc_dir_entry	*entry;
+};
+
+#define acpi_device_dir(d)	((d)->dir.entry)
+
+
+/* Plug and Play */
+
+typedef char			acpi_bus_id[5];
+typedef unsigned long		acpi_bus_address;
+typedef char			acpi_hardware_id[9];
+typedef char			acpi_unique_id[9];
+typedef char			acpi_device_name[40];
+typedef char			acpi_device_class[20];
+
+struct acpi_device_pnp {
+	acpi_bus_id		bus_id;		               /* Object name */
+	acpi_bus_address	bus_address;	                      /* _ADR */
+	acpi_hardware_id	hardware_id;	                      /* _HID */
+	acpi_unique_id		unique_id;	                      /* _UID */
+	acpi_device_name	device_name;	         /* Driver-determined */
+	acpi_device_class	device_class;	         /*        "          */
+};
+
+#define acpi_device_bid(d)	((d)->pnp.bus_id)
+#define acpi_device_adr(d)	((d)->pnp.bus_address)
+#define acpi_device_hid(d)	((d)->pnp.hardware_id)
+#define acpi_device_uid(d)	((d)->pnp.unique_id)
+#define acpi_device_name(d)	((d)->pnp.device_name)
+#define acpi_device_class(d)	((d)->pnp.device_class)
+
+
+/* Power Management */
+
+struct acpi_device_power_flags {
+	u8			explicit_get:1;		     /* _PSC present? */
+	u8			power_resources:1;	   /* Power resources */
+	u8			inrush_current:1;	  /* Serialize Dx->D0 */
+	u8			wake_capable:1;		 /* Wakeup supported? */
+	u8			wake_enabled:1;		/* Enabled for wakeup */
+	u8			power_removed:1;	   /* Optimize Dx->D0 */
+	u8			reserved:2;
+};
+
+struct acpi_device_power_state {
+	struct {
+		u8			valid:1;	
+		u8			explicit_set:1;	     /* _PSx present? */
+		u8			reserved:6;
+	}			flags;
+	int			power;		  /* % Power (compared to D0) */
+	int			latency;	/* Dx->D0 time (microseconds) */
+	struct acpi_handle_list	resources;	/* Power resources referenced */
+};
+
+struct acpi_device_power {
+	int			state;		             /* Current state */
+	struct acpi_device_power_flags flags;
+	struct acpi_device_power_state states[4];     /* Power states (D0-D3) */
+};
+
+
+/* Performance Management */
+
+struct acpi_device_perf_flags {
+	u8			reserved:8;
+};
+
+struct acpi_device_perf_state {
+	struct {
+		u8			valid:1;	
+		u8			reserved:7;
+	}			flags;
+	u8			power;		  /* % Power (compared to P0) */
+	u8			performance;	  /* % Performance (    "   ) */
+	int			latency;	/* Px->P0 time (microseconds) */
+};
+
+struct acpi_device_perf {
+	int			state;
+	struct acpi_device_perf_flags flags;
+	int			state_count;
+	struct acpi_device_perf_state *states;
+};
+
+
+/* Device */
+
+struct acpi_device {
+	acpi_handle		handle;
+	struct acpi_device	*parent;
+	struct list_head	children;
+	struct list_head	node;
+	struct acpi_device_status status;
+	struct acpi_device_flags flags;
+	struct acpi_device_pnp	pnp;
+	struct acpi_device_power power;
+	struct acpi_device_perf	performance;
+	struct acpi_device_dir	dir;
+	struct acpi_driver	*driver;
+	void			*driver_data;
+#ifdef CONFIG_LDM
+	struct device		dev;
+#endif
+};
+
+#define acpi_driver_data(d)	((d)->driver_data)
+
+
+/*
+ * Events
+ * ------
+ */
+
+struct acpi_bus_event {
+	struct list_head	node;
+	acpi_device_class	device_class;
+	acpi_bus_id		bus_id;
+	u32			type;
+	u32			data;
+};
+
+
+/*
+ * External Functions
+ */
+
+int acpi_bus_get_device(acpi_handle, struct acpi_device **device);
+int acpi_bus_get_status (struct acpi_device *device);
+int acpi_bus_get_power (acpi_handle handle, int *state);
+int acpi_bus_set_power (acpi_handle handle, int state);
+int acpi_bus_generate_event (struct acpi_device *device, u8 type, int data);
+int acpi_bus_receive_event (struct acpi_bus_event *event);
+int acpi_bus_register_driver (struct acpi_driver *driver);
+int acpi_bus_unregister_driver (struct acpi_driver *driver);
+int acpi_bus_scan (struct acpi_device *device);
+int acpi_init (void);
+void acpi_exit (void);
+
+
+#endif /*CONFIG_ACPI_BUS*/
+
+#endif /*__ACPI_BUS_H__*/
diff -Nru a/drivers/acpi/acpi_button.c b/drivers/acpi/acpi_button.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_button.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,383 @@
+/*
+ *  acpi_button.c - ACPI Button Driver ($Revision: 22 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_BUTTON_COMPONENT
+ACPI_MODULE_NAME		("acpi_button")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_BUTTON_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define PREFIX			"ACPI: "
+
+
+int acpi_button_add (struct acpi_device *device);
+int acpi_button_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_button_driver = {
+	name:			ACPI_BUTTON_DRIVER_NAME,
+	class:			ACPI_BUTTON_CLASS,
+	ids:			"ACPI_FPB,ACPI_FSB,PNP0C0D,PNP0C0C,PNP0C0E",
+	ops:			{
+					add:	acpi_button_add,
+					remove:	acpi_button_remove,
+				},
+};
+
+struct acpi_button {
+	acpi_handle		handle;
+	struct acpi_device	*device;	/* Fixed button kludge */
+	u8			type;
+	unsigned long		pushed;
+};
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_button_dir = NULL;
+
+
+static int
+acpi_button_read_info (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_button	*button = (struct acpi_button *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_button_read_info");
+
+	if (!button || !button->device)
+		goto end;
+
+	p += sprintf(p, "type:                    %s\n", 
+		acpi_device_name(button->device));
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_button_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_button_add_fs");
+
+	if (!acpi_button_dir) {
+		acpi_button_dir = proc_mkdir(ACPI_BUTTON_CLASS, acpi_root_dir);
+		if (!acpi_button_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_button_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'info' [R] */
+	entry = create_proc_entry(ACPI_BUTTON_FILE_INFO,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_BUTTON_FILE_INFO));
+	else {
+		entry->read_proc = acpi_button_read_info;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_button_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_button_remove_fs");
+
+	if (!acpi_button_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_button_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                Driver Interface
+   -------------------------------------------------------------------------- */
+
+void
+acpi_button_notify (
+	acpi_handle		handle,
+	u32			event,
+	void			*data)
+{
+	struct acpi_button	*button = (struct acpi_button *) data;
+
+	ACPI_FUNCTION_TRACE("acpi_button_notify");
+
+	if (!button || !button->device)
+		return_VOID;
+
+	switch (event) {
+	case ACPI_BUTTON_NOTIFY_STATUS:
+		acpi_bus_generate_event(button->device, event, ++button->pushed);
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"Unsupported event [0x%x]\n", event));
+		break;
+	}
+
+	return_VOID;
+}
+
+
+acpi_status
+acpi_button_notify_fixed (
+	void			*data)
+{
+	struct acpi_button	*button = (struct acpi_button *) data;
+	
+	ACPI_FUNCTION_TRACE("acpi_button_notify_fixed");
+
+	if (!button)
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+
+	acpi_button_notify(button->handle, ACPI_BUTTON_NOTIFY_STATUS, button);
+
+	return_ACPI_STATUS(AE_OK);
+}
+
+
+int
+acpi_button_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_button	*button = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_button_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	button = kmalloc(sizeof(struct acpi_button), GFP_KERNEL);
+	if (!button)
+		return_VALUE(-ENOMEM);
+	memset(button, 0, sizeof(struct acpi_button));
+
+	button->device = device;
+	button->handle = device->handle;
+	sprintf(acpi_device_class(device), "%s", ACPI_BUTTON_CLASS);
+	acpi_driver_data(device) = button;
+
+	/*
+	 * Determine the button type (via hid), as fixed-feature buttons
+	 * need to be handled a bit differently than generic-space.
+	 */
+	if (!strcmp(acpi_device_hid(device), ACPI_BUTTON_HID_POWERF)) {
+		button->type = ACPI_BUTTON_TYPE_POWERF;
+		sprintf(acpi_device_name(device), "%s",
+			ACPI_BUTTON_DEVICE_NAME_POWERF);
+	}
+	else if (!strcmp(acpi_device_hid(device), ACPI_BUTTON_HID_SLEEPF)) {
+		button->type = ACPI_BUTTON_TYPE_SLEEPF;
+		sprintf(acpi_device_name(device), "%s",
+			ACPI_BUTTON_DEVICE_NAME_SLEEPF);
+	}
+	else if (!strcmp(acpi_device_hid(device), ACPI_BUTTON_HID_POWER)) {
+		button->type = ACPI_BUTTON_TYPE_POWER;
+		sprintf(acpi_device_name(device), "%s",
+			ACPI_BUTTON_DEVICE_NAME_POWER);
+	}
+	else if (!strcmp(acpi_device_hid(device), ACPI_BUTTON_HID_SLEEP)) {
+		button->type = ACPI_BUTTON_TYPE_SLEEP;
+		sprintf(acpi_device_name(device), "%s",
+			ACPI_BUTTON_DEVICE_NAME_SLEEP);
+	}
+	else if (!strcmp(acpi_device_hid(device), ACPI_BUTTON_HID_LID)) {
+		button->type = ACPI_BUTTON_TYPE_LID;
+		sprintf(acpi_device_name(device), "%s",
+			ACPI_BUTTON_DEVICE_NAME_LID);
+	}
+	else {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Unsupported hid [%s]\n",
+			acpi_device_hid(device)));
+		result = -ENODEV;
+		goto end;
+	}
+
+	result = acpi_button_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	switch (button->type) {
+	case ACPI_BUTTON_TYPE_POWERF:
+		status = acpi_install_fixed_event_handler (
+			ACPI_EVENT_POWER_BUTTON,
+			acpi_button_notify_fixed,
+			button);
+		break;
+	case ACPI_BUTTON_TYPE_SLEEPF:
+		status = acpi_install_fixed_event_handler (
+			ACPI_EVENT_SLEEP_BUTTON,
+			acpi_button_notify_fixed,
+			button);
+		break;
+	default:
+		status = acpi_install_notify_handler (
+			button->handle,
+			ACPI_DEVICE_NOTIFY,
+			acpi_button_notify,
+			button);
+		break;
+	}
+
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error installing notify handler\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	printk(KERN_INFO PREFIX "%s [%s]\n", 
+		acpi_device_name(device), acpi_device_bid(device));
+
+end:
+	if (0 != result) {
+		acpi_button_remove_fs(device);
+		kfree(button);
+	}
+
+	return_VALUE(result);
+}
+
+
+int
+acpi_button_remove (struct acpi_device *device, int type)
+{
+	acpi_status		status = 0;
+	struct acpi_button	*button = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_button_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	button = acpi_driver_data(device);
+
+	/* Unregister for device notifications. */
+	switch (button->type) {
+	case ACPI_BUTTON_TYPE_POWERF:
+		status = acpi_remove_fixed_event_handler(
+			ACPI_EVENT_POWER_BUTTON, acpi_button_notify_fixed);
+		break;
+	case ACPI_BUTTON_TYPE_SLEEPF:
+		status = acpi_remove_fixed_event_handler(
+			ACPI_EVENT_SLEEP_BUTTON, acpi_button_notify_fixed);
+		break;
+	default:
+		status = acpi_remove_notify_handler(button->handle,
+			ACPI_DEVICE_NOTIFY, acpi_button_notify);
+		break;
+	}
+
+	if (ACPI_FAILURE(status))
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error removing notify handler\n"));
+
+	acpi_button_remove_fs(device);	
+
+	kfree(button);
+
+	return_VALUE(0);
+}
+
+
+static int __init
+acpi_button_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_button_init");
+
+	result = acpi_bus_register_driver(&acpi_button_driver);
+	if (0 > result)
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+static void __exit
+acpi_button_exit (void)
+{
+	ACPI_FUNCTION_TRACE("acpi_button_exit");
+
+	acpi_bus_unregister_driver(&acpi_button_driver);
+
+	return_VOID;
+}
+
+
+module_init(acpi_button_init);
+module_exit(acpi_button_exit);
diff -Nru a/drivers/acpi/acpi_drivers.h b/drivers/acpi/acpi_drivers.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_drivers.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,328 @@
+/*
+ *  acpi_drivers.h  ($Revision: 17 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#ifndef __ACPI_DRIVERS_H__
+#define __ACPI_DRIVERS_H__
+
+#include <linux/acpi.h>
+#include "acpi_bus.h"
+
+
+#define ACPI_DRIVER_VERSION		0x20020308
+#define ACPI_MAX_STRING			80
+
+
+/* --------------------------------------------------------------------------
+                                    ACPI Bus
+   -------------------------------------------------------------------------- */
+
+#define ACPI_BUS_COMPONENT		0x00010000
+#define ACPI_BUS_CLASS			"system_bus"
+#define ACPI_BUS_HID			"ACPI_BUS"
+#define ACPI_BUS_DRIVER_NAME		"ACPI Bus Driver"
+#define ACPI_BUS_DEVICE_NAME		"System Bus"
+
+
+/* --------------------------------------------------------------------------
+                                  AC Adapter
+   -------------------------------------------------------------------------- */
+
+#define ACPI_AC_COMPONENT		0x00020000
+#define ACPI_AC_CLASS			"ac_adapter"
+#define ACPI_AC_HID 			"ACPI0003"
+#define ACPI_AC_DRIVER_NAME		"ACPI AC Adapter Driver"
+#define ACPI_AC_DEVICE_NAME		"AC Adapter"
+#define ACPI_AC_FILE_STATE		"state"
+#define ACPI_AC_NOTIFY_STATUS		0x80
+#define ACPI_AC_STATUS_OFFLINE		0x00
+#define ACPI_AC_STATUS_ONLINE		0x01
+#define ACPI_AC_STATUS_UNKNOWN		0xFF
+
+
+/* --------------------------------------------------------------------------
+                                     Battery
+   -------------------------------------------------------------------------- */
+
+#define ACPI_BATTERY_COMPONENT		0x00040000
+#define ACPI_BATTERY_CLASS		"battery"
+#define ACPI_BATTERY_HID		"PNP0C0A"
+#define ACPI_BATTERY_DRIVER_NAME	"ACPI Battery Driver"
+#define ACPI_BATTERY_DEVICE_NAME	"Battery"
+#define ACPI_BATTERY_FILE_INFO		"info"
+#define ACPI_BATTERY_FILE_STATUS	"state"
+#define ACPI_BATTERY_FILE_ALARM		"alarm"
+#define ACPI_BATTERY_NOTIFY_STATUS	0x80
+#define ACPI_BATTERY_NOTIFY_INFO	0x81
+#define ACPI_BATTERY_UNITS_WATTS	"mW"
+#define ACPI_BATTERY_UNITS_AMPS		"mA"
+
+
+/* --------------------------------------------------------------------------
+                                      Button
+   -------------------------------------------------------------------------- */
+
+#define ACPI_BUTTON_COMPONENT		0x00080000
+#define ACPI_BUTTON_CLASS		"button"
+#define ACPI_BUTTON_HID_LID		"PNP0C0D"
+#define ACPI_BUTTON_HID_POWER		"PNP0C0C"	
+#define ACPI_BUTTON_HID_POWERF		"ACPI_FPB"
+#define ACPI_BUTTON_HID_SLEEP		"PNP0C0E"
+#define ACPI_BUTTON_HID_SLEEPF		"ACPI_FSB"
+#define ACPI_BUTTON_DRIVER_NAME		"ACPI Button Driver"
+#define ACPI_BUTTON_DEVICE_NAME_POWER	"Power Button"
+#define ACPI_BUTTON_DEVICE_NAME_POWERF	"Power Button"
+#define ACPI_BUTTON_DEVICE_NAME_SLEEP	"Sleep Button"
+#define ACPI_BUTTON_DEVICE_NAME_SLEEPF	"Sleep Button"
+#define ACPI_BUTTON_DEVICE_NAME_LID	"Lid Switch"
+#define ACPI_BUTTON_FILE_INFO		"info"
+#define ACPI_BUTTON_TYPE_UNKNOWN	0x00
+#define ACPI_BUTTON_TYPE_POWER		0x01
+#define ACPI_BUTTON_TYPE_POWERF		0x02
+#define ACPI_BUTTON_TYPE_SLEEP		0x03
+#define ACPI_BUTTON_TYPE_SLEEPF		0x04
+#define ACPI_BUTTON_TYPE_LID		0x05
+#define ACPI_BUTTON_NOTIFY_STATUS	0x80
+
+
+/* --------------------------------------------------------------------------
+                                Embedded Controller
+   -------------------------------------------------------------------------- */
+
+#define ACPI_EC_COMPONENT		0x00100000
+#define ACPI_EC_CLASS			"embedded_controller"
+#define ACPI_EC_HID			"PNP0C09"
+#define ACPI_EC_DRIVER_NAME		"ACPI Embedded Controller Driver"
+#define ACPI_EC_DEVICE_NAME		"Embedded Controller"
+#define ACPI_EC_FILE_INFO		"info"
+
+#ifdef CONFIG_ACPI_EC
+
+int acpi_ec_init (void);
+void acpi_ec_exit (void);
+
+#endif
+
+
+/* --------------------------------------------------------------------------
+                                       Fan
+   -------------------------------------------------------------------------- */
+
+#define ACPI_FAN_COMPONENT		0x00200000
+#define ACPI_FAN_CLASS			"fan"
+#define ACPI_FAN_HID			"PNP0C0B"
+#define ACPI_FAN_DRIVER_NAME		"ACPI Fan Driver"
+#define ACPI_FAN_DEVICE_NAME		"Fan"
+#define ACPI_FAN_FILE_STATE		"state"
+#define ACPI_FAN_NOTIFY_STATUS		0x80
+
+
+/* --------------------------------------------------------------------------
+                                       PCI
+   -------------------------------------------------------------------------- */
+
+#define ACPI_PCI_LINK_COMPONENT		0x00400000
+#define ACPI_PCI_LINK_CLASS		"irq_routing"
+#define ACPI_PCI_LINK_HID		"PNP0C0F"
+#define ACPI_PCI_LINK_DRIVER_NAME	"ACPI PCI Interrupt Link Driver"
+#define ACPI_PCI_LINK_DEVICE_NAME	"PCI Interrupt Link"
+#define ACPI_PCI_LINK_FILE_INFO		"info"
+#define ACPI_PCI_LINK_FILE_STATUS	"state"
+
+#define ACPI_PCI_ROOT_COMPONENT		0x00800000
+#define ACPI_PCI_ROOT_CLASS		"bridge"
+#define ACPI_PCI_ROOT_HID		"PNP0A03"
+#define ACPI_PCI_ROOT_DRIVER_NAME	"ACPI PCI Root Bridge Driver"
+#define ACPI_PCI_ROOT_DEVICE_NAME	"PCI Root Bridge"
+
+#define ACPI_PCI_PRT_DEVICE_NAME	"PCI Interrupt Routing Table"
+
+#ifdef CONFIG_ACPI_PCI
+
+
+int acpi_pci_link_get_irq (struct acpi_prt_entry *entry, int *irq);
+int acpi_pci_link_set_irq (struct acpi_prt_entry *entry, int irq);
+int acpi_pci_link_init (void);
+void acpi_pci_link_exit (void);
+
+int acpi_pci_root_init (void);
+void acpi_pci_root_exit (void);
+
+#endif
+
+
+/* --------------------------------------------------------------------------
+                                  Power Resource
+   -------------------------------------------------------------------------- */
+
+#define ACPI_POWER_COMPONENT		0x01000000
+#define ACPI_POWER_CLASS		"power_resource"
+#define ACPI_POWER_HID			"ACPI_PWR"
+#define ACPI_POWER_DRIVER_NAME		"ACPI Power Resource Driver"
+#define ACPI_POWER_DEVICE_NAME		"Power Resource"
+#define ACPI_POWER_FILE_INFO		"info"
+#define ACPI_POWER_FILE_STATUS		"state"
+#define ACPI_POWER_RESOURCE_STATE_OFF	0x00
+#define ACPI_POWER_RESOURCE_STATE_ON	0x01
+#define ACPI_POWER_RESOURCE_STATE_UNKNOWN 0xFF
+
+#ifdef CONFIG_ACPI_POWER
+
+int acpi_power_get_inferred_state (struct acpi_device *device);
+int acpi_power_transition (struct acpi_device *device, int state);
+int acpi_power_init (void);
+void acpi_power_exit (void);
+
+#endif
+
+
+/* --------------------------------------------------------------------------
+                                    Processor
+   -------------------------------------------------------------------------- */
+
+#define ACPI_PROCESSOR_COMPONENT	0x02000000
+#define ACPI_PROCESSOR_CLASS		"processor"
+#define ACPI_PROCESSOR_HID		"ACPI_CPU"
+#define ACPI_PROCESSOR_DRIVER_NAME	"ACPI Processor Driver"
+#define ACPI_PROCESSOR_DEVICE_NAME	"Processor"
+#define ACPI_PROCESSOR_FILE_INFO	"info"
+#define ACPI_PROCESSOR_FILE_POWER	"power"
+#define ACPI_PROCESSOR_FILE_PERFORMANCE	"performance"
+#define ACPI_PROCESSOR_FILE_THROTTLING	"throttling"
+#define ACPI_PROCESSOR_FILE_LIMIT	"limit"
+#define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80
+#define ACPI_PROCESSOR_NOTIFY_POWER	0x81
+#define ACPI_PROCESSOR_LIMIT_NONE	0x00
+#define ACPI_PROCESSOR_LIMIT_INCREMENT	0x01
+#define ACPI_PROCESSOR_LIMIT_DECREMENT	0x02
+
+int acpi_processor_set_limit(acpi_handle handle, int flags, int *state);
+
+
+/* --------------------------------------------------------------------------
+                                     System
+   -------------------------------------------------------------------------- */
+
+#define ACPI_SYSTEM_COMPONENT		0x04000000
+#define ACPI_SYSTEM_CLASS		"system"
+#define ACPI_SYSTEM_HID			"ACPI_SYS"
+#define ACPI_SYSTEM_DRIVER_NAME		"ACPI System Driver"
+#define ACPI_SYSTEM_DEVICE_NAME		"System"
+#define ACPI_SYSTEM_FILE_INFO		"info"
+#define ACPI_SYSTEM_FILE_EVENT		"event"
+#define ACPI_SYSTEM_FILE_ALARM		"alarm"
+#define ACPI_SYSTEM_FILE_DSDT		"dsdt"
+#define ACPI_SYSTEM_FILE_FADT		"fadt"
+#define ACPI_SYSTEM_FILE_SLEEP		"sleep"
+#define ACPI_SYSTEM_FILE_DEBUG_LAYER	"debug_layer"
+#define ACPI_SYSTEM_FILE_DEBUG_LEVEL	"debug_level"
+
+#ifdef CONFIG_ACPI_SYSTEM
+
+int acpi_system_init (void);
+void acpi_system_exit (void);
+
+#endif
+
+
+/* --------------------------------------------------------------------------
+                                 Thermal Zone
+   -------------------------------------------------------------------------- */
+
+#define ACPI_THERMAL_COMPONENT		0x08000000
+#define ACPI_THERMAL_CLASS		"thermal_zone"
+#define ACPI_THERMAL_HID		"ACPI_THM"
+#define ACPI_THERMAL_DRIVER_NAME	"ACPI Thermal Zone Driver"
+#define ACPI_THERMAL_DEVICE_NAME	"Thermal Zone"
+#define ACPI_THERMAL_FILE_STATE		"state"
+#define ACPI_THERMAL_FILE_TEMPERATURE	"temperature"
+#define ACPI_THERMAL_FILE_TRIP_POINTS	"trip_points"
+#define ACPI_THERMAL_FILE_COOLING_MODE	"cooling_mode"
+#define ACPI_THERMAL_FILE_POLLING_FREQ	"polling_frequency"
+#define ACPI_THERMAL_NOTIFY_TEMPERATURE	0x80
+#define ACPI_THERMAL_NOTIFY_THRESHOLDS	0x81
+#define ACPI_THERMAL_NOTIFY_DEVICES	0x82
+#define ACPI_THERMAL_NOTIFY_CRITICAL	0xF0
+#define ACPI_THERMAL_NOTIFY_HOT		0xF1
+#define ACPI_THERMAL_MODE_ACTIVE	0x00
+#define ACPI_THERMAL_MODE_PASSIVE	0x01
+#define ACPI_THERMAL_PATH_POWEROFF	"/sbin/poweroff"
+
+
+/* --------------------------------------------------------------------------
+                                Debug Support
+   -------------------------------------------------------------------------- */
+
+#define ACPI_DEBUG_RESTORE	0
+#define ACPI_DEBUG_LOW		1
+#define ACPI_DEBUG_MEDIUM	2
+#define ACPI_DEBUG_HIGH		3
+#define ACPI_DEBUG_DRIVERS	4
+
+extern u32 acpi_dbg_level;
+extern u32 acpi_dbg_layer;
+
+static inline void
+acpi_set_debug (
+	u32			flag)
+{
+	static u32		layer_save;
+	static u32		level_save;
+
+	switch (flag) {
+	case ACPI_DEBUG_RESTORE:
+		acpi_dbg_layer = layer_save;
+		acpi_dbg_level = level_save;
+		break;
+	case ACPI_DEBUG_LOW:
+	case ACPI_DEBUG_MEDIUM:
+	case ACPI_DEBUG_HIGH:
+	case ACPI_DEBUG_DRIVERS:
+		layer_save = acpi_dbg_layer;
+		level_save = acpi_dbg_level;
+		break;
+	}
+
+	switch (flag) {
+	case ACPI_DEBUG_LOW:
+		acpi_dbg_layer = ACPI_COMPONENT_DEFAULT | ACPI_ALL_DRIVERS;
+		acpi_dbg_level = DEBUG_DEFAULT;
+		break;
+	case ACPI_DEBUG_MEDIUM:
+		acpi_dbg_layer = ACPI_COMPONENT_DEFAULT | ACPI_ALL_DRIVERS;
+		acpi_dbg_level = ACPI_LV_FUNCTIONS | ACPI_LV_ALL_EXCEPTIONS;
+		break;
+	case ACPI_DEBUG_HIGH:
+		acpi_dbg_layer = 0xFFFFFFFF;
+		acpi_dbg_level = 0xFFFFFFFF;
+		break;
+	case ACPI_DEBUG_DRIVERS:
+		acpi_dbg_layer = ACPI_ALL_DRIVERS;
+		acpi_dbg_level = 0xFFFFFFFF;
+		break;
+	}
+}
+
+
+#endif /*__ACPI_DRIVERS_H__*/
diff -Nru a/drivers/acpi/acpi_ec.c b/drivers/acpi/acpi_ec.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_ec.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,736 @@
+/*
+ *  acpi_ec.c - ACPI Embedded Controller Driver ($Revision: 27 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_EC_COMPONENT
+ACPI_MODULE_NAME		("acpi_ec")
+
+#define PREFIX			"ACPI: "
+
+
+#define ACPI_EC_FLAG_OBF	0x01	/* Output buffer full */
+#define ACPI_EC_FLAG_IBF	0x02	/* Input buffer full */
+#define ACPI_EC_FLAG_SCI	0x20	/* EC-SCI occurred */
+
+#define ACPI_EC_EVENT_OBF	0x01	/* Output buffer full */
+#define ACPI_EC_EVENT_IBE	0x02	/* Input buffer empty */
+
+#define ACPI_EC_UDELAY		100	/* Poll @ 100us increments */
+#define ACPI_EC_UDELAY_COUNT	1000	/* Wait 10ms max. during EC ops */
+#define ACPI_EC_UDELAY_GLK	1000	/* Wait 1ms max. to get global lock */
+
+#define ACPI_EC_COMMAND_READ	0x80
+#define ACPI_EC_COMMAND_WRITE	0x81
+#define ACPI_EC_COMMAND_QUERY	0x84
+
+static int acpi_ec_add (struct acpi_device *device);
+static int acpi_ec_remove (struct acpi_device *device, int type);
+static int acpi_ec_start (struct acpi_device *device);
+static int acpi_ec_stop (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_ec_driver = {
+	name:			ACPI_EC_DRIVER_NAME,
+	class:			ACPI_EC_CLASS,
+	ids:			ACPI_EC_HID,
+	ops:			{
+					add:	acpi_ec_add,
+					remove:	acpi_ec_remove,
+					start:	acpi_ec_start,
+					stop:	acpi_ec_stop,
+				},
+};
+
+struct acpi_ec {
+	acpi_handle		handle;
+	unsigned long		gpe_bit;
+	unsigned long		status_port;
+	unsigned long		command_port;
+	unsigned long		data_port;
+	unsigned long		global_lock;
+	spinlock_t		lock;
+};
+
+
+/* --------------------------------------------------------------------------
+                             Transaction Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_ec_wait (
+	struct acpi_ec		*ec,
+	u8			event)
+{
+	u8			acpi_ec_status = 0;
+	u32			i = ACPI_EC_UDELAY_COUNT;
+
+	if (!ec)
+		return -EINVAL;
+
+	/* Poll the EC status register waiting for the event to occur. */
+	switch (event) {
+	case ACPI_EC_EVENT_OBF:
+		do {
+			acpi_ec_status = inb(ec->status_port);
+			if (acpi_ec_status & ACPI_EC_FLAG_OBF)
+				return 0;
+			udelay(ACPI_EC_UDELAY);
+		} while (--i>0);
+		break;
+	case ACPI_EC_EVENT_IBE:
+		do {
+			acpi_ec_status = inb(ec->status_port);
+			if (!(acpi_ec_status & ACPI_EC_FLAG_IBF))
+				return 0;
+			udelay(ACPI_EC_UDELAY);
+		} while (--i>0);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return -ETIME;
+}
+
+
+static int
+acpi_ec_read (
+	struct acpi_ec		*ec,
+	u8			address,
+	u8			*data)
+{
+	acpi_status		status = AE_OK;
+	int			result = 0;
+	unsigned long		flags = 0;
+	u32			glk = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_read");
+
+	if (!ec || !data)
+		return_VALUE(-EINVAL);
+
+	*data = 0;
+
+	if (ec->global_lock) {
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+	}
+	
+	spin_lock_irqsave(&ec->lock, flags);
+
+	outb(ACPI_EC_COMMAND_READ, ec->command_port);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (0 != result)
+		goto end;
+
+	outb(address, ec->data_port);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
+	if (0 != result)
+		goto end;
+
+	*data = inb(ec->data_port);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Read [%02x] from address [%02x]\n",
+		*data, address));
+
+end:
+	spin_unlock_irqrestore(&ec->lock, flags);
+
+	if (ec->global_lock)
+		acpi_release_global_lock(glk);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_ec_write (
+	struct acpi_ec		*ec,
+	u8			address,
+	u8			data)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	unsigned long		flags = 0;
+	u32			glk = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_write");
+
+	if (!ec)
+		return_VALUE(-EINVAL);
+
+	if (ec->global_lock) {
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+	}
+
+	spin_lock_irqsave(&ec->lock, flags);
+
+	outb(ACPI_EC_COMMAND_WRITE, ec->command_port);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (0 != result)
+		goto end;
+
+	outb(address, ec->data_port);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (0 != result)
+		goto end;
+
+	outb(data, ec->data_port);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_IBE);
+	if (0 != result)
+		goto end;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Wrote [%02x] to address [%02x]\n",
+		data, address));
+
+end:
+	spin_unlock_irqrestore(&ec->lock, flags);
+
+	if (ec->global_lock)
+		acpi_release_global_lock(glk);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_ec_query (
+	struct acpi_ec		*ec,
+	u8			*data)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	unsigned long		flags = 0;
+	u32			glk = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_query");
+
+	if (!ec || !data)
+		return_VALUE(-EINVAL);
+
+	*data = 0;
+
+	if (ec->global_lock) {
+		status = acpi_acquire_global_lock(ACPI_EC_UDELAY_GLK, &glk);
+		if (ACPI_FAILURE(status))
+			return_VALUE(-ENODEV);
+	}
+
+	/*
+	 * Query the EC to find out which _Qxx method we need to evaluate.
+	 * Note that successful completion of the query causes the ACPI_EC_SCI
+	 * bit to be cleared (and thus clearing the interrupt source).
+	 */
+
+	spin_lock_irqsave(&ec->lock, flags);
+
+	outb(ACPI_EC_COMMAND_QUERY, ec->command_port);
+	result = acpi_ec_wait(ec, ACPI_EC_EVENT_OBF);
+	if (0 != result)
+		goto end;
+	
+	*data = inb(ec->data_port);
+	if (!*data)
+		result = -ENODATA;
+
+end:
+	spin_unlock_irqrestore(&ec->lock, flags);
+
+	if (ec->global_lock)
+		acpi_release_global_lock(glk);
+
+	return_VALUE(result);
+}
+
+
+/* --------------------------------------------------------------------------
+                                Event Management
+   -------------------------------------------------------------------------- */
+
+struct acpi_ec_query_data {
+	acpi_handle		handle;
+	u8			data;
+};
+
+
+static void
+acpi_ec_gpe_query (
+	void			*data)
+{
+	struct acpi_ec_query_data *query_data = NULL;
+	static char		object_name[5] = {'_','Q','0','0','\0'};
+	const char		hex[] = {'0','1','2','3','4','5','6','7',
+				         '8','9','A','B','C','D','E','F'};
+
+	ACPI_FUNCTION_TRACE("acpi_ec_gpe_query");
+
+	if (!data)
+		return;
+
+	query_data = (struct acpi_ec_query_data *) data;
+
+	object_name[2] = hex[((query_data->data >> 4) & 0x0F)];
+	object_name[3] = hex[(query_data->data & 0x0F)];
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluating %s\n", object_name));
+
+	acpi_evaluate(query_data->handle, object_name, NULL, NULL);
+
+	kfree(query_data);
+
+	return;
+}
+
+
+static void
+acpi_ec_gpe_handler (
+	void			*data)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_ec		*ec = (struct acpi_ec *) data;
+	u8			value = 0;
+	unsigned long		flags = 0;
+	struct acpi_ec_query_data *query_data = NULL;
+
+	if (!ec)
+		return;
+
+	spin_lock_irqsave(&ec->lock, flags);
+	value = inb(ec->command_port);
+	spin_unlock_irqrestore(&ec->lock, flags);
+
+	/* TBD: Implement asynch events!
+	 * NOTE: All we care about are EC-SCI's.  Other EC events are
+	 *       handled via polling (yuck!).  This is because some systems
+	 *       treat EC-SCIs as level (versus EDGE!) triggered, preventing
+	 *       a purely interrupt-driven approach (grumble, grumble).
+	 */
+
+	if (!(value & ACPI_EC_FLAG_SCI))
+		return;
+
+	if (0 != acpi_ec_query(ec, &value))
+		return;
+
+	query_data = kmalloc(sizeof(struct acpi_ec_query_data), GFP_KERNEL);
+	if (!query_data)
+		return;
+	query_data->handle = ec->handle;
+	query_data->data = value;
+
+	status = acpi_os_queue_for_execution(OSD_PRIORITY_GPE,
+		acpi_ec_gpe_query, query_data);
+	if (ACPI_FAILURE(status))
+		kfree(query_data);
+
+	return;
+}
+
+
+/* --------------------------------------------------------------------------
+                             Address Space Management
+   -------------------------------------------------------------------------- */
+
+static acpi_status
+acpi_ec_space_setup (
+	acpi_handle		region_handle,
+	u32			function,
+	void			*handler_context,
+	void			**return_context)
+{
+	/*
+	 * The EC object is in the handler context and is needed
+	 * when calling the acpi_ec_space_handler.
+	 */
+	*return_context = handler_context;
+
+	return AE_OK;
+}
+
+
+static acpi_status
+acpi_ec_space_handler (
+	u32			function,
+	ACPI_PHYSICAL_ADDRESS	address,
+	u32			bit_width,
+	acpi_integer		*value,
+	void			*handler_context,
+	void			*region_context)
+{
+	int			result = 0;
+	struct acpi_ec		*ec = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_space_handler");
+
+	if ((address > 0xFF) || (bit_width != 8) || !value || !handler_context)
+		return_VALUE(AE_BAD_PARAMETER);
+
+	ec = (struct acpi_ec *) handler_context;
+
+	switch (function) {
+	case ACPI_READ:
+		result = acpi_ec_read(ec, (u8) address, (u8*) value);
+		break;
+	case ACPI_WRITE:
+		result = acpi_ec_write(ec, (u8) address, (u8) *value);
+		break;
+	default:
+		result = -EINVAL;
+		break;
+	}
+
+	switch (result) {
+	case -EINVAL:
+		return_VALUE(AE_BAD_PARAMETER);
+		break;
+	case -ENODEV:
+		return_VALUE(AE_NOT_FOUND);
+		break;
+	case -ETIME:
+		return_VALUE(AE_TIME);
+		break;
+	default:
+		return_VALUE(AE_OK);
+	}
+
+}
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_ec_dir = NULL;
+
+
+static int
+acpi_ec_read_info (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_ec		*ec = (struct acpi_ec *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_read_info");
+
+	if (!ec || (off != 0))
+		goto end;
+
+	p += sprintf(p, "gpe bit:                 0x%02x\n",
+		(u32) ec->gpe_bit);
+	p += sprintf(p, "ports:                   0x%02x, 0x%02x\n",
+		(u32) ec->status_port, (u32) ec->data_port);
+	p += sprintf(p, "use global lock:         %s\n",
+		ec->global_lock?"yes":"no");
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_ec_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_add_fs");
+
+	if (!acpi_ec_dir) {
+		acpi_ec_dir = proc_mkdir(ACPI_EC_CLASS, acpi_root_dir);
+		if (!acpi_ec_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_ec_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	entry = create_proc_read_entry(ACPI_EC_FILE_INFO, S_IRUGO,
+		acpi_device_dir(device), acpi_ec_read_info,
+		acpi_driver_data(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN,
+			"Unable to create '%s' fs entry\n",
+			ACPI_EC_FILE_INFO));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_ec_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_ec_remove_fs");
+
+	if (!acpi_ec_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_ec_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                               Driver Interface
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_ec_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_ec		*ec = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	ec = kmalloc(sizeof(struct acpi_ec), GFP_KERNEL);
+	if (!ec)
+		return_VALUE(-ENOMEM);
+	memset(ec, 0, sizeof(struct acpi_ec));
+
+	ec->handle = device->handle;
+	ec->lock = SPIN_LOCK_UNLOCKED;
+	sprintf(acpi_device_name(device), "%s", ACPI_EC_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_EC_CLASS);
+	acpi_driver_data(device) = ec;
+
+	/* Use the global lock for all EC transactions? */
+	acpi_evaluate_integer(ec->handle, "_GLK", NULL, &ec->global_lock);
+
+	/* Get GPE bit assignment (EC events). */
+	status = acpi_evaluate_integer(ec->handle, "_GPE", NULL, &ec->gpe_bit);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error obtaining GPE bit assignment\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	result = acpi_ec_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	printk(KERN_INFO PREFIX "%s [%s] (gpe %d)\n",
+		acpi_device_name(device), acpi_device_bid(device),
+		(u32) ec->gpe_bit);
+
+end:
+	if (0 != result)
+		kfree(ec);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_ec_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	struct acpi_ec		*ec = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_remove");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	ec = (struct acpi_ec *) acpi_driver_data(device);
+
+	acpi_ec_remove_fs(device);
+
+	kfree(ec);
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_ec_start (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_ec		*ec = NULL;
+	acpi_buffer		buffer = {ACPI_ALLOCATE_BUFFER, NULL};
+	acpi_resource		*resource = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_start");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	ec = (struct acpi_ec *) acpi_driver_data(device);
+
+	if (!ec)
+		return_VALUE(-EINVAL);
+
+	/*
+	 * Get I/O port addresses
+	 */
+
+	status = acpi_get_current_resources(ec->handle, &buffer);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error getting I/O port addresses"));
+		return_VALUE(-ENODEV);
+	}
+
+	resource = (acpi_resource *) buffer.pointer;
+	if (!resource || (resource->id != ACPI_RSTYPE_IO)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid or missing resource\n"));
+		result = -ENODEV;
+		goto end;
+	}
+	ec->data_port = resource->data.io.min_base_address;
+
+	resource = ACPI_NEXT_RESOURCE(resource);
+	if (!resource || (resource->id != ACPI_RSTYPE_IO)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid or missing resource\n"));
+		result = -ENODEV;
+		goto end;
+	}
+	ec->command_port = ec->status_port = resource->data.io.min_base_address;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "gpe=0x%02x, ports=0x%2x,0x%2x\n",
+		(u32) ec->gpe_bit, (u32) ec->command_port, (u32) ec->data_port));
+
+	/*
+	 * Install GPE handler
+	 */
+
+	status = acpi_install_gpe_handler(ec->gpe_bit,
+		ACPI_EVENT_EDGE_TRIGGERED, &acpi_ec_gpe_handler, ec);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	status = acpi_install_address_space_handler (ec->handle,
+			ACPI_ADR_SPACE_EC, &acpi_ec_space_handler,
+			&acpi_ec_space_setup, ec);
+	if (ACPI_FAILURE(status)) {
+		acpi_remove_address_space_handler(ec->handle,
+			ACPI_ADR_SPACE_EC, &acpi_ec_space_handler);
+		return_VALUE(-ENODEV);
+	}
+end:
+	kfree(buffer.pointer);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_ec_stop (
+	struct acpi_device	*device,
+	int			type)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_ec		*ec = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_stop");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	ec = (struct acpi_ec *) acpi_driver_data(device);
+
+	status = acpi_remove_address_space_handler(ec->handle,
+		ACPI_ADR_SPACE_EC, &acpi_ec_space_handler);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	status = acpi_remove_gpe_handler(ec->gpe_bit, &acpi_ec_gpe_handler);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+int __init
+acpi_ec_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_init");
+
+	result = acpi_bus_register_driver(&acpi_ec_driver);
+	if (0 > result) {
+		remove_proc_entry(ACPI_EC_CLASS, acpi_root_dir);
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_ec_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_ec_exit");
+
+	result = acpi_bus_unregister_driver(&acpi_ec_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_EC_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
diff -Nru a/drivers/acpi/acpi_fan.c b/drivers/acpi/acpi_fan.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_fan.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,300 @@
+/*
+ *  acpi_fan.c - ACPI Fan Driver ($Revision: 25 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_FAN_COMPONENT
+ACPI_MODULE_NAME		("acpi_fan")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_FAN_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define PREFIX			"ACPI: "
+
+
+int acpi_fan_add (struct acpi_device *device);
+int acpi_fan_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_fan_driver = {
+	name:			ACPI_FAN_DRIVER_NAME,
+	class:			ACPI_FAN_CLASS,
+	ids:			ACPI_FAN_HID,
+	ops:			{
+					add:	acpi_fan_add,
+					remove:	acpi_fan_remove,
+				},
+};
+
+struct acpi_fan {
+	acpi_handle		handle;
+};
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_fan_dir = NULL;
+
+
+static int
+acpi_fan_read_state (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_fan		*fan = (struct acpi_fan *) data;
+	char			*p = page;
+	int			len = 0;
+	int			state = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_fan_read_state");
+
+	if (!fan || (off != 0))
+		goto end;
+
+	if (0 != acpi_bus_get_power(fan->handle, &state))
+		goto end;
+
+	p += sprintf(p, "status:                  %s\n",
+		!state?"on":"off");
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_fan_write_state (
+	struct file		*file,
+	const char		*buffer,
+	unsigned long		count,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_fan		*fan = (struct acpi_fan *) data;
+	char			state_string[12] = {'\0'};
+
+	ACPI_FUNCTION_TRACE("acpi_fan_write_state");
+
+	if (!fan || (count > sizeof(state_string) - 1))
+		return_VALUE(-EINVAL);
+	
+	if (copy_from_user(state_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	state_string[count] = '\0';
+	
+	result = acpi_bus_set_power(fan->handle, 
+		simple_strtoul(state_string, NULL, 0));
+	if (0 != result)
+		return_VALUE(result);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_fan_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_fan_add_fs");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	if (!acpi_fan_dir) {
+		acpi_fan_dir = proc_mkdir(ACPI_FAN_CLASS, acpi_root_dir);
+		if (!acpi_fan_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_fan_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'status' [R/W] */
+	entry = create_proc_entry(ACPI_FAN_FILE_STATE,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_FAN_FILE_STATE));
+	else {
+		entry->read_proc = acpi_fan_read_state;
+		entry->write_proc = acpi_fan_write_state;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_fan_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_fan_remove_fs");
+
+	if (!acpi_fan_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_fan_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Interface
+   -------------------------------------------------------------------------- */
+
+int
+acpi_fan_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	struct acpi_fan		*fan = NULL;
+	int			state = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_fan_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	fan = kmalloc(sizeof(struct acpi_fan), GFP_KERNEL);
+	if (!fan)
+		return_VALUE(-ENOMEM);
+	memset(fan, 0, sizeof(struct acpi_fan));
+
+	fan->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_FAN_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_FAN_CLASS);
+	acpi_driver_data(device) = fan;
+
+	result = acpi_bus_get_power(fan->handle, &state);
+	if (0 != result) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error reading power state\n"));
+		goto end;
+	}
+
+	result = acpi_fan_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	printk(KERN_INFO PREFIX "%s [%s] (%s)\n",
+		acpi_device_name(device), acpi_device_bid(device),
+		!device->power.state?"on":"off");
+
+end:
+	if (0 != result)
+		kfree(fan);
+
+	return_VALUE(result);
+}
+
+
+int
+acpi_fan_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	struct acpi_fan		*fan = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_fan_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	fan = (struct acpi_fan *) acpi_driver_data(device);
+
+	acpi_fan_remove_fs(device);
+
+	kfree(fan);
+
+	return_VALUE(0);
+}
+
+
+int __init
+acpi_fan_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_fan_init");
+
+	result = acpi_bus_register_driver(&acpi_fan_driver);
+	if (0 > result)
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_fan_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_fan_exit");
+
+	result = acpi_bus_unregister_driver(&acpi_fan_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_FAN_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
+
+
+module_init(acpi_fan_init);
+module_exit(acpi_fan_exit);
+
diff -Nru a/drivers/acpi/acpi_ksyms.c b/drivers/acpi/acpi_ksyms.c
--- a/drivers/acpi/acpi_ksyms.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/acpi_ksyms.c	Fri Mar 15 17:51:02 2002
@@ -1,64 +1,58 @@
 /*
- *  ksyms.c - ACPI exported symbols
+ *  acpi_ksyms.c - ACPI Kernel Symbols ($Revision: 13 $)
  *
- *  Copyright (C) 2000 Andrew Grover
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
-#include <linux/config.h>
 #include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/acpi.h>
-#include "acpi.h"
-#include "acdebug.h"
+#include "include/acpi.h"
+#include "acpi_bus.h"
 
-extern int acpi_in_debugger;
-extern FADT_DESCRIPTOR acpi_fadt;
 
-#define _COMPONENT	OS_DEPENDENT
-	MODULE_NAME	("symbols")
+#ifdef CONFIG_ACPI_INTERPRETER
+
+/* ACPI Debugger */
 
 #ifdef ENABLE_DEBUGGER
+
+extern int			acpi_in_debugger;
+
 EXPORT_SYMBOL(acpi_in_debugger);
 EXPORT_SYMBOL(acpi_db_user_commands);
-#endif
+
+#endif /* ENABLE_DEBUGGER */
+
+/* ACPI Core Subsystem */
 
 #ifdef ACPI_DEBUG
+EXPORT_SYMBOL(acpi_dbg_layer);
+EXPORT_SYMBOL(acpi_dbg_level);
 EXPORT_SYMBOL(acpi_ut_debug_print_raw);
 EXPORT_SYMBOL(acpi_ut_debug_print);
 EXPORT_SYMBOL(acpi_ut_status_exit);
+EXPORT_SYMBOL(acpi_ut_value_exit);
 EXPORT_SYMBOL(acpi_ut_exit);
 EXPORT_SYMBOL(acpi_ut_trace);
-#endif
-
-EXPORT_SYMBOL(acpi_gbl_FADT);
-
-EXPORT_SYMBOL(acpi_os_free);
-EXPORT_SYMBOL(acpi_os_printf);
-EXPORT_SYMBOL(acpi_os_callocate);
-EXPORT_SYMBOL(acpi_os_sleep);
-EXPORT_SYMBOL(acpi_os_stall);
-EXPORT_SYMBOL(acpi_os_queue_for_execution);
-
-EXPORT_SYMBOL(acpi_dbg_layer);
-EXPORT_SYMBOL(acpi_dbg_level);
-
-EXPORT_SYMBOL(acpi_format_exception);
+#endif /*ACPI_DEBUG*/
 
 EXPORT_SYMBOL(acpi_get_handle);
 EXPORT_SYMBOL(acpi_get_parent);
@@ -68,7 +62,6 @@
 EXPORT_SYMBOL(acpi_get_next_object);
 EXPORT_SYMBOL(acpi_evaluate_object);
 EXPORT_SYMBOL(acpi_get_table);
-
 EXPORT_SYMBOL(acpi_install_notify_handler);
 EXPORT_SYMBOL(acpi_remove_notify_handler);
 EXPORT_SYMBOL(acpi_install_gpe_handler);
@@ -77,39 +70,61 @@
 EXPORT_SYMBOL(acpi_remove_address_space_handler);
 EXPORT_SYMBOL(acpi_install_fixed_event_handler);
 EXPORT_SYMBOL(acpi_remove_fixed_event_handler);
-
 EXPORT_SYMBOL(acpi_acquire_global_lock);
 EXPORT_SYMBOL(acpi_release_global_lock);
-
 EXPORT_SYMBOL(acpi_get_current_resources);
 EXPORT_SYMBOL(acpi_get_possible_resources);
 EXPORT_SYMBOL(acpi_set_current_resources);
-
 EXPORT_SYMBOL(acpi_enable_event);
 EXPORT_SYMBOL(acpi_disable_event);
 EXPORT_SYMBOL(acpi_clear_event);
-
 EXPORT_SYMBOL(acpi_get_timer_duration);
 EXPORT_SYMBOL(acpi_get_timer);
+EXPORT_SYMBOL(acpi_hw_get_sleep_type_data);
+EXPORT_SYMBOL(acpi_hw_bit_register_read);
+EXPORT_SYMBOL(acpi_hw_bit_register_write);
+EXPORT_SYMBOL(acpi_enter_sleep_state);
+EXPORT_SYMBOL(acpi_get_system_info);
 
+/* ACPI OS Services Layer (acpi_osl.c) */
+
+EXPORT_SYMBOL(acpi_os_free);
+EXPORT_SYMBOL(acpi_os_printf);
+EXPORT_SYMBOL(acpi_os_sleep);
+EXPORT_SYMBOL(acpi_os_stall);
+EXPORT_SYMBOL(acpi_os_signal);
+EXPORT_SYMBOL(acpi_os_queue_for_execution);
 EXPORT_SYMBOL(acpi_os_signal_semaphore);
 EXPORT_SYMBOL(acpi_os_create_semaphore);
 EXPORT_SYMBOL(acpi_os_delete_semaphore);
 EXPORT_SYMBOL(acpi_os_wait_semaphore);
 
-EXPORT_SYMBOL(acpi_os_read_port);
-EXPORT_SYMBOL(acpi_os_write_port);
+/* ACPI Utilities (acpi_utils.c) */
+
+EXPORT_SYMBOL(acpi_extract_package);
+EXPORT_SYMBOL(acpi_evaluate);
+EXPORT_SYMBOL(acpi_evaluate_integer);
+EXPORT_SYMBOL(acpi_evaluate_reference);
+
+#endif /*CONFIG_ACPI_INTERPRETER*/
+
+
+/* ACPI Bus Driver (acpi_bus.c) */
+
+#ifdef CONFIG_ACPI_BUS
 
 EXPORT_SYMBOL(acpi_fadt);
-EXPORT_SYMBOL(acpi_hw_register_bit_access);
-EXPORT_SYMBOL(acpi_hw_obtain_sleep_type_register_data);
-EXPORT_SYMBOL(acpi_enter_sleep_state);
-EXPORT_SYMBOL(acpi_get_system_info);
-EXPORT_SYMBOL(acpi_leave_sleep_state);
-/*EXPORT_SYMBOL(acpi_save_state_mem);*/
-/*EXPORT_SYMBOL(acpi_save_state_disk);*/
-EXPORT_SYMBOL(acpi_hw_register_read);
-EXPORT_SYMBOL(acpi_set_firmware_waking_vector);
-EXPORT_SYMBOL(acpi_subsystem_status);
+EXPORT_SYMBOL(acpi_root_dir);
+EXPORT_SYMBOL(acpi_bus_get_device);
+EXPORT_SYMBOL(acpi_bus_get_status);
+EXPORT_SYMBOL(acpi_bus_get_power);
+EXPORT_SYMBOL(acpi_bus_set_power);
+EXPORT_SYMBOL(acpi_bus_generate_event);
+EXPORT_SYMBOL(acpi_bus_receive_event);
+EXPORT_SYMBOL(acpi_bus_register_driver);
+EXPORT_SYMBOL(acpi_bus_unregister_driver);
+EXPORT_SYMBOL(acpi_bus_scan);
+EXPORT_SYMBOL(acpi_init);
+
+#endif /*CONFIG_ACPI_BUS*/
 
-EXPORT_SYMBOL(acpi_os_signal);
diff -Nru a/drivers/acpi/acpi_osl.c b/drivers/acpi/acpi_osl.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_osl.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,830 @@
+/*
+ *  acpi_osl.c - OS-dependent functions ($Revision: 65 $)
+ *
+ *  Copyright (C) 2000 Andrew Henroid
+ *  Copyright (C) 2001 Andrew Grover
+ *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/mm.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/kmod.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+#include "acpi.h"
+
+#ifdef CONFIG_ACPI_EFI
+#include <asm/efi.h>
+#endif
+
+#ifdef _IA64
+#include <asm/hw_irq.h>
+#include <asm/delay.h>
+#endif
+
+
+#define _COMPONENT		ACPI_OS_SERVICES
+ACPI_MODULE_NAME	("osl")
+
+#define PREFIX		"ACPI: "
+
+typedef struct
+{
+    OSD_EXECUTION_CALLBACK  function;
+    void		    *context;
+} ACPI_OS_DPC;
+
+
+#ifdef ENABLE_DEBUGGER
+#include <linux/kdb.h>
+/* stuff for debugger support */
+int acpi_in_debugger = 0;
+extern NATIVE_CHAR line_buf[80];
+#endif /*ENABLE_DEBUGGER*/
+
+static int acpi_irq_irq = 0;
+static OSD_HANDLER acpi_irq_handler = NULL;
+static void *acpi_irq_context = NULL;
+
+
+acpi_status
+acpi_os_initialize(void)
+{
+	/*
+	 * Initialize PCI configuration space access, as we'll need to access
+	 * it while walking the namespace (bus 0 and root bridges w/ _BBNs).
+	 */
+	pcibios_config_init();
+	if (!pci_config_read || !pci_config_write) {
+		printk(KERN_ERR PREFIX "Access to PCI configuration space unavailable\n");
+		return AE_NULL_ENTRY;
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_terminate(void)
+{
+	if (acpi_irq_handler) {
+		acpi_os_remove_interrupt_handler(acpi_irq_irq,
+						 acpi_irq_handler);
+	}
+
+	return AE_OK;
+}
+
+void
+acpi_os_printf(const NATIVE_CHAR *fmt,...)
+{
+	va_list args;
+	va_start(args, fmt);
+	acpi_os_vprintf(fmt, args);
+	va_end(args);
+}
+
+void
+acpi_os_vprintf(const NATIVE_CHAR *fmt, va_list args)
+{
+	static char buffer[512];
+	
+	vsprintf(buffer, fmt, args);
+
+#ifdef ENABLE_DEBUGGER
+	if (acpi_in_debugger) {
+		kdb_printf("%s", buffer);
+	} else {
+		printk("%s", buffer);
+	}
+#else
+	printk("%s", buffer);
+#endif
+}
+
+void *
+acpi_os_allocate(u32 size)
+{
+	return kmalloc(size, GFP_KERNEL);
+}
+
+void *
+acpi_os_callocate(u32 size)
+{
+	void *ptr = acpi_os_allocate(size);
+	if (ptr)
+		memset(ptr, 0, size);
+
+	return ptr;
+}
+
+void
+acpi_os_free(void *ptr)
+{
+	kfree(ptr);
+}
+
+
+acpi_status
+acpi_os_get_root_pointer(u32 flags, ACPI_PHYSICAL_ADDRESS *phys_addr)
+{
+#ifndef CONFIG_ACPI_EFI
+	if (ACPI_FAILURE(acpi_find_root_pointer(flags, phys_addr))) {
+		printk(KERN_ERR PREFIX "System description tables not found\n");
+		return AE_NOT_FOUND;
+	}
+#else /*CONFIG_ACPI_EFI*/
+	if (efi.acpi20)
+		*phys_addr = (ACPI_PHYSICAL_ADDRESS) efi.acpi20;
+	else if (efi.acpi)
+		*phys_addr = (ACPI_PHYSICAL_ADDRESS) efi.acpi;
+	else {
+		printk(KERN_ERR PREFIX "System description tables not found\n");
+		*phys_addr = 0;
+		return AE_NOT_FOUND;
+	}
+#endif /*CONFIG_ACPI_EFI*/
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_map_memory(ACPI_PHYSICAL_ADDRESS phys, u32 size, void **virt)
+{
+	if (phys > ULONG_MAX) {
+		printk(KERN_ERR PREFIX "Cannot map memory that high\n");
+		return AE_BAD_PARAMETER;
+	}
+
+	/*
+	 * ioremap already checks to ensure this is in reserved space
+	 */
+	*virt = ioremap((unsigned long) phys, size);
+	if (!*virt)
+		return AE_NO_MEMORY;
+
+	return AE_OK;
+}
+
+void
+acpi_os_unmap_memory(void *virt, u32 size)
+{
+	iounmap(virt);
+}
+
+acpi_status
+acpi_os_get_physical_address(void *virt, ACPI_PHYSICAL_ADDRESS *phys)
+{
+	if(!phys || !virt)
+		return AE_BAD_PARAMETER;
+
+	*phys = virt_to_phys(virt);
+
+	return AE_OK;
+}
+
+static void
+acpi_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+	(*acpi_irq_handler)(acpi_irq_context);
+}
+
+acpi_status
+acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context)
+{
+#ifdef _IA64
+	irq = isa_irq_to_vector(irq);
+#endif /*_IA64*/
+	acpi_irq_irq = irq;
+	acpi_irq_handler = handler;
+	acpi_irq_context = context;
+	if (request_irq(irq, acpi_irq, SA_SHIRQ, "acpi", acpi_irq)) {
+		printk(KERN_ERR PREFIX "SCI (IRQ%d) allocation failed\n", irq);
+		return AE_NOT_ACQUIRED;
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_remove_interrupt_handler(u32 irq, OSD_HANDLER handler)
+{
+	if (acpi_irq_handler) {
+#ifdef _IA64
+		irq = isa_irq_to_vector(irq);
+#endif /*_IA64*/
+		free_irq(irq, acpi_irq);
+		acpi_irq_handler = NULL;
+	}
+
+	return AE_OK;
+}
+
+/*
+ * Running in interpreter thread context, safe to sleep
+ */
+
+void
+acpi_os_sleep(u32 sec, u32 ms)
+{
+	current->state = TASK_INTERRUPTIBLE;
+	schedule_timeout(HZ * sec + (ms * HZ) / 1000);
+}
+
+void
+acpi_os_stall(u32 us)
+{
+	if (us > 10000) {
+		mdelay(us / 1000);
+	}
+	else {
+		udelay(us);
+	}
+}
+
+acpi_status
+acpi_os_read_port(
+	ACPI_IO_ADDRESS	port,
+	void		*value,
+	u32		width)
+{
+	u32 dummy;
+
+	if (!value)
+		value = &dummy;
+
+	switch (width)
+	{
+	case 8:
+		*(u8*)  value = inb(port);
+		break;
+	case 16:
+		*(u16*) value = inw(port);
+		break;
+	case 32:
+		*(u32*) value = inl(port);
+		break;
+	default:
+		BUG();
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_write_port(
+	ACPI_IO_ADDRESS	port,
+	acpi_integer	value,
+	u32		width)
+{
+	switch (width)
+	{
+	case 8:
+		outb(value, port);
+		break;
+	case 16:
+		outw(value, port);
+		break;
+	case 32:
+		outl(value, port);
+		break;
+	default:
+		BUG();
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_read_memory(
+	ACPI_PHYSICAL_ADDRESS	phys_addr,
+	void			*value,
+	u32			width)
+{
+	u32 dummy;
+
+	if (!value)
+		value = &dummy;
+
+	switch (width)
+	{
+	case 8:
+		*(u8*) value = *(u8*) phys_to_virt(phys_addr);
+		break;
+	case 16:
+		*(u16*) value = *(u16*) phys_to_virt(phys_addr);
+		break;
+	case 32:
+		*(u32*) value = *(u32*) phys_to_virt(phys_addr);
+		break;
+	default:
+		BUG();
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_write_memory(
+	ACPI_PHYSICAL_ADDRESS	phys_addr,
+	acpi_integer		value,
+	u32			width)
+{
+	switch (width)
+	{
+	case 8:
+		*(u8*) phys_to_virt(phys_addr) = value;
+		break;
+	case 16:
+		*(u16*) phys_to_virt(phys_addr) = value;
+		break;
+	case 32:
+		*(u32*) phys_to_virt(phys_addr) = value;
+		break;
+	default:
+		BUG();
+	}
+
+	return AE_OK;
+}
+
+
+acpi_status
+acpi_os_read_pci_configuration (
+	acpi_pci_id             *pci_id,
+	u32                     reg,
+	void                    *value,
+	u32                     width)
+{
+	int			result = 0;
+	if (!value)
+		return AE_BAD_PARAMETER;
+
+	switch (width)
+	{
+	case 8:
+		result = pci_config_read(pci_id->segment, pci_id->bus,
+			pci_id->device, pci_id->function, reg, 1, value);
+		break;
+	case 16:
+		result = pci_config_read(pci_id->segment, pci_id->bus,
+			pci_id->device, pci_id->function, reg, 2, value);
+		break;
+	case 32:
+		result = pci_config_read(pci_id->segment, pci_id->bus,
+			pci_id->device, pci_id->function, reg, 4, value);
+		break;
+	default:
+		BUG();
+	}
+
+	return (result ? AE_ERROR : AE_OK);
+}
+
+acpi_status
+acpi_os_write_pci_configuration (
+	acpi_pci_id             *pci_id,
+	u32                     reg,
+	acpi_integer            value,
+	u32                     width)
+{
+	int			result = 0;
+
+	switch (width)
+	{
+	case 8:
+		result = pci_config_write(pci_id->segment, pci_id->bus,
+			pci_id->device, pci_id->function, reg, 1, value);
+		break;
+	case 16:
+		result = pci_config_write(pci_id->segment, pci_id->bus,
+			pci_id->device, pci_id->function, reg, 2, value);
+		break;
+	case 32:
+		result = pci_config_write(pci_id->segment, pci_id->bus,
+			pci_id->device, pci_id->function, reg, 4, value);
+		break;
+	default:
+		BUG();
+	}
+
+	return (result ? AE_ERROR : AE_OK);
+}
+
+
+acpi_status
+acpi_os_load_module (
+	char *module_name)
+{
+	ACPI_FUNCTION_TRACE ("os_load_module");
+
+	if (!module_name)
+		return AE_BAD_PARAMETER;
+
+	if (0 > request_module(module_name)) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to load module [%s].\n", module_name));
+		return AE_ERROR;
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_unload_module (
+	char *module_name)
+{
+	if (!module_name)
+		return AE_BAD_PARAMETER;
+
+	/* TODO: How on Linux? */
+	/* this is done automatically for all modules with
+	use_count = 0, I think. see: MOD_INC_USE_COUNT -ASG */
+
+	return AE_OK;
+}
+
+
+/*
+ * See acpi_os_queue_for_execution()
+ */
+static int
+acpi_os_queue_exec (
+	void *context)
+{
+	ACPI_OS_DPC		*dpc = (ACPI_OS_DPC*)context;
+
+	ACPI_FUNCTION_TRACE ("os_queue_exec");
+
+	daemonize();
+	strcpy(current->comm, "kacpidpc");
+
+	if (!dpc || !dpc->function)
+		return AE_BAD_PARAMETER;
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Executing function [%p(%p)].\n", dpc->function, dpc->context));
+
+	dpc->function(dpc->context);
+
+	kfree(dpc);
+
+	return 1;
+}
+
+static void
+acpi_os_schedule_exec (
+	void *context)
+{
+	ACPI_OS_DPC		*dpc = NULL;
+	int			thread_pid = -1;
+
+	ACPI_FUNCTION_TRACE ("os_schedule_exec");
+
+	dpc = (ACPI_OS_DPC*)context;
+	if (!dpc) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
+		return;
+	}
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Creating new thread to run function [%p(%p)].\n", dpc->function, dpc->context));
+
+	thread_pid = kernel_thread(acpi_os_queue_exec, dpc,
+		(CLONE_FS | CLONE_FILES | SIGCHLD));
+	if (thread_pid < 0) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Call to kernel_thread() failed.\n"));
+		acpi_os_free(dpc);
+	}
+}
+
+acpi_status
+acpi_os_queue_for_execution(
+	u32			priority,
+	OSD_EXECUTION_CALLBACK	function,
+	void			*context)
+{
+	acpi_status 		status = AE_OK;
+	ACPI_OS_DPC 		*dpc = NULL;
+
+	ACPI_FUNCTION_TRACE ("os_queue_for_execution");
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Scheduling function [%p(%p)] for deferred execution.\n", function, context));
+
+	if (!function)
+		return AE_BAD_PARAMETER;
+
+	/*
+	 * Queue via DPC:
+	 * --------------
+	 * Note that we have to use two different processes for queuing DPCs:
+	 *	 Interrupt-Level: Use schedule_task; can't spawn a new thread.
+	 *	    Kernel-Level: Spawn a new kernel thread, as schedule_task has
+	 *			  its limitations (e.g. single-threaded model), and
+	 *			  all other task queues run at interrupt-level.
+	 */
+	switch (priority) {
+
+	case OSD_PRIORITY_GPE:
+	{
+		static struct tq_struct task;
+
+		/*
+		 * Allocate/initialize DPC structure.  Note that this memory will be
+		 * freed by the callee.
+		 */
+		dpc = kmalloc(sizeof(ACPI_OS_DPC), GFP_ATOMIC);
+		if (!dpc)
+			return AE_NO_MEMORY;
+
+		dpc->function = function;
+		dpc->context = context;
+
+		memset(&task, 0, sizeof(struct tq_struct));
+
+		task.routine = acpi_os_schedule_exec;
+		task.data = (void*)dpc;
+
+		if (schedule_task(&task) < 0) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Call to schedule_task() failed.\n"));
+			status = AE_ERROR;
+		}
+	}
+	break;
+
+	default:
+		/*
+		 * Allocate/initialize DPC structure.  Note that this memory will be
+		 * freed by the callee.
+		 */
+		dpc = kmalloc(sizeof(ACPI_OS_DPC), GFP_KERNEL);
+		if (!dpc)
+			return AE_NO_MEMORY;
+
+		dpc->function = function;
+		dpc->context = context;
+
+		acpi_os_schedule_exec(dpc);
+		break;
+	}
+
+	return status;
+}
+
+
+acpi_status
+acpi_os_create_semaphore(
+	u32		max_units,
+	u32		initial_units,
+	acpi_handle	*handle)
+{
+	struct semaphore	*sem = NULL;
+
+	ACPI_FUNCTION_TRACE ("os_create_semaphore");
+
+	sem = acpi_os_callocate(sizeof(struct semaphore));
+	if (!sem)
+		return AE_NO_MEMORY;
+
+	sema_init(sem, initial_units);
+
+	*handle = (acpi_handle*)sem;
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Creating semaphore[%p|%d].\n", *handle, initial_units));
+
+	return AE_OK;
+}
+
+
+/*
+ * TODO: A better way to delete semaphores?  Linux doesn't have a
+ * 'delete_semaphore()' function -- may result in an invalid
+ * pointer dereference for non-synchronized consumers.	Should
+ * we at least check for blocked threads and signal/cancel them?
+ */
+
+acpi_status
+acpi_os_delete_semaphore(
+	acpi_handle	handle)
+{
+	struct semaphore *sem = (struct semaphore*) handle;
+
+	ACPI_FUNCTION_TRACE ("os_delete_semaphore");
+
+	if (!sem)
+		return AE_BAD_PARAMETER;
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting semaphore[%p].\n", handle));
+
+	acpi_os_free(sem); sem =  NULL;
+
+	return AE_OK;
+}
+
+
+/*
+ * TODO: The kernel doesn't have a 'down_timeout' function -- had to
+ * improvise.  The process is to sleep for one scheduler quantum
+ * until the semaphore becomes available.  Downside is that this
+ * may result in starvation for timeout-based waits when there's
+ * lots of semaphore activity.
+ *
+ * TODO: Support for units > 1?
+ */
+acpi_status
+acpi_os_wait_semaphore(
+	acpi_handle		handle,
+	u32			units,
+	u32			timeout)
+{
+	acpi_status		status = AE_OK;
+	struct semaphore	*sem = (struct semaphore*)handle;
+	int			ret = 0;
+
+	ACPI_FUNCTION_TRACE ("os_wait_semaphore");
+
+	if (!sem || (units < 1))
+		return AE_BAD_PARAMETER;
+
+	if (units > 1)
+		return AE_SUPPORT;
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Waiting for semaphore[%p|%d|%d]\n", handle, units, timeout));
+
+	switch (timeout)
+	{
+		/*
+		 * No Wait:
+		 * --------
+		 * A zero timeout value indicates that we shouldn't wait - just
+		 * acquire the semaphore if available otherwise return AE_TIME
+		 * (a.k.a. 'would block').
+		 */
+		case 0:
+		if(down_trylock(sem))
+			status = AE_TIME;
+		break;
+
+		/*
+		 * Wait Indefinitely:
+		 * ------------------
+		 */
+		case WAIT_FOREVER:
+		ret = down_interruptible(sem);
+		if (ret < 0)
+			status = AE_ERROR;
+		break;
+
+		/*
+		 * Wait w/ Timeout:
+		 * ----------------
+		 */
+		default:
+		// TODO: A better timeout algorithm?
+		{
+			int i = 0;
+			static const int quantum_ms = 1000/HZ;
+
+			ret = down_trylock(sem);
+			for (i = timeout; (i > 0 && ret < 0); i -= quantum_ms) {
+				current->state = TASK_INTERRUPTIBLE;
+				schedule_timeout(1);
+				ret = down_trylock(sem);
+			}
+	
+			if (ret != 0)
+			 status = AE_TIME;
+			}
+		break;
+	}
+
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Failed to acquire semaphore[%p|%d|%d]\n", handle, units, timeout));
+	}
+	else {
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Acquired semaphore[%p|%d|%d]\n", handle, units, timeout));
+	}
+
+	return status;
+}
+
+
+/*
+ * TODO: Support for units > 1?
+ */
+acpi_status
+acpi_os_signal_semaphore(
+    acpi_handle 	    handle,
+    u32 		    units)
+{
+	struct semaphore *sem = (struct semaphore *) handle;
+
+	ACPI_FUNCTION_TRACE ("os_signal_semaphore");
+
+	if (!sem || (units < 1))
+		return AE_BAD_PARAMETER;
+
+	if (units > 1)
+		return AE_SUPPORT;
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Signaling semaphore[%p|%d]\n", handle, units));
+
+	up(sem);
+
+	return AE_OK;
+}
+
+u32
+acpi_os_get_line(NATIVE_CHAR *buffer)
+{
+
+#ifdef ENABLE_DEBUGGER
+	if (acpi_in_debugger) {
+		u32 chars;
+
+		kdb_read(buffer, sizeof(line_buf));
+
+		/* remove the CR kdb includes */
+		chars = strlen(buffer) - 1;
+		buffer[chars] = '\0';
+	}
+#endif
+
+	return 0;
+}
+
+/*
+ * We just have to assume we're dealing with valid memory
+ */
+
+BOOLEAN
+acpi_os_readable(void *ptr, u32 len)
+{
+	return 1;
+}
+
+BOOLEAN
+acpi_os_writable(void *ptr, u32 len)
+{
+	return 1;
+}
+
+u32
+acpi_os_get_thread_id (void)
+{
+	if (!in_interrupt())
+		return current->pid;
+
+	return 0;
+}
+
+acpi_status
+acpi_os_signal (
+    u32		function,
+    void	*info)
+{
+	switch (function)
+	{
+	case ACPI_SIGNAL_FATAL:
+		printk(KERN_ERR PREFIX "Fatal opcode executed\n");
+		break;
+	case ACPI_SIGNAL_BREAKPOINT:
+		{
+			char *bp_info = (char*) info;
+
+			printk(KERN_ERR "ACPI breakpoint: %s\n", bp_info);
+		}
+	default:
+		break;
+	}
+
+	return AE_OK;
+}
+
+acpi_status
+acpi_os_breakpoint(NATIVE_CHAR *msg)
+{
+	acpi_os_printf("breakpoint: %s", msg);
+	
+	return AE_OK;
+}
+
diff -Nru a/drivers/acpi/acpi_pci_link.c b/drivers/acpi/acpi_pci_link.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_pci_link.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,524 @@
+/*
+ *  acpi_pci_link.c - ACPI PCI Interrupt Link Device Driver ($Revision: 19 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * TBD: 
+ *      1. Support more than one IRQ resource entry per link device.
+ *	2. Implement start/stop mechanism and use ACPI Bus Driver facilities
+ *	   for IRQ management (e.g. start()->_SRS).
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/pm.h>
+#include <linux/pci.h>
+
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_PCI_LINK_COMPONENT
+ACPI_MODULE_NAME		("acpi_pci_link")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_PCI_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define PREFIX			"ACPI: "
+
+#define ACPI_PCI_LINK_MAX_IRQS	16
+
+
+static int acpi_pci_link_add (struct acpi_device *device);
+static int acpi_pci_link_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_pci_link_driver = {
+        name:                   ACPI_PCI_LINK_DRIVER_NAME,
+        class:                  ACPI_PCI_LINK_CLASS,
+        ids:                    ACPI_PCI_LINK_HID,
+        ops:                    {
+                                        add:    acpi_pci_link_add,
+                                        remove: acpi_pci_link_remove,
+                                },
+};
+
+struct acpi_pci_link_irq {
+	u8			active;			/* Current IRQ */
+	u8			possible_count;
+	u8			possible[ACPI_PCI_LINK_MAX_IRQS];
+	struct {
+		u8			valid:1;
+		u8			enabled:1;
+		u8			shareable:1;	/* 0 = Exclusive */
+		u8			polarity:1;	/* 0 = Active-High */
+		u8			trigger:1;	/* 0 = Level-Triggered */
+		u8			producer:1;	/* 0 = Consumer-Only */
+		u8			reserved:2;
+	}			flags;
+};
+
+struct acpi_pci_link {
+	acpi_handle		handle;
+	struct acpi_pci_link_irq irq;
+};
+
+
+/* --------------------------------------------------------------------------
+                            PCI Link Device Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_pci_link_get_current (
+	struct acpi_pci_link	*link)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	acpi_buffer		buffer = {0, NULL};
+	acpi_resource		*resource = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_get_current");
+
+	if (!link || !link->handle)
+		return_VALUE(-EINVAL);
+
+	link->irq.active = 0;
+
+	status = acpi_get_current_resources(link->handle, &buffer);
+	if (status != AE_BUFFER_OVERFLOW) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _CRS\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	buffer.pointer = kmalloc(buffer.length, GFP_KERNEL);
+	if (!buffer.pointer)
+		return_VALUE(-ENOMEM);
+	memset(buffer.pointer, 0, buffer.length);
+
+	status = acpi_get_current_resources(link->handle, &buffer);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _CRS\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	resource = (acpi_resource *) buffer.pointer;
+
+	switch (resource->id) {
+	case ACPI_RSTYPE_IRQ:
+	{
+		acpi_resource_irq *p = &resource->data.irq;
+		if (p->number_of_interrupts > 0)
+			link->irq.active = p->interrupts[0];
+		else {
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Blank IRQ resource\n"));
+			result = -ENODEV;
+			goto end;
+		}
+		break;
+	}
+	case ACPI_RSTYPE_EXT_IRQ:
+	{
+		acpi_resource_ext_irq *p = &resource->data.extended_irq;
+		if (p->number_of_interrupts > 0)
+			link->irq.active = p->interrupts[0];
+		else {
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Blank IRQ resource\n"));
+			result = -ENODEV;
+			goto end;
+		}
+		break;
+	}
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"First resource is not an IRQ entry\n"));
+		break;
+	}
+
+end:
+	kfree(buffer.pointer);
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_pci_link_get_possible (
+	struct acpi_pci_link	*link)
+{
+	int                     result = 0;
+	acpi_status		status = AE_OK;
+	acpi_buffer		buffer = {0, NULL};
+	acpi_resource		*resource = NULL;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_get_possible");
+
+	if (!link)
+		return_VALUE(-EINVAL);
+
+	status = acpi_get_possible_resources(link->handle, &buffer);
+	if (status != AE_BUFFER_OVERFLOW) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _PRS\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	buffer.pointer = kmalloc(buffer.length, GFP_KERNEL);
+	if (!buffer.pointer)
+		return_VALUE(-ENOMEM);
+	memset(buffer.pointer, 0, buffer.length);
+
+	status = acpi_get_possible_resources(link->handle, &buffer);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _PRS\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	resource = (acpi_resource *) buffer.pointer;
+
+	switch (resource->id) {
+	case ACPI_RSTYPE_IRQ:
+	{
+		acpi_resource_irq *p = &resource->data.irq;
+
+		for (i = 0; (i<p->number_of_interrupts && i<ACPI_PCI_LINK_MAX_IRQS); i++) {
+			link->irq.possible[i] = p->interrupts[i];
+			link->irq.possible_count++;
+		}
+
+		if (!p->number_of_interrupts) {
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Blank IRQ resource\n"));
+			result = -ENODEV;
+			goto end;
+		}
+
+		link->irq.flags.trigger = p->edge_level;
+		link->irq.flags.polarity = p->active_high_low;
+		link->irq.flags.shareable = p->shared_exclusive;
+
+		break;
+	}
+	case ACPI_RSTYPE_EXT_IRQ:
+	{
+		acpi_resource_ext_irq *p = &resource->data.extended_irq;
+
+		for (i = 0; (i<p->number_of_interrupts && i<ACPI_PCI_LINK_MAX_IRQS); i++) {
+			link->irq.possible[i] = p->interrupts[i];
+			link->irq.possible_count++;
+		}
+
+		if (!p->number_of_interrupts) {
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Blank IRQ resource\n"));
+			result = -ENODEV;
+			goto end;
+		}
+
+		link->irq.flags.trigger = p->edge_level;
+		link->irq.flags.polarity = p->active_high_low;
+		link->irq.flags.shareable = p->shared_exclusive;
+
+		break;
+	}
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"First resource is not an IRQ entry\n"));
+		break;
+	}
+
+end:
+	kfree(buffer.pointer);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_pci_link_set (
+	struct acpi_pci_link	*link,
+	u32			irq)
+{
+	acpi_status		status = AE_OK;
+	struct {
+		acpi_resource	res;
+		acpi_resource   end;
+	}                       resource;
+	acpi_buffer		buffer = {sizeof(resource)+1, &resource};
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_set");
+
+	if (!link || !irq)
+		return_VALUE(-EINVAL);
+
+	memset(&resource, 0, sizeof(resource));
+
+	resource.res.id = ACPI_RSTYPE_IRQ;
+	resource.res.length = sizeof(acpi_resource);
+	resource.res.data.irq.edge_level = link->irq.flags.trigger;
+	resource.res.data.irq.active_high_low = link->irq.flags.polarity;
+	resource.res.data.irq.shared_exclusive = link->irq.flags.shareable;
+	resource.res.data.irq.number_of_interrupts = 1;
+	resource.res.data.irq.interrupts[0] = irq;
+	resource.end.id = ACPI_RSTYPE_END_TAG;
+
+	status = acpi_set_current_resources(link->handle, &buffer);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _SRS\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_pci_link_get_irq (
+	struct acpi_prt_entry	*entry,
+	int			*irq)
+{
+	int                     result = -ENODEV;
+	struct acpi_device	*device = NULL;
+	struct acpi_pci_link	*link = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_get_irq");
+
+	if (!entry || !entry->source.handle || !irq)
+		return_VALUE(-EINVAL);
+
+	/* TBD: Support multiple index values (not just first). */
+	if (0 != entry->source.index) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"Unsupported resource index [%d]\n", 
+			entry->source.index));
+		return_VALUE(-ENODEV);
+	}
+
+	result = acpi_bus_get_device(entry->source.handle, &device);
+	if (0 != result) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Link IRQ invalid\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	link = (struct acpi_pci_link *) acpi_driver_data(device);
+	if (!link) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid link context\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	if (!link->irq.flags.valid) 
+		return_VALUE(-ENODEV);
+
+	/* TBD: Support multiple index (IRQ) entries per Link Device */
+	if (0 != entry->source.index) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"Unsupported IRQ resource index [%d]\n", 
+			entry->source.index));
+		return_VALUE(-EFAULT);
+	}
+
+	*irq = link->irq.active;
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_pci_link_set_irq (
+	struct acpi_prt_entry	*entry,
+	int			irq)
+{
+	int			result = 0;
+	int			i = 0;
+	int			valid = 0;
+	struct acpi_device	*device = NULL;
+	struct acpi_pci_link	*link = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_set_irq");
+
+	if (!entry || !entry->source.handle || !irq)
+		return_VALUE(-EINVAL);
+
+	/* TBD: Support multiple index values (not just first). */
+	if (0 != entry->source.index) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"Unsupported resource index [%d]\n", 
+			entry->source.index));
+		return_VALUE(-ENODEV);
+	}
+
+	result = acpi_bus_get_device(entry->source.handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	link = (struct acpi_pci_link *) acpi_driver_data(device);
+	if (!link) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid link context\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	if (!link->irq.flags.valid) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Link IRQ invalid\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	/* Is the target IRQ the same as the currently enabled IRQ? */
+	if (link->irq.flags.enabled && (irq == link->irq.active)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Link IRQ already at target\n"));
+		return_VALUE(0);
+	}
+
+	/* Is the target IRQ in the list of possible IRQs? */
+	for (i=0; i<link->irq.possible_count; i++) {
+		if (irq == link->irq.possible[i])
+			valid = 1;
+	}
+	if (!valid) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Target IRQ invalid\n"));
+		return_VALUE(-EINVAL);
+	}
+
+	/* TBD: Do we need to disable this link device before resetting? */
+
+	/* Set the new IRQ */
+	result = acpi_pci_link_set(link, irq);
+	if (0 != result)
+		return_VALUE(result);
+
+	link->irq.active = irq;
+
+	return_VALUE(result);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Interface
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_pci_link_add (
+	struct acpi_device *device)
+{
+	int			result = 0;
+	struct acpi_pci_link	*link = NULL;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	link = kmalloc(sizeof(struct acpi_pci_link), GFP_KERNEL);
+	if (!link)
+		return_VALUE(-ENOMEM);
+	memset(link, 0, sizeof(struct acpi_pci_link));
+
+	link->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_PCI_LINK_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_PCI_LINK_CLASS);
+	acpi_driver_data(device) = link;
+
+	result = acpi_pci_link_get_possible(link);
+	if (0 != result)
+		return_VALUE(result);
+
+	if (!device->status.enabled) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Enabling at IRQ [%d]\n",
+			link->irq.possible[0]));
+
+		result = acpi_pci_link_set(link, link->irq.possible[0]);
+		if (0 != result)
+			return_VALUE(result);
+
+		result = acpi_bus_get_status(device);
+		if (0 != result)
+			return_VALUE(result);
+
+		if (!device->status.enabled) {
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+				"Enable failed\n"));
+			return_VALUE(-EFAULT);
+		}
+	}
+
+	result = acpi_pci_link_get_current(link);
+	if (0 != result)
+		return_VALUE(result);
+
+	link->irq.flags.valid = 1;
+
+	printk(PREFIX "%s [%s] (IRQs", 
+		acpi_device_name(device), acpi_device_bid(device));
+	for (i = 0; i < link->irq.possible_count; i++)
+		printk("%s%d", 
+			(link->irq.active==link->irq.possible[i])?" *":" ",
+			link->irq.possible[i]);
+	printk(")\n");
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_pci_link_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	struct acpi_pci_link *link = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_link_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	link = (struct acpi_pci_link *) acpi_driver_data(device);
+
+	kfree(link);
+
+	return_VALUE(0);
+}
+
+
+int __init
+acpi_pci_link_init (void)
+{
+	ACPI_FUNCTION_TRACE("acpi_pci_link_init");
+
+	if (0 > acpi_bus_register_driver(&acpi_pci_link_driver))
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_pci_link_exit (void)
+{
+	ACPI_FUNCTION_TRACE("acpi_pci_link_init");
+
+	acpi_bus_unregister_driver(&acpi_pci_link_driver);
+
+	return_VOID;
+}
diff -Nru a/drivers/acpi/acpi_pci_root.c b/drivers/acpi/acpi_pci_root.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_pci_root.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,474 @@
+/*
+ *  acpi_pci_root.c - ACPI PCI Root Bridge Driver ($Revision: 22 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/pm.h>
+#include <linux/pci.h>
+#include <linux/acpi.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_PCI_ROOT_COMPONENT
+ACPI_MODULE_NAME		("pci_root")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_PCI_ROOT_DRIVER_NAME);
+
+extern struct pci_ops *pci_root_ops;
+
+#define PREFIX			"ACPI: "
+
+static int acpi_pci_root_add (struct acpi_device *device);
+static int acpi_pci_root_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_pci_root_driver = {
+        name:                   ACPI_PCI_ROOT_DRIVER_NAME,
+        class:                  ACPI_PCI_ROOT_CLASS,
+        ids:                    ACPI_PCI_ROOT_HID,
+        ops:                    {
+                                        add:    acpi_pci_root_add,
+                                        remove: acpi_pci_root_remove,
+                                },
+};
+
+struct acpi_pci_root_context {
+	acpi_handle		handle;
+	struct {
+		u8			seg;	/* Root's segment number */
+		u8			bus;	/* Root's bus number */
+		u8			sub;	/* Max subordinate bus */
+	}			id;
+	struct pci_bus		*bus;
+	struct pci_dev		*dev;
+};
+
+struct acpi_prt_list		acpi_prts;
+
+
+/* --------------------------------------------------------------------------
+                        PCI Routing Table (PRT) Support
+   -------------------------------------------------------------------------- */
+
+static struct acpi_prt_entry *
+acpi_prt_find_entry (
+	struct pci_dev		*dev,
+	u8			pin)
+{
+	struct acpi_prt_entry	*entry = NULL;
+	struct list_head	*node = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_prt_find_entry");
+
+	/* TBD: Locking */
+	list_for_each(node, &acpi_prts.entries) {
+		entry = list_entry(node, struct acpi_prt_entry, node);
+		if ((entry->id.dev == PCI_SLOT(dev->devfn)) 
+			&& (entry->id.pin == pin))
+			return_PTR(entry);
+	}
+
+	return_PTR(NULL);
+}
+
+
+int
+acpi_prt_get_irq (
+	struct pci_dev		*dev,
+	u8			pin,
+	int			*irq)
+{
+	int			result = 0;
+	struct acpi_prt_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_get_current_irq");
+
+	if (!dev || !irq)
+		return_VALUE(-ENODEV);
+
+	entry = acpi_prt_find_entry(dev, pin);
+	if (!entry)
+		return_VALUE(-ENODEV);
+
+	/* Type 1: Dynamic (e.g. PCI Link Device) */
+	if (entry->source.handle)
+		result = acpi_pci_link_get_irq(entry, irq);
+	/* Type 2: Static (e.g. I/O [S]APIC Direct) */
+	else
+		*irq = entry->source.index;
+	
+	return_VALUE(0);
+}
+
+
+int
+acpi_prt_set_irq (
+	struct pci_dev		*dev,
+	u8			pin,
+	int			irq)
+{
+	int			result = 0;
+	int			i = 0;
+	int			valid = 0;
+	struct acpi_prt_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_set_current_irq");
+
+	if (!dev || !irq)
+		return_VALUE(-EINVAL);
+
+	entry = acpi_prt_find_entry(dev, pin);
+	if (!entry)
+		return_VALUE(-ENODEV);
+
+	/* Type 1: Dynamic (e.g. PCI Link Device) */
+	if (entry->source.handle)
+		result = acpi_pci_link_set_irq(entry, irq);
+	/* Type 2: Static (e.g. I/O [S]APIC Direct) */
+	else
+		result = -EFAULT;
+	
+	return_VALUE(result);
+}
+
+
+static int
+acpi_prt_add_entry (
+	acpi_handle		handle,
+	u8			seg,
+	u8			bus,
+	acpi_pci_routing_table	*prt)
+{
+	struct acpi_prt_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_prt_add_entry");
+
+	if (!prt)
+		return_VALUE(-EINVAL);
+
+	entry = kmalloc(sizeof(struct acpi_prt_entry), GFP_KERNEL);
+	if (!entry)
+		return_VALUE(-ENOMEM);
+	memset(entry, 0, sizeof(struct acpi_prt_entry));
+
+	entry->id.seg = seg;
+	entry->id.bus = bus;
+	entry->id.dev = prt->address >> 16;
+	entry->id.pin = prt->pin;
+
+	/*
+	 * Type 1: Dynamic
+	 * ---------------
+	 * The 'source' field specifies the PCI interrupt link device used to
+	 * configure the IRQ assigned to this slot|dev|pin.  The 'source_index'
+	 * indicates which resource descriptor in the resource template (of
+	 * the link device) this interrupt is allocated from.
+	 */
+	if (prt->source)
+		acpi_get_handle(handle, prt->source, &entry->source.handle);
+	/*
+	 * Type 2: Static
+	 * --------------
+	 * The 'source' field is NULL, and the 'source_index' field specifies
+	 * the IRQ value, which is hardwired to specific interrupt inputs on
+	 * the interrupt controller.
+	 */
+	else
+		entry->source.handle = NULL;
+
+	entry->source.index = prt->source_index;
+
+	/* 
+	 * NOTE: Don't query the Link Device for IRQ information at this time
+	 *       because Link Device enumeration may not have occurred yet
+	 *       (e.g. exists somewhere 'below' this _PRT entry in the ACPI
+	 *       namespace).
+	 */
+
+	printk(KERN_INFO "      %02X:%02X:%02X[%c] -> %s[%d]\n", 
+		entry->id.seg, entry->id.bus, entry->id.dev, 
+		('A' + entry->id.pin), prt->source, entry->source.index);
+
+	/* TBD: Acquire/release lock */
+	list_add_tail(&entry->node, &acpi_prts.entries);
+
+	acpi_prts.count++;
+
+	return_VALUE(0);
+}
+
+
+static acpi_status
+acpi_prt_callback (
+	acpi_handle             handle,
+	u32                     nesting_level,
+	void                    *context,
+	void                    **return_value)
+{
+	acpi_status		status = AE_OK;
+	acpi_handle		prt_handle = NULL;
+	char			pathname[PATHNAME_MAX] = {0};
+	acpi_buffer		buffer = {0, NULL};
+	acpi_pci_routing_table	*prt = NULL;
+	unsigned long		sta = 0;
+	struct acpi_pci_root_context *root = (struct acpi_pci_root_context *) context;
+	u8			bus_number = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_prt_callback");
+
+	if (!root)
+		return_VALUE(AE_BAD_PARAMETER);
+
+	status = acpi_get_handle(handle, METHOD_NAME__PRT, &prt_handle);
+	if (ACPI_FAILURE(status))
+		return_VALUE(AE_OK);
+
+	buffer.length = sizeof(pathname);
+	buffer.pointer = pathname;
+	acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
+
+	/* 
+	 * Evalute _STA to see if the device containing this _PRT is present.
+	 */
+	status = acpi_evaluate_integer(handle, METHOD_NAME__STA, NULL, &sta);
+	switch (status) {
+	case AE_OK:
+		if (!(sta & 0x01)) {
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+				"Found _PRT but device [%s] not present\n", 
+				pathname));
+			return_VALUE(AE_OK);
+		}
+		break;
+	case AE_NOT_FOUND:
+		/* assume present */
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Error evaluating %s._STA [%s]\n", 
+			pathname, acpi_format_exception(status)));
+		return_VALUE(status);
+	}
+
+	printk(KERN_INFO PREFIX "%s [%s._PRT]\n", ACPI_PCI_PRT_DEVICE_NAME, 
+		pathname);
+
+	/* 
+	 * Evaluate this _PRT and add all entries to our global list.
+	 */
+
+	buffer.length = 0;
+	buffer.pointer = NULL;
+	status = acpi_get_irq_routing_table(handle, &buffer);
+	if (status != AE_BUFFER_OVERFLOW) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Error evaluating _PRT [%s]\n", 
+			acpi_format_exception(status)));
+		return_VALUE(status);
+	}
+
+	prt = kmalloc(buffer.length, GFP_KERNEL);
+	if (!prt)
+		return_VALUE(-ENOMEM);
+	memset(prt, 0, buffer.length);
+	buffer.pointer = prt;
+
+	status = acpi_get_irq_routing_table(handle, &buffer);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Error evaluating _PRT [%s]\n", 
+			acpi_format_exception(status)));
+		kfree(buffer.pointer);
+		return_VALUE(status);
+	}
+
+	if (root->handle == handle)
+		bus_number = root->id.bus;
+	else {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Need to get subordinate bus number!\n"));
+		/* get the bus number for this device */
+	}
+
+	while (prt && (prt->length > 0)) {
+		acpi_prt_add_entry(handle, root->id.seg, bus_number, prt);
+		prt = (acpi_pci_routing_table*)((unsigned long)prt + prt->length);
+	}
+
+	return_VALUE(AE_OK);
+}
+
+
+/* --------------------------------------------------------------------------
+                                Driver Interface
+   -------------------------------------------------------------------------- */
+
+int
+acpi_pci_root_add (
+	struct acpi_device	*device)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_pci_root_context *context = NULL;
+	unsigned long		temp = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_root_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	context = kmalloc(sizeof(struct acpi_pci_root_context), GFP_KERNEL);
+	if (!context)
+		return_VALUE(-ENOMEM);
+	memset(context, 0, sizeof(struct acpi_pci_root_context));
+
+	context->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_PCI_ROOT_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_PCI_ROOT_CLASS);
+	acpi_driver_data(device) = context;
+
+	status = acpi_evaluate_integer(context->handle, METHOD_NAME__SEG, 
+		NULL, &temp);
+	if (ACPI_SUCCESS(status))
+		context->id.seg = temp;
+	else
+		context->id.seg = 0;
+
+	status = acpi_evaluate_integer(context->handle, METHOD_NAME__BBN, 
+		NULL, &temp);
+	if (ACPI_SUCCESS(status))
+		context->id.bus = temp;
+	else
+		context->id.bus = 0;
+
+	/* TBD: Evaluate _CRS for bus range of child P2P (bus min/max/len) */
+
+	printk(KERN_INFO PREFIX "%s [%s] (%02x:%02x)\n", 
+		acpi_device_name(device), acpi_device_bid(device),
+		context->id.seg, context->id.bus);
+
+	/*
+	 * Scan all devices on this root bridge.  Note that this must occur
+	 * now to get the correct bus number assignments for subordinate
+	 * PCI-PCI bridges.
+	 */
+	pci_scan_bus(context->id.bus, pci_root_ops, NULL);
+
+	/* Evaluate _PRT for this root bridge. */
+	acpi_prt_callback(context->handle, 0, context, NULL);
+
+	/* Evaluate all subordinate _PRTs. */
+	acpi_walk_namespace(ACPI_TYPE_DEVICE, context->handle, ACPI_UINT32_MAX, 
+		acpi_prt_callback, context, NULL);
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_pci_root_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	struct acpi_pci_dev_context *context = NULL;
+
+	if (!device)
+		return -EINVAL;
+
+	if (device->driver_data)
+		/* Root bridge */
+		kfree(device->driver_data);
+	else {
+		/* Standard PCI device */
+		context = acpi_driver_data(device);
+		if (context)
+			kfree(context);
+	}
+
+	return 0;
+}
+
+
+int __init 
+acpi_pci_irq_init (void)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	acpi_object		arg = {ACPI_TYPE_INTEGER};
+	acpi_object_list        arg_list = {1, &arg};
+	int			irq_model = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_irq_init");
+
+	/* 
+	 * Let the system know what interrupt model we are using by
+	 * evaluating the \_PIC object, if exists.
+	 */
+
+	result = acpi_get_interrupt_model(&irq_model);
+	if (0 != result)
+		return_VALUE(result);
+
+	arg.integer.value = irq_model;
+
+	status = acpi_evaluate_object(NULL, "\\_PIC", &arg_list, NULL);
+	if (ACPI_FAILURE(status) && (status != AE_NOT_FOUND)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Error evaluating _PIC\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+int __init
+acpi_pci_root_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_pci_root_init");
+
+	acpi_prts.count = 0;
+	INIT_LIST_HEAD(&acpi_prts.entries);
+
+	result = acpi_pci_irq_init();
+	if (0 != result)
+		return_VALUE(result);
+
+	if (0 > acpi_bus_register_driver(&acpi_pci_root_driver))
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_pci_root_exit (void)
+{
+	ACPI_FUNCTION_TRACE("acpi_pci_root_exit");
+
+	acpi_bus_unregister_driver(&acpi_pci_root_driver);
+}
+
diff -Nru a/drivers/acpi/acpi_power.c b/drivers/acpi/acpi_power.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_power.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,610 @@
+/*
+ *  acpi_power.c - ACPI Bus Power Management ($Revision: 34 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_POWER_COMPONENT
+ACPI_MODULE_NAME		("acpi_power")
+
+#define PREFIX			"ACPI: "
+
+
+int acpi_power_add (struct acpi_device *device);
+int acpi_power_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_power_driver = {
+	name:			ACPI_POWER_DRIVER_NAME,
+	class:			ACPI_POWER_CLASS,
+	ids:			ACPI_POWER_HID,
+	ops:			{
+					add:	acpi_power_add,
+					remove:	acpi_power_remove,
+				},
+};
+
+struct acpi_power_resource
+{
+	acpi_handle		handle;
+	acpi_bus_id		name;
+	u32			system_level;
+	u32			order;
+	int			state;
+	int			references;
+};
+
+static struct list_head		acpi_power_resource_list;
+
+
+/* --------------------------------------------------------------------------
+                             Power Resource Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_power_get_context (
+	acpi_handle		handle,
+	struct acpi_power_resource **resource)
+{
+	int			result = 0;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_power_get_context");
+
+	if (!resource)
+		return_VALUE(-ENODEV);
+
+	result = acpi_bus_get_device(handle, &device);
+	if (0 != result) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Error getting context [%p]\n",
+			handle));
+		return_VALUE(result);
+	}
+
+	*resource = (struct acpi_power_resource *) acpi_driver_data(device);
+	if (!resource)
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_power_get_state (
+	struct acpi_power_resource *resource)
+{
+	acpi_status		status = AE_OK;
+	unsigned long		sta = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_power_get_state");
+
+	if (!resource)
+		return_VALUE(-EINVAL);
+
+	status = acpi_evaluate_integer(resource->handle, "_STA", NULL, &sta);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	if (sta & 0x01)
+		resource->state = ACPI_POWER_RESOURCE_STATE_ON;
+	else
+		resource->state = ACPI_POWER_RESOURCE_STATE_OFF;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] is %s\n",
+		resource->name, resource->state?"on":"off"));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_power_get_list_state (
+	struct acpi_handle_list	*list,
+	int			*state)
+{
+	int			result = 0;
+	struct acpi_power_resource *resource = NULL;
+	u32			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_power_get_list_state");
+
+	if (!list || !state)
+		return_VALUE(-EINVAL);
+
+	/* The state of the list is 'on' IFF all resources are 'on'. */
+
+	for (i=0; i<list->count; i++) {
+		result = acpi_power_get_context(list->handles[i], &resource);
+		if (0 != result)
+			return_VALUE(result);
+		result = acpi_power_get_state(resource);
+		if (0 != result)
+			return_VALUE(result);
+
+		*state = resource->state;
+
+		if (*state != ACPI_POWER_RESOURCE_STATE_ON)
+			break;
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource list is %s\n",
+		*state?"on":"off"));
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_power_on (
+	acpi_handle		handle)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_device	*device = NULL;
+	struct acpi_power_resource *resource = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_power_on");
+
+	result = acpi_power_get_context(handle, &resource);
+	if (0 != result)
+		return_VALUE(result);
+
+	resource->references++;
+
+	if ((resource->references > 1) 
+		|| (resource->state == ACPI_POWER_RESOURCE_STATE_ON)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] already on\n",
+			resource->name));
+		return_VALUE(0);
+	}
+
+	status = acpi_evaluate(resource->handle, "_ON", NULL, NULL);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	result = acpi_power_get_state(resource);
+	if (0 != result)
+		return_VALUE(result);
+	if (resource->state != ACPI_POWER_RESOURCE_STATE_ON)
+		return_VALUE(-ENOEXEC);
+
+	/* Update the power resource's _device_ power state */
+	result = acpi_bus_get_device(resource->handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+	device->power.state = ACPI_STATE_D0;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] turned on\n",
+		resource->name));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_power_off (
+	acpi_handle		handle)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_device	*device = NULL;
+	struct acpi_power_resource *resource = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_power_off");
+
+	result = acpi_power_get_context(handle, &resource);
+	if (0 != result)
+		return_VALUE(result);
+
+	if (resource->references)
+		resource->references--;
+
+	if (resource->references) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, 
+			"Resource [%s] is still in use, dereferencing\n",
+			device->pnp.bus_id));
+		return_VALUE(0);
+	}
+
+	if (resource->state == ACPI_POWER_RESOURCE_STATE_OFF) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] already off\n",
+			device->pnp.bus_id));
+		return_VALUE(0);
+	}
+
+	status = acpi_evaluate(resource->handle, "_OFF", NULL, NULL);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	result = acpi_power_get_state(resource);
+	if (0 != result)
+		return_VALUE(result);
+	if (resource->state != ACPI_POWER_RESOURCE_STATE_OFF)
+		return_VALUE(-ENOEXEC);
+
+	/* Update the power resource's _device_ power state */
+	result = acpi_bus_get_device(resource->handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+	device->power.state = ACPI_STATE_D3;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resource [%s] turned off\n",
+		resource->name));
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                             Device Power Management
+   -------------------------------------------------------------------------- */
+
+int
+acpi_power_get_inferred_state (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	struct acpi_handle_list	*list = NULL;
+	int			list_state = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_power_get_inferred_state");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	device->power.state = ACPI_STATE_UNKNOWN;
+
+	/*
+	 * We know a device's inferred power state when all the resources
+	 * required for a given D-state are 'on'.
+	 */
+	for (i=ACPI_STATE_D0; i<ACPI_STATE_D3; i++) {
+		list = &device->power.states[i].resources;
+		if (list->count < 1)
+			continue;
+
+		result = acpi_power_get_list_state(list, &list_state);
+		if (0 != result)
+			return_VALUE(result);
+
+		if (list_state == ACPI_POWER_RESOURCE_STATE_ON) {
+			device->power.state = i;
+			return_VALUE(0);
+		}
+	}
+
+	device->power.state = ACPI_STATE_D3;
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_power_transition (
+	struct acpi_device	*device,
+	int			state)
+{
+	int			result = 0;
+	struct acpi_handle_list	*cl = NULL;	/* Current Resources */
+	struct acpi_handle_list	*tl = NULL;	/* Target Resources */
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_power_transition");
+
+	if (!device || (state < ACPI_STATE_D0) || (state > ACPI_STATE_D3))
+		return_VALUE(-EINVAL);
+
+	cl = &device->power.states[device->power.state].resources;
+	tl = &device->power.states[state].resources;
+
+	device->power.state = ACPI_STATE_UNKNOWN;
+
+	if (!cl->count && !tl->count) {
+		result = -ENODEV;
+		goto end;
+	}
+
+	/* TBD: Resources must be ordered. */
+
+	/*
+	 * First we reference all power resources required in the target list
+	 * (e.g. so the device doesn't loose power while transitioning).
+	 */
+	for (i=0; i<tl->count; i++) {
+		result = acpi_power_on(tl->handles[i]);
+		if (0 != result)
+			goto end;
+	}
+
+	device->power.state = state;
+
+	/*
+	 * Then we dereference all power resources used in the current list.
+	 */
+	for (i=0; i<cl->count; i++) {
+		result = acpi_power_off(cl->handles[i]);
+		if (0 != result)
+			goto end;
+	}
+
+end:
+	if (0 != result)
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, 
+			"Error transitioning device [%s] to D%d\n",
+			device->pnp.bus_id, state));
+
+	return_VALUE(result);
+}
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_power_dir = NULL;
+
+
+static int
+acpi_power_read_status (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_power_resource *resource = NULL;
+	char			*p = page;
+	int			len;
+
+	ACPI_FUNCTION_TRACE("acpi_power_read_status");
+
+	if (!data || (off != 0))
+		goto end;
+
+	resource = (struct acpi_power_resource *) data;
+
+	p += sprintf(p, "state:                   ");
+	switch (resource->state) {
+	case ACPI_POWER_RESOURCE_STATE_ON:
+		p += sprintf(p, "on\n");
+		break;
+	case ACPI_POWER_RESOURCE_STATE_OFF:
+		p += sprintf(p, "off\n");
+		break;
+	default:
+		p += sprintf(p, "unknown\n");
+		break;
+	}
+
+	p += sprintf(p, "system level:            S%d\n",
+		resource->system_level);
+	p += sprintf(p, "order:                   %d\n",
+		resource->order);
+	p += sprintf(p, "reference count:         %d\n",
+		resource->references);
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_power_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_power_add_fs");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	if (!acpi_power_dir) {
+		acpi_power_dir = proc_mkdir(ACPI_POWER_CLASS, acpi_root_dir);
+		if (!acpi_power_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_power_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'status' [R] */
+	entry = create_proc_entry(ACPI_POWER_FILE_STATUS,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_POWER_FILE_STATUS));
+	else {
+		entry->read_proc = acpi_power_read_status;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_power_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_power_remove_fs");
+
+	if (!acpi_power_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_power_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                Driver Interface
+   -------------------------------------------------------------------------- */
+
+int
+acpi_power_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_power_resource *resource = NULL;
+	acpi_object		acpi_object;
+	acpi_buffer		buffer = {sizeof(acpi_object), &acpi_object};
+
+	ACPI_FUNCTION_TRACE("acpi_power_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	resource = kmalloc(sizeof(struct acpi_power_resource), GFP_KERNEL);
+	if (!resource)
+		return_VALUE(-ENOMEM);
+	memset(resource, 0, sizeof(struct acpi_power_resource));
+
+	resource->handle = device->handle;
+	sprintf(resource->name, "%s", device->pnp.bus_id);
+	sprintf(acpi_device_name(device), "%s", ACPI_POWER_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_POWER_CLASS);
+	acpi_driver_data(device) = resource;
+
+	/* Evalute the object to get the system level and resource order. */
+	status = acpi_evaluate_object(resource->handle, NULL, NULL, &buffer);
+	if (ACPI_FAILURE(status)) {
+		result = -ENODEV;
+		goto end;
+	}
+	resource->system_level = acpi_object.power_resource.system_level;
+	resource->order = acpi_object.power_resource.resource_order;
+
+	result = acpi_power_get_state(resource);
+	if (0 != result)
+		goto end;
+
+	switch (resource->state) {
+	case ACPI_POWER_RESOURCE_STATE_ON:
+		device->power.state = ACPI_STATE_D0;
+		break;
+	case ACPI_POWER_RESOURCE_STATE_OFF:
+		device->power.state = ACPI_STATE_D3;
+		break;
+	default:
+		device->power.state = ACPI_STATE_UNKNOWN;
+		break;
+	}
+
+	result = acpi_power_add_fs(device);
+	if (0 != result)
+		goto end;
+	
+	printk(KERN_INFO PREFIX "%s [%s] (%s)\n", acpi_device_name(device),
+		acpi_device_bid(device), resource->state?"on":"off");
+
+end:
+	if (0 != result)
+		kfree(resource);
+	
+	return_VALUE(result);
+}
+
+
+int
+acpi_power_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	struct acpi_power_resource *resource = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_power_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	resource = (struct acpi_power_resource *) acpi_driver_data(device);
+
+	acpi_power_remove_fs(device);
+
+	kfree(resource);
+
+	return_VALUE(0);
+}
+
+
+int __init
+acpi_power_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_power_init");
+
+	INIT_LIST_HEAD(&acpi_power_resource_list);
+
+	result = acpi_bus_register_driver(&acpi_power_driver);
+	if (0 > result) {
+		remove_proc_entry(ACPI_POWER_CLASS, acpi_root_dir);
+		return_VALUE(-ENODEV);
+	}
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_power_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_power_exit");
+
+	/* TBD: Empty acpi_power_resource_list */
+
+	result = acpi_bus_unregister_driver(&acpi_power_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_POWER_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
diff -Nru a/drivers/acpi/acpi_processor.c b/drivers/acpi/acpi_processor.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_processor.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1870 @@
+/*
+ * acpi_processor.c - ACPI Processor Driver ($Revision: 50 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *  TBD:
+ *	1. Make # power/performance states dynamic.
+ *	2. Includes support for _real_ performance states (not just throttle).
+ *	3. Support duty_cycle values that span bit 4.
+ *	4. Optimize by having scheduler determine business instead of
+ *         having us try to calculate it here.
+ *      5. Need C1 timing -- must modify kernel (IRQ handler) to get this.
+ *	6. Convert time values to ticks (initially) to avoid having to do
+ *         the math (acpi_get_timer_duration).
+ *      7. What is a good default value for the OS busy_metric?
+ *      8. Support both thermal and power limits.
+ *      9. Resolve PIIX4 BMISX errata issue (getting an I/O port value of 0).
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/pm.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_PROCESSOR_COMPONENT
+ACPI_MODULE_NAME		("acpi_processor")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_PROCESSOR_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+#define PREFIX				"ACPI: "
+
+
+#define ACPI_PROCESSOR_MAX_POWER	ACPI_C_STATE_COUNT
+#define ACPI_PROCESSOR_MAX_C2_LATENCY	100
+#define ACPI_PROCESSOR_MAX_C3_LATENCY	1000
+
+#define ACPI_PROCESSOR_MAX_PERFORMANCE	4
+
+#define ACPI_PROCESSOR_MAX_THROTTLING	16
+#define ACPI_PROCESSOR_MAX_THROTTLE	500	/* 50% */
+#define ACPI_PROCESSOR_MAX_DUTY_WIDTH	4
+
+const u32 POWER_OF_2[] = {1,2,4,8,16,32,64};
+
+#define ACPI_PROCESSOR_MAX_LIMIT	20
+
+static int acpi_processor_add (struct acpi_device *device);
+static int acpi_processor_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_processor_driver = {
+	name:			ACPI_PROCESSOR_DRIVER_NAME,
+	class:			ACPI_PROCESSOR_CLASS,
+	ids:			ACPI_PROCESSOR_HID,
+	ops:			{
+					add:	acpi_processor_add,
+					remove:	acpi_processor_remove,
+				},
+};
+
+/* Power Management */
+
+struct acpi_processor_cx_policy {
+	u32			count;
+	int			state;
+	struct {
+		u32			time;
+		u32			count;
+		u32			bm;
+	}			threshold;
+};
+
+struct acpi_processor_cx {
+	u8			valid;
+	u32			address;
+	u32			latency;
+	u32			power;
+	u32			usage;
+	struct acpi_processor_cx_policy promotion;
+	struct acpi_processor_cx_policy demotion;
+};
+
+struct acpi_processor_power {
+	int			state;
+	int			default_state;
+	u32			bm_activity;
+	u32			busy_metric;
+	struct acpi_processor_cx states[ACPI_PROCESSOR_MAX_POWER];
+};
+
+/* Performance Management */
+
+struct acpi_processor_px {
+	u8			valid;
+	u32			core_frequency;
+	u32			power;
+	u32			transition_latency;
+	u32			bus_master_latency;
+	u32			control;
+	u32			status;
+};
+
+struct acpi_processor_performance {
+	int			state;
+	int			state_count;
+	struct acpi_processor_px states[ACPI_PROCESSOR_MAX_PERFORMANCE];
+};
+
+
+/* Throttling Control */
+
+struct acpi_processor_tx {
+	u8			valid;
+	u16			power;
+	u16			performance;
+};
+
+struct acpi_processor_throttling {
+	int			state;
+	u32			address;
+	u8			duty_offset;
+	u8			duty_width;
+	int			state_count;
+	struct acpi_processor_tx states[ACPI_PROCESSOR_MAX_THROTTLING];
+};
+
+/* Limit Interface */
+
+struct acpi_processor_lx {
+	u8			valid;
+	u16			performance;
+	int			px;
+	int			tx;
+};
+
+struct acpi_processor_limit {
+	int			state;
+	int			state_count;
+	struct {
+		u8			valid;
+		u16			performance;
+		int			px;
+		int			tx;
+	}			states[ACPI_PROCESSOR_MAX_LIMIT];
+};
+
+struct acpi_processor_flags {
+	u8			bm_control:1;
+	u8			power:1;
+	u8			performance:1;
+	u8			throttling:1;
+	u8			limit:1;
+	u8			reserved:3;
+};
+
+struct acpi_processor_errata {
+	struct {
+		u8			reverse_throttle;
+		u32			bmisx;
+	}			piix4;
+};
+
+struct acpi_processor {
+	acpi_handle		handle;
+	u32			acpi_id;
+	u32			id;
+	struct acpi_processor_flags flags;
+	struct acpi_processor_errata errata;
+	struct acpi_processor_power power;
+	struct acpi_processor_performance performance;
+	struct acpi_processor_throttling throttling;
+	struct acpi_processor_limit limit;
+};
+
+
+static u8			acpi_processor_smp = 0;
+
+
+/* --------------------------------------------------------------------------
+                                Errata Handling
+   -------------------------------------------------------------------------- */
+
+int
+acpi_processor_get_errata (
+	struct acpi_processor	*pr)
+{
+	struct pci_dev		*dev = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_errata");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	/*
+	 * PIIX4
+	 * -----
+	 */
+	dev = pci_find_subsys(PCI_VENDOR_ID_INTEL,
+		PCI_DEVICE_ID_INTEL_82371AB_3, PCI_ANY_ID, PCI_ANY_ID, dev);
+	if (dev) {
+		u8		rev = 0;
+
+		pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
+
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "PIIX4 ACPI rev %d\n", rev));
+
+		switch (rev) {
+
+		case 0:		/* PIIX4 A-step */
+		case 1:		/* PIIX4 B-step */
+			/*
+			 * Workaround for reverse-notation on throttling states
+			 * used by early PIIX4 models.
+			 */
+			pr->errata.piix4.reverse_throttle = 1;
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+				"Reverse-throttle errata enabled\n"));
+
+		case 2:		/* PIIX4E */
+		case 3:		/* PIIX4M */
+			/*
+			 * Workaround for errata #18 "C3 Power State/BMIDE and
+			 * Type-F DMA Livelock" from the July 2001 PIIX4
+			 * specification update.  Applies to all PIIX4 models.
+			 */
+			/* TBD: Why is the bmisx value always ZERO? */
+			pr->errata.piix4.bmisx = pci_resource_start(dev, 4);
+			if (pr->errata.piix4.bmisx)
+				ACPI_DEBUG_PRINT((ACPI_DB_INFO, 
+					"BM-IDE errata enabled\n"));
+			break;
+		}
+	}
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                Power Management
+   -------------------------------------------------------------------------- */
+
+static struct acpi_processor *acpi_processor_list[NR_CPUS];
+static void (*pm_idle_save)(void) = NULL;
+
+static void
+acpi_processor_power_activate (
+	struct acpi_processor	*pr,
+	int			state)
+{
+	if (!pr)
+		return;
+
+	pr->power.states[pr->power.state].promotion.count = 0;
+	pr->power.states[pr->power.state].demotion.count = 0;
+
+	/* Cleanup from old state. */
+	switch (pr->power.state) {
+	case ACPI_STATE_C3:
+		/* Disable bus master reload */
+		acpi_hw_bit_register_write(ACPI_BITREG_BUS_MASTER_RLD, 0, ACPI_MTX_DO_NOT_LOCK);
+		break;
+	}
+
+	/* Prepare to use new state. */
+	switch (state) {
+	case ACPI_STATE_C3:
+		/* Enable bus master reload */
+		acpi_hw_bit_register_write(ACPI_BITREG_BUS_MASTER_RLD, 1, ACPI_MTX_DO_NOT_LOCK);
+		break;
+	}
+
+	pr->power.state = state;
+
+	return;
+}
+
+
+static void
+acpi_processor_idle (void)
+{
+	struct acpi_processor	*pr = NULL;
+	struct acpi_processor_cx *cx = NULL;
+	int			next_state = 0;
+	u32			start_ticks = 0;
+	u32			end_ticks = 0;
+	u32			time_elapsed = 0;
+	static unsigned long	last_idle_jiffies = 0;
+
+	pr = acpi_processor_list[smp_processor_id()];
+	if (!pr)
+		return;
+
+	/*
+	 * Interrupts must be disabled during bus mastering calculations and
+	 * for C2/C3 transitions.
+	 */
+	__cli();
+
+	next_state = pr->power.state;
+
+	/*
+	 * Check OS Idleness:
+	 * ------------------
+	 * If the OS has been busy (hasn't called the idle handler in a while)
+	 * then automatically demote to the default power state (e.g. C1).
+	 *
+	 * TBD: Optimize by having scheduler determine business instead
+	 *      of having us try to calculate it here.
+	 */
+	if (pr->power.state != pr->power.default_state) {
+		if ((jiffies - last_idle_jiffies) >= pr->power.busy_metric) {
+			next_state = pr->power.default_state;
+			if (next_state != pr->power.state)
+				acpi_processor_power_activate(pr, next_state);
+		}
+	}
+
+	/*
+	 * Log BM Activity:
+	 * ----------------
+	 * Read BM_STS and record its value for later use by C3 policy.
+	 * (Note that we save the BM_STS values for the last 32 cycles).
+	 */
+	if (pr->flags.bm_control) {
+		pr->power.bm_activity <<= 1;
+		if (acpi_hw_bit_register_read(ACPI_BITREG_BUS_MASTER_STATUS, ACPI_MTX_DO_NOT_LOCK)) {
+			pr->power.bm_activity |= 1;
+			acpi_hw_bit_register_write(ACPI_BITREG_BUS_MASTER_STATUS,
+				1, ACPI_MTX_DO_NOT_LOCK);
+		}
+		/*
+		 * PIIX4 Errata:
+		 * -------------
+		 * This code is a workaround for errata #18 "C3 Power State/
+		 * BMIDE and Type-F DMA Livelock" from the July '01 PIIX4
+		 * specification update.  Note that BM_STS doesn't always
+		 * reflect the true state of bus mastering activity; forcing
+		 * us to manually check the BMIDEA bit of each IDE channel.
+		 */
+		else if (pr->errata.piix4.bmisx) {
+			if ((inb_p(pr->errata.piix4.bmisx + 0x02) & 0x01) ||
+				(inb_p(pr->errata.piix4.bmisx + 0x0A) & 0x01))
+				pr->power.bm_activity |= 1;
+		}
+	}
+
+	cx = &(pr->power.states[pr->power.state]);
+	cx->usage++;
+
+	/*
+	 * Sleep:
+	 * ------
+	 * Invoke the current Cx state to put the processor to sleep.
+	 */
+	switch (pr->power.state) {
+
+	case ACPI_STATE_C1:
+		/* Invoke C1. */
+		safe_halt();
+		/*
+                 * TBD: Can't get time duration while in C1, as resumes
+		 *      go to an ISR rather than here.  Need to instrument
+		 *      base interrupt handler.
+		 */
+		time_elapsed = 0xFFFFFFFF;
+		break;
+
+	case ACPI_STATE_C2:
+		/* See how long we're asleep for */
+		start_ticks = inl(acpi_fadt.Xpm_tmr_blk.address);
+		/* Invoke C2 */
+		inb(pr->power.states[ACPI_STATE_C2].address);
+		/* Dummy op - must do something useless after P_LVL2 read */
+		end_ticks = inl(acpi_fadt.Xpm_tmr_blk.address);
+		/* Compute time elapsed */
+		end_ticks = inl(acpi_fadt.Xpm_tmr_blk.address);
+		/* Re-enable interrupts */
+		__sti();
+		/*
+		 * Compute the amount of time asleep (in the Cx state).
+		 * TBD: Convert to PM timer ticks initially to avoid having
+		 *      to do the math (acpi_get_timer_duration).
+		 */
+		acpi_get_timer_duration(start_ticks, end_ticks, &time_elapsed);
+		break;
+
+	case ACPI_STATE_C3:
+		/* Disable bus master arbitration */
+		acpi_hw_bit_register_write(ACPI_BITREG_ARB_DISABLE, 1, ACPI_MTX_DO_NOT_LOCK);
+		/* See how long we're asleep for */
+		start_ticks = inl(acpi_fadt.Xpm_tmr_blk.address);
+		/* Invoke C2 */
+		inb(pr->power.states[ACPI_STATE_C3].address);
+		/* Dummy op - must do something useless after P_LVL3 read */
+		end_ticks = inl(acpi_fadt.Xpm_tmr_blk.address);
+		/* Compute time elapsed */
+		end_ticks = inl(acpi_fadt.Xpm_tmr_blk.address);
+		/* Enable bus master arbitration */
+		acpi_hw_bit_register_write(ACPI_BITREG_ARB_DISABLE, 0, ACPI_MTX_DO_NOT_LOCK);
+		/* Re-enable interrupts */
+		__sti();
+		/*
+		 * Compute the amount of time asleep (in the Cx state).
+		 * TBD: Convert to PM timer ticks initially to avoid having
+		 *      to do the math (acpi_get_timer_duration).
+		 */
+		acpi_get_timer_duration(start_ticks, end_ticks, &time_elapsed);
+		break;
+
+	default:
+		__sti();
+		return;
+	}
+
+	/*
+	 * Promotion?
+	 * ----------
+	 * Track the number of longs (time asleep is greater than threshold)
+	 * and promote when the count threshold is reached.  Note that bus
+	 * mastering activity may prevent promotions.
+	 */
+	if (cx->promotion.state) {
+		if (time_elapsed >= cx->promotion.threshold.time) {
+			cx->promotion.count++;
+ 			cx->demotion.count = 0;
+			if (cx->promotion.count >= cx->promotion.threshold.count) {
+				if (pr->flags.bm_control) {
+					if (!(pr->power.bm_activity & cx->promotion.threshold.bm))
+						next_state = cx->promotion.state;
+				}
+				else
+					next_state = cx->promotion.state;
+			}
+		}
+	}
+
+	/*
+	 * Demotion?
+	 * ---------
+	 * Track the number of shorts (time asleep is less than time threshold)
+	 * and demote when the usage threshold is reached.  Note that bus
+	 * mastering activity may cause immediate demotions.
+	 */
+	if (cx->demotion.state) {
+		if (time_elapsed < cx->demotion.threshold.time) {
+			cx->demotion.count++;
+			cx->promotion.count = 0;
+			if (cx->demotion.count >= cx->demotion.threshold.count)
+				next_state = cx->demotion.state;
+		}
+		if (pr->flags.bm_control) {
+			if (pr->power.bm_activity & cx->demotion.threshold.bm)
+				next_state = cx->demotion.state;
+		}
+	}
+
+	/*
+	 * New Cx State?
+	 * -------------
+	 * If we're going to start using a new Cx state we must clean up
+	 * from the previous and prepare to use the new.
+	 */
+	if (next_state != pr->power.state)
+		acpi_processor_power_activate(pr, next_state);
+
+	/*
+	 * Track OS Idleness:
+	 * ------------------
+	 * Record a jiffies timestamp to compute time elapsed between calls
+	 * to the idle handler.
+	 */
+	last_idle_jiffies = jiffies;
+
+	return;
+}
+
+
+static int
+acpi_processor_set_power_policy (
+	struct acpi_processor	*pr)
+{
+	ACPI_FUNCTION_TRACE("acpi_processor_set_power_policy");
+
+	/*
+	 * This function sets the default Cx state policy (OS idle handler).
+	 * Our scheme is to promote quickly to C2 but more conservatively
+	 * to C3.  We're favoring C2  for its characteristics of low latency
+	 * (quick response), good power savings, and ability to allow bus
+	 * mastering activity.  Note that the Cx state policy is completely
+	 * customizable and can be altered dynamically.
+	 */
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	/*
+	 * The Busy Metric is used to determine when the OS has been busy
+	 * and thus when policy should return to using the default Cx state
+	 * (e.g. C1).  On Linux we use the number of jiffies (scheduler
+	 * quantums) that transpire between calls to the idle handler.
+	 *
+	 * TBD: What is a good value for the OS busy_metric?
+	 */
+	pr->power.busy_metric = 2;
+
+	/*
+	 * C0/C1
+	 * -----
+	 */
+	if (pr->power.states[ACPI_STATE_C1].valid) {
+		pr->power.state = ACPI_STATE_C1;
+		pr->power.default_state = ACPI_STATE_C1;
+	}
+	else {
+		pr->power.state = ACPI_STATE_C0;
+		pr->power.default_state = ACPI_STATE_C0;
+		return_VALUE(0);
+	}
+
+	/*
+	 * C1/C2
+	 * -----
+	 * Set the default C1 promotion and C2 demotion policies, where we
+	 * promote from C1 to C2 anytime we're asleep in C1 for longer than
+	 * two times the C2 latency (to amortize cost of transitions). Demote
+	 * from C2 to C1 anytime we're asleep in C2 for less than this time.
+	 */
+	if (pr->power.states[ACPI_STATE_C2].valid) {
+		pr->power.states[ACPI_STATE_C1].promotion.threshold.count = 10;
+		pr->power.states[ACPI_STATE_C1].promotion.threshold.time =
+			(2 * pr->power.states[ACPI_STATE_C2].latency);
+		pr->power.states[ACPI_STATE_C1].promotion.state = ACPI_STATE_C2;
+
+		pr->power.states[ACPI_STATE_C2].demotion.threshold.count = 1;
+		pr->power.states[ACPI_STATE_C2].demotion.threshold.time =
+			(2 * pr->power.states[ACPI_STATE_C2].latency);
+		pr->power.states[ACPI_STATE_C2].demotion.state = ACPI_STATE_C1;
+	}
+
+	/*
+	 * C2/C3
+	 * -----
+	 * Set default C2 promotion and C3 demotion policies, where we promote
+	 * from C2 to C3 after 4 cycles (0x0F) of no bus mastering activity
+	 * (while maintaining sleep time criteria).  Demote immediately on a
+	 * short or whenever bus mastering activity occurs.
+	 */
+	if ((pr->power.states[ACPI_STATE_C2].valid) &&
+		(pr->power.states[ACPI_STATE_C3].valid)) {
+		pr->power.states[ACPI_STATE_C2].promotion.threshold.count = 1;
+		pr->power.states[ACPI_STATE_C2].promotion.threshold.time =
+			(2 * pr->power.states[ACPI_STATE_C3].latency);
+		pr->power.states[ACPI_STATE_C2].promotion.threshold.bm = 0x0F;
+		pr->power.states[ACPI_STATE_C2].promotion.state = ACPI_STATE_C3;
+
+		pr->power.states[ACPI_STATE_C3].demotion.threshold.count = 1;
+		pr->power.states[ACPI_STATE_C3].demotion.threshold.time =
+			(2 * pr->power.states[ACPI_STATE_C3].latency);
+		pr->power.states[ACPI_STATE_C3].demotion.threshold.bm = 0x0F;
+		pr->power.states[ACPI_STATE_C3].demotion.state = ACPI_STATE_C2;
+	}
+
+	return_VALUE(0);
+}
+
+
+int
+acpi_processor_get_power_info (
+	struct acpi_processor	*pr)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_power_info");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		"lvl2[0x%08x] lvl3[0x%08x]\n",
+		pr->power.states[ACPI_STATE_C2].address,
+		pr->power.states[ACPI_STATE_C3].address));
+
+	/* TBD: Support ACPI 2.0 objects */
+
+	/*
+	 * C0
+	 * --
+	 * This state exists only as filler in our array.
+	 */
+	pr->power.states[ACPI_STATE_C0].valid = TRUE;
+
+	/*
+	 * C1
+	 * --
+	 * ACPI requires C1 support for all processors.
+	 *
+	 * TBD: What about PROC_C1?
+	 */
+	pr->power.states[ACPI_STATE_C1].valid = TRUE;
+
+	/*
+	 * C2
+	 * --
+	 * We're (currently) only supporting C2 on UP systems.
+	 *
+	 * TBD: Support for C2 on MP (P_LVL2_UP).
+	 */
+	if (pr->power.states[ACPI_STATE_C2].address) {
+		pr->power.states[ACPI_STATE_C2].latency = acpi_fadt.plvl2_lat;
+		if (acpi_fadt.plvl2_lat > ACPI_PROCESSOR_MAX_C2_LATENCY)
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+				"C2 latency too large [%d]\n",
+				acpi_fadt.plvl2_lat));
+		else if (!acpi_processor_smp)
+			pr->power.states[ACPI_STATE_C2].valid = TRUE;
+	}
+
+	/*
+	 * C3
+	 * --
+	 * We're (currently) only supporting C3 on UP systems that include
+	 * bus mastering arbitration control.  Note that this method of
+	 * maintaining cache coherency (disabling of bus mastering) cannot be
+	 * used on SMP systems, and flushing caches (e.g. WBINVD) is simply
+	 * too costly (at this time).
+	 */
+	if (pr->power.states[ACPI_STATE_C3].address) {
+		pr->power.states[ACPI_STATE_C3].latency = acpi_fadt.plvl3_lat;
+		if (acpi_fadt.plvl3_lat > ACPI_PROCESSOR_MAX_C3_LATENCY)
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+				"C3 latency too large [%d]\n", 
+				acpi_fadt.plvl3_lat));
+		else if (!acpi_processor_smp && pr->flags.bm_control)
+			pr->power.states[ACPI_STATE_C3].valid = 1;
+	}
+
+	/*
+	 * Set Default Policy
+	 * ------------------
+	 * Now that we know which state are supported, set the default
+	 * policy.  Note that this policy can be changed dynamically
+	 * (e.g. encourage deeper sleeps to conserve battery life when
+	 * not on AC).
+	 */
+	result = acpi_processor_set_power_policy(pr);
+	if (0 != result)
+		return_VALUE(result);
+
+	/*
+	 * If this processor supports C2 or C3 we denote it as being 'power
+	 * manageable'.  Note that there's really no policy involved for
+	 * when only C1 is supported.
+	 */
+	if (pr->power.states[ACPI_STATE_C2].valid
+		|| pr->power.states[ACPI_STATE_C3].valid)
+		pr->flags.power = 1;
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                              Performance Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_processor_get_performance (
+	struct acpi_processor	*pr)
+{
+	ACPI_FUNCTION_TRACE("acpi_processor_get_performance_state");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	if (!pr->flags.performance)
+		return_VALUE(0);
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_processor_set_performance (
+	struct acpi_processor	*pr,
+	int			state)
+{
+	ACPI_FUNCTION_TRACE("acpi_processor_set_performance_state");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	if (!pr->flags.performance)
+		return_VALUE(-ENODEV);
+
+	if (state >= pr->performance.state_count)
+		return_VALUE(-ENODEV);
+
+	if (state == pr->performance.state)
+		return_VALUE(0);
+
+	/* TBD */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_processor_get_performance_info (
+	struct acpi_processor	*pr)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_performance_info");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	/* TBD: Support ACPI 2.0 objects */
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                              Throttling Control
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_processor_get_throttling (
+	struct acpi_processor	*pr)
+{
+	int			state = 0;
+	u32			value = 0;
+	u32			duty_mask = 0;
+	u32			duty_value = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_throttling");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	if (!pr->flags.throttling)
+		return_VALUE(-ENODEV);
+
+	pr->throttling.state = 0;
+
+	__cli();
+
+	duty_mask = pr->throttling.state_count - 1;
+	duty_mask <<= pr->throttling.duty_offset;
+
+	value = inb(pr->throttling.address);
+
+	/*
+	 * Compute the current throttling state when throttling is enabled
+	 * (bit 4 is on).  Note that the reverse_throttling flag indicates
+	 * that the duty_value is opposite of that specified by ACPI.
+	 */
+	if (value & 0x10) {
+		duty_value = value & duty_mask;
+		duty_value >>= pr->throttling.duty_offset;
+
+		if (duty_value) {
+			if (pr->errata.piix4.reverse_throttle)
+				state = duty_value;
+			else
+				state = pr->throttling.state_count-duty_value;
+		}
+	}
+
+	pr->throttling.state = state;
+
+	__sti();
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Throttling state is T%d (%d%% throttling applied)\n",
+		state, pr->throttling.states[state].performance));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_processor_set_throttling (
+	struct acpi_processor	*pr,
+	int			state)
+{
+	u32                     value = 0;
+	u32                     duty_mask = 0;
+	u32                     duty_value = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_set_throttling");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	if ((state < 0) || (state > (pr->throttling.state_count - 1)))
+		return_VALUE(-EINVAL);
+
+	if (!pr->flags.throttling || !pr->throttling.states[state].valid)
+		return_VALUE(-ENODEV);
+
+	if (state == pr->throttling.state)
+		return_VALUE(0);
+
+	__cli();
+
+	/*
+	 * Calculate the duty_value and duty_mask.  Note that the
+	 * reverse_throttling flag indicates that the duty_value is
+	 * opposite of that specified by ACPI.
+	 */
+	if (state) {
+		if (pr->errata.piix4.reverse_throttle)
+			duty_value = state;
+		else
+			duty_value = pr->throttling.state_count - state;
+
+		duty_value <<= pr->throttling.duty_offset;
+
+		/* Used to clear all duty_value bits */
+		duty_mask = pr->performance.state_count - 1;
+		duty_mask <<= acpi_fadt.duty_offset;
+		duty_mask = ~duty_mask;
+	}
+
+	/*
+	 * Disable throttling by writing a 0 to bit 4.  Note that we must
+	 * turn it off before you can change the duty_value.
+	 */
+	value = inb(pr->throttling.address);
+	if (value & 0x10) {
+		value &= 0xFFFFFFEF;
+		outl(value, pr->throttling.address);
+	}
+
+	/*
+	 * Write the new duty_value and then enable throttling.  Note
+	 * that a state value of 0 leaves throttling disabled.
+	 */
+	if (state) {
+		value &= duty_mask;
+		value |= duty_value;
+		outl(value, pr->throttling.address);
+
+		value |= 0x00000010;
+		outl(value, pr->throttling.address);
+	}
+
+	pr->throttling.state = state;
+
+	__sti();
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Throttling state set to T%d (%d%%)\n",
+		state, (pr->throttling.states[state].performance?pr->throttling.states[state].performance/10:0)));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_processor_get_throttling_info (
+	struct acpi_processor	*pr)
+{
+	int			result = 0;
+	int			step = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_throttling_info");
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+		"pblk_address[0x%08x] duty_offset[%d] duty_width[%d]\n",
+		pr->throttling.address,
+		pr->throttling.duty_offset,
+		pr->throttling.duty_width));
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	/* TBD: Support ACPI 2.0 objects */
+
+	if (!pr->throttling.address) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No throttling register\n"));
+		return_VALUE(0);
+	}
+	else if (!pr->throttling.duty_width) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid duty_width\n"));
+		return_VALUE(-EFAULT);
+	}
+	/* TBD: Support duty_cycle values that span bit 4. */
+	else if ((pr->throttling.duty_offset
+		+ pr->throttling.duty_width) > 4) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "duty_cycle spans bit 4\n"));
+		return_VALUE(0);
+	}
+
+	pr->throttling.state_count = POWER_OF_2[acpi_fadt.duty_width];
+
+	/*
+	 * Compute state values. Note that throttling displays a linear power/
+	 * performance relationship (at 50% performance the CPU will consume
+	 * 50% power).  Values are in 1/10th of a percent to preserve accuracy.
+	 */
+
+	step = (1000 / pr->throttling.state_count);
+
+	for (i=0; i<pr->throttling.state_count; i++) {
+		pr->throttling.states[i].performance = step * i;
+		pr->throttling.states[i].power = step * i;
+		pr->throttling.states[i].valid = 1;
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d throttling states\n", 
+		pr->throttling.state_count));
+
+	pr->flags.throttling = 1;
+
+	/*
+	 * Disable throttling (if enabled).  We'll let subsequent policy (e.g. 
+	 * thermal) decide to lower performance if it so chooses, but for now 
+	 * we'll crank up the speed.
+	 */
+
+	result = acpi_processor_get_throttling(pr);
+	if (0 != result)
+		goto end;
+
+	if (pr->throttling.state) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Disabling throttling (was T%d)\n", 
+			pr->throttling.state));
+		result = acpi_processor_set_throttling(pr, 0);
+		if (0 != result)
+			goto end;
+	}
+
+end:
+	if (0 != result)
+		pr->flags.throttling = 0;
+
+	return_VALUE(result);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Limit Interface
+   -------------------------------------------------------------------------- */
+
+int
+acpi_processor_set_limit (
+	acpi_handle		handle,
+	int			type,
+	int			*state)
+{
+	int			result = 0;
+	struct acpi_processor	*pr = NULL;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_set_limit");
+
+	if (!state)
+		return_VALUE(-EINVAL);
+
+	result = acpi_bus_get_device(handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	pr = (struct acpi_processor *) acpi_driver_data(device);
+	if (!pr)
+		return_VALUE(-ENODEV);
+
+	if (!pr->flags.limit)
+		return_VALUE(-ENODEV);
+
+	switch (type) {
+	case ACPI_PROCESSOR_LIMIT_NONE:
+		*state = 0;
+		pr->limit.state = 0;
+		break;
+	case ACPI_PROCESSOR_LIMIT_INCREMENT:
+		if (*state == (pr->limit.state_count - 1)) {
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Already at maximum limit state\n"));
+			return_VALUE(1);
+		}
+		*state = ++pr->limit.state;
+		break;
+	case ACPI_PROCESSOR_LIMIT_DECREMENT:
+		if (*state == 0) {
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Already at minimum limit state\n"));
+			return_VALUE(1);
+		}
+		*state = --pr->limit.state;
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid limit type [%d]\n",
+			type));
+		*state = pr->limit.state;
+		return_VALUE(-EINVAL);
+		break;
+	}
+
+	if (pr->flags.performance) {
+		result = acpi_processor_set_performance(pr, 
+			pr->limit.states[*state].px);
+		if (0 != result)
+			goto end;
+	}
+
+	if (pr->flags.throttling) {
+		result = acpi_processor_set_throttling(pr, 
+			pr->limit.states[*state].tx);
+		if (0 != result)
+			goto end;
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d] limit now %d%% (P%d:T%d)\n",
+		pr->id,
+		pr->limit.states[*state].performance / 10,
+		pr->limit.states[*state].px,
+		pr->limit.states[*state].tx));
+
+end:
+	if (0 != result)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Unable to set limit\n"));
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_processor_get_limit_info (
+	struct acpi_processor	*pr)
+{
+	int			i = 0;
+	int			px = 0;
+	int			tx = 0;
+	int			base_perf = 1000;
+	int			throttle = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_limit_info");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+	/*
+	 * Limit
+	 * -----
+	 * Our default policy is to only use throttling at the lowest
+	 * performance state.  This is enforced by adding throttling states 
+	 * after perormance states.  We also only expose throttling states 
+	 * less than the maximum throttle value (e.g. 50%).
+	 */
+
+	if (pr->flags.performance) {
+		for (px=0; px<pr->performance.state_count; px++) {
+			if (!pr->performance.states[px].valid)
+				continue;
+			i = pr->limit.state_count++;
+			pr->limit.states[i].px = px;
+			pr->limit.states[i].performance = (pr->performance.states[px].core_frequency / pr->performance.states[0].core_frequency) * 1000;
+			pr->limit.states[i].valid = 1;
+		}
+		px--;
+		base_perf = pr->limit.states[i].performance;
+	}
+
+	if (pr->flags.throttling) {
+		for (tx=0; tx<pr->throttling.state_count; tx++) {
+			if (!pr->throttling.states[tx].valid)
+				continue;
+			if (pr->throttling.states[tx].performance > ACPI_PROCESSOR_MAX_THROTTLE)
+				continue;
+			i = pr->limit.state_count++;
+			pr->limit.states[i].px = px;
+			pr->limit.states[i].tx = tx;
+			throttle = (base_perf * pr->throttling.states[tx].performance) / 1000;
+			pr->limit.states[i].performance = base_perf - throttle;
+			pr->limit.states[i].valid = 1;
+		}
+	}
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d limit states\n", 
+		pr->limit.state_count));
+
+	if (pr->limit.state_count)
+		pr->flags.limit = 1;
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_processor_dir = NULL;
+
+static int
+acpi_processor_read_info (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_read_info");
+
+	if (!pr || (off != 0))
+		goto end;
+
+	p += sprintf(p, "processor id:            %d\n",
+		pr->id);
+
+	p += sprintf(p, "acpi id:                 %d\n",
+		pr->acpi_id);
+
+	p += sprintf(p, "bus mastering control:   %s\n",
+		pr->flags.bm_control ? "yes" : "no");
+
+	p += sprintf(p, "power management:        %s\n",
+		pr->flags.power ? "yes" : "no");
+
+	p += sprintf(p, "throttling control:      %s\n",
+		pr->flags.throttling ? "yes" : "no");
+
+	p += sprintf(p, "performance management:  %s\n",
+		pr->flags.performance ? "yes" : "no");
+
+	p += sprintf(p, "limit interface:         %s\n",
+		pr->flags.limit ? "yes" : "no");
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_processor_read_power (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			*p = page;
+	int			len = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_read_power");
+
+	if (!pr || (off != 0))
+		goto end;
+
+	p += sprintf(p, "active state:            C%d\n",
+		pr->power.state);
+
+	p += sprintf(p, "default state:           C%d\n",
+		pr->power.default_state);
+
+	p += sprintf(p, "bus master activity:     %08x\n",
+		pr->power.bm_activity);
+
+	p += sprintf(p, "states:\n");
+
+	for (i=1; i<ACPI_C_STATE_COUNT; i++) {
+
+		p += sprintf(p, "   %cC%d:                  ", 
+			(i == pr->power.state?'*':' '), i);
+
+		if (!pr->power.states[i].valid) {
+			p += sprintf(p, "<not supported>\n");
+			continue;
+		}
+
+		if (pr->power.states[i].promotion.state)
+			p += sprintf(p, "promotion[C%d] ",
+				pr->power.states[i].promotion.state);
+		else
+			p += sprintf(p, "promotion[--] ");
+
+		if (pr->power.states[i].demotion.state)
+			p += sprintf(p, "demotion[C%d] ",
+				pr->power.states[i].demotion.state);
+		else
+			p += sprintf(p, "demotion[--] ");
+
+		p += sprintf(p, "latency[%03d] usage[%08d]\n",
+			pr->power.states[i].latency,
+			pr->power.states[i].usage);
+	}
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_processor_read_performance (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			*p = page;
+	int			len = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_read_performance");
+
+	if (!pr || (off != 0))
+		goto end;
+
+	if (!pr->flags.performance) {
+		p += sprintf(p, "<not supported>\n");
+		goto end;
+	}
+
+	p += sprintf(p, "state count:             %d\n",
+		pr->performance.state_count);
+
+	p += sprintf(p, "active state:            P%d\n",
+		pr->performance.state);
+
+	p += sprintf(p, "states:\n");
+
+	for (i=0; i<pr->performance.state_count; i++)
+		p += sprintf(p, "   %cP%d:                %d Mhz, %d mW %s\n",
+			(i == pr->performance.state?'*':' '), i,
+			pr->performance.states[i].core_frequency,
+			pr->performance.states[i].power,
+			(pr->performance.states[i].valid?"":"(disabled)"));
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_processor_write_performance (
+        struct file		*file,
+        const char		*buffer,
+        unsigned long		count,
+        void			*data)
+{
+	int			result = 0;
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			state_string[12] = {'\0'};
+
+	ACPI_FUNCTION_TRACE("acpi_processor_write_performance");
+
+	if (!pr || (count > sizeof(state_string) - 1))
+		return_VALUE(-EINVAL);
+	
+	if (copy_from_user(state_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	state_string[count] = '\0';
+	
+	result = acpi_processor_set_throttling(pr, 
+		simple_strtoul(state_string, NULL, 0));
+	if (0 != result)
+		return_VALUE(result);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_processor_read_throttling (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			*p = page;
+	int			len = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_read_throttling");
+
+	if (!pr || (off != 0))
+		goto end;
+
+	if (!(pr->throttling.state_count > 0)) {
+		p += sprintf(p, "<not supported>\n");
+		goto end;
+	}
+
+	p += sprintf(p, "state count:             %d\n",
+		pr->throttling.state_count);
+
+	p += sprintf(p, "active state:            T%d\n",
+		pr->throttling.state);
+
+	p += sprintf(p, "states:\n");
+
+	for (i=0; i<pr->throttling.state_count; i++)
+		p += sprintf(p, "   %cT%d:                  %02d%% %s\n",
+			(i == pr->throttling.state?'*':' '), i,
+			(pr->throttling.states[i].performance?pr->throttling.states[i].performance/10:0),
+			(pr->throttling.states[i].valid?"":"(disabled)"));
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_processor_write_throttling (
+        struct file		*file,
+        const char		*buffer,
+        unsigned long		count,
+        void			*data)
+{
+	int			result = 0;
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			state_string[12] = {'\0'};
+
+	ACPI_FUNCTION_TRACE("acpi_processor_write_throttling");
+
+	if (!pr || (count > sizeof(state_string) - 1))
+		return_VALUE(-EINVAL);
+	
+	if (copy_from_user(state_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	state_string[count] = '\0';
+	
+	result = acpi_processor_set_throttling(pr, 
+		simple_strtoul(state_string, NULL, 0));
+	if (0 != result)
+		return_VALUE(result);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_processor_read_limit (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			*p = page;
+	int			len = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_read_limit");
+
+	if (!pr || (off != 0))
+		goto end;
+
+	if (!pr->flags.limit) {
+		p += sprintf(p, "<not supported>\n");
+		goto end;
+	}
+
+	p += sprintf(p, "state count:             %d\n",
+		pr->limit.state_count);
+
+	p += sprintf(p, "active state:            L%d\n",
+		pr->limit.state);
+
+	p += sprintf(p, "states:\n");
+
+	for (i=0; i<pr->limit.state_count; i++)
+		p += sprintf(p, "   %cL%d:                  %02d%% [P%d:T%d] %s\n",
+			(i == pr->limit.state?'*':' '),
+			i,
+			pr->limit.states[i].performance / 10,
+			pr->limit.states[i].px,
+			pr->limit.states[i].tx,
+			pr->limit.states[i].valid?"":"(disabled)");
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_processor_write_limit (
+        struct file		*file,
+        const char		*buffer,
+        unsigned long		count,
+        void			*data)
+{
+	int			result = 0;
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	char			limit_string[12] = {'\0'};
+	int			limit = 0;
+	int			state = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_write_limit");
+
+	if (!pr || (count > sizeof(limit_string) - 1))
+		return_VALUE(-EINVAL);
+	
+	if (copy_from_user(limit_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	limit_string[count] = '\0';
+
+	limit = simple_strtoul(limit_string, NULL, 0);
+	
+	result = acpi_processor_set_limit(pr->handle, limit, &state);
+	if (0 != result)
+		return_VALUE(result);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_processor_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_add_fs");
+
+	if (!acpi_processor_dir) {
+		acpi_processor_dir = proc_mkdir(ACPI_PROCESSOR_CLASS, 
+			acpi_root_dir);
+		if (!acpi_processor_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_processor_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'info' [R] */
+	entry = create_proc_entry(ACPI_PROCESSOR_FILE_INFO,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_PROCESSOR_FILE_INFO));
+	else {
+		entry->read_proc = acpi_processor_read_info;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'power' [R] */
+	entry = create_proc_entry(ACPI_PROCESSOR_FILE_POWER,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_PROCESSOR_FILE_POWER));
+	else {
+		entry->read_proc = acpi_processor_read_power;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'performance' [R/W] */
+	entry = create_proc_entry(ACPI_PROCESSOR_FILE_PERFORMANCE,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_PROCESSOR_FILE_PERFORMANCE));
+	else {
+		entry->read_proc = acpi_processor_read_performance;
+		entry->write_proc = acpi_processor_write_performance;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'throttling' [R/W] */
+	entry = create_proc_entry(ACPI_PROCESSOR_FILE_THROTTLING,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_PROCESSOR_FILE_THROTTLING));
+	else {
+		entry->read_proc = acpi_processor_read_throttling;
+		entry->write_proc = acpi_processor_write_throttling;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'thermal_limit' [R/W] */
+	entry = create_proc_entry(ACPI_PROCESSOR_FILE_LIMIT,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_PROCESSOR_FILE_LIMIT));
+	else {
+		entry->read_proc = acpi_processor_read_limit;
+		entry->write_proc = acpi_processor_write_limit;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_processor_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_processor_remove_fs");
+
+	if (!acpi_processor_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_processor_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Interface
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_processor_get_info (
+	struct acpi_processor	*pr)
+{
+	acpi_status		status = 0;
+	acpi_object		object = {0};
+	acpi_buffer		buffer = {sizeof(acpi_object), &object};
+	static int		cpu_count = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_get_info");
+
+	if (!pr)
+		return_VALUE(-EINVAL);
+
+#ifdef CONFIG_SMP
+	if (smp_num_cpus > 1)
+		acpi_processor_smp = smp_num_cpus;
+#endif
+
+	acpi_processor_get_errata(pr);
+
+	/*
+	 * Check to see if we have bus mastering arbitration control.  This
+	 * is required for proper C3 usage (to maintain cache coherency).
+	 */
+	if (acpi_fadt.V1_pm2_cnt_blk && acpi_fadt.pm2_cnt_len) {
+		pr->flags.bm_control = 1;
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"Bus mastering arbitration control present\n"));
+	}
+	else
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"No bus mastering arbitration control\n"));
+
+	/*
+	 * Evalute the processor object.  Note that it is common on SMP to
+	 * have the first (boot) processor with a valid PBLK address while
+	 * all others have a NULL address.
+	 */
+	status = acpi_evaluate_object(pr->handle, NULL, NULL, &buffer);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error evaluating processor object\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	/*
+	 * TBD: Synch processor ID (via LAPIC/LSAPIC structures) on SMP.
+	 *	>>> 'acpi_get_processor_id(acpi_id, &id)' in arch/xxx/acpi.c
+	 */
+	pr->id = cpu_count++;
+	pr->acpi_id = object.processor.proc_id;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Processor [%d:%d]\n", pr->id, 
+		pr->acpi_id));
+
+	if (!object.processor.pblk_address)
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No PBLK (NULL address)\n"));
+	else if (object.processor.pblk_length < 6)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid PBLK length [%d]\n",
+			object.processor.pblk_length));
+	else {
+		pr->throttling.address = object.processor.pblk_address;
+		pr->throttling.duty_offset = acpi_fadt.duty_offset;
+		pr->throttling.duty_width = acpi_fadt.duty_width;
+		pr->power.states[ACPI_STATE_C2].address =
+			object.processor.pblk_address + 4;
+		pr->power.states[ACPI_STATE_C3].address =
+			object.processor.pblk_address + 5;
+	}
+
+	acpi_processor_get_power_info(pr);
+	acpi_processor_get_performance_info(pr);
+	acpi_processor_get_throttling_info(pr);
+	acpi_processor_get_limit_info(pr);
+
+	return_VALUE(0);
+}
+
+
+static void
+acpi_processor_notify (
+	acpi_handle		handle,
+	u32			event,
+	void			*data)
+{
+	struct acpi_processor	*pr = (struct acpi_processor *) data;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_notify");
+
+	if (!pr)
+		return_VOID;
+
+	if (0 != acpi_bus_get_device(pr->handle, &device))
+		return_VOID;
+
+	switch (event) {
+	case ACPI_PROCESSOR_NOTIFY_PERFORMANCE:
+	case ACPI_PROCESSOR_NOTIFY_POWER:
+		acpi_bus_generate_event(device, event, 0);
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"Unsupported event [0x%x]\n", event));
+		break;
+	}
+
+	return_VOID;
+}
+
+
+static int
+acpi_processor_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_processor	*pr = NULL;
+	u32			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	pr = kmalloc(sizeof(struct acpi_processor), GFP_KERNEL);
+	if (!pr)
+		return_VALUE(-ENOMEM);
+	memset(pr, 0, sizeof(struct acpi_processor));
+
+	pr->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_PROCESSOR_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_PROCESSOR_CLASS);
+	acpi_driver_data(device) = pr;
+
+	result = acpi_processor_get_info(pr);
+	if (0 != result)
+		goto end;
+
+	result = acpi_processor_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	/*
+	 * TBD: Fix notify handler installation for processors.
+	 *
+	status = acpi_install_notify_handler(pr->handle, ACPI_DEVICE_NOTIFY, 
+		acpi_processor_notify, pr);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"Error installing notify handler\n"));
+		result = -ENODEV;
+		goto end;
+	}
+	*/
+
+	acpi_processor_list[pr->id] = pr;
+
+	/*
+	 * Set Idle Handler
+	 * ----------------
+	 * Install the idle handler if power management (states other than C1)
+	 * is supported.  Note that the default idle handler (default_idle)
+	 * will be used on platforms that only support C1.
+	 */
+	if ((pr->id == 0) && (pr->flags.power)) {
+		pm_idle_save = pm_idle;
+		pm_idle = acpi_processor_idle;
+	}
+	
+	printk(KERN_INFO PREFIX "%s [%s] (supports",
+		acpi_device_name(device), acpi_device_bid(device));
+	for (i=1; i<ACPI_C_STATE_COUNT; i++)
+		if (pr->power.states[i].valid)
+			printk(" C%d", i);
+	if (pr->flags.performance)
+		printk(", %d performance states", pr->performance.state_count);
+	if (pr->flags.throttling)
+		printk(", %d throttling states", pr->throttling.state_count);
+	if (pr->errata.piix4.bmisx)
+		printk(", PIIX4 errata");
+	printk(")\n");
+
+end:
+	if (0 != result) {
+		acpi_processor_remove_fs(device);
+		kfree(pr);
+	}
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_processor_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_processor	*pr = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	pr = (struct acpi_processor *) acpi_driver_data(device);
+
+	/*
+	status = acpi_remove_notify_handler(pr->handle, ACPI_DEVICE_NOTIFY, 
+		acpi_processor_notify);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, 
+			"Error removing notify handler\n"));
+		return_VALUE(-ENODEV);
+	}
+	*/
+
+	/* Unregister the idle handler when processor #0 is removed. */
+	if (pr->id == 0)
+		pm_idle = pm_idle_save;
+
+	acpi_processor_remove_fs(device);
+
+	acpi_processor_list[pr->id] = NULL;
+
+	kfree(pr);
+
+	return_VALUE(0);
+}
+
+
+static int __init
+acpi_processor_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_init");
+
+	memset(&acpi_processor_list, 0, sizeof(acpi_processor_list));
+
+	result = acpi_bus_register_driver(&acpi_processor_driver);
+	if (0 > result)
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+static void __exit
+acpi_processor_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_processor_exit");
+
+	result = acpi_bus_unregister_driver(&acpi_processor_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_PROCESSOR_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
+
+
+module_init(acpi_processor_init);
+module_exit(acpi_processor_exit);
diff -Nru a/drivers/acpi/acpi_system.c b/drivers/acpi/acpi_system.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_system.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1232 @@
+/*
+ *  acpi_system.c - ACPI System Driver ($Revision: 40 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/poll.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <asm/uaccess.h>
+#include <asm/acpi.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+#ifdef CONFIG_X86
+#ifdef CONFIG_ACPI_SLEEP
+#include <linux/mc146818rtc.h>
+#endif
+#endif
+
+
+#define _COMPONENT		ACPI_SYSTEM_COMPONENT
+ACPI_MODULE_NAME		("acpi_system")
+
+#define PREFIX			"ACPI: "
+
+extern FADT_DESCRIPTOR		acpi_fadt;
+
+static int acpi_system_add (struct acpi_device *device);
+static int acpi_system_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_system_driver = {
+	name:			ACPI_SYSTEM_DRIVER_NAME,
+	class:			ACPI_SYSTEM_CLASS,
+	ids:			ACPI_SYSTEM_HID,
+	ops:			{
+					add:	acpi_system_add,
+					remove:	acpi_system_remove
+				},
+};
+
+struct acpi_system
+{
+	acpi_handle		handle;
+	u8			states[ACPI_S_STATE_COUNT];
+};
+
+/* Global vars for handling event proc entry */
+static spinlock_t		acpi_system_event_lock = SPIN_LOCK_UNLOCKED;
+int				event_is_open = 0;
+extern struct list_head		acpi_bus_event_list;
+extern wait_queue_head_t	acpi_bus_event_queue;
+
+/* --------------------------------------------------------------------------
+                                  System Sleep
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_PM
+
+static void
+acpi_power_off (void)
+{
+	acpi_enter_sleep_state_prep(ACPI_STATE_S5);
+	acpi_disable_irqs();
+	acpi_enter_sleep_state(ACPI_STATE_S5);
+	acpi_disable_irqs();
+}
+
+#endif /*CONFIG_PM*/
+
+
+#ifdef CONFIG_ACPI_SLEEP
+
+/**
+ * acpi_system_restore_state - OS-specific restoration of state
+ * @state:	sleep state we're exiting
+ *
+ * Note that if we're coming back from S4, the memory image should have already
+ * been loaded from the disk and is already in place. (Otherwise how else would we
+ * be here?).
+ */
+acpi_status
+acpi_system_restore_state (
+	u32			state)
+{
+	/* restore processor state
+	 * We should only be here if we're coming back from STR or STD.
+	 * And, in the case of the latter, the memory image should have already
+	 * been loaded from disk.
+	 */
+	if (state > ACPI_STATE_S1)
+		acpi_restore_state_mem();
+
+	/* wait for power to come back */
+	mdelay(10);
+#ifdef HAVE_NEW_DEVICE_MODEL
+	/* turn all the devices back on */
+	device_resume(RESUME_POWER_ON);
+
+	/* enable interrupts once again */
+	acpi_enable_irqs();
+
+	/* restore device context */
+	device_resume(RESUME_RESTORE_STATE);
+#endif
+	return AE_OK;
+}
+
+/**
+ * acpi_system_save_state - save OS specific state and power down devices
+ * @state:	sleep state we're entering.
+ *
+ * This handles saving all context to memory, and possibly disk.
+ * First, we call to the device driver layer to save device state.
+ * Once we have that, we save whatevery processor and kernel state we
+ * need to memory.
+ * If we're entering S4, we then write the memory image to disk.
+ *
+ * Only then is it safe for us to power down devices, since we may need
+ * the disks and upstream buses to write to.
+ */
+acpi_status
+acpi_system_save_state(
+	u32			state)
+{
+	int			error = 0;
+
+#ifdef HAVE_NEW_DEVICE_MODEL
+	/* Send notification to devices that they will be suspended.
+	 * If any device or driver cannot make the transition, either up
+	 * or down, we'll get an error back.
+	 */
+	error = device_suspend(state, SUSPEND_NOTIFY);
+	if (error)
+		return AE_ERROR;
+#endif
+	if (state < ACPI_STATE_S5) {
+
+#ifdef HAVE_NEW_DEVICE_MODEL
+		/* Tell devices to stop I/O and actually save their state.
+		 * It is theoretically possible that something could fail,
+		 * so handle that gracefully..
+		 */
+		error = device_suspend(state, SUSPEND_SAVE_STATE);
+		if (error) {
+			/* tell devices to restore state if they have
+			 * it saved and to start taking I/O requests.
+			 */
+			device_resume(RESUME_RESTORE_STATE);
+			return error;
+		}
+#endif
+
+		/* flush caches */
+		wbinvd();
+
+		/* Do arch specific saving of state. */
+		if (state > ACPI_STATE_S1) {
+			error = acpi_save_state_mem();
+
+			if (!error && (state == ACPI_STATE_S4))
+				error = acpi_save_state_disk();
+
+#ifdef HAVE_NEW_DEVICE_MODEL
+			if (error) {
+				device_resume(RESUME_RESTORE_STATE);
+				return error;
+			}
+#endif
+		}
+	}
+#ifdef HAVE_NEW_DEVICE_MODEL
+	/* disable interrupts
+	 * Note that acpi_suspend -- our caller -- will do this once we return.
+	 * But, we want it done early, so we don't get any suprises during
+	 * the device suspend sequence.
+	 */
+	acpi_disable_irqs();
+
+	/* Unconditionally turn off devices.
+	 * Obvious if we enter a sleep state.
+	 * If entering S5 (soft off), this should put devices in a
+	 * quiescent state.
+	 */
+	error = device_suspend(state, SUSPEND_POWER_DOWN);
+
+	/* We're pretty screwed if we got an error from this.
+	 * We try to recover by simply calling our own restore_state
+	 * function; see above for definition.
+	 *
+	 * If it's S5 though, go through with it anyway..
+	 */
+	if (error && state != ACPI_STATE_S5)
+		acpi_system_restore_state(state);
+#endif
+	return error ? AE_ERROR : AE_OK;
+}
+
+
+/****************************************************************************
+ *
+ * FUNCTION:    acpi_system_suspend
+ *
+ * PARAMETERS:  %state: Sleep state to enter.
+ *
+ * RETURN:      acpi_status, whether or not we successfully entered and
+ *              exited sleep.
+ *
+ * DESCRIPTION: Perform OS-specific action to enter sleep state.
+ *              This is the final step in going to sleep, per spec.  If we
+ *              know we're coming back (i.e. not entering S5), we save the
+ *              processor flags. [ We'll have to save and restore them anyway,
+ *              so we use the arch-agnostic save_flags and restore_flags
+ *              here.]  We then set the place to return to in arch-specific
+ *              globals using arch_set_return_point. Finally, we call the
+ *              ACPI function to write the proper values to I/O ports.
+ *
+ ****************************************************************************/
+
+acpi_status
+acpi_system_suspend(
+	u32			state)
+{
+	acpi_status		status = AE_ERROR;
+	unsigned long		flags = 0;
+
+	save_flags(flags);
+	
+	switch (state)
+	{
+	case ACPI_STATE_S1:
+		/* do nothing */
+		break;
+
+	case ACPI_STATE_S2:
+	case ACPI_STATE_S3:
+		acpi_save_register_state((unsigned long)&&acpi_sleep_done);
+		break;
+	}
+
+	barrier();
+	status = acpi_enter_sleep_state(state);
+
+acpi_sleep_done:
+
+	acpi_restore_register_state();
+	restore_flags(flags);
+
+	return status;
+}
+
+
+/**
+ * acpi_suspend - OS-agnostic system suspend/resume support (S? states)
+ * @state:	state we're entering
+ *
+ */
+acpi_status
+acpi_suspend (
+	u32			state)
+{
+	acpi_status status;
+
+	/* get out if state is invalid */
+	if (state < ACPI_STATE_S1 || state > ACPI_STATE_S5)
+		return AE_ERROR;
+
+	/* do we have a wakeup address for S2 and S3? */
+	if (state == ACPI_STATE_S2 || state == ACPI_STATE_S3) {
+		if (!acpi_wakeup_address)
+			return AE_ERROR;
+		acpi_set_firmware_waking_vector((ACPI_PHYSICAL_ADDRESS) acpi_wakeup_address);
+	}
+
+	acpi_enter_sleep_state_prep(state);
+
+	status = acpi_system_save_state(state);
+	if (!ACPI_SUCCESS(status))
+		return status;
+
+	/* disable interrupts and flush caches */
+	acpi_disable_irqs();
+	wbinvd();
+
+	/* perform OS-specific sleep actions */
+	status = acpi_system_suspend(state);
+
+	/* Even if we failed to go to sleep, all of the devices are in an suspended
+	 * mode. So, we run these unconditionaly to make sure we have a usable system
+	 * no matter what.
+	 */
+	acpi_system_restore_state(state);
+	acpi_leave_sleep_state(state);
+
+	/* make sure interrupts are enabled */
+	acpi_enable_irqs();
+
+	/* reset firmware waking vector */
+	acpi_set_firmware_waking_vector((ACPI_PHYSICAL_ADDRESS) 0);
+
+	return status;
+}
+
+#endif /* CONFIG_ACPI_SLEEP */
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+
+static int
+acpi_system_read_info (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_system	*system = (struct acpi_system *) data;
+	char			*p = page;
+	int			size = 0;
+	u32			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_read_info");
+
+	if (!system || (off != 0))
+		goto end;
+
+	p += sprintf(p, "version:                 %x\n", ACPI_CA_VERSION);
+
+	p += sprintf(p, "states:                  ");
+	for (i=0; i<ACPI_S_STATE_COUNT; i++) {
+		if (system->states[i])
+			p += sprintf(p, "S%d ", i);
+	}
+	p += sprintf(p, "\n");
+
+end:
+	size = (p - page);
+	if (size <= off+count) *eof = 1;
+	*start = page + off;
+	size -= off;
+	if (size>count) size = count;
+	if (size<0) size = 0;
+
+	return_VALUE(size);
+}
+
+static int acpi_system_open_event(struct inode *inode, struct file *file);
+static ssize_t acpi_system_read_event (struct file*, char*, size_t, loff_t*);
+static int acpi_system_close_event(struct inode *inode, struct file *file);
+static unsigned int acpi_system_poll_event(struct file *file, poll_table *wait);
+
+
+static struct file_operations acpi_system_event_ops = {
+	open:		acpi_system_open_event,
+	read:		acpi_system_read_event,
+	release:	acpi_system_close_event,
+	poll:		acpi_system_poll_event,
+};
+
+static int
+acpi_system_open_event(struct inode *inode, struct file *file)
+{
+	spin_lock_irq (&acpi_system_event_lock);
+
+	if(event_is_open)
+		goto out_busy;
+
+	event_is_open = 1;
+
+	spin_unlock_irq (&acpi_system_event_lock);
+	return 0;
+
+out_busy:
+	spin_unlock_irq (&acpi_system_event_lock);
+	return -EBUSY;
+}
+
+static ssize_t
+acpi_system_read_event (
+	struct file		*file,
+	char			*buffer,
+	size_t			count,
+	loff_t			*ppos)
+{
+	int			result = 0;
+	char			outbuf[ACPI_MAX_STRING];
+	int			size = 0;
+	struct acpi_bus_event	event;
+
+	ACPI_FUNCTION_TRACE("acpi_system_read_event");
+
+	memset(&event, 0, sizeof(struct acpi_bus_event));
+
+	if (count < ACPI_MAX_STRING)
+		goto end;
+
+	if ((file->f_flags & O_NONBLOCK)
+	    && (list_empty(&acpi_bus_event_list)))
+		return_VALUE(-EAGAIN);
+
+	result = acpi_bus_receive_event(&event);
+	if (0 != result) {
+		size = sprintf(outbuf, "error\n");
+		goto end;
+	}
+
+	size = sprintf(outbuf, "%s %s %08x %08x\n", 
+		event.device_class?event.device_class:"<unknown>",
+		event.bus_id?event.bus_id:"<unknown>", 
+		event.type, 
+		event.data);
+
+end:
+	if (copy_to_user(buffer, outbuf, size))
+		return_VALUE(-EFAULT);
+
+	*ppos += size;
+
+	return_VALUE(size);
+}
+
+static int
+acpi_system_close_event(struct inode *inode, struct file *file)
+{
+	spin_lock_irq (&acpi_system_event_lock);
+	event_is_open = 0;
+	spin_unlock_irq (&acpi_system_event_lock);
+	return 0;
+}
+
+static unsigned int
+acpi_system_poll_event(
+	struct file		*file,
+	poll_table		*wait)
+{
+	poll_wait(file, &acpi_bus_event_queue, wait);
+	if (!list_empty(&acpi_bus_event_list))
+		return POLLIN | POLLRDNORM;
+	return 0;
+}
+
+static ssize_t acpi_system_read_dsdt (struct file*, char*, size_t, loff_t*);
+
+static struct file_operations acpi_system_dsdt_ops = {
+	read:			acpi_system_read_dsdt,
+};
+
+static ssize_t
+acpi_system_read_dsdt (
+	struct file		*file,
+	char			*buffer,
+	size_t			count,
+	loff_t			*ppos)
+{
+	acpi_status		status = AE_OK;
+	acpi_buffer		dsdt = {ACPI_ALLOCATE_BUFFER, NULL};
+	void			*data = 0;
+	size_t			size = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_read_dsdt");
+
+	status = acpi_get_table(ACPI_TABLE_DSDT, 1, &dsdt);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	if (*ppos < dsdt.length) {
+		data = dsdt.pointer + file->f_pos;
+		size = dsdt.length - file->f_pos;
+		if (size > count)
+			size = count;
+		if (copy_to_user(buffer, data, size)) {
+			kfree(dsdt.pointer);
+			return_VALUE(-EFAULT);
+		}
+	}
+
+	kfree(dsdt.pointer);
+
+	*ppos += size;
+
+	return_VALUE(size);
+}
+
+
+static ssize_t acpi_system_read_fadt (struct file*, char*, size_t, loff_t*);
+
+static struct file_operations acpi_system_fadt_ops = {
+	read:			acpi_system_read_fadt,
+};
+
+static ssize_t
+acpi_system_read_fadt (
+	struct file		*file,
+	char			*buffer,
+	size_t			count,
+	loff_t			*ppos)
+{
+	acpi_status		status = AE_OK;
+	acpi_buffer		fadt = {ACPI_ALLOCATE_BUFFER, NULL};
+	void			*data = 0;
+	size_t			size = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_read_fadt");
+
+	status = acpi_get_table(ACPI_TABLE_FADT, 1, &fadt);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	if (*ppos < fadt.length) {
+		data = fadt.pointer + file->f_pos;
+		size = fadt.length - file->f_pos;
+		if (size > count)
+			size = count;
+		if (copy_to_user(buffer, data, size)) {
+			kfree(fadt.pointer);
+			return_VALUE(-EFAULT);
+		}
+	}
+
+	kfree(fadt.pointer);
+
+	*ppos += size;
+
+	return_VALUE(size);
+}
+
+
+#ifdef ACPI_DEBUG
+
+static int
+acpi_system_read_debug (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	char			*p = page;
+	int 			size = 0;
+	u32                     var;
+
+	if (off != 0)
+		goto end;
+
+	switch ((unsigned long) data) {
+	case 0:
+		p += sprintf(p, "0x%08x\n", acpi_dbg_layer);
+		break;
+	case 1:
+		p += sprintf(p, "0x%08x\n", acpi_dbg_level);
+		break;
+	default:
+		p += sprintf(p, "Invalid debug option\n");
+		break;
+	}
+	
+end:
+	size = (p - page);
+	if (size <= off+count) *eof = 1;
+	*start = page + off;
+	size -= off;
+	if (size>count) size = count;
+	if (size<0) size = 0;
+
+	return size;
+}
+
+
+static int
+acpi_system_write_debug (
+	struct file             *file,
+        const char              *buffer,
+	unsigned long           count,
+        void                    *data)
+{
+	char			debug_string[12] = {'\0'};
+	u32                     *pvar;
+
+	ACPI_FUNCTION_TRACE("acpi_system_write_debug");
+
+	if (count > sizeof(debug_string) - 1)
+		return_VALUE(-EINVAL);
+
+	if (copy_from_user(debug_string, buffer, count))
+		return_VALUE(-EFAULT);
+
+	debug_string[count] = '\0';
+
+	switch ((unsigned long) data) {
+	case 0:
+		acpi_dbg_layer = simple_strtoul(debug_string, NULL, 0);
+		break;
+	case 1:
+		acpi_dbg_level = simple_strtoul(debug_string, NULL, 0);
+		break;
+	default:
+		return_VALUE(-EINVAL);
+	}
+
+	return_VALUE(count);
+}
+
+#endif /* ACPI_DEBUG */
+
+
+#ifdef CONFIG_ACPI_SLEEP
+
+static int
+acpi_system_read_sleep (
+        char                    *page,
+        char                    **start,
+        off_t                   off,
+        int                     count,
+        int                     *eof,
+        void                    *data)
+{
+	struct acpi_system	*system = (struct acpi_system *) data;
+	char			*p = page;
+	int			size;
+	int			i;
+
+	ACPI_FUNCTION_TRACE("acpi_system_read_sleep");
+
+	if (!system || (off != 0))
+		goto end;
+
+	for (i = 0; i <= ACPI_STATE_S5; i++) {
+		if (system->states[i])
+			p += sprintf(p,"S%d ", i);
+	}
+
+	p += sprintf(p, "\n");
+
+end:
+	size = (p - page);
+	if (size <= off+count) *eof = 1;
+	*start = page + off;
+	size -= off;
+	if (size>count) size = count;
+	if (size<0) size = 0;
+
+	return_VALUE(size);
+}
+
+
+static int
+acpi_system_write_sleep (
+	struct file		*file,
+	const char		*buffer,
+	unsigned long		count,
+	void			*data)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_system	*system = (struct acpi_system *) data;
+	char			state_string[12] = {'\0'};
+	u32			state = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_write_sleep");
+
+	if (!system || (count > sizeof(state_string) - 1))
+		return_VALUE(-EINVAL);
+
+	if (copy_from_user(state_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	state_string[count] = '\0';
+	
+	state = simple_strtoul(state_string, NULL, 0);
+	
+	if (!system->states[state])
+		return_VALUE(-ENODEV);
+	
+	status = acpi_suspend(state);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+	
+	return_VALUE(count);
+}
+
+
+static int
+acpi_system_read_alarm (
+	char                    *page,
+	char                    **start,
+	off_t                   off,
+	int                     count,
+	int                     *eof,
+	void                    *context)
+{
+	char			*p = page;
+	int			size = 0;
+	u32			sec, min, hr;
+	u32			day, mo, yr;
+
+	ACPI_FUNCTION_TRACE("acpi_system_read_alarm");
+
+	if (off != 0)
+		goto end;
+
+	spin_lock(&rtc_lock);
+
+	sec = CMOS_READ(RTC_SECONDS_ALARM);
+	min = CMOS_READ(RTC_MINUTES_ALARM);
+	hr = CMOS_READ(RTC_HOURS_ALARM);
+
+#if 0	/* If we ever get an FACP with proper values... */
+	if (acpi_gbl_FADT->day_alrm)
+		day = CMOS_READ(acpi_gbl_FADT->day_alrm);
+	else
+		day =  CMOS_READ(RTC_DAY_OF_MONTH);
+	if (acpi_gbl_FADT->mon_alrm)
+		mo = CMOS_READ(acpi_gbl_FADT->mon_alrm);
+	else
+		mo = CMOS_READ(RTC_MONTH);;
+	if (acpi_gbl_FADT->century)
+		yr = CMOS_READ(acpi_gbl_FADT->century) * 100 + CMOS_READ(RTC_YEAR);
+	else
+		yr = CMOS_READ(RTC_YEAR);
+#else
+	day = CMOS_READ(RTC_DAY_OF_MONTH);
+	mo = CMOS_READ(RTC_MONTH);
+	yr = CMOS_READ(RTC_YEAR);
+#endif
+
+	spin_unlock(&rtc_lock);
+
+	BCD_TO_BIN(sec);
+	BCD_TO_BIN(min);
+	BCD_TO_BIN(hr);
+	BCD_TO_BIN(day);
+	BCD_TO_BIN(mo);
+	BCD_TO_BIN(yr);
+
+	p += sprintf(p,"%4.4u-", yr);
+	p += (mo > 12)  ? sprintf(p, "**-")  : sprintf(p, "%2.2u-", mo);
+	p += (day > 31) ? sprintf(p, "** ")  : sprintf(p, "%2.2u ", day);
+	p += (hr > 23)  ? sprintf(p, "**:")  : sprintf(p, "%2.2u:", hr);
+	p += (min > 59) ? sprintf(p, "**:")  : sprintf(p, "%2.2u:", min);
+	p += (sec > 59) ? sprintf(p, "**\n") : sprintf(p, "%2.2u\n", sec);
+
+ end:
+	size = p - page;
+	if (size < count) *eof = 1;
+	else if (size > count) size = count;
+	if (size < 0) size = 0;
+	*start = page;
+
+	return_VALUE(size);
+}
+
+
+static int
+get_date_field (
+	char			**p,
+	u32			*value)
+{
+	char			*next = NULL;
+	char			*string_end = NULL;
+	int			result = -EINVAL;
+
+	/*
+	 * Try to find delimeter, only to insert null.  The end of the
+	 * string won't have one, but is still valid.
+	 */
+	next = strpbrk(*p, "- :");
+	if (next)
+		*next++ = '\0';
+
+	*value = simple_strtoul(*p, &string_end, 10);
+
+	/* Signal success if we got a good digit */
+	if (string_end != *p)
+		result = 0;
+
+	if (next)
+		*p = next;
+
+	return result;
+}
+
+
+static int
+acpi_system_write_alarm (
+	struct file		*file,
+	const char		*buffer,
+	unsigned long		count,
+	void			*data)
+{
+	int			result = 0;
+	char			alarm_string[30] = {'\0'};
+	char			*p = alarm_string;
+	u32			sec, min, hr, day, mo, yr;
+	int			adjust = 0;
+	unsigned char		rtc_control = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_write_alarm");
+
+	if (count > sizeof(alarm_string) - 1)
+		return_VALUE(-EINVAL);
+	
+	if (copy_from_user(alarm_string, buffer, count))
+		return_VALUE(-EFAULT);
+
+	alarm_string[count] = '\0';
+
+	/* check for time adjustment */
+	if (alarm_string[0] == '+') {
+		p++;
+		adjust = 1;
+	}
+
+	if ((result = get_date_field(&p, &yr)))
+		goto end;
+	if ((result = get_date_field(&p, &mo)))
+		goto end;
+	if ((result = get_date_field(&p, &day)))
+		goto end;
+	if ((result = get_date_field(&p, &hr)))
+		goto end;
+	if ((result = get_date_field(&p, &min)))
+		goto end;
+	if ((result = get_date_field(&p, &sec)))
+		goto end;
+
+	if (sec > 59) {
+		min += 1;
+		sec -= 60;
+	}
+	if (min > 59) {
+		hr += 1;
+		min -= 60;
+	}
+	if (hr > 23) {
+		day += 1;
+		hr -= 24;
+	}
+	if (day > 31) {
+		mo += 1;
+		day -= 31;
+	}
+	if (mo > 12) {
+		yr += 1;
+		mo -= 12;
+	}
+
+	spin_lock_irq(&rtc_lock);
+
+	rtc_control = CMOS_READ(RTC_CONTROL);
+	if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+		BIN_TO_BCD(yr);
+		BIN_TO_BCD(mo);
+		BIN_TO_BCD(day);
+		BIN_TO_BCD(hr);
+		BIN_TO_BCD(min);
+		BIN_TO_BCD(sec);
+	}
+
+	if (adjust) {
+		yr  += CMOS_READ(RTC_YEAR);
+		mo  += CMOS_READ(RTC_MONTH);
+		day += CMOS_READ(RTC_DAY_OF_MONTH);
+		hr  += CMOS_READ(RTC_HOURS);
+		min += CMOS_READ(RTC_MINUTES);
+		sec += CMOS_READ(RTC_SECONDS);
+	}
+
+	spin_unlock_irq(&rtc_lock);
+
+	if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+		BCD_TO_BIN(yr);
+		BCD_TO_BIN(mo);
+		BCD_TO_BIN(day);
+		BCD_TO_BIN(hr);
+		BCD_TO_BIN(min);
+		BCD_TO_BIN(sec);
+	}
+
+	if (sec > 59) {
+		min++;
+		sec -= 60;
+	}
+	if (min > 59) {
+		hr++;
+		min -= 60;
+	}
+	if (hr > 23) {
+		day++;
+		hr -= 24;
+	}
+	if (day > 31) {
+		mo++;
+		day -= 31;
+	}
+	if (mo > 12) {
+		yr++;
+		mo -= 12;
+	}
+	if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
+		BIN_TO_BCD(yr);
+		BIN_TO_BCD(mo);
+		BIN_TO_BCD(day);
+		BIN_TO_BCD(hr);
+		BIN_TO_BCD(min);
+		BIN_TO_BCD(sec);
+	}
+
+	spin_lock_irq(&rtc_lock);
+
+	/* write the fields the rtc knows about */
+	CMOS_WRITE(hr, RTC_HOURS_ALARM);
+	CMOS_WRITE(min, RTC_MINUTES_ALARM);
+	CMOS_WRITE(sec, RTC_SECONDS_ALARM);
+
+	/*
+	 * If the system supports an enhanced alarm it will have non-zero
+	 * offsets into the CMOS RAM here -- which for some reason are pointing
+	 * to the RTC area of memory.
+	 */
+#if 0
+	if (acpi_gbl_FADT->day_alrm)
+		CMOS_WRITE(day, acpi_gbl_FADT->day_alrm);
+	if (acpi_gbl_FADT->mon_alrm)
+		CMOS_WRITE(mo, acpi_gbl_FADT->mon_alrm);
+	if (acpi_gbl_FADT->century)
+		CMOS_WRITE(yr/100, acpi_gbl_FADT->century);
+#endif
+	/* enable the rtc alarm interrupt */
+	if (!(rtc_control & RTC_AIE)) {
+		rtc_control |= RTC_AIE;
+		CMOS_WRITE(rtc_control,RTC_CONTROL);
+		CMOS_READ(RTC_INTR_FLAGS);
+	}
+
+	spin_unlock_irq(&rtc_lock);
+
+	acpi_hw_bit_register_write(ACPI_BITREG_RT_CLOCK_ENABLE, 1, ACPI_MTX_LOCK);
+
+	file->f_pos += count;
+
+	result = 0;
+end:
+	return_VALUE(result ? result : count);
+}
+
+#endif /*CONFIG_ACPI_SLEEP*/
+
+
+static int
+acpi_system_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_system_add_fs");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	/* 'info' [R] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_INFO,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_INFO));
+	else {
+		entry->read_proc = acpi_system_read_info;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'dsdt' [R] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_DSDT,
+		S_IRUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_DSDT));
+	else
+		entry->proc_fops = &acpi_system_dsdt_ops;
+
+	/* 'fadt' [R] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_FADT,
+		S_IRUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_FADT));
+	else
+		entry->proc_fops = &acpi_system_fadt_ops;
+
+	/* 'event' [R] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_EVENT,
+		S_IRUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_EVENT));
+	else
+		entry->proc_fops = &acpi_system_event_ops;
+
+#ifdef CONFIG_ACPI_SLEEP
+
+	/* 'sleep' [R/W]*/
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_SLEEP,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_SLEEP));
+	else {
+		entry->read_proc = acpi_system_read_sleep;
+		entry->write_proc = acpi_system_write_sleep;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'alarm' [R/W] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_ALARM,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_ALARM));
+	else {
+		entry->read_proc = acpi_system_read_alarm;
+		entry->write_proc = acpi_system_write_alarm;
+		entry->data = acpi_driver_data(device);
+	}
+
+#endif /*CONFIG_ACPI_SLEEP*/
+
+#ifdef ACPI_DEBUG
+
+	/* 'debug_layer' [R/W] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_DEBUG_LAYER,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_DEBUG_LAYER));
+	else {
+		entry->read_proc  = acpi_system_read_debug;
+		entry->write_proc = acpi_system_write_debug;
+		entry->data = (void *) 0;
+	}
+
+	/* 'debug_level' [R/W] */
+	entry = create_proc_entry(ACPI_SYSTEM_FILE_DEBUG_LEVEL,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_SYSTEM_FILE_DEBUG_LEVEL));
+	else {
+		entry->read_proc  = acpi_system_read_debug;
+		entry->write_proc = acpi_system_write_debug;
+		entry->data = (void *) 1;
+	}
+
+#endif /*ACPI_DEBUG*/
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_system_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_system_remove_fs");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	remove_proc_entry(ACPI_SYSTEM_FILE_INFO, acpi_device_dir(device));
+	remove_proc_entry(ACPI_SYSTEM_FILE_DSDT, acpi_device_dir(device));
+	remove_proc_entry(ACPI_SYSTEM_FILE_EVENT, acpi_device_dir(device));
+#ifdef CONFIG_ACPI_SLEEP
+	remove_proc_entry(ACPI_SYSTEM_FILE_SLEEP, acpi_device_dir(device));
+	remove_proc_entry(ACPI_SYSTEM_FILE_ALARM, acpi_device_dir(device));
+#endif
+#ifdef ACPI_DEBUG
+	remove_proc_entry(ACPI_SYSTEM_FILE_DEBUG_LAYER,
+		acpi_device_dir(device));
+	remove_proc_entry(ACPI_SYSTEM_FILE_DEBUG_LEVEL,
+		acpi_device_dir(device));
+#endif
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Interface
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_system_add (
+	struct acpi_device	*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_system	*system = NULL;
+	u8			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	system = kmalloc(sizeof(struct acpi_system), GFP_KERNEL);
+	if (!system)
+		return_VALUE(-ENOMEM);
+	memset(system, 0, sizeof(struct acpi_system));
+
+	system->handle = device->handle;
+	sprintf(acpi_device_name(device), "%s", ACPI_SYSTEM_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_SYSTEM_CLASS);
+	acpi_driver_data(device) = system;
+
+	result = acpi_system_add_fs(device);
+	if (0 != result)
+		goto end;
+
+	printk(KERN_INFO PREFIX "%s [%s] (supports", 
+		acpi_device_name(device), acpi_device_bid(device));
+	for (i=0; i<ACPI_S_STATE_COUNT; i++) {
+		u8 type_a, type_b;
+		status = acpi_hw_get_sleep_type_data(i, &type_a, &type_b);
+		if (ACPI_SUCCESS(status)) {
+			system->states[i] = 1;
+			printk(" S%d", i);
+		}
+	}
+	printk(")\n");
+
+#ifdef CONFIG_PM
+	/* Install the soft-off (S5) handler. */
+	if (system->states[ACPI_STATE_S5])
+		pm_power_off = acpi_power_off;
+#endif
+
+end:
+	if (0 != result)
+		kfree(system);
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_system_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	struct acpi_system	*system = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_system_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	system = (struct acpi_system *) acpi_driver_data(device);
+
+#ifdef CONFIG_PM
+	/* Remove the soft-off (S5) handler. */
+	if (system->states[ACPI_STATE_S5])
+		pm_power_off = NULL;
+#endif
+
+	acpi_system_remove_fs(device);
+
+	kfree(system);
+
+	return 0;
+}
+
+
+int __init
+acpi_system_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_system_init");
+
+	result = acpi_bus_register_driver(&acpi_system_driver);
+	if (0 > result)
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+void __exit
+acpi_system_exit (void)
+{
+	ACPI_FUNCTION_TRACE("acpi_system_exit");
+	acpi_bus_unregister_driver(&acpi_system_driver);
+	return_VOID;
+}
diff -Nru a/drivers/acpi/acpi_tables.c b/drivers/acpi/acpi_tables.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_tables.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,514 @@
+/*
+ *  acpi_tables.c - ACPI Boot-Time Table Parsing
+ *
+ *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/irq.h>
+#include <linux/acpi.h>
+
+#define PREFIX			"ACPI: "
+
+#define ACPI_MAX_TABLES		ACPI_TABLE_COUNT
+
+static char *acpi_table_signatures[ACPI_TABLE_COUNT] = {
+	[ACPI_TABLE_UNKNOWN]	= "????",
+	[ACPI_APIC]		= "APIC",
+	[ACPI_BOOT]		= "BOOT",
+	[ACPI_DBGP]		= "DBGP",
+	[ACPI_DSDT]		= "DSDT",
+	[ACPI_ECDT]		= "ECDT",
+	[ACPI_ETDT]		= "ETDT",
+	[ACPI_FACP]		= "FACP",
+	[ACPI_FACS]		= "FACS",
+	[ACPI_OEMX]		= "OEM",
+	[ACPI_PSDT]		= "PSDT",
+	[ACPI_SBST]		= "SBST",
+	[ACPI_SLIT]		= "SLIT",
+	[ACPI_SPCR]		= "SPCR",
+	[ACPI_SRAT]		= "SRAT",
+	[ACPI_SSDT]		= "SSDT",
+	[ACPI_SPMI]		= "SPMI"
+};
+
+/* System Description Table (RSDT/XSDT) */
+struct acpi_table_sdt {
+	unsigned long		pa;		/* Physical Address */
+	unsigned long		count;		/* Table count */
+	struct {
+		unsigned long		pa;
+		enum acpi_table_id	id;
+		unsigned long		size;
+	}			entry[ACPI_MAX_TABLES];
+} __attribute__ ((packed));
+
+static struct acpi_table_sdt	sdt;
+
+acpi_madt_entry_handler		madt_handlers[ACPI_MADT_ENTRY_COUNT];
+
+struct acpi_boot_flags	acpi_boot = {1, 0}; /* Enabled by default */
+
+
+void
+acpi_table_print (
+	struct acpi_table_header *header,
+	unsigned long		phys_addr)
+{
+	char			*name = NULL;
+
+	if (!header)
+		return;
+
+	/* Some table signatures aren't good table names */
+
+	if (0 == strncmp((char *) &header->signature,
+		acpi_table_signatures[ACPI_APIC],
+		sizeof(header->signature))) {
+		name = "MADT";
+	}
+	else if (0 == strncmp((char *) &header->signature,
+		acpi_table_signatures[ACPI_FACP],
+		sizeof(header->signature))) {
+		name = "FADT";
+	}
+	else
+		name = header->signature;
+
+	printk(KERN_INFO PREFIX "%.4s (v%3.3d %6.6s %8.8s %5.5d.%5.5d) @ 0x%p\n",
+		name, header->revision, header->oem_id,
+		header->oem_table_id, header->oem_revision >> 16,
+		header->oem_revision & 0xffff, (void *) phys_addr);
+}
+
+
+void
+acpi_table_print_madt_entry (
+	acpi_table_entry_header	*header)
+{
+	if (!header)
+		return;
+
+	switch (header->type) {
+
+	case ACPI_MADT_LAPIC:
+	{
+		struct acpi_table_lapic *p =
+			(struct acpi_table_lapic*) header;
+		printk(KERN_INFO PREFIX "LAPIC (acpi_id[0x%02x] lapic_id[0x%02x] %s)\n",
+			p->acpi_id, p->id, p->flags.enabled?"enabled":"disabled");
+	}
+		break;
+
+	case ACPI_MADT_IOAPIC:
+	{
+		struct acpi_table_ioapic *p =
+			(struct acpi_table_ioapic*) header;
+		printk(KERN_INFO PREFIX "IOAPIC (id[0x%02x] address[0x%08x] global_irq_base[0x%x])\n",
+			p->id, p->address, p->global_irq_base);
+	}
+		break;
+
+	case ACPI_MADT_INT_SRC_OVR:
+	{
+		struct acpi_table_int_src_ovr *p =
+			(struct acpi_table_int_src_ovr*) header;
+		printk(KERN_INFO PREFIX "INT_SRC_OVR (bus[%d] irq[0x%x] global_irq[0x%x] polarity[0x%x] trigger[0x%x])\n",
+			p->bus, p->bus_irq, p->global_irq, p->flags.polarity, p->flags.trigger);
+	}
+		break;
+
+	case ACPI_MADT_NMI_SRC:
+	{
+		struct acpi_table_nmi_src *p =
+			(struct acpi_table_nmi_src*) header;
+		printk(KERN_INFO PREFIX "NMI_SRC (polarity[0x%x] trigger[0x%x] global_irq[0x%x])\n",
+			p->flags.polarity, p->flags.trigger, p->global_irq);
+	}
+		break;
+
+	case ACPI_MADT_LAPIC_NMI:
+	{
+		struct acpi_table_lapic_nmi *p =
+			(struct acpi_table_lapic_nmi*) header;
+		printk(KERN_INFO PREFIX "LAPIC_NMI (acpi_id[0x%02x] polarity[0x%x] trigger[0x%x] lint[0x%x])\n",
+			p->acpi_id, p->flags.polarity, p->flags.trigger, p->lint);
+	}
+		break;
+
+	case ACPI_MADT_LAPIC_ADDR_OVR:
+	{
+		struct acpi_table_lapic_addr_ovr *p =
+			(struct acpi_table_lapic_addr_ovr*) header;
+		printk(KERN_INFO PREFIX "LAPIC_ADDR_OVR (address[0x%016Lx])\n",
+			p->address);
+	}
+		break;
+
+	case ACPI_MADT_IOSAPIC:
+	{
+		struct acpi_table_iosapic *p =
+			(struct acpi_table_iosapic*) header;
+		printk(KERN_INFO PREFIX "IOSAPIC (id[0x%x] global_irq_base[0x%x] address[0x%016Lx])\n",
+			p->id, p->global_irq_base, p->address);
+	}
+		break;
+
+	case ACPI_MADT_LSAPIC:
+	{
+		struct acpi_table_lsapic *p =
+			(struct acpi_table_lsapic*) header;
+		printk(KERN_INFO PREFIX "LSAPIC (acpi_id[0x%02x] lsapic_id[0x%02x] lsapic_eid[0x%02x] %s)\n",
+			p->acpi_id, p->id, p->eid, p->flags.enabled?"enabled":"disabled");
+	}
+		break;
+
+	case ACPI_MADT_PLAT_INT_SRC:
+	{
+		struct acpi_table_plat_int_src *p =
+			(struct acpi_table_plat_int_src*) header;
+		printk(KERN_INFO PREFIX "PLAT_INT_SRC (polarity[0x%x] trigger[0x%x] type[0x%x] id[0x%04x] eid[0x%x] iosapic_vector[0x%x] global_irq[0x%x]\n",
+			p->flags.polarity, p->flags.trigger, p->type, p->id, p->eid, p->iosapic_vector, p->global_irq);
+	}
+		break;
+
+	default:
+		printk(KERN_WARNING PREFIX "Found unsupported MADT entry (type = 0x%x)\n",
+			header->type);
+		break;
+	}
+}
+
+
+static int
+acpi_table_compute_checksum (
+	void			*table_pointer,
+	unsigned long		length)
+{
+	u8			*p = (u8 *) table_pointer;
+	unsigned long		remains = length;
+	unsigned long		sum = 0;
+
+	if (!p || !length)
+		return -EINVAL;
+
+	while (remains--)
+		sum += *p++;
+
+	return (sum & 0xFF);
+}
+
+
+int __init
+acpi_table_parse_madt (
+	enum acpi_table_id	id,
+	acpi_madt_entry_handler	handler)
+{
+	struct acpi_table_madt	*madt = NULL;
+	acpi_table_entry_header	*entry = NULL;
+	unsigned long		count = 0;
+	unsigned long		madt_end = 0;
+	int			i = 0;
+
+	if (!handler)
+		return -EINVAL;
+
+	/* Locate the MADT (if exists). There should only be one. */
+
+	for (i = 0; i < sdt.count; i++) {
+		if (sdt.entry[i].id != ACPI_APIC)
+			continue;
+		madt = (struct acpi_table_madt *)
+			__acpi_map_table(sdt.entry[i].pa, sdt.entry[i].size);
+		if (!madt) {
+			printk(KERN_WARNING PREFIX "Unable to map MADT\n");
+			return -ENODEV;
+		}
+		break;
+	}
+
+	if (!madt) {
+		printk(KERN_WARNING PREFIX "MADT not present\n");
+		return -ENODEV;
+	}
+
+	madt_end = (unsigned long) madt + sdt.entry[i].size;
+
+	/* Parse all entries looking for a match. */
+
+	entry = (acpi_table_entry_header *)
+		((unsigned long) madt + sizeof(struct acpi_table_madt));
+
+	while (((unsigned long) entry) < madt_end) {
+		if (entry->type == id) {
+			count++;
+			handler(entry);
+		}
+		entry = (acpi_table_entry_header *)
+			((unsigned long) entry += entry->length);
+	}
+
+	return count;
+}
+
+
+int __init
+acpi_table_parse (
+	enum acpi_table_id	id,
+	acpi_table_handler	handler)
+{
+	int			count = 0;
+	int			i = 0;
+
+	if (!handler)
+		return -EINVAL;
+
+	for (i = 0; i < sdt.count; i++) {
+		if (sdt.entry[i].id != id)
+			continue;
+		handler(sdt.entry[i].pa, sdt.entry[i].size);
+		count++;
+	}
+
+	return count;
+}
+
+
+static int __init
+acpi_table_get_sdt (
+	struct acpi_table_rsdp	*rsdp)
+{
+	struct acpi_table_header *header = NULL;
+	int			i, id = 0;
+
+	if (!rsdp)
+		return -EINVAL;
+
+	/* First check XSDT (but only on ACPI 2.0-compatible systems) */
+
+	if ((rsdp->revision >= 2) &&
+		(((struct acpi20_table_rsdp*)rsdp)->xsdt_address)) {
+			
+		struct acpi_table_xsdt	*mapped_xsdt = NULL;
+
+		sdt.pa = ((struct acpi20_table_rsdp*)rsdp)->xsdt_address;
+
+		header = (struct acpi_table_header *)
+			__acpi_map_table(sdt.pa, sizeof(struct acpi_table_header));
+
+		if (!header) {
+			printk(KERN_WARNING PREFIX "Unable to map XSDT header\n");
+			return -ENODEV;
+		}
+
+		if (strncmp(header->signature, "XSDT", 4)) {
+			printk(KERN_WARNING PREFIX "XSDT signature incorrect\n");
+			return -ENODEV;
+		}
+
+		sdt.count = (header->length - sizeof(struct acpi_table_header)) >> 3;
+		if (sdt.count > ACPI_MAX_TABLES) {
+			printk(KERN_WARNING PREFIX "Truncated %lu XSDT entries\n",
+				(ACPI_MAX_TABLES - sdt.count));
+			sdt.count = ACPI_MAX_TABLES;
+		}
+
+		mapped_xsdt = (struct acpi_table_xsdt *)
+			__acpi_map_table(sdt.pa, header->length);
+		if (!mapped_xsdt) {
+			printk(KERN_WARNING PREFIX "Unable to map XSDT\n");
+			return -ENODEV;
+		}
+
+		header = &mapped_xsdt->header;
+
+		for (i = 0; i < sdt.count; i++)
+			sdt.entry[i].pa = (unsigned long) mapped_xsdt->entry[i];
+	}
+
+	/* Then check RSDT */
+
+	else if (rsdp->rsdt_address) {
+
+		struct acpi_table_rsdt	*mapped_rsdt = NULL;
+
+		sdt.pa = rsdp->rsdt_address;
+
+		header = (struct acpi_table_header *)
+			__acpi_map_table(sdt.pa, sizeof(struct acpi_table_header));
+		if (!header) {
+			printk(KERN_WARNING PREFIX "Unable to map RSDT header\n");
+			return -ENODEV;
+		}
+
+		if (strncmp(header->signature, "RSDT", 4)) {
+			printk(KERN_WARNING PREFIX "RSDT signature incorrect\n");
+			return -ENODEV;
+		}
+
+		sdt.count = (header->length - sizeof(struct acpi_table_header)) >> 2;
+		if (sdt.count > ACPI_MAX_TABLES) {
+			printk(KERN_WARNING PREFIX "Truncated %lu RSDT entries\n",
+				(ACPI_TABLE_COUNT - sdt.count));
+			sdt.count = ACPI_MAX_TABLES;
+		}
+
+		mapped_rsdt = (struct acpi_table_rsdt *)
+			__acpi_map_table(sdt.pa, header->length);
+		if (!mapped_rsdt) {
+			printk(KERN_WARNING PREFIX "Unable to map RSDT\n");
+			return -ENODEV;
+		}
+
+		header = &mapped_rsdt->header;
+
+		for (i = 0; i < sdt.count; i++)
+			sdt.entry[i].pa = (unsigned long) mapped_rsdt->entry[i];
+	}
+
+	else {
+		printk(KERN_WARNING PREFIX "No System Description Table (RSDT/XSDT) specified in RSDP\n");
+		return -ENODEV;
+	}
+
+	acpi_table_print(header, sdt.pa);
+
+	for (i = 0; i < sdt.count; i++) {
+
+		header = (struct acpi_table_header *)
+			__acpi_map_table(sdt.entry[i].pa,
+				sizeof(struct acpi_table_header));
+		if (!header)
+			continue;
+
+		acpi_table_print(header, sdt.entry[i].pa);
+
+		if (0 != acpi_table_compute_checksum(header, header->length)) {
+			printk(KERN_WARNING "  >>> ERROR: Invalid checksum\n");
+			continue;
+		}
+
+		sdt.entry[i].size = header->length;
+
+		for (id = 0; id < ACPI_TABLE_COUNT; id++) {
+			if (0 == strncmp((char *) &header->signature,
+				acpi_table_signatures[id],
+				sizeof(header->signature))) {
+				sdt.entry[i].id = id;
+			}
+		}
+	}
+
+	return 0;
+}
+
+
+static void __init
+acpi_table_parse_cmdline (
+	char		*cmdline)
+{
+	char		*p = NULL;
+
+	/* NOTE: We're called too early in the boot process to use __setup */
+
+	if (!cmdline || !(p = strstr(cmdline, "acpi_boot=")))
+		return;
+
+	p += 10;
+
+	while (*p && (*p != ' ')) {
+		if (0 == memcmp(p, "madt", 4)) {
+			printk(KERN_INFO PREFIX "MADT processing enabled\n");
+			acpi_boot.madt = 1;
+			p += 4;
+		}
+		else if (0 == memcmp(p, "on", 2)) {
+			printk(KERN_INFO PREFIX "Boot-time table processing enabled\n");
+			acpi_boot.madt = 1;
+			p += 2;
+		}
+		else if (0 == memcmp(p, "off", 2)) {
+			printk(KERN_INFO PREFIX "Boot-time table processing disabled\n");
+			acpi_boot.madt = 0;
+			p += 3;
+		}
+		else
+			p++;
+
+		if (*p == ',')
+			p ++;
+	}
+}
+
+
+int __init
+acpi_table_init (
+	char			*cmdline)
+{
+	struct acpi_table_rsdp	*rsdp = NULL;
+	unsigned long		rsdp_phys = 0;
+	int			result = 0;
+
+	memset(&sdt, 0, sizeof(struct acpi_table_sdt));
+	memset(&madt_handlers, 0, sizeof(madt_handlers));
+
+	acpi_table_parse_cmdline(cmdline);
+
+	/* Locate and map the Root System Description Table (RSDP) */
+
+	if ((0 != acpi_find_rsdp(&rsdp_phys)) || !rsdp_phys) {
+		printk(KERN_ERR PREFIX "Unable to locate RSDP\n");
+		return -ENODEV;
+	}
+
+	rsdp = (struct acpi_table_rsdp *) __va(rsdp_phys);
+	if (!rsdp) {
+		printk(KERN_WARNING PREFIX "Unable to map RSDP\n");
+		return -ENODEV;
+	}
+
+	printk(KERN_INFO PREFIX "RSDP (v%3.3d %6.6s                     ) @ 0x%p\n",
+		rsdp->revision, rsdp->oem_id, (void *) rsdp_phys);
+
+	if (rsdp->revision < 2)
+		result = acpi_table_compute_checksum(rsdp, sizeof(struct acpi_table_rsdp));
+	else
+		result = acpi_table_compute_checksum(rsdp, ((struct acpi20_table_rsdp *)rsdp)->length);
+
+	if (0 != result) {
+		printk(KERN_WARNING "  >>> ERROR: Invalid checksum\n");
+		return -ENODEV;
+	}
+
+	/* Locate and map the System Description table (RSDT/XSDT) */
+
+	if (0 != acpi_table_get_sdt(rsdp))
+		return -ENODEV;
+
+	return 0;
+}
diff -Nru a/drivers/acpi/acpi_thermal.c b/drivers/acpi/acpi_thermal.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_thermal.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1307 @@
+/*
+ *  acpi_thermal.c - ACPI Thermal Zone Driver ($Revision: 33 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This driver fully implements the ACPI thermal policy as described in the
+ *  ACPI 2.0 Specification.
+ *
+ *  TBD: 1. Implement passive cooling hysteresis.
+ *       2. Enhance passive cooling (CPU) states/limit interface to support
+ *          concepts of 'multiple limiters', upper/lower limits, etc.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/kmod.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_THERMAL_COMPONENT
+ACPI_MODULE_NAME		("acpi_thermal")
+
+MODULE_AUTHOR("Paul Diefenbaugh");
+MODULE_DESCRIPTION(ACPI_THERMAL_DRIVER_NAME);
+MODULE_LICENSE("GPL");
+
+static int tzp = 0;
+MODULE_PARM(tzp, "i");
+MODULE_PARM_DESC(tzp, "Thermal zone polling frequency, in 1/10 seconds.\n");
+
+#define PREFIX			"ACPI: "
+
+
+#define ACPI_THERMAL_MAX_ACTIVE	10
+
+#define KELVIN_TO_CELSIUS(t)	((t-2732+5)/10)
+
+static int acpi_thermal_add (struct acpi_device *device);
+static int acpi_thermal_remove (struct acpi_device *device, int type);
+
+static struct acpi_driver acpi_thermal_driver = {
+	name:			ACPI_THERMAL_DRIVER_NAME,
+	class:			ACPI_THERMAL_CLASS,
+	ids:			ACPI_THERMAL_HID,
+	ops:			{
+					add:	acpi_thermal_add,
+					remove:	acpi_thermal_remove,
+				},
+};
+
+struct acpi_thermal_state {
+	u8			critical:1;
+	u8			hot:1;
+	u8			passive:1;
+	u8			active:1;
+	u8			reserved:4;
+	int			passive_index;		/* a.k.a. limit state */
+	int			active_index;
+};
+
+struct acpi_thermal_state_flags {
+	u8			valid:1;
+	u8			enabled:1;
+	u8			reserved:6;
+};
+
+struct acpi_thermal_critical {
+	struct acpi_thermal_state_flags flags;
+	unsigned long		temperature;
+};
+
+struct acpi_thermal_hot {
+	struct acpi_thermal_state_flags flags;
+	unsigned long		temperature;
+};
+
+struct acpi_thermal_passive {
+	struct acpi_thermal_state_flags flags;
+	unsigned long		temperature;
+	unsigned long		tc1;
+	unsigned long		tc2;
+	unsigned long		tsp;
+	struct acpi_handle_list	devices;
+};
+
+struct acpi_thermal_active {
+	struct acpi_thermal_state_flags flags;
+	unsigned long		temperature;
+	struct acpi_handle_list	devices;
+};
+
+struct acpi_thermal_trips {
+	struct acpi_thermal_critical critical;
+	struct acpi_thermal_hot	hot;
+	struct acpi_thermal_passive passive;
+	struct acpi_thermal_active active[ACPI_THERMAL_MAX_ACTIVE];
+};
+
+struct acpi_thermal_flags {
+	u8			cooling_mode:1;		/* _SCP */
+	u8			devices:1;		/* _TZD */
+	u8			reserved:6;
+};
+
+struct acpi_thermal {
+	acpi_handle		handle;
+	acpi_bus_id		name;
+	unsigned long		temperature;
+	unsigned long		last_temperature;
+	unsigned long		polling_frequency;
+	u8			cooling_mode;
+	struct acpi_thermal_flags flags;
+	struct acpi_thermal_state state;
+	struct acpi_thermal_trips trips;
+	struct acpi_handle_list	devices;
+	struct timer_list	timer;
+};
+
+
+/* --------------------------------------------------------------------------
+                             Thermal Zone Management
+   -------------------------------------------------------------------------- */
+
+static int
+acpi_thermal_get_temperature (
+	struct acpi_thermal *tz)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_get_temperature");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	tz->last_temperature = tz->temperature;
+
+	status = acpi_evaluate_integer(tz->handle, "_TMP", NULL, &tz->temperature);
+	if (ACPI_FAILURE(status))
+		return -ENODEV;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Temperature is %lu dK\n", tz->temperature));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_get_polling_frequency (
+	struct acpi_thermal	*tz)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_get_polling_frequency");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	status = acpi_evaluate_integer(tz->handle, "_TZP", NULL, &tz->polling_frequency);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Polling frequency is %lu dS\n", tz->polling_frequency));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_set_polling (
+	struct acpi_thermal	*tz,
+	int			seconds)
+{
+	ACPI_FUNCTION_TRACE("acpi_thermal_set_polling");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	tz->polling_frequency = seconds * 10;	/* Convert value to deci-seconds */
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Polling frequency set to %lu seconds\n", tz->polling_frequency));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_set_cooling_mode (
+	struct acpi_thermal	*tz,
+	int			mode)
+{
+	acpi_status		status = AE_OK;
+	acpi_object		arg0 = {ACPI_TYPE_INTEGER};
+	acpi_object_list	arg_list= {1, &arg0};
+	acpi_handle		handle = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_set_cooling_mode");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	status = acpi_get_handle(tz->handle, "_SCP", &handle);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "_SCP not present\n"));
+		return_VALUE(-ENODEV);
+	}
+
+	arg0.integer.value = mode;
+
+	status = acpi_evaluate(handle, NULL, &arg_list, NULL);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	tz->cooling_mode = mode;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Cooling mode [%s]\n", 
+		mode?"passive":"active"));
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_get_trip_points (
+	struct acpi_thermal *tz)
+{
+	acpi_status		status = AE_OK;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_get_trip_points");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	/* Critical Shutdown (required) */
+
+	status = acpi_evaluate_integer(tz->handle, "_CRT", NULL, 
+		&tz->trips.critical.temperature);
+	if (ACPI_FAILURE(status)) {
+		tz->trips.critical.flags.valid = 0;
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "No critical threshold\n"));
+		return -ENODEV;
+	}
+	else {
+		tz->trips.critical.flags.valid = 1;
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found critical threshold [%lu]\n", tz->trips.critical.temperature));
+	}
+
+	/* Critical Sleep (optional) */
+
+	status = acpi_evaluate_integer(tz->handle, "_HOT", NULL, &tz->trips.hot.temperature);
+	if (ACPI_FAILURE(status)) {
+		tz->trips.hot.flags.valid = 0;
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No hot threshold\n"));
+	}
+	else {
+		tz->trips.hot.flags.valid = 1;
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found hot threshold [%lu]\n", tz->trips.hot.temperature));
+	}
+
+	/* Passive: Processors (optional) */
+
+	status = acpi_evaluate_integer(tz->handle, "_PSV", NULL, &tz->trips.passive.temperature);
+	if (ACPI_FAILURE(status)) {
+		tz->trips.passive.flags.valid = 0;
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No passive threshold\n"));
+	}
+	else {
+		tz->trips.passive.flags.valid = 1;
+
+		status = acpi_evaluate_integer(tz->handle, "_TC1", NULL, &tz->trips.passive.tc1);
+		if (ACPI_FAILURE(status))
+			tz->trips.passive.flags.valid = 0;
+
+		status = acpi_evaluate_integer(tz->handle, "_TC2", NULL, &tz->trips.passive.tc2);
+		if (ACPI_FAILURE(status))
+			tz->trips.passive.flags.valid = 0;
+
+		status = acpi_evaluate_integer(tz->handle, "_TSP", NULL, &tz->trips.passive.tsp);
+		if (ACPI_FAILURE(status))
+			tz->trips.passive.flags.valid = 0;
+
+		status = acpi_evaluate_reference(tz->handle, "_PSL", NULL, &tz->trips.passive.devices);
+		if (ACPI_FAILURE(status))
+			tz->trips.passive.flags.valid = 0;
+
+		if (!tz->trips.passive.flags.valid)
+			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid passive threshold\n"));
+		else
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found passive threshold [%lu]\n", tz->trips.passive.temperature));
+	}
+
+	/* Active: Fans, etc. (optional) */
+
+	for (i=0; i<ACPI_THERMAL_MAX_ACTIVE; i++) {
+
+		char name[5] = {'_','A','C',('0'+i),'\0'};
+
+		status = acpi_evaluate_integer(tz->handle, name, NULL, &tz->trips.active[i].temperature);
+		if (ACPI_FAILURE(status))
+			break;
+
+		name[2] = 'L';
+		status = acpi_evaluate_reference(tz->handle, name, NULL, &tz->trips.active[i].devices);
+		if (ACPI_SUCCESS(status)) {
+			tz->trips.active[i].flags.valid = 1;
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found active threshold [%d]:[%lu]\n", i, tz->trips.active[i].temperature));
+		}
+		else
+			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid active threshold [%d]\n", i));
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_get_devices (
+	struct acpi_thermal	*tz)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_get_devices");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	status = acpi_evaluate_reference(tz->handle, "_TZD", NULL, &tz->devices);
+	if (ACPI_FAILURE(status))
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_call_usermode (
+	char			*path)
+{
+	char			*argv[2] = {NULL, NULL};
+	char			*envp[3] = {NULL, NULL, NULL};
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_call_usermode");
+
+	if (!path)
+		return_VALUE(-EINVAL);;
+
+	argv[0] = path;
+
+	/* minimal command environment */
+	envp[0] = "HOME=/";
+	envp[1] = "PATH=/sbin:/bin:/usr/sbin:/usr/bin";
+	
+	call_usermodehelper(argv[0], argv, envp);
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_critical (
+	struct acpi_thermal	*tz)
+{
+	int			result = 0;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_critical");
+
+	if (!tz || !tz->trips.critical.flags.valid)
+		return_VALUE(-EINVAL);
+
+	if (tz->temperature >= tz->trips.critical.temperature) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Critical trip point\n"));
+		tz->trips.critical.flags.enabled = 1;
+	}
+	else if (tz->trips.critical.flags.enabled)
+		tz->trips.critical.flags.enabled = 0;
+
+	result = acpi_bus_get_device(tz->handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	acpi_bus_generate_event(device, ACPI_THERMAL_NOTIFY_CRITICAL, tz->trips.critical.flags.enabled);
+
+	acpi_thermal_call_usermode(ACPI_THERMAL_PATH_POWEROFF);
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_hot (
+	struct acpi_thermal	*tz)
+{
+	int			result = 0;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_hot");
+
+	if (!tz || !tz->trips.hot.flags.valid)
+		return_VALUE(-EINVAL);
+
+	if (tz->temperature >= tz->trips.hot.temperature) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Hot trip point\n"));
+		tz->trips.hot.flags.enabled = 1;
+	}
+	else if (tz->trips.hot.flags.enabled)
+		tz->trips.hot.flags.enabled = 0;
+
+	result = acpi_bus_get_device(tz->handle, &device);
+	if (0 != result)
+		return_VALUE(result);
+
+	acpi_bus_generate_event(device, ACPI_THERMAL_NOTIFY_HOT, tz->trips.hot.flags.enabled);
+
+	/* TBD: Call user-mode "sleep(S4)" function */
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_passive (
+	struct acpi_thermal	*tz)
+{
+	int			result = 0;
+	struct acpi_thermal_passive *passive = NULL;
+	int			trend = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_passive");
+
+	if (!tz || !tz->trips.passive.flags.valid)
+		return_VALUE(-EINVAL);
+
+	passive = &(tz->trips.passive);
+
+	/*
+	 * Above Trip?
+	 * -----------
+	 * Calculate the thermal trend (using the passive cooling equation)
+	 * and modify the performance limit for all passive cooling devices
+	 * accordingly.  Note that we assume symmetry.
+	 */
+	if (tz->temperature >= passive->temperature) {
+		trend = (passive->tc1 * (tz->temperature - tz->last_temperature)) + (passive->tc2 * (tz->temperature - passive->temperature));
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "trend[%d]=(tc1[%lu]*(tmp[%lu]-last[%lu]))+(tc2[%lu]*(tmp[%lu]-psv[%lu]))\n", trend, passive->tc1, tz->temperature, tz->last_temperature, passive->tc2, tz->temperature, passive->temperature));
+		/* Heating up? */
+		if (trend > 0)
+			for (i=0; i<passive->devices.count; i++)
+				acpi_processor_set_limit(passive->devices.handles[i], ACPI_PROCESSOR_LIMIT_INCREMENT, &tz->state.passive_index);
+		/* Cooling off? */
+		else if (trend < 0)
+			for (i=0; i<passive->devices.count; i++)
+				acpi_processor_set_limit(passive->devices.handles[i], ACPI_PROCESSOR_LIMIT_DECREMENT, &tz->state.passive_index);
+	}
+
+	/*
+	 * Below Trip?
+	 * -----------
+	 * Implement passive cooling hysteresis to slowly increase performance
+	 * and avoid thrashing around the passive trip point.  Note that we
+	 * assume symmetry.
+	 */
+	else if (tz->trips.passive.flags.enabled) {
+		for (i=0; i<passive->devices.count; i++)
+			acpi_processor_set_limit(passive->devices.handles[i], ACPI_PROCESSOR_LIMIT_DECREMENT, &tz->state.passive_index);
+		if (0 == tz->state.passive_index) {
+			tz->trips.passive.flags.enabled = 0;
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Disabling passive cooling (zone is cool)\n"));
+		}
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_active (
+	struct acpi_thermal	*tz)
+{
+	int			result = 0;
+	struct acpi_thermal_active *active = NULL;
+	int                     i = 0;
+	int			j = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_active");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	for (i=0; i<ACPI_THERMAL_MAX_ACTIVE; i++) {
+
+		active = &(tz->trips.active[i]);
+		if (!active || !active->flags.valid)
+			break;
+
+		/*
+		 * Above Threshold?
+		 * ----------------
+		 * If not already enabled, turn ON all cooling devices
+		 * associated with this active threshold.
+		 */
+		if (tz->temperature >= active->temperature) {
+			tz->state.active_index = i;
+			if (!active->flags.enabled) {
+				for (j = 0; j < active->devices.count; j++) {
+					result = acpi_bus_set_power(active->devices.handles[j], ACPI_STATE_D0);
+					if (0 != result) {
+						ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Unable to turn cooling device [%p] 'on'\n", active->devices.handles[j]));
+						continue;
+					}
+					active->flags.enabled = 1;
+					ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Cooling device [%p] now 'on'\n", active->devices.handles[j]));
+				}
+			}
+		}
+		/*
+		 * Below Threshold?
+		 * ----------------
+		 * Turn OFF all cooling devices associated with this
+		 * threshold.
+		 */
+		else if (active->flags.enabled) {
+			for (j = 0; j < active->devices.count; j++) {
+				result = acpi_bus_set_power(active->devices.handles[j], ACPI_STATE_D3);
+				if (0 != result) {
+					ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Unable to turn cooling device [%p] 'off'\n", active->devices.handles[j]));
+					continue;
+				}
+				active->flags.enabled = 0;
+				ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Cooling device [%p] now 'off'\n", active->devices.handles[j]));
+			}
+		}
+	}
+
+	return_VALUE(0);
+}
+
+
+static void acpi_thermal_check (void *context);
+
+static void
+acpi_thermal_run (
+	unsigned long		data)
+{
+	acpi_os_queue_for_execution(OSD_PRIORITY_GPE,  acpi_thermal_check, (void *) data);
+}
+
+
+static void
+acpi_thermal_check (
+	void                    *data)
+{
+	int			result = 0;
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	unsigned long		sleep_time = 0;
+	int			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_check");
+
+	if (!tz) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
+		return_VOID;
+	}
+
+	result = acpi_thermal_get_temperature(tz);
+	if (0 != result)
+		return_VOID;
+	
+	memset(&tz->state, 0, sizeof(tz->state));
+	
+	/*
+	 * Check Trip Points
+	 * -----------------
+	 * Compare the current temperature to the trip point values to see
+	 * if we've entered one of the thermal policy states.  Note that
+	 * this function determines when a state is entered, but the 
+	 * individual policy decides when it is exited (e.g. hysteresis).
+	 */
+	if ((tz->trips.critical.flags.valid) && (tz->temperature >= tz->trips.critical.temperature))
+		tz->trips.critical.flags.enabled = 1;
+	if ((tz->trips.hot.flags.valid) && (tz->temperature >= tz->trips.hot.temperature))
+		tz->trips.hot.flags.enabled = 1;
+	if ((tz->trips.passive.flags.valid) && (tz->temperature >= tz->trips.passive.temperature))
+		tz->trips.passive.flags.enabled = 1;
+	for (i=0; i<ACPI_THERMAL_MAX_ACTIVE; i++)
+		if ((tz->trips.active[i].flags.valid) && (tz->temperature >= tz->trips.active[i].temperature))
+			tz->trips.active[i].flags.enabled = 1;
+
+	/*
+	 * Invoke Policy
+	 * -------------
+	 * Separated from the above check to allow individual policy to 
+	 * determine when to exit a given state.
+	 */
+	if (tz->trips.critical.flags.enabled)
+		acpi_thermal_critical(tz);
+	if (tz->trips.hot.flags.enabled)
+		acpi_thermal_hot(tz);
+	if (tz->trips.passive.flags.enabled)
+		acpi_thermal_passive(tz);
+	if (tz->trips.active[0].flags.enabled)
+		acpi_thermal_active(tz);
+
+	/*
+	 * Calculate State
+	 * ---------------
+	 * Again, separated from the above two to allow independent policy
+	 * decisions.
+	 */
+	if (tz->trips.critical.flags.enabled)
+		tz->state.critical = 1;
+	if (tz->trips.hot.flags.enabled)
+		tz->state.hot = 1;
+	if (tz->trips.passive.flags.enabled)
+		tz->state.passive = 1;
+	for (i=0; i<ACPI_THERMAL_MAX_ACTIVE; i++)
+		if (tz->trips.active[i].flags.enabled)
+			tz->state.active = 1;
+
+	/*
+	 * Calculate Sleep Time
+	 * --------------------
+	 * If we're in the passive state, use _TSP's value.  Otherwise
+	 * use the default polling frequency (e.g. _TZP).  If no polling
+	 * frequency is specified then we'll wait forever (at least until
+	 * a thermal event occurs).  Note that _TSP and _TZD values are
+	 * given in 1/10th seconds (we must covert to milliseconds).
+	 */
+	if (tz->state.passive)
+		sleep_time = tz->trips.passive.tsp * 100;
+	else if (tz->polling_frequency > 0)
+		sleep_time = tz->polling_frequency * 100;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "%s: temperature[%lu] sleep[%lu]\n", 
+		tz->name, tz->temperature, sleep_time));
+
+	/*
+	 * Schedule Next Poll
+	 * ------------------
+	 */
+	if (!sleep_time) {
+		if (timer_pending(&(tz->timer)))
+			del_timer(&(tz->timer));
+	}
+	else {
+		if (timer_pending(&(tz->timer)))
+			mod_timer(&(tz->timer), (HZ * sleep_time) / 1000);
+		else {
+			tz->timer.data = (u32) tz;
+			tz->timer.function = acpi_thermal_run;
+			tz->timer.expires = jiffies + (HZ * sleep_time) / 1000;
+			add_timer(&(tz->timer));
+		}
+	}
+
+	return_VOID;
+}
+
+
+/* --------------------------------------------------------------------------
+                              FS Interface (/proc)
+   -------------------------------------------------------------------------- */
+
+#include <linux/compatmac.h>
+#include <linux/proc_fs.h>
+
+struct proc_dir_entry		*acpi_thermal_dir = NULL;
+
+
+static int
+acpi_thermal_read_state (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_read_state");
+
+	if (!tz || (off != 0))
+		goto end;
+
+	p += sprintf(p, "state:                   ");
+
+	if (!tz->state.critical && !tz->state.hot && !tz->state.passive && !tz->state.active)
+		p += sprintf(p, "ok\n");
+	else {
+		if (tz->state.critical)
+			p += sprintf(p, "critical ");
+		if (tz->state.hot)
+			p += sprintf(p, "hot ");
+		if (tz->state.passive)
+			p += sprintf(p, "passive[%d] ", tz->state.passive_index);
+		if (tz->state.active)
+			p += sprintf(p, "active[%d]", tz->state.active_index);
+		p += sprintf(p, "\n");
+	}
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_thermal_read_temperature (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_read_temperature");
+
+	if (!tz || (off != 0))
+		goto end;
+
+	result = acpi_thermal_get_temperature(tz);
+	if (0 != result)
+		goto end;
+
+	p += sprintf(p, "temperature:             %lu C\n", 
+		KELVIN_TO_CELSIUS(tz->temperature));
+	
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_thermal_read_trip_points (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			*p = page;
+	int			len = 0;
+	int			i = 0;
+	int			j = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_read_trip_points");
+
+	if (!tz || (off != 0))
+		goto end;
+
+	if (tz->trips.critical.flags.valid)
+		p += sprintf(p, "critical (S5):           %lu C\n",
+			KELVIN_TO_CELSIUS(tz->trips.critical.temperature));
+
+	if (tz->trips.hot.flags.valid)
+		p += sprintf(p, "hot (S4):                %lu C\n",
+			KELVIN_TO_CELSIUS(tz->trips.hot.temperature));
+
+	if (tz->trips.passive.flags.valid) {
+		p += sprintf(p, "passive:                 %lu C: tc1=%lu tc2=%lu tsp=%lu devices=",
+			KELVIN_TO_CELSIUS(tz->trips.passive.temperature),
+			tz->trips.passive.tc1,
+			tz->trips.passive.tc2, 
+			tz->trips.passive.tsp);
+		for (j=0; j<tz->trips.passive.devices.count; j++) 
+			p += sprintf(p, "0x%p ", 
+				tz->trips.passive.devices.handles[j]);
+		p += sprintf(p, "\n");
+	}
+
+	for (i=0; i<ACPI_THERMAL_MAX_ACTIVE; i++) {
+		if (!(tz->trips.active[i].flags.valid))
+			break;
+		p += sprintf(p, "active[%d]:               %lu C: devices=",
+			i, KELVIN_TO_CELSIUS(tz->trips.active[i].temperature));
+		for (j=0; j<tz->trips.active[i].devices.count; j++) 
+			p += sprintf(p, "0x%p ",
+				tz->trips.active[i].devices.handles[j]);
+		p += sprintf(p, "\n");
+	}
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_thermal_read_cooling_mode (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_read_cooling_mode");
+
+	if (!tz || (off != 0))
+		goto end;
+
+	if (!tz->flags.cooling_mode) {
+		p += sprintf(p, "<not supported>\n");
+		goto end;
+	}
+
+	p += sprintf(p, "cooling mode:            %s\n",
+		tz->cooling_mode?"passive":"active");
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_thermal_write_cooling_mode (
+	struct file		*file,
+	const char		*buffer,
+	unsigned long		count,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			mode_string[12] = {'\0'};
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_write_cooling_mode");
+
+	if (!tz || (count > sizeof(mode_string) - 1))
+		return_VALUE(-EINVAL);
+
+	if (!tz->flags.cooling_mode)
+		return_VALUE(-ENODEV);
+
+	if (copy_from_user(mode_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	mode_string[count] = '\0';
+	
+	result = acpi_thermal_set_cooling_mode(tz, 
+		simple_strtoul(mode_string, NULL, 0));
+	if (0 != result)
+		return_VALUE(result);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_thermal_read_polling (
+	char			*page,
+	char			**start,
+	off_t			off,
+	int 			count,
+	int 			*eof,
+	void			*data)
+{
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			*p = page;
+	int			len = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_read_polling");
+
+	if (!tz || (off != 0))
+		goto end;
+
+	if (!tz->polling_frequency) {
+		p += sprintf(p, "<polling disabled>\n");
+		goto end;
+	}
+
+	p += sprintf(p, "polling frequency:       %lu seconds\n",
+		(tz->polling_frequency / 10));
+
+end:
+	len = (p - page);
+	if (len <= off+count) *eof = 1;
+	*start = page + off;
+	len -= off;
+	if (len>count) len = count;
+	if (len<0) len = 0;
+
+	return_VALUE(len);
+}
+
+
+static int
+acpi_thermal_write_polling (
+	struct file		*file,
+	const char		*buffer,
+	unsigned long		count,
+	void			*data)
+{
+	int			result = 0;
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	char			polling_string[12] = {'\0'};
+	int			seconds = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_write_polling");
+
+	if (!tz || (count > sizeof(polling_string) - 1))
+		return_VALUE(-EINVAL);
+	
+	if (copy_from_user(polling_string, buffer, count))
+		return_VALUE(-EFAULT);
+	
+	polling_string[count] = '\0';
+
+	seconds = simple_strtoul(polling_string, NULL, 0);
+	
+	result = acpi_thermal_set_polling(tz, seconds);
+	if (0 != result)
+		return_VALUE(result);
+
+	acpi_thermal_check(tz);
+
+	return_VALUE(count);
+}
+
+
+static int
+acpi_thermal_add_fs (
+	struct acpi_device	*device)
+{
+	struct proc_dir_entry	*entry = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_add_fs");
+
+	if (!acpi_thermal_dir) {
+		acpi_thermal_dir = proc_mkdir(ACPI_THERMAL_CLASS, 
+			acpi_root_dir);
+		if (!acpi_thermal_dir)
+			return_VALUE(-ENODEV);
+	}
+
+	if (!acpi_device_dir(device)) {
+		acpi_device_dir(device) = proc_mkdir(acpi_device_bid(device),
+			acpi_thermal_dir);
+		if (!acpi_device_dir(device))
+			return_VALUE(-ENODEV);
+	}
+
+	/* 'state' [R] */
+	entry = create_proc_entry(ACPI_THERMAL_FILE_STATE,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_THERMAL_FILE_STATE));
+	else {
+		entry->read_proc = acpi_thermal_read_state;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'temperature' [R] */
+	entry = create_proc_entry(ACPI_THERMAL_FILE_TEMPERATURE,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_THERMAL_FILE_TEMPERATURE));
+	else {
+		entry->read_proc = acpi_thermal_read_temperature;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'trip_points' [R] */
+	entry = create_proc_entry(ACPI_THERMAL_FILE_TRIP_POINTS,
+		S_IRUGO, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_THERMAL_FILE_POLLING_FREQ));
+	else {
+		entry->read_proc = acpi_thermal_read_trip_points;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'cooling_mode' [R/W] */
+	entry = create_proc_entry(ACPI_THERMAL_FILE_COOLING_MODE,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_THERMAL_FILE_COOLING_MODE));
+	else {
+		entry->read_proc = acpi_thermal_read_cooling_mode;
+		entry->write_proc = acpi_thermal_write_cooling_mode;
+		entry->data = acpi_driver_data(device);
+	}
+
+	/* 'polling_frequency' [R/W] */
+	entry = create_proc_entry(ACPI_THERMAL_FILE_POLLING_FREQ,
+		S_IFREG|S_IRUGO|S_IWUSR, acpi_device_dir(device));
+	if (!entry)
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Unable to create '%s' fs entry\n",
+			ACPI_THERMAL_FILE_POLLING_FREQ));
+	else {
+		entry->read_proc = acpi_thermal_read_polling;
+		entry->write_proc = acpi_thermal_write_polling;
+		entry->data = acpi_driver_data(device);
+	}
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_remove_fs (
+	struct acpi_device	*device)
+{
+	ACPI_FUNCTION_TRACE("acpi_thermal_remove_fs");
+
+	if (!acpi_thermal_dir)
+		return_VALUE(-ENODEV);
+
+	if (acpi_device_dir(device))
+		remove_proc_entry(acpi_device_bid(device), acpi_thermal_dir);
+
+	return_VALUE(0);
+}
+
+
+/* --------------------------------------------------------------------------
+                                 Driver Interface
+   -------------------------------------------------------------------------- */
+
+static void
+acpi_thermal_notify (
+	acpi_handle 		handle,
+	u32 			event,
+	void 			*data)
+{
+	struct acpi_thermal	*tz = (struct acpi_thermal *) data;
+	struct acpi_device	*device = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_notify");
+
+	if (!tz)
+		return_VOID;
+
+	if (0 != acpi_bus_get_device(tz->handle, &device))
+		return_VOID;
+
+	switch (event) {
+	case ACPI_THERMAL_NOTIFY_TEMPERATURE:
+		acpi_thermal_check(tz);
+		break;
+	case ACPI_THERMAL_NOTIFY_THRESHOLDS:
+		acpi_thermal_get_trip_points(tz);
+		acpi_thermal_check(tz);
+		acpi_bus_generate_event(device, event, 0);
+		break;
+	case ACPI_THERMAL_NOTIFY_DEVICES:
+		if (tz->flags.devices)
+			acpi_thermal_get_devices(tz);
+		acpi_bus_generate_event(device, event, 0);
+		break;
+	default:
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO,
+			"Unsupported event [0x%x]\n", event));
+		break;
+	}
+
+	return_VOID;
+}
+
+
+static int
+acpi_thermal_get_info (
+	struct acpi_thermal	*tz)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_get_info");
+
+	if (!tz)
+		return_VALUE(-EINVAL);
+
+	/* Get temperature [_TMP] (required) */
+	result = acpi_thermal_get_temperature(tz);
+	if (0 != result)
+		return_VALUE(result);
+
+	/* Set the cooling mode [_SCP] to active cooling (default) */
+	result = acpi_thermal_set_cooling_mode(tz, ACPI_THERMAL_MODE_ACTIVE);
+	if (0 == result)
+		tz->flags.cooling_mode = 1;
+
+	/* Get trip points [_CRT, _PSV, etc.] (required) */
+	result = acpi_thermal_get_trip_points(tz);
+	if (0 != result)
+		return_VALUE(result);
+
+	/* Get default polling frequency [_TZP] (optional) */
+	if (tzp)
+		tz->polling_frequency = tzp;
+	else
+		acpi_thermal_get_polling_frequency(tz);
+
+	/* Get devices in this thermal zone [_TZD] (optional) */
+	result = acpi_thermal_get_devices(tz);
+	if (0 == result)
+		tz->flags.devices = 1;
+
+	return_VALUE(0);
+}
+
+
+static int
+acpi_thermal_add (
+	struct acpi_device 		*device)
+{
+	int			result = 0;
+	acpi_status		status = AE_OK;
+	struct acpi_thermal	*tz = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_add");
+
+	if (!device)
+		return_VALUE(-EINVAL);
+
+	tz = kmalloc(sizeof(struct acpi_thermal), GFP_KERNEL);
+	if (!tz)
+		return_VALUE(-ENOMEM);
+	memset(tz, 0, sizeof(struct acpi_thermal));
+
+	tz->handle = device->handle;
+	sprintf(tz->name, "%s", device->pnp.bus_id);
+	sprintf(acpi_device_name(device), "%s", ACPI_THERMAL_DEVICE_NAME);
+	sprintf(acpi_device_class(device), "%s", ACPI_THERMAL_CLASS);
+	acpi_driver_data(device) = tz;
+
+	result = acpi_thermal_get_info(tz);
+	if (0 != result)
+		goto end;
+
+	result = acpi_thermal_add_fs(device);
+	if (0 != result)
+		return_VALUE(result);
+
+	acpi_thermal_check(tz);
+
+	status = acpi_install_notify_handler(tz->handle,
+		ACPI_DEVICE_NOTIFY, acpi_thermal_notify, tz);
+	if (ACPI_FAILURE(status)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error installing notify handler\n"));
+		result = -ENODEV;
+		goto end;
+	}
+
+	init_timer(&tz->timer);
+
+	printk(KERN_INFO PREFIX "%s [%s] (%lu C)\n",
+		acpi_device_name(device), acpi_device_bid(device),
+		KELVIN_TO_CELSIUS(tz->temperature));
+
+end:
+	if (result) {
+		acpi_thermal_remove_fs(device);
+		kfree(tz);
+	}
+
+	return_VALUE(result);
+}
+
+
+static int
+acpi_thermal_remove (
+	struct acpi_device	*device,
+	int			type)
+{
+	acpi_status		status = AE_OK;
+	struct acpi_thermal	*tz = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_remove");
+
+	if (!device || !acpi_driver_data(device))
+		return_VALUE(-EINVAL);
+
+	tz = (struct acpi_thermal *) acpi_driver_data(device);
+
+	if (timer_pending(&(tz->timer)))
+		del_timer(&(tz->timer));
+
+	status = acpi_remove_notify_handler(tz->handle,
+		ACPI_DEVICE_NOTIFY, acpi_thermal_notify);
+	if (ACPI_FAILURE(status))
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR,
+			"Error removing notify handler\n"));
+
+	/* Terminate policy */
+	if (tz->trips.passive.flags.valid
+		&& tz->trips.passive.flags.enabled) {
+		tz->trips.passive.flags.enabled = 0;
+		acpi_thermal_passive(tz);
+	}
+	if (tz->trips.active[0].flags.valid
+		&& tz->trips.active[0].flags.enabled) {
+		tz->trips.active[0].flags.enabled = 0;
+		acpi_thermal_active(tz);
+	}
+
+	acpi_thermal_remove_fs(device);
+
+	return_VALUE(0);
+}
+
+
+static int __init
+acpi_thermal_init (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_init");
+
+	result = acpi_bus_register_driver(&acpi_thermal_driver);
+	if (0 > result)
+		return_VALUE(-ENODEV);
+
+	return_VALUE(0);
+}
+
+
+static void __exit
+acpi_thermal_exit (void)
+{
+	int			result = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_thermal_exit");
+
+	result = acpi_bus_unregister_driver(&acpi_thermal_driver);
+	if (0 == result)
+		remove_proc_entry(ACPI_THERMAL_CLASS, acpi_root_dir);
+
+	return_VOID;
+}
+
+
+module_init(acpi_thermal_init);
+module_exit(acpi_thermal_exit);
diff -Nru a/drivers/acpi/acpi_utils.c b/drivers/acpi/acpi_utils.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/acpi/acpi_utils.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,460 @@
+/*
+ *  acpi_utils.c - ACPI Utility Functions ($Revision: 5 $)
+ *
+ *  Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
+ *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/types.h>
+#include "acpi_bus.h"
+#include "acpi_drivers.h"
+
+
+#define _COMPONENT		ACPI_BUS_COMPONENT
+ACPI_MODULE_NAME		("acpi_utils")
+
+
+/* --------------------------------------------------------------------------
+                            Object Evaluation Helpers
+   -------------------------------------------------------------------------- */
+
+#ifdef ACPI_DEBUG
+#define acpi_util_eval_error(h,p,s) {\
+	char prefix[80] = {'\0'};\
+	acpi_buffer buffer = {sizeof(prefix), prefix};\
+	acpi_get_name(h, ACPI_FULL_PATHNAME, &buffer);\
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluate [%s.%s]: %s\n",\
+		(char *) prefix, p, acpi_format_exception(s))); }
+#else
+#define acpi_util_eval_error(h,p,s)
+#endif
+
+
+acpi_status
+acpi_extract_package (
+	acpi_object		*package,
+	acpi_buffer		*format,
+	acpi_buffer		*buffer)
+{
+	u32			size_required = 0;
+	u32			tail_offset = 0;
+	char			*format_string = NULL;
+	u32			format_count = 0;
+	u32			i = 0;
+	u8			*head = NULL;
+	u8			*tail = NULL;
+
+	ACPI_FUNCTION_TRACE("acpi_extract_package");
+
+	if (!package || (package->type != ACPI_TYPE_PACKAGE) || (package->package.count < 1)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid 'package' argument\n"));
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+	}
+
+	if (!format || !format->pointer || (format->length < 1)) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid 'format' argument\n"));
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+	}
+
+	if (!buffer) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid 'buffer' argument\n"));
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+	}
+
+	format_count = (format->length/sizeof(char)) - 1;
+	if (format_count > package->package.count) {
+		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Format specifies more objects [%d] than exist in package [%d].", format_count, package->package.count));
+		return_ACPI_STATUS(AE_BAD_DATA);
+	}
+
+	format_string = (char*)format->pointer;
+
+	/*
+	 * Calculate size_required.
+	 */
+	for (i=0; i<format_count; i++) {
+
+		acpi_object *element = &(package->package.elements[i]);
+
+		if (!element) {
+			return_ACPI_STATUS(AE_BAD_DATA);
+		}
+
+		switch (element->type) {
+
+		case ACPI_TYPE_INTEGER:
+			switch (format_string[i]) {
+			case 'N':
+				size_required += sizeof(acpi_integer);
+				tail_offset += sizeof(acpi_integer);
+				break;
+			case 'S':
+				size_required += sizeof(char*) + sizeof(acpi_integer) + sizeof(char);
+				tail_offset += sizeof(char*);
+				break;
+			default:
+				ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid package element [%d]: got number, expecing [%c].\n", i, format_string[i]));
+				return_ACPI_STATUS(AE_BAD_DATA);
+				break;
+			}
+			break;
+
+		case ACPI_TYPE_STRING:
+		case ACPI_TYPE_BUFFER:
+			switch (format_string[i]) {
+			case 'S':
+				size_required += sizeof(char*) + (element->string.length * sizeof(char)) + sizeof(char);
+				tail_offset += sizeof(char*);
+				break;
+			case 'B':
+				size_required += sizeof(u8*) + (element->buffer.length * sizeof(u8));
+				tail_offset += sizeof(u8*);
+				break;
+			default:
+				ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid package element [%d] got string/buffer, expecing [%c].\n", i, format_string[i]));
+				return_ACPI_STATUS(AE_BAD_DATA);
+				break;
+			}
+			break;
+
+		case ACPI_TYPE_PACKAGE:
+		default:
+			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found unsupported element at index=%d\n", i));
+			/* TBD: handle nested packages... */
+			return_ACPI_STATUS(AE_SUPPORT);
+			break;
+		}
+	}
+
+	/*
+	 * Validate output buffer.
+	 */
+	if (buffer->length < size_required) {
+		buffer->length = size_required;
+		return_ACPI_STATUS(AE_BUFFER_OVERFLOW);
+	}
+	else if (buffer->length != size_required || !buffer->pointer) {
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+	}
+
+	head = buffer->pointer;
+	tail = buffer->pointer + tail_offset;
+
+	/*
+	 * Extract package data.
+	 */
+	for (i=0; i<format_count; i++) {
+
+		u8 **pointer = NULL;
+		acpi_object *element = &(package->package.elements[i]);
+
+		if (!element) {
+			return_ACPI_STATUS(AE_BAD_DATA);
+		}
+
+		switch (element->type) {
+
+		case ACPI_TYPE_INTEGER:
+			switch (format_string[i]) {
+			case 'N':
+				*((acpi_integer*)head) = element->integer.value;
+				head += sizeof(acpi_integer);
+				break;
+			case 'S':
+				pointer = (u8**)head;
+				*pointer = tail;
+				*((acpi_integer*)tail) = element->integer.value;
+				head += sizeof(acpi_integer*);
+				tail += sizeof(acpi_integer);
+				/* NULL terminate string */
+				*tail = (char)0;
+				tail += sizeof(char);
+				break;
+			default:
+				/* Should never get here */
+				break;
+			}
+			break;
+
+		case ACPI_TYPE_STRING:
+		case ACPI_TYPE_BUFFER:
+			switch (format_string[i]) {
+			case 'S':
+				pointer = (u8**)head;
+				*pointer = tail;
+				memcpy(tail, element->string.pointer, element->string.length);
+				head += sizeof(char*);
+				tail += element->string.length * sizeof(char);
+				/* NULL terminate string */
+				*tail = (char)0;
+				tail += sizeof(char);
+				break;
+			case 'B':
+				pointer = (u8**)head;
+				*pointer = tail;
+				memcpy(tail, element->buffer.pointer, element->buffer.length);
+				head += sizeof(u8*);
+				tail += element->buffer.length * sizeof(u8);
+				break;
+			default:
+				/* Should never get here */
+				break;
+			}
+			break;
+
+		case ACPI_TYPE_PACKAGE:
+			/* TBD: handle nested packages... */
+		default:
+			/* Should never get here */
+			break;
+		}
+	}
+
+	return_ACPI_STATUS(AE_OK);
+}
+
+
+acpi_status
+acpi_evaluate (
+	acpi_handle		handle,
+	acpi_string		pathname,
+	acpi_object_list	*arguments,
+	acpi_buffer		*buffer)
+{
+	acpi_status		status = AE_OK;
+
+	ACPI_FUNCTION_TRACE("acpi_evaluate");
+
+	/* If caller provided a buffer it must be unallocated/zero'd. */
+	if (buffer && (buffer->length != 0 || buffer->pointer))
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+
+	/*
+	 * Evalute object. The first attempt is just to get the size of the
+	 * object data (that is unless there's no return data); the second
+	 * gets the data.
+	 */
+	status = acpi_evaluate_object(handle, pathname, arguments, buffer);
+
+	if (ACPI_SUCCESS(status)) {
+		return_ACPI_STATUS(status);
+	}
+
+	else if (buffer && (status == AE_BUFFER_OVERFLOW)) {
+
+		/* Gotta allocate - CALLER MUST FREE! */
+		buffer->pointer = kmalloc(buffer->length, GFP_KERNEL);
+		if (!buffer->pointer) {
+			return_ACPI_STATUS(AE_NO_MEMORY);
+		}
+		memset(buffer->pointer, 0, buffer->length);
+
+		/* Re-evaluate - this time it should work. */
+		status = acpi_evaluate_object(handle, pathname, arguments,
+			buffer);
+	}
+
+	if (ACPI_FAILURE(status)) {
+		if (status != AE_NOT_FOUND)
+			acpi_util_eval_error(handle, pathname, status);
+		if (buffer && buffer->pointer) {
+			kfree(buffer->pointer);
+			buffer->length = 0;
+		}
+	}
+
+	return_ACPI_STATUS(status);
+}
+
+
+acpi_status
+acpi_evaluate_integer (
+	acpi_handle		handle,
+	acpi_string		pathname,
+	acpi_object_list	*arguments,
+	unsigned long		*data)
+{
+	acpi_status             status = AE_OK;
+	acpi_object             element;
+	acpi_buffer		buffer = {sizeof(acpi_object), &element};
+
+	ACPI_FUNCTION_TRACE("acpi_evaluate_integer");
+
+	if (!data)
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+
+	status = acpi_evaluate_object(handle, pathname, arguments, &buffer);
+	if (ACPI_FAILURE(status)) {
+		acpi_util_eval_error(handle, pathname, status);
+		return_ACPI_STATUS(status);
+	}
+
+	if (element.type != ACPI_TYPE_INTEGER) {
+		acpi_util_eval_error(handle, pathname, AE_BAD_DATA);
+		return_ACPI_STATUS(AE_BAD_DATA);
+	}
+
+	*data = element.integer.value;
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Return value [%lu]\n", *data));
+
+	return_ACPI_STATUS(AE_OK);
+}
+
+
+#if 0
+acpi_status
+acpi_evaluate_string (
+	acpi_handle		handle,
+	acpi_string		pathname,
+	acpi_object_list	*arguments,
+	acpi_string		*data)
+{
+	acpi_status             status = AE_OK;
+	acpi_object             *element = NULL;
+	acpi_buffer		buffer = {ACPI_ALLOCATE_BUFFER, NULL};
+
+	ACPI_FUNCTION_TRACE("acpi_evaluate_string");
+
+	if (!data)
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+
+	status = acpi_evaluate_object(handle, pathname, arguments, &buffer);
+	if (ACPI_FAILURE(status)) {
+		acpi_util_eval_error(handle, pathname, status);
+		return_ACPI_STATUS(status);
+	}
+
+	element = (acpi_object *) buffer.pointer;
+
+	if ((element->type != ACPI_TYPE_STRING) 
+		|| (element->type != ACPI_TYPE_BUFFER)
+		|| !element->string.length) {
+		acpi_util_eval_error(handle, pathname, AE_BAD_DATA);
+		return_ACPI_STATUS(AE_BAD_DATA);
+	}
+
+	*data = kmalloc(element->string.length + 1, GFP_KERNEL);
+	if (!data) {
+		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Memory allocation error\n"));
+		return_VALUE(-ENOMEM);
+	}
+	memset(*data, 0, element->string.length + 1);
+
+	memcpy(*data, element->string.pointer, element->string.length);
+
+	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Return value [%s]\n", *data));
+
+	return_ACPI_STATUS(AE_OK);
+}
+#endif
+
+
+acpi_status
+acpi_evaluate_reference (
+	acpi_handle		handle,
+	acpi_string		pathname,
+	acpi_object_list	*arguments,
+	struct acpi_handle_list	*list)
+{
+	acpi_status		status = AE_OK;
+	acpi_object		*package = NULL;
+	acpi_object		*element = NULL;
+	acpi_buffer		buffer = {0, NULL};
+	u32			i = 0;
+
+	ACPI_FUNCTION_TRACE("acpi_evaluate_reference");
+
+	if (!list) {
+		return_ACPI_STATUS(AE_BAD_PARAMETER);
+	}
+
+	/* Evaluate object. */
+
+	status = acpi_evaluate(handle, pathname, arguments, &buffer);
+	if (ACPI_FAILURE(status))
+		goto end;
+
+	package = (acpi_object *) buffer.pointer;
+
+	if (!package || (package->type != ACPI_TYPE_PACKAGE)
+		|| (package->package.count == 0)) {
+		status = AE_BAD_DATA;
+		acpi_util_eval_error(handle, pathname, status);
+		goto end;
+	}
+
+	/* Allocate list - CALLER MUST FREE! */
+	list->count = package->package.count;
+	if (list->count > 10) {
+		return AE_NO_MEMORY;
+	}
+	/* TBD: dynamically allocate */
+	/*
+	list->handles = kmalloc(sizeof(acpi_handle)*(list->count), GFP_KERNEL);
+	if (!list->handles) {
+		return_ACPI_STATUS(AE_NO_MEMORY);
+	}
+	memset(list->handles, 0, sizeof(acpi_handle)*(list->count));
+	*/
+
+	/* Parse package data. */
+
+	for (i = 0; i < list->count; i++) {
+
+		element = &(package->package.elements[i]);
+
+		if (!element || (element->type != ACPI_TYPE_STRING)) {
+			status = AE_BAD_DATA;
+			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid element in package (not a device reference)\n"));
+			acpi_util_eval_error(handle, pathname, status);
+			break;
+		}
+
+		/* Convert reference (e.g. "\_PR_.CPU_") to acpi_handle. */
+
+		status = acpi_get_handle(handle, element->string.pointer,
+			&(list->handles[i]));
+		if (ACPI_FAILURE(status)) {
+			status = AE_BAD_DATA;
+			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Unable to resolve device reference [%s]\n", element->string.pointer));
+			acpi_util_eval_error(handle, pathname, status);
+			break;
+		}
+
+		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resolved reference [%s]->[%p]\n", element->string.pointer, list->handles[i]));
+	}
+
+end:
+	if (ACPI_FAILURE(status)) {
+		list->count = 0;
+		//kfree(list->handles);
+	}
+
+	kfree(buffer.pointer);
+
+	return_ACPI_STATUS(status);
+}
+
+
diff -Nru a/drivers/acpi/debugger/Makefile b/drivers/acpi/debugger/Makefile
--- a/drivers/acpi/debugger/Makefile	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/debugger/Makefile	Fri Mar 15 17:51:03 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/debugger/dbcmds.c b/drivers/acpi/debugger/dbcmds.c
--- a/drivers/acpi/debugger/dbcmds.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/debugger/dbcmds.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbcmds - debug commands and output routines
- *              $Revision: 66 $
+ *              $Revision: 79 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -39,7 +39,7 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbcmds")
+	 ACPI_MODULE_NAME    ("dbcmds")
 
 
 /*
@@ -79,6 +79,8 @@
  * DESCRIPTION: Check if this namespace object refers to the target object
  *              that is passed in as the context value.
  *
+ * Note: Currently doesn't check subobjects within the Node's object
+ *
  ******************************************************************************/
 
 acpi_status
@@ -100,17 +102,10 @@
 
 	/* Check for match against the object attached to the node */
 
-	if (node->object == obj_desc) {
+	if (acpi_ns_get_attached_object (node) == obj_desc) {
 		acpi_os_printf ("Reference at Node->Object %p [%4.4s]\n", node, &node->name);
 	}
 
-	/* Check first child for a match */
-	/* TBD: [Investigate] probably now obsolete with new datastructure */
-
-	if (node->child == (void *) obj_desc) {
-		acpi_os_printf ("Reference at Node->Child %p [%4.4s]\n", node, &node->name);
-	}
-
 	return (AE_OK);
 }
 
@@ -136,7 +131,7 @@
 
 	/* Convert string to object pointer */
 
-	obj_desc = (acpi_operand_object *) STRTOUL (object_arg, NULL, 16);
+	obj_desc = ACPI_TO_POINTER (ACPI_STRTOUL (object_arg, NULL, 16));
 
 	/* Search all nodes in namespace */
 
@@ -227,7 +222,7 @@
 	/* Search all tables for the target type */
 
 	for (i = 0; i < NUM_ACPI_TABLES; i++) {
-		if (!STRNCMP (table_arg, acpi_gbl_acpi_table_data[i].signature,
+		if (!ACPI_STRNCMP (table_arg, acpi_gbl_acpi_table_data[i].signature,
 				acpi_gbl_acpi_table_data[i].sig_length)) {
 			/* Found the table, unload it */
 
@@ -279,14 +274,14 @@
 
 	/* Get and verify the breakpoint address */
 
-	address = STRTOUL (location, NULL, 16);
+	address = ACPI_STRTOUL (location, NULL, 16);
 	if (address <= op->aml_offset) {
 		acpi_os_printf ("Breakpoint %X is beyond current address %X\n", address, op->aml_offset);
 	}
 
 	/* Save breakpoint in current walk */
 
-	walk_state->method_breakpoint = address;
+	walk_state->user_breakpoint = address;
 	acpi_os_printf ("Breakpoint set at AML offset %X\n", address);
 }
 
@@ -348,10 +343,9 @@
 	}
 
 	if (statements) {
-		num_statements = STRTOUL (statements, NULL, 0);
+		num_statements = ACPI_STRTOUL (statements, NULL, 0);
 	}
 
-
 	acpi_db_display_op (NULL, op, num_statements);
 }
 
@@ -385,13 +379,13 @@
 		/* Check if numeric argument, must be a Node */
 
 		if ((start_arg[0] >= 0x30) && (start_arg[0] <= 0x39)) {
-			subtree_entry = (acpi_handle) STRTOUL (start_arg, NULL, 16);
+			subtree_entry = ACPI_TO_POINTER (ACPI_STRTOUL (start_arg, NULL, 16));
 			if (!acpi_os_readable (subtree_entry, sizeof (acpi_namespace_node))) {
 				acpi_os_printf ("Address %p is invalid in this address space\n", subtree_entry);
 				return;
 			}
 
-			if (!VALID_DESCRIPTOR_TYPE ((subtree_entry), ACPI_DESC_TYPE_NAMED)) {
+			if (ACPI_GET_DESCRIPTOR_TYPE (subtree_entry) != ACPI_DESC_TYPE_NAMED) {
 				acpi_os_printf ("Address %p is not a valid Named object\n", subtree_entry);
 				return;
 			}
@@ -411,19 +405,18 @@
 		/* Now we can check for the depth argument */
 
 		if (depth_arg) {
-			max_depth = STRTOUL (depth_arg, NULL, 0);
+			max_depth = ACPI_STRTOUL (depth_arg, NULL, 0);
 		}
 	}
 
-
-	acpi_db_set_output_destination (DB_DUPLICATE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_DUPLICATE_OUTPUT);
 	acpi_os_printf ("ACPI Namespace (from %p subtree):\n", subtree_entry);
 
 	/* Display the subtree */
 
-	acpi_db_set_output_destination (DB_REDIRECTABLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_REDIRECTABLE_OUTPUT);
 	acpi_ns_dump_objects (ACPI_TYPE_ANY, ACPI_DISPLAY_SUMMARY, max_depth, ACPI_UINT32_MAX, subtree_entry);
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 }
 
 
@@ -450,24 +443,22 @@
 	u16                     owner_id;
 
 
-	owner_id = (u16) STRTOUL (owner_arg, NULL, 0);
-
+	owner_id = (u16) ACPI_STRTOUL (owner_arg, NULL, 0);
 
 	/* Now we can check for the depth argument */
 
 	if (depth_arg) {
-		max_depth = STRTOUL (depth_arg, NULL, 0);
+		max_depth = ACPI_STRTOUL (depth_arg, NULL, 0);
 	}
 
-
-	acpi_db_set_output_destination (DB_DUPLICATE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_DUPLICATE_OUTPUT);
 	acpi_os_printf ("ACPI Namespace by owner %X:\n", owner_id);
 
 	/* Display the subtree */
 
-	acpi_db_set_output_destination (DB_REDIRECTABLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_REDIRECTABLE_OUTPUT);
 	acpi_ns_dump_objects (ACPI_TYPE_ANY, ACPI_DISPLAY_SUMMARY, max_depth, owner_id, subtree_entry);
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 }
 
 
@@ -549,7 +540,7 @@
 
 	/* Validate Type_arg */
 
-	STRUPR (type_arg);
+	ACPI_STRUPR (type_arg);
 	type = type_arg[0];
 	if ((type != 'L') &&
 		(type != 'A')) {
@@ -559,8 +550,8 @@
 
 	/* Get the index and value */
 
-	index = STRTOUL (index_arg, NULL, 16);
-	value = STRTOUL (value_arg, NULL, 16);
+	index = ACPI_STRTOUL (index_arg, NULL, 16);
+	value = ACPI_STRTOUL (value_arg, NULL, 16);
 
 	walk_state = acpi_ds_get_current_walk_state (acpi_gbl_current_walk_list);
 	if (!walk_state) {
@@ -642,23 +633,22 @@
 {
 	acpi_operand_object     *obj_desc;
 	acpi_status             status;
-	u32                     buf_size;
-	NATIVE_CHAR             buffer[64];
+	acpi_buffer             buffer;
 
 
-	obj_desc = ((acpi_namespace_node *)obj_handle)->object;
-	buf_size = sizeof (buffer) / sizeof (*buffer);
+	obj_desc = acpi_ns_get_attached_object ((acpi_namespace_node *) obj_handle);
 
 	/* Get and display the full pathname to this object */
 
-	status = acpi_ns_handle_to_pathname (obj_handle, &buf_size, buffer);
-
+	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
+	status = acpi_ns_handle_to_pathname (obj_handle, &buffer);
 	if (ACPI_FAILURE (status)) {
 		acpi_os_printf ("Could Not get pathname for object %p\n", obj_handle);
 		return (AE_OK);
 	}
 
-	acpi_os_printf ("%32s", buffer);
+	acpi_os_printf ("%32s", buffer.pointer);
+	ACPI_MEM_FREE (buffer.pointer);
 
 
 	/* Display short information about the object */
@@ -714,7 +704,7 @@
 	NATIVE_CHAR             *obj_type_arg,
 	NATIVE_CHAR             *display_count_arg)
 {
-	acpi_object_type8       type;
+	acpi_object_type        type;
 
 
 	/* Get the object type */
@@ -725,17 +715,17 @@
 		return (AE_OK);
 	}
 
-	acpi_db_set_output_destination (DB_DUPLICATE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_DUPLICATE_OUTPUT);
 	acpi_os_printf ("Objects of type [%s] defined in the current ACPI Namespace: \n", acpi_ut_get_type_name (type));
 
-	acpi_db_set_output_destination (DB_REDIRECTABLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_REDIRECTABLE_OUTPUT);
 
 	/* Walk the namespace from the root */
 
 	acpi_walk_namespace (type, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
 			   acpi_db_walk_for_specific_objects, (void *) &type, NULL);
 
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 	return (AE_OK);
 }
 
@@ -763,8 +753,7 @@
 	acpi_status             status;
 	NATIVE_CHAR             *requested_name = (NATIVE_CHAR *) context;
 	u32                     i;
-	u32                     buf_size;
-	NATIVE_CHAR             buffer[96];
+	acpi_buffer             buffer;
 
 
 	/* Check for a name match */
@@ -783,16 +772,15 @@
 
 	/* Get the full pathname to this object */
 
-	buf_size = sizeof (buffer) / sizeof (*buffer);
-
-	status = acpi_ns_handle_to_pathname (obj_handle, &buf_size, buffer);
+	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
+	status = acpi_ns_handle_to_pathname (obj_handle, &buffer);
 	if (ACPI_FAILURE (status)) {
 		acpi_os_printf ("Could Not get pathname for object %p\n", obj_handle);
 	}
-
 	else {
-		acpi_os_printf ("%32s (%p) - %s\n", buffer, obj_handle,
+		acpi_os_printf ("%32s (%p) - %s\n", buffer.pointer, obj_handle,
 			acpi_ut_get_type_name (((acpi_namespace_node *) obj_handle)->type));
+		ACPI_MEM_FREE (buffer.pointer);
 	}
 
 	return (AE_OK);
@@ -817,7 +805,7 @@
 	NATIVE_CHAR             *name_arg)
 {
 
-	if (STRLEN (name_arg) > 4) {
+	if (ACPI_STRLEN (name_arg) > 4) {
 		acpi_os_printf ("Name must be no longer than 4 characters\n");
 		return (AE_OK);
 	}
@@ -827,7 +815,7 @@
 	acpi_walk_namespace (ACPI_TYPE_ANY, ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
 			   acpi_db_walk_and_match_name, name_arg, NULL);
 
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 	return (AE_OK);
 }
 
@@ -849,6 +837,9 @@
 acpi_db_set_scope (
 	NATIVE_CHAR             *name)
 {
+	acpi_status             status;
+	acpi_namespace_node     *node;
+
 
 	if (!name || name[0] == 0) {
 		acpi_os_printf ("Current scope: %s\n", acpi_gbl_db_scope_buf);
@@ -857,19 +848,38 @@
 
 	acpi_db_prep_namestring (name);
 
-	/* TBD: [Future] Validate scope here */
 
 	if (name[0] == '\\') {
-		STRCPY (acpi_gbl_db_scope_buf, name);
-		STRCAT (acpi_gbl_db_scope_buf, "\\");
-	}
+		/* Validate new scope from the root */
 
+		status = acpi_ns_get_node_by_path (name, acpi_gbl_root_node, ACPI_NS_NO_UPSEARCH, &node);
+		if (ACPI_FAILURE (status)) {
+			goto error_exit;
+		}
+
+		ACPI_STRCPY (acpi_gbl_db_scope_buf, name);
+		ACPI_STRCAT (acpi_gbl_db_scope_buf, "\\");
+	}
 	else {
-		STRCAT (acpi_gbl_db_scope_buf, name);
-		STRCAT (acpi_gbl_db_scope_buf, "\\");
+		/* Validate new scope relative to old scope */
+
+		status = acpi_ns_get_node_by_path (name, acpi_gbl_db_scope_node, ACPI_NS_NO_UPSEARCH, &node);
+		if (ACPI_FAILURE (status)) {
+			goto error_exit;
+		}
+
+		ACPI_STRCAT (acpi_gbl_db_scope_buf, name);
+		ACPI_STRCAT (acpi_gbl_db_scope_buf, "\\");
 	}
 
+	acpi_gbl_db_scope_node = node;
 	acpi_os_printf ("New scope: %s\n", acpi_gbl_db_scope_buf);
+	return;
+
+
+error_exit:
+
+	acpi_os_printf ("Could not attach scope: %s, %s\n", name, acpi_format_exception (status));
 }
 
 
@@ -895,18 +905,18 @@
 	acpi_buffer             return_obj;
 
 
-	acpi_db_set_output_destination (DB_REDIRECTABLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_REDIRECTABLE_OUTPUT);
+	acpi_dbg_level |= ACPI_LV_RESOURCES;
 
 	/* Convert string to object pointer */
 
-	obj_desc = (acpi_operand_object *) STRTOUL (object_arg, NULL, 16);
+	obj_desc = ACPI_TO_POINTER (ACPI_STRTOUL (object_arg, NULL, 16));
 
 	/* Prepare for a return object of arbitrary size */
 
 	return_obj.pointer          = acpi_gbl_db_buffer;
 	return_obj.length           = ACPI_DEBUG_BUFFER_SIZE;
 
-
 	/* _PRT */
 
 	acpi_os_printf ("Evaluating _PRT\n");
@@ -950,12 +960,19 @@
 	status = acpi_get_current_resources (obj_desc, &return_obj);
 	if (ACPI_FAILURE (status)) {
 		acpi_os_printf ("Acpi_get_current_resources failed: %s\n", acpi_format_exception (status));
+		goto get_prs;
 	}
 
 	else {
 		acpi_rs_dump_resource_list ((acpi_resource *) acpi_gbl_db_buffer);
 	}
 
+	status = acpi_set_current_resources (obj_desc, &return_obj);
+	if (ACPI_FAILURE (status)) {
+		acpi_os_printf ("Acpi_set_current_resources failed: %s\n", acpi_format_exception (status));
+		goto get_prs;
+	}
+
 
 	/* _PRS */
 
@@ -986,7 +1003,7 @@
 
 cleanup:
 
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 	return;
 #endif
 
diff -Nru a/drivers/acpi/debugger/dbdisasm.c b/drivers/acpi/debugger/dbdisasm.c
--- a/drivers/acpi/debugger/dbdisasm.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/debugger/dbdisasm.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbdisasm - parser op tree display routines
- *              $Revision: 50 $
+ *              $Revision: 61 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,10 +34,9 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbdisasm")
+	 ACPI_MODULE_NAME    ("dbdisasm")
 
 
-#define MAX_SHOW_ENTRY      128
 #define BLOCK_PAREN         1
 #define BLOCK_BRACE         2
 #define DB_NO_OP_INFO       "            [%2.2d]  "
@@ -67,14 +66,12 @@
 	switch (op->opcode) {
 	case AML_METHOD_OP:
 		return (BLOCK_BRACE);
-		break;
 
 	default:
 		break;
 	}
 
 	return (BLOCK_PAREN);
-
 }
 
 
@@ -101,11 +98,23 @@
 	acpi_parse_object       *op)
 {
 	acpi_parse_object       *target_op;
+	char                    *name;
 
 
+	if (op->flags & ACPI_PARSEOP_GENERIC) {
+		name = op->value.name;
+		if (name[0] == '\\') {
+			acpi_os_printf (" (Fully Qualified Pathname)");
+			return (AE_OK);
+		}
+	}
+	else {
+		name = (char *) &((acpi_parse2_object *) op)->name;
+	}
+
 	/* Search parent tree up to the root if necessary */
 
-	target_op = acpi_ps_find (op, op->value.name, 0, 0);
+	target_op = acpi_ps_find (op, name, 0, 0);
 	if (!target_op) {
 		/*
 		 * Didn't find the name in the parse tree.  This may be
@@ -115,7 +124,6 @@
 		 */
 		acpi_os_printf (" **** Path not found in parse tree");
 	}
-
 	else {
 		/* The target was found, print the name and complete path */
 
@@ -136,8 +144,7 @@
 {
 	acpi_status             status;
 	acpi_namespace_node     *node;
-	NATIVE_CHAR             buffer[MAX_SHOW_ENTRY];
-	u32                     buffer_size = MAX_SHOW_ENTRY;
+	acpi_buffer             buffer;
 	u32                     debug_level;
 
 
@@ -153,7 +160,7 @@
 		/* Node not defined in this scope, look it up */
 
 		status = acpi_ns_lookup (walk_state->scope_info, op->value.string, ACPI_TYPE_ANY,
-				  IMODE_EXECUTE, NS_SEARCH_PARENT, walk_state, &(node));
+				  ACPI_IMODE_EXECUTE, ACPI_NS_SEARCH_PARENT, walk_state, &(node));
 
 		if (ACPI_FAILURE (status)) {
 			/*
@@ -172,13 +179,15 @@
 
 	/* Convert Named_desc/handle to a full pathname */
 
-	status = acpi_ns_handle_to_pathname (node, &buffer_size, buffer);
+	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
+	status = acpi_ns_handle_to_pathname (node, &buffer);
 	if (ACPI_FAILURE (status)) {
 		acpi_os_printf ("****Could not get pathname****)");
 		goto exit;
 	}
 
-	acpi_os_printf (" (Path %s)", buffer);
+	acpi_os_printf (" (Path %s)", buffer.pointer);
+	ACPI_MEM_FREE (buffer.pointer);
 
 
 exit:
@@ -219,118 +228,115 @@
 	u32                     j;
 
 
-	if (op) {
-		while (op) {
-			/* indentation */
-
-			depth_count = 0;
-			if (!acpi_gbl_db_opt_verbose) {
-				depth_count++;
+	if (!op) {
+		acpi_db_display_opcode (walk_state, op);
+		return;
+	}
+
+
+	while (op) {
+		/* Indentation */
+
+		depth_count = 0;
+		if (!acpi_gbl_db_opt_verbose) {
+			depth_count++;
+		}
+
+		/* Determine the nesting depth of this argument */
+
+		for (depth = op->parent; depth; depth = depth->parent) {
+			arg = acpi_ps_get_arg (depth, 0);
+			while (arg && arg != origin) {
+				arg = arg->next;
 			}
 
-			/* Determine the nesting depth of this argument */
+			if (arg) {
+				break;
+			}
 
-			for (depth = op->parent; depth; depth = depth->parent) {
-				arg = acpi_ps_get_arg (depth, 0);
-				while (arg && arg != origin) {
-					arg = arg->next;
-				}
+			depth_count++;
+		}
 
-				if (arg) {
-					break;
-				}
+		/* Open a new block if we are nested further than last time */
 
-				depth_count++;
+		if (depth_count > last_depth) {
+			VERBOSE_PRINT ((DB_NO_OP_INFO, last_depth));
+			for (i = 0; i < last_depth; i++) {
+				acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
 			}
 
+			if (acpi_db_block_type (op) == BLOCK_PAREN) {
+				acpi_os_printf ("(\n");
+			}
+			else {
+				acpi_os_printf ("{\n");
+			}
+		}
 
-			/* Open a new block if we are nested further than last time */
+		/* Close a block if we are nested less than last time */
 
-			if (depth_count > last_depth) {
-				VERBOSE_PRINT ((DB_NO_OP_INFO, last_depth));
-				for (i = 0; i < last_depth; i++) {
+		else if (depth_count < last_depth) {
+			for (j = 0; j < (last_depth - depth_count); j++) {
+				VERBOSE_PRINT ((DB_NO_OP_INFO, last_depth - j));
+				for (i = 0; i < (last_depth - j - 1); i++) {
 					acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
 				}
 
 				if (acpi_db_block_type (op) == BLOCK_PAREN) {
-					acpi_os_printf ("(\n");
+					acpi_os_printf (")\n");
 				}
 				else {
-					acpi_os_printf ("{\n");
+					acpi_os_printf ("}\n");
 				}
 			}
+		}
 
-			/* Close a block if we are nested less than last time */
-
-			else if (depth_count < last_depth) {
-				for (j = 0; j < (last_depth - depth_count); j++) {
-					VERBOSE_PRINT ((DB_NO_OP_INFO, last_depth - j));
-					for (i = 0; i < (last_depth - j - 1); i++) {
-						acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
-					}
-
-					if (acpi_db_block_type (op) == BLOCK_PAREN) {
-						acpi_os_printf (")\n");
-					}
-					else {
-						acpi_os_printf ("}\n");
-					}
-				}
-			}
-
-			/* In verbose mode, print the AML offset, opcode and depth count */
-
-			VERBOSE_PRINT ((DB_FULL_OP_INFO, (unsigned) op->aml_offset, op->opcode, depth_count));
+		/* In verbose mode, print the AML offset, opcode and depth count */
 
+		VERBOSE_PRINT ((DB_FULL_OP_INFO, (unsigned) op->aml_offset, op->opcode, depth_count));
 
-			/* Indent the output according to the depth count */
 
-			for (i = 0; i < depth_count; i++) {
-				acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
-			}
+		/* Indent the output according to the depth count */
 
+		for (i = 0; i < depth_count; i++) {
+			acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
+		}
 
-			/* Now print the opcode */
+		/* Now print the opcode */
 
-			acpi_db_display_opcode (walk_state, op);
+		acpi_db_display_opcode (walk_state, op);
 
-			/* Resolve a name reference */
+		/* Resolve a name reference */
 
-			if ((op->opcode == AML_INT_NAMEPATH_OP && op->value.name)  &&
-				(op->parent) &&
-				(acpi_gbl_db_opt_verbose)) {
-				acpi_ps_display_object_pathname (walk_state, op);
-			}
+		if ((op->opcode == AML_INT_NAMEPATH_OP && op->value.name)  &&
+			(op->parent) &&
+			(acpi_gbl_db_opt_verbose)) {
+			acpi_ps_display_object_pathname (walk_state, op);
+		}
 
-			acpi_os_printf ("\n");
+		acpi_os_printf ("\n");
 
-			/* Get the next node in the tree */
+		/* Get the next node in the tree */
 
-			op = acpi_ps_get_depth_next (origin, op);
-			last_depth = depth_count;
+		op = acpi_ps_get_depth_next (origin, op);
+		last_depth = depth_count;
 
-			num_opcodes--;
-			if (!num_opcodes) {
-				op = NULL;
-			}
+		num_opcodes--;
+		if (!num_opcodes) {
+			op = NULL;
 		}
+	}
 
-		/* Close the last block(s) */
+	/* Close the last block(s) */
 
-		depth_count = last_depth -1;
-		for (i = 0; i < last_depth; i++) {
-			VERBOSE_PRINT ((DB_NO_OP_INFO, last_depth - i));
-			for (j = 0; j < depth_count; j++) {
-				acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
-			}
-			acpi_os_printf ("}\n");
-			depth_count--;
+	depth_count = last_depth -1;
+	for (i = 0; i < last_depth; i++) {
+		VERBOSE_PRINT ((DB_NO_OP_INFO, last_depth - i));
+		for (j = 0; j < depth_count; j++) {
+			acpi_os_printf ("%s", acpi_gbl_db_disasm_indent);
 		}
-
-	}
-
-	else {
-		acpi_db_display_opcode (walk_state, op);
+		acpi_os_printf ("}\n");
+		depth_count--;
 	}
 }
 
@@ -352,7 +358,6 @@
 	NATIVE_CHAR             *name)
 {
 	u32                     seg_count;
-	u8                      do_dot = FALSE;
 
 
 	if (!name) {
@@ -360,21 +365,27 @@
 		return;
 	}
 
-	if (acpi_ps_is_prefix_char (GET8 (name))) {
-		/* append prefix character */
+	/* Handle all Scope Prefix operators */
+
+	while (acpi_ps_is_prefix_char (ACPI_GET8 (name))) {
+		/* Append prefix character */
 
-		acpi_os_printf ("%1c", GET8 (name));
+		acpi_os_printf ("%1c", ACPI_GET8 (name));
 		name++;
 	}
 
-	switch (GET8 (name)) {
+	switch (ACPI_GET8 (name)) {
+	case 0:
+		seg_count = 0;
+		break;
+
 	case AML_DUAL_NAME_PREFIX:
 		seg_count = 2;
 		name++;
 		break;
 
 	case AML_MULTI_NAME_PREFIX_OP:
-		seg_count = (u32) GET8 (name + 1);
+		seg_count = (u32) ACPI_GET8 (name + 1);
 		name += 2;
 		break;
 
@@ -383,19 +394,18 @@
 		break;
 	}
 
-	while (seg_count--) {
-		/* append Name segment */
+	while (seg_count) {
+		/* Append Name segment */
+
+		acpi_os_printf ("%4.4s", name);
 
-		if (do_dot) {
-			/* append dot */
+		seg_count--;
+		if (seg_count) {
+			/* Not last name, append dot separator */
 
 			acpi_os_printf (".");
 		}
-
-		acpi_os_printf ("%4.4s", name);
-		do_dot = TRUE;
-
-		name += 4;
+		name += ACPI_NAME_SIZE;
 	}
 }
 
@@ -433,7 +443,6 @@
 		return;
 	}
 
-
 	if (op_info->flags & AML_CREATE) {
 		/* Field creation - check for a fully qualified namepath */
 
@@ -492,7 +501,6 @@
 						acpi_os_printf ("%4.4s", name_path->value.string);
 					}
 				}
-
 				else {
 					name = acpi_ps_get_name (search);
 					acpi_os_printf ("%4.4s", &name);
@@ -538,21 +546,17 @@
 		acpi_os_printf ("<NULL OP PTR>");
 	}
 
-
 	/* op and arguments */
 
 	switch (op->opcode) {
-
 	case AML_BYTE_OP:
 
 		if (acpi_gbl_db_opt_verbose) {
 			acpi_os_printf ("(u8) 0x%2.2X", op->value.integer8);
 		}
-
 		else {
 			acpi_os_printf ("0x%2.2X", op->value.integer8);
 		}
-
 		break;
 
 
@@ -561,11 +565,9 @@
 		if (acpi_gbl_db_opt_verbose) {
 			acpi_os_printf ("(u16) 0x%4.4X", op->value.integer16);
 		}
-
 		else {
 			acpi_os_printf ("0x%4.4X", op->value.integer16);
 		}
-
 		break;
 
 
@@ -574,11 +576,9 @@
 		if (acpi_gbl_db_opt_verbose) {
 			acpi_os_printf ("(u32) 0x%8.8X", op->value.integer32);
 		}
-
 		else {
 			acpi_os_printf ("0x%8.8X", op->value.integer32);
 		}
-
 		break;
 
 
@@ -588,12 +588,10 @@
 			acpi_os_printf ("(u64) 0x%8.8X%8.8X", op->value.integer64.hi,
 					 op->value.integer64.lo);
 		}
-
 		else {
 			acpi_os_printf ("0x%8.8X%8.8X", op->value.integer64.hi,
 					 op->value.integer64.lo);
 		}
-
 		break;
 
 
@@ -602,11 +600,9 @@
 		if (op->value.string) {
 			acpi_os_printf ("\"%s\"", op->value.string);
 		}
-
 		else {
 			acpi_os_printf ("<\"NULL STRING PTR\">");
 		}
-
 		break;
 
 
@@ -615,11 +611,9 @@
 		if (op->value.string) {
 			acpi_os_printf ("\"%s\"", op->value.string);
 		}
-
 		else {
 			acpi_os_printf ("\"<NULL STATIC STRING PTR>\"");
 		}
-
 		break;
 
 
@@ -652,7 +646,6 @@
 		if (acpi_gbl_db_opt_verbose) {
 			acpi_os_printf ("Byte_list   (Length 0x%8.8X)  ", op->value.integer32);
 		}
-
 		else {
 			acpi_os_printf ("0x%2.2X", op->value.integer32);
 
@@ -663,7 +656,6 @@
 				acpi_os_printf (", 0x%2.2X", byte_data[i]);
 			}
 		}
-
 		break;
 
 
@@ -682,7 +674,6 @@
 			acpi_db_decode_internal_object (walk_state->results->results.obj_desc [walk_state->results->results.num_results-1]);
 		}
 #endif
-
 		break;
 	}
 
@@ -702,14 +693,11 @@
 		name = acpi_ps_get_name (op);
 		acpi_os_printf (" %4.4s", &name);
 
-		if (acpi_gbl_db_opt_verbose) {
-			acpi_os_printf (" (Path \\");
-			acpi_db_display_path (op);
-			acpi_os_printf (")");
+		if ((acpi_gbl_db_opt_verbose) && (op->opcode != AML_INT_NAMEDFIELD_OP)) {
+			acpi_ps_display_object_pathname (walk_state, op);
 		}
 	}
 }
-
 
 #endif  /* ENABLE_DEBUGGER */
 
diff -Nru a/drivers/acpi/debugger/dbdisply.c b/drivers/acpi/debugger/dbdisply.c
--- a/drivers/acpi/debugger/dbdisply.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/debugger/dbdisply.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbdisply - debug display commands
- *              $Revision: 57 $
+ *              $Revision: 66 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -39,7 +39,7 @@
 
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbdisply")
+	 ACPI_MODULE_NAME    ("dbdisply")
 
 
 /******************************************************************************
@@ -75,8 +75,7 @@
 
 	/* Simple flat pointer */
 
-	obj_ptr = (void *) STRTOUL (target, NULL, 16);
-
+	obj_ptr = ACPI_TO_POINTER (ACPI_STRTOUL (target, NULL, 16));
 #endif
 
 	return (obj_ptr);
@@ -107,7 +106,7 @@
 	acpi_os_printf ("Parser Op Descriptor:\n");
 	acpi_os_printf ("%20.20s : %4.4X\n", "Opcode", op->opcode);
 
-	DEBUG_ONLY_MEMBERS (acpi_os_printf ("%20.20s : %s\n", "Opcode Name", info->name));
+	ACPI_DEBUG_ONLY_MEMBERS (acpi_os_printf ("%20.20s : %s\n", "Opcode Name", info->name));
 
 	acpi_os_printf ("%20.20s : %p\n", "Value/Arg_list", op->value);
 	acpi_os_printf ("%20.20s : %p\n", "Parent", op->parent);
@@ -136,6 +135,7 @@
 {
 	void                    *obj_ptr;
 	acpi_namespace_node     *node;
+	acpi_operand_object     *obj_desc;
 	u32                     display = DB_BYTE_DISPLAY;
 	NATIVE_CHAR             buffer[80];
 	acpi_buffer             ret_buf;
@@ -150,7 +150,7 @@
 	/* Decode the output type */
 
 	if (output_type) {
-		STRUPR (output_type);
+		ACPI_STRUPR (output_type);
 		if (output_type[0] == 'W') {
 			display = DB_WORD_DISPLAY;
 		}
@@ -162,7 +162,6 @@
 		}
 	}
 
-
 	ret_buf.length = sizeof (buffer);
 	ret_buf.pointer = buffer;
 
@@ -177,8 +176,10 @@
 
 		/* Decode the object type */
 
-		if (VALID_DESCRIPTOR_TYPE ((obj_ptr), ACPI_DESC_TYPE_NAMED)) {
-			/* This is a Node */
+		switch (ACPI_GET_DESCRIPTOR_TYPE (obj_ptr)) {
+		case ACPI_DESC_TYPE_NAMED:
+
+			/* This is a namespace Node */
 
 			if (!acpi_os_readable (obj_ptr, sizeof (acpi_namespace_node))) {
 				acpi_os_printf ("Cannot read entire Named object at address %p\n", obj_ptr);
@@ -187,10 +188,11 @@
 
 			node = obj_ptr;
 			goto dump_nte;
-		}
 
-		else if (VALID_DESCRIPTOR_TYPE ((obj_ptr), ACPI_DESC_TYPE_INTERNAL)) {
-			/* This is an ACPI OBJECT */
+
+		case ACPI_DESC_TYPE_INTERNAL:
+
+			/* This is a ACPI OPERAND OBJECT */
 
 			if (!acpi_os_readable (obj_ptr, sizeof (acpi_operand_object))) {
 				acpi_os_printf ("Cannot read entire ACPI object at address %p\n", obj_ptr);
@@ -199,22 +201,27 @@
 
 			acpi_ut_dump_buffer (obj_ptr, sizeof (acpi_operand_object), display, ACPI_UINT32_MAX);
 			acpi_ex_dump_object_descriptor (obj_ptr, 1);
-		}
+			break;
 
-		else if (VALID_DESCRIPTOR_TYPE ((obj_ptr), ACPI_DESC_TYPE_PARSER)) {
-			/* This is an Parser Op object */
+
+		case ACPI_DESC_TYPE_PARSER:
+
+			/* This is a Parser Op object */
 
 			if (!acpi_os_readable (obj_ptr, sizeof (acpi_parse_object))) {
 				acpi_os_printf ("Cannot read entire Parser object at address %p\n", obj_ptr);
 				return;
 			}
 
-
 			acpi_ut_dump_buffer (obj_ptr, sizeof (acpi_parse_object), display, ACPI_UINT32_MAX);
 			acpi_db_dump_parser_descriptor ((acpi_parse_object *) obj_ptr);
-		}
+			break;
+
+
+		default:
+
+			/* Is not a recognizeable object */
 
-		else {
 			size = 16;
 			if (acpi_os_readable (obj_ptr, 64)) {
 				size = 64;
@@ -223,12 +230,12 @@
 			/* Just dump some memory */
 
 			acpi_ut_dump_buffer (obj_ptr, size, display, ACPI_UINT32_MAX);
+			break;
 		}
 
 		return;
 	}
 
-
 	/* The parameter is a name string that must be resolved to a Named obj */
 
 	node = acpi_db_local_ns_lookup (target);
@@ -257,15 +264,16 @@
 	acpi_ut_dump_buffer ((void *) node, sizeof (acpi_namespace_node), display, ACPI_UINT32_MAX);
 	acpi_ex_dump_node (node, 1);
 
-	if (node->object) {
-		acpi_os_printf ("\n_attached Object (%p):\n", node->object);
-		if (!acpi_os_readable (node->object, sizeof (acpi_operand_object))) {
-			acpi_os_printf ("Invalid internal ACPI Object at address %p\n", node->object);
+	obj_desc = acpi_ns_get_attached_object (node);
+	if (obj_desc) {
+		acpi_os_printf ("\n_attached Object (%p):\n", obj_desc);
+		if (!acpi_os_readable (obj_desc, sizeof (acpi_operand_object))) {
+			acpi_os_printf ("Invalid internal ACPI Object at address %p\n", obj_desc);
 			return;
 		}
 
-		acpi_ut_dump_buffer ((void *) node->object, sizeof (acpi_operand_object), display, ACPI_UINT32_MAX);
-		acpi_ex_dump_object_descriptor (node->object, 1);
+		acpi_ut_dump_buffer ((void *) obj_desc, sizeof (acpi_operand_object), display, ACPI_UINT32_MAX);
+		acpi_ex_dump_object_descriptor (obj_desc, 1);
 	}
 }
 
@@ -298,8 +306,8 @@
 	switch (obj_desc->common.type) {
 	case ACPI_TYPE_INTEGER:
 
-		acpi_os_printf (" %.8X%.8X", HIDWORD (obj_desc->integer.value),
-				 LODWORD (obj_desc->integer.value));
+		acpi_os_printf (" %.8X%.8X", ACPI_HIDWORD (obj_desc->integer.value),
+				 ACPI_LODWORD (obj_desc->integer.value));
 		break;
 
 
@@ -358,26 +366,32 @@
 		return;
 	}
 
-
 	/* Decode the object type */
 
-	else if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_PARSER)) {
+	switch (ACPI_GET_DESCRIPTOR_TYPE (obj_desc)) {
+	case ACPI_DESC_TYPE_PARSER:
+
 		acpi_os_printf ("<Parser> ");
-	}
+		break;
+
+
+	case ACPI_DESC_TYPE_NAMED:
 
-	else if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_NAMED)) {
 		acpi_os_printf ("<Node>          Name %4.4s Type-%s",
 				  &((acpi_namespace_node *)obj_desc)->name,
 				  acpi_ut_get_type_name (((acpi_namespace_node *) obj_desc)->type));
+
 		if (((acpi_namespace_node *) obj_desc)->flags & ANOBJ_METHOD_ARG) {
 			acpi_os_printf (" [Method Arg]");
 		}
 		if (((acpi_namespace_node *) obj_desc)->flags & ANOBJ_METHOD_LOCAL) {
 			acpi_os_printf (" [Method Local]");
 		}
-	}
+		break;
+
+
+	case ACPI_DESC_TYPE_INTERNAL:
 
-	else if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_INTERNAL)) {
 		type = obj_desc->common.type;
 		if (type > INTERNAL_TYPE_MAX) {
 			acpi_os_printf (" Type %x [Invalid Type]", type);
@@ -428,7 +442,7 @@
 				break;
 
 			case AML_INDEX_OP:
-				acpi_os_printf ("[Index]   ");
+				acpi_os_printf ("[Index]         ");
 				acpi_db_decode_internal_object (obj_desc->reference.object);
 				break;
 
@@ -444,12 +458,16 @@
 			acpi_db_decode_internal_object (obj_desc);
 			break;
 		}
-	}
+		break;
+
+
+	default:
 
-	else {
 		acpi_os_printf ("<Not a valid ACPI Object Descriptor> ");
+		break;
 	}
 
+
 	acpi_os_printf ("\n");
 }
 
@@ -494,9 +512,9 @@
 	}
 
 	obj_desc = walk_state->method_desc;
-	node = walk_state->method_node;
+	node    = walk_state->method_node;
 
-	num_args = obj_desc->method.param_count;
+	num_args    = obj_desc->method.param_count;
 	concurrency = obj_desc->method.concurrency;
 
 	acpi_os_printf ("Currently executing control method is [%4.4s]\n", &node->name);
@@ -546,7 +564,6 @@
 			break;
 		}
 
-
 		op = acpi_ps_get_depth_next (start_op, op);
 	}
 
@@ -587,8 +604,6 @@
 
 	obj_desc = walk_state->method_desc;
 	node = walk_state->method_node;
-
-
 	acpi_os_printf ("Local Variables for method [%4.4s]:\n", &node->name);
 
 	for (i = 0; i < MTH_NUM_LOCALS; i++) {
@@ -629,12 +644,13 @@
 	}
 
 	obj_desc = walk_state->method_desc;
-	node = walk_state->method_node;
+	node    = walk_state->method_node;
 
-	num_args = obj_desc->method.param_count;
+	num_args    = obj_desc->method.param_count;
 	concurrency = obj_desc->method.concurrency;
 
-	acpi_os_printf ("Method [%4.4s] has %X arguments, max concurrency = %X\n", &node->name, num_args, concurrency);
+	acpi_os_printf ("Method [%4.4s] has %X arguments, max concurrency = %X\n",
+			&node->name, num_args, concurrency);
 
 	for (i = 0; i < num_args; i++) {
 		obj_desc = walk_state->arguments[i].object;
@@ -679,7 +695,8 @@
 		num_results = walk_state->results->results.num_results;
 	}
 
-	acpi_os_printf ("Method [%4.4s] has %X stacked result objects\n", &node->name, num_results);
+	acpi_os_printf ("Method [%4.4s] has %X stacked result objects\n",
+		&node->name, num_results);
 
 	for (i = 0; i < num_results; i++) {
 		obj_desc = walk_state->results->results.obj_desc[i];
@@ -716,7 +733,6 @@
 	}
 
 	node = walk_state->method_node;
-
 	acpi_os_printf ("Current Control Method Call Tree\n");
 
 	for (i = 0; walk_state; i++) {
@@ -740,6 +756,10 @@
  *
  * DESCRIPTION: Display the result of an AML opcode
  *
+ * Note: Curently only displays the result object if we are single stepping.
+ * However, this output may be useful in other contexts and could be enabled
+ * to do so if needed.
+ *
  ******************************************************************************/
 
 void
@@ -748,10 +768,8 @@
 	acpi_walk_state         *walk_state)
 {
 
-	/* TBD: [Future] We don't always want to display the result.
-	 * For now, only display if single stepping
-	 * however, this output is very useful in other contexts also
-	 */
+	/* Only display if single stepping */
+
 	if (!acpi_gbl_cm_single_step) {
 		return;
 	}
@@ -780,7 +798,6 @@
 	acpi_operand_object     *obj_desc,
 	acpi_walk_state         *walk_state)
 {
-
 
 	if (!acpi_gbl_cm_single_step) {
 		return;
diff -Nru a/drivers/acpi/debugger/dbexec.c b/drivers/acpi/debugger/dbexec.c
--- a/drivers/acpi/debugger/dbexec.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/debugger/dbexec.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbexec - debugger control method execution
- *              $Revision: 34 $
+ *              $Revision: 39 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -38,10 +38,10 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbexec")
+	 ACPI_MODULE_NAME    ("dbexec")
 
 
-db_method_info              acpi_gbl_db_method_info;
+acpi_db_method_info         acpi_gbl_db_method_info;
 
 
 /*******************************************************************************
@@ -59,7 +59,7 @@
 
 acpi_status
 acpi_db_execute_method (
-	db_method_info          *info,
+	acpi_db_method_info     *info,
 	acpi_buffer             *return_obj)
 {
 	acpi_status             status;
@@ -77,13 +77,12 @@
 	if (info->args && info->args[0]) {
 		for (i = 0; info->args[i] && i < MTH_NUM_ARGS; i++) {
 			params[i].type              = ACPI_TYPE_INTEGER;
-			params[i].integer.value     = STRTOUL (info->args[i], NULL, 16);
+			params[i].integer.value     = ACPI_STRTOUL (info->args[i], NULL, 16);
 		}
 
 		param_objects.pointer       = params;
 		param_objects.count         = i;
 	}
-
 	else {
 		/* Setup default parameters */
 
@@ -103,7 +102,6 @@
 	return_obj->pointer          = acpi_gbl_db_buffer;
 	return_obj->length           = ACPI_DEBUG_BUFFER_SIZE;
 
-
 	/* Do the actual method execution */
 
 	status = acpi_evaluate_object (NULL, info->pathname, &param_objects, return_obj);
@@ -129,7 +127,7 @@
 
 void
 acpi_db_execute_setup (
-	db_method_info          *info)
+	acpi_db_method_info         *info)
 {
 
 	/* Catenate the current scope to the supplied name */
@@ -137,24 +135,24 @@
 	info->pathname[0] = 0;
 	if ((info->name[0] != '\\') &&
 		(info->name[0] != '/')) {
-		STRCAT (info->pathname, acpi_gbl_db_scope_buf);
+		ACPI_STRCAT (info->pathname, acpi_gbl_db_scope_buf);
 	}
 
-	STRCAT (info->pathname, info->name);
+	ACPI_STRCAT (info->pathname, info->name);
 	acpi_db_prep_namestring (info->pathname);
 
-	acpi_db_set_output_destination (DB_DUPLICATE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_DUPLICATE_OUTPUT);
 	acpi_os_printf ("Executing %s\n", info->pathname);
 
 	if (info->flags & EX_SINGLE_STEP) {
 		acpi_gbl_cm_single_step = TRUE;
-		acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+		acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 	}
 
 	else {
 		/* No single step, allow redirection to a file */
 
-		acpi_db_set_output_destination (DB_REDIRECTABLE_OUTPUT);
+		acpi_db_set_output_destination (ACPI_DB_REDIRECTABLE_OUTPUT);
 	}
 }
 
@@ -176,11 +174,11 @@
 u32
 acpi_db_get_outstanding_allocations (void)
 {
-	u32                     i;
 	u32                     outstanding = 0;
 
-
 #ifdef ACPI_DBG_TRACK_ALLOCATIONS
+	u32                     i;
+
 
 	for (i = ACPI_MEM_LIST_FIRST_CACHE_LIST; i < ACPI_NUM_MEM_LISTS; i++) {
 		outstanding += (acpi_gbl_memory_lists[i].total_allocated -
@@ -248,7 +246,7 @@
 
 	allocations = acpi_db_get_outstanding_allocations () - previous_allocations;
 
-	acpi_db_set_output_destination (DB_DUPLICATE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_DUPLICATE_OUTPUT);
 
 	if (allocations > 0) {
 		acpi_os_printf ("Outstanding: %ld allocations after execution\n",
@@ -271,7 +269,7 @@
 		}
 	}
 
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 }
 
 
@@ -288,12 +286,12 @@
  *
  ******************************************************************************/
 
-void
+void ACPI_SYSTEM_XFACE
 acpi_db_method_thread (
 	void                    *context)
 {
 	acpi_status             status;
-	db_method_info          *info = context;
+	acpi_db_method_info     *info = context;
 	u32                     i;
 	acpi_buffer             return_obj;
 
@@ -344,15 +342,14 @@
 
 	/* Get the arguments */
 
-	num_threads = STRTOUL (num_threads_arg, NULL, 0);
-	num_loops = STRTOUL (num_loops_arg, NULL, 0);
+	num_threads = ACPI_STRTOUL (num_threads_arg, NULL, 0);
+	num_loops  = ACPI_STRTOUL (num_loops_arg, NULL, 0);
 
 	if (!num_threads || !num_loops) {
 		acpi_os_printf ("Bad argument: Threads %X, Loops %X\n", num_threads, num_loops);
 		return;
 	}
 
-
 	/* Create the synchronization semaphore */
 
 	status = acpi_os_create_semaphore (1, 0, &thread_gate);
@@ -371,7 +368,6 @@
 
 	acpi_db_execute_setup (&acpi_gbl_db_method_info);
 
-
 	/* Create the threads */
 
 	acpi_os_printf ("Creating %X threads to execute %X times each\n", num_threads, num_loops);
@@ -380,7 +376,6 @@
 		acpi_os_queue_for_execution (OSD_PRIORITY_MED, acpi_db_method_thread, &acpi_gbl_db_method_info);
 	}
 
-
 	/* Wait for all threads to complete */
 
 	i = num_threads;
@@ -393,9 +388,9 @@
 
 	acpi_os_delete_semaphore (thread_gate);
 
-	acpi_db_set_output_destination (DB_DUPLICATE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_DUPLICATE_OUTPUT);
 	acpi_os_printf ("All threads (%X) have completed\n", num_threads);
-	acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+	acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 }
 
 
diff -Nru a/drivers/acpi/debugger/dbfileio.c b/drivers/acpi/debugger/dbfileio.c
--- a/drivers/acpi/debugger/dbfileio.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/debugger/dbfileio.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: dbfileio - Debugger file I/O commands.  These can't usually
  *              be used when running the debugger in Ring 0 (Kernel mode)
- *              $Revision: 53 $
+ *              $Revision: 59 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,7 +35,7 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbfileio")
+	 ACPI_MODULE_NAME    ("dbfileio")
 
 
 /*
@@ -64,7 +64,7 @@
  *
  ******************************************************************************/
 
-acpi_object_type8
+acpi_object_type
 acpi_db_match_argument (
 	NATIVE_CHAR             *user_argument,
 	ARGUMENT_INFO           *arguments)
@@ -77,8 +77,8 @@
 	}
 
 	for (i = 0; arguments[i].name; i++) {
-		if (STRSTR (arguments[i].name, user_argument) == arguments[i].name) {
-			return ((acpi_object_type8) i);
+		if (ACPI_STRSTR (arguments[i].name, user_argument) == arguments[i].name) {
+			return (i);
 		}
 	}
 
@@ -141,7 +141,7 @@
 	acpi_gbl_debug_file = fopen (name, "w+");
 	if (acpi_gbl_debug_file) {
 		acpi_os_printf ("Debug output file %s opened\n", name);
-		STRCPY (acpi_gbl_db_debug_filename, name);
+		ACPI_STRCPY (acpi_gbl_db_debug_filename, name);
 		acpi_gbl_db_output_to_file = TRUE;
 	}
 	else {
@@ -200,11 +200,11 @@
 
 	/* We only support a limited number of table types */
 
-	if (STRNCMP ((char *) table_header.signature, DSDT_SIG, 4) &&
-		STRNCMP ((char *) table_header.signature, PSDT_SIG, 4) &&
-		STRNCMP ((char *) table_header.signature, SSDT_SIG, 4)) {
+	if (ACPI_STRNCMP ((char *) table_header.signature, DSDT_SIG, 4) &&
+		ACPI_STRNCMP ((char *) table_header.signature, PSDT_SIG, 4) &&
+		ACPI_STRNCMP ((char *) table_header.signature, SSDT_SIG, 4)) {
 		acpi_os_printf ("Table signature is invalid\n");
-		DUMP_BUFFER (&table_header, sizeof (acpi_table_header));
+		ACPI_DUMP_BUFFER (&table_header, sizeof (acpi_table_header));
 		return (AE_ERROR);
 	}
 
@@ -224,7 +224,7 @@
 
 	/* Copy the header to the buffer */
 
-	MEMCPY (*table_ptr, &table_header, sizeof (table_header));
+	ACPI_MEMCPY (*table_ptr, &table_header, sizeof (table_header));
 
 	/* Get the rest of the table */
 
@@ -275,7 +275,7 @@
 	acpi_table_desc         table_info;
 
 
-	FUNCTION_TRACE ("Ae_local_load_table");
+	ACPI_FUNCTION_TRACE ("Ae_local_load_table");
 
 	if (!table_ptr) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
@@ -354,7 +354,7 @@
 
 	status = ae_local_load_table (acpi_gbl_db_table_ptr);
 	if (ACPI_FAILURE (status)) {
-		if (status == AE_EXIST) {
+		if (status == AE_ALREADY_EXISTS) {
 			acpi_os_printf ("Table %4.4s is already installed\n",
 					  &acpi_gbl_db_table_ptr->signature);
 		}
@@ -363,7 +363,6 @@
 					  acpi_format_exception (status));
 		}
 
-		acpi_os_free (acpi_gbl_db_table_ptr);
 		return (status);
 	}
 
diff -Nru a/drivers/acpi/debugger/dbhistry.c b/drivers/acpi/debugger/dbhistry.c
--- a/drivers/acpi/debugger/dbhistry.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/debugger/dbhistry.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dbhistry - debugger HISTORY command
- *              $Revision: 19 $
+ *              $Revision: 22 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -38,7 +38,7 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbhistry")
+	 ACPI_MODULE_NAME    ("dbhistry")
 
 
 #define HI_NO_HISTORY       0
@@ -78,10 +78,9 @@
 	NATIVE_CHAR             *command_line)
 {
 
-
 	/* Put command into the next available slot */
 
-	STRCPY (acpi_gbl_history_buffer[acpi_gbl_next_history_index].command, command_line);
+	ACPI_STRCPY (acpi_gbl_history_buffer[acpi_gbl_next_history_index].command, command_line);
 
 	acpi_gbl_history_buffer[acpi_gbl_next_history_index].cmd_num = acpi_gbl_next_cmd_num;
 
@@ -100,12 +99,10 @@
 		acpi_gbl_next_history_index = 0;
 	}
 
-
 	acpi_gbl_next_cmd_num++;
 	if (acpi_gbl_num_history < HISTORY_SIZE) {
 		acpi_gbl_num_history++;
 	}
-
 }
 
 
@@ -171,9 +168,8 @@
 	}
 
 	else {
-		cmd_num = STRTOUL (command_num_arg, NULL, 0);
+		cmd_num = ACPI_STRTOUL (command_num_arg, NULL, 0);
 	}
-
 
 	/* Search history buffer */
 
diff -Nru a/drivers/acpi/debugger/dbinput.c b/drivers/acpi/debugger/dbinput.c
--- a/drivers/acpi/debugger/dbinput.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/debugger/dbinput.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbinput - user front-end to the AML debugger
- *              $Revision: 72 $
+ *              $Revision: 81 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,56 +35,14 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbinput")
+	 ACPI_MODULE_NAME    ("dbinput")
 
 
 /*
- * Globals that are specific to the debugger
- */
-
-NATIVE_CHAR                 acpi_gbl_db_line_buf[80];
-NATIVE_CHAR                 acpi_gbl_db_parsed_buf[80];
-NATIVE_CHAR                 acpi_gbl_db_scope_buf[40];
-NATIVE_CHAR                 acpi_gbl_db_debug_filename[40];
-NATIVE_CHAR                 *acpi_gbl_db_args[DB_MAX_ARGS];
-NATIVE_CHAR                 *acpi_gbl_db_buffer = NULL;
-NATIVE_CHAR                 *acpi_gbl_db_filename = NULL;
-u8                          acpi_gbl_db_output_to_file = FALSE;
-
-u32                         acpi_gbl_db_debug_level = ACPI_LV_VERBOSITY2;
-u32                         acpi_gbl_db_console_debug_level = NORMAL_DEFAULT | ACPI_LV_TABLES;
-u8                          acpi_gbl_db_output_flags = DB_CONSOLE_OUTPUT;
-
-
-u8                          acpi_gbl_db_opt_tables    = FALSE;
-u8                          acpi_gbl_db_opt_disasm    = FALSE;
-u8                          acpi_gbl_db_opt_stats     = FALSE;
-u8                          acpi_gbl_db_opt_parse_jit = FALSE;
-u8                          acpi_gbl_db_opt_verbose   = TRUE;
-u8                          acpi_gbl_db_opt_ini_methods = TRUE;
-
-/*
- * Statistic globals
- */
-u16                         acpi_gbl_obj_type_count[INTERNAL_TYPE_NODE_MAX+1];
-u16                         acpi_gbl_node_type_count[INTERNAL_TYPE_NODE_MAX+1];
-u16                         acpi_gbl_obj_type_count_misc;
-u16                         acpi_gbl_node_type_count_misc;
-u32                         acpi_gbl_num_nodes;
-u32                         acpi_gbl_num_objects;
-
-
-u32                         acpi_gbl_size_of_parse_tree;
-u32                         acpi_gbl_size_of_method_trees;
-u32                         acpi_gbl_size_of_node_entries;
-u32                         acpi_gbl_size_of_acpi_objects;
-
-/*
  * Top-level debugger commands.
  *
  * This list of commands must match the string table below it
  */
-
 enum acpi_ex_debugger_commands
 {
 	CMD_NOT_FOUND = 0,
@@ -224,13 +182,11 @@
 
 	}
 
-
 	/*
 	 * Parameter is the command class
 	 *
 	 * The idea here is to keep each class of commands smaller than a screenful
 	 */
-
 	switch (help_type[0])
 	{
 	case 'G':
@@ -321,6 +277,7 @@
 {
 	NATIVE_CHAR             *start;
 
+
 	/* At end of buffer? */
 
 	if (!string || !(*string))
@@ -328,7 +285,6 @@
 		return (NULL);
 	}
 
-
 	/* Get rid of any spaces at the beginning */
 
 	if (*string == ' ')
@@ -353,12 +309,10 @@
 		string++;
 	}
 
-
 	if (!(*string))
 	{
 		*next = NULL;
 	}
-
 	else
 	{
 		*string = 0;
@@ -392,11 +346,11 @@
 	NATIVE_CHAR             *this;
 
 
-	STRCPY (acpi_gbl_db_parsed_buf, input_buffer);
-	STRUPR (acpi_gbl_db_parsed_buf);
+	ACPI_STRCPY (acpi_gbl_db_parsed_buf, input_buffer);
+	ACPI_STRUPR (acpi_gbl_db_parsed_buf);
 
 	this = acpi_gbl_db_parsed_buf;
-	for (i = 0; i < DB_MAX_ARGS; i++)
+	for (i = 0; i < ACPI_DEBUGGER_MAX_ARGS; i++)
 	{
 		acpi_gbl_db_args[i] = acpi_db_get_next_token (this, &next);
 		if (!acpi_gbl_db_args[i])
@@ -407,12 +361,11 @@
 		this = next;
 	}
 
-
 	/* Uppercase the actual command */
 
 	if (acpi_gbl_db_args[0])
 	{
-		STRUPR (acpi_gbl_db_args[0]);
+		ACPI_STRUPR (acpi_gbl_db_args[0]);
 	}
 
 	count = i;
@@ -451,7 +404,8 @@
 
 	for (i = CMD_FIRST_VALID; acpi_gbl_db_commands[i].name; i++)
 	{
-		if (STRSTR (acpi_gbl_db_commands[i].name, user_command) == acpi_gbl_db_commands[i].name)
+		if (ACPI_STRSTR (acpi_gbl_db_commands[i].name, user_command) ==
+				   acpi_gbl_db_commands[i].name)
 		{
 			return (i);
 		}
@@ -601,7 +555,6 @@
 			status = AE_CTRL_TRUE;
 		}
 		return (status);
-		break;
 
 	case CMD_HISTORY_LAST:
 		command_line = acpi_db_get_from_history (NULL);
@@ -625,9 +578,6 @@
 		if (op)
 		{
 			acpi_gbl_cm_single_step = TRUE;
-
-/* TBD: Must get current walk state */
-			/* Acpi_gbl_Method_breakpoint = 0; */
 			return (AE_OK);
 		}
 		break;
@@ -641,13 +591,13 @@
 		else if (param_count == 2)
 		{
 			temp = acpi_gbl_db_console_debug_level;
-			acpi_gbl_db_console_debug_level = STRTOUL (acpi_gbl_db_args[1], NULL, 16);
+			acpi_gbl_db_console_debug_level = ACPI_STRTOUL (acpi_gbl_db_args[1], NULL, 16);
 			acpi_os_printf ("Debug Level for console output was %8.8lX, now %8.8lX\n", temp, acpi_gbl_db_console_debug_level);
 		}
 		else
 		{
 			temp = acpi_gbl_db_debug_level;
-			acpi_gbl_db_debug_level = STRTOUL (acpi_gbl_db_args[1], NULL, 16);
+			acpi_gbl_db_debug_level = ACPI_STRTOUL (acpi_gbl_db_args[1], NULL, 16);
 			acpi_os_printf ("Debug Level for file output was %8.8lX, now %8.8lX\n", temp, acpi_gbl_db_debug_level);
 		}
 		break;
@@ -681,12 +631,12 @@
 		break;
 
 	case CMD_NOTIFY:
-		temp = STRTOUL (acpi_gbl_db_args[2], NULL, 0);
+		temp = ACPI_STRTOUL (acpi_gbl_db_args[2], NULL, 0);
 		acpi_db_send_notify (acpi_gbl_db_args[1], temp);
 		break;
 
 	case CMD_OBJECT:
-		acpi_db_display_objects (STRUPR (acpi_gbl_db_args[1]), acpi_gbl_db_args[2]);
+		acpi_db_display_objects (ACPI_STRUPR (acpi_gbl_db_args[1]), acpi_gbl_db_args[2]);
 		break;
 
 	case CMD_OPEN:
@@ -723,14 +673,13 @@
 
 	case CMD_STOP:
 		return (AE_AML_ERROR);
-		break;
 
 	case CMD_TABLES:
 		acpi_db_display_table_info (acpi_gbl_db_args[1]);
 		break;
 
 	case CMD_TERMINATE:
-		acpi_db_set_output_destination (DB_REDIRECTABLE_OUTPUT);
+		acpi_db_set_output_destination (ACPI_DB_REDIRECTABLE_OUTPUT);
 		acpi_ut_subsystem_shutdown ();
 
 		/* TBD: [Restructure] Need some way to re-initialize without re-creating the semaphores! */
@@ -798,11 +747,12 @@
  *
  ******************************************************************************/
 
-void
+void ACPI_SYSTEM_XFACE
 acpi_db_execute_thread (
 	void                    *context)
 {
 	acpi_status             status = AE_OK;
+	acpi_status             Mstatus;
 
 
 	while (status != AE_CTRL_TERMINATE)
@@ -810,9 +760,19 @@
 		acpi_gbl_method_executing = FALSE;
 		acpi_gbl_step_to_next_call = FALSE;
 
-		acpi_ut_acquire_mutex (ACPI_MTX_DEBUG_CMD_READY);
+		Mstatus = acpi_ut_acquire_mutex (ACPI_MTX_DEBUG_CMD_READY);
+		if (ACPI_FAILURE (Mstatus))
+		{
+			return;
+		}
+
 		status = acpi_db_command_dispatch (acpi_gbl_db_line_buf, NULL, NULL);
-		acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_COMPLETE);
+
+		Mstatus = acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_COMPLETE);
+		if (ACPI_FAILURE (Mstatus))
+		{
+			return;
+		}
 	}
 }
 
@@ -834,7 +794,7 @@
 acpi_db_single_thread (
 	void)
 {
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 
 
 	acpi_gbl_method_executing = FALSE;
@@ -872,17 +832,17 @@
 	{
 		/* Force output to console until a command is entered */
 
-		acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+		acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 
 		/* Different prompt if method is executing */
 
 		if (!acpi_gbl_method_executing)
 		{
-			acpi_os_printf ("%1c ", DB_COMMAND_PROMPT);
+			acpi_os_printf ("%1c ", ACPI_DEBUGGER_COMMAND_PROMPT);
 		}
 		else
 		{
-			acpi_os_printf ("%1c ", DB_EXECUTE_PROMPT);
+			acpi_os_printf ("%1c ", ACPI_DEBUGGER_EXECUTE_PROMPT);
 		}
 
 		/* Get the user input line */
@@ -898,10 +858,18 @@
 			 * Signal the debug thread that we have a command to execute,
 			 * and wait for the command to complete.
 			 */
-			acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_READY);
-			acpi_ut_acquire_mutex (ACPI_MTX_DEBUG_CMD_COMPLETE);
+			status = acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_READY);
+			if (ACPI_FAILURE (status))
+			{
+				return (status);
+			}
+
+			status = acpi_ut_acquire_mutex (ACPI_MTX_DEBUG_CMD_COMPLETE);
+			if (ACPI_FAILURE (status))
+			{
+				return (status);
+			}
 		}
-
 		else
 		{
 			/* Just call to the command line interpreter */
@@ -909,7 +877,6 @@
 			acpi_db_single_thread ();
 		}
 	}
-
 
 	/*
 	 * Only this thread (the original thread) should actually terminate the subsystem,
diff -Nru a/drivers/acpi/debugger/dbstats.c b/drivers/acpi/debugger/dbstats.c
--- a/drivers/acpi/debugger/dbstats.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/debugger/dbstats.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbstats - Generation and display of ACPI table statistics
- *              $Revision: 47 $
+ *              $Revision: 55 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbstats")
+	 ACPI_MODULE_NAME    ("dbstats")
 
 /*
  * Statistics subcommands
@@ -67,9 +67,8 @@
  * RETURN:      None
  *
  * DESCRIPTION: Add this object to the global counts, by object type.
- *              Recursively handles subobjects and packages.
- *
- *              [TBD] Restructure - remove recursion.
+ *              Limited recursion handles subobjects and packages, and this
+ *              is probably acceptable within the AML debugger only.
  *
  ******************************************************************************/
 
@@ -77,7 +76,6 @@
 acpi_db_enumerate_object (
 	acpi_operand_object     *obj_desc)
 {
-	u32                     type;
 	u32                     i;
 
 
@@ -91,22 +89,21 @@
 
 	acpi_gbl_num_objects++;
 
-	type = obj_desc->common.type;
-	if (type > INTERNAL_TYPE_NODE_MAX)
+	if (obj_desc->common.type > INTERNAL_TYPE_NODE_MAX)
 	{
 		acpi_gbl_obj_type_count_misc++;
 	}
 	else
 	{
-		acpi_gbl_obj_type_count [type]++;
+		acpi_gbl_obj_type_count [obj_desc->common.type]++;
 	}
 
 	/* Count the sub-objects */
 
-	switch (type)
+	switch (obj_desc->common.type)
 	{
 	case ACPI_TYPE_PACKAGE:
-		for (i = 0; i< obj_desc->package.count; i++)
+		for (i = 0; i < obj_desc->package.count; i++)
 		{
 			acpi_db_enumerate_object (obj_desc->package.elements[i]);
 		}
@@ -118,7 +115,15 @@
 		acpi_db_enumerate_object (obj_desc->device.addr_handler);
 		break;
 
+	case ACPI_TYPE_BUFFER_FIELD:
+		if (acpi_ns_get_secondary_object (obj_desc))
+		{
+			acpi_gbl_obj_type_count [ACPI_TYPE_BUFFER_FIELD]++;
+		}
+		break;
+
 	case ACPI_TYPE_REGION:
+		acpi_gbl_obj_type_count [INTERNAL_TYPE_REGION_FIELD ]++;
 		acpi_db_enumerate_object (obj_desc->region.addr_handler);
 		break;
 
@@ -172,7 +177,7 @@
 	acpi_gbl_num_nodes++;
 
 	node = (acpi_namespace_node *) obj_handle;
-	obj_desc = ((acpi_namespace_node *) obj_handle)->object;
+	obj_desc = acpi_ns_get_attached_object (node);
 
 	acpi_db_enumerate_object (obj_desc);
 
@@ -271,8 +276,10 @@
 {
 	u32                     i;
 	u32                     type;
-	u32                     outstanding;
 	u32                     size;
+#ifdef ACPI_DBG_TRACK_ALLOCATIONS
+	u32                     outstanding;
+#endif
 
 
 	if (!acpi_gbl_DSDT)
@@ -286,7 +293,7 @@
 		return (AE_OK);
 	}
 
-	STRUPR (type_arg);
+	ACPI_STRUPR (type_arg);
 	type = acpi_db_match_argument (type_arg, acpi_db_stat_types);
 	if (type == (u32) -1)
 	{
@@ -368,11 +375,11 @@
 
 			if (acpi_gbl_memory_lists[i].object_size)
 			{
-				size = ROUND_UP_TO_1K (outstanding * acpi_gbl_memory_lists[i].object_size);
+				size = ACPI_ROUND_UP_TO_1K (outstanding * acpi_gbl_memory_lists[i].object_size);
 			}
 			else
 			{
-				size = ROUND_UP_TO_1K (acpi_gbl_memory_lists[i].current_total_size);
+				size = ACPI_ROUND_UP_TO_1K (acpi_gbl_memory_lists[i].current_total_size);
 			}
 
 			acpi_os_printf ("  Mem:   [Alloc Free Outstanding Size]  % 7d % 7d % 7d % 7d Kb\n",
@@ -425,6 +432,7 @@
 		acpi_os_printf ("Notify_handler %3d\n", sizeof (ACPI_OBJECT_NOTIFY_HANDLER));
 		acpi_os_printf ("Addr_handler   %3d\n", sizeof (ACPI_OBJECT_ADDR_HANDLER));
 		acpi_os_printf ("Extra          %3d\n", sizeof (ACPI_OBJECT_EXTRA));
+		acpi_os_printf ("Data           %3d\n", sizeof (ACPI_OBJECT_DATA));
 
 		acpi_os_printf ("\n");
 
diff -Nru a/drivers/acpi/debugger/dbutils.c b/drivers/acpi/debugger/dbutils.c
--- a/drivers/acpi/debugger/dbutils.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/debugger/dbutils.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbutils - AML debugger utilities
- *              $Revision: 45 $
+ *              $Revision: 51 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -38,7 +38,7 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbutils")
+	 ACPI_MODULE_NAME    ("dbutils")
 
 
 /*******************************************************************************
@@ -61,10 +61,8 @@
 
 	acpi_gbl_db_output_flags = (u8) output_flags;
 
-	if (output_flags & DB_REDIRECTABLE_OUTPUT) {
-		if (acpi_gbl_db_output_to_file) {
-			acpi_dbg_level = acpi_gbl_db_debug_level;
-		}
+	if ((output_flags & ACPI_DB_REDIRECTABLE_OUTPUT) && acpi_gbl_db_output_to_file) {
+		acpi_dbg_level = acpi_gbl_db_debug_level;
 	}
 	else {
 		acpi_dbg_level = acpi_gbl_db_console_debug_level;
@@ -92,7 +90,7 @@
 	acpi_os_printf ("\n_location %X:\n", address);
 
 	acpi_dbg_level |= ACPI_LV_TABLES;
-	acpi_ut_dump_buffer ((u8 *) address, 64, DB_BYTE_DISPLAY, ACPI_UINT32_MAX);
+	acpi_ut_dump_buffer (ACPI_TO_POINTER (address), 64, DB_BYTE_DISPLAY, ACPI_UINT32_MAX);
 }
 
 
@@ -135,8 +133,9 @@
 
 	case ACPI_TYPE_INTEGER:
 
-		acpi_os_printf ("[Integer] = %8.8X%8.8X\n", HIDWORD (obj_desc->integer.value),
-				 LODWORD (obj_desc->integer.value));
+		acpi_os_printf ("[Integer] = %8.8X%8.8X\n",
+				 ACPI_HIDWORD (obj_desc->integer.value),
+				 ACPI_LODWORD (obj_desc->integer.value));
 		break;
 
 
@@ -215,7 +214,7 @@
 		return;
 	}
 
-	STRUPR (name);
+	ACPI_STRUPR (name);
 
 	/* Convert a leading forward slash to a backslash */
 
@@ -268,7 +267,7 @@
 	acpi_walk_state         *walk_state;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("Pass two parse ....\n");
@@ -339,6 +338,9 @@
  *
  * DESCRIPTION: Lookup a name in the ACPI namespace
  *
+ * Note: Currently begins search from the root.  Could be enhanced to use
+ * the current prefix (scope) node as the search beginning point.
+ *
  ******************************************************************************/
 
 acpi_namespace_node *
@@ -360,21 +362,17 @@
 		return (NULL);
 	}
 
-	/* Lookup the name */
-
-	/* TBD: [Investigate] what scope do we use? */
-	/* Use the root scope for the start of the search */
-
-	status = acpi_ns_lookup (NULL, internal_path, ACPI_TYPE_ANY, IMODE_EXECUTE,
-			   NS_NO_UPSEARCH | NS_DONT_OPEN_SCOPE, NULL, &node);
-
+	/*
+	 * Lookup the name.
+	 * (Uses root node as the search starting point)
+	 */
+	status = acpi_ns_lookup (NULL, internal_path, ACPI_TYPE_ANY, ACPI_IMODE_EXECUTE,
+			   ACPI_NS_NO_UPSEARCH | ACPI_NS_DONT_OPEN_SCOPE, NULL, &node);
 	if (ACPI_FAILURE (status)) {
 		acpi_os_printf ("Could not locate name: %s %s\n", name, acpi_format_exception (status));
 	}
 
-
 	ACPI_MEM_FREE (internal_path);
-
 	return (node);
 }
 
diff -Nru a/drivers/acpi/debugger/dbxface.c b/drivers/acpi/debugger/dbxface.c
--- a/drivers/acpi/debugger/dbxface.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/debugger/dbxface.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dbxface - AML Debugger external interfaces
- *              $Revision: 45 $
+ *              $Revision: 55 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -37,7 +37,7 @@
 #ifdef ENABLE_DEBUGGER
 
 #define _COMPONENT          ACPI_DEBUGGER
-	 MODULE_NAME         ("dbxface")
+	 ACPI_MODULE_NAME    ("dbxface")
 
 
 /*******************************************************************************
@@ -64,25 +64,33 @@
 	acpi_status             status = AE_OK;
 	u32                     original_debug_level;
 	acpi_parse_object       *display_op;
+	acpi_parse_object       *parent_op;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
-	/* Is there a breakpoint set? */
+	/* Check for single-step breakpoint */
 
-	if (walk_state->method_breakpoint) {
+	if (walk_state->method_breakpoint && (walk_state->method_breakpoint <= op->aml_offset)) {
 		/* Check if the breakpoint has been reached or passed */
+		/* Hit the breakpoint, resume single step, reset breakpoint */
 
-		if (walk_state->method_breakpoint <= op->aml_offset) {
-			/* Hit the breakpoint, resume single step, reset breakpoint */
+		acpi_os_printf ("***Break*** at AML offset %X\n", op->aml_offset);
+		acpi_gbl_cm_single_step = TRUE;
+		acpi_gbl_step_to_next_call = FALSE;
+		walk_state->method_breakpoint = 0;
+	}
 
-			acpi_os_printf ("***Break*** at AML offset %X\n", op->aml_offset);
-			acpi_gbl_cm_single_step = TRUE;
-			acpi_gbl_step_to_next_call = FALSE;
-			walk_state->method_breakpoint = 0;
-		}
+	/* Check for user breakpoint (Must be on exact Aml offset) */
+
+	else if (walk_state->user_breakpoint && (walk_state->user_breakpoint == op->aml_offset)) {
+		acpi_os_printf ("***User_breakpoint*** at AML offset %X\n", op->aml_offset);
+		acpi_gbl_cm_single_step = TRUE;
+		acpi_gbl_step_to_next_call = FALSE;
+		walk_state->method_breakpoint = 0;
 	}
 
+
 	/*
 	 * Check if this is an opcode that we are interested in --
 	 * namely, opcodes that have arguments
@@ -95,7 +103,6 @@
 	case AML_CLASS_UNKNOWN:
 	case AML_CLASS_ARGUMENT:    /* constants, literals, etc.  do nothing */
 		return (AE_OK);
-		break;
 	}
 
 	/*
@@ -121,10 +128,36 @@
 
 
 		display_op = op;
-		if (op->parent) {
-			if ((op->parent->opcode == AML_IF_OP) ||
-				(op->parent->opcode == AML_WHILE_OP)) {
-				display_op = op->parent;
+		parent_op = op->parent;
+		if (parent_op) {
+			if ((walk_state->control_state) &&
+				(walk_state->control_state->common.state == ACPI_CONTROL_PREDICATE_EXECUTING)) {
+				/*
+				 * We are executing the predicate of an IF or WHILE statement
+				 * Search upwards for the containing IF or WHILE so that the
+				 * entire predicate can be displayed.
+				 */
+				while (parent_op) {
+					if ((parent_op->opcode == AML_IF_OP) ||
+						(parent_op->opcode == AML_WHILE_OP)) {
+						display_op = parent_op;
+						break;
+					}
+					parent_op = parent_op->parent;
+				}
+			}
+			else {
+				while (parent_op) {
+					if ((parent_op->opcode == AML_IF_OP)    ||
+						(parent_op->opcode == AML_ELSE_OP)  ||
+						(parent_op->opcode == AML_SCOPE_OP) ||
+						(parent_op->opcode == AML_METHOD_OP) ||
+						(parent_op->opcode == AML_WHILE_OP)) {
+						break;
+					}
+					display_op = parent_op;
+					parent_op = parent_op->parent;
+				}
 			}
 		}
 
@@ -135,15 +168,15 @@
 		if ((op->opcode == AML_IF_OP) ||
 			(op->opcode == AML_WHILE_OP)) {
 			if (walk_state->control_state->common.value) {
-				acpi_os_printf ("Predicate was TRUE, executed block\n");
+				acpi_os_printf ("Predicate = [True], IF block was executed\n");
 			}
 			else {
-				acpi_os_printf ("Predicate is FALSE, skipping block\n");
+				acpi_os_printf ("Predicate = [False], Skipping IF block\n");
 			}
 		}
 
 		else if (op->opcode == AML_ELSE_OP) {
-			/* TBD */
+			acpi_os_printf ("Predicate = [False], ELSE block was executed\n");
 		}
 
 		/* Restore everything */
@@ -159,7 +192,6 @@
 		return (AE_OK);
 	}
 
-
 	/*
 	 * If we are executing a step-to-call command,
 	 * Check if this is a method call.
@@ -176,7 +208,6 @@
 		acpi_gbl_step_to_next_call = FALSE;
 	}
 
-
 	/*
 	 * If the next opcode is a method call, we will "step over" it
 	 * by default.
@@ -184,11 +215,9 @@
 	if (op->opcode == AML_INT_METHODCALL_OP) {
 		acpi_gbl_cm_single_step = FALSE; /* No more single step while executing called method */
 
-		/* Set the breakpoint on the call, it will stop execution as soon as we return */
+		/* Set the breakpoint on/before the call, it will stop execution as soon as we return */
 
-		/* TBD: [Future] don't kill the user breakpoint! */
-
-		walk_state->method_breakpoint = /* Op->Aml_offset + */ 1; /* Must be non-zero! */
+		walk_state->method_breakpoint = 1; /* Must be non-zero! */
 	}
 
 
@@ -204,8 +233,14 @@
 		if (acpi_gbl_debugger_configuration == DEBUGGER_MULTI_THREADED) {
 			/* Handshake with the front-end that gets user command lines */
 
-			acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_COMPLETE);
-			acpi_ut_acquire_mutex (ACPI_MTX_DEBUG_CMD_READY);
+			status = acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_COMPLETE);
+			if (ACPI_FAILURE (status)) {
+				return (status);
+			}
+			status = acpi_ut_acquire_mutex (ACPI_MTX_DEBUG_CMD_READY);
+			if (ACPI_FAILURE (status)) {
+				return (status);
+			}
 		}
 
 		else {
@@ -213,15 +248,15 @@
 
 			/* Force output to console until a command is entered */
 
-			acpi_db_set_output_destination (DB_CONSOLE_OUTPUT);
+			acpi_db_set_output_destination (ACPI_DB_CONSOLE_OUTPUT);
 
 			/* Different prompt if method is executing */
 
 			if (!acpi_gbl_method_executing) {
-				acpi_os_printf ("%1c ", DB_COMMAND_PROMPT);
+				acpi_os_printf ("%1c ", ACPI_DEBUGGER_COMMAND_PROMPT);
 			}
 			else {
-				acpi_os_printf ("%1c ", DB_EXECUTE_PROMPT);
+				acpi_os_printf ("%1c ", ACPI_DEBUGGER_EXECUTE_PROMPT);
 			}
 
 			/* Get the user input line */
@@ -256,16 +291,33 @@
 acpi_db_initialize (void)
 {
 
-
 	/* Init globals */
 
-	acpi_gbl_db_buffer = acpi_os_callocate (ACPI_DEBUG_BUFFER_SIZE);
+	acpi_gbl_db_buffer          = NULL;
+	acpi_gbl_db_filename        = NULL;
+	acpi_gbl_db_output_to_file  = FALSE;
+
+	acpi_gbl_db_debug_level     = ACPI_LV_VERBOSITY2;
+	acpi_gbl_db_console_debug_level = NORMAL_DEFAULT | ACPI_LV_TABLES;
+	acpi_gbl_db_output_flags    = ACPI_DB_CONSOLE_OUTPUT;
+
+	acpi_gbl_db_opt_tables      = FALSE;
+	acpi_gbl_db_opt_disasm      = FALSE;
+	acpi_gbl_db_opt_stats       = FALSE;
+	acpi_gbl_db_opt_verbose     = TRUE;
+	acpi_gbl_db_opt_ini_methods = TRUE;
+
+	acpi_gbl_db_buffer = acpi_os_allocate (ACPI_DEBUG_BUFFER_SIZE);
+	if (!acpi_gbl_db_buffer) {
+		return 0;
+	}
+	ACPI_MEMSET (acpi_gbl_db_buffer, 0, ACPI_DEBUG_BUFFER_SIZE);
 
 	/* Initial scope is the root */
 
 	acpi_gbl_db_scope_buf [0] = '\\';
 	acpi_gbl_db_scope_buf [1] = 0;
-
+	acpi_gbl_db_scope_node = acpi_gbl_root_node;
 
 	/*
 	 * If configured for multi-thread support, the debug executor runs in
diff -Nru a/drivers/acpi/dispatcher/Makefile b/drivers/acpi/dispatcher/Makefile
--- a/drivers/acpi/dispatcher/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/dispatcher/Makefile	Fri Mar 15 17:51:02 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/dispatcher/dsfield.c b/drivers/acpi/dispatcher/dsfield.c
--- a/drivers/acpi/dispatcher/dsfield.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/dispatcher/dsfield.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dsfield - Dispatcher field routines
- *              $Revision: 46 $
+ *              $Revision: 62 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dsfield")
+	 ACPI_MODULE_NAME    ("dsfield")
 
 
 /*******************************************************************************
@@ -65,9 +65,11 @@
 	acpi_namespace_node     *node;
 	acpi_status             status;
 	acpi_operand_object     *obj_desc;
+	acpi_operand_object     *second_desc = NULL;
+	u32                     flags;
 
 
-	FUNCTION_TRACE ("Ds_create_buffer_field");
+	ACPI_FUNCTION_TRACE ("Ds_create_buffer_field");
 
 
 	/* Get the Name_string argument */
@@ -86,12 +88,23 @@
 	}
 
 	/*
+	 * During the load phase, we want to enter the name of the field into
+	 * the namespace.  During the execute phase (when we evaluate the size
+	 * operand), we want to lookup the name
+	 */
+	if (walk_state->parse_flags & ACPI_PARSE_EXECUTE) {
+		flags = ACPI_NS_NO_UPSEARCH | ACPI_NS_DONT_OPEN_SCOPE;
+	}
+	else {
+		flags = ACPI_NS_NO_UPSEARCH | ACPI_NS_DONT_OPEN_SCOPE | ACPI_NS_ERROR_IF_FOUND;
+	}
+
+	/*
 	 * Enter the Name_string into the namespace
 	 */
 	status = acpi_ns_lookup (walk_state->scope_info, arg->value.string,
-			 INTERNAL_TYPE_DEF_ANY, IMODE_LOAD_PASS1,
-			 NS_NO_UPSEARCH | NS_DONT_OPEN_SCOPE,
-			 walk_state, &(node));
+			 INTERNAL_TYPE_DEF_ANY, ACPI_IMODE_LOAD_PASS1,
+			 flags, walk_state, &(node));
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
@@ -107,7 +120,8 @@
 	 * we need to create the field object.  Otherwise, this was a lookup of an
 	 * existing node and we don't want to create the field object again.
 	 */
-	if (node->object) {
+	obj_desc = acpi_ns_get_attached_object (node);
+	if (obj_desc) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
@@ -125,27 +139,21 @@
 	}
 
 	/*
-	 * Allocate a method object for this field unit
-	 */
-	obj_desc->buffer_field.extra = acpi_ut_create_internal_object (
-			   INTERNAL_TYPE_EXTRA);
-	if (!obj_desc->buffer_field.extra) {
-		status = AE_NO_MEMORY;
-		goto cleanup;
-	}
-
-	/*
 	 * Remember location in AML stream of the field unit
 	 * opcode and operands -- since the buffer and index
 	 * operands must be evaluated.
 	 */
-	obj_desc->buffer_field.extra->extra.aml_start = ((acpi_parse2_object *) op)->data;
-	obj_desc->buffer_field.extra->extra.aml_length = ((acpi_parse2_object *) op)->length;
+	second_desc                 = obj_desc->common.next_object;
+	second_desc->extra.aml_start = ((acpi_parse2_object *) op)->data;
+	second_desc->extra.aml_length = ((acpi_parse2_object *) op)->length;
 	obj_desc->buffer_field.node = node;
 
-	/* Attach constructed field descriptor to parent node */
+	/* Attach constructed field descriptors to parent node */
 
 	status = acpi_ns_attach_object (node, obj_desc, ACPI_TYPE_BUFFER_FIELD);
+	if (ACPI_FAILURE (status)) {
+		goto cleanup;
+	}
 
 
 cleanup:
@@ -181,7 +189,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_U32 ("Ds_get_field_names", info);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_get_field_names", info);
 
 
 	/* First field starts at bit zero */
@@ -200,6 +208,12 @@
 		switch (arg->opcode) {
 		case AML_INT_RESERVEDFIELD_OP:
 
+			if (((acpi_integer) info->field_bit_position + arg->value.size) >
+				ACPI_UINT32_MAX) {
+				ACPI_REPORT_ERROR (("Bit offset within field too large (> 0xFFFFFFFF)\n"));
+				return_ACPI_STATUS (AE_SUPPORT);
+			}
+
 			info->field_bit_position += arg->value.size;
 			break;
 
@@ -207,38 +221,55 @@
 		case AML_INT_ACCESSFIELD_OP:
 
 			/*
-			 * Get a new Access_type and Access_attribute for all
-			 * entries (until end or another Access_as keyword)
+			 * Get a new Access_type and Access_attribute -- to be used for all
+			 * field units that follow, until field end or another Access_as keyword.
+			 *
+			 * In Field_flags, preserve the flag bits other than the ACCESS_TYPE bits
 			 */
-			info->field_flags = (u8) ((info->field_flags & FIELD_ACCESS_TYPE_MASK) ||
-					  ((u8) (arg->value.integer >> 8)));
+			info->field_flags = (u8) ((info->field_flags & ~(AML_FIELD_ACCESS_TYPE_MASK)) |
+					  ((u8) (arg->value.integer32 >> 8)));
+
+			info->attribute = (u8) (arg->value.integer32);
 			break;
 
 
 		case AML_INT_NAMEDFIELD_OP:
 
-			/* Enter a new field name into the namespace */
+			/* Lookup the name */
 
 			status = acpi_ns_lookup (walk_state->scope_info,
 					  (NATIVE_CHAR *) &((acpi_parse2_object *)arg)->name,
-					  info->field_type, IMODE_LOAD_PASS1,
-					  NS_NO_UPSEARCH | NS_DONT_OPEN_SCOPE,
-					  NULL, &info->field_node);
+					  info->field_type, ACPI_IMODE_EXECUTE, ACPI_NS_DONT_OPEN_SCOPE,
+					  walk_state, &info->field_node);
 			if (ACPI_FAILURE (status)) {
-				return_ACPI_STATUS (status);
-			}
+				if (status != AE_ALREADY_EXISTS) {
+					return_ACPI_STATUS (status);
+				}
 
-			/* Create and initialize an object for the new Field Node */
-
-			info->field_bit_length = arg->value.size;
-
-			status = acpi_ex_prep_field_value (info);
-			if (ACPI_FAILURE (status)) {
-				return_ACPI_STATUS (status);
+				ACPI_REPORT_ERROR (("Field name [%4.4s] already exists in current scope\n",
+						  &((acpi_parse2_object *)arg)->name));
+			}
+			else {
+				arg->node = info->field_node;
+				info->field_bit_length = arg->value.size;
+
+				/* Create and initialize an object for the new Field Node */
+
+				status = acpi_ex_prep_field_value (info);
+				if (ACPI_FAILURE (status)) {
+					return_ACPI_STATUS (status);
+				}
 			}
 
 			/* Keep track of bit position for the next field */
 
+			if (((acpi_integer) info->field_bit_position + arg->value.size) >
+				ACPI_UINT32_MAX) {
+				ACPI_REPORT_ERROR (("Field [%4.4s] bit offset too large (> 0xFFFFFFFF)\n",
+					&info->field_node->name));
+				return_ACPI_STATUS (AE_SUPPORT);
+			}
+
 			info->field_bit_position += info->field_bit_length;
 			break;
 
@@ -248,7 +279,6 @@
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid opcode in field list: %X\n",
 				arg->opcode));
 			return_ACPI_STATUS (AE_AML_ERROR);
-			break;
 		}
 
 		arg = arg->next;
@@ -283,7 +313,7 @@
 	ACPI_CREATE_FIELD_INFO  info;
 
 
-	FUNCTION_TRACE_PTR ("Ds_create_field", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_create_field", op);
 
 
 	/* First arg is the name of the parent Op_region (must already exist) */
@@ -291,8 +321,8 @@
 	arg = op->value.arg;
 	if (!region_node) {
 		status = acpi_ns_lookup (walk_state->scope_info, arg->value.name,
-				  ACPI_TYPE_REGION, IMODE_EXECUTE,
-				  NS_SEARCH_PARENT, walk_state, &region_node);
+				  ACPI_TYPE_REGION, ACPI_IMODE_EXECUTE,
+				  ACPI_NS_SEARCH_PARENT, walk_state, &region_node);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
@@ -302,6 +332,7 @@
 
 	arg = arg->next;
 	info.field_flags = arg->value.integer8;
+	info.attribute = 0;
 
 	/* Each remaining arg is a Named Field */
 
@@ -316,6 +347,85 @@
 
 /*******************************************************************************
  *
+ * FUNCTION:    Acpi_ds_init_field_objects
+ *
+ * PARAMETERS:  Op              - Op containing the Field definition and args
+ *  `           Walk_state      - Current method state
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: For each "Field Unit" name in the argument list that is
+ *              part of the field declaration, enter the name into the
+ *              namespace.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ds_init_field_objects (
+	acpi_parse_object       *op,
+	acpi_walk_state         *walk_state)
+{
+	acpi_status             status = AE_AML_ERROR;
+	acpi_parse_object       *arg = NULL;
+	acpi_namespace_node     *node;
+	u8                      type = 0;
+
+
+	ACPI_FUNCTION_TRACE_PTR ("Ds_init_field_objects", op);
+
+
+	switch (walk_state->opcode) {
+	case AML_FIELD_OP:
+		arg = acpi_ps_get_arg (op, 2);
+		type = INTERNAL_TYPE_REGION_FIELD;
+		break;
+
+	case AML_BANK_FIELD_OP:
+		arg = acpi_ps_get_arg (op, 4);
+		type = INTERNAL_TYPE_BANK_FIELD;
+		break;
+
+	case AML_INDEX_FIELD_OP:
+		arg = acpi_ps_get_arg (op, 3);
+		type = INTERNAL_TYPE_INDEX_FIELD;
+		break;
+	}
+
+	/*
+	 * Walk the list of entries in the Field_list
+	 */
+	while (arg) {
+		/* Ignore OFFSET and ACCESSAS terms here */
+
+		if (arg->opcode == AML_INT_NAMEDFIELD_OP) {
+			status = acpi_ns_lookup (walk_state->scope_info,
+					  (NATIVE_CHAR *) &((acpi_parse2_object *)arg)->name,
+					  type, ACPI_IMODE_LOAD_PASS1,
+					  ACPI_NS_NO_UPSEARCH | ACPI_NS_DONT_OPEN_SCOPE | ACPI_NS_ERROR_IF_FOUND,
+					  walk_state, &node);
+			if (ACPI_FAILURE (status)) {
+				if (status != AE_ALREADY_EXISTS) {
+					return_ACPI_STATUS (status);
+				}
+
+				ACPI_REPORT_ERROR (("Field name [%4.4s] already exists in current scope\n",
+						  &((acpi_parse2_object *)arg)->name));
+			}
+
+			arg->node = node;
+		}
+
+		/* Move to next field in the list */
+
+		arg = arg->next;
+	}
+
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
  * FUNCTION:    Acpi_ds_create_bank_field
  *
  * PARAMETERS:  Op              - Op containing the Field definition and args
@@ -339,7 +449,7 @@
 	ACPI_CREATE_FIELD_INFO  info;
 
 
-	FUNCTION_TRACE_PTR ("Ds_create_bank_field", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_create_bank_field", op);
 
 
 	/* First arg is the name of the parent Op_region (must already exist) */
@@ -347,8 +457,8 @@
 	arg = op->value.arg;
 	if (!region_node) {
 		status = acpi_ns_lookup (walk_state->scope_info, arg->value.name,
-				  ACPI_TYPE_REGION, IMODE_EXECUTE,
-				  NS_SEARCH_PARENT, walk_state, &region_node);
+				  ACPI_TYPE_REGION, ACPI_IMODE_EXECUTE,
+				  ACPI_NS_SEARCH_PARENT, walk_state, &region_node);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
@@ -358,8 +468,8 @@
 
 	arg = arg->next;
 	status = acpi_ns_lookup (walk_state->scope_info, arg->value.string,
-			  INTERNAL_TYPE_BANK_FIELD_DEFN, IMODE_EXECUTE,
-			  NS_SEARCH_PARENT, walk_state, &info.register_node);
+			  INTERNAL_TYPE_BANK_FIELD_DEFN, ACPI_IMODE_EXECUTE,
+			  ACPI_NS_SEARCH_PARENT, walk_state, &info.register_node);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
@@ -410,15 +520,15 @@
 	ACPI_CREATE_FIELD_INFO  info;
 
 
-	FUNCTION_TRACE_PTR ("Ds_create_index_field", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_create_index_field", op);
 
 
 	/* First arg is the name of the Index register (must already exist) */
 
 	arg = op->value.arg;
 	status = acpi_ns_lookup (walk_state->scope_info, arg->value.string,
-			  ACPI_TYPE_ANY, IMODE_EXECUTE,
-			  NS_SEARCH_PARENT, walk_state, &info.register_node);
+			  ACPI_TYPE_ANY, ACPI_IMODE_EXECUTE,
+			  ACPI_NS_SEARCH_PARENT, walk_state, &info.register_node);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
@@ -427,8 +537,8 @@
 
 	arg = arg->next;
 	status = acpi_ns_lookup (walk_state->scope_info, arg->value.string,
-			  INTERNAL_TYPE_INDEX_FIELD_DEFN, IMODE_EXECUTE,
-			  NS_SEARCH_PARENT, walk_state, &info.data_register_node);
+			  INTERNAL_TYPE_INDEX_FIELD_DEFN, ACPI_IMODE_EXECUTE,
+			  ACPI_NS_SEARCH_PARENT, walk_state, &info.data_register_node);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
diff -Nru a/drivers/acpi/dispatcher/dsmethod.c b/drivers/acpi/dispatcher/dsmethod.c
--- a/drivers/acpi/dispatcher/dsmethod.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/dispatcher/dsmethod.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dsmethod - Parser/Interpreter interface - control method parsing
- *              $Revision: 69 $
+ *              $Revision: 79 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,7 +35,7 @@
 
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dsmethod")
+	 ACPI_MODULE_NAME    ("dsmethod")
 
 
 /*******************************************************************************
@@ -68,7 +68,7 @@
 	acpi_walk_state         *walk_state;
 
 
-	FUNCTION_TRACE_PTR ("Ds_parse_method", obj_handle);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_parse_method", obj_handle);
 
 
 	/* Parameter Validation */
@@ -78,13 +78,12 @@
 	}
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "**** Parsing [%4.4s] **** Named_obj=%p\n",
-		(char*)&((acpi_namespace_node *)obj_handle)->name, obj_handle));
-
+		(char *) &((acpi_namespace_node *) obj_handle)->name, obj_handle));
 
 	/* Extract the method object from the method Node */
 
 	node = (acpi_namespace_node *) obj_handle;
-	obj_desc = node->object;
+	obj_desc = acpi_ns_get_attached_object (node);
 	if (!obj_desc) {
 		return_ACPI_STATUS (AE_NULL_OBJECT);
 	}
@@ -115,9 +114,17 @@
 	acpi_ps_set_name (op, node->name);
 	op->node = node;
 
+	/*
+	 * Get a new Owner_id for objects created by this method. Namespace
+	 * objects (such as Operation Regions) can be created during the
+	 * first pass parse.
+	 */
+	owner_id = acpi_ut_allocate_owner_id (ACPI_OWNER_TYPE_METHOD);
+	obj_desc->method.owning_id = owner_id;
+
 	/* Create and initialize a new walk state */
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
+	walk_state = acpi_ds_create_walk_state (owner_id,
 			   NULL, NULL, NULL);
 	if (!walk_state) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
@@ -126,7 +133,7 @@
 	status = acpi_ds_init_aml_walk (walk_state, op, node, obj_desc->method.aml_start,
 			  obj_desc->method.aml_length, NULL, NULL, 1);
 	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
+		acpi_ds_delete_walk_state (walk_state);
 		return_ACPI_STATUS (status);
 	}
 
@@ -145,16 +152,10 @@
 		return_ACPI_STATUS (status);
 	}
 
-	/* Get a new Owner_id for objects created by this method */
-
-	owner_id = acpi_ut_allocate_owner_id (OWNER_TYPE_METHOD);
-	obj_desc->method.owning_id = owner_id;
-
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "**** [%4.4s] Parsed **** Named_obj=%p Op=%p\n",
-		(char*)&((acpi_namespace_node *)obj_handle)->name, obj_handle, op));
+		(char *) &((acpi_namespace_node *) obj_handle)->name, obj_handle, op));
 
 	acpi_ps_delete_parse_tree (op);
-
 	return_ACPI_STATUS (status);
 }
 
@@ -186,14 +187,13 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_PTR ("Ds_begin_method_execution", method_node);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_begin_method_execution", method_node);
 
 
 	if (!method_node) {
 		return_ACPI_STATUS (AE_NULL_ENTRY);
 	}
 
-
 	/*
 	 * If there is a concurrency limit on this method, we need to
 	 * obtain a unit from the method semaphore.
@@ -221,13 +221,11 @@
 				 WAIT_FOREVER);
 	}
 
-
 	/*
 	 * Increment the method parse tree thread count since it has been
 	 * reentered one more time (even if it is the same thread)
 	 */
 	obj_desc->method.thread_count++;
-
 	return_ACPI_STATUS (status);
 }
 
@@ -247,9 +245,9 @@
 
 acpi_status
 acpi_ds_call_control_method (
-	acpi_walk_list          *walk_list,
+	ACPI_THREAD_STATE       *thread,
 	acpi_walk_state         *this_walk_state,
-	acpi_parse_object       *op)  /* TBD: This operand is obsolete */
+	acpi_parse_object       *op)
 {
 	acpi_status             status;
 	acpi_namespace_node     *method_node;
@@ -258,7 +256,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE_PTR ("Ds_call_control_method", this_walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_call_control_method", this_walk_state);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Execute method %p, currentstate=%p\n",
 		this_walk_state->prev_op, this_walk_state));
@@ -284,14 +282,12 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/* 1) Parse: Create a new walk state for the preempting walk */
 
 	next_walk_state = acpi_ds_create_walk_state (obj_desc->method.owning_id,
 			  op, obj_desc, NULL);
 	if (!next_walk_state) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
-		goto cleanup;
 	}
 
 	/* Create and init a Root Node */
@@ -306,7 +302,7 @@
 			  obj_desc->method.aml_start, obj_desc->method.aml_length,
 			  NULL, NULL, 1);
 	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
+		acpi_ds_delete_walk_state (next_walk_state);
 		goto cleanup;
 	}
 
@@ -315,11 +311,10 @@
 	status = acpi_ps_parse_aml (next_walk_state);
 	acpi_ps_delete_parse_tree (op);
 
-
 	/* 2) Execute: Create a new state for the preempting walk */
 
 	next_walk_state = acpi_ds_create_walk_state (obj_desc->method.owning_id,
-			  NULL, obj_desc, walk_list);
+			  NULL, obj_desc, thread);
 	if (!next_walk_state) {
 		status = AE_NO_MEMORY;
 		goto cleanup;
@@ -390,7 +385,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ds_restart_control_method", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_restart_control_method", walk_state);
 
 
 	if (return_desc) {
@@ -405,7 +400,6 @@
 				return_ACPI_STATUS (status);
 			}
 		}
-
 		else {
 			/*
 			 * Delete the return value if it will not be used by the
@@ -413,7 +407,6 @@
 			 */
 			acpi_ut_remove_reference (return_desc);
 		}
-
 	}
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
@@ -446,12 +439,13 @@
 {
 	acpi_operand_object     *obj_desc;
 	acpi_namespace_node     *method_node;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ds_terminate_control_method", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_terminate_control_method", walk_state);
 
 
-	/* The method object should be stored in the walk state */
+	/* The current method object was saved in the walk state */
 
 	obj_desc = walk_state->method_desc;
 	if (!obj_desc) {
@@ -467,8 +461,10 @@
 	 * If this is the last thread executing the method,
 	 * we have additional cleanup to perform
 	 */
-	acpi_ut_acquire_mutex (ACPI_MTX_PARSER);
-
+	status = acpi_ut_acquire_mutex (ACPI_MTX_PARSER);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Signal completion of the execution of this method if necessary */
 
@@ -493,7 +489,11 @@
 		 * Delete any namespace entries created immediately underneath
 		 * the method
 		 */
-		acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+		status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
+
 		if (method_node->child) {
 			acpi_ns_delete_namespace_subtree (method_node);
 		}
@@ -503,11 +503,14 @@
 		 * the namespace
 		 */
 		acpi_ns_delete_namespace_by_owner (walk_state->method_desc->method.owning_id);
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
 	}
 
-	acpi_ut_release_mutex (ACPI_MTX_PARSER);
-	return_ACPI_STATUS (AE_OK);
+	status = acpi_ut_release_mutex (ACPI_MTX_PARSER);
+	return_ACPI_STATUS (status);
 }
 
 
diff -Nru a/drivers/acpi/dispatcher/dsmthdat.c b/drivers/acpi/dispatcher/dsmthdat.c
--- a/drivers/acpi/dispatcher/dsmthdat.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/dispatcher/dsmthdat.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dsmthdat - control method arguments and local variables
- *              $Revision: 49 $
+ *              $Revision: 58 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dsmthdat")
+	 ACPI_MODULE_NAME    ("dsmthdat")
 
 
 /*******************************************************************************
@@ -49,6 +49,12 @@
  *              This allows Ref_of and De_ref_of to work properly for these
  *              special data types.
  *
+ * NOTES:       Walk_state fields are initialized to zero by the
+ *              ACPI_MEM_CALLOCATE().
+ *
+ *              A pseudo-Namespace Node is assigned to each argument and local
+ *              so that Ref_of() can return a pointer to the Node.
+ *
  ******************************************************************************/
 
 acpi_status
@@ -58,37 +64,30 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE ("Ds_method_data_init");
+	ACPI_FUNCTION_TRACE ("Ds_method_data_init");
 
-	/*
-	 * Walk_state fields are initialized to zero by the
-	 * ACPI_MEM_CALLOCATE().
-	 *
-	 * An Node is assigned to each argument and local so
-	 * that Ref_of() can return a pointer to the Node.
-	 */
 
 	/* Init the method arguments */
 
 	for (i = 0; i < MTH_NUM_ARGS; i++) {
-		MOVE_UNALIGNED32_TO_32 (&walk_state->arguments[i].name,
+		ACPI_MOVE_UNALIGNED32_TO_32 (&walk_state->arguments[i].name,
 				 NAMEOF_ARG_NTE);
-		walk_state->arguments[i].name      |= (i << 24);
-		walk_state->arguments[i].data_type  = ACPI_DESC_TYPE_NAMED;
-		walk_state->arguments[i].type       = ACPI_TYPE_ANY;
-		walk_state->arguments[i].flags      = ANOBJ_END_OF_PEER_LIST | ANOBJ_METHOD_ARG;
+		walk_state->arguments[i].name     |= (i << 24);
+		walk_state->arguments[i].descriptor = ACPI_DESC_TYPE_NAMED;
+		walk_state->arguments[i].type      = ACPI_TYPE_ANY;
+		walk_state->arguments[i].flags     = ANOBJ_END_OF_PEER_LIST | ANOBJ_METHOD_ARG;
 	}
 
 	/* Init the method locals */
 
 	for (i = 0; i < MTH_NUM_LOCALS; i++) {
-		MOVE_UNALIGNED32_TO_32 (&walk_state->local_variables[i].name,
+		ACPI_MOVE_UNALIGNED32_TO_32 (&walk_state->local_variables[i].name,
 				 NAMEOF_LOCAL_NTE);
 
-		walk_state->local_variables[i].name  |= (i << 24);
-		walk_state->local_variables[i].data_type = ACPI_DESC_TYPE_NAMED;
-		walk_state->local_variables[i].type   = ACPI_TYPE_ANY;
-		walk_state->local_variables[i].flags  = ANOBJ_END_OF_PEER_LIST | ANOBJ_METHOD_LOCAL;
+		walk_state->local_variables[i].name    |= (i << 24);
+		walk_state->local_variables[i].descriptor = ACPI_DESC_TYPE_NAMED;
+		walk_state->local_variables[i].type     = ACPI_TYPE_ANY;
+		walk_state->local_variables[i].flags    = ANOBJ_END_OF_PEER_LIST | ANOBJ_METHOD_LOCAL;
 	}
 
 	return_ACPI_STATUS (AE_OK);
@@ -113,48 +112,34 @@
 	acpi_walk_state         *walk_state)
 {
 	u32                     index;
-	acpi_operand_object     *object;
-
 
-	FUNCTION_TRACE ("Ds_method_data_delete_all");
 
+	ACPI_FUNCTION_TRACE ("Ds_method_data_delete_all");
 
-	/* Delete the locals */
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting local variables in %p\n", walk_state));
+	/* Detach the locals */
 
 	for (index = 0; index < MTH_NUM_LOCALS; index++) {
-		object = walk_state->local_variables[index].object;
-		if (object) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Deleting Local%d=%p\n", index, object));
-
-			/* Remove first */
-
-			walk_state->local_variables[index].object = NULL;
+		if (walk_state->local_variables[index].object) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Deleting Local%d=%p\n",
+					index, walk_state->local_variables[index].object));
 
-			/* Was given a ref when stored */
+			/* Detach object (if present) and remove a reference */
 
-			acpi_ut_remove_reference (object);
+			acpi_ns_detach_object (&walk_state->local_variables[index]);
 	   }
 	}
 
-
-	/* Delete the arguments */
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting arguments in %p\n", walk_state));
+	/* Detach the arguments */
 
 	for (index = 0; index < MTH_NUM_ARGS; index++) {
-		object = walk_state->arguments[index].object;
-		if (object) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Deleting Arg%d=%p\n", index, object));
-
-			/* Remove first */
-
-			walk_state->arguments[index].object = NULL;
+		if (walk_state->arguments[index].object) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Deleting Arg%d=%p\n",
+					index, walk_state->arguments[index].object));
 
-			 /* Was given a ref when stored */
+			/* Detach object (if present) and remove a reference */
 
-			acpi_ut_remove_reference (object);
+			acpi_ns_detach_object (&walk_state->arguments[index]);
 		}
 	}
 
@@ -172,7 +157,9 @@
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Initialize arguments for a method
+ * DESCRIPTION: Initialize arguments for a method.  The parameter list is a list
+ *              of ACPI operand objects, either null terminated or whose length
+ *              is defined by Max_param_count.
  *
  ******************************************************************************/
 
@@ -183,11 +170,10 @@
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status;
-	u32                     mindex;
-	u32                     pindex;
+	u32                     index = 0;
 
 
-	FUNCTION_TRACE_PTR ("Ds_method_data_init_args", params);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_method_data_init_args", params);
 
 
 	if (!params) {
@@ -197,106 +183,90 @@
 
 	/* Copy passed parameters into the new method stack frame  */
 
-	for (pindex = mindex = 0;
-		(mindex < MTH_NUM_ARGS) && (pindex < max_param_count);
-		mindex++) {
-		if (params[pindex]) {
-			/*
-			 * A valid parameter.
-			 * Set the current method argument to the
-			 * Params[Pindex++] argument object descriptor
-			 */
-			status = acpi_ds_store_object_to_local (AML_ARG_OP, mindex,
-					  params[pindex], walk_state);
-			if (ACPI_FAILURE (status)) {
-				break;
-			}
-
-			pindex++;
+	while ((index < MTH_NUM_ARGS) && (index < max_param_count) && params[index]) {
+		/*
+		 * A valid parameter.
+		 * Store the argument in the method/walk descriptor
+		 */
+		status = acpi_ds_store_object_to_local (AML_ARG_OP, index, params[index],
+				 walk_state);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
 		}
 
-		else {
-			break;
-		}
+		index++;
 	}
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "%d args passed to method\n", pindex));
+	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "%d args passed to method\n", index));
 	return_ACPI_STATUS (AE_OK);
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ds_method_data_get_entry
+ * FUNCTION:    Acpi_ds_method_data_get_node
  *
  * PARAMETERS:  Opcode              - Either AML_LOCAL_OP or AML_ARG_OP
- *              Index               - Which local_var or argument to get
- *              Entry               - Pointer to where a pointer to the stack
- *                                    entry is returned.
+ *              Index               - Which local_var or argument whose type
+ *                                      to get
  *              Walk_state          - Current walk state object
  *
- * RETURN:      Status
- *
- * DESCRIPTION: Get the address of the object entry given by Opcode:Index
+ * RETURN:      Get the Node associated with a local or arg.
  *
  ******************************************************************************/
 
 acpi_status
-acpi_ds_method_data_get_entry (
+acpi_ds_method_data_get_node (
 	u16                     opcode,
 	u32                     index,
 	acpi_walk_state         *walk_state,
-	acpi_operand_object     ***entry)
+	acpi_namespace_node     **node)
 {
-
-	FUNCTION_TRACE_U32 ("Ds_method_data_get_entry", index);
+	ACPI_FUNCTION_TRACE ("Ds_method_data_get_node");
 
 
 	/*
-	 * Get the requested object.
-	 * The stack "Opcode" is either a Local_variable or an Argument
+	 * Method Locals and Arguments are supported
 	 */
 	switch (opcode) {
-
 	case AML_LOCAL_OP:
 
 		if (index > MTH_MAX_LOCAL) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Local_var index %d is invalid (max %d)\n",
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Local index %d is invalid (max %d)\n",
 				index, MTH_MAX_LOCAL));
-			return_ACPI_STATUS (AE_BAD_PARAMETER);
+			return_ACPI_STATUS (AE_AML_INVALID_INDEX);
 		}
 
-		*entry = (acpi_operand_object  **)
-				 &walk_state->local_variables[index].object;
-		break;
+		/* Return a pointer to the pseudo-node */
 
+		*node = &walk_state->local_variables[index];
+		break;
 
 	case AML_ARG_OP:
 
 		if (index > MTH_MAX_ARG) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Arg index %d is invalid (max %d)\n",
 				index, MTH_MAX_ARG));
-			return_ACPI_STATUS (AE_BAD_PARAMETER);
+			return_ACPI_STATUS (AE_AML_INVALID_INDEX);
 		}
 
-		*entry = (acpi_operand_object  **)
-				 &walk_state->arguments[index].object;
-		break;
+		/* Return a pointer to the pseudo-node */
 
+		*node = &walk_state->arguments[index];
+		break;
 
 	default:
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Opcode %d is invalid\n", opcode));
-		return_ACPI_STATUS (AE_BAD_PARAMETER);
+		return_ACPI_STATUS (AE_AML_BAD_OPCODE);
 	}
 
-
 	return_ACPI_STATUS (AE_OK);
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ds_method_data_set_entry
+ * FUNCTION:    Acpi_ds_method_data_set_value
  *
  * PARAMETERS:  Opcode              - Either AML_LOCAL_OP or AML_ARG_OP
  *              Index               - Which local_var or argument to get
@@ -310,22 +280,22 @@
  ******************************************************************************/
 
 acpi_status
-acpi_ds_method_data_set_entry (
+acpi_ds_method_data_set_value (
 	u16                     opcode,
 	u32                     index,
 	acpi_operand_object     *object,
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status;
-	acpi_operand_object     **entry;
+	acpi_namespace_node     *node;
 
 
-	FUNCTION_TRACE ("Ds_method_data_set_entry");
+	ACPI_FUNCTION_TRACE ("Ds_method_data_set_value");
 
 
-	/* Get a pointer to the stack entry to set */
+	/* Get the namespace node for the arg/local */
 
-	status = acpi_ds_method_data_get_entry (opcode, index, walk_state, &entry);
+	status = acpi_ds_method_data_get_node (opcode, index, walk_state, &node);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
@@ -336,8 +306,7 @@
 
 	/* Install the object into the stack entry */
 
-	*entry = object;
-
+	node->object = object;
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -351,105 +320,43 @@
  *                                      to get
  *              Walk_state          - Current walk state object
  *
- * RETURN:      Data type of selected Arg or Local
- *              Used only in Exec_monadic2()/Type_op.
+ * RETURN:      Data type of current value of the selected Arg or Local
  *
  ******************************************************************************/
 
-acpi_object_type8
+acpi_object_type
 acpi_ds_method_data_get_type (
 	u16                     opcode,
 	u32                     index,
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status;
-	acpi_operand_object     **entry;
+	acpi_namespace_node     *node;
 	acpi_operand_object     *object;
 
 
-	FUNCTION_TRACE ("Ds_method_data_get_type");
+	ACPI_FUNCTION_TRACE ("Ds_method_data_get_type");
 
 
-	/* Get a pointer to the requested stack entry */
+	/* Get the namespace node for the arg/local */
 
-	status = acpi_ds_method_data_get_entry (opcode, index, walk_state, &entry);
+	status = acpi_ds_method_data_get_node (opcode, index, walk_state, &node);
 	if (ACPI_FAILURE (status)) {
 		return_VALUE ((ACPI_TYPE_NOT_FOUND));
 	}
 
-	/* Get the object from the method stack */
-
-	object = *entry;
-
-	/* Get the object type */
+	/* Get the object */
 
+	object = acpi_ns_get_attached_object (node);
 	if (!object) {
-		/* Any == 0 => "uninitialized" -- see spec 15.2.3.5.2.28 */
-		return_VALUE (ACPI_TYPE_ANY);
-	}
-
-	return_VALUE (object->common.type);
-}
+		/* Uninitialized local/arg, return TYPE_ANY */
 
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ds_method_data_get_node
- *
- * PARAMETERS:  Opcode              - Either AML_LOCAL_OP or AML_ARG_OP
- *              Index               - Which local_var or argument whose type
- *                                      to get
- *              Walk_state          - Current walk state object
- *
- * RETURN:      Get the Node associated with a local or arg.
- *
- ******************************************************************************/
-
-acpi_namespace_node *
-acpi_ds_method_data_get_node (
-	u16                     opcode,
-	u32                     index,
-	acpi_walk_state         *walk_state)
-{
-	acpi_namespace_node     *node = NULL;
-
-
-	FUNCTION_TRACE ("Ds_method_data_get_node");
-
-
-	switch (opcode) {
-
-	case AML_LOCAL_OP:
-
-		if (index > MTH_MAX_LOCAL) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Local index %d is invalid (max %d)\n",
-				index, MTH_MAX_LOCAL));
-			return_PTR (node);
-		}
-
-		node =  &walk_state->local_variables[index];
-		break;
-
-
-	case AML_ARG_OP:
-
-		if (index > MTH_MAX_ARG) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Arg index %d is invalid (max %d)\n",
-				index, MTH_MAX_ARG));
-			return_PTR (node);
-		}
-
-		node = &walk_state->arguments[index];
-		break;
-
-
-	default:
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Opcode %d is invalid\n", opcode));
-		break;
+		return_VALUE (ACPI_TYPE_ANY);
 	}
 
+	/* Get the object type */
 
-	return_PTR (node);
+	return_VALUE (object->common.type);
 }
 
 
@@ -479,11 +386,11 @@
 	acpi_operand_object     **dest_desc)
 {
 	acpi_status             status;
-	acpi_operand_object     **entry;
+	acpi_namespace_node     *node;
 	acpi_operand_object     *object;
 
 
-	FUNCTION_TRACE ("Ds_method_data_get_value");
+	ACPI_FUNCTION_TRACE ("Ds_method_data_get_value");
 
 
 	/* Validate the object descriptor */
@@ -493,24 +400,22 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	/* Get the namespace node for the arg/local */
 
-	/* Get a pointer to the requested method stack entry */
-
-	status = acpi_ds_method_data_get_entry (opcode, index, walk_state, &entry);
+	status = acpi_ds_method_data_get_node (opcode, index, walk_state, &node);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
 
-	/* Get the object from the method stack */
-
-	object = *entry;
+	/* Get the object from the node */
 
+	object = node->object;
 
 	/* Examine the returned object, it must be valid. */
 
 	if (!object) {
 		/*
-		 * Index points to uninitialized object stack value.
+		 * Index points to uninitialized object.
 		 * This means that either 1) The expected argument was
 		 * not passed to the method, or 2) A local variable
 		 * was referenced by the method (via the ASL)
@@ -519,25 +424,22 @@
 		switch (opcode) {
 		case AML_ARG_OP:
 
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Uninitialized Arg[%d] at entry %p\n",
-				index, entry));
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Uninitialized Arg[%d] at node %p\n",
+				index, node));
 
 			return_ACPI_STATUS (AE_AML_UNINITIALIZED_ARG);
-			break;
 
 		case AML_LOCAL_OP:
 
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Uninitialized Local[%d] at entry %p\n",
-				index, entry));
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Uninitialized Local[%d] at node %p\n",
+				index, node));
 
 			return_ACPI_STATUS (AE_AML_UNINITIALIZED_LOCAL);
-			break;
 		}
 	}
 
-
 	/*
-	 * Index points to initialized and valid object stack value.
+	 * The Index points to an initialized and valid object.
 	 * Return an additional reference to the object
 	 */
 	*dest_desc = object;
@@ -569,37 +471,37 @@
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status;
-	acpi_operand_object     **entry;
+	acpi_namespace_node     *node;
 	acpi_operand_object     *object;
 
 
-	FUNCTION_TRACE ("Ds_method_data_delete_value");
+	ACPI_FUNCTION_TRACE ("Ds_method_data_delete_value");
 
 
-	/* Get a pointer to the requested entry */
+	/* Get the namespace node for the arg/local */
 
-	status = acpi_ds_method_data_get_entry (opcode, index, walk_state, &entry);
+	status = acpi_ds_method_data_get_node (opcode, index, walk_state, &node);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
 
-	/* Get the current entry in this slot k */
+	/* Get the associated object */
 
-	object = *entry;
+	object = acpi_ns_get_attached_object (node);
 
 	/*
 	 * Undefine the Arg or Local by setting its descriptor
 	 * pointer to NULL. Locals/Args can contain both
 	 * ACPI_OPERAND_OBJECTS and ACPI_NAMESPACE_NODEs
 	 */
-	*entry = NULL;
+	node->object = NULL;
 
 	if ((object) &&
-		(VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_INTERNAL))) {
+		(ACPI_GET_DESCRIPTOR_TYPE (object) == ACPI_DESC_TYPE_INTERNAL)) {
 		/*
-		 * There is a valid object in this slot
+		 * There is a valid object.
 		 * Decrement the reference count by one to balance the
-		 * increment when the object was stored in the slot.
+		 * increment when the object was stored.
 		 */
 		acpi_ut_remove_reference (object);
 	}
@@ -614,14 +516,14 @@
  *
  * PARAMETERS:  Opcode              - Either AML_LOCAL_OP or AML_ARG_OP
  *              Index               - Which local_var or argument to set
- *              Src_desc            - Value to be stored
+ *              Obj_desc            - Value to be stored
  *              Walk_state          - Current walk state
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Store a value in an Arg or Local.  The Src_desc is installed
+ * DESCRIPTION: Store a value in an Arg or Local.  The Obj_desc is installed
  *              as the new value for the Arg or Local and the reference count
- *              for Src_desc is incremented.
+ *              for Obj_desc is incremented.
  *
  ******************************************************************************/
 
@@ -629,45 +531,45 @@
 acpi_ds_store_object_to_local (
 	u16                     opcode,
 	u32                     index,
-	acpi_operand_object     *src_desc,
+	acpi_operand_object     *obj_desc,
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status;
-	acpi_operand_object     **entry;
+	acpi_namespace_node     *node;
+	acpi_operand_object     *current_obj_desc;
 
 
-	FUNCTION_TRACE ("Ds_method_data_set_value");
+	ACPI_FUNCTION_TRACE ("Ds_store_object_to_local");
 	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Opcode=%d Idx=%d Obj=%p\n",
-		opcode, index, src_desc));
+		opcode, index, obj_desc));
 
 
 	/* Parameter validation */
 
-	if (!src_desc) {
+	if (!obj_desc) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	/* Get the namespace node for the arg/local */
 
-	/* Get a pointer to the requested method stack entry */
-
-	status = acpi_ds_method_data_get_entry (opcode, index, walk_state, &entry);
+	status = acpi_ds_method_data_get_node (opcode, index, walk_state, &node);
 	if (ACPI_FAILURE (status)) {
-		goto cleanup;
+		return_ACPI_STATUS (status);
 	}
 
-	if (*entry == src_desc) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Obj=%p already installed!\n", src_desc));
-		goto cleanup;
+	current_obj_desc = acpi_ns_get_attached_object (node);
+	if (current_obj_desc == obj_desc) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Obj=%p already installed!\n", obj_desc));
+		return_ACPI_STATUS (status);
 	}
 
-
 	/*
 	 * If there is an object already in this slot, we either
 	 * have to delete it, or if this is an argument and there
 	 * is an object reference stored there, we have to do
 	 * an indirect store!
 	 */
-	if (*entry) {
+	if (current_obj_desc) {
 		/*
 		 * Check for an indirect store if an argument
 		 * contains an object reference (stored as an Node).
@@ -685,36 +587,24 @@
 		 * Weird, but true.
 		 */
 		if ((opcode == AML_ARG_OP) &&
-			(VALID_DESCRIPTOR_TYPE (*entry, ACPI_DESC_TYPE_NAMED))) {
+			(ACPI_GET_DESCRIPTOR_TYPE (current_obj_desc) == ACPI_DESC_TYPE_NAMED)) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_EXEC,
-				"Arg (%p) is an Obj_ref(Node), storing in %p\n",
-				src_desc, *entry));
+				"Arg (%p) is an Obj_ref(Node), storing in node %p\n",
+				obj_desc, current_obj_desc));
 
 			/* Detach an existing object from the Node */
 
-			acpi_ns_detach_object ((acpi_namespace_node *) *entry);
+			acpi_ns_detach_object ((acpi_namespace_node *) current_obj_desc);
 
 			/*
 			 * Store this object into the Node
-			 * (do the indirect store)
+			 * (perform the indirect store)
 			 */
-			status = acpi_ns_attach_object ((acpi_namespace_node *) *entry, src_desc,
-					   src_desc->common.type);
+			status = acpi_ns_attach_object ((acpi_namespace_node *) current_obj_desc,
+					  obj_desc, obj_desc->common.type);
 			return_ACPI_STATUS (status);
 		}
 
-
-#ifdef ACPI_ENABLE_IMPLICIT_CONVERSION
-		/*
-		 * Perform "Implicit conversion" of the new object to the type of the
-		 * existing object
-		 */
-		status = acpi_ex_convert_to_target_type ((*entry)->common.type, &src_desc, walk_state);
-		if (ACPI_FAILURE (status)) {
-			goto cleanup;
-		}
-#endif
-
 		/*
 		 * Delete the existing object
 		 * before storing the new one
@@ -722,27 +612,14 @@
 		acpi_ds_method_data_delete_value (opcode, index, walk_state);
 	}
 
-
 	/*
-	 * Install the Obj_stack descriptor (*Src_desc) into
+	 * Install the Obj_stack descriptor (*Obj_desc) into
 	 * the descriptor for the Arg or Local.
 	 * Install the new object in the stack entry
 	 * (increments the object reference count by one)
 	 */
-	status = acpi_ds_method_data_set_entry (opcode, index, src_desc, walk_state);
-	if (ACPI_FAILURE (status)) {
-		goto cleanup;
-	}
-
-	/* Normal exit */
-
-	return_ACPI_STATUS (AE_OK);
-
-
-	/* Error exit */
-
-cleanup:
-
+	status = acpi_ds_method_data_set_value (opcode, index, obj_desc, walk_state);
 	return_ACPI_STATUS (status);
 }
+
 
diff -Nru a/drivers/acpi/dispatcher/dsobject.c b/drivers/acpi/dispatcher/dsobject.c
--- a/drivers/acpi/dispatcher/dsobject.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/dispatcher/dsobject.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dsobject - Dispatcher object management routines
- *              $Revision: 81 $
+ *              $Revision: 90 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dsobject")
+	 ACPI_MODULE_NAME    ("dsobject")
 
 
 /*******************************************************************************
@@ -62,13 +62,13 @@
 	void                    *context,
 	void                    **return_value)
 {
-	acpi_object_type8       type;
+	acpi_object_type        type;
 	acpi_status             status;
 	acpi_init_walk_info     *info = (acpi_init_walk_info *) context;
 	u8                      table_revision;
 
 
-	PROC_NAME ("Ds_init_one_object");
+	ACPI_FUNCTION_NAME ("Ds_init_one_object");
 
 
 	info->object_count++;
@@ -89,7 +89,6 @@
 	type = acpi_ns_get_type (obj_handle);
 
 	switch (type) {
-
 	case ACPI_TYPE_REGION:
 
 		acpi_ds_initialize_region (obj_handle);
@@ -121,7 +120,7 @@
 		status = acpi_ds_parse_method (obj_handle);
 		if (ACPI_FAILURE (status)) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Method %p [%4.4s] - parse failure, %s\n",
-				obj_handle, (char*)&((acpi_namespace_node *)obj_handle)->name,
+				obj_handle, (char *) &((acpi_namespace_node *) obj_handle)->name,
 				acpi_format_exception (status)));
 
 			/* This parse failed, but we will continue parsing more methods */
@@ -134,6 +133,7 @@
 		 * for every execution since there isn't much overhead
 		 */
 		acpi_ns_delete_namespace_subtree (obj_handle);
+		acpi_ns_delete_namespace_by_owner (((acpi_namespace_node *) obj_handle)->object->method.owning_id);
 		break;
 
 	default:
@@ -170,7 +170,7 @@
 	acpi_init_walk_info     info;
 
 
-	FUNCTION_TRACE ("Ds_initialize_objects");
+	ACPI_FUNCTION_TRACE ("Ds_initialize_objects");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
@@ -235,7 +235,7 @@
 	acpi_operand_object     *obj_desc;
 
 
-	PROC_NAME ("Ds_init_object_from_op");
+	ACPI_FUNCTION_NAME ("Ds_init_object_from_op");
 
 
 	obj_desc = *ret_obj_desc;
@@ -252,6 +252,8 @@
 	switch (obj_desc->common.type) {
 	case ACPI_TYPE_BUFFER:
 
+		obj_desc->buffer.node = (acpi_namespace_node *) walk_state->operands[0];
+
 		/* First arg is a number */
 
 		acpi_ds_create_operand (walk_state, op->value.arg, 0);
@@ -285,7 +287,7 @@
 
 		if (obj_desc->buffer.length == 0) {
 			obj_desc->buffer.pointer = NULL;
-			REPORT_WARNING (("Buffer created with zero length in AML\n"));
+			ACPI_REPORT_WARNING (("Buffer created with zero length in AML\n"));
 			break;
 		}
 
@@ -312,8 +314,8 @@
 				return (AE_TYPE);
 			}
 
-			MEMCPY (obj_desc->buffer.pointer, byte_list->data,
-					obj_desc->buffer.length);
+			ACPI_MEMCPY (obj_desc->buffer.pointer, byte_list->data,
+					  obj_desc->buffer.length);
 		}
 
 		break;
@@ -339,7 +341,7 @@
 
 	case ACPI_TYPE_STRING:
 		obj_desc->string.pointer = op->value.string;
-		obj_desc->string.length = STRLEN (op->value.string);
+		obj_desc->string.length = ACPI_STRLEN (op->value.string);
 
 		/*
 		 * The string is contained in the ACPI table, don't ever try
@@ -422,42 +424,38 @@
 	acpi_operand_object     **obj_desc_ptr)
 {
 	acpi_operand_object     *obj_desc;
-	acpi_object_type8       type;
 	acpi_status             status;
-	u32                     length;
 	char                    *name;
 
 
-	FUNCTION_TRACE ("Ds_build_internal_simple_obj");
+	ACPI_FUNCTION_TRACE ("Ds_build_internal_simple_obj");
 
 
 	if (op->opcode == AML_INT_NAMEPATH_OP) {
 		/*
-		 * This is an object reference.  If The name was
-		 * previously looked up in the NS, it is stored in this op.
+		 * This is an object reference.  If this name was
+		 * previously looked up in the namespace, it was stored in this op.
 		 * Otherwise, go ahead and look it up now
 		 */
 		if (!op->node) {
-			status = acpi_ns_lookup (walk_state->scope_info,
-					  op->value.string, ACPI_TYPE_ANY,
-					  IMODE_EXECUTE,
-					  NS_SEARCH_PARENT | NS_DONT_OPEN_SCOPE,
-					  NULL,
-					  (acpi_namespace_node **)&(op->node));
+			status = acpi_ns_lookup (walk_state->scope_info, op->value.string,
+					  ACPI_TYPE_ANY, ACPI_IMODE_EXECUTE,
+					  ACPI_NS_SEARCH_PARENT | ACPI_NS_DONT_OPEN_SCOPE, NULL,
+					  (acpi_namespace_node **) &(op->node));
 
 			if (ACPI_FAILURE (status)) {
 				if (status == AE_NOT_FOUND) {
 					name = NULL;
-					acpi_ns_externalize_name (ACPI_UINT32_MAX, op->value.string, &length, &name);
+					acpi_ns_externalize_name (ACPI_UINT32_MAX, op->value.string, NULL, &name);
 
 					if (name) {
-						REPORT_WARNING (("Reference %s at AML %X not found\n",
+						ACPI_REPORT_WARNING (("Reference %s at AML %X not found\n",
 								 name, op->aml_offset));
 						ACPI_MEM_FREE (name);
 					}
 
 					else {
-						REPORT_WARNING (("Reference %s at AML %X not found\n",
+						ACPI_REPORT_WARNING (("Reference %s at AML %X not found\n",
 								   op->value.string, op->aml_offset));
 					}
 
@@ -469,23 +467,11 @@
 				}
 			}
 		}
-
-		/*
-		 * The reference will be a Reference
-		 * TBD: [Restructure] unless we really need a separate
-		 *  type of INTERNAL_TYPE_REFERENCE change
-		 *  Acpi_ds_map_opcode_to_data_type to handle this case
-		 */
-		type = INTERNAL_TYPE_REFERENCE;
-	}
-	else {
-		type = acpi_ds_map_opcode_to_data_type (op->opcode, NULL);
 	}
 
-
 	/* Create and init the internal ACPI object */
 
-	obj_desc = acpi_ut_create_internal_object (type);
+	obj_desc = acpi_ut_create_internal_object ((acpi_ps_get_opcode_info (op->opcode))->object_type);
 	if (!obj_desc) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
@@ -527,7 +513,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ds_build_internal_package_obj");
+	ACPI_FUNCTION_TRACE ("Ds_build_internal_package_obj");
 
 
 	obj_desc = acpi_ut_create_internal_object (ACPI_TYPE_PACKAGE);
@@ -651,7 +637,7 @@
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE_PTR ("Ds_create_node", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_create_node", op);
 
 
 	/*
@@ -659,7 +645,7 @@
 	 * parts of the table, we can arrive here twice.  Only init
 	 * the named object node the first time through
 	 */
-	if (node->object) {
+	if (acpi_ns_get_attached_object (node)) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
@@ -682,7 +668,7 @@
 
 	/* Init obj */
 
-	status = acpi_ns_attach_object (node, obj_desc, (u8) node->type);
+	status = acpi_ns_attach_object (node, obj_desc, node->type);
 
 	/* Remove local reference to the object */
 
diff -Nru a/drivers/acpi/dispatcher/dsopcode.c b/drivers/acpi/dispatcher/dsopcode.c
--- a/drivers/acpi/dispatcher/dsopcode.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/dispatcher/dsopcode.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: dsopcode - Dispatcher Op Region support and handling of
  *                         "control" opcodes
- *              $Revision: 56 $
+ *              $Revision: 73 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,77 +35,52 @@
 #include "actables.h"
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dsopcode")
+	 ACPI_MODULE_NAME    ("dsopcode")
 
 
 /*****************************************************************************
  *
- * FUNCTION:    Acpi_ds_get_buffer_field_arguments
+ * FUNCTION:    Acpi_ds_execute_arguments
  *
- * PARAMETERS:  Obj_desc        - A valid Buffer_field object
+ * PARAMETERS:  Node                - Parent NS node
+ *              Extra_desc          - Has AML pointer and length
  *
  * RETURN:      Status.
  *
- * DESCRIPTION: Get Buffer_field Buffer and Index. This implements the late
- *              evaluation of these field attributes.
+ * DESCRIPTION: Late execution of region or field arguments
  *
  ****************************************************************************/
 
 acpi_status
-acpi_ds_get_buffer_field_arguments (
-	acpi_operand_object     *obj_desc)
+acpi_ds_execute_arguments (
+	acpi_namespace_node     *node,
+	acpi_operand_object     *extra_desc)
 {
-	acpi_operand_object     *extra_desc;
-	acpi_namespace_node     *node;
-	acpi_parse_object       *op;
-	acpi_parse_object       *field_op;
 	acpi_status             status;
-	acpi_table_desc         *table_desc;
+	acpi_parse_object       *op;
 	acpi_walk_state         *walk_state;
+	acpi_parse_object       *arg;
 
 
-	FUNCTION_TRACE_PTR ("Ds_get_buffer_field_arguments", obj_desc);
-
-
-	if (obj_desc->common.flags & AOPOBJ_DATA_VALID) {
-		return_ACPI_STATUS (AE_OK);
-	}
-
-
-	/* Get the AML pointer (method object) and Buffer_field node */
-
-	extra_desc = obj_desc->buffer_field.extra;
-	node = obj_desc->buffer_field.node;
-
-	DEBUG_EXEC(acpi_ut_display_init_pathname (node, " [Field]"));
-	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[%4.4s] Buffer_field JIT Init\n",
-		(char*)&node->name));
+	ACPI_FUNCTION_TRACE ("Acpi_ds_execute_arguments");
 
 
 	/*
 	 * Allocate a new parser op to be the root of the parsed
-	 * Op_region tree
+	 * Buffer_field tree
 	 */
 	op = acpi_ps_alloc_op (AML_SCOPE_OP);
 	if (!op) {
-		return (AE_NO_MEMORY);
+		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
 	/* Save the Node for use in Acpi_ps_parse_aml */
 
-	op->node = acpi_ns_get_parent_object (node);
-
-	/* Get a handle to the parent ACPI table */
-
-	status = acpi_tb_handle_to_object (node->owner_id, &table_desc);
-	if (ACPI_FAILURE (status)) {
-		return_ACPI_STATUS (status);
-	}
+	op->node = acpi_ns_get_parent_node (node);
 
 	/* Create and initialize a new parser state */
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
-			   NULL, NULL, NULL);
+	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT, NULL, NULL, NULL);
 	if (!walk_state) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
@@ -113,12 +88,10 @@
 	status = acpi_ds_init_aml_walk (walk_state, op, NULL, extra_desc->extra.aml_start,
 			  extra_desc->extra.aml_length, NULL, NULL, 1);
 	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
+		acpi_ds_delete_walk_state (walk_state);
 		return_ACPI_STATUS (status);
 	}
 
-	/* TBD: No Walk flags?? */
-
 	walk_state->parse_flags = 0;
 
 	/* Pass1: Parse the entire Buffer_field declaration */
@@ -131,27 +104,23 @@
 
 	/* Get and init the actual Field_unit Op created above */
 
-	field_op = op->value.arg;
+	arg = op->value.arg;
 	op->node = node;
-
-
-	field_op = op->value.arg;
-	field_op->node = node;
+	arg->node = node;
 	acpi_ps_delete_parse_tree (op);
 
-	/* Evaluate the address and length arguments for the Op_region */
+	/* Evaluate the address and length arguments for the Buffer Field */
 
 	op = acpi_ps_alloc_op (AML_SCOPE_OP);
 	if (!op) {
-		return (AE_NO_MEMORY);
+		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
-	op->node = acpi_ns_get_parent_object (node);
+	op->node = acpi_ns_get_parent_node (node);
 
 	/* Create and initialize a new parser state */
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
-			   NULL, NULL, NULL);
+	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT, NULL, NULL, NULL);
 	if (!walk_state) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
@@ -159,152 +128,106 @@
 	status = acpi_ds_init_aml_walk (walk_state, op, NULL, extra_desc->extra.aml_start,
 			  extra_desc->extra.aml_length, NULL, NULL, 3);
 	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
+		acpi_ds_delete_walk_state (walk_state);
 		return_ACPI_STATUS (status);
 	}
 
 	status = acpi_ps_parse_aml (walk_state);
 	acpi_ps_delete_parse_tree (op);
-
-	/*
-	 * The pseudo-method object is no longer needed since the region is
-	 * now initialized
-	 */
-	acpi_ut_remove_reference (obj_desc->buffer_field.extra);
-	obj_desc->buffer_field.extra = NULL;
-
 	return_ACPI_STATUS (status);
 }
 
 
 /*****************************************************************************
  *
- * FUNCTION:    Acpi_ds_get_region_arguments
+ * FUNCTION:    Acpi_ds_get_buffer_field_arguments
  *
- * PARAMETERS:  Obj_desc        - A valid region object
+ * PARAMETERS:  Obj_desc        - A valid Buffer_field object
  *
  * RETURN:      Status.
  *
- * DESCRIPTION: Get region address and length.  This implements the late
- *              evaluation of these region attributes.
+ * DESCRIPTION: Get Buffer_field Buffer and Index. This implements the late
+ *              evaluation of these field attributes.
  *
  ****************************************************************************/
 
 acpi_status
-acpi_ds_get_region_arguments (
+acpi_ds_get_buffer_field_arguments (
 	acpi_operand_object     *obj_desc)
 {
-	acpi_operand_object     *extra_desc = NULL;
+	acpi_operand_object     *extra_desc;
 	acpi_namespace_node     *node;
-	acpi_parse_object       *op;
-	acpi_parse_object       *region_op;
 	acpi_status             status;
-	acpi_table_desc         *table_desc;
-	acpi_walk_state         *walk_state;
 
 
-	FUNCTION_TRACE_PTR ("Ds_get_region_arguments", obj_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_get_buffer_field_arguments", obj_desc);
 
 
-	if (obj_desc->region.flags & AOPOBJ_DATA_VALID) {
+	if (obj_desc->common.flags & AOPOBJ_DATA_VALID) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
+	/* Get the AML pointer (method object) and Buffer_field node */
 
-	/* Get the AML pointer (method object) and region node */
-
-	extra_desc = obj_desc->region.extra;
-	node = obj_desc->region.node;
-
-	DEBUG_EXEC(acpi_ut_display_init_pathname (node, " [Operation Region]"));
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[%4.4s] Op_region Init at AML %p\n",
-		(char*)&node->name, extra_desc->extra.aml_start));
-
-	/*
-	 * Allocate a new parser op to be the root of the parsed
-	 * Op_region tree
-	 */
-	op = acpi_ps_alloc_op (AML_SCOPE_OP);
-	if (!op) {
-		return (AE_NO_MEMORY);
-	}
-
-	/* Save the Node for use in Acpi_ps_parse_aml */
+	extra_desc = acpi_ns_get_secondary_object (obj_desc);
+	node = obj_desc->buffer_field.node;
 
-	op->node = acpi_ns_get_parent_object (node);
+	ACPI_DEBUG_EXEC(acpi_ut_display_init_pathname (node, " [Field]"));
+	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[%4.4s] Buffer_field JIT Init\n",
+		(char *) &node->name));
 
-	/* Get a handle to the parent ACPI table */
+	/* Execute the AML code for the Term_arg arguments */
 
-	status = acpi_tb_handle_to_object (node->owner_id, &table_desc);
-	if (ACPI_FAILURE (status)) {
-		return_ACPI_STATUS (status);
-	}
+	status = acpi_ds_execute_arguments (node, extra_desc);
+	return_ACPI_STATUS (status);
+}
 
-	/* Create and initialize a new parser state */
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
-			   op, NULL, NULL);
-	if (!walk_state) {
-		return_ACPI_STATUS (AE_NO_MEMORY);
-	}
+/*****************************************************************************
+ *
+ * FUNCTION:    Acpi_ds_get_region_arguments
+ *
+ * PARAMETERS:  Obj_desc        - A valid region object
+ *
+ * RETURN:      Status.
+ *
+ * DESCRIPTION: Get region address and length.  This implements the late
+ *              evaluation of these region attributes.
+ *
+ ****************************************************************************/
 
-	status = acpi_ds_init_aml_walk (walk_state, op, NULL, extra_desc->extra.aml_start,
-			  extra_desc->extra.aml_length, NULL, NULL, 1);
-	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
-		return_ACPI_STATUS (status);
-	}
+acpi_status
+acpi_ds_get_region_arguments (
+	acpi_operand_object     *obj_desc)
+{
+	acpi_namespace_node     *node;
+	acpi_status             status;
+	acpi_operand_object     *region_obj2;
 
-	/* TBD: No Walk flags?? */
 
-	walk_state->parse_flags = 0;
+	ACPI_FUNCTION_TRACE_PTR ("Ds_get_region_arguments", obj_desc);
 
-	/* Parse the entire Op_region declaration, creating a parse tree */
 
-	status = acpi_ps_parse_aml (walk_state);
-	if (ACPI_FAILURE (status)) {
-		acpi_ps_delete_parse_tree (op);
-		return_ACPI_STATUS (status);
+	if (obj_desc->region.flags & AOPOBJ_DATA_VALID) {
+		return_ACPI_STATUS (AE_OK);
 	}
 
-	/* Get and init the actual Region_op created above */
-
-	region_op = op->value.arg;
-	op->node = node;
-
-
-	region_op = op->value.arg;
-	region_op->node = node;
-	acpi_ps_delete_parse_tree (op);
-
-	/* Evaluate the address and length arguments for the Op_region */
-
-	op = acpi_ps_alloc_op (AML_SCOPE_OP);
-	if (!op) {
-		return (AE_NO_MEMORY);
+	region_obj2 = acpi_ns_get_secondary_object (obj_desc);
+	if (!region_obj2) {
+		return_ACPI_STATUS (AE_NOT_EXIST);
 	}
 
-	op->node = acpi_ns_get_parent_object (node);
+	/* Get the AML pointer (method object) and region node */
 
-	/* Create and initialize a new parser state */
+	node = obj_desc->region.node;
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
-			   op, NULL, NULL);
-	if (!walk_state) {
-		return_ACPI_STATUS (AE_NO_MEMORY);
-	}
+	ACPI_DEBUG_EXEC(acpi_ut_display_init_pathname (node, " [Operation Region]"));
 
-	status = acpi_ds_init_aml_walk (walk_state, op, NULL, extra_desc->extra.aml_start,
-			  extra_desc->extra.aml_length, NULL, NULL, 3);
-	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
-		return_ACPI_STATUS (status);
-	}
+	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[%4.4s] Op_region Init at AML %p\n",
+		(char *) &node->name, region_obj2->extra.aml_start));
 
-	status = acpi_ps_parse_aml (walk_state);
-	acpi_ps_delete_parse_tree (op);
 
+	status = acpi_ds_execute_arguments (node, region_obj2);
 	return_ACPI_STATUS (status);
 }
 
@@ -334,7 +257,6 @@
 	/* Namespace is NOT locked */
 
 	status = acpi_ev_initialize_region (obj_desc, FALSE);
-
 	return (status);
 }
 
@@ -350,21 +272,6 @@
  * DESCRIPTION: Get Buffer_field Buffer and Index
  *              Called from Acpi_ds_exec_end_op during Buffer_field parse tree walk
  *
- * ACPI SPECIFICATION REFERENCES:
- *  Each of the Buffer Field opcodes is defined as specified in in-line
- *  comments below. For each one, use the following definitions.
- *
- *  Def_bit_field   :=  Bit_field_op    Src_buf Bit_idx Destination
- *  Def_byte_field  :=  Byte_field_op   Src_buf Byte_idx Destination
- *  Def_create_field := Create_field_op Src_buf Bit_idx Num_bits Name_string
- *  Def_dWord_field :=  DWord_field_op  Src_buf Byte_idx Destination
- *  Def_word_field  :=  Word_field_op   Src_buf Byte_idx Destination
- *  Bit_index       :=  Term_arg=>Integer
- *  Byte_index      :=  Term_arg=>Integer
- *  Destination     :=  Name_string
- *  Num_bits        :=  Term_arg=>Integer
- *  Source_buf      :=  Term_arg=>Buffer
- *
  ****************************************************************************/
 
 acpi_status
@@ -386,7 +293,7 @@
 	acpi_operand_object     *src_desc = NULL;
 
 
-	FUNCTION_TRACE_PTR ("Ds_eval_buffer_field_operands", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_eval_buffer_field_operands", op);
 
 
 	/*
@@ -411,11 +318,10 @@
 		return_ACPI_STATUS (AE_NOT_EXIST);
 	}
 
-
 	/* Resolve the operands */
 
-	status = acpi_ex_resolve_operands (op->opcode, WALK_OPERANDS, walk_state);
-	DUMP_OPERANDS (WALK_OPERANDS, IMODE_EXECUTE, acpi_ps_get_opcode_name (op->opcode),
+	status = acpi_ex_resolve_operands (op->opcode, ACPI_WALK_OPERANDS, walk_state);
+	ACPI_DUMP_OPERANDS (ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE, acpi_ps_get_opcode_name (op->opcode),
 			  walk_state->num_operands, "after Acpi_ex_resolve_operands");
 
 	if (ACPI_FAILURE (status)) {
@@ -437,16 +343,14 @@
 
 	off_desc = walk_state->operands[1];
 	src_desc = walk_state->operands[0];
-
-
-	offset = (u32) off_desc->integer.value;
+	offset  = (u32) off_desc->integer.value;
 
 	/*
 	 * If Res_desc is a Name, it will be a direct name pointer after
 	 * Acpi_ex_resolve_operands()
 	 */
-	if (!VALID_DESCRIPTOR_TYPE (res_desc, ACPI_DESC_TYPE_NAMED)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "(%s) destination must be a Node\n",
+	if (ACPI_GET_DESCRIPTOR_TYPE (res_desc) != ACPI_DESC_TYPE_NAMED) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "(%s) destination must be a NS Node\n",
 			acpi_ps_get_opcode_name (op->opcode)));
 
 		status = AE_AML_OPERAND_TYPE;
@@ -457,79 +361,60 @@
 	 * Setup the Bit offsets and counts, according to the opcode
 	 */
 	switch (op->opcode) {
-
-	/* Def_create_field */
-
 	case AML_CREATE_FIELD_OP:
 
 		/* Offset is in bits, count is in bits */
 
 		bit_offset  = offset;
 		bit_count   = (u32) cnt_desc->integer.value;
-		field_flags = ACCESS_BYTE_ACC;
+		field_flags = AML_FIELD_ACCESS_BYTE;
 		break;
 
-
-	/* Def_create_bit_field */
-
 	case AML_CREATE_BIT_FIELD_OP:
 
 		/* Offset is in bits, Field is one bit */
 
 		bit_offset  = offset;
 		bit_count   = 1;
-		field_flags = ACCESS_BYTE_ACC;
+		field_flags = AML_FIELD_ACCESS_BYTE;
 		break;
 
-
-	/* Def_create_byte_field */
-
 	case AML_CREATE_BYTE_FIELD_OP:
 
 		/* Offset is in bytes, field is one byte */
 
 		bit_offset  = 8 * offset;
 		bit_count   = 8;
-		field_flags = ACCESS_BYTE_ACC;
+		field_flags = AML_FIELD_ACCESS_BYTE;
 		break;
 
-
-	/* Def_create_word_field */
-
 	case AML_CREATE_WORD_FIELD_OP:
 
 		/* Offset is in bytes, field is one word */
 
 		bit_offset  = 8 * offset;
 		bit_count   = 16;
-		field_flags = ACCESS_WORD_ACC;
+		field_flags = AML_FIELD_ACCESS_WORD;
 		break;
 
-
-	/* Def_create_dWord_field */
-
 	case AML_CREATE_DWORD_FIELD_OP:
 
 		/* Offset is in bytes, field is one dword */
 
 		bit_offset  = 8 * offset;
 		bit_count   = 32;
-		field_flags = ACCESS_DWORD_ACC;
+		field_flags = AML_FIELD_ACCESS_DWORD;
 		break;
 
-
-	/* Def_create_qWord_field */
-
 	case AML_CREATE_QWORD_FIELD_OP:
 
 		/* Offset is in bytes, field is one qword */
 
 		bit_offset  = 8 * offset;
 		bit_count   = 64;
-		field_flags = ACCESS_QWORD_ACC;
+		field_flags = AML_FIELD_ACCESS_QWORD;
 		break;
 
-
 	default:
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
@@ -539,7 +424,6 @@
 		goto cleanup;
 	}
 
-
 	/*
 	 * Setup field according to the object type
 	 */
@@ -558,12 +442,11 @@
 			goto cleanup;
 		}
 
-
 		/*
 		 * Initialize areas of the field object that are common to all fields
 		 * For Field_flags, use LOCK_RULE = 0 (NO_LOCK), UPDATE_RULE = 0 (UPDATE_PRESERVE)
 		 */
-		status = acpi_ex_prep_common_field_object (obj_desc, field_flags,
+		status = acpi_ex_prep_common_field_object (obj_desc, field_flags, 0,
 				  bit_offset, bit_count);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
@@ -575,7 +458,6 @@
 
 		src_desc->common.reference_count = (u16) (src_desc->common.reference_count +
 				  obj_desc->common.reference_count);
-
 		break;
 
 
@@ -583,12 +465,11 @@
 
 	default:
 
-		if ((src_desc->common.type > (u8) INTERNAL_TYPE_REFERENCE) || !acpi_ut_valid_object_type (src_desc->common.type)) /* TBD: This line MUST be a single line until Acpi_src can handle it (block deletion) */ {
+		if ((src_desc->common.type > (u8) INTERNAL_TYPE_REFERENCE) || !acpi_ut_valid_object_type (src_desc->common.type)) /* This line MUST be a single line until Acpi_src can handle it (block deletion) */ {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 				"Tried to create field in invalid object type %X\n",
 				src_desc->common.type));
 		}
-
 		else {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 				"Tried to create field in improper object type - %s\n",
@@ -624,7 +505,6 @@
 	if (ACPI_FAILURE (status)) {
 		acpi_ut_remove_reference (res_desc); /* Result descriptor */
 	}
-
 	else {
 		/* Now the address and length are valid for this Buffer_field */
 
@@ -660,7 +540,7 @@
 	acpi_parse_object       *next_op;
 
 
-	FUNCTION_TRACE_PTR ("Ds_eval_region_operands", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_eval_region_operands", op);
 
 
 	/*
@@ -685,16 +565,15 @@
 
 	/* Resolve the length and address operands to numbers */
 
-	status = acpi_ex_resolve_operands (op->opcode, WALK_OPERANDS, walk_state);
+	status = acpi_ex_resolve_operands (op->opcode, ACPI_WALK_OPERANDS, walk_state);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
 
-	DUMP_OPERANDS (WALK_OPERANDS, IMODE_EXECUTE,
+	ACPI_DUMP_OPERANDS (ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE,
 			  acpi_ps_get_opcode_name (op->opcode),
 			  1, "after Acpi_ex_resolve_operands");
 
-
 	obj_desc = acpi_ns_get_attached_object (node);
 	if (!obj_desc) {
 		return_ACPI_STATUS (AE_NOT_EXIST);
@@ -718,9 +597,9 @@
 	obj_desc->region.address = (ACPI_PHYSICAL_ADDRESS) operand_desc->integer.value;
 	acpi_ut_remove_reference (operand_desc);
 
-
 	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Rgn_obj %p Addr %8.8X%8.8X Len %X\n",
-		obj_desc, HIDWORD(obj_desc->region.address), LODWORD(obj_desc->region.address),
+		obj_desc,
+		ACPI_HIDWORD (obj_desc->region.address), ACPI_LODWORD (obj_desc->region.address),
 		obj_desc->region.length));
 
 	/* Now the address and length are valid for this opregion */
@@ -754,7 +633,7 @@
 	acpi_generic_state      *control_state;
 
 
-	PROC_NAME ("Ds_exec_begin_control_op");
+	ACPI_FUNCTION_NAME ("Ds_exec_begin_control_op");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op=%p Opcode=%2.2X State=%p\n", op,
@@ -774,20 +653,20 @@
 			status = AE_NO_MEMORY;
 			break;
 		}
-
-		acpi_ut_push_generic_state (&walk_state->control_state, control_state);
-
 		/*
 		 * Save a pointer to the predicate for multiple executions
 		 * of a loop
 		 */
-		walk_state->control_state->control.aml_predicate_start =
-				 walk_state->parser_state.aml - 1;
-				 /* TBD: can this be removed? */
-				 /*Acpi_ps_pkg_length_encoding_size (GET8 (Walk_state->Parser_state->Aml));*/
-		break;
+		control_state->control.aml_predicate_start = walk_state->parser_state.aml - 1;
+		control_state->control.package_end = walk_state->parser_state.pkg_end;
+		control_state->control.opcode = op->opcode;
 
 
+		/* Push the control state on this walk's control stack */
+
+		acpi_ut_push_generic_state (&walk_state->control_state, control_state);
+		break;
+
 	case AML_ELSE_OP:
 
 		/* Predicate is in the state object */
@@ -799,12 +678,10 @@
 
 		break;
 
-
 	case AML_RETURN_OP:
 
 		break;
 
-
 	default:
 		break;
 	}
@@ -825,7 +702,6 @@
  * DESCRIPTION: Handles all control ops encountered during control method
  *              execution.
  *
- *
  ******************************************************************************/
 
 acpi_status
@@ -837,7 +713,7 @@
 	acpi_generic_state      *control_state;
 
 
-	PROC_NAME ("Ds_exec_end_control_op");
+	ACPI_FUNCTION_NAME ("Ds_exec_end_control_op");
 
 
 	switch (op->opcode) {
@@ -922,7 +798,6 @@
 			 */
 			walk_state->return_desc = walk_state->operands[0];
 		}
-
 		else if ((walk_state->results) &&
 				 (walk_state->results->results.num_results > 0)) {
 			/*
@@ -934,18 +809,17 @@
 			 *
 			 * Allow references created by the Index operator to return unchanged.
 			 */
-			if (VALID_DESCRIPTOR_TYPE (walk_state->results->results.obj_desc [0], ACPI_DESC_TYPE_INTERNAL) &&
+			if ((ACPI_GET_DESCRIPTOR_TYPE (walk_state->results->results.obj_desc[0]) == ACPI_DESC_TYPE_INTERNAL) &&
 				((walk_state->results->results.obj_desc [0])->common.type == INTERNAL_TYPE_REFERENCE) &&
 				((walk_state->results->results.obj_desc [0])->reference.opcode != AML_INDEX_OP)) {
-					status = acpi_ex_resolve_to_value (&walk_state->results->results.obj_desc [0], walk_state);
-					if (ACPI_FAILURE (status)) {
-						return (status);
-					}
+				status = acpi_ex_resolve_to_value (&walk_state->results->results.obj_desc [0], walk_state);
+				if (ACPI_FAILURE (status)) {
+					return (status);
+				}
 			}
 
 			walk_state->return_desc = walk_state->results->results.obj_desc [0];
 		}
-
 		else {
 			/* No return operand */
 
@@ -987,30 +861,35 @@
 
 
 	case AML_BREAK_OP:
+	case AML_CONTINUE_OP: /* ACPI 2.0 */
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-			"Break to end of current package, Op=%p\n", op));
 
-		/* TBD: update behavior for ACPI 2.0 */
+		/* Pop and delete control states until we find a while */
 
-		/*
-		 * As per the ACPI specification:
-		 *      "The break operation causes the current package
-		 *          execution to complete"
-		 *      "Break -- Stop executing the current code package
-		 *          at this point"
-		 *
-		 * Returning AE_FALSE here will cause termination of
-		 * the current package, and execution will continue one
-		 * level up, starting with the completion of the parent Op.
-		 */
-		status = AE_CTRL_FALSE;
-		break;
+		while (walk_state->control_state &&
+				(walk_state->control_state->control.opcode != AML_WHILE_OP)) {
+			control_state = acpi_ut_pop_generic_state (&walk_state->control_state);
+			acpi_ut_delete_generic_state (control_state);
+		}
 
+		/* No while found? */
 
-	case AML_CONTINUE_OP: /* ACPI 2.0 */
+		if (!walk_state->control_state) {
+			return (AE_AML_NO_WHILE);
+		}
+
+		/* Was: Walk_state->Aml_last_while = Walk_state->Control_state->Control.Aml_predicate_start; */
+
+		walk_state->aml_last_while = walk_state->control_state->control.package_end;
 
-		status = AE_NOT_IMPLEMENTED;
+		/* Return status depending on opcode */
+
+		if (op->opcode == AML_BREAK_OP) {
+			status = AE_CTRL_BREAK;
+		}
+		else {
+			status = AE_CTRL_CONTINUE;
+		}
 		break;
 
 
@@ -1022,7 +901,6 @@
 		status = AE_AML_BAD_OPCODE;
 		break;
 	}
-
 
 	return (status);
 }
diff -Nru a/drivers/acpi/dispatcher/dsutils.c b/drivers/acpi/dispatcher/dsutils.c
--- a/drivers/acpi/dispatcher/dsutils.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/dispatcher/dsutils.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: dsutils - Dispatcher utilities
- *              $Revision: 80 $
+ *              $Revision: 88 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 #include "acdebug.h"
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dsutils")
+	 ACPI_MODULE_NAME    ("dsutils")
 
 
 /*******************************************************************************
@@ -58,7 +58,7 @@
 	const acpi_opcode_info  *parent_info;
 
 
-	FUNCTION_TRACE_PTR ("Ds_is_result_used", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_is_result_used", op);
 
 
 	/* Must have both an Op and a Result Object */
@@ -68,7 +68,6 @@
 		return_VALUE (TRUE);
 	}
 
-
 	/*
 	 * If there is no parent, the result can't possibly be used!
 	 * (An executing method typically has no parent, since each
@@ -79,18 +78,15 @@
 		return_VALUE (FALSE);
 	}
 
-
 	/*
 	 * Get info on the parent.  The root Op is AML_SCOPE
 	 */
-
 	parent_info = acpi_ps_get_opcode_info (op->parent->opcode);
 	if (parent_info->class == AML_CLASS_UNKNOWN) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown parent opcode. Op=%p\n", op));
 		return_VALUE (FALSE);
 	}
 
-
 	/*
 	 * Decide what to do with the result based on the parent.  If
 	 * the parent opcode will not use the result, delete the object.
@@ -98,78 +94,80 @@
 	 * as an operand later.
 	 */
 	switch (parent_info->class) {
-	/*
-	 * In these cases, the parent will never use the return object
-	 */
-	case AML_CLASS_CONTROL:        /* IF, ELSE, WHILE only */
+	case AML_CLASS_CONTROL:
 
 		switch (op->parent->opcode) {
 		case AML_RETURN_OP:
 
 			/* Never delete the return value associated with a return opcode */
 
-			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-				"Result used, [RETURN] opcode=%X Op=%p\n", op->opcode, op));
-			return_VALUE (TRUE);
-			break;
+			goto result_used;
 
 		case AML_IF_OP:
 		case AML_WHILE_OP:
 
 			/*
 			 * If we are executing the predicate AND this is the predicate op,
-			 * we will use the return value!
+			 * we will use the return value
 			 */
-			if ((walk_state->control_state->common.state == CONTROL_PREDICATE_EXECUTING) &&
+			if ((walk_state->control_state->common.state == ACPI_CONTROL_PREDICATE_EXECUTING) &&
 				(walk_state->control_state->control.predicate_op == op)) {
-				ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-					"Result used as a predicate, [IF/WHILE] opcode=%X Op=%p\n",
-					op->opcode, op));
-				return_VALUE (TRUE);
+				goto result_used;
 			}
-
-			break;
 		}
 
+		/* The general control opcode returns no result */
 
-		/* Fall through to not used case below */
+		goto result_not_used;
 
 
-	case AML_CLASS_NAMED_OBJECT:   /* Scope, method, etc. */
 	case AML_CLASS_CREATE:
 
 		/*
 		 * These opcodes allow Term_arg(s) as operands and therefore
-		 * method calls.  The result is used.
+		 * the operands can be method calls.  The result is used.
 		 */
-		if ((op->parent->opcode == AML_REGION_OP)               ||
-			(op->parent->opcode == AML_CREATE_FIELD_OP)         ||
-			(op->parent->opcode == AML_CREATE_BIT_FIELD_OP)     ||
-			(op->parent->opcode == AML_CREATE_BYTE_FIELD_OP)    ||
-			(op->parent->opcode == AML_CREATE_WORD_FIELD_OP)    ||
-			(op->parent->opcode == AML_CREATE_DWORD_FIELD_OP)   ||
-			(op->parent->opcode == AML_CREATE_QWORD_FIELD_OP)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-				"Result used, [Region or Create_field] opcode=%X Op=%p\n",
-				op->opcode, op));
-			return_VALUE (TRUE);
+		goto result_used;
+
+
+	case AML_CLASS_NAMED_OBJECT:
+
+		if ((op->parent->opcode == AML_REGION_OP)       ||
+			(op->parent->opcode == AML_DATA_REGION_OP)) {
+			/*
+			 * These opcodes allow Term_arg(s) as operands and therefore
+			 * the operands can be method calls.  The result is used.
+			 */
+			goto result_used;
 		}
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-			"Result not used, Parent opcode=%X Op=%p\n", op->opcode, op));
+		goto result_not_used;
 
-		return_VALUE (FALSE);
-		break;
 
 	/*
 	 * In all other cases. the parent will actually use the return
 	 * object, so keep it.
 	 */
 	default:
-		break;
+		goto result_used;
 	}
 
+
+result_used:
+	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Result of [%s] used by Parent [%s] Op=%p\n",
+			acpi_ps_get_opcode_name (op->opcode),
+			acpi_ps_get_opcode_name (op->parent->opcode), op));
+
 	return_VALUE (TRUE);
+
+
+result_not_used:
+	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Result of [%s] not used by Parent [%s] Op=%p\n",
+			acpi_ps_get_opcode_name (op->opcode),
+			acpi_ps_get_opcode_name (op->parent->opcode), op));
+
+	return_VALUE (FALSE);
+
 }
 
 
@@ -200,7 +198,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ds_delete_result_if_not_used", result_obj);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_delete_result_if_not_used", result_obj);
 
 
 	if (!op) {
@@ -252,16 +250,15 @@
 	acpi_status             status = AE_OK;
 	NATIVE_CHAR             *name_string;
 	u32                     name_length;
-	acpi_object_type8       data_type;
 	acpi_operand_object     *obj_desc;
 	acpi_parse_object       *parent_op;
 	u16                     opcode;
-	u32                     flags;
-	operating_mode          interpreter_mode;
+	acpi_interpreter_mode   interpreter_mode;
 	const acpi_opcode_info  *op_info;
+	char                    *name;
 
 
-	FUNCTION_TRACE_PTR ("Ds_create_operand", arg);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_create_operand", arg);
 
 
 	/* A valid name must be looked up in the namespace */
@@ -298,25 +295,20 @@
 			(parent_op->opcode != AML_INT_NAMEPATH_OP)) {
 			/* Enter name into namespace if not found */
 
-			interpreter_mode = IMODE_LOAD_PASS2;
+			interpreter_mode = ACPI_IMODE_LOAD_PASS2;
 		}
 
 		else {
 			/* Return a failure if name not found */
 
-			interpreter_mode = IMODE_EXECUTE;
+			interpreter_mode = ACPI_IMODE_EXECUTE;
 		}
 
 		status = acpi_ns_lookup (walk_state->scope_info, name_string,
 				 ACPI_TYPE_ANY, interpreter_mode,
-				 NS_SEARCH_PARENT | NS_DONT_OPEN_SCOPE,
+				 ACPI_NS_SEARCH_PARENT | ACPI_NS_DONT_OPEN_SCOPE,
 				 walk_state,
 				 (acpi_namespace_node **) &obj_desc);
-
-		/* Free the namestring created above */
-
-		ACPI_MEM_FREE (name_string);
-
 		/*
 		 * The only case where we pass through (ignore) a NOT_FOUND
 		 * error is for the Cond_ref_of opcode.
@@ -340,13 +332,18 @@
 				 */
 				status = AE_AML_NAME_NOT_FOUND;
 
-				/* TBD: Externalize Name_string and print */
-
+				name = NULL;
+				acpi_ns_externalize_name (ACPI_UINT32_MAX, name_string, NULL, &name);
 				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-						"Object name was not found in namespace\n"));
+						"Object name [%s] was not found in namespace\n", name));
+				ACPI_MEM_FREE (name);
 			}
 		}
 
+		/* Free the namestring created above */
+
+		ACPI_MEM_FREE (name_string);
+
 		/* Check status from the lookup */
 
 		if (ACPI_FAILURE (status)) {
@@ -359,7 +356,7 @@
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
-		DEBUGGER_EXEC (acpi_db_display_argument_object (obj_desc, walk_state));
+		ACPI_DEBUGGER_EXEC (acpi_db_display_argument_object (obj_desc, walk_state));
 	}
 
 
@@ -376,30 +373,25 @@
 			opcode = AML_ZERO_OP;       /* Has no arguments! */
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Null namepath: Arg=%p\n", arg));
-
-			/*
-			 * TBD: [Investigate] anything else needed for the
-			 * zero op lvalue?
-			 */
 		}
 
 		else {
 			opcode = arg->opcode;
 		}
 
+		/* Get the object type of the argument */
 
-		/* Get the data type of the argument */
-
-		data_type = acpi_ds_map_opcode_to_data_type (opcode, &flags);
-		if (data_type == INTERNAL_TYPE_INVALID) {
+		op_info = acpi_ps_get_opcode_info (opcode);
+		if (op_info->object_type == INTERNAL_TYPE_INVALID) {
 			return_ACPI_STATUS (AE_NOT_IMPLEMENTED);
 		}
 
-		if (flags & OP_HAS_RETURN_VALUE) {
+		if (op_info->flags & AML_HAS_RETVAL) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
 				"Argument previously created, already stacked \n"));
 
-			DEBUGGER_EXEC (acpi_db_display_argument_object (walk_state->operands [walk_state->num_operands - 1], walk_state));
+			ACPI_DEBUGGER_EXEC (acpi_db_display_argument_object (
+				walk_state->operands [walk_state->num_operands - 1], walk_state));
 
 			/*
 			 * Use value that was already previously returned
@@ -415,13 +407,12 @@
 					acpi_format_exception (status)));
 				return_ACPI_STATUS (status);
 			}
-
 		}
 
 		else {
 			/* Create an ACPI_INTERNAL_OBJECT for the argument */
 
-			obj_desc = acpi_ut_create_internal_object (data_type);
+			obj_desc = acpi_ut_create_internal_object (op_info->object_type);
 			if (!obj_desc) {
 				return_ACPI_STATUS (AE_NO_MEMORY);
 			}
@@ -443,7 +434,7 @@
 			return_ACPI_STATUS (status);
 		}
 
-		DEBUGGER_EXEC (acpi_db_display_argument_object (obj_desc, walk_state));
+		ACPI_DEBUGGER_EXEC (acpi_db_display_argument_object (obj_desc, walk_state));
 	}
 
 	return_ACPI_STATUS (AE_OK);
@@ -474,7 +465,7 @@
 	u32                     arg_count = 0;
 
 
-	FUNCTION_TRACE_PTR ("Ds_create_operands", first_arg);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_create_operands", first_arg);
 
 
 	/* For all arguments in the list... */
@@ -534,18 +525,13 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_PTR ("Ds_resolve_operands", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_resolve_operands", walk_state);
 
 
 	/*
 	 * Attempt to resolve each of the valid operands
 	 * Method arguments are passed by value, not by reference
 	 */
-
-	/*
-	 * TBD: [Investigate] Note from previous parser:
-	 *   Ref_of problem with Acpi_ex_resolve_to_value() conversion.
-	 */
 	for (i = 0; i < walk_state->num_operands; i++) {
 		status = acpi_ex_resolve_to_value (&walk_state->operands[i], walk_state);
 		if (ACPI_FAILURE (status)) {
@@ -555,264 +541,4 @@
 
 	return_ACPI_STATUS (status);
 }
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ds_map_opcode_to_data_type
- *
- * PARAMETERS:  Opcode          - AML opcode to map
- *              Out_flags       - Additional info about the opcode
- *
- * RETURN:      The ACPI type associated with the opcode
- *
- * DESCRIPTION: Convert a raw AML opcode to the associated ACPI data type,
- *              if any.  If the opcode returns a value as part of the
- *              intepreter execution, a flag is returned in Out_flags.
- *
- ******************************************************************************/
-
-acpi_object_type8
-acpi_ds_map_opcode_to_data_type (
-	u16                     opcode,
-	u32                     *out_flags)
-{
-	acpi_object_type8       data_type = INTERNAL_TYPE_INVALID;
-	const acpi_opcode_info  *op_info;
-	u32                     flags = 0;
-
-
-	PROC_NAME ("Ds_map_opcode_to_data_type");
-
-
-	op_info = acpi_ps_get_opcode_info (opcode);
-	if (op_info->class == AML_CLASS_UNKNOWN) {
-		/* Unknown opcode */
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown AML opcode: %x\n", opcode));
-		return (data_type);
-	}
-
-
-/*
- * TBD: Use op class
- */
-
-	switch (op_info->type) {
-
-	case AML_TYPE_LITERAL:
-
-		switch (opcode) {
-		case AML_BYTE_OP:
-		case AML_WORD_OP:
-		case AML_DWORD_OP:
-		case AML_QWORD_OP:
-
-			data_type = ACPI_TYPE_INTEGER;
-			break;
-
-
-		case AML_STRING_OP:
-
-			data_type = ACPI_TYPE_STRING;
-			break;
-
-		case AML_INT_NAMEPATH_OP:
-			data_type = INTERNAL_TYPE_REFERENCE;
-			break;
-
-		default:
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Unknown (type LITERAL) AML opcode: %x\n", opcode));
-			break;
-		}
-		break;
-
-
-	case AML_TYPE_DATA_TERM:
-
-		switch (opcode) {
-		case AML_BUFFER_OP:
-
-			data_type = ACPI_TYPE_BUFFER;
-			break;
-
-		case AML_PACKAGE_OP:
-		case AML_VAR_PACKAGE_OP:
-
-			data_type = ACPI_TYPE_PACKAGE;
-			break;
-
-		default:
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Unknown (type DATA_TERM) AML opcode: %x\n", opcode));
-			break;
-		}
-		break;
-
-
-	case AML_TYPE_CONSTANT:
-	case AML_TYPE_METHOD_ARGUMENT:
-	case AML_TYPE_LOCAL_VARIABLE:
-
-		data_type = INTERNAL_TYPE_REFERENCE;
-		break;
-
-
-	case AML_TYPE_EXEC_1A_0T_1R:
-	case AML_TYPE_EXEC_1A_1T_1R:
-	case AML_TYPE_EXEC_2A_0T_1R:
-	case AML_TYPE_EXEC_2A_1T_1R:
-	case AML_TYPE_EXEC_2A_2T_1R:
-	case AML_TYPE_EXEC_3A_1T_1R:
-	case AML_TYPE_EXEC_6A_0T_1R:
-	case AML_TYPE_RETURN:
-
-		flags = OP_HAS_RETURN_VALUE;
-		data_type = ACPI_TYPE_ANY;
-		break;
-
-
-	case AML_TYPE_METHOD_CALL:
-
-		flags = OP_HAS_RETURN_VALUE;
-		data_type = ACPI_TYPE_METHOD;
-		break;
-
-
-	case AML_TYPE_NAMED_FIELD:
-	case AML_TYPE_NAMED_SIMPLE:
-	case AML_TYPE_NAMED_COMPLEX:
-	case AML_TYPE_NAMED_NO_OBJ:
-
-		data_type = acpi_ds_map_named_opcode_to_data_type (opcode);
-		break;
-
-
-	case AML_TYPE_EXEC_1A_0T_0R:
-	case AML_TYPE_EXEC_2A_0T_0R:
-	case AML_TYPE_EXEC_3A_0T_0R:
-	case AML_TYPE_EXEC_1A_1T_0R:
-	case AML_TYPE_CONTROL:
-
-		/* No mapping needed at this time */
-
-		break;
-
-
-	default:
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-			"Unimplemented data type opcode: %x\n", opcode));
-		break;
-	}
-
-	/* Return flags to caller if requested */
-
-	if (out_flags) {
-		*out_flags = flags;
-	}
-
-	return (data_type);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ds_map_named_opcode_to_data_type
- *
- * PARAMETERS:  Opcode              - The Named AML opcode to map
- *
- * RETURN:      The ACPI type associated with the named opcode
- *
- * DESCRIPTION: Convert a raw Named AML opcode to the associated data type.
- *              Named opcodes are a subsystem of the AML opcodes.
- *
- ******************************************************************************/
-
-acpi_object_type8
-acpi_ds_map_named_opcode_to_data_type (
-	u16                     opcode)
-{
-	acpi_object_type8       data_type;
-
-
-	FUNCTION_ENTRY ();
-
-
-	/* Decode Opcode */
-
-	switch (opcode) {
-	case AML_SCOPE_OP:
-		data_type = INTERNAL_TYPE_SCOPE;
-		break;
-
-	case AML_DEVICE_OP:
-		data_type = ACPI_TYPE_DEVICE;
-		break;
-
-	case AML_THERMAL_ZONE_OP:
-		data_type = ACPI_TYPE_THERMAL;
-		break;
-
-	case AML_METHOD_OP:
-		data_type = ACPI_TYPE_METHOD;
-		break;
-
-	case AML_POWER_RES_OP:
-		data_type = ACPI_TYPE_POWER;
-		break;
-
-	case AML_PROCESSOR_OP:
-		data_type = ACPI_TYPE_PROCESSOR;
-		break;
-
-	case AML_FIELD_OP:                              /* Field_op */
-		data_type = INTERNAL_TYPE_FIELD_DEFN;
-		break;
-
-	case AML_INDEX_FIELD_OP:                        /* Index_field_op */
-		data_type = INTERNAL_TYPE_INDEX_FIELD_DEFN;
-		break;
-
-	case AML_BANK_FIELD_OP:                         /* Bank_field_op */
-		data_type = INTERNAL_TYPE_BANK_FIELD_DEFN;
-		break;
-
-	case AML_INT_NAMEDFIELD_OP:                     /* NO CASE IN ORIGINAL  */
-		data_type = ACPI_TYPE_ANY;
-		break;
-
-	case AML_NAME_OP:                               /* Name_op - special code in original */
-	case AML_INT_NAMEPATH_OP:
-		data_type = ACPI_TYPE_ANY;
-		break;
-
-	case AML_ALIAS_OP:
-		data_type = INTERNAL_TYPE_ALIAS;
-		break;
-
-	case AML_MUTEX_OP:
-		data_type = ACPI_TYPE_MUTEX;
-		break;
-
-	case AML_EVENT_OP:
-		data_type = ACPI_TYPE_EVENT;
-		break;
-
-	case AML_DATA_REGION_OP:
-	case AML_REGION_OP:
-		data_type = ACPI_TYPE_REGION;
-		break;
-
-
-	default:
-		data_type = ACPI_TYPE_ANY;
-		break;
-
-	}
-
-	return (data_type);
-}
-
 
diff -Nru a/drivers/acpi/dispatcher/dswexec.c b/drivers/acpi/dispatcher/dswexec.c
--- a/drivers/acpi/dispatcher/dswexec.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/dispatcher/dswexec.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: dswexec - Dispatcher method execution callbacks;
  *                        dispatch to interpreter.
- *              $Revision: 79 $
+ *              $Revision: 89 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,10 +35,10 @@
 
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dswexec")
+	 ACPI_MODULE_NAME    ("dswexec")
 
 /*
- * Dispatch tables for opcode classes
+ * Dispatch table for opcode classes
  */
 ACPI_EXECUTE_OP         acpi_gbl_op_type_dispatch [] = {
 			 acpi_ex_opcode_1A_0T_0R,
@@ -68,17 +68,17 @@
 acpi_status
 acpi_ds_get_predicate_value (
 	acpi_walk_state         *walk_state,
-	u32                     has_result_obj) {
+	acpi_operand_object     *result_obj) {
 	acpi_status             status = AE_OK;
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE_PTR ("Ds_get_predicate_value", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_get_predicate_value", walk_state);
 
 
 	walk_state->control_state->common.state = 0;
 
-	if (has_result_obj) {
+	if (result_obj) {
 		status = acpi_ds_result_pop (&obj_desc, walk_state);
 		if (ACPI_FAILURE (status)) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
@@ -88,7 +88,6 @@
 			return_ACPI_STATUS (status);
 		}
 	}
-
 	else {
 		status = acpi_ds_create_operand (walk_state, walk_state->op, 0);
 		if (ACPI_FAILURE (status)) {
@@ -110,7 +109,6 @@
 		return_ACPI_STATUS (AE_AML_NO_OPERAND);
 	}
 
-
 	/*
 	 * Result of predicate evaluation currently must
 	 * be a number
@@ -124,7 +122,6 @@
 		goto cleanup;
 	}
 
-
 	/* Truncate the predicate to 32-bits if necessary */
 
 	acpi_ex_truncate_for32bit_table (obj_desc, walk_state);
@@ -136,7 +133,6 @@
 	if (obj_desc->integer.value) {
 		walk_state->control_state->common.value = TRUE;
 	}
-
 	else {
 		/*
 		 * Predicate is FALSE, we will just toss the
@@ -149,12 +145,12 @@
 
 cleanup:
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Completed a predicate eval=%X Op=%pn",
+	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Completed a predicate eval=%X Op=%p\n",
 		walk_state->control_state->common.value, walk_state->op));
 
 	 /* Break to debugger to display result */
 
-	DEBUGGER_EXEC (acpi_db_display_result_object (obj_desc, walk_state));
+	ACPI_DEBUGGER_EXEC (acpi_db_display_result_object (obj_desc, walk_state));
 
 	/*
 	 * Delete the predicate result object (we know that
@@ -162,7 +158,7 @@
 	 */
 	acpi_ut_remove_reference (obj_desc);
 
-	walk_state->control_state->common.state = CONTROL_NORMAL;
+	walk_state->control_state->common.state = ACPI_CONTROL_NORMAL;
 	return_ACPI_STATUS (status);
 }
 
@@ -192,7 +188,7 @@
 	u32                     opcode_class;
 
 
-	FUNCTION_TRACE_PTR ("Ds_exec_begin_op", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_exec_begin_op", walk_state);
 
 
 	op = walk_state->op;
@@ -206,6 +202,12 @@
 		walk_state->op = op;
 		walk_state->op_info = acpi_ps_get_opcode_info (op->opcode);
 		walk_state->opcode = op->opcode;
+
+		if (acpi_ns_opens_scope (walk_state->op_info->object_type)) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "(%s) Popping scope for Op %p\n",
+				acpi_ut_get_type_name (walk_state->op_info->object_type), op));
+			acpi_ds_scope_stack_pop (walk_state);
+		}
 	}
 
 	if (op == walk_state->origin) {
@@ -223,11 +225,11 @@
 	 */
 	if ((walk_state->control_state) &&
 		(walk_state->control_state->common.state ==
-			CONTROL_CONDITIONAL_EXECUTING)) {
+			ACPI_CONTROL_CONDITIONAL_EXECUTING)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Exec predicate Op=%p State=%p\n",
 				  op, walk_state));
 
-		walk_state->control_state->common.state = CONTROL_PREDICATE_EXECUTING;
+		walk_state->control_state->common.state = ACPI_CONTROL_PREDICATE_EXECUTING;
 
 		/* Save start of predicate */
 
@@ -260,7 +262,7 @@
 
 	case AML_CLASS_NAMED_OBJECT:
 
-		if (walk_state->walk_type == WALK_METHOD) {
+		if (walk_state->walk_type == ACPI_WALK_METHOD) {
 			/*
 			 * Found a named object declaration during method
 			 * execution;  we must enter this object into the
@@ -271,19 +273,16 @@
 			status = acpi_ds_load2_begin_op (walk_state, NULL);
 		}
 
-
 		if (op->opcode == AML_REGION_OP) {
 			status = acpi_ds_result_stack_push (walk_state);
 		}
-
 		break;
 
 
-	/* most operators with arguments */
-
 	case AML_CLASS_EXECUTE:
 	case AML_CLASS_CREATE:
 
+		/* most operators with arguments */
 		/* Start a new result/operand state */
 
 		status = acpi_ds_result_stack_push (walk_state);
@@ -329,7 +328,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE_PTR ("Ds_exec_end_op", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_exec_end_op", walk_state);
 
 
 	op      = walk_state->op;
@@ -349,22 +348,19 @@
 	walk_state->return_desc = NULL;
 	walk_state->result_obj = NULL;
 
-
 	/* Call debugger for single step support (DEBUG build only) */
 
-	DEBUGGER_EXEC (status = acpi_db_single_step (walk_state, op, op_class));
-	DEBUGGER_EXEC (if (ACPI_FAILURE (status)) {return_ACPI_STATUS (status);});
-
+	ACPI_DEBUGGER_EXEC (status = acpi_db_single_step (walk_state, op, op_class));
+	ACPI_DEBUGGER_EXEC (if (ACPI_FAILURE (status)) {return_ACPI_STATUS (status);});
 
-	switch (op_class) {
 	/* Decode the Opcode Class */
 
-	case AML_CLASS_ARGUMENT: /* constants, literals, etc.  do nothing */
+	switch (op_class) {
+	case AML_CLASS_ARGUMENT:    /* constants, literals, etc. -- do nothing */
 		break;
 
-	/* most operators with arguments */
 
-	case AML_CLASS_EXECUTE:
+	case AML_CLASS_EXECUTE:     /* most operators with arguments */
 
 		/* Build resolved operand stack */
 
@@ -385,37 +381,26 @@
 		status = acpi_ex_resolve_operands (walk_state->opcode,
 				  &(walk_state->operands [walk_state->num_operands -1]),
 				  walk_state);
-		if (ACPI_FAILURE (status)) {
-			/* TBD: must pop and delete operands */
-
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "[%s]: Could not resolve operands, %s\n",
-				acpi_ps_get_opcode_name (walk_state->opcode), acpi_format_exception (status)));
+		if (ACPI_SUCCESS (status)) {
+			ACPI_DUMP_OPERANDS (ACPI_WALK_OPERANDS, ACPI_IMODE_EXECUTE,
+					  acpi_ps_get_opcode_name (walk_state->opcode),
+					  walk_state->num_operands, "after Ex_resolve_operands");
 
 			/*
-			 * On error, we must delete all the operands and clear the
-			 * operand stack
+			 * Dispatch the request to the appropriate interpreter handler
+			 * routine.  There is one routine per opcode "type" based upon the
+			 * number of opcode arguments and return type.
 			 */
-			for (i = 0; i < walk_state->num_operands; i++) {
-				acpi_ut_remove_reference (walk_state->operands[i]);
-				walk_state->operands[i] = NULL;
-			}
-
-			walk_state->num_operands = 0;
-			goto cleanup;
+			status = acpi_gbl_op_type_dispatch [op_type] (walk_state);
+		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"[%s]: Could not resolve operands, %s\n",
+				acpi_ps_get_opcode_name (walk_state->opcode),
+				acpi_format_exception (status)));
 		}
 
-		DUMP_OPERANDS (WALK_OPERANDS, IMODE_EXECUTE, acpi_ps_get_opcode_name (walk_state->opcode),
-				  walk_state->num_operands, "after Ex_resolve_operands");
-
-		/*
-		 * Dispatch the request to the appropriate interpreter handler
-		 * routine.  There is one routine per opcode "type" based upon the
-		 * number of opcode arguments and return type.
-		 */
-		status = acpi_gbl_op_type_dispatch [op_type] (walk_state);
-
-
-		/* Delete argument objects and clear the operand stack */
+		/* Always delete the argument objects and clear the operand stack */
 
 		for (i = 0; i < walk_state->num_operands; i++) {
 			/*
@@ -425,7 +410,6 @@
 			acpi_ut_remove_reference (walk_state->operands[i]);
 			walk_state->operands[i] = NULL;
 		}
-
 		walk_state->num_operands = 0;
 
 		/*
@@ -478,10 +462,9 @@
 			}
 
 			/*
-			 * Since the operands will be passed to another
-			 * control method, we must resolve all local
-			 * references here (Local variables, arguments
-			 * to *this* method, etc.)
+			 * Since the operands will be passed to another control method,
+			 * we must resolve all local references here (Local variables,
+			 * arguments to *this* method, etc.)
 			 */
 			status = acpi_ds_resolve_operands (walk_state);
 			if (ACPI_FAILURE (status)) {
@@ -499,7 +482,6 @@
 			 * especially the operand count!
 			 */
 			return_ACPI_STATUS (status);
-			break;
 
 
 		case AML_TYPE_CREATE_FIELD:
@@ -519,6 +501,7 @@
 		case AML_TYPE_NAMED_FIELD:
 		case AML_TYPE_NAMED_COMPLEX:
 		case AML_TYPE_NAMED_SIMPLE:
+		case AML_TYPE_NAMED_NO_OBJ:
 
 			status = acpi_ds_load2_end_op (walk_state);
 			if (ACPI_FAILURE (status)) {
@@ -539,18 +522,21 @@
 
 			break;
 
+
 		case AML_TYPE_UNDEFINED:
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Undefined opcode type Op=%p\n", op));
 			return_ACPI_STATUS (AE_NOT_IMPLEMENTED);
-			break;
 
 
 		case AML_TYPE_BOGUS:
-			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Internal opcode=%X type Op=%p\n",
+
+			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
+				"Internal opcode=%X type Op=%p\n",
 				walk_state->opcode, op));
 			break;
 
+
 		default:
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
@@ -563,8 +549,8 @@
 	}
 
 	/*
-	 * ACPI 2.0 support for 64-bit integers:
-	 * Truncate numeric result value if we are executing from a 32-bit ACPI table
+	 * ACPI 2.0 support for 64-bit integers: Truncate numeric
+	 * result value if we are executing from a 32-bit ACPI table
 	 */
 	acpi_ex_truncate_for32bit_table (walk_state->result_obj, walk_state);
 
@@ -575,9 +561,9 @@
 
 	if ((walk_state->control_state) &&
 		(walk_state->control_state->common.state ==
-			CONTROL_PREDICATE_EXECUTING) &&
+			ACPI_CONTROL_PREDICATE_EXECUTING) &&
 		(walk_state->control_state->control.predicate_op == op)) {
-		status = acpi_ds_get_predicate_value (walk_state, (u32) walk_state->result_obj);
+		status = acpi_ds_get_predicate_value (walk_state, walk_state->result_obj);
 		walk_state->result_obj = NULL;
 	}
 
@@ -586,7 +572,7 @@
 	if (walk_state->result_obj) {
 		/* Break to debugger to display result */
 
-		DEBUGGER_EXEC (acpi_db_display_result_object (walk_state->result_obj, walk_state));
+		ACPI_DEBUGGER_EXEC (acpi_db_display_result_object (walk_state->result_obj, walk_state));
 
 		/*
 		 * Delete the result op if and only if:
@@ -598,10 +584,7 @@
 
 	/* Always clear the object stack */
 
-	/* TBD: [Investigate] Clear stack of return value,
-	but don't delete it */
 	walk_state->num_operands = 0;
-
 	return_ACPI_STATUS (status);
 }
 
diff -Nru a/drivers/acpi/dispatcher/dswload.c b/drivers/acpi/dispatcher/dswload.c
--- a/drivers/acpi/dispatcher/dswload.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/dispatcher/dswload.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dswload - Dispatcher namespace load callbacks
- *              $Revision: 50 $
+ *              $Revision: 61 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
 
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dswload")
+	 ACPI_MODULE_NAME    ("dswload")
 
 
 /*******************************************************************************
@@ -77,7 +77,6 @@
 
 	default:
 		return (AE_BAD_PARAMETER);
-		break;
 	}
 
 	return (AE_OK);
@@ -106,16 +105,20 @@
 	acpi_parse_object       *op;
 	acpi_namespace_node     *node;
 	acpi_status             status;
-	acpi_object_type8       data_type;
+	acpi_object_type        object_type;
 	NATIVE_CHAR             *path;
 
 
-	PROC_NAME ("Ds_load1_begin_op");
+	ACPI_FUNCTION_NAME ("Ds_load1_begin_op");
 
 	op = walk_state->op;
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op=%p State=%p\n", op, walk_state));
 
 
+	if (op && (op->opcode == AML_INT_NAMEDFIELD_OP)) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op=%p State=%p\n", op, walk_state));
+	}
+
 	/* We are only interested in opcodes that have an associated name */
 
 	if (walk_state->op) {
@@ -136,25 +139,18 @@
 
 	/* Map the raw opcode into an internal object type */
 
-	data_type = acpi_ds_map_named_opcode_to_data_type (walk_state->opcode);
-
+	object_type = walk_state->op_info->object_type;
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-		"State=%p Op=%p Type=%x\n", walk_state, op, data_type));
-
-
-	if (walk_state->opcode == AML_SCOPE_OP) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-			"State=%p Op=%p Type=%x\n", walk_state, op, data_type));
-	}
+		"State=%p Op=%p Type=%x\n", walk_state, op, object_type));
 
 	/*
 	 * Enter the named type into the internal namespace.  We enter the name
 	 * as we go downward in the parse tree.  Any necessary subobjects that involve
 	 * arguments to the opcode must be created as we go back up the parse tree later.
 	 */
-	status = acpi_ns_lookup (walk_state->scope_info, path, data_type,
-			  IMODE_LOAD_PASS1, NS_NO_UPSEARCH, walk_state, &(node));
+	status = acpi_ns_lookup (walk_state->scope_info, path, object_type,
+			  ACPI_IMODE_LOAD_PASS1, ACPI_NS_NO_UPSEARCH, walk_state, &(node));
 
 	if (ACPI_FAILURE (status)) {
 		return (status);
@@ -205,10 +201,10 @@
 	acpi_walk_state         *walk_state)
 {
 	acpi_parse_object       *op;
-	acpi_object_type8       data_type;
+	acpi_object_type        object_type;
 
 
-	PROC_NAME ("Ds_load1_end_op");
+	ACPI_FUNCTION_NAME ("Ds_load1_end_op");
 
 	op = walk_state->op;
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op=%p State=%p\n", op, walk_state));
@@ -216,30 +212,44 @@
 
 	/* We are only interested in opcodes that have an associated name */
 
-	if (!(walk_state->op_info->flags & AML_NAMED)) {
+	if (!(walk_state->op_info->flags & (AML_NAMED | AML_FIELD))) {
+		return (AE_OK);
+	}
+
+	/* Get the object type to determine if we should pop the scope */
+
+	object_type = walk_state->op_info->object_type;
+
+	if (walk_state->op_info->flags & AML_FIELD) {
+		if (walk_state->opcode == AML_FIELD_OP         ||
+			walk_state->opcode == AML_BANK_FIELD_OP    ||
+			walk_state->opcode == AML_INDEX_FIELD_OP) {
+			acpi_ds_init_field_objects (op, walk_state);
+		}
 		return (AE_OK);
 	}
 
-	/* Get the type to determine if we should pop the scope */
 
-	data_type = acpi_ds_map_named_opcode_to_data_type (op->opcode);
+	if (op->opcode == AML_REGION_OP) {
+		/*Status = */acpi_ex_create_region (((acpi_parse2_object *) op)->data,
+				  ((acpi_parse2_object *) op)->length,
+						 (ACPI_ADR_SPACE_TYPE) ((op->value.arg)->value.integer), walk_state);
+	}
 
 	if (op->opcode == AML_NAME_OP) {
-		/* For Name opcode, check the argument */
+		/* For Name opcode, get the object type from the argument */
 
 		if (op->value.arg) {
-			data_type = acpi_ds_map_opcode_to_data_type (
-					  (op->value.arg)->opcode, NULL);
-			((acpi_namespace_node *)op->node)->type =
-					  (u8) data_type;
+			object_type = (acpi_ps_get_opcode_info ((op->value.arg)->opcode))->object_type;
+			op->node->type = (u8) object_type;
 		}
 	}
 
 	/* Pop the scope stack */
 
-	if (acpi_ns_opens_scope (data_type)) {
+	if (acpi_ns_opens_scope (object_type)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "(%s): Popping scope for Op %p\n",
-			acpi_ut_get_type_name (data_type), op));
+			acpi_ut_get_type_name (object_type), op));
 
 		acpi_ds_scope_stack_pop (walk_state);
 	}
@@ -270,28 +280,22 @@
 	acpi_parse_object       *op;
 	acpi_namespace_node     *node;
 	acpi_status             status;
-	acpi_object_type8       data_type;
+	acpi_object_type        object_type;
 	NATIVE_CHAR             *buffer_ptr;
 	void                    *original = NULL;
 
 
-	PROC_NAME ("Ds_load2_begin_op");
+	ACPI_FUNCTION_NAME ("Ds_load2_begin_op");
+
 
 	op = walk_state->op;
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op=%p State=%p\n", op, walk_state));
 
-
 	if (op) {
 		/* We only care about Namespace opcodes here */
 
-		if (!(walk_state->op_info->flags & AML_NSOPCODE) &&
-			walk_state->opcode != AML_INT_NAMEPATH_OP) {
-			return (AE_OK);
-		}
-
-		/* TBD: [Restructure] Temp! same code as in psparse */
-
-		if (!(walk_state->op_info->flags & AML_NAMED)) {
+		if ((!(walk_state->op_info->flags & AML_NSOPCODE) && (walk_state->opcode != AML_INT_NAMEPATH_OP)) ||
+			(!(walk_state->op_info->flags & AML_NAMED))) {
 			return (AE_OK);
 		}
 
@@ -315,16 +319,17 @@
 		}
 	}
 	else {
+		/* Get the namestring from the raw AML */
+
 		buffer_ptr = acpi_ps_get_next_namestring (&walk_state->parser_state);
 	}
 
+	/* Map the opcode into an internal object type */
 
-	/* Map the raw opcode into an internal object type */
-
-	data_type = acpi_ds_map_named_opcode_to_data_type (walk_state->opcode);
+	object_type = walk_state->op_info->object_type;
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
-		"State=%p Op=%p Type=%x\n", walk_state, op, data_type));
+		"State=%p Op=%p Type=%x\n", walk_state, op, object_type));
 
 
 	if (walk_state->opcode == AML_FIELD_OP         ||
@@ -333,23 +338,21 @@
 		node = NULL;
 		status = AE_OK;
 	}
-
 	else if (walk_state->opcode == AML_INT_NAMEPATH_OP) {
 		/*
 		 * The Name_path is an object reference to an existing object. Don't enter the
 		 * name into the namespace, but look it up for use later
 		 */
-		status = acpi_ns_lookup (walk_state->scope_info, buffer_ptr, data_type,
-				  IMODE_EXECUTE, NS_SEARCH_PARENT, walk_state, &(node));
+		status = acpi_ns_lookup (walk_state->scope_info, buffer_ptr, object_type,
+				  ACPI_IMODE_EXECUTE, ACPI_NS_SEARCH_PARENT, walk_state, &(node));
 	}
-
 	else {
 		if (op && op->node) {
 			original = op->node;
 			node = op->node;
 
-			if (acpi_ns_opens_scope (data_type)) {
-				status = acpi_ds_scope_stack_push (node, data_type, walk_state);
+			if (acpi_ns_opens_scope (object_type)) {
+				status = acpi_ds_scope_stack_push (node, object_type, walk_state);
 				if (ACPI_FAILURE (status)) {
 					return (status);
 				}
@@ -363,8 +366,8 @@
 		 * as we go downward in the parse tree.  Any necessary subobjects that involve
 		 * arguments to the opcode must be created as we go back up the parse tree later.
 		 */
-		status = acpi_ns_lookup (walk_state->scope_info, buffer_ptr, data_type,
-				  IMODE_EXECUTE, NS_NO_UPSEARCH, walk_state, &(node));
+		status = acpi_ns_lookup (walk_state->scope_info, buffer_ptr, object_type,
+				  ACPI_IMODE_EXECUTE, ACPI_NS_NO_UPSEARCH, walk_state, &(node));
 	}
 
 	if (ACPI_SUCCESS (status)) {
@@ -376,7 +379,7 @@
 				return (AE_NO_MEMORY);
 			}
 
-			/* Initialize */
+			/* Initialize the new op */
 
 			((acpi_parse2_object *)op)->name = node->name;
 			*out_op = op;
@@ -423,18 +426,18 @@
 {
 	acpi_parse_object       *op;
 	acpi_status             status = AE_OK;
-	acpi_object_type8       data_type;
+	acpi_object_type        object_type;
 	acpi_namespace_node     *node;
 	acpi_parse_object       *arg;
 	acpi_namespace_node     *new_node;
 	u32                     i;
 
 
-	PROC_NAME ("Ds_load2_end_op");
+	ACPI_FUNCTION_NAME ("Ds_load2_end_op");
 
 	op = walk_state->op;
-	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Op=%p State=%p\n", op, walk_state));
-
+	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Opcode [%s] Op %p State %p\n",
+			walk_state->op_info->name, op, walk_state));
 
 	/* Only interested in opcodes that have namespace objects */
 
@@ -446,7 +449,7 @@
 		ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
 			"Ending scope Op=%p State=%p\n", op, walk_state));
 
-		if (((acpi_parse2_object *)op)->name == -1) {
+		if (((acpi_parse2_object *)op)->name == ACPI_UINT16_MAX) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unnamed scope! Op=%p State=%p\n",
 				op, walk_state));
 			return (AE_OK);
@@ -454,7 +457,7 @@
 	}
 
 
-	data_type = acpi_ds_map_named_opcode_to_data_type (op->opcode);
+	object_type = walk_state->op_info->object_type;
 
 	/*
 	 * Get the Node/name from the earlier lookup
@@ -471,10 +474,9 @@
 
 	/* Pop the scope stack */
 
-	if (acpi_ns_opens_scope (data_type)) {
-
+	if (acpi_ns_opens_scope (object_type)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "(%s) Popping scope for Op %p\n",
-			acpi_ut_get_type_name (data_type), op));
+			acpi_ut_get_type_name (object_type), op));
 		acpi_ds_scope_stack_pop (walk_state);
 	}
 
@@ -527,7 +529,6 @@
 
 	 case AML_TYPE_NAMED_FIELD:
 
-		arg = op->value.arg;
 		switch (op->opcode) {
 		case AML_INDEX_FIELD_OP:
 
@@ -535,13 +536,11 @@
 					   walk_state);
 			break;
 
-
 		case AML_BANK_FIELD_OP:
 
 			status = acpi_ds_create_bank_field (op, arg->node, walk_state);
 			break;
 
-
 		case AML_FIELD_OP:
 
 			status = acpi_ds_create_field (op, arg->node, walk_state);
@@ -563,25 +562,21 @@
 			status = acpi_ex_create_processor (walk_state);
 			break;
 
-
 		case AML_POWER_RES_OP:
 
 			status = acpi_ex_create_power_resource (walk_state);
 			break;
 
-
 		case AML_MUTEX_OP:
 
 			status = acpi_ex_create_mutex (walk_state);
 			break;
 
-
 		case AML_EVENT_OP:
 
 			status = acpi_ex_create_event (walk_state);
 			break;
 
-
 		case AML_DATA_REGION_OP:
 
 			status = acpi_ex_create_table_region (walk_state);
@@ -597,7 +592,6 @@
 
 			status = AE_OK;
 			goto cleanup;
-			break;
 		}
 
 		/* Delete operands */
@@ -615,13 +609,13 @@
 		switch (op->opcode) {
 		case AML_METHOD_OP:
 			/*
-			 * Method_op Pkg_length Names_string Method_flags Term_list
+			 * Method_op Pkg_length Name_string Method_flags Term_list
 			 */
 			ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
 				"LOADING-Method: State=%p Op=%p Named_obj=%p\n",
 				walk_state, op, node));
 
-			if (!node->object) {
+			if (!acpi_ns_get_attached_object (node)) {
 				status = acpi_ds_create_operands (walk_state, arg);
 				if (ACPI_FAILURE (status)) {
 					goto cleanup;
@@ -639,9 +633,21 @@
 			 * The Op_region is not fully parsed at this time. Only valid argument is the Space_id.
 			 * (We must save the address of the AML of the address and length operands)
 			 */
-			status = acpi_ex_create_region (((acpi_parse2_object *) op)->data,
-					  ((acpi_parse2_object *) op)->length,
-							 (ACPI_ADR_SPACE_TYPE) arg->value.integer, walk_state);
+			/*
+			 * If we have a valid region, initialize it
+			 * Namespace is NOT locked at this point.
+			 */
+			status = acpi_ev_initialize_region (acpi_ns_get_attached_object (node), FALSE);
+			if (ACPI_FAILURE (status)) {
+				/*
+				 *  If AE_NOT_EXIST is returned, it is not fatal
+				 *  because many regions get created before a handler
+				 *  is installed for said region.
+				 */
+				if (AE_NOT_EXIST == status) {
+					status = AE_OK;
+				}
+			}
 			break;
 
 
@@ -669,14 +675,17 @@
 		 * Lookup the method name and save the Node
 		 */
 		status = acpi_ns_lookup (walk_state->scope_info, arg->value.string,
-				  ACPI_TYPE_ANY, IMODE_LOAD_PASS2,
-				  NS_SEARCH_PARENT | NS_DONT_OPEN_SCOPE,
+				  ACPI_TYPE_ANY, ACPI_IMODE_LOAD_PASS2,
+				  ACPI_NS_SEARCH_PARENT | ACPI_NS_DONT_OPEN_SCOPE,
 				  walk_state, &(new_node));
 		if (ACPI_SUCCESS (status)) {
-			/* TBD: has name already been resolved by here ??*/
-
-			/* TBD: [Restructure] Make sure that what we found is indeed a method! */
-			/* We didn't search for a method on purpose, to see if the name would resolve! */
+			/*
+			 * Make sure that what we found is indeed a method
+			 * We didn't search for a method on purpose, to see if the name would resolve
+			 */
+			if (new_node->type != ACPI_TYPE_METHOD) {
+				status = AE_AML_OPERAND_TYPE;
+			}
 
 			/* We could put the returned object (Node) on the object stack for later, but
 			 * for now, we will put it in the "op" object that the parser uses, so we
diff -Nru a/drivers/acpi/dispatcher/dswscope.c b/drivers/acpi/dispatcher/dswscope.c
--- a/drivers/acpi/dispatcher/dswscope.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/acpi/dispatcher/dswscope.c	Fri Mar 15 17:51:04 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dswscope - Scope stack manipulation
- *              $Revision: 49 $
+ *              $Revision: 52 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dswscope")
+	 ACPI_MODULE_NAME    ("dswscope")
 
 
 #define STACK_POP(head) head
@@ -53,7 +53,7 @@
 {
 	acpi_generic_state      *scope_info;
 
-	PROC_NAME ("Ds_scope_stack_clear");
+	ACPI_FUNCTION_NAME ("Ds_scope_stack_clear");
 
 
 	while (walk_state->scope_info) {
@@ -84,26 +84,26 @@
 acpi_status
 acpi_ds_scope_stack_push (
 	acpi_namespace_node     *node,
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_walk_state         *walk_state)
 {
 	acpi_generic_state      *scope_info;
 
 
-	FUNCTION_TRACE ("Ds_scope_stack_push");
+	ACPI_FUNCTION_TRACE ("Ds_scope_stack_push");
 
 
 	if (!node) {
 		/* Invalid scope   */
 
-		REPORT_ERROR (("Ds_scope_stack_push: null scope passed\n"));
+		ACPI_REPORT_ERROR (("Ds_scope_stack_push: null scope passed\n"));
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
 	/* Make sure object type is valid */
 
 	if (!acpi_ex_validate_object_type (type)) {
-		REPORT_WARNING (("Ds_scope_stack_push: type code out of range\n"));
+		ACPI_REPORT_WARNING (("Ds_scope_stack_push: type code out of range\n"));
 	}
 
 
@@ -152,7 +152,7 @@
 	acpi_generic_state      *scope_info;
 
 
-	FUNCTION_TRACE ("Ds_scope_stack_pop");
+	ACPI_FUNCTION_TRACE ("Ds_scope_stack_pop");
 
 
 	/*
diff -Nru a/drivers/acpi/dispatcher/dswstate.c b/drivers/acpi/dispatcher/dswstate.c
--- a/drivers/acpi/dispatcher/dswstate.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/dispatcher/dswstate.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: dswstate - Dispatcher parse tree walk management routines
- *              $Revision: 54 $
+ *              $Revision: 59 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_DISPATCHER
-	 MODULE_NAME         ("dswstate")
+	 ACPI_MODULE_NAME    ("dswstate")
 
 
 /*******************************************************************************
@@ -57,7 +57,7 @@
 	acpi_generic_state      *state;
 
 
-	PROC_NAME ("Ds_result_insert");
+	ACPI_FUNCTION_NAME ("Ds_result_insert");
 
 
 	state = walk_state->results;
@@ -116,7 +116,7 @@
 	acpi_generic_state      *state;
 
 
-	PROC_NAME ("Ds_result_remove");
+	ACPI_FUNCTION_NAME ("Ds_result_remove");
 
 
 	state = walk_state->results;
@@ -181,7 +181,7 @@
 	acpi_generic_state      *state;
 
 
-	PROC_NAME ("Ds_result_pop");
+	ACPI_FUNCTION_NAME ("Ds_result_pop");
 
 
 	state = walk_state->results;
@@ -241,7 +241,7 @@
 	acpi_generic_state      *state;
 
 
-	PROC_NAME ("Ds_result_pop_from_bottom");
+	ACPI_FUNCTION_NAME ("Ds_result_pop_from_bottom");
 
 
 	state = walk_state->results;
@@ -307,7 +307,7 @@
 	acpi_generic_state      *state;
 
 
-	PROC_NAME ("Ds_result_push");
+	ACPI_FUNCTION_NAME ("Ds_result_push");
 
 
 	state = walk_state->results;
@@ -360,7 +360,7 @@
 {
 	acpi_generic_state      *state;
 
-	PROC_NAME ("Ds_result_stack_push");
+	ACPI_FUNCTION_NAME ("Ds_result_stack_push");
 
 
 	state = acpi_ut_create_generic_state ();
@@ -396,7 +396,7 @@
 {
 	acpi_generic_state      *state;
 
-	PROC_NAME ("Ds_result_stack_pop");
+	ACPI_FUNCTION_NAME ("Ds_result_stack_pop");
 
 
 	/* Check for stack underflow */
@@ -440,7 +440,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE_PTR ("Ds_obj_stack_delete_all", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_obj_stack_delete_all", walk_state);
 
 
 	/* The stack size is configurable, but fixed */
@@ -474,7 +474,7 @@
 	void                    *object,
 	acpi_walk_state         *walk_state)
 {
-	PROC_NAME ("Ds_obj_stack_push");
+	ACPI_FUNCTION_NAME ("Ds_obj_stack_push");
 
 
 	/* Check for stack overflow */
@@ -519,7 +519,7 @@
 	acpi_operand_object     **object,
 	acpi_walk_state         *walk_state)
 {
-	PROC_NAME ("Ds_obj_stack_pop_object");
+	ACPI_FUNCTION_NAME ("Ds_obj_stack_pop_object");
 
 
 	/* Check for stack underflow */
@@ -580,7 +580,7 @@
 {
 	u32                     i;
 
-	PROC_NAME ("Ds_obj_stack_pop");
+	ACPI_FUNCTION_NAME ("Ds_obj_stack_pop");
 
 
 	for (i = 0; i < pop_count; i++) {
@@ -628,7 +628,7 @@
 	u32                     i;
 	acpi_operand_object     *obj_desc;
 
-	PROC_NAME ("Ds_obj_stack_pop_and_delete");
+	ACPI_FUNCTION_NAME ("Ds_obj_stack_pop_and_delete");
 
 
 	for (i = 0; i < pop_count; i++) {
@@ -679,7 +679,7 @@
 	acpi_walk_state         *walk_state)
 {
 
-	FUNCTION_TRACE_PTR ("Ds_obj_stack_get_value", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_obj_stack_get_value", walk_state);
 
 
 	/* Can't do it if the stack is empty */
@@ -704,31 +704,32 @@
  *
  * FUNCTION:    Acpi_ds_get_current_walk_state
  *
- * PARAMETERS:  Walk_list       - Get current active state for this walk list
+ * PARAMETERS:  Thread          - Get current active state for this Thread
  *
  * RETURN:      Pointer to the current walk state
  *
  * DESCRIPTION: Get the walk state that is at the head of the list (the "current"
- *              walk state.
+ *              walk state.)
  *
  ******************************************************************************/
 
 acpi_walk_state *
 acpi_ds_get_current_walk_state (
-	acpi_walk_list          *walk_list)
+	ACPI_THREAD_STATE       *thread)
 
 {
-	PROC_NAME ("Ds_get_current_walk_state");
+	ACPI_FUNCTION_NAME ("Ds_get_current_walk_state");
 
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_PARSE, "Ds_get_current_walk_state, =%p\n",
-		walk_list->walk_state));
-
-	if (!walk_list) {
+	if (!thread) {
 		return (NULL);
 	}
 
-	return (walk_list->walk_state);
+	ACPI_DEBUG_PRINT ((ACPI_DB_PARSE, "Ds_get_current_walk_state, =%p\n",
+		thread->walk_state_list));
+
+
+	return (thread->walk_state_list);
 }
 
 
@@ -748,13 +749,13 @@
 void
 acpi_ds_push_walk_state (
 	acpi_walk_state         *walk_state,
-	acpi_walk_list          *walk_list)
+	ACPI_THREAD_STATE       *thread)
 {
-	FUNCTION_TRACE ("Ds_push_walk_state");
+	ACPI_FUNCTION_TRACE ("Ds_push_walk_state");
 
 
-	walk_state->next    = walk_list->walk_state;
-	walk_list->walk_state = walk_state;
+	walk_state->next      = thread->walk_state_list;
+	thread->walk_state_list = walk_state;
 
 	return_VOID;
 }
@@ -776,25 +777,25 @@
 
 acpi_walk_state *
 acpi_ds_pop_walk_state (
-	acpi_walk_list          *walk_list)
+	ACPI_THREAD_STATE       *thread)
 {
 	acpi_walk_state         *walk_state;
 
 
-	FUNCTION_TRACE ("Ds_pop_walk_state");
+	ACPI_FUNCTION_TRACE ("Ds_pop_walk_state");
 
 
-	walk_state = walk_list->walk_state;
+	walk_state = thread->walk_state_list;
 
 	if (walk_state) {
 		/* Next walk state becomes the current walk state */
 
-		walk_list->walk_state = walk_state->next;
+		thread->walk_state_list = walk_state->next;
 
 		/*
 		 * Don't clear the NEXT field, this serves as an indicator
 		 * that there is a parent WALK STATE
-		 *     Walk_state->Next = NULL;
+		 *     NO: Walk_state->Next = NULL;
 		 */
 	}
 
@@ -807,12 +808,12 @@
  * FUNCTION:    Acpi_ds_create_walk_state
  *
  * PARAMETERS:  Origin          - Starting point for this walk
- *              Walk_list       - Owning walk list
+ *              Thread          - Current thread state
  *
  * RETURN:      Pointer to the new walk state.
  *
- * DESCRIPTION: Allocate and initialize a new walk state.  The current walk state
- *              is set to this new state.
+ * DESCRIPTION: Allocate and initialize a new walk state.  The current walk
+ *              state is set to this new state.
  *
  ******************************************************************************/
 
@@ -821,13 +822,13 @@
 	acpi_owner_id           owner_id,
 	acpi_parse_object       *origin,
 	acpi_operand_object     *mth_desc,
-	acpi_walk_list          *walk_list)
+	ACPI_THREAD_STATE       *thread)
 {
 	acpi_walk_state         *walk_state;
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ds_create_walk_state");
+	ACPI_FUNCTION_TRACE ("Ds_create_walk_state");
 
 
 	walk_state = acpi_ut_acquire_from_cache (ACPI_MEM_LIST_WALK);
@@ -839,7 +840,7 @@
 	walk_state->owner_id        = owner_id;
 	walk_state->origin          = origin;
 	walk_state->method_desc     = mth_desc;
-	walk_state->walk_list       = walk_list;
+	walk_state->thread          = thread;
 
 	/* Init the method args/local */
 
@@ -856,8 +857,8 @@
 
 	/* Put the new state at the head of the walk list */
 
-	if (walk_list) {
-		acpi_ds_push_walk_state (walk_state, walk_list);
+	if (thread) {
+		acpi_ds_push_walk_state (walk_state, thread);
 	}
 
 	return_PTR (walk_state);
@@ -892,7 +893,7 @@
 	acpi_parse_state        *parser_state = &walk_state->parser_state;
 
 
-	FUNCTION_TRACE ("Ds_init_aml_walk");
+	ACPI_FUNCTION_TRACE ("Ds_init_aml_walk");
 
 
 	walk_state->parser_state.aml    =
@@ -901,7 +902,6 @@
 	walk_state->parser_state.pkg_end = aml_start + aml_length;
 
 	/* The Next_op of the Next_walk will be the beginning of the method */
-	/* TBD: [Restructure] -- obsolete? */
 
 	walk_state->next_op             = NULL;
 	walk_state->params              = params;
@@ -914,7 +914,7 @@
 
 	if (method_node) {
 		walk_state->parser_state.start_node = method_node;
-		walk_state->walk_type               = WALK_METHOD;
+		walk_state->walk_type               = ACPI_WALK_METHOD;
 		walk_state->method_node             = method_node;
 		walk_state->method_desc             = acpi_ns_get_attached_object (method_node);
 
@@ -972,7 +972,7 @@
 	acpi_generic_state      *state;
 
 
-	FUNCTION_TRACE_PTR ("Ds_delete_walk_state", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ds_delete_walk_state", walk_state);
 
 
 	if (!walk_state) {
@@ -1038,7 +1038,7 @@
 acpi_ds_delete_walk_state_cache (
 	void)
 {
-	FUNCTION_TRACE ("Ds_delete_walk_state_cache");
+	ACPI_FUNCTION_TRACE ("Ds_delete_walk_state_cache");
 
 
 	acpi_ut_delete_generic_cache (ACPI_MEM_LIST_WALK);
diff -Nru a/drivers/acpi/driver.c b/drivers/acpi/driver.c
--- a/drivers/acpi/driver.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,217 +0,0 @@
-/*
- *  driver.c - ACPI driver
- *
- *  Copyright (C) 2000 Andrew Henroid
- *  Copyright (C) 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/*
- * Changes
- * David Woodhouse <dwmw2@redhat.com> 2000-12-6
- * - Fix interruptible_sleep_on() races
- * Andrew Grover <andrew.grover@intel.com> 2001-2-28
- * - Major revamping
- * Peter Breuer <ptb@it.uc3m.es> 2001-5-20
- * - parse boot time params.
- */
-
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-#include <linux/pm.h>
-#include <linux/acpi.h>
-#include <asm/uaccess.h>
-#include "acpi.h"
-
-
-#define _COMPONENT	OS_DEPENDENT
-	MODULE_NAME	("driver")
-
-FADT_DESCRIPTOR acpi_fadt;
-
-static int acpi_disabled = 0;
-
-enum acpi_blacklist_predicates
-{
-	all_versions,
-	less_than_or_equal,
-	equal,
-	greater_than_or_equal,
-};
-
-struct acpi_blacklist_item
-{
-	char oem_id[7];
-	char oem_table_id[9];
-	u32  oem_revision;
-	enum acpi_blacklist_predicates oem_revision_predicate;
-};
-
-/*
- * Currently, this blacklists based on items in the FADT. We may want to
- * expand this to using other ACPI tables in the future, too.
- */
-static struct acpi_blacklist_item acpi_blacklist[] __initdata = 
-{
-	{"TOSHIB", "750     ", 0x970814, less_than_or_equal}, /* Portege 7020, BIOS 8.10 */
-	{""}
-};
-
-int
-acpi_blacklisted(FADT_DESCRIPTOR *fadt)
-{
-	int i = 0;
-
-	while (acpi_blacklist[i].oem_id[0] != '\0')
-	{
-		if (strncmp(acpi_blacklist[i].oem_id, fadt->header.oem_id, 6)) {
-			i++;
-			continue;
-		}
-
-		if (strncmp(acpi_blacklist[i].oem_table_id, fadt->header.oem_table_id, 8)) {
-			i++;
-			continue;
-		}
-
-		if (acpi_blacklist[i].oem_revision_predicate == all_versions)
-			return TRUE;
-
-		if (acpi_blacklist[i].oem_revision_predicate == less_than_or_equal
-		    && fadt->header.oem_revision <= acpi_blacklist[i].oem_revision)
-			return TRUE;
-
-		if (acpi_blacklist[i].oem_revision_predicate == greater_than_or_equal
-		    && fadt->header.oem_revision >= acpi_blacklist[i].oem_revision)
-			return TRUE;
-
-		if (acpi_blacklist[i].oem_revision_predicate == equal
-		    && fadt->header.oem_revision == acpi_blacklist[i].oem_revision)
-			return TRUE;
-
-		i++;
-	}
-
-	return FALSE;
-}
-
-/*
- * Start the interpreter
- */
-int
-acpi_init(void)
-{
-	acpi_buffer		buffer;
-	acpi_system_info	sys_info;
-
-	if (PM_IS_ACTIVE()) {
-		printk(KERN_NOTICE "ACPI: APM is already active, exiting\n");
-		return -ENODEV;
-	}
-
-	if (acpi_disabled) {
-		printk(KERN_NOTICE "ACPI: disabled by cmdline, exiting\n");
-		return -ENODEV;
-	}
-
-	if (!ACPI_SUCCESS(acpi_initialize_subsystem())) {
-		printk(KERN_ERR "ACPI: Driver initialization failed\n");
-		return -ENODEV;
-	}
-
-	/* from this point on, on error we must call acpi_terminate() */
-	if (!ACPI_SUCCESS(acpi_load_tables())) {
-		printk(KERN_ERR "ACPI: System description table load failed\n");
-		acpi_terminate();
-		return -ENODEV;
-	}
-
-	/* get a separate copy of the FADT for use by other drivers */
-	memset(&acpi_fadt, 0, sizeof(acpi_fadt));
-	buffer.pointer = &acpi_fadt;
-	buffer.length = sizeof(acpi_fadt);
-
-	if (!ACPI_SUCCESS(acpi_get_table(ACPI_TABLE_FADT, 1, &buffer))) {
-		printk(KERN_ERR "ACPI: Could not get FADT\n");
-		acpi_terminate();
-		return -ENODEV;
-	}
-
-	if (acpi_blacklisted(&acpi_fadt)) {
-		printk(KERN_ERR "ACPI: On blacklist -- BIOS not fully ACPI compliant\n");
-		acpi_terminate();
-		return -ENODEV;
-	}
-
-	buffer.length  = sizeof(sys_info);
-	buffer.pointer = &sys_info;
-
-	if (!ACPI_SUCCESS (acpi_get_system_info(&buffer))) {
-		printk(KERN_ERR "ACPI: Could not get system info\n");
-		acpi_terminate();
-		return -ENODEV;
-	}
-
-	printk(KERN_INFO "ACPI: Core Subsystem version [%x]\n", sys_info.acpi_ca_version);
-
-	if (!ACPI_SUCCESS(acpi_enable_subsystem(ACPI_FULL_INITIALIZATION))) {
-		printk(KERN_ERR "ACPI: Subsystem enable failed\n");
-		acpi_terminate();
-		return -ENODEV;
-	}
-
-	printk(KERN_INFO "ACPI: Subsystem enabled\n");
-
-	pm_active = 1;
-
-	return 0;
-}
-
-/*
- * Terminate the interpreter
- */
-void
-acpi_exit(void)
-{
-	acpi_terminate();
-
-	pm_active = 0;
-
-	printk(KERN_ERR "ACPI: Subsystem disabled\n");
-}
-
-module_init(acpi_init);
-module_exit(acpi_exit);
-
-#ifndef MODULE
-static int __init acpi_setup(char *str) {
-	while (str && *str) {
-	if (strncmp(str, "off", 3) == 0)
-		acpi_disabled = 1;
-	str = strchr(str, ',');
-	if (str)
-		str += strspn(str, ", \t");
-	}
-	return 1;
-}
-
-__setup("acpi=", acpi_setup);
-#endif
diff -Nru a/drivers/acpi/events/Makefile b/drivers/acpi/events/Makefile
--- a/drivers/acpi/events/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/events/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/events/evevent.c b/drivers/acpi/events/evevent.c
--- a/drivers/acpi/events/evevent.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/events/evevent.c	Fri Mar 15 17:51:02 2002
@@ -1,13 +1,12 @@
 /******************************************************************************
  *
- * Module Name: evevent - Fixed and General Purpose Acpi_event
- *                          handling and dispatch
- *              $Revision: 51 $
+ * Module Name: evevent - Fixed and General Purpose Even handling and dispatch
+ *              $Revision: 71 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +29,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evevent")
+	 ACPI_MODULE_NAME    ("evevent")
 
 
 /*******************************************************************************
@@ -41,9 +40,7 @@
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Ensures that the system control interrupt (SCI) is properly
- *              configured, disables SCI event sources, installs the SCI
- *              handler
+ * DESCRIPTION: Initialize global data structures for events.
  *
  ******************************************************************************/
 
@@ -54,7 +51,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ev_initialize");
+	ACPI_FUNCTION_TRACE ("Ev_initialize");
 
 
 	/* Make sure we have ACPI tables */
@@ -64,17 +61,6 @@
 		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
 	}
 
-
-	/* Make sure the BIOS supports ACPI mode */
-
-	if (SYS_MODE_LEGACY == acpi_hw_get_mode_capabilities()) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "ACPI Mode is not supported!\n"));
-		return_ACPI_STATUS (AE_ERROR);
-	}
-
-
-	acpi_gbl_original_mode = acpi_hw_get_mode();
-
 	/*
 	 * Initialize the Fixed and General Purpose Acpi_events prior. This is
 	 * done prior to enabling SCIs to prevent interrupts from occuring
@@ -82,30 +68,63 @@
 	 */
 	status = acpi_ev_fixed_event_initialize ();
 	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Unable to initialize fixed events.\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL,
+				"Unable to initialize fixed events, %s\n",
+				acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
 
 	status = acpi_ev_gpe_initialize ();
 	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Unable to initialize general purpose events.\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL,
+				"Unable to initialize general purpose events, %s\n",
+				acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
 
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ev_handler_initialize
+ *
+ * PARAMETERS:  None
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Install handlers for the SCI, Global Lock, and GPEs.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ev_handler_initialize (
+	void)
+{
+	acpi_status             status;
+
+
+	ACPI_FUNCTION_TRACE ("Ev_initialize");
+
+
 	/* Install the SCI handler */
 
 	status = acpi_ev_install_sci_handler ();
 	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Unable to install System Control Interrupt Handler\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL,
+				"Unable to install System Control Interrupt Handler, %s\n",
+				acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
 
-
 	/* Install handlers for control method GPE handlers (_Lxx, _Exx) */
 
 	status = acpi_ev_init_gpe_control_methods ();
 	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Unable to initialize Gpe control methods\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL,
+				"Unable to initialize GPE control methods, %s\n",
+				acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
 
@@ -113,11 +132,12 @@
 
 	status = acpi_ev_init_global_lock_handler ();
 	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Unable to initialize Global Lock handler\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL,
+				"Unable to initialize Global Lock handler, %s\n",
+				acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -130,27 +150,32 @@
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Initialize the Fixed Acpi_event data structures
+ * DESCRIPTION: Install the fixed event handlers and enable the fixed events.
  *
  ******************************************************************************/
 
 acpi_status
-acpi_ev_fixed_event_initialize(void)
+acpi_ev_fixed_event_initialize (
+	void)
 {
-	int                     i = 0;
+	NATIVE_UINT             i;
 
-	/* Initialize the structure that keeps track of fixed event handlers */
 
+	/*
+	 * Initialize the structure that keeps track of fixed event handlers
+	 * and enable the fixed events.
+	 */
 	for (i = 0; i < ACPI_NUM_FIXED_EVENTS; i++) {
 		acpi_gbl_fixed_event_handlers[i].handler = NULL;
 		acpi_gbl_fixed_event_handlers[i].context = NULL;
-	}
 
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, TMR_EN, 0);
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, GBL_EN, 0);
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, PWRBTN_EN, 0);
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, SLPBTN_EN, 0);
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, RTC_EN, 0);
+		/* Enable the fixed event */
+
+		if (acpi_gbl_fixed_event_info[i].enable_register_id != 0xFF) {
+			acpi_hw_bit_register_write (acpi_gbl_fixed_event_info[i].enable_register_id,
+					 0, ACPI_MTX_LOCK);
+		}
+	}
 
 	return (AE_OK);
 }
@@ -169,54 +194,41 @@
  ******************************************************************************/
 
 u32
-acpi_ev_fixed_event_detect (void)
+acpi_ev_fixed_event_detect (
+	void)
 {
-	u32                     int_status = INTERRUPT_NOT_HANDLED;
-	u32                     status_register;
-	u32                     enable_register;
+	u32                     int_status = ACPI_INTERRUPT_NOT_HANDLED;
+	u32                     gpe_status;
+	u32                     gpe_enable;
+	NATIVE_UINT             i;
 
 
-	PROC_NAME ("Ev_fixed_event_detect");
+	ACPI_FUNCTION_NAME ("Ev_fixed_event_detect");
 
 
 	/*
 	 * Read the fixed feature status and enable registers, as all the cases
 	 * depend on their values.
 	 */
-	status_register = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_STS);
-	enable_register = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_EN);
+	gpe_status = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS);
+	gpe_enable = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_ENABLE);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INTERRUPTS,
 		"Fixed Acpi_event Block: Enable %08X Status %08X\n",
-		enable_register, status_register));
-
-
-	/* power management timer roll over */
-
-	if ((status_register & ACPI_STATUS_PMTIMER) &&
-		(enable_register & ACPI_ENABLE_PMTIMER)) {
-		int_status |= acpi_ev_fixed_event_dispatch (ACPI_EVENT_PMTIMER);
-	}
+		gpe_enable, gpe_status));
 
-	/* global event (BIOS wants the global lock) */
-
-	if ((status_register & ACPI_STATUS_GLOBAL) &&
-		(enable_register & ACPI_ENABLE_GLOBAL)) {
-		int_status |= acpi_ev_fixed_event_dispatch (ACPI_EVENT_GLOBAL);
-	}
-
-	/* power button event */
-
-	if ((status_register & ACPI_STATUS_POWER_BUTTON) &&
-		(enable_register & ACPI_ENABLE_POWER_BUTTON)) {
-		int_status |= acpi_ev_fixed_event_dispatch (ACPI_EVENT_POWER_BUTTON);
-	}
+	/*
+	 * Check for all possible Fixed Events and dispatch those that are active
+	 */
+	for (i = 0; i < ACPI_NUM_FIXED_EVENTS; i++) {
+		/* Both the status and enable bits must be on for this event */
 
-	/* sleep button event */
+		if ((gpe_status & acpi_gbl_fixed_event_info[i].status_bit_mask) &&
+			(gpe_enable & acpi_gbl_fixed_event_info[i].enable_bit_mask)) {
+			/* Found an active (signalled) event */
 
-	if ((status_register & ACPI_STATUS_SLEEP_BUTTON) &&
-		(enable_register & ACPI_ENABLE_SLEEP_BUTTON)) {
-		int_status |= acpi_ev_fixed_event_dispatch (ACPI_EVENT_SLEEP_BUTTON);
+			int_status |= acpi_ev_fixed_event_dispatch (i);
+		}
 	}
 
 	return (int_status);
@@ -240,60 +252,32 @@
 acpi_ev_fixed_event_dispatch (
 	u32                     event)
 {
-	u32                     register_id;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* Clear the status bit */
 
-	switch (event) {
-	case ACPI_EVENT_PMTIMER:
-		register_id = TMR_STS;
-		break;
-
-	case ACPI_EVENT_GLOBAL:
-		register_id = GBL_STS;
-		break;
-
-	case ACPI_EVENT_POWER_BUTTON:
-		register_id = PWRBTN_STS;
-		break;
-
-	case ACPI_EVENT_SLEEP_BUTTON:
-		register_id = SLPBTN_STS;
-		break;
-
-	case ACPI_EVENT_RTC:
-		register_id = RTC_STS;
-		break;
-
-	default:
-		return 0;
-		break;
-	}
-
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK, register_id, 1);
+	acpi_hw_bit_register_write (acpi_gbl_fixed_event_info[event].status_register_id,
+			 1, ACPI_MTX_DO_NOT_LOCK);
 
 	/*
 	 * Make sure we've got a handler.  If not, report an error.
 	 * The event is disabled to prevent further interrupts.
 	 */
 	if (NULL == acpi_gbl_fixed_event_handlers[event].handler) {
-		register_id = (PM1_EN | REGISTER_BIT_ID(register_id));
-
-		acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK,
-				 register_id, 0);
+		acpi_hw_bit_register_write (acpi_gbl_fixed_event_info[event].enable_register_id,
+				0, ACPI_MTX_DO_NOT_LOCK);
 
-		REPORT_ERROR (
+		ACPI_REPORT_ERROR (
 			("Ev_gpe_dispatch: No installed handler for fixed event [%08X]\n",
 			event));
 
-		return (INTERRUPT_NOT_HANDLED);
+		return (ACPI_INTERRUPT_NOT_HANDLED);
 	}
 
-	/* Invoke the handler */
+	/* Invoke the Fixed Event handler */
 
 	return ((acpi_gbl_fixed_event_handlers[event].handler)(
 			  acpi_gbl_fixed_event_handlers[event].context));
@@ -315,138 +299,171 @@
 acpi_status
 acpi_ev_gpe_initialize (void)
 {
-	u32                     i;
-	u32                     j;
-	u32                     register_index;
+	NATIVE_UINT             i;
+	NATIVE_UINT             j;
+	NATIVE_UINT             gpe_block;
+	u32                     gpe_register;
+	u32                     gpe_number_index;
 	u32                     gpe_number;
-	u16                     gpe0register_count;
-	u16                     gpe1_register_count;
+	ACPI_GPE_REGISTER_INFO  *gpe_register_info;
 
 
-	FUNCTION_TRACE ("Ev_gpe_initialize");
+	ACPI_FUNCTION_TRACE ("Ev_gpe_initialize");
+
 
 	/*
-	 * Set up various GPE counts
+	 * Initialize the GPE Block globals
 	 *
-	 * You may ask,why are the GPE register block lengths divided by 2?
-	 * From the ACPI 2.0 Spec, section, 4.7.1.6 General-Purpose Event
-	 * Registers, we have,
+	 * Why the GPE register block lengths divided by 2:  From the ACPI Spec,
+	 * section "General-Purpose Event Registers", we have:
 	 *
 	 * "Each register block contains two registers of equal length
-	 * GPEx_STS and GPEx_EN (where x is 0 or 1). The length of the
-	 * GPE0_STS and GPE0_EN registers is equal to half the GPE0_LEN
-	 * The length of the GPE1_STS and GPE1_EN registers is equal to
-	 * half the GPE1_LEN. If a generic register block is not supported
-	 * then its respective block pointer and block length values in the
-	 * FADT table contain zeros. The GPE0_LEN and GPE1_LEN do not need
-	 * to be the same size."
-	 */
-	gpe0register_count          = (u16) DIV_2 (acpi_gbl_FADT->gpe0blk_len);
-	gpe1_register_count         = (u16) DIV_2 (acpi_gbl_FADT->gpe1_blk_len);
-	acpi_gbl_gpe_register_count = gpe0register_count + gpe1_register_count;
+	 *  GPEx_STS and GPEx_EN (where x is 0 or 1). The length of the
+	 *  GPE0_STS and GPE0_EN registers is equal to half the GPE0_LEN
+	 *  The length of the GPE1_STS and GPE1_EN registers is equal to
+	 *  half the GPE1_LEN. If a generic register block is not supported
+	 *  then its respective block pointer and block length values in the
+	 *  FADT table contain zeros. The GPE0_LEN and GPE1_LEN do not need
+	 *  to be the same size."
+	 */
+	acpi_gbl_gpe_block_info[0].register_count = (u16) ACPI_DIV_2 (acpi_gbl_FADT->gpe0_blk_len);
+	acpi_gbl_gpe_block_info[1].register_count = (u16) ACPI_DIV_2 (acpi_gbl_FADT->gpe1_blk_len);
+
+	acpi_gbl_gpe_block_info[0].block_address = (u16) ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe0_blk.address);
+	acpi_gbl_gpe_block_info[1].block_address = (u16) ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address);
+
+	acpi_gbl_gpe_block_info[0].block_base_number = 0;
+	acpi_gbl_gpe_block_info[1].block_base_number = acpi_gbl_FADT->gpe1_base;
 
+	acpi_gbl_gpe_register_count = acpi_gbl_gpe_block_info[0].register_count +
+			 acpi_gbl_gpe_block_info[1].register_count;
 	if (!acpi_gbl_gpe_register_count) {
-		REPORT_WARNING (("Zero GPEs are defined in the FADT\n"));
+		ACPI_REPORT_WARNING (("Zero GPEs are defined in the FADT\n"));
 		return_ACPI_STATUS (AE_OK);
 	}
 
+	/* Determine the maximum GPE number for this machine */
+
+	acpi_gbl_gpe_number_max = ACPI_MUL_8 (acpi_gbl_gpe_block_info[0].register_count) - 1;
+
+	if (acpi_gbl_gpe_block_info[1].register_count) {
+		/* Check for GPE0/GPE1 overlap */
+
+		if (acpi_gbl_gpe_number_max >= acpi_gbl_FADT->gpe1_base) {
+			ACPI_REPORT_ERROR (("GPE0 block overlaps the GPE1 block\n"));
+			return_ACPI_STATUS (AE_BAD_VALUE);
+		}
+
+		/* GPE0 and GPE1 do not have to be contiguous in the GPE number space */
+
+		acpi_gbl_gpe_number_max = acpi_gbl_FADT->gpe1_base + (ACPI_MUL_8 (acpi_gbl_gpe_block_info[1].register_count) - 1);
+	}
+
+	/* Check for Max GPE number out-of-range */
+
+	if (acpi_gbl_gpe_number_max > ACPI_GPE_MAX) {
+		ACPI_REPORT_ERROR (("Maximum GPE number from FADT is too large: 0x%X\n", acpi_gbl_gpe_number_max));
+		return_ACPI_STATUS (AE_BAD_VALUE);
+	}
+
 	/*
-	 * Allocate the Gpe information block
+	 * Allocate the GPE number-to-index translation table
 	 */
-	acpi_gbl_gpe_registers = ACPI_MEM_CALLOCATE (acpi_gbl_gpe_register_count *
-			  sizeof (acpi_gpe_registers));
-	if (!acpi_gbl_gpe_registers) {
+	acpi_gbl_gpe_number_to_index = ACPI_MEM_CALLOCATE (sizeof (ACPI_GPE_INDEX_INFO) *
+			   (acpi_gbl_gpe_number_max + 1));
+	if (!acpi_gbl_gpe_number_to_index) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-			"Could not allocate the Gpe_registers block\n"));
+			"Could not allocate the Gpe_number_to_index table\n"));
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
+	/* Set the Gpe index table to GPE_INVALID */
+
+	ACPI_MEMSET (acpi_gbl_gpe_number_to_index, (int) ACPI_GPE_INVALID,
+			sizeof (ACPI_GPE_INDEX_INFO) * (acpi_gbl_gpe_number_max + 1));
+
 	/*
-	 * Allocate the Gpe dispatch handler block
-	 * There are eight distinct GP events per register.
-	 * Initialization to zeros is sufficient
-	 */
-	acpi_gbl_gpe_info = ACPI_MEM_CALLOCATE (MUL_8 (acpi_gbl_gpe_register_count) *
-			  sizeof (acpi_gpe_level_info));
-	if (!acpi_gbl_gpe_info) {
-		ACPI_MEM_FREE (acpi_gbl_gpe_registers);
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Could not allocate the Gpe_info block\n"));
-		return_ACPI_STATUS (AE_NO_MEMORY);
+	 * Allocate the GPE register information block
+	 */
+	acpi_gbl_gpe_register_info = ACPI_MEM_CALLOCATE (acpi_gbl_gpe_register_count *
+			  sizeof (ACPI_GPE_REGISTER_INFO));
+	if (!acpi_gbl_gpe_register_info) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+			"Could not allocate the Gpe_register_info table\n"));
+		goto error_exit1;
 	}
 
-	/* Set the Gpe validation table to GPE_INVALID */
-
-	MEMSET (acpi_gbl_gpe_valid, (int) ACPI_GPE_INVALID, ACPI_NUM_GPE);
+	/*
+	 * Allocate the GPE dispatch handler block.  There are eight distinct GPEs
+	 * per register.  Initialization to zeros is sufficient.
+	 */
+	acpi_gbl_gpe_number_info = ACPI_MEM_CALLOCATE (ACPI_MUL_8 (acpi_gbl_gpe_register_count) *
+			  sizeof (ACPI_GPE_NUMBER_INFO));
+	if (!acpi_gbl_gpe_number_info) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Could not allocate the Gpe_number_info table\n"));
+		goto error_exit2;
+	}
 
 	/*
-	 * Initialize the Gpe information and validation blocks.  A goal of these
-	 * blocks is to hide the fact that there are two separate GPE register sets
-	 * In a given block, the status registers occupy the first half, and
-	 * the enable registers occupy the second half.
+	 * Initialize the GPE information and validation tables.  A goal of these
+	 * tables is to hide the fact that there are two separate GPE register sets
+	 * in a given gpe hardware block, the status registers occupy the first half,
+	 * and the enable registers occupy the second half.  Another goal is to hide
+	 * the fact that there may be multiple GPE hardware blocks.
 	 */
+	gpe_register = 0;
+	gpe_number_index = 0;
 
-	/* GPE Block 0 */
+	for (gpe_block = 0; gpe_block < ACPI_MAX_GPE_BLOCKS; gpe_block++) {
+		for (i = 0; i < acpi_gbl_gpe_block_info[gpe_block].register_count; i++) {
+			gpe_register_info = &acpi_gbl_gpe_register_info[gpe_register];
 
-	register_index = 0;
+			/* Init the Register info for this entire GPE register (8 GPEs) */
 
-	for (i = 0; i < gpe0register_count; i++) {
-		acpi_gbl_gpe_registers[register_index].status_addr =
-				 (u16) (ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe0blk.address) + i);
+			gpe_register_info->base_gpe_number = (u8) (acpi_gbl_gpe_block_info[gpe_block].block_base_number + (ACPI_MUL_8 (i)));
+			gpe_register_info->status_addr = (u16) (acpi_gbl_gpe_block_info[gpe_block].block_address + i);
+			gpe_register_info->enable_addr = (u16) (acpi_gbl_gpe_block_info[gpe_block].block_address + i +
+					  acpi_gbl_gpe_block_info[gpe_block].register_count);
 
-		acpi_gbl_gpe_registers[register_index].enable_addr =
-				 (u16) (ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe0blk.address) + i + gpe0register_count);
+			/* Init the Index mapping info for each GPE number within this register */
 
-		acpi_gbl_gpe_registers[register_index].gpe_base = (u8) MUL_8 (i);
+			for (j = 0; j < 8; j++) {
+				gpe_number = gpe_register_info->base_gpe_number + j;
+				acpi_gbl_gpe_number_to_index[gpe_number].number_index = (u8) gpe_number_index;
 
-		for (j = 0; j < 8; j++) {
-			gpe_number = acpi_gbl_gpe_registers[register_index].gpe_base + j;
-			acpi_gbl_gpe_valid[gpe_number] = (u8) register_index;
-		}
+				acpi_gbl_gpe_number_info[gpe_number_index].bit_mask = acpi_gbl_decode_to8bit[j];
+				gpe_number_index++;
+			}
 
-		/*
-		 * Clear the status/enable registers.  Note that status registers
-		 * are cleared by writing a '1', while enable registers are cleared
-		 * by writing a '0'.
-		 */
-		acpi_os_write_port (acpi_gbl_gpe_registers[register_index].enable_addr, 0x00, 8);
-		acpi_os_write_port (acpi_gbl_gpe_registers[register_index].status_addr, 0xFF, 8);
+			/*
+			 * Clear the status/enable registers.  Note that status registers
+			 * are cleared by writing a '1', while enable registers are cleared
+			 * by writing a '0'.
+			 */
+			acpi_os_write_port (gpe_register_info->enable_addr, 0x00, 8);
+			acpi_os_write_port (gpe_register_info->status_addr, 0xFF, 8);
 
-		register_index++;
+			gpe_register++;
+		}
 	}
 
-	/* GPE Block 1 */
-
-	for (i = 0; i < gpe1_register_count; i++) {
-		acpi_gbl_gpe_registers[register_index].status_addr =
-				 (u16) (ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address) + i);
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "GPE registers: %X@%8.8X%8.8X (Blk0) %X@%8.8X%8.8X (Blk1)\n",
+		acpi_gbl_gpe_block_info[0].register_count,
+		ACPI_HIDWORD (acpi_gbl_FADT->Xgpe0_blk.address), ACPI_LODWORD (acpi_gbl_FADT->Xgpe0_blk.address),
+		acpi_gbl_gpe_block_info[1].register_count,
+		ACPI_HIDWORD (acpi_gbl_FADT->Xgpe1_blk.address), ACPI_LODWORD (acpi_gbl_FADT->Xgpe1_blk.address)));
 
-		acpi_gbl_gpe_registers[register_index].enable_addr =
-				 (u16) (ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address) + i + gpe1_register_count);
+	return_ACPI_STATUS (AE_OK);
 
-		acpi_gbl_gpe_registers[register_index].gpe_base =
-				 (u8) (acpi_gbl_FADT->gpe1_base + MUL_8 (i));
 
-		for (j = 0; j < 8; j++) {
-			gpe_number = acpi_gbl_gpe_registers[register_index].gpe_base + j;
-			acpi_gbl_gpe_valid[gpe_number] = (u8) register_index;
-		}
+	/* Error cleanup */
 
-		/*
-		 * Clear the status/enable registers.  Note that status registers
-		 * are cleared by writing a '1', while enable registers are cleared
-		 * by writing a '0'.
-		 */
-		acpi_os_write_port (acpi_gbl_gpe_registers[register_index].enable_addr, 0x00, 8);
-		acpi_os_write_port (acpi_gbl_gpe_registers[register_index].status_addr, 0xFF, 8);
+error_exit2:
+	ACPI_MEM_FREE (acpi_gbl_gpe_register_info);
 
-		register_index++;
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "GPE registers: %X@%8.8X%8.8X (Blk0) %X@%8.8X%8.8X (Blk1)\n",
-		gpe0register_count, HIDWORD(acpi_gbl_FADT->Xgpe0blk.address), LODWORD(acpi_gbl_FADT->Xgpe0blk.address),
-		gpe1_register_count, HIDWORD(acpi_gbl_FADT->Xgpe1_blk.address), LODWORD(acpi_gbl_FADT->Xgpe1_blk.address)));
-
-	return_ACPI_STATUS (AE_OK);
+error_exit1:
+	ACPI_MEM_FREE (acpi_gbl_gpe_number_to_index);
+	return_ACPI_STATUS (AE_NO_MEMORY);
 }
 
 
@@ -468,7 +485,7 @@
  *              Where:
  *                  L      - means that the GPE is level triggered
  *                  E      - means that the GPE is edge triggered
- *                  nn     - is the GPE number
+ *                  nn     - is the GPE number [in HEX]
  *
  ******************************************************************************/
 
@@ -480,28 +497,33 @@
 	void                    **return_value)
 {
 	u32                     gpe_number;
+	u32                     gpe_number_index;
 	NATIVE_CHAR             name[ACPI_NAME_SIZE + 1];
 	u8                      type;
 
 
-	PROC_NAME ("Ev_save_method_info");
+	ACPI_FUNCTION_NAME ("Ev_save_method_info");
 
 
 	/* Extract the name from the object and convert to a string */
 
-	MOVE_UNALIGNED32_TO_32 (name, &((acpi_namespace_node *) obj_handle)->name);
+	ACPI_MOVE_UNALIGNED32_TO_32 (name,
+			  &((acpi_namespace_node *) obj_handle)->name);
 	name[ACPI_NAME_SIZE] = 0;
 
 	/*
-	 * Edge/Level determination is based on the 2nd s8 of the method name
+	 * Edge/Level determination is based on the 2nd character of the method name
 	 */
-	if (name[1] == 'L') {
+	switch (name[1]) {
+	case 'L':
 		type = ACPI_EVENT_LEVEL_TRIGGERED;
-	}
-	else if (name[1] == 'E') {
+		break;
+
+	case 'E':
 		type = ACPI_EVENT_EDGE_TRIGGERED;
-	}
-	else {
+		break;
+
+	default:
 		/* Unknown method type, just ignore it! */
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
@@ -510,9 +532,9 @@
 		return (AE_OK);
 	}
 
-	/* Convert the last two characters of the name to the Gpe Number */
+	/* Convert the last two characters of the name to the GPE Number */
 
-	gpe_number = STRTOUL (&name[2], NULL, 16);
+	gpe_number = ACPI_STRTOUL (&name[2], NULL, 16);
 	if (gpe_number == ACPI_UINT32_MAX) {
 		/* Conversion failed; invalid method, just ignore it */
 
@@ -522,9 +544,10 @@
 		return (AE_OK);
 	}
 
-	/* Ensure that we have a valid GPE number */
+	/* Get GPE index and ensure that we have a valid GPE number */
 
-	if (acpi_gbl_gpe_valid[gpe_number] == ACPI_GPE_INVALID) {
+	gpe_number_index = acpi_ev_get_gpe_number_index (gpe_number);
+	if (gpe_number_index == ACPI_GPE_INVALID) {
 		/* Not valid, all we can do here is ignore it */
 
 		return (AE_OK);
@@ -534,9 +557,8 @@
 	 * Now we can add this information to the Gpe_info block
 	 * for use during dispatch of this GPE.
 	 */
-	acpi_gbl_gpe_info [gpe_number].type         = type;
-	acpi_gbl_gpe_info [gpe_number].method_handle = obj_handle;
-
+	acpi_gbl_gpe_number_info [gpe_number_index].type    = type;
+	acpi_gbl_gpe_number_info [gpe_number_index].method_handle = obj_handle;
 
 	/*
 	 * Enable the GPE (SCIs should be disabled at this point)
@@ -555,10 +577,9 @@
  *
  * PARAMETERS:  None
  *
- * RETURN:      None
+ * RETURN:      Status
  *
  * DESCRIPTION: Obtain the control methods associated with the GPEs.
- *
  *              NOTE: Must be called AFTER namespace initialization!
  *
  ******************************************************************************/
@@ -569,7 +590,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ev_init_gpe_control_methods");
+	ACPI_FUNCTION_TRACE ("Ev_init_gpe_control_methods");
 
 
 	/* Get a permanent handle to the _GPE object */
@@ -597,21 +618,23 @@
  *
  * RETURN:      INTERRUPT_HANDLED or INTERRUPT_NOT_HANDLED
  *
- * DESCRIPTION: Detect if any GP events have occurred
+ * DESCRIPTION: Detect if any GP events have occurred.  This function is
+ *              executed at interrupt level.
  *
  ******************************************************************************/
 
 u32
 acpi_ev_gpe_detect (void)
 {
-	u32                     int_status = INTERRUPT_NOT_HANDLED;
+	u32                     int_status = ACPI_INTERRUPT_NOT_HANDLED;
 	u32                     i;
 	u32                     j;
 	u8                      enabled_status_byte;
 	u8                      bit_mask;
+	ACPI_GPE_REGISTER_INFO  *gpe_register_info;
 
 
-	PROC_NAME ("Ev_gpe_detect");
+	ACPI_FUNCTION_NAME ("Ev_gpe_detect");
 
 
 	/*
@@ -620,23 +643,24 @@
 	 * Find all currently active GP events.
 	 */
 	for (i = 0; i < acpi_gbl_gpe_register_count; i++) {
-		acpi_os_read_port (acpi_gbl_gpe_registers[i].status_addr,
-				&acpi_gbl_gpe_registers[i].status, 8);
+		gpe_register_info = &acpi_gbl_gpe_register_info[i];
+
+		acpi_os_read_port (gpe_register_info->status_addr,
+				  &gpe_register_info->status, 8);
 
-		acpi_os_read_port (acpi_gbl_gpe_registers[i].enable_addr,
-				&acpi_gbl_gpe_registers[i].enable, 8);
+		acpi_os_read_port (gpe_register_info->enable_addr,
+				  &gpe_register_info->enable, 8);
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INTERRUPTS,
 			"GPE block at %X - Enable %08X Status %08X\n",
-			acpi_gbl_gpe_registers[i].enable_addr,
-			acpi_gbl_gpe_registers[i].status,
-			acpi_gbl_gpe_registers[i].enable));
+			gpe_register_info->enable_addr,
+			gpe_register_info->status,
+			gpe_register_info->enable));
 
 		/* First check if there is anything active at all in this register */
 
-		enabled_status_byte = (u8) (acpi_gbl_gpe_registers[i].status &
-				   acpi_gbl_gpe_registers[i].enable);
-
+		enabled_status_byte = (u8) (gpe_register_info->status &
+				   gpe_register_info->enable);
 		if (!enabled_status_byte) {
 			/* No active GPEs in this register, move on */
 
@@ -654,7 +678,7 @@
 				 * or method.
 				 */
 				int_status |= acpi_ev_gpe_dispatch (
-						  acpi_gbl_gpe_registers[i].gpe_base + j);
+						  gpe_register_info->base_gpe_number + j);
 			}
 		}
 	}
@@ -667,7 +691,7 @@
  *
  * FUNCTION:    Acpi_ev_asynch_execute_gpe_method
  *
- * PARAMETERS:  Gpe_number      - The 0-based Gpe number
+ * PARAMETERS:  Gpe_number      - The 0-based GPE number
  *
  * RETURN:      None
  *
@@ -679,38 +703,49 @@
  *
  ******************************************************************************/
 
-static void
+static void ACPI_SYSTEM_XFACE
 acpi_ev_asynch_execute_gpe_method (
 	void                    *context)
 {
-	u32                     gpe_number = (u32) context;
-	acpi_gpe_level_info     gpe_info;
+	u32                     gpe_number = (u32) ACPI_TO_INTEGER (context);
+	u32                     gpe_number_index;
+	ACPI_GPE_NUMBER_INFO    gpe_info;
 
 
-	FUNCTION_TRACE ("Ev_asynch_execute_gpe_method");
+	ACPI_FUNCTION_TRACE ("Ev_asynch_execute_gpe_method");
 
-	/*
-	 * Take a snapshot of the GPE info for this level
-	 */
-	acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
-	gpe_info = acpi_gbl_gpe_info [gpe_number];
-	acpi_ut_release_mutex (ACPI_MTX_EVENTS);
+
+	gpe_number_index = acpi_ev_get_gpe_number_index (gpe_number);
+	if (gpe_number_index == ACPI_GPE_INVALID) {
+		return_VOID;
+	}
 
 	/*
-	 * Method Handler (_Lxx, _Exx):
-	 * ----------------------------
-	 * Evaluate the _Lxx/_Exx control method that corresponds to this GPE.
+	 * Take a snapshot of the GPE info for this level - we copy the
+	 * info to prevent a race condition with Remove_handler.
 	 */
+	if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_EVENTS))) {
+		return_VOID;
+	}
+
+	gpe_info = acpi_gbl_gpe_number_info [gpe_number_index];
+	if (ACPI_FAILURE (acpi_ut_release_mutex (ACPI_MTX_EVENTS))) {
+		return_VOID;
+	}
+
 	if (gpe_info.method_handle) {
+		/*
+		 * Invoke the GPE Method (_Lxx, _Exx):
+		 * (Evaluate the _Lxx/_Exx control method that corresponds to this GPE.)
+		 */
 		acpi_ns_evaluate_by_handle (gpe_info.method_handle, NULL, NULL);
 	}
 
-	/*
-	 * Level-Triggered?
-	 * ----------------
-	 * If level-triggered we clear the GPE status bit after handling the event.
-	 */
 	if (gpe_info.type & ACPI_EVENT_LEVEL_TRIGGERED) {
+		/*
+		 * GPE is level-triggered, we clear the GPE status bit after handling
+		 * the event.
+		 */
 		acpi_hw_clear_gpe (gpe_number);
 	}
 
@@ -718,7 +753,6 @@
 	 * Enable the GPE.
 	 */
 	acpi_hw_enable_gpe (gpe_number);
-
 	return_VOID;
 }
 
@@ -727,18 +761,13 @@
  *
  * FUNCTION:    Acpi_ev_gpe_dispatch
  *
- * PARAMETERS:  Gpe_number      - The 0-based Gpe number
+ * PARAMETERS:  Gpe_number      - The 0-based GPE number
  *
  * RETURN:      INTERRUPT_HANDLED or INTERRUPT_NOT_HANDLED
  *
- * DESCRIPTION: Handle and dispatch a General Purpose Acpi_event.
- *              Clears the status bit for the requested event.
- *
- * TBD: [Investigate] is this still valid or necessary:
- * The Gpe handler differs from the fixed events in that it clears the enable
- * bit rather than the status bit to clear the interrupt.  This allows
- * software outside of interrupt context to determine what caused the SCI and
- * dispatch the correct AML.
+ * DESCRIPTION: Dispatch a General Purpose Event to either a function (e.g. EC)
+ *              or method (e.g. _Lxx/_Exx) handler.  This function executes
+ *              at interrupt level.
  *
  ******************************************************************************/
 
@@ -746,82 +775,79 @@
 acpi_ev_gpe_dispatch (
 	u32                     gpe_number)
 {
-	acpi_gpe_level_info     gpe_info;
+	u32                     gpe_number_index;
+	ACPI_GPE_NUMBER_INFO    *gpe_info;
 
 
-	FUNCTION_TRACE ("Ev_gpe_dispatch");
+	ACPI_FUNCTION_TRACE ("Ev_gpe_dispatch");
 
 
-	/*
-	 * Valid GPE number?
-	 */
-	if (acpi_gbl_gpe_valid[gpe_number] == ACPI_GPE_INVALID) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid GPE bit [%X].\n", gpe_number));
-		return_VALUE (INTERRUPT_NOT_HANDLED);
+	gpe_number_index = acpi_ev_get_gpe_number_index (gpe_number);
+	if (gpe_number_index == ACPI_GPE_INVALID) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid event, GPE[%X].\n", gpe_number));
+		return_VALUE (ACPI_INTERRUPT_NOT_HANDLED);
 	}
 
 	/*
-	 * Disable the GPE.
+	 * We don't have to worry about mutex on Gpe_info because we are
+	 * executing at interrupt level.
 	 */
-	acpi_hw_disable_gpe (gpe_number);
-
-	gpe_info = acpi_gbl_gpe_info [gpe_number];
+	gpe_info = &acpi_gbl_gpe_number_info [gpe_number_index];
 
 	/*
-	 * Edge-Triggered?
-	 * ---------------
 	 * If edge-triggered, clear the GPE status bit now.  Note that
 	 * level-triggered events are cleared after the GPE is serviced.
 	 */
-	if (gpe_info.type & ACPI_EVENT_EDGE_TRIGGERED) {
+	if (gpe_info->type & ACPI_EVENT_EDGE_TRIGGERED) {
 		acpi_hw_clear_gpe (gpe_number);
 	}
-		/*
-		 * Function Handler (e.g. EC)?
-		 */
-	if (gpe_info.handler) {
-		/* Invoke function handler (at interrupt level). */
-
-		gpe_info.handler (gpe_info.context);
 
-		/* Level-Triggered? */
-
-		if (gpe_info.type & ACPI_EVENT_LEVEL_TRIGGERED) {
-			acpi_hw_clear_gpe (gpe_number);
-		}
-
-		/* Enable GPE */
+	/*
+	 * Dispatch the GPE to either an installed handler, or the control
+	 * method associated with this GPE (_Lxx or _Exx).
+	 * If a handler exists, we invoke it and do not attempt to run the method.
+	 * If there is neither a handler nor a method, we disable the level to
+	 * prevent further events from coming in here.
+	 */
+	if (gpe_info->handler) {
+		/* Invoke the installed handler (at interrupt level) */
 
-		acpi_hw_enable_gpe (gpe_number);
+		gpe_info->handler (gpe_info->context);
 	}
+	else if (gpe_info->method_handle) {
+		/*
+		 * Execute the method associated with the GPE.
+		 */
+		if (ACPI_FAILURE (acpi_os_queue_for_execution (OSD_PRIORITY_GPE,
+				 acpi_ev_asynch_execute_gpe_method,
+				 ACPI_TO_POINTER (gpe_number)))) {
+			ACPI_REPORT_ERROR (("Acpi_ev_gpe_dispatch: Unable to queue handler for GPE[%X], disabling event\n", gpe_number));
 
-	/*
-	 * Method Handler (e.g. _Exx/_Lxx)?
-	 */
-	else if (gpe_info.method_handle) {
-		if (ACPI_FAILURE(acpi_os_queue_for_execution (OSD_PRIORITY_GPE,
-			acpi_ev_asynch_execute_gpe_method, (void*) gpe_number))) {
 			/*
-			 * Shoudn't occur, but if it does report an error. Note that
-			 * the GPE will remain disabled until the ACPI Core Subsystem
-			 * is restarted, or the handler is removed/reinstalled.
+			 * Disable the GPE on error.  The GPE will remain disabled until the ACPI
+			 * Core Subsystem is restarted, or the handler is reinstalled.
 			 */
-			REPORT_ERROR (("Acpi_ev_gpe_dispatch: Unable to queue handler for GPE bit [%X]\n", gpe_number));
+			acpi_hw_disable_gpe (gpe_number);
 		}
 	}
-
-	/*
-	 * No Handler? Report an error and leave the GPE disabled.
-	 */
 	else {
-		REPORT_ERROR (("Acpi_ev_gpe_dispatch: No installed handler for GPE [%X]\n", gpe_number));
+		/* No handler or method to run! */
 
-		/* Level-Triggered? */
+		ACPI_REPORT_ERROR (("Acpi_ev_gpe_dispatch: No handler or method for GPE[%X], disabling event\n", gpe_number));
 
-		if (gpe_info.type & ACPI_EVENT_LEVEL_TRIGGERED) {
-			acpi_hw_clear_gpe (gpe_number);
-		}
+		/*
+		 * Disable the GPE.  The GPE will remain disabled until the ACPI
+		 * Core Subsystem is restarted, or the handler is reinstalled.
+		 */
+		acpi_hw_disable_gpe (gpe_number);
+	}
+
+	/*
+	 * It is now safe to clear level-triggered evnets.
+	 */
+	if (gpe_info->type & ACPI_EVENT_LEVEL_TRIGGERED) {
+		acpi_hw_clear_gpe (gpe_number);
 	}
 
-	return_VALUE (INTERRUPT_HANDLED);
+	return_VALUE (ACPI_INTERRUPT_HANDLED);
 }
diff -Nru a/drivers/acpi/events/evmisc.c b/drivers/acpi/events/evmisc.c
--- a/drivers/acpi/events/evmisc.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/events/evmisc.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: evmisc - ACPI device notification handler dispatch
  *                       and ACPI Global Lock support
- *              $Revision: 35 $
+ *              $Revision: 47 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,59 @@
 #include "achware.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evmisc")
+	 ACPI_MODULE_NAME    ("evmisc")
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ev_get_gpe_register_index
+ *
+ * PARAMETERS:  Gpe_number      - Raw GPE number
+ *
+ * RETURN:      None.
+ *
+ * DESCRIPTION: Returns the register index (index into the GPE register info
+ *              table) associated with this GPE.
+ *
+ ******************************************************************************/
+
+u32
+acpi_ev_get_gpe_register_index (
+	u32                     gpe_number)
+{
+
+	if (gpe_number > acpi_gbl_gpe_number_max) {
+		return (ACPI_GPE_INVALID);
+	}
+
+	return (ACPI_DIV_8 (acpi_gbl_gpe_number_to_index[gpe_number].number_index));
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ev_get_gpe_number_index
+ *
+ * PARAMETERS:  Gpe_number      - Raw GPE number
+ *
+ * RETURN:      None.
+ *
+ * DESCRIPTION: Returns the number index (index into the GPE number info table)
+ *              associated with this GPE.
+ *
+ ******************************************************************************/
+
+u32
+acpi_ev_get_gpe_number_index (
+	u32                     gpe_number)
+{
+
+	if (gpe_number > acpi_gbl_gpe_number_max) {
+		return (ACPI_GPE_INVALID);
+	}
+
+	return (acpi_gbl_gpe_number_to_index[gpe_number].number_index);
+}
 
 
 /*******************************************************************************
@@ -58,7 +110,7 @@
 	acpi_status             status = AE_OK;
 
 
-	PROC_NAME ("Ev_queue_notify_request");
+	ACPI_FUNCTION_NAME ("Ev_queue_notify_request");
 
 
 	/*
@@ -92,18 +144,17 @@
 		break;
 	}
 
-
 	/*
 	 * Get the notify object attached to the device Node
 	 */
 	obj_desc = acpi_ns_get_attached_object (node);
 	if (obj_desc) {
-
 		/* We have the notify object, Get the right handler */
 
 		switch (node->type) {
 		case ACPI_TYPE_DEVICE:
-			if (notify_value <= MAX_SYS_NOTIFY) {
+
+			if (notify_value <= ACPI_MAX_SYS_NOTIFY) {
 				handler_obj = obj_desc->device.sys_handler;
 			}
 			else {
@@ -111,8 +162,10 @@
 			}
 			break;
 
+
 		case ACPI_TYPE_THERMAL:
-			if (notify_value <= MAX_SYS_NOTIFY) {
+
+			if (notify_value <= ACPI_MAX_SYS_NOTIFY) {
 				handler_obj = obj_desc->thermal_zone.sys_handler;
 			}
 			else {
@@ -122,13 +175,11 @@
 		}
 	}
 
-
 	/* If there is any handler to run, schedule the dispatcher */
 
-	if ((acpi_gbl_sys_notify.handler && (notify_value <= MAX_SYS_NOTIFY)) ||
-		(acpi_gbl_drv_notify.handler && (notify_value > MAX_SYS_NOTIFY)) ||
+	if ((acpi_gbl_sys_notify.handler && (notify_value <= ACPI_MAX_SYS_NOTIFY)) ||
+		(acpi_gbl_drv_notify.handler && (notify_value > ACPI_MAX_SYS_NOTIFY)) ||
 		handler_obj) {
-
 		notify_info = acpi_ut_create_generic_state ();
 		if (!notify_info) {
 			return (AE_NO_MEMORY);
@@ -169,7 +220,7 @@
  *
  ******************************************************************************/
 
-void
+void ACPI_SYSTEM_XFACE
 acpi_ev_notify_dispatch (
 	void                    *context)
 {
@@ -179,14 +230,14 @@
 	acpi_operand_object     *handler_obj;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
 	 * We will invoke a global notify handler if installed.
 	 * This is done _before_ we invoke the per-device handler attached to the device.
 	 */
-	if (notify_info->notify.value <= MAX_SYS_NOTIFY) {
+	if (notify_info->notify.value <= ACPI_MAX_SYS_NOTIFY) {
 		/* Global system notification handler */
 
 		if (acpi_gbl_sys_notify.handler) {
@@ -194,7 +245,6 @@
 			global_context = acpi_gbl_sys_notify.context;
 		}
 	}
-
 	else {
 		/* Global driver notification handler */
 
@@ -204,7 +254,6 @@
 		}
 	}
 
-
 	/* Invoke the system handler first, if present */
 
 	if (global_handler) {
@@ -237,7 +286,7 @@
  *
  ******************************************************************************/
 
-static void
+static void ACPI_SYSTEM_XFACE
 acpi_ev_global_lock_thread (
 	void                    *context)
 {
@@ -270,7 +319,6 @@
 	void                    *context)
 {
 	u8                      acquired = FALSE;
-	void                    *global_lock;
 
 
 	/*
@@ -278,8 +326,7 @@
 	 * If we don't get it now, it will be marked pending and we will
 	 * take another interrupt when it becomes free.
 	 */
-	global_lock = acpi_gbl_FACS->global_lock;
-	ACPI_ACQUIRE_GLOBAL_LOCK (global_lock, acquired);
+	ACPI_ACQUIRE_GLOBAL_LOCK (acpi_gbl_common_fACS.global_lock, acquired);
 	if (acquired) {
 		/* Got the lock, now wake all threads waiting for it */
 
@@ -291,7 +338,7 @@
 				  context);
 	}
 
-	return (INTERRUPT_HANDLED);
+	return (ACPI_INTERRUPT_HANDLED);
 }
 
 
@@ -311,7 +358,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ev_init_global_lock_handler");
+	ACPI_FUNCTION_TRACE ("Ev_init_global_lock_handler");
 
 
 	acpi_gbl_global_lock_present = TRUE;
@@ -320,7 +367,7 @@
 
 	/*
 	 * If the global lock does not exist on this platform, the attempt
-	 * to enable GBL_STS will fail (the GBL_EN bit will not stick)
+	 * to enable GBL_STATUS will fail (the GBL_ENABLE bit will not stick)
 	 * Map to AE_OK, but mark global lock as not present.
 	 * Any attempt to actually use the global lock will be flagged
 	 * with an error.
@@ -345,14 +392,15 @@
  *****************************************************************************/
 
 acpi_status
-acpi_ev_acquire_global_lock(void)
+acpi_ev_acquire_global_lock (
+	u32                     timeout)
 {
 	acpi_status             status = AE_OK;
 	u8                      acquired = FALSE;
-	void                    *global_lock;
 
 
-	FUNCTION_TRACE ("Ev_acquire_global_lock");
+	ACPI_FUNCTION_TRACE ("Ev_acquire_global_lock");
+
 
 	/* Make sure that we actually have a global lock */
 
@@ -364,46 +412,36 @@
 
 	acpi_gbl_global_lock_thread_count++;
 
-
-	/* If we (OS side) have the hardware lock already, we are done */
+	/* If we (OS side vs. BIOS side) have the hardware lock already, we are done */
 
 	if (acpi_gbl_global_lock_acquired) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
-	/* Only if the FACS is valid */
-
-	if (!acpi_gbl_FACS) {
-		return_ACPI_STATUS (AE_OK);
-	}
-
-
 	/* We must acquire the actual hardware lock */
 
-	global_lock = acpi_gbl_FACS->global_lock;
-	ACPI_ACQUIRE_GLOBAL_LOCK (global_lock, acquired);
+	ACPI_ACQUIRE_GLOBAL_LOCK (acpi_gbl_common_fACS.global_lock, acquired);
 	if (acquired) {
 	   /* We got the lock */
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Acquired the Global Lock\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Acquired the HW Global Lock\n"));
 
 		acpi_gbl_global_lock_acquired = TRUE;
 		return_ACPI_STATUS (AE_OK);
 	}
 
-
 	/*
 	 * Did not get the lock.  The pending bit was set above, and we must now
 	 * wait until we get the global lock released interrupt.
 	 */
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Waiting for the HW Global Lock\n"));
 
-	 /*
-	  * Acquire the global lock semaphore first.
-	  * Since this wait will block, we must release the interpreter
-	  */
+	/*
+	 * Acquire the global lock semaphore first.
+	 * Since this wait will block, we must release the interpreter
+	 */
 	status = acpi_ex_system_wait_semaphore (acpi_gbl_global_lock_semaphore,
-			  ACPI_UINT32_MAX);
+			  timeout);
 	return_ACPI_STATUS (status);
 }
 
@@ -420,41 +458,81 @@
 acpi_ev_release_global_lock (void)
 {
 	u8                      pending = FALSE;
-	void                    *global_lock;
 
 
-	FUNCTION_TRACE ("Ev_release_global_lock");
+	ACPI_FUNCTION_TRACE ("Ev_release_global_lock");
 
 
 	if (!acpi_gbl_global_lock_thread_count) {
-		REPORT_WARNING(("Global Lock has not be acquired, cannot release\n"));
+		ACPI_REPORT_WARNING(("Cannot release HW Global Lock, it has not been acquired\n"));
 		return_VOID;
 	}
 
-   /* One fewer thread has the global lock */
+	/* One fewer thread has the global lock */
 
 	acpi_gbl_global_lock_thread_count--;
+	if (acpi_gbl_global_lock_thread_count) {
+		/* There are still some threads holding the lock, cannot release */
+
+		return_VOID;
+	}
 
-	/* Have all threads released the lock? */
+	/*
+	 * No more threads holding lock, we can do the actual hardware
+	 * release
+	 */
+	ACPI_RELEASE_GLOBAL_LOCK (acpi_gbl_common_fACS.global_lock, pending);
+	acpi_gbl_global_lock_acquired = FALSE;
 
-	if (!acpi_gbl_global_lock_thread_count) {
-		/*
-		 * No more threads holding lock, we can do the actual hardware
-		 * release
-		 */
-		global_lock = acpi_gbl_FACS->global_lock;
-		ACPI_RELEASE_GLOBAL_LOCK (global_lock, pending);
-		acpi_gbl_global_lock_acquired = FALSE;
-
-		/*
-		 * If the pending bit was set, we must write GBL_RLS to the control
-		 * register
-		 */
-		if (pending) {
-			acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK,
-					 GBL_RLS, 1);
-		}
+	/*
+	 * If the pending bit was set, we must write GBL_RLS to the control
+	 * register
+	 */
+	if (pending) {
+		acpi_hw_bit_register_write (ACPI_BITREG_GLOBAL_LOCK_RELEASE, 1, ACPI_MTX_LOCK);
+	}
+
+	return_VOID;
+}
+
+
+/******************************************************************************
+ *
+ * FUNCTION:    Acpi_ev_terminate
+ *
+ * PARAMETERS:  none
+ *
+ * RETURN:      none
+ *
+ * DESCRIPTION: free memory allocated for table storage.
+ *
+ ******************************************************************************/
+
+void
+acpi_ev_terminate (void)
+{
+
+	ACPI_FUNCTION_TRACE ("Ev_terminate");
+
+
+	/*
+	 * Free global tables, etc.
+	 */
+	if (acpi_gbl_gpe_register_info) {
+		ACPI_MEM_FREE (acpi_gbl_gpe_register_info);
+		acpi_gbl_gpe_register_info = NULL;
+	}
+
+	if (acpi_gbl_gpe_number_info) {
+		ACPI_MEM_FREE (acpi_gbl_gpe_number_info);
+		acpi_gbl_gpe_number_info = NULL;
+	}
+
+	if (acpi_gbl_gpe_number_to_index) {
+		ACPI_MEM_FREE (acpi_gbl_gpe_number_to_index);
+		acpi_gbl_gpe_number_to_index = NULL;
 	}
 
 	return_VOID;
 }
+
diff -Nru a/drivers/acpi/events/evregion.c b/drivers/acpi/events/evregion.c
--- a/drivers/acpi/events/evregion.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/events/evregion.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: evregion - ACPI Address_space (Op_region) handler dispatch
- *              $Revision: 113 $
+ *              $Revision: 128 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 #include "amlcode.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evregion")
+	 ACPI_MODULE_NAME    ("evregion")
 
 
 /*******************************************************************************
@@ -53,7 +53,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ev_install_default_address_space_handlers");
+	ACPI_FUNCTION_TRACE ("Ev_install_default_address_space_handlers");
 
 
 	/*
@@ -68,40 +68,46 @@
 	 * space must be always available -- even though we are nowhere
 	 * near ready to find the PCI root buses at this point.
 	 *
-	 * NOTE: We ignore AE_EXIST because this means that a handler has
-	 * already been installed (via Acpi_install_address_space_handler)
+	 * NOTE: We ignore AE_ALREADY_EXISTS because this means that a handler
+	 * has already been installed (via Acpi_install_address_space_handler)
 	 */
-	status = acpi_install_address_space_handler (acpi_gbl_root_node,
+
+	status = acpi_install_address_space_handler ((acpi_handle) acpi_gbl_root_node,
 			   ACPI_ADR_SPACE_SYSTEM_MEMORY,
 			   ACPI_DEFAULT_HANDLER, NULL, NULL);
 	if ((ACPI_FAILURE (status)) &&
-		(status != AE_EXIST)) {
+		(status != AE_ALREADY_EXISTS)) {
 		return_ACPI_STATUS (status);
 	}
 
-	status = acpi_install_address_space_handler (acpi_gbl_root_node,
+	status = acpi_install_address_space_handler ((acpi_handle) acpi_gbl_root_node,
 			   ACPI_ADR_SPACE_SYSTEM_IO,
 			   ACPI_DEFAULT_HANDLER, NULL, NULL);
 	if ((ACPI_FAILURE (status)) &&
-		(status != AE_EXIST)) {
+		(status != AE_ALREADY_EXISTS)) {
 		return_ACPI_STATUS (status);
 	}
 
-	status = acpi_install_address_space_handler (acpi_gbl_root_node,
+	status = acpi_install_address_space_handler ((acpi_handle) acpi_gbl_root_node,
 			   ACPI_ADR_SPACE_PCI_CONFIG,
 			   ACPI_DEFAULT_HANDLER, NULL, NULL);
 	if ((ACPI_FAILURE (status)) &&
-		(status != AE_EXIST)) {
+		(status != AE_ALREADY_EXISTS)) {
 		return_ACPI_STATUS (status);
 	}
 
+	status = acpi_install_address_space_handler ((acpi_handle) acpi_gbl_root_node,
+			   ACPI_ADR_SPACE_DATA_TABLE,
+			   ACPI_DEFAULT_HANDLER, NULL, NULL);
+	if ((ACPI_FAILURE (status)) &&
+		(status != AE_ALREADY_EXISTS)) {
+		return_ACPI_STATUS (status);
+	}
 
 	return_ACPI_STATUS (AE_OK);
 }
 
 
-/* TBD: [Restructure] Move elsewhere */
-
 /*******************************************************************************
  *
  * FUNCTION:    Acpi_ev_execute_reg_method
@@ -121,13 +127,19 @@
 	u32                     function)
 {
 	acpi_operand_object    *params[3];
+	acpi_operand_object    *region_obj2;
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ev_execute_reg_method");
+	ACPI_FUNCTION_TRACE ("Ev_execute_reg_method");
 
 
-	if (region_obj->region.extra->extra.method_REG == NULL) {
+	region_obj2 = acpi_ns_get_secondary_object (region_obj);
+	if (!region_obj2) {
+		return_ACPI_STATUS (AE_NOT_EXIST);
+	}
+
+	if (region_obj2->extra.method_REG == NULL) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
@@ -161,8 +173,8 @@
 	/*
 	 *  Execute the method, no return value
 	 */
-	DEBUG_EXEC(acpi_ut_display_init_pathname (region_obj->region.extra->extra.method_REG, " [Method]"));
-	status = acpi_ns_evaluate_by_handle (region_obj->region.extra->extra.method_REG, params, NULL);
+	ACPI_DEBUG_EXEC(acpi_ut_display_init_pathname (region_obj2->extra.method_REG, " [Method]"));
+	status = acpi_ns_evaluate_by_handle (region_obj2->extra.method_REG, params, NULL);
 
 	acpi_ut_remove_reference (params[1]);
 
@@ -181,7 +193,7 @@
  *              Space_id            - ID of the address space (0-255)
  *              Function            - Read or Write operation
  *              Address             - Where in the space to read or write
- *              Bit_width           - Field width in bits (8, 16, or 32)
+ *              Bit_width           - Field width in bits (8, 16, 32, or 64)
  *              Value               - Pointer to in or out value
  *
  * RETURN:      Status
@@ -197,18 +209,24 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value)
+	acpi_integer            *value)
 {
 	acpi_status             status;
 	acpi_adr_space_handler  handler;
 	acpi_adr_space_setup    region_setup;
 	acpi_operand_object     *handler_desc;
+	acpi_operand_object     *region_obj2;
 	void                    *region_context = NULL;
 
 
-	FUNCTION_TRACE ("Ev_address_space_dispatch");
+	ACPI_FUNCTION_TRACE ("Ev_address_space_dispatch");
 
 
+	region_obj2 = acpi_ns_get_secondary_object (region_obj);
+	if (!region_obj2) {
+		return_ACPI_STATUS (AE_NOT_EXIST);
+	}
+
 	/*
 	 * Ensure that there is a handler associated with this region
 	 */
@@ -217,14 +235,14 @@
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "no handler for region(%p) [%s]\n",
 			region_obj, acpi_ut_get_region_name (region_obj->region.space_id)));
 
-		return_ACPI_STATUS(AE_NOT_EXIST);
+		return_ACPI_STATUS (AE_NOT_EXIST);
 	}
 
 	/*
 	 * It may be the case that the region has never been initialized
 	 * Some types of regions require special init code
 	 */
-	if (!(region_obj->region.flags & AOPOBJ_INITIALIZED)) {
+	if (!(region_obj->region.flags & AOPOBJ_SETUP_COMPLETE)) {
 		/*
 		 * This region has not been initialized yet, do it
 		 */
@@ -258,16 +276,16 @@
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Region Init: %s [%s]\n",
 				acpi_format_exception (status),
 				acpi_ut_get_region_name (region_obj->region.space_id)));
-			return_ACPI_STATUS(status);
+			return_ACPI_STATUS (status);
 		}
 
-		region_obj->region.flags |= AOPOBJ_INITIALIZED;
+		region_obj->region.flags |= AOPOBJ_SETUP_COMPLETE;
 
 		/*
 		 *  Save the returned context for use in all accesses to
 		 *  this particular region.
 		 */
-		region_obj->region.extra->extra.region_context = region_context;
+		region_obj2->extra.region_context = region_context;
 	}
 
 	/*
@@ -277,10 +295,10 @@
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_OPREGION,
 		"Addrhandler %p (%p), Address %8.8X%8.8X\n",
-		&region_obj->region.addr_handler->addr_handler, handler, HIDWORD(address),
-		LODWORD(address)));
+		&region_obj->region.addr_handler->addr_handler, handler,
+		ACPI_HIDWORD (address), ACPI_LODWORD (address)));
 
-	if (!(handler_desc->addr_handler.flags & ADDR_HANDLER_DEFAULT_INSTALLED)) {
+	if (!(handler_desc->addr_handler.flags & ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) {
 		/*
 		 *  For handlers other than the default (supplied) handlers, we must
 		 *  exit the interpreter because the handler *might* block -- we don't
@@ -294,15 +312,15 @@
 	 */
 	status = handler (function, address, bit_width, value,
 			 handler_desc->addr_handler.context,
-			 region_obj->region.extra->extra.region_context);
+			 region_obj2->extra.region_context);
 
 	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Region handler: %s [%s]\n",
-			acpi_format_exception (status),
-			acpi_ut_get_region_name (region_obj->region.space_id)));
+		ACPI_REPORT_ERROR (("Handler for [%s] returned %s\n",
+			acpi_ut_get_region_name (region_obj->region.space_id),
+			acpi_format_exception (status)));
 	}
 
-	if (!(handler_desc->addr_handler.flags & ADDR_HANDLER_DEFAULT_INSTALLED)) {
+	if (!(handler_desc->addr_handler.flags & ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) {
 		/*
 		 * We just returned from a non-default handler, we must re-enter the
 		 * interpreter
@@ -337,13 +355,18 @@
 	acpi_operand_object     **last_obj_ptr;
 	acpi_adr_space_setup    region_setup;
 	void                    *region_context;
+	acpi_operand_object     *region_obj2;
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ev_disassociate_region_from_handler");
+	ACPI_FUNCTION_TRACE ("Ev_disassociate_region_from_handler");
 
 
-	region_context = region_obj->region.extra->extra.region_context;
+	region_obj2 = acpi_ns_get_secondary_object (region_obj);
+	if (!region_obj2) {
+		return;
+	}
+	region_context = region_obj2->extra.region_context;
 
 	/*
 	 *  Get the address handler from the region object
@@ -378,7 +401,10 @@
 			obj_desc->region.next = NULL;           /* Must clear field */
 
 			if (acpi_ns_is_locked) {
-				acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+				status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+				if (ACPI_FAILURE (status)) {
+					return_VOID;
+				}
 			}
 
 			/*
@@ -387,7 +413,10 @@
 			acpi_ev_execute_reg_method (region_obj, 0);
 
 			if (acpi_ns_is_locked) {
-				acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+				status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+				if (ACPI_FAILURE (status)) {
+					return_VOID;
+				}
 			}
 
 			/*
@@ -406,7 +435,7 @@
 					acpi_ut_get_region_name (region_obj->region.space_id)));
 			}
 
-			region_obj->region.flags &= ~(AOPOBJ_INITIALIZED);
+			region_obj->region.flags &= ~(AOPOBJ_SETUP_COMPLETE);
 
 			/*
 			 *  Remove handler reference in the region
@@ -466,7 +495,7 @@
 	acpi_status     status;
 
 
-	FUNCTION_TRACE ("Ev_associate_region_and_handler");
+	ACPI_FUNCTION_TRACE ("Ev_associate_region_and_handler");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_OPREGION,
@@ -475,18 +504,19 @@
 
 
 	/*
-	 *  Link this region to the front of the handler's list
+	 * Link this region to the front of the handler's list
 	 */
 	region_obj->region.next = handler_obj->addr_handler.region_list;
 	handler_obj->addr_handler.region_list = region_obj;
 
 	/*
-	 *  set the region's handler
+	 * Set the region's handler
 	 */
 	region_obj->region.addr_handler = handler_obj;
 
 	/*
-	 *  Last thing, tell all users that this region is usable
+	 * Tell all users that this region is usable by running the _REG
+	 * method
 	 */
 	if (acpi_ns_is_locked) {
 		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
@@ -495,7 +525,7 @@
 	status = acpi_ev_execute_reg_method (region_obj, 1);
 
 	if (acpi_ns_is_locked) {
-		acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+		(void) acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
 	}
 
 	return_ACPI_STATUS (status);
@@ -510,8 +540,8 @@
  *              Level               - Nesting level of the handle
  *              Context             - Passed into Acpi_ns_walk_namespace
  *
- * DESCRIPTION: This routine checks to see if the object is a Region if it
- *              is then the address handler is installed in it.
+ * DESCRIPTION: This routine installs an address handler into objects that are
+ *              of type Region.
  *
  *              If the Object is a Device, and the device has a handler of
  *              the same type then the search is terminated in that branch.
@@ -535,7 +565,7 @@
 	acpi_status             status;
 
 
-	PROC_NAME ("Ev_addr_handler_helper");
+	ACPI_FUNCTION_NAME ("Ev_addr_handler_helper");
 
 
 	handler_obj = (acpi_operand_object *) context;
@@ -576,7 +606,7 @@
 	/*
 	 *  Devices are handled different than regions
 	 */
-	if (IS_THIS_OBJECT_TYPE (obj_desc, ACPI_TYPE_DEVICE)) {
+	if (obj_desc->common.type == ACPI_TYPE_DEVICE) {
 		/*
 		 *  See if this guy has any handlers
 		 */
diff -Nru a/drivers/acpi/events/evrgnini.c b/drivers/acpi/events/evrgnini.c
--- a/drivers/acpi/events/evrgnini.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/events/evrgnini.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: evrgnini- ACPI Address_space (Op_region) init
- *              $Revision: 48 $
+ *              $Revision: 57 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 #include "amlcode.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evrgnini")
+	 ACPI_MODULE_NAME    ("evrgnini")
 
 
 /*******************************************************************************
@@ -56,7 +56,10 @@
 	void                    *handler_context,
 	void                    **region_context)
 {
-	FUNCTION_TRACE ("Ev_system_memory_region_setup");
+	acpi_operand_object     *region_desc = (acpi_operand_object *) handle;
+	acpi_mem_space_context  *local_region_context;
+
+	ACPI_FUNCTION_TRACE ("Ev_system_memory_region_setup");
 
 
 	if (function == ACPI_REGION_DEACTIVATE) {
@@ -70,11 +73,17 @@
 
 	/* Activate.  Create a new context */
 
-	*region_context = ACPI_MEM_CALLOCATE (sizeof (acpi_mem_space_context));
-	if (!(*region_context)) {
+	local_region_context = ACPI_MEM_CALLOCATE (sizeof (acpi_mem_space_context));
+	if (!(local_region_context)) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
+	/* Save the region length and address for use in the handler */
+
+	local_region_context->length = region_desc->region.length;
+	local_region_context->address = region_desc->region.address;
+
+	*region_context = local_region_context;
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -101,7 +110,7 @@
 	void                    *handler_context,
 	void                    **region_context)
 {
-	FUNCTION_TRACE ("Ev_io_space_region_setup");
+	ACPI_FUNCTION_TRACE ("Ev_io_space_region_setup");
 
 
 	if (function == ACPI_REGION_DEACTIVATE) {
@@ -148,7 +157,7 @@
 	acpi_device_id          object_hID;
 
 
-	FUNCTION_TRACE ("Ev_pci_config_region_setup");
+	ACPI_FUNCTION_TRACE ("Ev_pci_config_region_setup");
 
 
 	handler_obj = region_obj->region.addr_handler;
@@ -188,7 +197,7 @@
 	 *  First get device and function numbers from the _ADR object
 	 *  in the parent's scope.
 	 */
-	node = acpi_ns_get_parent_object (region_obj->region.node);
+	node = acpi_ns_get_parent_node (region_obj->region.node);
 
 
 	/* Acpi_evaluate the _ADR object */
@@ -200,8 +209,8 @@
 	 *  do nothing on failures.
 	 */
 	if (ACPI_SUCCESS (status)) {
-		pci_id->device = HIWORD (temp);
-		pci_id->function = LOWORD (temp);
+		pci_id->device  = ACPI_HIWORD (temp);
+		pci_id->function = ACPI_LOWORD (temp);
 	}
 
 	/*
@@ -224,16 +233,16 @@
 		while (node != acpi_gbl_root_node) {
 			status = acpi_ut_execute_HID (node, &object_hID);
 			if (ACPI_SUCCESS (status)) {
-				if (!(STRNCMP (object_hID.buffer, PCI_ROOT_HID_STRING,
+				if (!(ACPI_STRNCMP (object_hID.buffer, PCI_ROOT_HID_STRING,
 						   sizeof (PCI_ROOT_HID_STRING)))) {
-					acpi_install_address_space_handler (node,
+					acpi_install_address_space_handler ((acpi_handle) node,
 							   ACPI_ADR_SPACE_PCI_CONFIG,
 							   ACPI_DEFAULT_HANDLER, NULL, NULL);
 					break;
 				}
 			}
 
-			node = acpi_ns_get_parent_object (node);
+			node = acpi_ns_get_parent_node (node);
 		}
 	}
 	else {
@@ -245,7 +254,7 @@
 	 */
 	status = acpi_ut_evaluate_numeric_object (METHOD_NAME__SEG, node, &temp);
 	if (ACPI_SUCCESS (status)) {
-		pci_id->segment = LOWORD (temp);
+		pci_id->segment = ACPI_LOWORD (temp);
 	}
 
 	/*
@@ -253,7 +262,7 @@
 	 */
 	status = acpi_ut_evaluate_numeric_object (METHOD_NAME__BBN, node, &temp);
 	if (ACPI_SUCCESS (status)) {
-		pci_id->bus = LOWORD (temp);
+		pci_id->bus = ACPI_LOWORD (temp);
 	}
 
 	*region_context = pci_id;
@@ -286,7 +295,7 @@
 	void                    **region_context)
 {
 
-	FUNCTION_TRACE ("Ev_pci_bar_region_setup");
+	ACPI_FUNCTION_TRACE ("Ev_pci_bar_region_setup");
 
 
 	return_ACPI_STATUS (AE_OK);
@@ -318,7 +327,7 @@
 	void                    **region_context)
 {
 
-	FUNCTION_TRACE ("Ev_cmos_region_setup");
+	ACPI_FUNCTION_TRACE ("Ev_cmos_region_setup");
 
 
 	return_ACPI_STATUS (AE_OK);
@@ -347,7 +356,7 @@
 	void                    *handler_context,
 	void                    **region_context)
 {
-	FUNCTION_TRACE ("Ev_default_region_setup");
+	ACPI_FUNCTION_TRACE ("Ev_default_region_setup");
 
 
 	if (function == ACPI_REGION_DEACTIVATE) {
@@ -394,21 +403,33 @@
 	acpi_status             status;
 	acpi_namespace_node     *method_node;
 	acpi_name               *reg_name_ptr = (acpi_name *) METHOD_NAME__REG;
+	acpi_operand_object     *region_obj2;
 
 
-	FUNCTION_TRACE_U32 ("Ev_initialize_region", acpi_ns_locked);
+	ACPI_FUNCTION_TRACE_U32 ("Ev_initialize_region", acpi_ns_locked);
 
 
 	if (!region_obj) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	node = acpi_ns_get_parent_object (region_obj->region.node);
+	if (region_obj->common.flags & AOPOBJ_OBJECT_INITIALIZED) {
+		return_ACPI_STATUS (AE_OK);
+	}
+
+	region_obj2 = acpi_ns_get_secondary_object (region_obj);
+	if (!region_obj2) {
+		return_ACPI_STATUS (AE_NOT_EXIST);
+	}
+	node = acpi_ns_get_parent_node (region_obj->region.node);
+
+
 	space_id = region_obj->region.space_id;
 
 	region_obj->region.addr_handler = NULL;
-	region_obj->region.extra->extra.method_REG = NULL;
-	region_obj->region.flags &= ~(AOPOBJ_INITIALIZED);
+	region_obj2->extra.method_REG = NULL;
+	region_obj->common.flags &= ~(AOPOBJ_SETUP_COMPLETE);
+	region_obj->common.flags |= AOPOBJ_OBJECT_INITIALIZED;
 
 	/*
 	 *  Find any "_REG" associated with this region definition
@@ -421,7 +442,7 @@
 		 *  definition.  This will be executed when the handler is attached
 		 *  or removed
 		 */
-		region_obj->region.extra->extra.method_REG = method_node;
+		region_obj2->extra.method_REG = method_node;
 	}
 
 	/*
@@ -470,6 +491,7 @@
 					 */
 					acpi_ev_associate_region_and_handler (handler_obj, region_obj,
 							acpi_ns_locked);
+
 					return_ACPI_STATUS (AE_OK);
 				}
 
@@ -482,7 +504,7 @@
 		 *  This one does not have the handler we need
 		 *  Pop up one level
 		 */
-		node = acpi_ns_get_parent_object (node);
+		node = acpi_ns_get_parent_node (node);
 
 	} /* while Node != ROOT */
 
diff -Nru a/drivers/acpi/events/evsci.c b/drivers/acpi/events/evsci.c
--- a/drivers/acpi/events/evsci.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/events/evsci.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: evsci - System Control Interrupt configuration and
  *                      legacy to ACPI mode state transition functions
- *              $Revision: 74 $
+ *              $Revision: 83 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,17 +31,7 @@
 
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evsci")
-
-
-/*
- * Elements correspond to counts for TMR, NOT_USED, GBL, PWR_BTN, SLP_BTN, RTC,
- * and GENERAL respectively.  These counts are modified by the ACPI interrupt
- * handler.
- *
- * TBD: [Investigate] Note that GENERAL should probably be split out into
- * one element for each bit in the GPE registers
- */
+	 ACPI_MODULE_NAME    ("evsci")
 
 
 /*******************************************************************************
@@ -58,23 +48,24 @@
  *
  ******************************************************************************/
 
-static u32
-acpi_ev_sci_handler (void *context)
+static u32 ACPI_SYSTEM_XFACE
+acpi_ev_sci_handler (
+	void                    *context)
 {
-	u32                     interrupt_handled = INTERRUPT_NOT_HANDLED;
+	u32                     interrupt_handled = ACPI_INTERRUPT_NOT_HANDLED;
 
 
-	FUNCTION_TRACE("Ev_sci_handler");
+	ACPI_FUNCTION_TRACE("Ev_sci_handler");
 
 
 	/*
 	 * Make sure that ACPI is enabled by checking SCI_EN.  Note that we are
 	 * required to treat the SCI interrupt as sharable, level, active low.
 	 */
-	if (!acpi_hw_register_bit_access (ACPI_READ, ACPI_MTX_DO_NOT_LOCK, SCI_EN)) {
+	if (!acpi_hw_bit_register_read (ACPI_BITREG_SCI_ENABLE, ACPI_MTX_DO_NOT_LOCK)) {
 		/* ACPI is not enabled;  this interrupt cannot be for us */
 
-		return_VALUE (INTERRUPT_NOT_HANDLED);
+		return_VALUE (ACPI_INTERRUPT_NOT_HANDLED);
 	}
 
 	/*
@@ -113,7 +104,7 @@
 	u32                     status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ev_install_sci_handler");
+	ACPI_FUNCTION_TRACE ("Ev_install_sci_handler");
 
 
 	status = acpi_os_install_interrupt_handler ((u32) acpi_gbl_FADT->sci_int,
@@ -123,7 +114,6 @@
 
 
 /******************************************************************************
-
  *
  * FUNCTION:    Acpi_ev_remove_sci_handler
  *
@@ -132,151 +122,28 @@
  * RETURN:      E_OK if handler uninstalled OK, E_ERROR if handler was not
  *              installed to begin with
  *
- * DESCRIPTION: Restores original status of all fixed event enable bits and
- *              removes SCI handler.
+ * DESCRIPTION: Remove the SCI interrupt handler.  No further SCIs will be
+ *              taken.
+ *
+ * Note:  It doesn't seem important to disable all events or set the event
+ *        enable registers to their original values.  The OS should disable
+ *        the SCI interrupt level when the handler is removed, so no more
+ *        events will come in.
  *
  ******************************************************************************/
 
 acpi_status
 acpi_ev_remove_sci_handler (void)
 {
-	FUNCTION_TRACE ("Ev_remove_sci_handler");
-
-
-#if 0
-	/* TBD:[Investigate] Figure this out!!  Disable all events first ???  */
-
-	if (original_fixed_enable_bit_status ^ 1 << acpi_event_index (TMR_FIXED_EVENT)) {
-		acpi_event_disable_event (TMR_FIXED_EVENT);
-	}
-
-	if (original_fixed_enable_bit_status ^ 1 << acpi_event_index (GBL_FIXED_EVENT)) {
-		acpi_event_disable_event (GBL_FIXED_EVENT);
-	}
-
-	if (original_fixed_enable_bit_status ^ 1 << acpi_event_index (PWR_BTN_FIXED_EVENT)) {
-		acpi_event_disable_event (PWR_BTN_FIXED_EVENT);
-	}
-
-	if (original_fixed_enable_bit_status ^ 1 << acpi_event_index (SLP_BTN_FIXED_EVENT)) {
-		acpi_event_disable_event (SLP_BTN_FIXED_EVENT);
-	}
-
-	if (original_fixed_enable_bit_status ^ 1 << acpi_event_index (RTC_FIXED_EVENT)) {
-		acpi_event_disable_event (RTC_FIXED_EVENT);
-	}
+	ACPI_FUNCTION_TRACE ("Ev_remove_sci_handler");
 
-	original_fixed_enable_bit_status = 0;
 
-#endif
+	/* Just let the OS remove the handler and disable the level */
 
 	acpi_os_remove_interrupt_handler ((u32) acpi_gbl_FADT->sci_int,
 			   acpi_ev_sci_handler);
 
 	return_ACPI_STATUS (AE_OK);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ev_restore_acpi_state
- *
- * PARAMETERS:  none
- *
- * RETURN:      none
- *
- * DESCRIPTION: Restore the original ACPI state of the machine
- *
- ******************************************************************************/
-
-void
-acpi_ev_restore_acpi_state (void)
-{
-	u32                     index;
-
-
-	FUNCTION_TRACE ("Ev_restore_acpi_state");
-
-
-	/* Restore the state of the chipset enable bits. */
-
-	if (acpi_gbl_restore_acpi_chipset == TRUE) {
-		/* Restore the fixed events */
-
-		if (acpi_hw_register_read (ACPI_MTX_LOCK, PM1_EN) !=
-				acpi_gbl_pm1_enable_register_save) {
-			acpi_hw_register_write (ACPI_MTX_LOCK, PM1_EN,
-				acpi_gbl_pm1_enable_register_save);
-		}
-
-
-		/* Ensure that all status bits are clear */
-
-		acpi_hw_clear_acpi_status ();
-
-
-		/* Now restore the GPEs */
-
-		for (index = 0; index < DIV_2 (acpi_gbl_FADT->gpe0blk_len); index++) {
-			if (acpi_hw_register_read (ACPI_MTX_LOCK, GPE0_EN_BLOCK | index) !=
-					acpi_gbl_gpe0enable_register_save[index]) {
-				acpi_hw_register_write (ACPI_MTX_LOCK, GPE0_EN_BLOCK | index,
-					acpi_gbl_gpe0enable_register_save[index]);
-			}
-		}
-
-		/* GPE 1 present? */
-
-		if (acpi_gbl_FADT->gpe1_blk_len) {
-			for (index = 0; index < DIV_2 (acpi_gbl_FADT->gpe1_blk_len); index++) {
-				if (acpi_hw_register_read (ACPI_MTX_LOCK, GPE1_EN_BLOCK | index) !=
-					acpi_gbl_gpe1_enable_register_save[index]) {
-					acpi_hw_register_write (ACPI_MTX_LOCK, GPE1_EN_BLOCK | index,
-						acpi_gbl_gpe1_enable_register_save[index]);
-				}
-			}
-		}
-
-		if (acpi_hw_get_mode() != acpi_gbl_original_mode) {
-			acpi_hw_set_mode (acpi_gbl_original_mode);
-		}
-	}
-
-	return_VOID;
-}
-
-
-/******************************************************************************
- *
- * FUNCTION:    Acpi_ev_terminate
- *
- * PARAMETERS:  none
- *
- * RETURN:      none
- *
- * DESCRIPTION: free memory allocated for table storage.
- *
- ******************************************************************************/
-
-void
-acpi_ev_terminate (void)
-{
-
-	FUNCTION_TRACE ("Ev_terminate");
-
-
-	/*
-	 * Free global tables, etc.
-	 */
-	if (acpi_gbl_gpe_registers) {
-		ACPI_MEM_FREE (acpi_gbl_gpe_registers);
-	}
-
-	if (acpi_gbl_gpe_info) {
-		ACPI_MEM_FREE (acpi_gbl_gpe_info);
-	}
-
-	return_VOID;
 }
 
 
diff -Nru a/drivers/acpi/events/evxface.c b/drivers/acpi/events/evxface.c
--- a/drivers/acpi/events/evxface.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/events/evxface.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: evxface - External interfaces for ACPI events
- *              $Revision: 116 $
+ *              $Revision: 125 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evxface")
+	 ACPI_MODULE_NAME    ("evxface")
 
 
 /*******************************************************************************
@@ -60,7 +60,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_install_fixed_event_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_install_fixed_event_handler");
 
 
 	/* Parameter validation */
@@ -69,12 +69,15 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Don't allow two handlers. */
 
 	if (NULL != acpi_gbl_fixed_event_handlers[event].handler) {
-		status = AE_EXIST;
+		status = AE_ALREADY_EXISTS;
 		goto cleanup;
 	}
 
@@ -85,7 +88,7 @@
 	acpi_gbl_fixed_event_handlers[event].context = context;
 
 	status = acpi_enable_event (event, ACPI_EVENT_FIXED, 0);
-	if (!ACPI_SUCCESS (status)) {
+	if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Could not enable fixed event.\n"));
 
 		/* Remove the handler */
@@ -93,7 +96,6 @@
 		acpi_gbl_fixed_event_handlers[event].handler = NULL;
 		acpi_gbl_fixed_event_handlers[event].context = NULL;
 	}
-
 	else {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 			"Enabled fixed event %X, Handler=%p\n", event, handler));
@@ -101,7 +103,7 @@
 
 
 cleanup:
-	acpi_ut_release_mutex (ACPI_MTX_EVENTS);
+	(void) acpi_ut_release_mutex (ACPI_MTX_EVENTS);
 	return_ACPI_STATUS (status);
 }
 
@@ -127,7 +129,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Acpi_remove_fixed_event_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_remove_fixed_event_handler");
 
 
 	/* Parameter validation */
@@ -136,7 +138,10 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Disable the event before removing the handler */
 
@@ -147,7 +152,7 @@
 	acpi_gbl_fixed_event_handlers[event].handler = NULL;
 	acpi_gbl_fixed_event_handlers[event].context = NULL;
 
-	if (!ACPI_SUCCESS (status)) {
+	if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_WARN,
 			"Could not write to fixed event enable register.\n"));
 	}
@@ -155,7 +160,7 @@
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Disabled fixed event %X.\n", event));
 	}
 
-	acpi_ut_release_mutex (ACPI_MTX_EVENTS);
+	(void) acpi_ut_release_mutex (ACPI_MTX_EVENTS);
 	return_ACPI_STATUS (status);
 }
 
@@ -187,10 +192,10 @@
 	acpi_operand_object     *obj_desc;
 	acpi_operand_object     *notify_obj;
 	acpi_namespace_node     *device_node;
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_install_notify_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_install_notify_handler");
 
 
 	/* Parameter validation */
@@ -200,7 +205,10 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Convert and validate the device handle */
 
@@ -223,7 +231,7 @@
 			  acpi_gbl_sys_notify.handler) ||
 			((handler_type == ACPI_DEVICE_NOTIFY) &&
 			  acpi_gbl_drv_notify.handler)) {
-			status = AE_EXIST;
+			status = AE_ALREADY_EXISTS;
 			goto unlock_and_exit;
 		}
 
@@ -269,11 +277,10 @@
 				  obj_desc->device.sys_handler) ||
 				((handler_type == ACPI_DEVICE_NOTIFY) &&
 				  obj_desc->device.drv_handler)) {
-				status = AE_EXIST;
+				status = AE_ALREADY_EXISTS;
 				goto unlock_and_exit;
 			}
 		}
-
 		else {
 			/* Create a new object */
 
@@ -285,7 +292,7 @@
 
 			/* Attach new object to the Node */
 
-			status = acpi_ns_attach_object (device, obj_desc, (u8) device_node->type);
+			status = acpi_ns_attach_object (device, obj_desc, device_node->type);
 			if (ACPI_FAILURE (status)) {
 				goto unlock_and_exit;
 			}
@@ -307,7 +314,6 @@
 		if (handler_type == ACPI_SYSTEM_NOTIFY) {
 			obj_desc->device.sys_handler = notify_obj;
 		}
-
 		else /* ACPI_DEVICE_NOTIFY */ {
 			obj_desc->device.drv_handler = notify_obj;
 		}
@@ -315,7 +321,7 @@
 
 
 unlock_and_exit:
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
 
@@ -344,10 +350,10 @@
 	acpi_operand_object     *notify_obj;
 	acpi_operand_object     *obj_desc;
 	acpi_namespace_node     *device_node;
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_remove_notify_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_remove_notify_handler");
 
 
 	/* Parameter validation */
@@ -357,7 +363,10 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Convert and validate the device handle */
 
@@ -445,7 +454,7 @@
 
 
 unlock_and_exit:
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
 
@@ -474,38 +483,43 @@
 	acpi_gpe_handler        handler,
 	void                    *context)
 {
-	acpi_status             status = AE_OK;
+	acpi_status             status;
+	u32                     gpe_number_index;
 
 
-	FUNCTION_TRACE ("Acpi_install_gpe_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_install_gpe_handler");
 
 
 	/* Parameter validation */
 
-	if (!handler || (gpe_number > ACPI_GPE_MAX)) {
+	if (!handler) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
 	/* Ensure that we have a valid GPE number */
 
-	if (acpi_gbl_gpe_valid[gpe_number] == ACPI_GPE_INVALID) {
+	gpe_number_index = acpi_ev_get_gpe_number_index (gpe_number);
+	if (gpe_number_index == ACPI_GPE_INVALID) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Make sure that there isn't a handler there already */
 
-	if (acpi_gbl_gpe_info[gpe_number].handler) {
-		status = AE_EXIST;
+	if (acpi_gbl_gpe_number_info[gpe_number_index].handler) {
+		status = AE_ALREADY_EXISTS;
 		goto cleanup;
 	}
 
 	/* Install the handler */
 
-	acpi_gbl_gpe_info[gpe_number].handler = handler;
-	acpi_gbl_gpe_info[gpe_number].context = context;
-	acpi_gbl_gpe_info[gpe_number].type = (u8) type;
+	acpi_gbl_gpe_number_info[gpe_number_index].handler = handler;
+	acpi_gbl_gpe_number_info[gpe_number_index].context = context;
+	acpi_gbl_gpe_number_info[gpe_number_index].type = (u8) type;
 
 	/* Clear the GPE (of stale events), the enable it */
 
@@ -514,7 +528,7 @@
 
 
 cleanup:
-	acpi_ut_release_mutex (ACPI_MTX_EVENTS);
+	(void) acpi_ut_release_mutex (ACPI_MTX_EVENTS);
 	return_ACPI_STATUS (status);
 }
 
@@ -537,21 +551,23 @@
 	u32                     gpe_number,
 	acpi_gpe_handler        handler)
 {
-	acpi_status             status = AE_OK;
+	acpi_status             status;
+	u32                     gpe_number_index;
 
 
-	FUNCTION_TRACE ("Acpi_remove_gpe_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_remove_gpe_handler");
 
 
 	/* Parameter validation */
 
-	if (!handler || (gpe_number > ACPI_GPE_MAX)) {
+	if (!handler) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
 	/* Ensure that we have a valid GPE number */
 
-	if (acpi_gbl_gpe_valid[gpe_number] == ACPI_GPE_INVALID) {
+	gpe_number_index = acpi_ev_get_gpe_number_index (gpe_number);
+	if (gpe_number_index == ACPI_GPE_INVALID) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
@@ -559,11 +575,14 @@
 
 	acpi_hw_disable_gpe (gpe_number);
 
-	acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_EVENTS);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Make sure that the installed handler is the same */
 
-	if (acpi_gbl_gpe_info[gpe_number].handler != handler) {
+	if (acpi_gbl_gpe_number_info[gpe_number_index].handler != handler) {
 		acpi_hw_enable_gpe (gpe_number);
 		status = AE_BAD_PARAMETER;
 		goto cleanup;
@@ -571,12 +590,12 @@
 
 	/* Remove the handler */
 
-	acpi_gbl_gpe_info[gpe_number].handler = NULL;
-	acpi_gbl_gpe_info[gpe_number].context = NULL;
+	acpi_gbl_gpe_number_info[gpe_number_index].handler = NULL;
+	acpi_gbl_gpe_number_info[gpe_number_index].context = NULL;
 
 
 cleanup:
-	acpi_ut_release_mutex (ACPI_MTX_EVENTS);
+	(void) acpi_ut_release_mutex (ACPI_MTX_EVENTS);
 	return_ACPI_STATUS (status);
 }
 
@@ -596,23 +615,29 @@
 
 acpi_status
 acpi_acquire_global_lock (
-	void)
+	u32                     timeout,
+	u32                     *handle)
 {
 	acpi_status             status;
 
 
+	if (!handle) {
+		return (AE_BAD_PARAMETER);
+	}
+
 	status = acpi_ex_enter_interpreter ();
 	if (ACPI_FAILURE (status)) {
 		return (status);
 	}
 
-	/*
-	 * TBD: [Restructure] add timeout param to internal interface, and
-	 * perhaps INTERPRETER_LOCKED
-	 */
-	status = acpi_ev_acquire_global_lock ();
+	status = acpi_ev_acquire_global_lock (timeout);
 	acpi_ex_exit_interpreter ();
 
+	if (ACPI_SUCCESS (status)) {
+		acpi_gbl_global_lock_handle++;
+		*handle = acpi_gbl_global_lock_handle;
+	}
+
 	return (status);
 }
 
@@ -631,8 +656,12 @@
 
 acpi_status
 acpi_release_global_lock (
-	void)
+	u32                     handle)
 {
+
+	if (handle != acpi_gbl_global_lock_handle) {
+		return (AE_NOT_ACQUIRED);
+	}
 
 	acpi_ev_release_global_lock ();
 	return (AE_OK);
diff -Nru a/drivers/acpi/events/evxfevnt.c b/drivers/acpi/events/evxfevnt.c
--- a/drivers/acpi/events/evxfevnt.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/events/evxfevnt.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: evxfevnt - External Interfaces, ACPI event disable/enable
- *              $Revision: 38 $
+ *              $Revision: 51 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evxfevnt")
+	 ACPI_MODULE_NAME    ("evxfevnt")
 
 
 /*******************************************************************************
@@ -50,36 +50,36 @@
 acpi_status
 acpi_enable (void)
 {
-	acpi_status             status;
+	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Acpi_enable");
+	ACPI_FUNCTION_TRACE ("Acpi_enable");
 
 
-	/* Make sure we've got ACPI tables */
+	/* Make sure we have ACPI tables */
 
 	if (!acpi_gbl_DSDT) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "No ACPI tables present!\n"));
 		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
 	}
 
-	/* Make sure the BIOS supports ACPI mode */
+	acpi_gbl_original_mode = acpi_hw_get_mode ();
 
-	if (SYS_MODE_LEGACY == acpi_hw_get_mode_capabilities()) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Only legacy mode supported!\n"));
-		return_ACPI_STATUS (AE_ERROR);
+	if (acpi_gbl_original_mode == ACPI_SYS_MODE_ACPI) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_OK, "Already in ACPI mode.\n"));
 	}
+	else {
+		/* Transition to ACPI mode */
 
-	/* Transition to ACPI mode */
+		status = acpi_hw_set_mode (ACPI_SYS_MODE_ACPI);
+		if (ACPI_FAILURE (status)) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Could not transition to ACPI mode.\n"));
+			return_ACPI_STATUS (status);
+		}
 
-	status = acpi_hw_set_mode (SYS_MODE_ACPI);
-	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_FATAL, "Could not transition to ACPI mode.\n"));
-		return_ACPI_STATUS (status);
+		ACPI_DEBUG_PRINT ((ACPI_DB_OK, "Transition to ACPI mode successful\n"));
 	}
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_OK, "Transition to ACPI mode successful\n"));
-
 	return_ACPI_STATUS (status);
 }
 
@@ -100,25 +100,25 @@
 acpi_status
 acpi_disable (void)
 {
-	acpi_status             status;
+	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Acpi_disable");
+	ACPI_FUNCTION_TRACE ("Acpi_disable");
 
 
-	/* Restore original mode  */
+	if (acpi_hw_get_mode () != acpi_gbl_original_mode) {
+		/* Restore original mode  */
 
-	status = acpi_hw_set_mode (acpi_gbl_original_mode);
-	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to transition to original mode"));
-		return_ACPI_STATUS (status);
+		status = acpi_hw_set_mode (acpi_gbl_original_mode);
+		if (ACPI_FAILURE (status)) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to transition to original mode"));
+			return_ACPI_STATUS (status);
+		}
 	}
 
 	/* Unload the SCI interrupt handler  */
 
 	acpi_ev_remove_sci_handler ();
-	acpi_ev_restore_acpi_state ();
-
 	return_ACPI_STATUS (status);
 }
 
@@ -144,58 +144,37 @@
 	u32                     flags)
 {
 	acpi_status             status = AE_OK;
-	u32                     register_id;
 
 
-	FUNCTION_TRACE ("Acpi_enable_event");
+	ACPI_FUNCTION_TRACE ("Acpi_enable_event");
 
 
-	/* The Type must be either Fixed Acpi_event or GPE */
+	/* The Type must be either Fixed Event or GPE */
 
 	switch (type) {
-
 	case ACPI_EVENT_FIXED:
 
-		/* Decode the Fixed Acpi_event */
-
-		switch (event) {
-		case ACPI_EVENT_PMTIMER:
-			register_id = TMR_EN;
-			break;
-
-		case ACPI_EVENT_GLOBAL:
-			register_id = GBL_EN;
-			break;
-
-		case ACPI_EVENT_POWER_BUTTON:
-			register_id = PWRBTN_EN;
-			break;
-
-		case ACPI_EVENT_SLEEP_BUTTON:
-			register_id = SLPBTN_EN;
-			break;
-
-		case ACPI_EVENT_RTC:
-			register_id = RTC_EN;
-			break;
+		/* Decode the Fixed Event */
 
-		default:
+		if (event > ACPI_NUM_FIXED_EVENTS) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
-			break;
 		}
 
 		/*
 		 * Enable the requested fixed event (by writing a one to the
 		 * enable register bit)
 		 */
-		acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, register_id, 1);
+		acpi_hw_bit_register_write (acpi_gbl_fixed_event_info[event].enable_register_id,
+				1, ACPI_MTX_LOCK);
 
-		if (1 != acpi_hw_register_bit_access(ACPI_READ, ACPI_MTX_LOCK, register_id)) {
+		/* Make sure that the hardware responded */
+
+		if (1 != acpi_hw_bit_register_read (acpi_gbl_fixed_event_info[event].enable_register_id,
+				  ACPI_MTX_LOCK)) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Fixed event bit clear when it should be set\n"));
+				"Could not enable %s event\n", acpi_ut_get_event_name (event)));
 			return_ACPI_STATUS (AE_NO_HARDWARE_RESPONSE);
 		}
-
 		break;
 
 
@@ -203,21 +182,17 @@
 
 		/* Ensure that we have a valid GPE number */
 
-		if ((event > ACPI_GPE_MAX) ||
-			(acpi_gbl_gpe_valid[event] == ACPI_GPE_INVALID)) {
+		if (acpi_ev_get_gpe_number_index (event) == ACPI_GPE_INVALID) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
 		}
 
-
 		/* Enable the requested GPE number */
 
-		if (flags & ACPI_EVENT_ENABLE) {
-			acpi_hw_enable_gpe (event);
-		}
+		acpi_hw_enable_gpe (event);
+
 		if (flags & ACPI_EVENT_WAKE_ENABLE) {
 			acpi_hw_enable_gpe_for_wakeup (event);
 		}
-
 		break;
 
 
@@ -226,7 +201,6 @@
 		status = AE_BAD_PARAMETER;
 	}
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -252,58 +226,35 @@
 	u32                     flags)
 {
 	acpi_status             status = AE_OK;
-	u32                     register_id;
 
 
-	FUNCTION_TRACE ("Acpi_disable_event");
+	ACPI_FUNCTION_TRACE ("Acpi_disable_event");
 
 
-	/* The Type must be either Fixed Acpi_event or GPE */
+	/* The Type must be either Fixed Event or GPE */
 
 	switch (type) {
-
 	case ACPI_EVENT_FIXED:
 
-		/* Decode the Fixed Acpi_event */
+		/* Decode the Fixed Event */
 
-		switch (event) {
-		case ACPI_EVENT_PMTIMER:
-			register_id = TMR_EN;
-			break;
-
-		case ACPI_EVENT_GLOBAL:
-			register_id = GBL_EN;
-			break;
-
-		case ACPI_EVENT_POWER_BUTTON:
-			register_id = PWRBTN_EN;
-			break;
-
-		case ACPI_EVENT_SLEEP_BUTTON:
-			register_id = SLPBTN_EN;
-			break;
-
-		case ACPI_EVENT_RTC:
-			register_id = RTC_EN;
-			break;
-
-		default:
+		if (event > ACPI_NUM_FIXED_EVENTS) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
-			break;
 		}
 
 		/*
 		 * Disable the requested fixed event (by writing a zero to the
 		 * enable register bit)
 		 */
-		acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, register_id, 0);
+		acpi_hw_bit_register_write (acpi_gbl_fixed_event_info[event].enable_register_id,
+				0, ACPI_MTX_LOCK);
 
-		if (0 != acpi_hw_register_bit_access(ACPI_READ, ACPI_MTX_LOCK, register_id)) {
+		if (0 != acpi_hw_bit_register_read (acpi_gbl_fixed_event_info[event].enable_register_id,
+				 ACPI_MTX_LOCK)) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Fixed event bit set when it should be clear,\n"));
+				"Could not disable %s events\n", acpi_ut_get_event_name (event)));
 			return_ACPI_STATUS (AE_NO_HARDWARE_RESPONSE);
 		}
-
 		break;
 
 
@@ -311,20 +262,21 @@
 
 		/* Ensure that we have a valid GPE number */
 
-		if ((event > ACPI_GPE_MAX) ||
-			(acpi_gbl_gpe_valid[event] == ACPI_GPE_INVALID)) {
+		if (acpi_ev_get_gpe_number_index (event) == ACPI_GPE_INVALID) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
 		}
 
-		/* Disable the requested GPE number */
+		/*
+		 * Only disable the requested GPE number for wake if specified.
+		 * Otherwise, turn it totally off
+		 */
 
-		if (flags & ACPI_EVENT_DISABLE) {
-			acpi_hw_disable_gpe (event);
-		}
 		if (flags & ACPI_EVENT_WAKE_DISABLE) {
 			acpi_hw_disable_gpe_for_wakeup (event);
 		}
-
+		else {
+			acpi_hw_disable_gpe (event);
+		}
 		break;
 
 
@@ -355,51 +307,28 @@
 	u32                     type)
 {
 	acpi_status             status = AE_OK;
-	u32                     register_id;
 
 
-	FUNCTION_TRACE ("Acpi_clear_event");
+	ACPI_FUNCTION_TRACE ("Acpi_clear_event");
 
 
-	/* The Type must be either Fixed Acpi_event or GPE */
+	/* The Type must be either Fixed Event or GPE */
 
 	switch (type) {
-
 	case ACPI_EVENT_FIXED:
 
-		/* Decode the Fixed Acpi_event */
+		/* Decode the Fixed Event */
 
-		switch (event) {
-		case ACPI_EVENT_PMTIMER:
-			register_id = TMR_STS;
-			break;
-
-		case ACPI_EVENT_GLOBAL:
-			register_id = GBL_STS;
-			break;
-
-		case ACPI_EVENT_POWER_BUTTON:
-			register_id = PWRBTN_STS;
-			break;
-
-		case ACPI_EVENT_SLEEP_BUTTON:
-			register_id = SLPBTN_STS;
-			break;
-
-		case ACPI_EVENT_RTC:
-			register_id = RTC_STS;
-			break;
-
-		default:
+		if (event > ACPI_NUM_FIXED_EVENTS) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
-			break;
 		}
 
 		/*
 		 * Clear the requested fixed event (By writing a one to the
 		 * status register bit)
 		 */
-		acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, register_id, 1);
+		acpi_hw_bit_register_write (acpi_gbl_fixed_event_info[event].status_register_id,
+				1, ACPI_MTX_LOCK);
 		break;
 
 
@@ -407,12 +336,10 @@
 
 		/* Ensure that we have a valid GPE number */
 
-		if ((event > ACPI_GPE_MAX) ||
-			(acpi_gbl_gpe_valid[event] == ACPI_GPE_INVALID)) {
+		if (acpi_ev_get_gpe_number_index (event) == ACPI_GPE_INVALID) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
 		}
 
-
 		acpi_hw_clear_gpe (event);
 		break;
 
@@ -449,10 +376,9 @@
 	acpi_event_status       *event_status)
 {
 	acpi_status             status = AE_OK;
-	u32                     register_id;
 
 
-	FUNCTION_TRACE ("Acpi_get_event_status");
+	ACPI_FUNCTION_TRACE ("Acpi_get_event_status");
 
 
 	if (!event_status) {
@@ -460,43 +386,21 @@
 	}
 
 
-	/* The Type must be either Fixed Acpi_event or GPE */
+	/* The Type must be either Fixed Event or GPE */
 
 	switch (type) {
-
 	case ACPI_EVENT_FIXED:
 
-		/* Decode the Fixed Acpi_event */
-
-		switch (event) {
-		case ACPI_EVENT_PMTIMER:
-			register_id = TMR_STS;
-			break;
-
-		case ACPI_EVENT_GLOBAL:
-			register_id = GBL_STS;
-			break;
-
-		case ACPI_EVENT_POWER_BUTTON:
-			register_id = PWRBTN_STS;
-			break;
-
-		case ACPI_EVENT_SLEEP_BUTTON:
-			register_id = SLPBTN_STS;
-			break;
-
-		case ACPI_EVENT_RTC:
-			register_id = RTC_STS;
-			break;
+		/* Decode the Fixed Event */
 
-		default:
+		if (event > ACPI_NUM_FIXED_EVENTS) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
-			break;
 		}
 
 		/* Get the status of the requested fixed event */
 
-		*event_status = acpi_hw_register_bit_access (ACPI_READ, ACPI_MTX_LOCK, register_id);
+		*event_status = acpi_hw_bit_register_read (acpi_gbl_fixed_event_info[event].status_register_id,
+				   ACPI_MTX_LOCK);
 		break;
 
 
@@ -504,11 +408,9 @@
 
 		/* Ensure that we have a valid GPE number */
 
-		if ((event > ACPI_GPE_MAX) ||
-			(acpi_gbl_gpe_valid[event] == ACPI_GPE_INVALID)) {
+		if (acpi_ev_get_gpe_number_index (event) == ACPI_GPE_INVALID) {
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
 		}
-
 
 		/* Obtain status on the requested GPE number */
 
diff -Nru a/drivers/acpi/events/evxfregn.c b/drivers/acpi/events/evxfregn.c
--- a/drivers/acpi/events/evxfregn.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/events/evxfregn.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: evxfregn - External Interfaces, ACPI Operation Regions and
  *                         Address Spaces.
- *              $Revision: 40 $
+ *              $Revision: 48 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_EVENTS
-	 MODULE_NAME         ("evxfregn")
+	 ACPI_MODULE_NAME    ("evxfregn")
 
 
 /*******************************************************************************
@@ -63,23 +63,24 @@
 	acpi_operand_object     *obj_desc;
 	acpi_operand_object     *handler_obj;
 	acpi_namespace_node     *node;
-	acpi_status             status = AE_OK;
-	acpi_object_type8       type;
+	acpi_status             status;
+	acpi_object_type        type;
 	u16                     flags = 0;
 
 
-	FUNCTION_TRACE ("Acpi_install_address_space_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_install_address_space_handler");
 
 
 	/* Parameter validation */
 
-	if ((!device)   ||
-		((!handler)  && (handler != ACPI_DEFAULT_HANDLER)) ||
-		(space_id > ACPI_MAX_ADDRESS_SPACE)) {
+	if (!device) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Convert and validate the device handle */
 
@@ -103,7 +104,7 @@
 	}
 
 	if (handler == ACPI_DEFAULT_HANDLER) {
-		flags = ADDR_HANDLER_DEFAULT_INSTALLED;
+		flags = ACPI_ADDR_HANDLER_DEFAULT_INSTALLED;
 
 		switch (space_id) {
 		case ACPI_ADR_SPACE_SYSTEM_MEMORY:
@@ -131,10 +132,14 @@
 			setup   = acpi_ev_pci_bar_region_setup;
 			break;
 
+		case ACPI_ADR_SPACE_DATA_TABLE:
+			handler = acpi_ex_data_table_space_handler;
+			setup   = NULL;
+			break;
+
 		default:
 			status = AE_NOT_EXIST;
 			goto unlock_and_exit;
-			break;
 		}
 	}
 
@@ -164,7 +169,7 @@
 			 * address space.
 			 */
 			if(handler_obj->addr_handler.space_id == space_id) {
-				status = AE_EXIST;
+				status = AE_ALREADY_EXISTS;
 				goto unlock_and_exit;
 			}
 
@@ -174,7 +179,6 @@
 			handler_obj = handler_obj->addr_handler.next;
 		}
 	}
-
 	else {
 		ACPI_DEBUG_PRINT ((ACPI_DB_OPREGION,
 			"Creating object on Device %p while installing handler\n", node));
@@ -200,7 +204,7 @@
 
 		/* Attach the new object to the Node */
 
-		status = acpi_ns_attach_object (node, obj_desc, (u8) type);
+		status = acpi_ns_attach_object (node, obj_desc, type);
 		if (ACPI_FAILURE (status)) {
 			acpi_ut_remove_reference (obj_desc);
 			goto unlock_and_exit;
@@ -246,7 +250,7 @@
 	 * of the branch
 	 */
 	status = acpi_ns_walk_namespace (ACPI_TYPE_ANY, device,
-			 ACPI_UINT32_MAX, NS_WALK_UNLOCK,
+			 ACPI_UINT32_MAX, ACPI_NS_WALK_UNLOCK,
 			 acpi_ev_addr_handler_helper,
 			 handler_obj, NULL);
 
@@ -260,7 +264,7 @@
 
 
 unlock_and_exit:
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
 
@@ -289,21 +293,22 @@
 	acpi_operand_object     *region_obj;
 	acpi_operand_object     **last_obj_ptr;
 	acpi_namespace_node     *node;
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_remove_address_space_handler");
+	ACPI_FUNCTION_TRACE ("Acpi_remove_address_space_handler");
 
 
 	/* Parameter validation */
 
-	if ((!device)   ||
-		((!handler)  && (handler != ACPI_DEFAULT_HANDLER)) ||
-		(space_id > ACPI_MAX_ADDRESS_SPACE)) {
+	if (!device) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Convert and validate the device handle */
 
@@ -313,7 +318,6 @@
 		goto unlock_and_exit;
 	}
 
-
 	/* Make sure the internal object exists */
 
 	obj_desc = acpi_ns_get_attached_object (node);
@@ -396,7 +400,7 @@
 
 
 unlock_and_exit:
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
 
diff -Nru a/drivers/acpi/executer/Makefile b/drivers/acpi/executer/Makefile
--- a/drivers/acpi/executer/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/executer/exconfig.c b/drivers/acpi/executer/exconfig.c
--- a/drivers/acpi/executer/exconfig.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/executer/exconfig.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: exconfig - Namespace reconfiguration (Load/Unload opcodes)
- *              $Revision: 44 $
+ *              $Revision: 59 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,151 +35,358 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exconfig")
+	 ACPI_MODULE_NAME    ("exconfig")
 
 
-/*****************************************************************************
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_add_table
+ *
+ * PARAMETERS:  Table               - Pointer to raw table
+ *              Parent_node         - Where to load the table (scope)
+ *              Ddb_handle          - Where to return the table handle.
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Common function to Install and Load an ACPI table with a
+ *              returned table handle.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ex_add_table (
+	acpi_table_header       *table,
+	acpi_namespace_node     *parent_node,
+	acpi_operand_object     **ddb_handle)
+{
+	acpi_status             status;
+	acpi_table_desc         table_info;
+	acpi_operand_object     *obj_desc;
+
+
+	ACPI_FUNCTION_TRACE ("Ex_add_table");
+
+
+	/* Create an object to be the table handle */
+
+	obj_desc = acpi_ut_create_internal_object (INTERNAL_TYPE_REFERENCE);
+	if (!obj_desc) {
+		return_ACPI_STATUS (AE_NO_MEMORY);
+	}
+
+	/* Install the new table into the local data structures */
+
+	table_info.pointer     = table;
+	table_info.length      = table->length;
+	table_info.allocation  = ACPI_MEM_ALLOCATED;
+	table_info.base_pointer = table;
+
+	status = acpi_tb_install_table (NULL, &table_info);
+	if (ACPI_FAILURE (status)) {
+		goto cleanup;
+	}
+
+	/* Add the table to the namespace */
+
+	status = acpi_ns_load_table (table_info.installed_desc, parent_node);
+	if (ACPI_FAILURE (status)) {
+		/* Uninstall table on error */
+
+		acpi_tb_uninstall_table (table_info.installed_desc);
+		goto cleanup;
+	}
+
+	/* Init the table handle */
+
+	obj_desc->reference.opcode = AML_LOAD_OP;
+	obj_desc->reference.object = table_info.installed_desc;
+	*ddb_handle = obj_desc;
+	return_ACPI_STATUS (AE_OK);
+
+
+cleanup:
+	acpi_ut_remove_reference (obj_desc);
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
  *
  * FUNCTION:    Acpi_ex_load_table_op
  *
- * PARAMETERS:  Rgn_desc        - Op region where the table will be obtained
- *              Ddb_handle      - Where a handle to the table will be returned
+ * PARAMETERS:  Walk_state          - Current state with operands
+ *              Return_desc         - Where to store the return object
  *
  * RETURN:      Status
  *
  * DESCRIPTION: Load an ACPI table
  *
- ****************************************************************************/
+ ******************************************************************************/
 
 acpi_status
-acpi_ex_load_op (
-	acpi_operand_object     *rgn_desc,
-	acpi_operand_object     *ddb_handle)
+acpi_ex_load_table_op (
+	acpi_walk_state         *walk_state,
+	acpi_operand_object     **return_desc)
 {
 	acpi_status             status;
-	acpi_operand_object     *table_desc = NULL;
-	u8                      *table_ptr;
-	u8                      *table_data_ptr;
-	acpi_table_header       table_header;
-	acpi_table_desc         table_info;
-	u32                     i;
+	acpi_operand_object     **operand = &walk_state->operands[0];
+	acpi_table_header       *table;
+	acpi_namespace_node     *parent_node;
+	acpi_namespace_node     *start_node;
+	acpi_namespace_node     *parameter_node = NULL;
+	acpi_operand_object     *ddb_handle;
+
+
+	ACPI_FUNCTION_TRACE ("Ex_load_table_op");
+
 
+	/*
+	 * Make sure that the signature does not match one of the tables that
+	 * is already loaded.
+	 */
+	status = acpi_tb_match_signature (operand[0]->string.pointer, NULL);
+	if (status == AE_OK) {
+		/* Signature matched -- don't allow override */
+
+		return_ACPI_STATUS (AE_ALREADY_EXISTS);
+	}
+
+	/* Find the ACPI table */
+
+	status = acpi_tb_find_table (operand[0]->string.pointer,
+			   operand[1]->string.pointer,
+			   operand[2]->string.pointer, &table);
+	if (ACPI_FAILURE (status)) {
+		if (status != AE_NOT_FOUND) {
+			return_ACPI_STATUS (status);
+		}
 
-	FUNCTION_TRACE ("Ex_load_op");
+		/* Not found, return an Integer=0 and AE_OK */
 
-	/* TBD: [Unhandled] Object can be either a field or an opregion */
+		ddb_handle = acpi_ut_create_internal_object (ACPI_TYPE_INTEGER);
+		if (!ddb_handle) {
+			return_ACPI_STATUS (AE_NO_MEMORY);
+		}
+
+		ddb_handle->integer.value = 0;
+		*return_desc = ddb_handle;
+
+		return_ACPI_STATUS (AE_OK);
+	}
+
+	/* Default nodes */
 
+	start_node = walk_state->scope_info->scope.node;
+	parent_node = acpi_gbl_root_node;
 
-	/* Get the table header */
+	/* Root_path (optional parameter) */
 
-	table_header.length = 0;
-	for (i = 0; i < sizeof (acpi_table_header); i++) {
-		status = acpi_ev_address_space_dispatch (rgn_desc, ACPI_READ_ADR_SPACE,
-				   (ACPI_PHYSICAL_ADDRESS) i, 8,
-				   (u32 *) ((u8 *) &table_header + i));
+	if (operand[3]->string.length > 0) {
+		/*
+		 * Find the node referenced by the Root_path_string. This is the
+		 * location within the namespace where the table will be loaded.
+		 */
+		status = acpi_ns_get_node_by_path (operand[3]->string.pointer, start_node,
+				   ACPI_NS_SEARCH_PARENT, &parent_node);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
 	}
 
-	/* Allocate a buffer for the entire table */
+	/* Parameter_path (optional parameter) */
 
-	table_ptr = ACPI_MEM_ALLOCATE (table_header.length);
-	if (!table_ptr) {
-		return_ACPI_STATUS (AE_NO_MEMORY);
+	if (operand[4]->string.length > 0) {
+		if ((operand[4]->string.pointer[0] != '\\') &&
+			(operand[4]->string.pointer[0] != '^')) {
+			/*
+			 * Path is not absolute, so it will be relative to the node
+			 * referenced by the Root_path_string (or the NS root if omitted)
+			 */
+			start_node = parent_node;
+		}
+
+		/*
+		 * Find the node referenced by the Parameter_path_string
+		 */
+		status = acpi_ns_get_node_by_path (operand[4]->string.pointer, start_node,
+				   ACPI_NS_SEARCH_PARENT, &parameter_node);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
 	}
 
-	/* Copy the header to the buffer */
+	/* Load the table into the namespace */
 
-	MEMCPY (table_ptr, &table_header, sizeof (acpi_table_header));
-	table_data_ptr = table_ptr + sizeof (acpi_table_header);
+	status = acpi_ex_add_table (table, parent_node, &ddb_handle);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
+	/* Parameter Data (optional) */
 
-	/* Get the table from the op region */
+	if (parameter_node) {
+		/* Store the parameter data into the optional parameter object */
 
-	for (i = 0; i < table_header.length; i++) {
-		status = acpi_ev_address_space_dispatch (rgn_desc, ACPI_READ_ADR_SPACE,
-				   (ACPI_PHYSICAL_ADDRESS) i, 8,
-				   (u32 *) (table_data_ptr + i));
+		status = acpi_ex_store (operand[5], (acpi_operand_object *) parameter_node,
+				 walk_state);
 		if (ACPI_FAILURE (status)) {
-			goto cleanup;
+			acpi_ex_unload_table (ddb_handle);
 		}
 	}
 
+	return_ACPI_STATUS  (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_load_op
+ *
+ * PARAMETERS:  Obj_desc        - Region or Field where the table will be
+ *                                obtained
+ *              Target          - Where a handle to the table will be stored
+ *              Walk_state      - Current state
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Load an ACPI table from a field or operation region
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ex_load_op (
+	acpi_operand_object     *obj_desc,
+	acpi_operand_object     *target,
+	acpi_walk_state         *walk_state)
+{
+	acpi_status             status;
+	acpi_operand_object     *ddb_handle;
+	acpi_operand_object     *buffer_desc = NULL;
+	acpi_table_header       *table_ptr = NULL;
+	u8                      *table_data_ptr;
+	acpi_table_header       table_header;
+	u32                     i;
+
+
+	ACPI_FUNCTION_TRACE ("Ex_load_op");
+
+
+	/* Object can be either an Op_region or a Field */
+
+	switch (ACPI_GET_OBJECT_TYPE (obj_desc)) {
+	case ACPI_TYPE_REGION:
+
+		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Load from Region %p %s\n",
+			obj_desc, acpi_ut_get_type_name (obj_desc->common.type)));
+
+		/* Get the table header */
+
+		table_header.length = 0;
+		for (i = 0; i < sizeof (acpi_table_header); i++) {
+			status = acpi_ev_address_space_dispatch (obj_desc, ACPI_READ,
+					   (ACPI_PHYSICAL_ADDRESS) i, 8,
+					   (acpi_integer *) ((u8 *) &table_header + i));
+			if (ACPI_FAILURE (status)) {
+				return_ACPI_STATUS (status);
+			}
+		}
+
+		/* Allocate a buffer for the entire table */
+
+		table_ptr = ACPI_MEM_ALLOCATE (table_header.length);
+		if (!table_ptr) {
+			return_ACPI_STATUS (AE_NO_MEMORY);
+		}
+
+		/* Copy the header to the buffer */
 
-	/* Table must be either an SSDT or a PSDT */
+		ACPI_MEMCPY (table_ptr, &table_header, sizeof (acpi_table_header));
+		table_data_ptr = ACPI_PTR_ADD (u8, table_ptr, sizeof (acpi_table_header));
 
-	if ((!STRNCMP (table_header.signature,
+		/* Get the table from the op region */
+
+		for (i = 0; i < table_header.length; i++) {
+			status = acpi_ev_address_space_dispatch (obj_desc, ACPI_READ,
+					   (ACPI_PHYSICAL_ADDRESS) i, 8,
+					   (acpi_integer *) (table_data_ptr + i));
+			if (ACPI_FAILURE (status)) {
+				goto cleanup;
+			}
+		}
+		break;
+
+
+	case ACPI_TYPE_BUFFER_FIELD:
+	case INTERNAL_TYPE_REGION_FIELD:
+	case INTERNAL_TYPE_BANK_FIELD:
+	case INTERNAL_TYPE_INDEX_FIELD:
+
+		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Load from Field %p %s\n",
+			obj_desc, acpi_ut_get_type_name (obj_desc->common.type)));
+
+		/*
+		 * The length of the field must be at least as large as the table.
+		 * Read the entire field and thus the entire table.  Buffer is
+		 * allocated during the read.
+		 */
+		status = acpi_ex_read_data_from_field (obj_desc, &buffer_desc);
+		if (ACPI_FAILURE (status)) {
+			goto cleanup;
+		}
+
+		table_ptr = (acpi_table_header *) buffer_desc->buffer.pointer;
+		break;
+
+
+	default:
+		return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
+	}
+
+	/* The table must be either an SSDT or a PSDT */
+
+	if ((!ACPI_STRNCMP (table_ptr->signature,
 			  acpi_gbl_acpi_table_data[ACPI_TABLE_PSDT].signature,
 			  acpi_gbl_acpi_table_data[ACPI_TABLE_PSDT].sig_length)) &&
-		(!STRNCMP (table_header.signature,
+		(!ACPI_STRNCMP (table_ptr->signature,
 				 acpi_gbl_acpi_table_data[ACPI_TABLE_SSDT].signature,
 				 acpi_gbl_acpi_table_data[ACPI_TABLE_SSDT].sig_length))) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 			"Table has invalid signature [%4.4s], must be SSDT or PSDT\n",
-			(char*)table_header.signature));
+			(char *) &table_ptr->signature));
 		status = AE_BAD_SIGNATURE;
 		goto cleanup;
 	}
 
-	/* Create an object to be the table handle */
-
-	table_desc = acpi_ut_create_internal_object (INTERNAL_TYPE_REFERENCE);
-	if (!table_desc) {
-		status = AE_NO_MEMORY;
-		goto cleanup;
-	}
-
-
 	/* Install the new table into the local data structures */
 
-	table_info.pointer     = (acpi_table_header *) table_ptr;
-	table_info.length      = table_header.length;
-	table_info.allocation  = ACPI_MEM_ALLOCATED;
-	table_info.base_pointer = table_ptr;
-
-	status = acpi_tb_install_table (NULL, &table_info);
+	status = acpi_ex_add_table (table_ptr, acpi_gbl_root_node, &ddb_handle);
 	if (ACPI_FAILURE (status)) {
 		goto cleanup;
 	}
 
-	/* Add the table to the namespace */
+	/* Store the Ddb_handle into the Target operand */
 
-	/* TBD: [Restructure] - change to whatever new interface is appropriate */
-/*
-	Status = Acpi_load_namespace ();
-	if (ACPI_FAILURE (Status))
-	{
-*/
-		/* TBD: [Errors] Unload the table on failure ? */
-/*
-		goto Cleanup;
+	status = acpi_ex_store (ddb_handle, target, walk_state);
+	if (ACPI_FAILURE (status)) {
+		acpi_ex_unload_table (ddb_handle);
 	}
-*/
-
-
-	/* TBD: [Investigate] we need a pointer to the table desc */
-
-	/* Init the table handle */
-
-	table_desc->reference.opcode = AML_LOAD_OP;
-	table_desc->reference.object = table_info.installed_desc;
-
-	/* TBD: store the tabledesc into the Ddb_handle target */
-	/* Ddb_handle = Table_desc; */
 
 	return_ACPI_STATUS (status);
 
 
 cleanup:
 
-	ACPI_MEM_FREE (table_desc);
-	ACPI_MEM_FREE (table_ptr);
+	if (buffer_desc) {
+		acpi_ut_remove_reference (buffer_desc);
+	}
+	else {
+		ACPI_MEM_FREE (table_ptr);
+	}
 	return_ACPI_STATUS (status);
 }
 
 
-/*****************************************************************************
+/*******************************************************************************
  *
  * FUNCTION:    Acpi_ex_unload_table
  *
@@ -189,7 +396,7 @@
  *
  * DESCRIPTION: Unload an ACPI table
  *
- ****************************************************************************/
+ ******************************************************************************/
 
 acpi_status
 acpi_ex_unload_table (
@@ -200,7 +407,7 @@
 	acpi_table_desc         *table_info;
 
 
-	FUNCTION_TRACE ("Ex_unload_table");
+	ACPI_FUNCTION_TRACE ("Ex_unload_table");
 
 
 	/*
@@ -210,7 +417,7 @@
 	 * validated here.
 	 */
 	if ((!ddb_handle) ||
-		(!VALID_DESCRIPTOR_TYPE (ddb_handle, ACPI_DESC_TYPE_INTERNAL)) ||
+		(ACPI_GET_DESCRIPTOR_TYPE (ddb_handle) != ACPI_DESC_TYPE_INTERNAL) ||
 		(((acpi_operand_object  *)ddb_handle)->common.type !=
 				INTERNAL_TYPE_REFERENCE)) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
@@ -236,7 +443,6 @@
 	/* Delete the table descriptor (Ddb_handle) */
 
 	acpi_ut_remove_reference (table_desc);
-
 	return_ACPI_STATUS (status);
 }
 
diff -Nru a/drivers/acpi/executer/exconvrt.c b/drivers/acpi/executer/exconvrt.c
--- a/drivers/acpi/executer/exconvrt.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exconvrt.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: exconvrt - Object conversion routines
- *              $Revision: 24 $
+ *              $Revision: 30 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exconvrt")
+	 ACPI_MODULE_NAME    ("exconvrt")
 
 
 /*******************************************************************************
@@ -65,13 +65,13 @@
 	u32                     integer_size = sizeof (acpi_integer);
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_TRACE_PTR ("Ex_convert_to_integer", obj_desc);
 
 
 	switch (obj_desc->common.type) {
 	case ACPI_TYPE_INTEGER:
 		*result_desc = obj_desc;
-		return (AE_OK);
+		return_ACPI_STATUS (AE_OK);
 
 	case ACPI_TYPE_STRING:
 		pointer = obj_desc->string.pointer;
@@ -84,7 +84,7 @@
 		break;
 
 	default:
-		return (AE_TYPE);
+		return_ACPI_STATUS (AE_TYPE);
 	}
 
 	/*
@@ -92,10 +92,9 @@
 	 */
 	ret_desc = acpi_ut_create_internal_object (ACPI_TYPE_INTEGER);
 	if (!ret_desc) {
-		return (AE_NO_MEMORY);
+		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
-
 	/* Handle both ACPI 1.0 and ACPI 2.0 Integer widths */
 
 	if (walk_state->method_node->flags & ANOBJ_DATA_WIDTH_32) {
@@ -106,7 +105,6 @@
 		integer_size = sizeof (u32);
 	}
 
-
 	/*
 	 * Convert the buffer/string to an integer.  Note that both buffers and
 	 * strings are treated as raw data - we don't convert ascii to hex for
@@ -130,13 +128,13 @@
 	switch (obj_desc->common.type) {
 	case ACPI_TYPE_STRING:
 
-		/* TBD: Need to use 64-bit STRTOUL */
+		/* TBD: Need to use 64-bit ACPI_STRTOUL */
 
 		/*
 		 * Convert string to an integer
 		 * String must be hexadecimal as per the ACPI specification
 		 */
-		result = STRTOUL (pointer, NULL, 16);
+		result = ACPI_STRTOUL (pointer, NULL, 16);
 		break;
 
 
@@ -154,7 +152,6 @@
 			 */
 			result |= (((acpi_integer) pointer[i]) << (i * 8));
 		}
-
 		break;
 	}
 
@@ -169,7 +166,7 @@
 	}
 
 	*result_desc = ret_desc;
-	return (AE_OK);
+	return_ACPI_STATUS (AE_OK);
 }
 
 
@@ -199,7 +196,7 @@
 	u8                      *new_buf;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_TRACE_PTR ("Ex_convert_to_buffer", obj_desc);
 
 
 	switch (obj_desc->common.type) {
@@ -210,7 +207,7 @@
 		 */
 		ret_desc = acpi_ut_create_internal_object (ACPI_TYPE_BUFFER);
 		if (!ret_desc) {
-			return (AE_NO_MEMORY);
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
 		/* Handle both ACPI 1.0 and ACPI 2.0 Integer widths */
@@ -224,15 +221,15 @@
 			integer_size = sizeof (u32);
 		}
 
-		/* Need enough space for one integers */
+		/* Need enough space for one integer */
 
 		ret_desc->buffer.length = integer_size;
 		new_buf = ACPI_MEM_CALLOCATE (integer_size);
 		if (!new_buf) {
-			REPORT_ERROR
+			ACPI_REPORT_ERROR
 				(("Ex_convert_to_buffer: Buffer allocation failure\n"));
 			acpi_ut_remove_reference (ret_desc);
-			return (AE_NO_MEMORY);
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
 		/* Copy the integer to the buffer */
@@ -244,12 +241,6 @@
 
 		/* Return the new buffer descriptor */
 
-		if (*result_desc == obj_desc) {
-			if (walk_state->opcode != AML_STORE_OP) {
-				acpi_ut_remove_reference (obj_desc);
-			}
-		}
-
 		*result_desc = ret_desc;
 		break;
 
@@ -265,11 +256,10 @@
 
 
 	default:
-		return (AE_TYPE);
-		break;
-   }
+		return_ACPI_STATUS (AE_TYPE);
+	}
 
-	return (AE_OK);
+	return_ACPI_STATUS (AE_OK);
 }
 
 
@@ -301,7 +291,7 @@
 	u8                      leading_zero = TRUE;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	switch (base) {
@@ -323,7 +313,7 @@
 			}
 
 			if (!leading_zero) {
-				string[k] = (u8) (ASCII_ZERO + remainder);
+				string[k] = (u8) (ACPI_ASCII_ZERO + remainder);
 				k++;
 			}
 		}
@@ -336,7 +326,7 @@
 		for (i = 0, j = ((length * 2) -1); i < (length * 2); i++, j--) {
 
 			hex_digit = acpi_ut_hex_to_ascii_char (integer, (j * 4));
-			if (hex_digit != ASCII_ZERO) {
+			if (hex_digit != ACPI_ASCII_ZERO) {
 				leading_zero = FALSE;
 			}
 
@@ -358,7 +348,7 @@
 	 * Finally, null terminate the string and return the length
 	 */
 	if (!k) {
-		string [0] = ASCII_ZERO;
+		string [0] = ACPI_ASCII_ZERO;
 		k = 1;
 	}
 	string [k] = 0;
@@ -398,7 +388,7 @@
 	u8                      *pointer;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_TRACE_PTR ("Ex_convert_to_string", obj_desc);
 
 
 	switch (obj_desc->common.type) {
@@ -425,17 +415,17 @@
 		 */
 		ret_desc = acpi_ut_create_internal_object (ACPI_TYPE_STRING);
 		if (!ret_desc) {
-			return (AE_NO_MEMORY);
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
 		/* Need enough space for one ASCII integer plus null terminator */
 
 		new_buf = ACPI_MEM_CALLOCATE (string_length + 1);
 		if (!new_buf) {
-			REPORT_ERROR
+			ACPI_REPORT_ERROR
 				(("Ex_convert_to_string: Buffer allocation failure\n"));
 			acpi_ut_remove_reference (ret_desc);
-			return (AE_NO_MEMORY);
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
 
@@ -477,7 +467,7 @@
 
 		if (max_length > ACPI_MAX_STRING_CONVERSION) {
 			if (string_length > ACPI_MAX_STRING_CONVERSION) {
-				return (AE_AML_STRING_LIMIT);
+				return_ACPI_STATUS (AE_AML_STRING_LIMIT);
 			}
 		}
 
@@ -486,7 +476,7 @@
 		 */
 		ret_desc = acpi_ut_create_internal_object (ACPI_TYPE_STRING);
 		if (!ret_desc) {
-			return (AE_NO_MEMORY);
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
 		/* String length is the lesser of the Max or the actual length */
@@ -497,10 +487,10 @@
 
 		new_buf = ACPI_MEM_CALLOCATE (string_length + 1);
 		if (!new_buf) {
-			REPORT_ERROR
+			ACPI_REPORT_ERROR
 				(("Ex_convert_to_string: Buffer allocation failure\n"));
 			acpi_ut_remove_reference (ret_desc);
-			return (AE_NO_MEMORY);
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
 		/*
@@ -519,7 +509,7 @@
 
 		new_buf [index-1] = 0;
 		ret_desc->buffer.pointer = new_buf;
-		ret_desc->string.length = STRLEN ((char *) new_buf);
+		ret_desc->string.length = ACPI_STRLEN ((char *) new_buf);
 
 
 		/* Return the new buffer descriptor */
@@ -543,17 +533,16 @@
 		else {
 			/* Must copy the string first and then truncate it */
 
-			return (AE_NOT_IMPLEMENTED);
+			return_ACPI_STATUS (AE_NOT_IMPLEMENTED);
 		}
 		break;
 
 
 	default:
-		return (AE_TYPE);
-		break;
-   }
+		return_ACPI_STATUS (AE_TYPE);
+	}
 
-	return (AE_OK);
+	return_ACPI_STATUS (AE_OK);
 }
 
 
@@ -561,27 +550,33 @@
  *
  * FUNCTION:    Acpi_ex_convert_to_target_type
  *
- * PARAMETERS:  *Obj_desc       - Object to be converted.
- *              Walk_state      - Current method state
+ * PARAMETERS:  Destination_type    - Current type of the destination
+ *              Source_desc         - Source object to be converted.
+ *              Walk_state          - Current method state
  *
  * RETURN:      Status
  *
- * DESCRIPTION:
+ * DESCRIPTION: Implements "implicit conversion" rules for storing an object.
  *
  ******************************************************************************/
 
 acpi_status
 acpi_ex_convert_to_target_type (
-	acpi_object_type8       destination_type,
-	acpi_operand_object     **obj_desc,
+	acpi_object_type        destination_type,
+	acpi_operand_object     *source_desc,
+	acpi_operand_object     **result_desc,
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_convert_to_target_type");
+	ACPI_FUNCTION_TRACE ("Ex_convert_to_target_type");
 
 
+	/* Default behavior */
+
+	*result_desc = source_desc;
+
 	/*
 	 * If required by the target,
 	 * perform implicit conversion on the source before we store it.
@@ -601,10 +596,10 @@
 		default:
 			/* No conversion allowed for these types */
 
-			if (destination_type != (*obj_desc)->common.type) {
+			if (destination_type != source_desc->common.type) {
 				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 					"Target does not allow conversion of type %s to %s\n",
-					acpi_ut_get_type_name ((*obj_desc)->common.type),
+					acpi_ut_get_type_name ((source_desc)->common.type),
 					acpi_ut_get_type_name (destination_type)));
 				status = AE_TYPE;
 			}
@@ -623,7 +618,7 @@
 			 * These types require an Integer operand.  We can convert
 			 * a Buffer or a String to an Integer if necessary.
 			 */
-			status = acpi_ex_convert_to_integer (*obj_desc, obj_desc, walk_state);
+			status = acpi_ex_convert_to_integer (source_desc, result_desc, walk_state);
 			break;
 
 
@@ -633,17 +628,17 @@
 			 * The operand must be a String.  We can convert an
 			 * Integer or Buffer if necessary
 			 */
-			status = acpi_ex_convert_to_string (*obj_desc, obj_desc, 16, ACPI_UINT32_MAX, walk_state);
+			status = acpi_ex_convert_to_string (source_desc, result_desc, 16, ACPI_UINT32_MAX, walk_state);
 			break;
 
 
 		case ACPI_TYPE_BUFFER:
 
 			/*
-			 * The operand must be a String.  We can convert an
-			 * Integer or Buffer if necessary
+			 * The operand must be a Buffer.  We can convert an
+			 * Integer or String if necessary
 			 */
-			status = acpi_ex_convert_to_buffer (*obj_desc, obj_desc, walk_state);
+			status = acpi_ex_convert_to_buffer (source_desc, result_desc, walk_state);
 			break;
 		}
 		break;
diff -Nru a/drivers/acpi/executer/excreate.c b/drivers/acpi/executer/excreate.c
--- a/drivers/acpi/executer/excreate.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/excreate.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: excreate - Named object creation
- *              $Revision: 71 $
+ *              $Revision: 89 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,10 +31,11 @@
 #include "acnamesp.h"
 #include "acevents.h"
 #include "acdispat.h"
+#include "actables.h"
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("excreate")
+	 ACPI_MODULE_NAME    ("excreate")
 
 
 /*****************************************************************************
@@ -58,7 +59,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ex_create_alias");
+	ACPI_FUNCTION_TRACE ("Ex_create_alias");
 
 
 	/* Get the source/alias operands (both namespace nodes) */
@@ -69,7 +70,7 @@
 	/* Attach the original source object to the new Alias Node */
 
 	status = acpi_ns_attach_object ((acpi_namespace_node *) walk_state->operands[0],
-			   source_node->object,
+			   acpi_ns_get_attached_object (source_node),
 			   source_node->type);
 
 	/*
@@ -105,7 +106,7 @@
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE ("Ex_create_event");
+	ACPI_FUNCTION_TRACE ("Ex_create_event");
 
 
 	obj_desc = acpi_ut_create_internal_object (ACPI_TYPE_EVENT);
@@ -114,11 +115,11 @@
 		goto cleanup;
 	}
 
-	/* Create the actual OS semaphore */
-
-	/* TBD: [Investigate] should be created with 0 or 1 units? */
-
-	status = acpi_os_create_semaphore (ACPI_NO_UNIT_LIMIT, 1,
+	/*
+	 * Create the actual OS semaphore, with zero initial units -- meaning
+	 * that the event is created in an unsignalled state
+	 */
+	status = acpi_os_create_semaphore (ACPI_NO_UNIT_LIMIT, 0,
 			   &obj_desc->event.semaphore);
 	if (ACPI_FAILURE (status)) {
 		goto cleanup;
@@ -127,7 +128,7 @@
 	/* Attach object to the Node */
 
 	status = acpi_ns_attach_object ((acpi_namespace_node *) walk_state->operands[0],
-			   obj_desc, (u8) ACPI_TYPE_EVENT);
+			   obj_desc, ACPI_TYPE_EVENT);
 
 cleanup:
 	/*
@@ -161,7 +162,7 @@
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE_PTR ("Ex_create_mutex", WALK_OPERANDS);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_create_mutex", ACPI_WALK_OPERANDS);
 
 
 	/* Create the new mutex object */
@@ -172,8 +173,11 @@
 		goto cleanup;
 	}
 
-	/* Create the actual OS semaphore */
-
+	/*
+	 * Create the actual OS semaphore.
+	 * One unit max to make it a mutex, with one initial unit to allow
+	 * the mutex to be acquired.
+	 */
 	status = acpi_os_create_semaphore (1, 1, &obj_desc->mutex.semaphore);
 	if (ACPI_FAILURE (status)) {
 		goto cleanup;
@@ -184,7 +188,7 @@
 	obj_desc->mutex.sync_level = (u8) walk_state->operands[1]->integer.value;
 
 	status = acpi_ns_attach_object ((acpi_namespace_node *) walk_state->operands[0],
-			  obj_desc, (u8) ACPI_TYPE_MUTEX);
+			  obj_desc, ACPI_TYPE_MUTEX);
 
 
 cleanup:
@@ -222,20 +226,21 @@
 	acpi_status             status;
 	acpi_operand_object     *obj_desc;
 	acpi_namespace_node     *node;
+	acpi_operand_object     *region_obj2;
 
 
-	FUNCTION_TRACE ("Ex_create_region");
+	ACPI_FUNCTION_TRACE ("Ex_create_region");
 
 
 	/* Get the Node from the object stack  */
 
-	node = (acpi_namespace_node *) walk_state->operands[0];
+	node = walk_state->op->node;
 
 	/*
 	 * If the region object is already attached to this node,
 	 * just return
 	 */
-	if (node->object) {
+	if (acpi_ns_get_attached_object (node)) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
@@ -243,9 +248,9 @@
 	 * Space ID must be one of the predefined IDs, or in the user-defined
 	 * range
 	 */
-	if ((region_space >= NUM_REGION_TYPES) &&
-		(region_space < USER_REGION_BEGIN)) {
-		REPORT_ERROR (("Invalid Address_space type %X\n", region_space));
+	if ((region_space >= ACPI_NUM_PREDEFINED_REGIONS) &&
+		(region_space < ACPI_USER_REGION_BEGIN)) {
+		ACPI_REPORT_ERROR (("Invalid Address_space type %X\n", region_space));
 		return_ACPI_STATUS (AE_AML_INVALID_SPACE_ID);
 	}
 
@@ -261,21 +266,13 @@
 		goto cleanup;
 	}
 
-	/* Allocate a method object for this region */
-
-	obj_desc->region.extra = acpi_ut_create_internal_object (
-			 INTERNAL_TYPE_EXTRA);
-	if (!obj_desc->region.extra) {
-		status = AE_NO_MEMORY;
-		goto cleanup;
-	}
-
 	/*
 	 * Remember location in AML stream of address & length
 	 * operands since they need to be evaluated at run time.
 	 */
-	obj_desc->region.extra->extra.aml_start = aml_start;
-	obj_desc->region.extra->extra.aml_length = aml_length;
+	region_obj2                 = obj_desc->common.next_object;
+	region_obj2->extra.aml_start = aml_start;
+	region_obj2->extra.aml_length = aml_length;
 
 	/* Init the region from the operands */
 
@@ -286,34 +283,14 @@
 
 	/* Install the new region object in the parent Node */
 
-	status = acpi_ns_attach_object (node, obj_desc,
-			  (u8) ACPI_TYPE_REGION);
-	if (ACPI_FAILURE (status)) {
-		goto cleanup;
-	}
+	status = acpi_ns_attach_object (node, obj_desc, ACPI_TYPE_REGION);
 
-	/*
-	 * If we have a valid region, initialize it
-	 * Namespace is NOT locked at this point.
-	 */
-	status = acpi_ev_initialize_region (obj_desc, FALSE);
-	if (ACPI_FAILURE (status)) {
-		/*
-		 *  If AE_NOT_EXIST is returned, it is not fatal
-		 *  because many regions get created before a handler
-		 *  is installed for said region.
-		 */
-		if (AE_NOT_EXIST == status) {
-			status = AE_OK;
-		}
-	}
 
 cleanup:
 
 	/* Remove local reference to the object */
 
 	acpi_ut_remove_reference (obj_desc);
-
 	return_ACPI_STATUS (status);
 }
 
@@ -334,24 +311,81 @@
 acpi_ex_create_table_region (
 	acpi_walk_state         *walk_state)
 {
-	acpi_status             status = AE_OK;
+	acpi_status             status;
+	acpi_operand_object     **operand = &walk_state->operands[0];
+	acpi_operand_object     *obj_desc;
+	acpi_namespace_node     *node;
+	acpi_table_header       *table;
+	acpi_operand_object     *region_obj2;
 
 
-	FUNCTION_TRACE ("Ex_create_table_region");
+	ACPI_FUNCTION_TRACE ("Ex_create_table_region");
 
-/*
-	acpi_operand_object     *Obj_desc;
-	Obj_desc = Acpi_ut_create_internal_object (ACPI_TYPE_REGION);
-	if (!Obj_desc)
-	{
-		Status = AE_NO_MEMORY;
-		goto Cleanup;
+	/* Get the Node from the object stack  */
+
+	node = walk_state->op->node;
+
+	/*
+	 * If the region object is already attached to this node,
+	 * just return
+	 */
+	if (acpi_ns_get_attached_object (node)) {
+		return_ACPI_STATUS (AE_OK);
+	}
+
+	/* Find the ACPI table */
+
+	status = acpi_tb_find_table (operand[1]->string.pointer,
+			   operand[2]->string.pointer,
+			   operand[3]->string.pointer, &table);
+
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
+	/* Create the region descriptor */
 
-Cleanup:
-*/
+	obj_desc = acpi_ut_create_internal_object (ACPI_TYPE_REGION);
+	if (!obj_desc) {
+		return_ACPI_STATUS (AE_NO_MEMORY);
+	}
+
+	region_obj2                     = obj_desc->common.next_object;
+	region_obj2->extra.region_context = NULL;
+
+	/* Init the region from the operands */
+
+	obj_desc->region.space_id = REGION_DATA_TABLE;
+	obj_desc->region.address = (ACPI_PHYSICAL_ADDRESS) ACPI_TO_INTEGER (table);
+	obj_desc->region.length = table->length;
+	obj_desc->region.node   = node;
+	obj_desc->region.flags  = AOPOBJ_DATA_VALID;
+
+	/* Install the new region object in the parent Node */
 
+	status = acpi_ns_attach_object (node, obj_desc, ACPI_TYPE_REGION);
+	if (ACPI_FAILURE (status)) {
+		goto cleanup;
+	}
+
+	status = acpi_ev_initialize_region (obj_desc, FALSE);
+	if (ACPI_FAILURE (status)) {
+		if (status == AE_NOT_EXIST) {
+			status = AE_OK;
+		}
+		else {
+			goto cleanup;
+		}
+	}
+
+	obj_desc->region.flags |= AOPOBJ_SETUP_COMPLETE;
+
+
+cleanup:
+
+	/* Remove local reference to the object */
+
+	acpi_ut_remove_reference (obj_desc);
 	return_ACPI_STATUS (status);
 }
 
@@ -381,7 +415,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ex_create_processor", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_create_processor", walk_state);
 
 
 	/* Create the processor object */
@@ -401,7 +435,7 @@
 	/* Install the processor object in the parent Node */
 
 	status = acpi_ns_attach_object ((acpi_namespace_node *) operand[0],
-			  obj_desc, (u8) ACPI_TYPE_PROCESSOR);
+			  obj_desc, ACPI_TYPE_PROCESSOR);
 
 
 	/* Remove local reference to the object */
@@ -436,7 +470,7 @@
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE_PTR ("Ex_create_power_resource", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_create_power_resource", walk_state);
 
 
 	/* Create the power resource object */
@@ -454,7 +488,7 @@
 	/* Install the  power resource object in the parent Node */
 
 	status = acpi_ns_attach_object ((acpi_namespace_node *) operand[0],
-			  obj_desc, (u8) ACPI_TYPE_POWER);
+			  obj_desc, ACPI_TYPE_POWER);
 
 
 	/* Remove local reference to the object */
@@ -491,7 +525,7 @@
 	u8                      method_flags;
 
 
-	FUNCTION_TRACE_PTR ("Ex_create_method", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_create_method", walk_state);
 
 
 	/* Create a new method object */
@@ -533,7 +567,7 @@
 	/* Attach the new object to the method Node */
 
 	status = acpi_ns_attach_object ((acpi_namespace_node *) operand[0],
-			  obj_desc, (u8) ACPI_TYPE_METHOD);
+			  obj_desc, ACPI_TYPE_METHOD);
 
 	/* Remove local reference to the object */
 
diff -Nru a/drivers/acpi/executer/exdump.c b/drivers/acpi/executer/exdump.c
--- a/drivers/acpi/executer/exdump.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exdump.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: exdump - Interpreter debug output routines
- *              $Revision: 126 $
+ *              $Revision: 145 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acparser.h"
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exdump")
+	 ACPI_MODULE_NAME    ("exdump")
 
 
 /*
@@ -69,11 +69,16 @@
 	u8                      *current_aml_ptr = NULL; /* Pointer to current byte of AML value    */
 
 
-	FUNCTION_TRACE ("Ex_show_hex_value");
+	ACPI_FUNCTION_TRACE ("Ex_show_hex_value");
 
 
+	if (!((ACPI_LV_LOAD & acpi_dbg_level) && (_COMPONENT & acpi_dbg_layer))) {
+		return;
+	}
+
 	if (!aml_start) {
-		REPORT_ERROR (("Ex_show_hex_value: null pointer\n"));
+		ACPI_REPORT_ERROR (("Ex_show_hex_value: null pointer\n"));
+		return;
 	}
 
 	/*
@@ -97,26 +102,25 @@
 	}
 
 	for (length = lead_space; length; --length ) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_LOAD, " "));
+		acpi_os_printf (" ");
 	}
 
 	while (byte_count--) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_LOAD, "%02x", *aml_start++));
-
+		acpi_os_printf ("%02x", *aml_start++);
 		if (byte_count) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_LOAD, " "));
+			acpi_os_printf (" ");
 		}
 	}
 
 	if (show_decimal_value) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_LOAD, " [%d]", value));
+		acpi_os_printf (" [%d]", value);
 	}
 
 	if (0 == lead_space) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_LOAD, " "));
+		acpi_os_printf (" ");
 	}
 
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_LOAD, "\n"));
+	acpi_os_printf ("\n");
 	return_VOID;
 }
 
@@ -125,27 +129,31 @@
  *
  * FUNCTION:    Acpi_ex_dump_operand
  *
- * PARAMETERS:  *Entry_desc         - Pointer to entry to be dumped
+ * PARAMETERS:  *Obj_desc         - Pointer to entry to be dumped
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Dump a stack entry
+ * DESCRIPTION: Dump an operand object
  *
  ****************************************************************************/
 
 acpi_status
 acpi_ex_dump_operand (
-	acpi_operand_object     *entry_desc)
+	acpi_operand_object     *obj_desc)
 {
 	u8                      *buf = NULL;
 	u32                     length;
 	u32                     i;
 
 
-	PROC_NAME ("Ex_dump_operand")
+	ACPI_FUNCTION_NAME ("Ex_dump_operand")
+
 
+	if (!((ACPI_LV_INFO & acpi_dbg_level) && (_COMPONENT & acpi_dbg_layer))) {
+		return (AE_OK);
+	}
 
-	if (!entry_desc) {
+	if (!obj_desc) {
 		/*
 		 * This usually indicates that something serious is wrong --
 		 * since most (if not all)
@@ -155,117 +163,117 @@
 		return (AE_OK);
 	}
 
-	if (VALID_DESCRIPTOR_TYPE (entry_desc, ACPI_DESC_TYPE_NAMED)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%p NS Node: ", entry_desc));
-		DUMP_ENTRY (entry_desc, ACPI_LV_INFO);
+	if (ACPI_GET_DESCRIPTOR_TYPE (obj_desc) == ACPI_DESC_TYPE_NAMED) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%p NS Node: ", obj_desc));
+		ACPI_DUMP_ENTRY (obj_desc, ACPI_LV_INFO);
 		return (AE_OK);
 	}
 
-	if (!VALID_DESCRIPTOR_TYPE (entry_desc, ACPI_DESC_TYPE_INTERNAL)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%p Is not a local object \n", entry_desc));
-		DUMP_BUFFER (entry_desc, sizeof (acpi_operand_object));
+	if (ACPI_GET_DESCRIPTOR_TYPE (obj_desc) != ACPI_DESC_TYPE_INTERNAL) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%p is not a local object\n", obj_desc));
+		ACPI_DUMP_BUFFER (obj_desc, sizeof (acpi_operand_object));
 		return (AE_OK);
 	}
 
-	/*  Entry_desc is a valid object */
+	/*  Obj_desc is a valid object */
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%p ", entry_desc));
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%p ", obj_desc));
 
-	switch (entry_desc->common.type) {
+	switch (obj_desc->common.type) {
 	case INTERNAL_TYPE_REFERENCE:
 
-		switch (entry_desc->reference.opcode) {
+		switch (obj_desc->reference.opcode) {
 		case AML_ZERO_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Zero\n"));
+			acpi_os_printf ("Reference: Zero\n");
 			break;
 
 
 		case AML_ONE_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: One\n"));
+			acpi_os_printf ("Reference: One\n");
 			break;
 
 
 		case AML_ONES_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Ones\n"));
+			acpi_os_printf ("Reference: Ones\n");
 			break;
 
 
 		case AML_REVISION_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Revision\n"));
+			acpi_os_printf ("Reference: Revision\n");
 			break;
 
 
 		case AML_DEBUG_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Debug\n"));
+			acpi_os_printf ("Reference: Debug\n");
 			break;
 
 
 		case AML_NAME_OP:
 
-			DUMP_PATHNAME (entry_desc->reference.object, "Reference: Name: ",
+			ACPI_DUMP_PATHNAME (obj_desc->reference.object, "Reference: Name: ",
 					  ACPI_LV_INFO, _COMPONENT);
-			DUMP_ENTRY (entry_desc->reference.object, ACPI_LV_INFO);
+			ACPI_DUMP_ENTRY (obj_desc->reference.object, ACPI_LV_INFO);
 			break;
 
 
 		case AML_INDEX_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Index %p\n",
-					 entry_desc->reference.object));
+			acpi_os_printf ("Reference: Index %p\n",
+					 obj_desc->reference.object);
 			break;
 
 
 		case AML_ARG_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Arg%d",
-					 entry_desc->reference.offset));
+			acpi_os_printf ("Reference: Arg%d",
+					 obj_desc->reference.offset);
 
-			if (ACPI_TYPE_INTEGER == entry_desc->common.type) {
+			if (ACPI_TYPE_INTEGER == obj_desc->common.type) {
 				/* Value is a Number */
 
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, " value is [%8.8X%8.8x]",
-						  HIDWORD(entry_desc->integer.value),
-						  LODWORD(entry_desc->integer.value)));
+				acpi_os_printf (" value is [%8.8X%8.8x]",
+						 ACPI_HIDWORD(obj_desc->integer.value),
+						 ACPI_LODWORD(obj_desc->integer.value));
 			}
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\n"));
+			acpi_os_printf ("\n");
 			break;
 
 
 		case AML_LOCAL_OP:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference: Local%d",
-					 entry_desc->reference.offset));
+			acpi_os_printf ("Reference: Local%d",
+					 obj_desc->reference.offset);
 
-			if (ACPI_TYPE_INTEGER == entry_desc->common.type) {
+			if (ACPI_TYPE_INTEGER == obj_desc->common.type) {
 
 				/* Value is a Number */
 
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, " value is [%8.8X%8.8x]",
-						  HIDWORD(entry_desc->integer.value),
-						  LODWORD(entry_desc->integer.value)));
+				acpi_os_printf (" value is [%8.8X%8.8x]",
+						 ACPI_HIDWORD(obj_desc->integer.value),
+						 ACPI_LODWORD(obj_desc->integer.value));
 			}
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\n"));
+			acpi_os_printf ("\n");
 			break;
 
 
 		case AML_INT_NAMEPATH_OP:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Reference.Node->Name %X\n",
-					 entry_desc->reference.node->name));
+			acpi_os_printf ("Reference.Node->Name %X\n",
+					 obj_desc->reference.node->name);
 			break;
 
 		default:
 
 			/*  unknown opcode  */
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Unknown opcode=%X\n",
-				entry_desc->reference.opcode));
+			acpi_os_printf ("Unknown opcode=%X\n",
+				obj_desc->reference.opcode);
 			break;
 
 		}
@@ -275,11 +283,11 @@
 
 	case ACPI_TYPE_BUFFER:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Buffer len %X @ %p \n",
-				 entry_desc->buffer.length,
-				 entry_desc->buffer.pointer));
+		acpi_os_printf ("Buffer len %X @ %p \n",
+				 obj_desc->buffer.length,
+				 obj_desc->buffer.pointer);
 
-		length = entry_desc->buffer.length;
+		length = obj_desc->buffer.length;
 
 		if (length > 64) {
 			length = 64;
@@ -287,13 +295,13 @@
 
 		/* Debug only -- dump the buffer contents */
 
-		if (entry_desc->buffer.pointer) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Buffer Contents: "));
+		if (obj_desc->buffer.pointer) {
+			acpi_os_printf ("Buffer Contents: ");
 
-			for (buf = entry_desc->buffer.pointer; length--; ++buf) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, " %02x", *buf));
+			for (buf = obj_desc->buffer.pointer; length--; ++buf) {
+				acpi_os_printf (" %02x", *buf);
 			}
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO,"\n"));
+			acpi_os_printf ("\n");
 		}
 
 		break;
@@ -301,135 +309,136 @@
 
 	case ACPI_TYPE_INTEGER:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Integer %8.8X%8.8X\n",
-				 HIDWORD (entry_desc->integer.value),
-				 LODWORD (entry_desc->integer.value)));
+		acpi_os_printf ("Integer %8.8X%8.8X\n",
+				 ACPI_HIDWORD (obj_desc->integer.value),
+				 ACPI_LODWORD (obj_desc->integer.value));
 		break;
 
 
 	case INTERNAL_TYPE_IF:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "If [Integer] %8.8X%8.8X\n",
-				 HIDWORD (entry_desc->integer.value),
-				 LODWORD (entry_desc->integer.value)));
+		acpi_os_printf ("If [Integer] %8.8X%8.8X\n",
+				 ACPI_HIDWORD (obj_desc->integer.value),
+				 ACPI_LODWORD (obj_desc->integer.value));
 		break;
 
 
 	case INTERNAL_TYPE_WHILE:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "While [Integer] %8.8X%8.8X\n",
-				 HIDWORD (entry_desc->integer.value),
-				 LODWORD (entry_desc->integer.value)));
+		acpi_os_printf ("While [Integer] %8.8X%8.8X\n",
+				 ACPI_HIDWORD (obj_desc->integer.value),
+				 ACPI_LODWORD (obj_desc->integer.value));
 		break;
 
 
 	case ACPI_TYPE_PACKAGE:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Package count %X @ %p\n",
-				 entry_desc->package.count, entry_desc->package.elements));
+		acpi_os_printf ("Package count %X @ %p\n",
+				 obj_desc->package.count, obj_desc->package.elements);
 
 		/*
 		 * If elements exist, package vector pointer is valid,
 		 * and debug_level exceeds 1, dump package's elements.
 		 */
-		if (entry_desc->package.count &&
-			entry_desc->package.elements &&
+		if (obj_desc->package.count &&
+			obj_desc->package.elements &&
 			acpi_dbg_level > 1) {
 			acpi_operand_object**element;
 			u16                 element_index;
 
-			for (element_index = 0, element = entry_desc->package.elements;
-				  element_index < entry_desc->package.count;
+			for (element_index = 0, element = obj_desc->package.elements;
+				  element_index < obj_desc->package.count;
 				  ++element_index, ++element) {
 				acpi_ex_dump_operand (*element);
 			}
 		}
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\n"));
+		acpi_os_printf ("\n");
 
 		break;
 
 
 	case ACPI_TYPE_REGION:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Region %s (%X)",
-			acpi_ut_get_region_name (entry_desc->region.space_id),
-			entry_desc->region.space_id));
+		acpi_os_printf ("Region %s (%X)",
+			acpi_ut_get_region_name (obj_desc->region.space_id),
+			obj_desc->region.space_id);
 
 		/*
 		 * If the address and length have not been evaluated,
 		 * don't print them.
 		 */
-		if (!(entry_desc->region.flags & AOPOBJ_DATA_VALID)) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\n"));
+		if (!(obj_desc->region.flags & AOPOBJ_DATA_VALID)) {
+			acpi_os_printf ("\n");
 		}
 		else {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, " base %8.8X%8.8X Length %X\n",
-				HIDWORD(entry_desc->region.address),
-				LODWORD(entry_desc->region.address),
-				entry_desc->region.length));
+			acpi_os_printf (" base %8.8X%8.8X Length %X\n",
+				ACPI_HIDWORD (obj_desc->region.address),
+				ACPI_LODWORD (obj_desc->region.address),
+				obj_desc->region.length);
 		}
 		break;
 
 
 	case ACPI_TYPE_STRING:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "String length %X @ %p \"",
-				 entry_desc->string.length, entry_desc->string.pointer));
+		acpi_os_printf ("String length %X @ %p \"",
+				 obj_desc->string.length, obj_desc->string.pointer);
 
-		for (i = 0; i < entry_desc->string.length; i++) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "%c",
-					 entry_desc->string.pointer[i]));
+		for (i = 0; i < obj_desc->string.length; i++) {
+			acpi_os_printf ("%c",
+					 obj_desc->string.pointer[i]);
 		}
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\"\n"));
+		acpi_os_printf ("\"\n");
 		break;
 
 
 	case INTERNAL_TYPE_BANK_FIELD:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Bank_field\n"));
+		acpi_os_printf ("Bank_field\n");
 		break;
 
 
 	case INTERNAL_TYPE_REGION_FIELD:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO,
-			"Region_field: bits=%X bitaccwidth=%X lock=%X update=%X at byte=%X bit=%X of below:\n",
-			entry_desc->field.bit_length,    entry_desc->field.access_bit_width,
-			entry_desc->field.lock_rule,     entry_desc->field.update_rule,
-			entry_desc->field.base_byte_offset, entry_desc->field.start_field_bit_offset));
-		DUMP_STACK_ENTRY (entry_desc->field.region_obj);
+		acpi_os_printf (
+			"Region_field: Bits=%X Acc_width=%X Lock=%X Update=%X at byte=%X bit=%X of below:\n",
+			obj_desc->field.bit_length, obj_desc->field.access_byte_width,
+			obj_desc->field.field_flags & AML_FIELD_LOCK_RULE_MASK,
+			obj_desc->field.field_flags & AML_FIELD_UPDATE_RULE_MASK,
+			obj_desc->field.base_byte_offset, obj_desc->field.start_field_bit_offset);
+		ACPI_DUMP_STACK_ENTRY (obj_desc->field.region_obj);
 		break;
 
 
 	case INTERNAL_TYPE_INDEX_FIELD:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Index_field\n"));
+		acpi_os_printf ("Index_field\n");
 		break;
 
 
 	case ACPI_TYPE_BUFFER_FIELD:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO,
+		acpi_os_printf (
 			"Buffer_field: %X bits at byte %X bit %X of \n",
-			entry_desc->buffer_field.bit_length, entry_desc->buffer_field.base_byte_offset,
-			entry_desc->buffer_field.start_field_bit_offset));
+			obj_desc->buffer_field.bit_length, obj_desc->buffer_field.base_byte_offset,
+			obj_desc->buffer_field.start_field_bit_offset);
 
-		if (!entry_desc->buffer_field.buffer_obj)
+		if (!obj_desc->buffer_field.buffer_obj)
 		{
 			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "*NULL* \n"));
 		}
 
 		else if (ACPI_TYPE_BUFFER !=
-				  entry_desc->buffer_field.buffer_obj->common.type)
+				  obj_desc->buffer_field.buffer_obj->common.type)
 		{
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "*not a Buffer* \n"));
+			acpi_os_printf ("*not a Buffer* \n");
 		}
 
 		else
 		{
-			DUMP_STACK_ENTRY (entry_desc->buffer_field.buffer_obj);
+			ACPI_DUMP_STACK_ENTRY (obj_desc->buffer_field.buffer_obj);
 		}
 
 		break;
@@ -437,68 +446,54 @@
 
 	case ACPI_TYPE_EVENT:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Event\n"));
+		acpi_os_printf ("Event\n");
 		break;
 
 
 	case ACPI_TYPE_METHOD:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO,
+		acpi_os_printf (
 			"Method(%X) @ %p:%X\n",
-			entry_desc->method.param_count,
-			entry_desc->method.aml_start, entry_desc->method.aml_length));
+			obj_desc->method.param_count,
+			obj_desc->method.aml_start, obj_desc->method.aml_length);
 		break;
 
 
 	case ACPI_TYPE_MUTEX:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Mutex\n"));
+		acpi_os_printf ("Mutex\n");
 		break;
 
 
 	case ACPI_TYPE_DEVICE:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Device\n"));
+		acpi_os_printf ("Device\n");
 		break;
 
 
 	case ACPI_TYPE_POWER:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Power\n"));
+		acpi_os_printf ("Power\n");
 		break;
 
 
 	case ACPI_TYPE_PROCESSOR:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Processor\n"));
+		acpi_os_printf ("Processor\n");
 		break;
 
 
 	case ACPI_TYPE_THERMAL:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Thermal\n"));
+		acpi_os_printf ("Thermal\n");
 		break;
 
 
 	default:
-		/*  unknown Entry_desc->Common.Type value   */
+		/*  unknown Obj_desc->Common.Type value   */
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "Unknown Type %X\n",
-			entry_desc->common.type));
-
-		/* Back up to previous entry */
-
-		entry_desc--;
-
-
-		/* TBD: [Restructure]  Change to use dump object routine !! */
-		/*       What is all of this?? */
-
-		DUMP_BUFFER (entry_desc, sizeof (acpi_operand_object));
-		DUMP_BUFFER (++entry_desc, sizeof (acpi_operand_object));
-		DUMP_BUFFER (++entry_desc, sizeof (acpi_operand_object));
+		acpi_os_printf ("Unknown Type %X\n", obj_desc->common.type);
 		break;
-
 	}
 
 	return (AE_OK);
@@ -521,7 +516,7 @@
 void
 acpi_ex_dump_operands (
 	acpi_operand_object     **operands,
-	operating_mode          interpreter_mode,
+	acpi_interpreter_mode   interpreter_mode,
 	NATIVE_CHAR             *ident,
 	u32                     num_levels,
 	NATIVE_CHAR             *note,
@@ -529,10 +524,10 @@
 	u32                     line_number)
 {
 	NATIVE_UINT             i;
-	acpi_operand_object     **entry_desc;
+	acpi_operand_object     **obj_desc;
 
 
-	PROC_NAME ("Ex_dump_operands");
+	ACPI_FUNCTION_NAME ("Ex_dump_operands");
 
 
 	if (!ident)
@@ -559,9 +554,9 @@
 
 	for (i = 0; num_levels > 0; i--, num_levels--)
 	{
-		entry_desc = &operands[i];
+		obj_desc = &operands[i];
 
-		if (ACPI_FAILURE (acpi_ex_dump_operand (*entry_desc)))
+		if (ACPI_FAILURE (acpi_ex_dump_operand (*obj_desc)))
 		{
 			break;
 		}
@@ -576,6 +571,57 @@
 
 /*****************************************************************************
  *
+ * FUNCTION:    Acpi_ex_out*
+ *
+ * PARAMETERS:  Title               - Descriptive text
+ *              Value               - Value to be displayed
+ *
+ * DESCRIPTION: Object dump output formatting functions.  These functions
+ *              reduce the number of format strings required and keeps them
+ *              all in one place for easy modification.
+ *
+ ****************************************************************************/
+
+void
+acpi_ex_out_string (
+	char                    *title,
+	char                    *value)
+{
+	acpi_os_printf ("%20s : %s\n", title, value);
+}
+
+void
+acpi_ex_out_pointer (
+	char                    *title,
+	void                    *value)
+{
+	acpi_os_printf ("%20s : %p\n", title, value);
+}
+
+void
+acpi_ex_out_integer (
+	char                    *title,
+	u32                     value)
+{
+	acpi_os_printf ("%20s : %X\n", title, value);
+}
+
+void
+acpi_ex_out_address (
+	char                    *title,
+	ACPI_PHYSICAL_ADDRESS   value)
+{
+#ifdef _IA16
+	acpi_os_printf ("%20s : %p\n", title, value);
+#else
+	acpi_os_printf ("%20s : %8.8X%8.8X\n", title,
+			 ACPI_HIDWORD (value), ACPI_LODWORD (value));
+#endif
+}
+
+
+/*****************************************************************************
+ *
  * FUNCTION:    Acpi_ex_dump_node
  *
  * PARAMETERS:  *Node           - Descriptor to dump
@@ -591,7 +637,7 @@
 	u32                     flags)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (!flags)
@@ -603,15 +649,15 @@
 	}
 
 
-	acpi_os_printf ("%20s : %4.4s\n", "Name",           (char*)&node->name);
-	acpi_os_printf ("%20s : %s\n",  "Type",             acpi_ut_get_type_name (node->type));
-	acpi_os_printf ("%20s : %X\n",  "Flags",            node->flags);
-	acpi_os_printf ("%20s : %X\n",  "Owner Id",         node->owner_id);
-	acpi_os_printf ("%20s : %X\n",  "Reference Count",  node->reference_count);
-	acpi_os_printf ("%20s : %p\n",  "Attached Object",  node->object);
-	acpi_os_printf ("%20s : %p\n",  "Child_list",       node->child);
-	acpi_os_printf ("%20s : %p\n",  "Next_peer",        node->peer);
-	acpi_os_printf ("%20s : %p\n",  "Parent",           acpi_ns_get_parent_object (node));
+	acpi_os_printf ("%20s : %4.4s\n",     "Name", (char *) &node->name);
+	acpi_ex_out_string ("Type",           acpi_ut_get_type_name (node->type));
+	acpi_ex_out_integer ("Flags",         node->flags);
+	acpi_ex_out_integer ("Owner Id",      node->owner_id);
+	acpi_ex_out_integer ("Reference Count", node->reference_count);
+	acpi_ex_out_pointer ("Attached Object", acpi_ns_get_attached_object (node));
+	acpi_ex_out_pointer ("Child_list",    node->child);
+	acpi_ex_out_pointer ("Next_peer",     node->peer);
+	acpi_ex_out_pointer ("Parent",        acpi_ns_get_parent_node (node));
 }
 
 
@@ -631,10 +677,10 @@
 	acpi_operand_object     *obj_desc,
 	u32                     flags)
 {
-	const acpi_opcode_info  *op_info;
+	u32                     i;
 
 
-	FUNCTION_TRACE ("Ex_dump_object_descriptor");
+	ACPI_FUNCTION_TRACE ("Ex_dump_object_descriptor");
 
 
 	if (!flags)
@@ -645,16 +691,17 @@
 		}
 	}
 
-	if (!(VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_INTERNAL)))
+	if (ACPI_GET_DESCRIPTOR_TYPE (obj_desc) != ACPI_DESC_TYPE_INTERNAL)
 	{
-		acpi_os_printf ("%p is not a valid ACPI object\n", obj_desc);
+		acpi_os_printf ("Ex_dump_object_descriptor: %p is not a valid ACPI object\n", obj_desc);
 		return;
 	}
 
 	/* Common Fields */
 
-	acpi_os_printf ("%20s : %X\n", "Reference Count", obj_desc->common.reference_count);
-	acpi_os_printf ("%20s : %X\n", "Flags", obj_desc->common.flags);
+	acpi_ex_out_string ("Type",          acpi_ut_get_type_name (obj_desc->common.type));
+	acpi_ex_out_integer ("Reference Count", obj_desc->common.reference_count);
+	acpi_ex_out_integer ("Flags",        obj_desc->common.flags);
 
 	/* Object-specific Fields */
 
@@ -662,198 +709,189 @@
 	{
 	case ACPI_TYPE_INTEGER:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Integer");
-		acpi_os_printf ("%20s : %X%8.8X\n", "Value", HIDWORD (obj_desc->integer.value),
-				  LODWORD (obj_desc->integer.value));
+		acpi_os_printf ("%20s : %X%8.8X\n", "Value",
+				  ACPI_HIDWORD (obj_desc->integer.value),
+				  ACPI_LODWORD (obj_desc->integer.value));
 		break;
 
 
 	case ACPI_TYPE_STRING:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "String");
-		acpi_os_printf ("%20s : %X\n", "Length", obj_desc->string.length);
-		acpi_os_printf ("%20s : %p\n", "Pointer", obj_desc->string.pointer);
+		acpi_ex_out_integer ("Length",       obj_desc->string.length);
+		acpi_ex_out_pointer ("Pointer",      obj_desc->string.pointer);
 		break;
 
 
 	case ACPI_TYPE_BUFFER:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Buffer");
-		acpi_os_printf ("%20s : %X\n", "Length", obj_desc->buffer.length);
-		acpi_os_printf ("%20s : %p\n", "Pointer", obj_desc->buffer.pointer);
+		acpi_ex_out_integer ("Length",       obj_desc->buffer.length);
+		acpi_ex_out_pointer ("Pointer",      obj_desc->buffer.pointer);
 		break;
 
 
 	case ACPI_TYPE_PACKAGE:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Package");
-		acpi_os_printf ("%20s : %X\n", "Flags", obj_desc->package.flags);
-		acpi_os_printf ("%20s : %X\n", "Count", obj_desc->package.count);
-		acpi_os_printf ("%20s : %p\n", "Elements", obj_desc->package.elements);
-		acpi_os_printf ("%20s : %p\n", "Next_element", obj_desc->package.next_element);
-		break;
-
+		acpi_ex_out_integer ("Flags",        obj_desc->package.flags);
+		acpi_ex_out_integer ("Count",        obj_desc->package.count);
+		acpi_ex_out_pointer ("Elements",     obj_desc->package.elements);
+		acpi_ex_out_pointer ("Next_element", obj_desc->package.next_element);
 
-	case ACPI_TYPE_BUFFER_FIELD:
+		/* Dump the package contents */
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Buffer_field");
-		acpi_os_printf ("%20s : %X\n", "Bit_length", obj_desc->buffer_field.bit_length);
-		acpi_os_printf ("%20s : %X\n", "Bit_offset", obj_desc->buffer_field.start_field_bit_offset);
-		acpi_os_printf ("%20s : %X\n", "Base_byte_offset",obj_desc->buffer_field.base_byte_offset);
-		acpi_os_printf ("%20s : %p\n", "Buffer_obj", obj_desc->buffer_field.buffer_obj);
+		if (obj_desc->package.count > 0)
+		{
+			acpi_os_printf ("\n_package Contents:\n");
+			for (i = 0; i < obj_desc->package.count; i++)
+			{
+				acpi_os_printf ("[%.3d] %p", i, obj_desc->package.elements[i]);
+				if (obj_desc->package.elements[i])
+				{
+					acpi_os_printf (" %s", acpi_ut_get_type_name ((obj_desc->package.elements[i])->common.type));
+				}
+				acpi_os_printf ("\n");
+			}
+		}
 		break;
 
 
 	case ACPI_TYPE_DEVICE:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Device");
-		acpi_os_printf ("%20s : %p\n", "Addr_handler", obj_desc->device.addr_handler);
-		acpi_os_printf ("%20s : %p\n", "Sys_handler", obj_desc->device.sys_handler);
-		acpi_os_printf ("%20s : %p\n", "Drv_handler", obj_desc->device.drv_handler);
+		acpi_ex_out_pointer ("Addr_handler", obj_desc->device.addr_handler);
+		acpi_ex_out_pointer ("Sys_handler",  obj_desc->device.sys_handler);
+		acpi_ex_out_pointer ("Drv_handler",  obj_desc->device.drv_handler);
 		break;
 
+
 	case ACPI_TYPE_EVENT:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Event");
-		acpi_os_printf ("%20s : %X\n", "Semaphore", obj_desc->event.semaphore);
+		acpi_ex_out_pointer ("Semaphore",    obj_desc->event.semaphore);
 		break;
 
 
 	case ACPI_TYPE_METHOD:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Method");
-		acpi_os_printf ("%20s : %X\n", "Param_count", obj_desc->method.param_count);
-		acpi_os_printf ("%20s : %X\n", "Concurrency", obj_desc->method.concurrency);
-		acpi_os_printf ("%20s : %p\n", "Semaphore", obj_desc->method.semaphore);
-		acpi_os_printf ("%20s : %X\n", "Aml_length", obj_desc->method.aml_length);
-		acpi_os_printf ("%20s : %X\n", "Aml_start", obj_desc->method.aml_start);
+		acpi_ex_out_integer ("Param_count",  obj_desc->method.param_count);
+		acpi_ex_out_integer ("Concurrency",  obj_desc->method.concurrency);
+		acpi_ex_out_pointer ("Semaphore",    obj_desc->method.semaphore);
+		acpi_ex_out_integer ("Owning_id",    obj_desc->method.owning_id);
+		acpi_ex_out_integer ("Aml_length",   obj_desc->method.aml_length);
+		acpi_ex_out_pointer ("Aml_start",    obj_desc->method.aml_start);
 		break;
 
 
 	case ACPI_TYPE_MUTEX:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Mutex");
-		acpi_os_printf ("%20s : %X\n", "Sync_level", obj_desc->mutex.sync_level);
-		acpi_os_printf ("%20s : %p\n", "Owner", obj_desc->mutex.owner);
-		acpi_os_printf ("%20s : %X\n", "Acquisition_depth", obj_desc->mutex.acquisition_depth);
-		acpi_os_printf ("%20s : %p\n", "Semaphore", obj_desc->mutex.semaphore);
+		acpi_ex_out_integer ("Sync_level",   obj_desc->mutex.sync_level);
+		acpi_ex_out_pointer ("Owner_thread", obj_desc->mutex.owner_thread);
+		acpi_ex_out_integer ("Acquisition_depth",obj_desc->mutex.acquisition_depth);
+		acpi_ex_out_pointer ("Semaphore",    obj_desc->mutex.semaphore);
 		break;
 
 
 	case ACPI_TYPE_REGION:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Region");
-		acpi_os_printf ("%20s : %X\n", "Space_id", obj_desc->region.space_id);
-		acpi_os_printf ("%20s : %X\n", "Flags", obj_desc->region.flags);
-		acpi_os_printf ("%20s : %X\n", "Address", obj_desc->region.address);
-		acpi_os_printf ("%20s : %X\n", "Length", obj_desc->region.length);
-		acpi_os_printf ("%20s : %p\n", "Addr_handler", obj_desc->region.addr_handler);
-		acpi_os_printf ("%20s : %p\n", "Next", obj_desc->region.next);
+		acpi_ex_out_integer ("Space_id",     obj_desc->region.space_id);
+		acpi_ex_out_integer ("Flags",        obj_desc->region.flags);
+		acpi_ex_out_address ("Address",      obj_desc->region.address);
+		acpi_ex_out_integer ("Length",       obj_desc->region.length);
+		acpi_ex_out_pointer ("Addr_handler", obj_desc->region.addr_handler);
+		acpi_ex_out_pointer ("Next",         obj_desc->region.next);
 		break;
 
 
 	case ACPI_TYPE_POWER:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Power_resource");
-		acpi_os_printf ("%20s : %X\n", "System_level", obj_desc->power_resource.system_level);
-		acpi_os_printf ("%20s : %X\n", "Resource_order", obj_desc->power_resource.resource_order);
-		acpi_os_printf ("%20s : %p\n", "Sys_handler", obj_desc->power_resource.sys_handler);
-		acpi_os_printf ("%20s : %p\n", "Drv_handler", obj_desc->power_resource.drv_handler);
+		acpi_ex_out_integer ("System_level", obj_desc->power_resource.system_level);
+		acpi_ex_out_integer ("Resource_order", obj_desc->power_resource.resource_order);
+		acpi_ex_out_pointer ("Sys_handler",  obj_desc->power_resource.sys_handler);
+		acpi_ex_out_pointer ("Drv_handler",  obj_desc->power_resource.drv_handler);
 		break;
 
 
 	case ACPI_TYPE_PROCESSOR:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Processor");
-		acpi_os_printf ("%20s : %X\n", "Processor ID", obj_desc->processor.proc_id);
-		acpi_os_printf ("%20s : %X\n", "Length", obj_desc->processor.length);
-		acpi_os_printf ("%20s : %X\n", "Address", obj_desc->processor.address);
-		acpi_os_printf ("%20s : %p\n", "Sys_handler", obj_desc->processor.sys_handler);
-		acpi_os_printf ("%20s : %p\n", "Drv_handler", obj_desc->processor.drv_handler);
-		acpi_os_printf ("%20s : %p\n", "Addr_handler", obj_desc->processor.addr_handler);
+		acpi_ex_out_integer ("Processor ID", obj_desc->processor.proc_id);
+		acpi_ex_out_integer ("Length",       obj_desc->processor.length);
+		acpi_ex_out_integer ("Address",      obj_desc->processor.address);
+		acpi_ex_out_pointer ("Sys_handler",  obj_desc->processor.sys_handler);
+		acpi_ex_out_pointer ("Drv_handler",  obj_desc->processor.drv_handler);
+		acpi_ex_out_pointer ("Addr_handler", obj_desc->processor.addr_handler);
 		break;
 
 
 	case ACPI_TYPE_THERMAL:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Thermal_zone");
-		acpi_os_printf ("%20s : %p\n", "Sys_handler", obj_desc->thermal_zone.sys_handler);
-		acpi_os_printf ("%20s : %p\n", "Drv_handler", obj_desc->thermal_zone.drv_handler);
-		acpi_os_printf ("%20s : %p\n", "Addr_handler", obj_desc->thermal_zone.addr_handler);
+		acpi_ex_out_pointer ("Sys_handler",  obj_desc->thermal_zone.sys_handler);
+		acpi_ex_out_pointer ("Drv_handler",  obj_desc->thermal_zone.drv_handler);
+		acpi_ex_out_pointer ("Addr_handler", obj_desc->thermal_zone.addr_handler);
 		break;
 
 
+	case ACPI_TYPE_BUFFER_FIELD:
 	case INTERNAL_TYPE_REGION_FIELD:
-
-		acpi_os_printf ("%20s : %p\n", "Access_bit_width", obj_desc->field.access_bit_width);
-		acpi_os_printf ("%20s : %p\n", "Bit_length", obj_desc->field.bit_length);
-		acpi_os_printf ("%20s : %p\n", "Base_byte_offset",obj_desc->field.base_byte_offset);
-		acpi_os_printf ("%20s : %p\n", "Bit_offset", obj_desc->field.start_field_bit_offset);
-		acpi_os_printf ("%20s : %p\n", "Region_obj", obj_desc->field.region_obj);
-		break;
-
-
 	case INTERNAL_TYPE_BANK_FIELD:
+	case INTERNAL_TYPE_INDEX_FIELD:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Bank_field");
-		acpi_os_printf ("%20s : %X\n", "Access_bit_width", obj_desc->bank_field.access_bit_width);
-		acpi_os_printf ("%20s : %X\n", "Lock_rule", obj_desc->bank_field.lock_rule);
-		acpi_os_printf ("%20s : %X\n", "Update_rule", obj_desc->bank_field.update_rule);
-		acpi_os_printf ("%20s : %X\n", "Bit_length", obj_desc->bank_field.bit_length);
-		acpi_os_printf ("%20s : %X\n", "Bit_offset", obj_desc->bank_field.start_field_bit_offset);
-		acpi_os_printf ("%20s : %X\n", "Base_byte_offset", obj_desc->bank_field.base_byte_offset);
-		acpi_os_printf ("%20s : %X\n", "Value", obj_desc->bank_field.value);
-		acpi_os_printf ("%20s : %p\n", "Region_obj", obj_desc->bank_field.region_obj);
-		acpi_os_printf ("%20s : %X\n", "Bank_register_obj", obj_desc->bank_field.bank_register_obj);
-		break;
+		acpi_ex_out_integer ("Field_flags",  obj_desc->common_field.field_flags);
+		acpi_ex_out_integer ("Access_byte_width", obj_desc->common_field.access_byte_width);
+		acpi_ex_out_integer ("Bit_length",   obj_desc->common_field.bit_length);
+		acpi_ex_out_integer ("Fld_bit_offset", obj_desc->common_field.start_field_bit_offset);
+		acpi_ex_out_integer ("Base_byte_offset", obj_desc->common_field.base_byte_offset);
+		acpi_ex_out_integer ("Datum_valid_bits", obj_desc->common_field.datum_valid_bits);
+		acpi_ex_out_integer ("End_fld_valid_bits", obj_desc->common_field.end_field_valid_bits);
+		acpi_ex_out_integer ("End_buf_valid_bits", obj_desc->common_field.end_buffer_valid_bits);
+		acpi_ex_out_pointer ("Parent_node",  obj_desc->common_field.node);
 
+		switch (obj_desc->common.type)
+		{
+		case ACPI_TYPE_BUFFER_FIELD:
+			acpi_ex_out_pointer ("Buffer_obj",   obj_desc->buffer_field.buffer_obj);
+			break;
 
-	case INTERNAL_TYPE_INDEX_FIELD:
+		case INTERNAL_TYPE_REGION_FIELD:
+			acpi_ex_out_pointer ("Region_obj",   obj_desc->field.region_obj);
+			break;
+
+		case INTERNAL_TYPE_BANK_FIELD:
+			acpi_ex_out_integer ("Value",        obj_desc->bank_field.value);
+			acpi_ex_out_pointer ("Region_obj",   obj_desc->bank_field.region_obj);
+			acpi_ex_out_pointer ("Bank_obj",     obj_desc->bank_field.bank_obj);
+			break;
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Index_field");
-		acpi_os_printf ("%20s : %X\n", "Access_bit_width", obj_desc->index_field.access_bit_width);
-		acpi_os_printf ("%20s : %X\n", "Lock_rule", obj_desc->index_field.lock_rule);
-		acpi_os_printf ("%20s : %X\n", "Update_rule", obj_desc->index_field.update_rule);
-		acpi_os_printf ("%20s : %X\n", "Bit_length", obj_desc->index_field.bit_length);
-		acpi_os_printf ("%20s : %X\n", "Bit_offset", obj_desc->index_field.start_field_bit_offset);
-		acpi_os_printf ("%20s : %X\n", "Value", obj_desc->index_field.value);
-		acpi_os_printf ("%20s : %X\n", "Index", obj_desc->index_field.index_obj);
-		acpi_os_printf ("%20s : %X\n", "Data", obj_desc->index_field.data_obj);
+		case INTERNAL_TYPE_INDEX_FIELD:
+			acpi_ex_out_integer ("Value",        obj_desc->index_field.value);
+			acpi_ex_out_pointer ("Index",        obj_desc->index_field.index_obj);
+			acpi_ex_out_pointer ("Data",         obj_desc->index_field.data_obj);
+			break;
+		}
 		break;
 
 
 	case INTERNAL_TYPE_REFERENCE:
 
-		op_info = acpi_ps_get_opcode_info (obj_desc->reference.opcode);
-
-		acpi_os_printf ("%20s : %s\n", "Type", "Reference");
-		acpi_os_printf ("%20s : %X\n", "Target_type", obj_desc->reference.target_type);
-		acpi_os_printf ("%20s : %s\n", "Opcode", op_info->name);
-		acpi_os_printf ("%20s : %X\n", "Offset", obj_desc->reference.offset);
-		acpi_os_printf ("%20s : %p\n", "Obj_desc", obj_desc->reference.object);
-		acpi_os_printf ("%20s : %p\n", "Node", obj_desc->reference.node);
-		acpi_os_printf ("%20s : %p\n", "Where", obj_desc->reference.where);
+		acpi_ex_out_integer ("Target_type",  obj_desc->reference.target_type);
+		acpi_ex_out_string ("Opcode",        (acpi_ps_get_opcode_info (obj_desc->reference.opcode))->name);
+		acpi_ex_out_integer ("Offset",       obj_desc->reference.offset);
+		acpi_ex_out_pointer ("Obj_desc",     obj_desc->reference.object);
+		acpi_ex_out_pointer ("Node",         obj_desc->reference.node);
+		acpi_ex_out_pointer ("Where",        obj_desc->reference.where);
 		break;
 
 
 	case INTERNAL_TYPE_ADDRESS_HANDLER:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Address Handler");
-		acpi_os_printf ("%20s : %X\n", "Space_id", obj_desc->addr_handler.space_id);
-		acpi_os_printf ("%20s : %p\n", "Next", obj_desc->addr_handler.next);
-		acpi_os_printf ("%20s : %p\n", "Region_list", obj_desc->addr_handler.region_list);
-		acpi_os_printf ("%20s : %p\n", "Node", obj_desc->addr_handler.node);
-		acpi_os_printf ("%20s : %p\n", "Handler", obj_desc->addr_handler.handler);
-		acpi_os_printf ("%20s : %p\n", "Context", obj_desc->addr_handler.context);
+		acpi_ex_out_integer ("Space_id",     obj_desc->addr_handler.space_id);
+		acpi_ex_out_pointer ("Next",         obj_desc->addr_handler.next);
+		acpi_ex_out_pointer ("Region_list",  obj_desc->addr_handler.region_list);
+		acpi_ex_out_pointer ("Node",         obj_desc->addr_handler.node);
+		acpi_ex_out_pointer ("Context",      obj_desc->addr_handler.context);
 		break;
 
 
 	case INTERNAL_TYPE_NOTIFY:
 
-		acpi_os_printf ("%20s : %s\n", "Type", "Notify Handler");
-		acpi_os_printf ("%20s : %p\n", "Node", obj_desc->notify_handler.node);
-		acpi_os_printf ("%20s : %p\n", "Handler", obj_desc->notify_handler.handler);
-		acpi_os_printf ("%20s : %p\n", "Context", obj_desc->notify_handler.context);
+		acpi_ex_out_pointer ("Node",         obj_desc->notify_handler.node);
+		acpi_ex_out_pointer ("Context",      obj_desc->notify_handler.context);
 		break;
 
 
@@ -866,15 +904,17 @@
 	case INTERNAL_TYPE_WHILE:
 	case INTERNAL_TYPE_SCOPE:
 	case INTERNAL_TYPE_DEF_ANY:
+	case INTERNAL_TYPE_EXTRA:
+	case INTERNAL_TYPE_DATA:
 
-		acpi_os_printf ("*** Structure display not implemented for type %X! ***\n",
+		acpi_os_printf ("Ex_dump_object_descriptor: Display not implemented for object type %X\n",
 			obj_desc->common.type);
 		break;
 
 
 	default:
 
-		acpi_os_printf ("*** Cannot display unknown type %X! ***\n", obj_desc->common.type);
+		acpi_os_printf ("Ex_dump_object_descriptor: Unknown object type %X\n", obj_desc->common.type);
 		break;
 	}
 
diff -Nru a/drivers/acpi/executer/exfield.c b/drivers/acpi/executer/exfield.c
--- a/drivers/acpi/executer/exfield.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exfield.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: exfield - ACPI AML (p-code) execution - field manipulation
- *              $Revision: 95 $
+ *              $Revision: 105 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,21 +34,20 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exfield")
+	 ACPI_MODULE_NAME    ("exfield")
 
 
 /*******************************************************************************
  *
  * FUNCTION:    Acpi_ex_read_data_from_field
  *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Number of bytes to transfer
+ * PARAMETERS:  Obj_desc            - The named field
+ *              Ret_buffer_desc     - Where the return data object is stored
  *
- * RETURN:      Status3
+ * RETURN:      Status
  *
- * DESCRIPTION: Read or write a named field
+ * DESCRIPTION: Read from a named field.  Returns either an Integer or a
+ *              Buffer, depending on the size of the field.
  *
  ******************************************************************************/
 
@@ -61,9 +60,10 @@
 	acpi_operand_object     *buffer_desc;
 	u32                     length;
 	void                    *buffer;
+	u8                      locked;
 
 
-	FUNCTION_TRACE_PTR ("Ex_read_data_from_field", obj_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_read_data_from_field", obj_desc);
 
 
 	/* Parameter validation */
@@ -72,6 +72,19 @@
 		return_ACPI_STATUS (AE_AML_NO_OPERAND);
 	}
 
+	if (obj_desc->common.type == ACPI_TYPE_BUFFER_FIELD) {
+		/*
+		 * If the Buffer_field arguments have not been previously evaluated,
+		 * evaluate them now and save the results.
+		 */
+		if (!(obj_desc->common.flags & AOPOBJ_DATA_VALID)) {
+			status = acpi_ds_get_buffer_field_arguments (obj_desc);
+			if (ACPI_FAILURE (status)) {
+				return_ACPI_STATUS (status);
+			}
+		}
+	}
+
 	/*
 	 * Allocate a buffer for the contents of the field.
 	 *
@@ -82,7 +95,7 @@
 	 *
 	 * Note: Field.length is in bits.
 	 */
-	length = ROUND_BITS_UP_TO_BYTES (obj_desc->field.bit_length);
+	length = ACPI_ROUND_BITS_UP_TO_BYTES (obj_desc->field.bit_length);
 
 	if (length > sizeof (acpi_integer)) {
 		/* Field is too large for an Integer, create a Buffer instead */
@@ -103,7 +116,6 @@
 		buffer_desc->buffer.length = length;
 		buffer = buffer_desc->buffer.pointer;
 	}
-
 	else {
 		/* Field will fit within an Integer (normal case) */
 
@@ -116,35 +128,29 @@
 		buffer = &buffer_desc->integer.value;
 	}
 
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+		"Obj=%p Type=%X Buf=%p Len=%X\n",
+		obj_desc, obj_desc->common.type, buffer, length));
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+		"Field_write: Bit_len=%X Bit_off=%X Byte_off=%X\n",
+		obj_desc->common_field.bit_length,
+		obj_desc->common_field.start_field_bit_offset,
+		obj_desc->common_field.base_byte_offset));
 
-	/* Read from the appropriate field */
-
-	switch (obj_desc->common.type) {
-	case ACPI_TYPE_BUFFER_FIELD:
-		status = acpi_ex_access_buffer_field (ACPI_READ, obj_desc, buffer, length);
-		break;
-
-	case INTERNAL_TYPE_REGION_FIELD:
-		status = acpi_ex_access_region_field (ACPI_READ, obj_desc, buffer, length);
-		break;
-
-	case INTERNAL_TYPE_BANK_FIELD:
-		status = acpi_ex_access_bank_field (ACPI_READ, obj_desc, buffer, length);
-		break;
+	locked = acpi_ex_acquire_global_lock (obj_desc->common_field.field_flags);
 
-	case INTERNAL_TYPE_INDEX_FIELD:
-		status = acpi_ex_access_index_field (ACPI_READ, obj_desc, buffer, length);
-		break;
+	/* Read from the field */
 
-	default:
-		status = AE_AML_INTERNAL;
-	}
+	status = acpi_ex_extract_from_field (obj_desc, buffer, length);
 
+	/*
+	 * Release global lock if we acquired it earlier
+	 */
+	acpi_ex_release_global_lock (locked);
 
 	if (ACPI_FAILURE (status)) {
 		acpi_ut_remove_reference (buffer_desc);
 	}
-
 	else if (ret_buffer_desc) {
 		*ret_buffer_desc = buffer_desc;
 	}
@@ -157,18 +163,15 @@
  *
  * FUNCTION:    Acpi_ex_write_data_to_field
  *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Number of bytes to transfer
+ * PARAMETERS:  Source_desc         - Contains data to write
+ *              Obj_desc            - The named field
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Read or write a named field
+ * DESCRIPTION: Write to a named field
  *
  ******************************************************************************/
 
-
 acpi_status
 acpi_ex_write_data_to_field (
 	acpi_operand_object     *source_desc,
@@ -176,10 +179,13 @@
 {
 	acpi_status             status;
 	u32                     length;
+	u32                     required_length;
 	void                    *buffer;
+	void                    *new_buffer;
+	u8                      locked;
 
 
-	FUNCTION_TRACE_PTR ("Ex_write_data_to_field", obj_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_write_data_to_field", obj_desc);
 
 
 	/* Parameter validation */
@@ -188,6 +194,18 @@
 		return_ACPI_STATUS (AE_AML_NO_OPERAND);
 	}
 
+	if (obj_desc->common.type == ACPI_TYPE_BUFFER_FIELD) {
+		/*
+		 * If the Buffer_field arguments have not been previously evaluated,
+		 * evaluate them now and save the results.
+		 */
+		if (!(obj_desc->common.flags & AOPOBJ_DATA_VALID)) {
+			status = acpi_ds_get_buffer_field_arguments (obj_desc);
+			if (ACPI_FAILURE (status)) {
+				return_ACPI_STATUS (status);
+			}
+		}
+	}
 
 	/*
 	 * Get a pointer to the data to be written
@@ -212,315 +230,61 @@
 		return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 	}
 
-
 	/*
-	 * Decode the type of field to be written
+	 * We must have a buffer that is at least as long as the field
+	 * we are writing to.  This is because individual fields are
+	 * indivisible and partial writes are not supported -- as per
+	 * the ACPI specification.
 	 */
-	switch (obj_desc->common.type) {
-	case ACPI_TYPE_BUFFER_FIELD:
-		status = acpi_ex_access_buffer_field (ACPI_WRITE, obj_desc, buffer, length);
-		break;
-
-	case INTERNAL_TYPE_REGION_FIELD:
-		status = acpi_ex_access_region_field (ACPI_WRITE, obj_desc, buffer, length);
-		break;
+	new_buffer = NULL;
+	required_length = ACPI_ROUND_BITS_UP_TO_BYTES (obj_desc->common_field.bit_length);
 
-	case INTERNAL_TYPE_BANK_FIELD:
-		status = acpi_ex_access_bank_field (ACPI_WRITE, obj_desc, buffer, length);
-		break;
-
-	case INTERNAL_TYPE_INDEX_FIELD:
-		status = acpi_ex_access_index_field (ACPI_WRITE, obj_desc, buffer, length);
-		break;
+	if (length < required_length) {
+		/* We need to create a new buffer */
 
-	default:
-		return_ACPI_STATUS (AE_AML_INTERNAL);
-	}
-
-
-	return_ACPI_STATUS (status);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_access_buffer_field
- *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Number of bytes to transfer
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Read or write a named field
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_access_buffer_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length)
-{
-	acpi_status             status;
-
-
-	FUNCTION_TRACE_PTR ("Ex_access_buffer_field", obj_desc);
-
-
-	/*
-	 * If the Buffer_field arguments have not been previously evaluated,
-	 * evaluate them now and save the results.
-	 */
-	if (!(obj_desc->common.flags & AOPOBJ_DATA_VALID)) {
-		status = acpi_ds_get_buffer_field_arguments (obj_desc);
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
+		new_buffer = ACPI_MEM_CALLOCATE (required_length);
+		if (!new_buffer) {
+			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
-	}
-
-
-	status = acpi_ex_common_access_field (mode, obj_desc, buffer, buffer_length);
-
-	return_ACPI_STATUS (status);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_access_region_field
- *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Number of bytes to transfer
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Read or write a named field
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_access_region_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length)
-{
-	acpi_status             status;
-	u8                      locked;
-
-
-	FUNCTION_TRACE_PTR ("Ex_access_region_field", obj_desc);
-
-
-	/*
-	 * Get the global lock if needed
-	 */
-	locked = acpi_ex_acquire_global_lock (obj_desc->field.lock_rule);
-
-	status = acpi_ex_common_access_field (mode, obj_desc, buffer, buffer_length);
-
-
-	/*
-	 * Release global lock if we acquired it earlier
-	 */
-	acpi_ex_release_global_lock (locked);
-
-	return_ACPI_STATUS (status);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_access_bank_field
- *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Number of bytes to transfer
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Read or write a Bank Field
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_access_bank_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length)
-{
-	acpi_status             status;
-	u8                      locked;
-
-
-	FUNCTION_TRACE_PTR ("Ex_access_bank_field", obj_desc);
-
 
-	/*
-	 * Get the global lock if needed
-	 */
-	locked = acpi_ex_acquire_global_lock (obj_desc->bank_field.lock_rule);
+		/*
+		 * Copy the original data to the new buffer, starting
+		 * at Byte zero.  All unused (upper) bytes of the
+		 * buffer will be 0.
+		 */
+		ACPI_MEMCPY ((char *) new_buffer, (char *) buffer, length);
+		buffer = new_buffer;
+		length = required_length;
+	}
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+		"Obj=%p Type=%X Buf=%p Len=%X\n",
+		obj_desc, obj_desc->common.type, buffer, length));
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+		"Field_read: Bit_len=%X Bit_off=%X Byte_off=%X\n",
+		obj_desc->common_field.bit_length,
+		obj_desc->common_field.start_field_bit_offset,
+		obj_desc->common_field.base_byte_offset));
 
+	locked = acpi_ex_acquire_global_lock (obj_desc->common_field.field_flags);
 
 	/*
-	 * Write the Bank_value to the Bank_register to select the bank.
-	 * The Bank_value for this Bank_field is specified in the
-	 * Bank_field ASL declaration. The Bank_register is always a Field in
-	 * an operation region.
+	 * Write to the field
 	 */
-	status = acpi_ex_common_access_field (ACPI_WRITE,
-			 obj_desc->bank_field.bank_register_obj,
-			 &obj_desc->bank_field.value,
-			 sizeof (obj_desc->bank_field.value));
-	if (ACPI_FAILURE (status)) {
-		goto cleanup;
-	}
+	status = acpi_ex_insert_into_field (obj_desc, buffer, length);
 
 	/*
-	 * The bank was successfully selected, now read or write the actual
-	 * data.
-	 */
-	status = acpi_ex_common_access_field (mode, obj_desc, buffer, buffer_length);
-
-
-cleanup:
-	/*
 	 * Release global lock if we acquired it earlier
 	 */
 	acpi_ex_release_global_lock (locked);
 
-	return_ACPI_STATUS (status);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_access_index_field
- *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Number of bytes to transfer
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Read or write a Index Field
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_access_index_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length)
-{
-	acpi_status             status;
-	u8                      locked;
-
-
-	FUNCTION_TRACE_PTR ("Ex_access_index_field", obj_desc);
-
-
-	/*
-	 * Get the global lock if needed
-	 */
-	locked = acpi_ex_acquire_global_lock (obj_desc->index_field.lock_rule);
+	/* Free temporary buffer if we used one */
 
-
-	/*
-	 * Set Index value to select proper Data register
-	 */
-	status = acpi_ex_common_access_field (ACPI_WRITE,
-			 obj_desc->index_field.index_obj,
-			 &obj_desc->index_field.value,
-			 sizeof (obj_desc->index_field.value));
-	if (ACPI_FAILURE (status)) {
-		goto cleanup;
+	if (new_buffer) {
+		ACPI_MEM_FREE (new_buffer);
 	}
 
-	/* Now read/write the data register */
-
-	status = acpi_ex_common_access_field (mode, obj_desc->index_field.data_obj,
-			  buffer, buffer_length);
-
-cleanup:
-	/*
-	 * Release global lock if we acquired it earlier
-	 */
-	acpi_ex_release_global_lock (locked);
-
 	return_ACPI_STATUS (status);
 }
 
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_common_access_field
- *
- * PARAMETERS:  Mode                - ACPI_READ or ACPI_WRITE
- *              *Field_node         - Parent node for field to be accessed
- *              *Buffer             - Value(s) to be read or written
- *              Buffer_length       - Size of buffer, in bytes.  Must be large
- *                                    enough for all bits of the field.
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Read or write a named field
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_common_access_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length)
-{
-	acpi_status             status;
-
-
-	FUNCTION_TRACE_PTR ("Ex_common_access_field", obj_desc);
-
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Obj=%p Type=%X Buf=%p Len=%X\n",
-		obj_desc, obj_desc->common.type, buffer, buffer_length));
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Mode=%d Bit_len=%X Bit_off=%X Byte_off=%X\n",
-		mode, obj_desc->common_field.bit_length,
-		obj_desc->common_field.start_field_bit_offset,
-		obj_desc->common_field.base_byte_offset));
-
-
-	/* Perform the actual read or write of the field */
-
-	switch (mode) {
-	case ACPI_READ:
-
-		status = acpi_ex_extract_from_field (obj_desc, buffer, buffer_length);
-		break;
-
-
-	case ACPI_WRITE:
-
-		status = acpi_ex_insert_into_field (obj_desc, buffer, buffer_length);
-		break;
-
-
-	default:
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown I/O Mode: %X\n", mode));
-		status = AE_BAD_PARAMETER;
-		break;
-	}
-
-
-	return_ACPI_STATUS (status);
-}
 
diff -Nru a/drivers/acpi/executer/exfldio.c b/drivers/acpi/executer/exfldio.c
--- a/drivers/acpi/executer/exfldio.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exfldio.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: exfldio - Aml Field I/O
- *              $Revision: 66 $
+ *              $Revision: 82 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,25 +34,26 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exfldio")
+	 ACPI_MODULE_NAME    ("exfldio")
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_setup_field
+ * FUNCTION:    Acpi_ex_setup_region
  *
- * PARAMETERS:  *Obj_desc           - Field to be read or written
- *              Field_datum_byte_offset  - Current offset into the field
+ * PARAMETERS:  *Obj_desc               - Field to be read or written
+ *              Field_datum_byte_offset - Byte offset of this datum within the
+ *                                        parent field
  *
  * RETURN:      Status
  *
  * DESCRIPTION: Common processing for Acpi_ex_extract_from_field and
- *              Acpi_ex_insert_into_field
+ *              Acpi_ex_insert_into_field. Initialize the
  *
  ******************************************************************************/
 
 acpi_status
-acpi_ex_setup_field (
+acpi_ex_setup_region (
 	acpi_operand_object     *obj_desc,
 	u32                     field_datum_byte_offset)
 {
@@ -60,7 +61,7 @@
 	acpi_operand_object     *rgn_desc;
 
 
-	FUNCTION_TRACE_U32 ("Ex_setup_field", field_datum_byte_offset);
+	ACPI_FUNCTION_TRACE_U32 ("Ex_setup_region", field_datum_byte_offset);
 
 
 	rgn_desc = obj_desc->common_field.region_obj;
@@ -76,7 +77,6 @@
 	 * evaluate them now and save the results.
 	 */
 	if (!(rgn_desc->region.flags & AOPOBJ_DATA_VALID)) {
-
 		status = acpi_ds_get_region_arguments (rgn_desc);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
@@ -88,9 +88,9 @@
 	 * length of one field datum (access width) must fit within the region.
 	 * (Region length is specified in bytes)
 	 */
-	if (rgn_desc->region.length < (obj_desc->common_field.base_byte_offset +
-			   field_datum_byte_offset +
-			   obj_desc->common_field.access_byte_width)) {
+	if (rgn_desc->region.length < (obj_desc->common_field.base_byte_offset
+			   + field_datum_byte_offset
+			   + obj_desc->common_field.access_byte_width)) {
 		if (rgn_desc->region.length < obj_desc->common_field.access_byte_width) {
 			/*
 			 * This is the case where the Access_type (Acc_word, etc.) is wider
@@ -98,8 +98,9 @@
 			 * byte, and a field with Dword access specified.
 			 */
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Field access width (%d bytes) too large for region size (%X)\n",
-				obj_desc->common_field.access_byte_width, rgn_desc->region.length));
+				"Field [%4.4s] access width (%d bytes) too large for region [%4.4s] (length %X)\n",
+				(char *) &obj_desc->common_field.node->name, obj_desc->common_field.access_byte_width,
+				(char *) &rgn_desc->region.node->name, rgn_desc->region.length));
 		}
 
 		/*
@@ -107,10 +108,10 @@
 		 * exceeds region length, indicate an error
 		 */
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-			"Field base+offset+width %X+%X+%X exceeds region size (%X bytes) field=%p region=%p\n",
-			obj_desc->common_field.base_byte_offset, field_datum_byte_offset,
-			obj_desc->common_field.access_byte_width,
-			rgn_desc->region.length, obj_desc, rgn_desc));
+			"Field [%4.4s] Base+Offset+Width %X+%X+%X is beyond end of region [%4.4s] (length %X)\n",
+			(char *) &obj_desc->common_field.node->name, obj_desc->common_field.base_byte_offset,
+			field_datum_byte_offset, obj_desc->common_field.access_byte_width,
+			(char *) &rgn_desc->region.node->name, rgn_desc->region.length));
 
 		return_ACPI_STATUS (AE_AML_REGION_LIMIT);
 	}
@@ -121,116 +122,410 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_read_field_datum
+ * FUNCTION:    Acpi_ex_access_region
  *
- * PARAMETERS:  *Obj_desc           - Field to be read
- *              *Value              - Where to store value (must be 32 bits)
+ * PARAMETERS:  *Obj_desc               - Field to be read
+ *              Field_datum_byte_offset - Byte offset of this datum within the
+ *                                        parent field
+ *              *Value                  - Where to store value (must be 32 bits)
+ *              Read_write              - Read or Write flag
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Retrieve the value of the given field
+ * DESCRIPTION: Read or Write a single field datum to an Operation Region.
  *
  ******************************************************************************/
 
 acpi_status
-acpi_ex_read_field_datum (
+acpi_ex_access_region (
 	acpi_operand_object     *obj_desc,
 	u32                     field_datum_byte_offset,
-	u32                     *value)
+	acpi_integer            *value,
+	u32                     read_write)
 {
 	acpi_status             status;
 	acpi_operand_object     *rgn_desc;
 	ACPI_PHYSICAL_ADDRESS   address;
-	u32                     local_value;
 
 
-	FUNCTION_TRACE_U32 ("Ex_read_field_datum", field_datum_byte_offset);
+	ACPI_FUNCTION_TRACE ("Acpi_ex_access_region");
+
+
+	/*
+	 * The physical address of this field datum is:
+	 *
+	 * 1) The base of the region, plus
+	 * 2) The base offset of the field, plus
+	 * 3) The current offset into the field
+	 */
+	rgn_desc = obj_desc->common_field.region_obj;
+	address = rgn_desc->region.address
+			 + obj_desc->common_field.base_byte_offset
+			 + field_datum_byte_offset;
+
+	if (read_write == ACPI_READ) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "[READ]"));
+	}
+	else {
+		ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "[WRITE]"));
+	}
+
+	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_BFIELD,
+		" Region[%s-%X] Access %X Base:Off %X:%X at %8.8X%8.8X\n",
+		acpi_ut_get_region_name (rgn_desc->region.space_id),
+		rgn_desc->region.space_id,
+		obj_desc->common_field.access_byte_width,
+		obj_desc->common_field.base_byte_offset,
+		field_datum_byte_offset,
+		ACPI_HIDWORD (address), ACPI_LODWORD (address)));
+
+	/* Invoke the appropriate Address_space/Op_region handler */
 
+	status = acpi_ev_address_space_dispatch (rgn_desc, read_write,
+			  address, ACPI_MUL_8 (obj_desc->common_field.access_byte_width), value);
 
-	if (!value) {
-		local_value = 0;
-		value = &local_value;   /*  support reads without saving value  */
+	if (ACPI_FAILURE (status)) {
+		if (status == AE_NOT_IMPLEMENTED) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Region %s(%X) not implemented\n",
+				acpi_ut_get_region_name (rgn_desc->region.space_id),
+				rgn_desc->region.space_id));
+		}
+
+		else if (status == AE_NOT_EXIST) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Region %s(%X) has no handler\n",
+				acpi_ut_get_region_name (rgn_desc->region.space_id),
+				rgn_desc->region.space_id));
+		}
+	}
+
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_register_overflow
+ *
+ * PARAMETERS:  *Obj_desc               - Register(Field) to be written
+ *              Value                   - Value to be stored
+ *
+ * RETURN:      TRUE if value overflows the field, FALSE otherwise
+ *
+ * DESCRIPTION: Check if a value is out of range of the field being written.
+ *              Used to check if the values written to Index and Bank registers
+ *              are out of range.  Normally, the value is simply truncated
+ *              to fit the field, but this case is most likely a serious
+ *              coding error in the ASL.
+ *
+ ******************************************************************************/
+
+u8
+acpi_ex_register_overflow (
+	acpi_operand_object     *obj_desc,
+	acpi_integer            value)
+{
+
+	if (obj_desc->common_field.bit_length >= ACPI_INTEGER_BIT_SIZE) {
+		/*
+		 * The field is large enough to hold the maximum integer, so we can
+		 * never overflow it.
+		 */
+		return (FALSE);
+	}
+
+	if (value >= (acpi_integer) (1 << obj_desc->common_field.bit_length)) {
+		/*
+		 * The Value is larger than the maximum value that can fit into
+		 * the register.
+		 */
+		return (TRUE);
 	}
 
-	/* Clear the entire return buffer first, [Very Important!] */
+	/* The Value will fit into the field with no truncation */
 
-	*value = 0;
+	return (FALSE);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_field_datum_io
+ *
+ * PARAMETERS:  *Obj_desc               - Field to be read
+ *              Field_datum_byte_offset - Byte offset of this datum within the
+ *                                        parent field
+ *              *Value                  - Where to store value (must be 64 bits)
+ *              Read_write              - Read or Write flag
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Read or Write a single datum of a field.  The Field_type is
+ *              demultiplexed here to handle the different types of fields
+ *              (Buffer_field, Region_field, Index_field, Bank_field)
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ex_field_datum_io (
+	acpi_operand_object     *obj_desc,
+	u32                     field_datum_byte_offset,
+	acpi_integer            *value,
+	u32                     read_write)
+{
+	acpi_status             status;
+	acpi_integer            local_value;
+
+
+	ACPI_FUNCTION_TRACE_U32 ("Ex_field_datum_io", field_datum_byte_offset);
+
+
+	if (read_write == ACPI_READ) {
+		if (!value) {
+			local_value = 0;
+			value = &local_value; /* To support reads without saving return value */
+		}
+
+		/* Clear the entire return buffer first, [Very Important!] */
+
+		*value = 0;
+	}
 
 	/*
-	 * Buffer_fields - Read from a Buffer
-	 * Other Fields - Read from a Operation Region.
+	 * The four types of fields are:
+	 *
+	 * Buffer_fields - Read/write from/to a Buffer
+	 * Region_fields - Read/write from/to a Operation Region.
+	 * Bank_fields  - Write to a Bank Register, then read/write from/to an Op_region
+	 * Index_fields - Write to an Index Register, then read/write from/to a Data Register
 	 */
 	switch (obj_desc->common.type) {
 	case ACPI_TYPE_BUFFER_FIELD:
-
 		/*
-		 * For Buffer_fields, we only need to copy the data from the
-		 * source buffer.  Length is the field width in bytes.
+		 * If the Buffer_field arguments have not been previously evaluated,
+		 * evaluate them now and save the results.
 		 */
-		MEMCPY (value, (obj_desc->buffer_field.buffer_obj)->buffer.pointer
-				  + obj_desc->buffer_field.base_byte_offset + field_datum_byte_offset,
-				  obj_desc->common_field.access_byte_width);
+		if (!(obj_desc->common.flags & AOPOBJ_DATA_VALID)) {
+			status = acpi_ds_get_buffer_field_arguments (obj_desc);
+			if (ACPI_FAILURE (status)) {
+				return_ACPI_STATUS (status);
+			}
+		}
+
+		if (read_write == ACPI_READ) {
+			/*
+			 * Copy the data from the source buffer.
+			 * Length is the field width in bytes.
+			 */
+			ACPI_MEMCPY (value, (obj_desc->buffer_field.buffer_obj)->buffer.pointer
+					  + obj_desc->buffer_field.base_byte_offset
+					  + field_datum_byte_offset,
+					  obj_desc->common_field.access_byte_width);
+		}
+		else {
+			/*
+			 * Copy the data to the target buffer.
+			 * Length is the field width in bytes.
+			 */
+			ACPI_MEMCPY ((obj_desc->buffer_field.buffer_obj)->buffer.pointer
+					+ obj_desc->buffer_field.base_byte_offset
+					+ field_datum_byte_offset,
+					value, obj_desc->common_field.access_byte_width);
+		}
+
 		status = AE_OK;
 		break;
 
 
-	case INTERNAL_TYPE_REGION_FIELD:
 	case INTERNAL_TYPE_BANK_FIELD:
 
+		/* Ensure that the Bank_value is not beyond the capacity of the register */
+
+		if (acpi_ex_register_overflow (obj_desc->bank_field.bank_obj,
+				  obj_desc->bank_field.value)) {
+			return_ACPI_STATUS (AE_AML_REGISTER_LIMIT);
+		}
+
 		/*
-		 * For other fields, we need to go through an Operation Region
-		 * (Only types that will get here are Region_fields and Bank_fields)
+		 * For Bank_fields, we must write the Bank_value to the Bank_register
+		 * (itself a Region_field) before we can access the data.
 		 */
-		status = acpi_ex_setup_field (obj_desc, field_datum_byte_offset);
+		status = acpi_ex_insert_into_field (obj_desc->bank_field.bank_obj,
+				 &obj_desc->bank_field.value,
+				 sizeof (obj_desc->bank_field.value));
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
 
 		/*
-		 * The physical address of this field datum is:
-		 *
-		 * 1) The base of the region, plus
-		 * 2) The base offset of the field, plus
-		 * 3) The current offset into the field
-		 */
-		rgn_desc = obj_desc->common_field.region_obj;
-		address = rgn_desc->region.address + obj_desc->common_field.base_byte_offset +
-				 field_datum_byte_offset;
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "Region %s(%X) width %X base:off %X:%X at %8.8X%8.8X\n",
-			acpi_ut_get_region_name (rgn_desc->region.space_id),
-			rgn_desc->region.space_id, obj_desc->common_field.access_bit_width,
-			obj_desc->common_field.base_byte_offset, field_datum_byte_offset,
-			HIDWORD(address), LODWORD(address)));
+		 * Now that the Bank has been selected, fall through to the
+		 * Region_field case and write the datum to the Operation Region
+		 */
 
-		/* Invoke the appropriate Address_space/Op_region handler */
+		/* No break; ! */
 
-		status = acpi_ev_address_space_dispatch (rgn_desc, ACPI_READ_ADR_SPACE,
-				  address, obj_desc->common_field.access_bit_width, value);
-		if (status == AE_NOT_IMPLEMENTED) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Region %s(%X) not implemented\n",
-				acpi_ut_get_region_name (rgn_desc->region.space_id),
-				rgn_desc->region.space_id));
+
+	case INTERNAL_TYPE_REGION_FIELD:
+		/*
+		 * For simple Region_fields, we just directly access the owning
+		 * Operation Region.
+		 */
+		status = acpi_ex_setup_region (obj_desc, field_datum_byte_offset);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
 		}
 
-		else if (status == AE_NOT_EXIST) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Region %s(%X) has no handler\n",
-				acpi_ut_get_region_name (rgn_desc->region.space_id),
-				rgn_desc->region.space_id));
+		status = acpi_ex_access_region (obj_desc, field_datum_byte_offset, value,
+				  read_write);
+		break;
+
+
+	case INTERNAL_TYPE_INDEX_FIELD:
+
+
+		/* Ensure that the Index_value is not beyond the capacity of the register */
+
+		if (acpi_ex_register_overflow (obj_desc->index_field.index_obj,
+				  obj_desc->index_field.value)) {
+			return_ACPI_STATUS (AE_AML_REGISTER_LIMIT);
+		}
+
+		/* Write the index value to the Index_register (itself a Region_field) */
+
+		status = acpi_ex_insert_into_field (obj_desc->index_field.index_obj,
+				 &obj_desc->index_field.value,
+				 sizeof (obj_desc->index_field.value));
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
+
+		if (read_write == ACPI_READ) {
+			/* Read the datum from the Data_register */
+
+			status = acpi_ex_extract_from_field (obj_desc->index_field.data_obj,
+					  value, obj_desc->common_field.access_byte_width);
+		}
+		else {
+			/* Write the datum to the Data register */
+
+			status = acpi_ex_insert_into_field (obj_desc->index_field.data_obj,
+					  value, obj_desc->common_field.access_byte_width);
 		}
 		break;
 
 
 	default:
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "%p, wrong source type - %s\n",
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "%p, Wrong object type - %s\n",
 			obj_desc, acpi_ut_get_type_name (obj_desc->common.type)));
 		status = AE_AML_INTERNAL;
 		break;
 	}
 
+	if (ACPI_SUCCESS (status)) {
+		if (read_write == ACPI_READ) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "Value Read=%8.8X%8.8X\n",
+					   ACPI_HIDWORD (*value), ACPI_LODWORD (*value)));
+		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "Value Written=%8.8X%8.8X\n",
+					   ACPI_HIDWORD (*value), ACPI_LODWORD (*value)));
+		}
+	}
+
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_write_with_update_rule
+ *
+ * PARAMETERS:  *Obj_desc           - Field to be set
+ *              Value               - Value to store
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Apply the field update rule to a field write
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ex_write_with_update_rule (
+	acpi_operand_object     *obj_desc,
+	acpi_integer            mask,
+	acpi_integer            field_value,
+	u32                     field_datum_byte_offset)
+{
+	acpi_status             status = AE_OK;
+	acpi_integer            merged_value;
+	acpi_integer            current_value;
+
+
+	ACPI_FUNCTION_TRACE_U32 ("Ex_write_with_update_rule", mask);
+
+
+	/* Start with the new bits  */
+
+	merged_value = field_value;
+
+	/* If the mask is all ones, we don't need to worry about the update rule */
+
+	if (mask != ACPI_UINT32_MAX) {
+		/* Decode the update rule */
+
+		switch (obj_desc->common_field.field_flags & AML_FIELD_UPDATE_RULE_MASK) {
+		case AML_FIELD_UPDATE_PRESERVE:
+			/*
+			 * Check if update rule needs to be applied (not if mask is all
+			 * ones)  The left shift drops the bits we want to ignore.
+			 */
+			if ((~mask << (ACPI_MUL_8 (sizeof (mask)) -
+					 ACPI_MUL_8 (obj_desc->common_field.access_byte_width))) != 0) {
+				/*
+				 * Read the current contents of the byte/word/dword containing
+				 * the field, and merge with the new field value.
+				 */
+				status = acpi_ex_field_datum_io (obj_desc, field_datum_byte_offset,
+						  &current_value, ACPI_READ);
+				merged_value |= (current_value & ~mask);
+			}
+			break;
+
+		case AML_FIELD_UPDATE_WRITE_AS_ONES:
+
+			/* Set positions outside the field to all ones */
+
+			merged_value |= ~mask;
+			break;
+
+		case AML_FIELD_UPDATE_WRITE_AS_ZEROS:
+
+			/* Set positions outside the field to all zeros */
+
+			merged_value &= mask;
+			break;
+
+		default:
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Write_with_update_rule: Unknown Update_rule setting: %x\n",
+				(obj_desc->common_field.field_flags & AML_FIELD_UPDATE_RULE_MASK)));
+			return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
+		}
+	}
+
+	/* Write the merged value */
+
+	status = acpi_ex_field_datum_io (obj_desc, field_datum_byte_offset,
+			  &merged_value, ACPI_WRITE);
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "Returned value=%08X \n", *value));
+	ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD,
+		"Mask %8.8X%8.8X Datum_offset %X Value %8.8X%8.8X, Merged_value %8.8X%8.8X\n",
+		ACPI_HIDWORD (mask), ACPI_LODWORD (mask),
+		field_datum_byte_offset,
+		ACPI_HIDWORD (field_value), ACPI_LODWORD (field_value),
+		ACPI_HIDWORD (merged_value),ACPI_LODWORD (merged_value)));
 
 	return_ACPI_STATUS (status);
 }
@@ -240,41 +535,49 @@
  *
  * FUNCTION:    Acpi_ex_get_buffer_datum
  *
- * PARAMETERS:  Merged_datum        - Value to store
- *              Buffer              - Receiving buffer
- *              Byte_granularity    - 1/2/4 Granularity of the field
+ * PARAMETERS:  Datum               - Where the Datum is returned
+ *              Buffer              - Raw field buffer
+ *              Byte_granularity    - 1/2/4/8 Granularity of the field
  *                                    (aka Datum Size)
  *              Offset              - Datum offset into the buffer
  *
  * RETURN:      none
  *
- * DESCRIPTION: Store the merged datum to the buffer according to the
+ * DESCRIPTION: Get a datum from the buffer according to the buffer field
  *              byte granularity
  *
  ******************************************************************************/
 
-static void
+void
 acpi_ex_get_buffer_datum(
-	u32                     *datum,
+	acpi_integer            *datum,
 	void                    *buffer,
 	u32                     byte_granularity,
 	u32                     offset)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	switch (byte_granularity) {
 	case ACPI_FIELD_BYTE_GRANULARITY:
+
 		*datum = ((u8 *) buffer) [offset];
 		break;
 
 	case ACPI_FIELD_WORD_GRANULARITY:
-		MOVE_UNALIGNED16_TO_32 (datum, &(((u16 *) buffer) [offset]));
+
+		ACPI_MOVE_UNALIGNED16_TO_32 (datum, &(((u16 *) buffer) [offset]));
 		break;
 
 	case ACPI_FIELD_DWORD_GRANULARITY:
-		MOVE_UNALIGNED32_TO_32 (datum, &(((u32 *) buffer) [offset]));
+
+		ACPI_MOVE_UNALIGNED32_TO_32 (datum, &(((u32 *) buffer) [offset]));
+		break;
+
+	case ACPI_FIELD_QWORD_GRANULARITY:
+
+		ACPI_MOVE_UNALIGNED64_TO_64 (datum, &(((u64 *) buffer) [offset]));
 		break;
 	}
 }
@@ -286,7 +589,7 @@
  *
  * PARAMETERS:  Merged_datum        - Value to store
  *              Buffer              - Receiving buffer
- *              Byte_granularity    - 1/2/4 Granularity of the field
+ *              Byte_granularity    - 1/2/4/8 Granularity of the field
  *                                    (aka Datum Size)
  *              Offset              - Datum offset into the buffer
  *
@@ -297,28 +600,36 @@
  *
  ******************************************************************************/
 
-static void
+void
 acpi_ex_set_buffer_datum (
-	u32                     merged_datum,
+	acpi_integer            merged_datum,
 	void                    *buffer,
 	u32                     byte_granularity,
 	u32                     offset)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	switch (byte_granularity) {
 	case ACPI_FIELD_BYTE_GRANULARITY:
+
 		((u8 *) buffer) [offset] = (u8) merged_datum;
 		break;
 
 	case ACPI_FIELD_WORD_GRANULARITY:
-		MOVE_UNALIGNED16_TO_16 (&(((u16 *) buffer)[offset]), &merged_datum);
+
+		ACPI_MOVE_UNALIGNED16_TO_16 (&(((u16 *) buffer)[offset]), &merged_datum);
 		break;
 
 	case ACPI_FIELD_DWORD_GRANULARITY:
-		MOVE_UNALIGNED32_TO_32 (&(((u32 *) buffer)[offset]), &merged_datum);
+
+		ACPI_MOVE_UNALIGNED32_TO_32 (&(((u32 *) buffer)[offset]), &merged_datum);
+		break;
+
+	case ACPI_FIELD_QWORD_GRANULARITY:
+
+		ACPI_MOVE_UNALIGNED64_TO_64 (&(((u64 *) buffer)[offset]), &merged_datum);
 		break;
 	}
 }
@@ -346,22 +657,23 @@
 	acpi_status             status;
 	u32                     field_datum_byte_offset;
 	u32                     datum_offset;
-	u32                     previous_raw_datum;
-	u32                     this_raw_datum = 0;
-	u32                     merged_datum = 0;
+	acpi_integer            previous_raw_datum;
+	acpi_integer            this_raw_datum = 0;
+	acpi_integer            merged_datum = 0;
 	u32                     byte_field_length;
 	u32                     datum_count;
 
 
-	FUNCTION_TRACE ("Ex_extract_from_field");
+	ACPI_FUNCTION_TRACE ("Ex_extract_from_field");
 
 
 	/*
 	 * The field must fit within the caller's buffer
 	 */
-	byte_field_length = ROUND_BITS_UP_TO_BYTES (obj_desc->common_field.bit_length);
+	byte_field_length = ACPI_ROUND_BITS_UP_TO_BYTES (obj_desc->common_field.bit_length);
 	if (byte_field_length > buffer_length) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Field size %X (bytes) too large for buffer (%X)\n",
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+			"Field size %X (bytes) too large for buffer (%X)\n",
 			byte_field_length, buffer_length));
 
 		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
@@ -369,26 +681,27 @@
 
 	/* Convert field byte count to datum count, round up if necessary */
 
-	datum_count = ROUND_UP_TO (byte_field_length, obj_desc->common_field.access_byte_width);
+	datum_count = ACPI_ROUND_UP_TO (byte_field_length,
+			   obj_desc->common_field.access_byte_width);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-		"Byte_len=%x, Datum_len=%x, Bit_gran=%x, Byte_gran=%x\n",
-		byte_field_length, datum_count, obj_desc->common_field.access_bit_width,
-		obj_desc->common_field.access_byte_width));
+		"Byte_len=%x, Datum_len=%x, Byte_gran=%x\n",
+		byte_field_length, datum_count,obj_desc->common_field.access_byte_width));
 
 	/*
 	 * Clear the caller's buffer (the whole buffer length as given)
 	 * This is very important, especially in the cases where a byte is read,
 	 * but the buffer is really a u32 (4 bytes).
 	 */
-	MEMSET (buffer, 0, buffer_length);
+	ACPI_MEMSET (buffer, 0, buffer_length);
 
 	/* Read the first raw datum to prime the loop */
 
 	field_datum_byte_offset = 0;
 	datum_offset= 0;
 
-	status = acpi_ex_read_field_datum (obj_desc, field_datum_byte_offset, &previous_raw_datum);
+	status = acpi_ex_field_datum_io (obj_desc, field_datum_byte_offset,
+			  &previous_raw_datum, ACPI_READ);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
@@ -397,7 +710,7 @@
 	/* We might actually be done if the request fits in one datum */
 
 	if ((datum_count == 1) &&
-		(obj_desc->common_field.access_flags & AFIELD_SINGLE_DATUM)) {
+		(obj_desc->common_field.flags & AOPOBJ_SINGLE_DATUM)) {
 		/* 1) Shift the valid data bits down to start at bit 0 */
 
 		merged_datum = (previous_raw_datum >> obj_desc->common_field.start_field_bit_offset);
@@ -405,7 +718,7 @@
 		/* 2) Mask off any upper unused bits (bits not part of the field) */
 
 		if (obj_desc->common_field.end_buffer_valid_bits) {
-			merged_datum &= MASK_BITS_ABOVE (obj_desc->common_field.end_buffer_valid_bits);
+			merged_datum &= ACPI_MASK_BITS_ABOVE (obj_desc->common_field.end_buffer_valid_bits);
 		}
 
 		/* Store the datum to the caller buffer */
@@ -427,17 +740,18 @@
 		 * to perform a final read, since this would potentially read
 		 * past the end of the region.
 		 *
-		 * TBD: [Investigate] It may make more sense to just split the aligned
-		 * and non-aligned cases since the aligned case is so very simple,
+		 * We could just split the aligned and non-aligned cases since the
+		 * aligned case is so very simple, but this would require more code.
 		 */
-		if ((obj_desc->common_field.start_field_bit_offset != 0)  ||
+		if ((obj_desc->common_field.start_field_bit_offset != 0) ||
 			((obj_desc->common_field.start_field_bit_offset == 0) &&
 			(datum_offset < (datum_count -1)))) {
 			/*
 			 * Get the next raw datum, it contains some or all bits
 			 * of the current field datum
 			 */
-			status = acpi_ex_read_field_datum (obj_desc, field_datum_byte_offset, &this_raw_datum);
+			status = acpi_ex_field_datum_io (obj_desc, field_datum_byte_offset,
+					  &this_raw_datum, ACPI_READ);
 			if (ACPI_FAILURE (status)) {
 				return_ACPI_STATUS (status);
 			}
@@ -451,7 +765,6 @@
 
 			merged_datum = previous_raw_datum;
 		}
-
 		else {
 			/*
 			 * Put together the appropriate bits of the two raw data to make a
@@ -474,7 +787,7 @@
 				 */
 				if (obj_desc->common_field.end_buffer_valid_bits) {
 					merged_datum &=
-						MASK_BITS_ABOVE (obj_desc->common_field.end_buffer_valid_bits);
+						ACPI_MASK_BITS_ABOVE (obj_desc->common_field.end_buffer_valid_bits);
 				}
 			}
 		}
@@ -483,8 +796,8 @@
 		 * Store the merged field datum in the caller's buffer, according to
 		 * the granularity of the field (size of each datum).
 		 */
-		acpi_ex_set_buffer_datum (merged_datum, buffer, obj_desc->common_field.access_byte_width,
-				datum_offset);
+		acpi_ex_set_buffer_datum (merged_datum, buffer,
+				obj_desc->common_field.access_byte_width, datum_offset);
 
 		/*
 		 * Save the raw datum that was just acquired since it may contain bits
@@ -500,211 +813,6 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_write_field_datum
- *
- * PARAMETERS:  *Obj_desc           - Field to be set
- *              Value               - Value to store
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Store the value into the given field
- *
- ******************************************************************************/
-
-static acpi_status
-acpi_ex_write_field_datum (
-	acpi_operand_object     *obj_desc,
-	u32                     field_datum_byte_offset,
-	u32                     value)
-{
-	acpi_status             status = AE_OK;
-	acpi_operand_object     *rgn_desc = NULL;
-	ACPI_PHYSICAL_ADDRESS   address;
-
-
-	FUNCTION_TRACE_U32 ("Ex_write_field_datum", field_datum_byte_offset);
-
-
-	/*
-	 * Buffer_fields - Read from a Buffer
-	 * Other Fields - Read from a Operation Region.
-	 */
-	switch (obj_desc->common.type) {
-	case ACPI_TYPE_BUFFER_FIELD:
-
-		/*
-		 * For Buffer_fields, we only need to copy the data to the
-		 * target buffer.  Length is the field width in bytes.
-		 */
-		MEMCPY ((obj_desc->buffer_field.buffer_obj)->buffer.pointer
-				+ obj_desc->buffer_field.base_byte_offset + field_datum_byte_offset,
-				&value, obj_desc->common_field.access_byte_width);
-		status = AE_OK;
-		break;
-
-
-	case INTERNAL_TYPE_REGION_FIELD:
-	case INTERNAL_TYPE_BANK_FIELD:
-
-		/*
-		 * For other fields, we need to go through an Operation Region
-		 * (Only types that will get here are Region_fields and Bank_fields)
-		 */
-		status = acpi_ex_setup_field (obj_desc, field_datum_byte_offset);
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
-		}
-
-		/*
-		 * The physical address of this field datum is:
-		 *
-		 * 1) The base of the region, plus
-		 * 2) The base offset of the field, plus
-		 * 3) The current offset into the field
-		 */
-		rgn_desc = obj_desc->common_field.region_obj;
-		address = rgn_desc->region.address +
-				 obj_desc->common_field.base_byte_offset +
-				 field_datum_byte_offset;
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD,
-			"Store %X in Region %s(%X) at %8.8X%8.8X width %X\n",
-			value, acpi_ut_get_region_name (rgn_desc->region.space_id),
-			rgn_desc->region.space_id, HIDWORD(address), LODWORD(address),
-			obj_desc->common_field.access_bit_width));
-
-		/* Invoke the appropriate Address_space/Op_region handler */
-
-		status = acpi_ev_address_space_dispatch (rgn_desc, ACPI_WRITE_ADR_SPACE,
-				  address, obj_desc->common_field.access_bit_width, &value);
-
-		if (status == AE_NOT_IMPLEMENTED) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"**** Region type %s(%X) not implemented\n",
-				acpi_ut_get_region_name (rgn_desc->region.space_id),
-				rgn_desc->region.space_id));
-		}
-
-		else if (status == AE_NOT_EXIST) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"**** Region type %s(%X) does not have a handler\n",
-				acpi_ut_get_region_name (rgn_desc->region.space_id),
-				rgn_desc->region.space_id));
-		}
-
-		break;
-
-
-	default:
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "%p, wrong source type - %s\n",
-			obj_desc, acpi_ut_get_type_name (obj_desc->common.type)));
-		status = AE_AML_INTERNAL;
-		break;
-	}
-
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "Value written=%08X \n", value));
-	return_ACPI_STATUS (status);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_write_field_datum_with_update_rule
- *
- * PARAMETERS:  *Obj_desc           - Field to be set
- *              Value               - Value to store
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Apply the field update rule to a field write
- *
- ******************************************************************************/
-
-static acpi_status
-acpi_ex_write_field_datum_with_update_rule (
-	acpi_operand_object     *obj_desc,
-	u32                     mask,
-	u32                     field_value,
-	u32                     field_datum_byte_offset)
-{
-	acpi_status             status = AE_OK;
-	u32                     merged_value;
-	u32                     current_value;
-
-
-	FUNCTION_TRACE ("Ex_write_field_datum_with_update_rule");
-
-
-	/* Start with the new bits  */
-
-	merged_value = field_value;
-
-	/* If the mask is all ones, we don't need to worry about the update rule */
-
-	if (mask != ACPI_UINT32_MAX) {
-		/* Decode the update rule */
-
-		switch (obj_desc->common_field.update_rule) {
-		case UPDATE_PRESERVE:
-			/*
-			 * Check if update rule needs to be applied (not if mask is all
-			 * ones)  The left shift drops the bits we want to ignore.
-			 */
-			if ((~mask << (sizeof (mask) * 8 -
-					  obj_desc->common_field.access_bit_width)) != 0) {
-				/*
-				 * Read the current contents of the byte/word/dword containing
-				 * the field, and merge with the new field value.
-				 */
-				status = acpi_ex_read_field_datum (obj_desc, field_datum_byte_offset,
-						  &current_value);
-				merged_value |= (current_value & ~mask);
-			}
-			break;
-
-
-		case UPDATE_WRITE_AS_ONES:
-
-			/* Set positions outside the field to all ones */
-
-			merged_value |= ~mask;
-			break;
-
-
-		case UPDATE_WRITE_AS_ZEROS:
-
-			/* Set positions outside the field to all zeros */
-
-			merged_value &= mask;
-			break;
-
-
-		default:
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Write_with_update_rule: Unknown Update_rule setting: %x\n",
-				obj_desc->common_field.update_rule));
-			return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
-			break;
-		}
-	}
-
-
-	/* Write the merged value */
-
-	status = acpi_ex_write_field_datum (obj_desc, field_datum_byte_offset,
-			  merged_value);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_BFIELD, "Mask %X Datum_offset %X Value %X, Merged_value %X\n",
-		mask, field_datum_byte_offset, field_value, merged_value));
-
-	return_ACPI_STATUS (status);
-}
-
-
-/*******************************************************************************
- *
  * FUNCTION:    Acpi_ex_insert_into_field
  *
  * PARAMETERS:  *Obj_desc           - Field to be set
@@ -725,15 +833,15 @@
 	acpi_status             status;
 	u32                     field_datum_byte_offset;
 	u32                     datum_offset;
-	u32                     mask;
-	u32                     merged_datum;
-	u32                     previous_raw_datum;
-	u32                     this_raw_datum;
+	acpi_integer            mask;
+	acpi_integer            merged_datum;
+	acpi_integer            previous_raw_datum;
+	acpi_integer            this_raw_datum;
 	u32                     byte_field_length;
 	u32                     datum_count;
 
 
-	FUNCTION_TRACE ("Ex_insert_into_field");
+	ACPI_FUNCTION_TRACE ("Ex_insert_into_field");
 
 
 	/*
@@ -742,24 +850,21 @@
 	 * larger than the field, this typically happens when an integer is
 	 * written to a field that is actually smaller than an integer.
 	 */
-	byte_field_length = ROUND_BITS_UP_TO_BYTES (obj_desc->common_field.bit_length);
+	byte_field_length = ACPI_ROUND_BITS_UP_TO_BYTES (obj_desc->common_field.bit_length);
 	if (buffer_length < byte_field_length) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Buffer length %X too small for field %X\n",
 			buffer_length, byte_field_length));
 
-		/* TBD: Need a better error code */
-
 		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
 	}
 
 	/* Convert byte count to datum count, round up if necessary */
 
-	datum_count = ROUND_UP_TO (byte_field_length, obj_desc->common_field.access_byte_width);
+	datum_count = ACPI_ROUND_UP_TO (byte_field_length, obj_desc->common_field.access_byte_width);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-		"Byte_len=%x, Datum_len=%x, Bit_gran=%x, Byte_gran=%x\n",
-		byte_field_length, datum_count, obj_desc->common_field.access_bit_width,
-		obj_desc->common_field.access_byte_width));
+		"Byte_len=%x, Datum_len=%x, Byte_gran=%x\n",
+		byte_field_length, datum_count, obj_desc->common_field.access_byte_width));
 
 	/*
 	 * Break the request into up to three parts (similar to an I/O request):
@@ -785,15 +890,15 @@
 	 *
 	 * Mask off bits that are "below" the field (if any)
 	 */
-	mask = MASK_BITS_BELOW (obj_desc->common_field.start_field_bit_offset);
+	mask = ACPI_MASK_BITS_BELOW (obj_desc->common_field.start_field_bit_offset);
 
 	/* If the field fits in one datum, may need to mask upper bits */
 
-	if ((obj_desc->common_field.access_flags & AFIELD_SINGLE_DATUM) &&
+	if ((obj_desc->common_field.flags & AOPOBJ_SINGLE_DATUM) &&
 		 obj_desc->common_field.end_field_valid_bits) {
 		/* There are bits above the field, mask them off also */
 
-		mask &= MASK_BITS_ABOVE (obj_desc->common_field.end_field_valid_bits);
+		mask &= ACPI_MASK_BITS_ABOVE (obj_desc->common_field.end_field_valid_bits);
 	}
 
 	/* Shift and mask the value into the field position */
@@ -803,7 +908,7 @@
 
 	/* Apply the update rule (if necessary) and write the datum to the field */
 
-	status = acpi_ex_write_field_datum_with_update_rule (obj_desc, mask, merged_datum,
+	status = acpi_ex_write_with_update_rule (obj_desc, mask, merged_datum,
 			   field_datum_byte_offset);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
@@ -812,7 +917,7 @@
 	/* If the entire field fits within one datum, we are done. */
 
 	if ((datum_count == 1) &&
-	   (obj_desc->common_field.access_flags & AFIELD_SINGLE_DATUM)) {
+	   (obj_desc->common_field.flags & AOPOBJ_SINGLE_DATUM)) {
 		return_ACPI_STATUS (AE_OK);
 	}
 
@@ -849,7 +954,6 @@
 				(previous_raw_datum >> obj_desc->common_field.datum_valid_bits) |
 				(this_raw_datum << obj_desc->common_field.start_field_bit_offset);
 		}
-
 		else {
 			/* Field began aligned on datum boundary */
 
@@ -874,24 +978,23 @@
 				 *
 				 * Mask off the unused bits above (after) the end-of-field
 				 */
-				mask = MASK_BITS_ABOVE (obj_desc->common_field.end_field_valid_bits);
+				mask = ACPI_MASK_BITS_ABOVE (obj_desc->common_field.end_field_valid_bits);
 				merged_datum &= mask;
 
 				/* Write the last datum with the update rule */
 
-				status = acpi_ex_write_field_datum_with_update_rule (obj_desc, mask,
-						  merged_datum, field_datum_byte_offset);
+				status = acpi_ex_write_with_update_rule (obj_desc, mask, merged_datum,
+						   field_datum_byte_offset);
 				if (ACPI_FAILURE (status)) {
 					return_ACPI_STATUS (status);
 				}
 			}
 		}
-
 		else {
 			/* Normal case -- write the completed datum */
 
-			status = acpi_ex_write_field_datum (obj_desc,
-					  field_datum_byte_offset, merged_datum);
+			status = acpi_ex_field_datum_io (obj_desc, field_datum_byte_offset,
+					  &merged_datum, ACPI_WRITE);
 			if (ACPI_FAILURE (status)) {
 				return_ACPI_STATUS (status);
 			}
diff -Nru a/drivers/acpi/executer/exmisc.c b/drivers/acpi/executer/exmisc.c
--- a/drivers/acpi/executer/exmisc.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exmisc.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exmisc - ACPI AML (p-code) execution - specific opcodes
- *              $Revision: 92 $
+ *              $Revision: 100 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exmisc")
+	 ACPI_MODULE_NAME    ("exmisc")
 
 
 /*******************************************************************************
@@ -59,10 +59,12 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_PTR ("Ex_get_object_reference", obj_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_get_object_reference", obj_desc);
 
 
-	if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_INTERNAL)) {
+	switch (ACPI_GET_DESCRIPTOR_TYPE (obj_desc)) {
+	case ACPI_DESC_TYPE_INTERNAL:
+
 		if (obj_desc->common.type != INTERNAL_TYPE_REFERENCE) {
 			*return_desc = NULL;
 			status = AE_TYPE;
@@ -77,8 +79,9 @@
 		case AML_LOCAL_OP:
 		case AML_ARG_OP:
 
-			*return_desc = (void *) acpi_ds_method_data_get_node (obj_desc->reference.opcode,
-					  obj_desc->reference.offset, walk_state);
+			status = acpi_ds_method_data_get_node (obj_desc->reference.opcode,
+					  obj_desc->reference.offset, walk_state,
+					  (acpi_namespace_node **) return_desc);
 			break;
 
 		default:
@@ -89,18 +92,22 @@
 			status = AE_AML_INTERNAL;
 			goto cleanup;
 		}
+		break;
 
-	}
 
-	else if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_NAMED)) {
+	case ACPI_DESC_TYPE_NAMED:
+
 		/* Must be a named object;  Just return the Node */
 
 		*return_desc = obj_desc;
-	}
+		break;
+
+
+	default:
 
-	else {
 		*return_desc = NULL;
 		status = AE_TYPE;
+		break;
 	}
 
 
@@ -113,7 +120,7 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_do_concatenate
+ * FUNCTION:    Acpi_ex_concat_template
  *
  * PARAMETERS:  *Obj_desc           - Object to be converted.  Must be an
  *                                    Integer, Buffer, or String
@@ -121,13 +128,106 @@
  *
  * RETURN:      Status
  *
+ * DESCRIPTION: Concatenate two resource templates
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ex_concat_template (
+	acpi_operand_object     *obj_desc1,
+	acpi_operand_object     *obj_desc2,
+	acpi_operand_object     **actual_return_desc,
+	acpi_walk_state         *walk_state)
+{
+	acpi_status             status;
+	acpi_operand_object     *return_desc;
+	NATIVE_CHAR             *new_buf;
+	u8                      *end_tag1;
+	u8                      *end_tag2;
+	ACPI_SIZE               length1;
+	ACPI_SIZE               length2;
+
+
+	ACPI_FUNCTION_TRACE ("Ex_concat_template");
+
+
+	/* Find the End_tags in each resource template */
+
+	end_tag1 = acpi_ut_get_resource_end_tag (obj_desc1);
+	end_tag2 = acpi_ut_get_resource_end_tag (obj_desc2);
+	if (!end_tag1 || !end_tag2) {
+		return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
+	}
+
+	/* Create a new buffer object for the result */
+
+	return_desc = acpi_ut_create_internal_object (ACPI_TYPE_BUFFER);
+	if (!return_desc) {
+		return_ACPI_STATUS (AE_NO_MEMORY);
+	}
+
+	/* Allocate a new buffer for the result */
+
+	length1 = ACPI_PTR_DIFF (end_tag1, obj_desc1->buffer.pointer);
+	length2 = ACPI_PTR_DIFF (end_tag2, obj_desc2->buffer.pointer) +
+			  2; /* Size of END_TAG */
+
+	new_buf = ACPI_MEM_ALLOCATE (length1 + length2);
+	if (!new_buf) {
+		ACPI_REPORT_ERROR
+			(("Ex_concat_template: Buffer allocation failure\n"));
+		status = AE_NO_MEMORY;
+		goto cleanup;
+	}
+
+	/* Copy the templates to the new descriptor */
+
+	ACPI_MEMCPY (new_buf, obj_desc1->buffer.pointer, length1);
+	ACPI_MEMCPY (new_buf + length1, obj_desc2->buffer.pointer, length2);
+
+	/*
+	 * Point the return object to the new buffer
+	 */
+	return_desc->buffer.pointer = (u8 *) new_buf;
+	return_desc->buffer.length = length1 + length2;
+
+	/* Compute the new checksum */
+
+	new_buf[return_desc->buffer.length - 1] =
+			acpi_ut_generate_checksum (return_desc->buffer.pointer,
+					 (return_desc->buffer.length - 1));
+
+	/* Return the completed template descriptor */
+
+	*actual_return_desc = return_desc;
+	return_ACPI_STATUS (AE_OK);
+
+
+cleanup:
+
+	acpi_ut_remove_reference (return_desc);
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_do_concatenate
+ *
+ * PARAMETERS:  Obj_desc1           - First source object
+ *              Obj_desc2           - Second source object
+ *              Actual_return_desc  - Where to place the return object
+ *              Walk_state          - Current walk state
+ *
+ * RETURN:      Status
+ *
  * DESCRIPTION: Concatenate two objects OF THE SAME TYPE.
  *
  ******************************************************************************/
 
 acpi_status
 acpi_ex_do_concatenate (
-	acpi_operand_object     *obj_desc,
+	acpi_operand_object     *obj_desc1,
 	acpi_operand_object     *obj_desc2,
 	acpi_operand_object     **actual_return_desc,
 	acpi_walk_state         *walk_state)
@@ -140,7 +240,7 @@
 	u32                     integer_size = sizeof (acpi_integer);
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -149,7 +249,7 @@
 	 * 2) Two Strings concatenated to produce a string
 	 * 3) Two Buffers concatenated to produce a buffer
 	 */
-	switch (obj_desc->common.type) {
+	switch (obj_desc1->common.type) {
 	case ACPI_TYPE_INTEGER:
 
 		/* Handle both ACPI 1.0 and ACPI 2.0 Integer widths */
@@ -175,7 +275,7 @@
 		return_desc->buffer.length = integer_size * 2;
 		new_buf = ACPI_MEM_CALLOCATE (return_desc->buffer.length);
 		if (!new_buf) {
-			REPORT_ERROR
+			ACPI_REPORT_ERROR
 				(("Ex_do_concatenate: Buffer allocation failure\n"));
 			status = AE_NO_MEMORY;
 			goto cleanup;
@@ -185,7 +285,7 @@
 
 		/* Convert the first integer */
 
-		this_integer = obj_desc->integer.value;
+		this_integer = obj_desc1->integer.value;
 		for (i = 0; i < integer_size; i++) {
 			new_buf[i] = (u8) this_integer;
 			this_integer >>= 8;
@@ -211,24 +311,24 @@
 
 		/* Operand0 is string  */
 
-		new_buf = ACPI_MEM_ALLOCATE (obj_desc->string.length +
+		new_buf = ACPI_MEM_ALLOCATE (obj_desc1->string.length +
 				  obj_desc2->string.length + 1);
 		if (!new_buf) {
-			REPORT_ERROR
+			ACPI_REPORT_ERROR
 				(("Ex_do_concatenate: String allocation failure\n"));
 			status = AE_NO_MEMORY;
 			goto cleanup;
 		}
 
-		STRCPY (new_buf, obj_desc->string.pointer);
-		STRCPY (new_buf + obj_desc->string.length,
+		ACPI_STRCPY (new_buf, obj_desc1->string.pointer);
+		ACPI_STRCPY (new_buf + obj_desc1->string.length,
 				  obj_desc2->string.pointer);
 
 		/* Point the return object to the new string */
 
 		return_desc->string.pointer = new_buf;
-		return_desc->string.length = obj_desc->string.length +=
-				  obj_desc2->string.length;
+		return_desc->string.length = obj_desc1->string.length +
+				   obj_desc2->string.length;
 		break;
 
 
@@ -241,27 +341,27 @@
 			return (AE_NO_MEMORY);
 		}
 
-		new_buf = ACPI_MEM_ALLOCATE (obj_desc->buffer.length +
+		new_buf = ACPI_MEM_ALLOCATE (obj_desc1->buffer.length +
 				  obj_desc2->buffer.length);
 		if (!new_buf) {
-			REPORT_ERROR
+			ACPI_REPORT_ERROR
 				(("Ex_do_concatenate: Buffer allocation failure\n"));
 			status = AE_NO_MEMORY;
 			goto cleanup;
 		}
 
-		MEMCPY (new_buf, obj_desc->buffer.pointer,
-				  obj_desc->buffer.length);
-		MEMCPY (new_buf + obj_desc->buffer.length, obj_desc2->buffer.pointer,
+		ACPI_MEMCPY (new_buf, obj_desc1->buffer.pointer,
+				  obj_desc1->buffer.length);
+		ACPI_MEMCPY (new_buf + obj_desc1->buffer.length, obj_desc2->buffer.pointer,
 				   obj_desc2->buffer.length);
 
 		/*
 		 * Point the return object to the new buffer
 		 */
 
-		return_desc->buffer.pointer    = (u8 *) new_buf;
-		return_desc->buffer.length     = obj_desc->buffer.length +
-				 obj_desc2->buffer.length;
+		return_desc->buffer.pointer = (u8 *) new_buf;
+		return_desc->buffer.length = obj_desc1->buffer.length +
+				  obj_desc2->buffer.length;
 		break;
 
 
@@ -270,7 +370,6 @@
 		return_desc = NULL;
 	}
 
-
 	*actual_return_desc = return_desc;
 	return (AE_OK);
 
@@ -288,7 +387,7 @@
  *
  * PARAMETERS:  Opcode              - AML opcode
  *              Operand0            - Integer operand #0
- *              Operand0            - Integer operand #1
+ *              Operand1            - Integer operand #1
  *
  * RETURN:      Integer result of the operation
  *
@@ -369,7 +468,7 @@
  *
  * PARAMETERS:  Opcode              - AML opcode
  *              Operand0            - Integer operand #0
- *              Operand0            - Integer operand #1
+ *              Operand1            - Integer operand #1
  *
  * RETURN:      TRUE/FALSE result of the operation
  *
diff -Nru a/drivers/acpi/executer/exmutex.c b/drivers/acpi/executer/exmutex.c
--- a/drivers/acpi/executer/exmutex.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exmutex.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exmutex - ASL Mutex Acquire/Release functions
- *              $Revision: 7 $
+ *              $Revision: 10 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acevents.h"
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exmutex")
+	 ACPI_MODULE_NAME    ("exmutex")
 
 
 /*******************************************************************************
@@ -51,13 +51,23 @@
 acpi_ex_unlink_mutex (
 	acpi_operand_object     *obj_desc)
 {
+	ACPI_THREAD_STATE       *thread = obj_desc->mutex.owner_thread;
+
+
+	if (!thread) {
+		return;
+	}
 
 	if (obj_desc->mutex.next) {
 		(obj_desc->mutex.next)->mutex.prev = obj_desc->mutex.prev;
 	}
+
 	if (obj_desc->mutex.prev) {
 		(obj_desc->mutex.prev)->mutex.next = obj_desc->mutex.next;
 	}
+	else {
+		thread->acquired_mutex_list = obj_desc->mutex.next;
+	}
 }
 
 
@@ -77,23 +87,27 @@
 void
 acpi_ex_link_mutex (
 	acpi_operand_object     *obj_desc,
-	acpi_operand_object     *list_head)
+	ACPI_THREAD_STATE       *thread)
 {
+	acpi_operand_object     *list_head;
+
+
+	list_head = thread->acquired_mutex_list;
 
 	/* This object will be the first object in the list */
 
-	obj_desc->mutex.prev = list_head;
-	obj_desc->mutex.next = list_head->mutex.next;
+	obj_desc->mutex.prev = NULL;
+	obj_desc->mutex.next = list_head;
 
 	/* Update old first object to point back to this object */
 
-	if (list_head->mutex.next) {
-		(list_head->mutex.next)->mutex.prev = obj_desc;
+	if (list_head) {
+		list_head->mutex.prev = obj_desc;
 	}
 
 	/* Update list head */
 
-	list_head->mutex.next = obj_desc;
+	thread->acquired_mutex_list = obj_desc;
 }
 
 
@@ -119,7 +133,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ex_acquire_mutex", obj_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_acquire_mutex", obj_desc);
 
 	if (!obj_desc) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
@@ -129,15 +143,18 @@
 	 * Current Sync must be less than or equal to the sync level of the
 	 * mutex.  This mechanism provides some deadlock prevention
 	 */
-	if (walk_state->current_sync_level > obj_desc->mutex.sync_level) {
+	if (walk_state->thread->current_sync_level > obj_desc->mutex.sync_level) {
 		return_ACPI_STATUS (AE_AML_MUTEX_ORDER);
 	}
 
 	/*
-	 * If the mutex is already owned by this thread,
-	 * just increment the acquisition depth
+	 * Support for multiple acquires by the owning thread
 	 */
-	if (obj_desc->mutex.owner == walk_state) {
+	if (obj_desc->mutex.owner_thread == walk_state->thread) {
+		/*
+		 * The mutex is already owned by this thread,
+		 * just increment the acquisition depth
+		 */
 		obj_desc->mutex.acquisition_depth++;
 		return_ACPI_STATUS (AE_OK);
 	}
@@ -153,14 +170,14 @@
 
 	/* Have the mutex, update mutex and walk info */
 
-	obj_desc->mutex.owner = walk_state;
+	obj_desc->mutex.owner_thread    = walk_state->thread;
 	obj_desc->mutex.acquisition_depth = 1;
-	walk_state->current_sync_level = obj_desc->mutex.sync_level;
 
-	/* Link the mutex to the walk state for force-unlock at method exit */
+	walk_state->thread->current_sync_level = obj_desc->mutex.sync_level;
 
-	acpi_ex_link_mutex (obj_desc, (acpi_operand_object *)
-			 &(walk_state->walk_list->acquired_mutex_list));
+	/* Link the mutex to the current thread for force-unlock at method exit */
+
+	acpi_ex_link_mutex (obj_desc, walk_state->thread);
 
 	return_ACPI_STATUS (AE_OK);
 }
@@ -186,7 +203,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ex_release_mutex");
+	ACPI_FUNCTION_TRACE ("Ex_release_mutex");
 
 
 	if (!obj_desc) {
@@ -195,13 +212,13 @@
 
 	/* The mutex must have been previously acquired in order to release it */
 
-	if (!obj_desc->mutex.owner) {
+	if (!obj_desc->mutex.owner_thread) {
 		return_ACPI_STATUS (AE_AML_MUTEX_NOT_ACQUIRED);
 	}
 
 	/* The Mutex is owned, but this thread must be the owner */
 
-	if (obj_desc->mutex.owner != walk_state) {
+	if (obj_desc->mutex.owner_thread != walk_state->thread) {
 		return_ACPI_STATUS (AE_AML_NOT_OWNER);
 	}
 
@@ -209,7 +226,7 @@
 	 * The sync level of the mutex must be less than or
 	 * equal to the current sync level
 	 */
-	if (obj_desc->mutex.sync_level > walk_state->current_sync_level) {
+	if (obj_desc->mutex.sync_level > walk_state->thread->current_sync_level) {
 		return_ACPI_STATUS (AE_AML_MUTEX_ORDER);
 	}
 
@@ -223,6 +240,9 @@
 		return_ACPI_STATUS (AE_OK);
 	}
 
+	/* Unlink the mutex from the owner's list */
+
+	acpi_ex_unlink_mutex (obj_desc);
 
 	/* Release the mutex */
 
@@ -230,12 +250,8 @@
 
 	/* Update the mutex and walk state */
 
-	obj_desc->mutex.owner = NULL;
-	walk_state->current_sync_level = obj_desc->mutex.sync_level;
-
-	/* Unlink the mutex from the owner's list */
-
-	acpi_ex_unlink_mutex (obj_desc);
+	obj_desc->mutex.owner_thread = NULL;
+	walk_state->thread->current_sync_level = obj_desc->mutex.sync_level;
 
 	return_ACPI_STATUS (status);
 }
@@ -255,13 +271,13 @@
 
 acpi_status
 acpi_ex_release_all_mutexes (
-	acpi_operand_object     *list_head)
+	ACPI_THREAD_STATE       *thread)
 {
-	acpi_operand_object     *next = list_head->mutex.next;
+	acpi_operand_object     *next = thread->acquired_mutex_list;
 	acpi_operand_object     *this;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -271,16 +287,17 @@
 		this = next;
 		next = this->mutex.next;
 
-		/* Mark mutex un-owned */
-
-		this->mutex.owner = NULL;
-		this->mutex.prev = NULL;
-		this->mutex.next = NULL;
-		this->mutex.acquisition_depth = 0;
+		this->mutex.acquisition_depth = 1;
+		this->mutex.prev             = NULL;
+		this->mutex.next             = NULL;
 
 		 /* Release the mutex */
 
 		acpi_ex_system_release_mutex (this);
+
+		/* Mark mutex unowned */
+
+		this->mutex.owner_thread     = NULL;
 	}
 
 	return (AE_OK);
diff -Nru a/drivers/acpi/executer/exnames.c b/drivers/acpi/executer/exnames.c
--- a/drivers/acpi/executer/exnames.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exnames.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exnames - interpreter/scanner name load/execute
- *              $Revision: 83 $
+ *              $Revision: 90 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exnames")
+	 ACPI_MODULE_NAME    ("exnames")
 
 
 /* AML Package Length encodings */
@@ -67,7 +67,7 @@
 	NATIVE_CHAR             *name_string;
 	u32                      size_needed;
 
-	FUNCTION_TRACE ("Ex_allocate_name_string");
+	ACPI_FUNCTION_TRACE ("Ex_allocate_name_string");
 
 
 	/*
@@ -75,7 +75,7 @@
 	 * Also, one byte for the null terminator.
 	 * This may actually be somewhat longer than needed.
 	 */
-	if (prefix_count == (u32) -1) {
+	if (prefix_count == ACPI_UINT32_MAX) {
 		/* Special case for root */
 
 		size_needed = 1 + (ACPI_NAME_SIZE * num_name_segs) + 2 + 1;
@@ -90,7 +90,7 @@
 	 */
 	name_string = ACPI_MEM_ALLOCATE (size_needed);
 	if (!name_string) {
-		REPORT_ERROR (("Ex_allocate_name_string: Could not allocate size %d\n", size_needed));
+		ACPI_REPORT_ERROR (("Ex_allocate_name_string: Could not allocate size %d\n", size_needed));
 		return_PTR (NULL);
 	}
 
@@ -98,10 +98,9 @@
 
 	/* Set up Root or Parent prefixes if needed */
 
-	if (prefix_count == (u32) -1) {
+	if (prefix_count == ACPI_UINT32_MAX) {
 		*temp_ptr++ = AML_ROOT_PREFIX;
 	}
-
 	else {
 		while (prefix_count--) {
 			*temp_ptr++ = AML_PARENT_PREFIX;
@@ -117,7 +116,6 @@
 		*temp_ptr++ = AML_MULTI_NAME_PREFIX_OP;
 		*temp_ptr++ = (char) num_name_segs;
 	}
-
 	else if (2 == num_name_segs) {
 		/* Set up dual prefixes */
 
@@ -156,7 +154,7 @@
 	NATIVE_CHAR             char_buf[5];
 
 
-	FUNCTION_TRACE ("Ex_name_segment");
+	ACPI_FUNCTION_TRACE ("Ex_name_segment");
 
 
 	/*
@@ -174,7 +172,7 @@
 
 	for (index = 4;
 		(index > 0) && (acpi_ut_valid_acpi_character (*aml_address));
-		--index) {
+		index--) {
 		char_buf[4 - index] = *aml_address++;
 		ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "%c\n", char_buf[4 - index]));
 	}
@@ -188,17 +186,15 @@
 		char_buf[4] = '\0';
 
 		if (name_string) {
-			STRCAT (name_string, char_buf);
+			ACPI_STRCAT (name_string, char_buf);
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
 				"Appended to - %s \n", name_string));
 		}
-
 		else {
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
 				"No Name string - %s \n", char_buf));
 		}
 	}
-
 	else if (4 == index) {
 		/*
 		 * First character was not a valid name character,
@@ -209,7 +205,6 @@
 			char_buf[0]));
 		status = AE_CTRL_PENDING;
 	}
-
 	else {
 		/* Segment started with one or more valid characters, but fewer than 4 */
 
@@ -235,10 +230,9 @@
  *
  ******************************************************************************/
 
-
 acpi_status
 acpi_ex_get_name_string (
-	acpi_object_type8       data_type,
+	acpi_object_type        data_type,
 	u8                      *in_aml_address,
 	NATIVE_CHAR             **out_name_string,
 	u32                     *out_name_length)
@@ -248,11 +242,10 @@
 	NATIVE_CHAR             *name_string = NULL;
 	u32                     num_segments;
 	u32                     prefix_count = 0;
-	u8                      prefix = 0;
 	u8                      has_prefix = FALSE;
 
 
-	FUNCTION_TRACE_PTR ("Ex_get_name_string", aml_address);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_get_name_string", aml_address);
 
 
 	if (INTERNAL_TYPE_REGION_FIELD == data_type  ||
@@ -268,24 +261,22 @@
 			status = acpi_ex_name_segment (&aml_address, name_string);
 		}
 	}
-
 	else {
 		/*
 		 * Data_type is not a field name.
 		 * Examine first character of name for root or parent prefix operators
 		 */
 		switch (*aml_address) {
-
 		case AML_ROOT_PREFIX:
 
-			prefix = *aml_address++;
-			ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Root_prefix: %x\n", prefix));
+			ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Root_prefix(\\) at %p\n", aml_address));
 
 			/*
 			 * Remember that we have a Root_prefix --
 			 * see comment in Acpi_ex_allocate_name_string()
 			 */
-			prefix_count = (u32) -1;
+			aml_address++;
+			prefix_count = ACPI_UINT32_MAX;
 			has_prefix = TRUE;
 			break;
 
@@ -295,18 +286,21 @@
 			/* Increment past possibly multiple parent prefixes */
 
 			do {
-				prefix = *aml_address++;
-				ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Parent_prefix: %x\n", prefix));
+				ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Parent_prefix (^) at %p\n", aml_address));
 
-				++prefix_count;
+				aml_address++;
+				prefix_count++;
 
 			} while (*aml_address == AML_PARENT_PREFIX);
+
 			has_prefix = TRUE;
 			break;
 
 
 		default:
 
+			/* Not a prefix character */
+
 			break;
 		}
 
@@ -314,12 +308,11 @@
 		/* Examine first character of name for name segment prefix operator */
 
 		switch (*aml_address) {
-
 		case AML_DUAL_NAME_PREFIX:
 
-			prefix = *aml_address++;
-			ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Dual_name_prefix: %x\n", prefix));
+			ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Dual_name_prefix at %p\n", aml_address));
 
+			aml_address++;
 			name_string = acpi_ex_allocate_name_string (prefix_count, 2);
 			if (!name_string) {
 				status = AE_NO_MEMORY;
@@ -339,12 +332,12 @@
 
 		case AML_MULTI_NAME_PREFIX_OP:
 
-			prefix = *aml_address++;
-			ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Multi_name_prefix: %x\n", prefix));
+			ACPI_DEBUG_PRINT ((ACPI_DB_LOAD, "Multi_name_prefix at %p\n", aml_address));
 
 			/* Fetch count of segments remaining in name path */
 
-			num_segments = *aml_address++;
+			aml_address++;
+			num_segments = *aml_address;
 
 			name_string = acpi_ex_allocate_name_string (prefix_count, num_segments);
 			if (!name_string) {
@@ -354,11 +347,12 @@
 
 			/* Indicate that we processed a prefix */
 
+			aml_address++;
 			has_prefix = TRUE;
 
 			while (num_segments &&
 					(status = acpi_ex_name_segment (&aml_address, name_string)) == AE_OK) {
-				--num_segments;
+				num_segments--;
 			}
 
 			break;
@@ -368,7 +362,7 @@
 
 			/* Null_name valid as of 8-12-98 ASL/AML Grammar Update */
 
-			if (-1 == prefix_count) {
+			if (prefix_count == ACPI_UINT32_MAX) {
 				ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Name_seg is \"\\\" followed by NULL\n"));
 			}
 
@@ -396,19 +390,16 @@
 
 			status = acpi_ex_name_segment (&aml_address, name_string);
 			break;
-
-		}   /* Switch (Peek_op ())   */
+		}
 	}
 
-
 	if (AE_CTRL_PENDING == status && has_prefix) {
 		/* Ran out of segments after processing a prefix */
 
-		REPORT_ERROR (
+		ACPI_REPORT_ERROR (
 			("Ex_do_name: Malformed Name at %p\n", name_string));
 		status = AE_AML_BAD_NAME;
 	}
-
 
 	*out_name_string = name_string;
 	*out_name_length = (u32) (aml_address - in_aml_address);
diff -Nru a/drivers/acpi/executer/exoparg1.c b/drivers/acpi/executer/exoparg1.c
--- a/drivers/acpi/executer/exoparg1.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/executer/exoparg1.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exoparg1 - AML execution - opcodes with 1 argument
- *              $Revision: 120 $
+ *              $Revision: 134 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exoparg1")
+	 ACPI_MODULE_NAME    ("exoparg1")
 
 
 /*!
@@ -81,10 +81,10 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_1A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_1A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
-	/* Examine the opcode */
+	/* Examine the AML opcode */
 
 	switch (walk_state->opcode) {
 	case AML_RELEASE_OP:    /*  Release (Mutex_object) */
@@ -107,13 +107,13 @@
 
 	case AML_SLEEP_OP:      /*  Sleep (Msec_time) */
 
-		acpi_ex_system_do_suspend ((u32) operand[0]->integer.value);
+		status = acpi_ex_system_do_suspend ((u32) operand[0]->integer.value);
 		break;
 
 
 	case AML_STALL_OP:      /*  Stall (Usec_time) */
 
-		acpi_ex_system_do_stall ((u32) operand[0]->integer.value);
+		status = acpi_ex_system_do_stall ((u32) operand[0]->integer.value);
 		break;
 
 
@@ -125,7 +125,7 @@
 
 	default:                /*  Unknown opcode  */
 
-		REPORT_ERROR (("Acpi_ex_opcode_1A_0T_0R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_1A_0T_0R: Unknown opcode %X\n",
 			walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		break;
@@ -156,19 +156,20 @@
 	acpi_operand_object     **operand = &walk_state->operands[0];
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_1A_1T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_1A_1T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
-	switch (walk_state->opcode) {
+	/* Examine the AML opcode */
 
+	switch (walk_state->opcode) {
 	case AML_LOAD_OP:
 
-		status = acpi_ex_load_op (operand[0], operand[1]);
+		status = acpi_ex_load_op (operand[0], operand[1], walk_state);
 		break;
 
 	default:                        /* Unknown opcode */
 
-		REPORT_ERROR (("Acpi_ex_opcode_1A_1T_0R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_1A_1T_0R: Unknown opcode %X\n",
 			walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
@@ -208,7 +209,7 @@
 	acpi_integer            digit;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_1A_1T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_1A_1T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	/* Create a return object of type Integer for most opcodes */
@@ -230,6 +231,7 @@
 		break;
 	}
 
+	/* Examine the AML opcode */
 
 	switch (walk_state->opcode) {
 
@@ -241,7 +243,6 @@
 
 	case AML_FIND_SET_LEFT_BIT_OP:  /* Find_set_left_bit (Operand, Result) */
 
-
 		return_desc->integer.value = operand[0]->integer.value;
 
 		/*
@@ -258,7 +259,6 @@
 
 	case AML_FIND_SET_RIGHT_BIT_OP: /* Find_set_right_bit (Operand, Result) */
 
-
 		return_desc->integer.value = operand[0]->integer.value;
 
 		/*
@@ -312,7 +312,8 @@
 
 		if (operand[0]->integer.value > ACPI_MAX_BCD_VALUE) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "BCD overflow: %8.8X%8.8X\n",
-				HIDWORD(operand[0]->integer.value), LODWORD(operand[0]->integer.value)));
+				ACPI_HIDWORD(operand[0]->integer.value),
+				ACPI_LODWORD(operand[0]->integer.value)));
 			status = AE_AML_NUMERIC_OVERFLOW;
 			goto cleanup;
 		}
@@ -330,7 +331,7 @@
 			/* Create the BCD digit from the remainder above */
 
 			if (digit > 0) {
-				return_desc->integer.value += (temp32 << (i * 4));
+				return_desc->integer.value += ((acpi_integer) temp32 << (i * 4));
 			}
 		}
 		break;
@@ -371,7 +372,6 @@
 
 		return_desc->integer.value = ACPI_INTEGER_MAX;
 		goto cleanup;
-		break;
 
 
 	case AML_STORE_OP:              /* Store (Source, Target) */
@@ -395,7 +395,6 @@
 		walk_state->result_obj = operand[0];
 		walk_state->operands[0] = NULL; /* Prevent deletion */
 		return_ACPI_STATUS (status);
-		break;
 
 
 	/*
@@ -403,8 +402,7 @@
 	 */
 	case AML_COPY_OP:               /* Copy (Source, Target) */
 
-		status = AE_NOT_IMPLEMENTED;
-		goto cleanup;
+		status = acpi_ut_copy_iobject_to_iobject (operand[0], &return_desc, walk_state);
 		break;
 
 
@@ -432,29 +430,26 @@
 		break;
 
 
-	/*
-	 * These are two obsolete opcodes
-	 */
 	case AML_SHIFT_LEFT_BIT_OP:     /*  Shift_left_bit (Source, Bit_num) */
 	case AML_SHIFT_RIGHT_BIT_OP:    /*  Shift_right_bit (Source, Bit_num) */
 
-
+		/*
+		 * These are two obsolete opcodes
+		 */
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "%s is obsolete and not implemented\n",
 				  acpi_ps_get_opcode_name (walk_state->opcode)));
 		status = AE_SUPPORT;
 		goto cleanup;
-		break;
 
 
 	default:                        /* Unknown opcode */
 
-		REPORT_ERROR (("Acpi_ex_opcode_1A_1T_1R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_1A_1T_1R: Unknown opcode %X\n",
 			walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
 	}
 
-
 	/*
 	 * Store the return value computed above into the target object
 	 */
@@ -499,13 +494,12 @@
 	acpi_integer            value;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_1A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_1A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
-	/* Get the operand and decode the opcode */
+	/* Examine the AML opcode */
 
 	switch (walk_state->opcode) {
-
 	case AML_LNOT_OP:               /* LNot (Operand) */
 
 		return_desc = acpi_ut_create_internal_object (ACPI_TYPE_INTEGER);
@@ -523,10 +517,10 @@
 
 		/*
 		 * Since we are expecting a Reference operand, it
-		 * can be either a Node or an internal object.
+		 * can be either a NS Node or an internal object.
 		 */
 		return_desc = operand[0];
-		if (VALID_DESCRIPTOR_TYPE (operand[0], ACPI_DESC_TYPE_INTERNAL)) {
+		if (ACPI_GET_DESCRIPTOR_TYPE (operand[0]) == ACPI_DESC_TYPE_INTERNAL) {
 			/* Internal reference object - prevent deletion */
 
 			acpi_ut_add_reference (return_desc);
@@ -582,7 +576,7 @@
 
 			case AML_DEBUG_OP:
 
-				/* Per 1.0b spec, Debug object is of type "Debug_object" */
+				/* The Debug Object is of type "Debug_object" */
 
 				type = ACPI_TYPE_DEBUG_OBJECT;
 				break;
@@ -601,7 +595,6 @@
 					 */
 					type = (*(operand[0]->reference.where))->common.type;
 				}
-
 				break;
 
 
@@ -615,13 +608,12 @@
 
 			default:
 
-				REPORT_ERROR (("Acpi_ex_opcode_1A_0T_1R/Type_op: Internal error - Unknown Reference subtype %X\n",
+				ACPI_REPORT_ERROR (("Acpi_ex_opcode_1A_0T_1R/Type_op: Internal error - Unknown Reference subtype %X\n",
 					operand[0]->reference.opcode));
 				status = AE_AML_INTERNAL;
 				goto cleanup;
 			}
 		}
-
 		else {
 			/*
 			 * It's not a Reference, so it must be a direct name pointer.
@@ -655,15 +647,19 @@
 	case AML_SIZE_OF_OP:            /* Size_of (Source_object) */
 
 		temp_desc = operand[0];
-		if (VALID_DESCRIPTOR_TYPE (operand[0], ACPI_DESC_TYPE_NAMED)) {
+		if (ACPI_GET_DESCRIPTOR_TYPE (operand[0]) == ACPI_DESC_TYPE_NAMED) {
 			temp_desc = acpi_ns_get_attached_object ((acpi_namespace_node *) operand[0]);
 		}
 
 		if (!temp_desc) {
 			value = 0;
 		}
-
 		else {
+			/*
+			 * Type is guaranteed to be a buffer, string, or package at this
+			 * point (even if the original operand was an object reference, it
+			 * will be resolved and typechecked during operand resolution.)
+			 */
 			switch (temp_desc->common.type) {
 			case ACPI_TYPE_BUFFER:
 				value = temp_desc->buffer.length;
@@ -677,16 +673,9 @@
 				value = temp_desc->package.count;
 				break;
 
-			case INTERNAL_TYPE_REFERENCE:
-
-				/* TBD: this must be a reference to a buf/str/pkg?? */
-
-				value = 4;
-				break;
-
 			default:
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Not Buf/Str/Pkg - found type %X\n",
-					temp_desc->common.type));
+				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Size_of, Not Buf/Str/Pkg - found type %s\n",
+					acpi_ut_get_type_name (temp_desc->common.type)));
 				status = AE_AML_OPERAND_TYPE;
 				goto cleanup;
 			}
@@ -715,75 +704,93 @@
 		break;
 
 
-	case AML_DEREF_OF_OP:           /* Deref_of (Obj_reference) */
+	case AML_DEREF_OF_OP:           /* Deref_of (Obj_reference | String) */
 
-		/* Check for a method local or argument */
+		/* Check for a method local or argument, or standalone String */
 
-		if (!VALID_DESCRIPTOR_TYPE (operand[0], ACPI_DESC_TYPE_NAMED)) {
-			/*
-			 * Must resolve/dereference the local/arg reference first
-			 */
-			switch (operand[0]->reference.opcode) {
-			/* Set Operand[0] to the value of the local/arg */
+		if (ACPI_GET_DESCRIPTOR_TYPE (operand[0]) != ACPI_DESC_TYPE_NAMED) {
+			switch (ACPI_GET_OBJECT_TYPE (operand[0])) {
+			case INTERNAL_TYPE_REFERENCE:
+				/*
+				 * This is a Deref_of (Local_x | Arg_x)
+				 *
+				 * Must resolve/dereference the local/arg reference first
+				 */
+				switch (operand[0]->reference.opcode) {
+				case AML_LOCAL_OP:
+				case AML_ARG_OP:
 
-			case AML_LOCAL_OP:
-			case AML_ARG_OP:
+					/* Set Operand[0] to the value of the local/arg */
 
-				acpi_ds_method_data_get_value (operand[0]->reference.opcode,
-						operand[0]->reference.offset, walk_state, &temp_desc);
+					acpi_ds_method_data_get_value (operand[0]->reference.opcode,
+							operand[0]->reference.offset, walk_state, &temp_desc);
 
-				/*
-				 * Delete our reference to the input object and
-				 * point to the object just retrieved
-				 */
-				acpi_ut_remove_reference (operand[0]);
-				operand[0] = temp_desc;
-				break;
+					/*
+					 * Delete our reference to the input object and
+					 * point to the object just retrieved
+					 */
+					acpi_ut_remove_reference (operand[0]);
+					operand[0] = temp_desc;
+					break;
 
-			default:
+				default:
 
-				/* Index op - handled below */
+					/* Must be an Index op - handled below */
+					break;
+				}
 				break;
-			}
-		}
 
 
-		/* Operand[0] may have changed from the code above */
-
-		if (VALID_DESCRIPTOR_TYPE (operand[0], ACPI_DESC_TYPE_NAMED)) {
-			/* Get the actual object from the Node (This is the dereference) */
+			case ACPI_TYPE_STRING:
 
-			return_desc = ((acpi_namespace_node *) operand[0])->object;
+				/*
+				 * This is a Deref_of (String). The string is a reference to a named ACPI object.
+				 *
+				 * 1) Find the owning Node
+				 * 2) Dereference the node to an actual object.  Could be a Field, so we nee
+				 *    to resolve the node to a value.
+				 */
+				status = acpi_ns_get_node_by_path (operand[0]->string.pointer, walk_state->scope_info->scope.node,
+						  ACPI_NS_SEARCH_PARENT, (acpi_namespace_node **) &return_desc);
+				if (ACPI_FAILURE (status)) {
+					goto cleanup;
+				}
 
-			/* Returning a pointer to the object, add another reference! */
+				status = acpi_ex_resolve_node_to_value ((acpi_namespace_node **) &return_desc, walk_state);
+				goto cleanup;
 
-			acpi_ut_add_reference (return_desc);
-		}
 
-		else {
-			/*
-			 * This must be a reference object produced by the Index
-			 * ASL operation -- check internal opcode
-			 */
-			if ((operand[0]->reference.opcode != AML_INDEX_OP) &&
-				(operand[0]->reference.opcode != AML_REF_OF_OP)) {
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown opcode in ref(%p) - %X\n",
-					operand[0], operand[0]->reference.opcode));
+			default:
 
-				status = AE_TYPE;
+				status = AE_AML_OPERAND_TYPE;
 				goto cleanup;
 			}
+		}
 
+		/* Operand[0] may have changed from the code above */
 
+		if (ACPI_GET_DESCRIPTOR_TYPE (operand[0]) == ACPI_DESC_TYPE_NAMED) {
+			/*
+			 * This is a Deref_of (Object_reference)
+			 * Get the actual object from the Node (This is the dereference).
+			 * -- This case may only happen when a Local_x or Arg_x is dereferenced above.
+			 */
+			return_desc = acpi_ns_get_attached_object ((acpi_namespace_node *) operand[0]);
+		}
+		else {
+			/*
+			 * This must be a reference object produced by either the Index() or
+			 * Ref_of() operator
+			 */
 			switch (operand[0]->reference.opcode) {
 			case AML_INDEX_OP:
 
 				/*
-				 * Supported target types for the Index operator are
-				 * 1) A Buffer
-				 * 2) A Package
+				 * The target type for the Index operator must be
+				 * either a Buffer or a Package
 				 */
-				if (operand[0]->reference.target_type == ACPI_TYPE_BUFFER_FIELD) {
+				switch (operand[0]->reference.target_type) {
+				case ACPI_TYPE_BUFFER_FIELD:
 					/*
 					 * The target is a buffer, we must create a new object that
 					 * contains one element of the buffer, the element pointed
@@ -799,16 +806,19 @@
 						goto cleanup;
 					}
 
+					/*
+					 * Since we are returning the value of the buffer at the
+					 * indexed location, we don't need to add an additional
+					 * reference to the buffer itself.
+					 */
 					temp_desc = operand[0]->reference.object;
 					return_desc->integer.value =
 						temp_desc->buffer.pointer[operand[0]->reference.offset];
+					break;
 
-					/* TBD: [Investigate] (see below) Don't add an additional
-					 * ref!
-					 */
-				}
 
-				else if (operand[0]->reference.target_type == ACPI_TYPE_PACKAGE) {
+				case ACPI_TYPE_PACKAGE:
+
 					/*
 					 * The target is a package, we want to return the referenced
 					 * element of the package.  We must add another reference to
@@ -821,7 +831,6 @@
 						 * an uninitialized package element and is thus a
 						 * severe error.
 						 */
-
 						ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "NULL package element obj %p\n",
 							operand[0]));
 						status = AE_AML_UNINITIALIZED_ELEMENT;
@@ -829,15 +838,16 @@
 					}
 
 					acpi_ut_add_reference (return_desc);
-				}
+					break;
+
+
+				default:
 
-				else {
-					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown Target_type %X in obj %p\n",
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown Index Target_type %X in obj %p\n",
 						operand[0]->reference.target_type, operand[0]));
 					status = AE_AML_OPERAND_TYPE;
 					goto cleanup;
 				}
-
 				break;
 
 
@@ -849,15 +859,22 @@
 
 				acpi_ut_add_reference (return_desc);
 				break;
+
+
+			default:
+				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown opcode in ref(%p) - %X\n",
+					operand[0], operand[0]->reference.opcode));
+
+				status = AE_TYPE;
+				goto cleanup;
 			}
 		}
-
 		break;
 
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_1A_0T_1R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_1A_0T_1R: Unknown opcode %X\n",
 			walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
diff -Nru a/drivers/acpi/executer/exoparg2.c b/drivers/acpi/executer/exoparg2.c
--- a/drivers/acpi/executer/exoparg2.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/executer/exoparg2.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: exoparg2 - AML execution - opcodes with 2 arguments
- *              $Revision: 97 $
+ *              $Revision: 104 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exoparg2")
+	 ACPI_MODULE_NAME    ("exoparg2")
 
 
 /*!
@@ -84,7 +84,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_2A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_2A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	/* Examine the opcode */
@@ -97,37 +97,36 @@
 
 		node = (acpi_namespace_node *) operand[0];
 
-		/* The node must refer to a device or thermal zone */
+		/* The node must refer to a device or thermal zone or processor */
 
-		if (node && operand[1])     /* TBD: is this check necessary? */ {
-			switch (node->type) {
-			case ACPI_TYPE_DEVICE:
-			case ACPI_TYPE_THERMAL:
+		switch (node->type) {
+		case ACPI_TYPE_DEVICE:
+		case ACPI_TYPE_THERMAL:
+		case ACPI_TYPE_PROCESSOR:
 
-				/*
-				 * Dispatch the notify to the appropriate handler
-				 * NOTE: the request is queued for execution after this method
-				 * completes.  The notify handlers are NOT invoked synchronously
-				 * from this thread -- because handlers may in turn run other
-				 * control methods.
-				 */
-				status = acpi_ev_queue_notify_request (node,
-						 (u32) operand[1]->integer.value);
-				break;
-
-			default:
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unexpected notify object type %X\n",
-					node->type));
+			/*
+			 * Dispatch the notify to the appropriate handler
+			 * NOTE: the request is queued for execution after this method
+			 * completes.  The notify handlers are NOT invoked synchronously
+			 * from this thread -- because handlers may in turn run other
+			 * control methods.
+			 */
+			status = acpi_ev_queue_notify_request (node,
+					 (u32) operand[1]->integer.value);
+			break;
 
-				status = AE_AML_OPERAND_TYPE;
-				break;
-			}
+		default:
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unexpected notify object type %X\n",
+				node->type));
+
+			status = AE_AML_OPERAND_TYPE;
+			break;
 		}
 		break;
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_2A_0T_0R: Unknown opcode %X\n", walk_state->opcode));
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_2A_0T_0R: Unknown opcode %X\n", walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 	}
 
@@ -158,7 +157,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_2A_2T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_2A_2T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	/*
@@ -191,11 +190,10 @@
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_2A_2T_1R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_2A_2T_1R: Unknown opcode %X\n",
 				walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
-		break;
 	}
 
 
@@ -257,7 +255,7 @@
 	acpi_status             status      = AE_OK;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_2A_1T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_2A_1T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	/*
@@ -344,7 +342,7 @@
 
 	case AML_CONCAT_RES_OP:         /* Concatenate_res_template (Buffer, Buffer, Result) (ACPI 2.0) */
 
-		status = AE_NOT_IMPLEMENTED;
+		status = acpi_ex_concat_template (operand[0], operand[1], &return_desc, walk_state);
 		break;
 
 
@@ -424,12 +422,11 @@
 
 		walk_state->result_obj = return_desc;
 		goto cleanup;
-		break;
 
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_2A_1T_1R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_2A_1T_1R: Unknown opcode %X\n",
 				walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		break;
@@ -486,7 +483,7 @@
 	u8                      logical_result = FALSE;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_2A_0T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_2A_0T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	/* Create the internal return object */
@@ -531,10 +528,9 @@
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_2A_0T_1R: Unknown opcode %X\n", walk_state->opcode));
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_2A_0T_1R: Unknown opcode %X\n", walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
-		break;
 	}
 
 
diff -Nru a/drivers/acpi/executer/exoparg3.c b/drivers/acpi/executer/exoparg3.c
--- a/drivers/acpi/executer/exoparg3.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exoparg3.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exoparg3 - AML execution - opcodes with 3 arguments
- *              $Revision: 3 $
+ *              $Revision: 9 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exoparg3")
+	 ACPI_MODULE_NAME    ("exoparg3")
 
 
 /*!
@@ -79,7 +79,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_3A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_3A_0T_0R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	switch (walk_state->opcode) {
@@ -112,11 +112,10 @@
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_3A_0T_0R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_3A_0T_0R: Unknown opcode %X\n",
 				walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
-		break;
 	}
 
 
@@ -150,7 +149,7 @@
 	u32                     length;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_3A_1T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_3A_1T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	switch (walk_state->opcode) {
@@ -188,30 +187,29 @@
 
 			buffer = ACPI_MEM_CALLOCATE (length + 1);
 			if (!buffer) {
-				return (AE_NO_MEMORY);
+				status = AE_NO_MEMORY;
+				goto cleanup;
 			}
 
 			/* Copy the portion requested */
 
-			MEMCPY (buffer, operand[0]->string.pointer + index,
-					length);
+			ACPI_MEMCPY (buffer, operand[0]->string.pointer + index,
+					  length);
 
 			/* Set the length of the new String/Buffer */
 
 			return_desc->string.pointer = buffer;
 			return_desc->string.length = length;
 		}
-
 		break;
 
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_3A_0T_0R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_3A_0T_0R: Unknown opcode %X\n",
 				walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
-		break;
 	}
 
 	/* Store the result in the target */
diff -Nru a/drivers/acpi/executer/exoparg6.c b/drivers/acpi/executer/exoparg6.c
--- a/drivers/acpi/executer/exoparg6.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exoparg6.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exoparg6 - AML execution - opcodes with 6 arguments
- *              $Revision: 4 $
+ *              $Revision: 10 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exoparg6")
+	 ACPI_MODULE_NAME    ("exoparg6")
 
 
 /*!
@@ -158,7 +158,7 @@
 	acpi_operand_object     *this_element;
 
 
-	FUNCTION_TRACE_STR ("Ex_opcode_6A_0T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
+	ACPI_FUNCTION_TRACE_STR ("Ex_opcode_6A_0T_1R", acpi_ps_get_opcode_name (walk_state->opcode));
 
 
 	switch (walk_state->opcode) {
@@ -199,6 +199,7 @@
 		 * Examine each element until a match is found.  Within the loop,
 		 * "continue" signifies that the current element does not match
 		 * and the next should be examined.
+		 *
 		 * Upon finding a match, the loop will terminate via "break" at
 		 * the bottom.  If it terminates "normally", Match_value will be -1
 		 * (its initial value) indicating that no match was found.  When
@@ -209,27 +210,21 @@
 
 			/*
 			 * Treat any NULL or non-numeric elements as non-matching.
-			 * TBD [Unhandled] - if an element is a Name,
-			 *      should we examine its value?
 			 */
 			if (!this_element ||
 				this_element->common.type != ACPI_TYPE_INTEGER) {
 				continue;
 			}
 
-
 			/*
-			 * Within these switch statements:
-			 *      "break" (exit from the switch) signifies a match;
-			 *      "continue" (proceed to next iteration of enclosing
-			 *          "for" loop) signifies a non-match.
+			 * "continue" (proceed to next iteration of enclosing
+			 * "for" loop) signifies a non-match.
 			 */
 			if (!acpi_ex_do_match ((u32) operand[1]->integer.value,
 					   this_element->integer.value, operand[2]->integer.value)) {
 				continue;
 			}
 
-
 			if (!acpi_ex_do_match ((u32) operand[3]->integer.value,
 					   this_element->integer.value, operand[4]->integer.value)) {
 				continue;
@@ -246,18 +241,16 @@
 
 	case AML_LOAD_TABLE_OP:
 
-		status = AE_NOT_IMPLEMENTED;
-		goto cleanup;
+		status = acpi_ex_load_table_op (walk_state, &return_desc);
 		break;
 
 
 	default:
 
-		REPORT_ERROR (("Acpi_ex_opcode_3A_0T_0R: Unknown opcode %X\n",
+		ACPI_REPORT_ERROR (("Acpi_ex_opcode_3A_0T_0R: Unknown opcode %X\n",
 				walk_state->opcode));
 		status = AE_AML_BAD_OPCODE;
 		goto cleanup;
-		break;
 	}
 
 
diff -Nru a/drivers/acpi/executer/exprep.c b/drivers/acpi/executer/exprep.c
--- a/drivers/acpi/executer/exprep.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exprep.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exprep - ACPI AML (p-code) execution - field prep utilities
- *              $Revision: 99 $
+ *              $Revision: 114 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,74 +33,102 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exprep")
+	 ACPI_MODULE_NAME    ("exprep")
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_decode_field_access_type
+ * FUNCTION:    Acpi_ex_decode_field_access
  *
  * PARAMETERS:  Access          - Encoded field access bits
  *              Length          - Field length.
  *
- * RETURN:      Field granularity (8, 16, 32 or 64)
+ * RETURN:      Field granularity (8, 16, 32 or 64) and
+ *              Byte_alignment (1, 2, 3, or 4)
  *
  * DESCRIPTION: Decode the Access_type bits of a field definition.
  *
  ******************************************************************************/
 
 static u32
-acpi_ex_decode_field_access_type (
-	u32                     access,
-	u16                     length,
-	u32                     *alignment)
+acpi_ex_decode_field_access (
+	acpi_operand_object     *obj_desc,
+	u8                      field_flags,
+	u32                     *return_byte_alignment)
 {
-	PROC_NAME ("Ex_decode_field_access_type");
+	u32                     access;
+	u32                     length;
+	u8                      byte_alignment;
+	u8                      bit_length;
+
+
+	ACPI_FUNCTION_NAME ("Ex_decode_field_access");
+
 
+	access = (field_flags & AML_FIELD_ACCESS_TYPE_MASK);
+	length = obj_desc->common_field.bit_length;
 
 	switch (access) {
-	case ACCESS_ANY_ACC:
+	case AML_FIELD_ACCESS_ANY:
 
-		*alignment = 8;
+		byte_alignment = 1;
+		bit_length = 8;
+
+#if 0
+		/*
+		 * TBD: optimize
+		 *
+		 * Any attempt to optimize the access size to the size of the field
+		 * must take into consideration the length of the region and take
+		 * care that an access to the field will not attempt to access
+		 * beyond the end of the region.
+		 */
 
 		/* Use the length to set the access type */
 
 		if (length <= 8) {
-			return (8);
+			bit_length = 8;
 		}
 		else if (length <= 16) {
-			return (16);
+			bit_length = 16;
 		}
 		else if (length <= 32) {
-			return (32);
+			bit_length = 32;
 		}
 		else if (length <= 64) {
-			return (64);
+			bit_length = 64;
 		}
+		else {
+			/* Larger than Qword - just use byte-size chunks */
 
-		/* Default is 8 (byte) */
+			bit_length = 8;
+		}
+#endif
+		break;
 
-		return (8);
+	case AML_FIELD_ACCESS_BYTE:
+		byte_alignment = 1;
+		bit_length = 8;
 		break;
 
-	case ACCESS_BYTE_ACC:
-		*alignment = 8;
-		return (8);
+	case AML_FIELD_ACCESS_WORD:
+		byte_alignment = 2;
+		bit_length = 16;
 		break;
 
-	case ACCESS_WORD_ACC:
-		*alignment = 16;
-		return (16);
+	case AML_FIELD_ACCESS_DWORD:
+		byte_alignment = 4;
+		bit_length = 32;
 		break;
 
-	case ACCESS_DWORD_ACC:
-		*alignment = 32;
-		return (32);
+	case AML_FIELD_ACCESS_QWORD:  /* ACPI 2.0 */
+		byte_alignment = 8;
+		bit_length = 64;
 		break;
 
-	case ACCESS_QWORD_ACC:  /* ACPI 2.0 */
-		*alignment = 64;
-		return (64);
+	case AML_FIELD_ACCESS_BUFFER:  /* ACPI 2.0 */
+		byte_alignment = 8;
+		bit_length = 8;
 		break;
 
 	default:
@@ -111,6 +139,18 @@
 			access));
 		return (0);
 	}
+
+	if (obj_desc->common.type == ACPI_TYPE_BUFFER_FIELD) {
+		/*
+		 * Buffer_field access can be on any byte boundary, so the
+		 * Byte_alignment is always 1 byte -- regardless of any Byte_alignment
+		 * implied by the field access type.
+		 */
+		byte_alignment = 1;
+	}
+
+	*return_byte_alignment = byte_alignment;
+	return (bit_length);
 }
 
 
@@ -128,7 +168,9 @@
  * RETURN:      Status
  *
  * DESCRIPTION: Initialize the areas of the field object that are common
- *              to the various types of fields.
+ *              to the various types of fields.  Note: This is very "sensitive"
+ *              code because we are solving the general case for field
+ *              alignment.
  *
  ******************************************************************************/
 
@@ -136,107 +178,90 @@
 acpi_ex_prep_common_field_object (
 	acpi_operand_object     *obj_desc,
 	u8                      field_flags,
+	u8                      field_attribute,
 	u32                     field_bit_position,
 	u32                     field_bit_length)
 {
 	u32                     access_bit_width;
-	u32                     alignment;
+	u32                     byte_alignment;
 	u32                     nearest_byte_address;
 
 
-	FUNCTION_TRACE ("Ex_prep_common_field_object");
+	ACPI_FUNCTION_TRACE ("Ex_prep_common_field_object");
 
 
 	/*
 	 * Note: the structure being initialized is the
-	 * ACPI_COMMON_FIELD_INFO;  No structure fields outside of the common area
-	 * are initialized by this procedure.
+	 * ACPI_COMMON_FIELD_INFO;  No structure fields outside of the common
+	 * area are initialized by this procedure.
 	 */
-
-	/* Demultiplex the Field_flags byte */
-
-	obj_desc->common_field.lock_rule = (u8) ((field_flags & LOCK_RULE_MASK)
-			 >> LOCK_RULE_SHIFT);
-	obj_desc->common_field.update_rule = (u8) ((field_flags & UPDATE_RULE_MASK)
-			 >> UPDATE_RULE_SHIFT);
-	/* Other misc fields */
-
-	obj_desc->common_field.bit_length = (u16) field_bit_length;
+	obj_desc->common_field.field_flags = field_flags;
+	obj_desc->common_field.attribute = field_attribute;
+	obj_desc->common_field.bit_length = field_bit_length;
 
 	/*
 	 * Decode the access type so we can compute offsets.  The access type gives
 	 * two pieces of information - the width of each field access and the
-	 * necessary alignment of the access.  For Any_acc, the width used is the
-	 * largest necessary/possible in an attempt to access the whole field in one
-	 * I/O operation.  However, for Any_acc, the alignment is 8. For all other
-	 * access types (Byte, Word, Dword, Qword), the width is the same as the
-	 * alignment.
+	 * necessary Byte_alignment (address granularity) of the access.
+	 *
+	 * For Any_acc, the Access_bit_width is the largest width that is both necessary
+	 * and possible in an attempt to access the whole field in one
+	 * I/O operation.  However, for Any_acc, the Byte_alignment is always one byte.
+	 *
+	 * For all Buffer Fields, the Byte_alignment is always one byte.
+	 *
+	 * For all other access types (Byte, Word, Dword, Qword), the Bitwidth is the
+	 * same (equivalent) as the Byte_alignment.
 	 */
-	access_bit_width = acpi_ex_decode_field_access_type (
-			   ((field_flags & ACCESS_TYPE_MASK) >> ACCESS_TYPE_SHIFT),
-			   obj_desc->field.bit_length, &alignment);
+	access_bit_width = acpi_ex_decode_field_access (obj_desc, field_flags, &byte_alignment);
 	if (!access_bit_width) {
 		return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
 	}
 
 	/* Setup width (access granularity) fields */
 
-	obj_desc->common_field.access_bit_width = (u8) access_bit_width;         /* 8, 16, 32, 64 */
-	obj_desc->common_field.access_byte_width = (u8) DIV_8 (access_bit_width); /* 1, 2,  4,  8 */
-
-	if (obj_desc->common.type == ACPI_TYPE_BUFFER_FIELD) {
-		/*
-		 * Buffer_field access can be on any byte boundary, so the
-		 * alignment is always 8 (regardless of any alignment implied by the
-		 * field access type.)
-		 */
-		alignment = 8;
-	}
-
+	obj_desc->common_field.access_byte_width = (u8) ACPI_DIV_8 (access_bit_width); /* 1, 2, 4,  8 */
 
 	/*
 	 * Base_byte_offset is the address of the start of the field within the region. It is
 	 * the byte address of the first *datum* (field-width data unit) of the field.
 	 * (i.e., the first datum that contains at least the first *bit* of the field.)
+	 * Note: Byte_alignment is always either equal to the Access_bit_width or 8 (Byte access),
+	 * and it defines the addressing granularity of the parent region or buffer.
 	 */
-	nearest_byte_address                      = ROUND_BITS_DOWN_TO_BYTES (field_bit_position);
-	obj_desc->common_field.base_byte_offset   = ROUND_DOWN (nearest_byte_address,
-			   DIV_8 (alignment));
+	nearest_byte_address                     = ACPI_ROUND_BITS_DOWN_TO_BYTES (field_bit_position);
+	obj_desc->common_field.base_byte_offset  = ACPI_ROUND_DOWN (nearest_byte_address, byte_alignment);
 
 	/*
 	 * Start_field_bit_offset is the offset of the first bit of the field within a field datum.
-	 * This is calculated as the number of bits from the Base_byte_offset. In other words,
-	 * the start of the field is relative to a byte address, regardless of the access type
-	 * of the field.
 	 */
-	obj_desc->common_field.start_field_bit_offset = (u8) (MOD_8 (field_bit_position));
-
-	/*
-	 * Datum_valid_bits is the number of valid field bits in the first field datum.
-	 */
-	obj_desc->common_field.datum_valid_bits   = (u8) (access_bit_width -
-			   obj_desc->common_field.start_field_bit_offset);
+	obj_desc->common_field.start_field_bit_offset = (u8) (field_bit_position -
+			  ACPI_MUL_8 (obj_desc->common_field.base_byte_offset));
 
 	/*
 	 * Valid bits -- the number of bits that compose a partial datum,
 	 * 1) At the end of the field within the region (arbitrary starting bit offset)
 	 * 2) At the end of a buffer used to contain the field (starting offset always zero)
 	 */
-	obj_desc->common_field.end_field_valid_bits = (u8) ((obj_desc->common_field.start_field_bit_offset +
-			   field_bit_length) % access_bit_width);
+	obj_desc->common_field.end_field_valid_bits = (u8) ((obj_desc->common_field.start_field_bit_offset + field_bit_length) %
+			   access_bit_width);
 	obj_desc->common_field.end_buffer_valid_bits = (u8) (field_bit_length % access_bit_width); /* Start_buffer_bit_offset always = 0 */
 
+	/*
+	 * Datum_valid_bits is the number of valid field bits in the first field datum.
+	 */
+	obj_desc->common_field.datum_valid_bits  = (u8) (access_bit_width -
+			  obj_desc->common_field.start_field_bit_offset);
 
 	/*
-	 * Does the entire field fit within a single field access element
-	 * (datum)?  (without crossing a datum boundary)
+	 * Does the entire field fit within a single field access element? (datum)
+	 * (i.e., without crossing a datum boundary)
 	 */
-	if ((obj_desc->common_field.start_field_bit_offset + obj_desc->common_field.bit_length) <=
-		(u16) obj_desc->common_field.access_bit_width) {
-		obj_desc->common_field.access_flags |= AFIELD_SINGLE_DATUM;
+	if ((obj_desc->common_field.start_field_bit_offset + field_bit_length) <=
+		(u16) access_bit_width) {
+		obj_desc->common.flags |= AOPOBJ_SINGLE_DATUM;
 	}
 
-
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -267,7 +292,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ex_prep_field_value");
+	ACPI_FUNCTION_TRACE ("Ex_prep_field_value");
 
 
 	/* Parameter validation */
@@ -280,14 +305,15 @@
 
 		type = acpi_ns_get_type (info->region_node);
 		if (type != ACPI_TYPE_REGION) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Needed Region, found type %X %s\n",
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Needed Region, found type %X %s\n",
 				type, acpi_ut_get_type_name (type)));
 
 			return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 		}
 	}
 
-	/* Allocate a new region object */
+	/* Allocate a new field object */
 
 	obj_desc = acpi_ut_create_internal_object (info->field_type);
 	if (!obj_desc) {
@@ -296,8 +322,9 @@
 
 	/* Initialize areas of the object that are common to all fields */
 
+	obj_desc->common_field.node = info->field_node;
 	status = acpi_ex_prep_common_field_object (obj_desc, info->field_flags,
-			  info->field_bit_position, info->field_bit_length);
+			 info->attribute, info->field_bit_position, info->field_bit_length);
 	if (ACPI_FAILURE (status)) {
 		acpi_ut_delete_object_desc (obj_desc);
 		return_ACPI_STATUS (status);
@@ -308,33 +335,34 @@
 	switch (info->field_type) {
 	case INTERNAL_TYPE_REGION_FIELD:
 
-		obj_desc->field.region_obj  = acpi_ns_get_attached_object (info->region_node);
+		obj_desc->field.region_obj   = acpi_ns_get_attached_object (info->region_node);
 
 		/* An additional reference for the container */
 
 		acpi_ut_add_reference (obj_desc->field.region_obj);
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Region_field: Bitoff=%X Off=%X Gran=%X Region %p\n",
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+			"Region_field: Bitoff=%X Off=%X Gran=%X Region %p\n",
 			obj_desc->field.start_field_bit_offset, obj_desc->field.base_byte_offset,
-			obj_desc->field.access_bit_width, obj_desc->field.region_obj));
+			obj_desc->field.access_byte_width, obj_desc->field.region_obj));
 		break;
 
 
 	case INTERNAL_TYPE_BANK_FIELD:
 
-		obj_desc->bank_field.value         = info->bank_value;
-		obj_desc->bank_field.region_obj    = acpi_ns_get_attached_object (info->region_node);
-		obj_desc->bank_field.bank_register_obj = acpi_ns_get_attached_object (info->register_node);
+		obj_desc->bank_field.value   = info->bank_value;
+		obj_desc->bank_field.region_obj = acpi_ns_get_attached_object (info->region_node);
+		obj_desc->bank_field.bank_obj = acpi_ns_get_attached_object (info->register_node);
 
 		/* An additional reference for the attached objects */
 
 		acpi_ut_add_reference (obj_desc->bank_field.region_obj);
-		acpi_ut_add_reference (obj_desc->bank_field.bank_register_obj);
+		acpi_ut_add_reference (obj_desc->bank_field.bank_obj);
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Bank Field: Bit_off=%X Off=%X Gran=%X Region %p Bank_reg %p\n",
 			obj_desc->bank_field.start_field_bit_offset, obj_desc->bank_field.base_byte_offset,
-			obj_desc->field.access_bit_width, obj_desc->bank_field.region_obj,
-			obj_desc->bank_field.bank_register_obj));
+			obj_desc->field.access_byte_width, obj_desc->bank_field.region_obj,
+			obj_desc->bank_field.bank_obj));
 		break;
 
 
@@ -343,7 +371,7 @@
 		obj_desc->index_field.index_obj = acpi_ns_get_attached_object (info->register_node);
 		obj_desc->index_field.data_obj = acpi_ns_get_attached_object (info->data_register_node);
 		obj_desc->index_field.value  = (u32) (info->field_bit_position /
-				  obj_desc->field.access_bit_width);
+				  ACPI_MUL_8 (obj_desc->field.access_byte_width));
 
 		if (!obj_desc->index_field.data_obj || !obj_desc->index_field.index_obj) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Null Index Object\n"));
@@ -357,7 +385,7 @@
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Index_field: bitoff=%X off=%X gran=%X Index %p Data %p\n",
 			obj_desc->index_field.start_field_bit_offset, obj_desc->index_field.base_byte_offset,
-			obj_desc->field.access_bit_width, obj_desc->index_field.index_obj,
+			obj_desc->field.access_byte_width, obj_desc->index_field.index_obj,
 			obj_desc->index_field.data_obj));
 		break;
 	}
@@ -367,10 +395,10 @@
 	 * preserving the current type of that Named_obj.
 	 */
 	status = acpi_ns_attach_object (info->field_node, obj_desc,
-			  (u8) acpi_ns_get_type (info->field_node));
+			  acpi_ns_get_type (info->field_node));
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "set Named_obj %p (%4.4s) val = %p\n",
-		info->field_node, (char*)&(info->field_node->name), obj_desc));
+			info->field_node, (char *) &(info->field_node->name), obj_desc));
 
 	/* Remove local reference to the object */
 
diff -Nru a/drivers/acpi/executer/exregion.c b/drivers/acpi/executer/exregion.c
--- a/drivers/acpi/executer/exregion.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exregion.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exregion - ACPI default Op_region (address space) handlers
- *              $Revision: 61 $
+ *              $Revision: 72 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exregion")
+	 ACPI_MODULE_NAME    ("exregion")
 
 
 /*******************************************************************************
@@ -60,7 +60,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context)
 {
@@ -68,9 +68,11 @@
 	void                    *logical_addr_ptr = NULL;
 	acpi_mem_space_context  *mem_info = region_context;
 	u32                     length;
+	u32                     window_size;
+	u32                     remaining;
 
 
-	FUNCTION_TRACE ("Ex_system_memory_space_handler");
+	ACPI_FUNCTION_TRACE ("Ex_system_memory_space_handler");
 
 
 	/* Validate and translate the bit width */
@@ -88,14 +90,16 @@
 		length = 4;
 		break;
 
+	case 64:
+		length = 8;
+		break;
+
 	default:
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid System_memory width %d\n",
 			bit_width));
 		return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
-		break;
 	}
 
-
 	/*
 	 * Does the request fit into the cached memory mapping?
 	 * Is 1) Address below the current mapping? OR
@@ -115,61 +119,70 @@
 					   mem_info->mapped_length);
 		}
 
-		mem_info->mapped_length = 0; /* In case of failure below */
+		/*
+		 * Don't attempt to map memory beyond the end of the region, and
+		 * constrain the maximum mapping size to something reasonable.
+		 */
+		remaining = (u32) ((mem_info->address + (ACPI_PHYSICAL_ADDRESS) mem_info->length) - address);
+		if (remaining > SYSMEM_REGION_WINDOW_SIZE) {
+			window_size = SYSMEM_REGION_WINDOW_SIZE;
+		}
+		else {
+			window_size = remaining;
+		}
 
 		/* Create a new mapping starting at the address given */
 
-		status = acpi_os_map_memory (address, SYSMEM_REGION_WINDOW_SIZE,
+		status = acpi_os_map_memory (address, window_size,
 				  (void **) &mem_info->mapped_logical_address);
 		if (ACPI_FAILURE (status)) {
+			mem_info->mapped_length = 0;
 			return_ACPI_STATUS (status);
 		}
 
 		/* Save the physical address and mapping size */
 
 		mem_info->mapped_physical_address = address;
-		mem_info->mapped_length = SYSMEM_REGION_WINDOW_SIZE;
+		mem_info->mapped_length = window_size;
 	}
 
-
 	/*
 	 * Generate a logical pointer corresponding to the address we want to
 	 * access
 	 */
-
-	/* TBD: should these pointers go to 64-bit in all cases ? */
-
 	logical_addr_ptr = mem_info->mapped_logical_address +
 			  ((acpi_integer) address - (acpi_integer) mem_info->mapped_physical_address);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 		"System_memory %d (%d width) Address=%8.8X%8.8X\n", function, bit_width,
-		HIDWORD (address), LODWORD (address)));
+		ACPI_HIDWORD (address), ACPI_LODWORD (address)));
 
    /* Perform the memory read or write */
 
 	switch (function) {
+	case ACPI_READ:
 
-	case ACPI_READ_ADR_SPACE:
-
+		*value = 0;
 		switch (bit_width) {
 		case 8:
 			*value = (u32)* (u8 *) logical_addr_ptr;
 			break;
 
 		case 16:
-			MOVE_UNALIGNED16_TO_32 (value, logical_addr_ptr);
+			ACPI_MOVE_UNALIGNED16_TO_16 (value, logical_addr_ptr);
 			break;
 
 		case 32:
-			MOVE_UNALIGNED32_TO_32 (value, logical_addr_ptr);
+			ACPI_MOVE_UNALIGNED32_TO_32 (value, logical_addr_ptr);
 			break;
-		}
 
+		case 64:
+			ACPI_MOVE_UNALIGNED64_TO_64 (value, logical_addr_ptr);
+			break;
+		}
 		break;
 
-
-	case ACPI_WRITE_ADR_SPACE:
+	case ACPI_WRITE:
 
 		switch (bit_width) {
 		case 8:
@@ -177,17 +190,19 @@
 			break;
 
 		case 16:
-			MOVE_UNALIGNED16_TO_16 (logical_addr_ptr, value);
+			ACPI_MOVE_UNALIGNED16_TO_16 (logical_addr_ptr, value);
 			break;
 
 		case 32:
-			MOVE_UNALIGNED32_TO_32 (logical_addr_ptr, value);
+			ACPI_MOVE_UNALIGNED32_TO_32 (logical_addr_ptr, value);
 			break;
-		}
 
+		case 64:
+			ACPI_MOVE_UNALIGNED64_TO_64 (logical_addr_ptr, value);
+			break;
+		}
 		break;
 
-
 	default:
 		status = AE_BAD_PARAMETER;
 		break;
@@ -220,37 +235,34 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context)
 {
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_system_io_space_handler");
+	ACPI_FUNCTION_TRACE ("Ex_system_io_space_handler");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 		"System_iO %d (%d width) Address=%8.8X%8.8X\n", function, bit_width,
-		HIDWORD (address), LODWORD (address)));
+		ACPI_HIDWORD (address), ACPI_LODWORD (address)));
 
 	/* Decode the function parameter */
 
 	switch (function) {
-
-	case ACPI_READ_ADR_SPACE:
+	case ACPI_READ:
 
 		*value = 0;
 		status = acpi_os_read_port ((ACPI_IO_ADDRESS) address, value, bit_width);
 		break;
 
-
-	case ACPI_WRITE_ADR_SPACE:
+	case ACPI_WRITE:
 
 		status = acpi_os_write_port ((ACPI_IO_ADDRESS) address, *value, bit_width);
 		break;
 
-
 	default:
 		status = AE_BAD_PARAMETER;
 		break;
@@ -283,7 +295,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context)
 {
@@ -292,11 +304,11 @@
 	u16                     pci_register;
 
 
-	FUNCTION_TRACE ("Ex_pci_config_space_handler");
+	ACPI_FUNCTION_TRACE ("Ex_pci_config_space_handler");
 
 
 	/*
-	 *  The arguments to Acpi_os(Read|Write)Pci_cfg(Byte|Word|Dword) are:
+	 *  The arguments to Acpi_os(Read|Write)Pci_configuration are:
 	 *
 	 *  Pci_segment is the PCI bus segment range 0-31
 	 *  Pci_bus     is the PCI bus number range 0-255
@@ -308,7 +320,7 @@
 	 *
 	 */
 	pci_id      = (acpi_pci_id *) region_context;
-	pci_register = (u16) address;
+	pci_register = (u16) (ACPI_SIZE) address;
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 		"Pci_config %d (%d) Seg(%04x) Bus(%04x) Dev(%04x) Func(%04x) Reg(%04x)\n",
@@ -316,20 +328,17 @@
 		pci_id->function, pci_register));
 
 	switch (function) {
-
-	case ACPI_READ_ADR_SPACE:
+	case ACPI_READ:
 
 		*value = 0;
 		status = acpi_os_read_pci_configuration (pci_id, pci_register, value, bit_width);
 		break;
 
-
-	case ACPI_WRITE_ADR_SPACE:
+	case ACPI_WRITE:
 
 		status = acpi_os_write_pci_configuration (pci_id, pci_register, *value, bit_width);
 		break;
 
-
 	default:
 
 		status = AE_BAD_PARAMETER;
@@ -363,14 +372,14 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context)
 {
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_cmos_space_handler");
+	ACPI_FUNCTION_TRACE ("Ex_cmos_space_handler");
 
 
 	return_ACPI_STATUS (status);
@@ -400,16 +409,75 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
+	void                    *handler_context,
+	void                    *region_context)
+{
+	acpi_status             status = AE_OK;
+
+
+	ACPI_FUNCTION_TRACE ("Ex_pci_bar_space_handler");
+
+
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ex_data_table_space_handler
+ *
+ * PARAMETERS:  Function            - Read or Write operation
+ *              Address             - Where in the space to read or write
+ *              Bit_width           - Field width in bits (8, 16, or 32)
+ *              Value               - Pointer to in or out value
+ *              Handler_context     - Pointer to Handler's context
+ *              Region_context      - Pointer to context specific to the
+ *                                    accessed region
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Handler for the Data Table address space (Op Region)
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ex_data_table_space_handler (
+	u32                     function,
+	ACPI_PHYSICAL_ADDRESS   address,
+	u32                     bit_width,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context)
 {
 	acpi_status             status = AE_OK;
+	u32                     byte_width = ACPI_DIV_8 (bit_width);
+	u32                     i;
+	char                    *logical_addr_ptr;
+
+
+	ACPI_FUNCTION_TRACE ("Ex_data_table_space_handler");
+
+
+	logical_addr_ptr = ACPI_PHYSADDR_TO_PTR (address);
 
 
-	FUNCTION_TRACE ("Ex_pci_bar_space_handler");
+   /* Perform the memory read or write */
+
+	switch (function) {
+	case ACPI_READ:
 
+		for (i = 0; i < byte_width; i++) {
+			((char *) value) [i] = logical_addr_ptr[i];
+		}
+		break;
+
+	case ACPI_WRITE:
+
+		return_ACPI_STATUS (AE_SUPPORT);
+	}
 
 	return_ACPI_STATUS (status);
 }
+
 
diff -Nru a/drivers/acpi/executer/exresnte.c b/drivers/acpi/executer/exresnte.c
--- a/drivers/acpi/executer/exresnte.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exresnte.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exresnte - AML Interpreter object resolution
- *              $Revision: 43 $
+ *              $Revision: 50 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -36,7 +36,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exresnte")
+	 ACPI_MODULE_NAME    ("exresnte")
 
 
 /*******************************************************************************
@@ -75,25 +75,24 @@
 	acpi_operand_object     *source_desc;
 	acpi_operand_object     *obj_desc = NULL;
 	acpi_namespace_node     *node;
-	acpi_object_type8       entry_type;
+	acpi_object_type        entry_type;
 	acpi_integer            temp_val;
 
 
-	FUNCTION_TRACE ("Ex_resolve_node_to_value");
+	ACPI_FUNCTION_TRACE ("Ex_resolve_node_to_value");
 
 
 	/*
 	 * The stack pointer points to a acpi_namespace_node (Node).  Get the
 	 * object that is attached to the Node.
 	 */
-	node      = *object_ptr;
-	source_desc  = acpi_ns_get_attached_object (node);
+	node       = *object_ptr;
+	source_desc = acpi_ns_get_attached_object (node);
 	entry_type = acpi_ns_get_type ((acpi_handle) node);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Entry=%p Source_desc=%p Type=%X\n",
 		 node, source_desc, entry_type));
 
-
 	/*
 	 * Several object types require no further processing:
 	 * 1) Devices rarely have an attached object, return the Node
@@ -115,7 +114,6 @@
 	 * of the attached object or pointer
 	 */
 	switch (entry_type) {
-
 	case ACPI_TYPE_PACKAGE:
 
 		if (ACPI_TYPE_PACKAGE != source_desc->common.type) {
@@ -187,7 +185,6 @@
 		status = acpi_ex_read_data_from_field (source_desc, &obj_desc);
 		break;
 
-
 	/*
 	 * For these objects, just return the object attached to the Node
 	 */
@@ -214,7 +211,6 @@
 			node));
 
 		return_ACPI_STATUS (AE_AML_OPERAND_TYPE);  /* Cannot be AE_TYPE */
-		break;
 
 
 	/*
diff -Nru a/drivers/acpi/executer/exresolv.c b/drivers/acpi/executer/exresolv.c
--- a/drivers/acpi/executer/exresolv.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exresolv.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exresolv - AML Interpreter object resolution
- *              $Revision: 101 $
+ *              $Revision: 106 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -36,112 +36,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exresolv")
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_get_buffer_field_value
- *
- * PARAMETERS:  *Obj_desc           - Pointer to a Buffer_field
- *              *Result_desc        - Pointer to an empty descriptor which will
- *                                    become an Integer with the field's value
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Retrieve the value from a Buffer_field
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_get_buffer_field_value (
-	acpi_operand_object     *obj_desc,
-	acpi_operand_object     *result_desc)
-{
-	acpi_status             status;
-	u32                     mask;
-	u8                      *location;
-
-
-	FUNCTION_TRACE ("Ex_get_buffer_field_value");
-
-
-	/*
-	 * Parameter validation
-	 */
-	if (!obj_desc) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - null field pointer\n"));
-		return_ACPI_STATUS (AE_AML_NO_OPERAND);
-	}
-
-	if (!(obj_desc->common.flags & AOPOBJ_DATA_VALID)) {
-		status = acpi_ds_get_buffer_field_arguments (obj_desc);
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
-		}
-	}
-
-	if (!obj_desc->buffer_field.buffer_obj) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - null container pointer\n"));
-		return_ACPI_STATUS (AE_AML_INTERNAL);
-	}
-
-	if (ACPI_TYPE_BUFFER != obj_desc->buffer_field.buffer_obj->common.type) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - container is not a Buffer\n"));
-		return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
-	}
-
-	if (!result_desc) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - null result pointer\n"));
-		return_ACPI_STATUS (AE_AML_INTERNAL);
-	}
-
-
-	/* Field location is (base of buffer) + (byte offset) */
-
-	location = obj_desc->buffer_field.buffer_obj->buffer.pointer
-			 + obj_desc->buffer_field.base_byte_offset;
-
-	/*
-	 * Construct Mask with as many 1 bits as the field width
-	 *
-	 * NOTE: Only the bottom 5 bits are valid for a shift operation, so
-	 *  special care must be taken for any shift greater than 31 bits.
-	 *
-	 * TBD: [Unhandled] Fields greater than 32 bits will not work.
-	 */
-	if (obj_desc->buffer_field.bit_length < 32) {
-		mask = ((u32) 1 << obj_desc->buffer_field.bit_length) - (u32) 1;
-	}
-	else {
-		mask = ACPI_UINT32_MAX;
-	}
-
-	result_desc->integer.type = (u8) ACPI_TYPE_INTEGER;
-
-	/* Get the 32 bit value at the location */
-
-	MOVE_UNALIGNED32_TO_32 (&result_desc->integer.value, location);
-
-	/*
-	 * Shift the 32-bit word containing the field, and mask off the
-	 * resulting value
-	 */
-	result_desc->integer.value =
-		(result_desc->integer.value >> obj_desc->buffer_field.start_field_bit_offset) & mask;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-		"** Read from buffer %p byte %d bit %d width %d addr %p mask %08X val %8.8X%8.8X\n",
-		obj_desc->buffer_field.buffer_obj->buffer.pointer,
-		obj_desc->buffer_field.base_byte_offset,
-		obj_desc->buffer_field.start_field_bit_offset,
-		obj_desc->buffer_field.bit_length,
-		location, mask,
-		HIDWORD(result_desc->integer.value),
-		LODWORD(result_desc->integer.value)));
-
-	return_ACPI_STATUS (AE_OK);
-}
+	 ACPI_MODULE_NAME    ("exresolv")
 
 
 /*******************************************************************************
@@ -167,7 +62,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ex_resolve_to_value", stack_ptr);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_resolve_to_value", stack_ptr);
 
 
 	if (!stack_ptr || !*stack_ptr) {
@@ -175,13 +70,12 @@
 		return_ACPI_STATUS (AE_AML_NO_OPERAND);
 	}
 
-
 	/*
 	 * The entity pointed to by the Stack_ptr can be either
 	 * 1) A valid acpi_operand_object, or
 	 * 2) A acpi_namespace_node (Named_obj)
 	 */
-	if (VALID_DESCRIPTOR_TYPE (*stack_ptr, ACPI_DESC_TYPE_INTERNAL)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (*stack_ptr) == ACPI_DESC_TYPE_INTERNAL) {
 		status = acpi_ex_resolve_object_to_value (stack_ptr, walk_state);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
@@ -192,7 +86,7 @@
 	 * Object on the stack may have changed if Acpi_ex_resolve_object_to_value()
 	 * was called (i.e., we can't use an _else_ here.)
 	 */
-	if (VALID_DESCRIPTOR_TYPE (*stack_ptr, ACPI_DESC_TYPE_NAMED)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (*stack_ptr) == ACPI_DESC_TYPE_NAMED) {
 		status = acpi_ex_resolve_node_to_value ((acpi_namespace_node **) stack_ptr,
 				  walk_state);
 		if (ACPI_FAILURE (status)) {
@@ -200,7 +94,6 @@
 		}
 	}
 
-
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Resolved object %p\n", *stack_ptr));
 	return_ACPI_STATUS (AE_OK);
 }
@@ -233,7 +126,7 @@
 	u16                     opcode;
 
 
-	FUNCTION_TRACE ("Ex_resolve_object_to_value");
+	ACPI_FUNCTION_TRACE ("Ex_resolve_object_to_value");
 
 
 	stack_desc = *stack_ptr;
@@ -241,13 +134,11 @@
 	/* This is an acpi_operand_object  */
 
 	switch (stack_desc->common.type) {
-
 	case INTERNAL_TYPE_REFERENCE:
 
 		opcode = stack_desc->reference.opcode;
 
 		switch (opcode) {
-
 		case AML_NAME_OP:
 
 			/*
@@ -290,7 +181,6 @@
 				stack_desc->reference.offset, obj_desc));
 			break;
 
-
 		/*
 		 * For constants, we must change the reference/constant object
 		 * to a real integer object
@@ -359,7 +249,6 @@
 					acpi_ut_add_reference (obj_desc);
 					*stack_ptr = obj_desc;
 				}
-
 				else {
 					/*
 					 * A NULL object descriptor means an unitialized element of
@@ -381,7 +270,6 @@
 				status = AE_AML_INTERNAL;
 				break;
 			}
-
 			break;
 
 
@@ -402,51 +290,24 @@
 
 		break; /* case INTERNAL_TYPE_REFERENCE */
 
-
+	/*
+	 * These cases may never happen here, but just in case..
+	 */
 	case ACPI_TYPE_BUFFER_FIELD:
-
-		obj_desc = acpi_ut_create_internal_object (ACPI_TYPE_ANY);
-		if (!obj_desc) {
-			return_ACPI_STATUS (AE_NO_MEMORY);
-		}
-
-		status = acpi_ex_get_buffer_field_value (stack_desc, obj_desc);
-		if (ACPI_FAILURE (status)) {
-			acpi_ut_remove_reference (obj_desc);
-			obj_desc = NULL;
-		}
-
-		*stack_ptr = (void *) obj_desc;
-		break;
-
-
+	case INTERNAL_TYPE_REGION_FIELD:
 	case INTERNAL_TYPE_BANK_FIELD:
+	case INTERNAL_TYPE_INDEX_FIELD:
 
-		obj_desc = acpi_ut_create_internal_object (ACPI_TYPE_ANY);
-		if (!obj_desc) {
-			return_ACPI_STATUS (AE_NO_MEMORY);
-		}
-
-		/* TBD: WRONG! */
-
-		status = acpi_ex_get_buffer_field_value (stack_desc, obj_desc);
-		if (ACPI_FAILURE (status)) {
-			acpi_ut_remove_reference (obj_desc);
-			obj_desc = NULL;
-		}
+		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Field_read Source_desc=%p Type=%X\n",
+			stack_desc, stack_desc->common.type));
 
+		status = acpi_ex_read_data_from_field (stack_desc, &obj_desc);
 		*stack_ptr = (void *) obj_desc;
 		break;
 
-
-	/* TBD: [Future] - may need to handle Index_field, and Def_field someday */
-
 	default:
-
 		break;
-
-	}   /* switch (Stack_desc->Common.Type) */
-
+	}
 
 	return_ACPI_STATUS (status);
 }
diff -Nru a/drivers/acpi/executer/exresop.c b/drivers/acpi/executer/exresop.c
--- a/drivers/acpi/executer/exresop.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/executer/exresop.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exresop - AML Interpreter operand/object resolution
- *              $Revision: 41 $
+ *              $Revision: 47 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -36,7 +36,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exresop")
+	 ACPI_MODULE_NAME    ("exresop")
 
 
 /*******************************************************************************
@@ -59,7 +59,7 @@
 	acpi_object_type        this_type,
 	void                    *object)
 {
-	PROC_NAME ("Ex_check_object_type");
+	ACPI_FUNCTION_NAME ("Ex_check_object_type");
 
 
 	if (type_needed == ACPI_TYPE_ANY) {
@@ -85,18 +85,21 @@
  *
  * FUNCTION:    Acpi_ex_resolve_operands
  *
- * PARAMETERS:  Opcode              Opcode being interpreted
- *              Stack_ptr           Top of operand stack
+ * PARAMETERS:  Opcode              - Opcode being interpreted
+ *              Stack_ptr           - Pointer to the operand stack to be
+ *                                    resolved
+ *              Walk_state          - Current stateu
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Convert stack entries to required types
+ * DESCRIPTION: Convert multiple input operands to the types required by the
+ *              target operator.
  *
- *      Each nibble in Arg_types represents one required operand
- *      and indicates the required Type:
+ *      Each nibble (actually 5 bits)  in Arg_types represents one required
+ *      operand and indicates the required Type:
  *
- *      The corresponding stack entry will be converted to the
- *      required type if possible, else return an exception
+ *      The corresponding operand will be converted to the required type if
+ *      possible, otherwise we abort with an exception.
  *
  ******************************************************************************/
 
@@ -116,7 +119,7 @@
 	acpi_object_type        type_needed;
 
 
-	FUNCTION_TRACE_U32 ("Ex_resolve_operands", opcode);
+	ACPI_FUNCTION_TRACE_U32 ("Ex_resolve_operands", opcode);
 
 
 	op_info = acpi_ps_get_opcode_info (opcode);
@@ -124,7 +127,6 @@
 		return_ACPI_STATUS (AE_AML_BAD_OPCODE);
 	}
 
-
 	arg_types = op_info->runtime_args;
 	if (arg_types == ARGI_INVALID_OPCODE) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - %X is not a valid AML opcode\n",
@@ -136,7 +138,6 @@
 	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Opcode %X Operand_types=%X \n",
 		opcode, arg_types));
 
-
 	/*
 	 * Normal exit is with (Arg_types == 0) at end of argument list.
 	 * Function will return an exception from within the loop upon
@@ -158,13 +159,17 @@
 
 		/* Decode the descriptor type */
 
-		if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_NAMED)) {
+		switch (ACPI_GET_DESCRIPTOR_TYPE (obj_desc)) {
+		case ACPI_DESC_TYPE_NAMED:
+
 			/* Node */
 
 			object_type = ((acpi_namespace_node *) obj_desc)->type;
-		}
+			break;
+
+
+		case ACPI_DESC_TYPE_INTERNAL:
 
-		else if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_INTERNAL)) {
 			/* ACPI internal object */
 
 			object_type = obj_desc->common.type;
@@ -187,7 +192,6 @@
 					return_ACPI_STATUS (AE_AML_BAD_OPCODE);
 				}
 
-
 				switch (obj_desc->reference.opcode) {
 				case AML_ZERO_OP:
 				case AML_ONE_OP:
@@ -199,27 +203,28 @@
 				case AML_LOCAL_OP:
 				case AML_REVISION_OP:
 
-					DEBUG_ONLY_MEMBERS (ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+					ACPI_DEBUG_ONLY_MEMBERS (ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 						"Reference Opcode: %s\n", op_info->name)));
 					break;
 
 				default:
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 						"Reference Opcode: Unknown [%02x]\n",
 						obj_desc->reference.opcode));
 
 					return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
-					break;
 				}
 			}
-		}
+			break;
+
+
+		default:
 
-		else {
 			/* Invalid descriptor */
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 				"Bad descriptor type %X in Obj %p\n",
-				obj_desc->common.data_type, obj_desc));
+				ACPI_GET_DESCRIPTOR_TYPE (obj_desc), obj_desc));
 
 			return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 		}
@@ -231,24 +236,35 @@
 		this_arg_type = GET_CURRENT_ARG_TYPE (arg_types);
 		INCREMENT_ARG_LIST (arg_types);
 
-
 		/*
 		 * Handle cases where the object does not need to be
 		 * resolved to a value
 		 */
 		switch (this_arg_type) {
+		case ARGI_REF_OR_STRING:        /* Can be a String or Reference */
+
+			if ((ACPI_GET_DESCRIPTOR_TYPE (obj_desc) == ACPI_DESC_TYPE_INTERNAL) &&
+				(ACPI_GET_OBJECT_TYPE (obj_desc) == ACPI_TYPE_STRING)) {
+				/*
+				 * String found - the string references a named object and must be
+				 * resolved to a node
+				 */
+				goto next_operand;
+			}
 
-		case ARGI_REFERENCE:            /* References */
+			/* Else not a string - fall through to the normal Reference case below */
+
+		case ARGI_REFERENCE:            /* References: */
 		case ARGI_INTEGER_REF:
 		case ARGI_OBJECT_REF:
 		case ARGI_DEVICE_REF:
-		case ARGI_TARGETREF:            /* TBD: must implement implicit conversion rules before store */
+		case ARGI_TARGETREF:            /* Allows implicit conversion rules before store */
 		case ARGI_FIXED_TARGET:         /* No implicit conversion before store to target */
-		case ARGI_SIMPLE_TARGET:        /* Name, Local, or Arg - no implicit conversion */
+		case ARGI_SIMPLE_TARGET:        /* Name, Local, or Arg - no implicit conversion  */
 
 			/* Need an operand of type INTERNAL_TYPE_REFERENCE */
 
-			if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_NAMED))            /* direct name ptr OK as-is */ {
+			if (ACPI_GET_DESCRIPTOR_TYPE (obj_desc) == ACPI_DESC_TYPE_NAMED) /* Node (name) ptr OK as-is */ {
 				goto next_operand;
 			}
 
@@ -258,7 +274,6 @@
 				return_ACPI_STATUS (status);
 			}
 
-
 			if (AML_NAME_OP == obj_desc->reference.opcode) {
 				/*
 				 * Convert an indirect name ptr to direct name ptr and put
@@ -268,9 +283,7 @@
 				acpi_ut_remove_reference (obj_desc);
 				(*stack_ptr) = temp_node;
 			}
-
 			goto next_operand;
-			break;
 
 
 		case ARGI_ANYTYPE:
@@ -298,7 +311,6 @@
 			return_ACPI_STATUS (status);
 		}
 
-
 		/*
 		 * Check the resulting object (value) type
 		 */
@@ -362,7 +374,7 @@
 			status = acpi_ex_convert_to_integer (*stack_ptr, stack_ptr, walk_state);
 			if (ACPI_FAILURE (status)) {
 				if (status == AE_TYPE) {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 						"Needed [Integer/String/Buffer], found [%s] %p\n",
 						acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
 
@@ -371,9 +383,7 @@
 
 				return_ACPI_STATUS (status);
 			}
-
 			goto next_operand;
-			break;
 
 
 		case ARGI_BUFFER:
@@ -385,7 +395,7 @@
 			status = acpi_ex_convert_to_buffer (*stack_ptr, stack_ptr, walk_state);
 			if (ACPI_FAILURE (status)) {
 				if (status == AE_TYPE) {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 						"Needed [Integer/String/Buffer], found [%s] %p\n",
 						acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
 
@@ -394,9 +404,7 @@
 
 				return_ACPI_STATUS (status);
 			}
-
 			goto next_operand;
-			break;
 
 
 		case ARGI_STRING:
@@ -408,7 +416,7 @@
 			status = acpi_ex_convert_to_string (*stack_ptr, stack_ptr, 16, ACPI_UINT32_MAX, walk_state);
 			if (ACPI_FAILURE (status)) {
 				if (status == AE_TYPE) {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 						"Needed [Integer/String/Buffer], found [%s] %p\n",
 						acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
 
@@ -417,82 +425,109 @@
 
 				return_ACPI_STATUS (status);
 			}
-
 			goto next_operand;
-			break;
 
 
 		case ARGI_COMPUTEDATA:
 
 			/* Need an operand of type INTEGER, STRING or BUFFER */
 
-			if ((ACPI_TYPE_INTEGER != (*stack_ptr)->common.type) &&
-				(ACPI_TYPE_STRING != (*stack_ptr)->common.type) &&
-				(ACPI_TYPE_BUFFER != (*stack_ptr)->common.type)) {
-				ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+			switch ((*stack_ptr)->common.type) {
+			case ACPI_TYPE_INTEGER:
+			case ACPI_TYPE_STRING:
+			case ACPI_TYPE_BUFFER:
+
+				/* Valid operand */
+			   break;
+
+			default:
+				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 					"Needed [Integer/String/Buffer], found [%s] %p\n",
 					acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
 
 				return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 			}
 			goto next_operand;
-			break;
 
 
 		case ARGI_DATAOBJECT:
 			/*
 			 * ARGI_DATAOBJECT is only used by the Size_of operator.
+			 * Need a buffer, string, package, or Node reference.
 			 *
-			 * The ACPI specification allows Size_of to return the size of
-			 *  a Buffer, String or Package.  However, the MS ACPI.SYS AML
-			 *  Interpreter also allows an Node reference to return without
-			 *  error with a size of 4.
-			 */
-
-			/* Need a buffer, string, package or Node reference */
-
-			if (((*stack_ptr)->common.type != ACPI_TYPE_BUFFER) &&
-				((*stack_ptr)->common.type != ACPI_TYPE_STRING) &&
-				((*stack_ptr)->common.type != ACPI_TYPE_PACKAGE) &&
-				((*stack_ptr)->common.type != INTERNAL_TYPE_REFERENCE)) {
-				ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-					"Needed [Buf/Str/Pkg/Ref], found [%s] %p\n",
-					acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
-
-				return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
-			}
-
-			/*
-			 * If this is a reference, only allow a reference to an Node.
+			 * The only reference allowed here is a direct reference to
+			 * a namespace node.
 			 */
 			if ((*stack_ptr)->common.type == INTERNAL_TYPE_REFERENCE) {
 				if (!(*stack_ptr)->reference.node) {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 						"Needed [Node Reference], found [%p]\n",
 						*stack_ptr));
 
 					return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 				}
+
+				/* Get the object attached to the node */
+
+				temp_node = acpi_ns_get_attached_object ((*stack_ptr)->reference.node);
+				if (!temp_node) {
+					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+						"Node [%p] has no attached object\n",
+						(*stack_ptr)->reference.node));
+
+					return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
+				}
+
+				/*
+				 * Swap the reference object with the node's object.  Must add
+				 * a reference to the node object, and remove a reference from
+				 * the original reference object.
+				 */
+				acpi_ut_add_reference (temp_node);
+				acpi_ut_remove_reference (*stack_ptr);
+				(*stack_ptr) = temp_node;
+			}
+
+			/* Need a buffer, string, package */
+
+			switch ((*stack_ptr)->common.type) {
+			case ACPI_TYPE_PACKAGE:
+			case ACPI_TYPE_STRING:
+			case ACPI_TYPE_BUFFER:
+
+				/* Valid operand */
+				break;
+
+			default:
+				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+					"Needed [Buf/Str/Pkg], found [%s] %p\n",
+					acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
+
+				return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 			}
 			goto next_operand;
-			break;
 
 
 		case ARGI_COMPLEXOBJ:
 
 			/* Need a buffer or package or (ACPI 2.0) String */
 
-			if (((*stack_ptr)->common.type != ACPI_TYPE_BUFFER) &&
-				((*stack_ptr)->common.type != ACPI_TYPE_STRING) &&
-				((*stack_ptr)->common.type != ACPI_TYPE_PACKAGE)) {
-				ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-					"Needed [Buf/Pkg], found [%s] %p\n",
+			switch ((*stack_ptr)->common.type) {
+			case ACPI_TYPE_PACKAGE:
+			case ACPI_TYPE_STRING:
+			case ACPI_TYPE_BUFFER:
+
+				/* Valid operand */
+				break;
+
+			default:
+				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+					"Needed [Buf/Str/Pkg], found [%s] %p\n",
 					acpi_ut_get_type_name ((*stack_ptr)->common.type), *stack_ptr));
 
 				return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 			}
 			goto next_operand;
-			break;
 
 
 		default:
@@ -506,7 +541,6 @@
 			return_ACPI_STATUS (AE_BAD_PARAMETER);
 		}
 
-
 		/*
 		 * Make sure that the original object was resolved to the
 		 * required object type (Simple cases only).
@@ -517,7 +551,6 @@
 			return_ACPI_STATUS (status);
 		}
 
-
 next_operand:
 		/*
 		 * If more operands needed, decrement Stack_ptr to point
@@ -528,7 +561,6 @@
 		}
 
 	}   /* while (*Types) */
-
 
 	return_ACPI_STATUS (status);
 }
diff -Nru a/drivers/acpi/executer/exstore.c b/drivers/acpi/executer/exstore.c
--- a/drivers/acpi/executer/exstore.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/executer/exstore.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exstore - AML Interpreter object store support
- *              $Revision: 150 $
+ *              $Revision: 162 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,7 +35,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exstore")
+	 ACPI_MODULE_NAME    ("exstore")
 
 
 /*******************************************************************************
@@ -46,13 +46,15 @@
  *              *Dest_desc          - Where to store it.  Must be an NS node
  *                                    or an acpi_operand_object of type
  *                                    Reference;
+ *              Walk_state          - Current walk state
  *
  * RETURN:      Status
  *
  * DESCRIPTION: Store the value described by Source_desc into the location
  *              described by Dest_desc. Called by various interpreter
  *              functions to store the result of an operation into
- *              the destination operand.
+ *              the destination operand -- not just simply the actual "Store"
+ *              ASL operator.
  *
  ******************************************************************************/
 
@@ -66,19 +68,19 @@
 	acpi_operand_object     *ref_desc = dest_desc;
 
 
-	FUNCTION_TRACE_PTR ("Ex_store", dest_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_store", dest_desc);
 
 
 	/* Validate parameters */
 
 	if (!source_desc || !dest_desc) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - null pointer\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Null parameter\n"));
 		return_ACPI_STATUS (AE_AML_NO_OPERAND);
 	}
 
 	/* Dest_desc can be either a namespace node or an ACPI object */
 
-	if (VALID_DESCRIPTOR_TYPE (dest_desc, ACPI_DESC_TYPE_NAMED)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (dest_desc) == ACPI_DESC_TYPE_NAMED) {
 		/*
 		 * Dest is a namespace node,
 		 * Storing an object into a Name "container"
@@ -86,12 +88,9 @@
 		status = acpi_ex_store_object_to_node (source_desc,
 				 (acpi_namespace_node *) dest_desc, walk_state);
 
-		/* All done, that's it */
-
 		return_ACPI_STATUS (status);
 	}
 
-
 	/* Destination object must be an object of type Reference */
 
 	if (dest_desc->common.type != INTERNAL_TYPE_REFERENCE) {
@@ -100,15 +99,14 @@
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 			"Destination is not a Reference_obj [%p]\n", dest_desc));
 
-		DUMP_STACK_ENTRY (source_desc);
-		DUMP_STACK_ENTRY (dest_desc);
-		DUMP_OPERANDS (&dest_desc, IMODE_EXECUTE, "Ex_store",
+		ACPI_DUMP_STACK_ENTRY (source_desc);
+		ACPI_DUMP_STACK_ENTRY (dest_desc);
+		ACPI_DUMP_OPERANDS (&dest_desc, ACPI_IMODE_EXECUTE, "Ex_store",
 				  2, "Target is not a Reference_obj");
 
 		return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 	}
 
-
 	/*
 	 * Examine the Reference opcode.  These cases are handled:
 	 *
@@ -119,7 +117,6 @@
 	 * 5) Store to a constant -- a noop
 	 */
 	switch (ref_desc->reference.opcode) {
-
 	case AML_NAME_OP:
 
 		/* Storing an object into a Name "container" */
@@ -161,15 +158,16 @@
 		switch (source_desc->common.type) {
 		case ACPI_TYPE_INTEGER:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "0x%X (%d)\n",
-				(u32) source_desc->integer.value, (u32) source_desc->integer.value));
+			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "%8.8X%8.8X\n",
+					ACPI_HIWORD (source_desc->integer.value),
+					ACPI_LOWORD (source_desc->integer.value)));
 			break;
 
 
 		case ACPI_TYPE_BUFFER:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "Length 0x%X\n",
-				(u32) source_desc->buffer.length));
+			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "Length %.2X\n",
+					(u32) source_desc->buffer.length));
 			break;
 
 
@@ -181,14 +179,15 @@
 
 		case ACPI_TYPE_PACKAGE:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "Elements - 0x%X\n",
-				(u32) source_desc->package.elements));
+			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "Elements Ptr - %p\n",
+					source_desc->package.elements));
 			break;
 
 
 		default:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "@0x%p\n", source_desc));
+			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_DEBUG_OBJECT, "Type %s %p\n",
+					acpi_ut_get_type_name (source_desc->common.type), source_desc));
 			break;
 		}
 
@@ -202,27 +201,23 @@
 	case AML_REVISION_OP:
 
 		/*
-		 * Storing to a constant is a no-op -- see ACPI Specification
-		 * Delete the reference descriptor, however
+		 * Storing to a constant is a no-op according to the  ACPI
+		 * Specification. (Delete the reference descriptor, however.)
 		 */
 		break;
 
 
 	default:
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Internal - Unknown Reference subtype %02x\n",
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown Reference subtype %02x\n",
 			ref_desc->reference.opcode));
-
-		/* TBD: [Restructure] use object dump routine !! */
-
-		DUMP_BUFFER (ref_desc, sizeof (acpi_operand_object));
+		ACPI_DUMP_ENTRY (ref_desc, ACPI_LV_ERROR);
 
 		status = AE_AML_INTERNAL;
 		break;
 
 	}   /* switch (Ref_desc->Reference.Opcode) */
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -231,36 +226,36 @@
  *
  * FUNCTION:    Acpi_ex_store_object_to_index
  *
- * PARAMETERS:  *Source_desc          - Value to be stored
- *              *Node               - Named object to receive the value
+ * PARAMETERS:  *Source_desc            - Value to be stored
+ *              *Dest_desc              - Named object to receive the value
+ *              Walk_state              - Current walk state
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Store the object to the named object.
+ * DESCRIPTION: Store the object to indexed Buffer or Package element
  *
  ******************************************************************************/
 
 acpi_status
 acpi_ex_store_object_to_index (
 	acpi_operand_object     *source_desc,
-	acpi_operand_object     *dest_desc,
+	acpi_operand_object     *index_desc,
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status = AE_OK;
 	acpi_operand_object     *obj_desc;
-	u32                     length;
-	u32                     i;
+	acpi_operand_object     *new_desc;
 	u8                      value = 0;
 
 
-	FUNCTION_TRACE ("Ex_store_object_to_index");
+	ACPI_FUNCTION_TRACE ("Ex_store_object_to_index");
 
 
 	/*
 	 * Destination must be a reference pointer, and
 	 * must point to either a buffer or a package
 	 */
-	switch (dest_desc->reference.target_type) {
+	switch (index_desc->reference.target_type) {
 	case ACPI_TYPE_PACKAGE:
 		/*
 		 * Storing to a package element is not simple.  The source must be
@@ -268,95 +263,48 @@
 		 * source is copied into the destination - we can't just point to the
 		 * source object.
 		 */
-		if (dest_desc->reference.target_type == ACPI_TYPE_PACKAGE) {
-			/*
-			 * The object at *(Dest_desc->Reference.Where) is the
-			 * element within the package that is to be modified.
-			 */
-			obj_desc = *(dest_desc->reference.where);
-			if (obj_desc) {
-				/*
-				 * If the Destination element is a package, we will delete
-				 *  that object and construct a new one.
-				 *
-				 * TBD: [Investigate] Should both the src and dest be required
-				 *      to be packages?
-				 *       && (Source_desc->Common.Type == ACPI_TYPE_PACKAGE)
-				 */
-				if (obj_desc->common.type == ACPI_TYPE_PACKAGE) {
-					/* Take away the reference for being part of a package */
-
-					acpi_ut_remove_reference (obj_desc);
-					obj_desc = NULL;
-				}
-			}
-
-			if (!obj_desc) {
-				/*
-				 * If the Obj_desc is NULL, it means that an uninitialized package
-				 * element has been used as a destination (this is OK), therefore,
-				 * we must create the destination element to match the type of the
-				 * source element NOTE: Source_desccan be of any type.
-				 */
-				obj_desc = acpi_ut_create_internal_object (source_desc->common.type);
-				if (!obj_desc) {
-					return_ACPI_STATUS (AE_NO_MEMORY);
-				}
-
-				/*
-				 * If the source is a package, copy the source to the new dest
-				 */
-				if (ACPI_TYPE_PACKAGE == obj_desc->common.type) {
-					status = acpi_ut_copy_ipackage_to_ipackage (source_desc, obj_desc, walk_state);
-					if (ACPI_FAILURE (status)) {
-						acpi_ut_remove_reference (obj_desc);
-						return_ACPI_STATUS (status);
-					}
-				}
-
-				/* Install the new descriptor into the package */
-
-				*(dest_desc->reference.where) = obj_desc;
-			}
-
-			if (ACPI_TYPE_PACKAGE != obj_desc->common.type) {
-				/*
-				 * The destination element is not a package, so we need to
-				 * convert the contents of the source (Source_desc) and copy into
-				 * the destination (Obj_desc)
-				 */
-				status = acpi_ex_store_object_to_object (source_desc, obj_desc,
-						  walk_state);
-				if (ACPI_FAILURE (status)) {
-					/*
-					 * An error occurrered when copying the internal object
-					 * so delete the reference.
-					 */
-					ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-						"Unable to copy the internal object\n"));
-					return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
-				}
-			}
+		/*
+		 * The object at *(Index_desc->Reference.Where) is the
+		 * element within the package that is to be modified.
+		 */
+		obj_desc = *(index_desc->reference.where);
+
+		/* Do the conversion/store */
+
+		status = acpi_ex_store_object_to_object (source_desc, obj_desc, &new_desc,
+				  walk_state);
+		if (ACPI_FAILURE (status)) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Could not store object to indexed package element\n"));
+			return_ACPI_STATUS (status);
+		}
+
+		/*
+		 * If a new object was created, we must install it as the new
+		 * package element
+		 */
+		if (new_desc != obj_desc) {
+			acpi_ut_remove_reference (obj_desc);
+			*(index_desc->reference.where) = new_desc;
 		}
 		break;
 
 
 	case ACPI_TYPE_BUFFER_FIELD:
 
-
-		/* TBD: can probably call the generic Buffer/Field routines */
-
 		/*
-		 * Storing into a buffer at a location defined by an Index.
+		 * Store into a Buffer (not actually a real Buffer_field) at a
+		 * location defined by an Index.
 		 *
-		 * Each 8-bit element of the source object is written to the
-		 * 8-bit Buffer Field of the Index destination object.
+		 * The first 8-bit element of the source object is written to the
+		 * 8-bit Buffer location defined by the Index destination object,
+		 * according to the ACPI 2.0 specification.
 		 */
 
 		/*
-		 * Set the Obj_desc to the destination object and type check.
+		 * Make sure the target is a Buffer
 		 */
-		obj_desc = dest_desc->reference.object;
+		obj_desc = index_desc->reference.object;
 		if (obj_desc->common.type != ACPI_TYPE_BUFFER) {
 			return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 		}
@@ -367,65 +315,45 @@
 		 */
 		switch (source_desc->common.type) {
 		case ACPI_TYPE_INTEGER:
-			/*
-			 * Type is Integer, assign bytewise
-			 * This loop to assign each of the elements is somewhat
-			 * backward because of the Big Endian-ness of IA-64
-			 */
-			length = sizeof (acpi_integer);
-			for (i = length; i != 0; i--) {
-				value = (u8)(source_desc->integer.value >> (MUL_8 (i - 1)));
-				obj_desc->buffer.pointer[dest_desc->reference.offset] = value;
-			}
-			break;
 
+			/* Use the least-significant byte of the integer */
 
-		case ACPI_TYPE_BUFFER:
-			/*
-			 * Type is Buffer, the Length is in the structure.
-			 * Just loop through the elements and assign each one in turn.
-			 */
-			length = source_desc->buffer.length;
-			for (i = 0; i < length; i++) {
-				value = source_desc->buffer.pointer[i];
-				obj_desc->buffer.pointer[dest_desc->reference.offset] = value;
-			}
+			value = (u8) (source_desc->integer.value);
 			break;
 
+		case ACPI_TYPE_BUFFER:
 
-		case ACPI_TYPE_STRING:
-			/*
-			 * Type is String, the Length is in the structure.
-			 * Just loop through the elements and assign each one in turn.
-			 */
-			length = source_desc->string.length;
-			for (i = 0; i < length; i++) {
-				value = source_desc->string.pointer[i];
-				obj_desc->buffer.pointer[dest_desc->reference.offset] = value;
-			}
+			value = source_desc->buffer.pointer[0];
 			break;
 
+		case ACPI_TYPE_STRING:
+
+			value = source_desc->string.pointer[0];
+			break;
 
 		default:
 
-			/* Other types are invalid */
+			/* All other types are invalid */
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Source must be Number/Buffer/String type, not %X\n",
-				source_desc->common.type));
-			status = AE_AML_OPERAND_TYPE;
-			break;
+				"Source must be Integer/Buffer/String type, not %s\n",
+				acpi_ut_get_type_name (source_desc->common.type)));
+			return_ACPI_STATUS (AE_AML_OPERAND_TYPE);
 		}
+
+		/* Store the source value into the target buffer byte */
+
+		obj_desc->buffer.pointer[index_desc->reference.offset] = value;
 		break;
 
 
 	default:
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Target is not a Package or Buffer_field\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+			"Target is not a Package or Buffer_field\n"));
 		status = AE_AML_OPERAND_TYPE;
 		break;
 	}
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -434,15 +362,16 @@
  *
  * FUNCTION:    Acpi_ex_store_object_to_node
  *
- * PARAMETERS:  *Source_desc           - Value to be stored
- *              *Node                  - Named object to receive the value
+ * PARAMETERS:  Source_desc             - Value to be stored
+ *              Node                    - Named object to receive the value
+ *              Walk_state              - Current walk state
  *
  * RETURN:      Status
  *
  * DESCRIPTION: Store the object to the named object.
  *
  *              The Assignment of an object to a named object is handled here
- *              The val passed in will replace the current value (if any)
+ *              The value passed in will replace the current value (if any)
  *              with the input value.
  *
  *              When storing into an object the data is converted to the
@@ -450,10 +379,7 @@
  *              that the target object type (for an initialized target) will
  *              not be changed by a store operation.
  *
- *              NOTE: the global lock is acquired early.  This will result
- *              in the global lock being held a bit longer.  Also, if the
- *              function fails during set up we may get the lock when we
- *              don't really need it.  I don't think we care.
+ *              Assumes parameters are already validated.
  *
  ******************************************************************************/
 
@@ -465,26 +391,22 @@
 {
 	acpi_status             status = AE_OK;
 	acpi_operand_object     *target_desc;
-	acpi_object_type8       target_type = ACPI_TYPE_ANY;
+	acpi_operand_object     *new_desc;
+	acpi_object_type        target_type;
 
 
-	FUNCTION_TRACE ("Ex_store_object_to_node");
+	ACPI_FUNCTION_TRACE_PTR ("Ex_store_object_to_node", source_desc);
 
 
 	/*
-	 * Assuming the parameters were already validated
-	 */
-
-	/*
 	 * Get current type of the node, and object attached to Node
 	 */
 	target_type = acpi_ns_get_type (node);
 	target_desc = acpi_ns_get_attached_object (node);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Storing %p(%s) into node %p(%s)\n",
-		node, acpi_ut_get_type_name (source_desc->common.type),
-		source_desc, acpi_ut_get_type_name (target_type)));
-
+		source_desc, acpi_ut_get_type_name (source_desc->common.type),
+			  node, acpi_ut_get_type_name (target_type)));
 
 	/*
 	 * Resolve the source object to an actual value
@@ -495,7 +417,6 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/*
 	 * Do the actual store operation
 	 */
@@ -522,22 +443,24 @@
 		 *
 		 * Copy and/or convert the source object to a new target object
 		 */
-		status = acpi_ex_store_object (source_desc, target_type, &target_desc, walk_state);
+		status = acpi_ex_store_object_to_object (source_desc, target_desc, &new_desc, walk_state);
 		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
 
-		/*
-		 * Store the new Target_desc as the new value of the Name, and set
-		 * the Name's type to that of the value being stored in it.
-		 * Source_desc reference count is incremented by Attach_object.
-		 */
-		status = acpi_ns_attach_object (node, target_desc, target_type);
+		if (new_desc != target_desc) {
+			/*
+			 * Store the new New_desc as the new value of the Name, and set
+			 * the Name's type to that of the value being stored in it.
+			 * Source_desc reference count is incremented by Attach_object.
+			 */
+			status = acpi_ns_attach_object (node, new_desc, target_type);
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-			"Store %s into %s via Convert/Attach\n",
-			acpi_ut_get_type_name (target_desc->common.type),
-			acpi_ut_get_type_name (target_type)));
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+				"Store %s into %s via Convert/Attach\n",
+				acpi_ut_get_type_name (source_desc->common.type),
+				acpi_ut_get_type_name (new_desc->common.type)));
+		}
 		break;
 
 
@@ -553,91 +476,7 @@
 		break;
 	}
 
-
 	return_ACPI_STATUS (status);
 }
 
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ex_store_object_to_object
- *
- * PARAMETERS:  *Source_desc           - Value to be stored
- *              *Dest_desc          - Object to receive the value
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Store an object to another object.
- *
- *              The Assignment of an object to another (not named) object
- *              is handled here.
- *              The val passed in will replace the current value (if any)
- *              with the input value.
- *
- *              When storing into an object the data is converted to the
- *              target object type then stored in the object.  This means
- *              that the target object type (for an initialized target) will
- *              not be changed by a store operation.
- *
- *              This module allows destination types of Number, String,
- *              and Buffer.
- *
- ******************************************************************************/
-
-acpi_status
-acpi_ex_store_object_to_object (
-	acpi_operand_object     *source_desc,
-	acpi_operand_object     *dest_desc,
-	acpi_walk_state         *walk_state)
-{
-	acpi_status             status = AE_OK;
-	acpi_object_type8       destination_type = dest_desc->common.type;
-
-
-	FUNCTION_TRACE ("Ex_store_object_to_object");
-
-
-	/*
-	 *  Assuming the parameters are valid!
-	 */
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Storing %p(%s) to %p(%s)\n",
-			  source_desc, acpi_ut_get_type_name (source_desc->common.type),
-			  dest_desc, acpi_ut_get_type_name (dest_desc->common.type)));
-
-
-	/*
-	 * From this interface, we only support Integers/Strings/Buffers
-	 */
-	switch (destination_type) {
-	case ACPI_TYPE_INTEGER:
-	case ACPI_TYPE_STRING:
-	case ACPI_TYPE_BUFFER:
-		break;
-
-	default:
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Store into %s not implemented\n",
-			acpi_ut_get_type_name (dest_desc->common.type)));
-
-		return_ACPI_STATUS (AE_NOT_IMPLEMENTED);
-	}
-
-
-	/*
-	 * Resolve the source object to an actual value
-	 * (If it is a reference object)
-	 */
-	status = acpi_ex_resolve_object (&source_desc, destination_type, walk_state);
-	if (ACPI_FAILURE (status)) {
-		return_ACPI_STATUS (status);
-	}
-
-
-	/*
-	 * Copy and/or convert the source object to the destination object
-	 */
-	status = acpi_ex_store_object (source_desc, destination_type, &dest_desc, walk_state);
-
-
-	return_ACPI_STATUS (status);
-}
 
diff -Nru a/drivers/acpi/executer/exstoren.c b/drivers/acpi/executer/exstoren.c
--- a/drivers/acpi/executer/exstoren.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exstoren.c	Fri Mar 15 17:51:01 2002
@@ -3,12 +3,12 @@
  *
  * Module Name: exstoren - AML Interpreter object store support,
  *                        Store to Node (namespace object)
- *              $Revision: 40 $
+ *              $Revision: 46 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -36,7 +36,7 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exstoren")
+	 ACPI_MODULE_NAME    ("exstoren")
 
 
 /*******************************************************************************
@@ -57,66 +57,61 @@
 acpi_status
 acpi_ex_resolve_object (
 	acpi_operand_object     **source_desc_ptr,
-	acpi_object_type8       target_type,
+	acpi_object_type        target_type,
 	acpi_walk_state         *walk_state)
 {
 	acpi_operand_object     *source_desc = *source_desc_ptr;
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_resolve_object");
+	ACPI_FUNCTION_TRACE ("Ex_resolve_object");
 
 
 	/*
-	 * Ensure we have a Source that can be stored in the target
+	 * Ensure we have a Target that can be stored to
 	 */
 	switch (target_type) {
-
-	/* This case handles the "interchangeable" types Integer, String, and Buffer. */
-
-	/*
-	 * These cases all require only Integers or values that
-	 * can be converted to Integers (Strings or Buffers)
-	 */
 	case ACPI_TYPE_BUFFER_FIELD:
 	case INTERNAL_TYPE_REGION_FIELD:
 	case INTERNAL_TYPE_BANK_FIELD:
 	case INTERNAL_TYPE_INDEX_FIELD:
+		/*
+		 * These cases all require only Integers or values that
+		 * can be converted to Integers (Strings or Buffers)
+		 */
 
-	/*
-	 * Stores into a Field/Region or into a Buffer/String
-	 * are all essentially the same.
-	 */
 	case ACPI_TYPE_INTEGER:
 	case ACPI_TYPE_STRING:
 	case ACPI_TYPE_BUFFER:
 
+		/*
+		 * Stores into a Field/Region or into a Integer/Buffer/String
+		 * are all essentially the same.  This case handles the
+		 * "interchangeable" types Integer, String, and Buffer.
+		 */
+		if (source_desc->common.type == INTERNAL_TYPE_REFERENCE) {
+			/* Resolve a reference object first */
 
-		/* TBD: FIX - check for source==REF, resolve, then check type */
+			status = acpi_ex_resolve_to_value (source_desc_ptr, walk_state);
+			if (ACPI_FAILURE (status)) {
+				break;
+			}
+		}
 
 		/*
-		 * If Source_desc is not a valid type, try to resolve it to one.
+		 * Must have a Integer, Buffer, or String
 		 */
 		if ((source_desc->common.type != ACPI_TYPE_INTEGER)    &&
 			(source_desc->common.type != ACPI_TYPE_BUFFER)     &&
 			(source_desc->common.type != ACPI_TYPE_STRING)) {
 			/*
-			 * Initially not a valid type, convert
+			 * Conversion successful but still not a valid type
 			 */
-			status = acpi_ex_resolve_to_value (source_desc_ptr, walk_state);
-			if (ACPI_SUCCESS (status) &&
-				(source_desc->common.type != ACPI_TYPE_INTEGER)    &&
-				(source_desc->common.type != ACPI_TYPE_BUFFER)     &&
-				(source_desc->common.type != ACPI_TYPE_STRING)) {
-				/*
-				 * Conversion successful but still not a valid type
-				 */
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-					"Cannot assign type %s to %s (must be type Int/Str/Buf)\n",
-					acpi_ut_get_type_name ((*source_desc_ptr)->common.type),
-					acpi_ut_get_type_name (target_type)));
-				status = AE_AML_OPERAND_TYPE;
-			}
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Cannot assign type %s to %s (must be type Int/Str/Buf)\n",
+				acpi_ut_get_type_name (source_desc->common.type),
+				acpi_ut_get_type_name (target_type)));
+			status = AE_AML_OPERAND_TYPE;
 		}
 		break;
 
@@ -147,11 +142,11 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_store_object
+ * FUNCTION:    Acpi_ex_store_object_to_object
  *
  * PARAMETERS:  Source_desc         - Object to store
- *              Target_type         - Current type of the target
- *              Target_desc_ptr     - Pointer to the target
+ *              Dest_desc           - Object to recieve a copy of the source
+ *              New_desc            - New object if Dest_desc is obsoleted
  *              Walk_state          - Current walk state
  *
  * RETURN:      Status
@@ -161,93 +156,114 @@
  *              conversion), and a copy of the value of the source to
  *              the target.
  *
+ *              The Assignment of an object to another (not named) object
+ *              is handled here.
+ *              The Source passed in will replace the current value (if any)
+ *              with the input value.
+ *
+ *              When storing into an object the data is converted to the
+ *              target object type then stored in the object.  This means
+ *              that the target object type (for an initialized target) will
+ *              not be changed by a store operation.
+ *
+ *              This module allows destination types of Number, String,
+ *              Buffer, and Package.
+ *
+ *              Assumes parameters are already validated.  NOTE: Source_desc
+ *              resolution (from a reference object) must be performed by
+ *              the caller if necessary.
+ *
  ******************************************************************************/
 
 acpi_status
-acpi_ex_store_object (
+acpi_ex_store_object_to_object (
 	acpi_operand_object     *source_desc,
-	acpi_object_type8       target_type,
-	acpi_operand_object     **target_desc_ptr,
+	acpi_operand_object     *dest_desc,
+	acpi_operand_object     **new_desc,
 	acpi_walk_state         *walk_state)
 {
-	acpi_operand_object     *target_desc = *target_desc_ptr;
+	acpi_operand_object     *actual_src_desc;
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_store_object");
+	ACPI_FUNCTION_TRACE_PTR ("Acpi_ex_store_object_to_object", source_desc);
 
 
-	/*
-	 * Perform the "implicit conversion" of the source to the current type
-	 * of the target - As per the ACPI specification.
-	 *
-	 * If no conversion performed, Source_desc is left alone, otherwise it
-	 * is updated with a new object.
-	 */
-	status = acpi_ex_convert_to_target_type (target_type, &source_desc, walk_state);
-	if (ACPI_FAILURE (status)) {
+	actual_src_desc = source_desc;
+	if (!dest_desc) {
+		/*
+		 * There is no destination object (An uninitialized node or
+		 * package element), so we can simply copy the source object
+		 * creating a new destination object
+		 */
+		status = acpi_ut_copy_iobject_to_iobject (actual_src_desc, new_desc, walk_state);
 		return_ACPI_STATUS (status);
 	}
 
+	if (source_desc->common.type != dest_desc->common.type) {
+		/*
+		 * The source type does not match the type of the destination.
+		 * Perform the "implicit conversion" of the source to the current type
+		 * of the target as per the ACPI specification.
+		 *
+		 * If no conversion performed, Actual_src_desc = Source_desc.
+		 * Otherwise, Actual_src_desc is a temporary object to hold the
+		 * converted object.
+		 */
+		status = acpi_ex_convert_to_target_type (dest_desc->common.type, source_desc,
+				  &actual_src_desc, walk_state);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
+	}
+
 	/*
 	 * We now have two objects of identical types, and we can perform a
 	 * copy of the *value* of the source object.
 	 */
-	switch (target_type) {
-	case ACPI_TYPE_ANY:
-	case INTERNAL_TYPE_DEF_ANY:
-
-		/*
-		 * The target namespace node is uninitialized (has no target object),
-		 * and will take on the type of the source object
-		 */
-		*target_desc_ptr = source_desc;
-		break;
-
-
+	switch (dest_desc->common.type) {
 	case ACPI_TYPE_INTEGER:
 
-		target_desc->integer.value = source_desc->integer.value;
+		dest_desc->integer.value = actual_src_desc->integer.value;
 
 		/* Truncate value if we are executing from a 32-bit ACPI table */
 
-		acpi_ex_truncate_for32bit_table (target_desc, walk_state);
+		acpi_ex_truncate_for32bit_table (dest_desc, walk_state);
 		break;
 
 	case ACPI_TYPE_STRING:
 
-		status = acpi_ex_copy_string_to_string (source_desc, target_desc);
+		status = acpi_ex_store_string_to_string (actual_src_desc, dest_desc);
 		break;
 
-
 	case ACPI_TYPE_BUFFER:
 
-		status = acpi_ex_copy_buffer_to_buffer (source_desc, target_desc);
+		status = acpi_ex_store_buffer_to_buffer (actual_src_desc, dest_desc);
 		break;
 
-
 	case ACPI_TYPE_PACKAGE:
 
-		/*
-		 * TBD: [Unhandled] Not real sure what to do here
-		 */
-		status = AE_NOT_IMPLEMENTED;
+		status = acpi_ut_copy_iobject_to_iobject (actual_src_desc, &dest_desc, walk_state);
 		break;
 
-
 	default:
-
 		/*
 		 * All other types come here.
 		 */
 		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Store into type %s not implemented\n",
-			acpi_ut_get_type_name (target_type)));
+			acpi_ut_get_type_name (dest_desc->common.type)));
 
 		status = AE_NOT_IMPLEMENTED;
 		break;
 	}
 
+	if (actual_src_desc != source_desc) {
+		/* Delete the intermediate (temporary) source object */
+
+		acpi_ut_remove_reference (actual_src_desc);
+	}
 
+	*new_desc = dest_desc;
 	return_ACPI_STATUS (status);
 }
 
diff -Nru a/drivers/acpi/executer/exstorob.c b/drivers/acpi/executer/exstorob.c
--- a/drivers/acpi/executer/exstorob.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/executer/exstorob.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exstorob - AML Interpreter object store support, store to object
- *              $Revision: 37 $
+ *              $Revision: 41 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,12 +35,12 @@
 
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exstorob")
+	 ACPI_MODULE_NAME    ("exstorob")
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_copy_buffer_to_buffer
+ * FUNCTION:    Acpi_ex_store_buffer_to_buffer
  *
  * PARAMETERS:  Source_desc         - Source object to copy
  *              Target_desc         - Destination object of the copy
@@ -52,7 +52,7 @@
  ******************************************************************************/
 
 acpi_status
-acpi_ex_copy_buffer_to_buffer (
+acpi_ex_store_buffer_to_buffer (
 	acpi_operand_object     *source_desc,
 	acpi_operand_object     *target_desc)
 {
@@ -60,7 +60,7 @@
 	u8                      *buffer;
 
 
-	PROC_NAME ("Ex_copy_buffer_to_buffer");
+	ACPI_FUNCTION_NAME ("Ex_store_buffer_to_buffer");
 
 
 	/*
@@ -89,15 +89,15 @@
 	if (length <= target_desc->buffer.length) {
 		/* Clear existing buffer and copy in the new one */
 
-		MEMSET (target_desc->buffer.pointer, 0, target_desc->buffer.length);
-		MEMCPY (target_desc->buffer.pointer, buffer, length);
+		ACPI_MEMSET (target_desc->buffer.pointer, 0, target_desc->buffer.length);
+		ACPI_MEMCPY (target_desc->buffer.pointer, buffer, length);
 	}
 
 	else {
 		/*
 		 * Truncate the source, copy only what will fit
 		 */
-		MEMCPY (target_desc->buffer.pointer, buffer, target_desc->buffer.length);
+		ACPI_MEMCPY (target_desc->buffer.pointer, buffer, target_desc->buffer.length);
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 			"Truncating src buffer from %X to %X\n",
@@ -110,7 +110,7 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ex_copy_string_to_string
+ * FUNCTION:    Acpi_ex_store_string_to_string
  *
  * PARAMETERS:  Source_desc         - Source object to copy
  *              Target_desc         - Destination object of the copy
@@ -122,7 +122,7 @@
  ******************************************************************************/
 
 acpi_status
-acpi_ex_copy_string_to_string (
+acpi_ex_store_string_to_string (
 	acpi_operand_object     *source_desc,
 	acpi_operand_object     *target_desc)
 {
@@ -130,7 +130,7 @@
 	u8                      *buffer;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -145,8 +145,8 @@
 	if (length < target_desc->string.length) {
 		/* Clear old string and copy in the new one */
 
-		MEMSET (target_desc->string.pointer, 0, target_desc->string.length);
-		MEMCPY (target_desc->string.pointer, buffer, length);
+		ACPI_MEMSET (target_desc->string.pointer, 0, target_desc->string.length);
+		ACPI_MEMCPY (target_desc->string.pointer, buffer, length);
 	}
 
 	else {
@@ -168,7 +168,7 @@
 		}
 
 		target_desc->string.length = length;
-		MEMCPY (target_desc->string.pointer, buffer, length);
+		ACPI_MEMCPY (target_desc->string.pointer, buffer, length);
 	}
 
 	return (AE_OK);
diff -Nru a/drivers/acpi/executer/exsystem.c b/drivers/acpi/executer/exsystem.c
--- a/drivers/acpi/executer/exsystem.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exsystem.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exsystem - Interface to OS services
- *              $Revision: 67 $
+ *              $Revision: 71 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acevents.h"
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exsystem")
+	 ACPI_MODULE_NAME    ("exsystem")
 
 
 /*******************************************************************************
@@ -56,9 +56,10 @@
 	u32                     timeout)
 {
 	acpi_status             status;
+	acpi_status             status2;
 
 
-	FUNCTION_TRACE ("Ex_system_wait_semaphore");
+	ACPI_FUNCTION_TRACE ("Ex_system_wait_semaphore");
 
 
 	status = acpi_os_wait_semaphore (semaphore, 1, 0);
@@ -78,11 +79,11 @@
 
 		/* Reacquire the interpreter */
 
-		status = acpi_ex_enter_interpreter ();
-		if (ACPI_SUCCESS (status)) {
-			/* Restore the timeout exception */
+		status2 = acpi_ex_enter_interpreter ();
+		if (ACPI_FAILURE (status2)) {
+			/* Report fatal error, could not acquire interpreter */
 
-			status = AE_TIME;
+			return_ACPI_STATUS (status2);
 		}
 	}
 
@@ -96,17 +97,20 @@
  *
  * PARAMETERS:  How_long            - The amount of time to stall
  *
- * RETURN:      None
+ * RETURN:      Status
  *
  * DESCRIPTION: Suspend running thread for specified amount of time.
  *
  ******************************************************************************/
 
-void
+acpi_status
 acpi_ex_system_do_stall (
 	u32                     how_long)
 {
-	FUNCTION_ENTRY ();
+	acpi_status             status = AE_OK;
+
+
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (how_long > 1000) /* 1 millisecond */ {
@@ -118,12 +122,14 @@
 
 		/* And now we must get the interpreter again */
 
-		acpi_ex_enter_interpreter ();
+		status = acpi_ex_enter_interpreter ();
 	}
 
 	else {
 		acpi_os_sleep (0, (how_long / 1000) + 1);
 	}
+
+	return (status);
 }
 
 
@@ -139,12 +145,14 @@
  *
  ******************************************************************************/
 
-void
+acpi_status
 acpi_ex_system_do_suspend (
 	u32                     how_long)
 {
+	acpi_status             status;
+
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* Since this thread will sleep, we must release the interpreter */
@@ -156,7 +164,8 @@
 
 	/* And now we must get the interpreter again */
 
-	acpi_ex_enter_interpreter ();
+	status = acpi_ex_enter_interpreter ();
+	return (status);
 }
 
 
@@ -183,7 +192,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_PTR ("Ex_system_acquire_mutex", obj_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Ex_system_acquire_mutex", obj_desc);
 
 
 	if (!obj_desc) {
@@ -194,7 +203,7 @@
 	 * Support for the _GL_ Mutex object -- go get the global lock
 	 */
 	if (obj_desc->mutex.semaphore == acpi_gbl_global_lock_semaphore) {
-		status = acpi_ev_acquire_global_lock ();
+		status = acpi_ev_acquire_global_lock ((u32) time_desc->integer.value);
 		return_ACPI_STATUS (status);
 	}
 
@@ -226,7 +235,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_system_release_mutex");
+	ACPI_FUNCTION_TRACE ("Ex_system_release_mutex");
 
 
 	if (!obj_desc) {
@@ -266,7 +275,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_system_signal_event");
+	ACPI_FUNCTION_TRACE ("Ex_system_signal_event");
 
 
 	if (obj_desc) {
@@ -300,7 +309,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ex_system_wait_event");
+	ACPI_FUNCTION_TRACE ("Ex_system_wait_event");
 
 
 	if (obj_desc) {
@@ -308,7 +317,6 @@
 				  (u32) time_desc->integer.value);
 	}
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -333,7 +341,7 @@
 	void                    *temp_semaphore;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
diff -Nru a/drivers/acpi/executer/exutils.c b/drivers/acpi/executer/exutils.c
--- a/drivers/acpi/executer/exutils.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/executer/exutils.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: exutils - interpreter/scanner utilities
- *              $Revision: 85 $
+ *              $Revision: 93 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -50,7 +50,7 @@
 #include "acparser.h"
 
 #define _COMPONENT          ACPI_EXECUTER
-	 MODULE_NAME         ("exutils")
+	 ACPI_MODULE_NAME    ("exutils")
 
 
 /*******************************************************************************
@@ -59,8 +59,8 @@
  *
  * PARAMETERS:  None
  *
- * DESCRIPTION: Enter the interpreter execution region
- *              TBD: should be a macro
+ * DESCRIPTION: Enter the interpreter execution region.  Failure to enter
+ *              the interpreter region is a fatal system error
  *
  ******************************************************************************/
 
@@ -69,10 +69,14 @@
 {
 	acpi_status             status;
 
-	FUNCTION_TRACE ("Ex_enter_interpreter");
+	ACPI_FUNCTION_TRACE ("Ex_enter_interpreter");
 
 
 	status = acpi_ut_acquire_mutex (ACPI_MTX_EXECUTE);
+	if (ACPI_FAILURE (status)) {
+		ACPI_REPORT_ERROR (("Fatal - Could not acquire interpreter lock\n"));
+	}
+
 	return_ACPI_STATUS (status);
 }
 
@@ -95,17 +99,18 @@
  *          already executing
  *      7) About to invoke a user-installed opregion handler
  *
- *              TBD: should be a macro
- *
  ******************************************************************************/
 
 void
 acpi_ex_exit_interpreter (void)
 {
-	FUNCTION_TRACE ("Ex_exit_interpreter");
+	acpi_status             status;
+
 
+	ACPI_FUNCTION_TRACE ("Ex_exit_interpreter");
 
-	acpi_ut_release_mutex (ACPI_MTX_EXECUTE);
+
+	status = acpi_ut_release_mutex (ACPI_MTX_EXECUTE);
 
 	return_VOID;
 }
@@ -126,7 +131,7 @@
 	acpi_object_type        type)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if ((type > ACPI_TYPE_MAX && type < INTERNAL_TYPE_BEGIN) ||
@@ -159,7 +164,7 @@
 	acpi_walk_state         *walk_state)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -186,7 +191,8 @@
  *
  * FUNCTION:    Acpi_ex_acquire_global_lock
  *
- * PARAMETERS:  Rule            - Lock rule: Always_lock, Never_lock
+ * PARAMETERS:  Field_flags           - Flags with Lock rule:
+ *                                      Always_lock or Never_lock
  *
  * RETURN:      TRUE/FALSE indicating whether the lock was actually acquired
  *
@@ -198,25 +204,24 @@
 
 u8
 acpi_ex_acquire_global_lock (
-	u32                     rule)
+	u32                     field_flags)
 {
 	u8                      locked = FALSE;
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ex_acquire_global_lock");
+	ACPI_FUNCTION_TRACE ("Ex_acquire_global_lock");
 
 
-	/* Only attempt lock if the Rule says so */
+	/* Only attempt lock if the Always_lock bit is set */
 
-	if (rule == (u32) GLOCK_ALWAYS_LOCK) {
-		/* We should attempt to get the lock */
+	if (field_flags & AML_FIELD_LOCK_RULE_MASK) {
+		/* We should attempt to get the lock, wait forever */
 
-		status = acpi_ev_acquire_global_lock ();
+		status = acpi_ev_acquire_global_lock (ACPI_UINT32_MAX);
 		if (ACPI_SUCCESS (status)) {
 			locked = TRUE;
 		}
-
 		else {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Could not acquire Global Lock, %s\n",
 				acpi_format_exception (status)));
@@ -245,7 +250,7 @@
 	u8                      locked_by_me)
 {
 
-	FUNCTION_TRACE ("Ex_release_global_lock");
+	ACPI_FUNCTION_TRACE ("Ex_release_global_lock");
 
 
 	/* Only attempt unlock if the caller locked it */
@@ -256,7 +261,6 @@
 		acpi_ev_release_global_lock ();
 	}
 
-
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -280,13 +284,12 @@
 	u32                     num_digits = 0;
 
 
-	FUNCTION_TRACE ("Ex_digits_needed");
+	ACPI_FUNCTION_TRACE ("Ex_digits_needed");
 
 
 	if (base < 1) {
-		REPORT_ERROR (("Ex_digits_needed: Internal error - Invalid base\n"));
+		ACPI_REPORT_ERROR (("Ex_digits_needed: Internal error - Invalid base\n"));
 	}
-
 	else {
 		/*
 		 * acpi_integer is unsigned, which is why we don't worry about a '-'
@@ -325,7 +328,7 @@
 	} in;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	in.value = value;
@@ -358,7 +361,7 @@
 	u32                     id;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* swap to big-endian to get contiguous bits */
@@ -399,7 +402,7 @@
 	u32                     remainder;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	digits_needed = acpi_ex_digits_needed (value, 10);
diff -Nru a/drivers/acpi/hardware/Makefile b/drivers/acpi/hardware/Makefile
--- a/drivers/acpi/hardware/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/hardware/Makefile	Fri Mar 15 17:51:02 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/hardware/hwacpi.c b/drivers/acpi/hardware/hwacpi.c
--- a/drivers/acpi/hardware/hwacpi.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/hardware/hwacpi.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: hwacpi - ACPI Hardware Initialization/Mode Interface
- *              $Revision: 46 $
+ *              $Revision: 53 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_HARDWARE
-	 MODULE_NAME         ("hwacpi")
+	 ACPI_MODULE_NAME    ("hwacpi")
 
 
 /******************************************************************************
@@ -49,131 +49,28 @@
 acpi_hw_initialize (
 	void)
 {
-	acpi_status             status = AE_OK;
-	u32                     index;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Hw_initialize");
+	ACPI_FUNCTION_TRACE ("Hw_initialize");
 
 
 	/* We must have the ACPI tables by the time we get here */
 
 	if (!acpi_gbl_FADT) {
-		acpi_gbl_restore_acpi_chipset = FALSE;
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "No FADT!\n"));
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "A FADT is not loaded\n"));
 
 		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
 	}
 
-	/* Identify current ACPI/legacy mode   */
-
-	switch (acpi_gbl_system_flags & SYS_MODES_MASK) {
-	case (SYS_MODE_ACPI):
-
-		acpi_gbl_original_mode = SYS_MODE_ACPI;
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "System supports ACPI mode only.\n"));
-		break;
-
-
-	case (SYS_MODE_LEGACY):
-
-		acpi_gbl_original_mode = SYS_MODE_LEGACY;
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-			"Tables loaded from buffer, hardware assumed to support LEGACY mode only.\n"));
-		break;
-
-
-	case (SYS_MODE_ACPI | SYS_MODE_LEGACY):
-
-		if (acpi_hw_get_mode () == SYS_MODE_ACPI) {
-			acpi_gbl_original_mode = SYS_MODE_ACPI;
-		}
-		else {
-			acpi_gbl_original_mode = SYS_MODE_LEGACY;
-		}
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-			"System supports both ACPI and LEGACY modes.\n"));
+	/* Sanity check the FADT for valid values */
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-			"System is currently in %s mode.\n",
-			(acpi_gbl_original_mode == SYS_MODE_ACPI) ? "ACPI" : "LEGACY"));
-		break;
-	}
-
-
-	if (acpi_gbl_system_flags & SYS_MODE_ACPI) {
-		/* Target system supports ACPI mode */
-
-		/*
-		 * The purpose of this code is to save the initial state
-		 * of the ACPI event enable registers. An exit function will be
-		 * registered which will restore this state when the application
-		 * exits. The exit function will also clear all of the ACPI event
-		 * status bits prior to restoring the original mode.
-		 *
-		 * The location of the PM1a_evt_blk enable registers is defined as the
-		 * base of PM1a_evt_blk + DIV_2(PM1a_evt_blk_length). Since the spec further
-		 * fully defines the PM1a_evt_blk to be a total of 4 bytes, the offset
-		 * for the enable registers is always 2 from the base. It is hard
-		 * coded here. If this changes in the spec, this code will need to
-		 * be modified. The PM1b_evt_blk behaves as expected.
-		 */
-		acpi_gbl_pm1_enable_register_save = (u16) acpi_hw_register_read (
-				   ACPI_MTX_LOCK, PM1_EN);
-
-
-		/*
-		 * The GPEs behave similarly, except that the length of the register
-		 * block is not fixed, so the buffer must be allocated with malloc
-		 */
-		if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xgpe0blk.address) &&
-			acpi_gbl_FADT->gpe0blk_len) {
-			/* GPE0 specified in FADT  */
-
-			acpi_gbl_gpe0enable_register_save = ACPI_MEM_ALLOCATE (
-					   DIV_2 (acpi_gbl_FADT->gpe0blk_len));
-			if (!acpi_gbl_gpe0enable_register_save) {
-				return_ACPI_STATUS (AE_NO_MEMORY);
-			}
-
-			/* Save state of GPE0 enable bits */
-
-			for (index = 0; index < DIV_2 (acpi_gbl_FADT->gpe0blk_len); index++) {
-				acpi_gbl_gpe0enable_register_save[index] =
-					(u8) acpi_hw_register_read (ACPI_MTX_LOCK, GPE0_EN_BLOCK | index);
-			}
-		}
-
-		else {
-			acpi_gbl_gpe0enable_register_save = NULL;
-		}
-
-		if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address) &&
-			acpi_gbl_FADT->gpe1_blk_len) {
-			/* GPE1 defined */
-
-			acpi_gbl_gpe1_enable_register_save = ACPI_MEM_ALLOCATE (
-					   DIV_2 (acpi_gbl_FADT->gpe1_blk_len));
-			if (!acpi_gbl_gpe1_enable_register_save) {
-				return_ACPI_STATUS (AE_NO_MEMORY);
-			}
-
-			/* save state of GPE1 enable bits */
-
-			for (index = 0; index < DIV_2 (acpi_gbl_FADT->gpe1_blk_len); index++) {
-				acpi_gbl_gpe1_enable_register_save[index] =
-					(u8) acpi_hw_register_read (ACPI_MTX_LOCK, GPE1_EN_BLOCK | index);
-			}
-		}
-
-		else {
-			acpi_gbl_gpe1_enable_register_save = NULL;
-		}
+	status = acpi_ut_validate_fadt ();
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	return_ACPI_STATUS (status);
+	return_ACPI_STATUS (AE_OK);
 }
 
 
@@ -185,8 +82,7 @@
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Transitions the system into the requested mode or does nothing
- *              if the system is already in that mode.
+ * DESCRIPTION: Transitions the system into the requested mode.
  *
  ******************************************************************************/
 
@@ -198,17 +94,16 @@
 	acpi_status             status = AE_NO_HARDWARE_RESPONSE;
 
 
-	FUNCTION_TRACE ("Hw_set_mode");
+	ACPI_FUNCTION_TRACE ("Hw_set_mode");
 
 
-	if (mode == SYS_MODE_ACPI) {
+	if (mode == ACPI_SYS_MODE_ACPI) {
 		/* BIOS should have disabled ALL fixed and GP events */
 
 		acpi_os_write_port (acpi_gbl_FADT->smi_cmd, acpi_gbl_FADT->acpi_enable, 8);
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Attempting to enable ACPI mode\n"));
 	}
-
-	else if (mode == SYS_MODE_LEGACY) {
+	else if (mode == ACPI_SYS_MODE_LEGACY) {
 		/*
 		 * BIOS should clear all fixed status bits and restore fixed event
 		 * enable bits to default
@@ -248,73 +143,13 @@
 acpi_hw_get_mode (void)
 {
 
-	FUNCTION_TRACE ("Hw_get_mode");
+	ACPI_FUNCTION_TRACE ("Hw_get_mode");
 
 
-	if (acpi_hw_register_bit_access (ACPI_READ, ACPI_MTX_LOCK, SCI_EN)) {
-		return_VALUE (SYS_MODE_ACPI);
+	if (acpi_hw_bit_register_read (ACPI_BITREG_SCI_ENABLE, ACPI_MTX_LOCK)) {
+		return_VALUE (ACPI_SYS_MODE_ACPI);
 	}
 	else {
-		return_VALUE (SYS_MODE_LEGACY);
+		return_VALUE (ACPI_SYS_MODE_LEGACY);
 	}
 }
-
-
-/******************************************************************************
- *
- * FUNCTION:    Acpi_hw_get_mode_capabilities
- *
- * PARAMETERS:  none
- *
- * RETURN:      logical OR of SYS_MODE_ACPI and SYS_MODE_LEGACY determined at initial
- *              system state.
- *
- * DESCRIPTION: Returns capablities of system
- *
- ******************************************************************************/
-
-u32
-acpi_hw_get_mode_capabilities (void)
-{
-
-	FUNCTION_TRACE ("Hw_get_mode_capabilities");
-
-
-	if (!(acpi_gbl_system_flags & SYS_MODES_MASK)) {
-		if (acpi_hw_get_mode () == SYS_MODE_LEGACY) {
-			/*
-			 * Assume that if this call is being made, Acpi_init has been called
-			 * and ACPI support has been established by the presence of the
-			 * tables.  Therefore since we're in SYS_MODE_LEGACY, the system
-			 * must support both modes
-			 */
-			acpi_gbl_system_flags |= (SYS_MODE_ACPI | SYS_MODE_LEGACY);
-		}
-
-		else {
-			/* TBD: [Investigate] !!! this may be unsafe... */
-			/*
-			 * system is is ACPI mode, so try to switch back to LEGACY to see if
-			 * it is supported
-			 */
-			acpi_hw_set_mode (SYS_MODE_LEGACY);
-
-			if (acpi_hw_get_mode () == SYS_MODE_LEGACY) {
-				/* Now in SYS_MODE_LEGACY, so both are supported */
-
-				acpi_gbl_system_flags |= (SYS_MODE_ACPI | SYS_MODE_LEGACY);
-				acpi_hw_set_mode (SYS_MODE_ACPI);
-			}
-
-			else {
-				/* Still in SYS_MODE_ACPI so this must be an ACPI only system */
-
-				acpi_gbl_system_flags |= SYS_MODE_ACPI;
-			}
-		}
-	}
-
-	return_VALUE (acpi_gbl_system_flags & SYS_MODES_MASK);
-}
-
-
diff -Nru a/drivers/acpi/hardware/hwgpe.c b/drivers/acpi/hardware/hwgpe.c
--- a/drivers/acpi/hardware/hwgpe.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/hardware/hwgpe.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Module Name: hwgpe - Low level GPE enable/disable/clear functions
- *              $Revision: 35 $
+ *              $Revision: 39 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,27 @@
 #include "acevents.h"
 
 #define _COMPONENT          ACPI_HARDWARE
-	 MODULE_NAME         ("hwgpe")
+	 ACPI_MODULE_NAME    ("hwgpe")
+
+
+/******************************************************************************
+ *
+ * FUNCTION:    Acpi_hw_get_gpe_bit_mask
+ *
+ * PARAMETERS:  Gpe_number      - The GPE
+ *
+ * RETURN:      Gpe register bitmask for this gpe level
+ *
+ * DESCRIPTION: Get the bitmask for this GPE
+ *
+ ******************************************************************************/
+
+u32
+acpi_hw_get_gpe_bit_mask (
+	u32                     gpe_number)
+{
+	return (acpi_gbl_gpe_number_info [acpi_ev_get_gpe_number_index (gpe_number)].bit_mask);
+}
 
 
 /******************************************************************************
@@ -54,29 +74,28 @@
 	u32                     bit_mask;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	/*
-	 * Translate GPE number to index into global registers array.
-	 */
-	register_index = acpi_gbl_gpe_valid[gpe_number];
+	/* Translate GPE number to index into global registers array. */
 
-	/*
-	 * Figure out the bit offset for this GPE within the target register.
-	 */
-	bit_mask = acpi_gbl_decode_to8bit [MOD_8 (gpe_number)];
+	register_index = acpi_ev_get_gpe_register_index (gpe_number);
+
+	/* Get the register bitmask for this GPE */
+
+	bit_mask = acpi_hw_get_gpe_bit_mask (gpe_number);
 
 	/*
 	 * Read the current value of the register, set the appropriate bit
 	 * to enable the GPE, and write out the new register.
 	 */
 	in_byte = 0;
-	acpi_os_read_port (acpi_gbl_gpe_registers[register_index].enable_addr, &in_byte, 8);
-	acpi_os_write_port (acpi_gbl_gpe_registers[register_index].enable_addr,
-			   (in_byte | bit_mask), 8);
+	acpi_os_read_port (acpi_gbl_gpe_register_info[register_index].enable_addr, &in_byte, 8);
+	acpi_os_write_port (acpi_gbl_gpe_register_info[register_index].enable_addr,
+			  (in_byte | bit_mask), 8);
 }
 
+
 /******************************************************************************
  *
  * FUNCTION:    Acpi_hw_enable_gpe_for_wakeup
@@ -98,25 +117,24 @@
 	u32                     bit_mask;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	/*
-	 * Translate GPE number to index into global registers array.
-	 */
-	register_index = acpi_gbl_gpe_valid[gpe_number];
+	/* Translate GPE number to index into global registers array. */
 
-	/*
-	 * Figure out the bit offset for this GPE within the target register.
-	 */
-	bit_mask = acpi_gbl_decode_to8bit [MOD_8 (gpe_number)];
+	register_index = acpi_ev_get_gpe_register_index (gpe_number);
+
+	/* Get the register bitmask for this GPE */
+
+	bit_mask = acpi_hw_get_gpe_bit_mask (gpe_number);
 
 	/*
 	 * Set the bit so we will not disable this when sleeping
 	 */
-	acpi_gbl_gpe_registers[register_index].wake_enable |= bit_mask;
+	acpi_gbl_gpe_register_info[register_index].wake_enable |= bit_mask;
 }
 
+
 /******************************************************************************
  *
  * FUNCTION:    Acpi_hw_disable_gpe
@@ -138,31 +156,30 @@
 	u32                     bit_mask;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	/*
-	 * Translate GPE number to index into global registers array.
-	 */
-	register_index = acpi_gbl_gpe_valid[gpe_number];
+	/* Translate GPE number to index into global registers array. */
 
-	/*
-	 * Figure out the bit offset for this GPE within the target register.
-	 */
-	bit_mask = acpi_gbl_decode_to8bit [MOD_8 (gpe_number)];
+	register_index = acpi_ev_get_gpe_register_index (gpe_number);
+
+	/* Get the register bitmask for this GPE */
+
+	bit_mask = acpi_hw_get_gpe_bit_mask (gpe_number);
 
 	/*
 	 * Read the current value of the register, clear the appropriate bit,
 	 * and write out the new register value to disable the GPE.
 	 */
 	in_byte = 0;
-	acpi_os_read_port (acpi_gbl_gpe_registers[register_index].enable_addr, &in_byte, 8);
-	acpi_os_write_port (acpi_gbl_gpe_registers[register_index].enable_addr,
+	acpi_os_read_port (acpi_gbl_gpe_register_info[register_index].enable_addr, &in_byte, 8);
+	acpi_os_write_port (acpi_gbl_gpe_register_info[register_index].enable_addr,
 			 (in_byte & ~bit_mask), 8);
 
 	acpi_hw_disable_gpe_for_wakeup(gpe_number);
 }
 
+
 /******************************************************************************
  *
  * FUNCTION:    Acpi_hw_disable_gpe_for_wakeup
@@ -184,25 +201,24 @@
 	u32                     bit_mask;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	/*
-	 * Translate GPE number to index into global registers array.
-	 */
-	register_index = acpi_gbl_gpe_valid[gpe_number];
+	/* Translate GPE number to index into global registers array. */
 
-	/*
-	 * Figure out the bit offset for this GPE within the target register.
-	 */
-	bit_mask = acpi_gbl_decode_to8bit [MOD_8 (gpe_number)];
+	register_index = acpi_ev_get_gpe_register_index (gpe_number);
+
+	/* Get the register bitmask for this GPE */
+
+	bit_mask = acpi_hw_get_gpe_bit_mask (gpe_number);
 
 	/*
 	 * Clear the bit so we will disable this when sleeping
 	 */
-	acpi_gbl_gpe_registers[register_index].wake_enable &= ~bit_mask;
+	acpi_gbl_gpe_register_info[register_index].wake_enable &= ~bit_mask;
 }
 
+
 /******************************************************************************
  *
  * FUNCTION:    Acpi_hw_clear_gpe
@@ -223,24 +239,22 @@
 	u32                     bit_mask;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	/*
-	 * Translate GPE number to index into global registers array.
-	 */
-	register_index = acpi_gbl_gpe_valid[gpe_number];
+	/* Translate GPE number to index into global registers array. */
 
-	/*
-	 * Figure out the bit offset for this GPE within the target register.
-	 */
-	bit_mask = acpi_gbl_decode_to8bit [MOD_8 (gpe_number)];
+	register_index = acpi_ev_get_gpe_register_index (gpe_number);
+
+	/* Get the register bitmask for this GPE */
+
+	bit_mask = acpi_hw_get_gpe_bit_mask (gpe_number);
 
 	/*
 	 * Write a one to the appropriate bit in the status register to
 	 * clear this GPE.
 	 */
-	acpi_os_write_port (acpi_gbl_gpe_registers[register_index].status_addr, bit_mask, 8);
+	acpi_os_write_port (acpi_gbl_gpe_register_info[register_index].status_addr, bit_mask, 8);
 }
 
 
@@ -264,9 +278,10 @@
 	u32                     in_byte = 0;
 	u32                     register_index = 0;
 	u32                     bit_mask = 0;
+	ACPI_GPE_REGISTER_INFO  *gpe_register_info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (!event_status) {
@@ -275,42 +290,39 @@
 
 	(*event_status) = 0;
 
-	/*
-	 * Translate GPE number to index into global registers array.
-	 */
-	register_index = acpi_gbl_gpe_valid[gpe_number];
+	/* Translate GPE number to index into global registers array. */
 
-	/*
-	 * Figure out the bit offset for this GPE within the target register.
-	 */
-	bit_mask = acpi_gbl_decode_to8bit [MOD_8 (gpe_number)];
+	register_index = acpi_ev_get_gpe_register_index (gpe_number);
+	gpe_register_info = &acpi_gbl_gpe_register_info[register_index];
+
+	/* Get the register bitmask for this GPE */
+
+	bit_mask = acpi_hw_get_gpe_bit_mask (gpe_number);
+
+	/* GPE Enabled? */
 
-	/*
-	 * Enabled?:
-	 */
 	in_byte = 0;
-	acpi_os_read_port (acpi_gbl_gpe_registers[register_index].enable_addr, &in_byte, 8);
+	acpi_os_read_port (gpe_register_info->enable_addr, &in_byte, 8);
 	if (bit_mask & in_byte) {
 		(*event_status) |= ACPI_EVENT_FLAG_ENABLED;
 	}
 
-	/*
-	 * Enabled for wake?:
-	 */
-	if (bit_mask & acpi_gbl_gpe_registers[register_index].wake_enable) {
+	/* GPE Enabled for wake? */
+
+	if (bit_mask & gpe_register_info->wake_enable) {
 		(*event_status) |= ACPI_EVENT_FLAG_WAKE_ENABLED;
 	}
 
-	/*
-	 * Set?
-	 */
+	/* GPE active (set)? */
+
 	in_byte = 0;
-	acpi_os_read_port (acpi_gbl_gpe_registers[register_index].status_addr, &in_byte, 8);
+	acpi_os_read_port (gpe_register_info->status_addr, &in_byte, 8);
 	if (bit_mask & in_byte) {
 		(*event_status) |= ACPI_EVENT_FLAG_SET;
 	}
 }
 
+
 /******************************************************************************
  *
  * FUNCTION:    Acpi_hw_disable_non_wakeup_gpes
@@ -321,7 +333,7 @@
  *
  * DESCRIPTION: Disable all non-wakeup GPEs
  *              Call with interrupts disabled. The interrupt handler also
- *              modifies Acpi_gbl_Gpe_registers[i].Enable, so it should not be
+ *              modifies Acpi_gbl_Gpe_register_info[i].Enable, so it should not be
  *              given the chance to run until after non-wake GPEs are
  *              re-enabled.
  *
@@ -332,25 +344,31 @@
 	void)
 {
 	u32                     i;
+	ACPI_GPE_REGISTER_INFO  *gpe_register_info;
+
+
+	ACPI_FUNCTION_ENTRY ();
 
-	FUNCTION_ENTRY ();
 
 	for (i = 0; i < acpi_gbl_gpe_register_count; i++) {
+		gpe_register_info = &acpi_gbl_gpe_register_info[i];
+
 		/*
 		 * Read the enabled status of all GPEs. We
 		 * will be using it to restore all the GPEs later.
 		 */
-		acpi_os_read_port (acpi_gbl_gpe_registers[i].enable_addr,
-				&acpi_gbl_gpe_registers[i].enable, 8);
+		acpi_os_read_port (gpe_register_info->enable_addr,
+				  &gpe_register_info->enable, 8);
 
 		/*
-		 * Disable all GPEs but wakeup GPEs.
+		 * Disable all GPEs except wakeup GPEs.
 		 */
-		acpi_os_write_port(acpi_gbl_gpe_registers[i].enable_addr,
-				acpi_gbl_gpe_registers[i].wake_enable, 8);
+		acpi_os_write_port(gpe_register_info->enable_addr,
+				  gpe_register_info->wake_enable, 8);
 	}
 }
 
+
 /******************************************************************************
  *
  * FUNCTION:    Acpi_hw_enable_non_wakeup_gpes
@@ -368,15 +386,20 @@
 	void)
 {
 	u32                     i;
+	ACPI_GPE_REGISTER_INFO  *gpe_register_info;
+
+
+	ACPI_FUNCTION_ENTRY ();
 
-	FUNCTION_ENTRY ();
 
 	for (i = 0; i < acpi_gbl_gpe_register_count; i++) {
+		gpe_register_info = &acpi_gbl_gpe_register_info[i];
+
 		/*
 		 * We previously stored the enabled status of all GPEs.
 		 * Blast them back in.
 		 */
-		acpi_os_write_port(acpi_gbl_gpe_registers[i].enable_addr,
-				acpi_gbl_gpe_registers[i].enable, 8);
+		acpi_os_write_port(gpe_register_info->enable_addr,
+				  gpe_register_info->enable, 8);
 	}
 }
diff -Nru a/drivers/acpi/hardware/hwregs.c b/drivers/acpi/hardware/hwregs.c
--- a/drivers/acpi/hardware/hwregs.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/hardware/hwregs.c	Fri Mar 15 17:51:02 2002
@@ -3,12 +3,12 @@
  *
  * Module Name: hwregs - Read/write access functions for the various ACPI
  *                       control and status registers.
- *              $Revision: 110 $
+ *              $Revision: 120 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,36 +31,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_HARDWARE
-	 MODULE_NAME         ("hwregs")
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_hw_get_bit_shift
- *
- * PARAMETERS:  Mask            - Input mask to determine bit shift from.
- *                                Must have at least 1 bit set.
- *
- * RETURN:      Bit location of the lsb of the mask
- *
- * DESCRIPTION: Returns the bit number for the low order bit that's set.
- *
- ******************************************************************************/
-
-u32
-acpi_hw_get_bit_shift (
-	u32                     mask)
-{
-	u32                     shift;
-
-
-	FUNCTION_TRACE ("Hw_get_bit_shift");
-
-
-	for (shift = 0; ((mask >> shift) & 1) == 0; shift++) { ; }
-
-	return_VALUE (shift);
-}
+	 ACPI_MODULE_NAME    ("hwregs")
 
 
 /*******************************************************************************
@@ -78,89 +49,83 @@
 void
 acpi_hw_clear_acpi_status (void)
 {
-	u16                     gpe_length;
-	u16                     index;
+	NATIVE_UINT             i;
+	NATIVE_UINT             gpe_block;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Hw_clear_acpi_status");
+	ACPI_FUNCTION_TRACE ("Hw_clear_acpi_status");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %04X\n",
-		ALL_FIXED_STS_BITS,
+		ACPI_BITMASK_ALL_FIXED_STATUS,
 		(u16) ACPI_GET_ADDRESS (acpi_gbl_FADT->Xpm1a_evt_blk.address)));
 
 
-	acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE);
+	if (ACPI_FAILURE (status)) {
+		return_VOID;
+	}
 
-	acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, PM1_STS, ALL_FIXED_STS_BITS);
+	acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
+			ACPI_BITMASK_ALL_FIXED_STATUS);
 
+	/* Clear the fixed events */
 
 	if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xpm1b_evt_blk.address)) {
 		acpi_os_write_port ((ACPI_IO_ADDRESS)
 			ACPI_GET_ADDRESS (acpi_gbl_FADT->Xpm1b_evt_blk.address),
-			ALL_FIXED_STS_BITS, 16);
-	}
-
-	/* now clear the GPE Bits */
-
-	if (acpi_gbl_FADT->gpe0blk_len) {
-		gpe_length = (u16) DIV_2 (acpi_gbl_FADT->gpe0blk_len);
-
-		for (index = 0; index < gpe_length; index++) {
-			acpi_os_write_port ((ACPI_IO_ADDRESS) (
-				ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe0blk.address) + index),
-					0xFF, 8);
-		}
+			ACPI_BITMASK_ALL_FIXED_STATUS, 16);
 	}
 
-	if (acpi_gbl_FADT->gpe1_blk_len) {
-		gpe_length = (u16) DIV_2 (acpi_gbl_FADT->gpe1_blk_len);
+	/* Clear the GPE Bits */
 
-		for (index = 0; index < gpe_length; index++) {
-			acpi_os_write_port ((ACPI_IO_ADDRESS) (
-				ACPI_GET_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address) + index),
+	for (gpe_block = 0; gpe_block < ACPI_MAX_GPE_BLOCKS; gpe_block++) {
+		for (i = 0; i < acpi_gbl_gpe_block_info[gpe_block].register_count; i++) {
+			acpi_os_write_port ((ACPI_IO_ADDRESS)
+				(acpi_gbl_gpe_block_info[gpe_block].block_address + i),
 				0xFF, 8);
 		}
 	}
 
-	acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
 	return_VOID;
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_hw_obtain_sleep_type_register_data
+ * FUNCTION:    Acpi_hw_get_sleep_type_data
  *
- * PARAMETERS:  Sleep_state       - Numeric state requested
- *              *Slp_Typ_a         - Pointer to byte to receive SLP_TYPa value
- *              *Slp_Typ_b         - Pointer to byte to receive SLP_TYPb value
+ * PARAMETERS:  Sleep_state         - Numeric sleep state
+ *              *Sleep_type_a        - Where SLP_TYPa is returned
+ *              *Sleep_type_b        - Where SLP_TYPb is returned
  *
  * RETURN:      Status - ACPI status
  *
- * DESCRIPTION: Acpi_hw_obtain_sleep_type_register_data() obtains the SLP_TYP and
- *              SLP_TYPb values for the sleep state requested.
+ * DESCRIPTION: Obtain the SLP_TYPa and SLP_TYPb values for the requested sleep
+ *              state.
  *
  ******************************************************************************/
 
 acpi_status
-acpi_hw_obtain_sleep_type_register_data (
+acpi_hw_get_sleep_type_data (
 	u8                      sleep_state,
-	u8                      *slp_typ_a,
-	u8                      *slp_typ_b)
+	u8                      *sleep_type_a,
+	u8                      *sleep_type_b)
 {
 	acpi_status             status = AE_OK;
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE ("Hw_obtain_sleep_type_register_data");
+	ACPI_FUNCTION_TRACE ("Hw_get_sleep_type_data");
 
 
 	/*
 	 *  Validate parameters
 	 */
 	if ((sleep_state > ACPI_S_STATES_MAX) ||
-		!slp_typ_a || !slp_typ_b) {
+		!sleep_type_a || !sleep_type_b) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
@@ -174,7 +139,7 @@
 	}
 
 	if (!obj_desc) {
-		REPORT_ERROR (("Missing Sleep State object\n"));
+		ACPI_REPORT_ERROR (("Missing Sleep State object\n"));
 		return_ACPI_STATUS (AE_NOT_EXIST);
 	}
 
@@ -185,386 +150,251 @@
 	 */
 
 	/* Even though Acpi_evaluate_object resolves package references,
-	 * Ns_evaluate dpesn't. So, we do it here.
+	 * Ns_evaluate doesn't. So, we do it here.
 	 */
 	status = acpi_ut_resolve_package_references(obj_desc);
 
 	if (obj_desc->package.count < 2) {
 		/* Must have at least two elements */
 
-		REPORT_ERROR (("Sleep State package does not have at least two elements\n"));
-		status = AE_ERROR;
+		ACPI_REPORT_ERROR (("Sleep State package does not have at least two elements\n"));
+		status = AE_AML_NO_OPERAND;
 	}
-
-	else if (((obj_desc->package.elements[0])->common.type !=
-			 ACPI_TYPE_INTEGER) ||
-			 ((obj_desc->package.elements[1])->common.type !=
-				ACPI_TYPE_INTEGER)) {
+	else if (((obj_desc->package.elements[0])->common.type != ACPI_TYPE_INTEGER) ||
+			 ((obj_desc->package.elements[1])->common.type != ACPI_TYPE_INTEGER)) {
 		/* Must have two  */
 
-		REPORT_ERROR (("Sleep State package elements are not both of type Number\n"));
-		status = AE_ERROR;
+		ACPI_REPORT_ERROR (("Sleep State package elements are not both of type Number\n"));
+		status = AE_AML_OPERAND_TYPE;
 	}
-
 	else {
 		/*
 		 *  Valid _Sx_ package size, type, and value
 		 */
-		*slp_typ_a = (u8) (obj_desc->package.elements[0])->integer.value;
-
-		*slp_typ_b = (u8) (obj_desc->package.elements[1])->integer.value;
+		*sleep_type_a = (u8) (obj_desc->package.elements[0])->integer.value;
+		*sleep_type_b = (u8) (obj_desc->package.elements[1])->integer.value;
 	}
 
-
 	if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Bad Sleep object %p type %X\n",
 			obj_desc, obj_desc->common.type));
 	}
 
 	acpi_ut_remove_reference (obj_desc);
-
 	return_ACPI_STATUS (status);
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_hw_register_bit_access
+ * FUNCTION:    Acpi_hw_get_register_bit_mask
+ *
+ * PARAMETERS:  Register_id     - index of ACPI Register to access
+ *
+ * RETURN:      The bit mask to be used when accessing the register
  *
- * PARAMETERS:  Read_write      - Either ACPI_READ or ACPI_WRITE.
+ * DESCRIPTION: Map Register_id into a register bit mask.
+ *
+ ******************************************************************************/
+
+ACPI_BIT_REGISTER_INFO *
+acpi_hw_get_bit_register_info (
+	u32                     register_id)
+{
+	ACPI_FUNCTION_NAME ("Hw_get_bit_register_info");
+
+
+	if (register_id > ACPI_BITREG_MAX) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid Bit_register ID: %X\n", register_id));
+		return (NULL);
+	}
+
+	return (&acpi_gbl_bit_register_info[register_id]);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_hw_bit_register_read
+ *
+ * PARAMETERS:  Register_id     - index of ACPI Register to access
  *              Use_lock        - Lock the hardware
- *              Register_id     - index of ACPI Register to access
- *              Value           - (only used on write) value to write to the
- *                                Register.  Shifted all the way right.
  *
- * RETURN:      Value written to or read from specified Register.  This value
- *              is shifted all the way right.
+ * RETURN:      Value is read from specified Register.  Value returned is
+ *              normalized to bit0 (is shifted all the way right)
  *
- * DESCRIPTION: Generic ACPI Register read/write function.
+ * DESCRIPTION: ACPI Bit_register read function.
  *
  ******************************************************************************/
 
 u32
-acpi_hw_register_bit_access (
-	NATIVE_UINT             read_write,
-	u8                      use_lock,
+acpi_hw_bit_register_read (
 	u32                     register_id,
-	...)                    /* Value (only used on write) */
+	u32                     flags)
 {
 	u32                     register_value = 0;
-	u32                     mask = 0;
-	u32                     value = 0;
-	va_list                 marker;
+	ACPI_BIT_REGISTER_INFO  *bit_reg_info;
 
 
-	FUNCTION_TRACE ("Hw_register_bit_access");
+	ACPI_FUNCTION_TRACE ("Hw_bit_register_read");
 
 
-	if (read_write == ACPI_WRITE) {
-		va_start (marker, register_id);
-		value = va_arg (marker, u32);
-		va_end (marker);
+	if (flags & ACPI_MTX_LOCK) {
+		if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE))) {
+			return_VALUE (0);
+		}
 	}
 
-	if (ACPI_MTX_LOCK == use_lock) {
-		acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE);
+	/* Get the info structure corresponding to the requested ACPI Register */
+
+	bit_reg_info = acpi_hw_get_bit_register_info (register_id);
+	if (!bit_reg_info) {
+		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	/*
-	 * Decode the Register ID
-	 * Register id = Register block id | bit id
-	 *
-	 * Check bit id to fine locate Register offset.
-	 * Check Mask to determine Register offset, and then read-write.
-	 */
-	switch (REGISTER_BLOCK_ID (register_id)) {
-	case PM1_STS:
+	register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, bit_reg_info->parent_register);
 
-		switch (register_id) {
-		case TMR_STS:
-			mask = TMR_STS_MASK;
-			break;
-
-		case BM_STS:
-			mask = BM_STS_MASK;
-			break;
-
-		case GBL_STS:
-			mask = GBL_STS_MASK;
-			break;
-
-		case PWRBTN_STS:
-			mask = PWRBTN_STS_MASK;
-			break;
-
-		case SLPBTN_STS:
-			mask = SLPBTN_STS_MASK;
-			break;
-
-		case RTC_STS:
-			mask = RTC_STS_MASK;
-			break;
-
-		case WAK_STS:
-			mask = WAK_STS_MASK;
-			break;
-
-		default:
-			mask = 0;
-			break;
-		}
+	if (flags & ACPI_MTX_LOCK) {
+		(void) acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
+	}
 
-		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_STS);
+	/* Normalize the value that was read */
 
-		if (read_write == ACPI_WRITE) {
-			/*
-			 * Status Registers are different from the rest.  Clear by
-			 * writing 1, writing 0 has no effect.  So, the only relevent
-			 * information is the single bit we're interested in, all
-			 * others should be written as 0 so they will be left
-			 * unchanged
-			 */
-			value <<= acpi_hw_get_bit_shift (mask);
-			value &= mask;
-
-			if (value) {
-				acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, PM1_STS,
-					(u16) value);
-				register_value = 0;
-			}
-		}
+	register_value = ((register_value & bit_reg_info->access_bit_mask) >> bit_reg_info->bit_position);
 
-		break;
+	ACPI_DEBUG_PRINT ((ACPI_DB_IO, "ACPI Register_read: got %X\n", register_value));
+	return_VALUE (register_value);
+}
 
 
-	case PM1_EN:
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_hw_bit_register_write
+ *
+ * PARAMETERS:  Register_id     - ID of ACPI Bit_register to access
+ *              Value           - (only used on write) value to write to the
+ *                                Register, NOT pre-normalized to the bit pos.
+ *              Flags           - Lock the hardware or not
+ *
+ * RETURN:      Value written to from specified Register.  This value
+ *              is shifted all the way right.
+ *
+ * DESCRIPTION: ACPI Bit Register write function.
+ *
+ ******************************************************************************/
 
-		switch (register_id) {
-		case TMR_EN:
-			mask = TMR_EN_MASK;
-			break;
-
-		case GBL_EN:
-			mask = GBL_EN_MASK;
-			break;
-
-		case PWRBTN_EN:
-			mask = PWRBTN_EN_MASK;
-			break;
-
-		case SLPBTN_EN:
-			mask = SLPBTN_EN_MASK;
-			break;
-
-		case RTC_EN:
-			mask = RTC_EN_MASK;
-			break;
-
-		default:
-			mask = 0;
-			break;
-		}
+u32
+acpi_hw_bit_register_write (
+	u32                     register_id,
+	u32                     value,
+	u32                     flags)
+{
+	u32                     register_value = 0;
+	ACPI_BIT_REGISTER_INFO  *bit_reg_info;
 
-		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_EN);
 
-		if (read_write == ACPI_WRITE) {
-			register_value &= ~mask;
-			value          <<= acpi_hw_get_bit_shift (mask);
-			value          &= mask;
-			register_value |= value;
+	ACPI_FUNCTION_TRACE_U32 ("Hw_bit_register_write", register_id);
 
-			acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, PM1_EN, (u16) register_value);
+
+	if (flags & ACPI_MTX_LOCK) {
+		if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE))) {
+			return_VALUE (0);
 		}
+	}
 
-		break;
+	/* Get the info structure corresponding to the requested ACPI Register */
 
+	bit_reg_info = acpi_hw_get_bit_register_info (register_id);
+	if (!bit_reg_info) {
+		return_ACPI_STATUS (AE_BAD_PARAMETER);
+	}
 
-	case PM1_CONTROL:
+	/* Always do a register read first so we can insert the new bits  */
 
-		switch (register_id) {
-		case SCI_EN:
-			mask = SCI_EN_MASK;
-			break;
-
-		case BM_RLD:
-			mask = BM_RLD_MASK;
-			break;
-
-		case GBL_RLS:
-			mask = GBL_RLS_MASK;
-			break;
-
-		case SLP_TYPE_A:
-		case SLP_TYPE_B:
-			mask = SLP_TYPE_X_MASK;
-			break;
-
-		case SLP_EN:
-			mask = SLP_EN_MASK;
-			break;
-
-		default:
-			mask = 0;
-			break;
-		}
+	register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, bit_reg_info->parent_register);
 
+	/*
+	 * Decode the Register ID
+	 * Register id = Register block id | bit id
+	 *
+	 * Check bit id to fine locate Register offset.
+	 * Check Mask to determine Register offset, and then read-write.
+	 */
+	switch (bit_reg_info->parent_register) {
+	case ACPI_REGISTER_PM1_STATUS:
 
 		/*
-		 * Read the PM1 Control register.
-		 * Note that at this level, the fact that there are actually TWO
-		 * registers (A and B) and that B may not exist, are abstracted.
+		 * Status Registers are different from the rest.  Clear by
+		 * writing 1, writing 0 has no effect.  So, the only relevent
+		 * information is the single bit we're interested in, all others should
+		 * be written as 0 so they will be left unchanged
 		 */
-		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM1_CONTROL);
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM1 control: Read %X\n", register_value));
-
-		if (read_write == ACPI_WRITE) {
-			register_value &= ~mask;
-			value          <<= acpi_hw_get_bit_shift (mask);
-			value          &= mask;
-			register_value |= value;
-
-			/*
-			 * SLP_TYPE_x Registers are written differently
-			 * than any other control Registers with
-			 * respect to A and B Registers.  The value
-			 * for A may be different than the value for B
-			 *
-			 * Therefore, pass the Register_id, not just generic PM1_CONTROL,
-			 * because we need to do different things. Yuck.
-			 */
-			acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, register_id,
-					(u16) register_value);
+		value = ACPI_REGISTER_PREPARE_BITS (value, bit_reg_info->bit_position, bit_reg_info->access_bit_mask);
+		if (value) {
+			acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_STATUS,
+				(u16) value);
+			register_value = 0;
 		}
 		break;
 
 
-	case PM2_CONTROL:
-
-		switch (register_id) {
-		case ARB_DIS:
-			mask = ARB_DIS_MASK;
-			break;
-
-		default:
-			mask = 0;
-			break;
-		}
-
-		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, PM2_CONTROL);
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM2 control: Read %X from %8.8X%8.8X\n",
-			register_value, HIDWORD(acpi_gbl_FADT->Xpm2_cnt_blk.address),
-			LODWORD(acpi_gbl_FADT->Xpm2_cnt_blk.address)));
+	case ACPI_REGISTER_PM1_ENABLE:
 
-		if (read_write == ACPI_WRITE) {
-			register_value &= ~mask;
-			value          <<= acpi_hw_get_bit_shift (mask);
-			value          &= mask;
-			register_value |= value;
-
-			ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
-				register_value,
-				HIDWORD(acpi_gbl_FADT->Xpm2_cnt_blk.address),
-				LODWORD(acpi_gbl_FADT->Xpm2_cnt_blk.address)));
+		ACPI_REGISTER_INSERT_VALUE (register_value, bit_reg_info->bit_position, bit_reg_info->access_bit_mask, value);
 
-			acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK,
-					   PM2_CONTROL, (u8) (register_value));
-		}
+		acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM1_ENABLE, (u16) register_value);
 		break;
 
 
-	case PM_TIMER:
+	case ACPI_REGISTER_PM1_CONTROL:
 
-		mask = TMR_VAL_MASK;
-		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK,
-				 PM_TIMER);
-		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM_TIMER: Read %X from %8.8X%8.8X\n",
-			register_value,
-			HIDWORD(acpi_gbl_FADT->Xpm_tmr_blk.address),
-			LODWORD(acpi_gbl_FADT->Xpm_tmr_blk.address)));
+		/*
+		 * Read the PM1 Control register.
+		 * Note that at this level, the fact that there are actually TWO
+		 * registers (A and B - and that B may not exist) is abstracted.
+		 */
+		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM1 control: Read %X\n", register_value));
 
+		ACPI_REGISTER_INSERT_VALUE (register_value, bit_reg_info->bit_position, bit_reg_info->access_bit_mask, value);
+
+		acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, register_id,
+				(u16) register_value);
 		break;
 
 
-	case GPE1_EN_BLOCK:
-	case GPE1_STS_BLOCK:
-	case GPE0_EN_BLOCK:
-	case GPE0_STS_BLOCK:
-
-		/* Determine the bit to be accessed
-		 *
-		 *  (u32) Register_id:
-		 *      31      24       16       8        0
-		 *      +--------+--------+--------+--------+
-		 *      |  gpe_block_id   |  gpe_bit_number |
-		 *      +--------+--------+--------+--------+
-		 *
-		 *     gpe_block_id is one of GPE[01]_EN_BLOCK and GPE[01]_STS_BLOCK
-		 *     gpe_bit_number is relative from the gpe_block (0x00~0xFF)
-		 */
-		mask = REGISTER_BIT_ID(register_id); /* gpe_bit_number */
-		register_id = REGISTER_BLOCK_ID(register_id) | (mask >> 3);
-		mask = acpi_gbl_decode_to8bit [mask % 8];
+	case ACPI_REGISTER_PM2_CONTROL:
 
-		/*
-		 * The base address of the GPE 0 Register Block
-		 * Plus 1/2 the length of the GPE 0 Register Block
-		 * The enable Register is the Register following the Status Register
-		 * and each Register is defined as 1/2 of the total Register Block
-		 */
-
-		/*
-		 * This sets the bit within Enable_bit that needs to be written to
-		 * the Register indicated in Mask to a 1, all others are 0
-		 */
+		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, ACPI_REGISTER_PM2_CONTROL);
 
-		/* Now get the current Enable Bits in the selected Reg */
+		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "PM2 control: Read %X from %8.8X%8.8X\n",
+			register_value, ACPI_HIDWORD (acpi_gbl_FADT->Xpm2_cnt_blk.address),
+			ACPI_LODWORD (acpi_gbl_FADT->Xpm2_cnt_blk.address)));
 
-		register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK, register_id);
-		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "GPE Enable bits: Read %X from %X\n",
-			register_value, register_id));
-
-		if (read_write == ACPI_WRITE) {
-			register_value &= ~mask;
-			value          <<= acpi_hw_get_bit_shift (mask);
-			value          &= mask;
-			register_value |= value;
-
-			/*
-			 * This write will put the Action state into the General Purpose
-			 * Enable Register indexed by the value in Mask
-			 */
-			ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %04X\n",
-				register_value, register_id));
-			acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK, register_id,
-				(u8) register_value);
-			register_value = acpi_hw_register_read (ACPI_MTX_DO_NOT_LOCK,
-					   register_id);
-		}
-		break;
+		ACPI_REGISTER_INSERT_VALUE (register_value, bit_reg_info->bit_position, bit_reg_info->access_bit_mask, value);
 
+		ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
+			register_value,
+			ACPI_HIDWORD (acpi_gbl_FADT->Xpm2_cnt_blk.address),
+			ACPI_LODWORD (acpi_gbl_FADT->Xpm2_cnt_blk.address)));
 
-	case SMI_CMD_BLOCK:
-	case PROCESSOR_BLOCK:
+		acpi_hw_register_write (ACPI_MTX_DO_NOT_LOCK,
+				   ACPI_REGISTER_PM2_CONTROL, (u8) (register_value));
+		break;
 
-		/* Not used by any callers at this time - therefore, not implemented */
 
 	default:
-
-		mask = 0;
 		break;
 	}
 
-	if (ACPI_MTX_LOCK == use_lock) {
-		acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
+	if (flags & ACPI_MTX_LOCK) {
+		(void) acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
 	}
 
+	/* Normalize the value that was read */
 
-	register_value &= mask;
-	register_value >>= acpi_hw_get_bit_shift (mask);
+	register_value = ((register_value & bit_reg_info->access_bit_mask) >> bit_reg_info->bit_position);
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_IO, "Register I/O: returning %X\n", register_value));
+	ACPI_DEBUG_PRINT ((ACPI_DB_IO, "ACPI Register_write actual %X\n", register_value));
 	return_VALUE (register_value);
 }
 
@@ -592,79 +422,50 @@
 	u32                     bank_offset;
 
 
-	FUNCTION_TRACE ("Hw_register_read");
+	ACPI_FUNCTION_TRACE ("Hw_register_read");
 
 
 	if (ACPI_MTX_LOCK == use_lock) {
-		acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE);
+		if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE))) {
+			return_VALUE (0);
+		}
 	}
 
-
-	switch (REGISTER_BLOCK_ID(register_id)) {
-	case PM1_STS: /* 16-bit access */
+	switch (register_id) {
+	case ACPI_REGISTER_PM1_STATUS:           /* 16-bit access */
 
 		value =  acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1a_evt_blk, 0);
 		value |= acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1b_evt_blk, 0);
 		break;
 
 
-	case PM1_EN: /* 16-bit access*/
+	case ACPI_REGISTER_PM1_ENABLE:           /* 16-bit access*/
 
-		bank_offset = DIV_2 (acpi_gbl_FADT->pm1_evt_len);
+		bank_offset = ACPI_DIV_2 (acpi_gbl_FADT->pm1_evt_len);
 		value =  acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1a_evt_blk, bank_offset);
 		value |= acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1b_evt_blk, bank_offset);
 		break;
 
 
-	case PM1_CONTROL: /* 16-bit access */
+	case ACPI_REGISTER_PM1_CONTROL:          /* 16-bit access */
 
 		value =  acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1a_cnt_blk, 0);
 		value |= acpi_hw_low_level_read (16, &acpi_gbl_FADT->Xpm1b_cnt_blk, 0);
 		break;
 
 
-	case PM2_CONTROL: /* 8-bit access */
+	case ACPI_REGISTER_PM2_CONTROL:          /* 8-bit access */
 
 		value =  acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xpm2_cnt_blk, 0);
 		break;
 
 
-	case PM_TIMER: /* 32-bit access */
+	case ACPI_REGISTER_PM_TIMER:             /* 32-bit access */
 
 		value =  acpi_hw_low_level_read (32, &acpi_gbl_FADT->Xpm_tmr_blk, 0);
 		break;
 
-
-	/*
-	 * For the GPE? Blocks, the lower word of Register_id contains the
-	 * byte offset for which to read, as each part of each block may be
-	 * several bytes long.
-	 */
-	case GPE0_STS_BLOCK: /* 8-bit access */
-
-		bank_offset = REGISTER_BIT_ID(register_id);
-		value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe0blk, bank_offset);
-		break;
-
-	case GPE0_EN_BLOCK: /* 8-bit access */
-
-		bank_offset = DIV_2 (acpi_gbl_FADT->gpe0blk_len) + REGISTER_BIT_ID(register_id);
-		value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe0blk, bank_offset);
-		break;
-
-	case GPE1_STS_BLOCK: /* 8-bit access */
-
-		bank_offset = REGISTER_BIT_ID(register_id);
-		value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe1_blk, bank_offset);
-		break;
-
-	case GPE1_EN_BLOCK: /* 8-bit access */
-
-		bank_offset = DIV_2 (acpi_gbl_FADT->gpe1_blk_len) + REGISTER_BIT_ID(register_id);
-		value = acpi_hw_low_level_read (8, &acpi_gbl_FADT->Xgpe1_blk, bank_offset);
-		break;
-
-	case SMI_CMD_BLOCK: /* 8bit */
+	case ACPI_REGISTER_SMI_COMMAND_BLOCK:    /* 8-bit access */
 
 		acpi_os_read_port (acpi_gbl_FADT->smi_cmd, &value, 8);
 		break;
@@ -674,9 +475,8 @@
 		break;
 	}
 
-
 	if (ACPI_MTX_LOCK == use_lock) {
-		acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
 	}
 
 	return_VALUE (value);
@@ -706,93 +506,65 @@
 	u32                     bank_offset;
 
 
-	FUNCTION_TRACE ("Hw_register_write");
+	ACPI_FUNCTION_TRACE ("Hw_register_write");
 
 
 	if (ACPI_MTX_LOCK == use_lock) {
-		acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE);
+		if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_HARDWARE))) {
+			return_VOID;
+		}
 	}
 
-
-	switch (REGISTER_BLOCK_ID (register_id)) {
-	case PM1_STS: /* 16-bit access */
+	switch (register_id) {
+	case ACPI_REGISTER_PM1_STATUS:           /* 16-bit access */
 
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_evt_blk, 0);
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_evt_blk, 0);
 		break;
 
 
-	case PM1_EN: /* 16-bit access*/
+	case ACPI_REGISTER_PM1_ENABLE:           /* 16-bit access*/
 
-		bank_offset = DIV_2 (acpi_gbl_FADT->pm1_evt_len);
+		bank_offset = ACPI_DIV_2 (acpi_gbl_FADT->pm1_evt_len);
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_evt_blk, bank_offset);
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_evt_blk, bank_offset);
 		break;
 
 
-	case PM1_CONTROL: /* 16-bit access */
+	case ACPI_REGISTER_PM1_CONTROL:          /* 16-bit access */
 
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_cnt_blk, 0);
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_cnt_blk, 0);
 		break;
 
 
-	case PM1A_CONTROL: /* 16-bit access */
+	case ACPI_REGISTER_PM1A_CONTROL:         /* 16-bit access */
 
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1a_cnt_blk, 0);
 		break;
 
 
-	case PM1B_CONTROL: /* 16-bit access */
+	case ACPI_REGISTER_PM1B_CONTROL:         /* 16-bit access */
 
 		acpi_hw_low_level_write (16, value, &acpi_gbl_FADT->Xpm1b_cnt_blk, 0);
 		break;
 
 
-	case PM2_CONTROL: /* 8-bit access */
+	case ACPI_REGISTER_PM2_CONTROL:          /* 8-bit access */
 
 		acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xpm2_cnt_blk, 0);
 		break;
 
 
-	case PM_TIMER: /* 32-bit access */
+	case ACPI_REGISTER_PM_TIMER:             /* 32-bit access */
 
 		acpi_hw_low_level_write (32, value, &acpi_gbl_FADT->Xpm_tmr_blk, 0);
 		break;
 
 
-	case GPE0_STS_BLOCK: /* 8-bit access */
-
-		bank_offset = REGISTER_BIT_ID(register_id);
-		acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe0blk, bank_offset);
-		break;
-
-
-	case GPE0_EN_BLOCK: /* 8-bit access */
-
-		bank_offset = DIV_2 (acpi_gbl_FADT->gpe0blk_len) + REGISTER_BIT_ID(register_id);
-		acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe0blk, bank_offset);
-		break;
-
-
-	case GPE1_STS_BLOCK: /* 8-bit access */
-
-		bank_offset = REGISTER_BIT_ID(register_id);
-		acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe1_blk, bank_offset);
-		break;
-
-
-	case GPE1_EN_BLOCK: /* 8-bit access */
-
-		bank_offset = DIV_2 (acpi_gbl_FADT->gpe1_blk_len) + REGISTER_BIT_ID(register_id);
-		acpi_hw_low_level_write (8, value, &acpi_gbl_FADT->Xgpe1_blk, bank_offset);
-		break;
-
-
-	case SMI_CMD_BLOCK: /* 8bit */
+	case ACPI_REGISTER_SMI_COMMAND_BLOCK:    /* 8-bit access */
 
-		/* For 2.0, SMI_CMD is always in IO space */
-		/* TBD: what about 1.0? 0.71? */
+		/* SMI_CMD is currently always in IO space */
 
 		acpi_os_write_port (acpi_gbl_FADT->smi_cmd, value, 8);
 		break;
@@ -803,9 +575,8 @@
 		break;
 	}
 
-
 	if (ACPI_MTX_LOCK == use_lock) {
-		acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_HARDWARE);
 	}
 
 	return_VOID;
@@ -839,7 +610,7 @@
 	u16                     pci_register;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -851,7 +622,6 @@
 		return 0;
 	}
 
-
 	/*
 	 * Three address spaces supported:
 	 * Memory, Io, or PCI config.
@@ -918,7 +688,7 @@
 	u16                     pci_register;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -929,7 +699,6 @@
 		(!ACPI_VALID_ADDRESS (reg->address))) {
 		return;
 	}
-
 
 	/*
 	 * Three address spaces supported:
diff -Nru a/drivers/acpi/hardware/hwsleep.c b/drivers/acpi/hardware/hwsleep.c
--- a/drivers/acpi/hardware/hwsleep.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/hardware/hwsleep.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Name: hwsleep.c - ACPI Hardware Sleep/Wake Interface
- *              $Revision: 22 $
+ *              $Revision: 35 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -29,7 +29,7 @@
 #include "achware.h"
 
 #define _COMPONENT          ACPI_HARDWARE
-	 MODULE_NAME         ("hwsleep")
+	 ACPI_MODULE_NAME    ("hwsleep")
 
 
 /******************************************************************************
@@ -39,7 +39,7 @@
  * PARAMETERS:  Physical_address    - Physical address of ACPI real mode
  *                                    entry point.
  *
- * RETURN:      AE_OK or AE_ERROR
+ * RETURN:      Status
  *
  * DESCRIPTION: Access function for d_firmware_waking_vector field in FACS
  *
@@ -50,22 +50,16 @@
 	ACPI_PHYSICAL_ADDRESS physical_address)
 {
 
-	FUNCTION_TRACE ("Acpi_set_firmware_waking_vector");
-
+	ACPI_FUNCTION_TRACE ("Acpi_set_firmware_waking_vector");
 
-	/* Make sure that we have an FACS */
-
-	if (!acpi_gbl_FACS) {
-		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
-	}
 
 	/* Set the vector */
 
-	if (acpi_gbl_FACS->vector_width == 32) {
-		* (u32 *) acpi_gbl_FACS->firmware_waking_vector = (u32) physical_address;
+	if (acpi_gbl_common_fACS.vector_width == 32) {
+		*(u32 *) acpi_gbl_common_fACS.firmware_waking_vector = (u32) physical_address;
 	}
 	else {
-		*acpi_gbl_FACS->firmware_waking_vector = physical_address;
+		*acpi_gbl_common_fACS.firmware_waking_vector = physical_address;
 	}
 
 	return_ACPI_STATUS (AE_OK);
@@ -82,7 +76,7 @@
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Access function for d_firmware_waking_vector field in FACS
+ * DESCRIPTION: Access function for Firmware_waking_vector field in FACS
  *
  ******************************************************************************/
 
@@ -91,141 +85,177 @@
 	ACPI_PHYSICAL_ADDRESS *physical_address)
 {
 
-	FUNCTION_TRACE ("Acpi_get_firmware_waking_vector");
+	ACPI_FUNCTION_TRACE ("Acpi_get_firmware_waking_vector");
 
 
 	if (!physical_address) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	/* Make sure that we have an FACS */
-
-	if (!acpi_gbl_FACS) {
-		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
-	}
-
 	/* Get the vector */
 
-	if (acpi_gbl_FACS->vector_width == 32) {
-		*physical_address = * (u32 *) acpi_gbl_FACS->firmware_waking_vector;
+	if (acpi_gbl_common_fACS.vector_width == 32) {
+		*physical_address = *(u32 *) acpi_gbl_common_fACS.firmware_waking_vector;
 	}
 	else {
-		*physical_address = *acpi_gbl_FACS->firmware_waking_vector;
+		*physical_address = *acpi_gbl_common_fACS.firmware_waking_vector;
 	}
 
 	return_ACPI_STATUS (AE_OK);
 }
 
+
 /******************************************************************************
  *
- * FUNCTION:    Acpi_enter_sleep_state
+ * FUNCTION:    Acpi_enter_sleep_state_prep
  *
  * PARAMETERS:  Sleep_state         - Which sleep state to enter
  *
  * RETURN:      Status
  *
- * DESCRIPTION: Enter a system sleep state (see ACPI 2.0 spec p 231)
+ * DESCRIPTION: Prepare to enter a system sleep state (see ACPI 2.0 spec p 231)
+ *              This function must execute with interrupts enabled.
+ *              We break sleeping into 2 stages so that OSPM can handle
+ *              various OS-specific tasks between the two steps.
  *
  ******************************************************************************/
 
 acpi_status
-acpi_enter_sleep_state (
+acpi_enter_sleep_state_prep (
 	u8                  sleep_state)
 {
 	acpi_status         status;
 	acpi_object_list    arg_list;
 	acpi_object         arg;
-	u8                  type_a;
-	u8                  type_b;
-	u16                 PM1Acontrol;
-	u16                 PM1Bcontrol;
 
 
-	FUNCTION_TRACE ("Acpi_enter_sleep_state");
+	ACPI_FUNCTION_TRACE ("Acpi_enter_sleep_state_prep");
 
 
 	/*
 	 * _PSW methods could be run here to enable wake-on keyboard, LAN, etc.
 	 */
-	status = acpi_hw_obtain_sleep_type_register_data (sleep_state, &type_a, &type_b);
-	if (!ACPI_SUCCESS (status)) {
-		return status;
+	status = acpi_hw_get_sleep_type_data (sleep_state,
+			  &acpi_gbl_sleep_type_a, &acpi_gbl_sleep_type_b);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	/* run the _PTS and _GTS methods */
+	/* Setup parameter object */
 
-	MEMSET(&arg_list, 0, sizeof(arg_list));
 	arg_list.count = 1;
 	arg_list.pointer = &arg;
 
-	MEMSET(&arg, 0, sizeof(arg));
 	arg.type = ACPI_TYPE_INTEGER;
 	arg.integer.value = sleep_state;
 
-	acpi_evaluate_object (NULL, "\\_PTS", &arg_list, NULL);
-	acpi_evaluate_object (NULL, "\\_GTS", &arg_list, NULL);
+	/* Run the _PTS and _GTS methods */
+
+	status = acpi_evaluate_object (NULL, "\\_PTS", &arg_list, NULL);
+	if (ACPI_FAILURE (status) && status != AE_NOT_FOUND) {
+		return_ACPI_STATUS (status);
+	}
 
-	/* clear wake status */
+	status = acpi_evaluate_object (NULL, "\\_GTS", &arg_list, NULL);
+	if (ACPI_FAILURE (status) && status != AE_NOT_FOUND) {
+		return_ACPI_STATUS (status);
+	}
 
-	acpi_hw_register_bit_access (ACPI_WRITE, ACPI_MTX_LOCK, WAK_STS, 1);
+	return_ACPI_STATUS (AE_OK);
+}
 
-	disable ();
+
+/******************************************************************************
+ *
+ * FUNCTION:    Acpi_enter_sleep_state
+ *
+ * PARAMETERS:  Sleep_state         - Which sleep state to enter
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Enter a system sleep state (see ACPI 2.0 spec p 231)
+ *              THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_enter_sleep_state (
+	u8                      sleep_state)
+{
+	u16                     PM1Acontrol;
+	u16                     PM1Bcontrol;
+	ACPI_BIT_REGISTER_INFO  *sleep_type_reg_info;
+	ACPI_BIT_REGISTER_INFO  *sleep_enable_reg_info;
+
+
+	ACPI_FUNCTION_TRACE ("Acpi_enter_sleep_state");
+
+
+	if ((acpi_gbl_sleep_type_a > ACPI_SLEEP_TYPE_MAX) ||
+		(acpi_gbl_sleep_type_b > ACPI_SLEEP_TYPE_MAX)) {
+		ACPI_REPORT_ERROR (("Sleep values out of range: A=%x B=%x\n",
+			acpi_gbl_sleep_type_a, acpi_gbl_sleep_type_b));
+		return_ACPI_STATUS (AE_AML_OPERAND_VALUE);
+	}
+
+
+	sleep_type_reg_info = acpi_hw_get_bit_register_info (ACPI_BITREG_SLEEP_TYPE_A);
+	sleep_enable_reg_info = acpi_hw_get_bit_register_info (ACPI_BITREG_SLEEP_ENABLE);
+
+	/* Clear wake status */
+
+	acpi_hw_bit_register_write (ACPI_BITREG_WAKE_STATUS, 1, ACPI_MTX_LOCK);
+	acpi_hw_clear_acpi_status();
+
+	/* TBD: Disable arbitration here? */
 
 	acpi_hw_disable_non_wakeup_gpes();
 
-	PM1Acontrol = (u16) acpi_hw_register_read (ACPI_MTX_LOCK, PM1_CONTROL);
+	/* Get current value of PM1A control */
 
+	PM1Acontrol = (u16) acpi_hw_register_read (ACPI_MTX_LOCK, ACPI_REGISTER_PM1_CONTROL);
 	ACPI_DEBUG_PRINT ((ACPI_DB_OK, "Entering S%d\n", sleep_state));
 
-	/* mask off SLP_EN and SLP_TYP fields */
+	/* Clear SLP_EN and SLP_TYP fields */
 
-	PM1Acontrol &= ~(SLP_TYPE_X_MASK | SLP_EN_MASK);
+	PM1Acontrol &= ~(sleep_type_reg_info->access_bit_mask | sleep_enable_reg_info->access_bit_mask);
 	PM1Bcontrol = PM1Acontrol;
 
-	/* mask in SLP_TYP */
-
-	PM1Acontrol |= (type_a << acpi_hw_get_bit_shift (SLP_TYPE_X_MASK));
-	PM1Bcontrol |= (type_b << acpi_hw_get_bit_shift (SLP_TYPE_X_MASK));
+	/* Insert SLP_TYP bits */
 
-	/* write #1: fill in SLP_TYP data */
+	PM1Acontrol |= (acpi_gbl_sleep_type_a << sleep_type_reg_info->bit_position);
+	PM1Bcontrol |= (acpi_gbl_sleep_type_b << sleep_type_reg_info->bit_position);
 
-	acpi_hw_register_write (ACPI_MTX_LOCK, PM1A_CONTROL, PM1Acontrol);
-	acpi_hw_register_write (ACPI_MTX_LOCK, PM1B_CONTROL, PM1Bcontrol);
+	/* Write #1: fill in SLP_TYP data */
 
-	/* mask in SLP_EN */
+	acpi_hw_register_write (ACPI_MTX_LOCK, ACPI_REGISTER_PM1A_CONTROL, PM1Acontrol);
+	acpi_hw_register_write (ACPI_MTX_LOCK, ACPI_REGISTER_PM1B_CONTROL, PM1Bcontrol);
 
-	PM1Acontrol |= (1 << acpi_hw_get_bit_shift (SLP_EN_MASK));
-	PM1Bcontrol |= (1 << acpi_hw_get_bit_shift (SLP_EN_MASK));
+	/* Insert SLP_ENABLE bit */
 
-	/* flush caches */
+	PM1Acontrol |= sleep_enable_reg_info->access_bit_mask;
+	PM1Bcontrol |= sleep_enable_reg_info->access_bit_mask;
 
-	wbinvd();
+	/* Write #2: SLP_TYP + SLP_EN */
 
-	/* write #2: SLP_TYP + SLP_EN */
-
-	acpi_hw_register_write (ACPI_MTX_LOCK, PM1A_CONTROL, PM1Acontrol);
-	acpi_hw_register_write (ACPI_MTX_LOCK, PM1B_CONTROL, PM1Bcontrol);
+	acpi_hw_register_write (ACPI_MTX_LOCK, ACPI_REGISTER_PM1A_CONTROL, PM1Acontrol);
+	acpi_hw_register_write (ACPI_MTX_LOCK, ACPI_REGISTER_PM1B_CONTROL, PM1Bcontrol);
 
 	/*
 	 * Wait a second, then try again. This is to get S4/5 to work on all machines.
 	 */
 	if (sleep_state > ACPI_STATE_S3) {
-		acpi_os_stall(1000000);
+		acpi_os_stall (1000000);
 
-		acpi_hw_register_write (ACPI_MTX_LOCK, PM1_CONTROL,
-			(1 << acpi_hw_get_bit_shift (SLP_EN_MASK)));
+		acpi_hw_register_write (ACPI_MTX_LOCK, ACPI_REGISTER_PM1_CONTROL,
+				sleep_enable_reg_info->access_bit_mask);
 	}
 
-	/* wait until we enter sleep state */
+	/* Wait until we enter sleep state */
 
-	do {
-		acpi_os_stall(10000);
+	while (!acpi_hw_bit_register_read (ACPI_BITREG_WAKE_STATUS, ACPI_MTX_LOCK)) {
+		/* Spin until we wake */
 	}
-	while (!acpi_hw_register_bit_access (ACPI_READ, ACPI_MTX_LOCK, WAK_STS));
-
-	acpi_hw_enable_non_wakeup_gpes();
-
-	enable ();
 
 	return_ACPI_STATUS (AE_OK);
 }
@@ -248,21 +278,35 @@
 {
 	acpi_object_list    arg_list;
 	acpi_object         arg;
+	acpi_status         status;
+
 
+	ACPI_FUNCTION_TRACE ("Acpi_leave_sleep_state");
 
-	FUNCTION_TRACE ("Acpi_leave_sleep_state");
 
+	/* Ensure Enter_sleep_state_prep -> Enter_sleep_state ordering */
+
+	acpi_gbl_sleep_type_a = ACPI_SLEEP_TYPE_INVALID;
+
+	/* Setup parameter object */
 
-	MEMSET (&arg_list, 0, sizeof(arg_list));
 	arg_list.count = 1;
 	arg_list.pointer = &arg;
 
-	MEMSET (&arg, 0, sizeof(arg));
 	arg.type = ACPI_TYPE_INTEGER;
 	arg.integer.value = sleep_state;
 
-	acpi_evaluate_object (NULL, "\\_BFS", &arg_list, NULL);
-	acpi_evaluate_object (NULL, "\\_WAK", &arg_list, NULL);
+	/* Ignore any errors from these methods */
+
+	status = acpi_evaluate_object (NULL, "\\_BFS", &arg_list, NULL);
+	if (ACPI_FAILURE (status) && status != AE_NOT_FOUND) {
+		ACPI_REPORT_ERROR (("Method _BFS failed, %s\n", acpi_format_exception (status)));
+	}
+
+	status = acpi_evaluate_object (NULL, "\\_WAK", &arg_list, NULL);
+	if (ACPI_FAILURE (status) && status != AE_NOT_FOUND) {
+		ACPI_REPORT_ERROR (("Method _WAK failed, %s\n", acpi_format_exception (status)));
+	}
 
 	/* _WAK returns stuff - do we want to look at it? */
 
diff -Nru a/drivers/acpi/hardware/hwtimer.c b/drivers/acpi/hardware/hwtimer.c
--- a/drivers/acpi/hardware/hwtimer.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/hardware/hwtimer.c	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Name: hwtimer.c - ACPI Power Management Timer Interface
- *              $Revision: 14 $
+ *              $Revision: 19 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "achware.h"
 
 #define _COMPONENT          ACPI_HARDWARE
-	 MODULE_NAME         ("hwtimer")
+	 ACPI_MODULE_NAME    ("hwtimer")
 
 
 /******************************************************************************
@@ -47,7 +47,7 @@
 acpi_get_timer_resolution (
 	u32                     *resolution)
 {
-	FUNCTION_TRACE ("Acpi_get_timer_resolution");
+	ACPI_FUNCTION_TRACE ("Acpi_get_timer_resolution");
 
 
 	if (!resolution) {
@@ -57,7 +57,6 @@
 	if (0 == acpi_gbl_FADT->tmr_val_ext) {
 		*resolution = 24;
 	}
-
 	else {
 		*resolution = 32;
 	}
@@ -82,7 +81,7 @@
 acpi_get_timer (
 	u32                     *ticks)
 {
-	FUNCTION_TRACE ("Acpi_get_timer");
+	ACPI_FUNCTION_TRACE ("Acpi_get_timer");
 
 
 	if (!ticks) {
@@ -129,13 +128,12 @@
 	u32                     *time_elapsed)
 {
 	u32                     delta_ticks = 0;
-	u32                     seconds = 0;
-	u32                     milliseconds = 0;
-	u32                     microseconds = 0;
-	u32                     remainder = 0;
+	uint64_overlay          normalized_ticks;
+	acpi_status             status;
+	acpi_integer            out_quotient;
 
 
-	FUNCTION_TRACE ("Acpi_get_timer_duration");
+	ACPI_FUNCTION_TRACE ("Acpi_get_timer_duration");
 
 
 	if (!time_elapsed) {
@@ -150,21 +148,18 @@
 	if (start_ticks < end_ticks) {
 		delta_ticks = end_ticks - start_ticks;
 	}
-
 	else if (start_ticks > end_ticks) {
-		/* 24-bit Timer */
-
 		if (0 == acpi_gbl_FADT->tmr_val_ext) {
+			/* 24-bit Timer */
+
 			delta_ticks = (((0x00FFFFFF - start_ticks) + end_ticks) & 0x00FFFFFF);
 		}
-
-		/* 32-bit Timer */
-
 		else {
+			/* 32-bit Timer */
+
 			delta_ticks = (0xFFFFFFFF - start_ticks) + end_ticks;
 		}
 	}
-
 	else {
 		*time_elapsed = 0;
 		return_ACPI_STATUS (AE_OK);
@@ -173,49 +168,18 @@
 	/*
 	 * Compute Duration:
 	 * -----------------
-	 * Since certain compilers (gcc/Linux, argh!) don't support 64-bit
-	 * divides in kernel-space we have to do some trickery to preserve
-	 * accuracy while using 32-bit math.
-	 *
-	 * TBD: Change to use 64-bit math when supported.
 	 *
-	 * The process is as follows:
-	 *  1. Compute the number of seconds by dividing Delta Ticks by
-	 *     the timer frequency.
-	 *  2. Compute the number of milliseconds in the remainder from step #1
-	 *     by multiplying by 1000 and then dividing by the timer frequency.
-	 *  3. Compute the number of microseconds in the remainder from step #2
-	 *     by multiplying by 1000 and then dividing by the timer frequency.
-	 *  4. Add the results from steps 1, 2, and 3 to get the total duration.
+	 * Requires a 64-bit divide:
 	 *
-	 * Example: The time elapsed for Delta_ticks = 0xFFFFFFFF should be
-	 *          1199864031 microseconds.  This is computed as follows:
-	 *          Step #1: Seconds = 1199; Remainder = 3092840
-	 *          Step #2: Milliseconds = 864; Remainder = 113120
-	 *          Step #3: Microseconds = 31; Remainder = <don't care!>
+	 * Time_elapsed = (Delta_ticks * 1000000) / PM_TIMER_FREQUENCY;
 	 */
+	normalized_ticks.full = ((u64) delta_ticks) * 1000000;
 
-	/* Step #1 */
+	status = acpi_ut_short_divide (&normalized_ticks.full, PM_TIMER_FREQUENCY,
+			   &out_quotient, NULL);
 
-	seconds = delta_ticks / PM_TIMER_FREQUENCY;
-	remainder = delta_ticks % PM_TIMER_FREQUENCY;
-
-	/* Step #2 */
-
-	milliseconds = (remainder * 1000) / PM_TIMER_FREQUENCY;
-	remainder = (remainder * 1000) % PM_TIMER_FREQUENCY;
-
-	/* Step #3 */
-
-	microseconds = (remainder * 1000) / PM_TIMER_FREQUENCY;
-
-	/* Step #4 */
-
-	*time_elapsed = seconds * 1000000;
-	*time_elapsed += milliseconds * 1000;
-	*time_elapsed += microseconds;
-
-	return_ACPI_STATUS (AE_OK);
+	*time_elapsed = (u32) out_quotient;
+	return_ACPI_STATUS (status);
 }
 
 
diff -Nru a/drivers/acpi/include/acconfig.h b/drivers/acpi/include/acconfig.h
--- a/drivers/acpi/include/acconfig.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/include/acconfig.h	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acconfig.h - Global configuration constants
- *       $Revision: 74 $
+ *       $Revision: 94 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,12 +34,13 @@
  *****************************************************************************/
 
 /*
- * ACPI_DEBUG           - This switch enables all the debug facilities of the ACPI
- *                          subsystem.  This includes the DEBUG_PRINT output statements
- *                          When disabled, all DEBUG_PRINT statements are compiled out.
+ * ACPI_DEBUG           - This switch enables all the debug facilities of the
+ *                        ACPI subsystem.  This includes the DEBUG_PRINT output
+ *                        statements.  When disabled, all DEBUG_PRINT
+ *                        statements are compiled out.
  *
  * ACPI_APPLICATION     - Use this switch if the subsystem is going to be run
- *                          at the application level.
+ *                        at the application level.
  *
  */
 
@@ -53,43 +54,44 @@
 
 /* Version string */
 
-#define ACPI_CA_VERSION             0x20011018
+#define ACPI_CA_VERSION             0x20020308
 
 /* Version of ACPI supported */
 
 #define ACPI_CA_SUPPORT_LEVEL       2
 
-
 /* Maximum objects in the various object caches */
 
-#define MAX_STATE_CACHE_DEPTH       64         /* State objects for stacks */
+#define MAX_STATE_CACHE_DEPTH       64          /* State objects for stacks */
 #define MAX_PARSE_CACHE_DEPTH       96          /* Parse tree objects */
 #define MAX_EXTPARSE_CACHE_DEPTH    64          /* Parse tree objects */
 #define MAX_OBJECT_CACHE_DEPTH      64          /* Interpreter operand objects */
-#define MAX_WALK_CACHE_DEPTH        4           /* Objects for parse tree walks (method execution) */
-
+#define MAX_WALK_CACHE_DEPTH        4           /* Objects for parse tree walks */
 
 /* String size constants */
 
 #define MAX_STRING_LENGTH           512
-#define PATHNAME_MAX                256     /* A full namespace pathname */
-
+#define PATHNAME_MAX                256         /* A full namespace pathname */
 
 /* Maximum count for a semaphore object */
 
 #define MAX_SEMAPHORE_COUNT         256
 
-
 /* Max reference count (for debug only) */
 
 #define MAX_REFERENCE_COUNT         0x400
 
-
 /* Size of cached memory mapping for system memory operation region */
 
 #define SYSMEM_REGION_WINDOW_SIZE   4096
 
 
+/******************************************************************************
+ *
+ * Configuration of subsystem behavior
+ *
+ *****************************************************************************/
+
 /*
  * Debugger threading model
  * Use single threaded if the entire subsystem is contained in an application
@@ -98,7 +100,6 @@
  * By default the model is single threaded if ACPI_APPLICATION is set,
  * multi-threaded if ACPI_APPLICATION is not set.
  */
-
 #define DEBUGGER_SINGLE_THREADED    0
 #define DEBUGGER_MULTI_THREADED     1
 
@@ -109,6 +110,12 @@
 #define DEBUGGER_THREADING          DEBUGGER_MULTI_THREADED
 #endif
 
+/*
+ * Should the subystem abort the loading of an ACPI table if the
+ * table checksum is incorrect?
+ */
+#define ACPI_CHECKSUM_ABORT         FALSE
+
 
 /******************************************************************************
  *
@@ -116,10 +123,13 @@
  *
  *****************************************************************************/
 
+/* Number of distinct GPE register blocks */
+
+#define ACPI_MAX_GPE_BLOCKS         2
+
 /*
  * Method info (in WALK_STATE), containing local variables and argumetns
  */
-
 #define MTH_NUM_LOCALS              8
 #define MTH_MAX_LOCAL               7
 
@@ -133,17 +143,15 @@
 /*
  * Operand Stack (in WALK_STATE), Must be large enough to contain MTH_MAX_ARG
  */
-
 #define OBJ_NUM_OPERANDS            8
 #define OBJ_MAX_OPERAND             7
 
 /* Names within the namespace are 4 bytes long */
 
 #define ACPI_NAME_SIZE              4
-#define PATH_SEGMENT_LENGTH         5           /* 4 chars for name + 1 s8 for separator */
+#define PATH_SEGMENT_LENGTH         5           /* 4 chars for name + 1 char for separator */
 #define PATH_SEPARATOR              '.'
 
-
 /* Constants used in searching for the RSDP in low memory */
 
 #define LO_RSDP_WINDOW_BASE         0           /* Physical Address */
@@ -152,10 +160,32 @@
 #define HI_RSDP_WINDOW_SIZE         0x20000
 #define RSDP_SCAN_STEP              16
 
+/* Operation regions */
+
+#define ACPI_NUM_PREDEFINED_REGIONS 8
+#define ACPI_USER_REGION_BEGIN      0x80
+
 /* Maximum Space_ids for Operation Regions */
 
 #define ACPI_MAX_ADDRESS_SPACE      255
-#define ACPI_NUM_ADDRESS_SPACES     256
+
+/* RSDP checksums */
+
+#define ACPI_RSDP_CHECKSUM_LENGTH   20
+#define ACPI_RSDP_XCHECKSUM_LENGTH  36
+
+
+/******************************************************************************
+ *
+ * ACPI AML Debugger
+ *
+ *****************************************************************************/
+
+
+#define ACPI_DEBUGGER_MAX_ARGS             8  /* Must be max method args + 1 */
+
+#define ACPI_DEBUGGER_COMMAND_PROMPT      '-'
+#define ACPI_DEBUGGER_EXECUTE_PROMPT      '%'
 
 
 #endif /* _ACCONFIG_H */
diff -Nru a/drivers/acpi/include/acdebug.h b/drivers/acpi/include/acdebug.h
--- a/drivers/acpi/include/acdebug.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acdebug.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acdebug.h - ACPI/AML debugger
- *       $Revision: 50 $
+ *       $Revision: 57 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -27,61 +27,8 @@
 #define __ACDEBUG_H__
 
 
-#define DB_MAX_ARGS             8  /* Must be max method args + 1 */
-
-#define DB_COMMAND_PROMPT      '-'
-#define DB_EXECUTE_PROMPT      '%'
-
-
-extern int                      optind;
-extern NATIVE_CHAR              *optarg;
-extern u8                       *aml_start;
-extern u32                      aml_length;
-
-extern u8                       acpi_gbl_db_opt_tables;
-extern u8                       acpi_gbl_db_opt_disasm;
-extern u8                       acpi_gbl_db_opt_stats;
-extern u8                       acpi_gbl_db_opt_parse_jit;
-extern u8                       acpi_gbl_db_opt_verbose;
-extern u8                       acpi_gbl_db_opt_ini_methods;
-
-
-extern NATIVE_CHAR              *acpi_gbl_db_args[DB_MAX_ARGS];
-extern NATIVE_CHAR              acpi_gbl_db_line_buf[80];
-extern NATIVE_CHAR              acpi_gbl_db_scope_buf[40];
-extern NATIVE_CHAR              acpi_gbl_db_debug_filename[40];
-extern u8                       acpi_gbl_db_output_to_file;
-extern NATIVE_CHAR              *acpi_gbl_db_buffer;
-extern NATIVE_CHAR              *acpi_gbl_db_filename;
-extern NATIVE_CHAR              *acpi_gbl_db_disasm_indent;
-extern u8                       acpi_gbl_db_output_flags;
-extern u32                      acpi_gbl_db_debug_level;
-extern u32                      acpi_gbl_db_console_debug_level;
-extern acpi_table_header        *acpi_gbl_db_table_ptr;
-
-/*
- * Statistic globals
- */
-extern u16                      acpi_gbl_obj_type_count[INTERNAL_TYPE_NODE_MAX+1];
-extern u16                      acpi_gbl_node_type_count[INTERNAL_TYPE_NODE_MAX+1];
-extern u16                      acpi_gbl_obj_type_count_misc;
-extern u16                      acpi_gbl_node_type_count_misc;
-extern u32                      acpi_gbl_num_nodes;
-extern u32                      acpi_gbl_num_objects;
-
-
-extern u32                      acpi_gbl_size_of_parse_tree;
-extern u32                      acpi_gbl_size_of_method_trees;
-extern u32                      acpi_gbl_size_of_node_entries;
-extern u32                      acpi_gbl_size_of_acpi_objects;
-
-
 #define ACPI_DEBUG_BUFFER_SIZE  4196
 
-#define DB_REDIRECTABLE_OUTPUT  0x01
-#define DB_CONSOLE_OUTPUT       0x02
-#define DB_DUPLICATE_OUTPUT     0x03
-
 
 typedef struct command_info
 {
@@ -306,7 +253,7 @@
  * dbfileio - Debugger file I/O commands
  */
 
-acpi_object_type8
+acpi_object_type
 acpi_db_match_argument (
 	NATIVE_CHAR             *user_argument,
 	ARGUMENT_INFO           *arguments);
@@ -351,7 +298,7 @@
 	acpi_walk_state         *walk_state,
 	acpi_parse_object       *op);
 
-void
+void ACPI_SYSTEM_XFACE
 acpi_db_execute_thread (
 	void                    *context);
 
diff -Nru a/drivers/acpi/include/acdispat.h b/drivers/acpi/include/acdispat.h
--- a/drivers/acpi/include/acdispat.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acdispat.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acdispat.h - dispatcher (parser to interpreter interface)
- *       $Revision: 45 $
+ *       $Revision: 51 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -86,7 +86,7 @@
 acpi_status
 acpi_ds_get_predicate_value (
 	acpi_walk_state         *walk_state,
-	u32                     has_result_obj);
+	acpi_operand_object     *result_obj);
 
 acpi_status
 acpi_ds_exec_begin_op (
@@ -123,6 +123,11 @@
 	acpi_parse_object       *op,
 	acpi_walk_state         *walk_state);
 
+acpi_status
+acpi_ds_init_field_objects (
+	acpi_parse_object       *op,
+	acpi_walk_state         *walk_state);
+
 
 /* dsload - Parser/Interpreter interface, namespace load callbacks */
 
@@ -175,7 +180,7 @@
 acpi_ds_is_method_value (
 	acpi_operand_object     *obj_desc);
 
-acpi_object_type8
+acpi_object_type
 acpi_ds_method_data_get_type (
 	u16                     opcode,
 	u32                     index,
@@ -200,18 +205,19 @@
 	u32                     max_param_count,
 	acpi_walk_state         *walk_state);
 
-acpi_namespace_node *
+acpi_status
 acpi_ds_method_data_get_node (
 	u16                     opcode,
 	u32                     index,
-	acpi_walk_state         *walk_state);
+	acpi_walk_state         *walk_state,
+	acpi_namespace_node     **node);
 
 acpi_status
 acpi_ds_method_data_init (
 	acpi_walk_state         *walk_state);
 
 acpi_status
-acpi_ds_method_data_set_entry (
+acpi_ds_method_data_set_value (
 	u16                     opcode,
 	u32                     index,
 	acpi_operand_object     *object,
@@ -226,7 +232,7 @@
 
 acpi_status
 acpi_ds_call_control_method (
-	acpi_walk_list          *walk_list,
+	ACPI_THREAD_STATE       *thread,
 	acpi_walk_state         *walk_state,
 	acpi_parse_object       *op);
 
@@ -331,15 +337,6 @@
 acpi_ds_resolve_operands (
 	acpi_walk_state         *walk_state);
 
-acpi_object_type8
-acpi_ds_map_opcode_to_data_type (
-	u16                     opcode,
-	u32                     *out_flags);
-
-acpi_object_type8
-acpi_ds_map_named_opcode_to_data_type (
-	u16                     opcode);
-
 
 /*
  * dswscope - Scope Stack manipulation
@@ -348,7 +345,7 @@
 acpi_status
 acpi_ds_scope_stack_push (
 	acpi_namespace_node     *node,
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_walk_state         *walk_state);
 
 
@@ -368,7 +365,7 @@
 	acpi_owner_id           owner_id,
 	acpi_parse_object       *origin,
 	acpi_operand_object     *mth_desc,
-	acpi_walk_list          *walk_list);
+	ACPI_THREAD_STATE       *thread);
 
 acpi_status
 acpi_ds_init_aml_walk (
@@ -396,12 +393,12 @@
 
 acpi_walk_state *
 acpi_ds_pop_walk_state (
-	acpi_walk_list          *walk_list);
+	ACPI_THREAD_STATE       *thread);
 
 void
 acpi_ds_push_walk_state (
 	acpi_walk_state         *walk_state,
-	acpi_walk_list          *walk_list);
+	ACPI_THREAD_STATE       *thread);
 
 acpi_status
 acpi_ds_result_stack_pop (
@@ -417,7 +414,7 @@
 
 acpi_walk_state *
 acpi_ds_get_current_walk_state (
-	acpi_walk_list          *walk_list);
+	ACPI_THREAD_STATE       *thread);
 
 void
 acpi_ds_delete_walk_state_cache (
diff -Nru a/drivers/acpi/include/acevents.h b/drivers/acpi/include/acevents.h
--- a/drivers/acpi/include/acevents.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acevents.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acevents.h - Event subcomponent prototypes and defines
- *       $Revision: 66 $
+ *       $Revision: 75 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,9 +31,13 @@
 acpi_ev_initialize (
 	void);
 
+acpi_status
+acpi_ev_handler_initialize (
+	void);
+
 
 /*
- * Acpi_evfixed - Fixed event handling
+ * Evfixed - Fixed event handling
  */
 
 acpi_status
@@ -46,16 +50,16 @@
 
 u32
 acpi_ev_fixed_event_dispatch (
-	u32                     acpi_event);
+	u32                     event);
 
 
 /*
- * Acpi_evglock - Global Lock support
+ * Evmisc
  */
 
 acpi_status
 acpi_ev_acquire_global_lock(
-	void);
+	u32                     timeout);
 
 void
 acpi_ev_release_global_lock(
@@ -65,9 +69,26 @@
 acpi_ev_init_global_lock_handler (
 	void);
 
+u32
+acpi_ev_get_gpe_register_index (
+	u32                     gpe_number);
+
+u32
+acpi_ev_get_gpe_number_index (
+	u32                     gpe_number);
+
+acpi_status
+acpi_ev_queue_notify_request (
+	acpi_namespace_node     *node,
+	u32                     notify_value);
+
+void ACPI_SYSTEM_XFACE
+acpi_ev_notify_dispatch (
+	void                    *context);
+
 
 /*
- * Acpi_evgpe - GPE handling and dispatch
+ * Evgpe - GPE handling and dispatch
  */
 
 acpi_status
@@ -86,22 +107,8 @@
 acpi_ev_gpe_detect (
 	void);
 
-
-/*
- * Acpi_evnotify - Device Notify handling and dispatch
- */
-
-acpi_status
-acpi_ev_queue_notify_request (
-	acpi_namespace_node     *node,
-	u32                     notify_value);
-
-void
-acpi_ev_notify_dispatch (
-	void                    *context);
-
 /*
- * Acpi_evregion - Address Space handling
+ * Evregion - Address Space handling
  */
 
 acpi_status
@@ -114,8 +121,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value);
-
+	acpi_integer            *value);
 
 acpi_status
 acpi_ev_addr_handler_helper (
@@ -129,7 +135,6 @@
 	acpi_operand_object    *region_obj,
 	u8                      acpi_ns_is_locked);
 
-
 acpi_status
 acpi_ev_associate_region_and_handler (
 	acpi_operand_object     *handler_obj,
@@ -138,7 +143,7 @@
 
 
 /*
- * Acpi_evregini - Region initialization and setup
+ * Evregini - Region initialization and setup
  */
 
 acpi_status
@@ -204,10 +209,6 @@
 u32
 acpi_ev_initialize_sCI (
 	u32                     program_sCI);
-
-void
-acpi_ev_restore_acpi_state (
-	void);
 
 void
 acpi_ev_terminate (
diff -Nru a/drivers/acpi/include/acexcep.h b/drivers/acpi/include/acexcep.h
--- a/drivers/acpi/include/acexcep.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acexcep.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acexcep.h - Exception codes returned by the ACPI subsystem
- *       $Revision: 50 $
+ *       $Revision: 57 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -54,7 +54,7 @@
 #define AE_NO_MEMORY                    (acpi_status) (0x0004 | AE_CODE_ENVIRONMENTAL)
 #define AE_NOT_FOUND                    (acpi_status) (0x0005 | AE_CODE_ENVIRONMENTAL)
 #define AE_NOT_EXIST                    (acpi_status) (0x0006 | AE_CODE_ENVIRONMENTAL)
-#define AE_EXIST                        (acpi_status) (0x0007 | AE_CODE_ENVIRONMENTAL)
+#define AE_ALREADY_EXISTS               (acpi_status) (0x0007 | AE_CODE_ENVIRONMENTAL)
 #define AE_TYPE                         (acpi_status) (0x0008 | AE_CODE_ENVIRONMENTAL)
 #define AE_NULL_OBJECT                  (acpi_status) (0x0009 | AE_CODE_ENVIRONMENTAL)
 #define AE_NULL_ENTRY                   (acpi_status) (0x000A | AE_CODE_ENVIRONMENTAL)
@@ -85,8 +85,9 @@
 #define AE_BAD_PATHNAME                 (acpi_status) (0x0003 | AE_CODE_PROGRAMMER)
 #define AE_BAD_DATA                     (acpi_status) (0x0004 | AE_CODE_PROGRAMMER)
 #define AE_BAD_ADDRESS                  (acpi_status) (0x0005 | AE_CODE_PROGRAMMER)
+#define AE_ALIGNMENT                    (acpi_status) (0x0006 | AE_CODE_PROGRAMMER)
 
-#define AE_CODE_PGM_MAX                 0x0005
+#define AE_CODE_PGM_MAX                 0x0006
 
 
 /*
@@ -96,8 +97,9 @@
 #define AE_BAD_HEADER                   (acpi_status) (0x0002 | AE_CODE_ACPI_TABLES)
 #define AE_BAD_CHECKSUM                 (acpi_status) (0x0003 | AE_CODE_ACPI_TABLES)
 #define AE_BAD_VALUE                    (acpi_status) (0x0004 | AE_CODE_ACPI_TABLES)
+#define AE_TABLE_NOT_SUPPORTED          (acpi_status) (0x0005 | AE_CODE_ACPI_TABLES)
 
-#define AE_CODE_TBL_MAX                 0x0003
+#define AE_CODE_TBL_MAX                 0x0005
 
 
 /*
@@ -129,8 +131,11 @@
 #define AE_AML_MUTEX_ORDER              (acpi_status) (0x0017 | AE_CODE_AML)
 #define AE_AML_MUTEX_NOT_ACQUIRED       (acpi_status) (0x0018 | AE_CODE_AML)
 #define AE_AML_INVALID_RESOURCE_TYPE    (acpi_status) (0x0019 | AE_CODE_AML)
+#define AE_AML_INVALID_INDEX            (acpi_status) (0x001A | AE_CODE_AML)
+#define AE_AML_REGISTER_LIMIT           (acpi_status) (0x001B | AE_CODE_AML)
+#define AE_AML_NO_WHILE                 (acpi_status) (0x001C | AE_CODE_AML)
 
-#define AE_CODE_AML_MAX                 0x0019
+#define AE_CODE_AML_MAX                 0x001C
 
 /*
  * Internal exceptions used for control
@@ -143,8 +148,10 @@
 #define AE_CTRL_DEPTH                   (acpi_status) (0x0006 | AE_CODE_CONTROL)
 #define AE_CTRL_END                     (acpi_status) (0x0007 | AE_CODE_CONTROL)
 #define AE_CTRL_TRANSFER                (acpi_status) (0x0008 | AE_CODE_CONTROL)
+#define AE_CTRL_BREAK                   (acpi_status) (0x0009 | AE_CODE_CONTROL)
+#define AE_CTRL_CONTINUE                (acpi_status) (0x000A | AE_CODE_CONTROL)
 
-#define AE_CODE_CTRL_MAX                0x0008
+#define AE_CODE_CTRL_MAX                0x000A
 
 
 #ifdef DEFINE_ACPI_GLOBALS
@@ -162,7 +169,7 @@
 	"AE_NO_MEMORY",
 	"AE_NOT_FOUND",
 	"AE_NOT_EXIST",
-	"AE_EXIST",
+	"AE_ALREADY_EXISTS",
 	"AE_TYPE",
 	"AE_NULL_OBJECT",
 	"AE_NULL_ENTRY",
@@ -181,7 +188,7 @@
 	"AE_NOT_ACQUIRED",
 	"AE_ALREADY_ACQUIRED",
 	"AE_NO_HARDWARE_RESPONSE",
-	"AE_NO_GLOBAL_LOCK",
+	"AE_NO_GLOBAL_LOCK"
 };
 
 NATIVE_CHAR const   *acpi_gbl_exception_names_pgm[] =
@@ -191,6 +198,7 @@
 	"AE_BAD_PATHNAME",
 	"AE_BAD_DATA",
 	"AE_BAD_ADDRESS",
+	"AE_ALIGNMENT"
 };
 
 NATIVE_CHAR const   *acpi_gbl_exception_names_tbl[] =
@@ -199,6 +207,7 @@
 	"AE_BAD_HEADER",
 	"AE_BAD_CHECKSUM",
 	"AE_BAD_VALUE",
+	"AE_TABLE_NOT_SUPPORTED"
 };
 
 NATIVE_CHAR const   *acpi_gbl_exception_names_aml[] =
@@ -228,6 +237,9 @@
 	"AE_AML_MUTEX_ORDER",
 	"AE_AML_MUTEX_NOT_ACQUIRED",
 	"AE_AML_INVALID_RESOURCE_TYPE",
+	"AE_AML_INVALID_INDEX",
+	"AE_AML_REGISTER_LIMIT",
+	"AE_AML_NO_WHILE"
 };
 
 NATIVE_CHAR const   *acpi_gbl_exception_names_ctrl[] =
@@ -240,6 +252,8 @@
 	"AE_CTRL_DEPTH",
 	"AE_CTRL_END",
 	"AE_CTRL_TRANSFER",
+	"AE_CTRL_BREAK",
+	"AE_CTRL_CONTINUE"
 };
 
 #endif /* ACPI GLOBALS */
diff -Nru a/drivers/acpi/include/acglobal.h b/drivers/acpi/include/acglobal.h
--- a/drivers/acpi/include/acglobal.h	Fri Mar 15 17:51:00 2002
+++ b/drivers/acpi/include/acglobal.h	Fri Mar 15 17:51:00 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acglobal.h - Declarations for global variables
- *       $Revision: 106 $
+ *       $Revision: 120 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -71,11 +71,12 @@
  * of each in the system.  Each global points to the actual table.
  *
  */
-ACPI_EXTERN RSDP_DESCRIPTOR             *acpi_gbl_RSDP;
-ACPI_EXTERN xsdt_descriptor             *acpi_gbl_XSDT;
-ACPI_EXTERN FADT_DESCRIPTOR             *acpi_gbl_FADT;
-ACPI_EXTERN acpi_table_header           *acpi_gbl_DSDT;
-ACPI_EXTERN acpi_common_facs            *acpi_gbl_FACS;
+ACPI_EXTERN RSDP_DESCRIPTOR            *acpi_gbl_RSDP;
+ACPI_EXTERN xsdt_descriptor            *acpi_gbl_XSDT;
+ACPI_EXTERN FADT_DESCRIPTOR            *acpi_gbl_FADT;
+ACPI_EXTERN acpi_table_header          *acpi_gbl_DSDT;
+ACPI_EXTERN FACS_DESCRIPTOR            *acpi_gbl_FACS;
+ACPI_EXTERN acpi_common_facs            acpi_gbl_common_fACS;
 
 /*
  * Since there may be multiple SSDTs and PSDTS, a single pointer is not
@@ -107,22 +108,18 @@
 ACPI_EXTERN ACPI_MEMORY_LIST            acpi_gbl_memory_lists[ACPI_NUM_MEM_LISTS];
 ACPI_EXTERN ACPI_OBJECT_NOTIFY_HANDLER  acpi_gbl_drv_notify;
 ACPI_EXTERN ACPI_OBJECT_NOTIFY_HANDLER  acpi_gbl_sys_notify;
-ACPI_EXTERN u8                         *acpi_gbl_gpe0enable_register_save;
-ACPI_EXTERN u8                         *acpi_gbl_gpe1_enable_register_save;
 ACPI_EXTERN acpi_walk_state            *acpi_gbl_breakpoint_walk;
 ACPI_EXTERN acpi_handle                 acpi_gbl_global_lock_semaphore;
 
 ACPI_EXTERN u32                         acpi_gbl_global_lock_thread_count;
-ACPI_EXTERN u32                         acpi_gbl_restore_acpi_chipset;
 ACPI_EXTERN u32                         acpi_gbl_original_mode;
-ACPI_EXTERN u32                         acpi_gbl_edge_level_save;
-ACPI_EXTERN u32                         acpi_gbl_irq_enable_save;
 ACPI_EXTERN u32                         acpi_gbl_rsdp_original_location;
 ACPI_EXTERN u32                         acpi_gbl_ns_lookup_count;
 ACPI_EXTERN u32                         acpi_gbl_ps_find_count;
 ACPI_EXTERN u16                         acpi_gbl_pm1_enable_register_save;
 ACPI_EXTERN u16                         acpi_gbl_next_table_owner_id;
 ACPI_EXTERN u16                         acpi_gbl_next_method_owner_id;
+ACPI_EXTERN u16                         acpi_gbl_global_lock_handle;
 ACPI_EXTERN u8                          acpi_gbl_debugger_configuration;
 ACPI_EXTERN u8                          acpi_gbl_global_lock_acquired;
 ACPI_EXTERN u8                          acpi_gbl_step_to_next_call;
@@ -130,7 +127,6 @@
 ACPI_EXTERN u8                          acpi_gbl_global_lock_present;
 
 extern u8                               acpi_gbl_shutdown;
-extern u32                              acpi_gbl_system_flags;
 extern u32                              acpi_gbl_startup_flags;
 extern const u8                         acpi_gbl_decode_to8bit[8];
 extern const NATIVE_CHAR                *acpi_gbl_db_sleep_states[ACPI_NUM_SLEEP_STATES];
@@ -150,14 +146,14 @@
 ACPI_EXTERN acpi_namespace_node        *acpi_gbl_root_node;
 
 extern const u8                         acpi_gbl_ns_properties[NUM_NS_TYPES];
-extern const predefined_names           acpi_gbl_pre_defined_names [NUM_PREDEFINED_NAMES];
+extern const acpi_predefined_names      acpi_gbl_pre_defined_names [NUM_PREDEFINED_NAMES];
 
 #ifdef ACPI_DEBUG
 ACPI_EXTERN u32                         acpi_gbl_current_node_count;
 ACPI_EXTERN u32                         acpi_gbl_current_node_size;
 ACPI_EXTERN u32                         acpi_gbl_max_concurrent_node_count;
-ACPI_EXTERN u32                         acpi_gbl_entry_stack_pointer;
-ACPI_EXTERN u32                         acpi_gbl_lowest_stack_pointer;
+ACPI_EXTERN ACPI_SIZE                   acpi_gbl_entry_stack_pointer;
+ACPI_EXTERN ACPI_SIZE                   acpi_gbl_lowest_stack_pointer;
 ACPI_EXTERN u32                         acpi_gbl_deepest_nesting;
 #endif
 
@@ -168,11 +164,7 @@
  ****************************************************************************/
 
 
-ACPI_EXTERN acpi_walk_list             *acpi_gbl_current_walk_list;
-
-/* Address Space handlers */
-
-ACPI_EXTERN acpi_adr_space_info         acpi_gbl_address_spaces[ACPI_NUM_ADDRESS_SPACES];
+ACPI_EXTERN ACPI_THREAD_STATE           *acpi_gbl_current_walk_list;
 
 /* Control method single step flag */
 
@@ -187,34 +179,41 @@
 
 ACPI_EXTERN acpi_parse_object           *acpi_gbl_parsed_namespace_root;
 
+/*****************************************************************************
+ *
+ * Hardware globals
+ *
+ ****************************************************************************/
+
+ACPI_EXTERN ACPI_BIT_REGISTER_INFO      acpi_gbl_bit_register_info[ACPI_NUM_BITREG];
+ACPI_EXTERN u8                          acpi_gbl_sleep_type_a;
+ACPI_EXTERN u8                          acpi_gbl_sleep_type_b;
+
 
 /*****************************************************************************
  *
- * Event globals
+ * Event and GPE globals
  *
  ****************************************************************************/
 
-ACPI_EXTERN acpi_fixed_event_info       acpi_gbl_fixed_event_handlers[ACPI_NUM_FIXED_EVENTS];
+extern      acpi_fixed_event_info       acpi_gbl_fixed_event_info[ACPI_NUM_FIXED_EVENTS];
+ACPI_EXTERN ACPI_FIXED_EVENT_HANDLER    acpi_gbl_fixed_event_handlers[ACPI_NUM_FIXED_EVENTS];
+
 ACPI_EXTERN acpi_handle                 acpi_gbl_gpe_obj_handle;
 ACPI_EXTERN u32                         acpi_gbl_gpe_register_count;
-ACPI_EXTERN acpi_gpe_registers         *acpi_gbl_gpe_registers;
-ACPI_EXTERN acpi_gpe_level_info        *acpi_gbl_gpe_info;
+ACPI_EXTERN u32                         acpi_gbl_gpe_number_max;
+ACPI_EXTERN ACPI_GPE_REGISTER_INFO     *acpi_gbl_gpe_register_info;
+ACPI_EXTERN ACPI_GPE_NUMBER_INFO       *acpi_gbl_gpe_number_info;
+ACPI_EXTERN ACPI_GPE_BLOCK_INFO         acpi_gbl_gpe_block_info[ACPI_MAX_GPE_BLOCKS];
 
 /*
- * Gpe validation and translation table
- * Indexed by the GPE number, returns GPE_INVALID if the GPE is not supported.
- * Otherwise, returns a valid index into the global GPE table.
+ * GPE translation table
+ * Indexed by the GPE number, returns a valid index into the global GPE tables.
  *
  * This table is needed because the GPE numbers supported by block 1 do not
  * have to be contiguous with the GPE numbers supported by block 0.
  */
-ACPI_EXTERN u8                          acpi_gbl_gpe_valid [ACPI_NUM_GPE];
-
-/* Acpi_event counter for debug only */
-
-#ifdef ACPI_DEBUG
-ACPI_EXTERN u32                         acpi_gbl_event_count[ACPI_NUM_FIXED_EVENTS];
-#endif
+ACPI_EXTERN ACPI_GPE_INDEX_INFO        *acpi_gbl_gpe_number_to_index;
 
 
 /*****************************************************************************
@@ -223,10 +222,58 @@
  *
  ****************************************************************************/
 
+
+ACPI_EXTERN u8                          acpi_gbl_db_output_flags;
+
+
 #ifdef ENABLE_DEBUGGER
+
 ACPI_EXTERN u8                          acpi_gbl_method_executing;
 ACPI_EXTERN u8                          acpi_gbl_db_terminate_threads;
-#endif
+
+ACPI_EXTERN int                         optind;
+ACPI_EXTERN NATIVE_CHAR                *optarg;
+ACPI_EXTERN u8                         *aml_start;
+ACPI_EXTERN u32                         aml_length;
+
+ACPI_EXTERN u8                          acpi_gbl_db_opt_tables;
+ACPI_EXTERN u8                          acpi_gbl_db_opt_disasm;
+ACPI_EXTERN u8                          acpi_gbl_db_opt_stats;
+ACPI_EXTERN u8                          acpi_gbl_db_opt_verbose;
+ACPI_EXTERN u8                          acpi_gbl_db_opt_ini_methods;
+
+
+ACPI_EXTERN NATIVE_CHAR                *acpi_gbl_db_args[ACPI_DEBUGGER_MAX_ARGS];
+ACPI_EXTERN NATIVE_CHAR                 acpi_gbl_db_line_buf[80];
+ACPI_EXTERN NATIVE_CHAR                 acpi_gbl_db_parsed_buf[80];
+ACPI_EXTERN NATIVE_CHAR                 acpi_gbl_db_scope_buf[40];
+ACPI_EXTERN NATIVE_CHAR                 acpi_gbl_db_debug_filename[40];
+ACPI_EXTERN u8                          acpi_gbl_db_output_to_file;
+ACPI_EXTERN NATIVE_CHAR                *acpi_gbl_db_buffer;
+ACPI_EXTERN NATIVE_CHAR                *acpi_gbl_db_filename;
+ACPI_EXTERN NATIVE_CHAR                *acpi_gbl_db_disasm_indent;
+ACPI_EXTERN u32                         acpi_gbl_db_debug_level;
+ACPI_EXTERN u32                         acpi_gbl_db_console_debug_level;
+ACPI_EXTERN acpi_table_header          *acpi_gbl_db_table_ptr;
+ACPI_EXTERN acpi_namespace_node        *acpi_gbl_db_scope_node;
+
+/*
+ * Statistic globals
+ */
+ACPI_EXTERN u16                         acpi_gbl_obj_type_count[INTERNAL_TYPE_NODE_MAX+1];
+ACPI_EXTERN u16                         acpi_gbl_node_type_count[INTERNAL_TYPE_NODE_MAX+1];
+ACPI_EXTERN u16                         acpi_gbl_obj_type_count_misc;
+ACPI_EXTERN u16                         acpi_gbl_node_type_count_misc;
+ACPI_EXTERN u32                         acpi_gbl_num_nodes;
+ACPI_EXTERN u32                         acpi_gbl_num_objects;
+
+
+ACPI_EXTERN u32                         acpi_gbl_size_of_parse_tree;
+ACPI_EXTERN u32                         acpi_gbl_size_of_method_trees;
+ACPI_EXTERN u32                         acpi_gbl_size_of_node_entries;
+ACPI_EXTERN u32                         acpi_gbl_size_of_acpi_objects;
+
+#endif /* ENABLE_DEBUGGER */
 
 
 #endif /* __ACGLOBAL_H__ */
diff -Nru a/drivers/acpi/include/achware.h b/drivers/acpi/include/achware.h
--- a/drivers/acpi/include/achware.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/achware.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: achware.h -- hardware specific interfaces
- *       $Revision: 56 $
+ *       $Revision: 58 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -60,13 +60,20 @@
 
 /* Register I/O Prototypes */
 
+ACPI_BIT_REGISTER_INFO *
+acpi_hw_get_bit_register_info (
+	u32                     register_id);
 
 u32
-acpi_hw_register_bit_access (
-	NATIVE_UINT             read_write,
-	u8                      use_lock,
+acpi_hw_bit_register_read (
+	u32                     register_id,
+	u32                     flags);
+
+u32
+acpi_hw_bit_register_write (
 	u32                     register_id,
-	... /* DWORD Write Value */);
+	u32                     value,
+	u32                     flags);
 
 u32
 acpi_hw_register_read (
@@ -96,10 +103,6 @@
 acpi_hw_clear_acpi_status (
    void);
 
-u32
-acpi_hw_get_bit_shift (
-	u32                     mask);
-
 
 /* GPE support */
 
@@ -140,7 +143,7 @@
 /* Sleep Prototypes */
 
 acpi_status
-acpi_hw_obtain_sleep_type_register_data (
+acpi_hw_get_sleep_type_data (
 	u8                      sleep_state,
 	u8                      *slp_typ_a,
 	u8                      *slp_typ_b);
diff -Nru a/drivers/acpi/include/acinterp.h b/drivers/acpi/include/acinterp.h
--- a/drivers/acpi/include/acinterp.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/acinterp.h	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acinterp.h - Interpreter subcomponent prototypes and defines
- *       $Revision: 116 $
+ *       $Revision: 132 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -27,24 +27,7 @@
 #define __ACINTERP_H__
 
 
-#define WALK_OPERANDS       &(walk_state->operands [walk_state->num_operands -1])
-
-
-/* Interpreter constants */
-
-#define AML_END_OF_BLOCK            -1
-#define PUSH_PKG_LENGTH             1
-#define DO_NOT_PUSH_PKG_LENGTH      0
-
-
-#define STACK_TOP                   0
-#define STACK_BOTTOM                (u32) -1
-
-/* Constants for global "When_to_parse_methods" */
-
-#define METHOD_PARSE_AT_INIT        0x0
-#define METHOD_PARSE_JUST_IN_TIME   0x1
-#define METHOD_DELETE_AT_COMPLETION 0x2
+#define ACPI_WALK_OPERANDS       (&(walk_state->operands [walk_state->num_operands -1]))
 
 
 acpi_status
@@ -55,7 +38,7 @@
 
 
 /*
- * amxface - External interpreter interfaces
+ * exxface - External interpreter interfaces
  */
 
 acpi_status
@@ -70,7 +53,7 @@
 
 
 /*
- * amconvrt - object conversion
+ * exconvrt - object conversion
  */
 
 acpi_status
@@ -95,13 +78,14 @@
 
 acpi_status
 acpi_ex_convert_to_target_type (
-	acpi_object_type8       destination_type,
-	acpi_operand_object     **obj_desc,
+	acpi_object_type        destination_type,
+	acpi_operand_object     *source_desc,
+	acpi_operand_object     **result_desc,
 	acpi_walk_state         *walk_state);
 
 
 /*
- * amfield - ACPI AML (p-code) execution - field manipulation
+ * exfield - ACPI AML (p-code) execution - field manipulation
  */
 
 acpi_status
@@ -117,52 +101,49 @@
 	u32                     buffer_length);
 
 acpi_status
-acpi_ex_setup_field (
+acpi_ex_setup_region (
 	acpi_operand_object     *obj_desc,
-	u32                     field_byte_offset);
+	u32                     field_datum_byte_offset);
 
 acpi_status
-acpi_ex_read_field_datum (
+acpi_ex_access_region (
 	acpi_operand_object     *obj_desc,
-	u32                     field_byte_offset,
-	u32                     *value);
+	u32                     field_datum_byte_offset,
+	acpi_integer            *value,
+	u32                     read_write);
 
-acpi_status
-acpi_ex_common_access_field (
-	u32                     mode,
+u8
+acpi_ex_register_overflow (
 	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length);
-
+	acpi_integer            value);
 
 acpi_status
-acpi_ex_access_index_field (
-	u32                     mode,
+acpi_ex_field_datum_io (
 	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length);
+	u32                     field_datum_byte_offset,
+	acpi_integer            *value,
+	u32                     read_write);
 
 acpi_status
-acpi_ex_access_bank_field (
-	u32                     mode,
+acpi_ex_write_with_update_rule (
 	acpi_operand_object     *obj_desc,
-	void                    *buffer,
-	u32                     buffer_length);
+	acpi_integer            mask,
+	acpi_integer            field_value,
+	u32                     field_datum_byte_offset);
 
-acpi_status
-acpi_ex_access_region_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
+void
+acpi_ex_get_buffer_datum(
+	acpi_integer            *datum,
 	void                    *buffer,
-	u32                     buffer_length);
-
+	u32                     byte_granularity,
+	u32                     offset);
 
-acpi_status
-acpi_ex_access_buffer_field (
-	u32                     mode,
-	acpi_operand_object     *obj_desc,
+void
+acpi_ex_set_buffer_datum (
+	acpi_integer            merged_datum,
 	void                    *buffer,
-	u32                     buffer_length);
+	u32                     byte_granularity,
+	u32                     offset);
 
 acpi_status
 acpi_ex_read_data_from_field (
@@ -175,7 +156,7 @@
 	acpi_operand_object     *obj_desc);
 
 /*
- * ammisc - ACPI AML (p-code) execution - specific opcodes
+ * exmisc - ACPI AML (p-code) execution - specific opcodes
  */
 
 acpi_status
@@ -197,6 +178,13 @@
 	acpi_walk_state         *walk_state);
 
 acpi_status
+acpi_ex_concat_template (
+	acpi_operand_object     *obj_desc,
+	acpi_operand_object     *obj_desc2,
+	acpi_operand_object     **actual_return_desc,
+	acpi_walk_state         *walk_state);
+
+acpi_status
 acpi_ex_do_concatenate (
 	acpi_operand_object     *obj_desc,
 	acpi_operand_object     *obj_desc2,
@@ -216,15 +204,6 @@
 	acpi_integer            operand1);
 
 acpi_status
-acpi_ex_load_op (
-	acpi_operand_object     *rgn_desc,
-	acpi_operand_object     *ddb_handle);
-
-acpi_status
-acpi_ex_unload_table (
-	acpi_operand_object     *ddb_handle);
-
-acpi_status
 acpi_ex_create_mutex (
 	acpi_walk_state         *walk_state);
 
@@ -263,7 +242,33 @@
 
 
 /*
- * ammutex - mutex support
+ * exconfig - dynamic table load/unload
+ */
+
+acpi_status
+acpi_ex_add_table (
+	acpi_table_header       *table,
+	acpi_namespace_node     *parent_node,
+	acpi_operand_object     **ddb_handle);
+
+acpi_status
+acpi_ex_load_op (
+	acpi_operand_object     *obj_desc,
+	acpi_operand_object     *target,
+	acpi_walk_state         *walk_state);
+
+acpi_status
+acpi_ex_load_table_op (
+	acpi_walk_state         *walk_state,
+	acpi_operand_object     **return_desc);
+
+acpi_status
+acpi_ex_unload_table (
+	acpi_operand_object     *ddb_handle);
+
+
+/*
+ * exmutex - mutex support
  */
 
 acpi_status
@@ -279,57 +284,35 @@
 
 acpi_status
 acpi_ex_release_all_mutexes (
-	acpi_operand_object     *mutex_list);
+	ACPI_THREAD_STATE       *thread);
 
 void
 acpi_ex_unlink_mutex (
 	acpi_operand_object     *obj_desc);
 
+void
+acpi_ex_link_mutex (
+	acpi_operand_object     *obj_desc,
+	ACPI_THREAD_STATE       *thread);
 
 /*
- * amprep - ACPI AML (p-code) execution - prep utilities
+ * exprep - ACPI AML (p-code) execution - prep utilities
  */
 
 acpi_status
 acpi_ex_prep_common_field_object (
 	acpi_operand_object     *obj_desc,
 	u8                      field_flags,
-	u32                     field_position,
-	u32                     field_length);
-
-acpi_status
-acpi_ex_prep_region_field_value (
-	acpi_namespace_node     *node,
-	acpi_handle             region,
-	u8                      field_flags,
-	u32                     field_position,
-	u32                     field_length);
-
-acpi_status
-acpi_ex_prep_bank_field_value (
-	acpi_namespace_node     *node,
-	acpi_namespace_node     *region_node,
-	acpi_namespace_node     *bank_register_node,
-	u32                     bank_val,
-	u8                      field_flags,
-	u32                     field_position,
-	u32                     field_length);
-
-acpi_status
-acpi_ex_prep_index_field_value (
-	acpi_namespace_node     *node,
-	acpi_namespace_node     *index_reg,
-	acpi_namespace_node     *data_reg,
-	u8                      field_flags,
-	u32                     field_position,
-	u32                     field_length);
+	u8                      field_attribute,
+	u32                     field_bit_position,
+	u32                     field_bit_length);
 
 acpi_status
 acpi_ex_prep_field_value (
 	ACPI_CREATE_FIELD_INFO  *info);
 
 /*
- * amsystem - Interface to OS services
+ * exsystem - Interface to OS services
  */
 
 acpi_status
@@ -337,11 +320,11 @@
 	acpi_operand_object     *value,
 	acpi_operand_object     *obj_desc);
 
-void
+acpi_status
 acpi_ex_system_do_suspend(
 	u32                     time);
 
-void
+acpi_status
 acpi_ex_system_do_stall (
 	u32                     time);
 
@@ -374,7 +357,7 @@
 
 
 /*
- * ammonadic - ACPI AML (p-code) execution, monadic operators
+ * exmonadic - ACPI AML (p-code) execution, monadic operators
  */
 
 acpi_status
@@ -394,7 +377,7 @@
 	acpi_walk_state         *walk_state);
 
 /*
- * amdyadic - ACPI AML (p-code) execution, dyadic operators
+ * exdyadic - ACPI AML (p-code) execution, dyadic operators
  */
 
 acpi_status
@@ -415,7 +398,7 @@
 
 
 /*
- * amresolv  - Object resolution and get value functions
+ * exresolv  - Object resolution and get value functions
  */
 
 acpi_status
@@ -433,14 +416,9 @@
 	acpi_operand_object     **stack_ptr,
 	acpi_walk_state         *walk_state);
 
-acpi_status
-acpi_ex_get_buffer_field_value (
-	acpi_operand_object     *field_desc,
-	acpi_operand_object     *result_desc);
-
 
 /*
- * amdump - Scanner debug output routines
+ * exdump - Scanner debug output routines
  */
 
 void
@@ -457,7 +435,7 @@
 void
 acpi_ex_dump_operands (
 	acpi_operand_object     **operands,
-	operating_mode          interpreter_mode,
+	acpi_interpreter_mode   interpreter_mode,
 	NATIVE_CHAR             *ident,
 	u32                     num_levels,
 	NATIVE_CHAR             *note,
@@ -477,7 +455,7 @@
 
 
 /*
- * amnames - interpreter/scanner name load/execute
+ * exnames - interpreter/scanner name load/execute
  */
 
 NATIVE_CHAR *
@@ -496,7 +474,7 @@
 
 acpi_status
 acpi_ex_get_name_string (
-	acpi_object_type8       data_type,
+	acpi_object_type        data_type,
 	u8                      *in_aml_address,
 	NATIVE_CHAR             **out_name_string,
 	u32                     *out_name_length);
@@ -504,11 +482,11 @@
 acpi_status
 acpi_ex_do_name (
 	acpi_object_type        data_type,
-	operating_mode          load_exec_mode);
+	acpi_interpreter_mode   load_exec_mode);
 
 
 /*
- * amstore - Object store support
+ * exstore - Object store support
  */
 
 acpi_status
@@ -529,42 +507,36 @@
 	acpi_namespace_node     *node,
 	acpi_walk_state         *walk_state);
 
-acpi_status
-acpi_ex_store_object_to_object (
-	acpi_operand_object     *source_desc,
-	acpi_operand_object     *dest_desc,
-	acpi_walk_state         *walk_state);
-
 
 /*
- *
+ * exstoren
  */
 
 acpi_status
 acpi_ex_resolve_object (
 	acpi_operand_object     **source_desc_ptr,
-	acpi_object_type8       target_type,
+	acpi_object_type        target_type,
 	acpi_walk_state         *walk_state);
 
 acpi_status
-acpi_ex_store_object (
+acpi_ex_store_object_to_object (
 	acpi_operand_object     *source_desc,
-	acpi_object_type8       target_type,
-	acpi_operand_object     **target_desc_ptr,
+	acpi_operand_object     *dest_desc,
+	acpi_operand_object     **new_desc,
 	acpi_walk_state         *walk_state);
 
 
 /*
- * amcopy - object copy
+ * excopy - object copy
  */
 
 acpi_status
-acpi_ex_copy_buffer_to_buffer (
+acpi_ex_store_buffer_to_buffer (
 	acpi_operand_object     *source_desc,
 	acpi_operand_object     *target_desc);
 
 acpi_status
-acpi_ex_copy_string_to_string (
+acpi_ex_store_string_to_string (
 	acpi_operand_object     *source_desc,
 	acpi_operand_object     *target_desc);
 
@@ -589,7 +561,7 @@
 	acpi_operand_object     *target_desc);
 
 /*
- * amutils - interpreter/scanner utilities
+ * exutils - interpreter/scanner utilities
  */
 
 acpi_status
@@ -634,7 +606,7 @@
 
 
 /*
- * amregion - default Op_region handlers
+ * exregion - default Op_region handlers
  */
 
 acpi_status
@@ -642,7 +614,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
@@ -651,7 +623,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
@@ -660,7 +632,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
@@ -669,7 +641,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
@@ -678,7 +650,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
@@ -687,7 +659,7 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
@@ -696,9 +668,18 @@
 	u32                     function,
 	ACPI_PHYSICAL_ADDRESS   address,
 	u32                     bit_width,
-	u32                     *value,
+	acpi_integer            *value,
 	void                    *handler_context,
 	void                    *region_context);
 
+
+acpi_status
+acpi_ex_data_table_space_handler (
+	u32                     function,
+	ACPI_PHYSICAL_ADDRESS   address,
+	u32                     bit_width,
+	acpi_integer            *value,
+	void                    *handler_context,
+	void                    *region_context);
 
 #endif /* __INTERP_H__ */
diff -Nru a/drivers/acpi/include/aclocal.h b/drivers/acpi/include/aclocal.h
--- a/drivers/acpi/include/aclocal.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/aclocal.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: aclocal.h - Internal data types used across the ACPI subsystem
- *       $Revision: 138 $
+ *       $Revision: 159 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -49,6 +49,7 @@
 #define ACPI_DESC_TYPE_STATE_WSCOPE     0x26
 #define ACPI_DESC_TYPE_STATE_RESULT     0x27
 #define ACPI_DESC_TYPE_STATE_NOTIFY     0x28
+#define ACPI_DESC_TYPE_STATE_THREAD     0x29
 #define ACPI_DESC_TYPE_WALK             0x44
 #define ACPI_DESC_TYPE_PARSER           0x66
 #define ACPI_DESC_TYPE_INTERNAL         0x88
@@ -138,10 +139,10 @@
 
 
 typedef u16                             acpi_owner_id;
-#define OWNER_TYPE_TABLE                0x0
-#define OWNER_TYPE_METHOD               0x1
-#define FIRST_METHOD_ID                 0x0000
-#define FIRST_TABLE_ID                  0x8000
+#define ACPI_OWNER_TYPE_TABLE           0x0
+#define ACPI_OWNER_TYPE_METHOD          0x1
+#define ACPI_FIRST_METHOD_ID            0x0000
+#define ACPI_FIRST_TABLE_ID             0x8000
 
 /* TBD: [Restructure] get rid of the need for this! */
 
@@ -166,11 +167,11 @@
 
 typedef enum
 {
-	IMODE_LOAD_PASS1                = 0x01,
-	IMODE_LOAD_PASS2                = 0x02,
-	IMODE_EXECUTE                   = 0x0E
+	ACPI_IMODE_LOAD_PASS1               = 0x01,
+	ACPI_IMODE_LOAD_PASS2               = 0x02,
+	ACPI_IMODE_EXECUTE                  = 0x0E
 
-} operating_mode;
+} acpi_interpreter_mode;
 
 
 /*
@@ -183,7 +184,7 @@
 
 typedef struct acpi_node
 {
-	u8                      data_type;
+	u8                      descriptor;     /* Used to differentiate object descriptor types */
 	u8                      type;           /* Type associated with this name */
 	u16                     owner_id;
 	u32                     name;           /* ACPI Name, always 4 chars per ACPI spec */
@@ -198,12 +199,12 @@
 } acpi_namespace_node;
 
 
-#define ENTRY_NOT_FOUND             NULL
+#define ACPI_ENTRY_NOT_FOUND            NULL
 
 
 /* Node flags */
 
-#define ANOBJ_AML_ATTACHMENT            0x01
+#define ANOBJ_RESERVED                  0x01
 #define ANOBJ_END_OF_PEER_LIST          0x02
 #define ANOBJ_DATA_WIDTH_32             0x04     /* Parent table is 64-bits */
 #define ANOBJ_METHOD_ARG                0x08
@@ -243,13 +244,13 @@
 	acpi_handle             *list;
 	u32                     *count;
 
-} find_context;
+} acpi_find_context;
 
 
 typedef struct
 {
 	acpi_namespace_node     *node;
-} ns_search_data;
+} acpi_ns_search_data;
 
 
 /*
@@ -258,10 +259,10 @@
 typedef struct
 {
 	NATIVE_CHAR             *name;
-	acpi_object_type8       type;
+	u8                      type;
 	NATIVE_CHAR             *val;
 
-} predefined_names;
+} acpi_predefined_names;
 
 
 /* Object types used during package copies */
@@ -297,20 +298,11 @@
 	u32                     field_bit_position;
 	u32                     field_bit_length;
 	u8                      field_flags;
+	u8                      attribute;
 	u8                      field_type;
 
 } ACPI_CREATE_FIELD_INFO;
 
-/*
- * Field flags: Bits 00 - 03 : Access_type (Any_acc, Byte_acc, etc.)
- *                   04      : Lock_rule (1 == Lock)
- *                   05 - 06 : Update_rule
- */
-
-#define FIELD_ACCESS_TYPE_MASK      0x0F
-#define FIELD_LOCK_RULE_MASK        0x10
-#define FIELD_UPDATE_RULE_MASK      0x60
-
 
 /*****************************************************************************
  *
@@ -318,38 +310,17 @@
  *
  ****************************************************************************/
 
-
-/* Status bits. */
-
-#define ACPI_STATUS_PMTIMER             0x0001
-#define ACPI_STATUS_BUSMASTER           0x0010
-#define ACPI_STATUS_GLOBAL              0x0020
-#define ACPI_STATUS_POWER_BUTTON        0x0100
-#define ACPI_STATUS_SLEEP_BUTTON        0x0200
-#define ACPI_STATUS_RTC_ALARM           0x0400
-
-/* Enable bits. */
-
-#define ACPI_ENABLE_PMTIMER             0x0001
-#define ACPI_ENABLE_GLOBAL              0x0020
-#define ACPI_ENABLE_POWER_BUTTON        0x0100
-#define ACPI_ENABLE_SLEEP_BUTTON        0x0200
-#define ACPI_ENABLE_RTC_ALARM           0x0400
-
-
-/*
- * Entry in the Address_space (AKA Operation Region) table
- */
+/* Information about each GPE register block */
 
 typedef struct
 {
-	acpi_adr_space_handler  handler;
-	void                    *context;
-
-} acpi_adr_space_info;
+	u16                     register_count;
+	u16                     block_address;
+	u8                      block_base_number;
 
+} ACPI_GPE_BLOCK_INFO;
 
-/* Values and addresses of the GPE registers (both banks) */
+/* Information about a particular GPE register pair */
 
 typedef struct
 {
@@ -358,9 +329,9 @@
 	u8                      status;         /* Current value of status reg */
 	u8                      enable;         /* Current value of enable reg */
 	u8                      wake_enable;    /* Mask of bits to keep enabled when sleeping */
-	u8                      gpe_base;       /* Base GPE number */
+	u8                      base_gpe_number; /* Base GPE number for this register */
 
-} acpi_gpe_registers;
+} ACPI_GPE_REGISTER_INFO;
 
 
 #define ACPI_GPE_LEVEL_TRIGGERED        1
@@ -371,14 +342,21 @@
 
 typedef struct
 {
-	u8                      type;           /* Level or Edge */
-
 	acpi_handle             method_handle;  /* Method handle for direct (fast) execution */
 	acpi_gpe_handler        handler;        /* Address of handler, if any */
 	void                    *context;       /* Context to be passed to handler */
+	u8                      type;           /* Level or Edge */
+	u8                      bit_mask;
+
+
+} ACPI_GPE_NUMBER_INFO;
+
 
-} acpi_gpe_level_info;
+typedef struct
+{
+	u8                      number_index;
 
+} ACPI_GPE_INDEX_INFO;
 
 /* Information about each particular fixed event */
 
@@ -387,9 +365,18 @@
 	acpi_event_handler      handler;        /* Address of handler. */
 	void                    *context;       /* Context to be passed to handler */
 
-} acpi_fixed_event_info;
+} ACPI_FIXED_EVENT_HANDLER;
 
 
+typedef struct
+{
+	u8                      status_register_id;
+	u8                      enable_register_id;
+	u16                     status_bit_mask;
+	u16                     enable_bit_mask;
+
+} acpi_fixed_event_info;
+
 /* Information used during field processing */
 
 typedef struct
@@ -408,16 +395,15 @@
  ****************************************************************************/
 
 
-#define CONTROL_NORMAL                  0xC0
-#define CONTROL_CONDITIONAL_EXECUTING   0xC1
-#define CONTROL_PREDICATE_EXECUTING     0xC2
-#define CONTROL_PREDICATE_FALSE         0xC3
-#define CONTROL_PREDICATE_TRUE          0xC4
+#define ACPI_CONTROL_NORMAL                  0xC0
+#define ACPI_CONTROL_CONDITIONAL_EXECUTING   0xC1
+#define ACPI_CONTROL_PREDICATE_EXECUTING     0xC2
+#define ACPI_CONTROL_PREDICATE_FALSE         0xC3
+#define ACPI_CONTROL_PREDICATE_TRUE          0xC4
 
 
 /* Forward declarations */
 struct acpi_walk_state;
-struct acpi_walk_list;
 struct acpi_parse_obj;
 struct acpi_obj_mutex;
 
@@ -471,7 +457,9 @@
 {
 	ACPI_STATE_COMMON
 	struct acpi_parse_obj   *predicate_op;
-	u8                      *aml_predicate_start; /* Start of if/while predicate */
+	u8                      *aml_predicate_start;   /* Start of if/while predicate */
+	u8                      *package_end;           /* End of if/while block */
+	u16                     opcode;
 
 } acpi_control_state;
 
@@ -490,16 +478,31 @@
 typedef struct acpi_pscope_state
 {
 	ACPI_STATE_COMMON
-	struct acpi_parse_obj   *op;            /* current op being parsed */
-	u8                      *arg_end;       /* current argument end */
-	u8                      *pkg_end;       /* current package end */
-	u32                     arg_list;       /* next argument to parse */
-	u32                     arg_count;      /* Number of fixed arguments */
+	struct acpi_parse_obj   *op;                    /* current op being parsed */
+	u8                      *arg_end;               /* current argument end */
+	u8                      *pkg_end;               /* current package end */
+	u32                     arg_list;               /* next argument to parse */
+	u32                     arg_count;              /* Number of fixed arguments */
 
 } acpi_pscope_state;
 
 
 /*
+ * Thread state - one per thread across multiple walk states.  Multiple walk
+ * states are created when there are nested control methods executing.
+ */
+typedef struct acpi_thread_state
+{
+	ACPI_STATE_COMMON
+	struct acpi_walk_state  *walk_state_list;       /* Head of list of Walk_states for this thread */
+	union acpi_operand_obj  *acquired_mutex_list;   /* List of all currently acquired mutexes */
+	u32                     thread_id;              /* Running thread ID */
+	u16                     current_sync_level;     /* Mutex Sync (nested acquire) level */
+
+} ACPI_THREAD_STATE;
+
+
+/*
  * Result values - used to accumulate the results of nested
  * AML arguments
  */
@@ -546,6 +549,7 @@
 	acpi_scope_state        scope;
 	acpi_pscope_state       parse_scope;
 	acpi_pkg_state          pkg;
+	ACPI_THREAD_STATE       thread;
 	acpi_result_values      results;
 	acpi_notify_info        notify;
 
@@ -574,16 +578,16 @@
  */
 typedef struct acpi_opcode_info
 {
+#ifdef _OPCODE_NAMES
+	NATIVE_CHAR             *name;          /* Opcode name (debug only) */
+#endif
 	u32                     parse_args;     /* Grammar/Parse time arguments */
 	u32                     runtime_args;   /* Interpret time arguments */
-	u16                     flags;          /* Misc flags */
+	u32                     flags;          /* Misc flags */
+	u8                      object_type;    /* Corresponding internal object type */
 	u8                      class;          /* Opcode class */
 	u8                      type;           /* Opcode type */
 
-#ifdef _OPCODE_NAMES
-	NATIVE_CHAR             *name;          /* op name (debug only) */
-#endif
-
 } acpi_opcode_info;
 
 
@@ -610,7 +614,7 @@
 	u32                     aml_offset;     /* offset of declaration in AML */\
 	struct acpi_parse_obj   *parent;        /* parent op */\
 	struct acpi_parse_obj   *next;          /* next op */\
-	DEBUG_ONLY_MEMBERS (\
+	ACPI_DEBUG_ONLY_MEMBERS (\
 	NATIVE_CHAR             op_name[16])    /* op name (debug only) */\
 			  /* NON-DEBUG members below: */\
 	acpi_namespace_node     *node;          /* for use by interpreter */\
@@ -652,153 +656,143 @@
 	u8                      *aml_end;       /* (last + 1) AML byte */
 	u8                      *pkg_start;     /* current package begin */
 	u8                      *pkg_end;       /* current package end */
-
 	struct acpi_parse_obj   *start_op;      /* root of parse tree */
 	struct acpi_node        *start_node;
 	union acpi_gen_state    *scope;         /* current scope */
+	struct acpi_parse_obj   *start_scope;
 
+} acpi_parse_state;
 
-	struct acpi_parse_obj   *start_scope;
 
+/* Parse object flags */
 
-} acpi_parse_state;
+#define ACPI_PARSEOP_GENERIC                    0x01
+#define ACPI_PARSEOP_NAMED                      0x02
+#define ACPI_PARSEOP_DEFERRED                   0x04
+#define ACPI_PARSEOP_BYTELIST                   0x08
+#define ACPI_PARSEOP_IN_CACHE                   0x80
 
 
 /*****************************************************************************
  *
- * Hardware and PNP
+ * Hardware (ACPI registers) and PNP
  *
  ****************************************************************************/
 
+#define PCI_ROOT_HID_STRING         "PNP0A03"
 
-/* PCI */
-#define PCI_ROOT_HID_STRING             "PNP0A03"
-
-/*
- * The #define's and enum below establish an abstract way of identifying what
- * register block and register is to be accessed.  Do not change any of the
- * values as they are used in switch statements and offset calculations.
- */
+typedef struct
+{
+	u8                      parent_register;
+	u8                      bit_position;
+	u16                     access_bit_mask;
 
-#define REGISTER_BLOCK_MASK             0xFF00  /* Register Block Id    */
-#define BIT_IN_REGISTER_MASK            0x00FF  /* Bit Id in the Register Block Id    */
-#define BYTE_IN_REGISTER_MASK           0x00FF  /* Register Offset in the Register Block    */
+} ACPI_BIT_REGISTER_INFO;
 
-#define REGISTER_BLOCK_ID(reg_id)       (reg_id & REGISTER_BLOCK_MASK)
-#define REGISTER_BIT_ID(reg_id)         (reg_id & BIT_IN_REGISTER_MASK)
-#define REGISTER_OFFSET(reg_id)         (reg_id & BYTE_IN_REGISTER_MASK)
 
 /*
- * Access Rule
- *  To access a Register Bit:
- *  -> Use Bit Name (= Register Block Id | Bit Id) defined in the enum.
- *
- *  To access a Register:
- *  -> Use Register Id (= Register Block Id | Register Offset)
+ * Register IDs
+ * These are the full ACPI registers
  */
+#define ACPI_REGISTER_PM1_STATUS                0x01
+#define ACPI_REGISTER_PM1_ENABLE                0x02
+#define ACPI_REGISTER_PM1_CONTROL               0x03
+#define ACPI_REGISTER_PM1A_CONTROL              0x04
+#define ACPI_REGISTER_PM1B_CONTROL              0x05
+#define ACPI_REGISTER_PM2_CONTROL               0x06
+#define ACPI_REGISTER_PM_TIMER                  0x07
+#define ACPI_REGISTER_PROCESSOR_BLOCK           0x08
+#define ACPI_REGISTER_SMI_COMMAND_BLOCK         0x09
 
 
 /*
- * Register Block Id
+ * Bit_register IDs
+ * These are bitfields defined within the full ACPI registers
  */
-#define PM1_STS                         0x0100
-#define PM1_EN                          0x0200
-#define PM1_CONTROL                     0x0300
-#define PM1A_CONTROL                    0x0400
-#define PM1B_CONTROL                    0x0500
-#define PM2_CONTROL                     0x0600
-#define PM_TIMER                        0x0700
-#define PROCESSOR_BLOCK                 0x0800
-#define GPE0_STS_BLOCK                  0x0900
-#define GPE0_EN_BLOCK                   0x0A00
-#define GPE1_STS_BLOCK                  0x0B00
-#define GPE1_EN_BLOCK                   0x0C00
-#define SMI_CMD_BLOCK                   0x0D00
+#define ACPI_BITREG_TIMER_STATUS                0x00
+#define ACPI_BITREG_BUS_MASTER_STATUS           0x01
+#define ACPI_BITREG_GLOBAL_LOCK_STATUS          0x02
+#define ACPI_BITREG_POWER_BUTTON_STATUS         0x03
+#define ACPI_BITREG_SLEEP_BUTTON_STATUS         0x04
+#define ACPI_BITREG_RT_CLOCK_STATUS             0x05
+#define ACPI_BITREG_WAKE_STATUS                 0x06
 
-/*
- * Address space bitmasks for mmio or io spaces
- */
+#define ACPI_BITREG_TIMER_ENABLE                0x07
+#define ACPI_BITREG_GLOBAL_LOCK_ENABLE          0x08
+#define ACPI_BITREG_POWER_BUTTON_ENABLE         0x09
+#define ACPI_BITREG_SLEEP_BUTTON_ENABLE         0x0A
+#define ACPI_BITREG_RT_CLOCK_ENABLE             0x0B
+#define ACPI_BITREG_WAKE_ENABLE                 0x0C
 
-#define SMI_CMD_ADDRESS_SPACE           0x01
-#define PM1_BLK_ADDRESS_SPACE           0x02
-#define PM2_CNT_BLK_ADDRESS_SPACE       0x04
-#define PM_TMR_BLK_ADDRESS_SPACE        0x08
-#define GPE0_BLK_ADDRESS_SPACE          0x10
-#define GPE1_BLK_ADDRESS_SPACE          0x20
+#define ACPI_BITREG_SCI_ENABLE                  0x0D
+#define ACPI_BITREG_BUS_MASTER_RLD              0x0E
+#define ACPI_BITREG_GLOBAL_LOCK_RELEASE         0x0F
+#define ACPI_BITREG_SLEEP_TYPE_A                0x10
+#define ACPI_BITREG_SLEEP_TYPE_B                0x11
+#define ACPI_BITREG_SLEEP_ENABLE                0x12
 
-/*
- * Control bit definitions
- */
-#define TMR_STS                         (PM1_STS | 0x01)
-#define BM_STS                          (PM1_STS | 0x02)
-#define GBL_STS                         (PM1_STS | 0x03)
-#define PWRBTN_STS                      (PM1_STS | 0x04)
-#define SLPBTN_STS                      (PM1_STS | 0x05)
-#define RTC_STS                         (PM1_STS | 0x06)
-#define WAK_STS                         (PM1_STS | 0x07)
-
-#define TMR_EN                          (PM1_EN | 0x01)
-			 /* no BM_EN */
-#define GBL_EN                          (PM1_EN | 0x03)
-#define PWRBTN_EN                       (PM1_EN | 0x04)
-#define SLPBTN_EN                       (PM1_EN | 0x05)
-#define RTC_EN                          (PM1_EN | 0x06)
-#define WAK_EN                          (PM1_EN | 0x07)
+#define ACPI_BITREG_ARB_DISABLE                 0x13
 
-#define SCI_EN                          (PM1_CONTROL | 0x01)
-#define BM_RLD                          (PM1_CONTROL | 0x02)
-#define GBL_RLS                         (PM1_CONTROL | 0x03)
-#define SLP_TYPE_A                      (PM1_CONTROL | 0x04)
-#define SLP_TYPE_B                      (PM1_CONTROL | 0x05)
-#define SLP_EN                          (PM1_CONTROL | 0x06)
+#define ACPI_BITREG_MAX                         0x13
+#define ACPI_NUM_BITREG                         ACPI_BITREG_MAX + 1
 
-#define ARB_DIS                         (PM2_CONTROL | 0x01)
 
-#define TMR_VAL                         (PM_TIMER | 0x01)
+/* Masks used to access the Bit_registers */
 
-#define GPE0_STS                        (GPE0_STS_BLOCK | 0x01)
-#define GPE0_EN                         (GPE0_EN_BLOCK  | 0x01)
+#define ACPI_BITMASK_TIMER_STATUS               0x0001
+#define ACPI_BITMASK_BUS_MASTER_STATUS          0x0010
+#define ACPI_BITMASK_GLOBAL_LOCK_STATUS         0x0020
+#define ACPI_BITMASK_POWER_BUTTON_STATUS        0x0100
+#define ACPI_BITMASK_SLEEP_BUTTON_STATUS        0x0200
+#define ACPI_BITMASK_RT_CLOCK_STATUS            0x0400
+#define ACPI_BITMASK_WAKE_STATUS                0x8000
 
-#define GPE1_STS                        (GPE1_STS_BLOCK | 0x01)
-#define GPE1_EN                         (GPE1_EN_BLOCK  | 0x01)
+#define ACPI_BITMASK_ALL_FIXED_STATUS           (ACPI_BITMASK_TIMER_STATUS          | \
+			 ACPI_BITMASK_BUS_MASTER_STATUS     | \
+			 ACPI_BITMASK_GLOBAL_LOCK_STATUS    | \
+			 ACPI_BITMASK_POWER_BUTTON_STATUS   | \
+			 ACPI_BITMASK_SLEEP_BUTTON_STATUS   | \
+			 ACPI_BITMASK_RT_CLOCK_STATUS       | \
+			 ACPI_BITMASK_WAKE_STATUS)
 
+#define ACPI_BITMASK_TIMER_ENABLE               0x0001
+#define ACPI_BITMASK_GLOBAL_LOCK_ENABLE         0x0020
+#define ACPI_BITMASK_POWER_BUTTON_ENABLE        0x0100
+#define ACPI_BITMASK_SLEEP_BUTTON_ENABLE        0x0200
+#define ACPI_BITMASK_RT_CLOCK_ENABLE            0x0400
 
-#define TMR_STS_MASK                    0x0001
-#define BM_STS_MASK                     0x0010
-#define GBL_STS_MASK                    0x0020
-#define PWRBTN_STS_MASK                 0x0100
-#define SLPBTN_STS_MASK                 0x0200
-#define RTC_STS_MASK                    0x0400
-#define WAK_STS_MASK                    0x8000
+#define ACPI_BITMASK_SCI_ENABLE                 0x0001
+#define ACPI_BITMASK_BUS_MASTER_RLD             0x0002
+#define ACPI_BITMASK_GLOBAL_LOCK_RELEASE        0x0004
+#define ACPI_BITMASK_SLEEP_TYPE_X               0x1C00
+#define ACPI_BITMASK_SLEEP_ENABLE               0x2000
 
-#define ALL_FIXED_STS_BITS              (TMR_STS_MASK   | BM_STS_MASK  | GBL_STS_MASK \
-					  | PWRBTN_STS_MASK | SLPBTN_STS_MASK \
-					  | RTC_STS_MASK | WAK_STS_MASK)
+#define ACPI_BITMASK_ARB_DISABLE                0x0001
 
-#define TMR_EN_MASK                     0x0001
-#define GBL_EN_MASK                     0x0020
-#define PWRBTN_EN_MASK                  0x0100
-#define SLPBTN_EN_MASK                  0x0200
-#define RTC_EN_MASK                     0x0400
 
-#define SCI_EN_MASK                     0x0001
-#define BM_RLD_MASK                     0x0002
-#define GBL_RLS_MASK                    0x0004
-#define SLP_TYPE_X_MASK                 0x1C00
-#define SLP_EN_MASK                     0x2000
+/* Raw bit position of each Bit_register */
 
-#define ARB_DIS_MASK                    0x0001
-#define TMR_VAL_MASK                    0xFFFFFFFF
+#define ACPI_BITPOSITION_TIMER_STATUS           0x00
+#define ACPI_BITPOSITION_BUS_MASTER_STATUS      0x04
+#define ACPI_BITPOSITION_GLOBAL_LOCK_STATUS     0x05
+#define ACPI_BITPOSITION_POWER_BUTTON_STATUS    0x08
+#define ACPI_BITPOSITION_SLEEP_BUTTON_STATUS    0x09
+#define ACPI_BITPOSITION_RT_CLOCK_STATUS        0x0A
+#define ACPI_BITPOSITION_WAKE_STATUS            0x0F
 
-#define GPE0_STS_MASK
-#define GPE0_EN_MASK
+#define ACPI_BITPOSITION_TIMER_ENABLE           0x00
+#define ACPI_BITPOSITION_GLOBAL_LOCK_ENABLE     0x05
+#define ACPI_BITPOSITION_POWER_BUTTON_ENABLE    0x08
+#define ACPI_BITPOSITION_SLEEP_BUTTON_ENABLE    0x09
+#define ACPI_BITPOSITION_RT_CLOCK_ENABLE        0x0A
 
-#define GPE1_STS_MASK
-#define GPE1_EN_MASK
+#define ACPI_BITPOSITION_SCI_ENABLE             0x00
+#define ACPI_BITPOSITION_BUS_MASTER_RLD         0x01
+#define ACPI_BITPOSITION_GLOBAL_LOCK_RELEASE    0x02
+#define ACPI_BITPOSITION_SLEEP_TYPE_X           0x0A
+#define ACPI_BITPOSITION_SLEEP_ENABLE           0x0D
 
-
-#define ACPI_READ                       1
-#define ACPI_WRITE                      2
+#define ACPI_BITPOSITION_ARB_DISABLE            0x00
 
 
 /*****************************************************************************
@@ -810,45 +804,45 @@
 
 /* Resource_type values */
 
-#define RESOURCE_TYPE_MEMORY_RANGE              0
-#define RESOURCE_TYPE_IO_RANGE                  1
-#define RESOURCE_TYPE_BUS_NUMBER_RANGE          2
+#define ACPI_RESOURCE_TYPE_MEMORY_RANGE         0
+#define ACPI_RESOURCE_TYPE_IO_RANGE             1
+#define ACPI_RESOURCE_TYPE_BUS_NUMBER_RANGE     2
 
 /* Resource descriptor types and masks */
 
-#define RESOURCE_DESC_TYPE_LARGE                0x80
-#define RESOURCE_DESC_TYPE_SMALL                0x00
+#define ACPI_RDESC_TYPE_LARGE                   0x80
+#define ACPI_RDESC_TYPE_SMALL                   0x00
 
-#define RESOURCE_DESC_TYPE_MASK                 0x80
-#define RESOURCE_DESC_SMALL_MASK                0x78        /* Only bits 6:3 contain the type */
+#define ACPI_RDESC_TYPE_MASK                    0x80
+#define ACPI_RDESC_SMALL_MASK                   0x78 /* Only bits 6:3 contain the type */
 
 
 /*
  * Small resource descriptor types
  * Note: The 3 length bits (2:0) must be zero
  */
-#define RESOURCE_DESC_IRQ_FORMAT                0x20
-#define RESOURCE_DESC_DMA_FORMAT                0x28
-#define RESOURCE_DESC_START_DEPENDENT           0x30
-#define RESOURCE_DESC_END_DEPENDENT             0x38
-#define RESOURCE_DESC_IO_PORT                   0x40
-#define RESOURCE_DESC_FIXED_IO_PORT             0x48
-#define RESOURCE_DESC_SMALL_VENDOR              0x70
-#define RESOURCE_DESC_END_TAG                   0x78
+#define ACPI_RDESC_TYPE_IRQ_FORMAT              0x20
+#define ACPI_RDESC_TYPE_DMA_FORMAT              0x28
+#define ACPI_RDESC_TYPE_START_DEPENDENT         0x30
+#define ACPI_RDESC_TYPE_END_DEPENDENT           0x38
+#define ACPI_RDESC_TYPE_IO_PORT                 0x40
+#define ACPI_RDESC_TYPE_FIXED_IO_PORT           0x48
+#define ACPI_RDESC_TYPE_SMALL_VENDOR            0x70
+#define ACPI_RDESC_TYPE_END_TAG                 0x78
 
 /*
  * Large resource descriptor types
  */
 
-#define RESOURCE_DESC_MEMORY_24                 0x81
-#define RESOURCE_DESC_GENERAL_REGISTER          0x82
-#define RESOURCE_DESC_LARGE_VENDOR              0x84
-#define RESOURCE_DESC_MEMORY_32                 0x85
-#define RESOURCE_DESC_FIXED_MEMORY_32           0x86
-#define RESOURCE_DESC_DWORD_ADDRESS_SPACE       0x87
-#define RESOURCE_DESC_WORD_ADDRESS_SPACE        0x88
-#define RESOURCE_DESC_EXTENDED_XRUPT            0x89
-#define RESOURCE_DESC_QWORD_ADDRESS_SPACE       0x8A
+#define ACPI_RDESC_TYPE_MEMORY_24               0x81
+#define ACPI_RDESC_TYPE_GENERAL_REGISTER        0x82
+#define ACPI_RDESC_TYPE_LARGE_VENDOR            0x84
+#define ACPI_RDESC_TYPE_MEMORY_32               0x85
+#define ACPI_RDESC_TYPE_FIXED_MEMORY_32         0x86
+#define ACPI_RDESC_TYPE_DWORD_ADDRESS_SPACE     0x87
+#define ACPI_RDESC_TYPE_WORD_ADDRESS_SPACE      0x88
+#define ACPI_RDESC_TYPE_EXTENDED_XRUPT          0x89
+#define ACPI_RDESC_TYPE_QWORD_ADDRESS_SPACE     0x8A
 
 
 /* String version of device HIDs and UIDs */
@@ -868,7 +862,7 @@
  *
  ****************************************************************************/
 
-#define ASCII_ZERO                      0x30
+#define ACPI_ASCII_ZERO                      0x30
 
 /*****************************************************************************
  *
@@ -885,7 +879,12 @@
 	u32                     num_loops;
 	NATIVE_CHAR             pathname[128];
 
-} db_method_info;
+} acpi_db_method_info;
+
+
+#define ACPI_DB_REDIRECTABLE_OUTPUT  0x01
+#define ACPI_DB_CONSOLE_OUTPUT       0x02
+#define ACPI_DB_DUPLICATE_OUTPUT     0x03
 
 
 /*****************************************************************************
@@ -905,10 +904,9 @@
 
 /* Entry for a memory allocation (debug only) */
 
-
-#define MEM_MALLOC                      0
-#define MEM_CALLOC                      1
-#define MAX_MODULE_NAME                 16
+#define ACPI_MEM_MALLOC                      0
+#define ACPI_MEM_CALLOC                      1
+#define ACPI_MAX_MODULE_NAME                 16
 
 #define ACPI_COMMON_DEBUG_MEM_HEADER \
 	struct acpi_debug_mem_block *previous; \
@@ -916,9 +914,8 @@
 	u32                         size; \
 	u32                         component; \
 	u32                         line; \
-	NATIVE_CHAR                 module[MAX_MODULE_NAME]; \
+	NATIVE_CHAR                 module[ACPI_MAX_MODULE_NAME]; \
 	u8                          alloc_type;
-
 
 typedef struct
 {
diff -Nru a/drivers/acpi/include/acmacros.h b/drivers/acpi/include/acmacros.h
--- a/drivers/acpi/include/acmacros.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acmacros.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acmacros.h - C macros for the entire subsystem.
- *       $Revision: 97 $
+ *       $Revision: 115 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,37 +31,10 @@
  * Data manipulation macros
  */
 
-#ifndef LOWORD
-#define LOWORD(l)                       ((u16)(NATIVE_UINT)(l))
-#endif
-
-#ifndef HIWORD
-#define HIWORD(l)                       ((u16)((((NATIVE_UINT)(l)) >> 16) & 0xFFFF))
-#endif
-
-#ifndef LOBYTE
-#define LOBYTE(l)                       ((u8)(u16)(l))
-#endif
-
-#ifndef HIBYTE
-#define HIBYTE(l)                       ((u8)((((u16)(l)) >> 8) & 0xFF))
-#endif
-
-#define BIT0(x)                         ((((x) & 0x01) > 0) ? 1 : 0)
-#define BIT1(x)                         ((((x) & 0x02) > 0) ? 1 : 0)
-#define BIT2(x)                         ((((x) & 0x04) > 0) ? 1 : 0)
-
-#define BIT3(x)                         ((((x) & 0x08) > 0) ? 1 : 0)
-#define BIT4(x)                         ((((x) & 0x10) > 0) ? 1 : 0)
-#define BIT5(x)                         ((((x) & 0x20) > 0) ? 1 : 0)
-#define BIT6(x)                         ((((x) & 0x40) > 0) ? 1 : 0)
-#define BIT7(x)                         ((((x) & 0x80) > 0) ? 1 : 0)
-
-#define LOW_BASE(w)                     ((u16) ((w) & 0x0000FFFF))
-#define MID_BASE(b)                     ((u8) (((b) & 0x00FF0000) >> 16))
-#define HI_BASE(b)                      ((u8) (((b) & 0xFF000000) >> 24))
-#define LOW_LIMIT(w)                    ((u16) ((w) & 0x0000FFFF))
-#define HI_LIMIT(b)                     ((u8) (((b) & 0x00FF0000) >> 16))
+#define ACPI_LOWORD(l)                  ((u16)(NATIVE_UINT)(l))
+#define ACPI_HIWORD(l)                  ((u16)((((NATIVE_UINT)(l)) >> 16) & 0xFFFF))
+#define ACPI_LOBYTE(l)                  ((u8)(u16)(l))
+#define ACPI_HIBYTE(l)                  ((u8)((((u16)(l)) >> 8) & 0xFF))
 
 
 #ifdef _IA16
@@ -69,13 +42,8 @@
  * For 16-bit addresses, we have to assume that the upper 32 bits
  * are zero.
  */
-#ifndef LODWORD
-#define LODWORD(l)                      (l)
-#endif
-
-#ifndef HIDWORD
-#define HIDWORD(l)                      (0)
-#endif
+#define ACPI_LODWORD(l)                 (l)
+#define ACPI_HIDWORD(l)                 (0)
 
 #define ACPI_GET_ADDRESS(a)             ((a).lo)
 #define ACPI_STORE_ADDRESS(a,b)         {(a).hi=0;(a).lo=(b);}
@@ -86,13 +54,8 @@
 /*
  * acpi_integer is 32-bits, no 64-bit support on this platform
  */
-#ifndef LODWORD
-#define LODWORD(l)                      ((u32)(l))
-#endif
-
-#ifndef HIDWORD
-#define HIDWORD(l)                      (0)
-#endif
+#define ACPI_LODWORD(l)                 ((u32)(l))
+#define ACPI_HIDWORD(l)                 (0)
 
 #define ACPI_GET_ADDRESS(a)             (a)
 #define ACPI_STORE_ADDRESS(a,b)         ((a)=(b))
@@ -103,13 +66,8 @@
 /*
  * Full 64-bit address/integer on both 32-bit and 64-bit platforms
  */
-#ifndef LODWORD
-#define LODWORD(l)                      ((u32)(u64)(l))
-#endif
-
-#ifndef HIDWORD
-#define HIDWORD(l)                      ((u32)(((*(uint64_struct *)(&l))).hi))
-#endif
+#define ACPI_LODWORD(l)                 ((u32)(u64)(l))
+#define ACPI_HIDWORD(l)                 ((u32)(((*(uint64_struct *)(&l))).hi))
 
 #define ACPI_GET_ADDRESS(a)             (a)
 #define ACPI_STORE_ADDRESS(a,b)         ((a)=(b))
@@ -121,13 +79,28 @@
   * Extract a byte of data using a pointer.  Any more than a byte and we
   * get into potential aligment issues -- see the STORE macros below
   */
-#define GET8(addr)                      (*(u8*)(addr))
+#define ACPI_GET8(addr)                 (*(u8*)(addr))
 
 /* Pointer arithmetic */
 
+#define ACPI_PTR_ADD(t,a,b)             (t *) ((char *)(a) + (b))
+#define ACPI_PTR_DIFF(a,b)              (NATIVE_UINT) ((char *)(a) - (char *)(b))
+
+/* Pointer/Integer type conversions */
 
-#define POINTER_ADD(t,a,b)              (t *) ((NATIVE_UINT)(a) + (NATIVE_UINT)(b))
-#define POINTER_DIFF(a,b)               ((u32) ((NATIVE_UINT)(a) - (NATIVE_UINT)(b)))
+#define ACPI_TO_POINTER(i)              ACPI_PTR_ADD (void,NULL,(NATIVE_UINT)i)
+#define ACPI_TO_INTEGER(p)              ACPI_PTR_DIFF (p,NULL)
+#define ACPI_OFFSET(d,o)                ((ACPI_SIZE) ACPI_TO_INTEGER (&(((d *)0)->o)))
+#define ACPI_FADT_OFFSET(o)             ACPI_OFFSET (FADT_DESCRIPTOR, o)
+
+
+#ifdef _IA16
+#define ACPI_PHYSADDR_TO_PTR(i)         (void *)(i)
+#define ACPI_PTR_TO_PHYSADDR(i)         (char *)(i)
+#else
+#define ACPI_PHYSADDR_TO_PTR(i)         ACPI_TO_POINTER(i)
+#define ACPI_PTR_TO_PHYSADDR(i)         ACPI_TO_INTEGER(i)
+#endif
 
 /*
  * Macros for moving data around to/from buffers that are possibly unaligned.
@@ -139,10 +112,10 @@
 
 /* The hardware supports unaligned transfers, just do the move */
 
-#define MOVE_UNALIGNED16_TO_16(d,s)     *(u16*)(d) = *(u16*)(s)
-#define MOVE_UNALIGNED32_TO_32(d,s)     *(u32*)(d) = *(u32*)(s)
-#define MOVE_UNALIGNED16_TO_32(d,s)     *(u32*)(d) = *(u16*)(s)
-#define MOVE_UNALIGNED64_TO_64(d,s)     *(u64*)(d) = *(u64*)(s)
+#define ACPI_MOVE_UNALIGNED16_TO_16(d,s)    *(u16 *)(d) = *(u16 *)(s)
+#define ACPI_MOVE_UNALIGNED32_TO_32(d,s)    *(u32 *)(d) = *(u32 *)(s)
+#define ACPI_MOVE_UNALIGNED16_TO_32(d,s)    *(u32 *)(d) = *(u16 *)(s)
+#define ACPI_MOVE_UNALIGNED64_TO_64(d,s)    *(u64 *)(d) = *(u64 *)(s)
 
 #else
 /*
@@ -151,24 +124,24 @@
  * the destination (or both) is/are unaligned.
  */
 
-#define MOVE_UNALIGNED16_TO_16(d,s)     {((u8 *)(d))[0] = ((u8 *)(s))[0];\
-	 ((u8 *)(d))[1] = ((u8 *)(s))[1];}
+#define ACPI_MOVE_UNALIGNED16_TO_16(d,s)    {((u8 *)(d))[0] = ((u8 *)(s))[0];\
+	  ((u8 *)(d))[1] = ((u8 *)(s))[1];}
 
-#define MOVE_UNALIGNED32_TO_32(d,s)     {((u8 *)(d))[0] = ((u8 *)(s))[0];\
-			  ((u8 *)(d))[1] = ((u8 *)(s))[1];\
-			  ((u8 *)(d))[2] = ((u8 *)(s))[2];\
-			  ((u8 *)(d))[3] = ((u8 *)(s))[3];}
-
-#define MOVE_UNALIGNED16_TO_32(d,s)     {(*(u32*)(d)) = 0; MOVE_UNALIGNED16_TO_16(d,s);}
-
-#define MOVE_UNALIGNED64_TO_64(d,s)     {((u8 *)(d))[0] = ((u8 *)(s))[0];\
-					   ((u8 *)(d))[1] = ((u8 *)(s))[1];\
-					   ((u8 *)(d))[2] = ((u8 *)(s))[2];\
-					   ((u8 *)(d))[3] = ((u8 *)(s))[3];\
-					   ((u8 *)(d))[4] = ((u8 *)(s))[4];\
-					   ((u8 *)(d))[5] = ((u8 *)(s))[5];\
-					   ((u8 *)(d))[6] = ((u8 *)(s))[6];\
-					   ((u8 *)(d))[7] = ((u8 *)(s))[7];}
+#define ACPI_MOVE_UNALIGNED32_TO_32(d,s)    {((u8 *)(d))[0] = ((u8 *)(s))[0];\
+			   ((u8 *)(d))[1] = ((u8 *)(s))[1];\
+			   ((u8 *)(d))[2] = ((u8 *)(s))[2];\
+			   ((u8 *)(d))[3] = ((u8 *)(s))[3];}
+
+#define ACPI_MOVE_UNALIGNED16_TO_32(d,s)    {(*(u32*)(d)) = 0; ACPI_MOVE_UNALIGNED16_TO_16(d,s);}
+
+#define ACPI_MOVE_UNALIGNED64_TO_64(d,s)    {((u8 *)(d))[0] = ((u8 *)(s))[0];\
+					 ((u8 *)(d))[1] = ((u8 *)(s))[1];\
+					 ((u8 *)(d))[2] = ((u8 *)(s))[2];\
+					 ((u8 *)(d))[3] = ((u8 *)(s))[3];\
+					 ((u8 *)(d))[4] = ((u8 *)(s))[4];\
+					 ((u8 *)(d))[5] = ((u8 *)(s))[5];\
+					 ((u8 *)(d))[6] = ((u8 *)(s))[6];\
+					 ((u8 *)(d))[7] = ((u8 *)(s))[7];}
 
 #endif
 
@@ -177,52 +150,50 @@
  * Fast power-of-two math macros for non-optimized compilers
  */
 
-#define _DIV(value,power_of2)           ((u32) ((value) >> (power_of2)))
-#define _MUL(value,power_of2)           ((u32) ((value) << (power_of2)))
-#define _MOD(value,divisor)             ((u32) ((value) & ((divisor) -1)))
-
-#define DIV_2(a)                        _DIV(a,1)
-#define MUL_2(a)                        _MUL(a,1)
-#define MOD_2(a)                        _MOD(a,2)
-
-#define DIV_4(a)                        _DIV(a,2)
-#define MUL_4(a)                        _MUL(a,2)
-#define MOD_4(a)                        _MOD(a,4)
-
-#define DIV_8(a)                        _DIV(a,3)
-#define MUL_8(a)                        _MUL(a,3)
-#define MOD_8(a)                        _MOD(a,8)
-
-#define DIV_16(a)                       _DIV(a,4)
-#define MUL_16(a)                       _MUL(a,4)
-#define MOD_16(a)                       _MOD(a,16)
+#define _ACPI_DIV(value,power_of2)      ((u32) ((value) >> (power_of2)))
+#define _ACPI_MUL(value,power_of2)      ((u32) ((value) << (power_of2)))
+#define _ACPI_MOD(value,divisor)        ((u32) ((value) & ((divisor) -1)))
+
+#define ACPI_DIV_2(a)                   _ACPI_DIV(a,1)
+#define ACPI_MUL_2(a)                   _ACPI_MUL(a,1)
+#define ACPI_MOD_2(a)                   _ACPI_MOD(a,2)
+
+#define ACPI_DIV_4(a)                   _ACPI_DIV(a,2)
+#define ACPI_MUL_4(a)                   _ACPI_MUL(a,2)
+#define ACPI_MOD_4(a)                   _ACPI_MOD(a,4)
+
+#define ACPI_DIV_8(a)                   _ACPI_DIV(a,3)
+#define ACPI_MUL_8(a)                   _ACPI_MUL(a,3)
+#define ACPI_MOD_8(a)                   _ACPI_MOD(a,8)
+
+#define ACPI_DIV_16(a)                  _ACPI_DIV(a,4)
+#define ACPI_MUL_16(a)                  _ACPI_MUL(a,4)
+#define ACPI_MOD_16(a)                  _ACPI_MOD(a,16)
 
 
 /*
  * Rounding macros (Power of two boundaries only)
  */
-#define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
-#define ROUND_UP(value,boundary)        (((value) + ((boundary)-1)) & (~((boundary)-1)))
+#define ACPI_ROUND_DOWN(value,boundary)      (((NATIVE_UINT)(value)) & (~((boundary)-1)))
+#define ACPI_ROUND_UP(value,boundary)        ((((NATIVE_UINT)(value)) + ((boundary)-1)) & (~((boundary)-1)))
 
-#define ROUND_DOWN_TO_32_BITS(a)        ROUND_DOWN(a,4)
-#define ROUND_DOWN_TO_64_BITS(a)        ROUND_DOWN(a,8)
-#define ROUND_DOWN_TO_NATIVE_WORD(a)    ROUND_DOWN(a,ALIGNED_ADDRESS_BOUNDARY)
+#define ACPI_ROUND_DOWN_TO_32_BITS(a)        ACPI_ROUND_DOWN(a,4)
+#define ACPI_ROUND_DOWN_TO_64_BITS(a)        ACPI_ROUND_DOWN(a,8)
+#define ACPI_ROUND_DOWN_TO_NATIVE_WORD(a)    ACPI_ROUND_DOWN(a,ALIGNED_ADDRESS_BOUNDARY)
 
-#define ROUND_UP_TO_32_bITS(a)          ROUND_UP(a,4)
-#define ROUND_UP_TO_64_bITS(a)          ROUND_UP(a,8)
-#define ROUND_UP_TO_NATIVE_WORD(a)      ROUND_UP(a,ALIGNED_ADDRESS_BOUNDARY)
+#define ACPI_ROUND_UP_TO_32_bITS(a)          ACPI_ROUND_UP(a,4)
+#define ACPI_ROUND_UP_TO_64_bITS(a)          ACPI_ROUND_UP(a,8)
+#define ACPI_ROUND_UP_TO_NATIVE_WORD(a)      ACPI_ROUND_UP(a,ALIGNED_ADDRESS_BOUNDARY)
 
-#define ROUND_PTR_UP_TO_4(a,b)          ((b *)(((NATIVE_UINT)(a) + 3) & ~3))
-#define ROUND_PTR_UP_TO_8(a,b)          ((b *)(((NATIVE_UINT)(a) + 7) & ~7))
 
-#define ROUND_BITS_UP_TO_BYTES(a)       DIV_8((a) + 7)
-#define ROUND_BITS_DOWN_TO_BYTES(a)     DIV_8((a))
+#define ACPI_ROUND_BITS_UP_TO_BYTES(a)       ACPI_DIV_8((a) + 7)
+#define ACPI_ROUND_BITS_DOWN_TO_BYTES(a)     ACPI_DIV_8((a))
 
-#define ROUND_UP_TO_1K(a)               (((a) + 1023) >> 10)
+#define ACPI_ROUND_UP_TO_1K(a)               (((a) + 1023) >> 10)
 
 /* Generic (non-power-of-two) rounding */
 
-#define ROUND_UP_TO(value,boundary)     (((value) + ((boundary)-1)) / (boundary))
+#define ACPI_ROUND_UP_TO(value,boundary)     (((value) + ((boundary)-1)) / (boundary))
 
 /*
  * Bitmask creation
@@ -230,9 +201,10 @@
  * MASK_BITS_ABOVE creates a mask starting AT the position and above
  * MASK_BITS_BELOW creates a mask starting one bit BELOW the position
  */
-#define MASK_BITS_ABOVE(position)       (~(((u32)(-1)) << ((u32) (position))))
-#define MASK_BITS_BELOW(position)       (((u32)(-1)) << ((u32) (position)))
+#define ACPI_MASK_BITS_ABOVE(position)       (~(((acpi_integer)(-1)) << ((u32) (position))))
+#define ACPI_MASK_BITS_BELOW(position)       (((acpi_integer)(-1)) << ((u32) (position)))
 
+#define ACPI_IS_OCTAL_DIGIT(d)               (((char)(d) >= '0') && ((char)(d) <= '7'))
 
 /* Macros for GAS addressing */
 
@@ -256,23 +228,30 @@
 
 #endif
 
+
+/* Bitfields within ACPI registers */
+
+#define ACPI_REGISTER_PREPARE_BITS(val, pos, mask)      ((val << pos) & mask)
+#define ACPI_REGISTER_INSERT_VALUE(reg, pos, mask, val)  reg = (reg & (~(mask))) | ACPI_REGISTER_PREPARE_BITS(val, pos, mask)
+
 /*
- * An acpi_handle (which is actually an acpi_namespace_node *) can appear in some contexts,
- * such as on ap_obj_stack, where a pointer to an acpi_operand_object can also
+ * An acpi_namespace_node * can appear in some contexts,
+ * where a pointer to an acpi_operand_object  can also
  * appear.  This macro is used to distinguish them.
  *
- * The Data_type field is the first field in both structures.
+ * The "Descriptor" field is the first field in both structures.
  */
-#define VALID_DESCRIPTOR_TYPE(d,t)      (((acpi_namespace_node *)d)->data_type == t)
+#define ACPI_GET_DESCRIPTOR_TYPE(d)     (((acpi_namespace_node *)d)->descriptor)
+#define ACPI_SET_DESCRIPTOR_TYPE(d,t)   (((acpi_namespace_node *)d)->descriptor = t)
 
 
 /* Macro to test the object type */
 
-#define IS_THIS_OBJECT_TYPE(d,t)        (((acpi_operand_object  *)d)->common.type == (u8)t)
+#define ACPI_GET_OBJECT_TYPE(d)         (((acpi_operand_object *)d)->common.type)
 
 /* Macro to check the table flags for SINGLE or MULTIPLE tables are allowed */
 
-#define IS_SINGLE_TABLE(x)              (((x) & 0x01) == ACPI_TABLE_SINGLE ? 1 : 0)
+#define ACPI_IS_SINGLE_TABLE(x)         (((x) & 0x01) == ACPI_TABLE_SINGLE ? 1 : 0)
 
 /*
  * Macro to check if a pointer is within an ACPI table.
@@ -281,11 +260,11 @@
  * and ((u8 *)b+b->Length) points one byte past the end of the table.
  */
 #ifndef _IA16
-#define IS_IN_ACPI_TABLE(a,b)           (((u8 *)(a) >= (u8 *)(b + 1)) &&\
-							   ((u8 *)(a) < ((u8 *)b + b->length)))
+#define ACPI_IS_IN_ACPI_TABLE(a,b)      (((u8 *)(a) >= (u8 *)(b + 1)) &&\
+							 ((u8 *)(a) < ((u8 *)b + b->length)))
 
 #else
-#define IS_IN_ACPI_TABLE(a,b)           (_segment)(a) == (_segment)(b) &&\
+#define ACPI_IS_IN_ACPI_TABLE(a,b)      (_segment)(a) == (_segment)(b) &&\
 									 (((u8 *)(a) >= (u8 *)(b + 1)) &&\
 									 ((u8 *)(a) < ((u8 *)b + b->length)))
 #endif
@@ -294,9 +273,9 @@
  * Macros for the master AML opcode table
  */
 #ifdef ACPI_DEBUG
-#define ACPI_OP(name,Pargs,Iargs,class,type,flags)     {Pargs,Iargs,flags,class,type,name}
+#define ACPI_OP(name,Pargs,Iargs,obj_type,class,type,flags)    {name,Pargs,Iargs,flags,obj_type,class,type}
 #else
-#define ACPI_OP(name,Pargs,Iargs,class,type,flags)     {Pargs,Iargs,flags,class,type}
+#define ACPI_OP(name,Pargs,Iargs,obj_type,class,type,flags)    {Pargs,Iargs,flags,obj_type,class,type}
 #endif
 
 #define ARG_TYPE_WIDTH                  5
@@ -335,7 +314,7 @@
  * 5) Expand address to 64 bits
  */
 #define ASL_BUILD_GAS_FROM_ENTRY(a,b,c,d)   {a.address_space_id = (u8) d;\
-											 a.register_bit_width = (u8) MUL_8 (b);\
+											 a.register_bit_width = (u8) ACPI_MUL_8 (b);\
 											 a.register_bit_offset = 0;\
 											 a.reserved = 0;\
 											 ACPI_STORE_ADDRESS (a.address,c);}
@@ -349,7 +328,7 @@
  * Reporting macros that are never compiled out
  */
 
-#define PARAM_LIST(pl)                  pl
+#define ACPI_PARAM_LIST(pl)                  pl
 
 /*
  * Error reporting.  These versions add callers module and line#.  Since
@@ -359,32 +338,32 @@
 
 #ifdef ACPI_DEBUG
 
-#define REPORT_INFO(fp)                 {acpi_ut_report_info(_THIS_MODULE,__LINE__,_COMPONENT); \
-											acpi_os_printf PARAM_LIST(fp);}
-#define REPORT_ERROR(fp)                {acpi_ut_report_error(_THIS_MODULE,__LINE__,_COMPONENT); \
-											acpi_os_printf PARAM_LIST(fp);}
-#define REPORT_WARNING(fp)              {acpi_ut_report_warning(_THIS_MODULE,__LINE__,_COMPONENT); \
-											acpi_os_printf PARAM_LIST(fp);}
+#define ACPI_REPORT_INFO(fp)                {acpi_ut_report_info(_THIS_MODULE,__LINE__,_COMPONENT); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
+#define ACPI_REPORT_ERROR(fp)               {acpi_ut_report_error(_THIS_MODULE,__LINE__,_COMPONENT); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
+#define ACPI_REPORT_WARNING(fp)             {acpi_ut_report_warning(_THIS_MODULE,__LINE__,_COMPONENT); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
 
 #else
 
-#define REPORT_INFO(fp)                 {acpi_ut_report_info("ACPI",__LINE__,_COMPONENT); \
-											acpi_os_printf PARAM_LIST(fp);}
-#define REPORT_ERROR(fp)                {acpi_ut_report_error("ACPI",__LINE__,_COMPONENT); \
-											acpi_os_printf PARAM_LIST(fp);}
-#define REPORT_WARNING(fp)              {acpi_ut_report_warning("ACPI",__LINE__,_COMPONENT); \
-											acpi_os_printf PARAM_LIST(fp);}
+#define ACPI_REPORT_INFO(fp)                {acpi_ut_report_info("ACPI",__LINE__,_COMPONENT); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
+#define ACPI_REPORT_ERROR(fp)               {acpi_ut_report_error("ACPI",__LINE__,_COMPONENT); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
+#define ACPI_REPORT_WARNING(fp)             {acpi_ut_report_warning("ACPI",__LINE__,_COMPONENT); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
 
 #endif
 
 /* Error reporting.  These versions pass thru the module and line# */
 
-#define _REPORT_INFO(a,b,c,fp)          {acpi_ut_report_info(a,b,c); \
-											acpi_os_printf PARAM_LIST(fp);}
-#define _REPORT_ERROR(a,b,c,fp)         {acpi_ut_report_error(a,b,c); \
-											acpi_os_printf PARAM_LIST(fp);}
-#define _REPORT_WARNING(a,b,c,fp)       {acpi_ut_report_warning(a,b,c); \
-											acpi_os_printf PARAM_LIST(fp);}
+#define _ACPI_REPORT_INFO(a,b,c,fp)         {acpi_ut_report_info(a,b,c); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
+#define _ACPI_REPORT_ERROR(a,b,c,fp)        {acpi_ut_report_error(a,b,c); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
+#define _ACPI_REPORT_WARNING(a,b,c,fp)      {acpi_ut_report_warning(a,b,c); \
+												acpi_os_printf ACPI_PARAM_LIST(fp);}
 
 /*
  * Debug macros that are conditionally compiled
@@ -392,7 +371,7 @@
 
 #ifdef ACPI_DEBUG
 
-#define MODULE_NAME(name)               static char *_THIS_MODULE = name;
+#define ACPI_MODULE_NAME(name)               static char *_THIS_MODULE = name;
 
 /*
  * Function entry tracing.
@@ -400,21 +379,21 @@
  * as a local string ("_Proc_name) so that it can be also used by the function exit macros below.
  */
 
-#define PROC_NAME(a)                    acpi_debug_print_info _dbg;     \
+#define ACPI_FUNCTION_NAME(a)           acpi_debug_print_info _dbg;     \
 										_dbg.component_id = _COMPONENT; \
 										_dbg.proc_name   = a;           \
 										_dbg.module_name = _THIS_MODULE;
 
-#define FUNCTION_TRACE(a)               PROC_NAME(a)\
-										acpi_ut_trace(__LINE__,&_dbg)
-#define FUNCTION_TRACE_PTR(a,b)         PROC_NAME(a)\
-										acpi_ut_trace_ptr(__LINE__,&_dbg,(void *)b)
-#define FUNCTION_TRACE_U32(a,b)         PROC_NAME(a)\
-										acpi_ut_trace_u32(__LINE__,&_dbg,(u32)b)
-#define FUNCTION_TRACE_STR(a,b)         PROC_NAME(a)\
-										acpi_ut_trace_str(__LINE__,&_dbg,(NATIVE_CHAR *)b)
+#define ACPI_FUNCTION_TRACE(a)          ACPI_FUNCTION_NAME(a)\
+											acpi_ut_trace(__LINE__,&_dbg)
+#define ACPI_FUNCTION_TRACE_PTR(a,b)    ACPI_FUNCTION_NAME(a)\
+											acpi_ut_trace_ptr(__LINE__,&_dbg,(void *)b)
+#define ACPI_FUNCTION_TRACE_U32(a,b)    ACPI_FUNCTION_NAME(a)\
+											acpi_ut_trace_u32(__LINE__,&_dbg,(u32)b)
+#define ACPI_FUNCTION_TRACE_STR(a,b)    ACPI_FUNCTION_NAME(a)\
+											acpi_ut_trace_str(__LINE__,&_dbg,(NATIVE_CHAR *)b)
 
-#define FUNCTION_ENTRY()                acpi_ut_track_stack_ptr()
+#define ACPI_FUNCTION_ENTRY()           acpi_ut_track_stack_ptr()
 
 /*
  * Function exit tracing.
@@ -431,38 +410,39 @@
 
 /* Conditional execution */
 
-#define DEBUG_EXEC(a)                   a
-#define NORMAL_EXEC(a)
+#define ACPI_DEBUG_EXEC(a)              a
+#define ACPI_NORMAL_EXEC(a)
 
-#define DEBUG_DEFINE(a)                 a;
-#define DEBUG_ONLY_MEMBERS(a)           a;
+#define ACPI_DEBUG_DEFINE(a)            a;
+#define ACPI_DEBUG_ONLY_MEMBERS(a)      a;
 #define _OPCODE_NAMES
 #define _VERBOSE_STRUCTURES
 
 
 /* Stack and buffer dumping */
 
-#define DUMP_STACK_ENTRY(a)             acpi_ex_dump_operand(a)
-#define DUMP_OPERANDS(a,b,c,d,e)        acpi_ex_dump_operands(a,b,c,d,e,_THIS_MODULE,__LINE__)
+#define ACPI_DUMP_STACK_ENTRY(a)        acpi_ex_dump_operand(a)
+#define ACPI_DUMP_OPERANDS(a,b,c,d,e)   acpi_ex_dump_operands(a,b,c,d,e,_THIS_MODULE,__LINE__)
 
 
-#define DUMP_ENTRY(a,b)                 acpi_ns_dump_entry (a,b)
-#define DUMP_TABLES(a,b)                acpi_ns_dump_tables(a,b)
-#define DUMP_PATHNAME(a,b,c,d)          acpi_ns_dump_pathname(a,b,c,d)
-#define DUMP_RESOURCE_LIST(a)           acpi_rs_dump_resource_list(a)
-#define DUMP_BUFFER(a,b)                acpi_ut_dump_buffer((u8 *)a,b,DB_BYTE_DISPLAY,_COMPONENT)
-#define BREAK_MSG(a)                    acpi_os_signal (ACPI_SIGNAL_BREAKPOINT,(a))
+#define ACPI_DUMP_ENTRY(a,b)            acpi_ns_dump_entry (a,b)
+#define ACPI_DUMP_TABLES(a,b)           acpi_ns_dump_tables(a,b)
+#define ACPI_DUMP_PATHNAME(a,b,c,d)     acpi_ns_dump_pathname(a,b,c,d)
+#define ACPI_DUMP_RESOURCE_LIST(a)      acpi_rs_dump_resource_list(a)
+#define ACPI_DUMP_BUFFER(a,b)           acpi_ut_dump_buffer((u8 *)a,b,DB_BYTE_DISPLAY,_COMPONENT)
+#define ACPI_BREAK_MSG(a)               acpi_os_signal (ACPI_SIGNAL_BREAKPOINT,(a))
 
 
 /*
  * Generate INT3 on ACPI_ERROR (Debug only!)
  */
 
-#define ERROR_BREAK
-#ifdef  ERROR_BREAK
-#define BREAK_ON_ERROR(lvl)              if ((lvl)&ACPI_ERROR) acpi_os_signal(ACPI_SIGNAL_BREAKPOINT,"Fatal error encountered\n")
+#define ACPI_ERROR_BREAK
+#ifdef  ACPI_ERROR_BREAK
+#define ACPI_BREAK_ON_ERROR(lvl)        if ((lvl)&ACPI_ERROR) \
+											acpi_os_signal(ACPI_SIGNAL_BREAKPOINT,"Fatal error encountered\n")
 #else
-#define BREAK_ON_ERROR(lvl)
+#define ACPI_BREAK_ON_ERROR(lvl)
 #endif
 
 /*
@@ -472,8 +452,8 @@
  *    2) Debug error level or trace level for the print statement is enabled
  */
 
-#define ACPI_DEBUG_PRINT(pl)            acpi_ut_debug_print PARAM_LIST(pl)
-#define ACPI_DEBUG_PRINT_RAW(pl)        acpi_ut_debug_print_raw PARAM_LIST(pl)
+#define ACPI_DEBUG_PRINT(pl)            acpi_ut_debug_print ACPI_PARAM_LIST(pl)
+#define ACPI_DEBUG_PRINT_RAW(pl)        acpi_ut_debug_print_raw ACPI_PARAM_LIST(pl)
 
 
 #else
@@ -482,33 +462,33 @@
  * leaving no executable debug code!
  */
 
-#define MODULE_NAME(name)
+#define ACPI_MODULE_NAME(name)
 #define _THIS_MODULE ""
 
-#define DEBUG_EXEC(a)
-#define NORMAL_EXEC(a)                  a;
+#define ACPI_DEBUG_EXEC(a)
+#define ACPI_NORMAL_EXEC(a)             a;
 
-#define DEBUG_DEFINE(a)
-#define DEBUG_ONLY_MEMBERS(a)
-#define PROC_NAME(a)
-#define FUNCTION_TRACE(a)
-#define FUNCTION_TRACE_PTR(a,b)
-#define FUNCTION_TRACE_U32(a,b)
-#define FUNCTION_TRACE_STR(a,b)
-#define FUNCTION_EXIT
-#define FUNCTION_STATUS_EXIT(s)
-#define FUNCTION_VALUE_EXIT(s)
-#define FUNCTION_ENTRY()
-#define DUMP_STACK_ENTRY(a)
-#define DUMP_OPERANDS(a,b,c,d,e)
-#define DUMP_ENTRY(a,b)
-#define DUMP_TABLES(a,b)
-#define DUMP_PATHNAME(a,b,c,d)
-#define DUMP_RESOURCE_LIST(a)
-#define DUMP_BUFFER(a,b)
+#define ACPI_DEBUG_DEFINE(a)
+#define ACPI_DEBUG_ONLY_MEMBERS(a)
+#define ACPI_FUNCTION_NAME(a)
+#define ACPI_FUNCTION_TRACE(a)
+#define ACPI_FUNCTION_TRACE_PTR(a,b)
+#define ACPI_FUNCTION_TRACE_U32(a,b)
+#define ACPI_FUNCTION_TRACE_STR(a,b)
+#define ACPI_FUNCTION_EXIT
+#define ACPI_FUNCTION_STATUS_EXIT(s)
+#define ACPI_FUNCTION_VALUE_EXIT(s)
+#define ACPI_FUNCTION_ENTRY()
+#define ACPI_DUMP_STACK_ENTRY(a)
+#define ACPI_DUMP_OPERANDS(a,b,c,d,e)
+#define ACPI_DUMP_ENTRY(a,b)
+#define ACPI_DUMP_TABLES(a,b)
+#define ACPI_DUMP_PATHNAME(a,b,c,d)
+#define ACPI_DUMP_RESOURCE_LIST(a)
+#define ACPI_DUMP_BUFFER(a,b)
 #define ACPI_DEBUG_PRINT(pl)
 #define ACPI_DEBUG_PRINT_RAW(pl)
-#define BREAK_MSG(a)
+#define ACPI_BREAK_MSG(a)
 
 #define return_VOID                     return
 #define return_ACPI_STATUS(s)           return(s)
@@ -523,9 +503,9 @@
  * DEBUG_PRINT stuff (set by ACPI_DEBUG) is on, or not.
  */
 #ifdef ENABLE_DEBUGGER
-#define DEBUGGER_EXEC(a)                a
+#define ACPI_DEBUGGER_EXEC(a)           a
 #else
-#define DEBUGGER_EXEC(a)
+#define ACPI_DEBUGGER_EXEC(a)
 #endif
 
 
@@ -534,9 +514,9 @@
  * we are using ACPI_DEBUG to get the debug output
  */
 #ifdef _IA16
-#undef DEBUG_ONLY_MEMBERS
+#undef ACPI_DEBUG_ONLY_MEMBERS
 #undef _VERBOSE_STRUCTURES
-#define DEBUG_ONLY_MEMBERS(a)
+#define ACPI_DEBUG_ONLY_MEMBERS(a)
 #endif
 
 
@@ -545,11 +525,11 @@
  * 1) Set name to blanks
  * 2) Copy the object name
  */
-#define ADD_OBJECT_NAME(a,b)            MEMSET (a->common.name, ' ', sizeof (a->common.name));\
-										STRNCPY (a->common.name, acpi_gbl_ns_type_names[b], sizeof (a->common.name))
+#define ACPI_ADD_OBJECT_NAME(a,b)       ACPI_MEMSET (a->common.name, ' ', sizeof (a->common.name));\
+										ACPI_STRNCPY (a->common.name, acpi_gbl_ns_type_names[b], sizeof (a->common.name))
 #else
 
-#define ADD_OBJECT_NAME(a,b)
+#define ACPI_ADD_OBJECT_NAME(a,b)
 #endif
 
 
@@ -561,8 +541,8 @@
 
 /* Memory allocation */
 
-#define ACPI_MEM_ALLOCATE(a)            acpi_os_allocate(a)
-#define ACPI_MEM_CALLOCATE(a)           acpi_os_callocate(a)
+#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate(a,_COMPONENT,_THIS_MODULE,__LINE__)
+#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate(a, _COMPONENT,_THIS_MODULE,__LINE__)
 #define ACPI_MEM_FREE(a)                acpi_os_free(a)
 #define ACPI_MEM_TRACKING(a)
 
@@ -571,9 +551,9 @@
 
 /* Memory allocation */
 
-#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate(a,_COMPONENT,_THIS_MODULE,__LINE__)
-#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate(a, _COMPONENT,_THIS_MODULE,__LINE__)
-#define ACPI_MEM_FREE(a)                acpi_ut_free(a,_COMPONENT,_THIS_MODULE,__LINE__)
+#define ACPI_MEM_ALLOCATE(a)            acpi_ut_allocate_and_track(a,_COMPONENT,_THIS_MODULE,__LINE__)
+#define ACPI_MEM_CALLOCATE(a)           acpi_ut_callocate_and_track(a, _COMPONENT,_THIS_MODULE,__LINE__)
+#define ACPI_MEM_FREE(a)                acpi_ut_free_and_track(a,_COMPONENT,_THIS_MODULE,__LINE__)
 #define ACPI_MEM_TRACKING(a)            a
 
 #endif /* ACPI_DBG_TRACK_ALLOCATIONS */
diff -Nru a/drivers/acpi/include/acnamesp.h b/drivers/acpi/include/acnamesp.h
--- a/drivers/acpi/include/acnamesp.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acnamesp.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acnamesp.h - Namespace subcomponent prototypes and defines
- *       $Revision: 110 $
+ *       $Revision: 123 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -29,37 +29,37 @@
 
 /* To search the entire name space, pass this as Search_base */
 
-#define NS_ALL                  ((acpi_handle)0)
+#define ACPI_NS_ALL                 ((acpi_handle)0)
 
 /*
  * Elements of Acpi_ns_properties are bit significant
  * and should be one-to-one with values of acpi_object_type
  */
-#define NSP_NORMAL              0
-#define NSP_NEWSCOPE            1   /* a definition of this type opens a name scope */
-#define NSP_LOCAL               2   /* suppress search of enclosing scopes */
+#define ACPI_NS_NORMAL              0
+#define ACPI_NS_NEWSCOPE            1   /* a definition of this type opens a name scope */
+#define ACPI_NS_LOCAL               2   /* suppress search of enclosing scopes */
 
 
 /* Definitions of the predefined namespace names  */
 
-#define ACPI_UNKNOWN_NAME       (u32) 0x3F3F3F3F     /* Unknown name is  "????" */
-#define ACPI_ROOT_NAME          (u32) 0x2F202020     /* Root name is     "/   " */
-#define ACPI_SYS_BUS_NAME       (u32) 0x5F53425F     /* Sys bus name is  "_SB_" */
+#define ACPI_UNKNOWN_NAME           (u32) 0x3F3F3F3F     /* Unknown name is  "????" */
+#define ACPI_ROOT_NAME              (u32) 0x2F202020     /* Root name is     "/   " */
+#define ACPI_SYS_BUS_NAME           (u32) 0x5F53425F     /* Sys bus name is  "_SB_" */
 
-#define NS_ROOT_PATH            "/"
-#define NS_SYSTEM_BUS           "_SB_"
+#define ACPI_NS_ROOT_PATH           "\\"
+#define ACPI_NS_SYSTEM_BUS          "_SB_"
 
 
 /* Flags for Acpi_ns_lookup, Acpi_ns_search_and_enter */
 
-#define NS_NO_UPSEARCH          0
-#define NS_SEARCH_PARENT        0x01
-#define NS_DONT_OPEN_SCOPE      0x02
-#define NS_NO_PEER_SEARCH       0x04
-#define NS_ERROR_IF_FOUND       0x08
+#define ACPI_NS_NO_UPSEARCH         0
+#define ACPI_NS_SEARCH_PARENT       0x01
+#define ACPI_NS_DONT_OPEN_SCOPE     0x02
+#define ACPI_NS_NO_PEER_SEARCH      0x04
+#define ACPI_NS_ERROR_IF_FOUND      0x08
 
-#define NS_WALK_UNLOCK          TRUE
-#define NS_WALK_NO_UNLOCK       FALSE
+#define ACPI_NS_WALK_UNLOCK         TRUE
+#define ACPI_NS_WALK_NO_UNLOCK      FALSE
 
 
 acpi_status
@@ -94,7 +94,7 @@
 
 acpi_status
 acpi_ns_walk_namespace (
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_handle             start_object,
 	u32                     max_depth,
 	u8                      unlock_before_callback,
@@ -104,7 +104,7 @@
 
 acpi_namespace_node *
 acpi_ns_get_next_node (
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_namespace_node     *parent,
 	acpi_namespace_node     *child);
 
@@ -148,8 +148,8 @@
 acpi_ns_lookup (
 	acpi_generic_state      *scope_info,
 	NATIVE_CHAR             *name,
-	acpi_object_type8       type,
-	operating_mode          interpreter_mode,
+	acpi_object_type        type,
+	acpi_interpreter_mode   interpreter_mode,
 	u32                     flags,
 	acpi_walk_state         *walk_state,
 	acpi_namespace_node     **ret_node);
@@ -216,12 +216,17 @@
 	u32                     component);
 
 void
+acpi_ns_print_pathname (
+	u32                     num_segments,
+	char                    *pathname);
+
+void
 acpi_ns_dump_root_devices (
 	void);
 
 void
 acpi_ns_dump_objects (
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	u8                      display_type,
 	u32                     max_depth,
 	u32                     ownder_id,
@@ -277,15 +282,15 @@
 
 
 /*
- * Scope manipulation - nsscope
+ * Name and Scope manipulation - nsnames
  */
 
 u32
 acpi_ns_opens_scope (
-	acpi_object_type8       type);
+	acpi_object_type        type);
 
 NATIVE_CHAR *
-acpi_ns_get_table_pathname (
+acpi_ns_get_external_pathname (
 	acpi_namespace_node     *node);
 
 NATIVE_CHAR *
@@ -294,9 +299,8 @@
 
 acpi_status
 acpi_ns_handle_to_pathname (
-	acpi_handle             obj_handle,
-	u32                     *buf_size,
-	NATIVE_CHAR             *user_buffer);
+	acpi_handle             target_handle,
+	acpi_buffer             *buffer);
 
 u8
 acpi_ns_pattern_match (
@@ -304,25 +308,51 @@
 	NATIVE_CHAR             *search_for);
 
 acpi_status
-acpi_ns_get_node (
-	NATIVE_CHAR             *pathname,
+acpi_ns_get_node_by_path (
+	NATIVE_CHAR             *external_pathname,
 	acpi_namespace_node     *in_prefix_node,
+	u32                     flags,
 	acpi_namespace_node     **out_node);
 
-u32
+ACPI_SIZE
 acpi_ns_get_pathname_length (
 	acpi_namespace_node     *node);
 
 
 /*
- * Object management for NTEs - nsobject
+ * Object management for namespace nodes - nsobject
  */
 
 acpi_status
 acpi_ns_attach_object (
 	acpi_namespace_node     *node,
 	acpi_operand_object     *object,
-	acpi_object_type8       type);
+	acpi_object_type        type);
+
+acpi_operand_object *
+acpi_ns_get_attached_object (
+	acpi_namespace_node     *node);
+
+acpi_operand_object *
+acpi_ns_get_secondary_object (
+	acpi_operand_object     *obj_desc);
+
+acpi_status
+acpi_ns_attach_data (
+	acpi_namespace_node     *node,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    *data);
+
+acpi_status
+acpi_ns_detach_data (
+	acpi_namespace_node     *node,
+	ACPI_OBJECT_HANDLER     handler);
+
+acpi_status
+acpi_ns_get_attached_data (
+	acpi_namespace_node     *node,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    **data);
 
 
 /*
@@ -334,8 +364,8 @@
 	u32                     entry_name,
 	acpi_walk_state         *walk_state,
 	acpi_namespace_node     *node,
-	operating_mode          interpreter_mode,
-	acpi_object_type8       type,
+	acpi_interpreter_mode   interpreter_mode,
+	acpi_object_type        type,
 	u32                     flags,
 	acpi_namespace_node     **ret_node);
 
@@ -343,7 +373,7 @@
 acpi_ns_search_node (
 	u32                     entry_name,
 	acpi_namespace_node     *node,
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_namespace_node     **ret_node);
 
 void
@@ -351,7 +381,7 @@
 	acpi_walk_state         *walk_state,
 	acpi_namespace_node     *parent_node,   /* Parent */
 	acpi_namespace_node     *node,      /* New Child*/
-	acpi_object_type8       type);
+	acpi_object_type        type);
 
 
 /*
@@ -366,17 +396,13 @@
 acpi_ns_valid_path_separator (
 	NATIVE_CHAR             sep);
 
-acpi_object_type8
+acpi_object_type
 acpi_ns_get_type (
 	acpi_namespace_node     *node);
 
-void *
-acpi_ns_get_attached_object (
-	acpi_namespace_node     *node);
-
 u32
 acpi_ns_local (
-	acpi_object_type8       type);
+	acpi_object_type        type);
 
 acpi_status
 acpi_ns_build_internal_name (
@@ -411,7 +437,7 @@
 	void);
 
 acpi_namespace_node *
-acpi_ns_get_parent_object (
+acpi_ns_get_parent_node (
 	acpi_namespace_node     *node);
 
 
diff -Nru a/drivers/acpi/include/acobject.h b/drivers/acpi/include/acobject.h
--- a/drivers/acpi/include/acobject.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acobject.h	Fri Mar 15 17:51:01 2002
@@ -2,12 +2,12 @@
 /******************************************************************************
  *
  * Name: acobject.h - Definition of acpi_operand_object  (Internal object only)
- *       $Revision: 93 $
+ *       $Revision: 106 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -58,44 +58,40 @@
  */
 
 
-#define ACPI_OBJECT_COMMON_HEADER           /* SIZE/ALIGNMENT: 32-bits plus trailing 8-bit flag */\
-	u8                          data_type;          /* To differentiate various internal objs */\
+#define ACPI_OBJECT_COMMON_HEADER           /* SIZE/ALIGNMENT: 32 bits, one ptr plus trailing 8-bit flag */\
+	u8                          descriptor;         /* To differentiate various internal objs */\
 	u8                          type;               /* acpi_object_type */\
 	u16                         reference_count;    /* For object deletion management */\
+	union acpi_operand_obj      *next_object;       /* Objects linked to parent NS node */\
 	u8                          flags; \
 
 /* Defines for flag byte above */
 
-#define AOPOBJ_STATIC_ALLOCATION    0x1
-#define AOPOBJ_STATIC_POINTER       0x2
-#define AOPOBJ_DATA_VALID           0x4
-#define AOPOBJ_ZERO_CONST           0x4
-#define AOPOBJ_INITIALIZED          0x8
+#define AOPOBJ_RESERVED             0x01
+#define AOPOBJ_STATIC_POINTER       0x02
+#define AOPOBJ_DATA_VALID           0x04
+#define AOPOBJ_OBJECT_INITIALIZED   0x08
+#define AOPOBJ_SETUP_COMPLETE       0x10
+#define AOPOBJ_SINGLE_DATUM         0x20
 
 
 /*
  * Common bitfield for the field objects
- * "Field Datum"    -- a datum from the actual field object
- * "Buffer Datum"   -- a datum from a user buffer, read from or to be written to the field
+ * "Field Datum"  -- a datum from the actual field object
+ * "Buffer Datum" -- a datum from a user buffer, read from or to be written to the field
  */
 #define ACPI_COMMON_FIELD_INFO              /* SIZE/ALIGNMENT: 24 bits + three 32-bit values */\
-	u8                          access_flags;\
-	u16                         bit_length;         /* Length of field in bits */\
-	u32                         base_byte_offset;   /* Byte offset within containing object */\
-	u8                          access_bit_width;   /* Read/Write size in bits (from ASL Access_type)*/\
+	u8                          field_flags;        /* Access, update, and lock bits */\
+	u8                          attribute;          /* From Access_as keyword */\
 	u8                          access_byte_width;  /* Read/Write size in bytes */\
-	u8                          update_rule;        /* How neighboring field bits are handled */\
-	u8                          lock_rule;          /* Global Lock: 1 = "Must Lock" */\
+	u32                         bit_length;         /* Length of field in bits */\
+	u32                         base_byte_offset;   /* Byte offset within containing object */\
 	u8                          start_field_bit_offset;/* Bit offset within first field datum (0-63) */\
 	u8                          datum_valid_bits;   /* Valid bit in first "Field datum" */\
 	u8                          end_field_valid_bits; /* Valid bits in the last "field datum" */\
 	u8                          end_buffer_valid_bits; /* Valid bits in the last "buffer datum" */\
-	u32                         value;              /* Value to store into the Bank or Index register */
-
-
-/* Access flag bits */
-
-#define AFIELD_SINGLE_DATUM         0x1
+	u32                         value;              /* Value to store into the Bank or Index register */\
+	acpi_namespace_node         *node;              /* Link back to parent node */
 
 
 /*
@@ -150,6 +146,7 @@
 	ACPI_OBJECT_COMMON_HEADER
 	ACPI_COMMON_BUFFER_INFO
 	u8                          *pointer;           /* Buffer value in AML stream or in allocated space */
+	acpi_namespace_node         *node;              /* Link back to parent node */
 
 } ACPI_OBJECT_BUFFER;
 
@@ -210,8 +207,8 @@
 	u16                         sync_level;
 	u16                         acquisition_depth;
 
+	struct acpi_thread_state    *owner_thread;
 	void                        *semaphore;
-	void                        *owner;
 	union acpi_operand_obj      *prev;              /* Link for list of acquired mutexes */
 	union acpi_operand_obj      *next;              /* Link for list of acquired mutexes */
 
@@ -225,7 +222,6 @@
 	u8                          space_id;
 	u32                         length;
 	ACPI_PHYSICAL_ADDRESS       address;
-	union acpi_operand_obj      *extra;             /* Pointer to executable AML (in region definition) */
 
 	union acpi_operand_obj      *addr_handler;      /* Handler for system notifies */
 	acpi_namespace_node         *node;              /* containing object */
@@ -301,7 +297,7 @@
 	ACPI_COMMON_FIELD_INFO
 
 	union acpi_operand_obj      *region_obj;        /* Containing Op_region object */
-	union acpi_operand_obj      *bank_register_obj; /* Bank_select Register object */
+	union acpi_operand_obj      *bank_obj;          /* Bank_select Register object */
 
 } ACPI_OBJECT_BANK_FIELD;
 
@@ -329,8 +325,6 @@
 	ACPI_OBJECT_COMMON_HEADER
 	ACPI_COMMON_FIELD_INFO
 
-	union acpi_operand_obj      *extra;             /* Pointer to executable AML (in field definition) */
-	acpi_namespace_node         *node;              /* Parent (containing) object node */
 	union acpi_operand_obj      *buffer_obj;        /* Containing Buffer object */
 
 } ACPI_OBJECT_BUFFER_FIELD;
@@ -353,7 +347,7 @@
 
 /* Flags for address handler */
 
-#define ADDR_HANDLER_DEFAULT_INSTALLED  0x1
+#define ACPI_ADDR_HANDLER_DEFAULT_INSTALLED  0x1
 
 
 typedef struct /* ADDRESS HANDLER */
@@ -414,6 +408,15 @@
 } ACPI_OBJECT_EXTRA;
 
 
+typedef struct /* DATA */
+{
+	ACPI_OBJECT_COMMON_HEADER
+	ACPI_OBJECT_HANDLER         handler;
+	void                        *pointer;
+
+} ACPI_OBJECT_DATA;
+
+
 /******************************************************************************
  *
  * acpi_operand_object  Descriptor - a giant union of all of the above
@@ -445,6 +448,7 @@
 	ACPI_OBJECT_NOTIFY_HANDLER  notify_handler;
 	ACPI_OBJECT_ADDR_HANDLER    addr_handler;
 	ACPI_OBJECT_EXTRA           extra;
+	ACPI_OBJECT_DATA            data;
 
 } acpi_operand_object;
 
diff -Nru a/drivers/acpi/include/acoutput.h b/drivers/acpi/include/acoutput.h
--- a/drivers/acpi/include/acoutput.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/include/acoutput.h	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acoutput.h -- debug output
- *       $Revision: 84 $
+ *       $Revision: 86 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -46,25 +46,18 @@
 #define ACPI_DEBUGGER               0x00000200
 #define ACPI_OS_SERVICES            0x00000400
 
-#define ACPI_BUS                    0x00010000
-#define ACPI_SYSTEM                 0x00020000
-#define ACPI_POWER                  0x00040000
-#define ACPI_EC                     0x00080000
-#define ACPI_AC_ADAPTER             0x00100000
-#define ACPI_BATTERY                0x00200000
-#define ACPI_BUTTON                 0x00400000
-#define ACPI_PROCESSOR              0x00800000
-#define ACPI_THERMAL                0x01000000
-#define ACPI_FAN                    0x02000000
-
-#define ACPI_ALL_COMPONENTS         0x0FFFFFFF
+#define ACPI_ALL_COMPONENTS         0x00000FFF
 
 #define ACPI_COMPONENT_DEFAULT      (ACPI_ALL_COMPONENTS)
 
+/* Component IDs for ACPI tools and utilities */
+
+#define ACPI_COMPILER               0x00001000
+#define ACPI_TOOLS                  0x00002000
 
-#define ACPI_COMPILER               0x10000000
-#define ACPI_TOOLS                  0x20000000
+/* Component IDs reserved for ACPI drivers */
 
+#define ACPI_ALL_DRIVERS            0xFFFF0000
 
 /*
  * Raw debug output levels, do not use these in the DEBUG_PRINT macros
diff -Nru a/drivers/acpi/include/acparser.h b/drivers/acpi/include/acparser.h
--- a/drivers/acpi/include/acparser.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acparser.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: acparser.h - AML Parser subcomponent prototypes and defines
- *       $Revision: 54 $
+ *       $Revision: 58 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,15 +28,11 @@
 #define __ACPARSER_H__
 
 
-#define OP_HAS_RETURN_VALUE         1
+#define OP_HAS_RETURN_VALUE             1
 
 /* variable # arguments */
 
-#define ACPI_VAR_ARGS               ACPI_UINT32_MAX
-
-/* maximum virtual address */
-
-#define ACPI_MAX_AML                ((u8 *)(~0UL))
+#define ACPI_VAR_ARGS                   ACPI_UINT32_MAX
 
 
 #define ACPI_PARSE_DELETE_TREE          0x0001
@@ -48,7 +44,8 @@
 #define ACPI_PARSE_EXECUTE              0x0030
 #define ACPI_PARSE_MODE_MASK            0x0030
 
-/* psapi - Parser external interfaces */
+
+/* Parser external interfaces */
 
 acpi_status
 acpi_psx_load_table (
@@ -61,6 +58,7 @@
 	acpi_operand_object     **params,
 	acpi_operand_object     **return_obj_desc);
 
+
 /******************************************************************************
  *
  * Parser interfaces
@@ -85,8 +83,8 @@
 void
 acpi_ps_get_next_simple_arg (
 	acpi_parse_state        *parser_state,
-	u32                     arg_type,       /* type of argument */
-	acpi_parse_object       *arg);           /* (OUT) argument data */
+	u32                     arg_type,
+	acpi_parse_object       *arg);
 
 void
 acpi_ps_get_next_namepath (
@@ -106,6 +104,19 @@
 	u32                     *arg_count);
 
 
+/* psfind */
+
+acpi_parse_object *
+acpi_ps_find_name (
+	acpi_parse_object       *scope,
+	u32                     name,
+	u32                     opcode);
+
+acpi_parse_object*
+acpi_ps_get_parent (
+	acpi_parse_object       *op);
+
+
 /* psopcode - AML Opcode information */
 
 const acpi_opcode_info *
@@ -119,6 +130,21 @@
 
 /* psparse - top level parsing routines */
 
+u32
+acpi_ps_get_opcode_size (
+	u32                     opcode);
+
+u8
+acpi_ps_complete_this_op (
+	acpi_walk_state         *walk_state,
+	acpi_parse_object       *op);
+
+acpi_status
+acpi_ps_next_parse_state (
+	acpi_walk_state         *walk_state,
+	acpi_parse_object       *op,
+	acpi_status             callback_status);
+
 acpi_status
 acpi_ps_find_object (
 	acpi_walk_state         *walk_state,
@@ -232,6 +258,10 @@
 	acpi_walk_state         *walk_state,
 	acpi_parse_object       *op,
 	acpi_parse_upwards      ascending_callback);
+
+acpi_status
+acpi_ps_delete_completed_op (
+	acpi_walk_state         *walk_state);
 
 
 /* psutils - parser utilities */
diff -Nru a/drivers/acpi/include/acpi.h b/drivers/acpi/include/acpi.h
--- a/drivers/acpi/include/acpi.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/acpi.h	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acpi.h - Master include file, Publics and external data.
- *       $Revision: 54 $
+ *       $Revision: 55 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
diff -Nru a/drivers/acpi/include/acpiosxf.h b/drivers/acpi/include/acpiosxf.h
--- a/drivers/acpi/include/acpiosxf.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acpiosxf.h	Fri Mar 15 17:51:01 2002
@@ -9,7 +9,7 @@
 
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -62,12 +62,12 @@
  * Types specific to the OS service interfaces
  */
 
-typedef
-u32 (*OSD_HANDLER) (
+typedef u32
+(ACPI_SYSTEM_XFACE *OSD_HANDLER) (
 	void                    *context);
 
-typedef
-void (*OSD_EXECUTION_CALLBACK) (
+typedef void
+(ACPI_SYSTEM_XFACE *OSD_EXECUTION_CALLBACK) (
 	void                    *context);
 
 
@@ -121,11 +121,7 @@
 
 void *
 acpi_os_allocate (
-	u32                     size);
-
-void *
-acpi_os_callocate (
-	u32                     size);
+	ACPI_SIZE               size);
 
 void
 acpi_os_free (
@@ -134,13 +130,13 @@
 acpi_status
 acpi_os_map_memory (
 	ACPI_PHYSICAL_ADDRESS   physical_address,
-	u32                     length,
+	ACPI_SIZE               size,
 	void                    **logical_address);
 
 void
 acpi_os_unmap_memory (
 	void                    *logical_address,
-	u32                     length);
+	ACPI_SIZE               size);
 
 acpi_status
 acpi_os_get_physical_address (
@@ -202,7 +198,7 @@
 acpi_status
 acpi_os_write_port (
 	ACPI_IO_ADDRESS         address,
-	NATIVE_UINT             value,
+	acpi_integer            value,
 	u32                     width);
 
 
@@ -220,7 +216,7 @@
 acpi_status
 acpi_os_write_memory (
 	ACPI_PHYSICAL_ADDRESS   address,
-	NATIVE_UINT             value,
+	acpi_integer            value,
 	u32                     width);
 
 
@@ -240,7 +236,7 @@
 acpi_os_write_pci_configuration (
 	acpi_pci_id             *pci_id,
 	u32                     register,
-	NATIVE_UINT             value,
+	acpi_integer            value,
 	u32                     width);
 
 
@@ -272,12 +268,12 @@
  * Debug print routines
  */
 
-s32
+void ACPI_INTERNAL_VAR_XFACE
 acpi_os_printf (
 	const NATIVE_CHAR       *format,
 	...);
 
-s32
+void
 acpi_os_vprintf (
 	const NATIVE_CHAR       *format,
 	va_list                 args);
diff -Nru a/drivers/acpi/include/acpixf.h b/drivers/acpi/include/acpixf.h
--- a/drivers/acpi/include/acpixf.h	Fri Mar 15 17:51:00 2002
+++ b/drivers/acpi/include/acpixf.h	Fri Mar 15 17:51:00 2002
@@ -6,7 +6,7 @@
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -67,6 +67,10 @@
 acpi_format_exception (
 	acpi_status             exception);
 
+acpi_status
+acpi_purge_cached_objects (
+	void);
+
 
 /*
  * ACPI Memory manager
@@ -158,6 +162,23 @@
 	acpi_string             pathname,
 	acpi_handle             *ret_handle);
 
+acpi_status
+acpi_attach_data (
+	acpi_handle             obj_handle,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    *data);
+
+acpi_status
+acpi_detach_data (
+	acpi_handle             obj_handle,
+	ACPI_OBJECT_HANDLER     handler);
+
+acpi_status
+acpi_get_data (
+	acpi_handle             obj_handle,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    **data);
+
 
 /*
  * Object manipulation and enumeration
@@ -244,11 +265,12 @@
 
 acpi_status
 acpi_acquire_global_lock (
-	void);
+	u32                     timeout,
+	u32                     *handle);
 
 acpi_status
 acpi_release_global_lock (
-	void);
+	u32                     handle);
 
 acpi_status
 acpi_remove_gpe_handler (
@@ -314,6 +336,11 @@
 acpi_status
 acpi_get_firmware_waking_vector (
 	ACPI_PHYSICAL_ADDRESS   *physical_address);
+
+
+acpi_status
+acpi_enter_sleep_state_prep (
+	u8 sleep_state);
 
 acpi_status
 acpi_enter_sleep_state (
diff -Nru a/drivers/acpi/include/acresrc.h b/drivers/acpi/include/acresrc.h
--- a/drivers/acpi/include/acresrc.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acresrc.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acresrc.h - Resource Manager function prototypes
- *       $Revision: 25 $
+ *       $Revision: 30 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -55,24 +55,21 @@
 acpi_status
 acpi_rs_create_resource_list (
 	acpi_operand_object     *byte_stream_buffer,
-	u8                      *output_buffer,
-	u32                     *output_buffer_length);
+	acpi_buffer             *output_buffer);
 
 acpi_status
 acpi_rs_create_byte_stream (
 	acpi_resource           *linked_list_buffer,
-	u8                      *output_buffer,
-	u32                     *output_buffer_length);
+	acpi_buffer             *output_buffer);
 
 acpi_status
 acpi_rs_create_pci_routing_table (
-	acpi_operand_object     *method_return_object,
-	u8                      *output_buffer,
-	u32                     *output_buffer_length);
+	acpi_operand_object     *package_object,
+	acpi_buffer             *output_buffer);
 
 
 /*
- *Function prototypes called from Acpi_rs_create*APIs
+ *Function prototypes called from Acpi_rs_create*
  */
 
 void
@@ -93,225 +90,224 @@
 acpi_rs_calculate_list_length (
 	u8                      *byte_stream_buffer,
 	u32                     byte_stream_buffer_length,
-	u32                     *size_needed);
+	ACPI_SIZE               *size_needed);
 
 acpi_status
 acpi_rs_calculate_byte_stream_length (
 	acpi_resource           *linked_list_buffer,
-	u32                     *size_needed);
+	ACPI_SIZE               *size_needed);
 
 acpi_status
 acpi_rs_calculate_pci_routing_table_length (
 	acpi_operand_object     *package_object,
-	u32                     *buffer_size_needed);
+	ACPI_SIZE               *buffer_size_needed);
 
 acpi_status
 acpi_rs_byte_stream_to_list (
 	u8                      *byte_stream_buffer,
 	u32                     byte_stream_buffer_length,
-	u8                      **output_buffer);
+	u8                      *output_buffer);
 
 acpi_status
 acpi_rs_list_to_byte_stream (
 	acpi_resource           *linked_list,
 	u32                     byte_stream_size_needed,
-	u8                      **output_buffer);
+	u8                      *output_buffer);
 
 acpi_status
 acpi_rs_io_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_fixed_io_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_io_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_fixed_io_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_irq_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_irq_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_dma_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_dma_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_address16_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_address16_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_address32_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_address32_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_address64_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_address64_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
-acpi_rs_start_dependent_functions_resource (
+acpi_rs_start_depend_fns_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
-acpi_rs_end_dependent_functions_resource (
+acpi_rs_end_depend_fns_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
-acpi_rs_start_dependent_functions_stream (
+acpi_rs_start_depend_fns_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
-acpi_rs_end_dependent_functions_stream (
+acpi_rs_end_depend_fns_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_memory24_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_memory24_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_memory32_range_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size
-);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_fixed_memory32_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_memory32_range_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_fixed_memory32_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_extended_irq_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_extended_irq_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_end_tag_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_end_tag_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 acpi_status
 acpi_rs_vendor_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size);
+	ACPI_SIZE               *structure_size);
 
 acpi_status
 acpi_rs_vendor_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed);
+	ACPI_SIZE               *bytes_consumed);
 
 u8
 acpi_rs_get_resource_type (
diff -Nru a/drivers/acpi/include/acstruct.h b/drivers/acpi/include/acstruct.h
--- a/drivers/acpi/include/acstruct.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acstruct.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acstruct.h - Internal structs
- *       $Revision: 10 $
+ *       $Revision: 16 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -39,12 +39,12 @@
  * the tree (for whatever reason), and for control method execution.
  */
 
-#define NEXT_OP_DOWNWARD    1
-#define NEXT_OP_UPWARD      2
+#define ACPI_NEXT_OP_DOWNWARD    1
+#define ACPI_NEXT_OP_UPWARD      2
 
-#define WALK_NON_METHOD     0
-#define WALK_METHOD         1
-#define WALK_METHOD_RESTART 2
+#define ACPI_WALK_NON_METHOD     0
+#define ACPI_WALK_METHOD         1
+#define ACPI_WALK_METHOD_RESTART 2
 
 typedef struct acpi_walk_state
 {
@@ -56,12 +56,12 @@
 	u8                      num_operands;                       /* Stack pointer for Operands[] array */
 	u8                      return_used;
 	u8                      walk_type;
-	u16                     current_sync_level;                 /* Mutex Sync (nested acquire) level */
 	u16                     opcode;                             /* Current AML opcode */
 	u32                     arg_count;                          /* push for fixed or var args */
 	u32                     aml_offset;
 	u32                     arg_types;
 	u32                     method_breakpoint;                  /* For single stepping */
+	u32                     user_breakpoint;                    /* User AML breakpoint */
 	u32                     parse_flags;
 	u32                     prev_arg_types;
 
@@ -86,33 +86,17 @@
 	union acpi_operand_obj  *return_desc;                       /* Return object, if any */
 	acpi_generic_state      *scope_info;                        /* Stack of nested scopes */
 
-/* TBD: Obsolete with removal of WALK procedure ? */
 	acpi_parse_object       *prev_op;                           /* Last op that was processed */
 	acpi_parse_object       *next_op;                           /* next op to be processed */
-
-
 	acpi_parse_downwards    descending_callback;
 	acpi_parse_upwards      ascending_callback;
-	struct acpi_walk_list   *walk_list;
+	ACPI_THREAD_STATE       *thread;
 	struct acpi_walk_state  *next;                              /* Next Walk_state in list */
 
 
 } acpi_walk_state;
 
 
-/*
- * Walk list - head of a tree of walk states.  Multiple walk states are created when there
- * are nested control methods executing.
- */
-typedef struct acpi_walk_list
-{
-
-	acpi_walk_state         *walk_state;
-	ACPI_OBJECT_MUTEX       acquired_mutex_list;               /* List of all currently acquired mutexes */
-
-} acpi_walk_list;
-
-
 /* Info used by Acpi_ps_init_objects */
 
 typedef struct acpi_init_walk_info
@@ -128,7 +112,7 @@
 } acpi_init_walk_info;
 
 
-/* Info used by TBD */
+/* Info used by Acpi_ns_initialize_devices */
 
 typedef struct acpi_device_walk_info
 {
diff -Nru a/drivers/acpi/include/actables.h b/drivers/acpi/include/actables.h
--- a/drivers/acpi/include/actables.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/include/actables.h	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: actables.h - ACPI table management
- *       $Revision: 32 $
+ *       $Revision: 35 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -119,6 +119,11 @@
 	acpi_table_desc         *table_info);
 
 acpi_status
+acpi_tb_match_signature (
+	NATIVE_CHAR             *signature,
+	acpi_table_desc         *table_info);
+
+acpi_status
 acpi_tb_recognize_table (
 	acpi_table_header       *table_ptr,
 	acpi_table_desc         *table_info);
@@ -176,6 +181,13 @@
 /*
  * tbutils - common table utilities
  */
+
+acpi_status
+acpi_tb_find_table (
+	NATIVE_CHAR             *signature,
+	NATIVE_CHAR             *oem_id,
+	NATIVE_CHAR             *oem_table_id,
+	acpi_table_header       **table_ptr);
 
 acpi_status
 acpi_tb_map_acpi_table (
diff -Nru a/drivers/acpi/include/actbl.h b/drivers/acpi/include/actbl.h
--- a/drivers/acpi/include/actbl.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/actbl.h	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: actbl.h - Table data structures defined in ACPI specification
- *       $Revision: 46 $
+ *       $Revision: 52 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,6 @@
 /*
  *  Values for description table header signatures
  */
-
 #define RSDP_NAME               "RSDP"
 #define RSDP_SIG                "RSD PTR "  /* RSDT Pointer signature */
 #define APIC_SIG                "APIC"      /* Multiple APIC Description Table */
@@ -42,7 +41,7 @@
 #define XSDT_SIG                "XSDT"      /* Extended  System Description Table */
 #define SSDT_SIG                "SSDT"      /* Secondary System Description Table */
 #define SBST_SIG                "SBST"      /* Smart Battery Specification Table */
-#define SPIC_SIG                "SPIC"      /* iosapic table */
+#define SPIC_SIG                "SPIC"      /* IOSAPIC table */
 #define BOOT_SIG                "BOOT"      /* Boot table */
 
 
@@ -75,29 +74,27 @@
  * Architecture-independent tables
  * The architecture dependent tables are in separate files
  */
-
 typedef struct  /* Root System Descriptor Pointer */
 {
-	NATIVE_CHAR             signature [8];          /* contains "RSD PTR " */
-	u8                      checksum;               /* to make sum of struct == 0 */
+	NATIVE_CHAR             signature [8];          /* ACPI signature, contains "RSD PTR " */
+	u8                      checksum;               /* To make sum of struct == 0 */
 	NATIVE_CHAR             oem_id [6];             /* OEM identification */
 	u8                      revision;               /* Must be 0 for 1.0, 2 for 2.0 */
 	u32                     rsdt_physical_address;  /* 32-bit physical address of RSDT */
 	u32                     length;                 /* XSDT Length in bytes including hdr */
 	u64                     xsdt_physical_address;  /* 64-bit physical address of XSDT */
 	u8                      extended_checksum;      /* Checksum of entire table */
-	NATIVE_CHAR             reserved [3];           /* reserved field must be 0 */
+	NATIVE_CHAR             reserved [3];           /* Reserved field must be 0 */
 
 } RSDP_DESCRIPTOR;
 
 
 typedef struct  /* ACPI common table header */
 {
-	NATIVE_CHAR             signature [4];          /* identifies type of table */
-	u32                     length;                 /* length of table, in bytes,
-			  * including header */
-	u8                      revision;               /* specification minor version # */
-	u8                      checksum;               /* to make sum of entire table == 0 */
+	NATIVE_CHAR             signature [4];          /* ACPI signature (4 ASCII characters) */
+	u32                     length;                 /* Length of table, in bytes, including header */
+	u8                      revision;               /* ACPI Specification minor version # */
+	u8                      checksum;               /* To make sum of entire table == 0 */
 	NATIVE_CHAR             oem_id [6];             /* OEM identification */
 	NATIVE_CHAR             oem_table_id [8];       /* OEM table identification */
 	u32                     oem_revision;           /* OEM revision number */
@@ -118,7 +115,7 @@
 
 typedef struct  /* APIC Table */
 {
-	acpi_table_header       header;                 /* table header */
+	acpi_table_header       header;                 /* ACPI table header */
 	u32                     local_apic_address;     /* Physical address for accessing local APICs */
 	u32                     PCATcompat      : 1;    /* a one indicates system also has dual 8259s */
 	u32                     reserved1       : 31;
@@ -138,7 +135,7 @@
 {
 	APIC_HEADER             header;
 	u8                      processor_apic_id;      /* ACPI processor id */
-	u8                      local_apic_id;          /* processor's local APIC id */
+	u8                      local_apic_id;          /* Processor's local APIC id */
 	u32                     processor_enabled: 1;   /* Processor is usable if set */
 	u32                     reserved1       : 31;
 
@@ -149,21 +146,21 @@
 {
 	APIC_HEADER             header;
 	u8                      io_apic_id;             /* I/O APIC ID */
-	u8                      reserved;               /* reserved - must be zero */
+	u8                      reserved;               /* Reserved - must be zero */
 	u32                     io_apic_address;        /* APIC's physical address */
-	u32                     vector;                 /* interrupt vector index where INTI
+	u32                     vector;                 /* Interrupt vector index where INTI
 			  * lines start */
 } IO_APIC;
 
 
 /*
-**  IA64 TODO:  Add SAPIC Tables
-*/
+ *  IA64 TBD:  Add SAPIC Tables
+ */
 
 /*
-**  IA64 TODO:  Modify Smart Battery Description to comply with ACPI IA64
-**              extensions.
-*/
+ *  IA64 TBD:   Modify Smart Battery Description to comply with ACPI IA64
+ *              extensions.
+ */
 typedef struct  /* Smart Battery Description Table */
 {
 	acpi_table_header       header;
@@ -182,7 +179,6 @@
  * and type of memory allocation (mapped or allocated) for each
  * table for 1) when we exit, and 2) if a new table is installed
  */
-
 #define ACPI_MEM_NOT_ALLOCATED  0
 #define ACPI_MEM_ALLOCATED      1
 #define ACPI_MEM_MAPPED         2
@@ -191,7 +187,7 @@
 
 #define ACPI_TABLE_SINGLE       0
 #define ACPI_TABLE_MULTIPLE     1
-
+#define ACPI_TABLE_EXECUTABLE   2
 
 /* Data about each known table type */
 
@@ -199,19 +195,17 @@
 {
 	NATIVE_CHAR             *name;
 	NATIVE_CHAR             *signature;
+	void                    **global_ptr;
 	u8                      sig_length;
 	u8                      flags;
-	u16                     status;
-	void                    **global_ptr;
 
 } ACPI_TABLE_SUPPORT;
 
+
 /*
  * Get the architecture-specific tables
  */
-
-#include "actbl1.h"   /* Acpi 1.0 table defintions */
-#include "actbl71.h"  /* Acpi 0.71 IA-64 Extension table defintions */
+#include "actbl1.h"   /* Acpi 1.0 table definitions */
 #include "actbl2.h"   /* Acpi 2.0 table definitions */
 
 #endif /* __ACTBL_H__ */
diff -Nru a/drivers/acpi/include/actbl1.h b/drivers/acpi/include/actbl1.h
--- a/drivers/acpi/include/actbl1.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/actbl1.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: actbl1.h - ACPI 1.0 tables
- *       $Revision: 17 $
+ *       $Revision: 21 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,91 +28,88 @@
 
 #pragma pack(1)
 
-/*************************************/
-/* ACPI Specification Rev 1.0 for    */
-/* the Root System Description Table */
-/*************************************/
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
 typedef struct
 {
-	acpi_table_header       header;                 /* Table header */
+	acpi_table_header       header;                 /* ACPI Table header */
 	u32                     table_offset_entry [1]; /* Array of pointers to other */
 			 /* ACPI tables */
 } RSDT_DESCRIPTOR_REV1;
 
 
-/***************************************/
-/* ACPI Specification Rev 1.0 for      */
-/* the Firmware ACPI Control Structure */
-/***************************************/
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
 typedef struct
 {
-	NATIVE_CHAR             signature[4];           /* signature "FACS" */
-	u32                     length;                 /* length of structure, in bytes */
-	u32                     hardware_signature;     /* hardware configuration signature */
+	NATIVE_CHAR             signature[4];           /* ACPI Signature */
+	u32                     length;                 /* Length of structure, in bytes */
+	u32                     hardware_signature;     /* Hardware configuration signature */
 	u32                     firmware_waking_vector; /* ACPI OS waking vector */
 	u32                     global_lock;            /* Global Lock */
 	u32                     S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
-	u32                     reserved1       : 31;   /* must be 0 */
-	u8                      resverved3 [40];        /* reserved - must be zero */
+	u32                     reserved1       : 31;   /* Must be 0 */
+	u8                      resverved3 [40];        /* Reserved - must be zero */
 
 } facs_descriptor_rev1;
 
 
-/************************************/
-/* ACPI Specification Rev 1.0 for   */
-/* the Fixed ACPI Description Table */
-/************************************/
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
 typedef struct
 {
-	acpi_table_header       header;                 /* table header */
+	acpi_table_header       header;                 /* ACPI Table header */
 	u32                     firmware_ctrl;          /* Physical address of FACS */
 	u32                     dsdt;                   /* Physical address of DSDT */
 	u8                      model;                  /* System Interrupt Model */
-	u8                      reserved1;              /* reserved */
+	u8                      reserved1;              /* Reserved */
 	u16                     sci_int;                /* System vector of SCI interrupt */
 	u32                     smi_cmd;                /* Port address of SMI command port */
-	u8                      acpi_enable;            /* value to write to smi_cmd to enable ACPI */
-	u8                      acpi_disable;           /* value to write to smi_cmd to disable ACPI */
+	u8                      acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
+	u8                      acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
 	u8                      S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
-	u8                      reserved2;              /* reserved - must be zero */
+	u8                      reserved2;              /* Reserved - must be zero */
 	u32                     pm1a_evt_blk;           /* Port address of Power Mgt 1a Acpi_event Reg Blk */
 	u32                     pm1b_evt_blk;           /* Port address of Power Mgt 1b Acpi_event Reg Blk */
 	u32                     pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
 	u32                     pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
 	u32                     pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
 	u32                     pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
-	u32                     gpe0blk;                /* Port addr of General Purpose Acpi_event 0 Reg Blk */
+	u32                     gpe0_blk;               /* Port addr of General Purpose Acpi_event 0 Reg Blk */
 	u32                     gpe1_blk;               /* Port addr of General Purpose Acpi_event 1 Reg Blk */
 	u8                      pm1_evt_len;            /* Byte Length of ports at pm1_x_evt_blk */
 	u8                      pm1_cnt_len;            /* Byte Length of ports at pm1_x_cnt_blk */
 	u8                      pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
 	u8                      pm_tm_len;              /* Byte Length of ports at pm_tm_blk */
-	u8                      gpe0blk_len;            /* Byte Length of ports at gpe0_blk */
+	u8                      gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
 	u8                      gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
-	u8                      gpe1_base;              /* offset in gpe model where gpe1 events start */
-	u8                      reserved3;              /* reserved */
-	u16                     plvl2_lat;              /* worst case HW latency to enter/exit C2 state */
-	u16                     plvl3_lat;              /* worst case HW latency to enter/exit C3 state */
+	u8                      gpe1_base;              /* Offset in gpe model where gpe1 events start */
+	u8                      reserved3;              /* Reserved */
+	u16                     plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
+	u16                     plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
 	u16                     flush_size;             /* Size of area read to flush caches */
 	u16                     flush_stride;           /* Stride used in flushing caches */
-	u8                      duty_offset;            /* bit location of duty cycle field in p_cnt reg */
-	u8                      duty_width;             /* bit width of duty cycle field in p_cnt reg */
-	u8                      day_alrm;               /* index to day-of-month alarm in RTC CMOS RAM */
-	u8                      mon_alrm;               /* index to month-of-year alarm in RTC CMOS RAM */
-	u8                      century;                /* index to century in RTC CMOS RAM */
-	u8                      reserved4;              /* reserved */
-	u8                      reserved4a;             /* reserved */
-	u8                      reserved4b;             /* reserved */
-	u32                     wb_invd         : 1;    /* wbinvd instruction works properly */
-	u32                     wb_invd_flush   : 1;    /* wbinvd flushes but does not invalidate */
-	u32                     proc_c1         : 1;    /* all processors support C1 state */
+	u8                      duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
+	u8                      duty_width;             /* Bit width of duty cycle field in p_cnt reg */
+	u8                      day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
+	u8                      mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
+	u8                      century;                /* Index to century in RTC CMOS RAM */
+	u8                      reserved4;              /* Reserved */
+	u8                      reserved4a;             /* Reserved */
+	u8                      reserved4b;             /* Reserved */
+	u32                     wb_invd         : 1;    /* The wbinvd instruction works properly */
+	u32                     wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
+	u32                     proc_c1         : 1;    /* All processors support C1 state */
 	u32                     plvl2_up        : 1;    /* C2 state works on MP system */
 	u32                     pwr_button      : 1;    /* Power button is handled as a generic feature */
 	u32                     sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
 	u32                     fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
 	u32                     rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
-	u32                     tmr_val_ext     : 1;    /* tmr_val is 32 bits */
-	u32                     reserved5       : 23;   /* reserved - must be zero */
+	u32                     tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
+	u32                     reserved5       : 23;   /* Reserved - must be zero */
 
 }  fadt_descriptor_rev1;
 
diff -Nru a/drivers/acpi/include/actbl2.h b/drivers/acpi/include/actbl2.h
--- a/drivers/acpi/include/actbl2.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/actbl2.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: actbl2.h - ACPI Specification Revision 2.0 Tables
- *       $Revision: 24 $
+ *       $Revision: 27 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -49,48 +49,48 @@
 #pragma pack(1)
 
 /*
- * ACPI Specification Rev 2.0 for the Root System Description Table
+ * ACPI 2.0 Root System Description Table (RSDT)
  */
 typedef struct
 {
-	acpi_table_header       header;                 /* Table header */
+	acpi_table_header       header;                 /* ACPI table header */
 	u32                     table_offset_entry [1]; /* Array of pointers to  */
-			 /* other tables' headers */
+			 /* ACPI table headers */
 } RSDT_DESCRIPTOR_REV2;
 
 
 /*
- * ACPI Specification Rev 2.0 for the Extended System Description Table (XSDT)
+ * ACPI 2.0 Extended System Description Table (XSDT)
  */
 typedef struct
 {
-	acpi_table_header       header;                 /* Table header */
+	acpi_table_header       header;                 /* ACPI table header */
 	u64                     table_offset_entry [1]; /* Array of pointers to  */
-			 /* other tables' headers */
+			 /* ACPI table headers */
 } XSDT_DESCRIPTOR_REV2;
 
 
 /*
- * ACPI Specification Rev 2.0 for the Firmware ACPI Control Structure
+ * ACPI 2.0 Firmware ACPI Control Structure (FACS)
  */
 typedef struct
 {
-	NATIVE_CHAR             signature[4];           /* signature "FACS" */
-	u32                     length;                 /* length of structure, in bytes */
-	u32                     hardware_signature;     /* hardware configuration signature */
+	NATIVE_CHAR             signature[4];           /* ACPI signature */
+	u32                     length;                 /* Length of structure, in bytes */
+	u32                     hardware_signature;     /* Hardware configuration signature */
 	u32                     firmware_waking_vector; /* 32bit physical address of the Firmware Waking Vector. */
 	u32                     global_lock;            /* Global Lock used to synchronize access to shared hardware resources */
-	u32                     S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
-	u32                     reserved1       : 31;   /* must be 0 */
+	u32                     S4bios_f        : 1;    /* S4Bios_f - Indicates if S4BIOS support is present */
+	u32                     reserved1       : 31;   /* Must be 0 */
 	u64                     Xfirmware_waking_vector; /* 64bit physical address of the Firmware Waking Vector. */
 	u8                      version;                /* Version of this table */
-	u8                      reserved3 [31];         /* reserved - must be zero */
+	u8                      reserved3 [31];         /* Reserved - must be zero */
 
 } facs_descriptor_rev2;
 
 
 /*
- * ACPI Specification Rev 2.0 for the Generic Address Structure (GAS)
+ * ACPI 2.0 Generic Address Structure (GAS)
  */
 typedef struct
 {
@@ -104,64 +104,64 @@
 
 
 /*
- * ACPI Specification Rev 2.0 for the Fixed ACPI Description Table
+ * ACPI 2.0 Fixed ACPI Description Table (FADT)
  */
 typedef struct
 {
-	acpi_table_header       header;             /* table header */
+	acpi_table_header       header;             /* ACPI table header */
 	u32                     V1_firmware_ctrl;   /* 32-bit physical address of FACS */
 	u32                     V1_dsdt;            /* 32-bit physical address of DSDT */
 	u8                      reserved1;          /* System Interrupt Model isn't used in ACPI 2.0*/
 	u8                      prefer_PM_profile;  /* Conveys preferred power management profile to OSPM. */
 	u16                     sci_int;            /* System vector of SCI interrupt */
 	u32                     smi_cmd;            /* Port address of SMI command port */
-	u8                      acpi_enable;        /* value to write to smi_cmd to enable ACPI */
-	u8                      acpi_disable;       /* value to write to smi_cmd to disable ACPI */
+	u8                      acpi_enable;        /* Value to write to smi_cmd to enable ACPI */
+	u8                      acpi_disable;       /* Value to write to smi_cmd to disable ACPI */
 	u8                      S4bios_req;         /* Value to write to SMI CMD to enter S4BIOS state */
-	u8                      pstate_cnt;         /* processor performance state control*/
+	u8                      pstate_cnt;         /* Processor performance state control*/
 	u32                     V1_pm1a_evt_blk;    /* Port address of Power Mgt 1a Acpi_event Reg Blk */
 	u32                     V1_pm1b_evt_blk;    /* Port address of Power Mgt 1b Acpi_event Reg Blk */
 	u32                     V1_pm1a_cnt_blk;    /* Port address of Power Mgt 1a Control Reg Blk */
 	u32                     V1_pm1b_cnt_blk;    /* Port address of Power Mgt 1b Control Reg Blk */
 	u32                     V1_pm2_cnt_blk;     /* Port address of Power Mgt 2 Control Reg Blk */
 	u32                     V1_pm_tmr_blk;      /* Port address of Power Mgt Timer Ctrl Reg Blk */
-	u32                     V1_gpe0blk;         /* Port addr of General Purpose Acpi_event 0 Reg Blk */
+	u32                     V1_gpe0_blk;        /* Port addr of General Purpose Acpi_event 0 Reg Blk */
 	u32                     V1_gpe1_blk;        /* Port addr of General Purpose Acpi_event 1 Reg Blk */
 	u8                      pm1_evt_len;        /* Byte Length of ports at pm1_x_evt_blk */
 	u8                      pm1_cnt_len;        /* Byte Length of ports at pm1_x_cnt_blk */
 	u8                      pm2_cnt_len;        /* Byte Length of ports at pm2_cnt_blk */
 	u8                      pm_tm_len;          /* Byte Length of ports at pm_tm_blk */
-	u8                      gpe0blk_len;        /* Byte Length of ports at gpe0_blk */
+	u8                      gpe0_blk_len;       /* Byte Length of ports at gpe0_blk */
 	u8                      gpe1_blk_len;       /* Byte Length of ports at gpe1_blk */
-	u8                      gpe1_base;          /* offset in gpe model where gpe1 events start */
+	u8                      gpe1_base;          /* Offset in gpe model where gpe1 events start */
 	u8                      cst_cnt;            /* Support for the _CST object and C States change notification.*/
-	u16                     plvl2_lat;          /* worst case HW latency to enter/exit C2 state */
-	u16                     plvl3_lat;          /* worst case HW latency to enter/exit C3 state */
-	u16                     flush_size;         /* number of flush strides that need to be read */
+	u16                     plvl2_lat;          /* Worst case HW latency to enter/exit C2 state */
+	u16                     plvl3_lat;          /* Worst case HW latency to enter/exit C3 state */
+	u16                     flush_size;         /* Number of flush strides that need to be read */
 	u16                     flush_stride;       /* Processor's memory cache line width, in bytes */
 	u8                      duty_offset;        /* Processor_s duty cycle index in processor's P_CNT reg*/
 	u8                      duty_width;         /* Processor_s duty cycle value bit width in P_CNT register.*/
-	u8                      day_alrm;           /* index to day-of-month alarm in RTC CMOS RAM */
-	u8                      mon_alrm;           /* index to month-of-year alarm in RTC CMOS RAM */
-	u8                      century;            /* index to century in RTC CMOS RAM */
+	u8                      day_alrm;           /* Index to day-of-month alarm in RTC CMOS RAM */
+	u8                      mon_alrm;           /* Index to month-of-year alarm in RTC CMOS RAM */
+	u8                      century;            /* Index to century in RTC CMOS RAM */
 	u16                     iapc_boot_arch;     /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/
-	u8                      reserved2;          /* reserved */
-	u32                     wb_invd     : 1;    /* wbinvd instruction works properly */
-	u32                     wb_invd_flush : 1;  /* wbinvd flushes but does not invalidate */
-	u32                     proc_c1     : 1;    /* all processors support C1 state */
+	u8                      reserved2;          /* Reserved */
+	u32                     wb_invd     : 1;    /* The wbinvd instruction works properly */
+	u32                     wb_invd_flush : 1;  /* The wbinvd flushes but does not invalidate */
+	u32                     proc_c1     : 1;    /* All processors support C1 state */
 	u32                     plvl2_up    : 1;    /* C2 state works on MP system */
 	u32                     pwr_button  : 1;    /* Power button is handled as a generic feature */
 	u32                     sleep_button : 1;   /* Sleep button is handled as a generic feature, or not present */
 	u32                     fixed_rTC   : 1;    /* RTC wakeup stat not in fixed register space */
 	u32                     rtcs4       : 1;    /* RTC wakeup stat not possible from S4 */
-	u32                     tmr_val_ext : 1;    /* tmr_val is 32 bits */
+	u32                     tmr_val_ext : 1;    /* Indicates tmr_val is 32 bits 0=24-bits*/
 	u32                     dock_cap    : 1;    /* Supports Docking */
 	u32                     reset_reg_sup : 1;  /* Indicates system supports system reset via the FADT RESET_REG*/
 	u32                     sealed_case : 1;    /* Indicates system has no internal expansion capabilities and case is sealed. */
 	u32                     headless    : 1;    /* Indicates system does not have local video capabilities or local input devices.*/
 	u32                     cpu_sw_sleep : 1;   /* Indicates to OSPM that a processor native instruction */
-			   /* must be executed after writing the SLP_TYPx register. */
-	u32                     reserved6   : 18;   /* reserved - must be zero */
+			   /* Must be executed after writing the SLP_TYPx register. */
+	u32                     reserved6   : 18;   /* Reserved - must be zero */
 
 	acpi_generic_address    reset_register;     /* Reset register address in GAS format */
 	u8                      reset_value;        /* Value to write to the Reset_register port to reset the system. */
@@ -174,7 +174,7 @@
 	acpi_generic_address    Xpm1b_cnt_blk;      /* Extended Power Mgt 1b Control Reg Blk address */
 	acpi_generic_address    Xpm2_cnt_blk;       /* Extended Power Mgt 2 Control Reg Blk address */
 	acpi_generic_address    Xpm_tmr_blk;        /* Extended Power Mgt Timer Ctrl Reg Blk address */
-	acpi_generic_address    Xgpe0blk;           /* Extended General Purpose Acpi_event 0 Reg Blk address */
+	acpi_generic_address    Xgpe0_blk;          /* Extended General Purpose Acpi_event 0 Reg Blk address */
 	acpi_generic_address    Xgpe1_blk;          /* Extended General Purpose Acpi_event 1 Reg Blk address */
 
 }  fadt_descriptor_rev2;
diff -Nru a/drivers/acpi/include/actbl71.h b/drivers/acpi/include/actbl71.h
--- a/drivers/acpi/include/actbl71.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/actbl71.h	Fri Mar 15 17:51:03 2002
@@ -3,12 +3,12 @@
  * Name: actbl71.h - IA-64 Extensions to the ACPI Spec Rev. 0.71
  *                   This file includes tables specific to this
  *                   specification revision.
- *       $Revision: 11 $
+ *       $Revision: 12 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -111,13 +111,13 @@
 	u64                 pm1b_cnt_blk;       /* Port address of Power Mgt 1b Control Reg Blk */
 	u64                 pm2_cnt_blk;        /* Port address of Power Mgt 2 Control Reg Blk */
 	u64                 pm_tmr_blk;         /* Port address of Power Mgt Timer Ctrl Reg Blk */
-	u64                 gpe0blk;            /* Port addr of General Purpose Acpi_event 0 Reg Blk */
+	u64                 gpe0_blk;           /* Port addr of General Purpose Acpi_event 0 Reg Blk */
 	u64                 gpe1_blk;           /* Port addr of General Purpose Acpi_event 1 Reg Blk */
 	u8                  pm1_evt_len;        /* Byte Length of ports at pm1_x_evt_blk */
 	u8                  pm1_cnt_len;        /* Byte Length of ports at pm1_x_cnt_blk */
 	u8                  pm2_cnt_len;        /* Byte Length of ports at pm2_cnt_blk */
 	u8                  pm_tm_len;          /* Byte Length of ports at pm_tm_blk */
-	u8                  gpe0blk_len;        /* Byte Length of ports at gpe0_blk */
+	u8                  gpe0_blk_len;       /* Byte Length of ports at gpe0_blk */
 	u8                  gpe1_blk_len;       /* Byte Length of ports at gpe1_blk */
 	u8                  gpe1_base;          /* offset in gpe model where gpe1 events start */
 	u8                  reserved3;          /* reserved */
diff -Nru a/drivers/acpi/include/actypes.h b/drivers/acpi/include/actypes.h
--- a/drivers/acpi/include/actypes.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/actypes.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: actypes.h - Common data types for the entire ACPI subsystem
- *       $Revision: 193 $
+ *       $Revision: 224 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -45,7 +45,6 @@
  * UINT64       64-bit (8 byte) unsigned value
  * NATIVE_INT   32-bit on IA-32, 64-bit on IA-64 signed value
  * NATIVE_UINT  32-bit on IA-32, 64-bit on IA-64 unsigned value
- * UCHAR        Character. 1 byte unsigned value.
  */
 
 
@@ -55,21 +54,22 @@
  */
 typedef unsigned char                   UINT8;
 typedef unsigned char                   BOOLEAN;
-typedef unsigned char                   UCHAR;
 typedef unsigned short                  UINT16;
 typedef int                             INT32;
 typedef unsigned int                    UINT32;
 typedef COMPILER_DEPENDENT_UINT64       UINT64;
 
 typedef UINT64                          NATIVE_UINT;
-typedef INT64                           NATIVE_INT;
+typedef UINT64                          NATIVE_INT;
 
 typedef NATIVE_UINT                     ACPI_TBLPTR;
 typedef UINT64                          ACPI_IO_ADDRESS;
 typedef UINT64                          ACPI_PHYSICAL_ADDRESS;
+typedef UINT64                          ACPI_SIZE;
 
 #define ALIGNED_ADDRESS_BOUNDARY        0x00000008      /* No hardware alignment support in IA64 */
 #define ACPI_USE_NATIVE_DIVIDE                          /* Native 64-bit integer support */
+#define ACPI_MAX_PTR                    0xFFFFFFFFFFFFFFFF
 
 
 #elif _IA16
@@ -78,7 +78,6 @@
  */
 typedef unsigned char                   UINT8;
 typedef unsigned char                   BOOLEAN;
-typedef unsigned char                   UCHAR;
 typedef unsigned int                    UINT16;
 typedef long                            INT32;
 typedef int                             INT16;
@@ -97,10 +96,12 @@
 typedef UINT32                          ACPI_TBLPTR;
 typedef UINT32                          ACPI_IO_ADDRESS;
 typedef char                            *ACPI_PHYSICAL_ADDRESS;
+typedef UINT32                          ACPI_SIZE;
 
 #define ALIGNED_ADDRESS_BOUNDARY        0x00000002
 #define _HW_ALIGNMENT_SUPPORT
 #define ACPI_USE_NATIVE_DIVIDE                          /* No 64-bit integers, ok to use native divide */
+#define ACPI_MAX_PTR                    0xFFFF
 
 /*
  * (16-bit only) internal integers must be 32-bits, so
@@ -115,7 +116,6 @@
  */
 typedef unsigned char                   UINT8;
 typedef unsigned char                   BOOLEAN;
-typedef unsigned char                   UCHAR;
 typedef unsigned short                  UINT16;
 typedef int                             INT32;
 typedef unsigned int                    UINT32;
@@ -127,9 +127,11 @@
 typedef NATIVE_UINT                     ACPI_TBLPTR;
 typedef UINT32                          ACPI_IO_ADDRESS;
 typedef UINT64                          ACPI_PHYSICAL_ADDRESS;
+typedef UINT32                          ACPI_SIZE;
 
 #define ALIGNED_ADDRESS_BOUNDARY        0x00000004
 #define _HW_ALIGNMENT_SUPPORT
+#define ACPI_MAX_PTR                    0xFFFFFFFF
 #endif
 
 
@@ -151,11 +153,13 @@
 #define ACPI_UINT16_MAX                 (UINT16) 0xFFFF
 #define ACPI_UINT32_MAX                 (UINT32) 0xFFFFFFFF
 #define ACPI_UINT64_MAX                 (UINT64) 0xFFFFFFFFFFFFFFFF
+#define ACPI_ASCII_MAX                  0x7F
 
 
 #ifdef DEFINE_ALTERNATE_TYPES
 /*
- * Types used only in translated source
+ * Types used only in translated source, defined here to enable
+ * cross-platform compilation only.
  */
 typedef INT32                           s32;
 typedef UINT8                           u8;
@@ -251,7 +255,7 @@
  * Constants with special meanings
  */
 
-#define ACPI_ROOT_OBJECT                (acpi_handle)(-1)
+#define ACPI_ROOT_OBJECT                (acpi_handle) ACPI_PTR_ADD (char, NULL, ACPI_UINT32_MAX)
 
 
 /*
@@ -261,9 +265,10 @@
 #define ACPI_NO_ADDRESS_SPACE_INIT      0x01
 #define ACPI_NO_HARDWARE_INIT           0x02
 #define ACPI_NO_EVENT_INIT              0x04
-#define ACPI_NO_ACPI_ENABLE             0x08
-#define ACPI_NO_DEVICE_INIT             0x10
-#define ACPI_NO_OBJECT_INIT             0x20
+#define ACPI_NO_HANDLER_INIT            0x08
+#define ACPI_NO_ACPI_ENABLE             0x10
+#define ACPI_NO_DEVICE_INIT             0x20
+#define ACPI_NO_OBJECT_INIT             0x40
 
 /*
  * Initialization state
@@ -292,6 +297,19 @@
 #define ACPI_D_STATES_MAX               ACPI_STATE_D3
 #define ACPI_D_STATE_COUNT              4
 
+#define ACPI_STATE_C0                   (u8) 0
+#define ACPI_STATE_C1                   (u8) 1
+#define ACPI_STATE_C2                   (u8) 2
+#define ACPI_STATE_C3                   (u8) 3
+#define ACPI_C_STATES_MAX               ACPI_STATE_C3
+#define ACPI_C_STATE_COUNT              4
+
+/*
+ * Sleep type invalid value
+ */
+#define ACPI_SLEEP_TYPE_MAX             0x7
+#define ACPI_SLEEP_TYPE_INVALID         0xFF
+
 /*
  * Standard notify values
  */
@@ -326,35 +344,33 @@
  * Types associated with names.  The first group of
  * values correspond to the definition of the ACPI
  * Object_type operator (See the ACPI Spec). Therefore,
- * only add to the first group if the spec changes!
+ * only add to the first group if the spec changes.
  *
  * Types must be kept in sync with the Acpi_ns_properties
  * and Acpi_ns_type_names arrays
  */
 
 typedef u32                             acpi_object_type;
-typedef u8                              acpi_object_type8;
-
 
-#define ACPI_TYPE_ANY                   0  /* 0x00  */
-#define ACPI_TYPE_INTEGER               1  /* 0x01  Byte/Word/Dword/Zero/One/Ones */
-#define ACPI_TYPE_STRING                2  /* 0x02  */
-#define ACPI_TYPE_BUFFER                3  /* 0x03  */
-#define ACPI_TYPE_PACKAGE               4  /* 0x04  Byte_const, multiple Data_term/Constant/Super_name */
-#define ACPI_TYPE_FIELD_UNIT            5  /* 0x05  */
-#define ACPI_TYPE_DEVICE                6  /* 0x06  Name, multiple Node */
-#define ACPI_TYPE_EVENT                 7  /* 0x07  */
-#define ACPI_TYPE_METHOD                8  /* 0x08  Name, Byte_const, multiple Code */
-#define ACPI_TYPE_MUTEX                 9  /* 0x09  */
-#define ACPI_TYPE_REGION                10 /* 0x0A  */
-#define ACPI_TYPE_POWER                 11 /* 0x0B  Name,Byte_const,Word_const,multi Node */
-#define ACPI_TYPE_PROCESSOR             12 /* 0x0C  Name,Byte_const,DWord_const,Byte_const,multi Nm_o */
-#define ACPI_TYPE_THERMAL               13 /* 0x0D  Name, multiple Node */
-#define ACPI_TYPE_BUFFER_FIELD          14 /* 0x0E  */
-#define ACPI_TYPE_DDB_HANDLE            15 /* 0x0F  */
-#define ACPI_TYPE_DEBUG_OBJECT          16 /* 0x10  */
+#define ACPI_TYPE_ANY                   0x00
+#define ACPI_TYPE_INTEGER               0x01  /* Byte/Word/Dword/Zero/One/Ones */
+#define ACPI_TYPE_STRING                0x02
+#define ACPI_TYPE_BUFFER                0x03
+#define ACPI_TYPE_PACKAGE               0x04  /* Byte_const, multiple Data_term/Constant/Super_name */
+#define ACPI_TYPE_FIELD_UNIT            0x05
+#define ACPI_TYPE_DEVICE                0x06  /* Name, multiple Node */
+#define ACPI_TYPE_EVENT                 0x07
+#define ACPI_TYPE_METHOD                0x08  /* Name, Byte_const, multiple Code */
+#define ACPI_TYPE_MUTEX                 0x09
+#define ACPI_TYPE_REGION                0x0A
+#define ACPI_TYPE_POWER                 0x0B  /* Name,Byte_const,Word_const,multi Node */
+#define ACPI_TYPE_PROCESSOR             0x0C  /* Name,Byte_const,DWord_const,Byte_const,multi Nm_o */
+#define ACPI_TYPE_THERMAL               0x0D  /* Name, multiple Node */
+#define ACPI_TYPE_BUFFER_FIELD          0x0E
+#define ACPI_TYPE_DDB_HANDLE            0x0F
+#define ACPI_TYPE_DEBUG_OBJECT          0x10
 
-#define ACPI_TYPE_MAX                   16
+#define ACPI_TYPE_MAX                   0x10
 
 /*
  * This section contains object types that do not relate to the ACPI Object_type operator.
@@ -363,36 +379,37 @@
  * Also, values exceeding the largest official ACPI Object_type must not overlap with
  * defined AML opcodes.
  */
-#define INTERNAL_TYPE_BEGIN             17
+#define INTERNAL_TYPE_BEGIN             0x11
 
-#define INTERNAL_TYPE_REGION_FIELD      17 /* 0x11  */
-#define INTERNAL_TYPE_BANK_FIELD        18 /* 0x12  */
-#define INTERNAL_TYPE_INDEX_FIELD       19 /* 0x13  */
-#define INTERNAL_TYPE_REFERENCE         20 /* 0x14  Arg#, Local#, Name, Debug; used only in descriptors */
-#define INTERNAL_TYPE_ALIAS             21 /* 0x15  */
-#define INTERNAL_TYPE_NOTIFY            22 /* 0x16  */
-#define INTERNAL_TYPE_ADDRESS_HANDLER   23 /* 0x17  */
-#define INTERNAL_TYPE_RESOURCE          24 /* 0x18  */
-#define INTERNAL_TYPE_RESOURCE_FIELD    25 /* 0x19  */
+#define INTERNAL_TYPE_REGION_FIELD      0x11
+#define INTERNAL_TYPE_BANK_FIELD        0x12
+#define INTERNAL_TYPE_INDEX_FIELD       0x13
+#define INTERNAL_TYPE_REFERENCE         0x14  /* Arg#, Local#, Name, Debug; used only in descriptors */
+#define INTERNAL_TYPE_ALIAS             0x15
+#define INTERNAL_TYPE_NOTIFY            0x16
+#define INTERNAL_TYPE_ADDRESS_HANDLER   0x17
+#define INTERNAL_TYPE_RESOURCE          0x18
+#define INTERNAL_TYPE_RESOURCE_FIELD    0x19
 
 
-#define INTERNAL_TYPE_NODE_MAX          25
+#define INTERNAL_TYPE_NODE_MAX          0x19
 
 /* These are pseudo-types because there are never any namespace nodes with these types */
 
-#define INTERNAL_TYPE_FIELD_DEFN        26 /* 0x1A  Name, Byte_const, multiple Field_element */
-#define INTERNAL_TYPE_BANK_FIELD_DEFN   27 /* 0x1B  2 Name,DWord_const,Byte_const,multi Field_element */
-#define INTERNAL_TYPE_INDEX_FIELD_DEFN  28 /* 0x1C  2 Name, Byte_const, multiple Field_element */
-#define INTERNAL_TYPE_IF                29 /* 0x1D  */
-#define INTERNAL_TYPE_ELSE              30 /* 0x1E  */
-#define INTERNAL_TYPE_WHILE             31 /* 0x1F  */
-#define INTERNAL_TYPE_SCOPE             32 /* 0x20  Name, multiple Node */
-#define INTERNAL_TYPE_DEF_ANY           33 /* 0x21  type is Any, suppress search of enclosing scopes */
-#define INTERNAL_TYPE_EXTRA             34 /* 0x22  */
+#define INTERNAL_TYPE_FIELD_DEFN        0x1A  /* Name, Byte_const, multiple Field_element */
+#define INTERNAL_TYPE_BANK_FIELD_DEFN   0x1B  /* 2 Name,DWord_const,Byte_const,multi Field_element */
+#define INTERNAL_TYPE_INDEX_FIELD_DEFN  0x1C  /* 2 Name, Byte_const, multiple Field_element */
+#define INTERNAL_TYPE_IF                0x1D
+#define INTERNAL_TYPE_ELSE              0x1E
+#define INTERNAL_TYPE_WHILE             0x1F
+#define INTERNAL_TYPE_SCOPE             0x20  /* Name, multiple Node */
+#define INTERNAL_TYPE_DEF_ANY           0x21  /* type is Any, suppress search of enclosing scopes */
+#define INTERNAL_TYPE_EXTRA             0x22
+#define INTERNAL_TYPE_DATA              0x23
 
-#define INTERNAL_TYPE_MAX               34
+#define INTERNAL_TYPE_MAX               0x23
 
-#define INTERNAL_TYPE_INVALID           35
+#define INTERNAL_TYPE_INVALID           0x24
 #define ACPI_TYPE_NOT_FOUND             0xFF
 
 
@@ -428,51 +445,48 @@
 #define ACPI_BTYPE_OBJECTS_AND_REFS     0x0001FFFF  /* ARG or LOCAL */
 #define ACPI_BTYPE_ALL_OBJECTS          0x0000FFFF
 
+/*
+ * All I/O
+ */
+#define ACPI_READ                       0
+#define ACPI_WRITE                      1
+
 
 /*
- * Acpi_event Types:
- * ------------
- * Fixed & general purpose...
+ * Acpi_event Types: Fixed & General Purpose
  */
 
 typedef u32                             acpi_event_type;
 
-#define ACPI_EVENT_FIXED                (acpi_event_type) 0
-#define ACPI_EVENT_GPE                  (acpi_event_type) 1
+#define ACPI_EVENT_FIXED                0
+#define ACPI_EVENT_GPE                  1
 
 /*
  * Fixed events
  */
 
-#define ACPI_EVENT_PMTIMER              (acpi_event_type) 0
-	/*
-	 * There's no bus master event so index 1 is used for IRQ's that are not
-	 * handled by the SCI handler
-	 */
-#define ACPI_EVENT_NOT_USED             (acpi_event_type) 1
-#define ACPI_EVENT_GLOBAL               (acpi_event_type) 2
-#define ACPI_EVENT_POWER_BUTTON         (acpi_event_type) 3
-#define ACPI_EVENT_SLEEP_BUTTON         (acpi_event_type) 4
-#define ACPI_EVENT_RTC                  (acpi_event_type) 5
-#define ACPI_EVENT_GENERAL              (acpi_event_type) 6
-#define ACPI_EVENT_MAX                  6
-#define ACPI_NUM_FIXED_EVENTS           (acpi_event_type) 7
+#define ACPI_EVENT_PMTIMER              0
+#define ACPI_EVENT_GLOBAL               1
+#define ACPI_EVENT_POWER_BUTTON         2
+#define ACPI_EVENT_SLEEP_BUTTON         3
+#define ACPI_EVENT_RTC                  4
+#define ACPI_EVENT_MAX                  4
+#define ACPI_NUM_FIXED_EVENTS           ACPI_EVENT_MAX + 1
 
 #define ACPI_GPE_INVALID                0xFF
 #define ACPI_GPE_MAX                    0xFF
 #define ACPI_NUM_GPE                    256
 
-#define ACPI_EVENT_LEVEL_TRIGGERED      (acpi_event_type) 1
-#define ACPI_EVENT_EDGE_TRIGGERED       (acpi_event_type) 2
+#define ACPI_EVENT_LEVEL_TRIGGERED      1
+#define ACPI_EVENT_EDGE_TRIGGERED       2
 
 /*
  * GPEs
  */
-#define ACPI_EVENT_ENABLE               0x1
-#define ACPI_EVENT_WAKE_ENABLE	        0x2
 
-#define ACPI_EVENT_DISABLE              0x1
-#define ACPI_EVENT_WAKE_DISABLE         0x2
+#define ACPI_EVENT_WAKE_ENABLE          0x1
+
+#define ACPI_EVENT_WAKE_DISABLE         0x1
 
 
 /*
@@ -504,7 +518,7 @@
 #define ACPI_DEVICE_NOTIFY              1
 #define ACPI_MAX_NOTIFY_HANDLER_TYPE    1
 
-#define MAX_SYS_NOTIFY                  0x7f
+#define ACPI_MAX_SYS_NOTIFY                  0x7f
 
 
 /* Address Space (Operation Region) Types */
@@ -518,6 +532,7 @@
 #define ACPI_ADR_SPACE_SMBUS            (ACPI_ADR_SPACE_TYPE) 4
 #define ACPI_ADR_SPACE_CMOS             (ACPI_ADR_SPACE_TYPE) 5
 #define ACPI_ADR_SPACE_PCI_BAR_TARGET   (ACPI_ADR_SPACE_TYPE) 6
+#define ACPI_ADR_SPACE_DATA_TABLE       (ACPI_ADR_SPACE_TYPE) 7
 
 
 /*
@@ -576,7 +591,7 @@
 		u32                         resource_order;
 	} power_resource;
 
-} acpi_object, *PACPI_OBJECT;
+} acpi_object;
 
 
 /*
@@ -588,16 +603,20 @@
 	u32                         count;
 	acpi_object                 *pointer;
 
-} acpi_object_list, *PACPI_OBJECT_LIST;
+} acpi_object_list;
 
 
 /*
  * Miscellaneous common Data Structures used by the interfaces
  */
 
+#define ACPI_NO_BUFFER              0
+#define ACPI_ALLOCATE_BUFFER        (ACPI_SIZE) (-1)
+#define ACPI_ALLOCATE_LOCAL_BUFFER  (ACPI_SIZE) (-2)
+
 typedef struct
 {
-	u32                         length;         /* Length in bytes of the buffer */
+	ACPI_SIZE                   length;         /* Length in bytes of the buffer */
 	void                        *pointer;       /* pointer to buffer */
 
 } acpi_buffer;
@@ -616,10 +635,10 @@
  * Structure and flags for Acpi_get_system_info
  */
 
-#define SYS_MODE_UNKNOWN                0x0000
-#define SYS_MODE_ACPI                   0x0001
-#define SYS_MODE_LEGACY                 0x0002
-#define SYS_MODES_MASK                  0x0003
+#define ACPI_SYS_MODE_UNKNOWN           0x0000
+#define ACPI_SYS_MODE_ACPI              0x0001
+#define ACPI_SYS_MODE_LEGACY            0x0002
+#define ACPI_SYS_MODES_MASK             0x0003
 
 
 /*
@@ -669,22 +688,25 @@
 	u32                         value,
 	void                        *context);
 
+typedef
+void (*ACPI_OBJECT_HANDLER) (
+	acpi_handle                 object,
+	u32                         function,
+	void                        *data);
 
-/* Address Spaces (Operation Regions */
 
-#define ACPI_READ_ADR_SPACE     1
-#define ACPI_WRITE_ADR_SPACE    2
+/* Address Spaces (Operation Regions */
 
 typedef
 acpi_status (*acpi_adr_space_handler) (
 	u32                         function,
 	ACPI_PHYSICAL_ADDRESS       address,
 	u32                         bit_width,
-	u32                         *value,
+	acpi_integer                *value,
 	void                        *handler_context,
 	void                        *region_context);
 
-#define ACPI_DEFAULT_HANDLER            ((acpi_adr_space_handler) NULL)
+#define ACPI_DEFAULT_HANDLER        ((acpi_adr_space_handler) NULL)
 
 
 typedef
@@ -707,8 +729,8 @@
 
 /* Interrupt handler return values */
 
-#define INTERRUPT_NOT_HANDLED           0x00
-#define INTERRUPT_HANDLED               0x01
+#define ACPI_INTERRUPT_NOT_HANDLED      0x00
+#define ACPI_INTERRUPT_HANDLED          0x01
 
 
 /* Structure and flags for Acpi_get_device_info */
@@ -755,6 +777,8 @@
 
 typedef struct
 {
+	u32                         length;
+	ACPI_PHYSICAL_ADDRESS       address;
 	ACPI_PHYSICAL_ADDRESS       mapped_physical_address;
 	u8                          *mapped_logical_address;
 	u32                         mapped_length;
@@ -773,78 +797,78 @@
 /*
  *  Memory Attributes
  */
-#define READ_ONLY_MEMORY                (u8) 0x00
-#define READ_WRITE_MEMORY               (u8) 0x01
+#define ACPI_READ_ONLY_MEMORY           (u8) 0x00
+#define ACPI_READ_WRITE_MEMORY          (u8) 0x01
 
-#define NON_CACHEABLE_MEMORY            (u8) 0x00
-#define CACHABLE_MEMORY                 (u8) 0x01
-#define WRITE_COMBINING_MEMORY          (u8) 0x02
-#define PREFETCHABLE_MEMORY             (u8) 0x03
+#define ACPI_NON_CACHEABLE_MEMORY       (u8) 0x00
+#define ACPI_CACHABLE_MEMORY            (u8) 0x01
+#define ACPI_WRITE_COMBINING_MEMORY     (u8) 0x02
+#define ACPI_PREFETCHABLE_MEMORY        (u8) 0x03
 
 /*
  *  IO Attributes
- *  The ISA IO ranges are:     n000-n0FFh,  n400-n4_fFh, n800-n8_fFh, n_c00-n_cFFh.
+ *  The ISA IO ranges are:     n000-n0_fFh, n400-n4_fFh, n800-n8_fFh, n_c00-n_cFFh.
  *  The non-ISA IO ranges are: n100-n3_fFh, n500-n7_fFh, n900-n_bFFh, n_cD0-n_fFFh.
  */
-#define NON_ISA_ONLY_RANGES             (u8) 0x01
-#define ISA_ONLY_RANGES                 (u8) 0x02
-#define ENTIRE_RANGE                    (NON_ISA_ONLY_RANGES | ISA_ONLY_RANGES)
+#define ACPI_NON_ISA_ONLY_RANGES        (u8) 0x01
+#define ACPI_ISA_ONLY_RANGES            (u8) 0x02
+#define ACPI_ENTIRE_RANGE               (ACPI_NON_ISA_ONLY_RANGES | ACPI_ISA_ONLY_RANGES)
 
 /*
  *  IO Port Descriptor Decode
  */
-#define DECODE_10                       (u8) 0x00    /* 10-bit IO address decode */
-#define DECODE_16                       (u8) 0x01    /* 16-bit IO address decode */
+#define ACPI_DECODE_10                  (u8) 0x00    /* 10-bit IO address decode */
+#define ACPI_DECODE_16                  (u8) 0x01    /* 16-bit IO address decode */
 
 /*
  *  IRQ Attributes
  */
-#define EDGE_SENSITIVE                  (u8) 0x00
-#define LEVEL_SENSITIVE                 (u8) 0x01
+#define ACPI_EDGE_SENSITIVE             (u8) 0x00
+#define ACPI_LEVEL_SENSITIVE            (u8) 0x01
 
-#define ACTIVE_HIGH                     (u8) 0x00
-#define ACTIVE_LOW                      (u8) 0x01
+#define ACPI_ACTIVE_HIGH                (u8) 0x00
+#define ACPI_ACTIVE_LOW                 (u8) 0x01
 
-#define EXCLUSIVE                       (u8) 0x00
-#define SHARED                          (u8) 0x01
+#define ACPI_EXCLUSIVE                  (u8) 0x00
+#define ACPI_SHARED                     (u8) 0x01
 
 /*
  *  DMA Attributes
  */
-#define COMPATIBILITY                   (u8) 0x00
-#define TYPE_A                          (u8) 0x01
-#define TYPE_B                          (u8) 0x02
-#define TYPE_F                          (u8) 0x03
-
-#define NOT_BUS_MASTER                  (u8) 0x00
-#define BUS_MASTER                      (u8) 0x01
-
-#define TRANSFER_8                      (u8) 0x00
-#define TRANSFER_8_16                   (u8) 0x01
-#define TRANSFER_16                     (u8) 0x02
+#define ACPI_COMPATIBILITY              (u8) 0x00
+#define ACPI_TYPE_A                     (u8) 0x01
+#define ACPI_TYPE_B                     (u8) 0x02
+#define ACPI_TYPE_F                     (u8) 0x03
+
+#define ACPI_NOT_BUS_MASTER             (u8) 0x00
+#define ACPI_BUS_MASTER                 (u8) 0x01
+
+#define ACPI_TRANSFER_8                 (u8) 0x00
+#define ACPI_TRANSFER_8_16              (u8) 0x01
+#define ACPI_TRANSFER_16                (u8) 0x02
 
 /*
  * Start Dependent Functions Priority definitions
  */
-#define GOOD_CONFIGURATION              (u8) 0x00
-#define ACCEPTABLE_CONFIGURATION        (u8) 0x01
-#define SUB_OPTIMAL_CONFIGURATION       (u8) 0x02
+#define ACPI_GOOD_CONFIGURATION         (u8) 0x00
+#define ACPI_ACCEPTABLE_CONFIGURATION   (u8) 0x01
+#define ACPI_SUB_OPTIMAL_CONFIGURATION  (u8) 0x02
 
 /*
  *  16, 32 and 64-bit Address Descriptor resource types
  */
-#define MEMORY_RANGE                    (u8) 0x00
-#define IO_RANGE                        (u8) 0x01
-#define BUS_NUMBER_RANGE                (u8) 0x02
+#define ACPI_MEMORY_RANGE               (u8) 0x00
+#define ACPI_IO_RANGE                   (u8) 0x01
+#define ACPI_BUS_NUMBER_RANGE           (u8) 0x02
 
-#define ADDRESS_NOT_FIXED               (u8) 0x00
-#define ADDRESS_FIXED                   (u8) 0x01
+#define ACPI_ADDRESS_NOT_FIXED          (u8) 0x00
+#define ACPI_ADDRESS_FIXED              (u8) 0x01
 
-#define POS_DECODE                      (u8) 0x00
-#define SUB_DECODE                      (u8) 0x01
+#define ACPI_POS_DECODE                 (u8) 0x00
+#define ACPI_SUB_DECODE                 (u8) 0x01
 
-#define PRODUCER                        (u8) 0x00
-#define CONSUMER                        (u8) 0x01
+#define ACPI_PRODUCER                   (u8) 0x00
+#define ACPI_CONSUMER                   (u8) 0x01
 
 
 /*
@@ -908,6 +932,12 @@
 
 typedef struct
 {
+	u8                          checksum;
+
+} ACPI_RESOURCE_END_TAG;
+
+typedef struct
+{
 	u32                         read_write_attribute;
 	u32                         min_base_address;
 	u32                         max_base_address;
@@ -1053,7 +1083,7 @@
 #define ACPI_RSTYPE_ADDRESS64           13
 #define ACPI_RSTYPE_EXT_IRQ             14
 
-typedef u32                     acpi_resource_type;
+typedef u32                             acpi_resource_type;
 
 typedef union
 {
@@ -1063,6 +1093,7 @@
 	acpi_resource_io            io;
 	acpi_resource_fixed_io      fixed_io;
 	acpi_resource_vendor        vendor_specific;
+	ACPI_RESOURCE_END_TAG       end_tag;
 	acpi_resource_mem24         memory24;
 	acpi_resource_mem32         memory32;
 	acpi_resource_fixed_mem32   fixed_memory32;
@@ -1081,20 +1112,25 @@
 
 } acpi_resource;
 
-#define ACPI_RESOURCE_LENGTH            12
-#define ACPI_RESOURCE_LENGTH_NO_DATA    8       /* Id + Length fields */
+#define ACPI_RESOURCE_LENGTH                12
+#define ACPI_RESOURCE_LENGTH_NO_DATA        8       /* Id + Length fields */
 
-#define SIZEOF_RESOURCE(type)   (ACPI_RESOURCE_LENGTH_NO_DATA + sizeof (type))
+#define ACPI_SIZEOF_RESOURCE(type)          (ACPI_RESOURCE_LENGTH_NO_DATA + sizeof (type))
 
-#define NEXT_RESOURCE(res)      (acpi_resource *)((u8 *) res + res->length)
+#define ACPI_NEXT_RESOURCE(res)             (acpi_resource *)((u8 *) res + res->length)
 
+#ifdef _HW_ALIGNMENT_SUPPORT
+#define ACPI_ALIGN_RESOURCE_SIZE(length)    (length)
+#else
+#define ACPI_ALIGN_RESOURCE_SIZE(length)    ACPI_ROUND_UP_TO_NATIVE_WORD(length)
+#endif
 
 /*
- * END: Definitions for Resource Attributes
+ * END: of definitions for Resource Attributes
  */
 
 
-typedef struct pci_routing_table
+typedef struct acpi_pci_routing_table
 {
 	u32                         length;
 	u32                         pin;
@@ -1102,11 +1138,11 @@
 	u32                         source_index;
 	NATIVE_CHAR                 source[4];      /* pad to 64 bits so sizeof() works in all cases */
 
-} pci_routing_table;
-
+} acpi_pci_routing_table;
 
 /*
- * END: Definitions for PCI Routing tables
+ * END: of definitions for PCI Routing tables
  */
+
 
 #endif /* __ACTYPES_H__ */
diff -Nru a/drivers/acpi/include/acutils.h b/drivers/acpi/include/acutils.h
--- a/drivers/acpi/include/acutils.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/include/acutils.h	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acutils.h -- prototypes for the common (subsystem-wide) procedures
- *       $Revision: 117 $
+ *       $Revision: 130 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -46,7 +46,7 @@
 typedef struct acpi_pkg_info
 {
 	u8                      *free_space;
-	u32                     length;
+	ACPI_SIZE               length;
 	u32                     object_space;
 	u32                     num_packages;
 } acpi_pkg_info;
@@ -102,14 +102,18 @@
 
 NATIVE_CHAR *
 acpi_ut_get_type_name (
-	u32                     type);
+	acpi_object_type        type);
+
+#endif
+
 
 NATIVE_CHAR *
 acpi_ut_get_region_name (
 	u8                      space_id);
 
-#endif
-
+NATIVE_CHAR *
+acpi_ut_get_event_name (
+	u32                     event_id);
 
 u8
 acpi_ut_hex_to_ascii_char (
@@ -118,7 +122,7 @@
 
 u8
 acpi_ut_valid_object_type (
-	u32                     type);
+	acpi_object_type        type);
 
 acpi_owner_id
 acpi_ut_allocate_owner_id (
@@ -244,6 +248,17 @@
 	acpi_operand_object     *dest_obj,
 	acpi_walk_state         *walk_state);
 
+acpi_status
+acpi_ut_copy_simple_object (
+	acpi_operand_object     *source_desc,
+	acpi_operand_object     *dest_desc);
+
+acpi_status
+acpi_ut_copy_iobject_to_iobject (
+	acpi_operand_object     *source_desc,
+	acpi_operand_object     **dest_desc,
+	acpi_walk_state         *walk_state);
+
 
 /*
  * Ut_create - Object creation
@@ -338,7 +353,7 @@
 	u32                     display,
 	u32                     component_id);
 
-void
+void ACPI_INTERNAL_VAR_XFACE
 acpi_ut_debug_print (
 	u32                     requested_debug_level,
 	u32                     line_number,
@@ -346,7 +361,7 @@
 	char                    *format,
 	...) ACPI_PRINTF_LIKE_FUNC;
 
-void
+void ACPI_INTERNAL_VAR_XFACE
 acpi_ut_debug_print_raw (
 	u32                     requested_debug_level,
 	u32                     line_number,
@@ -383,6 +398,7 @@
 /* Method name strings */
 
 #define METHOD_NAME__HID        "_HID"
+#define METHOD_NAME__CID        "_CID"
 #define METHOD_NAME__UID        "_UID"
 #define METHOD_NAME__ADR        "_ADR"
 #define METHOD_NAME__STA        "_STA"
@@ -404,6 +420,11 @@
 	acpi_device_id          *hid);
 
 acpi_status
+acpi_ut_execute_CID (
+	acpi_namespace_node     *device_node,
+	acpi_device_id          *cid);
+
+acpi_status
 acpi_ut_execute_STA (
 	acpi_namespace_node     *device_node,
 	u32                     *status_flags);
@@ -452,7 +473,7 @@
 	NATIVE_CHAR             *module_name,
 	u32                     line_number,
 	u32                     component_id,
-	acpi_object_type8       type);
+	acpi_object_type        type);
 
 void *
 acpi_ut_allocate_object_desc_dbg (
@@ -491,17 +512,17 @@
 acpi_status
 acpi_ut_get_simple_object_size (
 	acpi_operand_object     *obj,
-	u32                     *obj_length);
+	ACPI_SIZE               *obj_length);
 
 acpi_status
 acpi_ut_get_package_object_size (
 	acpi_operand_object     *obj,
-	u32                     *obj_length);
+	ACPI_SIZE               *obj_length);
 
 acpi_status
 acpi_ut_get_object_size(
 	acpi_operand_object     *obj,
-	u32                     *obj_length);
+	ACPI_SIZE               *obj_length);
 
 
 /*
@@ -522,6 +543,10 @@
 acpi_ut_create_generic_state (
 	void);
 
+ACPI_THREAD_STATE *
+acpi_ut_create_thread_state (
+	void);
+
 acpi_generic_state *
 acpi_ut_create_update_state (
 	acpi_operand_object     *object,
@@ -596,6 +621,14 @@
 acpi_ut_resolve_package_references (
 	acpi_operand_object     *obj_desc);
 
+u8 *
+acpi_ut_get_resource_end_tag (
+	acpi_operand_object     *obj_desc);
+
+u8
+acpi_ut_generate_checksum (
+	u8                      *buffer,
+	u32                     length);
 
 #ifdef ACPI_DEBUG
 void
@@ -623,31 +656,73 @@
 acpi_ut_delete_generic_cache (
 	u32                     list_id);
 
+acpi_status
+acpi_ut_validate_buffer (
+	acpi_buffer             *buffer);
+
+acpi_status
+acpi_ut_initialize_buffer (
+	acpi_buffer             *buffer,
+	ACPI_SIZE               required_length);
+
 
-/* Debug Memory allocation functions */
+/* Memory allocation functions */
 
 void *
 acpi_ut_allocate (
-	u32                     size,
+	ACPI_SIZE               size,
 	u32                     component,
 	NATIVE_CHAR             *module,
 	u32                     line);
 
 void *
 acpi_ut_callocate (
-	u32                     size,
+	ACPI_SIZE               size,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line);
+
+
+#ifdef ACPI_DBG_TRACK_ALLOCATIONS
+
+void *
+acpi_ut_allocate_and_track (
+	ACPI_SIZE               size,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line);
+
+void *
+acpi_ut_callocate_and_track (
+	ACPI_SIZE               size,
 	u32                     component,
 	NATIVE_CHAR             *module,
 	u32                     line);
 
 void
-acpi_ut_free (
+acpi_ut_free_and_track (
 	void                    *address,
 	u32                     component,
 	NATIVE_CHAR             *module,
 	u32                     line);
+acpi_status
+acpi_ut_track_allocation (
+	u32                     list_id,
+	acpi_debug_mem_block    *address,
+	ACPI_SIZE               size,
+	u8                      alloc_type,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line);
+
+acpi_status
+acpi_ut_remove_allocation (
+	u32                     list_id,
+	acpi_debug_mem_block    *address,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line);
 
-#ifdef ACPI_DBG_TRACK_ALLOCATIONS
 void
 acpi_ut_dump_allocation_info (
 	void);
diff -Nru a/drivers/acpi/include/amlcode.h b/drivers/acpi/include/amlcode.h
--- a/drivers/acpi/include/amlcode.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/amlcode.h	Fri Mar 15 17:51:03 2002
@@ -3,12 +3,12 @@
  * Name: amlcode.h - Definitions for AML, as included in "definition blocks"
  *                   Declarations and definitions contained herein are derived
  *                   directly from the ACPI specification.
- *       $Revision: 58 $
+ *       $Revision: 66 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -218,6 +218,9 @@
  * Resolved argument types for the AML Interpreter
  * Each field in the Arg_types u32 is 5 bits, allowing for a maximum of 6 arguments.
  * There can be up to 31 unique argument types (0 is end-of-arg-list indicator)
+ *
+ * Note: If and when 5 bits becomes insufficient, it would probably be best
+ * to convert to a 6-byte array of argument types, allowing 8 bits per argument.
  */
 
 /* "Standard" ACPI types are 1-15 (0x0F) */
@@ -247,6 +250,7 @@
 #define ARGI_FIXED_TARGET           0x1B     /* Target, no implicit conversion */
 #define ARGI_SIMPLE_TARGET          0x1C     /* Name, Local, Arg -- no implicit conversion */
 #define ARGI_BUFFERSTRING           0x1D
+#define ARGI_REF_OR_STRING          0x1E     /* Reference or String (Used by DEREFOF op only) */
 
 #define ARGI_INVALID_OPCODE         0xFFFFFFFF
 
@@ -369,7 +373,8 @@
 	REGION_SMBUS,
 	REGION_CMOS,
 	REGION_PCI_BAR,
-	REGION_FIXED_HW                 = 0x7F,
+	REGION_DATA_TABLE,              /* Internal use only */
+	REGION_FIXED_HW                 = 0x7F
 
 } AML_REGION_TYPES;
 
@@ -390,52 +395,76 @@
 #define MAX_MATCH_OPERATOR          5
 
 
-/* Field Access Types */
+/*
+ * Field_flags
+ *
+ * This byte is extracted from the AML and includes three separate
+ * pieces of information about the field:
+ * 1) The field access type
+ * 2) The field update rule
+ * 3) The lock rule for the field
+ *
+ * Bits 00 - 03 : Access_type (Any_acc, Byte_acc, etc.)
+ *      04      : Lock_rule (1 == Lock)
+ *      05 - 06 : Update_rule
+ */
+#define AML_FIELD_ACCESS_TYPE_MASK  0x0F
+#define AML_FIELD_LOCK_RULE_MASK    0x10
+#define AML_FIELD_UPDATE_RULE_MASK  0x60
 
-#define ACCESS_TYPE_MASK            0x0f
-#define ACCESS_TYPE_SHIFT           0
+
+/* 1) Field Access Types */
 
 typedef enum
 {
-	ACCESS_ANY_ACC                  = 0,
-	ACCESS_BYTE_ACC                 = 1,
-	ACCESS_WORD_ACC                 = 2,
-	ACCESS_DWORD_ACC                = 3,
-	ACCESS_QWORD_ACC                = 4,    /* ACPI 2.0 */
-	ACCESS_BLOCK_ACC                = 4,
-	ACCESS_SMBSEND_RECV_ACC         = 5,
-	ACCESS_SMBQUICK_ACC             = 6
+	AML_FIELD_ACCESS_ANY            = 0x00,
+	AML_FIELD_ACCESS_BYTE           = 0x01,
+	AML_FIELD_ACCESS_WORD           = 0x02,
+	AML_FIELD_ACCESS_DWORD          = 0x03,
+	AML_FIELD_ACCESS_QWORD          = 0x04,    /* ACPI 2.0 */
+	AML_FIELD_ACCESS_BUFFER         = 0x05     /* ACPI 2.0 */
 
 } AML_ACCESS_TYPE;
 
 
-/* Field Lock Rules */
-
-#define LOCK_RULE_MASK              0x10
-#define LOCK_RULE_SHIFT             4
+/* 2) Field Lock Rules */
 
 typedef enum
 {
-	GLOCK_NEVER_LOCK                = 0,
-	GLOCK_ALWAYS_LOCK               = 1
+	AML_FIELD_LOCK_NEVER            = 0x00,
+	AML_FIELD_LOCK_ALWAYS           = 0x10
 
 } AML_LOCK_RULE;
 
 
-/* Field Update Rules */
-
-#define UPDATE_RULE_MASK            0x060
-#define UPDATE_RULE_SHIFT           5
+/* 3) Field Update Rules */
 
 typedef enum
 {
-	UPDATE_PRESERVE                 = 0,
-	UPDATE_WRITE_AS_ONES            = 1,
-	UPDATE_WRITE_AS_ZEROS           = 2
+	AML_FIELD_UPDATE_PRESERVE       = 0x00,
+	AML_FIELD_UPDATE_WRITE_AS_ONES  = 0x20,
+	AML_FIELD_UPDATE_WRITE_AS_ZEROS = 0x40
 
 } AML_UPDATE_RULE;
 
 
+/*
+ * Field Access Attributes.
+ * This byte is extracted from the AML via the
+ * Access_as keyword
+ */
+typedef enum
+{
+	AML_FIELD_ATTRIB_SMB_QUICK      = 0x02,
+	AML_FIELD_ATTRIB_SMB_SEND_RCV   = 0x04,
+	AML_FIELD_ATTRIB_SMB_BYTE       = 0x06,
+	AML_FIELD_ATTRIB_SMB_WORD       = 0x08,
+	AML_FIELD_ATTRIB_SMB_BLOCK      = 0x0A,
+	AML_FIELD_ATTRIB_SMB_CALL       = 0x0E
+
+} AML_ACCESS_ATTRIBUTE;
+
+
 /* bit fields in Method_flags byte */
 
 #define METHOD_FLAGS_ARG_COUNT      0x07
@@ -445,15 +474,11 @@
 
 /* Array sizes.  Used for range checking also */
 
-#define NUM_REGION_TYPES            7
-#define NUM_ACCESS_TYPES            7
+#define NUM_ACCESS_TYPES            6
 #define NUM_UPDATE_RULES            3
 #define NUM_MATCH_OPS               7
 #define NUM_OPCODES                 256
 #define NUM_FIELD_NAMES             2
-
-
-#define USER_REGION_BEGIN           0x80
 
 
 #endif /* __AMLCODE_H__ */
diff -Nru a/drivers/acpi/include/platform/acenv.h b/drivers/acpi/include/platform/acenv.h
--- a/drivers/acpi/include/platform/acenv.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/include/platform/acenv.h	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acenv.h - Generation environment specific items
- *       $Revision: 77 $
+ *       $Revision: 85 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -105,18 +105,30 @@
 
 /*! [Begin] no source code translation */
 
-#ifdef _LINUX
+#if defined(_LINUX)
 #include "aclinux.h"
 
-#elif _AED_EFI
+#elif defined(_AED_EFI)
 #include "acefi.h"
 
-#elif WIN32
+#elif defined(MSDOS)
+#include "acdos16.h"
+
+#elif defined(WIN32)
 #include "acwin.h"
 
-#elif __FreeBSD__
+#elif defined(WIN64)
+#include "acwin64.h"
+
+#elif defined(__FreeBSD__)
 #include "acfreebsd.h"
 
+#elif defined(MODESTO)
+#include "acmodesto.h"
+
+#elif defined(NETWARE)
+#include "acnetware.h"
+
 #else
 
 /* All other environments */
@@ -135,7 +147,6 @@
 
 #endif
 
-
 /*! [End] no source code translation !*/
 
 /******************************************************************************
@@ -166,21 +177,21 @@
  * We will be linking to the standard Clib functions
  */
 
-#define STRSTR(s1,s2)   strstr((s1), (s2))
-#define STRUPR(s)       acpi_ut_strupr ((s))
-#define STRLEN(s)       (u32) strlen((s))
-#define STRCPY(d,s)     strcpy((d), (s))
-#define STRNCPY(d,s,n)  strncpy((d), (s), (NATIVE_INT)(n))
-#define STRNCMP(d,s,n)  strncmp((d), (s), (NATIVE_INT)(n))
-#define STRCMP(d,s)     strcmp((d), (s))
-#define STRCAT(d,s)     strcat((d), (s))
-#define STRNCAT(d,s,n)  strncat((d), (s), (NATIVE_INT)(n))
-#define STRTOUL(d,s,n)  strtoul((d), (s), (NATIVE_INT)(n))
-#define MEMCPY(d,s,n)   memcpy((d), (s), (NATIVE_INT)(n))
-#define MEMSET(d,s,n)   memset((d), (s), (NATIVE_INT)(n))
-#define TOUPPER         toupper
-#define TOLOWER         tolower
-#define IS_XDIGIT       isxdigit
+#define ACPI_STRSTR(s1,s2)      strstr((s1), (s2))
+#define ACPI_STRUPR(s)          acpi_ut_strupr ((s))
+#define ACPI_STRLEN(s)          (u32) strlen((s))
+#define ACPI_STRCPY(d,s)        strcpy((d), (s))
+#define ACPI_STRNCPY(d,s,n)     strncpy((d), (s), (NATIVE_INT)(n))
+#define ACPI_STRNCMP(d,s,n)     strncmp((d), (s), (NATIVE_INT)(n))
+#define ACPI_STRCMP(d,s)        strcmp((d), (s))
+#define ACPI_STRCAT(d,s)        strcat((d), (s))
+#define ACPI_STRNCAT(d,s,n)     strncat((d), (s), (NATIVE_INT)(n))
+#define ACPI_STRTOUL(d,s,n)     strtoul((d), (s), (NATIVE_INT)(n))
+#define ACPI_MEMCPY(d,s,n)      (void) memcpy((d), (s), (NATIVE_INT)(n))
+#define ACPI_MEMSET(d,s,n)      (void) memset((d), (s), (NATIVE_INT)(n))
+#define ACPI_TOUPPER            toupper
+#define ACPI_TOLOWER            tolower
+#define ACPI_IS_XDIGIT          isxdigit
 
 /******************************************************************************
  *
@@ -207,35 +218,35 @@
  * Storage alignment properties
  */
 
-#define  _AUPBND         (sizeof (NATIVE_INT) - 1)
-#define  _ADNBND         (sizeof (NATIVE_INT) - 1)
+#define  _AUPBND                (sizeof (NATIVE_INT) - 1)
+#define  _ADNBND                (sizeof (NATIVE_INT) - 1)
 
 /*
  * Variable argument list macro definitions
  */
 
-#define _bnd(X, bnd)    (((sizeof (X)) + (bnd)) & (~(bnd)))
-#define va_arg(ap, T)   (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
-#define va_end(ap)      (void) 0
-#define va_start(ap, A) (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
+#define _bnd(X, bnd)            (((sizeof (X)) + (bnd)) & (~(bnd)))
+#define va_arg(ap, T)           (*(T *)(((ap) += (_bnd (T, _AUPBND))) - (_bnd (T,_ADNBND))))
+#define va_end(ap)              (void) 0
+#define va_start(ap, A)         (void) ((ap) = (((char *) &(A)) + (_bnd (A,_AUPBND))))
 
 #endif /* va_arg */
 
 
-#define STRSTR(s1,s2)    acpi_ut_strstr ((s1), (s2))
-#define STRUPR(s)        acpi_ut_strupr ((s))
-#define STRLEN(s)        acpi_ut_strlen ((s))
-#define STRCPY(d,s)      acpi_ut_strcpy ((d), (s))
-#define STRNCPY(d,s,n)   acpi_ut_strncpy ((d), (s), (n))
-#define STRNCMP(d,s,n)   acpi_ut_strncmp ((d), (s), (n))
-#define STRCMP(d,s)      acpi_ut_strcmp ((d), (s))
-#define STRCAT(d,s)      acpi_ut_strcat ((d), (s))
-#define STRNCAT(d,s,n)   acpi_ut_strncat ((d), (s), (n))
-#define STRTOUL(d,s,n)   acpi_ut_strtoul ((d), (s),(n))
-#define MEMCPY(d,s,n)    acpi_ut_memcpy ((d), (s), (n))
-#define MEMSET(d,v,n)    acpi_ut_memset ((d), (v), (n))
-#define TOUPPER          acpi_ut_to_upper
-#define TOLOWER          acpi_ut_to_lower
+#define ACPI_STRSTR(s1,s2)      acpi_ut_strstr ((s1), (s2))
+#define ACPI_STRUPR(s)          acpi_ut_strupr ((s))
+#define ACPI_STRLEN(s)          acpi_ut_strlen ((s))
+#define ACPI_STRCPY(d,s)        acpi_ut_strcpy ((d), (s))
+#define ACPI_STRNCPY(d,s,n)     acpi_ut_strncpy ((d), (s), (n))
+#define ACPI_STRNCMP(d,s,n)     acpi_ut_strncmp ((d), (s), (n))
+#define ACPI_STRCMP(d,s)        acpi_ut_strcmp ((d), (s))
+#define ACPI_STRCAT(d,s)        acpi_ut_strcat ((d), (s))
+#define ACPI_STRNCAT(d,s,n)     acpi_ut_strncat ((d), (s), (n))
+#define ACPI_STRTOUL(d,s,n)     acpi_ut_strtoul ((d), (s),(n))
+#define ACPI_MEMCPY(d,s,n)      (void) acpi_ut_memcpy ((d), (s), (n))
+#define ACPI_MEMSET(d,v,n)      (void) acpi_ut_memset ((d), (v), (n))
+#define ACPI_TOUPPER            acpi_ut_to_upper
+#define ACPI_TOLOWER            acpi_ut_to_lower
 
 #endif /* ACPI_USE_SYSTEM_CLIBRARY */
 
@@ -256,13 +267,27 @@
  */
 
 /* Unrecognized compiler, use defaults */
+
 #ifndef ACPI_ASM_MACROS
 
+/*
+ * Calling conventions:
+ *
+ * ACPI_SYSTEM_XFACE        - Interfaces to host OS (handlers, threads)
+ * ACPI_EXTERNAL_XFACE      - External ACPI interfaces
+ * ACPI_INTERNAL_XFACE      - Internal ACPI interfaces
+ * ACPI_INTERNAL_VAR_XFACE  - Internal variable-parameter list interfaces
+ */
+#define ACPI_SYSTEM_XFACE
+#define ACPI_EXTERNAL_XFACE
+#define ACPI_INTERNAL_XFACE
+#define ACPI_INTERNAL_VAR_XFACE
+
 #define ACPI_ASM_MACROS
 #define causeinterrupt(level)
 #define BREAKPOINT3
-#define disable()
-#define enable()
+#define acpi_disable_irqs()
+#define acpi_enable_irqs()
 #define halt()
 #define ACPI_ACQUIRE_GLOBAL_LOCK(Glptr, acq)
 #define ACPI_RELEASE_GLOBAL_LOCK(Glptr, acq)
@@ -283,12 +308,8 @@
 
 /******************************************************************************
  *
- * Compiler-specific
+ * Compiler-specific information is contained in the compiler-specific
+ * headers.
  *
  *****************************************************************************/
-
-/* this has been moved to compiler-specific headers, which are included from the
-   platform header. */
-
-
 #endif /* __ACENV_H__ */
diff -Nru a/drivers/acpi/include/platform/acgcc.h b/drivers/acpi/include/platform/acgcc.h
--- a/drivers/acpi/include/platform/acgcc.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/platform/acgcc.h	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: acgcc.h - GCC specific defines, etc.
- *       $Revision: 14 $
+ *       $Revision: 19 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,14 +31,31 @@
 #define _IA64
 
 #define COMPILER_DEPENDENT_UINT64   unsigned long
+
+/*
+ * Calling conventions:
+ *
+ * ACPI_SYSTEM_XFACE        - Interfaces to host OS (handlers, threads)
+ * ACPI_EXTERNAL_XFACE      - External ACPI interfaces
+ * ACPI_INTERNAL_XFACE      - Internal ACPI interfaces
+ * ACPI_INTERNAL_VAR_XFACE  - Internal variable-parameter list interfaces
+ */
+#define ACPI_SYSTEM_XFACE
+#define ACPI_EXTERNAL_XFACE
+#define ACPI_INTERNAL_XFACE
+#define ACPI_INTERNAL_VAR_XFACE
+
 /* Single threaded */
+
 #define ACPI_APPLICATION
 
+/* Asm macros */
+
 #define ACPI_ASM_MACROS
 #define causeinterrupt(level)
 #define BREAKPOINT3
-#define disable() __cli()
-#define enable()  __sti()
+#define acpi_disable_irqs() __cli()
+#define acpi_enable_irqs()  __sti()
 
 /*! [Begin] no source code translation */
 
@@ -95,11 +112,27 @@
 #else /* DO IA32 */
 
 #define COMPILER_DEPENDENT_UINT64   unsigned long long
+
+/*
+ * Calling conventions:
+ *
+ * ACPI_SYSTEM_XFACE        - Interfaces to host OS (handlers, threads)
+ * ACPI_EXTERNAL_XFACE      - External ACPI interfaces
+ * ACPI_INTERNAL_XFACE      - Internal ACPI interfaces
+ * ACPI_INTERNAL_VAR_XFACE  - Internal variable-parameter list interfaces
+ */
+#define ACPI_SYSTEM_XFACE
+#define ACPI_EXTERNAL_XFACE
+#define ACPI_INTERNAL_XFACE
+#define ACPI_INTERNAL_VAR_XFACE
+
+/* Asm macros */
+
 #define ACPI_ASM_MACROS
 #define causeinterrupt(level)
 #define BREAKPOINT3
-#define disable() __cli()
-#define enable()  __sti()
+#define acpi_disable_irqs() __cli()
+#define acpi_enable_irqs()  __sti()
 #define halt()    __asm__ __volatile__ ("sti; hlt":::"memory")
 
 /*! [Begin] no source code translation
@@ -152,9 +185,9 @@
 
 #define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
 	asm("shrl   $1,%2;"             \
-	    "rcrl   $1,%3;"             \
-	    :"=r"(n_hi), "=r"(n_lo)     \
-	    :"0"(n_hi), "1"(n_lo))
+		"rcrl   $1,%3;"             \
+		:"=r"(n_hi), "=r"(n_lo)     \
+		:"0"(n_hi), "1"(n_lo))
 
 /*! [End] no source code translation !*/
 
diff -Nru a/drivers/acpi/include/platform/aclinux.h b/drivers/acpi/include/platform/aclinux.h
--- a/drivers/acpi/include/platform/aclinux.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/include/platform/aclinux.h	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Name: aclinux.h - OS specific defines, etc.
- *       $Revision: 14 $
+ *       $Revision: 15 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
diff -Nru a/drivers/acpi/namespace/Makefile b/drivers/acpi/namespace/Makefile
--- a/drivers/acpi/namespace/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/namespace/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/namespace/nsaccess.c b/drivers/acpi/namespace/nsaccess.c
--- a/drivers/acpi/namespace/nsaccess.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/acpi/namespace/nsaccess.c	Fri Mar 15 17:51:04 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: nsaccess - Top-level functions for accessing ACPI namespace
- *              $Revision: 135 $
+ *              $Revision: 152 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsaccess")
+	 ACPI_MODULE_NAME    ("nsaccess")
 
 
 /*******************************************************************************
@@ -52,16 +52,19 @@
 acpi_status
 acpi_ns_root_initialize (void)
 {
-	acpi_status             status = AE_OK;
-	const predefined_names  *init_val = NULL;
-	acpi_namespace_node     *new_node;
-	acpi_operand_object     *obj_desc;
+	acpi_status                 status;
+	const acpi_predefined_names *init_val = NULL;
+	acpi_namespace_node         *new_node;
+	acpi_operand_object         *obj_desc;
 
 
-	FUNCTION_TRACE ("Ns_root_initialize");
+	ACPI_FUNCTION_TRACE ("Ns_root_initialize");
 
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/*
 	 * The global root ptr is initially NULL, so a non-NULL value indicates
@@ -72,22 +75,20 @@
 		goto unlock_and_exit;
 	}
 
-
 	/*
 	 * Tell the rest of the subsystem that the root is initialized
 	 * (This is OK because the namespace is locked)
 	 */
 	acpi_gbl_root_node = &acpi_gbl_root_node_struct;
 
-
 	/* Enter the pre-defined names in the name table */
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Entering predefined entries into namespace\n"));
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+		"Entering predefined entries into namespace\n"));
 
 	for (init_val = acpi_gbl_pre_defined_names; init_val->name; init_val++) {
 		status = acpi_ns_lookup (NULL, init_val->name, init_val->type,
-				 IMODE_LOAD_PASS2, NS_NO_UPSEARCH,
-				 NULL, &new_node);
+				  ACPI_IMODE_LOAD_PASS2, ACPI_NS_NO_UPSEARCH, NULL, &new_node);
 
 		if (ACPI_FAILURE (status) || (!new_node)) /* Must be on same line for code converter */ {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
@@ -116,13 +117,11 @@
 			 * internal representation. Only types actually
 			 * used for initial values are implemented here.
 			 */
-
 			switch (init_val->type) {
-
 			case ACPI_TYPE_INTEGER:
 
 				obj_desc->integer.value =
-						(acpi_integer) STRTOUL (init_val->val, NULL, 10);
+						(acpi_integer) ACPI_STRTOUL (init_val->val, NULL, 10);
 				break;
 
 
@@ -131,7 +130,7 @@
 				/*
 				 * Build an object around the static string
 				 */
-				obj_desc->string.length = STRLEN (init_val->val);
+				obj_desc->string.length = ACPI_STRLEN (init_val->val);
 				obj_desc->string.pointer = init_val->val;
 				obj_desc->common.flags |= AOPOBJ_STATIC_POINTER;
 				break;
@@ -140,16 +139,15 @@
 			case ACPI_TYPE_MUTEX:
 
 				obj_desc->mutex.sync_level =
-						 (u16) STRTOUL (init_val->val, NULL, 10);
+						 (u16) ACPI_STRTOUL (init_val->val, NULL, 10);
 
-				if (STRCMP (init_val->name, "_GL_") == 0) {
+				if (ACPI_STRCMP (init_val->name, "_GL_") == 0) {
 					/*
 					 * Create a counting semaphore for the
 					 * global lock
 					 */
 					status = acpi_os_create_semaphore (ACPI_NO_UNIT_LIMIT,
 							 1, &obj_desc->mutex.semaphore);
-
 					if (ACPI_FAILURE (status)) {
 						goto unlock_and_exit;
 					}
@@ -160,13 +158,11 @@
 					 */
 					acpi_gbl_global_lock_semaphore = obj_desc->mutex.semaphore;
 				}
-
 				else {
 					/* Create a mutex */
 
 					status = acpi_os_create_semaphore (1, 1,
 							   &obj_desc->mutex.semaphore);
-
 					if (ACPI_FAILURE (status)) {
 						goto unlock_and_exit;
 					}
@@ -175,7 +171,7 @@
 
 
 			default:
-				REPORT_ERROR (("Unsupported initial type value %X\n",
+				ACPI_REPORT_ERROR (("Unsupported initial type value %X\n",
 					init_val->type));
 				acpi_ut_remove_reference (obj_desc);
 				obj_desc = NULL;
@@ -194,7 +190,7 @@
 
 
 unlock_and_exit:
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
 
@@ -226,8 +222,8 @@
 acpi_ns_lookup (
 	acpi_generic_state      *scope_info,
 	NATIVE_CHAR             *pathname,
-	acpi_object_type8       type,
-	operating_mode          interpreter_mode,
+	acpi_object_type        type,
+	acpi_interpreter_mode   interpreter_mode,
 	u32                     flags,
 	acpi_walk_state         *walk_state,
 	acpi_namespace_node     **return_node)
@@ -235,33 +231,26 @@
 	acpi_status             status;
 	acpi_namespace_node     *prefix_node;
 	acpi_namespace_node     *current_node = NULL;
-	acpi_namespace_node     *scope_to_push = NULL;
 	acpi_namespace_node     *this_node = NULL;
 	u32                     num_segments;
 	acpi_name               simple_name;
-	u8                      null_name_path = FALSE;
-	acpi_object_type8       type_to_check_for;
-	acpi_object_type8       this_search_type;
-	u32                     local_flags = flags & ~NS_ERROR_IF_FOUND;
+	acpi_object_type        type_to_check_for;
+	acpi_object_type        this_search_type;
+	u32                     local_flags = flags & ~ACPI_NS_ERROR_IF_FOUND;
 
-	DEBUG_EXEC              (u32 i;)
 
-
-	FUNCTION_TRACE ("Ns_lookup");
+	ACPI_FUNCTION_TRACE ("Ns_lookup");
 
 
 	if (!return_node) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	acpi_gbl_ns_lookup_count++;
-
-	*return_node = ENTRY_NOT_FOUND;
-
+	*return_node = ACPI_ENTRY_NOT_FOUND;
 
 	if (!acpi_gbl_root_node) {
-		return (AE_NO_NAMESPACE);
+		return_ACPI_STATUS (AE_NO_NAMESPACE);
 	}
 
 	/*
@@ -270,7 +259,8 @@
 	 */
 	if ((!scope_info) ||
 		(!scope_info->scope.node)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Null scope prefix, using root node (%p)\n",
+		ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
+			"Null scope prefix, using root node (%p)\n",
 			acpi_gbl_root_node));
 
 		prefix_node = acpi_gbl_root_node;
@@ -279,7 +269,6 @@
 		prefix_node = scope_info->scope.node;
 	}
 
-
 	/*
 	 * This check is explicitly split to relax the Type_to_check_for
 	 * conditions for Bank_field_defn. Originally, both Bank_field_defn and
@@ -292,210 +281,200 @@
 
 		type_to_check_for = ACPI_TYPE_REGION;
 	}
-
 	else if (INTERNAL_TYPE_BANK_FIELD_DEFN == type) {
 		/* Bank_field_defn defines data fields in a Field Object */
 
 		type_to_check_for = ACPI_TYPE_ANY;
 	}
-
 	else {
 		type_to_check_for = type;
 	}
 
-
-	/* TBD: [Restructure] - Move the pathname stuff into a new procedure */
-
-	/* Examine the name pointer */
-
+	/*
+	 * Begin examination of the actual pathname
+	 */
 	if (!pathname) {
-		/*  8-12-98 ASL Grammar Update supports null Name_path  */
+		/* A Null Name_path is allowed and refers to the root */
 
-		null_name_path = TRUE;
 		num_segments = 0;
-		this_node = acpi_gbl_root_node;
+		this_node    = acpi_gbl_root_node;
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
-			"Null Pathname (Zero segments),  Flags=%x\n", flags));
+			"Null Pathname (Zero segments), Flags=%x\n", flags));
 	}
-
 	else {
 		/*
-		 * Valid name pointer (Internal name format)
+		 * Name pointer is valid (and must be in internal name format)
 		 *
-		 * Check for prefixes.  As represented in the AML stream, a
-		 * Pathname consists of an optional scope prefix followed by
-		 * a segment part.
+		 * Check for scope prefixes:
 		 *
-		 * If present, the scope prefix is either a Root_prefix (in
-		 * which case the name is fully qualified), or zero or more
-		 * Parent_prefixes (in which case the name's scope is relative
-		 * to the current scope).
+		 * As represented in the AML stream, a namepath consists of an
+		 * optional scope prefix followed by a name segment part.
 		 *
-		 * The segment part consists of either:
-		 *  - A single 4-byte name segment, or
-		 *  - A Dual_name_prefix followed by two 4-byte name segments, or
-		 *  - A Multi_name_prefix_op, followed by a byte indicating the
-		 *    number of segments and the segments themselves.
+		 * If present, the scope prefix is either a Root Prefix (in
+		 * which case the name is fully qualified), or one or more
+		 * Parent Prefixes (in which case the name's scope is relative
+		 * to the current scope).
 		 */
 		if (*pathname == AML_ROOT_PREFIX) {
-			/* Pathname is fully qualified, look in root name table */
+			/* Pathname is fully qualified, start from the root */
 
-			current_node = acpi_gbl_root_node;
+			this_node = acpi_gbl_root_node;
 
-			/* point to segment part */
+			/* Point to name segment part */
 
 			pathname++;
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Searching from root [%p]\n",
-				current_node));
-
-			/* Direct reference to root, "\" */
-
-			if (!(*pathname)) {
-				this_node = acpi_gbl_root_node;
-				goto check_for_new_scope_and_exit;
-			}
+				this_node));
 		}
-
 		else {
 			/* Pathname is relative to current scope, start there */
 
-			current_node = prefix_node;
-
-			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Searching relative to pfx scope [%p]\n",
+			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
+				"Searching relative to pfx scope [%p]\n",
 				prefix_node));
 
 			/*
-			 * Handle up-prefix (carat).  More than one prefix
-			 * is supported
+			 * Handle multiple Parent Prefixes (carat) by just getting
+			 * the parent node for each prefix instance.
 			 */
+			this_node = prefix_node;
 			while (*pathname == AML_PARENT_PREFIX) {
-				/* Point to segment part or next Parent_prefix */
-
+				/*
+				 * Point past this prefix to the name segment
+				 * part or the next Parent Prefix
+				 */
 				pathname++;
 
-				/*  Backup to the parent's scope  */
+				/* Backup to the parent node */
 
-				this_node = acpi_ns_get_parent_object (current_node);
+				this_node = acpi_ns_get_parent_node (this_node);
 				if (!this_node) {
 					/* Current scope has no parent scope */
 
-					REPORT_ERROR (
-						("Too many parent prefixes (^) - reached root\n"));
+					ACPI_REPORT_ERROR (
+						("ACPI path has too many parent prefixes (^) - reached beyond root node\n"));
 					return_ACPI_STATUS (AE_NOT_FOUND);
 				}
-
-				current_node = this_node;
 			}
 		}
 
-
 		/*
-		 * Examine the name prefix opcode, if any,
-		 * to determine the number of segments
+		 * Determine the number of ACPI name segments in this pathname.
+		 *
+		 * The segment part consists of either:
+		 *  - A Null name segment (0)
+		 *  - A Dual_name_prefix followed by two 4-byte name segments
+		 *  - A Multi_name_prefix followed by a byte indicating the
+		 *      number of segments and the segments themselves.
+		 *  - A single 4-byte name segment
+		 *
+		 * Examine the name prefix opcode, if any, to determine the number of
+		 * segments.
 		 */
-		if (*pathname == AML_DUAL_NAME_PREFIX) {
-			num_segments = 2;
+		switch (*pathname) {
+		case 0:
+			/*
+			 * Null name after a root or parent prefixes. We already
+			 * have the correct target node and there are no name segments.
+			 */
+			num_segments = 0;
 
-			/* point to first segment */
+			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
+				"Prefix-only Pathname (Zero name segments), Flags=%x\n", flags));
+			break;
+
+		case AML_DUAL_NAME_PREFIX:
 
+			/* Two segments, point to first name segment */
+
+			num_segments = 2;
 			pathname++;
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
 				"Dual Pathname (2 segments, Flags=%X)\n", flags));
-		}
+			break;
 
-		else if (*pathname == AML_MULTI_NAME_PREFIX_OP) {
-			num_segments = (u32)* (u8 *) ++pathname;
+		case AML_MULTI_NAME_PREFIX_OP:
 
-			/* point to first segment */
+			/* Extract segment count, point to first name segment */
 
 			pathname++;
+			num_segments = (u32) (u8) *pathname;
+			pathname++;
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
 				"Multi Pathname (%d Segments, Flags=%X) \n",
 				num_segments, flags));
-		}
+			break;
 
-		else {
+		default:
 			/*
-			 * No Dual or Multi prefix, hence there is only one
-			 * segment and Pathname is already pointing to it.
+			 * Not a Null name, no Dual or Multi prefix, hence there is
+			 * only one name segment and Pathname is already pointing to it.
 			 */
 			num_segments = 1;
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
 				"Simple Pathname (1 segment, Flags=%X)\n", flags));
+			break;
 		}
 
-#ifdef ACPI_DEBUG
-
-		/* TBD: [Restructure] Make this a procedure */
-
-		/* Debug only: print the entire name that we are about to lookup */
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "["));
-
-		for (i = 0; i < num_segments; i++) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_NAMES, "%4.4s/", (char*)&pathname[i * 4]));
-		}
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_NAMES, "]\n"));
-#endif
+		ACPI_DEBUG_EXEC (acpi_ns_print_pathname (num_segments, pathname));
 	}
 
-
 	/*
-	 * Search namespace for each segment of the name.
-	 * Loop through and verify/add each name segment.
+	 * Search namespace for each segment of the name.  Loop through and
+	 * verify/add each name segment.
 	 */
-	while (num_segments-- && current_node) {
+	current_node = this_node;
+	while (num_segments && current_node) {
 		/*
 		 * Search for the current name segment under the current
-		 * named object.  The Type is significant only at the last (topmost)
-		 * level.  (We don't care about the types along the path, only
+		 * named object.  The Type is significant only at the last name
+		 * segment.  (We don't care about the types along the path, only
 		 * the type of the final target object.)
 		 */
 		this_search_type = ACPI_TYPE_ANY;
+		num_segments--;
 		if (!num_segments) {
 			this_search_type = type;
 			local_flags = flags;
 		}
 
-		/* Pluck one ACPI name from the front of the pathname */
+		/* Extract one ACPI name from the front of the pathname */
 
-		MOVE_UNALIGNED32_TO_32 (&simple_name, pathname);
+		ACPI_MOVE_UNALIGNED32_TO_32 (&simple_name, pathname);
 
 		/* Try to find the ACPI name */
 
-		status = acpi_ns_search_and_enter (simple_name, walk_state,
-				   current_node, interpreter_mode,
-				   this_search_type, local_flags,
-				   &this_node);
-
+		status = acpi_ns_search_and_enter (simple_name, walk_state, current_node,
+				  interpreter_mode, this_search_type, local_flags, &this_node);
 		if (ACPI_FAILURE (status)) {
 			if (status == AE_NOT_FOUND) {
-				/* Name not found in ACPI namespace  */
+				/* Name not found in ACPI namespace */
 
 				ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
-					"Name [%4.4s] not found in scope %p\n",
-					(char*)&simple_name, current_node));
+					"Name [%4.4s] not found in scope [%4.4s] %p\n",
+					(char *) &simple_name, (char *) &current_node->name, current_node));
 			}
 
 			return_ACPI_STATUS (status);
 		}
 
-
 		/*
+		 * Sanity typecheck of the target object:
+		 *
 		 * If 1) This is the last segment (Num_segments == 0)
-		 *    2) and looking for a specific type
+		 *    2) And we are looking for a specific type
 		 *       (Not checking for TYPE_ANY)
 		 *    3) Which is not an alias
-		 *    4) which is not a local type (TYPE_DEF_ANY)
-		 *    5) which is not a local type (TYPE_SCOPE)
-		 *    6) which is not a local type (TYPE_INDEX_FIELD_DEFN)
-		 *    7) and type of object is known (not TYPE_ANY)
-		 *    8) and object does not match request
+		 *    4) Which is not a local type (TYPE_DEF_ANY)
+		 *    5) Which is not a local type (TYPE_SCOPE)
+		 *    6) Which is not a local type (TYPE_INDEX_FIELD_DEFN)
+		 *    7) And the type of target object is known (not TYPE_ANY)
+		 *    8) And target object does not match what we are looking for
 		 *
 		 * Then we have a type mismatch.  Just warn and ignore it.
 		 */
@@ -509,9 +488,9 @@
 			(this_node->type    != type_to_check_for)) {
 			/* Complain about a type mismatch */
 
-			REPORT_WARNING (
+			ACPI_REPORT_WARNING (
 				("Ns_lookup: %4.4s, type %X, checking for type %X\n",
-				(char*)&simple_name, this_node->type, type_to_check_for));
+				(char *) &simple_name, this_node->type, type_to_check_for));
 		}
 
 		/*
@@ -519,57 +498,32 @@
 		 * specific type, but the type of found object is known, use that type
 		 * to see if it opens a scope.
 		 */
-		if ((0 == num_segments) && (ACPI_TYPE_ANY == type)) {
+		if ((num_segments == 0) && (type == ACPI_TYPE_ANY)) {
 			type = this_node->type;
 		}
 
-		if ((num_segments || acpi_ns_opens_scope (type)) &&
-			(this_node->child == NULL)) {
-			/*
-			 * More segments or the type implies enclosed scope,
-			 * and the next scope has not been allocated.
-			 */
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Load mode=%X  This_node=%p\n",
-				interpreter_mode, this_node));
-		}
-
-		current_node = this_node;
-
-		/* point to next name segment */
+		/* Point to next name segment and make this node current */
 
 		pathname += ACPI_NAME_SIZE;
+		current_node = this_node;
 	}
 
-
 	/*
 	 * Always check if we need to open a new scope
 	 */
-check_for_new_scope_and_exit:
-
-	if (!(flags & NS_DONT_OPEN_SCOPE) && (walk_state)) {
+	if (!(flags & ACPI_NS_DONT_OPEN_SCOPE) && (walk_state)) {
 		/*
-		 * If entry is a type which opens a scope,
-		 * push the new scope on the scope stack.
+		 * If entry is a type which opens a scope, push the new scope on the
+		 * scope stack.
 		 */
 		if (acpi_ns_opens_scope (type_to_check_for)) {
-			/*  8-12-98 ASL Grammar Update supports null Name_path  */
-
-			if (null_name_path) {
-				/* TBD: [Investigate] - is this the correct thing to do? */
-
-				scope_to_push = NULL;
-			}
-			else {
-				scope_to_push = this_node;
-			}
-
-			status = acpi_ds_scope_stack_push (scope_to_push, type,
-					   walk_state);
+			status = acpi_ds_scope_stack_push (this_node, type, walk_state);
 			if (ACPI_FAILURE (status)) {
 				return_ACPI_STATUS (status);
 			}
 
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Set global scope to %p\n", scope_to_push));
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+				"Setting global scope to %p\n", this_node));
 		}
 	}
 
diff -Nru a/drivers/acpi/namespace/nsalloc.c b/drivers/acpi/namespace/nsalloc.c
--- a/drivers/acpi/namespace/nsalloc.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/namespace/nsalloc.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: nsalloc - Namespace allocation and deletion utilities
- *              $Revision: 60 $
+ *              $Revision: 70 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsalloc")
+	 ACPI_MODULE_NAME    ("nsalloc")
 
 
 /*******************************************************************************
@@ -52,7 +52,7 @@
 	acpi_namespace_node     *node;
 
 
-	FUNCTION_TRACE ("Ns_create_node");
+	ACPI_FUNCTION_TRACE ("Ns_create_node");
 
 
 	node = ACPI_MEM_CALLOCATE (sizeof (acpi_namespace_node));
@@ -62,9 +62,9 @@
 
 	ACPI_MEM_TRACKING (acpi_gbl_memory_lists[ACPI_MEM_LIST_NSNODE].total_allocated++);
 
-	node->data_type      = ACPI_DESC_TYPE_NAMED;
 	node->name           = name;
 	node->reference_count = 1;
+	ACPI_SET_DESCRIPTOR_TYPE (node, ACPI_DESC_TYPE_NAMED);
 
 	return_PTR (node);
 }
@@ -91,10 +91,10 @@
 	acpi_namespace_node     *next_node;
 
 
-	FUNCTION_TRACE_PTR ("Ns_delete_node", node);
+	ACPI_FUNCTION_TRACE_PTR ("Ns_delete_node", node);
 
 
-	parent_node = acpi_ns_get_parent_object (node);
+	parent_node = acpi_ns_get_parent_node (node);
 
 	prev_node = NULL;
 	next_node = parent_node->child;
@@ -118,12 +118,9 @@
 	ACPI_MEM_TRACKING (acpi_gbl_memory_lists[ACPI_MEM_LIST_NSNODE].total_freed++);
 
 	/*
-	 * Detach an object if there is one
+	 * Detach an object if there is one then delete the node
 	 */
-	if (node->object) {
-		acpi_ns_detach_object (node);
-	}
-
+	acpi_ns_detach_object (node);
 	ACPI_MEM_FREE (node);
 	return_VOID;
 }
@@ -140,7 +137,11 @@
  *
  * RETURN:      None
  *
- * DESCRIPTION: Initialize a new entry within a namespace table.
+ * DESCRIPTION: Initialize a new namespace node and install it amongst
+ *              its peers.
+ *
+ *              Note: Current namespace lookup is linear search, so the nodes
+ *              are not linked in any particular order.
  *
  ******************************************************************************/
 
@@ -149,13 +150,13 @@
 	acpi_walk_state         *walk_state,
 	acpi_namespace_node     *parent_node,   /* Parent */
 	acpi_namespace_node     *node,          /* New Child*/
-	acpi_object_type8       type)
+	acpi_object_type        type)
 {
 	u16                     owner_id = TABLE_ID_DSDT;
 	acpi_namespace_node     *child_node;
 
 
-	FUNCTION_TRACE ("Ns_install_node");
+	ACPI_FUNCTION_TRACE ("Ns_install_node");
 
 
 	/*
@@ -167,16 +168,12 @@
 		owner_id = walk_state->owner_id;
 	}
 
-
-	/* link the new entry into the parent and existing children */
-
-	/* TBD: Could be first, last, or alphabetic */
+	/* Link the new entry into the parent and existing children */
 
 	child_node = parent_node->child;
 	if (!child_node) {
 		parent_node->child = node;
 	}
-
 	else {
 		while (!(child_node->flags & ANOBJ_END_OF_PEER_LIST)) {
 			child_node = child_node->peer;
@@ -210,7 +207,7 @@
 		 * real definition is found later.
 		 */
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "[%4.4s] is a forward reference\n",
-			(char*)&node->name));
+			(char *) &node->name));
 	}
 
 	/*
@@ -235,13 +232,13 @@
 	}
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "%4.4s added to %p at %p\n",
-		(char*)&node->name, parent_node, node));
+		(char *) &node->name, parent_node, node));
 
 	/*
 	 * Increment the reference count(s) of all parents up to
 	 * the root!
 	 */
-	while ((node = acpi_ns_get_parent_object (node)) != NULL) {
+	while ((node = acpi_ns_get_parent_node (node)) != NULL) {
 		node->reference_count++;
 	}
 
@@ -257,8 +254,8 @@
  *
  * RETURN:      None.
  *
- * DESCRIPTION: Delete all children of the parent object. Deletes a
- *              "scope".
+ * DESCRIPTION: Delete all children of the parent object. In other words,
+ *              deletes a "scope".
  *
  ******************************************************************************/
 
@@ -271,7 +268,7 @@
 	u8                      flags;
 
 
-	FUNCTION_TRACE_PTR ("Ns_delete_children", parent_node);
+	ACPI_FUNCTION_TRACE_PTR ("Ns_delete_children", parent_node);
 
 
 	if (!parent_node) {
@@ -338,7 +335,7 @@
  * RETURN:      None.
  *
  * DESCRIPTION: Delete a subtree of the namespace.  This includes all objects
- *              stored within the subtree.  Scope tables are deleted also
+ *              stored within the subtree.
  *
  ******************************************************************************/
 
@@ -350,7 +347,7 @@
 	u32                     level = 1;
 
 
-	FUNCTION_TRACE ("Ns_delete_namespace_subtree");
+	ACPI_FUNCTION_TRACE ("Ns_delete_namespace_subtree");
 
 
 	if (!parent_node) {
@@ -383,7 +380,6 @@
 				child_node    = 0;
 			}
 		}
-
 		else {
 			/*
 			 * No more children of this parent node.
@@ -403,7 +399,7 @@
 
 			/* Move up the tree to the grandparent */
 
-			parent_node = acpi_ns_get_parent_object (parent_node);
+			parent_node = acpi_ns_get_parent_node (parent_node);
 		}
 	}
 
@@ -430,34 +426,37 @@
 acpi_ns_remove_reference (
 	acpi_namespace_node     *node)
 {
-	acpi_namespace_node     *next_node;
+	acpi_namespace_node     *parent_node;
+	acpi_namespace_node     *this_node;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
 	 * Decrement the reference count(s) of this node and all
 	 * nodes up to the root,  Delete anything with zero remaining references.
 	 */
-	next_node = node;
-	while (next_node) {
-		/* Decrement the reference count on this node*/
+	this_node = node;
+	while (this_node) {
+		/* Prepare to move up to parent */
 
-		next_node->reference_count--;
+		parent_node = acpi_ns_get_parent_node (this_node);
+
+		/* Decrement the reference count on this node */
+
+		this_node->reference_count--;
 
 		/* Delete the node if no more references */
 
-		if (!next_node->reference_count) {
+		if (!this_node->reference_count) {
 			/* Delete all children and delete the node */
 
-			acpi_ns_delete_children (next_node);
-			acpi_ns_delete_node (next_node);
+			acpi_ns_delete_children (this_node);
+			acpi_ns_delete_node (this_node);
 		}
 
-		/* Move up to parent */
-
-		next_node = acpi_ns_get_parent_object (next_node);
+		this_node = parent_node;
 	}
 }
 
@@ -481,60 +480,66 @@
 	u16                     owner_id)
 {
 	acpi_namespace_node     *child_node;
+	acpi_namespace_node     *deletion_node;
 	u32                     level;
 	acpi_namespace_node     *parent_node;
 
 
-	FUNCTION_TRACE ("Ns_delete_namespace_by_owner");
+	ACPI_FUNCTION_TRACE_U32 ("Ns_delete_namespace_by_owner", owner_id);
 
 
-	parent_node = acpi_gbl_root_node;
-	child_node  = 0;
-	level       = 1;
+	parent_node   = acpi_gbl_root_node;
+	child_node    = NULL;
+	deletion_node = NULL;
+	level         = 1;
 
 	/*
 	 * Traverse the tree of nodes until we bubble back up
 	 * to where we started.
 	 */
 	while (level > 0) {
-		/* Get the next node in this scope (NULL if none) */
+		/*
+		 * Get the next child of this parent node. When Child_node is NULL,
+		 * the first child of the parent is returned
+		 */
+		child_node = acpi_ns_get_next_node (ACPI_TYPE_ANY, parent_node, child_node);
+
+		if (deletion_node) {
+			acpi_ns_remove_reference (deletion_node);
+			deletion_node = NULL;
+		}
 
-		child_node = acpi_ns_get_next_node (ACPI_TYPE_ANY, parent_node,
-				 child_node);
 		if (child_node) {
 			if (child_node->owner_id == owner_id) {
-				/* Found a child node - detach any attached object */
+				/* Found a matching child node - detach any attached object */
 
 				acpi_ns_detach_object (child_node);
 			}
 
 			/* Check if this node has any children */
 
-			if (acpi_ns_get_next_node (ACPI_TYPE_ANY, child_node, 0)) {
+			if (acpi_ns_get_next_node (ACPI_TYPE_ANY, child_node, NULL)) {
 				/*
 				 * There is at least one child of this node,
 				 * visit the node
 				 */
 				level++;
 				parent_node   = child_node;
-				child_node    = 0;
+				child_node    = NULL;
 			}
-
 			else if (child_node->owner_id == owner_id) {
-				acpi_ns_remove_reference (child_node);
+				deletion_node = child_node;
 			}
 		}
-
 		else {
 			/*
 			 * No more children of this parent node.
 			 * Move up to the grandparent.
 			 */
 			level--;
-
 			if (level != 0) {
 				if (parent_node->owner_id == owner_id) {
-					acpi_ns_remove_reference (parent_node);
+					deletion_node = parent_node;
 				}
 			}
 
@@ -544,7 +549,7 @@
 
 			/* Move up the tree to the grandparent */
 
-			parent_node = acpi_ns_get_parent_object (parent_node);
+			parent_node = acpi_ns_get_parent_node (parent_node);
 		}
 	}
 
diff -Nru a/drivers/acpi/namespace/nsdump.c b/drivers/acpi/namespace/nsdump.c
--- a/drivers/acpi/namespace/nsdump.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/namespace/nsdump.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: nsdump - table dumping routines for debug
- *              $Revision: 105 $
+ *              $Revision: 127 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,11 +32,52 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsdump")
-
+	 ACPI_MODULE_NAME    ("nsdump")
 
 #if defined(ACPI_DEBUG) || defined(ENABLE_DEBUGGER)
 
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ns_print_pathname
+ *
+ * PARAMETERS:  Num_segment         - Number of ACPI name segments
+ *              Pathname            - The compressed (internal) path
+ *
+ * DESCRIPTION: Print an object's full namespace pathname
+ *
+ ******************************************************************************/
+
+void
+acpi_ns_print_pathname (
+	u32                     num_segments,
+	char                    *pathname)
+{
+	ACPI_FUNCTION_NAME ("Acpi_ns_print_pathname");
+
+
+	if (!(acpi_dbg_level & ACPI_LV_NAMES) || !(acpi_dbg_layer & ACPI_NAMESPACE)) {
+		return;
+	}
+
+		/* Print the entire name */
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "["));
+
+	while (num_segments) {
+		acpi_os_printf ("%4.4s", pathname);
+		pathname += ACPI_NAME_SIZE;
+
+		num_segments--;
+		if (num_segments) {
+			acpi_os_printf (".");
+		}
+	}
+
+	acpi_os_printf ("]\n");
+}
+
+
 /*******************************************************************************
  *
  * FUNCTION:    Acpi_ns_dump_pathname
@@ -58,11 +99,11 @@
 	u32                     level,
 	u32                     component)
 {
-	NATIVE_CHAR             *buffer;
-	u32                     length;
+	acpi_buffer             buffer;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ns_dump_pathname");
+	ACPI_FUNCTION_TRACE ("Ns_dump_pathname");
 
 
 	/* Do this only if the requested debug level and component are enabled */
@@ -71,21 +112,17 @@
 		return_ACPI_STATUS (AE_OK);
 	}
 
-	buffer = ACPI_MEM_ALLOCATE (PATHNAME_MAX);
-	if (!buffer) {
-		return_ACPI_STATUS (AE_NO_MEMORY);
-	}
-
 	/* Convert handle to a full pathname and print it (with supplied message) */
 
-	length = PATHNAME_MAX;
-	if (ACPI_SUCCESS (acpi_ns_handle_to_pathname (handle, &length, buffer))) {
-		acpi_os_printf ("%s %s (%p)\n", msg, buffer, handle);
-	}
+	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
 
-	ACPI_MEM_FREE (buffer);
+	status = acpi_ns_handle_to_pathname (handle, &buffer);
+	if (ACPI_SUCCESS (status)) {
+		acpi_os_printf ("%s %s (Node %p)\n", msg, buffer.pointer, handle);
+		ACPI_MEM_FREE (buffer.pointer);
+	}
 
-	return_ACPI_STATUS (AE_OK);
+	return_ACPI_STATUS (status);
 }
 
 
@@ -112,16 +149,17 @@
 	acpi_walk_info          *info = (acpi_walk_info *) context;
 	acpi_namespace_node     *this_node;
 	acpi_operand_object     *obj_desc = NULL;
-	acpi_object_type8       obj_type;
-	acpi_object_type8       type;
+	acpi_object_type        obj_type;
+	acpi_object_type        type;
 	u32                     bytes_to_dump;
 	u32                     downstream_sibling_mask = 0;
 	u32                     level_tmp;
 	u32                     which_bit;
 	u32                     i;
+	u32                     dbg_level;
 
 
-	PROC_NAME ("Ns_dump_one_object");
+	ACPI_FUNCTION_NAME ("Ns_dump_one_object");
 
 
 	this_node = acpi_ns_map_handle_to_node (obj_handle);
@@ -147,68 +185,63 @@
 		return (AE_OK);
 	}
 
-
 	/* Indent the object according to the level */
 
 	while (level_tmp--) {
-
 		/* Print appropriate characters to form tree structure */
 
 		if (level_tmp) {
 			if (downstream_sibling_mask & which_bit) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "|"));
+				acpi_os_printf ("|");
 			}
-
 			else {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " "));
+				acpi_os_printf (" ");
 			}
 
 			which_bit <<= 1;
 		}
-
 		else {
 			if (acpi_ns_exist_downstream_sibling (this_node + 1)) {
 				downstream_sibling_mask |= (1 << (level - 1));
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "+"));
+				acpi_os_printf ("+");
 			}
-
 			else {
 				downstream_sibling_mask &= ACPI_UINT32_MAX ^ (1 << (level - 1));
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "+"));
+				acpi_os_printf ("+");
 			}
 
 			if (this_node->child == NULL) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "-"));
+				acpi_os_printf ("-");
 			}
-
 			else if (acpi_ns_exist_downstream_sibling (this_node->child)) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "+"));
+				acpi_os_printf ("+");
 			}
-
 			else {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "-"));
+				acpi_os_printf ("-");
 			}
 		}
 	}
 
-
 	/* Check the integrity of our data */
 
 	if (type > INTERNAL_TYPE_MAX) {
-		type = INTERNAL_TYPE_DEF_ANY;                                /* prints as *ERROR* */
+		type = INTERNAL_TYPE_DEF_ANY;  /* prints as *ERROR* */
 	}
 
 	if (!acpi_ut_valid_acpi_name (this_node->name)) {
-		REPORT_WARNING (("Invalid ACPI Name %08X\n", this_node->name));
+		ACPI_REPORT_WARNING (("Invalid ACPI Name %08X\n", this_node->name));
 	}
 
 	/*
 	 * Now we can print out the pertinent information
 	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " %4.4s %-12s %p",
-			(char*)&this_node->name, acpi_ut_get_type_name (type), this_node));
+	acpi_os_printf (" %4.4s %-12s %p",
+			(char *) &this_node->name, acpi_ut_get_type_name (type), this_node);
 
-	obj_desc = this_node->object;
+	dbg_level = acpi_dbg_level;
+	acpi_dbg_level = 0;
+	obj_desc = acpi_ns_get_attached_object (this_node);
+	acpi_dbg_level = dbg_level;
 
 	switch (info->display_type) {
 	case ACPI_DISPLAY_SUMMARY:
@@ -216,110 +249,109 @@
 		if (!obj_desc) {
 			/* No attached object, we are done */
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "\n"));
+			acpi_os_printf ("\n");
 			return (AE_OK);
 		}
 
-
 		switch (type) {
 		case ACPI_TYPE_PROCESSOR:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " ID %d Addr %.4X Len %.4X\n",
+			acpi_os_printf (" ID %d Addr %.4X Len %.4X\n",
 					 obj_desc->processor.proc_id,
 					 obj_desc->processor.address,
-					 obj_desc->processor.length));
+					 obj_desc->processor.length);
 			break;
 
 		case ACPI_TYPE_DEVICE:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Notification object: %p", obj_desc));
+			acpi_os_printf (" Notification object: %p", obj_desc);
 			break;
 
 		case ACPI_TYPE_METHOD:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Args %d Len %.4X Aml %p \n",
+			acpi_os_printf (" Args %d Len %.4X Aml %p \n",
 					 obj_desc->method.param_count,
 					 obj_desc->method.aml_length,
-					 obj_desc->method.aml_start));
+					 obj_desc->method.aml_start);
 			break;
 
 		case ACPI_TYPE_INTEGER:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " = %8.8X%8.8X\n",
-					 HIDWORD (obj_desc->integer.value),
-					 LODWORD (obj_desc->integer.value)));
+			acpi_os_printf (" = %8.8X%8.8X\n",
+					 ACPI_HIDWORD (obj_desc->integer.value),
+					 ACPI_LODWORD (obj_desc->integer.value));
 			break;
 
 		case ACPI_TYPE_PACKAGE:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Elements %.2X\n",
-					 obj_desc->package.count));
+			acpi_os_printf (" Elements %.2X\n",
+					 obj_desc->package.count);
 			break;
 
 		case ACPI_TYPE_BUFFER:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Len %.2X",
-					 obj_desc->buffer.length));
+			acpi_os_printf (" Len %.2X",
+					 obj_desc->buffer.length);
 
 			/* Dump some of the buffer */
 
 			if (obj_desc->buffer.length > 0) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " ="));
+				acpi_os_printf (" =");
 				for (i = 0; (i < obj_desc->buffer.length && i < 12); i++) {
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " %.2X",
-							obj_desc->buffer.pointer[i]));
+					acpi_os_printf (" %.2X", obj_desc->buffer.pointer[i]);
 				}
 			}
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "\n"));
+			acpi_os_printf ("\n");
 			break;
 
 		case ACPI_TYPE_STRING:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Len %.2X",
-					 obj_desc->string.length));
+			acpi_os_printf (" Len %.2X", obj_desc->string.length);
 
 			if (obj_desc->string.length > 0) {
-				 ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " = \"%.32s\"...",
-						 obj_desc->string.pointer));
+				 acpi_os_printf (" = \"%.32s\"...", obj_desc->string.pointer);
 			}
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "\n"));
+			acpi_os_printf ("\n");
 			break;
 
 		case ACPI_TYPE_REGION:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " [%s]",
-					 acpi_ut_get_region_name (obj_desc->region.space_id)));
+			acpi_os_printf (" [%s]", acpi_ut_get_region_name (obj_desc->region.space_id));
 			if (obj_desc->region.flags & AOPOBJ_DATA_VALID) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Addr %8.8X%8.8X Len %.4X\n",
-						 HIDWORD(obj_desc->region.address),
-						 LODWORD(obj_desc->region.address),
-						 obj_desc->region.length));
+				acpi_os_printf (" Addr %8.8X%8.8X Len %.4X\n",
+						 ACPI_HIDWORD (obj_desc->region.address),
+						 ACPI_LODWORD (obj_desc->region.address),
+						 obj_desc->region.length);
 			}
 			else {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " [Address/Length not evaluated]\n"));
+				acpi_os_printf (" [Address/Length not evaluated]\n");
 			}
 			break;
 
 		case INTERNAL_TYPE_REFERENCE:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " [%s]\n",
-					 acpi_ps_get_opcode_name (obj_desc->reference.opcode)));
+			acpi_os_printf (" [%s]\n",
+					acpi_ps_get_opcode_name (obj_desc->reference.opcode));
 			break;
 
 		case ACPI_TYPE_BUFFER_FIELD:
-
-			/* TBD: print Buffer name when we can easily get it */
+			if (obj_desc->buffer_field.buffer_obj &&
+				obj_desc->buffer_field.buffer_obj->buffer.node) {
+				acpi_os_printf (" Buf [%4.4s]",
+						(char *) &obj_desc->buffer_field.buffer_obj->buffer.node->name);
+			}
 			break;
 
 		case INTERNAL_TYPE_REGION_FIELD:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Rgn [%4.4s]",
-					 (char *) &obj_desc->common_field.region_obj->region.node->name));
+			acpi_os_printf (" Rgn [%4.4s]",
+					(char *) &obj_desc->common_field.region_obj->region.node->name);
 			break;
 
 		case INTERNAL_TYPE_BANK_FIELD:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Rgn [%4.4s]",
-					 (char *) &obj_desc->common_field.region_obj->region.node->name));
+			acpi_os_printf (" Rgn [%4.4s] Bnk [%4.4s]",
+					(char *) &obj_desc->common_field.region_obj->region.node->name,
+					(char *) &obj_desc->bank_field.bank_obj->common_field.node->name);
 			break;
 
 		case INTERNAL_TYPE_INDEX_FIELD:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Rgn [%4.4s]",
-					 (char *) &obj_desc->index_field.index_obj->common_field.region_obj->region.node->name));
+			acpi_os_printf (" Idx [%4.4s] Dat [%4.4s]",
+					(char *) &obj_desc->index_field.index_obj->common_field.node->name,
+					(char *) &obj_desc->index_field.data_obj->common_field.node->name);
 			break;
 
 		default:
-
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Object %p\n", obj_desc));
+			acpi_os_printf (" Object %p\n", obj_desc);
 			break;
 		}
 
@@ -330,10 +362,11 @@
 		case INTERNAL_TYPE_REGION_FIELD:
 		case INTERNAL_TYPE_BANK_FIELD:
 		case INTERNAL_TYPE_INDEX_FIELD:
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " Off %.2X Len %.2X Acc %.2d\n",
-					 (obj_desc->common_field.base_byte_offset * 8) + obj_desc->common_field.start_field_bit_offset,
-					 obj_desc->common_field.bit_length,
-					 obj_desc->common_field.access_bit_width));
+			acpi_os_printf (" Off %.2X Len %.2X Acc %.2d\n",
+					(obj_desc->common_field.base_byte_offset * 8)
+						+ obj_desc->common_field.start_field_bit_offset,
+					obj_desc->common_field.bit_length,
+					obj_desc->common_field.access_byte_width);
 			break;
 		}
 
@@ -342,62 +375,57 @@
 
 	case ACPI_DISPLAY_OBJECTS:
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "%p O:%p",
-				this_node, obj_desc));
+		acpi_os_printf ("%p O:%p",
+				this_node, obj_desc);
 
 		if (!obj_desc) {
 			/* No attached object, we are done */
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "\n"));
+			acpi_os_printf ("\n");
 			return (AE_OK);
 		}
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "(R%d)",
-				obj_desc->common.reference_count));
+		acpi_os_printf ("(R%d)",
+				obj_desc->common.reference_count);
 
 		switch (type) {
-
 		case ACPI_TYPE_METHOD:
 
 			/* Name is a Method and its AML offset/length are set */
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " M:%p-%X\n",
-					 obj_desc->method.aml_start,
-					 obj_desc->method.aml_length));
-
+			acpi_os_printf (" M:%p-%X\n", obj_desc->method.aml_start,
+					  obj_desc->method.aml_length);
 			break;
 
-
 		case ACPI_TYPE_INTEGER:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " N:%X%X\n",
-					 HIDWORD(obj_desc->integer.value),
-					 LODWORD(obj_desc->integer.value)));
+			acpi_os_printf (" N:%X%X\n", ACPI_HIDWORD(obj_desc->integer.value),
+					 ACPI_LODWORD(obj_desc->integer.value));
 			break;
 
-
 		case ACPI_TYPE_STRING:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " S:%p-%X\n",
-					 obj_desc->string.pointer,
-					 obj_desc->string.length));
+			acpi_os_printf (" S:%p-%X\n", obj_desc->string.pointer,
+					  obj_desc->string.length);
 			break;
 
-
 		case ACPI_TYPE_BUFFER:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, " B:%p-%X\n",
-					 obj_desc->buffer.pointer,
-					 obj_desc->buffer.length));
+			acpi_os_printf (" B:%p-%X\n", obj_desc->buffer.pointer,
+					  obj_desc->buffer.length);
 			break;
 
-
 		default:
 
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "\n"));
+			acpi_os_printf ("\n");
 			break;
 		}
 		break;
+
+
+	default:
+		acpi_os_printf ("\n");
+		break;
 	}
 
 	/* If debug turned off, done */
@@ -409,48 +437,55 @@
 
 	/* If there is an attached object, display it */
 
-	obj_desc = this_node->object;
+	dbg_level = acpi_dbg_level;
+	acpi_dbg_level = 0;
+	obj_desc = acpi_ns_get_attached_object (this_node);
+	acpi_dbg_level = dbg_level;
 
 	/* Dump attached objects */
 
 	while (obj_desc) {
 		obj_type = INTERNAL_TYPE_INVALID;
+		acpi_os_printf ("      Attached Object %p: ", obj_desc);
 
 		/* Decode the type of attached object and dump the contents */
 
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "        Attached Object %p: ", obj_desc));
+		switch (ACPI_GET_DESCRIPTOR_TYPE (obj_desc)) {
+		case ACPI_DESC_TYPE_NAMED:
 
-		if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_NAMED)) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "(Ptr to Node)\n"));
+			acpi_os_printf ("(Ptr to Node)\n");
 			bytes_to_dump = sizeof (acpi_namespace_node);
-		}
+			break;
+
 
+		case ACPI_DESC_TYPE_INTERNAL:
 
-		else if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_INTERNAL)) {
 			obj_type = obj_desc->common.type;
 
 			if (obj_type > INTERNAL_TYPE_MAX) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "(Ptr to ACPI Object type %X [UNKNOWN])\n", obj_type));
+				acpi_os_printf ("(Ptr to ACPI Object type %X [UNKNOWN])\n", obj_type);
 				bytes_to_dump = 32;
 			}
-
 			else {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "(Ptr to ACPI Object type %2.2X [%s])\n",
-						   obj_type, acpi_ut_get_type_name (obj_type)));
+				acpi_os_printf ("(Ptr to ACPI Object type %2.2X [%s])\n",
+						   obj_type, acpi_ut_get_type_name (obj_type));
 				bytes_to_dump = sizeof (acpi_operand_object);
 			}
-		}
+			break;
 
-		else {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "(String or Buffer - not descriptor)\n"));
+
+		default:
+
+			acpi_os_printf ("(String or Buffer ptr - not an object descriptor)\n");
 			bytes_to_dump = 16;
+			break;
 		}
 
-		DUMP_BUFFER (obj_desc, bytes_to_dump);
+		ACPI_DUMP_BUFFER (obj_desc, bytes_to_dump);
 
 		/* If value is NOT an internal object, we are done */
 
-		if (VALID_DESCRIPTOR_TYPE (obj_desc, ACPI_DESC_TYPE_NAMED)) {
+		if (ACPI_GET_DESCRIPTOR_TYPE (obj_desc) != ACPI_DESC_TYPE_INTERNAL) {
 			goto cleanup;
 		}
 
@@ -494,11 +529,11 @@
 			goto cleanup;
 		}
 
-		obj_type = INTERNAL_TYPE_INVALID;    /* Terminate loop after next pass */
+		obj_type = INTERNAL_TYPE_INVALID;  /* Terminate loop after next pass */
 	}
 
 cleanup:
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "\n"));
+	acpi_os_printf ("\n");
 	return (AE_OK);
 }
 
@@ -521,7 +556,7 @@
 
 void
 acpi_ns_dump_objects (
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	u8                      display_type,
 	u32                     max_depth,
 	u32                     owner_id,
@@ -530,7 +565,7 @@
 	acpi_walk_info          info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	info.debug_level = ACPI_LV_TABLES;
@@ -538,7 +573,7 @@
 	info.display_type = display_type;
 
 
-	acpi_ns_walk_namespace (type, start_handle, max_depth, NS_WALK_NO_UNLOCK, acpi_ns_dump_one_object,
+	acpi_ns_walk_namespace (type, start_handle, max_depth, ACPI_NS_WALK_NO_UNLOCK, acpi_ns_dump_one_object,
 			   (void *) &info, NULL);
 }
 
@@ -569,7 +604,7 @@
 	u32                     i;
 
 
-	PROC_NAME ("Ns_dump_one_device");
+	ACPI_FUNCTION_NAME ("Ns_dump_one_device");
 
 
 	status = acpi_ns_dump_one_object (obj_handle, level, context, return_value);
@@ -581,7 +616,9 @@
 		}
 
 		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_TABLES, "    HID: %s, ADR: %8.8X%8.8X, Status: %x\n",
-				  info.hardware_id, HIDWORD(info.address), LODWORD(info.address), info.current_status));
+				  info.hardware_id,
+				  ACPI_HIDWORD (info.address), ACPI_LODWORD (info.address),
+				  info.current_status));
 	}
 
 	return (status);
@@ -604,7 +641,7 @@
 	acpi_handle             sys_bus_handle;
 
 
-	PROC_NAME ("Ns_dump_root_devices");
+	ACPI_FUNCTION_NAME ("Ns_dump_root_devices");
 
 
 	/* Only dump the table if tracing is enabled */
@@ -613,10 +650,10 @@
 		return;
 	}
 
-	acpi_get_handle (0, NS_SYSTEM_BUS, &sys_bus_handle);
+	acpi_get_handle (0, ACPI_NS_SYSTEM_BUS, &sys_bus_handle);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_TABLES, "Display of all devices in the namespace:\n"));
-	acpi_ns_walk_namespace (ACPI_TYPE_DEVICE, sys_bus_handle, ACPI_UINT32_MAX, NS_WALK_NO_UNLOCK,
+	acpi_ns_walk_namespace (ACPI_TYPE_DEVICE, sys_bus_handle, ACPI_UINT32_MAX, ACPI_NS_WALK_NO_UNLOCK,
 			   acpi_ns_dump_one_device, NULL, NULL);
 }
 
@@ -643,7 +680,7 @@
 	acpi_handle             search_handle = search_base;
 
 
-	FUNCTION_TRACE ("Ns_dump_tables");
+	ACPI_FUNCTION_TRACE ("Ns_dump_tables");
 
 
 	if (!acpi_gbl_root_node) {
@@ -655,7 +692,7 @@
 		return_VOID;
 	}
 
-	if (NS_ALL == search_base) {
+	if (ACPI_NS_ALL == search_base) {
 		/*  entire namespace    */
 
 		search_handle = acpi_gbl_root_node;
@@ -688,11 +725,12 @@
 	acpi_walk_info          info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	info.debug_level = debug_level;
 	info.owner_id = ACPI_UINT32_MAX;
+	info.display_type = ACPI_DISPLAY_SUMMARY;
 
 	acpi_ns_dump_one_object (handle, 1, &info, NULL);
 }
diff -Nru a/drivers/acpi/namespace/nseval.c b/drivers/acpi/namespace/nseval.c
--- a/drivers/acpi/namespace/nseval.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/namespace/nseval.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: nseval - Object evaluation interfaces -- includes control
  *                       method lookup and execution.
- *              $Revision: 102 $
+ *              $Revision: 109 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nseval")
+	 ACPI_MODULE_NAME    ("nseval")
 
 
 /*******************************************************************************
@@ -72,7 +72,7 @@
 	acpi_generic_state      scope_info;
 
 
-	FUNCTION_TRACE ("Ns_evaluate_relative");
+	ACPI_FUNCTION_TRACE ("Ns_evaluate_relative");
 
 
 	/*
@@ -91,11 +91,14 @@
 
 	/* Get the prefix handle and Node */
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	prefix_node = acpi_ns_map_handle_to_node (handle);
 	if (!prefix_node) {
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 		status = AE_BAD_PARAMETER;
 		goto cleanup;
 	}
@@ -104,10 +107,10 @@
 
 	scope_info.scope.node = prefix_node;
 	status = acpi_ns_lookup (&scope_info, internal_path, ACPI_TYPE_ANY,
-			 IMODE_EXECUTE, NS_NO_UPSEARCH, NULL,
+			 ACPI_IMODE_EXECUTE, ACPI_NS_NO_UPSEARCH, NULL,
 			 &node);
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 
 	if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Object [%s] not found [%s]\n",
@@ -120,7 +123,7 @@
 	 * to evaluate it.
 	 */
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%s [%p] Value %p\n",
-		pathname, node, node->object));
+		pathname, node, acpi_ns_get_attached_object (node)));
 
 	status = acpi_ns_evaluate_by_handle (node, params, return_object);
 
@@ -165,7 +168,7 @@
 	NATIVE_CHAR             *internal_path = NULL;
 
 
-	FUNCTION_TRACE ("Ns_evaluate_by_name");
+	ACPI_FUNCTION_TRACE ("Ns_evaluate_by_name");
 
 
 	/* Build an internal name string for the method */
@@ -175,15 +178,18 @@
 		return_ACPI_STATUS (status);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Lookup the name in the namespace */
 
 	status = acpi_ns_lookup (NULL, internal_path, ACPI_TYPE_ANY,
-			 IMODE_EXECUTE, NS_NO_UPSEARCH, NULL,
+			 ACPI_IMODE_EXECUTE, ACPI_NS_NO_UPSEARCH, NULL,
 			 &node);
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 
 	if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Object at [%s] was not found, status=%.4X\n",
@@ -196,7 +202,7 @@
 	 * to evaluate it.
 	 */
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%s [%p] Value %p\n",
-		pathname, node, node->object));
+		pathname, node, acpi_ns_get_attached_object (node)));
 
 	status = acpi_ns_evaluate_by_handle (node, params, return_object);
 
@@ -246,7 +252,7 @@
 	acpi_operand_object     *local_return_object;
 
 
-	FUNCTION_TRACE ("Ns_evaluate_by_handle");
+	ACPI_FUNCTION_TRACE ("Ns_evaluate_by_handle");
 
 
 	/* Check if namespace has been initialized */
@@ -269,11 +275,14 @@
 
 	/* Get the prefix handle and Node */
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	node = acpi_ns_map_handle_to_node (handle);
 	if (!node) {
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
@@ -368,7 +377,7 @@
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE ("Ns_execute_control_method");
+	ACPI_FUNCTION_TRACE ("Ns_execute_control_method");
 
 
 	/* Verify that there is a method associated with this object */
@@ -377,7 +386,7 @@
 	if (!obj_desc) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "No attached method object\n"));
 
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 		return_ACPI_STATUS (AE_NULL_OBJECT);
 	}
 
@@ -385,7 +394,7 @@
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Control method at Offset %p Length %x]\n",
 		obj_desc->method.aml_start + 1, obj_desc->method.aml_length - 1));
 
-	DUMP_PATHNAME (method_node, "Ns_execute_control_method: Executing",
+	ACPI_DUMP_PATHNAME (method_node, "Ns_execute_control_method: Executing",
 		ACPI_LV_NAMES, _COMPONENT);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "At offset %p\n",
@@ -399,7 +408,10 @@
 	 * interpreter locks to ensure that no thread is using the portion of the
 	 * namespace that is being deleted.
 	 */
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/*
 	 * Execute the method via the interpreter.  The interpreter is locked
@@ -427,7 +439,7 @@
  *
  * DESCRIPTION: Return the current value of the object
  *
- * MUTEX:       Assumes namespace is locked
+ * MUTEX:       Assumes namespace is locked, leaves namespace unlocked
  *
  ******************************************************************************/
 
@@ -438,110 +450,59 @@
 {
 	acpi_status             status = AE_OK;
 	acpi_operand_object     *obj_desc;
-	acpi_operand_object     *source_desc;
 
 
-	FUNCTION_TRACE ("Ns_get_object_value");
+	ACPI_FUNCTION_TRACE ("Ns_get_object_value");
 
 
 	/*
-	 *  We take the value from certain objects directly
+	 * Objects require additional resolution steps (e.g., the
+	 * Node may be a field that must be read, etc.) -- we can't just grab
+	 * the object out of the node.
 	 */
-	if ((node->type == ACPI_TYPE_PROCESSOR) ||
-		(node->type == ACPI_TYPE_POWER)) {
-		/*
-		 *  Create a Reference object to contain the object
-		 */
-		obj_desc = acpi_ut_create_internal_object (node->type);
-		if (!obj_desc) {
-		   status = AE_NO_MEMORY;
-		   goto unlock_and_exit;
-		}
-
-		/*
-		 *  Get the attached object
-		 */
-		source_desc = acpi_ns_get_attached_object (node);
-		if (!source_desc) {
-			status = AE_NULL_OBJECT;
-			goto unlock_and_exit;
-		}
-
-		/*
-		 * Just copy from the original to the return object
-		 *
-		 * TBD: [Future] - need a low-level object copy that handles
-		 * the reference count automatically.  (Don't want to copy it)
-		 */
-		MEMCPY (obj_desc, source_desc, sizeof (acpi_operand_object));
-		obj_desc->common.reference_count = 1;
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-	}
-
+	obj_desc = (acpi_operand_object *) node;
 
 	/*
-	 * Other objects require a reference object wrapper which we
-	 * then attempt to resolve.
+	 * Use Resolve_node_to_value() to get the associated value. This call
+	 * always deletes Obj_desc (allocated above).
+	 *
+	 * NOTE: we can get away with passing in NULL for a walk state
+	 * because Obj_desc is guaranteed to not be a reference to either
+	 * a method local or a method argument (because this interface can only be
+	 * called from the Acpi_evaluate external interface, never called from
+	 * a running control method.)
+	 *
+	 * Even though we do not directly invoke the interpreter
+	 * for this, we must enter it because we could access an opregion.
+	 * The opregion access code assumes that the interpreter
+	 * is locked.
+	 *
+	 * We must release the namespace lock before entering the
+	 * intepreter.
 	 */
-	else {
-		/* Create an Reference object to contain the object */
-
-		obj_desc = acpi_ut_create_internal_object (INTERNAL_TYPE_REFERENCE);
-		if (!obj_desc) {
-		   status = AE_NO_MEMORY;
-		   goto unlock_and_exit;
-		}
-
-		/* Construct a descriptor pointing to the name */
-
-		obj_desc->reference.opcode = (u8) AML_NAME_OP;
-		obj_desc->reference.object = (void *) node;
+	status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
+	status = acpi_ex_enter_interpreter ();
+	if (ACPI_SUCCESS (status)) {
+		status = acpi_ex_resolve_node_to_value ((acpi_namespace_node **) &obj_desc, NULL);
 		/*
-		 * Use Resolve_to_value() to get the associated value. This call
-		 * always deletes Obj_desc (allocated above).
-		 *
-		 * NOTE: we can get away with passing in NULL for a walk state
-		 * because Obj_desc is guaranteed to not be a reference to either
-		 * a method local or a method argument
-		 *
-		 * Even though we do not directly invoke the interpreter
-		 * for this, we must enter it because we could access an opregion.
-		 * The opregion access code assumes that the interpreter
-		 * is locked.
-		 *
-		 * We must release the namespace lock before entering the
-		 * intepreter.
+		 * If Acpi_ex_resolve_node_to_value() succeeded, the return value was
+		 * placed in Obj_desc.
 		 */
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-		status = acpi_ex_enter_interpreter ();
-		if (ACPI_SUCCESS (status)) {
-			status = acpi_ex_resolve_to_value (&obj_desc, NULL);
+		acpi_ex_exit_interpreter ();
 
-			acpi_ex_exit_interpreter ();
+		if (ACPI_SUCCESS (status)) {
+			status = AE_CTRL_RETURN_VALUE;
+			*return_obj_desc = obj_desc;
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Returning obj %p\n", *return_obj_desc));
 		}
 	}
 
-	/*
-	 * If Acpi_ex_resolve_to_value() succeeded, the return value was
-	 * placed in Obj_desc.
-	 */
-	if (ACPI_SUCCESS (status)) {
-		status = AE_CTRL_RETURN_VALUE;
-
-		*return_obj_desc = obj_desc;
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Returning obj %p\n", *return_obj_desc));
-	}
-
 	/* Namespace is unlocked */
 
 	return_ACPI_STATUS (status);
-
-
-unlock_and_exit:
-
-	/* Unlock the namespace */
-
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-	return_ACPI_STATUS (status);
 }
+
diff -Nru a/drivers/acpi/namespace/nsinit.c b/drivers/acpi/namespace/nsinit.c
--- a/drivers/acpi/namespace/nsinit.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/namespace/nsinit.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: nsinit - namespace initialization
- *              $Revision: 33 $
+ *              $Revision: 41 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsinit")
+	 ACPI_MODULE_NAME    ("nsinit")
 
 
 /*******************************************************************************
@@ -54,7 +54,7 @@
 	acpi_init_walk_info     info;
 
 
-	FUNCTION_TRACE ("Ns_initialize_objects");
+	ACPI_FUNCTION_TRACE ("Ns_initialize_objects");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH,
@@ -115,7 +115,7 @@
 	acpi_device_walk_info   info;
 
 
-	FUNCTION_TRACE ("Ns_initialize_devices");
+	ACPI_FUNCTION_TRACE ("Ns_initialize_devices");
 
 
 	info.device_count = 0;
@@ -168,14 +168,14 @@
 	void                    *context,
 	void                    **return_value)
 {
-	acpi_object_type8       type;
+	acpi_object_type        type;
 	acpi_status             status;
 	acpi_init_walk_info     *info = (acpi_init_walk_info *) context;
 	acpi_namespace_node     *node = (acpi_namespace_node *) obj_handle;
 	acpi_operand_object     *obj_desc;
 
 
-	PROC_NAME ("Ns_init_one_object");
+	ACPI_FUNCTION_NAME ("Ns_init_one_object");
 
 
 	info->object_count++;
@@ -184,7 +184,7 @@
 	/* And even then, we are only interested in a few object types */
 
 	type = acpi_ns_get_type (obj_handle);
-	obj_desc = node->object;
+	obj_desc = acpi_ns_get_attached_object (node);
 	if (!obj_desc) {
 		return (AE_OK);
 	}
@@ -218,7 +218,7 @@
 			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_ERROR, "\n"));
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 					"%s while getting region arguments [%4.4s]\n",
-					acpi_format_exception (status), (char*)&node->name));
+					acpi_format_exception (status), (char *) &node->name));
 		}
 
 		if (!(acpi_dbg_level & ACPI_LV_INIT)) {
@@ -241,7 +241,7 @@
 			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_ERROR, "\n"));
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 					"%s while getting buffer field arguments [%4.4s]\n",
-					acpi_format_exception (status), (char*)&node->name));
+					acpi_format_exception (status), (char *) &node->name));
 		}
 		if (!(acpi_dbg_level & ACPI_LV_INIT)) {
 			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK, "."));
@@ -291,7 +291,7 @@
 	acpi_device_walk_info  *info = (acpi_device_walk_info *) context;
 
 
-	FUNCTION_TRACE ("Ns_init_one_device");
+	ACPI_FUNCTION_TRACE ("Ns_init_one_device");
 
 
 	if (!(acpi_dbg_level & ACPI_LV_INIT)) {
@@ -300,20 +300,26 @@
 
 	info->device_count++;
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	node = acpi_ns_map_handle_to_node (obj_handle);
 	if (!node) {
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-		return (AE_BAD_PARAMETER);
+		(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/*
 	 * Run _STA to determine if we can run _INI on the device.
 	 */
-	DEBUG_EXEC (acpi_ut_display_init_pathname (node, "_STA [Method]"));
+	ACPI_DEBUG_EXEC (acpi_ut_display_init_pathname (node, "_STA [Method]"));
 	status = acpi_ut_execute_STA (node, &flags);
 	if (ACPI_FAILURE (status)) {
 		/* Ignore error and move on to next device */
@@ -333,7 +339,7 @@
 	/*
 	 * The device is present. Run _INI.
 	 */
-	DEBUG_EXEC (acpi_ut_display_init_pathname (obj_handle, "_INI [Method]"));
+	ACPI_DEBUG_EXEC (acpi_ut_display_init_pathname (obj_handle, "_INI [Method]"));
 	status = acpi_ns_evaluate_relative (obj_handle, "_INI", NULL, NULL);
 	if (AE_NOT_FOUND == status) {
 		/* No _INI means device requires no initialization */
@@ -345,7 +351,7 @@
 		/* Ignore error and move on to next device */
 
 #ifdef ACPI_DEBUG
-		NATIVE_CHAR *scope_name = acpi_ns_get_table_pathname (obj_handle);
+		NATIVE_CHAR *scope_name = acpi_ns_get_external_pathname (obj_handle);
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "%s._INI failed: %s\n",
 				scope_name, acpi_format_exception (status)));
diff -Nru a/drivers/acpi/namespace/nsload.c b/drivers/acpi/namespace/nsload.c
--- a/drivers/acpi/namespace/nsload.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/namespace/nsload.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: nsload - namespace loading/expanding/contracting procedures
- *              $Revision: 47 $
+ *              $Revision: 53 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,14 +34,14 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsload")
+	 ACPI_MODULE_NAME    ("nsload")
 
 
 /*******************************************************************************
  *
  * FUNCTION:    Acpi_load_namespace
  *
- * PARAMETERS:  Display_aml_during_load
+ * PARAMETERS:  None
  *
  * RETURN:      Status
  *
@@ -57,7 +57,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_load_name_space");
+	ACPI_FUNCTION_TRACE ("Acpi_load_name_space");
 
 
 	/* There must be at least a DSDT installed */
@@ -67,7 +67,6 @@
 		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
 	}
 
-
 	/*
 	 * Load the namespace.  The DSDT is required,
 	 * but the SSDT and PSDT tables are optional.
@@ -82,12 +81,10 @@
 	acpi_ns_load_table_by_type (ACPI_TABLE_SSDT);
 	acpi_ns_load_table_by_type (ACPI_TABLE_PSDT);
 
-
 	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
 		"ACPI Namespace successfully loaded at root %p\n",
 		acpi_gbl_root_node));
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -96,11 +93,12 @@
  *
  * FUNCTION:    Acpi_ns_one_parse_pass
  *
- * PARAMETERS:
+ * PARAMETERS:  Pass_number             - 1 or 2
+ *              Table_desc              - The table to be parsed.
  *
  * RETURN:      Status
  *
- * DESCRIPTION:
+ * DESCRIPTION: Perform one complete parse of an ACPI/AML table.
  *
  ******************************************************************************/
 
@@ -114,7 +112,7 @@
 	acpi_walk_state         *walk_state;
 
 
-	FUNCTION_TRACE ("Ns_one_complete_parse");
+	ACPI_FUNCTION_TRACE ("Ns_one_complete_parse");
 
 
 	/* Create and init a Root Node */
@@ -126,7 +124,6 @@
 
 	((acpi_parse2_object *) parse_root)->name = ACPI_ROOT_NAME;
 
-
 	/* Create and initialize a new walk state */
 
 	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
@@ -174,7 +171,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ns_parse_table");
+	ACPI_FUNCTION_TRACE ("Ns_parse_table");
 
 
 	/*
@@ -192,7 +189,6 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/*
 	 * AML Parse, pass 2
 	 *
@@ -232,8 +228,18 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ns_load_table");
+	ACPI_FUNCTION_TRACE ("Ns_load_table");
+
+
+	/* Check if table contains valid AML (must be DSDT, PSDT, SSDT, etc.) */
 
+	if (!(acpi_gbl_acpi_table_data[table_desc->type].flags & ACPI_TABLE_EXECUTABLE)) {
+		/* Just ignore this table */
+
+		return_ACPI_STATUS (AE_OK);
+	}
+
+	/* Check validity of the AML start and length */
 
 	if (!table_desc->aml_start) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Null AML pointer\n"));
@@ -242,13 +248,11 @@
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "AML block at %p\n", table_desc->aml_start));
 
-
 	if (!table_desc->aml_length) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Zero-length AML block\n"));
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	/*
 	 * Parse the table and load the namespace with all named
 	 * objects found within.  Control methods are NOT parsed
@@ -260,9 +264,13 @@
 	 */
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "**** Loading table into namespace ****\n"));
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	status = acpi_ns_parse_table (table_desc, node->child);
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
@@ -305,22 +313,23 @@
 	acpi_table_type         table_type)
 {
 	u32                     i;
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 	acpi_table_desc         *table_desc;
 
 
-	FUNCTION_TRACE ("Ns_load_table_by_type");
-
+	ACPI_FUNCTION_TRACE ("Ns_load_table_by_type");
 
-	acpi_ut_acquire_mutex (ACPI_MTX_TABLES);
 
+	status = acpi_ut_acquire_mutex (ACPI_MTX_TABLES);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/*
 	 * Table types supported are:
 	 * DSDT (one), SSDT/PSDT (multiple)
 	 */
 	switch (table_type) {
-
 	case ACPI_TABLE_DSDT:
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Loading DSDT\n"));
@@ -408,11 +417,8 @@
 
 
 unlock_and_exit:
-
-	acpi_ut_release_mutex (ACPI_MTX_TABLES);
-
+	(void) acpi_ut_release_mutex (ACPI_MTX_TABLES);
 	return_ACPI_STATUS (status);
-
 }
 
 
@@ -427,8 +433,8 @@
  * DESCRIPTION: Walks the namespace starting at the given handle and deletes
  *              all objects, entries, and scopes in the entire subtree.
  *
- *              TBD: [Investigate] What if any part of this subtree is in use?
- *              (i.e. on one of the object stacks?)
+ *              Namespace/Interpreter should be locked or the subsystem should
+ *              be in shutdown before this routine is called.
  *
  ******************************************************************************/
 
@@ -444,7 +450,7 @@
 	u32                     level;
 
 
-	FUNCTION_TRACE ("Ns_delete_subtree");
+	ACPI_FUNCTION_TRACE ("Ns_delete_subtree");
 
 
 	parent_handle = start_handle;
@@ -463,7 +469,6 @@
 
 		child_handle = next_child_handle;
 
-
 		/* Did we get a new object? */
 
 		if (ACPI_SUCCESS (status)) {
@@ -480,7 +485,6 @@
 				child_handle = 0;
 			}
 		}
-
 		else {
 			/*
 			 * No more children in this object, go back up to
@@ -526,7 +530,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ns_unload_name_space");
+	ACPI_FUNCTION_TRACE ("Ns_unload_name_space");
 
 
 	/* Parameter validation */
@@ -538,7 +542,6 @@
 	if (!handle) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
-
 
 	/* This function does the real work */
 
diff -Nru a/drivers/acpi/namespace/nsnames.c b/drivers/acpi/namespace/nsnames.c
--- a/drivers/acpi/namespace/nsnames.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/namespace/nsnames.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: nsnames - Name manipulation and search
- *              $Revision: 64 $
+ *              $Revision: 74 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,91 +31,123 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsnames")
+	 ACPI_MODULE_NAME    ("nsnames")
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ns_get_table_pathname
+ * FUNCTION:    Acpi_ns_build_external_path
  *
- * PARAMETERS:  Node        - Scope whose name is needed
+ * PARAMETERS:  Node            - NS node whose pathname is needed
+ *              Size            - Size of the pathname
+ *              *Name_buffer    - Where to return the pathname
  *
- * RETURN:      Pointer to storage containing the fully qualified name of
- *              the scope, in Label format (all segments strung together
- *              with no separators)
+ * RETURN:      Places the pathname into the Name_buffer, in external format
+ *              (name segments separated by path separators)
  *
- * DESCRIPTION: Used for debug printing in Acpi_ns_search_table().
+ * DESCRIPTION: Generate a full pathaname
  *
  ******************************************************************************/
 
-NATIVE_CHAR *
-acpi_ns_get_table_pathname (
-	acpi_namespace_node     *node)
+void
+acpi_ns_build_external_path (
+	acpi_namespace_node     *node,
+	ACPI_SIZE               size,
+	NATIVE_CHAR             *name_buffer)
 {
-	NATIVE_CHAR             *name_buffer;
-	u32                     size;
-	acpi_name               name;
-	acpi_namespace_node     *child_node;
+	u32                     index;
 	acpi_namespace_node     *parent_node;
 
 
-	FUNCTION_TRACE_PTR ("Ns_get_table_pathname", node);
+	ACPI_FUNCTION_NAME ("Ns_build_external_path");
 
 
-	if (!acpi_gbl_root_node || !node) {
-		/*
-		 * If the name space has not been initialized,
-		 * this function should not have been called.
-		 */
-		return_PTR (NULL);
+	/* Special case for root */
+
+	index = size - 1;
+	if (index < ACPI_NAME_SIZE) {
+		name_buffer[0] = AML_ROOT_PREFIX;
+		name_buffer[1] = 0;
+		return;
 	}
 
-	child_node = node->child;
+	/* Store terminator byte, then build name backwards */
+
+	parent_node = node;
+	name_buffer[index] = 0;
 
+	while ((index > ACPI_NAME_SIZE) && (parent_node != acpi_gbl_root_node)) {
+		index -= ACPI_NAME_SIZE;
 
-	/* Calculate required buffer size based on depth below root */
+		/* Put the name into the buffer */
+
+		ACPI_MOVE_UNALIGNED32_TO_32 ((name_buffer + index), &parent_node->name);
+		parent_node = acpi_ns_get_parent_node (parent_node);
 
-	size = 1;
-	parent_node = child_node;
-	while (parent_node) {
-		parent_node = acpi_ns_get_parent_object (parent_node);
-		if (parent_node) {
-			size += ACPI_NAME_SIZE;
-		}
+		/* Prefix name with the path separator */
+
+		index--;
+		name_buffer[index] = PATH_SEPARATOR;
 	}
 
+	/* Overwrite final separator with the root prefix character */
 
-	/* Allocate a buffer to be returned to caller */
+	name_buffer[index] = AML_ROOT_PREFIX;
 
-	name_buffer = ACPI_MEM_CALLOCATE (size + 1);
-	if (!name_buffer) {
-		REPORT_ERROR (("Ns_get_table_pathname: allocation failure\n"));
-		return_PTR (NULL);
+	if (index != 0) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+			"Could not construct pathname; index=%X, size=%X, Path=%s\n",
+			index, size, &name_buffer[size]));
 	}
 
+	return;
+}
 
-	/* Store terminator byte, then build name backwards */
 
-	name_buffer[size] = '\0';
-	while ((size > ACPI_NAME_SIZE) &&
-		acpi_ns_get_parent_object (child_node)) {
-		size -= ACPI_NAME_SIZE;
-		name = acpi_ns_find_parent_name (child_node);
+#ifdef ACPI_DEBUG
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ns_get_external_pathname
+ *
+ * PARAMETERS:  Node            - NS node whose pathname is needed
+ *
+ * RETURN:      Pointer to storage containing the fully qualified name of
+ *              the node, In external format (name segments separated by path
+ *              separators.)
+ *
+ * DESCRIPTION: Used for debug printing in Acpi_ns_search_table().
+ *
+ ******************************************************************************/
 
-		/* Put the name into the buffer */
+NATIVE_CHAR *
+acpi_ns_get_external_pathname (
+	acpi_namespace_node     *node)
+{
+	NATIVE_CHAR             *name_buffer;
+	ACPI_SIZE               size;
+
+
+	ACPI_FUNCTION_TRACE_PTR ("Ns_get_external_pathname", node);
 
-		MOVE_UNALIGNED32_TO_32 ((name_buffer + size), &name);
-		child_node = acpi_ns_get_parent_object (child_node);
-	}
 
-	name_buffer[--size] = AML_ROOT_PREFIX;
+	/* Calculate required buffer size based on depth below root */
+
+	size = acpi_ns_get_pathname_length (node);
+
+	/* Allocate a buffer to be returned to caller */
 
-	if (size != 0) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Bad pointer returned; size=%X\n", size));
+	name_buffer = ACPI_MEM_CALLOCATE (size);
+	if (!name_buffer) {
+		ACPI_REPORT_ERROR (("Ns_get_table_pathname: allocation failure\n"));
+		return_PTR (NULL);
 	}
 
+	/* Build the path in the allocated buffer */
+
+	acpi_ns_build_external_path (node, size, name_buffer);
 	return_PTR (name_buffer);
 }
+#endif
 
 
 /*******************************************************************************
@@ -130,31 +162,27 @@
  *
  ******************************************************************************/
 
-u32
+ACPI_SIZE
 acpi_ns_get_pathname_length (
 	acpi_namespace_node     *node)
 {
-	u32                     size;
+	ACPI_SIZE               size;
 	acpi_namespace_node     *next_node;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
 	 * Compute length of pathname as 5 * number of name segments.
 	 * Go back up the parent tree to the root
 	 */
-	for (size = 0, next_node = node;
-		  acpi_ns_get_parent_object (next_node);
-		  next_node = acpi_ns_get_parent_object (next_node)) {
-		size += PATH_SEGMENT_LENGTH;
-	}
-
-	/* Special case for size still 0 - no parent for "special" nodes */
+	size = 0;
+	next_node = node;
 
-	if (!size) {
-		size = PATH_SEGMENT_LENGTH;
+	while (next_node != acpi_gbl_root_node) {
+		size += PATH_SEGMENT_LENGTH;
+		next_node = acpi_ns_get_parent_node (next_node);
 	}
 
 	return (size + 1);
@@ -167,96 +195,49 @@
  *
  * PARAMETERS:  Target_handle           - Handle of named object whose name is
  *                                        to be found
- *              Buf_size                - Size of the buffer provided
- *              User_buffer             - Where the pathname is returned
+ *              Buffer                  - Where the pathname is returned
  *
  * RETURN:      Status, Buffer is filled with pathname if status is AE_OK
  *
  * DESCRIPTION: Build and return a full namespace pathname
  *
- * MUTEX:       Locks Namespace
- *
  ******************************************************************************/
 
 acpi_status
 acpi_ns_handle_to_pathname (
 	acpi_handle             target_handle,
-	u32                     *buf_size,
-	NATIVE_CHAR             *user_buffer)
+	acpi_buffer             *buffer)
 {
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 	acpi_namespace_node     *node;
-	u32                     path_length;
-	u32                     user_buf_size;
-	acpi_name               name;
-	u32                     size;
+	ACPI_SIZE               required_size;
 
 
-	FUNCTION_TRACE_PTR ("Ns_handle_to_pathname", target_handle);
+	ACPI_FUNCTION_TRACE_PTR ("Ns_handle_to_pathname", target_handle);
 
 
-	if (!acpi_gbl_root_node) {
-		/*
-		 * If the name space has not been initialized,
-		 * this function should not have been called.
-		 */
-		return_ACPI_STATUS (AE_NO_NAMESPACE);
-	}
-
 	node = acpi_ns_map_handle_to_node (target_handle);
 	if (!node) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	/* Determine size required for the caller buffer */
 
-	/* Set return length to the required path length */
-
-	path_length = acpi_ns_get_pathname_length (node);
-	size = path_length - 1;
-
-	user_buf_size = *buf_size;
-	*buf_size = path_length;
+	required_size = acpi_ns_get_pathname_length (node);
 
-	/* Check if the user buffer is sufficiently large */
+	/* Validate/Allocate/Clear caller buffer */
 
-	if (path_length > user_buf_size) {
-		status = AE_BUFFER_OVERFLOW;
-		goto exit;
+	status = acpi_ut_initialize_buffer (buffer, required_size);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	/* Store null terminator */
-
-	user_buffer[size] = 0;
-	size -= ACPI_NAME_SIZE;
-
-	/* Put the original ACPI name at the end of the path */
-
-	MOVE_UNALIGNED32_TO_32 ((user_buffer + size),
-			 &node->name);
-
-	user_buffer[--size] = PATH_SEPARATOR;
-
-	/* Build name backwards, putting "." between segments */
-
-	while ((size > ACPI_NAME_SIZE) && node) {
-		size -= ACPI_NAME_SIZE;
-		name = acpi_ns_find_parent_name (node);
-		MOVE_UNALIGNED32_TO_32 ((user_buffer + size), &name);
-
-		user_buffer[--size] = PATH_SEPARATOR;
-		node = acpi_ns_get_parent_object (node);
-	}
-
-	/*
-	 * Overlay the "." preceding the first segment with
-	 * the root name "\"
-	 */
-	user_buffer[size] = '\\';
+	/* Build the path in the caller buffer */
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Len=%X, %s \n", path_length, user_buffer));
+	acpi_ns_build_external_path (node, required_size, buffer->pointer);
 
-exit:
-	return_ACPI_STATUS (status);
+	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "%s [%X] \n", (char *) buffer->pointer, required_size));
+	return_ACPI_STATUS (AE_OK);
 }
 
 
diff -Nru a/drivers/acpi/namespace/nsobject.c b/drivers/acpi/namespace/nsobject.c
--- a/drivers/acpi/namespace/nsobject.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/namespace/nsobject.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: nsobject - Utilities for objects attached to namespace
  *                         table entries
- *              $Revision: 67 $
+ *              $Revision: 78 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsobject")
+	 ACPI_MODULE_NAME    ("nsobject")
 
 
 /*******************************************************************************
@@ -48,6 +48,8 @@
  * DESCRIPTION: Record the given object as the value associated with the
  *              name whose acpi_handle is passed.  If Object is NULL
  *              and Type is ACPI_TYPE_ANY, set the name as having no value.
+ *              Note: Future may require that the Node->Flags field be passed
+ *              as a parameter.
  *
  * MUTEX:       Assumes namespace is locked
  *
@@ -57,45 +59,37 @@
 acpi_ns_attach_object (
 	acpi_namespace_node     *node,
 	acpi_operand_object     *object,
-	acpi_object_type8       type)
+	acpi_object_type        type)
 {
 	acpi_operand_object     *obj_desc;
-	acpi_operand_object     *previous_obj_desc;
-	acpi_object_type8       obj_type = ACPI_TYPE_ANY;
-	u8                      flags;
+	acpi_operand_object     *last_obj_desc;
+	acpi_object_type        object_type = ACPI_TYPE_ANY;
 
 
-	FUNCTION_TRACE ("Ns_attach_object");
+	ACPI_FUNCTION_TRACE ("Ns_attach_object");
 
 
 	/*
 	 * Parameter validation
 	 */
-	if (!acpi_gbl_root_node) {
-		/* Name space not initialized  */
-
-		REPORT_ERROR (("Ns_attach_object: Namespace not initialized\n"));
-		return_ACPI_STATUS (AE_NO_NAMESPACE);
-	}
-
 	if (!node) {
 		/* Invalid handle */
 
-		REPORT_ERROR (("Ns_attach_object: Null Named_obj handle\n"));
+		ACPI_REPORT_ERROR (("Ns_attach_object: Null Named_obj handle\n"));
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
 	if (!object && (ACPI_TYPE_ANY != type)) {
 		/* Null object */
 
-		REPORT_ERROR (("Ns_attach_object: Null object, but type not ACPI_TYPE_ANY\n"));
+		ACPI_REPORT_ERROR (("Ns_attach_object: Null object, but type not ACPI_TYPE_ANY\n"));
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-	if (!VALID_DESCRIPTOR_TYPE (node, ACPI_DESC_TYPE_NAMED)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (node) != ACPI_DESC_TYPE_NAMED) {
 		/* Not a name handle */
 
-		REPORT_ERROR (("Ns_attach_object: Invalid handle\n"));
+		ACPI_REPORT_ERROR (("Ns_attach_object: Invalid handle\n"));
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
@@ -108,42 +102,27 @@
 		return_ACPI_STATUS (AE_OK);
 	}
 
-
-	/* Get the current flags field of the Node */
-
-	flags = node->flags;
-	flags &= ~ANOBJ_AML_ATTACHMENT;
-
-
 	/* If null object, we will just install it */
 
 	if (!object) {
-		obj_desc = NULL;
-		obj_type = ACPI_TYPE_ANY;
+		obj_desc   = NULL;
+		object_type = ACPI_TYPE_ANY;
 	}
 
 	/*
 	 * If the source object is a namespace Node with an attached object,
 	 * we will use that (attached) object
 	 */
-	else if (VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_NAMED) &&
+	else if ((ACPI_GET_DESCRIPTOR_TYPE (object) == ACPI_DESC_TYPE_NAMED) &&
 			((acpi_namespace_node *) object)->object) {
 		/*
 		 * Value passed is a name handle and that name has a
 		 * non-null value.  Use that name's value and type.
 		 */
-		obj_desc = ((acpi_namespace_node *) object)->object;
-		obj_type = ((acpi_namespace_node *) object)->type;
-
-		/*
-		 * Copy appropriate flags
-		 */
-		if (((acpi_namespace_node *) object)->flags & ANOBJ_AML_ATTACHMENT) {
-			flags |= ANOBJ_AML_ATTACHMENT;
-		}
+		obj_desc   = ((acpi_namespace_node *) object)->object;
+		object_type = ((acpi_namespace_node *) object)->type;
 	}
 
-
 	/*
 	 * Otherwise, we will use the parameter object, but we must type
 	 * it first
@@ -154,37 +133,15 @@
 		/* If a valid type (non-ANY) was given, just use it */
 
 		if (ACPI_TYPE_ANY != type) {
-			obj_type = type;
+			object_type = type;
 		}
-
 		else {
-			/*
-			 * Cannot figure out the type -- set to Def_any which
-			 * will print as an error in the name table dump
-			 */
-			if (acpi_dbg_level > 0) {
-				DUMP_PATHNAME (node,
-					"Ns_attach_object confused: setting bogus type for ",
-					ACPI_LV_INFO, _COMPONENT);
-
-				if (VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_NAMED)) {
-					DUMP_PATHNAME (object, "name ", ACPI_LV_INFO, _COMPONENT);
-				}
-
-				else {
-					DUMP_PATHNAME (object, "object ", ACPI_LV_INFO, _COMPONENT);
-					DUMP_STACK_ENTRY (object);
-				}
-			}
-
-			obj_type = INTERNAL_TYPE_DEF_ANY;
+			object_type = INTERNAL_TYPE_DEF_ANY;
 		}
 	}
 
-
 	ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Installing %p into Node %p [%4.4s]\n",
-		obj_desc, node, (char*)&node->name));
-
+		obj_desc, node, (char *) &node->name));
 
 	/*
 	 * Must increment the new value's reference count
@@ -192,29 +149,28 @@
 	 */
 	acpi_ut_add_reference (obj_desc);
 
-	/* Save the existing object (if any) for deletion later */
+	/* Detach an existing attached object if present */
 
-	previous_obj_desc = node->object;
-
-	/* Install the object and set the type, flags */
-
-	node->object   = obj_desc;
-	node->type     = (u8) obj_type;
-	node->flags    |= flags;
+	if (node->object) {
+		acpi_ns_detach_object (node);
+	}
 
 
 	/*
-	 * Delete an existing attached object.
+	 * Handle objects with multiple descriptors - walk
+	 * to the end of the descriptor list
 	 */
-	if (previous_obj_desc) {
-		/* One for the attach to the Node */
+	last_obj_desc = obj_desc;
+	while (last_obj_desc->common.next_object) {
+		last_obj_desc = last_obj_desc->common.next_object;
+	}
 
-		acpi_ut_remove_reference (previous_obj_desc);
+	/* Install the object at the front of the object list */
 
-		/* Now delete */
+	last_obj_desc->common.next_object = node->object;
 
-		acpi_ut_remove_reference (previous_obj_desc);
-	}
+	node->type     = (u8) object_type;
+	node->object   = obj_desc;
 
 	return_ACPI_STATUS (AE_OK);
 }
@@ -241,20 +197,32 @@
 	acpi_operand_object     *obj_desc;
 
 
-	FUNCTION_TRACE ("Ns_detach_object");
+	ACPI_FUNCTION_TRACE ("Ns_detach_object");
 
 
 	obj_desc = node->object;
-	if (!obj_desc) {
+	if (!obj_desc   ||
+		(obj_desc->common.type == INTERNAL_TYPE_DATA)) {
 		return_VOID;
 	}
 
 	/* Clear the entry in all cases */
 
 	node->object = NULL;
+	if (ACPI_GET_DESCRIPTOR_TYPE (obj_desc) == ACPI_DESC_TYPE_INTERNAL) {
+		node->object = obj_desc->common.next_object;
+		if (node->object &&
+		   (node->object->common.type != INTERNAL_TYPE_DATA)) {
+			node->object = node->object->common.next_object;
+		}
+	}
+
+	/* Reset the node type to untyped */
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Object=%p Value=%p Name %4.4s\n",
-		node, obj_desc, (char*)&node->name));
+	node->type = ACPI_TYPE_ANY;
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Node %p [%4.4s] Object %p\n",
+		node, (char *) &node->name, obj_desc));
 
 	/* Remove one reference on the object (and all subobjects) */
 
@@ -274,21 +242,197 @@
  *
  ******************************************************************************/
 
-void *
+acpi_operand_object *
 acpi_ns_get_attached_object (
 	acpi_namespace_node     *node)
 {
-	FUNCTION_TRACE_PTR ("Ns_get_attached_object", node);
+	ACPI_FUNCTION_TRACE_PTR ("Ns_get_attached_object", node);
 
 
 	if (!node) {
-		/* handle invalid */
-
 		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Null Node ptr\n"));
 		return_PTR (NULL);
 	}
 
+	if (!node->object ||
+			((ACPI_GET_DESCRIPTOR_TYPE (node->object) != ACPI_DESC_TYPE_INTERNAL)  &&
+			 (ACPI_GET_DESCRIPTOR_TYPE (node->object) != ACPI_DESC_TYPE_NAMED))    ||
+		(node->object->common.type == INTERNAL_TYPE_DATA)) {
+		return_PTR (NULL);
+	}
+
 	return_PTR (node->object);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ns_get_secondary_object
+ *
+ * PARAMETERS:  Node             - Parent Node to be examined
+ *
+ * RETURN:      Current value of the object field from the Node whose
+ *              handle is passed
+ *
+ ******************************************************************************/
+
+acpi_operand_object *
+acpi_ns_get_secondary_object (
+	acpi_operand_object     *obj_desc)
+{
+	ACPI_FUNCTION_TRACE_PTR ("Acpi_ns_get_secondary_object", obj_desc);
+
+
+	if ((!obj_desc)                                  ||
+		(obj_desc->common.type == INTERNAL_TYPE_DATA) ||
+		(!obj_desc->common.next_object)              ||
+		(obj_desc->common.next_object->common.type == INTERNAL_TYPE_DATA)) {
+		return_PTR (NULL);
+	}
+
+	return_PTR (obj_desc->common.next_object);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ns_attach_data
+ *
+ * PARAMETERS:
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION:
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ns_attach_data (
+	acpi_namespace_node     *node,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    *data)
+{
+	acpi_operand_object     *prev_obj_desc;
+	acpi_operand_object     *obj_desc;
+	acpi_operand_object     *data_desc;
+
+
+	/* */
+	prev_obj_desc = NULL;
+	obj_desc = node->object;
+	while (obj_desc) {
+		if ((obj_desc->common.type == INTERNAL_TYPE_DATA) &&
+			(obj_desc->data.handler == handler)) {
+			return (AE_ALREADY_EXISTS);
+		}
+
+		prev_obj_desc = obj_desc;
+		obj_desc = obj_desc->common.next_object;
+	}
+
+
+	/* Create an internal object for the data */
+
+	data_desc = acpi_ut_create_internal_object (INTERNAL_TYPE_DATA);
+	if (!data_desc) {
+		return (AE_NO_MEMORY);
+	}
+
+	data_desc->data.handler = handler;
+	data_desc->data.pointer = data;
+
+
+	/* Install the data object */
+
+	if (prev_obj_desc) {
+		prev_obj_desc->common.next_object = data_desc;
+	}
+	else {
+		node->object = data_desc;
+	}
+
+	return (AE_OK);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ns_detach_data
+ *
+ * PARAMETERS:
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION:
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ns_detach_data (
+	acpi_namespace_node     *node,
+	ACPI_OBJECT_HANDLER     handler)
+{
+	acpi_operand_object     *obj_desc;
+	acpi_operand_object     *prev_obj_desc;
+
+
+	prev_obj_desc = NULL;
+	obj_desc = node->object;
+	while (obj_desc) {
+		if ((obj_desc->common.type == INTERNAL_TYPE_DATA) &&
+			(obj_desc->data.handler == handler)) {
+			if (prev_obj_desc) {
+				prev_obj_desc->common.next_object = obj_desc->common.next_object;
+			}
+			else {
+				node->object = obj_desc->common.next_object;
+			}
+
+			acpi_ut_remove_reference (obj_desc);
+			return (AE_OK);
+		}
+
+		prev_obj_desc = obj_desc;
+		obj_desc = obj_desc->common.next_object;
+	}
+
+	return (AE_NOT_FOUND);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ns_get_attached_data
+ *
+ * PARAMETERS:
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION:
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ns_get_attached_data (
+	acpi_namespace_node     *node,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    **data)
+{
+	acpi_operand_object     *obj_desc;
+
+
+	obj_desc = node->object;
+	while (obj_desc) {
+		if ((obj_desc->common.type == INTERNAL_TYPE_DATA) &&
+			(obj_desc->data.handler == handler)) {
+			*data = obj_desc->data.pointer;
+			return (AE_OK);
+		}
+
+		obj_desc = obj_desc->common.next_object;
+	}
+
+	return (AE_NOT_FOUND);
 }
 
 
diff -Nru a/drivers/acpi/namespace/nssearch.c b/drivers/acpi/namespace/nssearch.c
--- a/drivers/acpi/namespace/nssearch.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/acpi/namespace/nssearch.c	Fri Mar 15 17:51:04 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: nssearch - Namespace search
- *              $Revision: 75 $
+ *              $Revision: 83 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nssearch")
+	 ACPI_MODULE_NAME    ("nssearch")
 
 
 /*******************************************************************************
@@ -64,30 +64,29 @@
 acpi_ns_search_node (
 	u32                     target_name,
 	acpi_namespace_node     *node,
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_namespace_node     **return_node)
 {
 	acpi_namespace_node     *next_node;
 
 
-	FUNCTION_TRACE ("Ns_search_node");
+	ACPI_FUNCTION_TRACE ("Ns_search_node");
 
 
 #ifdef ACPI_DEBUG
 	if (ACPI_LV_NAMES & acpi_dbg_level) {
 		NATIVE_CHAR         *scope_name;
 
-		scope_name = acpi_ns_get_table_pathname (node);
+		scope_name = acpi_ns_get_external_pathname (node);
 		if (scope_name) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Searching %s [%p] For %4.4s (type %X)\n",
-				scope_name, node, (char*)&target_name, type));
+			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Searching %s [%p] For %4.4s (type %s)\n",
+				scope_name, node, (char *) &target_name, acpi_ut_get_type_name (type)));
 
 			ACPI_MEM_FREE (scope_name);
 		}
 	}
 #endif
 
-
 	/*
 	 * Search for name in this table, which is to say that we must search
 	 * for the name among the children of this object
@@ -123,14 +122,13 @@
 			}
 
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES,
-				"Name %4.4s (actual type %X) found at %p\n",
-				(char*)&target_name, next_node->type, next_node));
+				"Name %4.4s Type [%s] found at %p\n",
+				(char *) &target_name, acpi_ut_get_type_name (next_node->type), next_node));
 
 			*return_node = next_node;
 			return_ACPI_STATUS (AE_OK);
 		}
 
-
 		/*
 		 * The last entry in the list points back to the parent,
 		 * so a flag is used to indicate the end-of-list
@@ -146,11 +144,10 @@
 		next_node = next_node->peer;
 	}
 
-
 	/* Searched entire table, not found */
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Name %4.4s (type %X) not found at %p\n",
-		(char*)&target_name, type, next_node));
+		(char *) &target_name, type, next_node));
 
 	return_ACPI_STATUS (AE_NOT_FOUND);
 }
@@ -185,17 +182,17 @@
 acpi_ns_search_parent_tree (
 	u32                     target_name,
 	acpi_namespace_node     *node,
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_namespace_node     **return_node)
 {
 	acpi_status             status;
 	acpi_namespace_node     *parent_node;
 
 
-	FUNCTION_TRACE ("Ns_search_parent_tree");
+	ACPI_FUNCTION_TRACE ("Ns_search_parent_tree");
 
 
-	parent_node = acpi_ns_get_parent_object (node);
+	parent_node = acpi_ns_get_parent_node (node);
 
 	/*
 	 * If there is no parent (at the root) or type is "local", we won't be
@@ -205,33 +202,33 @@
 		(!parent_node)) {
 		if (!parent_node) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "[%4.4s] has no parent\n",
-				(char*)&target_name));
+				(char *) &target_name));
 		}
 
 		if (acpi_ns_local (type)) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "[%4.4s] type %X is local(no search)\n",
-				(char*)&target_name, type));
+				(char *) &target_name, type));
 		}
 
 		return_ACPI_STATUS (AE_NOT_FOUND);
 	}
 
-
 	/* Search the parent tree */
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Searching parent for %4.4s\n", (char*)&target_name));
+	ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "Searching parent for %4.4s\n", (char *) &target_name));
 
 	/*
 	 * Search parents until found the target or we have backed up to
 	 * the root
 	 */
 	while (parent_node) {
-		/* Search parent scope */
-		/* TBD: [Investigate] Why ACPI_TYPE_ANY? */
-
+		/*
+		 * Search parent scope.  Use TYPE_ANY because we don't care about the
+		 * object type at this point, we only care about the existence of
+		 * the actual name we are searching for.  Typechecking comes later.
+		 */
 		status = acpi_ns_search_node (target_name, parent_node,
 				   ACPI_TYPE_ANY, return_node);
-
 		if (ACPI_SUCCESS (status)) {
 			return_ACPI_STATUS (status);
 		}
@@ -240,10 +237,9 @@
 		 * Not found here, go up another level
 		 * (until we reach the root)
 		 */
-		parent_node = acpi_ns_get_parent_object (parent_node);
+		parent_node = acpi_ns_get_parent_node (parent_node);
 	}
 
-
 	/* Not found in parent tree */
 
 	return_ACPI_STATUS (AE_NOT_FOUND);
@@ -280,8 +276,8 @@
 	u32                     target_name,
 	acpi_walk_state         *walk_state,
 	acpi_namespace_node     *node,
-	operating_mode          interpreter_mode,
-	acpi_object_type8       type,
+	acpi_interpreter_mode   interpreter_mode,
+	acpi_object_type        type,
 	u32                     flags,
 	acpi_namespace_node     **return_node)
 {
@@ -289,7 +285,7 @@
 	acpi_namespace_node     *new_node;
 
 
-	FUNCTION_TRACE ("Ns_search_and_enter");
+	ACPI_FUNCTION_TRACE ("Ns_search_and_enter");
 
 
 	/* Parameter validation */
@@ -298,25 +294,23 @@
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Null param-  Table %p Name %X Return %p\n",
 			node, target_name, return_node));
 
-		REPORT_ERROR (("Ns_search_and_enter: bad (null) parameter\n"));
+		ACPI_REPORT_ERROR (("Ns_search_and_enter: bad (null) parameter\n"));
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	/* Name must consist of printable characters */
 
 	if (!acpi_ut_valid_acpi_name (target_name)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "*** Bad character in name: %08x *** \n",
 			target_name));
 
-		REPORT_ERROR (("Ns_search_and_enter: Bad character in ACPI Name\n"));
+		ACPI_REPORT_ERROR (("Ns_search_and_enter: Bad character in ACPI Name\n"));
 		return_ACPI_STATUS (AE_BAD_CHARACTER);
 	}
 
-
 	/* Try to find the name in the table specified by the caller */
 
-	*return_node = ENTRY_NOT_FOUND;
+	*return_node = ACPI_ENTRY_NOT_FOUND;
 	status = acpi_ns_search_node (target_name, node, type, return_node);
 	if (status != AE_NOT_FOUND) {
 		/*
@@ -324,8 +318,8 @@
 		 * return the error
 		 */
 		if ((status == AE_OK) &&
-			(flags & NS_ERROR_IF_FOUND)) {
-			status = AE_EXIST;
+			(flags & ACPI_NS_ERROR_IF_FOUND)) {
+			status = AE_ALREADY_EXISTS;
 		}
 
 		/*
@@ -335,9 +329,8 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/*
-	 * Not found in the table.  If we are NOT performing the
+	 * The name was not found.  If we are NOT performing the
 	 * first pass (name entry) of loading the namespace, search
 	 * the parent tree (all the way to the root if necessary.)
 	 * We don't want to perform the parent search when the
@@ -345,8 +338,8 @@
 	 * the search when namespace references are being resolved
 	 * (load pass 2) and during the execution phase.
 	 */
-	if ((interpreter_mode != IMODE_LOAD_PASS1) &&
-		(flags & NS_SEARCH_PARENT)) {
+	if ((interpreter_mode != ACPI_IMODE_LOAD_PASS1) &&
+		(flags & ACPI_NS_SEARCH_PARENT)) {
 		/*
 		 * Not found in table - search parent tree according
 		 * to ACPI specification
@@ -358,17 +351,15 @@
 		}
 	}
 
-
 	/*
 	 * In execute mode, just search, never add names.  Exit now.
 	 */
-	if (interpreter_mode == IMODE_EXECUTE) {
+	if (interpreter_mode == ACPI_IMODE_EXECUTE) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_NAMES, "%4.4s Not found in %p [Not adding]\n",
-			(char*)&target_name, node));
+			(char *) &target_name, node));
 
 		return_ACPI_STATUS (AE_NOT_FOUND);
 	}
-
 
 	/* Create the new named object */
 
diff -Nru a/drivers/acpi/namespace/nsutils.c b/drivers/acpi/namespace/nsutils.c
--- a/drivers/acpi/namespace/nsutils.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/namespace/nsutils.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: nsutils - Utilities for accessing ACPI namespace, accessing
  *                        parents and siblings and Scope manipulation
- *              $Revision: 92 $
+ *              $Revision: 104 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "actables.h"
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsutils")
+	 ACPI_MODULE_NAME    ("nsutils")
 
 
 /*******************************************************************************
@@ -87,19 +87,19 @@
  *
  ******************************************************************************/
 
-acpi_object_type8
+acpi_object_type
 acpi_ns_get_type (
 	acpi_namespace_node     *node)
 {
-	FUNCTION_TRACE ("Ns_get_type");
+	ACPI_FUNCTION_TRACE ("Ns_get_type");
 
 
 	if (!node) {
-		REPORT_WARNING (("Ns_get_type: Null Node ptr"));
+		ACPI_REPORT_WARNING (("Ns_get_type: Null Node ptr"));
 		return_VALUE (ACPI_TYPE_ANY);
 	}
 
-	return_VALUE (node->type);
+	return_VALUE ((acpi_object_type) node->type);
 }
 
 
@@ -116,19 +116,19 @@
 
 u32
 acpi_ns_local (
-	acpi_object_type8       type)
+	acpi_object_type        type)
 {
-	FUNCTION_TRACE ("Ns_local");
+	ACPI_FUNCTION_TRACE ("Ns_local");
 
 
 	if (!acpi_ut_valid_object_type (type)) {
 		/* Type code out of range  */
 
-		REPORT_WARNING (("Ns_local: Invalid Object Type\n"));
-		return_VALUE (NSP_NORMAL);
+		ACPI_REPORT_WARNING (("Ns_local: Invalid Object Type\n"));
+		return_VALUE (ACPI_NS_NORMAL);
 	}
 
-	return_VALUE ((u32) acpi_gbl_ns_properties[type] & NSP_LOCAL);
+	return_VALUE ((u32) acpi_gbl_ns_properties[type] & ACPI_NS_LOCAL);
 }
 
 
@@ -154,7 +154,7 @@
 	u32                     i;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	next_external_char = info->external_name;
@@ -175,7 +175,6 @@
 		info->fully_qualified = TRUE;
 		next_external_char++;
 	}
-
 	else {
 		/*
 		 * Handle Carat prefixes
@@ -234,7 +233,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE ("Ns_build_internal_name");
+	ACPI_FUNCTION_TRACE ("Ns_build_internal_name");
 
 
 	/* Setup the correct prefixes, counts, and pointers */
@@ -268,15 +267,13 @@
 			}
 		}
 
-		if (num_segments == 1) {
+		if (num_segments <= 1) {
 			result = &internal_name[i];
 		}
-
 		else if (num_segments == 2) {
 			internal_name[i] = AML_DUAL_NAME_PREFIX;
 			result = &internal_name[i+1];
 		}
-
 		else {
 			internal_name[i] = AML_MULTI_NAME_PREFIX_OP;
 			internal_name[i+1] = (char) num_segments;
@@ -295,11 +292,10 @@
 
 				result[i] = '_';
 			}
-
 			else {
 				/* Convert the character to uppercase and save it */
 
-				result[i] = (char) TOUPPER (*external_name);
+				result[i] = (char) ACPI_TOUPPER (*external_name);
 				external_name++;
 			}
 		}
@@ -317,7 +313,6 @@
 		result += ACPI_NAME_SIZE;
 	}
 
-
 	/* Terminate the string */
 
 	*result = 0;
@@ -360,7 +355,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ns_internalize_name");
+	ACPI_FUNCTION_TRACE ("Ns_internalize_name");
 
 
 	if ((!external_name)     ||
@@ -369,7 +364,6 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	/* Get the length of the new internal name */
 
 	info.external_name = external_name;
@@ -420,22 +414,21 @@
 {
 	u32                     prefix_length = 0;
 	u32                     names_index = 0;
-	u32                     names_count = 0;
+	u32                     num_segments = 0;
 	u32                     i = 0;
 	u32                     j = 0;
+	u32                     required_length;
 
 
-	FUNCTION_TRACE ("Ns_externalize_name");
+	ACPI_FUNCTION_TRACE ("Ns_externalize_name");
 
 
 	if (!internal_name_length   ||
 		!internal_name          ||
-		!converted_name_length  ||
 		!converted_name) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	/*
 	 * Check for a prefix (one '\' | one or more '^').
 	 */
@@ -464,36 +457,36 @@
 	 */
 	if (prefix_length < internal_name_length) {
 		switch (internal_name[prefix_length]) {
+		case AML_MULTI_NAME_PREFIX_OP:
 
-		/* <count> 4-byte names */
+			/* <count> 4-byte names */
 
-		case AML_MULTI_NAME_PREFIX_OP:
 			names_index = prefix_length + 2;
-			names_count = (u32) internal_name[prefix_length + 1];
+			num_segments = (u32) (u8) internal_name[prefix_length + 1];
 			break;
 
+		case AML_DUAL_NAME_PREFIX:
 
-		/* two 4-byte names */
+			/* Two 4-byte names */
 
-		case AML_DUAL_NAME_PREFIX:
 			names_index = prefix_length + 1;
-			names_count = 2;
+			num_segments = 2;
 			break;
 
+		case 0:
 
-		/* Null_name */
+			/* Null_name */
 
-		case 0:
 			names_index = 0;
-			names_count = 0;
+			num_segments = 0;
 			break;
 
+		default:
 
-		/* one 4-byte name */
+			/* one 4-byte name */
 
-		default:
 			names_index = prefix_length;
-			names_count = 1;
+			num_segments = 1;
 			break;
 		}
 	}
@@ -503,23 +496,22 @@
 	 * of the prefix, length of all object names, length of any required
 	 * punctuation ('.') between object names, plus the NULL terminator.
 	 */
-	*converted_name_length = prefix_length + (4 * names_count) +
-			   ((names_count > 0) ? (names_count - 1) : 0) + 1;
+	required_length = prefix_length + (4 * num_segments) +
+			   ((num_segments > 0) ? (num_segments - 1) : 0) + 1;
 
 	/*
 	 * Check to see if we're still in bounds.  If not, there's a problem
 	 * with Internal_name (invalid format).
 	 */
-	if (*converted_name_length > internal_name_length) {
-		REPORT_ERROR (("Ns_externalize_name: Invalid internal name\n"));
+	if (required_length > internal_name_length) {
+		ACPI_REPORT_ERROR (("Ns_externalize_name: Invalid internal name\n"));
 		return_ACPI_STATUS (AE_BAD_PATHNAME);
 	}
 
 	/*
 	 * Build Converted_name...
 	 */
-
-	(*converted_name) = ACPI_MEM_CALLOCATE (*converted_name_length);
+	*converted_name = ACPI_MEM_CALLOCATE (required_length);
 	if (!(*converted_name)) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
@@ -530,8 +522,8 @@
 		(*converted_name)[j++] = internal_name[i];
 	}
 
-	if (names_count > 0) {
-		for (i = 0; i < names_count; i++) {
+	if (num_segments > 0) {
+		for (i = 0; i < num_segments; i++) {
 			if (i > 0) {
 				(*converted_name)[j++] = '.';
 			}
@@ -543,6 +535,10 @@
 		}
 	}
 
+	if (converted_name_length) {
+		*converted_name_length = required_length;
+	}
+
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -557,6 +553,9 @@
  *
  * DESCRIPTION: Convert a namespace handle to a real Node
  *
+ * Note: Real integer handles allow for more verification
+ *       and keep all pointers within this subsystem.
+ *
  ******************************************************************************/
 
 acpi_namespace_node *
@@ -564,13 +563,11 @@
 	acpi_handle             handle)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
-	 * Simple implementation for now;
-	 * TBD: [Future] Real integer handles allow for more verification
-	 * and keep all pointers within this subsystem!
+	 * Simple implementation.
 	 */
 	if (!handle) {
 		return (NULL);
@@ -580,10 +577,9 @@
 		return (acpi_gbl_root_node);
 	}
 
-
 	/* We can at least attempt to verify the handle */
 
-	if (!VALID_DESCRIPTOR_TYPE (handle, ACPI_DESC_TYPE_NAMED)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (handle) != ACPI_DESC_TYPE_NAMED) {
 		return (NULL);
 	}
 
@@ -611,8 +607,6 @@
 
 	/*
 	 * Simple implementation for now;
-	 * TBD: [Future] Real integer handles allow for more verification
-	 * and keep all pointers within this subsystem!
 	 */
 	return ((acpi_handle) node);
 
@@ -654,7 +648,7 @@
 	acpi_namespace_node     *this_node;
 
 
-	FUNCTION_TRACE ("Ns_terminate");
+	ACPI_FUNCTION_TRACE ("Ns_terminate");
 
 
 	this_node = acpi_gbl_root_node;
@@ -702,25 +696,25 @@
 
 u32
 acpi_ns_opens_scope (
-	acpi_object_type8       type)
+	acpi_object_type        type)
 {
-	FUNCTION_TRACE_U32 ("Ns_opens_scope", type);
+	ACPI_FUNCTION_TRACE_U32 ("Ns_opens_scope", type);
 
 
 	if (!acpi_ut_valid_object_type (type)) {
 		/* type code out of range  */
 
-		REPORT_WARNING (("Ns_opens_scope: Invalid Object Type\n"));
-		return_VALUE (NSP_NORMAL);
+		ACPI_REPORT_WARNING (("Ns_opens_scope: Invalid Object Type %X\n", type));
+		return_VALUE (ACPI_NS_NORMAL);
 	}
 
-	return_VALUE (((u32) acpi_gbl_ns_properties[type]) & NSP_NEWSCOPE);
+	return_VALUE (((u32) acpi_gbl_ns_properties[type]) & ACPI_NS_NEWSCOPE);
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ns_get_node
+ * FUNCTION:    Acpi_ns_get_node_by_path
  *
  * PARAMETERS:  *Pathname   - Name to be found, in external (ASL) format. The
  *                            \ (backslash) and ^ (carat) prefixes, and the
@@ -729,6 +723,8 @@
  *                            root of the name space.  If Name is fully
  *                            qualified (first s8 is '\'), the passed value
  *                            of Scope will not be accessed.
+ *              Flags       - Used to indicate whether to perform upsearch or
+ *                            not.
  *              Return_node - Where the Node is returned
  *
  * DESCRIPTION: Look up a name relative to a given scope and return the
@@ -739,9 +735,10 @@
  ******************************************************************************/
 
 acpi_status
-acpi_ns_get_node (
+acpi_ns_get_node_by_path (
 	NATIVE_CHAR             *pathname,
 	acpi_namespace_node     *start_node,
+	u32                     flags,
 	acpi_namespace_node     **return_node)
 {
 	acpi_generic_state      scope_info;
@@ -749,20 +746,13 @@
 	NATIVE_CHAR             *internal_path = NULL;
 
 
-	FUNCTION_TRACE_PTR ("Ns_get_node", pathname);
+	ACPI_FUNCTION_TRACE_PTR ("Ns_get_node_by_path", pathname);
 
 
-	/* Ensure that the namespace has been initialized */
-
-	if (!acpi_gbl_root_node) {
-		return_ACPI_STATUS (AE_NO_NAMESPACE);
-	}
-
 	if (!pathname) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	/* Convert path to internal representation */
 
 	status = acpi_ns_internalize_name (pathname, &internal_path);
@@ -770,8 +760,12 @@
 		return_ACPI_STATUS (status);
 	}
 
+	/* Must lock namespace during lookup */
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Setup lookup scope (search starting point) */
 
@@ -780,20 +774,17 @@
 	/* Lookup the name in the namespace */
 
 	status = acpi_ns_lookup (&scope_info, internal_path,
-			 ACPI_TYPE_ANY, IMODE_EXECUTE,
-			 NS_NO_UPSEARCH | NS_DONT_OPEN_SCOPE,
+			 ACPI_TYPE_ANY, ACPI_IMODE_EXECUTE,
+			 (flags | ACPI_NS_DONT_OPEN_SCOPE),
 			 NULL, return_node);
-
 	if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%s, %s\n",
 				internal_path, acpi_format_exception (status)));
 	}
 
-
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-
 	/* Cleanup */
 
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	ACPI_MEM_FREE (internal_path);
 	return_ACPI_STATUS (status);
 }
@@ -820,16 +811,17 @@
 	acpi_namespace_node     *parent_node;
 
 
-	FUNCTION_TRACE ("Ns_find_parent_name");
+	ACPI_FUNCTION_TRACE ("Ns_find_parent_name");
 
 
 	if (child_node) {
 		/* Valid entry.  Get the parent Node */
 
-		parent_node = acpi_ns_get_parent_object (child_node);
+		parent_node = acpi_ns_get_parent_node (child_node);
 		if (parent_node) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "Parent of %p [%4.4s] is %p [%4.4s]\n",
-				child_node, (char*)&child_node->name, parent_node, (char*)&parent_node->name));
+				child_node, (char *) &child_node->name,
+				parent_node, (char *) &parent_node->name));
 
 			if (parent_node->name) {
 				return_VALUE (parent_node->name);
@@ -837,7 +829,7 @@
 		}
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "unable to find parent of %p (%4.4s)\n",
-			child_node, (char*)&child_node->name));
+			child_node, (char *) &child_node->name));
 	}
 
 	return_VALUE (ACPI_UNKNOWN_NAME);
@@ -883,7 +875,7 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ns_get_parent_object
+ * FUNCTION:    Acpi_ns_get_parent_node
  *
  * PARAMETERS:  Node       - Current table entry
  *
@@ -895,12 +887,10 @@
 
 
 acpi_namespace_node *
-acpi_ns_get_parent_object (
+acpi_ns_get_parent_node (
 	acpi_namespace_node     *node)
 {
-
-
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (!node) {
diff -Nru a/drivers/acpi/namespace/nswalk.c b/drivers/acpi/namespace/nswalk.c
--- a/drivers/acpi/namespace/nswalk.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/acpi/namespace/nswalk.c	Fri Mar 15 17:51:04 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: nswalk - Functions for walking the ACPI namespace
- *              $Revision: 26 $
+ *              $Revision: 32 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nswalk")
+	 ACPI_MODULE_NAME    ("nswalk")
 
 
 /*******************************************************************************
@@ -54,14 +54,14 @@
 
 acpi_namespace_node *
 acpi_ns_get_next_node (
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_namespace_node     *parent_node,
 	acpi_namespace_node     *child_node)
 {
 	acpi_namespace_node     *next_node = NULL;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (!child_node) {
@@ -138,7 +138,7 @@
 
 acpi_status
 acpi_ns_walk_namespace (
-	acpi_object_type8       type,
+	acpi_object_type        type,
 	acpi_handle             start_node,
 	u32                     max_depth,
 	u8                      unlock_before_callback,
@@ -149,11 +149,11 @@
 	acpi_status             status;
 	acpi_namespace_node     *child_node;
 	acpi_namespace_node     *parent_node;
-	acpi_object_type8        child_type;
+	acpi_object_type        child_type;
 	u32                     level;
 
 
-	FUNCTION_TRACE ("Ns_walk_namespace");
+	ACPI_FUNCTION_TRACE ("Ns_walk_namespace");
 
 
 	/* Special case for the namespace Root Node */
@@ -194,14 +194,20 @@
 				 * callback function
 				 */
 				if (unlock_before_callback) {
-					acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+					status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+					if (ACPI_FAILURE (status)) {
+						return_ACPI_STATUS (status);
+					}
 				}
 
 				status = user_function (child_node, level,
 						 context, return_value);
 
 				if (unlock_before_callback) {
-					acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+					status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+					if (ACPI_FAILURE (status)) {
+						return_ACPI_STATUS (status);
+					}
 				}
 
 				switch (status) {
@@ -216,14 +222,12 @@
 					/* Exit now, with OK status */
 
 					return_ACPI_STATUS (AE_OK);
-					break;
 
 				default:
 
 					/* All others are valid exceptions */
 
 					return_ACPI_STATUS (status);
-					break;
 				}
 			}
 
@@ -247,7 +251,6 @@
 				}
 			}
 		}
-
 		else {
 			/*
 			 * No more children of this node (Acpi_ns_get_next_node
@@ -256,7 +259,7 @@
 			 */
 			level--;
 			child_node = parent_node;
-			parent_node = acpi_ns_get_parent_object (parent_node);
+			parent_node = acpi_ns_get_parent_node (parent_node);
 		}
 	}
 
diff -Nru a/drivers/acpi/namespace/nsxfname.c b/drivers/acpi/namespace/nsxfname.c
--- a/drivers/acpi/namespace/nsxfname.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/namespace/nsxfname.c	Fri Mar 15 17:51:02 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: nsxfname - Public interfaces to the ACPI subsystem
  *                         ACPI Namespace oriented interfaces
- *              $Revision: 82 $
+ *              $Revision: 89 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -35,7 +35,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsxfname")
+	 ACPI_MODULE_NAME    ("nsxfname")
 
 
 /****************************************************************************
@@ -67,7 +67,7 @@
 	acpi_namespace_node     *prefix_node = NULL;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* Parameter Validation */
@@ -79,20 +79,26 @@
 	/* Convert a parent handle to a prefix node */
 
 	if (parent) {
-		acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+		status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+		if (ACPI_FAILURE (status)) {
+			return (status);
+		}
 
 		prefix_node = acpi_ns_map_handle_to_node (parent);
 		if (!prefix_node) {
-			acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+			(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 			return (AE_BAD_PARAMETER);
 		}
 
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		if (ACPI_FAILURE (status)) {
+			return (status);
+		}
 	}
 
 	/* Special case for root, since we can't search for it */
 
-	if (STRCMP (pathname, NS_ROOT_PATH) == 0) {
+	if (ACPI_STRCMP (pathname, ACPI_NS_ROOT_PATH) == 0) {
 		*ret_handle = acpi_ns_convert_entry_to_handle (acpi_gbl_root_node);
 		return (AE_OK);
 	}
@@ -100,7 +106,7 @@
 	/*
 	 *  Find the Node and convert to a handle
 	 */
-	status = acpi_ns_get_node (pathname, prefix_node, &node);
+	status = acpi_ns_get_node_by_path (pathname, prefix_node, ACPI_NS_NO_UPSEARCH, &node);
 
 	*ret_handle = NULL;
 	if (ACPI_SUCCESS (status)) {
@@ -117,7 +123,7 @@
  *
  * PARAMETERS:  Handle          - Handle to be converted to a pathname
  *              Name_type       - Full pathname or single segment
- *              Ret_path_ptr    - Buffer for returned path
+ *              Buffer          - Buffer for returned path
  *
  * RETURN:      Pointer to a string containing the fully qualified Name.
  *
@@ -131,63 +137,63 @@
 acpi_get_name (
 	acpi_handle             handle,
 	u32                     name_type,
-	acpi_buffer             *ret_path_ptr)
+	acpi_buffer             *buffer)
 {
 	acpi_status             status;
 	acpi_namespace_node     *node;
 
 
-	/* Buffer pointer must be valid always */
+	/* Parameter validation */
 
-	if (!ret_path_ptr || (name_type > ACPI_NAME_TYPE_MAX)) {
+	if (name_type > ACPI_NAME_TYPE_MAX) {
 		return (AE_BAD_PARAMETER);
 	}
 
-	/* Allow length to be zero and ignore the pointer */
-
-	if ((ret_path_ptr->length) &&
-	   (!ret_path_ptr->pointer)) {
-		return (AE_BAD_PARAMETER);
+	status = acpi_ut_validate_buffer (buffer);
+	if (ACPI_FAILURE (status)) {
+		return (status);
 	}
 
 	if (name_type == ACPI_FULL_PATHNAME) {
 		/* Get the full pathname (From the namespace root) */
 
-		status = acpi_ns_handle_to_pathname (handle, &ret_path_ptr->length,
-				   ret_path_ptr->pointer);
+		status = acpi_ns_handle_to_pathname (handle, buffer);
 		return (status);
 	}
 
 	/*
 	 * Wants the single segment ACPI name.
-	 * Validate handle and convert to an Node
+	 * Validate handle and convert to a namespace Node
 	 */
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
+
 	node = acpi_ns_map_handle_to_node (handle);
 	if (!node) {
 		status = AE_BAD_PARAMETER;
 		goto unlock_and_exit;
 	}
 
-	/* Check if name will fit in buffer */
+	/* Validate/Allocate/Clear caller buffer */
 
-	if (ret_path_ptr->length < PATH_SEGMENT_LENGTH) {
-		ret_path_ptr->length = PATH_SEGMENT_LENGTH;
-		status = AE_BUFFER_OVERFLOW;
+	status = acpi_ut_initialize_buffer (buffer, PATH_SEGMENT_LENGTH);
+	if (ACPI_FAILURE (status)) {
 		goto unlock_and_exit;
 	}
 
 	/* Just copy the ACPI name from the Node and zero terminate it */
 
-	STRNCPY (ret_path_ptr->pointer, (NATIVE_CHAR *) &node->name,
+	ACPI_STRNCPY (buffer->pointer, (NATIVE_CHAR *) &node->name,
 			 ACPI_NAME_SIZE);
-	((NATIVE_CHAR *) ret_path_ptr->pointer) [ACPI_NAME_SIZE] = 0;
+	((NATIVE_CHAR *) buffer->pointer) [ACPI_NAME_SIZE] = 0;
 	status = AE_OK;
 
 
 unlock_and_exit:
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return (status);
 }
 
@@ -226,18 +232,24 @@
 		return (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
 
 	node = acpi_ns_map_handle_to_node (handle);
 	if (!node) {
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 		return (AE_BAD_PARAMETER);
 	}
 
 	info->type      = node->type;
 	info->name      = node->name;
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
 
 	/*
 	 * If not a device, we are all done.
@@ -260,8 +272,7 @@
 
 	status = acpi_ut_execute_HID (node, &hid);
 	if (ACPI_SUCCESS (status)) {
-		STRNCPY (info->hardware_id, hid.buffer, sizeof(info->hardware_id));
-
+		ACPI_STRNCPY (info->hardware_id, hid.buffer, sizeof(info->hardware_id));
 		info->valid |= ACPI_VALID_HID;
 	}
 
@@ -269,8 +280,7 @@
 
 	status = acpi_ut_execute_UID (node, &uid);
 	if (ACPI_SUCCESS (status)) {
-		STRCPY (info->unique_id, uid.buffer);
-
+		ACPI_STRCPY (info->unique_id, uid.buffer);
 		info->valid |= ACPI_VALID_UID;
 	}
 
diff -Nru a/drivers/acpi/namespace/nsxfobj.c b/drivers/acpi/namespace/nsxfobj.c
--- a/drivers/acpi/namespace/nsxfobj.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/acpi/namespace/nsxfobj.c	Fri Mar 15 17:51:00 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: nsxfobj - Public interfaces to the ACPI subsystem
  *                         ACPI Object oriented interfaces
- *              $Revision: 95 $
+ *              $Revision: 108 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 
 
 #define _COMPONENT          ACPI_NAMESPACE
-	 MODULE_NAME         ("nsxfobj")
+	 ACPI_MODULE_NAME    ("nsxfobj")
 
 
 /*******************************************************************************
@@ -65,12 +65,11 @@
 	acpi_status             status;
 	acpi_operand_object     **internal_params = NULL;
 	acpi_operand_object     *internal_return_obj = NULL;
-	u32                     buffer_space_needed;
-	u32                     user_buffer_length;
+	ACPI_SIZE               buffer_space_needed;
 	u32                     i;
 
 
-	FUNCTION_TRACE ("Acpi_evaluate_object");
+	ACPI_FUNCTION_TRACE ("Acpi_evaluate_object");
 
 
 	/*
@@ -83,12 +82,12 @@
 		 * Allocate a new parameter block for the internal objects
 		 * Add 1 to count to allow for null terminated internal list
 		 */
-		internal_params = ACPI_MEM_CALLOCATE ((external_params->count + 1) * sizeof (void *));
+		internal_params = ACPI_MEM_CALLOCATE ((external_params->count + 1) *
+				  sizeof (void *));
 		if (!internal_params) {
 			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
-
 		/*
 		 * Convert each external object in the list to an
 		 * internal object
@@ -96,7 +95,6 @@
 		for (i = 0; i < external_params->count; i++) {
 			status = acpi_ut_copy_eobject_to_iobject (&external_params->pointer[i],
 					 &internal_params[i]);
-
 			if (ACPI_FAILURE (status)) {
 				acpi_ut_delete_internal_object_list (internal_params);
 				return_ACPI_STATUS (status);
@@ -105,7 +103,6 @@
 		internal_params[external_params->count] = NULL;
 	}
 
-
 	/*
 	 * Three major cases:
 	 * 1) Fully qualified pathname
@@ -117,9 +114,9 @@
 		/*
 		 *  The path is fully qualified, just evaluate by name
 		 */
-		status = acpi_ns_evaluate_by_name (pathname, internal_params, &internal_return_obj);
+		status = acpi_ns_evaluate_by_name (pathname, internal_params,
+				 &internal_return_obj);
 	}
-
 	else if (!handle) {
 		/*
 		 * A handle is optional iff a fully qualified pathname
@@ -127,16 +124,16 @@
 		 * qualified names above, this is an error
 		 */
 		if (!pathname) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Both Handle and Pathname are NULL\n"));
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Both Handle and Pathname are NULL\n"));
 		}
-
 		else {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Handle is NULL and Pathname is relative\n"));
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Handle is NULL and Pathname is relative\n"));
 		}
 
 		status = AE_BAD_PARAMETER;
 	}
-
 	else {
 		/*
 		 * We get here if we have a handle -- and if we have a
@@ -148,15 +145,15 @@
 			 * The null pathname case means the handle is for
 			 * the actual object to be evaluated
 			 */
-			status = acpi_ns_evaluate_by_handle (handle, internal_params, &internal_return_obj);
+			status = acpi_ns_evaluate_by_handle (handle, internal_params,
+					  &internal_return_obj);
 		}
-
 		else {
 		   /*
 			* Both a Handle and a relative Pathname
 			*/
 			status = acpi_ns_evaluate_relative (handle, pathname, internal_params,
-					 &internal_return_obj);
+					  &internal_return_obj);
 		}
 	}
 
@@ -165,26 +162,23 @@
 	 * If we are expecting a return value, and all went well above,
 	 * copy the return value to an external object.
 	 */
-
 	if (return_buffer) {
-		user_buffer_length = return_buffer->length;
-		return_buffer->length = 0;
-
-		if (internal_return_obj) {
-			if (VALID_DESCRIPTOR_TYPE (internal_return_obj, ACPI_DESC_TYPE_NAMED)) {
+		if (!internal_return_obj) {
+			return_buffer->length = 0;
+		}
+		else {
+			if (ACPI_GET_DESCRIPTOR_TYPE (internal_return_obj) == ACPI_DESC_TYPE_NAMED) {
 				/*
-				 * If we got an Node as a return object,
-				 * this means the object we are evaluating
-				 * has nothing interesting to return (such
-				 * as a mutex, etc.)  We return an error
-				 * because these types are essentially
-				 * unsupported by this interface.  We
-				 * don't check up front because this makes
-				 * it easier to add support for various
-				 * types at a later date if necessary.
+				 * If we received a NS Node as a return object, this means that
+				 * the object we are evaluating has nothing interesting to
+				 * return (such as a mutex, etc.)  We return an error because
+				 * these types are essentially unsupported by this interface.
+				 * We don't check up front because this makes it easier to add
+				 * support for various types at a later date if necessary.
 				 */
 				status = AE_TYPE;
-				internal_return_obj = NULL; /* No need to delete an Node */
+				internal_return_obj = NULL; /* No need to delete a NS Node */
+				return_buffer->length = 0;
 			}
 
 			if (ACPI_SUCCESS (status)) {
@@ -195,38 +189,29 @@
 				status = acpi_ut_get_object_size (internal_return_obj,
 						   &buffer_space_needed);
 				if (ACPI_SUCCESS (status)) {
-					/*
-					 * Check if there is enough room in the
-					 * caller's buffer
-					 */
-					if (user_buffer_length < buffer_space_needed) {
+					/* Validate/Allocate/Clear caller buffer */
+
+					status = acpi_ut_initialize_buffer (return_buffer, buffer_space_needed);
+					if (ACPI_FAILURE (status)) {
 						/*
-						 * Caller's buffer is too small, can't
-						 * give him partial results fail the call
-						 * but return the buffer size needed
+						 * Caller's buffer is too small or a new one can't be allocated
 						 */
 						ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-							"Needed buffer size %X, received %X\n",
-							buffer_space_needed, user_buffer_length));
-
-						return_buffer->length = buffer_space_needed;
-						status = AE_BUFFER_OVERFLOW;
+							"Needed buffer size %X, %s\n",
+							buffer_space_needed, acpi_format_exception (status)));
 					}
-
 					else {
 						/*
 						 *  We have enough space for the object, build it
 						 */
 						status = acpi_ut_copy_iobject_to_eobject (internal_return_obj,
 								  return_buffer);
-						return_buffer->length = buffer_space_needed;
 					}
 				}
 			}
 		}
 	}
 
-
 	/* Delete the return and parameter objects */
 
 	if (internal_return_obj) {
@@ -275,7 +260,7 @@
 	acpi_handle             child,
 	acpi_handle             *ret_handle)
 {
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 	acpi_namespace_node     *node;
 	acpi_namespace_node     *parent_node = NULL;
 	acpi_namespace_node     *child_node = NULL;
@@ -287,7 +272,10 @@
 		return (AE_BAD_PARAMETER);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
 
 	/* If null handle, use the parent */
 
@@ -300,10 +288,8 @@
 			goto unlock_and_exit;
 		}
 	}
-
-	/* Non-null handle, ignore the parent */
-
 	else {
+		/* Non-null handle, ignore the parent */
 		/* Convert and validate the handle */
 
 		child_node = acpi_ns_map_handle_to_node (child);
@@ -313,11 +299,9 @@
 		}
 	}
 
-
 	/* Internal function does the real work */
 
-	node = acpi_ns_get_next_node ((acpi_object_type8) type,
-			   parent_node, child_node);
+	node = acpi_ns_get_next_node (type, parent_node, child_node);
 	if (!node) {
 		status = AE_NOT_FOUND;
 		goto unlock_and_exit;
@@ -330,7 +314,7 @@
 
 unlock_and_exit:
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return (status);
 }
 
@@ -354,6 +338,7 @@
 	acpi_object_type        *ret_type)
 {
 	acpi_namespace_node     *node;
+	acpi_status             status;
 
 
 	/* Parameter Validation */
@@ -371,21 +356,24 @@
 		return (AE_OK);
 	}
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
 
 	/* Convert and validate the handle */
 
 	node = acpi_ns_map_handle_to_node (handle);
 	if (!node) {
-		acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+		(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 		return (AE_BAD_PARAMETER);
 	}
 
 	*ret_type = node->type;
 
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-	return (AE_OK);
+	status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	return (status);
 }
 
 
@@ -409,7 +397,7 @@
 	acpi_handle             *ret_handle)
 {
 	acpi_namespace_node     *node;
-	acpi_status             status = AE_OK;
+	acpi_status             status;
 
 
 	if (!ret_handle) {
@@ -422,8 +410,10 @@
 		return (AE_NULL_ENTRY);
 	}
 
-
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
 
 	/* Convert and validate the handle */
 
@@ -433,22 +423,21 @@
 		goto unlock_and_exit;
 	}
 
-
 	/* Get the parent entry */
 
 	*ret_handle =
-		acpi_ns_convert_entry_to_handle (acpi_ns_get_parent_object (node));
+		acpi_ns_convert_entry_to_handle (acpi_ns_get_parent_node (node));
 
 	/* Return exeption if parent is null */
 
-	if (!acpi_ns_get_parent_object (node)) {
+	if (!acpi_ns_get_parent_node (node)) {
 		status = AE_NULL_ENTRY;
 	}
 
 
 unlock_and_exit:
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return (status);
 }
 
@@ -495,7 +484,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_walk_namespace");
+	ACPI_FUNCTION_TRACE ("Acpi_walk_namespace");
 
 
 	/* Parameter validation */
@@ -512,13 +501,15 @@
 	 * to the user function - since this function
 	 * must be allowed to make Acpi calls itself.
 	 */
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
-	status = acpi_ns_walk_namespace ((acpi_object_type8) type, start_object,
-			  max_depth, NS_WALK_UNLOCK, user_function, context,
-			  return_value);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ns_walk_namespace (type, start_object, max_depth, ACPI_NS_WALK_UNLOCK,
+			  user_function, context, return_value);
 
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
 
@@ -547,15 +538,23 @@
 	acpi_status             status;
 	acpi_namespace_node     *node;
 	u32                     flags;
-	acpi_device_id          device_id;
+	acpi_device_id          hid;
+	acpi_device_id          cid;
 	acpi_get_devices_info   *info;
 
 
 	info = context;
 
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
+
 	node = acpi_ns_map_handle_to_node (obj_handle);
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
 
 	if (!node) {
 		return (AE_BAD_PARAMETER);
@@ -570,25 +569,36 @@
 	}
 
 	if (!(flags & 0x01)) {
-		/* don't return at the device or children of the device if not there */
+		/* Don't return at the device or children of the device if not there */
 		return (AE_CTRL_DEPTH);
 	}
 
 	/*
-	 * Filter based on device HID
+	 * Filter based on device HID & CID
 	 */
 	if (info->hid != NULL) {
-		status = acpi_ut_execute_HID (node, &device_id);
+		status = acpi_ut_execute_HID (node, &hid);
 		if (status == AE_NOT_FOUND) {
 			return (AE_OK);
 		}
-
 		else if (ACPI_FAILURE (status)) {
 			return (AE_CTRL_DEPTH);
 		}
 
-		if (STRNCMP (device_id.buffer, info->hid, sizeof (device_id.buffer)) != 0) {
-			return (AE_OK);
+		if (ACPI_STRNCMP (hid.buffer, info->hid, sizeof (hid.buffer)) != 0) {
+			status = acpi_ut_execute_CID (node, &cid);
+			if (status == AE_NOT_FOUND) {
+				return (AE_OK);
+			}
+			else if (ACPI_FAILURE (status)) {
+				return (AE_CTRL_DEPTH);
+			}
+
+			/* TBD: Handle CID packages */
+
+			if (ACPI_STRNCMP (cid.buffer, info->hid, sizeof (cid.buffer)) != 0) {
+				return (AE_OK);
+			}
 		}
 	}
 
@@ -633,7 +643,7 @@
 	acpi_get_devices_info   info;
 
 
-	FUNCTION_TRACE ("Acpi_get_devices");
+	ACPI_FUNCTION_TRACE ("Acpi_get_devices");
 
 
 	/* Parameter validation */
@@ -656,14 +666,170 @@
 	 * to the user function - since this function
 	 * must be allowed to make Acpi calls itself.
 	 */
-	acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	status = acpi_ns_walk_namespace (ACPI_TYPE_DEVICE,
 			   ACPI_ROOT_OBJECT, ACPI_UINT32_MAX,
-			   NS_WALK_UNLOCK,
+			   ACPI_NS_WALK_UNLOCK,
 			   acpi_ns_get_device_callback, &info,
 			   return_value);
 
-	acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
-
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
 	return_ACPI_STATUS (status);
 }
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_attach_data
+ *
+ * PARAMETERS:
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION:
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_attach_data (
+	acpi_handle             obj_handle,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    *data)
+{
+	acpi_namespace_node     *node;
+	acpi_status             status;
+
+
+	/* Parameter validation */
+
+	if (!obj_handle ||
+		!handler    ||
+		!data) {
+		return (AE_BAD_PARAMETER);
+	}
+
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
+
+	/* Convert and validate the handle */
+
+	node = acpi_ns_map_handle_to_node (obj_handle);
+	if (!node) {
+		status = AE_BAD_PARAMETER;
+		goto unlock_and_exit;
+	}
+
+	status = acpi_ns_attach_data (node, handler, data);
+
+unlock_and_exit:
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	return (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_detach_data
+ *
+ * PARAMETERS:
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION:
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_detach_data (
+	acpi_handle             obj_handle,
+	ACPI_OBJECT_HANDLER     handler)
+{
+	acpi_namespace_node     *node;
+	acpi_status             status;
+
+
+	/* Parameter validation */
+
+	if (!obj_handle ||
+		!handler) {
+		return (AE_BAD_PARAMETER);
+	}
+
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
+
+	/* Convert and validate the handle */
+
+	node = acpi_ns_map_handle_to_node (obj_handle);
+	if (!node) {
+		status = AE_BAD_PARAMETER;
+		goto unlock_and_exit;
+	}
+
+	status = acpi_ns_detach_data (node, handler);
+
+unlock_and_exit:
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	return (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_get_data
+ *
+ * PARAMETERS:
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION:
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_get_data (
+	acpi_handle             obj_handle,
+	ACPI_OBJECT_HANDLER     handler,
+	void                    **data)
+{
+	acpi_namespace_node     *node;
+	acpi_status             status;
+
+
+	/* Parameter validation */
+
+	if (!obj_handle ||
+		!handler    ||
+		!data) {
+		return (AE_BAD_PARAMETER);
+	}
+
+	status = acpi_ut_acquire_mutex (ACPI_MTX_NAMESPACE);
+	if (ACPI_FAILURE (status)) {
+		return (status);
+	}
+
+	/* Convert and validate the handle */
+
+	node = acpi_ns_map_handle_to_node (obj_handle);
+	if (!node) {
+		status = AE_BAD_PARAMETER;
+		goto unlock_and_exit;
+	}
+
+	status = acpi_ns_get_attached_data (node, handler, data);
+
+unlock_and_exit:
+	(void) acpi_ut_release_mutex (ACPI_MTX_NAMESPACE);
+	return (status);
+}
+
+
diff -Nru a/drivers/acpi/os.c b/drivers/acpi/os.c
--- a/drivers/acpi/os.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,920 +0,0 @@
-/******************************************************************************
- * 
- * Module Name: os.c - Linux OSL functions
- *		$Revision: 49 $
- *
- *****************************************************************************/
-
-/*
- *  os.c - OS-dependent functions
- *
- *  Copyright (C) 2000 Andrew Henroid
- *  Copyright (C) 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-/* Changes
- *
- * Christopher Liebman <liebman@sponsera.com> 2001-5-15
- * - Fixed improper kernel_thread parameters 
- */
-
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-#include <linux/pci.h>
-#include <linux/interrupt.h>
-#include <linux/kmod.h>
-#include <linux/delay.h>
-#include <asm/io.h>
-#include <acpi.h>
-
-#ifdef CONFIG_ACPI_EFI
-#include <asm/efi.h>
-#endif
-
-#ifdef _IA64
-#include <asm/hw_irq.h>
-#endif 
-
-#define _COMPONENT	ACPI_OS_SERVICES
-	MODULE_NAME	("os")
-
-typedef struct 
-{
-    OSD_EXECUTION_CALLBACK  function;
-    void		    *context;
-} ACPI_OS_DPC;
-
-
-/*****************************************************************************
- *			       Debugger Stuff
- *****************************************************************************/
-
-#ifdef ENABLE_DEBUGGER
-
-#include <linux/kdb.h>
-
-/* stuff for debugger support */
-int acpi_in_debugger = 0;
-extern NATIVE_CHAR line_buf[80];
-
-#endif
-
-
-/*****************************************************************************
- *				    Globals
- *****************************************************************************/
-
-static int acpi_irq_irq = 0;
-static OSD_HANDLER acpi_irq_handler = NULL;
-static void *acpi_irq_context = NULL;
-
-
-/******************************************************************************
- *				   Functions
- *****************************************************************************/
-
-acpi_status
-acpi_os_initialize(void)
-{
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_terminate(void)
-{
-	if (acpi_irq_handler) {
-		acpi_os_remove_interrupt_handler(acpi_irq_irq,
-						 acpi_irq_handler);
-	}
-
-	return AE_OK;
-}
-
-s32
-acpi_os_printf(const NATIVE_CHAR *fmt,...)
-{
-	s32 size;
-	va_list args;
-	va_start(args, fmt);
-	size = acpi_os_vprintf(fmt, args);
-	va_end(args);
-
-	return size;
-}
-
-s32
-acpi_os_vprintf(const NATIVE_CHAR *fmt, va_list args)
-{
-	static char buffer[512];
-	int size = vsprintf(buffer, fmt, args);
-
-#ifdef ENABLE_DEBUGGER
-	if (acpi_in_debugger) {
-		kdb_printf("%s", buffer);
-	} else {
-		printk("%s", buffer);
-	}
-#else
-	printk("%s", buffer);
-#endif
-
-	return size;
-}
-
-void *
-acpi_os_allocate(u32 size)
-{
-	return kmalloc(size, GFP_KERNEL);
-}
-
-void *
-acpi_os_callocate(u32 size)
-{
-	void *ptr = acpi_os_allocate(size);
-	if (ptr)
-		memset(ptr, 0, size);
-
-	return ptr;
-}
-
-void
-acpi_os_free(void *ptr)
-{
-	kfree(ptr);
-}
-
-
-acpi_status
-acpi_os_get_root_pointer(u32 flags, ACPI_PHYSICAL_ADDRESS *phys_addr)
-{
-#ifndef CONFIG_ACPI_EFI
-	if (ACPI_FAILURE(acpi_find_root_pointer(flags, phys_addr))) {
-		printk(KERN_ERR "ACPI: System description tables not found\n");
-		return AE_ERROR;
-	}
-#else /*CONFIG_ACPI_EFI*/
-	if (efi.acpi20)
-		*phys_addr = (ACPI_PHYSICAL_ADDRESS) efi.acpi20;
-	else if (efi.acpi)
-		*phys_addr = (ACPI_PHYSICAL_ADDRESS) efi.acpi;
-	else {
-		printk(KERN_ERR "ACPI: System description tables not found\n");
-		*phys_addr = NULL;
-		return AE_ERROR;
-	}
-#endif /*CONFIG_ACPI_EFI*/
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_map_memory(ACPI_PHYSICAL_ADDRESS phys, u32 size, void **virt)
-{
-	if (phys > ULONG_MAX) {
-		printk(KERN_ERR "ACPI: Cannot map memory that high\n");
-		return AE_ERROR;
-	}
-
-	*virt = ioremap((unsigned long) phys, size);
-	if (!*virt)
-		return AE_ERROR;
-
-	return AE_OK;
-}
-
-void
-acpi_os_unmap_memory(void *virt, u32 size)
-{
-	iounmap(virt);
-}
-
-acpi_status
-acpi_os_get_physical_address(void *virt, ACPI_PHYSICAL_ADDRESS *phys)
-{
-	if(!phys || !virt)
-		return AE_BAD_PARAMETER;
-
-	*phys = virt_to_phys(virt);
-
-	return AE_OK;
-}
-
-static void
-acpi_irq(int irq, void *dev_id, struct pt_regs *regs)
-{
-	(*acpi_irq_handler)(acpi_irq_context);
-}
-
-acpi_status
-acpi_os_install_interrupt_handler(u32 irq, OSD_HANDLER handler, void *context)
-{
-#ifdef _IA64
-	irq = isa_irq_to_vector(irq);
-#endif /*_IA64*/
-	acpi_irq_irq = irq;
-	acpi_irq_handler = handler;
-	acpi_irq_context = context;
-	if (request_irq(irq,
-			acpi_irq,
-			SA_SHIRQ,
-			"acpi",
-			acpi_irq)) {
-		printk(KERN_ERR "ACPI: SCI (IRQ%d) allocation failed\n", irq);
-		return AE_ERROR;
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_remove_interrupt_handler(u32 irq, OSD_HANDLER handler)
-{
-	if (acpi_irq_handler) {
-#ifdef _IA64
-		irq = isa_irq_to_vector(irq);
-#endif /*_IA64*/
-		free_irq(irq, acpi_irq);
-		acpi_irq_handler = NULL;
-	}
-
-	return AE_OK;
-}
-
-/*
- * Running in interpreter thread context, safe to sleep
- */
-
-void
-acpi_os_sleep(u32 sec, u32 ms)
-{
-	current->state = TASK_INTERRUPTIBLE;
-	schedule_timeout(HZ * sec + (ms * HZ) / 1000);
-}
-
-void
-acpi_os_stall(u32 us)
-{
-	if (us > 10000) {
-		mdelay(us / 1000);
-	}
-	else {
-		udelay(us);
-	}
-}
-
-acpi_status
-acpi_os_read_port(
-	ACPI_IO_ADDRESS	port,
-	void		*value,
-	u32		width)
-{
-	u32 dummy;
-
-	if (!value)
-		value = &dummy;
-
-	switch (width)
-	{
-	case 8:
-		*(u8*)  value = inb(port);
-		break;
-	case 16:
-		*(u16*) value = inw(port);
-		break;
-	case 32:
-		*(u32*) value = inl(port);
-		break;
-	default:
-		BUG();
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_write_port(
-	ACPI_IO_ADDRESS	port,
-	NATIVE_UINT	value,
-	u32		width)
-{
-	switch (width)
-	{
-	case 8:
-		outb(value, port);
-		break;
-	case 16:
-		outw(value, port);
-		break;
-	case 32:
-		outl(value, port);
-		break;
-	default:
-		BUG();
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_read_memory(
-	ACPI_PHYSICAL_ADDRESS	phys_addr,
-	void			*value,
-	u32			width)
-{
-	u32 dummy;
-
-	if (!value)
-		value = &dummy;
-
-	switch (width)
-	{
-	case 8:
-		*(u8*) value = *(u8*) phys_to_virt(phys_addr);
-		break;
-	case 16:
-		*(u16*) value = *(u16*) phys_to_virt(phys_addr);
-		break;
-	case 32:
-		*(u32*) value = *(u32*) phys_to_virt(phys_addr);
-		break;
-	default:
-		BUG();
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_write_memory(
-	ACPI_PHYSICAL_ADDRESS	phys_addr,
-	u32			value,
-	u32			width)
-{
-	switch (width)
-	{
-	case 8:
-		*(u8*) phys_to_virt(phys_addr) = value;
-		break;
-	case 16:
-		*(u16*) phys_to_virt(phys_addr) = value;
-		break;
-	case 32:
-		*(u32*) phys_to_virt(phys_addr) = value;
-		break;
-	default:
-		BUG();
-	}
-
-	return AE_OK;
-}
-
-
-#ifdef CONFIG_ACPI_PCI
-
-/* Architecture-dependent low-level PCI configuration access functions. */
-extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *val);
-extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 val);
-
-acpi_status
-acpi_os_read_pci_configuration (
-	acpi_pci_id             *pci_id,
-	u32                     reg,
-	void                    *value,
-	u32                     width)
-{
-	int			result = 0;
-	if (!value)
-		return AE_ERROR;
-
-	switch (width)
-	{
-	case 8:
-		result = pci_config_read(pci_id->segment, pci_id->bus, 
-			pci_id->device, pci_id->function, reg, 1, value);
-		break;
-	case 16:
-		result = pci_config_read(pci_id->segment, pci_id->bus, 
-			pci_id->device, pci_id->function, reg, 2, value);
-		break;
-	case 32:
-		result = pci_config_read(pci_id->segment, pci_id->bus, 
-			pci_id->device, pci_id->function, reg, 4, value);
-		break;
-	default:
-		BUG();
-	}
-
-	return (result ? AE_ERROR : AE_OK);
-}
-
-acpi_status
-acpi_os_write_pci_configuration (
-	acpi_pci_id             *pci_id,
-	u32                     reg,
-	NATIVE_UINT             value,
-	u32                     width)
-{
-	int			result = 0;
-
-	switch (width)
-	{
-	case 8:
-		result = pci_config_write(pci_id->segment, pci_id->bus, 
-			pci_id->device, pci_id->function, reg, 1, value);
-		break;
-	case 16:
-		result = pci_config_write(pci_id->segment, pci_id->bus, 
-			pci_id->device, pci_id->function, reg, 2, value);
-		break;
-	case 32:
-		result = pci_config_write(pci_id->segment, pci_id->bus, 
-			pci_id->device, pci_id->function, reg, 4, value);
-		break;
-	default:
-		BUG();
-	}
-
-	return (result ? AE_ERROR : AE_OK);
-}
-
-#else /*CONFIG_ACPI_PCI*/
-
-acpi_status
-acpi_os_read_pci_configuration (
-	acpi_pci_id	*pci_id,
-	u32		reg,
-	void		*value,
-	u32		width)
-{
-	int devfn = PCI_DEVFN(pci_id->device, pci_id->function);
-	struct pci_dev *dev = pci_find_slot(pci_id->bus, devfn);
-
-	if (!value || !dev)
-		return AE_ERROR;
-
-	switch (width)
-	{
-	case 8:
-		if (pci_read_config_byte(dev, reg, (u8*) value))
-			return AE_ERROR;
-		break;
-	case 16:
-		if (pci_read_config_word(dev, reg, (u16*) value))
-			return AE_ERROR;
-		break;
-	case 32:
-		if (pci_read_config_dword(dev, reg, (u32*) value))
-			return AE_ERROR;
-		break;
-	default:
-		BUG();
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_write_pci_configuration (
-	acpi_pci_id	*pci_id,
-	u32		reg,
-	u32		value,
-	u32		width)
-{
-	int devfn = PCI_DEVFN(pci_id->device, pci_id->function);
-	struct pci_dev *dev = pci_find_slot(pci_id->bus, devfn);
-
-	if (!dev)
-		return AE_ERROR;
-
-	switch (width)
-	{
-	case 8:
-		if (pci_write_config_byte(dev, reg, value))
-			return AE_ERROR;
-		break;
-	case 16:
-		if (pci_write_config_word(dev, reg, value))
-			return AE_ERROR;
-		break;
-	case 32:
-		if (pci_write_config_dword(dev, reg, value))
-			return AE_ERROR;
-		break;
-	default:
-		BUG();
-	}
-
-	return AE_OK;
-}
-
-#endif /*CONFIG_ACPI_PCI*/
-
-
-acpi_status
-acpi_os_load_module (
-	char *module_name)
-{
-	PROC_NAME("acpi_os_load_module");
-
-	if (!module_name)
-		return AE_BAD_PARAMETER;
-
-	if (0 > request_module(module_name)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to load module [%s].\n", module_name));
-		return AE_ERROR;
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_unload_module (
-	char *module_name)
-{
-	if (!module_name)
-		return AE_BAD_PARAMETER;
-
-	/* TODO: How on Linux? */
-	/* this is done automatically for all modules with
-	use_count = 0, I think. see: MOD_INC_USE_COUNT -ASG */
-
-	return AE_OK;
-}
-
-
-/*
- * See acpi_os_queue_for_execution()
- */
-static int
-acpi_os_queue_exec (
-	void *context)
-{
-	ACPI_OS_DPC		*dpc = (ACPI_OS_DPC*)context;
-
-	PROC_NAME("acpi_os_queue_exec");
-
-	daemonize();
-	strcpy(current->comm, "kacpidpc");
-    
-	if (!dpc || !dpc->function)
-		return AE_BAD_PARAMETER;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Executing function [%p(%p)].\n", dpc->function, dpc->context));
-
-	dpc->function(dpc->context);
-
-	kfree(dpc);
-
-	return 1;
-}
-
-static void
-acpi_os_schedule_exec (
-	void *context)
-{
-	ACPI_OS_DPC		*dpc = NULL;
-	int			thread_pid = -1;
-
-	PROC_NAME("acpi_os_schedule_exec");
-
-	dpc = (ACPI_OS_DPC*)context;
-	if (!dpc) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
-		return;
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Creating new thread to run function [%p(%p)].\n", dpc->function, dpc->context));
-
-	thread_pid = kernel_thread(acpi_os_queue_exec, dpc, 
-		(CLONE_FS | CLONE_FILES | SIGCHLD));
-	if (thread_pid < 0) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Call to kernel_thread() failed.\n"));
-		acpi_os_free(dpc);
-	}
-}
-
-acpi_status
-acpi_os_queue_for_execution(
-	u32			priority,
-	OSD_EXECUTION_CALLBACK	function,
-	void			*context)
-{
-	acpi_status 		status = AE_OK;
-	ACPI_OS_DPC 		*dpc = NULL;
-
-	PROC_NAME("acpi_os_queue_for_execution");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Scheduling function [%p(%p)] for deferred execution.\n", function, context));
-
-	if (!function)
-		return AE_BAD_PARAMETER;
-
-	/*
-	 * Queue via DPC:
-	 * --------------
-	 * Note that we have to use two different processes for queuing DPCs:
-	 *	 Interrupt-Level: Use schedule_task; can't spawn a new thread.
-	 *	    Kernel-Level: Spawn a new kernel thread, as schedule_task has
-	 *			  its limitations (e.g. single-threaded model), and
-	 *			  all other task queues run at interrupt-level.
-	 */
-	switch (priority) {
-
-	case OSD_PRIORITY_GPE:
-	{
-		static struct tq_struct task;
-
-		/*
-		 * Allocate/initialize DPC structure.  Note that this memory will be
-		 * freed by the callee.
-		 */
-		dpc = kmalloc(sizeof(ACPI_OS_DPC), GFP_ATOMIC);
-		if (!dpc) 
-			return AE_NO_MEMORY;
-
-		dpc->function = function;
-		dpc->context = context;
-
-		memset(&task, 0, sizeof(struct tq_struct));
-
-		task.routine = acpi_os_schedule_exec;
-		task.data = (void*)dpc;
-
-		if (schedule_task(&task) < 0) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Call to schedule_task() failed.\n"));
-			status = AE_ERROR;
-		}
-	}
-	break;
-
-	default:
-		/*
-		 * Allocate/initialize DPC structure.  Note that this memory will be
-		 * freed by the callee.
-		 */
-		dpc = kmalloc(sizeof(ACPI_OS_DPC), GFP_KERNEL);
-		if (!dpc) 
-			return AE_NO_MEMORY;
-
-		dpc->function = function;
-		dpc->context = context;
-
-		acpi_os_schedule_exec(dpc);
-		break;
-	}
-
-	return status;
-}
-
-
-acpi_status
-acpi_os_create_semaphore(
-	u32		max_units,
-	u32		initial_units,
-	acpi_handle	*handle)
-{
-	struct semaphore	*sem = NULL;
-
-	PROC_NAME("acpi_os_create_semaphore");
-
-	sem = acpi_os_callocate(sizeof(struct semaphore));
-	if (!sem)
-		return AE_NO_MEMORY;
-
-	sema_init(sem, initial_units);
-
-	*handle = (acpi_handle*)sem;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Creating semaphore[%p|%d].\n", *handle, initial_units));
-
-	return AE_OK;
-}
-
-
-/* 
- * TODO: A better way to delete semaphores?  Linux doesn't have a
- * 'delete_semaphore()' function -- may result in an invalid
- * pointer dereference for non-synchronized consumers.	Should
- * we at least check for blocked threads and signal/cancel them?
- */
-
-acpi_status
-acpi_os_delete_semaphore(
-	acpi_handle	handle)
-{
-	struct semaphore *sem = (struct semaphore*) handle;
-
-	PROC_NAME("acpi_os_delete_semaphore");
-
-	if (!sem) 
-		return AE_BAD_PARAMETER;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting semaphore[%p].\n", handle));
-
-	acpi_os_free(sem); sem =  NULL;
-
-	return AE_OK;
-}
-
-
-/*
- * TODO: The kernel doesn't have a 'down_timeout' function -- had to
- * improvise.  The process is to sleep for one scheduler quantum
- * until the semaphore becomes available.  Downside is that this
- * may result in starvation for timeout-based waits when there's
- * lots of semaphore activity.
- *
- * TODO: Support for units > 1?
- */
-acpi_status
-acpi_os_wait_semaphore(
-	acpi_handle		handle,
-	u32			units,
-	u32			timeout)
-{
-	acpi_status		status = AE_OK;
-	struct semaphore	*sem = (struct semaphore*)handle;
-	int			ret = 0;
-
-	PROC_NAME("acpi_os_wait_semaphore");
-
-	if (!sem || (units < 1)) 
-		return AE_BAD_PARAMETER;
-
-	if (units > 1)
-		return AE_SUPPORT;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Waiting for semaphore[%p|%d|%d]\n", handle, units, timeout));
-
-	switch (timeout)
-	{
-		/*
-		 * No Wait:
-		 * --------
-		 * A zero timeout value indicates that we shouldn't wait - just
-		 * acquire the semaphore if available otherwise return AE_TIME
-		 * (a.k.a. 'would block').
-		 */
-		case 0:
-		if(down_trylock(sem))
-			status = AE_TIME;
-		break;
-
-		/*
-		 * Wait Indefinitely:
-		 * ------------------
-		 */
-		case WAIT_FOREVER:
-		ret = down_interruptible(sem);
-		if (ret < 0)
-			status = AE_ERROR;
-		break;
-
-		/*
-		 * Wait w/ Timeout:
-		 * ----------------
-		 */
-		default:
-		// TODO: A better timeout algorithm?
-		{
-			int i = 0;
-			static const int quantum_ms = 1000/HZ;
-
-			ret = down_trylock(sem);
-			for (i = timeout; (i > 0 && ret < 0); i -= quantum_ms) {
-				current->state = TASK_INTERRUPTIBLE;
-				schedule_timeout(1);
-				ret = down_trylock(sem);
-			}
-	
-			if (ret != 0)
-			 status = AE_TIME;
-			}
-		break;
-	}
-
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Failed to acquire semaphore[%p|%d|%d]\n", handle, units, timeout));
-	}
-	else {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Acquired semaphore[%p|%d|%d]\n", handle, units, timeout));
-	}
-
-	return status;
-}
-
-
-/*
- * TODO: Support for units > 1?
- */
-acpi_status
-acpi_os_signal_semaphore(
-    acpi_handle 	    handle, 
-    u32 		    units)
-{
-	struct semaphore *sem = (struct semaphore *) handle;
-
-	PROC_NAME("acpi_os_signal_semaphore");
-
-	if (!sem || (units < 1)) 
-		return AE_BAD_PARAMETER;
-
-	if (units > 1)
-		return AE_SUPPORT;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Signaling semaphore[%p|%d]\n", handle, units));
-
-	up(sem);
-
-	return AE_OK;
-}
-
-u32
-acpi_os_get_line(NATIVE_CHAR *buffer)
-{
-
-#ifdef ENABLE_DEBUGGER
-	if (acpi_in_debugger) {
-		u32 chars;
-
-		kdb_read(buffer, sizeof(line_buf));
-
-		/* remove the CR kdb includes */ 
-		chars = strlen(buffer) - 1;
-		buffer[chars] = '\0';
-	}
-#endif
-
-	return 0;
-}
-
-/*
- * We just have to assume we're dealing with valid memory
- */
-
-BOOLEAN
-acpi_os_readable(void *ptr, u32 len)
-{
-	return 1;
-}
-
-BOOLEAN
-acpi_os_writable(void *ptr, u32 len)
-{
-	return 1;
-}
-
-u32
-acpi_os_get_thread_id (void)
-{
-	if (!in_interrupt())
-		return current->pid;
-
-	return 0;
-}
-
-acpi_status
-acpi_os_signal (
-    u32		function,
-    void	*info)
-{
-	switch (function)
-	{
-	case ACPI_SIGNAL_FATAL:
-		printk(KERN_ERR "ACPI: Fatal opcode executed\n");
-		break;
-	case ACPI_SIGNAL_BREAKPOINT:
-		{
-			char *bp_info = (char*) info;
-
-			printk(KERN_ERR "ACPI breakpoint: %s\n", bp_info);
-		}
-	default:
-		break;
-	}
-
-	return AE_OK;
-}
-
-acpi_status
-acpi_os_breakpoint(NATIVE_CHAR *msg)
-{
-	acpi_os_printf("breakpoint: %s", msg);
-	
-	return AE_OK;
-}
-
diff -Nru a/drivers/acpi/ospm/Makefile b/drivers/acpi/ospm/Makefile
--- a/drivers/acpi/ospm/Makefile	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,22 +0,0 @@
-#
-# Makefile for the Linux OSPM code.
-#
-
-O_TARGET := $(notdir $(CURDIR)).o
-
-ACPI_CFLAGS += -I$(CURDIR)/include
-
-EXTRA_CFLAGS += $(ACPI_CFLAGS)
-
-subdir-$(CONFIG_ACPI_BUSMGR)	+= busmgr
-subdir-$(CONFIG_ACPI_EC)	+= ec
-subdir-$(CONFIG_ACPI_SYS)	+= system
-subdir-$(CONFIG_ACPI_CPU)	+= processor
-subdir-$(CONFIG_ACPI_CMBATT)	+= battery
-subdir-$(CONFIG_ACPI_AC)	+= ac_adapter
-subdir-$(CONFIG_ACPI_BUTTON)	+= button
-subdir-$(CONFIG_ACPI_THERMAL)	+= thermal
-
-obj-y				+= $(foreach dir,$(subdir-y),$(dir)/ospm_$(dir).o)
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/ac_adapter/Makefile b/drivers/acpi/ospm/ac_adapter/Makefile
--- a/drivers/acpi/ospm/ac_adapter/Makefile	Fri Mar 15 17:51:04 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/ac_adapter/ac.c b/drivers/acpi/ospm/ac_adapter/ac.c
--- a/drivers/acpi/ospm/ac_adapter/ac.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,398 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ac.c
- *   $Revision: 23 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <acpi.h>
-#include "ac.h"
-
-
-#define _COMPONENT		ACPI_AC_ADAPTER
-	MODULE_NAME 		("ac")
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:	ac_print
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION: Prints out information on a specific ac_adapter.
- *
- ****************************************************************************/
-
-void
-ac_print (
-	AC_CONTEXT		*ac_adapter)
-{
-#ifdef ACPI_DEBUG
-
-	acpi_buffer		buffer;
-
-	PROC_NAME("ac_print");
-
-	if (!ac_adapter) {
-		return;
-	}
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(ac_adapter->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic adapter information.
-	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| AC Adapter[%02x]:[%p] %s\n", ac_adapter->device_handle, ac_adapter->acpi_handle, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_add_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ac_add_device(
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	AC_CONTEXT		*ac_adapter = NULL;
-	acpi_device_info	info;
-
-	FUNCTION_TRACE("ac_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding ac_adapter device [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context."));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Allocate a new AC_CONTEXT structure.
-	 */
-	ac_adapter = acpi_os_callocate(sizeof(AC_CONTEXT));
-	if (!ac_adapter) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	ac_adapter->device_handle = device->handle;
-	ac_adapter->acpi_handle = device->acpi_handle;
-
-	/*
-	 * Get information on this object.
-	 */
-	status = acpi_get_object_info(ac_adapter->acpi_handle, &info);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to get object info for ac_adapter device."));
-		goto end;
-	}
-
-	/*
-	 * _UID?
-	 * -----
-	 */
-	if (info.valid & ACPI_VALID_UID) {
-		strncpy(ac_adapter->uid, info.unique_id, sizeof(info.unique_id));
-	}
-	else {
-		strncpy(ac_adapter->uid, "0", sizeof("0"));
-	}
-
-	/*
-	 * _STA?
-	 * -----
-	 */
-	if (!(info.valid & ACPI_VALID_STA)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Must have valid _STA.\n"));
-		status = AE_ERROR;
-		goto end;
-	}
-
-	status = ac_osl_add_device(ac_adapter);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	*context = ac_adapter;
-
-	ac_print(ac_adapter);
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(ac_adapter);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_remove_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ac_remove_device (
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-	AC_CONTEXT		*ac_adapter = NULL;
-
-	FUNCTION_TRACE("ac_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ac_adapter = (AC_CONTEXT*)*context;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing ac_adapter device [%02x].\n", ac_adapter->device_handle));
-
-	ac_osl_remove_device(ac_adapter);
-
-	acpi_os_free(ac_adapter);
-
-	*context = NULL;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:	ac_initialize
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ac_initialize (void)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("ac_initialize");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	driver.notify = &ac_notify;
-	driver.request = &ac_request;
-
-	/*
-	 * Register driver for AC Adapter devices.
-	 */
-	MEMCPY(criteria.hid, AC_HID_AC_ADAPTER, sizeof(AC_HID_AC_ADAPTER));
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_terminate
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ac_terminate (void)
-{
-	acpi_status 		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("ac_terminate");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Unregister driver for AC Adapter devices.
-	 */
-	MEMCPY(criteria.hid, AC_HID_AC_ADAPTER, sizeof(AC_HID_AC_ADAPTER));
-
-	driver.notify = &ac_notify;
-	driver.request = &ac_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/*****************************************************************************
- *
- * FUNCTION:	ac_notify
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-acpi_status
-ac_notify (
-	BM_NOTIFY		notify_type,
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-
-	FUNCTION_TRACE("ac_notify");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	switch (notify_type) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = ac_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = ac_remove_device(context);
-		break;
-
-	case AC_NOTIFY_STATUS_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Status change event detected.\n"));
-		status = ac_osl_generate_event(notify_type,
-			((AC_CONTEXT*)*context));
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_request
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ac_request (
-	BM_REQUEST		*request,
-	void			*context)
-{
-	acpi_status 		status = AE_OK;
-
-	FUNCTION_TRACE("ac_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Handle Request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/ac_adapter/ac_osl.c b/drivers/acpi/ospm/ac_adapter/ac_osl.c
--- a/drivers/acpi/ospm/ac_adapter/ac_osl.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,257 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ac_osl.c
- *   $Revision: 10 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <acpi.h>
-#include "ac.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - AC Adapter Driver");
-MODULE_LICENSE("GPL");
-
-
-#define AC_PROC_ROOT		"ac_adapter"
-#define AC_PROC_STATUS		"status"
-#define AC_ON_LINE		"on-line"
-#define AC_OFF_LINE		"off-line"
-
-extern struct proc_dir_entry	*bm_proc_root;
-static struct proc_dir_entry	*ac_proc_root = NULL;
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_osl_proc_read_status
- *
- ****************************************************************************/
-
-static int
-ac_osl_proc_read_status (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	acpi_status 		status = AE_OK;
-	AC_CONTEXT		*ac_adapter = NULL;
-	char			*p = page;
-	int			len;
-
-	if (!context) {
-		goto end;
-	}
-
-	ac_adapter = (AC_CONTEXT*)context;
-
-	/* don't get status more than once for a single proc read */
-	if (off != 0) {
-		goto end;
-	}
-
-	status = bm_evaluate_simple_integer(ac_adapter->acpi_handle,
-		"_PSR", &(ac_adapter->is_online));
-	if (ACPI_FAILURE(status)) {
-		p += sprintf(p, "Error reading AC Adapter status\n");
-		goto end;
-	}
-
-	if (ac_adapter->is_online) {
-		p += sprintf(p, "Status:                  %s\n",
-			AC_ON_LINE);
-	}
-	else {
-		p += sprintf(p, "Status:                  %s\n",
-			AC_OFF_LINE);
-	}
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return(len);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_osl_add_device
- *
- ****************************************************************************/
-
-acpi_status
-ac_osl_add_device(
-	AC_CONTEXT		*ac_adapter)
-{
-	struct proc_dir_entry	*proc_entry = NULL;
-
-	if (!ac_adapter) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	printk(KERN_INFO "ACPI: AC Adapter found\n");
-
-	proc_entry = proc_mkdir(ac_adapter->uid, ac_proc_root);
-	if (!proc_entry) {
-		return(AE_ERROR);
-	}
-
-	create_proc_read_entry(AC_PROC_STATUS, S_IFREG | S_IRUGO,
-		proc_entry, ac_osl_proc_read_status, (void*)ac_adapter);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_osl_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-ac_osl_remove_device (
-	AC_CONTEXT		*ac_adapter)
-{
-	char			proc_entry[64];
-
-	if (!ac_adapter) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	sprintf(proc_entry, "%s/%s", ac_adapter->uid, AC_PROC_STATUS);
-	remove_proc_entry(proc_entry, ac_proc_root);
-
-	sprintf(proc_entry, "%s", ac_adapter->uid);
-	remove_proc_entry(proc_entry, ac_proc_root);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_osl_generate_event
- *
- ****************************************************************************/
-
-acpi_status
-ac_osl_generate_event (
-	u32			event,
-	AC_CONTEXT		*ac_adapter)
-{
-	acpi_status		status = AE_OK;
-
-	if (!ac_adapter) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (event) {
-
-	case AC_NOTIFY_STATUS_CHANGE:
-		status = bm_osl_generate_event(ac_adapter->device_handle,
-			AC_PROC_ROOT, ac_adapter->uid, event, 0);
-		break;
-
-	default:
-		return(AE_BAD_PARAMETER);
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_osl_init
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	0: Success
- *
- * DESCRIPTION: Module initialization.
- *
- ****************************************************************************/
-
-static int __init
-ac_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	ac_proc_root = proc_mkdir(AC_PROC_ROOT, bm_proc_root);
-	if (!ac_proc_root) {
-		status = AE_ERROR;
-	}
-	else {
-		status = ac_initialize();
-		if (ACPI_FAILURE(status)) {
-			remove_proc_entry(AC_PROC_ROOT, bm_proc_root);
-		}
-
-	}
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	ac_osl_cleanup
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	<none>
- *
- * DESCRIPTION: Module cleanup.
- *
- ****************************************************************************/
-
-static void __exit
-ac_osl_cleanup (void)
-{
-	ac_terminate();
-
-	if (ac_proc_root) {
-		remove_proc_entry(AC_PROC_ROOT, bm_proc_root);
-	}
-
-	return;
-}
-
-
-module_init(ac_osl_init);
-module_exit(ac_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/battery/Makefile b/drivers/acpi/ospm/battery/Makefile
--- a/drivers/acpi/ospm/battery/Makefile	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/battery/bt.c b/drivers/acpi/ospm/battery/bt.c
--- a/drivers/acpi/ospm/battery/bt.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,654 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bt.c
- *   $Revision: 29 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <acpi.h>
-#include "bt.h"
-
-
-#define _COMPONENT		ACPI_BATTERY
-	MODULE_NAME 		("bt")
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:	bt_print
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION: Prints out information on a specific battery.
- *
- ****************************************************************************/
-
-void
-bt_print (
-	BT_CONTEXT		*battery)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer 		buffer;
-
-	PROC_NAME("bt_print");
-
-	if (!battery) {
-		return;
-	}
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(battery->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic battery information.
-	 */
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Battery[%02x]:[%p] %s\n", battery->device_handle, battery->acpi_handle, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   uid[%s] is_present[%d] power_units[%s]\n", battery->uid, battery->is_present, battery->power_units));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_get_info
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- * NOTES:	Allocates battery_info - which must be freed by the caller.
- *
- ****************************************************************************/
-
-acpi_status
-bt_get_info (
-	BT_CONTEXT		*battery,
-	BT_BATTERY_INFO 	**battery_info)
-{
-	acpi_status 		status = AE_OK;
-	acpi_buffer 		bif_buffer, package_format, package_data;
-	acpi_object 		*package = NULL;
-
-	FUNCTION_TRACE("bt_get_info");
-
-	if (!battery || !battery_info || *battery_info) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	memset(&bif_buffer, 0, sizeof(acpi_buffer));
-
-	/*
-	 * Evalute _BIF:
-	 * -------------
-	 * And be sure to deallocate bif_buffer.pointer!
-	 */
-	status = bm_evaluate_object(battery->acpi_handle, "_BIF", NULL,
-		&bif_buffer);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Extract Package Data:
-	 * ---------------------
-	 * Type-cast this bif_buffer to a package and use helper
-	 * functions to convert results into BT_BATTERY_INFO structure.
-	 * The first attempt is just to get the size of the package
-	 * data; the second gets the data (once we know the required
-	 * bif_buffer size).
-	 */
-	status = bm_cast_buffer(&bif_buffer, (void**)&package,
-		sizeof(acpi_object));
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	package_format.length = sizeof("NNNNNNNNNSSSS");
-	package_format.pointer = "NNNNNNNNNSSSS";
-
-	memset(&package_data, 0, sizeof(acpi_buffer));
-
-	status = bm_extract_package_data(package, &package_format,
-		&package_data);
-	if (status != AE_BUFFER_OVERFLOW) {
-		if (status == AE_OK) {
-			status = AE_ERROR;
-		}
-		goto end;
-	}
-
-	package_data.pointer = acpi_os_callocate(package_data.length);
-	if (!package_data.pointer) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	status = bm_extract_package_data(package, &package_format,
-		&package_data);
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(package_data.pointer);
-		goto end;
-	}
-
-	*battery_info = package_data.pointer;
-
-end:
-	acpi_os_free(bif_buffer.pointer);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_get_status
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_get_status (
-	BT_CONTEXT		*battery,
-	BT_BATTERY_STATUS	**battery_status)
-{
-	acpi_status 		status = AE_OK;
-	acpi_buffer 		bst_buffer, package_format, package_data;
-	acpi_object 		*package = NULL;
-
-	FUNCTION_TRACE("bt_get_status");
-
-	if (!battery || !battery_status || *battery_status) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	memset(&bst_buffer, 0, sizeof(acpi_buffer));
-
-	/*
-	 * Evalute _BST:
-	 * -------------
-	 * And be sure to deallocate bst_buffer.pointer!
-	 */
-	status = bm_evaluate_object(battery->acpi_handle, "_BST",
-		NULL, &bst_buffer);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Extract Package Data:
-	 * ---------------------
-	 * Type-cast this bst_buffer to a package and use helper
-	 * functions to convert results into BT_BATTERY_STATUS structure.
-	 * The first attempt is just to get the size of the package data;
-	 * the second gets the data (once we know the required bst_buffer
-	 * size).
-	 */
-	status = bm_cast_buffer(&bst_buffer, (void**)&package,
-		sizeof(acpi_object));
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	package_format.length = sizeof("NNNN");
-	package_format.pointer = "NNNN";
-
-	memset(&package_data, 0, sizeof(acpi_buffer));
-
-	status = bm_extract_package_data(package, &package_format,
-		&package_data);
-	if (status != AE_BUFFER_OVERFLOW) {
-		if (status == AE_OK) {
-			status = AE_ERROR;
-		}
-		goto end;
-	}
-
-	package_data.pointer = acpi_os_callocate(package_data.length);
-	if (!package_data.pointer) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	status = bm_extract_package_data(package, &package_format,
-		&package_data);
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(package_data.pointer);
-		goto end;
-	}
-
-	*battery_status = package_data.pointer;
-
-end:
-	acpi_os_free(bst_buffer.pointer);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_check_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_check_device (
-	BT_CONTEXT		*battery)
-{
-	acpi_status 		status = AE_OK;
-	BM_DEVICE_STATUS	battery_status = BM_STATUS_UNKNOWN;
-	u32 			was_present = FALSE;
-	BT_BATTERY_INFO 	*battery_info = NULL;
-
-	FUNCTION_TRACE("bt_check_device");
-
-	if (!battery) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	was_present = battery->is_present;
-
-	/*
-	 * Battery Present?
-	 * ----------------
-	 * Get the device status and check if battery slot is occupied.
-	 */
-	status = bm_get_device_status(battery->device_handle, &battery_status);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Unable to get battery status.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	if (battery_status & BM_STATUS_BATTERY_PRESENT) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Battery socket occupied.\n"));
-		battery->is_present = TRUE;
-	}
-	else {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Battery socket not occupied.\n"));
-		battery->is_present = FALSE;
-	}
-
-	/*
-	 * Battery Appeared?
-	 * -----------------
-	 */
-	if (!was_present && battery->is_present) {
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Battery insertion detected.\n"));
-
-		/*
-		 * Units of Power?
-		 * ---------------
-		 * Get the 'units of power', as we'll need this to report
-		 * status information.
-		 */
-		status = bt_get_info(battery, &battery_info);
-		if (ACPI_SUCCESS(status)) {
-			battery->power_units = (battery_info->power_unit)
-				? BT_POWER_UNITS_AMPS : BT_POWER_UNITS_WATTS;
-			acpi_os_free(battery_info);
-		}
-	}
-
-	/*
-	 * Battery Disappeared?
-	 * --------------------
-	 */
-	else if (was_present && !battery->is_present) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Battery removal detected.\n"));
-		battery->power_units = BT_POWER_UNITS_DEFAULT;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/*****************************************************************************
- *
- * FUNCTION:	bt_add_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_add_device (
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	BT_CONTEXT		*battery = NULL;
-
-	FUNCTION_TRACE("bt_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding battery device [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Allocate a new BT_CONTEXT structure.
-	 */
-	battery = acpi_os_callocate(sizeof(BT_CONTEXT));
-	if (!battery) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	battery->device_handle = device->handle;
-	battery->acpi_handle = device->acpi_handle;
-	strncpy(battery->uid, device->id.uid, sizeof(battery->uid));
-
-	battery->power_units = BT_POWER_UNITS_DEFAULT;
-	battery->is_present = FALSE;
-
-	/*
-	 * See if battery is really present.
-	 */
-	status = bt_check_device(battery);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	status = bt_osl_add_device(battery);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	*context = battery;
-
-	bt_print(battery);
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(battery);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/*****************************************************************************
- *
- * FUNCTION:	bt_remove_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_remove_device (
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-	BT_CONTEXT		*battery = NULL;
-
-	FUNCTION_TRACE("bt_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	battery = (BT_CONTEXT*)*context;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing battery device [%02x].\n", battery->device_handle));
-
-	bt_osl_remove_device(battery);
-
-	acpi_os_free(battery);
-
-	*context = NULL;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/*****************************************************************************
- *                               External Functions
- *****************************************************************************/
-
-/*****************************************************************************
- *
- * FUNCTION:	bt_initialize
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_initialize (void)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("bt_initialize");
-
-	memset(&criteria, 0, sizeof(BM_DEVICE_ID));
-	memset(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Register driver for driver method battery devices.
-	 */
-	MEMCPY(criteria.hid, BT_HID_CM_BATTERY, sizeof(BT_HID_CM_BATTERY));
-
-	driver.notify = &bt_notify;
-	driver.request = &bt_request;
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_terminate
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_terminate (void)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("bt_terminate");
-
-	memset(&criteria, 0, sizeof(BM_DEVICE_ID));
-	memset(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Unregister driver for driver method battery devices.
-	 */
-	MEMCPY(criteria.hid, BT_HID_CM_BATTERY, sizeof(BT_HID_CM_BATTERY));
-
-	driver.notify = &bt_notify;
-	driver.request = &bt_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_notify
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_notify (
-	BM_NOTIFY		notify_type,
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-
-	FUNCTION_TRACE("bt_notify");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	switch (notify_type) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = bt_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = bt_remove_device(context);
-		break;
-
-	case BT_NOTIFY_STATUS_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Status change (_BST) event detected.\n"));
-		status = bt_osl_generate_event(notify_type,
-			((BT_CONTEXT*)*context));
-		break;
-
-	case BT_NOTIFY_INFORMATION_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Information change (_BIF) event detected.\n"));
-		status = bt_check_device((BT_CONTEXT*)*context);
-		if (ACPI_SUCCESS(status)) {
-			status = bt_osl_generate_event(notify_type,
-				((BT_CONTEXT*)*context));
-		}
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_request
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bt_request (
-	BM_REQUEST		*request,
-	void			*context)
-{
-	acpi_status 		status = AE_OK;
-
-	FUNCTION_TRACE("bt_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context)
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-
-	/*
-	 * Handle request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/battery/bt_osl.c b/drivers/acpi/ospm/battery/bt_osl.c
--- a/drivers/acpi/ospm/battery/bt_osl.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,443 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bt_osl.c
- *   $Revision: 24 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * Changes:
- * Brendan Burns <bburns@wso.williams.edu> 2000-11-15
- * - added proc battery interface
- * - parse returned data from _BST and _BIF
- * Andy Grover <andrew.grover@intel.com> 2000-12-8
- * - improved proc interface
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <acpi.h>
-#include "bt.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - Control Method Battery Driver");
-MODULE_LICENSE("GPL");
-
-
-#define BT_PROC_ROOT		"battery"
-#define BT_PROC_STATUS		"status"
-#define BT_PROC_INFO		"info"
-
-extern struct proc_dir_entry	*bm_proc_root;
-static struct proc_dir_entry	*bt_proc_root = NULL;
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_proc_read_info
- *
- ****************************************************************************/
-
-static int
-bt_osl_proc_read_info (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	BT_CONTEXT		*battery = NULL;
-	BT_BATTERY_INFO 	*battery_info = NULL;
-	char			*p = page;
-	int 			len = 0;
-
-	if (!context || (off != 0)) {
-		goto end;
-	}
-
-	battery = (BT_CONTEXT*)context;
-
-	/*
-	 * Battery Present?
-	 * ----------------
-	 */
-	if (!battery->is_present) {
-		p += sprintf(p, "Present:                 no\n");
-		goto end;
-	}
-	else {
-		p += sprintf(p, "Present:                 yes\n");
-	}
-
-	/*
-	 * Get Battery Information:
-	 * ------------------------
-	 */
-	if (ACPI_FAILURE(bt_get_info(battery, &battery_info))) {
-		p += sprintf(p, "Error reading battery information (_BIF)\n");
-		goto end;
-	}
-
-	if (battery_info->design_capacity == BT_UNKNOWN) {
-		p += sprintf(p, "Design Capacity:         unknown\n");
-	}
-	else {
-		p += sprintf(p, "Design Capacity:         %d %sh\n",
-			 (u32)battery_info->design_capacity,
-			 battery->power_units);
-	}
-	
-	if (battery_info->last_full_capacity == BT_UNKNOWN) {
-		p += sprintf(p, "Last Full Capacity:      unknown\n");
-	}
-	else {
-		p += sprintf(p, "Last Full Capacity:      %d %sh\n",
-			 (u32)battery_info->last_full_capacity,
-			 battery->power_units);
-	}
-
-	if (battery_info->battery_technology == 0) {
-		p += sprintf(p, "Battery Technology:      primary (non-rechargeable)\n");
-	}
-	else if (battery_info->battery_technology == 1) {
-		p += sprintf(p, "Battery Technology:      secondary (rechargeable)\n");
-	}
-	else {
-		p += sprintf(p, "Battery Technology:      unknown\n");
-	}
-
-	if (battery_info->design_voltage == BT_UNKNOWN) {
-		p += sprintf(p, "Design Voltage:          unknown\n");
-	}
-	else {
-		p += sprintf(p, "Design Voltage:          %d mV\n",
-			 (u32)battery_info->design_voltage);
-	}
-	
-	p += sprintf(p, "Design Capacity Warning: %d %sh\n",
-		(u32)battery_info->design_capacity_warning,
-		battery->power_units);
-	p += sprintf(p, "Design Capacity Low:     %d %sh\n",
-		(u32)battery_info->design_capacity_low,
-		battery->power_units);
-	p += sprintf(p, "Capacity Granularity 1:  %d %sh\n",
-		(u32)battery_info->battery_capacity_granularity_1,
-		battery->power_units);
-	p += sprintf(p, "Capacity Granularity 2:  %d %sh\n",
-		(u32)battery_info->battery_capacity_granularity_2,
-		battery->power_units);
-	p += sprintf(p, "Model Number:            %s\n",
-		battery_info->model_number);
-	p += sprintf(p, "Serial Number:           %s\n",
-		battery_info->serial_number);
-	p += sprintf(p, "Battery Type:            %s\n",
-		battery_info->battery_type);
-	p += sprintf(p, "OEM Info:                %s\n",
-		battery_info->oem_info);
-	
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	acpi_os_free(battery_info);
-
-	return(len);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_proc_read_status
- *
- ****************************************************************************/
-
-static int
-bt_osl_proc_read_status (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	BT_CONTEXT		*battery = NULL;
-	BT_BATTERY_STATUS	*battery_status = NULL;
-	char			*p = page;
-	int 			len = 0;
-
-	if (!context || (off != 0)) {
-		goto end;
-	}
-
-	battery = (BT_CONTEXT*)context;
-
-	/*
-	 * Battery Present?
-	 * ----------------
-	 */
-	if (!battery->is_present) {
-		p += sprintf(p, "Present:                 no\n");
-		goto end;
-	}
-	else {
-		p += sprintf(p, "Present:                 yes\n");
-	}
-
-	/*
-	 * Get Battery Status:
-	 * -------------------
-	 */
-	if (ACPI_FAILURE(bt_get_status(battery, &battery_status))) {
-		p += sprintf(p, "Error reading battery status (_BST)\n");
-		goto end;
-	}
-
-	/*
-	 * Store Data:
-	 * -----------
-	 */
-
-	if (!battery_status->state) {
-		p += sprintf(p, "State:                   ok\n");
-	}
-	else {
-		if (battery_status->state & 0x1)
-			p += sprintf(p, "State:                   discharging\n");
-		if (battery_status->state & 0x2)
-			p += sprintf(p, "State:                   charging\n");
-		if (battery_status->state & 0x4)
-			p += sprintf(p, "State:                   critically low\n");
-	}
-
-	if (battery_status->present_rate == BT_UNKNOWN) {
-		p += sprintf(p, "Present Rate:            unknown\n");
-	}
-	else {
-		p += sprintf(p, "Present Rate:            %d %s\n",
-			(u32)battery_status->present_rate,
-			battery->power_units);
-	}
-
-	if (battery_status->remaining_capacity == BT_UNKNOWN) {
-		p += sprintf(p, "Remaining Capacity:      unknown\n");
-	}
-	else {
-		p += sprintf(p, "Remaining Capacity:      %d %sh\n",
-			(u32)battery_status->remaining_capacity,
-			battery->power_units);
-	}
-
-	if (battery_status->present_voltage == BT_UNKNOWN) {
-		p += sprintf(p, "Battery Voltage:         unknown\n");
-	}
-	else {
-		p += sprintf(p, "Battery Voltage:         %d mV\n",
-			(u32)battery_status->present_voltage);
-	}
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	acpi_os_free(battery_status);
-
-	return(len);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_add_device
- *
- ****************************************************************************/
-
-acpi_status
-bt_osl_add_device(
-	BT_CONTEXT		*battery)
-{
-	struct proc_dir_entry	*proc_entry = NULL;
-
-	if (!battery) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	if (battery->is_present) {
-		printk("ACPI: Battery socket found, battery present\n");
-	}
-	else {
-		printk("ACPI: Battery socket found, battery absent\n");
-	}
-
-	proc_entry = proc_mkdir(battery->uid, bt_proc_root);
-	if (!proc_entry) {
-		return(AE_ERROR);
-	}
-
-	create_proc_read_entry(BT_PROC_STATUS, S_IFREG | S_IRUGO,
-		proc_entry, bt_osl_proc_read_status, (void*)battery);
-
-	create_proc_read_entry(BT_PROC_INFO, S_IFREG | S_IRUGO,
-		proc_entry, bt_osl_proc_read_info, (void*)battery);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-bt_osl_remove_device (
-	BT_CONTEXT		*battery)
-{
-	char			proc_entry[64];
-
-	if (!battery) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	sprintf(proc_entry, "%s/%s", battery->uid, BT_PROC_INFO);
-	remove_proc_entry(proc_entry, bt_proc_root);
-
-	sprintf(proc_entry, "%s/%s", battery->uid, BT_PROC_STATUS);
-	remove_proc_entry(proc_entry, bt_proc_root);
-
-	sprintf(proc_entry, "%s", battery->uid);
-	remove_proc_entry(proc_entry, bt_proc_root);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_generate_event
- *
- ****************************************************************************/
-
-acpi_status
-bt_osl_generate_event (
-	u32			event,
-	BT_CONTEXT		*battery)
-{
-	acpi_status		status = AE_OK;
-
-	if (!battery) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (event) {
-
-	case BT_NOTIFY_STATUS_CHANGE:
-	case BT_NOTIFY_INFORMATION_CHANGE:
-		status = bm_osl_generate_event(battery->device_handle,
-			BT_PROC_ROOT, battery->uid, event, 0);
-		break;
-
-	default:
-		return(AE_BAD_PARAMETER);
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_init
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	0: Success
- *
- * DESCRIPTION: Module initialization.
- *
- ****************************************************************************/
-
-static int __init
-bt_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	/* abort if no busmgr */
-	if (!bm_proc_root)
-		return -ENODEV;
-
-	bt_proc_root = proc_mkdir(BT_PROC_ROOT, bm_proc_root);
-	if (!bt_proc_root) {
-		status = AE_ERROR;
-	}
-	else {
-		status = bt_initialize();
-		if (ACPI_FAILURE(status)) {
-			remove_proc_entry(BT_PROC_ROOT, bm_proc_root);
-		}
-	}
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bt_osl_cleanup
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	<none>
- *
- * DESCRIPTION: Module cleanup.
- *
- ****************************************************************************/
-
-static void __exit
-bt_osl_cleanup (void)
-{
-	bt_terminate();
-
-	if (bt_proc_root) {
-		remove_proc_entry(BT_PROC_ROOT, bm_proc_root);
-	}
-
-	return;
-}
-
-
-module_init(bt_osl_init);
-module_exit(bt_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/busmgr/Makefile b/drivers/acpi/ospm/busmgr/Makefile
--- a/drivers/acpi/ospm/busmgr/Makefile	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,8 +0,0 @@
-export-objs	:= bm_osl.o
-
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/busmgr/bm.c b/drivers/acpi/ospm/busmgr/bm.c
--- a/drivers/acpi/ospm/busmgr/bm.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,1146 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bm.c
- *   $Revision: 48 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <acpi.h>
-#include "bm.h"
-
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bm")
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-extern fadt_descriptor_rev2	acpi_fadt;
-/* TBD: Make dynamically sizeable. */
-BM_NODE_LIST			node_list;
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/*****************************************************************************
- *
- * FUNCTION:    bm_print_object
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-bm_print_object (
-	acpi_handle		handle)
-{
-	acpi_buffer		buffer;
-	acpi_handle		parent;
-	acpi_object_type	type;
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
-	acpi_get_parent(handle, &parent);
-	acpi_get_type(handle, &type);
-
-	/*
-	 * TBD: Hack to get around scope identification problem.
-	 */
-	if (type == ACPI_TYPE_ANY) {
-		if (ACPI_SUCCESS(acpi_get_next_object(ACPI_TYPE_ANY,
-			handle, 0, NULL))) {
-			type = INTERNAL_TYPE_SCOPE;
-		}
-	}
-
-	switch (type)
-	 {
-	case INTERNAL_TYPE_SCOPE:
-		acpi_os_printf("SCOPE: ");
-		break;
-	case ACPI_TYPE_INTEGER:
-		acpi_os_printf("SIMPLE (number): ");
-		break;
-	case ACPI_TYPE_STRING:
-		acpi_os_printf("SIMPLE (string): ");
-		break;
-	case ACPI_TYPE_BUFFER:
-		acpi_os_printf("SIMPLE (buffer): ");
-		break;
-	case ACPI_TYPE_PACKAGE:
-		acpi_os_printf("SIMPLE (package): ");
-		break;
-	case ACPI_TYPE_FIELD_UNIT:
-		acpi_os_printf("FIELD UNIT: ");
-		break;
-	case ACPI_TYPE_DEVICE:
-		acpi_os_printf("DEVICE: ");
-		break;
-	case ACPI_TYPE_EVENT:
-		acpi_os_printf("EVENT: ");
-		break;
-	case ACPI_TYPE_METHOD:
-		acpi_os_printf("CONTROL METHOD: ");
-		break;
-	case ACPI_TYPE_MUTEX:
-		acpi_os_printf("MUTEX: ");
-		break;
-	case ACPI_TYPE_REGION:
-		acpi_os_printf("OPERATION REGION: ");
-		break;
-	case ACPI_TYPE_POWER:
-		acpi_os_printf("POWER RESOURCE: ");
-		break;
-	case ACPI_TYPE_PROCESSOR:
-		acpi_os_printf("PROCESSOR: ");
-		break;
-	case ACPI_TYPE_THERMAL:
-		acpi_os_printf("THERMAL ZONE: ");
-		break;
-	case ACPI_TYPE_BUFFER_FIELD:
-		acpi_os_printf("BUFFER FIELD: ");
-		break;
-	case ACPI_TYPE_DDB_HANDLE:
-		acpi_os_printf("DDB HANDLE: ");
-		break;
-	default:
-		acpi_os_printf("OTHER (%d): ", type);
-		break;
-	}
-
-	acpi_os_printf("Object[%p][%s] parent[%p].\n", handle, (char*)buffer.pointer, parent);
-
-	acpi_os_free(buffer.pointer);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_print_node
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-bm_print_node (
-	BM_NODE			*node,
-	u32                     flags)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer             buffer;
-	BM_DEVICE		*device = NULL;
-	char                    *type_string = NULL;
-
-	PROC_NAME("bm_print_node");
-
-	if (!node) {
-		return;
-	}
-
-	device = &(node->device);
-
-	if (flags & BM_PRINT_PRESENT) {
-		if (!BM_DEVICE_PRESENT(device)) {
-			return;
-		}
-	}
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	acpi_get_name(device->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	switch(device->id.type) {
-	case BM_TYPE_SYSTEM:
-		type_string = " System";
-		break;
-	case BM_TYPE_SCOPE:
-		type_string = "  Scope";
-		break;
-	case BM_TYPE_PROCESSOR:
-		type_string = "   Proc";
-		break;
-	case BM_TYPE_THERMAL_ZONE:
-		type_string = "Thermal";
-		break;
-	case BM_TYPE_POWER_RESOURCE:
-		type_string = "  Power";
-		break;
-	case BM_TYPE_FIXED_BUTTON:
-		type_string = " Button";
-		break;
-	case BM_TYPE_DEVICE:
-		type_string = " Device";
-		break;
-	default:
-		type_string = "Unknown";
-		break;
-	}
-
-	if (!(flags & BM_PRINT_GROUP)) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+-------------------------------------------------------------------------------\n"));
-	}
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| %s[%02x]:[%p] flags[%02x] hid[%s] %s\n", type_string, device->handle, device->acpi_handle, device->flags, (device->id.hid[0] ? device->id.hid : "       "), (char*)buffer.pointer));
-
-	if (flags & BM_PRINT_IDENTIFICATION) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   identification: uid[%s] adr[%08x]\n", device->id.uid, device->id.adr));
-	}
-
-	if (flags & BM_PRINT_LINKAGE) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   linkage: this[%p] parent[%p] next[%p]\n", node, node->parent, node->next));
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|     scope.head[%p] scope.tail[%p]\n", node->scope.head, node->scope.tail));
-	}
-
-	if (flags & BM_PRINT_POWER) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   power: state[D%d] flags[%08x]\n", device->power.state, device->power.flags));
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|     S0[%02x] S1[%02x] S2[%02x] S3[%02x] S4[%02x] S5[%02x]\n", device->power.dx_supported[0], device->power.dx_supported[1], device->power.dx_supported[2], device->power.dx_supported[3], device->power.dx_supported[4], device->power.dx_supported[5]));
-	}
-
-	if (!(flags & BM_PRINT_GROUP)) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+-------------------------------------------------------------------------------\n"));
-	}
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_print_hierarchy
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-bm_print_hierarchy (void)
-{
-#ifdef ACPI_DEBUG
-	u32			i = 0;
-
-	FUNCTION_TRACE("bm_print_hierarchy");
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	for (i = 0; i < node_list.count; i++) {
-		bm_print_node(node_list.nodes[i], BM_PRINT_GROUP | BM_PRINT_PRESENT);
-	}
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-#endif /*ACPI_DEBUG*/
-
-	return_VOID;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_status
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_status (
-	BM_DEVICE		*device)
-{
-	acpi_status           status = AE_OK;
-
-	if (!device) {
-		return AE_BAD_PARAMETER;
-	}
-
-	device->status = BM_STATUS_UNKNOWN;
-
-	/*
-	 * Dynamic Status?
-	 * ---------------
-	 * If _STA isn't present we just return the default status.
-	 */
-	if (!(device->flags & BM_FLAGS_DYNAMIC_STATUS)) {
-		device->status = BM_STATUS_DEFAULT;
-		return AE_OK;
-	}
-
-	/*
-	 * Evaluate _STA:
-	 * --------------
-	 */
-	status = bm_evaluate_simple_integer(device->acpi_handle, "_STA",
-		&(device->status));
-
-	return status;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_identification
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_identification (
-	BM_DEVICE		*device)
-{
-	acpi_status             status = AE_OK;
-	acpi_device_info        info;
-
-	if (!device) {
-		return AE_BAD_PARAMETER;
-	}
-
-	if (!(device->flags & BM_FLAGS_IDENTIFIABLE)) {
-		return AE_OK;
-	}
-
-	device->id.uid[0] = BM_UID_UNKNOWN;
-	device->id.hid[0] = BM_HID_UNKNOWN;
-	device->id.adr = BM_ADDRESS_UNKNOWN;
-
-	/*
-	 * Get Object Info:
-	 * ----------------
-	 * Evalute _UID, _HID, and _ADR...
-	 */
-	status = acpi_get_object_info(device->acpi_handle, &info);
-	if (ACPI_FAILURE(status)) {
-		return status;
-	}
-
-	if (info.valid & ACPI_VALID_UID) {
-		MEMCPY((void*)device->id.uid, (void*)info.unique_id,
-			sizeof(BM_DEVICE_UID));
-	}
-
-	if (info.valid & ACPI_VALID_HID) {
-		MEMCPY((void*)device->id.hid, (void*)info.hardware_id,
-			sizeof(BM_DEVICE_HID));
-	}
-
-	if (info.valid & ACPI_VALID_ADR) {
-		device->id.adr = info.address;
-	}
-
-	return status;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_flags
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_flags (
-	BM_DEVICE		*device)
-{
-	acpi_handle		acpi_handle = NULL;
-
-	if (!device) {
-		return AE_BAD_PARAMETER;
-	}
-
-	device->flags = BM_FLAGS_UNKNOWN;
-
-	switch (device->id.type) {
-
-	case BM_TYPE_DEVICE:
-
-		/*
-		 * Presence of _DCK indicates a docking station.
-		 */
-		if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_DCK", &acpi_handle))) {
-			device->flags |= BM_FLAGS_DOCKING_STATION;
-		}
-
-		/*
-		 * Presence of _EJD and/or _EJx indicates 'ejectable'.
-		 * TBD: _EJx...
-		 */
-		if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_EJD", &acpi_handle))) {
-			device->flags |= BM_FLAGS_EJECTABLE;
-		}
-
-		/*
-		 * Presence of _PR0 or _PS0 indicates 'power manageable'.
-		 */
-		if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_PR0", &acpi_handle)) ||
-			ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_PS0", &acpi_handle))) {
-			device->flags |= BM_FLAGS_POWER_CONTROL;
-		}
-
-		/*
-		 * Presence of _CRS indicates 'configurable'.
-		 */
-		if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_CRS", &acpi_handle))) {
-			device->flags |= BM_FLAGS_CONFIGURABLE;
-		}
-
-		/* Fall through to next case statement. */
-
-	case BM_TYPE_PROCESSOR:
-	case BM_TYPE_THERMAL_ZONE:
-	case BM_TYPE_POWER_RESOURCE:
-		/*
-		 * Presence of _HID or _ADR indicates 'identifiable'.
-		 */
-		if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_HID", &acpi_handle)) ||
-		   ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-		   "_ADR", &acpi_handle))) {
-			device->flags |= BM_FLAGS_IDENTIFIABLE;
-		}
-
-		/*
-		 * Presence of _STA indicates 'dynamic status'.
-		 */
-		if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle,
-			"_STA", &acpi_handle))) {
-			device->flags |= BM_FLAGS_DYNAMIC_STATUS;
-		}
-
-		break;
-	}
-
-	return AE_OK;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_add_namespace_device
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_add_namespace_device (
-	acpi_handle             acpi_handle,
-	acpi_object_type        acpi_type,
-	BM_NODE			*parent,
-	BM_NODE			**child)
-{
-	acpi_status             status = AE_OK;
-	BM_NODE			*node = NULL;
-	BM_DEVICE		*device = NULL;
-
-	FUNCTION_TRACE("bm_add_namespace_device");
-
-	if (!parent || !child) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (node_list.count > BM_HANDLES_MAX) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	(*child) = NULL;
-
-	/*
-	 * Create Node:
-	 * ------------
-	 */
-	node = acpi_os_callocate(sizeof(BM_NODE));
-	if (!node) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	node->parent = parent;
-	node->next = NULL;
-
-	device = &(node->device);
-
-	device->handle = node_list.count;
-	device->acpi_handle = acpi_handle;
-
-	/*
-	 * Device Type:
-	 * ------------
-	 */
-	switch (acpi_type) {
-	case INTERNAL_TYPE_SCOPE:
-		device->id.type = BM_TYPE_SCOPE;
-		break;
-	case ACPI_TYPE_PROCESSOR:
-		device->id.type = BM_TYPE_PROCESSOR;
-		break;
-	case ACPI_TYPE_THERMAL:
-		device->id.type = BM_TYPE_THERMAL_ZONE;
-		break;
-	case ACPI_TYPE_POWER:
-		device->id.type = BM_TYPE_POWER_RESOURCE;
-		break;
-	case ACPI_TYPE_DEVICE:
-		device->id.type = BM_TYPE_DEVICE;
-		break;
-	}
-
-	/*
-	 * Get Other Device Info:
-	 * ----------------------
-	 * But only if this device's parent is present (which implies
-	 * this device MAY be present).
-	 */
-	if (BM_NODE_PRESENT(node->parent)) {
-		/*
-		 * Device Flags
-		 */
-		status = bm_get_flags(device);
-		if (ACPI_FAILURE(status)) {
-			goto end;
-		}
-
-		/*
-		 * Device Identification
-		 */
-		status = bm_get_identification(device);
-		if (ACPI_FAILURE(status)) {
-			goto end;
-		}
-
-		/*
-		 * Device Status
-		 */
-		status = bm_get_status(device);
-		if (ACPI_FAILURE(status)) {
-			goto end;
-		}
-
-		/*
-		 * Power Management:
-		 * -----------------
-		 * If this node doesn't provide direct power control
-		 * then we inherit PM capabilities from its parent.
-		 *
-		 * TBD: Inherit!
-		 */
-		if (BM_IS_POWER_CONTROL(device)) {
-			status = bm_get_pm_capabilities(node);
-			if (ACPI_FAILURE(status)) {
-				goto end;
-			}
-		}
-	}
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(node);
-	}
-	else {
-		/*
-		 * Add to the node_list.
-		 */
-		node_list.nodes[node_list.count++] = node;
-
-		/*
-		 * Formulate Hierarchy:
-		 * --------------------
-		 * Arrange within the namespace by assigning the parent and
-		 * adding to the parent device's list of children (scope).
-		 */
-		if (!parent->scope.head) {
-			parent->scope.head = node;
-		}
-		else {
-			if (!parent->scope.tail) {
-				(parent->scope.head)->next = node;
-			}
-			else {
-				(parent->scope.tail)->next = node;
-			}
-		}
-		parent->scope.tail = node;
-
-		(*child) = node;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_enumerate_namespace
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_enumerate_namespace (void)
-{
-	acpi_status		status = AE_OK;
-	acpi_handle             parent_handle = ACPI_ROOT_OBJECT;
-	acpi_handle             child_handle = NULL;
-	BM_NODE			*parent = NULL;
-	BM_NODE			*child = NULL;
-	acpi_object_type        acpi_type = 0;
-	u32                     level = 1;
-
-	FUNCTION_TRACE("bm_enumerate_namespace");
-
-	parent = node_list.nodes[0];
-
-	/*
-	 * Enumerate ACPI Namespace:
-	 * -------------------------
-	 * Parse through the ACPI namespace, identify all 'devices',
-	 * and create a new entry for each in our collection.
-	 */
-	while (level > 0) {
-
-		/*
-		 * Get the next object at this level.
-		 */
-		status = acpi_get_next_object(ACPI_TYPE_ANY, parent_handle, child_handle, &child_handle);
-		if (ACPI_SUCCESS(status)) {
-			/*
-			 * TBD: This is a hack to get around the problem
-			 *       identifying scope objects.  Scopes
-			 *       somehow need to be uniquely identified.
-			 */
-			status = acpi_get_type(child_handle, &acpi_type);
-			if (ACPI_SUCCESS(status) && (acpi_type == ACPI_TYPE_ANY)) {
-				status = acpi_get_next_object(ACPI_TYPE_ANY, child_handle, 0, NULL);
-				if (ACPI_SUCCESS(status)) {
-					acpi_type = INTERNAL_TYPE_SCOPE;
-				}
-			}
-
-			/*
-			 * Device?
-			 * -------
-			 * If this object is a 'device', insert into the
-			 * ACPI Bus Manager's local hierarchy and search
-			 * the object's scope for any child devices (a
-			 * depth-first search).
-			 */
-			switch (acpi_type) {
-			case INTERNAL_TYPE_SCOPE:
-			case ACPI_TYPE_DEVICE:
-			case ACPI_TYPE_PROCESSOR:
-			case ACPI_TYPE_THERMAL:
-			case ACPI_TYPE_POWER:
-				status = bm_add_namespace_device(child_handle, acpi_type, parent, &child);
-				if (ACPI_SUCCESS(status)) {
-					status = acpi_get_next_object(ACPI_TYPE_ANY, child_handle, 0, NULL);
-					if (ACPI_SUCCESS(status)) {
-						level++;
-						parent_handle = child_handle;
-						child_handle = 0;
-						parent = child;
-					}
-				}
-				break;
-			}
-		}
-
-		/*
-		 * Scope Exhausted:
-		 * ----------------
-		 * No more children in this object's scope, Go back up
-		 * in the namespace tree to the object's parent.
-		 */
-		else {
-			level--;
-			child_handle = parent_handle;
-			acpi_get_parent(parent_handle,
-				&parent_handle);
-
-			if (parent) {
-				parent = parent->parent;
-			}
-			else {
-				return_ACPI_STATUS(AE_NULL_ENTRY);
-			}
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_add_fixed_feature_device
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_add_fixed_feature_device (
-	BM_NODE			*parent,
-	BM_DEVICE_TYPE		device_type,
-	char			*device_hid)
-{
-	acpi_status             status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_add_fixed_feature_device");
-
-	if (!parent) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (node_list.count > BM_HANDLES_MAX) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	/*
-	 * Allocate the new device and add to the device array.
-	 */
-	node = acpi_os_callocate(sizeof(BM_NODE));
-	if (!node) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	/*
-	 * Get device info.
-	 */
-	node->device.handle = node_list.count;
-	node->device.acpi_handle = ACPI_ROOT_OBJECT;
-	node->device.id.type = BM_TYPE_FIXED_BUTTON;
-	if (device_hid) {
-		MEMCPY((void*)node->device.id.hid, device_hid,
-			sizeof(node->device.id.hid));
-	}
-	node->device.flags = BM_FLAGS_FIXED_FEATURE;
-	node->device.status = BM_STATUS_DEFAULT;
-	/* TBD: Device PM capabilities */
-
-	/*
-	 * Add to the node_list.
-	 */
-	node_list.nodes[node_list.count++] = node;
-
-	/*
-	 * Formulate Hierarchy:
-	 * --------------------
-	 * Arrange within the namespace by assigning the parent and
-	 * adding to the parent device's list of children (scope).
-	 */
-	node->parent = parent;
-	node->next = NULL;
-
-	if (parent) {
-		if (!parent->scope.head) {
-			parent->scope.head = node;
-		}
-		else {
-			if (!parent->scope.tail) {
-				(parent->scope.head)->next = node;
-			}
-			else {
-				(parent->scope.tail)->next = node;
-			}
-		}
-		parent->scope.tail = node;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_enumerate_fixed_features
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_enumerate_fixed_features (void)
-{
-	FUNCTION_TRACE("bm_enumerate_fixed_features");
-
-	/*
-	 * Root Object:
-	 * ------------
-	 * Fabricate the root object, which happens to always get a
-	 * device_handle of zero.
-	 */
-	node_list.nodes[0] = acpi_os_callocate(sizeof(BM_NODE));
-	if (NULL == (node_list.nodes[0])) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	node_list.nodes[0]->device.handle = BM_HANDLE_ROOT;
-	node_list.nodes[0]->device.acpi_handle = ACPI_ROOT_OBJECT;
-	node_list.nodes[0]->device.flags = BM_FLAGS_UNKNOWN;
-	node_list.nodes[0]->device.status = BM_STATUS_DEFAULT;
-	node_list.nodes[0]->device.id.type = BM_TYPE_SYSTEM;
-	/* TBD: Get system PM capabilities (Sx states?) */
-
-	node_list.count++;
-
-	/*
-	 * Fixed Features:
-	 * ---------------
-	 * Enumerate fixed-feature devices (e.g. power and sleep buttons).
-	 */
-	if (acpi_fadt.pwr_button == 0) {
-		bm_add_fixed_feature_device(node_list.nodes[0],
-			BM_TYPE_FIXED_BUTTON, BM_HID_POWER_BUTTON);
-	}
-
-	if (acpi_fadt.sleep_button == 0) {
-		bm_add_fixed_feature_device(node_list.nodes[0],
-			BM_TYPE_FIXED_BUTTON, BM_HID_SLEEP_BUTTON);
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_handle
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_handle (
-	acpi_handle             acpi_handle,
-	BM_HANDLE               *device_handle)
-{
-	acpi_status             status = AE_NOT_FOUND;
-	u32			i = 0;
-
-	FUNCTION_TRACE("bm_get_handle");
-
-	if (!device_handle) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	*device_handle = BM_HANDLE_UNKNOWN;
-
-	/*
-	 * Search all devices for a match on the ACPI handle.
-	 */
-	for (i=0; i<node_list.count; i++) {
-
-		if (!node_list.nodes[i]) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) node entry [%p] detected.\n", device_handle));
-			status = AE_NULL_ENTRY;
-			break;
-		}
-
-		if (node_list.nodes[i]->device.acpi_handle == acpi_handle) {
-			*device_handle = node_list.nodes[i]->device.handle;
-			status = AE_OK;
-			break;
-		}
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_node
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_node (
-	BM_HANDLE               device_handle,
-	acpi_handle             acpi_handle,
-	BM_NODE			**node)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("bm_get_node");
-
-	if (!node) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/* busmgr failed to init, but we're being called by subordinate drivers */
-	if (node_list.count < 1) {
-		return_ACPI_STATUS(AE_NOT_FOUND);
-	}
-
-	/*
-	 * If no device handle, resolve acpi handle to device handle.
-	 */
-	if (!device_handle && acpi_handle) {
-		status = bm_get_handle(acpi_handle, &device_handle);
-		if (ACPI_FAILURE(status))
-			return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Valid device handle?
-	 */
-	if (device_handle > BM_HANDLES_MAX) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid node handle [%02x] detected.\n", device_handle));
-		return_ACPI_STATUS(AE_ERROR);
-	}
-
-	*node = node_list.nodes[device_handle];
-
-	/*
-	 * Valid node?
-	 */
-	if (!(*node)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) node entry [%02x] detected.\n", device_handle));
-		return_ACPI_STATUS(AE_NULL_ENTRY);
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_initialize
- *
- * PARAMETERS:  <none>
- *
- * RETURN:      Exception code.
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_initialize (void)
-{
-	acpi_status             status = AE_OK;
-	u32                     start = 0;
-	u32                     stop = 0;
-	u32                     elapsed = 0;
-
-	FUNCTION_TRACE("bm_initialize");
-
-	MEMSET(&node_list, 0, sizeof(BM_NODE_LIST));
-
-	status = acpi_get_timer(&start);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Building device hierarchy.\n"));
-
-	/*
-	 * Enumerate ACPI fixed-feature devices.
-	 */
-	status = bm_enumerate_fixed_features();
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Enumerate the ACPI namespace.
-	 */
-	status = bm_enumerate_namespace();
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	acpi_get_timer(&stop);
-	acpi_get_timer_duration(start, stop, &elapsed);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Building device hierarchy took [%d] microseconds.\n", elapsed));
-
-	/*
-	 * Display hierarchy.
-	 */
-	bm_print_hierarchy();
-
-	/*
-	 * Register for all standard and device-specific notifications.
-	 */
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Registering for all device notifications.\n"));
-
-	status = acpi_install_notify_handler(ACPI_ROOT_OBJECT,
-		ACPI_SYSTEM_NOTIFY, &bm_notify, NULL);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to register for standard notifications.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	status = acpi_install_notify_handler(ACPI_ROOT_OBJECT,
-		ACPI_DEVICE_NOTIFY, &bm_notify, NULL);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to register for device-specific notifications.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "ACPI Bus Manager enabled.\n"));
-
-	/*
-	 * Initialize built-in power resource driver.
-	 */
-	bm_pr_initialize();
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_terminate
- *
- * PARAMETERS:  <none>
- *
- * RETURN:      Exception code.
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_terminate (void)
-{
-	acpi_status             status = AE_OK;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_terminate");
-
-	/*
-	 * Terminate built-in power resource driver.
-	 */
-	bm_pr_terminate();
-
-	/*
-	 * Unregister for all notifications.
-	 */
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Unregistering for device notifications.\n"));
-
-	status = acpi_remove_notify_handler(ACPI_ROOT_OBJECT,
-		ACPI_SYSTEM_NOTIFY, &bm_notify);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to un-register for standard notifications.\n"));
-	}
-
-	status = acpi_remove_notify_handler(ACPI_ROOT_OBJECT,
-		ACPI_DEVICE_NOTIFY, &bm_notify);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to un-register for device-specific notifications.\n"));
-	}
-
-	/*
-	 * Parse through the device array, freeing all entries.
-	 */
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing device hierarchy.\n"));
-	for (i = 0; i < node_list.count; i++) {
-		if (node_list.nodes[i]) {
-			acpi_os_free(node_list.nodes[i]);
-		}
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "ACPI Bus Manager disabled.\n"));
-
-	return_ACPI_STATUS(AE_OK);
-}
diff -Nru a/drivers/acpi/ospm/busmgr/bm_osl.c b/drivers/acpi/ospm/busmgr/bm_osl.c
--- a/drivers/acpi/ospm/busmgr/bm_osl.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,390 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bm_osl.c
- *   $Revision: 17 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <linux/spinlock.h>
-#include <linux/poll.h>
-#include <asm/uaccess.h>
-#include <acpi.h>
-#include "bm.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - ACPI Bus Manager");
-MODULE_LICENSE("GPL");
-
-
-/*****************************************************************************
- *                               Types & Defines
- *****************************************************************************/
-
-typedef struct
-{
-	BM_HANDLE		device_handle;
-	char			*device_type;
-	char			*device_instance;
-	u32			event_type;
-	u32			event_data;
-	struct list_head	list;
-} BM_OSL_EVENT;
-
-
-#define BM_PROC_ROOT		"acpi"
-#define BM_PROC_EVENT		"event"
-#define BM_PROC_DEVICES		"devices"
-
-#define BM_MAX_STRING_LENGTH	80
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-struct proc_dir_entry		*bm_proc_root = NULL;
-static struct proc_dir_entry	*bm_proc_event = NULL;
-
-#ifdef ACPI_DEBUG
-static u32			save_dbg_layer;
-static u32			save_dbg_level;
-#endif /*ACPI_DEBUG*/
-
-extern BM_NODE_LIST		node_list;
-
-static spinlock_t		bm_osl_event_lock = SPIN_LOCK_UNLOCKED;
-
-static LIST_HEAD(bm_event_list);
-
-static DECLARE_WAIT_QUEUE_HEAD(bm_event_wait_queue);
-
-static int event_is_open = 0;
-
-
-/****************************************************************************
- *                                 Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:	bm_osl_generate_event
- *
- * DESCRIPTION: Generates an event for user-space consumption by writing
- *              the event data to the 'event' file.
- *
- ****************************************************************************/
-
-acpi_status
-bm_osl_generate_event (
-	BM_HANDLE		device_handle,
-	char			*device_type,
-	char			*device_instance,
-	u32			event_type,
-	u32			event_data)
-{
-	BM_OSL_EVENT		*event = NULL;
-	u32			flags = 0;
-
-	/* drop event on the floor if no one's listening */
-	if (!event_is_open)
-		return (AE_OK);
-
-	/*
-	 * Allocate a new event structure.
-	 */
-	event = acpi_os_callocate(sizeof(BM_OSL_EVENT));
-	if (!event)
-		goto alloc_error;
-
-	event->device_type = acpi_os_callocate(strlen(device_type)
-		+ sizeof(char));
-	if (!event->device_type)
-		goto alloc_error;
-
-	event->device_instance = acpi_os_callocate(strlen(device_instance)
-		+ sizeof(char));
-	if (!event->device_instance)
-		goto alloc_error;
-
-	/*
-	 * Set event data.
-	 */
-	event->device_handle = device_handle;
-	strcpy(event->device_type, device_type);
-	strcpy(event->device_instance, device_instance);
-	event->event_type = event_type;
-	event->event_data = event_data;
-
-	/*
-	 * Add to the end of our event list.
-	 */
-	spin_lock_irqsave(&bm_osl_event_lock, flags);
-	list_add_tail(&event->list, &bm_event_list);
-	spin_unlock_irqrestore(&bm_osl_event_lock, flags);
-
-	/*
-	 * Signal waiting threads (if any).
-	 */
-	wake_up_interruptible(&bm_event_wait_queue);
-
-	return(AE_OK);
-
-alloc_error:
-	if (event->device_instance)
-		acpi_os_free(event->device_instance);
-
-	if (event->device_type)
-		acpi_os_free(event->device_type);
-
-	if (event)
-		acpi_os_free(event);		
-
-	return (AE_NO_MEMORY);
-}
-
-static int bm_osl_open_event(struct inode *inode, struct file *file)
-{
-	spin_lock_irq (&bm_osl_event_lock);
-
-	if(event_is_open)
-		goto out_busy;
-
-	event_is_open = 1;
-
-	spin_unlock_irq (&bm_osl_event_lock);
-	return 0;
-
-out_busy:
-	spin_unlock_irq (&bm_osl_event_lock);
-	return -EBUSY;
-}
-
-
-static int bm_osl_close_event(struct inode *inode, struct file *file)
-{
-	event_is_open = 0;
-	return 0;
-}
-
-/****************************************************************************
- *
- * FUNCTION:	bm_osl_read_event
- *
- * DESCRIPTION: Handles reads to the 'event' file by blocking user-mode
- *              threads until data (an event) is generated.
- *
- ****************************************************************************/
-static ssize_t
-bm_osl_read_event(
-	struct file		*file,
-	char			*buf,
-	size_t			count,
-	loff_t			*ppos)
-{
-	BM_OSL_EVENT		*event = NULL;
-	unsigned long		flags = 0;
-	static char		str[BM_MAX_STRING_LENGTH];
-	static int		chars_remaining = 0;
-	static char 		*ptr;
-
-	if (!chars_remaining) {
-		DECLARE_WAITQUEUE(wait, current);
-
-		if (list_empty(&bm_event_list)) {
-
-			if (file->f_flags & O_NONBLOCK)
-				return -EAGAIN;
-
-			set_current_state(TASK_INTERRUPTIBLE);
-			add_wait_queue(&bm_event_wait_queue, &wait);
-
-			if (list_empty(&bm_event_list)) {
-				schedule();
-			}
-
-			remove_wait_queue(&bm_event_wait_queue, &wait);
-			set_current_state(TASK_RUNNING);
-
-			if (signal_pending(current)) {
-				return -ERESTARTSYS;
-			}
-		}
-
-		spin_lock_irqsave(&bm_osl_event_lock, flags);
-		event = list_entry(bm_event_list.next, BM_OSL_EVENT, list);
-		list_del(&event->list);
-		spin_unlock_irqrestore(&bm_osl_event_lock, flags);
-
-		chars_remaining = sprintf(str, "%s %s %08x %08x\n",
-			event->device_type, event->device_instance,
-			event->event_type, event->event_data);
-		ptr = str;
-
-		acpi_os_free(event->device_type);
-		acpi_os_free(event->device_instance);
-		acpi_os_free(event);
-	}
-
-	if (chars_remaining < count)
-		count = chars_remaining;
-	
-	if (copy_to_user(buf, ptr, count))
-		return -EFAULT;
-
-	*ppos += count;
-	chars_remaining -= count;
-	ptr += count;
-
-	return count;
-}
-
-/****************************************************************************
- *
- * FUNCTION:	bm_osl_poll_event
- *
- * DESCRIPTION: Handles poll() of the 'event' file by blocking user-mode 
- *              threads until data (an event) is generated.
- *
- ****************************************************************************/
-static unsigned int
-bm_osl_poll_event(
-	struct file		*file, 
-	poll_table		*wait)
-{
-	poll_wait(file, &bm_event_wait_queue, wait);
-	if (!list_empty(&bm_event_list))
-		return POLLIN | POLLRDNORM;
-	return 0;
-}
-
-struct file_operations proc_event_operations = {
-	open:		bm_osl_open_event,
-	read:		bm_osl_read_event,
-	release:	bm_osl_close_event,
-	poll:		bm_osl_poll_event,	
-};
-
-/****************************************************************************
- *
- * FUNCTION:    bm_osl_init
- *
- ****************************************************************************/
-
-int
-bm_osl_init(void)
-{
-	acpi_status		status = AE_OK;
-
-	status = acpi_subsystem_status();
-	if (ACPI_FAILURE(status))
-		return -ENODEV;
-
-	bm_proc_root = proc_mkdir(BM_PROC_ROOT, NULL);
-	if (!bm_proc_root) {
-		return(AE_ERROR);
-	}
-
-	bm_proc_event = create_proc_entry(BM_PROC_EVENT, S_IRUSR, bm_proc_root);
-	if (bm_proc_event) {
-		bm_proc_event->proc_fops = &proc_event_operations;
-	}
-
-	status = bm_initialize();
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_osl_cleanup
- *
- ****************************************************************************/
-
-void
-bm_osl_cleanup(void)
-{
-	bm_terminate();
-
-	if (bm_proc_event) {
-		remove_proc_entry(BM_PROC_EVENT, bm_proc_root);
-		bm_proc_event = NULL;
-	}
-
-	if (bm_proc_root) {
-		remove_proc_entry(BM_PROC_ROOT, NULL);
-		bm_proc_root = NULL;
-	}
-
-	return;
-}
-
-
-module_init(bm_osl_init);
-module_exit(bm_osl_cleanup);
-
-
-/****************************************************************************
- *                                  Symbols
- ****************************************************************************/
-
-/* bm.c */
-
-EXPORT_SYMBOL(bm_get_node);
-
-/* bmdriver.c */
-
-EXPORT_SYMBOL(bm_get_device_power_state);
-EXPORT_SYMBOL(bm_set_device_power_state);
-EXPORT_SYMBOL(bm_get_device_info);
-EXPORT_SYMBOL(bm_get_device_status);
-EXPORT_SYMBOL(bm_get_device_context);
-EXPORT_SYMBOL(bm_register_driver);
-EXPORT_SYMBOL(bm_unregister_driver);
-
-/* bmsearch.c */
-
-EXPORT_SYMBOL(bm_search);
-
-/* bmrequest.c */
-
-EXPORT_SYMBOL(bm_request);
-
-/* bmutils.c */
-
-EXPORT_SYMBOL(bm_extract_package_data);
-EXPORT_SYMBOL(bm_evaluate_object);
-EXPORT_SYMBOL(bm_evaluate_simple_integer);
-EXPORT_SYMBOL(bm_evaluate_reference_list);
-EXPORT_SYMBOL(bm_copy_to_buffer);
-EXPORT_SYMBOL(bm_cast_buffer);
-
-/* bm_proc.c */
-
-EXPORT_SYMBOL(bm_osl_generate_event);
-EXPORT_SYMBOL(bm_proc_root);
diff -Nru a/drivers/acpi/ospm/busmgr/bmdriver.c b/drivers/acpi/ospm/busmgr/bmdriver.c
--- a/drivers/acpi/ospm/busmgr/bmdriver.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,469 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bmdriver.c
- *   $Revision: 21 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bmdriver")
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_device_power_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_device_power_state (
-	BM_HANDLE               device_handle,
-	BM_POWER_STATE		*state)
-{
-	acpi_status             status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_get_device_power_state");
-
-	if (!state) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	*state = ACPI_STATE_UNKNOWN;
-
-	/*
-	 * Resolve device handle to node.
-	 */
-	status = bm_get_node(device_handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Get the current power state.
-	 */
-	status = bm_get_power_state(node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	*state = node->device.power.state;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_set_device_power_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_set_device_power_state (
-	BM_HANDLE               device_handle,
-	BM_POWER_STATE		state)
-{
-	acpi_status           status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_set_device_power_state");
-
-	/*
-	 * Resolve device handle to node.
-	 */
-	status = bm_get_node(device_handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Set the current power state.
-	 */
-	status = bm_set_power_state(node, state);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_device_status
- *
- * PARAMETERS:
- *    device_handle is really an index number into the array of BM_DEVICE
- *                  structures in info_list.  This data item is passed to
- *                  the registered program's "notify" callback.  It is used
- *                  to retrieve the specific BM_DEVICE structure instance
- *                  associated with the callback.
- *    device_status is a pointer that receives the result of processing
- *                  the device's associated ACPI _STA.
- *
- * RETURN:
- *    The acpi_status value indicates success AE_OK or failure of the function
- *
- * DESCRIPTION: Evaluates the device's ACPI _STA, if it is present.
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_device_status (
-	BM_HANDLE               device_handle,
-	BM_DEVICE_STATUS        *device_status)
-{
-	acpi_status           status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_get_device_status");
-
-	if (!device_status) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	*device_status = BM_STATUS_UNKNOWN;
-
-	/*
-	 * Resolve device handle to node.
-	 */
-	status = bm_get_node(device_handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Parent Present?
-	 * ---------------
-	 * If the parent isn't present we can't evalute _STA on the child.
-	 * Return an unknown status.
-	 */
-	if (!BM_NODE_PRESENT(node->parent)) {
-		return_ACPI_STATUS(AE_OK);
-	}
-	
-	/*
-	 * Dynamic Status?
-	 * ---------------
-	 * If _STA isn't present we just return the default status.
-	 */
-	if (!(node->device.flags & BM_FLAGS_DYNAMIC_STATUS)) {
-		*device_status = BM_STATUS_DEFAULT;
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	/*
-	 * Evaluate _STA:
-	 * --------------
-	 */
-	status = bm_evaluate_simple_integer(node->device.acpi_handle, "_STA",
-		&(node->device.status));
-	if (ACPI_SUCCESS(status)) {
-		*device_status = node->device.status;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_device_info
- *
- * PARAMETERS:
- *    device_handle An index used to retrieve the associated BM_DEVICE info.
- *    device        A pointer to a BM_DEVICE structure instance pointer.
- *                  This pointed to BM_DEVICE structure will contain the
- *                  this device's information.
- *
- * RETURN:
- *    The acpi_status value indicates success AE_OK or failure of the function
- *
- * DESCRIPTION:
- *    Using the device_handle this function retrieves this device's
- *    BM_DEVICE structure instance and save's it in device.
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_device_info (
-	BM_HANDLE               device_handle,
-	BM_DEVICE               **device)
-{
-	acpi_status           status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_get_device_info");
-
-	if (!device) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Resolve device handle to internal device.
-	 */
-	status = bm_get_node(device_handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	*device = &(node->device);
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_device_context
- *
- *    device_handle An index used to retrieve the associated BM_DEVICE info.
- *    context       A pointer to a BM_DRIVER_CONTEXT structure instance.
- *
- * RETURN:
- *    The acpi_status value indicates success AE_OK or failure of the function
- *
- * DESCRIPTION:
- *    Using the device_handle this function retrieves this device's
- *    BM_DRIVER_CONTEXT structure instance and save's it in context.
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_device_context (
-	BM_HANDLE               device_handle,
-	BM_DRIVER_CONTEXT	*context)
-{
-	acpi_status           status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_get_device_context");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	*context = NULL;
-
-	/*
-	 * Resolve device handle to internal device.
-	 */
-	status = bm_get_node(device_handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	if (!node->driver.context) {
-		return_ACPI_STATUS(AE_NULL_ENTRY);
-	}
-
-	*context = node->driver.context;
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_register_driver
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_register_driver (
-	BM_DEVICE_ID		*criteria,
-	BM_DRIVER		*driver)
-{
-	acpi_status           status = AE_NOT_FOUND;
-	BM_HANDLE_LIST          device_list;
-	BM_NODE			*node = NULL;
-	BM_DEVICE		*device = NULL;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_register_driver");
-
-	if (!criteria || !driver || !driver->notify || !driver->request) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&device_list, 0, sizeof(BM_HANDLE_LIST));
-
-	/*
-	 * Find Matches:
-	 * -------------
-	 * Search through the entire device hierarchy for matches against
-	 * the given device criteria.
-	 */
-	status = bm_search(BM_HANDLE_ROOT, criteria, &device_list);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Install driver:
-	 * ----------------
-	 * For each match, record the driver information and execute the
-	 * driver's Notify() funciton (if present) to notify the driver
-	 * of the device's presence.
-	 */
-	for (i = 0; i < device_list.count; i++) {
-
-		/* Resolve the device handle. */
-		status = bm_get_node(device_list.handles[i], 0, &node);
-		if (ACPI_FAILURE(status)) {
-			continue;
-		}
-
-		device = &(node->device);
-
-		/*
-		 * Make sure another driver hasn't already registered for
-		 * this device.
-		 */
-		if (BM_IS_DRIVER_CONTROL(device)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Another driver has already registered for device [%02x].\n", device->handle));
-			continue;
-		}
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Registering driver for device [%02x].\n", device->handle));
-
-		/* Notify driver of new device. */
-		status = driver->notify(BM_NOTIFY_DEVICE_ADDED,
-			node->device.handle, &(node->driver.context));
-		if (ACPI_SUCCESS(status)) {
-			node->driver.notify = driver->notify;
-			node->driver.request = driver->request;
-			node->device.flags |= BM_FLAGS_DRIVER_CONTROL;
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_unregister_driver
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_unregister_driver (
-	BM_DEVICE_ID		*criteria,
-	BM_DRIVER		*driver)
-{
-	acpi_status           status = AE_NOT_FOUND;
-	BM_HANDLE_LIST          device_list;
-	BM_NODE			*node = NULL;
-	BM_DEVICE		*device = NULL;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_unregister_driver");
-
-	if (!criteria || !driver || !driver->notify || !driver->request) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&device_list, 0, sizeof(BM_HANDLE_LIST));
-
-	/*
-	 * Find Matches:
-	 * -------------
-	 * Search through the entire device hierarchy for matches against
-	 * the given device criteria.
-	 */
-	status = bm_search(BM_HANDLE_ROOT, criteria, &device_list);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Remove driver:
-	 * ---------------
-	 * For each match, execute the driver's Notify() function to allow
-	 * the driver to cleanup each device instance.
-	 */
-	for (i = 0; i < device_list.count; i++) {
-
-		/* Resolve the device handle. */
-		status = bm_get_node(device_list.handles[i], 0, &node);
-		if (ACPI_FAILURE(status)) {
-			continue;
-		}
-
-		device = &(node->device);
-
-		/*
-		 * Make sure driver has really registered for this device.
-		 */
-		if (!BM_IS_DRIVER_CONTROL(device)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Driver hasn't registered for device [%02x].\n", device->handle));
-			continue;
-		}
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Unregistering driver for device [%02x].\n", device->handle));
-
-		/* Notify driver of device removal. */
-		status = node->driver.notify(BM_NOTIFY_DEVICE_REMOVED,
-			node->device.handle, &(node->driver.context));
-		if (ACPI_SUCCESS(status)) {
-			node->driver.notify = NULL;
-			node->driver.request = NULL;
-			node->driver.context = NULL;
-			node->device.flags &= ~BM_FLAGS_DRIVER_CONTROL;
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
diff -Nru a/drivers/acpi/ospm/busmgr/bmnotify.c b/drivers/acpi/ospm/busmgr/bmnotify.c
--- a/drivers/acpi/ospm/busmgr/bmnotify.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,312 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bmnotify.c
- *   $Revision: 21 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-
-
-#define _COMPONENT		ACPI_BUS
-	 MODULE_NAME		("bmnotify")
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_generate_notify
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_generate_notify (
-	BM_NODE			*node,
-	u32			notify_type)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE		*device = NULL;
-
-	FUNCTION_TRACE("bm_generate_notify");
-
-	if (!node) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	device = &(node->device);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Sending notify [%02x] to device [%02x].\n", notify_type, node->device.handle));
-
-	if (!BM_IS_DRIVER_CONTROL(device)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "No driver installed for device [%02x].\n", device->handle));
-		return_ACPI_STATUS(AE_NOT_EXIST);
-	}
-
-	status = node->driver.notify(notify_type, node->device.handle,
-		&(node->driver.context));
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_device_check
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_device_check (
-	BM_NODE			*node,
-	u32			*status_change)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	BM_DEVICE_STATUS	old_status = BM_STATUS_UNKNOWN;
-
-	FUNCTION_TRACE("bm_device_check");
-
-	if (!node) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	device = &(node->device);
-
-	if (status_change) {
-		*status_change = FALSE;
-	}
-
-	old_status = device->status;
-
-	/*
-	 * Parent Present?
-	 * ---------------
-	 * Only check this device if its parent is present (which implies
-	 * this device MAY be present).
-	 */
-	if (!BM_NODE_PRESENT(node->parent)) {
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	/*
-	 * Get Status:
-	 * -----------
-	 * And see if the status has changed.
-	 */
-	status = bm_get_status(device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-	
-	if (old_status == node->device.status) {
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	if (status_change) {
-		*status_change = TRUE;
-	}
-	
-	/*
-	 * Device Insertion?
-	 * -----------------
-	 */
-	if ((device->status & BM_STATUS_PRESENT) &&
-		!(old_status & BM_STATUS_PRESENT)) {
-		/* TBD: Make sure driver is loaded, and if not, load. */
-		status = bm_generate_notify(node, BM_NOTIFY_DEVICE_ADDED);
-	}
-
-	/*
-	 * Device Removal?
-	 * ---------------
-	 */
-	else if (!(device->status & BM_STATUS_PRESENT) &&
-		(old_status & BM_STATUS_PRESENT)) {
-		/* TBD: Unload driver if last device instance. */
-		status = bm_generate_notify(node, BM_NOTIFY_DEVICE_REMOVED);
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_bus_check
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_bus_check (
-	BM_NODE			*parent_node)
-{
-	acpi_status             status = AE_OK;
-	u32			status_change = FALSE;
-
-	FUNCTION_TRACE("bm_bus_check");
-
-	if (!parent_node) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Status Change?
-	 * --------------
-	 */
-	status = bm_device_check(parent_node, &status_change);
-	if (ACPI_FAILURE(status) || !status_change) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Enumerate Scope:
-	 * ----------------
-	 * TBD: Enumerate child devices within this device's scope and
-	 *       run bm_device_check()'s on them...
-	 */
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_notify
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-bm_notify (
-	acpi_handle             acpi_handle,
-	u32                     notify_value,
-	void                    *context)
-{
-	acpi_status             status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_notify");
-
-	/*
-	 * Resolve the ACPI handle.
-	 */
-	status = bm_get_node(0, acpi_handle, &node);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Recieved notify [%02x] for unknown device [%p].\n", notify_value, acpi_handle));
-		return_VOID;
-	}
-
-	/*
-	 * Device-Specific or Standard?
-	 * ----------------------------
-	 * Device-specific notifies are forwarded to the control module's
-	 * notify() function for processing.  Standard notifies are handled
-	 * internally.
-	 */
-	if (notify_value > 0x7F) {
-		status = bm_generate_notify(node, notify_value);
-	}
-	else {
-		switch (notify_value) {
-
-		case BM_NOTIFY_BUS_CHECK:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received BUS CHECK notification for device [%02x].\n", node->device.handle));
-			status = bm_bus_check(node);
-			break;
-
-		case BM_NOTIFY_DEVICE_CHECK:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received DEVICE CHECK notification for device [%02x].\n", node->device.handle));
-			status = bm_device_check(node, NULL);
-			break;
-
-		case BM_NOTIFY_DEVICE_WAKE:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received DEVICE WAKE notification for device [%02x].\n", node->device.handle));
-			/* TBD */
-			break;
-
-		case BM_NOTIFY_EJECT_REQUEST:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received EJECT REQUEST notification for device [%02x].\n", node->device.handle));
-			/* TBD */
-			break;
-
-		case BM_NOTIFY_DEVICE_CHECK_LIGHT:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received DEVICE CHECK LIGHT notification for device [%02x].\n", node->device.handle));
-			/* TBD: Exactly what does the 'light' mean? */
-			status = bm_device_check(node, NULL);
-			break;
-
-		case BM_NOTIFY_FREQUENCY_MISMATCH:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received FREQUENCY MISMATCH notification for device [%02x].\n", node->device.handle));
-			/* TBD */
-			break;
-
-		case BM_NOTIFY_BUS_MODE_MISMATCH:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received BUS MODE MISMATCH notification for device [%02x].\n", node->device.handle));
-			/* TBD */
-			break;
-
-		case BM_NOTIFY_POWER_FAULT:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received POWER FAULT notification.\n"));
-			/* TBD */
-			break;
-
-		default:
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received unknown/unsupported notification.\n"));
-			break;
-		}
-	}
-
-	return_VOID;
-}
-
-
diff -Nru a/drivers/acpi/ospm/busmgr/bmpm.c b/drivers/acpi/ospm/busmgr/bmpm.c
--- a/drivers/acpi/ospm/busmgr/bmpm.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,442 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bmpm.c
- *   $Revision: 14 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-#include "bmpower.h"
-
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bmpm")
-
-
-/****************************************************************************
- *                             Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_inferred_power_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_inferred_power_state (
-	BM_DEVICE               *device)
-{
-	acpi_status             status = AE_OK;
-	BM_HANDLE_LIST          pr_list;
-	BM_POWER_STATE          list_state = ACPI_STATE_UNKNOWN;
-	char                    object_name[5] = {'_','P','R','0','\0'};
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_get_inferred_power_state");
-
-	if (!device) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&pr_list, 0, sizeof(BM_HANDLE_LIST));
-
-	device->power.state = ACPI_STATE_D3;
-
-	/*
-	 * Calculate Power State:
-	 * ----------------------
-	 * Try to infer the devices's power state by checking the state of
-	 * the devices's power resources.  We start by evaluating _PR0
-	 * (resource requirements at D0) and work through _PR1 and _PR2.
-	 * We know the current devices power state when all resources (for
-	 * a give Dx state) are ON.  If no power resources are on then the
-	 * device is assumed to be off (D3).
-	 */
-	for (i=ACPI_STATE_D0; i<ACPI_STATE_D3; i++) {
-
-		object_name[3] = '0' + i;
-
-		status = bm_evaluate_reference_list(device->acpi_handle,
-			object_name, &pr_list);
-
-		if (ACPI_SUCCESS(status)) {
-
-			status = bm_pr_list_get_state(&pr_list, &list_state);
-
-			if (ACPI_SUCCESS(status)) {
-
-				if (list_state == ACPI_STATE_D0) {
-					device->power.state = i;
-					break;
-				}
-			}
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_power_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_power_state (
-	BM_NODE			*node)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE               *device = NULL;
-
-	FUNCTION_TRACE("bm_get_power_state");
-
-	if (!node || !node->parent) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	device = &(node->device);
-
-	device->power.state = ACPI_STATE_UNKNOWN;
-
-	/*
-	 * Power Control?
-	 * --------------
-	 * If this device isn't directly power manageable (e.g. doesn't
-	 * include _PR0/_PS0) then there's nothing to do (state is static).
-	 */
-	if (!BM_IS_POWER_CONTROL(device)) {
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	/*
-	 * Parent Present?
-	 * ---------------
-	 * Make sure the parent is present before mucking with the child.
-	 */
-	if (!BM_NODE_PRESENT(node->parent)) {
-		return_ACPI_STATUS(AE_NOT_EXIST);
-	}
-	
-	/*
-	 * Get Power State:
-	 * ----------------
-	 * Either directly (via _PSC) or inferred (via power resource
-	 * dependencies).
-	 */
-	if (BM_IS_POWER_STATE(device)) {
-		status = bm_evaluate_simple_integer(device->acpi_handle,
-			"_PSC", &(device->power.state));
-	}
-	else {
-		status = bm_get_inferred_power_state(device);
-	}
-
-	if (ACPI_SUCCESS(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Device [%02x] is at power state [D%d].\n", device->handle, device->power.state));
-	}
-	else {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Error getting power state for device [%02x]\n", device->handle));
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_set_power_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_set_power_state (
-	BM_NODE			*node,
-	BM_POWER_STATE          state)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	BM_DEVICE		*parent_device = NULL;
-	BM_HANDLE_LIST          current_list;
-	BM_HANDLE_LIST          target_list;
-	char                    object_name[5] = {'_','P','R','0','\0'};
-
-	FUNCTION_TRACE("bm_set_power_state");
-
-	if (!node || !node->parent || (state > ACPI_STATE_D3)) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&current_list, 0, sizeof(BM_HANDLE_LIST));
-	MEMSET(&target_list, 0, sizeof(BM_HANDLE_LIST));
-
-	device = &(node->device);
-	parent_device = &(node->parent->device);
-
-	/*
-	 * Power Control?
-	 * --------------
-	 * If this device isn't directly power manageable (e.g. doesn't
-	 * include _PR0/_PS0) then return an error (can't set state).
-	 */
-	if (!BM_IS_POWER_CONTROL(device)) {
-		return_ACPI_STATUS(AE_ERROR);
-	}
-
-	/*
-	 * Parent Present?
-	 * ---------------
-	 * Make sure the parent is present before mucking with the child.
-	 */
-	if (!BM_NODE_PRESENT(node->parent)) {
-		return_ACPI_STATUS(AE_NOT_EXIST);
-	}
-	
-	/*
-	 * Check Parent's Power State:
-	 * ---------------------------
-	 * Can't be in a higher power state (lower Dx value) than parent.
-	 */
-	if (state < parent_device->power.state) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Cannot set device [%02x] to a higher-powered state than parent_device.\n", device->handle));
-		return_ACPI_STATUS(AE_ERROR);
-	}
-
-	/*
-	 * Get Resources:
-	 * --------------
-	 * Get the power resources associated with the device's current
-	 * and target power states.
-	 */
-	if (device->power.state != ACPI_STATE_UNKNOWN) {
-		object_name[3] = '0' + device->power.state;
-		bm_evaluate_reference_list(device->acpi_handle,
-			object_name, &current_list);
-	}
-
-	object_name[3] = '0' + state;
-	bm_evaluate_reference_list(device->acpi_handle, object_name,
-		&target_list);
-
-	/*
-	 * Transition Resources:
-	 * ---------------------
-	 * Transition all power resources referenced by this device to
-	 * the correct power state (taking into consideration sequencing
-	 * and dependencies to other devices).
-	 */
-	if (current_list.count || target_list.count) {
-		status = bm_pr_list_transition(&current_list, &target_list);
-	}
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Execute _PSx:
-	 * -------------
-	 * Execute the _PSx method corresponding to the target Dx state,
-	 * if it exists.
-	 */
-	object_name[2] = 'S';
-	object_name[3] = '0' + state;
-	bm_evaluate_object(device->acpi_handle, object_name, NULL, NULL);
-
-	if (ACPI_SUCCESS(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Device [%02x] is now at [D%d].\n", device->handle, state));
-		device->power.state = state;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_get_pm_capabilities
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_get_pm_capabilities (
-	BM_NODE			*node)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	BM_DEVICE		*parent_device = NULL;
-	acpi_handle             acpi_handle = NULL;
-	BM_POWER_STATE          dx_supported = ACPI_STATE_UNKNOWN;
-	char                    object_name[5] = {'_','S','0','D','\0'};
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_get_pm_capabilities");
-
-	if (!node || !node->parent) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	device = &(node->device);
-	parent_device = &(node->parent->device);
-
-	/*
-	 * Power Management Flags:
-	 * -----------------------
-	 */
-	if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_PSC",
-		&acpi_handle))) {
-		device->power.flags |= BM_FLAGS_POWER_STATE;
-	}
-
-	if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_IRC",
-		&acpi_handle))) {
-		device->power.flags |= BM_FLAGS_INRUSH_CURRENT;
-	}
-
-	if (ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_PRW",
-		&acpi_handle))) {
-		device->power.flags |= BM_FLAGS_WAKE_CAPABLE;
-	}
-
-	/*
-	 * Device Power State:
-	 * -------------------
-	 * Note that we can't get the device's power state until we've
-	 * initialized all power resources, so for now we just set to
-	 * unknown.
-	 */
-	device->power.state = ACPI_STATE_UNKNOWN;
-
-	/*
-	 * Dx Supported in S0:
-	 * -------------------
-	 * Figure out which Dx states are supported by this device for the
-	 * S0 (working) state.  Note that D0 and D3 are required (assumed).
-	 */
-	device->power.dx_supported[ACPI_STATE_S0] = BM_FLAGS_D0_SUPPORT |
-		BM_FLAGS_D3_SUPPORT;
-
-	if ((ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_PR1",
-		&acpi_handle))) ||
-		(ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_PS1",
-		&acpi_handle)))) {
-		device->power.dx_supported[ACPI_STATE_S0] |=
-			BM_FLAGS_D1_SUPPORT;
-	}
-
-	if ((ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_PR2",
-		&acpi_handle))) ||
-		(ACPI_SUCCESS(acpi_get_handle(device->acpi_handle, "_PS2",
-		&acpi_handle)))) {
-		device->power.dx_supported[ACPI_STATE_S0] |=
-			BM_FLAGS_D2_SUPPORT;
-	}
-
-	/*
-	 * Dx Supported in S1-S5:
-	 * ----------------------
-	 * Figure out which Dx states are supported by this device for
-	 * all other Sx states.
-	 */
-	for (i = ACPI_STATE_S1; i <= ACPI_STATE_S5; i++) {
-
-		/*
-		 * D3 support is assumed (off is always possible!).
-		 */
-		device->power.dx_supported[i] = BM_FLAGS_D3_SUPPORT;
-
-		/*
-		 * Evalute _Sx_d:
-		 * -------------
-		 * Which returns the highest (power) Dx state supported in
-		 * this system (Sx) state.  We convert this value to a bit
-		 * mask of supported states (conceptually simpler).
-		 */
-		status = bm_evaluate_simple_integer(device->acpi_handle,
-			object_name, &dx_supported);
-		if (ACPI_SUCCESS(status)) {
-			switch (dx_supported) {
-			case 0:
-				device->power.dx_supported[i] |=
-					BM_FLAGS_D0_SUPPORT;
-				/* fall through */
-			case 1:
-				device->power.dx_supported[i] |=
-					BM_FLAGS_D1_SUPPORT;
-				/* fall through */
-			case 2:
-				device->power.dx_supported[i] |=
-					BM_FLAGS_D2_SUPPORT;
-				/* fall through */
-			case 3:
-				device->power.dx_supported[i] |=
-					BM_FLAGS_D3_SUPPORT;
-				break;
-			}
-
-			/*
-			 * Validate:
-			 * ---------
-			 * Mask of any states that _Sx_d falsely advertises
-			 * (e.g.claims D1 support but neither _PR2 or _PS2
-			 * exist).  In other words, S1-S5 can't offer a Dx
-			 * state that isn't supported by S0.
-			 */
-			device->power.dx_supported[i] &=
-				device->power.dx_supported[ACPI_STATE_S0];
-		}
-
-		object_name[2]++;
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
diff -Nru a/drivers/acpi/ospm/busmgr/bmpower.c b/drivers/acpi/ospm/busmgr/bmpower.c
--- a/drivers/acpi/ospm/busmgr/bmpower.c	Fri Mar 15 17:51:04 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,664 +0,0 @@
-/****************************************************************************
- *
- * Module Name: bmpower.c - Driver for ACPI Power Resource 'devices'
- *   $Revision: 20 $
- *
- ****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * TBD: 1. Sequencing of power resource list transitions.
- *	2. Global serialization of power resource transtions (see ACPI
- *         spec section 7.1.2/7.1.3).
- *      3. Better error handling.
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-#include "bmpower.h"
-
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bmpower")
-
-
-/****************************************************************************
- *                             Function Prototypes
- ****************************************************************************/
-
-acpi_status
-bm_pr_notify (
-	BM_NOTIFY               notify_type,
-	BM_HANDLE               device_handle,
-	void                    **context);
-	
-acpi_status
-bm_pr_request (
-	BM_REQUEST		*request,
-	void                    *context);
-
-	
-/****************************************************************************
- *                             Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_print
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_print (
-	BM_POWER_RESOURCE	*pr)
-{
-	acpi_buffer             buffer;
-
-	PROC_NAME("bm_pr_print");
-
-	if (!pr) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return(AE_NO_MEMORY);
-	}
-
-	acpi_get_name(pr->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	acpi_os_printf("Power Resource: found\n");
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Power_resource[%02x]:[%p] %s\n", pr->device_handle, pr->acpi_handle, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   system_level[S%d] resource_order[%d]\n", pr->system_level, pr->resource_order));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   state[D%d] reference_count[%d]\n", pr->state, pr->reference_count));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_get_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_get_state (
-	BM_POWER_RESOURCE	*pr)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_STATUS        device_status = BM_STATUS_UNKNOWN;
-
-	FUNCTION_TRACE("bm_pr_get_state");
-
-	if (!pr) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	pr->state = ACPI_STATE_UNKNOWN;
-
-	/*
-	 * Evaluate _STA:
-	 * --------------
-	 * Evalute _STA to determine whether the power resource is ON or OFF.
-	 * Note that if the power resource isn't present we'll get AE_OK but
-	 * an unknown status.
-	 */
-	status = bm_get_device_status(pr->device_handle, &device_status);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Error reading status for power resource [%02x].\n", pr->device_handle));
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Mask off all bits but the first as some systems return non-standard
-	 * values (e.g. 0x51).
-	 */
-	switch (device_status & 0x01) {
-	case 0:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Power resource [%02x] is OFF.\n", pr->device_handle));
-		pr->state = ACPI_STATE_D3;
-		break;
-	case 1:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Power resource [%02x] is ON.\n", pr->device_handle));
-		pr->state = ACPI_STATE_D0;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_set_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_set_state (
-	BM_POWER_RESOURCE	*pr,
-	BM_POWER_STATE          target_state)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("bm_pr_set_state");
-
-	if (!pr) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	status = bm_pr_get_state(pr);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	if (target_state == pr->state) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Power resource [%02x] already at target power state [D%d].\n", pr->device_handle, pr->state));
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	switch (target_state) {
-
-	case ACPI_STATE_D0:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Turning power resource [%02x] ON.\n", pr->device_handle));
-		status = bm_evaluate_object(pr->acpi_handle, "_ON", NULL, NULL);
-		break;
-
-	case ACPI_STATE_D3:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Turning power resource [%02x] OFF.\n", pr->device_handle));
-		status = bm_evaluate_object(pr->acpi_handle, "_OFF", NULL, NULL);
-		break;
-
-	default:
-		status = AE_BAD_PARAMETER;
-		break;
-	}
-
-	status = bm_pr_get_state(pr);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_list_get_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_list_get_state (
-	BM_HANDLE_LIST          *pr_list,
-	BM_POWER_STATE          *power_state)
-{
-	acpi_status             status = AE_OK;
-	BM_POWER_RESOURCE	*pr = NULL;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_pr_list_get_state");
-
-	if (!pr_list || !power_state) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (pr_list->count < 1) {
-		pr->state = ACPI_STATE_UNKNOWN;
-		return_ACPI_STATUS(AE_ERROR);
-	}
-
-	(*power_state) = ACPI_STATE_D0;
-
-	/*
-	 * Calculate Current power_state:
-	 * -----------------------------
-	 * The current state of a list of power resources is ON if all
-	 * power resources are currently in the ON state.  In other words,
-	 * if any power resource in the list is OFF then the collection
-	 * isn't fully ON.
-	 */
-	for (i = 0; i < pr_list->count; i++) {
-
-		status = bm_get_device_context(pr_list->handles[i],
-			(BM_DRIVER_CONTEXT*)(&pr));
-		if (ACPI_FAILURE(status)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Invalid reference to power resource [%02x].\n", pr_list->handles[i]));
-			(*power_state) = ACPI_STATE_UNKNOWN;
-			break;
-		}
-
-		status = bm_pr_get_state(pr);
-		if (ACPI_FAILURE(status)) {
-			(*power_state) = ACPI_STATE_UNKNOWN;
-			break;
-		}
-
-		if (pr->state != ACPI_STATE_D0) {
-			(*power_state) = pr->state;
-			break;
-		}
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_list_transition
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_list_transition (
-	BM_HANDLE_LIST          *current_list,
-	BM_HANDLE_LIST          *target_list)
-{
-	acpi_status             status = AE_OK;
-	BM_POWER_RESOURCE	*pr = NULL;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_pr_list_transition");
-
-	if (!current_list || !target_list) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Reference Target:
-	 * -----------------
-	 * Reference all resources for the target power state first (so
-	 * the device doesn't get turned off while transitioning).  Power
-	 * resources that aren't on (new reference count of 1) are turned on.
-	 */
-	for (i = 0; i < target_list->count; i++) {
-
-		status = bm_get_device_context(target_list->handles[i],
-			(BM_DRIVER_CONTEXT*)(&pr));
-		if (ACPI_FAILURE(status)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Invalid reference to power resource [%02x].\n", target_list->handles[i]));
-			continue;
-		}
-
-		if (++pr->reference_count == 1) {
-			/* TBD: Need ordering based upon resource_order */
-			status = bm_pr_set_state(pr, ACPI_STATE_D0);
-			if (ACPI_FAILURE(status)) {
-				/* TBD: How do we handle this? */
-				ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to change power state for power resource [%02x].\n", target_list->handles[i]));
-			}
-		}
-	}
-
-	/*
-	 * Dereference Current:
-	 * --------------------
-	 * Dereference all resources for the current power state.  Power
-	 * resources no longer referenced (new reference count of 0) are
-	 * turned off.
-	 */
-	for (i = 0; i < current_list->count; i++) {
-
-		status = bm_get_device_context(current_list->handles[i],
-			(BM_DRIVER_CONTEXT*)(&pr));
-		if (ACPI_FAILURE(status)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Invalid reference to power resource [%02x].\n", target_list->handles[i]));
-			continue;
-		}
-
-		if (--pr->reference_count == 0) {
-			/* TBD: Need ordering based upon resource_order */
-			status = bm_pr_set_state(pr, ACPI_STATE_D3);
-			if (ACPI_FAILURE(status)) {
-				/* TBD: How do we handle this? */
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unable to change power state for power resource [%02x].\n", current_list->handles[i]));
-			}
-		}
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_add_device
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_add_device (
-	BM_HANDLE               device_handle,
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-	BM_POWER_RESOURCE	*pr = NULL;
-	BM_DEVICE		*device = NULL;
-	acpi_buffer		buffer;
-	acpi_object		acpi_object;
-
-	FUNCTION_TRACE("bm_pr_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding power resource [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	buffer.length = sizeof(acpi_object);
-	buffer.pointer = &acpi_object;
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Allocate a new BM_POWER_RESOURCE structure.
-	 */
-	pr = acpi_os_callocate(sizeof(BM_POWER_RESOURCE));
-	if (!pr) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	pr->device_handle = device->handle;
-	pr->acpi_handle = device->acpi_handle;
-
-	/*
-	 * Get information on this power resource.
-	 */
-	status = acpi_evaluate_object(pr->acpi_handle, NULL, NULL, &buffer);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	pr->system_level = acpi_object.power_resource.system_level;
-	pr->resource_order = acpi_object.power_resource.resource_order;
-	pr->state = ACPI_STATE_UNKNOWN;
-	pr->reference_count = 0;
-
-	/*
-	 * Get the power resource's current state (ON|OFF).
-	 */
-	status = bm_pr_get_state(pr);
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(pr);
-	}
-	else {
-		*context = pr;
-		bm_pr_print(pr);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_remove_device
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_remove_device (
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-	BM_POWER_RESOURCE	*pr = NULL;
-
-	FUNCTION_TRACE("bm_pr_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	pr = (BM_POWER_RESOURCE*)*context;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing power resource [%02x].\n", pr->device_handle));
-
-	acpi_os_free(pr);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_initialize
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_initialize (void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("bm_pr_initialize");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	criteria.type = BM_TYPE_POWER_RESOURCE;
-
-	driver.notify = &bm_pr_notify;
-	driver.request = &bm_pr_request;
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_terminate
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_terminate (void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("bm_pr_terminate");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	criteria.type = BM_TYPE_POWER_RESOURCE;
-
-	driver.notify = &bm_pr_notify;
-	driver.request = &bm_pr_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_notify
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_notify (
-	BM_NOTIFY               notify_type,
-	BM_HANDLE               device_handle,
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("bm_pr_notify");
-
-	switch (notify_type) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = bm_pr_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = bm_pr_remove_device(context);
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_pr_request
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_pr_request (
-	BM_REQUEST		*request,
-	void                    *context)
-{
-	acpi_status             status = AE_OK;
-	BM_POWER_RESOURCE	*pr = NULL;
-
-	FUNCTION_TRACE("bm_pr_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * context contains information specific to this power resource.
-	 */
-	pr = (BM_POWER_RESOURCE*)context;
-
-	/*
-	 * Handle request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
-
-
diff -Nru a/drivers/acpi/ospm/busmgr/bmrequest.c b/drivers/acpi/ospm/busmgr/bmrequest.c
--- a/drivers/acpi/ospm/busmgr/bmrequest.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,164 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bmrequest.c
- *   $Revision: 16 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bmrequest")
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_generate_request
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_generate_request (
-	BM_NODE			*node,
-	BM_REQUEST		*request)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE		*device = NULL;
-
-	FUNCTION_TRACE("bm_generate_request");
-
-	if (!node || !request) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	device = &(node->device);
-
-	if (!BM_IS_DRIVER_CONTROL(device)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "No driver installed for device [%02x].\n", device->handle));
-		return_ACPI_STATUS(AE_NOT_EXIST);
-	}
-
-	status = node->driver.request(request, node->driver.context);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_request
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_request (
-	BM_REQUEST              *request)
-{
-	acpi_status             status = AE_OK;
-	BM_NODE			*node = NULL;
-	BM_DEVICE		*device = NULL;
-
-	FUNCTION_TRACE("bm_request");
-
-	/*
-	 * Must have a valid request structure.
-	 */
-	if (!request) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Received request for device [%02x] command [%02x].\n", request->handle, request->command));
-
-	/*
-	 * Resolve the node.
-	 */
-	status = bm_get_node(request->handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	device = &(node->device);
-
-	/*
-	 * Device-Specific Request?
-	 * ------------------------
-	 * If a device-specific command (>=0x80) forward this request to
-	 * the appropriate driver.
-	 */
-	if (request->command & BM_COMMAND_DEVICE_SPECIFIC) {
-		status = bm_generate_request(node, request);
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Bus-Specific Requests:
-	 * ----------------------
-	 */
-	switch (request->command) {
-
-	case BM_COMMAND_GET_POWER_STATE:
-		status = bm_get_power_state(node);
-		if (ACPI_FAILURE(status)) {
-			break;
-		}
-		status = bm_copy_to_buffer(&(request->buffer),
-			&(device->power.state), sizeof(BM_POWER_STATE));
-		break;
-
-	case BM_COMMAND_SET_POWER_STATE:
-	 {
-		BM_POWER_STATE *power_state = NULL;
-
-		status = bm_cast_buffer(&(request->buffer),
-			(void**)&power_state, sizeof(BM_POWER_STATE));
-		if (ACPI_FAILURE(status)) {
-			break;
-		}
-		status = bm_set_power_state(node, *power_state);
-	}
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		request->status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/busmgr/bmsearch.c b/drivers/acpi/ospm/busmgr/bmsearch.c
--- a/drivers/acpi/ospm/busmgr/bmsearch.c	Fri Mar 15 17:51:00 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,192 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bmsearch.c
- *   $Revision: 16 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bmsearch")
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_compare
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_compare (
-	BM_DEVICE               *device,
-	BM_DEVICE_ID            *criteria)
-{
-	if (!device || !criteria) {
-		return AE_BAD_PARAMETER;
-	}
-
-	/*
-	 * Present?
-	 * --------
-	 * We're only going to match on devices that are present.
-	 * TBD: Optimize in bm_search (don't have to call here).
-	 */
-	if (!BM_DEVICE_PRESENT(device)) {
-		return AE_NOT_FOUND;
-	}
-
-	/*
-	 * Type?
-	 */
-	if (criteria->type && (criteria->type != device->id.type)) {
-		return AE_NOT_FOUND;
-	}
-
-	/*
-	 * HID?
-	 */
-	if ((criteria->hid[0]) && (0 != STRNCMP(criteria->hid,
-		device->id.hid, sizeof(BM_DEVICE_HID)))) {
-		return AE_NOT_FOUND;
-	}
-
-	/*
-	 * ADR?
-	 */
-	if ((criteria->adr) && (criteria->adr != device->id.adr)) {
-		return AE_NOT_FOUND;
-	}
-
-	return AE_OK;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_search
- *
- * PARAMETERS:
- *
- * RETURN:      AE_BAD_PARAMETER- invalid input parameter
- *              AE_NOT_EXIST    - start_device_handle doesn't exist
- *              AE_NOT_FOUND    - no matches to Search_info.criteria found
- *              AE_OK           - success
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_search(
-	BM_HANDLE               device_handle,
-	BM_DEVICE_ID            *criteria,
-	BM_HANDLE_LIST          *results)
-{
-	acpi_status             status = AE_OK;
-	BM_NODE			*node = NULL;
-
-	FUNCTION_TRACE("bm_search");
-
-	if (!criteria || !results) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	results->count = 0;
-
-	/*
-	 * Locate Starting Point:
-	 * ----------------------
-	 * Locate the node in the hierarchy where we'll begin our search.
-	 */
-	status = bm_get_node(device_handle, 0, &node);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Parse Hierarchy:
-	 * ----------------
-	 * Parse through the node hierarchy looking for matches.
-	 */
-	while (node && (results->count<=BM_HANDLES_MAX)) {
-		/*
-		 * Depth-first:
-		 * ------------
-		 * Searches are always performed depth-first.
-		 */
-		if (node->scope.head) {
-			status = bm_compare(&(node->device), criteria);
-			if (ACPI_SUCCESS(status)) {
-				results->handles[results->count++] =
-					node->device.handle;
-			}
-			node = node->scope.head;
-		}
-
-		/*
-		 * Now Breadth:
-		 * ------------
-		 * Search all peers until scope is exhausted.
-		 */
-		else {
-			status = bm_compare(&(node->device), criteria);
-			if (ACPI_SUCCESS(status)) {
-				results->handles[results->count++] =
-					node->device.handle;
-			}
-
-			/*
-			 * Locate Next Device:
-			 * -------------------
-			 * The next node is either a peer at this level
-			 * (node->next is valid), or we work are way back
-			 * up the tree until we either find a non-parsed
-			 * peer or hit the top (node->parent is NULL).
-			 */
-			while (!node->next && node->parent) {
-				node = node->parent;
-			}
-			node = node->next;
-		}
-	}
-
-	if (results->count == 0) {
-		return_ACPI_STATUS(AE_NOT_FOUND);
-	}
-	else {
-		return_ACPI_STATUS(AE_OK);
-	}
-}
-
diff -Nru a/drivers/acpi/ospm/busmgr/bmutils.c b/drivers/acpi/ospm/busmgr/bmutils.c
--- a/drivers/acpi/ospm/busmgr/bmutils.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,611 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bmutils.c
- *   $Revision: 43 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bm.h"
-
-
-#define _COMPONENT		ACPI_BUS
-	MODULE_NAME		("bmutils")
-
-
-#ifdef ACPI_DEBUG
-#define DEBUG_EVAL_ERROR(l,h,p,s)    bm_print_eval_error(l,h,p,s)
-#else
-#define DEBUG_EVAL_ERROR(l,h,p,s)
-#endif
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    bm_print_eval_error
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-bm_print_eval_error (
-	u32                     debug_level,
-	acpi_handle             handle,
-	acpi_string             pathname,
-	acpi_status             status)
-{
-	acpi_buffer		buffer;
-	acpi_status		local_status;
-
-	PROC_NAME("bm_print_eval_error");
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	local_status = acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
-	if (ACPI_FAILURE(local_status)) {
-		ACPI_DEBUG_PRINT((ACPI_DEBUG_LEVEL(debug_level), "Evaluate object [%p], %s\n", handle,
-			acpi_format_exception(status)));
-		return;
-	}
-
-	if (pathname) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluate object [%s.%s], %s\n", (char*)buffer.pointer, pathname,
-			acpi_format_exception(status)));
-	}
-	else {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Evaluate object [%s], %s\n", (char*)buffer.pointer,
-			acpi_format_exception(status)));
-	}
-
-	acpi_os_free(buffer.pointer);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_copy_to_buffer
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_copy_to_buffer (
-	acpi_buffer             *buffer,
-	void                    *data,
-	u32                     length)
-{
-	FUNCTION_TRACE("bm_copy_to_buffer");
-
-	if (!buffer || (!buffer->pointer) || !data || (length == 0)) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (length > buffer->length) {
-		buffer->length = length;
-		return_ACPI_STATUS(AE_BUFFER_OVERFLOW);
-	}
-
-	buffer->length = length;
-	MEMCPY(buffer->pointer, data, length);
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_cast_buffer
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_cast_buffer (
-	acpi_buffer             *buffer,
-	void                    **pointer,
-	u32                     length)
-{
-	FUNCTION_TRACE("bm_cast_buffer");
-
-	if (!buffer || !buffer->pointer || !pointer || length == 0) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (length > buffer->length) {
-		return_ACPI_STATUS(AE_BAD_DATA);
-	}
-
-	*pointer = buffer->pointer;
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_extract_package_data
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_extract_package_data (
-	acpi_object             *package,
-	acpi_buffer             *format,
-	acpi_buffer             *buffer)
-{
-	u32                     tail_offset = 0;
-	u32                     size_required = 0;
-	char			*format_string = NULL;
-	u32                     format_count = 0;
-	u32                     i = 0;
-	u8                      *head = NULL;
-	u8                      *tail = NULL;
-
-	FUNCTION_TRACE("bm_extract_package_data");
-
-	if (!package || (package->type != ACPI_TYPE_PACKAGE) || (package->package.count < 1)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid 'package' argument\n"));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (!format || !format->pointer || (format->length < 1)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid 'format' argument\n"));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (!buffer) {
-		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid 'buffer' argument\n"));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	format_count = (format->length/sizeof(char)) - 1;
-	if (format_count > package->package.count) {
-		ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Format specifies more objects [%d] than exist in package [%d].", format_count, package->package.count));
-		return_ACPI_STATUS(AE_BAD_DATA);
-	}
-
-	format_string = (char*)format->pointer;
-
-	/*
-	 * Calculate size_required.
-	 */
-	for (i=0; i<format_count; i++) {
-
-		acpi_object *element = &(package->package.elements[i]);
-
-		if (!element) {
-			return_ACPI_STATUS(AE_BAD_DATA);
-		}
-
-		switch (element->type) {
-
-		case ACPI_TYPE_INTEGER:
-			switch (format_string[i]) {
-			case 'N':
-				size_required += sizeof(acpi_integer);
-				tail_offset += sizeof(acpi_integer);
-				break;
-			case 'S':
-				size_required += sizeof(char*) + sizeof(acpi_integer) + sizeof(char);
-				tail_offset += sizeof(char*);
-				break;
-			default:
-				ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid package element [%d]: got number, expecing [%c].\n", i, format_string[i]));
-				return_ACPI_STATUS(AE_BAD_DATA);
-				break;
-			}
-			break;
-
-		case ACPI_TYPE_STRING:
-		case ACPI_TYPE_BUFFER:
-			switch (format_string[i]) {
-			case 'S':
-				size_required += sizeof(char*) + (element->string.length * sizeof(char)) + sizeof(char);
-				tail_offset += sizeof(char*);
-				break;
-			case 'B':
-				size_required += sizeof(u8*) + (element->buffer.length * sizeof(u8));
-				tail_offset += sizeof(u8*);
-				break;
-			default:
-				ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid package element [%d] got string/buffer, expecing [%c].\n", i, format_string[i]));
-				return_ACPI_STATUS(AE_BAD_DATA);
-				break;
-			}
-			break;
-
-		case ACPI_TYPE_PACKAGE:
-		default:
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found unsupported element at index=%d\n", i));
-			/* TBD: handle nested packages... */
-			return_ACPI_STATUS(AE_SUPPORT);
-			break;
-		}
-	}
-
-	/* 
-	 * Validate output buffer. 
-	 */
-	if (buffer->length < size_required) {
-		buffer->length = size_required;
-		return_ACPI_STATUS(AE_BUFFER_OVERFLOW);
-	}
-	else if (buffer->length != size_required || !buffer->pointer) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	head = buffer->pointer;
-	tail = buffer->pointer + tail_offset;
-
-	/* 
-	 * Extract package data.
-	 */
-	for (i=0; i<format_count; i++) {
-
-		u8 **pointer = NULL;
-		acpi_object *element = &(package->package.elements[i]);
-
-		switch (element->type) {
-
-		case ACPI_TYPE_INTEGER:
-			switch (format_string[i]) {
-			case 'N':
-				*((acpi_integer*)head) = element->integer.value;
-				head += sizeof(acpi_integer);
-				break;
-			case 'S':
-				pointer = (u8**)head;
-				*pointer = tail;
-				*((acpi_integer*)tail) = element->integer.value;
-				head += sizeof(acpi_integer*);
-				tail += sizeof(acpi_integer);
-				/* NULL terminate string */
-				*tail = (char)0;
-				tail += sizeof(char);
-				break;
-			default:
-				/* Should never get here */
-				break;
-			}
-			break;
-
-		case ACPI_TYPE_STRING:
-		case ACPI_TYPE_BUFFER:
-			switch (format_string[i]) {
-			case 'S':
-				pointer = (u8**)head;
-				*pointer = tail;
-				memcpy(tail, element->string.pointer, element->string.length);
-				head += sizeof(char*);
-				tail += element->string.length * sizeof(char);
-				/* NULL terminate string */
-				*tail = (char)0;
-				tail += sizeof(char);
-				break;
-			case 'B':
-				pointer = (u8**)head;
-				*pointer = tail;
-				memcpy(tail, element->buffer.pointer, element->buffer.length);
-				head += sizeof(u8*);
-				tail += element->buffer.length * sizeof(u8);
-				break;
-			default:
-				/* Should never get here */
-				break;
-			}
-			break;
-
-		case ACPI_TYPE_PACKAGE:
-			/* TBD: handle nested packages... */
-		default:
-			/* Should never get here */
-			break;
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_evaluate_object
- *
- * PARAMETERS:
- *
- * RETURN:      AE_OK
- *              AE_BUFFER_OVERFLOW  Evaluated object returned data, but
- *                                  caller did not provide buffer.
- *
- * DESCRIPTION: Helper for acpi_evaluate_object that handles buffer
- *              allocation.  Note that the caller is responsible for
- *              freeing buffer->pointer!
- *
- ****************************************************************************/
-
-acpi_status
-bm_evaluate_object (
-	acpi_handle             handle,
-	acpi_string             pathname,
-	acpi_object_list        *arguments,
-	acpi_buffer             *buffer)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("bm_evaluate_object");
-
-	/* If caller provided a buffer it must be unallocated/zero'd. */
-	if ((buffer) && (buffer->length != 0 || buffer->pointer)) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Evalute Object:
-	 * ---------------
-	 * The first attempt is just to get the size of the object data
-	 * (that is unless there's no return data, e.g. _INI); the second
-	 * gets the data.
-	 */
-	status = acpi_evaluate_object(handle, pathname, arguments, buffer);
-	if (ACPI_SUCCESS(status)) {
-		return_ACPI_STATUS(status);
-	}
-	else if ((buffer) && (status == AE_BUFFER_OVERFLOW)) {
-
-		/* Gotta allocate -- CALLER MUST FREE! */
-		buffer->pointer = acpi_os_callocate(buffer->length);
-		if (!buffer->pointer) {
-			return_ACPI_STATUS(AE_NO_MEMORY);
-		}
-
-		/* Re-evaluate -- this time it should work */
-		status = acpi_evaluate_object(handle, pathname,
-			arguments, buffer);
-	}
-
-	if (ACPI_FAILURE(status)) {
-		if (status != AE_NOT_FOUND) {
-			DEBUG_EVAL_ERROR(ACPI_LV_WARN, handle, pathname,
-				status);
-		}
-		if (buffer && buffer->pointer) {
-			acpi_os_free(buffer->pointer);
-			buffer->pointer = NULL;
-			buffer->length = 0;
-		}
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_evaluate_simple_integer
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bm_evaluate_simple_integer (
-	acpi_handle             handle,
-	acpi_string             pathname,
-	u32                     *data)
-{
-	acpi_status             status = AE_OK;
-	acpi_object             *element = NULL;
-	acpi_buffer             buffer;
-
-	FUNCTION_TRACE("bm_evaluate_simple_integer");
-
-	if (!data) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&buffer, 0, sizeof(acpi_buffer));
-
-	/*
-	 * Evaluate Object:
-	 * ----------------
-	 */
-	status = bm_evaluate_object(handle, pathname, NULL, &buffer);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "failed to evaluate object (%s)\n",
-			acpi_format_exception(status)));
-		goto end;
-	}
-
-	/*
-	 * Validate Data:
-	 * --------------
-	 */
-	status = bm_cast_buffer(&buffer, (void**)&element,
-		sizeof(acpi_object));
-	if (ACPI_FAILURE(status)) {
-		DEBUG_EVAL_ERROR(ACPI_LV_WARN, handle, pathname, status);
-		goto end;
-	}
-
-	if (element->type != ACPI_TYPE_INTEGER) {
-		status = AE_BAD_DATA;
-		DEBUG_EVAL_ERROR(ACPI_LV_WARN, handle, pathname, status);
-		goto end;
-	}
-
-	*data = element->integer.value;
-
-end:
-	acpi_os_free(buffer.pointer);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bm_evaluate_reference_list
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status  
-bm_evaluate_reference_list (
-	acpi_handle             handle,
-	acpi_string             pathname,
-	BM_HANDLE_LIST          *reference_list)
-{
-	acpi_status             status = AE_OK;
-	acpi_object             *package = NULL;
-	acpi_object             *element = NULL;
-	acpi_handle  		reference_handle = NULL;
-	acpi_buffer             buffer;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("bm_evaluate_reference_list");
-
-	if (!reference_list) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&buffer, 0, sizeof(acpi_buffer));
-
-	/*
-	 * Evaluate Object:
-	 * ----------------
-	 */
-	status = bm_evaluate_object(handle, pathname, NULL, &buffer);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	/*
-	 * Validate Package:
-	 * -----------------
-	 */
-	status = bm_cast_buffer(&buffer, (void**)&package,
-		sizeof(acpi_object));
-	if (ACPI_FAILURE(status)) {
-		DEBUG_EVAL_ERROR(ACPI_LV_WARN, handle, pathname, status);
-		goto end;
-	}
-
-	if (package->type != ACPI_TYPE_PACKAGE) {
-		status = AE_BAD_DATA;
-		DEBUG_EVAL_ERROR(ACPI_LV_WARN, handle, pathname, status);
-		goto end;
-	}
-
-	if (package->package.count > BM_HANDLES_MAX) {
-		package->package.count = BM_HANDLES_MAX;
-	}
-
-	/*
-	 * Parse Package Data:
-	 * -------------------
-	 */
-	for (i = 0; i < package->package.count; i++) {
-
-		element = &(package->package.elements[i]);
-
-		if (!element || (element->type != ACPI_TYPE_STRING)) {
-			status = AE_BAD_DATA;
-			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Invalid element in package (not a device reference).\n"));
-			DEBUG_EVAL_ERROR (ACPI_LV_WARN, handle, pathname, status);
-			break;
-		}
-
-		/*
-		 * Resolve reference string (e.g. "\_PR_.CPU_") to an
-		 * acpi_handle.
-		 */
-		status = acpi_get_handle(handle,
-			element->string.pointer, &reference_handle);
-		if (ACPI_FAILURE(status)) {
-			status = AE_BAD_DATA;
-			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Unable to resolve device reference [%s].\n", element->string.pointer));
-			DEBUG_EVAL_ERROR (ACPI_LV_WARN, handle, pathname, status);
-			break;
-		}
-
-		/*
-		 * Resolve acpi_handle to BM_HANDLE.
-		 */
-		status = bm_get_handle(reference_handle,
-			&(reference_list->handles[i]));
-		if (ACPI_FAILURE(status)) {
-			status = AE_BAD_DATA;
-			ACPI_DEBUG_PRINT((ACPI_DB_WARN, "Unable to resolve device reference for [%p].\n", reference_handle));
-			DEBUG_EVAL_ERROR (ACPI_LV_WARN, handle, pathname, status);
-			break;
-		}
-
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Resolved reference [%s]->[%p]->[%02x]\n", element->string.pointer, reference_handle, reference_list->handles[i]));
-
-		(reference_list->count)++;
-	}
-
-end:
-	acpi_os_free(buffer.pointer);
-
-	return_ACPI_STATUS(status);
-}
-
-
diff -Nru a/drivers/acpi/ospm/button/Makefile b/drivers/acpi/ospm/button/Makefile
--- a/drivers/acpi/ospm/button/Makefile	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/button/bn.c b/drivers/acpi/ospm/button/bn.c
--- a/drivers/acpi/ospm/button/bn.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,507 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: bn.c
- *   $Revision: 27 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Plxxe, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "bn.h"
-
-
-#define _COMPONENT		ACPI_BUTTON
-	MODULE_NAME		("bn")
-
-
-/*****************************************************************************
- *                            Internal Functions
- *****************************************************************************/
-
-/*****************************************************************************
- *
- * FUNCTION:	bn_print
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION: Prints out information on a specific button.
- *
- ****************************************************************************/
-
-void
-bn_print (
-	BN_CONTEXT		*button)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer		buffer;
-
-	PROC_NAME("bn_print");
-
-	if (!button) {
-		return;
-	}
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(button->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic button information.
-	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	switch (button->type) {
-
-	case BN_TYPE_POWER_BUTTON:
-	case BN_TYPE_POWER_BUTTON_FIXED:
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Power_button[%02x]:[%p] %s\n", button->device_handle, button->acpi_handle, (char*)buffer.pointer));
-		break;
-
-	case BN_TYPE_SLEEP_BUTTON:
-	case BN_TYPE_SLEEP_BUTTON_FIXED:
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Sleep_button[%02x]:[%p] %s\n", button->device_handle, button->acpi_handle, (char*)buffer.pointer));
-		break;
-
-	case BN_TYPE_LID_SWITCH:
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Lid_switch[%02x]:[%p] %s\n", button->device_handle, button->acpi_handle, (char*)buffer.pointer));
-		break;
-	}
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_add_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bn_add_device(
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	BN_CONTEXT		*button = NULL;
-
-	FUNCTION_TRACE("bn_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding button device [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid context.\n"));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info( device_handle, &device );
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Allocate a new BN_CONTEXT structure.
-	 */
-	button = acpi_os_callocate(sizeof(BN_CONTEXT));
-	if (!button) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	button->device_handle = device->handle;
-	button->acpi_handle = device->acpi_handle;
-
-	/*
-	 * Power Button?
-	 * -------------
-	 * Either fixed-feature or generic (namespace) types.
-	 */
-	if (strncmp(device->id.hid, BN_HID_POWER_BUTTON,
-		sizeof(BM_DEVICE_HID)) == 0) {
-
-		if (device->id.type == BM_TYPE_FIXED_BUTTON) {
-
-			button->type = BN_TYPE_POWER_BUTTON_FIXED;
-
-			/* Register for fixed-feature events. */
-			status = acpi_install_fixed_event_handler(
-				ACPI_EVENT_POWER_BUTTON, bn_notify_fixed,
-				(void*)button);
-		}
-		else {
-			button->type = BN_TYPE_POWER_BUTTON;
-		}
-
-	}
-
-	/*
-	 * Sleep Button?
-	 * -------------
-	 * Either fixed-feature or generic (namespace) types.
-	 */
-	else if (strncmp( device->id.hid, BN_HID_SLEEP_BUTTON,
-		sizeof(BM_DEVICE_HID)) == 0) {
-
-		if (device->id.type == BM_TYPE_FIXED_BUTTON) {
-
-			button->type = BN_TYPE_SLEEP_BUTTON_FIXED;
-
-			/* Register for fixed-feature events. */
-			status = acpi_install_fixed_event_handler(
-				ACPI_EVENT_SLEEP_BUTTON, bn_notify_fixed,
-				(void*)button);
-		}
-		else {
-			button->type = BN_TYPE_SLEEP_BUTTON;
-		}
-	}
-
-	/*
-	 * LID Switch?
-	 * -----------
-	 */
-	else if (strncmp( device->id.hid, BN_HID_LID_SWITCH,
-		sizeof(BM_DEVICE_HID)) == 0) {
-		button->type = BN_TYPE_LID_SWITCH;
-	}
-
-	status = bn_osl_add_device(button);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	*context = button;
-
-	bn_print(button);
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(button);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_remove_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bn_remove_device(
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-	BN_CONTEXT		*button = NULL;
-
-	FUNCTION_TRACE("bn_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	button = (BN_CONTEXT*)*context;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing button device [%02x].\n", button->device_handle));
-
-	/*
-	 * Unregister for fixed-feature events.
-	 */
-	switch (button->type) {
-	case BN_TYPE_POWER_BUTTON_FIXED:
-		status = acpi_remove_fixed_event_handler(
-			ACPI_EVENT_POWER_BUTTON, bn_notify_fixed);
-		break;
-	case BN_TYPE_SLEEP_BUTTON_FIXED:
-		status = acpi_remove_fixed_event_handler(
-			ACPI_EVENT_SLEEP_BUTTON, bn_notify_fixed);
-		break;
-	}
-
-	bn_osl_remove_device(button);
-
-	acpi_os_free(button);
-
-	*context = NULL;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/*****************************************************************************
- *			      External Functions
- *****************************************************************************/
-
-/*****************************************************************************
- *
- * FUNCTION:	bn_initialize
- *
- * PARAMETERS:	<none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
-
- ****************************************************************************/
-
-acpi_status
-bn_initialize (void)
-{
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("bn_initialize");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	driver.notify = &bn_notify;
-	driver.request = &bn_request;
-
-	/*
-	 * Register for power buttons.
-	 */
-	MEMCPY(criteria.hid, BN_HID_POWER_BUTTON, sizeof(BN_HID_POWER_BUTTON));
-	bm_register_driver(&criteria, &driver);
-
-	/*
-	 * Register for sleep buttons.
-	 */
-	MEMCPY(criteria.hid, BN_HID_SLEEP_BUTTON, sizeof(BN_HID_SLEEP_BUTTON));
-	bm_register_driver(&criteria, &driver);
-
-	/*
-	 * Register for LID switches.
-	 */
-	MEMCPY(criteria.hid, BN_HID_LID_SWITCH, sizeof(BN_HID_LID_SWITCH));
-	bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_terminate
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bn_terminate (void)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("bn_terminate");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	driver.notify = &bn_notify;
-	driver.request = &bn_request;
-
-	/*
-	 * Unregister for power buttons.
-	 */
-	MEMCPY(criteria.hid, BN_HID_POWER_BUTTON, sizeof(BN_HID_POWER_BUTTON));
-	status = bm_unregister_driver(&criteria, &driver);
-
-	/*
-	 * Unregister for sleep buttons.
-	 */
-	MEMCPY(criteria.hid, BN_HID_SLEEP_BUTTON, sizeof(BN_HID_SLEEP_BUTTON));
-	status = bm_unregister_driver(&criteria, &driver);
-
-	/*
-	 * Unregister for LID switches.
-	 */
-	MEMCPY(criteria.hid, BN_HID_LID_SWITCH, sizeof(BN_HID_LID_SWITCH));
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_notify_fixed
- *
- * PARAMETERS:	<none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bn_notify_fixed (
-	void			*context)
-{
-	acpi_status		status = AE_OK;
-
-	FUNCTION_TRACE("bn_notify_fixed");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Status change event detected.\n"));
-
-	status = bn_osl_generate_event(BN_NOTIFY_STATUS_CHANGE,
-		((BN_CONTEXT*)context));
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_notify
- *
- * PARAMETERS:	<none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bn_notify (
-	BM_NOTIFY		notify_type,
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-
-	FUNCTION_TRACE("bn_notify");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	switch (notify_type) {
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = bn_add_device(device_handle, context);
-		break;
-		
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = bn_remove_device(context);
-		break;
-		
-	case BN_NOTIFY_STATUS_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Status change event detected.\n"));
-		status = bn_osl_generate_event(BN_NOTIFY_STATUS_CHANGE,
-			((BN_CONTEXT*)*context));
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_request
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-bn_request (
-	BM_REQUEST		*request,
-	void			*context)
-{
-	acpi_status		status = AE_OK;
-
-	FUNCTION_TRACE("bn_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Handle Request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/button/bn_osl.c b/drivers/acpi/ospm/button/bn_osl.c
--- a/drivers/acpi/ospm/button/bn_osl.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,311 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bn_osl.c
- *   $Revision: 16 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <acpi.h>
-#include "bn.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - Button Driver");
-MODULE_LICENSE("GPL");
-
-
-#define BN_PROC_ROOT		"button"
-#define BN_PROC_POWER_BUTTON	"power"
-#define BN_PROC_SLEEP_BUTTON	"sleep"
-#define BN_PROC_LID_SWITCH	"lid"
-
-extern struct proc_dir_entry	*bm_proc_root;
-static struct proc_dir_entry	*bn_proc_root = NULL;
-
-
-#define BN_TYPE_UNKNOWN		0
-#define BN_TYPE_FIXED		1
-#define BN_TYPE_GENERIC		2
-
-static int bn_power_button = BN_TYPE_UNKNOWN;
-static int bn_sleep_button = BN_TYPE_UNKNOWN;
-static int bn_lid_switch = BN_TYPE_UNKNOWN;
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_osl_add_device
- *
- ****************************************************************************/
-
-acpi_status
-bn_osl_add_device(
-	BN_CONTEXT		*button)
-{
-	acpi_status		status = AE_OK;
-
-	if (!button) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (button->type) {
-
-	case BN_TYPE_POWER_BUTTON_FIXED:
-		bn_power_button = BN_TYPE_FIXED;
-		printk(KERN_INFO "ACPI: Power Button (FF) found\n");
-		if (!proc_mkdir(BN_PROC_POWER_BUTTON, bn_proc_root)) {
-			status = AE_ERROR;
-		}
-		break;
-
-	case BN_TYPE_POWER_BUTTON:
-		/* 
-		 * Avoid creating multiple /proc entries when (buggy) ACPI
-		 * BIOS tables erroneously list both fixed- and generic-
-		 * feature buttons.  Note that fixed-feature buttons are 
-		 * always enumerated first (and there can only be one) so
-		 * we only need to check here.
-		 */
-		switch (bn_power_button) {
-		case BN_TYPE_GENERIC:
-			printk(KERN_WARNING "ACPI: Multiple generic-space power buttons detected, using first\n");
-			break;
-		case BN_TYPE_FIXED:
-			printk(KERN_WARNING "ACPI: Multiple power buttons detected, ignoring fixed-feature\n");
-		default:
-			printk(KERN_INFO "ACPI: Power Button (CM) found\n");
-			bn_power_button = BN_TYPE_GENERIC;
-			if (!proc_mkdir(BN_PROC_POWER_BUTTON, bn_proc_root)) {
-				status = AE_ERROR;
-			}
-			break;
-		}
-		break;
-
-	case BN_TYPE_SLEEP_BUTTON_FIXED:
-		bn_sleep_button = BN_TYPE_FIXED;
-		printk(KERN_INFO "ACPI: Sleep Button (FF) found\n");
-		if (!proc_mkdir(BN_PROC_SLEEP_BUTTON, bn_proc_root)) {
-			status = AE_ERROR;
-		}
-		break;
-
-	case BN_TYPE_SLEEP_BUTTON:
-		/* 
-		 * Avoid creating multiple /proc entries when (buggy) ACPI
-		 * BIOS tables erroneously list both fixed- and generic-
-		 * feature buttons.  Note that fixed-feature buttons are 
-		 * always enumerated first (and there can only be one) so
-		 * we only need to check here.
-		 */
-		switch (bn_sleep_button) {
-		case BN_TYPE_GENERIC:
-			printk(KERN_WARNING "ACPI: Multiple generic-space sleep buttons detected, using first\n");
-			break;
-		case BN_TYPE_FIXED:
-			printk(KERN_WARNING "ACPI: Multiple sleep buttons detected, ignoring fixed-feature\n");
-		default:
-			bn_sleep_button = BN_TYPE_GENERIC;
-			printk(KERN_INFO "ACPI: Sleep Button (CM) found\n");
-			if (!proc_mkdir(BN_PROC_SLEEP_BUTTON, bn_proc_root)) {
-				status = AE_ERROR;
-			}
-			break;
-		}
-		break;
-
-	case BN_TYPE_LID_SWITCH:
-		if (bn_lid_switch) {
-			printk(KERN_WARNING "ACPI: Multiple generic-space lid switches detected, using first\n");
-			break;
-		}
-		bn_lid_switch = BN_TYPE_GENERIC;
-		printk(KERN_INFO "ACPI: Lid Switch (CM) found\n");
-		if (!proc_mkdir(BN_PROC_LID_SWITCH, bn_proc_root)) {
-			status = AE_ERROR;
-		}
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_osl_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-bn_osl_remove_device (
-	BN_CONTEXT		*button)
-{
-	if (!button) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (button->type) {
-
-	case BN_TYPE_POWER_BUTTON:
-	case BN_TYPE_POWER_BUTTON_FIXED:
-		remove_proc_entry(BN_PROC_POWER_BUTTON, bn_proc_root);
-		break;
-
-	case BN_TYPE_SLEEP_BUTTON:
-	case BN_TYPE_SLEEP_BUTTON_FIXED:
-		remove_proc_entry(BN_PROC_SLEEP_BUTTON, bn_proc_root);
-		break;
-
-	case BN_TYPE_LID_SWITCH:
-		remove_proc_entry(BN_PROC_LID_SWITCH, bn_proc_root);
-		break;
-	}
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	bn_osl_generate_event
- *
- ****************************************************************************/
-
-acpi_status
-bn_osl_generate_event (
-	u32			event,
-	BN_CONTEXT		*button)
-{
-	acpi_status		status = AE_OK;
-
-	if (!button) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (event) {
-
-	case BN_NOTIFY_STATUS_CHANGE:
-
-		switch(button->type) {
-
-		case BN_TYPE_POWER_BUTTON:
-		case BN_TYPE_POWER_BUTTON_FIXED:
-			status = bm_osl_generate_event(button->device_handle,
-				BN_PROC_ROOT, BN_PROC_POWER_BUTTON, event, 0);
-			break;
-
-		case BN_TYPE_SLEEP_BUTTON:
-		case BN_TYPE_SLEEP_BUTTON_FIXED:
-			status = bm_osl_generate_event(button->device_handle,
-				BN_PROC_ROOT, BN_PROC_SLEEP_BUTTON, event, 0);
-			break;
-
-		case BN_TYPE_LID_SWITCH:
-			status = bm_osl_generate_event(button->device_handle,
-				BN_PROC_ROOT, BN_PROC_LID_SWITCH, event, 0);
-			break;
-
-		default:
-			status = AE_SUPPORT;
-			break;
-		}
-
-		break;
-
-	default:
-		return(AE_BAD_PARAMETER);
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bn_osl_init
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	0: Success
- *
- * DESCRIPTION: Module initialization.
- *
- ****************************************************************************/
-
-static int __init
-bn_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	/* abort if no busmgr */
-	if (!bm_proc_root)
-		return -ENODEV;
-
-	bn_proc_root = proc_mkdir(BN_PROC_ROOT, bm_proc_root);
-	if (!bn_proc_root) {
-		status = AE_ERROR;
-	}
-	else {
-		status = bn_initialize();
-		if (ACPI_FAILURE(status)) {
-			remove_proc_entry(BN_PROC_ROOT, bm_proc_root);
-		}
-	}
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    bn_osl_cleanup
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	<none>
- *
- * DESCRIPTION: Module cleanup.
- *
- ****************************************************************************/
-
-static void __exit
-bn_osl_cleanup (void)
-{
-	bn_terminate();
-
-	if (bn_proc_root) {
-		remove_proc_entry(BN_PROC_ROOT, bm_proc_root);
-	}
-
-	return;
-}
-
-
-module_init(bn_osl_init);
-module_exit(bn_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/ec/Makefile b/drivers/acpi/ospm/ec/Makefile
--- a/drivers/acpi/ospm/ec/Makefile	Fri Mar 15 17:51:00 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/ec/ec_osl.c b/drivers/acpi/ospm/ec/ec_osl.c
--- a/drivers/acpi/ospm/ec/ec_osl.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,91 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ec_osl.c
- *   $Revision: 11 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <acpi.h>
-#include <bm.h>
-#include "ec.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - Embedded Controller Driver");
-MODULE_LICENSE("GPL");
-
-extern struct proc_dir_entry	*bm_proc_root;
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_osl_init
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	0: Success
- *
- * DESCRIPTION: Module initialization.
- *
- ****************************************************************************/
-
-static int __init
-ec_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	/* abort if no busmgr */
-	if (!bm_proc_root)
-		return -ENODEV;
-
-	status = ec_initialize();
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-/****************************************************************************
- *
- * FUNCTION:    ec_osl_cleanup
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	<none>
- *
- * DESCRIPTION: Module cleanup.
- *
- ****************************************************************************/
-
-static void __exit
-ec_osl_cleanup(void)
-{
-	ec_terminate();
-
-	return;
-}
-
-module_init(ec_osl_init);
-module_exit(ec_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/ec/ecgpe.c b/drivers/acpi/ospm/ec/ecgpe.c
--- a/drivers/acpi/ospm/ec/ecgpe.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,249 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ecgpe.c
- *   $Revision: 28 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "ec.h"
-
-#define _COMPONENT		ACPI_EC
-	MODULE_NAME		("ecgpe")
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_query_handler
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-ec_query_handler (
-	void                    *context)
-{
-	EC_CONTEXT		*ec = (EC_CONTEXT*)context;
-	static char		object_name[5] = {'_','Q','0','0','\0'};
-	const char		hex[] = {'0','1','2','3','4','5','6','7','8',
-					'9','A','B','C','D','E','F'};
-
-	FUNCTION_TRACE("ec_query_handler");
-
-	if (!ec) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
-		return_VOID;
-	}
-
-	/*
-	 * Evaluate _Qxx:
-	 * --------------
-	 * Evaluate corresponding _Qxx method.  Note that a zero query value
-	 * indicates a spurious EC_SCI (no such thing as _Q00).
-	 */
-	object_name[2] = hex[((ec->query_data >> 4) & 0x0F)];
-	object_name[3] = hex[(ec->query_data & 0x0F)];
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Evaluating [%s] for ec [%02x].\n", object_name, ec->device_handle));
-
-	bm_evaluate_object(ec->acpi_handle, object_name, NULL, NULL);
-
-	return_VOID;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_gpe_handler
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-ec_gpe_handler (
-	void                    *context)
-{
-	acpi_status             status = AE_OK;
-	EC_CONTEXT              *ec = (EC_CONTEXT*)context;
-	EC_STATUS               ec_status = 0;
-
-	FUNCTION_TRACE("ec_gpe_handler");
-
-	if (!ec) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
-		return_VOID;
-	}
-
-	/* TBD: synchronize w/ transaction (ectransx). */
-
-	/*
-	 * EC_SCI?
-	 * -------
-	 * Check the EC_SCI bit to see if this is an EC_SCI event.  If not (e.g.
-	 * OBF/IBE) just return, as we already poll to detect these events.
-	 */
-	acpi_os_read_port(ec->status_port, &ec_status, 8);
-	if (!(ec_status & EC_FLAG_SCI)) {
-		return_VOID;
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "EC_SCI event detected on ec [%02x] - running query.\n", ec->device_handle));
-
-	/*
-	 * Run Query:
-	 * ----------
-	 * Query the EC to find out which _Qxx method we need to evaluate.
-	 * Note that successful completion of the query causes the EC_SCI
-	 * bit to be cleared (and thus clearing the interrupt source).
-	 */
-	status = ec_io_write(ec, ec->command_port, EC_COMMAND_QUERY,
-		EC_EVENT_OUTPUT_BUFFER_FULL);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to send 'query command' to EC.\n"));
-		return_VOID;
-	}
-
-	status = ec_io_read(ec, ec->data_port, &(ec->query_data),
-		EC_EVENT_NONE);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Error reading query data.\n"));
-		return_VOID;
-	}
-
-	/* TBD: un-synchronize w/ transaction (ectransx). */
-
-	/*
-	 * Spurious EC_SCI?
-	 * ----------------
-	 */
-	if (!ec->query_data) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Spurious EC SCI detected.\n"));
-		return_VOID;
-	}
-
-	/*
-	 * Defer _Qxx Execution:
-	 * ---------------------
-	 * Can't evaluate this method now 'cause we're at interrupt-level.
-	 */
-	status = acpi_os_queue_for_execution(OSD_PRIORITY_GPE,
-		ec_query_handler, ec);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to defer _Qxx method evaluation.\n"));
-		return_VOID;
-	}
-
-	return_VOID;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_install_gpe_handler
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_install_gpe_handler (
-	EC_CONTEXT              *ec)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_install_gpe_handler");
-
-	if (!ec) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Evaluate _GPE:
-	 * --------------
-	 * Evaluate the "_GPE" object (required) to find out which GPE bit
-	 * is used by this EC to signal events (SCIs).
-	 */
-	status = bm_evaluate_simple_integer(ec->acpi_handle,
-		"_GPE", &(ec->gpe_bit));
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Install GPE Handler:
-	 * --------------------
-	 * Install a handler for this EC's GPE bit.
-	 */
-	status = acpi_install_gpe_handler(ec->gpe_bit, ACPI_EVENT_EDGE_TRIGGERED,
-		&ec_gpe_handler, ec);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "acpi_install_gpe_handler() failed for GPE bit [%02x] with status [%08x].\n", ec->gpe_bit, status));
-		ec->gpe_bit = EC_GPE_UNKNOWN;
-		return_ACPI_STATUS(status);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_remove_gpe_handler
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_remove_gpe_handler (
-	EC_CONTEXT              *ec)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_remove_gpe_handler");
-
-	if (!ec) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	status = acpi_remove_gpe_handler(ec->gpe_bit, &ec_gpe_handler);
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/ec/ecmain.c b/drivers/acpi/ospm/ec/ecmain.c
--- a/drivers/acpi/ospm/ec/ecmain.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,498 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ecmain.c
- *   $Revision: 29 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "ec.h"
-
-#define _COMPONENT		ACPI_EC
-	MODULE_NAME		("ecmain")
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    ec_print
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION: Prints out information on a specific ec.
- *
- ****************************************************************************/
-
-void
-ec_print (
-	EC_CONTEXT              *ec)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer             buffer;
-#endif /*ACPI_DEBUG*/
-
-	PROC_NAME("ec_print");
-
-	if (!ec) {
-		return;
-	}
-
-	acpi_os_printf("EC: found, GPE %d\n", ec->gpe_bit);
-
-#ifdef ACPI_DEBUG
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(ec->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic thermal zone information.
-	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Embedded_controller[%02x]:[%p] %s\n", ec->device_handle, ec->acpi_handle, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   gpe_bit[%02x] status/command_port[%02x] data_port[%02x]\n", ec->gpe_bit, ec->status_port, ec->data_port));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_get_port_values
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION: Evaluate _CRS to get the current resources (I/O port
- *              addresses) for this EC.
- *
- ****************************************************************************/
-
-acpi_status
-ec_get_port_values(
-	EC_CONTEXT              *ec)
-{
-	acpi_status             status = AE_OK;
-	acpi_buffer             buffer;
-	acpi_resource           *resource = NULL;
-
-	FUNCTION_TRACE("ec_get_port_values");
-
-	if (!ec) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	buffer.length = 0;
-	buffer.pointer = NULL;
-
-	status = acpi_get_current_resources(ec->acpi_handle, &buffer);
-	if (status != AE_BUFFER_OVERFLOW) {
-		return_ACPI_STATUS(status);
-	}
-
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	status = acpi_get_current_resources(ec->acpi_handle, &buffer);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	resource = (acpi_resource *) buffer.pointer;
-	ec->data_port = resource->data.io.min_base_address;
-
-	resource = NEXT_RESOURCE(resource);
-
-	ec->status_port = ec->command_port =
-		resource->data.io.min_base_address;
-end:
-	acpi_os_free(buffer.pointer);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_add_device
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_add_device(
-	BM_HANDLE               device_handle,
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	EC_CONTEXT              *ec = NULL;
-	u8                      gpe_handler = FALSE;
-	u8                      space_handler = FALSE;
-
-	FUNCTION_TRACE("ec_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding EC device [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Allocate a new EC_CONTEXT structure.
-	 */
-	ec = acpi_os_callocate(sizeof(EC_CONTEXT));
-	if (!ec) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	ec->device_handle = device->handle;
-	ec->acpi_handle = device->acpi_handle;
-
-	/*
-	 * Get the I/O port addresses for the command/status and data ports.
-	 */
-	status = ec_get_port_values(ec);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	/*
-	 * See if we need to obtain the global lock for EC transactions.
-	 */
-	status = bm_evaluate_simple_integer(ec->acpi_handle, "_GLK",
-		&ec->use_global_lock);
-	if (status == AE_NOT_FOUND) {
-		ec->use_global_lock = 0;
-	}
-	else if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "EC _GLK failed\n"));
-		goto end;
-	}
-
-	/*
-	 * Install a handler for servicing this EC's GPE.
-	 */
-	status = ec_install_gpe_handler(ec);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-	else {
-		gpe_handler = TRUE;
-	}
-
-	/*
-	 * Install a handler for servicing this EC's address space.
-	 */
-	status = ec_install_space_handler(ec);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-	else {
-		space_handler = TRUE;
-	}
-
-	/*
-	 * Create a semaphore to serialize EC transactions.
-	 */
-	status = acpi_os_create_semaphore(1,1, &(ec->mutex));
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	/*
-	 * Context now contains information specific to this EC.  Note
-	 * that we'll get this pointer back on every ec_request() and
-	 * ec_notify().
-	 */
-	*context = ec;
-
-	ec_print(ec);
-
-end:
-	if (ACPI_FAILURE(status)) {
-
-		if (gpe_handler) {
-			ec_remove_gpe_handler(ec);
-		}
-
-		if (space_handler) {
-			ec_remove_space_handler(ec);
-		}
-
-		if (ec->mutex) {
-			acpi_os_delete_semaphore(ec->mutex);
-		}
-
-		acpi_os_free(ec);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_remove_device
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_remove_device(
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-	EC_CONTEXT              *ec = NULL;
-
-	FUNCTION_TRACE("ec_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ec = (EC_CONTEXT*)*context;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing EC device [%02x].\n", ec->device_handle));
-
-	ec_remove_space_handler(ec);
-
-	ec_remove_gpe_handler(ec);
-
-	if (ec->mutex) {
-		acpi_os_delete_semaphore(ec->mutex);
-	}
-
-	acpi_os_free(ec);
-
-	*context = NULL;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    ec_initialize
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_initialize (void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("ec_initialize");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Register driver for AC Adapter devices.
-	 */
-	MEMCPY(criteria.hid, EC_HID_EC, sizeof(EC_HID_EC));
-
-	driver.notify = &ec_notify;
-	driver.request = &ec_request;
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_terminate
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_terminate(void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("ec_terminate");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Unregister driver for AC Adapter devices.
-	 */
-	MEMCPY(criteria.hid, EC_HID_EC, sizeof(EC_HID_EC));
-
-	driver.notify = &ec_notify;
-	driver.request = &ec_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_notify
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_notify (
-	BM_NOTIFY               notify,
-	BM_HANDLE               device_handle,
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_notify");
-
-	switch (notify) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = ec_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = ec_remove_device(context);
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_request
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_request (
-	BM_REQUEST              *request,
-	void                    *context)
-{
-	acpi_status             status = AE_OK;
-	EC_REQUEST              *ec_request = NULL;
-	EC_CONTEXT              *ec = NULL;
-
-	FUNCTION_TRACE("ec_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context)
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-
-	/*
-	 * buffer must contain a valid EC_REQUEST structure.
-	 */
-	status = bm_cast_buffer(&(request->buffer), (void**)&ec_request,
-		sizeof(EC_REQUEST));
-	if (ACPI_FAILURE(status))
-		return_ACPI_STATUS(status);
-
-	/*
-	 * context contains information specific to this EC.
-	 */
-	ec = (EC_CONTEXT*)context;
-
-	/*
-	 * Perform the Transaction.
-	 */
-	status = ec_transaction(ec, ec_request);
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/ec/ecspace.c b/drivers/acpi/ospm/ec/ecspace.c
--- a/drivers/acpi/ospm/ec/ecspace.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,192 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ecspace.c
- *   $Revision: 23 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "ec.h"
-
-#define _COMPONENT		ACPI_EC
-	MODULE_NAME		("ecspace")
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_space_setup
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_space_setup (
-	acpi_handle		region_handle,
-	u32			function,
-	void			*handler_context,
-	void			**return_context)
-{
-	/*
-	 * The EC object is in the handler context and is needed
-	 * when calling the ec_space_handler.
-	 */
-	*return_context = handler_context;
-
-	return AE_OK;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_space_handler
- *
- * PARAMETERS:  function            - Read or Write operation
- *              address             - Where in the space to read or write
- *              bit_width           - Field width in bits (should be 8)
- *              value               - Pointer to in or out value
- *              context             - context pointer
- *
- * RETURN:
- *
- * DESCRIPTION: Handler for the Embedded Controller (EC) address space
- *              (Op Region)
- *
- ****************************************************************************/
-
-acpi_status
-ec_space_handler (
-	u32                     function,
-	ACPI_PHYSICAL_ADDRESS   address,
-	u32                     bit_width,
-	u32                     *value,
-	void                    *handler_context,
-	void                    *region_context)
-{
-	acpi_status             status = AE_OK;
-	EC_CONTEXT              *ec = NULL;
-	EC_REQUEST              ec_request;
-
-	FUNCTION_TRACE("ec_space_handler");
-
-	if (address > 0xFF || bit_width != 8 || !value || !handler_context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ec = (EC_CONTEXT*)handler_context;
-
-	switch (function) {
-
-	case ACPI_READ_ADR_SPACE:
-		ec_request.command = EC_COMMAND_READ;
-		ec_request.address = address;
-		ec_request.data = 0;
-		break;
-
-	case ACPI_WRITE_ADR_SPACE:
-		ec_request.command = EC_COMMAND_WRITE;
-		ec_request.address = address;
-		ec_request.data = (u8)(*value);
-		break;
-
-	default:
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Received request with invalid function [%X].\n", function));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-		break;
-	}
-
-	/*
-	 * Perform the Transaction.
-	 */
-	status = ec_transaction(ec, &ec_request);
-	if (ACPI_SUCCESS(status)) {
-		(*value) = (u32)ec_request.data;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_install_space_handler
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_install_space_handler (
-	EC_CONTEXT              *ec)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_install_space_handler");
-
-	if (!ec) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	status = acpi_install_address_space_handler (ec->acpi_handle,
-		ACPI_ADR_SPACE_EC, &ec_space_handler, &ec_space_setup, ec);
-	
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_remove_space_handler
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_remove_space_handler (
-	EC_CONTEXT              *ec)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_remove_space_handler");
-
-	if (!ec) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	status = acpi_remove_address_space_handler(ec->acpi_handle,
-		ACPI_ADR_SPACE_EC, &ec_space_handler);
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/ec/ectransx.c b/drivers/acpi/ospm/ec/ectransx.c
--- a/drivers/acpi/ospm/ec/ectransx.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,343 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ectransx.c
- *   $Revision: 24 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include "ec.h"
-
-#define _COMPONENT		ACPI_EC
-	MODULE_NAME             ("ectransx")
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_io_wait
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_io_wait (
-	EC_CONTEXT              *ec,
-	EC_EVENT                wait_event)
-{
-	EC_STATUS               ec_status = 0;
-	u32                     i = 100;
-
-	if (!ec || ((wait_event != EC_EVENT_OUTPUT_BUFFER_FULL)
-		&& (wait_event != EC_EVENT_INPUT_BUFFER_EMPTY))) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Wait for Event:
-	 * ---------------
-	 * Poll the EC status register waiting for the event to occur.
-	 * Note that we'll wait a maximum of 1ms in 10us chunks.
-	 */
-	switch (wait_event) {
-
-	case EC_EVENT_OUTPUT_BUFFER_FULL:
-		do {
-			acpi_os_read_port(ec->status_port, &ec_status, 8);
-			if (ec_status & EC_FLAG_OUTPUT_BUFFER) {
-				return(AE_OK);
-			}
-			acpi_os_stall(10);
-		} while (--i>0);
-		break;
-
-	case EC_EVENT_INPUT_BUFFER_EMPTY:
-		do {
-			acpi_os_read_port(ec->status_port, &ec_status, 8);
-			if (!(ec_status & EC_FLAG_INPUT_BUFFER)) {
-				return(AE_OK);
-			}
-			acpi_os_stall(10);
-		} while (--i>0);
-		break;
-	}
-
-	return(AE_TIME);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_io_read
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_io_read (
-	EC_CONTEXT              *ec,
-	ACPI_IO_ADDRESS         io_port,
-	u8                      *data,
-	EC_EVENT                wait_event)
-{
-	acpi_status             status = AE_OK;
-
-	if (!ec || !data) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	acpi_os_read_port(io_port, (u32*) data, 8);
-
-	if (wait_event) {
-		status = ec_io_wait(ec, wait_event);
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_io_write
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_io_write (
-	EC_CONTEXT              *ec,
-	ACPI_IO_ADDRESS         io_port,
-	u8                      data,
-	EC_EVENT                wait_event)
-{
-	acpi_status             status = AE_OK;
-
-	if (!ec) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	acpi_os_write_port(io_port, data, 8);
-
-	if (wait_event) {
-		status = ec_io_wait(ec, wait_event);
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_read
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_read (
-	EC_CONTEXT              *ec,
-	u8                      address,
-	u8                      *data)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_read");
-
-	if (!ec || !data) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (ec->use_global_lock) {
-		status = acpi_acquire_global_lock();
-		if (ACPI_FAILURE(status)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Could not acquire Global Lock\n"));
-			return_ACPI_STATUS(status);
-		}
-	}
-
-	status = ec_io_write(ec, ec->command_port, EC_COMMAND_READ,
-		EC_EVENT_INPUT_BUFFER_EMPTY);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to send 'read command' to EC.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	status = ec_io_write(ec, ec->data_port, address,
-		EC_EVENT_OUTPUT_BUFFER_FULL);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to send 'read address' to EC.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	status = ec_io_read(ec, ec->data_port, data, EC_EVENT_NONE);
-
-	if (ec->use_global_lock) {
-		acpi_release_global_lock();
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Read data [%02x] from address [%02x] on ec [%02x].\n", (*data), address, ec->device_handle));
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_write
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_write (
-	EC_CONTEXT              *ec,
-	u8                      address,
-	u8                      data)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_write");
-
-	if (!ec)
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-
-	if (ec->use_global_lock) {
-		status = acpi_acquire_global_lock();
-		if (ACPI_FAILURE(status)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Could not acquire Global Lock\n"));
-			return_ACPI_STATUS(status);
-		}
-	}
-
-	status = ec_io_write(ec, ec->command_port, EC_COMMAND_WRITE,
-		EC_EVENT_INPUT_BUFFER_EMPTY);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to send 'write command' to EC.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	status = ec_io_write(ec, ec->data_port, address,
-		EC_EVENT_INPUT_BUFFER_EMPTY);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to send 'write address' to EC.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	status = ec_io_write(ec, ec->data_port, data,
-		EC_EVENT_INPUT_BUFFER_EMPTY);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to send 'write data' to EC.\n"));
-		return_ACPI_STATUS(status);
-	}
-
-	if (ec->use_global_lock) {
-		acpi_release_global_lock();
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Wrote data [%02x] to address [%02x] on ec [%02x].\n", data, address, ec->device_handle));
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    ec_transaction
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-ec_transaction (
-	EC_CONTEXT              *ec,
-	EC_REQUEST              *request)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("ec_transaction");
-
-	if (!ec || !request) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Obtain mutex to serialize all EC transactions.
-	 */
-	status = acpi_os_wait_semaphore(ec->mutex, 1, EC_DEFAULT_TIMEOUT);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Perform the transaction.
-	 */
-	switch (request->command) {
-
-	case EC_COMMAND_READ:
-		status = ec_read(ec, request->address, &(request->data));
-		break;
-
-	case EC_COMMAND_WRITE:
-		status = ec_write(ec, request->address, request->data);
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	/*
-	 * Signal the mutex to indicate transaction completion.
-	 */
-	acpi_os_signal_semaphore(ec->mutex, 1);
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/include/ac.h b/drivers/acpi/ospm/include/ac.h
--- a/drivers/acpi/ospm/include/ac.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,102 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ac.h
- *   $Revision: 6 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef __AC_H__
-#define __AC_H__
-
-#include <actypes.h>
-#include <acexcep.h>
-#include <bm.h>
-
-
-/*****************************************************************************
- *                            Types & Other Defines
- *****************************************************************************/
-
-/*
- * Notifications:
- * --------------
- */
-#define AC_NOTIFY_STATUS_CHANGE	((BM_NOTIFY) 0x80)
-
-/*
- * Hardware IDs:
- * -------------
- */
-#define AC_HID_AC_ADAPTER	"ACPI0003"
-
-
-/*
- * Device Context:
- * ---------------
- */
-typedef struct
-{
-	BM_HANDLE		device_handle;
-	acpi_handle		acpi_handle;
-	char			uid[9];
-	u32 			is_online;
-} AC_CONTEXT;
-
-
-/*****************************************************************************
- *                              Function Prototypes
- *****************************************************************************/
-
-acpi_status
-ac_initialize (void);
-
-acpi_status
-ac_terminate (void);
-
-acpi_status
-ac_notify (
-	u32			notify_type,
-	u32 			device,
-	void			**context);
-
-acpi_status
-ac_request(
-	BM_REQUEST		*request_info,
-	void			*context);
-
-/* AC Adapter Driver OSL */
-
-acpi_status
-ac_osl_add_device (
-	AC_CONTEXT		*ac_adapter);
-
-acpi_status
-ac_osl_remove_device (
-	AC_CONTEXT		*ac_adapter);
-
-acpi_status
-ac_osl_generate_event (
-	u32			event,
-	AC_CONTEXT		*ac_adapter);
-
-
-#endif	/* __AC_H__ */
diff -Nru a/drivers/acpi/ospm/include/bm.h b/drivers/acpi/ospm/include/bm.h
--- a/drivers/acpi/ospm/include/bm.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,583 +0,0 @@
-/*****************************************************************************
- *
- * Module name: bm.h
- *   $Revision: 41 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __BM_H__
-#define __BM_H__
-
-#include <actypes.h>
-#include <acexcep.h>
-
-
-/*****************************************************************************
- *                               Types & Defines
- *****************************************************************************/
-
-/*
- * Output Flags (Debug):
- * ---------------------
- */
-#define BM_PRINT_ALL		(0x00000000)
-#define BM_PRINT_GROUP		(0x00000001)
-#define BM_PRINT_LINKAGE	(0x00000002)
-#define BM_PRINT_IDENTIFICATION	(0x00000004)
-#define BM_PRINT_POWER		(0x00000008)
-#define BM_PRINT_PRESENT	(0x00000010)
-
-
-/*
- * BM_COMMAND:
- * -----------
- */
-typedef u32			BM_COMMAND;
-
-#define BM_COMMAND_UNKNOWN	((BM_COMMAND) 0x00)
-
-#define BM_COMMAND_GET_POWER_STATE ((BM_COMMAND) 0x01)
-#define BM_COMMAND_SET_POWER_STATE ((BM_COMMAND) 0x02)
-
-#define BM_COMMAND_DEVICE_SPECIFIC ((BM_COMMAND) 0x80)
-
-/*
- * BM_NOTIFY:
- * ----------
- * Standard ACPI notification values, from section 5.6.3 of the ACPI 2.0
- * specification.  Note that the Bus Manager internally handles all
- * standard ACPI notifications -- driver modules are never sent these
- * values (see "Bus Manager Notifications", below).
- */
-typedef u32			BM_NOTIFY;
-
-#define BM_NOTIFY_BUS_CHECK	((BM_NOTIFY) 0x00)
-#define BM_NOTIFY_DEVICE_CHECK	((BM_NOTIFY) 0x01)
-#define BM_NOTIFY_DEVICE_WAKE	((BM_NOTIFY) 0x02)
-#define BM_NOTIFY_EJECT_REQUEST	((BM_NOTIFY) 0x03)
-#define BM_NOTIFY_DEVICE_CHECK_LIGHT ((BM_NOTIFY) 0x04)
-#define BM_NOTIFY_FREQUENCY_MISMATCH ((BM_NOTIFY) 0x05)
-#define BM_NOTIFY_BUS_MODE_MISMATCH ((BM_NOTIFY) 0x06)
-#define BM_NOTIFY_POWER_FAULT	((BM_NOTIFY) 0x07)
-
-/*
- * These are a higher-level abstraction of ACPI notifications, intended
- * for consumption by driver modules to facilitate Pn_p.
- */
-#define BM_NOTIFY_UNKNOWN	((BM_NOTIFY) 0x00)
-#define BM_NOTIFY_DEVICE_ADDED	((BM_NOTIFY) 0x01)
-#define BM_NOTIFY_DEVICE_REMOVED ((BM_NOTIFY) 0x02)
-
-
-/*
- * BM_HANDLE:
- * ----------
- */
-typedef u32			BM_HANDLE;
-
-#define BM_HANDLE_ROOT		((BM_HANDLE) 0x00000000)
-#define BM_HANDLE_UNKNOWN	((BM_HANDLE) 0xFFFFFFFF)
-#define BM_HANDLES_MAX		100
-
-
-/*
- * BM_HANDLE_LIST:
- * ---------------
- */
-typedef struct
-{
-	u32			count;
-	BM_HANDLE		handles[BM_HANDLES_MAX];
-} BM_HANDLE_LIST;
-
-
-/*
- * BM_DEVICE_TYPE:
- * ---------------
- */
-typedef u32			BM_DEVICE_TYPE;
-
-#define BM_TYPE_UNKNOWN		((BM_DEVICE_TYPE) 0x00000000)
-
-#define BM_TYPE_SYSTEM		((BM_DEVICE_TYPE) 0x00000001)
-#define BM_TYPE_SCOPE		((BM_DEVICE_TYPE) 0x00000002)
-#define BM_TYPE_PROCESSOR	((BM_DEVICE_TYPE) 0x00000003)
-#define BM_TYPE_THERMAL_ZONE	((BM_DEVICE_TYPE) 0x00000004)
-#define BM_TYPE_POWER_RESOURCE	((BM_DEVICE_TYPE) 0x00000005)
-#define BM_TYPE_DEVICE		((BM_DEVICE_TYPE) 0x00000006)
-#define BM_TYPE_FIXED_BUTTON	((BM_DEVICE_TYPE) 0x00000007)
-
-
-/*
- * BM_DEVICE_UID:
- * --------------
- */
-typedef char			BM_DEVICE_UID[9];
-
-#define BM_UID_UNKNOWN		'0'
-
-
-/*
- * BM_DEVICE_HID:
- * --------------
- */
-typedef char			BM_DEVICE_HID[9];
-
-#define BM_HID_UNKNOWN		'\0'
-#define BM_HID_POWER_BUTTON	"PNP0C0C"
-#define BM_HID_SLEEP_BUTTON	"PNP0C0E"
-
-/*
- * BM_DEVICE_ADR:
- * --------------
- */
-typedef u32			BM_DEVICE_ADR;
-
-#define BM_ADDRESS_UNKNOWN	0
-
-
-/*
- * BM_DEVICE_FLAGS:
- * ----------------
- * The encoding of BM_DEVICE_FLAGS is illustrated below.
- * Note that a set bit (1) indicates the property is TRUE
- * (e.g. if bit 0 is set then the device has dynamic status).
- * +--+------------+-+-+-+-+-+-+-+
- * |31| Bits 30:7  |6|5|4|3|2|1|0|
- * +--+------------+-+-+-+-+-+-+-+
- *   |       |      | | | | | | |
- *   |       |      | | | | | | +- Dynamic status?
- *   |       |      | | | | | +--- Identifiable?
- *   |       |      | | | | +----- Configurable?
- *   |       |      | | | +------- Power Control?
- *   |       |      | | +--------- Ejectable?
- *   |       |      | +----------- Docking Station?
- *   |       |      +------------- Fixed-Feature?
- *   |       +-------------------- <Reserved>
- *   +---------------------------- Driver Control?
- *
- * Dynamic status:  Device has a _STA object.
- * Identifiable:    Device has a _HID and/or _ADR and possibly other
- *                  identification objects defined.
- * Configurable:    Device has a _CRS and possibly other configuration
- *                  objects defined.
- * Power Control:   Device has a _PR0 and/or _PS0 and possibly other
- *                  power management objects defined.
- * Ejectable:       Device has an _EJD and/or _EJx and possibly other
- *                  dynamic insertion/removal objects defined.
- * Docking Station: Device has a _DCK object defined.
- * Fixed-Feature:   Device does not exist in the namespace; was
- *                  enumerated as a fixed-feature (e.g. power button).
- * Driver Control:  A driver has been installed for this device.
- */
-typedef u32			BM_DEVICE_FLAGS;
-
-#define BM_FLAGS_UNKNOWN	((BM_DEVICE_FLAGS) 0x00000000)
-
-#define BM_FLAGS_DYNAMIC_STATUS	((BM_DEVICE_FLAGS) 0x00000001)
-#define BM_FLAGS_IDENTIFIABLE	((BM_DEVICE_FLAGS) 0x00000002)
-#define BM_FLAGS_CONFIGURABLE	((BM_DEVICE_FLAGS) 0x00000004)
-#define BM_FLAGS_POWER_CONTROL	((BM_DEVICE_FLAGS) 0x00000008)
-#define BM_FLAGS_EJECTABLE	((BM_DEVICE_FLAGS) 0x00000010)
-#define BM_FLAGS_DOCKING_STATION ((BM_DEVICE_FLAGS) 0x00000020)
-#define BM_FLAGS_FIXED_FEATURE	((BM_DEVICE_FLAGS) 0x00000040)
-#define BM_FLAGS_DRIVER_CONTROL	((BM_DEVICE_FLAGS) 0x80000000)
-
-
-/*
- * Device PM Flags:
- * ----------------
- * +-----------+-+-+-+-+-+-+-+
- * | Bits 31:7 |6|5|4|3|2|1|0|
- * +-----------+-+-+-+-+-+-+-+
- *       |      | | | | | | |
- *       |      | | | | | | +- D0 Support?
- *       |      | | | | | +--- D1 Support?
- *       |      | | | | +----- D2 Support?
- *       |      | | | +------- D3 Support?
- *       |      | | +--------- Power State Queriable?
- *       |      | +----------- Inrush Current?
- *       |      +------------- Wake Capable?
- *       +-------------------- <Reserved>
- *
- * D0-D3 Support:   Device supports corresponding Dx state.
- * Power State:     Device has a _PSC (current power state) object defined.
- * Inrush Current:  Device has an _IRC (inrush current) object defined.
- * Wake Capable:    Device has a _PRW (wake-capable) object defined.
- */
-#define BM_FLAGS_D0_SUPPORT	((BM_DEVICE_FLAGS) 0x00000001)
-#define BM_FLAGS_D1_SUPPORT	((BM_DEVICE_FLAGS) 0x00000002)
-#define BM_FLAGS_D2_SUPPORT	((BM_DEVICE_FLAGS) 0x00000004)
-#define BM_FLAGS_D3_SUPPORT	((BM_DEVICE_FLAGS) 0x00000008)
-#define BM_FLAGS_POWER_STATE	((BM_DEVICE_FLAGS) 0x00000010)
-#define BM_FLAGS_INRUSH_CURRENT	((BM_DEVICE_FLAGS) 0x00000020)
-#define BM_FLAGS_WAKE_CAPABLE	((BM_DEVICE_FLAGS) 0x00000040)
-
-
-/*
- * BM_DEVICE_STATUS:
- * -----------------
- * The encoding of BM_DEVICE_STATUS is illustrated below.
- * Note that a set bit (1) indicates the property is TRUE
- * (e.g. if bit 0 is set then the device is present).
- * +-----------+-+-+-+-+-+
- * | Bits 31:4 |4|3|2|1|0|
- * +-----------+-+-+-+-+-+
- *       |      | | | | |
- *       |      | | | | +- Present?
- *       |      | | | +--- Enabled?
- *       |      | | +----- Show in UI?
- *       |      | +------- Functioning?
- *       |      +--------- Battery Present?
- *       +---------------- <Reserved>
- */
-typedef u32			BM_DEVICE_STATUS;
-
-#define BM_STATUS_UNKNOWN	((BM_DEVICE_STATUS) 0x00000000)
-#define BM_STATUS_PRESENT	((BM_DEVICE_STATUS) 0x00000001)
-#define BM_STATUS_ENABLED	((BM_DEVICE_STATUS) 0x00000002)
-#define BM_STATUS_SHOW_UI	((BM_DEVICE_STATUS) 0x00000004)
-#define BM_STATUS_FUNCTIONING	((BM_DEVICE_STATUS) 0x00000008)
-#define BM_STATUS_BATTERY_PRESENT ((BM_DEVICE_STATUS) 0x00000010)
-#define BM_STATUS_DEFAULT	((BM_DEVICE_STATUS) 0x0000000F)
-
-
-/*
- * BM_POWER_STATE:
- * ---------------
- */
-typedef u32			BM_POWER_STATE;
-
-
-/*
- * BM_DEVICE_ID:
- * -------------
- */
-typedef struct
-{
-	BM_DEVICE_TYPE		type;
-	BM_DEVICE_UID		uid;
-	BM_DEVICE_HID		hid;
-	BM_DEVICE_ADR		adr;
-} BM_DEVICE_ID;
-
-
-/*
- * BM_DEVICE_POWER:
- * ----------------
- * Structure containing basic device power management information.
- */
-typedef struct
-{
-	BM_DEVICE_FLAGS		flags;
-	BM_POWER_STATE		state;
-	BM_DEVICE_FLAGS		dx_supported[ACPI_S_STATE_COUNT];
-} BM_DEVICE_POWER;
-
-
-/*
- * BM_DEVICE:
- * ----------
- */
-typedef struct
-{
-	BM_HANDLE		handle;
-	acpi_handle  		acpi_handle;
-	BM_DEVICE_FLAGS		flags;
-	BM_DEVICE_STATUS	status;
-	BM_DEVICE_ID		id;
-	BM_DEVICE_POWER		power;
-} BM_DEVICE;
-
-
-/*
- * BM_SEARCH:
- * ----------
- * Structure used for searching the ACPI Bus Manager's device hierarchy.
- */
-typedef struct
-{
-	BM_DEVICE_ID		criteria;
-	BM_HANDLE_LIST		results;
-} BM_SEARCH;
-
-
-/*
- * BM_REQUEST:
- * -----------
- * Structure used for sending requests to/through the ACPI Bus Manager.
- */
-typedef struct
-{
-	acpi_status		status;
-	BM_COMMAND		command;
-	BM_HANDLE		handle;
-	acpi_buffer		buffer;
-} BM_REQUEST;
-
-
-/*
- * Driver Registration:
- * --------------------
- */
-
-/* Driver Context */
-typedef void *			BM_DRIVER_CONTEXT;
-
-/* Notification Callback Function */
-typedef
-acpi_status (*BM_DRIVER_NOTIFY) (
-	BM_NOTIFY		notify_type,
-	BM_HANDLE		device_handle,
-	BM_DRIVER_CONTEXT	*context);
-
-/* Request Callback Function */
-typedef
-acpi_status (*BM_DRIVER_REQUEST) (
-	BM_REQUEST		*request,
-	BM_DRIVER_CONTEXT	context);
-
-/* Driver Registration */
-typedef struct
-{
-	BM_DRIVER_NOTIFY	notify;
-	BM_DRIVER_REQUEST	request;
-	BM_DRIVER_CONTEXT	context;
-} BM_DRIVER;
-
-
-/*
- * BM_NODE:
- * --------
- * Structure used to maintain the device hierarchy.
- */
-typedef struct _BM_NODE
-{
-	BM_DEVICE		device;
-	BM_DRIVER		driver;
-	struct _BM_NODE		*parent;
-	struct _BM_NODE		*next;
-	struct
-	{
-		struct _BM_NODE		*head;
-		struct _BM_NODE		*tail;
-	}			scope;
-} BM_NODE;
-
-
-/*
- * BM_NODE_LIST:
- * -------------
- * Structure used to maintain an array of node pointers.
- */
-typedef struct
-{
-	u32			count;
-	BM_NODE			*nodes[BM_HANDLES_MAX];
-} BM_NODE_LIST;
-
-
-/*****************************************************************************
- *                                  Macros
- *****************************************************************************/
-
-/*
- * Device Presence:
- * ----------------
- * Note that status (_STA) means something different for power resources
- * (they're assumed to always be present).
- */
-#define BM_DEVICE_PRESENT(d)	((d->id.type!=BM_TYPE_POWER_RESOURCE)?(d->status & BM_STATUS_PRESENT):TRUE)
-#define BM_NODE_PRESENT(n)	((n->device.id.type!=BM_TYPE_POWER_RESOURCE)?(n->device.status & BM_STATUS_PRESENT):TRUE)
-
-/*
- * Device Flags:
- * -------------
- */
-#define BM_IS_DRIVER_CONTROL(d)	(d->flags & BM_FLAGS_DRIVER_CONTROL)
-#define BM_IS_POWER_CONTROL(d)	(d->flags & BM_FLAGS_POWER_CONTROL)
-
- /*
- * Device Power Flags:
- * -------------------
- */
-#define BM_IS_POWER_STATE(d)	(d->power.flags & BM_FLAGS_POWER_STATE)
-
-/*****************************************************************************
- *                             Function Prototypes
- *****************************************************************************/
-
-/* bm.c */
-
-acpi_status
-bm_initialize (void);
-
-acpi_status
-bm_terminate (void);
-
-acpi_status
-bm_get_status (
-	BM_DEVICE		*device);
-
-acpi_status
-bm_get_handle (
-	acpi_handle             acpi_handle,
-	BM_HANDLE               *device_handle);
-
-acpi_status
-bm_get_node (
-	BM_HANDLE               device_handle,
-	acpi_handle             acpi_handle,
-	BM_NODE			**node);
-
-/* bmsearch.c */
-
-acpi_status
-bm_search(
-	BM_HANDLE               device_handle,
-	BM_DEVICE_ID            *criteria,
-	BM_HANDLE_LIST          *results);
-
-/* bmnotify.c */
-
-void
-bm_notify (
-	acpi_handle             acpi_handle,
-	u32                     notify_value,
-	void                    *context);
-
-/* bm_request.c */
-
-acpi_status
-bm_request (
-	BM_REQUEST		*request_info);
-
-/* bmdriver.c */
-
-acpi_status
-bm_get_device_power_state (
-	BM_HANDLE               device_handle,
-	BM_POWER_STATE		*state);
-
-acpi_status
-bm_set_device_power_state (
-	BM_HANDLE               device_handle,
-	BM_POWER_STATE		state);
-
-acpi_status
-bm_get_device_status (
-	BM_HANDLE               device_handle,
-	BM_DEVICE_STATUS        *device_status);
-
-acpi_status
-bm_get_device_info (
-	BM_HANDLE               device_handle,
-	BM_DEVICE		**device_info);
-
-acpi_status
-bm_get_device_context (
-	BM_HANDLE               device_handle,
-	BM_DRIVER_CONTEXT	*context);
-
-acpi_status
-bm_register_driver (
-	BM_DEVICE_ID		*criteria,
-	BM_DRIVER		*driver);
-
-acpi_status
-bm_unregister_driver (
-	BM_DEVICE_ID		*criteria,
-	BM_DRIVER		*driver);
-
-/* bmpm.c */
-
-acpi_status
-bm_get_pm_capabilities (
-	BM_NODE			*node);
-
-acpi_status
-bm_get_power_state (
-	BM_NODE			*node);
-
-acpi_status
-bm_set_power_state (
-	BM_NODE			*node,
-	BM_POWER_STATE          target_state);
-
-/* bmpower.c */
-
-acpi_status
-bm_pr_initialize (void);
-
-acpi_status
-bm_pr_terminate (void);
-	
-/* bmutils.c */
-
-acpi_status
-bm_cast_buffer (
-	acpi_buffer             *buffer,
-	void                    **pointer,
-	u32                     length);
-
-acpi_status
-bm_copy_to_buffer (
-	acpi_buffer             *buffer,
-	void                    *data,
-	u32                     length);
-
-acpi_status
-bm_extract_package_data (
-	acpi_object             *package,
-	acpi_buffer             *format,
-	acpi_buffer             *buffer);
-
-acpi_status
-bm_evaluate_object (
-	acpi_handle             acpi_handle,
-	acpi_string             pathname,
-	acpi_object_list        *arguments,
-	acpi_buffer             *buffer);
-
-acpi_status
-bm_evaluate_simple_integer (
-	acpi_handle             acpi_handle,
-	acpi_string             pathname,
-	u32                     *data);
-
-acpi_status
-bm_evaluate_reference_list (
-	acpi_handle             acpi_handle,
-	acpi_string             pathname,
-	BM_HANDLE_LIST          *reference_list);
-
-/* ACPI Bus Driver OSL */
-
-acpi_status
-bm_osl_generate_event (
-	BM_HANDLE		device_handle,
-	char			*device_type,
-	char			*device_instance,
-	u32			event_type,
-	u32			event_data);
-
-
-#endif  /* __BM_H__ */
diff -Nru a/drivers/acpi/ospm/include/bmpower.h b/drivers/acpi/ospm/include/bmpower.h
--- a/drivers/acpi/ospm/include/bmpower.h	Fri Mar 15 17:51:04 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,75 +0,0 @@
-/*****************************************************************************
- *
- * Module name: bmpower.h
- *   $Revision: 9 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __BMPOWER_H__
-#define __BMPOWER_H__
-
-#include "bm.h"
-
-
-/*****************************************************************************
- *                               Types & Defines
- *****************************************************************************/
-
-
-/*
- * BM_POWER_RESOURCE:
- * ------------------
- */
-typedef struct
-{
-	BM_HANDLE           device_handle;
-	acpi_handle         acpi_handle;
-	BM_POWER_STATE      system_level;
-	u32                 resource_order;
-	BM_POWER_STATE      state;
-	u32                 reference_count;
-} BM_POWER_RESOURCE;
-
-
-/*****************************************************************************
- *                             Function Prototypes
- *****************************************************************************/
-
-/* bmpower.c */
-
-acpi_status
-bm_pr_initialize (void);
-
-acpi_status
-bm_pr_terminate (void);
-
-acpi_status
-bm_pr_list_get_state (
-	BM_HANDLE_LIST          *resource_list,
-	BM_POWER_STATE          *power_state);
-
-acpi_status
-bm_pr_list_transition (
-	BM_HANDLE_LIST          *current_list,
-	BM_HANDLE_LIST          *target_list);
-
-
-#endif  /* __BMPOWER_H__ */
diff -Nru a/drivers/acpi/ospm/include/bn.h b/drivers/acpi/ospm/include/bn.h
--- a/drivers/acpi/ospm/include/bn.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,122 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bn.h
- *   $Revision: 12 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef __BN_H__
-#define __BN_H__
-
-#include <actypes.h>
-#include <acexcep.h>
-#include <bm.h>
-
-
-/*****************************************************************************
- *                            Types & Other Defines
- *****************************************************************************/
-
-/*
- * Notifications:
- * ---------------------
- */
-#define BN_NOTIFY_STATUS_CHANGE	((BM_NOTIFY) 0x80)
-
-
-/*
- * Types:
- * ------
- */
-#define BN_TYPE_POWER_BUTTON	0x01
-#define BN_TYPE_POWER_BUTTON_FIXED 0x02
-#define BN_TYPE_SLEEP_BUTTON	0x03
-#define BN_TYPE_SLEEP_BUTTON_FIXED 0x04
-#define BN_TYPE_LID_SWITCH	0x05
-
-
-/*
- * Hardware IDs:
- * -------------
- * TBD: Power and Sleep button HIDs also exist in <bm.h>.  Should all
- *      HIDs (ACPI well-known devices) exist in one place (e.g.
- *      acpi_hid.h)?
- */
-#define BN_HID_POWER_BUTTON	"PNP0C0C"
-#define BN_HID_SLEEP_BUTTON	"PNP0C0E"
-#define BN_HID_LID_SWITCH	"PNP0C0D"
-
-
-/*
- * Device Context:
- * ---------------
- */
-typedef struct
-{
-	BM_HANDLE		device_handle;
-	acpi_handle		acpi_handle;
-	u32			type;
-} BN_CONTEXT;
-
-
-/******************************************************************************
- *                              Function Prototypes
- *****************************************************************************/
-
-acpi_status
-bn_initialize (void);
-
-acpi_status
-bn_terminate (void);
-
-acpi_status
-bn_notify_fixed (
-	void			*context);
-
-acpi_status
-bn_notify (
-	u32			notify_type,
-	u32			device,
-	void			**context);
-
-acpi_status
-bn_request(
-	BM_REQUEST		*request_info,
-	void			*context);
-
-/* Button OSL */
-
-acpi_status
-bn_osl_add_device (
-	BN_CONTEXT		*button);
-
-acpi_status
-bn_osl_remove_device (
-	BN_CONTEXT		*button);
-
-acpi_status
-bn_osl_generate_event (
-	u32			event,
-	BN_CONTEXT		*button);
-
-
-#endif	/* __BN_H__ */
diff -Nru a/drivers/acpi/ospm/include/bt.h b/drivers/acpi/ospm/include/bt.h
--- a/drivers/acpi/ospm/include/bt.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,164 +0,0 @@
-/******************************************************************************
- *
- * Module Name: bt.h
- *   $Revision: 18 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef __BT_H__
-#define __BT_H__
-
-#include <actypes.h>
-#include <acexcep.h>
-#include <bm.h>
-
-
-/*****************************************************************************
- *                Types & Other Defines
- *****************************************************************************/
-
-/*! [Begin] no source code translation */
-
-#define BT_UNKNOWN		0xFFFFFFFF
-#define BT_POWER_UNITS_DEFAULT  "?"
-#define BT_POWER_UNITS_WATTS    "mW"
-#define BT_POWER_UNITS_AMPS	"mA"
-
-/*! [End] no source code translation !*/
-
-/*
- * Battery Notifications:
- * ----------------------
- */
-#define BT_NOTIFY_STATUS_CHANGE ((BM_NOTIFY) 0x80)
-#define BT_NOTIFY_INFORMATION_CHANGE ((BM_NOTIFY) 0x81)
-
-
-/*
- * Hardware IDs:
- * -------------
- */
-#define BT_HID_CM_BATTERY   "PNP0C0A"
-
-
-/*
- * BT_CM_BATTERY_INFO:
- * -------------------
- */
-typedef struct
-{
-	acpi_integer    power_unit;
-	acpi_integer    design_capacity;
-	acpi_integer    last_full_capacity;
-	acpi_integer    battery_technology;
-	acpi_integer    design_voltage;
-	acpi_integer    design_capacity_warning;
-	acpi_integer    design_capacity_low;
-	acpi_integer    battery_capacity_granularity_1;
-	acpi_integer    battery_capacity_granularity_2;
-	acpi_string     model_number;
-	acpi_string     serial_number;
-	acpi_string     battery_type;
-	acpi_string     oem_info;
-
-} BT_BATTERY_INFO;
-
-
-/*
- * BT_CM_BATTERY_STATUS:
- * ---------------------
- */
-typedef struct
-{
-	acpi_integer    state;
-	acpi_integer    present_rate;
-	acpi_integer    remaining_capacity;
-	acpi_integer    present_voltage;
-
-} BT_BATTERY_STATUS;
-
-
-/*
- * BT_CONTEXT:
- * -----------
- */
-typedef struct
-{
-	BM_HANDLE       device_handle;
-	acpi_handle     acpi_handle;
-	char            uid[9];
-	acpi_string     power_units;
-	u8              is_present;
-
-} BT_CONTEXT;
-
-
-/*****************************************************************************
- *              Function Prototypes
- *****************************************************************************/
-
-/* bt.c */
-
-acpi_status
-bt_initialize (void);
-
-acpi_status
-bt_terminate (void);
-
-acpi_status
-bt_notify (
-	u32         notify_type,
-	u32         device,
-	void        **context);
-
-acpi_status
-bt_request(
-	BM_REQUEST  *request_info,
-	void        *context);
-
-acpi_status
-bt_get_status (
-	BT_CONTEXT		*battery,
-	BT_BATTERY_STATUS   **battery_status);
-
-acpi_status
-bt_get_info (
-	BT_CONTEXT      *battery,
-	BT_BATTERY_INFO **battery_info);
-
-/* Battery OSL */
-
-acpi_status
-bt_osl_add_device (
-	BT_CONTEXT      *battery);
-
-acpi_status
-bt_osl_remove_device (
-	BT_CONTEXT      *battery);
-
-acpi_status
-bt_osl_generate_event (
-	u32         event,
-	BT_CONTEXT      *battery);
-
-
-#endif  /* __BT_H__ */
diff -Nru a/drivers/acpi/ospm/include/ec.h b/drivers/acpi/ospm/include/ec.h
--- a/drivers/acpi/ospm/include/ec.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,202 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: ec.h
- *   $Revision: 19 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef __EC_H__
-#define __EC_H__
-
-#include <linux/spinlock.h>
-#include <asm/semaphore.h>
-#include <actypes.h>
-#include <acexcep.h>
-#include <bm.h>
-
-
-/*****************************************************************************
- *                            Types & Other Defines
- *****************************************************************************/
-
-#define EC_DEFAULT_TIMEOUT	1000		/* 1 second */
-#define EC_GPE_UNKNOWN		0xFFFFFFFF
-#define EC_PORT_UNKNOWN		0x00000000
-#define EC_BURST_ENABLE_ACKNOWLEDGE 0x90
-
-
-/*
- * Commands:
- * ---------
- */
-typedef u8			EC_COMMAND;
-
-#define EC_COMMAND_UNKNOWN	((EC_COMMAND) 0x00)
-#define EC_COMMAND_READ		((EC_COMMAND) 0x80)
-#define EC_COMMAND_WRITE	((EC_COMMAND) 0x81)
-#define EC_COMMAND_QUERY	((EC_COMMAND) 0x84)
-
-
-/*
- * EC_STATUS:
- * ----------
- * The encoding of the EC status register is illustrated below.
- * Note that a set bit (1) indicates the property is TRUE
- * (e.g. if bit 0 is set then the output buffer is full).
- * +-+-+-+-+-+-+-+-+
- * |7|6|5|4|3|2|1|0|
- * +-+-+-+-+-+-+-+-+
- *  | | | | | | | |
- *  | | | | | | | +- Output Buffer Full (OBF)?
- *  | | | | | | +--- Input Buffer Full (IBF)?
- *  | | | | | +----- <reserved>
- *  | | | | +------- data Register is command Byte?
- *  | | | +--------- Burst Mode Enabled?
- *  | | +----------- SCI event?
- *  | +------------- SMI event?
- *  +--------------- <Reserved>
- *
- */
-typedef u32			EC_STATUS;
-
-#define EC_FLAG_OUTPUT_BUFFER	((EC_STATUS) 0x01)
-#define EC_FLAG_INPUT_BUFFER	((EC_STATUS) 0x02)
-#define EC_FLAG_BURST_MODE	((EC_STATUS) 0x10)
-#define EC_FLAG_SCI		((EC_STATUS) 0x20)
-
-
-/*
- * EC_EVENT:
- * ---------
- */
-typedef u32			EC_EVENT;
-
-#define EC_EVENT_UNKNOWN	((EC_EVENT) 0x00)
-#define EC_EVENT_NONE		((EC_EVENT) 0x00)
-#define EC_EVENT_OUTPUT_BUFFER_FULL ((EC_EVENT) 0x01)
-#define EC_EVENT_INPUT_BUFFER_EMPTY ((EC_EVENT) 0x02)
-#define EC_EVENT_SCI		((EC_EVENT) 0x03)
-
-
-/*
- * Hardware IDs:
- * -------------
- */
-#define EC_HID_EC		"PNP0C09"
-
-
-/*
- * EC_REQUEST:
- * -----------
- */
-typedef struct
-{
-	EC_COMMAND              command;
-	u8                      address;
-	u8                      data;
-} EC_REQUEST;
-
-
-/*
- * Device Context:
- * ---------------
- */
-typedef struct
-{
-	BM_HANDLE               device_handle;
-	acpi_handle             acpi_handle;
-	u32                     gpe_bit;
-	u32			status_port;
-	u32			command_port;
-	u32			data_port;
-	u32			use_global_lock;
-	u8                      query_data;
-	acpi_handle             mutex;
-} EC_CONTEXT;
-
-
-/*****************************************************************************
- *                             Function Prototypes
- *****************************************************************************/
-
-/* ec.c */
-
-acpi_status
-ec_initialize(void);
-
-acpi_status
-ec_terminate(void);
-
-acpi_status
-ec_notify (
-	u32                     notify_type,
-	u32                     device,
-	void                    **context);
-
-acpi_status
-ec_request(
-	BM_REQUEST              *request_info,
-	void                    *context);
-
-/* ectransx.c */
-
-acpi_status
-ec_transaction (
-	EC_CONTEXT              *ec,
-	EC_REQUEST              *ec_request);
-
-acpi_status
-ec_io_read (
-	EC_CONTEXT              *ec,
-	u32         		io_port,
-	u8                      *data,
-	EC_EVENT                wait_event);
-
-acpi_status
-ec_io_write (
-	EC_CONTEXT              *ec,
-	u32         		io_port,
-	u8                      data,
-	EC_EVENT                wait_event);
-
-/* ecgpe.c */
-
-acpi_status
-ec_install_gpe_handler (
-	EC_CONTEXT              *ec);
-
-acpi_status
-ec_remove_gpe_handler (
-	EC_CONTEXT              *ec);
-
-/* ecspace.c */
-
-acpi_status
-ec_install_space_handler (
-	EC_CONTEXT              *ec);
-
-acpi_status
-ec_remove_space_handler (
-	EC_CONTEXT              *ec);
-
-
-#endif  /* __EC_H__ */
diff -Nru a/drivers/acpi/ospm/include/pr.h b/drivers/acpi/ospm/include/pr.h
--- a/drivers/acpi/ospm/include/pr.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,265 +0,0 @@
-/******************************************************************************
- *
- * Module Name: processor.h
- *              $Revision: 13 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __PR_H__
-#define __PR_H__
-
-#include <bm.h>
-
-
-/*****************************************************************************
- *                             Types & Other Defines
- *****************************************************************************/
-
-
-#define PR_MAX_POWER_STATES	4
-#define PR_MAX_THROTTLE_STATES  8
-#define PR_MAX_PERF_STATES	32
-#define PR_MAX_C2_LATENCY	100
-#define PR_MAX_C3_LATENCY	1000
-
-
-/*
- * Commands:
- * ---------
- */
-#define PR_COMMAND_GET_POWER_INFO ((BM_COMMAND) 0x80)
-#define PR_COMMAND_SET_POWER_INFO ((BM_COMMAND) 0x81)
-#define PR_COMMAND_GET_PERF_INFO ((BM_COMMAND) 0x82)
-#define PR_COMMAND_GET_PERF_STATE ((BM_COMMAND) 0x83)
-#define PR_COMMAND_SET_PERF_LIMIT ((BM_COMMAND) 0x84)
-
-
-/*
- * Notifications:
- * --------------
- */
-#define PR_NOTIFY_PERF_STATES	((BM_NOTIFY) 0x80)
-#define PR_NOTIFY_POWER_STATES	((BM_NOTIFY) 0x81)
-
-
-/*
- * Performance Control:
- * --------------------
- */
-#define PR_PERF_DEC		0x00
-#define PR_PERF_INC		0x01
-#define PR_PERF_MAX		0xFF
-
-
-/*
- * Power States:
- * -------------
- */
-#define PR_C0			0x00
-#define PR_C1			0x01
-#define PR_C2			0x02
-#define PR_C3			0x03
-
-#define PR_C1_FLAG		0x01;
-#define PR_C2_FLAG		0x02;
-#define PR_C3_FLAG		0x04;
-
-
-/*
- * PR_CX_POLICY_VALUES:
- * --------------------
- */
-typedef struct
-{
-	u32			time_threshold;
-	u32			count_threshold;
-	u32                     bm_threshold;
-	u32         		target_state;
-	u32			count;
-} PR_CX_POLICY_VALUES;
-
-
-/*
- * PR_CX:
- * ------
- */
-typedef struct
-{
-	u32                     latency;
-	u32                     utilization;
-	u8                      is_valid;
-	PR_CX_POLICY_VALUES     promotion;
-	PR_CX_POLICY_VALUES     demotion;
-} PR_CX;
-
-
-/*
- * PR_POWER:
- * ---------
- */
-typedef struct
-{
-	ACPI_PHYSICAL_ADDRESS   p_lvl2;
-	ACPI_PHYSICAL_ADDRESS   p_lvl3;
-	u32                     bm_activity;
-	u32                     active_state;
-	u32			default_state;
-	u32			busy_metric;
-	u32                     state_count;
-	PR_CX                   state[PR_MAX_POWER_STATES];
-} PR_POWER;
-
-
-/*
- * PR_PERFORMANCE_STATE:
- * ---------------------
- */
-typedef struct
-{
-	u32                     performance;
-	u32                     power;
-} PR_PERFORMANCE_STATE;
-
-
-/*
- * PR_PERFORMANCE:
- * ---------------
- */
-typedef struct
-{
-	u32                     active_state;
-	u32			thermal_limit;
-	u32			power_limit;
-	u32                     state_count;
-	PR_PERFORMANCE_STATE    state[PR_MAX_PERF_STATES];
-} PR_PERFORMANCE;
-
-
-/*
- * PR_PBLOCK:
- * ----------
- */
-typedef struct
-{
-	u32                     length;
-	ACPI_PHYSICAL_ADDRESS   address;
-} PR_PBLOCK;
-
-
-/*
- * PR_CONTEXT:
- * -----------
- */
-typedef struct
-{
-	BM_HANDLE               device_handle;
-	acpi_handle             acpi_handle;
-	u32                     uid;
-	PR_PBLOCK               pblk;
-	PR_POWER		power;
-	PR_PERFORMANCE		performance;
-} PR_CONTEXT;
-
-
-/******************************************************************************
- *                             Function Prototypes
- *****************************************************************************/
-
-/* processor.c */
-
-acpi_status
-pr_initialize(void);
-
-acpi_status
-pr_terminate(void);
-
-acpi_status
-pr_notify (
-	BM_NOTIFY               notify_type,
-	BM_HANDLE               device_handle,
-	void                    **context);
-
-acpi_status
-pr_request(
-	BM_REQUEST		*request,
-	void                    *context);
-
-/* prpower.c */
-
-void
-pr_power_idle (void);
-
-acpi_status
-pr_power_add_device (
-	PR_CONTEXT              *processor);
-
-acpi_status
-pr_power_remove_device (
-	PR_CONTEXT              *processor);
-
-acpi_status
-pr_power_initialize (void);
-
-acpi_status
-pr_power_terminate (void);
-
-/* prperf.c */
-
-acpi_status
-pr_perf_get_state (
-	PR_CONTEXT              *processor,
-	u32                     *state);
-
-acpi_status
-pr_perf_set_state (
-	PR_CONTEXT              *processor,
-	u32                     state);
-
-acpi_status
-pr_perf_set_limit (
-	PR_CONTEXT              *processor,
-	u32                     limit);
-
-acpi_status
-pr_perf_add_device (
-	PR_CONTEXT              *processor);
-
-acpi_status
-pr_perf_remove_device (
-	PR_CONTEXT              *processor);
-
-/* Processor Driver OSL */
-
-acpi_status
-pr_osl_add_device (
-	PR_CONTEXT		*processor);
-
-acpi_status
-pr_osl_remove_device (
-	PR_CONTEXT		*processor);
-
-acpi_status
-pr_osl_generate_event (
-	u32			event,
-	PR_CONTEXT		*processor);
-
-
-#endif  /* __PR_H__ */
diff -Nru a/drivers/acpi/ospm/include/sm.h b/drivers/acpi/ospm/include/sm.h
--- a/drivers/acpi/ospm/include/sm.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,91 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: sm.h
- *   $Revision: 3 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#ifndef __SM_H__
-#define __SM_H__
-
-#include <actypes.h>
-#include <acexcep.h>
-#include <bm.h>
-
-
-/*****************************************************************************
- *                            Types & Other Defines
- *****************************************************************************/
-
-#define SM_MAX_SYSTEM_STATES	6	/* S0-S5 */
-
-
- /*
- * Device Context:
- * ---------------
- */
-typedef struct
-{
-	BM_HANDLE		device_handle;
-	acpi_handle 		acpi_handle;
-	u8			states[SM_MAX_SYSTEM_STATES];
-} SM_CONTEXT;
-
-
-/*****************************************************************************
- *                              Function Prototypes
- *****************************************************************************/
-
-acpi_status
-sm_initialize (void);
-
-acpi_status
-sm_terminate (void);
-
-acpi_status
-sm_notify (
-	u32			notify_type,
-	u32 			device,
-	void			**context);
-
-acpi_status
-sm_request(
-	BM_REQUEST		*request_info,
-	void			*context);
-
-/* System Driver OSL */
-
-acpi_status
-sm_osl_add_device (
-	SM_CONTEXT		*system);
-
-acpi_status
-sm_osl_remove_device (
-	SM_CONTEXT		*system);
-
-acpi_status
-sm_osl_generate_event (
-	u32			event,
-	SM_CONTEXT		*system);
-
-
-#endif	/* __SM_H__ */
diff -Nru a/drivers/acpi/ospm/include/tz.h b/drivers/acpi/ospm/include/tz.h
--- a/drivers/acpi/ospm/include/tz.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,252 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: tz.h
- *   $Revision: 24 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __TZ_H__
-#define __TZ_H__
-
-/* TBD: Linux-specific */
-#include <linux/module.h>
-#include <linux/timer.h>
-
-#include <bm.h>
-#include <pr.h>
-
-
-/*****************************************************************************
- *                             Types & Other Defines
- *****************************************************************************/
-
-#define TZ_MAX_THRESHOLDS	12	/* _AC0 through _AC9 + _CRT + _PSV */
-#define TZ_MAX_ACTIVE_THRESHOLDS 10	/* _AC0 through _AC9 */
-#define TZ_MAX_COOLING_DEVICES	10	/* TBD: Make size dynamic */
-
-
-/*
- * Notifications:
- * --------------
- */
-#define TZ_NOTIFY_TEMPERATURE_CHANGE ((BM_NOTIFY) 0x80)
-#define TZ_NOTIFY_THRESHOLD_CHANGE ((BM_NOTIFY) 0x81)
-#define TZ_NOTIFY_DEVICE_LISTS_CHANGE ((BM_NOTIFY) 0x82)
-
-
-/*
- * TZ_THRESHOLD_TYPE:
- * ------------------
- */
-typedef u32			TZ_THRESHOLD_TYPE;
-
-#define TZ_THRESHOLD_UNKNOWN	((TZ_THRESHOLD_TYPE) 0x00)
-#define TZ_THRESHOLD_CRITICAL	((TZ_THRESHOLD_TYPE) 0x01)
-
-#define TZ_THRESHOLD_PASSIVE	((TZ_THRESHOLD_TYPE) 0x02)
-#define TZ_THRESHOLD_ACTIVE	((TZ_THRESHOLD_TYPE) 0x03)
-
-
-/*
- * TZ_COOLING_STATE:
- * -----------------
- */
-typedef u32			TZ_COOLING_STATE;
-
-#define TZ_COOLING_UNKNOWN	((TZ_COOLING_STATE) 0x00)
-#define TZ_COOLING_ENABLED	((TZ_COOLING_STATE) 0x01)
-#define TZ_COOLING_DISABLED	((TZ_COOLING_STATE) 0x02)
-
-
-/*
- * TZ_COOLING_MODE:
- * ----------------
- */
-typedef u32			TZ_COOLING_MODE;
-
-#define TZ_COOLING_MODE_ACTIVE	((TZ_COOLING_MODE) 0x00)
-#define TZ_COOLING_MODE_PASSIVE	((TZ_COOLING_MODE) 0x01)
-
-
-/*
- * Thermal State:
- * --------------
- * The encoding of TZ_STATE is illustrated below.
- * Note that a set bit (1) indicates the property is TRUE
- * (e.g. if bit 0 is set then the device has dynamic status).
- * No bits set indicates an OK cooling state.
- * +--+--+--+-----------+----------+
- * |31|30|29| Bits 27:4 | Bits 3:0 |
- * +--+--+--+-----------+----------+
- *  |  |  |       |          |
- *  |  |  |       |          +------ Active Index
- *  |  |  |       +----------------- <reserved>
- *  |  |  +------------------------- Active
- *  |  +---------------------------- Passive
- *  +------------------------------- Critical
- *
- * Active Index:    Value representing the level of active cooling
- *                  presently applied (e.g. 0=_AL0, 9=_AL9).  Only
- *                  valid when 'Active' is set.
- * Active:          If set, indicates that the system temperature
- *                  has crossed at least one active threshold (_ALx).
- * Passive:         If set, indicates that the system temperature
- *                  has crossed the passive threshold (_PSL).
- * Passive:         If set, indicates that the system temperature
- *                  has crossed the critical threshold (_CRT).
- */
-typedef u32			TZ_STATE;
-
-#define TZ_STATE_OK		((TZ_STATE) 0x00000000)
-#define TZ_STATE_HOT		((TZ_STATE) 0x10000000)
-#define TZ_STATE_ACTIVE		((TZ_STATE) 0x20000000)
-#define TZ_STATE_PASSIVE	((TZ_STATE) 0x40000000)
-#define TZ_STATE_CRITICAL	((TZ_STATE) 0x80000000)
-
-typedef struct {
-	u32			temperature;
-} TZ_CRITICAL_THRESHOLD;
-
-typedef struct {
-	u8			is_valid;
-	u32			temperature;
-} TZ_HOT_THRESHOLD;
-
-typedef struct {
-	u8			is_valid;
-	u32			temperature;
-	u32			tc1;
-	u32			tc2;
-	u32			tsp;
-	BM_HANDLE_LIST		devices;
-} TZ_PASSIVE_THRESHOLD;
-
-typedef struct {
-	u8			is_valid;
-	u32			temperature;
-	TZ_COOLING_STATE	cooling_state;
-	BM_HANDLE_LIST		devices;
-} TZ_ACTIVE_THRESHOLD;
-
-typedef struct {
-	TZ_CRITICAL_THRESHOLD	critical;
-	TZ_HOT_THRESHOLD	hot;
-	TZ_PASSIVE_THRESHOLD	passive;
-	TZ_ACTIVE_THRESHOLD	active[TZ_MAX_ACTIVE_THRESHOLDS];
-} TZ_THRESHOLDS;
-
-/*
- * TZ_POLICY:
- * ---------
- */
-typedef struct {
-	u32			temperature;
-	TZ_STATE		state;
-	TZ_COOLING_MODE		cooling_mode;
-	u32			polling_freq;
-	TZ_THRESHOLDS		thresholds;
-	struct timer_list	timer;
-} TZ_POLICY;
-
-
-/*
- * TZ_CONTEXT:
- * -----------
- */
-typedef struct {
-	BM_HANDLE		device_handle;
-	acpi_handle		acpi_handle;
-	char			uid[9];
-	TZ_POLICY		policy;
-} TZ_CONTEXT;
-
-
-/*****************************************************************************
- *                             Function Prototypes
- *****************************************************************************/
-
-/* tz.c */
-
-acpi_status
-tz_initialize (void);
-
-acpi_status
-tz_terminate (void);
-
-acpi_status
-tz_notify (
-	BM_NOTIFY               notify_type,
-	BM_HANDLE               device_handle,
-	BM_DRIVER_CONTEXT	*context);
-
-acpi_status
-tz_request (
-	BM_REQUEST              *request,
-	BM_DRIVER_CONTEXT	context);
-
-acpi_status
-tz_get_temperature (
-	TZ_CONTEXT		*tz);
-
-acpi_status
-tz_get_thresholds (
-	TZ_CONTEXT		*tz);
-
-acpi_status
-tz_set_cooling_preference (
-	TZ_CONTEXT              *tz,
-	TZ_COOLING_MODE         cooling_mode);
-
-void
-tz_print (
-	TZ_CONTEXT              *tz);
-
-/* tzpolicy.c */
-
-acpi_status
-tz_policy_add_device (
-	TZ_CONTEXT              *tz);
-
-acpi_status
-tz_policy_remove_device (
-	TZ_CONTEXT              *tz);
-
-void
-tz_policy_check (
-	void                    *context);
-
-/* tz_osl.c */
-
-acpi_status
-tz_osl_add_device (
-	TZ_CONTEXT		*tz);
-
-acpi_status
-tz_osl_remove_device (
-	TZ_CONTEXT		*tz);
-
-acpi_status
-tz_osl_generate_event (
-	u32			event,
-	TZ_CONTEXT		*tz);
-
-
-#endif  /* __TZ_H__ */
diff -Nru a/drivers/acpi/ospm/processor/Makefile b/drivers/acpi/ospm/processor/Makefile
--- a/drivers/acpi/ospm/processor/Makefile	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/processor/pr.c b/drivers/acpi/ospm/processor/pr.c
--- a/drivers/acpi/ospm/processor/pr.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,497 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: pr.c
- *   $Revision: 34 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include <bm.h>
-#include "pr.h"
-
-
-#define _COMPONENT		ACPI_PROCESSOR
-	MODULE_NAME		("pr")
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-extern fadt_descriptor_rev2	acpi_fadt;
-
-
-/****************************************************************************
- *                             Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    pr_print
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION: Prints out information on a specific thermal zone.
- *
- ****************************************************************************/
-
-void
-pr_print (
-	PR_CONTEXT              *processor)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer             buffer;
-
-	FUNCTION_TRACE("pr_print");
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(processor->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic processor information.
-	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Processor[%02x]:[%p] uid[%02x] %s\n", processor->device_handle, processor->acpi_handle, processor->uid, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   power: %cC0 %cC1 %cC2[%d] %cC3[%d]\n", (processor->power.state[0].is_valid?'+':'-'), (processor->power.state[1].is_valid?'+':'-'), (processor->power.state[2].is_valid?'+':'-'), processor->power.state[2].latency, (processor->power.state[3].is_valid?'+':'-'), processor->power.state[3].latency));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   performance: states[%d]\n", processor->performance.state_count));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /* ACPI_DEBUG */
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_add_device
- *
- * PARAMETERS:  <none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_add_device(
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-	PR_CONTEXT		*processor = NULL;
-	BM_DEVICE		*device = NULL;
-	acpi_buffer		buffer;
-	acpi_object		acpi_object;
-	static u32		processor_count = 0;
-
-
-	FUNCTION_TRACE("pr_add_device");
-
-	if (!context || *context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	processor = acpi_os_callocate(sizeof(PR_CONTEXT));
-	if (!processor) {
-		return AE_NO_MEMORY;
-	}
-
-	processor->device_handle = device->handle;
-	processor->acpi_handle = device->acpi_handle;
-
-	/*
-	 * Processor Block:
-	 * ----------------
-	 */
-	memset(&acpi_object, 0, sizeof(acpi_object));
-
-	buffer.length = sizeof(acpi_object);
-	buffer.pointer = &acpi_object;
-
-	status = acpi_evaluate_object(processor->acpi_handle, NULL, NULL, &buffer);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	/*
-	 * Processor ID:
-	 * -------------
-	 * TBD:  We need to synchronize the processor ID values in ACPI
-	 *       with those of the APIC.  For example, an IBM T20 has a
-	 *       proc_id value of '1', where the Linux value for the
-	 *       first CPU on this system is '0'.  Since x86 CPUs are
-	 *       mapped 1:1 we can simply use a zero-based counter.  Note
-	 *       that this assumes that processor objects are enumerated
-	 *       in the proper order.
-	 */
-	/* processor->uid = acpi_object.processor.proc_id; */
-	processor->uid = processor_count++;
-
-	processor->pblk.length = acpi_object.processor.pblk_length;
-	processor->pblk.address = acpi_object.processor.pblk_address;
-
-	status = pr_power_add_device(processor);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	status = pr_perf_add_device(processor);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	status = pr_osl_add_device(processor);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	*context = processor;
-
-	pr_print(processor);
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(processor);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_remove_device
- *
- * PARAMETERS:  <none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_remove_device (
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-	PR_CONTEXT		*processor= NULL;
-
-	FUNCTION_TRACE("pr_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	processor = (PR_CONTEXT*)(*context);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing processor device [%02x].\n", processor->device_handle));
-
-	pr_osl_remove_device(processor);
-
-	pr_perf_remove_device(processor);
-
-	pr_power_remove_device(processor);
-
-	acpi_os_free(processor);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    pr_initialize
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_initialize (void)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("pr_initialize");
-
-	memset(&criteria, 0, sizeof(BM_DEVICE_ID));
-	memset(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Initialize power (Cx state) policy.
-	 */
-	status = pr_power_initialize();
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Register driver for processor devices.
-	 */
-	criteria.type = BM_TYPE_PROCESSOR;
-
-	driver.notify = &pr_notify;
-	driver.request = &pr_request;
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_terminate
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_terminate (void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("pr_terminate");
-
-	memset(&criteria, 0, sizeof(BM_DEVICE_ID));
-	memset(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Terminate power (Cx state) policy.
-	 */
-	status = pr_power_terminate();
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Unegister driver for processor devices.
-	 */
-	criteria.type = BM_TYPE_PROCESSOR;
-
-	driver.notify = &pr_notify;
-	driver.request = &pr_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_notify
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_notify (
-	BM_NOTIFY		notify_type,
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-	PR_CONTEXT		*processor = NULL;
-
-	FUNCTION_TRACE("pr_notify");
-
-	processor = (PR_CONTEXT*)*context;
-
-	switch (notify_type) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = pr_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = pr_remove_device(context);
-		break;
-
-	case PR_NOTIFY_PERF_STATES:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Performance states change event detected on processor [%02x].\n", device_handle));
-		/* TBD: Streamline (this is simple but overkill). */
-		status = pr_perf_remove_device(processor);
-		if (ACPI_SUCCESS(status)) {
-			status = pr_perf_add_device(processor);
-		}
-		if (ACPI_SUCCESS(status)) {
-			status = pr_osl_generate_event(notify_type,
-				(processor));
-		}
-		break;
-
-	case PR_NOTIFY_POWER_STATES:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Power states change event detected on processor [%02x].\n", device_handle));
-		/* TBD: Streamline (this is simple but overkill). */
-		status = pr_power_remove_device(processor);
-		if (ACPI_SUCCESS(status)) {
-			status = pr_power_add_device(processor);
-		}
-		if (ACPI_SUCCESS(status)) {
-			status = pr_osl_generate_event(notify_type,
-				(processor));
-		}
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_request
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_request (
-	BM_REQUEST		*request,
-	void			*context)
-{
-	acpi_status		status = AE_OK;
-	PR_CONTEXT		*processor = NULL;
-
-	FUNCTION_TRACE("pr_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	processor = (PR_CONTEXT*)context;
-
-	/*
-	 * Handle request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	case PR_COMMAND_GET_POWER_INFO:
-		status = bm_copy_to_buffer(&(request->buffer),
-			&(processor->power), sizeof(PR_POWER));
-		break;
-
-	case PR_COMMAND_SET_POWER_INFO:
-	 {
-		PR_POWER *power_info = NULL;
-		u32 i = 0;
-
-		status = bm_cast_buffer(&(request->buffer),
-			(void**)&power_info, sizeof(PR_POWER));
-		if (ACPI_SUCCESS(status)) {
-			for (i=0; i<processor->power.state_count; i++) {
-				MEMCPY(&(processor->power.state[i].promotion),
-					&(power_info->state[i].promotion),
-					sizeof(PR_CX_POLICY_VALUES));
-				MEMCPY(&(processor->power.state[i].demotion),
-					&(power_info->state[i].demotion),
-					sizeof(PR_CX_POLICY_VALUES));
-			}
-		}
-	}
-		break;
-
-	case PR_COMMAND_GET_PERF_INFO:
-		status = bm_copy_to_buffer(&(request->buffer),
-			&(processor->performance), sizeof(PR_PERFORMANCE));
-		break;
-
-	case PR_COMMAND_GET_PERF_STATE:
-		status = bm_copy_to_buffer(&(request->buffer),
-			&(processor->performance.active_state), sizeof(u32));
-		break;
-
-	case PR_COMMAND_SET_PERF_LIMIT:
-	 {
-		u32 *limit = NULL;
-
-		status = bm_cast_buffer(&(request->buffer),
-			(void**)&limit, sizeof(u32));
-		if (ACPI_SUCCESS(status)) {
-			status = pr_perf_set_limit(processor, *limit);
-		}
-	}
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/processor/pr_osl.c b/drivers/acpi/ospm/processor/pr_osl.c
--- a/drivers/acpi/ospm/processor/pr_osl.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,344 +0,0 @@
-/******************************************************************************
- *
- * Module Name: pr_osl.c
- *   $Revision: 21 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <linux/pci.h>
-#include <acpi.h>
-#include <bm.h>
-#include "pr.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - IA32 Processor Driver");
-MODULE_LICENSE("GPL");
-
-
-#define PR_PROC_ROOT		"processor"
-#define PR_PROC_STATUS		"status"
-#define PR_PROC_INFO		"info"
-
-extern struct proc_dir_entry	*bm_proc_root;
-static struct proc_dir_entry	*pr_proc_root = NULL;
-extern unsigned short		acpi_piix4_bmisx;
-
-
-/****************************************************************************
- *
- * FUNCTION:	pr_osl_proc_read_status
- *
- ****************************************************************************/
-
-static int
-pr_osl_proc_read_status (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	PR_CONTEXT		*processor = NULL;
-	char			*p = page;
-	int 			len = 0;
-
-	if (!context || (off != 0)) {
-		goto end;
-	}
-
-	processor = (PR_CONTEXT*)context;
-
-	p += sprintf(p, "Bus Mastering Activity:  %08x\n",
-		processor->power.bm_activity);
-
-	p += sprintf(p, "C-State Utilization:     C1[%d] C2[%d] C3[%d]\n",
-		processor->power.state[PR_C1].utilization,
-		processor->power.state[PR_C2].utilization,
-		processor->power.state[PR_C3].utilization);
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return(len);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	pr_osl_proc_read_info
- *
- ****************************************************************************/
-
-static int
-pr_osl_proc_read_info (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	PR_CONTEXT		*processor = NULL;
-	char			*p = page;
-	int 			len = 0;
-
-	if (!context || (off != 0)) {
-		goto end;
-	}
-
-	processor = (PR_CONTEXT*)context;
-
-	p += sprintf(p, "<TBD>\n");
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return(len);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	pr_osl_add_device
- *
- ****************************************************************************/
-
-acpi_status
-pr_osl_add_device(
-	PR_CONTEXT		*processor)
-{
-	u32			i = 0;
-	struct proc_dir_entry	*proc_entry = NULL, *proc;
-	char			processor_uid[16];
-
-	if (!processor) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	printk("Processor[%x]:", processor->uid);
-	for (i=0; i<processor->power.state_count; i++) {
-		if (processor->power.state[i].is_valid) {
-			printk(" C%d", i);
-		}
-	}
-	if (processor->performance.state_count > 1)
-		printk(", %d throttling states", processor->performance.state_count);
-	if (acpi_piix4_bmisx && processor->power.state[3].is_valid)
-		printk(" (PIIX errata enabled)");
-	printk("\n");
-
-	sprintf(processor_uid, "%d", processor->uid);
-
-	proc_entry = proc_mkdir(processor_uid, pr_proc_root);
-	if (!proc_entry)
-		return(AE_ERROR);
-
-	proc = create_proc_read_entry(PR_PROC_STATUS, S_IFREG | S_IRUGO, 
-				      proc_entry, pr_osl_proc_read_status, (void*)processor);
-	if (!proc_entry)
-		return(AE_ERROR);
-
-	proc = create_proc_read_entry(PR_PROC_INFO, S_IFREG | S_IRUGO, 
-				      proc_entry, pr_osl_proc_read_info, (void*)processor);
-	if (!proc_entry)
-		return(AE_ERROR);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	pr_osl_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-pr_osl_remove_device (
-	PR_CONTEXT		*processor)
-{
-	char			proc_entry[64];
-
-	if (!processor) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	sprintf(proc_entry, "%d/%s", processor->uid, PR_PROC_INFO);
-	remove_proc_entry(proc_entry, pr_proc_root);
-
-	sprintf(proc_entry, "%d/%s", processor->uid, PR_PROC_STATUS);
-	remove_proc_entry(proc_entry, pr_proc_root);
-
-	sprintf(proc_entry, "%d", processor->uid);
-	remove_proc_entry(proc_entry, pr_proc_root);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	pr_osl_generate_event
- *
- ****************************************************************************/
-
-acpi_status
-pr_osl_generate_event (
-	u32			event,
-	PR_CONTEXT		*processor)
-{
-	acpi_status		status = AE_OK;
-	char			processor_uid[16];
-
-	if (!processor) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (event) {
-
-	case PR_NOTIFY_PERF_STATES:
-	case PR_NOTIFY_POWER_STATES:
-		sprintf(processor_uid, "%d", processor->uid);
-		status = bm_osl_generate_event(processor->device_handle,
-			PR_PROC_ROOT, processor_uid, event, 0);
-		break;
-
-	default:
-		return(AE_BAD_PARAMETER);
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *                              Errata Handling
- ****************************************************************************/
-
-void acpi_pr_errata (void)
-{
-	struct pci_dev		*dev = NULL;
-
-	while ((dev = pci_find_subsys(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 
-		PCI_ANY_ID, PCI_ANY_ID, dev))) {
-		switch (dev->device) {
-		case PCI_DEVICE_ID_INTEL_82801BA_8:	/* PIIX4U4 */
-		case PCI_DEVICE_ID_INTEL_82801BA_9:	/* PIIX4U3 */
-		case PCI_DEVICE_ID_INTEL_82451NX:	/* PIIX4NX */
-		case PCI_DEVICE_ID_INTEL_82372FB_1:	/* PIIX4U2 */
-		case PCI_DEVICE_ID_INTEL_82801AA_1:	/* PIIX4U */
-		case PCI_DEVICE_ID_INTEL_82443MX_1:	/* PIIX4E2 */
-		case PCI_DEVICE_ID_INTEL_82801AB_1:	/* PIIX4E */
-		case PCI_DEVICE_ID_INTEL_82371AB:	/* PIIX4 */
-			acpi_piix4_bmisx = pci_resource_start(dev, 4);
-			return;
-		}
-	}
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	pr_osl_init
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	0: Success
- *
- * DESCRIPTION: Module initialization.
- *
- ****************************************************************************/
-
-static int __init
-pr_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	/* abort if no busmgr */
-	if (!bm_proc_root)
-		return -ENODEV;
-
-	acpi_pr_errata();
-
-	pr_proc_root = proc_mkdir(PR_PROC_ROOT, bm_proc_root);
-	if (!pr_proc_root) {
-		status = AE_ERROR;
-	}
-	else {
-		status = pr_initialize();
-		if (ACPI_FAILURE(status)) {
-			remove_proc_entry(PR_PROC_ROOT, bm_proc_root);
-		}
-
-	}
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_osl_cleanup
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	<none>
- *
- * DESCRIPTION: Module cleanup.
- *
- ****************************************************************************/
-
-static void __exit
-pr_osl_cleanup (void)
-{
-	pr_terminate();
-
-	if (pr_proc_root) {
-		remove_proc_entry(PR_PROC_ROOT, bm_proc_root);
-	}
-
-	return;
-}
-
-
-module_init(pr_osl_init);
-module_exit(pr_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/processor/prperf.c b/drivers/acpi/ospm/processor/prperf.c
--- a/drivers/acpi/ospm/processor/prperf.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,456 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: prperf.c
- *              $Revision: 21 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * TBD: 1. Support ACPI 2.0 processor performance states (not just throttling).
- *      2. Fully implement thermal -vs- power management limit control.
- */
-
-
-#include <acpi.h>
-#include <bm.h>
-#include "pr.h"
-
-#define _COMPONENT		ACPI_PROCESSOR
-	MODULE_NAME		("prperf")
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-extern fadt_descriptor_rev2	acpi_fadt;
-const u32			POWER_OF_2[] = {1,2,4,8,16,32,64,128,256,512};
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_perf_get_frequency
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_perf_get_frequency (
-	PR_CONTEXT		*processor,
-	u32			*frequency) {
-	acpi_status		status = AE_OK;
-
-	FUNCTION_TRACE("pr_perf_get_frequency");
-
-	if (!processor || !frequency) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/* TBD: Generic method to calculate processor frequency. */
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_perf_get_state
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-/* TBD:	Include support for _real_ performance states (not just throttling). */
-
-acpi_status
-pr_perf_get_state (
-	PR_CONTEXT              *processor,
-	u32                     *state)
-{
-	u32                     pblk_value = 0;
-	u32                     duty_mask = 0;
-	u32                     duty_cycle = 0;
-
-	FUNCTION_TRACE("pr_perf_get_state");
-
-	if (!processor || !state) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (processor->performance.state_count == 1) {
-		*state = 0;
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	acpi_os_read_port(processor->pblk.address, &pblk_value, 32);
-
-	/*
-	 * Throttling Enabled?
-	 * -------------------
-	 * If so, calculate the current throttling state, otherwise return
-	 * '100% performance' (state 0).
-	 */
-	if (pblk_value & 0x00000010) {
-
-		duty_mask = processor->performance.state_count - 1;
-		duty_mask <<= acpi_fadt.duty_offset;
-
-		duty_cycle = pblk_value & duty_mask;
-		duty_cycle >>= acpi_fadt.duty_offset;
-
-		if (duty_cycle == 0) {
-			*state = 0;
-		}
-		else {
-			*state = processor->performance.state_count -
-				duty_cycle;
-		}
-	}
-	else {
-		*state = 0;
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Processor [%02x] is at performance state [%d%%].\n", processor->device_handle, processor->performance.state[*state].performance));
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_perf_set_state
- *
- * PARAMETERS:
- *
- * RETURN:      AE_OK
- *              AE_BAD_PARAMETER
- *              AE_BAD_DATA         Invalid target throttling state.
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-/* TBD: Includes support for _real_ performance states (not just throttling). */
-
-acpi_status
-pr_perf_set_state (
-	PR_CONTEXT              *processor,
-	u32                     state)
-{
-	u32                     pblk_value = 0;
-	u32                     duty_mask = 0;
-	u32                     duty_cycle = 0;
-	u32                     i = 0;
-
-	FUNCTION_TRACE ("pr_perf_set_state");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (state > (processor->performance.state_count - 1)) {
-		return_ACPI_STATUS(AE_BAD_DATA);
-	}
-
-	if ((state == processor->performance.active_state) ||
-		(processor->performance.state_count == 1)) {
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	/*
-	 * Calculate Duty Cycle/Mask:
-	 * --------------------------
-	 * Note that we don't support duty_cycle values that span bit 4.
-	 */
-	if (state) {
-		duty_cycle = processor->performance.state_count - state;
-		duty_cycle <<= acpi_fadt.duty_offset;
-	}
-	else {
-		duty_cycle = 0;
-	}
-
-	duty_mask = ~((u32)(processor->performance.state_count - 1));
-	for (i=0; i<acpi_fadt.duty_offset; i++) {
-		duty_mask <<= acpi_fadt.duty_offset;
-		duty_mask += 1;
-	}
-
-	/*
-	 * Disable Throttling:
-	 * -------------------
-	 * Got to turn it off before you can change the duty_cycle value.
-	 * Throttling is disabled by writing a 0 to bit 4.
-	 */
-	acpi_os_read_port(processor->pblk.address, &pblk_value, 32);
-	if (pblk_value & 0x00000010) {
-		pblk_value &= 0xFFFFFFEF;
-		acpi_os_write_port(processor->pblk.address, pblk_value, 32);
-	}
-
-	/*
-	 * Set Duty Cycle:
-	 * ---------------
-	 * Mask off the old duty_cycle value, mask in the new.
-	 */
-	pblk_value &= duty_mask;
-	pblk_value |= duty_cycle;
-	acpi_os_write_port(processor->pblk.address, pblk_value, 32);
-
-	/*
-	 * Enable Throttling:
-	 * ------------------
-	 * But only for non-zero (non-100% performance) states.
-	 */
-	if (state) {
-		pblk_value |= 0x00000010;
-		acpi_os_write_port(processor->pblk.address, pblk_value, 32);
-	}
-
-	processor->performance.active_state = state;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Processor [%02x] set to performance state [%d%%].\n", processor->device_handle, processor->performance.state[state].performance));
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_perf_set_limit
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_perf_set_limit (
-	PR_CONTEXT              *processor,
-	u32                     limit)
-{
-	acpi_status		status = AE_OK;
-	PR_PERFORMANCE		*performance = NULL;
-
-	FUNCTION_TRACE ("pr_perf_set_limit");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	performance = &(processor->performance);
-
-	/*
-	 * Set Limit:
-	 * ----------
-	 * TBD:  Properly manage thermal and power limits (only set
-	 *	 performance state iff...).
-	 */
-	switch (limit) {
-
-	case PR_PERF_DEC:
-		if (performance->active_state <
-			(performance->state_count-1)) {
-			status = pr_perf_set_state(processor,
-				(performance->active_state+1));
-		}
-		break;
-
-	case PR_PERF_INC:
-		if (performance->active_state > 0) {
-			status = pr_perf_set_state(processor,
-				(performance->active_state-1));
-		}
-		break;
-
-	case PR_PERF_MAX:
-		if (performance->active_state != 0) {
-			status = pr_perf_set_state(processor, 0);
-		}
-		break;
-
-	default:
-		return_ACPI_STATUS(AE_BAD_DATA);
-		break;
-	}
-
-	if (ACPI_SUCCESS(status)) {
-		performance->thermal_limit = performance->active_state;
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Processor [%02x] thermal performance limit set to [%d%%].\n", processor->device_handle, processor->performance.state[performance->active_state].performance));
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    pr_perf_add_device
- *
- * PARAMETERS:  processor		Our processor-specific context.
- *
- * RETURN:      AE_OK
- *              AE_BAD_PARAMETER
- *
- * DESCRIPTION: Calculates the number of throttling states and the state
- *              performance/power values.
- *
- ****************************************************************************/
-
-/* TBD: Support duty_cycle values that span bit 4. */
-
-acpi_status
-pr_perf_add_device (
-	PR_CONTEXT              *processor)
-{
-	acpi_status             status = AE_OK;
-	u32                     i = 0;
-	u32                     performance_step = 0;
-	u32                     percentage = 0;
-
-	FUNCTION_TRACE("pr_perf_add_device");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Valid PBLK?
-	 * -----------
-	 * For SMP it is common to have the first (boot) processor have a
-	 * valid PBLK while all others do not -- which implies that
-	 * throttling has system-wide effects (duty_cycle programmed into
-	 * the chipset effects all processors).
-	 */
-	if ((processor->pblk.length < 6) || !processor->pblk.address) {
-		processor->performance.state_count = 1;
-	}
-
-	/*
-	 * Valid Duty Offset/Width?
-	 * ------------------------
-	 * We currently only support duty_cycle values that fall within
-	 * bits 0-3, as things get complicated when this value spans bit 4
-	 * (the throttling enable/disable bit).
-	 */
-	else if ((acpi_fadt.duty_offset + acpi_fadt.duty_width) > 4) {
-		processor->performance.state_count = 1;
-	}
-
-	/*
-	 * Compute State Count:
-	 * --------------------
-	 * The number of throttling states is computed as 2^duty_width,
-	 * but limited by PR_MAX_THROTTLE_STATES.  Note that a duty_width
-	 * of zero results is one throttling state (100%).
-	 */
-	else {
-		processor->performance.state_count =
-			POWER_OF_2[acpi_fadt.duty_width];
-	}
-
-	if (processor->performance.state_count > PR_MAX_THROTTLE_STATES) {
-		processor->performance.state_count = PR_MAX_THROTTLE_STATES;
-	}
-
-	/*
-	 * Compute State Values:
-	 * ---------------------
-	 * Note that clock throttling displays a linear power/performance
-	 * relationship (at 50% performance the CPU will consume 50% power).
-	 */
-	performance_step = (1000 / processor->performance.state_count);
-
-	for (i=0; i<processor->performance.state_count; i++) {
-		percentage = (1000 - (performance_step * i))/10;
-		processor->performance.state[i].performance = percentage;
-		processor->performance.state[i].power = percentage;
-	}
-
-	/*
-	 * Get Current State:
-	 * ------------------
-	 */
-	status = pr_perf_get_state(processor, &(processor->performance.active_state));
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Set to Maximum Performance:
-	 * ---------------------------
-	 * We'll let subsequent policy (e.g. thermal/power) decide to lower
-	 * performance if it so chooses, but for now crank up the speed.
-	 */
-	if (0 != processor->performance.active_state) {
-		status = pr_perf_set_state(processor, 0);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_perf_remove_device
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_perf_remove_device (
-	PR_CONTEXT              *processor)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("pr_perf_remove_device");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&(processor->performance), 0, sizeof(PR_PERFORMANCE));
-
-	return_ACPI_STATUS(status);
-}
-
diff -Nru a/drivers/acpi/ospm/processor/prpower.c b/drivers/acpi/ospm/processor/prpower.c
--- a/drivers/acpi/ospm/processor/prpower.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,665 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: prpower.c
- *   $Revision: 32 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-/* TBD: Linux specific */
-#include <linux/sched.h>
-#include <linux/pm.h>
-#include <asm/io.h>
-
-#include <acpi.h>
-#include <bm.h>
-#include "pr.h"
-
-#define _COMPONENT		ACPI_PROCESSOR
-	MODULE_NAME		("prpower")
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-extern FADT_DESCRIPTOR		acpi_fadt;
-static u32			last_idle_jiffies = 0;
-static PR_CONTEXT		*processor_list[NR_CPUS];
-static void			(*pr_pm_idle_save)(void) = NULL;
-static u8			bm_control = 0;
-
-
-/* Used for PIIX4 errata handling. */
-unsigned short			acpi_piix4_bmisx = 0;
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    pr_power_activate_state
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-pr_power_activate_state (
-	PR_CONTEXT		*processor,
-	u32			next_state)
-{
-
-	PROC_NAME("pr_power_activate_state");
-
-	if (!processor) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
-		return;
-	}
-
-	processor->power.state[processor->power.active_state].promotion.count = 0;
-	processor->power.state[processor->power.active_state].demotion.count = 0;
-
-	/*
-	 * Cleanup from old state.
-	 */
-	switch (processor->power.active_state) {
-
-	case PR_C3:
-		/* Disable bus master reload */
-		acpi_hw_register_bit_access(ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK,
-			BM_RLD, 0);
-		break;
-	}
-
-	/*
-	 * Prepare to use new state.
-	 */
-	switch (next_state) {
-
-	case PR_C3:
-		/* Enable bus master reload */
-		acpi_hw_register_bit_access(ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK,
-			BM_RLD, 1);
-		break;
-	}
-
-	processor->power.active_state = next_state;
-	
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_power_idle
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-void
-pr_power_idle (void)
-{
-	PR_CX			*c_state = NULL;
-	u32			next_state = 0;
-	u32			start_ticks, end_ticks, time_elapsed;
-	PR_CONTEXT		*processor = NULL;
-
-	PROC_NAME("pr_power_idle");
-
-	processor = processor_list[smp_processor_id()];
-
-	if (!processor || processor->power.active_state == PR_C0) {
-		return;
-	}
-
-	next_state = processor->power.active_state;
-
-	/*
-	 * Check OS Idleness:
-	 * ------------------
-	 * If the OS has been busy (hasn't called the idle handler in a while)
-	 * then automatically demote to the default power state (e.g. C1).
-	 *
-	 * TBD: Optimize by having scheduler determine business instead
-	 *      of having us try to calculate it.
-	 */
-	if (processor->power.active_state != processor->power.default_state) {
-		if ((jiffies - last_idle_jiffies) >= processor->power.busy_metric) {
-			next_state = processor->power.default_state;
-			if (next_state != processor->power.active_state) {
-				pr_power_activate_state(processor, next_state);
-			}
-		}
-	}
-
-	disable();
-
-	/*
-	 * Log BM Activity:
-	 * ----------------
-	 * Read BM_STS and record its value for later use by C3 policy.
-	 * (Note that we save the BM_STS values for the last 32 cycles).
-	 */
-	if (bm_control) {
-		processor->power.bm_activity <<= 1;
-		if (acpi_hw_register_bit_access(ACPI_READ, ACPI_MTX_DO_NOT_LOCK, BM_STS)) {
-			processor->power.bm_activity |= 1;
-			acpi_hw_register_bit_access(ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK,
-				BM_STS, 1);
-		}
-		else if (acpi_piix4_bmisx) {
-			/*
-			 * PIIX4 Errata:
-			 * -------------
-			 * This code is a workaround for errata #18 "C3 Power State/
-			 * BMIDE and Type-F DMA Livelock" from the July '01 PIIX4
-			 * specification update.  Note that BM_STS doesn't always
-			 * reflect the true state of bus mastering activity; forcing
-			 * us to manually check the BMIDEA bit of each IDE channel.
-			 */
-			if ((inb_p(acpi_piix4_bmisx + 0x02) & 0x01) ||
-				(inb_p(acpi_piix4_bmisx + 0x0A) & 0x01))
-				processor->power.bm_activity |= 1;
-		}
-	}
-
-	c_state = &(processor->power.state[processor->power.active_state]);
-
-	c_state->utilization++;
-
-	/*
-	 * Sleep:
-	 * ------
-	 * Invoke the current Cx state to put the processor to sleep.
-	 */
-	switch (processor->power.active_state) {
-
-	case PR_C1:
-		/* Invoke C1 */
-		enable(); halt();
-		/*
-	 * TBD: Can't get time duration while in C1, as resumes
-		 *      go to an ISR rather than here.
-		 */
-		time_elapsed = 0xFFFFFFFF;
-		break;
-
-	case PR_C2:
-		/* See how long we're asleep for */
-		acpi_get_timer(&start_ticks);
-		/* Invoke C2 */
-		acpi_os_read_port(processor->power.p_lvl2, NULL, 8);
-		/* Dummy op - must do something useless after P_LVL2 read */
-		acpi_hw_register_bit_access(ACPI_READ, ACPI_MTX_DO_NOT_LOCK, BM_STS);
-		/* Compute time elapsed */
-		acpi_get_timer(&end_ticks);
-		/* Re-enable interrupts */
-		enable();
-		acpi_get_timer_duration(start_ticks, end_ticks, &time_elapsed);
-		break;
-
-	case PR_C3:
-		/* Disable bus master arbitration */
-		acpi_hw_register_bit_access(ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK, ARB_DIS, 1);
-		/* See how long we're asleep for */
-		acpi_get_timer(&start_ticks);
-		/* Invoke C3 */
-		acpi_os_read_port(processor->power.p_lvl3, NULL, 8);
-		/* Dummy op - must do something useless after P_LVL3 read */
-		acpi_hw_register_bit_access(ACPI_READ, ACPI_MTX_DO_NOT_LOCK, BM_STS);
-		/* Compute time elapsed */
-		acpi_get_timer(&end_ticks);
-		/* Enable bus master arbitration */
-		acpi_hw_register_bit_access(ACPI_WRITE, ACPI_MTX_DO_NOT_LOCK,
-			ARB_DIS, 0);
-		/* Re-enable interrupts */
-		enable();
-		acpi_get_timer_duration(start_ticks, end_ticks, &time_elapsed);
-		break;
-
-	default:
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Attempt to use unsupported power state C%d.\n", processor->power.active_state));
-		enable();
-		break;
-	}
-
-	/*
-	 * Promotion?
-	 * ----------
-	 * Track the number of successful sleeps (time asleep is greater
-	 * than time_threshold) and promote when count_threshold is
-	 * reached.
-	 */
-	if ((c_state->promotion.target_state) && 	
-		(time_elapsed >= c_state->promotion.time_threshold)) {
-
-		c_state->promotion.count++;
- 		c_state->demotion.count = 0;
-
-		if (c_state->promotion.count >= c_state->promotion.count_threshold) {
-			/*
-			 * Bus Mastering Activity, if active and used
-			 * by this state's promotion policy, prevents
-			 * promotions from occuring.
-			 */
-			if (!bm_control || !(processor->power.bm_activity & c_state->promotion.bm_threshold))
-				next_state = c_state->promotion.target_state;
-		}
-	}
-
-	/*
-	 * Demotion?
-	 * ---------
-	 * Track the number of shorts (time asleep is less than
-	 * time_threshold) and demote when count_threshold is reached.
-	 */
-	if (c_state->demotion.target_state) {
-			
-		if (time_elapsed < c_state->demotion.time_threshold) {
-
-			c_state->demotion.count++;
-			c_state->promotion.count = 0;
-
-			if (c_state->demotion.count >=
-				c_state->demotion.count_threshold) {
-				next_state = c_state->demotion.target_state;
-			}
-		}
-
-		/*
-		 * Bus Mastering Activity, if active and used by this
-		 * state's promotion policy, causes an immediate demotion
-		 * to occur.
-		 */
-		if (bm_control && (processor->power.bm_activity & c_state->demotion.bm_threshold))
-			next_state = c_state->demotion.target_state;
-	}
-
-	/*
-	 * New Cx State?
-	 * -------------
-	 * If we're going to start using a new Cx state we must clean up
-	 * from the previous and prepare to use the new.
-	 */
-	if (next_state != processor->power.active_state) {
-		pr_power_activate_state(processor, next_state);
-		processor->power.active_state = processor->power.active_state;
-	}
-
-	/*
-	 * Track OS Idleness:
-	 * ------------------
-	 * Record a jiffies timestamp to compute time elapsed between calls
-	 * to the idle handler.
-	 */
-	last_idle_jiffies = jiffies;
-
-	return;
-}
-
-
-/*****************************************************************************
- *
- * FUNCTION:    pr_power_set_default_policy
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION: Sets the default Cx state policy (OS idle handler).  Our
- *              scheme is to promote quickly to C2 but more conservatively
- *              to C3.  We're favoring C2 for its characteristics of low
- *              latency (quick response), good power savings, and ability
- *              to allow bus mastering activity.
- *
- *              Note that Cx state policy is completely customizable, with
- *              the goal of having heuristics to alter policy dynamically.
- *
- ****************************************************************************/
-
-acpi_status
-pr_power_set_default_policy (
-	PR_CONTEXT                 *processor)
-{
-	FUNCTION_TRACE("pr_power_set_default_policy");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Busy Metric:
-	 * ------------
-	 * Used to determine when the OS has been busy and thus when
-	 * policy should return to using the default Cx state (e.g. C1).
-	 * On Linux we use the number of jiffies (scheduler quantums)
-	 * that transpire between calls to the idle handler.
-	 *
-	 * TBD: Linux-specific.
-	 */
-	processor->power.busy_metric = 2;
-
-	/*
-	 * C1:
-	 * ---
-	 * C1 serves as our default state.  It must be valid.
-	 */
-	if (processor->power.state[PR_C1].is_valid) {
-		processor->power.active_state =
-			processor->power.default_state = PR_C1;
-	}
-	else {
-		processor->power.active_state =
-			processor->power.default_state = PR_C0;
-		return_ACPI_STATUS(AE_OK);
-	}
-
-	/*
-	 * C2:
-	 * ---
-	 * Set default C1 promotion and C2 demotion policies.
-	 */
-	if (processor->power.state[PR_C2].is_valid) {
-		/*
-		 * Promote from C1 to C2 anytime we're asleep in C1 for
-		 * longer than two times the C2 latency (to amortize cost
-		 * of transition).  Demote from C2 to C1 anytime we're
-		 * asleep in C2 for less than this time.
-		 */
-		processor->power.state[PR_C1].promotion.count_threshold = 10;
-		processor->power.state[PR_C1].promotion.time_threshold =
-			2 * processor->power.state[PR_C2].latency;
-		processor->power.state[PR_C1].promotion.target_state = PR_C2;
-
-		processor->power.state[PR_C2].demotion.count_threshold = 1;
-		processor->power.state[PR_C2].demotion.time_threshold =
-			2 * processor->power.state[PR_C2].latency;
-		processor->power.state[PR_C2].demotion.target_state = PR_C1;
-	}
-
-	/*
-	 * C3:
-	 * ---
-	 * Set default C2 promotion and C3 demotion policies.
-	 */
-	if ((processor->power.state[PR_C2].is_valid) &&
-		(processor->power.state[PR_C3].is_valid)) {
-		/*
-		 * Promote from C2 to C3 after 4 cycles of no bus
-		 * mastering activity (while maintaining sleep time
-		 * criteria).  Demote immediately on a short or
-		 * whenever bus mastering activity occurs.
-		 */
-		processor->power.state[PR_C2].promotion.count_threshold = 1;
-		processor->power.state[PR_C2].promotion.time_threshold =
-			2 * processor->power.state[PR_C3].latency;
-		processor->power.state[PR_C2].promotion.bm_threshold =
-			0x0000000F;
-		processor->power.state[PR_C2].promotion.target_state =
-			PR_C3;
-
-		processor->power.state[PR_C3].demotion.count_threshold = 1;
-		processor->power.state[PR_C3].demotion.time_threshold =
-			2 * processor->power.state[PR_C3].latency;
-		processor->power.state[PR_C3].demotion.bm_threshold =
-			0x0000000F;
-		processor->power.state[PR_C3].demotion.target_state =
-			PR_C2;
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-/*****************************************************************************
- *
- * FUNCTION:    pr_power_add_device
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-/*
- * TBD: 1. PROC_C1 support.
- *      2. Symmetric Cx state support (different Cx states supported
- *         by different CPUs results in lowest common denominator).
- */
-
-acpi_status
-pr_power_add_device (
-	PR_CONTEXT                 *processor)
-{
-	FUNCTION_TRACE("pr_power_add_device");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * State Count:
-	 * ------------
-	 * Fixed at four (C0-C3).  We use is_valid to determine whether or
-	 * not a state actually gets used.
-	 */
-	processor->power.state_count = PR_MAX_POWER_STATES;
-
-	/*
-	 * C0:
-	 * ---
-	 * C0 exists only as filler in our array. (Let's assume its valid!)
-	 */
-	processor->power.state[PR_C0].is_valid = TRUE;
-
-	/*
-	 * C1:
-	 * ---
-	 * ACPI states that C1 must be supported by all processors
-	 * with a latency so small that it can be ignored.
-	 *
-	 * TBD: What about PROC_C1 support?
-	 */
-	processor->power.state[PR_C1].is_valid = TRUE;
-
-	/*
-	 * C2:
-	 * ---
-	 * We're only supporting C2 on UP systems with latencies <= 100us.
-	 *
-	 * TBD: Support for C2 on MP (P_LVL2_UP) -- I'm taking the
-	 *      conservative approach for now.
-	 */
-	processor->power.state[PR_C2].latency = acpi_fadt.plvl2_lat;
-
-#ifdef CONFIG_SMP
-	if (smp_num_cpus == 1) {
-#endif /*CONFIG_SMP*/
-		if (acpi_fadt.plvl2_lat <= PR_MAX_C2_LATENCY) {
-			processor->power.state[PR_C2].is_valid = TRUE;
-			processor->power.p_lvl2 = processor->pblk.address + 4;
-		}
-#ifdef CONFIG_SMP
-	}
-#endif /*CONFIG_SMP*/
-
-
-	/*
-	 * C3:
-	 * ---
-	 * We're only supporting C3 on UP systems with latencies <= 1000us,
-	 * and that include the ability to disable bus mastering while in
-	 * C3 (ARB_DIS) but allows bus mastering requests to wake the system
-	 * from C3 (BM_RLD).  Note his method of maintaining cache coherency
-	 * (disabling of bus mastering) cannot be used on SMP systems, and
-	 * flushing caches (e.g. WBINVD) is simply too costly at this time.
-	 *
-	 * TBD: Support for C3 on MP -- I'm taking the conservative
-	 *      approach for now.
-	 */
-	processor->power.state[PR_C3].latency = acpi_fadt.plvl3_lat;
-
-#ifdef CONFIG_SMP
-	if (smp_num_cpus == 1) {
-#endif /*CONFIG_SMP*/
-		if ((acpi_fadt.plvl3_lat <= PR_MAX_C3_LATENCY) && bm_control) {
-			processor->power.state[PR_C3].is_valid = TRUE;
-			processor->power.p_lvl3 = processor->pblk.address + 5;
-		}
-#ifdef CONFIG_SMP
-	}
-#endif /*CONFIG_SMP*/
-
-	/*
-	 * Set Default Policy:
-	 * -------------------
-	 * Now that we know which state are supported, set the default
-	 * policy.  Note that this policy can be changed dynamically
-	 * (e.g. encourage deeper sleeps to conserve battery life when
-	 * not on AC).
-	 */
-	pr_power_set_default_policy(processor);
-
-	/*
-	 * Save Processor Context:
-	 * -----------------------
-	 * TBD: Enhance Linux idle handler to take processor context
-	 *      parameter.
-	 */
-	processor_list[processor->uid] = processor;
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_power_remove_device
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_power_remove_device (
-	PR_CONTEXT              *processor)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("pr_power_remove_device");
-
-	if (!processor) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	MEMSET(&(processor->power), 0, sizeof(PR_POWER));
-
-	processor_list[processor->uid] = NULL;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_power_initialize
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_power_initialize (void)
-{
-	u32			i = 0;
-
-	FUNCTION_TRACE("pr_power_initialize");
-
-	/* TBD: Linux-specific. */
-	for (i=0; i<NR_CPUS; i++) {
-		processor_list[i] = NULL;
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Max CPUs[%d], this CPU[%d].\n", NR_CPUS, smp_processor_id()));
-
-	/* Only use C3 if we can control bus mastering. */
-	if (acpi_fadt.V1_pm2_cnt_blk && acpi_fadt.pm2_cnt_len)
-		bm_control = 1;
-
-	/*
-	 * Install idle handler.
-	 *
-	 * TBD: Linux-specific (need OSL function).
-	 */
-	pr_pm_idle_save = pm_idle;
-	pm_idle = pr_power_idle;
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    pr_power_terminate
- *
- * PARAMETERS:  <none>
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-pr_power_terminate (void)
-{
-	FUNCTION_TRACE("pr_power_terminate");
-
-	/*
-	 * Remove idle handler.
-	 *
-	 * TBD: Linux-specific (need OSL function).
-	 */
-	pm_idle = pr_pm_idle_save;
-
-	return_ACPI_STATUS(AE_OK);
-}
diff -Nru a/drivers/acpi/ospm/system/Makefile b/drivers/acpi/ospm/system/Makefile
--- a/drivers/acpi/ospm/system/Makefile	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/system/sm.c b/drivers/acpi/ospm/system/sm.c
--- a/drivers/acpi/ospm/system/sm.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,373 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: sm.c
- *   $Revision: 20 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <acpi.h>
-#include "sm.h"
-
-
-#define _COMPONENT		ACPI_SYSTEM
-	MODULE_NAME 		("sm")
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:	sm_print
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION: Prints out information on a specific system.
- *
- ****************************************************************************/
-
-void
-sm_print (
-	SM_CONTEXT		*system)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer		buffer;
-
-	PROC_NAME("sm_print");
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer) {
-		return;
-	}
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(system->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic system information.
-	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| System[%02x]:[%p] %s\n", system->device_handle, system->acpi_handle, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   states: %cS0 %cS1 %cS2 %cS3 %cS4 %cS5\n", (system->states[0]?'+':'-'), (system->states[1]?'+':'-'), (system->states[2]?'+':'-'), (system->states[3]?'+':'-'), (system->states[4]?'+':'-'), (system->states[5]?'+':'-')));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_add_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-sm_add_device(
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-	BM_DEVICE		*device = NULL;
-	SM_CONTEXT		*system = NULL;
-	u8			i, type_a, type_b;
-
-
-	FUNCTION_TRACE("sm_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding system device [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context."));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Allocate a new SM_CONTEXT structure.
-	 */
-	system = acpi_os_callocate(sizeof(SM_CONTEXT));
-	if (!system) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	system->device_handle = device->handle;
-	system->acpi_handle = device->acpi_handle;
-
-	/*
-	 * Sx States:
-	 * ----------
-	 * Figure out which Sx states are supported.
-	 */
-	for (i=0; i<SM_MAX_SYSTEM_STATES; i++) {
-		if (ACPI_SUCCESS(acpi_hw_obtain_sleep_type_register_data(
-			i,
-			&type_a,
-			&type_b))) {
-			system->states[i] = TRUE;
-		}
-	}
-
-	status = sm_osl_add_device(system);
-	if (ACPI_FAILURE(status)) {
-		goto end;
-	}
-
-	*context = system;
-
-	sm_print(system);
-
-end:
-	if (ACPI_FAILURE(status)) {
-		acpi_os_free(system);
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_remove_device
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-sm_remove_device (
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-	SM_CONTEXT		*system = NULL;
-
-	FUNCTION_TRACE("sm_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	system = (SM_CONTEXT*)*context;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing system device [%02x].\n", system->device_handle));
-
-	status = sm_osl_remove_device(system);
-
-	acpi_os_free(system);
-
-	*context = NULL;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                             External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:	sm_initialize
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-sm_initialize (void)
-{
-	acpi_status		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("sm_initialize");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Register driver for the System device.
-	 */
-	criteria.type = BM_TYPE_SYSTEM;
-
-	driver.notify = &sm_notify;
-	driver.request = &sm_request;
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_terminate
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-sm_terminate (void)
-{
-	acpi_status 		status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("sm_terminate");
-
-	MEMSET(&criteria, 0, sizeof(BM_DEVICE_ID));
-	MEMSET(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Unregister driver for System devices.
-	 */
-	criteria.type = BM_TYPE_SYSTEM;
-
-	driver.notify = &sm_notify;
-	driver.request = &sm_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/*****************************************************************************
- *
- * FUNCTION:	sm_notify
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-acpi_status
-sm_notify (
-	BM_NOTIFY		notify_type,
-	BM_HANDLE		device_handle,
-	void			**context)
-{
-	acpi_status 		status = AE_OK;
-
-	FUNCTION_TRACE("sm_notify");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	switch (notify_type) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = sm_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = sm_remove_device(context);
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_request
- *
- * PARAMETERS:	
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-sm_request (
-	BM_REQUEST		*request,
-	void			*context)
-{
-	acpi_status 		status = AE_OK;
-
-	FUNCTION_TRACE("sm_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Handle Request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/system/sm_osl.c b/drivers/acpi/ospm/system/sm_osl.c
--- a/drivers/acpi/ospm/system/sm_osl.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,919 +0,0 @@
-/******************************************************************************
- *
- * Module Name: sm_osl.c
- *   $Revision: 16 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <linux/pm.h>
-#include <asm/uaccess.h>
-#include <linux/acpi.h>
-#include <asm/io.h>
-#include <linux/mc146818rtc.h>
-#include <linux/delay.h>
-
-#include <acpi.h>
-#include "sm.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - ACPI System Driver");
-MODULE_LICENSE("GPL");
-
-
-#define SM_PROC_INFO		"info"
-#define SM_PROC_DSDT		"dsdt"
-
-extern struct proc_dir_entry	*bm_proc_root;
-struct proc_dir_entry		*sm_proc_root = NULL;
-static void 			(*sm_pm_power_off)(void) = NULL;
-
-static ssize_t sm_osl_read_dsdt(struct file *, char *, size_t, loff_t *);
-
-static struct file_operations proc_dsdt_operations = {
-	read:		sm_osl_read_dsdt,
-};
-
-static acpi_status sm_osl_suspend(u32 state);
-
-struct proc_dir_entry *bm_proc_sleep;
-struct proc_dir_entry *bm_proc_alarm;
-struct proc_dir_entry *bm_proc_gpe;
-
-static int
-sm_osl_proc_read_sleep (
-        char                    *page,
-        char                    **start,
-        off_t                   off,
-        int                     count,
-        int                     *eof,
-        void                    *context)
-{
-	SM_CONTEXT    *system = (SM_CONTEXT*) context;
-	char          *str = page;
-	int           len;
-	int           i;
-
-	if (!system)
-               goto end;
-
-	if (off != 0)
-               goto end;
-
-	for (i = 0; i <= ACPI_S5; i++) {
-		if (system->states[i])
-			str += sprintf(str,"S%d ", i);
-	}
-
-	str += sprintf(str, "\n");
-
-end:
-
-	len = (str - page);
-	if (len < (off + count))
-		*eof = 1;
-
-	*start = page + off;
-	len -= off;
-
-	if (len > count)
-		len = count;
-
-	if (len < 0)
-		len = 0;
-
-	return (len);
-}
-
-int sm_osl_proc_write_sleep (struct file *file,
-			     const char *buffer,
-			     unsigned long count,
-			     void *data)
-{
-	SM_CONTEXT    *system = (SM_CONTEXT*) data;
-	char          str[10];
-	char          *strend;
-	unsigned long value;
-	
-	if (count > (sizeof(str) - 1))
-		return -EINVAL;
-	
-	if (copy_from_user(str,buffer,count))
-		return -EFAULT;
-	
-	str[count] = '\0';
-	
-	value = simple_strtoul(str,&strend,0);
-	if (str == strend)
-		return -EINVAL;
-	
-	if (value == 0 || value >= ACPI_S5)
-		return -EINVAL;
-	
-	/*
-	 * make sure that the sleep state is supported
-	 */
-	if (system->states[value] != TRUE)
-		return -EINVAL;
-	
-	sm_osl_suspend(value);
-	
-	return (count);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_proc_read_info
- *
- ****************************************************************************/
-
-static int
-sm_osl_proc_read_info (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	acpi_status		status = AE_OK;
-	SM_CONTEXT		*system = NULL;
-	char			*p = page;
-	int			len;
-	acpi_system_info	system_info;
-	acpi_buffer		buffer;
-	u32			i = 0;
-
-	if (!context) {
-		goto end;
-	}
-
-	system = (SM_CONTEXT*) context;
-
-	/* don't get status more than once for a single proc read */
-	if (off != 0) {
-		goto end;
-	}
-
-	/*
-	 * Get ACPI CA Information.
-	 */
-	buffer.length  = sizeof(system_info);
-	buffer.pointer = &system_info;
-
-	status = acpi_get_system_info(&buffer);
-	if (ACPI_FAILURE(status)) {
-		p += sprintf(p, "ACPI-CA Version:         unknown\n");
-	}
-	else {
-		p += sprintf(p, "ACPI-CA Version:         %x\n",
-			system_info.acpi_ca_version);
-	}
-
-	p += sprintf(p, "Sx States Supported:     ");
-	for (i=0; i<SM_MAX_SYSTEM_STATES; i++) {
-		if (system->states[i]) {
-			p += sprintf(p, "S%d ", i);
-		}
-	}
-	p += sprintf(p, "\n");
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return(len);
-}
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_read_dsdt
- *
- ****************************************************************************/
-
-static ssize_t
-sm_osl_read_dsdt(
-	struct file		*file,
-	char			*buf,
-	size_t			count,
-	loff_t			*ppos)
-{
-	acpi_buffer		acpi_buf;
-	void			*data;
-	size_t			size = 0;
-
-	acpi_buf.length = 0;
-	acpi_buf.pointer = NULL;
-
-
-	/* determine what buffer size we will need */
-	if (acpi_get_table(ACPI_TABLE_DSDT, 1, &acpi_buf) != AE_BUFFER_OVERFLOW) {
-		return 0;
-	}
-
-	acpi_buf.pointer = kmalloc(acpi_buf.length, GFP_KERNEL);
-	if (!acpi_buf.pointer) {
-		return -ENOMEM;
-	}
-
-	/* get the table for real */
-	if (!ACPI_SUCCESS(acpi_get_table(ACPI_TABLE_DSDT, 1, &acpi_buf))) {
-		kfree(acpi_buf.pointer);
-		return 0;
-	}
-
-	if (*ppos < acpi_buf.length) {
-		data = acpi_buf.pointer + file->f_pos;
-		size = acpi_buf.length - file->f_pos;
-		if (size > count)
-			size = count;
-		if (copy_to_user(buf, data, size)) {
-			kfree(acpi_buf.pointer);
-			return -EFAULT;
-		}
-	}
-
-	kfree(acpi_buf.pointer);
-
-	*ppos += size;
-
-	return size;
-}
-
-static int
-sm_osl_proc_read_alarm (
-	char                    *page,
-	char                    **start,
-	off_t                   off,
-	int                     count,
-	int                     *eof,
-	void                    *context)
-{
-	char *str = page;
-	int len;
-	u32 sec,min,hr;
-	u32 day,mo,yr;
-
-	if (off != 0) goto out;
-
-	spin_lock(&rtc_lock);
-	sec = CMOS_READ(RTC_SECONDS_ALARM);
-	min = CMOS_READ(RTC_MINUTES_ALARM);
-	hr = CMOS_READ(RTC_HOURS_ALARM);
-
-#if 0
-	/* if I ever get an FACP with proper values, maybe I'll enable this code */
-	if (acpi_gbl_FADT->day_alrm)
-		day = CMOS_READ(acpi_gbl_FADT->day_alrm);
-	else
-		day =  CMOS_READ(RTC_DAY_OF_MONTH);
-	if (acpi_gbl_FADT->mon_alrm)
-		mo = CMOS_READ(acpi_gbl_FADT->mon_alrm);
-	else
-		mo = CMOS_READ(RTC_MONTH);;
-	if (acpi_gbl_FADT->century)
-		yr = CMOS_READ(acpi_gbl_FADT->century) * 100 + CMOS_READ(RTC_YEAR);
-	else
-		yr = CMOS_READ(RTC_YEAR);
-#else
-	day = CMOS_READ(RTC_DAY_OF_MONTH);
-	mo = CMOS_READ(RTC_MONTH);
-	yr = CMOS_READ(RTC_YEAR);
-#endif
-	spin_unlock(&rtc_lock);
-
-	BCD_TO_BIN(sec);
-	BCD_TO_BIN(min);
-	BCD_TO_BIN(hr);
-	BCD_TO_BIN(day);
-	BCD_TO_BIN(mo);
-	BCD_TO_BIN(yr);
-
-	str += sprintf(str,"%4.4u-",yr);
-
-	str += (mo > 12) ?
-		sprintf(str,"**-") :
-		sprintf(str,"%2.2u-",mo);
-
-	str += (day > 31) ?
-		sprintf(str,"** ") :
-		sprintf(str,"%2.2u ",day);
-
-	str += (hr > 23) ?
-		sprintf(str,"**:") :
-		sprintf(str,"%2.2u:",hr);
-
-	str += (min > 59) ?
-		sprintf(str,"**:") :
-		sprintf(str,"%2.2u:",min);
-
-	str += (sec > 59) ?
-		sprintf(str,"**\n") :
-		sprintf(str,"%2.2u\n",sec);
-
- out:
-	len = str - page;
-
-	if (len < count) *eof = 1;
-	else if (len > count) len = count;
-
-	if (len < 0) len = 0;
-
-	*start = page;
-
-	return len;
-}
-
-static int get_date_field(char **str, u32 *value)
-{
-	char *next,*strend;
-	int error = -EINVAL;
-
-	/* try to find delimeter, only to insert null;
-	 *  the end of string won't have one, but is still valid
-	 */
-	next = strpbrk(*str,"- :");
-	if (next) *next++ = '\0';
-
-	*value = simple_strtoul(*str,&strend,10);
-
-	/* signal success if we got a good digit */
-	if (strend != *str) error = 0;
-
-	if (next) *str = next;
-	return error;
-}
-
-
-
-int sm_osl_proc_write_alarm (
-	struct file *file,
-	const char *buffer,
-	unsigned long count,
-	void *data)
-{
-	char buf[30];
-	char *str = buf;
-	u32 sec,min,hr;
-	u32 day,mo,yr;
-	int adjust = 0;
-	unsigned char rtc_control;
-	int error = -EINVAL;
-
-	if (count > sizeof(buf) - 1) return -EINVAL;
-	
-	if (copy_from_user(str,buffer,count)) return -EFAULT;
-
-	str[count] = '\0';
-	/* check for time adjustment */
-	if (str[0] == '+') {
-		str++;
-		adjust = 1;
-	}
-
-	if ((error = get_date_field(&str,&yr)))  goto out;
-	if ((error = get_date_field(&str,&mo)))  goto out;
-	if ((error = get_date_field(&str,&day))) goto out;
-	if ((error = get_date_field(&str,&hr)))  goto out;
-	if ((error = get_date_field(&str,&min))) goto out;
-	if ((error = get_date_field(&str,&sec))) goto out;
-
-
-	if (sec > 59) {
-		min += 1;
-		sec -= 60;
-	}
-	if (min > 59) {
-		hr += 1;
-		min -= 60;
-	} 
-	if (hr > 23) {
-		day += 1;
-		hr -= 24;
-	}
-	if (day > 31) { 
-		mo += 1;
-		day -= 31;
-	}
-	if (mo > 12) {
-		yr += 1;
-		mo -= 12;
-	}
-
-	spin_lock_irq(&rtc_lock);
-	rtc_control = CMOS_READ(RTC_CONTROL);
-	if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
-		BIN_TO_BCD(yr);
-		BIN_TO_BCD(mo);
-		BIN_TO_BCD(day);
-		BIN_TO_BCD(hr);
-		BIN_TO_BCD(min);
-		BIN_TO_BCD(sec);
-	}
-
-	if (adjust) {
-		yr  += CMOS_READ(RTC_YEAR);
-		mo  += CMOS_READ(RTC_MONTH);
-		day += CMOS_READ(RTC_DAY_OF_MONTH);
-		hr  += CMOS_READ(RTC_HOURS);
-		min += CMOS_READ(RTC_MINUTES);
-		sec += CMOS_READ(RTC_SECONDS);
-	}
-	spin_unlock_irq(&rtc_lock);
-
-	if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
-		BCD_TO_BIN(yr);
-		BCD_TO_BIN(mo);
-		BCD_TO_BIN(day);
-		BCD_TO_BIN(hr);
-		BCD_TO_BIN(min);
-		BCD_TO_BIN(sec);
-	}
-
-	if (sec > 59) {
-		min++;
-		sec -= 60;
-	}
-	if (min > 59) {
-		hr++;
-		min -= 60;
-	}
-	if (hr > 23) {
-		day++;
-		hr -= 24;
-	}
-	if (day > 31) {
-		mo++;
-		day -= 31;
-	}
-	if (mo > 12) {
-		yr++;
-		mo -= 12;
-	}
-	if (!(rtc_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
-		BIN_TO_BCD(yr);
-		BIN_TO_BCD(mo);
-		BIN_TO_BCD(day);
-		BIN_TO_BCD(hr);
-		BIN_TO_BCD(min);
-		BIN_TO_BCD(sec);
-	}
-
-	spin_lock_irq(&rtc_lock);
-	/* write the fields the rtc knows about */
-	CMOS_WRITE(hr,RTC_HOURS_ALARM);
-	CMOS_WRITE(min,RTC_MINUTES_ALARM);
-	CMOS_WRITE(sec,RTC_SECONDS_ALARM);
-
-	/* If the system supports an enhanced alarm, it will have non-zero
-	 * offsets into the CMOS RAM here.
-	 * Which for some reason are pointing to the RTC area of memory.
-	 */
-#if 0
-	if (acpi_gbl_FADT->day_alrm) CMOS_WRITE(day,acpi_gbl_FADT->day_alrm);
-	if (acpi_gbl_FADT->mon_alrm) CMOS_WRITE(mo,acpi_gbl_FADT->mon_alrm);
-	if (acpi_gbl_FADT->century)  CMOS_WRITE(yr / 100,acpi_gbl_FADT->century);
-#endif
-	/* enable the rtc alarm interrupt */
-	if (!(rtc_control & RTC_AIE)) {
-		rtc_control |= RTC_AIE;
-		CMOS_WRITE(rtc_control,RTC_CONTROL);
-		CMOS_READ(RTC_INTR_FLAGS);
-	}
-
-	/* unlock the lock on the rtc now that we're done with it */
-	spin_unlock_irq(&rtc_lock);
-
-	acpi_hw_register_bit_access(ACPI_WRITE,ACPI_MTX_LOCK, RTC_EN, 1);
-
-	file->f_pos += count;
-
-	error = 0;
- out:
-	return error ? error : count;
-}
-
-static int 
-sm_osl_proc_read_gpe(
-	char                    *page,
-	char                    **start,
-	off_t                   off,
-	int                     count,
-	int                     *eof,
-	void                    *context)
-{
-	char *str = page;
-	int size;
-	int length;
-	int i;
-	u32 addr,data;
-	
-	if (off) goto out;
-
-	if (acpi_gbl_FADT->V1_gpe0blk) {
-		length = acpi_gbl_FADT->gpe0blk_len / 2;
-
-		str += sprintf(str,"GPE0: ");
-
-		for (i = length; i > 0; i--) {
-			addr = GPE0_EN_BLOCK | (i - 1);
-			data = acpi_hw_register_read(ACPI_MTX_LOCK,addr);
-			str += sprintf(str,"%2.2x ",data);
-		}
-		str += sprintf(str,"\n");
-
-		str += sprintf(str,"Status: ");
-		for (i = length; i > 0; i--) {
-			addr = GPE0_STS_BLOCK | (i - 1);
-			data = acpi_hw_register_read(ACPI_MTX_LOCK,addr);
-			str += sprintf(str,"%2.2x ",data);
-		}
-		str += sprintf(str,"\n");
-	}
-
-	if (acpi_gbl_FADT->V1_gpe1_blk) {
-		length = acpi_gbl_FADT->gpe1_blk_len / 2;
-
-
-		str += sprintf(str,"GPE1: ");
-		for (i = length; i > 0; i--) {
-			addr = GPE1_EN_BLOCK | (i - 1);
-			data = acpi_hw_register_read(ACPI_MTX_LOCK,addr);
-			str += sprintf(str,"%2.2x",data);
-		}
-		str += sprintf(str,"\n");
-
-		str += sprintf(str,"Status: ");
-		for (i = length; i > 0; i--) {
-			addr = GPE1_STS_BLOCK | (i - 1);
-			data = acpi_hw_register_read(ACPI_MTX_LOCK,addr);
-			str += sprintf(str,"%2.2x",data);
-		}
-		str += sprintf(str,"\n");
-	}
- out:
-	size = str - page;
-	if (size < count) *eof = 1;
-	else if (size > count) size = count;
-
-	if (size < 0) size = 0;
-	*start = page;
-
-	return size;
-}
-
-static int
-sm_osl_proc_write_gpe (
-	struct file *file,
-	const char *buffer,
-	unsigned long count,
-	void *data)
-{
-	char buf[256];
-	char *str = buf;
-	char *next;
-	int error = -EINVAL;
-	u32 addr,value = 0;
-
-	if (count > sizeof(buf) + 1) return -EINVAL;
-	
-	if (copy_from_user(str,buffer,count)) return -EFAULT;
-
-	str[count] = '\0';
-
-	/* set addr to which block to refer to */
-	if (!strncmp(str,"GPE0 ",5))      addr = GPE0_EN_BLOCK;
-	else if (!strncmp(str,"GPE1 ",5)) addr = GPE1_EN_BLOCK;
-	else goto out;
-
-	str += 5;
-
-	/* set low order bits to index of bit to set */
-	addr |= simple_strtoul(str,&next,0);
-	if (next == str) goto out;
-
-	if (next) {
-		str = ++next;
-		value = simple_strtoul(str,&next,0);
-		if (next == str) value = 1;
-	}
-
-	value = acpi_hw_register_bit_access(ACPI_WRITE,ACPI_MTX_LOCK,addr,(value ? 1 : 0));
-
-	error = 0;
- out:
-	return error ? error : count;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    sm_osl_suspend
- *
- * PARAMETERS:  %state: Sleep state to enter. Assumed that caller has filtered
- *              out bogus values, so it's one of S1, S2, S3 or S4
- *
- * RETURN:      ACPI_STATUS, whether or not we successfully entered and
- *              exited sleep.
- *
- * DESCRIPTION:
- * This function is the meat of the sleep routine, as far as the ACPI-CA is
- * concerned.
- *
- * See Chapter 9 of the ACPI 2.0 spec for details concerning the methodology here.
- *
- * It will do the following things:
- * - Call arch-specific routines to save the processor and kernel state
- * - Call acpi_enter_sleep_state to actually go to sleep
- * ....
- * When we wake back up, we will:
- * - Restore the processor and kernel state
- * - Return to the user
- *
- * By having this routine in here, it hides it from every part of the CA,
- * so it can remain OS-independent. The only function that calls this is
- * sm_proc_write_sleep, which gets the sleep state to enter from the user.
- *
- ****************************************************************************/
-static acpi_status
-sm_osl_suspend(u32 state)
-{
-	acpi_status status = AE_ERROR;
-	unsigned long wakeup_address;
-
-	/* get out if state is invalid */
-	if (state < ACPI_S1 || state > ACPI_S5) 
-		goto acpi_sleep_done;
-
-	/* make sure we don't get any suprises */
-	disable();
-
-	/* TODO: save device state and suspend them */
-	
-	/* save the processor state to memory if going into S2 or S3;
-	 * save it to disk if going into S4.
-	 * Also, set the FWV if going into an STR state
-	 */
-	if (state == ACPI_S2 || state == ACPI_S3) {
-#ifdef DONT_USE_UNTIL_LOWLEVEL_CODE_EXISTS
-		wakeup_address = acpi_save_state_mem((unsigned long)&&acpi_sleep_done);
-
-		if (!wakeup_address) goto acpi_sleep_done;
-
-		acpi_set_firmware_waking_vector(
-			(ACPI_PHYSICAL_ADDRESS)wakeup_address);
-#endif
-	} else if (state == ACPI_S4)
-#ifdef DONT_USE_UNTIL_LOWLEVEL_CODE_EXISTS
-		if (acpi_save_state_disk((unsigned long)&&acpi_sleep_done)) 
-			goto acpi_sleep_done;
-#endif
-
-	/* set status, since acpi_enter_sleep_state won't return unless something
-	 * goes wrong, or it's just S1.
-	 */
-	status = AE_OK;
-
-	mdelay(10);
-	status = acpi_enter_sleep_state(state);
-
- acpi_sleep_done:
-
-	/* pause for a bit to allow devices to come back on */
-	mdelay(10);
-
-	/* make sure that the firmware waking vector is reset */
-	acpi_set_firmware_waking_vector((ACPI_PHYSICAL_ADDRESS)0);
-
-	acpi_leave_sleep_state(state);
-
-	/* TODO: resume devices and restore their state */
-
-	enable();
-	return status;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_power_down
- *
- ****************************************************************************/
-
-void
-sm_osl_power_down (void)
-{
-	/* Power down the system (S5 = soft off). */
-	sm_osl_suspend(ACPI_S5);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_add_device
- *
- ****************************************************************************/
-
-acpi_status
-sm_osl_add_device(
-	SM_CONTEXT		*system)
-{
-	u32			i = 0;
-	struct proc_dir_entry	*bm_proc_dsdt;
-
-	if (!system) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	printk("ACPI: System firmware supports");
-	for (i=0; i<SM_MAX_SYSTEM_STATES; i++) {
-		if (system->states[i]) {
-			printk(" S%d", i);
-		}
-	}
-	printk("\n");
-
-	if (system->states[ACPI_STATE_S5]) {
-		sm_pm_power_off = pm_power_off;
-		pm_power_off = sm_osl_power_down;
-	}
-
-	create_proc_read_entry(SM_PROC_INFO, S_IRUGO,
-		sm_proc_root, sm_osl_proc_read_info, (void*)system);
-
-	bm_proc_sleep = create_proc_read_entry("sleep", S_IFREG | S_IRUGO | S_IWUSR,
-					    sm_proc_root, sm_osl_proc_read_sleep, (void*)system);
-	if (bm_proc_sleep)
-		bm_proc_sleep->write_proc = sm_osl_proc_write_sleep;
-
-	bm_proc_alarm = create_proc_read_entry("alarm", S_IFREG | S_IRUGO | S_IWUSR,
-					       sm_proc_root,sm_osl_proc_read_alarm, NULL);
-	if (bm_proc_alarm)
-		bm_proc_alarm->write_proc = sm_osl_proc_write_alarm;
-
-	bm_proc_gpe = create_proc_read_entry("gpe", S_IFREG | S_IRUGO | S_IWUSR,
-					     sm_proc_root,sm_osl_proc_read_gpe,NULL);
-	if (bm_proc_gpe)
-		bm_proc_gpe->write_proc = sm_osl_proc_write_gpe;
-	
-	/*
-	 * Get a wakeup address for use when we come back from sleep.
-	 * At least on IA-32, this needs to be in low memory.
-	 * When sleep is supported on other arch's, then we may want
-	 * to move this out to another place, but GFP_LOW should suffice
-	 * for now.
-	 */
-#if 0
-	if (system->states[ACPI_S3] || system->states[ACPI_S4]) {
-		acpi_wakeup_address = (unsigned long)virt_to_phys(get_free_page(GFP_LOWMEM));
-		printk(KERN_INFO "ACPI: Have wakeup address 0x%8.8x\n",acpi_wakeup_address);
-	}
-#endif
-
-	/*
-	 * This returns more than a page, so we need to use our own file ops,
-	 * not proc's generic ones
-	 */
-	bm_proc_dsdt = create_proc_entry(SM_PROC_DSDT, S_IRUSR, sm_proc_root);
-	if (bm_proc_dsdt) {
-		bm_proc_dsdt->proc_fops = &proc_dsdt_operations;
-	}
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-sm_osl_remove_device (
-	SM_CONTEXT		*system)
-{
-	if (!system) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	remove_proc_entry(SM_PROC_INFO, sm_proc_root);
-	remove_proc_entry(SM_PROC_DSDT, sm_proc_root);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_generate_event
- *
- ****************************************************************************/
-
-acpi_status
-sm_osl_generate_event (
-	u32			event,
-	SM_CONTEXT		*system)
-{
-	acpi_status		status = AE_OK;
-
-	if (!system) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (event) {
-
-	default:
-		return(AE_BAD_PARAMETER);
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_init
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	0: Success
- *
- * DESCRIPTION: Module initialization.
- *
- ****************************************************************************/
-
-static int __init
-sm_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	/* abort if no busmgr */
-	if (!bm_proc_root)
-		return -ENODEV;
-
-	sm_proc_root = bm_proc_root;
-	if (!sm_proc_root) {
-		status = AE_ERROR;
-	}
-	else {
-		status = sm_initialize();
-	}
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	sm_osl_cleanup
- *
- * PARAMETERS:	<none>
- *
- * RETURN:	<none>
- *
- * DESCRIPTION: Module cleanup.
- *
- ****************************************************************************/
-
-static void __exit
-sm_osl_cleanup (void)
-{
-	sm_terminate();
-
-	return;
-}
-
-
-module_init(sm_osl_init);
-module_exit(sm_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/thermal/Makefile b/drivers/acpi/ospm/thermal/Makefile
--- a/drivers/acpi/ospm/thermal/Makefile	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,6 +0,0 @@
-O_TARGET	:= ospm_$(notdir $(CURDIR)).o
-obj-m		:= $(O_TARGET)
-EXTRA_CFLAGS	+= $(ACPI_CFLAGS)
-obj-y		:= $(patsubst %.c,%.o,$(wildcard *.c))
-
-include $(TOPDIR)/Rules.make
diff -Nru a/drivers/acpi/ospm/thermal/tz.c b/drivers/acpi/ospm/thermal/tz.c
--- a/drivers/acpi/ospm/thermal/tz.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,642 +0,0 @@
-/*****************************************************************************
- *
- * Module Name: tz.c
- *   $Revision: 44 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <acpi.h>
-#include <bm.h>
-#include "tz.h"
-
-
-#define _COMPONENT		ACPI_THERMAL
-	MODULE_NAME		("tz")
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-extern int TZP;
-
-
-/****************************************************************************
- *                            Internal Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    tz_print
- *
- ****************************************************************************/
-
-void
-tz_print (
-	TZ_CONTEXT		*tz)
-{
-#ifdef ACPI_DEBUG
-	acpi_buffer		buffer;
-	u32			i,j = 0;
-	TZ_THRESHOLDS		*thresholds = NULL;
-
-	FUNCTION_TRACE("tz_print");
-
-	if (!tz)
-		return;
-
-	thresholds = &(tz->policy.thresholds);
-
-	buffer.length = 256;
-	buffer.pointer = acpi_os_callocate(buffer.length);
-	if (!buffer.pointer)
-		return;
-
-	/*
-	 * Get the full pathname for this ACPI object.
-	 */
-	acpi_get_name(tz->acpi_handle, ACPI_FULL_PATHNAME, &buffer);
-
-	/*
-	 * Print out basic thermal zone information.
-	 */
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "| Thermal_zone[%02x]:[%p] %s\n", tz->device_handle, tz->acpi_handle, (char*)buffer.pointer));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   temperature[%d] state[%08x]\n", tz->policy.temperature, tz->policy.state));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   cooling_mode[%08x] polling_freq[%d]\n", tz->policy.cooling_mode, tz->policy.polling_freq));
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   critical[%d]\n", thresholds->critical.temperature));
-	if (thresholds->hot.is_valid)
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   hot[%d]\n", thresholds->hot.temperature));
-	if (thresholds->passive.is_valid) {
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   passive[%d]: tc1[%d] tc2[%d] tsp[%d]\n", thresholds->passive.temperature, thresholds->passive.tc1, thresholds->passive.tc2, thresholds->passive.tsp));
-		if (thresholds->passive.devices.count > 0) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|     devices"));
-			for (j=0; (j<thresholds->passive.devices.count && j<10); j++) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "[%02x]", thresholds->passive.devices.handles[j]));
-			}
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\n"));
-		}
-	}
-	for (i=0; i<TZ_MAX_ACTIVE_THRESHOLDS; i++) {
-		if (!thresholds->active[i].is_valid)
-			break;
-		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|   active[%d]: index[%d]\n", thresholds->active[i].temperature, i));
-		if (thresholds->active[i].devices.count > 0) {
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "|     devices"));
-			for (j=0; (j<thresholds->active[i].devices.count && j<10); j++) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "[%02x]", thresholds->active[i].devices.handles[j]));
-			}
-			ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "\n"));
-		}
-	}
-
-	ACPI_DEBUG_PRINT_RAW ((ACPI_DB_INFO, "+------------------------------------------------------------\n"));
-
-	acpi_os_free(buffer.pointer);
-#endif /*ACPI_DEBUG*/
-
-	return;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_get_temperaturee
- *
- ****************************************************************************/
-
-acpi_status
-tz_get_temperature (
-	TZ_CONTEXT		*tz)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("tz_get_temperature");
-
-	if (!tz) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Evaluate the _TMP method to get the current temperature.
-	 */
-	status = bm_evaluate_simple_integer(tz->acpi_handle, "_TMP", &(tz->policy.temperature));
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Temperature is %d d_k\n", tz->policy.temperature));
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_set_cooling_preference
- *
- ****************************************************************************/
-
-acpi_status
-tz_set_cooling_preference (
-	TZ_CONTEXT              *tz,
-	TZ_COOLING_MODE         cooling_mode)
-{
-	acpi_status             status = AE_OK;
-	acpi_object_list        arg_list;
-	acpi_object             arg0;
-
-	FUNCTION_TRACE("tz_set_cooling_preference");
-
-	if (!tz || ((cooling_mode != TZ_COOLING_MODE_ACTIVE) && (cooling_mode != TZ_COOLING_MODE_PASSIVE))) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Build the argument list, which simply consists of the current
-	 * cooling preference.
-	 */
-	memset(&arg_list, 0, sizeof(acpi_object));
-	arg_list.count = 1;
-	arg_list.pointer = &arg0;
-
-	memset(&arg0, 0, sizeof(acpi_object));
-	arg0.type = ACPI_TYPE_INTEGER;
-	arg0.integer.value = cooling_mode;
-
-	/*
-	 * Evaluate "_SCP" - setting the new cooling preference.
-	 */
-	status = acpi_evaluate_object(tz->acpi_handle, "_SCP", &arg_list, NULL);
-	if (ACPI_FAILURE(status)) {
-		tz->policy.cooling_mode = -1;
-		return_ACPI_STATUS(status);
-	}
-
-	tz->policy.cooling_mode = cooling_mode;
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_get_thresholds
- *
- ****************************************************************************/
-
-acpi_status
-tz_get_thresholds (
-	TZ_CONTEXT		*tz)
-{
-	acpi_status		status = AE_OK;
-	TZ_THRESHOLDS		*thresholds = NULL;
-	u32			value = 0;
-	u32                     i = 0;
-
-	FUNCTION_TRACE("acpi_tz_get_thresholds");
-
-	if (!tz) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	thresholds = &(tz->policy.thresholds);
-
-	/* Critical Shutdown (required) */
-
-	status = bm_evaluate_simple_integer(tz->acpi_handle, "_CRT", &value);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "No critical threshold\n"));
-		return_ACPI_STATUS(status);
-	}
-	else {
-		thresholds->critical.temperature = value;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found critical threshold [%d]\n", thresholds->critical.temperature));
-
-	}
-
-	/* Critical Sleep (optional) */
-
-	status = bm_evaluate_simple_integer(tz->acpi_handle, "_HOT", &value);
-	if (ACPI_FAILURE(status)) {
-		thresholds->hot.is_valid = 0;
-		thresholds->hot.temperature = 0;
-	}
-	else {
-		thresholds->hot.is_valid = 1;
-		thresholds->hot.temperature = value;
-		ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found hot threshold [%d]\n", thresholds->hot.temperature));
-	}
-
-	/* Passive: Processors (optional) */
-
-	status = bm_evaluate_simple_integer(tz->acpi_handle, "_PSV", &value);
-	if (ACPI_FAILURE(status)) {
-		thresholds->passive.is_valid = 0;
-		thresholds->passive.temperature = 0;
-	}
-	else {
-		thresholds->passive.is_valid = 1;
-		thresholds->passive.temperature = value;
-
-		status = bm_evaluate_simple_integer(tz->acpi_handle, "_TC1", &value);
-		if (ACPI_FAILURE(status)) {
-			thresholds->passive.is_valid = 0;
-		}
-		thresholds->passive.tc1 = value;
-
-		status = bm_evaluate_simple_integer(tz->acpi_handle, "_TC2", &value);
-		if (ACPI_FAILURE(status)) {
-			thresholds->passive.is_valid = 0;
-		}
-		thresholds->passive.tc2 = value;
-
-		status = bm_evaluate_simple_integer(tz->acpi_handle, "_TSP", &value);
-		if (ACPI_FAILURE(status)) {
-			thresholds->passive.is_valid = 0;
-		}
-		thresholds->passive.tsp = value;
-
-		status = bm_evaluate_reference_list(tz->acpi_handle, "_PSL", &(thresholds->passive.devices));
-		if (ACPI_FAILURE(status)) {
-			thresholds->passive.is_valid = 0;
-		}
-
-		if (thresholds->passive.is_valid) {
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found passive threshold [%d]\n", thresholds->passive.temperature));
-		}
-		else {
-			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid passive threshold\n"));
-		}
-	}
-
-	/* Active: Fans, etc. (optional) */
-
-	for (i=0; i<TZ_MAX_ACTIVE_THRESHOLDS; i++) {
-
-		char name[5] = {'_','A','C',('0'+i),'\0'};
-
-		status = bm_evaluate_simple_integer(tz->acpi_handle, name, &value);
-		if (ACPI_FAILURE(status)) {
-			thresholds->active[i].is_valid = 0;
-			thresholds->active[i].temperature = 0;
-			break;
-		}
-
-		thresholds->active[i].temperature = value;
-		name[2] = 'L';
-
-		status = bm_evaluate_reference_list(tz->acpi_handle, name, &(thresholds->active[i].devices));
-		if (ACPI_SUCCESS(status)) {
-			thresholds->active[i].is_valid = 1;
-			ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found active threshold [%d]:[%d]\n", i, thresholds->active[i].temperature));
-		}
-		else {
-			ACPI_DEBUG_PRINT((ACPI_DB_ERROR, "Invalid active threshold [%d]\n", i));
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_add_device
- *
- ****************************************************************************/
-
-acpi_status
-tz_add_device (
-	BM_HANDLE               device_handle,
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-	TZ_CONTEXT              *tz = NULL;
-	BM_DEVICE		*device = NULL;
-	acpi_handle             tmp_handle = NULL;
-	static u32		zone_count = 0;
-
-	FUNCTION_TRACE("tz_add_device");
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding thermal zone [%02x].\n", device_handle));
-
-	if (!context || *context) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Invalid context for device [%02x].\n", device_handle));
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	/*
-	 * Get information on this device.
-	 */
-	status = bm_get_device_info(device_handle, &device);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Allocate a new Thermal Zone device.
-	 */
-	tz = acpi_os_callocate(sizeof(TZ_CONTEXT));
-	if (!tz) {
-		return_ACPI_STATUS(AE_NO_MEMORY);
-	}
-
-	tz->device_handle = device->handle;
-	tz->acpi_handle = device->acpi_handle;
-
-	/* TBD: How to manage 'uid' when zones are Pn_p? */
-	sprintf(tz->uid, "%d", zone_count++);
-
-	/*
-	 * Temperature:
-	 * ------------
-	 * Make sure we can read the zone's current temperature (_TMP).
-	 * If we can't, there's no use in doing any policy (abort).
-	 */
-	status = tz_get_temperature(tz);
-	if (ACPI_FAILURE(status))
-		goto end;
-
-	/*
-	 * Polling Frequency:
-	 * ------------------
-	 * If _TZP doesn't exist use the OS default polling frequency.
-	 */
-	status = bm_evaluate_simple_integer(tz->acpi_handle, "_TZP", &(tz->policy.polling_freq));
-	if (ACPI_FAILURE(status)) {
-		tz->policy.polling_freq = TZP;
-	}
-	status = AE_OK;
-
-	/*
-	 * Cooling Preference:
-	 * -------------------
-	 * Default to ACTIVE (noisy) cooling until policy decides otherwise.
-	 * Note that _SCP is optional.
-	 */
-	tz_set_cooling_preference(tz, TZ_COOLING_MODE_ACTIVE);
-
-	/*
-	 * Start Policy:
-	 * -------------
-	 * Thermal policy is included in the kernel (this driver) because
-	 * of the critical role it plays in avoiding nuclear meltdown. =O
-	 */
-	status = tz_policy_add_device(tz);
-	if (ACPI_FAILURE(status))
-		goto end;
-
-	status = tz_osl_add_device(tz);
-	if (ACPI_FAILURE(status))
-		goto end;
-
-	*context = tz;
-
-	tz_print(tz);
-
-end:
-	if (ACPI_FAILURE(status))
-		acpi_os_free(tz);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-tz_remove_device (
-	void			**context)
-{
-	acpi_status		status = AE_OK;
-	TZ_CONTEXT		*tz = NULL;
-
-	FUNCTION_TRACE("tz_remove_device");
-
-	if (!context || !*context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	tz = (TZ_CONTEXT*)(*context);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing thermal zone [%02x].\n", tz->device_handle));
-
-	status = tz_osl_remove_device(tz);
-
-	/*
-	 * Remove Policy:
-	 * --------------
-	 * TBD: Move all thermal zone policy to user-mode daemon...
-	 */
-	status = tz_policy_remove_device(tz);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	acpi_os_free(tz);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *                            External Functions
- ****************************************************************************/
-
-/****************************************************************************
- *
- * FUNCTION:    tz_initialize
- *
- ****************************************************************************/
-
-acpi_status
-tz_initialize (void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("tz_initialize");
-
-	memset(&criteria, 0, sizeof(BM_DEVICE_ID));
-	memset(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Register driver for thermal zone devices.
-	 */
-	criteria.type = BM_TYPE_THERMAL_ZONE;
-
-	driver.notify = &tz_notify;
-	driver.request = &tz_request;
-
-	status = bm_register_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_terminate
- *
- ****************************************************************************/
-
-acpi_status
-tz_terminate (void)
-{
-	acpi_status             status = AE_OK;
-	BM_DEVICE_ID		criteria;
-	BM_DRIVER		driver;
-
-	FUNCTION_TRACE("tz_terminate");
-
-	memset(&criteria, 0, sizeof(BM_DEVICE_ID));
-	memset(&driver, 0, sizeof(BM_DRIVER));
-
-	/*
-	 * Unregister driver for thermal zone devices.
-	 */
-	criteria.type = BM_TYPE_THERMAL_ZONE;
-
-	driver.notify = &tz_notify;
-	driver.request = &tz_request;
-
-	status = bm_unregister_driver(&criteria, &driver);
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_notify
- *
- ****************************************************************************/
-
-acpi_status
-tz_notify (
-	BM_NOTIFY               notify_type,
-	BM_HANDLE               device_handle,
-	void                    **context)
-{
-	acpi_status             status = AE_OK;
-	TZ_CONTEXT		*tz = NULL;
-
-	FUNCTION_TRACE("tz_notify");
-
-	if (!context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	tz = (TZ_CONTEXT*)*context;
-
-	switch (notify_type) {
-
-	case BM_NOTIFY_DEVICE_ADDED:
-		status = tz_add_device(device_handle, context);
-		break;
-
-	case BM_NOTIFY_DEVICE_REMOVED:
-		status = tz_remove_device(context);
-		break;
-
-	case TZ_NOTIFY_TEMPERATURE_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Temperature (_TMP) change event detected.\n"));
-		tz_policy_check(*context);
-		status = tz_get_temperature(tz);
-		if (ACPI_SUCCESS(status)) {
-			status = tz_osl_generate_event(notify_type, tz);
-		}
-		break;
-
-	case TZ_NOTIFY_THRESHOLD_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Threshold (_SCP) change event detected.\n"));
-		status = tz_policy_remove_device(tz);
-		if (ACPI_SUCCESS(status)) {
-			status = tz_policy_add_device(tz);
-		}
-		status = tz_osl_generate_event(notify_type, tz);
-		break;
-
-	case TZ_NOTIFY_DEVICE_LISTS_CHANGE:
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Device lists (_ALx, _PSL, _TZD) change event detected.\n"));
-		status = tz_policy_remove_device(tz);
-		if (ACPI_SUCCESS(status)) {
-			status = tz_policy_add_device(tz);
-		}
-		status = tz_osl_generate_event(notify_type, tz);
-		break;
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	return_ACPI_STATUS(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_request
- *
- ****************************************************************************/
-
-acpi_status
-tz_request (
-	BM_REQUEST		*request,
-	void                    *context)
-{
-	acpi_status             status = AE_OK;
-	TZ_CONTEXT              *tz = NULL;
-
-	FUNCTION_TRACE("tz_request");
-
-	/*
-	 * Must have a valid request structure and context.
-	 */
-	if (!request || !context) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	tz = (TZ_CONTEXT*)context;
-
-	/*
-	 * Handle request:
-	 * ---------------
-	 */
-	switch (request->command) {
-
-	default:
-		status = AE_SUPPORT;
-		break;
-	}
-
-	request->status = status;
-
-	return_ACPI_STATUS(status);
-}
diff -Nru a/drivers/acpi/ospm/thermal/tz_osl.c b/drivers/acpi/ospm/thermal/tz_osl.c
--- a/drivers/acpi/ospm/thermal/tz_osl.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,398 +0,0 @@
-/******************************************************************************
- *
- * Module Name: tz_osl.c
- *   $Revision: 25 $
- *
- *****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/proc_fs.h>
-#include <acpi.h>
-#include "tz.h"
-
-
-MODULE_AUTHOR("Andrew Grover");
-MODULE_DESCRIPTION("ACPI Component Architecture (CA) - Thermal Zone Driver");
-MODULE_LICENSE("GPL");
-
-int TZP = 0;
-MODULE_PARM(TZP, "i");
-MODULE_PARM_DESC(TZP, "Thermal zone polling frequency, in 1/10 seconds.\n");
-
-
-#define TZ_PROC_ROOT		"thermal"
-#define TZ_PROC_STATUS		"status"
-#define TZ_PROC_INFO		"info"
-
-extern struct proc_dir_entry	*bm_proc_root;
-static struct proc_dir_entry	*tz_proc_root = NULL;
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_proc_read_info
- *
- ****************************************************************************/
-
-static int
-tz_osl_proc_read_info (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	acpi_status		status = AE_OK;
-	char			name[5];
-	acpi_buffer		buffer = {sizeof(name), &name};
-	TZ_CONTEXT		*tz = NULL;
-	TZ_THRESHOLDS		*thresholds = NULL;
-	char			*p = page;
-	int 			len = 0;
-	u32			i,j;
-	u32			t = 0;
-
-	if (!context || (off != 0))
-		goto end;
-
-	tz = (TZ_CONTEXT*)context;
-
-	thresholds = &(tz->policy.thresholds);
-
-	p += sprintf(p, "critical (S5): trip=%d\n", thresholds->critical.temperature);
-	
-	if (thresholds->hot.is_valid)
-		p += sprintf(p, "critical (S4): trip=%d\n", thresholds->hot.temperature);
-
-	if (thresholds->passive.is_valid) {
-		p += sprintf(p, "passive:       trip=%d tc1=%d tc2=%d tsp=%d devices=", thresholds->passive.temperature, thresholds->passive.tc1, thresholds->passive.tc2, thresholds->passive.tsp);
-		for (j=0; j<thresholds->passive.devices.count; j++)
-			p += sprintf(p, "%08x%c", thresholds->passive.devices.handles[j], (j==thresholds->passive.devices.count-1)?'\n':',');
-	}
-
-	for (i=0; i<TZ_MAX_ACTIVE_THRESHOLDS; i++) {
-		if (!(thresholds->active[i].is_valid))
-			break;
-		p += sprintf(p, "active[%d]:     trip=%d devices=", i, thresholds->active[i].temperature);
-		for (j=0; j<thresholds->active[i].devices.count; j++)
-			p += sprintf(p, "%08x%c", thresholds->active[i].devices.handles[j], (j==thresholds->passive.devices.count-1)?'\n':',');
-	}
-
-	p += sprintf(p, "cooling mode:  ");
-	switch (tz->policy.cooling_mode) {
-	case TZ_COOLING_MODE_ACTIVE:
-		p += sprintf(p, "active (noisy)\n");
-		break;
-	case TZ_COOLING_MODE_PASSIVE:
-		p += sprintf(p, "passive (quiet)\n");
-		break;
-	default:
-		p += sprintf(p, "unknown\n");
-		break;
-	}
-
-	p += sprintf(p, "polling:       ");
-	switch (tz->policy.polling_freq) {
-	case 0:
-		p += sprintf(p, "disabled\n");
-		break;
-	default:
-		p += sprintf(p, "%d dS\n", tz->policy.polling_freq);
-		break;
-	}
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return len;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_proc_write_info
- *
- ****************************************************************************/
-
-static int tz_osl_proc_write_info (
-        struct file		*file, 
-        const char		*buffer, 
-        unsigned long		count, 
-        void			*data)
-{
-	TZ_CONTEXT		*tz = NULL;
-	u32			state = 0;
-	u32			size = 0;
-
-	if (!buffer || (count==0) || !data) {
-		goto end;
-	}
-
-	tz = (TZ_CONTEXT*)data;
-
-	size = strlen(buffer);
-	if (size < 4)
-		goto end;
-	
-	/* Cooling preference: "scp=0" (active) or "scp=1" (passive) */
-	if (0 == strncmp(buffer, "scp=", 4)) {
-		tz_set_cooling_preference(tz, (buffer[4] - '0'));
-	}
-
-	/* Polling frequency: "tzp=X" (poll every X [0-9] seconds) */
-	else if (0 == strncmp(buffer, "tzp=", 4)) {
-		tz->policy.polling_freq = (buffer[4] - '0') * 10;
-		tz_policy_check(tz);
-	}
-
-end:
-        return count;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_proc_read_status
- *
- ****************************************************************************/
-
-static int
-tz_osl_proc_read_status (
-	char			*page,
-	char			**start,
-	off_t			off,
-	int 			count,
-	int 			*eof,
-	void			*context)
-{
-	TZ_CONTEXT		*tz = NULL;
-	char			*p = page;
-	int 			len = 0;
-
-	if (!context || (off != 0)) {
-		goto end;
-	}
-
-	tz = (TZ_CONTEXT*)context;
-
-	/* Temperature */
-
-	tz_get_temperature(tz);
-
-	p += sprintf(p, "temperature:   %d dK\n", tz->policy.temperature);
-
-	p += sprintf(p, "state:         ");
-	if (tz->policy.state == 0)
-		p += sprintf(p, "ok\n");
-	else if (tz->policy.state & TZ_STATE_CRITICAL)
-		p += sprintf(p, "critical\n");
-	else if (tz->policy.state & TZ_STATE_HOT)
-		p += sprintf(p, "hot\n");
-	else {
-		if (tz->policy.state & TZ_STATE_ACTIVE)
-			p += sprintf(p, "active[%d] ", tz->policy.state & 0x07);
-		if (tz->policy.state & TZ_STATE_PASSIVE)
-			p += sprintf(p, "passive ");
-		p += sprintf(p, "\n");
-	}
-
-end:
-	len = (p - page);
-	if (len <= off+count) *eof = 1;
-	*start = page + off;
-	len -= off;
-	if (len>count) len = count;
-	if (len<0) len = 0;
-
-	return(len);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_add_device
- *
- ****************************************************************************/
-
-acpi_status
-tz_osl_add_device(
-	TZ_CONTEXT		*tz)
-{
-	struct proc_dir_entry	*proc_entry = NULL;
-	struct proc_dir_entry	*proc_child_entry = NULL;
-
-	if (!tz) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	printk("ACPI: Thermal Zone found\n");
-
-	proc_entry = proc_mkdir(tz->uid, tz_proc_root);
-	if (!proc_entry) 
-		return(AE_ERROR);
-
-	proc_child_entry = create_proc_read_entry(TZ_PROC_STATUS, S_IFREG | S_IRUGO, proc_entry, tz_osl_proc_read_status, (void*)tz);
-	if (!proc_child_entry) 
-		return(AE_ERROR);
-
-	proc_child_entry = create_proc_entry(TZ_PROC_INFO, S_IFREG | 0644, proc_entry);
-	if (!proc_child_entry)
-		return(AE_ERROR);
-
-	proc_child_entry->read_proc = tz_osl_proc_read_info;
-	proc_child_entry->write_proc = tz_osl_proc_write_info;
-	proc_child_entry->data = (void*)tz;
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_remove_device
- *
- ****************************************************************************/
-
-acpi_status
-tz_osl_remove_device (
-	TZ_CONTEXT		*tz)
-{
-	char			proc_entry[64];
-
-	if (!tz) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	sprintf(proc_entry, "%s/%s", tz->uid, TZ_PROC_INFO);
-	remove_proc_entry(proc_entry, tz_proc_root);
-
-	sprintf(proc_entry, "%s/%s", tz->uid, TZ_PROC_STATUS);
-	remove_proc_entry(proc_entry, tz_proc_root);
-
-	sprintf(proc_entry, "%s", tz->uid);
-	remove_proc_entry(proc_entry, tz_proc_root);
-
-	return(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_generate_event
- *
- ****************************************************************************/
-
-acpi_status
-tz_osl_generate_event (
-	u32			event,
-	TZ_CONTEXT		*tz)
-{
-	acpi_status		status = AE_OK;
-
-	if (!tz) {
-		return(AE_BAD_PARAMETER);
-	}
-
-	switch (event) {
-
-	case TZ_NOTIFY_TEMPERATURE_CHANGE:
-		status = bm_osl_generate_event(tz->device_handle,
-			TZ_PROC_ROOT, tz->uid, event,
-			tz->policy.temperature);
-		break;
-
-	case TZ_NOTIFY_THRESHOLD_CHANGE:
-	case TZ_NOTIFY_DEVICE_LISTS_CHANGE:
-		status = bm_osl_generate_event(tz->device_handle,
-			TZ_PROC_ROOT, tz->uid, event, 0);
-		break;
-
-	default:
-		return(AE_BAD_PARAMETER);
-		break;
-	}
-
-	return(status);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_init
- *
- ****************************************************************************/
-
-static int __init
-tz_osl_init (void)
-{
-	acpi_status		status = AE_OK;
-
-	/* abort if no busmgr */
-	if (!bm_proc_root)
-		return -ENODEV;
-
-	tz_proc_root = proc_mkdir(TZ_PROC_ROOT, bm_proc_root);
-	if (!tz_proc_root) {
-		status = AE_ERROR;
-	}
-	else {
-		status = tz_initialize();
-		if (ACPI_FAILURE(status)) {
-			remove_proc_entry(TZ_PROC_ROOT, bm_proc_root);
-		}
-
-	}
-
-	return (ACPI_SUCCESS(status)) ? 0 : -ENODEV;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:	tz_osl_cleanup
- *
- ****************************************************************************/
-
-static void __exit
-tz_osl_cleanup (void)
-{
-	tz_terminate();
-
-	if (tz_proc_root) {
-		remove_proc_entry(TZ_PROC_ROOT, bm_proc_root);
-	}
-
-	return;
-}
-
-
-module_init(tz_osl_init);
-module_exit(tz_osl_cleanup);
diff -Nru a/drivers/acpi/ospm/thermal/tzpolicy.c b/drivers/acpi/ospm/thermal/tzpolicy.c
--- a/drivers/acpi/ospm/thermal/tzpolicy.c	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,579 +0,0 @@
-/****************************************************************************
- *
- * Module Name: tzpolicy.c -
- *   $Revision: 30 $
- *
- ****************************************************************************/
-
-/*
- *  Copyright (C) 2000, 2001 Andrew Grover
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-/*
- * TBD: 1. Support performance-limit control for non-processor devices
- *         (those listed in _TZD, e.g. graphics).
- */
-
-#include <linux/proc_fs.h>
-#include <linux/sysctl.h>
-#include <linux/pm.h>
-#include <linux/sched.h>
-
-#include <acpi.h>
-#include <bm.h>
-#include "tz.h"
-
-
-#define _COMPONENT		ACPI_THERMAL
-	MODULE_NAME		("tzpolicy")
-
-
-/****************************************************************************
- *                                  Globals
- ****************************************************************************/
-
-void
-tz_policy_run (
-	unsigned long           data);
-
-
-/****************************************************************************
- *                              Internal Functions
- ****************************************************************************/
-
-acpi_status
-set_performance_limit (
-	BM_HANDLE               device_handle,
-	u32			flag)
-{
-	acpi_status             status;
-	BM_REQUEST              request;
-
-	request.status = AE_OK;
-	request.handle = device_handle;
-	request.command = PR_COMMAND_SET_PERF_LIMIT;
-	request.buffer.length = sizeof(u32);
-	request.buffer.pointer = &flag;
-
-	status = bm_request(&request);
-
-	if (ACPI_FAILURE(status))
-		return status;
-	else
-		return request.status;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_critical
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-tz_policy_critical(
-	TZ_CONTEXT		*tz)
-{
-	FUNCTION_TRACE("tz_policy_critical");
-
-	if (!tz) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (tz->policy.temperature >= tz->policy.thresholds.critical.temperature) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Critical (S5) threshold reached.\n"));
-		/* TBD:	Need method for shutting down system. */
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_hot
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-tz_policy_hot(
-	TZ_CONTEXT		*tz)
-{
-	FUNCTION_TRACE("tz_policy_hot");
-
-	if (!tz || !tz->policy.thresholds.hot.is_valid) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	if (tz->policy.temperature >= tz->policy.thresholds.hot.temperature) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Critical (S4) threshold reached.\n"));
-		/* TBD:	Need method for invoking OS-level critical suspend. */
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_passive
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-tz_policy_passive(
-	TZ_CONTEXT		*tz)
-{
-	TZ_PASSIVE_THRESHOLD	*passive = NULL;
-	static u32		last_temperature = 0;
-	s32			trend = 0;
-	u32			i = 0;
-
-	FUNCTION_TRACE("tz_policy_passive");
-
-	if (!tz || !tz->policy.thresholds.passive.is_valid) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	passive = &(tz->policy.thresholds.passive);
-
-	if (tz->policy.temperature >= passive->temperature) {
-		/*
-		 * Thermal trend?
-		 * --------------
-		 * Using the passive cooling equation (see the ACPI
-		 * Specification), calculate the current thermal trend
-		 * (a.k.a. performance delta).
-		 */
-		trend = passive->tc1 * (tz->policy.temperature - last_temperature) + passive->tc2 * (tz->policy.temperature - passive->temperature);
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "trend[%d] = TC1[%d]*(temp[%d]-last[%d]) + TC2[%d]*(temp[%d]-passive[%d])\n", trend, passive->tc1, tz->policy.temperature, last_temperature, passive->tc2, tz->policy.temperature, passive->temperature));
-
-		last_temperature = tz->policy.temperature;
-
-		/*
-		 * Heating Up?
-		 * -----------
-		 * Decrease thermal performance limit on all passive
-		 * cooling devices (processors).
-		 */
-		if (trend > 0) {
-			for (i=0; i<passive->devices.count; i++)
-				set_performance_limit(passive->devices.handles[i], PR_PERF_DEC);
-		}
-		/*
-		 * Cooling Off?
-		 * ------------
-		 * Increase thermal performance limit on all passive
-		 * cooling devices (processors).
-		 */
-		else if (trend < 0) {
-			for (i=0; i<passive->devices.count; i++)
-				set_performance_limit(passive->devices.handles[i], PR_PERF_INC);
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_active
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-tz_policy_active(
-	TZ_CONTEXT              *tz)
-{
-	acpi_status             status = AE_OK;
-	TZ_ACTIVE_THRESHOLD	*active = NULL;
-	u32                     i,j = 0;
-
-	FUNCTION_TRACE("tz_policy_active");
-
-	if (!tz || !tz->policy.thresholds.active[0].is_valid) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	for (i=0; i<TZ_MAX_ACTIVE_THRESHOLDS; i++) {
-
-		active = &(tz->policy.thresholds.active[i]);
-		if (!active || !active->is_valid)
-			break;
-
-		/*
-		 * Above Threshold?
-		 * ----------------
-		 * If not already enabled, turn ON all cooling devices
-		 * associated with this active threshold.
-		 */
-		if ((tz->policy.temperature >= active->temperature) && (active->cooling_state != TZ_COOLING_ENABLED)) {
-			for (j = 0; j < active->devices.count; j++) {
-				status = bm_set_device_power_state(active->devices.handles[j], ACPI_STATE_D0);
-				if (ACPI_SUCCESS(status)) {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Cooling device [%02x] now ON.\n", active->devices.handles[j]));
-				}
-				else {
-					ACPI_DEBUG_PRINT ((ACPI_DB_WARN, "Unable to turn ON cooling device [%02x].\n", active->devices.handles[j]));
-				}
-			}
-  			active->cooling_state = TZ_COOLING_ENABLED;
-		}
-		/*
-		 * Below Threshold?
-		 * ----------------
-		 * Turn OFF all cooling devices associated with this
-		 * threshold.  Note that by checking "if not disabled" we
-		 * turn off all cooling devices for thresholds in the
-		 * TZ_COOLING_STATE_UNKNOWN state, useful as a level-set
-		 * during the first pass.
-		 */
-		else if (active->cooling_state != TZ_COOLING_DISABLED) {
-			for (j = 0; j < active->devices.count; j++) {
-				status = bm_set_device_power_state(active->devices.handles[j], ACPI_STATE_D3);
-				if (ACPI_SUCCESS(status)) {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Cooling device [%02x] now OFF.\n", active->devices.handles[j]));
-				}
-				else {
-					ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Unable to turn OFF cooling device [%02x].\n", active->devices.handles[j]));
-				}
-			}
-			active->cooling_state = TZ_COOLING_DISABLED;
-		}
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_check
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION: Note that this function will get called whenever:
- *                1. A thermal event occurs.
- *                2. The polling/sampling time period expires.
- *
- ****************************************************************************/
-
-void
-tz_policy_check (
-	void                    *context)
-{
-	acpi_status             status = AE_OK;
-	TZ_CONTEXT              *tz = NULL;
-	TZ_POLICY		*policy = NULL;
-	TZ_THRESHOLDS		*thresholds = NULL;
-	u32                     previous_temperature = 0;
-	u32                     previous_state = 0;
-	u32                     active_index = 0;
-	u32                     i = 0;
-	u32                     sleep_time = 0;
-
-	FUNCTION_TRACE("tz_policy_check");
-
-	if (!context) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
-		return_VOID;
-	}
-
-	tz = (TZ_CONTEXT*)context;
-	policy = &(tz->policy);
-	thresholds = &(tz->policy.thresholds);
-
-	/*
-	 * Preserve Previous State:
-	 * ------------------------
-	 */
-	previous_temperature = tz->policy.temperature;
-	previous_state = tz->policy.state;
-
-	/*
-	 * Get Temperature:
-	 * ----------------
-	 */
-	status = tz_get_temperature(tz);
-	if (ACPI_FAILURE(status)) {
-		return_VOID;
-	}
-
-	/*
-	 * Calculate State:
-	 * ----------------
-	 */
-	policy->state = TZ_STATE_OK;
-
-	/* Critical? */
-	if (policy->temperature >= thresholds->critical.temperature)
-		policy->state |= TZ_STATE_CRITICAL;
-
-	/* Hot? */
-	if ((thresholds->hot.is_valid) &&  (policy->temperature >= thresholds->hot.temperature))
-		policy->state |= TZ_STATE_CRITICAL;
-
-	/* Passive? */
-	if ((thresholds->passive.is_valid) && (policy->temperature >= thresholds->passive.temperature))
-		policy->state |= TZ_STATE_PASSIVE;
-
-	/* Active? */
-	if (thresholds->active[0].is_valid) {
-		for (i=0; i<TZ_MAX_ACTIVE_THRESHOLDS; i++) {
-			if ((thresholds->active[i].is_valid) && (policy->temperature >= thresholds->active[i].temperature)) {
-				policy->state |= TZ_STATE_ACTIVE;
-				if (i > active_index)
-					active_index = i;
-			}
-		}
-		policy->state |= active_index;
-	}
-
-	/*
-	 * Invoke Policy:
-	 * --------------
-	 * Note that policy must be invoked both when 'going into' a
-	 * policy state (e.g. to allow fans to be turned on) and 'going
-	 * out of' a policy state (e.g. to allow fans to be turned off);
-	 * thus we must preserve the previous state.
-	 */
-	if (policy->state & TZ_STATE_CRITICAL)
-		tz_policy_critical(tz);
-	if (policy->state & TZ_STATE_HOT)
-		tz_policy_hot(tz);
-	if ((policy->state & TZ_STATE_PASSIVE) || (previous_state & TZ_STATE_PASSIVE))
-		tz_policy_passive(tz);
-	if ((policy->state & TZ_STATE_ACTIVE) || (previous_state & TZ_STATE_ACTIVE))
-		tz_policy_active(tz);
-
-	/*
-	 * Calculate Sleep Time:
-	 * ---------------------
-	 * If we're in the passive state, use _TSP's value.  Otherwise
-	 * use _TZP or the OS's default polling frequency.  If no polling
-	 * frequency is specified then we'll wait forever (that is, until
-	 * a thermal event occurs -- e.g. never poll).  Note that _TSP
-	 * and _TZD values are given in 1/10th seconds.
-	 */
-	if (policy->state & TZ_STATE_PASSIVE)
-		sleep_time = thresholds->passive.tsp * 100;
-	else if (policy->polling_freq > 0)
-		sleep_time = policy->polling_freq * 100;
-	else
-		sleep_time = WAIT_FOREVER;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Thermal_zone[%02x]: temperature[%d] state[%08x]\n", tz->device_handle, policy->temperature, policy->state));
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Scheduling next poll in [%d]ms.\n", sleep_time));
-
-	/*
-	 * Schedule Next Poll:
-	 * -------------------
-	 */
-	if (sleep_time < WAIT_FOREVER) {
-		if (timer_pending(&(policy->timer)))
-			mod_timer(&(policy->timer), (HZ*sleep_time)/1000);
-		else {
-			policy->timer.data = (u32)tz;
-			policy->timer.function = tz_policy_run;
-			policy->timer.expires = jiffies + (HZ*sleep_time)/1000;
-			add_timer(&(policy->timer));
-		}
-	}
-	else {
-		if (timer_pending(&(policy->timer)))
-			del_timer(&(policy->timer));
-	}
-
-	return_VOID;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_run
- *
- * PARAMETERS:
- *
- * RETURN:
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-
-void
-tz_policy_run (
-	unsigned long           data)
-{
-	acpi_status             status = AE_OK;
-
-	FUNCTION_TRACE("tz_policy_run");
-
-	if (!data) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Invalid (NULL) context.\n"));
-		return_VOID;
-	}
-
-	/*
-	 * Defer to Non-Interrupt Level:
-	 * -----------------------------
-	 * Note that all Linux kernel timers run at interrupt-level (ack!).
-	 */
-	status = acpi_os_queue_for_execution(OSD_PRIORITY_GPE,  tz_policy_check, (void*)data);
-	if (ACPI_FAILURE(status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Error invoking thermal policy.\n"));
-	}
-
-	return_VOID;
-}
-
-
-/****************************************************************************
- *
- * FUNCTION:    tz_policy_add_device
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-tz_policy_add_device (
-	TZ_CONTEXT		*tz)
-{
-	acpi_status             status = AE_OK;
-	TZ_THRESHOLDS           *thresholds = NULL;
-	u32                     i,j = 0;
-
-	FUNCTION_TRACE("tz_policy_add_device");
-
-	if (!tz) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Adding policy for thermal zone [%02x].\n", tz->device_handle));
-
-	/*
-	 * Get Thresholds:
-	 * ---------------
-	 */
-	status = tz_get_thresholds(tz);
-	if (ACPI_FAILURE(status)) {
-		return_ACPI_STATUS(status);
-	}
-
-	/*
-	 * Initialize Policies:
-	 * --------------------
-	 */
-	if (tz->policy.thresholds.passive.is_valid) {
-		for (i=0; i<tz->policy.thresholds.passive.devices.count; i++)
-			set_performance_limit(tz->policy.thresholds.passive.devices.handles[i], PR_PERF_MAX);
-		tz_policy_passive(tz);
-	}
-	if (tz->policy.thresholds.active[0].is_valid)
-		tz_policy_active(tz);
-
-	/*
-	 * Initialize Policy Timer:
-	 * ------------------------
-	 */
-	init_timer(&(tz->policy.timer));
-
-	/*
-	 * Start Policy:
-	 * -------------
-	 * Run an initial check using this zone's policy.
-	 */
-	tz_policy_check(tz);
-
-	return_ACPI_STATUS(AE_OK);
-}
-
-
-/*****************************************************************************
- *
- * FUNCTION:    tz_policy_remove_device
- *
- * PARAMETERS:
- *
- * RETURN:	
- *
- * DESCRIPTION:
- *
- ****************************************************************************/
-
-acpi_status
-tz_policy_remove_device(
-	TZ_CONTEXT		*tz)
-{
-	u32			i = 0;
-
-	FUNCTION_TRACE("tz_remove_device");
-
-	if (!tz) {
-		return_ACPI_STATUS(AE_BAD_PARAMETER);
-	}
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Removing policy for thermal zone [%02x].\n", tz->device_handle));
-
-	/*
-	 * Delete the thermal zone policy timer entry, if exists.
-	 */
-	if (timer_pending(&(tz->policy.timer)))
-		del_timer(&(tz->policy.timer));
-
-	/*
-	 * Reset thermal performance limit on all processors back to max.
-	 */
-	if (tz->policy.thresholds.passive.is_valid) {
-		for (i=0; i<tz->policy.thresholds.passive.devices.count; i++)
-			set_performance_limit(tz->policy.thresholds.passive.devices.handles[i], PR_PERF_MAX);
-	}
-
-	return_ACPI_STATUS(AE_OK);
-}
diff -Nru a/drivers/acpi/parser/Makefile b/drivers/acpi/parser/Makefile
--- a/drivers/acpi/parser/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/parser/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/parser/psargs.c b/drivers/acpi/parser/psargs.c
--- a/drivers/acpi/parser/psargs.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/parser/psargs.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: psargs - Parse AML opcode arguments
- *              $Revision: 52 $
+ *              $Revision: 58 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("psargs")
+	 ACPI_MODULE_NAME    ("psargs")
 
 
 /*******************************************************************************
@@ -54,10 +54,10 @@
 	u32                     length = 0;
 
 
-	FUNCTION_TRACE ("Ps_get_next_package_length");
+	ACPI_FUNCTION_TRACE ("Ps_get_next_package_length");
 
 
-	encoded_length = (u32) GET8 (parser_state->aml);
+	encoded_length = (u32) ACPI_GET8 (parser_state->aml);
 	parser_state->aml++;
 
 
@@ -70,7 +70,7 @@
 
 	case 1: /* 2-byte encoding (next byte + bits 0-3) */
 
-		length = ((GET8 (parser_state->aml) << 04) |
+		length = ((ACPI_GET8 (parser_state->aml) << 04) |
 				 (encoded_length & 0x0F));
 		parser_state->aml++;
 		break;
@@ -78,8 +78,8 @@
 
 	case 2: /* 3-byte encoding (next 2 bytes + bits 0-3) */
 
-		length = ((GET8 (parser_state->aml + 1) << 12) |
-				  (GET8 (parser_state->aml)    << 04) |
+		length = ((ACPI_GET8 (parser_state->aml + 1) << 12) |
+				  (ACPI_GET8 (parser_state->aml)    << 04) |
 				  (encoded_length & 0x0F));
 		parser_state->aml += 2;
 		break;
@@ -87,9 +87,9 @@
 
 	case 3: /* 4-byte encoding (next 3 bytes + bits 0-3) */
 
-		length = ((GET8 (parser_state->aml + 2) << 20) |
-				  (GET8 (parser_state->aml + 1) << 12) |
-				  (GET8 (parser_state->aml)    << 04) |
+		length = ((ACPI_GET8 (parser_state->aml + 2) << 20) |
+				  (ACPI_GET8 (parser_state->aml + 1) << 12) |
+				  (ACPI_GET8 (parser_state->aml)    << 04) |
 				  (encoded_length & 0x0F));
 		parser_state->aml += 3;
 		break;
@@ -120,7 +120,7 @@
 	NATIVE_UINT             length;
 
 
-	FUNCTION_TRACE ("Ps_get_next_package_end");
+	ACPI_FUNCTION_TRACE ("Ps_get_next_package_end");
 
 
 	length = (NATIVE_UINT) acpi_ps_get_next_package_length (parser_state);
@@ -153,12 +153,12 @@
 	u32                     length;
 
 
-	FUNCTION_TRACE ("Ps_get_next_namestring");
+	ACPI_FUNCTION_TRACE ("Ps_get_next_namestring");
 
 
 	/* Handle multiple prefix characters */
 
-	while (acpi_ps_is_prefix_char (GET8 (end))) {
+	while (acpi_ps_is_prefix_char (ACPI_GET8 (end))) {
 		/* include prefix '\\' or '^' */
 
 		end++;
@@ -166,7 +166,7 @@
 
 	/* Decode the path */
 
-	switch (GET8 (end)) {
+	switch (ACPI_GET8 (end)) {
 	case 0:
 
 		/* Null_name */
@@ -190,7 +190,7 @@
 
 		/* multiple name segments */
 
-		length = (u32) GET8 (end + 1) * 4;
+		length = (u32) ACPI_GET8 (end + 1) * 4;
 		end += 2 + length;
 		break;
 
@@ -247,7 +247,7 @@
 	acpi_parse_object       *count;
 
 
-	FUNCTION_TRACE ("Ps_get_next_namepath");
+	ACPI_FUNCTION_TRACE ("Ps_get_next_namepath");
 
 
 	path = acpi_ps_get_next_namestring (parser_state);
@@ -340,7 +340,7 @@
 	acpi_generic_state      scope_info;
 
 
-	FUNCTION_TRACE ("Ps_get_next_namepath");
+	ACPI_FUNCTION_TRACE ("Ps_get_next_namepath");
 
 
 	path = acpi_ps_get_next_namestring (parser_state);
@@ -369,8 +369,8 @@
 		 * parent tree, but don't open a new scope -- we just want to lookup the
 		 * object  (MUST BE mode EXECUTE to perform upsearch)
 		 */
-		status = acpi_ns_lookup (&scope_info, path, ACPI_TYPE_ANY, IMODE_EXECUTE,
-				 NS_SEARCH_PARENT | NS_DONT_OPEN_SCOPE, NULL,
+		status = acpi_ns_lookup (&scope_info, path, ACPI_TYPE_ANY, ACPI_IMODE_EXECUTE,
+				 ACPI_NS_SEARCH_PARENT | ACPI_NS_DONT_OPEN_SCOPE, NULL,
 				 &node);
 		if (ACPI_SUCCESS (status)) {
 			if (node->type == ACPI_TYPE_METHOD) {
@@ -391,11 +391,11 @@
 					name_op->node = method_node;
 					acpi_ps_append_arg (arg, name_op);
 
-					if (!method_node->object) {
+					if (!acpi_ns_get_attached_object (method_node)) {
 						return_VOID;
 					}
 
-					*arg_count = (method_node->object)->method.param_count;
+					*arg_count = (acpi_ns_get_attached_object (method_node))->method.param_count;
 				}
 
 				return_VOID;
@@ -444,7 +444,7 @@
 	acpi_parse_object       *arg)
 {
 
-	FUNCTION_TRACE_U32 ("Ps_get_next_simple_arg", arg_type);
+	ACPI_FUNCTION_TRACE_U32 ("Ps_get_next_simple_arg", arg_type);
 
 
 	switch (arg_type) {
@@ -452,7 +452,7 @@
 	case ARGP_BYTEDATA:
 
 		acpi_ps_init_op (arg, AML_BYTE_OP);
-		arg->value.integer = (u32) GET8 (parser_state->aml);
+		arg->value.integer = (u32) ACPI_GET8 (parser_state->aml);
 		parser_state->aml++;
 		break;
 
@@ -463,7 +463,7 @@
 
 		/* Get 2 bytes from the AML stream */
 
-		MOVE_UNALIGNED16_TO_32 (&arg->value.integer, parser_state->aml);
+		ACPI_MOVE_UNALIGNED16_TO_32 (&arg->value.integer, parser_state->aml);
 		parser_state->aml += 2;
 		break;
 
@@ -474,7 +474,7 @@
 
 		/* Get 4 bytes from the AML stream */
 
-		MOVE_UNALIGNED32_TO_32 (&arg->value.integer, parser_state->aml);
+		ACPI_MOVE_UNALIGNED32_TO_32 (&arg->value.integer, parser_state->aml);
 		parser_state->aml += 4;
 		break;
 
@@ -485,7 +485,7 @@
 
 		/* Get 8 bytes from the AML stream */
 
-		MOVE_UNALIGNED64_TO_64 (&arg->value.integer, parser_state->aml);
+		ACPI_MOVE_UNALIGNED64_TO_64 (&arg->value.integer, parser_state->aml);
 		parser_state->aml += 8;
 		break;
 
@@ -493,9 +493,9 @@
 	case ARGP_CHARLIST:
 
 		acpi_ps_init_op (arg, AML_STRING_OP);
-		arg->value.string = (char*) parser_state->aml;
+		arg->value.string = (char *) parser_state->aml;
 
-		while (GET8 (parser_state->aml) != '\0') {
+		while (ACPI_GET8 (parser_state->aml) != '\0') {
 			parser_state->aml++;
 		}
 		parser_state->aml++;
@@ -537,12 +537,12 @@
 	u32                     name;
 
 
-	FUNCTION_TRACE ("Ps_get_next_field");
+	ACPI_FUNCTION_TRACE ("Ps_get_next_field");
 
 
 	/* determine field type */
 
-	switch (GET8 (parser_state->aml)) {
+	switch (ACPI_GET8 (parser_state->aml)) {
 
 	default:
 
@@ -578,7 +578,7 @@
 
 			/* Get the 4-character name */
 
-			MOVE_UNALIGNED32_TO_32 (&name, parser_state->aml);
+			ACPI_MOVE_UNALIGNED32_TO_32 (&name, parser_state->aml);
 			acpi_ps_set_name (field, name);
 			parser_state->aml += 4;
 
@@ -598,11 +598,14 @@
 
 		case AML_INT_ACCESSFIELD_OP:
 
-			/* Get Access_type and Access_atrib and merge into the field Op */
-
-			field->value.integer = ((GET8 (parser_state->aml) << 8) |
-					  GET8 (parser_state->aml));
-			parser_state->aml += 2;
+			/*
+			 * Get Access_type and Access_attrib and merge into the field Op
+			 * Access_type is first operand, Access_attribute is second
+			 */
+			field->value.integer32 = (ACPI_GET8 (parser_state->aml) << 8);
+			parser_state->aml++;
+			field->value.integer32 |= ACPI_GET8 (parser_state->aml);
+			parser_state->aml++;
 			break;
 		}
 	}
@@ -639,7 +642,7 @@
 	u32                     subop;
 
 
-	FUNCTION_TRACE_PTR ("Ps_get_next_arg", parser_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_get_next_arg", parser_state);
 
 
 	switch (arg_type) {
@@ -717,7 +720,8 @@
 
 
 	case ARGP_TARGET:
-	case ARGP_SUPERNAME: {
+	case ARGP_SUPERNAME:
+	case ARGP_SIMPLENAME: {
 			subop = acpi_ps_peek_opcode (parser_state);
 			if (subop == 0              ||
 				acpi_ps_is_leading_char (subop) ||
diff -Nru a/drivers/acpi/parser/psopcode.c b/drivers/acpi/parser/psopcode.c
--- a/drivers/acpi/parser/psopcode.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/parser/psopcode.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: psopcode - Parser/Interpreter opcode information table
- *              $Revision: 49 $
+ *              $Revision: 64 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("psopcode")
+	 ACPI_MODULE_NAME    ("psopcode")
 
 
 #define _UNK                        0x6B
@@ -184,7 +184,7 @@
 #define ARGP_TO_STRING_OP               ARGP_LIST3 (ARGP_TERMARG,    ARGP_TERMARG,       ARGP_TARGET)
 #define ARGP_TYPE_OP                    ARGP_LIST1 (ARGP_SUPERNAME)
 #define ARGP_UNLOAD_OP                  ARGP_LIST1 (ARGP_SUPERNAME)
-#define ARGP_VAR_PACKAGE_OP             ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_BYTEDATA,      ARGP_DATAOBJLIST)
+#define ARGP_VAR_PACKAGE_OP             ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_TERMARG,       ARGP_DATAOBJLIST)
 #define ARGP_WAIT_OP                    ARGP_LIST2 (ARGP_SUPERNAME,  ARGP_TERMARG)
 #define ARGP_WHILE_OP                   ARGP_LIST3 (ARGP_PKGLENGTH,  ARGP_TERMARG,       ARGP_TERMLIST)
 #define ARGP_WORD_OP                    ARGP_LIST1 (ARGP_WORDDATA)
@@ -236,7 +236,7 @@
 #define ARGI_DATA_REGION_OP             ARGI_LIST3 (ARGI_STRING,     ARGI_STRING,       ARGI_STRING)
 #define ARGI_DEBUG_OP                   ARG_NONE
 #define ARGI_DECREMENT_OP               ARGI_LIST1 (ARGI_INTEGER_REF)
-#define ARGI_DEREF_OF_OP                ARGI_LIST1 (ARGI_REFERENCE)
+#define ARGI_DEREF_OF_OP                ARGI_LIST1 (ARGI_REF_OR_STRING)
 #define ARGI_DEVICE_OP                  ARGI_INVALID_OPCODE
 #define ARGI_DIVIDE_OP                  ARGI_LIST4 (ARGI_INTEGER,    ARGI_INTEGER,       ARGI_TARGETREF,    ARGI_TARGETREF)
 #define ARGI_DWORD_OP                   ARGI_INVALID_OPCODE
@@ -260,7 +260,7 @@
 #define ARGI_LNOT_OP                    ARGI_LIST1 (ARGI_INTEGER)
 #define ARGI_LNOTEQUAL_OP               ARGI_INVALID_OPCODE
 #define ARGI_LOAD_OP                    ARGI_LIST2 (ARGI_REGION,     ARGI_TARGETREF)
-#define ARGI_LOAD_TABLE_OP              ARGI_LIST6 (ARGI_STRING,     ARGI_STRING,        ARGI_STRING,       ARGI_STRING,    ARGI_STRING, ARGI_TARGETREF)
+#define ARGI_LOAD_TABLE_OP              ARGI_LIST6 (ARGI_STRING,     ARGI_STRING,        ARGI_STRING,       ARGI_STRING,    ARGI_STRING, ARGI_ANYTYPE)
 #define ARGI_LOCAL0                     ARG_NONE
 #define ARGI_LOCAL1                     ARG_NONE
 #define ARGI_LOCAL2                     ARG_NONE
@@ -328,7 +328,7 @@
 
 /******************************************************************************
 
- Opcodes that have associated namespace objects
+ Opcodes that have associated namespace objects (AML_NSOBJECT flag)
 
 	AML_SCOPE_OP
 	AML_DEVICE_OP
@@ -354,7 +354,7 @@
 	AML_INT_METHODCALL_OP
 	AML_INT_NAMEPATH_OP
 
-  Opcodes that are "namespace" opcodes
+  Opcodes that are "namespace" opcodes (AML_NSOPCODE flag)
 
 	AML_SCOPE_OP
 	AML_DEVICE_OP
@@ -372,7 +372,7 @@
 	AML_REGION_OP
 	AML_INT_NAMEDFIELD_OP
 
-  Opcodes that have an associated namespace node
+  Opcodes that have an associated namespace node (AML_NSNODE flag)
 
 	AML_SCOPE_OP
 	AML_DEVICE_OP
@@ -395,7 +395,7 @@
 	AML_INT_METHODCALL_OP
 	AML_INT_NAMEPATH_OP
 
-  Opcodes that define named ACPI objects
+  Opcodes that define named ACPI objects (AML_NAMED flag)
 
 	AML_SCOPE_OP
 	AML_DEVICE_OP
@@ -410,8 +410,8 @@
 	AML_REGION_OP
 	AML_INT_NAMEDFIELD_OP
 
-	Opcodes that contain executable AML as part of the definition that
-	must be deferred until needed
+  Opcodes that contain executable AML as part of the definition that
+  must be deferred until needed
 
 	AML_METHOD_OP
 	AML_VAR_PACKAGE_OP
@@ -447,146 +447,148 @@
  */
 
 
-static const acpi_opcode_info    aml_op_info[] =
+static const acpi_opcode_info    acpi_gbl_aml_op_info[] =
 {
-/* Index           Name                 Parser Args               Interpreter Args                 Class                      Type                  Flags */
+/*! [Begin] no source code translation */
+/* Index           Name                 Parser Args               Interpreter Args                ObjectType                Class                      Type                  Flags */
 
-/* 00 */ ACPI_OP ("Zero",               ARGP_ZERO_OP,              ARGI_ZERO_OP,               AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
-/* 01 */ ACPI_OP ("One",                ARGP_ONE_OP,               ARGI_ONE_OP,                AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
-/* 02 */ ACPI_OP ("Alias",              ARGP_ALIAS_OP,             ARGI_ALIAS_OP,              AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 03 */ ACPI_OP ("Name",               ARGP_NAME_OP,              ARGI_NAME_OP,               AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_COMPLEX,   AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 04 */ ACPI_OP ("Byte_const",         ARGP_BYTE_OP,              ARGI_BYTE_OP,               AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
-/* 05 */ ACPI_OP ("Word_const",         ARGP_WORD_OP,              ARGI_WORD_OP,               AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
-/* 06 */ ACPI_OP ("Dword_const",        ARGP_DWORD_OP,             ARGI_DWORD_OP,              AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
-/* 07 */ ACPI_OP ("String",             ARGP_STRING_OP,            ARGI_STRING_OP,             AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
-/* 08 */ ACPI_OP ("Scope",              ARGP_SCOPE_OP,             ARGI_SCOPE_OP,              AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_NO_OBJ,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 09 */ ACPI_OP ("Buffer",             ARGP_BUFFER_OP,            ARGI_BUFFER_OP,             AML_CLASS_ARGUMENT,        AML_TYPE_DATA_TERM,       AML_HAS_ARGS),
-/* 0A */ ACPI_OP ("Package",            ARGP_PACKAGE_OP,           ARGI_PACKAGE_OP,            AML_CLASS_ARGUMENT,        AML_TYPE_DATA_TERM,       AML_HAS_ARGS),
-/* 0B */ ACPI_OP ("Method",             ARGP_METHOD_OP,            ARGI_METHOD_OP,             AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_COMPLEX,   AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED | AML_DEFER),
-/* 0C */ ACPI_OP ("Local0",             ARGP_LOCAL0,               ARGI_LOCAL0,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 0D */ ACPI_OP ("Local1",             ARGP_LOCAL1,               ARGI_LOCAL1,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 0E */ ACPI_OP ("Local2",             ARGP_LOCAL2,               ARGI_LOCAL2,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 0F */ ACPI_OP ("Local3",             ARGP_LOCAL3,               ARGI_LOCAL3,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 10 */ ACPI_OP ("Local4",             ARGP_LOCAL4,               ARGI_LOCAL4,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 11 */ ACPI_OP ("Local5",             ARGP_LOCAL5,               ARGI_LOCAL5,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 12 */ ACPI_OP ("Local6",             ARGP_LOCAL6,               ARGI_LOCAL6,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 13 */ ACPI_OP ("Local7",             ARGP_LOCAL7,               ARGI_LOCAL7,                AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
-/* 14 */ ACPI_OP ("Arg0",               ARGP_ARG0,                 ARGI_ARG0,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 15 */ ACPI_OP ("Arg1",               ARGP_ARG1,                 ARGI_ARG1,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 16 */ ACPI_OP ("Arg2",               ARGP_ARG2,                 ARGI_ARG2,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 17 */ ACPI_OP ("Arg3",               ARGP_ARG3,                 ARGI_ARG3,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 18 */ ACPI_OP ("Arg4",               ARGP_ARG4,                 ARGI_ARG4,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 19 */ ACPI_OP ("Arg5",               ARGP_ARG5,                 ARGI_ARG5,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 1_a */ ACPI_OP ("Arg6",              ARGP_ARG6,                 ARGI_ARG6,                  AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
-/* 1_b */ ACPI_OP ("Store",             ARGP_STORE_OP,             ARGI_STORE_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 1_c */ ACPI_OP ("Ref_of",            ARGP_REF_OF_OP,            ARGI_REF_OF_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 1_d */ ACPI_OP ("Add",               ARGP_ADD_OP,               ARGI_ADD_OP,                AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 1_e */ ACPI_OP ("Concatenate",       ARGP_CONCAT_OP,            ARGI_CONCAT_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
-/* 1_f */ ACPI_OP ("Subtract",          ARGP_SUBTRACT_OP,          ARGI_SUBTRACT_OP,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 20 */ ACPI_OP ("Increment",          ARGP_INCREMENT_OP,         ARGI_INCREMENT_OP,          AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 21 */ ACPI_OP ("Decrement",          ARGP_DECREMENT_OP,         ARGI_DECREMENT_OP,          AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 22 */ ACPI_OP ("Multiply",           ARGP_MULTIPLY_OP,          ARGI_MULTIPLY_OP,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 23 */ ACPI_OP ("Divide",             ARGP_DIVIDE_OP,            ARGI_DIVIDE_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_2T_1R,   AML_FLAGS_EXEC_2A_2T_1R),
-/* 24 */ ACPI_OP ("Shift_left",         ARGP_SHIFT_LEFT_OP,        ARGI_SHIFT_LEFT_OP,         AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 25 */ ACPI_OP ("Shift_right",        ARGP_SHIFT_RIGHT_OP,       ARGI_SHIFT_RIGHT_OP,        AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 26 */ ACPI_OP ("And",                ARGP_BIT_AND_OP,           ARGI_BIT_AND_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 27 */ ACPI_OP ("NAnd",               ARGP_BIT_NAND_OP,          ARGI_BIT_NAND_OP,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 28 */ ACPI_OP ("Or",                 ARGP_BIT_OR_OP,            ARGI_BIT_OR_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 29 */ ACPI_OP ("NOr",                ARGP_BIT_NOR_OP,           ARGI_BIT_NOR_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 2_a */ ACPI_OP ("XOr",               ARGP_BIT_XOR_OP,           ARGI_BIT_XOR_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
-/* 2_b */ ACPI_OP ("Not",               ARGP_BIT_NOT_OP,           ARGI_BIT_NOT_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 2_c */ ACPI_OP ("Find_set_left_bit", ARGP_FIND_SET_LEFT_BIT_OP, ARGI_FIND_SET_LEFT_BIT_OP,  AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 2_d */ ACPI_OP ("Find_set_right_bit", ARGP_FIND_SET_RIGHT_BIT_OP,ARGI_FIND_SET_RIGHT_BIT_OP, AML_CLASS_EXECUTE,        AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 2_e */ ACPI_OP ("Deref_of",          ARGP_DEREF_OF_OP,          ARGI_DEREF_OF_OP,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 2_f */ ACPI_OP ("Notify",            ARGP_NOTIFY_OP,            ARGI_NOTIFY_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_0R,   AML_FLAGS_EXEC_2A_0T_0R),
-/* 30 */ ACPI_OP ("Size_of",            ARGP_SIZE_OF_OP,           ARGI_SIZE_OF_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 31 */ ACPI_OP ("Index",              ARGP_INDEX_OP,             ARGI_INDEX_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
-/* 32 */ ACPI_OP ("Match",              ARGP_MATCH_OP,             ARGI_MATCH_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_6A_0T_1R,   AML_FLAGS_EXEC_6A_0T_1R),
-/* 33 */ ACPI_OP ("Create_dWord_field", ARGP_CREATE_DWORD_FIELD_OP,ARGI_CREATE_DWORD_FIELD_OP, AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
-/* 34 */ ACPI_OP ("Create_word_field",  ARGP_CREATE_WORD_FIELD_OP, ARGI_CREATE_WORD_FIELD_OP,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
-/* 35 */ ACPI_OP ("Create_byte_field",  ARGP_CREATE_BYTE_FIELD_OP, ARGI_CREATE_BYTE_FIELD_OP,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
-/* 36 */ ACPI_OP ("Create_bit_field",   ARGP_CREATE_BIT_FIELD_OP,  ARGI_CREATE_BIT_FIELD_OP,   AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
-/* 37 */ ACPI_OP ("Object_type",        ARGP_TYPE_OP,              ARGI_TYPE_OP,               AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 38 */ ACPI_OP ("LAnd",               ARGP_LAND_OP,              ARGI_LAND_OP,               AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
-/* 39 */ ACPI_OP ("LOr",                ARGP_LOR_OP,               ARGI_LOR_OP,                AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
-/* 3_a */ ACPI_OP ("LNot",              ARGP_LNOT_OP,              ARGI_LNOT_OP,               AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
-/* 3_b */ ACPI_OP ("LEqual",            ARGP_LEQUAL_OP,            ARGI_LEQUAL_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
-/* 3_c */ ACPI_OP ("LGreater",          ARGP_LGREATER_OP,          ARGI_LGREATER_OP,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
-/* 3_d */ ACPI_OP ("LLess",             ARGP_LLESS_OP,             ARGI_LLESS_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
-/* 3_e */ ACPI_OP ("If",                ARGP_IF_OP,                ARGI_IF_OP,                 AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
-/* 3_f */ ACPI_OP ("Else",              ARGP_ELSE_OP,              ARGI_ELSE_OP,               AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
-/* 40 */ ACPI_OP ("While",              ARGP_WHILE_OP,             ARGI_WHILE_OP,              AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
-/* 41 */ ACPI_OP ("Noop",               ARGP_NOOP_OP,              ARGI_NOOP_OP,               AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
-/* 42 */ ACPI_OP ("Return",             ARGP_RETURN_OP,            ARGI_RETURN_OP,             AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
-/* 43 */ ACPI_OP ("Break",              ARGP_BREAK_OP,             ARGI_BREAK_OP,              AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
-/* 44 */ ACPI_OP ("Break_point",        ARGP_BREAK_POINT_OP,       ARGI_BREAK_POINT_OP,        AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
-/* 45 */ ACPI_OP ("Ones",               ARGP_ONES_OP,              ARGI_ONES_OP,               AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
+/* 00 */ ACPI_OP ("Zero",               ARGP_ZERO_OP,              ARGI_ZERO_OP,               INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
+/* 01 */ ACPI_OP ("One",                ARGP_ONE_OP,               ARGI_ONE_OP,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
+/* 02 */ ACPI_OP ("Alias",              ARGP_ALIAS_OP,             ARGI_ALIAS_OP,              INTERNAL_TYPE_ALIAS,     AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 03 */ ACPI_OP ("Name",               ARGP_NAME_OP,              ARGI_NAME_OP,               ACPI_TYPE_ANY,           AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_COMPLEX,   AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 04 */ ACPI_OP ("ByteConst",          ARGP_BYTE_OP,              ARGI_BYTE_OP,               ACPI_TYPE_INTEGER,       AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
+/* 05 */ ACPI_OP ("WordConst",          ARGP_WORD_OP,              ARGI_WORD_OP,               ACPI_TYPE_INTEGER,       AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
+/* 06 */ ACPI_OP ("DwordConst",         ARGP_DWORD_OP,             ARGI_DWORD_OP,              ACPI_TYPE_INTEGER,       AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
+/* 07 */ ACPI_OP ("String",             ARGP_STRING_OP,            ARGI_STRING_OP,             ACPI_TYPE_STRING,        AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
+/* 08 */ ACPI_OP ("Scope",              ARGP_SCOPE_OP,             ARGI_SCOPE_OP,              INTERNAL_TYPE_SCOPE,     AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_NO_OBJ,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 09 */ ACPI_OP ("Buffer",             ARGP_BUFFER_OP,            ARGI_BUFFER_OP,             ACPI_TYPE_BUFFER,        AML_CLASS_ARGUMENT,        AML_TYPE_DATA_TERM,       AML_HAS_ARGS),
+/* 0A */ ACPI_OP ("Package",            ARGP_PACKAGE_OP,           ARGI_PACKAGE_OP,            ACPI_TYPE_PACKAGE,       AML_CLASS_ARGUMENT,        AML_TYPE_DATA_TERM,       AML_HAS_ARGS),
+/* 0B */ ACPI_OP ("Method",             ARGP_METHOD_OP,            ARGI_METHOD_OP,             ACPI_TYPE_METHOD,        AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_COMPLEX,   AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED | AML_DEFER),
+/* 0C */ ACPI_OP ("Local0",             ARGP_LOCAL0,               ARGI_LOCAL0,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 0D */ ACPI_OP ("Local1",             ARGP_LOCAL1,               ARGI_LOCAL1,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 0E */ ACPI_OP ("Local2",             ARGP_LOCAL2,               ARGI_LOCAL2,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 0F */ ACPI_OP ("Local3",             ARGP_LOCAL3,               ARGI_LOCAL3,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 10 */ ACPI_OP ("Local4",             ARGP_LOCAL4,               ARGI_LOCAL4,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 11 */ ACPI_OP ("Local5",             ARGP_LOCAL5,               ARGI_LOCAL5,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 12 */ ACPI_OP ("Local6",             ARGP_LOCAL6,               ARGI_LOCAL6,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 13 */ ACPI_OP ("Local7",             ARGP_LOCAL7,               ARGI_LOCAL7,                INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LOCAL_VARIABLE,  0),
+/* 14 */ ACPI_OP ("Arg0",               ARGP_ARG0,                 ARGI_ARG0,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 15 */ ACPI_OP ("Arg1",               ARGP_ARG1,                 ARGI_ARG1,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 16 */ ACPI_OP ("Arg2",               ARGP_ARG2,                 ARGI_ARG2,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 17 */ ACPI_OP ("Arg3",               ARGP_ARG3,                 ARGI_ARG3,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 18 */ ACPI_OP ("Arg4",               ARGP_ARG4,                 ARGI_ARG4,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 19 */ ACPI_OP ("Arg5",               ARGP_ARG5,                 ARGI_ARG5,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 1A */ ACPI_OP ("Arg6",               ARGP_ARG6,                 ARGI_ARG6,                  INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_METHOD_ARGUMENT, 0),
+/* 1B */ ACPI_OP ("Store",              ARGP_STORE_OP,             ARGI_STORE_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 1C */ ACPI_OP ("RefOf",              ARGP_REF_OF_OP,            ARGI_REF_OF_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 1D */ ACPI_OP ("Add",                ARGP_ADD_OP,               ARGI_ADD_OP,                ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 1E */ ACPI_OP ("Concatenate",        ARGP_CONCAT_OP,            ARGI_CONCAT_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
+/* 1F */ ACPI_OP ("Subtract",           ARGP_SUBTRACT_OP,          ARGI_SUBTRACT_OP,           ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 20 */ ACPI_OP ("Increment",          ARGP_INCREMENT_OP,         ARGI_INCREMENT_OP,          ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 21 */ ACPI_OP ("Decrement",          ARGP_DECREMENT_OP,         ARGI_DECREMENT_OP,          ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 22 */ ACPI_OP ("Multiply",           ARGP_MULTIPLY_OP,          ARGI_MULTIPLY_OP,           ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 23 */ ACPI_OP ("Divide",             ARGP_DIVIDE_OP,            ARGI_DIVIDE_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_2T_1R,   AML_FLAGS_EXEC_2A_2T_1R),
+/* 24 */ ACPI_OP ("ShiftLeft",          ARGP_SHIFT_LEFT_OP,        ARGI_SHIFT_LEFT_OP,         ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 25 */ ACPI_OP ("ShiftRight",         ARGP_SHIFT_RIGHT_OP,       ARGI_SHIFT_RIGHT_OP,        ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 26 */ ACPI_OP ("And",                ARGP_BIT_AND_OP,           ARGI_BIT_AND_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 27 */ ACPI_OP ("NAnd",               ARGP_BIT_NAND_OP,          ARGI_BIT_NAND_OP,           ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 28 */ ACPI_OP ("Or",                 ARGP_BIT_OR_OP,            ARGI_BIT_OR_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 29 */ ACPI_OP ("NOr",                ARGP_BIT_NOR_OP,           ARGI_BIT_NOR_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 2A */ ACPI_OP ("XOr",                ARGP_BIT_XOR_OP,           ARGI_BIT_XOR_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R | AML_MATH),
+/* 2B */ ACPI_OP ("Not",                ARGP_BIT_NOT_OP,           ARGI_BIT_NOT_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 2C */ ACPI_OP ("FindSetLeftBit",     ARGP_FIND_SET_LEFT_BIT_OP, ARGI_FIND_SET_LEFT_BIT_OP,  ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 2D */ ACPI_OP ("FindSetRightBit",    ARGP_FIND_SET_RIGHT_BIT_OP,ARGI_FIND_SET_RIGHT_BIT_OP, ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 2E */ ACPI_OP ("DerefOf",            ARGP_DEREF_OF_OP,          ARGI_DEREF_OF_OP,           ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 2F */ ACPI_OP ("Notify",             ARGP_NOTIFY_OP,            ARGI_NOTIFY_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_0R,   AML_FLAGS_EXEC_2A_0T_0R),
+/* 30 */ ACPI_OP ("SizeOf",             ARGP_SIZE_OF_OP,           ARGI_SIZE_OF_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 31 */ ACPI_OP ("Index",              ARGP_INDEX_OP,             ARGI_INDEX_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
+/* 32 */ ACPI_OP ("Match",              ARGP_MATCH_OP,             ARGI_MATCH_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_6A_0T_1R,   AML_FLAGS_EXEC_6A_0T_1R),
+/* 33 */ ACPI_OP ("CreateDWordField",   ARGP_CREATE_DWORD_FIELD_OP,ARGI_CREATE_DWORD_FIELD_OP, ACPI_TYPE_BUFFER_FIELD,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
+/* 34 */ ACPI_OP ("CreateWordField",    ARGP_CREATE_WORD_FIELD_OP, ARGI_CREATE_WORD_FIELD_OP,  ACPI_TYPE_BUFFER_FIELD,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
+/* 35 */ ACPI_OP ("CreateByteField",    ARGP_CREATE_BYTE_FIELD_OP, ARGI_CREATE_BYTE_FIELD_OP,  ACPI_TYPE_BUFFER_FIELD,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
+/* 36 */ ACPI_OP ("CreateBitField",     ARGP_CREATE_BIT_FIELD_OP,  ARGI_CREATE_BIT_FIELD_OP,   ACPI_TYPE_BUFFER_FIELD,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
+/* 37 */ ACPI_OP ("ObjectType",         ARGP_TYPE_OP,              ARGI_TYPE_OP,               ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 38 */ ACPI_OP ("LAnd",               ARGP_LAND_OP,              ARGI_LAND_OP,               ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
+/* 39 */ ACPI_OP ("LOr",                ARGP_LOR_OP,               ARGI_LOR_OP,                ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
+/* 3A */ ACPI_OP ("LNot",               ARGP_LNOT_OP,              ARGI_LNOT_OP,               ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_1R,   AML_FLAGS_EXEC_1A_0T_1R),
+/* 3B */ ACPI_OP ("LEqual",             ARGP_LEQUAL_OP,            ARGI_LEQUAL_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
+/* 3C */ ACPI_OP ("LGreater",           ARGP_LGREATER_OP,          ARGI_LGREATER_OP,           ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
+/* 3D */ ACPI_OP ("LLess",              ARGP_LLESS_OP,             ARGI_LLESS_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R | AML_LOGICAL),
+/* 3E */ ACPI_OP ("If",                 ARGP_IF_OP,                ARGI_IF_OP,                 ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
+/* 3F */ ACPI_OP ("Else",               ARGP_ELSE_OP,              ARGI_ELSE_OP,               ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
+/* 40 */ ACPI_OP ("While",              ARGP_WHILE_OP,             ARGI_WHILE_OP,              ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
+/* 41 */ ACPI_OP ("Noop",               ARGP_NOOP_OP,              ARGI_NOOP_OP,               ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
+/* 42 */ ACPI_OP ("Return",             ARGP_RETURN_OP,            ARGI_RETURN_OP,             ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         AML_HAS_ARGS),
+/* 43 */ ACPI_OP ("Break",              ARGP_BREAK_OP,             ARGI_BREAK_OP,              ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
+/* 44 */ ACPI_OP ("BreakPoint",         ARGP_BREAK_POINT_OP,       ARGI_BREAK_POINT_OP,        ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
+/* 45 */ ACPI_OP ("Ones",               ARGP_ONES_OP,              ARGI_ONES_OP,               INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
 
 /* Prefixed opcodes (Two-byte opcodes with a prefix op) */
 
-/* 46 */ ACPI_OP ("Mutex",              ARGP_MUTEX_OP,             ARGI_MUTEX_OP,              AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 47 */ ACPI_OP ("Event",              ARGP_EVENT_OP,             ARGI_EVENT_OP,              AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED ),
-/* 48 */ ACPI_OP ("Cond_ref_of",        ARGP_COND_REF_OF_OP,       ARGI_COND_REF_OF_OP,        AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 49 */ ACPI_OP ("Create_field",       ARGP_CREATE_FIELD_OP,      ARGI_CREATE_FIELD_OP,       AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_FIELD | AML_CREATE),
-/* 4_a */ ACPI_OP ("Load",              ARGP_LOAD_OP,              ARGI_LOAD_OP,               AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_0R,   AML_FLAGS_EXEC_1A_1T_0R),
-/* 4_b */ ACPI_OP ("Stall",             ARGP_STALL_OP,             ARGI_STALL_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
-/* 4_c */ ACPI_OP ("Sleep",             ARGP_SLEEP_OP,             ARGI_SLEEP_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
-/* 4_d */ ACPI_OP ("Acquire",           ARGP_ACQUIRE_OP,           ARGI_ACQUIRE_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R),
-/* 4_e */ ACPI_OP ("Signal",            ARGP_SIGNAL_OP,            ARGI_SIGNAL_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
-/* 4_f */ ACPI_OP ("Wait",              ARGP_WAIT_OP,              ARGI_WAIT_OP,               AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R),
-/* 50 */ ACPI_OP ("Reset",              ARGP_RESET_OP,             ARGI_RESET_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
-/* 51 */ ACPI_OP ("Release",            ARGP_RELEASE_OP,           ARGI_RELEASE_OP,            AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
-/* 52 */ ACPI_OP ("From_bCD",           ARGP_FROM_BCD_OP,          ARGI_FROM_BCD_OP,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 53 */ ACPI_OP ("To_bCD",             ARGP_TO_BCD_OP,            ARGI_TO_BCD_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 54 */ ACPI_OP ("Unload",             ARGP_UNLOAD_OP,            ARGI_UNLOAD_OP,             AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
-/* 55 */ ACPI_OP ("Revision",           ARGP_REVISION_OP,          ARGI_REVISION_OP,           AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
-/* 56 */ ACPI_OP ("Debug",              ARGP_DEBUG_OP,             ARGI_DEBUG_OP,              AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
-/* 57 */ ACPI_OP ("Fatal",              ARGP_FATAL_OP,             ARGI_FATAL_OP,              AML_CLASS_EXECUTE,         AML_TYPE_EXEC_3A_0T_0R,   AML_FLAGS_EXEC_3A_0T_0R),
-/* 58 */ ACPI_OP ("Op_region",          ARGP_REGION_OP,            ARGI_REGION_OP,             AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_COMPLEX,   AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED | AML_DEFER),
-/* 59 */ ACPI_OP ("Field",              ARGP_FIELD_OP,             ARGI_FIELD_OP,              AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_FIELD,     AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_FIELD),
-/* 5_a */ ACPI_OP ("Device",            ARGP_DEVICE_OP,            ARGI_DEVICE_OP,             AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_NO_OBJ,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 5_b */ ACPI_OP ("Processor",         ARGP_PROCESSOR_OP,         ARGI_PROCESSOR_OP,          AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 5_c */ ACPI_OP ("Power_resource",    ARGP_POWER_RES_OP,         ARGI_POWER_RES_OP,          AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 5_d */ ACPI_OP ("Thermal_zone",      ARGP_THERMAL_ZONE_OP,      ARGI_THERMAL_ZONE_OP,       AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_NO_OBJ,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
-/* 5_e */ ACPI_OP ("Index_field",       ARGP_INDEX_FIELD_OP,       ARGI_INDEX_FIELD_OP,        AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_FIELD,     AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_FIELD),
-/* 5_f */ ACPI_OP ("Bank_field",        ARGP_BANK_FIELD_OP,        ARGI_BANK_FIELD_OP,         AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_FIELD,     AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_FIELD),
+/* 46 */ ACPI_OP ("Mutex",              ARGP_MUTEX_OP,             ARGI_MUTEX_OP,              ACPI_TYPE_MUTEX,         AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 47 */ ACPI_OP ("Event",              ARGP_EVENT_OP,             ARGI_EVENT_OP,              ACPI_TYPE_EVENT,         AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED ),
+/* 48 */ ACPI_OP ("CondRefOf",          ARGP_COND_REF_OF_OP,       ARGI_COND_REF_OF_OP,        ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 49 */ ACPI_OP ("CreateField",        ARGP_CREATE_FIELD_OP,      ARGI_CREATE_FIELD_OP,       ACPI_TYPE_BUFFER_FIELD,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_FIELD | AML_CREATE),
+/* 4A */ ACPI_OP ("Load",               ARGP_LOAD_OP,              ARGI_LOAD_OP,               ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_0R,   AML_FLAGS_EXEC_1A_1T_0R),
+/* 4B */ ACPI_OP ("Stall",              ARGP_STALL_OP,             ARGI_STALL_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
+/* 4C */ ACPI_OP ("Sleep",              ARGP_SLEEP_OP,             ARGI_SLEEP_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
+/* 4D */ ACPI_OP ("Acquire",            ARGP_ACQUIRE_OP,           ARGI_ACQUIRE_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R),
+/* 4E */ ACPI_OP ("Signal",             ARGP_SIGNAL_OP,            ARGI_SIGNAL_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
+/* 4F */ ACPI_OP ("Wait",               ARGP_WAIT_OP,              ARGI_WAIT_OP,               ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_0T_1R,   AML_FLAGS_EXEC_2A_0T_1R),
+/* 50 */ ACPI_OP ("Reset",              ARGP_RESET_OP,             ARGI_RESET_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
+/* 51 */ ACPI_OP ("Release",            ARGP_RELEASE_OP,           ARGI_RELEASE_OP,            ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
+/* 52 */ ACPI_OP ("FromBCD",            ARGP_FROM_BCD_OP,          ARGI_FROM_BCD_OP,           ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 53 */ ACPI_OP ("ToBCD",              ARGP_TO_BCD_OP,            ARGI_TO_BCD_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 54 */ ACPI_OP ("Unload",             ARGP_UNLOAD_OP,            ARGI_UNLOAD_OP,             ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_0T_0R,   AML_FLAGS_EXEC_1A_0T_0R),
+/* 55 */ ACPI_OP ("Revision",           ARGP_REVISION_OP,          ARGI_REVISION_OP,           INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
+/* 56 */ ACPI_OP ("Debug",              ARGP_DEBUG_OP,             ARGI_DEBUG_OP,              INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_CONSTANT,        0),
+/* 57 */ ACPI_OP ("Fatal",              ARGP_FATAL_OP,             ARGI_FATAL_OP,              ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_3A_0T_0R,   AML_FLAGS_EXEC_3A_0T_0R),
+/* 58 */ ACPI_OP ("OperationRegion",    ARGP_REGION_OP,            ARGI_REGION_OP,             ACPI_TYPE_REGION,        AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_COMPLEX,   AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED | AML_DEFER),
+/* 59 */ ACPI_OP ("Field",              ARGP_FIELD_OP,             ARGI_FIELD_OP,              INTERNAL_TYPE_FIELD_DEFN,AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_FIELD,     AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_FIELD),
+/* 5A */ ACPI_OP ("Device",             ARGP_DEVICE_OP,            ARGI_DEVICE_OP,             ACPI_TYPE_DEVICE,        AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_NO_OBJ,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 5B */ ACPI_OP ("Processor",          ARGP_PROCESSOR_OP,         ARGI_PROCESSOR_OP,          ACPI_TYPE_PROCESSOR,     AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 5C */ ACPI_OP ("PowerResource",      ARGP_POWER_RES_OP,         ARGI_POWER_RES_OP,          ACPI_TYPE_POWER,         AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 5D */ ACPI_OP ("ThermalZone",        ARGP_THERMAL_ZONE_OP,      ARGI_THERMAL_ZONE_OP,       ACPI_TYPE_THERMAL,       AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_NO_OBJ,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
+/* 5E */ ACPI_OP ("IndexField",         ARGP_INDEX_FIELD_OP,       ARGI_INDEX_FIELD_OP,        INTERNAL_TYPE_INDEX_FIELD_DEFN,AML_CLASS_NAMED_OBJECT, AML_TYPE_NAMED_FIELD,  AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_FIELD),
+/* 5F */ ACPI_OP ("BankField",          ARGP_BANK_FIELD_OP,        ARGI_BANK_FIELD_OP,         INTERNAL_TYPE_BANK_FIELD_DEFN,AML_CLASS_NAMED_OBJECT,  AML_TYPE_NAMED_FIELD,  AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_FIELD),
 
 /* Internal opcodes that map to invalid AML opcodes */
 
-/* 60 */ ACPI_OP ("LNot_equal",         ARGP_LNOTEQUAL_OP,         ARGI_LNOTEQUAL_OP,          AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_HAS_ARGS),
-/* 61 */ ACPI_OP ("LLess_equal",        ARGP_LLESSEQUAL_OP,        ARGI_LLESSEQUAL_OP,         AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_HAS_ARGS),
-/* 62 */ ACPI_OP ("LGreater_equal",     ARGP_LGREATEREQUAL_OP,     ARGI_LGREATEREQUAL_OP,      AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_HAS_ARGS),
-/* 63 */ ACPI_OP ("[Name_path]",        ARGP_NAMEPATH_OP,          ARGI_NAMEPATH_OP,           AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         AML_NSOBJECT | AML_NSNODE ),
-/* 64 */ ACPI_OP ("[Method_call]",      ARGP_METHODCALL_OP,        ARGI_METHODCALL_OP,         AML_CLASS_METHOD_CALL,     AML_TYPE_METHOD_CALL,     AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE),
-/* 65 */ ACPI_OP ("[Byte_list]",        ARGP_BYTELIST_OP,          ARGI_BYTELIST_OP,           AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
-/* 66 */ ACPI_OP ("[Reserved_field]",   ARGP_RESERVEDFIELD_OP,     ARGI_RESERVEDFIELD_OP,      AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           0),
-/* 67 */ ACPI_OP ("[Named_field]",      ARGP_NAMEDFIELD_OP,        ARGI_NAMEDFIELD_OP,         AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED ),
-/* 68 */ ACPI_OP ("[Access_field]",     ARGP_ACCESSFIELD_OP,       ARGI_ACCESSFIELD_OP,        AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           0),
-/* 69 */ ACPI_OP ("[Static_string",     ARGP_STATICSTRING_OP,      ARGI_STATICSTRING_OP,       AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           0),
-/* 6_a */ ACPI_OP ("[Return Value]",    ARG_NONE,                  ARG_NONE,                   AML_CLASS_RETURN_VALUE,    AML_TYPE_RETURN,          AML_HAS_ARGS | AML_HAS_RETVAL),
-/* 6_b */ ACPI_OP ("UNKNOWN_OP!",       ARG_NONE,                  ARG_NONE,                   AML_CLASS_UNKNOWN,         AML_TYPE_BOGUS,           AML_HAS_ARGS),
-/* 6_c */ ACPI_OP ("ASCII_ONLY!",       ARG_NONE,                  ARG_NONE,                   AML_CLASS_ASCII,           AML_TYPE_BOGUS,           AML_HAS_ARGS),
-/* 6_d */ ACPI_OP ("PREFIX_ONLY!",      ARG_NONE,                  ARG_NONE,                   AML_CLASS_PREFIX,          AML_TYPE_BOGUS,           AML_HAS_ARGS),
+/* 60 */ ACPI_OP ("LNotEqual",          ARGP_LNOTEQUAL_OP,         ARGI_LNOTEQUAL_OP,          ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_HAS_ARGS),
+/* 61 */ ACPI_OP ("LLessEqual",         ARGP_LLESSEQUAL_OP,        ARGI_LLESSEQUAL_OP,         ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_HAS_ARGS),
+/* 62 */ ACPI_OP ("LGreaterEqual",      ARGP_LGREATEREQUAL_OP,     ARGI_LGREATEREQUAL_OP,      ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_HAS_ARGS),
+/* 63 */ ACPI_OP ("[NamePath]",         ARGP_NAMEPATH_OP,          ARGI_NAMEPATH_OP,           INTERNAL_TYPE_REFERENCE, AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         AML_NSOBJECT | AML_NSNODE ),
+/* 64 */ ACPI_OP ("[MethodCall]",       ARGP_METHODCALL_OP,        ARGI_METHODCALL_OP,         ACPI_TYPE_METHOD,        AML_CLASS_METHOD_CALL,     AML_TYPE_METHOD_CALL,     AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE),
+/* 65 */ ACPI_OP ("[ByteList]",         ARGP_BYTELIST_OP,          ARGI_BYTELIST_OP,           ACPI_TYPE_ANY,           AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
+/* 66 */ ACPI_OP ("[ReservedField]",    ARGP_RESERVEDFIELD_OP,     ARGI_RESERVEDFIELD_OP,      ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           0),
+/* 67 */ ACPI_OP ("[NamedField]",       ARGP_NAMEDFIELD_OP,        ARGI_NAMEDFIELD_OP,         ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED ),
+/* 68 */ ACPI_OP ("[AccessField]",      ARGP_ACCESSFIELD_OP,       ARGI_ACCESSFIELD_OP,        ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           0),
+/* 69 */ ACPI_OP ("[StaticString",      ARGP_STATICSTRING_OP,      ARGI_STATICSTRING_OP,       ACPI_TYPE_ANY,           AML_CLASS_INTERNAL,        AML_TYPE_BOGUS,           0),
+/* 6A */ ACPI_OP ("[Return Value]",     ARG_NONE,                  ARG_NONE,                   ACPI_TYPE_ANY,           AML_CLASS_RETURN_VALUE,    AML_TYPE_RETURN,          AML_HAS_ARGS | AML_HAS_RETVAL),
+/* 6B */ ACPI_OP ("UNKNOWN_OP!",        ARG_NONE,                  ARG_NONE,                   INTERNAL_TYPE_INVALID,   AML_CLASS_UNKNOWN,         AML_TYPE_BOGUS,           AML_HAS_ARGS),
+/* 6C */ ACPI_OP ("ASCII_ONLY!",        ARG_NONE,                  ARG_NONE,                   ACPI_TYPE_ANY,           AML_CLASS_ASCII,           AML_TYPE_BOGUS,           AML_HAS_ARGS),
+/* 6D */ ACPI_OP ("PREFIX_ONLY!",       ARG_NONE,                  ARG_NONE,                   ACPI_TYPE_ANY,           AML_CLASS_PREFIX,          AML_TYPE_BOGUS,           AML_HAS_ARGS),
 
 
 /* ACPI 2.0 opcodes */
 
-/* 6_e */ ACPI_OP ("Qword_const",       ARGP_QWORD_OP,             ARGI_QWORD_OP,              AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
-/* 6_f */ ACPI_OP ("Var_package",       ARGP_VAR_PACKAGE_OP,       ARGI_VAR_PACKAGE_OP,        AML_CLASS_ARGUMENT,        AML_TYPE_DATA_TERM,       AML_HAS_ARGS | AML_DEFER),
-/* 70 */ ACPI_OP ("Concat_res",         ARGP_CONCAT_RES_OP,        ARGI_CONCAT_RES_OP,         AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
-/* 71 */ ACPI_OP ("Mod",                ARGP_MOD_OP,               ARGI_MOD_OP,                AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
-/* 72 */ ACPI_OP ("Create_qWord_field", ARGP_CREATE_QWORD_FIELD_OP,ARGI_CREATE_QWORD_FIELD_OP, AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
-/* 73 */ ACPI_OP ("To_buffer",          ARGP_TO_BUFFER_OP,         ARGI_TO_BUFFER_OP,          AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 74 */ ACPI_OP ("To_decimal_string",  ARGP_TO_DEC_STR_OP,        ARGI_TO_DEC_STR_OP,         AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 75 */ ACPI_OP ("To_hex_string",      ARGP_TO_HEX_STR_OP,        ARGI_TO_HEX_STR_OP,         AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 76 */ ACPI_OP ("To_integer",         ARGP_TO_INTEGER_OP,        ARGI_TO_INTEGER_OP,         AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 77 */ ACPI_OP ("To_string",          ARGP_TO_STRING_OP,         ARGI_TO_STRING_OP,          AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
-/* 78 */ ACPI_OP ("Copy_object",        ARGP_COPY_OP,              ARGI_COPY_OP,               AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
-/* 79 */ ACPI_OP ("Mid",                ARGP_MID_OP,               ARGI_MID_OP,                AML_CLASS_EXECUTE,         AML_TYPE_EXEC_3A_1T_1R,   AML_FLAGS_EXEC_3A_1T_1R),
-/* 7_a */ ACPI_OP ("Continue",          ARGP_CONTINUE_OP,          ARGI_CONTINUE_OP,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
-/* 7_b */ ACPI_OP ("Load_table",        ARGP_LOAD_TABLE_OP,        ARGI_LOAD_TABLE_OP,         AML_CLASS_EXECUTE,         AML_TYPE_EXEC_6A_0T_1R,   AML_FLAGS_EXEC_6A_0T_1R),
-/* 7_c */ ACPI_OP ("Data_op_region",    ARGP_DATA_REGION_OP,       ARGI_DATA_REGION_OP,        AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 6E */ ACPI_OP ("QwordConst",         ARGP_QWORD_OP,             ARGI_QWORD_OP,              ACPI_TYPE_INTEGER,       AML_CLASS_ARGUMENT,        AML_TYPE_LITERAL,         0),
+/* 6F */ ACPI_OP ("Package /*Var*/",    ARGP_VAR_PACKAGE_OP,       ARGI_VAR_PACKAGE_OP,        ACPI_TYPE_PACKAGE,       AML_CLASS_ARGUMENT,        AML_TYPE_DATA_TERM,       AML_HAS_ARGS | AML_DEFER),
+/* 70 */ ACPI_OP ("ConcatenateResTemplate", ARGP_CONCAT_RES_OP,    ARGI_CONCAT_RES_OP,         ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
+/* 71 */ ACPI_OP ("Mod",                ARGP_MOD_OP,               ARGI_MOD_OP,                ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
+/* 72 */ ACPI_OP ("CreateQWordField",   ARGP_CREATE_QWORD_FIELD_OP,ARGI_CREATE_QWORD_FIELD_OP, ACPI_TYPE_BUFFER_FIELD,  AML_CLASS_CREATE,          AML_TYPE_CREATE_FIELD,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSNODE | AML_DEFER | AML_CREATE),
+/* 73 */ ACPI_OP ("ToBuffer",           ARGP_TO_BUFFER_OP,         ARGI_TO_BUFFER_OP,          ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 74 */ ACPI_OP ("ToDecimalString",    ARGP_TO_DEC_STR_OP,        ARGI_TO_DEC_STR_OP,         ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 75 */ ACPI_OP ("ToHexString",        ARGP_TO_HEX_STR_OP,        ARGI_TO_HEX_STR_OP,         ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 76 */ ACPI_OP ("ToInteger",          ARGP_TO_INTEGER_OP,        ARGI_TO_INTEGER_OP,         ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 77 */ ACPI_OP ("ToString",           ARGP_TO_STRING_OP,         ARGI_TO_STRING_OP,          ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_2A_1T_1R,   AML_FLAGS_EXEC_2A_1T_1R),
+/* 78 */ ACPI_OP ("CopyObject",         ARGP_COPY_OP,              ARGI_COPY_OP,               ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_1A_1T_1R,   AML_FLAGS_EXEC_1A_1T_1R),
+/* 79 */ ACPI_OP ("Mid",                ARGP_MID_OP,               ARGI_MID_OP,                ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_3A_1T_1R,   AML_FLAGS_EXEC_3A_1T_1R),
+/* 7A */ ACPI_OP ("Continue",           ARGP_CONTINUE_OP,          ARGI_CONTINUE_OP,           ACPI_TYPE_ANY,           AML_CLASS_CONTROL,         AML_TYPE_CONTROL,         0),
+/* 7B */ ACPI_OP ("LoadTable",          ARGP_LOAD_TABLE_OP,        ARGI_LOAD_TABLE_OP,         ACPI_TYPE_ANY,           AML_CLASS_EXECUTE,         AML_TYPE_EXEC_6A_0T_1R,   AML_FLAGS_EXEC_6A_0T_1R),
+/* 7C */ ACPI_OP ("DataTableRegion",    ARGP_DATA_REGION_OP,       ARGI_DATA_REGION_OP,        ACPI_TYPE_REGION,        AML_CLASS_NAMED_OBJECT,    AML_TYPE_NAMED_SIMPLE,    AML_HAS_ARGS | AML_NSOBJECT | AML_NSOPCODE | AML_NSNODE | AML_NAMED),
 
+/*! [End] no source code translation !*/
 };
 
 /*
@@ -594,7 +596,7 @@
  * index into the table above
  */
 
-static const u8 aml_short_op_info_index[256] =
+static const u8 acpi_gbl_short_op_index[256] =
 {
 /*              0     1     2     3     4     5     6     7  */
 /*              8     9     A     B     C     D     E     F  */
@@ -633,7 +635,7 @@
 };
 
 
-static const u8 aml_long_op_info_index[NUM_EXTENDED_OPCODE] =
+static const u8 acpi_gbl_long_op_index[NUM_EXTENDED_OPCODE] =
 {
 /*              0     1     2     3     4     5     6     7  */
 /*              8     9     A     B     C     D     E     F  */
@@ -676,57 +678,39 @@
 acpi_ps_get_opcode_info (
 	u16                     opcode)
 {
-	const acpi_opcode_info  *op_info;
-	u8                      upper_opcode;
-	u8                      lower_opcode;
-
-
-	PROC_NAME ("Ps_get_opcode_info");
-
-
-	/* Split the 16-bit opcode into separate bytes */
-
-	upper_opcode = (u8) (opcode >> 8);
-	lower_opcode = (u8) opcode;
-
-	/* Default is "unknown opcode" */
-
-	op_info = &aml_op_info [_UNK];
+	ACPI_FUNCTION_NAME ("Ps_get_opcode_info");
 
 
 	/*
 	 * Detect normal 8-bit opcode or extended 16-bit opcode
 	 */
-
-	switch (upper_opcode) {
+	switch ((u8) (opcode >> 8)) {
 	case 0:
 
 		/* Simple (8-bit) opcode: 0-255, can't index beyond table  */
 
-		op_info = &aml_op_info [aml_short_op_info_index [lower_opcode]];
-		break;
-
+		return (&acpi_gbl_aml_op_info [acpi_gbl_short_op_index [(u8) opcode]]);
 
 	case AML_EXTOP:
 
 		/* Extended (16-bit, prefix+opcode) opcode */
 
-		if (lower_opcode <= MAX_EXTENDED_OPCODE) {
-			op_info = &aml_op_info [aml_long_op_info_index [lower_opcode]];
+		if (((u8) opcode) <= MAX_EXTENDED_OPCODE) {
+			return (&acpi_gbl_aml_op_info [acpi_gbl_long_op_index [(u8) opcode]]);
 		}
-		break;
 
+		/* Else fall through to error case below */
 
 	default:
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown extended opcode=%X\n", opcode));
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Unknown extended opcode [%X]\n", opcode));
 		break;
 	}
 
 
-	/* Get the Op info pointer for this opcode */
+	/* Default is "unknown opcode" */
 
-	return (op_info);
+	return (&acpi_gbl_aml_op_info [_UNK]);
 }
 
 
@@ -747,6 +731,8 @@
 acpi_ps_get_opcode_name (
 	u16                     opcode)
 {
+#ifdef ACPI_DEBUG
+
 	const acpi_opcode_info  *op;
 
 
@@ -754,10 +740,11 @@
 
 	/* Always guaranteed to return a valid pointer */
 
-#ifdef ACPI_DEBUG
 	return (op->name);
+
 #else
 	return ("AE_NOT_CONFIGURED");
+
 #endif
 }
 
diff -Nru a/drivers/acpi/parser/psparse.c b/drivers/acpi/parser/psparse.c
--- a/drivers/acpi/parser/psparse.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/parser/psparse.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: psparse - Parser top level AML parse routines
- *              $Revision: 104 $
+ *              $Revision: 119 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -42,7 +42,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("psparse")
+	 ACPI_MODULE_NAME    ("psparse")
 
 
 u32                         acpi_gbl_depth = 0;
@@ -61,7 +61,7 @@
  *
  ******************************************************************************/
 
-static u32
+u32
 acpi_ps_get_opcode_size (
 	u32                     opcode)
 {
@@ -99,32 +99,16 @@
 
 
 	aml = parser_state->aml;
-	opcode = (u16) GET8 (aml);
+	opcode = (u16) ACPI_GET8 (aml);
 
-	aml++;
 
-
-	/*
-	 * Original code special cased LNOTEQUAL, LLESSEQUAL, LGREATEREQUAL.
-	 * These opcodes are no longer recognized. Instead, they are broken into
-	 * two opcodes.
-	 *
-	 *
-	 *    if (Opcode == AML_EXTOP
-	 *       || (Opcode == AML_LNOT
-	 *          && (GET8 (Aml) == AML_LEQUAL
-	 *               || GET8 (Aml) == AML_LGREATER
-	 *               || GET8 (Aml) == AML_LLESS)))
-	 *
-	 *     extended Opcode, !=, <=, or >=
-	 */
 	if (opcode == AML_EXTOP) {
 		/* Extended opcode */
 
-		opcode = (u16) ((opcode << 8) | GET8 (aml));
+		aml++;
+		opcode = (u16) ((opcode << 8) | ACPI_GET8 (aml));
 	}
 
-
 	return (opcode);
 }
 
@@ -194,7 +178,7 @@
  *
  ******************************************************************************/
 
-static u8
+u8
 acpi_ps_complete_this_op (
 	acpi_walk_state         *walk_state,
 	acpi_parse_object       *op)
@@ -206,8 +190,14 @@
 	acpi_parse_object       *replacement_op = NULL;
 
 
-	FUNCTION_TRACE_PTR ("Ps_complete_this_op", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_complete_this_op", op);
+
 
+	/* Check for null Op, can happen if AML code is corrupt */
+
+	if (!op) {
+		return_VALUE (TRUE);
+	}
 
 	/* Delete this op and the subtree below it if asked to */
 
@@ -223,29 +213,34 @@
 			parent_info = acpi_ps_get_opcode_info (op->parent->opcode);
 
 			switch (parent_info->class) {
-			case AML_CLASS_CONTROL:        /* IF, ELSE, WHILE only */
+			case AML_CLASS_CONTROL:
 				break;
 
-			case AML_CLASS_NAMED_OBJECT:   /* Scope, method, etc. */
 			case AML_CLASS_CREATE:
 
 				/*
 				 * These opcodes contain Term_arg operands. The current
 				 * op must be replace by a placeholder return op
 				 */
+				replacement_op = acpi_ps_alloc_op (AML_INT_RETURN_VALUE_OP);
+				if (!replacement_op) {
+					return_VALUE (FALSE);
+				}
+				break;
+
+			case AML_CLASS_NAMED_OBJECT:
+
+				/*
+				 * These opcodes contain Term_arg operands. The current
+				 * op must be replace by a placeholder return op
+				 */
 				if ((op->parent->opcode == AML_REGION_OP)               ||
-					(op->parent->opcode == AML_CREATE_FIELD_OP)         ||
-					(op->parent->opcode == AML_CREATE_BIT_FIELD_OP)     ||
-					(op->parent->opcode == AML_CREATE_BYTE_FIELD_OP)    ||
-					(op->parent->opcode == AML_CREATE_WORD_FIELD_OP)    ||
-					(op->parent->opcode == AML_CREATE_DWORD_FIELD_OP)   ||
-					(op->parent->opcode == AML_CREATE_QWORD_FIELD_OP)) {
+					(op->parent->opcode == AML_DATA_REGION_OP)) {
 					replacement_op = acpi_ps_alloc_op (AML_INT_RETURN_VALUE_OP);
 					if (!replacement_op) {
 						return_VALUE (FALSE);
 					}
 				}
-
 				break;
 
 			default:
@@ -294,7 +289,6 @@
 
 				prev = next;
 			}
-
 		}
 
 		/* Now we can actually delete the subtree rooted at op */
@@ -324,7 +318,7 @@
  *
  ******************************************************************************/
 
-static acpi_status
+acpi_status
 acpi_ps_next_parse_state (
 	acpi_walk_state         *walk_state,
 	acpi_parse_object       *op,
@@ -332,11 +326,9 @@
 {
 	acpi_parse_state        *parser_state = &walk_state->parser_state;
 	acpi_status             status = AE_CTRL_PENDING;
-	u8                      *start;
-	u32                     package_length;
 
 
-	FUNCTION_TRACE_PTR ("Ps_next_parse_state", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_next_parse_state", op);
 
 
 	switch (callback_status) {
@@ -351,32 +343,33 @@
 		break;
 
 
-	case AE_CTRL_PENDING:
+	case AE_CTRL_BREAK:
 
-		/*
-		 * Predicate of a WHILE was true and the loop just completed an
-		 * execution.  Go back to the start of the loop and reevaluate the
-		 * predicate.
-		 */
+		parser_state->aml = walk_state->aml_last_while;
+		walk_state->control_state->common.value = FALSE;
+		status = AE_CTRL_BREAK;
+		break;
+
+	case AE_CTRL_CONTINUE:
 
-		/* TBD: How to handle a break within a while. */
-		/* This code attempts it */
+
+		parser_state->aml = walk_state->aml_last_while;
+		status = AE_CTRL_CONTINUE;
+		break;
+
+	case AE_CTRL_PENDING:
 
 		parser_state->aml = walk_state->aml_last_while;
 		break;
 
 
 	case AE_CTRL_TRUE:
+
 		/*
 		 * Predicate of an IF was true, and we are at the matching ELSE.
 		 * Just close out this package
-		 *
-		 * Note: Parser_state->Aml is modified by the package length procedure
-		 * TBD: [Investigate] perhaps it shouldn't, too much trouble
 		 */
-		start = parser_state->aml;
-		package_length = acpi_ps_get_next_package_length (parser_state);
-		parser_state->aml = start + package_length;
+		parser_state->aml = acpi_ps_get_next_package_end (parser_state);
 		break;
 
 
@@ -451,14 +444,14 @@
 	u8                      *aml_op_start;
 
 
-	FUNCTION_TRACE_PTR ("Ps_parse_loop", walk_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_parse_loop", walk_state);
 
 
 	parser_state = &walk_state->parser_state;
 	walk_state->arg_types = 0;
 
 #ifndef PARSER_ONLY
-	if (walk_state->walk_type & WALK_METHOD_RESTART) {
+	if (walk_state->walk_type & ACPI_WALK_METHOD_RESTART) {
 		/* We are restarting a preempted control method */
 
 		if (acpi_ps_has_completed_scope (parser_state)) {
@@ -471,14 +464,14 @@
 				(parser_state->scope->parse_scope.op->opcode == AML_WHILE_OP)) &&
 				(walk_state->control_state) &&
 				(walk_state->control_state->common.state ==
-					CONTROL_PREDICATE_EXECUTING)) {
+					ACPI_CONTROL_PREDICATE_EXECUTING)) {
 
 				/*
 				 * A predicate was just completed, get the value of the
 				 * predicate and branch based on that value
 				 */
 				walk_state->op = NULL;
-				status = acpi_ds_get_predicate_value (walk_state, TRUE);
+				status = acpi_ds_get_predicate_value (walk_state, ACPI_TO_POINTER (TRUE));
 				if (ACPI_FAILURE (status) &&
 					((status & AE_CODE_MASK) != AE_CODE_CONTROL)) {
 					if (status == AE_AML_NO_RETURN_VALUE) {
@@ -545,7 +538,7 @@
 					"Found unknown opcode %X at AML offset %X, ignoring\n",
 					walk_state->opcode, walk_state->aml_offset));
 
-				DUMP_BUFFER (parser_state->aml, 128);
+				ACPI_DUMP_BUFFER (parser_state->aml, 128);
 
 				/* Assume one-byte bad opcode */
 
@@ -590,9 +583,6 @@
 					walk_state->op = NULL;
 
 					status = walk_state->descending_callback (walk_state, &op);
-
-					/* TBD: check status here? */
-
 					if (ACPI_FAILURE (status)) {
 						ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "During name lookup/catalog, %s\n",
 								acpi_format_exception (status)));
@@ -602,6 +592,7 @@
 					if (op == NULL) {
 						continue;
 					}
+
 					status = acpi_ps_next_parse_state (walk_state, op, status);
 					if (status == AE_CTRL_PENDING) {
 						status = AE_OK;
@@ -616,7 +607,6 @@
 				acpi_ps_append_arg (op, pre_op.value.arg);
 				acpi_gbl_depth++;
 
-
 				if (op->opcode == AML_REGION_OP) {
 					/*
 					 * Defer final parsing of an Operation_region body,
@@ -635,7 +625,6 @@
 				}
 			}
 
-
 			else {
 				/* Not a named opcode, just allocate Op and append to parent */
 
@@ -645,7 +634,6 @@
 					return_ACPI_STATUS (AE_NO_MEMORY);
 				}
 
-
 				if (walk_state->op_info->flags & AML_CREATE) {
 					/*
 					 * Backup to beginning of Create_xXXfield declaration
@@ -662,7 +650,7 @@
 					 * Find the object.  This will either insert the object into
 					 * the namespace or simply look it up
 					 */
-					walk_state->op    = op;
+					walk_state->op = op;
 
 					status = walk_state->descending_callback (walk_state, &op);
 					status = acpi_ps_next_parse_state (walk_state, op, status);
@@ -681,8 +669,8 @@
 
 			if (walk_state->op_info) {
 				ACPI_DEBUG_PRINT ((ACPI_DB_PARSE,
-					"Op=%p Opcode=%4.4X Aml %p Oft=%5.5X\n",
-					 op, op->opcode, parser_state->aml, op->aml_offset));
+					"Opcode %4.4X [%s] Op %p Aml %p Aml_offset %5.5X\n",
+					 op->opcode, walk_state->op_info->name, op, parser_state->aml, op->aml_offset));
 			}
 		}
 
@@ -691,7 +679,6 @@
 
 		walk_state->arg_count = 0;
 
-
 		if (walk_state->arg_types) /* Are there any arguments that must be processed? */ {
 			/* get arguments */
 
@@ -732,7 +719,6 @@
 					INCREMENT_ARG_LIST (walk_state->arg_types);
 				}
 
-
 				/* For a method, save the length and address of the body */
 
 				if (op->opcode == AML_METHOD_OP) {
@@ -741,9 +727,9 @@
 					 * because we don't have enough info in the first pass
 					 * to parse them correctly.
 					 */
-					((acpi_parse2_object * ) op)->data    = parser_state->aml;
-					((acpi_parse2_object * ) op)->length  = (u32) (parser_state->pkg_end -
-							   parser_state->aml);
+					((acpi_parse2_object * ) op)->data   = parser_state->aml;
+					((acpi_parse2_object * ) op)->length = (u32) (parser_state->pkg_end -
+							  parser_state->aml);
 
 					/*
 					 * Skip body of method.  For Op_regions, we must continue
@@ -751,166 +737,193 @@
 					 * package (We don't know where the end is).
 					 */
 					parser_state->aml   = parser_state->pkg_end;
-					walk_state->arg_count          = 0;
+					walk_state->arg_count = 0;
+				}
+				else if (op->opcode == AML_WHILE_OP) {
+					if (walk_state->control_state) {
+						walk_state->control_state->control.package_end = parser_state->pkg_end;
+					}
 				}
-
 				break;
 			}
 		}
 
 
-		/*
-		 * Zero Arg_count means that all arguments for this op have been processed
-		 */
-		if (!walk_state->arg_count) {
-			/* completed Op, prepare for next */
+		/* Check for arguments that need to be processed */
 
-			walk_state->op_info = acpi_ps_get_opcode_info (op->opcode);
-			if (walk_state->op_info->flags & AML_NAMED) {
-				if (acpi_gbl_depth) {
-					acpi_gbl_depth--;
-				}
+		if (walk_state->arg_count) {
+			/* There are arguments (complex ones), push Op and prepare for argument */
 
-				if (op->opcode == AML_REGION_OP) {
-					/*
-					 * Skip parsing of control method or opregion body,
-					 * because we don't have enough info in the first pass
-					 * to parse them correctly.
-					 *
-					 * Completed parsing an Op_region declaration, we now
-					 * know the length.
-					 */
-					((acpi_parse2_object * ) op)->length = (u32) (parser_state->aml -
-							   ((acpi_parse2_object * ) op)->data);
-				}
+			acpi_ps_push_scope (parser_state, op, walk_state->arg_types, walk_state->arg_count);
+			op = NULL;
+			continue;
+		}
+
+
+		/* All arguments have been processed -- Op is complete, prepare for next */
+
+		walk_state->op_info = acpi_ps_get_opcode_info (op->opcode);
+		if (walk_state->op_info->flags & AML_NAMED) {
+			if (acpi_gbl_depth) {
+				acpi_gbl_depth--;
 			}
 
-			if (walk_state->op_info->flags & AML_CREATE) {
+			if (op->opcode == AML_REGION_OP) {
 				/*
-				 * Backup to beginning of Create_xXXfield declaration (1 for
-				 * Opcode)
+				 * Skip parsing of control method or opregion body,
+				 * because we don't have enough info in the first pass
+				 * to parse them correctly.
 				 *
-				 * Body_length is unknown until we parse the body
+				 * Completed parsing an Op_region declaration, we now
+				 * know the length.
 				 */
 				((acpi_parse2_object * ) op)->length = (u32) (parser_state->aml -
 						   ((acpi_parse2_object * ) op)->data);
 			}
+		}
 
-			/* This op complete, notify the dispatcher */
+		if (walk_state->op_info->flags & AML_CREATE) {
+			/*
+			 * Backup to beginning of Create_xXXfield declaration (1 for
+			 * Opcode)
+			 *
+			 * Body_length is unknown until we parse the body
+			 */
+			((acpi_parse2_object * ) op)->length = (u32) (parser_state->aml -
+					   ((acpi_parse2_object * ) op)->data);
+		}
 
-			if (walk_state->ascending_callback != NULL) {
-				walk_state->op    = op;
-				walk_state->opcode = op->opcode;
+		/* This op complete, notify the dispatcher */
 
-				status = walk_state->ascending_callback (walk_state);
-				status = acpi_ps_next_parse_state (walk_state, op, status);
-				if (status == AE_CTRL_PENDING) {
-					status = AE_OK;
-					goto close_this_op;
-				}
+		if (walk_state->ascending_callback != NULL) {
+			walk_state->op    = op;
+			walk_state->opcode = op->opcode;
+
+			status = walk_state->ascending_callback (walk_state);
+			status = acpi_ps_next_parse_state (walk_state, op, status);
+			if (status == AE_CTRL_PENDING) {
+				status = AE_OK;
+				goto close_this_op;
 			}
+		}
 
 
 close_this_op:
+		/*
+		 * Finished one argument of the containing scope
+		 */
+		parser_state->scope->parse_scope.arg_count--;
+
+		/* Close this Op (may result in parse subtree deletion) */
+
+		if (acpi_ps_complete_this_op (walk_state, op)) {
+			op = NULL;
+		}
+
+		switch (status) {
+		case AE_OK:
+			break;
+
+
+		case AE_CTRL_TRANSFER:
 
 			/*
-			 * Finished one argument of the containing scope
+			 * We are about to transfer to a called method.
 			 */
-			parser_state->scope->parse_scope.arg_count--;
+			walk_state->prev_op = op;
+			walk_state->prev_arg_types = walk_state->arg_types;
+			return_ACPI_STATUS (status);
 
-			/* Close this Op (may result in parse subtree deletion) */
 
-			if (acpi_ps_complete_this_op (walk_state, op)) {
-				op = NULL;
-			}
+		case AE_CTRL_END:
 
+			acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
 
-			switch (status) {
-			case AE_OK:
-				break;
+			walk_state->op    = op;
+			walk_state->op_info = acpi_ps_get_opcode_info (op->opcode);
+			walk_state->opcode = op->opcode;
 
+			status = walk_state->ascending_callback (walk_state);
+			status = acpi_ps_next_parse_state (walk_state, op, status);
 
-			case AE_CTRL_TRANSFER:
+			acpi_ps_complete_this_op (walk_state, op);
+			op = NULL;
+			status = AE_OK;
+			break;
 
-				/*
-				 * We are about to transfer to a called method.
-				 */
-				walk_state->prev_op = op;
-				walk_state->prev_arg_types = walk_state->arg_types;
-				return_ACPI_STATUS (status);
-				break;
 
+		case AE_CTRL_BREAK:
+		case AE_CTRL_CONTINUE:
 
-			case AE_CTRL_END:
+			/* Pop off scopes until we find the While */
 
+			while (!op || (op->opcode != AML_WHILE_OP)) {
 				acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
+			}
 
-				walk_state->op    = op;
-				walk_state->op_info = acpi_ps_get_opcode_info (op->opcode);
-				walk_state->opcode = op->opcode;
+			/* Close this iteration of the While loop */
 
-				status = walk_state->ascending_callback (walk_state);
-				status = acpi_ps_next_parse_state (walk_state, op, status);
+			walk_state->op    = op;
+			walk_state->op_info = acpi_ps_get_opcode_info (op->opcode);
+			walk_state->opcode = op->opcode;
 
-				acpi_ps_complete_this_op (walk_state, op);
-				op = NULL;
-				status = AE_OK;
-				break;
+			status = walk_state->ascending_callback (walk_state);
+			status = acpi_ps_next_parse_state (walk_state, op, status);
 
+			acpi_ps_complete_this_op (walk_state, op);
+			op = NULL;
 
-			case AE_CTRL_TERMINATE:
+			status = AE_OK;
+			break;
 
-				status = AE_OK;
 
-				/* Clean up */
-				do {
-					if (op) {
-						acpi_ps_complete_this_op (walk_state, op);
-					}
+		case AE_CTRL_TERMINATE:
 
-					acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
-				} while (op);
+			status = AE_OK;
 
-				return_ACPI_STATUS (status);
-				break;
+			/* Clean up */
+			do {
+				if (op) {
+					acpi_ps_complete_this_op (walk_state, op);
+				}
+				acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
 
+			} while (op);
 
-			default:  /* All other non-AE_OK status */
+			return_ACPI_STATUS (status);
 
-				if (op == NULL) {
-					acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
-				}
-				walk_state->prev_op = op;
-				walk_state->prev_arg_types = walk_state->arg_types;
 
-				/*
-				 * TEMP:
-				 */
+		default:  /* All other non-AE_OK status */
 
-				return_ACPI_STATUS (status);
-				break;
-			}
+			do {
+				if (op) {
+					acpi_ps_complete_this_op (walk_state, op);
+				}
+				acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
 
-			/* This scope complete? */
+			} while (op);
 
-			if (acpi_ps_has_completed_scope (parser_state)) {
-				acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
-				ACPI_DEBUG_PRINT ((ACPI_DB_PARSE, "Popped scope, Op=%p\n", op));
-			}
 
-			else {
-				op = NULL;
+			/*
+			 * TBD: Cleanup parse ops on error
+			 */
+#if 0
+			if (op == NULL) {
+				acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
 			}
-
+#endif
+			walk_state->prev_op = op;
+			walk_state->prev_arg_types = walk_state->arg_types;
+			return_ACPI_STATUS (status);
 		}
 
+		/* This scope complete? */
 
-		/* Arg_count is non-zero */
-
+		if (acpi_ps_has_completed_scope (parser_state)) {
+			acpi_ps_pop_scope (parser_state, &op, &walk_state->arg_types, &walk_state->arg_count);
+			ACPI_DEBUG_PRINT ((ACPI_DB_PARSE, "Popped scope, Op=%p\n", op));
+		}
 		else {
-			/* complex argument, push Op and prepare for argument */
-
-			acpi_ps_push_scope (parser_state, op, walk_state->arg_types, walk_state->arg_count);
 			op = NULL;
 		}
 
@@ -992,30 +1005,32 @@
 	acpi_walk_state         *walk_state)
 {
 	acpi_status             status;
-	acpi_walk_list          walk_list;
-	acpi_walk_list          *prev_walk_list = acpi_gbl_current_walk_list;
+	ACPI_THREAD_STATE       *thread;
+	ACPI_THREAD_STATE       *prev_walk_list = acpi_gbl_current_walk_list;
 	acpi_walk_state         *previous_walk_state;
 
 
-	FUNCTION_TRACE ("Ps_parse_aml");
+	ACPI_FUNCTION_TRACE ("Ps_parse_aml");
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_PARSE, "Entered with Walk_state=%p Aml=%p size=%X\n",
 		walk_state, walk_state->parser_state.aml, walk_state->parser_state.aml_size));
 
 
-	/* Create and initialize a new walk list */
+	/* Create and initialize a new thread state */
 
-	walk_list.walk_state            = NULL;
-	walk_list.acquired_mutex_list.prev = NULL;
-	walk_list.acquired_mutex_list.next = NULL;
-
-	walk_state->walk_list = &walk_list;
-	acpi_ds_push_walk_state (walk_state, &walk_list);
+	thread = acpi_ut_create_thread_state ();
+	if (!thread) {
+		return_ACPI_STATUS (AE_NO_MEMORY);
+	}
 
+	walk_state->thread = thread;
+	acpi_ds_push_walk_state (walk_state, thread);
 
-	/* TBD: [Restructure] TEMP until we pass Walk_state to the interpreter
+	/*
+	 * This global allows the AML debugger to get a handle to the currently
+	 * executing control method.
 	 */
-	acpi_gbl_current_walk_list = &walk_list;
+	acpi_gbl_current_walk_list = thread;
 
 	/*
 	 * Execute the walk loop as long as there is a valid Walk State.  This
@@ -1041,13 +1056,13 @@
 			 * A method call was detected.
 			 * Transfer control to the called control method
 			 */
-			status = acpi_ds_call_control_method (&walk_list, walk_state, NULL);
+			status = acpi_ds_call_control_method (thread, walk_state, NULL);
 
 			/*
 			 * If the transfer to the new method method call worked, a new walk
 			 * state was created -- get it
 			 */
-			walk_state = acpi_ds_get_current_walk_state (&walk_list);
+			walk_state = acpi_ds_get_current_walk_state (thread);
 			continue;
 		}
 
@@ -1057,7 +1072,7 @@
 
 		/* We are done with this walk, move on to the parent if any */
 
-		walk_state = acpi_ds_pop_walk_state (&walk_list);
+		walk_state = acpi_ds_pop_walk_state (thread);
 
 		/* Reset the current scope to the beginning of scope stack */
 
@@ -1082,17 +1097,25 @@
 
 		/* Check if we have restarted a preempted walk */
 
-		walk_state = acpi_ds_get_current_walk_state (&walk_list);
+		walk_state = acpi_ds_get_current_walk_state (thread);
 		if (walk_state) {
 			if (ACPI_SUCCESS (status)) {
-				/* There is another walk state, restart it */
-
 				/*
-				 * If the method returned value is not used by the parent,
+				 * There is another walk state, restart it.
+				 * If the method return value is not used by the parent,
 				 * The object is deleted
 				 */
 				acpi_ds_restart_control_method (walk_state, previous_walk_state->return_desc);
-				walk_state->walk_type |= WALK_METHOD_RESTART;
+				walk_state->walk_type |= ACPI_WALK_METHOD_RESTART;
+			}
+			else {
+				/* On error, delete any return object */
+
+				acpi_ut_remove_reference (previous_walk_state->return_desc);
+
+				ACPI_REPORT_ERROR (("Method execution failed, %s\n", acpi_format_exception (status)));
+				ACPI_DUMP_PATHNAME (walk_state->method_node, "Method pathname: ",
+					ACPI_LV_ERROR, _COMPONENT);
 			}
 		}
 
@@ -1113,10 +1136,10 @@
 		acpi_ds_delete_walk_state (previous_walk_state);
 	}
 
-
 	/* Normal exit */
 
-	acpi_ex_release_all_mutexes ((acpi_operand_object *) &walk_list.acquired_mutex_list);
+	acpi_ex_release_all_mutexes (thread);
+	acpi_ut_delete_generic_state ((acpi_generic_state *) thread);
 	acpi_gbl_current_walk_list = prev_walk_list;
 	return_ACPI_STATUS (status);
 }
diff -Nru a/drivers/acpi/parser/psscope.c b/drivers/acpi/parser/psscope.c
--- a/drivers/acpi/parser/psscope.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/parser/psscope.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: psscope - Parser scope stack management routines
- *              $Revision: 30 $
+ *              $Revision: 35 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acparser.h"
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("psscope")
+	 ACPI_MODULE_NAME    ("psscope")
 
 
 /*******************************************************************************
@@ -95,7 +95,7 @@
 	acpi_generic_state      *scope;
 
 
-	FUNCTION_TRACE_PTR ("Ps_init_scope", root_op);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_init_scope", root_op);
 
 
 	scope = acpi_ut_create_generic_state ();
@@ -141,12 +141,12 @@
 	acpi_generic_state      *scope;
 
 
-	FUNCTION_TRACE_PTR ("Ps_push_scope", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_push_scope", op);
 
 
 	scope = acpi_ut_create_generic_state ();
 	if (!scope) {
-		return (AE_NO_MEMORY);
+		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
 
@@ -170,7 +170,7 @@
 	else {
 		/* single argument */
 
-		scope->parse_scope.arg_end = ACPI_MAX_AML;
+		scope->parse_scope.arg_end = ACPI_TO_POINTER (ACPI_MAX_PTR);
 	}
 
 	return_ACPI_STATUS (AE_OK);
@@ -203,7 +203,7 @@
 	acpi_generic_state      *scope = parser_state->scope;
 
 
-	FUNCTION_TRACE ("Ps_pop_scope");
+	ACPI_FUNCTION_TRACE ("Ps_pop_scope");
 
 
 	/*
@@ -257,7 +257,7 @@
 {
 	acpi_generic_state      *scope;
 
-	FUNCTION_TRACE_PTR ("Ps_cleanup_scope", parser_state);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_cleanup_scope", parser_state);
 
 
 	if (!parser_state) {
diff -Nru a/drivers/acpi/parser/pstree.c b/drivers/acpi/parser/pstree.c
--- a/drivers/acpi/parser/pstree.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/parser/pstree.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: pstree - Parser op tree manipulation/traversal/search
- *              $Revision: 35 $
+ *              $Revision: 37 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -29,7 +29,7 @@
 #include "amlcode.h"
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("pstree")
+	 ACPI_MODULE_NAME    ("pstree")
 
 
 /*******************************************************************************
@@ -54,7 +54,7 @@
 	const acpi_opcode_info  *op_info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* Get the info structure for this opcode */
@@ -108,7 +108,7 @@
 	const acpi_opcode_info  *op_info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (!op) {
@@ -121,7 +121,7 @@
 	if (op_info->class == AML_CLASS_UNKNOWN) {
 		/* Invalid opcode */
 
-		REPORT_ERROR (("Ps_append_arg: Invalid AML Opcode: 0x%2.2X\n", op->opcode));
+		ACPI_REPORT_ERROR (("Ps_append_arg: Invalid AML Opcode: 0x%2.2X\n", op->opcode));
 		return;
 	}
 
@@ -181,7 +181,7 @@
 	acpi_parse_object       *child = NULL;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	switch (op->opcode) {
@@ -249,7 +249,7 @@
 	acpi_parse_object       *arg;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (!op) {
diff -Nru a/drivers/acpi/parser/psutils.c b/drivers/acpi/parser/psutils.c
--- a/drivers/acpi/parser/psutils.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/parser/psutils.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: psutils - Parser miscellaneous utilities (Parser only)
- *              $Revision: 44 $
+ *              $Revision: 49 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -29,14 +29,7 @@
 #include "amlcode.h"
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("psutils")
-
-
-#define PARSEOP_GENERIC     0x01
-#define PARSEOP_NAMED       0x02
-#define PARSEOP_DEFERRED    0x04
-#define PARSEOP_BYTELIST    0x08
-#define PARSEOP_IN_CACHE    0x80
+	 ACPI_MODULE_NAME    ("psutils")
 
 
 /*******************************************************************************
@@ -58,19 +51,14 @@
 	acpi_parse_object       *op,
 	u16                     opcode)
 {
-	const acpi_opcode_info  *aml_op;
-
-
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	op->data_type = ACPI_DESC_TYPE_PARSER;
 	op->opcode = opcode;
 
-	aml_op = acpi_ps_get_opcode_info (opcode);
-
-	DEBUG_ONLY_MEMBERS (STRNCPY (op->op_name, aml_op->name,
-			   sizeof (op->op_name)));
+	ACPI_DEBUG_ONLY_MEMBERS (ACPI_STRNCPY (op->op_name,
+			(acpi_ps_get_opcode_info (opcode))->name, sizeof (op->op_name)));
 }
 
 
@@ -98,7 +86,7 @@
 	const acpi_opcode_info  *op_info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	op_info = acpi_ps_get_opcode_info (opcode);
@@ -107,22 +95,22 @@
 
 	if (op_info->flags & AML_DEFER) {
 		size = sizeof (acpi_parse2_object);
-		flags = PARSEOP_DEFERRED;
+		flags = ACPI_PARSEOP_DEFERRED;
 	}
 
 	else if (op_info->flags & AML_NAMED) {
 		size = sizeof (acpi_parse2_object);
-		flags = PARSEOP_NAMED;
+		flags = ACPI_PARSEOP_NAMED;
 	}
 
 	else if (opcode == AML_INT_BYTELIST_OP) {
 		size = sizeof (acpi_parse2_object);
-		flags = PARSEOP_BYTELIST;
+		flags = ACPI_PARSEOP_BYTELIST;
 	}
 
 	else {
 		size = sizeof (acpi_parse_object);
-		flags = PARSEOP_GENERIC;
+		flags = ACPI_PARSEOP_GENERIC;
 	}
 
 
@@ -165,14 +153,14 @@
 acpi_ps_free_op (
 	acpi_parse_object       *op)
 {
-	PROC_NAME ("Ps_free_op");
+	ACPI_FUNCTION_NAME ("Ps_free_op");
 
 
 	if (op->opcode == AML_INT_RETURN_VALUE_OP) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Free retval op: %p\n", op));
 	}
 
-	if (op->flags == PARSEOP_GENERIC) {
+	if (op->flags == ACPI_PARSEOP_GENERIC) {
 		acpi_ut_release_to_cache (ACPI_MEM_LIST_PSNODE, op);
 	}
 
@@ -198,7 +186,7 @@
 acpi_ps_delete_parse_cache (
 	void)
 {
-	FUNCTION_TRACE ("Ps_delete_parse_cache");
+	ACPI_FUNCTION_TRACE ("Ps_delete_parse_cache");
 
 
 	acpi_ut_delete_generic_cache (ACPI_MEM_LIST_PSNODE);
@@ -249,7 +237,7 @@
 
 	/* The "generic" object has no name associated with it */
 
-	if (op->flags & PARSEOP_GENERIC) {
+	if (op->flags & ACPI_PARSEOP_GENERIC) {
 		return (0);
 	}
 
@@ -270,7 +258,7 @@
 
 	/* The "generic" object has no name associated with it */
 
-	if (op->flags & PARSEOP_GENERIC) {
+	if (op->flags & ACPI_PARSEOP_GENERIC) {
 		return;
 	}
 
diff -Nru a/drivers/acpi/parser/pswalk.c b/drivers/acpi/parser/pswalk.c
--- a/drivers/acpi/parser/pswalk.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/parser/pswalk.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: pswalk - Parser routines to walk parsed op tree(s)
- *              $Revision: 58 $
+ *              $Revision: 63 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 #include "acinterp.h"
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("pswalk")
+	 ACPI_MODULE_NAME    ("pswalk")
 
 
 /*******************************************************************************
@@ -61,12 +61,12 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_PTR ("Ps_get_next_walk_op", op);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_get_next_walk_op", op);
 
 
 	/* Check for a argument only if we are descending in the tree */
 
-	if (walk_state->next_op_info != NEXT_OP_UPWARD) {
+	if (walk_state->next_op_info != ACPI_NEXT_OP_UPWARD) {
 		/* Look for an argument or child of the current op */
 
 		next = acpi_ps_get_arg (op, 0);
@@ -75,12 +75,11 @@
 
 			walk_state->prev_op     = op;
 			walk_state->next_op     = next;
-			walk_state->next_op_info = NEXT_OP_DOWNWARD;
+			walk_state->next_op_info = ACPI_NEXT_OP_DOWNWARD;
 
 			return_ACPI_STATUS (AE_OK);
 		}
 
-
 		/*
 		 * No more children, this Op is complete.  Save Next and Parent
 		 * in case the Op object gets deleted by the callback routine
@@ -115,7 +114,7 @@
 
 			walk_state->prev_op     = op;
 			walk_state->next_op     = next;
-			walk_state->next_op_info = NEXT_OP_DOWNWARD;
+			walk_state->next_op_info = ACPI_NEXT_OP_DOWNWARD;
 
 			/* Continue downward */
 
@@ -127,7 +126,6 @@
 		 * the tree
 		 */
 	}
-
 	else {
 		/*
 		 * We are resuming a walk, and we were (are) going upward in the tree.
@@ -136,7 +134,6 @@
 		parent = op;
 	}
 
-
 	/*
 	 * Look for a sibling of the current Op's parent
 	 * Continue moving up the tree until we find a node that has not been
@@ -175,7 +172,7 @@
 
 			walk_state->prev_op     = parent;
 			walk_state->next_op     = next;
-			walk_state->next_op_info = NEXT_OP_DOWNWARD;
+			walk_state->next_op_info = ACPI_NEXT_OP_DOWNWARD;
 
 			return_ACPI_STATUS (status);
 		}
@@ -188,9 +185,10 @@
 	}
 
 
-	/* Got all the way to the top of the tree, we must be done! */
-	/* However, the code should have terminated in the loop above */
-
+	/*
+	 * Got all the way to the top of the tree, we must be done!
+	 * However, the code should have terminated in the loop above
+	 */
 	walk_state->next_op     = NULL;
 
 	return_ACPI_STATUS (AE_OK);
@@ -212,7 +210,7 @@
  *
  ******************************************************************************/
 
-static acpi_status
+acpi_status
 acpi_ps_delete_completed_op (
 	acpi_walk_state         *walk_state)
 {
@@ -239,10 +237,10 @@
 	acpi_parse_object       *subtree_root)
 {
 	acpi_walk_state         *walk_state;
-	acpi_walk_list          walk_list;
+	ACPI_THREAD_STATE       *thread;
 
 
-	FUNCTION_TRACE_PTR ("Ps_delete_parse_tree", subtree_root);
+	ACPI_FUNCTION_TRACE_PTR ("Ps_delete_parse_tree", subtree_root);
 
 
 	if (!subtree_root) {
@@ -251,11 +249,13 @@
 
 	/* Create and initialize a new walk list */
 
-	walk_list.walk_state = NULL;
-	walk_list.acquired_mutex_list.prev = NULL;
-	walk_list.acquired_mutex_list.next = NULL;
+	thread = acpi_ut_create_thread_state ();
+	if (!thread) {
+		return_VOID;
+	}
+
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT, NULL, NULL, &walk_list);
+	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT, NULL, NULL, thread);
 	if (!walk_state) {
 		return_VOID;
 	}
@@ -264,14 +264,12 @@
 	walk_state->descending_callback = NULL;
 	walk_state->ascending_callback  = NULL;
 
-
 	walk_state->origin = subtree_root;
 	walk_state->next_op = subtree_root;
 
-
 	/* Head downward in the tree */
 
-	walk_state->next_op_info = NEXT_OP_DOWNWARD;
+	walk_state->next_op_info = ACPI_NEXT_OP_DOWNWARD;
 
 	/* Visit all nodes in the subtree */
 
@@ -282,7 +280,7 @@
 
 	/* We are done with this walk */
 
-	acpi_ex_release_all_mutexes ((acpi_operand_object *) &walk_list.acquired_mutex_list);
+	acpi_ut_delete_generic_state ((acpi_generic_state *) thread);
 	acpi_ds_delete_walk_state (walk_state);
 
 	return_VOID;
diff -Nru a/drivers/acpi/parser/psxface.c b/drivers/acpi/parser/psxface.c
--- a/drivers/acpi/parser/psxface.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/parser/psxface.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: psxface - Parser external interfaces
- *              $Revision: 52 $
+ *              $Revision: 59 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_PARSER
-	 MODULE_NAME         ("psxface")
+	 ACPI_MODULE_NAME    ("psxface")
 
 
 /*******************************************************************************
@@ -67,7 +67,7 @@
 	acpi_walk_state         *walk_state;
 
 
-	FUNCTION_TRACE ("Psx_execute");
+	ACPI_FUNCTION_TRACE ("Psx_execute");
 
 
 	/* Validate the Node and get the attached object */
@@ -113,9 +113,16 @@
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
+	/*
+	 * Get a new Owner_id for objects created by this method. Namespace
+	 * objects (such as Operation Regions) can be created during the
+	 * first pass parse.
+	 */
+	obj_desc->method.owning_id = acpi_ut_allocate_owner_id (ACPI_OWNER_TYPE_METHOD);
+
 	/* Create and initialize a new walk state */
 
-	walk_state = acpi_ds_create_walk_state (TABLE_ID_DSDT,
+	walk_state = acpi_ds_create_walk_state (obj_desc->method.owning_id,
 			   NULL, NULL, NULL);
 	if (!walk_state) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
@@ -124,7 +131,7 @@
 	status = acpi_ds_init_aml_walk (walk_state, op, method_node, obj_desc->method.aml_start,
 			  obj_desc->method.aml_length, NULL, NULL, 1);
 	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
+		acpi_ds_delete_walk_state (walk_state);
 		return_ACPI_STATUS (status);
 	}
 
@@ -164,7 +171,7 @@
 	status = acpi_ds_init_aml_walk (walk_state, op, method_node, obj_desc->method.aml_start,
 			  obj_desc->method.aml_length, params, return_obj_desc, 3);
 	if (ACPI_FAILURE (status)) {
-		/* TBD: delete walk state */
+		acpi_ds_delete_walk_state (walk_state);
 		return_ACPI_STATUS (status);
 	}
 
@@ -182,13 +189,6 @@
 		}
 	}
 
-
-	if (ACPI_FAILURE (status)) {
-		DUMP_PATHNAME (method_node, "Ps_execute: method failed -",
-			ACPI_LV_ERROR, _COMPONENT);
-	}
-
-
 	/*
 	 * If the method has returned an object, signal this to the caller with
 	 * a control exception code
@@ -196,11 +196,10 @@
 	if (*return_obj_desc) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Method returned Obj_desc=%p\n",
 			*return_obj_desc));
-		DUMP_STACK_ENTRY (*return_obj_desc);
+		ACPI_DUMP_STACK_ENTRY (*return_obj_desc);
 
 		status = AE_CTRL_RETURN_VALUE;
 	}
-
 
 	return_ACPI_STATUS (status);
 }
diff -Nru a/drivers/acpi/resources/Makefile b/drivers/acpi/resources/Makefile
--- a/drivers/acpi/resources/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/resources/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/resources/rsaddr.c b/drivers/acpi/resources/rsaddr.c
--- a/drivers/acpi/resources/rsaddr.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/acpi/resources/rsaddr.c	Fri Mar 15 17:51:00 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsaddr - Address resource descriptors (16/32/64)
- *              $Revision: 19 $
+ *              $Revision: 24 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsaddr")
+	 ACPI_MODULE_NAME    ("rsaddr")
 
 
 /*******************************************************************************
@@ -37,13 +37,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -56,26 +55,26 @@
 acpi_status
 acpi_rs_address16_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	NATIVE_CHAR             *temp_ptr;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_address16);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_address16);
 	u32                     index;
 	u16                     temp16;
 	u8                      temp8;
 
 
-	FUNCTION_TRACE ("Rs_address16_resource");
+	ACPI_FUNCTION_TRACE ("Rs_address16_resource");
 
 	/*
 	 * Point past the Descriptor to get the number of bytes consumed
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	*bytes_consumed = temp16 + 3;
 	output_struct->id = ACPI_RSTYPE_ADDRESS16;
@@ -87,6 +86,7 @@
 	temp8 = *buffer;
 
 	/* Values 0-2 are valid */
+
 	if (temp8 > 2) {
 		return_ACPI_STATUS (AE_AML_INVALID_RESOURCE_TYPE);
 	}
@@ -99,24 +99,20 @@
 	buffer += 1;
 	temp8 = *buffer;
 
-	/*
-	 * Producer / Consumer
-	 */
+	/* Producer / Consumer */
+
 	output_struct->data.address16.producer_consumer = temp8 & 0x01;
 
-	/*
-	 * Decode
-	 */
+	/* Decode */
+
 	output_struct->data.address16.decode = (temp8 >> 1) & 0x01;
 
-	/*
-	 * Min Address Fixed
-	 */
+	/* Min Address Fixed */
+
 	output_struct->data.address16.min_address_fixed = (temp8 >> 2) & 0x01;
 
-	/*
-	 * Max Address Fixed
-	 */
+	/* Max Address Fixed */
+
 	output_struct->data.address16.max_address_fixed = (temp8 >> 3) & 0x01;
 
 	/*
@@ -125,19 +121,17 @@
 	buffer += 1;
 	temp8 = *buffer;
 
-	if (MEMORY_RANGE == output_struct->data.address16.resource_type) {
+	if (ACPI_MEMORY_RANGE == output_struct->data.address16.resource_type) {
 		output_struct->data.address16.attribute.memory.read_write_attribute =
 				(u16) (temp8 & 0x01);
 		output_struct->data.address16.attribute.memory.cache_attribute =
 				(u16) ((temp8 >> 1) & 0x0F);
 	}
-
 	else {
-		if (IO_RANGE == output_struct->data.address16.resource_type) {
+		if (ACPI_IO_RANGE == output_struct->data.address16.resource_type) {
 			output_struct->data.address16.attribute.io.range_attribute =
 				(u16) (temp8 & 0x03);
 		}
-
 		else {
 			/* BUS_NUMBER_RANGE == Address16.Data->Resource_type */
 			/* Nothing needs to be filled in */
@@ -148,35 +142,35 @@
 	 * Get Granularity (Bytes 6-7)
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.granularity,
+	ACPI_MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.granularity,
 			 buffer);
 
 	/*
 	 * Get Min_address_range (Bytes 8-9)
 	 */
 	buffer += 2;
-	MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.min_address_range,
+	ACPI_MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.min_address_range,
 			 buffer);
 
 	/*
 	 * Get Max_address_range (Bytes 10-11)
 	 */
 	buffer += 2;
-	MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.max_address_range,
+	ACPI_MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.max_address_range,
 			 buffer);
 
 	/*
 	 * Get Address_translation_offset (Bytes 12-13)
 	 */
 	buffer += 2;
-	MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.address_translation_offset,
+	ACPI_MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.address_translation_offset,
 			 buffer);
 
 	/*
 	 * Get Address_length (Bytes 14-15)
 	 */
 	buffer += 2;
-	MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.address_length,
+	ACPI_MOVE_UNALIGNED16_TO_16 (&output_struct->data.address16.address_length,
 			 buffer);
 
 	/*
@@ -233,9 +227,8 @@
 		 * Struct_size to the next 32-bit boundary.
 		 */
 		temp8 = (u8) (index + 1);
-		struct_size += ROUND_UP_TO_32_bITS (temp8);
+		struct_size += ACPI_ROUND_UP_TO_32_bITS (temp8);
 	}
-
 	else {
 		output_struct->data.address16.resource_source.index = 0x00;
 		output_struct->data.address16.resource_source.string_length = 0;
@@ -261,9 +254,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -276,16 +268,16 @@
 acpi_rs_address16_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u8                      *length_field;
 	u8                      temp8;
 	NATIVE_CHAR             *temp_pointer = NULL;
-	u32                     actual_bytes;
+	ACPI_SIZE               actual_bytes;
 
 
-	FUNCTION_TRACE ("Rs_address16_stream");
+	ACPI_FUNCTION_TRACE ("Rs_address16_stream");
 
 
 	/*
@@ -324,7 +316,7 @@
 	 */
 	temp8 = 0;
 
-	if (MEMORY_RANGE == linked_list->data.address16.resource_type) {
+	if (ACPI_MEMORY_RANGE == linked_list->data.address16.resource_type) {
 		temp8 = (u8)
 			(linked_list->data.address16.attribute.memory.read_write_attribute &
 			 0x01);
@@ -333,8 +325,7 @@
 			(linked_list->data.address16.attribute.memory.cache_attribute &
 			 0x0F) << 1;
 	}
-
-	else if (IO_RANGE == linked_list->data.address16.resource_type) {
+	else if (ACPI_IO_RANGE == linked_list->data.address16.resource_type) {
 		temp8 = (u8)
 			(linked_list->data.address16.attribute.io.range_attribute &
 			 0x03);
@@ -346,35 +337,35 @@
 	/*
 	 * Set the address space granularity
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer,
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer,
 			   &linked_list->data.address16.granularity);
 	buffer += 2;
 
 	/*
 	 * Set the address range minimum
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer,
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer,
 			   &linked_list->data.address16.min_address_range);
 	buffer += 2;
 
 	/*
 	 * Set the address range maximum
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer,
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer,
 			   &linked_list->data.address16.max_address_range);
 	buffer += 2;
 
 	/*
 	 * Set the address translation offset
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer,
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer,
 			   &linked_list->data.address16.address_translation_offset);
 	buffer += 2;
 
 	/*
 	 * Set the address length
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer,
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer,
 			   &linked_list->data.address16.address_length);
 	buffer += 2;
 
@@ -392,21 +383,21 @@
 		/*
 		 * Copy the string
 		 */
-		STRCPY (temp_pointer,
+		ACPI_STRCPY (temp_pointer,
 				linked_list->data.address16.resource_source.string_ptr);
 
 		/*
 		 * Buffer needs to be set to the length of the sting + one for the
 		 *  terminating null
 		 */
-		buffer += (STRLEN (linked_list->data.address16.resource_source.string_ptr)
+		buffer += (ACPI_STRLEN (linked_list->data.address16.resource_source.string_ptr)
 				 + 1);
 	}
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	actual_bytes = POINTER_DIFF (buffer, *output_buffer);
+	actual_bytes = ACPI_PTR_DIFF (buffer, *output_buffer);
 	*bytes_consumed = actual_bytes;
 
 	/*
@@ -414,7 +405,7 @@
 	 * minus the header size (3 bytes)
 	 */
 	actual_bytes -= 3;
-	MOVE_UNALIGNED16_TO_16 (length_field, &actual_bytes);
+	ACPI_MOVE_UNALIGNED16_TO_16 (length_field, &actual_bytes);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -425,13 +416,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -444,33 +434,32 @@
 acpi_status
 acpi_rs_address32_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer;
 	acpi_resource           *output_struct;
 	u16                     temp16;
 	u8                      temp8;
 	NATIVE_CHAR             *temp_ptr;
-	u32                     struct_size;
+	ACPI_SIZE               struct_size;
 	u32                     index;
 
 
-	FUNCTION_TRACE ("Rs_address32_resource");
+	ACPI_FUNCTION_TRACE ("Rs_address32_resource");
 
 
 	buffer = byte_stream_buffer;
 	output_struct = (acpi_resource *) *output_buffer;
 
-	struct_size = SIZEOF_RESOURCE (acpi_resource_address32);
+	struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_address32);
 
 	/*
 	 * Point past the Descriptor to get the number of bytes consumed
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
-
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	*bytes_consumed = temp16 + 3;
 
 	output_struct->id = ACPI_RSTYPE_ADDRESS32;
@@ -520,20 +509,18 @@
 	buffer += 1;
 	temp8 = *buffer;
 
-	if (MEMORY_RANGE == output_struct->data.address32.resource_type) {
+	if (ACPI_MEMORY_RANGE == output_struct->data.address32.resource_type) {
 		output_struct->data.address32.attribute.memory.read_write_attribute =
 				(u16) (temp8 & 0x01);
 
 		output_struct->data.address32.attribute.memory.cache_attribute =
 				(u16) ((temp8 >> 1) & 0x0F);
 	}
-
 	else {
-		if (IO_RANGE == output_struct->data.address32.resource_type) {
+		if (ACPI_IO_RANGE == output_struct->data.address32.resource_type) {
 			output_struct->data.address32.attribute.io.range_attribute =
 				(u16) (temp8 & 0x03);
 		}
-
 		else {
 			/* BUS_NUMBER_RANGE == Output_struct->Data.Address32.Resource_type */
 			/* Nothing needs to be filled in */
@@ -544,35 +531,35 @@
 	 * Get Granularity (Bytes 6-9)
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.granularity,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.granularity,
 			 buffer);
 
 	/*
 	 * Get Min_address_range (Bytes 10-13)
 	 */
 	buffer += 4;
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.min_address_range,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.min_address_range,
 			 buffer);
 
 	/*
 	 * Get Max_address_range (Bytes 14-17)
 	 */
 	buffer += 4;
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.max_address_range,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.max_address_range,
 			 buffer);
 
 	/*
 	 * Get Address_translation_offset (Bytes 18-21)
 	 */
 	buffer += 4;
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.address_translation_offset,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.address_translation_offset,
 			 buffer);
 
 	/*
 	 * Get Address_length (Bytes 22-25)
 	 */
 	buffer += 4;
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.address_length,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.address32.address_length,
 			 buffer);
 
 	/*
@@ -606,7 +593,6 @@
 		/* Copy the string into the buffer */
 
 		index = 0;
-
 		while (0x00 != *buffer) {
 			*temp_ptr = *buffer;
 
@@ -627,9 +613,8 @@
 		 *  Struct_size to the next 32-bit boundary.
 		 */
 		temp8 = (u8) (index + 1);
-		struct_size += ROUND_UP_TO_32_bITS (temp8);
+		struct_size += ACPI_ROUND_UP_TO_32_bITS (temp8);
 	}
-
 	else {
 		output_struct->data.address32.resource_source.index = 0x00;
 		output_struct->data.address32.resource_source.string_length = 0;
@@ -655,9 +640,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -670,7 +654,7 @@
 acpi_rs_address32_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer;
 	u16                     *length_field;
@@ -678,7 +662,7 @@
 	NATIVE_CHAR             *temp_pointer;
 
 
-	FUNCTION_TRACE ("Rs_address32_stream");
+	ACPI_FUNCTION_TRACE ("Rs_address32_stream");
 
 
 	buffer = *output_buffer;
@@ -692,7 +676,6 @@
 	/*
 	 * Set a pointer to the Length field - to be filled in later
 	 */
-
 	length_field = (u16 *) buffer;
 	buffer += 2;
 
@@ -720,7 +703,7 @@
 	 */
 	temp8 = 0;
 
-	if(MEMORY_RANGE == linked_list->data.address32.resource_type) {
+	if (ACPI_MEMORY_RANGE == linked_list->data.address32.resource_type) {
 		temp8 = (u8)
 			(linked_list->data.address32.attribute.memory.read_write_attribute &
 			0x01);
@@ -729,8 +712,7 @@
 			(linked_list->data.address32.attribute.memory.cache_attribute &
 			 0x0F) << 1;
 	}
-
-	else if (IO_RANGE == linked_list->data.address32.resource_type) {
+	else if (ACPI_IO_RANGE == linked_list->data.address32.resource_type) {
 		temp8 = (u8)
 			(linked_list->data.address32.attribute.io.range_attribute &
 			 0x03);
@@ -742,35 +724,35 @@
 	/*
 	 * Set the address space granularity
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			  &linked_list->data.address32.granularity);
 	buffer += 4;
 
 	/*
 	 * Set the address range minimum
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			  &linked_list->data.address32.min_address_range);
 	buffer += 4;
 
 	/*
 	 * Set the address range maximum
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			  &linked_list->data.address32.max_address_range);
 	buffer += 4;
 
 	/*
 	 * Set the address translation offset
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			  &linked_list->data.address32.address_translation_offset);
 	buffer += 4;
 
 	/*
 	 * Set the address length
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			  &linked_list->data.address32.address_length);
 	buffer += 4;
 
@@ -788,20 +770,20 @@
 		/*
 		 * Copy the string
 		 */
-		STRCPY (temp_pointer,
+		ACPI_STRCPY (temp_pointer,
 			linked_list->data.address32.resource_source.string_ptr);
 
 		/*
 		 * Buffer needs to be set to the length of the sting + one for the
 		 *  terminating null
 		 */
-		buffer += (STRLEN (linked_list->data.address32.resource_source.string_ptr) + 1);
+		buffer += (ACPI_STRLEN (linked_list->data.address32.resource_source.string_ptr) + 1);
 	}
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 
 	/*
 	 * Set the length field to the number of bytes consumed
@@ -818,13 +800,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -837,32 +818,32 @@
 acpi_status
 acpi_rs_address64_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer;
 	acpi_resource           *output_struct;
 	u16                     temp16;
 	u8                      temp8;
 	NATIVE_CHAR             *temp_ptr;
-	u32                     struct_size;
+	ACPI_SIZE               struct_size;
 	u32                     index;
 
 
-	FUNCTION_TRACE ("Rs_address64_resource");
+	ACPI_FUNCTION_TRACE ("Rs_address64_resource");
 
 
 	buffer = byte_stream_buffer;
 	output_struct = (acpi_resource *) *output_buffer;
 
-	struct_size = SIZEOF_RESOURCE (acpi_resource_address64);
+	struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_address64);
 
 	/*
 	 * Point past the Descriptor to get the number of bytes consumed
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	*bytes_consumed = temp16 + 3;
 	output_struct->id = ACPI_RSTYPE_ADDRESS64;
@@ -874,6 +855,7 @@
 	temp8 = *buffer;
 
 	/* Values 0-2 are valid */
+
 	if(temp8 > 2) {
 		return_ACPI_STATUS (AE_AML_INVALID_RESOURCE_TYPE);
 	}
@@ -912,20 +894,18 @@
 	buffer += 1;
 	temp8 = *buffer;
 
-	if (MEMORY_RANGE == output_struct->data.address64.resource_type) {
+	if (ACPI_MEMORY_RANGE == output_struct->data.address64.resource_type) {
 		output_struct->data.address64.attribute.memory.read_write_attribute =
 				(u16) (temp8 & 0x01);
 
 		output_struct->data.address64.attribute.memory.cache_attribute =
 				(u16) ((temp8 >> 1) & 0x0F);
 	}
-
 	else {
-		if (IO_RANGE == output_struct->data.address64.resource_type) {
+		if (ACPI_IO_RANGE == output_struct->data.address64.resource_type) {
 			output_struct->data.address64.attribute.io.range_attribute =
 				(u16) (temp8 & 0x03);
 		}
-
 		else {
 			/* BUS_NUMBER_RANGE == Output_struct->Data.Address64.Resource_type */
 			/* Nothing needs to be filled in */
@@ -936,35 +916,35 @@
 	 * Get Granularity (Bytes 6-13)
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.granularity,
+	ACPI_MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.granularity,
 			 buffer);
 
 	/*
 	 * Get Min_address_range (Bytes 14-21)
 	 */
 	buffer += 8;
-	MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.min_address_range,
+	ACPI_MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.min_address_range,
 			 buffer);
 
 	/*
 	 * Get Max_address_range (Bytes 22-29)
 	 */
 	buffer += 8;
-	MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.max_address_range,
+	ACPI_MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.max_address_range,
 			 buffer);
 
 	/*
 	 * Get Address_translation_offset (Bytes 30-37)
 	 */
 	buffer += 8;
-	MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.address_translation_offset,
+	ACPI_MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.address_translation_offset,
 			 buffer);
 
 	/*
 	 * Get Address_length (Bytes 38-45)
 	 */
 	buffer += 8;
-	MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.address_length,
+	ACPI_MOVE_UNALIGNED64_TO_64 (&output_struct->data.address64.address_length,
 			 buffer);
 
 	/*
@@ -1000,7 +980,6 @@
 		/* Copy the string into the buffer */
 
 		index = 0;
-
 		while (0x00 != *buffer) {
 			*temp_ptr = *buffer;
 
@@ -1022,9 +1001,8 @@
 		 * Struct_size to the next 32-bit boundary.
 		 */
 		temp8 = (u8) (index + 1);
-		struct_size += ROUND_UP_TO_32_bITS (temp8);
+		struct_size += ACPI_ROUND_UP_TO_32_bITS (temp8);
 	}
-
 	else {
 		output_struct->data.address64.resource_source.index = 0x00;
 		output_struct->data.address64.resource_source.string_length = 0;
@@ -1050,9 +1028,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -1065,7 +1042,7 @@
 acpi_rs_address64_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer;
 	u16                     *length_field;
@@ -1073,7 +1050,7 @@
 	NATIVE_CHAR             *temp_pointer;
 
 
-	FUNCTION_TRACE ("Rs_address64_stream");
+	ACPI_FUNCTION_TRACE ("Rs_address64_stream");
 
 
 	buffer = *output_buffer;
@@ -1115,7 +1092,7 @@
 	 */
 	temp8 = 0;
 
-	if(MEMORY_RANGE == linked_list->data.address64.resource_type) {
+	if (ACPI_MEMORY_RANGE == linked_list->data.address64.resource_type) {
 		temp8 = (u8)
 			(linked_list->data.address64.attribute.memory.read_write_attribute &
 			0x01);
@@ -1124,8 +1101,7 @@
 			(linked_list->data.address64.attribute.memory.cache_attribute &
 			 0x0F) << 1;
 	}
-
-	else if (IO_RANGE == linked_list->data.address64.resource_type) {
+	else if (ACPI_IO_RANGE == linked_list->data.address64.resource_type) {
 		temp8 = (u8)
 			(linked_list->data.address64.attribute.io.range_attribute &
 			 0x03);
@@ -1137,35 +1113,35 @@
 	/*
 	 * Set the address space granularity
 	 */
-	MOVE_UNALIGNED64_TO_64 (buffer,
+	ACPI_MOVE_UNALIGNED64_TO_64 (buffer,
 			   &linked_list->data.address64.granularity);
 	buffer += 8;
 
 	/*
 	 * Set the address range minimum
 	 */
-	MOVE_UNALIGNED64_TO_64 (buffer,
+	ACPI_MOVE_UNALIGNED64_TO_64 (buffer,
 			   &linked_list->data.address64.min_address_range);
 	buffer += 8;
 
 	/*
 	 * Set the address range maximum
 	 */
-	MOVE_UNALIGNED64_TO_64 (buffer,
+	ACPI_MOVE_UNALIGNED64_TO_64 (buffer,
 			   &linked_list->data.address64.max_address_range);
 	buffer += 8;
 
 	/*
 	 * Set the address translation offset
 	 */
-	MOVE_UNALIGNED64_TO_64 (buffer,
+	ACPI_MOVE_UNALIGNED64_TO_64 (buffer,
 			   &linked_list->data.address64.address_translation_offset);
 	buffer += 8;
 
 	/*
 	 * Set the address length
 	 */
-	MOVE_UNALIGNED64_TO_64 (buffer,
+	ACPI_MOVE_UNALIGNED64_TO_64 (buffer,
 			   &linked_list->data.address64.address_length);
 	buffer += 8;
 
@@ -1183,19 +1159,19 @@
 		/*
 		 * Copy the string
 		 */
-		STRCPY (temp_pointer, linked_list->data.address64.resource_source.string_ptr);
+		ACPI_STRCPY (temp_pointer, linked_list->data.address64.resource_source.string_ptr);
 
 		/*
 		 * Buffer needs to be set to the length of the sting + one for the
 		 *  terminating null
 		 */
-		buffer += (STRLEN (linked_list->data.address64.resource_source.string_ptr) + 1);
+		buffer += (ACPI_STRLEN (linked_list->data.address64.resource_source.string_ptr) + 1);
 	}
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 
 	/*
 	 * Set the length field to the number of bytes consumed
diff -Nru a/drivers/acpi/resources/rscalc.c b/drivers/acpi/resources/rscalc.c
--- a/drivers/acpi/resources/rscalc.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/acpi/resources/rscalc.c	Fri Mar 15 17:51:00 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rscalc - Calculate stream and list lengths
- *              $Revision: 32 $
+ *              $Revision: 39 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rscalc")
+	 ACPI_MODULE_NAME    ("rscalc")
 
 
 /*******************************************************************************
@@ -52,15 +52,15 @@
 acpi_status
 acpi_rs_calculate_byte_stream_length (
 	acpi_resource           *linked_list,
-	u32                     *size_needed)
+	ACPI_SIZE               *size_needed)
 {
-	u32                     byte_stream_size_needed = 0;
-	u32                     segment_size;
+	ACPI_SIZE               byte_stream_size_needed = 0;
+	ACPI_SIZE               segment_size;
 	acpi_resource_ext_irq   *ex_irq = NULL;
 	u8                      done = FALSE;
 
 
-	FUNCTION_TRACE ("Rs_calculate_byte_stream_length");
+	ACPI_FUNCTION_TRACE ("Rs_calculate_byte_stream_length");
 
 
 	while (!done) {
@@ -243,7 +243,6 @@
 			 * so exit with an error
 			 */
 			return_ACPI_STATUS (AE_AML_INVALID_RESOURCE_TYPE);
-			break;
 
 		} /* switch (Linked_list->Id) */
 
@@ -255,7 +254,7 @@
 		/*
 		 * Point to the next object
 		 */
-		linked_list = POINTER_ADD (acpi_resource,
+		linked_list = ACPI_PTR_ADD (acpi_resource,
 				  linked_list, linked_list->length);
 	}
 
@@ -289,7 +288,7 @@
 acpi_rs_calculate_list_length (
 	u8                      *byte_stream_buffer,
 	u32                     byte_stream_buffer_length,
-	u32                     *size_needed)
+	ACPI_SIZE               *size_needed)
 {
 	u32                     buffer_size = 0;
 	u32                     bytes_parsed = 0;
@@ -305,7 +304,7 @@
 	u8                      additional_bytes;
 
 
-	FUNCTION_TRACE ("Rs_calculate_list_length");
+	ACPI_FUNCTION_TRACE ("Rs_calculate_list_length");
 
 
 	while (bytes_parsed < byte_stream_buffer_length) {
@@ -315,65 +314,65 @@
 		resource_type = acpi_rs_get_resource_type (*byte_stream_buffer);
 
 		switch (resource_type) {
-		case RESOURCE_DESC_MEMORY_24:
+		case ACPI_RDESC_TYPE_MEMORY_24:
 			/*
 			 * 24-Bit Memory Resource
 			 */
 			bytes_consumed = 12;
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_mem24);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_mem24);
 			break;
 
 
-		case RESOURCE_DESC_LARGE_VENDOR:
+		case ACPI_RDESC_TYPE_LARGE_VENDOR:
 			/*
 			 * Vendor Defined Resource
 			 */
 			buffer = byte_stream_buffer;
 			++buffer;
 
-			MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+			ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 			bytes_consumed = temp16 + 3;
 
 			/*
 			 * Ensure a 32-bit boundary for the structure
 			 */
-			temp16 = (u16) ROUND_UP_TO_32_bITS (temp16);
+			temp16 = (u16) ACPI_ROUND_UP_TO_32_bITS (temp16);
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_vendor) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_vendor) +
 					   (temp16 * sizeof (u8));
 			break;
 
 
-		case RESOURCE_DESC_MEMORY_32:
+		case ACPI_RDESC_TYPE_MEMORY_32:
 			/*
 			 * 32-Bit Memory Range Resource
 			 */
 
 			bytes_consumed = 20;
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_mem32);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_mem32);
 			break;
 
 
-		case RESOURCE_DESC_FIXED_MEMORY_32:
+		case ACPI_RDESC_TYPE_FIXED_MEMORY_32:
 			/*
 			 * 32-Bit Fixed Memory Resource
 			 */
 			bytes_consumed = 12;
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_fixed_mem32);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_fixed_mem32);
 			break;
 
 
-		case RESOURCE_DESC_QWORD_ADDRESS_SPACE:
+		case ACPI_RDESC_TYPE_QWORD_ADDRESS_SPACE:
 			/*
 			 * 64-Bit Address Resource
 			 */
 			buffer = byte_stream_buffer;
 
 			++buffer;
-			MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+			ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 			bytes_consumed = temp16 + 3;
 
@@ -397,21 +396,21 @@
 			/*
 			 * Ensure a 64-bit boundary for the structure
 			 */
-			temp8 = (u8) ROUND_UP_TO_64_bITS (temp8);
+			temp8 = (u8) ACPI_ROUND_UP_TO_64_bITS (temp8);
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_address64) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_address64) +
 					   (temp8 * sizeof (u8));
 			break;
 
 
-		case RESOURCE_DESC_DWORD_ADDRESS_SPACE:
+		case ACPI_RDESC_TYPE_DWORD_ADDRESS_SPACE:
 			/*
 			 * 32-Bit Address Resource
 			 */
 			buffer = byte_stream_buffer;
 
 			++buffer;
-			MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+			ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 			bytes_consumed = temp16 + 3;
 
@@ -435,21 +434,21 @@
 			/*
 			 * Ensure a 32-bit boundary for the structure
 			 */
-			temp8 = (u8) ROUND_UP_TO_32_bITS (temp8);
+			temp8 = (u8) ACPI_ROUND_UP_TO_32_bITS (temp8);
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_address32) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_address32) +
 					   (temp8 * sizeof (u8));
 			break;
 
 
-		case RESOURCE_DESC_WORD_ADDRESS_SPACE:
+		case ACPI_RDESC_TYPE_WORD_ADDRESS_SPACE:
 			/*
 			 * 16-Bit Address Resource
 			 */
 			buffer = byte_stream_buffer;
 
 			++buffer;
-			MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+			ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 			bytes_consumed = temp16 + 3;
 
@@ -473,21 +472,21 @@
 			/*
 			 * Ensure a 32-bit boundary for the structure
 			 */
-			temp8 = (u8) ROUND_UP_TO_32_bITS (temp8);
+			temp8 = (u8) ACPI_ROUND_UP_TO_32_bITS (temp8);
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_address16) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_address16) +
 					   (temp8 * sizeof (u8));
 			break;
 
 
-		case RESOURCE_DESC_EXTENDED_XRUPT:
+		case ACPI_RDESC_TYPE_EXTENDED_XRUPT:
 			/*
 			 * Extended IRQ
 			 */
 			buffer = byte_stream_buffer;
 
 			++buffer;
-			MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+			ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 			bytes_consumed = temp16 + 3;
 
@@ -518,7 +517,6 @@
 			if (9 + additional_bytes < temp16) {
 				temp8 = (u8) (temp16 - (9 + additional_bytes));
 			}
-
 			else {
 				temp8 = 0;
 			}
@@ -526,15 +524,15 @@
 			/*
 			 * Ensure a 32-bit boundary for the structure
 			 */
-			temp8 = (u8) ROUND_UP_TO_32_bITS (temp8);
+			temp8 = (u8) ACPI_ROUND_UP_TO_32_bITS (temp8);
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_ext_irq) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_ext_irq) +
 					   (additional_bytes * sizeof (u8)) +
 					   (temp8 * sizeof (u8));
 			break;
 
 
-		case RESOURCE_DESC_IRQ_FORMAT:
+		case ACPI_RDESC_TYPE_IRQ_FORMAT:
 			/*
 			 * IRQ Resource.
 			 * Determine if it there are two or three trailing bytes
@@ -545,7 +543,6 @@
 			if(temp8 & 0x01) {
 				bytes_consumed = 4;
 			}
-
 			else {
 				bytes_consumed = 3;
 			}
@@ -558,7 +555,7 @@
 			/*
 			 * Look at the number of bits set
 			 */
-			MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+			ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 			for (index = 0; index < 16; index++) {
 				if (temp16 & 0x1) {
@@ -568,12 +565,12 @@
 				temp16 >>= 1;
 			}
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_io) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_io) +
 					   (number_of_interrupts * sizeof (u32));
 			break;
 
 
-		case RESOURCE_DESC_DMA_FORMAT:
+		case ACPI_RDESC_TYPE_DMA_FORMAT:
 			/*
 			 * DMA Resource
 			 */
@@ -598,12 +595,12 @@
 				temp8 >>= 1;
 			}
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_dma) +
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_dma) +
 					   (number_of_channels * sizeof (u32));
 			break;
 
 
-		case RESOURCE_DESC_START_DEPENDENT:
+		case ACPI_RDESC_TYPE_START_DEPENDENT:
 			/*
 			 * Start Dependent Functions Resource
 			 * Determine if it there are two or three trailing bytes
@@ -618,11 +615,11 @@
 				bytes_consumed = 1;
 			}
 
-			structure_size = SIZEOF_RESOURCE (acpi_resource_start_dpf);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_start_dpf);
 			break;
 
 
-		case RESOURCE_DESC_END_DEPENDENT:
+		case ACPI_RDESC_TYPE_END_DEPENDENT:
 			/*
 			 * End Dependent Functions Resource
 			 */
@@ -631,25 +628,25 @@
 			break;
 
 
-		case RESOURCE_DESC_IO_PORT:
+		case ACPI_RDESC_TYPE_IO_PORT:
 			/*
 			 * IO Port Resource
 			 */
 			bytes_consumed = 8;
-			structure_size = SIZEOF_RESOURCE (acpi_resource_io);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_io);
 			break;
 
 
-		case RESOURCE_DESC_FIXED_IO_PORT:
+		case ACPI_RDESC_TYPE_FIXED_IO_PORT:
 			/*
 			 * Fixed IO Port Resource
 			 */
 			bytes_consumed = 4;
-			structure_size = SIZEOF_RESOURCE (acpi_resource_fixed_io);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_fixed_io);
 			break;
 
 
-		case RESOURCE_DESC_SMALL_VENDOR:
+		case ACPI_RDESC_TYPE_SMALL_VENDOR:
 			/*
 			 * Vendor Specific Resource
 			 */
@@ -662,13 +659,13 @@
 			/*
 			 * Ensure a 32-bit boundary for the structure
 			 */
-			temp8 = (u8) ROUND_UP_TO_32_bITS (temp8);
-			structure_size = SIZEOF_RESOURCE (acpi_resource_vendor) +
+			temp8 = (u8) ACPI_ROUND_UP_TO_32_bITS (temp8);
+			structure_size = ACPI_SIZEOF_RESOURCE (acpi_resource_vendor) +
 					   (temp8 * sizeof (u8));
 			break;
 
 
-		case RESOURCE_DESC_END_TAG:
+		case ACPI_RDESC_TYPE_END_TAG:
 			/*
 			 * End Tag
 			 */
@@ -684,14 +681,12 @@
 			 *  so exit with an error
 			 */
 			return_ACPI_STATUS (AE_AML_INVALID_RESOURCE_TYPE);
-			break;
 		}
 
-
 		/*
 		 * Update the return value and counter
 		 */
-		buffer_size += structure_size;
+		buffer_size += ACPI_ALIGN_RESOURCE_SIZE(structure_size);
 		bytes_parsed += bytes_consumed;
 
 		/*
@@ -700,7 +695,6 @@
 		byte_stream_buffer += bytes_consumed;
 	}
 
-
 	/*
 	 * This is the data the caller needs
 	 */
@@ -729,7 +723,7 @@
 acpi_status
 acpi_rs_calculate_pci_routing_table_length (
 	acpi_operand_object     *package_object,
-	u32                     *buffer_size_needed)
+	ACPI_SIZE               *buffer_size_needed)
 {
 	u32                     number_of_elements;
 	u32                     temp_size_needed = 0;
@@ -741,7 +735,7 @@
 	u32                     table_index;
 
 
-	FUNCTION_TRACE ("Rs_calculate_pci_routing_table_length");
+	ACPI_FUNCTION_TRACE ("Rs_calculate_pci_routing_table_length");
 
 
 	number_of_elements = package_object->package.count;
@@ -781,7 +775,6 @@
 					((*sub_object_list)->reference.opcode == AML_INT_NAMEPATH_OP))) {
 				name_found = TRUE;
 			}
-
 			else {
 				/*
 				 * Look at the next element
@@ -790,7 +783,7 @@
 			}
 		}
 
-		temp_size_needed += (sizeof (pci_routing_table) - 4);
+		temp_size_needed += (sizeof (acpi_pci_routing_table) - 4);
 
 		/*
 		 * Was a String type found?
@@ -803,13 +796,11 @@
 				 */
 				temp_size_needed += (*sub_object_list)->string.length;
 			}
-
 			else {
 				temp_size_needed += acpi_ns_get_pathname_length (
 						   (*sub_object_list)->reference.node);
 			}
 		}
-
 		else {
 			/*
 			 * If no name was found, then this is a NULL, which is
@@ -820,7 +811,7 @@
 
 		/* Round up the size since each element must be aligned */
 
-		temp_size_needed = ROUND_UP_TO_64_bITS (temp_size_needed);
+		temp_size_needed = ACPI_ROUND_UP_TO_64_bITS (temp_size_needed);
 
 		/*
 		 * Point to the next acpi_operand_object
@@ -828,10 +819,9 @@
 		top_object_list++;
 	}
 
-
 	/*
 	 * Adding an extra element to the end of the list, essentially a NULL terminator
 	 */
-	*buffer_size_needed = temp_size_needed + sizeof (pci_routing_table);
+	*buffer_size_needed = temp_size_needed + sizeof (acpi_pci_routing_table);
 	return_ACPI_STATUS (AE_OK);
 }
diff -Nru a/drivers/acpi/resources/rscreate.c b/drivers/acpi/resources/rscreate.c
--- a/drivers/acpi/resources/rscreate.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/resources/rscreate.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rscreate - Create resource lists/tables
- *              $Revision: 36 $
+ *              $Revision: 53 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 #include "acnamesp.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rscreate")
+	 ACPI_MODULE_NAME    ("rscreate")
 
 
 /*******************************************************************************
@@ -55,17 +55,16 @@
 acpi_status
 acpi_rs_create_resource_list (
 	acpi_operand_object     *byte_stream_buffer,
-	u8                      *output_buffer,
-	u32                     *output_buffer_length)
+	acpi_buffer             *output_buffer)
 {
 
 	acpi_status             status;
 	u8                      *byte_stream_start;
-	u32                     list_size_needed = 0;
+	ACPI_SIZE               list_size_needed = 0;
 	u32                     byte_stream_buffer_length;
 
 
-	FUNCTION_TRACE ("Rs_create_resource_list");
+	ACPI_FUNCTION_TRACE ("Rs_create_resource_list");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Byte_stream_buffer = %p\n", byte_stream_buffer));
@@ -85,43 +84,27 @@
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Status=%X List_size_needed=%X\n",
 		status, list_size_needed));
-
-	/*
-	 * Exit with the error passed back
-	 */
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
 
-	/*
-	 * If the linked list will fit into the available buffer
-	 * call to fill in the list
-	 */
-	if (list_size_needed <= *output_buffer_length) {
-		/*
-		 * Zero out the return buffer before proceeding
-		 */
-		MEMSET (output_buffer, 0x00, *output_buffer_length);
-
-		status = acpi_rs_byte_stream_to_list (byte_stream_start, byte_stream_buffer_length,
-				 &output_buffer);
+	/* Validate/Allocate/Clear caller buffer */
 
-		/*
-		 * Exit with the error passed back
-		 */
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
-		}
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Output_buffer = %p\n", output_buffer));
+	status = acpi_ut_initialize_buffer (output_buffer, list_size_needed);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	else {
-		*output_buffer_length = list_size_needed;
-		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
+	/* Do the conversion */
+
+	status = acpi_rs_byte_stream_to_list (byte_stream_start, byte_stream_buffer_length,
+			  output_buffer->pointer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	*output_buffer_length = list_size_needed;
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Output_buffer %p Length %X\n",
+			output_buffer->pointer, output_buffer->length));
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -137,225 +120,203 @@
  *
  * RETURN:      Status  AE_OK if okay, else a valid acpi_status code.
  *              If the Output_buffer is too small, the error will be
- *              AE_BUFFER_OVERFLOW and Output_buffer_length will point
+ *              AE_BUFFER_OVERFLOW and Output_buffer->Length will point
  *              to the size buffer needed.
  *
  * DESCRIPTION: Takes the acpi_operand_object  package and creates a
  *              linked list of PCI interrupt descriptions
  *
+ * NOTE: It is the caller's responsibility to ensure that the start of the
+ * output buffer is aligned properly (if necessary).
+ *
  ******************************************************************************/
 
 acpi_status
 acpi_rs_create_pci_routing_table (
 	acpi_operand_object     *package_object,
-	u8                      *output_buffer,
-	u32                     *output_buffer_length)
+	acpi_buffer             *output_buffer)
 {
-	u8                      *buffer = output_buffer;
+	u8                      *buffer;
 	acpi_operand_object     **top_object_list = NULL;
 	acpi_operand_object     **sub_object_list = NULL;
 	acpi_operand_object     *package_element = NULL;
-	u32                     buffer_size_needed = 0;
+	ACPI_SIZE               buffer_size_needed = 0;
 	u32                     number_of_elements = 0;
 	u32                     index = 0;
-	pci_routing_table       *user_prt = NULL;
+	acpi_pci_routing_table  *user_prt = NULL;
 	acpi_namespace_node     *node;
 	acpi_status             status;
+	acpi_buffer             path_buffer;
 
 
-	FUNCTION_TRACE ("Rs_create_pci_routing_table");
+	ACPI_FUNCTION_TRACE ("Rs_create_pci_routing_table");
 
 
+	/* Params already validated, so we don't re-validate here */
+
 	/*
-	 * Params already validated, so we don't re-validate here
+	 * Get the required buffer length
 	 */
 	status = acpi_rs_calculate_pci_routing_table_length (package_object,
 			 &buffer_size_needed);
-
-	if (!ACPI_SUCCESS(status)) {
+	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Buffer_size_needed = %X\n", buffer_size_needed));
 
+	/* Validate/Allocate/Clear caller buffer */
+
+	status = acpi_ut_initialize_buffer (output_buffer, buffer_size_needed);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	/*
-	 * If the data will fit into the available buffer
-	 * call to fill in the list
+	 * Loop through the ACPI_INTERNAL_OBJECTS - Each object should contain an
+	 * acpi_integer Address, a u8 Pin, a Name and a u8 Source_index.
 	 */
-	if (buffer_size_needed <= *output_buffer_length) {
+	top_object_list  = package_object->package.elements;
+	number_of_elements = package_object->package.count;
+	buffer           = output_buffer->pointer;
+	user_prt         = (acpi_pci_routing_table *) buffer;
+
+	for (index = 0; index < number_of_elements; index++) {
 		/*
-		 * Zero out the return buffer before proceeding
+		 * Point User_prt past this current structure
+		 *
+		 * NOTE: On the first iteration, User_prt->Length will
+		 * be zero because we cleared the return buffer earlier
 		 */
-		MEMSET (output_buffer, 0x00, *output_buffer_length);
+		buffer += user_prt->length;
+		user_prt = (acpi_pci_routing_table *) buffer;
 
 		/*
-		 * Loop through the ACPI_INTERNAL_OBJECTS - Each object should
-		 * contain a u32 Address, a u8 Pin, a Name and a u8
-		 * Source_index.
+		 * Fill in the Length field with the information we have at this point.
+		 * The minus four is to subtract the size of the u8 Source[4] member
+		 * because it is added below.
 		 */
-		top_object_list     = package_object->package.elements;
-		number_of_elements  = package_object->package.count;
-		user_prt            = (pci_routing_table *) buffer;
-
-
-		buffer = ROUND_PTR_UP_TO_8 (buffer, u8);
-
-		for (index = 0; index < number_of_elements; index++) {
-			/*
-			 * Point User_prt past this current structure
-			 *
-			 * NOTE: On the first iteration, User_prt->Length will
-			 * be zero because we cleared the return buffer earlier
-			 */
-			buffer += user_prt->length;
-			user_prt = (pci_routing_table *) buffer;
+		user_prt->length = (sizeof (acpi_pci_routing_table) -4);
 
+		/*
+		 * Dereference the sub-package
+		 */
+		package_element = *top_object_list;
 
-			/*
-			 * Fill in the Length field with the information we
-			 * have at this point.
-			 * The minus four is to subtract the size of the
-			 * u8 Source[4] member because it is added below.
-			 */
-			user_prt->length = (sizeof (pci_routing_table) -4);
-
-			/*
-			 * Dereference the sub-package
-			 */
-			package_element = *top_object_list;
+		/*
+		 * The Sub_object_list will now point to an array of the four IRQ
+		 * elements: Address, Pin, Source and Source_index
+		 */
+		sub_object_list = package_element->package.elements;
 
-			/*
-			 * The Sub_object_list will now point to an array of
-			 * the four IRQ elements: Address, Pin, Source and
-			 * Source_index
-			 */
-			sub_object_list = package_element->package.elements;
+		/*
+		 * 1) First subobject:  Dereference the Address
+		 */
+		if (ACPI_TYPE_INTEGER == (*sub_object_list)->common.type) {
+			user_prt->address = (*sub_object_list)->integer.value;
+		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
+				acpi_ut_get_type_name ((*sub_object_list)->common.type)));
+			return_ACPI_STATUS (AE_BAD_DATA);
+		}
 
-			/*
-			 * 1) First subobject:  Dereference the Address
-			 */
-			if (ACPI_TYPE_INTEGER == (*sub_object_list)->common.type) {
-				user_prt->address = (*sub_object_list)->integer.value;
-			}
+		/*
+		 * 2) Second subobject: Dereference the Pin
+		 */
+		sub_object_list++;
 
-			else {
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
-					acpi_ut_get_type_name ((*sub_object_list)->common.type)));
-				return_ACPI_STATUS (AE_BAD_DATA);
-			}
+		if (ACPI_TYPE_INTEGER == (*sub_object_list)->common.type) {
+			user_prt->pin = (u32) (*sub_object_list)->integer.value;
+		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
+				acpi_ut_get_type_name ((*sub_object_list)->common.type)));
+			return_ACPI_STATUS (AE_BAD_DATA);
+		}
 
-			/*
-			 * 2) Second subobject: Dereference the Pin
-			 */
-			sub_object_list++;
+		/*
+		 * 3) Third subobject: Dereference the Source Name
+		 */
+		sub_object_list++;
 
-			if (ACPI_TYPE_INTEGER == (*sub_object_list)->common.type) {
-				user_prt->pin = (u32) (*sub_object_list)->integer.value;
-			}
+		switch ((*sub_object_list)->common.type) {
+		case INTERNAL_TYPE_REFERENCE:
 
-			else {
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
-					acpi_ut_get_type_name ((*sub_object_list)->common.type)));
+			if ((*sub_object_list)->reference.opcode != AML_INT_NAMEPATH_OP) {
+			   ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need name, found reference op %X\n",
+					(*sub_object_list)->reference.opcode));
 				return_ACPI_STATUS (AE_BAD_DATA);
 			}
 
-			/*
-			 * 3) Third subobject: Dereference the Source Name
-			 */
-			sub_object_list++;
-
-			switch ((*sub_object_list)->common.type) {
-			case INTERNAL_TYPE_REFERENCE:
+			node = (*sub_object_list)->reference.node;
 
-				if ((*sub_object_list)->reference.opcode != AML_INT_NAMEPATH_OP) {
-				   ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need name, found reference op %X\n",
-						(*sub_object_list)->reference.opcode));
-					return_ACPI_STATUS (AE_BAD_DATA);
-				}
+			/* Use *remaining* length of the buffer as max for pathname */
 
-				node = (*sub_object_list)->reference.node;
+			path_buffer.length = output_buffer->length -
+					   (u32) ((u8 *) user_prt->source - (u8 *) output_buffer->pointer);
+			path_buffer.pointer = user_prt->source;
 
-				/* TBD: use *remaining* length of the buffer! */
+			status = acpi_ns_handle_to_pathname ((acpi_handle *) node, &path_buffer);
 
-				status = acpi_ns_handle_to_pathname ((acpi_handle *) node,
-						 output_buffer_length, user_prt->source);
+			user_prt->length += ACPI_STRLEN (user_prt->source) + 1; /* include null terminator */
+			break;
 
-				user_prt->length += STRLEN (user_prt->source) + 1; /* include null terminator */
-				break;
 
+		case ACPI_TYPE_STRING:
 
-			case ACPI_TYPE_STRING:
+			ACPI_STRCPY (user_prt->source,
+				  (*sub_object_list)->string.pointer);
 
-				STRCPY (user_prt->source,
-					  (*sub_object_list)->string.pointer);
+			/* Add to the Length field the length of the string */
 
-				/*
-				 * Add to the Length field the length of the string
-				 */
-				user_prt->length += (*sub_object_list)->string.length;
-				break;
+			user_prt->length += (*sub_object_list)->string.length;
+			break;
 
 
-			case ACPI_TYPE_INTEGER:
-				/*
-				 * If this is a number, then the Source Name
-				 * is NULL, since the entire buffer was zeroed
-				 * out, we can leave this alone.
-				 */
-				/*
-				 * Add to the Length field the length of
-				 * the u32 NULL
-				 */
-				user_prt->length += sizeof (u32);
-				break;
+		case ACPI_TYPE_INTEGER:
+			/*
+			 * If this is a number, then the Source Name is NULL, since the
+			 * entire buffer was zeroed out, we can leave this alone.
+			 *
+			 * Add to the Length field the length of the u32 NULL
+			 */
+			user_prt->length += sizeof (u32);
+			break;
 
 
-			default:
+		default:
 
-			   ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
-					acpi_ut_get_type_name ((*sub_object_list)->common.type)));
-			   return_ACPI_STATUS (AE_BAD_DATA);
-			   break;
-			}
+		   ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
+				acpi_ut_get_type_name ((*sub_object_list)->common.type)));
+		   return_ACPI_STATUS (AE_BAD_DATA);
+		}
 
-			/* Now align the current length */
+		/* Now align the current length */
 
-			user_prt->length = ROUND_UP_TO_64_bITS (user_prt->length);
+		user_prt->length = ACPI_ROUND_UP_TO_64_bITS (user_prt->length);
 
-			/*
-			 * 4) Fourth subobject: Dereference the Source Index
-			 */
-			sub_object_list++;
-
-			if (ACPI_TYPE_INTEGER == (*sub_object_list)->common.type) {
-				user_prt->source_index = (u32) (*sub_object_list)->integer.value;
-			}
-
-			else {
-				ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
-					acpi_ut_get_type_name ((*sub_object_list)->common.type)));
-				return_ACPI_STATUS (AE_BAD_DATA);
-			}
+		/*
+		 * 4) Fourth subobject: Dereference the Source Index
+		 */
+		sub_object_list++;
 
-			/*
-			 * Point to the next acpi_operand_object
-			 */
-			top_object_list++;
+		if (ACPI_TYPE_INTEGER == (*sub_object_list)->common.type) {
+			user_prt->source_index = (u32) (*sub_object_list)->integer.value;
+		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Need Integer, found %s\n",
+				acpi_ut_get_type_name ((*sub_object_list)->common.type)));
+			return_ACPI_STATUS (AE_BAD_DATA);
 		}
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Output_buffer = %p\n", output_buffer));
-	}
-
-	else {
-		*output_buffer_length = buffer_size_needed;
+		/* Point to the next acpi_operand_object */
 
-		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
+		top_object_list++;
 	}
 
-	/*
-	 * Report the amount of buffer used
-	 */
-	*output_buffer_length = buffer_size_needed;
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Output_buffer %p Length %X\n",
+			output_buffer->pointer, output_buffer->length));
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -366,11 +327,10 @@
  *
  * PARAMETERS:  Linked_list_buffer      - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's buffer
- *              Output_buffer_length    - Size of Output_buffer
  *
  * RETURN:      Status  AE_OK if okay, else a valid acpi_status code.
  *              If the Output_buffer is too small, the error will be
- *              AE_BUFFER_OVERFLOW and Output_buffer_length will point
+ *              AE_BUFFER_OVERFLOW and Output_buffer->Length will point
  *              to the size buffer needed.
  *
  * DESCRIPTION: Takes the linked list of device resources and
@@ -382,14 +342,13 @@
 acpi_status
 acpi_rs_create_byte_stream (
 	acpi_resource           *linked_list_buffer,
-	u8                      *output_buffer,
-	u32                     *output_buffer_length)
+	acpi_buffer             *output_buffer)
 {
 	acpi_status             status;
-	u32                     byte_stream_size_needed = 0;
+	ACPI_SIZE               byte_stream_size_needed = 0;
 
 
-	FUNCTION_TRACE ("Rs_create_byte_stream");
+	ACPI_FUNCTION_TRACE ("Rs_create_byte_stream");
 
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Linked_list_buffer = %p\n", linked_list_buffer));
@@ -397,7 +356,7 @@
 	/*
 	 * Params already validated, so we don't re-validate here
 	 *
-	 * Pass the Linked_list_buffer into a module that can calculate
+	 * Pass the Linked_list_buffer into a module that calculates
 	 * the buffer size needed for the byte stream.
 	 */
 	status = acpi_rs_calculate_byte_stream_length (linked_list_buffer,
@@ -405,42 +364,27 @@
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Byte_stream_size_needed=%X, %s\n",
 		byte_stream_size_needed, acpi_format_exception (status)));
-
-	/*
-	 * Exit with the error passed back
-	 */
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
 
-	/*
-	 * If the linked list will fit into the available buffer
-	 * call to fill in the list
-	 */
-	if (byte_stream_size_needed <= *output_buffer_length) {
-		/*
-		 * Zero out the return buffer before proceeding
-		 */
-		MEMSET (output_buffer, 0x00, *output_buffer_length);
-
-		status = acpi_rs_list_to_byte_stream (linked_list_buffer, byte_stream_size_needed,
-				 &output_buffer);
+	/* Validate/Allocate/Clear caller buffer */
 
-		/*
-		 * Exit with the error passed back
-		 */
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
-		}
-
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Output_buffer = %p\n", output_buffer));
+	status = acpi_ut_initialize_buffer (output_buffer, byte_stream_size_needed);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	else {
-		*output_buffer_length = byte_stream_size_needed;
-		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
+	/* Do the conversion */
+
+	status = acpi_rs_list_to_byte_stream (linked_list_buffer, byte_stream_size_needed,
+			  output_buffer->pointer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Output_buffer %p Length %X\n",
+			output_buffer->pointer, output_buffer->length));
 	return_ACPI_STATUS (AE_OK);
 }
 
diff -Nru a/drivers/acpi/resources/rsdump.c b/drivers/acpi/resources/rsdump.c
--- a/drivers/acpi/resources/rsdump.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/resources/rsdump.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsdump - Functions to display the resource structures.
- *              $Revision: 23 $
+ *              $Revision: 29 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsdump")
+	 ACPI_MODULE_NAME    ("rsdump")
 
 
 #ifdef ACPI_DEBUG
@@ -53,19 +53,19 @@
 	u8                      index = 0;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("IRQ Resource\n");
 
 	acpi_os_printf ("  %s Triggered\n",
-			 LEVEL_SENSITIVE == irq_data->edge_level ? "Level" : "Edge");
+			 ACPI_LEVEL_SENSITIVE == irq_data->edge_level ? "Level" : "Edge");
 
 	acpi_os_printf ("  Active %s\n",
-			 ACTIVE_LOW == irq_data->active_high_low ? "Low" : "High");
+			 ACPI_ACTIVE_LOW == irq_data->active_high_low ? "Low" : "High");
 
 	acpi_os_printf ("  %s\n",
-			 SHARED == irq_data->shared_exclusive ? "Shared" : "Exclusive");
+			 ACPI_SHARED == irq_data->shared_exclusive ? "Shared" : "Exclusive");
 
 	acpi_os_printf ("  %X Interrupts ( ", irq_data->number_of_interrupts);
 
@@ -98,25 +98,25 @@
 	u8                      index = 0;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("DMA Resource\n");
 
 	switch (dma_data->type) {
-	case COMPATIBILITY:
+	case ACPI_COMPATIBILITY:
 		acpi_os_printf ("  Compatibility mode\n");
 		break;
 
-	case TYPE_A:
+	case ACPI_TYPE_A:
 		acpi_os_printf ("  Type A\n");
 		break;
 
-	case TYPE_B:
+	case ACPI_TYPE_B:
 		acpi_os_printf ("  Type B\n");
 		break;
 
-	case TYPE_F:
+	case ACPI_TYPE_F:
 		acpi_os_printf ("  Type F\n");
 		break;
 
@@ -126,19 +126,19 @@
 	}
 
 	acpi_os_printf ("  %sBus Master\n",
-			 BUS_MASTER == dma_data->bus_master ? "" : "Not a ");
+			 ACPI_BUS_MASTER == dma_data->bus_master ? "" : "Not a ");
 
 
 	switch (dma_data->transfer) {
-	case TRANSFER_8:
+	case ACPI_TRANSFER_8:
 		acpi_os_printf ("  8-bit only transfer\n");
 		break;
 
-	case TRANSFER_8_16:
+	case ACPI_TRANSFER_8_16:
 		acpi_os_printf ("  8 and 16-bit transfer\n");
 		break;
 
-	case TRANSFER_16:
+	case ACPI_TRANSFER_16:
 		acpi_os_printf ("  16 bit only transfer\n");
 		break;
 
@@ -160,7 +160,7 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_rs_dump_start_dependent_functions
+ * FUNCTION:    Acpi_rs_dump_start_depend_fns
  *
  * PARAMETERS:  Data            - pointer to the resource structure to dump.
  *
@@ -171,27 +171,27 @@
  ******************************************************************************/
 
 void
-acpi_rs_dump_start_dependent_functions (
+acpi_rs_dump_start_depend_fns (
 	acpi_resource_data          *data)
 {
 	acpi_resource_start_dpf     *sdf_data = (acpi_resource_start_dpf *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("Start Dependent Functions Resource\n");
 
 	switch (sdf_data->compatibility_priority) {
-	case GOOD_CONFIGURATION:
+	case ACPI_GOOD_CONFIGURATION:
 		acpi_os_printf ("  Good configuration\n");
 		break;
 
-	case ACCEPTABLE_CONFIGURATION:
+	case ACPI_ACCEPTABLE_CONFIGURATION:
 		acpi_os_printf ("  Acceptable configuration\n");
 		break;
 
-	case SUB_OPTIMAL_CONFIGURATION:
+	case ACPI_SUB_OPTIMAL_CONFIGURATION:
 		acpi_os_printf ("  Sub-optimal configuration\n");
 		break;
 
@@ -201,15 +201,15 @@
 	}
 
 	switch(sdf_data->performance_robustness) {
-	case GOOD_CONFIGURATION:
+	case ACPI_GOOD_CONFIGURATION:
 		acpi_os_printf ("  Good configuration\n");
 		break;
 
-	case ACCEPTABLE_CONFIGURATION:
+	case ACPI_ACCEPTABLE_CONFIGURATION:
 		acpi_os_printf ("  Acceptable configuration\n");
 		break;
 
-	case SUB_OPTIMAL_CONFIGURATION:
+	case ACPI_SUB_OPTIMAL_CONFIGURATION:
 		acpi_os_printf ("  Sub-optimal configuration\n");
 		break;
 
@@ -242,13 +242,13 @@
 	acpi_resource_io        *io_data = (acpi_resource_io *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("Io Resource\n");
 
 	acpi_os_printf ("  %d bit decode\n",
-			 DECODE_16 == io_data->io_decode ? 16 : 10);
+			 ACPI_DECODE_16 == io_data->io_decode ? 16 : 10);
 
 	acpi_os_printf ("  Range minimum base: %08X\n",
 			 io_data->min_base_address);
@@ -285,7 +285,7 @@
 	acpi_resource_fixed_io  *fixed_io_data = (acpi_resource_fixed_io *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("Fixed Io Resource\n");
@@ -319,7 +319,7 @@
 	u16                     index = 0;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("Vendor Specific Resource\n");
@@ -354,13 +354,13 @@
 	acpi_resource_mem24     *memory24_data = (acpi_resource_mem24 *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("24-Bit Memory Range Resource\n");
 
 	acpi_os_printf ("  Read%s\n",
-			 READ_WRITE_MEMORY ==
+			 ACPI_READ_WRITE_MEMORY ==
 			 memory24_data->read_write_attribute ?
 			 "/Write" : " only");
 
@@ -399,13 +399,13 @@
 	acpi_resource_mem32     *memory32_data = (acpi_resource_mem32 *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("32-Bit Memory Range Resource\n");
 
 	acpi_os_printf ("  Read%s\n",
-			 READ_WRITE_MEMORY ==
+			 ACPI_READ_WRITE_MEMORY ==
 			 memory32_data->read_write_attribute ?
 			 "/Write" : " only");
 
@@ -444,13 +444,13 @@
 	acpi_resource_fixed_mem32   *fixed_memory32_data = (acpi_resource_fixed_mem32 *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("32-Bit Fixed Location Memory Range Resource\n");
 
 	acpi_os_printf ("  Read%s\n",
-			 READ_WRITE_MEMORY ==
+			 ACPI_READ_WRITE_MEMORY ==
 			 fixed_memory32_data->read_write_attribute ?
 			 "/Write" : " Only");
 
@@ -483,34 +483,34 @@
 	acpi_resource_address16 *address16_data = (acpi_resource_address16 *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("16-Bit Address Space Resource\n");
 	acpi_os_printf ("  Resource Type: ");
 
 	switch (address16_data->resource_type) {
-	case MEMORY_RANGE:
+	case ACPI_MEMORY_RANGE:
 
 		acpi_os_printf ("Memory Range\n");
 
 		switch (address16_data->attribute.memory.cache_attribute) {
-		case NON_CACHEABLE_MEMORY:
+		case ACPI_NON_CACHEABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Noncacheable memory\n");
 			break;
 
-		case CACHABLE_MEMORY:
+		case ACPI_CACHABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Cacheable memory\n");
 			break;
 
-		case WRITE_COMBINING_MEMORY:
+		case ACPI_WRITE_COMBINING_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Write-combining memory\n");
 			break;
 
-		case PREFETCHABLE_MEMORY:
+		case ACPI_PREFETCHABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Prefetchable memory\n");
 			break;
@@ -522,27 +522,27 @@
 		}
 
 		acpi_os_printf ("  Type Specific: Read%s\n",
-			READ_WRITE_MEMORY ==
+			ACPI_READ_WRITE_MEMORY ==
 			address16_data->attribute.memory.read_write_attribute ?
 			"/Write" : " Only");
 		break;
 
-	case IO_RANGE:
+	case ACPI_IO_RANGE:
 
 		acpi_os_printf ("I/O Range\n");
 
 		switch (address16_data->attribute.io.range_attribute) {
-		case NON_ISA_ONLY_RANGES:
+		case ACPI_NON_ISA_ONLY_RANGES:
 			acpi_os_printf ("  Type Specific: "
 					  "Non-ISA Io Addresses\n");
 			break;
 
-		case ISA_ONLY_RANGES:
+		case ACPI_ISA_ONLY_RANGES:
 			acpi_os_printf ("  Type Specific: "
 					  "ISA Io Addresses\n");
 			break;
 
-		case ENTIRE_RANGE:
+		case ACPI_ENTIRE_RANGE:
 			acpi_os_printf ("  Type Specific: "
 					  "ISA and non-ISA Io Addresses\n");
 			break;
@@ -554,7 +554,7 @@
 		}
 		break;
 
-	case BUS_NUMBER_RANGE:
+	case ACPI_BUS_NUMBER_RANGE:
 
 		acpi_os_printf ("Bus Number Range\n");
 		break;
@@ -566,19 +566,19 @@
 	}
 
 	acpi_os_printf ("  Resource %s\n",
-			CONSUMER == address16_data->producer_consumer ?
+			ACPI_CONSUMER == address16_data->producer_consumer ?
 			"Consumer" : "Producer");
 
 	acpi_os_printf ("  %s decode\n",
-			 SUB_DECODE == address16_data->decode ?
+			 ACPI_SUB_DECODE == address16_data->decode ?
 			 "Subtractive" : "Positive");
 
 	acpi_os_printf ("  Min address is %s fixed\n",
-			 ADDRESS_FIXED == address16_data->min_address_fixed ?
+			 ACPI_ADDRESS_FIXED == address16_data->min_address_fixed ?
 			 "" : "not");
 
 	acpi_os_printf ("  Max address is %s fixed\n",
-			 ADDRESS_FIXED == address16_data->max_address_fixed ?
+			 ACPI_ADDRESS_FIXED == address16_data->max_address_fixed ?
 			 "" : "not");
 
 	acpi_os_printf ("  Granularity: %08X\n",
@@ -626,33 +626,33 @@
 	acpi_resource_address32 *address32_data = (acpi_resource_address32 *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("32-Bit Address Space Resource\n");
 
 	switch (address32_data->resource_type) {
-	case MEMORY_RANGE:
+	case ACPI_MEMORY_RANGE:
 
 		acpi_os_printf ("  Resource Type: Memory Range\n");
 
 		switch (address32_data->attribute.memory.cache_attribute) {
-		case NON_CACHEABLE_MEMORY:
+		case ACPI_NON_CACHEABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Noncacheable memory\n");
 			break;
 
-		case CACHABLE_MEMORY:
+		case ACPI_CACHABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Cacheable memory\n");
 			break;
 
-		case WRITE_COMBINING_MEMORY:
+		case ACPI_WRITE_COMBINING_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Write-combining memory\n");
 			break;
 
-		case PREFETCHABLE_MEMORY:
+		case ACPI_PREFETCHABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Prefetchable memory\n");
 			break;
@@ -664,27 +664,27 @@
 		}
 
 		acpi_os_printf ("  Type Specific: Read%s\n",
-			READ_WRITE_MEMORY ==
+			ACPI_READ_WRITE_MEMORY ==
 			address32_data->attribute.memory.read_write_attribute ?
 			"/Write" : " Only");
 		break;
 
-	case IO_RANGE:
+	case ACPI_IO_RANGE:
 
 		acpi_os_printf ("  Resource Type: Io Range\n");
 
 		switch (address32_data->attribute.io.range_attribute) {
-			case NON_ISA_ONLY_RANGES:
+			case ACPI_NON_ISA_ONLY_RANGES:
 				acpi_os_printf ("  Type Specific: "
 						  "Non-ISA Io Addresses\n");
 				break;
 
-			case ISA_ONLY_RANGES:
+			case ACPI_ISA_ONLY_RANGES:
 				acpi_os_printf ("  Type Specific: "
 						  "ISA Io Addresses\n");
 				break;
 
-			case ENTIRE_RANGE:
+			case ACPI_ENTIRE_RANGE:
 				acpi_os_printf ("  Type Specific: "
 						  "ISA and non-ISA Io Addresses\n");
 				break;
@@ -696,7 +696,7 @@
 			}
 		break;
 
-	case BUS_NUMBER_RANGE:
+	case ACPI_BUS_NUMBER_RANGE:
 
 		acpi_os_printf ("  Resource Type: Bus Number Range\n");
 		break;
@@ -708,19 +708,19 @@
 	}
 
 	acpi_os_printf ("  Resource %s\n",
-			 CONSUMER == address32_data->producer_consumer ?
+			 ACPI_CONSUMER == address32_data->producer_consumer ?
 			 "Consumer" : "Producer");
 
 	acpi_os_printf ("  %s decode\n",
-			 SUB_DECODE == address32_data->decode ?
+			 ACPI_SUB_DECODE == address32_data->decode ?
 			 "Subtractive" : "Positive");
 
 	acpi_os_printf ("  Min address is %s fixed\n",
-			 ADDRESS_FIXED == address32_data->min_address_fixed ?
+			 ACPI_ADDRESS_FIXED == address32_data->min_address_fixed ?
 			 "" : "not ");
 
 	acpi_os_printf ("  Max address is %s fixed\n",
-			 ADDRESS_FIXED == address32_data->max_address_fixed ?
+			 ACPI_ADDRESS_FIXED == address32_data->max_address_fixed ?
 			 "" : "not ");
 
 	acpi_os_printf ("  Granularity: %08X\n",
@@ -768,33 +768,33 @@
 	acpi_resource_address64 *address64_data = (acpi_resource_address64 *) data;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("64-Bit Address Space Resource\n");
 
 	switch (address64_data->resource_type) {
-	case MEMORY_RANGE:
+	case ACPI_MEMORY_RANGE:
 
 		acpi_os_printf ("  Resource Type: Memory Range\n");
 
 		switch (address64_data->attribute.memory.cache_attribute) {
-		case NON_CACHEABLE_MEMORY:
+		case ACPI_NON_CACHEABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Noncacheable memory\n");
 			break;
 
-		case CACHABLE_MEMORY:
+		case ACPI_CACHABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Cacheable memory\n");
 			break;
 
-		case WRITE_COMBINING_MEMORY:
+		case ACPI_WRITE_COMBINING_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Write-combining memory\n");
 			break;
 
-		case PREFETCHABLE_MEMORY:
+		case ACPI_PREFETCHABLE_MEMORY:
 			acpi_os_printf ("  Type Specific: "
 					  "Prefetchable memory\n");
 			break;
@@ -806,27 +806,27 @@
 		}
 
 		acpi_os_printf ("  Type Specific: Read%s\n",
-			READ_WRITE_MEMORY ==
+			ACPI_READ_WRITE_MEMORY ==
 			address64_data->attribute.memory.read_write_attribute ?
 			"/Write" : " Only");
 		break;
 
-	case IO_RANGE:
+	case ACPI_IO_RANGE:
 
 		acpi_os_printf ("  Resource Type: Io Range\n");
 
 		switch (address64_data->attribute.io.range_attribute) {
-			case NON_ISA_ONLY_RANGES:
+			case ACPI_NON_ISA_ONLY_RANGES:
 				acpi_os_printf ("  Type Specific: "
 						  "Non-ISA Io Addresses\n");
 				break;
 
-			case ISA_ONLY_RANGES:
+			case ACPI_ISA_ONLY_RANGES:
 				acpi_os_printf ("  Type Specific: "
 						  "ISA Io Addresses\n");
 				break;
 
-			case ENTIRE_RANGE:
+			case ACPI_ENTIRE_RANGE:
 				acpi_os_printf ("  Type Specific: "
 						  "ISA and non-ISA Io Addresses\n");
 				break;
@@ -838,7 +838,7 @@
 			}
 		break;
 
-	case BUS_NUMBER_RANGE:
+	case ACPI_BUS_NUMBER_RANGE:
 
 		acpi_os_printf ("  Resource Type: Bus Number Range\n");
 		break;
@@ -850,19 +850,19 @@
 	}
 
 	acpi_os_printf ("  Resource %s\n",
-			 CONSUMER == address64_data->producer_consumer ?
+			 ACPI_CONSUMER == address64_data->producer_consumer ?
 			 "Consumer" : "Producer");
 
 	acpi_os_printf ("  %s decode\n",
-			 SUB_DECODE == address64_data->decode ?
+			 ACPI_SUB_DECODE == address64_data->decode ?
 			 "Subtractive" : "Positive");
 
 	acpi_os_printf ("  Min address is %s fixed\n",
-			 ADDRESS_FIXED == address64_data->min_address_fixed ?
+			 ACPI_ADDRESS_FIXED == address64_data->min_address_fixed ?
 			 "" : "not ");
 
 	acpi_os_printf ("  Max address is %s fixed\n",
-			 ADDRESS_FIXED == address64_data->max_address_fixed ?
+			 ACPI_ADDRESS_FIXED == address64_data->max_address_fixed ?
 			 "" : "not ");
 
 	acpi_os_printf ("  Granularity: %16X\n",
@@ -911,25 +911,25 @@
 	u8                      index = 0;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	acpi_os_printf ("Extended IRQ Resource\n");
 
 	acpi_os_printf ("  Resource %s\n",
-			 CONSUMER == ext_irq_data->producer_consumer ?
+			 ACPI_CONSUMER == ext_irq_data->producer_consumer ?
 			 "Consumer" : "Producer");
 
 	acpi_os_printf ("  %s\n",
-			 LEVEL_SENSITIVE == ext_irq_data->edge_level ?
+			 ACPI_LEVEL_SENSITIVE == ext_irq_data->edge_level ?
 			 "Level" : "Edge");
 
 	acpi_os_printf ("  Active %s\n",
-			 ACTIVE_LOW == ext_irq_data->active_high_low ?
+			 ACPI_ACTIVE_LOW == ext_irq_data->active_high_low ?
 			 "low" : "high");
 
 	acpi_os_printf ("  %s\n",
-			 SHARED == ext_irq_data->shared_exclusive ?
+			 ACPI_SHARED == ext_irq_data->shared_exclusive ?
 			 "Shared" : "Exclusive");
 
 	acpi_os_printf ("  Interrupts : %X ( ",
@@ -972,7 +972,7 @@
 	u8                  done = FALSE;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (acpi_dbg_level & ACPI_LV_RESOURCES && _COMPONENT & acpi_dbg_layer) {
@@ -989,7 +989,7 @@
 				break;
 
 			case ACPI_RSTYPE_START_DPF:
-				acpi_rs_dump_start_dependent_functions (&resource->data);
+				acpi_rs_dump_start_depend_fns (&resource->data);
 				break;
 
 			case ACPI_RSTYPE_END_DPF:
@@ -1049,7 +1049,7 @@
 
 			}
 
-			resource = POINTER_ADD (acpi_resource, resource, resource->length);
+			resource = ACPI_PTR_ADD (acpi_resource, resource, resource->length);
 		}
 	}
 
@@ -1070,25 +1070,26 @@
 
 void
 acpi_rs_dump_irq_list (
-	u8                  *route_table)
+	u8                      *route_table)
 {
-	u8                  *buffer = route_table;
-	u8                  count = 0;
-	u8                  done = FALSE;
-	pci_routing_table   *prt_element;
+	u8                      *buffer = route_table;
+	u8                      count = 0;
+	u8                      done = FALSE;
+	acpi_pci_routing_table  *prt_element;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (acpi_dbg_level & ACPI_LV_RESOURCES && _COMPONENT & acpi_dbg_layer) {
-		prt_element = (pci_routing_table *) buffer;
+		prt_element = (acpi_pci_routing_table *) buffer;
 
 		while (!done) {
 			acpi_os_printf ("PCI IRQ Routing Table structure %X.\n", count++);
 
-			acpi_os_printf ("  Address: %X\n",
-					 prt_element->address);
+			acpi_os_printf ("  Address: %8.8X%8.8X\n",
+					 ACPI_HIDWORD (prt_element->address),
+					 ACPI_LODWORD (prt_element->address));
 
 			acpi_os_printf ("  Pin: %X\n", prt_element->pin);
 
@@ -1099,7 +1100,7 @@
 
 			buffer += prt_element->length;
 
-			prt_element = (pci_routing_table *) buffer;
+			prt_element = (acpi_pci_routing_table *) buffer;
 
 			if(0 == prt_element->length) {
 				done = TRUE;
diff -Nru a/drivers/acpi/resources/rsio.c b/drivers/acpi/resources/rsio.c
--- a/drivers/acpi/resources/rsio.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/acpi/resources/rsio.c	Fri Mar 15 17:51:00 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsio - IO and DMA resource descriptors
- *              $Revision: 14 $
+ *              $Revision: 17 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsio")
+	 ACPI_MODULE_NAME    ("rsio")
 
 
 /*******************************************************************************
@@ -37,13 +37,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -56,18 +55,18 @@
 acpi_status
 acpi_rs_io_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_io);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_io);
 
 
-	FUNCTION_TRACE ("Rs_io_resource");
+	ACPI_FUNCTION_TRACE ("Rs_io_resource");
 
 
 	/*
@@ -89,7 +88,7 @@
 	 * Check Min_base Address
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	output_struct->data.io.min_base_address = temp16;
 
@@ -97,7 +96,7 @@
 	 * Check Max_base Address
 	 */
 	buffer += 2;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	output_struct->data.io.max_base_address = temp16;
 
@@ -136,13 +135,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -155,18 +153,18 @@
 acpi_status
 acpi_rs_fixed_io_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_fixed_io);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_fixed_io);
 
 
-	FUNCTION_TRACE ("Rs_fixed_io_resource");
+	ACPI_FUNCTION_TRACE ("Rs_fixed_io_resource");
 
 
 	/*
@@ -180,7 +178,7 @@
 	 * Check Range Base Address
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	output_struct->data.fixed_io.base_address = temp16;
 
@@ -211,9 +209,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -226,14 +223,14 @@
 acpi_rs_io_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_io_stream");
+	ACPI_FUNCTION_TRACE ("Rs_io_stream");
 
 
 	/*
@@ -255,7 +252,7 @@
 	 */
 	temp16 = (u16) linked_list->data.io.min_base_address;
 
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -263,7 +260,7 @@
 	 */
 	temp16 = (u16) linked_list->data.io.max_base_address;
 
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -285,7 +282,7 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -296,9 +293,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -311,14 +307,14 @@
 acpi_rs_fixed_io_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_fixed_io_stream");
+	ACPI_FUNCTION_TRACE ("Rs_fixed_io_stream");
 
 
 	/*
@@ -333,7 +329,7 @@
 	 */
 	temp16 = (u16) linked_list->data.fixed_io.base_address;
 
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -347,7 +343,7 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -358,13 +354,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -377,19 +372,19 @@
 acpi_status
 acpi_rs_dma_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u8                      temp8 = 0;
 	u8                      index;
 	u8                      i;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_dma);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_dma);
 
 
-	FUNCTION_TRACE ("Rs_dma_resource");
+	ACPI_FUNCTION_TRACE ("Rs_dma_resource");
 
 
 	/*
@@ -464,9 +459,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -479,7 +473,7 @@
 acpi_rs_dma_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
@@ -487,7 +481,7 @@
 	u8                      index;
 
 
-	FUNCTION_TRACE ("Rs_dma_stream");
+	ACPI_FUNCTION_TRACE ("Rs_dma_stream");
 
 
 	/*
@@ -523,7 +517,7 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
diff -Nru a/drivers/acpi/resources/rsirq.c b/drivers/acpi/resources/rsirq.c
--- a/drivers/acpi/resources/rsirq.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/resources/rsirq.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsirq - IRQ resource descriptors
- *              $Revision: 18 $
+ *              $Revision: 24 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsirq")
+	 ACPI_MODULE_NAME    ("rsirq")
 
 
 /*******************************************************************************
@@ -37,13 +37,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -56,9 +55,9 @@
 acpi_status
 acpi_rs_irq_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
@@ -66,10 +65,10 @@
 	u8                      temp8 = 0;
 	u8                      index;
 	u8                      i;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_irq);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_irq);
 
 
-	FUNCTION_TRACE ("Rs_irq_resource");
+	ACPI_FUNCTION_TRACE ("Rs_irq_resource");
 
 
 	/*
@@ -84,7 +83,7 @@
 	 * Point to the 16-bits of Bytes 1 and 2
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	output_struct->data.irq.number_of_interrupts = 0;
 
@@ -114,16 +113,14 @@
 		 * Check for HE, LL or HL
 		 */
 		if (temp8 & 0x01) {
-			output_struct->data.irq.edge_level = EDGE_SENSITIVE;
-			output_struct->data.irq.active_high_low = ACTIVE_HIGH;
+			output_struct->data.irq.edge_level = ACPI_EDGE_SENSITIVE;
+			output_struct->data.irq.active_high_low = ACPI_ACTIVE_HIGH;
 		}
-
 		else {
 			if (temp8 & 0x8) {
-				output_struct->data.irq.edge_level = LEVEL_SENSITIVE;
-				output_struct->data.irq.active_high_low = ACTIVE_LOW;
+				output_struct->data.irq.edge_level = ACPI_LEVEL_SENSITIVE;
+				output_struct->data.irq.active_high_low = ACPI_ACTIVE_LOW;
 			}
-
 			else {
 				/*
 				 * Only _LL and _HE polarity/trigger interrupts
@@ -139,15 +136,14 @@
 		 */
 		output_struct->data.irq.shared_exclusive = (temp8 >> 3) & 0x01;
 	}
-
 	else {
 		/*
 		 * Assume Edge Sensitive, Active High, Non-Sharable
 		 * per ACPI Specification
 		 */
-		output_struct->data.irq.edge_level = EDGE_SENSITIVE;
-		output_struct->data.irq.active_high_low = ACTIVE_HIGH;
-		output_struct->data.irq.shared_exclusive = EXCLUSIVE;
+		output_struct->data.irq.edge_level = ACPI_EDGE_SENSITIVE;
+		output_struct->data.irq.active_high_low = ACPI_ACTIVE_HIGH;
+		output_struct->data.irq.shared_exclusive = ACPI_EXCLUSIVE;
 	}
 
 	/*
@@ -169,9 +165,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -184,7 +179,7 @@
 acpi_rs_irq_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
@@ -193,20 +188,19 @@
 	u8                      IRQinfo_byte_needed;
 
 
-	FUNCTION_TRACE ("Rs_irq_stream");
+	ACPI_FUNCTION_TRACE ("Rs_irq_stream");
 
 
 	/*
 	 * The descriptor field is set based upon whether a third byte is
 	 * needed to contain the IRQ Information.
 	 */
-	if (EDGE_SENSITIVE == linked_list->data.irq.edge_level &&
-		ACTIVE_HIGH == linked_list->data.irq.active_high_low &&
-		EXCLUSIVE == linked_list->data.irq.shared_exclusive) {
+	if (ACPI_EDGE_SENSITIVE == linked_list->data.irq.edge_level &&
+		ACPI_ACTIVE_HIGH == linked_list->data.irq.active_high_low &&
+		ACPI_EXCLUSIVE == linked_list->data.irq.shared_exclusive) {
 		*buffer = 0x22;
 		IRQinfo_byte_needed = FALSE;
 	}
-
 	else {
 		*buffer = 0x23;
 		IRQinfo_byte_needed = TRUE;
@@ -225,7 +219,7 @@
 		temp16 |= 0x1 << temp8;
 	}
 
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -236,11 +230,10 @@
 		temp8 = (u8) ((linked_list->data.irq.shared_exclusive &
 				 0x01) << 4);
 
-		if (LEVEL_SENSITIVE == linked_list->data.irq.edge_level &&
-			ACTIVE_LOW == linked_list->data.irq.active_high_low) {
+		if (ACPI_LEVEL_SENSITIVE == linked_list->data.irq.edge_level &&
+			ACPI_ACTIVE_LOW == linked_list->data.irq.active_high_low) {
 			temp8 |= 0x08;
 		}
-
 		else {
 			temp8 |= 0x01;
 		}
@@ -252,7 +245,7 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -263,13 +256,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -282,9 +274,9 @@
 acpi_status
 acpi_rs_extended_irq_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
@@ -292,17 +284,17 @@
 	u8                      temp8 = 0;
 	NATIVE_CHAR             *temp_ptr;
 	u8                      index;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_ext_irq);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_ext_irq);
 
 
-	FUNCTION_TRACE ("Rs_extended_irq_resource");
+	ACPI_FUNCTION_TRACE ("Rs_extended_irq_resource");
 
 
 	/*
 	 * Point past the Descriptor to get the number of bytes consumed
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	*bytes_consumed = temp16 + 3;
 	output_struct->id = ACPI_RSTYPE_EXT_IRQ;
@@ -316,28 +308,20 @@
 	output_struct->data.extended_irq.producer_consumer = temp8 & 0x01;
 
 	/*
-	 * Check for HE, LL or HL
+	 * Check for Interrupt Mode
+	 *
+	 * The definition of an Extended IRQ changed between ACPI spec v1.0b
+	 * and ACPI spec 2.0 (section 6.4.3.6 in both).
+	 *
+	 * - Edge/Level are defined opposite in the table vs the headers
 	 */
-	if(temp8 & 0x02) {
-		output_struct->data.extended_irq.edge_level = EDGE_SENSITIVE;
-		output_struct->data.extended_irq.active_high_low = ACTIVE_HIGH;
-	}
-
-	else {
-		if(temp8 & 0x4) {
-			output_struct->data.extended_irq.edge_level = LEVEL_SENSITIVE;
-			output_struct->data.extended_irq.active_high_low = ACTIVE_LOW;
-		}
+	output_struct->data.extended_irq.edge_level =
+			   (temp8 & 0x2) ? ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
 
-		else {
-			/*
-			 * Only _LL and _HE polarity/trigger interrupts
-			 * are allowed (ACPI spec v1.0b ection 6.4.2.1),
-			 * so an error will occur if we reach this point
-			 */
-			return_ACPI_STATUS (AE_BAD_DATA);
-		}
-	}
+	/*
+	 * Check Interrupt Polarity
+	 */
+	output_struct->data.extended_irq.active_high_low = (temp8 >> 2) & 0x1;
 
 	/*
 	 * Check for sharable
@@ -404,7 +388,6 @@
 		/* Copy the string into the buffer */
 
 		index = 0;
-
 		while (0x00 != *buffer) {
 			*temp_ptr = *buffer;
 
@@ -425,9 +408,8 @@
 		 * Struct_size to the next 32-bit boundary.
 		 */
 		temp8 = (u8) (index + 1);
-		struct_size += ROUND_UP_TO_32_bITS (temp8);
+		struct_size += ACPI_ROUND_UP_TO_32_bITS (temp8);
 	}
-
 	else {
 		output_struct->data.extended_irq.resource_source.index = 0x00;
 		output_struct->data.extended_irq.resource_source.string_length = 0;
@@ -453,9 +435,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -468,7 +449,7 @@
 acpi_rs_extended_irq_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     *length_field;
@@ -477,7 +458,7 @@
 	NATIVE_CHAR             *temp_pointer = NULL;
 
 
-	FUNCTION_TRACE ("Rs_extended_irq_stream");
+	ACPI_FUNCTION_TRACE ("Rs_extended_irq_stream");
 
 
 	/*
@@ -498,14 +479,24 @@
 	temp8 = (u8)(linked_list->data.extended_irq.producer_consumer & 0x01);
 	temp8 |= ((linked_list->data.extended_irq.shared_exclusive & 0x01) << 3);
 
-	if (LEVEL_SENSITIVE == linked_list->data.extended_irq.edge_level &&
-	   ACTIVE_LOW == linked_list->data.extended_irq.active_high_low) {
-		temp8 |= 0x04;
-	}
-	else {
-		temp8 |= 0x02;
+	/*
+	 * Set the Interrupt Mode
+	 *
+	 * The definition of an Extended IRQ changed between ACPI spec v1.0b
+	 * and ACPI spec 2.0 (section 6.4.3.6 in both).  This code does not
+	 * implement the more restrictive definition of 1.0b
+	 *
+	 * - Edge/Level are defined opposite in the table vs the headers
+	 */
+	if (ACPI_EDGE_SENSITIVE == linked_list->data.extended_irq.edge_level) {
+		temp8 |= 0x2;
 	}
 
+	/*
+	 * Set the Interrupt Polarity
+	 */
+	temp8 |= ((linked_list->data.extended_irq.active_high_low & 0x1) << 2);
+
 	*buffer = temp8;
 	buffer += 1;
 
@@ -519,7 +510,7 @@
 
 	for (index = 0; index < linked_list->data.extended_irq.number_of_interrupts;
 		 index++) {
-		MOVE_UNALIGNED32_TO_32 (buffer,
+		ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 				  &linked_list->data.extended_irq.interrupts[index]);
 		buffer += 4;
 	}
@@ -536,20 +527,20 @@
 		/*
 		 * Copy the string
 		 */
-		STRCPY (temp_pointer,
+		ACPI_STRCPY (temp_pointer,
 			linked_list->data.extended_irq.resource_source.string_ptr);
 
 		/*
 		 * Buffer needs to be set to the length of the sting + one for the
 		 * terminating null
 		 */
-		buffer += (STRLEN (linked_list->data.extended_irq.resource_source.string_ptr) + 1);
+		buffer += (ACPI_STRLEN (linked_list->data.extended_irq.resource_source.string_ptr) + 1);
 	}
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 
 	/*
 	 * Set the length field to the number of bytes consumed
diff -Nru a/drivers/acpi/resources/rslist.c b/drivers/acpi/resources/rslist.c
--- a/drivers/acpi/resources/rslist.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/resources/rslist.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rslist - Linked list utilities
- *              $Revision: 19 $
+ *              $Revision: 26 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rslist")
+	 ACPI_MODULE_NAME    ("rslist")
 
 
 /*******************************************************************************
@@ -49,29 +49,27 @@
 	u8                      resource_start_byte)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
 	 * Determine if this is a small or large resource
 	 */
-	switch (resource_start_byte & RESOURCE_DESC_TYPE_MASK) {
-	case RESOURCE_DESC_TYPE_SMALL:
+	switch (resource_start_byte & ACPI_RDESC_TYPE_MASK) {
+	case ACPI_RDESC_TYPE_SMALL:
 
 		/*
 		 * Small Resource Type -- Only bits 6:3 are valid
 		 */
-		return ((u8) (resource_start_byte & RESOURCE_DESC_SMALL_MASK));
-		break;
+		return ((u8) (resource_start_byte & ACPI_RDESC_SMALL_MASK));
 
 
-	case RESOURCE_DESC_TYPE_LARGE:
+	case ACPI_RDESC_TYPE_LARGE:
 
 		/*
 		 * Large Resource Type -- All bits are valid
 		 */
 		return (resource_start_byte);
-		break;
 	}
 
 	return (0xFF);
@@ -98,18 +96,18 @@
 acpi_rs_byte_stream_to_list (
 	u8                      *byte_stream_buffer,
 	u32                     byte_stream_buffer_length,
-	u8                      **output_buffer)
+	u8                      *output_buffer)
 {
 	acpi_status             status;
 	u32                     bytes_parsed = 0;
 	u8                      resource_type = 0;
-	u32                     bytes_consumed = 0;
-	u8                      **buffer = output_buffer;
-	u32                     structure_size = 0;
+	ACPI_SIZE               bytes_consumed = 0;
+	u8                      *buffer = output_buffer;
+	ACPI_SIZE               structure_size = 0;
 	u8                      end_tag_processed = FALSE;
+	acpi_resource           *resource;
 
-
-	FUNCTION_TRACE ("Rs_byte_stream_to_list");
+	ACPI_FUNCTION_TRACE ("Rs_byte_stream_to_list");
 
 
 	while (bytes_parsed < byte_stream_buffer_length &&
@@ -120,148 +118,148 @@
 		resource_type = acpi_rs_get_resource_type (*byte_stream_buffer);
 
 		switch (resource_type) {
-		case RESOURCE_DESC_MEMORY_24:
+		case ACPI_RDESC_TYPE_MEMORY_24:
 			/*
 			 * 24-Bit Memory Resource
 			 */
 			status = acpi_rs_memory24_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_LARGE_VENDOR:
+		case ACPI_RDESC_TYPE_LARGE_VENDOR:
 			/*
 			 * Vendor Defined Resource
 			 */
 			status = acpi_rs_vendor_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_MEMORY_32:
+		case ACPI_RDESC_TYPE_MEMORY_32:
 			/*
 			 * 32-Bit Memory Range Resource
 			 */
 			status = acpi_rs_memory32_range_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_FIXED_MEMORY_32:
+		case ACPI_RDESC_TYPE_FIXED_MEMORY_32:
 			/*
 			 * 32-Bit Fixed Memory Resource
 			 */
 			status = acpi_rs_fixed_memory32_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_QWORD_ADDRESS_SPACE:
+		case ACPI_RDESC_TYPE_QWORD_ADDRESS_SPACE:
 			/*
 			 * 64-Bit Address Resource
 			 */
 			status = acpi_rs_address64_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_DWORD_ADDRESS_SPACE:
+		case ACPI_RDESC_TYPE_DWORD_ADDRESS_SPACE:
 			/*
 			 * 32-Bit Address Resource
 			 */
 			status = acpi_rs_address32_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_WORD_ADDRESS_SPACE:
+		case ACPI_RDESC_TYPE_WORD_ADDRESS_SPACE:
 			/*
 			 * 16-Bit Address Resource
 			 */
 			status = acpi_rs_address16_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_EXTENDED_XRUPT:
+		case ACPI_RDESC_TYPE_EXTENDED_XRUPT:
 			/*
 			 * Extended IRQ
 			 */
 			status = acpi_rs_extended_irq_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_IRQ_FORMAT:
+		case ACPI_RDESC_TYPE_IRQ_FORMAT:
 			/*
 			 * IRQ Resource
 			 */
 			status = acpi_rs_irq_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_DMA_FORMAT:
+		case ACPI_RDESC_TYPE_DMA_FORMAT:
 			/*
 			 * DMA Resource
 			 */
 			status = acpi_rs_dma_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_START_DEPENDENT:
+		case ACPI_RDESC_TYPE_START_DEPENDENT:
 			/*
 			 * Start Dependent Functions Resource
 			 */
-			status = acpi_rs_start_dependent_functions_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+			status = acpi_rs_start_depend_fns_resource (byte_stream_buffer,
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_END_DEPENDENT:
+		case ACPI_RDESC_TYPE_END_DEPENDENT:
 			/*
 			 * End Dependent Functions Resource
 			 */
-			status = acpi_rs_end_dependent_functions_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+			status = acpi_rs_end_depend_fns_resource (byte_stream_buffer,
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_IO_PORT:
+		case ACPI_RDESC_TYPE_IO_PORT:
 			/*
 			 * IO Port Resource
 			 */
 			status = acpi_rs_io_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_FIXED_IO_PORT:
+		case ACPI_RDESC_TYPE_FIXED_IO_PORT:
 			/*
 			 * Fixed IO Port Resource
 			 */
 			status = acpi_rs_fixed_io_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_SMALL_VENDOR:
+		case ACPI_RDESC_TYPE_SMALL_VENDOR:
 			/*
 			 * Vendor Specific Resource
 			 */
 			status = acpi_rs_vendor_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
-		case RESOURCE_DESC_END_TAG:
+		case ACPI_RDESC_TYPE_END_TAG:
 			/*
 			 * End Tag
 			 */
 			end_tag_processed = TRUE;
 			status = acpi_rs_end_tag_resource (byte_stream_buffer,
-					 &bytes_consumed, buffer, &structure_size);
+					 &bytes_consumed, &buffer, &structure_size);
 			break;
 
 
@@ -273,8 +271,7 @@
 			break;
 		}
 
-
-		if (!ACPI_SUCCESS(status)) {
+		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
 
@@ -291,7 +288,9 @@
 		/*
 		 * Set the Buffer to the next structure
 		 */
-		*buffer += structure_size;
+		resource = (acpi_resource *)buffer;
+		resource->length = ACPI_ALIGN_RESOURCE_SIZE(resource->length);
+		buffer += ACPI_ALIGN_RESOURCE_SIZE(structure_size);
 
 	} /*  end while */
 
@@ -331,15 +330,15 @@
 acpi_rs_list_to_byte_stream (
 	acpi_resource           *linked_list,
 	u32                     byte_stream_size_needed,
-	u8                      **output_buffer)
+	u8                      *output_buffer)
 {
 	acpi_status             status;
-	u8                      *buffer = *output_buffer;
-	u32                     bytes_consumed = 0;
+	u8                      *buffer = output_buffer;
+	ACPI_SIZE               bytes_consumed = 0;
 	u8                      done = FALSE;
 
 
-	FUNCTION_TRACE ("Rs_list_to_byte_stream");
+	ACPI_FUNCTION_TRACE ("Rs_list_to_byte_stream");
 
 
 	while (!done) {
@@ -362,7 +361,7 @@
 			/*
 			 * Start Dependent Functions Resource
 			 */
-			status = acpi_rs_start_dependent_functions_stream (linked_list,
+			status = acpi_rs_start_depend_fns_stream (linked_list,
 					  &buffer, &bytes_consumed);
 			break;
 
@@ -370,7 +369,7 @@
 			/*
 			 * End Dependent Functions Resource
 			 */
-			status = acpi_rs_end_dependent_functions_stream (linked_list,
+			status = acpi_rs_end_depend_fns_stream (linked_list,
 					  &buffer, &bytes_consumed);
 			break;
 
@@ -472,8 +471,7 @@
 
 		} /* switch (Linked_list->Id) */
 
-
-		if (!ACPI_SUCCESS(status)) {
+		if (ACPI_FAILURE (status)) {
 			return_ACPI_STATUS (status);
 		}
 
@@ -485,7 +483,7 @@
 		/*
 		 * Point to the next object
 		 */
-		linked_list = POINTER_ADD (acpi_resource,
+		linked_list = ACPI_PTR_ADD (acpi_resource,
 				  linked_list, linked_list->length);
 	}
 
diff -Nru a/drivers/acpi/resources/rsmemory.c b/drivers/acpi/resources/rsmemory.c
--- a/drivers/acpi/resources/rsmemory.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/resources/rsmemory.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsmem24 - Memory resource descriptors
- *              $Revision: 14 $
+ *              $Revision: 17 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsmemory")
+	 ACPI_MODULE_NAME    ("rsmemory")
 
 
 /*******************************************************************************
@@ -37,13 +37,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -56,18 +55,18 @@
 acpi_status
 acpi_rs_memory24_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_mem24);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_mem24);
 
 
-	FUNCTION_TRACE ("Rs_memory24_resource");
+	ACPI_FUNCTION_TRACE ("Rs_memory24_resource");
 
 
 	/*
@@ -75,7 +74,7 @@
 	 */
 	buffer += 1;
 
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	buffer += 2;
 	*bytes_consumed = temp16 + 3;
 	output_struct->id = ACPI_RSTYPE_MEM24;
@@ -90,28 +89,28 @@
 	/*
 	 * Get Min_base_address (Bytes 4-5)
 	 */
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	buffer += 2;
 	output_struct->data.memory24.min_base_address = temp16;
 
 	/*
 	 * Get Max_base_address (Bytes 6-7)
 	 */
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	buffer += 2;
 	output_struct->data.memory24.max_base_address = temp16;
 
 	/*
 	 * Get Alignment (Bytes 8-9)
 	 */
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	buffer += 2;
 	output_struct->data.memory24.alignment = temp16;
 
 	/*
 	 * Get Range_length (Bytes 10-11)
 	 */
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	output_struct->data.memory24.range_length = temp16;
 
 	/*
@@ -133,9 +132,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -148,14 +146,14 @@
 acpi_rs_memory24_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_memory24_stream");
+	ACPI_FUNCTION_TRACE ("Rs_memory24_stream");
 
 
 	/*
@@ -168,7 +166,7 @@
 	 * The length field is static
 	 */
 	temp16 = 0x09;
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -181,31 +179,31 @@
 	/*
 	 * Set the Range minimum base address
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.min_base_address);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.min_base_address);
 	buffer += 2;
 
 	/*
 	 * Set the Range maximum base address
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.max_base_address);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.max_base_address);
 	buffer += 2;
 
 	/*
 	 * Set the base alignment
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.alignment);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.alignment);
 	buffer += 2;
 
 	/*
 	 * Set the range length
 	 */
-	MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.range_length);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &linked_list->data.memory24.range_length);
 	buffer += 2;
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -216,13 +214,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -235,18 +232,18 @@
 acpi_status
 acpi_rs_memory32_range_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_mem32);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_mem32);
 
 
-	FUNCTION_TRACE ("Rs_memory32_range_resource");
+	ACPI_FUNCTION_TRACE ("Rs_memory32_range_resource");
 
 
 	/*
@@ -254,7 +251,7 @@
 	 */
 	buffer += 1;
 
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 	buffer += 2;
 	*bytes_consumed = temp16 + 3;
 
@@ -281,27 +278,27 @@
 	/*
 	 * Get Min_base_address (Bytes 4-7)
 	 */
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.min_base_address,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.min_base_address,
 			 buffer);
 	buffer += 4;
 
 	/*
 	 * Get Max_base_address (Bytes 8-11)
 	 */
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.max_base_address,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.max_base_address,
 			 buffer);
 	buffer += 4;
 
 	/*
 	 * Get Alignment (Bytes 12-15)
 	 */
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.alignment, buffer);
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.alignment, buffer);
 	buffer += 4;
 
 	/*
 	 * Get Range_length (Bytes 16-19)
 	 */
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.range_length, buffer);
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.memory32.range_length, buffer);
 
 	/*
 	 * Set the Length parameter
@@ -322,13 +319,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -341,25 +337,25 @@
 acpi_status
 acpi_rs_fixed_memory32_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_fixed_mem32);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_fixed_mem32);
 
 
-	FUNCTION_TRACE ("Rs_fixed_memory32_resource");
+	ACPI_FUNCTION_TRACE ("Rs_fixed_memory32_resource");
 
 
 	/*
 	 * Point past the Descriptor to get the number of bytes consumed
 	 */
 	buffer += 1;
-	MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+	ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 	buffer += 2;
 	*bytes_consumed = temp16 + 3;
@@ -376,14 +372,14 @@
 	/*
 	 * Get Range_base_address (Bytes 4-7)
 	 */
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.fixed_memory32.range_base_address,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.fixed_memory32.range_base_address,
 			 buffer);
 	buffer += 4;
 
 	/*
 	 * Get Range_length (Bytes 8-11)
 	 */
-	MOVE_UNALIGNED32_TO_32 (&output_struct->data.fixed_memory32.range_length,
+	ACPI_MOVE_UNALIGNED32_TO_32 (&output_struct->data.fixed_memory32.range_length,
 			 buffer);
 
 	/*
@@ -405,9 +401,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -420,14 +415,14 @@
 acpi_rs_memory32_range_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_memory32_range_stream");
+	ACPI_FUNCTION_TRACE ("Rs_memory32_range_stream");
 
 
 	/*
@@ -441,7 +436,7 @@
 	 */
 	temp16 = 0x11;
 
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -454,31 +449,31 @@
 	/*
 	 * Set the Range minimum base address
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.min_base_address);
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.min_base_address);
 	buffer += 4;
 
 	/*
 	 * Set the Range maximum base address
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.max_base_address);
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.max_base_address);
 	buffer += 4;
 
 	/*
 	 * Set the base alignment
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.alignment);
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.alignment);
 	buffer += 4;
 
 	/*
 	 * Set the range length
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.range_length);
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer, &linked_list->data.memory32.range_length);
 	buffer += 4;
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -489,9 +484,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -504,14 +498,14 @@
 acpi_rs_fixed_memory32_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_fixed_memory32_stream");
+	ACPI_FUNCTION_TRACE ("Rs_fixed_memory32_stream");
 
 
 	/*
@@ -525,7 +519,7 @@
 	 */
 	temp16 = 0x09;
 
-	MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+	ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 	buffer += 2;
 
 	/*
@@ -538,21 +532,21 @@
 	/*
 	 * Set the Range base address
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			 &linked_list->data.fixed_memory32.range_base_address);
 	buffer += 4;
 
 	/*
 	 * Set the range length
 	 */
-	MOVE_UNALIGNED32_TO_32 (buffer,
+	ACPI_MOVE_UNALIGNED32_TO_32 (buffer,
 			 &linked_list->data.fixed_memory32.range_length);
 	buffer += 4;
 
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
diff -Nru a/drivers/acpi/resources/rsmisc.c b/drivers/acpi/resources/rsmisc.c
--- a/drivers/acpi/resources/rsmisc.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/resources/rsmisc.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsmisc - Miscellaneous resource descriptors
- *              $Revision: 16 $
+ *              $Revision: 20 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsmisc")
+	 ACPI_MODULE_NAME    ("rsmisc")
 
 
 /*******************************************************************************
@@ -37,13 +37,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -56,15 +55,15 @@
 acpi_status
 acpi_rs_end_tag_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
-	u32                     struct_size = ACPI_RESOURCE_LENGTH;
+	ACPI_SIZE               struct_size = ACPI_RESOURCE_LENGTH;
 
 
-	FUNCTION_TRACE ("Rs_end_tag_resource");
+	ACPI_FUNCTION_TRACE ("Rs_end_tag_resource");
 
 
 	/*
@@ -96,9 +95,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -111,13 +109,13 @@
 acpi_rs_end_tag_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_end_tag_stream");
+	ACPI_FUNCTION_TRACE ("Rs_end_tag_stream");
 
 
 	/*
@@ -138,7 +136,7 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -149,13 +147,12 @@
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -168,19 +165,19 @@
 acpi_status
 acpi_rs_vendor_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u16                     temp16 = 0;
 	u8                      temp8 = 0;
 	u8                      index;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_vendor);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_vendor);
 
 
-	FUNCTION_TRACE ("Rs_vendor_resource");
+	ACPI_FUNCTION_TRACE ("Rs_vendor_resource");
 
 
 	/*
@@ -190,14 +187,13 @@
 
 	if (temp8 & 0x80) {
 		/*
-		 * Large Item
-		 * Point to the length field
+		 * Large Item, point to the length field
 		 */
 		buffer += 1;
 
 		/* Dereference */
 
-		MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
+		ACPI_MOVE_UNALIGNED16_TO_16 (&temp16, buffer);
 
 		/* Calculate bytes consumed */
 
@@ -207,11 +203,9 @@
 
 		buffer += 2;
 	}
-
 	else {
 		/*
-		 * Small Item
-		 * Dereference the size
+		 * Small Item, dereference the size
 		 */
 		temp16 = (u8)(*buffer & 0x07);
 
@@ -237,7 +231,7 @@
 	 * calculate the length of the vendor string and expand the
 	 * Struct_size to the next 32-bit boundary.
 	 */
-	struct_size += ROUND_UP_TO_32_bITS (temp16);
+	struct_size += ACPI_ROUND_UP_TO_32_bITS (temp16);
 
 	/*
 	 * Set the Length parameter
@@ -258,9 +252,8 @@
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -273,7 +266,7 @@
 acpi_rs_vendor_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u16                     temp16 = 0;
@@ -281,7 +274,7 @@
 	u8                      index;
 
 
-	FUNCTION_TRACE ("Rs_vendor_stream");
+	ACPI_FUNCTION_TRACE ("Rs_vendor_stream");
 
 
 	/*
@@ -289,22 +282,19 @@
 	 */
 	if(linked_list->data.vendor_specific.length > 7) {
 		/*
-		 * Large Item
-		 * Set the descriptor field and length bytes
+		 * Large Item, Set the descriptor field and length bytes
 		 */
 		*buffer = 0x84;
 		buffer += 1;
 
 		temp16 = (u16) linked_list->data.vendor_specific.length;
 
-		MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
+		ACPI_MOVE_UNALIGNED16_TO_16 (buffer, &temp16);
 		buffer += 2;
 	}
-
 	else {
 		/*
-		 * Small Item
-		 * Set the descriptor field
+		 * Small Item, Set the descriptor field
 		 */
 		temp8 = 0x70;
 		temp8 |= linked_list->data.vendor_specific.length;
@@ -326,24 +316,23 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_rs_start_dependent_functions_resource
+ * FUNCTION:    Acpi_rs_start_depend_fns_resource
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -354,19 +343,19 @@
  ******************************************************************************/
 
 acpi_status
-acpi_rs_start_dependent_functions_resource (
+acpi_rs_start_depend_fns_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	u8                      *buffer = byte_stream_buffer;
-	acpi_resource          *output_struct = (acpi_resource *) *output_buffer;
+	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
 	u8                      temp8 = 0;
-	u32                     struct_size = SIZEOF_RESOURCE (acpi_resource_start_dpf);
+	ACPI_SIZE               struct_size = ACPI_SIZEOF_RESOURCE (acpi_resource_start_dpf);
 
 
-	FUNCTION_TRACE ("Rs_start_dependent_functions_resource");
+	ACPI_FUNCTION_TRACE ("Rs_start_depend_fns_resource");
 
 
 	/*
@@ -403,13 +392,12 @@
 			return_ACPI_STATUS (AE_AML_ERROR);
 		}
 	}
-
 	else {
 		output_struct->data.start_dpf.compatibility_priority =
-				ACCEPTABLE_CONFIGURATION;
+				ACPI_ACCEPTABLE_CONFIGURATION;
 
 		output_struct->data.start_dpf.performance_robustness =
-				ACCEPTABLE_CONFIGURATION;
+				ACPI_ACCEPTABLE_CONFIGURATION;
 	}
 
 	/*
@@ -427,17 +415,16 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_rs_end_dependent_functions_resource
+ * FUNCTION:    Acpi_rs_end_depend_fns_resource
  *
  * PARAMETERS:  Byte_stream_buffer      - Pointer to the resource input byte
  *                                        stream
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes consumed from
- *                                        the Byte_stream_buffer
- *              Output_buffer           - Pointer to the user's return buffer
- *              Structure_size          - u32 pointer that is filled with
- *                                        the number of bytes in the filled
- *                                        in structure
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        consumed the Byte_stream_buffer is
+ *                                        returned
+ *              Output_buffer           - Pointer to the return data buffer
+ *              Structure_size          - Pointer to where the number of bytes
+ *                                        in the return data struct is returned
  *
  * RETURN:      Status
  *
@@ -448,17 +435,17 @@
  ******************************************************************************/
 
 acpi_status
-acpi_rs_end_dependent_functions_resource (
+acpi_rs_end_depend_fns_resource (
 	u8                      *byte_stream_buffer,
-	u32                     *bytes_consumed,
+	ACPI_SIZE               *bytes_consumed,
 	u8                      **output_buffer,
-	u32                     *structure_size)
+	ACPI_SIZE               *structure_size)
 {
 	acpi_resource           *output_struct = (acpi_resource *) *output_buffer;
-	u32                     struct_size = ACPI_RESOURCE_LENGTH;
+	ACPI_SIZE               struct_size = ACPI_RESOURCE_LENGTH;
 
 
-	FUNCTION_TRACE ("Rs_end_dependent_functions_resource");
+	ACPI_FUNCTION_TRACE ("Rs_end_depend_fns_resource");
 
 
 	/*
@@ -486,7 +473,7 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_rs_start_dependent_functions_stream
+ * FUNCTION:    Acpi_rs_start_depend_fns_stream
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
@@ -502,25 +489,25 @@
  ******************************************************************************/
 
 acpi_status
-acpi_rs_start_dependent_functions_stream (
+acpi_rs_start_depend_fns_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 	u8                      temp8 = 0;
 
 
-	FUNCTION_TRACE ("Rs_start_dependent_functions_stream");
+	ACPI_FUNCTION_TRACE ("Rs_start_depend_fns_stream");
 
 
 	/*
 	 * The descriptor field is set based upon whether a byte is needed
 	 * to contain Priority data.
 	 */
-	if (ACCEPTABLE_CONFIGURATION ==
+	if (ACPI_ACCEPTABLE_CONFIGURATION ==
 			linked_list->data.start_dpf.compatibility_priority &&
-		ACCEPTABLE_CONFIGURATION ==
+		ACPI_ACCEPTABLE_CONFIGURATION ==
 			linked_list->data.start_dpf.performance_robustness) {
 		*buffer = 0x30;
 	}
@@ -544,20 +531,19 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_rs_end_dependent_functions_stream
+ * FUNCTION:    Acpi_rs_end_depend_fns_stream
  *
  * PARAMETERS:  Linked_list             - Pointer to the resource linked list
  *              Output_buffer           - Pointer to the user's return buffer
- *              Bytes_consumed          - u32 pointer that is filled with
- *                                        the number of bytes of the
- *                                        Output_buffer used
+ *              Bytes_consumed          - Pointer to where the number of bytes
+ *                                        used in the Output_buffer is returned
  *
  * RETURN:      Status
  *
@@ -567,16 +553,15 @@
  ******************************************************************************/
 
 acpi_status
-acpi_rs_end_dependent_functions_stream (
+acpi_rs_end_depend_fns_stream (
 	acpi_resource           *linked_list,
 	u8                      **output_buffer,
-	u32                     *bytes_consumed
-	)
+	ACPI_SIZE               *bytes_consumed)
 {
 	u8                      *buffer = *output_buffer;
 
 
-	FUNCTION_TRACE ("Rs_end_dependent_functions_stream");
+	ACPI_FUNCTION_TRACE ("Rs_end_depend_fns_stream");
 
 
 	/*
@@ -588,7 +573,7 @@
 	/*
 	 * Return the number of bytes consumed in this operation
 	 */
-	*bytes_consumed = POINTER_DIFF (buffer, *output_buffer);
+	*bytes_consumed = ACPI_PTR_DIFF (buffer, *output_buffer);
 	return_ACPI_STATUS (AE_OK);
 }
 
diff -Nru a/drivers/acpi/resources/rsutils.c b/drivers/acpi/resources/rsutils.c
--- a/drivers/acpi/resources/rsutils.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/resources/rsutils.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsutils - Utilities for the resource manager
- *              $Revision: 23 $
+ *              $Revision: 29 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsutils")
+	 ACPI_MODULE_NAME    ("rsutils")
 
 
 /*******************************************************************************
@@ -58,15 +58,12 @@
 {
 	acpi_operand_object     *ret_obj;
 	acpi_status             status;
-	u32                     buffer_space_needed;
 
 
-	FUNCTION_TRACE ("Rs_get_prt_method_data");
+	ACPI_FUNCTION_TRACE ("Rs_get_prt_method_data");
 
 
-	/* already validated params, so we won't repeat here */
-
-	buffer_space_needed = ret_buffer->length;
+	/* Parameters guaranteed valid by caller */
 
 	/*
 	 *  Execute the method, no parameters
@@ -83,34 +80,25 @@
 		return_ACPI_STATUS (AE_TYPE);
 	}
 
-
 	/*
-	 * The return object will be a package, so check the
-	 *  parameters.  If the return object is not a package,
-	 *  then the underlying AML code is corrupt or improperly
-	 *  written.
+	 * The return object will be a package, so check the parameters.  If the
+	 * return object is not a package, then the underlying AML code is corrupt
+	 * or improperly written.
 	 */
 	if (ACPI_TYPE_PACKAGE != ret_obj->common.type) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_PRT did not return a Package, returned %s\n",
+				acpi_ut_get_type_name (ret_obj->common.type)));
 		status = AE_AML_OPERAND_TYPE;
 		goto cleanup;
 	}
 
 	/*
-	 * Make the call to create a resource linked list from the
-	 *  byte stream buffer that comes back from the _CRS method
-	 *  execution.
-	 */
-	status = acpi_rs_create_pci_routing_table (ret_obj, ret_buffer->pointer,
-			  &buffer_space_needed);
-
-	/*
-	 * Tell the user how much of the buffer we have used or is needed
-	 *  and return the final status.
+	 * Create a resource linked list from the byte stream buffer that comes
+	 * back from the _CRS method execution.
 	 */
-	ret_buffer->length = buffer_space_needed;
+	status = acpi_rs_create_pci_routing_table (ret_obj, ret_buffer);
 
-
-	/* On exit, we must delete the object returned by evaluate_object */
+	/* On exit, we must delete the object returned by Evaluate_object */
 
 cleanup:
 
@@ -144,16 +132,15 @@
 {
 	acpi_operand_object     *ret_obj;
 	acpi_status             status;
-	u32                     buffer_space_needed = ret_buffer->length;
 
 
-	FUNCTION_TRACE ("Rs_get_crs_method_data");
+	ACPI_FUNCTION_TRACE ("Rs_get_crs_method_data");
 
 
-	/* already validated params, so we won't repeat here */
+	/* Parameters guaranteed valid by caller */
 
 	/*
-	 *  Execute the method, no parameters
+	 * Execute the method, no parameters
 	 */
 	status = acpi_ns_evaluate_relative (handle, "_CRS", NULL, &ret_obj);
 	if (ACPI_FAILURE (status)) {
@@ -169,30 +156,23 @@
 
 	/*
 	 * The return object will be a buffer, but check the
-	 *  parameters.  If the return object is not a buffer,
-	 *  then the underlying AML code is corrupt or improperly
-	 *  written.
+	 * parameters.  If the return object is not a buffer,
+	 * then the underlying AML code is corrupt or improperly
+	 * written.
 	 */
 	if (ACPI_TYPE_BUFFER != ret_obj->common.type) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_CRS did not return a Buffer, returned %s\n",
+				acpi_ut_get_type_name (ret_obj->common.type)));
 		status = AE_AML_OPERAND_TYPE;
 		goto cleanup;
 	}
 
 	/*
 	 * Make the call to create a resource linked list from the
-	 *  byte stream buffer that comes back from the _CRS method
-	 *  execution.
+	 * byte stream buffer that comes back from the _CRS method
+	 * execution.
 	 */
-	status = acpi_rs_create_resource_list (ret_obj, ret_buffer->pointer,
-			 &buffer_space_needed);
-
-
-	/*
-	 * Tell the user how much of the buffer we have used or is needed
-	 *  and return the final status.
-	 */
-	ret_buffer->length = buffer_space_needed;
-
+	status = acpi_rs_create_resource_list (ret_obj, ret_buffer);
 
 	/* On exit, we must delete the object returned by evaluate_object */
 
@@ -228,16 +208,15 @@
 {
 	acpi_operand_object     *ret_obj;
 	acpi_status             status;
-	u32                     buffer_space_needed = ret_buffer->length;
 
 
-	FUNCTION_TRACE ("Rs_get_prs_method_data");
+	ACPI_FUNCTION_TRACE ("Rs_get_prs_method_data");
 
 
-	/* already validated params, so we won't repeat here */
+	/* Parameters guaranteed valid by caller */
 
 	/*
-	 *  Execute the method, no parameters
+	 * Execute the method, no parameters
 	 */
 	status = acpi_ns_evaluate_relative (handle, "_PRS", NULL, &ret_obj);
 	if (ACPI_FAILURE (status)) {
@@ -253,29 +232,23 @@
 
 	/*
 	 * The return object will be a buffer, but check the
-	 *  parameters.  If the return object is not a buffer,
-	 *  then the underlying AML code is corrupt or improperly
-	 *  written..
+	 * parameters.  If the return object is not a buffer,
+	 * then the underlying AML code is corrupt or improperly
+	 * written..
 	 */
 	if (ACPI_TYPE_BUFFER != ret_obj->common.type) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_PRS did not return a Buffer, returned %s\n",
+				acpi_ut_get_type_name (ret_obj->common.type)));
 		status = AE_AML_OPERAND_TYPE;
 		goto cleanup;
 	}
 
 	/*
 	 * Make the call to create a resource linked list from the
-	 *  byte stream buffer that comes back from the _CRS method
-	 *  execution.
-	 */
-	status = acpi_rs_create_resource_list (ret_obj, ret_buffer->pointer,
-			 &buffer_space_needed);
-
-	/*
-	 * Tell the user how much of the buffer we have used or is needed
-	 *  and return the final status.
+	 * byte stream buffer that comes back from the _CRS method
+	 * execution.
 	 */
-	ret_buffer->length = buffer_space_needed;
-
+	status = acpi_rs_create_resource_list (ret_obj, ret_buffer);
 
 	/* On exit, we must delete the object returned by evaluate_object */
 
@@ -311,50 +284,25 @@
 {
 	acpi_operand_object     *params[2];
 	acpi_status             status;
-	u8                      *byte_stream = NULL;
-	u32                     buffer_size_needed = 0;
+	acpi_buffer             buffer;
 
 
-	FUNCTION_TRACE ("Rs_set_srs_method_data");
+	ACPI_FUNCTION_TRACE ("Rs_set_srs_method_data");
 
 
-	/* already validated params, so we won't repeat here */
+	/* Parameters guaranteed valid by caller */
 
 	/*
 	 * The In_buffer parameter will point to a linked list of
 	 * resource parameters.  It needs to be formatted into a
-	 * byte stream to be sent in as an input parameter.
-	 */
-	buffer_size_needed = 0;
-
-	/*
-	 * First call is to get the buffer size needed
-	 */
-	status = acpi_rs_create_byte_stream (in_buffer->pointer, byte_stream,
-			 &buffer_size_needed);
-	/*
-	 * We expect a return of AE_BUFFER_OVERFLOW
-	 * if not, exit with the error
+	 * byte stream to be sent in as an input parameter to _SRS
+	 *
+	 * Convert the linked list into a byte stream
 	 */
-	if (AE_BUFFER_OVERFLOW != status) {
-		return_ACPI_STATUS (status);
-	}
-
-	/*
-	 * Allocate the buffer needed
-	 */
-	byte_stream = ACPI_MEM_CALLOCATE (buffer_size_needed);
-	if (NULL == byte_stream) {
-		return_ACPI_STATUS (AE_NO_MEMORY);
-	}
-
-	/*
-	 * Now call to convert the linked list into a byte stream
-	 */
-	status = acpi_rs_create_byte_stream (in_buffer->pointer, byte_stream,
-			 &buffer_size_needed);
+	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
+	status = acpi_rs_create_byte_stream (in_buffer->pointer, &buffer);
 	if (ACPI_FAILURE (status)) {
-		goto cleanup;
+		return_ACPI_STATUS (status);
 	}
 
 	/*
@@ -362,28 +310,26 @@
 	 */
 	params[0] = acpi_ut_create_internal_object (ACPI_TYPE_BUFFER);
 	if (!params[0]) {
-		status = AE_NO_MEMORY;
-		goto cleanup;
+		acpi_os_free (buffer.pointer);
+		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
-	params [1] = NULL;
 
 	/*
-	 *  Set up the parameter object
+	 * Set up the parameter object
 	 */
-	params[0]->buffer.length  = buffer_size_needed;
-	params[0]->buffer.pointer = byte_stream;
+	params[0]->buffer.length  = buffer.length;
+	params[0]->buffer.pointer = buffer.pointer;
+	params[1] = NULL;
 
 	/*
 	 * Execute the method, no return value
 	 */
 	status = acpi_ns_evaluate_relative (handle, "_SRS", params, NULL);
-	acpi_ut_remove_reference (params[0]);
 
 	/*
 	 * Clean up and return the status from Acpi_ns_evaluate_relative
 	 */
-cleanup:
-
+	acpi_ut_remove_reference (params[0]);
 	return_ACPI_STATUS (status);
 }
 
diff -Nru a/drivers/acpi/resources/rsxface.c b/drivers/acpi/resources/rsxface.c
--- a/drivers/acpi/resources/rsxface.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/resources/rsxface.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: rsxface - Public interfaces to the resource manager
- *              $Revision: 15 $
+ *              $Revision: 18 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 #include "acresrc.h"
 
 #define _COMPONENT          ACPI_RESOURCES
-	 MODULE_NAME         ("rsxface")
+	 ACPI_MODULE_NAME    ("rsxface")
 
 
 /*******************************************************************************
@@ -64,7 +64,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_get_irq_routing_table ");
+	ACPI_FUNCTION_TRACE ("Acpi_get_irq_routing_table ");
 
 
 	/*
@@ -73,12 +73,15 @@
 	 * we also need a valid pointer in the buffer. If it's a zero buffer length,
 	 * we'll be returning the needed buffer size, so keep going.
 	 */
-	if ((!device_handle)        ||
-		(!ret_buffer)           ||
-		((!ret_buffer->pointer) && (ret_buffer->length))) {
+	if (!device_handle) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	status = acpi_ut_validate_buffer (ret_buffer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	status = acpi_rs_get_prt_method_data (device_handle, ret_buffer);
 	return_ACPI_STATUS (status);
 }
@@ -116,7 +119,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_get_current_resources");
+	ACPI_FUNCTION_TRACE ("Acpi_get_current_resources");
 
 
 	/*
@@ -125,12 +128,15 @@
 	 * we also need a valid pointer in the buffer. If it's a zero buffer length,
 	 * we'll be returning the needed buffer size, so keep going.
 	 */
-	if ((!device_handle)        ||
-		(!ret_buffer)           ||
-		((ret_buffer->length) && (!ret_buffer->pointer))) {
+	if (!device_handle) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	status = acpi_ut_validate_buffer (ret_buffer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	status = acpi_rs_get_crs_method_data (device_handle, ret_buffer);
 	return_ACPI_STATUS (status);
 }
@@ -165,7 +171,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_get_possible_resources");
+	ACPI_FUNCTION_TRACE ("Acpi_get_possible_resources");
 
 
 	/*
@@ -174,12 +180,15 @@
 	 * we also need a valid pointer in the buffer. If it's a zero buffer length,
 	 * we'll be returning the needed buffer size, so keep going.
 	 */
-	if ((!device_handle)        ||
-		(!ret_buffer)           ||
-		((ret_buffer->length) && (!ret_buffer->pointer))) {
+	if (!device_handle) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	status = acpi_ut_validate_buffer (ret_buffer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	status = acpi_rs_get_prs_method_data (device_handle, ret_buffer);
 	return_ACPI_STATUS (status);
 }
@@ -211,7 +220,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_set_current_resources");
+	ACPI_FUNCTION_TRACE ("Acpi_set_current_resources");
 
 
 	/*
diff -Nru a/drivers/acpi/tables/Makefile b/drivers/acpi/tables/Makefile
--- a/drivers/acpi/tables/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/tables/Makefile	Fri Mar 15 17:51:01 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/tables/tbconvrt.c b/drivers/acpi/tables/tbconvrt.c
--- a/drivers/acpi/tables/tbconvrt.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/tables/tbconvrt.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: tbconvrt - ACPI Table conversion utilities
- *              $Revision: 28 $
+ *              $Revision: 36 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -25,13 +25,11 @@
 
 
 #include "acpi.h"
-#include "achware.h"
 #include "actables.h"
-#include "actbl.h"
 
 
 #define _COMPONENT          ACPI_TABLES
-	 MODULE_NAME         ("tbconvrt")
+	 ACPI_MODULE_NAME    ("tbconvrt")
 
 
 /*******************************************************************************
@@ -54,7 +52,7 @@
 	u32                     pointer_size;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 #ifndef _IA64
@@ -62,7 +60,6 @@
 	if (RSDP->revision < 2) {
 		pointer_size = sizeof (u32);
 	}
-
 	else
 #endif
 	{
@@ -101,17 +98,17 @@
 	xsdt_descriptor         *new_table;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	*number_of_tables = acpi_tb_get_table_count (acpi_gbl_RSDP, table_info->pointer);
+	/* Get the number of tables defined in the RSDT or XSDT */
 
+	*number_of_tables = acpi_tb_get_table_count (acpi_gbl_RSDP, table_info->pointer);
 
 	/* Compute size of the converted XSDT */
 
 	table_size = (*number_of_tables * sizeof (u64)) + sizeof (acpi_table_header);
 
-
 	/* Allocate an XSDT */
 
 	new_table = ACPI_MEM_CALLOCATE (table_size);
@@ -121,20 +118,15 @@
 
 	/* Copy the header and set the length */
 
-	MEMCPY (new_table, table_info->pointer, sizeof (acpi_table_header));
+	ACPI_MEMCPY (new_table, table_info->pointer, sizeof (acpi_table_header));
 	new_table->header.length = table_size;
 
 	/* Copy the table pointers */
 
 	for (i = 0; i < *number_of_tables; i++) {
 		if (acpi_gbl_RSDP->revision < 2) {
-#ifdef _IA64
-			new_table->table_offset_entry[i] =
-				((RSDT_DESCRIPTOR_REV071 *) table_info->pointer)->table_offset_entry[i];
-#else
 			ACPI_STORE_ADDRESS (new_table->table_offset_entry[i],
 				((RSDT_DESCRIPTOR_REV1 *) table_info->pointer)->table_offset_entry[i]);
-#endif
 		}
 		else {
 			new_table->table_offset_entry[i] =
@@ -142,12 +134,10 @@
 		}
 	}
 
-
 	/* Delete the original table (either mapped or in a buffer) */
 
 	acpi_tb_delete_single_table (table_info);
 
-
 	/* Point the table descriptor to the new table */
 
 	table_info->pointer     = (acpi_table_header *) new_table;
@@ -163,12 +153,12 @@
  *
  * FUNCTION:    Acpi_tb_convert_table_fadt
  *
- * PARAMETERS:
+ * PARAMETERS:  None
  *
- * RETURN:
+ * RETURN:      Status
  *
  * DESCRIPTION:
- *    Converts BIOS supplied 1.0 and 0.71 ACPI FADT to an intermediate
+ *    Converts a BIOS supplied ACPI 1.0 FADT to an intermediate
  *    ACPI 2.0 FADT. If the BIOS supplied a 2.0 FADT then it is simply
  *    copied to the intermediate FADT.  The ACPI CA software uses this
  *    intermediate FADT. Thus a significant amount of special #ifdef
@@ -180,254 +170,84 @@
 acpi_status
 acpi_tb_convert_table_fadt (void)
 {
-
-#ifdef _IA64
-	fadt_descriptor_rev071 *FADT71;
-	u8                      pm1_address_space;
-	u8                      pm2_address_space;
-	u8                      pm_timer_address_space;
-	u8                      gpe0address_space;
-	u8                      gpe1_address_space;
-#else
 	fadt_descriptor_rev1   *FADT1;
-#endif
-
 	fadt_descriptor_rev2   *FADT2;
 	acpi_table_desc        *table_desc;
 
 
-	FUNCTION_TRACE ("Tb_convert_table_fadt");
-
+	ACPI_FUNCTION_TRACE ("Tb_convert_table_fadt");
 
-	/* Acpi_gbl_FADT is valid */
-	/* Allocate and zero the 2.0 buffer */
 
+	/*
+	 * Acpi_gbl_FADT is valid
+	 * Allocate and zero the 2.0 FADT buffer
+	 */
 	FADT2 = ACPI_MEM_CALLOCATE (sizeof (fadt_descriptor_rev2));
 	if (FADT2 == NULL) {
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
-
-	/* The ACPI FADT revision number is FADT2_REVISION_ID=3 */
-	/* So, if the current table revision is less than 3 it is type 1.0 or 0.71 */
-
+	/*
+	 * The ACPI FADT revision number is FADT2_REVISION_ID=3
+	 * So, if the current table revision is less than 3 it is type 1.0
+	 */
 	if (acpi_gbl_FADT->header.revision >= FADT2_REVISION_ID) {
 		/* We have an ACPI 2.0 FADT but we must copy it to our local buffer */
 
 		*FADT2 = *((fadt_descriptor_rev2*) acpi_gbl_FADT);
-
 	}
-
 	else {
-
-#ifdef _IA64
-		/*
-		 * For the 64-bit case only, a revision ID less than V2.0 means the
-		 * tables are the 0.71 extensions
-		 */
-
-		/* The BIOS stored FADT should agree with Revision 0.71 */
-
-		FADT71 = (fadt_descriptor_rev071 *) acpi_gbl_FADT;
-
-		/* Copy the table header*/
-
-		FADT2->header       = FADT71->header;
-
-		/* Copy the common fields */
-
-		FADT2->sci_int      = FADT71->sci_int;
-		FADT2->acpi_enable  = FADT71->acpi_enable;
-		FADT2->acpi_disable = FADT71->acpi_disable;
-		FADT2->S4bios_req   = FADT71->S4bios_req;
-		FADT2->plvl2_lat    = FADT71->plvl2_lat;
-		FADT2->plvl3_lat    = FADT71->plvl3_lat;
-		FADT2->day_alrm     = FADT71->day_alrm;
-		FADT2->mon_alrm     = FADT71->mon_alrm;
-		FADT2->century      = FADT71->century;
-		FADT2->gpe1_base    = FADT71->gpe1_base;
-
-		/*
-		 * We still use the block length registers even though
-		 * the GAS structure should obsolete them.  This is because
-		 * these registers are byte lengths versus the GAS which
-		 * contains a bit width
-		 */
-		FADT2->pm1_evt_len  = FADT71->pm1_evt_len;
-		FADT2->pm1_cnt_len  = FADT71->pm1_cnt_len;
-		FADT2->pm2_cnt_len  = FADT71->pm2_cnt_len;
-		FADT2->pm_tm_len    = FADT71->pm_tm_len;
-		FADT2->gpe0blk_len  = FADT71->gpe0blk_len;
-		FADT2->gpe1_blk_len = FADT71->gpe1_blk_len;
-		FADT2->gpe1_base    = FADT71->gpe1_base;
-
-		/* Copy the existing 0.71 flags to 2.0. The other bits are zero.*/
-
-		FADT2->wb_invd      = FADT71->flush_cash;
-		FADT2->proc_c1      = FADT71->proc_c1;
-		FADT2->plvl2_up     = FADT71->plvl2_up;
-		FADT2->pwr_button   = FADT71->pwr_button;
-		FADT2->sleep_button = FADT71->sleep_button;
-		FADT2->fixed_rTC    = FADT71->fixed_rTC;
-		FADT2->rtcs4        = FADT71->rtcs4;
-		FADT2->tmr_val_ext  = FADT71->tmr_val_ext;
-		FADT2->dock_cap     = FADT71->dock_cap;
-
-
-		/* We should not use these next two addresses */
-		/* Since our buffer is pre-zeroed nothing to do for */
-		/* the next three data items in the structure */
-		/* FADT2->Firmware_ctrl = 0; */
-		/* FADT2->Dsdt = 0; */
-
-		/* System Interrupt Model isn't used in ACPI 2.0*/
-		/* FADT2->Reserved1 = 0; */
-
-		/* This field is set by the OEM to convey the preferred */
-		/* power management profile to OSPM. It doesn't have any*/
-		/* 0.71 equivalence.  Since we don't know what kind of  */
-		/* 64-bit system this is, we will pick unspecified.     */
-
-		FADT2->prefer_PM_profile = PM_UNSPECIFIED;
-
-
-		/* Port address of SMI command port */
-		/* We shouldn't use this port because IA64 doesn't */
-		/* have or use SMI.  It has PMI. */
-
-		FADT2->smi_cmd      = (u32)(FADT71->smi_cmd & 0xFFFFFFFF);
-
-
-		/* processor performance state control*/
-		/* The value OSPM writes to the SMI_CMD register to assume */
-		/* processor performance state control responsibility. */
-		/* There isn't any equivalence in 0.71 */
-		/* Again this should be meaningless for IA64 */
-		/* FADT2->Pstate_cnt = 0; */
-
-		/* The 32-bit Power management and GPE registers are */
-		/* not valid in IA-64 and we are not going to use them */
-		/* so leaving them pre-zeroed. */
-
-		/* Support for the _CST object and C States change notification.*/
-		/* This data item hasn't any 0.71 equivalence so leaving it zero.*/
-		/* FADT2->Cst_cnt = 0; */
-
-		/* number of flush strides that need to be read */
-		/* No 0.71 equivalence. Leave pre-zeroed. */
-		/* FADT2->Flush_size = 0; */
-
-		/* Processor's memory cache line width, in bytes */
-		/* No 0.71 equivalence. Leave pre-zeroed. */
-		/* FADT2->Flush_stride = 0; */
-
-		/* Processor's duty cycle index in processor's P_CNT reg*/
-		/* No 0.71 equivalence. Leave pre-zeroed. */
-		/* FADT2->Duty_offset = 0; */
-
-		/* Processor's duty cycle value bit width in P_CNT register.*/
-		/* No 0.71 equivalence. Leave pre-zeroed. */
-		/* FADT2->Duty_width = 0; */
-
-
-		/* Since there isn't any equivalence in 0.71 */
-		/* and since Big_sur had to support legacy */
-
-		FADT2->iapc_boot_arch = BAF_LEGACY_DEVICES;
-
-		/* Copy to ACPI 2.0 64-BIT Extended Addresses */
-
-		FADT2->Xfirmware_ctrl = FADT71->firmware_ctrl;
-		FADT2->Xdsdt         = FADT71->dsdt;
-
-
-		/* Extract the address space IDs */
-
-		pm1_address_space   = (u8)((FADT71->address_space & PM1_BLK_ADDRESS_SPACE)    >> 1);
-		pm2_address_space   = (u8)((FADT71->address_space & PM2_CNT_BLK_ADDRESS_SPACE) >> 2);
-		pm_timer_address_space = (u8)((FADT71->address_space & PM_TMR_BLK_ADDRESS_SPACE) >> 3);
-		gpe0address_space   = (u8)((FADT71->address_space & GPE0_BLK_ADDRESS_SPACE)   >> 4);
-		gpe1_address_space  = (u8)((FADT71->address_space & GPE1_BLK_ADDRESS_SPACE)   >> 5);
-
-		/*
-		 * Convert the 0.71 (non-GAS style) Block addresses to V2.0 GAS structures,
-		 * in this order:
-		 *
-		 * PM 1_a Events
-		 * PM 1_b Events
-		 * PM 1_a Control
-		 * PM 1_b Control
-		 * PM 2 Control
-		 * PM Timer Control
-		 * GPE Block 0
-		 * GPE Block 1
-		 */
-
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1a_evt_blk, FADT71->pm1_evt_len, FADT71->pm1a_evt_blk, pm1_address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1b_evt_blk, FADT71->pm1_evt_len, FADT71->pm1b_evt_blk, pm1_address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1a_cnt_blk, FADT71->pm1_cnt_len, FADT71->pm1a_cnt_blk, pm1_address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm1b_cnt_blk, FADT71->pm1_cnt_len, FADT71->pm1b_cnt_blk, pm1_address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm2_cnt_blk, FADT71->pm2_cnt_len, FADT71->pm2_cnt_blk, pm2_address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xpm_tmr_blk, FADT71->pm_tm_len,  FADT71->pm_tmr_blk, pm_timer_address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xgpe0blk,    FADT71->gpe0blk_len, FADT71->gpe0blk,   gpe0address_space);
-		ASL_BUILD_GAS_FROM_ENTRY (FADT2->Xgpe1_blk,   FADT71->gpe1_blk_len, FADT71->gpe1_blk, gpe1_address_space);
-
-#else
-
 		/* ACPI 1.0 FACS */
 
-
 		/* The BIOS stored FADT should agree with Revision 1.0 */
 
 		FADT1 = (fadt_descriptor_rev1*) acpi_gbl_FADT;
 
 		/*
-		 * Copy the table header and the common part of the tables
-		 * The 2.0 table is an extension of the 1.0 table, so the
-		 * entire 1.0 table can be copied first, then expand some
-		 * fields to 64 bits.
+		 * Copy the table header and the common part of the tables.
+		 *
+		 * The 2.0 table is an extension of the 1.0 table, so the entire 1.0
+		 * table can be copied first, then expand some fields to 64 bits.
 		 */
-		MEMCPY (FADT2, FADT1, sizeof (fadt_descriptor_rev1));
-
+		ACPI_MEMCPY (FADT2, FADT1, sizeof (fadt_descriptor_rev1));
 
 		/* Convert table pointers to 64-bit fields */
 
 		ACPI_STORE_ADDRESS (FADT2->Xfirmware_ctrl, FADT1->firmware_ctrl);
 		ACPI_STORE_ADDRESS (FADT2->Xdsdt, FADT1->dsdt);
 
-		/* System Interrupt Model isn't used in ACPI 2.0*/
-		/* FADT2->Reserved1 = 0; */
-
-		/* This field is set by the OEM to convey the preferred */
-		/* power management profile to OSPM. It doesn't have any*/
-		/* 1.0 equivalence.  Since we don't know what kind of   */
-		/* 32-bit system this is, we will pick unspecified.     */
+		/*
+		 * System Interrupt Model isn't used in ACPI 2.0 (FADT2->Reserved1 = 0;)
+		 */
 
+		/*
+		 * This field is set by the OEM to convey the preferred power management
+		 * profile to OSPM. It doesn't have any 1.0 equivalence.  Since we don't
+		 * know what kind of 32-bit system this is, we will use "unspecified".
+		 */
 		FADT2->prefer_PM_profile = PM_UNSPECIFIED;
 
-
-		/* Processor Performance State Control. This is the value  */
-		/* OSPM writes to the SMI_CMD register to assume processor */
-		/* performance state control responsibility. There isn't   */
-		/* any equivalence in 1.0.  So leave it zeroed.            */
-
+		/*
+		 * Processor Performance State Control. This is the value OSPM writes to
+		 * the SMI_CMD register to assume processor performance state control
+		 * responsibility. There isn't any equivalence in 1.0, leave it zeroed.
+		 */
 		FADT2->pstate_cnt = 0;
 
-
-		/* Support for the _CST object and C States change notification.*/
-		/* This data item hasn't any 1.0 equivalence so leaving it zero.*/
-
+		/*
+		 * Support for the _CST object and C States change notification.
+		 * This data item hasn't any 1.0 equivalence so leave it zero.
+		 */
 		FADT2->cst_cnt = 0;
 
-
-		/* Since there isn't any equivalence in 1.0 and since it   */
-		/* is highly likely that a 1.0 system has legacy  support. */
-
+		/*
+		 * Since there isn't any equivalence in 1.0 and since it highly likely
+		 * that a 1.0 system has legacy support.
+		 */
 		FADT2->iapc_boot_arch = BAF_LEGACY_DEVICES;
 
-
 		/*
-		 * Convert the V1.0 Block addresses to V2.0 GAS structures
+		 * Convert the V1.0 block addresses to V2.0 GAS structures
 		 * in this order:
 		 *
 		 * PM 1_a Events
@@ -439,32 +259,27 @@
 		 * GPE Block 0
 		 * GPE Block 1
 		 */
-
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1a_evt_blk, FADT1->pm1_evt_len, FADT1->pm1a_evt_blk);
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1b_evt_blk, FADT1->pm1_evt_len, FADT1->pm1b_evt_blk);
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1a_cnt_blk, FADT1->pm1_cnt_len, FADT1->pm1a_cnt_blk);
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm1b_cnt_blk, FADT1->pm1_cnt_len, FADT1->pm1b_cnt_blk);
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm2_cnt_blk, FADT1->pm2_cnt_len, FADT1->pm2_cnt_blk);
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xpm_tmr_blk, FADT1->pm_tm_len,  FADT1->pm_tmr_blk);
-		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xgpe0blk,    FADT1->gpe0blk_len, FADT1->gpe0blk);
+		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xgpe0_blk,   FADT1->gpe0_blk_len, FADT1->gpe0_blk);
 		ASL_BUILD_GAS_FROM_V1_ENTRY (FADT2->Xgpe1_blk,   FADT1->gpe1_blk_len, FADT1->gpe1_blk);
-#endif
 	}
 
-
 	/*
 	 * Global FADT pointer will point to the common V2.0 FADT
 	 */
 	acpi_gbl_FADT = FADT2;
 	acpi_gbl_FADT->header.length = sizeof (FADT_DESCRIPTOR);
 
-
 	/* Free the original table */
 
 	table_desc = &acpi_gbl_acpi_tables[ACPI_TABLE_FADT];
 	acpi_tb_delete_single_table (table_desc);
 
-
 	/* Install the new table */
 
 	table_desc->pointer = (acpi_table_header *) acpi_gbl_FADT;
@@ -472,14 +287,12 @@
 	table_desc->allocation = ACPI_MEM_ALLOCATED;
 	table_desc->length = sizeof (fadt_descriptor_rev2);
 
-
 	/* Dump the entire FADT */
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_TABLES,
 		"Hex dump of common internal FADT, size %d (%X)\n",
 		acpi_gbl_FADT->header.length, acpi_gbl_FADT->header.length));
-	DUMP_BUFFER ((u8 *) (acpi_gbl_FADT), acpi_gbl_FADT->header.length);
-
+	ACPI_DUMP_BUFFER ((u8 *) (acpi_gbl_FADT), acpi_gbl_FADT->header.length);
 
 	return_ACPI_STATUS (AE_OK);
 }
@@ -489,11 +302,12 @@
  *
  * FUNCTION:    Acpi_tb_convert_table_facs
  *
- * PARAMETERS:
+ * PARAMETERS:  Table_info      - Info for currently installad FACS
  *
- * RETURN:
+ * RETURN:      Status
  *
- * DESCRIPTION:
+ * DESCRIPTION: Convert ACPI 1.0 and ACPI 2.0 FACS to a common internal
+ *              table format.
  *
  ******************************************************************************/
 
@@ -501,66 +315,33 @@
 acpi_tb_build_common_facs (
 	acpi_table_desc         *table_info)
 {
-	acpi_common_facs        *common_facs;
-
-#ifdef _IA64
-	facs_descriptor_rev071  *FACS71;
-#else
 	facs_descriptor_rev1    *FACS1;
-#endif
-
 	facs_descriptor_rev2    *FACS2;
 
 
-	FUNCTION_TRACE ("Tb_build_common_facs");
-
-
-	/* Allocate a common FACS */
-
-	common_facs = ACPI_MEM_CALLOCATE (sizeof (acpi_common_facs));
-	if (!common_facs) {
-		return_ACPI_STATUS (AE_NO_MEMORY);
-	}
+	ACPI_FUNCTION_TRACE ("Tb_build_common_facs");
 
 
 	/* Copy fields to the new FACS */
 
 	if (acpi_gbl_RSDP->revision < 2) {
-#ifdef _IA64
-		/* 0.71 FACS */
-
-		FACS71 = (facs_descriptor_rev071 *) acpi_gbl_FACS;
-
-		common_facs->global_lock = (u32 *) &(FACS71->global_lock);
-		common_facs->firmware_waking_vector = &FACS71->firmware_waking_vector;
-		common_facs->vector_width = 64;
-#else
 		/* ACPI 1.0 FACS */
 
 		FACS1 = (facs_descriptor_rev1 *) acpi_gbl_FACS;
 
-		common_facs->global_lock = &(FACS1->global_lock);
-		common_facs->firmware_waking_vector = (u64 *) &FACS1->firmware_waking_vector;
-		common_facs->vector_width = 32;
-
-#endif
+		acpi_gbl_common_fACS.global_lock = &(FACS1->global_lock);
+		acpi_gbl_common_fACS.firmware_waking_vector = (u64 *) &FACS1->firmware_waking_vector;
+		acpi_gbl_common_fACS.vector_width = 32;
 	}
-
 	else {
 		/* ACPI 2.0 FACS */
 
 		FACS2 = (facs_descriptor_rev2 *) acpi_gbl_FACS;
 
-		common_facs->global_lock = &(FACS2->global_lock);
-		common_facs->firmware_waking_vector = &FACS2->Xfirmware_waking_vector;
-		common_facs->vector_width = 64;
+		acpi_gbl_common_fACS.global_lock = &(FACS2->global_lock);
+		acpi_gbl_common_fACS.firmware_waking_vector = &FACS2->Xfirmware_waking_vector;
+		acpi_gbl_common_fACS.vector_width = 64;
 	}
-
-
-	/* Set the global FACS pointer to point to the common FACS */
-
-
-	acpi_gbl_FACS = common_facs;
 
 	return_ACPI_STATUS  (AE_OK);
 }
diff -Nru a/drivers/acpi/tables/tbget.c b/drivers/acpi/tables/tbget.c
--- a/drivers/acpi/tables/tbget.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/tables/tbget.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: tbget - ACPI Table get* routines
- *              $Revision: 56 $
+ *              $Revision: 63 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -25,14 +25,11 @@
 
 
 #include "acpi.h"
-#include "achware.h"
 #include "actables.h"
 
 
 #define _COMPONENT          ACPI_TABLES
-	 MODULE_NAME         ("tbget")
-
-#define RSDP_CHECKSUM_LENGTH 20
+	 ACPI_MODULE_NAME    ("tbget")
 
 
 /*******************************************************************************
@@ -60,7 +57,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE ("Tb_get_table_ptr");
+	ACPI_FUNCTION_TRACE ("Tb_get_table_ptr");
 
 
 	if (!acpi_gbl_DSDT) {
@@ -71,7 +68,6 @@
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	/*
 	 * For all table types (Single/Multiple), the first
 	 * instance is always in the list head.
@@ -85,7 +81,6 @@
 		return_ACPI_STATUS (AE_OK);
 	}
 
-
 	/*
 	 * Check for instance out of range
 	 */
@@ -141,14 +136,13 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Tb_get_table");
+	ACPI_FUNCTION_TRACE ("Tb_get_table");
 
 
 	if (!table_info) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
-
 	if (buffer_ptr) {
 		/*
 		 * Getting data from a buffer, not BIOS tables
@@ -171,14 +165,13 @@
 		/* Copy the entire table (including header) to the local buffer */
 
 		size = table_header->length;
-		MEMCPY (full_table, buffer_ptr, size);
+		ACPI_MEMCPY (full_table, buffer_ptr, size);
 
 		/* Save allocation type */
 
 		allocation = ACPI_MEM_ALLOCATED;
 	}
 
-
 	/*
 	 * Not reading from a buffer, just map the table's physical memory
 	 * into our address space.
@@ -196,7 +189,6 @@
 		allocation = ACPI_MEM_MAPPED;
 	}
 
-
 	/* Return values */
 
 	table_info->pointer     = full_table;
@@ -232,7 +224,7 @@
 	acpi_table_desc         table_info;
 
 
-	FUNCTION_TRACE ("Tb_get_all_tables");
+	ACPI_FUNCTION_TRACE ("Tb_get_all_tables");
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Number of tables: %d\n", number_of_tables));
 
@@ -245,7 +237,7 @@
 	for (index = 0; index < number_of_tables; index++) {
 		/* Clear the Table_info each time */
 
-		MEMSET (&table_info, 0, sizeof (acpi_table_desc));
+		ACPI_MEMSET (&table_info, 0, sizeof (acpi_table_desc));
 
 		/* Get the table via the XSDT */
 
@@ -278,7 +270,6 @@
 		}
 	}
 
-
 	/*
 	 * Convert the FADT to a common format.  This allows earlier revisions of the
 	 * table to coexist with newer versions, using common access code.
@@ -288,7 +279,6 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/*
 	 * Get the minimum set of ACPI tables, namely:
 	 *
@@ -323,7 +313,6 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/*
 	 * Get the DSDT (We know that the FADT is valid now)
 	 */
@@ -343,26 +332,18 @@
 	/* Dump the DSDT Header */
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_TABLES, "Hex dump of DSDT Header:\n"));
-	DUMP_BUFFER ((u8 *) acpi_gbl_DSDT, sizeof (acpi_table_header));
+	ACPI_DUMP_BUFFER ((u8 *) acpi_gbl_DSDT, sizeof (acpi_table_header));
 
 	/* Dump the entire DSDT */
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_TABLES,
 		"Hex dump of DSDT (After header), size %d (%x)\n",
 		acpi_gbl_DSDT->length, acpi_gbl_DSDT->length));
-	DUMP_BUFFER ((u8 *) (acpi_gbl_DSDT + 1), acpi_gbl_DSDT->length);
-
-	/*
-	 * Initialize the capabilities flags.
-	 * Assumes that platform supports ACPI_MODE since we have tables!
-	 */
-	acpi_gbl_system_flags |= acpi_hw_get_mode_capabilities ();
-
+	ACPI_DUMP_BUFFER ((u8 *) (acpi_gbl_DSDT + 1), acpi_gbl_DSDT->length);
 
 	/* Always delete the RSDP mapping, we are done with it */
 
 	acpi_tb_delete_acpi_table (ACPI_TABLE_RSDP);
-
 	return_ACPI_STATUS (status);
 }
 
@@ -385,17 +366,17 @@
 {
 	acpi_table_desc         table_info;
 	acpi_status             status;
-	u8                      *table_ptr;
+	RSDP_DESCRIPTOR         *rsdp;
 
 
-	FUNCTION_TRACE ("Tb_verify_rsdp");
+	ACPI_FUNCTION_TRACE ("Tb_verify_rsdp");
 
 
 	/*
 	 * Obtain access to the RSDP structure
 	 */
 	status = acpi_os_map_memory (rsdp_physical_address, sizeof (RSDP_DESCRIPTOR),
-			  (void **) &table_ptr);
+			  (void **) &rsdp);
 	if (ACPI_FAILURE (status)) {
 		return_ACPI_STATUS (status);
 	}
@@ -403,28 +384,36 @@
 	/*
 	 *  The signature and checksum must both be correct
 	 */
-	if (STRNCMP ((NATIVE_CHAR *) table_ptr, RSDP_SIG, sizeof (RSDP_SIG)-1) != 0) {
+	if (ACPI_STRNCMP ((NATIVE_CHAR *) rsdp, RSDP_SIG, sizeof (RSDP_SIG)-1) != 0) {
 		/* Nope, BAD Signature */
 
 		status = AE_BAD_SIGNATURE;
 		goto cleanup;
 	}
 
-	if (acpi_tb_checksum (table_ptr, RSDP_CHECKSUM_LENGTH) != 0) {
-		/* Nope, BAD Checksum */
+	/* Check the standard checksum */
 
+	if (acpi_tb_checksum (rsdp, ACPI_RSDP_CHECKSUM_LENGTH) != 0) {
 		status = AE_BAD_CHECKSUM;
 		goto cleanup;
 	}
 
-	/* TBD: Check extended checksum if table version >= 2 */
+	/* Check extended checksum if table version >= 2 */
+
+	if (rsdp->revision >= 2) {
+		if (acpi_tb_checksum (rsdp, ACPI_RSDP_XCHECKSUM_LENGTH) != 0) {
+			status = AE_BAD_CHECKSUM;
+			goto cleanup;
+		}
+	}
+
 
 	/* The RSDP supplied is OK */
 
-	table_info.pointer     = (acpi_table_header *) table_ptr;
+	table_info.pointer     = (acpi_table_header *) rsdp;
 	table_info.length      = sizeof (RSDP_DESCRIPTOR);
 	table_info.allocation  = ACPI_MEM_MAPPED;
-	table_info.base_pointer = table_ptr;
+	table_info.base_pointer = rsdp;
 
 	/* Save the table pointers and allocation info */
 
@@ -433,7 +422,6 @@
 		goto cleanup;
 	}
 
-
 	/* Save the RSDP in a global for easy access */
 
 	acpi_gbl_RSDP = (RSDP_DESCRIPTOR *) table_info.pointer;
@@ -443,7 +431,7 @@
 	/* Error exit */
 cleanup:
 
-	acpi_os_unmap_memory (table_ptr, sizeof (RSDP_DESCRIPTOR));
+	acpi_os_unmap_memory (rsdp, sizeof (RSDP_DESCRIPTOR));
 	return_ACPI_STATUS (status);
 }
 
@@ -467,7 +455,7 @@
 	ACPI_PHYSICAL_ADDRESS   physical_address;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/*
@@ -475,14 +463,8 @@
 	 * For RSDP revision 2 (and above), we use the XSDT
 	 */
 	if (acpi_gbl_RSDP->revision < 2) {
-#ifdef _IA64
-		/* 0.71 RSDP has 64bit Rsdt address field */
-		physical_address = ((RSDP_DESCRIPTOR_REV071 *)acpi_gbl_RSDP)->rsdt_physical_address;
-#else
 		physical_address = (ACPI_PHYSICAL_ADDRESS) acpi_gbl_RSDP->rsdt_physical_address;
-#endif
 	}
-
 	else {
 		physical_address = (ACPI_PHYSICAL_ADDRESS)
 				   ACPI_GET_ADDRESS (acpi_gbl_RSDP->xsdt_physical_address);
@@ -511,29 +493,28 @@
 	u32                     no_match;
 
 
-	PROC_NAME ("Tb_validate_rsdt");
+	ACPI_FUNCTION_NAME ("Tb_validate_rsdt");
 
 
 	/*
 	 * For RSDP revision 0 or 1, we use the RSDT.
-	 * For RSDP revision 2 (and above), we use the XSDT
+	 * For RSDP revision 2 and above, we use the XSDT
 	 */
 	if (acpi_gbl_RSDP->revision < 2) {
-		no_match = STRNCMP ((char *) table_ptr, RSDT_SIG,
+		no_match = ACPI_STRNCMP ((char *) table_ptr, RSDT_SIG,
 				  sizeof (RSDT_SIG) -1);
 	}
 	else {
-		no_match = STRNCMP ((char *) table_ptr, XSDT_SIG,
+		no_match = ACPI_STRNCMP ((char *) table_ptr, XSDT_SIG,
 				  sizeof (XSDT_SIG) -1);
 	}
 
-
 	if (no_match) {
 		/* Invalid RSDT or XSDT signature */
 
-		REPORT_ERROR (("Invalid signature where RSDP indicates RSDT/XSDT should be located\n"));
+		ACPI_REPORT_ERROR (("Invalid signature where RSDP indicates RSDT/XSDT should be located\n"));
 
-		DUMP_BUFFER (acpi_gbl_RSDP, 20);
+		ACPI_DUMP_BUFFER (acpi_gbl_RSDP, 20);
 
 		ACPI_DEBUG_PRINT_RAW ((ACPI_DB_ERROR,
 			"RSDT/XSDT signature at %X is invalid\n",
@@ -570,18 +551,16 @@
 	acpi_status             status;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if ((flags & ACPI_MEMORY_MODE) == ACPI_LOGICAL_ADDRESSING) {
 		*size = SIZE_IN_HEADER;
 		status = acpi_tb_map_acpi_table (physical_address, size, table_ptr);
 	}
-
 	else {
 		*size = 0;
-		*table_ptr = (acpi_table_header *) (ACPI_TBLPTR) physical_address;
-
+		*table_ptr = ACPI_PHYSADDR_TO_PTR (physical_address);
 		status = AE_OK;
 	}
 
@@ -610,7 +589,7 @@
 	ACPI_PHYSICAL_ADDRESS   physical_address;
 
 
-	FUNCTION_TRACE ("Tb_get_table_rsdt");
+	ACPI_FUNCTION_TRACE ("Tb_get_table_rsdt");
 
 
 	/*
@@ -618,13 +597,12 @@
 	 */
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 		"RSDP located at %p, RSDT physical=%8.8X%8.8X \n",
-		acpi_gbl_RSDP, HIDWORD(acpi_gbl_RSDP->rsdt_physical_address),
-		LODWORD(acpi_gbl_RSDP->rsdt_physical_address)));
-
+		acpi_gbl_RSDP,
+		ACPI_HIDWORD (acpi_gbl_RSDP->rsdt_physical_address),
+		ACPI_LODWORD (acpi_gbl_RSDP->rsdt_physical_address)));
 
 	physical_address = acpi_tb_get_rsdt_address ();
 
-
 	/* Get the RSDT/XSDT */
 
 	status = acpi_tb_get_table (physical_address, NULL, &table_info);
@@ -634,7 +612,6 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/* Check the RSDT or XSDT signature */
 
 	status = acpi_tb_validate_rsdt (table_info.pointer);
@@ -642,14 +619,12 @@
 		return_ACPI_STATUS (status);
 	}
 
-
 	/*
 	 * Valid RSDT signature, verify the checksum.  If it fails, just
 	 * print a warning and ignore it.
 	 */
 	status = acpi_tb_verify_table_checksum (table_info.pointer);
 
-
 	/* Convert and/or copy to an XSDT structure */
 
 	status = acpi_tb_convert_to_xsdt (&table_info, number_of_tables);
@@ -667,7 +642,6 @@
 	acpi_gbl_XSDT = (xsdt_descriptor *) table_info.pointer;
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "XSDT located at %p\n", acpi_gbl_XSDT));
-
 	return_ACPI_STATUS (status);
 }
 
@@ -700,7 +674,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Tb_get_table_facs");
+	ACPI_FUNCTION_TRACE ("Tb_get_table_facs");
 
 
 	/* Must have a valid FADT pointer */
@@ -720,13 +694,12 @@
 			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
-		MEMCPY (table_ptr, buffer_ptr, size);
+		ACPI_MEMCPY (table_ptr, buffer_ptr, size);
 
 		/* Save allocation type */
 
 		allocation = ACPI_MEM_ALLOCATED;
 	}
-
 	else {
 		/* Just map the physical memory to our address space */
 
@@ -740,7 +713,6 @@
 
 		allocation = ACPI_MEM_MAPPED;
 	}
-
 
 	/* Return values */
 
diff -Nru a/drivers/acpi/tables/tbinstal.c b/drivers/acpi/tables/tbinstal.c
--- a/drivers/acpi/tables/tbinstal.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/tables/tbinstal.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: tbinstal - ACPI table installation and removal
- *              $Revision: 45 $
+ *              $Revision: 55 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -25,12 +25,59 @@
 
 
 #include "acpi.h"
-#include "achware.h"
 #include "actables.h"
 
 
 #define _COMPONENT          ACPI_TABLES
-	 MODULE_NAME         ("tbinstal")
+	 ACPI_MODULE_NAME    ("tbinstal")
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_tb_match_signature
+ *
+ * PARAMETERS:  Signature           - Table signature to match
+ *              Table_info          - Return data
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Compare signature against the list of "ACPI-subsystem-owned"
+ *              tables (DSDT/FADT/SSDT, etc.) Returns the Table_type_iD on match.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_tb_match_signature (
+	NATIVE_CHAR             *signature,
+	acpi_table_desc         *table_info)
+{
+	NATIVE_UINT             i;
+
+
+	ACPI_FUNCTION_TRACE ("Tb_match_signature");
+
+
+	/*
+	 * Search for a signature match among the known table types
+	 */
+	for (i = 0; i < NUM_ACPI_TABLES; i++) {
+		if (!ACPI_STRNCMP (signature, acpi_gbl_acpi_table_data[i].signature,
+				   acpi_gbl_acpi_table_data[i].sig_length)) {
+			/* Found a signature match, return index if requested */
+
+			if (table_info) {
+				table_info->type = (u8) i;
+			}
+
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "ACPI Signature match %4.4s\n",
+				(char *) acpi_gbl_acpi_table_data[i].signature));
+
+			return_ACPI_STATUS (AE_OK);
+		}
+	}
+
+	return_ACPI_STATUS (AE_TABLE_NOT_SUPPORTED);
+}
 
 
 /*******************************************************************************
@@ -55,7 +102,7 @@
 {
 	acpi_status             status;
 
-	FUNCTION_TRACE ("Tb_install_table");
+	ACPI_FUNCTION_TRACE ("Tb_install_table");
 
 
 	/*
@@ -69,7 +116,10 @@
 
 	/* Lock tables while installing */
 
-	acpi_ut_acquire_mutex (ACPI_MTX_TABLES);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_TABLES);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Install the table into the global data structure */
 
@@ -78,7 +128,7 @@
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%s located at %p\n",
 		acpi_gbl_acpi_table_data[table_info->type].name, table_info->pointer));
 
-	acpi_ut_release_mutex (ACPI_MTX_TABLES);
+	(void) acpi_ut_release_mutex (ACPI_MTX_TABLES);
 	return_ACPI_STATUS (status);
 }
 
@@ -111,11 +161,9 @@
 {
 	acpi_table_header       *table_header;
 	acpi_status             status;
-	acpi_table_type         table_type = 0;
-	u32                     i;
 
 
-	FUNCTION_TRACE ("Tb_recognize_table");
+	ACPI_FUNCTION_TRACE ("Tb_recognize_table");
 
 
 	/* Ensure that we have a valid table pointer */
@@ -126,52 +174,32 @@
 	}
 
 	/*
-	 * Search for a signature match among the known table types
-	 * Start at index one -> Skip the RSDP
+	 * We only "recognize" a limited number of ACPI tables -- namely, the
+	 * ones that are used by the subsystem (DSDT, FADT, etc.)
+	 *
+	 * An AE_NOT_FOUND means that the table was not recognized.
+	 * This can be any one of many valid ACPI tables, it just isn't one of
+	 * the tables that is consumed by the core subsystem
 	 */
-	status = AE_SUPPORT;
-	for (i = 1; i < NUM_ACPI_TABLES; i++) {
-		if (!STRNCMP (table_header->signature,
-				  acpi_gbl_acpi_table_data[i].signature,
-				  acpi_gbl_acpi_table_data[i].sig_length)) {
-			/*
-			 * Found a signature match, get the pertinent info from the
-			 * Table_data structure
-			 */
-			table_type      = i;
-			status          = acpi_gbl_acpi_table_data[i].status;
+	status = acpi_tb_match_signature (table_header->signature, table_info);
+	if (ACPI_SUCCESS (status)) {
+		/* Return the table type and length via the info struct */
 
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Found %4.4s\n",
-				(char*)acpi_gbl_acpi_table_data[i].signature));
-			break;
-		}
-	}
+		table_info->length  = table_header->length;
 
-	/* Return the table type and length via the info struct */
-
-	table_info->type    = (u8) table_type;
-	table_info->length  = table_header->length;
-
-
-	/*
-	 * Validate checksum for _most_ tables,
-	 * even the ones whose signature we don't recognize
-	 */
-	if (table_type != ACPI_TABLE_FACS) {
-		/* But don't abort if the checksum is wrong */
-		/* TBD: [Future] make this a configuration option? */
-
-		acpi_tb_verify_table_checksum (table_header);
-	}
+		/*
+		 * Validate checksum for _most_ tables,
+		 * even the ones whose signature we don't recognize
+		 */
+		if (table_info->type != ACPI_TABLE_FACS) {
+			status = acpi_tb_verify_table_checksum (table_header);
+			if (ACPI_FAILURE (status) &&
+				(!ACPI_CHECKSUM_ABORT)) {
+				/* Ignore the error if configuration says so */
 
-	/*
-	 * An AE_SUPPORT means that the table was not recognized.
-	 * We basically ignore this;  just print a debug message
-	 */
-	if (status == AE_SUPPORT) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-			"Unsupported table %s (Type %X) was found and discarded\n",
-			acpi_gbl_acpi_table_data[table_type].name, table_type));
+				status = AE_OK;
+			}
+		}
 	}
 
 	return_ACPI_STATUS (status);
@@ -200,7 +228,7 @@
 	acpi_table_desc         *table_desc;
 
 
-	FUNCTION_TRACE_U32 ("Tb_init_table_descriptor", table_type);
+	ACPI_FUNCTION_TRACE_U32 ("Tb_init_table_descriptor", table_type);
 
 	/*
 	 * Install the table into the global data structure
@@ -208,25 +236,24 @@
 	list_head   = &acpi_gbl_acpi_tables[table_type];
 	table_desc  = list_head;
 
-
 	/*
 	 * Two major types of tables:  1) Only one instance is allowed.  This
 	 * includes most ACPI tables such as the DSDT.  2) Multiple instances of
 	 * the table are allowed.  This includes SSDT and PSDTs.
 	 */
-	if (IS_SINGLE_TABLE (acpi_gbl_acpi_table_data[table_type].flags)) {
+	if (ACPI_IS_SINGLE_TABLE (acpi_gbl_acpi_table_data[table_type].flags)) {
 		/*
 		 * Only one table allowed, and a table has alread been installed
 		 *  at this location, so return an error.
 		 */
 		if (list_head->pointer) {
-			return_ACPI_STATUS (AE_EXIST);
+			return_ACPI_STATUS (AE_ALREADY_EXISTS);
 		}
 
 		table_desc->count = 1;
+		table_desc->prev = NULL;
+		table_desc->next = NULL;
 	}
-
-
 	else {
 		/*
 		 * Multiple tables allowed for this table type, we must link
@@ -253,15 +280,14 @@
 
 			list_head->prev = table_desc;
 		}
-
 		else {
 			table_desc->count = 1;
 		}
 	}
 
-
 	/* Common initialization of the table descriptor */
 
+	table_desc->type                = table_info->type;
 	table_desc->pointer             = table_info->pointer;
 	table_desc->base_pointer        = table_info->base_pointer;
 	table_desc->length              = table_info->length;
@@ -269,7 +295,7 @@
 	table_desc->aml_start           = (u8 *) (table_desc->pointer + 1),
 	table_desc->aml_length          = (u32) (table_desc->length -
 			 (u32) sizeof (acpi_table_header));
-	table_desc->table_id            = acpi_ut_allocate_owner_id (OWNER_TYPE_TABLE);
+	table_desc->table_id            = acpi_ut_allocate_owner_id (ACPI_OWNER_TYPE_TABLE);
 	table_desc->loaded_into_namespace = FALSE;
 
 	/*
@@ -280,7 +306,6 @@
 		*(acpi_gbl_acpi_table_data[table_type].global_ptr) = table_info->pointer;
 	}
 
-
 	/* Return Data */
 
 	table_info->table_id        = table_desc->table_id;
@@ -315,7 +340,6 @@
 	for (type = 0; type < NUM_ACPI_TABLES; type++) {
 		acpi_tb_delete_acpi_table (type);
 	}
-
 }
 
 
@@ -336,21 +360,22 @@
 acpi_tb_delete_acpi_table (
 	acpi_table_type             type)
 {
-	FUNCTION_TRACE_U32 ("Tb_delete_acpi_table", type);
+
+	ACPI_FUNCTION_TRACE_U32 ("Tb_delete_acpi_table", type);
 
 
 	if (type > ACPI_TABLE_MAX) {
 		return_VOID;
 	}
 
-
-	acpi_ut_acquire_mutex (ACPI_MTX_TABLES);
+	if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_TABLES))) {
+		return;
+	}
 
 	/* Free the table */
 
 	acpi_tb_free_acpi_tables_of_type (&acpi_gbl_acpi_tables[type]);
 
-
 	/* Clear the appropriate "typed" global table pointer */
 
 	switch (type) {
@@ -380,8 +405,7 @@
 		break;
 	}
 
-	acpi_ut_release_mutex (ACPI_MTX_TABLES);
-
+	(void) acpi_ut_release_mutex (ACPI_MTX_TABLES);
 	return_VOID;
 }
 
@@ -408,7 +432,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE_PTR ("Tb_free_acpi_tables_of_type", list_head);
+	ACPI_FUNCTION_TRACE_PTR ("Tb_free_acpi_tables_of_type", list_head);
 
 
 	/* Get the head of the list */
@@ -454,17 +478,14 @@
 		/* Valid table, determine type of memory allocation */
 
 		switch (table_desc->allocation) {
-
 		case ACPI_MEM_NOT_ALLOCATED:
 			break;
 
-
 		case ACPI_MEM_ALLOCATED:
 
 			ACPI_MEM_FREE (table_desc->base_pointer);
 			break;
 
-
 		case ACPI_MEM_MAPPED:
 
 			acpi_os_unmap_memory (table_desc->base_pointer, table_desc->length);
@@ -495,14 +516,13 @@
 	acpi_table_desc         *next_desc;
 
 
-	FUNCTION_TRACE_PTR ("Tb_delete_single_table", table_desc);
+	ACPI_FUNCTION_TRACE_PTR ("Tb_delete_single_table", table_desc);
 
 
 	if (!table_desc) {
 		return_PTR (NULL);
 	}
 
-
 	/* Unlink the descriptor */
 
 	if (table_desc->prev) {
@@ -513,16 +533,13 @@
 		table_desc->next->prev = table_desc->prev;
 	}
 
-
 	/* Free the memory allocated for the table itself */
 
 	acpi_tb_delete_single_table (table_desc);
 
-
 	/* Free the table descriptor (Don't delete the list head, tho) */
 
 	if ((table_desc->prev) == (table_desc->next)) {
-
 		next_desc = NULL;
 
 		/* Clear the list head */
@@ -530,16 +547,13 @@
 		table_desc->pointer  = NULL;
 		table_desc->length   = 0;
 		table_desc->count    = 0;
-
 	}
-
 	else {
 		/* Free the table descriptor */
 
 		next_desc = table_desc->next;
 		ACPI_MEM_FREE (table_desc);
 	}
-
 
 	return_PTR (next_desc);
 }
diff -Nru a/drivers/acpi/tables/tbutils.c b/drivers/acpi/tables/tbutils.c
--- a/drivers/acpi/tables/tbutils.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/tables/tbutils.c	Fri Mar 15 17:51:02 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: tbutils - Table manipulation utilities
- *              $Revision: 42 $
+ *              $Revision: 49 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_TABLES
-	 MODULE_NAME         ("tbutils")
+	 ACPI_MODULE_NAME    ("tbutils")
 
 
 /*******************************************************************************
@@ -55,7 +55,7 @@
 	acpi_table_desc         *list_head;
 
 
-	PROC_NAME ("Tb_handle_to_object");
+	ACPI_FUNCTION_NAME ("Tb_handle_to_object");
 
 
 	for (i = 0; i < ACPI_TABLE_MAX; i++) {
@@ -79,81 +79,6 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_tb_system_table_pointer
- *
- * PARAMETERS:  *Where              - Pointer to be examined
- *
- * RETURN:      TRUE if Where is within the AML stream (in one of the ACPI
- *              system tables such as the DSDT or an SSDT.)
- *              FALSE otherwise
- *
- ******************************************************************************/
-
-u8
-acpi_tb_system_table_pointer (
-	void                    *where)
-{
-	u32                     i;
-	acpi_table_desc         *table_desc;
-	acpi_table_header       *table;
-
-
-	/* No function trace, called too often! */
-
-
-	/* Ignore null pointer */
-
-	if (!where) {
-		return (FALSE);
-	}
-
-
-	/* Check for a pointer within the DSDT */
-
-	if ((acpi_gbl_DSDT) &&
-		(IS_IN_ACPI_TABLE (where, acpi_gbl_DSDT))) {
-		return (TRUE);
-	}
-
-
-	/* Check each of the loaded SSDTs (if any)*/
-
-	table_desc = &acpi_gbl_acpi_tables[ACPI_TABLE_SSDT];
-
-	for (i = 0; i < acpi_gbl_acpi_tables[ACPI_TABLE_SSDT].count; i++) {
-		table = table_desc->pointer;
-
-		if (IS_IN_ACPI_TABLE (where, table)) {
-			return (TRUE);
-		}
-
-		table_desc = table_desc->next;
-	}
-
-
-	/* Check each of the loaded PSDTs (if any)*/
-
-	table_desc = &acpi_gbl_acpi_tables[ACPI_TABLE_PSDT];
-
-	for (i = 0; i < acpi_gbl_acpi_tables[ACPI_TABLE_PSDT].count; i++) {
-		table = table_desc->pointer;
-
-		if (IS_IN_ACPI_TABLE (where, table)) {
-			return (TRUE);
-		}
-
-		table_desc = table_desc->next;
-	}
-
-
-	/* Pointer does not point into any system table */
-
-	return (FALSE);
-}
-
-
-/*******************************************************************************
- *
  * FUNCTION:    Acpi_tb_validate_table_header
  *
  * PARAMETERS:  Table_header        - Logical pointer to the table
@@ -179,7 +104,7 @@
 	acpi_name               signature;
 
 
-	PROC_NAME ("Tb_validate_table_header");
+	ACPI_FUNCTION_NAME ("Tb_validate_table_header");
 
 
 	/* Verify that this is a valid address */
@@ -193,14 +118,14 @@
 
 	/* Ensure that the signature is 4 ASCII characters */
 
-	MOVE_UNALIGNED32_TO_32 (&signature, &table_header->signature);
+	ACPI_MOVE_UNALIGNED32_TO_32 (&signature, &table_header->signature);
 	if (!acpi_ut_valid_acpi_name (signature)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 			"Table signature at %p [%p] has invalid characters\n",
 			table_header, &signature));
 
-		REPORT_WARNING (("Invalid table signature %4.4s found\n", (char*)&signature));
-		DUMP_BUFFER (table_header, sizeof (acpi_table_header));
+		ACPI_REPORT_WARNING (("Invalid table signature %4.4s found\n", (char *) &signature));
+		ACPI_DUMP_BUFFER (table_header, sizeof (acpi_table_header));
 		return (AE_BAD_SIGNATURE);
 	}
 
@@ -210,10 +135,10 @@
 	if (table_header->length < sizeof (acpi_table_header)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 			"Invalid length in table header %p name %4.4s\n",
-			table_header, (char*)&signature));
+			table_header, (char *) &signature));
 
-		REPORT_WARNING (("Invalid table header length found\n"));
-		DUMP_BUFFER (table_header, sizeof (acpi_table_header));
+		ACPI_REPORT_WARNING (("Invalid table header length (0x%X) found\n", table_header->length));
+		ACPI_DUMP_BUFFER (table_header, sizeof (acpi_table_header));
 		return (AE_BAD_HEADER);
 	}
 
@@ -248,7 +173,7 @@
 	acpi_status             status = AE_OK;
 
 
-	PROC_NAME ("Tb_map_acpi_table");
+	ACPI_FUNCTION_NAME ("Tb_map_acpi_table");
 
 
 	/* If size is zero, look at the table header to get the actual size */
@@ -323,7 +248,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Tb_verify_table_checksum");
+	ACPI_FUNCTION_TRACE ("Tb_verify_table_checksum");
 
 
 	/* Compute the checksum on the table */
@@ -333,8 +258,8 @@
 	/* Return the appropriate exception */
 
 	if (checksum) {
-		REPORT_WARNING (("Invalid checksum (%X) in table %4.4s\n",
-			checksum, (char*)&table_header->signature));
+		ACPI_REPORT_WARNING (("Invalid checksum (%X) in table %4.4s\n",
+			checksum, (char *) &table_header->signature));
 
 		status = AE_BAD_CHECKSUM;
 	}
@@ -362,8 +287,8 @@
 	void                    *buffer,
 	u32                     length)
 {
-	u8                      *limit;
-	u8                      *rover;
+	const u8                *limit;
+	const u8                *rover;
 	u8                      sum = 0;
 
 
diff -Nru a/drivers/acpi/tables/tbxface.c b/drivers/acpi/tables/tbxface.c
--- a/drivers/acpi/tables/tbxface.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/tables/tbxface.c	Fri Mar 15 17:51:03 2002
@@ -2,12 +2,12 @@
  *
  * Module Name: tbxface - Public interfaces to the ACPI subsystem
  *                         ACPI table oriented interfaces
- *              $Revision: 45 $
+ *              $Revision: 51 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 
 
 #define _COMPONENT          ACPI_TABLES
-	 MODULE_NAME         ("tbxface")
+	 ACPI_MODULE_NAME    ("tbxface")
 
 
 /*******************************************************************************
@@ -56,7 +56,7 @@
 	u32                     number_of_tables = 0;
 
 
-	FUNCTION_TRACE ("Acpi_load_tables");
+	ACPI_FUNCTION_TRACE ("Acpi_load_tables");
 
 
 	/* Get the RSDP */
@@ -64,7 +64,7 @@
 	status = acpi_os_get_root_pointer (ACPI_LOGICAL_ADDRESSING,
 			  &rsdp_physical_address);
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Acpi_load_tables: Could not get RSDP, %s\n",
+		ACPI_REPORT_ERROR (("Acpi_load_tables: Could not get RSDP, %s\n",
 				  acpi_format_exception (status)));
 		goto error_exit;
 	}
@@ -73,7 +73,7 @@
 
 	status = acpi_tb_verify_rsdp (rsdp_physical_address);
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Acpi_load_tables: RSDP Failed validation: %s\n",
+		ACPI_REPORT_ERROR (("Acpi_load_tables: RSDP Failed validation: %s\n",
 				  acpi_format_exception (status)));
 		goto error_exit;
 	}
@@ -82,7 +82,7 @@
 
 	status = acpi_tb_get_table_rsdt (&number_of_tables);
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Acpi_load_tables: Could not load RSDT: %s\n",
+		ACPI_REPORT_ERROR (("Acpi_load_tables: Could not load RSDT: %s\n",
 				  acpi_format_exception (status)));
 		goto error_exit;
 	}
@@ -91,7 +91,7 @@
 
 	status = acpi_tb_get_all_tables (number_of_tables, NULL);
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Acpi_load_tables: Error getting required tables (DSDT/FADT/FACS): %s\n",
+		ACPI_REPORT_ERROR (("Acpi_load_tables: Error getting required tables (DSDT/FADT/FACS): %s\n",
 				  acpi_format_exception (status)));
 		goto error_exit;
 	}
@@ -103,7 +103,7 @@
 
 	status = acpi_ns_load_namespace ();
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Acpi_load_tables: Could not load namespace: %s\n",
+		ACPI_REPORT_ERROR (("Acpi_load_tables: Could not load namespace: %s\n",
 				  acpi_format_exception (status)));
 		goto error_exit;
 	}
@@ -112,7 +112,7 @@
 
 
 error_exit:
-	REPORT_ERROR (("Acpi_load_tables: Could not load tables: %s\n",
+	ACPI_REPORT_ERROR (("Acpi_load_tables: Could not load tables: %s\n",
 			  acpi_format_exception (status)));
 
 	return_ACPI_STATUS (status);
@@ -143,7 +143,7 @@
 	acpi_table_desc         table_info;
 
 
-	FUNCTION_TRACE ("Acpi_load_table");
+	ACPI_FUNCTION_TRACE ("Acpi_load_table");
 
 
 	if (!table_ptr) {
@@ -167,16 +167,32 @@
 		return_ACPI_STATUS (status);
 	}
 
+	/* Convert the table to common format if necessary */
+
+	switch (table_info.type) {
+	case ACPI_TABLE_FADT:
+
+		status = acpi_tb_convert_table_fadt ();
+		break;
+
+	case ACPI_TABLE_FACS:
+
+		status = acpi_tb_build_common_facs (&table_info);
+		break;
+
+	default:
+		/* Load table into namespace if it contains executable AML */
+
+		status = acpi_ns_load_table (table_info.installed_desc, acpi_gbl_root_node);
+		break;
+	}
 
-	status = acpi_ns_load_table (table_info.installed_desc, acpi_gbl_root_node);
 	if (ACPI_FAILURE (status)) {
 		/* Uninstall table and free the buffer */
 
 		acpi_tb_uninstall_table (table_info.installed_desc);
-		return_ACPI_STATUS (status);
 	}
 
-
 	return_ACPI_STATUS (status);
 }
 
@@ -200,7 +216,7 @@
 	acpi_table_desc         *list_head;
 
 
-	FUNCTION_TRACE ("Acpi_unload_table");
+	ACPI_FUNCTION_TRACE ("Acpi_unload_table");
 
 
 	/* Parameter validation */
@@ -263,7 +279,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_get_table_header");
+	ACPI_FUNCTION_TRACE ("Acpi_get_table_header");
 
 
 	if ((instance == 0)                 ||
@@ -275,7 +291,7 @@
 	/* Check the table type and instance */
 
 	if ((table_type > ACPI_TABLE_MAX)   ||
-		(IS_SINGLE_TABLE (acpi_gbl_acpi_table_data[table_type].flags) &&
+		(ACPI_IS_SINGLE_TABLE (acpi_gbl_acpi_table_data[table_type].flags) &&
 		 instance > 1)) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
@@ -298,7 +314,7 @@
 	/*
 	 * Copy the header to the caller's buffer
 	 */
-	MEMCPY ((void *) out_table_header, (void *) tbl_ptr,
+	ACPI_MEMCPY ((void *) out_table_header, (void *) tbl_ptr,
 			 sizeof (acpi_table_header));
 
 	return_ACPI_STATUS (status);
@@ -336,25 +352,27 @@
 {
 	acpi_table_header       *tbl_ptr;
 	acpi_status             status;
-	u32                     ret_buf_len;
+	u32                     table_length;
 
 
-	FUNCTION_TRACE ("Acpi_get_table");
+	ACPI_FUNCTION_TRACE ("Acpi_get_table");
 
 
-	/*
-	 *  If we have a buffer, we must have a length too
-	 */
-	if ((instance == 0)                 ||
-		(!ret_buffer)                   ||
-		((!ret_buffer->pointer) && (ret_buffer->length))) {
+	/* Parameter validation */
+
+	if (instance == 0) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
 
+	status = acpi_ut_validate_buffer (ret_buffer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
+
 	/* Check the table type and instance */
 
 	if ((table_type > ACPI_TABLE_MAX)   ||
-		(IS_SINGLE_TABLE (acpi_gbl_acpi_table_data[table_type].flags) &&
+		(ACPI_IS_SINGLE_TABLE (acpi_gbl_acpi_table_data[table_type].flags) &&
 		 instance > 1)) {
 		return_ACPI_STATUS (AE_BAD_PARAMETER);
 	}
@@ -375,31 +393,28 @@
 		return_ACPI_STATUS (AE_NOT_EXIST);
 	}
 
-	/*
-	 * Got a table ptr, assume it's ok and copy it to the user's buffer
-	 */
+	/* Get the table length */
+
 	if (table_type == ACPI_TABLE_RSDP) {
 		/*
 		 *  RSD PTR is the only "table" without a header
 		 */
-		ret_buf_len = sizeof (RSDP_DESCRIPTOR);
+		table_length = sizeof (RSDP_DESCRIPTOR);
 	}
 	else {
-		ret_buf_len = tbl_ptr->length;
+		table_length = tbl_ptr->length;
 	}
 
-	/*
-	 * Verify we have space in the caller's buffer for the table
-	 */
-	if (ret_buffer->length < ret_buf_len) {
-		ret_buffer->length = ret_buf_len;
-		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
-	}
+	/* Validate/Allocate/Clear caller buffer */
 
-	ret_buffer->length = ret_buf_len;
+	status = acpi_ut_initialize_buffer (ret_buffer, table_length);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
-	MEMCPY ((void *) ret_buffer->pointer, (void *) tbl_ptr, ret_buf_len);
+	/* Copy the table to the buffer */
 
+	ACPI_MEMCPY ((void *) ret_buffer->pointer, (void *) tbl_ptr, table_length);
 	return_ACPI_STATUS (AE_OK);
 }
 
diff -Nru a/drivers/acpi/tables/tbxfroot.c b/drivers/acpi/tables/tbxfroot.c
--- a/drivers/acpi/tables/tbxfroot.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/tables/tbxfroot.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: tbxfroot - Find the root ACPI table (RSDT)
- *              $Revision: 52 $
+ *              $Revision: 58 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -25,225 +25,67 @@
 
 
 #include "acpi.h"
-#include "achware.h"
 #include "actables.h"
 
 
 #define _COMPONENT          ACPI_TABLES
-	 MODULE_NAME         ("tbxfroot")
-
-#define RSDP_CHECKSUM_LENGTH 20
+	 ACPI_MODULE_NAME    ("tbxfroot")
 
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_find_root_pointer
+ * FUNCTION:    Acpi_tb_find_table
  *
- * PARAMETERS:  **Rsdp_physical_address     - Where to place the RSDP address
- *              Flags                       - Logical/Physical addressing
+ * PARAMETERS:  Signature           - String with ACPI table signature
+ *              Oem_id              - String with the table OEM ID
+ *              Oem_table_id        - String with the OEM Table ID.
  *
- * RETURN:      Status, Physical address of the RSDP
+ * RETURN:      Status
  *
- * DESCRIPTION: Find the RSDP
+ * DESCRIPTION: Find an ACPI table (in the RSDT/XSDT) that matches the
+ *              Signature, OEM ID and OEM Table ID.
  *
  ******************************************************************************/
 
 acpi_status
-acpi_find_root_pointer (
-	u32                     flags,
-	ACPI_PHYSICAL_ADDRESS   *rsdp_physical_address)
+acpi_tb_find_table (
+	NATIVE_CHAR             *signature,
+	NATIVE_CHAR             *oem_id,
+	NATIVE_CHAR             *oem_table_id,
+	acpi_table_header       **table_ptr)
 {
-	acpi_table_desc         table_info;
 	acpi_status             status;
+	acpi_table_header       *table;
 
 
-	FUNCTION_TRACE ("Acpi_find_root_pointer");
+	ACPI_FUNCTION_TRACE ("Tb_find_table");
 
 
-	/* Get the RSDP */
+	/* Validate string lengths */
 
-	status = acpi_tb_find_rsdp (&table_info, flags);
-	if (ACPI_FAILURE (status)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "RSDP structure not found\n"));
-		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
+	if ((ACPI_STRLEN (signature)  > 4) ||
+		(ACPI_STRLEN (oem_id)     > 6) ||
+		(ACPI_STRLEN (oem_table_id) > 8)) {
+		return_ACPI_STATUS (AE_AML_STRING_LIMIT);
 	}
 
-	*rsdp_physical_address = table_info.physical_address;
-
-	return_ACPI_STATUS (AE_OK);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_tb_scan_memory_for_rsdp
- *
- * PARAMETERS:  Start_address       - Starting pointer for search
- *              Length              - Maximum length to search
- *
- * RETURN:      Pointer to the RSDP if found, otherwise NULL.
- *
- * DESCRIPTION: Search a block of memory for the RSDP signature
- *
- ******************************************************************************/
-
-u8 *
-acpi_tb_scan_memory_for_rsdp (
-	u8                      *start_address,
-	u32                     length)
-{
-	u32                     offset;
-	u8                      *mem_rover;
-
-
-	FUNCTION_TRACE ("Tb_scan_memory_for_rsdp");
-
-
-	/* Search from given start addr for the requested length  */
-
-	for (offset = 0, mem_rover = start_address;
-		 offset < length;
-		 offset += RSDP_SCAN_STEP, mem_rover += RSDP_SCAN_STEP) {
-
-		/* The signature and checksum must both be correct */
-
-		if (STRNCMP ((NATIVE_CHAR *) mem_rover,
-				RSDP_SIG, sizeof (RSDP_SIG)-1) == 0 &&
-			acpi_tb_checksum (mem_rover, RSDP_CHECKSUM_LENGTH) == 0) {
-			/* If so, we have found the RSDP */
-
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-				"RSDP located at physical address %p\n",mem_rover));
-			return_PTR (mem_rover);
-		}
-	}
-
-	/* Searched entire block, no RSDP was found */
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,"Searched entire block, no RSDP was found.\n"));
-
-	return_PTR (NULL);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_tb_find_rsdp
- *
- * PARAMETERS:  *Table_info             - Where the table info is returned
- *              Flags                   - Current memory mode (logical vs.
- *                                        physical addressing)
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Search lower 1_mbyte of memory for the root system descriptor
- *              pointer structure.  If it is found, set *RSDP to point to it.
- *
- *              NOTE: The RSDP must be either in the first 1_k of the Extended
- *              BIOS Data Area or between E0000 and FFFFF (ACPI 1.0 section
- *              5.2.2; assertion #421).
- *
- ******************************************************************************/
-
-acpi_status
-acpi_tb_find_rsdp (
-	acpi_table_desc         *table_info,
-	u32                     flags)
-{
-	u8                      *table_ptr;
-	u8                      *mem_rover;
-	u64                     phys_addr;
-	acpi_status             status = AE_OK;
-
-
-	FUNCTION_TRACE ("Tb_find_rsdp");
-
-
-	/*
-	 * Scan supports either 1) Logical addressing or 2) Physical addressing
-	 */
-	if ((flags & ACPI_MEMORY_MODE) == ACPI_LOGICAL_ADDRESSING) {
-		/*
-		 * 1) Search EBDA (low memory) paragraphs
-		 */
-		status = acpi_os_map_memory (LO_RSDP_WINDOW_BASE, LO_RSDP_WINDOW_SIZE,
-				  (void **) &table_ptr);
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
-		}
-
-		mem_rover = acpi_tb_scan_memory_for_rsdp (table_ptr, LO_RSDP_WINDOW_SIZE);
-		acpi_os_unmap_memory (table_ptr, LO_RSDP_WINDOW_SIZE);
-
-		if (mem_rover) {
-			/* Found it, return the physical address */
-
-			phys_addr = LO_RSDP_WINDOW_BASE;
-			phys_addr += (mem_rover - table_ptr);
-
-			table_info->physical_address = phys_addr;
-
-			return_ACPI_STATUS (AE_OK);
-		}
-
-		/*
-		 * 2) Search upper memory: 16-byte boundaries in E0000h-F0000h
-		 */
-		status = acpi_os_map_memory (HI_RSDP_WINDOW_BASE, HI_RSDP_WINDOW_SIZE,
-				  (void **) &table_ptr);
-		if (ACPI_FAILURE (status)) {
-			return_ACPI_STATUS (status);
-		}
-
-		mem_rover = acpi_tb_scan_memory_for_rsdp (table_ptr, HI_RSDP_WINDOW_SIZE);
-		acpi_os_unmap_memory (table_ptr, HI_RSDP_WINDOW_SIZE);
-
-		if (mem_rover) {
-			/* Found it, return the physical address */
+	/* Find the table */
 
-			phys_addr = HI_RSDP_WINDOW_BASE;
-			phys_addr += (mem_rover - table_ptr);
-
-			table_info->physical_address = phys_addr;
-
-			return_ACPI_STATUS (AE_OK);
-		}
+	status = acpi_get_firmware_table (signature, 1,
+			   ACPI_LOGICAL_ADDRESSING, &table);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
+	/* Check Oem_id and Oem_table_id */
 
-	/*
-	 * Physical addressing
-	 */
-	else {
-		/*
-		 * 1) Search EBDA (low memory) paragraphs
-		 */
-		mem_rover = acpi_tb_scan_memory_for_rsdp ((u8 *) LO_RSDP_WINDOW_BASE,
-				  LO_RSDP_WINDOW_SIZE);
-		if (mem_rover) {
-			/* Found it, return the physical address */
-
-			table_info->physical_address = (ACPI_TBLPTR) mem_rover;
-			return_ACPI_STATUS (AE_OK);
-		}
-
-		/*
-		 * 2) Search upper memory: 16-byte boundaries in E0000h-F0000h
-		 */
-		mem_rover = acpi_tb_scan_memory_for_rsdp ((u8 *) HI_RSDP_WINDOW_BASE,
-				  HI_RSDP_WINDOW_SIZE);
-		if (mem_rover) {
-			/* Found it, return the physical address */
-
-			table_info->physical_address = (ACPI_TBLPTR) mem_rover;
-			return_ACPI_STATUS (AE_OK);
-		}
+	if ((oem_id[0]     && ACPI_STRCMP (oem_id, table->oem_id)) ||
+		(oem_table_id[0] && ACPI_STRCMP (oem_table_id, table->oem_table_id))) {
+		return_ACPI_STATUS (AE_AML_NAME_NOT_FOUND);
 	}
 
-
-	/* RSDP signature was not found */
-
-	return_ACPI_STATUS (AE_NOT_FOUND);
+	*table_ptr = table;
+	return_ACPI_STATUS (AE_OK);
 }
 
 
@@ -287,7 +129,7 @@
 	u32                     j;
 
 
-	FUNCTION_TRACE ("Acpi_get_firmware_table");
+	ACPI_FUNCTION_TRACE ("Acpi_get_firmware_table");
 
 
 	/*
@@ -323,20 +165,20 @@
 			}
 		}
 		else {
-			acpi_gbl_RSDP = (void *) (NATIVE_UINT) physical_address;
+			acpi_gbl_RSDP = ACPI_PHYSADDR_TO_PTR (physical_address);
 		}
 
 		/*
 		 *  The signature and checksum must both be correct
 		 */
-		if (STRNCMP ((NATIVE_CHAR *) acpi_gbl_RSDP, RSDP_SIG, sizeof (RSDP_SIG)-1) != 0) {
+		if (ACPI_STRNCMP ((NATIVE_CHAR *) acpi_gbl_RSDP, RSDP_SIG, sizeof (RSDP_SIG)-1) != 0) {
 			/* Nope, BAD Signature */
 
 			status = AE_BAD_SIGNATURE;
 			goto cleanup;
 		}
 
-		if (acpi_tb_checksum (acpi_gbl_RSDP, RSDP_CHECKSUM_LENGTH) != 0) {
+		if (acpi_tb_checksum (acpi_gbl_RSDP, ACPI_RSDP_CHECKSUM_LENGTH) != 0) {
 			/* Nope, BAD Checksum */
 
 			status = AE_BAD_CHECKSUM;
@@ -344,12 +186,11 @@
 		}
 	}
 
-
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 		"RSDP located at %p, RSDT physical=%8.8X%8.8X \n",
-		acpi_gbl_RSDP, HIDWORD(acpi_gbl_RSDP->rsdt_physical_address),
-		LODWORD(acpi_gbl_RSDP->rsdt_physical_address)));
-
+		acpi_gbl_RSDP,
+		ACPI_HIDWORD (acpi_gbl_RSDP->rsdt_physical_address),
+		ACPI_LODWORD (acpi_gbl_RSDP->rsdt_physical_address)));
 
 	/* Get the RSDT and validate it */
 
@@ -364,7 +205,6 @@
 		goto cleanup;
 	}
 
-
 	/* Get the number of table pointers within the RSDT */
 
 	table_count = acpi_tb_get_table_count (acpi_gbl_RSDP, rsdt_ptr);
@@ -378,7 +218,8 @@
 		/* Get the next table pointer */
 
 		if (acpi_gbl_RSDP->revision < 2) {
-			physical_address = ((RSDT_DESCRIPTOR *) rsdt_ptr)->table_offset_entry[i];
+			physical_address = (ACPI_PHYSICAL_ADDRESS)
+				((RSDT_DESCRIPTOR *) rsdt_ptr)->table_offset_entry[i];
 		}
 		else {
 			physical_address = (ACPI_PHYSICAL_ADDRESS)
@@ -394,7 +235,7 @@
 
 		/* Compare table signatures and table instance */
 
-		if (!STRNCMP ((char *) table_ptr, signature, STRLEN (signature))) {
+		if (!ACPI_STRNCMP ((char *) table_ptr, signature, ACPI_STRLEN (signature))) {
 			/* An instance of the table was found */
 
 			j++;
@@ -426,4 +267,215 @@
 	return_ACPI_STATUS (status);
 }
 
+
+/* TBD: Move to a new file */
+
+#ifndef _IA16
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_find_root_pointer
+ *
+ * PARAMETERS:  **Rsdp_physical_address     - Where to place the RSDP address
+ *              Flags                       - Logical/Physical addressing
+ *
+ * RETURN:      Status, Physical address of the RSDP
+ *
+ * DESCRIPTION: Find the RSDP
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_find_root_pointer (
+	u32                     flags,
+	ACPI_PHYSICAL_ADDRESS   *rsdp_physical_address)
+{
+	acpi_table_desc         table_info;
+	acpi_status             status;
+
+
+	ACPI_FUNCTION_TRACE ("Acpi_find_root_pointer");
+
+
+	/* Get the RSDP */
+
+	status = acpi_tb_find_rsdp (&table_info, flags);
+	if (ACPI_FAILURE (status)) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "RSDP structure not found\n"));
+		return_ACPI_STATUS (AE_NO_ACPI_TABLES);
+	}
+
+	*rsdp_physical_address = table_info.physical_address;
+	return_ACPI_STATUS (AE_OK);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_tb_scan_memory_for_rsdp
+ *
+ * PARAMETERS:  Start_address       - Starting pointer for search
+ *              Length              - Maximum length to search
+ *
+ * RETURN:      Pointer to the RSDP if found, otherwise NULL.
+ *
+ * DESCRIPTION: Search a block of memory for the RSDP signature
+ *
+ ******************************************************************************/
+
+u8 *
+acpi_tb_scan_memory_for_rsdp (
+	u8                      *start_address,
+	u32                     length)
+{
+	u32                     offset;
+	u8                      *mem_rover;
+
+
+	ACPI_FUNCTION_TRACE ("Tb_scan_memory_for_rsdp");
+
+
+	/* Search from given start addr for the requested length  */
+
+	for (offset = 0, mem_rover = start_address;
+		 offset < length;
+		 offset += RSDP_SCAN_STEP, mem_rover += RSDP_SCAN_STEP) {
+
+		/* The signature and checksum must both be correct */
+
+		if (ACPI_STRNCMP ((NATIVE_CHAR *) mem_rover,
+				RSDP_SIG, sizeof (RSDP_SIG)-1) == 0 &&
+			acpi_tb_checksum (mem_rover, ACPI_RSDP_CHECKSUM_LENGTH) == 0) {
+			/* If so, we have found the RSDP */
+
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+				"RSDP located at physical address %p\n",mem_rover));
+			return_PTR (mem_rover);
+		}
+	}
+
+	/* Searched entire block, no RSDP was found */
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO,"Searched entire block, no RSDP was found.\n"));
+	return_PTR (NULL);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_tb_find_rsdp
+ *
+ * PARAMETERS:  *Table_info             - Where the table info is returned
+ *              Flags                   - Current memory mode (logical vs.
+ *                                        physical addressing)
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Search lower 1_mbyte of memory for the root system descriptor
+ *              pointer structure.  If it is found, set *RSDP to point to it.
+ *
+ *              NOTE: The RSDP must be either in the first 1_k of the Extended
+ *              BIOS Data Area or between E0000 and FFFFF (ACPI 1.0 section
+ *              5.2.2; assertion #421).
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_tb_find_rsdp (
+	acpi_table_desc         *table_info,
+	u32                     flags)
+{
+	u8                      *table_ptr;
+	u8                      *mem_rover;
+	u64                     phys_addr;
+	acpi_status             status = AE_OK;
+
+
+	ACPI_FUNCTION_TRACE ("Tb_find_rsdp");
+
+
+	/*
+	 * Scan supports either 1) Logical addressing or 2) Physical addressing
+	 */
+	if ((flags & ACPI_MEMORY_MODE) == ACPI_LOGICAL_ADDRESSING) {
+		/*
+		 * 1) Search EBDA (low memory) paragraphs
+		 */
+		status = acpi_os_map_memory ((u64) LO_RSDP_WINDOW_BASE, LO_RSDP_WINDOW_SIZE,
+				  (void **) &table_ptr);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
+
+		mem_rover = acpi_tb_scan_memory_for_rsdp (table_ptr, LO_RSDP_WINDOW_SIZE);
+		acpi_os_unmap_memory (table_ptr, LO_RSDP_WINDOW_SIZE);
+
+		if (mem_rover) {
+			/* Found it, return the physical address */
+
+			phys_addr = LO_RSDP_WINDOW_BASE;
+			phys_addr += (mem_rover - table_ptr);
+
+			table_info->physical_address = phys_addr;
+			return_ACPI_STATUS (AE_OK);
+		}
+
+		/*
+		 * 2) Search upper memory: 16-byte boundaries in E0000h-F0000h
+		 */
+		status = acpi_os_map_memory ((u64) HI_RSDP_WINDOW_BASE, HI_RSDP_WINDOW_SIZE,
+				  (void **) &table_ptr);
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
+
+		mem_rover = acpi_tb_scan_memory_for_rsdp (table_ptr, HI_RSDP_WINDOW_SIZE);
+		acpi_os_unmap_memory (table_ptr, HI_RSDP_WINDOW_SIZE);
+
+		if (mem_rover) {
+			/* Found it, return the physical address */
+
+			phys_addr = HI_RSDP_WINDOW_BASE;
+			phys_addr += (mem_rover - table_ptr);
+
+			table_info->physical_address = phys_addr;
+			return_ACPI_STATUS (AE_OK);
+		}
+	}
+
+	/*
+	 * Physical addressing
+	 */
+	else {
+		/*
+		 * 1) Search EBDA (low memory) paragraphs
+		 */
+		mem_rover = acpi_tb_scan_memory_for_rsdp (ACPI_PHYSADDR_TO_PTR (LO_RSDP_WINDOW_BASE),
+				  LO_RSDP_WINDOW_SIZE);
+		if (mem_rover) {
+			/* Found it, return the physical address */
+
+			table_info->physical_address = ACPI_TO_INTEGER (mem_rover);
+			return_ACPI_STATUS (AE_OK);
+		}
+
+		/*
+		 * 2) Search upper memory: 16-byte boundaries in E0000h-F0000h
+		 */
+		mem_rover = acpi_tb_scan_memory_for_rsdp (ACPI_PHYSADDR_TO_PTR (HI_RSDP_WINDOW_BASE),
+				  HI_RSDP_WINDOW_SIZE);
+		if (mem_rover) {
+			/* Found it, return the physical address */
+
+			table_info->physical_address = ACPI_TO_INTEGER (mem_rover);
+			return_ACPI_STATUS (AE_OK);
+		}
+	}
+
+	/* RSDP signature was not found */
+
+	return_ACPI_STATUS (AE_NOT_FOUND);
+}
+
+#endif
 
diff -Nru a/drivers/acpi/utilities/Makefile b/drivers/acpi/utilities/Makefile
--- a/drivers/acpi/utilities/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/acpi/utilities/Makefile	Fri Mar 15 17:51:02 2002
@@ -1,11 +1,10 @@
 #
 # Makefile for all Linux ACPI interpreter subdirectories
-# EXCEPT for the ospm directory
 #
 
 O_TARGET := $(notdir $(CURDIR)).o
 
-obj-$(CONFIG_ACPI) := $(patsubst %.c,%.o,$(wildcard *.c))
+obj-$(CONFIG_ACPI_INTERPRETER) := $(patsubst %.c,%.o,$(wildcard *.c))
 
 EXTRA_CFLAGS += $(ACPI_CFLAGS)
 
diff -Nru a/drivers/acpi/utilities/utalloc.c b/drivers/acpi/utilities/utalloc.c
--- a/drivers/acpi/utilities/utalloc.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/utilities/utalloc.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utalloc - local cache and memory allocation routines
- *              $Revision: 106 $
+ *              $Revision: 121 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 #include "acglobal.h"
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utalloc")
+	 ACPI_MODULE_NAME    ("utalloc")
 
 
 /******************************************************************************
@@ -56,7 +56,7 @@
 	ACPI_MEMORY_LIST        *cache_info;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* If walk cache is full, just free this wallkstate object */
@@ -70,12 +70,14 @@
 	/* Otherwise put this object back into the cache */
 
 	else {
-		acpi_ut_acquire_mutex (ACPI_MTX_CACHES);
+		if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_CACHES))) {
+			return;
+		}
 
 		/* Mark the object as cached */
 
-		MEMSET (object, 0xCA, cache_info->object_size);
-		((acpi_operand_object *) object)->common.data_type = ACPI_CACHED_OBJECT;
+		ACPI_MEMSET (object, 0xCA, cache_info->object_size);
+		ACPI_SET_DESCRIPTOR_TYPE (object, ACPI_CACHED_OBJECT);
 
 		/* Put the object at the head of the cache list */
 
@@ -83,7 +85,7 @@
 		cache_info->list_head = object;
 		cache_info->cache_depth++;
 
-		acpi_ut_release_mutex (ACPI_MTX_CACHES);
+		(void) acpi_ut_release_mutex (ACPI_MTX_CACHES);
 	}
 }
 
@@ -110,11 +112,14 @@
 	void                    *object;
 
 
-	PROC_NAME ("Ut_acquire_from_cache");
+	ACPI_FUNCTION_NAME ("Ut_acquire_from_cache");
 
 
 	cache_info = &acpi_gbl_memory_lists[list_id];
-	acpi_ut_acquire_mutex (ACPI_MTX_CACHES);
+	if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_CACHES))) {
+		return (NULL);
+	}
+
 	ACPI_MEM_TRACKING (cache_info->cache_requests++);
 
 	/* Check the cache first */
@@ -133,11 +138,13 @@
 			object, acpi_gbl_memory_lists[list_id].list_name));
 #endif
 
-		acpi_ut_release_mutex (ACPI_MTX_CACHES);
+		if (ACPI_FAILURE (acpi_ut_release_mutex (ACPI_MTX_CACHES))) {
+			return (NULL);
+		}
 
 		/* Clear (zero) the previously used Object */
 
-		MEMSET (object, 0, cache_info->object_size);
+		ACPI_MEMSET (object, 0, cache_info->object_size);
 	}
 
 	else {
@@ -145,7 +152,9 @@
 
 		/* Avoid deadlock with ACPI_MEM_CALLOCATE */
 
-		acpi_ut_release_mutex (ACPI_MTX_CACHES);
+		if (ACPI_FAILURE (acpi_ut_release_mutex (ACPI_MTX_CACHES))) {
+			return (NULL);
+		}
 
 		object = ACPI_MEM_CALLOCATE (cache_info->object_size);
 		ACPI_MEM_TRACKING (cache_info->total_allocated++);
@@ -175,7 +184,7 @@
 	char                    *next;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	cache_info = &acpi_gbl_memory_lists[list_id];
@@ -191,9 +200,230 @@
 }
 
 
-#ifdef ACPI_DBG_TRACK_ALLOCATIONS
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_validate_buffer
+ *
+ * PARAMETERS:  Buffer              - Buffer descriptor to be validated
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Perform parameter validation checks on an acpi_buffer
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_validate_buffer (
+	acpi_buffer             *buffer)
+{
+
+	/* Obviously, the structure pointer must be valid */
+
+	if (!buffer) {
+		return (AE_BAD_PARAMETER);
+	}
+
+	/* Special semantics for the length */
+
+	if ((buffer->length == ACPI_NO_BUFFER)              ||
+		(buffer->length == ACPI_ALLOCATE_BUFFER)        ||
+		(buffer->length == ACPI_ALLOCATE_LOCAL_BUFFER)) {
+		return (AE_OK);
+	}
+
+	/* Length is valid, the buffer pointer must be also */
+
+	if (!buffer->pointer) {
+		return (AE_BAD_PARAMETER);
+	}
+
+	return (AE_OK);
+}
 
 
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_initialize_buffer
+ *
+ * PARAMETERS:  Required_length     - Length needed
+ *              Buffer              - Buffer to be validated
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Validate that the buffer is of the required length or
+ *              allocate a new buffer.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_initialize_buffer (
+	acpi_buffer             *buffer,
+	ACPI_SIZE               required_length)
+{
+	acpi_status             status = AE_OK;
+
+
+	switch (buffer->length) {
+	case ACPI_NO_BUFFER:
+
+		/* Set the exception and returned the required length */
+
+		status = AE_BUFFER_OVERFLOW;
+		break;
+
+
+	case ACPI_ALLOCATE_BUFFER:
+
+		/* Allocate a new buffer */
+
+		buffer->pointer = acpi_os_allocate (required_length);
+		if (!buffer->pointer) {
+			return (AE_NO_MEMORY);
+		}
+
+		/* Clear the buffer */
+
+		ACPI_MEMSET (buffer->pointer, 0, required_length);
+		break;
+
+
+	case ACPI_ALLOCATE_LOCAL_BUFFER:
+
+		/* Allocate a new buffer with local interface to allow tracking */
+
+		buffer->pointer = ACPI_MEM_ALLOCATE (required_length);
+		if (!buffer->pointer) {
+			return (AE_NO_MEMORY);
+		}
+
+		/* Clear the buffer */
+
+		ACPI_MEMSET (buffer->pointer, 0, required_length);
+		break;
+
+
+	default:
+
+		/* Validate the size of the buffer */
+
+		if (buffer->length < required_length) {
+			status = AE_BUFFER_OVERFLOW;
+		}
+
+		/* Clear the buffer */
+
+		ACPI_MEMSET (buffer->pointer, 0, required_length);
+		break;
+	}
+
+	buffer->length = required_length;
+	return (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_allocate
+ *
+ * PARAMETERS:  Size                - Size of the allocation
+ *              Component           - Component type of caller
+ *              Module              - Source file name of caller
+ *              Line                - Line number of caller
+ *
+ * RETURN:      Address of the allocated memory on success, NULL on failure.
+ *
+ * DESCRIPTION: The subsystem's equivalent of malloc.
+ *
+ ******************************************************************************/
+
+void *
+acpi_ut_allocate (
+	ACPI_SIZE               size,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line)
+{
+	void                    *allocation;
+
+
+	ACPI_FUNCTION_TRACE_U32 ("Ut_allocate", size);
+
+
+	/* Check for an inadvertent size of zero bytes */
+
+	if (!size) {
+		_ACPI_REPORT_ERROR (module, line, component,
+				("Ut_allocate: Attempt to allocate zero bytes\n"));
+		size = 1;
+	}
+
+	allocation = acpi_os_allocate (size);
+	if (!allocation) {
+		/* Report allocation error */
+
+		_ACPI_REPORT_ERROR (module, line, component,
+				("Ut_allocate: Could not allocate size %X\n", size));
+
+		return_PTR (NULL);
+	}
+
+	return_PTR (allocation);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_callocate
+ *
+ * PARAMETERS:  Size                - Size of the allocation
+ *              Component           - Component type of caller
+ *              Module              - Source file name of caller
+ *              Line                - Line number of caller
+ *
+ * RETURN:      Address of the allocated memory on success, NULL on failure.
+ *
+ * DESCRIPTION: Subsystem equivalent of calloc.
+ *
+ ******************************************************************************/
+
+void *
+acpi_ut_callocate (
+	ACPI_SIZE               size,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line)
+{
+	void                    *allocation;
+
+
+	ACPI_FUNCTION_TRACE_U32 ("Ut_callocate", size);
+
+
+	/* Check for an inadvertent size of zero bytes */
+
+	if (!size) {
+		_ACPI_REPORT_ERROR (module, line, component,
+				("Ut_callocate: Attempt to allocate zero bytes\n"));
+		return_PTR (NULL);
+	}
+
+	allocation = acpi_os_allocate (size);
+	if (!allocation) {
+		/* Report allocation error */
+
+		_ACPI_REPORT_ERROR (module, line, component,
+				("Ut_callocate: Could not allocate size %X\n", size));
+		return_PTR (NULL);
+	}
+
+	/* Clear the memory block */
+
+	ACPI_MEMSET (allocation, 0, size);
+	return_PTR (allocation);
+}
+
+
+#ifdef ACPI_DBG_TRACK_ALLOCATIONS
 /*
  * These procedures are used for tracking memory leaks in the subsystem, and
  * they get compiled out when the ACPI_DBG_TRACK_ALLOCATIONS is not set.
@@ -208,9 +438,156 @@
 
 /*******************************************************************************
  *
+ * FUNCTION:    Acpi_ut_allocate_and_track
+ *
+ * PARAMETERS:  Size                - Size of the allocation
+ *              Component           - Component type of caller
+ *              Module              - Source file name of caller
+ *              Line                - Line number of caller
+ *
+ * RETURN:      Address of the allocated memory on success, NULL on failure.
+ *
+ * DESCRIPTION: The subsystem's equivalent of malloc.
+ *
+ ******************************************************************************/
+
+void *
+acpi_ut_allocate_and_track (
+	ACPI_SIZE               size,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line)
+{
+	acpi_debug_mem_block    *allocation;
+	acpi_status             status;
+
+
+	allocation = acpi_ut_allocate (size + sizeof (acpi_debug_mem_block), component,
+			  module, line);
+	if (!allocation) {
+		return (NULL);
+	}
+
+	status = acpi_ut_track_allocation (ACPI_MEM_LIST_GLOBAL, allocation, size,
+			  ACPI_MEM_MALLOC, component, module, line);
+	if (ACPI_FAILURE (status)) {
+		acpi_os_free (allocation);
+		return (NULL);
+	}
+
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].total_allocated++;
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].current_total_size += (u32) size;
+
+	return ((void *) &allocation->user_space);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_callocate_and_track
+ *
+ * PARAMETERS:  Size                - Size of the allocation
+ *              Component           - Component type of caller
+ *              Module              - Source file name of caller
+ *              Line                - Line number of caller
+ *
+ * RETURN:      Address of the allocated memory on success, NULL on failure.
+ *
+ * DESCRIPTION: Subsystem equivalent of calloc.
+ *
+ ******************************************************************************/
+
+void *
+acpi_ut_callocate_and_track (
+	ACPI_SIZE               size,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line)
+{
+	acpi_debug_mem_block    *allocation;
+	acpi_status             status;
+
+
+	allocation = acpi_ut_callocate (size + sizeof (acpi_debug_mem_block), component,
+			  module, line);
+	if (!allocation) {
+		/* Report allocation error */
+
+		_ACPI_REPORT_ERROR (module, line, component,
+				("Ut_callocate: Could not allocate size %X\n", size));
+		return (NULL);
+	}
+
+	status = acpi_ut_track_allocation (ACPI_MEM_LIST_GLOBAL, allocation, size,
+			   ACPI_MEM_CALLOC, component, module, line);
+	if (ACPI_FAILURE (status)) {
+		acpi_os_free (allocation);
+		return (NULL);
+	}
+
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].total_allocated++;
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].current_total_size += (u32) size;
+
+	return ((void *) &allocation->user_space);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_free_and_track
+ *
+ * PARAMETERS:  Allocation          - Address of the memory to deallocate
+ *              Component           - Component type of caller
+ *              Module              - Source file name of caller
+ *              Line                - Line number of caller
+ *
+ * RETURN:      None
+ *
+ * DESCRIPTION: Frees the memory at Allocation
+ *
+ ******************************************************************************/
+
+void
+acpi_ut_free_and_track (
+	void                    *allocation,
+	u32                     component,
+	NATIVE_CHAR             *module,
+	u32                     line)
+{
+	acpi_debug_mem_block    *debug_block;
+
+
+	ACPI_FUNCTION_TRACE_PTR ("Ut_free", allocation);
+
+
+	if (NULL == allocation) {
+		_ACPI_REPORT_ERROR (module, line, component,
+			("Acpi_ut_free: Attempt to delete a NULL address\n"));
+
+		return_VOID;
+	}
+
+	debug_block = (acpi_debug_mem_block *)
+			  (((char *) allocation) - sizeof (acpi_debug_mem_header));
+
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].total_freed++;
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].current_total_size -= debug_block->size;
+
+	acpi_ut_remove_allocation (ACPI_MEM_LIST_GLOBAL, debug_block,
+			component, module, line);
+	acpi_os_free (debug_block);
+
+	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "%p freed\n", allocation));
+
+	return_VOID;
+}
+
+
+/*******************************************************************************
+ *
  * FUNCTION:    Acpi_ut_find_allocation
  *
- * PARAMETERS:  Address             - Address of allocated memory
+ * PARAMETERS:  Allocation             - Address of allocated memory
  *
  * RETURN:      A list element if found; NULL otherwise.
  *
@@ -221,12 +598,12 @@
 acpi_debug_mem_block *
 acpi_ut_find_allocation (
 	u32                     list_id,
-	void                    *address)
+	void                    *allocation)
 {
 	acpi_debug_mem_block    *element;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	if (list_id > ACPI_MEM_LIST_MAX) {
@@ -238,7 +615,7 @@
 	/* Search for the address. */
 
 	while (element) {
-		if (element == address) {
+		if (element == allocation) {
 			return (element);
 		}
 
@@ -253,7 +630,7 @@
  *
  * FUNCTION:    Acpi_ut_track_allocation
  *
- * PARAMETERS:  Address             - Address of allocated memory
+ * PARAMETERS:  Allocation          - Address of allocated memory
  *              Size                - Size of the allocation
  *              Alloc_type          - MEM_MALLOC or MEM_CALLOC
  *              Component           - Component type of caller
@@ -269,8 +646,8 @@
 acpi_status
 acpi_ut_track_allocation (
 	u32                     list_id,
-	acpi_debug_mem_block    *address,
-	u32                     size,
+	acpi_debug_mem_block    *allocation,
+	ACPI_SIZE               size,
 	u8                      alloc_type,
 	u32                     component,
 	NATIVE_CHAR             *module,
@@ -281,7 +658,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_PTR ("Ut_track_allocation", address);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_track_allocation", allocation);
 
 
 	if (list_id > ACPI_MEM_LIST_MAX) {
@@ -289,46 +666,49 @@
 	}
 
 	mem_list = &acpi_gbl_memory_lists[list_id];
-	acpi_ut_acquire_mutex (ACPI_MTX_MEMORY);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_MEMORY);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/*
 	 * Search list for this address to make sure it is not already on the list.
 	 * This will catch several kinds of problems.
 	 */
 
-	element = acpi_ut_find_allocation (list_id, address);
+	element = acpi_ut_find_allocation (list_id, allocation);
 	if (element) {
-		REPORT_ERROR (("Ut_track_allocation: Address already present in list! (%p)\n",
-			address));
+		ACPI_REPORT_ERROR (("Ut_track_allocation: Allocation already present in list! (%p)\n",
+			allocation));
 
-		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Element %p Address %p\n", element, address));
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "Element %p Address %p\n", element, allocation));
 
 		goto unlock_and_exit;
 	}
 
 	/* Fill in the instance data. */
 
-	address->size      = size;
-	address->alloc_type = alloc_type;
-	address->component = component;
-	address->line      = line;
+	allocation->size      = (u32) size;
+	allocation->alloc_type = alloc_type;
+	allocation->component = component;
+	allocation->line      = line;
 
-	STRNCPY (address->module, module, MAX_MODULE_NAME);
+	ACPI_STRNCPY (allocation->module, module, ACPI_MAX_MODULE_NAME);
 
 	/* Insert at list head */
 
 	if (mem_list->list_head) {
-		((acpi_debug_mem_block *)(mem_list->list_head))->previous = address;
+		((acpi_debug_mem_block *)(mem_list->list_head))->previous = allocation;
 	}
 
-	address->next = mem_list->list_head;
-	address->previous = NULL;
+	allocation->next = mem_list->list_head;
+	allocation->previous = NULL;
 
-	mem_list->list_head = address;
+	mem_list->list_head = allocation;
 
 
 unlock_and_exit:
-	acpi_ut_release_mutex (ACPI_MTX_MEMORY);
+	status = acpi_ut_release_mutex (ACPI_MTX_MEMORY);
 	return_ACPI_STATUS (status);
 }
 
@@ -337,7 +717,7 @@
  *
  * FUNCTION:    Acpi_ut_remove_allocation
  *
- * PARAMETERS:  Address             - Address of allocated memory
+ * PARAMETERS:  Allocation          - Address of allocated memory
  *              Component           - Component type of caller
  *              Module              - Source file name of caller
  *              Line                - Line number of caller
@@ -351,15 +731,16 @@
 acpi_status
 acpi_ut_remove_allocation (
 	u32                     list_id,
-	acpi_debug_mem_block    *address,
+	acpi_debug_mem_block    *allocation,
 	u32                     component,
 	NATIVE_CHAR             *module,
 	u32                     line)
 {
 	ACPI_MEMORY_LIST        *mem_list;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_remove_allocation");
+	ACPI_FUNCTION_TRACE ("Ut_remove_allocation");
 
 
 	if (list_id > ACPI_MEM_LIST_MAX) {
@@ -370,37 +751,38 @@
 	if (NULL == mem_list->list_head) {
 		/* No allocations! */
 
-		_REPORT_ERROR (module, line, component,
+		_ACPI_REPORT_ERROR (module, line, component,
 				("Ut_remove_allocation: Empty allocation list, nothing to free!\n"));
 
 		return_ACPI_STATUS (AE_OK);
 	}
 
-
-	acpi_ut_acquire_mutex (ACPI_MTX_MEMORY);
+	status = acpi_ut_acquire_mutex (ACPI_MTX_MEMORY);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/* Unlink */
 
-	if (address->previous) {
-		(address->previous)->next = address->next;
+	if (allocation->previous) {
+		(allocation->previous)->next = allocation->next;
 	}
 	else {
-		mem_list->list_head = address->next;
+		mem_list->list_head = allocation->next;
 	}
 
-	if (address->next) {
-		(address->next)->previous = address->previous;
+	if (allocation->next) {
+		(allocation->next)->previous = allocation->previous;
 	}
 
-
 	/* Mark the segment as deleted */
 
-	MEMSET (&address->user_space, 0xEA, address->size);
+	ACPI_MEMSET (&allocation->user_space, 0xEA, allocation->size);
 
-	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "Freeing size %X\n", address->size));
+	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "Freeing size %X\n", allocation->size));
 
-	acpi_ut_release_mutex (ACPI_MTX_MEMORY);
-	return_ACPI_STATUS (AE_OK);
+	status = acpi_ut_release_mutex (ACPI_MTX_MEMORY);
+	return_ACPI_STATUS (status);
 }
 
 
@@ -424,7 +806,7 @@
 	ACPI_MEMORY_LIST        *Mem_list;
 */
 
-	FUNCTION_TRACE ("Ut_dump_allocation_info");
+	ACPI_FUNCTION_TRACE ("Ut_dump_allocation_info");
 
 /*
 	ACPI_DEBUG_PRINT (TRACE_ALLOCATIONS | TRACE_TABLES,
@@ -482,302 +864,114 @@
 	NATIVE_CHAR             *module)
 {
 	acpi_debug_mem_block    *element;
-	u32                     i;
-
-
-	FUNCTION_TRACE ("Ut_dump_allocations");
+	u32                     num_outstanding = 0;
 
 
-	element = acpi_gbl_memory_lists[0].list_head;
-	if (element == NULL) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_OK,
-				"No outstanding allocations.\n"));
-		return_VOID;
-	}
+	ACPI_FUNCTION_TRACE ("Ut_dump_allocations");
 
 
 	/*
 	 * Walk the allocation list.
 	 */
-	acpi_ut_acquire_mutex (ACPI_MTX_MEMORY);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_OK,
-		"Outstanding allocations:\n"));
+	if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_MEMORY))) {
+		return;
+	}
 
-	for (i = 1; ; i++)  /* Just a counter */ {
+	element = acpi_gbl_memory_lists[0].list_head;
+	while (element) {
 		if ((element->component & component) &&
-			((module == NULL) || (0 == STRCMP (module, element->module)))) {
+			((module == NULL) || (0 == ACPI_STRCMP (module, element->module)))) {
+			/* Ignore allocated objects that are in a cache */
+
 			if (((acpi_operand_object  *)(&element->user_space))->common.type != ACPI_CACHED_OBJECT) {
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-						 "%p Len %04X %9.9s-%d",
+				acpi_os_printf ("%p Len %04X %9.9s-%d ",
 						 &element->user_space, element->size, element->module,
-						 element->line));
+						 element->line);
 
 				/* Most of the elements will be internal objects. */
 
-				switch (((acpi_operand_object  *)
-					(&element->user_space))->common.data_type) {
+				switch (ACPI_GET_DESCRIPTOR_TYPE (&element->user_space)) {
 				case ACPI_DESC_TYPE_INTERNAL:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" Obj_type %12.12s R%d",
+					acpi_os_printf ("Obj_type %12.12s R%d",
 							acpi_ut_get_type_name (((acpi_operand_object *)(&element->user_space))->common.type),
-							((acpi_operand_object *)(&element->user_space))->common.reference_count));
+							((acpi_operand_object *)(&element->user_space))->common.reference_count);
 					break;
 
 				case ACPI_DESC_TYPE_PARSER:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" Parse_obj Opcode %04X",
-							((acpi_parse_object *)(&element->user_space))->opcode));
+					acpi_os_printf ("Parse_obj Opcode %04X",
+							((acpi_parse_object *)(&element->user_space))->opcode);
 					break;
 
 				case ACPI_DESC_TYPE_NAMED:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" Node %4.4s",
-							(char*)&((acpi_namespace_node *)(&element->user_space))->name));
+					acpi_os_printf ("Node %4.4s",
+							(char *) &((acpi_namespace_node *)(&element->user_space))->name);
 					break;
 
 				case ACPI_DESC_TYPE_STATE:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" Untyped State_obj"));
+					acpi_os_printf ("Untyped State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_UPDATE:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" UPDATE State_obj"));
+					acpi_os_printf ("UPDATE State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_PACKAGE:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" PACKAGE State_obj"));
+					acpi_os_printf ("PACKAGE State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_CONTROL:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" CONTROL State_obj"));
+					acpi_os_printf ("CONTROL State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_RPSCOPE:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" ROOT-PARSE-SCOPE State_obj"));
+					acpi_os_printf ("ROOT-PARSE-SCOPE State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_PSCOPE:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" PARSE-SCOPE State_obj"));
+					acpi_os_printf ("PARSE-SCOPE State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_WSCOPE:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" WALK-SCOPE State_obj"));
+					acpi_os_printf ("WALK-SCOPE State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_RESULT:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" RESULT State_obj"));
+					acpi_os_printf ("RESULT State_obj");
 					break;
 
 				case ACPI_DESC_TYPE_STATE_NOTIFY:
-					ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK,
-							" NOTIFY State_obj"));
+					acpi_os_printf ("NOTIFY State_obj");
+					break;
+
+				case ACPI_DESC_TYPE_STATE_THREAD:
+					acpi_os_printf ("THREAD State_obj");
 					break;
 				}
 
-				ACPI_DEBUG_PRINT_RAW ((ACPI_DB_OK, "\n"));
+				acpi_os_printf ( "\n");
+				num_outstanding++;
 			}
 		}
-
-		if (element->next == NULL) {
-			break;
-		}
-
 		element = element->next;
 	}
 
-	acpi_ut_release_mutex (ACPI_MTX_MEMORY);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_OK,
-		"Total number of unfreed allocations = %d(%X)\n", i,i));
-
-
-	return_VOID;
-
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ut_allocate
- *
- * PARAMETERS:  Size                - Size of the allocation
- *              Component           - Component type of caller
- *              Module              - Source file name of caller
- *              Line                - Line number of caller
- *
- * RETURN:      Address of the allocated memory on success, NULL on failure.
- *
- * DESCRIPTION: The subsystem's equivalent of malloc.
- *
- ******************************************************************************/
-
-void *
-acpi_ut_allocate (
-	u32                     size,
-	u32                     component,
-	NATIVE_CHAR             *module,
-	u32                     line)
-{
-	acpi_debug_mem_block    *address;
-	acpi_status             status;
-
-
-	FUNCTION_TRACE_U32 ("Ut_allocate", size);
-
-
-	/* Check for an inadvertent size of zero bytes */
-
-	if (!size) {
-		_REPORT_ERROR (module, line, component,
-				("Ut_allocate: Attempt to allocate zero bytes\n"));
-		size = 1;
-	}
-
-	address = acpi_os_allocate (size + sizeof (acpi_debug_mem_block));
-	if (!address) {
-		/* Report allocation error */
-
-		_REPORT_ERROR (module, line, component,
-				("Ut_allocate: Could not allocate size %X\n", size));
-
-		return_PTR (NULL);
-	}
-
-	status = acpi_ut_track_allocation (ACPI_MEM_LIST_GLOBAL, address, size,
-			  MEM_MALLOC, component, module, line);
-	if (ACPI_FAILURE (status)) {
-		acpi_os_free (address);
-		return_PTR (NULL);
-	}
-
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].total_allocated++;
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].current_total_size += size;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "%p Size %X\n", address, size));
-
-	return_PTR ((void *) &address->user_space);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ut_callocate
- *
- * PARAMETERS:  Size                - Size of the allocation
- *              Component           - Component type of caller
- *              Module              - Source file name of caller
- *              Line                - Line number of caller
- *
- * RETURN:      Address of the allocated memory on success, NULL on failure.
- *
- * DESCRIPTION: Subsystem equivalent of calloc.
- *
- ******************************************************************************/
-
-void *
-acpi_ut_callocate (
-	u32                     size,
-	u32                     component,
-	NATIVE_CHAR             *module,
-	u32                     line)
-{
-	acpi_debug_mem_block    *address;
-	acpi_status             status;
-
-
-	FUNCTION_TRACE_U32 ("Ut_callocate", size);
-
-
-	/* Check for an inadvertent size of zero bytes */
-
-	if (!size) {
-		_REPORT_ERROR (module, line, component,
-				("Ut_callocate: Attempt to allocate zero bytes\n"));
-		return_PTR (NULL);
-	}
-
-
-	address = acpi_os_callocate (size + sizeof (acpi_debug_mem_block));
-	if (!address) {
-		/* Report allocation error */
+	(void) acpi_ut_release_mutex (ACPI_MTX_MEMORY);
 
-		_REPORT_ERROR (module, line, component,
-				("Ut_callocate: Could not allocate size %X\n", size));
-		return_PTR (NULL);
-	}
+	/* Print summary */
 
-	status = acpi_ut_track_allocation (ACPI_MEM_LIST_GLOBAL, address, size,
-			   MEM_CALLOC, component, module, line);
-	if (ACPI_FAILURE (status)) {
-		acpi_os_free (address);
-		return_PTR (NULL);
+	if (!num_outstanding) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_OK,
+				"No outstanding allocations.\n"));
 	}
-
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].total_allocated++;
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].current_total_size += size;
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "%p Size %X\n", address, size));
-	return_PTR ((void *) &address->user_space);
-}
-
-
-/*******************************************************************************
- *
- * FUNCTION:    Acpi_ut_free
- *
- * PARAMETERS:  Address             - Address of the memory to deallocate
- *              Component           - Component type of caller
- *              Module              - Source file name of caller
- *              Line                - Line number of caller
- *
- * RETURN:      None
- *
- * DESCRIPTION: Frees the memory at Address
- *
- ******************************************************************************/
-
-void
-acpi_ut_free (
-	void                    *address,
-	u32                     component,
-	NATIVE_CHAR             *module,
-	u32                     line)
-{
-	acpi_debug_mem_block    *debug_block;
-
-
-	FUNCTION_TRACE_PTR ("Ut_free", address);
-
-
-	if (NULL == address) {
-		_REPORT_ERROR (module, line, component,
-			("Acpi_ut_free: Trying to delete a NULL address\n"));
-
-		return_VOID;
+	else {
+		ACPI_DEBUG_PRINT ((ACPI_DB_OK,
+			"%d(%X) Outstanding allocations\n",
+			num_outstanding, num_outstanding));
 	}
 
-	debug_block = (acpi_debug_mem_block *)
-			  (((char *) address) - sizeof (acpi_debug_mem_header));
-
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].total_freed++;
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_GLOBAL].current_total_size -= debug_block->size;
-
-	acpi_ut_remove_allocation (ACPI_MEM_LIST_GLOBAL, debug_block,
-			component, module, line);
-	acpi_os_free (debug_block);
-
-	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "%p freed\n", address));
-
 	return_VOID;
 }
+
 
 #endif  /* #ifdef ACPI_DBG_TRACK_ALLOCATIONS */
 
diff -Nru a/drivers/acpi/utilities/utcopy.c b/drivers/acpi/utilities/utcopy.c
--- a/drivers/acpi/utilities/utcopy.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/utilities/utcopy.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utcopy - Internal to external object translation utilities
- *              $Revision: 83 $
+ *              $Revision: 94 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utcopy")
+	 ACPI_MODULE_NAME    ("utcopy")
 
 
 /*******************************************************************************
@@ -56,27 +56,28 @@
 	acpi_operand_object     *internal_object,
 	acpi_object             *external_object,
 	u8                      *data_space,
-	u32                     *buffer_space_used)
+	ACPI_SIZE               *buffer_space_used)
 {
-	u32                     length = 0;
+	acpi_buffer             buffer;
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ut_copy_isimple_to_esimple");
+	ACPI_FUNCTION_TRACE ("Ut_copy_isimple_to_esimple");
+
 
+	*buffer_space_used = 0;
 
 	/*
 	 * Check for NULL object case (could be an uninitialized
 	 * package element
 	 */
 	if (!internal_object) {
-		*buffer_space_used = 0;
 		return_ACPI_STATUS (AE_OK);
 	}
 
 	/* Always clear the external object */
 
-	MEMSET (external_object, 0, sizeof (acpi_object));
+	ACPI_MEMSET (external_object, 0, sizeof (acpi_object));
 
 	/*
 	 * In general, the external object will be the same type as
@@ -87,28 +88,31 @@
 	/* However, only a limited number of external types are supported */
 
 	switch (internal_object->common.type) {
-
 	case ACPI_TYPE_STRING:
 
-		length = internal_object->string.length + 1;
-		external_object->string.length = internal_object->string.length;
 		external_object->string.pointer = (NATIVE_CHAR *) data_space;
-		MEMCPY ((void *) data_space, (void *) internal_object->string.pointer, length);
+		external_object->string.length = internal_object->string.length;
+		*buffer_space_used = ACPI_ROUND_UP_TO_NATIVE_WORD (internal_object->string.length + 1);
+
+		ACPI_MEMCPY ((void *) data_space, (void *) internal_object->string.pointer,
+				 internal_object->string.length + 1);
 		break;
 
 
 	case ACPI_TYPE_BUFFER:
 
-		length = internal_object->buffer.length;
-		external_object->buffer.length = internal_object->buffer.length;
 		external_object->buffer.pointer = data_space;
-		MEMCPY ((void *) data_space, (void *) internal_object->buffer.pointer, length);
+		external_object->buffer.length = internal_object->buffer.length;
+		*buffer_space_used = ACPI_ROUND_UP_TO_NATIVE_WORD (internal_object->string.length);
+
+		ACPI_MEMCPY ((void *) data_space, (void *) internal_object->buffer.pointer,
+				 internal_object->buffer.length);
 		break;
 
 
 	case ACPI_TYPE_INTEGER:
 
-		external_object->integer.value= internal_object->integer.value;
+		external_object->integer.value = internal_object->integer.value;
 		break;
 
 
@@ -143,15 +147,19 @@
 			 * This is a named reference, get the string.  We already know that
 			 * we have room for it, use max length
 			 */
-			length = MAX_STRING_LENGTH;
 			external_object->type = ACPI_TYPE_STRING;
 			external_object->string.pointer = (NATIVE_CHAR *) data_space;
+
+			buffer.length = MAX_STRING_LENGTH;
+			buffer.pointer = data_space;
+
 			status = acpi_ns_handle_to_pathname ((acpi_handle *) internal_object->reference.node,
-					 &length, (char *) data_space);
+					 &buffer);
 
 			/* Converted (external) string length is returned from above */
 
-			external_object->string.length = length;
+			external_object->string.length = buffer.length;
+			*buffer_space_used = ACPI_ROUND_UP_TO_NATIVE_WORD (buffer.length);
 			break;
 
 		default:
@@ -189,12 +197,8 @@
 		 * There is no corresponding external object type
 		 */
 		return_ACPI_STATUS (AE_SUPPORT);
-		break;
 	}
 
-
-	*buffer_space_used = (u32) ROUND_UP_TO_NATIVE_WORD (length);
-
 	return_ACPI_STATUS (status);
 }
 
@@ -220,12 +224,12 @@
 {
 	acpi_status             status = AE_OK;
 	acpi_pkg_info           *info = (acpi_pkg_info *) context;
-	u32                     object_space;
+	ACPI_SIZE               object_space;
 	u32                     this_index;
 	acpi_object             *target_object;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	this_index   = state->pkg.index;
@@ -236,16 +240,16 @@
 	case ACPI_COPY_TYPE_SIMPLE:
 
 		/*
-		 * This is a simple or null object -- get the size
+		 * This is a simple or null object
 		 */
 		status = acpi_ut_copy_isimple_to_esimple (source_object,
 				  target_object, info->free_space, &object_space);
 		if (ACPI_FAILURE (status)) {
 			return (status);
 		}
-
 		break;
 
+
 	case ACPI_COPY_TYPE_PACKAGE:
 
 		/*
@@ -264,18 +268,17 @@
 		 * Save space for the array of objects (Package elements)
 		 * update the buffer length counter
 		 */
-		object_space = (u32) ROUND_UP_TO_NATIVE_WORD (
+		object_space = ACPI_ROUND_UP_TO_NATIVE_WORD (
 				   target_object->package.count * sizeof (acpi_object));
 		break;
 
+
 	default:
 		return (AE_BAD_PARAMETER);
 	}
 
-
 	info->free_space  += object_space;
 	info->length      += object_space;
-
 	return (status);
 }
 
@@ -303,14 +306,14 @@
 acpi_ut_copy_ipackage_to_epackage (
 	acpi_operand_object     *internal_object,
 	u8                      *buffer,
-	u32                     *space_used)
+	ACPI_SIZE               *space_used)
 {
 	acpi_object             *external_object;
 	acpi_status             status;
 	acpi_pkg_info           info;
 
 
-	FUNCTION_TRACE ("Ut_copy_ipackage_to_epackage");
+	ACPI_FUNCTION_TRACE ("Ut_copy_ipackage_to_epackage");
 
 
 	/*
@@ -324,31 +327,27 @@
 	info.length      = 0;
 	info.object_space = 0;
 	info.num_packages = 1;
-	info.free_space  = buffer + ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object));
-
+	info.free_space  = buffer + ACPI_ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object));
 
 	external_object->type              = internal_object->common.type;
 	external_object->package.count     = internal_object->package.count;
 	external_object->package.elements  = (acpi_object *) info.free_space;
 
-
 	/*
 	 * Build an array of ACPI_OBJECTS in the buffer
 	 * and move the free space past it
 	 */
 	info.free_space += external_object->package.count *
-			  ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object));
-
+			  ACPI_ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object));
 
 	status = acpi_ut_walk_package_tree (internal_object, external_object,
 			 acpi_ut_copy_ielement_to_eelement, &info);
 
 	*space_used = info.length;
-
 	return_ACPI_STATUS (status);
-
 }
 
+
 /*******************************************************************************
  *
  * FUNCTION:    Acpi_ut_copy_iobject_to_eobject
@@ -371,10 +370,10 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_copy_iobject_to_eobject");
+	ACPI_FUNCTION_TRACE ("Ut_copy_iobject_to_eobject");
 
 
-	if (IS_THIS_OBJECT_TYPE (internal_object, ACPI_TYPE_PACKAGE)) {
+	if (internal_object->common.type == ACPI_TYPE_PACKAGE) {
 		/*
 		 * Package object:  Copy all subobjects (including
 		 * nested packages)
@@ -382,7 +381,6 @@
 		status = acpi_ut_copy_ipackage_to_epackage (internal_object,
 				  ret_buffer->pointer, &ret_buffer->length);
 	}
-
 	else {
 		/*
 		 * Build a simple object (no nested objects)
@@ -390,7 +388,7 @@
 		status = acpi_ut_copy_isimple_to_esimple (internal_object,
 				  (acpi_object *) ret_buffer->pointer,
 				  ((u8 *) ret_buffer->pointer +
-				  ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object))),
+				  ACPI_ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object))),
 				  &ret_buffer->length);
 		/*
 		 * build simple does not include the object size in the length
@@ -427,7 +425,7 @@
 	acpi_operand_object     *internal_object;
 
 
-	FUNCTION_TRACE ("Ut_copy_esimple_to_isimple");
+	ACPI_FUNCTION_TRACE ("Ut_copy_esimple_to_isimple");
 
 
 	/*
@@ -449,7 +447,6 @@
 		 * Whatever other type -- it is not supported
 		 */
 		return_ACPI_STATUS (AE_SUPPORT);
-		break;
 	}
 
 
@@ -464,9 +461,9 @@
 			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
-		MEMCPY (internal_object->string.pointer,
-				external_object->string.pointer,
-				external_object->string.length);
+		ACPI_MEMCPY (internal_object->string.pointer,
+				  external_object->string.pointer,
+				  external_object->string.length);
 
 		internal_object->string.length = external_object->string.length;
 		break;
@@ -479,9 +476,9 @@
 			return_ACPI_STATUS (AE_NO_MEMORY);
 		}
 
-		MEMCPY (internal_object->buffer.pointer,
-				external_object->buffer.pointer,
-				external_object->buffer.length);
+		ACPI_MEMCPY (internal_object->buffer.pointer,
+				  external_object->buffer.pointer,
+				  external_object->buffer.length);
 
 		internal_object->buffer.length = external_object->buffer.length;
 		break;
@@ -493,7 +490,6 @@
 		break;
 	}
 
-
 	*ret_internal_object = internal_object;
 	return_ACPI_STATUS (AE_OK);
 }
@@ -537,7 +533,7 @@
 	acpi_object             *this_external_obj;
 
 
-	FUNCTION_TRACE ("Ut_copy_epackage_to_ipackage");
+	ACPI_FUNCTION_TRACE ("Ut_copy_epackage_to_ipackage");
 
 
 	/*
@@ -591,23 +587,13 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_copy_eobject_to_iobject");
+	ACPI_FUNCTION_TRACE ("Ut_copy_eobject_to_iobject");
 
 
 	if (external_object->type == ACPI_TYPE_PACKAGE) {
 		/*
-		 * Package objects contain other objects (which can be objects)
-		 * buildpackage does it all
-		 *
-		 * TBD: Package conversion must be completed and tested
-		 * NOTE: this code converts packages as input parameters to
-		 * control methods only.  This is a very, very rare case.
+		 * Packages as external input to control methods are not supported,
 		 */
-/*
-		Status = Acpi_ut_copy_epackage_to_ipackage(Internal_object,
-				 Ret_buffer->Pointer,
-				 &Ret_buffer->Length);
-*/
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 			"Packages as parameters not implemented!\n"));
 
@@ -627,11 +613,80 @@
 
 /*******************************************************************************
  *
+ * FUNCTION:    Acpi_ut_copy_simple_object
+ *
+ * PARAMETERS:  Source_desc         - The internal object to be copied
+ *              Dest_desc           - New target object
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Simple copy of one internal object to another.  Reference count
+ *              of the destination object is preserved.
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_copy_simple_object (
+	acpi_operand_object     *source_desc,
+	acpi_operand_object     *dest_desc)
+{
+	u16                     reference_count;
+	acpi_operand_object     *next_object;
+
+
+	/* Save fields from destination that we don't want to overwrite */
+
+	reference_count = dest_desc->common.reference_count;
+	next_object = dest_desc->common.next_object;
+
+	/* Copy the entire source object over the destination object*/
+
+	ACPI_MEMCPY ((char *) dest_desc, (char *) source_desc, sizeof (acpi_operand_object));
+
+	/* Restore the saved fields */
+
+	dest_desc->common.reference_count = reference_count;
+	dest_desc->common.next_object = next_object;
+
+	/* Handle the objects with extra data */
+
+	switch (dest_desc->common.type) {
+	case ACPI_TYPE_BUFFER:
+
+		dest_desc->buffer.node = NULL;
+
+	case ACPI_TYPE_STRING:
+
+		/*
+		 * Allocate and copy the actual string if and only if:
+		 * 1) There is a valid string (length > 0)
+		 * 2) The string is not static (not in an ACPI table) (in this case,
+		 *    the actual pointer was already copied above)
+		 */
+		if ((source_desc->string.length) &&
+			(!(source_desc->common.flags & AOPOBJ_STATIC_POINTER))) {
+			dest_desc->string.pointer = ACPI_MEM_ALLOCATE (source_desc->string.length);
+			if (!dest_desc->string.pointer) {
+				return (AE_NO_MEMORY);
+			}
+
+			ACPI_MEMCPY (dest_desc->string.pointer, source_desc->string.pointer,
+					  source_desc->string.length);
+		}
+		break;
+	}
+
+	return (AE_OK);
+}
+
+
+/*******************************************************************************
+ *
  * FUNCTION:    Acpi_ut_copy_ielement_to_ielement
  *
  * PARAMETERS:  ACPI_PKG_CALLBACK
  *
- * RETURN:      Status          - the status of the call
+ * RETURN:      Status
  *
  * DESCRIPTION: Copy one package element to another package element
  *
@@ -650,7 +705,7 @@
 	acpi_operand_object     *target_object;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	this_index    = state->pkg.index;
@@ -668,8 +723,7 @@
 			return (AE_NO_MEMORY);
 		}
 
-		status = acpi_ex_store_object_to_object (source_object, target_object,
-				  (acpi_walk_state *) context);
+		status = acpi_ut_copy_simple_object (source_object, target_object);
 		if (ACPI_FAILURE (status)) {
 			return (status);
 		}
@@ -679,14 +733,13 @@
 
 
 	case 1:
+
 		/*
 		 * This object is a package - go down another nesting level
 		 * Create and build the package object
 		 */
 		target_object = acpi_ut_create_internal_object (ACPI_TYPE_PACKAGE);
 		if (!target_object) {
-			/* TBD: must delete package created up to this point */
-
 			return (AE_NO_MEMORY);
 		}
 
@@ -703,11 +756,11 @@
 		*this_target_ptr = target_object;
 		break;
 
+
 	default:
 		return (AE_BAD_PARAMETER);
 	}
 
-
 	return (status);
 }
 
@@ -735,7 +788,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Ut_copy_ipackage_to_ipackage");
+	ACPI_FUNCTION_TRACE ("Ut_copy_ipackage_to_ipackage");
 
 
 	dest_obj->common.type   = source_obj->common.type;
@@ -747,18 +800,76 @@
 	 */
 	dest_obj->package.elements = ACPI_MEM_CALLOCATE ((source_obj->package.count + 1) *
 			 sizeof (void *));
-	dest_obj->package.next_element = dest_obj->package.elements;
-
 	if (!dest_obj->package.elements) {
-		REPORT_ERROR (
+		ACPI_REPORT_ERROR (
 			("Aml_build_copy_internal_package_object: Package allocation failure\n"));
 		return_ACPI_STATUS (AE_NO_MEMORY);
 	}
 
+	/* Init */
 
+	dest_obj->package.next_element = dest_obj->package.elements;
+
+	/*
+	 * Copy the package element-by-element by walking the package "tree".
+	 * This handles nested packages of arbitrary depth.
+	 */
 	status = acpi_ut_walk_package_tree (source_obj, dest_obj,
 			 acpi_ut_copy_ielement_to_ielement, walk_state);
+	if (ACPI_FAILURE (status)) {
+		/* On failure, delete the destination package object */
+
+		acpi_ut_remove_reference (dest_obj);
+	}
+
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_copy_iobject_to_iobject
+ *
+ * PARAMETERS:  Walk_state          - Current walk state
+ *              Source_desc         - The internal object to be copied
+ *              Dest_desc           - Where the copied object is returned
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Copy an internal object to a new internal object
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_copy_iobject_to_iobject (
+	acpi_operand_object     *source_desc,
+	acpi_operand_object     **dest_desc,
+	acpi_walk_state         *walk_state)
+{
+	acpi_status             status = AE_OK;
+
+
+	ACPI_FUNCTION_TRACE ("Ut_copy_iobject_to_iobject");
+
+
+	/* Create the top level object */
+
+	*dest_desc = acpi_ut_create_internal_object (source_desc->common.type);
+	if (!*dest_desc) {
+		return_ACPI_STATUS (AE_NO_MEMORY);
+	}
+
+	/* Copy the object and possible subobjects */
+
+	if (source_desc->common.type == ACPI_TYPE_PACKAGE) {
+		status = acpi_ut_copy_ipackage_to_ipackage (source_desc, *dest_desc,
+				  walk_state);
+	}
+	else {
+		status = acpi_ut_copy_simple_object (source_desc, *dest_desc);
+	}
 
 	return_ACPI_STATUS (status);
 }
+
 
diff -Nru a/drivers/acpi/utilities/utdebug.c b/drivers/acpi/utilities/utdebug.c
--- a/drivers/acpi/utilities/utdebug.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/utilities/utdebug.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utdebug - Debug print routines
- *              $Revision: 90 $
+ *              $Revision: 96 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -27,7 +27,7 @@
 #include "acpi.h"
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utdebug")
+	 ACPI_MODULE_NAME    ("utdebug")
 
 
 u32             acpi_gbl_prev_thread_id = 0xFFFFFFFF;
@@ -57,7 +57,7 @@
 	u32                 current_sp;
 
 
-	acpi_gbl_entry_stack_pointer = (u32) &current_sp;
+	acpi_gbl_entry_stack_pointer = ACPI_PTR_DIFF (&current_sp, NULL);
 }
 
 
@@ -77,9 +77,10 @@
 acpi_ut_track_stack_ptr (
 	void)
 {
-	u32                 current_sp;
+	ACPI_SIZE           current_sp;
+
 
-	current_sp = (u32) &current_sp;
+	current_sp = ACPI_PTR_DIFF (&current_sp, NULL);
 
 	if (current_sp < acpi_gbl_lowest_stack_pointer) {
 		acpi_gbl_lowest_stack_pointer = current_sp;
@@ -111,7 +112,7 @@
  *
  ****************************************************************************/
 
-void
+void  ACPI_INTERNAL_VAR_XFACE
 acpi_ut_debug_print (
 	u32                     requested_debug_level,
 	u32                     line_number,
@@ -184,7 +185,7 @@
  *
  ****************************************************************************/
 
-void
+void  ACPI_INTERNAL_VAR_XFACE
 acpi_ut_debug_print_raw (
 	u32                     requested_debug_level,
 	u32                     line_number,
@@ -431,7 +432,8 @@
 {
 
 	acpi_ut_debug_print (ACPI_LV_FUNCTIONS, line_number, dbg_info,
-			"%s %8.8X%8.8X\n", acpi_gbl_fn_exit_str, HIDWORD(value), LODWORD(value));
+			"%s %8.8X%8.8X\n", acpi_gbl_fn_exit_str,
+			ACPI_HIDWORD (value), ACPI_LODWORD (value));
 
 	acpi_gbl_nesting_level--;
 }
@@ -539,8 +541,8 @@
 
 			case DB_WORD_DISPLAY:
 
-				MOVE_UNALIGNED16_TO_32 (&temp32,
-						 &buffer[i + j]);
+				ACPI_MOVE_UNALIGNED16_TO_32 (&temp32,
+						   &buffer[i + j]);
 				acpi_os_printf ("%04X ", temp32);
 				j += 2;
 				break;
@@ -548,8 +550,8 @@
 
 			case DB_DWORD_DISPLAY:
 
-				MOVE_UNALIGNED32_TO_32 (&temp32,
-						 &buffer[i + j]);
+				ACPI_MOVE_UNALIGNED32_TO_32 (&temp32,
+						   &buffer[i + j]);
 				acpi_os_printf ("%08X ", temp32);
 				j += 4;
 				break;
@@ -557,12 +559,12 @@
 
 			case DB_QWORD_DISPLAY:
 
-				MOVE_UNALIGNED32_TO_32 (&temp32,
-						 &buffer[i + j]);
+				ACPI_MOVE_UNALIGNED32_TO_32 (&temp32,
+						   &buffer[i + j]);
 				acpi_os_printf ("%08X", temp32);
 
-				MOVE_UNALIGNED32_TO_32 (&temp32,
-						 &buffer[i + j + 4]);
+				ACPI_MOVE_UNALIGNED32_TO_32 (&temp32,
+						   &buffer[i + j + 4]);
 				acpi_os_printf ("%08X ", temp32);
 				j += 8;
 				break;
diff -Nru a/drivers/acpi/utilities/utdelete.c b/drivers/acpi/utilities/utdelete.c
--- a/drivers/acpi/utilities/utdelete.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/utilities/utdelete.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: utdelete - object deletion and reference count utilities
- *              $Revision: 81 $
+ *              $Revision: 87 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -31,7 +31,7 @@
 #include "acparser.h"
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utdelete")
+	 ACPI_MODULE_NAME    ("utdelete")
 
 
 /*******************************************************************************
@@ -53,9 +53,10 @@
 {
 	void                    *obj_pointer = NULL;
 	acpi_operand_object     *handler_desc;
+	acpi_operand_object     *second_desc;
 
 
-	FUNCTION_TRACE_PTR ("Ut_delete_internal_obj", object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_delete_internal_obj", object);
 
 
 	if (!object) {
@@ -138,7 +139,6 @@
 			acpi_os_delete_semaphore (object->method.semaphore);
 			object->method.semaphore = NULL;
 		}
-
 		break;
 
 
@@ -146,7 +146,8 @@
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "***** Region %p\n", object));
 
-		if (object->region.extra) {
+		second_desc = acpi_ns_get_secondary_object (object);
+		if (second_desc) {
 			/*
 			 * Free the Region_context if and only if the handler is one of the
 			 * default handlers -- and therefore, we created the context object
@@ -154,13 +155,13 @@
 			 */
 			handler_desc = object->region.addr_handler;
 			if ((handler_desc) &&
-				(handler_desc->addr_handler.hflags == ADDR_HANDLER_DEFAULT_INSTALLED)) {
-				obj_pointer = object->region.extra->extra.region_context;
+				(handler_desc->addr_handler.hflags == ACPI_ADDR_HANDLER_DEFAULT_INSTALLED)) {
+				obj_pointer = second_desc->extra.region_context;
 			}
 
 			/* Now we can free the Extra object */
 
-			acpi_ut_delete_object_desc (object->region.extra);
+			acpi_ut_delete_object_desc (second_desc);
 		}
 		break;
 
@@ -169,38 +170,32 @@
 
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "***** Buffer Field %p\n", object));
 
-		if (object->buffer_field.extra) {
-			acpi_ut_delete_object_desc (object->buffer_field.extra);
+		second_desc = acpi_ns_get_secondary_object (object);
+		if (second_desc) {
+			acpi_ut_delete_object_desc (second_desc);
 		}
 		break;
 
+
 	default:
 		break;
 	}
 
 
-	/*
-	 * Delete any allocated memory found above
-	 */
+	/* Free any allocated memory (pointer within the object) found above */
+
 	if (obj_pointer) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting Obj Ptr %p \n", obj_pointer));
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting Object Subptr %p\n",
+				obj_pointer));
 		ACPI_MEM_FREE (obj_pointer);
 	}
 
-	/* Only delete the object if it was dynamically allocated */
-
-	if (object->common.flags & AOPOBJ_STATIC_ALLOCATION) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Object %p [%s] static allocation, no delete\n",
-			object, acpi_ut_get_type_name (object->common.type)));
-	}
+	/* Now the object can be safely deleted */
 
-	if (!(object->common.flags & AOPOBJ_STATIC_ALLOCATION)) {
-		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting object %p [%s]\n",
+	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Deleting Object %p [%s]\n",
 			object, acpi_ut_get_type_name (object->common.type)));
 
-		acpi_ut_delete_object_desc (object);
-	}
-
+	acpi_ut_delete_object_desc (object);
 	return_VOID;
 }
 
@@ -225,7 +220,7 @@
 	acpi_operand_object     **internal_obj;
 
 
-	FUNCTION_TRACE ("Ut_delete_internal_object_list");
+	ACPI_FUNCTION_TRACE ("Ut_delete_internal_object_list");
 
 
 	/* Walk the null-terminated internal list */
@@ -264,7 +259,7 @@
 	u16                     new_count;
 
 
-	PROC_NAME ("Ut_update_ref_count");
+	ACPI_FUNCTION_NAME ("Ut_update_ref_count");
 
 	if (!object) {
 		return;
@@ -386,7 +381,7 @@
 	acpi_generic_state       *state;
 
 
-	FUNCTION_TRACE_PTR ("Ut_update_object_reference", object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_update_object_reference", object);
 
 
 	/* Ignore a null object ptr */
@@ -395,16 +390,14 @@
 		return_ACPI_STATUS (AE_OK);
 	}
 
-
 	/*
-	 * Make sure that this isn't a namespace handle or an AML pointer
+	 * Make sure that this isn't a namespace handle
 	 */
-	if (VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_NAMED)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (object) == ACPI_DESC_TYPE_NAMED) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Object %p is NS handle\n", object));
 		return_ACPI_STATUS (AE_OK);
 	}
 
-
 	state = acpi_ut_create_update_state (object, action);
 
 	while (state) {
@@ -417,7 +410,6 @@
 		 * Different object types have different subobjects.
 		 */
 		switch (object->common.type) {
-
 		case ACPI_TYPE_DEVICE:
 
 			status = acpi_ut_create_update_state_and_push (object->device.addr_handler,
@@ -490,7 +482,7 @@
 		case INTERNAL_TYPE_BANK_FIELD:
 
 			status = acpi_ut_create_update_state_and_push (
-					 object->bank_field.bank_register_obj, action, &state_list);
+					 object->bank_field.bank_obj, action, &state_list);
 			if (ACPI_FAILURE (status)) {
 				return_ACPI_STATUS (status);
 			}
@@ -526,7 +518,6 @@
 			break;
 		}
 
-
 		/*
 		 * Now we can update the count in the main object.  This can only
 		 * happen after we update the sub-objects in case this causes the
@@ -534,13 +525,11 @@
 		 */
 		acpi_ut_update_ref_count (object, action);
 
-
 		/* Move on to the next object to be updated */
 
 		state = acpi_ut_pop_generic_state (&state_list);
 	}
 
-
 	return_ACPI_STATUS (AE_OK);
 }
 
@@ -563,7 +552,7 @@
 	acpi_operand_object     *object)
 {
 
-	FUNCTION_TRACE_PTR ("Ut_add_reference", object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_add_reference", object);
 
 
 	/*
@@ -599,7 +588,7 @@
 	acpi_operand_object     *object)
 {
 
-	FUNCTION_TRACE_PTR ("Ut_remove_reference", object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_remove_reference", object);
 
 	/*
 	 * Allow a NULL pointer to be passed in, just ignore it.  This saves
@@ -607,7 +596,7 @@
 	 *
 	 */
 	if (!object ||
-		(VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_NAMED))) {
+		(ACPI_GET_DESCRIPTOR_TYPE (object) == ACPI_DESC_TYPE_NAMED)) {
 		return_VOID;
 	}
 
diff -Nru a/drivers/acpi/utilities/uteval.c b/drivers/acpi/utilities/uteval.c
--- a/drivers/acpi/utilities/uteval.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/utilities/uteval.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: uteval - Object evaluation
- *              $Revision: 31 $
+ *              $Revision: 37 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -30,7 +30,7 @@
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("uteval")
+	 ACPI_MODULE_NAME    ("uteval")
 
 
 /*******************************************************************************
@@ -60,7 +60,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_evaluate_numeric_object");
+	ACPI_FUNCTION_TRACE ("Ut_evaluate_numeric_object");
 
 
 	/* Execute the method */
@@ -69,11 +69,11 @@
 	if (ACPI_FAILURE (status)) {
 		if (status == AE_NOT_FOUND) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "%s on %4.4s was not found\n",
-				object_name, (char*)&device_node->name));
+				object_name, (char *) &device_node->name));
 		}
 		else {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "%s on %4.4s failed with status %s\n",
-				object_name, (char*)&device_node->name,
+				object_name, (char *) &device_node->name,
 				acpi_format_exception (status)));
 		}
 
@@ -138,7 +138,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_execute_HID");
+	ACPI_FUNCTION_TRACE ("Ut_execute_HID");
 
 
 	/* Execute the method */
@@ -148,12 +148,11 @@
 	if (ACPI_FAILURE (status)) {
 		if (status == AE_NOT_FOUND) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "_HID on %4.4s was not found\n",
-				(char*)&device_node->name));
+				(char *) &device_node->name));
 		}
-
 		else {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_HID on %4.4s failed %s\n",
-				(char*)&device_node->name, acpi_format_exception (status)));
+				(char *) &device_node->name, acpi_format_exception (status)));
 		}
 
 		return_ACPI_STATUS (status);
@@ -177,21 +176,111 @@
 			"Type returned from _HID not a number or string: %s(%X) \n",
 			acpi_ut_get_type_name (obj_desc->common.type), obj_desc->common.type));
 	}
-
 	else {
 		if (obj_desc->common.type == ACPI_TYPE_INTEGER) {
 			/* Convert the Numeric HID to string */
 
 			acpi_ex_eisa_id_to_string ((u32) obj_desc->integer.value, hid->buffer);
 		}
-
 		else {
 			/* Copy the String HID from the returned object */
 
-			STRNCPY(hid->buffer, obj_desc->string.pointer, sizeof(hid->buffer));
+			ACPI_STRNCPY (hid->buffer, obj_desc->string.pointer, sizeof(hid->buffer));
+		}
+	}
+
+	/* On exit, we must delete the return object */
+
+	acpi_ut_remove_reference (obj_desc);
+
+	return_ACPI_STATUS (status);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_execute_CID
+ *
+ * PARAMETERS:  Device_node         - Node for the device
+ *              *Cid                - Where the CID is returned
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Executes the _CID control method that returns one or more
+ *              compatible hardware IDs for the device.
+ *
+ *              NOTE: Internal function, no parameter validation
+ *
+ ******************************************************************************/
+
+acpi_status
+acpi_ut_execute_CID (
+	acpi_namespace_node     *device_node,
+	acpi_device_id          *cid)
+{
+	acpi_operand_object     *obj_desc;
+	acpi_status             status;
+
+
+	ACPI_FUNCTION_TRACE ("Ut_execute_CID");
+
+	/* Execute the method */
+
+	status = acpi_ns_evaluate_relative (device_node,
+			 METHOD_NAME__CID, NULL, &obj_desc);
+	if (ACPI_FAILURE (status)) {
+		if (status == AE_NOT_FOUND) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "_CID on %4.4s was not found\n",
+				(char *)&device_node->name));
 		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_CID on %4.4s failed %s\n",
+				(char *)&device_node->name, acpi_format_exception (status)));
+		}
+
+		return_ACPI_STATUS (status);
 	}
 
+	/* Did we get a return object? */
+
+	if (!obj_desc) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "No object was returned from _CID\n"));
+		return_ACPI_STATUS (AE_TYPE);
+	}
+
+	/*
+	 *  A _CID can return either a single compatible ID or a package of compatible
+	 *  IDs.  Each compatible ID can be a Number (32 bit compressed EISA ID) or
+	 *  string (PCI ID format, e.g. "PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss").
+	 */
+	switch (obj_desc->common.type) {
+	case ACPI_TYPE_INTEGER:
+
+		/* Convert the Numeric CID to string */
+
+		acpi_ex_eisa_id_to_string ((u32) obj_desc->integer.value, cid->buffer);
+		break;
+
+	case ACPI_TYPE_STRING:
+
+		/* Copy the String CID from the returned object */
+
+		ACPI_STRNCPY (cid->buffer, obj_desc->string.pointer, sizeof(cid->buffer));
+		break;
+
+	case ACPI_TYPE_PACKAGE:
+
+		/* TBD: Parse package elements; need different return struct, etc. */
+		break;
+
+	default:
+
+		status = AE_TYPE;
+		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+			"Type returned from _CID not a number, string, or package: %s(%X) \n",
+			acpi_ut_get_type_name (obj_desc->common.type), obj_desc->common.type));
+		break;
+	}
 
 	/* On exit, we must delete the return object */
 
@@ -226,7 +315,7 @@
 	acpi_status             status;
 
 
-	PROC_NAME ("Ut_execute_UID");
+	ACPI_FUNCTION_NAME ("Ut_execute_UID");
 
 
 	/* Execute the method */
@@ -236,13 +325,12 @@
 	if (ACPI_FAILURE (status)) {
 		if (status == AE_NOT_FOUND) {
 			ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "_UID on %4.4s was not found\n",
-				(char*)&device_node->name));
+				(char *) &device_node->name));
 		}
-
 		else {
 			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 				"_UID on %4.4s failed %s\n",
-				(char*)&device_node->name, acpi_format_exception (status)));
+				(char *) &device_node->name, acpi_format_exception (status)));
 		}
 
 		return (status);
@@ -266,18 +354,16 @@
 			"Type returned from _UID was not a number or string: %X \n",
 			obj_desc->common.type));
 	}
-
 	else {
 		if (obj_desc->common.type == ACPI_TYPE_INTEGER) {
 			/* Convert the Numeric UID to string */
 
 			acpi_ex_unsigned_integer_to_string (obj_desc->integer.value, uid->buffer);
 		}
-
 		else {
 			/* Copy the String UID from the returned object */
 
-			STRNCPY(uid->buffer, obj_desc->string.pointer, sizeof(uid->buffer));
+			ACPI_STRNCPY (uid->buffer, obj_desc->string.pointer, sizeof(uid->buffer));
 		}
 	}
 
@@ -315,7 +401,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_execute_STA");
+	ACPI_FUNCTION_TRACE ("Ut_execute_STA");
 
 
 	/* Execute the method */
@@ -325,7 +411,7 @@
 	if (AE_NOT_FOUND == status) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
 			"_STA on %4.4s was not found, assuming present.\n",
-			(char*)&device_node->name));
+			(char *) &device_node->name));
 
 		*flags = 0x0F;
 		status = AE_OK;
@@ -333,7 +419,7 @@
 
 	else if (ACPI_FAILURE (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR, "_STA on %4.4s failed %s\n",
-			(char*)&device_node->name,
+			(char *) &device_node->name,
 			acpi_format_exception (status)));
 	}
 
@@ -353,7 +439,6 @@
 				"Type returned from _STA was not a number: %X \n",
 				obj_desc->common.type));
 		}
-
 		else {
 			/* Extract the status flags */
 
diff -Nru a/drivers/acpi/utilities/utglobal.c b/drivers/acpi/utilities/utglobal.c
--- a/drivers/acpi/utilities/utglobal.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/utilities/utglobal.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utglobal - Global variables for the ACPI subsystem
- *              $Revision: 133 $
+ *              $Revision: 153 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -33,7 +33,7 @@
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utglobal")
+	 ACPI_MODULE_NAME    ("utglobal")
 
 
 /******************************************************************************
@@ -136,10 +136,9 @@
 
 /* System flags */
 
-u32                         acpi_gbl_system_flags = 0;
 u32                         acpi_gbl_startup_flags = 0;
 
-/* System starts unitialized! */
+/* System starts uninitialized */
 
 u8                          acpi_gbl_shutdown = TRUE;
 
@@ -168,7 +167,7 @@
  *    during the initialization sequence.
  */
 
-const predefined_names      acpi_gbl_pre_defined_names[] =
+const acpi_predefined_names     acpi_gbl_pre_defined_names[] =
 { {"_GPE",    INTERNAL_TYPE_DEF_ANY},
 	{"_PR_",    INTERNAL_TYPE_DEF_ANY},
 	{"_SB_",    ACPI_TYPE_DEVICE},
@@ -188,44 +187,45 @@
  * and the table is indexed by values of acpi_object_type
  */
 
-const u8                    acpi_gbl_ns_properties[] =
+const u8                        acpi_gbl_ns_properties[] =
 {
-	NSP_NORMAL,                 /* 00 Any              */
-	NSP_NORMAL,                 /* 01 Number           */
-	NSP_NORMAL,                 /* 02 String           */
-	NSP_NORMAL,                 /* 03 Buffer           */
-	NSP_LOCAL,                  /* 04 Package          */
-	NSP_NORMAL,                 /* 05 Field_unit       */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 06 Device           */
-	NSP_LOCAL,                  /* 07 Acpi_event       */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 08 Method           */
-	NSP_LOCAL,                  /* 09 Mutex            */
-	NSP_LOCAL,                  /* 10 Region           */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 11 Power            */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 12 Processor        */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 13 Thermal          */
-	NSP_NORMAL,                 /* 14 Buffer_field     */
-	NSP_NORMAL,                 /* 15 Ddb_handle       */
-	NSP_NORMAL,                 /* 16 Debug Object     */
-	NSP_NORMAL,                 /* 17 Def_field        */
-	NSP_NORMAL,                 /* 18 Bank_field       */
-	NSP_NORMAL,                 /* 19 Index_field      */
-	NSP_NORMAL,                 /* 20 Reference        */
-	NSP_NORMAL,                 /* 21 Alias            */
-	NSP_NORMAL,                 /* 22 Notify           */
-	NSP_NORMAL,                 /* 23 Address Handler  */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 24 Resource Desc    */
-	NSP_NEWSCOPE | NSP_LOCAL,   /* 25 Resource Field   */
-	NSP_NORMAL,                 /* 26 Def_field_defn   */
-	NSP_NORMAL,                 /* 27 Bank_field_defn  */
-	NSP_NORMAL,                 /* 28 Index_field_defn */
-	NSP_NORMAL,                 /* 29 If               */
-	NSP_NORMAL,                 /* 30 Else             */
-	NSP_NORMAL,                 /* 31 While            */
-	NSP_NEWSCOPE,               /* 32 Scope            */
-	NSP_LOCAL,                  /* 33 Def_any          */
-	NSP_NORMAL,                 /* 34 Extra            */
-	NSP_NORMAL                  /* 35 Invalid          */
+	ACPI_NS_NORMAL,                     /* 00 Any              */
+	ACPI_NS_NORMAL,                     /* 01 Number           */
+	ACPI_NS_NORMAL,                     /* 02 String           */
+	ACPI_NS_NORMAL,                     /* 03 Buffer           */
+	ACPI_NS_LOCAL,                      /* 04 Package          */
+	ACPI_NS_NORMAL,                     /* 05 Field_unit       */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 06 Device           */
+	ACPI_NS_LOCAL,                      /* 07 Acpi_event       */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 08 Method           */
+	ACPI_NS_LOCAL,                      /* 09 Mutex            */
+	ACPI_NS_LOCAL,                      /* 10 Region           */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 11 Power            */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 12 Processor        */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 13 Thermal          */
+	ACPI_NS_NORMAL,                     /* 14 Buffer_field     */
+	ACPI_NS_NORMAL,                     /* 15 Ddb_handle       */
+	ACPI_NS_NORMAL,                     /* 16 Debug Object     */
+	ACPI_NS_NORMAL,                     /* 17 Def_field        */
+	ACPI_NS_NORMAL,                     /* 18 Bank_field       */
+	ACPI_NS_NORMAL,                     /* 19 Index_field      */
+	ACPI_NS_NORMAL,                     /* 20 Reference        */
+	ACPI_NS_NORMAL,                     /* 21 Alias            */
+	ACPI_NS_NORMAL,                     /* 22 Notify           */
+	ACPI_NS_NORMAL,                     /* 23 Address Handler  */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 24 Resource Desc    */
+	ACPI_NS_NEWSCOPE | ACPI_NS_LOCAL,   /* 25 Resource Field   */
+	ACPI_NS_NORMAL,                     /* 26 Def_field_defn   */
+	ACPI_NS_NORMAL,                     /* 27 Bank_field_defn  */
+	ACPI_NS_NORMAL,                     /* 28 Index_field_defn */
+	ACPI_NS_NORMAL,                     /* 29 If               */
+	ACPI_NS_NORMAL,                     /* 30 Else             */
+	ACPI_NS_NORMAL,                     /* 31 While            */
+	ACPI_NS_NEWSCOPE,                   /* 32 Scope            */
+	ACPI_NS_LOCAL,                      /* 33 Def_any          */
+	ACPI_NS_NORMAL,                     /* 34 Extra            */
+	ACPI_NS_NORMAL,                     /* 35 Data             */
+	ACPI_NS_NORMAL                      /* 36 Invalid          */
 };
 
 
@@ -261,12 +261,15 @@
 
 /******************************************************************************
  *
- * Table globals
+ * Table name globals
  *
  * NOTE: This table includes ONLY the ACPI tables that the subsystem consumes.
  * it is NOT an exhaustive list of all possible ACPI tables.  All ACPI tables
  * that are not used by the subsystem are simply ignored.
  *
+ * Do NOT add any table to this list that is not consumed directly by this
+ * subsystem.
+ *
  ******************************************************************************/
 
 
@@ -275,18 +278,147 @@
 
 ACPI_TABLE_SUPPORT          acpi_gbl_acpi_table_data[NUM_ACPI_TABLES] =
 {
-	/***********    Name,    Signature,  Signature size,    How many allowed?,   Supported?  Global typed pointer */
+	/***********    Name,   Signature, Global typed pointer     Signature size,      How many allowed?,    Contains valid AML? */
+
+	/* RSDP 0 */ {RSDP_NAME, RSDP_SIG, NULL,                    sizeof (RSDP_SIG)-1, ACPI_TABLE_SINGLE},
+	/* DSDT 1 */ {DSDT_SIG,  DSDT_SIG, (void **) &acpi_gbl_DSDT, sizeof (DSDT_SIG)-1, ACPI_TABLE_SINGLE  | ACPI_TABLE_EXECUTABLE},
+	/* FADT 2 */ {FADT_SIG,  FADT_SIG, (void **) &acpi_gbl_FADT, sizeof (FADT_SIG)-1, ACPI_TABLE_SINGLE},
+	/* FACS 3 */ {FACS_SIG,  FACS_SIG, (void **) &acpi_gbl_FACS, sizeof (FACS_SIG)-1, ACPI_TABLE_SINGLE},
+	/* PSDT 4 */ {PSDT_SIG,  PSDT_SIG, NULL,                    sizeof (PSDT_SIG)-1, ACPI_TABLE_MULTIPLE | ACPI_TABLE_EXECUTABLE},
+	/* SSDT 5 */ {SSDT_SIG,  SSDT_SIG, NULL,                    sizeof (SSDT_SIG)-1, ACPI_TABLE_MULTIPLE | ACPI_TABLE_EXECUTABLE},
+	/* XSDT 6 */ {XSDT_SIG,  XSDT_SIG, NULL,                    sizeof (RSDT_SIG)-1, ACPI_TABLE_SINGLE},
+};
+
+
+/******************************************************************************
+ *
+ * Event and Hardware globals
+ *
+ ******************************************************************************/
+
+ACPI_BIT_REGISTER_INFO      acpi_gbl_bit_register_info[ACPI_NUM_BITREG] =
+{
+	/* Name                                     Parent Register             Register Bit Position                   Register Bit Mask       */
+
+	/* ACPI_BITREG_TIMER_STATUS         */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_TIMER_STATUS,          ACPI_BITMASK_TIMER_STATUS},
+	/* ACPI_BITREG_BUS_MASTER_STATUS    */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_BUS_MASTER_STATUS,     ACPI_BITMASK_BUS_MASTER_STATUS},
+	/* ACPI_BITREG_GLOBAL_LOCK_STATUS   */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_GLOBAL_LOCK_STATUS,    ACPI_BITMASK_GLOBAL_LOCK_STATUS},
+	/* ACPI_BITREG_POWER_BUTTON_STATUS  */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_POWER_BUTTON_STATUS,   ACPI_BITMASK_POWER_BUTTON_STATUS},
+	/* ACPI_BITREG_SLEEP_BUTTON_STATUS  */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_SLEEP_BUTTON_STATUS,   ACPI_BITMASK_SLEEP_BUTTON_STATUS},
+	/* ACPI_BITREG_RT_CLOCK_STATUS      */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_RT_CLOCK_STATUS,       ACPI_BITMASK_RT_CLOCK_STATUS},
+	/* ACPI_BITREG_WAKE_STATUS          */   {ACPI_REGISTER_PM1_STATUS,   ACPI_BITPOSITION_WAKE_STATUS,           ACPI_BITMASK_WAKE_STATUS},
+
+	/* ACPI_BITREG_TIMER_ENABLE         */   {ACPI_REGISTER_PM1_ENABLE,   ACPI_BITPOSITION_TIMER_ENABLE,          ACPI_BITMASK_TIMER_ENABLE},
+	/* ACPI_BITREG_GLOBAL_LOCK_ENABLE   */   {ACPI_REGISTER_PM1_ENABLE,   ACPI_BITPOSITION_GLOBAL_LOCK_ENABLE,    ACPI_BITMASK_GLOBAL_LOCK_ENABLE},
+	/* ACPI_BITREG_POWER_BUTTON_ENABLE  */   {ACPI_REGISTER_PM1_ENABLE,   ACPI_BITPOSITION_POWER_BUTTON_ENABLE,   ACPI_BITMASK_POWER_BUTTON_ENABLE},
+	/* ACPI_BITREG_SLEEP_BUTTON_ENABLE  */   {ACPI_REGISTER_PM1_ENABLE,   ACPI_BITPOSITION_SLEEP_BUTTON_ENABLE,   ACPI_BITMASK_SLEEP_BUTTON_ENABLE},
+	/* ACPI_BITREG_RT_CLOCK_ENABLE      */   {ACPI_REGISTER_PM1_ENABLE,   ACPI_BITPOSITION_RT_CLOCK_ENABLE,       ACPI_BITMASK_RT_CLOCK_ENABLE},
+	/* ACPI_BITREG_WAKE_ENABLE          */   {ACPI_REGISTER_PM1_ENABLE,   0,                                      0},
+
+	/* ACPI_BITREG_SCI_ENABLE           */   {ACPI_REGISTER_PM1_CONTROL,  ACPI_BITPOSITION_SCI_ENABLE,            ACPI_BITMASK_SCI_ENABLE},
+	/* ACPI_BITREG_BUS_MASTER_RLD       */   {ACPI_REGISTER_PM1_CONTROL,  ACPI_BITPOSITION_BUS_MASTER_RLD,        ACPI_BITMASK_BUS_MASTER_RLD},
+	/* ACPI_BITREG_GLOBAL_LOCK_RELEASE  */   {ACPI_REGISTER_PM1_CONTROL,  ACPI_BITPOSITION_GLOBAL_LOCK_RELEASE,   ACPI_BITMASK_GLOBAL_LOCK_RELEASE},
+	/* ACPI_BITREG_SLEEP_TYPE_A         */   {ACPI_REGISTER_PM1_CONTROL,  ACPI_BITPOSITION_SLEEP_TYPE_X,          ACPI_BITMASK_SLEEP_TYPE_X},
+	/* ACPI_BITREG_SLEEP_TYPE_B         */   {ACPI_REGISTER_PM1_CONTROL,  ACPI_BITPOSITION_SLEEP_TYPE_X,          ACPI_BITMASK_SLEEP_TYPE_X},
+	/* ACPI_BITREG_SLEEP_ENABLE         */   {ACPI_REGISTER_PM1_CONTROL,  ACPI_BITPOSITION_SLEEP_ENABLE,          ACPI_BITMASK_SLEEP_ENABLE},
+
+	/* ACPI_BITREG_ARB_DIS              */   {ACPI_REGISTER_PM2_CONTROL,  ACPI_BITPOSITION_ARB_DISABLE,           ACPI_BITMASK_ARB_DISABLE}
+};
+
+
+acpi_fixed_event_info       acpi_gbl_fixed_event_info[ACPI_NUM_FIXED_EVENTS] =
+{
+	/* ACPI_EVENT_PMTIMER       */  {ACPI_BITREG_TIMER_STATUS,          ACPI_BITREG_TIMER_ENABLE,        ACPI_BITMASK_TIMER_STATUS,          ACPI_BITMASK_TIMER_ENABLE},
+	/* ACPI_EVENT_GLOBAL        */  {ACPI_BITREG_GLOBAL_LOCK_STATUS,    ACPI_BITREG_GLOBAL_LOCK_ENABLE,  ACPI_BITMASK_GLOBAL_LOCK_STATUS,    ACPI_BITMASK_GLOBAL_LOCK_ENABLE},
+	/* ACPI_EVENT_POWER_BUTTON  */  {ACPI_BITREG_POWER_BUTTON_STATUS,   ACPI_BITREG_POWER_BUTTON_ENABLE, ACPI_BITMASK_POWER_BUTTON_STATUS,   ACPI_BITMASK_POWER_BUTTON_ENABLE},
+	/* ACPI_EVENT_SLEEP_BUTTON  */  {ACPI_BITREG_SLEEP_BUTTON_STATUS,   ACPI_BITREG_SLEEP_BUTTON_ENABLE, ACPI_BITMASK_SLEEP_BUTTON_STATUS,   ACPI_BITMASK_SLEEP_BUTTON_ENABLE},
+	/* ACPI_EVENT_RTC           */  {ACPI_BITREG_RT_CLOCK_STATUS,       ACPI_BITREG_RT_CLOCK_ENABLE,     0,                                  0},
+};
+
+/*****************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_get_region_name
+ *
+ * PARAMETERS:  None.
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Translate a Space ID into a name string (Debug only)
+ *
+ ****************************************************************************/
+
+/* Region type decoding */
+
+const NATIVE_CHAR *acpi_gbl_region_types[ACPI_NUM_PREDEFINED_REGIONS] =
+{
+	"System_memory",
+	"System_iO",
+	"PCIConfig",
+	"Embedded_control",
+	"SMBus",
+	"CMOS",
+	"PCIBar_target",
+	"Data_table",
+};
+
+
+NATIVE_CHAR *
+acpi_ut_get_region_name (
+	u8                      space_id)
+{
+
+	if (space_id >= ACPI_USER_REGION_BEGIN)
+	{
+		return ("User_defined_region");
+	}
+
+	else if (space_id >= ACPI_NUM_PREDEFINED_REGIONS)
+	{
+		return ("Invalid_space_iD");
+	}
+
+	return ((NATIVE_CHAR *) acpi_gbl_region_types[space_id]);
+}
 
-	/* RSDP 0 */ {RSDP_NAME, RSDP_SIG, sizeof (RSDP_SIG)-1, ACPI_TABLE_SINGLE,   AE_OK,      NULL},
-	/* DSDT 1 */ {DSDT_SIG,  DSDT_SIG, sizeof (DSDT_SIG)-1, ACPI_TABLE_SINGLE,   AE_OK,      (void **) &acpi_gbl_DSDT},
-	/* FADT 2 */ {FADT_SIG,  FADT_SIG, sizeof (FADT_SIG)-1, ACPI_TABLE_SINGLE,   AE_OK,      (void **) &acpi_gbl_FADT},
-	/* FACS 3 */ {FACS_SIG,  FACS_SIG, sizeof (FACS_SIG)-1, ACPI_TABLE_SINGLE,   AE_OK,      (void **) &acpi_gbl_FACS},
-	/* PSDT 4 */ {PSDT_SIG,  PSDT_SIG, sizeof (PSDT_SIG)-1, ACPI_TABLE_MULTIPLE, AE_OK,      NULL},
-	/* SSDT 5 */ {SSDT_SIG,  SSDT_SIG, sizeof (SSDT_SIG)-1, ACPI_TABLE_MULTIPLE, AE_OK,      NULL},
-	/* XSDT 6 */ {XSDT_SIG,  XSDT_SIG, sizeof (RSDT_SIG)-1, ACPI_TABLE_SINGLE,   AE_OK,      NULL},
+
+/*****************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_get_event_name
+ *
+ * PARAMETERS:  None.
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Translate a Event ID into a name string (Debug only)
+ *
+ ****************************************************************************/
+
+/* Event type decoding */
+
+const NATIVE_CHAR *acpi_gbl_event_types[ACPI_NUM_FIXED_EVENTS] =
+{
+	"PM_Timer",
+	"Global_lock",
+	"Power_button",
+	"Sleep_button",
+	"Real_time_clock",
 };
 
 
+NATIVE_CHAR *
+acpi_ut_get_event_name (
+	u32                     event_id)
+{
+
+	if (event_id > ACPI_EVENT_MAX)
+	{
+		return ("Invalid_event_iD");
+	}
+
+	return ((NATIVE_CHAR *) acpi_gbl_event_types[event_id]);
+}
+
+
 #ifdef ACPI_DEBUG
 
 /*
@@ -321,6 +453,18 @@
 }
 
 
+/*****************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_get_type_name
+ *
+ * PARAMETERS:  None.
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Translate a Type ID into a name string (Debug only)
+ *
+ ****************************************************************************/
+
 /*
  * Elements of Acpi_gbl_Ns_type_names below must match
  * one-to-one with values of acpi_object_type
@@ -370,25 +514,14 @@
 	/* 32 */ "Scope",
 	/* 33 */ "Def_any",
 	/* 34 */ "Extra",
-	/* 35 */ "Invalid"
+	/* 35 */ "Data",
+	/* 36 */ "Invalid"
 };
 
 
-/*****************************************************************************
- *
- * FUNCTION:    Acpi_ut_get_type_name
- *
- * PARAMETERS:  None.
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Translate a Type ID into a name string (Debug only)
- *
- ****************************************************************************/
-
 NATIVE_CHAR *
 acpi_ut_get_type_name (
-	u32                     type)
+	acpi_object_type        type)
 {
 
 	if (type > INTERNAL_TYPE_INVALID)
@@ -400,51 +533,6 @@
 }
 
 
-/* Region type decoding */
-
-const NATIVE_CHAR *acpi_gbl_region_types[NUM_REGION_TYPES] =
-{
-	"System_memory",
-	"System_iO",
-	"PCIConfig",
-	"Embedded_control",
-	"SMBus",
-	"CMOS",
-	"PCIBar_target",
-};
-
-
-/*****************************************************************************
- *
- * FUNCTION:    Acpi_ut_get_region_name
- *
- * PARAMETERS:  None.
- *
- * RETURN:      Status
- *
- * DESCRIPTION: Translate a Space ID into a name string (Debug only)
- *
- ****************************************************************************/
-
-NATIVE_CHAR *
-acpi_ut_get_region_name (
-	u8                      space_id)
-{
-
-	if (space_id >= USER_REGION_BEGIN)
-	{
-		return ("User_defined_region");
-	}
-
-	else if (space_id >= NUM_REGION_TYPES)
-	{
-		return ("Invalid_space_iD");
-	}
-
-	return ((NATIVE_CHAR *) acpi_gbl_region_types[space_id]);
-}
-
-
 /* Data used in keeping track of fields */
 
 const NATIVE_CHAR *acpi_gbl_FEnames[NUM_FIELD_NAMES] =
@@ -474,9 +562,8 @@
 	"Byte_acc",
 	"Word_acc",
 	"DWord_acc",
-	"Block_acc",
-	"SMBSend_recv_acc",
-	"SMBQuick_acc"
+	"QWord_acc",
+	"Buffer_acc",
 };
 
 
@@ -506,7 +593,7 @@
 
 u8
 acpi_ut_valid_object_type (
-	u32                     type)
+	acpi_object_type        type)
 {
 
 	if (type > ACPI_TYPE_MAX)
@@ -539,40 +626,41 @@
 	acpi_owner_id           owner_id = 0xFFFF;
 
 
-	FUNCTION_TRACE ("Ut_allocate_owner_id");
+	ACPI_FUNCTION_TRACE ("Ut_allocate_owner_id");
 
 
-	acpi_ut_acquire_mutex (ACPI_MTX_CACHES);
+	if (ACPI_FAILURE (acpi_ut_acquire_mutex (ACPI_MTX_CACHES)))
+	{
+		return (0);
+	}
 
 	switch (id_type)
 	{
-	case OWNER_TYPE_TABLE:
+	case ACPI_OWNER_TYPE_TABLE:
 
 		owner_id = acpi_gbl_next_table_owner_id;
 		acpi_gbl_next_table_owner_id++;
 
-		if (acpi_gbl_next_table_owner_id == FIRST_METHOD_ID)
+		if (acpi_gbl_next_table_owner_id == ACPI_FIRST_METHOD_ID)
 		{
-			acpi_gbl_next_table_owner_id = FIRST_TABLE_ID;
+			acpi_gbl_next_table_owner_id = ACPI_FIRST_TABLE_ID;
 		}
 		break;
 
 
-	case OWNER_TYPE_METHOD:
+	case ACPI_OWNER_TYPE_METHOD:
 
 		owner_id = acpi_gbl_next_method_owner_id;
 		acpi_gbl_next_method_owner_id++;
 
-		if (acpi_gbl_next_method_owner_id == FIRST_TABLE_ID)
+		if (acpi_gbl_next_method_owner_id == ACPI_FIRST_TABLE_ID)
 		{
-			acpi_gbl_next_method_owner_id = FIRST_METHOD_ID;
+			acpi_gbl_next_method_owner_id = ACPI_FIRST_METHOD_ID;
 		}
 		break;
 	}
 
-
-	acpi_ut_release_mutex (ACPI_MTX_CACHES);
-
+	(void) acpi_ut_release_mutex (ACPI_MTX_CACHES);
 	return_VALUE (owner_id);
 }
 
@@ -595,17 +683,17 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE ("Ut_init_globals");
+	ACPI_FUNCTION_TRACE ("Ut_init_globals");
 
 	/* Memory allocation and cache lists */
 
-	MEMSET (acpi_gbl_memory_lists, 0, sizeof (ACPI_MEMORY_LIST) * ACPI_NUM_MEM_LISTS);
+	ACPI_MEMSET (acpi_gbl_memory_lists, 0, sizeof (ACPI_MEMORY_LIST) * ACPI_NUM_MEM_LISTS);
 
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_STATE].link_offset      = (u16) (NATIVE_UINT) &(((acpi_generic_state *) NULL)->common.next);
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_PSNODE].link_offset     = (u16) (NATIVE_UINT) &(((acpi_parse_object *) NULL)->next);
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_PSNODE_EXT].link_offset = (u16) (NATIVE_UINT) &(((acpi_parse2_object *) NULL)->next);
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_OPERAND].link_offset    = (u16) (NATIVE_UINT) &(((acpi_operand_object *) NULL)->cache.next);
-	acpi_gbl_memory_lists[ACPI_MEM_LIST_WALK].link_offset       = (u16) (NATIVE_UINT) &(((acpi_walk_state *) NULL)->next);
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_STATE].link_offset      = (u16) ACPI_PTR_DIFF (&(((acpi_generic_state *) NULL)->common.next), NULL);
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_PSNODE].link_offset     = (u16) ACPI_PTR_DIFF (&(((acpi_parse_object *) NULL)->next), NULL);
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_PSNODE_EXT].link_offset = (u16) ACPI_PTR_DIFF (&(((acpi_parse2_object *) NULL)->next), NULL);
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_OPERAND].link_offset    = (u16) ACPI_PTR_DIFF (&(((acpi_operand_object *) NULL)->cache.next), NULL);
+	acpi_gbl_memory_lists[ACPI_MEM_LIST_WALK].link_offset       = (u16) ACPI_PTR_DIFF (&(((acpi_walk_state *) NULL)->next), NULL);
 
 	acpi_gbl_memory_lists[ACPI_MEM_LIST_NSNODE].object_size     = sizeof (acpi_namespace_node);
 	acpi_gbl_memory_lists[ACPI_MEM_LIST_STATE].object_size      = sizeof (acpi_generic_state);
@@ -640,15 +728,6 @@
 		acpi_gbl_acpi_tables[i].count       = 0;
 	}
 
-
-	/* Address Space handler array */
-
-	for (i = 0; i < ACPI_NUM_ADDRESS_SPACES; i++)
-	{
-		acpi_gbl_address_spaces[i].handler  = NULL;
-		acpi_gbl_address_spaces[i].context  = NULL;
-	}
-
 	/* Mutex locked flags */
 
 	for (i = 0; i < NUM_MTX; i++)
@@ -675,11 +754,10 @@
 
 	acpi_gbl_global_lock_acquired       = FALSE;
 	acpi_gbl_global_lock_thread_count   = 0;
+	acpi_gbl_global_lock_handle         = 0;
 
 	/* Miscellaneous variables */
 
-	acpi_gbl_system_flags               = 0;
-	acpi_gbl_startup_flags              = 0;
 	acpi_gbl_rsdp_original_location     = 0;
 	acpi_gbl_cm_single_step             = FALSE;
 	acpi_gbl_db_terminate_threads       = FALSE;
@@ -687,24 +765,22 @@
 	acpi_gbl_ns_lookup_count            = 0;
 	acpi_gbl_ps_find_count              = 0;
 	acpi_gbl_acpi_hardware_present      = TRUE;
-	acpi_gbl_next_table_owner_id        = FIRST_TABLE_ID;
-	acpi_gbl_next_method_owner_id       = FIRST_METHOD_ID;
+	acpi_gbl_next_table_owner_id        = ACPI_FIRST_TABLE_ID;
+	acpi_gbl_next_method_owner_id       = ACPI_FIRST_METHOD_ID;
 	acpi_gbl_debugger_configuration     = DEBUGGER_THREADING;
+	acpi_gbl_db_output_flags            = ACPI_DB_CONSOLE_OUTPUT;
 
 	/* Hardware oriented */
 
-	acpi_gbl_gpe0enable_register_save   = NULL;
-	acpi_gbl_gpe1_enable_register_save  = NULL;
-	acpi_gbl_original_mode              = SYS_MODE_UNKNOWN;   /*  original ACPI/legacy mode   */
-	acpi_gbl_gpe_registers              = NULL;
-	acpi_gbl_gpe_info                   = NULL;
+	acpi_gbl_gpe_register_info          = NULL;
+	acpi_gbl_gpe_number_info            = NULL;
 
 	/* Namespace */
 
 	acpi_gbl_root_node                  = NULL;
 
 	acpi_gbl_root_node_struct.name      = ACPI_ROOT_NAME;
-	acpi_gbl_root_node_struct.data_type = ACPI_DESC_TYPE_NAMED;
+	acpi_gbl_root_node_struct.descriptor = ACPI_DESC_TYPE_NAMED;
 	acpi_gbl_root_node_struct.type      = ACPI_TYPE_ANY;
 	acpi_gbl_root_node_struct.child     = NULL;
 	acpi_gbl_root_node_struct.peer      = NULL;
diff -Nru a/drivers/acpi/utilities/utinit.c b/drivers/acpi/utilities/utinit.c
--- a/drivers/acpi/utilities/utinit.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/utilities/utinit.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utinit - Common ACPI subsystem initialization
- *              $Revision: 102 $
+ *              $Revision: 109 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,15 +28,9 @@
 #include "achware.h"
 #include "acnamesp.h"
 #include "acevents.h"
-#include "acparser.h"
-#include "acdispat.h"
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utinit")
-
-
-#define ACPI_OFFSET(d,o)    ((u32) &(((d *)0)->o))
-#define ACPI_FADT_OFFSET(o) ACPI_OFFSET (FADT_DESCRIPTOR, o)
+	 ACPI_MODULE_NAME    ("utinit")
 
 
 /*******************************************************************************
@@ -54,19 +48,16 @@
  *
  ******************************************************************************/
 
-static acpi_status
+static void
 acpi_ut_fadt_register_error (
 	NATIVE_CHAR             *register_name,
 	u32                     value,
-	u32                     offset)
+	ACPI_SIZE               offset)
 {
 
-	REPORT_ERROR (
+	ACPI_REPORT_WARNING (
 		("Invalid FADT value %s=%lX at offset %lX FADT=%p\n",
 		register_name, value, offset, acpi_gbl_FADT));
-
-
-	return (AE_BAD_VALUE);
 }
 
 
@@ -86,69 +77,67 @@
 acpi_ut_validate_fadt (
 	void)
 {
-	acpi_status                 status = AE_OK;
-
 
 	/*
 	 * Verify Fixed ACPI Description Table fields,
 	 * but don't abort on any problems, just display error
 	 */
 	if (acpi_gbl_FADT->pm1_evt_len < 4) {
-		status = acpi_ut_fadt_register_error ("PM1_EVT_LEN",
+		acpi_ut_fadt_register_error ("PM1_EVT_LEN",
 				  (u32) acpi_gbl_FADT->pm1_evt_len,
 				  ACPI_FADT_OFFSET (pm1_evt_len));
 	}
 
 	if (!acpi_gbl_FADT->pm1_cnt_len) {
-		status = acpi_ut_fadt_register_error ("PM1_CNT_LEN", 0,
+		acpi_ut_fadt_register_error ("PM1_CNT_LEN", 0,
 				  ACPI_FADT_OFFSET (pm1_cnt_len));
 	}
 
 	if (!ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xpm1a_evt_blk.address)) {
-		status = acpi_ut_fadt_register_error ("X_PM1a_EVT_BLK", 0,
+		acpi_ut_fadt_register_error ("X_PM1a_EVT_BLK", 0,
 				  ACPI_FADT_OFFSET (Xpm1a_evt_blk.address));
 	}
 
 	if (!ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xpm1a_cnt_blk.address)) {
-		status = acpi_ut_fadt_register_error ("X_PM1a_CNT_BLK", 0,
+		acpi_ut_fadt_register_error ("X_PM1a_CNT_BLK", 0,
 				  ACPI_FADT_OFFSET (Xpm1a_cnt_blk.address));
 	}
 
 	if (!ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xpm_tmr_blk.address)) {
-		status = acpi_ut_fadt_register_error ("X_PM_TMR_BLK", 0,
+		acpi_ut_fadt_register_error ("X_PM_TMR_BLK", 0,
 				  ACPI_FADT_OFFSET (Xpm_tmr_blk.address));
 	}
 
 	if ((ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xpm2_cnt_blk.address) &&
 		!acpi_gbl_FADT->pm2_cnt_len)) {
-		status = acpi_ut_fadt_register_error ("PM2_CNT_LEN",
+		acpi_ut_fadt_register_error ("PM2_CNT_LEN",
 				  (u32) acpi_gbl_FADT->pm2_cnt_len,
 				  ACPI_FADT_OFFSET (pm2_cnt_len));
 	}
 
 	if (acpi_gbl_FADT->pm_tm_len < 4) {
-		status = acpi_ut_fadt_register_error ("PM_TM_LEN",
+		acpi_ut_fadt_register_error ("PM_TM_LEN",
 				  (u32) acpi_gbl_FADT->pm_tm_len,
 				  ACPI_FADT_OFFSET (pm_tm_len));
 	}
 
-	/* length of GPE blocks must be a multiple of 2 */
+	/* Length of GPE blocks must be a multiple of 2 */
 
-	if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xgpe0blk.address) &&
-		(acpi_gbl_FADT->gpe0blk_len & 1)) {
-		status = acpi_ut_fadt_register_error ("(x)GPE0_BLK_LEN",
-				  (u32) acpi_gbl_FADT->gpe0blk_len,
-				  ACPI_FADT_OFFSET (gpe0blk_len));
+	if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xgpe0_blk.address) &&
+		(acpi_gbl_FADT->gpe0_blk_len & 1)) {
+		acpi_ut_fadt_register_error ("(x)GPE0_BLK_LEN",
+				  (u32) acpi_gbl_FADT->gpe0_blk_len,
+				  ACPI_FADT_OFFSET (gpe0_blk_len));
 	}
 
 	if (ACPI_VALID_ADDRESS (acpi_gbl_FADT->Xgpe1_blk.address) &&
 		(acpi_gbl_FADT->gpe1_blk_len & 1)) {
-		status = acpi_ut_fadt_register_error ("(x)GPE1_BLK_LEN",
+		acpi_ut_fadt_register_error ("(x)GPE1_BLK_LEN",
 				  (u32) acpi_gbl_FADT->gpe1_blk_len,
 				  ACPI_FADT_OFFSET (gpe1_blk_len));
 	}
 
-	return (status);
+	return (AE_OK);
 }
 
 
@@ -168,19 +157,12 @@
 acpi_ut_terminate (void)
 {
 
-	FUNCTION_TRACE ("Ut_terminate");
+	ACPI_FUNCTION_TRACE ("Ut_terminate");
 
 
 	/* Free global tables, etc. */
 
-	if (acpi_gbl_gpe0enable_register_save) {
-		ACPI_MEM_FREE (acpi_gbl_gpe0enable_register_save);
-	}
-
-	if (acpi_gbl_gpe1_enable_register_save) {
-		ACPI_MEM_FREE (acpi_gbl_gpe1_enable_register_save);
-	}
-
+	/* Nothing to do at this time */
 
 	return_VOID;
 }
@@ -203,7 +185,7 @@
 acpi_ut_subsystem_shutdown (void)
 {
 
-	FUNCTION_TRACE ("Ut_subsystem_shutdown");
+	ACPI_FUNCTION_TRACE ("Ut_subsystem_shutdown");
 
 	/* Just exit if subsystem is already shutdown */
 
@@ -217,7 +199,6 @@
 	acpi_gbl_shutdown = TRUE;
 	ACPI_DEBUG_PRINT ((ACPI_DB_INFO, "Shutting down ACPI Subsystem...\n"));
 
-
 	/* Close the Namespace */
 
 	acpi_ns_terminate ();
@@ -230,17 +211,9 @@
 
 	acpi_ut_terminate ();
 
-	/* Flush the local cache(s) */
-
-	acpi_ut_delete_generic_state_cache ();
-	acpi_ut_delete_object_cache ();
-	acpi_ds_delete_walk_state_cache ();
-
-	/* Close the Parser */
-
-	/* TBD: [Restructure] Acpi_ps_terminate () */
+	/* Purge the local caches */
 
-	acpi_ps_delete_parse_cache ();
+	acpi_purge_cached_objects ();
 
 	/* Debug only - display leftover memory allocation, if any */
 
diff -Nru a/drivers/acpi/utilities/utmath.c b/drivers/acpi/utilities/utmath.c
--- a/drivers/acpi/utilities/utmath.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/acpi/utilities/utmath.c	Fri Mar 15 17:51:04 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: utmath - Integer math support routines
- *              $Revision: 7 $
+ *              $Revision: 10 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -28,7 +28,7 @@
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utmath")
+	 ACPI_MODULE_NAME    ("utmath")
 
 /*
  * Support for double-precision integer divide.  This code is included here
@@ -66,14 +66,14 @@
 	u32                     remainder32;
 
 
-	FUNCTION_TRACE ("Ut_short_divide");
+	ACPI_FUNCTION_TRACE ("Ut_short_divide");
 
 	dividend.full = *in_dividend;
 
 	/* Always check for a zero divisor */
 
 	if (divisor == 0) {
-		REPORT_ERROR (("Acpi_ut_short_divide: Divide by zero\n"));
+		ACPI_REPORT_ERROR (("Acpi_ut_short_divide: Divide by zero\n"));
 		return_ACPI_STATUS (AE_AML_DIVIDE_BY_ZERO);
 	}
 
@@ -132,13 +132,13 @@
 	uint64_overlay          partial3;
 
 
-	FUNCTION_TRACE ("Ut_divide");
+	ACPI_FUNCTION_TRACE ("Ut_divide");
 
 
 	/* Always check for a zero divisor */
 
 	if (*in_divisor == 0) {
-		REPORT_ERROR (("Acpi_ut_divide: Divide by zero\n"));
+		ACPI_REPORT_ERROR (("Acpi_ut_divide: Divide by zero\n"));
 		return_ACPI_STATUS (AE_AML_DIVIDE_BY_ZERO);
 	}
 
@@ -257,13 +257,13 @@
 	u32                     *out_remainder)
 {
 
-	FUNCTION_TRACE ("Ut_short_divide");
+	ACPI_FUNCTION_TRACE ("Ut_short_divide");
 
 
 	/* Always check for a zero divisor */
 
 	if (divisor == 0) {
-		REPORT_ERROR (("Acpi_ut_short_divide: Divide by zero\n"));
+		ACPI_REPORT_ERROR (("Acpi_ut_short_divide: Divide by zero\n"));
 		return_ACPI_STATUS (AE_AML_DIVIDE_BY_ZERO);
 	}
 
@@ -286,13 +286,13 @@
 	acpi_integer            *out_quotient,
 	acpi_integer            *out_remainder)
 {
-	FUNCTION_TRACE ("Ut_divide");
+	ACPI_FUNCTION_TRACE ("Ut_divide");
 
 
 	/* Always check for a zero divisor */
 
 	if (*in_divisor == 0) {
-		REPORT_ERROR (("Acpi_ut_divide: Divide by zero\n"));
+		ACPI_REPORT_ERROR (("Acpi_ut_divide: Divide by zero\n"));
 		return_ACPI_STATUS (AE_AML_DIVIDE_BY_ZERO);
 	}
 
diff -Nru a/drivers/acpi/utilities/utmisc.c b/drivers/acpi/utilities/utmisc.c
--- a/drivers/acpi/utilities/utmisc.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/utilities/utmisc.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /*******************************************************************************
  *
  * Module Name: utmisc - common utility procedures
- *              $Revision: 52 $
+ *              $Revision: 67 $
  *
  ******************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -34,7 +34,50 @@
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utmisc")
+	 ACPI_MODULE_NAME    ("utmisc")
+
+
+#ifdef ACPI_DEBUG
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_display_init_pathname
+ *
+ * PARAMETERS:  Obj_handle          - Handle whose pathname will be displayed
+ *              Path                - Additional path string to be appended
+ *
+ * RETURN:      acpi_status
+ *
+ * DESCRIPTION: Display full pathnbame of an object, DEBUG ONLY
+ *
+ ******************************************************************************/
+
+void
+acpi_ut_display_init_pathname (
+	acpi_handle             obj_handle,
+	char                    *path)
+{
+	acpi_status             status;
+	acpi_buffer             buffer;
+
+
+	ACPI_FUNCTION_NAME ("Ut_display_init_pathname");
+
+
+	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
+
+	status = acpi_ns_handle_to_pathname (obj_handle, &buffer);
+	if (ACPI_SUCCESS (status)) {
+		if (path) {
+			ACPI_DEBUG_PRINT ((ACPI_DB_INIT, "%s.%s\n", (char *) buffer.pointer, path));
+		}
+		else {
+			ACPI_DEBUG_PRINT ((ACPI_DB_INIT, "%s\n", (char *) buffer.pointer));
+		}
+
+		ACPI_MEM_FREE (buffer.pointer);
+	}
+}
+#endif
 
 
 /*******************************************************************************
@@ -60,7 +103,7 @@
 	u32                     i;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	for (i = 0; i < ACPI_NAME_SIZE; i++) {
@@ -92,7 +135,7 @@
 	NATIVE_CHAR             character)
 {
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 	return ((u8)   ((character == '_') ||
 			   (character >= 'A' && character <= 'Z') ||
@@ -119,13 +162,13 @@
 	NATIVE_CHAR             *string;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* Walk entire string, uppercasing the letters */
 
 	for (string = src_string; *string; ) {
-		*string = (char) TOUPPER (*string);
+		*string = (char) ACPI_TOUPPER (*string);
 		string++;
 	}
 
@@ -153,7 +196,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Ut_mutex_initialize");
+	ACPI_FUNCTION_TRACE ("Ut_mutex_initialize");
 
 
 	/*
@@ -189,7 +232,7 @@
 	u32                     i;
 
 
-	FUNCTION_TRACE ("Ut_mutex_terminate");
+	ACPI_FUNCTION_TRACE ("Ut_mutex_terminate");
 
 
 	/*
@@ -222,7 +265,7 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_U32 ("Ut_create_mutex", mutex_id);
+	ACPI_FUNCTION_TRACE_U32 ("Ut_create_mutex", mutex_id);
 
 
 	if (mutex_id > MAX_MTX) {
@@ -260,7 +303,7 @@
 	acpi_status             status;
 
 
-	FUNCTION_TRACE_U32 ("Ut_delete_mutex", mutex_id);
+	ACPI_FUNCTION_TRACE_U32 ("Ut_delete_mutex", mutex_id);
 
 
 	if (mutex_id > MAX_MTX) {
@@ -298,7 +341,7 @@
 	u32                     this_thread_id;
 
 
-	PROC_NAME ("Ut_acquire_mutex");
+	ACPI_FUNCTION_NAME ("Ut_acquire_mutex");
 
 
 	if (mutex_id > MAX_MTX) {
@@ -340,7 +383,6 @@
 
 	status = acpi_os_wait_semaphore (acpi_gbl_acpi_mutex_info[mutex_id].mutex,
 			   1, WAIT_FOREVER);
-
 	if (ACPI_SUCCESS (status)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_MUTEX, "Thread %X acquired Mutex [%s]\n",
 				 this_thread_id, acpi_ut_get_mutex_name (mutex_id)));
@@ -380,7 +422,7 @@
 	u32                     this_thread_id;
 
 
-	PROC_NAME ("Ut_release_mutex");
+	ACPI_FUNCTION_NAME ("Ut_release_mutex");
 
 
 	this_thread_id = acpi_os_get_thread_id ();
@@ -469,7 +511,7 @@
 	acpi_generic_state       *state;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	/* Ignore null objects; these are expected */
@@ -513,7 +555,7 @@
 	acpi_generic_state       *state;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	state = acpi_ut_create_pkg_state (internal_object, external_object, index);
@@ -545,7 +587,7 @@
 	acpi_generic_state      **list_head,
 	acpi_generic_state      *state)
 {
-	FUNCTION_TRACE ("Ut_push_generic_state");
+	ACPI_FUNCTION_TRACE ("Ut_push_generic_state");
 
 
 	/* Push the state object onto the front of the list (stack) */
@@ -576,7 +618,7 @@
 	acpi_generic_state      *state;
 
 
-	FUNCTION_TRACE ("Ut_pop_generic_state");
+	ACPI_FUNCTION_TRACE ("Ut_pop_generic_state");
 
 
 	/* Remove the state object at the head of the list (stack) */
@@ -611,7 +653,7 @@
 	acpi_generic_state      *state;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
 	state = acpi_ut_acquire_from_cache (ACPI_MEM_LIST_STATE);
@@ -628,6 +670,45 @@
 
 /*******************************************************************************
  *
+ * FUNCTION:    Acpi_ut_create_thread_state
+ *
+ * PARAMETERS:  None
+ *
+ * RETURN:      Thread State
+ *
+ * DESCRIPTION: Create a "Thread State" - a flavor of the generic state used
+ *              to track per-thread info during method execution
+ *
+ ******************************************************************************/
+
+ACPI_THREAD_STATE *
+acpi_ut_create_thread_state (
+	void)
+{
+	acpi_generic_state      *state;
+
+
+	ACPI_FUNCTION_TRACE ("Ut_create_thread_state");
+
+
+	/* Create the generic state object */
+
+	state = acpi_ut_create_generic_state ();
+	if (!state) {
+		return_PTR (NULL);
+	}
+
+	/* Init fields specific to the update struct */
+
+	state->common.data_type = ACPI_DESC_TYPE_STATE_THREAD;
+	state->thread.thread_id = acpi_os_get_thread_id ();
+
+	return_PTR ((ACPI_THREAD_STATE *) state);
+}
+
+
+/*******************************************************************************
+ *
  * FUNCTION:    Acpi_ut_create_update_state
  *
  * PARAMETERS:  Object              - Initial Object to be installed in the
@@ -650,14 +731,14 @@
 	acpi_generic_state      *state;
 
 
-	FUNCTION_TRACE_PTR ("Ut_create_update_state", object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_create_update_state", object);
 
 
 	/* Create the generic state object */
 
 	state = acpi_ut_create_generic_state ();
 	if (!state) {
-		return (NULL);
+		return_PTR (NULL);
 	}
 
 	/* Init fields specific to the update struct */
@@ -693,14 +774,14 @@
 	acpi_generic_state      *state;
 
 
-	FUNCTION_TRACE_PTR ("Ut_create_pkg_state", internal_object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_create_pkg_state", internal_object);
 
 
 	/* Create the generic state object */
 
 	state = acpi_ut_create_generic_state ();
 	if (!state) {
-		return (NULL);
+		return_PTR (NULL);
 	}
 
 	/* Init fields specific to the update struct */
@@ -735,21 +816,21 @@
 	acpi_generic_state      *state;
 
 
-	FUNCTION_TRACE ("Ut_create_control_state");
+	ACPI_FUNCTION_TRACE ("Ut_create_control_state");
 
 
 	/* Create the generic state object */
 
 	state = acpi_ut_create_generic_state ();
 	if (!state) {
-		return (NULL);
+		return_PTR (NULL);
 	}
 
 
 	/* Init fields specific to the control struct */
 
 	state->common.data_type = ACPI_DESC_TYPE_STATE_CONTROL;
-	state->common.state     = CONTROL_CONDITIONAL_EXECUTING;
+	state->common.state     = ACPI_CONTROL_CONDITIONAL_EXECUTING;
 
 	return_PTR (state);
 }
@@ -772,7 +853,7 @@
 acpi_ut_delete_generic_state (
 	acpi_generic_state      *state)
 {
-	FUNCTION_TRACE ("Ut_delete_generic_state");
+	ACPI_FUNCTION_TRACE ("Ut_delete_generic_state");
 
 
 	acpi_ut_release_to_cache (ACPI_MEM_LIST_STATE, state);
@@ -797,7 +878,7 @@
 acpi_ut_delete_generic_state_cache (
 	void)
 {
-	FUNCTION_TRACE ("Ut_delete_generic_state_cache");
+	ACPI_FUNCTION_TRACE ("Ut_delete_generic_state_cache");
 
 
 	acpi_ut_delete_generic_cache (ACPI_MEM_LIST_STATE);
@@ -807,100 +888,109 @@
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ut_resolve_package_references
+ * FUNCTION:    Acpi_ut_resolve_reference
  *
- * PARAMETERS:  Obj_desc        - The Package object on which to resolve refs
+ * PARAMETERS:  ACPI_PKG_CALLBACK
  *
- * RETURN:      Status
+ * RETURN:      Status          - the status of the call
  *
- * DESCRIPTION: Walk through a package and turn internal references into values
+ * DESCRIPTION: Resolve a reference object to an actual value
  *
  ******************************************************************************/
 
 acpi_status
-acpi_ut_resolve_package_references (
-	acpi_operand_object     *obj_desc)
+acpi_ut_resolve_reference (
+	u8                      object_type,
+	acpi_operand_object     *source_object,
+	acpi_generic_state      *state,
+	void                    *context)
 {
-	u32                     count;
-	acpi_operand_object     *sub_object;
+	acpi_pkg_info           *info = (acpi_pkg_info *) context;
 
 
-	FUNCTION_TRACE ("Ut_resolve_package_references");
+	switch (object_type) {
+	case ACPI_COPY_TYPE_SIMPLE:
 
+		/*
+		 * Simple object - check for a reference
+		 */
+		if (source_object->common.type == INTERNAL_TYPE_REFERENCE) {
+			switch (source_object->reference.opcode) {
+			case AML_ZERO_OP:
 
-	if (obj_desc->common.type != ACPI_TYPE_PACKAGE) {
-		/* The object must be a package */
+				source_object->common.type = ACPI_TYPE_INTEGER;
+				source_object->integer.value = 0;
+				break;
 
-		REPORT_ERROR (("Must resolve Package Refs on a Package\n"));
-		return_ACPI_STATUS(AE_ERROR);
-	}
+			case AML_ONE_OP:
 
-	/*
-	 * TBD: what about nested packages? */
+				source_object->common.type = ACPI_TYPE_INTEGER;
+				source_object->integer.value = 1;
+				break;
 
-	for (count = 0; count < obj_desc->package.count; count++) {
-		sub_object = obj_desc->package.elements[count];
+			case AML_ONES_OP:
 
-		if (sub_object->common.type == INTERNAL_TYPE_REFERENCE) {
-			if (sub_object->reference.opcode == AML_ZERO_OP) {
-				sub_object->common.type = ACPI_TYPE_INTEGER;
-				sub_object->integer.value = 0;
+				source_object->common.type = ACPI_TYPE_INTEGER;
+				source_object->integer.value = ACPI_INTEGER_MAX;
+				break;
 			}
+		}
+		break;
 
-			else if (sub_object->reference.opcode == AML_ONE_OP) {
-				sub_object->common.type = ACPI_TYPE_INTEGER;
-				sub_object->integer.value = 1;
-			}
 
-			else if (sub_object->reference.opcode == AML_ONES_OP) {
-				sub_object->common.type = ACPI_TYPE_INTEGER;
-				sub_object->integer.value = ACPI_INTEGER_MAX;
-			}
-		}
+	case ACPI_COPY_TYPE_PACKAGE:
+
+		/* Package object - nothing much to do here, let the walk handle it */
+
+		info->num_packages++;
+		state->pkg.this_target_obj = NULL;
+		break;
 	}
 
-	return_ACPI_STATUS(AE_OK);
+	return (AE_OK);
 }
 
-#ifdef ACPI_DEBUG
 
 /*******************************************************************************
  *
- * FUNCTION:    Acpi_ut_display_init_pathname
+ * FUNCTION:    Acpi_ut_resolve_package_references
  *
- * PARAMETERS:  Obj_handle          - Handle whose pathname will be displayed
- *              Path                - Additional path string to be appended
+ * PARAMETERS:  Obj_desc        - The Package object on which to resolve refs
  *
- * RETURN:      acpi_status
+ * RETURN:      Status
  *
- * DESCRIPTION: Display full pathnbame of an object, DEBUG ONLY
+ * DESCRIPTION: Walk through a package and turn internal references into values
  *
  ******************************************************************************/
 
-void
-acpi_ut_display_init_pathname (
-	acpi_handle             obj_handle,
-	char                    *path)
+acpi_status
+acpi_ut_resolve_package_references (
+	acpi_operand_object     *obj_desc)
 {
+	acpi_pkg_info           info;
 	acpi_status             status;
-	u32                     length = 128;
-	char                    buffer[128];
 
 
-	PROC_NAME ("Ut_display_init_pathname");
+	ACPI_FUNCTION_TRACE ("Ut_resolve_package_references");
 
 
-	status = acpi_ns_handle_to_pathname (obj_handle, &length, buffer);
-	if (ACPI_SUCCESS (status)) {
-		if (path) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INIT, "%s.%s\n", buffer, path));
-		}
-		else {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INIT, "%s\n", buffer));
-		}
+	if (obj_desc->common.type != ACPI_TYPE_PACKAGE) {
+		/* The object must be a package */
+
+		ACPI_REPORT_ERROR (("Expecting a Package object\n"));
+		return_ACPI_STATUS (AE_TYPE);
 	}
+
+	info.length      = 0;
+	info.object_space = 0;
+	info.num_packages = 1;
+
+	status = acpi_ut_walk_package_tree (obj_desc, NULL,
+			 acpi_ut_resolve_reference, &info);
+
+	return_ACPI_STATUS (status);
 }
-#endif
+
 
 /*******************************************************************************
  *
@@ -928,7 +1018,7 @@
 	acpi_operand_object     *this_source_obj;
 
 
-	FUNCTION_TRACE ("Ut_walk_package_tree");
+	ACPI_FUNCTION_TRACE ("Ut_walk_package_tree");
 
 
 	state = acpi_ut_create_pkg_state (source_object, target_object, 0);
@@ -942,24 +1032,19 @@
 				  state->pkg.source_object->package.elements[this_index];
 
 		/*
-		 * Check for
+		 * Check for:
 		 * 1) An uninitialized package element.  It is completely
-		 *      legal to declare a package and leave it uninitialized
+		 *    legal to declare a package and leave it uninitialized
 		 * 2) Not an internal object - can be a namespace node instead
 		 * 3) Any type other than a package.  Packages are handled in else
-		 *      case below.
+		 *    case below.
 		 */
 		if ((!this_source_obj) ||
-			(!VALID_DESCRIPTOR_TYPE (
-					this_source_obj, ACPI_DESC_TYPE_INTERNAL)) ||
-			(!IS_THIS_OBJECT_TYPE (
-					this_source_obj, ACPI_TYPE_PACKAGE))) {
-
+			(ACPI_GET_DESCRIPTOR_TYPE (this_source_obj) != ACPI_DESC_TYPE_INTERNAL) ||
+			(this_source_obj->common.type != ACPI_TYPE_PACKAGE)) {
 			status = walk_callback (ACPI_COPY_TYPE_SIMPLE, this_source_obj,
 					 state, context);
 			if (ACPI_FAILURE (status)) {
-				/* TBD: must delete package created up to this point */
-
 				return_ACPI_STATUS (status);
 			}
 
@@ -975,7 +1060,6 @@
 				acpi_ut_delete_generic_state (state);
 				state = acpi_ut_pop_generic_state (&state_list);
 
-
 				/* Finished when there are no more states */
 
 				if (!state) {
@@ -994,32 +1078,23 @@
 				state->pkg.index++;
 			}
 		}
-
 		else {
-			/* This is a sub-object of type package */
+			/* This is a subobject of type package */
 
 			status = walk_callback (ACPI_COPY_TYPE_PACKAGE, this_source_obj,
 					  state, context);
 			if (ACPI_FAILURE (status)) {
-				/* TBD: must delete package created up to this point */
-
 				return_ACPI_STATUS (status);
 			}
 
-
-			/*
-			 * The callback above returned a new target package object.
-			 */
-
 			/*
 			 * Push the current state and create a new one
+			 * The callback above returned a new target package object.
 			 */
 			acpi_ut_push_generic_state (&state_list, state);
 			state = acpi_ut_create_pkg_state (this_source_obj,
 					   state->pkg.this_target_obj, 0);
 			if (!state) {
-				/* TBD: must delete package created up to this point */
-
 				return_ACPI_STATUS (AE_NO_MEMORY);
 			}
 		}
@@ -1027,7 +1102,89 @@
 
 	/* We should never get here */
 
-	return (AE_AML_INTERNAL);
+	return_ACPI_STATUS (AE_AML_INTERNAL);
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_generate_checksum
+ *
+ * PARAMETERS:  Buffer          - Buffer to be scanned
+ *              Length          - number of bytes to examine
+ *
+ * RETURN:      checksum
+ *
+ * DESCRIPTION: Generate a checksum on a raw buffer
+ *
+ ******************************************************************************/
+
+u8
+acpi_ut_generate_checksum (
+	u8                      *buffer,
+	u32                     length)
+{
+	u32                     i;
+	signed char             sum = 0;
+
+	for (i = 0; i < length; i++) {
+		sum = (signed char) (sum + buffer[i]);
+	}
+
+	return ((u8) (0 - sum));
+}
+
+
+/*******************************************************************************
+ *
+ * FUNCTION:    Acpi_ut_get_resource_end_tag
+ *
+ * PARAMETERS:  Obj_desc        - The resource template buffer object
+ *
+ * RETURN:      Pointer to the end tag
+ *
+ * DESCRIPTION: Find the END_TAG resource descriptor in a resource template
+ *
+ ******************************************************************************/
+
+
+u8 *
+acpi_ut_get_resource_end_tag (
+	acpi_operand_object     *obj_desc)
+{
+	u8                      buffer_byte;
+	u8                      *buffer;
+	u8                      *end_buffer;
+
+
+	buffer    = obj_desc->buffer.pointer;
+	end_buffer = buffer + obj_desc->buffer.length;
+
+	while (buffer < end_buffer) {
+		buffer_byte = *buffer;
+		if (buffer_byte & ACPI_RDESC_TYPE_MASK) {
+			/* Large Descriptor - Length is next 2 bytes */
+
+			buffer += ((*(buffer+1) | (*(buffer+2) << 8)) + 3);
+		}
+		else {
+			/* Small Descriptor.  End Tag will be found here */
+
+			if ((buffer_byte & ACPI_RDESC_SMALL_MASK) == ACPI_RDESC_TYPE_END_TAG) {
+				/* Found the end tag descriptor, all done. */
+
+				return (buffer);
+			}
+
+			/* Length is in the header */
+
+			buffer += ((buffer_byte & 0x07) + 1);
+		}
+	}
+
+	/* End tag not found */
+
+	return (NULL);
 }
 
 
diff -Nru a/drivers/acpi/utilities/utobject.c b/drivers/acpi/utilities/utobject.c
--- a/drivers/acpi/utilities/utobject.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/acpi/utilities/utobject.c	Fri Mar 15 17:51:03 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utobject - ACPI object create/delete/size/cache routines
- *              $Revision: 57 $
+ *              $Revision: 68 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,7 +32,7 @@
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utobject")
+	 ACPI_MODULE_NAME    ("utobject")
 
 
 /*******************************************************************************
@@ -62,26 +62,46 @@
 	NATIVE_CHAR             *module_name,
 	u32                     line_number,
 	u32                     component_id,
-	acpi_object_type8       type)
+	acpi_object_type        type)
 {
 	acpi_operand_object     *object;
+	acpi_operand_object     *second_object;
 
 
-	FUNCTION_TRACE_STR ("Ut_create_internal_object_dbg", acpi_ut_get_type_name (type));
+	ACPI_FUNCTION_TRACE_STR ("Ut_create_internal_object_dbg", acpi_ut_get_type_name (type));
 
 
 	/* Allocate the raw object descriptor */
 
 	object = acpi_ut_allocate_object_desc_dbg (module_name, line_number, component_id);
 	if (!object) {
-		/* Allocation failure */
-
 		return_PTR (NULL);
 	}
 
+	switch (type) {
+	case ACPI_TYPE_REGION:
+	case ACPI_TYPE_BUFFER_FIELD:
+
+		/* These types require a secondary object */
+
+		second_object = acpi_ut_allocate_object_desc_dbg (module_name, line_number, component_id);
+		if (!second_object) {
+			acpi_ut_delete_object_desc (object);
+			return_PTR (NULL);
+		}
+
+		second_object->common.type = INTERNAL_TYPE_EXTRA;
+		second_object->common.reference_count = 1;
+
+		/* Link the second object to the first */
+
+		object->common.next_object = second_object;
+		break;
+	}
+
 	/* Save the object type in the object descriptor */
 
-	object->common.type = type;
+	object->common.type = (u8) type;
 
 	/* Init the reference count */
 
@@ -108,7 +128,7 @@
 	void                    *object)
 {
 
-	PROC_NAME ("Ut_valid_internal_object");
+	ACPI_FUNCTION_NAME ("Ut_valid_internal_object");
 
 
 	/* Check for a null pointer */
@@ -121,31 +141,33 @@
 
 	/* Check the descriptor type field */
 
-	if (!VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_INTERNAL)) {
-		/* Not an ACPI internal object, do some further checking */
+	switch (ACPI_GET_DESCRIPTOR_TYPE (object)) {
+	case ACPI_DESC_TYPE_INTERNAL:
 
-		if (VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_NAMED)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-				"**** Obj %p is a named obj, not ACPI obj\n", object));
-		}
+		/* The object appears to be a valid acpi_operand_object  */
 
-		else if (VALID_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_PARSER)) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-				"**** Obj %p is a parser obj, not ACPI obj\n", object));
-		}
+		return (TRUE);
 
-		else {
-			ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
-				"**** Obj %p is of unknown type\n", object));
-		}
+	case ACPI_DESC_TYPE_NAMED:
 
-		return (FALSE);
-	}
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+			"**** Obj %p is a named obj, not ACPI obj\n", object));
+		break;
+
+	case ACPI_DESC_TYPE_PARSER:
+
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+			"**** Obj %p is a parser obj, not ACPI obj\n", object));
+		break;
 
+	default:
 
-	/* The object appears to be a valid acpi_operand_object  */
+		ACPI_DEBUG_PRINT ((ACPI_DB_INFO,
+			"**** Obj %p is of unknown type\n", object));
+		break;
+	}
 
-	return (TRUE);
+	return (FALSE);
 }
 
 
@@ -174,12 +196,12 @@
 	acpi_operand_object     *object;
 
 
-	FUNCTION_TRACE ("Ut_allocate_object_desc_dbg");
+	ACPI_FUNCTION_TRACE ("Ut_allocate_object_desc_dbg");
 
 
 	object = acpi_ut_acquire_from_cache (ACPI_MEM_LIST_OPERAND);
 	if (!object) {
-		_REPORT_ERROR (module_name, line_number, component_id,
+		_ACPI_REPORT_ERROR (module_name, line_number, component_id,
 				  ("Could not allocate an object descriptor\n"));
 
 		return_PTR (NULL);
@@ -188,7 +210,7 @@
 
 	/* Mark the descriptor type */
 
-	object->common.data_type = ACPI_DESC_TYPE_INTERNAL;
+	ACPI_SET_DESCRIPTOR_TYPE (object, ACPI_DESC_TYPE_INTERNAL);
 
 	ACPI_DEBUG_PRINT ((ACPI_DB_ALLOCATIONS, "%p Size %X\n",
 			object, sizeof (acpi_operand_object)));
@@ -213,12 +235,12 @@
 acpi_ut_delete_object_desc (
 	acpi_operand_object     *object)
 {
-	FUNCTION_TRACE_PTR ("Ut_delete_object_desc", object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_delete_object_desc", object);
 
 
 	/* Object must be an acpi_operand_object  */
 
-	if (object->common.data_type != ACPI_DESC_TYPE_INTERNAL) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (object) != ACPI_DESC_TYPE_INTERNAL) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
 			"Obj %p is not an ACPI object\n", object));
 		return_VOID;
@@ -247,7 +269,7 @@
 acpi_ut_delete_object_cache (
 	void)
 {
-	FUNCTION_TRACE ("Ut_delete_object_cache");
+	ACPI_FUNCTION_TRACE ("Ut_delete_object_cache");
 
 
 	acpi_ut_delete_generic_cache (ACPI_MEM_LIST_OPERAND);
@@ -275,13 +297,13 @@
 acpi_status
 acpi_ut_get_simple_object_size (
 	acpi_operand_object     *internal_object,
-	u32                     *obj_length)
+	ACPI_SIZE               *obj_length)
 {
-	u32                     length;
+	ACPI_SIZE               length;
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE_PTR ("Ut_get_simple_object_size", internal_object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_get_simple_object_size", internal_object);
 
 
 	/* Handle a null object (Could be a uninitialized package element -- which is legal) */
@@ -296,10 +318,10 @@
 
 	length = sizeof (acpi_object);
 
-	if (VALID_DESCRIPTOR_TYPE (internal_object, ACPI_DESC_TYPE_NAMED)) {
+	if (ACPI_GET_DESCRIPTOR_TYPE (internal_object) == ACPI_DESC_TYPE_NAMED) {
 		/* Object is a named object (reference), just return the length */
 
-		*obj_length = (u32) ROUND_UP_TO_NATIVE_WORD (length);
+		*obj_length = ACPI_ROUND_UP_TO_NATIVE_WORD (length);
 		return_ACPI_STATUS (status);
 	}
 
@@ -337,23 +359,37 @@
 
 	case INTERNAL_TYPE_REFERENCE:
 
-		/*
-		 * The only type that should be here is internal opcode NAMEPATH_OP -- since
-		 * this means an object reference
-		 */
-		if (internal_object->reference.opcode != AML_INT_NAMEPATH_OP) {
-			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
-				"Unsupported Reference opcode=%X in object %p\n",
-				internal_object->reference.opcode, internal_object));
-			status = AE_TYPE;
-		}
+		switch (internal_object->reference.opcode) {
+		case AML_ZERO_OP:
+		case AML_ONE_OP:
+		case AML_ONES_OP:
+		case AML_REVISION_OP:
+
+			/* These Constant opcodes will be resolved to Integers */
+
+			break;
+
+		case AML_INT_NAMEPATH_OP:
 
-		else {
 			/*
 			 * Get the actual length of the full pathname to this object.
 			 * The reference will be converted to the pathname to the object
 			 */
-			length += ROUND_UP_TO_NATIVE_WORD (acpi_ns_get_pathname_length (internal_object->reference.node));
+			length += ACPI_ROUND_UP_TO_NATIVE_WORD (acpi_ns_get_pathname_length (internal_object->reference.node));
+			break;
+
+		default:
+
+			/*
+			 * No other reference opcodes are supported.
+			 * Notably, Locals and Args are not supported, by this may be
+			 * required eventually.
+			 */
+			ACPI_DEBUG_PRINT ((ACPI_DB_ERROR,
+				"Unsupported Reference opcode=%X in object %p\n",
+				internal_object->reference.opcode, internal_object));
+			status = AE_TYPE;
+			break;
 		}
 		break;
 
@@ -373,8 +409,7 @@
 	 * on a machine word boundary. (preventing alignment faults on some
 	 * machines.)
 	 */
-	*obj_length = (u32) ROUND_UP_TO_NATIVE_WORD (length);
-
+	*obj_length = ACPI_ROUND_UP_TO_NATIVE_WORD (length);
 	return_ACPI_STATUS (status);
 }
 
@@ -400,11 +435,11 @@
 {
 	acpi_status             status = AE_OK;
 	acpi_pkg_info           *info = (acpi_pkg_info *) context;
-	u32                     object_space;
+	ACPI_SIZE               object_space;
 
 
 	switch (object_type) {
-	case 0:
+	case ACPI_COPY_TYPE_SIMPLE:
 
 		/*
 		 * Simple object - just get the size (Null object/entry is handled
@@ -419,18 +454,15 @@
 		break;
 
 
-	case 1:
-		/* Package - nothing much to do here, let the walk handle it */
+	case ACPI_COPY_TYPE_PACKAGE:
+
+		/* Package object - nothing much to do here, let the walk handle it */
 
 		info->num_packages++;
 		state->pkg.this_target_obj = NULL;
 		break;
-
-	default:
-		return (AE_BAD_PARAMETER);
 	}
 
-
 	return (status);
 }
 
@@ -455,13 +487,13 @@
 acpi_status
 acpi_ut_get_package_object_size (
 	acpi_operand_object     *internal_object,
-	u32                     *obj_length)
+	ACPI_SIZE               *obj_length)
 {
 	acpi_status             status;
 	acpi_pkg_info           info;
 
 
-	FUNCTION_TRACE_PTR ("Ut_get_package_object_size", internal_object);
+	ACPI_FUNCTION_TRACE_PTR ("Ut_get_package_object_size", internal_object);
 
 
 	info.length      = 0;
@@ -470,13 +502,16 @@
 
 	status = acpi_ut_walk_package_tree (internal_object, NULL,
 			 acpi_ut_get_element_length, &info);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
+	}
 
 	/*
 	 * We have handled all of the objects in all levels of the package.
 	 * just add the length of the package objects themselves.
 	 * Round up to the next machine word.
 	 */
-	info.length += ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object)) *
+	info.length += ACPI_ROUND_UP_TO_NATIVE_WORD (sizeof (acpi_object)) *
 			  info.num_packages;
 
 	/* Return the total package length */
@@ -503,19 +538,18 @@
 acpi_status
 acpi_ut_get_object_size(
 	acpi_operand_object     *internal_object,
-	u32                     *obj_length)
+	ACPI_SIZE               *obj_length)
 {
 	acpi_status             status;
 
 
-	FUNCTION_ENTRY ();
+	ACPI_FUNCTION_ENTRY ();
 
 
-	if ((VALID_DESCRIPTOR_TYPE (internal_object, ACPI_DESC_TYPE_INTERNAL)) &&
-		(IS_THIS_OBJECT_TYPE (internal_object, ACPI_TYPE_PACKAGE))) {
+	if ((ACPI_GET_DESCRIPTOR_TYPE (internal_object) == ACPI_DESC_TYPE_INTERNAL) &&
+		(internal_object->common.type == ACPI_TYPE_PACKAGE)) {
 		status = acpi_ut_get_package_object_size (internal_object, obj_length);
 	}
-
 	else {
 		status = acpi_ut_get_simple_object_size (internal_object, obj_length);
 	}
diff -Nru a/drivers/acpi/utilities/utxface.c b/drivers/acpi/utilities/utxface.c
--- a/drivers/acpi/utilities/utxface.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/acpi/utilities/utxface.c	Fri Mar 15 17:51:01 2002
@@ -1,12 +1,12 @@
 /******************************************************************************
  *
  * Module Name: utxface - External interfaces for "global" ACPI functions
- *              $Revision: 82 $
+ *              $Revision: 92 $
  *
  *****************************************************************************/
 
 /*
- *  Copyright (C) 2000, 2001 R. Byron Moore
+ *  Copyright (C) 2000 - 2002, R. Byron Moore
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -32,10 +32,12 @@
 #include "amlcode.h"
 #include "acdebug.h"
 #include "acexcep.h"
+#include "acparser.h"
+#include "acdispat.h"
 
 
 #define _COMPONENT          ACPI_UTILITIES
-	 MODULE_NAME         ("utxface")
+	 ACPI_MODULE_NAME    ("utxface")
 
 
 /*******************************************************************************
@@ -57,10 +59,10 @@
 {
 	acpi_status             status;
 
-	FUNCTION_TRACE ("Acpi_initialize_subsystem");
+	ACPI_FUNCTION_TRACE ("Acpi_initialize_subsystem");
 
 
-	DEBUG_EXEC(acpi_ut_init_stack_ptr_trace ());
+	ACPI_DEBUG_EXEC (acpi_ut_init_stack_ptr_trace ());
 
 
 	/* Initialize all globals used by the subsystem */
@@ -71,7 +73,7 @@
 
 	status = acpi_os_initialize ();
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("OSD failed to initialize, %s\n",
+		ACPI_REPORT_ERROR (("OSD failed to initialize, %s\n",
 			acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
@@ -80,7 +82,7 @@
 
 	status = acpi_ut_mutex_initialize ();
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Global mutex creation failure, %s\n",
+		ACPI_REPORT_ERROR (("Global mutex creation failure, %s\n",
 			acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
@@ -92,7 +94,7 @@
 
 	status = acpi_ns_root_initialize ();
 	if (ACPI_FAILURE (status)) {
-		REPORT_ERROR (("Namespace initialization failure, %s\n",
+		ACPI_REPORT_ERROR (("Namespace initialization failure, %s\n",
 			acpi_format_exception (status)));
 		return_ACPI_STATUS (status);
 	}
@@ -100,7 +102,7 @@
 
 	/* If configured, initialize the AML debugger */
 
-	DEBUGGER_EXEC (acpi_db_initialize ());
+	ACPI_DEBUGGER_EXEC (acpi_db_initialize ());
 
 	return_ACPI_STATUS (status);
 }
@@ -126,20 +128,13 @@
 	acpi_status             status = AE_OK;
 
 
-	FUNCTION_TRACE ("Acpi_enable_subsystem");
+	ACPI_FUNCTION_TRACE ("Acpi_enable_subsystem");
 
 
-	/* Sanity check the FADT for valid values */
-
-	status = acpi_ut_validate_fadt ();
-	if (ACPI_FAILURE (status)) {
-		return_ACPI_STATUS (status);
-	}
-
 	/*
-	 * Install the default Op_region handlers. These are
-	 * installed unless other handlers have already been
-	 * installed via the Install_address_space_handler interface
+	 * Install the default Op_region handlers. These are installed unless
+	 * other handlers have already been installed via the
+	 * Install_address_space_handler interface
 	 */
 	if (!(flags & ACPI_NO_ADDRESS_SPACE_INIT)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[Init] Installing default address space handlers\n"));
@@ -152,6 +147,7 @@
 
 	/*
 	 * We must initialize the hardware before we can enable ACPI.
+	 * FADT values are validated here.
 	 */
 	if (!(flags & ACPI_NO_HARDWARE_INIT)) {
 		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[Init] Initializing ACPI hardware\n"));
@@ -190,6 +186,16 @@
 		}
 	}
 
+	/* Install SCI handler, Global Lock handler, GPE handlers */
+
+	if (!(flags & ACPI_NO_HANDLER_INIT)) {
+		ACPI_DEBUG_PRINT ((ACPI_DB_EXEC, "[Init] Installing SCI/GL/GPE handlers\n"));
+
+		status = acpi_ev_handler_initialize ();
+		if (ACPI_FAILURE (status)) {
+			return_ACPI_STATUS (status);
+		}
+	}
 
 	/*
 	 * Initialize all device objects in the namespace
@@ -204,7 +210,6 @@
 		}
 	}
 
-
 	/*
 	 * Initialize the objects that remain uninitialized.  This
 	 * runs the executable AML that is part of the declaration of Op_regions
@@ -219,8 +224,14 @@
 		}
 	}
 
-	acpi_gbl_startup_flags |= ACPI_INITIALIZED_OK;
+	/*
+	 * Empty the caches (delete the cached objects) on the assumption that
+	 * the table load filled them up more than they will be at runtime --
+	 * thus wasting non-paged memory.
+	 */
+	status = acpi_purge_cached_objects ();
 
+	acpi_gbl_startup_flags |= ACPI_INITIALIZED_OK;
 	return_ACPI_STATUS (status);
 }
 
@@ -240,16 +251,12 @@
 acpi_status
 acpi_terminate (void)
 {
-	FUNCTION_TRACE ("Acpi_terminate");
+	ACPI_FUNCTION_TRACE ("Acpi_terminate");
 
 
 	/* Terminate the AML Debugger if present */
 
-	DEBUGGER_EXEC(acpi_gbl_db_terminate_threads = TRUE);
-
-	/* TBD: [Investigate] This is no longer needed?*/
-/*    Acpi_ut_release_mutex (ACPI_MTX_DEBUG_CMD_READY); */
-
+	ACPI_DEBUGGER_EXEC(acpi_gbl_db_terminate_threads = TRUE);
 
 	/* Shutdown and free all resources */
 
@@ -328,42 +335,39 @@
 {
 	acpi_system_info        *info_ptr;
 	u32                     i;
+	acpi_status             status;
 
 
-	FUNCTION_TRACE ("Acpi_get_system_info");
+	ACPI_FUNCTION_TRACE ("Acpi_get_system_info");
 
 
-	/*
-	 *  Must have a valid buffer
-	 */
-	if ((!out_buffer)         ||
-		(!out_buffer->pointer)) {
-		return_ACPI_STATUS (AE_BAD_PARAMETER);
+	/* Parameter validation */
+
+	status = acpi_ut_validate_buffer (out_buffer);
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-	if (out_buffer->length < sizeof (acpi_system_info)) {
-		/*
-		 *  Caller's buffer is too small
-		 */
-		out_buffer->length = sizeof (acpi_system_info);
+	/* Validate/Allocate/Clear caller buffer */
 
-		return_ACPI_STATUS (AE_BUFFER_OVERFLOW);
+	status = acpi_ut_initialize_buffer (out_buffer, sizeof (acpi_system_info));
+	if (ACPI_FAILURE (status)) {
+		return_ACPI_STATUS (status);
 	}
 
-
 	/*
-	 *  Set return length and get data
+	 * Populate the return buffer
 	 */
-	out_buffer->length = sizeof (acpi_system_info);
 	info_ptr = (acpi_system_info *) out_buffer->pointer;
 
 	info_ptr->acpi_ca_version   = ACPI_CA_VERSION;
 
 	/* System flags (ACPI capabilities) */
 
-	info_ptr->flags             = acpi_gbl_system_flags;
+	info_ptr->flags             = ACPI_SYS_MODE_ACPI;
 
 	/* Timer resolution - 24 or 32 bits  */
+
 	if (!acpi_gbl_FADT) {
 		info_ptr->timer_resolution = 0;
 	}
@@ -395,3 +399,28 @@
 }
 
 
+/*****************************************************************************
+ *
+ * FUNCTION:    Acpi_purge_cached_objects
+ *
+ * PARAMETERS:  None
+ *
+ * RETURN:      Status
+ *
+ * DESCRIPTION: Empty all caches (delete the cached objects)
+ *
+ ****************************************************************************/
+
+acpi_status
+acpi_purge_cached_objects (void)
+{
+	ACPI_FUNCTION_TRACE ("Acpi_purge_cached_objects");
+
+
+	acpi_ut_delete_generic_state_cache ();
+	acpi_ut_delete_object_cache ();
+	acpi_ds_delete_walk_state_cache ();
+	acpi_ps_delete_parse_cache ();
+
+	return_ACPI_STATUS (AE_OK);
+}
diff -Nru a/drivers/base/core.c b/drivers/base/core.c
--- a/drivers/base/core.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/base/core.c	Fri Mar 15 17:51:01 2002
@@ -21,7 +21,7 @@
 
 static struct device device_root = {
 	bus_id:		"root",
-	name:		"System Root",
+	name:		"System root",
 };
 
 int (*platform_notify)(struct device * dev) = NULL;
@@ -30,7 +30,7 @@
 extern int device_make_dir(struct device * dev);
 extern void device_remove_dir(struct device * dev);
 
-static spinlock_t device_lock;
+static spinlock_t device_lock = SPIN_LOCK_UNLOCKED;
 
 /**
  * device_register - register a device
@@ -126,20 +126,15 @@
 
 static int __init device_init(void)
 {
-	int error = 0;
-
-	DBG("DEV: Initialising Device Tree\n");
-
-	spin_lock_init(&device_lock);
+	int error;
 
 	error = init_driverfs_fs();
-
 	if (error) {
-		panic("DEV: could not initialise driverfs\n");
+		panic("DEV: could not initialize driverfs");
 		return error;
 	}
-
-	if ((error = device_init_root()))
+	error = device_init_root();
+	if (error)
 		printk(KERN_ERR "%s: device root init failed!\n", __FUNCTION__);
 	return error;
 }
diff -Nru a/drivers/char/efirtc.c b/drivers/char/efirtc.c
--- a/drivers/char/efirtc.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/char/efirtc.c	Fri Mar 15 17:51:03 2002
@@ -40,7 +40,7 @@
 #include <asm/uaccess.h>
 #include <asm/system.h>
 
-#define EFI_RTC_VERSION		"0.2"
+#define EFI_RTC_VERSION		"0.3"
 
 #define EFI_ISDST (EFI_TIME_ADJUST_DAYLIGHT|EFI_TIME_IN_DAYLIGHT)
 /*
@@ -315,56 +315,45 @@
 	spin_unlock_irqrestore(&efi_rtc_lock,flags);
 
 	p += sprintf(p,
-		     "Time      :\n"
-		     "Year      : %u\n"
-		     "Month     : %u\n"
-		     "Day       : %u\n"
-		     "Hour      : %u\n"
-		     "Minute    : %u\n"
-		     "Second    : %u\n"
-		     "Nanosecond: %u\n"
-		     "Daylight  : %u\n",
-		     eft.year, eft.month, eft.day, eft.hour, eft.minute,
-		     eft.second, eft.nanosecond, eft.daylight);
+		     "Time          : %u:%u:%u.%09u\n"
+		     "Date          : %u-%u-%u\n"
+		     "Daylight      : %u\n",
+		     eft.hour, eft.minute, eft.second, eft.nanosecond, 
+		     eft.year, eft.month, eft.day,
+		     eft.daylight);
 
 	if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE)
-		p += sprintf(p, "Timezone  : unspecified\n");
+		p += sprintf(p, "Timezone       : unspecified\n");
 	else
 		/* XXX fixme: convert to string? */
-		p += sprintf(p, "Timezone  : %u\n", eft.timezone);
+		p += sprintf(p, "Timezone       : %u\n", eft.timezone);
 		
 
 	p += sprintf(p,
-		     "\nWakeup Alm:\n"
-		     "Enabled   : %s\n"
-		     "Pending   : %s\n"
-		     "Year      : %u\n"
-		     "Month     : %u\n"
-		     "Day       : %u\n"
-		     "Hour      : %u\n"
-		     "Minute    : %u\n"
-		     "Second    : %u\n"
-		     "Nanosecond: %u\n"
-		     "Daylight  : %u\n",
-		     enabled == 1 ? "Yes" : "No",
-		     pending == 1 ? "Yes" : "No",
-		     alm.year, alm.month, alm.day, alm.hour, alm.minute,
-		     alm.second, alm.nanosecond, alm.daylight);
+		     "Alarm Time     : %u:%u:%u.%09u\n"
+		     "Alarm Date     : %u-%u-%u\n"
+		     "Alarm Daylight : %u\n"
+		     "Enabled        : %s\n"
+		     "Pending        : %s\n",
+		     alm.hour, alm.minute, alm.second, alm.nanosecond, 
+		     alm.year, alm.month, alm.day, 
+		     alm.daylight,
+		     enabled == 1 ? "yes" : "no",
+		     pending == 1 ? "yes" : "no");
 
 	if ( eft.timezone == EFI_UNSPECIFIED_TIMEZONE)
-		p += sprintf(p, "Timezone  : unspecified\n");
+		p += sprintf(p, "Timezone       : unspecified\n");
 	else
 		/* XXX fixme: convert to string? */
-		p += sprintf(p, "Timezone  : %u\n", eft.timezone);
+		p += sprintf(p, "Timezone       : %u\n", alm.timezone);
 
 	/*
 	 * now prints the capabilities
 	 */
 	p += sprintf(p,
-		     "\nClock Cap :\n"
-		     "Resolution: %u\n"
-		     "Accuracy  : %u\n"
-		     "SetstoZero: %u\n",
+		     "Resolution     : %u\n"
+		     "Accuracy       : %u\n"
+		     "SetstoZero     : %u\n",
 		      cap.resolution, cap.accuracy, cap.sets_to_zero);
 
 	return  p - buf;
@@ -390,7 +379,7 @@
 
 	misc_register(&efi_rtc_dev);
 
-	create_proc_read_entry ("efirtc", 0, NULL, efi_rtc_read_proc, NULL);
+	create_proc_read_entry ("driver/efirtc", 0, NULL, efi_rtc_read_proc, NULL);
 
 	return 0;
 }
diff -Nru a/drivers/char/rocket.c b/drivers/char/rocket.c
--- a/drivers/char/rocket.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/char/rocket.c	Fri Mar 15 17:51:01 2002
@@ -227,7 +227,7 @@
 	if (!info)
 		return 1;
 	if (info->magic != RPORT_MAGIC) {
-		printk(badmagic, MAJOR(device), MINOR(device), routine);
+		printk(badmagic, major(device), minor(device), routine);
 		return 1;
 	}
 #endif
@@ -896,7 +896,7 @@
 	CHANNEL_t	*cp;
 	unsigned long page;
 	
-	line = MINOR(tty->device) - tty->driver.minor_start;
+	line = minor(tty->device) - tty->driver.minor_start;
 	if ((line < 0) || (line >= MAX_RP_PORTS))
 		return -ENODEV;
 	if (!tmp_buf) {
diff -Nru a/drivers/char/stallion.c b/drivers/char/stallion.c
--- a/drivers/char/stallion.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/char/stallion.c	Fri Mar 15 17:51:02 2002
@@ -2402,18 +2402,25 @@
 			brdp->ioctrl);
 	}
 
-	if (check_region(brdp->ioaddr1, brdp->iosize1)) {
-		printk("STALLION: Warning, board %d I/O address %x conflicts "
-			"with another device\n", brdp->brdnr, brdp->ioaddr1);
-	}
-	if (brdp->iosize2 > 0) {
-		if (check_region(brdp->ioaddr2, brdp->iosize2)) {
-			printk("STALLION: Warning, board %d I/O address %x "
-				"conflicts with another device\n",
+	if (!request_region(brdp->ioaddr1, brdp->iosize1, name)) {
+		printk(KERN_WARNING "STALLION: Warning, board %d I/O address "
+			"%x conflicts with another device\n", brdp->brdnr, 
+			brdp->ioaddr1);
+		return(-EBUSY);
+	}
+	
+	if (brdp->iosize2 > 0)
+		if (!request_region(brdp->ioaddr2, brdp->iosize2, name)) {
+			printk(KERN_WARNING "STALLION: Warning, board %d I/O "
+				"address %x conflicts with another device\n",
 				brdp->brdnr, brdp->ioaddr2);
+			printk(KERN_WARNING "STALLION: Warning, also "
+				"releasing board %d I/O address %x \n", 
+				brdp->brdnr, brdp->ioaddr1);
+			release_region(brdp->ioaddr1, brdp->iosize1);
+        		return(-EBUSY);
 		}
-	}
- 
+
 /*
  *	Everything looks OK, so let's go ahead and probe for the hardware.
  */
@@ -2454,14 +2461,11 @@
  *	We have verfied that the board is actually present, so now we
  *	can complete the setup.
  */
-	request_region(brdp->ioaddr1, brdp->iosize1, name);
-	if (brdp->iosize2 > 0)
-		request_region(brdp->ioaddr2, brdp->iosize2, name);
 
 	panelp = (stlpanel_t *) stl_memalloc(sizeof(stlpanel_t));
 	if (panelp == (stlpanel_t *) NULL) {
-		printk("STALLION: failed to allocate memory (size=%d)\n",
-			sizeof(stlpanel_t));
+		printk(KERN_WARNING "STALLION: failed to allocate memory "
+			"(size=%d)\n", sizeof(stlpanel_t));
 		return(-ENOMEM);
 	}
 	memset(panelp, 0, sizeof(stlpanel_t));
@@ -2585,22 +2589,27 @@
 	}
 
 /*
- *	Check boards for possible IO address conflicts. We won't actually
- *	do anything about it here, just issue a warning...
+ *	Check boards for possible IO address conflicts and return fail status 
+ * 	if an IO conflict found.
  */
-	conflict = check_region(brdp->ioaddr1, brdp->iosize1) ?
-		brdp->ioaddr1 : 0;
-	if ((conflict == 0) && (brdp->iosize2 > 0))
-		conflict = check_region(brdp->ioaddr2, brdp->iosize2) ?
-			brdp->ioaddr2 : 0;
-	if (conflict) {
-		printk("STALLION: Warning, board %d I/O address %x conflicts "
-			"with another device\n", brdp->brdnr, conflict);
+	if (!request_region(brdp->ioaddr1, brdp->iosize1, name)) {
+		printk(KERN_WARNING "STALLION: Warning, board %d I/O address "
+			"%x conflicts with another device\n", brdp->brdnr, 
+			brdp->ioaddr1);
+		return(-EBUSY);
 	}
-
-	request_region(brdp->ioaddr1, brdp->iosize1, name);
+	
 	if (brdp->iosize2 > 0)
-		request_region(brdp->ioaddr2, brdp->iosize2, name);
+		if (!request_region(brdp->ioaddr2, brdp->iosize2, name)) {
+			printk(KERN_WARNING "STALLION: Warning, board %d I/O "
+				"address %x conflicts with another device\n",
+				brdp->brdnr, brdp->ioaddr2);
+			printk(KERN_WARNING "STALLION: Warning, also "
+				"releasing board %d I/O address %x \n", 
+				brdp->brdnr, brdp->ioaddr1);
+			release_region(brdp->ioaddr1, brdp->iosize1);
+			return(-EBUSY);
+		}
 
 /*
  *	Scan through the secondary io address space looking for panels.
diff -Nru a/drivers/char/sysrq.c b/drivers/char/sysrq.c
--- a/drivers/char/sysrq.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/char/sysrq.c	Fri Mar 15 17:51:02 2002
@@ -284,24 +284,20 @@
 
 /* signal sysrq helper function
  * Sends a signal to all user processes */
-static void send_sig_all(int sig, int even_init)
+static void send_sig_all(int sig)
 {
 	struct task_struct *p;
 
 	for_each_task(p) {
-		if (p->mm) { /* Not swapper nor kernel thread */
-			if (p->pid == 1 && even_init)
-				/* Ugly hack to kill init */
-				p->pid = 0x8000;
-			if (p->pid != 1)
-				force_sig(sig, p);
-		}
+		if (p->mm && p->pid != 1)
+			/* Not swapper, init nor kernel thread */
+			force_sig(sig, p);
 	}
 }
 
 static void sysrq_handle_term(int key, struct pt_regs *pt_regs,
 		struct kbd_struct *kbd, struct tty_struct *tty) {
-	send_sig_all(SIGTERM, 0);
+	send_sig_all(SIGTERM);
 	console_loglevel = 8;
 }
 static struct sysrq_key_op sysrq_term_op = {
@@ -312,7 +308,7 @@
 
 static void sysrq_handle_kill(int key, struct pt_regs *pt_regs,
 		struct kbd_struct *kbd, struct tty_struct *tty) {
-	send_sig_all(SIGKILL, 0);
+	send_sig_all(SIGKILL);
 	console_loglevel = 8;
 }
 static struct sysrq_key_op sysrq_kill_op = {
@@ -321,17 +317,6 @@
 	action_msg:	"Kill All Tasks",
 };
 
-static void sysrq_handle_killall(int key, struct pt_regs *pt_regs,
-		struct kbd_struct *kbd, struct tty_struct *tty) {
-	send_sig_all(SIGKILL, 1);
-	console_loglevel = 8;
-}
-static struct sysrq_key_op sysrq_killall_op = {
-	handler:	sysrq_handle_killall,
-	help_msg:	"killalL",
-	action_msg:	"Kill All Tasks (even init)",
-};
-
 /* END SIGNAL SYSRQ HANDLERS BLOCK */
 
 
@@ -366,7 +351,7 @@
 #else
 /* k */	NULL,
 #endif
-/* l */	&sysrq_killall_op,
+/* l */	NULL,
 /* m */	&sysrq_showmem_op,
 /* n */	NULL,
 /* o */	NULL, /* This will often be registered
diff -Nru a/drivers/hotplug/pci_hotplug_core.c b/drivers/hotplug/pci_hotplug_core.c
--- a/drivers/hotplug/pci_hotplug_core.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/hotplug/pci_hotplug_core.c	Fri Mar 15 17:51:02 2002
@@ -76,7 +76,6 @@
 };
 
 static struct super_operations pcihpfs_ops;
-static struct file_operations pcihpfs_dir_operations;
 static struct file_operations default_file_operations;
 static struct inode_operations pcihpfs_dir_inode_operations;
 static struct vfsmount *pcihpfs_mount;	/* one of the mounts of our fs for reference counting */
@@ -95,13 +94,6 @@
 	return 0;
 }
 
-/* SMP-safe */
-static struct dentry *pcihpfs_lookup (struct inode *dir, struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
 static struct inode *pcihpfs_get_inode (struct super_block *sb, int mode, int dev)
 {
 	struct inode *inode = new_inode(sb);
@@ -123,7 +115,7 @@
 			break;
 		case S_IFDIR:
 			inode->i_op = &pcihpfs_dir_inode_operations;
-			inode->i_fop = &pcihpfs_dir_operations;
+			inode->i_fop = &simple_dir_operations;
 			break;
 		}
 	}
@@ -241,11 +233,6 @@
 	return 0;
 }
 
-static struct file_operations pcihpfs_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-};
-
 static struct file_operations default_file_operations = {
 	read:		default_read_file,
 	write:		default_write_file,
@@ -302,7 +289,7 @@
 
 static struct inode_operations pcihpfs_dir_inode_operations = {
 	create:		pcihpfs_create,
-	lookup:		pcihpfs_lookup,
+	lookup:		simple_lookup,
 	unlink:		pcihpfs_unlink,
 	mkdir:		pcihpfs_mkdir,
 	rmdir:		pcihpfs_rmdir,
@@ -310,7 +297,7 @@
 };
 
 static struct super_operations pcihpfs_ops = {
-	statfs:		pcihpfs_statfs,
+	statfs:		simple_statfs,
 	put_inode:	force_delete,
 };
 
@@ -350,7 +337,7 @@
 	owner:		THIS_MODULE,
 	name:		"pcihpfs",
 	get_sb:		pcihpfs_get_sb,
-	fs_flags:	FS_LITTER,
+	kill_sb:	kill_litter_super,
 };
 
 static int get_mount (void)
diff -Nru a/drivers/ide/Config.help b/drivers/ide/Config.help
--- a/drivers/ide/Config.help	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/Config.help	Fri Mar 15 17:51:03 2002
@@ -251,19 +251,6 @@
   be (U)DMA capable but aren't. This is a blanket on/off test with no
   speed limit options.
 
-  Straight GNU GCC 2.7.3/2.8.X compilers are known to be safe;
-  whereas, many versions of EGCS have a problem and miscompile if you
-  say Y here.
-
-  If in doubt, say N.
-
-CONFIG_BLK_DEV_IDEDMA_TIMEOUT
-  If you say Y here, this is a NASTY UGLY HACK!
-
-  We have to issue an abort and requeue the request DMA engine got
-  turned off by a goofy ASIC, and we have to clean up the mess, and
-  here is as good as any.  Do it globally for all chipsets.
-
   If in doubt, say N.
 
 CONFIG_BLK_DEV_OFFBOARD
@@ -319,10 +306,6 @@
 
   It is SAFEST to say N to this question.
 
-CONFIG_BLK_DEV_ADMA
-  Please read the comments at the top of
-  <file:drivers/ide/ide-adma.c>.
-
 CONFIG_BLK_DEV_PDC_ADMA
   Please read the comments at the top of <file:drivers/ide/ide-pci.c>.
 
@@ -515,10 +498,16 @@
   For FastTrak enable overriding BIOS.
 
 CONFIG_BLK_DEV_SIS5513
-  This driver ensures (U)DMA support for SIS5513 chipset based
-  mainboards. SiS620/530 UDMA mode 4, SiS5600/5597 UDMA mode 2, all
-  other DMA mode 2 limited chipsets are unsupported to date.
+  This driver ensures (U)DMA support for SIS5513 chipset family based
+  mainboards.
 
+  The following chipsets are supported:
+  ATA16:  SiS5511, SiS5513
+  ATA33:  SiS5591, SiS5597, SiS5598, SiS5600
+  ATA66:  SiS530, SiS540, SiS620, SiS630, SiS640
+  ATA100: SiS635, SiS645, SiS650, SiS730, SiS735, SiS740,
+          SiS745, SiS750
+ 
   If you say Y here, you need to say Y to "Use DMA by default when
   available" as well.
 
diff -Nru a/drivers/ide/Config.in b/drivers/ide/Config.in
--- a/drivers/ide/Config.in	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/Config.in	Fri Mar 15 17:51:03 2002
@@ -4,7 +4,7 @@
 # Andre Hedrick <andre@linux-ide.org>
 #
 mainmenu_option next_comment
-comment 'IDE, ATA and ATAPI Block devices'
+comment 'ATA and ATAPI Block devices'
 
 dep_tristate 'Enhanced IDE/MFM/RLL disk/cdrom/tape/floppy support' CONFIG_BLK_DEV_IDE $CONFIG_IDE
 comment 'Please see Documentation/ide.txt for help/info on IDE drives'
@@ -34,121 +34,119 @@
    dep_tristate '  SCSI emulation support' CONFIG_BLK_DEV_IDESCSI $CONFIG_BLK_DEV_IDE $CONFIG_SCSI
 
    comment 'IDE chipset support'
-   if [ "$CONFIG_BLK_DEV_IDE" != "n" ]; then
-      dep_bool '  CMD640 chipset bugfix/support' CONFIG_BLK_DEV_CMD640 $CONFIG_X86
-      dep_bool '    CMD640 enhanced support' CONFIG_BLK_DEV_CMD640_ENHANCED $CONFIG_BLK_DEV_CMD640
-      dep_bool '  ISA-PNP EIDE support' CONFIG_BLK_DEV_ISAPNP $CONFIG_ISAPNP
-      if [ "$CONFIG_PCI" = "y" ]; then
-	 dep_bool '  RZ1000 chipset bugfix/support' CONFIG_BLK_DEV_RZ1000 $CONFIG_X86
-	 bool '  Generic PCI IDE chipset support' CONFIG_BLK_DEV_IDEPCI
-	 if [ "$CONFIG_BLK_DEV_IDEPCI" = "y" ]; then
-	    bool '    Sharing PCI IDE interrupts support' CONFIG_IDEPCI_SHARE_IRQ
-	    bool '    Generic PCI bus-master DMA support' CONFIG_BLK_DEV_IDEDMA_PCI
-	    bool '    Boot off-board chipsets first support' CONFIG_BLK_DEV_OFFBOARD
-	    dep_bool '      Use PCI DMA by default when available' CONFIG_IDEDMA_PCI_AUTO $CONFIG_BLK_DEV_IDEDMA_PCI
-            dep_bool '    Enable DMA only for disks ' CONFIG_IDEDMA_ONLYDISK $CONFIG_IDEDMA_PCI_AUTO
-	    define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_bool '      ATA Work(s) In Progress (EXPERIMENTAL)' CONFIG_IDEDMA_PCI_WIP $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_EXPERIMENTAL
-	    dep_bool '      Attempt to HACK around Chipsets that TIMEOUT (WIP)' CONFIG_BLK_DEV_IDEDMA_TIMEOUT $CONFIG_IDEDMA_PCI_WIP
-	    dep_bool '      Good-Bad DMA Model-Firmware (WIP)' CONFIG_IDEDMA_NEW_DRIVE_LISTINGS $CONFIG_IDEDMA_PCI_WIP
-#	    dep_bool '      Asynchronous DMA support (WIP) (EXPERIMENTAL)' CONFIG_BLK_DEV_ADMA $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_IDEDMA_PCI_WIP
-	    define_bool CONFIG_BLK_DEV_ADMA $CONFIG_BLK_DEV_IDEDMA_PCI
-#	    dep_bool '      Tag Command Queue DMA support (WIP) (EXPERIMENTAL)' CONFIG_BLK_DEV_IDEDMA_TCQ $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_IDEDMA_PCI_WIP
-
-	    dep_bool '    AEC62XX chipset support' CONFIG_BLK_DEV_AEC62XX $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_mbool '      AEC62XX Tuning support' CONFIG_AEC62XX_TUNING $CONFIG_BLK_DEV_AEC62XX
-	    dep_bool '    ALI M15x3 chipset support' CONFIG_BLK_DEV_ALI15X3 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_mbool '      ALI M15x3 WDC support (DANGEROUS)' CONFIG_WDC_ALI15X3 $CONFIG_BLK_DEV_ALI15X3
-	    dep_bool '    AMD Viper support' CONFIG_BLK_DEV_AMD74XX $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_mbool '      AMD Viper ATA-66 Override (WIP)' CONFIG_AMD74XX_OVERRIDE $CONFIG_BLK_DEV_AMD74XX $CONFIG_IDEDMA_PCI_WIP
-	    dep_bool '    CMD64X chipset support' CONFIG_BLK_DEV_CMD64X $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_bool '    CY82C693 chipset support' CONFIG_BLK_DEV_CY82C693 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_bool '    Cyrix CS5530 MediaGX chipset support' CONFIG_BLK_DEV_CS5530 $CONFIG_BLK_DEV_IDEDMA_PCI
-  	    dep_bool '    HPT34X chipset support' CONFIG_BLK_DEV_HPT34X $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_mbool '      HPT34X AUTODMA support (WIP)' CONFIG_HPT34X_AUTODMA $CONFIG_BLK_DEV_HPT34X $CONFIG_IDEDMA_PCI_WIP
-	    dep_bool '    HPT366 chipset support' CONFIG_BLK_DEV_HPT366 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
-	       dep_mbool '    Intel PIIXn chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
-	       dep_mbool '      PIIXn Tuning support' CONFIG_PIIX_TUNING $CONFIG_BLK_DEV_PIIX $CONFIG_IDEDMA_PCI_AUTO
-	    fi
-	    if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
-	       dep_mbool '    IT8172 IDE support' CONFIG_BLK_DEV_IT8172 $CONFIG_BLK_DEV_IDEDMA_PCI
-	       dep_mbool '      IT8172 IDE Tuning support' CONFIG_IT8172_TUNING $CONFIG_BLK_DEV_IT8172 $CONFIG_IDEDMA_PCI_AUTO
-	    fi
-	    dep_bool '    NS87415 chipset support (EXPERIMENTAL)' CONFIG_BLK_DEV_NS87415 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_bool '    OPTi 82C621 chipset enhanced support (EXPERIMENTAL)' CONFIG_BLK_DEV_OPTI621 $CONFIG_EXPERIMENTAL
-	    dep_mbool '   Pacific Digital A-DMA support (EXPERIMENTAL)' CONFIG_BLK_DEV_PDC_ADMA $CONFIG_BLK_DEV_ADMA $CONFIG_IDEDMA_PCI_WIP
-	    dep_bool '    PROMISE PDC202{46|62|65|67|68|69|70} support' CONFIG_BLK_DEV_PDC202XX $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_bool '      Special UDMA Feature' CONFIG_PDC202XX_BURST $CONFIG_BLK_DEV_PDC202XX
-	    dep_bool '      Special FastTrak Feature' CONFIG_PDC202XX_FORCE $CONFIG_BLK_DEV_PDC202XX
-	    dep_bool '    ServerWorks OSB4/CSB5 chipsets support' CONFIG_BLK_DEV_SVWKS $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
-	    dep_bool '    SiS5513 chipset support' CONFIG_BLK_DEV_SIS5513 $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
-	    dep_bool '    SLC90E66 chipset support' CONFIG_BLK_DEV_SLC90E66 $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
-	    dep_bool '    Tekram TRM290 chipset support (EXPERIMENTAL)' CONFIG_BLK_DEV_TRM290 $CONFIG_BLK_DEV_IDEDMA_PCI
-	    dep_bool '    VIA82CXXX chipset support' CONFIG_BLK_DEV_VIA82CXXX $CONFIG_BLK_DEV_IDEDMA_PCI
-         fi
-
-	 if [ "$CONFIG_PPC" = "y" -o "$CONFIG_ARM" = "y" ]; then
-	    bool '    Winbond SL82c105 support' CONFIG_BLK_DEV_SL82C105
-	 fi
-      fi
-      if [ "$CONFIG_ALL_PPC" = "y" ]; then
-	 bool '    Builtin PowerMac IDE support' CONFIG_BLK_DEV_IDE_PMAC
-	 dep_bool '      PowerMac IDE DMA support' CONFIG_BLK_DEV_IDEDMA_PMAC $CONFIG_BLK_DEV_IDE_PMAC
-	 dep_bool '        Use DMA by default' CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO $CONFIG_BLK_DEV_IDEDMA_PMAC
-	 if [ "$CONFIG_BLK_DEV_IDE_PMAC" = "y" ]; then
-	   define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PMAC
+   dep_bool '  CMD640 chipset bugfix/support' CONFIG_BLK_DEV_CMD640 $CONFIG_X86
+   dep_bool '    CMD640 enhanced support' CONFIG_BLK_DEV_CMD640_ENHANCED $CONFIG_BLK_DEV_CMD640
+   dep_bool '  ISA-PNP EIDE support' CONFIG_BLK_DEV_ISAPNP $CONFIG_ISAPNP
+   if [ "$CONFIG_PCI" = "y" ]; then
+      dep_bool '  RZ1000 chipset bugfix/support' CONFIG_BLK_DEV_RZ1000 $CONFIG_X86
+      bool '  Generic PCI IDE chipset support' CONFIG_BLK_DEV_IDEPCI
+      if [ "$CONFIG_BLK_DEV_IDEPCI" = "y" ]; then
+	 bool '    Boot off-board chipsets first support' CONFIG_BLK_DEV_OFFBOARD
+	 bool '    Sharing PCI IDE interrupts support' CONFIG_IDEPCI_SHARE_IRQ
+	 bool '    Generic PCI bus-master DMA support' CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '      Use PCI DMA by default when available' CONFIG_IDEDMA_PCI_AUTO $CONFIG_BLK_DEV_IDEDMA_PCI
+         dep_bool '    Enable DMA only for disks ' CONFIG_IDEDMA_ONLYDISK $CONFIG_IDEDMA_PCI_AUTO
+	 define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '    ATA Work(s) In Progress (EXPERIMENTAL)' CONFIG_IDEDMA_PCI_WIP $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_EXPERIMENTAL
+	 dep_bool '    Good-Bad DMA Model-Firmware (WIP)' CONFIG_IDEDMA_NEW_DRIVE_LISTINGS $CONFIG_IDEDMA_PCI_WIP
+	 dep_bool '    AEC62XX chipset support' CONFIG_BLK_DEV_AEC62XX $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_mbool '      AEC62XX Tuning support' CONFIG_AEC62XX_TUNING $CONFIG_BLK_DEV_AEC62XX
+	 dep_bool '    ALI M15x3 chipset support' CONFIG_BLK_DEV_ALI15X3 $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_mbool '      ALI M15x3 WDC support (DANGEROUS)' CONFIG_WDC_ALI15X3 $CONFIG_BLK_DEV_ALI15X3
+	 dep_bool '    AMD Viper support' CONFIG_BLK_DEV_AMD74XX $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_mbool '      AMD Viper ATA-66 Override (WIP)' CONFIG_AMD74XX_OVERRIDE $CONFIG_BLK_DEV_AMD74XX $CONFIG_IDEDMA_PCI_WIP
+	 dep_bool '    CMD64X chipset support' CONFIG_BLK_DEV_CMD64X $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '    CY82C693 chipset support' CONFIG_BLK_DEV_CY82C693 $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '    Cyrix CS5530 MediaGX chipset support' CONFIG_BLK_DEV_CS5530 $CONFIG_BLK_DEV_IDEDMA_PCI
+  	 dep_bool '    HPT34X chipset support' CONFIG_BLK_DEV_HPT34X $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_mbool '      HPT34X AUTODMA support (WIP)' CONFIG_HPT34X_AUTODMA $CONFIG_BLK_DEV_HPT34X $CONFIG_IDEDMA_PCI_WIP
+	 dep_bool '    HPT366 chipset support' CONFIG_BLK_DEV_HPT366 $CONFIG_BLK_DEV_IDEDMA_PCI
+	 if [ "$CONFIG_X86" = "y" -o "$CONFIG_IA64" = "y" ]; then
+	    dep_mbool '    Intel PIIXn chipsets support' CONFIG_BLK_DEV_PIIX $CONFIG_BLK_DEV_IDEDMA_PCI
+	    dep_mbool '      PIIXn Tuning support' CONFIG_PIIX_TUNING $CONFIG_BLK_DEV_PIIX $CONFIG_IDEDMA_PCI_AUTO
 	 fi
-	 if [ "$CONFIG_BLK_DEV_IDEDMA_PMAC" = "y" ]; then
-	   define_bool CONFIG_BLK_DEV_IDEPCI $CONFIG_BLK_DEV_IDEDMA_PMAC
+	 if [ "$CONFIG_MIPS_ITE8172" = "y" -o "$CONFIG_MIPS_IVR" = "y" ]; then
+	    dep_mbool '    IT8172 IDE support' CONFIG_BLK_DEV_IT8172 $CONFIG_BLK_DEV_IDEDMA_PCI
+	    dep_mbool '      IT8172 IDE Tuning support' CONFIG_IT8172_TUNING $CONFIG_BLK_DEV_IT8172 $CONFIG_IDEDMA_PCI_AUTO
 	 fi
+	 dep_bool '    NS87415 chipset support (EXPERIMENTAL)' CONFIG_BLK_DEV_NS87415 $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '    OPTi 82C621 chipset enhanced support (EXPERIMENTAL)' CONFIG_BLK_DEV_OPTI621 $CONFIG_EXPERIMENTAL
+	 dep_mbool '    Pacific Digital A-DMA support (EXPERIMENTAL)' CONFIG_BLK_DEV_PDC_ADMA $CONFIG_IDEDMA_PCI_WIP
+	 dep_bool '    PROMISE PDC202{46|62|65|67|68|69|70} support' CONFIG_BLK_DEV_PDC202XX $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '      Special UDMA Feature' CONFIG_PDC202XX_BURST $CONFIG_BLK_DEV_PDC202XX
+	 dep_bool '      Special FastTrak Feature' CONFIG_PDC202XX_FORCE $CONFIG_BLK_DEV_PDC202XX
+	 dep_bool '    ServerWorks OSB4/CSB5 chipsets support' CONFIG_BLK_DEV_SVWKS $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
+	 dep_bool '    SiS5513 chipset support' CONFIG_BLK_DEV_SIS5513 $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
+	 dep_bool '    SLC90E66 chipset support' CONFIG_BLK_DEV_SLC90E66 $CONFIG_BLK_DEV_IDEDMA_PCI $CONFIG_X86
+	 dep_bool '    Tekram TRM290 chipset support (EXPERIMENTAL)' CONFIG_BLK_DEV_TRM290 $CONFIG_BLK_DEV_IDEDMA_PCI
+	 dep_bool '    VIA82CXXX chipset support' CONFIG_BLK_DEV_VIA82CXXX $CONFIG_BLK_DEV_IDEDMA_PCI
       fi
-      if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
-	 dep_bool '    ICS IDE interface support' CONFIG_BLK_DEV_IDE_ICSIDE $CONFIG_ARCH_ACORN
-	 dep_bool '      ICS DMA support' CONFIG_BLK_DEV_IDEDMA_ICS $CONFIG_BLK_DEV_IDE_ICSIDE
-	 dep_bool '        Use ICS DMA by default' CONFIG_IDEDMA_ICS_AUTO $CONFIG_BLK_DEV_IDEDMA_ICS
-	 define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_ICS
-	 dep_bool '    RapIDE interface support' CONFIG_BLK_DEV_IDE_RAPIDE $CONFIG_ARCH_ACORN
-      fi
-      if [ "$CONFIG_AMIGA" = "y" ]; then
-	 dep_bool '  Amiga Gayle IDE interface support' CONFIG_BLK_DEV_GAYLE $CONFIG_AMIGA
-	 dep_mbool '    Amiga IDE Doubler support (EXPERIMENTAL)' CONFIG_BLK_DEV_IDEDOUBLER $CONFIG_BLK_DEV_GAYLE $CONFIG_EXPERIMENTAL
-      fi
-      if [ "$CONFIG_ZORRO" = "y" -a "$CONFIG_EXPERIMENTAL" = "y" ]; then
-	 dep_mbool '  Buddha/Catweasel IDE interface support (EXPERIMENTAL)' CONFIG_BLK_DEV_BUDDHA $CONFIG_ZORRO $CONFIG_EXPERIMENTAL
-      fi
-      if [ "$CONFIG_ATARI" = "y" ]; then
-	 dep_bool '  Falcon IDE interface support' CONFIG_BLK_DEV_FALCON_IDE $CONFIG_ATARI
-      fi
-      if [ "$CONFIG_MAC" = "y" ]; then
-	 dep_bool '  Macintosh Quadra/Powerbook IDE interface support' CONFIG_BLK_DEV_MAC_IDE $CONFIG_MAC
+
+      if [ "$CONFIG_PPC" = "y" -o "$CONFIG_ARM" = "y" ]; then
+	 bool '    Winbond SL82c105 support' CONFIG_BLK_DEV_SL82C105
       fi
-      if [ "$CONFIG_Q40" = "y" ]; then
-	 dep_bool '  Q40/Q60 IDE interface support' CONFIG_BLK_DEV_Q40IDE $CONFIG_Q40
+   fi
+   if [ "$CONFIG_ALL_PPC" = "y" ]; then
+      bool '    Builtin PowerMac IDE support' CONFIG_BLK_DEV_IDE_PMAC
+      dep_bool '      PowerMac IDE DMA support' CONFIG_BLK_DEV_IDEDMA_PMAC $CONFIG_BLK_DEV_IDE_PMAC
+      dep_bool '        Use DMA by default' CONFIG_BLK_DEV_IDEDMA_PMAC_AUTO $CONFIG_BLK_DEV_IDEDMA_PMAC
+      if [ "$CONFIG_BLK_DEV_IDE_PMAC" = "y" ]; then
+	 define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_PMAC
       fi
-      if [ "$CONFIG_8xx" = "y" ]; then
-         dep_bool '  MPC8xx IDE support' CONFIG_BLK_DEV_MPC8xx_IDE $CONFIG_8xx
+      if [ "$CONFIG_BLK_DEV_IDEDMA_PMAC" = "y" ]; then
+	 define_bool CONFIG_BLK_DEV_IDEPCI $CONFIG_BLK_DEV_IDEDMA_PMAC
       fi
+   fi
+   if [ "$CONFIG_ARCH_ACORN" = "y" ]; then
+      dep_bool '    ICS IDE interface support' CONFIG_BLK_DEV_IDE_ICSIDE $CONFIG_ARCH_ACORN
+      dep_bool '      ICS DMA support' CONFIG_BLK_DEV_IDEDMA_ICS $CONFIG_BLK_DEV_IDE_ICSIDE
+      dep_bool '        Use ICS DMA by default' CONFIG_IDEDMA_ICS_AUTO $CONFIG_BLK_DEV_IDEDMA_ICS
+      define_bool CONFIG_BLK_DEV_IDEDMA $CONFIG_BLK_DEV_IDEDMA_ICS
+      dep_bool '    RapIDE interface support' CONFIG_BLK_DEV_IDE_RAPIDE $CONFIG_ARCH_ACORN
+   fi
+   if [ "$CONFIG_AMIGA" = "y" ]; then
+      dep_bool '  Amiga Gayle IDE interface support' CONFIG_BLK_DEV_GAYLE $CONFIG_AMIGA
+      dep_mbool '    Amiga IDE Doubler support (EXPERIMENTAL)' CONFIG_BLK_DEV_IDEDOUBLER $CONFIG_BLK_DEV_GAYLE $CONFIG_EXPERIMENTAL
+   fi
+   if [ "$CONFIG_ZORRO" = "y" -a "$CONFIG_EXPERIMENTAL" = "y" ]; then
+      dep_mbool '  Buddha/Catweasel IDE interface support (EXPERIMENTAL)' CONFIG_BLK_DEV_BUDDHA $CONFIG_ZORRO $CONFIG_EXPERIMENTAL
+   fi
+   if [ "$CONFIG_ATARI" = "y" ]; then
+      dep_bool '  Falcon IDE interface support' CONFIG_BLK_DEV_FALCON_IDE $CONFIG_ATARI
+   fi
+   if [ "$CONFIG_MAC" = "y" ]; then
+      dep_bool '  Macintosh Quadra/Powerbook IDE interface support' CONFIG_BLK_DEV_MAC_IDE $CONFIG_MAC
+   fi
+   if [ "$CONFIG_Q40" = "y" ]; then
+      dep_bool '  Q40/Q60 IDE interface support' CONFIG_BLK_DEV_Q40IDE $CONFIG_Q40
+   fi
+   if [ "$CONFIG_8xx" = "y" ]; then
+      dep_bool '  MPC8xx IDE support' CONFIG_BLK_DEV_MPC8xx_IDE $CONFIG_8xx
+   fi
 
-      if [ "$CONFIG_BLK_DEV_MPC8xx_IDE" = "y" ]; then
-         choice 'Type of MPC8xx IDE interface'		\
-		"8xx_PCCARD	CONFIG_IDE_8xx_PCCARD	\
-		 8xx_DIRECT	CONFIG_IDE_8xx_DIRECT	\
-		 EXT_DIRECT	CONFIG_IDE_EXT_DIRECT"	8xx_PCCARD
-      fi
+   if [ "$CONFIG_BLK_DEV_MPC8xx_IDE" = "y" ]; then
+      choice 'Type of MPC8xx IDE interface'		\
+	     "8xx_PCCARD	CONFIG_IDE_8xx_PCCARD	\
+	      8xx_DIRECT	CONFIG_IDE_8xx_DIRECT	\
+	      EXT_DIRECT	CONFIG_IDE_EXT_DIRECT"	8xx_PCCARD
+   fi
 
-      bool '  Other IDE chipset support' CONFIG_IDE_CHIPSETS
-      if [ "$CONFIG_IDE_CHIPSETS" = "y" ]; then
-	 comment 'Note: most of these also require special kernel boot parameters'
-	 bool '    ALI M14xx support' CONFIG_BLK_DEV_ALI14XX
-	 bool '    DTC-2278 support' CONFIG_BLK_DEV_DTC2278
-	 bool '    Holtek HT6560B support' CONFIG_BLK_DEV_HT6560B
-	 if [ "$CONFIG_BLK_DEV_IDEDISK" = "y" -a "$CONFIG_EXPERIMENTAL" = "y" ]; then
-	    bool '    PROMISE DC4030 support (EXPERIMENTAL)' CONFIG_BLK_DEV_PDC4030
-	 fi
-	 bool '    QDI QD65xx support' CONFIG_BLK_DEV_QD65XX
-	 bool '    UMC-8672 support' CONFIG_BLK_DEV_UMC8672
+   bool '  Other IDE chipset support' CONFIG_IDE_CHIPSETS
+   if [ "$CONFIG_IDE_CHIPSETS" = "y" ]; then
+      comment 'Note: most of these also require special kernel boot parameters'
+      bool '    ALI M14xx support' CONFIG_BLK_DEV_ALI14XX
+      bool '    DTC-2278 support' CONFIG_BLK_DEV_DTC2278
+      bool '    Holtek HT6560B support' CONFIG_BLK_DEV_HT6560B
+      if [ "$CONFIG_BLK_DEV_IDEDISK" = "y" -a "$CONFIG_EXPERIMENTAL" = "y" ]; then
+	 bool '    PROMISE DC4030 support (EXPERIMENTAL)' CONFIG_BLK_DEV_PDC4030
       fi
+      bool '    QDI QD65xx support' CONFIG_BLK_DEV_QD65XX
+      bool '    UMC-8672 support' CONFIG_BLK_DEV_UMC8672
+   fi
+   if [ "$CONFIG_BLK_DEV_IDEDMA_PCI" = "y" -o \
+        "$CONFIG_BLK_DEV_IDEDMA_PMAC" = "y" -o \
+        "$CONFIG_BLK_DEV_IDEDMA_ICS" = "y" ]; then
+      bool '  IGNORE word93 Validation BITS' CONFIG_IDEDMA_IVB
    fi
 else
    bool 'Old hard disk (MFM/RLL/IDE) driver' CONFIG_BLK_DEV_HD_ONLY
@@ -161,12 +159,6 @@
    define_bool CONFIG_IDEDMA_AUTO y
 else
    define_bool CONFIG_IDEDMA_AUTO n
-fi
-
-if [ "$CONFIG_BLK_DEV_IDEDMA_PCI" = "y" -o \
-     "$CONFIG_BLK_DEV_IDEDMA_PMAC" = "y" -o \
-     "$CONFIG_BLK_DEV_IDEDMA_ICS" = "y" ]; then
-   bool '  IGNORE word93 Validation BITS' CONFIG_IDEDMA_IVB
 fi
 
 if [ "$CONFIG_BLK_DEV_TIVO" = "y" ]; then
diff -Nru a/drivers/ide/Makefile b/drivers/ide/Makefile
--- a/drivers/ide/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/Makefile	Fri Mar 15 17:51:01 2002
@@ -44,7 +44,6 @@
 ide-obj-$(CONFIG_BLK_DEV_HPT366)	+= hpt366.o
 ide-obj-$(CONFIG_BLK_DEV_HT6560B)	+= ht6560b.o
 ide-obj-$(CONFIG_BLK_DEV_IDE_ICSIDE)	+= icside.o
-ide-obj-$(CONFIG_BLK_DEV_ADMA)		+= ide-adma.o
 ide-obj-$(CONFIG_BLK_DEV_IDEDMA_PCI)	+= ide-dma.o
 ide-obj-$(CONFIG_BLK_DEV_IDEPCI)	+= ide-pci.o
 ide-obj-$(CONFIG_BLK_DEV_ISAPNP)	+= ide-pnp.o
@@ -76,7 +75,7 @@
 
 ide-obj-$(CONFIG_PROC_FS)		+= ide-proc.o
 
-ide-mod-objs		:= ide-taskfile.o ide.o ide-probe.o ide-geometry.o ide-features.o $(ide-obj-y)
+ide-mod-objs		:= ide-taskfile.o ide.o ide-probe.o ide-geometry.o ide-features.o ata-timing.o $(ide-obj-y)
 
 include $(TOPDIR)/Rules.make
 
diff -Nru a/drivers/ide/aec62xx.c b/drivers/ide/aec62xx.c
--- a/drivers/ide/aec62xx.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/aec62xx.c	Fri Mar 15 17:51:02 2002
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define DISPLAY_AEC62XX_TIMINGS
 
@@ -412,16 +412,11 @@
 static void aec62xx_tune_drive (ide_drive_t *drive, byte pio)
 {
 	byte speed;
-	byte new_pio = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
 
-	switch(pio) {
-		case 5:		speed = new_pio; break;
-		case 4:		speed = XFER_PIO_4; break;
-		case 3:		speed = XFER_PIO_3; break;
-		case 2:		speed = XFER_PIO_2; break;
-		case 1:		speed = XFER_PIO_1; break;
-		default:	speed = XFER_PIO_0; break;
-	}
+	if (pio == 255)
+		speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		speed = XFER_PIO_0 + min_t(byte, pio, 4);
 
 	switch(HWIF(drive)->pci_dev->device) {
 		case PCI_DEVICE_ID_ARTOP_ATP850UF:
diff -Nru a/drivers/ide/ali14xx.c b/drivers/ide/ali14xx.c
--- a/drivers/ide/ali14xx.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/ali14xx.c	Fri Mar 15 17:51:03 2002
@@ -48,7 +48,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /* port addresses for auto-detection */
 #define ALI_NUM_PORTS 4
@@ -67,8 +67,6 @@
 	{0x35, 0x03}, {0x00, 0x00}
 };
 
-#define ALI_MAX_PIO 4
-
 /* timing parameter registers for each drive */
 static struct { byte reg1, reg2, reg3, reg4; } regTab[4] = {
 	{0x03, 0x26, 0x04, 0x27},     /* drive 0 */
@@ -114,21 +112,26 @@
 	int time1, time2;
 	byte param1, param2, param3, param4;
 	unsigned long flags;
-	ide_pio_data_t d;
+	struct ata_timing *t;
+
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		pio = XFER_PIO_0 + min_t(byte, pio, 4);
 
-	pio = ide_get_best_pio_mode(drive, pio, ALI_MAX_PIO, &d);
+	t = ata_timing_data(pio);
 
 	/* calculate timing, according to PIO mode */
-	time1 = d.cycle_time;
-	time2 = ide_pio_timings[pio].active_time;
+	time1 = t->cycle;
+	time2 = t->active;
 	param3 = param1 = (time2 * system_bus_speed + 999) / 1000;
 	param4 = param2 = (time1 * system_bus_speed + 999) / 1000 - param1;
-	if (pio < 3) {
+	if (pio < XFER_PIO_3) {
 		param3 += 8;
 		param4 += 8;
 	}
 	printk("%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
-		drive->name, pio, time1, time2, param1, param2, param3, param4);
+		drive->name, pio - XFER_PIO_0, time1, time2, param1, param2, param3, param4);
 
 	/* stuff timing parameters into controller registers */
 	driveNum = (HWIF(drive)->index << 1) + drive->select.b.unit;
diff -Nru a/drivers/ide/alim15x3.c b/drivers/ide/alim15x3.c
--- a/drivers/ide/alim15x3.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/alim15x3.c	Fri Mar 15 17:51:01 2002
@@ -26,7 +26,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define DISPLAY_ALI_TIMINGS
 
@@ -241,7 +241,7 @@
 
 static void ali15x3_tune_drive (ide_drive_t *drive, byte pio)
 {
-	ide_pio_data_t d;
+	struct ata_timing *t;
 	ide_hwif_t *hwif = HWIF(drive);
 	struct pci_dev *dev = hwif->pci_dev;
 	int s_time, a_time, c_time;
@@ -251,14 +251,20 @@
 	int portFIFO = hwif->channel ? 0x55 : 0x54;
 	byte cd_dma_fifo = 0;
 
-	pio = ide_get_best_pio_mode(drive, pio, 5, &d);
-	s_time = ide_pio_timings[pio].setup_time;
-	a_time = ide_pio_timings[pio].active_time;
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		pio = XFER_PIO_0 + min_t(byte, pio, 4);
+
+	t = ata_timing_data(pio);
+
+	s_time = t->setup;
+	a_time = t->active;
 	if ((s_clc = (s_time * system_bus_speed + 999) / 1000) >= 8)
 		s_clc = 0;
 	if ((a_clc = (a_time * system_bus_speed + 999) / 1000) >= 8)
 		a_clc = 0;
-	c_time = ide_pio_timings[pio].cycle_time;
+	c_time = t->cycle;
 
 #if 0
 	if ((r_clc = ((c_time - s_time - a_time) * system_bus_speed + 999) / 1000) >= 16)
@@ -295,17 +301,6 @@
 	pci_write_config_byte(dev, port, s_clc);
 	pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
 	__restore_flags(flags);
-
-	/*
-	 * setup   active  rec
-	 * { 70,   165,    365 },   PIO Mode 0
-	 * { 50,   125,    208 },   PIO Mode 1
-	 * { 30,   100,    110 },   PIO Mode 2
-	 * { 30,   80,     70  },   PIO Mode 3 with IORDY
-	 * { 25,   70,     25  },   PIO Mode 4 with IORDY  ns
-	 * { 20,   50,     30  }    PIO Mode 5 with IORDY (nonstandard)
-	 */
-
 }
 
 static int ali15x3_tune_chipset (ide_drive_t *drive, byte speed)
diff -Nru a/drivers/ide/amd74xx.c b/drivers/ide/amd74xx.c
--- a/drivers/ide/amd74xx.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/amd74xx.c	Fri Mar 15 17:51:03 2002
@@ -1,485 +1,451 @@
 /*
- * linux/drivers/ide/amd74xx.c		Version 0.05	June 9, 2000
+ * $Id: amd74xx.c,v 2.7 2002/09/01 17:37:00 vojtech Exp $
  *
- * Copyright (C) 1999-2000		Andre Hedrick <andre@linux-ide.org>
- * May be copied or modified under the terms of the GNU General Public License
+ *  Copyright (c) 2000-2002 Vojtech Pavlik
  *
+ *  Based on the work of:
+ *	Andre Hedrick
+ */
+
+/*
+ * AMD 755/756/766/8111 IDE driver for Linux.
+ *
+ * UDMA66 and higher modes are autoenabled only in case the BIOS has detected a
+ * 80 wire cable. To ignore the BIOS data and assume the cable is present, use
+ * 'ide0=ata66' or 'ide1=ata66' on the kernel command line.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Should you need to contact me, the author, you can do so either by
+ * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
+ * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
  */
 
 #include <linux/config.h>
-#include <linux/types.h>
 #include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/timer.h>
-#include <linux/mm.h>
 #include <linux/ioport.h>
 #include <linux/blkdev.h>
-#include <linux/hdreg.h>
-
-#include <linux/interrupt.h>
-#include <linux/init.h>
 #include <linux/pci.h>
+#include <linux/init.h>
 #include <linux/ide.h>
-
 #include <asm/io.h>
-#include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
+
+#define AMD_IDE_ENABLE		0x40
+#define AMD_IDE_CONFIG		0x41
+#define AMD_CABLE_DETECT	0x42
+#define AMD_DRIVE_TIMING	0x48
+#define AMD_8BIT_TIMING		0x4e
+#define AMD_ADDRESS_SETUP	0x4c
+#define AMD_UDMA_TIMING		0x50
+
+#define AMD_UDMA		0x07
+#define AMD_UDMA_33		0x01
+#define AMD_UDMA_66		0x02
+#define AMD_UDMA_100		0x03
+#define AMD_BAD_SWDMA		0x08
+#define AMD_BAD_FIFO		0x10
 
-#define DISPLAY_VIPER_TIMINGS
+/*
+ * AMD SouthBridge chips.
+ */
+
+static struct amd_ide_chip {
+	char *name;
+	unsigned short id;
+	unsigned char rev;
+	unsigned char flags;
+} amd_ide_chips[] = {
+	{ "8111",		PCI_DEVICE_ID_AMD_8111_IDE,  0x00, AMD_UDMA_100 },
+	{ "768 Opus",		PCI_DEVICE_ID_AMD_OPUS_7441, 0x00, AMD_UDMA_100 },
+	{ "766 Viper",		PCI_DEVICE_ID_AMD_VIPER_7411, 0x00, AMD_UDMA_100 | AMD_BAD_FIFO },
+	{ "756/c4+ Viper",	PCI_DEVICE_ID_AMD_VIPER_7409, 0x07, AMD_UDMA_66 },
+	{ "756 Viper",		PCI_DEVICE_ID_AMD_VIPER_7409, 0x00, AMD_UDMA_66 | AMD_BAD_SWDMA },
+	{ "755 Cobra",		PCI_DEVICE_ID_AMD_COBRA_7401, 0x00, AMD_UDMA_33 | AMD_BAD_SWDMA },
+	{ NULL }
+};
+
+static struct amd_ide_chip *amd_config;
+static unsigned char amd_enabled;
+static unsigned int amd_80w;
+static unsigned int amd_clock;
+
+static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3 };
+static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 1 };
+static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100" };
+
+/*
+ * AMD /proc entry.
+ */
+
+#ifdef CONFIG_PROC_FS
 
-#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
 #include <linux/stat.h>
 #include <linux/proc_fs.h>
 
-static int amd74xx_get_info(char *, char **, off_t, int);
-extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
+byte amd74xx_proc;
+int amd_base;
 static struct pci_dev *bmide_dev;
+extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
 
-static int amd74xx_get_info (char *buffer, char **addr, off_t offset, int count)
-{
+#define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
+#define amd_print_drive(name, format, arg...)\
+	p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
+
+static int amd_get_info(char *buffer, char **addr, off_t offset, int count)
+{
+	int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
+		 uen[4], udma[4], active8b[4], recover8b[4];
+	struct pci_dev *dev = bmide_dev;
+	unsigned int v, u, i;
+	unsigned short c, w;
+	unsigned char t;
 	char *p = buffer;
-	u32 bibma = pci_resource_start(bmide_dev, 4);
-	u8 c0 = 0, c1 = 0;
 
-	/*
-	 * at that point bibma+0x2 et bibma+0xa are byte registers
-	 * to investigate:
-	 */
-	c0 = inb_p((unsigned short)bibma + 0x02);
-	c1 = inb_p((unsigned short)bibma + 0x0a);
-
-	p += sprintf(p, "\n                                AMD %04X VIPER Chipset.\n", bmide_dev->device);
-	p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
-	p += sprintf(p, "                %sabled                         %sabled\n",
-			(c0&0x80) ? "dis" : " en",
-			(c1&0x80) ? "dis" : " en");
-	p += sprintf(p, "--------------- drive0 --------- drive1 -------- drive0 ---------- drive1 ------\n");
-	p += sprintf(p, "DMA enabled:    %s              %s             %s               %s\n",
-			(c0&0x20) ? "yes" : "no ", (c0&0x40) ? "yes" : "no ",
-			(c1&0x20) ? "yes" : "no ", (c1&0x40) ? "yes" : "no " );
-	p += sprintf(p, "UDMA\n");
-	p += sprintf(p, "DMA\n");
-	p += sprintf(p, "PIO\n");
+	amd_print("----------AMD BusMastering IDE Configuration----------------");
 
-	return p-buffer;	/* => must be less than 4k! */
-}
-#endif  /* defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS) */
+	amd_print("Driver Version:                     2.7");
+	amd_print("South Bridge:                       AMD-%s", amd_config->name);
 
-byte amd74xx_proc = 0;
+	pci_read_config_byte(dev, PCI_REVISION_ID, &t);
+	amd_print("Revision:                           IDE %#x", t);
+	amd_print("Highest DMA rate:                   %s", amd_dma[amd_config->flags & AMD_UDMA]);
 
-extern char *ide_xfer_verbose (byte xfer_rate);
+	amd_print("BM-DMA base:                        %#x", amd_base);
+	amd_print("PCI clock:                          %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
+	
+	amd_print("-----------------------Primary IDE-------Secondary IDE------");
 
-static unsigned int amd74xx_swdma_check (struct pci_dev *dev)
-{
-	unsigned int class_rev;
+	pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
+	amd_print("Prefetch Buffer:       %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
+	amd_print("Post Write Buffer:     %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
 
-	if ((dev->device == PCI_DEVICE_ID_AMD_VIPER_7411) ||
-	    (dev->device == PCI_DEVICE_ID_AMD_VIPER_7441))
-		return 0;
-
-	pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
-	class_rev &= 0xff;
-	return ((int) (class_rev >= 7) ? 1 : 0);
-}
+	pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
+	amd_print("Enabled:               %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
 
-static int amd74xx_swdma_error(ide_drive_t *drive)
-{
-	printk("%s: single-word DMA not support (revision < C4)\n", drive->name);
-	return 0;
-}
+	c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
+	amd_print("Simplex only:          %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
 
-/*
- * Here is where all the hard work goes to program the chipset.
- *
- */
-static int amd74xx_tune_chipset (ide_drive_t *drive, byte speed)
-{
-	ide_hwif_t *hwif	= HWIF(drive);
-	struct pci_dev *dev	= hwif->pci_dev;
-	int err			= 0;
-	byte unit		= (drive->select.b.unit & 0x01);
-#ifdef CONFIG_BLK_DEV_IDEDMA
-	unsigned long dma_base	= hwif->dma_base;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
-	byte drive_pci		= 0x00;
-	byte drive_pci2		= 0x00;
-	byte ultra_timing	= 0x00;
-	byte dma_pio_timing	= 0x00;
-	byte pio_timing		= 0x00;
-
-        switch (drive->dn) {
-		case 0: drive_pci = 0x53; drive_pci2 = 0x4b; break;
-		case 1: drive_pci = 0x52; drive_pci2 = 0x4a; break;
-		case 2: drive_pci = 0x51; drive_pci2 = 0x49; break;
-		case 3: drive_pci = 0x50; drive_pci2 = 0x48; break;
-		default:
-                        return -1;
-        }
-
-	pci_read_config_byte(dev, drive_pci, &ultra_timing);
-	pci_read_config_byte(dev, drive_pci2, &dma_pio_timing);
-	pci_read_config_byte(dev, 0x4c, &pio_timing);
-
-#ifdef DEBUG
-	printk("%s:%d: Speed 0x%02x UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x\n",
-		drive->name, drive->dn, speed, ultra_timing, dma_pio_timing, pio_timing);
-#endif
+	amd_print("Cable Type:            %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
 
-	ultra_timing	&= ~0xC7;
-	dma_pio_timing	&= ~0xFF;
-	pio_timing	&= ~(0x03 << drive->dn);
-
-#ifdef DEBUG
-	printk("%s: UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x\n",
-		drive->name, ultra_timing, dma_pio_timing, pio_timing);
-#endif
+	if (!amd_clock)
+                return p - buffer;
 
-	switch(speed) {
-#ifdef CONFIG_BLK_DEV_IDEDMA
-		case XFER_UDMA_7:
-		case XFER_UDMA_6:
-			speed = XFER_UDMA_5;
-		case XFER_UDMA_5:
-			ultra_timing |= 0x46;
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_UDMA_4:
-			ultra_timing |= 0x45;
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_UDMA_3:
-			ultra_timing |= 0x44;
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_UDMA_2:
-			ultra_timing |= 0x40;
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_UDMA_1:
-			ultra_timing |= 0x41;
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_UDMA_0:
-			ultra_timing |= 0x42;
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_MW_DMA_2:
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_MW_DMA_1:
-			dma_pio_timing |= 0x21;
-			break;
-		case XFER_MW_DMA_0:
-			dma_pio_timing |= 0x77;
-			break;
-		case XFER_SW_DMA_2:
-			if (!amd74xx_swdma_check(dev))
-				return amd74xx_swdma_error(drive);
-			dma_pio_timing |= 0x42;
-			break;
-		case XFER_SW_DMA_1:
-			if (!amd74xx_swdma_check(dev))
-				return amd74xx_swdma_error(drive);
-			dma_pio_timing |= 0x65;
-			break;
-		case XFER_SW_DMA_0:
-			if (!amd74xx_swdma_check(dev))
-				return amd74xx_swdma_error(drive);
-			dma_pio_timing |= 0xA8;
-			break;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
-		case XFER_PIO_4:
-			dma_pio_timing |= 0x20;
-			break;
-		case XFER_PIO_3:
-			dma_pio_timing |= 0x22;
-			break;
-		case XFER_PIO_2:
-			dma_pio_timing |= 0x42;
-			break;
-		case XFER_PIO_1:
-			dma_pio_timing |= 0x65;
-			break;
-		case XFER_PIO_0:
-		default:
-			dma_pio_timing |= 0xA8;
-			break;
-        }
+	amd_print("-------------------drive0----drive1----drive2----drive3-----");
 
-	pio_timing |= (0x03 << drive->dn);
+	pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
+	pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
+	pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
+	pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
 
-	if (!drive->init_speed)
-		drive->init_speed = speed;
+	for (i = 0; i < 4; i++) {
+		setup[i]     = ((t >> ((3 - i) << 1)) & 0x3) + 1;
+		recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
+		active8b[i]  = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
+		active[i]    = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
+		recover[i]   = ((v >> ((3 - i) << 3)) & 0xf) + 1;
 
-#ifdef CONFIG_BLK_DEV_IDEDMA
-	pci_write_config_byte(dev, drive_pci, ultra_timing);
-#endif /* CONFIG_BLK_DEV_IDEDMA */
-	pci_write_config_byte(dev, drive_pci2, dma_pio_timing);
-	pci_write_config_byte(dev, 0x4c, pio_timing);
+		udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
+		uen[i]  = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
+		den[i]  = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
+
+		if (den[i] && uen[i] && udma[i] == 1) {
+			speed[i] = amd_clock * 3;
+			cycle[i] = 666666 / amd_clock;
+			continue;
+		}
+
+		speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
+		cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
+	}
+
+	amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
+
+	amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
+	amd_print_drive("Cmd Active:    ", "%8dns", 1000000 * active8b[i] / amd_clock);
+	amd_print_drive("Cmd Recovery:  ", "%8dns", 1000000 * recover8b[i] / amd_clock);
+	amd_print_drive("Data Active:   ", "%8dns", 1000000 * active[i] / amd_clock);
+	amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
+	amd_print_drive("Cycle Time:    ", "%8dns", cycle[i]);
+	amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
+
+	return p - buffer;	/* hoping it is less than 4K... */
+}
 
-#ifdef DEBUG
-	printk("%s: UDMA 0x%02x DMAPIO 0x%02x PIO 0x%02x\n",
-		drive->name, ultra_timing, dma_pio_timing, pio_timing);
 #endif
 
-#ifdef CONFIG_BLK_DEV_IDEDMA
-	if (speed > XFER_PIO_4) {
-		outb(inb(dma_base+2)|(1<<(5+unit)), dma_base+2);
-	} else {
-		outb(inb(dma_base+2) & ~(1<<(5+unit)), dma_base+2);
+/*
+ * amd_set_speed() writes timing values to the chipset registers
+ */
+
+static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ata_timing *timing)
+{
+	unsigned char t;
+
+	pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
+	t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
+	pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
+
+	pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
+		((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
+
+	pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
+		((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
+
+	switch (amd_config->flags & AMD_UDMA) {
+		case AMD_UDMA_33:  t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
+		case AMD_UDMA_66:  t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
+		case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
+		default: return;
 	}
-#endif /* CONFIG_BLK_DEV_IDEDMA */
 
-	err = ide_config_drive_speed(drive, speed);
-	drive->current_speed = speed;
-	return (err);
+	pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
 }
 
-static void config_chipset_for_pio (ide_drive_t *drive)
+/*
+ * amd_set_drive() computes timing values configures the drive and
+ * the chipset to a desired transfer mode. It also can be called
+ * by upper layers.
+ */
+
+static int amd_set_drive(ide_drive_t *drive, unsigned char speed)
 {
-	unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
-	unsigned short xfer_pio	= drive->id->eide_pio_modes;
-	byte			timing, speed, pio;
-
-	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
-
-	if (xfer_pio> 4)
-		xfer_pio = 0;
-
-	if (drive->id->eide_pio_iordy > 0) {
-		for (xfer_pio = 5;
-			xfer_pio>0 &&
-			drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
-			xfer_pio--);
-	} else {
-		xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
-			   (drive->id->eide_pio_modes & 2) ? 0x04 :
-			   (drive->id->eide_pio_modes & 1) ? 0x03 :
-			   (drive->id->tPIO & 2) ? 0x02 :
-			   (drive->id->tPIO & 1) ? 0x01 : xfer_pio;
-	}
-
-	timing = (xfer_pio >= pio) ? xfer_pio : pio;
-
-	switch(timing) {
-		case 4: speed = XFER_PIO_4;break;
-		case 3: speed = XFER_PIO_3;break;
-		case 2: speed = XFER_PIO_2;break;
-		case 1: speed = XFER_PIO_1;break;
-		default:
-			speed = (!drive->id->tPIO) ? XFER_PIO_0 : XFER_PIO_SLOW;
-			break;
+	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
+	struct ata_timing t, p;
+	int T, UT;
+
+	if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
+		if (ide_config_drive_speed(drive, speed))
+			printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
+				drive->dn >> 1, drive->dn & 1);
+
+	T = 1000000000 / amd_clock;
+	UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
+
+	ata_timing_compute(drive, speed, &t, T, UT);
+
+	if (peer->present) {
+		ata_timing_compute(peer, peer->current_speed, &p, T, UT);
+		ata_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
 	}
-	(void) amd74xx_tune_chipset(drive, speed);
+
+	if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
+
+	amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
+
+	if (!drive->init_speed)	
+		drive->init_speed = speed;
 	drive->current_speed = speed;
+
+	return 0;
 }
 
-static void amd74xx_tune_drive (ide_drive_t *drive, byte pio)
+/*
+ * amd74xx_tune_drive() is a callback from upper layers for
+ * PIO-only tuning.
+ */
+
+static void amd74xx_tune_drive(ide_drive_t *drive, unsigned char pio)
 {
-	byte speed;
-	switch(pio) {
-		case 4:		speed = XFER_PIO_4;break;
-		case 3:		speed = XFER_PIO_3;break;
-		case 2:		speed = XFER_PIO_2;break;
-		case 1:		speed = XFER_PIO_1;break;
-		default:	speed = XFER_PIO_0;break;
+	if (!((amd_enabled >> HWIF(drive)->channel) & 1))
+		return;
+
+	if (pio == 255) {
+		amd_set_drive(drive, ata_timing_mode(drive, XFER_PIO | XFER_EPIO));
+		return;
 	}
-	(void) amd74xx_tune_chipset(drive, speed);
+
+	amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
 }
 
 #ifdef CONFIG_BLK_DEV_IDEDMA
+
 /*
- * This allows the configuration of ide_pci chipset registers
- * for cards that learn about the drive's UDMA, DMA, PIO capabilities
- * after the drive is reported by the OS.
+ * amd74xx_dmaproc() is a callback from upper layers that can do
+ * a lot, but we use it for DMA/PIO tuning only, delegating everything
+ * else to the default ide_dmaproc().
  */
-static int config_chipset_for_dma (ide_drive_t *drive)
+
+int amd74xx_dmaproc(ide_dma_action_t func, ide_drive_t *drive)
 {
-	ide_hwif_t *hwif	= HWIF(drive);
-	struct pci_dev *dev	= hwif->pci_dev;
-	struct hd_driveid *id	= drive->id;
-	byte udma_66		= eighty_ninty_three(drive);
-	byte udma_100		= ((dev->device==PCI_DEVICE_ID_AMD_VIPER_7411)||
-				   (dev->device==PCI_DEVICE_ID_AMD_VIPER_7441)) ? 1 : 0;
-	byte speed		= 0x00;
-	int  rval;
-
-	if ((id->dma_ultra & 0x0020) && (udma_66) && (udma_100)) {
-		speed = XFER_UDMA_5;
-	} else if ((id->dma_ultra & 0x0010) && (udma_66)) {
-		speed = XFER_UDMA_4;
-	} else if ((id->dma_ultra & 0x0008) && (udma_66)) {
-		speed = XFER_UDMA_3;
-	} else if (id->dma_ultra & 0x0004) {
-		speed = XFER_UDMA_2;
-	} else if (id->dma_ultra & 0x0002) {
-		speed = XFER_UDMA_1;
-	} else if (id->dma_ultra & 0x0001) {
-		speed = XFER_UDMA_0;
-	} else if (id->dma_mword & 0x0004) {
-		speed = XFER_MW_DMA_2;
-	} else if (id->dma_mword & 0x0002) {
-		speed = XFER_MW_DMA_1;
-	} else if (id->dma_mword & 0x0001) {
-		speed = XFER_MW_DMA_0;
-	} else {
-		return ((int) ide_dma_off_quietly);
-	}
-
-	(void) amd74xx_tune_chipset(drive, speed);
-
-	rval = (int)(	((id->dma_ultra >> 11) & 7) ? ide_dma_on :
-			((id->dma_ultra >> 8) & 7) ? ide_dma_on :
-			((id->dma_mword >> 8) & 7) ? ide_dma_on :
-						     ide_dma_off_quietly);
 
-	return rval;
+	if (func == ide_dma_check) {
+
+		short w80 = HWIF(drive)->udma_four;
+
+		short speed = ata_timing_mode(drive,
+			XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA |
+			((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) |
+			(w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) |
+			(w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0));
+
+		amd_set_drive(drive, speed);
+
+		func = (HWIF(drive)->autodma && (speed & XFER_MODE) != XFER_PIO)
+			? ide_dma_on : ide_dma_off_quietly;
+	}
+
+	return ide_dmaproc(func, drive);
 }
 
-static int config_drive_xfer_rate (ide_drive_t *drive)
+#endif /* CONFIG_BLK_DEV_IDEDMA */
+
+/*
+ * The initialization callback. Here we determine the IDE chip type
+ * and initialize its drive independent registers.
+ */
+
+unsigned int __init pci_init_amd74xx(struct pci_dev *dev, const char *name)
 {
-	struct hd_driveid *id = drive->id;
-	ide_dma_action_t dma_func = ide_dma_on;
+	unsigned char t;
+	unsigned int u;
+	int i;
 
-	if (id && (id->capability & 1) && HWIF(drive)->autodma) {
-		/* Consult the list of known "bad" drives */
-		if (ide_dmaproc(ide_dma_bad_drive, drive)) {
-			dma_func = ide_dma_off;
-			goto fast_ata_pio;
-		}
-		dma_func = ide_dma_off_quietly;
-		if (id->field_valid & 4) {
-			if (id->dma_ultra & 0x003F) {
-				/* Force if Capable UltraDMA */
-				dma_func = config_chipset_for_dma(drive);
-				if ((id->field_valid & 2) &&
-				    (dma_func != ide_dma_on))
-					goto try_dma_modes;
-			}
-		} else if (id->field_valid & 2) {
-try_dma_modes:
-			if ((id->dma_mword & 0x0007) ||
-			    ((id->dma_1word & 0x007) &&
-			     (amd74xx_swdma_check(HWIF(drive)->pci_dev)))) {
-				/* Force if Capable regular DMA modes */
-				dma_func = config_chipset_for_dma(drive);
-				if (dma_func != ide_dma_on)
-					goto no_dma_set;
-			}
-			
-		} else if (ide_dmaproc(ide_dma_good_drive, drive)) {
-			if (id->eide_dma_time > 150) {
-				goto no_dma_set;
-			}
-			/* Consult the list of known "good" drives */
-			dma_func = config_chipset_for_dma(drive);
-			if (dma_func != ide_dma_on)
-				goto no_dma_set;
-		} else {
-			goto fast_ata_pio;
+/*
+ * Find out what AMD IDE is this.
+ */
+
+	for (amd_config = amd_ide_chips; amd_config->id; amd_config++) {
+			pci_read_config_byte(dev, PCI_REVISION_ID, &t);
+			if (dev->device == amd_config->id && t >= amd_config->rev)
+				break;
 		}
-	} else if ((id->capability & 8) || (id->field_valid & 2)) {
-fast_ata_pio:
-		dma_func = ide_dma_off_quietly;
-no_dma_set:
 
-		config_chipset_for_pio(drive);
+	if (!amd_config->id) {
+		printk(KERN_WARNING "AMD_IDE: Unknown AMD IDE Chip, contact Vojtech Pavlik <vojtech@ucw.cz>\n");
+		return -ENODEV;
 	}
-	return HWIF(drive)->dmaproc(dma_func, drive);
-}
 
 /*
- * amd74xx_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
+ * Check 80-wire cable presence.
  */
 
-int amd74xx_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
-{
-	switch (func) {
-		case ide_dma_check:
-			return config_drive_xfer_rate(drive);
-		default:
+	switch (amd_config->flags & AMD_UDMA) {
+
+		case AMD_UDMA_100:
+			pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
+			amd_80w = ((u & 0x3) ? 1 : 0) | ((u & 0xc) ? 2 : 0);
+			for (i = 24; i >= 0; i -= 8)
+				if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
+					printk(KERN_WARNING "AMD_IDE: Bios didn't set cable bits corectly. Enabling workaround.\n");
+					amd_80w |= (1 << (1 - (i >> 4)));
+				}
+			break;
+
+		case AMD_UDMA_66:
+			pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
+			for (i = 24; i >= 0; i -= 8)
+				if ((u >> i) & 4)
+					amd_80w |= (1 << (1 - (i >> 4)));
 			break;
 	}
-	return ide_dmaproc(func, drive);	/* use standard DMA stuff */
-}
-#endif /* CONFIG_BLK_DEV_IDEDMA */
 
-unsigned int __init pci_init_amd74xx(struct pci_dev *dev)
-{
-	unsigned long fixdma_base = pci_resource_start(dev, 4);
+	pci_read_config_dword(dev, AMD_IDE_ENABLE, &u);
+	amd_enabled = ((u & 1) ? 2 : 0) | ((u & 2) ? 1 : 0);
 
-#ifdef CONFIG_BLK_DEV_IDEDMA
-	if (!amd74xx_swdma_check(dev))
-		printk("%s: disabling single-word DMA support (revision < C4)\n", dev->name);
-#endif /* CONFIG_BLK_DEV_IDEDMA */
+/*
+ * Take care of prefetch & postwrite.
+ */
 
-	if (!fixdma_base) {
-		/*
-		 *
-		 */
-	} else {
-		/*
-		 * enable DMA capable bit, and "not" simplex only
-		 */
-		outb(inb(fixdma_base+2) & 0x60, fixdma_base+2);
+	pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
+	pci_write_config_byte(dev, AMD_IDE_CONFIG,
+		(amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
 
-		if (inb(fixdma_base+2) & 0x80)
-			printk("%s: simplex device: DMA will fail!!\n", dev->name);
+/*
+ * Determine the system bus clock.
+ */
+
+	amd_clock = system_bus_speed * 1000;
+
+	switch (amd_clock) {
+		case 33000: amd_clock = 33333; break;
+		case 37000: amd_clock = 37500; break;
+		case 41000: amd_clock = 41666; break;
 	}
-#if defined(DISPLAY_VIPER_TIMINGS) && defined(CONFIG_PROC_FS)
+
+	if (amd_clock < 20000 || amd_clock > 50000) {
+		printk(KERN_WARNING "AMD_IDE: User given PCI clock speed impossible (%d), using 33 MHz instead.\n", amd_clock);
+		printk(KERN_WARNING "AMD_IDE: Use ide0=ata66 if you want to assume 80-wire cable\n");
+		amd_clock = 33333;
+	}
+
+/*
+ * Print the boot message.
+ */
+
+	pci_read_config_byte(dev, PCI_REVISION_ID, &t);
+	printk(KERN_INFO "AMD_IDE: AMD-%s (rev %02x) IDE %s controller on pci%s\n",
+		amd_config->name, t, amd_dma[amd_config->flags & AMD_UDMA], dev->slot_name);
+
+/*
+ * Register /proc/ide/amd74xx entry
+ */
+
+#ifdef CONFIG_PROC_FS
 	if (!amd74xx_proc) {
-		amd74xx_proc = 1;
+		amd_base = pci_resource_start(dev, 4);
 		bmide_dev = dev;
-		amd74xx_display_info = &amd74xx_get_info;
+		amd74xx_display_info = &amd_get_info;
+		amd74xx_proc = 1;
 	}
-#endif /* DISPLAY_VIPER_TIMINGS && CONFIG_PROC_FS */
+#endif
 
 	return 0;
 }
 
-unsigned int __init ata66_amd74xx (ide_hwif_t *hwif)
+unsigned int __init ata66_amd74xx(ide_hwif_t *hwif)
 {
-#ifdef CONFIG_AMD74XX_OVERRIDE
-	byte ata66 = 1;
-#else
-	byte ata66 = 0;
-#endif /* CONFIG_AMD74XX_OVERRIDE */
-
-#if 0
-	pci_read_config_byte(hwif->pci_dev, 0x48, &ata66);
-	return ((ata66 & 0x02) ? 0 : 1);
-#endif
-	return ata66;
+	return ((amd_enabled & amd_80w) >> hwif->channel) & 1;
 }
 
-void __init ide_init_amd74xx (ide_hwif_t *hwif)
+void __init ide_init_amd74xx(ide_hwif_t *hwif)
 {
-	hwif->tuneproc = &amd74xx_tune_drive;
-	hwif->speedproc = &amd74xx_tune_chipset;
+	int i;
 
-	hwif->highmem = 1;
-
-#ifndef CONFIG_BLK_DEV_IDEDMA
-	hwif->drives[0].autotune = 1;
-	hwif->drives[1].autotune = 1;
+	hwif->tuneproc = &amd74xx_tune_drive;
+	hwif->speedproc = &amd_set_drive;
 	hwif->autodma = 0;
-	return;
-#else
 
+	for (i = 0; i < 2; i++) {
+		hwif->drives[i].io_32bit = 1;
+		hwif->drives[i].unmask = 1;
+		hwif->drives[i].autotune = 1;
+		hwif->drives[i].dn = hwif->channel * 2 + i;
+	}
+
+#ifdef CONFIG_BLK_DEV_IDEDMA
 	if (hwif->dma_base) {
+		hwif->highmem = 1;
 		hwif->dmaproc = &amd74xx_dmaproc;
+#ifdef CONFIG_IDEDMA_AUTO
 		if (!noautodma)
 			hwif->autodma = 1;
-	} else {
-		hwif->autodma = 0;
-		hwif->drives[0].autotune = 1;
-		hwif->drives[1].autotune = 1;
+#endif
 	}
 #endif /* CONFIG_BLK_DEV_IDEDMA */
 }
 
-void __init ide_dmacapable_amd74xx (ide_hwif_t *hwif, unsigned long dmabase)
+/*
+ * We allow the BM-DMA driver only work on enabled interfaces.
+ */
+
+void __init ide_dmacapable_amd74xx(ide_hwif_t *hwif, unsigned long dmabase)
 {
-	ide_setup_dma(hwif, dmabase, 8);
+	if ((amd_enabled >> hwif->channel) & 1)
+		ide_setup_dma(hwif, dmabase, 8);
 }
diff -Nru a/drivers/ide/ata-timing.c b/drivers/ide/ata-timing.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/ide/ata-timing.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,258 @@
+/*
+ * $Id: ata-timing.c,v 2.0 2002/03/12 15:48:43 vojtech Exp $
+ *
+ *  Copyright (c) 1999-2001 Vojtech Pavlik
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Should you need to contact me, the author, you can do so either by e-mail -
+ * mail your message to <vojtech@ucw.cz>, or by paper mail: Vojtech Pavlik,
+ * Simunkova 1594, Prague 8, 182 00 Czech Republic
+ */
+
+#include <linux/kernel.h>
+#include "ata-timing.h"
+
+/*
+ * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).  These were taken
+ * from ATA/ATAPI-6 standard, rev 0a, except for PIO 5, which is a nonstandard
+ * extension and UDMA6, which is currently supported only by Maxtor drives.
+ */
+
+struct ata_timing ata_timing[] = {
+
+	{ XFER_UDMA_6,     0,   0,   0,   0,   0,   0,   0,  15 },
+	{ XFER_UDMA_5,     0,   0,   0,   0,   0,   0,   0,  20 },
+	{ XFER_UDMA_4,     0,   0,   0,   0,   0,   0,   0,  30 },
+	{ XFER_UDMA_3,     0,   0,   0,   0,   0,   0,   0,  45 },
+
+	{ XFER_UDMA_2,     0,   0,   0,   0,   0,   0,   0,  60 },
+	{ XFER_UDMA_1,     0,   0,   0,   0,   0,   0,   0,  80 },
+	{ XFER_UDMA_0,     0,   0,   0,   0,   0,   0,   0, 120 },
+
+	{ XFER_UDMA_SLOW,  0,   0,   0,   0,   0,   0,   0, 150 },
+
+	{ XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 120,   0 },
+	{ XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 150,   0 },
+	{ XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 480,   0 },
+
+	{ XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 240,   0 },
+	{ XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 480,   0 },
+	{ XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 960,   0 },
+
+	{ XFER_PIO_5,     20,  50,  30, 100,  50,  30, 100,   0 },
+	{ XFER_PIO_4,     25,  70,  25, 120,  70,  25, 120,   0 },
+	{ XFER_PIO_3,     30,  80,  70, 180,  80,  70, 180,   0 },
+
+	{ XFER_PIO_2,     30, 290,  40, 330, 100,  90, 240,   0 },
+	{ XFER_PIO_1,     50, 290,  93, 383, 125, 100, 383,   0 },
+	{ XFER_PIO_0,     70, 290, 240, 600, 165, 150, 600,   0 },
+
+	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960,   0 },
+
+	{ -1 }
+};
+
+/*
+ * Determine the best transfer mode appilcable to a particular drive.  This has
+ * then to be matched agains in esp. other drives no the same channel or even
+ * the whole particular host chip.
+ */
+short ata_timing_mode(ide_drive_t *drive, int map)
+{
+	struct hd_driveid *id = drive->id;
+	short best = 0;
+
+	if (!id)
+		return XFER_PIO_SLOW;
+
+	/* Want UDMA and UDMA bitmap valid */
+	if ((map & XFER_UDMA) && (id->field_valid & 4)) {
+		if ((map & XFER_UDMA_133) == XFER_UDMA_133)
+			if ((best = (id->dma_ultra & 0x0040) ? XFER_UDMA_6 : 0)) return best;
+
+		if ((map & XFER_UDMA_100) == XFER_UDMA_100)
+			if ((best = (id->dma_ultra & 0x0020) ? XFER_UDMA_5 : 0)) return best;
+
+		if ((map & XFER_UDMA_66) == XFER_UDMA_66)
+			if ((best = (id->dma_ultra & 0x0010) ? XFER_UDMA_4 :
+				    (id->dma_ultra & 0x0008) ? XFER_UDMA_3 : 0)) return best;
+
+                if ((best = (id->dma_ultra & 0x0004) ? XFER_UDMA_2 :
+			    (id->dma_ultra & 0x0002) ? XFER_UDMA_1 :
+			    (id->dma_ultra & 0x0001) ? XFER_UDMA_0 : 0)) return best;
+	}
+
+	/* Want MWDMA and drive has EIDE fields */
+	if ((map & XFER_MWDMA) && (id->field_valid & 2)) {
+		if ((best = (id->dma_mword & 0x0004) ? XFER_MW_DMA_2 :
+			    (id->dma_mword & 0x0002) ? XFER_MW_DMA_1 :
+			    (id->dma_mword & 0x0001) ? XFER_MW_DMA_0 : 0))
+			return best;
+	}
+
+	/* Want SWDMA */
+	if (map & XFER_SWDMA) {
+
+		/* EIDE SWDMA */
+		if (id->field_valid & 2) {
+			if ((best = (id->dma_1word & 0x0004) ? XFER_SW_DMA_2 :
+				    (id->dma_1word & 0x0002) ? XFER_SW_DMA_1 :
+				    (id->dma_1word & 0x0001) ? XFER_SW_DMA_0 : 0))
+				return best;
+		}
+
+		/* Pre-EIDE style SWDMA */
+		if (id->capability & 1) {
+			if ((best = (id->tDMA == 2) ? XFER_SW_DMA_2 :
+				    (id->tDMA == 1) ? XFER_SW_DMA_1 :
+				    (id->tDMA == 0) ? XFER_SW_DMA_0 : 0))
+				return best;
+		}
+	}
+
+	/* EIDE PIO modes */
+	if ((map & XFER_EPIO) && (id->field_valid & 2)) {
+		if ((best = (drive->id->eide_pio_modes & 4) ? XFER_PIO_5 :
+			    (drive->id->eide_pio_modes & 2) ? XFER_PIO_4 :
+			    (drive->id->eide_pio_modes & 1) ? XFER_PIO_3 : 0))
+			return best;
+	}
+
+	return  (drive->id->tPIO == 2) ? XFER_PIO_2 :
+		(drive->id->tPIO == 1) ? XFER_PIO_1 :
+		(drive->id->tPIO == 0) ? XFER_PIO_0 : XFER_PIO_SLOW;
+}
+
+/*
+ * This is just unit conversion.
+ */
+void ata_timing_quantize(struct ata_timing *t, struct ata_timing *q,
+		int T, int UT)
+{
+	q->setup   = EZ(t->setup   * 1000,  T);
+	q->act8b   = EZ(t->act8b   * 1000,  T);
+	q->rec8b   = EZ(t->rec8b   * 1000,  T);
+	q->cyc8b   = EZ(t->cyc8b   * 1000,  T);
+	q->active  = EZ(t->active  * 1000,  T);
+	q->recover = EZ(t->recover * 1000,  T);
+	q->cycle   = EZ(t->cycle   * 1000,  T);
+	q->udma    = EZ(t->udma    * 1000, UT);
+}
+
+/*
+ * Match against each other the timing setup for two devices on one channel.
+ * Becouse they share the electrical interface we can unsually only use the
+ * lowest common denominator between them.
+ */
+void ata_timing_merge(struct ata_timing *a, struct ata_timing *b,
+		struct ata_timing *m, unsigned int what)
+{
+	if (what & IDE_TIMING_SETUP)
+		m->setup   = max(a->setup,   b->setup);
+	if (what & IDE_TIMING_ACT8B)
+		m->act8b   = max(a->act8b,   b->act8b);
+	if (what & IDE_TIMING_REC8B)
+		m->rec8b   = max(a->rec8b,   b->rec8b);
+	if (what & IDE_TIMING_CYC8B)
+		m->cyc8b   = max(a->cyc8b,   b->cyc8b);
+	if (what & IDE_TIMING_ACTIVE)
+		m->active  = max(a->active,  b->active);
+	if (what & IDE_TIMING_RECOVER)
+		m->recover = max(a->recover, b->recover);
+	if (what & IDE_TIMING_CYCLE)
+		m->cycle   = max(a->cycle,   b->cycle);
+	if (what & IDE_TIMING_UDMA)
+		m->udma    = max(a->udma,    b->udma);
+}
+
+/*
+ * Just get a pointer to the struct describing the timing values used commonly
+ * for a particular mode.
+ */
+struct ata_timing* ata_timing_data(short speed)
+{
+	struct ata_timing *t;
+
+	for (t = ata_timing; t->mode != speed; t++)
+		if (t->mode < 0)
+			return NULL;
+	return t;
+}
+
+int ata_timing_compute(ide_drive_t *drive, short speed, struct ata_timing *t,
+		int T, int UT)
+{
+	struct hd_driveid *id = drive->id;
+	struct ata_timing *s, p;
+
+	/* Find the mode.
+	 */
+
+	if (!(s = ata_timing_data(speed)))
+		return -EINVAL;
+
+	/* If the drive is an EIDE drive, it can tell us it needs extended
+	 * PIO/MWDMA cycle timing.
+	 */
+
+	/* EIDE drive */
+	if (id && id->field_valid & 2) {
+		memset(&p, 0, sizeof(p));
+
+		switch (speed & XFER_MODE) {
+			case XFER_PIO:
+				if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
+						    else p.cycle = p.cyc8b = id->eide_pio_iordy;
+				break;
+
+			case XFER_MWDMA:
+				p.cycle = id->eide_dma_min;
+				break;
+		}
+
+		ata_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
+	}
+
+	/* Convert the timing to bus clock counts.
+	 */
+
+	ata_timing_quantize(s, t, T, UT);
+
+	/* Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
+	 * S.M.A.R.T and some other commands. We have to ensure that the DMA
+	 * cycle timing is slower/equal than the fastest PIO timing.
+	 */
+
+	if ((speed & XFER_MODE) != XFER_PIO) {
+		ata_timing_compute(drive, ata_timing_mode(drive, XFER_PIO | XFER_EPIO), &p, T, UT);
+		ata_timing_merge(&p, t, t, IDE_TIMING_ALL);
+	}
+
+	/* Lenghten active & recovery time so that cycle time is correct.
+	 */
+
+	if (t->act8b + t->rec8b < t->cyc8b) {
+		t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
+		t->rec8b = t->cyc8b - t->act8b;
+	}
+
+	if (t->active + t->recover < t->cycle) {
+		t->active += (t->cycle - (t->active + t->recover)) / 2;
+		t->recover = t->cycle - t->active;
+	}
+
+	return 0;
+}
diff -Nru a/drivers/ide/ata-timing.h b/drivers/ide/ata-timing.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/ide/ata-timing.h	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,85 @@
+#ifndef _ATA_TIMING_H
+#define _ATA_TIMING_H
+
+/*
+ * $Id: ata-timing.h,v 2.0 2002/03/12 13:02:22 vojtech Exp $
+ *
+ *  Copyright (C) 1996  Linus Torvalds, Igor Abramov, and Mark Lord
+ *  Copyright (C) 1999-2001 Vojtech Pavlik
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/hdreg.h>
+#include <linux/ide.h>
+
+#define XFER_PIO_5		0x0d
+#define XFER_UDMA_SLOW		0x4f
+
+struct ata_timing {
+	short mode;
+	short setup;	/* t1 */
+	short act8b;	/* t2 for 8-bit io */
+	short rec8b;	/* t2i for 8-bit io */
+	short cyc8b;	/* t0 for 8-bit io */
+	short active;	/* t2 or tD */
+	short recover;	/* t2i or tK */
+	short cycle;	/* t0 */
+	short udma;	/* t2CYCTYP/2 */
+};
+
+extern struct ata_timing ata_timing[];
+
+#define IDE_TIMING_SETUP	0x01
+#define IDE_TIMING_ACT8B	0x02
+#define IDE_TIMING_REC8B	0x04
+#define IDE_TIMING_CYC8B	0x08
+#define IDE_TIMING_8BIT		0x0e
+#define IDE_TIMING_ACTIVE	0x10
+#define IDE_TIMING_RECOVER	0x20
+#define IDE_TIMING_CYCLE	0x40
+#define IDE_TIMING_UDMA		0x80
+#define IDE_TIMING_ALL		0xff
+
+#define FIT(v,x,y)	max_t(int,min_t(int,v,y),x)
+#define ENOUGH(v,unit)	(((v)-1)/(unit)+1)
+#define EZ(v,unit)	((v)?ENOUGH(v,unit):0)
+
+#define XFER_MODE	0xf0
+#define XFER_UDMA_133	0x48
+#define XFER_UDMA_100	0x44
+#define XFER_UDMA_66	0x42
+#define XFER_UDMA	0x40
+#define XFER_MWDMA	0x20
+#define XFER_SWDMA	0x10
+#define XFER_EPIO	0x01
+#define XFER_PIO	0x00
+
+/* External interface to host chips chanell timing setup.
+ *
+ * It's a bit elaborate due to the legacy we have to bear.
+ */
+
+extern short ata_timing_mode(ide_drive_t *drive, int map);
+extern void ata_timing_quantize(struct ata_timing *t, struct ata_timing *q,
+		int T, int UT);
+extern void ata_timing_merge(struct ata_timing *a, struct ata_timing *b,
+		struct ata_timing *m, unsigned int what);
+extern struct ata_timing* ata_timing_data(short speed);
+extern int ata_timing_compute(ide_drive_t *drive,
+		short speed, struct ata_timing *t, int T, int UT);
+#endif
diff -Nru a/drivers/ide/cmd640.c b/drivers/ide/cmd640.c
--- a/drivers/ide/cmd640.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/cmd640.c	Fri Mar 15 17:51:03 2002
@@ -112,7 +112,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /*
  * This flag is set in ide.c by the parameter:  ide0=cmd640_vlb
@@ -589,15 +589,11 @@
 /*
  * Set a specific pio_mode for a drive
  */
-static void cmd640_set_mode (unsigned int index, byte pio_mode, unsigned int cycle_time)
+static void cmd640_set_mode (unsigned int index, byte pio_mode, unsigned int cycle_time, unsigned int active_time, unsigned int setup_time)
 {
-	int setup_time, active_time, recovery_time, clock_time;
+	int recovery_time, clock_time;
 	byte setup_count, active_count, recovery_count, recovery_count2, cycle_count;
 
-	if (pio_mode > 5)
-		pio_mode = 5;
-	setup_time  = ide_pio_timings[pio_mode].setup_time;
-	active_time = ide_pio_timings[pio_mode].active_time;
 	recovery_time = cycle_time - (setup_time + active_time);
 	clock_time = 1000 / system_bus_speed;
 	cycle_count = (cycle_time + clock_time - 1) / clock_time;
@@ -635,7 +631,7 @@
 	 *
 	 * But we do not, because:
 	 *	1) this is the wrong place to do it (proper is do_special() in ide.c)
-	 * 	2) in practice this is rarely, if ever, necessary
+	 *	2) in practice this is rarely, if ever, necessary
 	 */
 	program_drive_counts (index);
 }
@@ -646,7 +642,7 @@
 static void cmd640_tune_drive (ide_drive_t *drive, byte mode_wanted)
 {
 	byte b;
-	ide_pio_data_t  d;
+	struct ata_timing *t;
 	unsigned int index = 0;
 
 	while (drive != cmd_drives[index]) {
@@ -674,14 +670,16 @@
 			return;
 	}
 
-	(void) ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
-	cmd640_set_mode (index, d.pio_mode, d.cycle_time);
+	if (mode_wanted == 255)
+		t = ata_timing_data(ata_timing_mode(drive, XFER_PIO | XFER_EPIO));
+	else
+		t = ata_timing_data(XFER_PIO_0 + min_t(byte, mode_wanted, 4));
+
+	cmd640_set_mode(index, t->mode - XFER_PIO_0, t->cycle, t->active, t->setup);
+
+	printk ("%s: selected cmd640 PIO mode%d (%dns)",
+		drive->name, t->mode, t->cycle);
 
-	printk ("%s: selected cmd640 PIO mode%d (%dns)%s",
-		drive->name,
-		d.pio_mode,
-		d.cycle_time,
-		d.overridden ? " (overriding vendor mode)" : "");
 	display_clocks(index);
 	return;
 }
diff -Nru a/drivers/ide/cmd64x.c b/drivers/ide/cmd64x.c
--- a/drivers/ide/cmd64x.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/cmd64x.c	Fri Mar 15 17:51:02 2002
@@ -23,7 +23,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #ifndef SPLIT_BYTE
 #define SPLIT_BYTE(B,H,L)	((H)=(B>>4), (L)=(B-((B>>4)<<4)))
@@ -272,17 +272,17 @@
 
 /*
  * Attempts to set the interface PIO mode.
- * The preferred method of selecting PIO modes (e.g. mode 4) is 
+ * The preferred method of selecting PIO modes (e.g. mode 4) is
  * "echo 'piomode:4' > /proc/ide/hdx/settings".  Special cases are
  * 8: prefetch off, 9: prefetch on, 255: auto-select best mode.
  * Called with 255 at boot time.
  */
 static void cmd64x_tuneproc (ide_drive_t *drive, byte mode_wanted)
 {
-	int setup_time, active_time, recovery_time, clock_time, pio_mode, cycle_time;
+	int recovery_time, clock_time;
 	byte recovery_count2, cycle_count;
 	int setup_count, active_count, recovery_count;
-	ide_pio_data_t  d;
+	struct ata_timing *t;
 
 	switch (mode_wanted) {
 		case 8: /* set prefetch off */
@@ -291,27 +291,21 @@
 			/*set_prefetch_mode(index, mode_wanted);*/
 			cmdprintk("%s: %sabled cmd640 prefetch\n", drive->name, mode_wanted ? "en" : "dis");
 			return;
+		case 255: mode_wanted = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
 	}
 
-	mode_wanted = ide_get_best_pio_mode (drive, mode_wanted, 5, &d);
-	pio_mode = d.pio_mode;
-	cycle_time = d.cycle_time;
+	t = ata_timing_data(XFER_PIO_0 + min_t(byte, mode_wanted, 4));
 
 	/*
 	 * I copied all this complicated stuff from cmd640.c and made a few minor changes.
 	 * For now I am just going to pray that it is correct.
 	 */
-	if (pio_mode > 5)
-		pio_mode = 5;
-	setup_time  = ide_pio_timings[pio_mode].setup_time;
-	active_time = ide_pio_timings[pio_mode].active_time;
-	recovery_time = cycle_time - (setup_time + active_time);
-	clock_time = 1000 / system_bus_speed;
-	cycle_count = (cycle_time + clock_time - 1) / clock_time;
-
-	setup_count = (setup_time + clock_time - 1) / clock_time;
 
-	active_count = (active_time + clock_time - 1) / clock_time;
+	recovery_time = t->cycle - (t->setup + t->active);
+	clock_time = 1000 / system_bus_speed;
+	cycle_count = (t->cycle + clock_time - 1) / clock_time;
+	setup_count = (t->setup + clock_time - 1) / clock_time;
+	active_count = (t->active + clock_time - 1) / clock_time;
 
 	recovery_count = (recovery_time + clock_time - 1) / clock_time;
 	recovery_count2 = cycle_count - (setup_count + active_count);
@@ -334,9 +328,8 @@
 	 */
 	program_drive_counts (drive, setup_count, active_count, recovery_count);
 
-	cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns)%s, clocks=%d/%d/%d\n",
-		drive->name, pio_mode, mode_wanted, cycle_time,
-		d.overridden ? " (overriding vendor mode)" : "",
+	cmdprintk("%s: selected cmd646 PIO mode%d : %d (%dns), clocks=%d/%d/%d\n",
+		drive->name, t.mode - XFER_PIO_0, mode_wanted, cycle_time,
 		setup_count, active_count, recovery_count);
 }
 
@@ -391,7 +384,7 @@
 static void config_cmd64x_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 {
 	byte speed	= 0x00;
-	byte set_pio	= ide_get_best_pio_mode(drive, 4, 5, NULL);
+	byte set_pio	= ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
 	cmd64x_tuneproc(drive, set_pio);
 	speed = XFER_PIO_0 + set_pio;
@@ -408,7 +401,7 @@
 	u8 speed		= 0x00;
 	u8 mode_pci		= 0x00;
 	u8 channel_timings	= cmd680_taskfile_timing(hwif);
-	u8 set_pio		= ide_get_best_pio_mode(drive, 4, 5, NULL);
+	u8 set_pio		= ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
 	pci_read_config_byte(dev, addr_mask, &mode_pci);
 	mode_pci &= ~((unit) ? 0x30 : 0x03);
diff -Nru a/drivers/ide/cs5530.c b/drivers/ide/cs5530.c
--- a/drivers/ide/cs5530.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/cs5530.c	Fri Mar 15 17:51:03 2002
@@ -27,7 +27,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define DISPLAY_CS5530_TIMINGS
 
@@ -114,10 +114,13 @@
 {
 	ide_hwif_t	*hwif = HWIF(drive);
 	unsigned int	format, basereg = CS5530_BASEREG(hwif);
-	static byte	modes[5] = {XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3, XFER_PIO_4};
 
-	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
-	if (!cs5530_set_xfer_mode(drive, modes[pio])) {
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		pio = XFER_PIO_0 + min_t(byte, pio, 4);
+
+	if (!cs5530_set_xfer_mode(drive, pio)) {
 		format = (inl(basereg+4) >> 31) & 1;
 		outl(cs5530_pio_timings[format][pio], basereg+(drive->select.b.unit<<3));
 	}
diff -Nru a/drivers/ide/cy82c693.c b/drivers/ide/cy82c693.c
--- a/drivers/ide/cy82c693.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/cy82c693.c	Fri Mar 15 17:51:02 2002
@@ -53,7 +53,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /* the current version */
 #define CY82_VERSION	"CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
@@ -137,11 +137,14 @@
  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
  *
- */ 
+ */
 static void compute_clocks (byte pio, pio_clocks_t *p_pclk)
 {
+	struct ata_timing *t;
 	int clk1, clk2;
 
+	t = ata_timing_data(XFER_PIO_0 + pio);
+
 	/* we don't check against CY82C693's min and max speed,
 	 * so you can play with the idebus=xx parameter
 	 */
@@ -150,15 +153,13 @@
 		pio = CY82C693_MAX_PIO;
 
 	/* let's calc the address setup time clocks */
-	p_pclk->address_time = (byte)calc_clk(ide_pio_timings[pio].setup_time, system_bus_speed);
+	p_pclk->address_time = (byte)calc_clk(t->setup, system_bus_speed);
 
 	/* let's calc the active and recovery time clocks */
-	clk1 = calc_clk(ide_pio_timings[pio].active_time, system_bus_speed);
+	clk1 = calc_clk(t->active, system_bus_speed);
 
 	/* calc recovery timing */
-	clk2 =	ide_pio_timings[pio].cycle_time -
-		ide_pio_timings[pio].active_time -
-		ide_pio_timings[pio].setup_time;
+	clk2 =	t->cycle - t->active - t->setup;
 
 	clk2 = calc_clk(clk2, system_bus_speed);
 
@@ -166,7 +167,7 @@
 
 	/* note: we use the same values for 16bit IOR and IOW
          *	those are all the same, since I don't have other
-	 *	timings than those from ide_modes.h
+	 *	timings than those from ata-timing.h
 	 */
 
 	p_pclk->time_16r = (byte)clk1;
@@ -321,7 +322,7 @@
 #endif /* CY82C693_DEBUG_LOGS */
 
         /* first let's calc the pio modes */
-	pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
+	pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
 #if CY82C693_DEBUG_INFO
 	printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
diff -Nru a/drivers/ide/dtc2278.c b/drivers/ide/dtc2278.c
--- a/drivers/ide/dtc2278.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/dtc2278.c	Fri Mar 15 17:51:03 2002
@@ -15,7 +15,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /*
  * Changing this #undef to #define may solve start up problems in some systems.
@@ -70,7 +70,7 @@
 {
 	unsigned long flags;
 
-	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
+	pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
 	if (pio >= 3) {
 		save_flags(flags);	/* all CPUs */
diff -Nru a/drivers/ide/hpt34x.c b/drivers/ide/hpt34x.c
--- a/drivers/ide/hpt34x.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/hpt34x.c	Fri Mar 15 17:51:01 2002
@@ -40,7 +40,7 @@
 
 #include <asm/io.h>
 #include <asm/irq.h>
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #ifndef SPLIT_BYTE
 #define SPLIT_BYTE(B,H,L)	((H)=(B>>4), (L)=(B-((B>>4)<<4)))
@@ -145,16 +145,16 @@
 	return(err);
 }
 
-static void config_chipset_for_pio (ide_drive_t *drive)
+static void config_chipset_for_pio(ide_drive_t *drive)
 {
 	unsigned short eide_pio_timing[6] = {960, 480, 240, 180, 120, 90};
 	unsigned short xfer_pio = drive->id->eide_pio_modes;
 
 	byte	timing, speed, pio;
 
-	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
+	pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
-	if (xfer_pio> 4)
+	if (xfer_pio > 4)
 		xfer_pio = 0;
 
 	if (drive->id->eide_pio_iordy > 0) {
diff -Nru a/drivers/ide/hpt366.c b/drivers/ide/hpt366.c
--- a/drivers/ide/hpt366.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/hpt366.c	Fri Mar 15 17:51:01 2002
@@ -61,7 +61,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define DISPLAY_HPT366_TIMINGS
 
@@ -600,9 +600,9 @@
 	unsigned short xfer_pio = drive->id->eide_pio_modes;
 	byte	timing, speed, pio;
 
-	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
+	pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
-	if (xfer_pio> 4)
+	if (xfer_pio > 4)
 		xfer_pio = 0;
 
 	if (drive->id->eide_pio_iordy > 0) {
@@ -928,13 +928,13 @@
 	pci_read_config_byte(dev, state_reg, &regXXh);
 
 	if (state) {
-		(void) ide_do_reset(drive);
+		// reset drives...
 		pci_write_config_byte(dev, state_reg, regXXh|0x80);
 		pci_write_config_byte(dev, 0x59, reg59h|reset);
 	} else {
 		pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 		pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
-		(void) ide_do_reset(drive);
+		// reset drives...
 	}
 	return 0;
 }
diff -Nru a/drivers/ide/ht6560b.c b/drivers/ide/ht6560b.c
--- a/drivers/ide/ht6560b.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/ht6560b.c	Fri Mar 15 17:51:02 2002
@@ -44,7 +44,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /* #define DEBUG */  /* remove comments for DEBUG messages */
 
@@ -199,20 +199,23 @@
 {
 	int active_time, recovery_time;
 	int active_cycles, recovery_cycles;
-	ide_pio_data_t d;
-	
+	struct ata_timing *t;
+
         if (pio) {
-		pio = ide_get_best_pio_mode(drive, pio, 5, &d);
-		
+		if (pio == 255)
+			pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+		else
+			pio = XFER_PIO_0 + min_t(byte, pio, 4);
+
+		t = ata_timing_data(pio);
+
 		/*
 		 *  Just like opti621.c we try to calculate the
 		 *  actual cycle time for recovery and activity
 		 *  according system bus speed.
 		 */
-		active_time = ide_pio_timings[pio].active_time;
-		recovery_time = d.cycle_time 
-			- active_time
-			- ide_pio_timings[pio].setup_time;
+		active_time = t->active;
+		recovery_time = t->cycle - active_time - t->setup;
 		/*
 		 *  Cycle times should be Vesa bus cycles
 		 */
@@ -227,7 +230,8 @@
 		if (recovery_cycles > 15) recovery_cycles = 0;  /* 0==16 */
 		
 #ifdef DEBUG
-		printk("ht6560b: drive %s setting pio=%d recovery=%d (%dns) active=%d (%dns)\n", drive->name, pio, recovery_cycles, recovery_time, active_cycles, active_time);
+		printk("ht6560b: drive %s setting pio=%d recovery=%d (%dns) active=%d (%dns)\n",
+			drive->name, pio - XFER_PIO_0, recovery_cycles, recovery_time, active_cycles, active_time);
 #endif
 		
 		return (byte)((recovery_cycles << 4) | active_cycles);
diff -Nru a/drivers/ide/icside.c b/drivers/ide/icside.c
--- a/drivers/ide/icside.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/icside.c	Fri Mar 15 17:51:01 2002
@@ -351,90 +351,6 @@
 	return ide_error(drive, "dma_intr", stat);
 }
 
-/*
- * The following is a sick duplication from ide-dma.c ;(
- *
- * This should be defined in one place only.
- */
-struct drive_list_entry {
-	char * id_model;
-	char * id_firmware;
-};
-
-static struct drive_list_entry drive_whitelist [] = {
-	{ "Micropolis 2112A",			"ALL"		},
-	{ "CONNER CTMA 4000",			"ALL"		},
-	{ "CONNER CTT8000-A",			"ALL"		},
-	{ "ST34342A",				"ALL"		},
-	{ NULL,					0		}
-};
-
-static struct drive_list_entry drive_blacklist [] = {
-	{ "WDC AC11000H",			"ALL"		},
-	{ "WDC AC22100H",			"ALL"		},
-	{ "WDC AC32500H",			"ALL"		},
-	{ "WDC AC33100H",			"ALL"		},
-	{ "WDC AC31600H",			"ALL"		},
-	{ "WDC AC32100H",			"24.09P07"	},
-	{ "WDC AC23200L",			"21.10N21"	},
-	{ "Compaq CRD-8241B",			"ALL"		},
-	{ "CRD-8400B",				"ALL"		},
-	{ "CRD-8480B",				"ALL"		},
-	{ "CRD-8480C",				"ALL"		},
-	{ "CRD-8482B",				"ALL"		},
- 	{ "CRD-84",				"ALL"		},
-	{ "SanDisk SDP3B",			"ALL"		},
-	{ "SanDisk SDP3B-64",			"ALL"		},
-	{ "SANYO CD-ROM CRD",			"ALL"		},
-	{ "HITACHI CDR-8",			"ALL"		},
-	{ "HITACHI CDR-8335",			"ALL"		},
-	{ "HITACHI CDR-8435",			"ALL"		},
-	{ "Toshiba CD-ROM XM-6202B",		"ALL"		},
-	{ "CD-532E-A",				"ALL"		},
-	{ "E-IDE CD-ROM CR-840",		"ALL"		},
-	{ "CD-ROM Drive/F5A",			"ALL"		},
-	{ "RICOH CD-R/RW MP7083A",		"ALL"		},
-	{ "WPI CDD-820",			"ALL"		},
-	{ "SAMSUNG CD-ROM SC-148C",		"ALL"		},
-	{ "SAMSUNG CD-ROM SC-148F",		"ALL"		},
-	{ "SAMSUNG CD-ROM SC",			"ALL"		},
-	{ "SanDisk SDP3B-64",			"ALL"		},
-	{ "SAMSUNG CD-ROM SN-124",		"ALL"		},
-	{ "PLEXTOR CD-R PX-W8432T",		"ALL"		},
-	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM",	"ALL"		},
-	{ "_NEC DV5800A",			"ALL"		},
-	{ NULL,					0		}
-};
-
-static int in_drive_list(struct hd_driveid *id, struct drive_list_entry * drive_table)
-{
-	for ( ; drive_table->id_model ; drive_table++)
-		if ((!strcmp(drive_table->id_model, id->model)) &&
-		    ((!strstr(drive_table->id_firmware, id->fw_rev)) ||
-		     (!strcmp(drive_table->id_firmware, "ALL"))))
-			return 1;
-	return 0;
-}
-
-/*
- *  For both Blacklisted and Whitelisted drives.
- *  This is setup to be called as an extern for future support
- *  to other special driver code.
- */
-static int icside_check_drive_lists(ide_drive_t *drive, int good_bad)
-{
-	struct hd_driveid *id = drive->id;
-
-	if (good_bad) {
-		return in_drive_list(id, drive_whitelist);
-	} else {
-		int blacklist = in_drive_list(id, drive_blacklist);
-		if (blacklist)
-			printk("%s: Disabling DMA for %s\n", drive->name, id->model);
-		return(blacklist);
-	}
-	return 0;
-}
 
 static int
 icside_dma_check(ide_drive_t *drive)
@@ -449,14 +365,6 @@
 		goto out;
 
 	/*
-	 * Consult the list of known "bad" drives
-	 */
-	if (icside_check_drive_lists(drive, 0)) {
-		func = ide_dma_off;
-		goto out;
-	}
-
-	/*
 	 * Enable DMA on any drive that has multiword DMA
 	 */
 	if (id->field_valid & 2) {
@@ -473,16 +381,6 @@
 		goto out;
 	}
 
-	/*
-	 * Consult the list of known "good" drives
-	 */
-	if (icside_check_drive_lists(drive, 1)) {
-		if (id->eide_dma_time > 150)
-			goto out;
-		xfer_mode = XFER_MW_DMA_1;
-		func = ide_dma_on;
-	}
-
 out:
 	func = icside_config_if(drive, xfer_mode);
 
@@ -563,11 +461,6 @@
 	case ide_dma_test_irq:
 		return inb((unsigned long)hwif->hw.priv) & 1;
 
-	case ide_dma_bad_drive:
-	case ide_dma_good_drive:
-		return icside_check_drive_lists(drive, (func ==
-						ide_dma_good_drive));
-
 	case ide_dma_verbose:
 		return icside_dma_verbose(drive);
 
@@ -605,13 +498,12 @@
 	return 0;
 }
 
-int ide_release_dma(ide_hwif_t *hwif)
+void ide_release_dma(ide_hwif_t *hwif)
 {
 	if (hwif->sg_table) {
 		kfree(hwif->sg_table);
 		hwif->sg_table = NULL;
 	}
-	return 1;
 }
 #endif
 
diff -Nru a/drivers/ide/ide-adma.c b/drivers/ide/ide-adma.c
--- a/drivers/ide/ide-adma.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,9 +0,0 @@
-/*
- *  linux/drivers/ide/ide-adma.c         Version 0.00	June 24, 2001
- *
- *  Copyright (c) 2001		Andre Hedrick <andre@linux-ide.org>
- *
- *  Asynchronous DMA -- TBA, this is a holding file.
- *
- */
-
diff -Nru a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c
--- a/drivers/ide/ide-cd.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/ide-cd.c	Fri Mar 15 17:51:03 2002
@@ -1671,11 +1671,16 @@
 	} else if (rq->flags & (REQ_PC | REQ_SENSE)) {
 		return cdrom_do_packet_command(drive);
 	} else if (rq->flags & REQ_SPECIAL) {
+
 		/*
+		 * FIXME: Kill REQ_SEPCIAL and replace it will command commands
+		 * queued at the request queue instead as suggested (abd
+		 * rightly so) by Linus.
+		 *
 		 * right now this can only be a reset...
 		 */
-		cdrom_end_request(drive, 1);
-		return ide_do_reset(drive);
+		cdrom_end_request(drive, 1); return ide_stopped;
+
 	} else if (rq->flags & REQ_BLOCK_PC) {
 		return cdrom_do_block_pc(drive, rq);
 	}
@@ -2507,6 +2512,11 @@
 		devinfo->mask |= CDC_PLAY_AUDIO;
 	if (!CDROM_CONFIG_FLAGS (drive)->close_tray)
 		devinfo->mask |= CDC_CLOSE_TRAY;
+
+	/* FIXME: I'm less that sure that this is the proper thing to do, since
+	 * ware already adding the devices to devfs int ide.c upon device
+	 * registration.
+	 */
 
 	devinfo->de = devfs_register(drive->de, "cd", DEVFS_FL_DEFAULT,
 				     HWIF(drive)->major, minor,
diff -Nru a/drivers/ide/ide-cs.c b/drivers/ide/ide-cs.c
--- a/drivers/ide/ide-cs.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/ide-cs.c	Fri Mar 15 17:51:02 2002
@@ -401,7 +401,7 @@
     DEBUG(0, "ide_release(0x%p)\n", link);
 
     if (info->ndev) {
-	ide_unregister(info->hd);
+	ide_unregister(&ide_hwifs[info->hd]);
 	MOD_DEC_USE_COUNT;
     }
 
diff -Nru a/drivers/ide/ide-disk.c b/drivers/ide/ide-disk.c
--- a/drivers/ide/ide-disk.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/ide/ide-disk.c	Fri Mar 15 17:51:01 2002
@@ -117,6 +117,8 @@
  */
 static ide_startstop_t do_rw_disk (ide_drive_t *drive, struct request *rq, unsigned long block)
 {
+	if (drive->blocked)
+		panic("ide: Request while drive blocked? You don't like your data intact?");
 	if (!(rq->flags & REQ_CMD)) {
 		blk_dump_rq_flags(rq, "do_rw_disk, bad command");
 		ide_end_request(drive, 0);
@@ -437,7 +439,7 @@
 	if ((args.tfRegister[IDE_STATUS_OFFSET] & 0x01) == 0) {
 		u32 high = ((args.hobRegister[IDE_HCYL_OFFSET_HOB])<<16) |
 			   ((args.hobRegister[IDE_LCYL_OFFSET_HOB])<<8) |
-  			    (args.hobRegister[IDE_SECTOR_OFFSET_HOB]); 
+			    (args.hobRegister[IDE_SECTOR_OFFSET_HOB]);
 		u32 low  = ((args.tfRegister[IDE_HCYL_OFFSET])<<16) |
 			   ((args.tfRegister[IDE_LCYL_OFFSET])<<8) |
 			    (args.tfRegister[IDE_SECTOR_OFFSET]);
@@ -456,7 +458,7 @@
 {
 	ide_task_t args;
 	unsigned long addr_set = 0;
-	
+
 	addr_req--;
 	/* Create IDE/ATA command request structure */
 	memset(&args, 0, sizeof(ide_task_t));
@@ -903,13 +905,51 @@
 	ide_add_setting(drive,	"max_failures",		SETTING_RW,					-1,			-1,			TYPE_INT,	0,	65535,				1,	1,	&drive->max_failures,		NULL);
 }
 
+static int idedisk_suspend(struct device *dev, u32 state, u32 level)
+{
+	ide_drive_t *drive = dev->driver_data;
+
+	/* I hope that every freeze operations from the upper levels have
+	 * already been done...
+	 */
+
+	/* wait until all commands are finished */
+	printk("ide_disk_suspend()\n");
+	while (HWGROUP(drive)->handler)
+		yield();
+
+	/* set the drive to standby */
+	printk(KERN_INFO "suspending: %s ", drive->name);
+	if (ata_ops(drive)) {
+		if (ata_ops(drive)->standby)
+			ata_ops(drive)->standby(drive);
+	}
+	drive->blocked = 1;
+
+	return 0;
+}
+
+static int idedisk_resume(struct device *dev, u32 level)
+{
+	ide_drive_t *drive = dev->driver_data;
+	if (!drive->blocked)
+		panic("ide: Resume but not suspended?\n");
+
+	drive->blocked = 0;
+	return 0;
+}
+
+
 /* This is just a hook for the overall driver tree.
  *
  * FIXME: This is soon goig to replace the custom linked list games played up
  * to great extend between the different components of the IDE drivers.
  */
 
-static struct device_driver idedisk_devdrv = {};
+static struct device_driver idedisk_devdrv = {
+	suspend: idedisk_suspend,
+	resume: idedisk_resume,
+};
 
 static void idedisk_setup(ide_drive_t *drive)
 {
@@ -956,6 +996,7 @@
 	    sprintf(drive->device.name, "ide-disk");
 	    drive->device.driver = &idedisk_devdrv;
 	    drive->device.parent = &HWIF(drive)->device;
+	    drive->device.driver_data = drive;
 	    device_register(&drive->device);
 	}
 
diff -Nru a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c
--- a/drivers/ide/ide-dma.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/ide-dma.c	Fri Mar 15 17:51:01 2002
@@ -106,65 +106,64 @@
 	char * id_firmware;
 };
 
-struct drive_list_entry drive_whitelist [] = {
-
-	{ "Micropolis 2112A"	,       "ALL"		},
-	{ "CONNER CTMA 4000"	,       "ALL"		},
-	{ "CONNER CTT8000-A"	,       "ALL"		},
-	{ "ST34342A"		,	"ALL"		},
-	{ 0			,	0		}
+struct drive_list_entry drive_whitelist[] = {
+	{ "Micropolis 2112A", NULL },
+	{ "CONNER CTMA 4000", NULL },
+	{ "CONNER CTT8000-A", NULL },
+	{ "ST34342A", NULL },
+	{ NULL, NULL }
 };
 
-struct drive_list_entry drive_blacklist [] = {
+struct drive_list_entry drive_blacklist[] = {
 
-	{ "WDC AC11000H"	,	"ALL"		},
-	{ "WDC AC22100H"	,	"ALL"		},
-	{ "WDC AC32500H"	,	"ALL"		},
-	{ "WDC AC33100H"	,	"ALL"		},
-	{ "WDC AC31600H"	,	"ALL"		},
-	{ "WDC AC32100H"	,	"24.09P07"	},
-	{ "WDC AC23200L"	,	"21.10N21"	},
-	{ "Compaq CRD-8241B"	,	"ALL"		},
-	{ "CRD-8400B"		,	"ALL"		},
-	{ "CRD-8480B",			"ALL"		},
-	{ "CRD-8480C",			"ALL"		},
-	{ "CRD-8482B",			"ALL"		},
- 	{ "CRD-84"		,	"ALL"		},
-	{ "SanDisk SDP3B"	,	"ALL"		},
-	{ "SanDisk SDP3B-64"	,	"ALL"		},
-	{ "SANYO CD-ROM CRD"	,	"ALL"		},
-	{ "HITACHI CDR-8"	,	"ALL"		},
-	{ "HITACHI CDR-8335"	,	"ALL"		},
-	{ "HITACHI CDR-8435"	,	"ALL"		},
-	{ "Toshiba CD-ROM XM-6202B"	,	"ALL"		},
-	{ "CD-532E-A"		,	"ALL"		},
-	{ "E-IDE CD-ROM CR-840",	"ALL"		},
-	{ "CD-ROM Drive/F5A",	"ALL"		},
-	{ "RICOH CD-R/RW MP7083A",	"ALL"		},
-	{ "WPI CDD-820",		"ALL"		},
-	{ "SAMSUNG CD-ROM SC-148C",	"ALL"		},
-	{ "SAMSUNG CD-ROM SC-148F",	"ALL"		},
-	{ "SAMSUNG CD-ROM SC",	"ALL"		},
-	{ "SanDisk SDP3B-64"	,	"ALL"		},
-	{ "SAMSUNG CD-ROM SN-124",	"ALL"		},
-	{ "PLEXTOR CD-R PX-W8432T",	"ALL"		},
-	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM",	"ALL"		},
-	{ "_NEC DV5800A",               "ALL"           },  
-	{ 0			,	0		}
+	{ "WDC AC11000H", NULL },
+	{ "WDC AC22100H", NULL },
+	{ "WDC AC32500H", NULL },
+	{ "WDC AC33100H", NULL },
+	{ "WDC AC31600H", NULL },
+	{ "WDC AC32100H", "24.09P07" },
+	{ "WDC AC23200L", "21.10N21" },
+	{ "Compaq CRD-8241B", NULL },
+	{ "CRD-8400B", NULL },
+	{ "CRD-8480B", NULL },
+	{ "CRD-8480C", NULL },
+	{ "CRD-8482B", NULL },
+	{ "CRD-84", NULL },
+	{ "SanDisk SDP3B", NULL },
+	{ "SanDisk SDP3B-64", NULL },
+	{ "SANYO CD-ROM CRD", NULL },
+	{ "HITACHI CDR-8", NULL },
+	{ "HITACHI CDR-8335", NULL },
+	{ "HITACHI CDR-8435", NULL },
+	{ "Toshiba CD-ROM XM-6202B", NULL },
+	{ "CD-532E-A", NULL },
+	{ "E-IDE CD-ROM CR-840", NULL },
+	{ "CD-ROM Drive/F5A", NULL },
+	{ "RICOH CD-R/RW MP7083A", NULL },
+	{ "WPI CDD-820", NULL },
+	{ "SAMSUNG CD-ROM SC-148C", NULL },
+	{ "SAMSUNG CD-ROM SC-148F", NULL },
+	{ "SAMSUNG CD-ROM SC", NULL },
+	{ "SanDisk SDP3B-64", NULL },
+	{ "SAMSUNG CD-ROM SN-124", NULL },
+	{ "PLEXTOR CD-R PX-W8432T", NULL },
+	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM", NULL },
+	{ "_NEC DV5800A", NULL },
+	{ NULL,	NULL }
 
 };
 
-int in_drive_list(struct hd_driveid *id, struct drive_list_entry * drive_table)
+static int in_drive_list(struct hd_driveid *id, struct drive_list_entry * drive_table)
 {
 	for ( ; drive_table->id_model ; drive_table++)
 		if ((!strcmp(drive_table->id_model, id->model)) &&
-		    ((!strstr(drive_table->id_firmware, id->fw_rev)) ||
-		     (!strcmp(drive_table->id_firmware, "ALL"))))
+		    ((drive_table->id_firmware && !strstr(drive_table->id_firmware, id->fw_rev)) ||
+		     (!drive_table->id_firmware)))
 			return 1;
 	return 0;
 }
 
-#else /* !CONFIG_IDEDMA_NEW_DRIVE_LISTINGS */
+#else
 
 /*
  * good_dma_drives() lists the model names (from "hdparm -i")
@@ -185,7 +184,7 @@
  * This is an empirical list. Its generated from bug reports. That means
  * while it reflects actual problem distributions it doesn't answer whether
  * the drive or the controller, or cabling, or software, or some combination
- * thereof is the fault. If you don't happen to agree with the kernel's 
+ * thereof is the fault. If you don't happen to agree with the kernel's
  * opinion of your drive - use hdparm to turn DMA on.
  */
 const char *bad_dma_drives[] = {"WDC AC11000H",
@@ -194,9 +193,9 @@
 				"WDC AC32500H",
 				"WDC AC33100H",
 				"WDC AC31600H",
- 				NULL};
+				NULL};
 
-#endif /* CONFIG_IDEDMA_NEW_DRIVE_LISTINGS */
+#endif
 
 /*
  * dma_intr() is the handler for disk read/write DMA interrupts
@@ -498,11 +497,10 @@
 	return hwif->dmaproc(ide_dma_off_quietly, drive);
 }
 
-#ifndef CONFIG_BLK_DEV_IDEDMA_TIMEOUT
 /*
- * 1 dmaing, 2 error, 4 intr
+ * 1 dma-ing, 2 error, 4 intr
  */
-static int dma_timer_expiry (ide_drive_t *drive)
+static int dma_timer_expiry(ide_drive_t *drive)
 {
 	byte dma_stat = inb(HWIF(drive)->dma_base+2);
 
@@ -522,30 +520,6 @@
 		return WAIT_CMD;
 	return 0;
 }
-#else /* CONFIG_BLK_DEV_IDEDMA_TIMEOUT */
-static ide_startstop_t ide_dma_timeout_revovery (ide_drive_t *drive)
-{
-	ide_hwgroup_t *hwgroup	= HWGROUP(drive);
-	ide_hwif_t *hwif	= HWIF(drive);
-	int enable_dma		= drive->using_dma;
-	unsigned long flags;
-	ide_startstop_t startstop;
-
-	spin_lock_irqsave(&ide_lock, flags);
-	hwgroup->handler = NULL;
-	del_timer(&hwgroup->timer);
-	spin_unlock_irqrestore(&ide_lock, flags);
-
-	drive->waiting_for_dma = 0;
-
-	startstop = ide_do_reset(drive);
-
-	if ((enable_dma) && !(drive->using_dma))
-		(void) hwif->dmaproc(ide_dma_on, drive);
-
-	return startstop;
-}
-#endif /* CONFIG_BLK_DEV_IDEDMA_TIMEOUT */
 
 static void ide_toggle_bounce(ide_drive_t *drive, int on)
 {
@@ -614,11 +588,7 @@
 			drive->waiting_for_dma = 1;
 			if (drive->type != ATA_DISK)
 				return 0;
-#ifdef CONFIG_BLK_DEV_IDEDMA_TIMEOUT
-			ide_set_handler(drive, &ide_dma_intr, 2*WAIT_CMD, NULL);	/* issue cmd to drive */
-#else
 			ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, dma_timer_expiry);	/* issue cmd to drive */
-#endif
 			if ((HWGROUP(drive)->rq->flags & REQ_DRIVE_TASKFILE) &&
 			    (drive->addressing == 1)) {
 				ide_task_t *args = HWGROUP(drive)->rq->special;
@@ -659,41 +629,8 @@
 		case ide_dma_verbose:
 			return report_drive_dmaing(drive);
 		case ide_dma_timeout:
-			// FIXME: Many IDE chipsets do not permit command file register access
-			// FIXME: while the bus-master function is still active.
-			// FIXME: To prevent deadlock with those chipsets, we must be extremely
-			// FIXME: careful here (and in ide_intr() as well) to NOT access any
-			// FIXME: registers from the 0x1Fx/0x17x sets before terminating the
-			// FIXME: bus-master operation via the bus-master control reg.
-			// FIXME: Otherwise, chipset deadlock will occur, and some systems will
-			// FIXME: lock up completely!!
-#ifdef CONFIG_BLK_DEV_IDEDMA_TIMEOUT
-			/*
-			 * Have to issue an abort and requeue the request
-			 * DMA engine got turned off by a goofy ASIC, and
-			 * we have to clean up the mess, and here is as good
-			 * as any.  Do it globally for all chipsets.
-			 */
-			outb(0x00, dma_base);		/* stop DMA */
-			dma_stat = inb(dma_base+2);	/* get DMA status */
-			outb(dma_stat|6, dma_base+2);	/* clear the INTR & ERROR bits */
-			printk("%s: %s: Lets do it again!" \
-				"stat = 0x%02x, dma_stat = 0x%02x\n",
-				drive->name, ide_dmafunc_verbose(func),
-				GET_STAT(), dma_stat);
-
-			if (dma_stat & 0xF0)
-				return ide_dma_timeout_revovery(drive);
-
-			printk("%s: %s: (restart_request) Lets do it again!" \
-				"stat = 0x%02x, dma_stat = 0x%02x\n",
-				drive->name, ide_dmafunc_verbose(func),
-				GET_STAT(), dma_stat);
-
-			return restart_request(drive);  // BUG: return types do not match!!
-//#else
-//			return HWGROUP(drive)->handler(drive);
-#endif /* CONFIG_BLK_DEV_IDEDMA_TIMEOUT */
+			printk("ide_dmaproc: DMA timeout occured!\n");
+			return 1;
 		case ide_dma_retune:
 		case ide_dma_lostirq:
 			printk("ide_dmaproc: chipset supported %s func only: %d\n", ide_dmafunc_verbose(func),  func);
@@ -707,8 +644,11 @@
 /*
  * Needed for allowing full modular support of ide-driver
  */
-int ide_release_dma (ide_hwif_t *hwif)
+void ide_release_dma(ide_hwif_t *hwif)
 {
+	if (!hwif->dma_base)
+		return;
+
 	if (hwif->dmatable_cpu) {
 		pci_free_consistent(hwif->pci_dev,
 				    PRD_ENTRIES * PRD_BYTES,
@@ -723,7 +663,7 @@
 	if ((hwif->dma_extra) && (hwif->channel == 0))
 		release_region((hwif->dma_base + 16), hwif->dma_extra);
 	release_region(hwif->dma_base, 8);
-	return 1;
+	hwif->dma_base = 0;
 }
 
 /*
diff -Nru a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c
--- a/drivers/ide/ide-floppy.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/ide-floppy.c	Fri Mar 15 17:51:02 2002
@@ -931,7 +931,7 @@
 			rq->errors++;
 			if (pc->c[0] == IDEFLOPPY_REQUEST_SENSE_CMD) {
 				printk (KERN_ERR "ide-floppy: I/O error in request sense command\n");
-				return ide_do_reset (drive);
+				return ide_stopped;
 			}
 			idefloppy_retry_pc (drive);				/* Retry operation */
 			return ide_stopped; /* queued, but not started */
@@ -945,8 +945,8 @@
 #ifdef CONFIG_BLK_DEV_IDEDMA
 	if (test_and_clear_bit (PC_DMA_IN_PROGRESS, &pc->flags)) {
 		printk (KERN_ERR "ide-floppy: The floppy wants to issue more interrupts in DMA mode\n");
-		(void) HWIF(drive)->dmaproc(ide_dma_off, drive);
-		return ide_do_reset (drive);
+		HWIF(drive)->dmaproc(ide_dma_off, drive);
+		return ide_stopped;
 	}
 #endif /* CONFIG_BLK_DEV_IDEDMA */
 	bcount.b.high=IN_BYTE (IDE_BCOUNTH_REG);			/* Get the number of bytes to transfer */
@@ -955,12 +955,12 @@
 
 	if (ireason.b.cod) {
 		printk (KERN_ERR "ide-floppy: CoD != 0 in idefloppy_pc_intr\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	if (ireason.b.io == test_bit (PC_WRITING, &pc->flags)) {	/* Hopefully, we will never get here */
 		printk (KERN_ERR "ide-floppy: We wanted to %s, ", ireason.b.io ? "Write":"Read");
 		printk (KERN_ERR "but the floppy wants us to %s !\n",ireason.b.io ? "Read":"Write");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	if (!test_bit (PC_WRITING, &pc->flags)) {			/* Reading - Check that we have enough space */
 		temp = pc->actually_transferred + bcount.all;
@@ -1012,7 +1012,7 @@
 	ireason.all=IN_BYTE (IDE_IREASON_REG);
 	if (!ireason.b.cod || ireason.b.io) {
 		printk (KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while issuing a packet command\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	ide_set_handler (drive, &idefloppy_pc_intr, IDEFLOPPY_WAIT_CMD, NULL);	/* Set the interrupt routine */
 	atapi_output_bytes (drive, floppy->pc->c, 12); /* Send the actual packet */
@@ -1053,7 +1053,7 @@
 	ireason.all=IN_BYTE (IDE_IREASON_REG);
 	if (!ireason.b.cod || ireason.b.io) {
 		printk (KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while issuing a packet command\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	/* 
 	 * The following delay solves a problem with ATAPI Zip 100 drives where the
diff -Nru a/drivers/ide/ide-m8xx.c b/drivers/ide/ide-m8xx.c
--- a/drivers/ide/ide-m8xx.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/ide-m8xx.c	Fri Mar 15 17:51:03 2002
@@ -37,7 +37,8 @@
 #include <asm/machdep.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
+
 static int identify  (volatile unsigned char *p);
 static void print_fixed (volatile unsigned char *p);
 static void print_funcid (int func);
@@ -89,6 +90,12 @@
 #endif	/* IDE0_BASE_OFFSET */
 };
 
+typedef struct ide_pio_timings_s {
+	int	setup_time;	/* Address setup (ns) minimum */
+	int	active_time;	/* Active pulse (ns) minimum */
+	int	cycle_time;	/* Cycle time (ns) minimum = (setup + active + recovery) */
+} ide_pio_timings_t;
+
 ide_pio_timings_t ide_pio_clocks[6];
 int hold_time[6] =  {30, 20, 15, 10, 10, 10 };   /* PIO Mode 5 with IORDY (nonstandard) */
 
@@ -222,19 +229,19 @@
 		/* Compute clock cycles for PIO timings */
 		for (i=0; i<6; ++i) {
 			bd_t	*binfo = (bd_t *)__res;
+			struct ata_timing *t;
+
+			t = ata_timing_data(i + XFER_PIO_0);
 
 			hold_time[i]   =
 				PCMCIA_MK_CLKS (hold_time[i],
 						binfo->bi_busfreq);
 			ide_pio_clocks[i].setup_time  =
-				PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
-						binfo->bi_busfreq);
+				PCMCIA_MK_CLKS (t->setup, binfo->bi_busfreq);
 			ide_pio_clocks[i].active_time =
-				PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
-						binfo->bi_busfreq);
+				PCMCIA_MK_CLKS (t->active, binfo->bi_busfreq);
 			ide_pio_clocks[i].cycle_time  =
-				PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
-						binfo->bi_busfreq);
+				PCMCIA_MK_CLKS (t->cycle, binfo->bi_busfreq);
 #if 0
 			printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
 				i,
@@ -242,10 +249,7 @@
 				ide_pio_clocks[i].active_time,
 				ide_pio_clocks[i].hold_time,
 				ide_pio_clocks[i].cycle_time,
-				ide_pio_timings[i].setup_time,
-				ide_pio_timings[i].active_time,
-				ide_pio_timings[i].hold_time,
-				ide_pio_timings[i].cycle_time);
+				t->setup, t->active, hold_time[i], t->cycle);
 #endif
 		}
 	}
@@ -429,13 +433,13 @@
 static void
 m8xx_ide_tuneproc(ide_drive_t *drive, byte pio)
 {
-	ide_pio_data_t d;
 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
 	volatile pcmconf8xx_t	*pcmp;
 	ulong timing, mask, reg;
 #endif
 
-	pio = ide_get_best_pio_mode(drive, pio, 4, &d);
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
 #if 1
 	printk("%s[%d] %s: best PIO mode: %d\n",
diff -Nru a/drivers/ide/ide-pci.c b/drivers/ide/ide-pci.c
--- a/drivers/ide/ide-pci.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/ide-pci.c	Fri Mar 15 17:51:03 2002
@@ -6,15 +6,8 @@
  */
 
 /*
- *  This module provides support for automatic detection and
- *  configuration of all PCI IDE interfaces present in a system.
- */
-
-/*
- * Chipsets that are on the IDE_IGNORE list because of problems of not being
- * set at compile time.
- *
- * CONFIG_BLK_DEV_PDC202XX
+ *  This module provides support for automatic detection and configuration of
+ *  all PCI ATA host chip chanells interfaces present in a system.
  */
 
 #include <linux/config.h>
@@ -34,7 +27,14 @@
 #define PCI_VENDOR_ID_HINT 0x3388
 #define PCI_DEVICE_ID_HINT 0x8013
 
-#define	IDE_IGNORE	((void *)-1)
+/*
+ * Some combi chips, which can be used on the PCI bus or the VL bus can be in
+ * some systems acessed either through the PCI config space or through the
+ * hosts IO bus.  If the corresponding initialization driver is using the host
+ * IO space to deal with them please define the following.
+ */
+
+#define	ATA_PCI_IGNORE	((void *)-1)
 #define IDE_NO_DRIVER	((void *)-2)
 
 #ifdef CONFIG_BLK_DEV_AEC62XX
@@ -284,10 +284,11 @@
 	{PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5530_IDE, pci_init_cs5530, NULL, ide_init_cs5530, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, ATA_F_DMA },
 #endif
 #ifdef CONFIG_BLK_DEV_AMD74XX
-	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, NULL, NULL, NULL, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
+	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
 	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
 	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
-	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7441, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
+	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
+	{PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, pci_init_amd74xx, ata66_amd74xx, ide_init_amd74xx, ide_dmacapable_amd74xx, {{0x40,0x01,0x01}, {0x40,0x02,0x02}}, ON_BOARD, 0, 0 },
 #endif
 #ifdef CONFIG_BLK_DEV_PDC_ADMA
 	{PCI_VENDOR_ID_PDC, PCI_DEVICE_ID_PDC_1841, pci_init_pdcadma, ata66_pdcadma, ide_init_pdcadma, ide_dmacapable_pdcadma, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, OFF_BOARD, 0, ATA_F_NODMA },
@@ -306,7 +307,7 @@
 	 * but which still need some generic quirk handling.
 	 */
 	{PCI_VENDOR_ID_PCTECH, PCI_DEVICE_ID_PCTECH_SAMURAI_IDE, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
-	{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640, NULL, NULL, IDE_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
+	{PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_640, NULL, NULL, ATA_PCI_IGNORE, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
 	{PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87410, NULL, NULL, NULL, NULL, {{0x43,0x08,0x08}, {0x47,0x08,0x08}}, ON_BOARD, 0, 0 },
 	{PCI_VENDOR_ID_HINT, PCI_DEVICE_ID_HINT, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
 	{PCI_VENDOR_ID_HOLTEK, PCI_DEVICE_ID_HOLTEK_6565, NULL, NULL, NULL, NULL, {{0x00,0x00,0x00}, {0x00,0x00,0x00}}, ON_BOARD, 0, 0 },
@@ -883,11 +884,11 @@
  * This finds all PCI IDE controllers and calls appropriate initialization
  * functions for them.
  */
-static void __init ide_scan_pcidev(struct pci_dev *dev)
+static void __init scan_pcidev(struct pci_dev *dev)
 {
 	unsigned short vendor;
 	unsigned short device;
-	ide_pci_device_t	*d;
+	ide_pci_device_t *d;
 
 	vendor = dev->vendor;
 	device = dev->device;
@@ -898,7 +899,7 @@
 	while (d->vendor && !(d->vendor == vendor && d->device == device))
 		++d;
 
-	if (d->init_hwif == IDE_IGNORE)
+	if (d->init_hwif == ATA_PCI_IGNORE)
 		printk("%s: has been ignored by PCI bus scan\n", dev->name);
 	else if ((d->vendor == PCI_VENDOR_ID_OPTI && d->device == PCI_DEVICE_ID_OPTI_82C558) && !(PCI_FUNC(dev->devfn) & 1))
 		return;
@@ -922,17 +923,17 @@
 	}
 }
 
-void __init ide_scan_pcibus (int scan_direction)
+void __init ide_scan_pcibus(int scan_direction)
 {
 	struct pci_dev *dev;
 
 	if (!scan_direction) {
 		pci_for_each_dev(dev) {
-			ide_scan_pcidev(dev);
+			scan_pcidev(dev);
 		}
 	} else {
 		pci_for_each_dev_reverse(dev) {
-			ide_scan_pcidev(dev);
+			scan_pcidev(dev);
 		}
 	}
 }
diff -Nru a/drivers/ide/ide-pmac.c b/drivers/ide/ide-pmac.c
--- a/drivers/ide/ide-pmac.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/ide-pmac.c	Fri Mar 15 17:51:03 2002
@@ -36,7 +36,7 @@
 #include <linux/pmu.h>
 #include <asm/irq.h>
 #endif
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 extern char *ide_dmafunc_verbose(ide_dma_action_t dmafunc);
 
@@ -274,7 +274,7 @@
 		printk(KERN_ERR "pmac_ide_do_setfeature disk not ready after SET_FEATURE !\n");
 out:
 	restore_flags(flags);
-	
+
 	return result;
 }
 
@@ -282,34 +282,40 @@
 static void
 pmac_ide_tuneproc(ide_drive_t *drive, byte pio)
 {
-	ide_pio_data_t d;
+	struct ata_timing *t;
 	int i;
 	u32 *timings;
 	int accessTicks, recTicks;
-	
+
 	i = pmac_ide_find(drive);
 	if (i < 0)
 		return;
-		
-	pio = ide_get_best_pio_mode(drive, pio, 4, &d);
-	accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
+
+	if (pio = 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		pio = XFER_PIO_0 + min_t(byte, pio, 4);
+
+	t = ata_timing_data(pio);
+
+	accessTicks = SYSCLK_TICKS(t->active);
 	if (drive->select.all & 0x10)
 		timings = &pmac_ide[i].timings[1];
 	else
 		timings = &pmac_ide[i].timings[0];
-	
+
 	if (pmac_ide[i].kind == controller_kl_ata4) {
 		/* The "ata-4" IDE controller of Core99 machines */
-		accessTicks = SYSCLK_TICKS_UDMA(ide_pio_timings[pio].active_time * 1000);
-		recTicks = SYSCLK_TICKS_UDMA(d.cycle_time * 1000) - accessTicks;
+		accessTicks = SYSCLK_TICKS_UDMA(t->active * 1000);
+		recTicks = SYSCLK_TICKS_UDMA(t->cycle * 1000) - accessTicks;
 
 		*timings = ((*timings) & 0x1FFFFFC00) | accessTicks | (recTicks << 5);
 	} else {
 		/* The old "ata-3" IDE controller */
-		accessTicks = SYSCLK_TICKS(ide_pio_timings[pio].active_time);
+		accessTicks = SYSCLK_TICKS(t->active);
 		if (accessTicks < 4)
 			accessTicks = 4;
-		recTicks = SYSCLK_TICKS(d.cycle_time) - accessTicks - 4;
+		recTicks = SYSCLK_TICKS(t->cycle) - accessTicks - 4;
 		if (recTicks < 1)
 			recTicks = 1;
 	
diff -Nru a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c
--- a/drivers/ide/ide-probe.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/ide/ide-probe.c	Fri Mar 15 17:51:00 2002
@@ -575,19 +575,17 @@
 static void ide_init_queue(ide_drive_t *drive)
 {
 	request_queue_t *q = &drive->queue;
-	int max_sectors;
-#ifdef CONFIG_BLK_DEV_PDC4030
-	int is_pdc4030_chipset = (HWIF(drive)->chipset == ide_pdc4030);
-#else
-	const int is_pdc4030_chipset = 0;
-#endif
+	int max_sectors = 255;
 
 	q->queuedata = HWGROUP(drive);
 	blk_init_queue(q, do_ide_request, &ide_lock);
 	blk_queue_segment_boundary(q, 0xffff);
 
 	/* IDE can do up to 128K per request, pdc4030 needs smaller limit */
-	max_sectors = (is_pdc4030_chipset ? 127 : 255);
+#ifdef CONFIG_BLK_DEV_PDC4030
+	if (HWIF(drive)->chipset == ide_pdc4030)
+		max_sectors = 127;
+#endif
 	blk_queue_max_sectors(q, max_sectors);
 
 	/* IDE DMA can do PRD_ENTRIES number of segments. */
diff -Nru a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c
--- a/drivers/ide/ide-tape.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/ide-tape.c	Fri Mar 15 17:51:01 2002
@@ -2108,7 +2108,7 @@
 #endif /* IDETAPE_DEBUG_LOG */
 			if (pc->c[0] == IDETAPE_REQUEST_SENSE_CMD) {
 				printk (KERN_ERR "ide-tape: I/O error in request sense command\n");
-				return ide_do_reset (drive);
+				return ide_stopped;
 			}
 #if IDETAPE_DEBUG_LOG
 			if (tape->debug_level >= 1)
@@ -2132,8 +2132,8 @@
 	if (test_and_clear_bit (PC_DMA_IN_PROGRESS, &pc->flags)) {
 		printk (KERN_ERR "ide-tape: The tape wants to issue more interrupts in DMA mode\n");
 		printk (KERN_ERR "ide-tape: DMA disabled, reverting to PIO\n");
-		(void) HWIF(drive)->dmaproc(ide_dma_off, drive);
-		return ide_do_reset (drive);
+		HWIF(drive)->dmaproc(ide_dma_off, drive);
+		return ide_stopped;
 	}
 #endif /* CONFIG_BLK_DEV_IDEDMA */
 	bcount.b.high = IN_BYTE (IDE_BCOUNTH_REG);			/* Get the number of bytes to transfer */
@@ -2142,12 +2142,12 @@
 
 	if (ireason.b.cod) {
 		printk (KERN_ERR "ide-tape: CoD != 0 in idetape_pc_intr\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	if (ireason.b.io == test_bit (PC_WRITING, &pc->flags)) {	/* Hopefully, we will never get here */
 		printk (KERN_ERR "ide-tape: We wanted to %s, ", ireason.b.io ? "Write":"Read");
 		printk (KERN_ERR "ide-tape: but the tape wants us to %s !\n",ireason.b.io ? "Read":"Write");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	if (!test_bit (PC_WRITING, &pc->flags)) {			/* Reading - Check that we have enough space */
 		temp = pc->actually_transferred + bcount.all;
@@ -2252,7 +2252,7 @@
 	}
 	if (!ireason.b.cod || ireason.b.io) {
 		printk (KERN_ERR "ide-tape: (IO,CoD) != (0,1) while issuing a packet command\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	tape->cmd_start_time = jiffies;
 	ide_set_handler(drive, &idetape_pc_intr, IDETAPE_WAIT_CMD, NULL);	/* Set the interrupt routine */
@@ -2725,7 +2725,7 @@
 				idetape_media_access_finished (drive);
 				return ide_stopped;
 			} else {
-				return ide_do_reset (drive);
+				return ide_stopped;
 			}
 		} else if (jiffies - tape->dsc_polling_start > IDETAPE_DSC_MA_THRESHOLD)
 			tape->dsc_polling_frequency = IDETAPE_DSC_MA_SLOW;
diff -Nru a/drivers/ide/ide-timing.h b/drivers/ide/ide-timing.h
--- a/drivers/ide/ide-timing.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,281 +0,0 @@
-#ifndef _IDE_TIMING_H
-#define _IDE_TIMING_H
-
-/*
- * $Id: ide-timing.h,v 1.6 2001/12/23 22:47:56 vojtech Exp $
- *
- *  Copyright (c) 1999-2001 Vojtech Pavlik
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- * Should you need to contact me, the author, you can do so either by
- * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
- * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
- */
-
-#include <linux/hdreg.h>
-
-#define XFER_PIO_5		0x0d
-#define XFER_UDMA_SLOW		0x4f
-
-struct ide_timing {
-	short mode;
-	short setup;	/* t1 */
-	short act8b;	/* t2 for 8-bit io */
-	short rec8b;	/* t2i for 8-bit io */
-	short cyc8b;	/* t0 for 8-bit io */
-	short active;	/* t2 or tD */
-	short recover;	/* t2i or tK */
-	short cycle;	/* t0 */
-	short udma;	/* t2CYCTYP/2 */
-};
-
-/*
- * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
- * These were taken from ATA/ATAPI-6 standard, rev 0a, except
- * for PIO 5, which is a nonstandard extension and UDMA6, which
- * is currently supported only by Maxtor drives. 
- */
-
-static struct ide_timing ide_timing[] = {
-
-	{ XFER_UDMA_6,     0,   0,   0,   0,   0,   0,   0,  15 },
-	{ XFER_UDMA_5,     0,   0,   0,   0,   0,   0,   0,  20 },
-	{ XFER_UDMA_4,     0,   0,   0,   0,   0,   0,   0,  30 },
-	{ XFER_UDMA_3,     0,   0,   0,   0,   0,   0,   0,  45 },
-
-	{ XFER_UDMA_2,     0,   0,   0,   0,   0,   0,   0,  60 },
-	{ XFER_UDMA_1,     0,   0,   0,   0,   0,   0,   0,  80 },
-	{ XFER_UDMA_0,     0,   0,   0,   0,   0,   0,   0, 120 },
-
-	{ XFER_UDMA_SLOW,  0,   0,   0,   0,   0,   0,   0, 150 },
-                                          
-	{ XFER_MW_DMA_2,  25,   0,   0,   0,  70,  25, 120,   0 },
-	{ XFER_MW_DMA_1,  45,   0,   0,   0,  80,  50, 150,   0 },
-	{ XFER_MW_DMA_0,  60,   0,   0,   0, 215, 215, 480,   0 },
-                                          
-	{ XFER_SW_DMA_2,  60,   0,   0,   0, 120, 120, 240,   0 },
-	{ XFER_SW_DMA_1,  90,   0,   0,   0, 240, 240, 480,   0 },
-	{ XFER_SW_DMA_0, 120,   0,   0,   0, 480, 480, 960,   0 },
-
-	{ XFER_PIO_5,     20,  50,  30, 100,  50,  30, 100,   0 },
-	{ XFER_PIO_4,     25,  70,  25, 120,  70,  25, 120,   0 },
-	{ XFER_PIO_3,     30,  80,  70, 180,  80,  70, 180,   0 },
-
-	{ XFER_PIO_2,     30, 290,  40, 330, 100,  90, 240,   0 },
-	{ XFER_PIO_1,     50, 290,  93, 383, 125, 100, 383,   0 },
-	{ XFER_PIO_0,     70, 290, 240, 600, 165, 150, 600,   0 },
-
-	{ XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960,   0 },
-
-	{ -1 }
-};
-
-#define IDE_TIMING_SETUP	0x01
-#define IDE_TIMING_ACT8B	0x02
-#define IDE_TIMING_REC8B	0x04
-#define IDE_TIMING_CYC8B	0x08
-#define IDE_TIMING_8BIT		0x0e
-#define IDE_TIMING_ACTIVE	0x10
-#define IDE_TIMING_RECOVER	0x20
-#define IDE_TIMING_CYCLE	0x40
-#define IDE_TIMING_UDMA		0x80
-#define IDE_TIMING_ALL		0xff
-
-#define MIN(a,b)	((a)<(b)?(a):(b))
-#define MAX(a,b)	((a)>(b)?(a):(b))
-#define FIT(v,min,max)	MAX(MIN(v,max),min)
-#define ENOUGH(v,unit)	(((v)-1)/(unit)+1)
-#define EZ(v,unit)	((v)?ENOUGH(v,unit):0)
-
-#define XFER_MODE	0xf0
-#define XFER_UDMA_133	0x48
-#define XFER_UDMA_100	0x44
-#define XFER_UDMA_66	0x42
-#define XFER_UDMA	0x40
-#define XFER_MWDMA	0x20
-#define XFER_SWDMA	0x10
-#define XFER_EPIO	0x01
-#define XFER_PIO	0x00
-
-static short ide_find_best_mode(ide_drive_t *drive, int map)
-{
-	struct hd_driveid *id = drive->id;
-	short best = 0;
-
-	if (!id)
-		return XFER_PIO_SLOW;
-
-	if ((map & XFER_UDMA) && (id->field_valid & 4)) {	/* Want UDMA and UDMA bitmap valid */
-
-		if ((map & XFER_UDMA_133) == XFER_UDMA_133)
-			if ((best = (id->dma_ultra & 0x0040) ? XFER_UDMA_6 : 0)) return best;
-
-		if ((map & XFER_UDMA_100) == XFER_UDMA_100)
-			if ((best = (id->dma_ultra & 0x0020) ? XFER_UDMA_5 : 0)) return best;
-
-		if ((map & XFER_UDMA_66) == XFER_UDMA_66)
-			if ((best = (id->dma_ultra & 0x0010) ? XFER_UDMA_4 :
-                	    	    (id->dma_ultra & 0x0008) ? XFER_UDMA_3 : 0)) return best;
-
-                if ((best = (id->dma_ultra & 0x0004) ? XFER_UDMA_2 :
-                	    (id->dma_ultra & 0x0002) ? XFER_UDMA_1 :
-                	    (id->dma_ultra & 0x0001) ? XFER_UDMA_0 : 0)) return best;
-	}
-
-	if ((map & XFER_MWDMA) && (id->field_valid & 2)) {	/* Want MWDMA and drive has EIDE fields */
-
-		if ((best = (id->dma_mword & 0x0004) ? XFER_MW_DMA_2 :
-                	    (id->dma_mword & 0x0002) ? XFER_MW_DMA_1 :
-                	    (id->dma_mword & 0x0001) ? XFER_MW_DMA_0 : 0)) return best;
-	}
-
-	if (map & XFER_SWDMA) {					/* Want SWDMA */
-
- 		if (id->field_valid & 2) {			/* EIDE SWDMA */
-
-			if ((best = (id->dma_1word & 0x0004) ? XFER_SW_DMA_2 :
-      				    (id->dma_1word & 0x0002) ? XFER_SW_DMA_1 :
-				    (id->dma_1word & 0x0001) ? XFER_SW_DMA_0 : 0)) return best;
-		}
-
-		if (id->capability & 1) {			/* Pre-EIDE style SWDMA */
-
-			if ((best = (id->tDMA == 2) ? XFER_SW_DMA_2 :
-				    (id->tDMA == 1) ? XFER_SW_DMA_1 :
-				    (id->tDMA == 0) ? XFER_SW_DMA_0 : 0)) return best;
-		}
-	}
-
-
-	if ((map & XFER_EPIO) && (id->field_valid & 2)) {	/* EIDE PIO modes */
-
-		if ((best = (drive->id->eide_pio_modes & 4) ? XFER_PIO_5 :
-			    (drive->id->eide_pio_modes & 2) ? XFER_PIO_4 :
-			    (drive->id->eide_pio_modes & 1) ? XFER_PIO_3 : 0)) return best;
-	}
-	
-	return  (drive->id->tPIO == 2) ? XFER_PIO_2 :
-		(drive->id->tPIO == 1) ? XFER_PIO_1 :
-		(drive->id->tPIO == 0) ? XFER_PIO_0 : XFER_PIO_SLOW;
-}
-
-static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, int T, int UT)
-{
-	q->setup   = EZ(t->setup   * 1000,  T);
-	q->act8b   = EZ(t->act8b   * 1000,  T);
-	q->rec8b   = EZ(t->rec8b   * 1000,  T);
-	q->cyc8b   = EZ(t->cyc8b   * 1000,  T);
-	q->active  = EZ(t->active  * 1000,  T);
-	q->recover = EZ(t->recover * 1000,  T);
-	q->cycle   = EZ(t->cycle   * 1000,  T);
-	q->udma    = EZ(t->udma    * 1000, UT);
-}
-
-static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, struct ide_timing *m, unsigned int what)
-{
-	if (what & IDE_TIMING_SETUP  ) m->setup   = MAX(a->setup,   b->setup);
-	if (what & IDE_TIMING_ACT8B  ) m->act8b   = MAX(a->act8b,   b->act8b);
-	if (what & IDE_TIMING_REC8B  ) m->rec8b   = MAX(a->rec8b,   b->rec8b);
-	if (what & IDE_TIMING_CYC8B  ) m->cyc8b   = MAX(a->cyc8b,   b->cyc8b);
-	if (what & IDE_TIMING_ACTIVE ) m->active  = MAX(a->active,  b->active);
-	if (what & IDE_TIMING_RECOVER) m->recover = MAX(a->recover, b->recover);
-	if (what & IDE_TIMING_CYCLE  ) m->cycle   = MAX(a->cycle,   b->cycle);
-	if (what & IDE_TIMING_UDMA   ) m->udma    = MAX(a->udma,    b->udma);
-}
-
-static struct ide_timing* ide_timing_find_mode(short speed)
-{
-	struct ide_timing *t;
-
-	for (t = ide_timing; t->mode != speed; t++)
-		if (t->mode < 0)
-			return NULL;
-	return t; 
-}
-
-static int ide_timing_compute(ide_drive_t *drive, short speed, struct ide_timing *t, int T, int UT)
-{
-	struct hd_driveid *id = drive->id;
-	struct ide_timing *s, p;
-
-/*
- * Find the mode.
- */
-
-	if (!(s = ide_timing_find_mode(speed)))
-		return -EINVAL;
-
-/*
- * If the drive is an EIDE drive, it can tell us it needs extended
- * PIO/MWDMA cycle timing.
- */
-
-	if (id && id->field_valid & 2) {	/* EIDE drive */
-
-		memset(&p, 0, sizeof(p));
-
-		switch (speed & XFER_MODE) {
-
-			case XFER_PIO:
-				if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
-						    else p.cycle = p.cyc8b = id->eide_pio_iordy;
-				break;
-
-			case XFER_MWDMA:
-				p.cycle = id->eide_dma_min;
-				break;
-		}
-
-		ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
-	}
-
-/*
- * Convert the timing to bus clock counts.
- */
-
-	ide_timing_quantize(s, t, T, UT);
-
-/*
- * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
- * and some other commands. We have to ensure that the DMA cycle timing is
- * slower/equal than the fastest PIO timing.
- */
-
-	if ((speed & XFER_MODE) != XFER_PIO) {
-		ide_timing_compute(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO), &p, T, UT);
-		ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
-	}
-
-/*
- * Lenghten active & recovery time so that cycle time is correct.
- */
-
-	if (t->act8b + t->rec8b < t->cyc8b) {
-		t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
-		t->rec8b = t->cyc8b - t->act8b;
-	}
-
-	if (t->active + t->recover < t->cycle) {
-		t->active += (t->cycle - (t->active + t->recover)) / 2;
-		t->recover = t->cycle - t->active;
-	}
-
-	return 0;
-}
-
-#endif
diff -Nru a/drivers/ide/ide.c b/drivers/ide/ide.c
--- a/drivers/ide/ide.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/ide/ide.c	Fri Mar 15 17:51:03 2002
@@ -149,7 +149,7 @@
 #include <asm/io.h>
 #include <asm/bitops.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /*
  * Those will be moved into separate header files eventually.
@@ -194,95 +194,6 @@
 extern void pnpide_init(int);
 #endif
 
-/*
- * Constant tables for PIO mode programming:
- */
-const ide_pio_timings_t ide_pio_timings[6] = {
-	{ 70,	165,	600 },	/* PIO Mode 0 */
-	{ 50,	125,	383 },	/* PIO Mode 1 */
-	{ 30,	100,	240 },	/* PIO Mode 2 */
-	{ 30,	80,	180 },	/* PIO Mode 3 with IORDY */
-	{ 25,	70,	120 },	/* PIO Mode 4 with IORDY */
-	{ 20,	50,	100 }	/* PIO Mode 5 with IORDY (nonstandard) */
-};
-
-/*
- * Black list. Some drives incorrectly report their maximal PIO mode,
- * at least in respect to CMD640. Here we keep info on some known drives.
- */
-static struct ide_pio_info {
-	const char	*name;
-	int		pio;
-} ide_pio_blacklist[] = {
-/*	{ "Conner Peripherals 1275MB - CFS1275A", 4 }, */
-	{ "Conner Peripherals 540MB - CFS540A", 3 },
-
-	{ "WDC AC2700",  3 },
-	{ "WDC AC2540",  3 },
-	{ "WDC AC2420",  3 },
-	{ "WDC AC2340",  3 },
-	{ "WDC AC2250",  0 },
-	{ "WDC AC2200",  0 },
-	{ "WDC AC21200", 4 },
-	{ "WDC AC2120",  0 },
-	{ "WDC AC2850",  3 },
-	{ "WDC AC1270",  3 },
-	{ "WDC AC1170",  1 },
-	{ "WDC AC1210",  1 },
-	{ "WDC AC280",   0 },
-/*	{ "WDC AC21000", 4 }, */
-	{ "WDC AC31000", 3 },
-	{ "WDC AC31200", 3 },
-/*	{ "WDC AC31600", 4 }, */
-
-	{ "Maxtor 7131 AT", 1 },
-	{ "Maxtor 7171 AT", 1 },
-	{ "Maxtor 7213 AT", 1 },
-	{ "Maxtor 7245 AT", 1 },
-	{ "Maxtor 7345 AT", 1 },
-	{ "Maxtor 7546 AT", 3 },
-	{ "Maxtor 7540 AV", 3 },
-
-	{ "SAMSUNG SHD-3121A", 1 },
-	{ "SAMSUNG SHD-3122A", 1 },
-	{ "SAMSUNG SHD-3172A", 1 },
-
-/*	{ "ST51080A", 4 },
- *	{ "ST51270A", 4 },
- *	{ "ST31220A", 4 },
- *	{ "ST31640A", 4 },
- *	{ "ST32140A", 4 },
- *	{ "ST3780A",  4 },
- */
-	{ "ST5660A",  3 },
-	{ "ST3660A",  3 },
-	{ "ST3630A",  3 },
-	{ "ST3655A",  3 },
-	{ "ST3391A",  3 },
-	{ "ST3390A",  1 },
-	{ "ST3600A",  1 },
-	{ "ST3290A",  0 },
-	{ "ST3144A",  0 },
-	{ "ST3491A",  1 },	/* reports 3, should be 1 or 2 (depending on
-				 * drive) according to Seagates FIND-ATA program */
-
-	{ "QUANTUM ELS127A", 0 },
-	{ "QUANTUM ELS170A", 0 },
-	{ "QUANTUM LPS240A", 0 },
-	{ "QUANTUM LPS210A", 3 },
-	{ "QUANTUM LPS270A", 3 },
-	{ "QUANTUM LPS365A", 3 },
-	{ "QUANTUM LPS540A", 3 },
-	{ "QUANTUM LIGHTNING 540A", 3 },
-	{ "QUANTUM LIGHTNING 730A", 3 },
-
-        { "QUANTUM FIREBALL_540", 3 }, /* Older Quantum Fireballs don't work */
-        { "QUANTUM FIREBALL_640", 3 },
-        { "QUANTUM FIREBALL_1080", 3 },
-        { "QUANTUM FIREBALL_1280", 3 },
-	{ NULL,	0 }
-};
-
 /* default maximum number of failures */
 #define IDE_DEFAULT_MAX_FAILURES	1
 
@@ -314,106 +225,6 @@
  */
 ide_hwif_t ide_hwifs[MAX_HWIFS];	/* master data repository */
 
-
-/*
- * This routine searches the ide_pio_blacklist for an entry
- * matching the start/whole of the supplied model name.
- *
- * Returns -1 if no match found.
- * Otherwise returns the recommended PIO mode from ide_pio_blacklist[].
- */
-int ide_scan_pio_blacklist (char *model)
-{
-	struct ide_pio_info *p;
-
-	for (p = ide_pio_blacklist; p->name != NULL; p++) {
-		if (strncmp(p->name, model, strlen(p->name)) == 0)
-			return p->pio;
-	}
-	return -1;
-}
-
-/*
- * This routine returns the recommended PIO settings for a given drive,
- * based on the drive->id information and the ide_pio_blacklist[].
- * This is used by most chipset support modules when "auto-tuning".
- */
-
-/*
- * Drive PIO mode auto selection
- */
-byte ide_get_best_pio_mode (ide_drive_t *drive, byte mode_wanted, byte max_mode, ide_pio_data_t *d)
-{
-	int pio_mode;
-	int cycle_time = 0;
-	int use_iordy = 0;
-	struct hd_driveid* id = drive->id;
-	int overridden  = 0;
-	int blacklisted = 0;
-
-	if (mode_wanted != 255) {
-		pio_mode = mode_wanted;
-	} else if (!drive->id) {
-		pio_mode = 0;
-	} else if ((pio_mode = ide_scan_pio_blacklist(id->model)) != -1) {
-		overridden = 1;
-		blacklisted = 1;
-		use_iordy = (pio_mode > 2);
-	} else {
-		pio_mode = id->tPIO;
-		if (pio_mode > 2) {	/* 2 is maximum allowed tPIO value */
-			pio_mode = 2;
-			overridden = 1;
-		}
-		if (id->field_valid & 2) {	  /* drive implements ATA2? */
-			if (id->capability & 8) { /* drive supports use_iordy? */
-				use_iordy = 1;
-				cycle_time = id->eide_pio_iordy;
-				if (id->eide_pio_modes & 7) {
-					overridden = 0;
-					if (id->eide_pio_modes & 4)
-						pio_mode = 5;
-					else if (id->eide_pio_modes & 2)
-						pio_mode = 4;
-					else
-						pio_mode = 3;
-				}
-			} else {
-				cycle_time = id->eide_pio;
-			}
-		}
-
-#if 0
-		if (drive->id->major_rev_num & 0x0004) printk("ATA-2 ");
-#endif
-
-		/*
-		 * Conservative "downgrade" for all pre-ATA2 drives
-		 */
-		if (pio_mode && pio_mode < 4) {
-			pio_mode--;
-			overridden = 1;
-#if 0
-			use_iordy = (pio_mode > 2);
-#endif
-			if (cycle_time && cycle_time < ide_pio_timings[pio_mode].cycle_time)
-				cycle_time = 0; /* use standard timing */
-		}
-	}
-	if (pio_mode > max_mode) {
-		pio_mode = max_mode;
-		cycle_time = 0;
-	}
-	if (d) {
-		d->pio_mode = pio_mode;
-		d->cycle_time = cycle_time ? cycle_time : ide_pio_timings[pio_mode].cycle_time;
-		d->use_iordy = use_iordy;
-		d->overridden = overridden;
-		d->blacklisted = blacklisted;
-	}
-	return pio_mode;
-}
-
 #if (DISK_RECOVERY_TIME > 0)
 /*
  * For really screwed hardware (hey, at least it *can* be used with Linux)
@@ -445,7 +256,7 @@
 /*
  * Do not even *think* about calling this!
  */
-static void init_hwif_data (unsigned int index)
+static void init_hwif_data(ide_hwif_t *hwif, unsigned int index)
 {
 	static const byte ide_major[] = {
 		IDE0_MAJOR, IDE1_MAJOR, IDE2_MAJOR, IDE3_MAJOR, IDE4_MAJOR,
@@ -454,7 +265,6 @@
 
 	unsigned int unit;
 	hw_regs_t hw;
-	ide_hwif_t *hwif = &ide_hwifs[index];
 
 	/* bulk initialize hwif & drive info with zeros */
 	memset(hwif, 0, sizeof(ide_hwif_t));
@@ -507,7 +317,7 @@
 #define MAGIC_COOKIE 0x12345678
 static void __init init_ide_data (void)
 {
-	unsigned int index;
+	unsigned int h;
 	static unsigned long magic_cookie = MAGIC_COOKIE;
 
 	if (magic_cookie != MAGIC_COOKIE)
@@ -515,8 +325,8 @@
 	magic_cookie = 0;
 
 	/* Initialize all interface structures */
-	for (index = 0; index < MAX_HWIFS; ++index)
-		init_hwif_data(index);
+	for (h = 0; h < MAX_HWIFS; ++h)
+		init_hwif_data(&ide_hwifs[h], h);
 
 	/* Add default hw interfaces */
 	ide_init_default_hwifs();
@@ -885,14 +695,6 @@
 	return ide_started;
 }
 
-/*
- * ide_do_reset() is the entry point to the drive/interface reset code.
- */
-ide_startstop_t ide_do_reset (ide_drive_t *drive)
-{
-	return do_reset1 (drive, 0);
-}
-
 static inline u32 read_24 (ide_drive_t *drive)
 {
 	return  (IN_BYTE(IDE_HCYL_REG)<<16) |
@@ -1116,7 +918,7 @@
 	} else {
 		if ((rq->errors & ERROR_RESET) == ERROR_RESET) {
 			++rq->errors;
-			return ide_do_reset(drive);
+			return do_reset1(drive, 0);
 		}
 		if ((rq->errors & ERROR_RECAL) == ERROR_RECAL)
 			drive->special.b.recalibrate = 1;
@@ -1629,7 +1431,7 @@
  * But note that it can also be invoked as a result of a "sleep" operation
  * triggered by the mod_timer() call in ide_do_request.
  */
-void ide_timer_expiry (unsigned long data)
+void ide_timer_expiry(unsigned long data)
 {
 	ide_hwgroup_t	*hwgroup = (ide_hwgroup_t *) data;
 	ide_handler_t	*handler;
@@ -1667,7 +1469,7 @@
 			if ((expiry = hwgroup->expiry) != NULL) {
 				/* continue */
 				if ((wait = expiry(drive)) != 0) {
-					/* reset timer */
+					/* reengage timer */
 					hwgroup->timer.expires  = jiffies + wait;
 					add_timer(&hwgroup->timer);
 					spin_unlock_irqrestore(&ide_lock, flags);
@@ -1867,15 +1669,15 @@
  * get_info_ptr() returns the (ide_drive_t *) for a given device number.
  * It returns NULL if the given device number does not match any present drives.
  */
-ide_drive_t *get_info_ptr (kdev_t i_rdev)
+ide_drive_t *get_info_ptr(kdev_t i_rdev)
 {
-	int		major = major(i_rdev);
-	unsigned int	h;
+	unsigned int major = major(i_rdev);
+	int h;
 
 	for (h = 0; h < MAX_HWIFS; ++h) {
 		ide_hwif_t  *hwif = &ide_hwifs[h];
 		if (hwif->present && major == hwif->major) {
-			unsigned unit = DEVICE_NR(i_rdev);
+			int unit = DEVICE_NR(i_rdev);
 			if (unit < MAX_DRIVES) {
 				ide_drive_t *drive = &hwif->drives[unit];
 				if (drive->present)
@@ -2012,13 +1814,13 @@
 {
 	ide_hwif_t *hwif;
 	ide_drive_t *drive;
-	int index;
-	int unit;
+	int h;
 
-	for (index = 0; index < MAX_HWIFS; ++index) {
-		hwif = &ide_hwifs[index];
+	for (h = 0; h < MAX_HWIFS; ++h) {
+		int unit;
+		hwif = &ide_hwifs[h];
 		for (unit = 0; unit < MAX_DRIVES; ++unit) {
-			drive = &ide_hwifs[index].drives[unit];
+			drive = &ide_hwifs[h].drives[unit];
 			if (drive->revalidate) {
 				drive->revalidate = 0;
 				if (!initializing)
@@ -2164,22 +1966,18 @@
 #endif
 }
 
-void ide_unregister (unsigned int index)
+void ide_unregister(ide_hwif_t *hwif)
 {
 	struct gendisk *gd;
 	ide_drive_t *drive, *d;
-	ide_hwif_t *hwif, *g;
+	ide_hwif_t *g;
 	ide_hwgroup_t *hwgroup;
 	int irq_count = 0, unit, i;
 	unsigned long flags;
 	unsigned int p, minor;
 	ide_hwif_t old_hwif;
 
-	if (index >= MAX_HWIFS)
-		return;
-	save_flags(flags);	/* all CPUs */
-	cli();			/* all CPUs */
-	hwif = &ide_hwifs[index];
+	spin_lock_irqsave(&ide_lock, flags);
 	if (!hwif->present)
 		goto abort;
 	put_device(&hwif->device);
@@ -2202,7 +2000,7 @@
 	/*
 	 * All clear?  Then blow away the buffer cache
 	 */
-	sti();
+	spin_unlock_irqrestore(&ide_lock, flags);
 	for (unit = 0; unit < MAX_DRIVES; ++unit) {
 		drive = &hwif->drives[unit];
 		if (!drive->present)
@@ -2214,11 +2012,11 @@
 				invalidate_device(devp, 0);
 			}
 		}
+	}
 #ifdef CONFIG_PROC_FS
-		destroy_proc_ide_drives(hwif);
+	destroy_proc_ide_drives(hwif);
 #endif
-	}
-	cli();
+	spin_lock_irqsave(&ide_lock, flags);
 	hwgroup = hwif->hwgroup;
 
 	/*
@@ -2271,11 +2069,8 @@
 		hwgroup->hwif = HWIF(hwgroup->drive);
 
 #if defined(CONFIG_BLK_DEV_IDEDMA) && !defined(CONFIG_DMA_NONPCI)
-	if (hwif->dma_base) {
-		(void) ide_release_dma(hwif);
-		hwif->dma_base = 0;
-	}
-#endif /* (CONFIG_BLK_DEV_IDEDMA) && !(CONFIG_DMA_NONPCI) */
+	ide_release_dma(hwif);
+#endif
 
 	/*
 	 * Remove us from the kernel's knowledge
@@ -2297,8 +2092,14 @@
 		kfree(gd);
 		hwif->gd = NULL;
 	}
+
+	/*
+	 * Reinitialize the hwif handler, but preserve any special methods for
+	 * it.
+	 */
+
 	old_hwif		= *hwif;
-	init_hwif_data(index);	/* restore hwif data to pristine status */
+	init_hwif_data(hwif, hwif->index);
 	hwif->hwgroup		= old_hwif.hwgroup;
 	hwif->tuneproc		= old_hwif.tuneproc;
 	hwif->speedproc		= old_hwif.speedproc;
@@ -2329,7 +2130,7 @@
 #endif
 	hwif->straight8		= old_hwif.straight8;
 abort:
-	restore_flags(flags);	/* all CPUs */
+	spin_unlock_irqrestore(&ide_lock, flags);
 }
 
 /*
@@ -2374,28 +2175,27 @@
  */
 int ide_register_hw(hw_regs_t *hw, ide_hwif_t **hwifp)
 {
-	int index, retry = 1;
+	int h, retry = 1;
 	ide_hwif_t *hwif;
 
 	do {
-		for (index = 0; index < MAX_HWIFS; ++index) {
-			hwif = &ide_hwifs[index];
+		for (h = 0; h < MAX_HWIFS; ++h) {
+			hwif = &ide_hwifs[h];
 			if (hwif->hw.io_ports[IDE_DATA_OFFSET] == hw->io_ports[IDE_DATA_OFFSET])
 				goto found;
 		}
-		for (index = 0; index < MAX_HWIFS; ++index) {
-			hwif = &ide_hwifs[index];
+		for (h = 0; h < MAX_HWIFS; ++h) {
+			hwif = &ide_hwifs[h];
 			if ((!hwif->present && !hwif->mate && !initializing) ||
 			    (!hwif->hw.io_ports[IDE_DATA_OFFSET] && initializing))
 				goto found;
 		}
-		for (index = 0; index < MAX_HWIFS; index++)
-			ide_unregister(index);
+		for (h = 0; h < MAX_HWIFS; ++h)
+			ide_unregister(&ide_hwifs[h]);
 	} while (retry--);
 	return -1;
 found:
-	if (hwif->present)
-		ide_unregister(index);
+	ide_unregister(hwif);
 	if (hwif->present)
 		return -1;
 	memcpy(&hwif->hw, hw, sizeof(*hw));
@@ -2415,7 +2215,7 @@
 	if (hwifp)
 		*hwifp = hwif;
 
-	return (initializing || hwif->present) ? index : -1;
+	return (initializing || hwif->present) ? h : -1;
 }
 
 /*
@@ -2756,21 +2556,6 @@
 				return -EACCES;
 			return ide_task_ioctl(drive, inode, file, cmd, arg);
 
-		case HDIO_SCAN_HWIF:
-		{
-			int args[3];
-			if (!capable(CAP_SYS_ADMIN)) return -EACCES;
-			if (copy_from_user(args, (void *)arg, 3 * sizeof(int)))
-				return -EFAULT;
-			if (ide_register(args[0], args[1], args[2]) == -1)
-				return -EIO;
-			return 0;
-		}
-	        case HDIO_UNREGISTER_HWIF:
-			if (!capable(CAP_SYS_ADMIN)) return -EACCES;
-			/* (arg > MAX_HWIFS) checked in function */
-			ide_unregister(arg);
-			return 0;
 		case HDIO_SET_NICE:
 			if (!capable(CAP_SYS_ADMIN)) return -EACCES;
 			if (arg != (arg & ((1 << IDE_NICE_DSC_OVERLAP) | (1 << IDE_NICE_1))))
@@ -2783,27 +2568,6 @@
 			}
 			drive->nice1 = (arg >> IDE_NICE_1) & 1;
 			return 0;
-		case HDIO_DRIVE_RESET:
-		{
-			unsigned long flags;
-			ide_hwgroup_t *hwgroup = HWGROUP(drive);
-
-			if (!capable(CAP_SYS_ADMIN)) return -EACCES;
-#if 1
-			spin_lock_irqsave(&ide_lock, flags);
-			if (hwgroup->handler != NULL) {
-				printk("%s: ide_set_handler: handler not null; %p\n", drive->name, hwgroup->handler);
-				hwgroup->handler(drive);
-				hwgroup->timer.expires = jiffies + 0;;
-				del_timer(&hwgroup->timer);
-			}
-			spin_unlock_irqrestore(&ide_lock, flags);
-#endif
-			ide_do_reset(drive);
-			if (drive->suspend_reset)
-				return ide_revalidate_disk(inode->i_rdev);
-			return 0;
-		}
 		case BLKGETSIZE:
 		case BLKGETSIZE64:
 		case BLKROSET:
@@ -3479,6 +3243,7 @@
 	revalidate:		ide_revalidate_disk
 }};
 
+EXPORT_SYMBOL(ide_fops);
 EXPORT_SYMBOL(ide_hwifs);
 EXPORT_SYMBOL(ide_spin_wait_hwgroup);
 EXPORT_SYMBOL(revalidate_drives);
@@ -3506,7 +3271,6 @@
 EXPORT_SYMBOL(ide_error);
 EXPORT_SYMBOL(ide_fixstring);
 EXPORT_SYMBOL(ide_wait_stat);
-EXPORT_SYMBOL(ide_do_reset);
 EXPORT_SYMBOL(restart_request);
 EXPORT_SYMBOL(ide_init_drive_cmd);
 EXPORT_SYMBOL(ide_do_drive_cmd);
@@ -3584,7 +3348,7 @@
  */
 static int __init ata_module_init(void)
 {
-	int i;
+	int h;
 
 	printk(KERN_INFO "Uniform Multi-Platform E-IDE driver ver.:" VERSION "\n");
 
@@ -3666,7 +3430,7 @@
 	pnpide_init(1);
 #endif
 
-#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULES)
+#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 # if defined(__mc68000__) || defined(CONFIG_APUS)
 	if (ide_hwifs[0].io_ports[IDE_DATA_OFFSET]) {
 		ide_get_lock(&ide_intr_lock, NULL, NULL);/* for atari only */
@@ -3714,8 +3478,8 @@
 
 	initializing = 0;
 
-	for (i = 0; i < MAX_HWIFS; ++i) {
-		ide_hwif_t  *hwif = &ide_hwifs[i];
+	for (h = 0; h < MAX_HWIFS; ++h) {
+		ide_hwif_t  *hwif = &ide_hwifs[h];
 		if (hwif->present)
 			ide_geninit(hwif);
 	}
@@ -3750,21 +3514,17 @@
 
 static void __exit cleanup_ata (void)
 {
-	int index;
+	int h;
 
 	unregister_reboot_notifier(&ide_notifier);
-	for (index = 0; index < MAX_HWIFS; ++index) {
-		ide_unregister(index);
-# if defined(CONFIG_BLK_DEV_IDEDMA) && !defined(CONFIG_DMA_NONPCI)
-		if (ide_hwifs[index].dma_base)
-			ide_release_dma(&ide_hwifs[index]);
-# endif /* (CONFIG_BLK_DEV_IDEDMA) && !(CONFIG_DMA_NONPCI) */
+	for (h = 0; h < MAX_HWIFS; ++h) {
+		ide_unregister(&ide_hwifs[h]);
 	}
 
 # ifdef CONFIG_PROC_FS
 	proc_ide_destroy();
 # endif
-	devfs_unregister (ide_devfs_handle);
+	devfs_unregister(ide_devfs_handle);
 }
 
 module_init(init_ata);
diff -Nru a/drivers/ide/ide_modes.h b/drivers/ide/ide_modes.h
--- a/drivers/ide/ide_modes.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,42 +0,0 @@
-/*
- *  linux/drivers/ide/ide_modes.h
- *
- *  Copyright (C) 1996  Linus Torvalds, Igor Abramov, and Mark Lord
- */
-
-#ifndef _IDE_MODES_H
-#define _IDE_MODES_H
-
-#include <linux/config.h>
-
-/*
- * Shared data/functions for determining best PIO mode for an IDE drive.
- */
-
-#ifdef CONFIG_BLK_DEV_IDE_MODES
-
-/*
- * Standard (generic) timings for PIO modes, from ATA2 specification.
- * These timings are for access to the IDE data port register *only*.
- * Some drives may specify a mode, while also specifying a different
- * value for cycle_time (from drive identification data).
- */
-typedef struct ide_pio_timings_s {
-	int	setup_time;	/* Address setup (ns) minimum */
-	int	active_time;	/* Active pulse (ns) minimum */
-	int	cycle_time;	/* Cycle time (ns) minimum = (setup + active + recovery) */
-} ide_pio_timings_t;
-
-typedef struct ide_pio_data_s {
-	byte pio_mode;
-	byte use_iordy;
-	byte overridden;
-	byte blacklisted;
-	unsigned int cycle_time;
-} ide_pio_data_t;
-
-extern int ide_scan_pio_blacklist (char *model);
-extern byte ide_get_best_pio_mode (ide_drive_t *drive, byte mode_wanted, byte max_mode, ide_pio_data_t *d);
-extern const ide_pio_timings_t ide_pio_timings[6];
-#endif
-#endif
diff -Nru a/drivers/ide/it8172.c b/drivers/ide/it8172.c
--- a/drivers/ide/it8172.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/it8172.c	Fri Mar 15 17:51:01 2002
@@ -41,7 +41,7 @@
 #include <asm/io.h>
 #include <asm/it8172/it8172_int.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /*
  * Prototypes
@@ -64,8 +64,12 @@
     int is_slave	= (&HWIF(drive)->drives[1] == drive);
     int master_port	= 0x40;
     int slave_port      = 0x44;
-    
-    pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
+
+    if (pio == 255)
+	pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
+    else
+       pio = min_t(byte, pio, 4);
+
     pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
     pci_read_config_dword(HWIF(drive)->pci_dev, slave_port, &slave_data);
 
@@ -181,30 +185,12 @@
     return err;
 }
 
-static int it8172_config_drive_for_dma (ide_drive_t *drive)
+static int it8172_config_drive_for_dma(ide_drive_t *drive)
 {
     struct hd_driveid *id = drive->id;
     byte speed;
 
-    if (id->dma_ultra & 0x0010) {
-	speed = XFER_UDMA_2;
-    } else if (id->dma_ultra & 0x0008) {
-	speed = XFER_UDMA_1;
-    } else if (id->dma_ultra & 0x0004) {
-	speed = XFER_UDMA_2;
-    } else if (id->dma_ultra & 0x0002) {
-	speed = XFER_UDMA_1;
-    } else if (id->dma_ultra & 0x0001) {
-	speed = XFER_UDMA_0;
-    } else if (id->dma_mword & 0x0004) {
-	speed = XFER_MW_DMA_2;
-    } else if (id->dma_mword & 0x0002) {
-	speed = XFER_MW_DMA_1;
-    } else if (id->dma_1word & 0x0004) {
-	speed = XFER_SW_DMA_2;
-    } else {
-	speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
-    }
+    speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA | XFER_UDMA);
 
     (void) it8172_tune_chipset(drive, speed);
 
diff -Nru a/drivers/ide/opti621.c b/drivers/ide/opti621.c
--- a/drivers/ide/opti621.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/opti621.c	Fri Mar 15 17:51:01 2002
@@ -97,7 +97,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define OPTI621_MAX_PIO 3
 /* In fact, I do not have any PIO 4 drive
@@ -144,12 +144,16 @@
 	int d;
 	ide_hwif_t *hwif = HWIF(drive);
 
-	drive->drive_data = ide_get_best_pio_mode(drive, pio, OPTI621_MAX_PIO, NULL);
+	if (pio == PIO_DONT_KNOW)
+		drive->drive_data = min(ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0, OPTI621_MAX_PIO);
+	else
+		drive->drive_data = pio;
+
 	for (d = 0; d < 2; ++d) {
 		drive = &hwif->drives[d];
 		if (drive->present) {
 			if (drive->drive_data == PIO_DONT_KNOW)
-				drive->drive_data = ide_get_best_pio_mode(drive, 255, OPTI621_MAX_PIO, NULL);
+				drive->drive_data = min(ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0, OPTI621_MAX_PIO);
 #ifdef OPTI621_DEBUG
 			printk("%s: Selected PIO mode %d\n", drive->name, drive->drive_data);
 #endif
@@ -210,27 +214,31 @@
 static void compute_clocks(int pio, pio_clocks_t *clks)
 {
         if (pio != PIO_NOT_EXIST) {
-        	int adr_setup, data_pls;
-
- 	       	adr_setup = ide_pio_timings[pio].setup_time;
-  	      	data_pls = ide_pio_timings[pio].active_time;
-	  	clks->address_time = cmpt_clk(adr_setup, system_bus_speed);
-	     	clks->data_time = cmpt_clk(data_pls, system_bus_speed);
-     		clks->recovery_time = cmpt_clk(ide_pio_timings[pio].cycle_time
-     			- adr_setup-data_pls, system_bus_speed);
-     		if (clks->address_time<1) clks->address_time = 1;
-     		if (clks->address_time>4) clks->address_time = 4;
-     		if (clks->data_time<1) clks->data_time = 1;
-     		if (clks->data_time>16) clks->data_time = 16;
-     		if (clks->recovery_time<2) clks->recovery_time = 2;
-     		if (clks->recovery_time>17) clks->recovery_time = 17;
+		int adr_setup;
+		int data_pls;
+		struct ata_timing *t;
+
+		t = ata_timing_data(pio);
+
+		adr_setup = t->setup;
+		data_pls = t->active;
+		clks->address_time = cmpt_clk(adr_setup, system_bus_speed);
+		clks->data_time = cmpt_clk(data_pls, system_bus_speed);
+		clks->recovery_time = cmpt_clk(t->cycle
+			- adr_setup-data_pls, system_bus_speed);
+		if (clks->address_time<1) clks->address_time = 1;
+		if (clks->address_time>4) clks->address_time = 4;
+		if (clks->data_time<1) clks->data_time = 1;
+		if (clks->data_time>16) clks->data_time = 16;
+		if (clks->recovery_time<2) clks->recovery_time = 2;
+		if (clks->recovery_time>17) clks->recovery_time = 17;
 	} else {
 		clks->address_time = 1;
 		clks->data_time = 1;
 		clks->recovery_time = 2;
 		/* minimal values */
 	}
- 
+
 }
 
 /* Main tune procedure, called from tuneproc. */
@@ -248,8 +256,8 @@
 
 	/* sets drive->drive_data for both drives */
 	compute_pios(drive, pio);
- 	pio1 = hwif->drives[0].drive_data;
- 	pio2 = hwif->drives[1].drive_data;
+	pio1 = hwif->drives[0].drive_data;
+	pio2 = hwif->drives[1].drive_data;
 
 	compute_clocks(pio1, &first);
 	compute_clocks(pio2, &second);
@@ -273,10 +281,10 @@
 	save_flags(flags);	/* all CPUs */
 	cli();			/* all CPUs */
 
-     	reg_base = hwif->io_ports[IDE_DATA_OFFSET];
+	reg_base = hwif->io_ports[IDE_DATA_OFFSET];
 	outb(0xc0, reg_base+CNTRL_REG);	/* allow Register-B */
 	outb(0xff, reg_base+5);		/* hmm, setupvic.exe does this ;-) */
-	inb(reg_base+CNTRL_REG); 	/* if reads 0xff, adapter not exist? */
+	inb(reg_base+CNTRL_REG);	/* if reads 0xff, adapter not exist? */
 	read_reg(CNTRL_REG);		/* if reads 0xc0, no interface exist? */
 	read_reg(STRAP_REG);		/* read version, probably 0 */
 
@@ -293,8 +301,8 @@
 	write_reg(0x85, CNTRL_REG);	/* use Register-A for drive 0 */
 					/* use Register-B for drive 1 */
 
- 	write_reg(misc, MISC_REG);	/* set address setup, DRDY timings,   */
- 					/*  and read prefetch for both drives */
+	write_reg(misc, MISC_REG);	/* set address setup, DRDY timings,   */
+					/*  and read prefetch for both drives */
 
 	restore_flags(flags);	/* all CPUs */
 }
diff -Nru a/drivers/ide/pdc202xx.c b/drivers/ide/pdc202xx.c
--- a/drivers/ide/pdc202xx.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/ide/pdc202xx.c	Fri Mar 15 17:51:04 2002
@@ -46,7 +46,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define PDC202XX_DEBUG_DRIVE_INFO		0
 #define PDC202XX_DECODE_REGISTER_INFO		0
@@ -681,9 +681,11 @@
 {
 	byte speed = 0x00;
 
-	pio = (pio == 5) ? 4 : pio;
-	speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, pio, NULL);
-        
+	if (pio == 255)
+		speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		speed = XFER_PIO_0 + min_t(byte, pio, 4);
+
 	return ((int) pdc202xx_tune_chipset(drive, speed));
 }
 
diff -Nru a/drivers/ide/pdc4030.c b/drivers/ide/pdc4030.c
--- a/drivers/ide/pdc4030.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/pdc4030.c	Fri Mar 15 17:51:02 2002
@@ -551,7 +551,6 @@
 {
 	struct request *rq	= HWGROUP(drive)->rq;
 	task_struct_t *taskfile	= (task_struct_t *) task->tfRegister;
-	ide_startstop_t startstop;
 	unsigned long timeout;
 	byte stat;
 
diff -Nru a/drivers/ide/pdcadma.c b/drivers/ide/pdcadma.c
--- a/drivers/ide/pdcadma.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/pdcadma.c	Fri Mar 15 17:51:02 2002
@@ -24,7 +24,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #undef DISPLAY_PDCADMA_TIMINGS
 
diff -Nru a/drivers/ide/piix.c b/drivers/ide/piix.c
--- a/drivers/ide/piix.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/piix.c	Fri Mar 15 17:51:02 2002
@@ -65,7 +65,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define PIIX_DEBUG_DRIVE_INFO		0
 
@@ -225,7 +225,11 @@
 				    { 2, 1 },
 				    { 2, 3 }, };
 
-	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
+	else
+		pio = min_t(byte, pio, 4);
+
 	pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
 	if (is_slave) {
 		master_data = master_data | 0x4000;
@@ -352,27 +356,9 @@
 				   (dev->device == PCI_DEVICE_ID_INTEL_82451NX) ||
 				   (dev->device == PCI_DEVICE_ID_INTEL_82801AB_1)) ? 1 : 0;
 
-	if ((id->dma_ultra & 0x0020) && (udma_66) && (ultra100)) {
-		speed = XFER_UDMA_5;
-	} else if ((id->dma_ultra & 0x0010) && (ultra)) {
-		speed = ((udma_66) && (ultra66)) ? XFER_UDMA_4 : XFER_UDMA_2;
-	} else if ((id->dma_ultra & 0x0008) && (ultra)) {
-		speed = ((udma_66) && (ultra66)) ? XFER_UDMA_3 : XFER_UDMA_1;
-	} else if ((id->dma_ultra & 0x0004) && (ultra)) {
-		speed = XFER_UDMA_2;
-	} else if ((id->dma_ultra & 0x0002) && (ultra)) {
-		speed = XFER_UDMA_1;
-	} else if ((id->dma_ultra & 0x0001) && (ultra)) {
-		speed = XFER_UDMA_0;
-	} else if (id->dma_mword & 0x0004) {
-		speed = XFER_MW_DMA_2;
-	} else if (id->dma_mword & 0x0002) {
-		speed = XFER_MW_DMA_1;
-	} else if (id->dma_1word & 0x0004) {
-		speed = XFER_SW_DMA_2;
-        } else {
-		speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
-	}
+	speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA
+					| (ultra ? XFER_UDMA : 0) | ((udma_66 & ultra66) ? XFER_UDMA_66 : 0)
+					| ((udma_66 & ultra100) ? XFER_UDMA_100 : 0));
 
 	(void) piix_tune_chipset(drive, speed);
 
@@ -385,7 +371,7 @@
 
 static void config_chipset_for_pio (ide_drive_t *drive)
 {
-	piix_tune_drive(drive, ide_get_best_pio_mode(drive, 255, 5, NULL));
+	piix_tune_drive(drive, ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0);
 }
 
 static int config_drive_xfer_rate (ide_drive_t *drive)
diff -Nru a/drivers/ide/qd65xx.c b/drivers/ide/qd65xx.c
--- a/drivers/ide/qd65xx.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/qd65xx.c	Fri Mar 15 17:51:02 2002
@@ -33,7 +33,7 @@
 #include <linux/init.h>
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 #include "qd65xx.h"
 
 /*
@@ -249,42 +249,46 @@
 
 static void qd6580_tune_drive (ide_drive_t *drive, byte pio)
 {
-	ide_pio_data_t d;
+	struct ata_timing *t;
 	int base = HWIF(drive)->select_data;
 	int active_time   = 175;
 	int recovery_time = 415; /* worst case values from the dos driver */
 
 	if (drive->id && !qd_find_disk_type(drive,&active_time,&recovery_time)) {
-		pio = ide_get_best_pio_mode(drive, pio, 255, &d);
-		pio = min(pio,4);
+
+		if (pio == 255)
+			pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+		else
+			pio = XFER_PIO_0 + min_t(byte, pio, 4);
+
+		t = ata_timing_data(pio);
 
 		switch (pio) {
 			case 0: break;
 			case 3:
-				if (d.cycle_time >= 110) {
+				if (t->cycle >= 110) {
 					active_time = 86;
-					recovery_time = d.cycle_time-102;
+					recovery_time = t->cycle-102;
 				} else
 					printk(KERN_WARNING "%s: Strange recovery time !\n",drive->name);
 				break;
 			case 4:
-				if (d.cycle_time >= 69) {
+				if (t->cycle >= 69) {
 					active_time = 70;
-					recovery_time = d.cycle_time-61;
+					recovery_time = t->cycle-61;
 				} else
 					printk(KERN_WARNING "%s: Strange recovery time !\n",drive->name);
 				break;
 			default:
-				if (d.cycle_time >= 180) {
+				if (t->cycle >= 180) {
 					active_time = 110;
-					recovery_time = d.cycle_time - 120;
+					recovery_time = t->cycle - 120;
 				} else {
-					active_time = ide_pio_timings[pio].active_time;
-					recovery_time = d.cycle_time
-							-active_time;
+					active_time = t->active;
+					recovery_time = t->cycle - active_time;
 				}
 		}
-		printk(KERN_INFO "%s: PIO mode%d\n",drive->name,pio);
+		printk(KERN_INFO "%s: PIO mode%d\n", drive->name, pio - XFER_PIO_0);
 	}
 
 	if (!HWIF(drive)->channel && drive->type != ATA_DISK) {
diff -Nru a/drivers/ide/serverworks.c b/drivers/ide/serverworks.c
--- a/drivers/ide/serverworks.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/serverworks.c	Fri Mar 15 17:51:01 2002
@@ -91,7 +91,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define DISPLAY_SVWKS_TIMINGS	1
 #undef SVWKS_DEBUG_DRIVE_INFO
@@ -263,7 +263,7 @@
 	byte pio_timing		= 0x00;
 	unsigned short csb5_pio	= 0x00;
 
-	byte pio	= ide_get_best_pio_mode(drive, 255, 5, NULL);
+	byte pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
         switch (drive->dn) {
 		case 0: drive_pci = 0x41; drive_pci2 = 0x45; break;
@@ -364,9 +364,9 @@
 	unsigned short xfer_pio = drive->id->eide_pio_modes;
 	byte timing, speed, pio;
 
-	pio = ide_get_best_pio_mode(drive, 255, 5, NULL);
+	pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
-	if (xfer_pio> 4)
+	if (xfer_pio > 4)
 		xfer_pio = 0;
 
 	if (drive->id->eide_pio_iordy > 0)
@@ -416,30 +416,11 @@
 	struct pci_dev *dev	= HWIF(drive)->pci_dev;
 	byte udma_66	= eighty_ninty_three(drive);
 	int ultra66	= (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ? 1 : 0;
-	int ultra100 	= (ultra66 && svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 1 : 0;
-	byte speed;
+	int ultra100	= (ultra66 && svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 1 : 0;
 
-	if ((id->dma_ultra & 0x0020) && (udma_66) && (ultra100)) {
-		speed = XFER_UDMA_5;
-	} else if (id->dma_ultra & 0x0010) {
-		speed = ((udma_66) && (ultra66)) ? XFER_UDMA_4 : XFER_UDMA_2;
-	} else if (id->dma_ultra & 0x0008) {
-		speed = ((udma_66) && (ultra66)) ? XFER_UDMA_3 : XFER_UDMA_1;
-	} else if (id->dma_ultra & 0x0004) {
-		speed = XFER_UDMA_2;
-	} else if (id->dma_ultra & 0x0002) {
-		speed = XFER_UDMA_1;
-	} else if (id->dma_ultra & 0x0001) {
-		speed = XFER_UDMA_0;
-	} else if (id->dma_mword & 0x0004) {
-		speed = XFER_MW_DMA_2;
-	} else if (id->dma_mword & 0x0002) {
-		speed = XFER_MW_DMA_1;
-	} else if (id->dma_1word & 0x0004) {
-		speed = XFER_SW_DMA_2;
-	} else {
-		speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
-	}
+	byte speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA | XFER_UDMA
+				| ((udma_66 && ultra66) ? XFER_UDMA_66 : 0)
+				| ((udma_66 && ultra100) ? XFER_UDMA_100 : 0));
 
 	(void) svwks_tune_chipset(drive, speed);
 
diff -Nru a/drivers/ide/sis5513.c b/drivers/ide/sis5513.c
--- a/drivers/ide/sis5513.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/sis5513.c	Fri Mar 15 17:51:02 2002
@@ -1,11 +1,35 @@
 /*
- * linux/drivers/ide/sis5513.c		Version 0.11	June 9, 2000
+ * linux/drivers/ide/sis5513.c		Version 0.13	March 4, 2002
  *
  * Copyright (C) 1999-2000	Andre Hedrick <andre@linux-ide.org>
+ * Copyright (C) 2002		Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
  * May be copied or modified under the terms of the GNU General Public License
  *
- * Thanks to SIS Taiwan for direct support and hardware.
- * Tested and designed on the SiS620/5513 chipset.
+*/
+
+/* Thanks :
+ * For direct support and hardware : SiS Taiwan.
+ * For ATA100 support advice       : Daniela Engert.
+ * For checking code correctness, providing patches :
+ * John Fremlin, Manfred Spraul
+ */
+
+/*
+ * Original tests and design on the SiS620/5513 chipset.
+ * ATA100 tests and design on the SiS735/5513 chipset.
+ * ATA16/33 design from specs
+ */
+
+/*
+ * TODO:
+ *	- Get ridden of SisHostChipInfo[] completness dependancy.
+ *	- Get ATA-133 datasheets, implement ATA-133 init code.
+ *	- Are there pre-ATA_16 SiS chips ? -> tune init code for them
+ *	  or remove ATA_00 define
+ *	- More checks in the config registers (force values instead of
+ *	  relying on the BIOS setting them correctly).
+ *	- Further optimisations ?
+ *	  . for example ATA66+ regs 0x48 & 0x4A
  */
 
 #include <linux/config.h>
@@ -26,90 +50,186 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
+// #define DEBUG
+/* if BROKEN_LEVEL is defined it limits the DMA mode
+   at boot time to its value */
+// #define BROKEN_LEVEL XFER_SW_DMA_0
 #define DISPLAY_SIS_TIMINGS
-#define SIS5513_DEBUG_DRIVE_INFO	0
 
-static struct pci_dev *host_dev = NULL;
+/* Miscellaneaous flags */
+#define SIS5513_LATENCY		0x01
+/* ATA transfer mode capabilities */
+#define ATA_00		0x00
+#define ATA_16		0x01
+#define ATA_33		0x02
+#define ATA_66		0x03
+#define ATA_100a	0x04
+#define ATA_100		0x05
+#define ATA_133		0x06
+
+static unsigned char dma_capability = 0x00;
 
-#define SIS5513_FLAG_ATA_00		0x00000000
-#define SIS5513_FLAG_ATA_16		0x00000001
-#define SIS5513_FLAG_ATA_33		0x00000002
-#define SIS5513_FLAG_ATA_66		0x00000004
-#define SIS5513_FLAG_LATENCY		0x00000010
 
+/*
+ * Debug code: following IDE config registers' changes
+ */
+#ifdef DEBUG
+/* Copy of IDE Config registers 0x00 -> 0x58
+   Fewer might be used depending on the actual chipset */
+static unsigned char ide_regs_copy[] = {
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0,
+	0x0, 0x0, 0x0, 0x0
+};
+
+static byte sis5513_max_config_register(void) {
+	switch(dma_capability) {
+		case ATA_00:
+		case ATA_16:	return 0x4f;
+		case ATA_33:	return 0x52;
+		case ATA_66:
+		case ATA_100a:
+		case ATA_100:
+		case ATA_133:
+		default:	return 0x57;
+	}
+}
+
+/* Read config registers, print differences from previous read */
+static void sis5513_load_verify_registers(struct pci_dev* dev, char* info) {
+	int i;
+	byte reg_val;
+	byte changed=0;
+	byte max = sis5513_max_config_register();
+
+	printk("SIS5513: %s, changed registers:\n", info);
+	for(i=0; i<=max; i++) {
+		pci_read_config_byte(dev, i, &reg_val);
+		if (reg_val != ide_regs_copy[i]) {
+			printk("%0#x: %0#x -> %0#x\n",
+			       i, ide_regs_copy[i], reg_val);
+			ide_regs_copy[i]=reg_val;
+			changed=1;
+		}
+	}
+
+	if (!changed) {
+		printk("none\n");
+	}
+}
+
+/* Load config registers, no printing */
+static void sis5513_load_registers(struct pci_dev* dev) {
+	int i;
+	byte max = sis5513_max_config_register();
+
+	for(i=0; i<=max; i++) {
+		pci_read_config_byte(dev, i, &(ide_regs_copy[i]));
+	}
+}
+
+/* Print a register */
+static void sis5513_print_register(int reg) {
+	printk(" %0#x:%0#x", reg, ide_regs_copy[reg]);
+}
+
+/* Print valuable registers */
+static void sis5513_print_registers(struct pci_dev* dev, char* marker) {
+	int i;
+	byte max = sis5513_max_config_register();
+
+	sis5513_load_registers(dev);
+	printk("SIS5513 %s\n", marker);
+	printk("SIS5513 dump:");
+	for(i=0x00; i<0x40; i++) {
+		if ((i % 0x10)==0) printk("\n             ");
+		sis5513_print_register(i);
+	}
+	for(; i<49; i++) {
+		sis5513_print_register(i);
+	}
+	printk("\n             ");
+
+	for(; i<=max; i++) {
+		sis5513_print_register(i);
+	}
+	printk("\n");
+}
+#endif
+
+
+/*
+ * Devices supported
+ */
 static const struct {
 	const char *name;
 	unsigned short host_id;
-	unsigned int flags;
+	unsigned char dma_capability;
+	unsigned char flags;
 } SiSHostChipInfo[] = {
-	{ "SiS530",	PCI_DEVICE_ID_SI_530,	SIS5513_FLAG_ATA_66, },
-	{ "SiS540",	PCI_DEVICE_ID_SI_540,	SIS5513_FLAG_ATA_66, },
-	{ "SiS620",	PCI_DEVICE_ID_SI_620,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS630",	PCI_DEVICE_ID_SI_630,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS635",	PCI_DEVICE_ID_SI_635,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS640",	PCI_DEVICE_ID_SI_640,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS645",	PCI_DEVICE_ID_SI_645,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS650",	PCI_DEVICE_ID_SI_650,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS730",	PCI_DEVICE_ID_SI_730,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS735",	PCI_DEVICE_ID_SI_735,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS740",	PCI_DEVICE_ID_SI_740,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS745",	PCI_DEVICE_ID_SI_745,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS750",	PCI_DEVICE_ID_SI_750,	SIS5513_FLAG_ATA_66|SIS5513_FLAG_LATENCY, },
-	{ "SiS5591",	PCI_DEVICE_ID_SI_5591,	SIS5513_FLAG_ATA_33, },
-	{ "SiS5597",	PCI_DEVICE_ID_SI_5597,	SIS5513_FLAG_ATA_33, },
-	{ "SiS5600",	PCI_DEVICE_ID_SI_5600,	SIS5513_FLAG_ATA_33, },
-	{ "SiS5511",	PCI_DEVICE_ID_SI_5511,	SIS5513_FLAG_ATA_16, },
-};
-
-#if 0
-
-static struct _pio_mode_mapping {
-	byte data_active;
-	byte recovery;
-	byte pio_mode;
-} pio_mode_mapping[] = {
-	{ 8, 12, 0 },
-	{ 6,  7, 1 },
-	{ 4,  4, 2 },
-	{ 3,  3, 3 },
-	{ 3,  1, 4 }
+	{ "SiS750",	PCI_DEVICE_ID_SI_750,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS745",	PCI_DEVICE_ID_SI_745,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS740",	PCI_DEVICE_ID_SI_740,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS735",	PCI_DEVICE_ID_SI_735,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS730",	PCI_DEVICE_ID_SI_730,	ATA_100a,	SIS5513_LATENCY },
+	{ "SiS650",	PCI_DEVICE_ID_SI_650,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS645",	PCI_DEVICE_ID_SI_645,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS635",	PCI_DEVICE_ID_SI_635,	ATA_100,	SIS5513_LATENCY },
+	{ "SiS640",	PCI_DEVICE_ID_SI_640,	ATA_66,		SIS5513_LATENCY },
+	{ "SiS630",	PCI_DEVICE_ID_SI_630,	ATA_66,		SIS5513_LATENCY },
+	{ "SiS620",	PCI_DEVICE_ID_SI_620,	ATA_66,		SIS5513_LATENCY },
+	{ "SiS540",	PCI_DEVICE_ID_SI_540,	ATA_66,		0},
+	{ "SiS530",	PCI_DEVICE_ID_SI_530,	ATA_66,		0},
+	{ "SiS5600",	PCI_DEVICE_ID_SI_5600,	ATA_33,		0},
+	{ "SiS5598",	PCI_DEVICE_ID_SI_5598,	ATA_33,		0},
+	{ "SiS5597",	PCI_DEVICE_ID_SI_5597,	ATA_33,		0},
+	{ "SiS5591",	PCI_DEVICE_ID_SI_5591,	ATA_33,		0},
+	{ "SiS5513",	PCI_DEVICE_ID_SI_5513,	ATA_16,		0},
+	{ "SiS5511",	PCI_DEVICE_ID_SI_5511,	ATA_16,		0},
 };
 
-static struct _dma_mode_mapping {
-	byte data_active;
-	byte recovery;
-	byte dma_mode;
-} dma_mode_mapping[] = {
-	{ 8, 8, 0 },
-	{ 3, 2, 1 },
-	{ 3, 1, 2 }
+/* Cycle time bits and values vary accross chip dma capabilities
+   These three arrays hold the register layout and the values to set.
+   Indexed by dma_capability and (dma_mode - XFER_UDMA_0) */
+static byte cycle_time_offset[] = {0,0,5,4,4,0,0};
+static byte cycle_time_range[] = {0,0,2,3,3,4,4};
+static byte cycle_time_value[][XFER_UDMA_5 - XFER_UDMA_0 + 1] = {
+	{0,0,0,0,0,0}, /* no udma */
+	{0,0,0,0,0,0}, /* no udma */
+	{3,2,1,0,0,0},
+	{7,5,3,2,1,0},
+	{7,5,3,2,1,0},
+	{11,7,5,4,2,1},
+	{0,0,0,0,0,0} /* not yet known, ask SiS */
 };
 
-static struct _udma_mode_mapping {
-	byte cycle_time;
-	char * udma_mode;
-} udma_mode_mapping[] = {
-	{ 8, "Mode 0" },
-	{ 6, "Mode 1" },
-	{ 4, "Mode 2" }, 
-	{ 3, "Mode 3" },
-	{ 2, "Mode 4" },
-	{ 0, "Mode 5" }
-};
+static struct pci_dev *host_dev = NULL;
 
-static __inline__ char * find_udma_mode (byte cycle_time)
-{
-	int n;
-	
-	for (n = 0; n <= 4; n++)
-		if (udma_mode_mapping[n].cycle_time <= cycle_time)
-			return udma_mode_mapping[n].udma_mode;
-	return udma_mode_mapping[4].udma_mode;
-}
-#endif
 
+/*
+ * Printing configuration
+ */
 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 #include <linux/stat.h>
 #include <linux/proc_fs.h>
@@ -118,12 +238,12 @@
 extern int (*sis_display_info)(char *, char **, off_t, int); /* ide-proc.c */
 static struct pci_dev *bmide_dev;
 
-static char *cable_type[] = {
+static char* cable_type[] = {
 	"80 pins",
 	"40 pins"
 };
 
-static char *recovery_time [] ={
+static char* recovery_time[] ={
 	"12 PCICLK", "1 PCICLK",
 	"2 PCICLK", "3 PCICLK",
 	"4 PCICLK", "5 PCICLCK",
@@ -134,101 +254,184 @@
 	"15 PCICLK", "15 PCICLK"
 };
 
-static char * cycle_time [] = {
-	"2 CLK", "2 CLK",
-	"3 CLK", "4 CLK",
-	"5 CLK", "6 CLK",
-	"7 CLK", "8 CLK"
-};
-
-static char * active_time [] = {
+static char* active_time[] = {
 	"8 PCICLK", "1 PCICLCK",
-	"2 PCICLK", "2 PCICLK",
+	"2 PCICLK", "3 PCICLK",
 	"4 PCICLK", "5 PCICLK",
 	"6 PCICLK", "12 PCICLK"
 };
 
+static char* cycle_time[] = {
+	"Reserved", "2 CLK",
+	"3 CLK", "4 CLK",
+	"5 CLK", "6 CLK",
+	"7 CLK", "8 CLK",
+	"9 CLK", "10 CLK",
+	"11 CLK", "12 CLK",
+	"Reserved", "Reserved",
+	"Reserved", "Reserved"
+};
+
+/* Generic add master or slave info function */
+static char* get_drives_info (char *buffer, byte pos)
+{
+	byte reg00, reg01, reg10, reg11; /* timing registers */
+	char* p = buffer;
+
+/* Postwrite/Prefetch */
+	pci_read_config_byte(bmide_dev, 0x4b, &reg00);
+	p += sprintf(p, "Drive %d:        Postwrite %s \t \t Postwrite %s\n",
+		     pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
+		     (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
+	p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
+		     (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
+		     (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
+
+	pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
+	pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
+	pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
+	pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
+
+/* UDMA */
+	if (dma_capability >= ATA_33) {
+		p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
+			     (reg01 & 0x80)  ? "Enabled" : "Disabled",
+			     (reg11 & 0x80) ? "Enabled" : "Disabled");
+
+		p += sprintf(p, "                UDMA Cycle Time    ");
+		switch(dma_capability) {
+			case ATA_33:	p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
+			case ATA_66:
+			case ATA_100a:	p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
+			case ATA_100:	p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
+			case ATA_133:
+			default:	p += sprintf(p, "133+ ?"); break;
+		}
+		p += sprintf(p, " \t UDMA Cycle Time    ");
+		switch(dma_capability) {
+			case ATA_33:	p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
+			case ATA_66:
+			case ATA_100a:	p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
+			case ATA_100:	p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
+			case ATA_133:
+			default:	p += sprintf(p, "133+ ?"); break;
+		}
+		p += sprintf(p, "\n");
+	}
+
+/* Data Active */
+	p += sprintf(p, "                Data Active Time   ");
+	switch(dma_capability) {
+		case ATA_00:
+		case ATA_16: /* confirmed */
+		case ATA_33:
+		case ATA_66:
+		case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
+		case ATA_100: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
+		case ATA_133:
+		default: p += sprintf(p, "133+ ?"); break;
+	}
+	p += sprintf(p, " \t Data Active Time   ");
+	switch(dma_capability) {
+		case ATA_00:
+		case ATA_16:
+		case ATA_33:
+		case ATA_66:
+		case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
+		case ATA_100: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
+		case ATA_133:
+		default: p += sprintf(p, "133+ ?"); break;
+	}
+	p += sprintf(p, "\n");
+
+/* Data Recovery */
+	/* warning: may need (reg&0x07) for pre ATA66 chips */
+	p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
+		     recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
+
+	return p;
+}
+
+static char* get_masters_info(char* buffer)
+{
+	return get_drives_info(buffer, 0);
+}
+
+static char* get_slaves_info(char* buffer)
+{
+	return get_drives_info(buffer, 1);
+}
+
+/* Main get_info, called on /proc/ide/sis reads */
 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
 {
-	int rc;
 	char *p = buffer;
-	byte reg,reg1;
+	byte reg;
 	u16 reg2, reg3;
 
+	p += sprintf(p, "\nSiS 5513 ");
+	switch(dma_capability) {
+		case ATA_00: p += sprintf(p, "Unknown???"); break;
+		case ATA_16: p += sprintf(p, "DMA 16"); break;
+		case ATA_33: p += sprintf(p, "Ultra 33"); break;
+		case ATA_66: p += sprintf(p, "Ultra 66"); break;
+		case ATA_100a:
+		case ATA_100: p += sprintf(p, "Ultra 100"); break;
+		case ATA_133:
+		default: p+= sprintf(p, "Ultra 133+"); break;
+	}
+	p += sprintf(p, " chipset\n");
 	p += sprintf(p, "--------------- Primary Channel ---------------- Secondary Channel -------------\n");
-	rc = pci_read_config_byte(bmide_dev, 0x4a, &reg);
-	p += sprintf(p, "Channel Status: %s \t \t \t \t %s \n",
-		     (reg & 0x02) ? "On" : "Off",
-		     (reg & 0x04) ? "On" : "Off");
-		     
-	rc = pci_read_config_byte(bmide_dev, 0x09, &reg);
+
+/* Status */
+	pci_read_config_byte(bmide_dev, 0x4a, &reg);
+	p += sprintf(p, "Channel Status: ");
+	if (dma_capability < ATA_66) {
+		p += sprintf(p, "%s \t \t \t \t %s\n",
+			     (reg & 0x04) ? "On" : "Off",
+			     (reg & 0x02) ? "On" : "Off");
+	} else {
+		p += sprintf(p, "%s \t \t \t \t %s \n",
+			     (reg & 0x02) ? "On" : "Off",
+			     (reg & 0x04) ? "On" : "Off");
+	}
+
+/* Operation Mode */
+	pci_read_config_byte(bmide_dev, 0x09, &reg);
 	p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
 		     (reg & 0x01) ? "Native" : "Compatible",
 		     (reg & 0x04) ? "Native" : "Compatible");
-		     	     
-	rc = pci_read_config_byte(bmide_dev, 0x48, &reg);
-	p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
-		     (reg & 0x10) ? cable_type[1] : cable_type[0],
-		     (reg & 0x20) ? cable_type[1] : cable_type[0]);
-		     
-	rc = pci_read_config_word(bmide_dev, 0x4c, &reg2);
-	rc = pci_read_config_word(bmide_dev, 0x4e, &reg3);
-	p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
-		     reg2, reg3);
-
-	rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);	     
-	p += sprintf(p, "Drive 0:        Postwrite %s \t \t Postwrite %s\n",
-		     (reg & 0x10) ? "Enabled" : "Disabled",
-		     (reg & 0x40) ? "Enabled" : "Disabled");
-	p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
-		     (reg & 0x01) ? "Enabled" : "Disabled",
-		     (reg & 0x04) ? "Enabled" : "Disabled");
-		          
-	rc = pci_read_config_byte(bmide_dev, 0x41, &reg);
-	rc = pci_read_config_byte(bmide_dev, 0x45, &reg1);
-	p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
-		     (reg & 0x80)  ? "Enabled" : "Disabled",
-		     (reg1 & 0x80) ? "Enabled" : "Disabled");
-	p += sprintf(p, "                UDMA Cycle Time    %s \t UDMA Cycle Time    %s\n",
-		     cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
-	p += sprintf(p, "                Data Active Time   %s \t Data Active Time   %s\n",
-		     active_time[(reg & 0x07)], active_time[(reg1 &0x07)] ); 
-
-	rc = pci_read_config_byte(bmide_dev, 0x40, &reg);
-	rc = pci_read_config_byte(bmide_dev, 0x44, &reg1);
-	p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
-		     recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
 
+/* 80-pin cable ? */
+	if (dma_capability > ATA_33) {
+		pci_read_config_byte(bmide_dev, 0x48, &reg);
+		p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
+			     (reg & 0x10) ? cable_type[1] : cable_type[0],
+			     (reg & 0x20) ? cable_type[1] : cable_type[0]);
+	}
 
-	rc = pci_read_config_byte(bmide_dev, 0x4b, &reg);	     
-	p += sprintf(p, "Drive 1:        Postwrite %s \t \t Postwrite %s\n",
-		     (reg & 0x20) ? "Enabled" : "Disabled",
-		     (reg & 0x80) ? "Enabled" : "Disabled");
-	p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
-		     (reg & 0x02) ? "Enabled" : "Disabled",
-		     (reg & 0x08) ? "Enabled" : "Disabled");
+/* Prefetch Count */
+	pci_read_config_word(bmide_dev, 0x4c, &reg2);
+	pci_read_config_word(bmide_dev, 0x4e, &reg3);
+	p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
+		     reg2, reg3);
 
-	rc = pci_read_config_byte(bmide_dev, 0x43, &reg);
-	rc = pci_read_config_byte(bmide_dev, 0x47, &reg1);
-	p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
-		     (reg & 0x80)  ? "Enabled" : "Disabled",
-		     (reg1 & 0x80) ? "Enabled" : "Disabled");
-	p += sprintf(p, "                UDMA Cycle Time    %s \t UDMA Cycle Time    %s\n",
-		     cycle_time[(reg & 0x70) >> 4], cycle_time[(reg1 & 0x70) >> 4]);
-	p += sprintf(p, "                Data Active Time   %s \t Data Active Time   %s\n",
-		     active_time[(reg & 0x07)], active_time[(reg1 &0x07)] ); 
+	p = get_masters_info(p);
+	p = get_slaves_info(p);
 
-	rc = pci_read_config_byte(bmide_dev, 0x42, &reg);
-	rc = pci_read_config_byte(bmide_dev, 0x46, &reg1);
-	p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
-		     recovery_time[(reg & 0x0f)], recovery_time[(reg1 & 0x0f)]);
 	return p-buffer;
 }
 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
 
+
 byte sis_proc = 0;
 extern char *ide_xfer_verbose (byte xfer_rate);
 
+
+/*
+ * Configuration functions
+ */
+/* Enables per-drive prefetch and postwrite */
 static void config_drive_art_rwp (ide_drive_t *drive)
 {
 	ide_hwif_t *hwif	= HWIF(drive);
@@ -237,14 +440,24 @@
 	byte reg4bh		= 0;
 	byte rw_prefetch	= (0x11 << drive->dn);
 
-	pci_read_config_byte(dev, 0x4b, &reg4bh);
+#ifdef DEBUG
+	printk("SIS5513: config_drive_art_rwp, drive %d\n", drive->dn);
+	sis5513_load_verify_registers(dev, "config_drive_art_rwp start");
+#endif
+
 	if (drive->type != ATA_DISK)
 		return;
-	
+	pci_read_config_byte(dev, 0x4b, &reg4bh);
+
 	if ((reg4bh & rw_prefetch) != rw_prefetch)
 		pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
+#ifdef DEBUG
+	sis5513_load_verify_registers(dev, "config_drive_art_rwp end");
+#endif
 }
 
+
+/* Set per-drive active and recovery time */
 static void config_art_rwp_pio (ide_drive_t *drive, byte pio)
 {
 	ide_hwif_t *hwif	= HWIF(drive);
@@ -255,16 +468,22 @@
 	unsigned short eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
 	unsigned short xfer_pio = drive->id->eide_pio_modes;
 
+#ifdef DEBUG
+	sis5513_load_verify_registers(dev, "config_drive_art_rwp_pio start");
+#endif
+
 	config_drive_art_rwp(drive);
-	pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
+
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 
 	if (xfer_pio> 4)
 		xfer_pio = 0;
 
 	if (drive->id->eide_pio_iordy > 0) {
 		for (xfer_pio = 5;
-			xfer_pio>0 &&
-			drive->id->eide_pio_iordy>eide_pio_timing[xfer_pio];
+			(xfer_pio > 0) &&
+			(drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
 			xfer_pio--);
 	} else {
 		xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
@@ -274,14 +493,10 @@
 
 	timing = (xfer_pio >= pio) ? xfer_pio : pio;
 
-/*
- *               Mode 0       Mode 1     Mode 2     Mode 3     Mode 4
- * Active time    8T (240ns)  6T (180ns) 4T (120ns) 3T  (90ns) 3T  (90ns)
- * 0x41 2:0 bits  000          110        100        011        011
- * Recovery time 12T (360ns)  7T (210ns) 4T (120ns) 3T  (90ns) 1T  (30ns)
- * 0x40 3:0 bits 0000         0111       0100       0011       0001
- * Cycle time    20T (600ns) 13T (390ns) 8T (240ns) 6T (180ns) 4T (120ns)
- */
+#ifdef DEBUG
+	printk("SIS5513: config_drive_art_rwp_pio, drive %d, pio %d, timing %d\n",
+	       drive->dn, pio, timing);
+#endif
 
 	switch(drive->dn) {
 		case 0:		drive_pci = 0x40; break;
@@ -291,31 +506,43 @@
 		default:	return;
 	}
 
-	pci_read_config_byte(dev, drive_pci, &test1);
-	pci_read_config_byte(dev, drive_pci|0x01, &test2);
-
-	/*
-	 * Do a blanket clear of active and recovery timings.
-	 */
-
-	test1 &= ~0x07;
-	test2 &= ~0x0F;
-
-	switch(timing) {
-		case 4:		test1 |= 0x01; test2 |= 0x03; break;
-		case 3:		test1 |= 0x03; test2 |= 0x03; break;
-		case 2:		test1 |= 0x04; test2 |= 0x04; break;
-		case 1:		test1 |= 0x07; test2 |= 0x06; break;
-		default:	break;
+	/* register layout changed with newer ATA100 chips */
+	if (dma_capability < ATA_100) {
+		pci_read_config_byte(dev, drive_pci, &test1);
+		pci_read_config_byte(dev, drive_pci+1, &test2);
+
+		/* Clear active and recovery timings */
+		test1 &= ~0x0F;
+		test2 &= ~0x07;
+
+		switch(timing) {
+			case 4:		test1 |= 0x01; test2 |= 0x03; break;
+			case 3:		test1 |= 0x03; test2 |= 0x03; break;
+			case 2:		test1 |= 0x04; test2 |= 0x04; break;
+			case 1:		test1 |= 0x07; test2 |= 0x06; break;
+			default:	break;
+		}
+		pci_write_config_byte(dev, drive_pci, test1);
+		pci_write_config_byte(dev, drive_pci+1, test2);
+	} else {
+		switch(timing) { /*   active  recovery
+					  v     v */
+			case 4:		test1 = 0x30|0x01; break;
+			case 3:		test1 = 0x30|0x03; break;
+			case 2:		test1 = 0x40|0x04; break;
+			case 1:		test1 = 0x60|0x07; break;
+			default:	break;
+		}
+		pci_write_config_byte(dev, drive_pci, test1);
 	}
 
-	pci_write_config_byte(dev, drive_pci, test1);
-	pci_write_config_byte(dev, drive_pci|0x01, test2);
+#ifdef DEBUG
+	sis5513_load_verify_registers(dev, "config_drive_art_rwp_pio start");
+#endif
 }
 
 static int config_chipset_for_pio (ide_drive_t *drive, byte pio)
 {
-	int err;
 	byte speed;
 
 	switch(pio) {
@@ -328,8 +555,7 @@
 
 	config_art_rwp_pio(drive, pio);
 	drive->current_speed = speed;
-	err = ide_config_drive_speed(drive, speed);
-	return err;
+	return ide_config_drive_speed(drive, speed);
 }
 
 static int sis5513_tune_chipset (ide_drive_t *drive, byte speed)
@@ -337,82 +563,73 @@
 	ide_hwif_t *hwif	= HWIF(drive);
 	struct pci_dev *dev	= hwif->pci_dev;
 
-	byte			drive_pci, test1, test2;
-	byte			unmask, four_two, mask = 0;
-
-	if (host_dev) {
-		switch(host_dev->device) {
-			case PCI_DEVICE_ID_SI_530:
-			case PCI_DEVICE_ID_SI_540:
-			case PCI_DEVICE_ID_SI_620:
-			case PCI_DEVICE_ID_SI_630:
-			case PCI_DEVICE_ID_SI_635:
-			case PCI_DEVICE_ID_SI_640:
-			case PCI_DEVICE_ID_SI_645:
-			case PCI_DEVICE_ID_SI_650:
-			case PCI_DEVICE_ID_SI_730:
-			case PCI_DEVICE_ID_SI_735:
-			case PCI_DEVICE_ID_SI_740:
-			case PCI_DEVICE_ID_SI_745:
-			case PCI_DEVICE_ID_SI_750:
-				unmask   = 0xF0;
-				four_two = 0x01;
-				break;
-			default:
-				unmask   = 0xE0;
-				four_two = 0x00;
-				break;
-		}
-	} else {
-		unmask   = 0xE0;
-		four_two = 0x00;
-	}
+	byte			drive_pci, reg;
 
+#ifdef DEBUG
+	sis5513_load_verify_registers(dev, "sis5513_tune_chipset start");
+	printk("SIS5513: sis5513_tune_chipset, drive %d, speed %d\n",
+	       drive->dn, speed);
+#endif
 	switch(drive->dn) {
-		case 0:		drive_pci = 0x40;break;
-		case 1:		drive_pci = 0x42;break;
-		case 2:		drive_pci = 0x44;break;
-		case 3:		drive_pci = 0x46;break;
+		case 0:		drive_pci = 0x40; break;
+		case 1:		drive_pci = 0x42; break;
+		case 2:		drive_pci = 0x44; break;
+		case 3:		drive_pci = 0x46; break;
 		default:	return ide_dma_off;
 	}
 
-	pci_read_config_byte(dev, drive_pci, &test1);
-	pci_read_config_byte(dev, drive_pci|0x01, &test2);
+#ifdef BROKEN_LEVEL
+#ifdef DEBUG
+	printk("SIS5513: BROKEN_LEVEL activated, speed=%d -> speed=%d\n", speed, BROKEN_LEVEL);
+#endif
+	if (speed > BROKEN_LEVEL) speed = BROKEN_LEVEL;
+#endif
 
-	if ((speed <= XFER_MW_DMA_2) && (test2 & 0x80)) {
-		pci_write_config_byte(dev, drive_pci|0x01, test2 & ~0x80);
-		pci_read_config_byte(dev, drive_pci|0x01, &test2);
-	} else {
-		pci_write_config_byte(dev, drive_pci|0x01, test2 & ~unmask);
+	pci_read_config_byte(dev, drive_pci+1, &reg);
+	/* Disable UDMA bit for non UDMA modes on UDMA chips */
+	if ((speed < XFER_UDMA_0) && (dma_capability > ATA_16)) {
+		reg &= 0x7F;
+		pci_write_config_byte(dev, drive_pci+1, reg);
 	}
 
+	/* Config chip for mode */
 	switch(speed) {
 #ifdef CONFIG_BLK_DEV_IDEDMA
-		case XFER_UDMA_5: mask = 0x80; break;
-		case XFER_UDMA_4: mask = 0x90; break;
-		case XFER_UDMA_3: mask = 0xA0; break;
-		case XFER_UDMA_2: mask = (four_two) ? 0xB0 : 0xA0; break;
-		case XFER_UDMA_1: mask = (four_two) ? 0xD0 : 0xC0; break;
-		case XFER_UDMA_0: mask = unmask; break;
+		case XFER_UDMA_5:
+		case XFER_UDMA_4:
+		case XFER_UDMA_3:
+		case XFER_UDMA_2:
+		case XFER_UDMA_1:
+		case XFER_UDMA_0:
+			/* Force the UDMA bit on if we want to use UDMA */
+			reg |= 0x80;
+			/* clean reg cycle time bits */
+			reg &= ~((0xFF >> (8 - cycle_time_range[dma_capability]))
+				 << cycle_time_offset[dma_capability]);
+			/* set reg cycle time bits */
+			reg |= cycle_time_value[dma_capability-ATA_00][speed-XFER_UDMA_0]
+				<< cycle_time_offset[dma_capability];
+			pci_write_config_byte(dev, drive_pci+1, reg);
+			break;
 		case XFER_MW_DMA_2:
 		case XFER_MW_DMA_1:
 		case XFER_MW_DMA_0:
 		case XFER_SW_DMA_2:
 		case XFER_SW_DMA_1:
-		case XFER_SW_DMA_0: break;
+		case XFER_SW_DMA_0:
+			break;
 #endif /* CONFIG_BLK_DEV_IDEDMA */
 		case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
 		case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
 		case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
 		case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
 		case XFER_PIO_0:
-		default:	 return((int) config_chipset_for_pio(drive, 0));
+		default:	 return((int) config_chipset_for_pio(drive, 0));	
 	}
-
-	if (speed > XFER_MW_DMA_2)
-		pci_write_config_byte(dev, drive_pci|0x01, test2|mask);
-
 	drive->current_speed = speed;
+#ifdef DEBUG
+	sis5513_load_verify_registers(dev, "sis5513_tune_chipset end");
+#endif
 	return ((int) ide_config_drive_speed(drive, speed));
 }
 
@@ -430,47 +647,27 @@
 	struct hd_driveid *id	= drive->id;
 	ide_hwif_t *hwif	= HWIF(drive);
 
-	byte			four_two = 0, speed = 0;
-	int			err;
+	byte			speed = 0;
 
 	byte unit		= (drive->select.b.unit & 0x01);
 	byte udma_66		= eighty_ninty_three(drive);
-	byte ultra_100		= 0;
 
-	if (host_dev) {
-		switch(host_dev->device) {
-			case PCI_DEVICE_ID_SI_635:
-			case PCI_DEVICE_ID_SI_640:
-			case PCI_DEVICE_ID_SI_645:
-			case PCI_DEVICE_ID_SI_650:
-			case PCI_DEVICE_ID_SI_730:
-			case PCI_DEVICE_ID_SI_735:
-			case PCI_DEVICE_ID_SI_740:
-			case PCI_DEVICE_ID_SI_745:
-			case PCI_DEVICE_ID_SI_750:
-				ultra_100 = 1;
-			case PCI_DEVICE_ID_SI_530:
-			case PCI_DEVICE_ID_SI_540:
-			case PCI_DEVICE_ID_SI_620:
-			case PCI_DEVICE_ID_SI_630:
-				four_two = 0x01;
-				break;
-			default:
-				four_two = 0x00; break;
-		}
-	}
+#ifdef DEBUG
+	printk("SIS5513: config_chipset_for_dma, drive %d, ultra %d\n",
+	       drive->dn, ultra);
+#endif
 
-	if ((id->dma_ultra & 0x0020) && (ultra) && (udma_66) && (four_two) && (ultra_100))
+	if ((id->dma_ultra & 0x0020) && ultra && udma_66 && (dma_capability >= ATA_100a))
 		speed = XFER_UDMA_5;
-	else if ((id->dma_ultra & 0x0010) && (ultra) && (udma_66) && (four_two))
+	else if ((id->dma_ultra & 0x0010) && ultra && udma_66 && (dma_capability >= ATA_66))
 		speed = XFER_UDMA_4;
-	else if ((id->dma_ultra & 0x0008) && (ultra) && (udma_66) && (four_two))
+	else if ((id->dma_ultra & 0x0008) && ultra && udma_66 && (dma_capability >= ATA_66))
 		speed = XFER_UDMA_3;
-	else if ((id->dma_ultra & 0x0004) && (ultra))
+	else if ((id->dma_ultra & 0x0004) && ultra && (dma_capability >= ATA_33))
 		speed = XFER_UDMA_2;
-	else if ((id->dma_ultra & 0x0002) && (ultra))
+	else if ((id->dma_ultra & 0x0002) && ultra && (dma_capability >= ATA_33))
 		speed = XFER_UDMA_1;
-	else if ((id->dma_ultra & 0x0001) && (ultra))
+	else if ((id->dma_ultra & 0x0001) && ultra && (dma_capability >= ATA_33))
 		speed = XFER_UDMA_0;
 	else if (id->dma_mword & 0x0004)
 		speed = XFER_MW_DMA_2;
@@ -489,11 +686,7 @@
 
 	outb(inb(hwif->dma_base+2)|(1<<(5+unit)), hwif->dma_base+2);
 
-	err = sis5513_tune_chipset(drive, speed);
-
-#if SIS5513_DEBUG_DRIVE_INFO
-	printk("%s: %s drive%d\n", drive->name, ide_xfer_verbose(speed), drive->dn);
-#endif /* SIS5513_DEBUG_DRIVE_INFO */
+	sis5513_tune_chipset(drive, speed);
 
 	return ((int)	((id->dma_ultra >> 11) & 7) ? ide_dma_on :
 			((id->dma_ultra >> 8) & 7) ? ide_dma_on :
@@ -550,9 +743,7 @@
 	return HWIF(drive)->dmaproc(dma_func, drive);
 }
 
-/*
- * sis5513_dmaproc() initiates/aborts (U)DMA read/write operations on a drive.
- */
+/* initiates/aborts (U)DMA read/write operations on a drive. */
 int sis5513_dmaproc (ide_dma_action_t func, ide_drive_t *drive)
 {
 	switch (func) {
@@ -567,15 +758,18 @@
 }
 #endif /* CONFIG_BLK_DEV_IDEDMA */
 
+/* Chip detection and general config */
 unsigned int __init pci_init_sis5513(struct pci_dev *dev)
 {
 	struct pci_dev *host;
 	int i = 0;
-	byte latency = 0;
 
-	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &latency);
+#ifdef DEBUG
+	sis5513_print_registers(dev, "pci_init_sis5513 start");
+#endif
 
-	for (i = 0; i < ARRAY_SIZE (SiSHostChipInfo) && !host_dev; i++) {
+	/* Find the chip */
+	for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !host_dev; i++) {
 		host = pci_find_device (PCI_VENDOR_ID_SI,
 					SiSHostChipInfo[i].host_id,
 					NULL);
@@ -583,30 +777,67 @@
 			continue;
 
 		host_dev = host;
+		dma_capability = SiSHostChipInfo[i].dma_capability;
 		printk(SiSHostChipInfo[i].name);
 		printk("\n");
-		if (SiSHostChipInfo[i].flags & SIS5513_FLAG_LATENCY) {
-			if (latency != 0x10)
-				pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
+
+		if (SiSHostChipInfo[i].flags & SIS5513_LATENCY) {
+			byte latency = (dma_capability == ATA_100)? 0x80 : 0x10; /* Lacking specs */
+			pci_write_config_byte(dev, PCI_LATENCY_TIMER, latency);
 		}
 	}
 
+	/* Make general config ops here
+	   1/ tell IDE channels to operate in Compabitility mode only
+	   2/ tell old chips to allow per drive IDE timings */
 	if (host_dev) {
-		byte reg52h = 0;
-
-		pci_read_config_byte(dev, 0x52, &reg52h);
-		if (!(reg52h & 0x04)) {
-			/* set IDE controller to operate in Compabitility mode only */
-			pci_write_config_byte(dev, 0x52, reg52h|0x04);
+		byte reg;
+		switch(dma_capability) {
+			case ATA_133:
+			case ATA_100:
+				/* Set compatibility bit */
+				pci_read_config_byte(dev, 0x49, &reg);
+				if (!(reg & 0x01)) {
+					pci_write_config_byte(dev, 0x49, reg|0x01);
+				}
+				break;
+			case ATA_100a:
+			case ATA_66:
+				/* On ATA_66 chips the bit was elsewhere */
+				pci_read_config_byte(dev, 0x52, &reg);
+				if (!(reg & 0x04)) {
+					pci_write_config_byte(dev, 0x52, reg|0x04);
+				}
+				break;
+			case ATA_33:
+				/* On ATA_33 we didn't have a single bit to set */
+				pci_read_config_byte(dev, 0x09, &reg);
+				if ((reg & 0x0f) != 0x00) {
+					pci_write_config_byte(dev, 0x09, reg&0xf0);
+				}
+			case ATA_16:
+				/* force per drive recovery and active timings
+				   needed on ATA_33 and below chips */
+				pci_read_config_byte(dev, 0x52, &reg);
+				if (!(reg & 0x08)) {
+					pci_write_config_byte(dev, 0x52, reg|0x08);
+				}
+				break;
+			case ATA_00:
+			default: break;
 		}
+
 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 		if (!sis_proc) {
 			sis_proc = 1;
 			bmide_dev = dev;
 			sis_display_info = &sis_get_info;
 		}
-#endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
+#endif
 	}
+#ifdef DEBUG
+	sis5513_load_verify_registers(dev, "pci_init_sis5513 end");
+#endif
 	return 0;
 }
 
@@ -616,27 +847,10 @@
 	byte mask = hwif->channel ? 0x20 : 0x10;
 	pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
 
-	if (host_dev) {
-		switch(host_dev->device) {
-			case PCI_DEVICE_ID_SI_530:
-			case PCI_DEVICE_ID_SI_540:
-			case PCI_DEVICE_ID_SI_620:
-			case PCI_DEVICE_ID_SI_630:
-			case PCI_DEVICE_ID_SI_635:
-			case PCI_DEVICE_ID_SI_640:
-			case PCI_DEVICE_ID_SI_645:
-			case PCI_DEVICE_ID_SI_650:
-			case PCI_DEVICE_ID_SI_730:
-			case PCI_DEVICE_ID_SI_735:
-			case PCI_DEVICE_ID_SI_740:
-			case PCI_DEVICE_ID_SI_745:
-			case PCI_DEVICE_ID_SI_750:
-				ata66 = (reg48h & mask) ? 0 : 1;
-			default:
-				break;
-		}
+	if (dma_capability >= ATA_66) {
+		ata66 = (reg48h & mask) ? 0 : 1;
 	}
-        return (ata66);
+        return ata66;
 }
 
 void __init ide_init_sis5513 (ide_hwif_t *hwif)
@@ -651,34 +865,17 @@
 		return;
 
 	if (host_dev) {
-		switch(host_dev->device) {
 #ifdef CONFIG_BLK_DEV_IDEDMA
-			case PCI_DEVICE_ID_SI_530:
-			case PCI_DEVICE_ID_SI_540:
-			case PCI_DEVICE_ID_SI_620:
-			case PCI_DEVICE_ID_SI_630:
-			case PCI_DEVICE_ID_SI_635:
-			case PCI_DEVICE_ID_SI_640:
-			case PCI_DEVICE_ID_SI_645:
-			case PCI_DEVICE_ID_SI_650:
-			case PCI_DEVICE_ID_SI_730:
-			case PCI_DEVICE_ID_SI_735:
-			case PCI_DEVICE_ID_SI_740:
-			case PCI_DEVICE_ID_SI_745:
-			case PCI_DEVICE_ID_SI_750:
-			case PCI_DEVICE_ID_SI_5600:
-			case PCI_DEVICE_ID_SI_5597:
-			case PCI_DEVICE_ID_SI_5591:
-				if (!noautodma)
-					hwif->autodma = 1;
-				hwif->highmem = 1;
-				hwif->dmaproc = &sis5513_dmaproc;
-				break;
-#endif /* CONFIG_BLK_DEV_IDEDMA */
-			default:
-				hwif->autodma = 0;
-				break;
+		if (dma_capability > ATA_16) {
+			hwif->autodma = noautodma ? 0 : 1;
+			hwif->highmem = 1;
+			hwif->dmaproc = &sis5513_dmaproc;
+		} else {
+#endif
+			hwif->autodma = 0;
+#ifdef CONFIG_BLK_DEV_IDEDMA
 		}
+#endif
 	}
 	return;
 }
diff -Nru a/drivers/ide/sl82c105.c b/drivers/ide/sl82c105.c
--- a/drivers/ide/sl82c105.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/sl82c105.c	Fri Mar 15 17:51:02 2002
@@ -22,7 +22,7 @@
 #include <asm/io.h>
 #include <asm/dma.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 extern char *ide_xfer_verbose (byte xfer_rate);
 
@@ -31,13 +31,13 @@
  * times for the interface.  This has protection against run-away
  * timings.
  */
-static unsigned int get_timing_sl82c105(ide_pio_data_t *p)
+static unsigned int get_timing_sl82c105(struct ata_timing *t)
 {
 	unsigned int cmd_on;
 	unsigned int cmd_off;
 
-	cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
-	cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
+	cmd_on = (t->active + 29) / 30;
+	cmd_off = (t->cycle - 30 * cmd_on + 29) / 30;
 
 	if (cmd_on > 32)
 		cmd_on = 32;
@@ -49,7 +49,7 @@
 	if (cmd_off == 0)
 		cmd_off = 1;
 
-	return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
+	return (cmd_on - 1) << 8 | (cmd_off - 1) | ((t->mode > XFER_PIO_2) ? 0x40 : 0x00);
 }
 
 /*
@@ -59,25 +59,21 @@
 {
 	ide_hwif_t *hwif = HWIF(drive);
 	struct pci_dev *dev = hwif->pci_dev;
-	ide_pio_data_t p;
+	struct ata_timing *t;
 	unsigned short drv_ctrl = 0x909;
 	unsigned int xfer_mode, reg;
 
 	reg = (hwif->channel ? 0x4c : 0x44) + (drive->select.b.unit ? 4 : 0);
 
-	pio = ide_get_best_pio_mode(drive, pio, 5, &p);
+	if (pio == 255)
+		xfer_mode = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
+	else
+		xfer_mode = XFER_PIO_0 + min_t(byte, pio, 4);
 
-	switch (pio) {
-	default:
-	case 0:		xfer_mode = XFER_PIO_0;		break;
-	case 1:		xfer_mode = XFER_PIO_1;		break;
-	case 2:		xfer_mode = XFER_PIO_2;		break;
-	case 3:		xfer_mode = XFER_PIO_3;		break;
-	case 4:		xfer_mode = XFER_PIO_4;		break;
-	}
+	t = ata_timing_data(xfer_mode);
 
 	if (ide_config_drive_speed(drive, xfer_mode) == 0)
-		drv_ctrl = get_timing_sl82c105(&p);
+		drv_ctrl = get_timing_sl82c105(t);
 
 	if (drive->using_dma == 0) {
 		/*
@@ -89,7 +85,7 @@
 
 		if (report) {
 			printk("%s: selected %s (%dns) (%04X)\n", drive->name,
-			       ide_xfer_verbose(xfer_mode), p.cycle_time, drv_ctrl);
+			       ide_xfer_verbose(xfer_mode), t->cycle, drv_ctrl);
 		}
 	}
 }
diff -Nru a/drivers/ide/slc90e66.c b/drivers/ide/slc90e66.c
--- a/drivers/ide/slc90e66.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/ide/slc90e66.c	Fri Mar 15 17:51:01 2002
@@ -48,7 +48,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 #define SLC90E66_DEBUG_DRIVE_INFO		0
 
@@ -202,7 +202,11 @@
 				    { 2, 1 },
 				    { 2, 3 }, };
 
-	pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
+	else
+		pio = min_t(byte, pio, 4);
+
 	pci_read_config_word(HWIF(drive)->pci_dev, master_port, &master_data);
 	if (is_slave) {
 		master_data = master_data | 0x4000;
@@ -299,30 +303,14 @@
 
 #if 1 /* allow PIO modes */
 	if (!HWIF(drive)->autodma) {
-		speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
+		speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO);
 		(void) slc90e66_tune_chipset(drive, speed);
 		return ((int) ide_dma_off_quietly);
 	}
 #endif
-	if ((id->dma_ultra & 0x0010) && (ultra)) {
-		speed = (udma_66) ? XFER_UDMA_4 : XFER_UDMA_2;
-	} else if ((id->dma_ultra & 0x0008) && (ultra)) {
-		speed = (udma_66) ? XFER_UDMA_3 : XFER_UDMA_1;
-	} else if ((id->dma_ultra & 0x0004) && (ultra)) {
-		speed = XFER_UDMA_2;
-	} else if ((id->dma_ultra & 0x0002) && (ultra)) {
-		speed = XFER_UDMA_1;
-	} else if ((id->dma_ultra & 0x0001) && (ultra)) {
-		speed = XFER_UDMA_0;
-	} else if (id->dma_mword & 0x0004) {
-		speed = XFER_MW_DMA_2;
-	} else if (id->dma_mword & 0x0002) {
-		speed = XFER_MW_DMA_1;
-	} else if (id->dma_1word & 0x0004) {
-		speed = XFER_SW_DMA_2;
-        } else {
-		speed = XFER_PIO_0 + ide_get_best_pio_mode(drive, 255, 5, NULL);
-	}
+
+	speed = ata_timing_mode(drive, XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA 
+					| (ultra ? XFER_UDMA : 0) | ((ultra && udma_66) ? XFER_UDMA_66 : 0));
 
 	(void) slc90e66_tune_chipset(drive, speed);
 
diff -Nru a/drivers/ide/umc8672.c b/drivers/ide/umc8672.c
--- a/drivers/ide/umc8672.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/umc8672.c	Fri Mar 15 17:51:02 2002
@@ -52,7 +52,7 @@
 
 #include <asm/io.h>
 
-#include "ide_modes.h"
+#include "ata-timing.h"
 
 /*
  * Default speeds.  These can be changed with "auto-tune" and/or hdparm.
@@ -113,7 +113,11 @@
 	unsigned long flags;
 	ide_hwgroup_t *hwgroup = ide_hwifs[HWIF(drive)->index^1].hwgroup;
 
-	pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
+	if (pio == 255)
+		pio = ata_timing_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
+	else
+		pio = min_t(byte, pio, 4);
+
 	printk("%s: setting umc8672 to PIO mode%d (speed %d)\n", drive->name, pio, pio_to_umc[pio]);
 	save_flags(flags);	/* all CPUs */
 	cli();			/* all CPUs */
diff -Nru a/drivers/ide/via82cxxx.c b/drivers/ide/via82cxxx.c
--- a/drivers/ide/via82cxxx.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/ide/via82cxxx.c	Fri Mar 15 17:51:02 2002
@@ -1,5 +1,5 @@
 /*
- * $Id: via82cxxx.c,v 3.33 2001/12/23 22:46:12 vojtech Exp $
+ * $Id: via82cxxx.c,v 3.34 2002/02/12 11:26:11 vojtech Exp $
  *
  *  Copyright (c) 2000-2001 Vojtech Pavlik
  *
@@ -67,7 +67,7 @@
 #include <linux/ide.h>
 #include <asm/io.h>
 
-#include "ide-timing.h"
+#include "ata-timing.h"
 
 #define VIA_IDE_ENABLE		0x40
 #define VIA_IDE_CONFIG		0x41
@@ -163,7 +163,7 @@
 
 	via_print("----------VIA BusMastering IDE Configuration----------------");
 
-	via_print("Driver Version:                     3.33");
+	via_print("Driver Version:                     3.34");
 	via_print("South Bridge:                       VIA %s", via_config->name);
 
 	pci_read_config_byte(isa_dev, PCI_REVISION_ID, &t);
@@ -269,7 +269,7 @@
  * via_set_speed() writes timing values to the chipset registers
  */
 
-static void via_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
+static void via_set_speed(struct pci_dev *dev, unsigned char dn, struct ata_timing *timing)
 {
 	unsigned char t;
 
@@ -303,7 +303,7 @@
 static int via_set_drive(ide_drive_t *drive, unsigned char speed)
 {
 	ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
-	struct ide_timing t, p;
+	struct ata_timing t, p;
 	unsigned int T, UT;
 
 	if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
@@ -321,11 +321,11 @@
 		default: UT = T;
 	}
 
-	ide_timing_compute(drive, speed, &t, T, UT);
+	ata_timing_compute(drive, speed, &t, T, UT);
 
 	if (peer->present) {
-		ide_timing_compute(peer, peer->current_speed, &p, T, UT);
-		ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
+		ata_timing_compute(peer, peer->current_speed, &p, T, UT);
+		ata_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
 	}
 
 	via_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
@@ -348,11 +348,11 @@
 		return;
 
 	if (pio == 255) {
-		via_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
+		via_set_drive(drive, ata_timing_mode(drive, XFER_PIO | XFER_EPIO));
 		return;
 	}
 
-	via_set_drive(drive, XFER_PIO_0 + MIN(pio, 5));
+	via_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
 }
 
 #ifdef CONFIG_BLK_DEV_IDEDMA
@@ -370,7 +370,7 @@
 
 		short w80 = HWIF(drive)->udma_four;
 
-		short speed = ide_find_best_mode(drive,
+		short speed = ata_timing_mode(drive,
 			XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
 			(via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
 			(w80 && (via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
@@ -495,7 +495,7 @@
 	if (via_clock < 20000 || via_clock > 50000) {
 		printk(KERN_WARNING "VP_IDE: User given PCI clock speed impossible (%d), using 33 MHz instead.\n", via_clock);
 		printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want to assume 80-wire cable.\n");
-		via_clock = 33;
+		via_clock = 33333;
 	}
 
 /*
diff -Nru a/drivers/isdn/Makefile b/drivers/isdn/Makefile
--- a/drivers/isdn/Makefile	Fri Mar 15 17:51:04 2002
+++ b/drivers/isdn/Makefile	Fri Mar 15 17:51:04 2002
@@ -10,7 +10,6 @@
 
 # Multipart objects.
 
-list-multi	:= isdn.o
 isdn-objs	:= isdn_net.o isdn_tty.o isdn_v110.o isdn_common.o
 
 # Optional parts of multipart objects.
@@ -50,8 +49,3 @@
 # The global Rules.make.
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-isdn.o: $(isdn-objs)
-	$(LD) -r -o $@ $(isdn-objs)
diff -Nru a/drivers/isdn/act2000/Makefile b/drivers/isdn/act2000/Makefile
--- a/drivers/isdn/act2000/Makefile	Fri Mar 15 17:51:03 2002
+++ b/drivers/isdn/act2000/Makefile	Fri Mar 15 17:51:03 2002
@@ -6,7 +6,6 @@
 
 # Multipart objects.
 
-list-multi	:= act2000.o
 act2000-objs	:= module.o capi.o act2000_isa.o
 
 # Each configuration option enables a list of files.
@@ -14,8 +13,3 @@
 obj-$(CONFIG_ISDN_DRV_ACT2000)	+= act2000.o
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-act2000.o: $(act2000-objs)
-	$(LD) -r -o $@ $(act2000-objs)
diff -Nru a/drivers/isdn/avmb1/Makefile b/drivers/isdn/avmb1/Makefile
--- a/drivers/isdn/avmb1/Makefile	Fri Mar 15 17:51:03 2002
+++ b/drivers/isdn/avmb1/Makefile	Fri Mar 15 17:51:03 2002
@@ -10,7 +10,6 @@
 
 # Multipart objects.
 
-list-multi	:= kernelcapi.o
 kernelcapi-objs	:= kcapi.o
 
 # Ordering constraints: kernelcapi.o first
@@ -32,9 +31,3 @@
 # The global Rules.make.
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-kernelcapi.o: $(kernelcapi-objs)
-	$(LD) -r -o $@ $(kernelcapi-objs)
-
diff -Nru a/drivers/isdn/avmb1/capifs.c b/drivers/isdn/avmb1/capifs.c
--- a/drivers/isdn/avmb1/capifs.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/isdn/avmb1/capifs.c	Fri Mar 15 17:51:02 2002
@@ -387,6 +387,7 @@
 	owner:		THIS_MODULE,
 	name:		"capifs",
 	get_sb:		capifs_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 void capifs_new_ncci(char type, unsigned int num, kdev_t device)
diff -Nru a/drivers/isdn/divert/Makefile b/drivers/isdn/divert/Makefile
--- a/drivers/isdn/divert/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/isdn/divert/Makefile	Fri Mar 15 17:51:01 2002
@@ -8,7 +8,6 @@
 
 # Multipart objects.
 
-list-multi		:= dss1_divert.o
 dss1_divert-objs	:= isdn_divert.o divert_procfs.o divert_init.o
 
 # Each configuration option enables a list of files.
@@ -16,12 +15,6 @@
 obj-$(CONFIG_ISDN_DIVERSION)	+= dss1_divert.o
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-dss1_divert.o: $(dss1_divert-objs)
-	$(LD) -r -o $@ $(dss1_divert-objs)
-
 
 
 
diff -Nru a/drivers/isdn/eicon/Makefile b/drivers/isdn/eicon/Makefile
--- a/drivers/isdn/eicon/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/isdn/eicon/Makefile	Fri Mar 15 17:51:02 2002
@@ -10,7 +10,6 @@
 
 # Multipart objects.
 
-list-multi	:= eicon.o divas.o
 eicon-objs	:= eicon_mod.o eicon_isa.o eicon_pci.o eicon_idi.o \
 		   eicon_io.o
 divas-objs	:= common.o idi.o bri.o pri.o log.o xlog.o kprintf.o fpga.o \
@@ -30,13 +29,3 @@
 obj-$(CONFIG_ISDN_DRV_EICON_DIVAS)	+= divas.o
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-eicon.o: $(eicon-objs)
-	$(LD) -r -o $@ $(eicon-objs)
-
-divas.o: $(divas-objs)
-	$(LD) -r -o $@ $(divas-objs)
-
-
diff -Nru a/drivers/isdn/hisax/Makefile b/drivers/isdn/hisax/Makefile
--- a/drivers/isdn/hisax/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/isdn/hisax/Makefile	Fri Mar 15 17:51:02 2002
@@ -14,7 +14,6 @@
 
 # Multipart objects.
 
-list-multi	  := hisax.o hisax_st5481.o
 hisax-objs	  := config.o isdnl1.o tei.o isdnl2.o isdnl3.o \
 		     lmgr.o q931.o callc.o fsm.o cert.o
 hisax_st5481-objs := st5481_init.o st5481_usb.o st5481_d.o st5481_b.o \
@@ -54,7 +53,7 @@
 hisax-objs-$(CONFIG_HISAX_W6692) += w6692.o
 #hisax-objs-$(CONFIG_HISAX_TESTEMU) += testemu.o
 
-hisax-objs += $(sort $(hisax-objs-y))
+hisax-objs += $(hisax-objs-y)
 
 # Each configuration option enables a list of files.
 
@@ -70,11 +69,3 @@
 CFLAGS_cert.o := -DCERTIFICATION=$(CERT)
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-hisax.o: $(hisax-objs)
-	$(LD) -r -o $@ $(hisax-objs)
-
-hisax_st5481.o: $(hisax_st5481-objs)
-	$(LD) -r -o $@ $(hisax_st5481-objs)
diff -Nru a/drivers/isdn/hysdn/Makefile b/drivers/isdn/hysdn/Makefile
--- a/drivers/isdn/hysdn/Makefile	Fri Mar 15 17:51:03 2002
+++ b/drivers/isdn/hysdn/Makefile	Fri Mar 15 17:51:03 2002
@@ -6,7 +6,6 @@
 
 # Multipart objects.
 
-list-multi	:= hysdn.o
 hysdn-objs	:= hysdn_procconf.o hysdn_proclog.o boardergo.o hysdn_boot.o \
 		   hysdn_sched.o hysdn_net.o hysdn_init.o
 
@@ -21,9 +20,3 @@
 obj-$(CONFIG_HYSDN)	+= hysdn.o
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-hysdn.o: $(hysdn-objs)
-	$(LD) -r -o $@ $(hysdn-objs)
-
diff -Nru a/drivers/isdn/pcbit/Makefile b/drivers/isdn/pcbit/Makefile
--- a/drivers/isdn/pcbit/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/isdn/pcbit/Makefile	Fri Mar 15 17:51:02 2002
@@ -6,7 +6,6 @@
 
 # Multipart objects.
 
-list-multi	:= pcbit.o
 pcbit-objs	:= module.o edss1.o drv.o layer2.o capi.o callbacks.o
 
 # Each configuration option enables a list of files.
@@ -14,8 +13,3 @@
 obj-$(CONFIG_ISDN_DRV_PCBIT)	+= pcbit.o
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-pcbit.o: $(pcbit-objs)
-	$(LD) -r -o $@ $(pcbit-objs)
diff -Nru a/drivers/isdn/sc/Makefile b/drivers/isdn/sc/Makefile
--- a/drivers/isdn/sc/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/isdn/sc/Makefile	Fri Mar 15 17:51:02 2002
@@ -6,7 +6,6 @@
 
 # Multipart objects.
 
-list-multi	:= sc.o
 sc-objs		:= shmem.o init.o debug.o packet.o command.o event.o \
 		   ioctl.o interrupt.o message.o timer.o	
 
@@ -15,8 +14,3 @@
 obj-$(CONFIG_ISDN_DRV_SC)	+= sc.o
 
 include $(TOPDIR)/Rules.make
-
-# Link rules for multi-part drivers.
-
-sc.o: $(sc-objs)
-	$(LD) -r -o $@ $(sc-objs)
diff -Nru a/drivers/media/radio/miropcm20-radio.c b/drivers/media/radio/miropcm20-radio.c
--- a/drivers/media/radio/miropcm20-radio.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/radio/miropcm20-radio.c	Fri Mar 15 17:51:02 2002
@@ -22,10 +22,9 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/videodev.h>
-#include "../../sound/aci.h"
+#include "../../../sound/oss/aci.h"
 #include "miropcm20-rds-core.h"
 
-static int users = 0;
 static int radio_nr = -1;
 MODULE_PARM(radio_nr, "i");
 
@@ -122,96 +121,86 @@
 	return 0;
 }
 
-static int pcm20_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int pcm20_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
-	struct pcm20_device *pcm20=dev->priv;
+	struct video_device *dev = video_devdata(file);
+	struct pcm20_device *pcm20 = dev->priv;
 	int i;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			strcpy(v.name, "Miro PCM20");
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			strcpy(v->name, "Miro PCM20");
+			v->channels=1;
+			v->audios=1;
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			struct video_tuner *v = arg;
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow=87*16000;
-			v.rangehigh=108*16000;
-			pcm20_getflags(pcm20, &v.flags, &v.signal);
-			v.flags|=VIDEO_TUNER_LOW;
-			v.mode=VIDEO_MODE_AUTO;
-			strcpy(v.name, "FM");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow=87*16000;
+			v->rangehigh=108*16000;
+			pcm20_getflags(pcm20, &v->flags, &v->signal);
+			v->flags|=VIDEO_TUNER_LOW;
+			v->mode=VIDEO_MODE_AUTO;
+			strcpy(v->name, "FM");
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &pcm20->freq, sizeof(pcm20->freq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = pcm20->freq;
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&pcm20->freq, arg, sizeof(pcm20->freq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			pcm20->freq = *freq;
 			i=pcm20_setfreq(pcm20, pcm20->freq);
 #if DEBUG
 			printk("First view (setfreq): 0x%x\n", i);
 #endif
 			return i;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags=VIDEO_AUDIO_MUTABLE;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags=VIDEO_AUDIO_MUTABLE;
 			if (pcm20->muted)
-				v.flags|=VIDEO_AUDIO_MUTE;
-			v.mode=VIDEO_SOUND_STEREO;
+				v->flags|=VIDEO_AUDIO_MUTE;
+			v->mode=VIDEO_SOUND_STEREO;
 			if (pcm20->stereo)
-				v.mode|=VIDEO_SOUND_MONO;
-			/* v.step=2048; */
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+				v->mode|=VIDEO_SOUND_MONO;
+			/* v->step=2048; */
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
 
-			pcm20_mute(pcm20, !!(v.flags&VIDEO_AUDIO_MUTE));
-			if(v.flags&VIDEO_SOUND_MONO)
+			pcm20_mute(pcm20, !!(v->flags&VIDEO_AUDIO_MUTE));
+			if(v->flags&VIDEO_SOUND_MONO)
 				pcm20_stereo(pcm20, 0);
-			if(v.flags&VIDEO_SOUND_STEREO)
+			if(v->flags&VIDEO_SOUND_STEREO)
 				pcm20_stereo(pcm20, 1);
 
 			return 0;
@@ -221,35 +210,27 @@
 	}
 }
 
-static int pcm20_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	MOD_INC_USE_COUNT;
-	return 0;
-}
-
-static void pcm20_close(struct video_device *dev)
-{
-	users--;
-	MOD_DEC_USE_COUNT;
-}
-
 static struct pcm20_device pcm20_unit = {
 	freq:   87*16000,
 	muted:  1,
 	stereo: 0
 };
 
+static struct file_operations pcm20_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device pcm20_radio = {
 	owner:		THIS_MODULE,
 	name:		"Miro PCM 20 radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_RTRACK,
-	open:		pcm20_open,
-	close:		pcm20_close,
-	ioctl:		pcm20_ioctl,
+	fops:           &pcm20_fops,
+	kernel_ioctl:	pcm20_ioctl,
 	priv:		&pcm20_unit
 };
 
diff -Nru a/drivers/media/radio/miropcm20-rds-core.c b/drivers/media/radio/miropcm20-rds-core.c
--- a/drivers/media/radio/miropcm20-rds-core.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/radio/miropcm20-rds-core.c	Fri Mar 15 17:51:03 2002
@@ -21,7 +21,7 @@
 #include <linux/slab.h>
 #include <asm/semaphore.h>
 #include <asm/io.h>
-#include "../../sound/aci.h"
+#include "../../../sound/oss/aci.h"
 #include "miropcm20-rds-core.h"
 
 #define DEBUG 0
diff -Nru a/drivers/media/radio/radio-aimslab.c b/drivers/media/radio/radio-aimslab.c
--- a/drivers/media/radio/radio-aimslab.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/radio/radio-aimslab.c	Fri Mar 15 17:51:02 2002
@@ -43,7 +43,6 @@
 
 static int io = CONFIG_RADIO_RTRACK_PORT; 
 static int radio_nr = -1;
-static int users = 0;
 static struct semaphore lock;
 
 struct rt_device
@@ -214,89 +213,77 @@
 	return 1;		/* signal present		*/
 }
 
-static int rt_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int rt_ioctl(struct inode *inode, struct file *file,
+		    unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct rt_device *rt=dev->priv;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "RadioTrack");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "RadioTrack");
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			struct video_tuner *v = arg;
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow=(87*16000);
-			v.rangehigh=(108*16000);
-			v.flags=VIDEO_TUNER_LOW;
-			v.mode=VIDEO_MODE_AUTO;
-			strcpy(v.name, "FM");
-			v.signal=0xFFFF*rt_getsigstr(rt);
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow=(87*16000);
+			v->rangehigh=(108*16000);
+			v->flags=VIDEO_TUNER_LOW;
+			v->mode=VIDEO_MODE_AUTO;
+			strcpy(v->name, "FM");
+			v->signal=0xFFFF*rt_getsigstr(rt);
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &rt->curfreq, sizeof(rt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = rt->curfreq;
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&rt->curfreq, arg,sizeof(rt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			rt->curfreq = *freq;
 			rt_setfreq(rt, rt->curfreq);
 			return 0;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags|=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
-			v.volume=rt->curvol * 6554;
-			v.step=6554;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags|=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
+			v->volume=rt->curvol * 6554;
+			v->step=6554;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
-
-			if(v.flags&VIDEO_AUDIO_MUTE) 
+			if(v->flags&VIDEO_AUDIO_MUTE) 
 				rt_mute(rt);
 			else
-				rt_setvol(rt,v.volume/6554);	
-
+				rt_setvol(rt,v->volume/6554);
 			return 0;
 		}
 		default:
@@ -304,30 +291,24 @@
 	}
 }
 
-static int rt_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void rt_close(struct video_device *dev)
-{
-	users--;
-}
-
 static struct rt_device rtrack_unit;
 
+static struct file_operations rtrack_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device rtrack_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"RadioTrack radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_RTRACK,
-	open:		rt_open,
-	close:		rt_close,
-	ioctl:		rt_ioctl,
+	fops:           &rtrack_fops,
+	kernel_ioctl:	rt_ioctl,
 };
 
 static int __init rtrack_init(void)
diff -Nru a/drivers/media/radio/radio-aztech.c b/drivers/media/radio/radio-aztech.c
--- a/drivers/media/radio/radio-aztech.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/radio/radio-aztech.c	Fri Mar 15 17:51:03 2002
@@ -42,7 +42,6 @@
 static int io = CONFIG_RADIO_AZTECH_PORT; 
 static int radio_nr = -1;
 static int radio_wait_time = 1000;
-static int users = 0;
 static struct semaphore lock;
 
 struct az_device
@@ -158,96 +157,85 @@
 	return 0;
 }
 
-static int az_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int az_ioctl(struct inode *inode, struct file *file,
+		    unsigned int cmd, void *arg)
 {
-	struct az_device *az=dev->priv;
+	struct video_device *dev = video_devdata(file);
+	struct az_device *az = dev->priv;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "Aztech Radio");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "Aztech Radio");
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			struct video_tuner *v = arg;
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow=(87*16000);
-			v.rangehigh=(108*16000);
-			v.flags=VIDEO_TUNER_LOW;
-			v.mode=VIDEO_MODE_AUTO;
-			v.signal=0xFFFF*az_getsigstr(az);
+			v->rangelow=(87*16000);
+			v->rangehigh=(108*16000);
+			v->flags=VIDEO_TUNER_LOW;
+			v->mode=VIDEO_MODE_AUTO;
+			v->signal=0xFFFF*az_getsigstr(az);
 			if(az_getstereo(az))
-				v.flags|=VIDEO_TUNER_STEREO_ON;
-			strcpy(v.name, "FM");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+				v->flags|=VIDEO_TUNER_STEREO_ON;
+			strcpy(v->name, "FM");
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
-			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &az->curfreq, sizeof(az->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = az->curfreq;
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&az->curfreq, arg,sizeof(az->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			az->curfreq = *freq;
 			az_setfreq(az, az->curfreq);
 			return 0;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags|=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags|=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
 			if(az->stereo)
-				v.mode=VIDEO_SOUND_STEREO;
+				v->mode=VIDEO_SOUND_STEREO;
 			else
-				v.mode=VIDEO_SOUND_MONO;
-			v.volume=az->curvol;
-			v.step=16384;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+				v->mode=VIDEO_SOUND_MONO;
+			v->volume=az->curvol;
+			v->step=16384;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
-			az->curvol=v.volume;
+			az->curvol=v->volume;
 
-			az->stereo=(v.mode&VIDEO_SOUND_STEREO)?1:0;
-			if(v.flags&VIDEO_AUDIO_MUTE) 
+			az->stereo=(v->mode&VIDEO_SOUND_STEREO)?1:0;
+			if(v->flags&VIDEO_AUDIO_MUTE) 
 				az_setvol(az,0);
 			else
-				az_setvol(az,az->curvol);								
+				az_setvol(az,az->curvol);
 			return 0;
 		}
 		default:
@@ -255,30 +243,24 @@
 	}
 }
 
-static int az_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void az_close(struct video_device *dev)
-{
-	users--;
-}
-
 static struct az_device aztech_unit;
 
+static struct file_operations aztech_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device aztech_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"Aztech radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_AZTECH,
-	open:		az_open,
-	close:		az_close,
-	ioctl:		az_ioctl,
+	fops:           &aztech_fops,
+	kernel_ioctl:   az_ioctl,
 };
 
 static int __init aztech_init(void)
diff -Nru a/drivers/media/radio/radio-cadet.c b/drivers/media/radio/radio-cadet.c
--- a/drivers/media/radio/radio-cadet.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/radio/radio-cadet.c	Fri Mar 15 17:51:03 2002
@@ -351,8 +351,8 @@
 
 
 
-static long cadet_read(struct video_device *v,char *buf,unsigned long count,
-		       int nonblock)
+static ssize_t cadet_read(struct file *file, char *data,
+			  size_t count, loff_t *ppos)
 {
         int i=0;
 	unsigned char readbuf[RDS_BUFFER];
@@ -369,7 +369,7 @@
 		add_timer(&readtimer);
 	}
 	if(rdsin==rdsout) {
-  	        if(nonblock) {
+  	        if (file->f_flags & O_NONBLOCK) {
 		        return -EWOULDBLOCK;
 		}
 	        interruptible_sleep_on(&readq);
@@ -377,70 +377,60 @@
 	while((i<count)&&(rdsin!=rdsout)) {
 	        readbuf[i++]=rdsbuf[rdsout++];
 	}
-	if(copy_to_user(buf,readbuf,i)) {
+	if (copy_to_user(data,readbuf,i))
 	        return -EFAULT;
-	}
 	return i;
 }
 
 
 
-static int cadet_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int cadet_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
-        unsigned freq;
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=2;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "ADS Cadet");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=2;
+			v->audios=1;
+			strcpy(v->name, "ADS Cadet");
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) { 
-				return -EFAULT;
-			}
-			if((v.tuner<0)||(v.tuner>1)) {
+			struct video_tuner *v = arg;
+			if((v->tuner<0)||(v->tuner>1)) {
 				return -EINVAL;
 			}
-			switch(v.tuner) {
+			switch(v->tuner) {
 			        case 0:
-			        strcpy(v.name,"FM");
-			        v.rangelow=1400;     /* 87.5 MHz */
-			        v.rangehigh=1728;    /* 108.0 MHz */
-			        v.flags=0;
-			        v.mode=0;
-			        v.mode|=VIDEO_MODE_AUTO;
-			        v.signal=sigstrength;
+			        strcpy(v->name,"FM");
+			        v->rangelow=1400;     /* 87.5 MHz */
+			        v->rangehigh=1728;    /* 108.0 MHz */
+			        v->flags=0;
+			        v->mode=0;
+			        v->mode|=VIDEO_MODE_AUTO;
+			        v->signal=sigstrength;
 			        if(cadet_getstereo()==1) {
-				        v.flags|=VIDEO_TUNER_STEREO_ON;
+				        v->flags|=VIDEO_TUNER_STEREO_ON;
 			        }
-				v.flags|=cadet_getrds();
+				v->flags|=cadet_getrds();
 			        if(copy_to_user(arg,&v, sizeof(v))) {
 				        return -EFAULT;
 			        }
 			        break;
 			        case 1:
-			        strcpy(v.name,"AM");
-			        v.rangelow=8320;      /* 520 kHz */
-			        v.rangehigh=26400;    /* 1650 kHz */
-			        v.flags=0;
-			        v.flags|=VIDEO_TUNER_LOW;
-			        v.mode=0;
-			        v.mode|=VIDEO_MODE_AUTO;
-			        v.signal=sigstrength;
+			        strcpy(v->name,"AM");
+			        v->rangelow=8320;      /* 520 kHz */
+			        v->rangehigh=26400;    /* 1650 kHz */
+			        v->flags=0;
+			        v->flags|=VIDEO_TUNER_LOW;
+			        v->mode=0;
+			        v->mode|=VIDEO_MODE_AUTO;
+			        v->signal=sigstrength;
 			        if(copy_to_user(arg,&v, sizeof(v))) {
 				        return -EFAULT;
 			        }
@@ -450,59 +440,53 @@
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))) {
-				return -EFAULT;
-			}
-			if((v.tuner<0)||(v.tuner>1)) {
+			struct video_tuner *v = arg;
+			if((v->tuner<0)||(v->tuner>1)) {
 				return -EINVAL;
 			}
-			curtuner=v.tuner;	
+			curtuner=v->tuner;	
 			return 0;
 		}
 		case VIDIOCGFREQ:
-		        freq=cadet_getfreq();
-			if(copy_to_user(arg, &freq, sizeof(freq)))
-				return -EFAULT;
+		{
+		        unsigned long *freq = arg;
+			*freq = cadet_getfreq();
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&freq, arg,sizeof(freq)))
-				return -EFAULT;
-			if((curtuner==0)&&((freq<1400)||(freq>1728))) {
+		{
+		        unsigned long *freq = arg;
+			if((curtuner==0)&&((*freq<1400)||(*freq>1728))) {
 			        return -EINVAL;
 			}
-			if((curtuner==1)&&((freq<8320)||(freq>26400))) {
+			if((curtuner==1)&&((*freq<8320)||(*freq>26400))) {
 			        return -EINVAL;
 			}
-			cadet_setfreq(freq);
+			cadet_setfreq(*freq);
 			return 0;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
 			if(cadet_getstereo()==0) {
-			        v.mode=VIDEO_SOUND_MONO;
-			}
-			else {
-			  v.mode=VIDEO_SOUND_STEREO;
-			}
-			v.volume=cadet_getvol();
-			v.step=0xffff;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			        v->mode=VIDEO_SOUND_MONO;
+			} else {
+				v->mode=VIDEO_SOUND_STEREO;
+			}
+			v->volume=cadet_getvol();
+			v->step=0xffff;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
-			cadet_setvol(v.volume);
-			if(v.flags&VIDEO_AUDIO_MUTE) 
+			cadet_setvol(v->volume);
+			if(v->flags&VIDEO_AUDIO_MUTE) 
 				cadet_setvol(0);
 			else
 				cadet_setvol(0xffff);
@@ -514,7 +498,7 @@
 }
 
 
-static int cadet_open(struct video_device *dev, int flags)
+static int cadet_open(struct inode *inode, struct file *file)
 {
 	if(users)
 		return -EBUSY;
@@ -523,26 +507,34 @@
 	return 0;
 }
 
-static void cadet_close(struct video_device *dev)
+static int cadet_release(struct inode *inode, struct file *file)
 {
         if(rdsstat==1) {
                 del_timer(&readtimer);
 		rdsstat=0;
 	}
 	users--;
+	return 0;
 }
 
 
+static struct file_operations cadet_fops = {
+	owner:		THIS_MODULE,
+	open:		cadet_open,
+	release:       	cadet_release,
+	read:		cadet_read,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device cadet_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"Cadet radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_CADET,
-	open:		cadet_open,
-	close:		cadet_close,
-	read:		cadet_read,
-	ioctl:		cadet_ioctl,
+	fops:           &cadet_fops,
+	kernel_ioctl:	cadet_ioctl,
 };
 
 static int isapnp_cadet_probe(void)
diff -Nru a/drivers/media/radio/radio-gemtek-pci.c b/drivers/media/radio/radio-gemtek-pci.c
--- a/drivers/media/radio/radio-gemtek-pci.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/radio/radio-gemtek-pci.c	Fri Mar 15 17:51:01 2002
@@ -90,24 +90,6 @@
 
 static int nr_radio = -1;
 
-static int gemtek_pci_open( struct video_device *dev, int flags)
-{
-	struct gemtek_pci_card *card =  dev->priv;
-
-/* Paranoid check */
-	if ( !card )
-		return -ENODEV;
-
-	return 0;
-}
-
-static void gemtek_pci_close( struct video_device *dev )
-{
-/*
- *  The module usage is managed by 'videodev'
- */
-}
-
 static inline u8 gemtek_pci_out( u16 value, u32 port )
 {
 	outw( value, port );
@@ -195,80 +177,65 @@
 	return ( inb( card->iobase ) & 0x08 ) ? 0 : 1;
 }
 
-static int gemtek_pci_ioctl( struct video_device *dev, unsigned int cmd, void *arg)
+static int gemtek_pci_ioctl(struct inode *inode, struct file *file,
+			    unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct gemtek_pci_card *card = dev->priv;
 
 	switch ( cmd ) {
 		case VIDIOCGCAP:
 		{
-			struct video_capability c;
-
-			c.type = VID_TYPE_TUNER;
-			c.channels = 1;
-			c.audios = 1;
-			c.maxwidth = 0;
-			c.maxheight = 0;
-			c.minwidth = 0;
-			c.minheight = 0;
-			strcpy( c.name, "Gemtek PCI Radio" );
-			if ( copy_to_user( arg, &c, sizeof( c ) ) )
-				return -EFAULT;
+			struct video_capability *c = arg;
 
+			memset(c,0,sizeof(*c));
+			c->type = VID_TYPE_TUNER;
+			c->channels = 1;
+			c->audios = 1;
+			strcpy( c->name, "Gemtek PCI Radio" );
 			return 0;
 		} 
 
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner t;
-
-			if ( copy_from_user( &t, arg, sizeof( struct video_tuner ) ) )
-				return -EFAULT;
+			struct video_tuner *t = arg;
 
-			if ( t.tuner ) 
+			if ( t->tuner ) 
 				return -EINVAL;
 
-			t.rangelow = GEMTEK_PCI_RANGE_LOW;
-			t.rangehigh = GEMTEK_PCI_RANGE_HIGH;
-			t.flags = VIDEO_TUNER_LOW;
-			t.mode = VIDEO_MODE_AUTO;
-			t.signal = 0xFFFF * gemtek_pci_getsignal( card );
-			strcpy( t.name, "FM" );
-
-			if ( copy_to_user( arg, &t, sizeof( struct video_tuner ) ) )
-				return -EFAULT;
-
+			t->rangelow = GEMTEK_PCI_RANGE_LOW;
+			t->rangehigh = GEMTEK_PCI_RANGE_HIGH;
+			t->flags = VIDEO_TUNER_LOW;
+			t->mode = VIDEO_MODE_AUTO;
+			t->signal = 0xFFFF * gemtek_pci_getsignal( card );
+			strcpy( t->name, "FM" );
 			return 0;
 		}
 
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner t;
-
-			if ( copy_from_user( &t, arg, sizeof( struct video_tuner ) ) )
-				return -EFAULT;
-
-			if ( t.tuner )
+			struct video_tuner *t = arg;
+			if ( t->tuner )
 				return -EINVAL;
-
 			return 0;
 		}
 
 		case VIDIOCGFREQ:
-			return put_user( card->current_frequency, (u32 *)arg );
-
+		{
+			unsigned long *freq = arg;
+			*freq = card->current_frequency;
+			return 0;
+		}
 		case VIDIOCSFREQ:
 		{
-			u32 frequency;
+			unsigned long *freq = arg;
 	 
-			if ( get_user( frequency, (u32 *)arg ) )
-				return -EFAULT;
-
-			if ( (frequency < GEMTEK_PCI_RANGE_LOW) || (frequency > GEMTEK_PCI_RANGE_HIGH) )
+			if ( (*freq < GEMTEK_PCI_RANGE_LOW) ||
+			     (*freq > GEMTEK_PCI_RANGE_HIGH) )
 				return -EINVAL;
 
-			gemtek_pci_setfrequency( card, frequency );
-			card->current_frequency = frequency;
+			gemtek_pci_setfrequency( card, *freq );
+			card->current_frequency = *freq;
 			card->mute = FALSE;
 
 			return 0;
@@ -276,36 +243,27 @@
   
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio a;
-
-			memset( &a, 0, sizeof( a ) );
-			a.flags |= VIDEO_AUDIO_MUTABLE;
-			a.volume = 1;
-			a.step = 65535;
-			strcpy( a.name, "Radio" );
-
-			if ( copy_to_user( arg, &a, sizeof( struct video_audio ) ) )
-				return -EFAULT;
+			struct video_audio *a = arg;
 
+			memset( a, 0, sizeof( *a ) );
+			a->flags |= VIDEO_AUDIO_MUTABLE;
+			a->volume = 1;
+			a->step = 65535;
+			strcpy( a->name, "Radio" );
 			return 0;			
 		}
 
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio a;
+			struct video_audio *a = arg;
 
-			if ( copy_from_user( &a, arg, sizeof( struct video_audio ) ) ) 
-				return -EFAULT;	
-
-			if ( a.audio ) 
+			if ( a->audio ) 
 				return -EINVAL;
 
-			if ( a.flags & VIDEO_AUDIO_MUTE ) 
+			if ( a->flags & VIDEO_AUDIO_MUTE ) 
 				gemtek_pci_mute( card );
-
 			else
 				gemtek_pci_unmute( card );
-
 			return 0;
 		}
 
@@ -333,19 +291,22 @@
 
 static u8 mx = 1;
 
-static char gemtek_pci_videodev_name[] = "Gemtek PCI Radio";
+static struct file_operations gemtek_pci_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
 
-static inline void gemtek_pci_init_struct( struct video_device *dev )
-{
-	memset( dev, 0, sizeof( struct video_device ) );
-	dev->owner = THIS_MODULE;
-	strcpy( dev->name , gemtek_pci_videodev_name );
-	dev->type = VID_TYPE_TUNER;
-	dev->hardware = VID_HARDWARE_GEMTEK;
-	dev->open = gemtek_pci_open;
-	dev->close = gemtek_pci_close;
-	dev->ioctl = gemtek_pci_ioctl;
-}
+static struct video_device vdev_template = {
+	owner:         THIS_MODULE,
+	name:          "Gemtek PCI Radio",
+	type:          VID_TYPE_TUNER,
+	hardware:      VID_HARDWARE_GEMTEK,
+	fops:          &gemtek_pci_fops,
+	kernel_ioctl:  gemtek_pci_ioctl,
+};
 
 static int __devinit gemtek_pci_probe( struct pci_dev *pci_dev, const struct pci_device_id *pci_id )
 {
@@ -378,7 +339,7 @@
 		printk( KERN_ERR "gemtek_pci: out of memory\n" );
 		goto err_video;
 	}
-	gemtek_pci_init_struct( devradio );
+	*devradio = vdev_template;
 
 	if ( video_register_device( devradio, VFL_TYPE_RADIO , nr_radio) == -1 ) {
 		kfree( devradio );
diff -Nru a/drivers/media/radio/radio-gemtek.c b/drivers/media/radio/radio-gemtek.c
--- a/drivers/media/radio/radio-gemtek.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/media/radio/radio-gemtek.c	Fri Mar 15 17:51:00 2002
@@ -31,7 +31,6 @@
 
 static int io = CONFIG_RADIO_GEMTEK_PORT; 
 static int radio_nr = -1;
-static int users = 0;
 static spinlock_t lock;
 
 struct gemtek_device
@@ -139,87 +138,77 @@
 	return 1;		/* signal present */
 }
 
-static int gemtek_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int gemtek_ioctl(struct inode *inode, struct file *file,
+			unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct gemtek_device *rt=dev->priv;
 
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "GemTek");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "GemTek");
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			struct video_tuner *v = arg;
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow=87*16000;
-			v.rangehigh=108*16000;
-			v.flags=VIDEO_TUNER_LOW;
-			v.mode=VIDEO_MODE_AUTO;
-			v.signal=0xFFFF*gemtek_getsigstr(rt);
-			strcpy(v.name, "FM");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow=87*16000;
+			v->rangehigh=108*16000;
+			v->flags=VIDEO_TUNER_LOW;
+			v->mode=VIDEO_MODE_AUTO;
+			v->signal=0xFFFF*gemtek_getsigstr(rt);
+			strcpy(v->name, "FM");
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &rt->curfreq, sizeof(rt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = rt->curfreq;
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&rt->curfreq, arg,sizeof(rt->curfreq)))
-				return -EFAULT;
-		/* needs to be called twice in order for getsigstr to work */
+		{
+			unsigned long *freq = arg;
+			rt->curfreq = *freq;
+			/* needs to be called twice in order for getsigstr to work */
 			gemtek_setfreq(rt, rt->curfreq);
 			gemtek_setfreq(rt, rt->curfreq);
 			return 0;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags|=VIDEO_AUDIO_MUTABLE;
-			v.volume=1;
-			v.step=65535;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = 0;
+			memset(v,0, sizeof(*v));
+			v->flags|=VIDEO_AUDIO_MUTABLE;
+			v->volume=1;
+			v->step=65535;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
 
-			if(v.flags&VIDEO_AUDIO_MUTE) 
+			if(v->flags&VIDEO_AUDIO_MUTE) 
 				gemtek_mute(rt);
 			else
 			        gemtek_unmute(rt);
@@ -231,30 +220,24 @@
 	}
 }
 
-static int gemtek_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void gemtek_close(struct video_device *dev)
-{
-	users--;
-}
-
 static struct gemtek_device gemtek_unit;
 
+static struct file_operations gemtek_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device gemtek_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"GemTek radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_GEMTEK,
-	open:		gemtek_open,
-	close:		gemtek_close,
-	ioctl:		gemtek_ioctl,
+	fops:           &gemtek_fops,
+	kernel_ioctl:	gemtek_ioctl,
 };
 
 static int __init gemtek_init(void)
diff -Nru a/drivers/media/radio/radio-maestro.c b/drivers/media/radio/radio-maestro.c
--- a/drivers/media/radio/radio-maestro.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/radio/radio-maestro.c	Fri Mar 15 17:51:03 2002
@@ -64,10 +64,16 @@
 static int radio_nr = -1;
 MODULE_PARM(radio_nr, "i");
 
+static int radio_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg);
 
-static int radio_open(struct video_device *, int);
-static int radio_ioctl(struct video_device *, unsigned int, void *);
-static void radio_close(struct video_device *);
+static struct file_operations maestro_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
 
 static struct video_device maestro_radio=
 {
@@ -75,9 +81,8 @@
 	name:		"Maestro radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_SF16MI,
-	open:		radio_open,
-	close:		radio_close,
-	ioctl:		radio_ioctl,
+	fops:           &maestro_fops,
+	kernel_ioctl:	radio_ioctl,
 };
 
 static struct radio_device
@@ -89,8 +94,6 @@
 	struct  semaphore lock;
 } radio_unit = {0, 0, 0, 0, };
 
-static int users = 0;
-
 static void sleep_125ms(void)
 {
 	current->state = TASK_INTERRUPTIBLE;
@@ -178,76 +181,61 @@
 	struct radio_device *card=dev->priv;
 	switch(cmd) {
 		case VIDIOCGCAP: {
-			struct video_capability v;
-			strcpy(v.name, "Maestro radio");
-			v.type=VID_TYPE_TUNER;
-			v.channels=v.audios=1;
-			v.maxwidth=v.maxheight=v.minwidth=v.minheight=0;
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			strcpy(v->name, "Maestro radio");
+			v->type=VID_TYPE_TUNER;
+			v->channels=v->audios=1;
 			return 0;
 		}
 		case VIDIOCGTUNER: {
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
+			struct video_tuner *v = arg;
+			if(v->tuner)
 				return -EINVAL;
 			(void)radio_bits_get(card);
-			v.flags = VIDEO_TUNER_LOW | card->stereo;
-			v.signal = card->tuned;
-			strcpy(v.name, "FM");
-			v.rangelow = FREQ_LO;
-			v.rangehigh = FREQ_HI;
-			v.mode = VIDEO_MODE_AUTO;
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->flags = VIDEO_TUNER_LOW | card->stereo;
+			v->signal = card->tuned;
+			strcpy(v->name, "FM");
+			v->rangelow = FREQ_LO;
+			v->rangehigh = FREQ_HI;
+			v->mode = VIDEO_MODE_AUTO;
 		        return 0;
 		}
 		case VIDIOCSTUNER: {
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			return 0;
 		}
 		case VIDIOCGFREQ: {
-			unsigned long tmp=BITS2FREQ(radio_bits_get(card));
-			if(copy_to_user(arg, &tmp, sizeof(tmp)))
-				return -EFAULT;
+			unsigned long *freq = arg;
+			*freq = BITS2FREQ(radio_bits_get(card));
 			return 0;
 		}
 		case VIDIOCSFREQ: {
-			unsigned long tmp;
-			if(copy_from_user(&tmp, arg, sizeof(tmp)))
-				return -EFAULT;
-			if ( tmp<FREQ_LO || tmp>FREQ_HI )
+			unsigned long *freq = arg;
+			if (*freq<FREQ_LO || *freq>FREQ_HI )
 				return -EINVAL;
-			radio_bits_set(card, FREQ2BITS(tmp));
+			radio_bits_set(card, FREQ2BITS(*freq));
 			return 0;
 		}
 		case VIDIOCGAUDIO: {	
-			struct video_audio v;
-			strcpy(v.name, "Radio");
-			v.audio=v.volume=v.bass=v.treble=v.balance=v.step=0;
-			v.flags=VIDEO_AUDIO_MUTABLE | card->muted;
-			v.mode=VIDEO_SOUND_STEREO;
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0,sizeof(*v));
+			strcpy(v->name, "Radio");
+			v->flags=VIDEO_AUDIO_MUTABLE | card->muted;
+			v->mode=VIDEO_SOUND_STEREO;
 			return 0;		
 		}
 		case VIDIOCSAUDIO: {
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.audio)
+			struct video_audio *v = arg;
+			if(v->audio)
 				return -EINVAL;
 			{
 				register __u16 io=card->io;
 				register __u16 omask = inw(io + IO_MASK);
 				outw(~STR_WREN, io + IO_MASK);
-				outw((card->muted = v.flags & VIDEO_AUDIO_MUTE)
+				outw((card->muted = v->flags & VIDEO_AUDIO_MUTE)
 				     ? STR_WREN : 0, io);
 				udelay4();
 				outw(omask, io + IO_MASK);
@@ -256,22 +244,22 @@
 			}
 		}
 		case VIDIOCGUNIT: {
-			struct video_unit v;
-			v.video=VIDEO_NO_UNIT;
-			v.vbi=VIDEO_NO_UNIT;
-			v.radio=dev->minor;
-			v.audio=0;
-			v.teletext=VIDEO_NO_UNIT;
-			if(copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			struct video_unit *v = arg;
+			v->video=VIDEO_NO_UNIT;
+			v->vbi=VIDEO_NO_UNIT;
+			v->radio=dev->minor;
+			v->audio=0;
+			v->teletext=VIDEO_NO_UNIT;
 			return 0;		
 		}
 		default: return -ENOIOCTLCMD;
 	}
 }
 
-static int radio_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int radio_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct radio_device *card=dev->priv;
 	int ret;
 	down(&card->lock);
@@ -279,20 +267,6 @@
 	up(&card->lock);
 	return ret;
 }
-
-static int radio_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void radio_close(struct video_device *dev)
-{
-	users--;
-}
-
 
 inline static __u16 radio_install(struct pci_dev *pcidev);
 
diff -Nru a/drivers/media/radio/radio-maxiradio.c b/drivers/media/radio/radio-maxiradio.c
--- a/drivers/media/radio/radio-maxiradio.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/radio/radio-maxiradio.c	Fri Mar 15 17:51:02 2002
@@ -72,19 +72,24 @@
 #define BITS2FREQ(x)	((x) * FREQ_STEP - FREQ_IF)
 
 
-static int radio_open(struct video_device *, int);
-static int radio_ioctl(struct video_device *, unsigned int, void *);
-static void radio_close(struct video_device *);
+static int radio_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg);
 
-static struct video_device maxiradio_radio=
+static struct file_operations maxiradio_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+static struct video_device maxiradio_radio =
 {
 	owner:		THIS_MODULE,
 	name:		"Maxi Radio FM2000 radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_SF16MI,
-	open:		radio_open,
-	close:		radio_close,
-	ioctl:		radio_ioctl,
+	fops:           &maxiradio_fops,
+	kernel_ioctl:	radio_ioctl,
 };
 
 static struct radio_device
@@ -169,149 +174,109 @@
 }
 
 
-inline static int radio_function(struct video_device *dev, 
+inline static int radio_function(struct video_device *dev,
 				 unsigned int cmd, void *arg)
 {
 	struct radio_device *card=dev->priv;
+
 	switch(cmd) {
 		case VIDIOCGCAP: {
-			struct video_capability v;
-			
-			strcpy(v.name, "Maxi Radio FM2000 radio");
-			v.type=VID_TYPE_TUNER;
-			v.channels=v.audios=1;
-			v.maxwidth=v.maxheight=v.minwidth=v.minheight=0;
+			struct video_capability *v = arg;
 			
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
-				
+			memset(v,0,sizeof(*v));
+			strcpy(v->name, "Maxi Radio FM2000 radio");
+			v->type=VID_TYPE_TUNER;
+			v->channels=v->audios=1;
 			return 0;
 		}
 		case VIDIOCGTUNER: {
-			struct video_tuner v;
+			struct video_tuner *v = arg;
 			
-			if(copy_from_user(&v, arg,sizeof(v))!=0)
-				return -EFAULT;
-				
-			if(v.tuner)
+			if(v->tuner)
 				return -EINVAL;
 				
 			card->stereo = 0xffff * get_stereo(card->io);
 			card->tuned = 0xffff * get_tune(card->io);
 			
-			v.flags = VIDEO_TUNER_LOW | card->stereo;
-			v.signal = card->tuned;
+			v->flags = VIDEO_TUNER_LOW | card->stereo;
+			v->signal = card->tuned;
 			
-			strcpy(v.name, "FM");
+			strcpy(v->name, "FM");
 			
-			v.rangelow = FREQ_LO;
-			v.rangehigh = FREQ_HI;
-			v.mode = VIDEO_MODE_AUTO;
+			v->rangelow = FREQ_LO;
+			v->rangehigh = FREQ_HI;
+			v->mode = VIDEO_MODE_AUTO;
 			
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
-				
-		  return 0;
+			return 0;
 		}
 		case VIDIOCSTUNER: {
-			struct video_tuner v;
-			
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-				
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
-				
 			return 0;
 		}
 		case VIDIOCGFREQ: {
-			unsigned long tmp=card->freq;
+			unsigned long *freq = arg;
 			
-			if(copy_to_user(arg, &tmp, sizeof(tmp)))
-				return -EFAULT;
-				
+			*freq = card->freq;
 			return 0;
 		}
-		
 		case VIDIOCSFREQ: {
-			unsigned long tmp;
+			unsigned long *freq = arg;
 			
-			if(copy_from_user(&tmp, arg, sizeof(tmp)))
-				return -EFAULT;
-				
-			if ( tmp<FREQ_LO || tmp>FREQ_HI )
+			if (*freq < FREQ_LO || *freq > FREQ_HI)
 				return -EINVAL;
-				
-			card->freq = tmp;
-			
+			card->freq = *freq;
 			set_freq(card->io, FREQ2BITS(card->freq));
 			sleep_125ms();
-
 			return 0;
 		}
 		case VIDIOCGAUDIO: {	
-			struct video_audio v;
-			strcpy(v.name, "Radio");
-			v.audio=v.volume=v.bass=v.treble=v.balance=v.step=0;
-			v.flags=VIDEO_AUDIO_MUTABLE | card->muted;
-			v.mode=VIDEO_SOUND_STEREO;
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0,sizeof(*v));
+			strcpy(v->name, "Radio");
+			v->flags=VIDEO_AUDIO_MUTABLE | card->muted;
+			v->mode=VIDEO_SOUND_STEREO;
 			return 0;		
 		}
 		
 		case VIDIOCSAUDIO: {
-			struct video_audio v;
+			struct video_audio *v = arg;
 			
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-				
-			if(v.audio)
+			if(v->audio)
 				return -EINVAL;
-				
-			
-			card->muted = v.flags & VIDEO_AUDIO_MUTE;
-				
+			card->muted = v->flags & VIDEO_AUDIO_MUTE;
 			if(card->muted)
 				turn_power(card->io, 0);
 			else
 				set_freq(card->io, FREQ2BITS(card->freq));
-				
 			return 0;
 		}
-		
 		case VIDIOCGUNIT: {
-			struct video_unit v;
-			v.video=VIDEO_NO_UNIT;
-			v.vbi=VIDEO_NO_UNIT;
-			v.radio=dev->minor;
-			v.audio=0;
-			v.teletext=VIDEO_NO_UNIT;
-			if(copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			struct video_unit *v = arg;
+			
+			v->video=VIDEO_NO_UNIT;
+			v->vbi=VIDEO_NO_UNIT;
+			v->radio=dev->minor;
+			v->audio=0;
+			v->teletext=VIDEO_NO_UNIT;
 			return 0;		
 		}
 		default: return -ENOIOCTLCMD;
 	}
 }
 
-static int radio_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int radio_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct radio_device *card=dev->priv;
 	int ret;
+	
 	down(&card->lock);
 	ret = radio_function(dev, cmd, arg);
 	up(&card->lock);
 	return ret;
-}
-
-static int radio_open(struct video_device *dev, int flags)
-{
-	return 0;
-}
-
-static void radio_close(struct video_device *dev)
-{
 }
 
 MODULE_AUTHOR("Dimitromanolakis Apostolos, apdim@grecian.net");
diff -Nru a/drivers/media/radio/radio-rtrack2.c b/drivers/media/radio/radio-rtrack2.c
--- a/drivers/media/radio/radio-rtrack2.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/radio/radio-rtrack2.c	Fri Mar 15 17:51:01 2002
@@ -24,7 +24,6 @@
 
 static int io = CONFIG_RADIO_RTRACK2_PORT; 
 static int radio_nr = -1;
-static int users = 0;
 static spinlock_t lock;
 
 struct rt_device
@@ -107,85 +106,75 @@
 	return 1;		/* signal present		*/
 }
 
-static int rt_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int rt_ioctl(struct inode *inode, struct file *file,
+		    unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct rt_device *rt=dev->priv;
 
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "RadioTrack II");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "RadioTrack II");
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			struct video_tuner *v = arg;
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow=88*16000;
-			v.rangehigh=108*16000;
-			v.flags=VIDEO_TUNER_LOW;
-			v.mode=VIDEO_MODE_AUTO;
-			v.signal=0xFFFF*rt_getsigstr(rt);
-			strcpy(v.name, "FM");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow=88*16000;
+			v->rangehigh=108*16000;
+			v->flags=VIDEO_TUNER_LOW;
+			v->mode=VIDEO_MODE_AUTO;
+			v->signal=0xFFFF*rt_getsigstr(rt);
+			strcpy(v->name, "FM");
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &rt->curfreq, sizeof(rt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = rt->curfreq;
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&rt->curfreq, arg,sizeof(rt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			rt->curfreq = *freq;
 			rt_setfreq(rt, rt->curfreq);
 			return 0;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags|=VIDEO_AUDIO_MUTABLE;
-			v.volume=1;
-			v.step=65535;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags|=VIDEO_AUDIO_MUTABLE;
+			v->volume=1;
+			v->step=65535;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
 
-			if(v.flags&VIDEO_AUDIO_MUTE) 
+			if(v->flags&VIDEO_AUDIO_MUTE) 
 				rt_mute(rt);
 			else
 			        rt_unmute(rt);
@@ -197,30 +186,24 @@
 	}
 }
 
-static int rt_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void rt_close(struct video_device *dev)
-{
-	users--;
-}
-
 static struct rt_device rtrack2_unit;
 
+static struct file_operations rtrack2_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device rtrack2_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"RadioTrack II radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_RTRACK2,
-	open:		rt_open,
-	close:		rt_close,
-	ioctl:		rt_ioctl,
+	fops:           &rtrack2_fops,
+	kernel_ioctl:   rt_ioctl,
 };
 
 static int __init rtrack2_init(void)
@@ -275,6 +258,6 @@
 
 /*
   Local variables:
-  compile-command: "gcc -c -DMODVERSIONS -D__KERNEL__ -DMODULE -O6 -Wall -Wstrict-prototypes -I /home/blp/tmp/linux-2.1.111-rtrack/include radio-rtrack2.c"
+  compile-command: "mmake"
   End:
 */
diff -Nru a/drivers/media/radio/radio-sf16fmi.c b/drivers/media/radio/radio-sf16fmi.c
--- a/drivers/media/radio/radio-sf16fmi.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/radio/radio-sf16fmi.c	Fri Mar 15 17:51:02 2002
@@ -36,7 +36,6 @@
 
 static int io = -1; 
 static int radio_nr = -1;
-static int users = 0;
 static struct pci_dev *dev = NULL;
 static struct semaphore lock;
 
@@ -133,121 +132,97 @@
 	return (res & 2) ? 0 : 0xFFFF;
 }
 
-static int fmi_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int fmi_ioctl(struct inode *inode, struct file *file,
+		     unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct fmi_device *fmi=dev->priv;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			strcpy(v.name, "SF16-FMx radio");
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			strcpy(v->name, "SF16-FMx radio");
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
+			struct video_tuner *v = arg;
 			int mult;
 
-			if(copy_from_user(&v, arg,sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */
+			if(v->tuner)	/* Only 1 tuner */
 				return -EINVAL;
-			strcpy(v.name, "FM");
+			strcpy(v->name, "FM");
 			mult = (fmi->flags & VIDEO_TUNER_LOW) ? 1 : 1000;
-			v.rangelow = RSF16_MINFREQ/mult;
-			v.rangehigh = RSF16_MAXFREQ/mult;
-			v.flags=fmi->flags;
-			v.mode=VIDEO_MODE_AUTO;
-			v.signal = fmi_getsigstr(fmi);
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow = RSF16_MINFREQ/mult;
+			v->rangehigh = RSF16_MAXFREQ/mult;
+			v->flags=fmi->flags;
+			v->mode=VIDEO_MODE_AUTO;
+			v->signal = fmi_getsigstr(fmi);
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
-			fmi->flags = v.flags & VIDEO_TUNER_LOW;
+			fmi->flags = v->flags & VIDEO_TUNER_LOW;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
 		{
-			unsigned long tmp = fmi->curfreq;
+			unsigned long *freq = arg;
+			*freq = fmi->curfreq;
 			if (!(fmi->flags & VIDEO_TUNER_LOW))
-				tmp /= 1000;
-			if(copy_to_user(arg, &tmp, sizeof(tmp)))
-				return -EFAULT;
+			    *freq /= 1000;
 			return 0;
 		}
 		case VIDIOCSFREQ:
 		{
-			unsigned long tmp;
-			if(copy_from_user(&tmp, arg, sizeof(tmp)))
-				return -EFAULT;
+			unsigned long *freq = arg;
 			if (!(fmi->flags & VIDEO_TUNER_LOW))
-				tmp *= 1000;
-			if ( tmp<RSF16_MINFREQ || tmp>RSF16_MAXFREQ )
-			  return -EINVAL;
+				*freq *= 1000;
+			if (*freq < RSF16_MINFREQ || *freq > RSF16_MAXFREQ )
+				return -EINVAL;
 			/*rounding in steps of 800 to match th freq
 			  that will be used */
-			fmi->curfreq = (tmp/800)*800; 
+			fmi->curfreq = (*freq/800)*800; 
 			fmi_setfreq(fmi);
 			return 0;
 		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			v.audio=0;
-			v.volume=0;
-			v.bass=0;
-			v.treble=0;
-			v.flags=( (!fmi->curvol)*VIDEO_AUDIO_MUTE | VIDEO_AUDIO_MUTABLE);
-			strcpy(v.name, "Radio");
-			v.mode=VIDEO_SOUND_STEREO;
-			v.balance=0;
-			v.step=0; /* No volume, just (un)mute */
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0,sizeof(*v));
+			v->flags=( (!fmi->curvol)*VIDEO_AUDIO_MUTE | VIDEO_AUDIO_MUTABLE);
+			strcpy(v->name, "Radio");
+			v->mode=VIDEO_SOUND_STEREO;
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.audio)
+			struct video_audio *v = arg;
+			if(v->audio)
 				return -EINVAL;
-			fmi->curvol= v.flags&VIDEO_AUDIO_MUTE ? 0 : 1;
+			fmi->curvol= v->flags&VIDEO_AUDIO_MUTE ? 0 : 1;
 			fmi->curvol ? 
-			  fmi_unmute(fmi->port) : fmi_mute(fmi->port);
+				fmi_unmute(fmi->port) : fmi_mute(fmi->port);
 			return 0;
 		}
 	        case VIDIOCGUNIT:
 		{
-               		struct video_unit v;
-			v.video=VIDEO_NO_UNIT;
-			v.vbi=VIDEO_NO_UNIT;
-			v.radio=dev->minor;
-			v.audio=0; /* How do we find out this??? */
-			v.teletext=VIDEO_NO_UNIT;
-			if(copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+               		struct video_unit *v = arg;
+			v->video=VIDEO_NO_UNIT;
+			v->vbi=VIDEO_NO_UNIT;
+			v->radio=dev->minor;
+			v->audio=0; /* How do we find out this??? */
+			v->teletext=VIDEO_NO_UNIT;
 			return 0;			
 		}
 		default:
@@ -255,30 +230,24 @@
 	}
 }
 
-static int fmi_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void fmi_close(struct video_device *dev)
-{
-	users--;
-}
-
 static struct fmi_device fmi_unit;
 
+static struct file_operations fmi_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device fmi_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"SF16FMx radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_SF16MI,
-	open:		fmi_open,
-	close:		fmi_close,
-	ioctl:		fmi_ioctl,
+	fops:           &fmi_fops,
+	kernel_ioctl:   fmi_ioctl,
 };
 
 /* ladis: this is my card. does any other types exist? */
diff -Nru a/drivers/media/radio/radio-terratec.c b/drivers/media/radio/radio-terratec.c
--- a/drivers/media/radio/radio-terratec.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/radio/radio-terratec.c	Fri Mar 15 17:51:03 2002
@@ -51,7 +51,6 @@
 
 static int io = CONFIG_RADIO_TERRATEC_PORT; 
 static int radio_nr = -1;
-static int users = 0;
 static spinlock_t lock;
 
 struct tt_device
@@ -186,89 +185,77 @@
 
 /* implement the video4linux api */
 
-static int tt_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int tt_ioctl(struct inode *inode, struct file *file,
+		    unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct tt_device *tt=dev->priv;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "ActiveRadio");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "ActiveRadio");
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			struct video_tuner *v = arg;
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow=(87*16000);
-			v.rangehigh=(108*16000);
-			v.flags=VIDEO_TUNER_LOW;
-			v.mode=VIDEO_MODE_AUTO;
-			strcpy(v.name, "FM");
-			v.signal=0xFFFF*tt_getsigstr(tt);
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow=(87*16000);
+			v->rangehigh=(108*16000);
+			v->flags=VIDEO_TUNER_LOW;
+			v->mode=VIDEO_MODE_AUTO;
+			strcpy(v->name, "FM");
+			v->signal=0xFFFF*tt_getsigstr(tt);
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &tt->curfreq, sizeof(tt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = tt->curfreq;
 			return 0;
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&tt->curfreq, arg,sizeof(tt->curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			tt->curfreq = *freq;
 			tt_setfreq(tt, tt->curfreq);
 			return 0;
+		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags|=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
-			v.volume=tt->curvol * 6554;
-			v.step=6554;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags|=VIDEO_AUDIO_MUTABLE|VIDEO_AUDIO_VOLUME;
+			v->volume=tt->curvol * 6554;
+			v->step=6554;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
-
-			if(v.flags&VIDEO_AUDIO_MUTE) 
+			if(v->flags&VIDEO_AUDIO_MUTE) 
 				tt_mute(tt);
 			else
-				tt_setvol(tt,v.volume/6554);	
-
+				tt_setvol(tt,v->volume/6554);
 			return 0;
 		}
 		default:
@@ -276,30 +263,24 @@
 	}
 }
 
-static int tt_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void tt_close(struct video_device *dev)
-{
-	users--;
-}
-
 static struct tt_device terratec_unit;
 
+static struct file_operations terratec_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device terratec_radio=
 {
 	owner:		THIS_MODULE,
 	name:		"TerraTec ActiveRadio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_TERRATEC,
-	open:		tt_open,
-	close:		tt_close,
-	ioctl:		tt_ioctl,
+	fops:           &terratec_fops,
+	kernel_ioctl:	tt_ioctl,
 };
 
 static int __init terratec_init(void)
diff -Nru a/drivers/media/radio/radio-trust.c b/drivers/media/radio/radio-trust.c
--- a/drivers/media/radio/radio-trust.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/radio/radio-trust.c	Fri Mar 15 17:51:03 2002
@@ -33,7 +33,6 @@
 static int io = CONFIG_RADIO_TRUST_PORT; 
 static int radio_nr = -1;
 static int ioval = 0xf;
-static int users = 0;
 static __u16 curvol;
 static __u16 curbass;
 static __u16 curtreble;
@@ -155,114 +154,89 @@
 	write_i2c(5, TSA6060T_ADDR, (f << 1) | 1, f >> 7, 0x60 | ((f >> 15) & 1), 0);
 }
 
-static int tr_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int tr_ioctl(struct inode *inode, struct file *file,
+		    unsigned int cmd, void *arg)
 {
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability v;
+			struct video_capability *v = arg;
 
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-
-			strcpy(v.name, "Trust FM Radio");
-
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "Trust FM Radio");
 
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
+			struct video_tuner *v = arg;
 
-			if(v.tuner)	/* Only 1 tuner */ 
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
 
-			v.rangelow = 87500 * 16;
-			v.rangehigh = 108000 * 16;
-			v.flags = VIDEO_TUNER_LOW;
-			v.mode = VIDEO_MODE_AUTO;
+			v->rangelow = 87500 * 16;
+			v->rangehigh = 108000 * 16;
+			v->flags = VIDEO_TUNER_LOW;
+			v->mode = VIDEO_MODE_AUTO;
 
-			v.signal = tr_getsigstr();
+			v->signal = tr_getsigstr();
 			if(tr_getstereo())
-				v.flags |= VIDEO_TUNER_STEREO_ON;
+				v->flags |= VIDEO_TUNER_STEREO_ON;
 
-			strcpy(v.name, "FM");
-
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			strcpy(v->name, "FM");
 
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner != 0)
+			struct video_tuner *v = arg;
+			if(v->tuner != 0)
 				return -EINVAL;
-
 			return 0;
 		}
 		case VIDIOCGFREQ:
-			if(copy_to_user(arg, &curfreq, sizeof(curfreq)))
-				return -EFAULT;
+		{
+			unsigned long *freq = arg;
+			*freq = curfreq;
 			return 0;
-
+		}
 		case VIDIOCSFREQ:
 		{
-			unsigned long f;
-
-			if(copy_from_user(&f, arg, sizeof(curfreq)))
-				return -EFAULT;
-			tr_setfreq(f);
+			unsigned long *freq = arg;
+			tr_setfreq(*freq);
 			return 0;
 		}
 		case VIDIOCGAUDIO:
 		{	
-			struct video_audio v;
+			struct video_audio *v = arg;
 
-			memset(&v,0, sizeof(v));
-			v.flags = VIDEO_AUDIO_MUTABLE | VIDEO_AUDIO_VOLUME |
+			memset(v,0, sizeof(*v));
+			v->flags = VIDEO_AUDIO_MUTABLE | VIDEO_AUDIO_VOLUME |
 			          VIDEO_AUDIO_BASS | VIDEO_AUDIO_TREBLE;
-			v.mode = curstereo? VIDEO_SOUND_STEREO : VIDEO_SOUND_MONO;
-			v.volume = curvol * 2048;
-			v.step = 2048;
-			v.bass = curbass * 4370;
-			v.treble = curtreble * 4370;
+			v->mode = curstereo? VIDEO_SOUND_STEREO : VIDEO_SOUND_MONO;
+			v->volume = curvol * 2048;
+			v->step = 2048;
+			v->bass = curbass * 4370;
+			v->treble = curtreble * 4370;
 			
-			strcpy(v.name, "Trust FM Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			strcpy(v->name, "Trust FM Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
+			struct video_audio *v = arg;
 
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			if(v->audio) 
 				return -EINVAL;
-
-			tr_setvol(v.volume);					
-			tr_setbass(v.bass);
-			tr_settreble(v.treble);
-			tr_setstereo(v.mode & VIDEO_SOUND_STEREO);
-			tr_setmute(v.flags & VIDEO_AUDIO_MUTE);
+			tr_setvol(v->volume);					
+			tr_setbass(v->bass);
+			tr_settreble(v->treble);
+			tr_setstereo(v->mode & VIDEO_SOUND_STEREO);
+			tr_setmute(v->flags & VIDEO_AUDIO_MUTE);
 			return 0;
 		}
 		default:
@@ -270,18 +244,13 @@
 	}
 }
 
-static int tr_open(struct video_device *dev, int flags)
-{
-	if(users)
-		return -EBUSY;
-	users++;
-	return 0;
-}
-
-static void tr_close(struct video_device *dev)
-{
-	users--;
-}
+static struct file_operations trust_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
 
 static struct video_device trust_radio=
 {
@@ -289,9 +258,8 @@
 	name:		"Trust FM Radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_TRUST,
-	open:		tr_open,
-	close:		tr_close,
-	ioctl:		tr_ioctl,
+	fops:           &trust_fops,
+	kernel_ioctl:	tr_ioctl,
 };
 
 static int __init trust_init(void)
diff -Nru a/drivers/media/radio/radio-typhoon.c b/drivers/media/radio/radio-typhoon.c
--- a/drivers/media/radio/radio-typhoon.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/radio/radio-typhoon.c	Fri Mar 15 17:51:02 2002
@@ -59,6 +59,7 @@
 	int muted;
 	unsigned long curfreq;
 	unsigned long mutefreq;
+	struct semaphore lock;
 };
 
 static void typhoon_setvol_generic(struct typhoon_device *dev, int vol);
@@ -68,19 +69,20 @@
 static void typhoon_mute(struct typhoon_device *dev);
 static void typhoon_unmute(struct typhoon_device *dev);
 static int typhoon_setvol(struct typhoon_device *dev, int vol);
-static int typhoon_ioctl(struct video_device *dev, unsigned int cmd, void *arg);
-static int typhoon_open(struct video_device *dev, int flags);
-static void typhoon_close(struct video_device *dev);
+static int typhoon_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, void *arg);
 #ifdef CONFIG_RADIO_TYPHOON_PROC_FS
 static int typhoon_get_info(char *buf, char **start, off_t offset, int len);
 #endif
 
 static void typhoon_setvol_generic(struct typhoon_device *dev, int vol)
 {
+	down(&dev->lock);
 	vol >>= 14;				/* Map 16 bit to 2 bit */
 	vol &= 3;
 	outb_p(vol / 2, dev->iobase);		/* Set the volume, high bit. */
 	outb_p(vol % 2, dev->iobase + 2);	/* Set the volume, low bit. */
+	up(&dev->lock);
 }
 
 static int typhoon_setfreq_generic(struct typhoon_device *dev,
@@ -100,6 +102,7 @@
 	 *
 	 */
 
+	down(&dev->lock);
 	x = frequency / 160;
 	outval = (x * x + 2500) / 5000;
 	outval = (outval * x + 5000) / 10000;
@@ -109,6 +112,7 @@
 	outb_p((outval >> 8) & 0x01, dev->iobase + 4);
 	outb_p(outval >> 9, dev->iobase + 6);
 	outb_p(outval & 0xff, dev->iobase + 8);
+	up(&dev->lock);
 
 	return 0;
 }
@@ -159,94 +163,79 @@
 }
 
 
-static int typhoon_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int typhoon_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct typhoon_device *typhoon = dev->priv;
 
 	switch (cmd) {
 	case VIDIOCGCAP:
 		{
-			struct video_capability v;
-			v.type = VID_TYPE_TUNER;
-			v.channels = 1;
-			v.audios = 1;
-			/* No we don't do pictures */
-			v.maxwidth = 0;
-			v.maxheight = 0;
-			v.minwidth = 0;
-			v.minheight = 0;
-			strcpy(v.name, "Typhoon Radio");
-			if (copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type = VID_TYPE_TUNER;
+			v->channels = 1;
+			v->audios = 1;
+			strcpy(v->name, "Typhoon Radio");
 			return 0;
 		}
 	case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if (copy_from_user(&v, arg, sizeof(v)) != 0)
-				return -EFAULT;
-			if (v.tuner)	/* Only 1 tuner */
+			struct video_tuner *v = arg;
+			if (v->tuner)	/* Only 1 tuner */
 				return -EINVAL;
-			v.rangelow = 875 * 1600;
-			v.rangehigh = 1080 * 1600;
-			v.flags = VIDEO_TUNER_LOW;
-			v.mode = VIDEO_MODE_AUTO;
-			v.signal = 0xFFFF;	/* We can't get the signal strength */
-			strcpy(v.name, "FM");
-			if (copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			v->rangelow = 875 * 1600;
+			v->rangehigh = 1080 * 1600;
+			v->flags = VIDEO_TUNER_LOW;
+			v->mode = VIDEO_MODE_AUTO;
+			v->signal = 0xFFFF;	/* We can't get the signal strength */
+			strcpy(v->name, "FM");
 			return 0;
 		}
 	case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if (copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if (v.tuner != 0)
+			struct video_tuner *v = arg;
+			if (v->tuner != 0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
 	case VIDIOCGFREQ:
-		if (copy_to_user(arg, &typhoon->curfreq,
-				 sizeof(typhoon->curfreq)))
-			return -EFAULT;
+	{
+		unsigned long *freq = arg;
+		*freq = typhoon->curfreq;
 		return 0;
+	}
 	case VIDIOCSFREQ:
-		if (copy_from_user(&typhoon->curfreq, arg,
-				   sizeof(typhoon->curfreq)))
-			return -EFAULT;
+	{
+		unsigned long *freq = arg;
+		typhoon->curfreq = *freq;
 		typhoon_setfreq(typhoon, typhoon->curfreq);
 		return 0;
+	}
 	case VIDIOCGAUDIO:
 		{
-			struct video_audio v;
-			memset(&v, 0, sizeof(v));
-			v.flags |= VIDEO_AUDIO_MUTABLE | VIDEO_AUDIO_VOLUME;
-			v.mode |= VIDEO_SOUND_MONO;
-			v.volume = typhoon->curvol;
-			v.step = 1 << 14;
-			strcpy(v.name, "Typhoon Radio");
-			if (copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v, 0, sizeof(*v));
+			v->flags |= VIDEO_AUDIO_MUTABLE | VIDEO_AUDIO_VOLUME;
+			v->mode |= VIDEO_SOUND_MONO;
+			v->volume = typhoon->curvol;
+			v->step = 1 << 14;
+			strcpy(v->name, "Typhoon Radio");
 			return 0;
 		}
 	case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			if (copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if (v.audio)
+			struct video_audio *v = arg;
+			if (v->audio)
 				return -EINVAL;
-
-			if (v.flags & VIDEO_AUDIO_MUTE)
+			if (v->flags & VIDEO_AUDIO_MUTE)
 				typhoon_mute(typhoon);
 			else
 				typhoon_unmute(typhoon);
-
-			if (v.flags & VIDEO_AUDIO_VOLUME)
-				typhoon_setvol(typhoon, v.volume);
-
+			if (v->flags & VIDEO_AUDIO_VOLUME)
+				typhoon_setvol(typhoon, v->volume);
 			return 0;
 		}
 	default:
@@ -254,21 +243,6 @@
 	}
 }
 
-static int typhoon_open(struct video_device *dev, int flags)
-{
-	struct typhoon_device *typhoon = dev->priv;
-	if (typhoon->users)
-		return -EBUSY;
-	typhoon->users++;
-	return 0;
-}
-
-static void typhoon_close(struct video_device *dev)
-{
-	struct typhoon_device *typhoon = dev->priv;
-	typhoon->users--;
-}
-
 static struct typhoon_device typhoon_unit =
 {
 	iobase:		CONFIG_RADIO_TYPHOON_PORT,
@@ -276,15 +250,22 @@
 	mutefreq:	CONFIG_RADIO_TYPHOON_MUTEFREQ,
 };
 
+static struct file_operations typhoon_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device typhoon_radio =
 {
 	owner:		THIS_MODULE,
 	name:		"Typhoon Radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_TYPHOON,
-	open:		typhoon_open,
-	close:		typhoon_close,
-	ioctl:		typhoon_ioctl,
+	fops:           &typhoon_fops,
+	kernel_ioctl:	typhoon_ioctl,
 };
 
 #ifdef CONFIG_RADIO_TYPHOON_PROC_FS
@@ -342,6 +323,7 @@
 		return -EINVAL;
 	}
 	typhoon_unit.iobase = io;
+	init_MUTEX(&typhoon_unit.lock);
 
 	if (mutefreq < 87000 || mutefreq > 108500) {
 		printk(KERN_ERR "radio-typhoon: You must set a frequency (in kHz) used when muting the card,\n");
diff -Nru a/drivers/media/video/Makefile b/drivers/media/video/Makefile
--- a/drivers/media/video/Makefile	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/Makefile	Fri Mar 15 17:51:02 2002
@@ -25,17 +25,18 @@
 # All of the (potential) objects that export symbols.
 # This list comes from 'grep -l EXPORT_SYMBOL *.[hc]'.
 
-export-objs     :=	i2c-old.o videodev.o bttv-if.o cpia.o
+export-objs     :=	i2c-old.o videodev.o bttv-if.o cpia.o video-buf.o
 
 list-multi	:=	bttv.o zoran.o
-bttv-objs	:=	bttv-driver.o bttv-cards.o bttv-if.o
+bttv-objs	:=	bttv-driver.o bttv-cards.o bttv-if.o \
+			bttv-risc.o bttv-vbi.o
 zoran-objs      :=	zr36120.o zr36120_i2c.o zr36120_mem.o
 
 obj-$(CONFIG_VIDEO_DEV) += videodev.o
 
 obj-$(CONFIG_BUS_I2C) += i2c-old.o
 obj-$(CONFIG_VIDEO_BT848) += bttv.o msp3400.o tvaudio.o \
-	tda7432.o tda9875.o tuner.o
+	tda7432.o tda9875.o tuner.o video-buf.o
 obj-$(CONFIG_SOUND_TVMIXER) += tvmixer.o
 
 obj-$(CONFIG_VIDEO_ZR36120) += zoran.o
diff -Nru a/drivers/media/video/bttv-cards.c b/drivers/media/video/bttv-cards.c
--- a/drivers/media/video/bttv-cards.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/video/bttv-cards.c	Fri Mar 15 17:51:03 2002
@@ -39,9 +39,9 @@
 #include "tuner.h"
 
 /* fwd decl */
+static void boot_msp34xx(struct bttv *btv, int pin);
 static void hauppauge_eeprom(struct bttv *btv);
 static void avermedia_eeprom(struct bttv *btv);
-
 static void init_PXC200(struct bttv *btv);
 #if 0
 static void init_tea5757(struct bttv *btv);
@@ -55,6 +55,9 @@
 static void gvbctv3pci_audio(struct bttv *btv, struct video_audio *v, int set);
 static void winfast2000_audio(struct bttv *btv, struct video_audio *v, int set);
 static void pvbt878p9b_audio(struct bttv *btv, struct video_audio *v, int set);
+static void fv2000s_audio(struct bttv *btv, struct video_audio *v, int set);
+static void windvr_audio(struct bttv *btv, struct video_audio *v, int set);
+static void rv605_muxsel(struct bttv *btv, unsigned int input);
 
 /* config variables */
 static int triton1=0;
@@ -77,7 +80,8 @@
 MODULE_PARM_DESC(triton1,"set ETBF pci config bit "
 		 "[enable bug compatibility for triton1 + others]");
 MODULE_PARM(vsfx,"i");
-MODULE_PARM_DESC(vsfx,"set VSFX pci config bit [yet another chipset flaw workaround]");
+MODULE_PARM_DESC(vsfx,"set VSFX pci config bit "
+		 "[yet another chipset flaw workaround]");
 MODULE_PARM(no_overlay,"i");
 MODULE_PARM(card,"1-4i");
 MODULE_PARM_DESC(card,"specify TV/grabber card model, see CARDLIST file for a list");
@@ -151,7 +155,7 @@
 	{ 0x00041461, BTTV_AVERMEDIA98,   "AVerMedia TVCapture 98" },
 
 	{ 0x300014ff, BTTV_MAGICTVIEW061, "TView 99 (CPH061)" },
-	{ 0x300214ff, BTTV_PHOEBE_TVMAS,  "Phoebe TV Master" },
+	{ 0x300214ff, BTTV_PHOEBE_TVMAS,  "Phoebe TV Master (CPH060)" },
 
 	{ 0x1117153b, BTTV_TERRATVALUE,   "Terratec TValue" },
 	{ 0x1118153b, BTTV_TERRATVALUE,   "Terratec TValue" },
@@ -161,6 +165,7 @@
 	{ 0x1127153b, BTTV_TERRATV,       "Terratec TV+"    },
 	{ 0x1134153b, BTTV_TERRATVALUE,   "Terratec TValue" },
 	{ 0x1135153b, BTTV_TERRATVALUER,  "Terratec TValue Radio" },
+	{ 0x5018153b, BTTV_TERRATVALUE,   "Terratec TValue" },
 
 	{ 0x400a15b0, BTTV_ZOLTRIX_GENIE, "Zoltrix Genie TV" },
 	{ 0x400d15b0, BTTV_ZOLTRIX_GENIE, "Zoltrix Genie TV / Radio" },
@@ -168,12 +173,14 @@
 	{ 0x401615b0, BTTV_ZOLTRIX_GENIE, "Zoltrix Genie TV / Radio" },
 
     	{ 0x010115cb, BTTV_GMV1,          "AG GMV1" },
-	{ 0x010114c7, BTTV_MODTEC_205,    "Modular Technology PCTV" },
+	{ 0x010114c7, BTTV_MODTEC_205,    "Modular Technology MM205 PCTV" },
 	{ 0x18501851, BTTV_CHRONOS_VS2,   "Flyvideo 98 (LR50)/ Chronos Video Shuttle II" },
 	{ 0x18511851, BTTV_FLYVIDEO98EZ,  "Flyvideo 98EZ (LR51)/ CyberMail AV" },
 	{ 0x18521852, BTTV_TYPHOON_TVIEW, "Flyvideo 98FM (LR50)/ Typhoon TView TV/FM Tuner" },
 	{ 0x10b42636, BTTV_HAUPPAUGE878,  "STB ???" },
 	{ 0x217d6606, BTTV_WINFAST2000,   "Leadtek WinFast TV 2000" },
+	{ 0x03116000, BTTV_SENSORAY311,   "Sensoray 311" },
+	{ 0x00790e11, BTTV_WINDVR,        "Canopus WinDVR PCI" },
 
 	{ 0, -1, NULL }
 };
@@ -276,8 +283,8 @@
 },{
 
 /* ---- card 0x08 ---------------------------------- */
-	name:		"Fly Video II (Bt848)",
-	video_inputs:	3,
+	name:		"FlyVideo II (Bt848) LR26",
+	video_inputs:	4,
 	audio_inputs:	1,
 	tuner:		0,
 	svhs:		2,
@@ -285,9 +292,10 @@
 	muxsel:		{ 2, 3, 1, 1},
 	audiomux:	{ 0, 0xc00, 0x800, 0x400, 0xc00, 0},
 	needs_tvaudio:	1,
+	pll:		PLL_28,
 	tuner_type:	-1,
 },{
-	name:		"TurboTV",
+	name:		"IXMicro TurboTV",
 	video_inputs:	3,
 	audio_inputs:	1,
 	tuner:		0,
@@ -346,14 +354,14 @@
 	pll:		PLL_28,
 	tuner_type:	-1,
 },{
-	name:		"Aimslab VHX",
+	name:		"Aimslab Video Highway Xtreme (VHX)",
 	video_inputs:	3,
 	audio_inputs:	1,
 	tuner:		0,
 	svhs:		2,
 	gpiomask:	7,
 	muxsel:		{ 2, 3, 1, 1},
-	audiomux:	{ 0, 1, 2, 3, 4},
+	audiomux:	{ 0, 2, 1, 3, 4}, /* old: { 0, 1, 2, 3, 4} */
 	needs_tvaudio:	1,
 	tuner_type:	-1,
 },{
@@ -393,6 +401,7 @@
 	needs_tvaudio:	1,
 	tuner_type:	-1,
 	audio_hook:	winview_audio,
+	has_radio:	1,
 },{
 	name:		"AVEC Intercapture",
 	video_inputs:	3,
@@ -438,7 +447,7 @@
 	pll:		PLL_28,
 	tuner_type:	TUNER_PHILIPS_PAL_I,
 },{
-	name:		"Phoebe Tv Master + FM",
+	name:		"Phoebe Tv Master + FM (CPH050)",
 	video_inputs:	3,
 	audio_inputs:	1,
 	tuner:		0,
@@ -752,6 +761,7 @@
 	gpiomask:	0x1f0000,
 	muxsel:		{ 2, 3, 1, 1},
 	audiomux:	{ 0xe2ffff, 0xebffff, 0, 0, 0xe0ffff, 0xe2ffff },
+	needs_tvaudio:	1,
 	no_msp34xx:	1,
 	pll:		PLL_35,
 	tuner_type:	1,
@@ -788,7 +798,7 @@
 	video_inputs:	4,
 	audio_inputs:	1,
 	tuner:		0,
-	svhs:		2,
+	svhs:		3,
 	gpiomask:	0xAA0000,
 	muxsel:		{ 2,3,1,1 },
 	audiomux:	{ 0x20000, 0, 0x80000, 0x80000, 0xa8000, 0x46000  },
@@ -860,7 +870,7 @@
 },{
 	/* Miguel Angel Alvarez <maacruz@navegalia.com>
 	   old Easy TV BT848 version (model CPH031) */
-	name:           "BESTBUY Easy TV",
+	name:           "BESTBUY Easy TV (CPH031)",
 	video_inputs:	4,
 	audio_inputs:   1,
 	tuner:          0,
@@ -890,7 +900,7 @@
 	/* This is the ultimate cheapo capture card 
 	 * just a BT848A on a small PCB!
 	 * Steve Hosgood <steve@equiinet.com> */
-	name:           "GrandTec 'Grand Video Capture'",
+	name:           "GrandTec 'Grand Video Capture' (Bt848)",
 	video_inputs:   2,
 	audio_inputs:   0,
 	tuner:          -1,
@@ -904,7 +914,7 @@
 	tuner_type:     -1,
 },{
         /* Daniel Herrington <daniel.herrington@home.com> */
-        name:           "Phoebe TV Master Only (No FM)",
+        name:           "Phoebe TV Master Only (No FM) CPH060",
         video_inputs:   3,
         audio_inputs:   1,
         tuner:          0,
@@ -917,7 +927,7 @@
         tuner_type:     TUNER_TEMIC_4036FY5_NTSC,
 },{
 	/* Matti Mottus <mottus@physic.ut.ee> */
-	name:		"TV Capturer",
+	name:		"TV Capturer (CPH03X)",
 	video_inputs:	4,
 	audio_inputs:	1,
 	tuner:		0,
@@ -931,7 +941,7 @@
 
 /* ---- card 0x3c ---------------------------------- */
 	/* Philip Blundell <philb@gnu.org> */
-	name:           "MM100PCTV",
+	name:           "Modular Technology MM100PCTV",
 	video_inputs:   2,
 	audio_inputs:   2,
 	gpiomask:       11,
@@ -977,7 +987,7 @@
 	tuner:		0,
 	svhs:		2,
 	gpiomask:	0xf03f,
-	muxsel:		{ 2, 3, 0, 1},
+	muxsel:		{ 2, 3, 1, 0 },
 	audiomux:	{ 0xbffe, 0, 0xbfff, 0, 0xbffe},
 	pll:		PLL_28,
 	tuner_type:	TUNER_TEMIC_4006FN5_MULTI_PAL,
@@ -1005,7 +1015,13 @@
 	svhs:           2,
 	gpiomask:	0x18e0,
 	muxsel:		{ 2, 3, 0, 1},
-	audiomux:	{ 0,0x18e0,0x1000,0x1000,0x1080, 0x1080 },
+			/* Radio changed from 1e80 to 0x800 to make
+			   Flyvideo2000S in .hu happy (gm)*/
+			/* -dk-???: set mute=0x1800 for tda9874h daughterboard */
+	audiomux:	{ 0x0000,0x0800,0x1000,0x1000,0x1800, 0x1080 },
+	audio_hook:	fv2000s_audio,
+	no_msp34xx:	1,
+	no_tda9875:	1,
 	needs_tvaudio:  1,
 	pll:            PLL_28,
 	tuner_type:     5,
@@ -1047,11 +1063,12 @@
         tuner:          0,
         svhs:           -1,
         gpiomask:       0x4f8a00,
-	                // 0x100000: 1=MSP enabled (0=disable again)
-			// 0x010000: somehow influences tuner picture quality (?)
-        audiomux:       {0x947fff, 0x987fff,0x947fff,0x947fff},
-                        //tvtuner, radio,   external,internal,mute,stereo
-        muxsel:         { 2, 3 ,0 ,1}, /* tuner, Composit, SVid, Composit-on-Svid-adapter*/
+	// 0x100000: 1=MSP enabled (0=disable again)
+	// 0x010000: Connected to "S0" on tda9880 (0=Pal/BG, 1=NTSC)
+        audiomux:       {0x947fff, 0x987fff,0x947fff,0x947fff, 0x947fff},
+	// tvtuner, radio,   external,internal, mute,  stereo
+	/* tuner, Composit, SVid, Composit-on-Svid-adapter*/
+        muxsel:         { 2, 3 ,0 ,1},
         tuner_type:     TUNER_MT2032,
 	pll:		PLL_28,
 	has_radio:	1,
@@ -1106,8 +1123,74 @@
 	tuner_type:	-1,
 	audio_hook:	pvbt878p9b_audio,
 	has_radio:	1,
-}
-};
+},{
+	/* Clay Kunz <ckunz@mail.arc.nasa.gov> */
+	/* you must jumper JP5 for the card to work */
+	name:           "Sensoray 311",
+	video_inputs:   5,
+	audio_inputs:   0,
+	tuner:          -1,
+	svhs:           4,
+	gpiomask:       0,
+	muxsel:         { 2, 3, 1, 0, 0},
+	audiomux:       { 0 },
+	needs_tvaudio:  0,
+	tuner_type:     -1,
+},{
+	/* Miguel Freitas <miguel@cetuc.puc-rio.br> */
+	name:           "RemoteVision MX (RV605)",
+	video_inputs:   16,
+	audio_inputs:   0,
+	tuner:          0,
+	svhs:           0,
+	gpiomask:       0x00,
+	gpiomask2:      0x07ff,
+	muxsel:         { 0x33, 0x13, 0x23, 0x43, 0xf3, 0x73, 0xe3, 0x03,
+			  0xd3, 0xb3, 0xc3, 0x63, 0x93, 0x53, 0x83, 0xa3 },
+	no_msp34xx:     1,
+	no_tda9875:     1,
+	tuner_type:     -1,
+	muxsel_hook:    rv605_muxsel,
+},{
+        name:           "Powercolor MTV878/ MTV878R/ MTV878F",
+        video_inputs:   3,
+        audio_inputs:   2, 
+        svhs:           2,
+        gpiomask:       0x1C800F,  // Bit0-2: Audio select, 8-12:remote control 14:remote valid 15:remote reset
+        muxsel:         { 2, 1, 1, },
+        audiomux:       { 0, 1, 2, 2, 4 },
+        needs_tvaudio:  0,
+        tuner_type:     TUNER_PHILIPS_PAL,
+	pll:		PLL_28,
+	has_radio:	1,
+},{
+
+/* ---- card 0x4c ---------------------------------- */
+        /* Masaki Suzuki <masaki@btree.org> */
+        name:           "Canopus WinDVR PCI (COMPAQ Presario 3524JP, 5112JP)",
+        video_inputs:   3,
+        audio_inputs:   1,
+        tuner:          0,
+        svhs:           2,
+        gpiomask:       0x140007,
+        muxsel:         { 2, 3, 1, 1 },
+        audiomux:       { 0, 1, 2, 3, 4, 0 },
+        tuner_type:     TUNER_PHILIPS_NTSC,
+        audio_hook:     windvr_audio,
+},{
+        name:           "GrandTec Multi Capture Card (Bt878)",
+        video_inputs:   4,
+        audio_inputs:   0,
+        tuner:          -1,
+        svhs:           -1,
+        gpiomask:       0,
+        muxsel:         { 2, 3, 1, 0 },
+        audiomux:       { 0 },
+        needs_tvaudio:  0,
+        no_msp34xx:     1,
+        pll:            PLL_28,
+        tuner_type:     -1,
+}};
 
 const int bttv_num_tvcards = (sizeof(bttv_tvcards)/sizeof(struct tvcard));
 
@@ -1195,12 +1278,58 @@
  * (most) board specific initialisations goes here
  */
 
+static void flyvideo_gpio(struct bttv *btv)
+{
+	int gpio,outbits;
+	int tuner=-1,ttype;
+	
+	outbits = btread(BT848_GPIO_OUT_EN);
+	btwrite(0x00, BT848_GPIO_OUT_EN);
+	udelay(8);  // without this we would see the 0x1800 mask
+	gpio=btread(BT848_GPIO_DATA);
+	btwrite(outbits, BT848_GPIO_OUT_EN);
+	// all cards provide GPIO info, some have an additional eeprom
+	
+	// lowest 3 bytes are remote control codes (no handshake needed)
+	ttype=(gpio&0x0f0000)>>16;
+	switch(ttype) {
+	case 0: tuner=4; // None
+		break;
+	case 4: tuner=5; // Philips PAL
+		break;
+	case 6: tuner=37; // LG PAL (newer TAPC series)
+		break;
+	case 0xC: tuner=3; // Philips SECAM(+PAL)
+		break;
+	default:
+		printk(KERN_INFO "bttv%d: flyvideo_gpio: unknown tuner type.\n", btv->nr);
+	}
+	
+	printk(KERN_INFO "bttv%d: Flyvideo Radio=%s RemoteControl=%s Tuner=%d gpio=0x%06x\n", 
+	       btv->nr,
+	       gpio&0x400000? "yes":"no",
+	       gpio&0x800000? "yes":"no", tuner, gpio);
+	
+	btv->tuner_type = tuner;
+	btv->has_radio = gpio&0x400000? 1:0; 
+}
+
 int miro_tunermap[] = { 0,6,2,3,   4,5,6,0,  3,0,4,5,  5,2,16,1,
 			14,2,17,1, 4,1,4,3,  1,2,16,1, 4,4,4,4 };
 int miro_fmtuner[]  = { 0,0,0,0,   0,0,0,0,  0,0,0,0,  0,0,0,1,
 			1,1,1,1,   1,1,1,0,  0,0,0,0,  0,0,0,0 };
 
-void __devinit bttv_init_card(struct bttv *btv)
+/* initialization part one -- before registering i2c bus */
+void __devinit bttv_init_card1(struct bttv *btv)
+{
+        if (btv->type == BTTV_HAUPPAUGE || btv->type == BTTV_HAUPPAUGE878)
+                boot_msp34xx(btv,5);
+	if (btv->type == BTTV_VOODOOTV_FM)
+		boot_msp34xx(btv,20);
+}
+
+/* initialization part one -- after registering i2c bus */
+void __devinit bttv_init_card2(struct bttv *btv)
 {
 	/* miro/pinnacle */
         if (btv->type == BTTV_MIRO      ||
@@ -1246,6 +1375,15 @@
 #endif
 	}
 
+	if (btv->type == BTTV_FLYVIDEO_98    ||
+	    btv->type == BTTV_FLYVIDEO       ||
+	    btv->type == BTTV_TYPHOON_TVIEW  ||
+	    btv->type == BTTV_CHRONOS_VS2    ||
+	    btv->type == BTTV_FLYVIDEO_98FM  ||
+	    btv->type == BTTV_FLYVIDEO2000   ||
+	    btv->type == BTTV_FLYVIDEO98EZ)
+		flyvideo_gpio(btv);
+
         if (btv->type == BTTV_HAUPPAUGE || btv->type == BTTV_HAUPPAUGE878) {
 		/* pick up some config infos from the eeprom */
 		bttv_readee(btv,eeprom_data,0xa0);
@@ -1449,22 +1587,24 @@
 		       btv->tuner_type, radio ? "yes" : "no");
 }
 
-// AVermedia specific stuff...
-// from  bktr_card.c
+
+/* ----------------------------------------------------------------------- */
+/* AVermedia specific stuff, from  bktr_card.c                             */
+
 int tuner_0_table[] = {
         TUNER_PHILIPS_NTSC,  TUNER_PHILIPS_PAL,
         TUNER_PHILIPS_PAL,   TUNER_PHILIPS_PAL,
         TUNER_PHILIPS_PAL,   TUNER_PHILIPS_PAL,
         TUNER_PHILIPS_SECAM, TUNER_PHILIPS_SECAM,
         TUNER_PHILIPS_SECAM, TUNER_PHILIPS_PAL};
-/*
+#if 0
 int tuner_0_fm_table[] = {
         PHILIPS_FR1236_NTSC,  PHILIPS_FR1216_PAL,
         PHILIPS_FR1216_PAL,   PHILIPS_FR1216_PAL,
         PHILIPS_FR1216_PAL,   PHILIPS_FR1216_PAL,
         PHILIPS_FR1236_SECAM, PHILIPS_FR1236_SECAM,
         PHILIPS_FR1236_SECAM, PHILIPS_FR1216_PAL};
-*/
+#endif
 
 int tuner_1_table[] = {
         TUNER_TEMIC_NTSC,  TUNER_TEMIC_PAL,
@@ -1475,11 +1615,12 @@
 
 static void __devinit avermedia_eeprom(struct bttv *btv)
 {
-        int tuner_make,tuner_tv_fm,tuner_format,tuner=0;
+        int tuner_make,tuner_tv_fm,tuner_format,tuner=0,remote;
 
 	tuner_make   = (eeprom_data[0x41] & 0x7);
         tuner_tv_fm  = (eeprom_data[0x41] & 0x18) >> 3;
         tuner_format = (eeprom_data[0x42] & 0xf0) >> 4;
+	remote       = (eeprom_data[0x42] & 0x01);
 
 	if (tuner_make == 0 || tuner_make == 2)
 		if(tuner_format <=9)
@@ -1492,11 +1633,32 @@
 		btv->nr,eeprom_data[0x41],eeprom_data[0x42]);
 	if(tuner) {
 		btv->tuner_type=tuner;
-		printk("%d\n",tuner);
+		printk("%d",tuner);
 	} else
-		printk("Unknown type\n");
+		printk("Unknown type");
+	printk(" radio:%s remote control:%s\n",
+		tuner_tv_fm?"yes":"no",
+		remote?"yes":"no");
 }
 
+/* used on Voodoo TV/FM (Voodoo 200), S0 wired to 0x10000 */
+void bttv_tda9880_setnorm(struct bttv *btv, int norm)
+{
+	// fix up our card entry
+	if(norm==VIDEO_MODE_NTSC) {
+		bttv_tvcards[BTTV_VOODOOTV_FM].audiomux[0]=0x957fff;
+		bttv_tvcards[BTTV_VOODOOTV_FM].audiomux[4]=0x957fff;
+		dprintk("bttv_tda9880_setnorm to NTSC\n");
+	}
+	else {
+	        bttv_tvcards[BTTV_VOODOOTV_FM].audiomux[0]=0x947fff;
+                bttv_tvcards[BTTV_VOODOOTV_FM].audiomux[4]=0x947fff;
+		dprintk("bttv_tda9880_setnorm to PAL\n");
+	}
+	// set GPIO according
+	btaor(bttv_tvcards[btv->type].audiomux[btv->audio],
+              ~bttv_tvcards[btv->type].gpiomask, BT848_GPIO_DATA);
+}
 
 
 /*
@@ -1506,7 +1668,7 @@
  * Hauppauge:  pin  5
  * Voodoo:     pin 20
  */
-void __devinit bttv_boot_msp34xx(struct bttv *btv, int pin)
+static void __devinit boot_msp34xx(struct bttv *btv, int pin)
 {
 	int mask = (1 << pin);
 
@@ -1918,9 +2080,115 @@
 		}
 	} else {
 		v->mode = VIDEO_SOUND_MONO | VIDEO_SOUND_STEREO |
-			  VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2;
+			VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2;
 	}
 }
+
+/*
+ * Dariusz Kowalewski <darekk@automex.pl>
+ * sound control for FlyVideo 2000S (with tda9874 decoder) 
+ * based on pvbt878p9b_audio() - this is not tested, please fix!!!
+ */
+static void
+fv2000s_audio(struct bttv *btv, struct video_audio *v, int set)
+{
+	unsigned int val = 0xffff;
+
+#if BTTV_VERSION_CODE > KERNEL_VERSION(0,8,0)
+	if (btv->radio_user)
+		return;
+#else
+	if (btv->radio)
+		return;
+#endif
+	if (set) {
+		if (v->mode & VIDEO_SOUND_MONO)	{
+			val = 0x0000;
+		}
+		if ((v->mode & (VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2))
+		    || (v->mode & VIDEO_SOUND_STEREO)) {
+			val = 0x1080; //-dk-???: 0x0880, 0x0080, 0x1800 ...
+		}
+		if (val != 0xffff) {
+			btaor(val, ~0x1800, BT848_GPIO_DATA);
+			if (bttv_gpio)
+				bttv_gpio_tracking(btv,"fv2000s");
+		}
+	} else {
+		v->mode = VIDEO_SOUND_MONO | VIDEO_SOUND_STEREO |
+			VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2;
+	}
+}
+
+/*
+ * sound control for Canopus WinDVR PCI
+ * Masaki Suzuki <masaki@btree.org>
+ */
+static void
+windvr_audio(struct bttv *btv, struct video_audio *v, int set)
+{
+        unsigned long val = 0;
+
+        if (set) {
+                if (v->mode & VIDEO_SOUND_MONO)
+                        val = 0x040000;
+                if (v->mode & VIDEO_SOUND_LANG1)
+                        val = 0;
+                if (v->mode & VIDEO_SOUND_LANG2)
+                        val = 0x100000;
+                if (v->mode & VIDEO_SOUND_STEREO)
+                        val = 0;
+                if (val) {
+                        btaor(val, ~0x140000, BT848_GPIO_DATA);
+                        if (bttv_gpio)
+                                bttv_gpio_tracking(btv,"windvr");
+                }
+        } else {
+                v->mode = VIDEO_SOUND_MONO | VIDEO_SOUND_STEREO |
+                          VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2;
+        }
+}
+
+/* RemoteVision MX (rv605) muxsel helper [Miguel Freitas]
+ *
+ * This is needed because rv605 don't use a normal multiplex, but a crosspoint
+ * switch instead (CD22M3494E). This IC can have multiple active connections
+ * between Xn (input) and Yn (output) pins. We need to clear any existing
+ * connection prior to establish a new one, pulsing the STROBE pin.
+ *
+ * The board hardwire Y0 (xpoint) to MUX1 and MUXOUT to Yin.
+ * GPIO pins are wired as:
+ *  GPIO[0:3] - AX[0:3] (xpoint) - P1[0:3] (microcontroler)
+ *  GPIO[4:6] - AY[0:2] (xpoint) - P1[4:6] (microcontroler)
+ *  GPIO[7]   - DATA (xpoint)    - P1[7] (microcontroler)
+ *  GPIO[8]   -                  - P3[5] (microcontroler)
+ *  GPIO[9]   - RESET (xpoint)   - P3[6] (microcontroler)
+ *  GPIO[10]  - STROBE (xpoint)  - P3[7] (microcontroler)
+ *  GPINTR    -                  - P3[4] (microcontroler)
+ *
+ * The microcontroler is a 80C32 like. It should be possible to change xpoint
+ * configuration either directly (as we are doing) or using the microcontroler
+ * which is also wired to I2C interface. I have no further info on the
+ * microcontroler features, one would need to disassembly the firmware.
+ * note: the vendor refused to give any information on this product, all
+ *       that stuff was found using a multimeter! :)
+ */
+static void rv605_muxsel(struct bttv *btv, unsigned int input)
+{
+	/* reset all conections */
+	btaor(0x200,~0x200, BT848_GPIO_DATA);
+	mdelay(1);
+	btaor(0x000,~0x200, BT848_GPIO_DATA);
+	mdelay(1);
+
+	/* create a new conection */
+	btaor(0x080,~0x480, BT848_GPIO_DATA);
+	btaor(0x480,~0x480, BT848_GPIO_DATA);
+	mdelay(1);
+	btaor(0x080,~0x480, BT848_GPIO_DATA);
+	mdelay(1);
+}
+
 
 /* ----------------------------------------------------------------------- */
 /* motherboard chipset specific stuff                                      */
diff -Nru a/drivers/media/video/bttv-driver.c b/drivers/media/video/bttv-driver.c
--- a/drivers/media/video/bttv-driver.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/bttv-driver.c	Fri Mar 15 17:51:02 2002
@@ -1,20 +1,23 @@
 /*
     bttv - Bt848 frame grabber driver
-
-    Copyright (C) 1996,97,98 Ralph  Metzler (rjkm@thp.uni-koeln.de)
-                           & Marcus Metzler (mocm@thp.uni-koeln.de)
-    (c) 1999,2000 Gerd Knorr <kraxel@goldbach.in-berlin.de>
-
+    
+    Copyright (C) 1996,97,98 Ralph  Metzler <rjkm@thp.uni-koeln.de>
+                           & Marcus Metzler <mocm@thp.uni-koeln.de>
+    (c) 1999-2002 Gerd Knorr <kraxel@bytesex.org>
+    
+    some v4l2 code lines are taken from Justin's bttv2 driver which is
+    (c) 2000 Justin Schoeman <justin@suntiger.ee.up.ac.za>
+    
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
     the Free Software Foundation; either version 2 of the License, or
     (at your option) any later version.
-
+    
     This program is distributed in the hope that it will be useful,
     but WITHOUT ANY WARRANTY; without even the implied warranty of
     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     GNU General Public License for more details.
-
+    
     You should have received a copy of the GNU General Public License
     along with this program; if not, write to the Free Software
     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
@@ -26,63 +29,61 @@
 #include <linux/errno.h>
 #include <linux/fs.h>
 #include <linux/kernel.h>
-#include <linux/major.h>
-#include <linux/slab.h>
-#include <linux/mm.h>
-#include <linux/poll.h>
-#include <linux/pci.h>
-#include <linux/signal.h>
-#include <asm/io.h>
-#include <linux/ioport.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
 #include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/wrapper.h>
 #include <linux/interrupt.h>
-#include <linux/kmod.h>
-#include <linux/vmalloc.h>
-#include <linux/init.h>
+#include <linux/kdev_t.h>
+
+#include <asm/io.h>
 
 #include "bttvp.h"
 #include "tuner.h"
 
-#define DEBUG(x)	/* Debug driver */
-#define MIN(a,b) (((a)>(b))?(b):(a))
-#define MAX(a,b) (((a)>(b))?(a):(b))
-
-static void bt848_set_risc_jmps(struct bttv *btv, int state);
+/* 2.4 / 2.5 driver compatibility stuff */
 
 int bttv_num;			/* number of Bt848s in use */
 struct bttv bttvs[BTTV_MAX];
 
-/* configuration variables */
+unsigned int bttv_debug = 0;
+unsigned int bttv_verbose = 1;
+unsigned int bttv_gpio = 0;
+
+/* config variables */
 #if defined(__sparc__) || defined(__powerpc__) || defined(__hppa__)
 static unsigned int bigendian=1;
 #else
 static unsigned int bigendian=0;
 #endif
-static unsigned int radio[BTTV_MAX];
-static unsigned int fieldnr = 0;
+static unsigned int radio[4];
 static unsigned int irq_debug = 0;
-static unsigned int gbuffers = 2;
-static unsigned int gbufsize = BTTV_MAX_FBUF;
-static unsigned int combfilter = 0;
-static unsigned int lumafilter = 0;
+static unsigned int gbuffers = 8;
+static unsigned int gbufsize = 0x208000;
+static unsigned int fdsr = 0;
+static unsigned int latency = -1;
+
 static int video_nr = -1;
 static int radio_nr = -1;
 static int vbi_nr = -1;
-unsigned int bttv_debug = 0;
-unsigned int bttv_verbose = 1;
-unsigned int bttv_gpio = 0;
 
-/* insmod options */
+/* options */
+static unsigned int combfilter = 0;
+static unsigned int lumafilter = 0;
+static unsigned int automute   = 1;
+static unsigned int chroma_agc = 0;
+static unsigned int adc_crush  = 1;
+
+/* API features (turn on/off stuff for testing) */
+static unsigned int sloppy     = 0;
+static unsigned int mmap       = 1;
+#ifdef HAVE_V4L2
+static unsigned int v4l2       = 1;
+#endif
+
+
+/* insmod args */
 MODULE_PARM(radio,"1-4i");
 MODULE_PARM_DESC(radio,"The TV card supports radio, default is 0 (no)");
 MODULE_PARM(bigendian,"i");
 MODULE_PARM_DESC(bigendian,"byte order of the framebuffer, default is native endian");
-MODULE_PARM(fieldnr,"i");
-MODULE_PARM_DESC(fieldnr,"count fields, default is 0 (no)");
 MODULE_PARM(bttv_verbose,"i");
 MODULE_PARM_DESC(bttv_verbose,"verbose startup messages, default is 1 (yes)");
 MODULE_PARM(bttv_gpio,"i");
@@ -92,17 +93,33 @@
 MODULE_PARM(irq_debug,"i");
 MODULE_PARM_DESC(irq_debug,"irq handler debug messages, default is 0 (no)");
 MODULE_PARM(gbuffers,"i");
-MODULE_PARM_DESC(gbuffers,"number of capture buffers, default is 2 (64 max)");
+MODULE_PARM_DESC(gbuffers,"number of capture buffers. range 2-32, default 8");
 MODULE_PARM(gbufsize,"i");
 MODULE_PARM_DESC(gbufsize,"size of the capture buffers, default is 0x208000");
-MODULE_PARM(combfilter,"i");
-MODULE_PARM(lumafilter,"i");
+MODULE_PARM(fdsr,"i");
+MODULE_PARM(latency,"i");
+MODULE_PARM_DESC(latency,"pci latency timer");
 
 MODULE_PARM(video_nr,"i");
 MODULE_PARM(radio_nr,"i");
 MODULE_PARM(vbi_nr,"i");
 
-MODULE_DESCRIPTION("bttv - v4l driver module for bt848/878 based cards");
+MODULE_PARM(combfilter,"i");
+MODULE_PARM(lumafilter,"i");
+MODULE_PARM(automute,"i");
+MODULE_PARM_DESC(automute,"mute audio on bad/missing video signal, default is 1 (yes)");
+MODULE_PARM(chroma_agc,"i");
+MODULE_PARM_DESC(chroma_agc,"enables the AGC of chroma signal, default is 0 (no)");
+MODULE_PARM(adc_crush,"i");
+MODULE_PARM_DESC(adc_crush,"enables the luminance ADC crush, default is 1 (yes)");
+
+MODULE_PARM(sloppy,"i");
+MODULE_PARM(mmap,"i");
+#ifdef HAVE_V4L2
+MODULE_PARM(v4l2,"i");
+#endif
+
+MODULE_DESCRIPTION("bttv - v4l/v4l2 driver module for bt848/878 based cards");
 MODULE_AUTHOR("Ralph Metzler & Marcus Metzler & Gerd Knorr");
 MODULE_LICENSE("GPL");
 
@@ -112,200 +129,486 @@
 __setup("bttv.radio=", p_radio);
 #endif
 
-#define I2C_TIMING (0x7<<4)
-#define I2C_DELAY   10
+#ifndef HAVE_V4L2
+/* some dummy defines to avoid cluttering up the source code with
+   a huge number of ifdef's for V4L2 */
+# define V4L2_STD_PAL          -1
+# define V4L2_STD_NTSC         -1
+# define V4L2_STD_SECAM        -1
+# define V4L2_STD_PAL_60       -1
+# define V4L2_STD_PAL_M        -1
+# define V4L2_STD_PAL_N        -1
+# define V4L2_STD_NTSC_N       -1
+# define V4L2_PIX_FMT_GREY     -1
+# define V4L2_PIX_FMT_HI240    -1
+# define V4L2_PIX_FMT_RGB555   -1
+# define V4L2_PIX_FMT_RGB555X  -1
+# define V4L2_PIX_FMT_RGB565   -1
+# define V4L2_PIX_FMT_RGB565X  -1
+# define V4L2_PIX_FMT_BGR24    -1
+# define V4L2_PIX_FMT_BGR32    -1
+# define V4L2_PIX_FMT_RGB32    -1
+# define V4L2_PIX_FMT_YUYV     -1
+# define V4L2_PIX_FMT_UYVY     -1
+# define V4L2_PIX_FMT_YUV422P  -1
+# define V4L2_PIX_FMT_YUV420   -1
+# define V4L2_PIX_FMT_YVU420   -1
+# define V4L2_PIX_FMT_YUV411P  -1
+# define V4L2_PIX_FMT_YUV410   -1
+# define V4L2_PIX_FMT_YVU410   -1
+# define V4L2_BUF_TYPE_CAPTURE -1
+# define V4L2_BUF_TYPE_VBI     -1
+# define BTTV_APIS "[v4l]"
+#else
+# define BTTV_APIS "[v4l/v4l2]"
+#endif
 
-#define I2C_SET(CTRL,DATA) \
-    { btwrite((CTRL<<1)|(DATA), BT848_I2C); udelay(I2C_DELAY); }
-#define I2C_GET()   (btread(BT848_I2C)&1)
+/* ----------------------------------------------------------------------- */
+/* static data                                                             */
 
-#define BURSTOFFSET 76
-#define BTTV_ERRORS 5
+const struct bttv_tvnorm bttv_tvnorms[] = {
+	/* PAL-BDGHI */
+        { V4L2_STD_PAL, 35468950,
+          922, 576, 1135, 0x7f, 0x72, (BT848_IFORM_PAL_BDGHI|BT848_IFORM_XT1),
+          1135, 186, 922, 0x20, 255},
+	/* NTSC */
+	{ V4L2_STD_NTSC, 28636363,
+          754, 480,  910, 0x70, 0x5d, (BT848_IFORM_NTSC|BT848_IFORM_XT0),
+          910, 135, 754, 0x1a, 144},
+	/* SECAM */
+        { V4L2_STD_SECAM, 35468950,
+          922, 576, 1135, 0x7f, 0xa0, (BT848_IFORM_SECAM|BT848_IFORM_XT1),
+          1135, 186, 922, 0x20, 255},
 
+	/* these ones are bttv specific (for v4l1) */
+        /* PAL-NC */
+        { V4L2_STD_PAL_60, 28636363,
+          640, 576,  910, 0x7f, 0x72, (BT848_IFORM_PAL_NC|BT848_IFORM_XT0),
+          780, 130, 734, 0x1a, 144},
+	/* PAL-M */
+	{ V4L2_STD_PAL_M, 28636363, 
+          640, 480, 910, 0x70, 0x5d, (BT848_IFORM_PAL_M|BT848_IFORM_XT0),
+	  780, 135, 754, 0x1a, 144},
+	/* PAL-N */
+	{ V4L2_STD_PAL_N, 35468950, 
+          768, 576, 1135, 0x7f, 0x72, (BT848_IFORM_PAL_N|BT848_IFORM_XT0),
+	  944, 186, 922, 0x20, 144},
+	/* NTSC-Japan */
+	{ V4L2_STD_NTSC_N, 28636363,
+          640, 480,  910, 0x70, 0x5d, (BT848_IFORM_NTSC_J|BT848_IFORM_XT0),
+	  780, 135, 754, 0x16, 144},
+};
+const int BTTV_TVNORMS = (sizeof(bttv_tvnorms)/sizeof(struct bttv_tvnorm));
 
-/*******************************/
-/* Memory management functions */
-/*******************************/
+/* ----------------------------------------------------------------------- */
+/* bttv format list
+   packed pixel formats must come first */
+const struct bttv_format bttv_formats[] = {
+	{
+		name:     "8 bpp, gray",
+		palette:  VIDEO_PALETTE_GREY,
+		fourcc:   V4L2_PIX_FMT_GREY,
+		btformat: BT848_COLOR_FMT_Y8,
+		depth:    8,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "8 bpp, dithered color",
+		palette:  VIDEO_PALETTE_HI240,
+		fourcc:   V4L2_PIX_FMT_HI240,
+		btformat: BT848_COLOR_FMT_RGB8,
+		depth:    8,
+		flags:    FORMAT_FLAGS_PACKED | FORMAT_FLAGS_DITHER,
+	},{
+		name:     "15 bpp RGB, le",
+		palette:  VIDEO_PALETTE_RGB555,
+		fourcc:   V4L2_PIX_FMT_RGB555,
+		btformat: BT848_COLOR_FMT_RGB15,
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "15 bpp RGB, be",
+		palette:  -1,
+		fourcc:   V4L2_PIX_FMT_RGB555X,
+		btformat: BT848_COLOR_FMT_RGB15,
+		btswap:   0x03, /* byteswap */
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "16 bpp RGB, le",
+		palette:  VIDEO_PALETTE_RGB565,
+		fourcc:   V4L2_PIX_FMT_RGB565,
+		btformat: BT848_COLOR_FMT_RGB16,
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "16 bpp RGB, be",
+		palette:  -1,
+		fourcc:   V4L2_PIX_FMT_RGB565X,
+		btformat: BT848_COLOR_FMT_RGB16,
+		btswap:   0x03, /* byteswap */
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "24 bpp RGB, le",
+		palette:  VIDEO_PALETTE_RGB24,
+		fourcc:   V4L2_PIX_FMT_BGR24,
+		btformat: BT848_COLOR_FMT_RGB24,
+		depth:    24,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "32 bpp RGB, le",
+		palette:  VIDEO_PALETTE_RGB32,
+		fourcc:   V4L2_PIX_FMT_BGR32,
+		btformat: BT848_COLOR_FMT_RGB32,
+		depth:    32,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "32 bpp RGB, be",
+		palette:  -1,
+		fourcc:   V4L2_PIX_FMT_RGB32,
+		btformat: BT848_COLOR_FMT_RGB32,
+		btswap:   0x0f, /* byte+word swap */
+		depth:    32,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "4:2:2, packed, YUYV",
+		palette:  VIDEO_PALETTE_YUV422,
+		fourcc:   V4L2_PIX_FMT_YUYV,
+		btformat: BT848_COLOR_FMT_YUY2,
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "4:2:2, packed, YUYV",
+		palette:  VIDEO_PALETTE_YUYV,
+		fourcc:   V4L2_PIX_FMT_YUYV,
+		btformat: BT848_COLOR_FMT_YUY2,
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "4:2:2, packed, UYVY",
+		palette:  VIDEO_PALETTE_UYVY,
+		fourcc:   V4L2_PIX_FMT_UYVY,
+		btformat: BT848_COLOR_FMT_YUY2,
+		btswap:   0x03, /* byteswap */
+		depth:    16,
+		flags:    FORMAT_FLAGS_PACKED,
+	},{
+		name:     "4:2:2, planar, Y-Cb-Cr",
+		palette:  VIDEO_PALETTE_YUV422P,
+		fourcc:   V4L2_PIX_FMT_YUV422P,
+		btformat: BT848_COLOR_FMT_YCrCb422,
+		depth:    16,
+		flags:    FORMAT_FLAGS_PLANAR,
+		hshift:   1,
+		vshift:   0,
+	},{
+		name:     "4:2:0, planar, Y-Cb-Cr",
+		palette:  VIDEO_PALETTE_YUV420P,
+		fourcc:   V4L2_PIX_FMT_YUV420,
+		btformat: BT848_COLOR_FMT_YCrCb422,
+		depth:    12,
+		flags:    FORMAT_FLAGS_PLANAR,
+		hshift:   1,
+		vshift:   1,
+	},{
+		name:     "4:2:0, planar, Y-Cr-Cb",
+		palette:  -1,
+		fourcc:   V4L2_PIX_FMT_YVU420,
+		btformat: BT848_COLOR_FMT_YCrCb422,
+		depth:    12,
+		flags:    FORMAT_FLAGS_PLANAR | FORMAT_FLAGS_CrCb,
+		hshift:   1,
+		vshift:   1,
+	},{
+		name:     "4:1:1, planar, Y-Cb-Cr",
+		palette:  VIDEO_PALETTE_YUV411P,
+		fourcc:   V4L2_PIX_FMT_YUV411P,
+		btformat: BT848_COLOR_FMT_YCrCb411,
+		depth:    12,
+		flags:    FORMAT_FLAGS_PLANAR,
+		hshift:   2,
+		vshift:   0,
+	},{
+		name:     "4:1:0, planar, Y-Cb-Cr",
+		palette:  VIDEO_PALETTE_YUV410P,
+		fourcc:   V4L2_PIX_FMT_YUV410,
+		btformat: BT848_COLOR_FMT_YCrCb411,
+		depth:    9,
+		flags:    FORMAT_FLAGS_PLANAR,
+		hshift:   2,
+		vshift:   2,
+	},{
+		name:     "4:1:0, planar, Y-Cr-Cb",
+		palette:  -1,
+		fourcc:   V4L2_PIX_FMT_YVU410,
+		btformat: BT848_COLOR_FMT_YCrCb411,
+		depth:    9,
+		flags:    FORMAT_FLAGS_PLANAR | FORMAT_FLAGS_CrCb,
+		hshift:   2,
+		vshift:   2,
+	},{
+		name:     "raw scanlines",
+		palette:  VIDEO_PALETTE_RAW,
+		fourcc:   -1,
+		btformat: BT848_COLOR_FMT_RAW,
+		depth:    8,
+		flags:    FORMAT_FLAGS_RAW,
+	}
+};
+const int BTTV_FORMATS = (sizeof(bttv_formats)/sizeof(struct bttv_format));
 
-#define MDEBUG(x)	do { } while(0)		/* Debug memory management */
+/* ----------------------------------------------------------------------- */
 
-/* [DaveM] I've recoded most of this so that:
- * 1) It's easier to tell what is happening
- * 2) It's more portable, especially for translating things
- *    out of vmalloc mapped areas in the kernel.
- * 3) Less unnecessary translations happen.
- *
- * The code used to assume that the kernel vmalloc mappings
- * existed in the page tables of every process, this is simply
- * not guarenteed.  We now use pgd_offset_k which is the
- * defined way to get at the kernel page tables.
- */
+#ifdef HAVE_V4L2
+#define V4L2_CID_PRIVATE_CHROMA_AGC  (V4L2_CID_PRIVATE_BASE + 0)
+#define V4L2_CID_PRIVATE_COMBFILTER  (V4L2_CID_PRIVATE_BASE + 1)
+#define V4L2_CID_PRIVATE_AUTOMUTE    (V4L2_CID_PRIVATE_BASE + 2)
+#define V4L2_CID_PRIVATE_LUMAFILTER  (V4L2_CID_PRIVATE_BASE + 3)
+#define V4L2_CID_PRIVATE_AGC_CRUSH   (V4L2_CID_PRIVATE_BASE + 4)
+#define V4L2_CID_PRIVATE_LASTP1      (V4L2_CID_PRIVATE_BASE + 5)
+
+static const struct v4l2_queryctrl no_ctl = {
+	name:  "42",
+	flags: V4L2_CTRL_FLAG_DISABLED,
+};
+static const struct v4l2_queryctrl bttv_ctls[] = {
+	/* --- video --- */
+	{
+		id:            V4L2_CID_BRIGHTNESS,
+		name:          "Brightness",
+		minimum:       0,
+		maximum:       65535,
+		step:          256,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_VIDEO,
+		group:         "Video",
+	},{
+		id:            V4L2_CID_CONTRAST,
+		name:          "Contrast",
+		minimum:       0,
+		maximum:       65535,
+		step:          128,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_VIDEO,
+		group:         "Video",
+	},{
+		id:            V4L2_CID_SATURATION,
+		name:          "Saturation",
+		minimum:       0,
+		maximum:       65535,
+		step:          128,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_VIDEO,
+		group:         "Video",
+	},{
+		id:            V4L2_CID_HUE,
+		name:          "Hue",
+		minimum:       0,
+		maximum:       65535,
+		step:          256,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_VIDEO,
+		group:         "Video",
+	},
+	/* --- audio --- */
+	{
+		id:            V4L2_CID_AUDIO_MUTE,
+		name:          "Mute",
+		minimum:       0,
+		maximum:       1,
+		type:          V4L2_CTRL_TYPE_BOOLEAN,
+		category:      V4L2_CTRL_CAT_AUDIO,
+		group:         "Audio",
+	},{
+		id:            V4L2_CID_AUDIO_VOLUME,
+		name:          "Volume",
+		minimum:       0,
+		maximum:       65535,
+		step:          65535/100,
+		default_value: 65535,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_AUDIO,
+		group:         "Audio",
+	},{
+		id:            V4L2_CID_AUDIO_BALANCE,
+		name:          "Balance",
+		minimum:       0,
+		maximum:       65535,
+		step:          65535/100,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_AUDIO,
+		group:         "Audio",
+	},{
+		id:            V4L2_CID_AUDIO_BASS,
+		name:          "Bass",
+		minimum:       0,
+		maximum:       65535,
+		step:          65535/100,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_AUDIO,
+		group:         "Audio",
+	},{
+		id:            V4L2_CID_AUDIO_TREBLE,
+		name:          "Treble",
+		minimum:       0,
+		maximum:       65535,
+		step:          65535/100,
+		default_value: 32768,
+		type:          V4L2_CTRL_TYPE_INTEGER,
+		category:      V4L2_CTRL_CAT_AUDIO,
+		group:         "Audio",
+	},
+	/* --- private --- */
+	{
+		id:            V4L2_CID_PRIVATE_CHROMA_AGC,
+		name:          "chroma agc",
+		minimum:       0,
+		maximum:       1,
+		type:          V4L2_CTRL_TYPE_BOOLEAN,
+		group:         "Private",
+	},{
+		id:            V4L2_CID_PRIVATE_COMBFILTER,
+		name:          "combfilter",
+		minimum:       0,
+		maximum:       1,
+		type:          V4L2_CTRL_TYPE_BOOLEAN,
+		group:         "Private",
+	},{
+		id:            V4L2_CID_PRIVATE_AUTOMUTE,
+		name:          "automute",
+		minimum:       0,
+		maximum:       1,
+		type:          V4L2_CTRL_TYPE_BOOLEAN,
+		group:         "Private",
+	},{
+		id:            V4L2_CID_PRIVATE_LUMAFILTER,
+		name:          "luma decimation filter",
+		minimum:       0,
+		maximum:       1,
+		type:          V4L2_CTRL_TYPE_BOOLEAN,
+		group:         "Private",
+	},{
+		id:            V4L2_CID_PRIVATE_AGC_CRUSH,
+		name:          "agc crush",
+		minimum:       0,
+		maximum:       1,
+		type:          V4L2_CTRL_TYPE_BOOLEAN,
+		group:         "Private",
+	}
+};
+const int BTTV_CTLS = (sizeof(bttv_ctls)/sizeof(struct v4l2_queryctrl));
+#endif /* HAVE_V4L2 */
 
+/* ----------------------------------------------------------------------- */
+/* resource management                                                     */
 
-/*
- * Take a vmalloc address, and turn it into
- * the aliased kernel virtual address..
- *
- * CAREFUL! Anybody who does this gets to sit
- * in their own cr*p when it comes to virtual
- * cache aliases. It's _your_ problem.
- *
- * Also, note how it only works within one page.
- * If you're doing page-crossing stuff, you're on
- * your own.
- *
- * THIS IS BROKEN CODE! You shouldn't do things
- * like this.
- */
-static inline void *vmalloc_to_virt(void *addr)
+static
+int check_alloc_btres(struct bttv *btv, struct bttv_fh *fh, int bit)
 {
-	struct page *page = vmalloc_to_page(addr);
-	return page_address(page) + (~PAGE_MASK & (unsigned long)addr);
-}
+	if (fh->resources & bit)
+		/* have it already allocated */
+		return 1;
 
-static inline unsigned long kvirt_to_bus(unsigned long addr) 
-{
-	unsigned long ret;
-	ret = virt_to_bus(vmalloc_to_virt((void *)addr));
-        MDEBUG(printk("kv2b(%lx-->%lx)", addr, ret));
-        return ret;
+	/* is it free? */
+	down(&btv->reslock);
+	if (btv->resources & bit) {
+		/* no, someone else uses it */
+		up(&btv->reslock);
+		return 0;
+	}
+	/* it's free, grab it */
+	fh->resources  |= bit;
+	btv->resources |= bit;
+	up(&btv->reslock);
+	return 1;
 }
 
-/* Here we want the physical address of the memory.
- * This is used when initializing the contents of the area.
- */
-static inline unsigned long kvirt_to_pa(unsigned long addr) 
+static
+int check_btres(struct bttv_fh *fh, int bit)
 {
-        unsigned long ret;
-	ret = virt_to_phys(vmalloc_to_virt((void *)addr));
-        MDEBUG(printk("kv2pa(%lx-->%lx)", addr, ret));
-        return ret;
+	return (fh->resources & bit);
 }
 
-static void * rvmalloc(unsigned long size)
+static
+int locked_btres(struct bttv *btv, int bit)
 {
-	void * mem;
-	unsigned long adr;
-
-	size=PAGE_ALIGN(size);
-	mem=vmalloc_32(size);
-	if (NULL == mem)
-		printk(KERN_INFO "bttv: vmalloc_32(%lu) failed\n",size);
-	else {
-		/* Clear the ram out, no junk to the user */
-		memset(mem, 0, size);
-	        adr=(unsigned long) mem;
-		while (size > 0) 
-                {
-			mem_map_reserve(vmalloc_to_page((void *)adr));
-			adr+=PAGE_SIZE;
-			size-=PAGE_SIZE;
-		}
-	}
-	return mem;
+	return (btv->resources & bit);
 }
 
-static void rvfree(void * mem, unsigned long size)
+static
+void free_btres(struct bttv *btv, struct bttv_fh *fh, int bits)
 {
-        unsigned long adr;
-        
-	if (mem) 
-	{
-	        adr=(unsigned long) mem;
-		while ((long) size > 0)
-                {
-			mem_map_unreserve(vmalloc_to_page((void *)adr));
-			adr+=PAGE_SIZE;
-			size-=PAGE_SIZE;
-		}
-		vfree(mem);
+#if 1 /* DEBUG */
+	if ((fh->resources & bits) != bits) {
+		/* trying to free ressources not allocated by us ... */
+		printk("bttv: BUG! (btres)\n");
 	}
+#endif
+	down(&btv->reslock);
+	fh->resources  &= ~bits;
+	btv->resources &= ~bits;
+	up(&btv->reslock);
 }
 
-
-
+/* ----------------------------------------------------------------------- */
 /*
- *	Create the giant waste of buffer space we need for now
- *	until we get DMA to user space sorted out (probably 2.3.x)
+ * sanity check for video framebuffer address ranges (overlay).
+ * let's see if that address range actually belongs to some
+ * pci display adapter.
  *
- *	We only create this as and when someone uses mmap
+ * FIXME: stuff isn't portable.  It's also a v4l API bug, pass a
+ * physical address in VIDIOCSFBUF isn't portable too ...
  */
- 
-static int fbuffer_alloc(struct bttv *btv)
-{
-	if(!btv->fbuffer)
-		btv->fbuffer=(unsigned char *) rvmalloc(gbuffers*gbufsize);
-	else
-		printk(KERN_ERR "bttv%d: Double alloc of fbuffer!\n",
-			btv->nr);
-	if(!btv->fbuffer)
-		return -ENOBUFS;
-	return 0;
-}
-
-/* ----------------------------------------------------------------------- */
 
-void bttv_gpio_tracking(struct bttv *btv, char *comment)
+static int
+find_videomem(unsigned long from, unsigned long to)
 {
-	unsigned int outbits, data;
-	outbits = btread(BT848_GPIO_OUT_EN);
-	data    = btread(BT848_GPIO_DATA);
-	printk(KERN_DEBUG "bttv%d: gpio: en=%08x, out=%08x in=%08x [%s]\n",
-	       btv->nr,outbits,data & outbits, data & ~outbits, comment);
-}
-
-static char *audio_modes[] = { "audio: tuner", "audio: radio", "audio: extern",
-			       "audio: intern", "audio: off" };
-
-static void audio(struct bttv *btv, int mode, int no_irq_context)
-{
-	btaor(bttv_tvcards[btv->type].gpiomask, ~bttv_tvcards[btv->type].gpiomask,
-              BT848_GPIO_OUT_EN);
-
-	switch (mode)
-	{
-	        case AUDIO_MUTE:
-                        btv->audio|=AUDIO_MUTE;
-			break;
- 		case AUDIO_UNMUTE:
-			btv->audio&=~AUDIO_MUTE;
-			mode=btv->audio;
-			break;
-		case AUDIO_OFF:
-			mode=AUDIO_OFF;
-			break;
-		case AUDIO_ON:
-			mode=btv->audio;
-			break;
-		default:
-			btv->audio&=AUDIO_MUTE;
-			btv->audio|=mode;
-			break;
+#if PCI_DMA_BUS_IS_PHYS
+	struct pci_dev *dev = NULL;
+	int i,match,found;
+
+	found = 0;
+	dprintk(KERN_DEBUG "bttv: checking video framebuffer address"
+		" (%lx-%lx)\n",from,to);
+        pci_for_each_dev(dev) {
+		if (dev->class != PCI_CLASS_NOT_DEFINED_VGA &&
+		    dev->class >> 16 != PCI_BASE_CLASS_DISPLAY)
+			continue;
+		dprintk(KERN_DEBUG
+			"  pci display adapter %04x:%04x at %02x:%02x.%x\n",
+			dev->vendor,dev->device,dev->bus->number,
+			PCI_SLOT(dev->devfn),PCI_FUNC(dev->devfn));
+		for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
+			if (!(dev->resource[i].flags & IORESOURCE_MEM))
+				continue;
+			if (dev->resource[i].flags & IORESOURCE_READONLY)
+				continue;
+			match = (from >= dev->resource[i].start) &&
+				(to-1 <= dev->resource[i].end);
+			if (match)
+				found = 1;
+			dprintk(KERN_DEBUG "    memory at %08lx-%08lx%s\n",
+				dev->resource[i].start,
+				dev->resource[i].end,
+				match ? "  (check passed)" : "");
+		}
 	}
-        /* if audio mute or not in H-lock, turn audio off */
-	if ((btv->audio&AUDIO_MUTE))
-	        mode=AUDIO_OFF;
-        if ((mode == AUDIO_TUNER) && (btv->radio))
-		mode = AUDIO_RADIO;
-	btaor(bttv_tvcards[btv->type].audiomux[mode],
-              ~bttv_tvcards[btv->type].gpiomask, BT848_GPIO_DATA);
-	if (bttv_gpio)
-		bttv_gpio_tracking(btv,audio_modes[mode]);
-	if (no_irq_context)
-		bttv_call_i2c_clients(btv,AUDC_SET_INPUT,&(mode));
-}
-
-
-extern inline void bt848_dma(struct bttv *btv, uint state)
-{
-	if (state)
-		btor(3, BT848_GPIO_DMA_CTL);
-	else
-		btand(~3, BT848_GPIO_DMA_CTL);
+	return found;
+#else
+	/* Hmm, the physical address passed to us is probably bogous */
+	dprintk(KERN_DEBUG "bttv: no overlay for this arch, sorry\n");
+	return 0;
+#endif
 }
 
-
-/* If Bt848a or Bt849, use PLL for PAL/SECAM and crystal for NTSC*/
+/* ----------------------------------------------------------------------- */
+/* If Bt848a or Bt849, use PLL for PAL/SECAM and crystal for NTSC          */
 
 /* Frequency = (F_input / PLL_X) * PLL_I.PLL_F/PLL_C 
    PLL_X = Reference pre-divider (0=1, 1=2) 
@@ -334,7 +637,6 @@
         fout=(fout%fin)*256;
         fl=fout/fin;
 
-        /*printk("0x%02x 0x%02x 0x%02x\n", fi, fh, fl);*/
         btwrite(fl, BT848_PLL_F_LO);
         btwrite(fh, BT848_PLL_F_HI);
         btwrite(fi|BT848_PLL_X, BT848_PLL_XCI);
@@ -343,2301 +645,2378 @@
 static int set_pll(struct bttv *btv)
 {
         int i;
-	unsigned long tv;
 
         if (!btv->pll.pll_crystal)
                 return 0;
 
         if (btv->pll.pll_ifreq == btv->pll.pll_ofreq) {
                 /* no PLL needed */
-                if (btv->pll.pll_current == 0) {
-                        /* printk ("bttv%d: PLL: is off\n",btv->nr); */
+                if (btv->pll.pll_current == 0)
                         return 0;
-                }
-		if (bttv_verbose)
-			printk ("bttv%d: PLL: switching off\n",btv->nr);
+		vprintk("bttv%d: PLL: switching off\n",btv->nr);
                 btwrite(0x00,BT848_TGCTRL);
                 btwrite(0x00,BT848_PLL_XCI);
                 btv->pll.pll_current = 0;
                 return 0;
         }
 
-        if (btv->pll.pll_ofreq == btv->pll.pll_current) {
-                /* printk("bttv%d: PLL: no change required\n",btv->nr); */
-                return 1;
-        }
-
-        if (bttv_verbose)
-		printk("bttv%d: PLL: %d => %d ... ",btv->nr,
-		       btv->pll.pll_ifreq, btv->pll.pll_ofreq);
+        if (btv->pll.pll_ofreq == btv->pll.pll_current)
+                return 0;
 
+	vprintk("bttv%d: PLL: %d => %d ",btv->nr,
+		btv->pll.pll_ifreq, btv->pll.pll_ofreq);
 	set_pll_freq(btv, btv->pll.pll_ifreq, btv->pll.pll_ofreq);
 
-	/*  Let other people run while the PLL stabilizes */
-	tv=jiffies+HZ/10;       /* .1 seconds */
-	do
-	{
-		schedule();
-	}
-	while(time_before(jiffies,tv));
-
-        for (i=0; i<100; i++) 
-        {
-                if ((btread(BT848_DSTATUS)&BT848_DSTATUS_PLOCK))
-                        btwrite(0,BT848_DSTATUS);
-                else
-                {
+        for (i=0; i<10; i++) {
+		/*  Let other people run while the PLL stabilizes */
+		vprintk(".");
+		current->state = TASK_INTERRUPTIBLE;
+		schedule_timeout(HZ/10);
+		
+                if (btread(BT848_DSTATUS) & BT848_DSTATUS_PLOCK) {
+			btwrite(0,BT848_DSTATUS);
+                } else {
                         btwrite(0x08,BT848_TGCTRL);
                         btv->pll.pll_current = btv->pll.pll_ofreq;
-			if (bttv_verbose)
-				printk("ok\n");
-                        return 1;
+			vprintk(" ok\n");
+                        return 0;
                 }
-                mdelay(10);
         }
-        btv->pll.pll_current = 0;
-	if (bttv_verbose)
-		printk("oops\n");
+        btv->pll.pll_current = -1;
+	vprintk("failed\n");
         return -1;
 }
 
-static void bt848_muxsel(struct bttv *btv, unsigned int input)
+/* ----------------------------------------------------------------------- */
+
+static void bt848_bright(struct bttv *btv, int bright)
 {
+	int value;
 
-#if 0 /* seems no card uses this ... */
-	btaor(bttv_tvcards[btv->type].gpiomask2,~bttv_tvcards[btv->type].gpiomask2,
-              BT848_GPIO_OUT_EN);
-#endif
+	btv->bright = bright;
 
-	/* This seems to get rid of some synchronization problems */
-	btand(~(3<<5), BT848_IFORM);
-	mdelay(10); 
-        
-	input %= bttv_tvcards[btv->type].video_inputs;
-	if (input==bttv_tvcards[btv->type].svhs) 
-	{
-		btor(BT848_CONTROL_COMP, BT848_E_CONTROL);
-		btor(BT848_CONTROL_COMP, BT848_O_CONTROL);
-	}
-	else
-	{
-		btand(~BT848_CONTROL_COMP, BT848_E_CONTROL);
-		btand(~BT848_CONTROL_COMP, BT848_O_CONTROL);
-	}
-	btaor((bttv_tvcards[btv->type].muxsel[input&7]&3)<<5, ~(3<<5), BT848_IFORM);
-	audio(btv, (input!=bttv_tvcards[btv->type].tuner) ? 
-              AUDIO_EXTERN : AUDIO_TUNER, 1);
-
-#if 0 /* seems no card uses this ... */
-	btaor(bttv_tvcards[btv->type].muxsel[input]>>4,
-		~bttv_tvcards[btv->type].gpiomask2, BT848_GPIO_DATA);
-	if (bttv_gpio)
-		bttv_gpio_tracking(btv,"muxsel");
-#endif
+	/* We want -128 to 127 we get 0-65535 */
+	value = (bright >> 8) - 128;
+	btwrite(value & 0xff, BT848_BRIGHT);
 }
 
-
-struct tvnorm 
+static void bt848_hue(struct bttv *btv, int hue)
 {
-        u32 Fsc;
-        u16 swidth, sheight; /* scaled standard width, height */
-	u16 totalwidth;
-	u8 adelay, bdelay, iform;
-	u32 scaledtwidth;
-	u16 hdelayx1, hactivex1;
-	u16 vdelay;
-        u8 vbipack;
-};
-
-static struct tvnorm tvnorms[] = {
-	/* PAL-BDGHI */
-        /* max. active video is actually 922, but 924 is divisible by 4 and 3! */
- 	/* actually, max active PAL with HSCALE=0 is 948, NTSC is 768 - nil */
-        { 35468950,
-          924, 576, 1135, 0x7f, 0x72, (BT848_IFORM_PAL_BDGHI|BT848_IFORM_XT1),
-          1135, 186, 924,
-#ifdef VIDEODAT_HACK
-	  VBI_MAXLINES*2,
-#else
-	  0x20,
-#endif
-	  255},
-
-	/* NTSC */
-	{ 28636363,
-          768, 480,  910, 0x68, 0x5d, (BT848_IFORM_NTSC|BT848_IFORM_XT0),
-          910, 128, 910, 0x1a, 144},
-#if 0
-	/* SECAM EAST */
-	{ 35468950, 
-          768, 576, 1135, 0x7f, 0xb0, (BT848_IFORM_SECAM|BT848_IFORM_XT1),
-	  944, 186, 922, 0x20, 255},
-#else
-	/* SECAM L */
-        { 35468950,
-          924, 576, 1135, 0x7f, 0xb0, (BT848_IFORM_SECAM|BT848_IFORM_XT1),
-          1135, 186, 922, 0x20, 255},
-#endif
-        /* PAL-NC */
-        { 28636363,
-          640, 576,  910, 0x68, 0x5d, (BT848_IFORM_PAL_NC|BT848_IFORM_XT0),
-          780, 130, 734, 0x1a, 144},
-	/* PAL-M */
-	{ 28636363, 
-          640, 480, 910, 0x68, 0x5d, (BT848_IFORM_PAL_M|BT848_IFORM_XT0),
-	  780, 135, 754, 0x1a, 144},
-	/* PAL-N */
-	{ 35468950, 
-          768, 576, 1135, 0x7f, 0x72, (BT848_IFORM_PAL_N|BT848_IFORM_XT1),
-	  944, 186, 922, 0x20, 144},
-	/* NTSC-Japan */
-	{ 28636363,
-          640, 480,  910, 0x68, 0x5d, (BT848_IFORM_NTSC_J|BT848_IFORM_XT0),
-	  780, 135, 754, 0x16, 144},
-};
-#define TVNORMS (sizeof(tvnorms)/sizeof(tvnorm))
-#define VBI_SPL 2044
+	int value;
+	
+	btv->hue = hue;
 
-/* RISC command to write one VBI data line */
-#define VBI_RISC BT848_RISC_WRITE|VBI_SPL|BT848_RISC_EOL|BT848_RISC_SOL
+	/* -128 to 127 */
+	value = (hue >> 8) - 128;
+        btwrite(value & 0xff, BT848_HUE);
+}
 
-static void make_vbitab(struct bttv *btv)
+static void bt848_contrast(struct bttv *btv, int cont)
 {
-	int i;
-	unsigned int *po=(unsigned int *) btv->vbi_odd;
-	unsigned int *pe=(unsigned int *) btv->vbi_even;
-  
-	if (bttv_debug > 1)
-		printk("bttv%d: vbi1: po=%08lx pe=%08lx\n",
-		       btv->nr,virt_to_bus(po), virt_to_bus(pe));
-        
-	*(po++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1); *(po++)=0;
-	for (i=0; i<VBI_MAXLINES; i++) 
-	{
-		*(po++)=cpu_to_le32(VBI_RISC);
-		*(po++)=cpu_to_le32(kvirt_to_bus((unsigned long)btv->vbibuf+i*2048));
-	}
-	*(po++)=cpu_to_le32(BT848_RISC_JUMP);
-	*(po++)=cpu_to_le32(virt_to_bus(btv->risc_jmp+4));
+	int value,hibit;
+	
+	btv->contrast = cont;
+	
+	/* 0-511 */
+	value = (cont  >> 7);
+	hibit = (value >> 6) & 4;
+        btwrite(value & 0xff, BT848_CONTRAST_LO);
+        btaor(hibit, ~4, BT848_E_CONTROL);
+        btaor(hibit, ~4, BT848_O_CONTROL);
+}
 
-	*(pe++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1); *(pe++)=0;
-	for (i=VBI_MAXLINES; i<VBI_MAXLINES*2; i++) 
-	{
-		*(pe++)=cpu_to_le32(VBI_RISC);
-		*(pe++)=cpu_to_le32(kvirt_to_bus((unsigned long)btv->vbibuf+i*2048));
-	}
-	*(pe++)=cpu_to_le32(BT848_RISC_JUMP|BT848_RISC_IRQ|(0x01<<16));
-	*(pe++)=cpu_to_le32(virt_to_bus(btv->risc_jmp+10));
+static void bt848_sat(struct bttv *btv, int color)
+{
+	int val_u,val_v,hibits;
+	
+	btv->saturation = color;
 
-	if (bttv_debug > 1)
-		printk("bttv%d: vbi2: po=%08lx pe=%08lx\n",
-		       btv->nr,virt_to_bus(po), virt_to_bus(pe));
+	/* 0-511 for the color */
+	val_u   = color >> 7;
+	val_v   = ((color>>7)*180L)/254;
+        hibits  = (val_u >> 7) & 2;
+	hibits |= (val_v >> 8) & 1;
+        btwrite(val_u & 0xff, BT848_SAT_U_LO);
+        btwrite(val_v & 0xff, BT848_SAT_V_LO);
+        btaor(hibits, ~3, BT848_E_CONTROL);
+        btaor(hibits, ~3, BT848_O_CONTROL);
 }
 
-static int fmtbppx2[16] = {
-        8, 6, 4, 4, 4, 3, 2, 2, 4, 3, 0, 0, 0, 0, 2, 0 
-};
-
-static int palette2fmt[] = {
-	0,
-	BT848_COLOR_FMT_Y8,
-	BT848_COLOR_FMT_RGB8,
-	BT848_COLOR_FMT_RGB16,
-	BT848_COLOR_FMT_RGB24,
-	BT848_COLOR_FMT_RGB32,
-	BT848_COLOR_FMT_RGB15,
-	BT848_COLOR_FMT_YUY2,
-	BT848_COLOR_FMT_YUY2,
-	-1,
-	-1,
-	-1,
-	BT848_COLOR_FMT_RAW,
-	BT848_COLOR_FMT_YCrCb422,
-	BT848_COLOR_FMT_YCrCb411,
-	BT848_COLOR_FMT_YCrCb422,
-	BT848_COLOR_FMT_YCrCb411,
-};
-#define PALETTEFMT_MAX (sizeof(palette2fmt)/sizeof(int))
+/* ----------------------------------------------------------------------- */
 
-static int make_rawrisctab(struct bttv *btv, unsigned int *ro,
-                            unsigned int *re, unsigned int *vbuf)
+static int
+video_mux(struct bttv *btv, unsigned int input)
 {
-        unsigned long line;
-	unsigned long bpl=1024;		/* bytes per line */
-	unsigned long vadr=(unsigned long) vbuf;
-
-	*(ro++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1); 
-        *(ro++)=cpu_to_le32(0);
-	*(re++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1);
-        *(re++)=cpu_to_le32(0);
-  
-        /* In PAL 650 blocks of 256 DWORDs are sampled, but only if VDELAY
-           is 2 and without separate VBI grabbing.
-           We'll have to handle this inside the IRQ handler ... */
-
-	for (line=0; line < 640; line++)
-	{
-                *(ro++)=cpu_to_le32(BT848_RISC_WRITE|bpl|BT848_RISC_SOL|BT848_RISC_EOL);
-                *(ro++)=cpu_to_le32(kvirt_to_bus(vadr));
-                *(re++)=cpu_to_le32(BT848_RISC_WRITE|bpl|BT848_RISC_SOL|BT848_RISC_EOL);
-                *(re++)=cpu_to_le32(kvirt_to_bus(vadr+gbufsize/2));
-                vadr+=bpl;
-	}
-	
-	*(ro++)=cpu_to_le32(BT848_RISC_JUMP);
-	*(ro++)=cpu_to_le32(btv->bus_vbi_even);
-	*(re++)=cpu_to_le32(BT848_RISC_JUMP|BT848_RISC_IRQ|(2<<16));
-	*(re++)=cpu_to_le32(btv->bus_vbi_odd);
-	
-	return 0;
-}
+	int mux,mask2;
 
-static int  make_prisctab(struct bttv *btv, unsigned int *ro,
-                          unsigned int *re, 
-                          unsigned int *vbuf, unsigned short width,
-                          unsigned short height, unsigned short fmt)
-{
-        unsigned long line, lmask;
-	unsigned long bl, blcr, blcb, rcmd;
-	unsigned long todo;
-	unsigned int **rp;
-	int inter;
-	unsigned long cbadr, cradr;
-	unsigned long vadr=(unsigned long) vbuf;
-	int shift, csize;	
-
-	if (bttv_debug > 1)
-		printk("bttv%d: prisc1: ro=%08lx re=%08lx\n",
-		       btv->nr,virt_to_bus(ro), virt_to_bus(re));
-
-	switch(fmt)
-	{
-        case VIDEO_PALETTE_YUV422P:
-                csize=(width*height)>>1;
-                shift=1;
-                lmask=0;
-                break;
-                
-        case VIDEO_PALETTE_YUV411P:
-                csize=(width*height)>>2;
-                shift=2;
-                lmask=0;
-                break;
-	 				
-	 case VIDEO_PALETTE_YUV420P:
-                csize=(width*height)>>2;
-                shift=1;
-                lmask=1;
-                break;
-                
-	 case VIDEO_PALETTE_YUV410P:
-                csize=(width*height)>>4;
-                shift=2;
-                lmask=3;
-                break;
-                
-        default:
-                return -1;
-	}
-	cbadr=vadr+(width*height);
-	cradr=cbadr+csize;
-	inter = (height>tvnorms[btv->win.norm].sheight/2) ? 1 : 0;
-	
-	*(ro++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM3);
-        *(ro++)=0;
-	*(re++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM3);
-        *(re++)=0;
-  
-	for (line=0; line < (height<<(1^inter)); line++)
-	{
-		if(line==height)
-		{
-			vadr+=csize<<1;
-			cbadr=vadr+(width*height);
-			cradr=cbadr+csize;
-		}
-	        if (inter) 
-		        rp= (line&1) ? &re : &ro;
-		else 
-	                rp= (line>=height) ? &ro : &re; 
-	                
-
-	        if(line&lmask)
-	        	rcmd=BT848_RISC_WRITE1S23|BT848_RISC_SOL;
-	        else
-	        	rcmd=BT848_RISC_WRITE123|BT848_RISC_SOL;
+	if (input >= bttv_tvcards[btv->type].video_inputs)
+		return -EINVAL;
 
-	        todo=width;
-		while(todo)
-		{
-                 bl=PAGE_SIZE-((PAGE_SIZE-1)&vadr);
-                 blcr=(PAGE_SIZE-((PAGE_SIZE-1)&cradr))<<shift;
-		 blcb=(PAGE_SIZE-((PAGE_SIZE-1)&cbadr))<<shift;
-		 bl=(blcr<bl) ? blcr : bl;
-		 bl=(blcb<bl) ? blcb : bl;
-		 bl=(bl>todo) ? todo : bl;
-		 blcr=bl>>shift;
-		 blcb=blcr;
-		 /* bl now containts the longest row that can be written */
-		 todo-=bl;
-		 if(!todo) rcmd|=BT848_RISC_EOL; /* if this is the last EOL */
-		 
-		 *((*rp)++)=cpu_to_le32(rcmd|bl);
-		 *((*rp)++)=cpu_to_le32(blcb|(blcr<<16));
-		 *((*rp)++)=cpu_to_le32(kvirt_to_bus(vadr));
-		 vadr+=bl;
-		 if((rcmd&(15<<28))==BT848_RISC_WRITE123)
-		 {
-		 	*((*rp)++)=cpu_to_le32(kvirt_to_bus(cbadr));
-		 	cbadr+=blcb;
-		 	*((*rp)++)=cpu_to_le32(kvirt_to_bus(cradr));
-		 	cradr+=blcr;
-		 }
-		 
-		 rcmd&=~BT848_RISC_SOL; /* only the first has SOL */
-		}
-	}
-	
-	*(ro++)=cpu_to_le32(BT848_RISC_JUMP);
-	*(ro++)=cpu_to_le32(btv->bus_vbi_even);
-	*(re++)=cpu_to_le32(BT848_RISC_JUMP|BT848_RISC_IRQ|(2<<16));
-	*(re++)=cpu_to_le32(btv->bus_vbi_odd);
-	
-	if (bttv_debug > 1)
-		printk("bttv%d: prisc2: ro=%08lx re=%08lx\n",
-		       btv->nr,virt_to_bus(ro), virt_to_bus(re));
+        /* needed by RemoteVideo MX */
+	mask2 = bttv_tvcards[btv->type].gpiomask2;
+	if (mask2)
+		btaor(mask2,~mask2,BT848_GPIO_OUT_EN);
 
-	return 0;
-}
- 
-static int  make_vrisctab(struct bttv *btv, unsigned int *ro,
-                          unsigned int *re, 
-                          unsigned int *vbuf, unsigned short width,
-                          unsigned short height, unsigned short palette)
-{
-        unsigned long line;
-	unsigned long bpl;  /* bytes per line */
-	unsigned long bl;
-	unsigned long todo;
-	unsigned int **rp;
-	int inter;
-	unsigned long vadr=(unsigned long) vbuf;
-
-        if (palette==VIDEO_PALETTE_RAW) 
-                return make_rawrisctab(btv, ro, re, vbuf);
-        if (palette>=VIDEO_PALETTE_PLANAR)
-                return make_prisctab(btv, ro, re, vbuf, width, height, palette);
-
-	if (bttv_debug > 1)
-		printk("bttv%d: vrisc1: ro=%08lx re=%08lx\n",
-		       btv->nr,virt_to_bus(ro), virt_to_bus(re));
-	
-	inter = (height>tvnorms[btv->win.norm].sheight/2) ? 1 : 0;
-	bpl=width*fmtbppx2[palette2fmt[palette]&0xf]/2;
-	
-	*(ro++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1); 
-        *(ro++)=cpu_to_le32(0);
-	*(re++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1);
-        *(re++)=cpu_to_le32(0);
-  
-	for (line=0; line < (height<<(1^inter)); line++)
-	{
-	        if (inter) 
-		        rp= (line&1) ? &re : &ro;
-		else 
-	                rp= (line>=height) ? &ro : &re; 
-
-		bl=PAGE_SIZE-((PAGE_SIZE-1)&vadr);
-		if (bpl<=bl)
-                {
-		        *((*rp)++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_SOL|
-			        BT848_RISC_EOL|bpl); 
-			*((*rp)++)=cpu_to_le32(kvirt_to_bus(vadr));
-			vadr+=bpl;
-		}
-		else
-		{
-		        todo=bpl;
-		        *((*rp)++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_SOL|bl);
-			*((*rp)++)=cpu_to_le32(kvirt_to_bus(vadr));
-			vadr+=bl;
-			todo-=bl;
-			while (todo>PAGE_SIZE)
-			{
-			        *((*rp)++)=cpu_to_le32(BT848_RISC_WRITE|PAGE_SIZE);
-				*((*rp)++)=cpu_to_le32(kvirt_to_bus(vadr));
-				vadr+=PAGE_SIZE;
-				todo-=PAGE_SIZE;
-			}
-			*((*rp)++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_EOL|todo);
-			*((*rp)++)=cpu_to_le32(kvirt_to_bus(vadr));
-			vadr+=todo;
-		}
+#if 0
+	/* This seems to get rid of some synchronization problems */
+	btand(~(3<<5), BT848_IFORM);
+	schedule_timeout(HZ/10);
+#endif
+        
+	if (input==bttv_tvcards[btv->type].svhs)  {
+		btor(BT848_CONTROL_COMP, BT848_E_CONTROL);
+		btor(BT848_CONTROL_COMP, BT848_O_CONTROL);
+	} else {
+		btand(~BT848_CONTROL_COMP, BT848_E_CONTROL);
+		btand(~BT848_CONTROL_COMP, BT848_O_CONTROL);
 	}
-	
-	*(ro++)=cpu_to_le32(BT848_RISC_JUMP);
-	*(ro++)=cpu_to_le32(btv->bus_vbi_even);
-	*(re++)=cpu_to_le32(BT848_RISC_JUMP|BT848_RISC_IRQ|(2<<16));
-	*(re++)=cpu_to_le32(btv->bus_vbi_odd);
-
-	if (bttv_debug > 1)
-		printk("bttv%d: vrisc2: ro=%08lx re=%08lx\n",
-		       btv->nr,virt_to_bus(ro), virt_to_bus(re));
-	
+	mux = bttv_tvcards[btv->type].muxsel[input] & 3;
+	btaor(mux<<5, ~(3<<5), BT848_IFORM);
+	dprintk(KERN_DEBUG "bttv%d: video mux: input=%d mux=%d\n",
+		btv->nr,input,mux);
+
+	/* card specific hook */
+	if(bttv_tvcards[btv->type].muxsel_hook)
+		bttv_tvcards[btv->type].muxsel_hook (btv, input);
 	return 0;
 }
 
-static unsigned char lmaskt[8] = 
-{ 0xff, 0xfe, 0xfc, 0xf8, 0xf0, 0xe0, 0xc0, 0x80};
-static unsigned char rmaskt[8] = 
-{ 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff};
+static char *audio_modes[] = {
+	"audio: tuner", "audio: radio", "audio: extern",
+	"audio: intern", "audio: off"
+};
 
-static void clip_draw_rectangle(unsigned char *clipmap, int x, int y, int w, int h)
+static int
+audio_mux(struct bttv *btv, int mode)
 {
-        unsigned char lmask, rmask, *p;
-        int W, l, r;
-	int i;
+	int val,mux;
+	
+	btaor(bttv_tvcards[btv->type].gpiomask,
+	      ~bttv_tvcards[btv->type].gpiomask,BT848_GPIO_OUT_EN);
 
-	if (bttv_debug > 1)
-		printk("bttv clip: %dx%d+%d+%d\n",w,h,x,y);
+	switch (mode) {
+	case AUDIO_MUTE:
+		btv->audio |= AUDIO_MUTE;
+		break;
+	case AUDIO_UNMUTE:
+		btv->audio &= ~AUDIO_MUTE;
+		break;
+	case AUDIO_TUNER:
+	case AUDIO_RADIO:
+	case AUDIO_EXTERN:
+	case AUDIO_INTERN:
+		btv->audio &= AUDIO_MUTE;
+		btv->audio |= mode;
+	}
+	dprintk("bttv%d: audio mux: mode=%d audio=%d\n",
+		btv->nr,mode,btv->audio);
+
+	mux = (btv->audio & AUDIO_MUTE) ? AUDIO_OFF : btv->audio;
+	val = bttv_tvcards[btv->type].audiomux[mux];
+	btaor(val,~bttv_tvcards[btv->type].gpiomask, BT848_GPIO_DATA);
+	if (bttv_gpio)
+		bttv_gpio_tracking(btv,audio_modes[mux]);
+	if (!in_interrupt())
+		bttv_call_i2c_clients(btv,AUDC_SET_INPUT,&(mux));
+	return 0;
+}
 
-	/* bitmap is fixed width, 128 bytes (1024 pixels represented) */
-        if (x<0)
-        {
-                w+=x;
-                x=0;
-        }
-        if (y<0)
-        {
-                h+=y;
-                y=0;
-        }
-	if (w < 0 || h < 0)	/* catch bad clips */
-		return;
-	/* out of range data should just fall through */
-        if (y+h>=625)
-                h=625-y;
-        if (x+w>=1024)
-                w=1024-x;
-
-        l=x>>3;
-        r=(x+w-1)>>3;
-        W=r-l-1;
-        lmask=lmaskt[x&7];
-        rmask=rmaskt[(x+w-1)&7];
-        p=clipmap+128*y+l;
-        
-        if (W>0) 
-        {
-                for (i=0; i<h; i++, p+=128) 
-                {
-                        *p|=lmask;
-                        memset(p+1, 0xff, W);
-                        p[W+1]|=rmask;
-                }
-        } else if (!W) {
-                for (i=0; i<h; i++, p+=128) 
-                {
-                        p[0]|=lmask;
-                        p[1]|=rmask;
-                }
-        } else {
-                for (i=0; i<h; i++, p+=128) 
-                        p[0]|=lmask&rmask;
-        }
-               
+static void
+i2c_vidiocschan(struct bttv *btv)
+{
+	struct video_channel c;
 
+	memset(&c,0,sizeof(c));
+	c.norm    = btv->tvnorm;
+	c.channel = btv->input;
+	bttv_call_i2c_clients(btv,VIDIOCSCHAN,&c);
 }
 
-static void make_clip_tab(struct bttv *btv, struct video_clip *cr, int ncr)
+static int
+set_tvnorm(struct bttv *btv, unsigned int norm)
 {
-	int i, line, x, y, bpl, width, height, inter, maxw;
-	unsigned int bpp, dx, sx, **rp, *ro, *re, flags, len;
-	unsigned long adr;
-	unsigned char *clipmap, *clipline, cbit, lastbit, outofmem;
-
-	/* take care: bpp != btv->win.bpp is allowed here */
-	bpp = fmtbppx2[btv->win.color_fmt&0xf]/2;
-	bpl=btv->win.bpl;
-	adr=btv->win.vidadr + btv->win.x * btv->win.bpp + btv->win.y * bpl;
-	inter=(btv->win.interlace&1)^1;
-	width=btv->win.width;
-	height=btv->win.height;
-	if (bttv_debug > 1)
-		printk("bttv%d: clip1: pal=%d size=%dx%d, bpl=%d bpp=%d\n",
-		       btv->nr,btv->picture.palette,width,height,bpl,bpp);
-	if(width > 1023)
-		width = 1023;		/* sanity check */
-	if(height > 625)
-		height = 625;		/* sanity check */
-	ro=btv->risc_scr_odd;
-	re=btv->risc_scr_even;
-
-	if (bttv_debug)
-		printk("bttv%d: clip: ro=%08lx re=%08lx\n",
-		       btv->nr,virt_to_bus(ro), virt_to_bus(re));
-
-	if ((clipmap=vmalloc(VIDEO_CLIPMAP_SIZE))==NULL) {
-		/* can't clip, don't generate any risc code */
-		*(ro++)=cpu_to_le32(BT848_RISC_JUMP);
-		*(ro++)=cpu_to_le32(btv->bus_vbi_even);
-		*(re++)=cpu_to_le32(BT848_RISC_JUMP);
-		*(re++)=cpu_to_le32(btv->bus_vbi_odd);
-	}
-	if (ncr < 0) {	/* bitmap was pased */
-		memcpy(clipmap, (unsigned char *)cr, VIDEO_CLIPMAP_SIZE);
-	} else {	/* convert rectangular clips to a bitmap */
-		memset(clipmap, 0, VIDEO_CLIPMAP_SIZE); /* clear map */
-		for (i=0; i<ncr; i++)
-			clip_draw_rectangle(clipmap, cr[i].x, cr[i].y,
-				cr[i].width, cr[i].height);
-	}
-	/* clip against viewing window AND screen 
-	   so we do not have to rely on the user program
-	 */
-	maxw = (bpl - btv->win.x * btv->win.bpp) / bpp;
-	clip_draw_rectangle(clipmap, (width > maxw) ? maxw : width,
-			    0, 1024, 768);
-	clip_draw_rectangle(clipmap,0,(btv->win.y+height>btv->win.sheight) ?
-			    (btv->win.sheight-btv->win.y) : height,1024,768);
-	if (btv->win.x<0)
-		clip_draw_rectangle(clipmap, 0, 0, -(btv->win.x), 768);
-	if (btv->win.y<0)
-		clip_draw_rectangle(clipmap, 0, 0, 1024, -(btv->win.y));
-	
-	*(ro++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1);
-        *(ro++)=cpu_to_le32(0);
-	*(re++)=cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1);
-        *(re++)=cpu_to_le32(0);
-	
-	/* translate bitmap to risc code */
-        for (line=outofmem=0; line < (height<<inter) && !outofmem; line++)
-        {
-		y = line>>inter;
-		rp= (line&1) ? &re : &ro;
-		clipline = clipmap + (y<<7); /* running pointers ... */
-		lastbit = *clipline & 1;
-		for(x=dx=0,sx=0; x<=width && !outofmem;) {
-			if (0 == (x&7)) {
-				/* check bytes not bits if we can ... */
-				if (lastbit) {
-					while (0xff==*clipline && x<width-8) {
-						x  += 8;
-						dx += 8;
-						clipline++;
-					}
-				} else {
-					while (0x00==*clipline && x<width-8) {
-						x  += 8;
-						dx += 8;
-						clipline++;
-					}
-				}
-			}
-			cbit = *clipline & (1<<(x&7));
-			if (x < width && !lastbit == !cbit) {
-				dx++;
-			} else {
-				/* generate the dma controller code */
-				len = dx * bpp;
-				flags = ((bpp==4) ? BT848_RISC_BYTE3 : 0);
-				flags |= ((!sx) ? BT848_RISC_SOL : 0);
-				flags |= ((sx + dx == width) ? BT848_RISC_EOL : 0);
-				if (!lastbit) {
-					*((*rp)++)=cpu_to_le32(BT848_RISC_WRITE|flags|len);
-					*((*rp)++)=cpu_to_le32(adr + bpp * sx);
-				} else {
-					*((*rp)++)=cpu_to_le32(BT848_RISC_SKIP|flags|len);
-				}
-				lastbit=cbit;
-				sx += dx;
-				dx = 1;
-				if (ro - btv->risc_scr_odd>(RISCMEM_LEN>>3) - 16)
-					outofmem++;
-				if (re - btv->risc_scr_even>(RISCMEM_LEN>>3) - 16)
-					outofmem++;
-			}
-			x++;
-			if (0 == (x&7))
-				clipline++;
-		}
-		if ((!inter)||(line&1))
-                        adr+=bpl;
-	}
-
-	vfree(clipmap);
-	/* outofmem flag relies on the following code to discard extra data */
-	*(ro++)=cpu_to_le32(BT848_RISC_JUMP);
-	*(ro++)=cpu_to_le32(btv->bus_vbi_even);
-	*(re++)=cpu_to_le32(BT848_RISC_JUMP);
-	*(re++)=cpu_to_le32(btv->bus_vbi_odd);
-
-	if (bttv_debug > 1)
-		printk("bttv%d: clip2: pal=%d size=%dx%d, bpl=%d bpp=%d\n",
-		       btv->nr,btv->picture.palette,width,height,bpl,bpp);
-}
+	const struct bttv_tvnorm *tvnorm;
 
-/*
- *	Set the registers for the size we have specified. Don't bother
- *	trying to understand this without the BT848 manual in front of
- *	you [AC]. 
- *
- *	PS: The manual is free for download in .pdf format from 
- *	www.brooktree.com - nicely done those folks.
- */
- 
-static inline void bt848_set_eogeo(struct bttv *btv, struct tvnorm *tvn,
-				   int odd, int width, int height)
-{
-        u16 vscale, hscale;
-	u32 xsf, sr;
-	u16 hdelay;
-	u8 crop, vtc;
-	int inter = (height>tvn->sheight/2) ? 0 : 1;
-        int off = odd ? 0x80 : 0x00;
-
-	xsf = (width*tvn->scaledtwidth)/tvn->swidth;
-	hscale = ((tvn->totalwidth*4096UL)/xsf-4096);
-	hdelay =  tvn->hdelayx1;
-	hdelay =  (hdelay*width)/tvn->swidth;
-	hdelay &= 0x3fe;
-	sr=((tvn->sheight>>inter)*512)/height-512;
-	vscale=(0x10000UL-sr)&0x1fff;
-	crop=((width>>8)&0x03)|((hdelay>>6)&0x0c)|
-		((tvn->sheight>>4)&0x30)|((tvn->vdelay>>2)&0xc0);
-	vscale |= inter ? (BT848_VSCALE_INT<<8) : 0;
-
-	if (combfilter) {
-		/* Some people say interpolation looks bad ... */
-		vtc = (width < 193) ? 2 : ((width < 385) ? 1 : 0);
-		if (width < 769)
-			btor(BT848_VSCALE_COMB, BT848_E_VSCALE_HI+off);
-		else
-			btand(~BT848_VSCALE_COMB, BT848_E_VSCALE_HI+off);
-	} else {
-		vtc = 0;
-		btand(~BT848_VSCALE_COMB, BT848_E_VSCALE_HI+off);
-	}
+	if (norm < 0 || norm >= BTTV_TVNORMS)
+		return -EINVAL;
 
-	btwrite(vtc, BT848_E_VTC+off);
-	btwrite(hscale>>8, BT848_E_HSCALE_HI+off);
-	btwrite(hscale&0xff, BT848_E_HSCALE_LO+off);
-	btaor((vscale>>8), 0xe0, BT848_E_VSCALE_HI+off);
-	btwrite(vscale&0xff, BT848_E_VSCALE_LO+off);
-	btwrite(width&0xff, BT848_E_HACTIVE_LO+off);
-	btwrite(hdelay&0xff, BT848_E_HDELAY_LO+off);
-	btwrite(tvn->sheight&0xff, BT848_E_VACTIVE_LO+off);
-	btwrite(tvn->vdelay&0xff, BT848_E_VDELAY_LO+off);
-	btwrite(crop, BT848_E_CROP+off);
-}
+	btv->tvnorm = norm;
+	tvnorm = &bttv_tvnorms[norm];
 
+	btwrite(tvnorm->adelay, BT848_ADELAY);
+	btwrite(tvnorm->bdelay, BT848_BDELAY);
+	btaor(tvnorm->iform,~(BT848_IFORM_NORM|BT848_IFORM_XTBOTH),
+	      BT848_IFORM);
+	btwrite(tvnorm->vbipack, BT848_VBI_PACK_SIZE);
+	btwrite(1, BT848_VBI_PACK_DEL);
+	
+	btv->pll.pll_ofreq = tvnorm->Fsc;
+	set_pll(btv);
+	return 0;
+}
 
-static void bt848_set_geo(struct bttv *btv,
-			  int no_irq_context)
+static void
+set_input(struct bttv *btv, unsigned int input)
 {
-	u16 ewidth, eheight, owidth, oheight;
-	u16 format, bswap;
-	struct tvnorm *tvn;
+	btv->input = input;
+	video_mux(btv,input);
+	audio_mux(btv,(input == bttv_tvcards[btv->type].tuner ?
+		       AUDIO_TUNER : AUDIO_EXTERN));
+	set_tvnorm(btv,btv->tvnorm);
+}
 
-	tvn=&tvnorms[btv->win.norm];
+static void init_bt848(struct bttv *btv)
+{
+	int val;
 	
-	btwrite(tvn->adelay, BT848_ADELAY);
-	btwrite(tvn->bdelay, BT848_BDELAY);
-	btaor(tvn->iform,~(BT848_IFORM_NORM|BT848_IFORM_XTBOTH), BT848_IFORM);
-	btwrite(tvn->vbipack, BT848_VBI_PACK_SIZE);
-	btwrite(1, BT848_VBI_PACK_DEL);
+	btwrite(0, BT848_SRESET);
+	btwrite(0x00, BT848_CAP_CTL);
+	btwrite(BT848_COLOR_CTL_GAMMA, BT848_COLOR_CTL);
+	btwrite(BT848_IFORM_XTAUTO | BT848_IFORM_AUTO, BT848_IFORM);
 
-        btv->pll.pll_ofreq = tvn->Fsc;
-	if (no_irq_context)
-		set_pll(btv);
-
-	btv->win.interlace = (btv->win.height>tvn->sheight/2) ? 1 : 0;
-
-	if (0 == btv->risc_cap_odd &&
-	    0 == btv->risc_cap_even) {
-		/* overlay only */
-		owidth  = btv->win.width;
-		oheight = btv->win.height;
-		ewidth  = btv->win.width;
-		eheight = btv->win.height;
-		format  = btv->win.color_fmt;
-		bswap   = btv->fb_color_ctl;
-	} else if (-1 != btv->gq_grab      &&
-		   0  == btv->risc_cap_odd &&
-		   !btv->win.interlace     &&
-		   btv->scr_on) {
-		/* odd field -> overlay, even field -> capture */
-		owidth  = btv->win.width;
-		oheight = btv->win.height;
-		ewidth  = btv->gbuf[btv->gq_grab].width;
-		eheight = btv->gbuf[btv->gq_grab].height;
-		format  = (btv->win.color_fmt & 0xf0) |
-			(btv->gbuf[btv->gq_grab].fmt & 0x0f);
-		bswap   = btv->fb_color_ctl & 0x0a;
+        /* set planar and packed mode trigger points and         */
+        /* set rising edge of inverted GPINTR pin as irq trigger */
+        btwrite(BT848_GPIO_DMA_CTL_PKTP_32|
+                BT848_GPIO_DMA_CTL_PLTP1_16|
+                BT848_GPIO_DMA_CTL_PLTP23_16|
+                BT848_GPIO_DMA_CTL_GPINTC|
+                BT848_GPIO_DMA_CTL_GPINTI, 
+                BT848_GPIO_DMA_CTL);
+
+	val = btv->opt_chroma_agc ? BT848_SCLOOP_CAGC : 0;
+        btwrite(val, BT848_E_SCLOOP);
+        btwrite(val, BT848_O_SCLOOP);
+
+        btwrite(0x20, BT848_E_VSCALE_HI);
+        btwrite(0x20, BT848_O_VSCALE_HI);
+        btwrite(BT848_ADC_RESERVED | (btv->opt_adc_crush ? BT848_ADC_CRUSH : 0),
+		BT848_ADC);
+
+	if (btv->opt_lumafilter) {
+		btwrite(0, BT848_E_CONTROL);
+		btwrite(0, BT848_O_CONTROL);
 	} else {
-		/* capture only */
-		owidth  = btv->gbuf[btv->gq_grab].width;
-		oheight = btv->gbuf[btv->gq_grab].height;
-		ewidth  = btv->gbuf[btv->gq_grab].width;
-		eheight = btv->gbuf[btv->gq_grab].height;
-		format  = btv->gbuf[btv->gq_grab].fmt;
-		bswap   = 0;
+		btwrite(BT848_CONTROL_LDEC, BT848_E_CONTROL);
+		btwrite(BT848_CONTROL_LDEC, BT848_O_CONTROL);
 	}
-
-	/* program odd + even fields */
-	bt848_set_eogeo(btv, tvn, 1, owidth, oheight);
-	bt848_set_eogeo(btv, tvn, 0, ewidth, eheight);
-
-	btwrite(format, BT848_COLOR_FMT);
-	btwrite(bswap | BT848_COLOR_CTL_GAMMA, BT848_COLOR_CTL);
 }
 
-
-static int bpp2fmt[4] = {
-        BT848_COLOR_FMT_RGB8, BT848_COLOR_FMT_RGB16,
-        BT848_COLOR_FMT_RGB24, BT848_COLOR_FMT_RGB32 
-};
-
-static void bt848_set_winsize(struct bttv *btv)
+extern void bttv_reinit_bt848(struct bttv *btv)
 {
-        unsigned short format;
+	unsigned long flags;
 
-	if (btv->picture.palette > 0 && btv->picture.palette <= VIDEO_PALETTE_YUV422) {
-		/* format set by VIDIOCSPICT */
-		format = palette2fmt[btv->picture.palette];
-	} else {
-		/* use default for the given color depth */
-		format = (btv->win.depth==15) ? BT848_COLOR_FMT_RGB15 :
-			bpp2fmt[(btv->win.bpp-1)&3];
-	}
-	btv->win.color_fmt = format;
-	if (bigendian &&
-	    format == BT848_COLOR_FMT_RGB32) {
-		btv->fb_color_ctl =
-			BT848_COLOR_CTL_WSWAP_ODD	|
-			BT848_COLOR_CTL_WSWAP_EVEN	|
-			BT848_COLOR_CTL_BSWAP_ODD	|
-			BT848_COLOR_CTL_BSWAP_EVEN;
-        } else if (bigendian &&
-		   (format == BT848_COLOR_FMT_RGB16 ||
-                    format == BT848_COLOR_FMT_RGB15)) {
-		btv->fb_color_ctl =
-			BT848_COLOR_CTL_BSWAP_ODD	|
-			BT848_COLOR_CTL_BSWAP_EVEN;
-        } else {
-		btv->fb_color_ctl = 0;
-	}
-
-	/*	RGB8 seems to be a 9x5x5 GRB color cube starting at
-	 *	color 16. Why the h... can't they even mention this in the
-	 *	data sheet?  [AC - because it's a standard format so I guess
-	 *	it never occurred to them]
-	 *	Enable dithering in this mode.
-	 */
-
-	if (format==BT848_COLOR_FMT_RGB8)
-                btand(~BT848_CAP_CTL_DITH_FRAME, BT848_CAP_CTL); 
-	else
-	        btor(BT848_CAP_CTL_DITH_FRAME, BT848_CAP_CTL);
+	if (bttv_verbose)
+		printk(KERN_INFO "bttv%d: reset, reinitialize\n",btv->nr);
+	spin_lock_irqsave(&btv->s_lock,flags);
+	btv->errors=0;
+	bttv_set_dma(btv,0,0);
+	spin_unlock_irqrestore(&btv->s_lock,flags);
 
-        bt848_set_geo(btv,1);
+	init_bt848(btv);
+        btv->pll.pll_current = -1;
+	set_input(btv,btv->input);
 }
 
-/*
- *	Grab into virtual memory.
- */
-
-static int vgrab(struct bttv *btv, struct video_mmap *mp)
+#ifdef HAVE_V4L2
+static int get_control(struct bttv *btv, struct v4l2_control *c)
 {
-	unsigned int *ro, *re;
-	unsigned int *vbuf;
-	unsigned long flags;
+	struct video_audio va;
+	int i;
 	
-	if(btv->fbuffer==NULL)
-	{
-		if(fbuffer_alloc(btv))
-			return -ENOBUFS;
+	for (i = 0; i < BTTV_CTLS; i++)
+		if (bttv_ctls[i].id == c->id)
+			break;
+	if (i == BTTV_CTLS)
+		return -EINVAL;
+	if (bttv_ctls[i].category == V4L2_CTRL_CAT_AUDIO) {
+		memset(&va,0,sizeof(va));
+		bttv_call_i2c_clients(btv, VIDIOCGAUDIO, &va);
+		if (bttv_tvcards[btv->type].audio_hook)
+			bttv_tvcards[btv->type].audio_hook(btv,&va,0);
 	}
+	switch (c->id) {
+	case V4L2_CID_BRIGHTNESS:
+		c->value = btv->bright;
+		break;
+	case V4L2_CID_HUE:
+		c->value = btv->hue;
+		break;
+	case V4L2_CID_CONTRAST:
+		c->value = btv->contrast;
+		break;
+	case V4L2_CID_SATURATION:
+		c->value = btv->saturation;
+		break;
 
-	if(mp->frame >= gbuffers || mp->frame < 0)
-		return -EINVAL;
-	if(btv->gbuf[mp->frame].stat != GBUFFER_UNUSED)
-		return -EBUSY;
-		
-	if(mp->height < 32 || mp->width < 48)
-		return -EINVAL;
-	if (mp->format >= PALETTEFMT_MAX)
-		return -EINVAL;
+	case V4L2_CID_AUDIO_MUTE:
+		c->value =  (VIDEO_AUDIO_MUTE == va.flags) ? 1 : 0;
+		break;
+	case V4L2_CID_AUDIO_VOLUME:
+		c->value = va.volume;
+		break;
+	case V4L2_CID_AUDIO_BALANCE:
+		c->value = va.balance;
+		break;
+	case V4L2_CID_AUDIO_BASS:
+		c->value = va.bass;
+		break;
+	case V4L2_CID_AUDIO_TREBLE:
+		c->value = va.treble;
+		break;
 
-	if (mp->height*mp->width*fmtbppx2[palette2fmt[mp->format]&0x0f]/2
-	    > gbufsize)
-		return -EINVAL;
-	if(-1 == palette2fmt[mp->format])
+	case V4L2_CID_PRIVATE_CHROMA_AGC:
+		c->value = btv->opt_chroma_agc;
+		break;
+	case V4L2_CID_PRIVATE_COMBFILTER:
+		c->value = btv->opt_combfilter;
+		break;
+	case V4L2_CID_PRIVATE_LUMAFILTER:
+		c->value = btv->opt_lumafilter;
+		break;
+	case V4L2_CID_PRIVATE_AUTOMUTE:
+		c->value = btv->opt_automute;
+		break;
+	case V4L2_CID_PRIVATE_AGC_CRUSH:
+		c->value = btv->opt_adc_crush;
+		break;
+	default:
 		return -EINVAL;
-
-	/*
-	 *	Ok load up the BT848
-	 */
-	 
-	vbuf=(unsigned int *)(btv->fbuffer+gbufsize*mp->frame);
-	ro=btv->gbuf[mp->frame].risc;
-	re=ro+2048;
-        make_vrisctab(btv, ro, re, vbuf, mp->width, mp->height, mp->format);
-
-	if (bttv_debug)
-		printk("bttv%d: cap vgrab: queue %d (%d:%dx%d)\n",
-		       btv->nr,mp->frame,mp->format,mp->width,mp->height);
-       	spin_lock_irqsave(&btv->s_lock, flags); 
-        btv->gbuf[mp->frame].stat    = GBUFFER_GRABBING;
-	btv->gbuf[mp->frame].fmt     = palette2fmt[mp->format];
-	btv->gbuf[mp->frame].width   = mp->width;
-	btv->gbuf[mp->frame].height  = mp->height;
-	btv->gbuf[mp->frame].ro      = virt_to_bus(ro);
-	btv->gbuf[mp->frame].re      = virt_to_bus(re);
-
-#if 1
-	if (mp->height <= tvnorms[btv->win.norm].sheight/2 &&
-	    mp->format != VIDEO_PALETTE_RAW)
-		btv->gbuf[mp->frame].ro = 0;
-#endif
-
-	if (-1 == btv->gq_grab && btv->gq_in == btv->gq_out) {
-		btv->gq_start = 1;
-		btv->risc_jmp[12]=cpu_to_le32(BT848_RISC_JUMP|(0x8<<16)|BT848_RISC_IRQ);
-        }
-	btv->gqueue[btv->gq_in++] = mp->frame;
-	btv->gq_in = btv->gq_in % MAX_GBUFFERS;
-
-	btor(3, BT848_CAP_CTL);
-	btor(3, BT848_GPIO_DMA_CTL);
-	spin_unlock_irqrestore(&btv->s_lock, flags);
+	}
 	return 0;
 }
 
-static long bttv_write(struct video_device *v, const char *buf, unsigned long count, int nonblock)
+static int set_control(struct bttv *btv, struct v4l2_control *c)
 {
-	return -EINVAL;
-}
+	struct video_audio va;
+	int i,val;
 
-static long bttv_read(struct video_device *v, char *buf, unsigned long count, int nonblock)
-{
-	struct bttv *btv= (struct bttv *)v;
-	int q,todo;
-	DECLARE_WAITQUEUE(wait, current);
+	for (i = 0; i < BTTV_CTLS; i++)
+		if (bttv_ctls[i].id == c->id)
+			break;
+	if (i == BTTV_CTLS)
+		return -EINVAL;
+	if (bttv_ctls[i].category == V4L2_CTRL_CAT_AUDIO) {
+		memset(&va,0,sizeof(va));
+		bttv_call_i2c_clients(btv, VIDIOCGAUDIO, &va);
+		if (bttv_tvcards[btv->type].audio_hook)
+			bttv_tvcards[btv->type].audio_hook(btv,&va,0);
+	}
+	switch (c->id) {
+	case V4L2_CID_BRIGHTNESS:
+		bt848_bright(btv,c->value);
+		break;
+	case V4L2_CID_HUE:
+		bt848_hue(btv,c->value);
+		break;
+	case V4L2_CID_CONTRAST:
+		bt848_contrast(btv,c->value);
+		break;
+	case V4L2_CID_SATURATION:
+		bt848_sat(btv,c->value);
+		break;
+	case V4L2_CID_AUDIO_MUTE:
+		if (c->value) {
+			va.flags |= VIDEO_AUDIO_MUTE;
+			audio_mux(btv, AUDIO_MUTE);
+		} else {
+			va.flags &= ~VIDEO_AUDIO_MUTE;
+			audio_mux(btv, AUDIO_UNMUTE);
+		}
+		break;
 
-	/* BROKEN: RETURNS VBI WHEN IT SHOULD RETURN GRABBED VIDEO FRAME */
-	todo=count;
-	while (todo && todo>(q=VBIBUF_SIZE-btv->vbip)) 
-	{
-		if(copy_to_user((void *) buf, (void *) btv->vbibuf+btv->vbip, q))
-			return -EFAULT;
-		todo-=q;
-		buf+=q;
+	case V4L2_CID_AUDIO_VOLUME:
+		va.volume = c->value;
+		break;
+	case V4L2_CID_AUDIO_BALANCE:
+		va.balance = c->value;
+		break;
+	case V4L2_CID_AUDIO_BASS:
+		va.bass = c->value;
+		break;
+	case V4L2_CID_AUDIO_TREBLE:
+		va.treble = c->value;
+		break;
 
-		add_wait_queue(&btv->vbiq, &wait);
-		current->state = TASK_INTERRUPTIBLE;
-		if (todo && q==VBIBUF_SIZE-btv->vbip) 
-		{
-			if(nonblock)
-			{
-				remove_wait_queue(&btv->vbiq, &wait);
-                                current->state = TASK_RUNNING;
-				if(count==todo)
-					return -EWOULDBLOCK;
-				return count-todo;
-			}
-			schedule();	
-			if(signal_pending(current))
-			{
-				remove_wait_queue(&btv->vbiq, &wait);
-                                current->state = TASK_RUNNING;
-
-				if(todo==count)
-					return -EINTR;
-				else
-					return count-todo;
-			}
+	case V4L2_CID_PRIVATE_CHROMA_AGC:
+		btv->opt_chroma_agc = c->value;
+		val = btv->opt_chroma_agc ? BT848_SCLOOP_CAGC : 0;
+		btwrite(val, BT848_E_SCLOOP);
+		btwrite(val, BT848_O_SCLOOP);
+		break;
+	case V4L2_CID_PRIVATE_COMBFILTER:
+		btv->opt_combfilter = c->value;
+		break;
+	case V4L2_CID_PRIVATE_LUMAFILTER:
+		btv->opt_lumafilter = c->value;
+		if (btv->opt_lumafilter) {
+			btand(~BT848_CONTROL_LDEC, BT848_E_CONTROL);
+			btand(~BT848_CONTROL_LDEC, BT848_O_CONTROL);
+		} else {
+			btor(BT848_CONTROL_LDEC, BT848_E_CONTROL);
+			btor(BT848_CONTROL_LDEC, BT848_O_CONTROL);
 		}
-		remove_wait_queue(&btv->vbiq, &wait);
-                current->state = TASK_RUNNING;
+		break;
+	case V4L2_CID_PRIVATE_AUTOMUTE:
+		btv->opt_automute = c->value;
+		break;
+	case V4L2_CID_PRIVATE_AGC_CRUSH:
+		btv->opt_adc_crush = c->value;
+		btwrite(BT848_ADC_RESERVED | (btv->opt_adc_crush ? BT848_ADC_CRUSH : 0),
+			BT848_ADC);
+		break;
+	default:
+		return -EINVAL;
 	}
-	if (todo) 
-	{
-		if(copy_to_user((void *) buf, (void *) btv->vbibuf+btv->vbip, todo))
-			return -EFAULT;
-		btv->vbip+=todo;
+	if (bttv_ctls[i].category == V4L2_CTRL_CAT_AUDIO) {
+		bttv_call_i2c_clients(btv, VIDIOCSAUDIO, &va);
+		if (bttv_tvcards[btv->type].audio_hook)
+			bttv_tvcards[btv->type].audio_hook(btv,&va,1);
 	}
-	return count;
+	return 0;
 }
+#endif /* HAVE_V4L2 */
+
+/* ----------------------------------------------------------------------- */
 
-static inline void burst(int on)
+void bttv_gpio_tracking(struct bttv *btv, char *comment)
 {
-	tvnorms[0].scaledtwidth = 1135 - (on?BURSTOFFSET-2:0);
-	tvnorms[0].hdelayx1     = 186  - (on?BURSTOFFSET  :0);
-	tvnorms[2].scaledtwidth = 1135 - (on?BURSTOFFSET-2:0);
-	tvnorms[2].hdelayx1     = 186  - (on?BURSTOFFSET  :0);
+	unsigned int outbits, data;
+	outbits = btread(BT848_GPIO_OUT_EN);
+	data    = btread(BT848_GPIO_DATA);
+	printk(KERN_DEBUG "bttv%d: gpio: en=%08x, out=%08x in=%08x [%s]\n",
+	       btv->nr,outbits,data & outbits, data & ~outbits, comment);
 }
 
-/*
- * called from irq handler on fatal errors.  Takes the grabber chip
- * offline, flag it needs a reinitialization (which can't be done
- * from irq context) and wake up all sleeping proccesses.  They would
- * block forever else.  We also need someone who actually does the
- * reinitialization from process context...
- */
-static void bt848_offline(struct bttv *btv)
+void bttv_field_count(struct bttv *btv)
 {
-	int i;
-	spin_lock(&btv->s_lock);
+	int need_count = 0;
 
-	/* cancel all outstanding grab requests */
-	btv->gq_in = 0;
-	btv->gq_out = 0;
-	btv->gq_grab = -1;
-	for (i = 0; i < gbuffers; i++)
-		if (btv->gbuf[i].stat == GBUFFER_GRABBING)
-			btv->gbuf[i].stat = GBUFFER_ERROR;
-
-	/* disable screen overlay and DMA */
-	btv->risc_cap_odd  = 0;
-	btv->risc_cap_even = 0;
-	bt848_set_risc_jmps(btv,0);
-
-	/* flag the chip needs a restart */
-	btv->needs_restart = 1;
-	spin_unlock(&btv->s_lock);
-
-	wake_up_interruptible(&btv->vbiq);
-	wake_up_interruptible(&btv->capq);
+	if (locked_btres(btv,RESOURCE_STREAMING))
+		need_count++;
+	if (btv->vbi.users)
+		need_count++;
+
+	if (need_count) {
+		/* start field counter */
+		btor(BT848_INT_VSYNC,BT848_INT_MASK);
+	} else {
+		/* stop field counter */
+		btand(~BT848_INT_VSYNC,BT848_INT_MASK);
+		btv->field_count = 0;
+	}
 }
 
-static void bt848_restart(struct bttv *btv)
+static const struct bttv_format*
+format_by_palette(int palette)
 {
- 	unsigned long irq_flags;
+	int i;
 
-	if (bttv_verbose)
-		printk("bttv%d: resetting chip\n",btv->nr);
-	btwrite(0xfffffUL, BT848_INT_STAT);
-	btand(~15, BT848_GPIO_DMA_CTL);
-	btwrite(0, BT848_SRESET);
-	btwrite(virt_to_bus(btv->risc_jmp+2),
-		BT848_RISC_STRT_ADD);
+	for (i = 0; i < BTTV_FORMATS; i++) {
+		if (-1 == bttv_formats[i].palette)
+			continue;
+		if (bttv_formats[i].palette == palette)
+			return bttv_formats+i;
+	}
+	return NULL;
+}
 
-	/* enforce pll reprogramming */
-	btv->pll.pll_current = 0;
-	set_pll(btv);
+#ifdef HAVE_V4L2
+static const struct bttv_format*
+format_by_fourcc(int fourcc)
+{
+	int i;
 
-	spin_lock_irqsave(&btv->s_lock, irq_flags);
-	btv->errors = 0;
-	btv->needs_restart = 0;
-	bt848_set_geo(btv,0);
-	bt848_set_risc_jmps(btv,-1);
-	spin_unlock_irqrestore(&btv->s_lock, irq_flags);
+	for (i = 0; i < BTTV_FORMATS; i++) {
+		if (-1 == bttv_formats[i].fourcc)
+			continue;
+		if (bttv_formats[i].fourcc == fourcc)
+			return bttv_formats+i;
+	}
+	return NULL;
 }
+#endif
 
-/*
- *	Open a bttv card. Right now the flags stuff is just playing
- */
+/* ----------------------------------------------------------------------- */
+/* misc helpers                                                            */
 
-static int bttv_open(struct video_device *dev, int flags)
+static int
+bttv_switch_overlay(struct bttv *btv, struct bttv_fh *fh,
+		    struct bttv_buffer *new)
 {
-	struct bttv *btv = (struct bttv *)dev;
-        int i,ret;
-
-	ret = -EBUSY;
-	if (bttv_debug)
-		printk("bttv%d: open called\n",btv->nr);
-
-	down(&btv->lock);
-	if (btv->user)
-		goto out_unlock;
-	
-	btv->fbuffer=(unsigned char *) rvmalloc(gbuffers*gbufsize);
-	ret = -ENOMEM;
-	if (!btv->fbuffer)
-		goto out_unlock;
-
-        btv->gq_in = 0;
-        btv->gq_out = 0;
-	btv->gq_grab = -1;
-        for (i = 0; i < gbuffers; i++)
-                btv->gbuf[i].stat = GBUFFER_UNUSED;
-
-	if (btv->needs_restart)
-		bt848_restart(btv);
-        burst(0);
-	set_pll(btv);
-        btv->user++;
-	up(&btv->lock);
-        return 0;
+	struct bttv_buffer *old;
+	unsigned long flags;
+	int retval = 0;
 
- out_unlock:
-	up(&btv->lock);
-	return ret;
+	if (new)
+		new->vb.state = STATE_DONE;
+	spin_lock_irqsave(&btv->s_lock,flags);
+	old = btv->screen;
+	btv->screen = new;
+	bttv_set_dma(btv, 0x03, 1);
+	spin_unlock_irqrestore(&btv->s_lock,flags);
+	if (NULL == new)
+		free_btres(btv,fh,RESOURCE_OVERLAY);
+	if (NULL != old)
+		bttv_dma_free(btv, old);
+	return retval;
 }
 
-static void bttv_close(struct video_device *dev)
+static void
+bttv_stop_streaming(struct bttv *btv, struct bttv_fh *fh)
 {
-	struct bttv *btv=(struct bttv *)dev;
- 	unsigned long irq_flags;
-	int need_wait;
+	unsigned long flags;
+	int i;
 
-	down(&btv->lock);
-	btv->user--;
-	spin_lock_irqsave(&btv->s_lock, irq_flags);
-	need_wait = (-1 != btv->gq_grab);
-	btv->gq_start = 0;
-	btv->gq_in = 0;
-	btv->gq_out = 0;
-	btv->gq_grab = -1;
-	btv->scr_on = 0;
-	btv->risc_cap_odd = 0;
-	btv->risc_cap_even = 0;
-	bt848_set_risc_jmps(btv,-1);
-	spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-
-	/*
-	 *	A word of warning. At this point the chip
-	 *	is still capturing because its FIFO hasn't emptied
-	 *	and the DMA control operations are posted PCI 
-	 *	operations.
-	 */
-
-	btread(BT848_I2C); 	/* This fixes the PCI posting delay */
-	
-	if (need_wait) {
-		/*
-		 *	This is sucky but right now I can't find a good way to
-		 *	be sure its safe to free the buffer. We wait 5-6 fields
-		 *	which is more than sufficient to be sure.
-		 */
-		current->state = TASK_UNINTERRUPTIBLE;
-		schedule_timeout(HZ/10);	/* Wait 1/10th of a second */
-	}
-	
-	/*
-	 *	We have allowed it to drain.
-	 */
-
-	if(btv->fbuffer)
-		rvfree((void *) btv->fbuffer, gbuffers*gbufsize);
-	btv->fbuffer=0;
-	up(&btv->lock);
+	/* remove queued buffers from list */
+	spin_lock_irqsave(&btv->s_lock,flags);
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == fh->bufs[i])
+			continue;
+		if (fh->bufs[i]->vb.state == STATE_QUEUED) {
+			list_del(&fh->bufs[i]->vb.queue);
+			fh->bufs[i]->vb.state = STATE_ERROR;
+		}
+	}
+	spin_unlock_irqrestore(&btv->s_lock,flags);
+
+	/* free all buffers + clear queue */
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == fh->bufs[i])
+			continue;
+		bttv_dma_free(fh->btv,fh->bufs[i]);
+	}
+	INIT_LIST_HEAD(&fh->stream);
+	free_btres(btv,fh,RESOURCE_STREAMING);
+	bttv_field_count(btv);
 }
 
+/* ----------------------------------------------------------------------- */
+/* video4linux (1) interface                                               */
 
-/***********************************/
-/* ioctls and supporting functions */
-/***********************************/
-
-extern inline void bt848_bright(struct bttv *btv, uint bright)
+static int bttv_prepare_buffer(struct bttv *btv, struct bttv_buffer *buf,
+ 			       const struct bttv_format *fmt,
+			       int width, int height, int field)
 {
-	btwrite(bright&0xff, BT848_BRIGHT);
+	int redo_dma_risc = 0;
+	int rc;
+	
+	/* check settings */
+	if (NULL == fmt)
+		return -EINVAL;
+	if (fmt->btformat == BT848_COLOR_FMT_RAW) {
+		width  = RAW_BPL;
+		height = RAW_LINES*2;
+		if (width*height > buf->vb.bsize)
+			return -EINVAL;
+		buf->vb.size = buf->vb.bsize;
+	} else {
+		if (width  < 48 ||
+		    height < 32 ||
+		    width  > bttv_tvnorms[btv->tvnorm].swidth ||
+		    height > bttv_tvnorms[btv->tvnorm].sheight)
+			return -EINVAL;
+		buf->vb.size = (width * height * fmt->depth) >> 3;
+		if (0 != buf->vb.baddr  &&  buf->vb.bsize < buf->vb.size)
+			return -EINVAL;
+	}
+
+	/* alloc + fill struct bttv_buffer (if changed) */
+	if (buf->vb.width != width || buf->vb.height != height ||
+	    buf->tvnorm != btv->tvnorm || buf->fmt != fmt) {
+		buf->vb.width  = width;
+		buf->vb.height = height;
+		buf->tvnorm    = btv->tvnorm;
+		buf->fmt       = fmt;
+		redo_dma_risc = 1;
+	}
+
+	if (STATE_NEEDS_INIT == buf->vb.state) {
+		field = bttv_buffer_field(btv, field, VBUF_FIELD_EVEN,
+					  btv->tvnorm, height);
+		if (field != buf->vb.field)
+			redo_dma_risc = 1;
+		if (redo_dma_risc)
+			bttv_dma_free(btv,buf);
+	}
+
+	/* alloc risc memory */
+	if (STATE_NEEDS_INIT == buf->vb.state) {
+		redo_dma_risc = 1;
+		if (0 != (rc = videobuf_iolock(btv->dev,&buf->vb)))
+			goto fail;
+	}
+
+	if (redo_dma_risc)
+		if (0 != (rc = bttv_buffer_risc(btv,buf)))
+			goto fail;
+
+	buf->vb.state = STATE_PREPARED;
+	return 0;
+
+ fail:
+	bttv_dma_free(btv,buf);
+	return rc;
 }
 
-extern inline void bt848_hue(struct bttv *btv, uint hue)
+static void
+bttv_queue_buffer(struct bttv *btv, struct bttv_buffer *buf)
 {
-	btwrite(hue&0xff, BT848_HUE);
-}
+	unsigned long flags;
+	
+	buf->vb.state = STATE_QUEUED;
+	spin_lock_irqsave(&btv->s_lock,flags);
+	list_add_tail(&buf->vb.queue,&btv->capture);
+	bttv_set_dma(btv, 0x03, 1);
+	spin_unlock_irqrestore(&btv->s_lock,flags);
+}
+
+static const char *v4l1_ioctls[] = {
+	"?", "CGAP", "GCHAN", "SCHAN", "GTUNER", "STUNER", "GPICT", "SPICT",
+	"CCAPTURE", "GWIN", "SWIN", "GFBUF", "SFBUF", "KEY", "GFREQ",
+	"SFREQ", "GAUDIO", "SAUDIO", "SYNC", "MCAPTURE", "GMBUF", "GUNIT",
+	"GCAPTURE", "SCAPTURE", "SPLAYMODE", "SWRITEMODE", "GPLAYINFO",
+	"SMICROCODE", "GVBIFMT", "SVBIFMT" };
+#define V4L1_IOCTLS (sizeof(v4l1_ioctls)/sizeof(char*))
+
+static const char *v4l2_ioctls[] = {
+	"QUERYCAP", "1", "ENUM_PIXFMT", "ENUM_FBUFFMT", "G_FMT", "S_FMT",
+	"G_COMP", "S_COMP", "REQBUFS", "QUERYBUF", "G_FBUF", "S_FBUF",
+	"G_WIN", "S_WIN", "PREVIEW", "QBUF", "16", "DQBUF", "STREAMON",
+	"STREAMOFF", "G_PERF", "G_PARM", "S_PARM", "G_STD", "S_STD",
+	"ENUMSTD", "ENUMINPUT", "G_CTRL", "S_CTRL", "G_TUNER", "S_TUNER",
+	"G_FREQ", "S_FREQ", "G_AUDIO", "S_AUDIO", "35", "QUERYCTRL",
+	"QUERYMENU", "G_INPUT", "S_INPUT", "ENUMCVT", "41", "42", "43",
+	"44", "45",  "G_OUTPUT", "S_OUTPUT", "ENUMOUTPUT", "G_AUDOUT",
+	"S_AUDOUT", "ENUMFX", "G_EFFECT", "S_EFFECT", "G_MODULATOR",
+	"S_MODULATOR"
+};
+#define V4L2_IOCTLS (sizeof(v4l2_ioctls)/sizeof(char*))
 
-extern inline void bt848_contrast(struct bttv *btv, uint cont)
+int bttv_common_ioctls(struct bttv *btv, unsigned int cmd, void *arg)
 {
-	unsigned int conthi;
+	switch (cmd) {
+        case BTTV_VERSION:
+                return BTTV_VERSION_CODE;
 
-	conthi=(cont>>6)&4;
-	btwrite(cont&0xff, BT848_CONTRAST_LO);
-	btaor(conthi, ~4, BT848_E_CONTROL);
-	btaor(conthi, ~4, BT848_O_CONTROL);
-}
+	/* ***  v4l1  *** ************************************************ */
+	case VIDIOCGFREQ:
+#ifdef HAVE_V4L2
+	case VIDIOC_G_FREQ:
+#endif
+	{
+		unsigned long *freq = arg;
+		*freq = btv->freq;
+		return 0;
+	}
+	case VIDIOCSFREQ:
+#ifdef HAVE_V4L2
+	case VIDIOC_S_FREQ:
+#endif
+	{
+		unsigned long *freq = arg;
+		down(&btv->lock);
+		btv->freq=*freq;
+		bttv_call_i2c_clients(btv,VIDIOCSFREQ,freq);
+		if (btv->has_matchbox && btv->radio_user)
+			tea5757_set_freq(btv,*freq);
+		up(&btv->lock);
+		return 0;
+	}
 
-extern inline void bt848_sat_u(struct bttv *btv, unsigned long data)
-{
-	u32 datahi;
+	case VIDIOCGTUNER:
+	{
+		struct video_tuner *v = arg;
+		
+		if (v->tuner) /* Only tuner 0 */
+			return -EINVAL;
+		strcpy(v->name, "Television");
+		v->rangelow  = 0;
+		v->rangehigh = 0x7FFFFFFF;
+		v->flags     = VIDEO_TUNER_PAL|VIDEO_TUNER_NTSC|VIDEO_TUNER_SECAM;
+		v->mode      = btv->tvnorm;
+		v->signal    = (btread(BT848_DSTATUS)&BT848_DSTATUS_HLOC) ? 0xFFFF : 0;
+		bttv_call_i2c_clients(btv,cmd,v);
+		return 0;
+	}
+	case VIDIOCSTUNER:
+	{
+		struct video_tuner *v = arg;
 
-	datahi=(data>>7)&2;
-	btwrite(data&0xff, BT848_SAT_U_LO);
-	btaor(datahi, ~2, BT848_E_CONTROL);
-	btaor(datahi, ~2, BT848_O_CONTROL);
-}
+		if (v->tuner) /* Only tuner 0 */
+			return -EINVAL;
+		if (v->mode >= BTTV_TVNORMS)
+			return -EINVAL;
 
-static inline void bt848_sat_v(struct bttv *btv, unsigned long data)
-{
-	u32 datahi;
+		down(&btv->lock);
+		set_tvnorm(btv,v->mode);
+		bttv_call_i2c_clients(btv,cmd,v);
+		up(&btv->lock);
+		return 0;
+	}
+	
+        case VIDIOCGCHAN:
+        {
+                struct video_channel *v = arg;
 
-	datahi=(data>>8)&1;
-	btwrite(data&0xff, BT848_SAT_V_LO);
-	btaor(datahi, ~1, BT848_E_CONTROL);
-	btaor(datahi, ~1, BT848_O_CONTROL);
-}
+                if (v->channel >= bttv_tvcards[btv->type].video_inputs)
+                        return -EINVAL;
+                v->tuners=0;
+                v->flags = VIDEO_VC_AUDIO;
+                v->type = VIDEO_TYPE_CAMERA;
+                v->norm = btv->tvnorm;
+                if(v->channel == bttv_tvcards[btv->type].tuner)  {
+                        strcpy(v->name,"Television");
+                        v->flags|=VIDEO_VC_TUNER;
+                        v->type=VIDEO_TYPE_TV;
+                        v->tuners=1;
+                } else if (v->channel == bttv_tvcards[btv->type].svhs) {
+                        strcpy(v->name,"S-Video");
+                } else {
+                        sprintf(v->name,"Composite%d",v->channel);
+		}
+		return 0;
+        }
+        case VIDIOCSCHAN:
+        {
+                struct video_channel *v = arg;
 
-/*
- *	ioctl routine
- */
- 
+		if (v->channel <  0 ||
+		    v->channel >= bttv_tvcards[btv->type].video_inputs)
+			return -EINVAL;
+		if (v->norm >= BTTV_TVNORMS)
+			return -EINVAL;
 
-static int bttv_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
-{
-	struct bttv *btv=(struct bttv *)dev;
- 	unsigned long irq_flags;
- 	int i,ret = 0;
+		down(&btv->lock);
+		if (v->channel == btv->input &&
+		    v->norm    == btv->tvnorm) {
+			/* nothing to do */
+			up(&btv->lock);
+			return 0;
+		}
 
-	if (bttv_debug > 1)
-		printk("bttv%d: ioctl 0x%x\n",btv->nr,cmd);
+		btv->tvnorm = v->norm;
+		set_input(btv,v->channel);
+		up(&btv->lock);
+		return 0;
+	}
 
-	switch (cmd) {
-	case VIDIOCGCAP:
+        case VIDIOCGAUDIO:
 	{
-		struct video_capability b;
-		strcpy(b.name,btv->video_dev.name);
-		b.type = VID_TYPE_CAPTURE|
-			((bttv_tvcards[btv->type].tuner != -1) ? VID_TYPE_TUNER : 0) |
-			VID_TYPE_OVERLAY|
-			VID_TYPE_CLIPPING|
-			VID_TYPE_FRAMERAM|
-			VID_TYPE_SCALES;
-		b.channels = bttv_tvcards[btv->type].video_inputs;
-		b.audios = bttv_tvcards[btv->type].audio_inputs;
-		b.maxwidth = tvnorms[btv->win.norm].swidth;
-		b.maxheight = tvnorms[btv->win.norm].sheight;
-		b.minwidth = 48;
-		b.minheight = 32;
-		if(copy_to_user(arg,&b,sizeof(b)))
-			return -EFAULT;
+		struct video_audio *v = arg;
+
+		memset(v,0,sizeof(*v));
+		strcpy(v->name,"Television");
+		v->flags |= VIDEO_AUDIO_MUTABLE;
+		v->mode  = VIDEO_SOUND_MONO;
+
+		down(&btv->lock);
+		bttv_call_i2c_clients(btv,cmd,v);
+
+		/* card specific hooks */
+		if (bttv_tvcards[btv->type].audio_hook)
+			bttv_tvcards[btv->type].audio_hook(btv,v,0);
+
+		up(&btv->lock);
 		return 0;
 	}
-	case VIDIOCGCHAN:
+	case VIDIOCSAUDIO:
 	{
-		struct video_channel v;
-		if(copy_from_user(&v, arg,sizeof(v)))
-			return -EFAULT;
-		v.flags=VIDEO_VC_AUDIO;
-		v.tuners=0;
-		v.type=VIDEO_TYPE_CAMERA;
-		v.norm = btv->win.norm;
-		if (v.channel>=bttv_tvcards[btv->type].video_inputs)
+		struct video_audio *v = arg;
+
+		if(v->audio <  0 ||
+		   v->audio >= bttv_tvcards[btv->type].audio_inputs)
 			return -EINVAL;
-		if(v.channel==bttv_tvcards[btv->type].tuner) 
-		{
-			strcpy(v.name,"Television");
-			v.flags|=VIDEO_VC_TUNER;
-			v.type=VIDEO_TYPE_TV;
-			v.tuners=1;
-		} 
-		else if(v.channel==bttv_tvcards[btv->type].svhs) 
-			strcpy(v.name,"S-Video");
-		else
-			sprintf(v.name,"Composite%d",v.channel);
+
+		down(&btv->lock);
+		audio_mux(btv, (v->flags&VIDEO_AUDIO_MUTE) ? AUDIO_MUTE : AUDIO_UNMUTE);
+		bttv_call_i2c_clients(btv,cmd,v);
+
+		/* card specific hooks */
+		if (bttv_tvcards[btv->type].audio_hook)
+			bttv_tvcards[btv->type].audio_hook(btv,v,1);
 		
-		if(copy_to_user(arg,&v,sizeof(v)))
-			return -EFAULT;
+		up(&btv->lock);
 		return 0;
 	}
-	/*
-	 *	Each channel has 1 tuner
-	 */
-	case VIDIOCSCHAN:
+
+#ifdef HAVE_V4L2
+	/* ***  v4l2  *** ************************************************ */
+	case VIDIOC_ENUMSTD:
 	{
-		struct video_channel v;
-		if(copy_from_user(&v, arg,sizeof(v)))
-			return -EFAULT;
-		
-		if (v.channel>bttv_tvcards[btv->type].video_inputs)
-			return -EINVAL;
-		if (v.norm > (sizeof(tvnorms)/sizeof(*tvnorms)))
-			return -EOPNOTSUPP;
+		struct v4l2_enumstd *e = arg;
 
-		bttv_call_i2c_clients(btv,cmd,&v);
-		down(&btv->lock);
-		bt848_muxsel(btv, v.channel);
-		btv->channel=v.channel;
-		if (btv->win.norm != v.norm) {
-			btv->win.norm = v.norm;
-			make_vbitab(btv);
-			spin_lock_irqsave(&btv->s_lock, irq_flags);
-			bt848_set_winsize(btv);
-			spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-		}
-		up(&btv->lock);
+		if (e->index < 0 || e->index >= BTTV_TVNORMS)
+			return -EINVAL;
+		v4l2_video_std_construct(&e->std, bttv_tvnorms[e->index].v4l2_id, 0);
+		e->inputs  = 0x0f;
+		e->outputs = 0x00;
 		return 0;
 	}
-	case VIDIOCGTUNER:
+	case VIDIOC_G_STD:
 	{
-		struct video_tuner v;
-		if(copy_from_user(&v,arg,sizeof(v))!=0)
-			return -EFAULT;
-#if 0 /* tuner.signal might be of intrest for non-tuner sources too ... */
-		if(v.tuner||btv->channel)	/* Only tuner 0 */
+		struct v4l2_standard *s = arg;
+		v4l2_video_std_construct(s,bttv_tvnorms[btv->tvnorm].v4l2_id,0);
+		return 0;
+	}
+	case VIDIOC_S_STD:
+	{
+		struct v4l2_standard *s = arg;
+		int i, id = v4l2_video_std_confirm(s);
+
+		for(i = 0; i < BTTV_TVNORMS; i++)
+			if (id == bttv_tvnorms[i].v4l2_id)
+				break;
+		if (i == BTTV_TVNORMS)
 			return -EINVAL;
-#endif
-		strcpy(v.name, "Television");
-		v.rangelow=0;
-		v.rangehigh=0xFFFFFFFF;
-		v.flags=VIDEO_TUNER_PAL|VIDEO_TUNER_NTSC|VIDEO_TUNER_SECAM;
-		v.mode = btv->win.norm;
-		v.signal = (btread(BT848_DSTATUS)&BT848_DSTATUS_HLOC) ? 0xFFFF : 0;
-		bttv_call_i2c_clients(btv,cmd,&v);
-		if(copy_to_user(arg,&v,sizeof(v)))
-			return -EFAULT;
+
+		down(&btv->lock);
+		set_tvnorm(btv,i);
+		i2c_vidiocschan(btv);
+		up(&btv->lock);
 		return 0;
 	}
-	/* We have but one tuner */
-	case VIDIOCSTUNER:
+
+	case VIDIOC_ENUMINPUT:
 	{
-		struct video_tuner v;
-		if(copy_from_user(&v, arg, sizeof(v)))
-			return -EFAULT;
-		/* Only one channel has a tuner */
-		if(v.tuner!=bttv_tvcards[btv->type].tuner)
+		struct v4l2_input *i = arg;
+
+		if (i->index >= bttv_tvcards[btv->type].video_inputs)
 			return -EINVAL;
- 				
-		if(v.mode!=VIDEO_MODE_PAL&&v.mode!=VIDEO_MODE_NTSC
-		   &&v.mode!=VIDEO_MODE_SECAM)
-			return -EOPNOTSUPP;
-		bttv_call_i2c_clients(btv,cmd,&v);
-		if (btv->win.norm != v.mode) {
-			btv->win.norm = v.mode;
-                        down(&btv->lock);
-			set_pll(btv);
-			make_vbitab(btv);
-			spin_lock_irqsave(&btv->s_lock, irq_flags);
-			bt848_set_winsize(btv);
-			spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-			up(&btv->lock);
+		i->type = V4L2_INPUT_TYPE_CAMERA;
+		i->capability = 0;
+		i->assoc_audio = 0;
+		if (i->index == bttv_tvcards[btv->type].tuner) {
+			sprintf(i->name, "Television");
+			i->type = V4L2_INPUT_TYPE_TUNER;
+			i->capability = V4L2_INPUT_CAP_AUDIO;
+		} else if (i->index==bttv_tvcards[btv->type].svhs) {
+			sprintf(i->name, "S-Video");
+		} else {
+                        sprintf(i->name,"Composite%d",i->index);
 		}
 		return 0;
 	}
-	case VIDIOCGPICT:
+	case VIDIOC_G_INPUT:
 	{
-		struct video_picture p=btv->picture;
-		if(copy_to_user(arg, &p, sizeof(p)))
-			return -EFAULT;
+		int *i = arg;
+		*i = btv->input;
 		return 0;
 	}
-	case VIDIOCSPICT:
+	case VIDIOC_S_INPUT:
 	{
-		struct video_picture p;
-		if(copy_from_user(&p, arg,sizeof(p)))
-			return -EFAULT;
-		if (p.palette > PALETTEFMT_MAX)
+		int *i = arg;
+		
+		if (*i < 0 || *i > bttv_tvcards[btv->type].video_inputs)
 			return -EINVAL;
 		down(&btv->lock);
-		/* We want -128 to 127 we get 0-65535 */
-		bt848_bright(btv, (p.brightness>>8)-128);
-		/* 0-511 for the colour */
-		bt848_sat_u(btv, p.colour>>7);
-		bt848_sat_v(btv, ((p.colour>>7)*201L)/237);
-		/* -128 to 127 */
-		bt848_hue(btv, (p.hue>>8)-128);
-		/* 0-511 */
-		bt848_contrast(btv, p.contrast>>7);
-		btv->picture = p;
+		set_input(btv,*i);
+		i2c_vidiocschan(btv);
 		up(&btv->lock);
 		return 0;
 	}
-	case VIDIOCSWIN:
-	{
-		struct video_window vw;
-		struct video_clip *vcp = NULL;
-			
-		if(copy_from_user(&vw,arg,sizeof(vw)))
-			return -EFAULT;
+	
+	case VIDIOC_G_TUNER: {
+		struct v4l2_tuner *t = arg;
 
 		down(&btv->lock);
-		if(vw.flags || vw.width < 16 || vw.height < 16) 
+		memset(t,0,sizeof(*t));
+		t->input = bttv_tvcards[btv->type].tuner;
+		strcpy(t->name, "Television");
+		v4l2_video_std_construct(&t->std, bttv_tvnorms[btv->tvnorm].v4l2_id, 0);
+		t->capability = V4L2_TUNER_CAP_NORM;
+		t->rangehigh = 0xffffffffUL;
+		t->rxsubchans = V4L2_TUNER_SUB_MONO;
+		if (btread(BT848_DSTATUS)&BT848_DSTATUS_HLOC)
+			t->signal = 0xffff;
 		{
-			spin_lock_irqsave(&btv->s_lock, irq_flags);
-			btv->scr_on = 0;
-			bt848_set_risc_jmps(btv,-1);
-			spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-			up(&btv->lock);
-			return -EINVAL;
+			/* Hmmm ... */
+			struct video_audio va;
+			memset(&va, 0, sizeof(struct video_audio));
+			bttv_call_i2c_clients(btv, VIDIOCGAUDIO, &va);
+			if (bttv_tvcards[btv->type].audio_hook)
+				bttv_tvcards[btv->type].audio_hook(btv,&va,0);
+			if(va.mode & VIDEO_SOUND_STEREO)
+				t->rxsubchans |= V4L2_TUNER_SUB_STEREO;
+			if(va.mode & VIDEO_SOUND_LANG1)
+				t->rxsubchans |= V4L2_TUNER_SUB_LANG1;
+			if(va.mode & VIDEO_SOUND_LANG2)
+				t->rxsubchans |= V4L2_TUNER_SUB_LANG2;
 		}
-		if (btv->win.bpp < 4) 
-		{	/* adjust and align writes */
-			vw.x = (vw.x + 3) & ~3;
-			vw.width &= ~3;
-		}
-		if (btv->needs_restart)
-			bt848_restart(btv);
-		btv->win.x=vw.x;
-		btv->win.y=vw.y;
-		btv->win.width=vw.width;
-		btv->win.height=vw.height;
+		/* FIXME: fill capability+audmode */
+		up(&btv->lock);
+		return 0;
+	}
+	case VIDIOC_S_TUNER: {
+		struct v4l2_tuner *t = arg;
 		
-		spin_lock_irqsave(&btv->s_lock, irq_flags);
-		bt848_set_risc_jmps(btv,0);
-		bt848_set_winsize(btv);
-		spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-
-		/*
-		 *	Do any clips.
-		 */
-		if(vw.clipcount<0) {
-			if((vcp=vmalloc(VIDEO_CLIPMAP_SIZE))==NULL) {
-				up(&btv->lock);
-				return -ENOMEM;
-			}
-			if(copy_from_user(vcp, vw.clips,
-					  VIDEO_CLIPMAP_SIZE)) {
-				up(&btv->lock);
-				vfree(vcp);
-				return -EFAULT;
-			}
-		} else if (vw.clipcount > 2048) {
-			up(&btv->lock);
+		if(t->input!=bttv_tvcards[btv->type].tuner)
 			return -EINVAL;
-		} else if (vw.clipcount) {
-			if((vcp=vmalloc(sizeof(struct video_clip)*
-					(vw.clipcount))) == NULL) {
-				up(&btv->lock);
-				return -ENOMEM;
-			}
-			if(copy_from_user(vcp,vw.clips,
-					  sizeof(struct video_clip)*
-					  vw.clipcount)) {
-				up(&btv->lock);
-				vfree(vcp);
-				return -EFAULT;
-			}
+		down(&btv->lock);
+		{
+			struct video_audio va;
+			memset(&va, 0, sizeof(struct video_audio));
+			if (t->audmode == V4L2_TUNER_MODE_MONO)
+				va.mode = VIDEO_SOUND_MONO;
+			else if (t->audmode == V4L2_TUNER_MODE_STEREO)
+				va.mode = VIDEO_SOUND_STEREO;
+			else if (t->audmode == V4L2_TUNER_MODE_LANG1)
+				va.mode = VIDEO_SOUND_LANG1;
+			else if (t->audmode == V4L2_TUNER_MODE_LANG2)
+				va.mode = VIDEO_SOUND_LANG2;
+			bttv_call_i2c_clients(btv, VIDIOCSAUDIO, &va);
+			if (bttv_tvcards[btv->type].audio_hook)
+				bttv_tvcards[btv->type].audio_hook(btv,&va,1);
 		}
-		make_clip_tab(btv, vcp, vw.clipcount);
-		if (vw.clipcount != 0)
-			vfree(vcp);
-		spin_lock_irqsave(&btv->s_lock, irq_flags);
-		bt848_set_risc_jmps(btv,-1);
-		spin_unlock_irqrestore(&btv->s_lock, irq_flags);
 		up(&btv->lock);
 		return 0;
 	}
-	case VIDIOCGWIN:
-	{
-		struct video_window vw;
-		memset(&vw,0,sizeof(vw));
-		vw.x=btv->win.x;
-		vw.y=btv->win.y;
-		vw.width=btv->win.width;
-		vw.height=btv->win.height;
-		if(btv->win.interlace)
-			vw.flags|=VIDEO_WINDOW_INTERLACE;
-		if(copy_to_user(arg,&vw,sizeof(vw)))
+#endif /* HAVE_V4L2 */
+
+	default:
+		return -ENOIOCTLCMD;
+	
+	}
+	return 0;
+}
+
+static int setup_window(struct bttv_fh *fh, struct bttv *btv,
+			int x, int y, int width, int height,
+			struct video_clip *user_clips, int nclips)
+{
+	struct video_clip *clips = NULL;
+	int n,size,retval = 0;
+	
+	if (width  < 48 ||
+	    height < 32 ||
+	    width  > bttv_tvnorms[btv->tvnorm].swidth ||
+	    height > bttv_tvnorms[btv->tvnorm].sheight ||
+	    NULL == fh->ovfmt)
+		return -EINVAL;
+	if (nclips > 2048)
+		return -EINVAL;
+
+	/* copy clips  --  luckily v4l1 + v4l2 are binary
+	   compatible here ...*/
+	n = nclips;
+	size = sizeof(struct video_clip)*(n+4);
+	clips = kmalloc(size,GFP_KERNEL);
+	if (NULL == clips)
+		return -ENOMEM;
+	if (n > 0) {
+		if (copy_from_user(clips,user_clips,
+				   sizeof(struct video_clip)*nclips)) {
+			kfree(clips);
 			return -EFAULT;
+		}
+	}
+	/* clip against screen */
+	if (NULL != btv->fbuf.base)
+		n = bttv_screen_clips(&btv->fbuf, x, y,
+				      width, height,
+				      clips, n);
+	bttv_sort_clips(clips,nclips);
+	
+	down(&fh->lock);
+	if (fh->ov.clips)
+		kfree(fh->ov.clips);
+	fh->ov.clips   = clips;
+	fh->ov.nclips  = nclips;
+	
+	fh->ov.x       = x;
+	fh->ov.y       = y;
+	fh->ov.width   = width;
+	fh->ov.height  = height;
+	btv->init.ov.width   = width;
+	btv->init.ov.height  = height;
+	
+	/* update overlay if needed */
+	retval = 0;
+	if (check_btres(fh, RESOURCE_OVERLAY)) {
+		struct bttv_buffer *new;
+		
+		new = videobuf_alloc(sizeof(*new),V4L2_BUF_TYPE_CAPTURE);
+		bttv_overlay_risc(btv, &fh->ov, fh->ovfmt, new);
+		retval = bttv_switch_overlay(btv,fh,new);
+	}
+	up(&fh->lock);
+	return retval;
+}
+
+static void release_buffer(struct file *file, struct videobuf_buffer *vb)
+{
+	struct bttv_buffer *buf = (struct bttv_buffer*)vb;
+	struct bttv_fh *fh = file->private_data;
+
+	bttv_dma_free(fh->btv,buf);
+}
+
+static int bttv_ioctl(struct inode *inode, struct file *file,
+		      unsigned int cmd, void *arg)
+{
+	struct bttv_fh *fh  = file->private_data;
+	struct bttv    *btv = fh->btv;
+	int retval;
+
+	if (bttv_debug > 1) {
+		switch (_IOC_TYPE(cmd)) {
+		case 'v':
+			printk("bttv%d: ioctl 0x%x (v4l1, VIDIOC%s)\n",
+			       btv->nr, cmd, (_IOC_NR(cmd) < V4L1_IOCTLS) ?
+			       v4l1_ioctls[_IOC_NR(cmd)] : "???");
+			break;
+		case 'V':
+			printk("bttv%d: ioctl 0x%x (v4l2, VIDIOC_%s)\n",
+			       btv->nr, cmd,  (_IOC_NR(cmd) < V4L2_IOCTLS) ?
+			       v4l2_ioctls[_IOC_NR(cmd)] : "???");
+			break;
+		default:
+			printk("bttv%d: ioctl 0x%x (???)\n",
+			       btv->nr, cmd);
+		}
+	}
+	if (btv->errors)
+		bttv_reinit_bt848(btv);
+
+	switch (cmd) {
+
+	/* ***  v4l1  *** ************************************************ */
+	case VIDIOCGCAP:
+	{
+                struct video_capability *cap = arg;
+
+		memset(cap,0,sizeof(*cap));
+                strcpy(cap->name,btv->video_dev.name);
+                cap->type = VID_TYPE_CAPTURE|
+			VID_TYPE_TUNER|
+			VID_TYPE_OVERLAY|
+			VID_TYPE_CLIPPING|
+                        VID_TYPE_SCALES;
+                cap->channels  = bttv_tvcards[btv->type].video_inputs;
+                cap->audios    = bttv_tvcards[btv->type].audio_inputs;
+                cap->maxwidth  = bttv_tvnorms[btv->tvnorm].swidth;
+                cap->maxheight = bttv_tvnorms[btv->tvnorm].sheight;
+                cap->minwidth  = 48;
+                cap->minheight = 32;
+                return 0;
+	}
+
+	case VIDIOCGPICT:
+	{
+		struct video_picture *pic = arg;
+
+		memset(pic,0,sizeof(*pic));
+		pic->brightness = btv->bright;
+		pic->contrast   = btv->contrast;
+		pic->hue        = btv->hue;
+		pic->colour     = btv->saturation;
+		if (fh->buf.fmt) {
+			pic->depth   = fh->buf.fmt->depth;
+			pic->palette = fh->buf.fmt->palette;
+		}
 		return 0;
 	}
-	case VIDIOCCAPTURE:
+	case VIDIOCSPICT:
 	{
-		int v;
-		if(copy_from_user(&v, arg,sizeof(v)))
-			return -EFAULT;
-		if(btv->win.vidadr == 0)
-			return -EINVAL;
-		if (btv->win.width==0 || btv->win.height==0)
+		struct video_picture *pic = arg;
+		const struct bttv_format *fmt;
+		
+		fmt = format_by_palette(pic->palette);
+		if (NULL == fmt)
 			return -EINVAL;
-		if (1 == no_overlay)
-			return -EIO;
-		spin_lock_irqsave(&btv->s_lock, irq_flags);
-		if (v == 1 && btv->win.vidadr != 0)
-			btv->scr_on = 1;
-		if (v == 0)
-			btv->scr_on = 0;
-		bt848_set_risc_jmps(btv,-1);
-		spin_unlock_irqrestore(&btv->s_lock, irq_flags);
+		down(&fh->lock);
+		retval = -EINVAL;
+		if (fmt->depth != pic->depth && !sloppy)
+			goto fh_unlock_and_return;
+		fh->ovfmt   = fmt;
+		fh->buf.fmt = fmt;
+		btv->init.ovfmt   = fmt;
+		btv->init.buf.fmt = fmt;
+		if (bigendian) {
+			/* dirty hack time:  swap bytes for overlay if the
+			   display adaptor is big endian (insmod option) */
+			if (fmt->palette == VIDEO_PALETTE_RGB555 ||
+			    fmt->palette == VIDEO_PALETTE_RGB565 ||
+			    fmt->palette == VIDEO_PALETTE_RGB32) {
+				fh->ovfmt = fmt+1;
+			}
+		}
+		bt848_bright(btv,pic->brightness);
+		bt848_contrast(btv,pic->contrast);
+		bt848_hue(btv,pic->hue);
+		bt848_sat(btv,pic->colour);
+		up(&fh->lock);
+                return 0;
+	}
+
+	case VIDIOCGWIN:
+	{
+		struct video_window *win = arg;
+
+		memset(win,0,sizeof(*win));
+		win->x      = fh->ov.x;
+		win->y      = fh->ov.y;
+		win->width  = fh->ov.width;
+		win->height = fh->ov.height;
 		return 0;
 	}
+	case VIDIOCSWIN:
+	{
+		struct video_window *win = arg;
+
+		retval = setup_window(fh,btv,win->x,win->y,
+				      win->width,win->height,
+				      win->clips,
+				      win->clipcount);
+		if (0 == retval) {
+			/* on v4l1 this ioctl affects the read() size too */
+			fh->buf.vb.width  = fh->ov.width;
+			fh->buf.vb.height = fh->ov.height;
+			btv->init.buf.vb.width  = fh->ov.width;
+			btv->init.buf.vb.height = fh->ov.height;
+		}
+		return retval;
+	}
+
 	case VIDIOCGFBUF:
 	{
-		struct video_buffer v;
-		v.base=(void *)btv->win.vidadr;
-		v.height=btv->win.sheight;
-		v.width=btv->win.swidth;
-		v.depth=btv->win.depth;
-		v.bytesperline=btv->win.bpl;
-		if(copy_to_user(arg, &v,sizeof(v)))
-			return -EFAULT;
+		struct video_buffer *fbuf = arg;
+		*fbuf = btv->fbuf;
 		return 0;
-			
 	}
 	case VIDIOCSFBUF:
 	{
-		struct video_buffer v;
+		struct video_buffer *fbuf = arg;
+		const struct bttv_format *fmt;
+		unsigned long end;
+
 		if(!capable(CAP_SYS_ADMIN) &&
-		   !capable(CAP_SYS_RAWIO))
-			return -EPERM;
-		if(copy_from_user(&v, arg,sizeof(v)))
-			return -EFAULT;
-		if(v.depth!=8 && v.depth!=15 && v.depth!=16 && 
-		   v.depth!=24 && v.depth!=32 && v.width > 16 &&
-		   v.height > 16 && v.bytesperline > 16)
+                   !capable(CAP_SYS_RAWIO))
+                        return -EPERM;
+		end = (unsigned long)fbuf->base +
+			fbuf->height * fbuf->bytesperline;
+		if (0 == find_videomem((unsigned long)fbuf->base,end))
 			return -EINVAL;
-		down(&btv->lock);
-		if (v.base)
-			btv->win.vidadr=(unsigned long)v.base;
-		btv->win.sheight=v.height;
-		btv->win.swidth=v.width;
-		btv->win.bpp=((v.depth+7)&0x38)/8;
-		btv->win.depth=v.depth;
-		btv->win.bpl=v.bytesperline;
-
-#if 0 /* was broken for ages and nobody noticed.  Looks like we don't need
-	 it any more as everybody explicitly sets the palette using VIDIOCSPICT
-	 these days */
-		/* set sefault color format */
-		switch (v.depth) {
-		case  8: btv->picture.palette = VIDEO_PALETTE_HI240;  break;
-		case 15: btv->picture.palette = VIDEO_PALETTE_RGB555; break;
-		case 16: btv->picture.palette = VIDEO_PALETTE_RGB565; break;
-		case 24: btv->picture.palette = VIDEO_PALETTE_RGB24;  break;
-		case 32: btv->picture.palette = VIDEO_PALETTE_RGB32;  break;
+		down(&fh->lock);
+		retval = -EINVAL;
+		if (sloppy) {
+			/* also set the default palette -- for backward
+			   compatibility with older versions */
+			switch (fbuf->depth) {
+			case 8:
+				fmt = format_by_palette(VIDEO_PALETTE_HI240);
+				break;
+			case 16:
+				fmt = format_by_palette(VIDEO_PALETTE_RGB565);
+				break;
+			case 24:
+				fmt = format_by_palette(VIDEO_PALETTE_RGB24);
+				break;
+			case 32:
+				fmt = format_by_palette(VIDEO_PALETTE_RGB32);
+				break;
+			case 15:
+				fbuf->depth = 16;
+				fmt = format_by_palette(VIDEO_PALETTE_RGB555);
+				break;
+			default:
+				fmt = NULL;
+				break;
+			}
+			if (NULL == fmt)
+				goto fh_unlock_and_return;
+			fh->ovfmt   = fmt;
+			fh->buf.fmt = fmt;
+			btv->init.ovfmt   = fmt;
+			btv->init.buf.fmt = fmt;
+		} else {
+			if (15 == fbuf->depth)
+				fbuf->depth = 16;
+			if (fbuf->depth !=  8 && fbuf->depth != 16 &&
+			    fbuf->depth != 24 && fbuf->depth != 32)
+				goto fh_unlock_and_return;
 		}
+		btv->fbuf = *fbuf;
+		up(&fh->lock);
+		return 0;
+	}
+
+	case VIDIOCCAPTURE:
+#ifdef HAVE_V4L2
+	case VIDIOC_PREVIEW:
 #endif
-	
-		if (bttv_debug)
-			printk("Display at %p is %d by %d, bytedepth %d, bpl %d\n",
-			       v.base, v.width,v.height, btv->win.bpp, btv->win.bpl);
-		spin_lock_irqsave(&btv->s_lock, irq_flags);
-		bt848_set_winsize(btv);
-		spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-		up(&btv->lock);
-		return 0;		
+	{
+		struct bttv_buffer *new;
+		int *on = arg;
+
+		if (*on) {
+			/* verify args */
+			if (NULL == btv->fbuf.base)
+				return -EINVAL;
+			if (fh->ov.width <48 ||
+			    fh->ov.height<32 ||
+			    fh->ov.width >bttv_tvnorms[btv->tvnorm].swidth  ||
+			    fh->ov.height>bttv_tvnorms[btv->tvnorm].sheight ||
+			    NULL == fh->ovfmt)
+				return -EINVAL;
+		}
+
+		if (!check_alloc_btres(btv,fh,RESOURCE_OVERLAY))
+			return -EBUSY;
+		
+		down(&fh->lock);
+		if (*on) {
+			fh->ov.tvnorm = btv->tvnorm;
+			new = videobuf_alloc(sizeof(*new),
+					     V4L2_BUF_TYPE_CAPTURE);
+			bttv_overlay_risc(btv, &fh->ov, fh->ovfmt, new);
+		} else {
+			new = NULL;
+		}
+
+		/* switch over */
+	        retval = bttv_switch_overlay(btv,fh,new);
+		up(&fh->lock);
+		return retval;
 	}
-	case VIDIOCKEY:
+
+	case VIDIOCGMBUF:
 	{
-		/* Will be handled higher up .. */
+		struct video_mbuf *mbuf = arg;
+		int i;
+
+		if (!mmap)
+			return -EINVAL;
+		down(&fh->lock);
+		retval = videobuf_mmap_setup
+			(file,(struct videobuf_buffer**)fh->bufs,
+			 sizeof(struct bttv_buffer),
+			 gbuffers,gbufsize,V4L2_BUF_TYPE_CAPTURE,
+			 release_buffer);
+		if (retval < 0)
+			goto fh_unlock_and_return;
+		memset(mbuf,0,sizeof(*mbuf));
+		mbuf->frames = gbuffers;
+		mbuf->size   = gbuffers * gbufsize;
+		for (i = 0; i < gbuffers; i++)
+			mbuf->offsets[i] = i * gbufsize;
+		up(&fh->lock);
 		return 0;
 	}
-	case VIDIOCGFREQ:
+	case VIDIOCMCAPTURE:
 	{
-		unsigned long v=btv->win.freq;
-		if(copy_to_user(arg,&v,sizeof(v)))
-			return -EFAULT;
+		struct video_mmap *vm = arg;
+		struct bttv_buffer *buf;
+
+		if (vm->frame >= VIDEO_MAX_FRAME)
+			return -EINVAL;
+
+		down(&fh->lock);
+		retval = -EINVAL;
+		buf = fh->bufs[vm->frame];
+		if (NULL == buf)
+			goto fh_unlock_and_return;
+		if (0 == buf->vb.baddr)
+			goto fh_unlock_and_return;
+		if (buf->vb.state == STATE_QUEUED ||
+		    buf->vb.state == STATE_ACTIVE)
+			goto fh_unlock_and_return;
+		
+		retval = bttv_prepare_buffer(btv,buf,
+					     format_by_palette(vm->format),
+					     vm->width,vm->height,0);
+		if (0 != retval)
+			goto fh_unlock_and_return;
+		bttv_queue_buffer(btv,buf);
+		up(&fh->lock);
 		return 0;
 	}
-	case VIDIOCSFREQ:
+	case VIDIOCSYNC:
 	{
-		unsigned long v;
-		if(copy_from_user(&v, arg, sizeof(v)))
-			return -EFAULT;
-		btv->win.freq=v;
-		bttv_call_i2c_clients(btv,cmd,&v);
-#if 1
-		if (btv->radio && btv->has_matchbox)
-			tea5757_set_freq(btv,v);
-#endif
-		return 0;
+		int *frame = arg;
+		struct bttv_buffer *buf;
+
+		if (*frame >= VIDEO_MAX_FRAME)
+			return -EINVAL;
+
+		down(&fh->lock);
+		retval = -EINVAL;
+		buf = fh->bufs[*frame];
+		if (NULL == buf)
+			goto fh_unlock_and_return;
+		retval = videobuf_waiton(&buf->vb,0,1);
+		if (0 != retval)
+			goto fh_unlock_and_return;
+		switch (buf->vb.state) {
+		case STATE_ERROR:
+			retval = -EIO;
+			/* fall through */
+		case STATE_DONE:
+			videobuf_dma_pci_sync(btv->dev,&buf->vb.dma);
+			bttv_dma_free(btv,buf);
+			break;
+		default:
+			retval = -EINVAL;
+			break;
+		}
+		up(&fh->lock);
+		return retval;
 	}
-	
+
+        case BTTV_VERSION:
+        case VIDIOCGFREQ:
+        case VIDIOCSFREQ:
+        case VIDIOCGTUNER:
+        case VIDIOCSTUNER:
+        case VIDIOCGCHAN:
+        case VIDIOCSCHAN:
 	case VIDIOCGAUDIO:
+	case VIDIOCSAUDIO:
+		return bttv_common_ioctls(btv,cmd,arg);
+
+
+#ifdef HAVE_V4L2
+	/* ***  v4l2  *** ************************************************ */
+	case VIDIOC_QUERYCAP:
 	{
-		struct video_audio v;
+		struct v4l2_capability *cap = arg;
 
-		v=btv->audio_dev;
-		v.flags&=~(VIDEO_AUDIO_MUTE|VIDEO_AUDIO_MUTABLE);
-		v.flags|=VIDEO_AUDIO_MUTABLE;
-		strcpy(v.name,"TV");
+		if (0 == v4l2)
+			return -EINVAL;
+                strcpy(cap->name,btv->video_dev.name);
+		cap->type = V4L2_TYPE_CAPTURE;
+		cap->flags = V4L2_FLAG_TUNER | V4L2_FLAG_PREVIEW
+			| V4L2_FLAG_READ | V4L2_FLAG_SELECT;
+		if (mmap)
+			cap->flags |= V4L2_FLAG_STREAMING;
+		cap->inputs = bttv_tvcards[btv->type].video_inputs;
+		cap->outputs = 0;
+		cap->audios = bttv_tvcards[btv->type].audio_inputs;
+		cap->maxwidth = bttv_tvnorms[btv->tvnorm].swidth;
+		cap->maxheight = bttv_tvnorms[btv->tvnorm].sheight;
+		cap->minwidth = 48;
+		cap->minheight = 32;
+		cap->maxframerate = 30;
+		return 0;
+	}
 
-		v.mode = VIDEO_SOUND_MONO;
-		bttv_call_i2c_clients(btv,cmd,&v);
+	case VIDIOC_ENUM_PIXFMT:
+	case VIDIOC_ENUM_FBUFFMT:
+	{
+		struct v4l2_fmtdesc *f = arg;
+		int i, index;
+
+		index = -1;
+		for (i = 0; i < BTTV_FORMATS; i++) {
+			if (bttv_formats[i].fourcc != -1)
+				index++;
+			if (index == f->index)
+				break;
+		}
+		if (BTTV_FORMATS == i)
+			return -EINVAL;
+		if (cmd == VIDIOC_ENUM_FBUFFMT &&
+		    0 == (bttv_formats[i].flags & FORMAT_FLAGS_PACKED))
+			return -EINVAL;
+		memset(f,0,sizeof(*f));
+		f->index = index;
+		strncpy(f->description,bttv_formats[i].name,31);
+		f->pixelformat = bttv_formats[i].fourcc;
+		f->depth = bttv_formats[i].depth;
+		return 0;
+	}
 
-		/* card specific hooks */
-		if (bttv_tvcards[btv->type].audio_hook)
-			bttv_tvcards[btv->type].audio_hook(btv,&v,0);
+	case VIDIOC_G_FMT:
+	{
+		struct v4l2_format *f = arg;
 
-		if(copy_to_user(arg,&v,sizeof(v)))
-			return -EFAULT;
+		memset(f,0,sizeof(*f));
+		f->type = V4L2_BUF_TYPE_CAPTURE;
+		f->fmt.pix.width        = fh->buf.vb.width;
+		f->fmt.pix.height       = fh->buf.vb.height;
+		f->fmt.pix.depth        = fh->buf.fmt->depth;
+		f->fmt.pix.pixelformat  = fh->buf.fmt->fourcc;
+		f->fmt.pix.sizeimage    =
+			(fh->buf.vb.width*fh->buf.vb.height*fh->buf.fmt->depth)/8;
 		return 0;
 	}
-	case VIDIOCSAUDIO:
+	case VIDIOC_S_FMT:
 	{
-		struct video_audio v;
+		struct v4l2_format *f = arg;
+		const struct bttv_format *fmt;
 
-		if(copy_from_user(&v,arg, sizeof(v)))
-			return -EFAULT;
-		down(&btv->lock);
-		if(v.flags&VIDEO_AUDIO_MUTE)
-			audio(btv, AUDIO_MUTE, 1);
-		/* One audio source per tuner -- huh? <GA> */
-		if(v.audio<0 || v.audio >= bttv_tvcards[btv->type].audio_inputs) {
-			up(&btv->lock);
+		if ((f->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_CAPTURE)
+			return -EINVAL;
+		fmt = format_by_fourcc(f->fmt.pix.pixelformat);
+		if (NULL == fmt)
+			return -EINVAL;
+		if (f->fmt.pix.width  < 48 ||
+		    f->fmt.pix.height < 32)
+			return -EINVAL;
+		if (f->fmt.pix.flags & V4L2_FMT_FLAG_BYTESPERLINE)
+			/* FIXME -- not implemented yet */
 			return -EINVAL;
-		}
-		/* bt848_muxsel(btv,v.audio); */
-		if(!(v.flags&VIDEO_AUDIO_MUTE))
-			audio(btv, AUDIO_UNMUTE, 1);
 
-		bttv_call_i2c_clients(btv,cmd,&v);
+		down(&fh->lock);
+		/* fixup format */
+		if (f->fmt.pix.width  > bttv_tvnorms[btv->tvnorm].swidth)
+			f->fmt.pix.width = bttv_tvnorms[btv->tvnorm].swidth;
+		if (f->fmt.pix.height > bttv_tvnorms[btv->tvnorm].sheight)
+			f->fmt.pix.height = bttv_tvnorms[btv->tvnorm].sheight;
+		if (!(f->fmt.pix.flags & V4L2_FMT_FLAG_INTERLACED) &&
+		    f->fmt.pix.height>bttv_tvnorms[btv->tvnorm].sheight/2)
+			f->fmt.pix.height=bttv_tvnorms[btv->tvnorm].sheight/2;
+
+		if (f->fmt.pix.height > bttv_tvnorms[btv->tvnorm].sheight/2) {
+			/* must interlace -- no field splitting available */
+			f->fmt.pix.flags &= ~(V4L2_FMT_FLAG_TOPFIELD|
+					      V4L2_FMT_FLAG_BOTFIELD);
+		} else {
+			/* one field is enouth -- no interlace needed */
+			f->fmt.pix.flags &= ~V4L2_FMT_FLAG_INTERLACED;
+		}
 		
-		/* card specific hooks */
-		if (bttv_tvcards[btv->type].audio_hook)
-			bttv_tvcards[btv->type].audio_hook(btv,&v,1);
+		/* update our state informations */
+		fh->buf.fmt             = fmt;
+		fh->buf.vb.width        = f->fmt.pix.width;
+		fh->buf.vb.height       = f->fmt.pix.height;
+		btv->init.buf.fmt       = fmt;
+		btv->init.buf.vb.width  = f->fmt.pix.width;
+		btv->init.buf.vb.height = f->fmt.pix.height;
 
-		btv->audio_dev=v;
-		up(&btv->lock);
+		/* update data for the application */
+		f->fmt.pix.depth = fmt->depth;
+		f->fmt.pix.sizeimage =
+			(fh->buf.vb.width * fh->buf.vb.height * fmt->depth)/8;
+		up(&fh->lock);
 		return 0;
 	}
 
-	case VIDIOCSYNC:
+	case VIDIOC_G_FBUF:
 	{
-		DECLARE_WAITQUEUE(wait, current);
+		struct v4l2_framebuffer *fb = arg;
 
-		if(copy_from_user((void *)&i,arg,sizeof(int)))
-			return -EFAULT;
-		if (i < 0 || i >= gbuffers)
+		memset(fb,0,sizeof(*fb));
+		fb->base[0]    = btv->fbuf.base;
+		fb->fmt.width  = btv->fbuf.width;
+		fb->fmt.height = btv->fbuf.height;
+		fb->fmt.bytesperline = btv->fbuf.bytesperline;
+		fb->fmt.flags  = V4L2_FMT_FLAG_BYTESPERLINE;
+		fb->capability = V4L2_FBUF_CAP_CLIPPING;
+		if (fh->ovfmt) {
+			fb->fmt.depth  = fh->ovfmt->depth;
+			fb->fmt.pixelformat  = fh->ovfmt->fourcc;
+		}
+		return 0;
+	}
+	case VIDIOC_S_FBUF:
+	{
+		struct v4l2_framebuffer *fb = arg;
+		const struct bttv_format *fmt;
+		unsigned long end;
+		
+		if(!capable(CAP_SYS_ADMIN) &&
+		   !capable(CAP_SYS_RAWIO))
+			return -EPERM;
+
+		/* check args */
+		end = (unsigned long)fb->base[0] +
+			fb->fmt.height * fb->fmt.bytesperline;
+		if (0 == find_videomem((unsigned long)fb->base[0],end))
 			return -EINVAL;
-		switch (btv->gbuf[i].stat) {
-		case GBUFFER_UNUSED:
-			ret = -EINVAL;
-			break;
-		case GBUFFER_GRABBING:
-			add_wait_queue(&btv->capq, &wait);
-			current->state = TASK_INTERRUPTIBLE;
-			while(btv->gbuf[i].stat==GBUFFER_GRABBING) {
-				if (bttv_debug)
-					printk("bttv%d: cap sync: sleep on %d\n",btv->nr,i);
-				schedule();
-				if(signal_pending(current)) {
-					remove_wait_queue(&btv->capq, &wait);
-					current->state = TASK_RUNNING;
-					return -EINTR;
-				}
+
+		fmt = format_by_fourcc(fb->fmt.pixelformat);
+		if (NULL == fmt)
+			return -EINVAL;
+		if (0 == (fmt->flags & FORMAT_FLAGS_PACKED))
+			return -EINVAL;
+
+		down(&fh->lock);
+		retval = -EINVAL;
+		if (fb->flags & V4L2_FBUF_FLAG_OVERLAY) {
+			if (fb->fmt.width > bttv_tvnorms[btv->tvnorm].swidth)
+				goto fh_unlock_and_return;
+			if (fb->fmt.height > bttv_tvnorms[btv->tvnorm].sheight)
+				goto fh_unlock_and_return;
+		}
+
+		/* ok, accept it */
+		btv->fbuf.base   = fb->base[0];
+		btv->fbuf.width  = fb->fmt.width;
+		btv->fbuf.height = fb->fmt.height;
+		btv->fbuf.depth  = fmt->depth;
+		if (fb->fmt.flags & V4L2_FMT_FLAG_BYTESPERLINE)
+			btv->fbuf.bytesperline = fb->fmt.bytesperline;
+		else
+			btv->fbuf.bytesperline = btv->fbuf.width*fmt->depth/8;
+		
+		retval = 0;
+		fh->ovfmt = fmt;
+		btv->init.ovfmt = fmt;
+		if (fb->flags & V4L2_FBUF_FLAG_OVERLAY) {
+			fh->ov.x      = 0;
+			fh->ov.y      = 0;
+			fh->ov.width  = fb->fmt.width;
+			fh->ov.height = fb->fmt.height;
+			btv->init.ov.width  = fb->fmt.width;
+			btv->init.ov.height = fb->fmt.height;
+			if (fh->ov.clips)
+				kfree(fh->ov.clips);
+			fh->ov.clips = NULL;
+			fh->ov.nclips = 0;
+
+			if (check_btres(fh, RESOURCE_OVERLAY)) {
+				struct bttv_buffer *new;
+		
+				new = videobuf_alloc(sizeof(*new),
+						     V4L2_BUF_TYPE_CAPTURE);
+				bttv_overlay_risc(btv,&fh->ov,fh->ovfmt,new);
+				retval = bttv_switch_overlay(btv,fh,new);
 			}
-			remove_wait_queue(&btv->capq, &wait);
-			current->state = TASK_RUNNING;
-			/* fall throuth */
-		case GBUFFER_DONE:
-		case GBUFFER_ERROR:
-			ret = (btv->gbuf[i].stat == GBUFFER_ERROR) ? -EIO : 0;
-			if (bttv_debug)
-				printk("bttv%d: cap sync: buffer %d, retval %d\n",btv->nr,i,ret);
-			btv->gbuf[i].stat = GBUFFER_UNUSED;
 		}
-		if (btv->needs_restart) {
-			down(&btv->lock);
-			bt848_restart(btv);
-			up(&btv->lock);
-		}
-		return ret;
+		up(&fh->lock);
+		return retval;
 	}
+	case VIDIOC_G_WIN:
+	{
+		struct v4l2_window *win = arg;
 
-	case BTTV_FIELDNR: 
-		if(copy_to_user((void *) arg, (void *) &btv->last_field, 
-				sizeof(btv->last_field)))
-			return -EFAULT;
-		break;
-      
-	case BTTV_PLLSET: {
-		struct bttv_pll_info p;
-		if(!capable(CAP_SYS_ADMIN))
-			return -EPERM;
-		if(copy_from_user(&p , (void *) arg, sizeof(btv->pll)))
-			return -EFAULT;
-		down(&btv->lock);
-		btv->pll.pll_ifreq = p.pll_ifreq;
-		btv->pll.pll_ofreq = p.pll_ofreq;
-		btv->pll.pll_crystal = p.pll_crystal;
-		up(&btv->lock);
-		break;
+		memset(win,0,sizeof(*win));
+		win->x      = fh->ov.x;
+		win->y      = fh->ov.y;
+		win->width  = fh->ov.width;
+		win->height = fh->ov.height;
+		return 0;
 	}
-
-	case VIDIOCMCAPTURE:
+	case VIDIOC_S_WIN:
 	{
-		struct video_mmap vm;
-		int ret;
-		if(copy_from_user((void *) &vm, (void *) arg, sizeof(vm)))
-			return -EFAULT;
-		down(&btv->lock);
-		ret = vgrab(btv, &vm);
-		up(&btv->lock);
-		return ret;
+		struct v4l2_window *win = arg;
+
+		return setup_window(fh,btv,win->x,win->y,
+				    win->width,win->height,
+				    (struct video_clip*)win->clips,
+				    win->clipcount);
 	}
-		
-	case VIDIOCGMBUF:
+
+	case VIDIOC_REQBUFS:
 	{
-		struct video_mbuf vm;
-		memset(&vm, 0 , sizeof(vm));
-		vm.size=gbufsize*gbuffers;
-		vm.frames=gbuffers;
-		for (i = 0; i < gbuffers; i++)
-			vm.offsets[i]=i*gbufsize;
-		if(copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-			return -EFAULT;
+		struct v4l2_requestbuffers *req = arg;
+		int size,count;
+
+		if (!mmap)
+			return -EINVAL;
+		if ((req->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_CAPTURE)
+			return -EINVAL;
+		if (req->count < 0)
+			return -EINVAL;
+
+		down(&fh->lock);
+		retval = -EINVAL;
+		if (NULL == fh->buf.fmt    ||
+		    0 == fh->buf.vb.width  ||
+		    0 == fh->buf.vb.height)
+			goto fh_unlock_and_return;
+
+		size = (fh->buf.vb.width*fh->buf.vb.height*fh->buf.fmt->depth) >> 3;
+		size = (size + PAGE_SIZE - 1) & PAGE_MASK;
+		count = req->count;
+		if (count > VIDEO_MAX_FRAME)
+			count = VIDEO_MAX_FRAME;
+		while (size * count > gbuffers * gbufsize)
+			count--;
+		retval = videobuf_mmap_setup(file,
+					     (struct videobuf_buffer**)fh->bufs,
+					     sizeof(struct bttv_buffer),
+					     count,size,V4L2_BUF_TYPE_CAPTURE,
+					     release_buffer);
+		if (retval < 0)
+			goto fh_unlock_and_return;
+		req->type  = V4L2_BUF_TYPE_CAPTURE;
+		req->count = count;
+		up(&fh->lock);
 		return 0;
 	}
-		
-	case VIDIOCGUNIT:
+	case VIDIOC_QUERYBUF:
 	{
-		struct video_unit vu;
-		vu.video=btv->video_dev.minor;
-		vu.vbi=btv->vbi_dev.minor;
-		if(btv->radio_dev.minor!=-1)
-			vu.radio=btv->radio_dev.minor;
-		else
-			vu.radio=VIDEO_NO_UNIT;
-		vu.audio=VIDEO_NO_UNIT;
-		vu.teletext=VIDEO_NO_UNIT;
-		if(copy_to_user((void *)arg, (void *)&vu, sizeof(vu)))
-			return -EFAULT;
+		struct v4l2_buffer *b = arg;
+
+		if ((b->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_CAPTURE)
+			return -EINVAL;
+		if (b->index < 0 || b->index > VIDEO_MAX_FRAME)
+			return -EINVAL;
+		if (NULL == fh->bufs[b->index])
+			return -EINVAL;
+		videobuf_status(b,&fh->bufs[b->index]->vb);
 		return 0;
 	}
-		
-	case BTTV_BURST_ON:
+	case VIDIOC_QBUF:
 	{
-		burst(1);
+		struct v4l2_buffer *b = arg;
+		struct bttv_buffer *buf;
+		int field = 0;
+
+		if ((b->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_CAPTURE)
+			return -EINVAL;
+		if (b->index < 0 || b->index > VIDEO_MAX_FRAME)
+			return -EINVAL;
+
+		down(&fh->lock);
+		retval = -EINVAL;
+		buf = fh->bufs[b->index];
+		if (NULL == buf)
+			goto fh_unlock_and_return;
+		if (0 == buf->vb.baddr)
+			goto fh_unlock_and_return;
+		if (buf->vb.state == STATE_QUEUED ||
+		    buf->vb.state == STATE_ACTIVE)
+			goto fh_unlock_and_return;
+
+		if (b->flags & V4L2_BUF_FLAG_TOPFIELD)
+			field |= VBUF_FIELD_ODD;
+		if (b->flags & V4L2_BUF_FLAG_BOTFIELD)
+		        field |= VBUF_FIELD_EVEN;
+		retval = bttv_prepare_buffer(btv,buf,fh->buf.fmt,
+					     fh->buf.vb.width,fh->buf.vb.height,field);
+		if (0 != retval)
+			goto fh_unlock_and_return;
+
+		list_add_tail(&buf->vb.stream,&fh->stream);
+		if (check_btres(fh, RESOURCE_STREAMING))
+			bttv_queue_buffer(btv,buf);
+		up(&fh->lock);
 		return 0;
 	}
+	case VIDIOC_DQBUF:
+	{
+		struct v4l2_buffer *b = arg;
+		struct bttv_buffer *buf;
 
-	case BTTV_BURST_OFF:
+		if ((b->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_CAPTURE)
+			return -EINVAL;
+
+		down(&fh->lock);
+		retval = -EINVAL;
+		if (list_empty(&fh->stream))
+			goto fh_unlock_and_return;
+		buf = list_entry(fh->stream.next, struct bttv_buffer, vb.stream);
+		retval = videobuf_waiton(&buf->vb,0,1);
+		if (retval < 0)
+			goto fh_unlock_and_return;
+		switch (buf->vb.state) {
+		case STATE_ERROR:
+			retval = -EIO;
+			/* fall through */
+		case STATE_DONE:
+			videobuf_dma_pci_sync(btv->dev,&buf->vb.dma);
+			buf->vb.state = STATE_IDLE;
+			break;
+		default:
+			retval = -EINVAL;
+			goto fh_unlock_and_return;
+		}
+		list_del(&buf->vb.stream);
+		memset(b,0,sizeof(*b));
+		videobuf_status(b,&buf->vb);
+		up(&fh->lock);
+		return retval;
+	}
+	case VIDIOC_STREAMON:
 	{
-		burst(0);
+		struct list_head *list;
+		struct bttv_buffer *buf;
+		
+		if (!check_alloc_btres(btv,fh,RESOURCE_STREAMING))
+			return -EBUSY;
+		bttv_field_count(btv);
+		down(&fh->lock);
+		list_for_each(list,&fh->stream) {
+			buf = list_entry(list, struct bttv_buffer, vb.stream);
+			if (buf->vb.state == STATE_PREPARED)
+				bttv_queue_buffer(btv,buf);
+		}
+		up(&fh->lock);
 		return 0;
 	}
-
-	case BTTV_VERSION:
+	case VIDIOC_STREAMOFF:
 	{
-		return BTTV_VERSION_CODE;
+		down(&fh->lock);
+		retval = -EINVAL;
+		if (!check_btres(fh, RESOURCE_STREAMING))
+			goto fh_unlock_and_return;
+		bttv_stop_streaming(btv,fh);
+		up(&fh->lock);
+		return 0;
 	}
-                        
-	case BTTV_PICNR:
+
+	case VIDIOC_QUERYCTRL:
 	{
-		/* return picture;*/
-		return  0;
+		struct v4l2_queryctrl *c = arg;
+		int i;
+
+		v4l2_fill_ctrl_category(c);
+		if ((c->id <  V4L2_CID_BASE ||
+		     c->id >= V4L2_CID_LASTP1) &&
+		    (c->id <  V4L2_CID_PRIVATE_BASE ||
+		     c->id >= V4L2_CID_PRIVATE_LASTP1))
+			return -EINVAL;
+		for (i = 0; i < BTTV_CTLS; i++)
+			if (bttv_ctls[i].id == c->id)
+				break;
+		if (i == BTTV_CTLS) {
+			*c = no_ctl;
+			return 0;
+		}
+		*c = bttv_ctls[i];
+		if (bttv_ctls[i].category == V4L2_CTRL_CAT_AUDIO) {
+			struct video_audio va;
+			memset(&va,0,sizeof(va));
+			bttv_call_i2c_clients(btv, VIDIOCGAUDIO, &va);
+			if (bttv_tvcards[btv->type].audio_hook)
+				bttv_tvcards[btv->type].audio_hook(btv,&va,0);
+			switch (bttv_ctls[i].id) {
+			case V4L2_CID_AUDIO_VOLUME:
+				if (!(va.flags & VIDEO_AUDIO_VOLUME))
+					*c = no_ctl;
+				break;
+			case V4L2_CID_AUDIO_BALANCE:
+				if (!(va.flags & VIDEO_AUDIO_BALANCE))
+					*c = no_ctl;
+				break;
+			case V4L2_CID_AUDIO_BASS:
+				if (!(va.flags & VIDEO_AUDIO_BASS))
+					*c = no_ctl;
+				break;
+			case V4L2_CID_AUDIO_TREBLE:
+				if (!(va.flags & VIDEO_AUDIO_TREBLE))
+					*c = no_ctl;
+				break;
+			}
+		}
+		return 0;
+	}
+	case VIDIOC_G_CTRL:
+		return get_control(btv,arg);
+	case VIDIOC_S_CTRL:
+		return set_control(btv,arg);
+	case VIDIOC_G_PARM:
+	{
+		struct v4l2_streamparm *parm = arg;
+		struct v4l2_standard s;
+		if (parm->type != V4L2_BUF_TYPE_CAPTURE)
+			return -EINVAL;
+		memset(parm,0,sizeof(*parm));
+		v4l2_video_std_construct(&s, bttv_tvnorms[btv->tvnorm].v4l2_id, 0);
+		parm->parm.capture.timeperframe = v4l2_video_std_tpf(&s);
+		return 0;
 	}
+	
+	case VIDIOC_ENUMSTD:
+	case VIDIOC_G_STD:
+	case VIDIOC_S_STD:
+	case VIDIOC_ENUMINPUT:
+	case VIDIOC_G_INPUT:
+	case VIDIOC_S_INPUT:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQ:
+	case VIDIOC_S_FREQ:
+		return bttv_common_ioctls(btv,cmd,arg);
+#endif /* HAVE_V4L2 */
 
 	default:
 		return -ENOIOCTLCMD;
 	}
 	return 0;
-}
 
-/*
- *	This maps the vmalloced and reserved fbuffer to user space.
- *
- *  FIXME: 
- *  - PAGE_READONLY should suffice!?
- *  - remap_page_range is kind of inefficient for page by page remapping.
- *    But e.g. pte_alloc() does not work in modules ... :-(
- */
-
-static int do_bttv_mmap(struct vm_area_struct *vma, struct bttv *btv, const char *adr, unsigned long size)
-{
-        unsigned long start=(unsigned long) adr;
-        unsigned long page,pos;
-
-        if (size>gbuffers*gbufsize)
-                return -EINVAL;
-        if (!btv->fbuffer) {
-                if(fbuffer_alloc(btv))
-                        return -EINVAL;
-        }
-        pos=(unsigned long) btv->fbuffer;
-        while (size > 0) {
-                page = kvirt_to_pa(pos);
-                if (remap_page_range(vma, start, page, PAGE_SIZE, PAGE_SHARED))
-                        return -EAGAIN;
-                start+=PAGE_SIZE;
-                pos+=PAGE_SIZE;
-                size-=PAGE_SIZE;
-        }
-        return 0;
+ fh_unlock_and_return:
+	up(&fh->lock);
+	return retval;
 }
 
-static int bttv_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size)
+/* start capture to a kernel bounce buffer */
+static int bttv_read_capture(struct bttv_fh *fh)
 {
-        struct bttv *btv=(struct bttv *)dev;
-        int r;
+	struct bttv *btv = fh->btv;
+	int rc;
+	
+	dprintk("bttv%d: read start\n",btv->nr);
+	rc = bttv_prepare_buffer(btv,&fh->read_buf,fh->buf.fmt,
+				 fh->buf.vb.width,fh->buf.vb.height,0);
+	if (0 != rc)
+		return rc;
 
-        down(&btv->lock);
-        r=do_bttv_mmap(vma, btv, adr, size);
-        up(&btv->lock);
-        return r;
+	bttv_queue_buffer(btv,&fh->read_buf);
+	fh->read_off = 0;
+	return 0;
 }
 
-
-static struct video_device bttv_template=
-{
-	owner:		THIS_MODULE,
-	name:		"UNSET",
-	type:		VID_TYPE_TUNER|VID_TYPE_CAPTURE|VID_TYPE_OVERLAY|VID_TYPE_TELETEXT,
-	hardware:	VID_HARDWARE_BT848,
-	open:		bttv_open,
-	close:		bttv_close,
-	read:		bttv_read,
-	write:		bttv_write,
-	ioctl:		bttv_ioctl,
-	mmap:		bttv_mmap,
-	minor:		-1,
-};
+/*
+ * blocking read for a complete video frame
+ * => no kernel bounce buffer needed.
+ */
+static ssize_t
+bttv_read_zerocopy(struct bttv_fh *fh, struct bttv *btv,
+		   char *data,size_t count, loff_t *ppos)
+{
+        int rc;
+
+        /* setup stuff */
+	dprintk("bttv%d: read zerocopy\n",btv->nr);
+        fh->read_buf.vb.baddr = (unsigned long)data;
+        fh->read_buf.vb.bsize = count;
+        rc = bttv_prepare_buffer(btv,&fh->read_buf,fh->buf.fmt,
+				 fh->buf.vb.width,fh->buf.vb.height,0);
+        if (0 != rc)
+		goto done;
+	
+        /* start capture & wait */
+        bttv_queue_buffer(btv,&fh->read_buf);
+        rc = videobuf_waiton(&fh->read_buf.vb,0,1);
+        if (0 == rc) {
+		videobuf_dma_pci_sync(btv->dev,&fh->read_buf.vb.dma);
+                rc = fh->read_buf.vb.size;
+	}
+
+ done:
+	/* cleanup */
+	bttv_dma_free(btv,&fh->read_buf);
+	fh->read_buf.vb.baddr = 0;
+	fh->read_buf.vb.size = 0;
+	return rc;
+}
 
 
-static long vbi_read(struct video_device *v, char *buf, unsigned long count,
-		     int nonblock)
-{
-	struct bttv *btv=(struct bttv *)(v-2);
-	int q,todo;
-	DECLARE_WAITQUEUE(wait, current);
-
-	todo=count;
-	while (todo && todo>(q=VBIBUF_SIZE-btv->vbip)) 
-	{
-		if (btv->needs_restart) {
-			down(&btv->lock);
-			bt848_restart(btv);
-			up(&btv->lock);
-		}
-		if(copy_to_user((void *) buf, (void *) btv->vbibuf+btv->vbip, q))
-			return -EFAULT;
-		todo-=q;
-		buf+=q;
+static ssize_t bttv_read(struct file *file, char *data,
+			 size_t count, loff_t *ppos)
+{
+	struct bttv_fh *fh = file->private_data;
+	struct bttv *btv = fh->btv;
+	int rc, bytes, size;
+
+	if (btv->errors)
+		bttv_reinit_bt848(btv);
+	if (locked_btres(btv,RESOURCE_STREAMING))
+		return -EBUSY;
 
-		add_wait_queue(&btv->vbiq, &wait);
-		current->state = TASK_INTERRUPTIBLE;
-		if (todo && q==VBIBUF_SIZE-btv->vbip) 
-		{
-			if(nonblock)
-			{
-				remove_wait_queue(&btv->vbiq, &wait);
-				current->state = TASK_RUNNING;
-				if(count==todo)
-					return -EWOULDBLOCK;
-				return count-todo;
-			}
-			schedule();
-			if(signal_pending(current))
-			{
-				remove_wait_queue(&btv->vbiq, &wait);
-                                current->state = TASK_RUNNING;
-				if(todo==count)
-					return -EINTR;
-				else
-					return count-todo;
+	down(&fh->lock);
+	size = fh->buf.fmt->depth*fh->buf.vb.width*fh->buf.vb.height >> 3;
+	if (-1 == fh->read_off  &&  count >= size  &&
+	    !(file->f_flags & O_NONBLOCK)) {
+		rc = bttv_read_zerocopy(fh,btv,data,count,ppos);
+		if (rc >= 0)
+			/* ok, all done */
+			goto unlock_out;
+		/* fallback to kernel bounce buffer on failures */
+	}
+	
+	if (-1 == fh->read_off) {
+		/* need to capture a new frame */
+		rc = bttv_read_capture(fh);
+		if (0 != rc)
+			goto unlock_out;
+	}
+
+	/* wait until capture is done */
+        rc = videobuf_waiton(&fh->read_buf.vb, file->f_flags & O_NONBLOCK,1);
+	if (0 != rc)
+		goto unlock_out;
+
+	/* copy to userspace */
+	bytes = count;
+	if (bytes > fh->read_buf.vb.size - fh->read_off)
+		bytes = fh->read_buf.vb.size - fh->read_off;
+	rc = -EFAULT;
+	if (copy_to_user(data,fh->read_buf.vb.dma.vmalloc +
+			 fh->read_off,bytes))
+		goto unlock_out;
+
+	rc = bytes;
+	fh->read_off += bytes;
+	dprintk("bttv%d: read %d bytes\n",btv->nr,bytes);
+	if (fh->read_off == fh->read_buf.vb.size) {
+		/* all data copied, cleanup */
+		dprintk("bttv%d: read done\n",btv->nr);
+		bttv_dma_free(btv,&fh->read_buf);
+		fh->read_off = -1;
+	}
+
+ unlock_out:
+	up(&fh->lock);
+	return rc;
+}
+
+static unsigned int bttv_poll(struct file *file, poll_table *wait)
+{
+	struct bttv_fh *fh = file->private_data;
+	struct bttv_buffer *buf;
+
+	if (check_alloc_btres(fh->btv,fh,RESOURCE_STREAMING)) {
+		/* streaming capture */
+		if (list_empty(&fh->stream))
+			return POLLERR;
+		buf = list_entry(fh->stream.next,struct bttv_buffer,vb.stream);
+	} else {
+		/* read() capture */
+		down(&fh->lock);
+		if (-1 == fh->read_off) {
+			/* need to capture a new frame */
+			if (locked_btres(fh->btv,RESOURCE_STREAMING) ||
+			    0 != bttv_read_capture(fh)) {
+				up(&fh->lock);
+				return POLLERR;
 			}
 		}
-		remove_wait_queue(&btv->vbiq, &wait);
-		current->state = TASK_RUNNING;
+		up(&fh->lock);
+		buf = &fh->read_buf;
 	}
-	if (todo) 
-	{
-		if(copy_to_user((void *) buf, (void *) btv->vbibuf+btv->vbip, todo))
-			return -EFAULT;
-		btv->vbip+=todo;
-	}
-	return count;
+	
+	poll_wait(file, &buf->vb.done, wait);
+	if (buf->vb.state == STATE_DONE ||
+	    buf->vb.state == STATE_ERROR)
+		return POLLIN|POLLRDNORM;
+	return 0;
 }
 
-static unsigned int vbi_poll(struct video_device *dev, struct file *file,
-	poll_table *wait)
+static int bttv_open(struct inode *inode, struct file *file)
 {
-	struct bttv *btv=(struct bttv *)(dev-2);
-	unsigned int mask = 0;
-
-	poll_wait(file, &btv->vbiq, wait);
+	unsigned int minor = minor(inode->i_rdev);
+	struct bttv *btv = NULL;
+	struct bttv_fh *fh;
+	int i;
 
-	if (btv->vbip < VBIBUF_SIZE)
-		mask |= (POLLIN | POLLRDNORM);
+	dprintk(KERN_DEBUG "bttv: open minor=%d\n",minor);
 
-	return mask;
-}
+	for (i = 0; i < bttv_num; i++) {
+		if (bttvs[i].video_dev.minor == minor) {
+			btv = &bttvs[i];
+			break;
+		}
+	}
+	if (NULL == btv)
+		return -ENODEV;
 
-static int vbi_open(struct video_device *dev, int flags)
-{
-	struct bttv *btv=(struct bttv *)(dev-2);
- 	unsigned long irq_flags;
+	dprintk(KERN_DEBUG "bttv%d: open called (video)\n",btv->nr);
 
-        down(&btv->lock);
-	if (btv->needs_restart)
-		bt848_restart(btv);
-	set_pll(btv);
-	btv->vbip=VBIBUF_SIZE;
-	spin_lock_irqsave(&btv->s_lock, irq_flags);
-	btv->vbi_on = 1;
-	bt848_set_risc_jmps(btv,-1);
-	spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-	up(&btv->lock);
+	/* allocate per filehandle data */
+	fh = kmalloc(sizeof(*fh),GFP_KERNEL);
+	if (NULL == fh)
+		return -ENOMEM;
+	file->private_data = fh;
+	*fh = btv->init;
+        init_MUTEX(&fh->lock);
+	INIT_LIST_HEAD(&fh->stream);
+	init_waitqueue_head(&fh->read_buf.vb.done);
+	fh->read_off = -1;
 
-	return 0;   
+	i2c_vidiocschan(btv);
+        return 0;
 }
 
-static void vbi_close(struct video_device *dev)
+static int bttv_release(struct inode *inode, struct file *file)
 {
-	struct bttv *btv=(struct bttv *)(dev-2);
- 	unsigned long irq_flags;
+	struct bttv_fh *fh = file->private_data;
+	struct bttv *btv = fh->btv;
 
-	spin_lock_irqsave(&btv->s_lock, irq_flags);
-	btv->vbi_on = 0;
-	bt848_set_risc_jmps(btv,-1);
-	spin_unlock_irqrestore(&btv->s_lock, irq_flags);
+	/* turn off overlay, stop outstanding captures */
+	if (check_btres(fh, RESOURCE_OVERLAY))
+		bttv_switch_overlay(btv,fh,NULL);
+	if (check_btres(fh, RESOURCE_STREAMING))
+		bttv_stop_streaming(btv,fh);
+	bttv_dma_free(btv,&fh->read_buf);
+
+	file->private_data = NULL;
+	kfree(fh);
+	return 0;
 }
 
-static int vbi_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int
+bttv_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	struct bttv *btv=(struct bttv *)(dev-2);
+	struct bttv_fh *fh = file->private_data;
+	int err;
 
-	switch (cmd) {	
-	case VIDIOCGCAP:
-	{
-		struct video_capability b;
-		strcpy(b.name,btv->vbi_dev.name);
-		b.type = ((bttv_tvcards[btv->type].tuner != -1) ? VID_TYPE_TUNER : 0) |
-			VID_TYPE_TELETEXT;
-		b.channels = 0;
-		b.audios = 0;
-		b.maxwidth = 0;
-		b.maxheight = 0;
-		b.minwidth = 0;
-		b.minheight = 0;
-		if(copy_to_user(arg,&b,sizeof(b)))
-			return -EFAULT;
-		return 0;
-	}
-	case VIDIOCGFREQ:
-	case VIDIOCSFREQ:
-	case VIDIOCGTUNER:
-	case VIDIOCSTUNER:
-	case VIDIOCGCHAN:
-	case VIDIOCSCHAN:
-	case BTTV_VERSION:
-		return bttv_ioctl(dev-2,cmd,arg);
-	case BTTV_VBISIZE:
-		/* make alevt happy :-) */
-		return VBIBUF_SIZE;
-	default:
+	if (!mmap)
 		return -EINVAL;
-	}
-}
+	down(&fh->lock);
+	err = videobuf_mmap_mapper(vma,(struct videobuf_buffer**)fh->bufs);
+	up(&fh->lock);
+	return err;
+}
+
+static struct file_operations bttv_fops =
+{
+	owner:	  THIS_MODULE,
+	open:	  bttv_open,
+	release:  bttv_release,
+	ioctl:	  video_generic_ioctl,
+	llseek:	  no_llseek,
+	read:	  bttv_read,
+	mmap:	  bttv_mmap,
+	poll:     bttv_poll,
+};
 
-static struct video_device vbi_template=
+static struct video_device bttv_template =
 {
-	owner:		THIS_MODULE,
-	name:		"bttv vbi",
-	type:		VID_TYPE_CAPTURE|VID_TYPE_TELETEXT,
-	hardware:	VID_HARDWARE_BT848,
-	open:		vbi_open,
-	close:		vbi_close,
-	read:		vbi_read,
-	write:		bttv_write,
-	poll:		vbi_poll,
-	ioctl:		vbi_ioctl,
-	minor:		-1,
+	name:     "UNSET",
+	type:     VID_TYPE_CAPTURE|VID_TYPE_TUNER|VID_TYPE_OVERLAY|
+	          VID_TYPE_CLIPPING|VID_TYPE_SCALES,
+	hardware: VID_HARDWARE_BT848,
+	fops:     &bttv_fops,
+	kernel_ioctl: bttv_ioctl,
+	minor:    -1,
 };
 
+/* ----------------------------------------------------------------------- */
+/* radio interface                                                         */
 
-static int radio_open(struct video_device *dev, int flags)
+static int radio_open(struct inode *inode, struct file *file)
 {
-	struct bttv *btv = (struct bttv *)(dev-1);
-	unsigned long v;
+	unsigned int minor = minor(inode->i_rdev);
+	struct bttv *btv = NULL;
+	unsigned long v = 400*16;
+	int i;
 
-        down(&btv->lock);
-	if (btv->user)
-		goto busy_unlock;
-	btv->user++;
+	dprintk("bttv: open minor=%d\n",minor);
 
-	btv->radio = 1;
-	v = 400*16;
-	bttv_call_i2c_clients(btv,VIDIOCSFREQ,&v);
-	bttv_call_i2c_clients(btv,AUDC_SET_RADIO,&btv->tuner_type);
-	bt848_muxsel(btv,0);
-	up(&btv->lock);
+	for (i = 0; i < bttv_num; i++) {
+		if (bttvs[i].radio_dev.minor == minor) {
+			btv = &bttvs[i];
+			break;
+		}
+	}
+	if (NULL == btv)
+		return -ENODEV;
+
+	dprintk("bttv%d: open called (radio)\n",btv->nr);
+	down(&btv->lock);
+	if (btv->radio_user) {
+		up(&btv->lock);
+		return -EBUSY;
+	}
+	btv->radio_user++;
+	file->private_data = btv;
 
-	return 0;   
+	i2c_vidiocschan(btv);
+	bttv_call_i2c_clients(btv,VIDIOCSFREQ,&v);
+        bttv_call_i2c_clients(btv,AUDC_SET_RADIO,&btv->tuner_type);
+	audio_mux(btv,AUDIO_RADIO);
 
- busy_unlock:
 	up(&btv->lock);
-	return -EBUSY;
+        return 0;
 }
 
-static void radio_close(struct video_device *dev)
+static int radio_release(struct inode *inode, struct file *file)
 {
-	struct bttv *btv=(struct bttv *)(dev-1);
+	struct bttv    *btv = file->private_data;
 
-	down(&btv->lock);
-	btv->user--;
-	btv->radio = 0;
-	up(&btv->lock);
+	btv->radio_user--;
+	return 0;
 }
 
-static long radio_read(struct video_device *v, char *buf, unsigned long count, int nonblock)
+static int radio_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
-	return -EINVAL;
-}
+	struct bttv    *btv = file->private_data;
 
-static int radio_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
-{
-        struct bttv *btv=(struct bttv *)(dev-1);
-	switch (cmd) {	
+	switch (cmd) {
 	case VIDIOCGCAP:
 	{
-		struct video_capability v;
-		strcpy(v.name,btv->video_dev.name);
-		v.type = VID_TYPE_TUNER;
-		v.channels = 1;
-		v.audios = 1;
-		/* No we don't do pictures */
-		v.maxwidth = 0;
-		v.maxheight = 0;
-		v.minwidth = 0;
-		v.minheight = 0;
-		if (copy_to_user(arg, &v, sizeof(v)))
-			return -EFAULT;
-		return 0;
-		break;
-	}
-	case VIDIOCGTUNER:
-	{
-		struct video_tuner v;
-		if(copy_from_user(&v,arg,sizeof(v))!=0)
-			return -EFAULT;
-		if(v.tuner||btv->channel)	/* Only tuner 0 */
-			return -EINVAL;
-		strcpy(v.name, "Radio");
-		/* japan:          76.0 MHz -  89.9 MHz
-		   western europe: 87.5 MHz - 108.0 MHz
-		   russia:         65.0 MHz - 108.0 MHz */
-		v.rangelow=(int)(65*16);
-		v.rangehigh=(int)(108*16);
-		v.flags= 0; /* XXX */
-		v.mode = 0; /* XXX */
-		bttv_call_i2c_clients(btv,cmd,&v);
-		if(copy_to_user(arg,&v,sizeof(v)))
-			return -EFAULT;
-		return 0;
+                struct video_capability *cap = arg;
+
+		memset(cap,0,sizeof(*cap));
+                strcpy(cap->name,btv->radio_dev.name);
+                cap->type = VID_TYPE_TUNER;
+		cap->channels = 1;
+		cap->audios = 1;
+                return 0;
 	}
-	case VIDIOCSTUNER:
-	{
-		struct video_tuner v;
-		if(copy_from_user(&v, arg, sizeof(v)))
-			return -EFAULT;
-		/* Only channel 0 has a tuner */
-		if(v.tuner!=0 || btv->channel)
-			return -EINVAL;
-		/* XXX anything to do ??? */
+
+        case VIDIOCGTUNER:
+        {
+                struct video_tuner *v = arg;
+
+                if(v->tuner)
+                        return -EINVAL;
+		memset(v,0,sizeof(*v));
+                strcpy(v->name, "Radio");
+                /* japan:          76.0 MHz -  89.9 MHz
+                   western europe: 87.5 MHz - 108.0 MHz
+                   russia:         65.0 MHz - 108.0 MHz */
+                v->rangelow=(int)(65*16);
+                v->rangehigh=(int)(108*16);
+                bttv_call_i2c_clients(btv,cmd,v);
+                return 0;
+        }
+        case VIDIOCSTUNER:
+		/* nothing to do */
 		return 0;
-	}
-	case VIDIOCGFREQ:
-	case VIDIOCSFREQ:
+	
+	case BTTV_VERSION:
+        case VIDIOCGFREQ:
+        case VIDIOCSFREQ:
 	case VIDIOCGAUDIO:
 	case VIDIOCSAUDIO:
-		bttv_ioctl((struct video_device *)btv,cmd,arg);
-		break;
+		return bttv_common_ioctls(btv,cmd,arg);
+
 	default:
 		return -ENOIOCTLCMD;
 	}
 	return 0;
 }
 
-static struct video_device radio_template=
+static struct file_operations radio_fops =
 {
-	owner:		THIS_MODULE,
-	name:		"bttv radio",
-	type:		VID_TYPE_TUNER,
-	hardware:	VID_HARDWARE_BT848,
-	open:		radio_open,
-	close:		radio_close,
-	read:		radio_read,          /* just returns -EINVAL */
-	write:		bttv_write,          /* just returns -EINVAL */
-	ioctl:		radio_ioctl,
-	minor:		-1,
+	owner:	  THIS_MODULE,
+	open:	  radio_open,
+	release:  radio_release,
+	ioctl:	  video_generic_ioctl,
+	llseek:	  no_llseek,
 };
 
+static struct video_device radio_template =
+{
+	name:     "bt848/878 radio",
+	type:     VID_TYPE_TUNER|VID_TYPE_TELETEXT,
+	hardware: VID_HARDWARE_BT848,
+	fops:     &radio_fops,
+	kernel_ioctl: radio_ioctl,
+	minor:    -1,
+};
+
+/* ----------------------------------------------------------------------- */
+/* irq handler                                                             */
 
-static void bt848_set_risc_jmps(struct bttv *btv, int flags)
+static char *irq_name[] = { "FMTCHG", "VSYNC", "HSYNC", "OFLOW", "HLOCK",
+			    "VPRES", "6", "7", "I2CDONE", "GPINT", "10",
+			    "RISCI", "FBUS", "FTRGT", "FDSR", "PPERR",
+			    "RIPERR", "PABORT", "OCERR", "SCERR" };
+
+static void bttv_print_irqbits(u32 print, u32 mark)
 {
-	if (-1 == flags) {
-		/* defaults */
-		flags = 0;
-		if (btv->scr_on)
-			flags |= 0x03;
-		if (btv->vbi_on)
-			flags |= 0x0c;
-	}
-
-	if (bttv_debug > 1)
-		printk("bttv%d: set_risc_jmp %08lx:",
-		       btv->nr,virt_to_bus(btv->risc_jmp));
-
-	/* Sync to start of odd field */
-	btv->risc_jmp[0]=cpu_to_le32(BT848_RISC_SYNC|BT848_RISC_RESYNC
-                                |BT848_FIFO_STATUS_VRE);
-	btv->risc_jmp[1]=cpu_to_le32(0);
-
-	/* Jump to odd vbi sub */
-	btv->risc_jmp[2]=cpu_to_le32(BT848_RISC_JUMP|(0xd<<20));
-	if (flags&8) {
-		if (bttv_debug > 1)
-			printk(" ev=%08lx",virt_to_bus(btv->vbi_odd));
-		btv->risc_jmp[3]=cpu_to_le32(virt_to_bus(btv->vbi_odd));
-	} else {
-		if (bttv_debug > 1)
-			printk(" -----------");
-		btv->risc_jmp[3]=cpu_to_le32(virt_to_bus(btv->risc_jmp+4));
-	}
-
-        /* Jump to odd sub */
-	btv->risc_jmp[4]=cpu_to_le32(BT848_RISC_JUMP|(0xe<<20));
-	if (0 != btv->risc_cap_odd) {
-		if (bttv_debug > 1)
-			printk(" e%d=%08x",btv->gq_grab,btv->risc_cap_odd);
-		flags |= 3;
-		btv->risc_jmp[5]=cpu_to_le32(btv->risc_cap_odd);
-	} else if ((flags&2) &&
-		   (!btv->win.interlace || 0 == btv->risc_cap_even)) {
-		if (bttv_debug > 1)
-			printk(" eo=%08lx",virt_to_bus(btv->risc_scr_odd));
-		btv->risc_jmp[5]=cpu_to_le32(virt_to_bus(btv->risc_scr_odd));
-	} else {
-		if (bttv_debug > 1)
-			printk(" -----------");
-		btv->risc_jmp[5]=cpu_to_le32(virt_to_bus(btv->risc_jmp+6));
+	int i;
+	
+	printk("bits:");
+	for (i = 0; i < (sizeof(irq_name)/sizeof(char*)); i++) {
+		if (print & (1 << i))
+			printk(" %s",irq_name[i]);
+		if (mark & (1 << i))
+			printk("*");
 	}
+}
 
-
-	/* Sync to start of even field */
-	btv->risc_jmp[6]=cpu_to_le32(BT848_RISC_SYNC|BT848_RISC_RESYNC
-                                |BT848_FIFO_STATUS_VRO);
-	btv->risc_jmp[7]=cpu_to_le32(0);
-
-	/* Jump to even vbi sub */
-	btv->risc_jmp[8]=cpu_to_le32(BT848_RISC_JUMP);
-	if (flags&4) {
-		if (bttv_debug > 1)
-			printk(" ov=%08lx",virt_to_bus(btv->vbi_even));
-		btv->risc_jmp[9]=cpu_to_le32(virt_to_bus(btv->vbi_even));
-	} else {
-		if (bttv_debug > 1)
-			printk(" -----------");
-		btv->risc_jmp[9]=cpu_to_le32(virt_to_bus(btv->risc_jmp+10));
-	}
-
-	/* Jump to even sub */
-	btv->risc_jmp[10]=cpu_to_le32(BT848_RISC_JUMP|(8<<20));
-	if (0 != btv->risc_cap_even) {
-		if (bttv_debug > 1)
-			printk(" o%d=%08x",btv->gq_grab,btv->risc_cap_even);
-		flags |= 3;
-		btv->risc_jmp[11]=cpu_to_le32(btv->risc_cap_even);
-	} else if ((flags&1) &&
-		   btv->win.interlace) {
-		if (bttv_debug > 1)
-			printk(" oo=%08lx",virt_to_bus(btv->risc_scr_even));
-		btv->risc_jmp[11]=cpu_to_le32(virt_to_bus(btv->risc_scr_even));
-	} else {
-		if (bttv_debug > 1)
-			printk(" -----------");
-		btv->risc_jmp[11]=cpu_to_le32(virt_to_bus(btv->risc_jmp+12));
+static void bttv_print_riscaddr(struct bttv *btv)
+{
+	printk("  main: %08Lx\n",
+	       (u64)btv->main.dma);
+	printk("  vbi : o=%08Lx e=%08Lx\n",
+	       btv->vcurr ? (u64)btv->vcurr->odd.dma : 0,
+	       btv->vcurr ? (u64)btv->vcurr->even.dma : 0);
+	printk("  cap : o=%08Lx e=%08Lx\n",
+	       btv->odd ? (u64)btv->odd->odd.dma : 0,
+	       btv->even ? (u64)btv->even->even.dma : 0);
+	printk("  scr : o=%08Lx e=%08Lx\n",
+	       btv->screen ? (u64)btv->screen->odd.dma  : 0,
+	       btv->screen ? (u64)btv->screen->even.dma : 0);
+}
+
+static void bttv_irq_timeout(unsigned long data)
+{
+	struct bttv *btv = (struct bttv *)data;
+	struct bttv_buffer *o_even,*o_odd,*o_vcurr;
+	struct bttv_buffer *capture;
+
+	if (bttv_verbose) {
+		printk(KERN_INFO "bttv%d: timeout: risc=%08x, ",
+		       btv->nr,btread(BT848_RISC_COUNT));
+		bttv_print_irqbits(btread(BT848_INT_STAT),0);
+		printk("\n");
 	}
 
-	if (btv->gq_start) {
-		btv->risc_jmp[12]=cpu_to_le32(BT848_RISC_JUMP|(0x8<<16)|BT848_RISC_IRQ);
+	spin_lock(&btv->s_lock);
+	o_odd   = btv->odd;
+	o_even  = btv->even;
+	o_vcurr = btv->vcurr;
+	btv->odd   = NULL;
+	btv->even  = NULL;
+	btv->vcurr = NULL;
+	
+	/* deactivate stuff */
+	bttv_risc_hook(btv, RISC_SLOT_O_FIELD, NULL, 0);
+	bttv_risc_hook(btv, RISC_SLOT_E_FIELD, NULL, 0);
+	bttv_risc_hook(btv, RISC_SLOT_O_VBI, NULL, 0);
+	bttv_risc_hook(btv, RISC_SLOT_E_VBI, NULL, 0);
+	bttv_set_dma(btv, 0, 0);
+
+	/* wake up + free */
+	if (o_odd == o_even) {
+		if (NULL != o_odd) {
+			o_odd->vb.state = STATE_ERROR;
+			wake_up(&o_odd->vb.done);
+		}
 	} else {
-		btv->risc_jmp[12]=cpu_to_le32(BT848_RISC_JUMP);
+		if (NULL != o_odd) {
+			o_odd->vb.state = STATE_ERROR;
+			wake_up(&o_odd->vb.done);
+		}
+		if (NULL != o_even) {
+			o_even->vb.state = STATE_ERROR;
+			wake_up(&o_even->vb.done);
+		}
+	}
+	if (NULL != o_vcurr) {
+		o_vcurr->vb.state = STATE_ERROR;
+		wake_up(&o_vcurr->vb.done);
 	}
-	btv->risc_jmp[13]=cpu_to_le32(virt_to_bus(btv->risc_jmp));
-
-	/* enable cpaturing and DMA */
-	if (bttv_debug > 1)
-		printk(" flags=0x%x dma=%s\n",
-		       flags,(flags&0x0f) ? "on" : "off");
-	btaor(flags, ~0x0f, BT848_CAP_CTL);
-	if (flags&0x0f)
-		bt848_dma(btv, 3);
-	else
-		bt848_dma(btv, 0);
-}
-
-# define do_video_register(dev,type,nr) video_register_device(dev,type,nr)
 
-static int __devinit init_video_dev(struct bttv *btv)
-{
-	audio(btv, AUDIO_MUTE, 1);
-        
-	if(do_video_register(&btv->video_dev,VFL_TYPE_GRABBER,video_nr)<0)
-		return -1;
-	if(do_video_register(&btv->vbi_dev,VFL_TYPE_VBI,vbi_nr)<0) 
-        {
-	        video_unregister_device(&btv->video_dev);
-		return -1;
+	/* cancel all outstanding capture / vbi requests */
+	while (!list_empty(&btv->capture)) {
+		capture = list_entry(btv->capture.next, struct bttv_buffer, vb.queue);
+		list_del(&capture->vb.queue);
+		capture->vb.state = STATE_ERROR;
+		wake_up(&capture->vb.done);
 	}
-	if (btv->has_radio)
-	{
-		if(do_video_register(&btv->radio_dev, VFL_TYPE_RADIO, radio_nr)<0) 
-                {
-		        video_unregister_device(&btv->vbi_dev);
-		        video_unregister_device(&btv->video_dev);
-			return -1;
-		}
+	while (!list_empty(&btv->vcapture)) {
+		capture = list_entry(btv->vcapture.next, struct bttv_buffer, vb.queue);
+		list_del(&capture->vb.queue);
+		capture->vb.state = STATE_ERROR;
+		wake_up(&capture->vb.done);
 	}
-        return 1;
+	
+	btv->errors++;
+	spin_unlock(&btv->s_lock);	
 }
 
-static int __devinit init_bt848(struct bttv *btv)
+static void
+bttv_irq_switch_fields(struct bttv *btv)
 {
-	int j;
- 	unsigned long irq_flags;
-
-	btv->user=0; 
-        init_MUTEX(&btv->lock);
-
-	/* dump current state of the gpio registers before changing them,
-	 * might help to make a new card work */
-	if (bttv_gpio)
-		bttv_gpio_tracking(btv,"init #1");
-
-	/* reset the bt848 */
-	btwrite(0, BT848_SRESET);
-	DEBUG(printk(KERN_DEBUG "bttv%d: bt848_mem: 0x%lx\n", btv->nr, (unsigned long) btv->bt848_mem));
+	struct bttv_buffer *o_even,*o_odd,*o_vcurr;
+	struct bttv_buffer *capture;
+	int irqflags = 0;
+#ifdef HAVE_V4L2
+	stamp_t ts;
+#endif
 
-	/* not registered yet */
-	btv->video_dev.minor = -1;
-	btv->radio_dev.minor = -1;
-	btv->vbi_dev.minor = -1;
-
-	/* default setup for max. PAL size in a 1024xXXX hicolor framebuffer */
-	btv->win.norm=0; /* change this to 1 for NTSC, 2 for SECAM */
-	btv->win.interlace=1;
-	btv->win.x=0;
-	btv->win.y=0;
-	btv->win.width=320;
-	btv->win.height=240;
-	btv->win.bpp=2;
-	btv->win.depth=16;
-	btv->win.color_fmt=BT848_COLOR_FMT_RGB16;
-	btv->win.bpl=1024*btv->win.bpp;
-	btv->win.swidth=1024;
-	btv->win.sheight=768;
-	btv->win.vidadr=0;
-	btv->vbi_on=0;
-	btv->scr_on=0;
-
-	btv->risc_scr_odd=0;
-	btv->risc_scr_even=0;
-	btv->risc_cap_odd=0;
-	btv->risc_cap_even=0;
-	btv->risc_jmp=0;
-	btv->vbibuf=0;
-        btv->field=btv->last_field=0;
+	spin_lock(&btv->s_lock);
+	o_odd   = btv->odd;
+	o_even  = btv->even;
+	o_vcurr = btv->vcurr;
+	btv->odd   = NULL;
+	btv->even  = NULL;
+	btv->vcurr = NULL;
+
+	/* vbi request ? */
+	if (!list_empty(&btv->vcapture)) {
+		irqflags = 1;
+		btv->vcurr = list_entry(btv->vcapture.next, struct bttv_buffer, vb.queue);
+		list_del(&btv->vcurr->vb.queue);
+	}
+
+	/* capture request ? */
+	if (!list_empty(&btv->capture)) {
+		irqflags = 1;
+		capture = list_entry(btv->capture.next, struct bttv_buffer, vb.queue);
+		list_del(&capture->vb.queue);
+		if (capture->vb.field & VBUF_FIELD_ODD)
+			btv->odd = capture;
+		if (capture->vb.field & VBUF_FIELD_EVEN)
+			btv->even = capture;
+
+		/* capture request for other field ? */
+		if (!(capture->vb.field & VBUF_FIELD_INTER) &&
+		    !list_empty(&btv->capture)) {
+			capture = list_entry(btv->capture.next, struct bttv_buffer, vb.queue);
+			if (!(capture->vb.field & VBUF_FIELD_INTER)) {
+				if (NULL == btv->odd &&
+				    capture->vb.field & VBUF_FIELD_ODD) {
+					btv->odd = capture;
+					list_del(&capture->vb.queue);
+				}
+				if (NULL == btv->even &&
+				    capture->vb.field & VBUF_FIELD_EVEN) {
+					btv->even = capture;
+					list_del(&capture->vb.queue);
+				}
+			}
+		}
+	}
 
-	btv->errors=0;
-	btv->needs_restart=0;
-	btv->has_radio=radio[btv->nr];
+	/* screen overlay ? */
+	if (NULL != btv->screen) {
+		if (btv->screen->vb.field & VBUF_FIELD_INTER) {
+			if (NULL == btv->odd && NULL == btv->even) {
+				btv->odd  = btv->screen;
+				btv->even = btv->screen;
+			}
+		} else {
+			if ((btv->screen->vb.field & VBUF_FIELD_ODD) &&
+			    NULL == btv->odd) {
+				btv->odd = btv->screen;
+			}
+			if ((btv->screen->vb.field & VBUF_FIELD_EVEN) &&
+			    NULL == btv->even) {
+				btv->even = btv->screen;
+			}
+		}
+	}
 
-	if (!(btv->risc_scr_odd=(unsigned int *) kmalloc(RISCMEM_LEN/2, GFP_KERNEL)))
-		return -1;
-	if (!(btv->risc_scr_even=(unsigned int *) kmalloc(RISCMEM_LEN/2, GFP_KERNEL)))
-		return -1;
-	if (!(btv->risc_jmp =(unsigned int *) kmalloc(2048, GFP_KERNEL)))
-		return -1;
-	btv->vbi_odd=btv->risc_jmp+16;
-	btv->vbi_even=btv->vbi_odd+256;
-	btv->bus_vbi_odd=virt_to_bus(btv->risc_jmp+12);
-	btv->bus_vbi_even=virt_to_bus(btv->risc_jmp+6);
-
-	btwrite(virt_to_bus(btv->risc_jmp+2), BT848_RISC_STRT_ADD);
-	btv->vbibuf=(unsigned char *) vmalloc_32(VBIBUF_SIZE);
-	if (!btv->vbibuf) 
-		return -1;
-	if (!(btv->gbuf = kmalloc(sizeof(struct bttv_gbuf)*gbuffers,GFP_KERNEL)))
-		return -1;
-	for (j = 0; j < gbuffers; j++) {
-		if (!(btv->gbuf[j].risc = kmalloc(16384,GFP_KERNEL)))
-			return -1;
+	if (irq_debug)
+		printk(KERN_DEBUG
+		       "bttv: irq odd=%p even=%p screen=%p vbi=%p\n",
+		       btv->odd,btv->even,btv->screen,btv->vcurr);
+	
+	/* activate new fields */
+	bttv_buffer_activate(btv,btv->odd,btv->even);
+	if (btv->vcurr) {
+		btv->vcurr->vb.state = STATE_ACTIVE;
+		bttv_risc_hook(btv, RISC_SLOT_O_VBI, &btv->vcurr->odd, 0);
+		bttv_risc_hook(btv, RISC_SLOT_E_VBI, &btv->vcurr->even, 0);
+	} else {
+		bttv_risc_hook(btv, RISC_SLOT_O_VBI, NULL, 0);
+		bttv_risc_hook(btv, RISC_SLOT_E_VBI, NULL, 0);
 	}
+	bttv_set_dma(btv, 0, irqflags);
 	
-	memset(btv->vbibuf, 0, VBIBUF_SIZE); /* We don't want to return random
-	                                        memory to the user */
-
-	btv->fbuffer=NULL;
-
-/*	btwrite(0, BT848_TDEC); */
-        btwrite(0x10, BT848_COLOR_CTL);
-	btwrite(0x00, BT848_CAP_CTL);
-	/* set planar and packed mode trigger points and         */
-	/* set rising edge of inverted GPINTR pin as irq trigger */
-	btwrite(BT848_GPIO_DMA_CTL_PKTP_32|
-		BT848_GPIO_DMA_CTL_PLTP1_16|
-		BT848_GPIO_DMA_CTL_PLTP23_16|
-		BT848_GPIO_DMA_CTL_GPINTC|
-		BT848_GPIO_DMA_CTL_GPINTI, 
-		BT848_GPIO_DMA_CTL);
-
-        /* select direct input */
-	btwrite(0x00, BT848_GPIO_REG_INP);
-	btwrite(0x00, BT848_GPIO_OUT_EN);
-	if (bttv_gpio)
-		bttv_gpio_tracking(btv,"init #2");
-
-	btwrite(BT848_IFORM_MUX1 | BT848_IFORM_XTAUTO | BT848_IFORM_AUTO,
-		BT848_IFORM);
-
-	btwrite(0xd8, BT848_CONTRAST_LO);
-	bt848_bright(btv, 0x10);
-
-	btwrite(0x20, BT848_E_VSCALE_HI);
-	btwrite(0x20, BT848_O_VSCALE_HI);
-	btwrite(/*BT848_ADC_SYNC_T|*/
-		BT848_ADC_RESERVED|BT848_ADC_CRUSH, BT848_ADC);
-
-	if (lumafilter) {
-		btwrite(0, BT848_E_CONTROL);
-		btwrite(0, BT848_O_CONTROL);
+	/* wake up + free */
+#ifdef HAVE_V4L2
+	v4l2_masterclock_gettime(&ts);
+#endif
+	if (o_odd == o_even) {
+		if (NULL != o_odd && btv->odd != o_odd) {
+#ifdef HAVE_V4L2
+			o_odd->vb.ts = ts;
+#endif
+			o_odd->vb.field_count = btv->field_count;
+			o_odd->vb.state = STATE_DONE;
+			wake_up(&o_odd->vb.done);
+		}
 	} else {
-		btwrite(BT848_CONTROL_LDEC, BT848_E_CONTROL);
-		btwrite(BT848_CONTROL_LDEC, BT848_O_CONTROL);
+		if (NULL != o_odd && btv->odd != o_odd) {
+#ifdef HAVE_V4L2
+			o_odd->vb.ts = ts;
+#endif
+			o_odd->vb.field_count = btv->field_count;
+			o_odd->vb.state = STATE_DONE;
+			wake_up(&o_odd->vb.done);
+		}
+		if (NULL != o_even && btv->even != o_even) {
+#ifdef HAVE_V4L2
+			o_even->vb.ts = ts;
+#endif
+			o_even->vb.field_count = btv->field_count;
+			o_even->vb.state = STATE_DONE;
+			wake_up(&o_even->vb.done);
+		}
 	}
-
-	btv->picture.colour=254<<7;
-	btv->picture.brightness=128<<8;
-	btv->picture.hue=128<<8;
-	btv->picture.contrast=0xd8<<7;
-
-	btwrite(0x00, BT848_E_SCLOOP);
-	btwrite(0x00, BT848_O_SCLOOP);
-
-	/* clear interrupt status */
-	btwrite(0xfffffUL, BT848_INT_STAT);
-        
-	/* set interrupt mask */
-	btwrite(btv->triton1|
-                /*BT848_INT_PABORT|BT848_INT_RIPERR|BT848_INT_PPERR|
-                  BT848_INT_FDSR|BT848_INT_FTRGT|BT848_INT_FBUS|*/
-                (fieldnr ? BT848_INT_VSYNC : 0)|
-		BT848_INT_GPINT|
-		BT848_INT_SCERR|
-		BT848_INT_RISCI|BT848_INT_OCERR|BT848_INT_VPRES|
-		BT848_INT_FMTCHG|BT848_INT_HLOCK,
-		BT848_INT_MASK);
-
-	bt848_muxsel(btv, 1);
-	bt848_set_winsize(btv);
-	make_vbitab(btv);
-	spin_lock_irqsave(&btv->s_lock, irq_flags);
-	bt848_set_risc_jmps(btv,-1);
-	spin_unlock_irqrestore(&btv->s_lock, irq_flags);
-
-	/* needs to be done before i2c is registered */
-        if (btv->type == BTTV_HAUPPAUGE || btv->type == BTTV_HAUPPAUGE878)
-                bttv_boot_msp34xx(btv,5);
-	if (btv->type == BTTV_VOODOOTV_FM)
-		bttv_boot_msp34xx(btv,20);
-
-	/* register i2c */
-        btv->tuner_type=-1;
-        init_bttv_i2c(btv);
-
-	/* some card-specific stuff (needs working i2c) */
-	bttv_init_card(btv);
-
-	/*
-	 *	Now add the template and register the device unit.
-	 */
-        init_video_dev(btv);
-
-	return 0;
+	if (NULL != o_vcurr) {
+#ifdef HAVE_V4L2
+		o_vcurr->vb.ts = ts;
+#endif
+		o_vcurr->vb.field_count = btv->field_count;
+		o_vcurr->vb.state = STATE_DONE;
+		wake_up(&o_vcurr->vb.done);
+	}
+	spin_unlock(&btv->s_lock);
 }
 
-/* ----------------------------------------------------------------------- */
-
-static char *irq_name[] = { "FMTCHG", "VSYNC", "HSYNC", "OFLOW", "HLOCK",
-			    "VPRES", "6", "7", "I2CDONE", "GPINT", "10",
-			    "RISCI", "FBUS", "FTRGT", "FDSR", "PPERR",
-			    "RIPERR", "PABORT", "OCERR", "SCERR" };
-
 static void bttv_irq(int irq, void *dev_id, struct pt_regs * regs)
 {
 	u32 stat,astat;
@@ -2660,15 +3039,11 @@
 		dstat=btread(BT848_DSTATUS);
 
 		if (irq_debug) {
-			int i;
-			printk(KERN_DEBUG "bttv%d: irq loop=%d risc=%x, bits:",
-			       btv->nr, count, stat>>28);
-			for (i = 0; i < (sizeof(irq_name)/sizeof(char*)); i++) {
-				if (stat & (1 << i))
-					printk(" %s",irq_name[i]);
-				if (astat & (1 << i))
-					printk("*");
-			}
+			printk(KERN_DEBUG "bttv%d: irq loop=%d fc=%d "
+			       "riscs=%x, riscc=%08x, ",
+			       btv->nr, count, btv->field_count,
+			       stat>>28, btread(BT848_RISC_COUNT));
+			bttv_print_irqbits(stat,astat);
 			if (stat & BT848_INT_HLOCK)
 				printk("   HLOC => %s", (dstat & BT848_DSTATUS_HLOC)
 				       ? "yes" : "no");
@@ -2681,311 +3056,316 @@
 			printk("\n");
 		}
 
-		if (astat&BT848_INT_GPINT)
-			wake_up_interruptible(&btv->gpioq);
-
 		if (astat&BT848_INT_VSYNC) 
-                        btv->field++;
-
-		if (astat&(BT848_INT_SCERR|BT848_INT_OCERR)) {
-			if (bttv_verbose)
-				printk("bttv%d: irq:%s%s risc_count=%08x\n",
-				       btv->nr,
-				       (astat&BT848_INT_SCERR) ? " SCERR" : "",
-				       (astat&BT848_INT_OCERR) ? " OCERR" : "",
-				       btread(BT848_RISC_COUNT));
-			btv->errors++;
-			if (btv->errors < BTTV_ERRORS) {
-				spin_lock(&btv->s_lock);
-				btand(~15, BT848_GPIO_DMA_CTL);
-				btwrite(virt_to_bus(btv->risc_jmp+2),
-					BT848_RISC_STRT_ADD);
-				bt848_set_geo(btv,0);
-				bt848_set_risc_jmps(btv,-1);
-				spin_unlock(&btv->s_lock);
-			} else {
-				if (bttv_verbose)
-					printk("bttv%d: aiee: error loops\n",btv->nr);
-				bt848_offline(btv);
-			}
-		}
-		if (astat&BT848_INT_RISCI) 
-		{
-			if (bttv_debug > 1)
-				printk("bttv%d: IRQ_RISCI\n",btv->nr);
+                        btv->field_count++;
 
-			/* captured VBI frame */
-			if (stat&(1<<28)) 
-			{
-				btv->vbip=0;
-				/* inc vbi frame count for detecting drops */
-				(*(u32 *)&(btv->vbibuf[VBIBUF_SIZE - 4]))++;
-				wake_up_interruptible(&btv->vbiq);
-			}
+		if (astat & BT848_INT_GPINT)
+			wake_up(&btv->gpioq);
+		
+                if ((astat & BT848_INT_RISCI)  &&  (stat & (1<<28)))
+			bttv_irq_switch_fields(btv);
 
-			/* captured full frame */
-			if (stat&(2<<28) && btv->gq_grab != -1) 
-			{
-                                btv->last_field=btv->field;
-				if (bttv_debug)
-					printk("bttv%d: cap irq: done %d\n",btv->nr,btv->gq_grab);
-				do_gettimeofday(&btv->gbuf[btv->gq_grab].tv);
-				spin_lock(&btv->s_lock);
-				btv->gbuf[btv->gq_grab].stat = GBUFFER_DONE;
-				btv->gq_grab = -1;
-			        if (btv->gq_in != btv->gq_out)
-				{
-					btv->gq_grab = btv->gqueue[btv->gq_out++];
-					btv->gq_out  = btv->gq_out % MAX_GBUFFERS;
-					if (bttv_debug)
-						printk("bttv%d: cap irq: capture %d\n",btv->nr,btv->gq_grab);
-                                        btv->risc_cap_odd  = btv->gbuf[btv->gq_grab].ro;
-					btv->risc_cap_even = btv->gbuf[btv->gq_grab].re;
-					bt848_set_risc_jmps(btv,-1);
-					bt848_set_geo(btv,0);
-					btwrite(BT848_COLOR_CTL_GAMMA,
-						BT848_COLOR_CTL);
-				} else {
-                                        btv->risc_cap_odd  = 0;
-					btv->risc_cap_even = 0;
-					bt848_set_risc_jmps(btv,-1);
-                                        bt848_set_geo(btv,0);
-					btwrite(btv->fb_color_ctl | BT848_COLOR_CTL_GAMMA,
-						BT848_COLOR_CTL);
-				}
-				spin_unlock(&btv->s_lock);
-				wake_up_interruptible(&btv->capq);
-				break;
-			}
-			if (stat&(8<<28) && btv->gq_start) 
-			{
-				spin_lock(&btv->s_lock);
-				btv->gq_start = 0;
-				btv->gq_grab = btv->gqueue[btv->gq_out++];
-				btv->gq_out  = btv->gq_out % MAX_GBUFFERS;
-				if (bttv_debug)
-					printk("bttv%d: cap irq: capture %d [start]\n",btv->nr,btv->gq_grab);
-				btv->risc_cap_odd  = btv->gbuf[btv->gq_grab].ro;
-				btv->risc_cap_even = btv->gbuf[btv->gq_grab].re;
-				bt848_set_risc_jmps(btv,-1);
-				bt848_set_geo(btv,0);
-				btwrite(BT848_COLOR_CTL_GAMMA,
-					BT848_COLOR_CTL);
-				spin_unlock(&btv->s_lock);
-			}
+		if ((astat & BT848_INT_HLOCK)  &&  btv->opt_automute) {
+			if ((dstat & BT848_DSTATUS_HLOC) || btv->radio_user)
+				audio_mux(btv, AUDIO_UNMUTE);
+			else
+				audio_mux(btv, AUDIO_MUTE);
 		}
 
-		if (astat&BT848_INT_HLOCK) {
-			if ((dstat&BT848_DSTATUS_HLOC) || (btv->radio))
-				audio(btv, AUDIO_ON,0);
-			else
-				audio(btv, AUDIO_OFF,0);
+		if (astat & (BT848_INT_SCERR|BT848_INT_OCERR)) {
+			printk(KERN_INFO "bttv%d: %s%s @ %08x,",btv->nr,
+			       (astat & BT848_INT_SCERR) ? "SCERR" : "",
+			       (astat & BT848_INT_OCERR) ? "OCERR" : "",
+			       btread(BT848_RISC_COUNT));
+			bttv_print_irqbits(stat,astat);
+			printk("\n");
+			if (bttv_debug)
+				bttv_print_riscaddr(btv);
 		}
-    
+		if (fdsr && astat & BT848_INT_FDSR) {
+			printk(KERN_INFO "bttv%d: FDSR @ %08x\n",
+			       btv->nr,btread(BT848_RISC_COUNT));
+			if (bttv_debug)
+				bttv_print_riscaddr(btv);
+		}
+
 		count++;
 		if (count > 20) {
 			btwrite(0, BT848_INT_MASK);
 			printk(KERN_ERR 
 			       "bttv%d: IRQ lockup, cleared int mask\n", btv->nr);
-			bt848_offline(btv);
 		}
 	}
 }
 
 
+/* ----------------------------------------------------------------------- */
+/* initialitation                                                          */
 
-/*
- *	Scan for a Bt848 card, request the irq and map the io memory 
- */
-
-/* Can't be marked __devexit with a reference from bttv_probe.  */
-static void bttv_remove(struct pci_dev *pci_dev)
+/* register video4linux devices */
+static int __devinit bttv_register_video(struct bttv *btv)
 {
-        u8 command;
-        int j;
-        struct bttv *btv = pci_get_drvdata(pci_dev);
-
-	if (bttv_verbose)
-		printk("bttv%d: unloading\n",btv->nr);
-
-        /* unregister i2c_bus */
-	if (0 == btv->i2c_rc)
-		i2c_bit_del_bus(&btv->i2c_adap);
-
-        /* turn off all capturing, DMA and IRQs */
-        btand(~15, BT848_GPIO_DMA_CTL);
-
-        /* first disable interrupts before unmapping the memory! */
-        btwrite(0, BT848_INT_MASK);
-        btwrite(~0x0UL,BT848_INT_STAT);
-        btwrite(0x0, BT848_GPIO_OUT_EN);
-	if (bttv_gpio)
-		bttv_gpio_tracking(btv,"cleanup");
-
-        /* disable PCI bus-mastering */
-        pci_read_config_byte(btv->dev, PCI_COMMAND, &command);
-        command &= ~PCI_COMMAND_MASTER;
-        pci_write_config_byte(btv->dev, PCI_COMMAND, command);
-
-        /* unmap and free memory */
-        for (j = 0; j < gbuffers; j++)
-                if (btv->gbuf[j].risc)
-                        kfree(btv->gbuf[j].risc);
-        if (btv->gbuf)
-                kfree((void *) btv->gbuf);
-
-        if (btv->risc_scr_odd)
-                kfree((void *) btv->risc_scr_odd);
-
-        if (btv->risc_scr_even)
-                kfree((void *) btv->risc_scr_even);
-
-        DEBUG(printk(KERN_DEBUG "free: risc_jmp: 0x%p.\n", btv->risc_jmp));
-        if (btv->risc_jmp)
-                kfree((void *) btv->risc_jmp);
-
-        DEBUG(printk(KERN_DEBUG "bt848_vbibuf: 0x%p.\n", btv->vbibuf));
-        if (btv->vbibuf)
-                vfree((void *) btv->vbibuf);
-
-        free_irq(btv->irq,btv);
-        DEBUG(printk(KERN_DEBUG "bt848_mem: 0x%p.\n", btv->bt848_mem));
-        if (btv->bt848_mem)
-                iounmap(btv->bt848_mem);
+        if(video_register_device(&btv->video_dev,VFL_TYPE_GRABBER,video_nr)<0)
+                return -1;
+	printk(KERN_INFO "bttv%d: registered device video%d\n",
+	       btv->nr,btv->video_dev.minor & 0x1f);
 
-        if (btv->video_dev.minor!=-1)
+        if(video_register_device(&btv->vbi_dev,VFL_TYPE_VBI,vbi_nr)<0) {
                 video_unregister_device(&btv->video_dev);
-        if (btv->vbi_dev.minor!=-1)
-                video_unregister_device(&btv->vbi_dev);
-        if (btv->radio_dev.minor != -1)
-                video_unregister_device(&btv->radio_dev);
-
-        release_mem_region(pci_resource_start(btv->dev,0),
-                           pci_resource_len(btv->dev,0));
-        /* wake up any waiting processes
-           because shutdown flag is set, no new processes (in this queue)
-           are expected
-        */
-        btv->shutdown=1;
-        wake_up(&btv->gpioq);
+                return -1;
+        }
+	printk(KERN_INFO "bttv%d: registered device vbi%d\n",
+	       btv->nr,btv->vbi_dev.minor & 0x1f);
 
-	pci_set_drvdata(pci_dev, NULL);
-        return;
+        if (!btv->has_radio)
+		return 0;
+	if (video_register_device(&btv->radio_dev, VFL_TYPE_RADIO,radio_nr)<0) {
+		video_unregister_device(&btv->vbi_dev);
+		video_unregister_device(&btv->video_dev);
+		return -1;
+        }
+	printk(KERN_INFO "bttv%d: registered device radio%d\n",
+	       btv->nr,btv->radio_dev.minor & 0x1f);
+        return 0;
 }
 
 
-static int __devinit bttv_probe(struct pci_dev *dev, const struct pci_device_id *pci_id)
+/* on OpenFirmware machines (PowerMac at least), PCI memory cycle */
+/* response on cards with no firmware is not enabled by OF */
+static void pci_set_command(struct pci_dev *dev)
 {
-	int result;
-	unsigned char lat;
-	struct bttv *btv;
 #if defined(__powerpc__)
         unsigned int cmd;
+	
+        pci_read_config_dword(dev, PCI_COMMAND, &cmd);
+        cmd = (cmd | PCI_COMMAND_MEMORY ); 
+        pci_write_config_dword(dev, PCI_COMMAND, cmd);
 #endif
+}
 
-	printk(KERN_INFO "bttv: Bt8xx card found (%d).\n", bttv_num);
+static int __devinit bttv_probe(struct pci_dev *dev,
+				const struct pci_device_id *pci_id)
+{
+	int result;
+	unsigned char lat;
+	struct bttv *btv;
 
+	if (bttv_num == BTTV_MAX)
+		return -ENOMEM;
+	printk(KERN_INFO "bttv: Bt8xx card found (%d).\n", bttv_num);
         btv=&bttvs[bttv_num];
-        btv->dev=dev;
-        btv->nr = bttv_num;
-        btv->bt848_mem=NULL;
-        btv->vbibuf=NULL;
-        btv->risc_jmp=NULL;
-        btv->vbi_odd=NULL;
-        btv->vbi_even=NULL;
-        init_waitqueue_head(&btv->vbiq);
-        init_waitqueue_head(&btv->capq);
-        btv->vbip=VBIBUF_SIZE;
-	btv->s_lock = SPIN_LOCK_UNLOCKED;
-	init_waitqueue_head(&btv->gpioq);
-	btv->shutdown=0;
-	
-	memcpy(&btv->video_dev,&bttv_template, sizeof(bttv_template));
-	memcpy(&btv->vbi_dev,&vbi_template, sizeof(vbi_template));
-	memcpy(&btv->radio_dev,&radio_template,sizeof(radio_template));
-	
-        btv->id=dev->device;
-        btv->irq=dev->irq;
-	btv->bt848_adr=pci_resource_start(dev,0);
-	if (pci_enable_device(dev))
+	memset(btv,0,sizeof(*btv));
+	btv->nr  = bttv_num;
+	sprintf(btv->name,"bttv%d",btv->nr);
+
+	/* initialize structs / fill in defaults */
+        init_MUTEX(&btv->lock);
+        init_MUTEX(&btv->reslock);
+        btv->s_lock = SPIN_LOCK_UNLOCKED;
+        init_waitqueue_head(&btv->gpioq);
+        INIT_LIST_HEAD(&btv->capture);
+        INIT_LIST_HEAD(&btv->vcapture);
+
+        init_MUTEX(&btv->vbi.lock);
+	INIT_LIST_HEAD(&btv->vbi.stream);
+
+	btv->timeout.function = bttv_irq_timeout;
+	btv->timeout.data     = (unsigned long)btv;
+	
+        btv->i2c_rc = -1;
+        btv->tuner_type = -1;
+
+	memcpy(&btv->video_dev, &bttv_template,     sizeof(bttv_template));
+	memcpy(&btv->radio_dev, &radio_template,    sizeof(radio_template));
+	memcpy(&btv->vbi_dev,   &bttv_vbi_template, sizeof(bttv_vbi_template));
+        btv->video_dev.minor = -1;
+	btv->video_dev.priv = btv;
+        btv->radio_dev.minor = -1;
+	btv->radio_dev.priv = btv;
+        btv->vbi_dev.minor = -1;
+	btv->vbi_dev.priv = btv;
+	btv->has_radio=radio[btv->nr];
+	
+	/* pci stuff (init, get irq/mmip, ... */
+	btv->dev = dev;
+        btv->id  = dev->device;
+	if (pci_enable_device(dev)) {
+                printk(KERN_WARNING "bttv%d: Can't enable device.\n",
+		       btv->nr);
+		return -EIO;
+	}
+        if (pci_set_dma_mask(dev, 0xffffffff)) {
+                printk(KERN_WARNING "bttv%d: No suitable DMA available.\n",
+		       btv->nr);
 		return -EIO;
+        }
 	if (!request_mem_region(pci_resource_start(dev,0),
 				pci_resource_len(dev,0),
-				"bttv")) {
+				btv->name)) {
 		return -EBUSY;
 	}
-        if (btv->id >= 878)
-                btv->i2c_command = 0x83;                   
-        else
-                btv->i2c_command=(I2C_TIMING | BT848_I2C_SCL | BT848_I2C_SDA);
+        pci_set_master(dev);
+	pci_set_command(dev);
+	pci_set_drvdata(dev,btv);
+	if (!pci_dma_supported(dev,0xffffffff)) {
+		printk("bttv: Oops: no 32bit PCI DMA ???\n");
+		result = -EIO;
+		goto fail1;
+	}
 
+	if (-1 != latency) {
+		printk(KERN_INFO "bttv%d: setting pci latency timer to %d\n",
+		       bttv_num,latency);
+		pci_write_config_byte(dev, PCI_LATENCY_TIMER, latency);
+	}
         pci_read_config_byte(dev, PCI_CLASS_REVISION, &btv->revision);
         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
         printk(KERN_INFO "bttv%d: Bt%d (rev %d) at %02x:%02x.%x, ",
                bttv_num,btv->id, btv->revision, dev->bus->number,
 	       PCI_SLOT(dev->devfn),PCI_FUNC(dev->devfn));
-        printk("irq: %d, latency: %d, memory: 0x%lx\n",
-	       btv->irq, lat, btv->bt848_adr);
+        printk("irq: %d, latency: %d, mmio: 0x%lx\n",
+	       btv->dev->irq, lat, pci_resource_start(dev,0));
 	
-	bttv_idcard(btv);
-
-#if defined(__powerpc__)
-        /* on OpenFirmware machines (PowerMac at least), PCI memory cycle */
-        /* response on cards with no firmware is not enabled by OF */
-        pci_read_config_dword(dev, PCI_COMMAND, &cmd);
-        cmd = (cmd | PCI_COMMAND_MEMORY ); 
-        pci_write_config_dword(dev, PCI_COMMAND, cmd);
-#endif
-
 #ifdef __sparc__
-	btv->bt848_mem=(unsigned char *)btv->bt848_adr;
+	/* why no ioremap for sparc? */
+	btv->bt848_mmio=(unsigned char *)pci_resource_start(dev,0);
 #else
-	btv->bt848_mem=ioremap(btv->bt848_adr, 0x1000);
+	btv->bt848_mmio=ioremap(pci_resource_start(dev,0), 0x1000);
 #endif
-        
-        /* clear interrupt mask */
-	btwrite(0, BT848_INT_MASK);
 
-        result = request_irq(btv->irq, bttv_irq,
-                             SA_SHIRQ | SA_INTERRUPT,"bttv",(void *)btv);
-        if (result==-EINVAL) 
-        {
-                printk(KERN_ERR "bttv%d: Bad irq number or handler\n",
-                       bttv_num);
-		goto fail1;
-        }
-        if (result==-EBUSY)
-        {
-                printk(KERN_ERR "bttv%d: IRQ %d busy, change your PnP config in BIOS\n",bttv_num,btv->irq);
+        /* identify card */
+	bttv_idcard(btv);
+
+        /* disable irqs, register irq handler */
+	btwrite(0, BT848_INT_MASK);
+        result = request_irq(btv->dev->irq, bttv_irq,
+                             SA_SHIRQ | SA_INTERRUPT,btv->name,(void *)btv);
+        if (result < 0) {
+                printk(KERN_ERR "bttv%d: can't get IRQ %d\n",
+		       bttv_num,btv->dev->irq);
 		goto fail1;
         }
-        if (result < 0) 
-		goto fail1;
-        
+
 	if (0 != bttv_handle_chipset(btv)) {
-		result = -1;
+		result = -EIO;
 		goto fail2;
-	}
+        }
+
+	/* init options from insmod args */
+	btv->opt_combfilter = combfilter;
+	btv->opt_lumafilter = lumafilter;
+	btv->opt_automute   = automute;
+	btv->opt_chroma_agc = chroma_agc;
+	btv->opt_adc_crush  = adc_crush;
+	
+	/* fill struct bttv with some useful defaults */
+	btv->init.btv = btv;
+	btv->init.ov.width      = 320;
+	btv->init.ov.height     = 240;
+	btv->init.buf.fmt       = format_by_palette(VIDEO_PALETTE_RGB24);
+	btv->init.buf.vb.width  = 320;
+	btv->init.buf.vb.height = 240;
+	btv->input = 0;
+
+	/* initialize hardware */
+        if (bttv_gpio)
+                bttv_gpio_tracking(btv,"pre-init");
+
+	bttv_risc_init_main(btv);
+	init_bt848(btv);
+
+	/* gpio */
+        btwrite(0x00, BT848_GPIO_REG_INP);
+        btwrite(0x00, BT848_GPIO_OUT_EN);
+        if (bttv_gpio)
+                bttv_gpio_tracking(btv,"init");
+
+        /* interrupt */
+        btwrite(0xfffffUL, BT848_INT_STAT);
+        btwrite((btv->triton1) |
+                BT848_INT_GPINT|
+                BT848_INT_SCERR|
+                (fdsr ? BT848_INT_FDSR : 0) |
+                BT848_INT_RISCI|BT848_INT_OCERR|BT848_INT_VPRES|
+                BT848_INT_FMTCHG|BT848_INT_HLOCK,
+                BT848_INT_MASK);
 	
-        pci_set_master(dev);
-	pci_set_drvdata(dev,btv);
+        /* needs to be done before i2c is registered */
+        bttv_init_card1(btv);
 
-	if(init_bt848(btv) < 0) {
-		bttv_remove(dev);
-		return -EIO;
-	}
-	bttv_num++;
+        /* register i2c */
+        init_bttv_i2c(btv);
 
+        /* some card-specific stuff (needs working i2c) */
+        bttv_init_card2(btv);
+
+        /* register video4linux */
+        bttv_register_video(btv);
+
+	bt848_bright(btv,32768);
+	bt848_contrast(btv,32768);
+	bt848_hue(btv,32768);
+	bt848_sat(btv,32768);
+	audio_mux(btv,AUDIO_MUTE);
+	set_input(btv,0);
+
+	/* everything is fine */
+	bttv_num++;
         return 0;
 
  fail2:
-        free_irq(btv->irq,btv);
+        free_irq(btv->dev->irq,btv);
+	
  fail1:
 	release_mem_region(pci_resource_start(btv->dev,0),
 			   pci_resource_len(btv->dev,0));
+	pci_set_drvdata(dev,NULL);
 	return result;
 }
 
+static void __devexit bttv_remove(struct pci_dev *pci_dev)
+{
+        struct bttv *btv = pci_get_drvdata(pci_dev);
+
+	if (bttv_verbose)
+		printk("bttv%d: unloading\n",btv->nr);
+
+        /* shutdown everything (DMA+IRQs) */
+	btand(~15, BT848_GPIO_DMA_CTL);
+	btwrite(0, BT848_INT_MASK);
+	btwrite(~0x0UL,BT848_INT_STAT);
+	btwrite(0x0, BT848_GPIO_OUT_EN);
+	if (bttv_gpio)
+		bttv_gpio_tracking(btv,"cleanup");
+
+	/* tell gpio modules we are leaving ... */
+	btv->shutdown=1;
+	wake_up(&btv->gpioq);
+
+        /* unregister i2c_bus */
+	if (0 == btv->i2c_rc)
+		i2c_bit_del_bus(&btv->i2c_adap);
+
+	/* unregister video4linux */
+        if (btv->video_dev.minor!=-1)
+                video_unregister_device(&btv->video_dev);
+        if (btv->radio_dev.minor!=-1)
+                video_unregister_device(&btv->radio_dev);
+	if (btv->vbi_dev.minor!=-1)
+                video_unregister_device(&btv->vbi_dev);
+
+	/* free allocated memory */
+	bttv_riscmem_free(btv->dev,&btv->main);
+
+	/* free ressources */
+        free_irq(btv->dev->irq,btv);
+        release_mem_region(pci_resource_start(btv->dev,0),
+                           pci_resource_len(btv->dev,0));
+
+	pci_set_drvdata(pci_dev, NULL);
+        return;
+}
+
 static struct pci_device_id bttv_pci_tbl[] __devinitdata = {
         {PCI_VENDOR_ID_BROOKTREE, PCI_DEVICE_ID_BT848,
          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
@@ -3007,28 +3387,30 @@
         remove:   bttv_remove,
 };
 
-int bttv_init_module(void)
+static int bttv_init_module(void)
 {
 	bttv_num = 0;
 
-	printk(KERN_INFO "bttv: driver version %d.%d.%d loaded\n",
+	printk(KERN_INFO "bttv: driver version %d.%d.%d loaded "
+	       BTTV_APIS "\n",
 	       (BTTV_VERSION_CODE >> 16) & 0xff,
 	       (BTTV_VERSION_CODE >> 8) & 0xff,
 	       BTTV_VERSION_CODE & 0xff);
-	if (gbuffers < 2 || gbuffers > MAX_GBUFFERS)
+	if (gbuffers < 2 || gbuffers > VIDEO_MAX_FRAME)
 		gbuffers = 2;
 	if (gbufsize < 0 || gbufsize > BTTV_MAX_FBUF)
 		gbufsize = BTTV_MAX_FBUF;
+	gbufsize = (gbufsize + PAGE_SIZE - 1) & PAGE_MASK;
 	if (bttv_verbose)
-		printk(KERN_INFO "bttv: using %d buffers with %dk (%dk total) for capture\n",
-		       gbuffers,gbufsize/1024,gbuffers*gbufsize/1024);
+		printk(KERN_INFO "bttv: using %d buffers with %dk (%d pages) each for capture\n",
+		       gbuffers, gbufsize >> 10, gbufsize >> PAGE_SHIFT);
 
 	bttv_check_chipset();
 
 	return pci_module_init(&bttv_pci_driver);
 }
 
-void bttv_cleanup_module(void)
+static void bttv_cleanup_module(void)
 {
 	pci_unregister_driver(&bttv_pci_driver);
 	return;
diff -Nru a/drivers/media/video/bttv-risc.c b/drivers/media/video/bttv-risc.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/media/video/bttv-risc.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,861 @@
+/*
+    bttv-risc.c  --  interfaces to other kernel modules
+
+    bttv risc code handling
+	- memory management
+	- generation
+
+    (c) 2000 Gerd Knorr <kraxel@goldbach.in-berlin.de>
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+*/
+
+#define __NO_VERSION__ 1
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/iobuf.h>
+#include <linux/vmalloc.h>
+#include <linux/interrupt.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include "bttvp.h"
+
+/* ---------------------------------------------------------- */
+/* allocate/free risc memory                                  */
+
+int  bttv_riscmem_alloc(struct pci_dev *pci,
+			struct bttv_riscmem *risc,
+			unsigned int size)
+{
+	unsigned long  *cpu;
+	dma_addr_t     dma;
+	
+	cpu = pci_alloc_consistent(pci, size, &dma);
+	if (NULL == cpu)
+		return -ENOMEM;
+	memset(cpu,0,size);
+
+	if (risc->cpu && risc->size < size) {
+		/* realloc (enlarge buffer) -- copy old stuff */
+		memcpy(cpu,risc->cpu,risc->size);
+		bttv_riscmem_free(pci,risc);
+	}
+	risc->cpu  = cpu;
+	risc->dma  = dma;
+	risc->size = size;
+
+	return 0;
+}
+
+void bttv_riscmem_free(struct pci_dev *pci,
+		       struct bttv_riscmem *risc)
+{
+	if (NULL == risc->cpu)
+		return;
+	pci_free_consistent(pci, risc->size, risc->cpu, risc->dma);
+	memset(risc,0,sizeof(*risc));
+}
+
+/* ---------------------------------------------------------- */
+/* risc code generators                                       */
+
+int
+bttv_risc_packed(struct bttv *btv, struct bttv_riscmem *risc,
+		 struct scatterlist *sglist,
+		 int offset, int bpl, int padding, int lines)
+{
+	int instructions,rc,line,todo;
+	struct scatterlist *sg;
+	unsigned long *rp;
+
+	/* estimate risc mem: worst case is one write per page border +
+	   one write per scan line + sync + jump (all 2 dwords) */
+	instructions  = (bpl * lines) / PAGE_SIZE + lines;
+	instructions += 2;
+	if ((rc = bttv_riscmem_alloc(btv->dev,risc,instructions*8)) < 0)
+		return rc;
+
+	/* sync instruction */
+	rp = risc->cpu;
+	*(rp++) = cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1);
+	*(rp++) = cpu_to_le32(0);
+
+	/* scan lines */
+	sg = sglist;
+	for (line = 0; line < lines; line++) {
+		while (offset >= sg_dma_len(sg)) {
+			offset -= sg_dma_len(sg);
+			sg++;
+		}
+		if (bpl <= sg_dma_len(sg)-offset) {
+			/* fits into current chunk */
+                        *(rp++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_SOL|
+					    BT848_RISC_EOL|bpl);
+                        *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
+                        offset+=bpl;
+		} else {
+			/* scanline needs to be splitted */
+                        todo = bpl;
+                        *(rp++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_SOL|
+					    (sg_dma_len(sg)-offset));
+                        *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
+                        todo -= (sg_dma_len(sg)-offset);
+                        offset = 0;
+                        sg++;
+                        while (todo > sg_dma_len(sg)) {
+                                *(rp++)=cpu_to_le32(BT848_RISC_WRITE|
+						    sg_dma_len(sg));
+                                *(rp++)=cpu_to_le32(sg_dma_address(sg));
+				todo -= sg_dma_len(sg);
+				sg++;
+			}
+                        *(rp++)=cpu_to_le32(BT848_RISC_WRITE|BT848_RISC_EOL|
+					    todo);
+			*(rp++)=cpu_to_le32(sg_dma_address(sg));
+			offset += todo;
+		}
+		offset += padding;
+	}
+
+	/* save pointer to jmp instruction address */
+	risc->jmp = rp;
+	return 0;
+}
+
+int
+bttv_risc_planar(struct bttv *btv, struct bttv_riscmem *risc,
+		 struct scatterlist *sglist,
+		 int yoffset, int ybpl, int ypadding, int ylines,
+		 int uoffset, int voffset, int hshift, int vshift,
+		 int cpadding)
+{
+	int instructions,rc,line,todo,ylen,chroma;
+	unsigned long *rp,ri;
+	struct scatterlist *ysg;
+	struct scatterlist *usg;
+	struct scatterlist *vsg;
+
+	/* estimate risc mem: worst case is one write per page border +
+	   one write per scan line (5 dwords)
+	   plus sync + jump (2 dwords) */
+	instructions  = (ybpl * ylines * 2) / PAGE_SIZE + ylines;
+	instructions += 2;
+	if ((rc = bttv_riscmem_alloc(btv->dev,risc,instructions*4*5)) < 0)
+		return rc;
+
+	/* sync instruction */
+	rp = risc->cpu;
+	*(rp++) = cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM3);
+	*(rp++) = cpu_to_le32(0);
+
+	/* scan lines */
+	ysg = sglist;
+	usg = sglist;
+	vsg = sglist;
+	for (line = 0; line < ylines; line++) {
+		switch (vshift) {
+		case 0:  chroma = 1;           break;
+		case 1:  chroma = !(line & 1); break;
+		case 2:  chroma = !(line & 3); break;
+		default: chroma = 0;
+		}
+		for (todo = ybpl; todo > 0; todo -= ylen) {
+			/* go to next sg entry if needed */
+			while (yoffset >= sg_dma_len(ysg)) {
+				yoffset -= sg_dma_len(ysg);
+				ysg++;
+			}
+			while (uoffset >= sg_dma_len(usg)) {
+				uoffset -= sg_dma_len(usg);
+				usg++;
+			}
+			while (voffset >= sg_dma_len(vsg)) {
+				voffset -= sg_dma_len(vsg);
+				vsg++;
+			}
+
+			/* calculate max number of bytes we can write */
+			ylen = todo;
+			if (yoffset + ylen > sg_dma_len(ysg))
+				ylen = sg_dma_len(ysg) - yoffset;
+			if (chroma) {
+				if (uoffset + (ylen>>hshift) > sg_dma_len(usg))
+					ylen = (sg_dma_len(usg) - uoffset) << hshift;
+				if (voffset + (ylen>>hshift) > sg_dma_len(vsg))
+					ylen = (sg_dma_len(vsg) - voffset) << hshift;
+				ri = BT848_RISC_WRITE123;
+			} else {
+				ri = BT848_RISC_WRITE1S23;
+			}
+			if (ybpl == todo)
+				ri |= BT848_RISC_SOL;
+			if (ylen == todo)
+				ri |= BT848_RISC_EOL;
+
+			/* write risc instruction */
+                        *(rp++)=cpu_to_le32(ri | ylen);
+                        *(rp++)=cpu_to_le32(((ylen >> hshift) << 16) |
+					    (ylen >> hshift));
+			*(rp++)=cpu_to_le32(sg_dma_address(ysg)+yoffset);
+			yoffset += ylen;
+			if (chroma) {
+				*(rp++)=cpu_to_le32(sg_dma_address(usg)+uoffset);
+				uoffset += ylen >> hshift;
+				*(rp++)=cpu_to_le32(sg_dma_address(vsg)+voffset);
+				voffset += ylen >> hshift;
+			}
+		}
+		yoffset += ypadding;
+		if (chroma) {
+			uoffset += cpadding;
+			voffset += cpadding;
+		}
+	}
+
+	/* save pointer to jmp instruction address */
+	risc->jmp = rp;
+	return 0;
+}
+
+/* ---------------------------------------------------------- */
+
+struct SKIPLIST {
+	int start;
+	int end;
+};
+
+int
+bttv_screen_clips(struct video_buffer *fbuf,
+		  int x, int y, int width, int height,
+		  struct video_clip *clips, int n)
+{
+	if (x < 0) {
+		/* left */
+		clips[n].x = 0;
+		clips[n].y = 0;
+		clips[n].width  = -x;
+		clips[n].height = height;
+		n++;
+	}
+	if (x+width > fbuf->width) {
+		/* right */
+		clips[n].x = fbuf->width - x;
+		clips[n].y = 0;
+		clips[n].width  = width - clips[n].x;
+		clips[n].height = height;
+		n++;
+	}
+	if (y < 0) {
+		/* top */
+		clips[n].x = 0;
+		clips[n].y = 0;
+		clips[n].width  = width;
+		clips[n].height = -y;
+		n++;
+	}
+	if (y+height > fbuf->height) {
+		/* bottom */
+		clips[n].x = 0;
+		clips[n].y = fbuf->height - y;
+		clips[n].width  = width;
+		clips[n].height = height - clips[n].y;
+		n++;
+	}
+	return n;
+}
+
+void
+bttv_sort_clips(struct video_clip *clips, int nclips)
+{
+	struct video_clip swap;
+	int i,j,n;
+
+	for (i = nclips-2; i >= 0; i--) {
+		for (n = 0, j = 0; j <= i; j++) {
+			if (clips[j].x > clips[j+1].x) {
+				swap = clips[j];
+				clips[j] = clips[j+1];
+				clips[j+1] = swap;
+				n++;
+			}
+		}
+		if (0 == n)
+			break;
+	}
+}
+
+static void
+calc_skips(int line, int width, int *maxy,
+	   struct SKIPLIST *skips, int *nskips,
+	   const struct video_clip *clips, int nclips)
+{
+	int clip,skip,maxline,end;
+
+	skip=0;
+	maxline = 9999;
+	for (clip = 0; clip < nclips; clip++) {
+
+		/* sanity checks */
+		if (clips[clip].x + clips[clip].width <= 0)
+			continue;
+		if (clips[clip].x > width)
+			break;
+		
+		/* vertical range */
+		if (line > clips[clip].y+clips[clip].height-1)
+			continue;
+		if (line < clips[clip].y) {
+			if (maxline > clips[clip].y-1)
+				maxline = clips[clip].y-1;
+			continue;
+		}
+		if (maxline > clips[clip].y+clips[clip].height-1)
+			maxline = clips[clip].y+clips[clip].height-1;
+
+		/* horizontal range */
+		if (0 == skip || clips[clip].x > skips[skip-1].end) {
+			/* new one */
+			skips[skip].start = clips[clip].x;
+			if (skips[skip].start < 0)
+				skips[skip].start = 0;
+			skips[skip].end = clips[clip].x + clips[clip].width;
+			if (skips[skip].end > width)
+				skips[skip].end = width;
+			skip++;
+		} else {
+			/* overlaps -- expand last one */
+			end = clips[clip].x + clips[clip].width;
+			if (skips[skip-1].end < end)
+				skips[skip-1].end = end;
+			if (skips[skip-1].end > width)
+				skips[skip-1].end = width;
+		}
+	}
+	*nskips = skip;
+	*maxy = maxline;
+
+	if (bttv_debug) {
+		printk(KERN_DEBUG "bttv: skips line %d-%d:",line,maxline);
+		for (skip = 0; skip < *nskips; skip++) {
+			printk(" %d-%d",skips[skip].start,skips[skip].end);
+		}
+		printk("\n");
+	}
+}
+
+int
+bttv_risc_overlay(struct bttv *btv, struct bttv_riscmem *risc,
+		  const struct bttv_format *fmt, struct bttv_overlay *ov,
+		  int fields)
+{
+	int instructions,rc,line,maxy,start,end,skip,nskips;
+	struct SKIPLIST *skips;
+	unsigned long *rp,ri,ra;
+	unsigned long addr;
+
+	/* skip list for window clipping */
+	if (NULL == (skips = kmalloc(sizeof(*skips) * ov->nclips,GFP_KERNEL)))
+		return -ENOMEM;
+	
+	/* estimate risc mem: worst case is (clip+1) * lines instructions
+	   + sync + jump (all 2 dwords) */
+	instructions  = (ov->nclips + 1) *
+		((fields & VBUF_FIELD_INTER) ? ov->height>>1 :  ov->height);
+	instructions += 2;
+	if ((rc = bttv_riscmem_alloc(btv->dev,risc,instructions*8)) < 0)
+		return rc;
+
+	/* sync instruction */
+	rp = risc->cpu;
+	*(rp++) = cpu_to_le32(BT848_RISC_SYNC|BT848_FIFO_STATUS_FM1);
+	*(rp++) = cpu_to_le32(0);
+
+	addr  = (unsigned long)btv->fbuf.base;
+	addr += btv->fbuf.bytesperline * ov->y;
+	addr += ((btv->fbuf.depth+7) >> 3) * ov->x;
+
+	/* scan lines */
+	for (maxy = -1, line = 0; line < ov->height;
+	     line++, addr += btv->fbuf.bytesperline) {
+		if (fields & VBUF_FIELD_INTER) {
+			if ((line%2) != 0 && (fields & VBUF_FIELD_ODD))
+				continue;
+			if ((line%2) != 1 && (fields & VBUF_FIELD_EVEN))
+				continue;
+		}
+
+		/* calculate clipping */
+		if (line > maxy)
+			calc_skips(line, ov->width, &maxy,
+				   skips, &nskips, ov->clips, ov->nclips);
+
+		/* write out risc code */
+		for (start = 0, skip = 0; start < ov->width; start = end) {
+			if (skip >= nskips) {
+				ri  = BT848_RISC_WRITE;
+				end = ov->width;
+			} else if (start < skips[skip].start) {
+				ri  = BT848_RISC_WRITE;
+				end = skips[skip].start;
+			} else {
+				ri  = BT848_RISC_SKIP;
+				end = skips[skip].end;
+				skip++;
+			}
+			if (BT848_RISC_WRITE == ri)
+				ra = addr + (fmt->depth>>3)*start;
+			else
+				ra = 0;
+				
+			if (0 == start)
+				ri |= BT848_RISC_SOL;
+			if (ov->width == end)
+				ri |= BT848_RISC_EOL;
+			ri |= (fmt->depth>>3) * (end-start);
+
+			*(rp++)=cpu_to_le32(ri);
+			if (0 != ra)
+				*(rp++)=cpu_to_le32(ra);
+		}
+	}
+
+	/* save pointer to jmp instruction address */
+	risc->jmp = rp;
+
+	kfree(skips);
+	return 0;
+}
+
+/* ---------------------------------------------------------- */
+
+void
+bttv_calc_geo(struct bttv *btv, struct bttv_geometry *geo,
+	      int width, int height, int interleaved, int norm)
+{
+	const struct bttv_tvnorm *tvnorm;
+        u32 xsf, sr;
+	int vdelay;
+
+	tvnorm = &bttv_tvnorms[norm];
+	vdelay = tvnorm->vdelay;
+	if (vdelay < btv->vbi.lines*2)
+		vdelay = btv->vbi.lines*2;
+
+        xsf = (width*tvnorm->scaledtwidth)/tvnorm->swidth;
+        geo->hscale =  ((tvnorm->totalwidth*4096UL)/xsf-4096);
+        geo->hdelay =  tvnorm->hdelayx1;
+        geo->hdelay =  (geo->hdelay*width)/tvnorm->swidth;
+        geo->hdelay &= 0x3fe;
+        sr = ((tvnorm->sheight >> (interleaved?0:1))*512)/height - 512;
+        geo->vscale =  (0x10000UL-sr) & 0x1fff;
+        geo->crop   =  ((width>>8)&0x03) | ((geo->hdelay>>6)&0x0c) |
+                ((tvnorm->sheight>>4)&0x30) | ((vdelay>>2)&0xc0);
+        geo->vscale |= interleaved ? (BT848_VSCALE_INT<<8) : 0;
+        geo->vdelay  =  vdelay;
+        geo->width   =  width;
+        geo->sheight =  tvnorm->sheight;
+
+        if (btv->opt_combfilter) {
+                geo->vtc  = (width < 193) ? 2 : ((width < 385) ? 1 : 0);
+                geo->comb = (width < 769) ? 1 : 0;
+        } else {
+                geo->vtc  = 0;
+                geo->comb = 0;
+        }
+}
+
+void
+bttv_apply_geo(struct bttv *btv, struct bttv_geometry *geo, int odd)
+{
+        int off = odd ? 0x80 : 0x00;
+
+	if (geo->comb)
+		btor(BT848_VSCALE_COMB, BT848_E_VSCALE_HI+off);
+	else
+		btand(~BT848_VSCALE_COMB, BT848_E_VSCALE_HI+off);
+
+        btwrite(geo->vtc,             BT848_E_VTC+off);
+        btwrite(geo->hscale >> 8,     BT848_E_HSCALE_HI+off);
+        btwrite(geo->hscale & 0xff,   BT848_E_HSCALE_LO+off);
+        btaor((geo->vscale>>8), 0xe0, BT848_E_VSCALE_HI+off);
+        btwrite(geo->vscale & 0xff,   BT848_E_VSCALE_LO+off);
+        btwrite(geo->width & 0xff,    BT848_E_HACTIVE_LO+off);
+        btwrite(geo->hdelay & 0xff,   BT848_E_HDELAY_LO+off);
+        btwrite(geo->sheight & 0xff,  BT848_E_VACTIVE_LO+off);
+        btwrite(geo->vdelay & 0xff,   BT848_E_VDELAY_LO+off);
+        btwrite(geo->crop,            BT848_E_CROP+off);
+}
+
+/* ---------------------------------------------------------- */
+/* risc group / risc main loop / dma management               */
+
+void
+bttv_set_dma(struct bttv *btv, int override, int irqflags)
+{
+	unsigned long cmd;
+	int capctl;
+
+	btv->cap_ctl = 0;
+	if (NULL != btv->odd)      btv->cap_ctl |= 0x02;
+	if (NULL != btv->even)     btv->cap_ctl |= 0x01;
+	if (NULL != btv->vcurr)    btv->cap_ctl |= 0x0c;
+
+	capctl  = 0;
+	capctl |= (btv->cap_ctl & 0x03) ? 0x03 : 0x00;  /* capture  */
+	capctl |= (btv->cap_ctl & 0x0c) ? 0x0c : 0x00;  /* vbi data */
+	capctl |= override;
+
+	d2printk(KERN_DEBUG
+		 "bttv%d: capctl=%x irq=%d odd=%08Lx/%08Lx even=%08Lx/%08Lx\n",
+		 btv->nr,capctl,irqflags,
+		 btv->vcurr ? (u64)btv->vcurr->odd.dma  : 0,
+		 btv->odd   ? (u64)btv->odd->odd.dma    : 0,
+		 btv->vcurr ? (u64)btv->vcurr->even.dma : 0,
+		 btv->even  ? (u64)btv->even->even.dma  : 0);
+	
+	cmd = BT848_RISC_JUMP;
+	if (irqflags) {
+		cmd |= BT848_RISC_IRQ | (irqflags << 16);
+		mod_timer(&btv->timeout, jiffies+BTTV_TIMEOUT);
+	} else {
+		del_timer(&btv->timeout);
+	}
+        btv->main.cpu[RISC_SLOT_LOOP] = cpu_to_le32(cmd);
+	
+	btaor(capctl, ~0x0f, BT848_CAP_CTL);
+	if (capctl) {
+		if (btv->dma_on)
+			return;
+		btwrite(btv->main.dma, BT848_RISC_STRT_ADD);
+		btor(3, BT848_GPIO_DMA_CTL);
+		btv->dma_on = 1;
+	} else {
+		if (!btv->dma_on)
+			return;
+                btand(~3, BT848_GPIO_DMA_CTL);
+		btv->dma_on = 0;
+	}
+	return;
+}
+
+int
+bttv_risc_init_main(struct bttv *btv)
+{
+	int rc;
+	
+	if ((rc = bttv_riscmem_alloc(btv->dev,&btv->main,PAGE_SIZE)) < 0)
+		return rc;
+	dprintk(KERN_DEBUG "bttv%d: risc main @ %08Lx\n",
+		btv->nr,(u64)btv->main.dma);
+
+	btv->main.cpu[0] = cpu_to_le32(BT848_RISC_SYNC | BT848_RISC_RESYNC |
+				       BT848_FIFO_STATUS_VRE);
+	btv->main.cpu[1] = cpu_to_le32(0);
+	btv->main.cpu[2] = cpu_to_le32(BT848_RISC_JUMP);
+	btv->main.cpu[3] = cpu_to_le32(btv->main.dma + (4<<2));
+
+	/* odd field */
+	btv->main.cpu[4] = cpu_to_le32(BT848_RISC_JUMP);
+	btv->main.cpu[5] = cpu_to_le32(btv->main.dma + (6<<2));
+	btv->main.cpu[6] = cpu_to_le32(BT848_RISC_JUMP);
+	btv->main.cpu[7] = cpu_to_le32(btv->main.dma + (8<<2));
+
+        btv->main.cpu[8] = cpu_to_le32(BT848_RISC_SYNC | BT848_RISC_RESYNC |
+				       BT848_FIFO_STATUS_VRO);
+        btv->main.cpu[9] = cpu_to_le32(0);
+
+	/* even field */
+        btv->main.cpu[10] = cpu_to_le32(BT848_RISC_JUMP);
+	btv->main.cpu[11] = cpu_to_le32(btv->main.dma + (12<<2));
+        btv->main.cpu[12] = cpu_to_le32(BT848_RISC_JUMP);
+	btv->main.cpu[13] = cpu_to_le32(btv->main.dma + (14<<2));
+
+	/* jump back to odd field */
+	btv->main.cpu[14] = cpu_to_le32(BT848_RISC_JUMP);
+        btv->main.cpu[15] = cpu_to_le32(btv->main.dma + (0<<2));
+
+	return 0;
+}
+
+int
+bttv_risc_hook(struct bttv *btv, int slot, struct bttv_riscmem *risc,
+	       int irqflags)
+{
+	unsigned long cmd;
+	unsigned long next = btv->main.dma + ((slot+2) << 2);
+
+	if (NULL == risc) {
+		d2printk(KERN_DEBUG "bttv%d: risc=%p slot[%d]=NULL\n",
+			 btv->nr,risc,slot);
+		btv->main.cpu[slot+1] = cpu_to_le32(next);
+	} else {
+		d2printk(KERN_DEBUG "bttv%d: risc=%p slot[%d]=%08Lx irq=%d\n",
+			 btv->nr,risc,slot,(u64)risc->dma,irqflags);
+		cmd = BT848_RISC_JUMP;
+		if (irqflags)
+			cmd |= BT848_RISC_IRQ | (irqflags << 16);
+		risc->jmp[0] = cpu_to_le32(cmd);
+		risc->jmp[1] = cpu_to_le32(next);
+		btv->main.cpu[slot+1] = cpu_to_le32(risc->dma);
+	}
+	return 0;
+}
+
+void
+bttv_dma_free(struct bttv *btv, struct bttv_buffer *buf)
+{
+	if (in_interrupt())
+		BUG();
+	videobuf_waiton(&buf->vb,0,0);
+	videobuf_dma_pci_unmap(btv->dev, &buf->vb.dma);
+	videobuf_dma_free(&buf->vb.dma);
+	bttv_riscmem_free(btv->dev,&buf->even);
+	bttv_riscmem_free(btv->dev,&buf->odd);
+	buf->vb.state = STATE_NEEDS_INIT;
+}
+
+int
+bttv_buffer_activate(struct bttv *btv,
+		     struct bttv_buffer *odd,
+		     struct bttv_buffer *even)
+{
+	if (NULL != odd  &&  NULL != even) {
+		odd->vb.state  = STATE_ACTIVE;
+		even->vb.state = STATE_ACTIVE;
+		bttv_apply_geo(btv, &odd->geo, 1);
+		bttv_apply_geo(btv, &even->geo,0);
+		bttv_risc_hook(btv, RISC_SLOT_O_FIELD, &odd->odd,   0);
+		bttv_risc_hook(btv, RISC_SLOT_E_FIELD, &even->even, 0);
+		btaor((odd->btformat & 0xf0) | (even->btformat & 0x0f),
+		      ~0xff, BT848_COLOR_FMT);
+		btaor((odd->btswap & 0x0a) | (even->btswap & 0x05),
+		      ~0x0f, BT848_COLOR_CTL);
+	} else if (NULL != odd) {
+		odd->vb.state  = STATE_ACTIVE;
+		bttv_apply_geo(btv, &odd->geo,1);
+		bttv_apply_geo(btv, &odd->geo,0);
+		bttv_risc_hook(btv, RISC_SLOT_O_FIELD, &odd->odd, 0);
+		bttv_risc_hook(btv, RISC_SLOT_E_FIELD, NULL,      0);
+		btaor(odd->btformat & 0xff, ~0xff, BT848_COLOR_FMT);
+		btaor(odd->btswap & 0x0f,   ~0x0f, BT848_COLOR_CTL);
+	} else if (NULL != even) {
+		even->vb.state = STATE_ACTIVE;
+		bttv_apply_geo(btv, &even->geo,1);
+		bttv_apply_geo(btv, &even->geo,0);
+		bttv_risc_hook(btv, RISC_SLOT_O_FIELD, NULL,        0);
+		bttv_risc_hook(btv, RISC_SLOT_E_FIELD, &even->even, 0);
+		btaor(even->btformat & 0xff, ~0xff, BT848_COLOR_FMT);
+		btaor(even->btswap & 0x0f,   ~0x0f, BT848_COLOR_CTL);
+	} else {
+		bttv_risc_hook(btv, RISC_SLOT_O_FIELD, NULL, 0);
+		bttv_risc_hook(btv, RISC_SLOT_E_FIELD, NULL, 0);
+	}
+	return 0;
+}
+
+/* ---------------------------------------------------------- */
+
+int
+bttv_buffer_field(struct bttv *btv, int field, int def_field,
+		  int norm, int height)
+{
+	const struct bttv_tvnorm *tvnorm = bttv_tvnorms + norm;
+
+	/* check interleave, even+odd fields */
+	if (height > (tvnorm->sheight >> 1)) {
+		field = VBUF_FIELD_ODD | VBUF_FIELD_EVEN | VBUF_FIELD_INTER;
+	} else {
+		if (field & def_field) {
+			field = def_field;
+		} else {
+			field = (def_field & VBUF_FIELD_EVEN)
+				? VBUF_FIELD_ODD : VBUF_FIELD_EVEN;
+		}
+	}
+	return field;
+}
+
+/* calculate geometry, build risc code */
+int
+bttv_buffer_risc(struct bttv *btv, struct bttv_buffer *buf)
+{
+	const struct bttv_tvnorm *tvnorm = bttv_tvnorms + buf->tvnorm;
+
+	buf->vb.field = bttv_buffer_field(btv,buf->vb.field, VBUF_FIELD_EVEN,
+					  buf->tvnorm,buf->vb.height);
+	dprintk(KERN_DEBUG
+		"bttv%d: buffer flags:%s%s%s format: %s size: %dx%d\n",
+		btv->nr,
+		(buf->vb.field & VBUF_FIELD_INTER) ? " interleave" : "",
+		(buf->vb.field & VBUF_FIELD_ODD)   ? " odd"        : "",
+		(buf->vb.field & VBUF_FIELD_EVEN)  ? " even"       : "",
+		buf->fmt->name,buf->vb.width,buf->vb.height);
+
+	/* packed pixel modes */
+	if (buf->fmt->flags & FORMAT_FLAGS_PACKED) {
+		int bpl, padding, lines;
+		bpl = (buf->fmt->depth >> 3) * buf->vb.width;
+
+		/* calculate geometry */
+		if (buf->vb.field & VBUF_FIELD_INTER) {
+			bttv_calc_geo(btv,&buf->geo,buf->vb.width,
+				      buf->vb.height,1,buf->tvnorm);
+			lines   = buf->vb.height >> 1;
+			padding = bpl;
+		} else {
+			bttv_calc_geo(btv,&buf->geo,buf->vb.width,
+				      buf->vb.height,0,buf->tvnorm);
+			lines   = buf->vb.height;
+			padding = 0;
+		}
+		
+		/* build risc code */
+		if (buf->vb.field & VBUF_FIELD_ODD)
+			bttv_risc_packed(btv,&buf->odd,buf->vb.dma.sglist,
+					 0,bpl,padding,lines);
+		if (buf->vb.field & VBUF_FIELD_EVEN)
+			bttv_risc_packed(btv,&buf->even,buf->vb.dma.sglist,
+					 padding,bpl,padding,lines);
+	}
+
+	/* planar modes */
+	if (buf->fmt->flags & FORMAT_FLAGS_PLANAR) {
+		struct bttv_riscmem *risc;
+		int uoffset, voffset;
+		int ypadding, cpadding, lines;
+
+		/* calculate chroma offsets */
+		uoffset = buf->vb.width * buf->vb.height;
+		voffset = buf->vb.width * buf->vb.height;
+		if (buf->fmt->flags & FORMAT_FLAGS_CrCb) {
+			/* Y-Cr-Cb plane order */
+			uoffset >>= buf->fmt->hshift;
+			uoffset >>= buf->fmt->vshift;
+			uoffset += voffset;
+		} else {
+			/* Y-Cb-Cr plane order */
+			voffset >>= buf->fmt->hshift;
+			voffset >>= buf->fmt->vshift;
+			voffset += uoffset;
+		}
+
+		if (buf->vb.field & VBUF_FIELD_INTER) {
+			bttv_calc_geo(btv,&buf->geo,buf->vb.width,
+				      buf->vb.height,1,buf->tvnorm);
+			lines     = buf->vb.height >> 1;
+			ypadding  = buf->vb.width;
+			if (!buf->fmt->vshift) {
+				/* chroma planes are interleaved too */
+				cpadding = buf->vb.width >> buf->fmt->hshift;
+			} else {
+				cpadding = 0;
+			}
+			bttv_risc_planar(btv,&buf->odd,
+					 buf->vb.dma.sglist,
+					 0,buf->vb.width,ypadding,lines,
+					 uoffset,voffset,buf->fmt->hshift,
+					 buf->fmt->vshift >> 1,
+					 cpadding);
+			bttv_risc_planar(btv,&buf->even,
+					 buf->vb.dma.sglist,
+					 ypadding,buf->vb.width,ypadding,lines,
+					 uoffset+cpadding,
+					 voffset+cpadding,
+					 buf->fmt->hshift,
+					 cpadding ? (buf->fmt->vshift>>1) : -1,
+					 cpadding);
+		} else {
+			if (buf->vb.field & VBUF_FIELD_ODD)
+				risc = &buf->odd;
+			else
+				risc = &buf->even;
+			bttv_calc_geo(btv,&buf->geo,buf->vb.width,
+				      buf->vb.height,0,buf->tvnorm);
+			bttv_risc_planar(btv, risc, buf->vb.dma.sglist,
+					 0,buf->vb.width,0,buf->vb.height,
+					 uoffset,voffset,buf->fmt->hshift,
+					 buf->fmt->vshift,0);
+		}
+	}
+
+	/* raw data */
+	if (buf->fmt->flags & FORMAT_FLAGS_RAW) {
+		/* build risc code */
+		buf->vb.field = VBUF_FIELD_INTER | VBUF_FIELD_ODD | VBUF_FIELD_EVEN;
+		bttv_calc_geo(btv,&buf->geo,tvnorm->swidth,tvnorm->sheight,
+			      1,buf->tvnorm);
+		bttv_risc_packed(btv, &buf->odd,  buf->vb.dma.sglist,
+				 0, RAW_BPL, 0, RAW_LINES);
+		bttv_risc_packed(btv, &buf->even, buf->vb.dma.sglist,
+				 buf->vb.size/2 , RAW_BPL, 0, RAW_LINES);
+	}
+
+	/* copy format info */
+	buf->btformat = buf->fmt->btformat;
+	buf->btswap   = buf->fmt->btswap;
+	return 0;
+}
+
+/* ---------------------------------------------------------- */
+
+/* calculate geometry, build risc code */
+int
+bttv_overlay_risc(struct bttv *btv,
+		  struct bttv_overlay *ov,
+		  const struct bttv_format *fmt,
+		  struct bttv_buffer *buf)
+{
+	int interleave;
+
+	/* check interleave, even+odd fields */
+	buf->vb.field = bttv_buffer_field(btv, 0, VBUF_FIELD_ODD,
+					  ov->tvnorm,ov->height);
+	dprintk(KERN_DEBUG
+		"bttv%d: overlay flags:%s%s%s format: %s size: %dx%d\n",
+		btv->nr,
+		(buf->vb.field & VBUF_FIELD_INTER) ? " interleave" : "",
+		(buf->vb.field & VBUF_FIELD_ODD)   ? " odd" : "",
+		(buf->vb.field & VBUF_FIELD_EVEN)  ? " even" : "",
+		fmt->name,ov->width,ov->height);
+
+	/* calculate geometry */
+	interleave = buf->vb.field & VBUF_FIELD_INTER;
+	bttv_calc_geo(btv,&buf->geo,ov->width,ov->height,
+		      interleave, ov->tvnorm);
+
+	/* build risc code */
+	if (buf->vb.field & VBUF_FIELD_ODD)
+		bttv_risc_overlay(btv, &buf->odd, fmt, ov,
+				  interleave | VBUF_FIELD_ODD);
+	if (buf->vb.field & VBUF_FIELD_EVEN)
+		bttv_risc_overlay(btv, &buf->even,fmt, ov,
+				  interleave | VBUF_FIELD_EVEN);
+
+	/* copy format info */
+	buf->btformat = fmt->btformat;
+	buf->btswap   = fmt->btswap;
+	return 0;
+}
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff -Nru a/drivers/media/video/bttv-vbi.c b/drivers/media/video/bttv-vbi.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/media/video/bttv-vbi.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,658 @@
+/*
+    bttv - Bt848 frame grabber driver
+    vbi interface
+    
+    (c) 2002 Gerd Knorr <kraxel@bytesex.org>
+    
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+    
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/kdev_t.h>
+#include <asm/io.h>
+#include "bttvp.h"
+
+#define VBI_DEFLINES 16
+#define VBI_MAXLINES 32
+
+static unsigned int vbibufs = 4;
+static unsigned int vbi_debug = 0;
+
+MODULE_PARM(vbibufs,"i");
+MODULE_PARM_DESC(vbibufs,"number of vbi buffers, range 2-32, default 4");
+MODULE_PARM(vbi_debug,"i");
+MODULE_PARM_DESC(vbi_debug,"vbi code debug messages, default is 0 (no)");
+
+#ifdef dprintk
+# undef dprintk
+#endif
+#define dprintk(fmt, arg...)	if (vbi_debug) \
+	printk(KERN_DEBUG "bttv%d/vbi: " fmt, btv->nr, ## arg)
+
+#ifndef HAVE_V4L2
+/* some dummy defines to avoid cluttering up the source code with
+   a huge number of ifdef's for V4L2 */
+# define V4L2_BUF_TYPE_CAPTURE -1
+# define V4L2_BUF_TYPE_VBI     -1
+#endif
+
+/* ----------------------------------------------------------------------- */
+/* vbi risc code + mm                                                      */
+
+static int
+vbi_buffer_risc(struct bttv *btv, struct bttv_buffer *buf)
+{
+	int bpl = 2048;
+
+	bttv_risc_packed(btv, &buf->odd, buf->vb.dma.sglist,
+			 0, bpl-4, 4, btv->vbi.lines);
+	bttv_risc_packed(btv, &buf->even, buf->vb.dma.sglist,
+			 btv->vbi.lines * bpl, bpl-4, 4, btv->vbi.lines);
+	return 0;
+}
+
+static int vbi_buffer_prepare(struct bttv *btv, struct bttv_buffer *buf)
+{
+	int rc;
+	
+	buf->vb.size = btv->vbi.lines * 2 * 2048;
+	if (0 != buf->vb.baddr  &&  buf->vb.bsize < buf->vb.size)
+		return -EINVAL;
+
+	if (STATE_NEEDS_INIT == buf->vb.state) {
+		if (0 != (rc = videobuf_iolock(btv->dev,&buf->vb)))
+			goto fail;
+		if (0 != (rc = vbi_buffer_risc(btv,buf)))
+			goto fail;
+	}
+	buf->vb.state = STATE_PREPARED;
+	dprintk("buf prepare ok: odd=%p even=%p\n",&buf->odd,&buf->even);
+	return 0;
+
+ fail:
+	bttv_dma_free(btv,buf);
+	return rc;
+}
+
+static void
+vbi_buffer_queue(struct bttv *btv, struct bttv_buffer *buf)
+{
+	unsigned long flags;
+	
+	buf->vb.state = STATE_QUEUED;
+	spin_lock_irqsave(&btv->s_lock,flags);
+	list_add_tail(&buf->vb.queue,&btv->vcapture);
+	bttv_set_dma(btv,0x0c,1);
+	spin_unlock_irqrestore(&btv->s_lock,flags);
+}
+
+static void vbi_buffer_release(struct file *file, struct videobuf_buffer *vb)
+{
+	struct bttv *btv = file->private_data;
+	struct bttv_buffer *buf = (struct bttv_buffer*)vb;
+
+	bttv_dma_free(btv,buf);
+}
+
+static void
+vbi_cancel_all(struct bttv *btv)
+{
+	unsigned long flags;
+	int i;
+
+	/* remove queued buffers from list */
+	spin_lock_irqsave(&btv->s_lock,flags);
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == btv->vbi.bufs[i])
+			continue;
+		if (btv->vbi.bufs[i]->vb.state == STATE_QUEUED) {
+			list_del(&btv->vbi.bufs[i]->vb.queue);
+			btv->vbi.bufs[i]->vb.state = STATE_ERROR;
+		}
+	}
+	spin_unlock_irqrestore(&btv->s_lock,flags);
+
+	/* free all buffers + clear queue */
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == btv->vbi.bufs[i])
+			continue;
+		bttv_dma_free(btv,btv->vbi.bufs[i]);
+	}
+	INIT_LIST_HEAD(&btv->vbi.stream);
+}
+
+/* ----------------------------------------------------------------------- */
+
+static int vbi_read_start(struct file *file, struct bttv *btv)
+{
+	int err,size,count,i;
+	
+	if (vbibufs < 2 || vbibufs > VIDEO_MAX_FRAME)
+		vbibufs = 2;
+
+	count = vbibufs;
+	size  = btv->vbi.lines * 2 * 2048;
+	err = videobuf_mmap_setup(file,
+				  (struct videobuf_buffer**)btv->vbi.bufs,
+				  sizeof(struct bttv_buffer),
+				  count,size,V4L2_BUF_TYPE_VBI,
+				  vbi_buffer_release);
+	if (err)
+		return err;
+	for (i = 0; i < count; i++) {
+		err = vbi_buffer_prepare(btv,btv->vbi.bufs[i]);
+		if (err)
+			return err;
+		list_add_tail(&btv->vbi.bufs[i]->vb.stream,&btv->vbi.stream);
+		vbi_buffer_queue(btv,btv->vbi.bufs[i]);
+	}
+	btv->vbi.reading = 1;
+	return 0;
+}
+
+static void vbi_read_stop(struct bttv *btv)
+{
+	int i;
+
+	vbi_cancel_all(btv);
+	INIT_LIST_HEAD(&btv->vbi.stream);
+	for (i = 0; i < vbibufs; i++) {
+		kfree(btv->vbi.bufs[i]);
+		btv->vbi.bufs[i] = NULL;
+	}
+	btv->vbi.reading = 0;
+}
+
+static void vbi_setlines(struct bttv *btv, int lines)
+{
+	int vdelay;
+
+	if (lines < 1)
+		lines = 1;
+	if (lines > VBI_MAXLINES)
+		lines = VBI_MAXLINES;
+	btv->vbi.lines = lines;
+
+	vdelay = btread(BT848_E_VDELAY_LO);
+	if (vdelay < lines*2) {
+		vdelay = lines*2;
+		btwrite(vdelay,BT848_E_VDELAY_LO);
+		btwrite(vdelay,BT848_O_VDELAY_LO);
+	}
+}
+
+#ifdef HAVE_V4L2
+static void vbi_fmt(struct bttv *btv, struct v4l2_format *f)
+{
+	memset(f,0,sizeof(*f));
+	f->type = V4L2_BUF_TYPE_VBI;
+	f->fmt.vbi.sampling_rate    = 35468950;
+	f->fmt.vbi.samples_per_line = 2048;
+	f->fmt.vbi.sample_format    = V4L2_VBI_SF_UBYTE;
+	f->fmt.vbi.offset           = 244;
+	f->fmt.vbi.count[0]         = btv->vbi.lines;
+	f->fmt.vbi.count[1]         = btv->vbi.lines;
+	f->fmt.vbi.flags            = 0;
+	switch (btv->tvnorm) {
+	case 1: /* NTSC */
+		f->fmt.vbi.start[0] = 10;
+		f->fmt.vbi.start[1] = 273;
+		break;
+	case 0: /* PAL */
+	case 2: /* SECAM */
+	default:
+		f->fmt.vbi.start[0] = 7;
+		f->fmt.vbi.start[1] = 319;
+	}
+}
+#endif
+
+/* ----------------------------------------------------------------------- */
+/* vbi interface                                                           */
+
+static int vbi_open(struct inode *inode, struct file *file)
+{
+	unsigned int minor = minor(inode->i_rdev);
+	struct bttv *btv = NULL;
+	int i;
+
+
+	for (i = 0; i < bttv_num; i++) {
+		if (bttvs[i].vbi_dev.minor == minor) {
+			btv = &bttvs[i];
+			break;
+		}
+	}
+	if (NULL == btv)
+		return -ENODEV;
+
+	down(&btv->vbi.lock);
+	if (btv->vbi.users) {
+		up(&btv->vbi.lock);
+		return -EBUSY;
+	}
+	dprintk("open minor=%d\n",minor);
+	file->private_data = btv;
+	btv->vbi.users++;
+	bttv_field_count(btv);
+	vbi_setlines(btv,VBI_DEFLINES);
+	
+	up(&btv->vbi.lock);
+	
+	return 0;
+}
+
+static int vbi_release(struct inode *inode, struct file *file)
+{
+	struct bttv    *btv = file->private_data;
+
+	down(&btv->vbi.lock);
+	if (btv->vbi.reading) {
+		vbi_read_stop(btv);
+		btv->vbi.read_buf = NULL;
+	}
+	btv->vbi.users--;
+	bttv_field_count(btv);
+	vbi_setlines(btv,0);
+	up(&btv->vbi.lock);
+	return 0;
+}
+
+static int vbi_ioctl(struct inode *inode, struct file *file,
+		     unsigned int cmd, void *arg)
+{
+	struct bttv *btv = file->private_data;
+#ifdef HAVE_V4L2
+	unsigned long flags;
+	int err;
+#endif
+	
+	if (btv->errors)
+		bttv_reinit_bt848(btv);
+	switch (cmd) {
+	case VIDIOCGCAP:
+	{
+                struct video_capability *cap = arg;
+
+		memset(cap,0,sizeof(*cap));
+                strcpy(cap->name,btv->vbi_dev.name);
+                cap->type = VID_TYPE_TUNER|VID_TYPE_TELETEXT;
+                return 0;
+	}
+
+	/* vbi/teletext ioctls */
+	case BTTV_VBISIZE:
+		return btv->vbi.lines * 2 * 2048;
+
+	case BTTV_VERSION:
+        case VIDIOCGFREQ:
+        case VIDIOCSFREQ:
+        case VIDIOCGTUNER:
+        case VIDIOCSTUNER:
+        case VIDIOCGCHAN:
+        case VIDIOCSCHAN:
+		return bttv_common_ioctls(btv,cmd,arg);
+
+#ifdef HAVE_V4L2
+	case VIDIOC_QUERYCAP:
+	{
+		struct v4l2_capability *cap = arg;
+
+		memset(cap,0,sizeof(*cap));
+                strcpy(cap->name, btv->name);
+		cap->type = V4L2_TYPE_VBI;
+		cap->flags = V4L2_FLAG_TUNER | V4L2_FLAG_READ |
+			V4L2_FLAG_STREAMING | V4L2_FLAG_SELECT;
+		return 0;
+	}
+	case VIDIOC_G_FMT:
+	{
+		struct v4l2_format *f = arg;
+
+		vbi_fmt(btv,f);
+		return 0;
+	}
+	case VIDIOC_S_FMT:
+	{
+		struct v4l2_format *f = arg;
+
+		if (btv->vbi.reading || btv->vbi.streaming)
+			return -EBUSY;
+		vbi_setlines(btv,f->fmt.vbi.count[0]);
+		vbi_fmt(btv,f);
+		return 0;
+	}
+
+	case VIDIOC_REQBUFS:
+	{
+		struct v4l2_requestbuffers *req = arg;
+		int size,count;
+
+		if ((req->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_VBI)
+			return -EINVAL;
+		if (req->count < 1)
+			return -EINVAL;
+
+		down(&btv->vbi.lock);
+		err = -EINVAL;
+
+		size  = btv->vbi.lines * 2 * 2048;
+		size  = (size + PAGE_SIZE - 1) & PAGE_MASK;
+		count = req->count;
+		if (count > VIDEO_MAX_FRAME)
+			count = VIDEO_MAX_FRAME;
+		err = videobuf_mmap_setup(file,
+					  (struct videobuf_buffer**)btv->vbi.bufs,
+					  sizeof(struct bttv_buffer),
+					  count,size,V4L2_BUF_TYPE_CAPTURE,
+					  vbi_buffer_release);
+		if (err < 0)
+			goto fh_unlock_and_return;
+		req->type  = V4L2_BUF_TYPE_VBI;
+		req->count = count;
+		up(&btv->vbi.lock);
+		return 0;
+	}
+	case VIDIOC_QUERYBUF:
+	{
+		struct v4l2_buffer *b = arg;
+
+		if ((b->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_VBI)
+			return -EINVAL;
+		if (b->index < 0 || b->index > VIDEO_MAX_FRAME)
+			return -EINVAL;
+		if (NULL == btv->vbi.bufs[b->index])
+			return -EINVAL;
+		videobuf_status(b,&btv->vbi.bufs[b->index]->vb);
+		return 0;
+	}
+	case VIDIOC_QBUF:
+	{
+		struct v4l2_buffer *b = arg;
+		struct bttv_buffer *buf;
+		
+		if ((b->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_VBI)
+			return -EINVAL;
+		if (b->index < 0 || b->index > VIDEO_MAX_FRAME)
+			return -EINVAL;
+
+		down(&btv->vbi.lock);
+		err = -EINVAL;
+		buf = btv->vbi.bufs[b->index];
+		if (NULL == buf)
+			goto fh_unlock_and_return;
+		if (0 == buf->vb.baddr)
+			goto fh_unlock_and_return;
+		if (buf->vb.state == STATE_QUEUED ||
+		    buf->vb.state == STATE_ACTIVE)
+			goto fh_unlock_and_return;
+		err = vbi_buffer_prepare(btv,buf);
+		if (0 != err)
+			goto fh_unlock_and_return;
+
+		list_add_tail(&buf->vb.stream,&btv->vbi.stream);
+		if (btv->vbi.streaming)
+			vbi_buffer_queue(btv,buf);
+		up(&btv->vbi.lock);
+		return 0;
+	}
+	case VIDIOC_DQBUF:
+	{
+		struct v4l2_buffer *b = arg;
+		struct bttv_buffer *buf;
+
+		if ((b->type & V4L2_BUF_TYPE_field) != V4L2_BUF_TYPE_VBI)
+			return -EINVAL;
+
+		down(&btv->vbi.lock);
+		err = -EINVAL;
+		if (list_empty(&btv->vbi.stream))
+			goto fh_unlock_and_return;
+		buf = list_entry(btv->vbi.stream.next,
+				 struct bttv_buffer, vb.stream);
+		err = videobuf_waiton(&buf->vb,0,1);
+		if (err < 0)
+			goto fh_unlock_and_return;
+		switch (buf->vb.state) {
+		case STATE_ERROR:
+			err = -EIO;
+			/* fall through */
+		case STATE_DONE:
+			videobuf_dma_pci_sync(btv->dev,&buf->vb.dma);
+			buf->vb.state = STATE_IDLE;
+			break;
+		default:
+			err = -EINVAL;
+			goto fh_unlock_and_return;
+		}
+		list_del(&buf->vb.stream);
+		memset(b,0,sizeof(*b));
+		videobuf_status(b,&buf->vb);
+		up(&btv->vbi.lock);
+		return err;
+	}
+	case VIDIOC_STREAMON:
+	{
+		struct list_head *list;
+		struct bttv_buffer *buf;
+
+		down(&btv->vbi.lock);
+		err = -EBUSY;
+		if (btv->vbi.reading)
+			goto fh_unlock_and_return;
+		spin_lock_irqsave(&btv->s_lock,flags);
+		list_for_each(list,&btv->vbi.stream) {
+			buf = list_entry(list, struct bttv_buffer, vb.stream);
+			if (buf->vb.state == STATE_PREPARED)
+				vbi_buffer_queue(btv,buf);
+		}
+		spin_unlock_irqrestore(&btv->s_lock,flags);
+		btv->vbi.streaming = 1;
+		up(&btv->vbi.lock);
+		return 0;
+	}
+	case VIDIOC_STREAMOFF:
+	{
+		down(&btv->vbi.lock);
+		err = -EINVAL;
+		if (!btv->vbi.streaming)
+			goto fh_unlock_and_return;
+		vbi_cancel_all(btv);
+		INIT_LIST_HEAD(&btv->vbi.stream);
+		btv->vbi.streaming = 0;
+		up(&btv->vbi.lock);
+		return 0;
+	}
+
+	case VIDIOC_ENUMSTD:
+	case VIDIOC_G_STD:
+	case VIDIOC_S_STD:
+	case VIDIOC_ENUMINPUT:
+	case VIDIOC_G_INPUT:
+	case VIDIOC_S_INPUT:
+	case VIDIOC_G_TUNER:
+	case VIDIOC_S_TUNER:
+	case VIDIOC_G_FREQ:
+	case VIDIOC_S_FREQ:
+		return bttv_common_ioctls(btv,cmd,arg);
+#endif /* HAVE_V4L2 */
+
+	default:
+		return -ENOIOCTLCMD;
+	}
+	return 0;
+
+#ifdef HAVE_V4L2
+ fh_unlock_and_return:
+	up(&btv->vbi.lock);
+	return err;
+#endif
+}
+
+static ssize_t vbi_read(struct file *file, char *data,
+			size_t count, loff_t *ppos)
+{
+	unsigned int *fc;
+	struct bttv *btv = file->private_data;
+	int err, bytes, retval = 0;
+
+	if (btv->errors)
+		bttv_reinit_bt848(btv);
+	down(&btv->vbi.lock);
+	if (!btv->vbi.reading) {
+		retval = vbi_read_start(file,btv);
+		if (retval < 0)
+			goto done;
+	}
+
+	while (count > 0) {
+		/* get / wait for data */
+		if (NULL == btv->vbi.read_buf) {
+			btv->vbi.read_buf = list_entry(btv->vbi.stream.next,
+						       struct bttv_buffer,
+						       vb.stream);
+			list_del(&btv->vbi.read_buf->vb.stream);
+			btv->vbi.read_off = 0;
+		}
+		err = videobuf_waiton(&btv->vbi.read_buf->vb,
+				      file->f_flags & O_NONBLOCK,1);
+		if (err < 0) {
+			if (0 == retval)
+				retval = err;
+			break;
+		}
+
+#if 1
+		/* dirty, undocumented hack -- pass the frame counter
+		 * within the last four bytes of each vbi data block.
+		 * We need that one to maintain backward compatibility
+		 * to all vbi decoding software out there ... */
+		fc  = (unsigned int*)btv->vbi.read_buf->vb.dma.vmalloc;
+		fc += (btv->vbi.read_buf->vb.size>>2) -1;
+		*fc = btv->vbi.read_buf->vb.field_count >> 1;
+#endif
+
+		/* copy stuff */
+		bytes = count;
+		if (bytes > btv->vbi.read_buf->vb.size - btv->vbi.read_off)
+			bytes = btv->vbi.read_buf->vb.size - btv->vbi.read_off;
+		if (copy_to_user(data + retval,btv->vbi.read_buf->vb.dma.vmalloc +
+				 btv->vbi.read_off,bytes)) {
+			if (0 == retval)
+				retval = -EFAULT;
+			break;
+		}
+		count             -= bytes;
+		retval            += bytes;
+		btv->vbi.read_off += bytes;
+		dprintk("read: %d bytes\n",bytes);
+
+		/* requeue buffer when done with copying */
+		if (btv->vbi.read_off == btv->vbi.read_buf->vb.size) {
+			list_add_tail(&btv->vbi.read_buf->vb.stream,
+				      &btv->vbi.stream);
+			vbi_buffer_queue(btv,btv->vbi.read_buf);
+			btv->vbi.read_buf = NULL;
+		}
+	}
+ done:
+	up(&btv->vbi.lock);
+	return retval;
+}
+
+static unsigned int vbi_poll(struct file *file, poll_table *wait)
+{
+	struct bttv *btv = file->private_data;
+	struct bttv_buffer *buf = NULL;
+	unsigned int rc = 0;
+
+	down(&btv->vbi.lock);
+	if (btv->vbi.streaming) {
+		if (!list_empty(&btv->vbi.stream))
+			buf = list_entry(btv->vbi.stream.next,
+					 struct bttv_buffer, vb.stream);
+	} else {
+		if (!btv->vbi.reading)
+			vbi_read_start(file,btv);
+		if (!btv->vbi.reading) {
+			rc = POLLERR;
+		} else if (NULL == btv->vbi.read_buf) {
+			btv->vbi.read_buf = list_entry(btv->vbi.stream.next,
+						       struct bttv_buffer,
+						       vb.stream);
+			list_del(&btv->vbi.read_buf->vb.stream);
+			btv->vbi.read_off = 0;
+		}
+		buf = btv->vbi.read_buf;
+	}
+	if (!buf)
+		rc = POLLERR;
+
+	if (0 == rc) {
+		poll_wait(file, &buf->vb.done, wait);
+		if (buf->vb.state == STATE_DONE ||
+		    buf->vb.state == STATE_ERROR)
+			rc = POLLIN|POLLRDNORM;
+	}
+	up(&btv->vbi.lock);
+	return rc;
+}
+
+static int
+vbi_mmap(struct file *file, struct vm_area_struct * vma)
+{
+	struct bttv *btv = file->private_data;
+	int err;
+
+	down(&btv->vbi.lock);
+	err = videobuf_mmap_mapper
+		(vma,(struct videobuf_buffer**)btv->vbi.bufs);
+	up(&btv->vbi.lock);
+	return err;
+}
+
+static struct file_operations vbi_fops =
+{
+	owner:	  THIS_MODULE,
+	open:	  vbi_open,
+	release:  vbi_release,
+	ioctl:	  video_generic_ioctl,
+	llseek:	  no_llseek,
+	read:	  vbi_read,
+	poll:	  vbi_poll,
+	mmap:	  vbi_mmap,
+};
+
+struct video_device bttv_vbi_template =
+{
+	name:     "bt848/878 vbi",
+	type:     VID_TYPE_TUNER|VID_TYPE_TELETEXT,
+	hardware: VID_HARDWARE_BT848,
+	fops:     &vbi_fops,
+	kernel_ioctl: vbi_ioctl,
+	minor:    -1,
+};
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff -Nru a/drivers/media/video/bttv.h b/drivers/media/video/bttv.h
--- a/drivers/media/video/bttv.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/video/bttv.h	Fri Mar 15 17:51:01 2002
@@ -87,7 +87,9 @@
 #define BTTV_PV_BT878P_PLUS 0x46
 #define BTTV_FLYVIDEO98EZ   0x47
 #define BTTV_PV_BT878P_9B   0x48
-
+#define BTTV_SENSORAY311    0x49
+#define BTTV_RV605          0x4a
+#define BTTV_WINDVR         0x4c
 
 /* i2c address list */
 #define I2C_TSA5522        0xc2
@@ -95,7 +97,7 @@
 #define I2C_TDA8425        0x82
 #define I2C_TDA9840        0x84
 #define I2C_TDA9850        0xb6 /* also used by 9855,9873 */
-#define I2C_TDA9874A       0xb0 /* also used by 9875 */
+#define I2C_TDA9874        0xb0 /* also used by 9875 */
 #define I2C_TDA9875        0xb0
 #define I2C_HAUPEE         0xa0
 #define I2C_STBEE          0xae
@@ -123,7 +125,7 @@
         int tuner;
         int svhs;
         u32 gpiomask;
-        u32 muxsel[8];
+        u32 muxsel[16];
         u32 audiomux[6]; /* Tuner, Radio, external, internal, mute, stereo */
         u32 gpiomask2;   /* GPIO MUX mask */
 
@@ -141,6 +143,7 @@
 	int tuner_type;
 	int has_radio;
 	void (*audio_hook)(struct bttv *btv, struct video_audio *v, int set);
+	void (*muxsel_hook)(struct bttv *btv, unsigned int input);
 };
 
 extern struct tvcard bttv_tvcards[];
@@ -148,11 +151,12 @@
 
 /* identification / initialization of the card */
 extern void bttv_idcard(struct bttv *btv);
-extern void bttv_init_card(struct bttv *btv);
+extern void bttv_init_card1(struct bttv *btv);
+extern void bttv_init_card2(struct bttv *btv);
 
 /* card-specific funtions */
 extern void tea5757_set_freq(struct bttv *btv, unsigned short freq);
-extern void bttv_boot_msp34xx(struct bttv *btv, int pin);
+extern void bttv_tda9880_setnorm(struct bttv *btv, int norm);
 
 /* kernel cmd line parse helper */
 extern int bttv_parse(char *str, int max, int *vals);
diff -Nru a/drivers/media/video/bttvp.h b/drivers/media/video/bttvp.h
--- a/drivers/media/video/bttvp.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/bttvp.h	Fri Mar 15 17:51:02 2002
@@ -1,11 +1,10 @@
 /*
     bttv - Bt848 frame grabber driver
 
-    bttv's *private* header file  --  nobody else than bttv itself
+    bttv's *private* header file  --  nobody other than bttv itself
     should ever include this file.
 
-    Copyright (C) 1996,97 Ralph Metzler (rjkm@thp.uni-koeln.de)
-    (c) 1999,2000 Gerd Knorr <kraxel@goldbach.in-berlin.de>
+    (c) 2000-2002 Gerd Knorr <kraxel@bytesex.org>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -25,203 +24,338 @@
 #ifndef _BTTVP_H_
 #define _BTTVP_H_
 
-#define BTTV_VERSION_CODE KERNEL_VERSION(0,7,83)
-
+#define BTTV_VERSION_CODE KERNEL_VERSION(0,8,38)
 
 #include <linux/types.h>
 #include <linux/wait.h>
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
+#include <linux/videodev.h>
+#include <linux/iobuf.h>
+#include <linux/pci.h>
+#include <asm/scatterlist.h>
 
 #include "bt848.h"
 #include "bttv.h"
+#include "video-buf.h"
 #include "audiochip.h"
 
 #ifdef __KERNEL__
 
+#define FORMAT_FLAGS_DITHER       0x01
+#define FORMAT_FLAGS_PACKED       0x02
+#define FORMAT_FLAGS_PLANAR       0x04
+#define FORMAT_FLAGS_RAW          0x08
+#define FORMAT_FLAGS_CrCb         0x10
+
+#define RISC_SLOT_O_VBI        4
+#define RISC_SLOT_O_FIELD      6
+#define RISC_SLOT_E_VBI       10
+#define RISC_SLOT_E_FIELD     12
+#define RISC_SLOT_LOOP        14
+
+#define RESOURCE_OVERLAY       1
+#define RESOURCE_STREAMING     2
+
+#define RAW_LINES            640
+#define RAW_BPL             1024
+
+/* ---------------------------------------------------------- */
+
+struct bttv_tvnorm 
+{
+	int v4l2_id;
+        u32 Fsc;
+        u16 swidth, sheight; /* scaled standard width, height */
+	u16 totalwidth;
+	u8 adelay, bdelay, iform;
+	u32 scaledtwidth;
+	u16 hdelayx1, hactivex1;
+	u16 vdelay;
+        u8 vbipack;
+};
+extern const struct bttv_tvnorm bttv_tvnorms[];
+extern const int BTTV_TVNORMS;
+
+struct bttv_format {
+	char *name;
+	int  palette;         /* video4linux 1      */
+	int  fourcc;          /* video4linux 2      */
+	int  btformat;        /* BT848_COLOR_FMT_*  */
+	int  btswap;          /* BT848_COLOR_CTL_*  */
+	int  depth;           /* bit/pixel          */
+	int  flags;
+	int  hshift,vshift;   /* for planar modes   */
+};
+extern const struct bttv_format bttv_formats[];
+extern const int BTTV_FORMATS;
+
+/* ---------------------------------------------------------- */
+
+struct bttv_geometry {
+	u8  vtc,crop,comb;
+	u16 width,hscale,hdelay;
+	u16 sheight,vscale,vdelay;
+};
+
+struct bttv_riscmem {
+	unsigned int   size;
+	unsigned long  *cpu;
+	unsigned long  *jmp;
+	dma_addr_t     dma;
+};
+
+struct bttv_buffer {
+	/* common v4l buffer stuff -- must be first */
+	struct videobuf_buffer     vb;
+
+	/* bttv specific */
+	const struct bttv_format   *fmt;
+	int                        tvnorm;
+	int                        btformat;
+	int                        btswap;
+	struct bttv_geometry       geo;
+	struct bttv_riscmem        even;
+	struct bttv_riscmem        odd;
+};
+
+struct bttv_overlay {
+	int tvnorm;
+	int x,y,width,height;
+	struct video_clip      *clips;
+	int                    nclips;
+};
+
+struct bttv_vbi {
+        struct semaphore           lock;
+	int                        users;
+	int                        lines;
+
+	/* mmap */
+	int                        streaming;
+	struct bttv_buffer         *bufs[VIDEO_MAX_FRAME];
+	struct list_head           stream;
+
+	/* read */
+	int                        reading;
+	int                        read_off;
+	struct bttv_buffer         *read_buf;
+};
+
+struct bttv_fh {
+	struct bttv              *btv;
+
+	/* locking */
+	int resources;
+	struct semaphore lock;
+
+	/* keep current driver settings */
+	const struct bttv_format *ovfmt;
+	struct bttv_overlay      ov;
+	struct bttv_buffer       buf;
+
+	/* for read() capture */
+	struct bttv_buffer       read_buf;
+	int                      read_off;
+
+	/* mmap()'ed buffers */
+	struct bttv_buffer       *bufs[VIDEO_MAX_FRAME];
+	struct list_head stream; /* v4l2 QBUF/DQBUF */
+};
+
+/* ---------------------------------------------------------- */
+/* bttv-risc.c                                                */
+
+/* alloc/free memory */
+int  bttv_riscmem_alloc(struct pci_dev *pci,
+			struct bttv_riscmem *risc,
+			unsigned int size);
+void bttv_riscmem_free(struct pci_dev *pci,
+		       struct bttv_riscmem *risc);
+
+/* risc code generators - capture */
+int bttv_risc_packed(struct bttv *btv, struct bttv_riscmem *risc,
+		     struct scatterlist *sglist,
+		     int offset, int bpl, int pitch, int lines);
+int bttv_risc_planar(struct bttv *btv, struct bttv_riscmem *risc,
+		     struct scatterlist *sglist,
+		     int yoffset, int ybpl, int ypadding, int ylines,
+		     int uoffset, int voffset, int hshift, int vshift,
+		     int cpadding);
+
+/* risc code generator + helpers - screen overlay */
+int bttv_screen_clips(struct video_buffer *fbuf,
+		      int x, int y, int width, int height,
+		      struct video_clip *clips, int n);
+void bttv_sort_clips(struct video_clip *clips, int nclips);
+int bttv_risc_overlay(struct bttv *btv, struct bttv_riscmem *risc,
+		      const struct bttv_format *fmt,
+		      struct bttv_overlay *ov, int flags);
+
+/* calculate / apply geometry settings */
+void bttv_calc_geo(struct bttv *btv, struct bttv_geometry *geo,
+		   int width, int height, int interleaved, int norm);
+void bttv_apply_geo(struct bttv *btv, struct bttv_geometry *geo, int odd);
+
+/* control dma register + risc main loop */
+void bttv_set_dma(struct bttv *btv, int override, int irqflags);
+int bttv_risc_init_main(struct bttv *btv);
+int bttv_risc_hook(struct bttv *btv, int slot, struct bttv_riscmem *risc,
+		   int irqflags);
+
+/* capture buffer handling */
+int bttv_buffer_field(struct bttv *btv, int field, int def_field,
+		      int tvnorm, int height);
+int bttv_buffer_risc(struct bttv *btv, struct bttv_buffer *buf);
+int bttv_buffer_activate(struct bttv *btv, struct bttv_buffer *odd,
+			 struct bttv_buffer *even);
+void bttv_dma_free(struct bttv *btv, struct bttv_buffer *buf);
+
+/* overlay handling */
+int bttv_overlay_risc(struct bttv *btv, struct bttv_overlay *ov,
+		      const struct bttv_format *fmt,
+		      struct bttv_buffer *buf);
+
+
+/* ---------------------------------------------------------- */
+/* bttv-vbi.c                                                 */
+
+extern struct video_device bttv_vbi_template;
+
 /* ---------------------------------------------------------- */
 /* bttv-driver.c                                              */
 
-/* insmod options / kernel args */
-extern int no_overlay;
+/* insmod options */
 extern unsigned int bttv_verbose;
 extern unsigned int bttv_debug;
 extern unsigned int bttv_gpio;
 extern void bttv_gpio_tracking(struct bttv *btv, char *comment);
 extern int init_bttv_i2c(struct bttv *btv);
 
-#define dprintk		if (bttv_debug) printk
+extern int bttv_common_ioctls(struct bttv *btv, unsigned int cmd, void *arg);
+extern void bttv_reinit_bt848(struct bttv *btv);
+extern void bttv_field_count(struct bttv *btv);
+
+#define vprintk  if (bttv_verbose) printk
+#define dprintk  if (bttv_debug >= 1) printk
+#define d2printk if (bttv_debug >= 2) printk
 
-/* Anybody who uses more than four? */
+/* our devices */
 #define BTTV_MAX 4
-extern int bttv_num;			/* number of Bt848s in use */
+extern int bttv_num;
 extern struct bttv bttvs[BTTV_MAX];
 
-
-#ifndef O_NONCAP  
-#define O_NONCAP	O_TRUNC
-#endif
-
-#ifdef VIDEODAT_HACK
-# define VBI_MAXLINES   19
-#else
-# define VBI_MAXLINES   16
-#endif
+#define BTTV_MAX_FBUF   0x208000
 #define VBIBUF_SIZE     (2048*VBI_MAXLINES*2)
-#define MAX_GBUFFERS	64
-#define RISCMEM_LEN	(32744*2)
+#define BTTV_TIMEOUT    (HZ/2) /* 0.5 seconds */
+#define BTTV_FREE_IDLE  (HZ)   /* one second */
 
-#define BTTV_MAX_FBUF	0x208000
-
-struct bttv_window 
-{
-	int x, y;
-	ushort width, height;
-	ushort bpp, bpl;
-	ushort swidth, sheight;
-	unsigned long vidadr;
-	ushort freq;
-	int norm;
-	int interlace;
-	int color_fmt;
-	ushort depth;
-};
 
 struct bttv_pll_info {
-	unsigned int pll_ifreq;	   /* PLL input frequency 	 */
-	unsigned int pll_ofreq;	   /* PLL output frequency       */
+	unsigned int pll_ifreq;    /* PLL input frequency        */
+	unsigned int pll_ofreq;    /* PLL output frequency       */
 	unsigned int pll_crystal;  /* Crystal used for input     */
 	unsigned int pll_current;  /* Currently programmed ofreq */
 };
 
-struct bttv_gbuf {
-	int stat;
-#define GBUFFER_UNUSED       0
-#define GBUFFER_GRABBING     1
-#define GBUFFER_DONE         2
-#define GBUFFER_ERROR        3
-	struct timeval tv;
-	
-	u16 width;
-	u16 height;
-	u16 fmt;
-	
-	u32 *risc;
-	unsigned long ro;
-	unsigned long re;
-};
-
 struct bttv {
-	struct video_device video_dev;
-	struct video_device radio_dev;
-	struct video_device vbi_dev;
-	struct video_picture picture;		/* Current picture params */
-	struct video_audio audio_dev;		/* Current audio params */
+	/* pci device config */
+	struct pci_dev *dev;
+	unsigned short id;
+	unsigned char revision;
+	unsigned char *bt848_mmio;   /* pointer to mmio */
 
-	spinlock_t s_lock;
-        struct semaphore lock;
-	int user;
-	int capuser;
+	/* card configuration info */
+        unsigned int nr;       /* dev nr (for printk("bttv%d: ...");  */
+	char name[8];          /* dev name */
+	int cardid;            /* pci subsystem id (bt878 based ones) */
+	int type;              /* card type (pointer into tvcards[])  */
+        int tuner_type;        /* tuner chip type */
+	struct bttv_pll_info pll;
+	int triton1;
 
-	/* i2c */
+	/* gpio interface */
+	wait_queue_head_t gpioq;
+	int shutdown;
+
+	/* i2c layer */
 	struct i2c_adapter         i2c_adap;
 	struct i2c_algo_bit_data   i2c_algo;
 	struct i2c_client          i2c_client;
 	int                        i2c_state, i2c_rc;
 	struct i2c_client         *i2c_clients[I2C_CLIENTS_MAX];
 
-        int tuner_type;
-        int channel;
-        
-        unsigned int nr;
-	unsigned short id;
-	struct pci_dev *dev;
-	unsigned int irq;          /* IRQ used by Bt848 card */
-	unsigned char revision;
-	unsigned long bt848_adr;      /* bus address of IO mem returned by PCI BIOS */
-	unsigned char *bt848_mem;   /* pointer to mapped IO memory */
-	unsigned long busriscmem; 
-	u32 *riscmem;
-  
-	unsigned char *vbibuf;
-	struct bttv_window win;
-	int fb_color_ctl;
-	int type;            /* card type  */
-	int cardid;
-	int audio;           /* audio mode */
-	int audio_chip;      /* set to one of the chips supported by bttv.c */
-	int radio;
-	int has_radio;
+	/* video4linux (1) */
+	struct video_device video_dev;
+	struct video_device radio_dev;
+	struct video_device vbi_dev;
 
-	/* miro/pinnacle + Aimslab VHX
-	   philips matchbox (tea5757 radio tuner) support */
+	/* locking */
+	spinlock_t s_lock;
+        struct semaphore lock;
+	int resources;
+        struct semaphore reslock;
+
+	/* video state */
+	int input;
+	int audio;
+	unsigned long freq;
+	int tvnorm,hue,contrast,bright,saturation;
+	struct video_buffer fbuf;
+	int field_count;
+
+	/* various options */
+	int opt_combfilter;
+	int opt_lumafilter;
+	int opt_automute;
+	int opt_chroma_agc;
+	int opt_adc_crush;
+
+	/* vbi data/state */
+	struct bttv_vbi vbi;
+
+	/* radio data/state */
+	int has_radio;
 	int has_matchbox;
-	int mbox_we;
+        int mbox_we;
 	int mbox_data;
 	int mbox_clk;
 	int mbox_most;
 	int mbox_mask;
-
-	u32 *risc_jmp;
-	u32 *vbi_odd;
-	u32 *vbi_even;
-	u32 bus_vbi_even;
-	u32 bus_vbi_odd;
-        wait_queue_head_t vbiq;
-	wait_queue_head_t capq;
-	int vbip;
-
-	u32 *risc_scr_odd;
-	u32 *risc_scr_even;
-	u32 risc_cap_odd;
-	u32 risc_cap_even;
-	int scr_on;
-	int vbi_on;
-	struct video_clip *cliprecs;
-
-	struct bttv_gbuf *gbuf;
-	int gqueue[MAX_GBUFFERS];
-	int gq_in,gq_out,gq_grab,gq_start;
-        char *fbuffer;
-
-	struct bttv_pll_info pll;
-	unsigned int Fsc;
-	unsigned int field;
-	unsigned int last_field; /* number of last grabbed field */
-	int i2c_command;
-	int triton1;
-
+	int radio_user;
+	
+	/* risc memory management data
+	   - must aquire s_lock before changing these
+	   - only the irq handler is supported to touch odd + even */
+	struct bttv_riscmem    main;
+	struct bttv_buffer     *odd;       /* current active odd field   */
+	struct bttv_buffer     *even;      /* current active even field  */
+	struct bttv_buffer     *screen;    /* overlay                    */
+	struct list_head       capture;    /* capture buffer queue       */
+	struct bttv_buffer     *vcurr;
+	struct list_head       vcapture;
+
+	unsigned long cap_ctl;
+	unsigned long dma_on;
+	struct timer_list timeout;
 	int errors;
-	int needs_restart;
 
-	wait_queue_head_t gpioq;
-	int shutdown;
+	int user;
+	struct bttv_fh init;
 };
+
+/* private ioctls */
+#define BTTV_VERSION            _IOR('v' , BASE_VIDIOCPRIVATE+6, int)
+#define BTTV_VBISIZE            _IOR('v' , BASE_VIDIOCPRIVATE+8, int)
+
 #endif
 
-#define btwrite(dat,adr)    writel((dat), (char *) (btv->bt848_mem+(adr)))
-#define btread(adr)         readl(btv->bt848_mem+(adr))
+#define btwrite(dat,adr)    writel((dat), (char *) (btv->bt848_mmio+(adr)))
+#define btread(adr)         readl(btv->bt848_mmio+(adr))
 
 #define btand(dat,adr)      btwrite((dat) & btread(adr), adr)
 #define btor(dat,adr)       btwrite((dat) | btread(adr), adr)
 #define btaor(dat,mask,adr) btwrite((dat) | ((mask) & btread(adr)), adr)
-
-/* bttv ioctls */
-
-#define BTTV_READEE		_IOW('v',  BASE_VIDIOCPRIVATE+0, char [256])
-#define BTTV_WRITEE		_IOR('v',  BASE_VIDIOCPRIVATE+1, char [256])
-#define BTTV_FIELDNR		_IOR('v' , BASE_VIDIOCPRIVATE+2, unsigned int)
-#define BTTV_PLLSET		_IOW('v' , BASE_VIDIOCPRIVATE+3, struct bttv_pll_info)
-#define BTTV_BURST_ON      	_IOR('v' , BASE_VIDIOCPRIVATE+4, int)
-#define BTTV_BURST_OFF     	_IOR('v' , BASE_VIDIOCPRIVATE+5, int)
-#define BTTV_VERSION  	        _IOR('v' , BASE_VIDIOCPRIVATE+6, int)
-#define BTTV_PICNR		_IOR('v' , BASE_VIDIOCPRIVATE+7, int)
-#define BTTV_VBISIZE            _IOR('v' , BASE_VIDIOCPRIVATE+8, int)
-
-#define TDA9850            0x01
-#define TDA9840            0x02
-#define TDA8425            0x03
-#define TEA6300            0x04
 
 #endif /* _BTTVP_H_ */
 
diff -Nru a/drivers/media/video/bw-qcam.c b/drivers/media/video/bw-qcam.c
--- a/drivers/media/video/bw-qcam.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/bw-qcam.c	Fri Mar 15 17:51:02 2002
@@ -694,125 +694,97 @@
  *	Video4linux interfacing
  */
 
-static int qcam_open(struct video_device *dev, int flags)
-{
-	return 0;
-}
-
-static void qcam_close(struct video_device *dev)
-{
-}
-
-static long qcam_write(struct video_device *v, const char *buf, unsigned long count, int noblock)
-{
-	return -EINVAL;
-}
-
-static int qcam_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int qcam_ioctl(struct inode *inode, struct file *file,
+		      unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct qcam_device *qcam=(struct qcam_device *)dev;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability b;
-			strcpy(b.name, "Quickcam");
-			b.type = VID_TYPE_CAPTURE|VID_TYPE_SCALES|VID_TYPE_MONOCHROME;
-			b.channels = 1;
-			b.audios = 0;
-			b.maxwidth = 320;
-			b.maxheight = 240;
-			b.minwidth = 80;
-			b.minheight = 60;
-			if(copy_to_user(arg, &b,sizeof(b)))
-				return -EFAULT;
+			struct video_capability *b = arg;
+			strcpy(b->name, "Quickcam");
+			b->type = VID_TYPE_CAPTURE|VID_TYPE_SCALES|VID_TYPE_MONOCHROME;
+			b->channels = 1;
+			b->audios = 0;
+			b->maxwidth = 320;
+			b->maxheight = 240;
+			b->minwidth = 80;
+			b->minheight = 60;
 			return 0;
 		}
 		case VIDIOCGCHAN:
 		{
-			struct video_channel v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.channel!=0)
+			struct video_channel *v = arg;
+			if(v->channel!=0)
 				return -EINVAL;
-			v.flags=0;
-			v.tuners=0;
+			v->flags=0;
+			v->tuners=0;
 			/* Good question.. its composite or SVHS so.. */
-			v.type = VIDEO_TYPE_CAMERA;
-			strcpy(v.name, "Camera");
+			v->type = VIDEO_TYPE_CAMERA;
+			strcpy(v->name, "Camera");
 			if(copy_to_user(arg, &v, sizeof(v)))
 				return -EFAULT;
 			return 0;
 		}
 		case VIDIOCSCHAN:
 		{
-			int v;
-			if(copy_from_user(&v, arg,sizeof(v)))
-				return -EFAULT;
-			if(v!=0)
+			struct video_channel *v = arg;
+			if(v->channel!=0)
 				return -EINVAL;
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
+			struct video_tuner *v = arg;
+			if(v->tuner)
 				return -EINVAL;
-			strcpy(v.name, "Format");
-			v.rangelow=0;
-			v.rangehigh=0;
-			v.flags= 0;
-			v.mode = VIDEO_MODE_AUTO;
-			if(copy_to_user(arg,&v,sizeof(v))!=0)
-				return -EFAULT;
+			strcpy(v->name, "Format");
+			v->rangelow=0;
+			v->rangehigh=0;
+			v->flags= 0;
+			v->mode = VIDEO_MODE_AUTO;
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
+			struct video_tuner *v = arg;
+			if(v->tuner)
 				return -EINVAL;
-			if(v.mode!=VIDEO_MODE_AUTO)
+			if(v->mode!=VIDEO_MODE_AUTO)
 				return -EINVAL;
 			return 0;
 		}
 		case VIDIOCGPICT:
 		{
-			struct video_picture p;
-			p.colour=0x8000;
-			p.hue=0x8000;
-			p.brightness=qcam->brightness<<8;
-			p.contrast=qcam->contrast<<8;
-			p.whiteness=qcam->whitebal<<8;
-			p.depth=qcam->bpp;
-			p.palette=VIDEO_PALETTE_GREY;
-			if(copy_to_user(arg, &p, sizeof(p)))
-				return -EFAULT;
+			struct video_picture *p = arg;
+			p->colour=0x8000;
+			p->hue=0x8000;
+			p->brightness=qcam->brightness<<8;
+			p->contrast=qcam->contrast<<8;
+			p->whiteness=qcam->whitebal<<8;
+			p->depth=qcam->bpp;
+			p->palette=VIDEO_PALETTE_GREY;
 			return 0;
 		}
 		case VIDIOCSPICT:
 		{
-			struct video_picture p;
-			if(copy_from_user(&p, arg, sizeof(p)))
-				return -EFAULT;
-			if(p.palette!=VIDEO_PALETTE_GREY)
+			struct video_picture *p = arg;
+			if(p->palette!=VIDEO_PALETTE_GREY)
 			    	return -EINVAL;
-			if(p.depth!=4 && p.depth!=6)
+			if(p->depth!=4 && p->depth!=6)
 				return -EINVAL;
 			
 			/*
 			 *	Now load the camera.
 			 */
 
-			qcam->brightness = p.brightness>>8;
-			qcam->contrast = p.contrast>>8;
-			qcam->whitebal = p.whiteness>>8;
-			qcam->bpp = p.depth;
+			qcam->brightness = p->brightness>>8;
+			qcam->contrast = p->contrast>>8;
+			qcam->whitebal = p->whiteness>>8;
+			qcam->bpp = p->depth;
 
 			down(&qcam->lock);			
 			qc_setscanmode(qcam);
@@ -823,27 +795,25 @@
 		}
 		case VIDIOCSWIN:
 		{
-			struct video_window vw;
-			if(copy_from_user(&vw, arg,sizeof(vw)))
-				return -EFAULT;
-			if(vw.flags)
+			struct video_window *vw = arg;
+			if(vw->flags)
 				return -EINVAL;
-			if(vw.clipcount)
+			if(vw->clipcount)
 				return -EINVAL;
-			if(vw.height<60||vw.height>240)
+			if(vw->height<60||vw->height>240)
 				return -EINVAL;
-			if(vw.width<80||vw.width>320)
+			if(vw->width<80||vw->width>320)
 				return -EINVAL;
 				
 			qcam->width = 320;
 			qcam->height = 240;
 			qcam->transfer_scale = 4;
 			
-			if(vw.width>=160 && vw.height>=120)
+			if(vw->width>=160 && vw->height>=120)
 			{
 				qcam->transfer_scale = 2;
 			}
-			if(vw.width>=320 && vw.height>=240)
+			if(vw->width>=320 && vw->height>=240)
 			{
 				qcam->width = 320;
 				qcam->height = 240;
@@ -862,28 +832,20 @@
 		}
 		case VIDIOCGWIN:
 		{
-			struct video_window vw;
-			memset(&vw, 0, sizeof(vw));
-			vw.width=qcam->width/qcam->transfer_scale;
-			vw.height=qcam->height/qcam->transfer_scale;
-			if(copy_to_user(arg, &vw, sizeof(vw)))
-				return -EFAULT;
+			struct video_window *vw = arg;
+			memset(vw, 0, sizeof(*vw));
+			vw->width=qcam->width/qcam->transfer_scale;
+			vw->height=qcam->height/qcam->transfer_scale;
 			return 0;
 		}
+		case VIDIOCKEY:
+			return 0;
 		case VIDIOCCAPTURE:
-			return -EINVAL;
 		case VIDIOCGFBUF:
-			return -EINVAL;
 		case VIDIOCSFBUF:
-			return -EINVAL;
-		case VIDIOCKEY:
-			return 0;
 		case VIDIOCGFREQ:
-			return -EINVAL;
 		case VIDIOCSFREQ:
-			return -EINVAL;
 		case VIDIOCGAUDIO:
-			return -EINVAL;
 		case VIDIOCSAUDIO:
 			return -EINVAL;
 		default:
@@ -892,8 +854,10 @@
 	return 0;
 }
 
-static long qcam_read(struct video_device *v, char *buf, unsigned long count,  int noblock)
+static int qcam_read(struct file *file, char *buf,
+		     size_t count, loff_t *ppos)
 {
+	struct video_device *v = video_devdata(file);
 	struct qcam_device *qcam=(struct qcam_device *)v;
 	int len;
 	parport_claim_or_block(qcam->pdev);
@@ -914,17 +878,22 @@
 	return len;
 }
  
+static struct file_operations qcam_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:          video_generic_ioctl,
+	read:		qcam_read,
+	llseek:         no_llseek,
+};
 static struct video_device qcam_template=
 {
 	owner:		THIS_MODULE,
 	name:		"Connectix Quickcam",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_QCAM_BW,
-	open:		qcam_open,
-	close:		qcam_close,
-	read:		qcam_read,
-	write:		qcam_write,
-	ioctl:		qcam_ioctl,
+	fops:           &qcam_fops,
+	kernel_ioctl:	qcam_ioctl,
 };
 
 #define MAX_CAMS 4
diff -Nru a/drivers/media/video/c-qcam.c b/drivers/media/video/c-qcam.c
--- a/drivers/media/video/c-qcam.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/video/c-qcam.c	Fri Mar 15 17:51:03 2002
@@ -496,125 +496,93 @@
  *	Video4linux interfacing
  */
 
-static int qcam_open(struct video_device *dev, int flags)
-{
-	return 0;
-}
-
-static void qcam_close(struct video_device *dev)
-{
-}
-
-static long qcam_write(struct video_device *v, const char *buf, unsigned long count, int noblock)
-{
-	return -EINVAL;
-}
-
-static int qcam_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int qcam_ioctl(struct inode *inode, struct file *file,
+		      unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct qcam_device *qcam=(struct qcam_device *)dev;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability b;
-			strcpy(b.name, "Quickcam");
-			b.type = VID_TYPE_CAPTURE|VID_TYPE_SCALES;
-			b.channels = 1;
-			b.audios = 0;
-			b.maxwidth = 320;
-			b.maxheight = 240;
-			b.minwidth = 80;
-			b.minheight = 60;
-			if(copy_to_user(arg, &b,sizeof(b)))
-				return -EFAULT;
+			struct video_capability *b = arg;
+			strcpy(b->name, "Quickcam");
+			b->type = VID_TYPE_CAPTURE|VID_TYPE_SCALES;
+			b->channels = 1;
+			b->audios = 0;
+			b->maxwidth = 320;
+			b->maxheight = 240;
+			b->minwidth = 80;
+			b->minheight = 60;
 			return 0;
 		}
 		case VIDIOCGCHAN:
 		{
-			struct video_channel v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.channel!=0)
+			struct video_channel *v = arg;
+			if(v->channel!=0)
 				return -EINVAL;
-			v.flags=0;
-			v.tuners=0;
+			v->flags=0;
+			v->tuners=0;
 			/* Good question.. its composite or SVHS so.. */
-			v.type = VIDEO_TYPE_CAMERA;
-			strcpy(v.name, "Camera");
-			if(copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			v->type = VIDEO_TYPE_CAMERA;
+			strcpy(v->name, "Camera");
 			return 0;
 		}
 		case VIDIOCSCHAN:
 		{
-			int v;
-			if(copy_from_user(&v, arg,sizeof(v)))
-				return -EFAULT;
-			if(v!=0)
+			struct video_channel *v = arg;
+			if(v->channel!=0)
 				return -EINVAL;
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
-				return -EINVAL;
-			strcpy(v.name, "Format");
-			v.rangelow=0;
-			v.rangehigh=0;
-			v.flags= 0;
-			v.mode = VIDEO_MODE_AUTO;
-			if(copy_to_user(arg,&v,sizeof(v))!=0)
-				return -EFAULT;
+			struct video_tuner *v = arg;
+			if(v->tuner)
+				return -EINVAL;
+			memset(v,0,sizeof(*v));
+			strcpy(v->name, "Format");
+			v->mode = VIDEO_MODE_AUTO;
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
+			struct video_tuner *v = arg;
+			if(v->tuner)
 				return -EINVAL;
-			if(v.mode!=VIDEO_MODE_AUTO)
+			if(v->mode!=VIDEO_MODE_AUTO)
 				return -EINVAL;
 			return 0;
 		}
 		case VIDIOCGPICT:
 		{
-			struct video_picture p;
-			p.colour=0x8000;
-			p.hue=0x8000;
-			p.brightness=qcam->brightness<<8;
-			p.contrast=qcam->contrast<<8;
-			p.whiteness=qcam->whitebal<<8;
-			p.depth=24;
-			p.palette=VIDEO_PALETTE_RGB24;
-			if(copy_to_user(arg, &p, sizeof(p)))
-				return -EFAULT;
+			struct video_picture *p = arg;
+			p->colour=0x8000;
+			p->hue=0x8000;
+			p->brightness=qcam->brightness<<8;
+			p->contrast=qcam->contrast<<8;
+			p->whiteness=qcam->whitebal<<8;
+			p->depth=24;
+			p->palette=VIDEO_PALETTE_RGB24;
 			return 0;
 		}
 		case VIDIOCSPICT:
 		{
-			struct video_picture p;
-			if(copy_from_user(&p, arg, sizeof(p)))
-				return -EFAULT;
+			struct video_picture *p = arg;
 
 			/*
 			 *	Sanity check args
 			 */
-			if (p.depth != 24 || p.palette != VIDEO_PALETTE_RGB24)
+			if (p->depth != 24 || p->palette != VIDEO_PALETTE_RGB24)
 				return -EINVAL;
 			
 			/*
 			 *	Now load the camera.
 			 */
-			qcam->brightness = p.brightness>>8;
-			qcam->contrast = p.contrast>>8;
-			qcam->whitebal = p.whiteness>>8;
+			qcam->brightness = p->brightness>>8;
+			qcam->contrast = p->contrast>>8;
+			qcam->whitebal = p->whiteness>>8;
 
 			down(&qcam->lock);			
 			parport_claim_or_block(qcam->pdev);
@@ -625,30 +593,28 @@
 		}
 		case VIDIOCSWIN:
 		{
-			struct video_window vw;
+			struct video_window *vw = arg;
 
-			if(copy_from_user(&vw, arg,sizeof(vw)))
-				return -EFAULT;
-			if(vw.flags)
+			if(vw->flags)
 				return -EINVAL;
-			if(vw.clipcount)
+			if(vw->clipcount)
 				return -EINVAL;
-			if(vw.height<60||vw.height>240)
+			if(vw->height<60||vw->height>240)
 				return -EINVAL;
-			if(vw.width<80||vw.width>320)
+			if(vw->width<80||vw->width>320)
 				return -EINVAL;
 				
 			qcam->width = 80;
 			qcam->height = 60;
 			qcam->mode = QC_DECIMATION_4;
 			
-			if(vw.width>=160 && vw.height>=120)
+			if(vw->width>=160 && vw->height>=120)
 			{
 				qcam->width = 160;
 				qcam->height = 120;
 				qcam->mode = QC_DECIMATION_2;
 			}
-			if(vw.width>=320 && vw.height>=240)
+			if(vw->width>=320 && vw->height>=240)
 			{
 				qcam->width = 320;
 				qcam->height = 240;
@@ -656,7 +622,7 @@
 			}
 			qcam->mode |= QC_MILLIONS;
 #if 0
-			if(vw.width>=640 && vw.height>=480)
+			if(vw->width>=640 && vw->height>=480)
 			{
 				qcam->width = 640;
 				qcam->height = 480;
@@ -674,28 +640,20 @@
 		}
 		case VIDIOCGWIN:
 		{
-			struct video_window vw;
-			memset(&vw, 0, sizeof(vw));
-			vw.width=qcam->width;
-			vw.height=qcam->height;
-			if(copy_to_user(arg, &vw, sizeof(vw)))
-				return -EFAULT;
+			struct video_window *vw = arg;
+			memset(vw, 0, sizeof(*vw));
+			vw->width=qcam->width;
+			vw->height=qcam->height;
 			return 0;
 		}
+		case VIDIOCKEY:
+			return 0;
 		case VIDIOCCAPTURE:
-			return -EINVAL;
 		case VIDIOCGFBUF:
-			return -EINVAL;
 		case VIDIOCSFBUF:
-			return -EINVAL;
-		case VIDIOCKEY:
-			return 0;
 		case VIDIOCGFREQ:
-			return -EINVAL;
 		case VIDIOCSFREQ:
-			return -EINVAL;
 		case VIDIOCGAUDIO:
-			return -EINVAL;
 		case VIDIOCSAUDIO:
 			return -EINVAL;
 		default:
@@ -704,8 +662,10 @@
 	return 0;
 }
 
-static long qcam_read(struct video_device *v, char *buf, unsigned long count,  int noblock)
+static int qcam_read(struct file *file, char *buf,
+		     size_t count, loff_t *ppos)
 {
+	struct video_device *v = video_devdata(file);
 	struct qcam_device *qcam=(struct qcam_device *)v;
 	int len;
 
@@ -719,17 +679,23 @@
 }
 
 /* video device template */
+static struct file_operations qcam_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:          video_generic_ioctl,
+	read:		qcam_read,
+	llseek:         no_llseek,
+};
+
 static struct video_device qcam_template=
 {
 	owner:		THIS_MODULE,
 	name:		"Colour QuickCam",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_QCAM_C,
-	open:		qcam_open,
-	close:		qcam_close,
-	read:		qcam_read,
-	write:		qcam_write,
-	ioctl:		qcam_ioctl,
+	fops:           &qcam_fops,
+	kernel_ioctl:	qcam_ioctl,
 };
 
 /* Initialize the QuickCam driver control structure. */
diff -Nru a/drivers/media/video/cpia.c b/drivers/media/video/cpia.c
--- a/drivers/media/video/cpia.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/video/cpia.c	Fri Mar 15 17:51:03 2002
@@ -2396,53 +2396,46 @@
 }
 
 /* ------------------------- V4L interface --------------------- */
-static int cpia_open(struct video_device *dev, int flags)
+static int cpia_open(struct inode *inode, struct file *file)
 {
-	int i;
+	struct video_device *dev = video_devdata(file);
 	struct cam_data *cam = dev->priv;
+	int err;
 
 	if (!cam) {
 		DBG("Internal error, cam_data not found!\n");
-		return -EBUSY;
+		return -ENODEV;
 	}
 	    
+	down(&cam->busy_lock);
+	err = -EBUSY;
 	if (cam->open_count > 0) {
 		DBG("Camera already open\n");
-		return -EBUSY;
+		goto oops;
 	}
 	
+	err = -ENOMEM;
 	if (!cam->raw_image) {
 		cam->raw_image = rvmalloc(CPIA_MAX_IMAGE_SIZE);
 		if (!cam->raw_image)
-			return -ENOMEM;
+			goto oops;
 	}
 
 	if (!cam->decompressed_frame.data) {
 		cam->decompressed_frame.data = rvmalloc(CPIA_MAX_FRAME_SIZE);
-		if (!cam->decompressed_frame.data) {
-			rvfree(cam->raw_image, CPIA_MAX_IMAGE_SIZE);
-			cam->raw_image = NULL;
-			return -ENOMEM;
-		}
+		if (!cam->decompressed_frame.data)
+			goto oops;
 	}
 	
 	/* open cpia */
-	if (cam->ops->open(cam->lowlevel_data)) {
-		rvfree(cam->decompressed_frame.data, CPIA_MAX_FRAME_SIZE);
-		cam->decompressed_frame.data = NULL;
-		rvfree(cam->raw_image, CPIA_MAX_IMAGE_SIZE);
-		cam->raw_image = NULL;
-		return -ENODEV;
-	}
+	err = -ENODEV;
+	if (cam->ops->open(cam->lowlevel_data))
+		goto oops;
 	
 	/* reset the camera */
-	if ((i = reset_camera(cam)) != 0) {
+	if ((err = reset_camera(cam)) != 0) {
 		cam->ops->close(cam->lowlevel_data);
-		rvfree(cam->decompressed_frame.data, CPIA_MAX_FRAME_SIZE);
-		cam->decompressed_frame.data = NULL;
-		rvfree(cam->raw_image, CPIA_MAX_IMAGE_SIZE);
-		cam->raw_image = NULL;
-		return i;
+		goto oops;
 	}
 	
 	/* Set ownership of /proc/cpia/videoX to current user */
@@ -2456,14 +2449,26 @@
 	cam->mmap_kludge = 0;
 	
 	++cam->open_count;
+	file->private_data = dev;
 	return 0;
+
+ oops:
+	if (cam->decompressed_frame.data) {
+		rvfree(cam->decompressed_frame.data, CPIA_MAX_FRAME_SIZE);
+		cam->decompressed_frame.data = NULL;
+	}
+	if (cam->raw_image) {
+		rvfree(cam->raw_image, CPIA_MAX_IMAGE_SIZE);
+		cam->raw_image = NULL;
+	}
+	up(&cam->busy_lock);
+	return err;
 }
 
-static void cpia_close(struct video_device *dev)
+static int cpia_close(struct inode *inode, struct file *file)
 {
-	struct cam_data *cam;
-
-	cam = dev->priv;
+	struct  video_device *dev = file->private_data;
+	struct cam_data *cam = dev->priv;
 
 	if (cam->ops) {
 	        /* Return ownership of /proc/cpia/videoX to root */
@@ -2501,19 +2506,18 @@
 		if (cam->frame_buf)
 			free_frame_buf(cam);
 
-		if (!cam->ops) {
-			video_unregister_device(dev);
+		if (!cam->ops)
 			kfree(cam);
-		}
 	}
-	
+	file->private_data = NULL;
 
-	return;
+	return 0;
 }
 
-static long cpia_read(struct video_device *dev, char *buf,
-                      unsigned long count, int noblock)
+static int cpia_read(struct file *file, char *buf,
+		     size_t count, loff_t *ppos)
 {
+	struct video_device *dev = file->private_data;
 	struct cam_data *cam = dev->priv;
 
 	/* make this _really_ smp and multithredi-safe */
@@ -2568,8 +2572,10 @@
 	return cam->decompressed_frame.count;
 }
 
-static int cpia_ioctl(struct video_device *dev, unsigned int ioctlnr, void *arg)
+static int cpia_ioctl(struct inode *inode, struct file *file,
+		      unsigned int ioctlnr, void *arg)
 {
+	struct video_device *dev = file->private_data;
 	struct cam_data *cam = dev->priv;
 	int retval = 0;
 
@@ -2586,99 +2592,80 @@
 	/* query capabilites */
 	case VIDIOCGCAP:
 	{
-		struct video_capability b;
+		struct video_capability *b = arg;
 
 		DBG("VIDIOCGCAP\n");
-		strcpy(b.name, "CPiA Camera");
-		b.type = VID_TYPE_CAPTURE;
-		b.channels = 1;
-		b.audios = 0;
-		b.maxwidth = 352;	/* VIDEOSIZE_CIF */
-		b.maxheight = 288;
-		b.minwidth = 48;	/* VIDEOSIZE_48_48 */
-		b.minheight = 48;
-
-		if (copy_to_user(arg, &b, sizeof(b)))
-			retval = -EFAULT;
-
+		strcpy(b->name, "CPiA Camera");
+		b->type = VID_TYPE_CAPTURE;
+		b->channels = 1;
+		b->audios = 0;
+		b->maxwidth = 352;	/* VIDEOSIZE_CIF */
+		b->maxheight = 288;
+		b->minwidth = 48;	/* VIDEOSIZE_48_48 */
+		b->minheight = 48;
 		break;
 	}
 
 	/* get/set video source - we are a camera and nothing else */
 	case VIDIOCGCHAN:
 	{
-		struct video_channel v;
+		struct video_channel *v = arg;
 
 		DBG("VIDIOCGCHAN\n");
-		if (copy_from_user(&v, arg, sizeof(v))) {
-			retval = -EFAULT;
-			break;
-		}
-		if (v.channel != 0) {
+		if (v->channel != 0) {
 			retval = -EINVAL;
 			break;
 		}
 
-		v.channel = 0;
-		strcpy(v.name, "Camera");
-		v.tuners = 0;
-		v.flags = 0;
-		v.type = VIDEO_TYPE_CAMERA;
-		v.norm = 0;
-
-		if (copy_to_user(arg, &v, sizeof(v)))
-			retval = -EFAULT;
+		v->channel = 0;
+		strcpy(v->name, "Camera");
+		v->tuners = 0;
+		v->flags = 0;
+		v->type = VIDEO_TYPE_CAMERA;
+		v->norm = 0;
 		break;
 	}
 	
 	case VIDIOCSCHAN:
 	{
-		int v;
+		struct video_channel *v = arg;
 
 		DBG("VIDIOCSCHAN\n");
-		if (copy_from_user(&v, arg, sizeof(v)))
-			retval = -EFAULT;
-
-		if (retval == 0 && v != 0)
+		if (v->channel != 0)
 			retval = -EINVAL;
-
 		break;
 	}
 
 	/* image properties */
 	case VIDIOCGPICT:
+	{
+		struct video_picture *pic = arg;
 		DBG("VIDIOCGPICT\n");
-		if (copy_to_user(arg, &cam->vp, sizeof(struct video_picture)))
-			retval = -EFAULT;
+		*pic = cam->vp;
 		break;
+	}
 	
 	case VIDIOCSPICT:
 	{
-		struct video_picture vp;
+		struct video_picture *vp = arg;
 
 		DBG("VIDIOCSPICT\n");
 
-		/* copy_from_user */
-		if (copy_from_user(&vp, arg, sizeof(vp))) {
-			retval = -EFAULT;
-			break;
-		}
-
 		/* check validity */
 		DBG("palette: %d\n", vp.palette);
 		DBG("depth: %d\n", vp.depth);
-		if (!valid_mode(vp.palette, vp.depth)) {
+		if (!valid_mode(vp->palette, vp->depth)) {
 			retval = -EINVAL;
 			break;
 		}
 
 		down(&cam->param_lock);
 		/* brightness, colour, contrast need no check 0-65535 */
-		memcpy( &cam->vp, &vp, sizeof(vp) );
+		cam->vp = *vp;
 		/* update cam->params.colourParams */
-		cam->params.colourParams.brightness = vp.brightness*100/65535;
-		cam->params.colourParams.contrast = vp.contrast*100/65535;
-		cam->params.colourParams.saturation = vp.colour*100/65535;
+		cam->params.colourParams.brightness = vp->brightness*100/65535;
+		cam->params.colourParams.contrast = vp->contrast*100/65535;
+		cam->params.colourParams.saturation = vp->colour*100/65535;
 		/* contrast is in steps of 8, so round */
 		cam->params.colourParams.contrast =
 			((cam->params.colourParams.contrast + 3) / 8) * 8;
@@ -2693,34 +2680,32 @@
 		cam->cmd_queue |= COMMAND_SETCOLOURPARAMS;
 		up(&cam->param_lock);
 		DBG("VIDIOCSPICT: %d / %d // %d / %d / %d / %d\n",
-		    vp.depth, vp.palette, vp.brightness, vp.hue, vp.colour,
-		    vp.contrast);
+		    vp->depth, vp->palette, vp->brightness, vp->hue, vp->colour,
+		    vp->contrast);
 		break;
 	}
 
 	/* get/set capture window */
 	case VIDIOCGWIN:
+	{
+		struct video_window *vw = arg;
 		DBG("VIDIOCGWIN\n");
 
-		if (copy_to_user(arg, &cam->vw, sizeof(struct video_window)))
-			retval = -EFAULT;
+		*vw = cam->vw;
 		break;
+	}
 	
 	case VIDIOCSWIN:
 	{
 		/* copy_from_user, check validity, copy to internal structure */
-		struct video_window vw;
+		struct video_window *vw = arg;
 		DBG("VIDIOCSWIN\n");
-		if (copy_from_user(&vw, arg, sizeof(vw))) {
-			retval = -EFAULT;
-			break;
-		}
 
-		if (vw.clipcount != 0) {    /* clipping not supported */
+		if (vw->clipcount != 0) {    /* clipping not supported */
 			retval = -EINVAL;
 			break;
 		}
-		if (vw.clips != NULL) {     /* clipping not supported */
+		if (vw->clips != NULL) {     /* clipping not supported */
 			retval = -EINVAL;
 			break;
 		}
@@ -2729,8 +2714,8 @@
 		* is requested by the user???
 		*/
 		down(&cam->param_lock);
-		if (vw.width != cam->vw.width || vw.height != cam->vw.height) {
-			int video_size = match_videosize(vw.width, vw.height);
+		if (vw->width != cam->vw.width || vw->height != cam->vw.height) {
+			int video_size = match_videosize(vw->width, vw->height);
 
 			if (video_size < 0) {
 				retval = -EINVAL;
@@ -2760,43 +2745,35 @@
 	/* mmap interface */
 	case VIDIOCGMBUF:
 	{
-		struct video_mbuf vm;
+		struct video_mbuf *vm = arg;
 		int i;
 
 		DBG("VIDIOCGMBUF\n");
-		memset(&vm, 0, sizeof(vm));
-		vm.size = CPIA_MAX_FRAME_SIZE*FRAME_NUM;
-		vm.frames = FRAME_NUM;
+		memset(vm, 0, sizeof(*vm));
+		vm->size = CPIA_MAX_FRAME_SIZE*FRAME_NUM;
+		vm->frames = FRAME_NUM;
 		for (i = 0; i < FRAME_NUM; i++)
-			vm.offsets[i] = CPIA_MAX_FRAME_SIZE * i;
-
-		if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-			retval = -EFAULT;
-
+			vm->offsets[i] = CPIA_MAX_FRAME_SIZE * i;
 		break;
 	}
 	
 	case VIDIOCMCAPTURE:
 	{
-		struct video_mmap vm;
+		struct video_mmap *vm = arg;
 		int video_size;
 
-		if (copy_from_user((void *)&vm, (void *)arg, sizeof(vm))) {
-			retval = -EFAULT;
-			break;
-		}
 #if 1
-		DBG("VIDIOCMCAPTURE: %d / %d / %dx%d\n", vm.format, vm.frame,
-		    vm.width, vm.height);
+		DBG("VIDIOCMCAPTURE: %d / %d / %dx%d\n", vm->format, vm->frame,
+		    vm->width, vm->height);
 #endif
-		if (vm.frame<0||vm.frame>=FRAME_NUM) {
+		if (vm->frame<0||vm->frame>=FRAME_NUM) {
 			retval = -EINVAL;
 			break;
 		}
 
 		/* set video format */
-		cam->vp.palette = vm.format;
-		switch(vm.format) {
+		cam->vp.palette = vm->format;
+		switch(vm->format) {
 		case VIDEO_PALETTE_GREY:
 		case VIDEO_PALETTE_RGB555:
 		case VIDEO_PALETTE_RGB565:
@@ -2819,7 +2796,7 @@
 			break;
 
 		/* set video size */
-		video_size = match_videosize(vm.width, vm.height);
+		video_size = match_videosize(vm->width, vm->height);
 		if (video_size < 0) {
 			retval = -EINVAL;
 			break;
@@ -2836,37 +2813,33 @@
 #endif
 		/* according to v4l-spec we must start streaming here */
 		cam->mmap_kludge = 1;
-		retval = capture_frame(cam, &vm);
+		retval = capture_frame(cam, vm);
 
 		break;
 	}
 	
 	case VIDIOCSYNC:
 	{
-		int frame;
+		int *frame = arg;
 
-		if (copy_from_user((void *)&frame, arg, sizeof(int))) {
-			retval = -EFAULT;
-			break;
-		}
 		//DBG("VIDIOCSYNC: %d\n", frame);
 
-		if (frame<0 || frame >= FRAME_NUM) {
+		if (*frame<0 || *frame >= FRAME_NUM) {
 			retval = -EINVAL;
 			break;
 		}
 
-		switch (cam->frame[frame].state) {
+		switch (cam->frame[*frame].state) {
 		case FRAME_UNUSED:
 		case FRAME_READY:
 		case FRAME_GRABBING:
-			DBG("sync to unused frame %d\n", frame);
+			DBG("sync to unused frame %d\n", *frame);
 			retval = -EINVAL;
 			break;
 
 		case FRAME_DONE:
-			cam->frame[frame].state = FRAME_UNUSED;
-			//DBG("VIDIOCSYNC: %d synced\n", frame);
+			cam->frame[*frame].state = FRAME_UNUSED;
+			//DBG("VIDIOCSYNC: %d synced\n", *frame);
 			break;
 		}
 		if (retval == -EINTR) {
@@ -2878,36 +2851,16 @@
 
 	/* pointless to implement overlay with this camera */
 	case VIDIOCCAPTURE:
-		retval = -EINVAL;
-		break;
 	case VIDIOCGFBUF:
-		retval = -EINVAL;
-		break;
 	case VIDIOCSFBUF:
-		retval = -EINVAL;
-		break;
 	case VIDIOCKEY:
-		retval = -EINVAL;
-		break;
-
 	/* tuner interface - we have none */
 	case VIDIOCGTUNER:
-		retval = -EINVAL;
-		break;
 	case VIDIOCSTUNER:
-		retval = -EINVAL;
-		break;
 	case VIDIOCGFREQ:
-		retval = -EINVAL;
-		break;
 	case VIDIOCSFREQ:
-		retval = -EINVAL;
-		break;
-
 	/* audio interface - we have none */
 	case VIDIOCGAUDIO:
-		retval = -EINVAL;
-		break;
 	case VIDIOCSAUDIO:
 		retval = -EINVAL;
 		break;
@@ -2922,10 +2875,11 @@
 } 
 
 /* FIXME */
-static int cpia_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr,
-                     unsigned long size)
+static int cpia_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	unsigned long start = (unsigned long)adr;
+	struct video_device *dev = file->private_data;
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end-vma->vm_start;
 	unsigned long page, pos;
 	struct cam_data *cam = dev->priv;
 	int retval;
@@ -2973,26 +2927,23 @@
 	return 0;
 }
 
-int cpia_video_init(struct video_device *vdev)
-{
-#ifdef CONFIG_PROC_FS
-	create_proc_cpia_cam(vdev->priv);
-#endif
-	return 0;
-}
+static struct file_operations cpia_fops = {
+	owner:		THIS_MODULE,
+	open:		cpia_open,
+	release:       	cpia_close,
+	read:		cpia_read,
+	mmap:		cpia_mmap,
+	ioctl:          video_generic_ioctl,
+	llseek:         no_llseek,
+};
 
 static struct video_device cpia_template = {
 	owner:		THIS_MODULE,
 	name:		"CPiA Camera",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_CPIA,      /* FIXME */
-	open:		cpia_open,
-	close:		cpia_close,
-	read:		cpia_read,
-	ioctl:		cpia_ioctl,
-	mmap:		cpia_mmap,
-	initialize:	cpia_video_init,
-	minor:		-1,
+	fops:           &cpia_fops,
+	kernel_ioctl:	cpia_ioctl,
 };
 
 /* initialise cam_data structure  */
@@ -3143,6 +3094,9 @@
 		printk(KERN_DEBUG "video_register_device failed\n");
 		return NULL;
 	}
+#ifdef CONFIG_PROC_FS
+	create_proc_cpia_cam(camera);
+#endif
 
 	/* get version information from camera: open/reset/close */
 
@@ -3184,12 +3138,9 @@
 
 void cpia_unregister_camera(struct cam_data *cam)
 {
-	if (!cam->open_count) {
-		DBG("unregistering video\n");
-		video_unregister_device(&cam->vdev);
-	} else {
-		LOG("/dev/video%d removed while open, "
-		    "deferring video_unregister_device\n", cam->vdev.minor);
+	DBG("unregistering video\n");
+	video_unregister_device(&cam->vdev);
+	if (cam->open_count) {
 		DBG("camera open -- setting ops to NULL\n");
 		cam->ops = NULL;
 	}
diff -Nru a/drivers/media/video/id.h b/drivers/media/video/id.h
--- a/drivers/media/video/id.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/video/id.h	Fri Mar 15 17:51:03 2002
@@ -24,6 +24,12 @@
 #ifndef  I2C_DRIVERID_TDA7432
 # define I2C_DRIVERID_TDA7432 I2C_DRIVERID_EXP0+6
 #endif
-#ifndef  I2C_DRIVERID_TDA9874A
-# define I2C_DRIVERID_TDA9874A I2C_DRIVERID_EXP0+7
+#ifndef  I2C_DRIVERID_TDA9874
+# define I2C_DRIVERID_TDA9874 I2C_DRIVERID_EXP0+7
 #endif
+
+/* algorithms */
+#ifndef I2C_ALGO_SAA7134
+# define I2C_ALGO_SAA7134 0x090000
+#endif
+
diff -Nru a/drivers/media/video/meye.c b/drivers/media/video/meye.c
--- a/drivers/media/video/meye.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/video/meye.c	Fri Mar 15 17:51:01 2002
@@ -868,124 +868,108 @@
 /* video4linux integration                                                  */
 /****************************************************************************/
 
-static int meye_open(struct video_device *dev, int flags) {
-	int i;
+static int meye_open(struct inode *inode, struct file *file) {
+	int i, err;
 
-	down(&meye.lock);
-	if (meye.open_count) {
-		up(&meye.lock);
-		return -EBUSY;
-	}
-	meye.open_count++;
+	err = video_exclusive_open(inode,file);
+	if (err < 0)
+		return err;
+			
 	if (mchip_dma_alloc()) {
 		printk(KERN_ERR "meye: mchip framebuffer allocation failed\n");
-		up(&meye.lock);
+		video_exclusive_release(inode,file);
 		return -ENOBUFS;
 	}
 	mchip_hic_stop();
 	meye_initq(&meye.grabq);
 	for (i = 0; i < MEYE_MAX_BUFNBRS; i++)
 		meye.grab_buffer[i].state = MEYE_BUF_UNUSED;
-	up(&meye.lock);
 	return 0;
 }
 
-static void meye_close(struct video_device *dev) {
-	down(&meye.lock);
-	meye.open_count--;
+static int meye_release(struct inode *inode, struct file *file) {
 	mchip_hic_stop();
-	up(&meye.lock);
+	video_exclusive_release(inode,file);
+	return 0;
 }
 
-static int meye_ioctl(struct video_device *dev, unsigned int cmd, void *arg) {
+static int meye_ioctl(struct inode *inode, struct file *file,
+		      unsigned int cmd, void *arg) {
 
 	switch (cmd) {
 
 	case VIDIOCGCAP: {
-		struct video_capability b;
-		strcpy(b.name,meye.video_dev.name);
-		b.type = VID_TYPE_CAPTURE;
-		b.channels = 1;
-		b.audios = 0;
-		b.maxwidth = 640;
-		b.maxheight = 480;
-		b.minwidth = 320;
-		b.minheight = 240;
-		if(copy_to_user(arg,&b,sizeof(b)))
-			return -EFAULT;
+		struct video_capability *b = arg;
+		strcpy(b->name,meye.video_dev.name);
+		b->type = VID_TYPE_CAPTURE;
+		b->channels = 1;
+		b->audios = 0;
+		b->maxwidth = 640;
+		b->maxheight = 480;
+		b->minwidth = 320;
+		b->minheight = 240;
 		break;
 	}
 
 	case VIDIOCGCHAN: {
-		struct video_channel v;
-		if(copy_from_user(&v, arg,sizeof(v)))
-			return -EFAULT;
-		v.flags = 0;
-		v.tuners = 0;
-		v.type = VIDEO_TYPE_CAMERA;
-		if (v.channel != 0)
-			return -EINVAL;
-		strcpy(v.name,"Camera");
-		if(copy_to_user(arg,&v,sizeof(v)))
-			return -EFAULT;
+		struct video_channel *v = arg;
+		v->flags = 0;
+		v->tuners = 0;
+		v->type = VIDEO_TYPE_CAMERA;
+		if (v->channel != 0)
+			return -EINVAL;
+		strcpy(v->name,"Camera");
 		break;
 	}
 
 	case VIDIOCSCHAN: {
-		struct video_channel v;
-		if(copy_from_user(&v, arg,sizeof(v)))
-			return -EFAULT;
-		if (v.channel != 0)
+		struct video_channel *v = arg;
+		if (v->channel != 0)
 			return -EINVAL;
 		break;
 	}
 
 	case VIDIOCGPICT: {
-		struct video_picture p = meye.picture;
-		if(copy_to_user(arg, &p, sizeof(p)))
-			return -EFAULT;
+		struct video_picture *p = arg;
+		*p = meye.picture;
 		break;
 	}
 
 	case VIDIOCSPICT: {
-		struct video_picture p;
-		if(copy_from_user(&p, arg,sizeof(p)))
-			return -EFAULT;
-		if (p.depth != 2)
+		struct video_picture *p = arg;
+		if (p->depth != 2)
 			return -EINVAL;
-		if (p.palette != VIDEO_PALETTE_YUV422)
+		if (p->palette != VIDEO_PALETTE_YUV422)
 			return -EINVAL;
 		down(&meye.lock);
 		sonypi_camera_command(SONYPI_COMMAND_SETCAMERABRIGHTNESS, 
-				      p.brightness >> 10);
+				      p->brightness >> 10);
 		sonypi_camera_command(SONYPI_COMMAND_SETCAMERAHUE, 
-				      p.hue >> 10);
+				      p->hue >> 10);
 		sonypi_camera_command(SONYPI_COMMAND_SETCAMERACOLOR, 
-				      p.colour >> 10);
+				      p->colour >> 10);
 		sonypi_camera_command(SONYPI_COMMAND_SETCAMERACONTRAST, 
-				      p.contrast >> 10);
-		memcpy(&meye.picture, &p, sizeof(p));
+				      p->contrast >> 10);
+		meye.picture = *p;
 		up(&meye.lock);
 		break;
 	}
 
 	case VIDIOCSYNC: {
-		int i;
+		int *i = arg;
 		DECLARE_WAITQUEUE(wait, current);
 
-		if(copy_from_user((void *)&i,arg,sizeof(int)))
-			return -EFAULT;
-		if (i < 0 || i >= gbuffers)
+		if (*i < 0 || *i >= gbuffers)
 			return -EINVAL;
 
-		switch (meye.grab_buffer[i].state) {
+		switch (meye.grab_buffer[*i].state) {
 
 		case MEYE_BUF_UNUSED:
 			return -EINVAL;
 		case MEYE_BUF_USING:
 			add_wait_queue(&meye.grabq.proc_list, &wait);
 			current->state = TASK_INTERRUPTIBLE;
-			while (meye.grab_buffer[i].state == MEYE_BUF_USING) {
+			while (meye.grab_buffer[*i].state == MEYE_BUF_USING) {
 				schedule();
 				if(signal_pending(current)) {
 					remove_wait_queue(&meye.grabq.proc_list, &wait);
@@ -997,36 +981,34 @@
 			current->state = TASK_RUNNING;
 			/* fall through */
 		case MEYE_BUF_DONE:
-			meye.grab_buffer[i].state = MEYE_BUF_UNUSED;
+			meye.grab_buffer[*i].state = MEYE_BUF_UNUSED;
 		}
 		break;
 	}
 
 	case VIDIOCMCAPTURE: {
-		struct video_mmap vm;
+		struct video_mmap *vm = arg;
 		int restart = 0;
 
-		if(copy_from_user((void *) &vm, (void *) arg, sizeof(vm)))
-			return -EFAULT;
-		if (vm.frame >= gbuffers || vm.frame < 0)
+		if (vm->frame >= gbuffers || vm->frame < 0)
 			return -EINVAL;
-		if (vm.format != VIDEO_PALETTE_YUV422)
+		if (vm->format != VIDEO_PALETTE_YUV422)
 			return -EINVAL;
-		if (vm.height * vm.width * 2 > gbufsize)
+		if (vm->height * vm->width * 2 > gbufsize)
 			return -EINVAL;
 		if (!meye.grab_fbuffer)
 			return -EINVAL;
-		if (meye.grab_buffer[vm.frame].state != MEYE_BUF_UNUSED)
+		if (meye.grab_buffer[vm->frame].state != MEYE_BUF_UNUSED)
 			return -EBUSY;
 
 		down(&meye.lock);
-		if (vm.width == 640 && vm.height == 480) {
+		if (vm->width == 640 && vm->height == 480) {
 			if (meye.params.subsample) {
 				meye.params.subsample = 0;
 				restart = 1;
 			}
 		}
-		else if (vm.width == 320 && vm.height == 240) {
+		else if (vm->width == 320 && vm->height == 240) {
 			if (!meye.params.subsample) {
 				meye.params.subsample = 1;
 				restart = 1;
@@ -1039,49 +1021,45 @@
 
 		if (restart || meye.mchip_mode != MCHIP_HIC_MODE_CONT_OUT)
 			mchip_continuous_start();
-		meye.grab_buffer[vm.frame].state = MEYE_BUF_USING;
-		meye_pushq(&meye.grabq, vm.frame);
+		meye.grab_buffer[vm->frame].state = MEYE_BUF_USING;
+		meye_pushq(&meye.grabq, vm->frame);
 		up(&meye.lock);
 		break;
 	}
 
 	case VIDIOCGMBUF: {
-		struct video_mbuf vm;
+		struct video_mbuf *vm = arg;
 		int i;
 
-		memset(&vm, 0 , sizeof(vm));
-		vm.size = gbufsize * gbuffers;
-		vm.frames = gbuffers;
+		memset(vm, 0 , sizeof(*vm));
+		vm->size = gbufsize * gbuffers;
+		vm->frames = gbuffers;
 		for (i = 0; i < gbuffers; i++)
-			vm.offsets[i] = i * gbufsize;
-		if(copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-			return -EFAULT;
+			vm->offsets[i] = i * gbufsize;
 		break;
 	}
 
 	case MEYEIOC_G_PARAMS: {
-		if (copy_to_user(arg, &meye.params, sizeof(meye.params)))
-			return -EFAULT;
+		struct meye_params *p = arg;
+		*p = meye.params;
 		break;
 	}
 
 	case MEYEIOC_S_PARAMS: {
-		struct meye_params jp;
-		if (copy_from_user(&jp, arg, sizeof(jp)))
-			return -EFAULT;
-		if (jp.subsample > 1)
+		struct meye_params *jp = arg;
+		if (jp->subsample > 1)
 			return -EINVAL;
-		if (jp.quality > 10)
+		if (jp->quality > 10)
 			return -EINVAL;
-		if (jp.sharpness > 63 || jp.agc > 63 || jp.picture > 63)
+		if (jp->sharpness > 63 || jp->agc > 63 || jp->picture > 63)
 			return -EINVAL;
-		if (jp.framerate > 31)
+		if (jp->framerate > 31)
 			return -EINVAL;
 		down(&meye.lock);
-		if (meye.params.subsample != jp.subsample ||
-		    meye.params.quality != jp.quality)
+		if (meye.params.subsample != jp->subsample ||
+		    meye.params.quality != jp->quality)
 			mchip_hic_stop();	/* need restart */
-		memcpy(&meye.params, &jp, sizeof(jp));
+		meye.params = *jp;
 		sonypi_camera_command(SONYPI_COMMAND_SETCAMERASHARPNESS,
 				      meye.params.sharpness);
 		sonypi_camera_command(SONYPI_COMMAND_SETCAMERAAGC,
@@ -1093,48 +1071,43 @@
 	}
 
 	case MEYEIOC_QBUF_CAPT: {
-		int nb;
-
-		if (copy_from_user((void *) &nb, (void *) arg, sizeof(int)))
-			return -EFAULT;
+		int *nb = arg;
 
 		if (!meye.grab_fbuffer) 
 			return -EINVAL;
-		if (nb >= gbuffers)
+		if (*nb >= gbuffers)
 			return -EINVAL;
-		if (nb < 0) {
+		if (*nb < 0) {
 			/* stop capture */
 			mchip_hic_stop();
 			return 0;
 		}
-		if (meye.grab_buffer[nb].state != MEYE_BUF_UNUSED)
+		if (meye.grab_buffer[*nb].state != MEYE_BUF_UNUSED)
 			return -EBUSY;
 		down(&meye.lock);
 		if (meye.mchip_mode != MCHIP_HIC_MODE_CONT_COMP)
 			mchip_cont_compression_start();
-		meye.grab_buffer[nb].state = MEYE_BUF_USING;
-		meye_pushq(&meye.grabq, nb);
+		meye.grab_buffer[*nb].state = MEYE_BUF_USING;
+		meye_pushq(&meye.grabq, *nb);
 		up(&meye.lock);
 		break;
 	}
 
 	case MEYEIOC_SYNC: {
-		int i;
+		int *i = arg;
 		DECLARE_WAITQUEUE(wait, current);
 
-		if(copy_from_user((void *)&i,arg,sizeof(int)))
-			return -EFAULT;
-		if (i < 0 || i >= gbuffers)
+		if (*i < 0 || *i >= gbuffers)
 			return -EINVAL;
 
-		switch (meye.grab_buffer[i].state) {
+		switch (meye.grab_buffer[*i].state) {
 
 		case MEYE_BUF_UNUSED:
 			return -EINVAL;
 		case MEYE_BUF_USING:
 			add_wait_queue(&meye.grabq.proc_list, &wait);
 			current->state = TASK_INTERRUPTIBLE;
-			while (meye.grab_buffer[i].state == MEYE_BUF_USING) {
+			while (meye.grab_buffer[*i].state == MEYE_BUF_USING) {
 				schedule();
 				if(signal_pending(current)) {
 					remove_wait_queue(&meye.grabq.proc_list, &wait);
@@ -1146,11 +1119,9 @@
 			current->state = TASK_RUNNING;
 			/* fall through */
 		case MEYE_BUF_DONE:
-			meye.grab_buffer[i].state = MEYE_BUF_UNUSED;
+			meye.grab_buffer[*i].state = MEYE_BUF_UNUSED;
 		}
-		i = meye.grab_buffer[i].size;
-		if (copy_to_user(arg, (void *)&i, sizeof(int)))
-			return -EFAULT;
+		*i = meye.grab_buffer[*i].size;
 		break;
 	}
 
@@ -1172,7 +1143,7 @@
 	}
 
 	case MEYEIOC_STILLJCAPT: {
-		int len = -1;
+		int *len = arg;
 
 		if (!meye.grab_fbuffer) 
 			return -EINVAL;
@@ -1180,14 +1151,13 @@
 			return -EBUSY;
 		down(&meye.lock);
 		meye.grab_buffer[0].state = MEYE_BUF_USING;
-		while (len == -1) {
+		*len = -1;
+		while (*len == -1) {
 			mchip_take_picture();
-			len = mchip_compress_frame(meye.grab_fbuffer, gbufsize);
+			*len = mchip_compress_frame(meye.grab_fbuffer, gbufsize);
 		}
 		meye.grab_buffer[0].state = MEYE_BUF_DONE;
 		up(&meye.lock);
-		if (copy_to_user(arg, (void *)&len, sizeof(int)))
-			return -EFAULT;
 		break;
 	}
 
@@ -1199,10 +1169,10 @@
 	return 0;
 }
 
-static int meye_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, 
-		     unsigned long size) {
-	unsigned long start=(unsigned long) adr;
-	unsigned long page,pos;
+static int meye_mmap(struct file *file, struct vm_area_struct *vma) {
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end - vma->vm_start;
+	unsigned long page, pos;
 
 	down(&meye.lock);
 	if (size > gbuffers * gbufsize) {
@@ -1234,15 +1204,22 @@
 	return 0;
 }
 
+static struct file_operations meye_fops = {
+	owner:		THIS_MODULE,
+	open:		meye_open,
+	release:	meye_release,
+	mmap:		meye_mmap,
+	ioctl:		video_generic_ioctl,
+	llseek:		no_llseek,
+};
+
 static struct video_device meye_template = {
 	owner:		THIS_MODULE,
 	name:		"meye",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_MEYE,
-	open:		meye_open,
-	close:		meye_close,
-	ioctl:		meye_ioctl,
-	mmap:		meye_mmap,
+	fops:		&meye_fops,
+	kernel_ioctl:	meye_ioctl,
 };
 
 static int __devinit meye_probe(struct pci_dev *pcidev, 
diff -Nru a/drivers/media/video/meye.h b/drivers/media/video/meye.h
--- a/drivers/media/video/meye.h	Fri Mar 15 17:51:00 2002
+++ b/drivers/media/video/meye.h	Fri Mar 15 17:51:00 2002
@@ -29,7 +29,7 @@
 #define _MEYE_PRIV_H_
 
 #define MEYE_DRIVER_MAJORVERSION	1
-#define MEYE_DRIVER_MINORVERSION	2
+#define MEYE_DRIVER_MINORVERSION	3
 
 /****************************************************************************/
 /* Motion JPEG chip registers                                               */
@@ -300,7 +300,6 @@
 	struct meye_grab_buffer grab_buffer[MEYE_MAX_BUFNBRS];
 
 	/* other */
-	unsigned int open_count;	/* open() count */
 	struct semaphore lock;		/* semaphore for open/mmap... */
 
 	struct meye_queue grabq;	/* queue for buffers to be grabbed */
diff -Nru a/drivers/media/video/msp3400.c b/drivers/media/video/msp3400.c
--- a/drivers/media/video/msp3400.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/video/msp3400.c	Fri Mar 15 17:51:01 2002
@@ -97,6 +97,7 @@
 	int nicam_on;
 	int acb;
 	int main, second;	/* sound carrier */
+	int input;
 
 	int muted;
 	int left, right;	/* volume */
@@ -462,6 +463,8 @@
 /* turn on/off nicam + stereo */
 static void msp3400c_setstereo(struct i2c_client *client, int mode)
 {
+	static char *strmode[] = { "0", "mono", "stereo", "3",
+				   "lang1", "5", "6", "7", "lang2" };
 	struct msp3400c *msp = client->data;
 	int nicam=0; /* channel source: FM/AM or nicam */
 	int src=0;
@@ -469,7 +472,7 @@
 	/* switch demodulator */
 	switch (msp->mode) {
 	case MSP_MODE_FM_TERRA:
-		dprintk("msp3400: FM setstereo: %d\n",mode);
+		dprintk("msp3400: FM setstereo: %s\n",strmode[mode]);
 		msp3400c_setcarrier(client,msp->second,msp->main);
 		switch (mode) {
 		case VIDEO_SOUND_STEREO:
@@ -483,7 +486,7 @@
 		}
 		break;
 	case MSP_MODE_FM_SAT:
-		dprintk("msp3400: SAT setstereo: %d\n",mode);
+		dprintk("msp3400: SAT setstereo: %s\n",strmode[mode]);
 		switch (mode) {
 		case VIDEO_SOUND_MONO:
 			msp3400c_setcarrier(client, MSP_CARRIER(6.5), MSP_CARRIER(6.5));
@@ -502,21 +505,21 @@
 	case MSP_MODE_FM_NICAM1:
 	case MSP_MODE_FM_NICAM2:
 	case MSP_MODE_AM_NICAM:
-		dprintk("msp3400: NICAM setstereo: %d\n",mode);
+		dprintk("msp3400: NICAM setstereo: %s\n",strmode[mode]);
 		msp3400c_setcarrier(client,msp->second,msp->main);
 		if (msp->nicam_on)
 			nicam=0x0100;
 		break;
 	case MSP_MODE_BTSC:
-		dprintk("msp3400: BTSC setstereo: %d\n",mode);
+		dprintk("msp3400: BTSC setstereo: %s\n",strmode[mode]);
 		nicam=0x0300;
 		break;
 	case MSP_MODE_EXTERN:
-		dprintk("msp3400: extern setstereo: %d\n", mode);
+		dprintk("msp3400: extern setstereo: %s\n",strmode[mode]);
 		nicam = 0x0200;
 		break;
 	case MSP_MODE_FM_RADIO:
-		dprintk("msp3400: FM-Radio setstereo: %d\n", mode);
+		dprintk("msp3400: FM-Radio setstereo: %s\n",strmode[mode]);
 		break;
 	default:
 		dprintk("msp3400: mono setstereo\n");
@@ -627,7 +630,7 @@
 	switch (msp->mode) {
 	case MSP_MODE_FM_TERRA:
 		val = msp3400c_read(client, I2C_MSP3400C_DFP, 0x18);
-		if (val > 32768)
+		if (val > 32767)
 			val -= 65536;
 		dprintk("msp34xx: stereo detect register: %d\n",val);
 		
@@ -822,7 +825,7 @@
 				msp->restart = 0;
 
 			val = msp3400c_read(client, I2C_MSP3400C_DFP, 0x1b);
-			if (val > 32768)
+			if (val > 32767)
 				val -= 65536;
 			if (val1 < val)
 				val1 = val, max1 = this;
@@ -859,7 +862,7 @@
 				goto restart;
 
 			val = msp3400c_read(client, I2C_MSP3400C_DFP, 0x1b);
-			if (val > 32768)
+			if (val > 32767)
 				val -= 65536;
 			if (val2 < val)
 				val2 = val, max2 = this;
@@ -1221,6 +1224,7 @@
 static struct i2c_client client_template = 
 {
 	name:   "(unset)",
+	flags:  I2C_CLIENT_ALLOW_USE,
         driver: &driver,
 };
 
@@ -1253,6 +1257,7 @@
 	msp->right  = 65535;
 	msp->bass   = 32768;
 	msp->treble = 32768;
+	msp->input  = -1;
 	for (i = 0; i < DFP_COUNT; i++)
 		msp->dfp_regs[i] = -1;
 
@@ -1391,6 +1396,9 @@
 		     - IN1 is often used for external input
 		     - Hauppauge uses IN2 for the radio */
 		dprintk(KERN_DEBUG "msp34xx: AUDC_SET_INPUT(%d)\n",*sarg);
+		if (*sarg == msp->input)
+			break;
+		msp->input = *sarg;
 		switch (*sarg) {
 		case AUDIO_RADIO:
 			msp->mode   = MSP_MODE_FM_RADIO;
@@ -1420,6 +1428,7 @@
 		break;
 
 	case AUDC_SET_RADIO:
+		dprintk(KERN_DEBUG "msp34xx: AUDC_SET_RADIO\n");
 		msp->norm = VIDEO_MODE_RADIO;
 		msp->watch_stereo=0;
 		del_timer(&msp->wake_stereo);
@@ -1471,6 +1480,7 @@
 	{
 		struct video_audio *va = arg;
 
+		dprintk(KERN_DEBUG "msp34xx: VIDIOCGAUDIO\n");
 		va->flags |= VIDEO_AUDIO_VOLUME |
 			VIDEO_AUDIO_BASS |
 			VIDEO_AUDIO_TREBLE |
@@ -1497,6 +1507,7 @@
 	{
 		struct video_audio *va = arg;
 
+		dprintk(KERN_DEBUG "msp34xx: VIDIOCSAUDIO\n");
 		msp->muted = (va->flags & VIDEO_AUDIO_MUTE);
 		msp->left = (MIN(65536 - va->balance,32768) *
 			     va->volume) / 32768;
@@ -1520,6 +1531,7 @@
 	{
 		struct video_channel *vc = arg;
 		
+		dprintk(KERN_DEBUG "msp34xx: VIDIOCSCHAN\n");
 		dprintk("msp34xx: switching to TV mode\n");
 		msp->norm = vc->norm;
 		break;
@@ -1527,6 +1539,7 @@
 	case VIDIOCSFREQ:
 	{
 		/* new channel -- kick audio carrier scan */
+		dprintk(KERN_DEBUG "msp34xx: VIDIOCSFREQ\n");
 		msp_wake_thread(client);
 		break;
 	}
@@ -1540,13 +1553,13 @@
 
 /* ----------------------------------------------------------------------- */
 
-int msp3400_init_module(void)
+static int msp3400_init_module(void)
 {
 	i2c_add_driver(&driver);
 	return 0;
 }
 
-void msp3400_cleanup_module(void)
+static void msp3400_cleanup_module(void)
 {
 	i2c_del_driver(&driver);
 }
diff -Nru a/drivers/media/video/pms.c b/drivers/media/video/pms.c
--- a/drivers/media/video/pms.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/pms.c	Fri Mar 15 17:51:02 2002
@@ -672,119 +672,93 @@
  *	Video4linux interfacing
  */
 
-static int pms_open(struct video_device *dev, int flags)
-{
-	return 0;
-}
-
-static void pms_close(struct video_device *dev)
-{
-}
-
-static long pms_write(struct video_device *v, const char *buf, unsigned long count, int noblock)
-{
-	return -EINVAL;
-}
-
-static int pms_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+static int pms_ioctl(struct inode *inode, struct file *file,
+		     unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	struct pms_device *pd=(struct pms_device *)dev;
 	
 	switch(cmd)
 	{
 		case VIDIOCGCAP:
 		{
-			struct video_capability b;
-			strcpy(b.name, "Mediavision PMS");
-			b.type = VID_TYPE_CAPTURE|VID_TYPE_SCALES;
-			b.channels = 4;
-			b.audios = 0;
-			b.maxwidth = 640;
-			b.maxheight = 480;
-			b.minwidth = 16;
-			b.minheight = 16;
-			if(copy_to_user(arg, &b,sizeof(b)))
-				return -EFAULT;
+			struct video_capability *b = arg;
+			strcpy(b->name, "Mediavision PMS");
+			b->type = VID_TYPE_CAPTURE|VID_TYPE_SCALES;
+			b->channels = 4;
+			b->audios = 0;
+			b->maxwidth = 640;
+			b->maxheight = 480;
+			b->minwidth = 16;
+			b->minheight = 16;
 			return 0;
 		}
 		case VIDIOCGCHAN:
 		{
-			struct video_channel v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.channel<0 || v.channel>3)
+			struct video_channel *v = arg;
+			if(v->channel<0 || v->channel>3)
 				return -EINVAL;
-			v.flags=0;
-			v.tuners=1;
+			v->flags=0;
+			v->tuners=1;
 			/* Good question.. its composite or SVHS so.. */
-			v.type = VIDEO_TYPE_CAMERA;
-			switch(v.channel)
+			v->type = VIDEO_TYPE_CAMERA;
+			switch(v->channel)
 			{
 				case 0:
-					strcpy(v.name, "Composite");break;
+					strcpy(v->name, "Composite");break;
 				case 1:
-					strcpy(v.name, "SVideo");break;
+					strcpy(v->name, "SVideo");break;
 				case 2:
-					strcpy(v.name, "Composite(VCR)");break;
+					strcpy(v->name, "Composite(VCR)");break;
 				case 3:
-					strcpy(v.name, "SVideo(VCR)");break;
+					strcpy(v->name, "SVideo(VCR)");break;
 			}
-			if(copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
 			return 0;
 		}
 		case VIDIOCSCHAN:
 		{
-			int v;
-			if(copy_from_user(&v, arg,sizeof(v)))
-				return -EFAULT;
-			if(v<0 || v>3)
-				return -EINVAL;
-			down(&pd->lock);		
-			pms_videosource(v&1);
-			pms_vcrinput(v>>1);
+			struct video_channel *v = arg;
+			if(v->channel<0 || v->channel>3)
+				return -EINVAL;
+			down(&pd->lock);
+			pms_videosource(v->channel&1);
+			pms_vcrinput(v->channel>>1);
 			up(&pd->lock);
 			return 0;
 		}
 		case VIDIOCGTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
-				return -EINVAL;
-			strcpy(v.name, "Format");
-			v.rangelow=0;
-			v.rangehigh=0;
-			v.flags= VIDEO_TUNER_PAL|VIDEO_TUNER_NTSC|VIDEO_TUNER_SECAM;
+			struct video_tuner *v = arg;
+			if(v->tuner)
+				return -EINVAL;
+			strcpy(v->name, "Format");
+			v->rangelow=0;
+			v->rangehigh=0;
+			v->flags= VIDEO_TUNER_PAL|VIDEO_TUNER_NTSC|VIDEO_TUNER_SECAM;
 			switch(standard)
 			{
 				case 0:
-					v.mode = VIDEO_MODE_AUTO;
+					v->mode = VIDEO_MODE_AUTO;
 					break;
 				case 1:
-					v.mode = VIDEO_MODE_NTSC;
+					v->mode = VIDEO_MODE_NTSC;
 					break;
 				case 2:
-					v.mode = VIDEO_MODE_PAL;
+					v->mode = VIDEO_MODE_PAL;
 					break;
 				case 3:
-					v.mode = VIDEO_MODE_SECAM;
+					v->mode = VIDEO_MODE_SECAM;
 					break;
 			}
-			if(copy_to_user(arg,&v,sizeof(v))!=0)
-				return -EFAULT;
 			return 0;
 		}
 		case VIDIOCSTUNER:
 		{
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v))!=0)
-				return -EFAULT;
-			if(v.tuner)
+			struct video_tuner *v = arg;
+			if(v->tuner)
 				return -EINVAL;
 			down(&pd->lock);
-			switch(v.mode)
+			switch(v->mode)
 			{
 				case VIDEO_MODE_AUTO:
 					pms_framerate(25);
@@ -815,48 +789,43 @@
 		}
 		case VIDIOCGPICT:
 		{
-			struct video_picture p=pd->picture;
-			if(copy_to_user(arg, &p, sizeof(p)))
-				return -EFAULT;
+			struct video_picture *p = arg;
+			*p = pd->picture;
 			return 0;
 		}
 		case VIDIOCSPICT:
 		{
-			struct video_picture p;
-			if(copy_from_user(&p, arg, sizeof(p)))
-				return -EFAULT;
-			if(!((p.palette==VIDEO_PALETTE_RGB565 && p.depth==16)
-			    ||(p.palette==VIDEO_PALETTE_RGB555 && p.depth==15)))
+			struct video_picture *p = arg;
+			if(!((p->palette==VIDEO_PALETTE_RGB565 && p->depth==16)
+			    ||(p->palette==VIDEO_PALETTE_RGB555 && p->depth==15)))
 			    	return -EINVAL;
-			pd->picture=p;
+			pd->picture= *p;
 			
 			/*
 			 *	Now load the card.
 			 */
 
 			down(&pd->lock);
-			pms_brightness(p.brightness>>8);
-			pms_hue(p.hue>>8);
-			pms_colour(p.colour>>8);
-			pms_contrast(p.contrast>>8);	
+			pms_brightness(p->brightness>>8);
+			pms_hue(p->hue>>8);
+			pms_colour(p->colour>>8);
+			pms_contrast(p->contrast>>8);	
 			up(&pd->lock);
 			return 0;
 		}
 		case VIDIOCSWIN:
 		{
-			struct video_window vw;
-			if(copy_from_user(&vw, arg,sizeof(vw)))
-				return -EFAULT;
-			if(vw.flags)
+			struct video_window *vw = arg;
+			if(vw->flags)
 				return -EINVAL;
-			if(vw.clipcount)
+			if(vw->clipcount)
 				return -EINVAL;
-			if(vw.height<16||vw.height>480)
+			if(vw->height<16||vw->height>480)
 				return -EINVAL;
-			if(vw.width<16||vw.width>640)
+			if(vw->width<16||vw->width>640)
 				return -EINVAL;
-			pd->width=vw.width;
-			pd->height=vw.height;
+			pd->width=vw->width;
+			pd->height=vw->height;
 			down(&pd->lock);
 			pms_resolution(pd->width, pd->height);
 			up(&pd->lock);			/* Ok we figured out what to use from our wide choice */
@@ -864,31 +833,20 @@
 		}
 		case VIDIOCGWIN:
 		{
-			struct video_window vw;
-			vw.x=0;
-			vw.y=0;
-			vw.width=pd->width;
-			vw.height=pd->height;
-			vw.chromakey=0;
-			vw.flags=0;
-			if(copy_to_user(arg, &vw, sizeof(vw)))
-				return -EFAULT;
+			struct video_window *vw = arg;
+			memset(vw,0,sizeof(*vw));
+			vw->width=pd->width;
+			vw->height=pd->height;
 			return 0;
 		}
+		case VIDIOCKEY:
+			return 0;
 		case VIDIOCCAPTURE:
-			return -EINVAL;
 		case VIDIOCGFBUF:
-			return -EINVAL;
 		case VIDIOCSFBUF:
-			return -EINVAL;
-		case VIDIOCKEY:
-			return 0;
 		case VIDIOCGFREQ:
-			return -EINVAL;
 		case VIDIOCSFREQ:
-			return -EINVAL;
 		case VIDIOCGAUDIO:
-			return -EINVAL;
 		case VIDIOCSAUDIO:
 			return -EINVAL;
 		default:
@@ -897,8 +855,10 @@
 	return 0;
 }
 
-static long pms_read(struct video_device *v, char *buf, unsigned long count,  int noblock)
+static int pms_read(struct file *file, char *buf,
+		    size_t count, loff_t *ppos)
 {
+	struct video_device *v = video_devdata(file);
 	struct pms_device *pd=(struct pms_device *)v;
 	int len;
 	
@@ -908,18 +868,23 @@
 	return len;
 }
 
- 
-struct video_device pms_template=
+static struct file_operations pms_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:          video_generic_ioctl,
+	read:           pms_read,
+	llseek:         no_llseek,
+};
+
+static struct video_device pms_template=
 {
 	owner:		THIS_MODULE,
 	name:		"Mediavision PMS",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_PMS,
-	open:		pms_open,
-	close:		pms_close,
-	read:		pms_read,
-	write:		pms_write,
-	ioctl:		pms_ioctl,
+	fops:           &pms_fops,
+	kernel_ioctl:	pms_ioctl,
 };
 
 struct pms_device pms_device;
diff -Nru a/drivers/media/video/saa5249.c b/drivers/media/video/saa5249.c
--- a/drivers/media/video/saa5249.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/saa5249.c	Fri Mar 15 17:51:02 2002
@@ -349,88 +349,78 @@
 	{
 		case VTXIOCGETINFO: 
 		{
-			vtx_info_t info;
-			info.version_major = VTX_VER_MAJ;
-			info.version_minor = VTX_VER_MIN;
-			info.numpages = NUM_DAUS;
-			/*info.cct_type = CCT_TYPE;*/
-			if(copy_to_user((void*)arg, &info, sizeof(vtx_info_t)))
-				return -EFAULT;
+			vtx_info_t *info = arg;
+			info->version_major = VTX_VER_MAJ;
+			info->version_minor = VTX_VER_MIN;
+			info->numpages = NUM_DAUS;
+			/*info->cct_type = CCT_TYPE;*/
 			return 0;
 		}
 
 		case VTXIOCCLRPAGE: 
 		{
-			vtx_pagereq_t req;
+			vtx_pagereq_t *req = arg;
       
-			if(copy_from_user(&req, (void*)arg, sizeof(vtx_pagereq_t)))
-				return -EFAULT;
-			if (req.pgbuf < 0 || req.pgbuf >= NUM_DAUS)
+			if (req->pgbuf < 0 || req->pgbuf >= NUM_DAUS)
 				return -EINVAL;
-			memset(t->vdau[req.pgbuf].pgbuf, ' ', sizeof(t->vdau[0].pgbuf));
-			t->vdau[req.pgbuf].clrfound = TRUE;
+			memset(t->vdau[req->pgbuf].pgbuf, ' ', sizeof(t->vdau[0].pgbuf));
+			t->vdau[req->pgbuf].clrfound = TRUE;
 			return 0;
 		}
 
 		case VTXIOCCLRFOUND: 
 		{
-			vtx_pagereq_t req;
+			vtx_pagereq_t *req = arg;
       
-			if(copy_from_user(&req, (void*)arg, sizeof(vtx_pagereq_t)))
-				return -EFAULT;
-			if (req.pgbuf < 0 || req.pgbuf >= NUM_DAUS)
+			if (req->pgbuf < 0 || req->pgbuf >= NUM_DAUS)
 				return -EINVAL;
-			t->vdau[req.pgbuf].clrfound = TRUE;
+			t->vdau[req->pgbuf].clrfound = TRUE;
 			return 0;
 		}
 
 		case VTXIOCPAGEREQ: 
 		{
-			vtx_pagereq_t req;
-			if(copy_from_user(&req, (void*)arg, sizeof(vtx_pagereq_t)))
-				return -EFAULT;
-			if (!(req.pagemask & PGMASK_PAGE))
-				req.page = 0;
-			if (!(req.pagemask & PGMASK_HOUR))
-				req.hour = 0;
-			if (!(req.pagemask & PGMASK_MINUTE))
-				req.minute = 0;
-			if (req.page < 0 || req.page > 0x8ff) /* 7FF ?? */
+			vtx_pagereq_t *req = arg;
+			if (!(req->pagemask & PGMASK_PAGE))
+				req->page = 0;
+			if (!(req->pagemask & PGMASK_HOUR))
+				req->hour = 0;
+			if (!(req->pagemask & PGMASK_MINUTE))
+				req->minute = 0;
+			if (req->page < 0 || req->page > 0x8ff) /* 7FF ?? */
 				return -EINVAL;
-			req.page &= 0x7ff;
-			if (req.hour < 0 || req.hour > 0x3f || req.minute < 0 || req.minute > 0x7f ||
-				req.pagemask < 0 || req.pagemask >= PGMASK_MAX || req.pgbuf < 0 || req.pgbuf >= NUM_DAUS)
+			req->page &= 0x7ff;
+			if (req->hour < 0 || req->hour > 0x3f || req->minute < 0 || req->minute > 0x7f ||
+				req->pagemask < 0 || req->pagemask >= PGMASK_MAX || req->pgbuf < 0 || req->pgbuf >= NUM_DAUS)
 				return -EINVAL;
-			t->vdau[req.pgbuf].sregs[0] = (req.pagemask & PG_HUND ? 0x10 : 0) | (req.page / 0x100);
-			t->vdau[req.pgbuf].sregs[1] = (req.pagemask & PG_TEN ? 0x10 : 0) | ((req.page / 0x10) & 0xf);
-			t->vdau[req.pgbuf].sregs[2] = (req.pagemask & PG_UNIT ? 0x10 : 0) | (req.page & 0xf);
-			t->vdau[req.pgbuf].sregs[3] = (req.pagemask & HR_TEN ? 0x10 : 0) | (req.hour / 0x10);
-			t->vdau[req.pgbuf].sregs[4] = (req.pagemask & HR_UNIT ? 0x10 : 0) | (req.hour & 0xf);
-			t->vdau[req.pgbuf].sregs[5] = (req.pagemask & MIN_TEN ? 0x10 : 0) | (req.minute / 0x10);
-			t->vdau[req.pgbuf].sregs[6] = (req.pagemask & MIN_UNIT ? 0x10 : 0) | (req.minute & 0xf);
-			t->vdau[req.pgbuf].stopped = FALSE;
-			t->vdau[req.pgbuf].clrfound = TRUE;
-			t->is_searching[req.pgbuf] = TRUE;
+			t->vdau[req->pgbuf].sregs[0] = (req->pagemask & PG_HUND ? 0x10 : 0) | (req->page / 0x100);
+			t->vdau[req->pgbuf].sregs[1] = (req->pagemask & PG_TEN ? 0x10 : 0) | ((req->page / 0x10) & 0xf);
+			t->vdau[req->pgbuf].sregs[2] = (req->pagemask & PG_UNIT ? 0x10 : 0) | (req->page & 0xf);
+			t->vdau[req->pgbuf].sregs[3] = (req->pagemask & HR_TEN ? 0x10 : 0) | (req->hour / 0x10);
+			t->vdau[req->pgbuf].sregs[4] = (req->pagemask & HR_UNIT ? 0x10 : 0) | (req->hour & 0xf);
+			t->vdau[req->pgbuf].sregs[5] = (req->pagemask & MIN_TEN ? 0x10 : 0) | (req->minute / 0x10);
+			t->vdau[req->pgbuf].sregs[6] = (req->pagemask & MIN_UNIT ? 0x10 : 0) | (req->minute & 0xf);
+			t->vdau[req->pgbuf].stopped = FALSE;
+			t->vdau[req->pgbuf].clrfound = TRUE;
+			t->is_searching[req->pgbuf] = TRUE;
 			return 0;
 		}
 
 		case VTXIOCGETSTAT: 
 		{
-			vtx_pagereq_t req;
+			vtx_pagereq_t *req = arg;
 			u8 infobits[10];
 			vtx_pageinfo_t info;
 			int a;
 
-			if(copy_from_user(&req, (void*)arg, sizeof(vtx_pagereq_t)))
-				return -EFAULT;
-			if (req.pgbuf < 0 || req.pgbuf >= NUM_DAUS)
+			if (req->pgbuf < 0 || req->pgbuf >= NUM_DAUS)
 				return -EINVAL;
-			if (!t->vdau[req.pgbuf].stopped) 
+			if (!t->vdau[req->pgbuf].stopped) 
 			{
 				if (i2c_senddata(t, 2, 0, -1) ||
-					i2c_sendbuf(t, 3, sizeof(t->vdau[0].sregs), t->vdau[req.pgbuf].sregs) ||
+					i2c_sendbuf(t, 3, sizeof(t->vdau[0].sregs), t->vdau[req->pgbuf].sregs) ||
 					i2c_senddata(t, 8, 0, 25, 0, ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', -1) ||
-					i2c_senddata(t, 2, 0, t->vdau[req.pgbuf].sregs[0] | 8, -1) ||
+					i2c_senddata(t, 2, 0, t->vdau[req->pgbuf].sregs[0] | 8, -1) ||
 					i2c_senddata(t, 8, 0, 25, 0, -1))
 					return -EIO;
 				jdelay(PAGE_WAIT);
@@ -438,43 +428,43 @@
 					return -EIO;
 
 				if (!(infobits[8] & 0x10) && !(infobits[7] & 0xf0) &&	/* check FOUND-bit */
-					(memcmp(infobits, t->vdau[req.pgbuf].laststat, sizeof(infobits)) || 
-					time_after_eq(jiffies, t->vdau[req.pgbuf].expire)))
+					(memcmp(infobits, t->vdau[req->pgbuf].laststat, sizeof(infobits)) || 
+					time_after_eq(jiffies, t->vdau[req->pgbuf].expire)))
 				{		/* check if new page arrived */
 					if (i2c_senddata(t, 8, 0, 0, 0, -1) ||
-						i2c_getdata(t, VTX_PAGESIZE, t->vdau[req.pgbuf].pgbuf))
+						i2c_getdata(t, VTX_PAGESIZE, t->vdau[req->pgbuf].pgbuf))
 						return -EIO;
-					t->vdau[req.pgbuf].expire = jiffies + PGBUF_EXPIRE;
-					memset(t->vdau[req.pgbuf].pgbuf + VTX_PAGESIZE, ' ', VTX_VIRTUALSIZE - VTX_PAGESIZE);
+					t->vdau[req->pgbuf].expire = jiffies + PGBUF_EXPIRE;
+					memset(t->vdau[req->pgbuf].pgbuf + VTX_PAGESIZE, ' ', VTX_VIRTUALSIZE - VTX_PAGESIZE);
 					if (t->virtual_mode) 
 					{
 						/* Packet X/24 */
 						if (i2c_senddata(t, 8, 0, 0x20, 0, -1) ||
-							i2c_getdata(t, 40, t->vdau[req.pgbuf].pgbuf + VTX_PAGESIZE + 20 * 40))
+							i2c_getdata(t, 40, t->vdau[req->pgbuf].pgbuf + VTX_PAGESIZE + 20 * 40))
 							return -EIO;
 						/* Packet X/27/0 */
 						if (i2c_senddata(t, 8, 0, 0x21, 0, -1) ||
-							i2c_getdata(t, 40, t->vdau[req.pgbuf].pgbuf + VTX_PAGESIZE + 16 * 40))
+							i2c_getdata(t, 40, t->vdau[req->pgbuf].pgbuf + VTX_PAGESIZE + 16 * 40))
 							return -EIO;
 						/* Packet 8/30/0...8/30/15
 						 * FIXME: AFAIK, the 5249 does hamming-decoding for some bytes in packet 8/30,
 						 *        so we should undo this here.
 						 */
 						if (i2c_senddata(t, 8, 0, 0x22, 0, -1) ||
-							i2c_getdata(t, 40, t->vdau[req.pgbuf].pgbuf + VTX_PAGESIZE + 23 * 40))
+							i2c_getdata(t, 40, t->vdau[req->pgbuf].pgbuf + VTX_PAGESIZE + 23 * 40))
 							return -EIO;
 					}
-					t->vdau[req.pgbuf].clrfound = FALSE;
-					memcpy(t->vdau[req.pgbuf].laststat, infobits, sizeof(infobits));
+					t->vdau[req->pgbuf].clrfound = FALSE;
+					memcpy(t->vdau[req->pgbuf].laststat, infobits, sizeof(infobits));
 				}
 				else
 				{
-					memcpy(infobits, t->vdau[req.pgbuf].laststat, sizeof(infobits));
+					memcpy(infobits, t->vdau[req->pgbuf].laststat, sizeof(infobits));
 				}
 			}
 			else
 			{
-				memcpy(infobits, t->vdau[req.pgbuf].laststat, sizeof(infobits));
+				memcpy(infobits, t->vdau[req->pgbuf].laststat, sizeof(infobits));
 			}
 
 			info.pagenum = ((infobits[8] << 8) & 0x700) | ((infobits[1] << 4) & 0xf0) | (infobits[0] & 0x0f);
@@ -502,59 +492,57 @@
 					break;
 				}
 			}
-			if (t->vdau[req.pgbuf].clrfound)
+			if (t->vdau[req->pgbuf].clrfound)
 				info.notfound = 1;
-			if(copy_to_user(req.buffer, &info, sizeof(vtx_pageinfo_t)))
+			if(copy_to_user(req->buffer, &info, sizeof(vtx_pageinfo_t)))
 				return -EFAULT;
 			if (!info.hamming && !info.notfound) 
 			{
-				t->is_searching[req.pgbuf] = FALSE;
+				t->is_searching[req->pgbuf] = FALSE;
 			}
 			return 0;
 		}
 
 		case VTXIOCGETPAGE: 
 		{
-			vtx_pagereq_t req;
+			vtx_pagereq_t *req = arg;
 			int start, end;
 
-			if(copy_from_user(&req, (void*)arg, sizeof(vtx_pagereq_t)))
-				return -EFAULT;
-			if (req.pgbuf < 0 || req.pgbuf >= NUM_DAUS || req.start < 0 ||
-				req.start > req.end || req.end >= (virtual_mode ? VTX_VIRTUALSIZE : VTX_PAGESIZE))
+			if (req->pgbuf < 0 || req->pgbuf >= NUM_DAUS || req->start < 0 ||
+				req->start > req->end || req->end >= (virtual_mode ? VTX_VIRTUALSIZE : VTX_PAGESIZE))
 				return -EINVAL;
-			if(copy_to_user(req.buffer, &t->vdau[req.pgbuf].pgbuf[req.start], req.end - req.start + 1))
+			if(copy_to_user(req->buffer, &t->vdau[req->pgbuf].pgbuf[req->start], req->end - req->start + 1))
 				return -EFAULT;
 				
 			 /* 
 			  *	Always read the time directly from SAA5249
 			  */
 			  
-			if (req.start <= 39 && req.end >= 32) 
+			if (req->start <= 39 && req->end >= 32) 
 			{
 				int len;
 				char buf[16];  
-				start = MAX(req.start, 32);
-				end = MIN(req.end, 39);
+				start = MAX(req->start, 32);
+				end = MIN(req->end, 39);
 				len=end-start+1;
 				if (i2c_senddata(t, 8, 0, 0, start, -1) ||
 					i2c_getdata(t, len, buf))
 					return -EIO;
-				if(copy_to_user(req.buffer+start-req.start, buf, len))
+				if(copy_to_user(req->buffer+start-req->start, buf, len))
 					return -EFAULT;
 			}
 			/* Insert the current header if DAU is still searching for a page */
-			if (req.start <= 31 && req.end >= 7 && t->is_searching[req.pgbuf]) 
+			if (req->start <= 31 && req->end >= 7 && t->is_searching[req->pgbuf]) 
 			{
 				char buf[32];
 				int len;
-				start = MAX(req.start, 7);
-				end = MIN(req.end, 31);
+				start = MAX(req->start, 7);
+				end = MIN(req->end, 31);
 				len=end-start+1;
 				if (i2c_senddata(t, 8, 0, 0, start, -1) ||
 					i2c_getdata(t, len, buf))
 					return -EIO;
-				if(copy_to_user(req.buffer+start-req.start, buf, len))
+				if(copy_to_user(req->buffer+start-req->start, buf, len))
 					return -EFAULT;
 			}
 			return 0;
@@ -562,14 +550,12 @@
 
 		case VTXIOCSTOPDAU: 
 		{
-			vtx_pagereq_t req;
+			vtx_pagereq_t *req = arg;
 
-			if(copy_from_user(&req, (void*)arg, sizeof(vtx_pagereq_t)))
-				return -EFAULT;
-			if (req.pgbuf < 0 || req.pgbuf >= NUM_DAUS)
+			if (req->pgbuf < 0 || req->pgbuf >= NUM_DAUS)
 				return -EINVAL;
-			t->vdau[req.pgbuf].stopped = TRUE;
-			t->is_searching[req.pgbuf] = FALSE;
+			t->vdau[req->pgbuf].stopped = TRUE;
+			t->is_searching[req->pgbuf] = FALSE;
 			return 0;
 		}
 
@@ -604,8 +590,10 @@
  *	Handle the locking
  */
  
-static int saa5249_ioctl(struct video_device *vd, unsigned int cmd, void *arg) 
+static int saa5249_ioctl(struct inode *inode, struct file *file,
+			 unsigned int cmd, void *arg) 
 {
+	struct video_device *vd = video_devdata(file);
 	struct saa5249_device *t=vd->priv;
 	int err;
 	
@@ -616,13 +604,20 @@
 	return err;
 }
 
-static int saa5249_open(struct video_device *vd, int nb) 
+static int saa5249_open(struct inode *inode, struct file *file) 
 {
+	struct video_device *vd = video_devdata(file);
 	struct saa5249_device *t=vd->priv;
-	int pgbuf;
+	int err,pgbuf;
 
-	if (t->client==NULL) 
-		return -ENODEV;
+	err = video_exclusive_open(inode,file);
+	if (err < 0)
+		return err;
+	
+	if (t->client==NULL) {
+		err = -ENODEV;
+		goto fail;
+	}
 
 	if (i2c_senddata(t, 0, 0, -1) ||		/* Select R11 */
 						/* Turn off parity checks (we do this ourselves) */
@@ -631,7 +626,8 @@
 		i2c_senddata(t, 4, NUM_DAUS, disp_modes[t->disp_mode][1], disp_modes[t->disp_mode][2], 7, -1)) /* Set display to page 4 */
 	
 	{
-		return -EIO;
+		err = -EIO;
+		goto fail;
 	}
 
 	for (pgbuf = 0; pgbuf < NUM_DAUS; pgbuf++) 
@@ -646,21 +642,22 @@
 	}
 	t->virtual_mode=FALSE;
 	return 0;
+
+ fail:
+	video_exclusive_release(inode,file);
+	return err;
 }
 
 
 
-static void saa5249_release(struct video_device *vd) 
+static int saa5249_release(struct inode *inode, struct file *file) 
 {
+	struct video_device *vd = video_devdata(file);
 	struct saa5249_device *t=vd->priv;
 	i2c_senddata(t, 1, 0x20, -1);		/* Turn off CCT */
 	i2c_senddata(t, 5, 3, 3, -1);		/* Turn off TV-display */
-	return;
-}
-
-static long saa5249_write(struct video_device *v, const char *buf, unsigned long l, int nb)
-{
-	return -EINVAL;
+	video_exclusive_release(inode,file);
+	return 0;
 }
 
 static int __init init_saa_5249 (void)
@@ -678,16 +675,22 @@
 module_init(init_saa_5249);
 module_exit(cleanup_saa_5249);
 
+static struct file_operations saa_fops = {
+	owner:		THIS_MODULE,
+	open:		saa5249_open,
+	release:       	saa5249_release,
+	ioctl:          video_generic_ioctl,
+	llseek:         no_llseek,
+};
+
 static struct video_device saa_template =
 {
 	owner:		THIS_MODULE,
 	name:		IF_NAME,
 	type:		VID_TYPE_TELETEXT,	/*| VID_TYPE_TUNER ?? */
 	hardware:	VID_HARDWARE_SAA5249,
-	open:		saa5249_open,
-	close:		saa5249_release,
-	write:		saa5249_write,
-	ioctl:		saa5249_ioctl,
+	fops:           &saa_fops,
+	kernel_ioctl:  	saa5249_ioctl,
 };
 
 MODULE_LICENSE("GPL");
diff -Nru a/drivers/media/video/tda7432.c b/drivers/media/video/tda7432.c
--- a/drivers/media/video/tda7432.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/video/tda7432.c	Fri Mar 15 17:51:03 2002
@@ -518,7 +518,7 @@
         &driver
 };
 
-int tda7432_init(void)
+static int tda7432_init(void)
 {
 
 	if ( (loudness < 0) || (loudness > 15) )
@@ -531,7 +531,7 @@
 	return 0;
 }
 
-void tda7432_fini(void)
+static void tda7432_fini(void)
 {
 	i2c_del_driver(&driver);
 }
diff -Nru a/drivers/media/video/tda9875.c b/drivers/media/video/tda9875.c
--- a/drivers/media/video/tda9875.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/media/video/tda9875.c	Fri Mar 15 17:51:03 2002
@@ -147,6 +147,24 @@
 }
 #endif
 
+static int i2c_read_register(struct i2c_adapter *adap, int addr, int reg)
+{
+        unsigned char write[1];
+        unsigned char read[1];
+        struct i2c_msg msgs[2] = {
+                { addr, 0,        1, write },
+                { addr, I2C_M_RD, 1, read  }
+        };
+        write[0] = reg;
+
+        if (2 != i2c_transfer(adap,msgs,2)) {
+                printk(KERN_WARNING "tda9875: I/O error (read2)\n");
+                return -1;
+        }
+        dprintk("tda9875: chip_read2: reg%d=0x%x\n",reg,read[0]);
+        return read[0];
+}
+
 static void tda9875_set(struct i2c_client *client)
 {
 	struct tda9875 *tda = client->data;
@@ -215,6 +233,22 @@
  * i2c interface functions *
  * *********************** */
 
+static int tda9875_checkit(struct i2c_adapter *adap, int addr)
+{
+	int dic,rev;
+
+	dic=i2c_read_register(adap,addr,254);
+	rev=i2c_read_register(adap,addr,255);
+
+	if(dic==0 || dic==2) { // tda9875 and tda9875A
+		printk("tda9875: TDA9875%s Rev.%d detected at 0x%x\n",
+		dic==0?"":"A", rev,addr<<1);
+		return 1;
+	}
+	printk("tda9875: no such chip at 0x%x (dic=0x%x rev=0x%x)\n",addr<<1,dic,rev);
+	return(0);
+}
+
 static int tda9875_attach(struct i2c_adapter *adap, int addr,
 			  unsigned short flags, int kind)
 {
@@ -232,6 +266,11 @@
         client->adapter = adap;
         client->addr = addr;
 	client->data = t;
+
+	if(!tda9875_checkit(adap,addr)) {
+		kfree(t);
+		return 1;
+	}
 	
 	do_tda9875_init(client);
 	MOD_INC_USE_COUNT;
@@ -375,22 +414,19 @@
         &driver
 };
 
-#ifdef MODULE
-int init_module(void)
-#else
-int tda9875_init(void)
-#endif
+static int tda9875_init(void)
 {
 	i2c_add_driver(&driver);
 	return 0;
 }
 
-#ifdef MODULE
-void cleanup_module(void)
+static void tda9875_fini(void)
 {
 	i2c_del_driver(&driver);
 }
-#endif
+
+module_init(tda9875_init);
+module_exit(tda9875_fini);
 
 /*
  * Local variables:
diff -Nru a/drivers/media/video/tuner.c b/drivers/media/video/tuner.c
--- a/drivers/media/video/tuner.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/tuner.c	Fri Mar 15 17:51:02 2002
@@ -154,7 +154,7 @@
 	  16*137.25,16*385.25,0x01,0x02,0x08,0x8e,732},
         { "Alps TSBE1",TEMIC,PAL,
 	  16*137.25,16*385.25,0x01,0x02,0x08,0x8e,732},
-        { "Alps TSBB5", Alps, PAL_I, /* tested (UK UHF) with Modtec MM205 */
+        { "Alps TSBB5", Alps, PAL_I, /* tested (UK UHF) with Modulartech MM205 */
 	  16*133.25,16*351.25,0x01,0x02,0x08,0x8e,632},
 
         { "Alps TSBE5", Alps, PAL, /* untested - data sheet guess. Only IF differs. */
@@ -175,7 +175,7 @@
         { "Temic PAL* auto (4006 FN5)", TEMIC, PAL,
           16*169.00, 16*454.00, 0xa0,0x90,0x30,0x8e,623},
 
-        { "Temic PAL (4009 FR5)", TEMIC, PAL,
+        { "Temic PAL_BG (4009 FR5) or PAL_I (4069 FR5)", TEMIC, PAL,
           16*141.00, 16*464.00, 0xa0,0x90,0x30,0x8e,623},
         { "Temic NTSC (4039 FR5)", TEMIC, NTSC,
           16*158.00, 16*453.00, 0xa0,0x90,0x30,0x8e,732},
@@ -271,7 +271,7 @@
 }
 #endif
 // Initalization as described in "MT203x Programming Procedures", Rev 1.2, Feb.2001
-int mt2032_init(struct i2c_client *c)
+static int mt2032_init(struct i2c_client *c)
 {
         unsigned char buf[21];
         int ret,xogc,xok=0;
@@ -345,7 +345,7 @@
 
 
 // IsSpurInBand()?
-int mt2032_spurcheck(int f1, int f2, int spectrum_from,int spectrum_to)
+static int mt2032_spurcheck(int f1, int f2, int spectrum_from,int spectrum_to)
 {
 	int n1=1,n2,f;
 
@@ -373,7 +373,7 @@
 	return 1;
 }
 
-int mt2032_compute_freq(int rfin, int if1, int if2, int spectrum_from,
+static int mt2032_compute_freq(int rfin, int if1, int if2, int spectrum_from,
 	int spectrum_to, unsigned char *buf, int *ret_sel, int xogc) //all in Hz
 {
         int fref,lo1,lo1n,lo1a,s,sel,lo1freq, desired_lo1,
@@ -449,7 +449,7 @@
 	return 0;
 }
 
-int mt2032_check_lo_lock(struct i2c_client *c)
+static int mt2032_check_lo_lock(struct i2c_client *c)
 {
 	int try,lock=0;
 	unsigned char buf[2];
@@ -469,7 +469,7 @@
         return lock;
 }
 
-int mt2032_optimize_vco(struct i2c_client *c,int sel,int lock)
+static int mt2032_optimize_vco(struct i2c_client *c,int sel,int lock)
 {
 	unsigned char buf[2];
 	int tad1;
@@ -505,7 +505,7 @@
 }
 
 
-void mt2032_set_if_freq(struct i2c_client *c,int rfin, int if1, int if2, int from, int to)
+static void mt2032_set_if_freq(struct i2c_client *c,int rfin, int if1, int if2, int from, int to)
 {
 	unsigned char buf[21];
 	int lint_try,ret,sel,lock=0;
@@ -560,7 +560,7 @@
 }
 
 
-void mt2032_set_tv_freq(struct i2c_client *c, int freq, int norm)
+static void mt2032_set_tv_freq(struct i2c_client *c, int freq, int norm)
 {
 	int if2,from,to;
 
@@ -815,14 +815,27 @@
 
 static int tuner_probe(struct i2c_adapter *adap)
 {
+	int rc;
+
 	if (0 != addr) {
 		normal_i2c_range[0] = addr;
 		normal_i2c_range[1] = addr;
 	}
 	this_adap = 0;
-	if (adap->id == (I2C_ALGO_BIT | I2C_HW_B_BT848))
-		return i2c_probe(adap, &addr_data, tuner_attach);
-	return 0;
+	switch (adap->id) {
+	case I2C_ALGO_BIT | I2C_HW_B_BT848:
+	case I2C_ALGO_SAA7134:
+		printk("tuner: probing %s i2c adapter [id=0x%x]\n",
+		       adap->name,adap->id);
+		rc = i2c_probe(adap, &addr_data, tuner_attach);
+		break;
+	default:
+		printk("tuner: ignoring %s i2c adapter [id=0x%x]\n",
+		       adap->name,adap->id);
+		rc = 0;
+		/* nothing */
+	}
+	return rc;
 }
 
 static int tuner_detach(struct i2c_client *client)
@@ -948,39 +961,34 @@
 /* ----------------------------------------------------------------------- */
 
 static struct i2c_driver driver = {
-        "i2c TV tuner driver",
-        I2C_DRIVERID_TUNER,
-        I2C_DF_NOTIFY,
-        tuner_probe,
-        tuner_detach,
-        tuner_command,
+        name:           "i2c TV tuner driver",
+        id:             I2C_DRIVERID_TUNER,
+        flags:          I2C_DF_NOTIFY,
+        attach_adapter: tuner_probe,
+        detach_client:  tuner_detach,
+        command:        tuner_command,
 };
-
 static struct i2c_client client_template =
 {
-        "(unset)",		/* name       */
-        -1,
-        0,
-        0,
-        NULL,
-        &driver
+        name:   "(unset)",
+	flags:  I2C_CLIENT_ALLOW_USE,
+        driver: &driver,
 };
 
-EXPORT_NO_SYMBOLS;
-
-int tuner_init_module(void)
+static int tuner_init_module(void)
 {
 	i2c_add_driver(&driver);
 	return 0;
 }
 
-void tuner_cleanup_module(void)
+static void tuner_cleanup_module(void)
 {
 	i2c_del_driver(&driver);
 }
 
 module_init(tuner_init_module);
 module_exit(tuner_cleanup_module);
+EXPORT_NO_SYMBOLS;
 
 /*
  * Overrides for Emacs so that we follow Linus's tabbing style.
diff -Nru a/drivers/media/video/tuner.h b/drivers/media/video/tuner.h
--- a/drivers/media/video/tuner.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/video/tuner.h	Fri Mar 15 17:51:01 2002
@@ -22,6 +22,8 @@
 #ifndef _TUNER_H
 #define _TUNER_H
 
+#include "id.h"
+
 #define TUNER_TEMIC_PAL     0        /* 4002 FH5 (3X 7756, 9483) */
 #define TUNER_PHILIPS_PAL_I 1
 #define TUNER_PHILIPS_NTSC  2
diff -Nru a/drivers/media/video/tvaudio.c b/drivers/media/video/tvaudio.c
--- a/drivers/media/video/tvaudio.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/tvaudio.c	Fri Mar 15 17:51:02 2002
@@ -120,14 +120,17 @@
 	/* current settings */
 	__u16 left,right,treble,bass,mode;
 	int prevmode;
+	int norm;
 	/* thread */
 	struct task_struct  *thread;
 	struct semaphore    *notify;
 	wait_queue_head_t    wq;
 	struct timer_list    wt;
 	int                  done;
+	int                  watch_stereo;
 };
 
+#define VIDEO_MODE_RADIO 16      /* norm magic for radio mode */
 
 /* ---------------------------------------------------------------------- */
 /* i2c addresses                                                          */
@@ -139,7 +142,7 @@
 	I2C_TDA9840   >> 1,
 	I2C_TDA985x_L >> 1,
 	I2C_TDA985x_H >> 1,
-	I2C_TDA9874A  >> 1,
+	I2C_TDA9874   >> 1,
 	I2C_PIC16C54  >> 1,
 	I2C_CLIENT_END };
 static unsigned short normal_i2c_range[2] = { I2C_CLIENT_END, I2C_CLIENT_END };
@@ -296,9 +299,9 @@
 		dprintk("%s: thread wakeup\n", chip->c.name);
 		if (chip->done || signal_pending(current))
 			break;
-		
-		if (0 != chip->mode)
-			/* don't do anything if mode != auto */
+
+		/* don't do anything for radio or if mode != auto */
+		if (chip->norm == VIDEO_MODE_RADIO || chip->mode != 0)
 			continue;
 		
 		/* have a look what's going on */
@@ -316,7 +319,7 @@
 	return 0;
 }
 
-void generic_checkmode(struct CHIPSTATE *chip)
+static void generic_checkmode(struct CHIPSTATE *chip)
 {
 	struct CHIPDESC  *desc = chiplist + chip->type;
 	int mode = desc->getmode(chip);
@@ -327,12 +330,12 @@
 	dprintk("%s: thread checkmode\n", chip->c.name);
 	chip->prevmode = mode;
 
-	if (mode & VIDEO_SOUND_LANG1)
+	if (mode & VIDEO_SOUND_STEREO)
+		desc->setmode(chip,VIDEO_SOUND_STEREO);
+	else if (mode & VIDEO_SOUND_LANG1)
 		desc->setmode(chip,VIDEO_SOUND_LANG1);
 	else if (mode & VIDEO_SOUND_LANG2)
 		desc->setmode(chip,VIDEO_SOUND_LANG2);
-	else if (mode & VIDEO_SOUND_STEREO)
-		desc->setmode(chip,VIDEO_SOUND_STEREO);
 	else
 		desc->setmode(chip,VIDEO_SOUND_MONO);
 }
@@ -360,7 +363,7 @@
 #define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
 #define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
 
-int  tda9840_getmode(struct CHIPSTATE *chip)
+static int tda9840_getmode(struct CHIPSTATE *chip)
 {
 	int val, mode;
 	
@@ -376,7 +379,7 @@
 	return mode;
 }
 
-void tda9840_setmode(struct CHIPSTATE *chip, int mode)
+static void tda9840_setmode(struct CHIPSTATE *chip, int mode)
 {
 	int update = 1;
 	int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
@@ -502,11 +505,11 @@
  * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
 #define TDA985x_ADJ	1<<7 /* Stereo adjust on/off (wideband and spectral */
 
-int tda9855_volume(int val) { return val/0x2e8+0x27; }
-int tda9855_bass(int val)   { return val/0xccc+0x06; }
-int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
+static int tda9855_volume(int val) { return val/0x2e8+0x27; }
+static int tda9855_bass(int val)   { return val/0xccc+0x06; }
+static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
 
-int  tda985x_getmode(struct CHIPSTATE *chip)
+static int  tda985x_getmode(struct CHIPSTATE *chip)
 {
 	int mode;
 
@@ -517,7 +520,7 @@
 	return mode | VIDEO_SOUND_MONO;
 }
 
-void tda985x_setmode(struct CHIPSTATE *chip, int mode)
+static void tda985x_setmode(struct CHIPSTATE *chip, int mode)
 {
 	int update = 1;
 	int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
@@ -657,7 +660,7 @@
 #define TDA9873_STEREO      2 /* Stereo sound is identified     */
 #define TDA9873_DUAL        4 /* Dual sound is identified       */
 
-int tda9873_getmode(struct CHIPSTATE *chip)
+static int tda9873_getmode(struct CHIPSTATE *chip)
 {
 	int val,mode;
 
@@ -672,7 +675,7 @@
 	return mode;
 }
 
-void tda9873_setmode(struct CHIPSTATE *chip, int mode)
+static void tda9873_setmode(struct CHIPSTATE *chip, int mode)
 {
 	int sw_data  = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
 	/*	int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
@@ -708,7 +711,7 @@
 		mode, sw_data);
 }
 
-int tda9873_checkit(struct CHIPSTATE *chip)
+static int tda9873_checkit(struct CHIPSTATE *chip)
 {
 	int rc;
 
@@ -719,10 +722,10 @@
 
 
 /* ---------------------------------------------------------------------- */
-/* audio chip description - defines+functions for tda9874a                */
+/* audio chip description - defines+functions for tda9874h and tda9874a   */
 /* Dariusz Kowalewski <darekk@automex.pl>                                 */
 
-/* Subaddresses for TDA9874A (slave rx) */
+/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
 #define TDA9874A_AGCGR		0x00	/* AGC gain */
 #define TDA9874A_GCONR		0x01	/* general config */
 #define TDA9874A_MSR		0x02	/* monitor select */
@@ -747,10 +750,10 @@
 #define TDA9874A_DAICONR	0x15	/* digital audio interface config */
 #define TDA9874A_I2SOSR		0x16	/* I2S-bus output select */
 #define TDA9874A_I2SOLAR	0x17	/* I2S-bus output level adj. */
-#define TDA9874A_MDACOSR	0x18	/* mono DAC output select */
-#define TDA9874A_ESP		0xFF	/* easy standard progr. */
+#define TDA9874A_MDACOSR	0x18	/* mono DAC output select (tda9874a) */
+#define TDA9874A_ESP		0xFF	/* easy standard progr. (tda9874a) */
 
-/* Subaddresses for TDA9874A (slave tx) */
+/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
 #define TDA9874A_DSR		0x00	/* device status */
 #define TDA9874A_NSR		0x01	/* NICAM status */
 #define TDA9874A_NECR		0x02	/* NICAM error count */
@@ -767,37 +770,91 @@
 
 static int tda9874a_mode = 1;		/* 0: A2, 1: NICAM */
 static int tda9874a_GCONR = 0xc0;	/* default config. input pin: SIFSEL=0 */
+static int tda9874a_NCONR = 0x01;	/* default NICAM config.: AMSEL=0,AMUTE=1 */
 static int tda9874a_ESP = 0x07;		/* default standard: NICAM D/K */
+static int tda9874a_dic = -1;		/* device id. code */
 
 /* insmod options for tda9874a */
 static int tda9874a_SIF = -1;
+static int tda9874a_AMSEL = -1;
 static int tda9874a_STD = -1;
 MODULE_PARM(tda9874a_SIF,"i");
+MODULE_PARM(tda9874a_AMSEL,"i");
 MODULE_PARM(tda9874a_STD,"i");
 
+/*
+ * initialization table for tda9874 decoder:
+ *  - carrier 1 freq. registers (3 bytes)
+ *  - carrier 2 freq. registers (3 bytes)
+ *  - demudulator config register
+ *  - FM de-emphasis register (slow identification mode)
+ * Note: frequency registers must be written in single i2c transfer.
+ */
+static struct tda9874a_MODES {
+	char *name;
+	audiocmd cmd;
+} tda9874a_modelist[9] = {
+  {	"A2, B/G",
+	{ 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
+  {	"A2, M (Korea)",
+	{ 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
+  {	"A2, D/K (1)",
+	{ 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
+  {	"A2, D/K (2)",
+	{ 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
+  {	"A2, D/K (3)",
+	{ 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
+  {	"NICAM, I",
+	{ 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
+  {	"NICAM, B/G",
+	{ 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
+  {	"NICAM, D/K", /* default */
+	{ 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
+  {	"NICAM, L",
+	{ 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
+};
 
 static int tda9874a_setup(struct CHIPSTATE *chip)
 {
 	chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
 	chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
 	chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
-	chip_write(chip, TDA9874A_FMMR, 0x80);
+	if(tda9874a_dic == 0x11) {
+		chip_write(chip, TDA9874A_FMMR, 0x80);
+	} else { /* dic == 0x07 */
+		chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
+		chip_write(chip, TDA9874A_FMMR, 0x00);
+	}
 	chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
 	chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
-	chip_write(chip, TDA9874A_NCONR, 0x00); /* not 0x04 as doc. table 10 says! */
+	chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
 	chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
-	chip_write(chip, TDA9874A_AMCONR, 0xf9);
-	chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80); /* 0x81 */
-	chip_write(chip, TDA9874A_AOSR, 0x80);
-	chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
-	chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
-
+	/* Note: If signal quality is poor you may want to change NICAM */
+	/* error limit registers (NLELR and NUELR) to some greater values. */
+	/* Then the sound would remain stereo, but won't be so clear. */
+	chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
+	chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
+
+	if(tda9874a_dic == 0x11) {
+		chip_write(chip, TDA9874A_AMCONR, 0xf9);
+		chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
+		chip_write(chip, TDA9874A_AOSR, 0x80);
+		chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
+		chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
+	} else { /* dic == 0x07 */
+		chip_write(chip, TDA9874A_AMCONR, 0xfb);
+		chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
+		chip_write(chip, TDA9874A_AOSR, 0x00); // or 0x10
+	}
+	dprintk("tda9874a_setup(): %s [0x%02X].\n",
+		tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
 	return 1;
 }
 
-int tda9874a_getmode(struct CHIPSTATE *chip)
+static int tda9874a_getmode(struct CHIPSTATE *chip)
 {
 	int dsr,nsr,mode;
+	int necr; /* just for debugging */
 
 	mode = VIDEO_SOUND_MONO;
 
@@ -805,55 +862,125 @@
 		return mode;
 	if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
 		return mode;
+	if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
+		return mode;
+
+	/* need to store dsr/nsr somewhere */
+	chip->shadow.bytes[MAXREGS-2] = dsr;
+	chip->shadow.bytes[MAXREGS-1] = nsr;
 
 	if(tda9874a_mode) {
-		/* check also DSR.RSSF and DSR.AMSTAT bits? */
-		if(nsr & 0x02) /* NSR.S/MB */
+		/* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
+		 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
+		 * that sound has (temporarily) switched from NICAM to
+		 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
+		 * error count. So in fact there is no stereo in this case :-(
+		 * But changing the mode to VIDEO_SOUND_MONO would switch
+		 * external 4052 multiplexer in audio_hook().
+		 */
+#if 0
+		if((nsr & 0x02) && !(dsr & 0x10)) /* NSR.S/MB=1 and DSR.AMSTAT=0 */
 			mode |= VIDEO_SOUND_STEREO;
-		if(nsr & 0x01) /* NSR.D/SB */ 
+#else
+		if(nsr & 0x02) /* NSR.S/MB=1 */
+			mode |= VIDEO_SOUND_STEREO;
+#endif
+		if(nsr & 0x01) /* NSR.D/SB=1 */ 
 			mode |= VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2;
 	} else {
-		if(dsr & 0x02) /* DSR.IDSTE */
+		if(dsr & 0x02) /* DSR.IDSTE=1 */
 			mode |= VIDEO_SOUND_STEREO;
-		if(dsr & 0x04) /* DSR.IDDUA */
+		if(dsr & 0x04) /* DSR.IDDUA=1 */
 			mode |= VIDEO_SOUND_LANG1 | VIDEO_SOUND_LANG2;
 	}
 
-	dprintk("tda9874a_getmode(): DSR=0x%X, NSR=0x%X, return: %d.\n",
-		 dsr, nsr, mode);
+	dprintk("tda9874a_getmode(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
+		 dsr, nsr, necr, mode);
 	return mode;
 }
 
-void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
+static void tda9874a_setmode(struct CHIPSTATE *chip, int mode)
 {
-	int aosr=0x80,mdacosr=0x82;
-
-	/* note: TDA9874A has auto-select function for audio output */
-	switch(mode) {
-	case VIDEO_SOUND_MONO:
-	case VIDEO_SOUND_STEREO:
-		break;
-	case VIDEO_SOUND_LANG1:
-		aosr = 0x80; /* dual A/A */
-		mdacosr = (tda9874a_mode) ? 0x82:0x80;
-		break;
-	case VIDEO_SOUND_LANG2:
-		aosr = 0xa0; /* dual B/B */
-		mdacosr = (tda9874a_mode) ? 0x83:0x81;
-		break;
-	default:
-		chip->mode = 0;
-		return;
+	/* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
+	/* If auto-muting is disabled, we can hear a signal of degrading quality. */
+	if(tda9874a_mode) {
+		if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
+			tda9874a_NCONR &= 0xfe; /* enable */
+		else
+			tda9874a_NCONR |= 0x01; /* disable */
+		chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
 	}
 
-	chip_write(chip, TDA9874A_AOSR, aosr);
-	chip_write(chip, TDA9874A_MDACOSR, mdacosr);
+	/* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
+	 * and has auto-select function for audio output (AOSR register).
+	 * Old TDA9874H doesn't support these features.
+	 * TDA9874A also has additional mono output pin (OUTM), which
+	 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
+	 */
+	if(tda9874a_dic == 0x11) {
+		int aosr = 0x80;
+		int mdacosr = (tda9874a_mode) ? 0x82:0x80;
+
+		switch(mode) {
+		case VIDEO_SOUND_MONO:
+		case VIDEO_SOUND_STEREO:
+			break;
+		case VIDEO_SOUND_LANG1:
+			aosr = 0x80; /* auto-select, dual A/A */
+			mdacosr = (tda9874a_mode) ? 0x82:0x80;
+			break;
+		case VIDEO_SOUND_LANG2:
+			aosr = 0xa0; /* auto-select, dual B/B */
+			mdacosr = (tda9874a_mode) ? 0x83:0x81;
+			break;
+		default:
+			chip->mode = 0;
+			return;
+		}
+		chip_write(chip, TDA9874A_AOSR, aosr);
+		chip_write(chip, TDA9874A_MDACOSR, mdacosr);
+
+		dprintk("tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
+			mode, aosr, mdacosr);
 
-	dprintk("tda9874a_setmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
-		mode, aosr, mdacosr);
+	} else { /* dic == 0x07 */
+		int fmmr,aosr;
+
+		switch(mode) {
+		case VIDEO_SOUND_MONO:
+			fmmr = 0x00; /* mono */
+			aosr = 0x10; /* A/A */
+			break;
+		case VIDEO_SOUND_STEREO:
+			if(tda9874a_mode) {
+				fmmr = 0x00;
+				aosr = 0x00; /* handled by NICAM auto-mute */
+			} else {
+				fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
+				aosr = 0x00;
+			}
+			break;
+		case VIDEO_SOUND_LANG1:
+			fmmr = 0x02; /* dual */
+			aosr = 0x10; /* dual A/A */
+			break;
+		case VIDEO_SOUND_LANG2:
+			fmmr = 0x02; /* dual */
+			aosr = 0x20; /* dual B/B */
+			break;
+		default:
+			chip->mode = 0;
+			return;
+		}
+		chip_write(chip, TDA9874A_FMMR, fmmr);
+		chip_write(chip, TDA9874A_AOSR, aosr);
+
+		dprintk("tda9874a_setmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
+			mode, fmmr, aosr);
+	}
 }
 
-int tda9874a_checkit(struct CHIPSTATE *chip)
+static int tda9874a_checkit(struct CHIPSTATE *chip)
 {
 	int dic,sic;	/* device id. and software id. codes */
 
@@ -864,10 +991,15 @@
 
 	dprintk("tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
 
-	return((dic & 0xff) == 0x11);
+	if((dic == 0x11)||(dic == 0x07)) {
+		dprintk("tvaudio: found tda9874%s.\n",(dic == 0x11) ? "a (new)":"h (old)");
+		tda9874a_dic = dic;	/* remember device id. */
+		return 1;
+	}
+	return 0;	/* not found */
 }
 
-int tda9874a_initialize(struct CHIPSTATE *chip)
+static int tda9874a_initialize(struct CHIPSTATE *chip)
 {
 	if(tda9874a_SIF != -1) {
 		if(tda9874a_SIF == 1)
@@ -887,6 +1019,15 @@
 		}
 	}
 
+	if(tda9874a_AMSEL != -1) {
+		if(tda9874a_AMSEL == 0)
+			tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
+		else if(tda9874a_AMSEL == 1)
+			tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
+		else
+			printk(KERN_WARNING "tda9874a: AMSEL parameter must be 0 or 1.\n");
+	}
+
 	tda9874a_setup(chip);
 
 	return 0;
@@ -915,8 +1056,8 @@
 #define TEA6420_S_SE       0x04  /* stereo E */
 #define TEA6420_S_GMU      0x05  /* general mute */
 
-int tea6300_shift10(int val) { return val >> 10; }
-int tea6300_shift12(int val) { return val >> 12; }
+static int tea6300_shift10(int val) { return val >> 10; }
+static int tea6300_shift12(int val) { return val >> 12; }
 
 
 /* ---------------------------------------------------------------------- */
@@ -931,8 +1072,8 @@
 #define TDA8425_S1_OFF     0xEE  /* audio off (mute on) */
 #define TDA8425_S1_ON      0xCE  /* audio on (mute off) - "linear stereo" mode */
 
-int tda8425_shift10(int val) { return val >> 10 | 0xc0; }
-int tda8425_shift12(int val) { return val >> 12 | 0xf0; }
+static int tda8425_shift10(int val) { return val >> 10 | 0xc0; }
+static int tda8425_shift12(int val) { return val >> 12 | 0xf0; }
 
 
 /* ---------------------------------------------------------------------- */
@@ -1015,13 +1156,13 @@
 		
 	},
 	{
-		name:       "tda9874a",
-		id:         I2C_DRIVERID_TDA9874A,
+		name:       "tda9874h/a",
+		id:         I2C_DRIVERID_TDA9874,
 		checkit:    tda9874a_checkit,
 		initialize: tda9874a_initialize,
 		insmodopt:  &tda9874a,
-		addr_lo:    I2C_TDA9874A >> 1,
-		addr_hi:    I2C_TDA9874A >> 1,
+		addr_lo:    I2C_TDA9874 >> 1,
+		addr_hi:    I2C_TDA9874 >> 1,
 
 		getmode:    tda9874a_getmode,
 		setmode:    tda9874a_setmode,
@@ -1160,7 +1301,7 @@
 	chip->c.data = chip;
 
 	/* find description for the chip */
-	dprintk("tvaudio: chip @ addr=0x%x\n", addr<<1);
+	dprintk("tvaudio: chip found @ i2c-addr=0x%x\n", addr<<1);
 	for (desc = chiplist; desc->name != NULL; desc++) {
 		if (0 == *(desc->insmodopt))
 			continue;
@@ -1175,7 +1316,8 @@
 		dprintk("tvaudio: no matching chip description found\n");
 		return -EIO;
 	}
-	dprintk("tvaudio: %s matches:%s%s%s\n",desc->name,
+	printk("tvaudio: found %s\n",desc->name);
+	dprintk("tvaudio: matches:%s%s%s.\n",
 		(desc->flags & CHIP_HAS_VOLUME)     ? " volume"      : "",
 		(desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
 		(desc->flags & CHIP_HAS_INPUTSEL)   ? " audiomux"    : "");
@@ -1272,6 +1414,14 @@
 				chip_write_masked(chip,desc->inputreg,desc->inputmap[*sarg],desc->inputmask);
 		}
 		break;
+
+	case AUDC_SET_RADIO:
+		dprintk(KERN_DEBUG "tvaudio: AUDC_SET_RADIO\n");
+		chip->norm = VIDEO_MODE_RADIO;
+		chip->watch_stereo = 0;
+		/* del_timer(&chip->wt); */
+		break;
+
 	/* --- v4l ioctls --- */
 	/* take care: bttv does userspace copying, we'll get a
 	   kernel pointer here... */
@@ -1290,10 +1440,12 @@
 			va->bass   = chip->bass;
 			va->treble = chip->treble;
 		}
-		if (desc->getmode)
-			va->mode = desc->getmode(chip);
-		else
-			va->mode = VIDEO_SOUND_MONO;
+		if (chip->norm != VIDEO_MODE_RADIO) {
+			if (desc->getmode)
+				va->mode = desc->getmode(chip);
+			else
+				va->mode = VIDEO_SOUND_MONO;
+		}
 		break;
 	}
 
@@ -1316,11 +1468,21 @@
 			chip_write(chip,desc->treblereg,desc->treblefunc(chip->treble));
 		}
 		if (desc->setmode && va->mode) {
+			chip->watch_stereo = 0;
+			/* del_timer(&chip->wt); */
 			chip->mode = va->mode;
 			desc->setmode(chip,va->mode);
 		}
 		break;
 	}
+	case VIDIOCSCHAN:
+	{
+		struct video_channel *vc = arg;
+		
+		dprintk(KERN_DEBUG "tvaudio: VIDIOCSCHAN\n");
+		chip->norm = vc->norm;
+		break;
+	}
 	case VIDIOCSFREQ:
 	{
 	    	chip->mode = 0; /* automatic */
@@ -1339,7 +1501,7 @@
 
 static struct i2c_driver driver = {
         name:            "generic i2c audio driver",
-        id:              I2C_DRIVERID_TVAUDIO, /* FIXME */
+        id:              I2C_DRIVERID_TVAUDIO,
         flags:           I2C_DF_NOTIFY,
         attach_adapter:  chip_probe,
         detach_client:   chip_detach,
@@ -1349,10 +1511,11 @@
 static struct i2c_client client_template =
 {
         name:   "(unset)",
+	flags:  I2C_CLIENT_ALLOW_USE,
         driver: &driver,
 };
 
-int audiochip_init_module(void)
+static int audiochip_init_module(void)
 {
 	struct CHIPDESC  *desc;
 	printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
@@ -1364,7 +1527,7 @@
 	return 0;
 }
 
-void audiochip_cleanup_module(void)
+static void audiochip_cleanup_module(void)
 {
 	i2c_del_driver(&driver);
 }
diff -Nru a/drivers/media/video/tvaudio.h b/drivers/media/video/tvaudio.h
--- a/drivers/media/video/tvaudio.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/video/tvaudio.h	Fri Mar 15 17:51:01 2002
@@ -6,7 +6,7 @@
 #define I2C_TDA9840        0x84
 #define I2C_TDA985x_L      0xb4 /* also used by 9873 */
 #define I2C_TDA985x_H      0xb6
-#define I2C_TDA9874A       0xb0 /* also used by 9875 */
+#define I2C_TDA9874        0xb0 /* also used by 9875 */
 
 #define I2C_TEA6300        0x80
 #define I2C_TEA6420	   0x98
diff -Nru a/drivers/media/video/tvmixer.c b/drivers/media/video/tvmixer.c
--- a/drivers/media/video/tvmixer.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/tvmixer.c	Fri Mar 15 17:51:02 2002
@@ -8,8 +8,9 @@
 #include <linux/slab.h>
 #include <linux/i2c.h>
 #include <linux/videodev.h>
-#include <asm/semaphore.h>
 #include <linux/init.h>
+#include <linux/kdev_t.h>
+#include <asm/semaphore.h>
 
 #include <linux/sound.h>
 #include <linux/soundcard.h>
@@ -320,7 +321,7 @@
 
 /* ----------------------------------------------------------------------- */
 
-int tvmixer_init_module(void)
+static int tvmixer_init_module(void)
 {
 	int i;
 	
@@ -330,7 +331,7 @@
 	return 0;
 }
 
-void tvmixer_cleanup_module(void)
+static void tvmixer_cleanup_module(void)
 {
 	int i;
 	
diff -Nru a/drivers/media/video/video-buf.c b/drivers/media/video/video-buf.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/media/video/video-buf.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,510 @@
+/*
+ * generic helper functions for video4linux capture buffers, to handle
+ * memory management and PCI DMA.  Right now bttv + saa7134 use it.
+ *
+ * The functions expect the hardware being able to scatter gatter
+ * (i.e. the buffers are not linear in physical memory, but fragmented
+ * into PAGE_SIZE chunks).  They also assume the driver does not need
+ * to touch the video data (thus it is probably not useful for USB as
+ * data often must be uncompressed by the drivers).
+ * 
+ * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/iobuf.h>
+#include <linux/vmalloc.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+
+#include "video-buf.h"
+
+static int debug = 0;
+
+MODULE_DESCRIPTION("helper module to manage video4linux pci dma buffers");
+MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
+MODULE_LICENSE("GPL");
+MODULE_PARM(debug,"i");
+
+#define dprintk(level, fmt, arg...)	if (debug >= level) \
+	printk(KERN_DEBUG "vbuf: " fmt, ## arg)
+
+struct scatterlist*
+videobuf_vmalloc_to_sg(unsigned char *virt, int nr_pages)
+{
+	struct scatterlist *sglist;
+	struct page *pg;
+	int i;
+
+	sglist = kmalloc(sizeof(struct scatterlist)*nr_pages, GFP_KERNEL);
+	if (NULL == sglist)
+		return NULL;
+	memset(sglist,0,sizeof(struct scatterlist)*nr_pages);
+	for (i = 0; i < nr_pages; i++, virt += PAGE_SIZE) {
+		pg = vmalloc_to_page(virt);
+		if (NULL == pg)
+			goto err;
+		if (PageHighMem(pg))
+			BUG();
+		sglist[i].page   = pg;
+		sglist[i].length = PAGE_SIZE;
+	}
+	return sglist;
+	
+ err:
+	kfree(sglist);
+	return NULL;
+}
+
+struct scatterlist*
+videobuf_iobuf_to_sg(struct kiobuf *iobuf)
+{
+	struct scatterlist *sglist;
+	int i = 0;
+
+	sglist = kmalloc(sizeof(struct scatterlist) * iobuf->nr_pages,
+			 GFP_KERNEL);
+	if (NULL == sglist)
+		return NULL;
+	memset(sglist,0,sizeof(struct scatterlist) * iobuf->nr_pages);
+
+	if (NULL == iobuf->maplist[0])
+		goto err;
+	if (PageHighMem(iobuf->maplist[0]))
+		/* DMA to highmem pages might not work */
+		goto err;
+	sglist[0].page   = iobuf->maplist[0];
+	sglist[0].offset = iobuf->offset;
+	sglist[0].length = PAGE_SIZE - iobuf->offset;
+	for (i = 1; i < iobuf->nr_pages; i++) {
+		if (NULL == iobuf->maplist[i])
+			goto err;
+		if (PageHighMem(iobuf->maplist[i]))
+			goto err;
+		sglist[i].page   = iobuf->maplist[i];
+		sglist[i].length = PAGE_SIZE;
+	}
+	return sglist;
+
+ err:
+	kfree(sglist);
+	return NULL;
+}
+
+/* --------------------------------------------------------------------- */
+
+int videobuf_dma_init_user(struct videobuf_dmabuf *dma, int direction,
+			   unsigned long data, unsigned long size)
+{
+	int err, rw = 0;
+
+	dma->direction = direction;
+	switch (dma->direction) {
+	case PCI_DMA_FROMDEVICE: rw = READ;  break;
+	case PCI_DMA_TODEVICE:   rw = WRITE; break;
+	default:                 BUG();
+	}
+	if (0 != (err = alloc_kiovec(1,&dma->iobuf)))
+		return err;
+	if (0 != (err = map_user_kiobuf(rw, dma->iobuf, data, size))) {
+		dprintk(1,"map_user_kiobuf: %d\n",err);
+		return err;
+	}
+	dma->nr_pages = dma->iobuf->nr_pages;
+	return 0;
+}
+
+int videobuf_dma_init_kernel(struct videobuf_dmabuf *dma, int direction,
+			     int nr_pages)
+{
+	dma->direction = direction;
+	dma->vmalloc = vmalloc_32(nr_pages << PAGE_SHIFT);
+	if (NULL == dma->vmalloc) {
+		dprintk(1,"vmalloc_32(%d pages) failed\n",nr_pages);
+		return -ENOMEM;
+	}
+	memset(dma->vmalloc,0,nr_pages << PAGE_SHIFT);
+	dma->nr_pages = nr_pages;
+	return 0;
+}
+
+int videobuf_dma_pci_map(struct pci_dev *dev, struct videobuf_dmabuf *dma)
+{
+	int err;
+
+	if (0 == dma->nr_pages)
+		BUG();
+	
+	if (dma->iobuf) {
+		if (0 != (err = lock_kiovec(1,&dma->iobuf,1))) {
+			dprintk(1,"lock_kiovec: %d\n",err);
+			return err;
+		}
+		dma->sglist = videobuf_iobuf_to_sg(dma->iobuf);
+	}
+	if (dma->vmalloc) {
+		dma->sglist = videobuf_vmalloc_to_sg
+			(dma->vmalloc,dma->nr_pages);
+	}
+	if (NULL == dma->sglist) {
+		dprintk(1,"scatterlist is NULL\n");
+		return -ENOMEM;
+	}
+	dma->sglen = pci_map_sg(dev,dma->sglist,dma->nr_pages,
+				 dma->direction);
+	return 0;
+}
+
+int videobuf_dma_pci_sync(struct pci_dev *dev, struct videobuf_dmabuf *dma)
+{
+	if (!dma->sglen)
+		BUG();
+
+	pci_dma_sync_sg(dev,dma->sglist,dma->nr_pages,dma->direction);
+	return 0;
+}
+
+int videobuf_dma_pci_unmap(struct pci_dev *dev, struct videobuf_dmabuf *dma)
+{
+	if (!dma->sglen)
+		return 0;
+
+	pci_unmap_sg(dev,dma->sglist,dma->nr_pages,dma->direction);
+	kfree(dma->sglist);
+	dma->sglist = NULL;
+	dma->sglen = 0;
+	if (dma->iobuf)
+		unlock_kiovec(1,&dma->iobuf);
+	return 0;
+}
+
+int videobuf_dma_free(struct videobuf_dmabuf *dma)
+{
+	if (dma->sglen)
+		BUG();
+
+	if (dma->iobuf) {
+		unmap_kiobuf(dma->iobuf);
+		free_kiovec(1,&dma->iobuf);
+		dma->iobuf = NULL;
+	}
+	if (dma->vmalloc) {
+		vfree(dma->vmalloc);
+		dma->vmalloc = NULL;
+	}
+	dma->direction = PCI_DMA_NONE;
+	return 0;
+}
+
+/* --------------------------------------------------------------------- */
+
+void* videobuf_alloc(int size, int type)
+{
+	struct videobuf_buffer *vb;
+
+	vb = kmalloc(size,GFP_KERNEL);
+	if (NULL != vb) {
+		memset(vb,0,size);
+		vb->type = type;
+		init_waitqueue_head(&vb->done);
+	}
+	return vb;
+}
+
+int videobuf_waiton(struct videobuf_buffer *vb, int non_blocking, int intr)
+{
+	int retval = 0;
+	DECLARE_WAITQUEUE(wait, current);
+	
+	add_wait_queue(&vb->done, &wait);
+	while (vb->state == STATE_ACTIVE ||
+	       vb->state == STATE_QUEUED) {
+		if (non_blocking) {
+			retval = -EAGAIN;
+			break;
+		}
+		current->state = intr ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
+		schedule();
+		if (intr && signal_pending(current)) {
+			dprintk(1,"buffer waiton: -EINTR\n");
+			retval = -EINTR;
+			break;
+		}
+	}
+	remove_wait_queue(&vb->done, &wait);
+	return retval;
+}
+
+int
+videobuf_iolock(struct pci_dev *pci, struct videobuf_buffer *vb)
+{
+	int err,pages;
+
+	if (0 == vb->baddr) {
+		/* no userspace addr -- kernel bounce buffer */
+		pages = PAGE_ALIGN(vb->size) >> PAGE_SHIFT;
+		dprintk(1,"kernel buf size=%ld (%d pages)\n",
+			vb->size,pages);
+		err = videobuf_dma_init_kernel(&vb->dma,PCI_DMA_FROMDEVICE,
+					       pages);
+		if (0 != err)
+			return err;
+	} else {
+		/* dma directly to userspace */
+		dprintk(1,"user buf addr=%08lx size=%ld\n",
+			vb->baddr,vb->bsize);
+		err = videobuf_dma_init_user(&vb->dma,PCI_DMA_FROMDEVICE,
+					     vb->baddr,vb->bsize);
+		if (0 != err)
+			return err;
+	}
+	err = videobuf_dma_pci_map(pci,&vb->dma);
+	if (0 != err)
+		return err;
+	return 0;
+}
+
+#ifdef HAVE_V4L2
+extern void
+videobuf_status(struct v4l2_buffer *b, struct videobuf_buffer *vb)
+{
+	b->index  = vb->i;
+	b->type   = vb->type;
+	b->offset = vb->boff;
+	b->length = vb->bsize;
+	b->flags  = 0;
+	if (vb->map)
+		b->flags |= V4L2_BUF_FLAG_MAPPED;
+	switch (vb->state) {
+	case STATE_PREPARED:
+	case STATE_QUEUED:
+	case STATE_ACTIVE:
+		b->flags |= V4L2_BUF_FLAG_QUEUED;
+		break;
+	case STATE_DONE:
+	case STATE_ERROR:
+		b->flags |= V4L2_BUF_FLAG_DONE;
+		break;
+	case STATE_NEEDS_INIT:
+	case STATE_IDLE:
+		/* nothing */
+		break;
+	}
+	if (!(vb->field & VBUF_FIELD_INTER)) {
+		if (vb->field & VBUF_FIELD_ODD)
+			b->flags |= V4L2_BUF_FLAG_TOPFIELD;
+		if (vb->field & VBUF_FIELD_EVEN)
+			b->flags |= V4L2_BUF_FLAG_BOTFIELD;
+	}
+	b->timestamp = vb->ts;
+	b->bytesused = vb->size;
+	b->sequence  = vb->field_count >> 1;
+}
+#endif /* HAVE_V4L2 */
+
+/* --------------------------------------------------------------------- */
+
+static void
+videobuf_vm_open(struct vm_area_struct *vma)
+{
+	struct videobuf_mapping *map = vma->vm_private_data;
+	map->count++;
+}
+
+static void
+videobuf_vm_close(struct vm_area_struct *vma)
+{
+	struct videobuf_mapping *map = vma->vm_private_data;
+	int i;
+
+	/* down(&fh->lock); FIXME */
+	map->count--;
+	if (0 == map->count) {
+		dprintk(1,"munmap %p\n",map);
+		for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+			if (NULL == map->buflist[i])
+				continue;
+			if (map->buflist[i]->map != map)
+				continue;
+			map->buflist[i]->map   = NULL;
+			map->buflist[i]->baddr = 0;
+			if (map->buflist[i]->free)
+				map->buflist[i]->free(vma->vm_file,map->buflist[i]);
+		}
+		kfree(map);
+	}
+	/* up(&fh->lock); FIXME */
+	return;
+}
+
+/*
+ * Get a anonymous page for the mapping.  Make sure we can DMA to that
+ * memory location with 32bit PCI devices (i.e. don't use highmem for
+ * now ...).  Bounce buffers don't work very well for the data rates
+ * video capture has.
+ */
+static struct page*
+videobuf_vm_nopage(struct vm_area_struct *vma, unsigned long vaddr,
+		  int write_access)
+{
+	struct page *page;
+
+	dprintk(3,"nopage: fault @ %08lx [vma %08lx-%08lx]\n",
+		vaddr,vma->vm_start,vma->vm_end);
+        if (vaddr > vma->vm_end)
+		return NOPAGE_SIGBUS;
+	page = alloc_page(GFP_USER);
+	if (!page)
+		return NOPAGE_OOM;
+	clear_user_page(page_address(page), vaddr);
+	return page;
+}
+
+static struct vm_operations_struct videobuf_vm_ops =
+{
+	open:     videobuf_vm_open,
+	close:    videobuf_vm_close,
+	nopage:   videobuf_vm_nopage,
+};
+
+int videobuf_mmap_setup(struct file *file, struct videobuf_buffer **buflist,
+			int msize, int bcount, int bsize, int type,
+			videobuf_buffer_free free)
+{
+	int i,err;
+
+	err = videobuf_mmap_free(file,buflist);
+	if (0 != err)
+		return err;
+	
+	for (i = 0; i < bcount; i++) {
+		buflist[i] = videobuf_alloc(msize,type);
+		buflist[i]->i     = i;
+		buflist[i]->boff  = bsize * i;
+		buflist[i]->bsize = bsize;
+		buflist[i]->free  = free;
+	}
+	dprintk(1,"mmap setup: %d buffers, %d bytes each\n",
+		bcount,bsize);
+	return 0;
+}
+
+int videobuf_mmap_free(struct file *file, struct videobuf_buffer **buflist)
+{
+	int i;
+
+	for (i = 0; i < VIDEO_MAX_FRAME; i++)
+		if (buflist[i] && buflist[i]->map)
+			return -EBUSY;
+	for (i = 0; i < VIDEO_MAX_FRAME; i++) {
+		if (NULL == buflist[i])
+			continue;
+		if (buflist[i]->free)
+			buflist[i]->free(file,buflist[i]);
+		kfree(buflist[i]);
+		buflist[i] = NULL;
+	}
+	return 0;
+}
+
+int videobuf_mmap_mapper(struct vm_area_struct *vma,
+			struct videobuf_buffer **buflist)
+{
+	struct videobuf_mapping *map;
+	int first,last,size,i;
+
+	if (!(vma->vm_flags & VM_WRITE)) {
+		dprintk(1,"mmap app bug: PROT_WRITE please\n");
+		return -EINVAL;
+	}
+	if (!(vma->vm_flags & VM_SHARED)) {
+		dprintk(1,"mmap app bug: MAP_SHARED please\n");
+		return -EINVAL;
+	}
+
+	/* look for first buffer to map */
+	for (first = 0; first < VIDEO_MAX_FRAME; first++) {
+		if (NULL == buflist[first])
+			continue;
+		if (buflist[first]->boff  == (vma->vm_pgoff << PAGE_SHIFT))
+			break;
+	}
+	if (VIDEO_MAX_FRAME == first) {
+		dprintk(1,"mmap app bug: offset invalid [offset=0x%lx]\n",
+			(vma->vm_pgoff << PAGE_SHIFT));
+		return -EINVAL;
+	}
+
+	/* look for last buffer to map */
+	for (size = 0, last = first; last < VIDEO_MAX_FRAME; last++) {
+		if (NULL == buflist[last])
+			continue;
+		if (buflist[last]->map)
+			return -EBUSY;
+		size += buflist[last]->bsize;
+		if (size == (vma->vm_end - vma->vm_start))
+			break;
+	}
+	if (VIDEO_MAX_FRAME == last) {
+		dprintk(1,"mmap app bug: size invalid [size=0x%lx]\n",
+			(vma->vm_end - vma->vm_start));
+		return -EINVAL;
+	}
+
+	/* create mapping + update buffer list */
+	map = kmalloc(sizeof(struct videobuf_mapping),GFP_KERNEL);
+	if (NULL == map)
+		return -ENOMEM;
+	for (size = 0, i = first; i <= last; size += buflist[i++]->bsize) {
+		buflist[i]->map   = map;
+		buflist[i]->baddr = vma->vm_start + size;
+	}
+	map->count   = 1;
+	map->start   = vma->vm_start;
+	map->end     = vma->vm_end;
+	map->buflist = buflist;
+	vma->vm_ops  = &videobuf_vm_ops;
+	vma->vm_flags |= VM_DONTEXPAND;
+	vma->vm_private_data = map;
+	dprintk(1,"mmap %p: %08lx-%08lx pgoff %08lx bufs %d-%d\n",
+		map,vma->vm_start,vma->vm_end,vma->vm_pgoff,first,last);
+	return 0;
+}
+
+/* --------------------------------------------------------------------- */
+
+EXPORT_SYMBOL_GPL(videobuf_vmalloc_to_sg);
+EXPORT_SYMBOL_GPL(videobuf_iobuf_to_sg);
+
+EXPORT_SYMBOL_GPL(videobuf_dma_init_user);
+EXPORT_SYMBOL_GPL(videobuf_dma_init_kernel);
+EXPORT_SYMBOL_GPL(videobuf_dma_pci_map);
+EXPORT_SYMBOL_GPL(videobuf_dma_pci_sync);
+EXPORT_SYMBOL_GPL(videobuf_dma_pci_unmap);
+EXPORT_SYMBOL_GPL(videobuf_dma_free);
+
+EXPORT_SYMBOL_GPL(videobuf_alloc);
+EXPORT_SYMBOL_GPL(videobuf_waiton);
+EXPORT_SYMBOL_GPL(videobuf_iolock);
+#ifdef HAVE_V4L2
+EXPORT_SYMBOL_GPL(videobuf_status);
+#endif
+
+EXPORT_SYMBOL_GPL(videobuf_mmap_setup);
+EXPORT_SYMBOL_GPL(videobuf_mmap_free);
+EXPORT_SYMBOL_GPL(videobuf_mmap_mapper);
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff -Nru a/drivers/media/video/video-buf.h b/drivers/media/video/video-buf.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/media/video/video-buf.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,178 @@
+/*
+ * generic helper functions for video4linux capture buffers, to handle
+ * memory management and PCI DMA.  Right now bttv + saa7134 use it.
+ *
+ * The functions expect the hardware being able to scatter gatter
+ * (i.e. the buffers are not linear in physical memory, but fragmented
+ * into PAGE_SIZE chunks).  They also assume the driver does not need
+ * to touch the video data (thus it is probably not useful for USB as
+ * data often must be uncompressed by the drivers).
+ * 
+ * (c) 2001,02 Gerd Knorr <kraxel@bytesex.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/videodev.h>
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * Return a scatterlist for some page-aligned vmalloc()'ed memory
+ * block (NULL on errors).  Memory for the scatterlist is allocated
+ * using kmalloc.  The caller must free the memory.
+ */
+struct scatterlist* videobuf_vmalloc_to_sg(unsigned char *virt, int nr_pages);
+
+/*
+ * Return a scatterlist for a locked iobuf (NULL on errors).  Memory
+ * for the scatterlist is allocated using kmalloc.  The caller must
+ * free the memory.
+ */
+struct scatterlist* videobuf_iobuf_to_sg(struct kiobuf *iobuf);
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * A small set of helper functions to manage buffers (both userland
+ * and kernel) for DMA.
+ *
+ * videobuf_init_*_dmabuf()
+ *	creates a buffer.  The userland version takes a userspace
+ *	pointer + length.  The kernel version just wants the size and
+ *	does memory allocation too using vmalloc_32().
+ *
+ * videobuf_pci_*_dmabuf()
+ *	see Documentation/DMA-mapping.txt, these functions to
+ *	basically the same.  The map function does also build a
+ *	scatterlist for the buffer (and unmap frees it ...)
+ *
+ * videobuf_free_dmabuf()
+ *	no comment ...
+ *
+ */
+
+struct videobuf_dmabuf {
+	/* for userland buffer */
+	struct kiobuf       *iobuf;
+
+	/* for kernel buffers */
+	void                *vmalloc;
+
+	/* common */
+	struct scatterlist  *sglist;
+	int                 sglen;
+	int                 nr_pages;
+	int                 direction;
+};
+
+int videobuf_dma_init_user(struct videobuf_dmabuf *dma, int direction,
+			   unsigned long data, unsigned long size);
+int videobuf_dma_init_kernel(struct videobuf_dmabuf *dma, int direction,
+			     int nr_pages);
+int videobuf_dma_pci_map(struct pci_dev *dev, struct videobuf_dmabuf *dma);
+int videobuf_dma_pci_sync(struct pci_dev *dev,
+			  struct videobuf_dmabuf *dma);
+int videobuf_dma_pci_unmap(struct pci_dev *dev, struct videobuf_dmabuf *dma);
+int videobuf_dma_free(struct videobuf_dmabuf *dma);
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * A small set of helper functions to manage video4linux buffers.
+ *
+ * struct videobuf_buffer holds the data structures used by the helper
+ * functions, additionally some commonly used fields for v4l buffers
+ * (width, height, lists, waitqueue) are in there.  That struct should
+ * be used as first element in the drivers buffer struct.
+ * 
+ * about the mmap helpers (videobuf_mmap_*):
+ *
+ * The mmaper function allows to map any subset of contingous buffers.
+ * This includes one mmap() call for all buffers (which the original
+ * video4linux API uses) as well as one mmap() for every single buffer
+ * (which v4l2 uses).
+ *
+ * If there is a valid mapping for a buffer, buffer->baddr/bsize holds
+ * userspace address + size which can be feeded into the
+ * videobuf_dma_init_user function listed above.
+ *
+ */
+
+struct videobuf_buffer;
+typedef void (*videobuf_buffer_free)(struct file *file,
+				     struct videobuf_buffer *vb);
+
+struct videobuf_mapping {
+	int count;
+	int highmem_ok;
+	unsigned long start;
+	unsigned long end;
+	struct videobuf_buffer **buflist;
+};
+
+#define VBUF_FIELD_EVEN  1
+#define VBUF_FIELD_ODD   2
+#define VBUF_FIELD_INTER 4
+
+enum videobuf_state {
+	STATE_NEEDS_INIT = 0,
+	STATE_PREPARED   = 1,
+	STATE_QUEUED     = 2,
+	STATE_ACTIVE     = 3,
+	STATE_DONE       = 4,
+	STATE_ERROR      = 5,
+	STATE_IDLE       = 6,
+};
+
+struct videobuf_buffer {
+	int                     i;
+
+	/* info about the buffer */
+	int                     type;
+	int                     width;
+	int                     height;
+	long                    size;
+	int                     field;
+	enum videobuf_state     state;
+	struct videobuf_dmabuf  dma;
+	struct list_head        stream;  /* QBUF/DQBUF list */
+
+	/* for mmap'ed buffers */
+	unsigned long  boff;             /* buffer offset (mmap) */
+	unsigned long  bsize;            /* buffer size */
+	unsigned long  baddr;            /* buffer addr (userland ptr!) */
+	struct videobuf_mapping *map;
+	videobuf_buffer_free    free;
+
+	/* touched by irq handler */
+	struct list_head        queue;
+	wait_queue_head_t       done;
+	int                     field_count;
+#ifdef HAVE_V4L2
+	stamp_t                 ts;
+#endif
+};
+
+void* videobuf_alloc(int size, int type);
+int videobuf_waiton(struct videobuf_buffer *vb, int non_blocking, int intr);
+int videobuf_iolock(struct pci_dev *pci, struct videobuf_buffer *vb);
+#ifdef HAVE_V4L2
+void videobuf_status(struct v4l2_buffer *b, struct videobuf_buffer *vb);
+#endif
+
+int videobuf_mmap_setup(struct file *file, struct videobuf_buffer **buflist,
+			int msize, int bcount, int bsize, int type,
+			videobuf_buffer_free free);
+int videobuf_mmap_free(struct file *file, struct videobuf_buffer **buflist);
+int videobuf_mmap_mapper(struct vm_area_struct *vma,
+			 struct videobuf_buffer **buflist);
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff -Nru a/drivers/media/video/videodev.c b/drivers/media/video/videodev.c
--- a/drivers/media/video/videodev.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/media/video/videodev.c	Fri Mar 15 17:51:01 2002
@@ -25,15 +25,13 @@
 #include <linux/mm.h>
 #include <linux/string.h>
 #include <linux/errno.h>
-#include <linux/videodev.h>
 #include <linux/init.h>
-
+#include <linux/kmod.h>
 #include <asm/uaccess.h>
 #include <asm/system.h>
 #include <asm/semaphore.h>
 
-#include <linux/kmod.h>
-
+#include <linux/videodev.h>
 
 #define VIDEO_NUM_DEVICES	256 
 
@@ -42,6 +40,7 @@
  */
  
 static struct video_device *video_device[VIDEO_NUM_DEVICES];
+static DECLARE_MUTEX(videodev_lock);
 
 
 #if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
@@ -62,155 +61,138 @@
 
 #endif /* CONFIG_PROC_FS && CONFIG_VIDEO_PROC_FS */
 
-
-/*
- *	Read will do some smarts later on. Buffer pin etc.
- */
- 
-static ssize_t video_read(struct file *file,
-	char *buf, size_t count, loff_t *ppos)
+struct video_device* video_devdata(struct file *file)
 {
-	struct video_device *vfl=video_device[minor(file->f_dentry->d_inode->i_rdev)];
-	if(vfl->read)
-		return vfl->read(vfl, buf, count, file->f_flags&O_NONBLOCK);
-	else
-		return -EINVAL;
+	return video_device[minor(file->f_dentry->d_inode->i_rdev)];
 }
 
-
-/*
- *	Write for now does nothing. No reason it shouldnt do overlay setting
- *	for some boards I guess..
- */
-
-static ssize_t video_write(struct file *file, const char *buf, 
-	size_t count, loff_t *ppos)
-{
-	struct video_device *vfl=video_device[minor(file->f_dentry->d_inode->i_rdev)];
-	if(vfl->write)
-		return vfl->write(vfl, buf, count, file->f_flags&O_NONBLOCK);
-	else
-		return 0;
-}
-
-/*
- *	Poll to see if we're readable, can probably be used for timing on incoming
- *	frames, etc..
- */
-
-static unsigned int video_poll(struct file *file, poll_table * wait)
-{
-	struct video_device *vfl=video_device[minor(file->f_dentry->d_inode->i_rdev)];
-	if(vfl->poll)
-		return vfl->poll(vfl, file, wait);
-	else
-		return 0;
-}
-
-
 /*
  *	Open a video device.
  */
-
 static int video_open(struct inode *inode, struct file *file)
 {
 	unsigned int minor = minor(inode->i_rdev);
-	int err, retval = 0;
+	int err = 0;
 	struct video_device *vfl;
+	struct file_operations *old_fops;
 	
 	if(minor>=VIDEO_NUM_DEVICES)
 		return -ENODEV;
-	lock_kernel();		
+	down(&videodev_lock);
 	vfl=video_device[minor];
 	if(vfl==NULL) {
 		char modname[20];
 
+		up(&videodev_lock);
 		sprintf (modname, "char-major-%d-%d", VIDEO_MAJOR, minor);
 		request_module(modname);
+		down(&videodev_lock);
 		vfl=video_device[minor];
 		if (vfl==NULL) {
-			retval = -ENODEV;
-			goto error_out;
-		}
-	}
-	if(vfl->busy) {
-		retval = -EBUSY;
-		goto error_out;
-	}
-	vfl->busy=1;		/* In case vfl->open sleeps */
-	
-	if(vfl->owner)
-		__MOD_INC_USE_COUNT(vfl->owner);
-	
-	if(vfl->open)
-	{
-		err=vfl->open(vfl,0);	/* Tell the device it is open */
-		if(err)
-		{
-			vfl->busy=0;
-			if(vfl->owner)
-				__MOD_DEC_USE_COUNT(vfl->owner);
-			
-			unlock_kernel();
-			return err;
+			up(&videodev_lock);
+			return -ENODEV;
 		}
 	}
-	unlock_kernel();
-	return 0;
-error_out:
-	unlock_kernel();
-	return retval;
+	old_fops = file->f_op;
+	file->f_op = fops_get(vfl->fops);
+	if(file->f_op->open)
+		err = file->f_op->open(inode,file);
+	if (err) {
+		fops_put(file->f_op);
+		file->f_op = fops_get(old_fops);
+	}
+	fops_put(old_fops);
+	up(&videodev_lock);
+	return err;
 }
 
 /*
- *	Last close of a video for Linux device
+ * ioctl helper function -- handles userspace copying
  */
+int
+video_generic_ioctl(struct inode *inode, struct file *file,
+		    unsigned int cmd, unsigned long arg)
+{
+	struct  video_device *vfl = video_devdata(file);
+	char	sbuf[128];
+	void    *mbuf = NULL;
+	void	*parg = NULL;
+	int	err  = -EINVAL;
 	
-static int video_release(struct inode *inode, struct file *file)
-{
-	struct video_device *vfl;
-	lock_kernel();
-	vfl=video_device[minor(inode->i_rdev)];
-	if(vfl->close)
-		vfl->close(vfl);
-	vfl->busy=0;
-	if(vfl->owner)
-		__MOD_DEC_USE_COUNT(vfl->owner);
-	unlock_kernel();
-	return 0;
-}
+	if (vfl->kernel_ioctl == NULL)
+		return -EINVAL;
 
-static int video_ioctl(struct inode *inode, struct file *file,
-	unsigned int cmd, unsigned long arg)
-{
-	struct video_device *vfl=video_device[minor(inode->i_rdev)];
-	int err=vfl->ioctl(vfl, cmd, (void *)arg);
+	/*  Copy arguments into temp kernel buffer  */
+	switch (_IOC_DIR(cmd)) {
+	case _IOC_NONE:
+		parg = (void *)arg;
+		break;
+	case _IOC_READ: /* some v4l ioctls are marked wrong ... */
+	case _IOC_WRITE:
+	case (_IOC_WRITE | _IOC_READ):
+		if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
+			parg = sbuf;
+		} else {
+			/* too big to allocate from stack */
+			mbuf = kmalloc(_IOC_SIZE(cmd),GFP_KERNEL);
+			if (NULL == mbuf)
+				return -ENOMEM;
+			parg = mbuf;
+		}
+		
+		err = -EFAULT;
+		if (copy_from_user(parg, (void *)arg, _IOC_SIZE(cmd)))
+			goto out;
+		break;
+	}
 
-	if(err!=-ENOIOCTLCMD)
-		return err;
-	
-	switch(cmd)
+	/* call driver */
+	err = vfl->kernel_ioctl(inode, file, cmd, parg);
+	if (err == -ENOIOCTLCMD)
+		err = -EINVAL;
+	if (err < 0)
+		goto out;
+
+	/*  Copy results into user buffer  */
+	switch (_IOC_DIR(cmd))
 	{
-		default:
-			return -EINVAL;
+	case _IOC_READ:
+	case (_IOC_WRITE | _IOC_READ):
+		if (copy_to_user((void *)arg, parg, _IOC_SIZE(cmd)))
+			err = -EFAULT;
+		break;
 	}
+
+out:
+	if (mbuf)
+		kfree(mbuf);
+	return err;
 }
 
 /*
- *	We need to do MMAP support
+ * open/release helper functions -- handle exclusive opens
  */
-  
-int video_mmap(struct file *file, struct vm_area_struct *vma)
+extern int video_exclusive_open(struct inode *inode, struct file *file)
 {
-	int ret = -EINVAL;
-	struct video_device *vfl=video_device[minor(file->f_dentry->d_inode->i_rdev)];
-	if(vfl->mmap) {
-		lock_kernel();
-		ret = vfl->mmap(vma, vfl, (char *)vma->vm_start, 
-				(unsigned long)(vma->vm_end-vma->vm_start));
-		unlock_kernel();
+	struct  video_device *vfl = video_devdata(file);
+	int retval = 0;
+
+	down(&vfl->lock);
+	if (vfl->users) {
+		retval = -EBUSY;
+	} else {
+		vfl->users++;
 	}
-	return ret;
+	up(&vfl->lock);
+	return retval;
+}
+
+extern int video_exclusive_release(struct inode *inode, struct file *file)
+{
+	struct  video_device *vfl = video_devdata(file);
+	
+	vfl->users--;
+	return 0;
 }
 
 /*
@@ -392,13 +374,10 @@
  *	%VFL_TYPE_RADIO - A radio card	
  */
 
-static DECLARE_MUTEX(videodev_register_lock);
-
 int video_register_device(struct video_device *vfd, int type, int nr)
 {
 	int i=0;
 	int base;
-	int err;
 	int end;
 	char *name_base;
 	char name[16];
@@ -430,50 +409,36 @@
 	}
 
 	/* pick a minor number */
-	down(&videodev_register_lock);
+	down(&videodev_lock);
 	if (-1 == nr) {
 		/* use first free */
 		for(i=base;i<end;i++)
 			if (NULL == video_device[i])
 				break;
 		if (i == end) {
-			up(&videodev_register_lock);
+			up(&videodev_lock);
 			return -ENFILE;
 		}
 	} else {
 		/* use the one the driver asked for */
 		i = base+nr;
 		if (NULL != video_device[i]) {
-			up(&videodev_register_lock);
+			up(&videodev_lock);
 			return -ENFILE;
 		}
 	}
 	video_device[i]=vfd;
 	vfd->minor=i;
-	up(&videodev_register_lock);
+	up(&videodev_lock);
 
-	/* The init call may sleep so we book the slot out
-	   then call */
-	MOD_INC_USE_COUNT;
-	if(vfd->initialize) {
-		err=vfd->initialize(vfd);
-		if(err<0) {
-			video_device[i]=NULL;
-			MOD_DEC_USE_COUNT;
-			return err;
-		}
-	}
 	sprintf (name, "v4l/%s%d", name_base, i - base);
-	/*
-	 *	Start the device root only. Anything else
-	 *	has serious privacy issues.
-	 */
 	vfd->devfs_handle =
 		devfs_register (NULL, name, DEVFS_FL_DEFAULT,
 				VIDEO_MAJOR, vfd->minor,
 				S_IFCHR | S_IRUSR | S_IWUSR,
 				&video_fops,
 				NULL);
+	init_MUTEX(&vfd->lock);
 	
 #if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
 	sprintf (name, "%s%d", name_base, i - base);
@@ -492,8 +457,9 @@
  
 void video_unregister_device(struct video_device *vfd)
 {
+	down(&videodev_lock);
 	if(video_device[vfd->minor]!=vfd)
-		panic("vfd: bad unregister");
+		panic("videodev: bad unregister");
 
 #if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
 	videodev_proc_destroy_dev (vfd);
@@ -501,7 +467,7 @@
 
 	devfs_unregister (vfd->devfs_handle);
 	video_device[vfd->minor]=NULL;
-	MOD_DEC_USE_COUNT;
+	up(&videodev_lock);
 }
 
 
@@ -509,13 +475,7 @@
 {
 	owner:		THIS_MODULE,
 	llseek:		no_llseek,
-	read:		video_read,
-	write:		video_write,
-	ioctl:		video_ioctl,
-	mmap:		video_mmap,
 	open:		video_open,
-	release:	video_release,
-	poll:		video_poll,
 };
 
 /*
@@ -540,12 +500,9 @@
 
 static void __exit videodev_exit(void)
 {
-#ifdef MODULE		
 #if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
 	videodev_proc_destroy ();
 #endif
-#endif
-	
 	devfs_unregister_chrdev(VIDEO_MAJOR, "video_capture");
 }
 
@@ -554,6 +511,10 @@
 
 EXPORT_SYMBOL(video_register_device);
 EXPORT_SYMBOL(video_unregister_device);
+EXPORT_SYMBOL(video_devdata);
+EXPORT_SYMBOL(video_generic_ioctl);
+EXPORT_SYMBOL(video_exclusive_open);
+EXPORT_SYMBOL(video_exclusive_release);
 
 MODULE_AUTHOR("Alan Cox");
 MODULE_DESCRIPTION("Device registrar for Video4Linux drivers");
diff -Nru a/drivers/media/video/w9966.c b/drivers/media/video/w9966.c
--- a/drivers/media/video/w9966.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/media/video/w9966.c	Fri Mar 15 17:51:02 2002
@@ -173,10 +173,27 @@
 static int w9966_i2c_wbyte(struct w9966_dev* cam, int data);
 static int w9966_i2c_rbyte(struct w9966_dev* cam);
 
-static int  w9966_v4l_open(struct video_device *vdev, int mode);
-static void w9966_v4l_close(struct video_device *vdev);
-static int  w9966_v4l_ioctl(struct video_device *vdev, unsigned int cmd, void *arg);
-static long w9966_v4l_read(struct video_device *vdev, char *buf, unsigned long count, int noblock);
+static int w9966_v4l_ioctl(struct inode *inode, struct file *file,
+			   unsigned int cmd, void *arg);
+static int w9966_v4l_read(struct file *file, char *buf,
+			  size_t count, loff_t *ppos);
+
+static struct file_operations w9966_fops = {
+	owner:		THIS_MODULE,
+	open:           video_exclusive_open,
+	release:        video_exclusive_release,
+	ioctl:          video_generic_ioctl,
+	read:           w9966_v4l_read,
+	llseek:         no_llseek,
+};
+static struct video_device w9966_template = {
+	owner:		THIS_MODULE,
+	name:           W9966_DRIVERNAME,
+	type:           VID_TYPE_CAPTURE | VID_TYPE_SCALES,
+	hardware:       VID_HARDWARE_W9966,
+	fops:           &w9966_fops,
+	kernel_ioctl:   w9966_v4l_ioctl,
+};
 
 /*
  *	Private function defines
@@ -309,16 +326,8 @@
 	w9966_pdev_release(cam);
 
 // Fill in the video_device struct and register us to v4l
-	memset(&cam->vdev, 0, sizeof(struct video_device));
-	strcpy(cam->vdev.name, W9966_DRIVERNAME);
-	cam->vdev.type = VID_TYPE_CAPTURE | VID_TYPE_SCALES;
-	cam->vdev.hardware = VID_HARDWARE_W9966;
-	cam->vdev.open = &w9966_v4l_open;
-	cam->vdev.close = &w9966_v4l_close;
-	cam->vdev.read = &w9966_v4l_read;
-	cam->vdev.ioctl = &w9966_v4l_ioctl;
+	memcpy(&cam->vdev, &w9966_template, sizeof(struct video_device));
 	cam->vdev.priv = (void*)cam;
-	cam->vdev.owner = THIS_MODULE;
 
 	if (video_register_device(&cam->vdev, VFL_TYPE_GRABBER, video_nr) == -1)		 
 		return -1;
@@ -691,101 +700,67 @@
  *	Video4linux interfacing
  */
 
-static int w9966_v4l_open(struct video_device *vdev, int flags)
-{
-	return 0;
-}
-
-static void w9966_v4l_close(struct video_device *vdev)
-{
-}
-
-static int w9966_v4l_ioctl(struct video_device *vdev, unsigned int cmd, void *arg)
+static int w9966_v4l_ioctl(struct inode *inode, struct file *file,
+			   unsigned int cmd, void *arg)
 {
+	struct video_device *vdev = video_devdata(file);
 	struct w9966_dev *cam = (struct w9966_dev*)vdev->priv;
 	
 	switch(cmd)
 	{
 	case VIDIOCGCAP:
 	{
-		struct video_capability vcap = {
-			W9966_DRIVERNAME,	// name
-			VID_TYPE_CAPTURE | VID_TYPE_SCALES,	// type
-			1, 0,			// vid, aud channels
-			W9966_WND_MAX_W,	// max w
-			W9966_WND_MAX_H,	// max h
-			2, 1			// min w, min h
+		static struct video_capability vcap = {
+			name:      W9966_DRIVERNAME,
+			type:      VID_TYPE_CAPTURE | VID_TYPE_SCALES,
+			channels:  1,
+			audios:    0,
+			maxwidth:  W9966_WND_MAX_W,
+			maxheight: W9966_WND_MAX_H,
+			minwidth:  2,
+			minheight: 1,
 		};
-
-		if(copy_to_user(arg, &vcap, sizeof(vcap)) != 0)
-			return -EFAULT;
-
+		struct video_capability *cap = arg;
+		*cap = vcap;
 		return 0;
 	}
 	case VIDIOCGCHAN:
 	{
-		struct video_channel vch;
-		if(copy_from_user(&vch, arg, sizeof(vch)) != 0)
-			return -EFAULT;
-
-		if(vch.channel != 0)	// We only support one channel (#0)
+		struct video_channel *vch = arg;
+		if(vch->channel != 0)	// We only support one channel (#0)
 			return -EINVAL;
-
-		strcpy(vch.name, "CCD-input");
-		vch.flags = 0;		// We have no tuner or audio
-		vch.tuners = 0;
-		vch.type = VIDEO_TYPE_CAMERA;
-		vch.norm = 0;		// ???
-		
-		if(copy_to_user(arg, &vch, sizeof(vch)) != 0)
-			return -EFAULT;
-		
+		memset(vch,0,sizeof(*vch));
+		strcpy(vch->name, "CCD-input");
+		vch->type = VIDEO_TYPE_CAMERA;
 		return 0;
 	}
 	case VIDIOCSCHAN:
 	{
-		struct video_channel vch;
-		if(copy_from_user(&vch, arg, sizeof(vch) ) != 0)
-			return -EFAULT;
-		
-		if(vch.channel != 0)
+		struct video_channel *vch = arg;
+		if(vch->channel != 0)
 			return -EINVAL;
-		
 		return 0;
 	}
 	case VIDIOCGTUNER:
 	{
-		struct video_tuner vtune;
-		if(copy_from_user(&vtune, arg, sizeof(vtune)) != 0)
-			return -EFAULT;
-		
-		if(vtune.tuner != 0);
+		struct video_tuner *vtune = arg;
+		if(vtune->tuner != 0);
 			return -EINVAL;
-		
-		strcpy(vtune.name, "no tuner");
-		vtune.rangelow = 0;
-		vtune.rangehigh = 0;
-		vtune.flags = VIDEO_TUNER_NORM;
-		vtune.mode = VIDEO_MODE_AUTO;
-		vtune.signal = 0xffff;
-		
-		if(copy_to_user(arg, &vtune, sizeof(vtune)) != 0)
-			return -EFAULT;
-		
+		strcpy(vtune->name, "no tuner");
+		vtune->rangelow = 0;
+		vtune->rangehigh = 0;
+		vtune->flags = VIDEO_TUNER_NORM;
+		vtune->mode = VIDEO_MODE_AUTO;
+		vtune->signal = 0xffff;
 		return 0;
 	}
 	case VIDIOCSTUNER:
 	{
-		struct video_tuner vtune;
-		if (copy_from_user(&vtune, arg, sizeof(vtune)) != 0)
-			return -EFAULT;
-		
-		if (vtune.tuner != 0)
+		struct video_tuner *vtune = arg;
+		if (vtune->tuner != 0)
 			return -EINVAL;
-		
-		if (vtune.mode != VIDEO_MODE_AUTO)
+		if (vtune->mode != VIDEO_MODE_AUTO)
 			return -EINVAL;
-		
 		return 0;
 	}
 	case VIDIOCGPICT:
@@ -798,25 +773,20 @@
 			0x8000,			// whiteness
 			16, VIDEO_PALETTE_YUV422// bpp, palette format
 		};
-
-		if(copy_to_user(arg, &vpic, sizeof(vpic)) != 0)
-			return -EFAULT;
-
+		struct video_picture *pic = arg;
+		*pic = vpic;
 		return 0;
 	}
 	case VIDIOCSPICT:
 	{
-		struct video_picture vpic;
-		if(copy_from_user(&vpic, arg, sizeof(vpic)) != 0)
-			return -EFAULT;
-		
-		if (vpic.depth != 16 || vpic.palette != VIDEO_PALETTE_YUV422)
+		struct video_picture *vpic = arg;
+		if (vpic->depth != 16 || vpic->palette != VIDEO_PALETTE_YUV422)
 			return -EINVAL;
 			
-		cam->brightness = vpic.brightness >> 8;
-		cam->hue = (vpic.hue >> 8) - 128;
-		cam->color = vpic.colour >> 9;
-		cam->contrast = vpic.contrast >> 9;
+		cam->brightness = vpic->brightness >> 8;
+		cam->hue = (vpic->hue >> 8) - 128;
+		cam->color = vpic->colour >> 9;
+		cam->contrast = vpic->contrast >> 9;
 
 		w9966_pdev_claim(cam);
 		
@@ -827,7 +797,7 @@
 			w9966_wReg_i2c(cam, 0x0d, cam->hue) == -1
 		) {
 			w9966_pdev_release(cam);
-			return -EFAULT;
+			return -EIO;
 		}
 		
 		w9966_pdev_release(cam);
@@ -836,42 +806,35 @@
 	case VIDIOCSWIN:
 	{
 		int ret;
-		struct video_window vwin;
+		struct video_window *vwin = arg;
 		
-		if (copy_from_user(&vwin, arg, sizeof(vwin)) != 0)
-			return -EFAULT;		
-		if (vwin.flags != 0)
+		if (vwin->flags != 0)
 			return -EINVAL;
-		if (vwin.clipcount != 0)
+		if (vwin->clipcount != 0)
 			return -EINVAL;
-		if (vwin.width < 2 || vwin.width > W9966_WND_MAX_W)
+		if (vwin->width < 2 || vwin->width > W9966_WND_MAX_W)
 			return -EINVAL;		
-		if (vwin.height < 1 || vwin.height > W9966_WND_MAX_H)
+		if (vwin->height < 1 || vwin->height > W9966_WND_MAX_H)
 			return -EINVAL;
 
 		// Update camera regs
 		w9966_pdev_claim(cam);
-		ret = w9966_setup(cam, 0, 0, 1023, 1023, vwin.width, vwin.height);
+		ret = w9966_setup(cam, 0, 0, 1023, 1023, vwin->width, vwin->height);
 		w9966_pdev_release(cam);
 		
 		if (ret != 0) {
 			DPRINTF("VIDIOCSWIN: w9966_setup() failed.\n");
-			return -EFAULT;
+			return -EIO;
 		}
 		
 		return 0;
 	}
 	case VIDIOCGWIN:
 	{
-		struct video_window vwin;
-		memset(&vwin, 0, sizeof(vwin));
-		
-		vwin.width = cam->width;
-		vwin.height = cam->height;
-		
-		if(copy_to_user(arg, &vwin, sizeof(vwin)) != 0)
-			return -EFAULT;
-		
+		struct video_window *vwin = arg;
+		memset(vwin, 0, sizeof(*vwin));
+		vwin->width = cam->width;
+		vwin->height = cam->height;
 		return 0;
 	}
 	// Unimplemented
@@ -891,8 +854,10 @@
 }
 
 // Capture data
-static long w9966_v4l_read(struct video_device *vdev, char *buf, unsigned long count,  int noblock)
+static int w9966_v4l_read(struct file *file, char *buf,
+			  size_t count, loff_t *ppos)
 {
+	struct video_device *vdev = video_devdata(file);
 	struct w9966_dev *cam = (struct w9966_dev *)vdev->priv;
 	unsigned char addr = 0xa0;	// ECP, read, CCD-transfer, 00000
 	unsigned char* dest = (unsigned char*)buf;
diff -Nru a/drivers/net/8139cp.c b/drivers/net/8139cp.c
--- a/drivers/net/8139cp.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/8139cp.c	Fri Mar 15 17:51:03 2002
@@ -65,9 +65,15 @@
 #include <asm/io.h>
 #include <asm/uaccess.h>
 
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#define CP_VLAN_TAG_USED 1
+#define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
+	do { (tx_desc)->opts2 = (vlan_tag_value); } while (0)
+#else
 #define CP_VLAN_TAG_USED 0
 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
 	do { (tx_desc)->opts2 = 0; } while (0)
+#endif
 
 /* These identify the driver base version and may not be removed. */
 static char version[] __devinitdata =
@@ -643,7 +649,7 @@
 
 	cp->tx_tail = tx_tail;
 
-	if (netif_queue_stopped(cp->dev) && (TX_BUFFS_AVAIL(cp) > 1))
+	if (netif_queue_stopped(cp->dev) && (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1)))
 		netif_wake_queue(cp->dev);
 }
 
@@ -658,9 +664,12 @@
 
 	spin_lock_irq(&cp->lock);
 
+	/* This is a hard error, log it. */
 	if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
 		netif_stop_queue(dev);
 		spin_unlock_irq(&cp->lock);
+		printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
+		       dev->name);
 		return 1;
 	}
 
@@ -760,9 +769,7 @@
 	if (netif_msg_tx_queued(cp))
 		printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
 		       dev->name, entry, skb->len);
-	if (TX_BUFFS_AVAIL(cp) < 0)
-		BUG();
-	if (TX_BUFFS_AVAIL(cp) == 0)
+	if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
 		netif_stop_queue(dev);
 
 	spin_unlock_irq(&cp->lock);
@@ -773,6 +780,9 @@
 	return 0;
 }
 
+/* Set or clear the multicast filter for this adaptor.
+   This routine is not state sensitive and need not be SMP locked. */
+
 static void __cp_set_rx_mode (struct net_device *dev)
 {
 	struct cp_private *cp = dev->priv;
@@ -1072,6 +1082,7 @@
 
 	/* if network interface not up, no need for complexity */
 	if (!netif_running(dev)) {
+		dev->mtu = new_mtu;
 		cp_set_rxbufsize(cp);	/* set new rx buf size */
 		return 0;
 	}
@@ -1081,6 +1092,7 @@
 	cp_stop_hw(cp);			/* stop h/w and free rings */
 	cp_clean_rings(cp);
 
+	dev->mtu = new_mtu;
 	cp_set_rxbufsize(cp);		/* set new rx buf size */
 
 	rc = cp_init_rings(cp);		/* realloc and restart h/w */
@@ -1226,7 +1238,7 @@
 }
 
 #if CP_VLAN_TAG_USED
-static int cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
+static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 {
 	struct cp_private *cp = dev->priv;
 
@@ -1234,8 +1246,6 @@
 	cp->vlgrp = grp;
 	cpw16(CpCmd, cpr16(CpCmd) | RxVlanOn);
 	spin_unlock_irq(&cp->lock);
-
-	return 0;
 }
 
 static void cp_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
diff -Nru a/drivers/net/acenic.c b/drivers/net/acenic.c
--- a/drivers/net/acenic.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/acenic.c	Fri Mar 15 17:51:03 2002
@@ -2,7 +2,7 @@
  * acenic.c: Linux driver for the Alteon AceNIC Gigabit Ethernet card
  *           and other Tigon based cards.
  *
- * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
+ * Copyright 1998-2002 by Jes Sorensen, <jes@trained-monkey.org>.
  *
  * Thanks to Alteon and 3Com for providing hardware and documentation
  * enabling me to write this driver.
@@ -30,6 +30,7 @@
  *   Pierrick Pinasseau (CERN): For lending me an Ultra 5 to test the
  *                              driver under Linux/Sparc64
  *   Matt Domsch <Matt_Domsch@dell.com>: Detect Alteon 1000baseT cards
+ *                                       ETHTOOL_GDRVINFO support
  *   Chip Salzenberg <chip@valinux.com>: Fix race condition between tx
  *                                       handler and close() cleanup.
  *   Ken Aaker <kdaaker@rchland.vnet.ibm.com>: Correct check for whether
@@ -64,6 +65,7 @@
 #include <linux/mm.h>
 #include <linux/highmem.h>
 #include <linux/sockios.h>
+#include <linux/if_vlan.h>
 
 #ifdef SIOCETHTOOL
 #include <linux/ethtool.h>
@@ -83,8 +85,10 @@
 
 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
 #define ACE_IS_TIGON_I(ap)	0
+#define ACE_TX_RING_ENTRIES(ap)	MAX_TX_RING_ENTRIES
 #else
 #define ACE_IS_TIGON_I(ap)	(ap->version == 1)
+#define ACE_TX_RING_ENTRIES(ap)	ap->tx_ring_entries
 #endif
 
 #ifndef PCI_VENDOR_ID_ALTEON
@@ -314,6 +318,12 @@
 #define BOARD_IDX_STATIC	0
 #define BOARD_IDX_OVERFLOW	-1
 
+#if (defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)) && \
+	defined(NETIF_F_HW_VLAN_RX)
+#define ACENIC_DO_VLAN	1
+#else
+#define ACENIC_DO_VLAN	0
+#endif
 
 #include "acenic.h"
 
@@ -553,7 +563,7 @@
 static int dis_pci_mem_inval[ACE_MAX_MOD_PARMS] = {1, 1, 1, 1, 1, 1, 1, 1};
 
 static char version[] __initdata = 
-  "acenic.c: v0.85 11/08/2001  Jes Sorensen, linux-acenic@SunSITE.dk\n"
+  "acenic.c: v0.88 03/14/2002  Jes Sorensen, linux-acenic@SunSITE.dk\n"
   "                            http://home.cern.ch/~jes/gige/acenic.html\n";
 
 static struct net_device *root_dev;
@@ -620,10 +630,14 @@
 		ap = dev->priv;
 		ap->pdev = pdev;
 
-		dev->irq = pdev->irq;
 		dev->open = &ace_open;
 		dev->hard_start_xmit = &ace_start_xmit;
 		dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
+#if ACENIC_DO_VLAN
+		dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+		dev->vlan_rx_register = ace_vlan_rx_register;
+		dev->vlan_rx_kill_vid = ace_vlan_rx_kill_vid;
+#endif
 		if (1) {
 			static void ace_watchdog(struct net_device *dev);
 			dev->tx_timeout = &ace_watchdog;
@@ -725,9 +739,9 @@
 		ap->name [sizeof (ap->name) - 1] = '\0';
 		printk("Gigabit Ethernet at 0x%08lx, ", dev->base_addr);
 #ifdef __sparc__
-		printk("irq %s\n", __irq_itoa(dev->irq));
+		printk("irq %s\n", __irq_itoa(pdev->irq));
 #else
-		printk("irq %i\n", dev->irq);
+		printk("irq %i\n", pdev->irq);
 #endif
 
 #ifdef CONFIG_ACENIC_OMIT_TIGON_I
@@ -960,6 +974,13 @@
 				    ap->evt_ring_dma);
 		ap->evt_ring = NULL;
 	}
+	if (ap->tx_ring != NULL && !ACE_IS_TIGON_I(ap)) {
+		size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
+		pci_free_consistent(ap->pdev, size, ap->tx_ring,
+				    ap->tx_ring_dma);
+	}
+	ap->tx_ring = NULL;
+
 	if (ap->evt_prd != NULL) {
 		pci_free_consistent(ap->pdev, sizeof(u32),
 				    (void *)ap->evt_prd, ap->evt_prd_dma);
@@ -1006,12 +1027,19 @@
 	if (ap->evt_ring == NULL)
 		goto fail;
 
-	size = (sizeof(struct tx_desc) * TX_RING_ENTRIES);
+	/*
+	 * Only allocate a host TX ring for the Tigon II, the Tigon I
+	 * has to use PCI registers for this ;-(
+	 */
+	if (!ACE_IS_TIGON_I(ap)) {
+		size = (sizeof(struct tx_desc) * MAX_TX_RING_ENTRIES);
 
-	ap->tx_ring = pci_alloc_consistent(ap->pdev, size, &ap->tx_ring_dma);
+		ap->tx_ring = pci_alloc_consistent(ap->pdev, size,
+						   &ap->tx_ring_dma);
 
-	if (ap->tx_ring == NULL)
-		goto fail;
+		if (ap->tx_ring == NULL)
+			goto fail;
+	}
 
 	ap->evt_prd = pci_alloc_consistent(ap->pdev, sizeof(u32),
 					   &ap->evt_prd_dma);
@@ -1086,6 +1114,7 @@
 	struct ace_private *ap;
 	struct ace_regs *regs;
 	struct ace_info *info = NULL;
+	struct pci_dev *pdev;
 	unsigned long myjif;
 	u64 tmp_ptr;
 	u32 tig_ver, mac1, mac2, tmp, pci_state;
@@ -1144,6 +1173,7 @@
 		       tigonFwReleaseFix);
 		writel(0, &regs->LocalCtrl);
 		ap->version = 1;
+		ap->tx_ring_entries = TIGON_I_TX_RING_ENTRIES;
 		break;
 #endif
 	case 6:
@@ -1159,6 +1189,7 @@
 		writel(SRAM_BANK_512K, &regs->LocalCtrl);
 		writel(SYNC_SRAM_TIMING, &regs->MiscCfg);
 		ap->version = 2;
+		ap->tx_ring_entries = MAX_TX_RING_ENTRIES;
 		break;
 	default:
 		printk(KERN_WARNING "  Unsupported Tigon version detected "
@@ -1224,7 +1255,8 @@
 	 * Ie. having two NICs in the machine, one will have the cache
 	 * line set at boot time, the other will not.
 	 */
-	pci_read_config_byte(ap->pdev, PCI_CACHE_LINE_SIZE, &cache_size);
+	pdev = ap->pdev;
+	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_size);
 	cache_size <<= 2;
 	if (cache_size != SMP_CACHE_BYTES) {
 		printk(KERN_INFO "  PCI cache line size set incorrectly "
@@ -1233,7 +1265,7 @@
 			printk("expecting %i\n", SMP_CACHE_BYTES);
 		else {
 			printk("correcting to %i\n", SMP_CACHE_BYTES);
-			pci_write_config_byte(ap->pdev, PCI_CACHE_LINE_SIZE,
+			pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
 					      SMP_CACHE_BYTES >> 2);
 		}
 	}
@@ -1265,7 +1297,7 @@
 		    dis_pci_mem_inval[board_idx]) {
 			if (ap->pci_command & PCI_COMMAND_INVALIDATE) {
 				ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
-				pci_write_config_word(ap->pdev, PCI_COMMAND,
+				pci_write_config_word(pdev, PCI_COMMAND,
 						      ap->pci_command);
 				printk(KERN_INFO "  Disabling PCI memory "
 				       "write and invalidate\n");
@@ -1292,7 +1324,7 @@
 				       "supported, PCI write and invalidate "
 				       "disabled\n", SMP_CACHE_BYTES);
 				ap->pci_command &= ~PCI_COMMAND_INVALIDATE;
-				pci_write_config_word(ap->pdev, PCI_COMMAND,
+				pci_write_config_word(pdev, PCI_COMMAND,
 						      ap->pci_command);
 			}
 		}
@@ -1334,16 +1366,16 @@
 	if (!(ap->pci_command & PCI_COMMAND_FAST_BACK)) {
 		printk(KERN_INFO "  Enabling PCI Fast Back to Back\n");
 		ap->pci_command |= PCI_COMMAND_FAST_BACK;
-		pci_write_config_word(ap->pdev, PCI_COMMAND, ap->pci_command);
+		pci_write_config_word(pdev, PCI_COMMAND, ap->pci_command);
 	}
 #endif
 		
 	/*
 	 * Configure DMA attributes.
 	 */
-	if (!pci_set_dma_mask(ap->pdev, 0xffffffffffffffffULL)) {
+	if (!pci_set_dma_mask(pdev, 0xffffffffffffffffULL)) {
 		ap->pci_using_dac = 1;
-	} else if (!pci_set_dma_mask(ap->pdev, 0xffffffffULL)) {
+	} else if (!pci_set_dma_mask(pdev, 0xffffffffULL)) {
 		ap->pci_using_dac = 0;
 	} else {
 		ecode = -ENODEV;
@@ -1370,12 +1402,14 @@
 		goto init_error;
 	}
 
-	ecode = request_irq(dev->irq, ace_interrupt, SA_SHIRQ, dev->name, dev);
+	ecode = request_irq(pdev->irq, ace_interrupt, SA_SHIRQ,
+			    dev->name, dev);
 	if (ecode) {
 		printk(KERN_WARNING "%s: Requested IRQ %d is busy\n",
-		       dev->name, dev->irq);
+		       dev->name, pdev->irq);
 		goto init_error;
-	}
+	} else
+		dev->irq = pdev->irq;
 
 	/*
 	 * Register the device here to be able to catch allocated
@@ -1386,7 +1420,7 @@
 
 #ifdef INDEX_DEBUG
 	spin_lock_init(&ap->debug_lock);
-	ap->last_tx = TX_RING_ENTRIES - 1;
+	ap->last_tx = ACE_TX_RING_ENTRIES(ap) - 1;
 	ap->last_std_rx = 0;
 	ap->last_mini_rx = 0;
 #endif
@@ -1428,6 +1462,9 @@
 	set_aceaddr(&info->rx_std_ctrl.rngptr, ap->rx_ring_base_dma);
 	info->rx_std_ctrl.max_len = ACE_STD_MTU + ETH_HLEN + 4;
 	info->rx_std_ctrl.flags = RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR;
+#if ACENIC_DO_VLAN
+	info->rx_std_ctrl.flags |= RCB_FLG_VLAN_ASSIST;
+#endif
 
 	memset(ap->rx_std_ring, 0,
 	       RX_STD_RING_ENTRIES * sizeof(struct rx_desc));
@@ -1443,6 +1480,9 @@
 		     (sizeof(struct rx_desc) * RX_STD_RING_ENTRIES)));
 	info->rx_jumbo_ctrl.max_len = 0;
 	info->rx_jumbo_ctrl.flags = RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR;
+#if ACENIC_DO_VLAN
+	info->rx_jumbo_ctrl.flags |= RCB_FLG_VLAN_ASSIST;
+#endif
 
 	memset(ap->rx_jumbo_ring, 0,
 	       RX_JUMBO_RING_ENTRIES * sizeof(struct rx_desc));
@@ -1465,6 +1505,9 @@
 		info->rx_mini_ctrl.max_len = ACE_MINI_SIZE;
 		info->rx_mini_ctrl.flags = 
 			RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR;
+#if ACENIC_DO_VLAN
+		info->rx_mini_ctrl.flags |= RCB_FLG_VLAN_ASSIST;
+#endif
 
 		for (i = 0; i < RX_MINI_RING_ENTRIES; i++)
 			ap->rx_mini_ring[i].flags =
@@ -1494,15 +1537,36 @@
 	*(ap->rx_ret_prd) = 0;
 
 	writel(TX_RING_BASE, &regs->WinBase);
-	memset(ap->tx_ring, 0, TX_RING_ENTRIES * sizeof(struct tx_desc));
 
-	set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
+	if (ACE_IS_TIGON_I(ap)) {
+		ap->tx_ring = (struct tx_desc *)regs->Window;
+		for (i = 0; i < (TIGON_I_TX_RING_ENTRIES * 
+				 sizeof(struct tx_desc) / 4); i++) {
+			writel(0, (unsigned long)ap->tx_ring + i * 4);
+		}
 
-	info->tx_ctrl.max_len = TX_RING_ENTRIES;
-	tmp = RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR|RCB_FLG_TX_HOST_RING;
+		set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE);
+	} else {
+		memset(ap->tx_ring, 0,
+		       MAX_TX_RING_ENTRIES * sizeof(struct tx_desc));
+
+		set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma);
+	}
+
+	info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap);
+	tmp = RCB_FLG_TCP_UDP_SUM|RCB_FLG_NO_PSEUDO_HDR;
+
+	/*
+	 * The Tigon I does not like having the TX ring in host memory ;-(
+	 */
+	if (!ACE_IS_TIGON_I(ap))
+		tmp |= RCB_FLG_TX_HOST_RING;
 #if TX_COAL_INTS_ONLY
 	tmp |= RCB_FLG_COAL_INT_ONLY;
 #endif
+#if ACENIC_DO_VLAN
+	tmp |= RCB_FLG_VLAN_ASSIST;
+#endif
 	info->tx_ctrl.flags = tmp;
 
 	set_aceaddr(&info->tx_csm_ptr, ap->tx_csm_dma);
@@ -1528,7 +1592,7 @@
 	ace_set_rxtx_parms(dev, 0);
 
 	if (board_idx == BOARD_IDX_OVERFLOW) {
-		printk(KERN_WARNING "%s: more than %i NICs detected, "
+		printk(KERN_WARNING "%s: more then %i NICs detected, "
 		       "ignoring module parameters!\n",
 		       dev->name, ACE_MAX_MOD_PARMS);
 	} else if (board_idx >= 0) {
@@ -2117,6 +2181,14 @@
 }
 
 
+#if ACENIC_DO_VLAN
+static int ace_vlan_rx(struct ace_private *ap, struct sk_buff *skb, u16 vlan_tag)
+{
+	return vlan_hwaccel_rx(skb, ap->vlgrp, vlan_tag);
+}
+#endif
+
+
 static void ace_rx_int(struct net_device *dev, u32 rxretprd, u32 rxretcsm)
 {
 	struct ace_private *ap = dev->priv;
@@ -2201,7 +2273,15 @@
 			skb->ip_summed = CHECKSUM_NONE;
 		}
 
-		netif_rx(skb);		/* send it up */
+		/* send it up */
+
+#if ACENIC_DO_VLAN
+		if (ap->vlgrp != NULL &&
+		    (bd_flags & BD_FLG_VLAN_TAG)) {
+			ace_vlan_rx(ap, skb, retdesc->vlan);
+		} else
+#endif
+			netif_rx(skb);
 
 		dev->last_rx = jiffies;
 		ap->stats.rx_packets++;
@@ -2260,7 +2340,7 @@
 			info->skb = NULL;
 		}
 
-		idx = (idx + 1) % TX_RING_ENTRIES;
+		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
 	} while (idx != txcsm);
 
 	if (netif_queue_stopped(dev))
@@ -2353,7 +2433,7 @@
 		 * update releases enough of space, otherwise we just
 		 * wait for device to make more work.
 		 */
-		if (!tx_ring_full(txcsm, ap->tx_prd))
+		if (!tx_ring_full(ap, txcsm, ap->tx_prd))
 			ace_tx_int(dev, txcsm, idx);
 	}
 
@@ -2425,6 +2505,37 @@
 }
 
 
+#if ACENIC_DO_VLAN
+static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
+{
+	struct ace_private *ap = dev->priv;
+	unsigned long flags;
+
+	save_flags(flags);
+	cli();
+
+	ap->vlgrp = grp;
+
+	restore_flags(flags);
+}
+
+
+static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
+{
+	struct ace_private *ap = dev->priv;
+	unsigned long flags;
+
+	save_flags(flags);
+	cli();
+
+	if (ap->vlgrp)
+		ap->vlgrp->vlan_devices[vid] = NULL;
+
+	restore_flags(flags);
+}
+#endif /* ACENIC_DO_VLAN */
+
+
 static int ace_open(struct net_device *dev)
 {
 	struct ace_private *ap;
@@ -2527,7 +2638,7 @@
 	save_flags(flags);
 	cli();
 
-	for (i = 0; i < TX_RING_ENTRIES; i++) {
+	for (i = 0; i < ACE_TX_RING_ENTRIES(ap); i++) {
 		struct sk_buff *skb;
 		dma_addr_t mapping;
 		struct tx_ring_info *info;
@@ -2537,7 +2648,13 @@
 		mapping = pci_unmap_addr(info, mapping);
 
 		if (mapping) {
-			memset(ap->tx_ring + i, 0, sizeof(struct tx_desc));
+			if (ACE_IS_TIGON_I(ap)) {
+				writel(0, &ap->tx_ring[i].addr.addrhi);
+				writel(0, &ap->tx_ring[i].addr.addrlo);
+				writel(0, &ap->tx_ring[i].flagsize);
+			} else
+				memset(ap->tx_ring + i, 0,
+				       sizeof(struct tx_desc));
 			pci_unmap_page(ap->pdev, mapping,
 				       pci_unmap_len(info, maplen),
 				       PCI_DMA_TODEVICE);
@@ -2562,6 +2679,7 @@
 	return 0;
 }
 
+
 static inline dma_addr_t
 ace_map_tx_skb(struct ace_private *ap, struct sk_buff *skb,
 	       struct sk_buff *tail, u32 idx)
@@ -2582,15 +2700,28 @@
 
 
 static inline void
-ace_load_tx_bd(struct tx_desc *desc, u64 addr, u32 flagsize)
+ace_load_tx_bd(struct ace_private *ap, struct tx_desc *desc, u64 addr,
+	       u32 flagsize, u32 vlan_tag)
 {
 #if !USE_TX_COAL_NOW
 	flagsize &= ~BD_FLG_COAL_NOW;
 #endif
 
-	desc->addr.addrhi = addr >> 32;
-	desc->addr.addrlo = addr;
-	desc->flagsize = flagsize;
+	if (!ACE_IS_TIGON_I(ap)) {
+		writel(addr >> 32, &desc->addr.addrhi);
+		writel(addr & 0xffffffff, &desc->addr.addrlo);
+		writel(flagsize, &desc->flagsize);
+#if ACENIC_DO_VLAN
+		writel(vlan_tag, &desc->vlanres);
+#endif
+	} else {
+		desc->addr.addrhi = addr >> 32;
+		desc->addr.addrlo = addr;
+		desc->flagsize = flagsize;
+#if ACENIC_DO_VLAN
+		desc->vlanres = vlan_tag;
+#endif
+	}
 }
 
 
@@ -2607,11 +2738,10 @@
 	if (early_stop_netif_stop_queue(dev))
  		return 1;
 
-
 restart:
 	idx = ap->tx_prd;
 
-	if (tx_ring_full(ap->tx_ret_csm, idx))
+	if (tx_ring_full(ap, ap->tx_ret_csm, idx))
 		goto overflow;
 
 #if MAX_SKB_FRAGS
@@ -2619,33 +2749,47 @@
 #endif
 	{
 		dma_addr_t mapping;
+		u32 vlan_tag = 0;
 
 		mapping = ace_map_tx_skb(ap, skb, skb, idx);
 		flagsize = (skb->len << 16) | (BD_FLG_END);
 		if (skb->ip_summed == CHECKSUM_HW)
 			flagsize |= BD_FLG_TCP_UDP_SUM;
+#if ACENIC_DO_VLAN
+		if (vlan_tx_tag_present(skb)) {
+			flagsize |= BD_FLG_VLAN_TAG;
+			vlan_tag = vlan_tx_tag_get(skb);
+		}
+#endif
 		desc = ap->tx_ring + idx;
-		idx = (idx + 1) % TX_RING_ENTRIES;
+		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
 
 		/* Look at ace_tx_int for explanations. */
-		if (tx_ring_full(ap->tx_ret_csm, idx))
+		if (tx_ring_full(ap, ap->tx_ret_csm, idx))
 			flagsize |= BD_FLG_COAL_NOW;
 
-		ace_load_tx_bd(desc, mapping, flagsize);
+		ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
 	}
 #if MAX_SKB_FRAGS
 	else {
 		dma_addr_t mapping;
+		u32 vlan_tag = 0;
 		int i, len = 0;
 
 		mapping = ace_map_tx_skb(ap, skb, NULL, idx);
 		flagsize = ((skb->len - skb->data_len) << 16);
 		if (skb->ip_summed == CHECKSUM_HW)
 			flagsize |= BD_FLG_TCP_UDP_SUM;
+#if ACENIC_DO_VLAN
+		if (vlan_tx_tag_present(skb)) {
+			flagsize |= BD_FLG_VLAN_TAG;
+			vlan_tag = vlan_tx_tag_get(skb);
+		}
+#endif
 
-		ace_load_tx_bd(ap->tx_ring + idx, mapping, flagsize);
+		ace_load_tx_bd(ap, ap->tx_ring + idx, mapping, flagsize, vlan_tag);
 
-		idx = (idx + 1) % TX_RING_ENTRIES;
+		idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
 
 		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 			skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
@@ -2662,11 +2806,11 @@
 			flagsize = (frag->size << 16);
 			if (skb->ip_summed == CHECKSUM_HW)
 				flagsize |= BD_FLG_TCP_UDP_SUM;
-			idx = (idx + 1) % TX_RING_ENTRIES;
+			idx = (idx + 1) % ACE_TX_RING_ENTRIES(ap);
 
 			if (i == skb_shinfo(skb)->nr_frags - 1) {
 				flagsize |= BD_FLG_END;
-				if (tx_ring_full(ap->tx_ret_csm, idx))
+				if (tx_ring_full(ap, ap->tx_ret_csm, idx))
 					flagsize |= BD_FLG_COAL_NOW;
 
 				/*
@@ -2679,7 +2823,7 @@
 			}
 			pci_unmap_addr_set(info, mapping, mapping);
 			pci_unmap_len_set(info, maplen, frag->size);
-			ace_load_tx_bd(desc, mapping, flagsize);
+			ace_load_tx_bd(ap, desc, mapping, flagsize, vlan_tag);
 		}
 	}
 #endif
@@ -2697,7 +2841,7 @@
 		 * serialized, this is the only situation we have to
 		 * re-test.
 		 */
-		if (!tx_ring_full(ap->tx_ret_csm, idx))
+		if (!tx_ring_full(ap, ap->tx_ret_csm, idx))
 			netif_wake_queue(dev);
 	}
 
@@ -2776,8 +2920,8 @@
 		return -EOPNOTSUPP;
 	if (copy_from_user(&ecmd, ifr->ifr_data, sizeof(ecmd)))
 		return -EFAULT;
-
-	if (ecmd.cmd == ETHTOOL_GSET) {
+	switch (ecmd.cmd) {
+	case ETHTOOL_GSET:
 		ecmd.supported =
 			(SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
 			 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
@@ -2825,7 +2969,8 @@
 		if(copy_to_user(ifr->ifr_data, &ecmd, sizeof(ecmd)))
 			return -EFAULT;
 		return 0;
-	} else if (ecmd.cmd == ETHTOOL_SSET) {
+
+	case ETHTOOL_SSET:
 		if(!capable(CAP_NET_ADMIN))
 			return -EPERM;
 
@@ -2882,7 +3027,24 @@
 			ace_issue_cmd(regs, &cmd);
 		}
 		return 0;
+
+	case ETHTOOL_GDRVINFO: {
+		struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO};
+		strncpy(info.driver, "acenic", sizeof(info.driver) - 1);
+		sprintf(info.fw_version, "%i.%i.%i", 
+			 tigonFwReleaseMajor, tigonFwReleaseMinor,
+			 tigonFwReleaseFix);
+		strncpy(info.version, version, sizeof(info.version) - 1);
+		if (ap && ap->pdev)
+			strcpy(info.bus_info, ap->pdev->slot_name);
+		if (copy_to_user(ifr->ifr_data, &info, sizeof(info)))
+			return -EFAULT;
+		return 0;
 	}
+	default:
+		break;
+	}
+	
 #endif
 
 	return -EOPNOTSUPP;
diff -Nru a/drivers/net/acenic.h b/drivers/net/acenic.h
--- a/drivers/net/acenic.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/acenic.h	Fri Mar 15 17:51:03 2002
@@ -417,7 +417,16 @@
 #define BD_FLG_TCP_UDP_SUM	0x01
 #define BD_FLG_IP_SUM		0x02
 #define BD_FLG_END		0x04
+#define BD_FLG_MORE		0x08
 #define BD_FLG_JUMBO		0x10
+#define BD_FLG_UCAST		0x20
+#define BD_FLG_MCAST		0x40
+#define BD_FLG_BCAST		0x60
+#define BD_FLG_TYP_MASK		0x60
+#define BD_FLG_IP_FRAG		0x80
+#define BD_FLG_IP_FRAG_END	0x100
+#define BD_FLG_VLAN_TAG		0x200
+#define BD_FLG_FRAME_ERROR	0x400
 #define BD_FLG_COAL_NOW		0x800
 #define BD_FLG_MINI		0x1000
 
@@ -437,11 +446,12 @@
 
 
 /*
- * TX ring
+ * TX ring - maximum TX ring entries for Tigon I's is 128
  */
-#define TX_RING_ENTRIES	256	
-#define TX_RING_SIZE	(TX_RING_ENTRIES * sizeof(struct tx_desc))
-#define TX_RING_BASE	0x3800
+#define MAX_TX_RING_ENTRIES	256
+#define TIGON_I_TX_RING_ENTRIES	128
+#define TX_RING_SIZE		(MAX_TX_RING_ENTRIES * sizeof(struct tx_desc))
+#define TX_RING_BASE		0x3800
 
 struct tx_desc{
         aceaddr	addr;
@@ -608,7 +618,7 @@
  */
 struct ace_skb
 {
-	struct tx_ring_info	tx_skbuff[TX_RING_ENTRIES];
+	struct tx_ring_info	tx_skbuff[MAX_TX_RING_ENTRIES];
 	struct ring_info	rx_std_skbuff[RX_STD_RING_ENTRIES];
 	struct ring_info	rx_mini_skbuff[RX_MINI_RING_ENTRIES];
 	struct ring_info	rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
@@ -632,6 +642,10 @@
 	struct ace_skb		*skb;
 	dma_addr_t		info_dma;	/* 32/64 bit */
 
+#if ACENIC_DO_VLAN
+	struct vlan_group	*vlgrp;
+#endif
+
 	int			version, link;
 	int			promisc, mcast_all;
 
@@ -642,6 +656,7 @@
 	u32			tx_prd;
 	volatile u32		tx_ret_csm;
 	struct timer_list	timer;
+	int			tx_ring_entries;
 
 	/*
 	 * RX elements
@@ -692,17 +707,17 @@
 
 #define TX_RESERVED	MAX_SKB_FRAGS
 
-static inline int tx_space (u32 csm, u32 prd)
+static inline int tx_space (struct ace_private *ap, u32 csm, u32 prd)
 {
-	return (csm - prd - 1) & (TX_RING_ENTRIES - 1);
+	return (csm - prd - 1) & (ACE_TX_RING_ENTRIES(ap) - 1);
 }
 
-#define tx_free(ap) 		tx_space((ap)->tx_ret_csm, (ap)->tx_prd)
+#define tx_free(ap) 		tx_space((ap)->tx_ret_csm, (ap)->tx_prd, ap)
 
 #if MAX_SKB_FRAGS
-#define tx_ring_full(csm, prd)	(tx_space(csm, prd) <= TX_RESERVED)
+#define tx_ring_full(ap, csm, prd)	(tx_space(ap, csm, prd) <= TX_RESERVED)
 #else
-#define tx_ring_full		0
+#define tx_ring_full			0
 #endif
 
 
@@ -711,7 +726,7 @@
 	u64 baddr = (u64) addr;
 	aa->addrlo = baddr & 0xffffffff;
 	aa->addrhi = baddr >> 32;
-	mb();
+	wmb();
 }
 
 
@@ -758,5 +773,9 @@
 static void ace_init_cleanup(struct net_device *dev);
 static struct net_device_stats *ace_get_stats(struct net_device *dev);
 static int read_eeprom_byte(struct net_device *dev, unsigned long offset);
+#if ACENIC_DO_VLAN
+static void ace_vlan_rx_register(struct net_device *dev, struct vlan_group *grp);
+static void ace_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid);
+#endif
 
 #endif /* _ACENIC_H_ */
diff -Nru a/drivers/net/at1700.c b/drivers/net/at1700.c
--- a/drivers/net/at1700.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/at1700.c	Fri Mar 15 17:51:02 2002
@@ -836,6 +836,7 @@
 			 i++, mclist = mclist->next)
 			set_bit(ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 26,
 					mc_filter);
+		outb(0x02, ioaddr + RX_MODE);	/* Use normal mode. */
 	}
 
 	save_flags(flags);
diff -Nru a/drivers/net/bmac.c b/drivers/net/bmac.c
--- a/drivers/net/bmac.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/bmac.c	Fri Mar 15 17:51:01 2002
@@ -17,6 +17,7 @@
 #include <linux/timer.h>
 #include <linux/proc_fs.h>
 #include <linux/init.h>
+#include <linux/crc32.h>
 #include <asm/prom.h>
 #include <asm/dbdma.h>
 #include <asm/io.h>
diff -Nru a/drivers/net/e100/e100.h b/drivers/net/e100/e100.h
--- a/drivers/net/e100/e100.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/e100/e100.h	Fri Mar 15 17:51:02 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
@@ -119,31 +118,16 @@
  *  defaults as considerably less data will be queued.
  */
 
-#define MAX_TCB        64	/* number of transmit control blocks */
-#define MAX_TBD        MAX_TCB
 #define TX_FRAME_CNT   8	/* consecutive transmit frames per interrupt */
 /* TX_FRAME_CNT must be less than MAX_TCB    */
-#define MAX_RFD      64
 
-#define E100_DEFAULT_TCB   MAX_TCB
+#define E100_DEFAULT_TCB   64
 #define E100_MIN_TCB       2*TX_FRAME_CNT + 3	/* make room for at least 2 interrupts */
-
-#ifdef __ia64__
- /* We can't use too many DMAble buffers on IA64 machines with >4 GB mem */
-#define E100_MAX_TCB       64
-#else
 #define E100_MAX_TCB       1024
-#endif /*  __ia64__ */
 
-#define E100_DEFAULT_RFD   MAX_RFD
+#define E100_DEFAULT_RFD   64
 #define E100_MIN_RFD       8
-
-#ifdef __ia64__
- /* We can't use too many DMAble buffers on IA64 machines with >4 GB mem */
-#define E100_MAX_RFD       64
-#else
 #define E100_MAX_RFD       1024
-#endif /*  __ia64__ */
 
 #define E100_DEFAULT_XSUM         true
 #define E100_DEFAULT_BER          ZLOCK_MAX_ERRORS
@@ -154,10 +138,6 @@
 
 #define TX_THRSHLD     8
 
-/* sleep time is at least 50 ms, in jiffies */
-#define SLEEP_TIME ((HZ / 20) + 1)
-#define CUS_TIMEOUT 1000
-
 /* IFS parameters */
 #define MIN_NUMBER_OF_TRANSMITS_100 1000
 #define MIN_NUMBER_OF_TRANSMITS_10  100
@@ -534,8 +514,6 @@
 
 #define RFD_POINTER(skb,bdp)      ((rfd_t *) (((unsigned char *)((skb)->data))-((bdp)->rfd_size)))
 #define SKB_RFD_STATUS(skb,bdp)   ((RFD_POINTER((skb),(bdp)))->rfd_header.cb_status)
-#define GET_SKB_DMA_ADDR(skb)		( *(dma_addr_t *)( (skb)->cb) )
-#define SET_SKB_DMA_ADDR(skb,dma_addr)	( *(dma_addr_t *)( (skb)->cb) = (dma_addr) )
 
 /* ====================================================================== */
 /*                              82557                                     */
@@ -766,6 +744,8 @@
 #define IPCB_INSERTVLAN_ENABLE 		BIT_1
 #define IPCB_IP_ACTIVATION_DEFAULT      IPCB_HARDWAREPARSING_ENABLE
 
+#define FOLD_CSUM(_XSUM)  ((((_XSUM << 16) | (_XSUM >> 16)) + _XSUM) >> 16)
+
 /* Transmit Buffer Descriptor (TBD)*/
 typedef struct _tbd_t {
 	u32 tbd_buf_addr;	/* Physical Transmit Buffer Address */
@@ -1008,6 +988,11 @@
 	u32 wolopts;
 	u16 ip_lbytes;
 #endif
+
+#ifdef CONFIG_PM
+	u32 pci_state[16];
+#endif
+
 };
 
 #define E100_AUTONEG        0
@@ -1029,5 +1014,18 @@
 				   u32 *st_result);
 extern unsigned char e100_get_link_state(struct e100_private *bdp);
 extern unsigned char e100_wait_scb(struct e100_private *bdp);
+
+#ifndef yield
+#define yield()					\
+        do {					\
+                current->policy |= SCHED_YIELD;	\
+                schedule();			\
+        } while (0)                                     
+#endif
+
+extern void e100_deisolate_driver(struct e100_private *bdp,
+				  u8 recover, u8 full_reset);
+extern unsigned char e100_hw_reset_recover(struct e100_private *bdp,
+					   u32 reset_cmd);
 
 #endif
diff -Nru a/drivers/net/e100/e100_config.c b/drivers/net/e100/e100_config.c
--- a/drivers/net/e100/e100_config.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/e100/e100_config.c	Fri Mar 15 17:51:02 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
diff -Nru a/drivers/net/e100/e100_config.h b/drivers/net/e100/e100_config.h
--- a/drivers/net/e100/e100_config.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/e100/e100_config.h	Fri Mar 15 17:51:01 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
diff -Nru a/drivers/net/e100/e100_eeprom.c b/drivers/net/e100/e100_eeprom.c
--- a/drivers/net/e100/e100_eeprom.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/e100/e100_eeprom.c	Fri Mar 15 17:51:02 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
@@ -69,6 +68,10 @@
 AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR 
 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+
+Portions (C) 2002 Red Hat, Inc. under the terms of the GNU GPL v2.
+
 *******************************************************************************/
 
 /**********************************************************************
@@ -134,7 +137,7 @@
 	u16 data = 0;
 	unsigned long expiration_time = jiffies + HZ / 100 + 1;
 
-	while (time_before(jiffies, expiration_time)) {
+	do {
 		// Get current value of General Control 2
 		data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
 
@@ -151,10 +154,12 @@
 			return true;
 		}
 
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(1);
-	}
-	return false;
+		if (time_before(jiffies, expiration_time))
+			yield();
+		else
+			return false;
+
+	} while (true);
 }
 
 //----------------------------------------------------------------------------------------
@@ -252,19 +257,12 @@
 // Returns: bits in an address for that size eeprom
 //----------------------------------------------------------------------------------------
 
-static u16
+static inline int
 eeprom_address_size(u16 size)
 {
-	switch (size) {
-	case 64:
-		return 6;
-	case 128:
-		return 7;
-	case 256:
-		return 8;
-	}
-
-	return 0;		//fix compiler warning or error!
+	int isize = size;
+	
+	return (ffs(isize) - 1);
 }
 
 //----------------------------------------------------------------------------------------
@@ -348,6 +346,7 @@
 			x |= EEDI;
 
 		writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
+		readw(&(adapter->scb->scb_status)); /* flush command to card */
 		udelay(EEPROM_STALL_TIME);
 		raise_clock(adapter, &x);
 		lower_clock(adapter, &x);
@@ -374,6 +373,7 @@
 {
 	*x = *x | EESK;
 	writew(*x, &CSR_EEPROM_CONTROL_FIELD(adapter));
+	readw(&(adapter->scb->scb_status)); /* flush command to card */
 	udelay(EEPROM_STALL_TIME);
 }
 
@@ -393,6 +393,7 @@
 {
 	*x = *x & ~EESK;
 	writew(*x, &CSR_EEPROM_CONTROL_FIELD(adapter));
+	readw(&(adapter->scb->scb_status)); /* flush command to card */
 	udelay(EEPROM_STALL_TIME);
 }
 
@@ -498,7 +499,7 @@
 	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
 	x &= ~(EEDI | EEDO | EESK);
 	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
-	wmb();
+	readw(&(adapter->scb->scb_status)); /* flush command to card */
 	udelay(EEPROM_STALL_TIME);
 	x |= EECS;
 	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
@@ -580,17 +581,16 @@
 
 	eeprom_stand_by(adapter);
 
-	while (time_before(jiffies, expiration_time)) {
+	do {
 		rmb();
 		x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
 		if (x & EEDO)
 			return true;
-
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(1);
-	}
-
-	return false;
+		if (time_before(jiffies, expiration_time))
+			yield();
+		else
+			return false;
+	} while (true);
 }
 
 //----------------------------------------------------------------------------------------
@@ -606,9 +606,10 @@
 	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
 	x &= ~(EECS | EESK);
 	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
-	wmb();
+	readw(&(adapter->scb->scb_status)); /* flush command to card */
 	udelay(EEPROM_STALL_TIME);
 	x |= EECS;
 	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
+	readw(&(adapter->scb->scb_status)); /* flush command to card */
 	udelay(EEPROM_STALL_TIME);
 }
diff -Nru a/drivers/net/e100/e100_main.c b/drivers/net/e100/e100_main.c
--- a/drivers/net/e100/e100_main.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/e100/e100_main.c	Fri Mar 15 17:51:03 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
@@ -69,6 +68,10 @@
 AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY OR 
 TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*******************************************************************************
+
+Portions (C) 2002 Red Hat, Inc. under the terms of the GNU GPL v2.
+
 *******************************************************************************/
 
 /**********************************************************************
@@ -122,7 +125,6 @@
 static void e100_get_speed_duplex_caps(struct e100_private *);
 static int e100_ethtool_get_settings(struct net_device *, struct ifreq *);
 static int e100_ethtool_set_settings(struct net_device *, struct ifreq *);
-static void e100_set_speed_duplex(struct e100_private *);
 
 #ifdef ETHTOOL_GDRVINFO
 static int e100_ethtool_get_drvinfo(struct net_device *, struct ifreq *);
@@ -163,7 +165,8 @@
 /* Global Data structures and variables */
 char e100_copyright[] __devinitdata = "Copyright (c) 2002 Intel Corporation";
 
-#define E100_VERSION  "2.0.20-pre1"
+#define E100_VERSION  "2.0.24-pre1"
+
 #define E100_FULL_DRIVER_NAME 	"Intel(R) PRO/100 Fast Ethernet Adapter - Loadable driver, ver "
 
 const char *e100_version = E100_VERSION;
@@ -171,13 +174,19 @@
 char *e100_short_driver_name = "e100";
 static int e100nics = 0;
 
+#ifdef CONFIG_PM
+static int e100_save_state(struct pci_dev *pcid, u32 state);
+static int e100_suspend(struct pci_dev *pcid, u32 state);
+static int e100_enable_wake(struct pci_dev *pcid, u32 state, int enable);
+static int e100_resume(struct pci_dev *pcid);
+#endif
+
 /*********************************************************************/
 /*! This is a GCC extension to ANSI C.
  *  See the item "Labeled Elements in Initializers" in the section
  *  "Extensions to the C Language Family" of the GCC documentation.
  *********************************************************************/
-
-#define E100_PARAM_INIT { [0 ... E100_MAX_NIC-1] = -1 }
+#define E100_PARAM_INIT { [0 ... E100_MAX_NIC] = -1 }
 
 /* All parameters are treated the same, as an integer array of values.
  * This macro just reduces the need to repeat the same declaration code
@@ -203,6 +212,7 @@
 static void e100intr(int, void *, struct pt_regs *);
 static void e100_print_brd_conf(struct e100_private *);
 static void e100_set_multi(struct net_device *);
+void e100_set_speed_duplex(struct e100_private *);
 
 char *e100_get_brand_msg(struct e100_private *);
 static u8 e100_pci_setup(struct pci_dev *, struct e100_private *);
@@ -517,6 +527,7 @@
 {
 	/* Disable interrupts on our PCI board by setting the mask bit */
 	writeb(SCB_INT_MASK, &bdp->scb->scb_cmd_hi);
+	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
 }
 
 /**
@@ -530,6 +541,7 @@
 e100_set_intr_mask(struct e100_private *bdp)
 {
 	writeb(bdp->intr_mask, &bdp->scb->scb_cmd_hi);
+	readw(&(bdp->scb->scb_status)); /* flushes last write, read-safe */
 }
 
 static inline void
@@ -537,6 +549,7 @@
 {
 	/* Trigger interrupt on our PCI board by asserting SWI bit */
 	writeb(SCB_SOFT_INT, &bdp->scb->scb_cmd_hi);
+	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
 }
 
 static int __devinit
@@ -728,8 +741,15 @@
 	}
 
 #ifdef ETHTOOL_GWOL
-	/* Set up wol options and enable PME */
-	e100_do_wol(pcid, bdp);
+	/* Set up wol options and enable PME if wol is enabled */
+	if (bdp->wolopts) {
+		e100_do_wol(pcid, bdp);
+		/* Enable PME for power state D3 */
+		pci_enable_wake(pcid, 3, 1);
+		/* Set power state to D1 in case driver is RELOADED */
+		/* If system powers down, device is switched from D1 to D3 */
+		pci_set_power_state(pcid, 1);
+	}
 #endif
 
 	e100_clear_structs(dev);
@@ -744,8 +764,15 @@
 	id_table:       e100_id_table,
 	probe:          e100_found1,
 	remove:         __devexit_p(e100_remove1),
+#ifdef CONFIG_PM
+	suspend:        e100_suspend,
+	resume:         e100_resume,
+	save_state:     e100_save_state,
+	enable_wake:    e100_enable_wake,
+#else
 	suspend:        NULL,
 	resume:         NULL,
+#endif
 };
 
 static int __init
@@ -774,79 +801,66 @@
 void __devinit
 e100_check_options(int board, struct e100_private *bdp)
 {
-	int val;
-
 	if (board >= E100_MAX_NIC) {
 		printk(KERN_NOTICE "No configuration available for board #%d\n",
 		       board);
 		printk(KERN_NOTICE "Using defaults for all values\n");
+		board = E100_MAX_NIC;
 	}
 
-	val = (board < E100_MAX_NIC) ? TxDescriptors[board] : -1;
-	e100_set_int_option(&(bdp->params.TxDescriptors), val, E100_MIN_TCB,
-			    E100_MAX_TCB, E100_DEFAULT_TCB,
+	e100_set_int_option(&(bdp->params.TxDescriptors), TxDescriptors[board],
+			    E100_MIN_TCB, E100_MAX_TCB, E100_DEFAULT_TCB,
 			    "TxDescriptor count");
 
-	val = (board < E100_MAX_NIC) ? RxDescriptors[board] : -1;
-	e100_set_int_option(&(bdp->params.RxDescriptors), val, E100_MIN_RFD,
-			    E100_MAX_RFD, E100_DEFAULT_RFD,
+	e100_set_int_option(&(bdp->params.RxDescriptors), RxDescriptors[board],
+			    E100_MIN_RFD, E100_MAX_RFD, E100_DEFAULT_RFD,
 			    "RxDescriptor count");
 
-	val = (board < E100_MAX_NIC) ? e100_speed_duplex[board] : -1;
-	e100_set_int_option(&(bdp->params.e100_speed_duplex), val, 0, 4,
+	e100_set_int_option(&(bdp->params.e100_speed_duplex),
+			    e100_speed_duplex[board], 0, 4,
 			    E100_DEFAULT_SPEED_DUPLEX, "speed/duplex mode");
 
-	val = (board < E100_MAX_NIC) ? ber[board] : -1;
-	e100_set_int_option(&(bdp->params.ber), val, 0, ZLOCK_MAX_ERRORS,
+	e100_set_int_option(&(bdp->params.ber), ber[board], 0, ZLOCK_MAX_ERRORS,
 			    E100_DEFAULT_BER, "Bit Error Rate count");
 
-	val = (board < E100_MAX_NIC) ? XsumRX[board] : -1;
-	e100_set_bool_option(bdp, val, PRM_XSUMRX, E100_DEFAULT_XSUM,
+	e100_set_bool_option(bdp, XsumRX[board], PRM_XSUMRX, E100_DEFAULT_XSUM,
 			     "XsumRX value");
 
 	/* Default ucode value depended on controller revision */
-	val = (board < E100_MAX_NIC) ? ucode[board] : -1;
 	if (bdp->rev_id >= D101MA_REV_ID) {
-		e100_set_bool_option(bdp, val, PRM_UCODE, E100_DEFAULT_UCODE,
-				     "ucode value");
+		e100_set_bool_option(bdp, ucode[board], PRM_UCODE,
+				     E100_DEFAULT_UCODE, "ucode value");
 	} else {
-		e100_set_bool_option(bdp, val, PRM_UCODE, false, "ucode value");
+		e100_set_bool_option(bdp, ucode[board], PRM_UCODE, false,
+				     "ucode value");
 	}
 
-	val = (board < E100_MAX_NIC) ? flow_control[board] : -1;
-	e100_set_bool_option(bdp, val, PRM_FC, E100_DEFAULT_FC,
+	e100_set_bool_option(bdp, flow_control[board], PRM_FC, E100_DEFAULT_FC,
 			     "flow control value");
 
-	val = (board < E100_MAX_NIC) ? IFS[board] : -1;
-	e100_set_bool_option(bdp, val, PRM_IFS, E100_DEFAULT_IFS, "IFS value");
+	e100_set_bool_option(bdp, IFS[board], PRM_IFS, E100_DEFAULT_IFS,
+			     "IFS value");
 
-	val = (board < E100_MAX_NIC) ? BundleSmallFr[board] : -1;
-	e100_set_bool_option(bdp, val, PRM_BUNDLE_SMALL,
+	e100_set_bool_option(bdp, BundleSmallFr[board], PRM_BUNDLE_SMALL,
 			     E100_DEFAULT_BUNDLE_SMALL_FR,
 			     "CPU saver bundle small frames value");
 
-	val = (board < E100_MAX_NIC) ? IntDelay[board] : -1;
-	e100_set_int_option(&(bdp->params.IntDelay), val, 0x0, 0xFFFF,
-			    E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY,
+	e100_set_int_option(&(bdp->params.IntDelay), IntDelay[board], 0x0,
+			    0xFFFF, E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY,
 			    "CPU saver interrupt delay value");
 
-	val = (board < E100_MAX_NIC) ? BundleMax[board] : -1;
-	e100_set_int_option(&(bdp->params.BundleMax), val, 0x1, 0xFFFF,
-			    E100_DEFAULT_CPUSAVER_BUNDLE_MAX,
+	e100_set_int_option(&(bdp->params.BundleMax), BundleMax[board], 0x1,
+			    0xFFFF, E100_DEFAULT_CPUSAVER_BUNDLE_MAX,
 			    "CPU saver bundle max value");
 
-	val = (board < E100_MAX_NIC) ? RxCongestionControl[board] : -1;
-	e100_set_bool_option(bdp, val, PRM_RX_CONG,
+	e100_set_bool_option(bdp, RxCongestionControl[board], PRM_RX_CONG,
 			     E100_DEFAULT_RX_CONGESTION_CONTROL,
 			     "Rx Congestion Control value");
 
-	val = (board < E100_MAX_NIC) ? PollingMaxWork[board] : -1;
-	e100_set_int_option(&(bdp->params.PollingMaxWork), val, 1, E100_MAX_RFD,
-			    RxDescriptors[board], "Polling Max Work value");
-
-	if (val <= 0) {
-		bdp->params.b_params &= ~PRM_RX_CONG;
-	}
+	e100_set_int_option(&(bdp->params.PollingMaxWork),
+			    PollingMaxWork[board], 1, E100_MAX_RFD,
+			    bdp->params.RxDescriptors,
+			    "Polling Max Work value");
 }
 
 /**
@@ -1194,7 +1208,7 @@
 	/* reconfigure the chip if something has changed in its config space */
 	e100_config(bdp);
 
-	if ((promisc_enbl) || (mulcast_enbl)) {
+	if (promisc_enbl || mulcast_enbl) {
 		goto exit;	/* no need for Multicast Cmd */
 	}
 
@@ -1996,8 +2010,9 @@
 		if (max_number_of_rfds && (rfd_cnt >= max_number_of_rfds)) {
 			break;
 		}
-		if (list_empty(&(bdp->active_rx_list)))
+		if (list_empty(&(bdp->active_rx_list))) {
 			break;
+		}
 
 		rx_struct = list_entry(bdp->active_rx_list.next,
 				       struct rx_list_elem, list_elem);
@@ -2030,10 +2045,8 @@
 				    (data_sz + bdp->rfd_size),
 				    PCI_DMA_FROMDEVICE);
 
-		// we unmap using DMA_TODEVICE to avoid another memcpy from the 
-		// bounce buffer
 		pci_unmap_single(bdp->pdev, rx_struct->dma_addr,
-				 sizeof (rfd_t), PCI_DMA_TODEVICE);
+				 sizeof (rfd_t), PCI_DMA_FROMDEVICE);
 
 		list_add(&(rx_struct->list_elem), &(bdp->rx_struct_pool));
 
@@ -2146,6 +2159,34 @@
 	}			/* end underrun check */
 }
 
+#ifdef E100_ZEROCOPY
+/**
+ * e100_pseudo_hdr_csum - compute IP pseudo-header checksum
+ * @ip: points to the header of the IP packet
+ *
+ * Return the 16 bit checksum of the IP pseudo-header.,which is computed
+ * on the fields: IP src, IP dst, next protocol, payload length.
+ * The checksum vaule is returned in network byte order.
+ */
+static inline u16
+e100_pseudo_hdr_csum(const struct iphdr *ip)
+{
+	u32 pseudo = 0;
+	u32 payload_len = 0;
+
+	payload_len = ntohs(ip->tot_len) - (ip->ihl * 4);
+
+	pseudo += htons(payload_len);
+	pseudo += (ip->protocol << 8);
+	pseudo += ip->saddr & 0x0000ffff;
+	pseudo += (ip->saddr & 0xffff0000) >> 16;
+	pseudo += ip->daddr & 0x0000ffff;
+	pseudo += (ip->daddr & 0xffff0000) >> 16;
+
+	return FOLD_CSUM(pseudo);
+}
+#endif /* E100_ZEROCOPY */
+
 /**
  * e100_prepare_xmit_buff - prepare a buffer for transmission
  * @bdp: atapter's private data struct
@@ -2166,6 +2207,12 @@
 	tcb = bdp->tcb_pool.data;
 	tcb += TCB_TO_USE(bdp->tcb_pool);
 
+	if (bdp->flags & USE_IPCB) {
+		tcb->tcbu.ipcb.ip_activation_high = IPCB_IP_ACTIVATION_DEFAULT;
+		tcb->tcbu.ipcb.ip_schedule &= ~IPCB_TCP_PACKET;
+		tcb->tcbu.ipcb.ip_schedule &= ~IPCB_TCPUDP_CHECKSUM_ENABLE;
+	}
+
 	tcb->tcb_hdr.cb_status = 0;
 	tcb->tcb_thrshld = bdp->tx_thld;
 	tcb->tcb_hdr.cb_cmd |= __constant_cpu_to_le16(CB_S_BIT);
@@ -2204,17 +2251,7 @@
 				chksum = &(udp->check);
 			}
 
-			*chksum = csum_tcpudp_magic(ip->daddr, ip->saddr,
-						    sizeof (struct tcphdr),
-						    ip->protocol, 0);
-		}
-	} else {
-		if (bdp->flags & USE_IPCB) {
-			tcb->tcbu.ipcb.ip_activation_high =
-				IPCB_IP_ACTIVATION_DEFAULT;
-			tcb->tcbu.ipcb.ip_schedule &= ~IPCB_TCP_PACKET;
-			tcb->tcbu.ipcb.ip_schedule &=
-				~IPCB_TCPUDP_CHECKSUM_ENABLE;
+			*chksum = e100_pseudo_hdr_csum(ip);
 		}
 	}
 
@@ -2319,9 +2356,8 @@
 		if (!e100_wait_cus_idle(bdp))
 			printk("%s cu_start: timeout waiting for cu\n",
 			       bdp->device->name);
-
 		if (!e100_wait_exec_cmplx(bdp, (u32) (tcb->tcb_phys),
-					 SCB_CUC_START)) {
+					  SCB_CUC_START)) {
 			printk("%s cu_start: timeout waiting for scb\n",
 			       bdp->device->name);
 			e100_exec_cmplx(bdp, (u32) (tcb->tcb_phys),
@@ -2378,6 +2414,7 @@
 
 	/* Do the port command */
 	writel(selftest_cmd, &bdp->scb->scb_port);
+	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
 
 	/* Wait at least 10 milliseconds for the self-test to complete */
 	set_current_state(TASK_UNINTERRUPTIBLE);
@@ -2386,8 +2423,6 @@
 	/* disable interrupts since the're now enabled */
 	e100_dis_intr(bdp);
 
-	rmb();
-
 	/* if The First Self Test DWORD Still Zero, We've timed out. If the
 	 * second DWORD is not zero then we have an error. */
 	if ((bdp->selftest->st_sign == 0) || (bdp->selftest->st_result != 0)) {
@@ -2670,7 +2705,7 @@
 	cb_header_t *ntcb_hdr;
 	unsigned long lock_flag;
 	unsigned long expiration_time;
-	unsigned char rc = false;
+	unsigned char rc = true;
 
 	ntcb_hdr = (cb_header_t *) command->non_tx_cmd;	/* get hdr of non tcb cmd */
 
@@ -2681,7 +2716,7 @@
 
 	wmb();
 
-	if (in_interrupt())
+	if (in_interrupt() || netif_running(bdp->device))
 		return e100_delayed_exec_non_cu_cmd(bdp, command);
 
 	spin_lock_bh(&(bdp->bd_non_tx_lock));
@@ -2705,28 +2740,30 @@
 
 	if (!e100_wait_exec_cmplx(bdp, command->dma_addr, SCB_CUC_START)) {
 		spin_unlock_irqrestore(&(bdp->bd_lock), lock_flag);
+		rc = false;
 		goto exit;
 	}
 
 	bdp->next_cu_cmd = START_WAIT;
 	spin_unlock_irqrestore(&(bdp->bd_lock), lock_flag);
 
-	/* now wait for completion of non-cu CB up to 20 msec*/
+	/* now wait for completion of non-cu CB up to 20 msec */
 	expiration_time = jiffies + HZ / 50 + 1;
-	while (time_before(jiffies, expiration_time)) {
-		rmb();
-		if ((ntcb_hdr->cb_status &
+	rmb();
+	while (!(ntcb_hdr->cb_status &
 		     __constant_cpu_to_le16(CB_STATUS_COMPLETE))) {
-			rc = true;
+
+		if (time_before(jiffies, expiration_time)) {
+			spin_unlock_bh(&(bdp->bd_non_tx_lock));
+			yield();
+			spin_lock_bh(&(bdp->bd_non_tx_lock));
+		} else {
+			rc = false;
 			goto exit;
 		}
-		spin_unlock_bh(&(bdp->bd_non_tx_lock));
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(1);
-		spin_lock_bh(&(bdp->bd_non_tx_lock));
+		rmb();
 	}
 
-	/* didn't get a C bit assume command failed */
 exit:
 	e100_free_non_tx_cmd(bdp, command);
 
@@ -2754,6 +2791,7 @@
 {
 	/* Do  a selective reset first to avoid a potential PCI hang */
 	writel(PORT_SELECTIVE_RESET, &bdp->scb->scb_port);
+	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
 
 	/* wait for the reset to take effect */
 	udelay(20);
@@ -3086,13 +3124,140 @@
 
 	del_timer_sync(&bdp->watchdog_timer);
 
-	netif_stop_queue(bdp->device);
+	if (netif_running(bdp->device))
+		netif_stop_queue(bdp->device);
 
 	bdp->last_tcb = NULL;
 
 	e100_sw_reset(bdp, PORT_SELECTIVE_RESET);
 }
 
+void
+e100_set_speed_duplex(struct e100_private *bdp)
+{
+	e100_phy_set_speed_duplex(bdp, true);
+	e100_config_fc(bdp);	/* re-config flow-control if necessary */
+	e100_config(bdp);	
+}
+
+static void
+e100_tcb_add_C_bit(struct e100_private *bdp)
+{
+	tcb_t *tcb = (tcb_t *) bdp->tcb_pool.data;
+	int i;
+
+	for (i = 0; i < bdp->params.TxDescriptors; i++, tcb++) {
+		tcb->tcb_hdr.cb_status |= cpu_to_le16(CB_STATUS_COMPLETE);
+	}
+}
+
+/* 
+ * Procedure:   e100_hw_reset_recover
+ *
+ * Description: This routine will recover the hw after reset.
+ *
+ * Arguments:
+ *      bdp - Ptr to this card's e100_bdconfig structure
+ *        reset_cmd - s/w reset or selective reset. 
+ *
+ * Returns:
+ *        true upon success
+ *        false upon failure
+ */
+unsigned char
+e100_hw_reset_recover(struct e100_private *bdp, u32 reset_cmd)
+{
+	bdp->last_tcb = NULL;
+	if (reset_cmd == PORT_SOFTWARE_RESET) {
+
+		/*load CU & RU base */
+		if (!e100_wait_exec_cmplx(bdp, 0, SCB_CUC_LOAD_BASE)) {
+			return false;
+		}
+
+		if (e100_load_microcode(bdp)) {
+			bdp->flags |= DF_UCODE_LOADED;
+		}
+
+		if (!e100_wait_exec_cmplx(bdp, 0, SCB_RUC_LOAD_BASE)) {
+			return false;
+		}
+
+		/* Issue the load dump counters address command */
+		if (!e100_wait_exec_cmplx(bdp, bdp->stat_cnt_phys,
+					  SCB_CUC_DUMP_ADDR)) {
+			return false;
+		}
+
+		if (!e100_setup_iaaddr(bdp, bdp->device->dev_addr)) {
+			printk(KERN_ERR
+			       "e100_hw_reset_recover: setup iaaddr failed\n");
+			return false;
+		}
+
+		e100_set_multi_exec(bdp->device);
+
+		/* Change for 82558 enhancement */
+		/* If 82558/9 and if the user has enabled flow control, set up * the
+		 * Flow Control Reg. in the CSR */
+		if ((bdp->flags & IS_BACHELOR)
+		    && (bdp->params.b_params & PRM_FC)) {
+			writeb(DFLT_FC_THLD,
+			       &bdp->scb->scb_ext.d101_scb.scb_fc_thld);
+			writeb(DFLT_FC_CMD,
+			       &bdp->scb->scb_ext.d101_scb.scb_fc_xon_xoff);
+		}
+
+	}
+
+	e100_force_config(bdp);
+
+	return true;
+}
+
+void
+e100_deisolate_driver(struct e100_private *bdp, u8 recover, u8 full_init)
+{
+	if (full_init) {
+		e100_sw_reset(bdp, PORT_SOFTWARE_RESET);
+		if (!e100_hw_reset_recover(bdp, PORT_SOFTWARE_RESET))
+			printk(KERN_ERR "e100_deisolate_driver:"
+			       " HW SOFTWARE reset recover failed\n");
+	}
+
+	if (recover) {
+
+		bdp->next_cu_cmd = START_WAIT;
+		bdp->last_tcb = NULL;
+
+		/* lets reset the chip */
+		if (!full_init) {
+			e100_sw_reset(bdp, PORT_SELECTIVE_RESET);
+
+			if (!e100_hw_reset_recover(bdp, PORT_SELECTIVE_RESET)) {
+				printk(KERN_ERR "e100_deisolate_driver:"
+				       " HW reset recover failed\n");
+			}
+		}
+		e100_start_ru(bdp);
+
+		/* relaunch watchdog timer in 2 sec */
+		mod_timer(&(bdp->watchdog_timer), jiffies + (2 * HZ));
+
+		// we must clear tcbs since we may have lost Tx intrrupt
+		// or have unsent frames on the tcb chain
+		e100_tcb_add_C_bit(bdp);
+		e100_tx_srv(bdp);
+
+		e100_set_intr_mask(bdp);
+
+		if (netif_running(bdp->device))
+			netif_wake_queue(bdp->device);
+	}
+
+	bdp->driver_isolated = false;
+}
+
 #ifdef E100_ETHTOOL_IOCTL
 static int
 e100_do_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr)
@@ -3458,14 +3623,6 @@
 
 }
 
-static void
-e100_set_speed_duplex(struct e100_private *bdp)
-{
-	e100_phy_set_speed_duplex(bdp, true);
-	e100_config_fc(bdp);	/* re-config flow-control if necessary */
-	e100_config(bdp);	
-}
-
 #ifdef ETHTOOL_GWOL
 static unsigned char
 e100_setup_filter(struct e100_private *bdp)
@@ -3510,32 +3667,19 @@
 static void
 e100_do_wol(struct pci_dev *pcid, struct e100_private *bdp)
 {
-	int enable = 0;
-	u32 state = 0;
-
-	if (bdp->wolopts) {
-		e100_config_wol(bdp);
-
-		if (!e100_config(bdp)) {
-			printk("e100_config WOL options failed\n");
-			goto exit;
-		}
+	e100_config_wol(bdp);
 
-		if (bdp->wolopts & (WAKE_UCAST | WAKE_ARP)) {
-			if (!e100_setup_filter(bdp)) {
-				printk("e100_config WOL options failed\n");
-				goto exit;
-			}
-			state = 1;
-			pci_set_power_state(pcid, state);
-		}
-		enable = 1;
+	if (e100_config(bdp)) {
+		if (bdp->wolopts & (WAKE_UCAST | WAKE_ARP))
+			if (!e100_setup_filter(bdp))
+				printk(KERN_ERR
+				       "e100_config WOL options failed\n");
+	} else {
+		printk(KERN_ERR "e100_config WOL failed\n");
 	}
-exit:
-	 pci_enable_wake(pcid, state, enable);
 }
 
-static u16 
+static u16
 e100_get_ip_lbytes(struct net_device *dev)
 {
 	struct in_ifaddr *ifa;
@@ -3795,3 +3939,84 @@
 	}
 	spin_unlock_bh(&(bdp->bd_non_tx_lock));
 }
+
+#ifdef CONFIG_PM
+static int
+e100_save_state(struct pci_dev *pcid, u32 state)
+{
+	struct net_device *dev;
+	struct e100_private *bdp;
+
+	/* Actually, PCI PM does NOT call this entry */
+	if (!(dev = (struct net_device *) pci_get_drvdata(pcid)))
+		return -1;
+	bdp = dev->priv;
+	pci_save_state(pcid, bdp->pci_state);
+	return 0;
+}
+
+static int
+e100_suspend(struct pci_dev *pcid, u32 state)
+{
+	struct net_device *netdev = pci_get_drvdata(pcid);
+	struct e100_private *bdp = netdev->priv;
+
+	e100_isolate_driver(bdp);
+	e100_save_state(pcid, state);
+
+	/* If wol is enabled */
+#ifdef ETHTOOL_GWOL
+	if (bdp->wolopts) {
+		bdp->ip_lbytes = e100_get_ip_lbytes(netdev);
+		e100_do_wol(pcid, bdp);
+		pci_enable_wake(pcid, 3, 1);	/* Enable PME for power state D3 */
+		pci_set_power_state(pcid, 3);	/* Set power state to D3.        */
+	} else {
+		/* Disable bus mastering */
+		pci_disable_device(pcid);
+		pci_set_power_state(pcid, state);
+	}
+#else
+	pci_disable_device(pcid);
+	pci_set_power_state(pcid, state);
+#endif
+
+	return 0;
+}
+
+static int
+e100_resume(struct pci_dev *pcid)
+{
+	struct net_device *netdev = pci_get_drvdata(pcid);
+	struct e100_private *bdp = netdev->priv;
+	u8 recover = false;
+	u8 full_init = false;
+
+	pci_set_power_state(pcid, 0);
+	pci_enable_wake(pcid, 0, 0);	/* Clear PME status and disable PME */
+	pci_restore_state(pcid, bdp->pci_state);
+
+	if (netif_running(netdev)) {
+		recover = true;
+	}
+
+#ifdef ETHTOOL_GWOL
+	if (bdp->wolopts & (WAKE_UCAST | WAKE_ARP)) {
+		full_init = true;
+	}
+#endif
+
+	e100_deisolate_driver(bdp, recover, full_init);
+
+	return 0;
+}
+
+static int
+e100_enable_wake(struct pci_dev *pcid, u32 state, int enable)
+{
+	/* Driver doesn't need to do anything because it will enable */
+	/* wol when suspended.                                       */
+	/* Actually, PCI PM does NOT call this entry.                */
+	return 0;
+}
+#endif /* CONFIG_PM */
diff -Nru a/drivers/net/e100/e100_phy.c b/drivers/net/e100/e100_phy.c
--- a/drivers/net/e100/e100_phy.c	Fri Mar 15 17:51:00 2002
+++ b/drivers/net/e100/e100_phy.c	Fri Mar 15 17:51:00 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
@@ -654,7 +653,7 @@
 e100_force_speed_duplex(struct e100_private *bdp)
 {
 	u16 control;
-	int neg_timeout = 2 * HZ;	//2 sec in jiffies
+	unsigned long expires;
 
 	bdp->flags |= DF_SPEED_FORCED;
 
@@ -697,20 +696,18 @@
 	e100_mdi_write(bdp, MII_BMCR, bdp->phy_addr, control);
 
 	/* loop must run at least once */
+	expires = jiffies + 2 * HZ;
 	do {
-		spin_unlock_bh(&(bdp->mdi_access_lock));
-
-		set_current_state(TASK_UNINTERRUPTIBLE);
-		schedule_timeout(SLEEP_TIME);
-
-		spin_lock_bh(&(bdp->mdi_access_lock));
-
-		if (e100_update_link_state(bdp)) {
+		if (e100_update_link_state(bdp) || 
+		    time_after(jiffies, expires)) {
 			break;
+		} else {
+			spin_unlock_bh(&(bdp->mdi_access_lock));
+			yield();
+			spin_lock_bh(&(bdp->mdi_access_lock));
 		}
-		neg_timeout -= SLEEP_TIME;
 
-	} while (neg_timeout > 0);
+	} while (true);
 
 	spin_unlock_bh(&(bdp->mdi_access_lock));
 }
@@ -769,7 +766,7 @@
  * Arguments:  bdp - Pointer to the e100_private structure for the board
  *
  * Returns: true if link state was changed
- *	    B_FLASE otherwise
+ *	   false otherwise
  *
  */
 unsigned char
@@ -820,7 +817,7 @@
 e100_auto_neg(struct e100_private *bdp, unsigned char force_restart)
 {
 	u16 stat_reg;
-	unsigned int i;
+	unsigned long expires;
 
 	bdp->flags &= ~DF_SPEED_FORCED;
 
@@ -841,22 +838,21 @@
 			       BMCR_ANENABLE | BMCR_ANRESTART);
 
 		/* wait for autoneg to complete (up to 3 seconds) */
-		for (i = 0; i < 60; i++) {
+		expires = jiffies + HZ * 3;
+		do {
 			/* now re-read the value. Sticky so read twice */
 			e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
 			e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &stat_reg);
 
-			if (stat_reg & BMSR_ANEGCOMPLETE)
+			if ((stat_reg & BMSR_ANEGCOMPLETE) ||
+			    time_after(jiffies, expires) ) {
 				goto exit;
-
-			spin_unlock_bh(&(bdp->mdi_access_lock));
-
-			set_current_state(TASK_UNINTERRUPTIBLE);
-			schedule_timeout(SLEEP_TIME);
-
-			spin_lock_bh(&(bdp->mdi_access_lock));
-
-		}
+			} else {
+				spin_unlock_bh(&(bdp->mdi_access_lock));
+				yield();
+				spin_lock_bh(&(bdp->mdi_access_lock));
+			}
+		} while (true);
 	}
 
 exit:
diff -Nru a/drivers/net/e100/e100_phy.h b/drivers/net/e100/e100_phy.h
--- a/drivers/net/e100/e100_phy.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/e100/e100_phy.h	Fri Mar 15 17:51:01 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
diff -Nru a/drivers/net/e100/e100_proc.c b/drivers/net/e100/e100_proc.c
--- a/drivers/net/e100/e100_proc.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/e100/e100_proc.c	Fri Mar 15 17:51:02 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
@@ -98,7 +97,8 @@
 
 #ifdef E100_CONFIG_PROC_FS
 #include "e100.h"
-
+/* MDI sleep time is at least 50 ms, in jiffies */
+#define MDI_SLEEP_TIME ((HZ / 20) + 1)
 /***************************************************************************/
 /*       /proc File System Interaface Support Functions                    */
 /***************************************************************************/
@@ -231,7 +231,7 @@
 	spin_unlock_bh(&bdp->mdi_access_lock);
 
 	set_current_state(TASK_UNINTERRUPTIBLE);
-	schedule_timeout(SLEEP_TIME);
+	schedule_timeout(MDI_SLEEP_TIME);
 
 	spin_lock_bh(&bdp->mdi_access_lock);
 
diff -Nru a/drivers/net/e100/e100_ucode.h b/drivers/net/e100/e100_ucode.h
--- a/drivers/net/e100/e100_ucode.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/e100/e100_ucode.h	Fri Mar 15 17:51:03 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
diff -Nru a/drivers/net/e100/e100_vendor.h b/drivers/net/e100/e100_vendor.h
--- a/drivers/net/e100/e100_vendor.h	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/e100/e100_vendor.h	Fri Mar 15 17:51:02 2002
@@ -2,9 +2,8 @@
 
 This software program is available to you under a choice of one of two 
 licenses. You may choose to be licensed under either the GNU General Public 
-License (GPL) Version 2, June 1991, available at 
-http://www.fsf.org/copyleft/gpl.html, or the Intel BSD + Patent License, the 
-text of which follows:
+License 2.0, June 1991, available at http://www.fsf.org/copyleft/gpl.html, 
+or the Intel BSD + Patent License, the text of which follows:
 
 Recipient has requested a license and Intel Corporation ("Intel") is willing
 to grant a license for the software entitled Linux Base Driver for the 
@@ -18,7 +17,7 @@
 "Recipient" means the party to whom Intel delivers this Software.
 
 "Licensee" means Recipient and those third parties that receive a license to 
-any operating system available under the GNU Public License version 2.0 or 
+any operating system available under the GNU General Public License 2.0 or 
 later.
 
 Copyright (c) 1999 - 2002 Intel Corporation.
@@ -51,10 +50,10 @@
 version of an operating system that has been distributed under the GNU 
 General Public License 2.0 or later. This patent license shall apply to the 
 combination of the Software and any operating system licensed under the GNU 
-Public License version 2.0 or later if, at the time Intel provides the 
+General Public License 2.0 or later if, at the time Intel provides the 
 Software to Recipient, such addition of the Software to the then publicly 
-available versions of such operating systems available under the GNU Public 
-License version 2.0 or later (whether in gold, beta or alpha form) causes 
+available versions of such operating systems available under the GNU General 
+Public License 2.0 or later (whether in gold, beta or alpha form) causes 
 such combination to be covered by the Licensed Patents. The patent license 
 shall not apply to any other combinations which include the Software. NO 
 hardware per se is licensed hereunder.
diff -Nru a/drivers/net/e1000/e1000_main.c b/drivers/net/e1000/e1000_main.c
--- a/drivers/net/e1000/e1000_main.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/e1000/e1000_main.c	Fri Mar 15 17:51:02 2002
@@ -183,7 +183,7 @@
 	name:     e1000_driver_name,
 	id_table: e1000_pci_tbl,
 	probe:    e1000_probe,
-	remove:   e1000_remove,
+	remove:   __devexit_p(e1000_remove),
 	/* Power Managment Hooks */
 	suspend:  NULL,
 	resume:   NULL
diff -Nru a/drivers/net/eepro100.c b/drivers/net/eepro100.c
--- a/drivers/net/eepro100.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/eepro100.c	Fri Mar 15 17:51:01 2002
@@ -64,8 +64,8 @@
 
 /* A few values that may be tweaked. */
 /* The ring sizes should be a power of two for efficiency. */
-#define TX_RING_SIZE	32
-#define RX_RING_SIZE	32
+#define TX_RING_SIZE	64
+#define RX_RING_SIZE	64
 /* How much slots multicast filter setup may take.
    Do not descrease without changing set_rx_mode() implementaion. */
 #define TX_MULTICAST_SIZE   2
@@ -114,7 +114,6 @@
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
 #include <linux/ethtool.h>
-#include <linux/delay.h>
 
 MODULE_AUTHOR("Maintainer: Andrey V. Savochkin <saw@saw.sw.com.sg>");
 MODULE_DESCRIPTION("Intel i82557/i82558/i82559 PCI EtherExpressPro driver");
@@ -570,6 +569,19 @@
 	if (speedo_debug > 0  &&  did_version++ == 0)
 		printk(version);
 
+	/* save power state before pci_enable_device overwrites it */
+	pm = pci_find_capability(pdev, PCI_CAP_ID_PM);
+	if (pm) {
+		u16 pwr_command;
+		pci_read_config_word(pdev, pm + PCI_PM_CTRL, &pwr_command);
+		acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
+	}
+
+	if (pci_enable_device(pdev))
+		goto err_out_free_mmio_region;
+
+	pci_set_master(pdev);
+
 	if (!request_region(pci_resource_start(pdev, 1),
 			pci_resource_len(pdev, 1), "eepro100")) {
 		printk (KERN_ERR "eepro100: cannot reserve I/O ports\n");
@@ -600,18 +612,6 @@
 			   pci_resource_start(pdev, 0), irq);
 #endif
 
-	/* save power state b4 pci_enable_device overwrites it */
-	pm = pci_find_capability(pdev, PCI_CAP_ID_PM);
-	if (pm) {
-		u16 pwr_command;
-		pci_read_config_word(pdev, pm + PCI_PM_CTRL, &pwr_command);
-		acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
-	}
-
-	if (pci_enable_device(pdev))
-		goto err_out_free_mmio_region;
-
-	pci_set_master(pdev);
 
 	if (speedo_found1(pdev, ioaddr, cards_found, acpi_idle_state) == 0)
 		cards_found++;
@@ -1074,6 +1074,51 @@
 	outw(CUStart | SCBMaskEarlyRx | SCBMaskFlowCtl, ioaddr + SCBCmd);
 }
 
+/*
+ * Sometimes the receiver stops making progress.  This routine knows how to
+ * get it going again, without losing packets or being otherwise nasty like
+ * a chip reset would be.  Previously the driver had a whole sequence
+ * of if RxSuspended, if it's no buffers do one thing, if it's no resources,
+ * do another, etc.  But those things don't really matter.  Separate logic
+ * in the ISR provides for allocating buffers--the other half of operation
+ * is just making sure the receiver is active.  speedo_rx_soft_reset does that.
+ * This problem with the old, more involved algorithm is shown up under
+ * ping floods on the order of 60K packets/second on a 100Mbps fdx network.
+ */
+static void
+speedo_rx_soft_reset(struct net_device *dev)
+{
+	struct speedo_private *sp = dev->priv;
+	struct RxFD *rfd;
+	long ioaddr;
+
+	ioaddr = dev->base_addr;
+	wait_for_cmd_done(ioaddr + SCBCmd);
+	if (inb(ioaddr + SCBCmd) != 0) {
+		printk("%s: previous command stalled\n", dev->name);
+		return;
+	}
+	/*
+	* Put the hardware into a known state.
+	*/
+	outb(RxAbort, ioaddr + SCBCmd);
+
+	rfd = sp->rx_ringp[sp->cur_rx % RX_RING_SIZE];
+
+	rfd->rx_buf_addr = 0xffffffff;
+
+	wait_for_cmd_done(ioaddr + SCBCmd);
+
+	if (inb(ioaddr + SCBCmd) != 0) {
+		printk("%s: RxAbort command stalled\n", dev->name);
+		return;
+	}
+	outl(sp->rx_ring_dma[sp->cur_rx % RX_RING_SIZE],
+		ioaddr + SCBPointer);
+	outb(RxStart, ioaddr + SCBCmd);
+}
+
+
 /* Media monitoring and control. */
 static void speedo_timer(unsigned long data)
 {
@@ -1377,9 +1422,10 @@
 
 	/* workaround for hardware bug on 10 mbit half duplex */
 
-	if ((sp->partner == 0) || (sp->chip_id == 1)) {
+	if ((sp->partner == 0) && (sp->chip_id == 1)) {
 		wait_for_cmd_done(ioaddr + SCBCmd);
 		outb(0 , ioaddr + SCBCmd);
+		udelay(1);
 	}
 
 	/* Trigger the command unit resume. */
@@ -1507,82 +1553,39 @@
 		if ((status & 0xfc00) == 0)
 			break;
 
-		/* Always check if all rx buffers are allocated.  --SAW */
-		speedo_refill_rx_buffers(dev, 0);
 
 		if ((status & 0x5000) ||	/* Packet received, or Rx error. */
 			(sp->rx_ring_state&(RrNoMem|RrPostponed)) == RrPostponed)
 									/* Need to gather the postponed packet. */
 			speedo_rx(dev);
 
-		if (status & 0x1000) {
-			spin_lock(&sp->lock);
-			if ((status & 0x003c) == 0x0028) {		/* No more Rx buffers. */
-				struct RxFD *rxf;
-				printk(KERN_WARNING "%s: card reports no RX buffers.\n",
-						dev->name);
-				rxf = sp->rx_ringp[sp->cur_rx % RX_RING_SIZE];
-				if (rxf == NULL) {
-					if (speedo_debug > 2)
-						printk(KERN_DEBUG
-								"%s: NULL cur_rx in speedo_interrupt().\n",
-								dev->name);
-					sp->rx_ring_state |= RrNoMem|RrNoResources;
-				} else if (rxf == sp->last_rxf) {
-					if (speedo_debug > 2)
-						printk(KERN_DEBUG
-								"%s: cur_rx is last in speedo_interrupt().\n",
-								dev->name);
-					sp->rx_ring_state |= RrNoMem|RrNoResources;
-				} else
-					outb(RxResumeNoResources, ioaddr + SCBCmd);
-			} else if ((status & 0x003c) == 0x0008) { /* No resources. */
-				struct RxFD *rxf;
-				printk(KERN_WARNING "%s: card reports no resources.\n",
-						dev->name);
-				rxf = sp->rx_ringp[sp->cur_rx % RX_RING_SIZE];
-				if (rxf == NULL) {
-					if (speedo_debug > 2)
-						printk(KERN_DEBUG
-								"%s: NULL cur_rx in speedo_interrupt().\n",
-								dev->name);
-					sp->rx_ring_state |= RrNoMem|RrNoResources;
-				} else if (rxf == sp->last_rxf) {
-					if (speedo_debug > 2)
-						printk(KERN_DEBUG
-								"%s: cur_rx is last in speedo_interrupt().\n",
-								dev->name);
-					sp->rx_ring_state |= RrNoMem|RrNoResources;
-				} else {
-					/* Restart the receiver. */
-					outl(sp->rx_ring_dma[sp->cur_rx % RX_RING_SIZE],
-						 ioaddr + SCBPointer);
-					outb(RxStart, ioaddr + SCBCmd);
-				}
-			}
-			sp->stats.rx_errors++;
-			spin_unlock(&sp->lock);
-		}
-
-		if ((sp->rx_ring_state&(RrNoMem|RrNoResources)) == RrNoResources) {
-			printk(KERN_WARNING
-					"%s: restart the receiver after a possible hang.\n",
-					dev->name);
-			spin_lock(&sp->lock);
-			/* Restart the receiver.
-			   I'm not sure if it's always right to restart the receiver
-			   here but I don't know another way to prevent receiver hangs.
-			   1999/12/25 SAW */
-			outl(sp->rx_ring_dma[sp->cur_rx % RX_RING_SIZE],
-				 ioaddr + SCBPointer);
-			outb(RxStart, ioaddr + SCBCmd);
-			sp->rx_ring_state &= ~RrNoResources;
-			spin_unlock(&sp->lock);
+		/* Always check if all rx buffers are allocated.  --SAW */
+		speedo_refill_rx_buffers(dev, 0);
+		
+		spin_lock(&sp->lock);
+		/*
+		 * The chip may have suspended reception for various reasons.
+		 * Check for that, and re-prime it should this be the case.
+		 */
+		switch ((status >> 2) & 0xf) {
+		case 0: /* Idle */
+			break;
+		case 1:	/* Suspended */
+		case 2:	/* No resources (RxFDs) */
+		case 9:	/* Suspended with no more RBDs */
+		case 10: /* No resources due to no RBDs */
+		case 12: /* Ready with no RBDs */
+			speedo_rx_soft_reset(dev);
+			break;
+		case 3:  case 5:  case 6:  case 7:  case 8:
+		case 11:  case 13:  case 14:  case 15:
+			/* these are all reserved values */
+			break;
 		}
-
+		
+		
 		/* User interrupt, Command/Tx unit interrupt or CU not active. */
 		if (status & 0xA400) {
-			spin_lock(&sp->lock);
 			speedo_tx_buffer_gc(dev);
 			if (sp->tx_full
 				&& (int)(sp->cur_tx - sp->dirty_tx) < TX_QUEUE_UNFULL) {
@@ -1590,8 +1593,9 @@
 				sp->tx_full = 0;
 				netif_wake_queue(dev); /* Attention: under a spinlock.  --SAW */
 			}
-			spin_unlock(&sp->lock);
 		}
+		
+		spin_unlock(&sp->lock);
 
 		if (--boguscnt < 0) {
 			printk(KERN_ERR "%s: Too much work at interrupt, status=0x%4.4x.\n",
@@ -2202,6 +2206,8 @@
 
 	if (!netif_running(dev))
 		return 0;
+		
+	del_timer_sync(&sp->timer);
 
 	netif_device_detach(dev);
 	outl(PortPartialReset, ioaddr + SCBPort);
@@ -2234,6 +2240,8 @@
 	sp->rx_mode = -1;
 	sp->flow_ctrl = sp->partner = 0;
 	set_rx_mode(dev);
+	sp->timer.expires = RUN_AT(2*HZ);
+	add_timer(&sp->timer);
 	return 0;
 }
 #endif /* CONFIG_PM */
diff -Nru a/drivers/net/hp100.c b/drivers/net/hp100.c
--- a/drivers/net/hp100.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/hp100.c	Fri Mar 15 17:51:02 2002
@@ -83,8 +83,6 @@
 **
 */
 
-#error Please convert me to Documentation/DMA-mapping.txt
-
 #define HP100_DEFAULT_PRIORITY_TX 0
 
 #undef HP100_DEBUG
@@ -212,8 +210,8 @@
 	hp100_ring_t rxring[MAX_RX_PDL];
 	hp100_ring_t txring[MAX_TX_PDL];
 
-	u_int *page_vaddr;	/* Virtual address of allocated page */
 	u_int *page_vaddr_algn;	/* Aligned virtual address of allocated page */
+	u_long whatever_offset;	/* Offset to bus/phys/dma address */
 	int rxrcommit;		/* # Rx PDLs commited to adapter */
 	int txrcommit;		/* # Tx PDLs commited to adapter */
 };
@@ -350,6 +348,18 @@
 static void hp100_RegisterDump(struct net_device *dev);
 #endif
 
+/* Conversion to new PCI API :
+ * Convert an address in a kernel buffer to a bus/phys/dma address.
+ * This work *only* for memory fragments part of lp->page_vaddr,
+ * because it was properly DMA allocated via pci_alloc_consistent(),
+ * so we just need to "retreive" the original mapping to bus/phys/dma
+ * address - Jean II */
+static inline dma_addr_t virt_to_whatever(struct net_device *dev, u32 * ptr)
+{
+  return ((u_long) ptr) +
+    ((struct hp100_private *) (dev->priv))->whatever_offset;
+}
+
 /* TODO: This function should not really be needed in a good design... */
 static void wait(void)
 {
@@ -627,9 +637,20 @@
 			local_mode = 3;
 		} else if (chip == HP100_CHIPID_LASSEN &&
 			   (lsw & (HP100_BM_WRITE | HP100_BM_READ)) == (HP100_BM_WRITE | HP100_BM_READ)) {
+			/* Conversion to new PCI API :
+			 * I don't have the doc, but I assume that the card
+			 * can map the full 32bit address space.
+			 * Also, we can have EISA Busmaster cards (not tested),
+			 * so beware !!! - Jean II */
+			if((bus == HP100_BUS_PCI) &&
+			   (pci_set_dma_mask(pci_dev, 0xffffffff))) {
+				/* Gracefully fallback to shared memory */
+				goto busmasterfail;
+			}
 			printk("hp100: %s: Busmaster mode enabled.\n", dev->name);
 			hp100_outw(HP100_MEM_EN | HP100_IO_EN | HP100_RESET_LB, OPTION_LSW);
 		} else {
+		busmasterfail:
 #ifdef HP100_DEBUG
 			printk("hp100: %s: Card not configured for BM or BM not supported with this card.\n", dev->name);
 			printk("hp100: %s: Trying shared memory mode.\n", dev->name);
@@ -772,11 +793,14 @@
 	 * in the cards shared memory area. But currently, busmaster has been
 	 * implemented/tested only with the lassen chip anyway... */
 	if (lp->mode == 1) {	/* busmaster */
+		dma_addr_t page_baddr;
 		/* Get physically continous memory for TX & RX PDLs    */
-		if ((lp->page_vaddr = kmalloc(MAX_RINGSIZE + 0x0f, GFP_KERNEL)) == NULL)
+		/* Conversion to new PCI API :
+		 * Pages are always aligned and zeroed, no need to it ourself.
+		 * Doc says should be OK for EISA bus as well - Jean II */
+		if ((lp->page_vaddr_algn = pci_alloc_consistent(lp->pci_dev, MAX_RINGSIZE, &page_baddr)) == NULL)
 			return -ENOMEM;
-		lp->page_vaddr_algn = ((u_int *) (((u_int) (lp->page_vaddr) + 0x0f) & ~0x0f));
-		memset(lp->page_vaddr, 0, MAX_RINGSIZE + 0x0f);
+		lp->whatever_offset = ((u_long) page_baddr) - ((u_long) lp->page_vaddr_algn);
 
 #ifdef HP100_DEBUG_BM
 		printk("hp100: %s: Reserved DMA memory from 0x%x to 0x%x\n", dev->name, (u_int) lp->page_vaddr_algn, (u_int) lp->page_vaddr_algn + MAX_RINGSIZE);
@@ -1189,7 +1213,7 @@
 {
 	struct hp100_private *lp = (struct hp100_private *) dev->priv;
 	hp100_ring_t *ringptr;
-	u_int *pageptr;
+	u_int *pageptr;		/* Warning : increment by 4 - Jean II */
 	int i;
 
 #ifdef HP100_DEBUG_B
@@ -1246,7 +1270,7 @@
 		       dev->name, (unsigned) pdlptr);
 
 	ringptr->pdl = pdlptr + 1;
-	ringptr->pdl_paddr = virt_to_bus(pdlptr + 1);
+	ringptr->pdl_paddr = virt_to_whatever(dev, pdlptr + 1);
 	ringptr->skb = (void *) NULL;
 
 	/* 
@@ -1257,7 +1281,7 @@
 	 */
 	/* Note that pdlptr+1 and not pdlptr is the pointer to the PDH */
 
-	*(pdlptr + 2) = (u_int) virt_to_bus(pdlptr);	/* Address Frag 1 */
+	*(pdlptr + 2) = (u_int) virt_to_whatever(dev, pdlptr);	/* Address Frag 1 */
 	*(pdlptr + 3) = 4;	/* Length  Frag 1 */
 
 	return ((((MAX_RX_FRAG * 2 + 2) + 3) / 4) * 4);
@@ -1272,7 +1296,7 @@
 		printk("hp100: %s: Init txpdl: Unaligned pdlptr 0x%x.\n", dev->name, (unsigned) pdlptr);
 
 	ringptr->pdl = pdlptr;	/* +1; */
-	ringptr->pdl_paddr = virt_to_bus(pdlptr);	/* +1 */
+	ringptr->pdl_paddr = virt_to_whatever(dev, pdlptr);	/* +1 */
 	ringptr->skb = (void *) NULL;
 
 	return ((((MAX_TX_FRAG * 2 + 2) + 3) / 4) * 4);
@@ -1331,8 +1355,10 @@
 				     (unsigned int) ringptr->skb->data);
 #endif
 
+		/* Conversion to new PCI API : map skbuf data to PCI bus.
+		 * Doc says it's OK for EISA as well - Jean II */
 		ringptr->pdl[0] = 0x00020000;	/* Write PDH */
-		ringptr->pdl[3] = ((u_int) virt_to_bus(ringptr->skb->data));
+		ringptr->pdl[3] = ((u_int) pci_map_single(((struct hp100_private *) (dev->priv))->pci_dev, ringptr->skb->data, MAX_ETHER_SIZE, PCI_DMA_FROMDEVICE));
 		ringptr->pdl[4] = MAX_ETHER_SIZE;	/* Length of Data */
 
 #ifdef HP100_DEBUG_BM
@@ -1585,7 +1611,6 @@
 
 	ringptr->skb = skb;
 	ringptr->pdl[0] = ((1 << 16) | i);	/* PDH: 1 Fragment & length */
-	ringptr->pdl[1] = (u32) virt_to_bus(skb->data);	/* 1st Frag: Adr. of data */
 	if (lp->chip == HP100_CHIPID_SHASTA) {
 		/* TODO:Could someone who has the EISA card please check if this works? */
 		ringptr->pdl[2] = i;
@@ -1593,6 +1618,9 @@
 		/* In the PDL, don't use the padded size but the real packet size: */
 		ringptr->pdl[2] = skb->len;	/* 1st Frag: Length of frag */
 	}
+	/* Conversion to new PCI API : map skbuf data to PCI bus.
+	 * Doc says it's OK for EISA as well - Jean II */
+	ringptr->pdl[1] = ((u32) pci_map_single(lp->pci_dev, skb->data, ringptr->pdl[2], PCI_DMA_TODEVICE));	/* 1st Frag: Adr. of data */
 
 	/* Hand this PDL to the card. */
 	hp100_outl(ringptr->pdl_paddr, TX_PDA_L);	/* Low Prio. Queue */
@@ -1641,6 +1669,8 @@
 				dev->name, (u_int) lp->txrhead->skb->data,
 				lp->txrcommit, hp100_inb(TX_PDL), donecount);
 #endif
+		/* Conversion to new PCI API : NOP */
+		pci_unmap_single(lp->pci_dev, (dma_addr_t) lp->txrhead->pdl[1], lp->txrhead->pdl[2], PCI_DMA_TODEVICE);
 		dev_kfree_skb_any(lp->txrhead->skb);
 		lp->txrhead->skb = (void *) NULL;
 		lp->txrhead = lp->txrhead->next;
@@ -1950,6 +1980,9 @@
 		header = *(ptr->pdl - 1);
 		pkt_len = (header & HP100_PKT_LEN_MASK);
 
+		/* Conversion to new PCI API : NOP */
+		pci_unmap_single(lp->pci_dev, (dma_addr_t) ptr->pdl[3], MAX_ETHER_SIZE, PCI_DMA_FROMDEVICE);
+
 #ifdef HP100_DEBUG_BM
 		printk("hp100: %s: rx_bm: header@0x%x=0x%x length=%d, errors=0x%x, dest=0x%x\n",
 				dev->name, (u_int) (ptr->pdl - 1), (u_int) header,
@@ -2910,7 +2943,7 @@
 	release_region(d->base_addr, HP100_REGION_SIZE);
 
 	if (p->mode == 1)	/* busmaster */
-		kfree(p->page_vaddr);
+		pci_free_consistent(p->pci_dev, MAX_RINGSIZE + 0x0f, p->page_vaddr_algn, virt_to_whatever(d, p->page_vaddr_algn));
 	if (p->mem_ptr_virt)
 		iounmap(p->mem_ptr_virt);
 	kfree(d->priv);
diff -Nru a/drivers/net/lance.c b/drivers/net/lance.c
--- a/drivers/net/lance.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/lance.c	Fri Mar 15 17:51:01 2002
@@ -354,7 +354,7 @@
    board probes now that kmalloc() can allocate ISA DMA-able regions.
    This also allows the LANCE driver to be used as a module.
    */
-int lance_probe(struct net_device *dev)
+int __init lance_probe(struct net_device *dev)
 {
 	int *port, result;
 
diff -Nru a/drivers/net/ns83820.c b/drivers/net/ns83820.c
--- a/drivers/net/ns83820.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/net/ns83820.c	Fri Mar 15 17:51:04 2002
@@ -1,7 +1,7 @@
-#define _VERSION "0.15"
+#define _VERSION "0.17"
 /* ns83820.c by Benjamin LaHaise <bcrl@redhat.com> with contributions.
  *
- * $Revision: 1.34.2.12 $
+ * $Revision: 1.34.2.14 $
  *
  * Copyright 2001 Benjamin LaHaise.
  * Copyright 2001 Red Hat.
@@ -51,6 +51,8 @@
  *				suppress duplicate link status messages
  *	20011117 	0.14 - ethtool GDRVINFO, GLINK support
  *	20011204 	0.15	get ppc (big endian) working
+ *	20011218	0.16	various cleanups
+ *	20020310	0.17	speedups
  *
  * Driver Overview
  * ===============
@@ -93,8 +95,8 @@
 #include <linux/in.h>	/* for IPPROTO_... */
 #include <linux/eeprom.h>
 #include <linux/compiler.h>
+#include <linux/prefetch.h>
 #include <linux/ethtool.h>
-//#include <linux/skbrefill.h>
 
 #include <asm/io.h>
 #include <asm/uaccess.h>
@@ -154,10 +156,16 @@
 #endif
 
 /* tunables */
-#define RX_BUF_SIZE	6144	/* 8192 */
-#define NR_RX_DESC	256
+#define RX_BUF_SIZE	1500	/* 8192 */
 
-#define NR_TX_DESC	256
+/* Must not exceed ~65000. */
+#define NR_RX_DESC	64
+#define NR_TX_DESC	64
+
+/* not tunable */
+#define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14)	/* rx/tx mac addr + type */
+
+#define MIN_TX_DESC_FREE	8
 
 /* register defines */
 #define CFGCS		0x04
@@ -408,7 +416,8 @@
 
 	struct sk_buff	*skbs[NR_RX_DESC];
 
-	unsigned	next_rx, next_empty;
+	u32		*next_rx_desc;
+	u16		next_rx, next_empty;
 
 	u32		*descs;
 	dma_addr_t	phy_descs;
@@ -423,6 +432,7 @@
 	struct pci_dev		*pci_dev;
 
 	struct rx_info		rx_info;
+	struct tasklet_struct	rx_tasklet;
 
 	unsigned		ihr;
 	struct tq_struct	tq_refill;
@@ -441,10 +451,11 @@
 	spinlock_t	tx_lock;
 
 	long		tx_idle;
-	u32		tx_done_idx;
-	u32		tx_idx;
-	volatile u32	tx_free_idx;	/* idx of free desc chain */
-	u32		tx_intr_idx;
+
+	u16		tx_done_idx;
+	u16		tx_idx;
+	volatile u16	tx_free_idx;	/* idx of free desc chain */
+	u16		tx_intr_idx;
 
 	struct sk_buff	*tx_skbs[NR_TX_DESC];
 
@@ -455,7 +466,7 @@
 
 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
 #define start_tx_okay(dev)	\
-	(((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > NR_TX_DESC/2)
+	(((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
 
 
 /* Packet Receiver
@@ -509,7 +520,7 @@
 	next_empty = dev->rx_info.next_empty;
 
 	/* don't overrun last rx marker */
-	if (nr_rx_empty(dev) <= 2) {
+	if (unlikely(nr_rx_empty(dev) <= 2)) {
 		kfree_skb(skb);
 		return 1;
 	}
@@ -523,34 +534,39 @@
 #endif
 
 	sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
-	if (dev->rx_info.skbs[next_empty])
+	if (unlikely(NULL != dev->rx_info.skbs[next_empty]))
 		BUG();
 	dev->rx_info.skbs[next_empty] = skb;
 
 	dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
-	cmdsts = RX_BUF_SIZE | CMDSTS_INTR;
-	buf = pci_map_single(dev->pci_dev, skb->tail, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
+	cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
+	buf = pci_map_single(dev->pci_dev, skb->tail,
+			     REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
 	build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
 	/* update link of previous rx */
-	if (next_empty != dev->rx_info.next_rx)
+	if (likely(next_empty != dev->rx_info.next_rx))
 		dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
 
 	return 0;
 }
 
-static int rx_refill(struct ns83820 *dev, int gfp)
+static inline int rx_refill(struct ns83820 *dev, int gfp)
 {
 	unsigned i;
 	long flags = 0;
 
+	if (unlikely(nr_rx_empty(dev) <= 2))
+		return 0;
+
 	dprintk("rx_refill(%p)\n", dev);
 	if (gfp == GFP_ATOMIC)
 		spin_lock_irqsave(&dev->rx_info.lock, flags);
 	for (i=0; i<NR_RX_DESC; i++) {
 		struct sk_buff *skb;
 		long res;
-		skb = __dev_alloc_skb(RX_BUF_SIZE+16, gfp);
-		if (!skb)
+		/* extra 16 bytes for alignment */
+		skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
+		if (unlikely(!skb))
 			break;
 
 		res = (long)skb->tail & 0xf;
@@ -575,6 +591,12 @@
 	return i ? 0 : -ENOMEM;
 }
 
+static void FASTCALL(rx_refill_atomic(struct ns83820 *dev));
+static void rx_refill_atomic(struct ns83820 *dev)
+{
+	rx_refill(dev, GFP_ATOMIC);
+}
+
 /* REFILL */
 static inline void queue_refill(void *_dev)
 {
@@ -590,6 +612,7 @@
 	build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
 }
 
+static void FASTCALL(phy_intr(struct ns83820 *dev));
 static void phy_intr(struct ns83820 *dev)
 {
 	static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
@@ -600,7 +623,6 @@
 	cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
 
 	if (dev->CFG_cache & CFG_TBI_EN) {
-
 		/* we have an optical transceiver */
 		tbisr = readl(dev->base + TBISR);
 		tanar = readl(dev->base + TANAR);
@@ -646,20 +668,24 @@
 		new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
 
 		if (cfg & CFG_SPDSTS1)
-			new_cfg |= CFG_MODE_1000 | CFG_SB;
+			new_cfg |= CFG_MODE_1000;
 		else
-			new_cfg &= ~CFG_MODE_1000 | CFG_SB;
+			new_cfg &= ~CFG_MODE_1000;
 
-		if ((cfg & CFG_LNKSTS) && ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) {
+		speed = ((cfg / CFG_SPDSTS0) & 3);
+		fullduplex = (cfg & CFG_DUPSTS);
+
+		if (fullduplex)
+			new_cfg |= CFG_SB;
+
+		if ((cfg & CFG_LNKSTS) &&
+		    ((new_cfg ^ dev->CFG_cache) & CFG_MODE_1000)) {
 			writel(new_cfg, dev->base + CFG);
 			dev->CFG_cache = new_cfg;
 		}
 
 		dev->CFG_cache &= ~CFG_SPDSTS;
 		dev->CFG_cache |= cfg & CFG_SPDSTS;
-
-		speed = ((cfg / CFG_SPDSTS0) & 3);
-		fullduplex = (cfg & CFG_DUPSTS);
 	}
 
 	newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
@@ -690,6 +716,7 @@
 
 	dev->rx_info.idle = 1;
 	dev->rx_info.next_rx = 0;
+	dev->rx_info.next_rx_desc = dev->rx_info.descs;
 	dev->rx_info.next_empty = 0;
 
 	for (i=0; i<NR_RX_DESC; i++)
@@ -724,7 +751,7 @@
 		dev->IMR_cache |= ISR_RXDESC;
 		dev->IMR_cache |= ISR_RXIDLE;
 		dev->IMR_cache |= ISR_TXDESC;
-		//dev->IMR_cache |= ISR_TXIDLE;
+		dev->IMR_cache |= ISR_TXIDLE;
 
 		writel(dev->IMR_cache, dev->base + IMR);
 		writel(1, dev->base + IER);
@@ -770,6 +797,41 @@
 	}
 }
 
+/* I hate the network stack sometimes */
+#ifdef __i386__
+#define skb_mangle_for_davem(skb,len)	(skb)
+#else
+static inline struct sk_buff *skb_mangle_for_davem(struct sk_buff *skb, int len)
+{
+	tmp = __dev_alloc_skb(len+2, GFP_ATOMIC);
+	if (!tmp)
+		goto done;
+	tmp->dev = &dev->net_dev;
+	skb_reserve(tmp, 2);
+	memcpy(skb_put(tmp, len), skb->data, len);
+	kfree_skb(skb);
+	return tmp;
+}
+#endif
+
+static void FASTCALL(ns83820_rx_kick(struct ns83820 *dev));
+static void ns83820_rx_kick(struct ns83820 *dev)
+{
+	/*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
+		if (dev->rx_info.up) {
+			rx_refill_atomic(dev);
+			kick_rx(dev);
+		}
+	}
+
+	if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
+		schedule_task(&dev->tq_refill);
+	else
+		kick_rx(dev);
+	if (dev->rx_info.idle)
+		Dprintk("BAD\n");
+}
+
 /* rx_irq
  *	
  */
@@ -785,10 +847,10 @@
 	dprintk("rx_irq(%p)\n", dev);
 	dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
 		readl(dev->base + RXDP),
-		(dev->rx_info.phy_descs),
-		dev->rx_info.next_rx,
+		(long)(dev->rx_info.phy_descs),
+		(int)dev->rx_info.next_rx,
 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
-		dev->rx_info.next_empty,
+		(int)dev->rx_info.next_empty,
 		(dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
 		);
 
@@ -798,7 +860,7 @@
 
 	dprintk("walking descs\n");
 	next_rx = info->next_rx;
-	desc = info->descs + (DESC_SIZE * next_rx);
+	desc = info->next_rx_desc;
 	while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[CMDSTS]))) &&
 	       (cmdsts != CMDSTS_OWN)) {
 		struct sk_buff *skb;
@@ -813,29 +875,17 @@
 		info->skbs[next_rx] = NULL;
 		info->next_rx = (next_rx + 1) % NR_RX_DESC;
 
-		barrier();
+		mb();
 		clear_rx_desc(dev, next_rx);
 
 		pci_unmap_single(dev->pci_dev, bufptr,
 				 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
-		if (CMDSTS_OK & cmdsts) {
-#if 0 //ndef __i386__
-			struct sk_buff *tmp;
-#endif
+		if (likely(CMDSTS_OK & cmdsts)) {
 			int len = cmdsts & 0xffff;
-			if (!skb)
-				BUG();
 			skb_put(skb, len);
-#if 0 //ndef __i386__	/* I hate the network stack sometimes */
-			tmp = __dev_alloc_skb(RX_BUF_SIZE+16, GFP_ATOMIC);
-			if (!tmp)
-				goto done;
-			tmp->dev = &dev->net_dev;
-			skb_reserve(tmp, 2);
-			memcpy(skb_put(tmp, len), skb->data, len);
-			kfree_skb(skb);
-			skb = tmp;
-#endif
+			skb = skb_mangle_for_davem(skb, len);
+			if (unlikely(!skb))
+				goto netdev_mangle_me_harder_failed;
 			if (cmdsts & CMDSTS_DEST_MULTI)
 				dev->stats.multicast ++;
 			dev->stats.rx_packets ++;
@@ -846,11 +896,10 @@
 				skb->ip_summed = CHECKSUM_NONE;
 			}
 			skb->protocol = eth_type_trans(skb, &dev->net_dev);
-			if (NET_RX_DROP == netif_rx(skb))
+			if (NET_RX_DROP == netif_rx(skb)) {
+netdev_mangle_me_harder_failed:
 				dev->stats.rx_dropped ++;
-#if 0 //ndef __i386__
-		done:;
-#endif
+			}
 		} else {
 			kfree_skb(skb);
 		}
@@ -860,6 +909,7 @@
 		desc = info->descs + (DESC_SIZE * next_rx);
 	}
 	info->next_rx = next_rx;
+	info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
 
 out:
 	if (0 && !nr) {
@@ -869,6 +919,15 @@
 	spin_unlock_irqrestore(&info->lock, flags);
 }
 
+static void rx_action(unsigned long _dev)
+{
+	struct ns83820 *dev = (void *)_dev;
+	rx_irq(dev);
+	writel(0x002, dev->base + IHR);
+	writel(dev->IMR_cache | ISR_RXDESC, dev->base + IMR);
+	rx_irq(dev);
+	ns83820_rx_kick(dev);
+}
 
 /* Packet Transmit code
  */
@@ -879,7 +938,9 @@
 	writel(CR_TXE, dev->base + CR);
 }
 
-/* no spinlock needed on the transmit irq path as the interrupt handler is serialized */
+/* No spinlock needed on the transmit irq path as the interrupt handler is
+ * serialized.
+ */
 static void do_tx_done(struct ns83820 *dev)
 {
 	u32 cmdsts, tx_done_idx, *desc;
@@ -917,7 +978,7 @@
 		tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
 		dev->tx_done_idx = tx_done_idx;
 		desc[CMDSTS] = cpu_to_le32(0);
-		barrier();
+		mb();
 		desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
 	}
 
@@ -952,7 +1013,6 @@
  * while trying to track down a bug in either the zero copy code or
  * the tx fifo (hence the MAX_FRAG_LEN).
  */
-#define MAX_FRAG_LEN	8192	/* disabled for now */
 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *_dev)
 {
 	struct ns83820 *dev = (struct ns83820 *)_dev;
@@ -970,9 +1030,9 @@
 
 	nr_frags =  skb_shinfo(skb)->nr_frags;
 again:
-	if (__builtin_expect(dev->CFG_cache & CFG_LNKSTS, 0)) {
+	if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
 		netif_stop_queue(&dev->net_dev);
-		if (__builtin_expect(dev->CFG_cache & CFG_LNKSTS, 0))
+		if (unlikely(dev->CFG_cache & CFG_LNKSTS))
 			return 1;
 		netif_start_queue(&dev->net_dev);
 	}
@@ -981,7 +1041,7 @@
 	tx_done_idx = dev->tx_done_idx;
 	nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
 	nr_free -= 1;
-	if ((nr_free <= nr_frags) || (nr_free <= 8192 / MAX_FRAG_LEN)) {
+	if (nr_free <= nr_frags) {
 		dprintk("stop_queue - not enough(%p)\n", dev);
 		netif_stop_queue(&dev->net_dev);
 
@@ -996,11 +1056,11 @@
 
 	if (free_idx == dev->tx_intr_idx) {
 		do_intr = 1;
-		dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/2) % NR_TX_DESC;
+		dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
 	}
 
 	nr_free -= nr_frags;
-	if (nr_free < 1) {
+	if (nr_free < MIN_TX_DESC_FREE) {
 		dprintk("stop_queue - last entry(%p)\n", dev);
 		netif_stop_queue(&dev->net_dev);
 		stopped = 1;
@@ -1028,14 +1088,6 @@
 	for (;;) {
 		volatile u32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
 		u32 residue = 0;
-#if 0
-		if (len > MAX_FRAG_LEN) {
-			residue = len;
-			/* align the start address of the next fragment */
-			len = MAX_FRAG_LEN;
-			residue -= len;
-		}
-#endif
 
 		dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
 			(unsigned long long)buf);
@@ -1084,6 +1136,7 @@
 {
 	u8 *base = dev->base;
 
+	/* the DP83820 will freeze counters, so we need to read all of them */
 	dev->stats.rx_errors		+= readl(base + 0x60) & 0xffff;
 	dev->stats.rx_crc_errors	+= readl(base + 0x64) & 0xffff;
 	dev->stats.rx_missed_errors	+= readl(base + 0x68) & 0xffff;
@@ -1162,54 +1215,54 @@
 	}
 }
 
+static void ns83820_mib_isr(struct ns83820 *dev)
+{
+	spin_lock(&dev->misc_lock);
+	ns83820_update_stats(dev);
+	spin_unlock(&dev->misc_lock);
+}
+
 static void ns83820_irq(int foo, void *data, struct pt_regs *regs)
 {
 	struct ns83820 *dev = data;
-	int count = 0;
 	u32 isr;
 	dprintk("ns83820_irq(%p)\n", dev);
 
 	dev->ihr = 0;
 
-	while (count++ < 32 && (isr = readl(dev->base + ISR))) {
-		dprintk("irq: %08x\n", isr);
-
-		if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
-			Dprintk("odd isr? 0x%08x\n", isr);
-
-	if ((ISR_RXEARLY | ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr) {
- 		if (ISR_RXIDLE & isr) {
-			dev->rx_info.idle = 1;
-			Dprintk("oh dear, we are idle\n");
-		}
+	isr = readl(dev->base + ISR);
+	dprintk("irq: %08x\n", isr);
 
-		if ((ISR_RXDESC) & isr) {
-			rx_irq(dev);
-			writel(4, dev->base + IHR);
-		}
-
-		if (nr_rx_empty(dev) >= NR_RX_DESC/4) {
-			if (dev->rx_info.up) {
-				rx_refill(dev, GFP_ATOMIC);
-				kick_rx(dev);
-			}
-		}
+#ifdef DEBUG
+	if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
+		Dprintk("odd isr? 0x%08x\n", isr);
+#endif
 
-		if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
-			schedule_task(&dev->tq_refill);
-		else
-			kick_rx(dev);
-		if (dev->rx_info.idle)
-			Dprintk("BAD\n");
+	if (ISR_RXIDLE & isr) {
+		dev->rx_info.idle = 1;
+		Dprintk("oh dear, we are idle\n");
+		ns83820_rx_kick(dev);
+	}
+
+	if ((ISR_RXDESC | ISR_RXOK) & isr) {
+		prefetch(dev->rx_info.next_rx_desc);
+		writel(dev->IMR_cache & ~(ISR_RXDESC | ISR_RXOK), dev->base + IMR);
+		tasklet_schedule(&dev->rx_tasklet);
+		//rx_irq(dev);
+		//writel(4, dev->base + IHR);
 	}
 
+	if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
+		ns83820_rx_kick(dev);
+
 	if (unlikely(ISR_RXSOVR & isr)) {
-		Dprintk("overrun: rxsovr\n");
-		dev->stats.rx_over_errors ++;
+		//printk("overrun: rxsovr\n");
+		dev->stats.rx_fifo_errors ++;
 	}
+
 	if (unlikely(ISR_RXORN & isr)) {
-		Dprintk("overrun: rxorn\n");
-		dev->stats.rx_over_errors ++;
+		//printk("overrun: rxorn\n");
+		dev->stats.rx_fifo_errors ++;
 	}
 
 	if ((ISR_RXRCMP & isr) && dev->rx_info.up)
@@ -1241,15 +1294,11 @@
 	if ((ISR_TXDESC | ISR_TXIDLE) & isr)
 		do_tx_done(dev);
 
-	if (ISR_MIB & isr) {
-		spin_lock(&dev->misc_lock);
-		ns83820_update_stats(dev);
-		spin_unlock(&dev->misc_lock);
-	}
+	if (unlikely(ISR_MIB & isr))
+		ns83820_mib_isr(dev);
 
-	if (ISR_PHY & isr)
+	if (unlikely(ISR_PHY & isr))
 		phy_intr(dev);
-	}
 
 #if 0	/* Still working on the interrupt mitigation strategy */
 	if (dev->ihr)
@@ -1412,6 +1461,7 @@
 	dev->net_dev.owner = THIS_MODULE;
 
 	PREPARE_TQUEUE(&dev->tq_refill, queue_refill, dev);
+	tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)dev);
 
 	err = pci_enable_device(pci_dev);
 	if (err) {
@@ -1430,8 +1480,9 @@
 	if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
 		goto out_disable;
 
-	dprintk("%p: %08lx  %p: %08lx\n", dev->tx_descs, dev->tx_phy_descs,
-		dev->rx_info.descs, dev->rx_info.phy_descs);
+	dprintk("%p: %08lx  %p: %08lx\n",
+		dev->tx_descs, (long)dev->tx_phy_descs,
+		dev->rx_info.descs, (long)dev->rx_info.phy_descs);
 	/* disable interrupts */
 	writel(0, dev->base + IMR);
 	writel(0, dev->base + IER);
@@ -1484,14 +1535,14 @@
 	dev->CFG_cache = readl(dev->base + CFG);
 
 	if ((dev->CFG_cache & CFG_PCI64_DET)) {
-		printk("%s: enabling 64 bit PCI addressing.\n",
+		printk("%s: detected 64 bit PCI data bus.\n",
 			dev->net_dev.name);
-		dev->CFG_cache |= CFG_T64ADDR | CFG_DATA64_EN;
-#if defined(USE_64BIT_ADDR)
-		dev->net_dev.features |= NETIF_F_HIGHDMA;
-#endif
+		/*dev->CFG_cache |= CFG_DATA64_EN;*/
+		if (!(dev->CFG_cache & CFG_DATA64_EN))
+			printk("%s: EEPROM did not enable 64 bit bus.  Disabled.\n",
+				dev->net_dev.name);
 	} else
-		dev->CFG_cache &= ~(CFG_T64ADDR | CFG_DATA64_EN);
+		dev->CFG_cache &= ~(CFG_DATA64_EN);
 
 	dev->CFG_cache &= (CFG_TBI_EN  | CFG_MRM_DIS   | CFG_MWI_DIS |
 			   CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
@@ -1528,8 +1579,12 @@
 	writel(dev->CFG_cache, dev->base + CFG);
 	dprintk("CFG: %08x\n", dev->CFG_cache);
 
+#if 1	/* Huh?  This sets the PCI latency register.  Should be done via 
+	 * the PCI layer.  FIXME.
+	 */
 	if (readl(dev->base + SRR))
 		writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
+#endif
 
 	/* Note!  The DMA burst size interacts with packet
 	 * transmission, such that the largest packet that
@@ -1543,13 +1598,15 @@
 	/* Flush the interrupt holdoff timer */
 	writel(0x000, dev->base + IHR);
 	writel(0x100, dev->base + IHR);
+	writel(0x000, dev->base + IHR);
 
 	/* Set Rx to full duplex, don't accept runt, errored, long or length
-	 * range errored packets.  Set MXDMA to 7 => 512 word burst
+	 * range errored packets.  Set MXDMA to 0 => 1024 word burst
 	 */
 	writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
+		| RXCFG_STRIPCRC
 		| RXCFG_ALP
-		| RXCFG_MXDMA | 0, dev->base + RXCFG);
+		| (RXCFG_MXDMA0 * 0) | 0, dev->base + RXCFG);
 
 	/* Disable priority queueing */
 	writel(0, dev->base + PQCR);
@@ -1576,7 +1633,11 @@
 	dev->net_dev.features |= NETIF_F_SG;
 	dev->net_dev.features |= NETIF_F_IP_CSUM;
 #if defined(USE_64BIT_ADDR) || defined(CONFIG_HIGHMEM4G)
-	dev->net_dev.features |= NETIF_F_HIGHDMA;
+	if ((dev->CFG_cache & CFG_T64ADDR)) {
+		printk(KERN_INFO "%s: using 64 bit addressing.\n",
+			dev->net_dev.name);
+		dev->net_dev.features |= NETIF_F_HIGHDMA;
+	}
 #endif
 
 	printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
@@ -1587,7 +1648,7 @@
 		dev->net_dev.dev_addr[2], dev->net_dev.dev_addr[3],
 		dev->net_dev.dev_addr[4], dev->net_dev.dev_addr[5],
 		addr, pci_dev->irq,
-		(dev->net_dev.features & NETIF_F_HIGHDMA) ? "sg" : "h,sg"
+		(dev->net_dev.features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
 		);
 
 	return 0;
diff -Nru a/drivers/net/pcnet32.c b/drivers/net/pcnet32.c
--- a/drivers/net/pcnet32.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/pcnet32.c	Fri Mar 15 17:51:02 2002
@@ -323,7 +323,7 @@
 
 static void pcnet32_probe_vlbus(void);
 static int  pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
-static int  pcnet32_probe1(unsigned long, unsigned char, int, struct pci_dev *);
+static int  pcnet32_probe1(unsigned long, unsigned int, int, struct pci_dev *);
 static int  pcnet32_open(struct net_device *);
 static int  pcnet32_init_ring(struct net_device *);
 static int  pcnet32_start_xmit(struct sk_buff *, struct net_device *);
@@ -507,7 +507,7 @@
  *  pdev will be NULL when called from pcnet32_probe_vlbus.
  */
 static int __devinit
-pcnet32_probe1(unsigned long ioaddr, unsigned char irq_line, int shared,
+pcnet32_probe1(unsigned long ioaddr, unsigned int irq_line, int shared,
 		struct pci_dev *pdev)
 {
     struct pcnet32_private *lp;
@@ -522,13 +522,13 @@
     u8 promaddr[6];
 
     /* reset the chip */
-    pcnet32_dwio_reset(ioaddr);
     pcnet32_wio_reset(ioaddr);
 
     /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
     if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
 	a = &pcnet32_wio;
     } else {
+	pcnet32_dwio_reset(ioaddr);
 	if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
 	    a = &pcnet32_dwio;
 	} else
@@ -789,7 +789,7 @@
     dev->set_multicast_list = &pcnet32_set_multicast_list;
     dev->do_ioctl = &pcnet32_ioctl;
     dev->tx_timeout = pcnet32_tx_timeout;
-    dev->watchdog_timeo = (HZ >> 1);
+    dev->watchdog_timeo = (5*HZ);
 
     lp->next = pcnet32_dev;
     pcnet32_dev = dev;
@@ -946,7 +946,7 @@
     for (i = 0; i < TX_RING_SIZE; i++) {
 	if (lp->tx_skbuff[i]) {
             pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
-	    dev_kfree_skb(lp->tx_skbuff[i]); 
+	    dev_kfree_skb_any(lp->tx_skbuff[i]); 
 	    lp->tx_skbuff[i] = NULL;
             lp->tx_dma_addr[i] = 0;
 	}
@@ -1022,8 +1022,9 @@
 pcnet32_tx_timeout (struct net_device *dev)
 {
     struct pcnet32_private *lp = dev->priv;
-    unsigned int ioaddr = dev->base_addr;
+    unsigned long ioaddr = dev->base_addr, flags;
 
+    spin_lock_irqsave(&lp->lock, flags);
     /* Transmitter timeout, serious problems. */
 	printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
 	       dev->name, lp->a.read_csr(ioaddr, 0));
@@ -1048,6 +1049,8 @@
 
 	dev->trans_start = jiffies;
 	netif_start_queue(dev);
+
+	spin_unlock_irqrestore(&lp->lock, flags);
 }
 
 
@@ -1055,7 +1058,7 @@
 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
     struct pcnet32_private *lp = dev->priv;
-    unsigned int ioaddr = dev->base_addr;
+    unsigned long ioaddr = dev->base_addr;
     u16 status;
     int entry;
     unsigned long flags;
@@ -1307,6 +1310,7 @@
 		    if ((newskb = dev_alloc_skb (PKT_BUF_SZ))) {
 			skb_reserve (newskb, 2);
 			skb = lp->rx_skbuff[entry];
+			pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry], skb->len, PCI_DMA_FROMDEVICE);
 			skb_put (skb, pkt_len);
 			lp->rx_skbuff[entry] = newskb;
 			newskb->dev = dev;
@@ -1473,9 +1477,10 @@
  */
 static void pcnet32_set_multicast_list(struct net_device *dev)
 {
-    unsigned long ioaddr = dev->base_addr;
+    unsigned long ioaddr = dev->base_addr, flags;
     struct pcnet32_private *lp = dev->priv;	 
 
+    spin_lock_irqsave(&lp->lock, flags);
     if (dev->flags&IFF_PROMISC) {
 	/* Log any net taps. */
 	printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
@@ -1488,6 +1493,7 @@
     lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
 
     pcnet32_restart(dev, 0x0042); /*  Resume normal operation */
+    spin_unlock_irqrestore(&lp->lock, flags);
 }
 
 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
diff -Nru a/drivers/net/pppoe.c b/drivers/net/pppoe.c
--- a/drivers/net/pppoe.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/pppoe.c	Fri Mar 15 17:51:01 2002
@@ -635,7 +635,7 @@
 		sk->state = PPPOX_CONNECTED;
 	}
 
-	sk->num = sp->sa_addr.pppoe.sid;
+	po->num = sp->sa_addr.pppoe.sid;
 
  end:
 	release_sock(sk);
@@ -788,7 +788,7 @@
 	hdr.ver = 1;
 	hdr.type = 1;
 	hdr.code = 0;
-	hdr.sid = sk->num;
+	hdr.sid = po->num;
 
 	lock_sock(sk);
 
@@ -862,7 +862,7 @@
 	hdr.ver	= 1;
 	hdr.type = 1;
 	hdr.code = 0;
-	hdr.sid	= sk->num;
+	hdr.sid	= po->num;
 	hdr.length = htons(skb->len);
 
 	if (!dev)
diff -Nru a/drivers/net/sunhme.c b/drivers/net/sunhme.c
--- a/drivers/net/sunhme.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/net/sunhme.c	Fri Mar 15 17:51:02 2002
@@ -1611,12 +1611,12 @@
 
 	/* Set the RX and TX ring ptrs. */
 	HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
-	     (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
-	     (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
+	     ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
+	     ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
 	hme_write32(hp, erxregs + ERX_RING,
-		    (hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
+		    ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
 	hme_write32(hp, etxregs + ETX_RING,
-		    (hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
+		    ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
 
 	/* Set the supported burst sizes. */
 	HMD(("happy_meal_init: old[%08x] bursts<",
@@ -2643,21 +2643,23 @@
 	struct happy_meal *hp;
 	struct net_device *dev;
 	int i, qfe_slot = -1;
+	int err = -ENODEV;
 
 	if (is_qfe) {
 		qp = quattro_sbus_find(sdev);
 		if (qp == NULL)
-			return -ENODEV;
+			goto err_out;
 		for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
 			if (qp->happy_meals[qfe_slot] == NULL)
 				break;
 		if (qfe_slot == 4)
-			return -ENODEV;
+			goto err_out;
 	}
 
+	err = -ENOMEM;
 	dev = init_etherdev(NULL, sizeof(struct happy_meal));
 	if (!dev)
-		return -ENOMEM;
+		goto err_out;
 	SET_MODULE_OWNER(dev);
 
 	if (hme_version_printed++ == 0)
@@ -2701,11 +2703,12 @@
 
 	spin_lock_init(&hp->happy_lock);
 
+	err = -ENODEV;
 	if (sdev->num_registers != 5) {
 		printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
 		       sdev->num_registers);
 		printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
-		return -ENODEV;
+		goto err_out_free_netdev;
 	}
 
 	if (qp != NULL) {
@@ -2719,35 +2722,35 @@
 				 GREG_REG_SIZE, "HME Global Regs");
 	if (!hp->gregs) {
 		printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
-		return -ENODEV;
+		goto err_out_free_netdev;
 	}
 
 	hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
 				   ETX_REG_SIZE, "HME TX Regs");
 	if (!hp->etxregs) {
 		printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
-		return -ENODEV;
+		goto err_out_iounmap;
 	}
 
 	hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
 				   ERX_REG_SIZE, "HME RX Regs");
 	if (!hp->erxregs) {
 		printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
-		return -ENODEV;
+		goto err_out_iounmap;
 	}
 
 	hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
 				      BMAC_REG_SIZE, "HME BIGMAC Regs");
 	if (!hp->bigmacregs) {
 		printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
-		return -ENODEV;
+		goto err_out_iounmap;
 	}
 
 	hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
 				   TCVR_REG_SIZE, "HME Tranceiver Regs");
 	if (!hp->tcvregs) {
 		printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
-		return -ENODEV;
+		goto err_out_iounmap;
 	}
 
 	hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
@@ -2770,6 +2773,11 @@
 	hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
 						PAGE_SIZE,
 						&hp->hblock_dvma);
+	err = -ENOMEM;
+	if (!hp->happy_block) {
+		printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
+		goto err_out_iounmap;
+	}
 
 	/* Force check of the link first time we are brought up. */
 	hp->linkcheck = 0;
@@ -2822,6 +2830,25 @@
 	root_happy_dev = hp;
 
 	return 0;
+
+err_out_iounmap:
+	if (hp->gregs)
+		sbus_iounmap(hp->gregs, GREG_REG_SIZE);
+	if (hp->etxregs)
+		sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
+	if (hp->erxregs)
+		sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
+	if (hp->bigmacregs)
+		sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
+	if (hp->tcvregs)
+		sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
+
+err_out_free_netdev:
+	unregister_netdev(dev);
+	kfree(dev);
+
+err_out:
+	return err;
 }
 #endif
 
@@ -2838,6 +2865,7 @@
 	unsigned long hpreg_base;
 	int i, qfe_slot = -1;
 	char prom_name[64];
+	int err;
 
 	/* Now make sure pci_dev cookie is there. */
 #ifdef __sparc__
@@ -2854,20 +2882,22 @@
 	strcpy(prom_name, "qfe");
 #endif
 
+	err = -ENODEV;
 	if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
 		qp = quattro_pci_find(pdev);
 		if (qp == NULL)
-			return -ENODEV;
+			goto err_out;
 		for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
 			if (qp->happy_meals[qfe_slot] == NULL)
 				break;
 		if (qfe_slot == 4)
-			return -ENODEV;
+			goto err_out;
 	}
 
 	dev = init_etherdev(NULL, sizeof(struct happy_meal));
+	err = -ENOMEM;
 	if (!dev)
-		return -ENOMEM;
+		goto err_out;
 	SET_MODULE_OWNER(dev);
 
 	if (hme_version_printed++ == 0)
@@ -2912,9 +2942,10 @@
 	}		
 
 	hpreg_base = pci_resource_start(pdev, 0);
+	err = -ENODEV;
 	if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
 		printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
-		return -ENODEV;
+		goto err_out_clear_quattro;
 	}
 	if ((hpreg_base = (unsigned long) ioremap(hpreg_base, 0x8000)) == 0) {
 		printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
@@ -2983,9 +3014,10 @@
 	hp->happy_block = (struct hmeal_init_block *)
 		pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
 
+	err = -ENODEV;
 	if (!hp->happy_block) {
 		printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
-		return -ENODEV;
+		goto err_out_iounmap;
 	}
 
 	hp->linkcheck = 0;
@@ -3034,6 +3066,19 @@
 	root_happy_dev = hp;
 
 	return 0;
+
+err_out_iounmap:
+	iounmap((void *)hp->gregs);
+
+err_out_clear_quattro:
+	if (qp != NULL)
+		qp->happy_meals[qfe_slot] = NULL;
+
+	unregister_netdev(dev);
+	kfree(dev);
+
+err_out:
+	return err;
 }
 #endif
 
diff -Nru a/drivers/net/sunhme.h b/drivers/net/sunhme.h
--- a/drivers/net/sunhme.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/sunhme.h	Fri Mar 15 17:51:03 2002
@@ -431,7 +431,7 @@
 	unsigned long	bigmacregs;     /* BIGMAC core regs		     */
 	unsigned long	tcvregs;        /* MIF transceiver regs              */
 
-	__u32                     hblock_dvma;    /* DVMA visible address happy block  */
+	dma_addr_t                hblock_dvma;    /* DVMA visible address happy block  */
 	unsigned int              happy_flags;    /* Driver state flags                */
 	enum happy_transceiver    tcvr_type;      /* Kind of transceiver in use        */
 	unsigned int              happy_bursts;   /* Get your mind out of the gutter   */
diff -Nru a/drivers/net/tg3.c b/drivers/net/tg3.c
--- a/drivers/net/tg3.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/tg3.c	Fri Mar 15 17:51:01 2002
@@ -1,4 +1,4 @@
-/* $Id: tg3.c,v 1.43.2.74 2002/03/06 22:22:29 davem Exp $
+/* $Id: tg3.c,v 1.43.2.79 2002/03/12 07:11:17 davem Exp $
  * tg3.c: Broadcom Tigon3 ethernet driver.
  *
  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
@@ -42,7 +42,11 @@
  */
 #define TG3_MINI_RING_WORKS 0
 
+#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
+#define TG3_VLAN_TAG_USED 1
+#else
 #define TG3_VLAN_TAG_USED 0
+#endif
 
 #include "tg3.h"
 
@@ -78,15 +82,16 @@
  * them in the NIC onboard memory.
  */
 #define TG3_RX_RING_SIZE		512
-#define TG3_RX_RING_PENDING		200
+#define TG3_DEF_RX_RING_PENDING		200
 #if TG3_MINI_RING_WORKS
 #define TG3_RX_MINI_RING_SIZE		256 /* ??? */
-#define TG3_RX_MINI_RING_PENDING	100
+#define TG3_DEF_RX_MINI_RING_PENDING	100
 #endif
 #define TG3_RX_JUMBO_RING_SIZE		256
-#define TG3_RX_JUMBO_RING_PENDING	100
+#define TG3_DEF_RX_JUMBO_RING_PENDING	100
 #define TG3_RX_RCB_RING_SIZE		1024
 #define TG3_TX_RING_SIZE		512
+#define TG3_DEF_TX_RING_PENDING		(TG3_TX_RING_SIZE - 1)
 
 #define TG3_RX_RING_BYTES	(sizeof(struct tg3_rx_buffer_desc) * \
 				 TG3_RX_RING_SIZE)
@@ -100,10 +105,12 @@
 			         TG3_RX_RCB_RING_SIZE)
 #define TG3_TX_RING_BYTES	(sizeof(struct tg3_tx_buffer_desc) * \
 				 TG3_TX_RING_SIZE)
+#define TX_RING_GAP(TP)	\
+	(TG3_TX_RING_SIZE - (TP)->tx_pending)
 #define TX_BUFFS_AVAIL(TP)						\
 	(((TP)->tx_cons <= (TP)->tx_prod) ?				\
-	  (TP)->tx_cons + (TG3_TX_RING_SIZE - 1) - (TP)->tx_prod :	\
-	  (TP)->tx_cons - (TP)->tx_prod - 1)
+	  (TP)->tx_cons + (TP)->tx_pending - (TP)->tx_prod :		\
+	  (TP)->tx_cons - (TP)->tx_prod - TX_RING_GAP(TP))
 #define NEXT_TX(N)		(((N) + 1) & (TG3_TX_RING_SIZE - 1))
 
 #define RX_PKT_BUF_SZ		(1536 + tp->rx_offset + 64)
@@ -1346,6 +1353,7 @@
 			aninfo.flags |= (MR_AN_ENABLE);
 
 			for (i = 0; i < 6; i++) {
+				unsigned int tick;
 				u32 tmp;
 
 				tw32(MAC_TX_AUTO_NEG, 0);
@@ -1358,7 +1366,8 @@
 
 				aninfo.state = ANEG_STATE_UNKNOWN;
 				aninfo.cur_time = 0;
-				while (aninfo.cur_time < 95000) {
+				tick = 0;
+				while (++tick < 95000) {
 					status = tg3_fiber_aneg_smachine(tp, &aninfo);
 					if (status == ANEG_DONE ||
 					    status == ANEG_FAILED)
@@ -1782,7 +1791,7 @@
 			skb = copy_skb;
 		}
 
-		if (!(tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) &&
+		if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
 		    (desc->type_flags & RXD_FLAG_TCPUDP_CSUM)) {
 			skb->csum = htons((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
 					  >> RXD_TCPCSUM_SHIFT);
@@ -1835,61 +1844,99 @@
 #endif
 }
 
-#define RATE_SAMPLE_INTERVAL	(1 * HZ)
-
 #define PKT_RATE_LOW		22000
 #define PKT_RATE_HIGH		61000
 
 static void tg3_rate_sample(struct tg3 *tp, unsigned long ticks)
 {
 	u32 delta, rx_now, tx_now;
-	int new_vals;
+	int new_vals, do_tx, do_rx;
 
 	rx_now = tp->hw_stats->rx_ucast_packets.low;
 	tx_now = tp->hw_stats->COS_out_packets[0].low;
 
 	delta  = (rx_now - tp->last_rx_count);
 	delta += (tx_now - tp->last_tx_count);
-	delta /= (ticks / RATE_SAMPLE_INTERVAL);
+	delta /= (ticks / tp->coalesce_config.rate_sample_jiffies);
 
 	tp->last_rx_count = rx_now;
 	tp->last_tx_count = tx_now;
 
 	new_vals = 0;
-	if (delta < PKT_RATE_LOW) {
-		if (tp->coalesce_config.rx_max_coalesced_frames !=
-		    LOW_RXMAX_FRAMES) {
+	do_tx = (tp->tg3_flags & TG3_FLAG_ADAPTIVE_TX) != 0;
+	do_rx = (tp->tg3_flags & TG3_FLAG_ADAPTIVE_RX) != 0;
+	if (delta < tp->coalesce_config.pkt_rate_low) {
+		if (do_rx &&
+		    tp->coalesce_config.rx_max_coalesced_frames !=
+		    tp->coalesce_config.rx_max_coalesced_frames_low) {
 			tp->coalesce_config.rx_max_coalesced_frames =
 				LOW_RXMAX_FRAMES;
 			tp->coalesce_config.rx_coalesce_ticks =
 				LOW_RXCOL_TICKS;
 			new_vals = 1;
 		}
-	} else if (delta < PKT_RATE_HIGH) {
-		if (tp->coalesce_config.rx_max_coalesced_frames !=
-		    DEFAULT_RXMAX_FRAMES) {
+		if (do_tx &&
+		    tp->coalesce_config.tx_max_coalesced_frames !=
+		    tp->coalesce_config.tx_max_coalesced_frames_low) {
+			tp->coalesce_config.tx_max_coalesced_frames =
+				tp->coalesce_config.tx_max_coalesced_frames_low;
+			tp->coalesce_config.tx_coalesce_ticks =
+				tp->coalesce_config.tx_coalesce_ticks_low;
+			new_vals = 1;
+		}
+	} else if (delta < tp->coalesce_config.pkt_rate_high) {
+		if (do_rx &&
+		    tp->coalesce_config.rx_max_coalesced_frames !=
+		    tp->coalesce_config.rx_max_coalesced_frames_def) {
 			tp->coalesce_config.rx_max_coalesced_frames =
-				DEFAULT_RXMAX_FRAMES;
+				tp->coalesce_config.rx_max_coalesced_frames_def;
 			tp->coalesce_config.rx_coalesce_ticks =
-				DEFAULT_RXCOL_TICKS;
+				tp->coalesce_config.rx_coalesce_ticks_def;
+			new_vals = 1;
+		}
+		if (do_tx &&
+		    tp->coalesce_config.tx_max_coalesced_frames !=
+		    tp->coalesce_config.tx_max_coalesced_frames_def) {
+			tp->coalesce_config.tx_max_coalesced_frames =
+				tp->coalesce_config.tx_max_coalesced_frames_def;
+			tp->coalesce_config.tx_coalesce_ticks =
+				tp->coalesce_config.tx_coalesce_ticks_def;
 			new_vals = 1;
 		}
 	} else {
-		if (tp->coalesce_config.rx_max_coalesced_frames !=
-		    HIGH_RXMAX_FRAMES) {
+		if (do_rx &&
+		    tp->coalesce_config.rx_max_coalesced_frames !=
+		    tp->coalesce_config.rx_max_coalesced_frames_high) {
 			tp->coalesce_config.rx_max_coalesced_frames =
-				HIGH_RXMAX_FRAMES;
+				tp->coalesce_config.rx_max_coalesced_frames_high;
 			tp->coalesce_config.rx_coalesce_ticks =
-				HIGH_RXCOL_TICKS;
+				tp->coalesce_config.rx_coalesce_ticks_high;
+			new_vals = 1;
+		}
+		if (do_tx &&
+		    tp->coalesce_config.tx_max_coalesced_frames !=
+		    tp->coalesce_config.tx_max_coalesced_frames_high) {
+			tp->coalesce_config.tx_max_coalesced_frames =
+				tp->coalesce_config.tx_max_coalesced_frames_high;
+			tp->coalesce_config.tx_coalesce_ticks =
+				tp->coalesce_config.tx_coalesce_ticks_high;
 			new_vals = 1;
 		}
 	}
 
 	if (new_vals) {
-		tw32(HOSTCC_RXCOL_TICKS,
-		     tp->coalesce_config.rx_coalesce_ticks);
-		tw32(HOSTCC_RXMAX_FRAMES,
-		     tp->coalesce_config.rx_max_coalesced_frames);
+		if (do_rx) {
+			tw32(HOSTCC_RXCOL_TICKS,
+			     tp->coalesce_config.rx_coalesce_ticks);
+			tw32(HOSTCC_RXMAX_FRAMES,
+			     tp->coalesce_config.rx_max_coalesced_frames);
+		}
+		if (do_tx) {
+			tw32(HOSTCC_TXCOL_TICKS,
+			     tp->coalesce_config.tx_coalesce_ticks);
+			tw32(HOSTCC_TXMAX_FRAMES,
+			     tp->coalesce_config.tx_max_coalesced_frames);
+		}
 	}
 
 	tp->last_rate_sample = jiffies;
@@ -1919,10 +1966,11 @@
 		did_pkts = 1;
 	}
 
-	if (did_pkts) {
+	if (did_pkts &&
+	    (tp->tg3_flags & (TG3_FLAG_ADAPTIVE_RX | TG3_FLAG_ADAPTIVE_TX))) {
 		unsigned long ticks = jiffies - tp->last_rate_sample;
 
-		if (ticks >= RATE_SAMPLE_INTERVAL)
+		if (ticks >= tp->coalesce_config.rate_sample_jiffies)
 			tg3_rate_sample(tp, ticks);
 	}
 }
@@ -2590,14 +2638,14 @@
 	}
 
 	/* Now allocate fresh SKBs for each rx ring. */
-	for (i = 0; i < TG3_RX_RING_PENDING; i++) {
+	for (i = 0; i < tp->rx_pending; i++) {
 		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
 				     -1, i) < 0)
 			break;
 	}
 
 #if TG3_MINI_RING_WORKS
-	for (i = 0; i < TG3_RX_MINI_RING_PENDING; i++) {
+	for (i = 0; i < tp->rx_mini_pending; i++) {
 		if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_MINI,
 				     -1, i) < 0)
 			break;
@@ -2605,7 +2653,7 @@
 #endif
 
 	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE) {
-		for (i = 0; i < TG3_RX_JUMBO_RING_PENDING; i++) {
+		for (i = 0; i < tp->rx_jumbo_pending; i++) {
 			if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
 					     -1, i) < 0)
 				break;
@@ -3420,11 +3468,11 @@
 	}
 
 	/* Setup replenish thresholds. */
-	tw32(RCVBDI_STD_THRESH, TG3_RX_RING_PENDING / 8);
+	tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
 #if TG3_MINI_RING_WORKS
-	tw32(RCVBDI_MINI_THRESH, TG3_RX_MINI_RING_PENDING / 8);
+	tw32(RCVBDI_MINI_THRESH, tp->rx_mini_pending / 8);
 #endif
-	tw32(RCVBDI_JUMBO_THRESH, TG3_RX_JUMBO_RING_PENDING / 8);
+	tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
 
 	/* Clear out send RCB ring in SRAM. */
 	for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
@@ -3462,17 +3510,17 @@
 			BDINFO_FLAGS_MAXLEN_SHIFT),
 		       0);
 
-	tp->rx_std_ptr = TG3_RX_RING_PENDING;
+	tp->rx_std_ptr = tp->rx_pending;
 	tw32_mailbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
 		     tp->rx_std_ptr);
 #if TG3_MINI_RING_WORKS
-	tp->rx_mini_ptr = TG3_RX_MINI_RING_PENDING;
+	tp->rx_mini_ptr = tp->rx_mini_pending;
 	tw32_mailbox(MAILBOX_RCV_MINI_PROD_IDX + TG3_64BIT_REG_LOW,
 		     tp->rx_mini_ptr);
 #endif
 
 	if (tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)
-		tp->rx_jumbo_ptr = TG3_RX_JUMBO_RING_PENDING;
+		tp->rx_jumbo_ptr = tp->rx_jumbo_pending;
 	else
 		tp->rx_jumbo_ptr = 0;
 	tw32_mailbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
@@ -3608,6 +3656,9 @@
 	udelay(10);
 	tw32(MAC_RX_MODE, tp->rx_mode);
 
+	if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
+		tw32(MAC_SERDES_CFG, 0x616000);
+
 	err = tg3_setup_phy(tp);
 	if (err)
 		return err;
@@ -4050,6 +4101,8 @@
 }
 #endif
 
+static struct net_device_stats *tg3_get_stats(struct net_device *);
+
 static int tg3_close(struct net_device *dev)
 {
 	struct tg3 *tp = dev->priv;
@@ -4073,6 +4126,9 @@
 
 	free_irq(dev->irq, dev);
 
+	memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
+	       sizeof(tp->net_stats_prev));
+
 	tg3_free_consistent(tp);
 
 	return 0;
@@ -4121,46 +4177,53 @@
 {
 	struct tg3 *tp = dev->priv;
 	struct net_device_stats *stats = &tp->net_stats;
+	struct net_device_stats *old_stats = &tp->net_stats_prev;
 	struct tg3_hw_stats *hw_stats = tp->hw_stats;
 
-	/* XXX Fix this... this is wrong because
-	 * XXX it means every open/close we lose the stats.
-	 */
 	if (!hw_stats)
-		return stats;
+		return old_stats;
 
-	stats->rx_packets =
+	stats->rx_packets = old_stats->rx_packets +
 		get_stat64(&hw_stats->rx_ucast_packets) +
 		get_stat64(&hw_stats->rx_mcast_packets) +
 		get_stat64(&hw_stats->rx_bcast_packets);
 		
-	stats->tx_packets =
+	stats->tx_packets = old_stats->tx_packets +
 		get_stat64(&hw_stats->COS_out_packets[0]);
 
-	stats->rx_bytes = get_stat64(&hw_stats->rx_octets);
-	stats->tx_bytes = get_stat64(&hw_stats->tx_octets);
-
-	stats->rx_errors = get_stat64(&hw_stats->rx_errors);
-	stats->tx_errors =
+	stats->rx_bytes = old_stats->rx_bytes +
+		get_stat64(&hw_stats->rx_octets);
+	stats->tx_bytes = old_stats->tx_bytes +
+		get_stat64(&hw_stats->tx_octets);
+
+	stats->rx_errors = old_stats->rx_errors +
+		get_stat64(&hw_stats->rx_errors);
+	stats->tx_errors = old_stats->tx_errors +
 		get_stat64(&hw_stats->tx_errors) +
 		get_stat64(&hw_stats->tx_mac_errors) +
 		get_stat64(&hw_stats->tx_carrier_sense_errors) +
 		get_stat64(&hw_stats->tx_discards);
 
-	stats->multicast = get_stat64(&hw_stats->rx_mcast_packets);
-	stats->collisions = get_stat64(&hw_stats->tx_collisions);
+	stats->multicast = old_stats->multicast +
+		get_stat64(&hw_stats->rx_mcast_packets);
+	stats->collisions = old_stats->collisions +
+		get_stat64(&hw_stats->tx_collisions);
 
-	stats->rx_length_errors =
+	stats->rx_length_errors = old_stats->rx_length_errors +
 		get_stat64(&hw_stats->rx_frame_too_long_errors) +
 		get_stat64(&hw_stats->rx_undersize_packets);
 
-	stats->rx_over_errors = get_stat64(&hw_stats->rxbds_empty);
-	stats->rx_frame_errors = get_stat64(&hw_stats->rx_align_errors);
-	stats->tx_aborted_errors = get_stat64(&hw_stats->tx_discards);
-	stats->tx_carrier_errors =
+	stats->rx_over_errors = old_stats->rx_over_errors +
+		get_stat64(&hw_stats->rxbds_empty);
+	stats->rx_frame_errors = old_stats->rx_frame_errors +
+		get_stat64(&hw_stats->rx_align_errors);
+	stats->tx_aborted_errors = old_stats->tx_aborted_errors +
+		get_stat64(&hw_stats->tx_discards);
+	stats->tx_carrier_errors = old_stats->tx_carrier_errors +
 		get_stat64(&hw_stats->tx_carrier_sense_errors);
 
-	stats->rx_crc_errors = calc_crc_errors(tp);
+	stats->rx_crc_errors = old_stats->rx_crc_errors +
+		calc_crc_errors(tp);
 
 	return stats;
 }
@@ -4255,16 +4318,18 @@
 	spin_unlock_irq(&tp->lock);
 }
 
+#define TG3_REGDUMP_LEN		(32 * 1024)
+
 static u8 *tg3_get_regs(struct tg3 *tp)
 {
-	u8 *orig_p = kmalloc((32 * 1024), GFP_KERNEL);
+	u8 *orig_p = kmalloc(TG3_REGDUMP_LEN, GFP_KERNEL);
 	u8 *p;
 	int i;
 
 	if (orig_p == NULL)
 		return NULL;
 
-	memset(orig_p, 0, (32 * 1024));
+	memset(orig_p, 0, TG3_REGDUMP_LEN);
 
 	spin_lock_irq(&tp->lock);
 
@@ -4320,6 +4385,177 @@
 	return orig_p;
 }
 
+static void tg3_to_ethtool_coal(struct tg3 *tp,
+				struct ethtool_coalesce *ecoal)
+{
+	ecoal->rx_coalesce_usecs =
+		tp->coalesce_config.rx_coalesce_ticks_def;
+	ecoal->rx_max_coalesced_frames =
+		tp->coalesce_config.rx_max_coalesced_frames_def;
+	ecoal->rx_coalesce_usecs_irq =
+		tp->coalesce_config.rx_coalesce_ticks_during_int_def;
+	ecoal->rx_max_coalesced_frames_irq =
+		tp->coalesce_config.rx_max_coalesced_frames_during_int_def;
+
+	ecoal->tx_coalesce_usecs =
+		tp->coalesce_config.tx_coalesce_ticks_def;
+	ecoal->tx_max_coalesced_frames =
+		tp->coalesce_config.tx_max_coalesced_frames_def;
+	ecoal->tx_coalesce_usecs_irq =
+		tp->coalesce_config.tx_coalesce_ticks_during_int_def;
+	ecoal->tx_max_coalesced_frames_irq =
+		tp->coalesce_config.tx_max_coalesced_frames_during_int_def;
+
+	ecoal->stats_block_coalesce_usecs =
+		tp->coalesce_config.stats_coalesce_ticks_def;
+
+	ecoal->use_adaptive_rx_coalesce =
+		(tp->tg3_flags & TG3_FLAG_ADAPTIVE_RX) != 0;
+	ecoal->use_adaptive_tx_coalesce =
+		(tp->tg3_flags & TG3_FLAG_ADAPTIVE_TX) != 0;
+
+	ecoal->pkt_rate_low =
+		tp->coalesce_config.pkt_rate_low;
+	ecoal->rx_coalesce_usecs_low =
+		tp->coalesce_config.rx_coalesce_ticks_low;
+	ecoal->rx_max_coalesced_frames_low =
+		tp->coalesce_config.rx_max_coalesced_frames_low;
+	ecoal->tx_coalesce_usecs_low =
+		tp->coalesce_config.tx_coalesce_ticks_low;
+	ecoal->tx_max_coalesced_frames_low =
+		tp->coalesce_config.tx_max_coalesced_frames_low;
+
+	ecoal->pkt_rate_high =
+		tp->coalesce_config.pkt_rate_high;
+	ecoal->rx_coalesce_usecs_high =
+		tp->coalesce_config.rx_coalesce_ticks_high;
+	ecoal->rx_max_coalesced_frames_high =
+		tp->coalesce_config.rx_max_coalesced_frames_high;
+	ecoal->tx_coalesce_usecs_high =
+		tp->coalesce_config.tx_coalesce_ticks_high;
+	ecoal->tx_max_coalesced_frames_high =
+		tp->coalesce_config.tx_max_coalesced_frames_high;
+
+	ecoal->rate_sample_interval =
+		tp->coalesce_config.rate_sample_jiffies / HZ;
+}
+
+static int tg3_from_ethtool_coal(struct tg3 *tp,
+				 struct ethtool_coalesce *ecoal)
+{
+	/* Make sure we are not getting garbage. */
+	if ((ecoal->rx_coalesce_usecs == 0 &&
+	     ecoal->rx_max_coalesced_frames == 0) ||
+	    (ecoal->tx_coalesce_usecs == 0 &&
+	     ecoal->tx_max_coalesced_frames == 0) ||
+	    ecoal->stats_block_coalesce_usecs == 0)
+		return -EINVAL;
+	if (ecoal->use_adaptive_rx_coalesce ||
+	    ecoal->use_adaptive_tx_coalesce) {
+		if (ecoal->pkt_rate_low > ecoal->pkt_rate_high)
+			return -EINVAL;
+		if (ecoal->rate_sample_interval == 0)
+			return -EINVAL;
+		if (ecoal->use_adaptive_rx_coalesce &&
+		    ((ecoal->rx_coalesce_usecs_low == 0 &&
+		      ecoal->rx_max_coalesced_frames_low == 0) ||
+		     (ecoal->rx_coalesce_usecs_high == 0 &&
+		      ecoal->rx_max_coalesced_frames_high == 0)))
+			return -EINVAL;
+		if (ecoal->use_adaptive_tx_coalesce &&
+		    ((ecoal->tx_coalesce_usecs_low == 0 &&
+		      ecoal->tx_max_coalesced_frames_low == 0) ||
+		     (ecoal->tx_coalesce_usecs_high == 0 &&
+		      ecoal->tx_max_coalesced_frames_high == 0)))
+			return -EINVAL;
+	}
+
+	/* Looks good, let it rip. */
+	spin_lock_irq(&tp->lock);
+	tp->coalesce_config.rx_coalesce_ticks =
+		tp->coalesce_config.rx_coalesce_ticks_def =
+		ecoal->rx_coalesce_usecs;
+	tp->coalesce_config.rx_max_coalesced_frames =
+		tp->coalesce_config.rx_max_coalesced_frames_def =
+		ecoal->rx_max_coalesced_frames;
+	tp->coalesce_config.rx_coalesce_ticks_during_int =
+		tp->coalesce_config.rx_coalesce_ticks_during_int_def =
+		ecoal->rx_coalesce_usecs_irq;
+	tp->coalesce_config.rx_max_coalesced_frames_during_int =
+		tp->coalesce_config.rx_max_coalesced_frames_during_int_def =
+		ecoal->rx_max_coalesced_frames_irq;
+	tp->coalesce_config.tx_coalesce_ticks =
+		tp->coalesce_config.tx_coalesce_ticks_def =
+		ecoal->tx_coalesce_usecs;
+	tp->coalesce_config.tx_max_coalesced_frames =
+		tp->coalesce_config.tx_max_coalesced_frames_def =
+		ecoal->tx_max_coalesced_frames;
+	tp->coalesce_config.tx_coalesce_ticks_during_int =
+		tp->coalesce_config.tx_coalesce_ticks_during_int_def =
+		ecoal->tx_coalesce_usecs_irq;
+	tp->coalesce_config.tx_max_coalesced_frames_during_int =
+		tp->coalesce_config.tx_max_coalesced_frames_during_int_def =
+		ecoal->tx_max_coalesced_frames_irq;
+	tp->coalesce_config.stats_coalesce_ticks =
+		tp->coalesce_config.stats_coalesce_ticks_def =
+		ecoal->stats_block_coalesce_usecs;
+
+	if (ecoal->use_adaptive_rx_coalesce)
+		tp->tg3_flags |= TG3_FLAG_ADAPTIVE_RX;
+	else
+		tp->tg3_flags &= ~TG3_FLAG_ADAPTIVE_RX;
+	if (ecoal->use_adaptive_tx_coalesce)
+		tp->tg3_flags |= TG3_FLAG_ADAPTIVE_TX;
+	else
+		tp->tg3_flags &= ~TG3_FLAG_ADAPTIVE_TX;
+
+	tp->coalesce_config.pkt_rate_low = ecoal->pkt_rate_low;
+	tp->coalesce_config.pkt_rate_high = ecoal->pkt_rate_high;
+	tp->coalesce_config.rate_sample_jiffies =
+		ecoal->rate_sample_interval * HZ;
+
+	tp->coalesce_config.rx_coalesce_ticks_low =
+		ecoal->rx_coalesce_usecs_low;
+	tp->coalesce_config.rx_max_coalesced_frames_low =
+		ecoal->rx_max_coalesced_frames_low;
+	tp->coalesce_config.tx_coalesce_ticks_low =
+		ecoal->tx_coalesce_usecs_low;
+	tp->coalesce_config.tx_max_coalesced_frames_low =
+		ecoal->tx_max_coalesced_frames_low;
+
+	tp->coalesce_config.rx_coalesce_ticks_high =
+		ecoal->rx_coalesce_usecs_high;
+	tp->coalesce_config.rx_max_coalesced_frames_high =
+		ecoal->rx_max_coalesced_frames_high;
+	tp->coalesce_config.tx_coalesce_ticks_high =
+		ecoal->tx_coalesce_usecs_high;
+	tp->coalesce_config.tx_max_coalesced_frames_high =
+		ecoal->tx_max_coalesced_frames_high;
+
+	tw32(HOSTCC_RXCOL_TICKS,
+	     tp->coalesce_config.rx_coalesce_ticks_def);
+	tw32(HOSTCC_RXMAX_FRAMES,
+	     tp->coalesce_config.rx_max_coalesced_frames_def);
+	tw32(HOSTCC_RXCOAL_TICK_INT,
+	     tp->coalesce_config.rx_coalesce_ticks_during_int_def);
+	tw32(HOSTCC_RXCOAL_MAXF_INT,
+	     tp->coalesce_config.rx_max_coalesced_frames_during_int_def);
+	tw32(HOSTCC_TXCOL_TICKS,
+	     tp->coalesce_config.tx_coalesce_ticks_def);
+	tw32(HOSTCC_TXMAX_FRAMES,
+	     tp->coalesce_config.tx_max_coalesced_frames_def);
+	tw32(HOSTCC_TXCOAL_TICK_INT,
+	     tp->coalesce_config.tx_coalesce_ticks_during_int_def);
+	tw32(HOSTCC_TXCOAL_MAXF_INT,
+	     tp->coalesce_config.tx_max_coalesced_frames_during_int_def);
+	tw32(HOSTCC_STAT_COAL_TICKS,
+	     tp->coalesce_config.stats_coalesce_ticks_def);
+
+	spin_unlock_irq(&tp->lock);
+
+	return 0;
+}
+
 static int tg3_ethtool_ioctl (struct net_device *dev, void *useraddr)
 {
 	struct tg3 *tp = dev->priv;
@@ -4334,7 +4570,10 @@
 		struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
 		strcpy (info.driver, DRV_MODULE_NAME);
 		strcpy (info.version, DRV_MODULE_VERSION);
+		memset(&info.fw_version, 0, sizeof(info.fw_version));
 		strcpy (info.bus_info, pci_dev->slot_name);
+		info.eedump_len = 0;
+		info.regdump_len = TG3_REGDUMP_LEN;
 		if (copy_to_user (useraddr, &info, sizeof (info)))
 			return -EFAULT;
 		return 0;
@@ -4368,8 +4607,8 @@
 		cmd.phy_address = PHY_ADDR;
 		cmd.transceiver = 0;
 		cmd.autoneg = tp->link_config.autoneg;
-		cmd.maxtxpkt = tp->coalesce_config.tx_max_coalesced_frames;
-		cmd.maxrxpkt = tp->coalesce_config.rx_max_coalesced_frames;
+		cmd.maxtxpkt = tp->coalesce_config.tx_max_coalesced_frames_def;
+		cmd.maxrxpkt = tp->coalesce_config.rx_max_coalesced_frames_def;
 		if (copy_to_user(useraddr, &cmd, sizeof(cmd)))
 			return -EFAULT;
 		return 0;
@@ -4422,9 +4661,11 @@
 		}
 
 		if (cmd.maxtxpkt || cmd.maxrxpkt) {
-			tp->coalesce_config.tx_max_coalesced_frames =
+			tp->coalesce_config.tx_max_coalesced_frames_def =
+				tp->coalesce_config.tx_max_coalesced_frames =
 				cmd.maxtxpkt;
-			tp->coalesce_config.rx_max_coalesced_frames =
+			tp->coalesce_config.rx_max_coalesced_frames_def =
+				tp->coalesce_config.rx_max_coalesced_frames =
 				cmd.maxrxpkt;
 
 			/* Coalescing config bits can be updated without
@@ -4448,8 +4689,8 @@
 
 		if (copy_from_user(&regs, useraddr, sizeof(regs)))
 			return -EFAULT;
-		if (regs.len > (32 * 1024))
-			regs.len = (32 * 1024);
+		if (regs.len > TG3_REGDUMP_LEN)
+			regs.len = TG3_REGDUMP_LEN;
 		regs.version = 0;
 		if (copy_to_user(useraddr, &regs, sizeof(regs)))
 			return -EFAULT;
@@ -4530,6 +4771,196 @@
 		if (copy_to_user(useraddr, &edata, sizeof(edata)))
 			return -EFAULT;
 	}
+	case ETHTOOL_GCOALESCE: {
+		struct ethtool_coalesce ecoal = { ETHTOOL_GCOALESCE };
+
+		tg3_to_ethtool_coal(tp, &ecoal);
+		if (copy_to_user(useraddr, &ecoal, sizeof(ecoal)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SCOALESCE: {
+		struct ethtool_coalesce ecoal;
+
+		if (copy_from_user(&ecoal, useraddr, sizeof(ecoal)))
+			return -EINVAL;
+
+		return tg3_from_ethtool_coal(tp, &ecoal);
+	}
+	case ETHTOOL_GRINGPARAM: {
+		struct ethtool_ringparam ering = { ETHTOOL_GRINGPARAM };
+
+		ering.rx_max_pending = TG3_RX_RING_SIZE - 1;
+#if TG3_MINI_RING_WORKS
+		ering.rx_mini_max_pending = TG3_RX_MINI_RING_SIZE - 1;
+#else
+		ering.rx_mini_max_pending = 0;
+#endif
+		ering.rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
+
+		ering.rx_pending = tp->rx_pending;
+#if TG3_MINI_RING_WORKS
+		ering.rx_mini_pending = tp->rx_mini_pending;
+#else
+		ering.rx_mini_pending = 0;
+#endif
+		ering.rx_jumbo_pending = tp->rx_jumbo_pending;
+		ering.tx_pending = tp->tx_pending;
+
+		if (copy_to_user(useraddr, &ering, sizeof(ering)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SRINGPARAM: {
+		struct ethtool_ringparam ering;
+
+		if (copy_from_user(&ering, useraddr, sizeof(ering)))
+			return -EFAULT;
+
+		if ((ering.rx_pending > TG3_RX_RING_SIZE - 1) ||
+#if TG3_MINI_RING_WORKS
+		    (ering.rx_mini_pending > TG3_RX_MINI_RING_SIZE - 1) ||
+#endif
+		    (ering.rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
+		    (ering.tx_pending > TG3_TX_RING_SIZE - 1))
+			return -EINVAL;
+
+		spin_lock_irq(&tp->lock);
+
+		tp->rx_pending = ering.rx_pending;
+#if TG3_MINI_RING_WORKS
+		tp->rx_mini_pending = ering.rx_mini_pending;
+#endif
+		tp->rx_jumbo_pending = ering.rx_jumbo_pending;
+		tp->tx_pending = ering.tx_pending;
+
+		tg3_halt(tp);
+		tg3_init_rings(tp);
+		tg3_init_hw(tp);
+		netif_wake_queue(tp->dev);
+		spin_unlock_irq(&tp->lock);
+
+		return 0;
+	}
+	case ETHTOOL_GPAUSEPARAM: {
+		struct ethtool_pauseparam epause = { ETHTOOL_GPAUSEPARAM };
+
+		epause.autoneg =
+			(tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
+		epause.rx_pause =
+			(tp->tg3_flags & TG3_FLAG_PAUSE_RX) != 0;
+		epause.tx_pause =
+			(tp->tg3_flags & TG3_FLAG_PAUSE_TX) != 0;
+		if (copy_to_user(useraddr, &epause, sizeof(epause)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SPAUSEPARAM: {
+		struct ethtool_pauseparam epause;
+
+		if (copy_from_user(&epause, useraddr, sizeof(epause)))
+			return -EFAULT;
+
+		spin_lock_irq(&tp->lock);
+		if (epause.autoneg)
+			tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
+		else
+			tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
+		if (epause.rx_pause)
+			tp->tg3_flags |= TG3_FLAG_PAUSE_RX;
+		else
+			tp->tg3_flags &= ~TG3_FLAG_PAUSE_RX;
+		if (epause.tx_pause)
+			tp->tg3_flags |= TG3_FLAG_PAUSE_TX;
+		else
+			tp->tg3_flags &= ~TG3_FLAG_PAUSE_TX;
+		tg3_halt(tp);
+		tg3_init_rings(tp);
+		tg3_init_hw(tp);
+		spin_unlock_irq(&tp->lock);
+
+		return 0;
+	}
+	case ETHTOOL_GRXCSUM: {
+		struct ethtool_value edata = { ETHTOOL_GRXCSUM };
+
+		edata.data =
+			(tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
+		if (copy_to_user(useraddr, &edata, sizeof(edata)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SRXCSUM: {
+		struct ethtool_value edata;
+
+		if (copy_from_user(&edata, useraddr, sizeof(edata)))
+			return -EFAULT;
+
+		if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
+			if (edata.data != 0)
+				return -EINVAL;
+			return 0;
+		}
+
+		spin_lock_irq(&tp->lock);
+		if (edata.data)
+			tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
+		else
+			tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
+		spin_unlock_irq(&tp->lock);
+
+		return 0;
+	}
+	case ETHTOOL_GTXCSUM: {
+		struct ethtool_value edata = { ETHTOOL_GTXCSUM };
+
+		edata.data =
+			(tp->dev->features & NETIF_F_IP_CSUM) != 0;
+		if (copy_to_user(useraddr, &edata, sizeof(edata)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_STXCSUM: {
+		struct ethtool_value edata;
+
+		if (copy_from_user(&edata, useraddr, sizeof(edata)))
+			return -EFAULT;
+
+		if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
+			if (edata.data != 0)
+				return -EINVAL;
+			return 0;
+		}
+
+		if (edata.data)
+			tp->dev->features |= NETIF_F_IP_CSUM;
+		else
+			tp->dev->features &= ~NETIF_F_IP_CSUM;
+
+		return 0;
+	}
+	case ETHTOOL_GSG: {
+		struct ethtool_value edata = { ETHTOOL_GSG };
+
+		edata.data =
+			(tp->dev->features & NETIF_F_SG) != 0;
+		if (copy_to_user(useraddr, &edata, sizeof(edata)))
+			return -EFAULT;
+		return 0;
+	}
+	case ETHTOOL_SSG: {
+		struct ethtool_value edata;
+
+		if (copy_from_user(&edata, useraddr, sizeof(edata)))
+			return -EFAULT;
+
+		if (edata.data)
+			tp->dev->features |= NETIF_F_SG;
+		else
+			tp->dev->features &= ~NETIF_F_SG;
+
+		return 0;
+	}
 	};
 
 	return -EOPNOTSUPP;
@@ -5126,10 +5557,10 @@
 		/* If not using tagged status, set the *_during_int
 		 * coalesce default config values to zero.
 		 */
-		tp->coalesce_config.rx_coalesce_ticks_during_int = 0;
-		tp->coalesce_config.rx_max_coalesced_frames_during_int = 0;
-		tp->coalesce_config.tx_coalesce_ticks_during_int = 0;
-		tp->coalesce_config.tx_max_coalesced_frames_during_int = 0;
+		tp->coalesce_config.rx_coalesce_ticks_during_int_def = 0;
+		tp->coalesce_config.rx_max_coalesced_frames_during_int_def = 0;
+		tp->coalesce_config.tx_coalesce_ticks_during_int_def = 0;
+		tp->coalesce_config.tx_max_coalesced_frames_during_int_def = 0;
 	}
 
 	if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
@@ -5566,20 +5997,57 @@
 
 static void __devinit tg3_init_coalesce_config(struct tg3 *tp)
 {
-	tp->coalesce_config.rx_coalesce_ticks = DEFAULT_RXCOL_TICKS;
-	tp->coalesce_config.rx_max_coalesced_frames = DEFAULT_RXMAX_FRAMES;
-	tp->coalesce_config.rx_coalesce_ticks_during_int =
+	tp->coalesce_config.rx_coalesce_ticks_def = DEFAULT_RXCOL_TICKS;
+	tp->coalesce_config.rx_max_coalesced_frames_def = DEFAULT_RXMAX_FRAMES;
+	tp->coalesce_config.rx_coalesce_ticks_during_int_def =
 		DEFAULT_RXCOAL_TICK_INT;
-	tp->coalesce_config.rx_max_coalesced_frames_during_int =
+	tp->coalesce_config.rx_max_coalesced_frames_during_int_def =
 		DEFAULT_RXCOAL_MAXF_INT;
-	tp->coalesce_config.tx_coalesce_ticks = DEFAULT_TXCOL_TICKS;
-	tp->coalesce_config.tx_max_coalesced_frames = DEFAULT_TXMAX_FRAMES;
-	tp->coalesce_config.tx_coalesce_ticks_during_int =
+	tp->coalesce_config.tx_coalesce_ticks_def = DEFAULT_TXCOL_TICKS;
+	tp->coalesce_config.tx_max_coalesced_frames_def = DEFAULT_TXMAX_FRAMES;
+	tp->coalesce_config.tx_coalesce_ticks_during_int_def =
 		DEFAULT_TXCOAL_TICK_INT;
-	tp->coalesce_config.tx_max_coalesced_frames_during_int =
+	tp->coalesce_config.tx_max_coalesced_frames_during_int_def =
 		DEFAULT_TXCOAL_MAXF_INT;
-	tp->coalesce_config.stats_coalesce_ticks =
+	tp->coalesce_config.stats_coalesce_ticks_def =
 		DEFAULT_STAT_COAL_TICKS;
+
+	tp->coalesce_config.rx_coalesce_ticks_low =
+		LOW_RXCOL_TICKS;
+	tp->coalesce_config.rx_max_coalesced_frames_low =
+		LOW_RXMAX_FRAMES;
+	tp->coalesce_config.tx_coalesce_ticks_low =
+		LOW_TXCOL_TICKS;
+	tp->coalesce_config.tx_max_coalesced_frames_low =
+		LOW_TXMAX_FRAMES;
+
+	tp->coalesce_config.rx_coalesce_ticks_high =
+		HIGH_RXCOL_TICKS;
+	tp->coalesce_config.rx_max_coalesced_frames_high =
+		HIGH_RXMAX_FRAMES;
+	tp->coalesce_config.tx_coalesce_ticks_high =
+		HIGH_TXCOL_TICKS;
+	tp->coalesce_config.tx_max_coalesced_frames_high =
+		HIGH_TXMAX_FRAMES;
+
+	/* Active == default */
+	tp->coalesce_config.rx_coalesce_ticks =
+		tp->coalesce_config.rx_coalesce_ticks_def;
+	tp->coalesce_config.rx_max_coalesced_frames =
+		tp->coalesce_config.rx_max_coalesced_frames_def;
+	tp->coalesce_config.tx_coalesce_ticks =
+		tp->coalesce_config.tx_coalesce_ticks_def;
+	tp->coalesce_config.tx_max_coalesced_frames =
+		tp->coalesce_config.tx_max_coalesced_frames_def;
+	tp->coalesce_config.stats_coalesce_ticks =
+		tp->coalesce_config.stats_coalesce_ticks_def;
+
+	tp->coalesce_config.rate_sample_jiffies = (1 * HZ);
+	tp->coalesce_config.pkt_rate_low = 22000;
+	tp->coalesce_config.pkt_rate_high = 61000;
+
+	tp->tg3_flags |= TG3_FLAG_ADAPTIVE_RX;
+	tp->tg3_flags &= ~(TG3_FLAG_ADAPTIVE_TX);
 }
 
 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
@@ -5743,6 +6211,13 @@
 
 	tg3_init_bufmgr_config(tp);
 
+	tp->rx_pending = TG3_DEF_RX_RING_PENDING;
+#if TG3_MINI_RING_WORKS
+	tp->rx_mini_pending = TG3_DEF_RX_MINI_RING_PENDING;
+#endif
+	tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
+	tp->tx_pending = TG3_DEF_TX_RING_PENDING;
+
 	dev->open = tg3_open;
 	dev->stop = tg3_close;
 	dev->get_stats = tg3_get_stats;
@@ -5777,8 +6252,11 @@
 	/* Tigon3 can do ipv4 only... and some chips have buggy
 	 * checksumming.
 	 */
-	if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0)
+	if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
 		dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
+		tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
+	} else
+		tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
 
 	err = register_netdev(dev);
 	if (err) {
diff -Nru a/drivers/net/tg3.h b/drivers/net/tg3.h
--- a/drivers/net/tg3.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/tg3.h	Fri Mar 15 17:51:01 2002
@@ -1,4 +1,4 @@
-/* $Id: tg3.h,v 1.37.2.30 2002/03/05 10:08:39 davem Exp $
+/* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
  * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
  *
  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
@@ -713,13 +713,17 @@
 #define  DEFAULT_RXCOL_TICKS		 0x00000048
 #define  HIGH_RXCOL_TICKS		 0x00000096
 #define HOSTCC_TXCOL_TICKS		0x00003c0c
+#define  LOW_TXCOL_TICKS		 0x00000096
 #define  DEFAULT_TXCOL_TICKS		 0x0000012c
+#define  HIGH_TXCOL_TICKS		 0x00000145
 #define HOSTCC_RXMAX_FRAMES		0x00003c10
 #define  LOW_RXMAX_FRAMES		 0x00000005
 #define  DEFAULT_RXMAX_FRAMES		 0x00000008
 #define  HIGH_RXMAX_FRAMES		 0x00000012
 #define HOSTCC_TXMAX_FRAMES		0x00003c14
+#define  LOW_TXMAX_FRAMES		 0x00000035
 #define  DEFAULT_TXMAX_FRAMES		 0x0000004b
+#define  HIGH_TXMAX_FRAMES		 0x00000052
 #define HOSTCC_RXCOAL_TICK_INT		0x00003c18
 #define  DEFAULT_RXCOAL_TICK_INT	 0x00000019
 #define HOSTCC_TXCOAL_TICK_INT		0x00003c1c
@@ -1681,17 +1685,42 @@
 };
 
 struct tg3_coalesce_config {
+	/* Current settings. */
 	u32		rx_coalesce_ticks;
 	u32		rx_max_coalesced_frames;
 	u32		rx_coalesce_ticks_during_int;
 	u32		rx_max_coalesced_frames_during_int;
-
 	u32		tx_coalesce_ticks;
 	u32		tx_max_coalesced_frames;
 	u32		tx_coalesce_ticks_during_int;
 	u32		tx_max_coalesced_frames_during_int;
-
 	u32		stats_coalesce_ticks;
+
+	/* Default settings. */
+	u32		rx_coalesce_ticks_def;
+	u32		rx_max_coalesced_frames_def;
+	u32		rx_coalesce_ticks_during_int_def;
+	u32		rx_max_coalesced_frames_during_int_def;
+	u32		tx_coalesce_ticks_def;
+	u32		tx_max_coalesced_frames_def;
+	u32		tx_coalesce_ticks_during_int_def;
+	u32		tx_max_coalesced_frames_during_int_def;
+	u32		stats_coalesce_ticks_def;
+
+	/* Adaptive RX/TX coalescing parameters. */
+	u32		rate_sample_jiffies;
+	u32		pkt_rate_low;
+	u32		pkt_rate_high;
+
+	u32		rx_coalesce_ticks_low;
+	u32		rx_max_coalesced_frames_low;
+	u32		tx_coalesce_ticks_low;
+	u32		tx_max_coalesced_frames_low;
+
+	u32		rx_coalesce_ticks_high;
+	u32		rx_max_coalesced_frames_high;
+	u32		tx_coalesce_ticks_high;
+	u32		tx_max_coalesced_frames_high;
 };
 
 struct tg3_bufmgr_config {
@@ -1720,6 +1749,7 @@
 	spinlock_t			indirect_lock;
 
 	struct net_device_stats		net_stats;
+	struct net_device_stats		net_stats_prev;
 	unsigned long			phy_crc_errors;
 
 	/* Adaptive coalescing engine. */
@@ -1731,9 +1761,11 @@
 	u32				tg3_flags;
 #define TG3_FLAG_HOST_TXDS		0x00000001
 #define TG3_FLAG_TXD_MBOX_HWBUG		0x00000002
-#define TG3_FLAG_BROKEN_CHECKSUMS	0x00000004
+#define TG3_FLAG_RX_CHECKSUMS		0x00000004
 #define TG3_FLAG_USE_LINKCHG_REG	0x00000008
 #define TG3_FLAG_USE_MI_INTERRUPT	0x00000010
+#define TG3_FLAG_ADAPTIVE_RX		0x00000020
+#define TG3_FLAG_ADAPTIVE_TX		0x00000040
 #define TG3_FLAG_PHY_RESET_ON_INIT	0x00000100
 #define TG3_FLAG_PCIX_TARGET_HWBUG	0x00000200
 #define TG3_FLAG_TAGGED_IRQ_STATUS	0x00000400
@@ -1751,6 +1783,10 @@
 #define TG3_FLAG_AUTONEG_DISABLE	0x00400000
 #define TG3_FLAG_JUMBO_ENABLE		0x00800000
 #define TG3_FLAG_10_100_ONLY		0x01000000
+#define TG3_FLAG_PAUSE_AUTONEG		0x02000000
+#define TG3_FLAG_PAUSE_RX		0x04000000
+#define TG3_FLAG_PAUSE_TX		0x08000000
+#define TG3_FLAG_BROKEN_CHECKSUMS	0x10000000
 #define TG3_FLAG_INIT_COMPLETE		0x80000000
 
 	u32				msg_enable;
@@ -1763,6 +1799,13 @@
 	struct tg3_link_config		link_config;
 	struct tg3_coalesce_config	coalesce_config;
 	struct tg3_bufmgr_config	bufmgr_config;
+
+	u32				rx_pending;
+#if TG3_MINI_RING_WORKS
+	u32				rx_mini_pending;
+#endif
+	u32				rx_jumbo_pending;
+	u32				tx_pending;
 
 	/* cache h/w values, often passed straight to h/w */
 	u32				rx_mode;
diff -Nru a/drivers/net/wan/Config.in b/drivers/net/wan/Config.in
--- a/drivers/net/wan/Config.in	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/wan/Config.in	Fri Mar 15 17:51:01 2002
@@ -24,6 +24,7 @@
       dep_tristate '    Support for COMX/CMX/HiCOMX boards' CONFIG_COMX_HW_COMX $CONFIG_COMX
       dep_tristate '    Support for LoCOMX board' CONFIG_COMX_HW_LOCOMX $CONFIG_COMX
       dep_tristate '    Support for MixCOM board' CONFIG_COMX_HW_MIXCOM $CONFIG_COMX
+      dep_tristate '    Support for MUNICH based boards: SliceCOM, PCICOM (WelCOM)' CONFIG_COMX_HW_MUNICH $CONFIG_COMX
       dep_tristate '    Support for HDLC and syncPPP protocols on MultiGate boards' CONFIG_COMX_PROTO_PPP $CONFIG_COMX
       if [ "$CONFIG_LAPB" = "y" ]; then
 	 dep_tristate '    Support for LAPB protocol on MultiGate boards' CONFIG_COMX_PROTO_LAPB $CONFIG_COMX
diff -Nru a/drivers/net/wan/Makefile b/drivers/net/wan/Makefile
--- a/drivers/net/wan/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/net/wan/Makefile	Fri Mar 15 17:51:01 2002
@@ -34,6 +34,7 @@
 obj-$(CONFIG_COMX_HW_COMX)	+= 				comx-hw-comx.o
 obj-$(CONFIG_COMX_HW_LOCOMX)	+= z85230.o	syncppp.o	comx-hw-locomx.o
 obj-$(CONFIG_COMX_HW_MIXCOM)	+=				comx-hw-mixcom.o
+obj-$(CONFIG_COMX_HW_MUNICH)	+=				comx-hw-munich.o
 obj-$(CONFIG_COMX_PROTO_PPP)	+=		syncppp.o	comx-proto-ppp.o
 obj-$(CONFIG_COMX_PROTO_LAPB)	+=				comx-proto-lapb.o
 obj-$(CONFIG_COMX_PROTO_FR)	+=				comx-proto-fr.o
diff -Nru a/drivers/net/wan/comx-hw-munich.c b/drivers/net/wan/comx-hw-munich.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/net/wan/comx-hw-munich.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,2872 @@
+/*
+ * Hardware-level driver for the SliceCOM board for Linux kernels 2.4.X
+ *
+ * Current maintainer / latest changes: Pasztor Szilard <don@itc.hu>
+ *
+ * Original author: Bartok Istvan <bartoki@itc.hu>
+ * Based on skeleton by Tivadar Szemethy <tiv@itc.hu>
+ *
+ * 0.51:
+ *      - port for 2.4.x
+ *	- clean up some code, make it more portable
+ *	- busted direct hardware access through mapped memory
+ *	- fix a possible race
+ *	- prevent procfs buffer overflow
+ *
+ * 0.50:
+ *	- support for the pcicom board, lots of rearrangements
+ *	- handle modem status lines
+ *
+ * 0.50a:
+ *	- fix for falc version 1.0
+ *
+ * 0.50b: T&t
+ *	- fix for bad localbus
+ */
+
+#define VERSION		"0.51"
+#define VERSIONSTR	"SliceCOM v" VERSION ", 2002/01/07\n"
+
+#include <linux/config.h>
+#include <linux/ctype.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/netdevice.h>
+#include <linux/proc_fs.h>
+#include <asm/delay.h>
+#include <asm/types.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <linux/ioport.h>
+#include <linux/pci.h>
+
+#define COMX_NEW
+
+#ifndef COMX_NEW
+#include "../include/comx.h"
+#include "../include/munich32x.h"
+#include "../include/falc-lh.h"
+#else
+#include "comx.h"
+#include "munich32x.h"
+#include "falc-lh.h"
+#endif
+
+MODULE_AUTHOR
+    ("Bartok Istvan <bartoki@itc.hu>, Gergely Madarasz <gorgo@itc.hu>, Szilard Pasztor <don@itc.hu>");
+MODULE_DESCRIPTION
+    ("Hardware-level driver for the SliceCOM and PciCOM (WelCOM) adapters");
+
+/*
+ *	TODO: az ilyenek a comxhw.h -ban szoktak lenni, idovel menjenek majd oda:
+ */
+
+#define FILENAME_BOARDNUM	"boardnum"	/* /proc/comx/comx0.1/boardnum          */
+#define FILENAME_TIMESLOTS	"timeslots"	/* /proc/comx/comx0.1/timeslots         */
+#define FILENAME_FRAMING	"framing"	/* /proc/comx/comx0.1/framing           */
+#define FILENAME_LINECODE	"linecode"	/* /proc/comx/comx0.1/linecode          */
+#define FILENAME_CLOCK_SOURCE	"clock_source"	/* /proc/comx/comx0.1/clock_source      */
+#define FILENAME_LOOPBACK	"loopback"	/* /proc/comx/comx0.1/loopback          */
+#define FILENAME_REG		"reg"		/* /proc/comx/comx0.1/reg               */
+#define FILENAME_LBIREG		"lbireg"	/* /proc/comx/comx0.1/lbireg            */
+
+#define SLICECOM_BOARDNUM_DEFAULT	0
+
+#define SLICECOM_FRAMING_CRC4		1
+#define SLICECOM_FRAMING_NO_CRC4	2
+#define SLICECOM_FRAMING_DEFAULT	SLICECOM_FRAMING_CRC4
+
+#define SLICECOM_LINECODE_HDB3		1
+#define SLICECOM_LINECODE_AMI		2
+#define SLICECOM_LINECODE_DEFAULT	SLICECOM_LINECODE_HDB3
+
+#define SLICECOM_CLOCK_SOURCE_LINE	1
+#define SLICECOM_CLOCK_SOURCE_INTERNAL	2
+#define SLICECOM_CLOCK_SOURCE_DEFAULT	SLICECOM_CLOCK_SOURCE_LINE
+
+#define SLICECOM_LOOPBACK_NONE		1
+#define SLICECOM_LOOPBACK_LOCAL		2
+#define SLICECOM_LOOPBACK_REMOTE	3
+#define SLICECOM_LOOPBACK_DEFAULT	SLICECOM_LOOPBACK_NONE
+
+#define MUNICH_VIRT(addr) (void *)(&bar1[addr])
+
+struct slicecom_stringtable
+{
+    char *name;
+    int value;
+};
+
+/* A convention: keep "default" the last not NULL when reading from /proc,
+   "error" is an indication that something went wrong, we have an undefined value */
+
+struct slicecom_stringtable slicecom_framings[] =
+{
+    {"crc4", SLICECOM_FRAMING_CRC4},
+    {"no-crc4", SLICECOM_FRAMING_NO_CRC4},
+    {"default", SLICECOM_FRAMING_DEFAULT},
+    {"error", 0}
+};
+
+struct slicecom_stringtable slicecom_linecodes[] =
+{
+    {"hdb3", SLICECOM_LINECODE_HDB3},
+    {"ami", SLICECOM_LINECODE_AMI},
+    {"default", SLICECOM_LINECODE_DEFAULT},
+    {"error", 0}
+};
+
+struct slicecom_stringtable slicecom_clock_sources[] =
+{
+    {"line", SLICECOM_CLOCK_SOURCE_LINE},
+    {"internal", SLICECOM_CLOCK_SOURCE_INTERNAL},
+    {"default", SLICECOM_CLOCK_SOURCE_DEFAULT},
+    {"error", 0}
+};
+
+struct slicecom_stringtable slicecom_loopbacks[] =
+{
+    {"none", SLICECOM_LOOPBACK_NONE},
+    {"local", SLICECOM_LOOPBACK_LOCAL},
+    {"remote", SLICECOM_LOOPBACK_REMOTE},
+    {"default", SLICECOM_LOOPBACK_DEFAULT},
+    {"error", 0}
+};
+
+/*
+ *	Some tunable values...
+ *
+ *	Note: when tuning values which change the length of text in
+ *	/proc/comx/comx[n]/status, keep in mind that it must be shorter then
+ *	PAGESIZE !
+ */
+
+#define MAX_BOARDS	4	/* ezzel 4 kartya lehet a gepben: 0..3          */
+#define RX_DESC_MAX	8	/* Rx ring size, must be >= 4                   */
+#define TX_DESC_MAX	4	/* Tx ring size, must be >= 2                   */
+				/* a sokkal hosszabb Tx ring mar ronthatja a nem-FIFO packet    */
+				/* schedulerek (fair queueing, stb.) hatekonysagat.             */
+#define MAX_WORK	10	/* TOD: update the info max. ennyi-1 esemenyt dolgoz fel egy interrupt hivasnal */
+
+/*
+ *	These are tunable too, but don't touch them without fully understanding what is happening
+ */
+
+#define UDELAY		20	/* We wait UDELAY usecs with disabled interrupts before and     */
+				/* after each command to avoid writing into each other's        */
+				/* ccb->action_spec. A _send_packet nem var, mert azt az        */
+				/* _interrupt()-bol is meghivhatja a LINE_tx()                  */
+
+/*
+ *	Just to avoid warnings about implicit declarations:
+ */
+
+static int MUNICH_close(struct net_device *dev);
+static struct comx_hardware slicecomhw;
+static struct comx_hardware pcicomhw;
+
+static unsigned long flags;
+static spinlock_t mister_lock = SPIN_LOCK_UNLOCKED;
+
+typedef volatile struct		/* Time Slot Assignment */
+{
+    u32 rxfillmask:8,		// ----------------------------+------+
+				//                             |      |
+      rxchannel:5,		// ----------------------+---+ |      |
+      rti:1,			// ---------------------+|   | |      |
+      res2:2,			// -------------------++||   | |      |
+				//                    ||||   | |      |
+      txfillmask:8,		// ----------+------+ ||||   | |      |
+				//           |      | ||||   | |      |
+      txchannel:5,		// ----+---+ |      | ||||   | |      |
+      tti:1,			// ---+|   | |      | ||||   | |      |
+      res1:2;			// -++||   | |      | ||||   | |      |
+				//   3          2          1
+    				//  10987654 32109876 54321098 76543210
+} timeslot_spec_t;
+
+typedef volatile struct		/* Receive Descriptor */
+{
+    u32 zero1:16, no:13, hi:1, hold:1, zero2:1;
+
+    u32 next;
+    u32 data;
+
+    u32 zero3:8, status:8, bno:13, zero4:1, c:1, fe:1;
+} rx_desc_t;
+
+typedef volatile struct		/* Transmit Descriptor */
+{
+    u32 fnum:11, csm:1, no13:1, zero1:2, v110:1, no:13, hi:1, hold:1, fe:1;
+
+    u32 next;
+    u32 data;
+
+} tx_desc_t;
+
+typedef volatile struct		/* Channel Specification */
+{
+    u32 iftf:1, mode:2, fa:1, trv:2, crc:1, inv:1, cs:1, tflag:7, ra:1, ro:1,
+	th:1, ta:1, to:1, ti:1, ri:1, nitbs:1, fit:1, fir:1, re:1, te:1, ch:1,
+	ifc:1, sfe:1, fe2:1;
+
+    u32 frda;
+    u32 ftda;
+
+    u32 itbs:6, zero1:26;
+
+} channel_spec_t;
+
+typedef volatile struct		/* Configuration Control Block */
+{
+    u32 action_spec;
+    u32 reserved1;
+    u32 reserved2;
+    timeslot_spec_t timeslot_spec[32];
+    channel_spec_t channel_spec[32];
+    u32 current_rx_desc[32];
+    u32 current_tx_desc[32];
+    u32 csa;			/* Control Start Address. CSA = *CCBA; CCB = *CSA */
+				/* MUNICH does it like: CCB = *( *CCBA )          */
+} munich_ccb_t;
+
+typedef volatile struct		/* Entry in the interrupt queue */
+{
+    u32 all;
+} munich_intq_t;
+
+#define MUNICH_INTQLEN	63	/* Rx/Tx Interrupt Queue Length
+				   (not the real len, but the TIQL/RIQL value)  */
+#define MUNICH_INTQMAX	( 16*(MUNICH_INTQLEN+1) )	/* Rx/Tx/Periph Interrupt Queue size in munich_intq_t's */
+#define MUNICH_INTQSIZE	( 4*MUNICH_INTQMAX )	/* Rx/Tx/Periph Interrupt Queue size in bytes           */
+
+#define MUNICH_PIQLEN	4	/* Peripheral Interrupt Queue Length. Unlike the RIQL/TIQL, */
+#define MUNICH_PIQMAX	( 4*MUNICH_PIQLEN )	/* PIQL register needs it like this                     */
+#define MUNICH_PIQSIZE	( 4*MUNICH_PIQMAX )
+
+typedef volatile u32 vol_u32;	/* TOD: ezek megszunnek ha atirom readw()/writew()-re - kész */
+typedef volatile u8 vol_u8;
+
+typedef volatile struct		/* counters of E1-errors and errored seconds, see rfc2495 */
+{
+    /* use here only unsigned ints, we depend on it when calculating the sum for the last N intervals */
+
+    unsigned line_code_violations,	/* AMI: bipolar violations, HDB3: hdb3 violations                       */
+      path_code_violations,	/* FAS errors and CRC4 errors                                                   */
+      e_bit_errors,		/* E-Bit Errors (the remote side received from us with CRC4-error) */
+      slip_secs,		/* number of seconds with (receive) Controlled Slip(s)          */
+      fr_loss_secs,		/* number of seconds an Out Of Frame defect was detected                */
+      line_err_secs,		/* number of seconds with one or more Line Code Violations              */
+      degraded_mins,		/* Degraded Minute - the estimated error rate is >1E-6, but <1E-3       */
+      errored_secs,		/* Errored Second - at least one of these happened:
+				   - Path Code Violation
+				   - Out Of Frame defect
+				   - Slip
+				   - receiving AIS
+				   - not incremented during an Unavailable Second                       */
+      bursty_err_secs,		/* Bursty Errored Second: (rfc2495 says it does not apply to E1)
+				   - Path Code Violations >1, but <320
+				   - not a Severely Errored Second
+				   - no AIS
+				   - not incremented during an Unavailabla Second                       */
+      severely_err_secs,	/* Severely Errored Second:
+				   - CRC4: >=832 Path COde Violations || >0 Out Of Frame defects
+				   - noCRC4: >=2048 Line Code Violations
+				   - not incremented during an Unavailable Second                       */
+      unavail_secs;		/* number of Unavailable Seconds. Unavailable state is said after:
+				   - 10 contiguous Severely Errored Seconds
+				   - or RAI || AIS || LOF || LOS 
+				   - (any) loopback has been set                                                */
+
+    /*
+     * we do not strictly comply to the rfc: we do not retroactively reduce errored_secs,
+     * bursty_err_secs, severely_err_secs when 'unavailable state' is reached
+     */
+
+} e1_stats_t;
+
+typedef volatile struct		/* ezek board-adatok, nem lehetnek a slicecom_privdata -ban     */
+{
+    int use_count;		/* num. of interfaces using the board                           */
+    int irq;			/* a kartya irq-ja. belemasoljuk a dev->irq -kba is, de csak hogy       */
+    /* szebb legyen az ifconfig outputja                            */
+    /* ha != 0, az azt jelenti hogy az az irq most nekunk sikeresen */
+    /* le van foglalva                                              */
+    struct pci_dev *pci;	/* a kartya PCI strukturaja. NULL, ha nincs kartya              */
+    u32 *bar1;			/* pci->base_address[0] ioremap()-ed by munich_probe(),         */
+    /* on x86 can be used both as a bus or virtual address.         */
+    /* These are the Munich's registers                             */
+    u8 *lbi;			/* pci->base_address[1] ioremap()-ed by munich_probe(),         */
+    /* this is a 256-byte range, the start of the LBI on the board  */
+    munich_ccb_t *ccb;		/* virtual address of CCB                                       */
+    munich_intq_t *tiq;		/* Tx Interrupt Queue                                           */
+    munich_intq_t *riq;		/* Rx Interrupt Queue                                           */
+    munich_intq_t *piq;		/* Peripheral Interrupt Queue (FALC interrupts arrive here)     */
+    int tiq_ptr,		/* A 'current' helyek a tiq/riq/piq -ban.                       */
+      riq_ptr,			/* amikor feldolgoztam az interruptokat, a legelso ures         */
+      piq_ptr;			/* interrupt_information szora mutatnak.                        */
+    struct net_device *twins[32];	/* MUNICH channel -> network interface assignment       */
+
+    unsigned long lastcheck;	/* When were the Rx rings last checked. Time in jiffies         */
+
+    struct timer_list modemline_timer;
+    char isx21;
+    char lineup;
+    char framing;		/* a beallitasok tarolasa                               */
+    char linecode;
+    char clock_source;
+    char loopback;
+
+    char devname[30];		/* what to show in /proc/interrupts                     */
+    unsigned histogram[MAX_WORK];	/* number of processed events in the interrupt loop     */
+    unsigned stat_pri_races;	/* number of special events, we try to handle them      */
+    unsigned stat_pti_races;
+    unsigned stat_pri_races_missed;	/* when it can not be handled, because of MAX_WORK      */
+    unsigned stat_pti_races_missed;
+
+#define SLICECOM_BOARD_INTERVALS_SIZE	97
+    e1_stats_t intervals[SLICECOM_BOARD_INTERVALS_SIZE];	/* E1 line statistics           */
+    unsigned current_interval;	/* pointer to the current interval                      */
+    unsigned elapsed_seconds;	/* elapsed seconds from the start of the current interval */
+    unsigned ses_seconds;	/* counter of contiguous Severely Errored Seconds       */
+    unsigned is_unavailable;	/* set to 1 after 10 contiguous Severely Errored Seconds */
+    unsigned no_ses_seconds;	/* contiguous Severely Error -free seconds in unavail state */
+
+    unsigned deg_elapsed_seconds;	/* for counting the 'Degraded Mins'                     */
+    unsigned deg_cumulated_errors;
+
+    struct module *owner;	/* pointer to our module to avoid module load races */
+} munich_board_t;
+
+struct slicecom_privdata
+{
+    int busy;			/* transmitter busy - number of packets in the Tx ring  */
+    int channel;		/* Munich logical channel ('channel-group' in Cisco)    */
+    unsigned boardnum;
+    u32 timeslots;		/* i-th bit means i-th timeslot is our                  */
+
+    int tx_ring_hist[TX_DESC_MAX];	/* histogram: number of packets in Tx ring when _send_packet is called  */
+
+    tx_desc_t tx_desc[TX_DESC_MAX];	/* the ring of Tx descriptors                           */
+    u8 tx_data[TX_DESC_MAX][TXBUFFER_SIZE];	/* buffers for data to transmit                 */
+    int tx_desc_ptr;		/* hanyadik descriptornal tartunk a beirassal   */
+    /* ahol ez all, oda irtunk utoljara                     */
+
+    rx_desc_t rx_desc[RX_DESC_MAX];	/* the ring of Rx descriptors                           */
+    u8 rx_data[RX_DESC_MAX][RXBUFFER_SIZE];	/* buffers for received data                            */
+    int rx_desc_ptr;		/* hanyadik descriptornal tartunk az olvasassal */
+
+    int rafutott;
+};
+
+static u32 reg, reg_ertek;	/* why static: don't write stack trash into regs if strtoul() fails */
+static u32 lbireg;
+static u8 lbireg_ertek;		/* why static: don't write stack trash into regs if strtoul() fails */
+
+static munich_board_t slicecom_boards[MAX_BOARDS];
+static munich_board_t pcicom_boards[MAX_BOARDS];
+
+/*
+ * Reprogram Idle Channel Registers in the FALC - send special code in not used channels
+ * Should be called from the open and close, when the timeslot assignment changes
+ */
+
+void rework_idle_channels(struct net_device *dev)
+{
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+    munich_board_t *board = slicecom_boards + hw->boardnum;
+    munich_ccb_t *ccb = board->ccb;
+
+    u8 *lbi = board->lbi;
+    int i, j, tmp;
+
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    for (i = 0; i < 4; i++)
+    {
+	tmp = 0xFF;
+	for (j = 0; j < 8; j++)
+	    if (ccb->timeslot_spec[8 * i + j].tti == 0) tmp ^= (0x80 >> j);
+	writeb(tmp, lbi + 0x30 + i);
+    }
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+/*
+ * Set PCM framing - /proc/comx/comx0/framing
+ */
+
+void slicecom_set_framing(int boardnum, int value)
+{
+    u8 *lbi = slicecom_boards[boardnum].lbi;
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    slicecom_boards[boardnum].framing = value;
+    switch (value)
+    {
+	case SLICECOM_FRAMING_CRC4:
+	    writeb(readb(lbi + FMR1) | 8, lbi + FMR1);
+	    writeb((readb(lbi + FMR2) & 0x3f) | 0x80, lbi + FMR2);
+	    break;
+	case SLICECOM_FRAMING_NO_CRC4:
+	    writeb(readb(lbi + FMR1) & 0xf7, lbi + FMR1);
+	    writeb(readb(lbi + FMR2) & 0x3f, lbi + FMR2);
+	    break;
+	default:
+	    printk("slicecom: board %d: unhandled " FILENAME_FRAMING
+		   " value %d\n", boardnum, value);
+    }
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+/*
+ * Set PCM linecode - /proc/comx/comx0/linecode
+ */
+
+void slicecom_set_linecode(int boardnum, int value)
+{
+    u8 *lbi = slicecom_boards[boardnum].lbi;
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    slicecom_boards[boardnum].linecode = value;
+    switch (value)
+    {
+	case SLICECOM_LINECODE_HDB3:
+	    writeb(readb(lbi + FMR0) | 0xf0, lbi + FMR0);
+	    break;
+	case SLICECOM_LINECODE_AMI:
+	    writeb((readb(lbi + FMR0) & 0x0f) | 0xa0, lbi + FMR0);
+	    break;
+	default:
+	    printk("slicecom: board %d: unhandled " FILENAME_LINECODE
+		   " value %d\n", boardnum, value);
+    }
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+/*
+ * Set PCM clock source - /proc/comx/comx0/clock_source
+ */
+
+void slicecom_set_clock_source(int boardnum, int value)
+{
+    u8 *lbi = slicecom_boards[boardnum].lbi;
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    slicecom_boards[boardnum].clock_source = value;
+    switch (value)
+    {
+	case SLICECOM_CLOCK_SOURCE_LINE:
+	    writeb(readb(lbi + LIM0) & ~1, lbi + LIM0);
+	    break;
+	case SLICECOM_CLOCK_SOURCE_INTERNAL:
+	    writeb(readb(lbi + LIM0) | 1, lbi + LIM0);
+	    break;
+	default:
+	    printk("slicecom: board %d: unhandled " FILENAME_CLOCK_SOURCE
+		   " value %d\n", boardnum, value);
+    }
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+/*
+ * Set loopbacks - /proc/comx/comx0/loopback
+ */
+
+void slicecom_set_loopback(int boardnum, int value)
+{
+    u8 *lbi = slicecom_boards[boardnum].lbi;
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    slicecom_boards[boardnum].loopback = value;
+    switch (value)
+    {
+	case SLICECOM_LOOPBACK_NONE:
+	    writeb(readb(lbi + LIM0) & ~2, lbi + LIM0);	/* Local Loop OFF  */
+	    writeb(readb(lbi + LIM1) & ~2, lbi + LIM1);	/* Remote Loop OFF */
+	    break;
+	case SLICECOM_LOOPBACK_LOCAL:
+	    writeb(readb(lbi + LIM1) & ~2, lbi + LIM1);	/* Remote Loop OFF */
+	    writeb(readb(lbi + LIM0) | 2, lbi + LIM0);	/* Local Loop ON   */
+	    break;
+	case SLICECOM_LOOPBACK_REMOTE:
+	    writeb(readb(lbi + LIM0) & ~2, lbi + LIM0);	/* Local Loop OFF  */
+	    writeb(readb(lbi + LIM1) | 2, lbi + LIM1);	/* Remote Loop ON  */
+	    break;
+	default:
+	    printk("slicecom: board %d: unhandled " FILENAME_LOOPBACK
+		   " value %d\n", boardnum, value);
+    }
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+/*
+ * Update E1 line status LEDs on the adapter
+ */
+
+void slicecom_update_leds(munich_board_t * board)
+{
+    u32 *bar1 = board->bar1;
+    u8 *lbi = board->lbi;
+    u8 frs0;
+    u32 leds;
+    int i;
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    leds = 0;
+    frs0 = readb(lbi + FRS0);	/* FRS0 bits described on page 137 */
+
+    if (!(frs0 & 0xa0))
+    {
+	leds |= 0x2000;		/* Green LED: Input signal seems to be OK, no LOS, no LFA       */
+	if (frs0 & 0x10)
+	    leds |= 0x8000;	/* Red LED: Receiving Remote Alarm                                      */
+    }
+    writel(leds, MUNICH_VIRT(GPDATA));
+
+    if (leds == 0x2000 && !board->lineup)
+    {				/* line up */
+	board->lineup = 1;
+	for (i = 0; i < 32; i++)
+	{
+	    if (board->twins[i] && (board->twins[i]->flags & IFF_RUNNING))
+	    {
+		struct comx_channel *ch = board->twins[i]->priv;
+
+		if (!test_and_set_bit(0, &ch->lineup_pending))
+		{
+		    ch->lineup_timer.function = comx_lineup_func;
+		    ch->lineup_timer.data = (unsigned long)board->twins[i];
+		    ch->lineup_timer.expires = jiffies + HZ * ch->lineup_delay;
+		    add_timer(&ch->lineup_timer);
+		}
+	    }
+	}
+    }
+    else if (leds != 0x2000 && board->lineup)
+    {				/* line down */
+	board->lineup = 0;
+	for (i = 0; i < 32; i++)
+	    if (board->twins[i] && (board->twins[i]->flags & IFF_RUNNING))
+	    {
+		struct comx_channel *ch = board->twins[i]->priv;
+
+		if (test_and_clear_bit(0, &ch->lineup_pending))
+		    del_timer(&ch->lineup_timer);
+		else if (ch->line_status & LINE_UP)
+		{
+		    ch->line_status &= ~LINE_UP;
+		    if (ch->LINE_status)
+			ch->LINE_status(board->twins[i], ch->line_status);
+		}
+	    }
+    }
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+/*
+ * This function gets called every second when the FALC issues the interrupt.
+ * Hardware counters contain error counts for last 1-second time interval.
+ * We add them to the global counters here.
+ * Read rfc2495 to understand this.
+ */
+
+void slicecom_update_line_counters(munich_board_t * board)
+{
+    e1_stats_t *curr_int = &board->intervals[board->current_interval];
+
+    u8 *lbi = board->lbi;
+
+    unsigned framing_errors, code_violations, path_code_violations, crc4_errors,
+	e_bit_errors;
+    unsigned slip_detected,	/* this one has logical value, not the number of slips! */
+      out_of_frame_defect,	/* logical value        */
+      ais_defect,		/* logical value        */
+      errored_sec, bursty_err_sec, severely_err_sec = 0, failure_sec;
+    u8 isr2, isr3, isr5, frs0;
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    isr2 = readb(lbi + ISR2);	/* ISR0-5 described on page 156     */
+    isr3 = readb(lbi + ISR3);
+    isr5 = readb(lbi + ISR5);
+    frs0 = readb(lbi + FRS0);	/* FRS0 described on page 137       */
+
+    /* Error Events: */
+
+    code_violations = readb(lbi + CVCL) + (readb(lbi + CVCH) << 8);
+    framing_errors = readb(lbi + FECL) + (readb(lbi + FECH) << 8);
+    crc4_errors = readb(lbi + CEC1L) + (readb(lbi + CEC1H) << 8);
+    e_bit_errors = readb(lbi + EBCL) + (readb(lbi + EBCH) << 8);
+    slip_detected = isr3 & (ISR3_RSN | ISR3_RSP);
+
+    path_code_violations = framing_errors + crc4_errors;
+
+    curr_int->line_code_violations += code_violations;
+    curr_int->path_code_violations += path_code_violations;
+    curr_int->e_bit_errors += e_bit_errors;
+
+    /* Performance Defects: */
+
+    /* there was an LFA in the last second, but maybe disappeared: */
+    out_of_frame_defect = (isr2 & ISR2_LFA) || (frs0 & FRS0_LFA);
+
+    /* there was an AIS in the last second, but maybe disappeared: */
+    ais_defect = (isr2 & ISR2_AIS) || (frs0 & FRS0_AIS);
+
+    /* Performance Parameters: */
+
+    if (out_of_frame_defect)
+	curr_int->fr_loss_secs++;
+    if (code_violations)
+	curr_int->line_err_secs++;
+
+    errored_sec = ((board->framing == SLICECOM_FRAMING_NO_CRC4) &&
+		   (code_violations)) || path_code_violations ||
+	out_of_frame_defect || slip_detected || ais_defect;
+
+    bursty_err_sec = !out_of_frame_defect && !ais_defect &&
+	(path_code_violations > 1) && (path_code_violations < 320);
+
+    switch (board->framing)
+    {
+	case SLICECOM_FRAMING_CRC4:
+	    severely_err_sec = out_of_frame_defect ||
+		(path_code_violations >= 832);
+	    break;
+	case SLICECOM_FRAMING_NO_CRC4:
+	    severely_err_sec = (code_violations >= 2048);
+	    break;
+    }
+
+    /*
+     * failure_sec: true if there was a condition leading to a failure
+     * (and leading to unavailable state) in this second:
+     */
+
+    failure_sec = (isr2 & ISR2_RA) || (frs0 & FRS0_RRA)	/* Remote/Far End/Distant Alarm Failure */
+	|| ais_defect || out_of_frame_defect	/* AIS or LOF Failure                           */
+	|| (isr2 & ISR2_LOS) || (frs0 & FRS0_LOS)	/* Loss Of Signal Failure                       */
+	|| (board->loopback != SLICECOM_LOOPBACK_NONE);	/* Loopback has been set                        */
+
+    if (board->is_unavailable)
+    {
+	if (severely_err_sec)
+	    board->no_ses_seconds = 0;
+	else
+	    board->no_ses_seconds++;
+
+	if ((board->no_ses_seconds >= 10) && !failure_sec)
+	{
+	    board->is_unavailable = 0;
+	    board->ses_seconds = 0;
+	    board->no_ses_seconds = 0;
+	}
+    }
+    else
+    {
+	if (severely_err_sec)
+	    board->ses_seconds++;
+	else
+	    board->ses_seconds = 0;
+
+	if ((board->ses_seconds >= 10) || failure_sec)
+	{
+	    board->is_unavailable = 1;
+	    board->ses_seconds = 0;
+	    board->no_ses_seconds = 0;
+	}
+    }
+
+    if (board->is_unavailable)
+	curr_int->unavail_secs++;
+    else
+    {
+	if (slip_detected)
+	    curr_int->slip_secs++;
+	curr_int->errored_secs += errored_sec;
+	curr_int->bursty_err_secs += bursty_err_sec;
+	curr_int->severely_err_secs += severely_err_sec;
+    }
+
+    /* the RFC does not say clearly which errors to count here, we try to count bit errors */
+
+    if (!board->is_unavailable && !severely_err_sec)
+    {
+	board->deg_cumulated_errors += code_violations;
+	board->deg_elapsed_seconds++;
+	if (board->deg_elapsed_seconds >= 60)
+	{
+	    if (board->deg_cumulated_errors >= 123)
+		curr_int->degraded_mins++;
+	    board->deg_cumulated_errors = 0;
+	    board->deg_elapsed_seconds = 0;
+	}
+
+    }
+
+    board->elapsed_seconds++;
+    if (board->elapsed_seconds >= 900)
+    {
+	board->current_interval =
+	    (board->current_interval + 1) % SLICECOM_BOARD_INTERVALS_SIZE;
+	memset((void *)&board->intervals[board->current_interval], 0,
+	       sizeof(e1_stats_t));
+	board->elapsed_seconds = 0;
+    }
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+}
+
+static void pcicom_modemline(unsigned long b)
+{
+    munich_board_t *board = (munich_board_t *) b;
+    struct net_device *dev = board->twins[0];
+    struct comx_channel *ch = dev->priv;
+    unsigned long regs;
+
+    regs = readl((void *)(&board->bar1[GPDATA]));
+    if ((ch->line_status & LINE_UP) && (regs & 0x0800))
+    {
+	ch->line_status &= ~LINE_UP;
+	board->lineup = 0;
+	if (ch->LINE_status)
+	{
+	    ch->LINE_status(dev, ch->line_status);
+	}
+    }
+
+    if (!(ch->line_status & LINE_UP) && !(regs & 0x0800))
+    {
+	ch->line_status |= LINE_UP;
+	board->lineup = 1;
+	if (ch->LINE_status)
+	{
+	    ch->LINE_status(dev, ch->line_status);
+	}
+    }
+
+    mod_timer((struct timer_list *)&board->modemline_timer, jiffies + HZ);
+}
+
+/* 
+ * Is it possible to transmit ?
+ * Called (may be called) by the protocol layer 
+ */
+
+static int MUNICH_txe(struct net_device *dev)
+{
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+
+    return (hw->busy < TX_DESC_MAX - 1);
+}
+
+/* 
+ * Hw probe function. Detects all the boards in the system,
+ * and fills up slicecom_boards[] and pcicom_boards[]
+ * Returns 0 on success.
+ * We do not disable interrupts!
+ */
+static int munich_probe(void)
+{
+    struct pci_dev *pci;
+    int boardnum;
+    int slicecom_boardnum;
+    int pcicom_boardnum;
+    u32 *bar1;
+    u8 *lbi;
+    munich_board_t *board;
+
+    for (boardnum = 0; boardnum < MAX_BOARDS; boardnum++)
+    {
+	pcicom_boards[boardnum].pci = 0;
+	pcicom_boards[boardnum].bar1 = 0;
+	pcicom_boards[boardnum].lbi = 0;
+	slicecom_boards[boardnum].pci = 0;
+	slicecom_boards[boardnum].bar1 = 0;
+	slicecom_boards[boardnum].lbi = 0;
+    }
+
+    pci = NULL;
+    board = NULL;
+    slicecom_boardnum = 0;
+    pcicom_boardnum = 0;
+
+    for (boardnum = 0;
+	boardnum < MAX_BOARDS && (pci = pci_find_device(PCI_VENDOR_ID_SIEMENS,
+	PCI_DEVICE_ID_SIEMENS_MUNICH32X, pci)); boardnum++)
+    {
+	if (pci_enable_device(pci))
+	    continue;
+
+	printk("munich_probe: munich chip found, IRQ %d\n", pci->irq);
+
+#if (LINUX_VERSION_CODE < 0x02030d)
+	bar1 = ioremap_nocache(pci->base_address[0], 0x100);
+	lbi = ioremap_nocache(pci->base_address[1], 0x100);
+#else
+	bar1 = ioremap_nocache(pci->resource[0].start, 0x100);
+	lbi = ioremap_nocache(pci->resource[1].start, 0x100);
+#endif
+
+	if (bar1 && lbi)
+	{
+	    pci_write_config_dword(pci, MUNICH_PCI_PCIRES, 0xe0000);
+	    set_current_state(TASK_UNINTERRUPTIBLE);
+	    schedule_timeout(1);
+	    pci_write_config_dword(pci, MUNICH_PCI_PCIRES, 0);
+	    set_current_state(TASK_UNINTERRUPTIBLE);
+	    schedule_timeout(1);
+	    /* check the type of the card */
+	    writel(LREG0_MAGIC, MUNICH_VIRT(LREG0));
+	    writel(LREG1_MAGIC, MUNICH_VIRT(LREG1));
+	    writel(LREG2_MAGIC, MUNICH_VIRT(LREG2));
+	    writel(LREG3_MAGIC, MUNICH_VIRT(LREG3));
+	    writel(LREG4_MAGIC, MUNICH_VIRT(LREG4));
+	    writel(LREG5_MAGIC, MUNICH_VIRT(LREG5));
+	    writel(LCONF_MAGIC2,MUNICH_VIRT(LCONF));	/* enable the DMSM */
+
+	    if ((readb(lbi + VSTR) == 0x13) || (readb(lbi + VSTR) == 0x10))
+	    {
+		board = slicecom_boards + slicecom_boardnum;
+		sprintf((char *)board->devname, "slicecom%d",
+			slicecom_boardnum);
+		board->isx21 = 0;
+		slicecom_boardnum++;
+	    }
+	    else if ((readb(lbi + VSTR) == 0x6) || (readb(lbi + GIS) == 0x6))
+	    {
+		board = pcicom_boards + pcicom_boardnum;
+		sprintf((char *)board->devname, "pcicom%d", pcicom_boardnum);
+		board->isx21 = 1;
+		pcicom_boardnum++;
+	    }
+	    if (board)
+	    {
+		printk("munich_probe: %s board found\n", board->devname);
+		writel(LCONF_MAGIC1, MUNICH_VIRT(LCONF));	/* reset the DMSM */
+		board->pci = pci;
+		board->bar1 = bar1;
+		board->lbi = lbi;
+		board->framing = SLICECOM_FRAMING_DEFAULT;
+		board->linecode = SLICECOM_LINECODE_DEFAULT;
+		board->clock_source = SLICECOM_CLOCK_SOURCE_DEFAULT;
+		board->loopback = SLICECOM_LOOPBACK_DEFAULT;
+		SET_MODULE_OWNER(board);
+	    }
+	    else
+	    {
+		printk("munich_probe: Board error, VSTR: %02X\n",
+		       readb(lbi + VSTR));
+		iounmap((void *)bar1);
+		iounmap((void *)lbi);
+	    }
+	}
+	else
+	{
+	    printk("munich_probe: ioremap() failed, not enabling this board!\n");
+	    /* .pci = NULL, so the MUNICH_open will not try to open it            */
+	    if (bar1) iounmap((void *)bar1);
+	    if (lbi) iounmap((void *)lbi);
+	}
+    }
+
+    if (!pci && !boardnum)
+    {
+	printk("munich_probe: no PCI present!\n");
+	return -ENODEV;
+    }
+
+    if (pcicom_boardnum + slicecom_boardnum == 0)
+    {
+	printk
+	    ("munich_probe: Couldn't find any munich board: vendor:device %x:%x not found\n",
+	     PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_MUNICH32X);
+	return -ENODEV;
+    }
+
+    /* Found some */
+    if (pcicom_boardnum)
+	printk("%d pcicom board(s) found.\n", pcicom_boardnum);
+    if (slicecom_boardnum)
+	printk("%d slicecom board(s) found.\n", slicecom_boardnum);
+
+    return 0;
+}
+
+/* 
+ * Reset the hardware. Get called only from within this module if needed.
+ */
+#if 0
+static int slicecom_reset(struct net_device *dev)
+{
+    struct comx_channel *ch = dev->priv;
+
+    printk("slicecom_reset: resetting the hardware\n");
+
+    /* Begin to reset the hardware */
+
+    if (ch->HW_set_clock)
+	ch->HW_set_clock(dev);
+
+    /* And finish it */
+
+    return 0;
+}
+#endif
+
+/* 
+ * Transmit a packet. 
+ * Called by the protocol layer
+ * Return values:	
+ *	FRAME_ACCEPTED:	frame is being transmited, transmitter is busy
+ *	FRAME_QUEUED:	frame is being transmitted, there's more room in
+ *				the transmitter for additional packet(s)
+ *	FRAME_ERROR:
+ *	FRAME_DROPPED:	there was some error
+ */
+
+static int MUNICH_send_packet(struct net_device *dev, struct sk_buff *skb)
+{
+    struct comx_channel *ch = (struct comx_channel *)dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+
+    /* Send it to the debug facility too if needed: */
+
+    if (ch->debug_flags & DEBUG_HW_TX)
+	comx_debug_bytes(dev, skb->data, skb->len, "MUNICH_send_packet");
+
+    /* If the line is inactive, don't accept: */
+
+    /* TODO: atgondolni hogy mi is legyen itt */
+    /* if (!(ch->line_status & LINE_UP)) return FRAME_DROPPED; */
+
+    /* More check, to be sure: */
+
+    if (skb->len > TXBUFFER_SIZE)
+    {
+	ch->stats.tx_errors++;
+	kfree_skb(skb);
+	return FRAME_ERROR;
+    }
+
+    /* Maybe you have to disable irq's while programming the hw: */
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    /* And more check: */
+
+    if (hw->busy >= TX_DESC_MAX - 1)
+    {
+	printk(KERN_ERR
+	       "%s: Transmitter called while busy... dropping frame, busy = %d\n",
+	       dev->name, hw->busy);
+	spin_unlock_irqrestore(&mister_lock, flags);
+	kfree_skb(skb);
+	return FRAME_DROPPED;
+    }
+
+    if (hw->busy >= 0)
+	hw->tx_ring_hist[hw->busy]++;
+    /* DELL: */
+    else
+	printk("slicecom: %s: FATAL: busy = %d\n", dev->name, hw->busy);
+
+//              /* DEL: */
+//      printk("slicecom: %s: _send_packet called, busy = %d\n", dev->name, hw->busy );
+
+    /* Packet can go, update stats: */
+
+    ch->stats.tx_packets++;
+    ch->stats.tx_bytes += skb->len;
+
+    /* Pass the packet to the HW:                   */
+    /* Step forward with the transmit descriptors:  */
+
+    hw->tx_desc_ptr = (hw->tx_desc_ptr + 1) % TX_DESC_MAX;
+
+    memcpy(&(hw->tx_data[hw->tx_desc_ptr][0]), skb->data, skb->len);
+    hw->tx_desc[hw->tx_desc_ptr].no = skb->len;
+
+    /* We don't issue any command, just step with the HOLD bit      */
+
+    hw->tx_desc[hw->tx_desc_ptr].hold = 1;
+    hw->tx_desc[(hw->tx_desc_ptr + TX_DESC_MAX - 1) % TX_DESC_MAX].hold = 0;
+
+#ifdef COMX_NEW
+    dev_kfree_skb(skb);
+#endif
+    /* csomag kerult a Tx ringbe: */
+
+    hw->busy++;
+
+    /* Report it: */
+
+    if (ch->debug_flags & DEBUG_HW_TX)
+	comx_debug(dev, "%s: MUNICH_send_packet was successful\n\n", dev->name);
+
+    if (hw->busy >= TX_DESC_MAX - 1)
+    {
+	spin_unlock_irqrestore(&mister_lock, flags);
+	return FRAME_ACCEPTED;
+    }
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    /* All done */
+
+    return FRAME_QUEUED;
+}
+
+/*
+ * Interrupt handler routine.
+ * Called by the Linux kernel.
+ * BEWARE! The interrupts are enabled on the call!
+ */
+static void MUNICH_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+    struct sk_buff *skb;
+    int length;
+    int rx_status;
+    int work;			/* hany esemenyt kezeltem mar le                                */
+    u32 *bar1;
+    u8 *lbi;
+    u32 stat,			/* az esemenyek, amiket a ebben a loop korben le kell meg kezelni       */
+      race_stat = 0,		/* race eseten ebben uzenek magamnak hogy mit kell meg lekezelni        */
+      ack;			/* ezt fogom a vegen a STAT-ba irni, kiveszek belole 1-1 bitet ha       */
+
+    /* az adott dolgot nem kell ack-olni mert volt vele munkam, es  */
+    /* legjobb ha visszaterek ide megegyszer                        */
+    munich_intq_t int_info;
+
+    struct net_device *dev;
+    struct comx_channel *ch;
+    struct slicecom_privdata *hw;
+    munich_board_t *board = (munich_board_t *) dev_id;
+    int channel;
+
+    //      , boardnum = (int)dev_id;
+
+    // board = munich_boards + boardnum;
+    bar1 = board->bar1;
+    lbi = board->lbi;
+
+    //      Do not uncomment this under heavy load! :->
+    //      printk("MUNICH_interrupt: masked STAT=0x%08x, tiq=0x%08x, riq=0x%08x, piq=0x%08x\n", stat, board->tiq[0].all, board->riq[0].all, board->piq[0].all );
+
+    for (work = 0; (stat = (race_stat | (readl(MUNICH_VIRT(STAT)) & ~STAT_NOT_HANDLED_BY_INTERRUPT))) && (work < MAX_WORK - 1); work++)
+    {
+	ack = stat & (STAT_PRI | STAT_PTI | STAT_LBII);
+
+	/* Handle the interrupt information in the Rx queue. We don't really trust      */
+	/* info from this queue, because it can be overflowed, so later check           */
+	/* every Rx ring for received packets. But there are some errors which can't    */
+	/* be counted from the Rx rings, so we parse it.                                        */
+
+	int_info = board->riq[board->riq_ptr];
+	if (int_info.all & 0xF0000000)	/* ha ez nem 0, akkor itt interrupt_info van                    */
+	{
+	    ack &= ~STAT_PRI;	/* don't ack the interrupt, we had some work to do              */
+
+	    channel = PCM_INT_CHANNEL(int_info.all);
+	    dev = board->twins[channel];
+
+	    if (dev == NULL)
+	    {
+		printk
+		    ("MUNICH_interrupt: got an Rx interrupt info for NULL device "
+		     "%s.twins[%d], int_info = 0x%08x\n", board->devname,
+		     channel, int_info.all);
+		goto go_for_next_interrupt;
+	    }
+
+	    ch = (struct comx_channel *)dev->priv;
+	    hw = (struct slicecom_privdata *)ch->HW_privdata;
+
+	    //      printk("Rx STAT=0x%08x int_info=0x%08x rx_desc_ptr=%d rx_desc.status=0x%01x\n",
+	    //              stat, int_info.all, hw->rx_desc_ptr, hw->rx_desc[ hw->rx_desc_ptr ].status );
+
+	    if (int_info.all & PCM_INT_HI)
+		printk("SliceCOM: %s: Host Initiated interrupt\n", dev->name);
+	    if (int_info.all & PCM_INT_IFC)
+		printk("SliceCOM: %s: Idle/Flag Change\n", dev->name);
+	    /* TOD: jo ez az Idle/Flag Change valamire? - azonnal latszik belole hogy mikor ad a masik oldal */
+	    /* TOD: ilyen IT most nem is jon, mert ki van maszkolva az interrupt, biztosan kell ez? */
+
+	    if (int_info.all & PCM_INT_FO)
+		/* Internal buffer (RB) overrun */
+		ch->stats.rx_over_errors++;	/* TOD: Ez azt jelenti hogy a belso RB nem volt hozzaferheto, es ezert kihagyott valamit. De nem csak csomag lehetett, hanem esemeny, stb. is. lasd page 247. Ezzel a 'cat status'-hoz igazodok, de a netdevice.h szerint nem egyertelmu hogy ide ez kellene. Nem lehet hogy rx_missed ? */
+		/* DE: nem gotozok sehova, elvileg jo igy */
+		/* kesobb meg visszaterek az FO-ra, ha packet-FO volt. Keresd a "packet-FO"-t. */
+	    if (int_info.all & PCM_INT_FI)	/* frame received, but we do not trust the int_info queue       */
+		if (int_info.all & PCM_INT_SF)
+		{		/* Short Frame: rovidebb mint a CRC */
+		    /* "rovidebb mint CRC+2byte" vizsgalat a "CRC+2"-nel */
+		    ch->stats.rx_length_errors++;	/* TOD: noveljem? ne noveljem? */
+		    goto go_for_next_interrupt;
+		}
+
+	    go_for_next_interrupt:	/* One step in the interrupt queue */
+	    board->riq[board->riq_ptr].all = 0;	/* megjelolom hogy itt meg nem jart a hw */
+	    board->riq_ptr = (board->riq_ptr + 1) % MUNICH_INTQMAX;
+
+	}
+
+	/* Check every Rx ring for incomed packets: */
+
+	for (channel = 0; channel < 32; channel++)
+	{
+	    dev = board->twins[channel];
+
+	    if (dev != NULL)
+	    {
+		ch = (struct comx_channel *)dev->priv;
+		hw = (struct slicecom_privdata *)ch->HW_privdata;
+
+		rx_status = hw->rx_desc[hw->rx_desc_ptr].status;
+
+		if (!(rx_status & 0x80))	/* mar jart itt a hardver */
+		{
+		    ack &= ~STAT_PRI;	/* Don't ack, we had some work          */
+
+		    /* Ez most egy kicsit zuros, mert itt mar nem latom az int_infot        */
+		    if (rx_status & RX_STATUS_ROF)
+			ch->stats.rx_over_errors++;	/* TOD: 'cat status'-hoz igazodok */
+
+		    if (rx_status & RX_STATUS_RA)
+			/* Abort received or issued on channel  */
+			ch->stats.rx_frame_errors++;	/* or HOLD bit in the descriptor                */
+			/* TOD: 'cat status'-hoz igazodok */
+
+		    if (rx_status & RX_STATUS_LFD)
+		    {		/* Long Frame (longer then MFL in the MODE1) */
+			ch->stats.rx_length_errors++;
+			goto go_for_next_frame;
+		    }
+
+		    if (rx_status & RX_STATUS_NOB)
+		    {		/* Not n*8 bits long frame - frame alignment */
+			ch->stats.rx_frame_errors++;	/* ez viszont nem igazodik a 'cat status'-hoz */
+			goto go_for_next_frame;
+		    }
+
+		    if (rx_status & RX_STATUS_CRCO)
+		    {		/* CRC error */
+			ch->stats.rx_crc_errors++;
+			goto go_for_next_frame;
+		    }
+
+		    if (rx_status & RX_STATUS_SF)
+		    {		/* Short Frame: rovidebb mint CRC+2byte */
+			ch->stats.rx_errors++;	/* The HW does not set PCI_INT_ERR bit for this one, see page 246 */
+			ch->stats.rx_length_errors++;
+			goto go_for_next_frame;
+		    }
+
+		    if (rx_status != 0)
+		    {
+			printk("SliceCOM: %s: unhandled rx_status: 0x%02x\n",
+			       dev->name, rx_status);
+			goto go_for_next_frame;
+		    }
+
+		    /* frame received without errors: */
+
+		    length = hw->rx_desc[hw->rx_desc_ptr].bno;
+		    ch->stats.rx_packets++;	/* Count only 'good' packets */
+		    ch->stats.rx_bytes += length;
+
+		    /* Allocate a larger skb and reserve the heading for efficiency: */
+
+		    if ((skb = dev_alloc_skb(length + 16)) == NULL)
+		    {
+			ch->stats.rx_dropped++;
+			goto go_for_next_frame;
+		    }
+
+		    /* Do bookkeeping: */
+
+		    skb_reserve(skb, 16);
+		    skb_put(skb, length);
+		    skb->dev = dev;
+
+		    /* Now copy the data into the buffer: */
+
+		    memcpy(skb->data, &(hw->rx_data[hw->rx_desc_ptr][0]), length);
+
+		    /* DEL: UGLY HACK!!!! */
+		    if (*((int *)skb->data) == 0x02000000 &&
+			*(((int *)skb->data) + 1) == 0x3580008f)
+		    {
+			printk("%s: swapping hack\n", dev->name);
+			*((int *)skb->data) = 0x3580008f;
+			*(((int *)skb->data) + 1) = 0x02000000;
+		    }
+
+		    if (ch->debug_flags & DEBUG_HW_RX)
+			comx_debug_skb(dev, skb, "MUNICH_interrupt receiving");
+
+		    /* Pass it to the protocol entity: */
+
+		    ch->LINE_rx(dev, skb);
+
+		    go_for_next_frame:
+		    /* DEL: rafutott-e a HOLD bitre -detektalas */
+		    {
+			if( ((rx_desc_t*)phys_to_virt(board->ccb->current_rx_desc[channel]))->hold
+			    && ((rx_desc_t*)phys_to_virt(board->ccb->current_rx_desc[channel]))->status != 0xff)
+			    hw->rafutott++;	/* rafutott: hanyszor volt olyan hogy a current descriptoron HOLD bit volt, es a hw mar befejezte az irast (azaz a hw rafutott a HOLD bitre) */
+		    }
+
+		    //      if( jiffies % 2 )               /* DELL: okozzunk egy kis Rx ring slipet :) */
+		    //      {
+		    /* Step forward with the receive descriptors: */
+		    /* if you change this, change the copy of it below too! Search for: "RxSlip" */
+		    hw->rx_desc[(hw->rx_desc_ptr + RX_DESC_MAX - 1) % RX_DESC_MAX].hold = 1;
+		    hw->rx_desc[hw->rx_desc_ptr].status = 0xFF;	/* megjelolom hogy itt meg nem jart a hw */
+		    hw->rx_desc[(hw->rx_desc_ptr + RX_DESC_MAX - 2) % RX_DESC_MAX].hold = 0;
+		    hw->rx_desc_ptr = (hw->rx_desc_ptr + 1) % RX_DESC_MAX;
+		    //      }
+		}
+	    }
+	}
+
+	stat &= ~STAT_PRI;
+
+//      }
+
+//      if( stat & STAT_PTI )   /* TOD: primko megvalositas: mindig csak egy esemenyt dolgozok fel, */
+	/* es nem torlom a STAT-ot, ezert ujra visszajon ide a rendszer. Amikor */
+	/* jon interrupt, de nincs mit feldolgozni, akkor torlom a STAT-ot.     */
+	/* 'needs a rewrite', de elso megoldasnak jo lesz                       */
+//              {
+
+udelay(10000);
+	int_info = board->tiq[board->tiq_ptr];
+	if (int_info.all & 0xF0000000)	/* ha ez nem 0, akkor itt interrupt_info van    */
+	{
+	    ack &= ~STAT_PTI;	/* don't ack the interrupt, we had some work to do      */
+
+	    channel = PCM_INT_CHANNEL(int_info.all);
+	    dev = board->twins[channel];
+
+	    if (dev == NULL)
+	    {
+		printk("MUNICH_interrupt: got a Tx interrupt for NULL device "
+		       "%s.twins[%d], int_info = 0x%08x\n",
+		       board->isx21 ? "pcicom" : "slicecom", channel, int_info.all);
+		goto go_for_next_tx_interrupt;
+	    }
+
+	    ch = (struct comx_channel *)dev->priv;
+	    hw = (struct slicecom_privdata *)ch->HW_privdata;
+
+	    //      printk("Tx STAT=0x%08x int_info=0x%08x tiq_ptr=%d\n", stat, int_info.all, board->tiq_ptr );
+
+	    if (int_info.all & PCM_INT_FE2)
+	    {			/* "Tx available"                               */
+		/* do nothing */
+	    }
+	    else if (int_info.all & PCM_INT_FO)
+	    {			/* Internal buffer (RB) overrun */
+		ch->stats.rx_over_errors++;
+	    }
+	    else
+	    {
+		printk("slicecom: %s: unhandled Tx int_info: 0x%08x\n",
+		       dev->name, int_info.all);
+	    }
+
+	    go_for_next_tx_interrupt:
+	    board->tiq[board->tiq_ptr].all = 0;
+	    board->tiq_ptr = (board->tiq_ptr + 1) % MUNICH_INTQMAX;
+	}
+
+	/* Check every Tx ring for incoming packets: */
+
+	for (channel = 0; channel < 32; channel++)
+	{
+	    dev = board->twins[channel];
+
+	    if (dev != NULL)
+	    {
+		int newbusy;
+
+		ch = (struct comx_channel *)dev->priv;
+		hw = (struct slicecom_privdata *)ch->HW_privdata;
+
+		/* We dont trust the "Tx available" info from the TIQ, but check        */
+		/* every ring if there is some free room                                        */
+
+		if (ch->init_status && netif_running(dev))
+		{
+		    newbusy = ( TX_DESC_MAX + (& hw->tx_desc[ hw->tx_desc_ptr ]) -
+			(tx_desc_t*)phys_to_virt(board->ccb->current_tx_desc[ hw->channel ]) ) % TX_DESC_MAX;
+
+		    if(newbusy < 0)
+		    {
+			printk("slicecom: %s: FATAL: fresly computed busy = %d, HW: 0x%p, SW: 0x%p\n",
+			dev->name, newbusy,
+			phys_to_virt(board->ccb->current_tx_desc[hw->channel]),
+			& hw->tx_desc[hw->tx_desc_ptr]);
+		    }
+
+		    /* Fogyott valami a Tx ringbol? */
+
+		    if (newbusy < hw->busy)
+		    {
+			// ack &= ~STAT_PTI;                            /* Don't ack, we had some work  */
+			hw->busy = newbusy;
+			if (ch->LINE_tx)
+			    ch->LINE_tx(dev);	/* Report it to protocol driver */
+		    }
+		    else if (newbusy > hw->busy)
+			printk("slicecom: %s: newbusy > hw->busy, this should not happen!\n", dev->name);
+		}
+	    }
+	}
+	stat &= ~STAT_PTI;
+
+	int_info = board->piq[board->piq_ptr];
+	if (int_info.all & 0xF0000000)	/* ha ez nem 0, akkor itt interrupt_info van            */
+	{
+	    ack &= ~STAT_LBII;	/* don't ack the interrupt, we had some work to do      */
+
+	    /* We do not really use (yet) the interrupt info from this queue, */
+
+	    // printk("slicecom: %s: LBI Interrupt event: %08x\n", board->devname, int_info.all);
+
+	    if (!board->isx21)
+	    {
+		slicecom_update_leds(board);
+		slicecom_update_line_counters(board);
+	    }
+
+	    goto go_for_next_lbi_interrupt;	/* To avoid warning about unused label  */
+
+	    go_for_next_lbi_interrupt:	/* One step in the interrupt queue */
+	    board->piq[board->piq_ptr].all = 0;	/* megjelolom hogy itt meg nem jart a hw        */
+	    board->piq_ptr = (board->piq_ptr + 1) % MUNICH_PIQMAX;
+	}
+	stat &= ~STAT_LBII;
+
+	writel(ack, MUNICH_VIRT(STAT));
+
+	if (stat & STAT_TSPA)
+	{
+	    //      printk("slicecom: %s: PCM TSP Asynchronous\n", board->devname);
+	    writel(STAT_TSPA, MUNICH_VIRT(STAT));
+	    stat &= ~STAT_TSPA;
+	}
+
+	if (stat & STAT_RSPA)
+	{
+	    //      printk("slicecom: %s: PCM RSP Asynchronous\n", board->devname);
+	    writel(STAT_RSPA, MUNICH_VIRT(STAT));
+	    stat &= ~STAT_RSPA;
+	}
+	if (stat)
+	{
+	    printk("MUNICH_interrupt: unhandled interrupt, STAT=0x%08x\n",
+		   stat);
+	    writel(stat, MUNICH_VIRT(STAT));	/* ha valamit megsem kezeltunk le, azert ack-ot kuldunk neki */
+	}
+
+    }
+    board->histogram[work]++;
+
+    /* We can miss these if we reach the MAX_WORK   */
+    /* Count it to see how often it happens         */
+
+    if (race_stat & STAT_PRI)
+	board->stat_pri_races_missed++;
+    if (race_stat & STAT_PTI)
+	board->stat_pti_races_missed++;
+    return;
+}
+
+void free_stuff(munich_board_t *board, struct comx_channel *ch)
+{
+/* Free CCB and the interrupt queues */
+    if (board->ccb) kfree((void *)board->ccb);
+    if (board->tiq) kfree((void *)board->tiq);
+    if (board->riq) kfree((void *)board->riq);
+    if (board->piq) kfree((void *)board->piq);
+}
+
+/* 
+ * Hardware open routine.
+ * Called by comx (upper) layer when the user wants to bring up the interface
+ * with ifconfig.
+ * Initializes hardware, allocates resources etc.
+ * Returns 0 on OK, or standard error value on error.
+ */
+
+static int MUNICH_open(struct net_device *dev)
+{
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+    struct proc_dir_entry *procfile = ch->procdir->subdir;
+    munich_board_t *board;
+    munich_ccb_t *ccb;
+
+    u32 *bar1;
+    u8 *lbi;
+    u32 stat;
+    unsigned long flags, jiffs;
+
+    int i, channel;
+    u32 timeslots = hw->timeslots;
+
+    board = hw->boardnum + (ch->hardware == &pcicomhw ? pcicom_boards : slicecom_boards);
+
+    bar1 = board->bar1;
+    lbi = board->lbi;
+
+    /* TODO: a timeslotok ellenorzese kell majd ide .. hat, biztos? mar a write_proc-ban is
+       ellenorzom valamennyire.
+       if (!dev->io || !dev->irq) return -ENODEV;
+     */
+
+    if (!board->pci)
+    {
+	printk("MUNICH_open: no %s board with boardnum = %d\n",
+	       ch->hardware->name, hw->boardnum);
+	return -ENODEV;
+    }
+
+    spin_lock_irqsave(&mister_lock, flags);
+    /* lock the section to avoid race with multiple opens and make sure
+       that no interrupts get called while this lock is active */
+
+    if (board->use_count == 0)	/* bring up the board if it was unused                  */
+	/* if fails, frees allocated resources and returns.     */
+	/* TOD: is it safe? nem kellene resetelni a kartyat?    */
+    {
+	printk("MUNICH_open: %s: bringing up board\n", board->devname);
+
+	/* Clean up the board's static struct if messed: */
+
+	for (i = 0; i < 32; i++)
+	    board->twins[i] = NULL;
+	for (i = 0; i < MAX_WORK; i++)
+	    board->histogram[i] = 0;
+
+	board->lineup = 0;
+
+	/* Allocate CCB: */
+        board->ccb = kmalloc(sizeof(munich_ccb_t), GFP_KERNEL);
+	if (board->ccb == NULL)
+	{
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    return -ENOMEM;
+	}
+	memset((void *)board->ccb, 0, sizeof(munich_ccb_t));
+	board->ccb->csa = virt_to_phys(board->ccb);
+	ccb = board->ccb;
+	for (i = 0; i < 32; i++)
+	{
+	    ccb->timeslot_spec[i].tti = 1;
+	    ccb->timeslot_spec[i].rti = 1;
+	}
+
+	/* Interrupt queues: */
+
+	board->tiq = kmalloc(MUNICH_INTQSIZE, GFP_KERNEL);
+	if (board->tiq == NULL)
+	{
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -ENOMEM;
+	}
+	memset((void *)board->tiq, 0, MUNICH_INTQSIZE);
+
+	board->riq = kmalloc(MUNICH_INTQSIZE, GFP_KERNEL);
+	if (board->riq == NULL)
+	{
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -ENOMEM;
+	}
+	memset((void *)board->riq, 0, MUNICH_INTQSIZE);
+
+	board->piq = kmalloc(MUNICH_PIQSIZE, GFP_KERNEL);
+	if (board->piq == NULL)
+	{
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -ENOMEM;
+	}
+	memset((void *)board->piq, 0, MUNICH_PIQSIZE);
+
+	board->tiq_ptr = 0;
+	board->riq_ptr = 0;
+	board->piq_ptr = 0;
+
+	/* Request irq: */
+
+	board->irq = 0;
+
+	/* (char*) cast to avoid warning about discarding volatile:             */
+	if (request_irq(board->pci->irq, MUNICH_interrupt, 0,
+	    (char *)board->devname, (void *)board))
+	{
+	    printk("MUNICH_open: %s: unable to obtain irq %d\n", board->devname,
+		   board->pci->irq);
+	    /* TOD: free other resources (a sok malloc feljebb)                     */
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -EAGAIN;
+	}
+	board->irq = board->pci->irq;	/* csak akkor legyen != 0, ha tenyleg le van foglalva nekunk */
+
+	/* Programming device: */
+
+	/* Reset the board like a power-on: */
+	/* TOD:
+	   - It is not a real power-on: if a DMA transaction fails with master abort, the board
+	   stays in half-dead state.
+	   - It doesn't reset the FALC line driver */
+
+	pci_write_config_dword(board->pci, MUNICH_PCI_PCIRES, 0xe0000);
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(1);
+	pci_write_config_dword(board->pci, MUNICH_PCI_PCIRES, 0);
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(1);
+
+        writel(virt_to_phys(&ccb->csa), MUNICH_VIRT(CCBA));
+        writel(virt_to_phys( board->tiq ), MUNICH_VIRT(TIQBA));
+        writel(MUNICH_INTQLEN, MUNICH_VIRT(TIQL));
+        writel(virt_to_phys( board->riq ), MUNICH_VIRT(RIQBA));
+        writel(MUNICH_INTQLEN, MUNICH_VIRT(RIQL));
+        writel(virt_to_phys( board->piq ), MUNICH_VIRT(PIQBA));
+        writel(MUNICH_PIQLEN, MUNICH_VIRT(PIQL));
+        
+	/* Put the magic values into the registers: */
+
+	writel(MODE1_MAGIC, MUNICH_VIRT(MODE1));
+	writel(MODE2_MAGIC, MUNICH_VIRT(MODE2));
+
+	writel(LREG0_MAGIC, MUNICH_VIRT(LREG0));
+	writel(LREG1_MAGIC, MUNICH_VIRT(LREG1));
+	writel(LREG2_MAGIC, MUNICH_VIRT(LREG2));
+	writel(LREG3_MAGIC, MUNICH_VIRT(LREG3));
+	writel(LREG4_MAGIC, MUNICH_VIRT(LREG4));
+	writel(LREG5_MAGIC, MUNICH_VIRT(LREG5));
+
+	writel(LCONF_MAGIC1, MUNICH_VIRT(LCONF));	/* reset the DMSM */
+	writel(LCONF_MAGIC2, MUNICH_VIRT(LCONF));	/* enable the DMSM */
+
+	writel(~0, MUNICH_VIRT(TXPOLL));
+	writel(board->isx21 ? 0x1400 : 0xa000, MUNICH_VIRT(GPDIR));
+
+	if (readl(MUNICH_VIRT(STAT))) writel(readl(MUNICH_VIRT(STAT)), MUNICH_VIRT(STAT));
+
+	ccb->action_spec = CCB_ACTIONSPEC_RES | CCB_ACTIONSPEC_IA;
+	writel(CMD_ARPCM, MUNICH_VIRT(CMD));	/* Start the PCM core reset */
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(1);
+
+	stat = 0;		/* Wait for the action to complete max. 1 second */
+	jiffs = jiffies;
+	while (!((stat = readl(MUNICH_VIRT(STAT))) & (STAT_PCMA | STAT_PCMF)) && time_before(jiffies, jiffs + HZ))
+	{
+	    set_current_state(TASK_UNINTERRUPTIBLE);
+	    schedule_timeout(1);
+	}
+
+	if (stat & STAT_PCMF)
+	{
+	    printk(KERN_ERR
+		   "MUNICH_open: %s: Initial ARPCM failed. STAT=0x%08x\n",
+		   board->devname, stat);
+	    writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMF, MUNICH_VIRT(STAT));
+	    free_irq(board->irq, (void *)board);	/* TOD: free other resources too *//* maybe shut down hw? */
+	    board->irq = 0;
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -EAGAIN;
+	}
+	else if (!(stat & STAT_PCMA))
+	{
+	    printk(KERN_ERR
+		   "MUNICH_open: %s: Initial ARPCM timeout. STAT=0x%08x\n",
+		   board->devname, stat);
+	    free_irq(board->irq, (void *)board);	/* TOD: free other resources too *//* maybe shut off the hw? */
+	    board->irq = 0;
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -EIO;
+	}
+
+	writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMA, MUNICH_VIRT(STAT));	/* Acknowledge */
+
+	if (board->isx21) writel(0, MUNICH_VIRT(GPDATA));
+
+	printk("MUNICH_open: %s: succesful HW-open took %ld jiffies\n",
+	       board->devname, jiffies - jiffs);
+
+	/* Set up the FALC hanging on the Local Bus: */
+
+	if (!board->isx21)
+	{
+	    writeb(0x0e, lbi + FMR1);
+	    writeb(0, lbi + LIM0);
+	    writeb(0xb0, lbi + LIM1);	/* TODO: input threshold */
+	    writeb(0xf7, lbi + XPM0);
+	    writeb(0x02, lbi + XPM1);
+	    writeb(0x00, lbi + XPM2);
+	    writeb(0xf0, lbi + FMR0);
+	    writeb(0x80, lbi + PCD);
+	    writeb(0x80, lbi + PCR);
+	    writeb(0x00, lbi + LIM2);
+	    writeb(0x07, lbi + XC0);
+	    writeb(0x3d, lbi + XC1);
+	    writeb(0x05, lbi + RC0);
+	    writeb(0x00, lbi + RC1);
+	    writeb(0x83, lbi + FMR2);
+	    writeb(0x9f, lbi + XSW);
+	    writeb(0x0f, lbi + XSP);
+	    writeb(0x00, lbi + TSWM);
+	    writeb(0xe0, lbi + MODE);
+	    writeb(0xff, lbi + IDLE);	/* Idle Code to send in unused timeslots        */
+	    writeb(0x83, lbi + IPC);	/* interrupt query line mode: Push/pull output, active high     */
+	    writeb(0xbf, lbi + IMR3);	/* send an interrupt every second               */
+
+	    slicecom_set_framing(hw->boardnum, board->framing);
+	    slicecom_set_linecode(hw->boardnum, board->linecode);
+	    slicecom_set_clock_source(hw->boardnum, board->clock_source);
+	    slicecom_set_loopback(hw->boardnum, board->loopback);
+
+	    memset((void *)board->intervals, 0, sizeof(board->intervals));
+	    board->current_interval = 0;
+	    board->elapsed_seconds = 0;
+	    board->ses_seconds = 0;
+	    board->is_unavailable = 0;
+	    board->no_ses_seconds = 0;
+	    board->deg_elapsed_seconds = 0;
+	    board->deg_cumulated_errors = 0;
+	}
+
+	/* Enable the interrupts last                                                   */
+	/* These interrupts will be enabled. We do not need the others. */
+
+	writel(readl(MUNICH_VIRT(IMASK)) & ~(STAT_PTI | STAT_PRI | STAT_LBII | STAT_TSPA | STAT_RSPA), MUNICH_VIRT(IMASK));
+    }
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    dev->irq = board->irq;	/* hogy szep legyen az ifconfig outputja */
+    ccb = board->ccb;		/* TOD: ez igy csunya egy kicsit hogy benn is meg kinn is beletoltom :( */
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    set_current_state(TASK_UNINTERRUPTIBLE);
+    schedule_timeout(1);
+
+    /* Check if the selected timeslots aren't used already */
+
+    for (i = 0; i < 32; i++)
+	if (((1 << i) & timeslots) && ccb->timeslot_spec[i].tti == 0)
+	{
+	    printk("MUNICH_open: %s: timeslot %d already used by %s\n",
+		   dev->name, i, board->twins[ccb->timeslot_spec[i].txchannel]->name);
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -EBUSY;	/* TOD: lehet hogy valami mas errno kellene? */
+	}
+
+    /* find a free channel: */
+    /* TODO: ugly, rewrite it  */
+
+    for (channel = 0; channel <= 32; channel++)
+    {
+	if (channel == 32)
+	{			/* not found a free one */
+	    printk
+		("MUNICH_open: %s: FATAL: can not find a free channel - this should not happen!\n",
+		 dev->name);
+	    spin_unlock_irqrestore(&mister_lock, flags);
+	    free_stuff(board, ch);
+	    return -ENODEV;
+	}
+	if (board->twins[channel] == NULL)
+	    break;		/* found the first free one */
+    }
+
+    board->lastcheck = jiffies;	/* avoid checking uninitialized hardware channel */
+
+    /* Open the channel. If fails, calls MUNICH_close() to properly free resources and stop the HW */
+
+    hw->channel = channel;
+    board->twins[channel] = dev;
+
+    board->use_count++;		/* meg nem nyitottuk meg a csatornat, de a twins-ben
+				   mar elfoglaltunk egyet, es ha a _close-t akarjuk hivni, akkor ez kell. */
+    for (i = 0; i < 32; i++)
+	if ((1 << i) & timeslots)
+	{
+	    ccb->timeslot_spec[i].tti = 0;
+	    ccb->timeslot_spec[i].txchannel = channel;
+	    ccb->timeslot_spec[i].txfillmask = ~0;
+
+	    ccb->timeslot_spec[i].rti = 0;
+	    ccb->timeslot_spec[i].rxchannel = channel;
+	    ccb->timeslot_spec[i].rxfillmask = ~0;
+	}
+
+    if (!board->isx21) rework_idle_channels(dev);
+
+    memset((void *)&(hw->tx_desc), 0, TX_DESC_MAX * sizeof(tx_desc_t));
+    memset((void *)&(hw->rx_desc), 0, RX_DESC_MAX * sizeof(rx_desc_t));
+
+    for (i = 0; i < TX_DESC_MAX; i++)
+    {
+	hw->tx_desc[i].fe = 1;
+	hw->tx_desc[i].fnum = 2;
+                hw->tx_desc[i].data     = virt_to_phys( & (hw->tx_data[i][0]) );
+                hw->tx_desc[i].next     = virt_to_phys( & (hw->tx_desc[ (i+1) % TX_DESC_MAX ]) );
+
+    }
+    hw->tx_desc_ptr = 0;	/* we will send an initial packet so it is correct: "oda irtunk utoljara" */
+    hw->busy = 0;
+    hw->tx_desc[hw->tx_desc_ptr].hold = 1;
+    hw->tx_desc[hw->tx_desc_ptr].no = 1;	/* TOD: inkabb csak 0 hosszut kuldjunk ki az initkor? */
+
+    for (i = 0; i < RX_DESC_MAX; i++)
+    {
+	hw->rx_desc[i].no = RXBUFFER_SIZE;
+	hw->rx_desc[i].data = virt_to_phys(&(hw->rx_data[i][0]));
+	hw->rx_desc[i].next = virt_to_phys(&(hw->rx_desc[(i+1) % RX_DESC_MAX]));
+	hw->rx_desc[i].status = 0xFF;
+    }
+    hw->rx_desc_ptr = 0;
+
+    hw->rx_desc[(hw->rx_desc_ptr + RX_DESC_MAX - 2) % RX_DESC_MAX].hold = 1;
+
+    memset((void *)&ccb->channel_spec[channel], 0, sizeof(channel_spec_t));
+
+    ccb->channel_spec[channel].ti = 0;	/* Transmit off */
+    ccb->channel_spec[channel].to = 1;
+    ccb->channel_spec[channel].ta = 0;
+
+    ccb->channel_spec[channel].th = 1;	/* Transmit hold        */
+
+    ccb->channel_spec[channel].ri = 0;	/* Receive off  */
+    ccb->channel_spec[channel].ro = 1;
+    ccb->channel_spec[channel].ra = 0;
+
+    ccb->channel_spec[channel].mode = 3;	/* HDLC */
+
+    ccb->action_spec = CCB_ACTIONSPEC_IN | (channel << 8);
+    writel(CMD_ARPCM, MUNICH_VIRT(CMD));
+    set_current_state(TASK_UNINTERRUPTIBLE);
+    schedule_timeout(1);
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    stat = 0;
+    jiffs = jiffies;
+    while (!((stat = readl(MUNICH_VIRT(STAT))) & (STAT_PCMA | STAT_PCMF)) && time_before(jiffies, jiffs + HZ))
+    {
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(1);
+    }
+
+    if (stat & STAT_PCMF)
+    {
+	printk(KERN_ERR "MUNICH_open: %s: %s channel %d off failed\n",
+	       dev->name, board->devname, channel);
+	writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMF, MUNICH_VIRT(STAT));
+	MUNICH_close(dev);
+	return -EAGAIN;
+    }
+    else if (!(stat & STAT_PCMA))
+    {
+	printk(KERN_ERR "MUNICH_open: %s: %s channel %d off timeout\n",
+	       dev->name, board->devname, channel);
+	MUNICH_close(dev);
+	return -EIO;
+    }
+
+    writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMA, MUNICH_VIRT(STAT));
+    //      printk("MUNICH_open: %s: succesful channel off took %ld jiffies\n", board->devname, jiffies-jiffs);
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    set_current_state(TASK_UNINTERRUPTIBLE);
+    schedule_timeout(1);
+
+    ccb->channel_spec[channel].ifc = 1;	/* 1 .. 'Idle/Flag change' interrupt letiltva   */
+    ccb->channel_spec[channel].fit = 1;
+    ccb->channel_spec[channel].nitbs = 1;
+    ccb->channel_spec[channel].itbs = 2;
+
+    /* TODOO: lehet hogy jo lenne igy, de utana kellene nezni hogy nem okoz-e fragmentaciot */
+    //      ccb->channel_spec[channel].itbs = 2 * number_of_timeslots;
+    //      printk("open: %s: number_of_timeslots: %d\n", dev->name, number_of_timeslots);
+
+    ccb->channel_spec[channel].mode = 3;	/* HDLC */
+    ccb->channel_spec[channel].ftda = virt_to_phys(&(hw->tx_desc));
+    ccb->channel_spec[channel].frda = virt_to_phys(&(hw->rx_desc[0]));
+
+    ccb->channel_spec[channel].ti = 1;	/* Transmit init        */
+    ccb->channel_spec[channel].to = 0;
+    ccb->channel_spec[channel].ta = 1;
+
+    ccb->channel_spec[channel].th = 0;
+
+    ccb->channel_spec[channel].ri = 1;	/* Receive init */
+    ccb->channel_spec[channel].ro = 0;
+    ccb->channel_spec[channel].ra = 1;
+
+    ccb->action_spec = CCB_ACTIONSPEC_ICO | (channel << 8);
+    writel(CMD_ARPCM, MUNICH_VIRT(CMD));	/* Start the channel init */
+    set_current_state(TASK_UNINTERRUPTIBLE);
+    schedule_timeout(1);
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    stat = 0;			/* Wait for the action to complete max. 1 second */
+    jiffs = jiffies;
+    while (!((stat = readl(MUNICH_VIRT(STAT))) & (STAT_PCMA | STAT_PCMF)) && time_before(jiffies, jiffs + HZ))
+    {
+	set_current_state(TASK_UNINTERRUPTIBLE);
+        schedule_timeout(1);
+    }
+
+    if (stat & STAT_PCMF)
+    {
+	printk(KERN_ERR "MUNICH_open: %s: channel open ARPCM failed\n",
+	       board->devname);
+	writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMF, MUNICH_VIRT(STAT));
+	MUNICH_close(dev);
+	return -EAGAIN;
+    }
+    else if (!(stat & STAT_PCMA))
+    {
+	printk(KERN_ERR "MUNICH_open: %s: channel open ARPCM timeout\n",
+	       board->devname);
+	MUNICH_close(dev);
+	return -EIO;
+    }
+
+    writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMA, MUNICH_VIRT(STAT));
+    //      printk("MUNICH_open: %s: succesful channel open took %ld jiffies\n", board->devname, jiffies-jiffs);
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    ccb->channel_spec[channel].nitbs = 0;	/* once ITBS defined, these must be 0   */
+    ccb->channel_spec[channel].itbs = 0;
+
+    if (board->isx21)
+    {
+	board->modemline_timer.data = (unsigned int)board;
+	board->modemline_timer.function = pcicom_modemline;
+	board->modemline_timer.expires = jiffies + HZ;
+	add_timer((struct timer_list *)&board->modemline_timer);
+    }
+
+    /* It is done. Declare that we're open: */
+    hw->busy = 0;		/* It may be 1 if the frame at Tx init already ended, but it is not     */
+    /* a real problem: we compute hw->busy on every interrupt                       */
+    hw->rafutott = 0;
+    ch->init_status |= HW_OPEN;
+
+    /* Initialize line state: */
+    if (board->lineup)
+	ch->line_status |= LINE_UP;
+    else
+	ch->line_status &= ~LINE_UP;
+
+    /* Remove w attribute from /proc files associated to hw parameters:
+       no write when the device is open */
+
+    for (; procfile; procfile = procfile->next)
+	if (strcmp(procfile->name, FILENAME_BOARDNUM) == 0 ||
+	    strcmp(procfile->name, FILENAME_TIMESLOTS) == 0)
+	    procfile->mode = S_IFREG | 0444;
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    return 0;
+}
+
+/*
+ * Hardware close routine.
+ * Called by comx (upper) layer when the user wants to bring down the interface
+ * with ifconfig.
+ * We also call it from MUNICH_open, if the open fails.
+ * Brings down hardware, frees resources, stops receiver
+ * Returns 0 on OK, or standard error value on error.
+ */
+
+static int MUNICH_close(struct net_device *dev)
+{
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+    struct proc_dir_entry *procfile = ch->procdir->subdir;
+    munich_board_t *board;
+    munich_ccb_t *ccb;
+
+    u32 *bar1;
+    u32 timeslots = hw->timeslots;
+    int stat, i, channel = hw->channel;
+    unsigned long jiffs;
+
+    board = hw->boardnum + (ch->hardware == &pcicomhw ? pcicom_boards : slicecom_boards);
+
+    ccb = board->ccb;
+    bar1 = board->bar1;
+
+    if (board->isx21)
+	del_timer((struct timer_list *)&board->modemline_timer);
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    set_current_state(TASK_UNINTERRUPTIBLE);
+    schedule_timeout(1);
+
+    /* Disable receiver for the channel: */
+
+    for (i = 0; i < 32; i++)
+	if ((1 << i) & timeslots)
+	{
+	    ccb->timeslot_spec[i].tti = 1;
+	    ccb->timeslot_spec[i].txfillmask = 0;	/* just to be double-sure :) */
+
+	    ccb->timeslot_spec[i].rti = 1;
+	    ccb->timeslot_spec[i].rxfillmask = 0;
+	}
+
+    if (!board->isx21) rework_idle_channels(dev);
+
+    ccb->channel_spec[channel].ti = 0;	/* Receive off, Transmit off */
+    ccb->channel_spec[channel].to = 1;
+    ccb->channel_spec[channel].ta = 0;
+    ccb->channel_spec[channel].th = 1;
+
+    ccb->channel_spec[channel].ri = 0;
+    ccb->channel_spec[channel].ro = 1;
+    ccb->channel_spec[channel].ra = 0;
+
+    board->twins[channel] = NULL;
+
+    ccb->action_spec = CCB_ACTIONSPEC_IN | (channel << 8);
+    writel(CMD_ARPCM, MUNICH_VIRT(CMD));
+    set_current_state(TASK_UNINTERRUPTIBLE);
+    schedule_timeout(1);
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    stat = 0;
+    jiffs = jiffies;
+    while (!((stat = readl(MUNICH_VIRT(STAT))) & (STAT_PCMA | STAT_PCMF)) && time_before(jiffies, jiffs + HZ))
+    {
+	set_current_state(TASK_UNINTERRUPTIBLE);
+	schedule_timeout(1);
+    }
+
+    if (stat & STAT_PCMF)
+    {
+	printk(KERN_ERR
+	       "MUNICH_close: %s: FATAL: channel off ARPCM failed, not closing!\n",
+	       dev->name);
+	writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMF, MUNICH_VIRT(STAT));
+	/* If we return success, the privdata (and the descriptor list) will be freed */
+	return -EIO;
+    }
+    else if (!(stat & STAT_PCMA))
+	printk(KERN_ERR "MUNICH_close: %s: channel off ARPCM timeout\n",
+	       board->devname);
+
+    writel(readl(MUNICH_VIRT(STAT)) & STAT_PCMA, MUNICH_VIRT(STAT));
+    //      printk("MUNICH_close: %s: channel off took %ld jiffies\n", board->devname, jiffies-jiffs);
+
+    spin_lock_irqsave(&mister_lock, flags);
+
+    board->use_count--;
+
+    if (!board->use_count)	/* we were the last user of the board */
+    {
+	printk("MUNICH_close: bringing down board %s\n", board->devname);
+
+	/* program down the board: */
+
+	writel(0x0000FF7F, MUNICH_VIRT(IMASK));	/* do not send any interrupts */
+	writel(0, MUNICH_VIRT(CMD));	/* stop the timer if someone started it */
+	writel(~0U, MUNICH_VIRT(STAT));	/* if an interrupt came between the cli()-sti(), quiet it */
+	if (ch->hardware == &pcicomhw)
+	    writel(0x1400, MUNICH_VIRT(GPDATA));
+
+	/* Put the board into 'reset' state: */
+	pci_write_config_dword(board->pci, MUNICH_PCI_PCIRES, 0xe0000);
+
+	/* Free irq and other resources: */
+	if (board->irq)
+	    free_irq(board->irq, (void *)board);	/* Ha nem inicializalta magat, akkor meg nincs irq */
+	board->irq = 0;
+
+	free_stuff(board, ch);
+    }
+
+    /* Enable setting of hw parameters */
+    for (; procfile; procfile = procfile->next)
+	if (strcmp(procfile->name, FILENAME_BOARDNUM) == 0 ||
+	    strcmp(procfile->name, FILENAME_TIMESLOTS) == 0)
+	    procfile->mode = S_IFREG | 0644;
+
+    /* We're not open anymore */
+    ch->init_status &= ~HW_OPEN;
+
+    spin_unlock_irqrestore(&mister_lock, flags);
+
+    return 0;
+}
+
+/* 
+ * Give (textual) status information.
+ * The text it returns will be a part of what appears when the user does a
+ * cat /proc/comx/comx[n]/status 
+ * Don't write more than PAGESIZE.
+ * Return value: number of bytes written (length of the string, incl. 0)
+ */
+
+static int MUNICH_minden(struct net_device *dev, char *page)
+{
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+    munich_board_t *board;
+    struct net_device *devp;
+
+    u8 *lbi;
+    e1_stats_t *curr_int, *prev_int;
+    e1_stats_t last4, last96;	/* sum of last 4, resp. last 96 intervals               */
+    unsigned *sump,		/* running pointer for the sum data                     */
+     *p;			/* running pointer for the interval data                */
+
+    int len = 0;
+    u8 frs0, frs1;
+    u8 fmr2;
+    int i, j;
+    u32 timeslots;
+
+    board = hw->boardnum + (ch->hardware == &pcicomhw ? pcicom_boards : slicecom_boards);
+
+    lbi = board->lbi;
+    curr_int = &board->intervals[board->current_interval];
+    prev_int =
+	&board->
+	intervals[(board->current_interval + SLICECOM_BOARD_INTERVALS_SIZE -
+		   1) % SLICECOM_BOARD_INTERVALS_SIZE];
+
+    if (!board->isx21)
+    {
+	frs0 = readb(lbi + FRS0);
+	fmr2 = readb(lbi + FMR2);
+	len += snprintf(page + len, PAGE_SIZE - len, "Controller status:\n");
+	if (frs0 == 0)
+	    len += snprintf(page + len, PAGE_SIZE - len, "\tNo alarms\n");
+	else
+	{
+	    if (frs0 & FRS0_LOS)
+	            len += snprintf(page + len, PAGE_SIZE - len, "\tLoss Of Signal\n");
+	    else
+	    {
+		if (frs0 & FRS0_AIS)
+		    len += snprintf(page + len, PAGE_SIZE - len,
+				 "\tAlarm Indication Signal\n");
+		else
+		{
+		    if (frs0 & FRS0_AUXP)
+			len += snprintf(page + len, PAGE_SIZE - len,
+				     "\tAuxiliary Pattern Indication\n");
+		    if (frs0 & FRS0_LFA)
+			len += snprintf(page + len, PAGE_SIZE - len,
+				     "\tLoss of Frame Alignment\n");
+		    else
+		    {
+			if (frs0 & FRS0_RRA)
+			    len += snprintf(page + len, PAGE_SIZE - len,
+					 "\tReceive Remote Alarm\n");
+
+			/* You can't set this framing with the /proc interface, but it  */
+			/* may be good to have here this alarm if you set it by hand:   */
+
+			if ((board->framing == SLICECOM_FRAMING_CRC4) &&
+			    (frs0 & FRS0_LMFA))
+			    len += snprintf(page + len, PAGE_SIZE - len,
+					 "\tLoss of CRC4 Multiframe Alignment\n");
+
+			if (((fmr2 & 0xc0) == 0xc0) && (frs0 & FRS0_NMF))
+			    len += snprintf(page + len, PAGE_SIZE - len,
+				 "\tNo CRC4 Multiframe alignment Found after 400 msec\n");
+		    }
+		}
+	    }
+	}
+
+	frs1 = readb(lbi + FRS1);
+	if (FRS1_XLS & frs1)
+	    len += snprintf(page + len, PAGE_SIZE - len,
+		 "\tTransmit Line Short\n");
+
+	/* debug Rx ring: DEL: - vagy meghagyni, de akkor legyen kicsit altalanosabb */
+    }
+
+    len += snprintf(page + len, PAGE_SIZE - len, "Rx ring:\n");
+    len += snprintf(page + len, PAGE_SIZE - len, "\trafutott: %d\n", hw->rafutott);
+    len += snprintf(page + len, PAGE_SIZE - len,
+		 "\tlastcheck: %ld, jiffies: %ld\n", board->lastcheck, jiffies);
+    len += snprintf(page + len, PAGE_SIZE - len, "\tbase: %08x\n",
+	(u32) virt_to_phys(&hw->rx_desc[0]));
+    len += snprintf(page + len, PAGE_SIZE - len, "\trx_desc_ptr: %d\n",
+		 hw->rx_desc_ptr);
+    len += snprintf(page + len, PAGE_SIZE - len, "\trx_desc_ptr: %08x\n",
+	(u32) virt_to_phys(&hw->rx_desc[hw->rx_desc_ptr]));
+    len += snprintf(page + len, PAGE_SIZE - len, "\thw_curr_ptr: %08x\n",
+		 board->ccb->current_rx_desc[hw->channel]);
+
+    for (i = 0; i < RX_DESC_MAX; i++)
+	len += snprintf(page + len, PAGE_SIZE - len, "\t%08x %08x %08x %08x\n",
+		     *((u32 *) & hw->rx_desc[i] + 0),
+		     *((u32 *) & hw->rx_desc[i] + 1),
+		     *((u32 *) & hw->rx_desc[i] + 2),
+		     *((u32 *) & hw->rx_desc[i] + 3));
+
+    if (!board->isx21)
+    {
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "Interfaces using this board: (channel-group, interface, timeslots)\n");
+	for (i = 0; i < 32; i++)
+	{
+	    devp = board->twins[i];
+	    if (devp != NULL)
+	    {
+		timeslots =
+		    ((struct slicecom_privdata *)((struct comx_channel *)devp->
+						  priv)->HW_privdata)->
+		    timeslots;
+		len += snprintf(page + len, PAGE_SIZE - len, "\t%2d %s: ", i,
+			     devp->name);
+		for (j = 0; j < 32; j++)
+		    if ((1 << j) & timeslots)
+			len += snprintf(page + len, PAGE_SIZE - len, "%d ", j);
+		len += snprintf(page + len, PAGE_SIZE - len, "\n");
+	    }
+	}
+    }
+
+    len += snprintf(page + len, PAGE_SIZE - len, "Interrupt work histogram:\n");
+    for (i = 0; i < MAX_WORK; i++)
+	len += snprintf(page + len, PAGE_SIZE - len, "hist[%2d]: %8u%c", i,
+		     board->histogram[i], (i &&
+					   ((i + 1) % 4 == 0 ||
+					    i == MAX_WORK - 1)) ? '\n' : ' ');
+
+    len += snprintf(page + len, PAGE_SIZE - len, "Tx ring histogram:\n");
+    for (i = 0; i < TX_DESC_MAX; i++)
+	len += snprintf(page + len, PAGE_SIZE - len, "hist[%2d]: %8u%c", i,
+		     hw->tx_ring_hist[i], (i &&
+					   ((i + 1) % 4 == 0 ||
+					    i ==
+					    TX_DESC_MAX - 1)) ? '\n' : ' ');
+
+    if (!board->isx21)
+    {
+
+	memset((void *)&last4, 0, sizeof(last4));
+	memset((void *)&last96, 0, sizeof(last96));
+
+	/* Calculate the sum of last 4 intervals: */
+
+	for (i = 1; i <= 4; i++)
+	{
+	    p = (unsigned *)&board->intervals[(board->current_interval +
+			   SLICECOM_BOARD_INTERVALS_SIZE -
+			   i) % SLICECOM_BOARD_INTERVALS_SIZE];
+	    sump = (unsigned *)&last4;
+	    for (j = 0; j < (sizeof(e1_stats_t) / sizeof(unsigned)); j++)
+		sump[j] += p[j];
+	}
+
+	/* Calculate the sum of last 96 intervals: */
+
+	for (i = 1; i <= 96; i++)
+	{
+	    p = (unsigned *)&board->intervals[(board->current_interval +
+			   SLICECOM_BOARD_INTERVALS_SIZE -
+			   i) % SLICECOM_BOARD_INTERVALS_SIZE];
+	    sump = (unsigned *)&last96;
+	    for (j = 0; j < (sizeof(e1_stats_t) / sizeof(unsigned)); j++)
+		sump[j] += p[j];
+	}
+
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "Data in current interval (%d seconds elapsed):\n",
+		     board->elapsed_seconds);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Line Code Violations, %d Path Code Violations, %d E-Bit Errors\n",
+		     curr_int->line_code_violations,
+		     curr_int->path_code_violations, curr_int->e_bit_errors);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Slip Secs, %d Fr Loss Secs, %d Line Err Secs, %d Degraded Mins\n",
+		     curr_int->slip_secs, curr_int->fr_loss_secs,
+		     curr_int->line_err_secs, curr_int->degraded_mins);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Errored Secs, %d Bursty Err Secs, %d Severely Err Secs, %d Unavail Secs\n",
+		     curr_int->errored_secs, curr_int->bursty_err_secs,
+		     curr_int->severely_err_secs, curr_int->unavail_secs);
+
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "Data in Interval 1 (15 minutes):\n");
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Line Code Violations, %d Path Code Violations, %d E-Bit Errors\n",
+		     prev_int->line_code_violations,
+		     prev_int->path_code_violations, prev_int->e_bit_errors);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Slip Secs, %d Fr Loss Secs, %d Line Err Secs, %d Degraded Mins\n",
+		     prev_int->slip_secs, prev_int->fr_loss_secs,
+		     prev_int->line_err_secs, prev_int->degraded_mins);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Errored Secs, %d Bursty Err Secs, %d Severely Err Secs, %d Unavail Secs\n",
+		     prev_int->errored_secs, prev_int->bursty_err_secs,
+		     prev_int->severely_err_secs, prev_int->unavail_secs);
+
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "Data in last 4 intervals (1 hour):\n");
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Line Code Violations, %d Path Code Violations, %d E-Bit Errors\n",
+		     last4.line_code_violations, last4.path_code_violations,
+		     last4.e_bit_errors);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Slip Secs, %d Fr Loss Secs, %d Line Err Secs, %d Degraded Mins\n",
+		     last4.slip_secs, last4.fr_loss_secs, last4.line_err_secs,
+		     last4.degraded_mins);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Errored Secs, %d Bursty Err Secs, %d Severely Err Secs, %d Unavail Secs\n",
+		     last4.errored_secs, last4.bursty_err_secs,
+		     last4.severely_err_secs, last4.unavail_secs);
+
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "Data in last 96 intervals (24 hours):\n");
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Line Code Violations, %d Path Code Violations, %d E-Bit Errors\n",
+		     last96.line_code_violations, last96.path_code_violations,
+		     last96.e_bit_errors);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Slip Secs, %d Fr Loss Secs, %d Line Err Secs, %d Degraded Mins\n",
+		     last96.slip_secs, last96.fr_loss_secs,
+		     last96.line_err_secs, last96.degraded_mins);
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "   %d Errored Secs, %d Bursty Err Secs, %d Severely Err Secs, %d Unavail Secs\n",
+		     last96.errored_secs, last96.bursty_err_secs,
+		     last96.severely_err_secs, last96.unavail_secs);
+
+    }
+
+//      len +=snprintf( page + len, PAGE_SIZE - len, "Special events:\n" );
+//      len +=snprintf( page + len, PAGE_SIZE - len, "\tstat_pri/missed: %u / %u\n", board->stat_pri_races, board->stat_pri_races_missed );
+//      len +=snprintf( page + len, PAGE_SIZE - len, "\tstat_pti/missed: %u / %u\n", board->stat_pti_races, board->stat_pti_races_missed );
+    return len;
+}
+
+/*
+ * Memory dump function. Not used currently.
+ */
+static int BOARD_dump(struct net_device *dev)
+{
+    printk
+	("BOARD_dump() requested. It is unimplemented, it should not be called\n");
+    return (-1);
+}
+
+/* 
+ * /proc file read function for the files registered by this module.
+ * This function is called by the procfs implementation when a user
+ * wants to read from a file registered by this module.
+ * page is the workspace, start should point to the real start of data,
+ * off is the file offset, data points to the file's proc_dir_entry
+ * structure.
+ * Returns the number of bytes copied to the request buffer.
+ */
+
+static int munich_read_proc(char *page, char **start, off_t off, int count,
+			    int *eof, void *data)
+{
+    struct proc_dir_entry *file = (struct proc_dir_entry *)data;
+    struct net_device *dev = file->parent->data;
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+    munich_board_t *board;
+
+    int len = 0, i;
+    u32 timeslots = hw->timeslots;
+
+    board = hw->boardnum + (ch->hardware == &pcicomhw ? pcicom_boards : slicecom_boards);
+
+    if (!strcmp(file->name, FILENAME_BOARDNUM))
+	len = sprintf(page, "%d\n", hw->boardnum);
+    else if (!strcmp(file->name, FILENAME_TIMESLOTS))
+    {
+	for (i = 0; i < 32; i++)
+	    if ((1 << i) & timeslots)
+		len += snprintf(page + len, PAGE_SIZE - len, "%d ", i);
+	len += snprintf(page + len, PAGE_SIZE - len, "\n");
+    }
+    else if (!strcmp(file->name, FILENAME_FRAMING))
+    {
+	i = 0;
+	while (slicecom_framings[i].value &&
+	       slicecom_framings[i].value != board->framing)
+	    i++;
+	len += snprintf(page + len, PAGE_SIZE - len, "%s\n",
+		     slicecom_framings[i].name);
+    }
+    else if (!strcmp(file->name, FILENAME_LINECODE))
+    {
+	i = 0;
+	while (slicecom_linecodes[i].value &&
+	       slicecom_linecodes[i].value != board->linecode)
+	    i++;
+	len += snprintf(page + len, PAGE_SIZE - len, "%s\n",
+		     slicecom_linecodes[i].name);
+    }
+    else if (!strcmp(file->name, FILENAME_CLOCK_SOURCE))
+    {
+	i = 0;
+	while (slicecom_clock_sources[i].value &&
+	       slicecom_clock_sources[i].value != board->clock_source)
+	    i++;
+	len +=
+	    snprintf(page + len, PAGE_SIZE - len, "%s\n",
+		     slicecom_clock_sources[i].name);
+    }
+    else if (!strcmp(file->name, FILENAME_LOOPBACK))
+    {
+	i = 0;
+	while (slicecom_loopbacks[i].value &&
+	       slicecom_loopbacks[i].value != board->loopback)
+	    i++;
+	len += snprintf(page + len, PAGE_SIZE - len, "%s\n",
+		     slicecom_loopbacks[i].name);
+    }
+    /* We set permissions to write-only for REG and LBIREG, but root can read them anyway: */
+    else if (!strcmp(file->name, FILENAME_REG))
+    {
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "%s: " FILENAME_REG ": write-only file\n", dev->name);
+    }
+    else if (!strcmp(file->name, FILENAME_LBIREG))
+    {
+	len += snprintf(page + len, PAGE_SIZE - len,
+		     "%s: " FILENAME_LBIREG ": write-only file\n", dev->name);
+    }
+    else
+    {
+	printk("slicecom_read_proc: internal error, filename %s\n", file->name);
+	return -EBADF;
+    }
+    /* file handling administration: count eof status, offset, start address
+       and count: */
+
+    if (off >= len)
+    {
+	*eof = 1;
+	return 0;
+    }
+
+    *start = page + off;
+    if (count >= len - off)
+	*eof = 1;
+    return min((off_t) count, (off_t) len - off);
+}
+
+/* 
+ * Write function for /proc files registered by us.
+ * See the comment on read function above.
+ * Beware! buffer is in userspace!!!
+ * Returns the number of bytes written
+ */
+
+static int munich_write_proc(struct file *file, const char *buffer,
+			     u_long count, void *data)
+{
+    struct proc_dir_entry *entry = (struct proc_dir_entry *)data;
+    struct net_device *dev = (struct net_device *)entry->parent->data;
+    struct comx_channel *ch = dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+    munich_board_t *board;
+
+    unsigned long ts, tmp_boardnum;
+
+    u32 tmp_timeslots = 0;
+    char *page, *p;
+    int i;
+
+    board = hw->boardnum + (ch->hardware == &pcicomhw ? pcicom_boards : slicecom_boards);
+
+    /* Paranoia checking: */
+
+    if (file->f_dentry->d_inode->i_ino != entry->low_ino)
+    {
+	printk(KERN_ERR "munich_write_proc: file <-> data internal error\n");
+	return -EIO;
+    }
+
+    /* Request tmp buffer */
+    if (!(page = (char *)__get_free_page(GFP_KERNEL)))
+	return -ENOMEM;
+
+    /* Copy user data and cut trailing \n */
+    copy_from_user(page, buffer, count = min(count, PAGE_SIZE));
+    if (*(page + count - 1) == '\n')
+	*(page + count - 1) = 0;
+    *(page + PAGE_SIZE - 1) = 0;
+
+    if (!strcmp(entry->name, FILENAME_BOARDNUM))
+    {
+	tmp_boardnum = simple_strtoul(page, NULL, 0);
+	if (0 <= tmp_boardnum && tmp_boardnum < MAX_BOARDS)
+	    hw->boardnum = tmp_boardnum;
+	else
+	{
+	    printk("%s: " FILENAME_BOARDNUM " range is 0...%d\n", dev->name,
+		   MAX_BOARDS - 1);
+	    free_page((unsigned long)page);
+	    return -EINVAL;
+	}
+    }
+    else if (!strcmp(entry->name, FILENAME_TIMESLOTS))
+    {
+	p = page;
+	while (*p)
+	{
+	    if (isspace(*p))
+		p++;
+	    else
+	    {
+		ts = simple_strtoul(p, &p, 10);	/* base = 10: Don't read 09 as an octal number */
+		/* ts = 0 ha nem tudta beolvasni a stringet, erre egy kicsit epitek itt: */
+		if (0 <= ts && ts < 32)
+		{
+		    tmp_timeslots |= (1 << ts);
+		}
+		else
+		{
+		    printk("%s: " FILENAME_TIMESLOTS " range is 1...31\n",
+			   dev->name);
+		    free_page((unsigned long)page);
+		    return -EINVAL;
+		}
+	    }
+	}
+	hw->timeslots = tmp_timeslots;
+    }
+    else if (!strcmp(entry->name, FILENAME_FRAMING))
+    {
+	i = 0;
+	while (slicecom_framings[i].value &&
+	       strncmp(slicecom_framings[i].name, page,
+		       strlen(slicecom_framings[i].name)))
+	    i++;
+	if (!slicecom_framings[i].value)
+	{
+	    printk("slicecom: %s: Invalid " FILENAME_FRAMING " '%s'\n",
+		   dev->name, page);
+	    free_page((unsigned long)page);
+	    return -EINVAL;
+	}
+	else
+	{			/*
+				 * If somebody says:
+				 *      echo >boardnum  0
+				 *      echo >framing   no-crc4
+				 *      echo >boardnum  1
+				 * - when the framing was set, hw->boardnum was 0, so it would set the framing for board 0
+				 * Workaround: allow to set it only if interface is administrative UP
+				 */
+	    if (netif_running(dev))
+		slicecom_set_framing(hw->boardnum, slicecom_framings[i].value);
+	    else
+	    {
+		printk("%s: " FILENAME_FRAMING
+		       " can not be set while the interface is DOWN\n",
+		       dev->name);
+		free_page((unsigned long)page);
+		return -EINVAL;
+	    }
+	}
+    }
+    else if (!strcmp(entry->name, FILENAME_LINECODE))
+    {
+	i = 0;
+	while (slicecom_linecodes[i].value &&
+	       strncmp(slicecom_linecodes[i].name, page,
+		       strlen(slicecom_linecodes[i].name)))
+	    i++;
+	if (!slicecom_linecodes[i].value)
+	{
+	    printk("slicecom: %s: Invalid " FILENAME_LINECODE " '%s'\n",
+		   dev->name, page);
+	    free_page((unsigned long)page);
+	    return -EINVAL;
+	}
+	else
+	{			/*
+				 * Allow to set it only if interface is administrative UP,
+				 * for the same reason as FILENAME_FRAMING
+				 */
+	    if (netif_running(dev))
+		slicecom_set_linecode(hw->boardnum,
+				      slicecom_linecodes[i].value);
+	    else
+	    {
+		printk("%s: " FILENAME_LINECODE
+		       " can not be set while the interface is DOWN\n",
+		       dev->name);
+		free_page((unsigned long)page);
+		return -EINVAL;
+	    }
+	}
+    }
+    else if (!strcmp(entry->name, FILENAME_CLOCK_SOURCE))
+    {
+	i = 0;
+	while (slicecom_clock_sources[i].value &&
+	       strncmp(slicecom_clock_sources[i].name, page,
+		       strlen(slicecom_clock_sources[i].name)))
+	    i++;
+	if (!slicecom_clock_sources[i].value)
+	{
+	    printk("%s: Invalid " FILENAME_CLOCK_SOURCE " '%s'\n", dev->name,
+		   page);
+	    free_page((unsigned long)page);
+	    return -EINVAL;
+	}
+	else
+	{			/*
+				 * Allow to set it only if interface is administrative UP,
+				 * for the same reason as FILENAME_FRAMING
+				 */
+	    if (netif_running(dev))
+		slicecom_set_clock_source(hw->boardnum,
+					  slicecom_clock_sources[i].value);
+	    else
+	    {
+		printk("%s: " FILENAME_CLOCK_SOURCE
+		       " can not be set while the interface is DOWN\n",
+		       dev->name);
+		free_page((unsigned long)page);
+		return -EINVAL;
+	    }
+	}
+    }
+    else if (!strcmp(entry->name, FILENAME_LOOPBACK))
+    {
+	i = 0;
+	while (slicecom_loopbacks[i].value &&
+	       strncmp(slicecom_loopbacks[i].name, page,
+		       strlen(slicecom_loopbacks[i].name)))
+	    i++;
+	if (!slicecom_loopbacks[i].value)
+	{
+	    printk("%s: Invalid " FILENAME_LOOPBACK " '%s'\n", dev->name, page);
+	    free_page((unsigned long)page);
+	    return -EINVAL;
+	}
+	else
+	{			/*
+				 * Allow to set it only if interface is administrative UP,
+				 * for the same reason as FILENAME_FRAMING
+				 */
+	    if (netif_running(dev))
+		slicecom_set_loopback(hw->boardnum,
+				      slicecom_loopbacks[i].value);
+	    else
+	    {
+		printk("%s: " FILENAME_LOOPBACK
+		       " can not be set while the interface is DOWN\n",
+		       dev->name);
+		free_page((unsigned long)page);
+		return -EINVAL;
+	    }
+	}
+    }
+    else if (!strcmp(entry->name, FILENAME_REG))
+    {				/* DEL: 'reg' csak tmp */
+	char *p;
+	u32 *bar1 = board->bar1;
+
+	reg = simple_strtoul(page, &p, 0);
+	reg_ertek = simple_strtoul(p + 1, NULL, 0);
+
+	if (reg < 0x100)
+	{
+	    printk("reg(0x%02x) := 0x%08x  jiff: %lu\n", reg, reg_ertek, jiffies);
+	    writel(reg_ertek, MUNICH_VIRT(reg >> 2));
+	}
+	else
+	{
+	    printk("reg(0x%02x) is 0x%08x  jiff: %lu\n", reg - 0x100,
+		   readl(MUNICH_VIRT((reg - 0x100) >> 2)), jiffies);
+	}
+    }
+    else if (!strcmp(entry->name, FILENAME_LBIREG))
+    {				/* DEL: 'lbireg' csak tmp */
+	char *p;
+	u8 *lbi = board->lbi;
+
+	lbireg = simple_strtoul(page, &p, 0);
+	lbireg_ertek = simple_strtoul(p + 1, NULL, 0);
+
+	if (lbireg < 0x100)
+	{
+	    printk("lbireg(0x%02x) := 0x%02x  jiff: %lu\n", lbireg,
+		   lbireg_ertek, jiffies);
+	    writeb(lbireg_ertek, lbi + lbireg);
+	}
+	else
+	    printk("lbireg(0x%02x) is 0x%02x  jiff: %lu\n", lbireg - 0x100,
+		   readb(lbi + lbireg - 0x100), jiffies);
+    }
+    else
+    {
+	printk(KERN_ERR "munich_write_proc: internal error, filename %s\n",
+	       entry->name);
+	free_page((unsigned long)page);
+	return -EBADF;
+    }
+
+    /* Don't forget to free the workspace */
+    free_page((unsigned long)page);
+    return count;
+}
+
+/* 
+ * Boardtype init function.
+ * Called by the comx (upper) layer, when you set boardtype.
+ * Allocates resources associated to using munich board for this device,
+ * initializes ch_struct pointers etc.
+ * Returns 0 on success and standard error codes on error.
+ */
+
+static int init_escape(struct comx_channel *ch)
+{
+    kfree(ch->HW_privdata);
+    return -EIO;
+}
+
+static int BOARD_init(struct net_device *dev)
+{
+    struct comx_channel *ch = (struct comx_channel *)dev->priv;
+    struct slicecom_privdata *hw;
+    struct proc_dir_entry *new_file;
+
+    /* Alloc data for private structure */
+    if ((ch->HW_privdata =
+	kmalloc(sizeof(struct slicecom_privdata), GFP_KERNEL)) == NULL)
+        return -ENOMEM;
+        
+    memset(hw = ch->HW_privdata, 0, sizeof(struct slicecom_privdata));
+
+    /* Register /proc files */
+    if ((new_file = create_proc_entry(FILENAME_BOARDNUM, S_IFREG | 0644,
+			   ch->procdir)) == NULL)
+	return init_escape(ch);
+    new_file->data = (void *)new_file;
+    new_file->read_proc = &munich_read_proc;
+    new_file->write_proc = &munich_write_proc;
+//      new_file->proc_iops = &comx_normal_inode_ops;
+    new_file->nlink = 1;
+
+    if (ch->hardware == &slicecomhw)
+    {
+	if ((new_file = create_proc_entry(FILENAME_TIMESLOTS, S_IFREG | 0644,
+			       ch->procdir)) == NULL)
+	    return init_escape(ch);
+	new_file->data = (void *)new_file;
+	new_file->read_proc = &munich_read_proc;
+	new_file->write_proc = &munich_write_proc;
+//              new_file->proc_iops = &comx_normal_inode_ops;
+	new_file->nlink = 1;
+
+	if ((new_file = create_proc_entry(FILENAME_FRAMING, S_IFREG | 0644,
+			       ch->procdir)) == NULL)
+	    return init_escape(ch);
+	new_file->data = (void *)new_file;
+	new_file->read_proc = &munich_read_proc;
+	new_file->write_proc = &munich_write_proc;
+//              new_file->proc_iops = &comx_normal_inode_ops;
+	new_file->nlink = 1;
+
+	if ((new_file = create_proc_entry(FILENAME_LINECODE, S_IFREG | 0644,
+			       ch->procdir)) == NULL)
+	    return init_escape(ch);
+	new_file->data = (void *)new_file;
+	new_file->read_proc = &munich_read_proc;
+	new_file->write_proc = &munich_write_proc;
+//              new_file->proc_iops = &comx_normal_inode_ops;
+	new_file->nlink = 1;
+
+	if ((new_file = create_proc_entry(FILENAME_CLOCK_SOURCE, S_IFREG | 0644,
+			       ch->procdir)) == NULL)
+	    return init_escape(ch);
+	new_file->data = (void *)new_file;
+	new_file->read_proc = &munich_read_proc;
+	new_file->write_proc = &munich_write_proc;
+//              new_file->proc_iops = &comx_normal_inode_ops;
+	new_file->nlink = 1;
+
+	if ((new_file = create_proc_entry(FILENAME_LOOPBACK, S_IFREG | 0644,
+			       ch->procdir)) == NULL)
+	    return init_escape(ch);
+	new_file->data = (void *)new_file;
+	new_file->read_proc = &munich_read_proc;
+	new_file->write_proc = &munich_write_proc;
+//              new_file->proc_iops = &comx_normal_inode_ops;
+	new_file->nlink = 1;
+    }
+
+    /* DEL: ez itt csak fejlesztesi celokra!! */
+    if ((new_file = create_proc_entry(FILENAME_REG, S_IFREG | 0200, ch->procdir)) == NULL)
+	return init_escape(ch);
+    new_file->data = (void *)new_file;
+    new_file->read_proc = &munich_read_proc;
+    new_file->write_proc = &munich_write_proc;
+//      new_file->proc_iops = &comx_normal_inode_ops;
+    new_file->nlink = 1;
+
+    /* DEL: ez itt csak fejlesztesi celokra!! */
+    if ((new_file = create_proc_entry(FILENAME_LBIREG, S_IFREG | 0200,
+			   ch->procdir)) == NULL)
+	return init_escape(ch);
+    new_file->data = (void *)new_file;
+    new_file->read_proc = &munich_read_proc;
+    new_file->write_proc = &munich_write_proc;
+//      new_file->proc_iops = &comx_normal_inode_ops;
+    new_file->nlink = 1;
+
+    /* Fill in ch_struct hw specific pointers: */
+
+    ch->HW_txe = MUNICH_txe;
+    ch->HW_open = MUNICH_open;
+    ch->HW_close = MUNICH_close;
+    ch->HW_send_packet = MUNICH_send_packet;
+#ifndef COMX_NEW
+    ch->HW_minden = MUNICH_minden;
+#else
+    ch->HW_statistics = MUNICH_minden;
+#endif
+
+    hw->boardnum = SLICECOM_BOARDNUM_DEFAULT;
+    hw->timeslots = ch->hardware == &pcicomhw ?  0xffffffff : 2;
+
+    /* O.K. Count one more user on this module */
+    MOD_INC_USE_COUNT;
+    return 0;
+}
+
+/* 
+ * Boardtype exit function.
+ * Called by the comx (upper) layer, when you clear boardtype from munich.
+ * Frees resources associated to using munich board for this device,
+ * resets ch_struct pointers etc.
+ */
+static int BOARD_exit(struct net_device *dev)
+{
+    struct comx_channel *ch = (struct comx_channel *)dev->priv;
+    struct slicecom_privdata *hw = ch->HW_privdata;
+//    munich_board_t *board;
+
+    /* Free private data area */
+//    board = hw->boardnum + (ch->hardware == &pcicomhw ? pcicom_boards : slicecom_boards);
+
+    kfree(ch->HW_privdata);
+    /* Remove /proc files */
+    remove_proc_entry(FILENAME_BOARDNUM, ch->procdir);
+    if (ch->hardware == &slicecomhw)
+    {
+	remove_proc_entry(FILENAME_TIMESLOTS, ch->procdir);
+	remove_proc_entry(FILENAME_FRAMING, ch->procdir);
+	remove_proc_entry(FILENAME_LINECODE, ch->procdir);
+	remove_proc_entry(FILENAME_CLOCK_SOURCE, ch->procdir);
+	remove_proc_entry(FILENAME_LOOPBACK, ch->procdir);
+    }
+    remove_proc_entry(FILENAME_REG, ch->procdir);
+    remove_proc_entry(FILENAME_LBIREG, ch->procdir);
+
+    /* Minus one user for the module accounting */
+    MOD_DEC_USE_COUNT;
+    return 0;
+}
+
+static struct comx_hardware slicecomhw =
+{
+    "slicecom",
+#ifdef COMX_NEW
+    VERSION,
+#endif
+    BOARD_init,
+    BOARD_exit,
+    BOARD_dump,
+    NULL
+};
+
+static struct comx_hardware pcicomhw =
+{
+    "pcicom",
+#ifdef COMX_NEW
+    VERSION,
+#endif
+    BOARD_init,
+    BOARD_exit,
+    BOARD_dump,
+    NULL
+};
+
+/* Module management */
+
+int __init init_mister(void)
+{
+    printk(VERSIONSTR);
+    comx_register_hardware(&slicecomhw);
+    comx_register_hardware(&pcicomhw);
+    return munich_probe();
+}
+
+static void __exit cleanup_mister(void)
+{
+    int i;
+
+    comx_unregister_hardware("slicecom");
+    comx_unregister_hardware("pcicom");
+
+    for (i = 0; i < MAX_BOARDS; i++)
+    {
+	if (slicecom_boards[i].bar1)
+	    iounmap((void *)slicecom_boards[i].bar1);
+	if (slicecom_boards[i].lbi)
+	    iounmap((void *)slicecom_boards[i].lbi);
+	if (pcicom_boards[i].bar1)
+	    iounmap((void *)pcicom_boards[i].bar1);
+	if (pcicom_boards[i].lbi)
+	    iounmap((void *)pcicom_boards[i].lbi);
+    }
+}
+
+module_init(init_mister);
+module_exit(cleanup_mister);
diff -Nru a/drivers/net/wan/comx.c b/drivers/net/wan/comx.c
--- a/drivers/net/wan/comx.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/net/wan/comx.c	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  * Device driver framework for the COMX line of synchronous serial boards
  * 
- * for Linux kernel 2.2.X
+ * for Linux kernel 2.2.X / 2.4.X
  *
  * Original authors:  Arpad Bakay <bakay.arpad@synergon.hu>,
  *                    Peter Bajan <bajan.peter@synergon.hu>,
diff -Nru a/drivers/net/wan/falc-lh.h b/drivers/net/wan/falc-lh.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/net/wan/falc-lh.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,102 @@
+/*
+ *	Defines for comx-hw-slicecom.c - FALC-LH specific
+ *
+ *	Author:		Bartok Istvan <bartoki@itc.hu>
+ *	Last modified:	Mon Feb  7 20:00:38 CET 2000
+ *
+ *	:set tabstop=6
+ */
+
+/*
+ *	Control register offsets on the LBI (page 90)
+ *	use it like:
+ *	lbi[ MODE ] = 0x34;
+ */
+
+#define MODE	0x03
+#define IPC		0x08
+#define IMR0	0x14	/* Interrupt Mask Register 0	*/
+#define IMR1	0x15
+#define IMR2	0x16
+#define IMR3	0x17
+#define IMR4	0x18
+#define IMR5	0x19
+#define FMR0	0x1a	/* Framer Mode Register 0	*/
+#define FMR1	0x1b
+#define FMR2	0x1c
+#define XSW		0x1e
+#define XSP		0x1f
+#define XC0		0x20
+#define XC1		0x21
+#define RC0		0x22
+#define RC1		0x23
+#define XPM0	0x24
+#define XPM1	0x25
+#define XPM2	0x26
+#define TSWM	0x27
+#define IDLE	0x29	/* Idle Code	*/
+#define LIM0	0x34
+#define LIM1	0x35
+#define PCD		0x36
+#define PCR		0x37
+#define LIM2	0x38
+
+/*
+ *	Status registers on the LBI (page 134)
+ *	these are read-only, use it like:
+ *	if( lbi[ FRS0 ] ) ...
+ */
+
+#define FRS0	0x4c	/* Framer Receive Status register 0	*/
+#define FRS1	0x4d	/* Framer Receive Status register 1	*/
+#define FECL	0x50	/* Framing Error Counter low byte	*/ /* Counts FAS word receive errors		*/
+#define FECH	0x51	/*                       high byte	*/
+#define CVCL	0x52	/* Code Violation Counter low byte	*/ /* Counts bipolar and HDB3 code violations	*/
+#define CVCH	0x53	/*                        high byte	*/
+#define CEC1L	0x54	/* CRC4 Error Counter 1 low byte	*/ /* Counts CRC4 errors in the incoming stream	*/
+#define CEC1H	0x55	/*                      high byte	*/
+#define EBCL	0x56	/* E Bit error Counter low byte	*/ /* E-bits: the remote end sends them, when	*/
+#define EBCH	0x57	/*                     high byte	*/ /* it detected a CRC4-error			*/
+#define ISR0	0x68	/* Interrupt Status Register 0	*/
+#define ISR1	0x69	/* Interrupt Status Register 1	*/
+#define ISR2	0x6a	/* Interrupt Status Register 2	*/
+#define ISR3	0x6b	/* Interrupt Status Register 3	*/
+#define ISR5	0x6c	/* Interrupt Status Register 5	*/
+#define GIS	0x6e	/* Global Interrupt Status Register	*/
+#define VSTR	0x6f	/* version information */
+
+/*
+ *	Bit fields
+ */
+
+#define FRS0_LOS		(1 << 7)
+#define FRS0_AIS		(1 << 6)
+#define FRS0_LFA		(1 << 5)
+#define FRS0_RRA		(1 << 4)
+#define FRS0_AUXP		(1 << 3)
+#define FRS0_NMF		(1 << 2)
+#define FRS0_LMFA		(1 << 1)
+
+#define FRS1_XLS		(1 << 1)
+#define FRS1_XLO		(1)
+
+#define ISR2_FAR		(1 << 7)
+#define ISR2_LFA		(1 << 6)
+#define ISR2_MFAR		(1 << 5)
+#define ISR2_T400MS	(1 << 4)
+#define ISR2_AIS		(1 << 3)
+#define ISR2_LOS		(1 << 2)
+#define ISR2_RAR		(1 << 1)
+#define ISR2_RA		(1)
+
+#define ISR3_ES		(1 << 7)
+#define ISR3_SEC		(1 << 6)
+#define ISR3_LMFA16	(1 << 5)
+#define ISR3_AIS16	(1 << 4)
+#define ISR3_RA16		(1 << 3)
+#define ISR3_API		(1 << 2)
+#define ISR3_RSN		(1 << 1)
+#define ISR3_RSP		(1)
+
+#define ISR5_XSP		(1 << 7)
+#define ISR5_XSN		(1 << 6)
diff -Nru a/drivers/net/wan/munich32x.h b/drivers/net/wan/munich32x.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/net/wan/munich32x.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,191 @@
+/*
+ *	Defines for comx-hw-slicecom.c - MUNICH32X specific
+ *
+ *	Author:        Bartok Istvan <bartoki@itc.hu>
+ *	Last modified: Tue Jan 11 14:27:36 CET 2000
+ *
+ *	:set tabstop=6
+ */
+
+#define TXBUFFER_SIZE	1536			/* Max mennyit tud a kartya hardver atvenni				*/
+#define RXBUFFER_SIZE	(TXBUFFER_SIZE+4)	/* For Rx reasons it must be a multiple of 4, and =>4 (page 265)	*/
+							/* +4 .. see page 265, bit FE							*/
+							/* TOD: a MODE1-be nem is ezt teszem, hanem a TXBUFFER-t, lehet hogy nem is kell? */
+
+//#define PCI_VENDOR_ID_SIEMENS			0x110a
+#define PCI_DEVICE_ID_SIEMENS_MUNICH32X	0x2101
+
+/*
+ *	PCI config space registers (page 120)
+ */
+
+#define MUNICH_PCI_PCIRES	0x4c		/* 0xe0000 resets	the chip	*/
+
+
+/*
+ *	MUNICH slave register offsets relative to base_address[0] (PCI BAR1) (page 181):
+ *	offsets are in bytes, registers are u32's, so we need a >>2 for indexing
+ *	the int[] by byte offsets. Use it like:
+ *
+ *	bar1[ STAT ] = ~0L;  or
+ *	x = bar1[ STAT ];
+ */
+
+#define CONF	(0x00 >> 2)
+#define CMD		(0x04 >> 2)
+#define STAT	(0x08 >> 2)
+#define STACK	(0x08 >> 2)
+#define IMASK	(0x0c >> 2)
+#define PIQBA	(0x14 >> 2)
+#define PIQL	(0x18 >> 2)
+#define MODE1	(0x20 >> 2)
+#define MODE2	(0x24 >> 2)
+#define CCBA	(0x28 >> 2)
+#define TXPOLL	(0x2c >> 2)
+#define TIQBA	(0x30 >> 2)
+#define TIQL	(0x34 >> 2)
+#define RIQBA	(0x38 >> 2)
+#define RIQL	(0x3c >> 2)
+#define LCONF	(0x40 >> 2)		/* LBI Configuration Register		*/
+#define LCCBA	(0x44 >> 2)		/* LBI Configuration Control Block	*/	/* DE: lehet hogy nem is kell? */
+#define LTIQBA	(0x50 >> 2)		/* DE: lehet hogy nem is kell? page 210: LBI DMA Controller intq - nem hasznalunk DMA-t.. */
+#define LTIQL	(0x54 >> 2)		/* DE: lehet hogy nem is kell? */
+#define LRIQBA	(0x58 >> 2)		/* DE: lehet hogy nem is kell? */
+#define LRIQL	(0x5c >> 2)		/* DE: lehet hogy nem is kell? */
+#define LREG0	(0x60 >> 2)		/* LBI Indirect External Configuration register 0	*/
+#define LREG1	(0x64 >> 2)
+#define LREG2	(0x68 >> 2)
+#define LREG3	(0x6c >> 2)
+#define LREG4	(0x70 >> 2)
+#define LREG5	(0x74 >> 2)
+#define LREG6	(0x78 >> 2)		/* LBI Indirect External Configuration register 6		*/
+#define LSTAT	(0x7c >> 2)		/* LBI Status Register							*/
+#define GPDIR	(0x80 >> 2)		/* General Purpose Bus DIRection - 0..input, 1..output	*/
+#define GPDATA	(0x84 >> 2)		/* General Purpose Bus DATA						*/
+
+
+/*
+ *	MUNICH commands: (they go into register CMD)
+ */
+
+#define CMD_ARPCM	0x01			/* Action Request Serial PCM Core	*/
+#define CMD_ARLBI	0x02			/* Action Request LBI			*/
+
+
+/*
+ *	MUNICH event bits in the STAT, STACK, IMASK registers (page 188,189)
+ */
+
+#define STAT_PTI	(1 << 15)
+#define STAT_PRI	(1 << 14)
+#define STAT_LTI	(1 << 13)
+#define STAT_LRI	(1 << 12)
+#define STAT_IOMI	(1 << 11)
+#define STAT_SSCI	(1 << 10)
+#define STAT_LBII	(1 << 9)
+#define STAT_MBI	(1 << 8)
+
+#define STAT_TI	(1 << 6)
+#define STAT_TSPA	(1 << 5)
+#define STAT_RSPA	(1 << 4)
+#define STAT_LBIF	(1 << 3)
+#define STAT_LBIA	(1 << 2)
+#define STAT_PCMF	(1 << 1)
+#define STAT_PCMA	(1) 
+
+/*
+ *	We do not handle these (and do not touch their STAT bits) in the interrupt loop
+ */
+
+#define STAT_NOT_HANDLED_BY_INTERRUPT	(STAT_PCMF | STAT_PCMA)
+
+
+/*
+ *	MUNICH MODE1/MODE2 slave register fields (page 193,196)
+ *	these are not all masks, MODE1_XX_YY are my magic values!
+ */
+
+#define MODE1_PCM_E1	(1 << 31)		/* E1, 2.048 Mbit/sec		*/
+#define MODE1_TBS_4	(1 << 24)		/* TBS = 4 .. no Tx bit shift	*/
+#define MODE1_RBS_4	(1 << 18)		/* RBS = 4 .. no Rx bit shift	*/
+#define MODE1_REN		(1 << 15)		/* Rx Enable			*/
+#define MODE1_MFL_MY	TXBUFFER_SIZE	/* Maximum Frame Length		*/
+#define MODE1_MAGIC	(MODE1_PCM_E1 | MODE1_TBS_4 | MODE1_RBS_4 | MODE1_REN | MODE1_MFL_MY)
+
+#define MODE2_HPOLL	(1 << 8)		/* Hold Poll			*/
+#define MODE2_SPOLL	(1 << 7)		/* Slow Poll			*/
+#define MODE2_TSF		(1)			/* real magic - discovered by probing :)	*/
+// #define MODE2_MAGIC	(MODE2_TSF)
+#define MODE2_MAGIC	(MODE2_SPOLL | MODE2_TSF)
+
+
+/*
+ *	LCONF bits (page 205)
+ *	these are not all masks, LCONF_XX_YY are my magic values!
+ */
+
+#define LCONF_IPA			(1 << 31)	/* Interrupt Pass. Use 1 for FALC54							*/
+#define LCONF_DCA			(1 << 30)	/* Disregard the int's for Channel A - DMSM does not try to handle them	*/
+#define LCONF_DCB			(1 << 29)	/* Disregard the int's for Channel B						*/
+#define LCONF_EBCRES		(1 << 22)	/* Reset LBI External Bus Controller, 0..reset, 1..normal operation	*/
+#define LCONF_LBIRES		(1 << 21)	/* Reset LBI DMSM, 0..reset, 1..normal operation				*/
+#define LCONF_BTYP_16DEMUX	(1 << 7)	/* 16-bit demultiplexed bus	*/
+#define LCONF_ABM			(1 << 4)	/* Arbitration Master		*/
+
+/* writing LCONF_MAGIC1 followed by a LCONF_MAGIC2 into LCONF resets the EBC and DMSM: */
+
+#define LCONF_MAGIC1		(LCONF_BTYP_16DEMUX | LCONF_ABM | LCONF_IPA | LCONF_DCA | LCONF_DCB)
+#define LCONF_MAGIC2		(LCONF_MAGIC1 | LCONF_EBCRES | LCONF_LBIRES)
+
+
+/*
+ *	LREGx magic values if a FALC54 is on the LBI (page 217)
+ */
+
+#define LREG0_MAGIC	0x00000264
+#define LREG1_MAGIC	0x6e6a6b66
+#define LREG2_MAGIC	0x00000264
+#define LREG3_MAGIC	0x6e686966
+#define LREG4_MAGIC	0x00000000
+#define LREG5_MAGIC	( (7<<27) | (3<<24) | (1<<21) | (7<<3) | (2<<9) )
+
+
+/*
+ *	PCM Action Specification fields (munich_ccb_t.action_spec)
+ */
+
+#define CCB_ACTIONSPEC_IN			(1 << 15)	/* init				*/
+#define CCB_ACTIONSPEC_ICO			(1 << 14)	/* init only this channel	*/
+#define CCB_ACTIONSPEC_RES			(1 << 6)	/* reset all channels		*/
+#define CCB_ACTIONSPEC_LOC			(1 << 5)
+#define CCB_ACTIONSPEC_LOOP			(1 << 4)
+#define CCB_ACTIONSPEC_LOOPI			(1 << 3)
+#define CCB_ACTIONSPEC_IA			(1 << 2)
+
+
+/*
+ *	Interrupt Information bits in the TIQ, RIQ
+ */
+
+#define PCM_INT_HI	(1 << 12)
+#define PCM_INT_FI	(1 << 11)
+#define PCM_INT_IFC	(1 << 10)
+#define PCM_INT_SF	(1 << 9)
+#define PCM_INT_ERR	(1 << 8)
+#define PCM_INT_FO	(1 << 7)
+#define PCM_INT_FE2	(1 << 6)
+
+#define PCM_INT_CHANNEL( info )	(info & 0x1F)
+
+
+/*
+ *	Rx status info in the rx_desc_t.status
+ */
+
+#define RX_STATUS_SF	(1 << 6)
+#define RX_STATUS_LOSS	(1 << 5)
+#define RX_STATUS_CRCO	(1 << 4)
+#define RX_STATUS_NOB	(1 << 3)
+#define RX_STATUS_LFD	(1 << 2)
+#define RX_STATUS_RA	(1 << 1)
+#define RX_STATUS_ROF	1 
diff -Nru a/drivers/parport/parport_cs.c b/drivers/parport/parport_cs.c
--- a/drivers/parport/parport_cs.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/parport/parport_cs.c	Fri Mar 15 17:51:03 2002
@@ -45,6 +45,7 @@
 #include <linux/string.h>
 #include <linux/timer.h>
 #include <linux/ioport.h>
+#include <linux/major.h>
 
 #include <linux/parport.h>
 #include <linux/parport_pc.h>
@@ -106,7 +107,6 @@
 static dev_link_t *dev_list = NULL;
 
 extern struct parport_operations parport_pc_ops;
-static struct parport_operations parport_cs_ops;
 
 /*====================================================================*/
 
@@ -458,13 +458,6 @@
 	       "does not match!\n");
 	return -1;
     }
-
-#if (LINUX_VERSION_CODE < VERSION(2,3,6))
-    /* This is to protect against unloading modules out of order */
-    parport_cs_ops = parport_pc_ops;
-    parport_cs_ops.inc_use_count = &inc_use_count;
-    parport_cs_ops.dec_use_count = &dec_use_count;
-#endif
 
     register_pccard_driver(&dev_info, &parport_attach, &parport_detach);
     return 0;
diff -Nru a/drivers/pci/pci.c b/drivers/pci/pci.c
--- a/drivers/pci/pci.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/pci/pci.c	Fri Mar 15 17:51:02 2002
@@ -849,18 +849,19 @@
 	pcibios_set_master(dev);
 }
 
+#ifndef HAVE_ARCH_PCI_MWI
 /**
- * pdev_set_mwi - arch helper function for pcibios_set_mwi
+ * pci_generic_prep_mwi - helper function for pci_set_mwi
  * @dev: the PCI device for which MWI is enabled
  *
- * Helper function for implementation the arch-specific pcibios_set_mwi
+ * Helper function for generic implementation of pcibios_prep_mwi
  * function.  Originally copied from drivers/net/acenic.c.
  * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
  *
- * RETURNS: An appriopriate -ERRNO error value on eror, or zero for success.
+ * RETURNS: An appropriate -ERRNO error value on eror, or zero for success.
  */
-int
-pdev_set_mwi(struct pci_dev *dev)
+static int
+pci_generic_prep_mwi(struct pci_dev *dev)
 {
 	int rc = 0;
 	u8 cache_size;
@@ -874,8 +875,8 @@
 	pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cache_size);
 	cache_size <<= 2;
 	if (cache_size != SMP_CACHE_BYTES) {
-		printk(KERN_WARNING "PCI: %s PCI cache line size set incorrectly "
-		       "(%i bytes) by BIOS/FW, ",
+		printk(KERN_WARNING "PCI: %s PCI cache line size set "
+		       "incorrectly (%i bytes) by BIOS/FW, ",
 		       dev->slot_name, cache_size);
 		if (cache_size > SMP_CACHE_BYTES) {
 			printk("expecting %i\n", SMP_CACHE_BYTES);
@@ -889,6 +890,7 @@
 
 	return rc;
 }
+#endif /* !HAVE_ARCH_PCI_MWI */
 
 /**
  * pci_set_mwi - enables memory-write-validate PCI transaction
@@ -907,9 +909,9 @@
 	u16 cmd;
 
 #ifdef HAVE_ARCH_PCI_MWI
-	rc = pcibios_set_mwi(dev);
+	rc = pcibios_prep_mwi(dev);
 #else
-	rc = pdev_set_mwi(dev);
+	rc = pci_generic_prep_mwi(dev);
 #endif
 
 	if (rc)
@@ -1011,13 +1013,15 @@
 			l = 0;
 		if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 			res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
+			res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
 			sz = pci_size(sz, PCI_BASE_ADDRESS_MEM_MASK);
 		} else {
 			res->start = l & PCI_BASE_ADDRESS_IO_MASK;
+			res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
 			sz = pci_size(sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
 		}
 		res->end = res->start + (unsigned long) sz;
-		res->flags |= (l & 0xf) | pci_calc_resource_flags(l);
+		res->flags |= pci_calc_resource_flags(l);
 		if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 		    == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 			pci_read_config_dword(dev, reg+4, &l);
@@ -2001,16 +2005,16 @@
 	int			map, block;
 
 	if ((page = pool_find_page (pool, dma)) == 0) {
-		printk (KERN_ERR "pci_pool_free %s/%s, %p/%x (bad dma)\n",
+		printk (KERN_ERR "pci_pool_free %s/%s, %p/%lx (bad dma)\n",
 			pool->dev ? pool->dev->slot_name : NULL,
-			pool->name, vaddr, (int) (dma & 0xffffffff));
+			pool->name, vaddr, (unsigned long) dma);
 		return;
 	}
 #ifdef	CONFIG_PCIPOOL_DEBUG
 	if (((dma - page->dma) + (void *)page->vaddr) != vaddr) {
-		printk (KERN_ERR "pci_pool_free %s/%s, %p (bad vaddr)/%x\n",
+		printk (KERN_ERR "pci_pool_free %s/%s, %p (bad vaddr)/%lx\n",
 			pool->dev ? pool->dev->slot_name : NULL,
-			pool->name, vaddr, (int) (dma & 0xffffffff));
+			pool->name, vaddr, (unsigned long) dma);
 		return;
 	}
 #endif
@@ -2099,7 +2103,6 @@
 EXPORT_SYMBOL(pci_set_master);
 EXPORT_SYMBOL(pci_set_mwi);
 EXPORT_SYMBOL(pci_clear_mwi);
-EXPORT_SYMBOL(pdev_set_mwi);
 EXPORT_SYMBOL(pci_set_dma_mask);
 EXPORT_SYMBOL(pci_dac_set_dma_mask);
 EXPORT_SYMBOL(pci_assign_resource);
diff -Nru a/drivers/pcmcia/i82092.c b/drivers/pcmcia/i82092.c
--- a/drivers/pcmcia/i82092.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/pcmcia/i82092.c	Fri Mar 15 17:51:03 2002
@@ -37,6 +37,7 @@
 	 },
 	 {} 
 };
+MODULE_DEVICE_TABLE(pci, i82092aa_pci_ids);
 
 static struct pci_driver i82092aa_pci_drv = {
 	name:           "i82092aa",
@@ -91,42 +92,41 @@
 static int __init i82092aa_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
 	unsigned char configbyte;
-	int i;
+	int i, ret;
 	
 	enter("i82092aa_pci_probe");
 	
-	if (pci_enable_device(dev))
-		return -EIO;
+	if ((ret = pci_enable_device(dev)))
+		return ret;
 		
 	pci_read_config_byte(dev, 0x40, &configbyte);  /* PCI Configuration Control */
 	switch(configbyte&6) {
 		case 0:
-			printk(KERN_INFO "i82092aa: configured as a 2 socket device.\n");
 			socket_count = 2;
 			break;
 		case 2:
-			printk(KERN_INFO "i82092aa: configured as a 1 socket device.\n");
 			socket_count = 1;
 			break;
 		case 4:
 		case 6:
-			printk(KERN_INFO "i82092aa: configured as a 4 socket device.\n");
 			socket_count = 4;
 			break;
 			
 		default:
 			printk(KERN_ERR "i82092aa: Oops, you did something we didn't think of.\n");
-			return -EIO;
-			break;
+			ret = -EIO;
+			goto err_out_disable;
+	}
+	printk(KERN_INFO "i82092aa: configured as a %d socket device.\n", socket_count);
+
+	if (request_region(pci_resource_start(dev, 0), 2, "i82092aa")) {
+		ret = -EBUSY;
+		goto err_out_disable;
 	}
 	
 	for (i = 0;i<socket_count;i++) {
 		sockets[i].card_state = 1; /* 1 = present but empty */
-		sockets[i].io_base = (dev->resource[0].start & ~1);
-		 if (sockets[i].io_base > 0) 
-		 	request_region(sockets[i].io_base, 2, "i82092aa");
-		 
-		
+		sockets[i].io_base = pci_resource_start(dev, 0);
 		sockets[i].cap.features |= SS_CAP_PCCARD;
 		sockets[i].cap.map_size = 0x1000;
 		sockets[i].cap.irq_mask = 0;
@@ -144,20 +144,28 @@
 	configbyte = 0xFF; /* bitmask, one bit per event, 1 = PCI interrupt, 0 = ISA interrupt */
 	pci_write_config_byte(dev, 0x50, configbyte); /* PCI Interrupt Routing Register */
 
-
 	/* Register the interrupt handler */
 	dprintk(KERN_DEBUG "Requesting interrupt %i \n",dev->irq);
-	if (request_irq(dev->irq, i82092aa_interrupt, SA_SHIRQ, "i82092aa", i82092aa_interrupt)) {
+	if ((ret = request_irq(dev->irq, i82092aa_interrupt, SA_SHIRQ, "i82092aa", i82092aa_interrupt))) {
 		printk(KERN_ERR "i82092aa: Failed to register IRQ %d, aborting\n", dev->irq);
-		return -EIO;
+		goto err_out_free_res;
 	}
 		 
-	
-	if (register_ss_entry(socket_count, &i82092aa_operations) != 0)
-		printk(KERN_NOTICE "i82092aa: register_ss_entry() failed\n");
+	if ((ret = register_ss_entry(socket_count, &i82092aa_operations) != 0)) {
+		printk(KERN_ERR "i82092aa: register_ss_entry() failed\n");
+		goto err_out_free_irq;
+	}
 
 	leave("i82092aa_pci_probe");
 	return 0;
+
+err_out_free_irq:
+	free_irq(dev->irq, i82092aa_interrupt);
+err_out_free_res:
+	release_region(pci_resource_start(dev, 0), 2);
+err_out_disable:
+	pci_disable_device(dev);
+	return ret;			
 }
 
 static void __exit i82092aa_pci_remove(struct pci_dev *dev)
diff -Nru a/drivers/pcmcia/sa1100_generic.c b/drivers/pcmcia/sa1100_generic.c
--- a/drivers/pcmcia/sa1100_generic.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/pcmcia/sa1100_generic.c	Fri Mar 15 17:51:01 2002
@@ -83,6 +83,68 @@
 static struct tq_struct sa1100_pcmcia_task;
 
 /*
+ * sa1100_pcmcia_default_mecr_timing
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * Calculate MECR clock wait states for given CPU clock
+ * speed and command wait state. This function can be over-
+ * written by a board specific version.
+ *
+ * The default is to simply calculate the BS values as specified in
+ * the INTEL SA1100 development manual
+ * "Expansion Memory (PCMCIA) Configuration Register (MECR)"
+ * that's section 10.2.5 in _my_ version of the manuial ;)
+ */
+static int sa1100_pcmcia_default_mecr_timing(unsigned int sock, unsigned int cpu_speed,
+		unsigned int cmd_time )
+{
+	return sa1100_pcmcia_mecr_bs( cmd_time, cpu_speed );
+}
+
+/* sa1100_pcmcia_set_mecr()
+ * ^^^^^^^^^^^^^^^^^^^^^^^^^^^
+ *
+ * set MECR value for socket <sock> based on this sockets
+ * io, mem and attribute space access speed.
+ * Call board specific BS value calculation to allow boards
+ * to tweak the BS values.
+ */
+static int sa1100_pcmcia_set_mecr( int sock )
+{
+	struct sa1100_pcmcia_socket *skt;
+	u32 mecr;
+	int clock;
+	long flags;
+	unsigned int bs;
+
+	if ( sock<0 || sock>SA1100_PCMCIA_MAX_SOCK )
+		return -1;
+
+	skt = PCMCIA_SOCKET( sock );
+
+	local_irq_save(flags);
+
+	clock = cpufreq_get(0);
+	bs = pcmcia_low_level->socket_get_timing( sock, clock, skt->speed_io);
+
+	mecr = MECR;
+	MECR_FAST_SET(mecr, sock, 0);
+	MECR_BSIO_SET(mecr, sock, bs );
+	MECR_BSA_SET(mecr, sock, bs );
+	MECR_BSM_SET(mecr, sock, bs );
+	MECR = mecr;
+
+	local_irq_restore(flags);
+
+    DEBUG(4, "%s(): FAST%u %lx  BSM%u %lx  BSA%u %lx  BSIO%u %lx\n",
+	  __FUNCTION__, sock, MECR_FAST_GET(mecr, sock), sock,
+	  MECR_BSM_GET(mecr, sock), sock, MECR_BSA_GET(mecr, sock),
+	  sock, MECR_BSIO_GET(mecr, sock));
+
+	return 0;
+}
+
+/*
  * sa1100_pcmcia_state_to_config
  * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
  *
@@ -586,26 +648,10 @@
   }
 
   if (map->flags & MAP_ACTIVE) {
-    unsigned int clock, speed = map->speed;
-    unsigned long mecr;
-
-    if (speed == 0)
-      speed = SA1100_PCMCIA_IO_ACCESS;
+    if ( map->speed == 0)
+       map->speed = SA1100_PCMCIA_IO_ACCESS;
 
-    clock = cpufreq_get(0);
-
-    mecr = MECR;
-
-    MECR_BSIO_SET(mecr, sock, sa1100_pcmcia_mecr_bs(speed, clock));
-
-    skt->speed_io = speed;
-
-    DEBUG(4, "%s(): FAST%u %lx  BSM%u %lx  BSA%u %lx  BSIO%u %lx\n",
-	  __FUNCTION__, sock, MECR_FAST_GET(mecr, sock), sock,
-	  MECR_BSM_GET(mecr, sock), sock, MECR_BSA_GET(mecr, sock), 
-	  sock, MECR_BSIO_GET(mecr, sock));
-
-    MECR = mecr;
+	sa1100_pcmcia_set_mecr( sock );
   }
 
   if (map->stop == 1)
@@ -683,39 +729,19 @@
   }
 
   if (map->flags & MAP_ACTIVE) {
-    unsigned int clock, speed = map->speed;
-    unsigned long mecr;
-
-    /*
-     * When clients issue RequestMap, the access speed is not always
-     * properly configured.  Choose some sensible defaults.
-     */
-    if (speed == 0) {
-      if (skt->cs_state.Vcc == 33)
-	speed = SA1100_PCMCIA_3V_MEM_ACCESS;
-      else
-	speed = SA1100_PCMCIA_5V_MEM_ACCESS;
-    }
-
-    clock = cpufreq_get(0);
+	  /*
+	   * When clients issue RequestMap, the access speed is not always
+	   * properly configured.  Choose some sensible defaults.
+	   */
+	  if (map->speed == 0) {
+		  if (skt->cs_state.Vcc == 33)
+			  map->speed = SA1100_PCMCIA_3V_MEM_ACCESS;
+		  else
+			  map->speed = SA1100_PCMCIA_5V_MEM_ACCESS;
+	  }
 
-    /* Fixme: MECR is not pre-empt safe. */
-    mecr = MECR;
+	  sa1100_pcmcia_set_mecr( sock );
 
-    if (map->flags & MAP_ATTRIB) {
-      MECR_BSA_SET(mecr, sock, sa1100_pcmcia_mecr_bs(speed, clock));
-      skt->speed_attr = speed;
-    } else {
-      MECR_BSM_SET(mecr, sock, sa1100_pcmcia_mecr_bs(speed, clock));
-      skt->speed_mem = speed;
-    }
-
-    DEBUG(4, "%s(): FAST%u %lx  BSM%u %lx  BSA%u %lx  BSIO%u %lx\n",
-	  __FUNCTION__, sock, MECR_FAST_GET(mecr, sock), sock,
-	  MECR_BSM_GET(mecr, sock), sock, MECR_BSA_GET(mecr, sock), 
-	  sock, MECR_BSIO_GET(mecr, sock));
-
-    MECR = mecr;
   }
 
   start = (map->flags & MAP_ATTRIB) ? skt->phys_attr : skt->phys_mem;
@@ -857,20 +883,10 @@
 static void sa1100_pcmcia_update_mecr(unsigned int clock)
 {
   unsigned int sock;
-  unsigned long mecr = MECR;
 
-  for(sock = 0; sock < SA1100_PCMCIA_MAX_SOCK; ++sock){
-    struct sa1100_pcmcia_socket *skt = PCMCIA_SOCKET(sock);
-
-    MECR_BSIO_SET(mecr, sock,
-		  sa1100_pcmcia_mecr_bs(skt->speed_io, clock));
-    MECR_BSA_SET(mecr, sock,
-		 sa1100_pcmcia_mecr_bs(skt->speed_attr, clock));
-    MECR_BSM_SET(mecr, sock,
-		 sa1100_pcmcia_mecr_bs(skt->speed_mem, clock));
+  for (sock = 0; sock < SA1100_PCMCIA_MAX_SOCK; ++sock) {
+	  sa1100_pcmcia_set_mecr( sock );
   }
-
-  MECR = mecr;
 }
 
 /* sa1100_pcmcia_notifier()
@@ -929,8 +945,7 @@
 	struct pcmcia_init pcmcia_init;
 	struct pcmcia_state state[SA1100_PCMCIA_MAX_SOCK];
 	struct pcmcia_state_array state_array;
-	unsigned int i, clock;
-	unsigned long mecr;
+	unsigned int i;
 	int ret;
 
 	/*
@@ -941,6 +956,13 @@
 
 	pcmcia_low_level = ops;
 
+	/*
+	 * set default MECR calculation if the board specific
+	 * code did not specify one...
+	 */
+	if (!pcmcia_low_level->socket_get_timing)
+		pcmcia_low_level->socket_get_timing = sa1100_pcmcia_default_mecr_timing;
+
 	pcmcia_init.handler = sa1100_pcmcia_interrupt;
 	ret = ops->init(&pcmcia_init);
 	if (ret < 0) {
@@ -967,10 +989,6 @@
 	 * We initialize the MECR to default values here, because we are
 	 * not guaranteed to see a SetIOMap operation at runtime.
 	 */
-	mecr = 0;
-
-	clock = cpufreq_get(0);
-
 	for (i = 0; i < sa1100_pcmcia_socket_count; i++) {
 		struct sa1100_pcmcia_socket *skt = PCMCIA_SOCKET(i);
 		struct pcmcia_irq_info irq_info;
@@ -1000,13 +1018,9 @@
 			goto out_err;
 		}
 
-		MECR_FAST_SET(mecr, i, 0);
-		MECR_BSIO_SET(mecr, i, sa1100_pcmcia_mecr_bs(skt->speed_io, clock));
-		MECR_BSA_SET(mecr, i, sa1100_pcmcia_mecr_bs(skt->speed_attr, clock));
-		MECR_BSM_SET(mecr, i, sa1100_pcmcia_mecr_bs(skt->speed_mem, clock));
+		sa1100_pcmcia_set_mecr( i );
 	}
 
-	MECR = mecr;
 
 	/* Only advertise as many sockets as we can detect */
 	ret = register_ss_entry(sa1100_pcmcia_socket_count,
diff -Nru a/drivers/pcmcia/sa1100_generic.h b/drivers/pcmcia/sa1100_generic.h
--- a/drivers/pcmcia/sa1100_generic.h	Fri Mar 15 17:51:01 2002
+++ b/drivers/pcmcia/sa1100_generic.h	Fri Mar 15 17:51:01 2002
@@ -69,6 +69,12 @@
    * Disable card status IRQs and PCMCIA bus on suspend.
    */
   int (*socket_suspend)(int sock);
+
+  /*
+   * Calculate MECR timing clock wait states
+   */
+  int (*socket_get_timing)(unsigned int sock, unsigned int cpu_speed,
+		  unsigned int cmd_time );
 };
 
 extern int sa1100_register_pcmcia(struct pcmcia_low_level *);
diff -Nru a/drivers/pnp/Makefile b/drivers/pnp/Makefile
--- a/drivers/pnp/Makefile	Fri Mar 15 17:51:01 2002
+++ b/drivers/pnp/Makefile	Fri Mar 15 17:51:01 2002
@@ -11,7 +11,7 @@
 O_TARGET := pnp.o
 
 export-objs := isapnp.o pnpbios_core.o
-multi-objs := isa-pnp.o pnpbios.o
+list-multi := isa-pnp.o pnpbios.o
 
 isa-pnp-proc-$(CONFIG_PROC_FS) = isapnp_proc.o
 pnpbios-proc-$(CONFIG_PROC_FS) = pnpbios_proc.o
diff -Nru a/drivers/scsi/ide-scsi.c b/drivers/scsi/ide-scsi.c
--- a/drivers/scsi/ide-scsi.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/scsi/ide-scsi.c	Fri Mar 15 17:51:01 2002
@@ -290,7 +290,7 @@
 			if (!test_bit(PC_WRITING, &pc->flags) && pc->actually_transferred && pc->actually_transferred <= 1024 && pc->buffer) {
 				printk(", rst = ");
 				scsi_buf = pc->scsi_cmd->request_buffer;
-				hexdump(scsi_buf, min(16, pc->scsi_cmd->request_bufflen));
+				hexdump(scsi_buf, min(16U, pc->scsi_cmd->request_bufflen));
 			} else printk("\n");
 		}
 	}
@@ -307,7 +307,7 @@
 
 static inline unsigned long get_timeout(idescsi_pc_t *pc)
 {
-	return max(WAIT_CMD, pc->timeout - jiffies);
+	return max((unsigned long) WAIT_CMD, pc->timeout - jiffies);
 }
 
 /*
@@ -350,7 +350,7 @@
 
 	if (ireason & IDESCSI_IREASON_COD) {
 		printk (KERN_ERR "ide-scsi: CoD != 0 in idescsi_pc_intr\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	if (ireason & IDESCSI_IREASON_IO) {
 		temp = pc->actually_transferred + bcount;
@@ -411,7 +411,7 @@
 	ireason = IN_BYTE (IDE_IREASON_REG);
 	if ((ireason & (IDESCSI_IREASON_IO | IDESCSI_IREASON_COD)) != IDESCSI_IREASON_COD) {
 		printk (KERN_ERR "ide-scsi: (IO,CoD) != (0,1) while issuing a packet command\n");
-		return ide_do_reset (drive);
+		return ide_stopped;
 	}
 	ide_set_handler(drive, &idescsi_pc_intr, get_timeout(pc), NULL);	/* Set the interrupt routine */
 	atapi_output_bytes (drive, scsi->pc->c, 12);			/* Send the actual packet */
@@ -565,7 +565,7 @@
 /*
  *	idescsi_init will register the driver for each scsi.
  */
-static int idescsi_init(void)
+int idescsi_init(void)
 {
 	ide_drive_t *drive;
 	idescsi_scsi_t *scsi;
diff -Nru a/drivers/usb/Config.help b/drivers/usb/Config.help
--- a/drivers/usb/Config.help	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/Config.help	Fri Mar 15 17:51:02 2002
@@ -170,6 +170,18 @@
   The module will be called audio.o. If you want to compile it as a
   module, say M here and read <file:Documentation/modules.txt>.
 
+CONFIG_USB_EMI26
+  This driver loads firmware to Emagic EMI 2|6 low latency USB
+  Audio interface.
+
+  After firmware load the device is handled with standard linux
+  USB Audio driver.
+
+  This code is also available as a module ( = code which can be
+  inserted in and removed from the running kernel whenever you want).
+  The module will be called audio.o. If you want to compile it as a
+  module, say M here and read <file:Documentation/modules.txt>.
+
 CONFIG_USB_ACM
   This driver supports USB modems and ISDN adapters which support the
   Communication Device Class Abstract Control Model interface.
@@ -316,12 +328,12 @@
   module, say M here and read <file:Documentation/modules.txt>.
 
 CONFIG_USB_PEGASUS
-  Say Y here if you know you have Pegasus or Pegasus II based adapter.
+  Say Y here if you know you have Pegasus or Pegasus-II based adapter.
   If in doubt then look at linux/drivers/usb/pegasus.h for the complete
   list of supported devices.
   If your particular adapter is not in the list and you are _sure_ it
-  is Pegasus or Pegasus II based then send me (pmanolov@lnxw.com) vendor
-  and device IDs.
+  is Pegasus or Pegasus II based then send me (pmanolov@users.sourceforge.net)
+  vendor and device IDs.
 
   This code is also available as a module ( = code which can be
   inserted in and removed from the running kernel whenever you want).
diff -Nru a/drivers/usb/Config.in b/drivers/usb/Config.in
--- a/drivers/usb/Config.in	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/Config.in	Fri Mar 15 17:51:02 2002
@@ -31,6 +31,7 @@
 
    comment 'USB Device Class drivers'
    dep_tristate '  USB Audio support' CONFIG_USB_AUDIO $CONFIG_USB $CONFIG_SOUND
+   dep_tristate '    EMI 2|6 USB Audio interface support' CONFIG_USB_EMI26 $CONFIG_USB_AUDIO
    dep_tristate '  USB Bluetooth support (EXPERIMENTAL)' CONFIG_USB_BLUETOOTH $CONFIG_USB $CONFIG_EXPERIMENTAL
    if [ "$CONFIG_SCSI" = "n" ]; then
       comment '  SCSI support is needed for USB Storage'
@@ -86,7 +87,7 @@
    if [ "$CONFIG_NET" = "n" ]; then
       comment '  Networking support is needed for USB Networking device support'
    else
-      dep_tristate '  USB ADMtek Pegasus-based ethernet device support (EXPERIMENTAL)' CONFIG_USB_PEGASUS $CONFIG_USB $CONFIG_NET $CONFIG_EXPERIMENTAL
+      dep_tristate '  USB Pegasus/Pegasus-II based ethernet device support (EXPERIMENTAL)' CONFIG_USB_PEGASUS $CONFIG_USB $CONFIG_NET $CONFIG_EXPERIMENTAL
       dep_tristate '  USB KLSI KL5USB101-based ethernet device support (EXPERIMENTAL)' CONFIG_USB_KAWETH $CONFIG_USB $CONFIG_NET $CONFIG_EXPERIMENTAL
       dep_tristate '  USB CATC NetMate-based Ethernet device support (EXPERIMENTAL)' CONFIG_USB_CATC $CONFIG_USB $CONFIG_NET $CONFIG_EXPERIMENTAL
       dep_tristate '  USB Communication Class Ethernet device support (EXPERIMENTAL)' CONFIG_USB_CDCETHER $CONFIG_USB $CONFIG_NET $CONFIG_EXPERIMENTAL
diff -Nru a/drivers/usb/Makefile b/drivers/usb/Makefile
--- a/drivers/usb/Makefile	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/Makefile	Fri Mar 15 17:51:03 2002
@@ -63,6 +63,7 @@
 obj-$(CONFIG_USB_ACM)		+= acm.o
 obj-$(CONFIG_USB_PRINTER)	+= printer.o
 obj-$(CONFIG_USB_AUDIO)		+= audio.o
+obj-$(CONFIG_USB_EMI26)		+= emi26.o
 obj-$(CONFIG_USB_IBMCAM)	+= ibmcam.o usbvideo.o ultracam.o
 obj-$(CONFIG_USB_KONICAWC)	+= konicawc.o usbvideo.o
 obj-$(CONFIG_USB_PWC)		+= pwc.o
diff -Nru a/drivers/usb/dsbr100.c b/drivers/usb/dsbr100.c
--- a/drivers/usb/dsbr100.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/dsbr100.c	Fri Mar 15 17:51:02 2002
@@ -81,10 +81,10 @@
 static void *usb_dsbr100_probe(struct usb_device *dev, unsigned int ifnum,
 			 const struct usb_device_id *id);
 static void usb_dsbr100_disconnect(struct usb_device *dev, void *ptr);
-static int usb_dsbr100_ioctl(struct video_device *dev, unsigned int cmd, 
-	void *arg);
-static int usb_dsbr100_open(struct video_device *dev, int flags);
-static void usb_dsbr100_close(struct video_device *dev);
+static int usb_dsbr100_ioctl(struct inode *inode, struct file *file,
+			     unsigned int cmd, void *arg);
+static int usb_dsbr100_open(struct inode *inode, struct file *file);
+static int usb_dsbr100_close(struct inode *inode, struct file *file);
 
 static int radio_nr = -1;
 MODULE_PARM(radio_nr, "i");
@@ -99,14 +99,21 @@
 } usb_dsbr100;
 
 
+static struct file_operations usb_dsbr100_fops = {
+	owner:		THIS_MODULE,
+	open:		usb_dsbr100_open,
+	release:       	usb_dsbr100_close,
+	ioctl:          video_generic_ioctl,
+	llseek:         no_llseek,
+};
 static struct video_device usb_dsbr100_radio=
 {
+	owner:		THIS_MODULE,
 	name:		"D-Link DSB R-100 USB radio",
 	type:		VID_TYPE_TUNER,
 	hardware:	VID_HARDWARE_AZTECH,
-	open:		usb_dsbr100_open,
-	close:		usb_dsbr100_close,
-	ioctl:		usb_dsbr100_ioctl,
+	fops:           &usb_dsbr100_fops,
+	kernel_ioctl:  	usb_dsbr100_ioctl,
 };
 
 static int users = 0;
@@ -205,9 +212,10 @@
 	unlock_kernel();
 }
 
-static int usb_dsbr100_ioctl(struct video_device *dev, unsigned int cmd, 
-	void *arg)
+static int usb_dsbr100_ioctl(struct inode *inode, struct file *file,
+			     unsigned int cmd, void *arg)
 {
+	struct video_device *dev = video_devdata(file);
 	usb_dsbr100 *radio=dev->priv;
 
 	if (!radio)
@@ -216,84 +224,68 @@
 	switch(cmd)
 	{
 		case VIDIOCGCAP: {
-			struct video_capability v;
-			v.type=VID_TYPE_TUNER;
-			v.channels=1;
-			v.audios=1;
-			/* No we don't do pictures */
-			v.maxwidth=0;
-			v.maxheight=0;
-			v.minwidth=0;
-			v.minheight=0;
-			strcpy(v.name, "D-Link R-100 USB Radio");
-			if(copy_to_user(arg,&v,sizeof(v)))
-				return -EFAULT;
+			struct video_capability *v = arg;
+			memset(v,0,sizeof(*v));
+			v->type=VID_TYPE_TUNER;
+			v->channels=1;
+			v->audios=1;
+			strcpy(v->name, "D-Link R-100 USB Radio");
 			return 0;
 		}
 		case VIDIOCGTUNER: {
-			struct video_tuner v;
+			struct video_tuner *v = arg;
 			dsbr100_getstat(radio);
-			if(copy_from_user(&v, arg,sizeof(v))!=0) 
-				return -EFAULT;
-			if(v.tuner)	/* Only 1 tuner */ 
+			if(v->tuner)	/* Only 1 tuner */ 
 				return -EINVAL;
-			v.rangelow = 87*16000;
-			v.rangehigh = 108*16000;
-			v.flags = VIDEO_TUNER_LOW;
-			v.mode = VIDEO_MODE_AUTO;
-			v.signal = radio->stereo*0x7000;
+			v->rangelow = 87*16000;
+			v->rangehigh = 108*16000;
+			v->flags = VIDEO_TUNER_LOW;
+			v->mode = VIDEO_MODE_AUTO;
+			v->signal = radio->stereo*0x7000;
 				/* Don't know how to get signal strength */
-			v.flags |= VIDEO_TUNER_STEREO_ON*radio->stereo;
-			strcpy(v.name, "DSB R-100");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			v->flags |= VIDEO_TUNER_STEREO_ON*radio->stereo;
+			strcpy(v->name, "DSB R-100");
 			return 0;
 		}
 		case VIDIOCSTUNER: {
-			struct video_tuner v;
-			if(copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if(v.tuner!=0)
+			struct video_tuner *v = arg;
+			if(v->tuner!=0)
 				return -EINVAL;
 			/* Only 1 tuner so no setting needed ! */
 			return 0;
 		}
-		case VIDIOCGFREQ: 
+		case VIDIOCGFREQ:
+		{
+			int *freq = arg;
 			if (radio->curfreq==-1)
 				return -EINVAL;
-			if(copy_to_user(arg, &(radio->curfreq), 
-				sizeof(radio->curfreq)))
-				return -EFAULT;
+			*freq = radio->curfreq;
 			return 0;
-
+		}
 		case VIDIOCSFREQ:
-			if(copy_from_user(&(radio->curfreq), arg,
-				sizeof(radio->curfreq)))
-				return -EFAULT;
+		{
+			int *freq = arg;
+			*freq = radio->curfreq;
 			if (dsbr100_setfreq(radio, radio->curfreq)==-1)
 				warn("set frequency failed");
 			return 0;
-
+		}
 		case VIDIOCGAUDIO: {
-			struct video_audio v;
-			memset(&v,0, sizeof(v));
-			v.flags|=VIDEO_AUDIO_MUTABLE;
-			v.mode=VIDEO_SOUND_STEREO;
-			v.volume=1;
-			v.step=1;
-			strcpy(v.name, "Radio");
-			if(copy_to_user(arg,&v, sizeof(v)))
-				return -EFAULT;
+			struct video_audio *v = arg;
+			memset(v,0, sizeof(*v));
+			v->flags|=VIDEO_AUDIO_MUTABLE;
+			v->mode=VIDEO_SOUND_STEREO;
+			v->volume=1;
+			v->step=1;
+			strcpy(v->name, "Radio");
 			return 0;			
 		}
 		case VIDIOCSAUDIO: {
-			struct video_audio v;
-			if(copy_from_user(&v, arg, sizeof(v))) 
-				return -EFAULT;	
-			if(v.audio) 
+			struct video_audio *v = arg;
+			if(v->audio) 
 				return -EINVAL;
 
-			if(v.flags&VIDEO_AUDIO_MUTE) {
+			if(v->flags&VIDEO_AUDIO_MUTE) {
 				if (dsbr100_stop(radio)==-1)
 					warn("radio did not respond properly");
 			}
@@ -308,8 +300,9 @@
 }
 
 
-static int usb_dsbr100_open(struct video_device *dev, int flags)
+static int usb_dsbr100_open(struct inode *inode, struct file *file)
 {
+	struct video_device *dev = video_devdata(file);
 	usb_dsbr100 *radio=dev->priv;
 
 	if (! radio) {
@@ -322,22 +315,22 @@
 		return -EBUSY;
 	}
 	users++;
-	MOD_INC_USE_COUNT;
 	if (dsbr100_start(radio)<0)
 		warn("radio did not start up properly");
 	dsbr100_setfreq(radio,radio->curfreq);
 	return 0;
 }
 
-static void usb_dsbr100_close(struct video_device *dev)
+static int usb_dsbr100_close(struct inode *inode, struct file *file)
 {
+	struct video_device *dev = video_devdata(file);
 	usb_dsbr100 *radio=dev->priv;
 
 	if (!radio)
-		return;
+		return -ENODEV;
 	users--;
 	dsbr100_stop(radio);
-	MOD_DEC_USE_COUNT;
+	return 0;
 }
 
 static int __init dsbr100_init(void)
diff -Nru a/drivers/usb/emi26.c b/drivers/usb/emi26.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/usb/emi26.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,239 @@
+/* 
+ * Emagic EMI 2|6 usb audio interface firmware loader.
+ * Copyright (C) 2002
+ * 	Tapio Laxström (tapio.laxstrom@iptime.fi)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, as published by
+ * the Free Software Foundation, version 2.
+ * 
+ * emi26.c,v 1.13 2002/03/08 13:10:26 tapio Exp
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/usb.h>
+
+#define MAX_INTEL_HEX_RECORD_LENGTH 16
+typedef struct _INTEL_HEX_RECORD
+{
+	__u32	length;
+	__u32	address;
+	__u32	type;
+	__u8	data[MAX_INTEL_HEX_RECORD_LENGTH];
+} INTEL_HEX_RECORD, *PINTEL_HEX_RECORD;
+
+/* include firmware (variables) */
+#include "emi26_fw.h"
+
+#define EMI26_VENDOR_ID 		0x086a  /* Emagic Soft-und Hardware GmBH */
+#define EMI26_PRODUCT_ID		0x0100	/* EMI 2|6 without firmware */
+
+#define ANCHOR_LOAD_INTERNAL	0xA0	/* Vendor specific request code for Anchor Upload/Download (This one is implemented in the core) */
+#define ANCHOR_LOAD_EXTERNAL	0xA3	/* This command is not implemented in the core. Requires firmware */
+#define ANCHOR_LOAD_FPGA	0xA5	/* This command is not implemented in the core. Requires firmware. Emagic extension */
+#define MAX_INTERNAL_ADDRESS	0x1B3F	/* This is the highest internal RAM address for the AN2131Q */
+#define CPUCS_REG		0x7F92  /* EZ-USB Control and Status Register.  Bit 0 controls 8051 reset */ 
+#define INTERNAL_RAM(address)   (address <= MAX_INTERNAL_ADDRESS)
+
+static int emi26_writememory( struct usb_device *dev, int address, unsigned char *data, int length, __u8 bRequest);
+static int emi26_set_reset(struct usb_device *dev, unsigned char reset_bit);
+static int emi26_load_firmware (struct usb_device *dev);
+static void *emi26_probe(struct usb_device *dev, unsigned int if_num, const struct usb_device_id *id);
+static void emi26_disconnect(struct usb_device *dev, void *drv_context);
+static int __init emi26_init (void);
+static void __exit emi26_exit (void);
+
+
+/* thanks to drivers/usb/serial/keyspan_pda.c code */
+static int emi26_writememory (struct usb_device *dev, int address, unsigned char *data, int length, __u8 request)
+{
+	int result;
+	unsigned char *buffer =  kmalloc (length, GFP_KERNEL);
+
+	if (!buffer) {
+		printk(KERN_ERR "emi26: kmalloc(%d) failed.", length);
+		return -ENOMEM;
+	}
+	memcpy (buffer, data, length);
+	/* Note: usb_control_msg returns negative value on error or length of the
+	 * 		 data that was written! */
+	result = usb_control_msg (dev, usb_sndctrlpipe(dev, 0), request, 0x40, address, 0, buffer, length, 300);
+	kfree (buffer);
+	return result;
+}
+
+/* thanks to drivers/usb/serial/keyspan_pda.c code */
+static int emi26_set_reset (struct usb_device *dev, unsigned char reset_bit)
+{
+	int response;
+	printk(KERN_INFO "%s - %d", __FUNCTION__, reset_bit);
+	/* printk(KERN_DEBUG "%s - %d", __FUNCTION__, reset_bit); */
+	response = emi26_writememory (dev, CPUCS_REG, &reset_bit, 1, 0xa0);
+	if (response < 0) {
+		printk(KERN_ERR "emi26: set_reset (%d) failed", reset_bit);
+	}
+	return response;
+}
+
+static int emi26_load_firmware (struct usb_device *dev)
+{
+	int err;
+	int i;
+	int pos = 0;	/* Position in hex record */
+	__u32 addr;	/* Address to write */
+	__u8 buf[1023];
+
+	/* Assert reset (stop the CPU in the EMI) */
+	err = emi26_set_reset(dev,1);
+	if (err < 0) {
+		printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+		return err;
+	}
+
+	/* 1. We need to put the loader for the FPGA into the EZ-USB */
+	for (i=0; g_Loader[i].type == 0; i++) {
+		err = emi26_writememory(dev, g_Loader[i].address, g_Loader[i].data, g_Loader[i].length, ANCHOR_LOAD_INTERNAL);
+		if (err < 0) {
+			printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+			return err;
+		}
+	}
+
+	/* De-assert reset (let the CPU run) */
+	err = emi26_set_reset(dev,0);
+
+	/* 2. We upload the FPGA firmware into the EMI
+	 * Note: collect up to 1023 (yes!) bytes and send them with
+	 * a single request. This is _much_ faster! */
+	do {
+		i = 0;
+		addr = g_bitstream[pos].address;
+
+		/* intel hex records are terminated with type 0 element */
+		while ((g_bitstream[pos].type == 0) && (i + g_bitstream[pos].length < sizeof(buf))) {
+			memcpy(buf + i, g_bitstream[pos].data, g_bitstream[pos].length);
+			i += g_bitstream[pos].length;
+			pos++;
+		}
+		err = emi26_writememory(dev, addr, buf, i, ANCHOR_LOAD_FPGA);
+		if (err < 0) {
+			printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+			return err;
+		}
+	} while (i > 0);
+
+	/* Assert reset (stop the CPU in the EMI) */
+	err = emi26_set_reset(dev,1);
+	if (err < 0) {
+		printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+		return err;
+	}
+
+	/* 3. We need to put the loader for the firmware into the EZ-USB (again...) */
+	for (i=0; g_Loader[i].type == 0; i++) {
+		err = emi26_writememory(dev, g_Loader[i].address, g_Loader[i].data, g_Loader[i].length, ANCHOR_LOAD_INTERNAL);
+		if (err < 0) {
+			printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+			return err;
+		}
+	}
+
+	/* De-assert reset (let the CPU run) */
+	err = emi26_set_reset(dev,0);
+	if (err < 0) {
+		printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+		return err;
+	}
+
+	/* 4. We put the part of the firmware that lies in the external RAM into the EZ-USB */
+	for (i=0; g_Firmware[i].type == 0; i++) {
+		if (!INTERNAL_RAM(g_Firmware[i].address)) {
+			err = emi26_writememory(dev, g_Firmware[i].address, g_Firmware[i].data, g_Firmware[i].length, ANCHOR_LOAD_EXTERNAL);
+			if (err < 0) {
+				printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+				return err;
+			}
+		}
+	}
+	
+	/* Assert reset (stop the CPU in the EMI) */
+	err = emi26_set_reset(dev,1);
+	if (err < 0) {
+		printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+		return err;
+	}
+
+	for (i=0; g_Firmware[i].type == 0; i++) {
+		if (INTERNAL_RAM(g_Firmware[i].address)) {
+			err = emi26_writememory(dev, g_Firmware[i].address, g_Firmware[i].data, g_Firmware[i].length, ANCHOR_LOAD_INTERNAL);
+			if (err < 0) {
+				printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+				return err;
+			}
+		}
+	}
+
+	/* De-assert reset (let the CPU run) */
+	err = emi26_set_reset(dev,0);
+	if (err < 0) {
+		printk(KERN_ERR "%s - error loading firmware: error = %d", __FUNCTION__, err);
+		return err;
+	}
+
+	/* return 1 to fail the driver inialization
+	 * and give real driver change to load */
+	return 1;
+}
+
+static __devinitdata struct usb_device_id id_table [] = {
+	{ USB_DEVICE(EMI26_VENDOR_ID, EMI26_PRODUCT_ID) },
+	{ }                                             /* Terminating entry */
+};
+
+MODULE_DEVICE_TABLE (usb, id_table);
+
+static void * emi26_probe(struct usb_device *dev, unsigned int if_num, const struct usb_device_id *id)
+{
+	printk(KERN_INFO "%s start", __FUNCTION__); 
+	
+	if((dev->descriptor.idVendor == EMI26_VENDOR_ID) && (dev->descriptor.idProduct == EMI26_PRODUCT_ID)) {
+		emi26_load_firmware(dev);
+	}
+	
+	/* do not return the driver context, let real audio driver do that */
+	return 0;
+}
+
+static void emi26_disconnect(struct usb_device *dev, void *drv_context)
+{
+}
+
+struct usb_driver emi26_driver = {
+name:			"emi26 - firmware loader",
+probe:			emi26_probe,
+disconnect:		emi26_disconnect,
+id_table:		NULL,
+};
+
+static int __init emi26_init (void)
+{
+	usb_register (&emi26_driver);
+	return 0;
+}
+
+static void __exit emi26_exit (void)
+{
+	usb_deregister (&emi26_driver);
+}
+
+module_init(emi26_init);
+module_exit(emi26_exit);
+
+MODULE_AUTHOR("tapio laxström");
+MODULE_DESCRIPTION("Emagic EMI 2|6 firmware loader.");
+MODULE_LICENSE("GPL");
+
+/* vi:ai:syntax=c:sw=8:ts=8:tw=80
+ */
diff -Nru a/drivers/usb/emi26_fw.h b/drivers/usb/emi26_fw.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/drivers/usb/emi26_fw.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,5775 @@
+/*
+ * This file is generated from three different files, provided by Emagic.
+ */
+/* generated Fri Mar 8 15:11:35 EET 2002 */
+
+/*
+ * This firmware is for the Emagic EMI 2|6 Audio Interface
+ *
+ * The firmware contained herein is Copyright (c) 1999-2002 Emagic
+ * as an unpublished work. This notice does not imply unrestricted
+ * or public access to this firmware which is a trade secret of Emagic,
+ * and which may not be reproduced, used, sold or transferred to
+ * any third party without Emagic's written consent. All Rights Reserved.
+ *
+ * This firmware may not be modified and may only be used with the
+ * Emagic EMI 2|6 Audio Interface. Distribution and/or Modification of
+ * any driver which includes this firmware, in whole or in part,
+ * requires the inclusion of this statement.
+ */
+INTEL_HEX_RECORD g_bitstream[]={
+{  16, 0x8010, 0, {0xff,0xff,0xff,0xff,0xaa,0x99,0x55,0x66,0x30,0x00,0x80,0x01,0x00,0x00,0x00,0x07 } },
+{  16, 0x8020, 0, {0x30,0x01,0x60,0x01,0x00,0x00,0x00,0x0b,0x30,0x01,0x20,0x01,0x00,0x80,0x3f,0x2d } },
+{  16, 0x8030, 0, {0x30,0x00,0xc0,0x01,0x00,0x00,0x00,0x00,0x30,0x00,0x80,0x01,0x00,0x00,0x00,0x09 } },
+{  16, 0x8040, 0, {0x30,0x00,0x20,0x01,0x00,0x00,0x00,0x00,0x30,0x00,0x80,0x01,0x00,0x00,0x00,0x01 } },
+{  16, 0x8050, 0, {0x30,0x00,0x40,0x00,0x50,0x00,0x3e,0x04,0x08,0x12,0x10,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8060, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8070, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x04 } },
+{  16, 0x8080, 0, {0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x10,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8090, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x80a0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x84 } },
+{  16, 0x80b0, 0, {0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x80c0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x80d0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00 } },
+{  16, 0x80e0, 0, {0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x80f0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8100, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8110, 0, {0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8120, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8130, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04 } },
+{  16, 0x8140, 0, {0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x13,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8150, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8160, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8170, 0, {0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x12,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8180, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8190, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x84 } },
+{  16, 0x81a0, 0, {0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xf7,0x10,0x01,0x14,0x00,0x25,0x00,0x05 } },
+{  16, 0x81b0, 0, {0x40,0x01,0x50,0x00,0x94,0x00,0x15,0x00,0x07,0x40,0x01,0xd0,0x00,0x94,0x00,0x25 } },
+{  16, 0x81c0, 0, {0x80,0x01,0x60,0x02,0xd8,0x00,0xf6,0x00,0x2f,0x80,0x02,0xe0,0x04,0xd8,0x37,0x44 } },
+{  16, 0x81d0, 0, {0x90,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x05,0xf2,0x00,0xcc,0x90,0x39,0x20 } },
+{  16, 0x81e0, 0, {0x0d,0x98,0x03,0xd2,0x00,0xe7,0x80,0x37,0x04,0x0e,0xf1,0x83,0x7e,0x00,0xdf,0x90 } },
+{  16, 0x81f0, 0, {0x31,0xe4,0x8f,0x79,0x03,0x7c,0x20,0xdf,0x22,0x33,0xc0,0x0c,0xf0,0x22,0x30,0x00 } },
+{  16, 0x8200, 0, {0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x10,0x62,0x00,0x80,0x24,0x22,0x20 } },
+{  16, 0x8210, 0, {0x08,0x98,0x12,0xe2,0x00,0x8b,0x81,0x20,0x94,0x08,0x74,0x02,0x2e,0x00,0x8a,0x01 } },
+{  16, 0x8220, 0, {0x22,0xc8,0x08,0x92,0x02,0x3d,0x80,0x8b,0x60,0x22,0x80,0x08,0xb0,0x02,0x20,0x04 } },
+{  16, 0x8230, 0, {0x30,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x88,0x05,0xc8,0x00,0xa0,0x00,0x20,0x00 } },
+{  16, 0x8240, 0, {0x0b,0x10,0x02,0xc0,0x00,0xa1,0x00,0x24,0x09,0x4a,0x32,0x02,0x48,0x00,0xb1,0x00 } },
+{  16, 0x8250, 0, {0x62,0xc0,0x09,0xa0,0x46,0xcc,0x24,0x93,0x49,0x2a,0x80,0x48,0x30,0x22,0x62,0x01 } },
+{  16, 0x8260, 0, {0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc0,0x15,0xa8,0x12,0xa8,0x00,0x22,0x00 } },
+{  16, 0x8270, 0, {0x08,0x90,0x02,0xe0,0x00,0x89,0x80,0x22,0x44,0x08,0xb0,0x12,0xa8,0x00,0xa9,0x40 } },
+{  16, 0x8280, 0, {0x22,0xc0,0x08,0x90,0x82,0xac,0x00,0x9b,0x04,0x2a,0xc4,0x08,0xb0,0x02,0x70,0x04 } },
+{  16, 0x8290, 0, {0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x14,0x84,0x00,0xe9,0x80,0xb2,0x64 } },
+{  16, 0x82a0, 0, {0x4d,0xa0,0x03,0xea,0x20,0xe9,0xc0,0x36,0x40,0x0e,0xb0,0x03,0x44,0x00,0xfb,0x90 } },
+{  16, 0x82b0, 0, {0xb2,0x88,0x0d,0xbc,0x03,0xec,0x08,0x5b,0x00,0x38,0x60,0x2c,0xb0,0x63,0x40,0x04 } },
+{  16, 0x82c0, 0, {0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe0,0x01,0xb4,0x26,0xdd,0x90,0x37,0x40 } },
+{  16, 0x82d0, 0, {0x4f,0xe0,0x13,0xf2,0x80,0xfd,0x00,0x3d,0xa0,0x0d,0x70,0x03,0x75,0x00,0x5e,0x00 } },
+{  16, 0x82e0, 0, {0x3f,0xa4,0x0d,0xf9,0x03,0x5c,0x10,0xeb,0x00,0x37,0x20,0x0f,0x30,0x03,0xb8,0x00 } },
+{  16, 0x82f0, 0, {0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x10,0xac,0x00,0xe9,0x80,0x32,0x40 } },
+{  16, 0x8300, 0, {0x0c,0xa1,0x83,0xe8,0x00,0xe9,0x00,0x32,0x42,0x0e,0xb0,0x03,0xac,0x48,0xe9,0x00 } },
+{  16, 0x8310, 0, {0x3a,0x80,0x0e,0xa4,0x03,0xec,0x00,0xeb,0x00,0xb2,0x03,0x0e,0xb0,0x0b,0x10,0x04 } },
+{  16, 0x8320, 0, {0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xc8,0x05,0x2e,0x80,0x89,0xd1,0x20,0x40 } },
+{  16, 0x8330, 0, {0x08,0xa0,0x02,0xc0,0x00,0x81,0x80,0x22,0x58,0x08,0xf5,0x02,0x2f,0x40,0x8b,0x00 } },
+{  16, 0x8340, 0, {0x20,0xc0,0x08,0x30,0x43,0x7c,0x00,0x87,0x00,0x22,0x40,0x08,0xf0,0x02,0x32,0x00 } },
+{  16, 0x8350, 0, {0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xe0,0x05,0x42,0x01,0x9a,0x44,0x28,0xa2 } },
+{  16, 0x8360, 0, {0x08,0x18,0x02,0xc0,0x80,0xa1,0x80,0xa0,0x00,0x08,0x30,0x02,0x8e,0x00,0xab,0x00 } },
+{  16, 0x8370, 0, {0x2c,0x40,0x0a,0x30,0x02,0x0c,0x00,0xa3,0x00,0x20,0x44,0x0a,0x30,0x02,0x38,0x00 } },
+{  16, 0x8380, 0, {0x50,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x01,0x32,0x00,0x96,0x82,0x2b,0xa2 } },
+{  16, 0x8390, 0, {0x88,0x5a,0x02,0xf2,0x00,0x05,0x80,0x29,0xa0,0x08,0x78,0x42,0xbe,0x00,0x8e,0x84 } },
+{  16, 0x83a0, 0, {0x2f,0x61,0x0a,0xd8,0x02,0x4e,0x10,0xa7,0x80,0x20,0x28,0x08,0x78,0x02,0x18,0x00 } },
+{  16, 0x83b0, 0, {0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x48,0x08,0x08,0x00,0xf2,0x24,0x38,0x80 } },
+{  16, 0x83c0, 0, {0x2c,0x1a,0x03,0xc4,0x00,0xe0,0x58,0xa0,0x80,0x2e,0x30,0x03,0x88,0x41,0xe3,0x02 } },
+{  16, 0x83d0, 0, {0x3c,0x40,0x06,0x20,0x03,0x8c,0x00,0xe3,0x00,0x10,0x00,0x0e,0x31,0x43,0x12,0x02 } },
+{  16, 0x83e0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x1d,0x98,0x00,0xee,0x01,0x37,0x84 } },
+{  16, 0x83f0, 0, {0x9f,0xd9,0x03,0xf0,0x48,0xfd,0x10,0x37,0xc0,0x07,0xb0,0x03,0x5c,0x00,0xf6,0x10 } },
+{  16, 0x8400, 0, {0x33,0xc0,0x0d,0xe1,0x03,0xed,0x20,0xdf,0x10,0x3f,0x48,0x0f,0xf0,0x23,0xd0,0x06 } },
+{  16, 0x8410, 0, {0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xa8,0x05,0xe4,0x02,0xcb,0x80,0x30,0xc0 } },
+{  16, 0x8420, 0, {0x0c,0xa0,0x03,0xe2,0x02,0xc9,0x00,0x3a,0x40,0x0d,0xb6,0x03,0x64,0x00,0xeb,0x00 } },
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+{  16, 0xf720, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00 } },
+{  16, 0xf730, 0, {0x00,0x00,0x00,0x3e,0xf7,0xff,0xf7,0xc0,0x00,0x00,0x00,0x00,0x2f,0xe7,0xb7,0xff } },
+{  16, 0xf740, 0, {0xc0,0x00,0x00,0x00,0x00,0x2f,0xfe,0x7f,0xf7,0xc0,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf750, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00 } },
+{  16, 0xf760, 0, {0x00,0x00,0x00,0x36,0xbf,0xfe,0xdf,0xc0,0x00,0x00,0x00,0x00,0x0f,0xf7,0xdf,0xff } },
+{  16, 0xf770, 0, {0xc0,0x00,0x00,0x00,0x00,0x3d,0xb7,0xb7,0xef,0xc0,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf780, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00 } },
+{  16, 0xf790, 0, {0x00,0x00,0x00,0x1f,0xdf,0xdf,0xff,0xc0,0x00,0x00,0x00,0x00,0x0f,0xdf,0xdf,0xff } },
+{  16, 0xf7a0, 0, {0xc0,0x00,0x00,0x00,0x00,0x3f,0xef,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf7b0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00 } },
+{  16, 0xf7c0, 0, {0x00,0x00,0x00,0x3f,0xbf,0x7f,0xff,0xc0,0x00,0x00,0x00,0x00,0x3f,0xff,0x7f,0xf7 } },
+{  16, 0xf7d0, 0, {0xc0,0x00,0x00,0x00,0x00,0x3f,0xdf,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf7e0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00 } },
+{  16, 0xf7f0, 0, {0x00,0x00,0x00,0x3f,0x7e,0xff,0xff,0x40,0x00,0x00,0x00,0x00,0x3f,0xfe,0xff,0xff } },
+{  16, 0xf800, 0, {0xc0,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf810, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00 } },
+{  16, 0xf820, 0, {0x00,0x00,0x00,0x37,0xff,0x6f,0xff,0xc0,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff } },
+{  16, 0xf830, 0, {0xc0,0x00,0x00,0x00,0x00,0x3f,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf840, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf850, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf860, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf870, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0x00,0x20,0x01,0x02,0x00,0x00,0x00 } },
+{  16, 0xf880, 0, {0x30,0x00,0x43,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf890, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf8a0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf8b0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf8c0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf8d0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf8e0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf8f0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0xc0,0x00,0x00,0x00,0x00,0x30 } },
+{  16, 0xf900, 0, {0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf910, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf920, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf930, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf940, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf950, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0xc0,0x30,0xc0,0x00 } },
+{  16, 0xf960, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf970, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf980, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf990, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf9a0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf9b0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0xc0,0x30,0xc0,0x30,0xc0,0x30 } },
+{  16, 0xf9c0, 0, {0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf9d0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf9e0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xf9f0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa00, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa10, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x00,0x00,0x00,0x00,0x0f } },
+{  16, 0xfa20, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa30, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa40, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa50, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa60, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa70, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xc0,0x00,0x00,0x00,0x00,0x3f } },
+{  16, 0xfa80, 0, {0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfa90, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfaa0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfab0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfac0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfad0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x30,0xc0,0x30,0xc0,0x0f } },
+{  16, 0xfae0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
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+{  16, 0xfb10, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb20, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb30, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x13,0x6b,0x00,0xc0,0x00,0xcf,0x2c } },
+{  16, 0xfb40, 0, {0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb50, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb60, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb70, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb80, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfb90, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x0f,0x00,0x00 } },
+{  16, 0xfba0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfbb0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfbc0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfbd0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfbe0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfbf0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0xc0,0x0f,0x00,0x0f,0x00,0x30 } },
+{  16, 0xfc00, 0, {0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc10, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc20, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc30, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc40, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc50, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3f,0xc0,0x3f,0xc0,0x00 } },
+{  16, 0xfc60, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc70, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc80, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfc90, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfca0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfcb0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30,0xc0,0x3f,0xc0,0x3f,0xc0,0x30 } },
+{  16, 0xfcc0, 0, {0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfcd0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfce0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfcf0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfd00, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfd10, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0f,0x00,0x0f,0x00,0x0f,0x00,0x0f } },
+{  16, 0xfd20, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0xfd30, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
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+{  16, 0x8fe0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x8ff0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9000, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9010, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9020, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9030, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9040, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9050, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9060, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9070, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9080, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9090, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x90a0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x90b0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x90c0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x90d0, 0, {0x30,0x00,0x00,0x01,0x00,0x00,0x44,0x72,0x30,0x00,0x80,0x01,0x00,0x00,0x00,0x03 } },
+{  16, 0x90e0, 0, {0x30,0x00,0x40,0x0c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x90f0, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9100, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  16, 0x9110, 0, {0x00,0x00,0x00,0x00,0x30,0x00,0x80,0x01,0x00,0x00,0x00,0x05,0x30,0x00,0xa0,0x01 } },
+{  16, 0x9120, 0, {0x00,0x00,0x00,0x00,0x30,0x00,0x00,0x01,0x00,0x00,0xe1,0x5a,0x00,0x00,0x00,0x00 } },
+{  12, 0x9130, 0, {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00 } },
+{  0 , 0x0000, 1, {0 }}
+};
+// VERSION=1.1.1.131
+// DATE=2001dec06
+// PRODUCT=EMI 2|6
+/*
+ * This firmware is for the Emagic EMI 2|6 Audio Interface
+ *
+ * The firmware contained herein is Copyright (c) 1999-2002 Emagic
+ * as an unpublished work. This notice does not imply unrestricted
+ * or public access to this firmware which is a trade secret of Emagic,
+ * and which may not be reproduced, used, sold or transferred to
+ * any third party without Emagic's written consent. All Rights Reserved.
+ *
+ * This firmware may not be modified and may only be used with the
+ * Emagic EMI 2|6 Audio Interface. Distribution and/or Modification of
+ * any driver which includes this firmware, in whole or in part,
+ * requires the inclusion of this statement.
+ */
+INTEL_HEX_RECORD g_Firmware[] = {
+{   3,0x0000,0,{0x02,0x43,0x56} },
+{   3,0x0003,0,{0x02,0x4b,0xcd} },
+{   3,0x000b,0,{0x02,0x4b,0xd2} },
+{   3,0x0013,0,{0x02,0x4b,0x92} },
+{   3,0x001b,0,{0x02,0x4b,0xd5} },
+{   3,0x0023,0,{0x02,0x1b,0x39} },
+{   3,0x002b,0,{0x02,0x43,0xe2} },
+{   3,0x0033,0,{0x02,0x3f,0xf3} },
+{   3,0x003b,0,{0x02,0x4b,0xc0} },
+{   3,0x0043,0,{0x02,0x47,0x00} },
+{   3,0x004b,0,{0x02,0x3f,0xfc} },
+{   3,0x0053,0,{0x02,0x37,0xfa} },
+{   3,0x005b,0,{0x02,0x4b,0xc7} },
+{   3,0x0063,0,{0x02,0x46,0xfc} },
+{  16,0x0500,0,{0x12,0x01,0x10,0x01,0x00,0x00,0x00,0x40,0x6a,0x08,0x01,0x01,0x00,0x01,0x01,0x02} },
+{  16,0x0510,0,{0x00,0x01,0x09,0x02,0xb8,0x01,0x03,0x01,0x00,0x80,0xa0,0x09,0x04,0x00,0x00,0x00} },
+{  16,0x0520,0,{0x01,0x01,0x00,0x00,0x0a,0x24,0x01,0x00,0x01,0x56,0x00,0x02,0x01,0x02,0x0c,0x24} },
+{  16,0x0530,0,{0x02,0x01,0x01,0x01,0x00,0x06,0x00,0x00,0x00,0x00,0x15,0x24,0x06,0x05,0x01,0x02} },
+{  16,0x0540,0,{0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09} },
+{  16,0x0550,0,{0x24,0x03,0x02,0x04,0x03,0x00,0x05,0x00,0x0c,0x24,0x02,0x03,0x01,0x02,0x00,0x02} },
+{  16,0x0560,0,{0x00,0x00,0x00,0x00,0x0d,0x24,0x06,0x06,0x03,0x02,0x03,0x00,0x00,0x00,0x00,0x00} },
+{  16,0x0570,0,{0x00,0x09,0x24,0x03,0x04,0x01,0x01,0x00,0x06,0x00,0x09,0x04,0x01,0x00,0x00,0x01} },
+{  16,0x0580,0,{0x02,0x00,0x00,0x09,0x04,0x01,0x01,0x02,0x01,0x02,0x00,0x00,0x07,0x24,0x01,0x01} },
+{  16,0x0590,0,{0x00,0x01,0x00,0x11,0x24,0x02,0x01,0x02,0x02,0x10,0x03,0x44,0xac,0x00,0x80,0xbb} },
+{  16,0x05a0,0,{0x00,0x00,0x77,0x01,0x09,0x05,0x0a,0x05,0x84,0x01,0x01,0x00,0x8f,0x07,0x25,0x01} },
+{  16,0x05b0,0,{0x01,0x00,0x00,0x00,0x09,0x05,0x8f,0x01,0x03,0x00,0x01,0x06,0x00,0x09,0x04,0x01} },
+{  16,0x05c0,0,{0x02,0x02,0x01,0x02,0x00,0x00,0x07,0x24,0x01,0x01,0x00,0x01,0x00,0x0e,0x24,0x02} },
+{  16,0x05d0,0,{0x01,0x06,0x02,0x10,0x02,0x44,0xac,0x00,0x80,0xbb,0x00,0x09,0x05,0x0a,0x05,0x4c} },
+{  16,0x05e0,0,{0x02,0x01,0x00,0x8f,0x07,0x25,0x01,0x01,0x00,0x00,0x00,0x09,0x05,0x8f,0x01,0x03} },
+{  16,0x05f0,0,{0x00,0x01,0x06,0x00,0x09,0x04,0x01,0x03,0x02,0x01,0x02,0x00,0x00,0x07,0x24,0x01} },
+{  16,0x0600,0,{0x01,0x00,0x01,0x00,0x0e,0x24,0x02,0x01,0x06,0x03,0x18,0x02,0x44,0xac,0x00,0x80} },
+{  16,0x0610,0,{0xbb,0x00,0x09,0x05,0x0a,0x05,0x72,0x03,0x01,0x00,0x8f,0x07,0x25,0x01,0x01,0x00} },
+{  16,0x0620,0,{0x00,0x00,0x09,0x05,0x8f,0x01,0x03,0x00,0x01,0x06,0x00,0x09,0x04,0x01,0x04,0x02} },
+{  16,0x0630,0,{0x01,0x02,0x00,0x00,0x07,0x24,0x01,0x01,0x00,0x01,0x00,0x0b,0x24,0x02,0x01,0x02} },
+{  16,0x0640,0,{0x03,0x18,0x01,0x00,0x77,0x01,0x09,0x05,0x0a,0x05,0x46,0x02,0x01,0x00,0x8f,0x07} },
+{  16,0x0650,0,{0x25,0x01,0x01,0x00,0x00,0x00,0x09,0x05,0x8f,0x01,0x03,0x00,0x01,0x06,0x00,0x09} },
+{  16,0x0660,0,{0x04,0x02,0x00,0x00,0x01,0x02,0x00,0x00,0x09,0x04,0x02,0x01,0x01,0x01,0x02,0x00} },
+{  16,0x0670,0,{0x00,0x07,0x24,0x01,0x04,0x00,0x01,0x00,0x11,0x24,0x02,0x01,0x02,0x02,0x10,0x03} },
+{  16,0x0680,0,{0x44,0xac,0x00,0x80,0xbb,0x00,0x00,0x77,0x01,0x09,0x05,0x8c,0x05,0x84,0x01,0x01} },
+{  16,0x0690,0,{0x00,0x00,0x07,0x25,0x01,0x01,0x02,0x00,0x00,0x09,0x04,0x02,0x02,0x01,0x01,0x02} },
+{  16,0x06a0,0,{0x00,0x00,0x07,0x24,0x01,0x04,0x00,0x01,0x00,0x11,0x24,0x02,0x01,0x02,0x03,0x18} },
+{  16,0x06b0,0,{0x03,0x44,0xac,0x00,0x80,0xbb,0x00,0x00,0x77,0x01,0x09,0x05,0x8c,0x05,0x46,0x02} },
+{  16,0x06c0,0,{0x01,0x00,0x00,0x07,0x25,0x01,0x01,0x02,0x00,0x00,0x05,0x0c,0x09,0x01,0xa1,0x01} },
+{  16,0x06d0,0,{0x05,0x0c,0x09,0xe9,0x05,0x0c,0x09,0xea,0x15,0x00,0x25,0x01,0x95,0x02,0x75,0x01} },
+{  16,0x06e0,0,{0x81,0x42,0x95,0x01,0x75,0x06,0x81,0x01,0x05,0x0c,0x09,0x00,0x05,0x0c,0x09,0x00} },
+{  16,0x06f0,0,{0x15,0x00,0x25,0x01,0x95,0x02,0x75,0x01,0x91,0x06,0x95,0x01,0x75,0x06,0x91,0x03} },
+{  16,0x0700,0,{0xc0,0x04,0x03,0x09,0x04,0x18,0x03,0x45,0x00,0x4d,0x00,0x41,0x00,0x47,0x00,0x49} },
+{  16,0x0710,0,{0x00,0x43,0x00,0x20,0x00,0x47,0x00,0x6d,0x00,0x62,0x00,0x48,0x00,0x1e,0x03,0x45} },
+{  16,0x0720,0,{0x00,0x6d,0x00,0x61,0x00,0x67,0x00,0x69,0x00,0x63,0x00,0x20,0x00,0x45,0x00,0x4d} },
+{  16,0x0730,0,{0x00,0x49,0x00,0x20,0x00,0x32,0x00,0x7c,0x00,0x36,0x00,0x2a,0x03,0x43,0x00,0x6f} },
+{  16,0x0740,0,{0x00,0x6e,0x00,0x66,0x00,0x69,0x00,0x67,0x00,0x75,0x00,0x72,0x00,0x61,0x00,0x74} },
+{  16,0x0750,0,{0x00,0x69,0x00,0x6f,0x00,0x6e,0x00,0x20,0x00,0x53,0x00,0x74,0x00,0x72,0x00,0x69} },
+{  16,0x0760,0,{0x00,0x6e,0x00,0x67,0x00,0x22,0x03,0x49,0x00,0x6e,0x00,0x74,0x00,0x65,0x00,0x72} },
+{  16,0x0770,0,{0x00,0x66,0x00,0x61,0x00,0x63,0x00,0x65,0x00,0x20,0x00,0x53,0x00,0x74,0x00,0x72} },
+{   9,0x0780,0,{0x00,0x69,0x00,0x6e,0x00,0x67,0x00,0x00,0x00} },
+{  16,0x0789,0,{0x74,0x00,0xf5,0x86,0x90,0xfd,0xa5,0x7c,0x05,0xa3,0xe5,0x82,0x45,0x83,0x70,0xf9} },
+{   1,0x0799,0,{0x22} },
+{  16,0x079a,0,{0x90,0x7f,0xd6,0xe0,0x44,0x80,0xf0,0x43,0x87,0x01,0x00,0x00,0x00,0x00,0x00,0x22} },
+{  16,0x07aa,0,{0xc0,0xd0,0xc0,0xe0,0x8f,0xe0,0xc0,0xe0,0x8e,0xe0,0xc0,0xe0,0x8d,0xe0,0xc0,0xe0} },
+{  16,0x07ba,0,{0x8c,0xe0,0xc0,0xe0,0xc0,0x82,0xc0,0x83,0x05,0x86,0xc0,0x84,0xc0,0x85,0xe5,0x18} },
+{  16,0x07ca,0,{0xb4,0x02,0x03,0x02,0x07,0xd9,0xb4,0x01,0x03,0x02,0x07,0xde,0x02,0x07,0xfa,0x7d} },
+{  16,0x07da,0,{0x01,0x02,0x08,0x16,0xe5,0x19,0x14,0xf5,0x19,0xc3,0xb5,0x13,0x03,0x02,0x07,0xf5} },
+{  16,0x07ea,0,{0x50,0x09,0xb4,0x00,0xea,0x75,0x19,0x0a,0x02,0x07,0xd9,0x7d,0x00,0x02,0x08,0x16} },
+{  16,0x07fa,0,{0xe5,0x19,0x14,0xf5,0x19,0xc3,0xb5,0x14,0x03,0x02,0x08,0x11,0x50,0x09,0xb4,0x00} },
+{  16,0x080a,0,{0xce,0x75,0x19,0x0a,0x02,0x07,0xd9,0x7d,0x02,0x02,0x08,0x16,0x7c,0x05,0x90,0x7f} },
+{  16,0x081a,0,{0x99,0xe0,0x54,0x40,0xdc,0x03,0x02,0x08,0x43,0xb4,0x00,0x1d,0x90,0x7f,0xe3,0x74} },
+{  16,0x082a,0,{0x7b,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x7f,0xe2,0x74,0x40,0xf0,0x90,0x7f,0xe5,0xf0} },
+{  16,0x083a,0,{0x90,0x7f,0xe2,0x74,0x00,0xf0,0x02,0x08,0x18,0x05,0x86,0x90,0x7f,0xe2,0x74,0x80} },
+{  16,0x084a,0,{0xf0,0x90,0x79,0x65,0xe0,0xb4,0x01,0x03,0x02,0x08,0x9e,0xb4,0x02,0x03,0x02,0x08} },
+{  16,0x085a,0,{0x96,0xb4,0x03,0x03,0x02,0x08,0x8e,0xb4,0x04,0x03,0x02,0x08,0x86,0xb4,0x05,0x03} },
+{  16,0x086a,0,{0x02,0x08,0x7e,0xb4,0x06,0x03,0x02,0x08,0x76,0x02,0x08,0xf4,0x05,0x86,0x90,0x7f} },
+{  16,0x087a,0,{0x6c,0x02,0x08,0xe9,0x05,0x86,0x90,0x7f,0x6c,0x02,0x08,0xdd,0x05,0x86,0x90,0x7f} },
+{  16,0x088a,0,{0x6c,0x02,0x08,0xcf,0x05,0x86,0x90,0x7f,0x6c,0x02,0x08,0xc0,0x05,0x86,0x90,0x7f} },
+{  16,0x089a,0,{0x6c,0x02,0x08,0xb2,0x05,0x86,0x90,0x7f,0x6c,0xf0,0x00,0xf0,0x00,0xf0,0x00,0xf0} },
+{  16,0x08aa,0,{0x0d,0xed,0xb4,0x2d,0xf4,0x02,0x08,0xf4,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0x0d,0xed} },
+{  16,0x08ba,0,{0xb4,0x2d,0xf5,0x02,0x08,0xf4,0xf0,0x00,0xf0,0x00,0xf0,0x00,0xf0,0x0d,0xed,0xb4} },
+{  16,0x08ca,0,{0x31,0xf4,0x02,0x08,0xf4,0xf0,0xf0,0xf0,0xf0,0xf0,0xf0,0x0d,0xed,0xb4,0x31,0xf5} },
+{  16,0x08da,0,{0x02,0x08,0xf4,0xf0,0xf0,0xf0,0xf0,0x0d,0xed,0xb4,0x61,0xf7,0x02,0x08,0xf4,0xf0} },
+{  16,0x08ea,0,{0xf0,0xf0,0xf0,0xf0,0xf0,0x0d,0xed,0xb4,0x61,0xf5,0x90,0x7f,0xe2,0x74,0x00,0xf0} },
+{  16,0x08fa,0,{0xd0,0x85,0xd0,0x84,0x05,0x86,0xd0,0x83,0xd0,0x82,0xd0,0xe0,0xfc,0xd0,0xe0,0xfd} },
+{   5,0x090a,0,{0xd0,0xe0,0xfe,0xd0,0xe0} },
+{   6,0x090f,0,{0xff,0xd0,0xe0,0xd0,0xd0,0x22} },
+{  16,0x0915,0,{0xc0,0xd0,0xc0,0xe0,0xc0,0x82,0xc0,0x83,0x90,0x7f,0x6f,0xe5,0x0c,0xf0,0xe5,0x0d} },
+{  13,0x0925,0,{0xf0,0xe5,0x0e,0xf0,0xd0,0x83,0xd0,0x82,0xd0,0xe0,0xd0,0xd0,0x22} },
+{  16,0x0932,0,{0xc0,0xd0,0xc0,0xe0,0x8f,0xe0,0xc0,0xe0,0x8e,0xe0,0xc0,0xe0,0xc0,0x82,0xc0,0x83} },
+{  16,0x0942,0,{0x05,0x86,0xc0,0x84,0xc0,0x85,0x90,0x79,0x70,0xe0,0xff,0xbf,0x00,0x03,0x02,0x0a} },
+{  16,0x0952,0,{0xb8,0x90,0x7f,0x96,0xe0,0x44,0x80,0xf0,0x90,0x7f,0xe2,0x74,0x80,0xf0,0x90,0x7f} },
+{  16,0x0962,0,{0x62,0xe0,0x05,0x86,0x90,0x7f,0xe2,0x74,0x00,0xf0,0x90,0x7f,0x96,0xe0,0x54,0x7f} },
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+{  16,0x0982,0,{0xbe,0xb4,0x02,0x03,0x02,0x09,0xc3,0xb4,0x03,0x03,0x02,0x09,0xac,0xb4,0x04,0x03} },
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+{  16,0x09a2,0,{0x3f,0xff,0x90,0x7f,0x63,0x05,0x86,0x02,0x09,0xc9,0xef,0x54,0x03,0xfe,0xef,0x03} },
+{  16,0x09b2,0,{0x03,0x54,0x3f,0xff,0x90,0x7f,0x63,0x05,0x86,0x02,0x0a,0x36,0x05,0x86,0x02,0x0a} },
+{  16,0x09c2,0,{0xa5,0x05,0x86,0x02,0x0a,0x8e,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0} },
+{  16,0x09d2,0,{0xe0,0x05,0x86,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0x05,0x86} },
+{  16,0x09e2,0,{0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0} },
+{  16,0x09f2,0,{0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0x05,0x86,0xdf,0xca,0xee,0xb4,0x00,0x03} },
+{  16,0x0a02,0,{0x02,0x0a,0xb2,0xb4,0x01,0x03,0x02,0x0a,0x25,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0x05} },
+{  16,0x0a12,0,{0x86,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0} },
+{  16,0x0a22,0,{0xe0,0x05,0x86,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0x05,0x86} },
+{  16,0x0a32,0,{0x02,0x0a,0xb2,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0} },
+{  13,0x0a42,0,{0xe0,0x05,0x86,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0xe0,0x05,0x86} },
+{  16,0x0a4f,0,{0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0x05,0x86,0xdf,0xd6} },
+{  16,0x0a5f,0,{0xee,0xb4,0x00,0x03,0x02,0x0a,0xb2,0xb4,0x01,0x03,0x02,0x0a,0x80,0xe0,0xe0,0xe0} },
+{  16,0x0a6f,0,{0xe0,0x05,0x86,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0x05} },
+{  16,0x0a7f,0,{0x86,0xe0,0xe0,0xe0,0xe0,0x05,0x86,0xe0,0xe0,0x05,0x86,0x02,0x0a,0xb2,0xe0,0xe0} },
+{  16,0x0a8f,0,{0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0} },
+{  16,0x0a9f,0,{0xdf,0xec,0x02,0x0a,0xb2,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0,0xe0} },
+{  16,0x0aaf,0,{0xe0,0xdf,0xf2,0x90,0x7f,0xe2,0x74,0x00,0xf0,0xd0,0x85,0xd0,0x84,0x05,0x86,0xd0} },
+{  14,0x0abf,0,{0x83,0xd0,0x82,0xd0,0xe0,0xfe,0xd0,0xe0,0xff,0xd0,0xe0,0xd0,0xd0,0x22} },
+{  16,0x0acd,0,{0xc0,0x82,0xc0,0x83,0xc0,0xe0,0xe8,0xc0,0xe0,0x78,0xd1,0xe8,0x14,0xf8,0x70,0xfb} },
+{  10,0x0add,0,{0xd0,0xe0,0xf8,0xd0,0xe0,0xd0,0x83,0xd0,0x82,0x22} },
+{  16,0x0ae7,0,{0xc0,0xd0,0xc0,0xe0,0x8f,0xe0,0xc0,0xe0,0x8e,0xe0,0xc0,0xe0,0x8d,0xe0,0xc0,0xe0} },
+{  16,0x0af7,0,{0x8c,0xe0,0xc0,0xe0,0x75,0x86,0x00,0xc0,0x82,0xc0,0x83,0x05,0x86,0xc0,0x84,0xc0} },
+{  16,0x0b07,0,{0x85,0x7e,0x00,0x90,0x79,0x8e,0xe0,0xb4,0x00,0x16,0x74,0x01,0xf0,0x90,0x06,0xca} },
+{  16,0x0b17,0,{0xa3,0xa3,0xa3,0xa3,0xa3,0xa3,0xa3,0xe0,0xff,0x90,0x79,0x8d,0xf0,0x02,0x0b,0x39} },
+{  16,0x0b27,0,{0x90,0x79,0x8d,0xe0,0xff,0x90,0x79,0x8f,0xe0,0xfd,0x90,0x79,0x90,0xe0,0xfc,0x02} },
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+{  16,0x0b47,0,{0x84,0x8c,0x85,0x05,0x86,0x90,0x7f,0x00,0x05,0x86,0xe0,0xa3,0x05,0x86,0xf0,0xa3} },
+{  16,0x0b57,0,{0x0e,0xee,0xb4,0x40,0x03,0x02,0x0b,0x6c,0x05,0x86,0xdf,0xee,0x90,0x79,0x8e,0x74} },
+{  16,0x0b67,0,{0x00,0xf0,0x02,0x0b,0x82,0x05,0x86,0xad,0x84,0xac,0x85,0x90,0x79,0x8f,0xed,0xf0} },
+{  16,0x0b77,0,{0x90,0x79,0x90,0xec,0xf0,0x90,0x79,0x8d,0x1f,0xef,0xf0,0x90,0x7f,0xb5,0xee,0xf0} },
+{  16,0x0b87,0,{0xd0,0x85,0xd0,0x84,0x05,0x86,0xd0,0x83,0xd0,0x82,0xd0,0xe0,0xfc,0xd0,0xe0,0xfd} },
+{  11,0x0b97,0,{0xd0,0xe0,0xfe,0xd0,0xe0,0xff,0xd0,0xe0,0xd0,0xd0,0x22} },
+{  16,0x0ba2,0,{0xc0,0xd0,0xc0,0xe0,0xc0,0x82,0xc0,0x83,0x90,0x7f,0xae,0xe0,0x54,0xe0,0xf0,0x90} },
+{  16,0x0bb2,0,{0x7f,0x96,0xe0,0x44,0x08,0x54,0xfb,0xf0,0x90,0x7f,0x97,0xe0,0x54,0xbf,0xf0,0x90} },
+{  16,0x0bc2,0,{0x7f,0xe3,0x74,0x7b,0xf0,0x90,0x7f,0xe4,0x74,0x40,0xf0,0x90,0x79,0x78,0xe0,0x90} },
+{  16,0x0bd2,0,{0x7b,0x40,0xf0,0x90,0x7f,0xe2,0x74,0x48,0xf0,0x90,0x7f,0xe5,0xe0,0x90,0x7f,0xe2} },
+{  16,0x0be2,0,{0x74,0x00,0xf0,0x90,0x7f,0x96,0xe0,0x54,0xf7,0x44,0x04,0xf0,0x90,0x7f,0xe3,0x74} },
+{  16,0x0bf2,0,{0x7b,0xf0,0x90,0x7f,0xe4,0x74,0x40,0xf0,0x90,0x79,0x79,0xe0,0x90,0x7b,0x40,0xf0} },
+{  16,0x0c02,0,{0x90,0x7f,0xe2,0x74,0x48,0xf0,0x90,0x7f,0xe5,0xe0,0x90,0x7f,0xe2,0x74,0x00,0xf0} },
+{  16,0x0c12,0,{0x90,0x7f,0x96,0xe0,0x54,0xf3,0xf0,0x90,0x7f,0xae,0xe0,0x44,0x1f,0xf0,0xd0,0x83} },
+{   7,0x0c22,0,{0xd0,0x82,0xd0,0xe0,0xd0,0xd0,0x22} },
+{  16,0x0c29,0,{0xc0,0xd0,0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x90,0x79,0x2f,0xe0,0x64,0xff,0xc3,0x24} },
+{  11,0x0c39,0,{0x01,0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0xd0,0xd0,0x22} },
+{  16,0x0c44,0,{0xbb,0x01,0x06,0x89,0x82,0x8a,0x83,0xe0,0x22,0x50,0x02,0xe7,0x22,0xbb,0xfe,0x02} },
+{   9,0x0c54,0,{0xe3,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0x22} },
+{  16,0x0c5d,0,{0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50} },
+{  16,0x0c6d,0,{0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22} },
+{  13,0x0c7d,0,{0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22} },
+{  16,0x0c8a,0,{0xbb,0x01,0x06,0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01} },
+{   2,0x0c9a,0,{0xf3,0x22} },
+{  16,0x0c9c,0,{0xf8,0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0} },
+{  16,0x0cac,0,{0x22,0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8} },
+{   2,0x0cbc,0,{0xf2,0x22} },
+{  16,0x0cbe,0,{0xc2,0xd5,0xec,0x30,0xe7,0x09,0xb2,0xd5,0xe4,0xc3,0x9d,0xfd,0xe4,0x9c,0xfc,0xee} },
+{  16,0x0cce,0,{0x30,0xe7,0x15,0xb2,0xd5,0xe4,0xc3,0x9f,0xff,0xe4,0x9e,0xfe,0x12,0x0e,0x40,0xc3} },
+{  16,0x0cde,0,{0xe4,0x9d,0xfd,0xe4,0x9c,0xfc,0x80,0x03,0x12,0x0e,0x40,0x30,0xd5,0x07,0xc3,0xe4} },
+{   6,0x0cee,0,{0x9f,0xff,0xe4,0x9e,0xfe,0x22} },
+{  16,0x0cf4,0,{0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,0x02} },
+{   6,0x0d04,0,{0x15,0x83,0xe0,0x38,0xf0,0x22} },
+{  16,0x0d0a,0,{0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0} },
+{  16,0x0d1a,0,{0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe} },
+{  16,0x0d2a,0,{0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83} },
+{   8,0x0d3a,0,{0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22} },
+{  16,0x0d42,0,{0xe8,0x8f,0xf0,0xa4,0xcc,0x8b,0xf0,0xa4,0x2c,0xfc,0xe9,0x8e,0xf0,0xa4,0x2c,0xfc} },
+{  16,0x0d52,0,{0x8a,0xf0,0xed,0xa4,0x2c,0xfc,0xea,0x8e,0xf0,0xa4,0xcd,0xa8,0xf0,0x8b,0xf0,0xa4} },
+{  16,0x0d62,0,{0x2d,0xcc,0x38,0x25,0xf0,0xfd,0xe9,0x8f,0xf0,0xa4,0x2c,0xcd,0x35,0xf0,0xfc,0xeb} },
+{  16,0x0d72,0,{0x8e,0xf0,0xa4,0xfe,0xa9,0xf0,0xeb,0x8f,0xf0,0xa4,0xcf,0xc5,0xf0,0x2e,0xcd,0x39} },
+{  15,0x0d82,0,{0xfe,0xe4,0x3c,0xfc,0xea,0xa4,0x2d,0xce,0x35,0xf0,0xfd,0xe4,0x3c,0xfc,0x22} },
+{  16,0x0d91,0,{0xeb,0x9f,0xf5,0xf0,0xea,0x9e,0x42,0xf0,0xe9,0x9d,0x42,0xf0,0xe8,0x9c,0x45,0xf0} },
+{   1,0x0da1,0,{0x22} },
+{  16,0x0da2,0,{0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0x02,0x0e,0xa1} },
+{  16,0x0db2,0,{0x50,0x07,0xe9,0x25,0x82,0xf8,0x02,0x0e,0x95,0xbb,0xfe,0x07,0xe9,0x25,0x82,0xf8} },
+{  16,0x0dc2,0,{0x02,0x0e,0xad,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0x02,0x0e,0xb9} },
+{  16,0x0dd2,0,{0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0x02,0x0e,0xd5} },
+{  16,0x0de2,0,{0x50,0x07,0xe9,0x25,0x82,0xf8,0x02,0x0e,0xc9,0xbb,0xfe,0x07,0xe9,0x25,0x82,0xf8} },
+{   4,0x0df2,0,{0x02,0x0e,0xe1,0x22} },
+{  16,0x0df6,0,{0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0x02,0x0f,0x06} },
+{  16,0x0e06,0,{0x50,0x07,0xe9,0x25,0x82,0xf8,0x02,0x0e,0xed,0xbb,0xfe,0x07,0xe9,0x25,0x82,0xf8} },
+{   4,0x0e16,0,{0x02,0x0f,0x37,0x22} },
+{  16,0x0e1a,0,{0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3} },
+{  16,0x0e2a,0,{0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68,0x60} },
+{   6,0x0e3a,0,{0xef,0xa3,0xa3,0xa3,0x80,0xdf} },
+{  16,0x0e40,0,{0xbc,0x00,0x0b,0xbe,0x00,0x29,0xef,0x8d,0xf0,0x84,0xff,0xad,0xf0,0x22,0xe4,0xcc} },
+{  16,0x0e50,0,{0xf8,0x75,0xf0,0x08,0xef,0x2f,0xff,0xee,0x33,0xfe,0xec,0x33,0xfc,0xee,0x9d,0xec} },
+{  16,0x0e60,0,{0x98,0x40,0x05,0xfc,0xee,0x9d,0xfe,0x0f,0xd5,0xf0,0xe9,0xe4,0xce,0xfd,0x22,0xed} },
+{  16,0x0e70,0,{0xf8,0xf5,0xf0,0xee,0x84,0x20,0xd2,0x1c,0xfe,0xad,0xf0,0x75,0xf0,0x08,0xef,0x2f} },
+{  16,0x0e80,0,{0xff,0xed,0x33,0xfd,0x40,0x07,0x98,0x50,0x06,0xd5,0xf0,0xf2,0x22,0xc3,0x98,0xfd} },
+{   5,0x0e90,0,{0x0f,0xd5,0xf0,0xea,0x22} },
+{  12,0x0e95,0,{0xe6,0xfc,0x08,0xe6,0xfd,0x08,0xe6,0xfe,0x08,0xe6,0xff,0x22} },
+{  12,0x0ea1,0,{0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22} },
+{  12,0x0ead,0,{0xe2,0xfc,0x08,0xe2,0xfd,0x08,0xe2,0xfe,0x08,0xe2,0xff,0x22} },
+{  16,0x0eb9,0,{0xe4,0x93,0xfc,0xa3,0xe4,0x93,0xfd,0xa3,0xe4,0x93,0xfe,0xa3,0xe4,0x93,0xff,0x22} },
+{  12,0x0ec9,0,{0xec,0xf6,0x08,0xed,0xf6,0x08,0xee,0xf6,0x08,0xef,0xf6,0x22} },
+{  12,0x0ed5,0,{0xec,0xf0,0xa3,0xed,0xf0,0xa3,0xee,0xf0,0xa3,0xef,0xf0,0x22} },
+{  12,0x0ee1,0,{0xec,0xf2,0x08,0xed,0xf2,0x08,0xee,0xf2,0x08,0xef,0xf2,0x22} },
+{  16,0x0eed,0,{0xd0,0x83,0xd0,0x82,0xe4,0x93,0xf6,0x08,0x74,0x01,0x93,0xf6,0x08,0x74,0x02,0x93} },
+{   9,0x0efd,0,{0xf6,0x08,0x74,0x03,0x93,0xf6,0x74,0x04,0x73} },
+{  16,0x0f06,0,{0xa8,0x82,0x85,0x83,0xf0,0xd0,0x83,0xd0,0x82,0x12,0x0f,0x1d,0x12,0x0f,0x1d,0x12} },
+{  16,0x0f16,0,{0x0f,0x1d,0x12,0x0f,0x1d,0xe4,0x73,0xe4,0x93,0xa3,0xc5,0x83,0xc5,0xf0,0xc5,0x83} },
+{  16,0x0f26,0,{0xc8,0xc5,0x82,0xc8,0xf0,0xa3,0xc5,0x83,0xc5,0xf0,0xc5,0x83,0xc8,0xc5,0x82,0xc8} },
+{   1,0x0f36,0,{0x22} },
+{  16,0x0f37,0,{0xd0,0x83,0xd0,0x82,0xe4,0x93,0xf2,0x08,0x74,0x01,0x93,0xf2,0x08,0x74,0x02,0x93} },
+{   9,0x0f47,0,{0xf2,0x08,0x74,0x03,0x93,0xf2,0x74,0x04,0x73} },
+{  16,0x0f50,0,{0xc2,0xaf,0xd2,0x2c,0x90,0x7f,0x93,0x74,0x30,0xf0,0x90,0x7f,0x9c,0x74,0xbf,0xf0} },
+{  16,0x0f60,0,{0x90,0x7f,0x96,0xe0,0x54,0x30,0xf0,0x90,0x7f,0x94,0x74,0x30,0xf0,0x90,0x7f,0x9d} },
+{  16,0x0f70,0,{0x74,0xcf,0xf0,0x90,0x7f,0x97,0x74,0xa0,0xf0,0x90,0x7f,0x95,0x74,0xcc,0xf0,0xe4} },
+{  16,0x0f80,0,{0x90,0x7f,0x9e,0xf0,0xc2,0x2d,0xc2,0x2a,0xc2,0x2b,0xc2,0x2e,0x90,0x79,0x74,0x04} },
+{  16,0x0f90,0,{0xf0,0x12,0x2e,0x94,0x12,0x49,0xe2,0x12,0x4b,0xe6,0x12,0x32,0x0d,0x12,0x3b,0x0d} },
+{  16,0x0fa0,0,{0x12,0x41,0xfd,0x12,0x3e,0x99,0xe5,0x1f,0x70,0x18,0x75,0x1f,0x01,0x12,0x17,0xff} },
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+{  16,0x0fc0,0,{0x1b,0x40,0x12,0x39,0x8d,0x90,0x7f,0xaf,0xe0,0x44,0x01,0xf0,0x90,0x7f,0xae,0xe0} },
+{  16,0x0fd0,0,{0x44,0x1f,0xf0,0x90,0x7f,0xac,0x74,0xff,0xf0,0x90,0x7f,0xad,0xf0,0x90,0x7f,0xde} },
+{  16,0x0fe0,0,{0xf0,0x90,0x7f,0xdf,0xf0,0x90,0x7f,0xab,0xf0,0x90,0x7f,0xa9,0xf0,0x90,0x7f,0xaa} },
+{  16,0x0ff0,0,{0xf0,0x53,0x91,0xef,0x43,0xd8,0x20,0xd2,0xe8,0x43,0xd8,0x20,0x43,0xa8,0x80,0x22} },
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+{  16,0x1010,0,{0xd9,0x14,0x70,0x02,0x61,0xd7,0x24,0x04,0x60,0x02,0x81,0x56,0xe4,0x90,0x79,0x78} },
+{  16,0x1020,0,{0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79,0xf0,0x44,0x01,0xf0,0x54,0xfd,0xf0,0x90} },
+{  16,0x1030,0,{0x79,0x7b,0xf0,0xe4,0x90,0x79,0x88,0xf0,0xa2,0xaf,0x33,0xf5,0x12,0xc2,0xaf,0x12} },
+{  16,0x1040,0,{0x0b,0xa2,0xe5,0x12,0x70,0x02,0x81,0x56,0xd2,0xaf,0x22,0x90,0x79,0x2d,0xe0,0x64} },
+{  16,0x1050,0,{0x01,0x70,0x79,0x90,0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74,0x30,0xf0,0x90,0x7f,0xff} },
+{  16,0x1060,0,{0x74,0xfc,0xf0,0xe4,0x90,0x79,0x78,0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79,0xf0} },
+{  16,0x1070,0,{0x44,0x01,0xf0,0x44,0x02,0xf0,0x90,0x79,0x7b,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12} },
+{  16,0x1080,0,{0xc2,0xaf,0x12,0x0b,0xa2,0x90,0x79,0x78,0x74,0x02,0xf0,0x90,0x79,0x84,0xe0,0x90} },
+{  16,0x1090,0,{0x79,0x79,0xf0,0x90,0x79,0x7f,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54,0xfe} },
+{  16,0x10a0,0,{0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x54,0xfd} },
+{  16,0x10b0,0,{0xf0,0x54,0xfb,0xf0,0x90,0x79,0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74,0x04} },
+{  16,0x10c0,0,{0xf0,0x90,0x79,0x88,0x14,0xf0,0xe5,0x12,0x60,0x02,0xd2,0xaf,0x90,0x79,0x2d,0xe0} },
+{  16,0x10d0,0,{0x64,0x02,0x70,0x79,0x90,0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74,0x34,0xf0,0x90,0x7f} },
+{  16,0x10e0,0,{0xff,0x74,0xfc,0xf0,0xe4,0x90,0x79,0x78,0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79} },
+{  16,0x10f0,0,{0xf0,0x44,0x01,0xf0,0x44,0x02,0xf0,0x90,0x79,0x7b,0xf0,0xa2,0xaf,0xe4,0x33,0xf5} },
+{  16,0x1100,0,{0x12,0xc2,0xaf,0x12,0x0b,0xa2,0x90,0x79,0x78,0x74,0x02,0xf0,0x90,0x79,0x84,0xe0} },
+{  16,0x1110,0,{0x90,0x79,0x79,0xf0,0x90,0x79,0x7f,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54} },
+{  16,0x1120,0,{0xfe,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x44} },
+{  16,0x1130,0,{0x02,0xf0,0x54,0xfb,0xf0,0x90,0x79,0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74} },
+{  16,0x1140,0,{0x04,0xf0,0x90,0x79,0x88,0x14,0xf0,0xe5,0x12,0x60,0x02,0xd2,0xaf,0x90,0x79,0x2d} },
+{  16,0x1150,0,{0xe0,0x64,0x03,0x60,0x02,0x81,0x56,0x90,0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74,0x64} },
+{  16,0x1160,0,{0xf0,0x90,0x7f,0xff,0x74,0xfc,0xf0,0xe4,0x90,0x79,0x78,0xf0,0x90,0x79,0x7b,0xe0} },
+{  16,0x1170,0,{0x90,0x79,0x79,0xf0,0x44,0x01,0xf0,0x44,0x02,0xf0,0x90,0x79,0x7b,0xf0,0xa2,0xaf} },
+{  16,0x1180,0,{0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b,0xa2,0x90,0x79,0x78,0x74,0x02,0xf0,0x90} },
+{  16,0x1190,0,{0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79,0x7f,0xe0,0xb4,0x01,0x09,0x90,0x79} },
+{  16,0x11a0,0,{0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x44,0x01,0xf0,0x90,0x79} },
+{  16,0x11b0,0,{0x79,0xe0,0x44,0x04,0xf0,0x90,0x79,0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74} },
+{  16,0x11c0,0,{0x04,0xf0,0x90,0x79,0x88,0x14,0xf0,0xe5,0x12,0x70,0x02,0x81,0x56,0xd2,0xaf,0x22} },
+{  16,0x11d0,0,{0x90,0x79,0x2d,0xe0,0x64,0x01,0x70,0x7a,0x90,0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74} },
+{  16,0x11e0,0,{0x88,0xf0,0x90,0x7f,0xff,0x74,0xfc,0xf0,0xe4,0x90,0x79,0x78,0xf0,0x90,0x79,0x7b} },
+{  16,0x11f0,0,{0xe0,0x90,0x79,0x79,0xf0,0x44,0x01,0xf0,0x54,0xfd,0xf0,0x90,0x79,0x7b,0xf0,0xa2} },
+{  16,0x1200,0,{0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b,0xa2,0x90,0x79,0x78,0x74,0x02,0xf0} },
+{  16,0x1210,0,{0x90,0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79,0x7f,0xe0,0xb4,0x01,0x09,0x90} },
+{  16,0x1220,0,{0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x44,0x01,0xf0,0x90} },
+{  16,0x1230,0,{0x79,0x79,0xe0,0x54,0xfd,0xf0,0x54,0xfb,0xf0,0x90,0x79,0x84,0xf0,0x12,0x0b,0xa2} },
+{  16,0x1240,0,{0x90,0x79,0x82,0x74,0x0c,0xf0,0x90,0x79,0x88,0x74,0x01,0xf0,0xe5,0x12,0x60,0x02} },
+{  16,0x1250,0,{0xd2,0xaf,0x90,0x79,0x2d,0xe0,0x64,0x02,0x60,0x02,0x81,0x56,0x90,0x7f,0xf2,0xf0} },
+{  16,0x1260,0,{0x90,0x7f,0xf3,0x74,0x94,0xf0,0x90,0x7f,0xff,0x74,0xfc,0xf0,0xe4,0x90,0x79,0x78} },
+{  16,0x1270,0,{0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79,0xf0,0x44,0x01,0xf0,0x54,0xfd,0xf0,0x90} },
+{  16,0x1280,0,{0x79,0x7b,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b,0xa2,0x90,0x79} },
+{  16,0x1290,0,{0x78,0x74,0x02,0xf0,0x90,0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79,0x7f,0xe0} },
+{  16,0x12a0,0,{0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0} },
+{  16,0x12b0,0,{0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x44,0x02,0xf0,0x54,0xfb,0xf0,0x90,0x79,0x84} },
+{  16,0x12c0,0,{0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74,0x0c,0xf0,0x90,0x79,0x88,0x74,0x01,0xf0} },
+{  16,0x12d0,0,{0xe5,0x12,0x70,0x02,0x81,0x56,0xd2,0xaf,0x22,0x90,0x79,0x2d,0xe0,0x64,0x01,0x70} },
+{  16,0x12e0,0,{0x77,0x90,0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74,0xcc,0xf0,0x90,0x7f,0xff,0x74,0xfc} },
+{  16,0x12f0,0,{0xf0,0xe4,0x90,0x79,0x78,0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79,0xf0,0x54,0xfc} },
+{  16,0x1300,0,{0xf0,0x90,0x79,0x7b,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b,0xa2} },
+{  16,0x1310,0,{0x90,0x79,0x78,0x74,0x02,0xf0,0x90,0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79} },
+{  16,0x1320,0,{0x7f,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79} },
+{  16,0x1330,0,{0x79,0xe0,0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x54,0xfd,0xf0,0x54,0xfb,0xf0,0x90} },
+{  16,0x1340,0,{0x79,0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74,0x12,0xf0,0x90,0x79,0x88,0x74} },
+{  16,0x1350,0,{0x02,0xf0,0xe5,0x12,0x60,0x02,0xd2,0xaf,0x90,0x79,0x2d,0xe0,0x64,0x02,0x70,0x77} },
+{  16,0x1360,0,{0x90,0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74,0xe0,0xf0,0x90,0x7f,0xff,0x74,0xfc,0xf0} },
+{  16,0x1370,0,{0xe4,0x90,0x79,0x78,0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79,0xf0,0x54,0xfc,0xf0} },
+{  16,0x1380,0,{0x90,0x79,0x7b,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b,0xa2,0x90} },
+{  16,0x1390,0,{0x79,0x78,0x74,0x02,0xf0,0x90,0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79,0x7f} },
+{  16,0x13a0,0,{0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79,0x79} },
+{  16,0x13b0,0,{0xe0,0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x44,0x02,0xf0,0x54,0xfb,0xf0,0x90,0x79} },
+{  16,0x13c0,0,{0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74,0x12,0xf0,0x90,0x79,0x88,0x74,0x02} },
+{  16,0x13d0,0,{0xf0,0xe5,0x12,0x60,0x02,0xd2,0xaf,0x90,0x79,0x2d,0xe0,0x64,0x03,0x70,0x77,0x90} },
+{  16,0x13e0,0,{0x7f,0xf2,0xf0,0x90,0x7f,0xf3,0x74,0x94,0xf0,0x90,0x7f,0xff,0x74,0xfc,0xf0,0xe4} },
+{  16,0x13f0,0,{0x90,0x79,0x78,0xf0,0x90,0x79,0x7b,0xe0,0x90,0x79,0x79,0xf0,0x54,0xfe,0xf0,0x44} },
+{  16,0x1400,0,{0x02,0xf0,0x90,0x79,0x7b,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b} },
+{  16,0x1410,0,{0xa2,0x90,0x79,0x78,0x74,0x02,0xf0,0x90,0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90} },
+{  16,0x1420,0,{0x79,0x7f,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90} },
+{  16,0x1430,0,{0x79,0x79,0xe0,0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x44,0x04,0xf0,0x90,0x79,0x84} },
+{  16,0x1440,0,{0xf0,0x12,0x0b,0xa2,0x90,0x79,0x82,0x74,0x06,0xf0,0x90,0x79,0x88,0x74,0x04,0xf0} },
+{   7,0x1450,0,{0xe5,0x12,0x60,0x02,0xd2,0xaf,0x22} },
+{  16,0x1457,0,{0xc2,0x28,0xc2,0x29,0x90,0x7f,0xe8,0xe0,0x12,0x0e,0x1a,0x14,0x84,0x00,0x14,0xe0} },
+{  16,0x1467,0,{0x01,0x14,0xf6,0x02,0x16,0x7c,0x21,0x16,0xbe,0x22,0x15,0x91,0x80,0x15,0xd1,0x81} },
+{  16,0x1477,0,{0x16,0x2e,0x82,0x16,0xcf,0xa1,0x17,0x05,0xa2,0x00,0x00,0x17,0x0a,0x90,0x7f,0xe9} },
+{  16,0x1487,0,{0xe0,0x14,0x60,0x11,0x24,0xfe,0x60,0x28,0x24,0xfe,0x60,0x3b,0x24,0xfc,0x70,0x40} },
+{  16,0x1497,0,{0x12,0x4a,0x2a,0xe1,0x16,0x12,0x4b,0xe0,0x40,0x02,0xe1,0x16,0x90,0x7f,0xea,0xe0} },
+{  16,0x14a7,0,{0xb4,0x01,0x04,0xc2,0x2a,0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16} },
+{  16,0x14b7,0,{0x12,0x4b,0xe2,0x90,0x7f,0xea,0xe0,0xb4,0x01,0x04,0xd2,0x2a,0xe1,0x16,0x90,0x7f} },
+{  16,0x14c7,0,{0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16} },
+{  16,0x14d7,0,{0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xe9,0xe0,0x24,0xf5,0x70} },
+{  16,0x14e7,0,{0x05,0x12,0x47,0x9c,0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90} },
+{  16,0x14f7,0,{0x7f,0xe9,0xe0,0x24,0xfd,0x60,0x54,0x24,0x02,0x60,0x02,0xa1,0x88,0x12,0x4b,0xe0} },
+{  16,0x1507,0,{0x40,0x02,0xe1,0x16,0x90,0x7f,0xea,0xe0,0x70,0x38,0x90,0x7f,0xec,0xe0,0xf4,0x54} },
+{  16,0x1517,0,{0x80,0xff,0xc4,0x54,0x0f,0xff,0xe0,0x54,0x07,0x2f,0x25,0xe0,0x24,0xb4,0xf5,0x82} },
+{  16,0x1527,0,{0xe4,0x34,0x7f,0xf5,0x83,0xe4,0xf0,0x90,0x7f,0xec,0xe0,0x54,0x80,0xff,0x13,0x13} },
+{  16,0x1537,0,{0x13,0x54,0x1f,0xff,0xe0,0x54,0x07,0x2f,0x90,0x7f,0xd7,0xf0,0xe0,0x44,0x20,0xf0} },
+{  16,0x1547,0,{0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x12,0x4b,0xe2,0x40,0x02} },
+{  16,0x1557,0,{0xe1,0x16,0x90,0x7f,0xea,0xe0,0x70,0x20,0x90,0x7f,0xec,0xe0,0xf4,0x54,0x80,0xff} },
+{  16,0x1567,0,{0xc4,0x54,0x0f,0xff,0xe0,0x54,0x07,0x2f,0x25,0xe0,0x24,0xb4,0xf5,0x82,0xe4,0x34} },
+{  16,0x1577,0,{0x7f,0xf5,0x83,0x74,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1} },
+{  16,0x1587,0,{0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xe9,0xe0,0x60,0x12} },
+{  16,0x1597,0,{0x24,0xf8,0x60,0x09,0x24,0x02,0x70,0x29,0x12,0x17,0x1e,0xe1,0x16,0x12,0x4b,0xa0} },
+{  16,0x15a7,0,{0xe1,0x16,0x12,0x4b,0xde,0xa2,0x2a,0xe4,0x33,0xff,0x25,0xe0,0xff,0xa2,0x2b,0xe4} },
+{  16,0x15b7,0,{0x33,0x4f,0x90,0x7f,0x00,0xf0,0xe4,0xa3,0xf0,0x90,0x7f,0xb5,0x74,0x02,0xf0,0xe1} },
+{  16,0x15c7,0,{0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xe9,0xe0,0x60,0x37} },
+{  16,0x15d7,0,{0x24,0xf6,0x60,0x2e,0x24,0x04,0x70,0x41,0x90,0x7f,0xeb,0xe0,0x24,0xde,0x60,0x0e} },
+{  16,0x15e7,0,{0x04,0x70,0x16,0xd2,0x29,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0xd2,0x29} },
+{  16,0x15f7,0,{0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{  16,0x1607,0,{0xe1,0x16,0x12,0x44,0x63,0xe1,0x16,0x12,0x4b,0xde,0xe4,0x90,0x7f,0x00,0xf0,0xa3} },
+{  16,0x1617,0,{0xf0,0x90,0x7f,0xb5,0x74,0x02,0xf0,0xe1,0x16,0x20,0x29,0x07,0x90,0x7f,0xb4,0xe0} },
+{  16,0x1627,0,{0x44,0x01,0xf0,0xc2,0x29,0xe1,0x16,0x90,0x7f,0xe9,0xe0,0x24,0xf4,0x60,0x34,0x24} },
+{  16,0x1637,0,{0x0c,0x70,0x39,0x12,0x4b,0xde,0x90,0x7f,0xec,0xe0,0xf4,0x54,0x80,0xff,0xc4,0x54} },
+{  16,0x1647,0,{0x0f,0xff,0xe0,0x54,0x07,0x2f,0x25,0xe0,0x24,0xb4,0xf5,0x82,0xe4,0x34,0x7f,0xf5} },
+{  16,0x1657,0,{0x83,0xe0,0x54,0xfd,0x90,0x7f,0x00,0xf0,0xe4,0xa3,0xf0,0x90,0x7f,0xb5,0x74,0x02} },
+{  16,0x1667,0,{0xf0,0xe1,0x16,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xb4,0xe0} },
+{  16,0x1677,0,{0x44,0x01,0xf0,0xe1,0x16,0x90,0x7f,0xe9,0xe0,0x24,0xf6,0x60,0x12,0x14,0x60,0x1a} },
+{  16,0x1687,0,{0x24,0x02,0x70,0x1d,0xd2,0x28,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x80,0x12,0xd2} },
+{  16,0x1697,0,{0x28,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x80,0x07,0x90,0x7f,0xb4,0xe0,0x44,0x01} },
+{  16,0x16a7,0,{0xf0,0x20,0x28,0x0f,0x90,0x79,0x85,0x74,0x01,0xf0,0x12,0x49,0x6f,0x90,0x7f,0xc5} },
+{  16,0x16b7,0,{0x74,0x02,0xf0,0xc2,0x28,0x80,0x58,0x90,0x79,0x86,0x74,0x01,0xf0,0x12,0x49,0x6f} },
+{  16,0x16c7,0,{0x90,0x7f,0xc5,0x74,0x02,0xf0,0x80,0x47,0x90,0x7f,0xe9,0xe0,0x24,0xfe,0x60,0x12} },
+{  16,0x16d7,0,{0x14,0x60,0x1a,0x24,0x02,0x70,0x1d,0xd2,0x28,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{  16,0x16e7,0,{0x80,0x12,0xd2,0x28,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x80,0x07,0x90,0x7f,0xb4} },
+{  16,0x16f7,0,{0xe0,0x44,0x01,0xf0,0x20,0x28,0x03,0x12,0x1a,0x7b,0xc2,0x28,0x80,0x11,0x12,0x2c} },
+{  16,0x1707,0,{0x2b,0x80,0x0c,0x12,0x4b,0xe4,0x50,0x07,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x90} },
+{   7,0x1717,0,{0x7f,0xb4,0xe0,0x44,0x02,0xf0,0x22} },
+{  16,0x171e,0,{0x12,0x4b,0xdc,0x40,0x02,0xe1,0xe3,0x90,0x7f,0xeb,0xe0,0x24,0xfe,0x60,0x1e,0x14} },
+{  16,0x172e,0,{0x60,0x46,0x14,0x60,0x6e,0x14,0x70,0x02,0xe1,0xd4,0x24,0x04,0x60,0x02,0xe1,0xdc} },
+{  16,0x173e,0,{0x74,0x05,0x90,0x7f,0xd4,0xf0,0x74,0x00,0x90,0x7f,0xd5,0xf0,0x22,0x90,0x7f,0xea} },
+{  16,0x174e,0,{0xe0,0xff,0x12,0x3f,0xa2,0x8b,0x33,0x8a,0x34,0x89,0x35,0xea,0x49,0x60,0x11,0xce} },
+{  16,0x175e,0,{0xea,0xce,0xee,0x90,0x7f,0xd4,0xf0,0xcf,0xe9,0xcf,0xef,0x90,0x7f,0xd5,0xf0,0x22} },
+{  16,0x176e,0,{0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f,0xea,0xe0,0xff,0x12,0x48,0x00} },
+{  16,0x177e,0,{0x8b,0x33,0x8a,0x34,0x89,0x35,0xea,0x49,0x60,0x11,0xce,0xea,0xce,0xee,0x90,0x7f} },
+{  16,0x178e,0,{0xd4,0xf0,0xcf,0xe9,0xcf,0xef,0x90,0x7f,0xd5,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44} },
+{  16,0x179e,0,{0x01,0xf0,0x22,0x90,0x7f,0xea,0xe0,0xff,0x90,0x7e,0xc0,0xe0,0xfd,0xa3,0xe0,0xfb} },
+{  16,0x17ae,0,{0x12,0x44,0xd2,0x8b,0x33,0x8a,0x34,0x89,0x35,0xea,0x49,0x60,0x11,0xce,0xea,0xce} },
+{  16,0x17be,0,{0xee,0x90,0x7f,0xd4,0xf0,0xcf,0xe9,0xcf,0xef,0x90,0x7f,0xd5,0xf0,0x22,0x90,0x7f} },
+{  16,0x17ce,0,{0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f} },
+{   5,0x17de,0,{0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x17e3,0,{0x22} },
+{  16,0x17e4,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x90,0x7f,0xc4,0xe4,0xf0,0x53,0x91,0xef,0x90,0x7f} },
+{  11,0x17f4,0,{0xab,0x74,0x04,0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{   1,0x17ff,0,{0x22} },
+{  16,0x1800,0,{0xe4,0x90,0x78,0x15,0xf0,0x7b,0x01,0x90,0x78,0x12,0x04,0xf0,0xa3,0x74,0x78,0xf0} },
+{  16,0x1810,0,{0xa3,0x74,0x58,0xf0,0x90,0x78,0x12,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90} },
+{  16,0x1820,0,{0x00,0x01,0x12,0x0c,0x5d,0xff,0x90,0x79,0x9a,0xe0,0x6f,0x60,0x18,0x90,0x78,0x15} },
+{  16,0x1830,0,{0xe0,0xc3,0x94,0x06,0x50,0x0f,0xe0,0x04,0xf0,0x90,0x78,0x13,0xe4,0x75,0xf0,0x0f} },
+{  16,0x1840,0,{0x12,0x0c,0xf4,0x80,0xcf,0x90,0x78,0x15,0xe0,0xb4,0x06,0x08,0x90,0x7f,0xb4,0xe0} },
+{  16,0x1850,0,{0x44,0x01,0xf0,0x22,0x90,0x78,0x12,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x12} },
+{  16,0x1860,0,{0x0c,0x44,0xff,0x24,0xbf,0x70,0x02,0x41,0x7a,0x24,0xe0,0x70,0x02,0x41,0x4c,0x24} },
+{  16,0x1870,0,{0x21,0x60,0x02,0x41,0x73,0x90,0x79,0x97,0xe0,0x24,0xfe,0x70,0x02,0x21,0x9a,0x14} },
+{  16,0x1880,0,{0x70,0x02,0x21,0xef,0x24,0x02,0x60,0x02,0x41,0x44,0x90,0x79,0x2d,0xe0,0xa3,0xf0} },
+{  16,0x1890,0,{0x90,0x79,0x23,0xe0,0xff,0xe4,0xfc,0xfd,0xfe,0xfb,0xfa,0x79,0x01,0xf8,0x12,0x0d} },
+{  16,0x18a0,0,{0x42,0xc8,0xec,0xc8,0xc9,0xed,0xc9,0xca,0xee,0xca,0xcb,0xef,0xcb,0x90,0x79,0x22} },
+{  16,0x18b0,0,{0xe0,0xfe,0xe4,0xfc,0xfd,0x2b,0xfb,0xea,0x3e,0xfa,0xed,0x39,0xf9,0xec,0x38,0xf8} },
+{  16,0x18c0,0,{0x90,0x79,0x21,0xe0,0xff,0xe4,0xfe,0xeb,0x2f,0xff,0xee,0x3a,0xfe,0xed,0x39,0xfd} },
+{  16,0x18d0,0,{0xec,0x38,0xfc,0x90,0x78,0x12,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00} },
+{  16,0x18e0,0,{0x02,0x12,0x0d,0xd2,0x90,0x00,0x02,0x12,0x0d,0xa2,0x7b,0x44,0x7a,0xac,0x79,0x00} },
+{  16,0x18f0,0,{0x78,0x00,0xc3,0x12,0x0d,0x91,0x70,0x05,0x90,0x79,0x2d,0x04,0xf0,0x90,0x78,0x12} },
+{  16,0x1900,0,{0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x02,0x12,0x0d,0xa2,0x7b,0x80} },
+{  16,0x1910,0,{0x7a,0xbb,0x79,0x00,0x78,0x00,0xc3,0x12,0x0d,0x91,0x70,0x06,0x90,0x79,0x2d,0x74} },
+{  16,0x1920,0,{0x02,0xf0,0x90,0x78,0x12,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x02} },
+{  16,0x1930,0,{0x12,0x0d,0xa2,0x7b,0x00,0x7a,0x77,0x79,0x01,0x78,0x00,0xc3,0x12,0x0d,0x91,0x70} },
+{  16,0x1940,0,{0x06,0x90,0x79,0x2d,0x74,0x03,0xf0,0x90,0x79,0x2d,0xe0,0xff,0xb4,0x01,0x09,0x75} },
+{  16,0x1950,0,{0x0c,0x67,0x75,0x0d,0x06,0x75,0x0e,0x0b,0xef,0xb4,0x02,0x08,0xe4,0xf5,0x0c,0xf5} },
+{  16,0x1960,0,{0x0d,0x75,0x0e,0x0c,0xef,0xb4,0x03,0x08,0xe4,0xf5,0x0c,0xf5,0x0d,0x75,0x0e,0x18} },
+{  16,0x1970,0,{0xef,0xb4,0x03,0x0d,0x90,0x79,0x2e,0xe0,0x64,0x03,0x60,0x05,0xd2,0x2f,0x12,0x3d} },
+{  16,0x1980,0,{0x79,0x90,0x79,0x2d,0xe0,0x64,0x03,0x60,0x0a,0xa3,0xe0,0xb4,0x03,0x05,0xc2,0x2f} },
+{  16,0x1990,0,{0x12,0x3d,0x79,0x12,0x10,0x00,0x12,0x28,0x01,0x22,0x90,0x79,0x23,0xe0,0xff,0xe4} },
+{  16,0x19a0,0,{0xfc,0xfd,0xfe,0xfb,0xfa,0x79,0x01,0xf8,0x12,0x0d,0x42,0xc8,0xec,0xc8,0xc9,0xed} },
+{  16,0x19b0,0,{0xc9,0xca,0xee,0xca,0xcb,0xef,0xcb,0x90,0x79,0x22,0xe0,0xfe,0xe4,0xfc,0xfd,0x2b} },
+{  16,0x19c0,0,{0xfb,0xea,0x3e,0xfa,0xed,0x39,0xf9,0xec,0x38,0xf8,0x90,0x79,0x21,0xe0,0xff,0xe4} },
+{  16,0x19d0,0,{0xfe,0xeb,0x2f,0xff,0xee,0x3a,0xfe,0xed,0x39,0xfd,0xec,0x38,0xfc,0x90,0x78,0x12} },
+{  16,0x19e0,0,{0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x06,0x12,0x0d,0xd2,0x22,0x90} },
+{  16,0x19f0,0,{0x79,0x23,0xe0,0xff,0xe4,0xfc,0xfd,0xfe,0xfb,0xfa,0x79,0x01,0xf8,0x12,0x0d,0x42} },
+{  16,0x1a00,0,{0xc8,0xec,0xc8,0xc9,0xed,0xc9,0xca,0xee,0xca,0xcb,0xef,0xcb,0x90,0x79,0x22,0xe0} },
+{  16,0x1a10,0,{0xfe,0xe4,0xfc,0xfd,0x2b,0xfb,0xea,0x3e,0xfa,0xed,0x39,0xf9,0xec,0x38,0xf8,0x90} },
+{  16,0x1a20,0,{0x79,0x21,0xe0,0xff,0xe4,0xfe,0xeb,0x2f,0xff,0xee,0x3a,0xfe,0xed,0x39,0xfd,0xec} },
+{  16,0x1a30,0,{0x38,0xfc,0x90,0x78,0x12,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x0a} },
+{  16,0x1a40,0,{0x12,0x0d,0xd2,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x79,0x97,0xe0} },
+{  16,0x1a50,0,{0x14,0x70,0x18,0x90,0x79,0x21,0xe0,0xff,0x90,0x78,0x12,0xe0,0xfb,0xa3,0xe0,0xfa} },
+{  16,0x1a60,0,{0xa3,0xe0,0xf9,0x90,0x00,0x0e,0xef,0x12,0x0c,0x9c,0x22,0x90,0x7f,0xb4,0xe0,0x44} },
+{  10,0x1a70,0,{0x01,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x1a7a,0,{0x22} },
+{  16,0x1a7b,0,{0xe4,0xff,0xfe,0x7b,0x01,0x90,0x78,0x0f,0x04,0xf0,0xa3,0x74,0x78,0xf0,0xa3,0x74} },
+{  16,0x1a8b,0,{0x2b,0xf0,0x90,0x78,0x0f,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x02} },
+{  16,0x1a9b,0,{0x12,0x0c,0x5d,0xfd,0x90,0x7f,0xec,0xe0,0x6d,0x60,0x13,0xef,0xc3,0x94,0x05,0x50} },
+{  16,0x1aab,0,{0x0d,0x0f,0x90,0x78,0x10,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x80,0xd4,0x8d,0x33} },
+{  16,0x1abb,0,{0x90,0x78,0x0f,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x12,0x0c} },
+{  16,0x1acb,0,{0x5d,0xfd,0x90,0x7f,0xed,0xe0,0x6d,0x60,0x13,0xee,0xc3,0x94,0x0b,0x50,0x0d,0x0e} },
+{  16,0x1adb,0,{0x90,0x78,0x10,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x80,0xd4,0x90,0x7f,0xed,0xe0} },
+{  16,0x1aeb,0,{0xf5,0x34,0xef,0x64,0x05,0x60,0x03,0xbe,0x0b,0x08,0x90,0x7f,0xb4,0xe0,0x44,0x01} },
+{  16,0x1afb,0,{0xf0,0x22,0x90,0x78,0x0f,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x12,0x0c,0x44} },
+{  16,0x1b0b,0,{0xff,0x24,0xf0,0x60,0x08,0x24,0x0f,0x70,0x0e,0x12,0x49,0x2a,0x22,0x12,0x4b,0x83} },
+{  14,0x1b1b,0,{0x90,0x79,0x20,0xe5,0x34,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x1b29,0,{0x22} },
+{  15,0x1b2a,0,{0x90,0x7f,0xea,0xe0,0xb4,0xff,0x04,0x12,0x34,0x16,0x22,0x12,0x38,0x00,0x22} },
+{   7,0x1b39,0,{0x53,0x98,0xfe,0x53,0x98,0xfd,0x32} },
+{  16,0x1b40,0,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} },
+{  16,0x1b50,0,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} },
+{  16,0x1b60,0,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} },
+{  16,0x1b70,0,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} },
+{  16,0x1b80,0,{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} },
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+{  16,0x2871,0,{0xf0,0x44,0x01,0xf0,0x44,0x02,0xf0,0x90,0x79,0x7e,0xe0,0xb4,0x01,0x09,0x90,0x79} },
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+{  16,0x2891,0,{0x79,0xe0,0x90,0x79,0x7c,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b} },
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+{  16,0x28c1,0,{0x79,0x79,0xe0,0x44,0x01,0xf0,0x90,0x79,0x79,0xe0,0x54,0xfd,0xf0,0x54,0xfb,0xf0} },
+{  16,0x28d1,0,{0x90,0x79,0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x7a,0x74,0x01,0xf0,0x90,0x79,0x65} },
+{  16,0x28e1,0,{0xf0,0xe5,0x12,0x60,0x02,0xd2,0xaf,0xe4,0x90,0x79,0x8c,0xf0,0x90,0x79,0x8b,0xf0} },
+{  16,0x28f1,0,{0x90,0x79,0x2d,0xe0,0x64,0x02,0x60,0x02,0x21,0x96,0x90,0x7f,0xfc,0x74,0xc8,0xf0} },
+{  16,0x2901,0,{0x90,0x7f,0xff,0x74,0xfc,0xf0,0x90,0x79,0x78,0x74,0x01,0xf0,0x90,0x79,0x7c,0xe0} },
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+{  16,0x29c1,0,{0x79,0x7e,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x44,0x04,0xf0,0x80,0x07,0x90} },
+{  16,0x29d1,0,{0x79,0x79,0xe0,0x54,0xfb,0xf0,0x90,0x79,0x79,0xe0,0x90,0x79,0x7c,0xf0,0xa2,0xaf} },
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+{  16,0x2ac1,0,{0x84,0xf0,0x12,0x0b,0xa2,0x90,0x79,0x7a,0x74,0x01,0xf0,0x90,0x79,0x65,0x04,0xf0} },
+{  16,0x2ad1,0,{0xe5,0x12,0x60,0x02,0xd2,0xaf,0xe4,0x90,0x79,0x8c,0xf0,0x90,0x79,0x8b,0xf0,0x90} },
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+{  16,0x2b11,0,{0x90,0x79,0x79,0xe0,0x44,0x04,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x54,0xfb,0xf0} },
+{  16,0x2b21,0,{0x90,0x79,0x79,0xe0,0x90,0x79,0x7c,0xf0,0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xc2,0xaf} },
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+{  16,0x2b41,0,{0xf0,0x90,0x79,0x7f,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80} },
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+{  16,0x2bb1,0,{0x7e,0xe0,0xb4,0x01,0x09,0x90,0x79,0x79,0xe0,0x44,0x04,0xf0,0x80,0x07,0x90,0x79} },
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+{  16,0x2bf1,0,{0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x44,0x01,0xf0,0x90,0x79,0x79} },
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+{  10,0x2c21,0,{0xe4,0x90,0x79,0x8c,0xf0,0x90,0x79,0x8b,0xf0,0x22} },
+{  16,0x2c2b,0,{0xe4,0xff,0x7b,0x01,0x90,0x78,0x16,0x04,0xf0,0xa3,0x74,0x78,0xf0,0xa3,0x74,0x58} },
+{  16,0x2c3b,0,{0xf0,0x90,0x78,0x16,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x12} },
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+{  16,0x2c6b,0,{0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x78,0x16,0xe0,0xfb,0xa3,0xe0,0xfa} },
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+{  16,0x2cdb,0,{0x7b,0x80,0x7a,0xbb,0x79,0x00,0x78,0x00,0xc3,0x12,0x0d,0x91,0x70,0x13,0x90,0x7f} },
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+{  16,0x2d4b,0,{0x0d,0x91,0x70,0x13,0x90,0x7f,0x00,0x74,0x44,0xf0,0xa3,0x74,0xac,0xf0,0xe4,0xa3} },
+{  16,0x2d5b,0,{0xf0,0x90,0x7f,0xb5,0x74,0x03,0xf0,0x90,0x78,0x16,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3} },
+{  16,0x2d6b,0,{0xe0,0xf9,0x90,0x00,0x06,0x12,0x0d,0xa2,0x7b,0x80,0x7a,0xbb,0x79,0x00,0x78,0x00} },
+{  16,0x2d7b,0,{0xc3,0x12,0x0d,0x91,0x70,0x13,0x90,0x7f,0x00,0x74,0x80,0xf0,0xa3,0x74,0xbb,0xf0} },
+{  16,0x2d8b,0,{0xe4,0xa3,0xf0,0x90,0x7f,0xb5,0x74,0x03,0xf0,0x90,0x78,0x16,0xe0,0xfb,0xa3,0xe0} },
+{  16,0x2d9b,0,{0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x06,0x12,0x0d,0xa2,0x7b,0x00,0x7a,0x77,0x79,0x01} },
+{  16,0x2dab,0,{0x78,0x00,0xc3,0x12,0x0d,0x91,0x60,0x02,0xc1,0x93,0x90,0x7f,0x00,0xf0,0xa3,0x74} },
+{  16,0x2dbb,0,{0x77,0xf0,0xa3,0x74,0x01,0xf0,0x90,0x7f,0xb5,0x74,0x03,0xf0,0x22,0x90,0x78,0x16} },
+{  16,0x2dcb,0,{0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x0a,0x12,0x0d,0xa2,0x7b,0x44} },
+{  16,0x2ddb,0,{0x7a,0xac,0x79,0x00,0x78,0x00,0xc3,0x12,0x0d,0x91,0x70,0x13,0x90,0x7f,0x00,0x74} },
+{  16,0x2deb,0,{0x44,0xf0,0xa3,0x74,0xac,0xf0,0xe4,0xa3,0xf0,0x90,0x7f,0xb5,0x74,0x03,0xf0,0x90} },
+{  16,0x2dfb,0,{0x78,0x16,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x0a,0x12,0x0d,0xa2} },
+{  16,0x2e0b,0,{0x7b,0x80,0x7a,0xbb,0x79,0x00,0x78,0x00,0xc3,0x12,0x0d,0x91,0x70,0x13,0x90,0x7f} },
+{  16,0x2e1b,0,{0x00,0x74,0x80,0xf0,0xa3,0x74,0xbb,0xf0,0xe4,0xa3,0xf0,0x90,0x7f,0xb5,0x74,0x03} },
+{  16,0x2e2b,0,{0xf0,0x90,0x78,0x16,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x0a,0x12} },
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+{  16,0x2e4b,0,{0x90,0x7f,0x00,0xf0,0xa3,0x74,0x77,0xf0,0xa3,0x74,0x01,0xf0,0x90,0x7f,0xb5,0x74} },
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+{   8,0x2e8b,0,{0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x2e93,0,{0x22} },
+{  16,0x2e94,0,{0x75,0x36,0x25,0x75,0x37,0x24,0x90,0x79,0x74,0xe0,0x64,0x01,0x70,0x54,0xf0,0xf5} },
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+{  10,0x2fd4,0,{0x80,0x05,0xe4,0x90,0x79,0x33,0xf0,0x12,0x47,0xdf} },
+{   1,0x2fde,0,{0x22} },
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+{   1,0x2fff,0,{0x22} },
+{  16,0x3000,0,{0xe4,0xfe,0x90,0x79,0x20,0xe0,0xfd,0xb4,0x05,0x11,0x90,0x78,0x25,0x74,0x01,0xf0} },
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+{  16,0x30c0,0,{0x90,0x00,0x03,0x12,0x0c,0x5d,0xfd,0xcc,0xee,0xcc,0x0e,0x74,0x00,0x2c,0xf5,0x82} },
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+{  16,0x30f0,0,{0x26,0xe4,0x75,0xf0,0x0b,0x12,0x0c,0xf4,0x0f,0x80,0xb4,0x90,0x7f,0xb5,0xee,0xf0} },
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+{  16,0x31b0,0,{0x46,0x90,0x78,0x25,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x09,0x12} },
+{  16,0x31c0,0,{0x0c,0x5d,0xfd,0xcc,0xee,0xcc,0x0e,0x74,0x00,0x2c,0xf5,0x82,0xe4,0x34,0x7f,0xf5} },
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+{  16,0x31f0,0,{0x0b,0x12,0x0c,0xf4,0x0f,0x80,0xb4,0x90,0x7f,0xb5,0xee,0xf0,0x22,0x90,0x7f,0xb4} },
+{  12,0x3200,0,{0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x320c,0,{0x22} },
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+{  16,0x321d,0,{0xf0,0x74,0x01,0x12,0x0c,0x8a,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0} },
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+{  16,0x327d,0,{0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x02,0x12,0x0c,0x8a,0x90,0x78} },
+{  16,0x328d,0,{0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x02,0x12,0x0c} },
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+{  16,0x32ad,0,{0x0c,0xf4,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x01,0x12} },
+{  16,0x32bd,0,{0x0c,0x8a,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01} },
+{  16,0x32cd,0,{0x74,0x03,0x12,0x0c,0x9c,0x90,0x00,0x02,0xe4,0x12,0x0c,0x9c,0x90,0x78,0x01,0xe4} },
+{  16,0x32dd,0,{0x75,0xf0,0x03,0x12,0x0c,0xf4,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0} },
+{  16,0x32ed,0,{0xf9,0x74,0x10,0x12,0x0c,0x8a,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0} },
+{  16,0x32fd,0,{0xf9,0x90,0x00,0x01,0x74,0x06,0x12,0x0c,0x9c,0x90,0x00,0x02,0xe4,0x12,0x0c,0x9c} },
+{  16,0x330d,0,{0x90,0x78,0x01,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x90,0x78,0x00,0xe0,0xfb,0xa3} },
+{  16,0x331d,0,{0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x02,0x12,0x0c,0x8a,0x90,0x78,0x00,0xe0,0xfb,0xa3} },
+{  16,0x332d,0,{0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x04,0x12,0x0c,0x9c,0x90,0x00,0x02} },
+{  16,0x333d,0,{0xe4,0x12,0x0c,0x9c,0x90,0x78,0x01,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x90,0x78} },
+{  16,0x334d,0,{0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x02,0x12,0x0c,0x8a,0x90,0x78} },
+{  16,0x335d,0,{0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x04,0x12,0x0c} },
+{  16,0x336d,0,{0x9c,0x90,0x00,0x02,0x74,0x04,0x12,0x0c,0x9c,0x90,0x78,0x01,0xe4,0x75,0xf0,0x03} },
+{  16,0x337d,0,{0x12,0x0c,0xf4,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x02} },
+{  16,0x338d,0,{0x12,0x0c,0x8a,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00} },
+{  16,0x339d,0,{0x01,0x74,0x03,0x12,0x0c,0x9c,0x90,0x00,0x02,0x74,0x04,0x12,0x0c,0x9c,0x90,0x78} },
+{  16,0x33ad,0,{0x01,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa} },
+{  16,0x33bd,0,{0xa3,0xe0,0xf9,0x74,0x02,0x12,0x0c,0x8a,0x90,0x78,0x00,0xe0,0xfb,0xa3,0xe0,0xfa} },
+{  16,0x33cd,0,{0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x02,0x12,0x0c,0x9c,0x90,0x00,0x02,0x74,0x04} },
+{  16,0x33dd,0,{0x12,0x0c,0x9c,0x90,0x78,0x01,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x90,0x78,0x00} },
+{  16,0x33ed,0,{0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x02,0x12,0x0c,0x8a,0x90,0x78,0x00} },
+{  16,0x33fd,0,{0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x01,0x12,0x0c,0x9c} },
+{   8,0x340d,0,{0x90,0x00,0x02,0x74,0x04,0x12,0x0c,0x9c} },
+{   1,0x3415,0,{0x22} },
+{  16,0x3416,0,{0xe4,0xfe,0x90,0x79,0x20,0xe0,0xfd,0xb4,0x05,0x11,0x90,0x78,0x1f,0x74,0x01,0xf0} },
+{  16,0x3426,0,{0xa3,0x74,0x78,0xf0,0xa3,0x74,0xb2,0xf0,0x75,0x35,0x07,0xed,0xb4,0x06,0x11,0x90} },
+{  16,0x3436,0,{0x78,0x1f,0x74,0x01,0xf0,0xa3,0x74,0x78,0xf0,0xa3,0x74,0xff,0xf0,0x75,0x35,0x03} },
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+{   7,0x3606,0,{0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x360d,0,{0x22} },
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+{  16,0x37a2,0,{0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0xe8,0xc0,0xe0,0xe9,0xc0,0xe0} },
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+{   6,0x37fa,0,{0x53,0x91,0xbf,0xd2,0x26,0x32} },
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+{  12,0x3980,0,{0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x398c,0,{0x22} },
+{  16,0x398d,0,{0xa2,0xaf,0xe4,0x33,0xf5,0x12,0xe4,0x90,0x79,0x83,0xf0,0x12,0x2f,0xdf,0x90,0x7f} },
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+{  16,0x39dd,0,{0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x79,0x66,0xf0,0xa3,0xf0,0x90,0x79,0x7b,0xf0,0xa3} },
+{  16,0x39ed,0,{0xf0,0x90,0x79,0x84,0xf0,0x90,0x79,0x7d,0xf0,0x90,0x79,0x75,0xf0,0xa3,0xf0,0xa3} },
+{  16,0x39fd,0,{0xf0,0xc2,0x23,0xc2,0x24,0xc2,0x25,0xc2,0x26,0xc2,0x20,0x90,0x7f,0x9b,0xe0,0xf5} },
+{  16,0x3a0d,0,{0x0a,0x54,0x20,0xf5,0x0a,0x70,0x06,0x90,0x79,0x7e,0xf0,0x80,0x06,0x90,0x79,0x7e} },
+{  16,0x3a1d,0,{0x74,0x01,0xf0,0x90,0x7f,0x9b,0xe0,0xf5,0x0a,0x54,0x02,0xf5,0x0a,0x70,0x06,0x90} },
+{  16,0x3a2d,0,{0x79,0x7f,0xf0,0x80,0x06,0x90,0x79,0x7f,0x74,0x01,0xf0,0x90,0x79,0x78,0x74,0x02} },
+{  16,0x3a3d,0,{0xf0,0x90,0x79,0x84,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79,0x7f,0xe0,0xb4,0x01,0x09} },
+{  16,0x3a4d,0,{0x90,0x79,0x79,0xe0,0x54,0xfe,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x44,0x01,0xf0} },
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+{  16,0x3a6d,0,{0xf0,0x90,0x79,0x7c,0xe0,0x90,0x79,0x79,0xf0,0x90,0x79,0x7e,0xe0,0xb4,0x01,0x09} },
+{  16,0x3a7d,0,{0x90,0x79,0x79,0xe0,0x44,0x04,0xf0,0x80,0x07,0x90,0x79,0x79,0xe0,0x54,0xfb,0xf0} },
+{  16,0x3a8d,0,{0x90,0x79,0x79,0xe0,0x90,0x79,0x7c,0xf0,0x12,0x0b,0xa2,0xe4,0x90,0x79,0x78,0xf0} },
+{  16,0x3a9d,0,{0xa3,0x04,0xf0,0xe4,0x90,0x79,0x88,0xf0,0x12,0x0b,0xa2,0x90,0x7f,0xfc,0x74,0xdd} },
+{  16,0x3aad,0,{0xf0,0x90,0x7f,0xff,0x74,0xff,0xf0,0x90,0x79,0x78,0x74,0x01,0xf0,0xa3,0xf0,0x12} },
+{  16,0x3abd,0,{0x0b,0xa2,0xe4,0x90,0x79,0x7a,0xf0,0x90,0x79,0x83,0x04,0xf0,0x12,0x2f,0xdf,0xe4} },
+{  16,0x3acd,0,{0x90,0x79,0x30,0xf0,0x90,0x79,0x85,0xf0,0xa3,0xf0,0xa3,0xf0,0x12,0x2e,0x94,0x90} },
+{  16,0x3add,0,{0x79,0x2d,0x74,0x02,0xf0,0x90,0x79,0x88,0x14,0xf0,0xc2,0x2f,0xe4,0x90,0x79,0x68} },
+{  16,0x3aed,0,{0xf0,0x90,0x79,0x8a,0xf0,0x90,0x79,0x6a,0xf0,0xa3,0xf0,0x75,0x13,0x08,0x75,0x14} },
+{  16,0x3afd,0,{0x08,0xf5,0x16,0xf5,0x15,0xf5,0x17,0x90,0x79,0x8c,0xf0,0x90,0x79,0x8b,0xf0,0x22} },
+{  16,0x3b0d,0,{0x7b,0x01,0x7a,0x78,0x79,0x58,0x90,0x78,0x03,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9} },
+{  16,0x3b1d,0,{0xf0,0x74,0x40,0x12,0x0c,0x8a,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0} },
+{  16,0x3b2d,0,{0xf9,0x90,0x00,0x01,0x74,0x0a,0x12,0x0c,0x9c,0x90,0x00,0x02,0x12,0x0d,0xf6,0x00} },
+{  16,0x3b3d,0,{0x00,0xbb,0x80,0x90,0x00,0x06,0x12,0x0d,0xf6,0x00,0x00,0xac,0x44,0x90,0x00,0x0a} },
+{  16,0x3b4d,0,{0x12,0x0d,0xf6,0x00,0x01,0x77,0x00,0x90,0x78,0x04,0xe4,0x75,0xf0,0x0f,0x12,0x0c} },
+{  16,0x3b5d,0,{0xf4,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x40,0x12,0x0c} },
+{  16,0x3b6d,0,{0x8a,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74} },
+{  16,0x3b7d,0,{0x8c,0x12,0x0c,0x9c,0x90,0x00,0x02,0x12,0x0d,0xf6,0x00,0x00,0xbb,0x80,0x90,0x00} },
+{  16,0x3b8d,0,{0x06,0x12,0x0d,0xf6,0x00,0x00,0xac,0x44,0x90,0x00,0x0a,0x12,0x0d,0xf6,0x00,0x01} },
+{  16,0x3b9d,0,{0x77,0x00,0x90,0x78,0x04,0xe4,0x75,0xf0,0x0f,0x12,0x0c,0xf4,0x90,0x78,0x03,0xe0} },
+{  16,0x3bad,0,{0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x40,0x12,0x0c,0x8a,0x90,0x78,0x03,0xe0} },
+{  16,0x3bbd,0,{0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x8f,0x12,0x0c,0x9c,0x90} },
+{  16,0x3bcd,0,{0x78,0x04,0xe4,0x75,0xf0,0x0f,0x12,0x0c,0xf4,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0} },
+{  16,0x3bdd,0,{0xfa,0xa3,0xe0,0xf9,0x74,0x41,0x12,0x0c,0x8a,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0} },
+{  16,0x3bed,0,{0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x74,0x84,0x12,0x0c,0x9c,0x90,0x78,0x04,0xe4} },
+{  16,0x3bfd,0,{0x75,0xf0,0x0f,0x12,0x0c,0xf4,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0} },
+{  16,0x3c0d,0,{0xf9,0x74,0x61,0x12,0x0c,0x8a,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0} },
+{  16,0x3c1d,0,{0xf9,0x90,0x00,0x01,0x74,0x81,0x12,0x0c,0x9c,0x90,0x78,0x04,0xe4,0x75,0xf0,0x0f} },
+{  16,0x3c2d,0,{0x12,0x0c,0xf4,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x74,0x61} },
+{  16,0x3c3d,0,{0x12,0x0c,0x8a,0x90,0x78,0x03,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00} },
+{   6,0x3c4d,0,{0x01,0x74,0x01,0x12,0x0c,0x9c} },
+{   1,0x3c53,0,{0x22} },
+{  16,0x3c54,0,{0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0xe8,0xc0,0xe0,0xe9,0xc0,0xe0} },
+{  16,0x3c64,0,{0xea,0xc0,0xe0,0xeb,0xc0,0xe0,0xec,0xc0,0xe0,0xed,0xc0,0xe0,0xee,0xc0,0xe0,0xef} },
+{   2,0x3c74,0,{0xc0,0xe0} },
+{  16,0x3c76,0,{0x90,0x7f,0xa2,0xe0,0xf5,0x0b,0x90,0x7f,0x74,0xe0,0x90,0x79,0x70,0xf0,0x90,0x7f} },
+{  16,0x3c86,0,{0x75,0xe0,0x90,0x79,0x71,0xf0,0x90,0x79,0x83,0xe0,0xff,0xfe,0x54,0x02,0xfe,0x70} },
+{  16,0x3c96,0,{0x0d,0xef,0x44,0x02,0xf0,0x12,0x2f,0xdf,0x90,0x79,0x74,0x74,0x01,0xf0,0xe5,0x0b} },
+{  16,0x3ca6,0,{0x20,0xe2,0x28,0x90,0x79,0x70,0xe0,0xfe,0xa3,0xe0,0x7c,0x00,0x24,0x00,0xf5,0x11} },
+{  16,0x3cb6,0,{0xec,0x3e,0xf5,0x10,0x90,0x79,0x82,0xe0,0xfd,0xae,0x10,0xaf,0x11,0x12,0x0c,0xbe} },
+{  16,0x3cc6,0,{0x90,0x79,0x70,0xef,0xf0,0x90,0x79,0x89,0x74,0x01,0xf0,0x12,0x48,0x43,0x12,0x48} },
+{  16,0x3cd6,0,{0x76,0x90,0x79,0x89,0xe0,0x64,0x01,0x70,0x32,0x12,0x41,0x08,0x90,0x79,0x89,0xe4} },
+{  16,0x3ce6,0,{0xf0,0x90,0x7f,0x98,0xe0,0x44,0x40,0xf0,0x90,0x7f,0x9e,0xe0,0x44,0x40,0xf0,0x90} },
+{  16,0x3cf6,0,{0x7f,0x95,0x74,0x80,0xf0,0x75,0xe8,0x01,0x12,0x09,0x32,0x75,0xe8,0x0d,0x90,0x7f} },
+{  16,0x3d06,0,{0x95,0x74,0xc0,0xf0,0x75,0xe8,0x0d,0xd2,0x20,0x80,0x05,0x75,0xe8,0x01,0xc2,0x20} },
+{  16,0x3d16,0,{0x20,0x20,0x2b,0x90,0x79,0x2d,0xe0,0xff,0xb4,0x01,0x09,0x75,0x0c,0x67,0x75,0x0d} },
+{  16,0x3d26,0,{0x06,0x75,0x0e,0x0b,0xef,0xb4,0x02,0x09,0x75,0x0c,0x00,0x75,0x0d,0x00,0x75,0x0e} },
+{  16,0x3d36,0,{0x0c,0xef,0xb4,0x03,0x09,0x75,0x0c,0x00,0x75,0x0d,0x00,0x75,0x0e,0x18,0x75,0xca} },
+{  16,0x3d46,0,{0x6f,0x75,0xcb,0xfe,0xd2,0xca,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x02,0xf0,0xf0} },
+{  16,0x3d56,0,{0xd0,0xe0,0xff,0xd0,0xe0,0xfe,0xd0,0xe0,0xfd,0xd0,0xe0,0xfc,0xd0,0xe0,0xfb,0xd0} },
+{  16,0x3d66,0,{0xe0,0xfa,0xd0,0xe0,0xf9,0xd0,0xe0,0xf8,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0} },
+{   3,0x3d76,0,{0xd0,0xe0,0x32} },
+{  16,0x3d79,0,{0x75,0x33,0x25,0x75,0x34,0x24,0x90,0x79,0x5c,0x74,0x01,0xf0,0xa3,0x74,0x78,0xf0} },
+{  16,0x3d89,0,{0xa3,0x74,0xb2,0xf0,0x20,0x2f,0x02,0xc1,0x17,0xe4,0xf5,0x35,0x75,0x22,0x01,0x90} },
+{  16,0x3d99,0,{0x79,0x5c,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x04,0x12,0x0c,0x5d} },
+{  16,0x3da9,0,{0xf5,0x36,0x75,0x35,0x06,0x74,0x42,0x25,0x35,0xf5,0x82,0xe4,0x34,0x79,0xf5,0x83} },
+{  16,0x3db9,0,{0xe5,0x36,0xf0,0x05,0x35,0xe5,0x35,0xb4,0x0c,0xeb,0xe5,0x35,0xc3,0x94,0x0d,0x40} },
+{  16,0x3dc9,0,{0x02,0xc1,0x98,0xe5,0x22,0x64,0x01,0x60,0x02,0xc1,0x98,0x90,0x7f,0xa5,0xe0,0x44} },
+{  16,0x3dd9,0,{0x80,0xf0,0x90,0x7f,0xa6,0xe5,0x33,0xf0,0x12,0x46,0xc0,0x74,0x4f,0x25,0x35,0xf5} },
+{  16,0x3de9,0,{0x82,0xe4,0x34,0x79,0xf5,0x83,0xe0,0x90,0x7f,0xa6,0xf0,0x12,0x46,0xc0,0x74,0x42} },
+{  16,0x3df9,0,{0x25,0x35,0xf5,0x82,0xe4,0x34,0x79,0xf5,0x83,0xe0,0x90,0x7f,0xa6,0xf0,0x12,0x46} },
+{  16,0x3e09,0,{0xc0,0x90,0x7f,0xa5,0x74,0x40,0xf0,0x12,0x0a,0xcd,0x05,0x35,0x80,0xac,0xe4,0xf5} },
+{  16,0x3e19,0,{0x35,0x75,0x22,0x01,0x90,0x79,0x5c,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90} },
+{  16,0x3e29,0,{0x00,0x04,0x12,0x0c,0x5d,0xf5,0x36,0x75,0x35,0x06,0x74,0x35,0x25,0x35,0xf5,0x82} },
+{  16,0x3e39,0,{0xe4,0x34,0x79,0xf5,0x83,0xe5,0x36,0xf0,0x05,0x35,0xe5,0x35,0xb4,0x0c,0xeb,0xe5} },
+{  16,0x3e49,0,{0x35,0xc3,0x94,0x0d,0x50,0x49,0xe5,0x22,0x64,0x01,0x70,0x43,0x90,0x7f,0xa5,0xe0} },
+{  16,0x3e59,0,{0x44,0x80,0xf0,0x90,0x7f,0xa6,0xe5,0x33,0xf0,0x12,0x46,0xc0,0x74,0x4f,0x25,0x35} },
+{  16,0x3e69,0,{0xf5,0x82,0xe4,0x34,0x79,0xf5,0x83,0xe0,0x90,0x7f,0xa6,0xf0,0x12,0x46,0xc0,0x74} },
+{  16,0x3e79,0,{0x35,0x25,0x35,0xf5,0x82,0xe4,0x34,0x79,0xf5,0x83,0xe0,0x90,0x7f,0xa6,0xf0,0x12} },
+{  15,0x3e89,0,{0x46,0xc0,0x90,0x7f,0xa5,0x74,0x40,0xf0,0x12,0x0a,0xcd,0x05,0x35,0x80,0xb0} },
+{   1,0x3e98,0,{0x22} },
+{  16,0x3e99,0,{0x90,0x78,0x09,0x74,0x01,0xf0,0xa3,0x74,0x78,0xf0,0xa3,0x74,0xb2,0xf0,0xe4,0xff} },
+{  16,0x3ea9,0,{0xfe,0x90,0x78,0x09,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0xef,0x12,0x0c,0x8a} },
+{  16,0x3eb9,0,{0x90,0x78,0x09,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0xe4,0x12} },
+{  16,0x3ec9,0,{0x0c,0x9c,0x90,0x00,0x02,0x74,0x15,0x12,0x0c,0x9c,0x90,0x00,0x03,0xe4,0x12,0x0c} },
+{  16,0x3ed9,0,{0x9c,0x90,0x00,0x04,0x74,0xff,0x12,0x0c,0x9c,0x90,0x00,0x05,0xe4,0x12,0x0c,0x9c} },
+{  16,0x3ee9,0,{0x90,0x00,0x06,0x74,0xc3,0x12,0x0c,0x9c,0x90,0x00,0x07,0xe4,0x12,0x0c,0x9c,0x90} },
+{  16,0x3ef9,0,{0x00,0x08,0xe4,0x12,0x0c,0x9c,0x90,0x00,0x09,0xe4,0x12,0x0c,0x9c,0x90,0x00,0x0a} },
+{  16,0x3f09,0,{0x74,0x01,0x12,0x0c,0x9c,0x90,0x78,0x0a,0xe4,0x75,0xf0,0x0b,0x12,0x0c,0xf4,0x0f} },
+{  16,0x3f19,0,{0x0e,0xbe,0x07,0x8d,0x90,0x78,0x09,0x74,0x01,0xf0,0xa3,0x74,0x78,0xf0,0xa3,0x74} },
+{  16,0x3f29,0,{0xff,0xf0,0xe4,0xff,0xfe,0x90,0x78,0x09,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9} },
+{  16,0x3f39,0,{0xef,0x12,0x0c,0x8a,0x90,0x78,0x09,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90} },
+{  16,0x3f49,0,{0x00,0x01,0xe4,0x12,0x0c,0x9c,0x90,0x00,0x02,0x74,0x15,0x12,0x0c,0x9c,0x90,0x00} },
+{  16,0x3f59,0,{0x03,0xe4,0x12,0x0c,0x9c,0x90,0x00,0x04,0x74,0x80,0x12,0x0c,0x9c,0x90,0x00,0x05} },
+{  16,0x3f69,0,{0xe4,0x12,0x0c,0x9c,0x90,0x00,0x06,0x74,0xc3,0x12,0x0c,0x9c,0x90,0x00,0x07,0xe4} },
+{  16,0x3f79,0,{0x12,0x0c,0x9c,0x90,0x00,0x08,0xe4,0x12,0x0c,0x9c,0x90,0x00,0x09,0xe4,0x12,0x0c} },
+{  16,0x3f89,0,{0x9c,0x90,0x00,0x0a,0x74,0x01,0x12,0x0c,0x9c,0x90,0x78,0x0a,0xe4,0x75,0xf0,0x0b} },
+{   8,0x3f99,0,{0x12,0x0c,0xf4,0x0f,0x0e,0xbe,0x03,0x8d} },
+{   1,0x3fa1,0,{0x22} },
+{  16,0x3fa2,0,{0xe4,0xfe,0x75,0x3d,0xff,0x75,0x3e,0x05,0x75,0x3f,0x12,0xab,0x3d,0xaa,0x3e,0xa9} },
+{  16,0x3fb2,0,{0x3f,0x90,0x00,0x01,0x12,0x0c,0x5d,0x64,0x02,0x70,0x2f,0xcd,0xee,0xcd,0x0e,0xed} },
+{  16,0x3fc2,0,{0x6f,0x70,0x01,0x22,0x90,0x00,0x02,0x12,0x0d,0x0a,0x85,0xf0,0x3b,0xf5,0x3c,0x62} },
+{  16,0x3fd2,0,{0x3b,0xe5,0x3b,0x62,0x3c,0xe5,0x3c,0x62,0x3b,0x29,0xfd,0xe5,0x3b,0x3a,0xc9,0xed} },
+{  16,0x3fe2,0,{0xc9,0x75,0x3d,0xff,0xf5,0x3e,0x89,0x3f,0x80,0xc1,0x7b,0x00,0x7a,0x00,0x79,0x00} },
+{   1,0x3ff2,0,{0x22} },
+{   9,0x3ff3,0,{0x53,0xd8,0xef,0x43,0xd8,0x20,0xc2,0x2d,0x32} },
+{   4,0x3ffc,0,{0x53,0x91,0xdf,0x32} },
+{  16,0x4000,0,{0x90,0x79,0x87,0xe0,0xb4,0x01,0x1d,0x90,0x79,0x85,0xe0,0xb4,0x01,0x03,0x12,0x42} },
+{  16,0x4010,0,{0xaa,0x90,0x79,0x86,0xe0,0xb4,0x01,0x03,0x12,0x18,0x00,0xe4,0x90,0x79,0x85,0xf0} },
+{  16,0x4020,0,{0xa3,0xf0,0xa3,0xf0,0x12,0x2e,0x94,0x90,0x7f,0x9b,0xe0,0xf5,0x0a,0x54,0x02,0xf5} },
+{  16,0x4030,0,{0x0a,0x70,0x04,0x90,0x79,0x7f,0xf0,0x90,0x7f,0x9b,0xe0,0xf5,0x0a,0x54,0x02,0xff} },
+{  16,0x4040,0,{0xf5,0x0a,0xbf,0x02,0x06,0x90,0x79,0x7f,0x74,0x01,0xf0,0x90,0x7f,0x9b,0xe0,0xf5} },
+{  16,0x4050,0,{0x0a,0x54,0x20,0xf5,0x0a,0x70,0x04,0x90,0x79,0x7e,0xf0,0x90,0x7f,0x9b,0xe0,0xf5} },
+{  16,0x4060,0,{0x0a,0x54,0x20,0xff,0xf5,0x0a,0xbf,0x20,0x06,0x90,0x79,0x7e,0x74,0x01,0xf0,0x90} },
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+{  16,0x4108,0,{0x90,0x79,0x2d,0xe0,0x64,0x01,0x70,0x35,0x90,0x79,0x70,0xe0,0xff,0xd3,0x94,0x2d} },
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+{  16,0x41fd,0,{0x7b,0x01,0x7a,0x78,0x79,0x4c,0x90,0x78,0x06,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9} },
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+{  11,0x434a,0,{0x12,0x1b,0x2a,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0} },
+{   1,0x4355,0,{0x22} },
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+{  16,0x44d6,0,{0x12,0x3f,0xa2,0xea,0x49,0x60,0x57,0x12,0x0c,0x44,0x7e,0x00,0x29,0xff,0xee,0x3a} },
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+{   4,0x4536,0,{0x7a,0x00,0x79,0x00} },
+{   1,0x453a,0,{0x22} },
+{  16,0x453b,0,{0xe4,0xff,0x7b,0x01,0x90,0x78,0x1c,0x04,0xf0,0xa3,0x74,0x78,0xf0,0xa3,0x74,0x4c} },
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+{   3,0x459b,0,{0x74,0x01,0xf0} },
+{   1,0x459e,0,{0x22} },
+{  14,0x459f,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0xee,0xc0,0xe0,0xef,0xc0,0xe0} },
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+{  16,0x45dd,0,{0xe4,0x34,0x79,0xf5,0x83,0xee,0xf0,0x0f,0x80,0xdb,0x53,0x91,0xef,0x90,0x7f,0xaa} },
+{   4,0x45ed,0,{0xe0,0x44,0x01,0xf0} },
+{  15,0x45f1,0,{0xd0,0xe0,0xff,0xd0,0xe0,0xfe,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
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+{  16,0x4610,0,{0xf0,0x90,0x78,0x19,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x02,0x12} },
+{  16,0x4620,0,{0x0c,0x5d,0xfe,0x90,0x7f,0xec,0xe0,0x6e,0x60,0x13,0xef,0xc3,0x94,0x04,0x50,0x0d} },
+{  16,0x4630,0,{0x90,0x78,0x1a,0xe4,0x75,0xf0,0x03,0x12,0x0c,0xf4,0x0f,0x80,0xd4,0xbf,0x04,0x08} },
+{  16,0x4640,0,{0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x78,0x19,0xe0,0xfb,0xa3,0xe0,0xfa} },
+{  16,0x4650,0,{0xa3,0xe0,0xf9,0x12,0x0c,0x44,0x90,0x7f,0x00,0xf0,0x90,0x7f,0xb5,0x74,0x01,0xf0} },
+{   1,0x4660,0,{0x22} },
+{  16,0x4661,0,{0x01,0x18,0x02,0x01,0x19,0x0a,0x01,0x1c,0x00,0xc1,0x28,0xc1,0x29,0x01,0x1f,0x01} },
+{  15,0x4671,0,{0x44,0x79,0x9f,0x00,0x00,0x00,0x00,0x41,0x79,0xa3,0x00,0x41,0x79,0xa4,0x00} },
+{   4,0x4680,0,{0x41,0x79,0x89,0x00} },
+{  16,0x4684,0,{0x01,0x22,0x01,0x41,0x79,0x31,0xff,0x41,0x79,0x34,0x00,0x4d,0x79,0x35,0x3f,0x3f} },
+{  16,0x4694,0,{0x00,0x08,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x15,0x4d,0x79,0x42,0x3f,0x3f} },
+{  16,0x46a4,0,{0x06,0x08,0x04,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x15,0x4d,0x79,0x4f,0x0a,0x0a} },
+{  11,0x46b4,0,{0x09,0x00,0x01,0x09,0x02,0x03,0x04,0x05,0x06,0x07,0x08} },
+{   1,0x46bf,0,{0x00} },
+{  16,0x46c0,0,{0x12,0x0a,0xcd,0x90,0x7f,0xa5,0xe0,0xf5,0x21,0xe5,0x21,0x54,0x01,0xf5,0x21,0x64} },
+{  16,0x46d0,0,{0x01,0x60,0x28,0xe5,0x22,0x64,0x01,0x70,0x22,0x90,0x7f,0xa5,0xe0,0xf5,0x21,0x54} },
+{  16,0x46e0,0,{0x02,0xf5,0x21,0x70,0x03,0x75,0x22,0x01,0x90,0x7f,0xa5,0xe0,0xf5,0x21,0x54,0x04} },
+{  12,0x46f0,0,{0xff,0xf5,0x21,0xbf,0x04,0xd3,0x75,0x22,0x01,0x80,0xce,0x22} },
+{   4,0x46fc,0,{0x53,0xd8,0xf7,0x32} },
+{  16,0x4700,0,{0x02,0x49,0xfa,0x00,0x02,0x3c,0x54,0x00,0x02,0x17,0xe4,0x00,0x02,0x4a,0x12,0x00} },
+{  16,0x4710,0,{0x02,0x37,0xa2,0x00,0x02,0x47,0xff,0x00,0x02,0x4a,0x41,0x00,0x02,0x45,0x9f,0x00} },
+{  16,0x4720,0,{0x02,0x49,0x8e,0x00,0x02,0x49,0xab,0x00,0x02,0x4a,0x58,0x00,0x02,0x4a,0x6f,0x00} },
+{  16,0x4730,0,{0x02,0x4a,0x86,0x00,0x02,0x4a,0x9d,0x00,0x02,0x4a,0xb4,0x00,0x02,0x4a,0xcb,0x00} },
+{  16,0x4740,0,{0x02,0x4a,0xe2,0x00,0x02,0x4a,0xf9,0x00,0x02,0x4b,0x10,0x00,0x02,0x4b,0x27,0x00} },
+{   8,0x4750,0,{0x02,0x4b,0x3e,0x00,0x02,0x4b,0x55,0x00} },
+{  16,0x4758,0,{0xe5,0x18,0x70,0x14,0x90,0x79,0x8c,0xe0,0x04,0xf0,0x90,0x79,0x8b,0xe0,0xc3,0x94} },
+{  16,0x4768,0,{0x00,0x40,0x15,0xe0,0x14,0xf0,0x80,0x10,0x90,0x79,0x8b,0xe0,0x04,0xf0,0xa3,0xe0} },
+{  16,0x4778,0,{0xc3,0x94,0x00,0x40,0x03,0xe0,0x14,0xf0,0x90,0x79,0x8b,0xe0,0xd3,0x94,0x14,0x40} },
+{  16,0x4788,0,{0x04,0xe4,0xf5,0x18,0xf0,0x90,0x79,0x8c,0xe0,0xd3,0x94,0x14,0x40,0x05,0x75,0x18} },
+{   4,0x4798,0,{0x01,0xe4,0xf0,0x22} },
+{  16,0x479c,0,{0x90,0x7f,0xd7,0xe0,0xf5,0x33,0x90,0x7f,0xec,0xe0,0xf5,0x09,0x14,0x60,0x11,0x14} },
+{  16,0x47ac,0,{0x60,0x1b,0x24,0x02,0x70,0x24,0x90,0x7f,0xea,0xe0,0x90,0x79,0x62,0xf0,0x80,0x21} },
+{  16,0x47bc,0,{0x90,0x7f,0xea,0xe0,0x90,0x79,0x63,0xf0,0x12,0x10,0x00,0x80,0x14,0x90,0x7f,0xea} },
+{  16,0x47cc,0,{0xe0,0x90,0x79,0x64,0xf0,0x12,0x28,0x01,0x80,0x07,0x90,0x7f,0xb4,0xe0,0x44,0x01} },
+{   2,0x47dc,0,{0xf0,0xd3} },
+{   1,0x47de,0,{0x22} },
+{  16,0x47df,0,{0x90,0x79,0x78,0x74,0x04,0xf0,0x90,0x79,0x33,0xe0,0x90,0x79,0x79,0xf0,0xa2,0xaf} },
+{  16,0x47ef,0,{0xe4,0x33,0xf5,0x12,0xc2,0xaf,0x12,0x0b,0xa2,0xe5,0x12,0x60,0x02,0xd2,0xaf,0x22} },
+{   1,0x47ff,0,{0x32} },
+{   2,0x4800,0,{0x8f,0x36} },
+{  16,0x4802,0,{0xe4,0xf5,0x37,0x75,0x38,0xff,0x75,0x39,0x07,0x75,0x3a,0x01,0xab,0x38,0xaa,0x39} },
+{  16,0x4812,0,{0xa9,0x3a,0x90,0x00,0x01,0x12,0x0c,0x5d,0xb4,0x03,0x1f,0xaf,0x37,0x05,0x37,0xef} },
+{  16,0x4822,0,{0x65,0x36,0x70,0x01,0x22,0x12,0x0c,0x44,0x7e,0x00,0x29,0xff,0xee,0x3a,0xc9,0xef} },
+{  16,0x4832,0,{0xc9,0x75,0x38,0xff,0xf5,0x39,0x89,0x3a,0x80,0xd2,0x7b,0x00,0x7a,0x00,0x79,0x00} },
+{   1,0x4842,0,{0x22} },
+{  16,0x4843,0,{0x30,0x26,0x2f,0xc2,0x26,0x90,0x79,0x2d,0xe0,0xff,0xb4,0x01,0x09,0xe4,0xf5,0x0c} },
+{  16,0x4853,0,{0x75,0x0d,0xf8,0x75,0x0e,0x0a,0xef,0xb4,0x02,0x09,0xe4,0xf5,0x0c,0x75,0x0d,0xf0} },
+{  16,0x4863,0,{0x75,0x0e,0x0b,0xef,0xb4,0x03,0x09,0xe4,0xf5,0x0c,0x75,0x0d,0xf8,0x75,0x0e,0x17} },
+{   3,0x4873,0,{0xd2,0x22,0x22} },
+{  16,0x4876,0,{0x30,0x25,0x2f,0xc2,0x25,0x90,0x79,0x2d,0xe0,0xff,0xb4,0x01,0x09,0x75,0x0c,0xc0} },
+{  16,0x4886,0,{0x75,0x0d,0x14,0x75,0x0e,0x0b,0xef,0xb4,0x02,0x09,0xe4,0xf5,0x0c,0x75,0x0d,0x10} },
+{  16,0x4896,0,{0x75,0x0e,0x0c,0xef,0xb4,0x03,0x09,0xe4,0xf5,0x0c,0x75,0x0d,0x18,0x75,0x0e,0x18} },
+{   3,0x48a6,0,{0xd2,0x22,0x22} },
+{  16,0x48a9,0,{0xe4,0xf5,0x32,0x12,0x0f,0x50,0x20,0x2e,0x10,0xe5,0x32,0xc3,0x94,0x02,0x50,0x09} },
+{  16,0x48b9,0,{0x05,0x32,0xd2,0x30,0x12,0x49,0x05,0x80,0xed,0x30,0x2e,0x05,0x12,0x14,0x57,0xc2} },
+{  15,0x48c9,0,{0x2e,0x30,0x2d,0x06,0x12,0x07,0x9a,0x12,0x48,0xd9,0x12,0x40,0x00,0x80,0xea} },
+{   1,0x48d8,0,{0x22} },
+{  16,0x48d9,0,{0x90,0x7f,0xd6,0xe0,0xf5,0x1d,0x54,0x80,0xf5,0x1d,0x64,0x80,0x70,0x1d,0xc2,0xaf} },
+{  16,0x48e9,0,{0xe0,0x44,0x80,0xf0,0xe0,0x44,0x01,0xf0,0x7f,0x0c,0x7e,0x00,0x12,0x4b,0x6c,0x90} },
+{  12,0x48f9,0,{0x7f,0xd6,0xe0,0x54,0xfe,0xf0,0x53,0x87,0xfe,0xd2,0xaf,0x22} },
+{  16,0x4905,0,{0x90,0x7f,0xd6,0xe0,0x54,0xfb,0xf0,0xe0,0x44,0x08,0xf0,0x30,0x30,0x04,0xe0,0x44} },
+{  16,0x4915,0,{0x02,0xf0,0x7f,0xdc,0x7e,0x05,0x12,0x4b,0x6c,0x90,0x7f,0xd6,0xe0,0x54,0xf7,0xf0} },
+{   5,0x4925,0,{0xe0,0x44,0x04,0xf0,0x22} },
+{  16,0x492a,0,{0x90,0x7f,0xeb,0xe0,0x14,0x70,0x14,0x90,0x7f,0xe9,0xe0,0x24,0x7f,0x70,0x04,0x12} },
+{  16,0x493a,0,{0x46,0x00,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44} },
+{   3,0x494a,0,{0x01,0xf0,0x22} },
+{  16,0x494d,0,{0x90,0x7f,0xeb,0xe0,0x14,0x70,0x13,0x90,0x7f,0xe9,0xe0,0x14,0x70,0x04,0x12,0x45} },
+{  16,0x495d,0,{0x3b,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x22,0x90,0x7f,0xb4,0xe0,0x44,0x01} },
+{   2,0x496d,0,{0xf0,0x22} },
+{  16,0x496f,0,{0xe4,0xff,0x74,0xe8,0x2f,0xf5,0x82,0xe4,0x34,0x7f,0xf5,0x83,0xe0,0xfe,0x74,0x96} },
+{  14,0x497f,0,{0x2f,0xf5,0x82,0xe4,0x34,0x79,0xf5,0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe4} },
+{   1,0x498d,0,{0x22} },
+{  16,0x498e,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x02,0xf0} },
+{  13,0x499e,0,{0x90,0x7f,0xb7,0x74,0x03,0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x49ab,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x02,0xf0} },
+{  13,0x49bb,0,{0x90,0x7f,0xc7,0x74,0x03,0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x49c8,0,{0x90,0x7f,0xd6,0xe0,0x30,0xe7,0x12,0xe0,0x44,0x01,0xf0,0x7f,0x14,0x7e,0x00,0x12} },
+{  10,0x49d8,0,{0x4b,0x6c,0x90,0x7f,0xd6,0xe0,0x54,0xfe,0xf0,0x22} },
+{  16,0x49e2,0,{0xe4,0xf5,0x1a,0x75,0x1b,0x01,0x90,0x79,0x91,0x04,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0} },
+{   8,0x49f2,0,{0xa3,0x74,0x0a,0xf0,0xe4,0xa3,0xf0,0x22} },
+{  16,0x49fa,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0xd2,0x2e,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x01} },
+{   8,0x4a0a,0,{0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4a12,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0xd2,0x2d,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x08} },
+{   8,0x4a22,0,{0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4a2a,0,{0x90,0x7f,0xea,0xe0,0xf5,0x08,0xe4,0x90,0x79,0x62,0xf0,0xa3,0xf0,0xa3,0xf0,0x90} },
+{   7,0x4a3a,0,{0x79,0x66,0xf0,0xa3,0xf0,0xd3,0x22} },
+{  16,0x4a41,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x01,0xf0} },
+{   7,0x4a51,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4a58,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x04,0xf0} },
+{   7,0x4a68,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4a6f,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x04,0xf0} },
+{   7,0x4a7f,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4a86,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x08,0xf0} },
+{   7,0x4a96,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4a9d,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x08,0xf0} },
+{   7,0x4aad,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4ab4,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x10,0xf0} },
+{   7,0x4ac4,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4acb,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x10,0xf0} },
+{   7,0x4adb,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4ae2,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x20,0xf0} },
+{   7,0x4af2,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4af9,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x20,0xf0} },
+{   7,0x4b09,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4b10,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x40,0xf0} },
+{   7,0x4b20,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4b27,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x40,0xf0} },
+{   7,0x4b37,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4b3e,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xa9,0xe0,0x44,0x80,0xf0} },
+{   7,0x4b4e,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4b55,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xaa,0xe0,0x44,0x80,0xf0} },
+{   7,0x4b65,0,{0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x4b6c,0,{0x8e,0x33,0x8f,0x34,0xe5,0x34,0x15,0x34,0xae,0x33,0x70,0x02,0x15,0x33,0x4e,0x60} },
+{   7,0x4b7c,0,{0x05,0x12,0x07,0x89,0x80,0xee,0x22} },
+{  15,0x4b83,0,{0x90,0x7f,0xea,0xe0,0xb4,0xff,0x04,0x12,0x30,0x00,0x22,0x12,0x36,0x0e,0x22} },
+{  14,0x4b92,0,{0xc0,0xe0,0xc2,0x8b,0xd2,0x24,0x30,0x23,0x02,0xc2,0x23,0xd0,0xe0,0x32} },
+{  14,0x4ba0,0,{0x90,0x7f,0x00,0xe5,0x08,0xf0,0x90,0x7f,0xb5,0x74,0x01,0xf0,0xd3,0x22} },
+{   9,0x4bae,0,{0x30,0x24,0x05,0xc2,0x24,0x75,0x18,0x01,0x22} },
+{   9,0x4bb7,0,{0x30,0x23,0x05,0xc2,0x23,0xe4,0xf5,0x18,0x22} },
+{   7,0x4bc0,0,{0x53,0xc0,0xfe,0x53,0xc0,0xfd,0x32} },
+{   6,0x4bc7,0,{0x53,0x91,0x7f,0xd2,0x25,0x32} },
+{   5,0x4bcd,0,{0xc2,0x89,0xd2,0x23,0x32} },
+{   3,0x4bd2,0,{0xc2,0x8d,0x32} },
+{   3,0x4bd5,0,{0xc2,0x8f,0x32} },
+{   2,0x4bd8,0,{0xd3,0x22} },
+{   2,0x4bda,0,{0xd3,0x22} },
+{   2,0x4bdc,0,{0xd3,0x22} },
+{   2,0x4bde,0,{0xd3,0x22} },
+{   2,0x4be0,0,{0xd3,0x22} },
+{   2,0x4be2,0,{0xd3,0x22} },
+{   2,0x4be4,0,{0xc3,0x22} },
+{   1,0x4be6,0,{0x22} },
+{   0,0x0000,1,{0 }}
+};
+/*
+VERSION=1.0.2.916
+DATE=12.02.2002
+*/
+/*
+ * This firmware is for the Emagic EMI 2|6 Audio Interface
+ *
+ * The firmware contained herein is Copyright (c) 1999-2002 Emagic
+ * as an unpublished work. This notice does not imply unrestricted
+ * or public access to this firmware which is a trade secret of Emagic,
+ * and which may not be reproduced, used, sold or transferred to
+ * any third party without Emagic's written consent. All Rights Reserved.
+ *
+ * This firmware may not be modified and may only be used with the
+ * Emagic EMI 2|6 Audio Interface. Distribution and/or Modification of
+ * any driver which includes this firmware, in whole or in part,
+ * requires the inclusion of this statement.
+ */
+INTEL_HEX_RECORD g_Loader[] = {
+{   3,0x0000,0,{0x02,0x03,0x1c} },
+{   3,0x0043,0,{0x02,0x04,0x00} },
+{  16,0x0100,0,{0x90,0x7f,0xe9,0xe0,0x24,0x5b,0x60,0x60,0x24,0x02,0x60,0x03,0x02,0x01,0xbe,0x90} },
+{  16,0x0110,0,{0x7f,0xea,0xe0,0x75,0x0a,0x00,0xf5,0x0b,0xa3,0xe0,0xfe,0xe4,0xee,0x42,0x0a,0x90} },
+{  16,0x0120,0,{0x7f,0xee,0xe0,0x75,0x15,0x00,0xf5,0x16,0xa3,0xe0,0xfe,0xe4,0xee,0x42,0x15,0xe5} },
+{  16,0x0130,0,{0x16,0x45,0x15,0x70,0x03,0x02,0x01,0xbe,0xe4,0x90,0x7f,0xc5,0xf0,0x90,0x7f,0xb4} },
+{  16,0x0140,0,{0xe0,0x20,0xe3,0xf9,0x90,0x7f,0xc5,0xe0,0xf5,0x0c,0x12,0x02,0x77,0xaf,0x0c,0x7e} },
+{  16,0x0150,0,{0x00,0xef,0x25,0x0b,0xf5,0x0b,0xee,0x35,0x0a,0xf5,0x0a,0xc3,0xe5,0x16,0x9f,0xf5} },
+{  16,0x0160,0,{0x16,0xe5,0x15,0x9e,0xf5,0x15,0x80,0xc7,0x90,0x7f,0xea,0xe0,0x75,0x0a,0x00,0xf5} },
+{  16,0x0170,0,{0x0b,0xa3,0xe0,0xfe,0xe4,0xee,0x42,0x0a,0x90,0x7f,0xee,0xe0,0x75,0x15,0x00,0xf5} },
+{  16,0x0180,0,{0x16,0xa3,0xe0,0xfe,0xe4,0xee,0x42,0x15,0xe5,0x16,0x45,0x15,0x60,0x30,0xe4,0x90} },
+{  16,0x0190,0,{0x7f,0xc5,0xf0,0x90,0x7f,0xb4,0xe0,0x20,0xe3,0xf9,0x90,0x7f,0xc5,0xe0,0xf5,0x0c} },
+{  16,0x01a0,0,{0x12,0x02,0x8f,0xaf,0x0c,0x7e,0x00,0xef,0x25,0x0b,0xf5,0x0b,0xee,0x35,0x0a,0xf5} },
+{  15,0x01b0,0,{0x0a,0xc3,0xe5,0x16,0x9f,0xf5,0x16,0xe5,0x15,0x9e,0xf5,0x15,0x80,0xca,0xc3} },
+{   1,0x01bf,0,{0x22} },
+{  16,0x01c0,0,{0xc2,0x20,0xd2,0xe8,0x43,0xd8,0x20,0x90,0x7f,0xab,0x74,0xff,0xf0,0x90,0x7f,0xa9} },
+{  16,0x01d0,0,{0xf0,0x90,0x7f,0xaa,0xf0,0x53,0x91,0xef,0x90,0x7f,0x95,0xe0,0x44,0xc0,0xf0,0x90} },
+{  16,0x01e0,0,{0x7f,0x98,0xe0,0x44,0xc0,0xf0,0x90,0x7f,0x9e,0xe0,0x44,0xc0,0xf0,0xe4,0x90,0x7f} },
+{  16,0x01f0,0,{0x94,0xf0,0x90,0x7f,0x9d,0xe0,0x44,0x0f,0xf0,0x90,0x7f,0x97,0xe0,0x54,0xf0,0xf0} },
+{  16,0x0200,0,{0x90,0x7f,0xaf,0xe0,0x44,0x01,0xf0,0x90,0x7f,0xae,0xe0,0x44,0x0d,0xf0,0xd2,0xaf} },
+{  16,0x0210,0,{0x90,0x7f,0x97,0xe0,0x54,0xf0,0xf0,0x20,0x20,0x42,0x75,0x14,0x00,0x75,0x13,0x00} },
+{  16,0x0220,0,{0x75,0x12,0x00,0x75,0x11,0x00,0x7f,0x48,0x7e,0x92,0x7d,0x00,0x7c,0x00,0xab,0x14} },
+{  16,0x0230,0,{0xaa,0x13,0xa9,0x12,0xa8,0x11,0xc3,0x12,0x04,0x9a,0x50,0xdb,0x20,0x20,0xd8,0x7a} },
+{  16,0x0240,0,{0x00,0x79,0x00,0x78,0x00,0xe5,0x14,0x24,0x01,0xf5,0x14,0xea,0x35,0x13,0xf5,0x13} },
+{  16,0x0250,0,{0xe9,0x35,0x12,0xf5,0x12,0xe8,0x35,0x11,0xf5,0x11,0x80,0xca,0x30,0x20,0xfd,0x12} },
+{  16,0x0260,0,{0x01,0x00,0x50,0x07,0x90,0x7f,0xb4,0xe0,0x44,0x01,0xf0,0x90,0x7f,0xb4,0xe0,0x44} },
+{   6,0x0270,0,{0x02,0xf0,0xc2,0x20,0x80,0xe6} },
+{   1,0x0276,0,{0x22} },
+{  16,0x0277,0,{0xe5,0x0c,0xff,0xe5,0x0b,0xf5,0x82,0xe5,0x0a,0xf5,0x83,0x75,0x92,0x7e,0x74,0xc0} },
+{   8,0x0287,0,{0xf8,0xe2,0x08,0xf0,0xa3,0xdf,0xfa,0x22} },
+{  16,0x028f,0,{0x90,0x7f,0x96,0x85,0x83,0x92,0xa8,0x82,0x79,0x02,0x90,0x00,0x00,0xe0,0xb4,0x00} },
+{  16,0x029f,0,{0x37,0x74,0x01,0xf0,0x90,0x7f,0x93,0xe0,0x54,0xfc,0xf0,0x90,0x7f,0x96,0xe0,0x54} },
+{  16,0x02af,0,{0xfc,0xf0,0x90,0x7f,0x9c,0xe0,0x44,0x03,0xf0,0x90,0x7f,0x94,0xe0,0x54,0x7f,0xf0} },
+{  16,0x02bf,0,{0x90,0x7f,0x97,0xe0,0x44,0x80,0xf0,0x90,0x7f,0x9d,0xe0,0x44,0x80,0xf0,0x90,0x7f} },
+{  16,0x02cf,0,{0x97,0xe0,0x54,0x7f,0xf0,0x44,0x80,0xf0,0xe5,0x0c,0xff,0x90,0x7e,0xc0,0xe0,0xf5} },
+{  16,0x02df,0,{0x28,0xe4,0xa2,0x47,0x33,0xf2,0x69,0xf2,0xe4,0xa2,0x46,0x33,0xf2,0x69,0xf2,0xe4} },
+{  16,0x02ef,0,{0xa2,0x45,0x33,0xf2,0x69,0xf2,0xe4,0xa2,0x44,0x33,0xf2,0x69,0xf2,0xe4,0xa2,0x43} },
+{  16,0x02ff,0,{0x33,0xf2,0x69,0xf2,0xe4,0xa2,0x42,0x33,0xf2,0x69,0xf2,0xe4,0xa2,0x41,0x33,0xf2} },
+{  13,0x030f,0,{0x69,0xf2,0xe4,0xa2,0x40,0x33,0xf2,0x69,0xf2,0xa3,0xdf,0xc2,0x22} },
+{  12,0x031c,0,{0x78,0x7f,0xe4,0xf6,0xd8,0xfd,0x75,0x81,0x29,0x02,0x03,0x63} },
+{  16,0x0328,0,{0x02,0x01,0xc0,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2} },
+{  16,0x0338,0,{0x08,0xdf,0xf4,0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33} },
+{  16,0x0348,0,{0xc4,0x54,0x0f,0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf} },
+{  16,0x0358,0,{0xe4,0x80,0x0b,0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x04,0x84,0xe4,0x7e} },
+{  16,0x0368,0,{0x01,0x93,0x60,0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93} },
+{  16,0x0378,0,{0xa3,0x60,0x01,0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3} },
+{  16,0x0388,0,{0xfa,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca} },
+{  16,0x0398,0,{0xf0,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe} },
+{  16,0x03a8,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x90,0x7f,0xc4,0xe4,0xf0,0x53,0x91,0xef,0x90,0x7f} },
+{  11,0x03b8,0,{0xab,0x74,0x04,0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x03c3,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0xd2,0x20,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x01} },
+{   8,0x03d3,0,{0xf0,0xd0,0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x03db,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x02,0xf0,0xd0} },
+{   6,0x03eb,0,{0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{   1,0x03f1,0,{0x32} },
+{   1,0x03f2,0,{0x32} },
+{   1,0x03f3,0,{0x32} },
+{   1,0x03f4,0,{0x32} },
+{   1,0x03f5,0,{0x32} },
+{   1,0x03f6,0,{0x32} },
+{   1,0x03f7,0,{0x32} },
+{   1,0x03f8,0,{0x32} },
+{   1,0x03f9,0,{0x32} },
+{   1,0x03fa,0,{0x32} },
+{   1,0x03fb,0,{0x32} },
+{   1,0x03fc,0,{0x32} },
+{   1,0x03fd,0,{0x32} },
+{   1,0x03fe,0,{0x32} },
+{   1,0x03ff,0,{0x32} },
+{  16,0x0400,0,{0x02,0x03,0xc3,0x00,0x02,0x03,0xdb,0x00,0x02,0x03,0xa8,0x00,0x02,0x04,0x6e,0x00} },
+{  16,0x0410,0,{0x02,0x04,0x58,0x00,0x02,0x03,0xf1,0x00,0x02,0x03,0xf2,0x00,0x02,0x03,0xf3,0x00} },
+{  16,0x0420,0,{0x02,0x03,0xf4,0x00,0x02,0x03,0xf5,0x00,0x02,0x03,0xf6,0x00,0x02,0x03,0xf7,0x00} },
+{  16,0x0430,0,{0x02,0x03,0xf8,0x00,0x02,0x03,0xf9,0x00,0x02,0x03,0xfa,0x00,0x02,0x03,0xfb,0x00} },
+{  16,0x0440,0,{0x02,0x03,0xfc,0x00,0x02,0x03,0xfd,0x00,0x02,0x03,0xfe,0x00,0x02,0x03,0xff,0x00} },
+{   8,0x0450,0,{0x02,0x04,0xab,0x00,0x02,0x04,0xac,0x00} },
+{  16,0x0458,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x10,0xf0,0xd0} },
+{   6,0x0468,0,{0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x046e,0,{0xc0,0xe0,0xc0,0x83,0xc0,0x82,0x53,0x91,0xef,0x90,0x7f,0xab,0x74,0x08,0xf0,0xd0} },
+{   6,0x047e,0,{0x82,0xd0,0x83,0xd0,0xe0,0x32} },
+{  16,0x0484,0,{0x02,0x0a,0x00,0x0f,0x01,0x0c,0x11,0x04,0x0d,0x00,0x00,0x00,0x00,0x41,0x00,0x00} },
+{   1,0x0494,0,{0x00} },
+{   4,0x0495,0,{0x02,0x17,0x00,0x00} },
+{   1,0x0499,0,{0x00} },
+{  16,0x049a,0,{0xeb,0x9f,0xf5,0xf0,0xea,0x9e,0x42,0xf0,0xe9,0x9d,0x42,0xf0,0xe8,0x9c,0x45,0xf0} },
+{   1,0x04aa,0,{0x22} },
+{   1,0x04ab,0,{0x32} },
+{   1,0x04ac,0,{0x32} },
+{  16,0x1100,0,{0x12,0x01,0x10,0x01,0x00,0x00,0x00,0x40,0x6a,0x08,0x01,0x01,0x00,0x01,0x01,0x02} },
+{  16,0x1110,0,{0x00,0x01,0x09,0x02,0x20,0x00,0x01,0x01,0x03,0xa0,0x00,0x09,0x04,0x00,0x00,0x02} },
+{  16,0x1120,0,{0xff,0x00,0x00,0x04,0x07,0x05,0x82,0x02,0x40,0x00,0x00,0x07,0x05,0x02,0x02,0x40} },
+{  16,0x1130,0,{0x00,0x00,0x04,0x03,0x09,0x04,0x26,0x03,0x41,0x00,0x6e,0x00,0x63,0x00,0x68,0x00} },
+{  16,0x1140,0,{0x6f,0x00,0x72,0x00,0x20,0x00,0x43,0x00,0x68,0x00,0x69,0x00,0x70,0x00,0x73,0x00} },
+{  16,0x1150,0,{0x2c,0x00,0x20,0x00,0x49,0x00,0x6e,0x00,0x63,0x00,0x2e,0x00,0x28,0x03,0x46,0x00} },
+{  16,0x1160,0,{0x69,0x00,0x72,0x00,0x6d,0x00,0x77,0x00,0x61,0x00,0x72,0x00,0x65,0x00,0x20,0x00} },
+{  16,0x1170,0,{0x46,0x00,0x72,0x00,0x61,0x00,0x6d,0x00,0x65,0x00,0x57,0x00,0x6f,0x00,0x72,0x00} },
+{  16,0x1180,0,{0x6b,0x00,0x73,0x00,0x2a,0x03,0x43,0x00,0x6f,0x00,0x6e,0x00,0x66,0x00,0x69,0x00} },
+{  16,0x1190,0,{0x67,0x00,0x75,0x00,0x72,0x00,0x61,0x00,0x74,0x00,0x69,0x00,0x6f,0x00,0x6e,0x00} },
+{  16,0x11a0,0,{0x20,0x00,0x53,0x00,0x74,0x00,0x72,0x00,0x69,0x00,0x6e,0x00,0x67,0x00,0x22,0x03} },
+{  16,0x11b0,0,{0x49,0x00,0x6e,0x00,0x74,0x00,0x65,0x00,0x72,0x00,0x66,0x00,0x61,0x00,0x63,0x00} },
+{  16,0x11c0,0,{0x65,0x00,0x20,0x00,0x53,0x00,0x74,0x00,0x72,0x00,0x69,0x00,0x6e,0x00,0x67,0x00} },
+{   2,0x11d0,0,{0x00,0x00} },
+{   0,0x0000,1,{0 }}
+};
diff -Nru a/drivers/usb/inode.c b/drivers/usb/inode.c
--- a/drivers/usb/inode.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/usb/inode.c	Fri Mar 15 17:51:01 2002
@@ -40,7 +40,6 @@
 #include <asm/byteorder.h>
 
 static struct super_operations usbfs_ops;
-static struct file_operations usbfs_dir_operations;
 static struct file_operations default_file_operations;
 static struct inode_operations usbfs_dir_inode_operations;
 static struct vfsmount *usbfs_mount;
@@ -141,21 +140,6 @@
 
 /* --------------------------------------------------------------------- */
 
-/* SMP-safe */
-static struct dentry *usbfs_lookup (struct inode *dir, struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
-static int usbfs_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = USBDEVICE_SUPER_MAGIC;
-	buf->f_bsize = PAGE_CACHE_SIZE;
-	buf->f_namelen = NAME_MAX;
-	return 0;
-}
-
 static struct inode *usbfs_get_inode (struct super_block *sb, int mode, int dev)
 {
 	struct inode *inode = new_inode(sb);
@@ -177,7 +161,7 @@
 			break;
 		case S_IFDIR:
 			inode->i_op = &usbfs_dir_inode_operations;
-			inode->i_fop = &usbfs_dir_operations;
+			inode->i_fop = &simple_dir_operations;
 			break;
 		}
 	}
@@ -296,11 +280,6 @@
 	return 0;
 }
 
-static struct file_operations usbfs_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-};
-
 static struct file_operations default_file_operations = {
 	read:		default_read_file,
 	write:		default_write_file,
@@ -310,14 +289,14 @@
 
 static struct inode_operations usbfs_dir_inode_operations = {
 	create:		usbfs_create,
-	lookup:		usbfs_lookup,
+	lookup:		simple_lookup,
 	unlink:		usbfs_unlink,
 	mkdir:		usbfs_mkdir,
 	rmdir:		usbfs_rmdir,
 };
 
 static struct super_operations usbfs_ops = {
-	statfs:		usbfs_statfs,
+	statfs:		simple_statfs,
 	put_inode:	force_delete,
 };
 
@@ -489,12 +468,14 @@
 	owner:		THIS_MODULE,
 	name:		"usbdevfs",
 	get_sb:		usb_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 static struct file_system_type usb_fs_type = {
 	owner:		THIS_MODULE,
 	name:		"usbfs",
 	get_sb:		usb_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 /* --------------------------------------------------------------------- */
diff -Nru a/drivers/usb/ov511.c b/drivers/usb/ov511.c
--- a/drivers/usb/ov511.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/ov511.c	Fri Mar 15 17:51:02 2002
@@ -55,16 +55,6 @@
 	#include <asm/cpufeature.h>
 #endif
 
-/* A new implementation of the V4L 1 API exists that gives drivers direct
- * access to file_operations. The old API is compatible with all 2.2 and 2.4
- * kernels, and all 2.5 kernels through 2.5.5 (at least).
- *
- * Remove this #define to enable the new API
- *
- * Note: This has nothing to do with the V4L 2 API.
- */
-#define OV511_OLD_V4L
-
 #include "ov511.h"
 
 /*
@@ -4467,16 +4457,10 @@
  *
  ***************************************************************************/
 
-#ifdef OV511_OLD_V4L
-static int 
-ov51x_v4l1_open(struct video_device *vdev, int flags)
-{
-#else
 static int 
 ov51x_v4l1_open(struct inode *inode, struct file *file)
 {
 	struct video_device *vdev = video_devdata(file);
-#endif
 	struct usb_ov511 *ov = vdev->priv;
 	int err, i;
 
@@ -4519,6 +4503,7 @@
 	}
 
 	ov->user++;
+	file->private_data = vdev;
 	
 	if (ov->led_policy == LED_AUTO)
 		ov51x_led_control(ov, 1);
@@ -4528,16 +4513,10 @@
 	return err;
 }
 
-#ifdef OV511_OLD_V4L
-static void 
-ov51x_v4l1_close(struct video_device *vdev)
-{
-#else
 static int 
 ov51x_v4l1_close(struct inode *inode, struct file *file)
 {
-	struct video_device *vdev = video_devdata(file);
-#endif
+	struct video_device *vdev = file->private_data;
 	struct usb_ov511 *ov = vdev->priv;
 
 	PDEBUG(4, "ov511_close");
@@ -4566,16 +4545,12 @@
 		up(&ov->cbuf_lock);
 
 		ov51x_dealloc(ov, 1);
-		video_unregister_device(&ov->vdev);
 		kfree(ov);
 		ov = NULL;
 	}
+	file->private_data = NULL;
 
-#ifdef OV511_OLD_V4L
-	return;
-#else
 	return 0;
-#endif
 }
 
 /* Do not call this function directly! */
@@ -5090,84 +5065,11 @@
 	return 0;
 }
 
-#ifdef OV511_OLD_V4L
-/* This is implemented as video_generic_ioctl() in the new V4L's videodev.c */
-int
-ov51x_v4l1_generic_ioctl(struct video_device *vdev, unsigned int cmd, void *arg)
-{
-	char	sbuf[128];
-	void    *mbuf = NULL;
-	void	*parg = NULL;
-	int	err  = -EINVAL;
-	
-	/*  Copy arguments into temp kernel buffer  */
-	switch (_IOC_DIR(cmd)) {
-	case _IOC_NONE:
-		parg = arg;
-		break;
-	case _IOC_READ: /* some v4l ioctls are marked wrong ... */
-	case _IOC_WRITE:
-	case (_IOC_WRITE | _IOC_READ):
-		if (_IOC_SIZE(cmd) <= sizeof(sbuf)) {
-			parg = sbuf;
-		} else {
-			/* too big to allocate from stack */
-			mbuf = kmalloc(_IOC_SIZE(cmd), GFP_KERNEL);
-			if (NULL == mbuf)
-				return -ENOMEM;
-			parg = mbuf;
-		}
-		
-		err = -EFAULT;
-		if (copy_from_user(parg, arg, _IOC_SIZE(cmd)))
-			goto out;
-		break;
-	}
-
-	err = ov51x_v4l1_ioctl_internal(vdev->priv, cmd, parg);
-	if (err == -ENOIOCTLCMD)
-		err = -EINVAL;
-	if (err < 0)
-		goto out;
-
-	/*  Copy results into user buffer  */
-	switch (_IOC_DIR(cmd))
-	{
-	case _IOC_READ:
-	case (_IOC_WRITE | _IOC_READ):
-		if (copy_to_user(arg, parg, _IOC_SIZE(cmd)))
-			err = -EFAULT;
-		break;
-	}
-
-out:
-	if (mbuf)
-		kfree(mbuf);
-	return err;
-}
-
-static int 
-ov51x_v4l1_ioctl(struct video_device *vdev, unsigned int cmd, void *arg)
-{
-	struct usb_ov511 *ov = vdev->priv;
-	int rc;
-
-	if (down_interruptible(&ov->lock))
-		return -EINTR;
-
-	rc = ov51x_v4l1_generic_ioctl(vdev, cmd, arg);
-
-	up(&ov->lock);
-	return rc;
-}
-
-#else	/* If new V4L API */
-
 static int 
 ov51x_v4l1_ioctl(struct inode *inode, struct file *file,
 		 unsigned int cmd, void *arg)
 {
-	struct video_device *vdev = video_devdata(file);
+	struct video_device *vdev = file->private_data;
 	struct usb_ov511 *ov = vdev->priv;
 	int rc;
 
@@ -5179,21 +5081,13 @@
 	up(&ov->lock);
 	return rc;
 }
-#endif	/* OV511_OLD_V4L */
 
-#ifdef OV511_OLD_V4L
-static inline long 
-ov51x_v4l1_read(struct video_device *vdev, char *buf, unsigned long count,
-		int noblock)
-{
-#else
 static inline int 
 ov51x_v4l1_read(struct file *file, char *buf, size_t cnt, loff_t *ppos)
 {
-	struct video_device *vdev = video_devdata(file);
+	struct video_device *vdev = file->private_data;
 	int noblock = file->f_flags&O_NONBLOCK;
 	unsigned long count = cnt;
-#endif
 	struct usb_ov511 *ov = vdev->priv;
 	int i, rc = 0, frmx = -1;
 	struct ov511_frame *frame;
@@ -5343,21 +5237,11 @@
 }
 
 static int
-#ifdef OV511_OLD_V4L
-ov51x_v4l1_mmap(struct vm_area_struct *vma, struct video_device *vdev,
-		const char *adr, unsigned long size)
-{
-	unsigned long start = (unsigned long)adr;
-
-#else	/* New V4L API */
-
 ov51x_v4l1_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	struct video_device *vdev = video_devdata(file);
+	struct video_device *vdev = file->private_data;
 	unsigned long start = vma->vm_start;
 	unsigned long size  = vma->vm_end - vma->vm_start;
-#endif	/* OV511_OLD_V4L */
-
 	struct usb_ov511 *ov = vdev->priv;
 	unsigned long page, pos;
 
@@ -5394,21 +5278,6 @@
 	return 0;
 }
 
-#ifdef OV511_OLD_V4L
-static struct video_device vdev_template = {
-	owner:		THIS_MODULE,
-	name:		"OV511 USB Camera",
-	type:		VID_TYPE_CAPTURE,
-	hardware:	VID_HARDWARE_OV511,
-	open:		ov51x_v4l1_open,
-	close:		ov51x_v4l1_close,
-	read:		ov51x_v4l1_read,
-	ioctl:		ov51x_v4l1_ioctl,
-	mmap:		ov51x_v4l1_mmap,
-};
-
-#else	/* New V4L API */
-
 static struct file_operations ov511_fops = {
 	owner:		THIS_MODULE,
 	open:		ov51x_v4l1_open,
@@ -5427,7 +5296,6 @@
 	fops:           &ov511_fops,
 	kernel_ioctl:	ov51x_v4l1_ioctl,
 };
-#endif	/* OV511_OLD_V4L */
 
 #if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
 static int 
@@ -6669,9 +6537,8 @@
 	PDEBUG(3, "");
 
 	/* We don't want people trying to open up the device */
-	if (!ov->user)
-		video_unregister_device(&ov->vdev);
-	else
+	video_unregister_device(&ov->vdev);
+	if (ov->user)
 		PDEBUG(3, "Device open...deferring video_unregister_device");
 
 	for (n = 0; n < OV511_NUMFRAMES; n++)
diff -Nru a/drivers/usb/pegasus.c b/drivers/usb/pegasus.c
--- a/drivers/usb/pegasus.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/pegasus.c	Fri Mar 15 17:51:03 2002
@@ -464,12 +464,16 @@
 	if ( i == REG_TIMEOUT )
 		return 1;
 
-	if ( usb_dev_id[pegasus->dev_index].vendor == VENDOR_LINKSYS ||
-	     usb_dev_id[pegasus->dev_index].vendor == VENDOR_DLINK ) {
+	if (usb_dev_id[pegasus->dev_index].vendor == VENDOR_LINKSYS ||
+	    usb_dev_id[pegasus->dev_index].vendor == VENDOR_DLINK) {
 		__u16	auxmode;
-
-		read_mii_word( pegasus, 0, MII_TPISTATUS, &auxmode );
-		write_mii_word( pegasus, 0, MII_TPISTATUS, auxmode | 4 );
+		read_mii_word(pegasus, 1, MII_TPISTATUS, &auxmode);
+		write_mii_word(pegasus, 1, MII_TPISTATUS, auxmode | 4);
+	}
+	if (usb_dev_id[pegasus->dev_index].vendor == VENDOR_ELCON) {
+		__u16   auxmode;
+		read_mii_word(pegasus, 3, 0x1b, &auxmode);
+		write_mii_word(pegasus, 3, 0x1b, auxmode | 4);
 	}
 
 	return	0;
diff -Nru a/drivers/usb/pegasus.h b/drivers/usb/pegasus.h
--- a/drivers/usb/pegasus.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/pegasus.h	Fri Mar 15 17:51:03 2002
@@ -66,7 +66,6 @@
 #define	PEGASUS_REQ_GET_REGS	0xf0
 #define	PEGASUS_REQ_SET_REGS	0xf1
 #define	PEGASUS_REQ_SET_REG	PEGASUS_REQ_SET_REGS
-#define	ALIGN(x)		x __attribute__((aligned(L1_CACHE_BYTES)))
 
 enum pegasus_registers {
 	EthCtrl0 = 0,
@@ -103,9 +102,9 @@
 	struct usb_ctrlrequest	dr;
 	wait_queue_head_t	ctrl_wait;
 	struct semaphore	ctrl_sem;
-	unsigned char		ALIGN(rx_buff[PEGASUS_MAX_MTU]);
-	unsigned char		ALIGN(tx_buff[PEGASUS_MAX_MTU]);
-	unsigned char		ALIGN(intr_buff[8]);
+	unsigned char		rx_buff[PEGASUS_MAX_MTU];
+	unsigned char		tx_buff[PEGASUS_MAX_MTU];
+	unsigned char		intr_buff[8];
 	__u8			eth_regs[4];
 	__u8			phy;
 	__u8			gpio_res;
@@ -129,6 +128,7 @@
 #define	VENDOR_COMPAQ		0x049f
 #define	VENDOR_COREGA		0x07aa
 #define	VENDOR_DLINK		0x2001
+#define	VENDOR_ELCON		0x0db7
 #define	VENDOR_ELSA		0x05cc
 #define	VENDOR_HAWKING		0x0e66
 #define	VENDOR_IODATA		0x04bb
@@ -208,6 +208,8 @@
 		DEFAULT_GPIO_RESET | HAS_HOME_PNA )
 PEGASUS_DEV( "D-Link DSB-650", VENDOR_DLINK, 0xabc1,
 		DEFAULT_GPIO_RESET )
+PEGASUS_DEV( "ELCON EPLC10Mi USB to Powerline Adapter", VENDOR_ELCON, 0x0002,
+		DEFAULT_GPIO_RESET | PEGASUS_II | HAS_HOME_PNA )
 PEGASUS_DEV( "Elsa Micolink USB2Ethernet", VENDOR_ELSA, 0x3000,
 		DEFAULT_GPIO_RESET )
 PEGASUS_DEV( "Hawking UF100 10/100 Ethernet", VENDOR_HAWKING, 0x400c,
diff -Nru a/drivers/usb/pwc-ctrl.c b/drivers/usb/pwc-ctrl.c
--- a/drivers/usb/pwc-ctrl.c	Fri Mar 15 17:51:04 2002
+++ b/drivers/usb/pwc-ctrl.c	Fri Mar 15 17:51:04 2002
@@ -1084,62 +1084,52 @@
 	
 	case VIDIOCPWCSCQUAL:
 	{	
-		int qual, ret;
+		int *qual = arg;
+		int ret;
 
-		if (copy_from_user(&qual, arg, sizeof(int)))
-			return -EFAULT;
-			
-		if (qual < 0 || qual > 3)
+		if (*qual < 0 || *qual > 3)
 			return -EINVAL;
-		ret = pwc_try_video_mode(pdev, pdev->view.x, pdev->view.y, pdev->vframes, qual, pdev->vsnapshot);
+		ret = pwc_try_video_mode(pdev, pdev->view.x, pdev->view.y, pdev->vframes, *qual, pdev->vsnapshot);
 		if (ret < 0)
 			return ret;
-		pdev->vcompression = qual;
+		pdev->vcompression = *qual;
 		break;
 	}
 	
 	case VIDIOCPWCGCQUAL:
 	{
-		if (copy_to_user(arg, &pdev->vcompression, sizeof(int)))
-			return -EFAULT;
+		int *qual = arg;
+
+		*qual = pdev->vcompression;
 		break;
 	}
 
 	case VIDIOCPWCSAGC:
 	{
-		int agc;
+		int *agc = arg;
 		
-		if (copy_from_user(&agc, arg, sizeof(agc)))
-			return -EFAULT;	
-		else {
-			if (pwc_set_agc(pdev, agc < 0 ? 1 : 0, agc))
-				return -EINVAL;
-		}
+		if (pwc_set_agc(pdev, *agc < 0 ? 1 : 0, *agc))
+			return -EINVAL;
 		break;
 	}
 	
 	case VIDIOCPWCGAGC:
 	{
-		int agc;
+		int *agc = arg;
 		
-		if (pwc_get_agc(pdev, &agc))
+		if (pwc_get_agc(pdev, agc))
 			return -EINVAL;
-		if (copy_to_user(arg, &agc, sizeof(agc)))
-			return -EFAULT;
 		break;
 	}
 	
 	case VIDIOCPWCSSHUTTER:
 	{
-		int shutter_speed, ret;
+		int *shutter_speed = arg;
+		int ret;
 
-		if (copy_from_user(&shutter_speed, arg, sizeof(shutter_speed)))
-			return -EFAULT;
-		else {
-			ret = pwc_set_shutter_speed(pdev, shutter_speed < 0 ? 1 : 0, shutter_speed);
-			if (ret < 0)
-				return ret;
-		}
+		ret = pwc_set_shutter_speed(pdev, *shutter_speed < 0 ? 1 : 0, *shutter_speed);
+		if (ret < 0)
+			return ret;
 		break;
 	}
 	
@@ -1149,48 +1139,40 @@
 
         case VIDIOCPWCSAWB:
 	{
-		struct pwc_whitebalance wb;
+		struct pwc_whitebalance *wb = arg;
 		int ret;
 		
-		if (copy_from_user(&wb, arg, sizeof(wb)))
-			return -EFAULT;
-	
-		ret = pwc_set_awb(pdev, wb.mode);
-		if (ret >= 0 && wb.mode == PWC_WB_MANUAL) {
-			pwc_set_red_gain(pdev, wb.manual_red);
-			pwc_set_blue_gain(pdev, wb.manual_blue);
+		ret = pwc_set_awb(pdev, wb->mode);
+		if (ret >= 0 && wb->mode == PWC_WB_MANUAL) {
+			pwc_set_red_gain(pdev, wb->manual_red);
+			pwc_set_blue_gain(pdev, wb->manual_blue);
 		}
 		break;
 	}
 
 	case VIDIOCPWCGAWB:
 	{
-		struct pwc_whitebalance wb;
+		struct pwc_whitebalance *wb = arg;
 		
-		memset(&wb, 0, sizeof(wb));
-		wb.mode = pwc_get_awb(pdev);
-		if (wb.mode < 0)
+		memset(wb, 0, sizeof(*wb));
+		wb->mode = pwc_get_awb(pdev);
+		if (wb->mode < 0)
 			return -EINVAL;
-		wb.manual_red = pwc_get_red_gain(pdev);
-		wb.manual_blue = pwc_get_blue_gain(pdev);
-		if (wb.mode == PWC_WB_AUTO) {
-			wb.read_red = pwc_read_red_gain(pdev);
-			wb.read_blue = pwc_read_blue_gain(pdev);
+		wb->manual_red = pwc_get_red_gain(pdev);
+		wb->manual_blue = pwc_get_blue_gain(pdev);
+		if (wb->mode == PWC_WB_AUTO) {
+			wb->read_red = pwc_read_red_gain(pdev);
+			wb->read_blue = pwc_read_blue_gain(pdev);
 		}
-		if (copy_to_user(arg, &wb, sizeof(wb)))
-			return -EFAULT;
 		break;
 	}
 
         case VIDIOCPWCSLED:
 	{
 		int ret;
-		struct pwc_leds leds;
-
-		if (copy_from_user(&leds, arg, sizeof(leds)))
-			return -EFAULT;
+		struct pwc_leds *leds = arg;
 
-		ret = pwc_set_leds(pdev, leds.led_on, leds.led_off);
+		ret = pwc_set_leds(pdev, leds->led_on, leds->led_off);
 		if (ret<0)
 		    return ret;
 	    break;
@@ -1201,13 +1183,11 @@
 	case VIDIOCPWCGLED:
 	{
 		int led;
-		struct pwc_leds leds;
+		struct pwc_leds *leds = arg;
 		
-		led = pwc_get_leds(pdev, &leds.led_on, &leds.led_off); 
+		led = pwc_get_leds(pdev, &leds->led_on, &leds->led_off); 
 		if (led < 0)
 			return -EINVAL;
-		if (copy_to_user(arg, &leds, sizeof(leds)))
-			return -EFAULT;
 		break;
 	}
 
diff -Nru a/drivers/usb/pwc-if.c b/drivers/usb/pwc-if.c
--- a/drivers/usb/pwc-if.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/pwc-if.c	Fri Mar 15 17:51:03 2002
@@ -120,28 +120,32 @@
 
 /***/
 
-static int  pwc_video_open(struct video_device *vdev, int mode);
-static void pwc_video_close(struct video_device *vdev);
-static long pwc_video_read(struct video_device *vdev, char *buf, unsigned long count, int noblock);
-static long pwc_video_write(struct video_device *vdev, const char *buf, unsigned long count, int noblock);
-static unsigned int pwc_video_poll(struct video_device *vdev, struct file *file, poll_table *wait);
-static int  pwc_video_ioctl(struct video_device *vdev, unsigned int cmd, void *arg);
-static int  pwc_video_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size);
+static int pwc_video_open(struct inode *inode, struct file *file);
+static int pwc_video_close(struct inode *inode, struct file *file);
+static int pwc_video_read(struct file *file, char *buf,
+			  size_t count, loff_t *ppos);
+static unsigned int pwc_video_poll(struct file *file, poll_table *wait);
+static int  pwc_video_ioctl(struct inode *inode, struct file *file,
+			    unsigned int ioctlnr, void *arg);
+static int  pwc_video_mmap(struct file *file, struct vm_area_struct *vma);
 
-static struct video_device pwc_template = {
+static struct file_operations pwc_fops = {
 	owner:		THIS_MODULE,
-	name:		"Philips Webcam",	/* Filled in later */
-	type:		VID_TYPE_CAPTURE,
-	hardware:	VID_HARDWARE_PWC,
 	open:		pwc_video_open,
-	close:		pwc_video_close,
+	release:       	pwc_video_close,
 	read:		pwc_video_read,
-	write:		pwc_video_write,
 	poll:		pwc_video_poll,
-	ioctl:		pwc_video_ioctl,
 	mmap:		pwc_video_mmap,
-	initialize:	NULL,			/* initialize */
-	minor:		0			/* minor */
+	ioctl:          video_generic_ioctl,
+	llseek:         no_llseek,
+};
+static struct video_device pwc_template = {
+	owner:		THIS_MODULE,
+	name:		"Philips Webcam",	/* Filled in later */
+	type:		VID_TYPE_CAPTURE,
+	hardware:	VID_HARDWARE_PWC,
+	fops:           &pwc_fops,
+	kernel_ioctl:	pwc_video_ioctl,
 };
 
 /***************************************************************************/
@@ -909,18 +913,19 @@
 /***************************************************************************/
 /* Video4Linux functions */
 
-static int pwc_video_open(struct video_device *vdev, int mode)
+static int pwc_video_open(struct inode *inode, struct file *file)
 {
 	int i;
+	struct video_device *vdev = video_devdata(file);
 	struct pwc_device *pdev;
 
-	Trace(TRACE_OPEN, "video_open called(0x%p, 0%o).\n", vdev, mode);
+	Trace(TRACE_OPEN, "video_open called(0x%p).\n", vdev);
 	
-	if (vdev == NULL)
-		BUG();
 	pdev = (struct pwc_device *)vdev->priv;
 	if (pdev == NULL)
 		BUG();
+	if (pdev->vopen)
+		return -EBUSY;
 	
 	down(&pdev->modlock);
 	if (!pdev->usb_init) {
@@ -1008,6 +1013,7 @@
 	}
 
 	pdev->vopen++;
+	file->private_data = vdev;
 	/* lock decompressor; this has a small race condition, since we 
 	   could in theory unload pwcx.o between pwc_find_decompressor()
 	   above and this call. I doubt it's ever going to be a problem.
@@ -1020,8 +1026,9 @@
 }
 
 /* Note that all cleanup is done in the reverse order as in _open */
-static void pwc_video_close(struct video_device *vdev)
+static int pwc_video_close(struct inode *inode, struct file *file)
 {
+	struct video_device *vdev = file->private_data;
 	struct pwc_device *pdev;
 	int i;
 
@@ -1041,13 +1048,7 @@
 	if (pdev->vframe_count > 20)
 		Info("Closing video device: %d frames received, dumped %d frames, %d frames with errors.\n", pdev->vframe_count, pdev->vframes_dumped, pdev->vframes_error);
 
-	if (pdev->unplugged) {
-		/* The device was unplugged or some other error occured */
-		/* We unregister the video_device */
-		Trace(TRACE_OPEN, "Delayed video device unregistered.\n");
-		video_unregister_device(pdev->vdev);
-	}
-	else {
+	if (!pdev->unplugged) {
 		/* Normal close: stop isochronuous and interrupt endpoint */
 		Trace(TRACE_OPEN, "Normal close(): setting interface to 0.\n");
 		usb_set_interface(pdev->udev, 0, 0);
@@ -1073,6 +1074,8 @@
 	/* wake up _disconnect() routine */
 	if (pdev->unplugged)
 		wake_up(&pdev->remove_ok);
+	file->private_data = NULL;
+	return 0;
 }
 
 /*
@@ -1087,12 +1090,15 @@
                 device is tricky anyhow.
  */
  
-static long pwc_video_read(struct video_device *vdev, char *buf, unsigned long count, int noblock)
+static int pwc_video_read(struct file *file, char *buf,
+			  size_t count, loff_t *ppos)
 {
+	struct video_device *vdev = file->private_data;
 	struct pwc_device *pdev;
+	int noblock = file->f_flags & O_NONBLOCK;
 	DECLARE_WAITQUEUE(wait, current);
 
-	Trace(TRACE_READ, "video_read(0x%p, %p, %ld, %d) called.\n", vdev, buf, count, noblock);
+	Trace(TRACE_READ, "video_read(0x%p, %p, %d) called.\n", vdev, buf, count);
 	if (vdev == NULL)
 		return -EFAULT;
 	pdev = vdev->priv;
@@ -1143,14 +1149,9 @@
 	return count;
 }
 
-
-static long pwc_video_write(struct video_device *vdev, const char *buf, unsigned long count, int noblock)
-{
-	return -EINVAL;   
-}
-
-static unsigned int pwc_video_poll(struct video_device *vdev, struct file *file, poll_table *wait)
+static unsigned int pwc_video_poll(struct file *file, poll_table *wait)
 {
+	struct video_device *vdev = file->private_data;
 	struct pwc_device *pdev;
 	
 	if (vdev == NULL)
@@ -1170,8 +1171,10 @@
 	return 0;
 }
         
-static int pwc_video_ioctl(struct video_device *vdev, unsigned int cmd, void *arg)
+static int pwc_video_ioctl(struct inode *inode, struct file *file,
+			   unsigned int cmd, void *arg)
 {
+	struct video_device *vdev = file->private_data;
 	struct pwc_device *pdev;
 	DECLARE_WAITQUEUE(wait, current);
 	
@@ -1185,39 +1188,30 @@
 		/* Query cabapilities */
 		case VIDIOCGCAP: 
 		{
-			struct video_capability caps;
+			struct video_capability *caps = arg;
 
-			strcpy(caps.name, vdev->name);
-			caps.type = VID_TYPE_CAPTURE;
-			caps.channels = 1;
-			caps.audios = 1;
-			caps.minwidth  = pdev->view_min.x;
-			caps.minheight = pdev->view_min.y;
-			caps.maxwidth  = pdev->view_max.x;
-			caps.maxheight = pdev->view_max.y;
-			if (copy_to_user(arg, &caps, sizeof(caps)))
-				return -EFAULT;
+			strcpy(caps->name, vdev->name);
+			caps->type = VID_TYPE_CAPTURE;
+			caps->channels = 1;
+			caps->audios = 1;
+			caps->minwidth  = pdev->view_min.x;
+			caps->minheight = pdev->view_min.y;
+			caps->maxwidth  = pdev->view_max.x;
+			caps->maxheight = pdev->view_max.y;
 			break;
 		}
 
 		/* Channel functions (simulate 1 channel) */
 		case VIDIOCGCHAN:
 		{
-			struct video_channel v;
+			struct video_channel *v = arg;
 
-			if (copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-			if (v.channel != 0)
+			if (v->channel != 0)
 				return -EINVAL;
-
-			v.flags = 0;
-			v.tuners = 0;
-			v.type = VIDEO_TYPE_CAMERA;
-			strcpy(v.name, "Webcam");
-
-			if (copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
-
+			v->flags = 0;
+			v->tuners = 0;
+			v->type = VIDEO_TYPE_CAMERA;
+			strcpy(v->name, "Webcam");
 			return 0;
 		}
 
@@ -1227,14 +1221,9 @@
 			   the bttv driver uses a video_channel arg, which
 			   makes sense becasue it also has the norm flag.
 			 */
-			struct video_channel v;
-
-			if (copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
-
-			if (v.channel != 0)
+			struct video_channel *v = arg;
+			if (v->channel != 0)
 				return -EINVAL;
-
 			return 0;
 		}
 
@@ -1242,48 +1231,41 @@
 		/* Picture functions; contrast etc. */
 		case VIDIOCGPICT:
 		{
-			struct video_picture p;
+			struct video_picture *p = arg;
 			int val;
 
-			p.colour = 0x8000;
-			p.hue = 0x8000;
+			p->colour = 0x8000;
+			p->hue = 0x8000;
 			val = pwc_get_brightness(pdev);
 			if (val >= 0)
-				p.brightness = val;
+				p->brightness = val;
 			else
-				p.brightness = 0xffff;
+				p->brightness = 0xffff;
 			val = pwc_get_contrast(pdev);
 			if (val >= 0)
-				p.contrast = val;
+				p->contrast = val;
 			else
-				p.contrast = 0xffff;
+				p->contrast = 0xffff;
 			/* Gamma, Whiteness, what's the difference? :) */
 			val = pwc_get_gamma(pdev);
 			if (val >= 0)
-				p.whiteness = val;
+				p->whiteness = val;
 			else
-				p.whiteness = 0xffff;
+				p->whiteness = 0xffff;
 			val = pwc_get_saturation(pdev);
 			if (val >= 0)
-				p.colour = val;
+				p->colour = val;
 			else
-				p.colour = 0xffff;
-			p.depth = 24;
-			p.palette = pdev->vpalette;
-			p.hue = 0xFFFF; /* N/A */
-
-			if (copy_to_user(arg, &p, sizeof(p)))
-				return -EFAULT;
+				p->colour = 0xffff;
+			p->depth = 24;
+			p->palette = pdev->vpalette;
+			p->hue = 0xFFFF; /* N/A */
 			break;
 		}
 		
 		case VIDIOCSPICT:
 		{
-			struct video_picture p;
-
-			if (copy_from_user(&p, arg, sizeof(p)))
-				return -EFAULT;
-
+			struct video_picture *p = arg;
 			/*
 			 *	FIXME:	Suppose we are mid read
 			        ANSWER: No problem: the firmware of the camera
@@ -1292,50 +1274,44 @@
 			                is used exactly once in the uncompress
 			                routine.
 			 */
-			pwc_set_brightness(pdev, p.brightness);
-			pwc_set_contrast(pdev, p.contrast);
-			pwc_set_gamma(pdev, p.whiteness);
-			pwc_set_saturation(pdev, p.colour);
-			if (p.palette && p.palette != pdev->vpalette) {
-				if (pwc_set_palette(pdev, p.palette) < 0)
+			if (p->palette && p->palette != pdev->vpalette) {
+				if (pwc_set_palette(pdev, p->palette) < 0)
 					return -EINVAL;
 			}
+			pwc_set_brightness(pdev, p->brightness);
+			pwc_set_contrast(pdev, p->contrast);
+			pwc_set_gamma(pdev, p->whiteness);
+			pwc_set_saturation(pdev, p->colour);
 			break;
 		}
 
 		/* Window/size parameters */		
 		case VIDIOCGWIN:
 		{
-			struct video_window vw;
+			struct video_window *vw = arg;
 			
-			vw.x = 0;
-			vw.y = 0;
-			vw.width = pdev->view.x;
-			vw.height = pdev->view.y;
-			vw.chromakey = 0;
-			vw.flags = (pdev->vframes << PWC_FPS_SHIFT) | 
+			vw->x = 0;
+			vw->y = 0;
+			vw->width = pdev->view.x;
+			vw->height = pdev->view.y;
+			vw->chromakey = 0;
+			vw->flags = (pdev->vframes << PWC_FPS_SHIFT) | 
 			           (pdev->vsnapshot ? PWC_FPS_SNAPSHOT : 0);
-			
-			if (copy_to_user(arg, &vw, sizeof(vw)))
-				return -EFAULT;			
 			break;
 		}
 		
 		case VIDIOCSWIN:
 		{
-			struct video_window vw;
+			struct video_window *vw = arg;
 			int fps, snapshot, ret;
-		
-			if (copy_from_user(&vw, arg, sizeof(vw)))
-				return -EFAULT;
 
-			fps = (vw.flags & PWC_FPS_FRMASK) >> PWC_FPS_SHIFT;
-			snapshot = vw.flags & PWC_FPS_SNAPSHOT;
+			fps = (vw->flags & PWC_FPS_FRMASK) >> PWC_FPS_SHIFT;
+			snapshot = vw->flags & PWC_FPS_SNAPSHOT;
 			if (fps == 0)
 				fps = pdev->vframes;
-			if (pdev->view.x == vw.width && pdev->view.y && fps == pdev->vframes && snapshot == pdev->vsnapshot)
+			if (pdev->view.x == vw->width && pdev->view.y && fps == pdev->vframes && snapshot == pdev->vsnapshot)
 				return 0;
-			ret = pwc_try_video_mode(pdev, vw.width, vw.height, fps, pdev->vcompression, snapshot);
+			ret = pwc_try_video_mode(pdev, vw->width, vw->height, fps, pdev->vcompression, snapshot);
 			if (ret)
 				return ret;
 			break;		
@@ -1344,16 +1320,9 @@
 		/* We don't have overlay support (yet) */
 		case VIDIOCGFBUF:
 		{
-			struct video_buffer vb;
-			
-			vb.base = NULL;
-			vb.height = 0;
-			vb.width = 0;
-			vb.depth = 0;
-			vb.bytesperline = 0;
-			
-			if (copy_to_user((void *)arg, (void *)&vb, sizeof(vb)))
-				return -EFAULT;
+			struct video_buffer *vb = arg;
+
+			memset(vb,0,sizeof(*vb));
 			break;
 		}
 
@@ -1361,29 +1330,24 @@
 		case VIDIOCGMBUF:
 		{
 			/* Tell the user program how much memory is needed for a mmap() */
-			struct video_mbuf vm;
+			struct video_mbuf *vm = arg;
 			int i;
 
-			memset(&vm, 0, sizeof(vm));
-			vm.size = default_mbufs * pdev->len_per_image;
-			vm.frames = default_mbufs; /* double buffering should be enough for most applications */
+			memset(vm, 0, sizeof(*vm));
+			vm->size = default_mbufs * pdev->len_per_image;
+			vm->frames = default_mbufs; /* double buffering should be enough for most applications */
 			for (i = 0; i < default_mbufs; i++)
-				vm.offsets[i] = i * pdev->len_per_image;
-
-			if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-				return -EFAULT;
+				vm->offsets[i] = i * pdev->len_per_image;
 			break;
 		}
 
 		case VIDIOCMCAPTURE:
 		{
 			/* Start capture into a given image buffer (called 'frame' in video_mmap structure) */
-			struct video_mmap vm;
+			struct video_mmap *vm = arg;
 
-			if (copy_from_user((void *)&vm, (void *)arg, sizeof(vm)))
-				return -EFAULT;
-			Trace(TRACE_READ, "VIDIOCMCAPTURE: %dx%d, frame %d, format %d\n", vm.width, vm.height, vm.frame, vm.format);
-			if (vm.frame < 0 || vm.frame >= default_mbufs)
+			Trace(TRACE_READ, "VIDIOCMCAPTURE: %dx%d, frame %d, format %d\n", vm->width, vm->height, vm->frame, vm->format);
+			if (vm->frame < 0 || vm->frame >= default_mbufs)
 				return -EINVAL;
 
 			/* xawtv is nasty. It probes the available palettes
@@ -1391,24 +1355,24 @@
 			   various palettes... The driver doesn't support
 			   such small images, so I'm working around it.
 			 */
-			if (vm.format && vm.format != pdev->vpalette)
-				if (pwc_set_palette(pdev, vm.format) < 0)
+			if (vm->format && vm->format != pdev->vpalette)
+				if (pwc_set_palette(pdev, vm->format) < 0)
 					return -EINVAL;
 			 
-			if ((vm.width != pdev->view.x || vm.height != pdev->view.y) &&
-			    (vm.width >= pdev->view_min.x && vm.height >= pdev->view_min.y)) {
+			if ((vm->width != pdev->view.x || vm->height != pdev->view.y) &&
+			    (vm->width >= pdev->view_min.x && vm->height >= pdev->view_min.y)) {
 				int ret;
 				
 				Trace(TRACE_OPEN, "VIDIOCMCAPTURE: changing size to please xawtv :-(.\n");
-				ret = pwc_try_video_mode(pdev, vm.width, vm.height, pdev->vframes, pdev->vcompression, pdev->vsnapshot);
+				ret = pwc_try_video_mode(pdev, vm->width, vm->height, pdev->vframes, pdev->vcompression, pdev->vsnapshot);
 				if (ret)
 					return ret;
 			} /* ... size mismatch */
 
 			/* FIXME: should we lock here? */
-			if (pdev->image_used[vm.frame])
+			if (pdev->image_used[vm->frame])
 				return -EBUSY;	/* buffer wasn't available. Bummer */
-			pdev->image_used[vm.frame] = 1;
+			pdev->image_used[vm->frame] = 1;
 
 			/* Okay, we're done here. In the SYNC call we wait until a 
 			   frame comes available, then expand image into the given 
@@ -1438,18 +1402,16 @@
 			   grabber card will then overwrite the buffer 
 			   you're working on.
 			 */
-			int mbuf, ret;
+			int *mbuf = arg;
+			int ret;
 
-			if (copy_from_user((void *)&mbuf, arg, sizeof(int)))
-				return -EFAULT;
-
-			Trace(TRACE_READ, "VIDIOCSYNC called (%d).\n", mbuf);
+			Trace(TRACE_READ, "VIDIOCSYNC called (%d).\n", *mbuf);
 
 			/* bounds check */
-			if (mbuf < 0 || mbuf >= default_mbufs)
+			if (*mbuf < 0 || *mbuf >= default_mbufs)
 				return -EINVAL;
 			/* check if this buffer was requested anyway */
-			if (pdev->image_used[mbuf] == 0)
+			if (pdev->image_used[*mbuf] == 0)
 				return -EINVAL;
 
 			/* Add ourselves to the frame wait-queue.
@@ -1471,8 +1433,8 @@
 		                	set_current_state(TASK_RUNNING);
 		                	return -ERESTARTSYS;
 	        	        }
-	                	schedule();
 		                set_current_state(TASK_INTERRUPTIBLE);
+	                	schedule();
 			}
 			remove_wait_queue(&pdev->frameq, &wait);
 			set_current_state(TASK_RUNNING);
@@ -1484,10 +1446,10 @@
 			   Grabber hardware may not be so forgiving.
 			 */
 			Trace(TRACE_READ, "VIDIOCSYNC: frame ready.\n");
-			pdev->fill_image = mbuf; /* tell in which buffer we want the image to be expanded */
+			pdev->fill_image = *mbuf; /* tell in which buffer we want the image to be expanded */
 			/* Decompress, etc */
 			ret = pwc_handle_frame(pdev);
-			pdev->image_used[mbuf] = 0;
+			pdev->image_used[*mbuf] = 0;
 			if (ret)
 				return -EFAULT;
 			break;
@@ -1495,44 +1457,35 @@
 		
 		case VIDIOCGAUDIO:
 		{
-			struct video_audio v;
-			
-			strcpy(v.name, "Microphone");
-			v.audio = -1; /* unknown audio minor */
-			v.flags = 0;
-			v.mode = VIDEO_SOUND_MONO;
-			v.volume = 0;
-			v.bass = 0;
-			v.treble = 0;
-			v.balance = 0x8000;
-			v.step = 1;
+			struct video_audio *v = arg;
 			
-			if (copy_to_user(arg, &v, sizeof(v)))
-				return -EFAULT;
+			strcpy(v->name, "Microphone");
+			v->audio = -1; /* unknown audio minor */
+			v->flags = 0;
+			v->mode = VIDEO_SOUND_MONO;
+			v->volume = 0;
+			v->bass = 0;
+			v->treble = 0;
+			v->balance = 0x8000;
+			v->step = 1;
 			break;	
 		}
 		
 		case VIDIOCSAUDIO:
 		{
-			struct video_audio v;
-			
-			if (copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
 			/* Dummy: nothing can be set */
 			break;
 		}
 		
 		case VIDIOCGUNIT:
 		{
-			struct video_unit vu;
+			struct video_unit *vu = arg;
 			
-			vu.video = pdev->vdev->minor & 0x3F;
-			vu.audio = -1; /* not known yet */
-			vu.vbi = -1;
-			vu.radio = -1;
-			vu.teletext = -1;
-			if (copy_to_user(arg, &vu, sizeof(vu)))
-				return -EFAULT;
+			vu->video = pdev->vdev->minor & 0x3F;
+			vu->audio = -1; /* not known yet */
+			vu->vbi = -1;
+			vu->radio = -1;
+			vu->teletext = -1;
 			break;
 		}
 		default:
@@ -1541,13 +1494,15 @@
 	return 0;
 }	
 
-static int pwc_video_mmap(struct vm_area_struct *vma, struct video_device *vdev, const char *adr, unsigned long size)
+static int pwc_video_mmap(struct file *file, struct vm_area_struct *vma)
 {
+	struct video_device *vdev = file->private_data;
 	struct pwc_device *pdev;
-	unsigned long start = (unsigned long)adr;
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end-vma->vm_start;
 	unsigned long page, pos;
 	
-	Trace(TRACE_MEMORY, "mmap(0x%p, 0x%p, %lu) called.\n", vdev, adr, size);
+	Trace(TRACE_MEMORY, "mmap(0x%p, 0x%lx, %lu) called.\n", vdev, start, size);
 	pdev = vdev->priv;
 
 	/* FIXME - audit mmap during a read */		
@@ -1811,6 +1766,7 @@
 	
 	pdev->unplugged = 1;
 	if (pdev->vdev != NULL) {
+		video_unregister_device(pdev->vdev); 
 		if (pdev->vopen) {
 			Info("Disconnected while device/video is open!\n");
 			
@@ -1839,7 +1795,6 @@
 		else {
 			/* Normal disconnect; remove from available devices */
 			Trace(TRACE_PROBE, "Unregistering video device normally.\n");
-			video_unregister_device(pdev->vdev); 
 			kfree(pdev->vdev);
 			pdev->vdev = NULL;
 		}
diff -Nru a/drivers/usb/se401.c b/drivers/usb/se401.c
--- a/drivers/usb/se401.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/se401.c	Fri Mar 15 17:51:02 2002
@@ -1000,29 +1000,30 @@
  ***************************************************************************/
 
 
-static int se401_open(struct video_device *dev, int flags)
+static int se401_open(struct inode *inode, struct file *file)
 {
+	struct video_device *dev = video_devdata(file);
 	struct usb_se401 *se401 = (struct usb_se401 *)dev;
 	int err = 0;
 
-	/* we are called with the BKL held */
-	MOD_INC_USE_COUNT;
-
+	if (se401->user)
+		return -EBUSY;
 	se401->user=1;
 	se401->fbuf=rvmalloc(se401->maxframesize * SE401_NUMFRAMES);
 	if(!se401->fbuf) err=-ENOMEM;
 
-        if (err) {
-		MOD_DEC_USE_COUNT;
+        if (0 != err) {
 		se401->user = 0;
+	} else {
+		file->private_data = dev;
 	}
 
 	return err;
 }
 
-static void se401_close(struct video_device *dev)
+static int se401_close(struct inode *inode, struct file *file)
 {
-	/* called with BKL held */
+	struct video_device *dev = file->private_data;
         struct usb_se401 *se401 = (struct usb_se401 *)dev;
 	int i;
 
@@ -1035,34 +1036,20 @@
 	se401->user=0;
 
         if (se401->removed) {
-                video_unregister_device(&se401->vdev);
 		kfree(se401->width);
 		kfree(se401->height);
                 kfree(se401);
                 se401 = NULL;
 		info("device unregistered");
 	}
-
-        MOD_DEC_USE_COUNT;
-}
-
-static int se401_init_done(struct video_device *dev)
-{
-#if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
-        create_proc_se401_cam((struct usb_se401 *)dev);
-#endif
-
-        return 0;
+	file->private_data = NULL;
+	return 0;
 }
 
-static long se401_write(struct video_device *dev, const char *buf, unsigned long
- count, int noblock)
-{
-        return -EINVAL;
-}
-
-static int se401_ioctl(struct video_device *vdev, unsigned int cmd, void *arg)
+static int se401_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
+	struct video_device *vdev = file->private_data;
         struct usb_se401 *se401 = (struct usb_se401 *)vdev;
 
         if (!se401->dev)
@@ -1071,138 +1058,104 @@
         switch (cmd) {
 	case VIDIOCGCAP:
 	{
-		struct video_capability b;
-		strcpy(b.name, se401->camera_name);
-		b.type = VID_TYPE_CAPTURE;
-		b.channels = 1;
-		b.audios = 0;
-		b.maxwidth = se401->width[se401->sizes-1];
-		b.maxheight = se401->height[se401->sizes-1];
-		b.minwidth = se401->width[0];
-		b.minheight = se401->height[0];
-
-		if (copy_to_user(arg, &b, sizeof(b)))
-			return -EFAULT;
-
+		struct video_capability *b = arg;
+		strcpy(b->name, se401->camera_name);
+		b->type = VID_TYPE_CAPTURE;
+		b->channels = 1;
+		b->audios = 0;
+		b->maxwidth = se401->width[se401->sizes-1];
+		b->maxheight = se401->height[se401->sizes-1];
+		b->minwidth = se401->width[0];
+		b->minheight = se401->height[0];
 		return 0;
 	}
 	case VIDIOCGCHAN:
 	{
-		struct video_channel v;
+		struct video_channel *v = arg;
 
-		if (copy_from_user(&v, arg, sizeof(v)))
-			return -EFAULT;
-		if (v.channel != 0)
+		if (v->channel != 0)
 			return -EINVAL;
-
-		v.flags = 0;
-		v.tuners = 0;
-		v.type = VIDEO_TYPE_CAMERA;
-		strcpy(v.name, "Camera");
-
-		if (copy_to_user(arg, &v, sizeof(v)))
-			return -EFAULT;
-
+		v->flags = 0;
+		v->tuners = 0;
+		v->type = VIDEO_TYPE_CAMERA;
+		strcpy(v->name, "Camera");
 		return 0;
 	}
 	case VIDIOCSCHAN:
 	{
-		int v;
+		struct video_channel *v = arg;
 
-		if (copy_from_user(&v, arg, sizeof(v)))
-			return -EFAULT;
-
-		if (v != 0)
+		if (v->channel != 0)
 			return -EINVAL;
-
 		return 0;
 	}
         case VIDIOCGPICT:
         {
-		struct video_picture p;
+		struct video_picture *p = arg;
 
-		se401_get_pict(se401, &p);
-
-		if (copy_to_user(arg, &p, sizeof(p)))
-			return -EFAULT;
+		se401_get_pict(se401, p);
 		return 0;
 	}
 	case VIDIOCSPICT:
 	{
-		struct video_picture p;
-
-		if (copy_from_user(&p, arg, sizeof(p)))
-			return -EFAULT;
+		struct video_picture *p = arg;
 
-		if (se401_set_pict(se401, &p))
+		if (se401_set_pict(se401, p))
 			return -EINVAL;
 		return 0;
 	}
 	case VIDIOCSWIN:
 	{
-		struct video_window vw;
+		struct video_window *vw = arg;
 
-		if (copy_from_user(&vw, arg, sizeof(vw)))
-			return -EFAULT;
-		if (vw.flags)
+		if (vw->flags)
 			return -EINVAL;
-		if (vw.clipcount)
+		if (vw->clipcount)
 			return -EINVAL;
-		if (se401_set_size(se401, vw.width, vw.height))
+		if (se401_set_size(se401, vw->width, vw->height))
 			return -EINVAL;
-
 		return 0;
         }
 	case VIDIOCGWIN:
 	{
-		struct video_window vw;
-
-		vw.x = 0;               /* FIXME */
-		vw.y = 0;
-		vw.chromakey = 0;
-		vw.flags = 0;
-		vw.clipcount = 0;
-		vw.width = se401->cwidth;
-		vw.height = se401->cheight;
-
-		if (copy_to_user(arg, &vw, sizeof(vw)))
-			return -EFAULT;
+		struct video_window *vw = arg;
 
+		vw->x = 0;               /* FIXME */
+		vw->y = 0;
+		vw->chromakey = 0;
+		vw->flags = 0;
+		vw->clipcount = 0;
+		vw->width = se401->cwidth;
+		vw->height = se401->cheight;
 		return 0;
 	}
 	case VIDIOCGMBUF:
 	{
-		struct video_mbuf vm;
+		struct video_mbuf *vm = arg;
 		int i;
 
-		memset(&vm, 0, sizeof(vm));
-		vm.size = SE401_NUMFRAMES * se401->maxframesize;
-		vm.frames = SE401_NUMFRAMES;
+		memset(vm, 0, sizeof(*vm));
+		vm->size = SE401_NUMFRAMES * se401->maxframesize;
+		vm->frames = SE401_NUMFRAMES;
 		for (i=0; i<SE401_NUMFRAMES; i++)
-			vm.offsets[i] = se401->maxframesize * i;
-
-		if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-		return -EFAULT;
-
+			vm->offsets[i] = se401->maxframesize * i;
 		return 0;
 	}
 	case VIDIOCMCAPTURE:
 	{
-		struct video_mmap vm;
+		struct video_mmap *vm = arg;
 
-		if (copy_from_user(&vm, arg, sizeof(vm)))
-		return -EFAULT;
-		if (vm.format != VIDEO_PALETTE_RGB24)
+		if (vm->format != VIDEO_PALETTE_RGB24)
 			return -EINVAL;
-		if (vm.frame >= SE401_NUMFRAMES)
+		if (vm->frame >= SE401_NUMFRAMES)
 			return -EINVAL;
-		if (se401->frame[vm.frame].grabstate != FRAME_UNUSED)
+		if (se401->frame[vm->frame].grabstate != FRAME_UNUSED)
 			return -EBUSY;
 
 		/* Is this according to the v4l spec??? */
-		if (se401_set_size(se401, vm.width, vm.height))
+		if (se401_set_size(se401, vm->width, vm->height))
 			return -EINVAL;
-		se401->frame[vm.frame].grabstate=FRAME_READY;
+		se401->frame[vm->frame].grabstate=FRAME_READY;
 
 		if (!se401->streaming)
 			se401_start_stream(se401);
@@ -1218,28 +1171,21 @@
 	}
 	case VIDIOCSYNC:
 	{
-		int frame, ret=0;
+		int *frame = arg;
+		int ret=0;
 
-		if (copy_from_user((void *)&frame, arg, sizeof(int)))
-			return -EFAULT;
-
-		if(frame <0 || frame >= SE401_NUMFRAMES)
+		if(*frame <0 || *frame >= SE401_NUMFRAMES)
 			return -EINVAL;
 
-		ret=se401_newframe(se401, frame);
-		se401->frame[frame].grabstate=FRAME_UNUSED;
+		ret=se401_newframe(se401, *frame);
+		se401->frame[*frame].grabstate=FRAME_UNUSED;
 		return ret;
 	}
 	case VIDIOCGFBUF:
 	{
-		struct video_buffer vb;
-
-		memset(&vb, 0, sizeof(vb));
-		vb.base = NULL; /* frame buffer not supported, not used */
-
-		if (copy_to_user((void *)arg, (void *)&vb, sizeof(vb)))
-			return -EFAULT;
+		struct video_buffer *vb = arg;
 
+		memset(vb, 0, sizeof(*vb));
 		return 0;
 	}
 	case VIDIOCKEY:
@@ -1264,10 +1210,11 @@
         return 0;
 }
 
-static long se401_read(struct video_device *dev, char *buf, unsigned long count,
- int noblock)
+static int se401_read(struct file *file, char *buf,
+		     size_t count, loff_t *ppos)
 {
 	int realcount=count, ret=0;
+	struct video_device *dev = file->private_data;
 	struct usb_se401 *se401 = (struct usb_se401 *)dev;
 
 
@@ -1304,11 +1251,12 @@
 	return realcount;
 }
 
-static int se401_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr,
-        unsigned long size)
+static int se401_mmap(struct file *file, struct vm_area_struct *vma)
 {
+	struct video_device *dev = file->private_data;
 	struct usb_se401 *se401 = (struct usb_se401 *)dev;
-	unsigned long start = (unsigned long)adr;
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end-vma->vm_start;
 	unsigned long page, pos;
 
 	down(&se401->lock);
@@ -1340,17 +1288,22 @@
         return 0;
 }
 
+static struct file_operations se401_fops = {
+	owner:		THIS_MODULE,
+        open:           se401_open,
+        release:        se401_close,
+        read:           se401_read,
+        mmap:           se401_mmap,
+	ioctl:          video_generic_ioctl,
+	llseek:         no_llseek,
+};
 static struct video_device se401_template = {
+	owner:		THIS_MODULE,
         name:           "se401 USB camera",
         type:           VID_TYPE_CAPTURE,
         hardware:       VID_HARDWARE_SE401,
-        open:           se401_open,
-        close:          se401_close,
-        read:           se401_read,
-        write:          se401_write,
-        ioctl:          se401_ioctl,
-        mmap:           se401_mmap,
-        initialize:     se401_init_done,
+	fops:           &se401_fops,
+        kernel_ioctl:   se401_ioctl,
 };
 
 
@@ -1515,6 +1468,9 @@
 		err("video_register_device failed");
 		return NULL;
 	}
+#if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
+        create_proc_se401_cam(se401);
+#endif
 	info("registered new video device: video%d", se401->vdev.minor);
 
         return se401;
@@ -1524,15 +1480,12 @@
 {
 	struct usb_se401 *se401 = (struct usb_se401 *) ptr;
 
-	lock_kernel();
-	/* We don't want people trying to open up the device */
+	video_unregister_device(&se401->vdev);
 	if (!se401->user){
-		video_unregister_device(&se401->vdev);
 		usb_se401_remove_disconnected(se401);
 	} else {
 		se401->removed = 1;
 	}
-	unlock_kernel();
 }
 
 static inline void usb_se401_remove_disconnected (struct usb_se401 *se401)
diff -Nru a/drivers/usb/serial/io_edgeport.c b/drivers/usb/serial/io_edgeport.c
--- a/drivers/usb/serial/io_edgeport.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/usb/serial/io_edgeport.c	Fri Mar 15 17:51:01 2002
@@ -2,7 +2,7 @@
  * Edgeport USB Serial Converter driver
  *
  * Copyright(c) 2000 Inside Out Networks, All rights reserved.
- * Copyright(c) 2001 Greg Kroah-Hartman <greg@kroah.com>
+ * Copyright(c) 2001-2002 Greg Kroah-Hartman <greg@kroah.com>
  *
  *	This program is free software; you can redistribute it and/or modify
  *	it under the terms of the GNU General Public License as published by
@@ -25,6 +25,9 @@
  *
  * Version history:
  * 
+ * 2.3 2002_03_08 greg kroah-hartman
+ *	- fixed bug when multiple devices were attached at the same time.
+ *
  * 2.2 2001_11_14 greg kroah-hartman
  *	- fixed bug in edge_close that kept the port from being used more
  *	  than once.
@@ -1438,8 +1441,8 @@
 		edge_port->write_in_progress = FALSE;
 		return;
 	}
-	buffer[0] = IOSP_BUILD_DATA_HDR1 (edge_port->port->number, count);
-	buffer[1] = IOSP_BUILD_DATA_HDR2 (edge_port->port->number, count);
+	buffer[0] = IOSP_BUILD_DATA_HDR1 (edge_port->port->number - edge_port->port->serial->minor, count);
+	buffer[1] = IOSP_BUILD_DATA_HDR2 (edge_port->port->number - edge_port->port->serial->minor, count);
 
 	/* now copy our data */
 	bytesleft =  fifo->size - fifo->tail;
@@ -2436,7 +2439,9 @@
 
 	currentCommand = buffer;
 
-	MAKE_CMD_EXT_CMD( &currentCommand, &length, edge_port->port->number, command, param);
+	MAKE_CMD_EXT_CMD (&currentCommand, &length,
+			  edge_port->port->number - edge_port->port->serial->minor,
+			  command, param);
 
 	status = write_cmd_usb (edge_port, buffer, length);
 	if (status) {
@@ -2516,9 +2521,9 @@
 	int cmdLen = 0;
 	int divisor;
 	int status;
-	unsigned char number = edge_port->port->number;
+	unsigned char number = edge_port->port->number - edge_port->port->serial->minor;
 
-	dbg(__FUNCTION__" - port = %d, baud = %d", number, baudRate);
+	dbg(__FUNCTION__" - port = %d, baud = %d", edge_port->port->number, baudRate);
 
 	status = calc_baud_rate_divisor (baudRate, &divisor);
 	if (status) {
@@ -2621,7 +2626,9 @@
 	currCmd = cmdBuffer;
 
 	// Build a cmd in the buffer to write the given register
-	MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, edge_port->port->number, regNum, regValue);
+	MAKE_CMD_WRITE_REG (&currCmd, &cmdLen,
+			    edge_port->port->number - edge_port->port->serial->minor,
+			    regNum, regValue);
 
 	status = write_cmd_usb(edge_port, cmdBuffer, cmdLen);
 	if (status) {
diff -Nru a/drivers/usb/serial/ipaq.c b/drivers/usb/serial/ipaq.c
--- a/drivers/usb/serial/ipaq.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/serial/ipaq.c	Fri Mar 15 17:51:02 2002
@@ -9,6 +9,16 @@
  *	the Free Software Foundation; either version 2 of the License, or
  *	(at your option) any later version.
  *
+ * (8/3/2002) ganesh
+ * 	The ipaq sometimes emits a '\0' before the CLIENT string. At this
+ * 	point of time, the ppp ldisc is not yet attached to the tty, so
+ * 	n_tty echoes "^ " to the ipaq, which messes up the chat. In 2.5.6-pre2
+ * 	this causes a panic because echo_char() tries to sleep in interrupt
+ * 	context.
+ * 	The fix is to tell the upper layers that this is a raw device so that
+ * 	echoing is suppressed. Thanks to Lyle Lindholm for a detailed bug
+ * 	report.
+ *
  * (25/2/2002) ganesh
  * 	Added support for the HP Jornada 548 and 568. Completely untested.
  * 	Thanks to info from Heath Robinson and Arieh Davidoff.
@@ -148,6 +158,8 @@
 		 */
 
 		port->tty->low_latency = 1;
+		port->tty->raw = 1;
+		port->tty->real_raw = 1;
 
 		/*
 		 * Lose the small buffers usbserial provides. Make larger ones.
diff -Nru a/drivers/usb/stv680.c b/drivers/usb/stv680.c
--- a/drivers/usb/stv680.c	Fri Mar 15 17:51:01 2002
+++ b/drivers/usb/stv680.c	Fri Mar 15 17:51:01 2002
@@ -1121,13 +1121,13 @@
  * Video4Linux
  *********************************************************************/
 
-static int stv_open (struct video_device *dev, int flags)
+static int stv_open (struct inode *inode, struct file *file)
 {
+	struct video_device *dev = video_devdata(file);
 	struct usb_stv *stv680 = (struct usb_stv *) dev;
 	int err = 0;
 
 	/* we are called with the BKL held */
-	MOD_INC_USE_COUNT;
 	stv680->user = 1;
 	err = stv_init (stv680);	/* main initialization routine for camera */
 
@@ -1137,18 +1137,17 @@
 			PDEBUG (0, "STV(e): Could not rvmalloc frame bufer");
 			err = -ENOMEM;
 		}
+		file->private_data = dev;
 	}
-	if (err) {
-		MOD_DEC_USE_COUNT;
+	if (err)
 		stv680->user = 0;
-	}
 
 	return err;
 }
 
-static void stv_close (struct video_device *dev)
+static int stv_close (struct inode *inode, struct file *file)
 {
-	/* called with BKL held */
+	struct video_device *dev = file->private_data;
 	struct usb_stv *stv680 = (struct usb_stv *) dev;
 	int i;
 
@@ -1164,21 +1163,18 @@
 	stv680->user = 0;
 
 	if (stv680->removed) {
-		video_unregister_device (&stv680->vdev);
 		kfree (stv680);
 		stv680 = NULL;
 		PDEBUG (0, "STV(i): device unregistered");
 	}
-	MOD_DEC_USE_COUNT;
-}
-
-static long stv680_write (struct video_device *dev, const char *buf, unsigned long count, int noblock)
-{
-	return -EINVAL;
+	file->private_data = NULL;
+	return 0;
 }
 
-static int stv680_ioctl (struct video_device *vdev, unsigned int cmd, void *arg)
+static int stv680_ioctl (struct inode *inode, struct file *file,
+			 unsigned int cmd, void *arg)
 {
+	struct video_device *vdev = file->private_data;
 	struct usb_stv *stv680 = (struct usb_stv *) vdev;
 
 	if (!stv680->udev)
@@ -1186,89 +1182,57 @@
 
 	switch (cmd) {
 	case VIDIOCGCAP:{
-			struct video_capability b;
+			struct video_capability *b = arg;
 
-			strcpy (b.name, stv680->camera_name);
-			b.type = VID_TYPE_CAPTURE;
-			b.channels = 1;
-			b.audios = 0;
-			b.maxwidth = stv680->maxwidth;
-			b.maxheight = stv680->maxheight;
-			b.minwidth = stv680->maxwidth / 2;
-			b.minheight = stv680->maxheight / 2;
-
-			if (copy_to_user (arg, &b, sizeof (b))) {
-				PDEBUG (2, "STV(e): VIDIOCGGAP failed");
-				return -EFAULT;
-			}
+			strcpy (b->name, stv680->camera_name);
+			b->type = VID_TYPE_CAPTURE;
+			b->channels = 1;
+			b->audios = 0;
+			b->maxwidth = stv680->maxwidth;
+			b->maxheight = stv680->maxheight;
+			b->minwidth = stv680->maxwidth / 2;
+			b->minheight = stv680->maxheight / 2;
 			return 0;
 		}
 	case VIDIOCGCHAN:{
-			struct video_channel v;
+			struct video_channel *v = arg;
 
-			if (copy_from_user (&v, arg, sizeof (v)))
-				return -EFAULT;
-			if (v.channel != 0)
+			if (v->channel != 0)
 				return -EINVAL;
-
-			v.flags = 0;
-			v.tuners = 0;
-			v.type = VIDEO_TYPE_CAMERA;
-			strcpy (v.name, "STV Camera");
-
-			if (copy_to_user (arg, &v, sizeof (v))) {
-				PDEBUG (2, "STV(e): VIDIOCGCHAN failed");
-				return -EFAULT;
-			}
+			v->flags = 0;
+			v->tuners = 0;
+			v->type = VIDEO_TYPE_CAMERA;
+			strcpy (v->name, "STV Camera");
 			return 0;
 		}
 	case VIDIOCSCHAN:{
-			int v;
-
-			if (copy_from_user (&v, arg, sizeof (v))) {
-				PDEBUG (2, "STV(e): VIDIOCSCHAN failed");
-				return -EFAULT;
-			}
-			if (v != 0)
+			struct video_channel *v = arg;
+			if (v->channel != 0)
 				return -EINVAL;
-
 			return 0;
 		}
 	case VIDIOCGPICT:{
-			struct video_picture p;
+			struct video_picture *p = arg;
 
-			stv680_get_pict (stv680, &p);
-			if (copy_to_user (arg, &p, sizeof (p))) {
-				PDEBUG (2, "STV(e): VIDIOCGPICT failed");
-				return -EFAULT;
-			}
+			stv680_get_pict (stv680, p);
 			return 0;
 		}
 	case VIDIOCSPICT:{
-			struct video_picture p;
+			struct video_picture *p = arg;
 
-			if (copy_from_user (&p, arg, sizeof (p))) {
-				PDEBUG (2, "STV(e): VIDIOCSPICT failed");
-				return -EFAULT;
-			}
-			copy_from_user (&p, arg, sizeof (p));
-			PDEBUG (2, "STV(i): palette set to %i in VIDIOSPICT", p.palette);
-
-			if (stv680_set_pict (stv680, &p))
+			if (stv680_set_pict (stv680, p))
 				return -EINVAL;
 			return 0;
 		}
 	case VIDIOCSWIN:{
-			struct video_window vw;
+			struct video_window *vw = arg;
 
-			if (copy_from_user (&vw, arg, sizeof (vw)))
-				return -EFAULT;
-			if (vw.flags)
+			if (vw->flags)
 				return -EINVAL;
-			if (vw.clipcount)
+			if (vw->clipcount)
 				return -EINVAL;
-			if (vw.width != stv680->vwidth) {
-				if (stv680_set_size (stv680, vw.width, vw.height)) {
+			if (vw->width != stv680->vwidth) {
+				if (stv680_set_size (stv680, vw->width, vw->height)) {
 					PDEBUG (2, "STV(e): failed (from user) set size in VIDIOCSWIN");
 					return -EINVAL;
 				}
@@ -1276,74 +1240,59 @@
 			return 0;
 		}
 	case VIDIOCGWIN:{
-			struct video_window vw;
+			struct video_window *vw = arg;
 
-			vw.x = 0;	/* FIXME */
-			vw.y = 0;
-			vw.chromakey = 0;
-			vw.flags = 0;
-			vw.clipcount = 0;
-			vw.width = stv680->vwidth;
-			vw.height = stv680->vheight;
-
-			if (copy_to_user (arg, &vw, sizeof (vw))) {
-				PDEBUG (2, "STV(e): VIDIOCGWIN failed");
-				return -EFAULT;
-			}
+			vw->x = 0;	/* FIXME */
+			vw->y = 0;
+			vw->chromakey = 0;
+			vw->flags = 0;
+			vw->clipcount = 0;
+			vw->width = stv680->vwidth;
+			vw->height = stv680->vheight;
 			return 0;
 		}
 	case VIDIOCGMBUF:{
-			struct video_mbuf vm;
+			struct video_mbuf *vm = arg;
 			int i;
 
-			memset (&vm, 0, sizeof (vm));
-			vm.size = STV680_NUMFRAMES * stv680->maxframesize;
-			vm.frames = STV680_NUMFRAMES;
+			memset (vm, 0, sizeof (*vm));
+			vm->size = STV680_NUMFRAMES * stv680->maxframesize;
+			vm->frames = STV680_NUMFRAMES;
 			for (i = 0; i < STV680_NUMFRAMES; i++)
-				vm.offsets[i] = stv680->maxframesize * i;
-
-			if (copy_to_user ((void *) arg, (void *) &vm, sizeof (vm))) {
-				PDEBUG (2, "STV(e): VIDIOCGMBUF failed");
-				return -EFAULT;
-			}
-
+				vm->offsets[i] = stv680->maxframesize * i;
 			return 0;
 		}
 	case VIDIOCMCAPTURE:{
-			struct video_mmap vm;
+			struct video_mmap *vm = arg;
 
-			if (copy_from_user (&vm, arg, sizeof (vm))) {
-				PDEBUG (2, "STV(e): VIDIOCMCAPTURE failed");
-				return -EFAULT;
-			}
-			if (vm.format != STV_VIDEO_PALETTE) {
+			if (vm->format != STV_VIDEO_PALETTE) {
 				PDEBUG (2, "STV(i): VIDIOCMCAPTURE vm.format (%i) != VIDEO_PALETTE (%i)",
-					vm.format, STV_VIDEO_PALETTE);
-				if ((vm.format == 3) && (swapRGB_on == 0))  {
+					vm->format, STV_VIDEO_PALETTE);
+				if ((vm->format == 3) && (swapRGB_on == 0))  {
 					PDEBUG (2, "STV(i): VIDIOCMCAPTURE swapRGB is (auto) ON");
 					/* this may fix those apps (e.g., xawtv) that want BGR */
 					swapRGB = 1;
 				}
 				return -EINVAL;
 			}
-			if (vm.frame >= STV680_NUMFRAMES) {
+			if (vm->frame >= STV680_NUMFRAMES) {
 				PDEBUG (2, "STV(e): VIDIOCMCAPTURE vm.frame > NUMFRAMES");
 				return -EINVAL;
 			}
-			if ((stv680->frame[vm.frame].grabstate == FRAME_ERROR)
-			    || (stv680->frame[vm.frame].grabstate == FRAME_GRABBING)) {
+			if ((stv680->frame[vm->frame].grabstate == FRAME_ERROR)
+			    || (stv680->frame[vm->frame].grabstate == FRAME_GRABBING)) {
 				PDEBUG (2, "STV(e): VIDIOCMCAPTURE grabstate (%i) error",
-					stv680->frame[vm.frame].grabstate);
+					stv680->frame[vm->frame].grabstate);
 				return -EBUSY;
 			}
 			/* Is this according to the v4l spec??? */
-			if (stv680->vwidth != vm.width) {
-				if (stv680_set_size (stv680, vm.width, vm.height)) {
+			if (stv680->vwidth != vm->width) {
+				if (stv680_set_size (stv680, vm->width, vm->height)) {
 					PDEBUG (2, "STV(e): VIDIOCMCAPTURE set_size failed");
 					return -EINVAL;
 				}
 			}
-			stv680->frame[vm.frame].grabstate = FRAME_READY;
+			stv680->frame[vm->frame].grabstate = FRAME_READY;
 
 			if (!stv680->streaming)
 				stv680_start_stream (stv680);
@@ -1351,30 +1300,21 @@
 			return 0;
 		}
 	case VIDIOCSYNC:{
-			int frame, ret = 0;
+			int *frame = arg;
+			int ret = 0;
 
-			if (copy_from_user ((void *) &frame, arg, sizeof (int))) {
-				PDEBUG (2, "STV(e): VIDIOCSYNC failed");
-				return -EFAULT;
-			}
-			if (frame < 0 || frame >= STV680_NUMFRAMES) {
+			if (*frame < 0 || *frame >= STV680_NUMFRAMES) {
 				PDEBUG (2, "STV(e): Bad frame # in VIDIOCSYNC");
 				return -EINVAL;
 			}
-			ret = stv680_newframe (stv680, frame);
-			stv680->frame[frame].grabstate = FRAME_UNUSED;
+			ret = stv680_newframe (stv680, *frame);
+			stv680->frame[*frame].grabstate = FRAME_UNUSED;
 			return ret;
 		}
 	case VIDIOCGFBUF:{
-			struct video_buffer vb;
+			struct video_buffer *vb = arg;
 
-			memset (&vb, 0, sizeof (vb));
-			vb.base = NULL;	/* frame buffer not supported, not used */
-
-			if (copy_to_user ((void *) arg, (void *) &vb, sizeof (vb))) {
-				PDEBUG (2, "STV(e): VIDIOCSYNC failed");
-				return -EFAULT;
-			}
+			memset (vb, 0, sizeof (*vb));
 			return 0;
 		}
 	case VIDIOCKEY:
@@ -1402,10 +1342,12 @@
 	return 0;
 }
 
-static int stv680_mmap (struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size)
+static int stv680_mmap (struct file *file, struct vm_area_struct *vma)
 {
+	struct video_device *dev = file->private_data;
 	struct usb_stv *stv680 = (struct usb_stv *) dev;
-	unsigned long start = (unsigned long) adr;
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end-vma->vm_start;
 	unsigned long page, pos;
 
 	down (&stv680->lock);
@@ -1438,8 +1380,10 @@
 	return 0;
 }
 
-static long stv680_read (struct video_device *dev, char *buf, unsigned long count, int noblock)
+static int stv680_read (struct file *file, char *buf,
+			size_t count, loff_t *ppos)
 {
+	struct video_device *dev = file->private_data;
 	unsigned long int realcount = count;
 	int ret = 0;
 	struct usb_stv *stv680 = (struct usb_stv *) dev;
@@ -1484,28 +1428,22 @@
 	return realcount;
 }				/* stv680_read */
 
-static int stv_init_done (struct video_device *dev)
-{
-
-#if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
-	if (create_proc_stv680_cam ((struct usb_stv *) dev) < 0)
-		return -1;
-#endif
-	return 0;
-}
-
+static struct file_operations stv680_fops = {
+	owner:		THIS_MODULE,
+	open:		stv_open,
+	release:       	stv_close,
+	read:		stv680_read,
+	mmap:		stv680_mmap,
+	ioctl:          video_generic_ioctl,
+	llseek:         no_llseek,
+};
 static struct video_device stv680_template = {
 	owner:		THIS_MODULE,
 	name:		"STV0680 USB camera",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_SE401,
-	open:		stv_open,
-	close:		stv_close,
-	read:		stv680_read,
-	write:		stv680_write,
-	ioctl:		stv680_ioctl,
-	mmap:		stv680_mmap,
-	initialize:	stv_init_done,
+	fops:           &stv680_fops,
+	kernel_ioctl:	stv680_ioctl,
 };
 
 static void *__devinit stv680_probe (struct usb_device *dev, unsigned int ifnum, const struct usb_device_id *id)
@@ -1552,6 +1490,9 @@
 		PDEBUG (0, "STV(e): video_register_device failed");
 		return NULL;
 	}
+#if defined(CONFIG_PROC_FS) && defined(CONFIG_VIDEO_PROC_FS)
+	create_proc_stv680_cam (stv680);
+#endif
 	PDEBUG (0, "STV(i): registered new video device: video%d", stv680->vdev.minor);
 
 	return stv680;
@@ -1593,15 +1534,13 @@
 {
 	struct usb_stv *stv680 = (struct usb_stv *) ptr;
 
-	lock_kernel ();
 	/* We don't want people trying to open up the device */
+	video_unregister_device (&stv680->vdev);
 	if (!stv680->user) {
-		video_unregister_device (&stv680->vdev);
 		usb_stv680_remove_disconnected (stv680);
 	} else {
 		stv680->removed = 1;
 	}
-	unlock_kernel ();
 }
 
 static struct usb_driver stv680_driver = {
diff -Nru a/drivers/usb/usb.c b/drivers/usb/usb.c
--- a/drivers/usb/usb.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/usb.c	Fri Mar 15 17:51:03 2002
@@ -2614,7 +2614,7 @@
 	usb_hub_cleanup();
 }
 
-module_init(usb_init);
+subsys_initcall(usb_init);
 module_exit(usb_exit);
 
 /*
diff -Nru a/drivers/usb/usbvideo.c b/drivers/usb/usbvideo.c
--- a/drivers/usb/usbvideo.c	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/usbvideo.c	Fri Mar 15 17:51:03 2002
@@ -934,6 +934,10 @@
 	usb_dec_dev_use(uvd->dev);
 	uvd->dev = NULL;    	    /* USB device is no more */
 
+	video_unregister_device(&uvd->vdev);
+	if (uvd->debug > 0)
+		info("%s: Video unregistered.", proc);
+
 	if (uvd->user)
 		info("%s: In use, disconnect pending.", proc);
 	else
@@ -961,9 +965,6 @@
 		err("%s: Illegal call", proc);
 		return;
 	}
-	video_unregister_device(&uvd->vdev);
-	if (uvd->debug > 0)
-		info("%s: Video unregistered.", proc);
 
 #if USES_PROC_FS
 	assert(uvd->handle != NULL);
@@ -1013,6 +1014,23 @@
 	return rv;
 }
 
+static struct file_operations usbvideo_fops = {
+	owner:	  THIS_MODULE,
+	open:     usbvideo_v4l_open,
+	release:  usbvideo_v4l_close,
+	read:     usbvideo_v4l_read,
+	mmap:     usbvideo_v4l_mmap,
+	ioctl:    video_generic_ioctl,
+	llseek:   no_llseek,
+};
+static struct video_device usbvideo_template = {
+	owner:	      THIS_MODULE,
+	type:         VID_TYPE_CAPTURE,
+	hardware:     VID_HARDWARE_CPIA,
+	fops:         &usbvideo_fops,
+	kernel_ioctl: usbvideo_v4l_ioctl,
+};
+
 uvd_t *usbvideo_AllocateDevice(usbvideo_t *cams)
 {
 	int i, devnum;
@@ -1050,20 +1068,8 @@
 	RingQueue_Initialize(&uvd->dp);
 
 	/* Initialize video device structure */
-	memset(&uvd->vdev, 0, sizeof(uvd->vdev));
-	i = sprintf(uvd->vdev.name, "%s USB Camera", cams->drvName);
-	if (i >= sizeof(uvd->vdev.name)) {
-		err("Wrote too much into uvd->vdev.name, expect trouble!");
-	}
-	uvd->vdev.type = VID_TYPE_CAPTURE;
-	uvd->vdev.hardware = VID_HARDWARE_CPIA;
-	uvd->vdev.open = usbvideo_v4l_open;
-	uvd->vdev.close = usbvideo_v4l_close;
-	uvd->vdev.read = usbvideo_v4l_read;
-	uvd->vdev.write = usbvideo_v4l_write;
-	uvd->vdev.ioctl = usbvideo_v4l_ioctl;
-	uvd->vdev.mmap = usbvideo_v4l_mmap;
-	uvd->vdev.initialize = usbvideo_v4l_initialize;
+	uvd->vdev = usbvideo_template;
+	sprintf(uvd->vdev.name, "%.20s USB Camera", cams->drvName);
 	/*
 	 * The client is free to overwrite those because we
 	 * return control to the client's probe function right now.
@@ -1136,21 +1142,11 @@
 
 /* ******************************************************************** */
 
-int usbvideo_v4l_initialize(struct video_device *dev)
-{
-	return 0;
-}
-
-long usbvideo_v4l_write(struct video_device *dev, const char *buf,
-			unsigned long count, int noblock)
-{
-	return -EINVAL;
-}
-
-int usbvideo_v4l_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size)
+int usbvideo_v4l_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	uvd_t *uvd = (uvd_t *) dev;
-	unsigned long start = (unsigned long) adr;
+	uvd_t *uvd = file->private_data;
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end-vma->vm_start;
 	unsigned long page, pos;
 
 	if (!CAMERA_IS_OPERATIONAL(uvd))
@@ -1190,15 +1186,16 @@
  * 27-Jan-2000 Used USBVIDEO_NUMSBUF as number of URB buffers.
  * 24-May-2000 Corrected to prevent race condition (MOD_xxx_USE_COUNT).
  */
-int usbvideo_v4l_open(struct video_device *dev, int flags)
+int usbvideo_v4l_open(struct inode *inode, struct file *file)
 {
 	static const char proc[] = "usbvideo_v4l_open";
+	struct video_device *dev = video_devdata(file);
 	uvd_t *uvd = (uvd_t *) dev;
 	const int sb_size = FRAMES_PER_DESC * uvd->iso_packet_len;
 	int i, errCode = 0;
 
 	if (uvd->debug > 1)
-		info("%s($%p,$%08x", proc, dev, flags);
+		info("%s($%p", proc, dev);
 
 	usbvideo_ClientIncModCount(uvd);
 	down(&uvd->lock);
@@ -1280,6 +1277,7 @@
 				if (uvd->debug > 1)
 					info("%s: Open succeeded.", proc);
 				uvd->user++;
+				file->private_data = uvd;
 			}
 		}
 	}
@@ -1303,10 +1301,11 @@
  * 27-Jan-2000 Used USBVIDEO_NUMSBUF as number of URB buffers.
  * 24-May-2000 Moved MOD_DEC_USE_COUNT outside of code that can sleep.
  */
-void usbvideo_v4l_close(struct video_device *dev)
+int usbvideo_v4l_close(struct inode *inode, struct file *file)
 {
 	static const char proc[] = "usbvideo_v4l_close";
-	uvd_t *uvd = (uvd_t *)dev;
+	struct video_device *dev = file->private_data;
+	uvd_t *uvd = (uvd_t *) dev;
 	int i;
 
 	if (uvd->debug > 1)
@@ -1338,6 +1337,8 @@
 
 	if (uvd->debug > 1)
 		info("%s: Completed.", proc);
+	file->private_data = NULL;
+	return 0;
 }
 
 /*
@@ -1348,118 +1349,103 @@
  * History:
  * 22-Jan-2000 Corrected VIDIOCSPICT to reject unsupported settings.
  */
-int usbvideo_v4l_ioctl(struct video_device *dev, unsigned int cmd, void *arg)
+int usbvideo_v4l_ioctl(struct inode *inode, struct file *file,
+		       unsigned int cmd, void *arg)
 {
-	uvd_t *uvd = (uvd_t *)dev;
+	uvd_t *uvd = file->private_data;
 
 	if (!CAMERA_IS_OPERATIONAL(uvd))
-		return -EFAULT;
+		return -EIO;
 
 	switch (cmd) {
 		case VIDIOCGCAP:
 		{
-			if (copy_to_user(arg, &uvd->vcap, sizeof(uvd->vcap)))
-				return -EFAULT;
+			struct video_capability *b = arg;
+			*b = uvd->vcap;
 			return 0;
 		}
 		case VIDIOCGCHAN:
 		{
-			if (copy_to_user(arg, &uvd->vchan, sizeof(uvd->vchan)))
-				return -EFAULT;
+			struct video_channel *v = arg;
+			*v = uvd->vchan;
 			return 0;
 		}
 		case VIDIOCSCHAN:
-		{	/* Not used but we return success */
-			int v;
-			if (copy_from_user(&v, arg, sizeof(v)))
-				return -EFAULT;
+		{	
+			struct video_channel *v = arg;
+			if (v->channel != 0)
+				return -EINVAL;
 			return 0;
 		}
 		case VIDIOCGPICT:
 		{
-			if (copy_to_user(arg, &uvd->vpic, sizeof(uvd->vpic)))
-				return -EFAULT;
+			struct video_picture *pic = arg;
+			*pic = uvd->vpic;
 			return 0;
 		}
 		case VIDIOCSPICT:
 		{
-			struct video_picture tmp;
+			struct video_picture *pic = arg;
 			/*
 			 * Use temporary 'video_picture' structure to preserve our
 			 * own settings (such as color depth, palette) that we
 			 * aren't allowing everyone (V4L client) to change.
 			 */
-			if (copy_from_user(&tmp, arg, sizeof(tmp)))
-				return -EFAULT;
-			uvd->vpic.brightness = tmp.brightness;
-			uvd->vpic.hue = tmp.hue;
-			uvd->vpic.colour = tmp.colour;
-			uvd->vpic.contrast = tmp.contrast;
+			uvd->vpic.brightness = pic->brightness;
+			uvd->vpic.hue = pic->hue;
+			uvd->vpic.colour = pic->colour;
+			uvd->vpic.contrast = pic->contrast;
 			uvd->settingsAdjusted = 0;	/* Will force new settings */
 			return 0;
 		}
 		case VIDIOCSWIN:
 		{
-			struct video_window vw;
+			struct video_window *vw = arg;
 
-			if (copy_from_user(&vw, arg, sizeof(vw)))
-				return -EFAULT;
-			if (vw.flags)
+			if (vw->flags)
 				return -EINVAL;
-			if (vw.clipcount)
+			if (vw->clipcount)
 				return -EINVAL;
-			if (vw.width != VIDEOSIZE_X(uvd->canvas))
+			if (vw->width != VIDEOSIZE_X(uvd->canvas))
 				return -EINVAL;
-			if (vw.height != VIDEOSIZE_Y(uvd->canvas))
+			if (vw->height != VIDEOSIZE_Y(uvd->canvas))
 				return -EINVAL;
 
 			return 0;
 		}
 		case VIDIOCGWIN:
 		{
-			struct video_window vw;
+			struct video_window *vw = arg;
 
-			vw.x = 0;
-			vw.y = 0;
-			vw.width = VIDEOSIZE_X(uvd->canvas);
-			vw.height = VIDEOSIZE_Y(uvd->canvas);
-			vw.chromakey = 0;
+			vw->x = 0;
+			vw->y = 0;
+			vw->width = VIDEOSIZE_X(uvd->canvas);
+			vw->height = VIDEOSIZE_Y(uvd->canvas);
+			vw->chromakey = 0;
 			if (VALID_CALLBACK(uvd, getFPS))
-				vw.flags = GET_CALLBACK(uvd, getFPS)(uvd);
+				vw->flags = GET_CALLBACK(uvd, getFPS)(uvd);
 			else 
-				vw.flags = 10; /* FIXME: do better! */
-
-			if (copy_to_user(arg, &vw, sizeof(vw)))
-				return -EFAULT;
-
+				vw->flags = 10; /* FIXME: do better! */
 			return 0;
 		}
 		case VIDIOCGMBUF:
 		{
-			struct video_mbuf vm;
-
-			memset(&vm, 0, sizeof(vm));
-			vm.size = uvd->max_frame_size * 2;
-			vm.frames = 2;
-			vm.offsets[0] = 0;
-			vm.offsets[1] = uvd->max_frame_size;
-
-			if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-				return -EFAULT;
+			struct video_mbuf *vm = arg;
 
+			memset(vm, 0, sizeof(*vm));
+			vm->size = uvd->max_frame_size * 2;
+			vm->frames = 2;
+			vm->offsets[0] = 0;
+			vm->offsets[1] = uvd->max_frame_size;
 			return 0;
 		}
 		case VIDIOCMCAPTURE:
 		{
-			struct video_mmap vm;
+			struct video_mmap *vm = arg;
 
-			if (copy_from_user((void *)&vm, (void *)arg, sizeof(vm))) {
-				err("VIDIOCMCAPTURE: copy_from_user() failed.");
-				return -EFAULT;
-			}
 			if (uvd->debug >= 1) {
 				info("VIDIOCMCAPTURE: frame=%d. size=%dx%d, format=%d.",
-				    vm.frame, vm.width, vm.height, vm.format);
+				     vm->frame, vm->width, vm->height, vm->format);
 			}
 			/*
 			 * Check if the requested size is supported. If the requestor
@@ -1474,56 +1460,53 @@
 			 * what size we support (returned by VIDIOCGCAP). However vidcat,
 			 * for one, does not care and allows to ask for any size.
 			 */
-			if ((vm.width > VIDEOSIZE_X(uvd->canvas)) ||
-			    (vm.height > VIDEOSIZE_Y(uvd->canvas))) {
+			if ((vm->width > VIDEOSIZE_X(uvd->canvas)) ||
+			    (vm->height > VIDEOSIZE_Y(uvd->canvas))) {
 				if (uvd->debug > 0) {
 					info("VIDIOCMCAPTURE: Size=%dx%d too large; "
-					     "allowed only up to %ldx%ld", vm.width, vm.height,
+					     "allowed only up to %ldx%ld", vm->width, vm->height,
 					     VIDEOSIZE_X(uvd->canvas), VIDEOSIZE_Y(uvd->canvas));
 				}
 				return -EINVAL;
 			}
 			/* Check if the palette is supported */
-			if (((1L << vm.format) & uvd->paletteBits) == 0) {
+			if (((1L << vm->format) & uvd->paletteBits) == 0) {
 				if (uvd->debug > 0) {
 					info("VIDIOCMCAPTURE: format=%d. not supported"
 					     " (paletteBits=$%08lx)",
-					     vm.format, uvd->paletteBits);
+					     vm->format, uvd->paletteBits);
 				}
 				return -EINVAL;
 			}
-			if ((vm.frame != 0) && (vm.frame != 1)) {
-				err("VIDIOCMCAPTURE: vm.frame=%d. !E [0,1]", vm.frame);
+			if ((vm->frame != 0) && (vm->frame != 1)) {
+				err("VIDIOCMCAPTURE: vm.frame=%d. !E [0,1]", vm->frame);
 				return -EINVAL;
 			}
-			if (uvd->frame[vm.frame].frameState == FrameState_Grabbing) {
+			if (uvd->frame[vm->frame].frameState == FrameState_Grabbing) {
 				/* Not an error - can happen */
 			}
-			uvd->frame[vm.frame].request = VIDEOSIZE(vm.width, vm.height);
-			uvd->frame[vm.frame].palette = vm.format;
+			uvd->frame[vm->frame].request = VIDEOSIZE(vm->width, vm->height);
+			uvd->frame[vm->frame].palette = vm->format;
 
 			/* Mark it as ready */
-			uvd->frame[vm.frame].frameState = FrameState_Ready;
+			uvd->frame[vm->frame].frameState = FrameState_Ready;
 
-			return usbvideo_NewFrame(uvd, vm.frame);
+			return usbvideo_NewFrame(uvd, vm->frame);
 		}
 		case VIDIOCSYNC:
 		{
-			int frameNum, ret;
+			int *frameNum = arg;
+			int ret;
 
-			if (copy_from_user((void *)&frameNum, arg, sizeof(frameNum))) {
-				err("VIDIOCSYNC: copy_from_user() failed.");
-				return -EFAULT;
-			}
-			if(frameNum < 0 || frameNum >= USBVIDEO_NUMFRAMES)
+			if (*frameNum < 0 || *frameNum >= USBVIDEO_NUMFRAMES)
 				return -EINVAL;
 				
 			if (uvd->debug >= 1)
-				info("VIDIOCSYNC: syncing to frame %d.", frameNum);
+				info("VIDIOCSYNC: syncing to frame %d.", *frameNum);
 			if (uvd->flags & FLAGS_NO_DECODING)
-				ret = usbvideo_GetFrame(uvd, frameNum);
+				ret = usbvideo_GetFrame(uvd, *frameNum);
 			else if (VALID_CALLBACK(uvd, getFrame)) {
-				ret = GET_CALLBACK(uvd, getFrame)(uvd, frameNum);
+				ret = GET_CALLBACK(uvd, getFrame)(uvd, *frameNum);
 				if ((ret < 0) && (uvd->debug >= 1)) {
 					err("VIDIOCSYNC: getFrame() returned %d.", ret);
 				}
@@ -1538,19 +1521,14 @@
 			 * the user space and it's up to the application to
 			 * make use of it until it asks for another frame.
 			 */
-			uvd->frame[frameNum].frameState = FrameState_Unused;
+			uvd->frame[*frameNum].frameState = FrameState_Unused;
 			return ret;
 		}
 		case VIDIOCGFBUF:
 		{
-			struct video_buffer vb;
-
-			memset(&vb, 0, sizeof(vb));
-			vb.base = NULL;	/* frame buffer not supported, not used */
-
-			if (copy_to_user((void *)arg, (void *)&vb, sizeof(vb)))
-				return -EFAULT;
+			struct video_buffer *vb = arg;
 
+			memset(vb, 0, sizeof(*vb));
  			return 0;
  		}
 		case VIDIOCKEY:
@@ -1588,10 +1566,12 @@
  * 20-Oct-2000 Created.
  * 01-Nov-2000 Added mutex (uvd->lock).
  */
-long usbvideo_v4l_read(struct video_device *dev, char *buf, unsigned long count, int noblock)
+int usbvideo_v4l_read(struct file *file, char *buf,
+		      size_t count, loff_t *ppos)
 {
 	static const char proc[] = "usbvideo_v4l_read";
-	uvd_t *uvd = (uvd_t *) dev;
+	uvd_t *uvd = file->private_data;
+	int noblock = file->f_flags & O_NONBLOCK;
 	int frmx = -1;
 	usbvideo_frame_t *frame;
 
@@ -1599,7 +1579,7 @@
 		return -EFAULT;
 
 	if (uvd->debug >= 1)
-		info("%s: %ld. bytes, noblock=%d.", proc, count, noblock);
+		info("%s: %d. bytes, noblock=%d.", proc, count, noblock);
 
 	down(&uvd->lock);	
 
@@ -1716,7 +1696,7 @@
 	/* Update last read position */
 	frame->seqRead_Index += count;
 	if (uvd->debug >= 1) {
-		err("%s: {copy} count used=%ld, new seqRead_Index=%ld",
+		err("%s: {copy} count used=%d, new seqRead_Index=%ld",
 			proc, count, frame->seqRead_Index);
 	}
 
diff -Nru a/drivers/usb/usbvideo.h b/drivers/usb/usbvideo.h
--- a/drivers/usb/usbvideo.h	Fri Mar 15 17:51:03 2002
+++ b/drivers/usb/usbvideo.h	Fri Mar 15 17:51:03 2002
@@ -347,15 +347,14 @@
 void usbvideo_Disconnect(struct usb_device *dev, void *ptr);
 void usbvideo_CameraRelease(uvd_t *uvd);
 
-void usbvideo_v4l_close(struct video_device *dev);
+int usbvideo_v4l_close(struct inode *inode, struct file *file);
 int usbvideo_v4l_initialize(struct video_device *dev);
-int usbvideo_v4l_ioctl(struct video_device *dev, unsigned int cmd, void *arg);
-int usbvideo_v4l_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size);
-int usbvideo_v4l_open(struct video_device *dev, int flags);
-long usbvideo_v4l_read(struct video_device *dev, char *buf,
-			unsigned long count, int noblock);
-long usbvideo_v4l_write(struct video_device *dev, const char *buf,
-			unsigned long count, int noblock);
+int usbvideo_v4l_ioctl(struct inode *inode, struct file *file,
+		       unsigned int ioctlnr, void *arg);
+int usbvideo_v4l_mmap(struct file *file, struct vm_area_struct *vma);
+int usbvideo_v4l_open(struct inode *inode, struct file *file);
+int usbvideo_v4l_read(struct file *file, char *buf,
+		      size_t count, loff_t *ppos);
 
 int usbvideo_GetFrame(uvd_t *uvd, int frameNum);
 int usbvideo_NewFrame(uvd_t *uvd, int framenum);
diff -Nru a/drivers/usb/vicam.c b/drivers/usb/vicam.c
--- a/drivers/usb/vicam.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/usb/vicam.c	Fri Mar 15 17:51:02 2002
@@ -413,34 +413,37 @@
  * 
  *****************************************************************************/
 
-static int vicam_v4l_open(struct video_device *vdev, int flags)
+static int vicam_v4l_open(struct inode *inode, struct file *file)
 {
+	struct video_device *vdev = video_devdata(file);
 	struct usb_vicam *vicam = (struct usb_vicam *)vdev;
 	int err = 0;
 	
 	dbg("vicam_v4l_open");
- 
 	down(&vicam->sem);
 
 	vicam->fbuf = rvmalloc(vicam->maxframesize * VICAM_NUMFRAMES);
-	if (!vicam->fbuf)
-		err=-ENOMEM;
-	else {
-		vicam->open_count = 1;
-	}
+	if (vicam->open_count) {
+		err = -EBUSY;
+	} else if (!vicam->fbuf) {
+		err =- ENOMEM;
+	} else {
 #ifdef BLINKING
-	vicam_sndctrl(1, vicam, VICAM_REQ_CAMERA_POWER, 0x01, NULL, 0);
-	info ("led on");
-	vicam_sndctrl(1, vicam, VICAM_REQ_LED_CONTROL, 0x01, NULL, 0);
+		vicam_sndctrl(1, vicam, VICAM_REQ_CAMERA_POWER, 0x01, NULL, 0);
+		info ("led on");
+		vicam_sndctrl(1, vicam, VICAM_REQ_LED_CONTROL, 0x01, NULL, 0);
 #endif
+		vicam->open_count++;
+		file->private_data = vdev;
+	}
 
 	up(&vicam->sem);
-	
 	return err;
 }
 
-static void vicam_v4l_close(struct video_device *vdev)
+static int vicam_v4l_close(struct inode *inode, struct file *file)
 {
+	struct video_device *vdev = file->private_data;
 	struct usb_vicam *vicam = (struct usb_vicam *)vdev;
 
 	dbg("vicam_v4l_close");
@@ -456,17 +459,21 @@
 	rvfree(vicam->fbuf, vicam->maxframesize * VICAM_NUMFRAMES);
 	vicam->fbuf = 0;
 	vicam->open_count=0;
+	file->private_data = NULL;
 
 	up(&vicam->sem);
 	/* Why does se401.c have a usbdevice check here? */
 	/* If device is unplugged while open, I guess we only may unregister now */
+	return 0;
 }
 
-static long vicam_v4l_read(struct video_device *vdev, char *user_buf, unsigned long buflen, int noblock)
+static int vicam_v4l_read(struct file *file, char *user_buf,
+			  size_t buflen, loff_t *ppos)
 {
+	struct video_device *vdev = file->private_data;
 	//struct usb_vicam *vicam = (struct usb_vicam *)vdev;
 
-	dbg("vicam_v4l_read(%ld)", buflen);
+	dbg("vicam_v4l_read(%d)", buflen);
 
 	if (!vdev || !buf)
 		return -EFAULT;
@@ -476,14 +483,10 @@
 	return buflen;
 }
 
-static long vicam_v4l_write(struct video_device *dev, const char *buf, unsigned long count, int noblock)
-{
-	info("vicam_v4l_write");
-	return -EINVAL;
-}
-
-static int vicam_v4l_ioctl(struct video_device *vdev, unsigned int cmd, void *arg)
+static int vicam_v4l_ioctl(struct inode *inode, struct file *file,
+			   unsigned int cmd, void *arg)
 {
+	struct video_device *vdev = file->private_data;
 	struct usb_vicam *vicam = (struct usb_vicam *)vdev;
 	int ret = -EL3RST;
 
@@ -495,98 +498,74 @@
 	switch (cmd) {
 	case VIDIOCGCAP:
 	{
-		struct video_capability b;
-		ret = vicam_get_capability(vicam,&b);
-		dbg("name %s",b.name);
-		if (copy_to_user(arg, &b, sizeof(b)))
-			ret = -EFAULT;
+		struct video_capability *b = arg;
+		ret = vicam_get_capability(vicam,b);
+		dbg("name %s",b->name);
+		break;
 	}
 	case VIDIOCGFBUF:
 	{
-		struct video_buffer vb;
+		struct video_buffer *vb = arg;
 		info("vicam_v4l_ioctl - VIDIOCGBUF - query frame buffer param");
 		/* frame buffer not supported, not used */
-		memset(&vb, 0, sizeof(vb));
-		vb.base = NULL;
-		
-		/* FIXME - VIDIOCGFBUF - why the void */
-		if (copy_to_user((void *)arg, (void *)&vb, sizeof(vb)))
-			ret = -EFAULT;
+		memset(vb, 0, sizeof(*vb));
 		ret = 0;
+		break;
 	}
 	case VIDIOCGWIN:
 	{
-		struct video_window vw;
-		ret = vicam_get_window(vicam, &vw);
-		if (copy_to_user(arg, &vw, sizeof(vw)))
-			ret = -EFAULT;
+		struct video_window *vw = arg;
+		ret = vicam_get_window(vicam, vw);
+		break;
 	}
 	case VIDIOCSWIN:
 	{
-		struct video_window vw;
-		if (copy_from_user(&vw, arg, sizeof(vw)))
-			ret = -EFAULT;
-		else
-			ret = vicam_set_window(vicam, &vw);
-		return ret;
+		struct video_window *vw = arg;
+		ret = vicam_set_window(vicam, vw);
+		break;
 	}
 	case VIDIOCGCHAN:
 	{
-		struct video_channel v;
+		struct video_channel *v = arg;
 
-		if (copy_from_user(&v, arg, sizeof(v)))
-			ret = -EFAULT;
-		else {
-			ret = vicam_get_channel(vicam,&v);
-			if (copy_to_user(arg, &v, sizeof(v)))
-				ret = -EFAULT;
-		}
+		ret = vicam_get_channel(vicam,v);
+		break;
 	}
 	case VIDIOCSCHAN:
 	{
-		struct video_channel v;
-		if (copy_from_user(&v, arg, sizeof(v)))
-			ret = -EFAULT;
-		else
-			ret = vicam_set_channel(vicam,&v);
+		struct video_channel *v = arg;
+		ret = vicam_set_channel(vicam,v);
+		break;
  	}
 	case VIDIOCGPICT:
 	{
-		struct video_picture p;
-		ret = vicam_get_picture(vicam, &p);
-		if (copy_to_user(arg, &p, sizeof(p)))
-			ret = -EFAULT;
+		struct video_picture *p = arg;
+		ret = vicam_get_picture(vicam,p);
+		break;
 	}
 	case VIDIOCSPICT:
 	{
-		struct video_picture p;
-		if (copy_from_user(&p, arg, sizeof(p)))
-			ret = -EFAULT;
-		else
-			ret = vicam_set_picture(vicam, &p);
+		struct video_picture *p = arg;
+		ret = vicam_set_picture(vicam,p);
+		break;
 	}
 	case VIDIOCGMBUF:
 	{
-		struct video_mbuf vm;
-		ret = vicam_get_mmapbuffer(vicam,&vm);
-		/* FIXME - VIDIOCGMBUF - why the void */
-		if (copy_to_user((void *)arg, (void *)&vm, sizeof(vm)))
-			ret = -EFAULT;
+		struct video_mbuf *vm = arg;
+		ret = vicam_get_mmapbuffer(vicam,vm);
+		break;
 	}
 	case VIDIOCMCAPTURE:
 	{
-		struct video_mmap vm;
-		ret = vicam_mmap_capture(vicam, &vm);
-		/* FIXME: This is probably not right */
+		struct video_mmap *vm = arg;
+		ret = vicam_mmap_capture(vicam,vm);
+		break;
 	}
 	case VIDIOCSYNC:
 	{
-		int frame;
-		/* FIXME - VIDIOCSYNC - why the void */
-		if (copy_from_user((void *)&frame, arg, sizeof(int)))
-			ret = -EFAULT;
-		else
-			ret = vicam_sync_frame(vicam,frame);
+		int *frame = arg;
+		ret = vicam_sync_frame(vicam,*frame);
+		break;
 	}
 
 	case VIDIOCKEY:
@@ -614,10 +593,12 @@
         return ret;
 }
 
-static int vicam_v4l_mmap(struct vm_area_struct *vma, struct video_device *dev, const char *adr, unsigned long size)
+static int vicam_v4l_mmap(struct file *file, struct vm_area_struct *vma)
 {
-	struct usb_vicam *vicam = (struct usb_vicam *)dev;
-	unsigned long start = (unsigned long)adr;
+	struct video_device *vdev = file->private_data;
+	struct usb_vicam *vicam = (struct usb_vicam *)vdev;
+	unsigned long start = vma->vm_start;
+	unsigned long size  = vma->vm_end-vma->vm_start;
 	unsigned long page, pos;
 
 	down(&vicam->sem);
@@ -651,27 +632,23 @@
         return 0;
 }
 
-/* FIXME - vicam_v4l_init */
-static int vicam_v4l_init(struct video_device *dev)
-{
-	/* stick proc fs stuff in here if wanted */
-	dbg("vicam_v4l_init");
-	return 0;
-}
-
 /* FIXME - vicam_template - important */
+static struct file_operations vicam_fops = {
+	owner:		THIS_MODULE,
+	open:		vicam_v4l_open,
+	release:       	vicam_v4l_close,
+	read:		vicam_v4l_read,
+	mmap:		vicam_v4l_mmap,
+	ioctl:		video_generic_ioctl,
+	llseek:         no_llseek,
+};
 static struct video_device vicam_template = {
 	owner:		THIS_MODULE,
 	name:		"vicam USB camera",
 	type:		VID_TYPE_CAPTURE,
 	hardware:	VID_HARDWARE_SE401, /* need to ask for own id */
-	open:		vicam_v4l_open,
-	close:		vicam_v4l_close,
-	read:		vicam_v4l_read,
-	write:		vicam_v4l_write,
-	ioctl:		vicam_v4l_ioctl,
-	mmap:		vicam_v4l_mmap,
-	initialize:	vicam_v4l_init,
+	fops:           &vicam_fops,
+	kernel_ioctl:	vicam_v4l_ioctl,
 };
 
 /******************************************************************************
@@ -872,8 +849,7 @@
 
 	vicam = (struct usb_vicam *) ptr;
 
-	if (!vicam->open_count)
-		video_unregister_device(&vicam->vdev);
+	video_unregister_device(&vicam->vdev);
 	vicam->udev = NULL;
 /*
 	vicam->frame[0].grabstate = FRAME_ERROR;
diff -Nru a/drivers/video/clgenfb.c b/drivers/video/clgenfb.c
--- a/drivers/video/clgenfb.c	Fri Mar 15 17:51:02 2002
+++ b/drivers/video/clgenfb.c	Fri Mar 15 17:51:02 2002
@@ -415,8 +415,6 @@
 static unsigned clgen_def_mode = 1;
 static int noaccel = 0;
 
-static int release_io_ports = 0;
-
 
 
 /*
@@ -2413,6 +2411,8 @@
 
 
 #ifdef CONFIG_PCI
+static int release_io_ports = 0;
+
 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
  * based on the DRAM bandwidth bit and DRAM bank switching bit.  This
  * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
@@ -2635,11 +2635,11 @@
 	release_mem_region(info->board_addr, info->board_size);
 
 	if (info->btype == BT_PICASSO4) {
-		iounmap (info->board_addr);
-		iounmap (info->fbmem_phys);
+		iounmap ((void *)info->board_addr);
+		iounmap ((void *)info->fbmem_phys);
 	} else {
 		if (info->board_addr > 0x01000000)
-			iounmap (info->board_addr);
+			iounmap ((void *)info->board_addr);
 	}
 }
 
diff -Nru a/fs/Config.help b/fs/Config.help
--- a/fs/Config.help	Fri Mar 15 17:51:03 2002
+++ b/fs/Config.help	Fri Mar 15 17:51:03 2002
@@ -211,30 +211,12 @@
 CONFIG_TMPFS
   Tmpfs is a file system which keeps all files in virtual memory.
 
-  In contrast to RAM disks, which get allocated a fixed amount of
-  physical RAM, tmpfs grows and shrinks to accommodate the files it
-  contains and is able to swap unneeded pages out to swap space.
-
-  Everything is "virtual" in the sense that no files will be created
-  on your hard drive; if you reboot, everything in tmpfs will be
+  Everything in tmpfs is temporary in the sense that no files will be
+  created on your hard drive. The files live in memory and swap
+  space. If you unmount a tmpfs instance, everything stored therein is
   lost.
 
-  You should mount the file system somewhere to be able to use
-  POSIX shared memory. Adding the following line to /etc/fstab should
-  take care of things:
-
-  tmpfs		/dev/shm	tmpfs		defaults	0 0
-
-  Remember to create the directory that you intend to mount tmpfs on
-  if necessary (/dev/shm is automagically created if you use devfs).
-
-  You can set limits for the number of blocks and inodes used by the
-  file system with the mount options "size", "nr_blocks" and
-  "nr_inodes". These parameters accept a suffix k, m or g for kilo,
-  mega and giga and can be changed on remount.
-
-  The initial permissions of the root directory can be set with the
-  mount option "mode".
+  See <file:Documentation/filesystems/tmpfs.txt> for details.
 
 CONFIG_RAMFS
   Ramfs is a file system which keeps all files in RAM. It allows
@@ -560,6 +542,10 @@
 CONFIG_NFSD_V3
   If you would like to include the NFSv3 server as well as the NFSv2
   server, say Y here.  If unsure, say Y.
+
+CONFIG_NFSD_TCP
+  Enable NFS service over TCP connections.  This the officially
+  still experimental, but seems to work well.
 
 CONFIG_HPFS_FS
   OS/2 is IBM's operating system for PC's, the same as Warp, and HPFS
diff -Nru a/fs/Config.in b/fs/Config.in
--- a/fs/Config.in	Fri Mar 15 17:51:01 2002
+++ b/fs/Config.in	Fri Mar 15 17:51:01 2002
@@ -44,7 +44,8 @@
 fi
 dep_tristate 'Journalling Flash File System v2 (JFFS2) support' CONFIG_JFFS2_FS $CONFIG_MTD
 if [ "$CONFIG_JFFS2_FS" = "y" -o "$CONFIG_JFFS2_FS" = "m" ] ; then
-   int 'JFFS2 debugging verbosity (0 = quiet, 2 = noisy)' CONFIG_JFFS2_FS_DEBUG 0
+   int '  JFFS2 debugging verbosity (0 = quiet, 2 = noisy)' CONFIG_JFFS2_FS_DEBUG 0
+   dep_bool '  JFFS2 support for NAND flash' CONFIG_JFFS2_FS_NAND $CONFIG_EXPERIMENTAL
 fi
 tristate 'Compressed ROM file system support' CONFIG_CRAMFS
 bool 'Virtual memory file system support (former shm fs)' CONFIG_TMPFS
diff -Nru a/fs/Makefile b/fs/Makefile
--- a/fs/Makefile	Fri Mar 15 17:51:01 2002
+++ b/fs/Makefile	Fri Mar 15 17:51:01 2002
@@ -14,12 +14,18 @@
 		bio.o super.o block_dev.o char_dev.o stat.o exec.o pipe.o \
 		namei.o fcntl.o ioctl.o readdir.o select.o fifo.o locks.o \
 		dcache.o inode.o attr.o bad_inode.o file.o iobuf.o dnotify.o \
-		filesystems.o namespace.o seq_file.o xattr.o
+		filesystems.o namespace.o seq_file.o xattr.o libfs.o
 
 ifeq ($(CONFIG_QUOTA),y)
 obj-y += dquot.o
 else
 obj-y += noquot.o
+endif
+
+ifneq ($(CONFIG_NFSD),n)
+ifneq ($(CONFIG_NFSD),)
+obj-y += nfsctl.o
+endif
 endif
 
 subdir-$(CONFIG_PROC_FS)	+= proc
diff -Nru a/fs/adfs/super.c b/fs/adfs/super.c
--- a/fs/adfs/super.c	Fri Mar 15 17:51:01 2002
+++ b/fs/adfs/super.c	Fri Mar 15 17:51:01 2002
@@ -485,6 +485,7 @@
 	owner:		THIS_MODULE,
 	name:		"adfs",
 	get_sb:		adfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/affs/super.c b/fs/affs/super.c
--- a/fs/affs/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/affs/super.c	Fri Mar 15 17:51:03 2002
@@ -536,6 +536,7 @@
 	owner:		THIS_MODULE,
 	name:		"affs",
 	get_sb:		affs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/autofs/Makefile b/fs/autofs/Makefile
--- a/fs/autofs/Makefile	Fri Mar 15 17:51:03 2002
+++ b/fs/autofs/Makefile	Fri Mar 15 17:51:03 2002
@@ -6,7 +6,7 @@
 
 O_TARGET := autofs.o
 
-obj-y   := dir.o dirhash.o init.o inode.o root.o symlink.o waitq.o
+obj-y   := dirhash.o init.o inode.o root.o symlink.o waitq.o
 obj-m   := $(O_TARGET)
 
 include $(TOPDIR)/Rules.make
diff -Nru a/fs/autofs/autofs_i.h b/fs/autofs/autofs_i.h
--- a/fs/autofs/autofs_i.h	Fri Mar 15 17:51:03 2002
+++ b/fs/autofs/autofs_i.h	Fri Mar 15 17:51:03 2002
@@ -139,9 +139,7 @@
 
 extern struct inode_operations autofs_root_inode_operations;
 extern struct inode_operations autofs_symlink_inode_operations;
-extern struct inode_operations autofs_dir_inode_operations;
 extern struct file_operations autofs_root_operations;
-extern struct file_operations autofs_dir_operations;
 
 /* Initializing function */
 
diff -Nru a/fs/autofs/dir.c b/fs/autofs/dir.c
--- a/fs/autofs/dir.c	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,35 +0,0 @@
-/* -*- linux-c -*- --------------------------------------------------------- *
- *
- * linux/fs/autofs/dir.c
- *
- *  Copyright 1997-1998 Transmeta Corporation -- All Rights Reserved
- *
- * This file is part of the Linux kernel and is made available under
- * the terms of the GNU General Public License, version 2, or at your
- * option, any later version, incorporated herein by reference.
- *
- * ------------------------------------------------------------------------- */
-
-#include "autofs_i.h"
-
-/*
- * No entries except for "." and "..", both of which are handled by the VFS
- * layer. So all children are negative and dcache-based versions of operations
- * are OK.
- */
-/* SMP-safe */
-static struct dentry *autofs_dir_lookup(struct inode *dir,struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
-struct file_operations autofs_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-};
-
-struct inode_operations autofs_dir_inode_operations = {
-	lookup:		autofs_dir_lookup,
-};
-
diff -Nru a/fs/autofs/init.c b/fs/autofs/init.c
--- a/fs/autofs/init.c	Fri Mar 15 17:51:01 2002
+++ b/fs/autofs/init.c	Fri Mar 15 17:51:01 2002
@@ -24,6 +24,7 @@
 	owner:		THIS_MODULE,
 	name:		"autofs",
 	get_sb:		autofs_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 static int __init init_autofs_fs(void)
diff -Nru a/fs/autofs/inode.c b/fs/autofs/inode.c
--- a/fs/autofs/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/autofs/inode.c	Fri Mar 15 17:51:03 2002
@@ -39,13 +39,12 @@
 	DPRINTK(("autofs: shutting down\n"));
 }
 
-static int autofs_statfs(struct super_block *sb, struct statfs *buf);
 static void autofs_read_inode(struct inode *inode);
 
 static struct super_operations autofs_sops = {
 	read_inode:	autofs_read_inode,
 	put_super:	autofs_put_super,
-	statfs:		autofs_statfs,
+	statfs:		simple_statfs,
 };
 
 static int parse_options(char *options, int *pipefd, uid_t *uid, gid_t *gid, pid_t *pgrp, int *minproto, int *maxproto)
@@ -191,14 +190,6 @@
 	return -EINVAL;
 }
 
-static int autofs_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = AUTOFS_SUPER_MAGIC;
-	buf->f_bsize = 1024;
-	buf->f_namelen = NAME_MAX;
-	return 0;
-}
-
 static void autofs_read_inode(struct inode *inode)
 {
 	ino_t ino = inode->i_ino;
@@ -207,8 +198,8 @@
 
 	/* Initialize to the default case (stub directory) */
 
-	inode->i_op = &autofs_dir_inode_operations;
-	inode->i_fop = &autofs_dir_operations;
+	inode->i_op = &simple_dir_inode_operations;
+	inode->i_fop = &simple_dir_operations;
 	inode->i_mode = S_IFDIR | S_IRUGO | S_IXUGO;
 	inode->i_nlink = 2;
 	inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;
diff -Nru a/fs/autofs4/autofs_i.h b/fs/autofs4/autofs_i.h
--- a/fs/autofs4/autofs_i.h	Fri Mar 15 17:51:01 2002
+++ b/fs/autofs4/autofs_i.h	Fri Mar 15 17:51:01 2002
@@ -139,7 +139,6 @@
 extern struct inode_operations autofs4_symlink_inode_operations;
 extern struct inode_operations autofs4_dir_inode_operations;
 extern struct inode_operations autofs4_root_inode_operations;
-extern struct file_operations autofs4_dir_operations;
 extern struct file_operations autofs4_root_operations;
 
 /* Initializing function */
diff -Nru a/fs/autofs4/init.c b/fs/autofs4/init.c
--- a/fs/autofs4/init.c	Fri Mar 15 17:51:01 2002
+++ b/fs/autofs4/init.c	Fri Mar 15 17:51:01 2002
@@ -24,6 +24,7 @@
 	owner:		THIS_MODULE,
 	name:		"autofs",
 	get_sb:		autofs_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 static int __init init_autofs4_fs(void)
diff -Nru a/fs/autofs4/inode.c b/fs/autofs4/inode.c
--- a/fs/autofs4/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/autofs4/inode.c	Fri Mar 15 17:51:03 2002
@@ -90,11 +90,9 @@
 	DPRINTK(("autofs: shutting down\n"));
 }
 
-static int autofs4_statfs(struct super_block *sb, struct statfs *buf);
-
 static struct super_operations autofs4_sops = {
 	put_super:	autofs4_put_super,
-	statfs:		autofs4_statfs,
+	statfs:		simple_statfs,
 };
 
 static int parse_options(char *options, int *pipefd, uid_t *uid, gid_t *gid,
@@ -280,14 +278,6 @@
 	return -EINVAL;
 }
 
-static int autofs4_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = AUTOFS_SUPER_MAGIC;
-	buf->f_bsize = 1024;
-	buf->f_namelen = NAME_MAX;
-	return 0;
-}
-
 struct inode *autofs4_get_inode(struct super_block *sb,
 				struct autofs_info *inf)
 {
@@ -313,7 +303,7 @@
 	if (S_ISDIR(inf->mode)) {
 		inode->i_nlink = 2;
 		inode->i_op = &autofs4_dir_inode_operations;
-		inode->i_fop = &autofs4_dir_operations;
+		inode->i_fop = &simple_dir_operations;
 	} else if (S_ISLNK(inf->mode)) {
 		inode->i_size = inf->size;
 		inode->i_op = &autofs4_symlink_inode_operations;
diff -Nru a/fs/autofs4/root.c b/fs/autofs4/root.c
--- a/fs/autofs4/root.c	Fri Mar 15 17:51:01 2002
+++ b/fs/autofs4/root.c	Fri Mar 15 17:51:01 2002
@@ -32,11 +32,6 @@
 	ioctl:		autofs4_root_ioctl,
 };
 
-struct file_operations autofs4_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-};
-
 struct inode_operations autofs4_root_inode_operations = {
 	lookup:		autofs4_root_lookup,
 	unlink:		autofs4_dir_unlink,
diff -Nru a/fs/bfs/inode.c b/fs/bfs/inode.c
--- a/fs/bfs/inode.c	Fri Mar 15 17:51:02 2002
+++ b/fs/bfs/inode.c	Fri Mar 15 17:51:02 2002
@@ -371,6 +371,7 @@
 	owner:		THIS_MODULE,
 	name:		"bfs",
 	get_sb:		bfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/binfmt_elf.c b/fs/binfmt_elf.c
--- a/fs/binfmt_elf.c	Fri Mar 15 17:51:03 2002
+++ b/fs/binfmt_elf.c	Fri Mar 15 17:51:03 2002
@@ -548,8 +548,12 @@
 			// printk(KERN_WARNING "ELF: Ambiguous type, using ELF\n");
 			interpreter_type = INTERPRETER_ELF;
 		}
+	} else {
+		/* Executables without an interpreter also need a personality  */
+		SET_PERSONALITY(elf_ex, ibcs2_interpreter);
 	}
 
+
 	/* OK, we are done with that, now set up the arg stuff,
 	   and then start this sucker up */
 
@@ -1094,7 +1098,7 @@
 	prstatus.pr_sigpend = current->pending.signal.sig[0];
 	prstatus.pr_sighold = current->blocked.sig[0];
 	psinfo.pr_pid = prstatus.pr_pid = current->pid;
-	psinfo.pr_ppid = prstatus.pr_ppid = current->p_pptr->pid;
+	psinfo.pr_ppid = prstatus.pr_ppid = current->parent->pid;
 	psinfo.pr_pgrp = prstatus.pr_pgrp = current->pgrp;
 	psinfo.pr_sid = prstatus.pr_sid = current->session;
 	prstatus.pr_utime.tv_sec = CT_TO_SECS(current->times.tms_utime);
diff -Nru a/fs/binfmt_misc.c b/fs/binfmt_misc.c
--- a/fs/binfmt_misc.c	Fri Mar 15 17:51:02 2002
+++ b/fs/binfmt_misc.c	Fri Mar 15 17:51:02 2002
@@ -616,36 +616,10 @@
 	write:		bm_status_write,
 };
 
-/* / */
-
-/* SMP-safe */
-static struct dentry * bm_lookup(struct inode *dir, struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
-static struct file_operations bm_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-};
-
-static struct inode_operations bm_dir_inode_operations = {
-	lookup:		bm_lookup,
-};
-
 /* Superblock handling */
 
-static int bm_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = sb->s_magic;
-	buf->f_bsize = PAGE_CACHE_SIZE;
-	buf->f_namelen = 255;
-	return 0;
-}
-
 static struct super_operations s_ops = {
-	statfs:		bm_statfs,
+	statfs:		simple_statfs,
 	put_inode:	force_delete,
 	clear_inode:	bm_clear_inode,
 };
@@ -670,8 +644,8 @@
 	inode = bm_get_inode(sb, S_IFDIR | 0755);
 	if (!inode)
 		return -ENOMEM;
-	inode->i_op = &bm_dir_inode_operations;
-	inode->i_fop = &bm_dir_operations;
+	inode->i_op = &simple_dir_inode_operations;
+	inode->i_fop = &simple_dir_operations;
 	dentry[0] = d_alloc_root(inode);
 	if (!dentry[0]) {
 		iput(inode);
@@ -721,7 +695,7 @@
 	owner:		THIS_MODULE,
 	name:		"binfmt_misc",
 	get_sb:		bm_get_sb,
-	fs_flags:	FS_LITTER,
+	kill_sb:	kill_litter_super,
 };
 
 static int __init init_misc_binfmt(void)
diff -Nru a/fs/block_dev.c b/fs/block_dev.c
--- a/fs/block_dev.c	Fri Mar 15 17:51:03 2002
+++ b/fs/block_dev.c	Fri Mar 15 17:51:03 2002
@@ -260,6 +260,7 @@
 static struct file_system_type bd_type = {
 	name:		"bdev",
 	get_sb:		bd_get_sb,
+	kill_sb:	kill_anon_super,
 	fs_flags:	FS_NOMOUNT,
 };
 
diff -Nru a/fs/coda/inode.c b/fs/coda/inode.c
--- a/fs/coda/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/coda/inode.c	Fri Mar 15 17:51:03 2002
@@ -316,4 +316,5 @@
 	owner:		THIS_MODULE,
 	name:		"coda",
 	get_sb:		coda_get_sb,
+	kill_sb:	kill_anon_super,
 };
diff -Nru a/fs/cramfs/inode.c b/fs/cramfs/inode.c
--- a/fs/cramfs/inode.c	Fri Mar 15 17:51:01 2002
+++ b/fs/cramfs/inode.c	Fri Mar 15 17:51:01 2002
@@ -20,16 +20,12 @@
 #include <linux/blkdev.h>
 #include <linux/cramfs_fs.h>
 #include <linux/smp_lock.h>
+#include <linux/slab.h>
+#include <linux/cramfs_fs_sb.h>
 #include <asm/semaphore.h>
 
 #include <asm/uaccess.h>
 
-#define CRAMFS_SB_MAGIC u.cramfs_sb.magic
-#define CRAMFS_SB_SIZE u.cramfs_sb.size
-#define CRAMFS_SB_BLOCKS u.cramfs_sb.blocks
-#define CRAMFS_SB_FILES u.cramfs_sb.files
-#define CRAMFS_SB_FLAGS u.cramfs_sb.flags
-
 static struct super_operations cramfs_ops;
 static struct inode_operations cramfs_dir_inode_operations;
 static struct file_operations cramfs_directory_operations;
@@ -188,12 +184,24 @@
 	return read_buffers[buffer] + offset;
 }
 
+static void cramfs_put_super(struct super_block *sb)
+{
+	kfree(sb->u.generic_sbp);
+	sb->u.generic_sbp = NULL;
+}
 
 static int cramfs_fill_super(struct super_block *sb, void *data, int silent)
 {
 	int i;
 	struct cramfs_super super;
 	unsigned long root_offset;
+	struct cramfs_sb_info *sbi;
+
+	sbi = kmalloc(sizeof(struct cramfs_sb_info), GFP_KERNEL);
+	if (!sbi)
+		return -ENOMEM;
+	sb->u.generic_sbp = sbi;
+	memset(sbi, 0, sizeof(struct cramfs_sb_info));
 
 	sb_set_blocksize(sb, PAGE_CACHE_SIZE);
 
@@ -229,16 +237,16 @@
 	}
 	root_offset = super.root.offset << 2;
 	if (super.flags & CRAMFS_FLAG_FSID_VERSION_2) {
-		sb->CRAMFS_SB_SIZE=super.size;
-		sb->CRAMFS_SB_BLOCKS=super.fsid.blocks;
-		sb->CRAMFS_SB_FILES=super.fsid.files;
+		sbi->size=super.size;
+		sbi->blocks=super.fsid.blocks;
+		sbi->files=super.fsid.files;
 	} else {
-		sb->CRAMFS_SB_SIZE=1<<28;
-		sb->CRAMFS_SB_BLOCKS=0;
-		sb->CRAMFS_SB_FILES=0;
+		sbi->size=1<<28;
+		sbi->blocks=0;
+		sbi->files=0;
 	}
-	sb->CRAMFS_SB_MAGIC=super.magic;
-	sb->CRAMFS_SB_FLAGS=super.flags;
+	sbi->magic=super.magic;
+	sbi->flags=super.flags;
 	if (root_offset == 0)
 		printk(KERN_INFO "cramfs: empty filesystem");
 	else if (!(super.flags & CRAMFS_FLAG_SHIFTED_ROOT_OFFSET) &&
@@ -254,6 +262,8 @@
 	sb->s_root = d_alloc_root(get_cramfs_inode(sb, &super.root));
 	return 0;
 out:
+	kfree(sbi);
+	sb->u.generic_sbp = NULL;
 	return -EINVAL;
 }
 
@@ -261,10 +271,10 @@
 {
 	buf->f_type = CRAMFS_MAGIC;
 	buf->f_bsize = PAGE_CACHE_SIZE;
-	buf->f_blocks = sb->CRAMFS_SB_BLOCKS;
+	buf->f_blocks = CRAMFS_SB(sb)->blocks;
 	buf->f_bfree = 0;
 	buf->f_bavail = 0;
-	buf->f_files = sb->CRAMFS_SB_FILES;
+	buf->f_files = CRAMFS_SB(sb)->files;
 	buf->f_ffree = 0;
 	buf->f_namelen = CRAMFS_MAXPATHLEN;
 	return 0;
@@ -334,7 +344,7 @@
 	int sorted;
 
 	lock_kernel();
-	sorted = dir->i_sb->CRAMFS_SB_FLAGS & CRAMFS_FLAG_SORTED_DIRS;
+	sorted = CRAMFS_SB(dir->i_sb)->flags & CRAMFS_FLAG_SORTED_DIRS;
 	while (offset < dir->i_size) {
 		struct cramfs_inode *de;
 		char *name;
@@ -445,6 +455,7 @@
 };
 
 static struct super_operations cramfs_ops = {
+	put_super:	cramfs_put_super,
 	statfs:		cramfs_statfs,
 };
 
@@ -458,6 +469,7 @@
 	owner:		THIS_MODULE,
 	name:		"cramfs",
 	get_sb:		cramfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/dcache.c b/fs/dcache.c
--- a/fs/dcache.c	Fri Mar 15 17:51:01 2002
+++ b/fs/dcache.c	Fri Mar 15 17:51:01 2002
@@ -1252,6 +1252,7 @@
 /* SLAB cache for buffer_head structures */
 kmem_cache_t *bh_cachep;
 EXPORT_SYMBOL(bh_cachep);
+EXPORT_SYMBOL(d_genocide);
 
 extern void bdev_cache_init(void);
 extern void cdev_cache_init(void);
diff -Nru a/fs/devfs/base.c b/fs/devfs/base.c
--- a/fs/devfs/base.c	Fri Mar 15 17:51:01 2002
+++ b/fs/devfs/base.c	Fri Mar 15 17:51:01 2002
@@ -2541,17 +2541,6 @@
     return 0;
 }   /*  End Function devfs_notify_change  */
 
-static int devfs_statfs (struct super_block *sb, struct statfs *buf)
-{
-    buf->f_type = DEVFS_SUPER_MAGIC;
-    buf->f_bsize = FAKE_BLOCK_SIZE;
-    buf->f_bfree = 0;
-    buf->f_bavail = 0;
-    buf->f_ffree = 0;
-    buf->f_namelen = NAME_MAX;
-    return 0;
-}   /*  End Function devfs_statfs  */
-
 static void devfs_clear_inode (struct inode *inode)
 {
     if ( S_ISBLK (inode->i_mode) ) bdput (inode->i_bdev);
@@ -2561,7 +2550,7 @@
 { 
     put_inode:     force_delete,
     clear_inode:   devfs_clear_inode,
-    statfs:        devfs_statfs,
+    statfs:        simple_statfs,
 };
 
 
@@ -3323,6 +3312,7 @@
 static struct file_system_type devfs_fs_type = {
 	name:		DEVFS_NAME,
 	get_sb:		devfs_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 /*  File operations for devfsd follow  */
diff -Nru a/fs/devpts/inode.c b/fs/devpts/inode.c
--- a/fs/devpts/inode.c	Fri Mar 15 17:51:02 2002
+++ b/fs/devpts/inode.c	Fri Mar 15 17:51:02 2002
@@ -48,12 +48,11 @@
 	kfree(sbi);
 }
 
-static int devpts_statfs(struct super_block *sb, struct statfs *buf);
 static int devpts_remount (struct super_block * sb, int * flags, char * data);
 
 static struct super_operations devpts_sops = {
 	put_super:	devpts_put_super,
-	statfs:		devpts_statfs,
+	statfs:		simple_statfs,
 	remount_fs:	devpts_remount,
 };
 
@@ -171,14 +170,6 @@
 	return error;
 }
 
-static int devpts_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = DEVPTS_SUPER_MAGIC;
-	buf->f_bsize = 1024;
-	buf->f_namelen = NAME_MAX;
-	return 0;
-}
-
 static struct super_block *devpts_get_sb(struct file_system_type *fs_type,
 	int flags, char *dev_name, void *data)
 {
@@ -189,6 +180,7 @@
 	owner:		THIS_MODULE,
 	name:		"devpts",
 	get_sb:		devpts_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 void devpts_pty_new(int number, kdev_t device)
diff -Nru a/fs/dnotify.c b/fs/dnotify.c
--- a/fs/dnotify.c	Fri Mar 15 17:51:02 2002
+++ b/fs/dnotify.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * Directory notifications for Linux.
  *
- * Copyright (C) 2000 Stephen Rothwell
+ * Copyright (C) 2000,2001,2002 Stephen Rothwell
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the
@@ -59,7 +59,7 @@
 	write_lock(&dn_lock);
 	prev = &inode->i_dnotify;
 	for (odn = *prev; odn != NULL; prev = &odn->dn_next, odn = *prev)
-		if (odn->dn_filp == filp)
+		if ((odn->dn_owner == current->files) && (odn->dn_filp == filp))
 			break;
 	if (odn != NULL) {
 		if (turning_off) {
@@ -82,6 +82,7 @@
 	dn->dn_mask = arg;
 	dn->dn_fd = fd;
 	dn->dn_filp = filp;
+	dn->dn_owner = current->files;
 	inode->i_dnotify_mask |= arg & ~DN_MULTISHOT;
 	dn->dn_next = inode->i_dnotify;
 	inode->i_dnotify = dn;
diff -Nru a/fs/driverfs/inode.c b/fs/driverfs/inode.c
--- a/fs/driverfs/inode.c	Fri Mar 15 17:51:01 2002
+++ b/fs/driverfs/inode.c	Fri Mar 15 17:51:01 2002
@@ -48,7 +48,6 @@
 #define DRIVERFS_MAGIC 0x42454552
 
 static struct super_operations driverfs_ops;
-static struct file_operations driverfs_dir_operations;
 static struct file_operations driverfs_file_operations;
 static struct inode_operations driverfs_dir_inode_operations;
 static struct dentry_operations driverfs_dentry_dir_ops;
@@ -58,21 +57,6 @@
 static spinlock_t mount_lock = SPIN_LOCK_UNLOCKED;
 static int mount_count = 0;
 
-static int driverfs_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = DRIVERFS_MAGIC;
-	buf->f_bsize = PAGE_CACHE_SIZE;
-	buf->f_namelen = 255;
-	return 0;
-}
-
-/* SMP-safe */
-static struct dentry *driverfs_lookup(struct inode *dir, struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
 struct inode *driverfs_get_inode(struct super_block *sb, int mode, int dev)
 {
 	struct inode *inode = new_inode(sb);
@@ -94,7 +78,7 @@
 			break;
 		case S_IFDIR:
 			inode->i_op = &driverfs_dir_inode_operations;
-			inode->i_fop = &driverfs_dir_operations;
+			inode->i_fop = &simple_dir_operations;
 			break;
 		}
 	}
@@ -375,14 +359,9 @@
 	release:	driverfs_release,
 };
 
-static struct file_operations driverfs_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-};
-
 static struct inode_operations driverfs_dir_inode_operations = {
 	create:		driverfs_create,
-	lookup:		driverfs_lookup,
+	lookup:		simple_lookup,
 	unlink:		driverfs_unlink,
 	mkdir:		driverfs_mkdir,
 	rmdir:		driverfs_rmdir,
@@ -393,7 +372,7 @@
 };
 
 static struct super_operations driverfs_ops = {
-	statfs:		driverfs_statfs,
+	statfs:		simple_statfs,
 	put_inode:	force_delete,
 };
 
@@ -433,7 +412,7 @@
 	owner:		THIS_MODULE,
 	name:		"driverfs",
 	get_sb:		driverfs_get_sb,
-	fs_flags:	FS_LITTER,
+	kill_sb:	kill_litter_super,
 };
 
 static int get_mount(void)
diff -Nru a/fs/efs/super.c b/fs/efs/super.c
--- a/fs/efs/super.c	Fri Mar 15 17:51:02 2002
+++ b/fs/efs/super.c	Fri Mar 15 17:51:02 2002
@@ -24,6 +24,7 @@
 	owner:		THIS_MODULE,
 	name:		"efs",
 	get_sb:		efs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
@@ -69,10 +70,17 @@
 		printk(KERN_INFO "efs_inode_cache: not all structures were freed\n");
 }
 
+void efs_put_super(struct super_block *s)
+{
+	kfree(s->u.generic_sbp);
+	s->u.generic_sbp = NULL;
+}
+
 static struct super_operations efs_superblock_operations = {
 	alloc_inode:	efs_alloc_inode,
 	destroy_inode:	efs_destroy_inode,
 	read_inode:	efs_read_inode,
+	put_super:	efs_put_super,
 	statfs:		efs_statfs,
 };
 
@@ -204,7 +212,11 @@
 	struct efs_sb_info *sb;
 	struct buffer_head *bh;
 
- 	sb = SUPER_INFO(s);
+ 	sb = kmalloc(sizeof(struct efs_sb_info), GFP_KERNEL);
+	if (!sb)
+		return -ENOMEM;
+	s->u.generic_sbp = sb;
+	memset(sb, 0, sizeof(struct efs_sb_info));
  
 	s->s_magic		= EFS_SUPER_MAGIC;
 	sb_set_blocksize(s, EFS_BLOCKSIZE);
@@ -262,6 +274,8 @@
 
 out_no_fs_ul:
 out_no_fs:
+	s->u.generic_sbp = NULL;
+	kfree(sb);
 	return -EINVAL;
 }
 
diff -Nru a/fs/exec.c b/fs/exec.c
--- a/fs/exec.c	Fri Mar 15 17:51:02 2002
+++ b/fs/exec.c	Fri Mar 15 17:51:02 2002
@@ -154,7 +154,7 @@
 }
 
 /*
- * count() counts the number of arguments/envelopes
+ * count() counts the number of strings in array ARGV.
  */
 static int count(char ** argv, int max)
 {
@@ -177,7 +177,7 @@
 }
 
 /*
- * 'copy_strings()' copies argument/envelope strings from user
+ * 'copy_strings()' copies argument/environment strings from user
  * memory to free pages in kernel mem. These are in a format ready
  * to be put directly into the top of new user memory.
  */
diff -Nru a/fs/ext2/balloc.c b/fs/ext2/balloc.c
--- a/fs/ext2/balloc.c	Fri Mar 15 17:51:02 2002
+++ b/fs/ext2/balloc.c	Fri Mar 15 17:51:02 2002
@@ -41,7 +41,7 @@
 	unsigned long group_desc;
 	unsigned long offset;
 	struct ext2_group_desc * desc;
-	struct ext2_sb_info *sbi = &sb->u.ext2_sb;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
 
 	if (block_group >= sbi->s_groups_count) {
 		ext2_error (sb, "ext2_get_group_desc",
@@ -110,7 +110,7 @@
 static struct buffer_head *load_block_bitmap(struct super_block * sb,
 						unsigned int block_group)
 {
-	struct ext2_sb_info *sbi = &sb->u.ext2_sb;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
 	int i, slot = 0;
 	struct buffer_head *bh = sbi->s_block_bitmap[0];
 
@@ -249,7 +249,7 @@
 	unsigned freed = 0, group_freed;
 
 	lock_super (sb);
-	es = sb->u.ext2_sb.s_es;
+	es = EXT2_SB(sb)->s_es;
 	if (block < le32_to_cpu(es->s_first_data_block) || 
 	    (block + count) > le32_to_cpu(es->s_blocks_count)) {
 		ext2_error (sb, "ext2_free_blocks",
@@ -285,9 +285,9 @@
 	if (in_range (le32_to_cpu(desc->bg_block_bitmap), block, count) ||
 	    in_range (le32_to_cpu(desc->bg_inode_bitmap), block, count) ||
 	    in_range (block, le32_to_cpu(desc->bg_inode_table),
-		      sb->u.ext2_sb.s_itb_per_group) ||
+		      EXT2_SB(sb)->s_itb_per_group) ||
 	    in_range (block + count - 1, le32_to_cpu(desc->bg_inode_table),
-		      sb->u.ext2_sb.s_itb_per_group))
+		      EXT2_SB(sb)->s_itb_per_group))
 		ext2_error (sb, "ext2_free_blocks",
 			    "Freeing blocks in system zones - "
 			    "Block = %lu, count = %lu",
@@ -552,11 +552,11 @@
 	int i;
 	
 	lock_super (sb);
-	es = sb->u.ext2_sb.s_es;
+	es = EXT2_SB(sb)->s_es;
 	desc_count = 0;
 	bitmap_count = 0;
 	desc = NULL;
-	for (i = 0; i < sb->u.ext2_sb.s_groups_count; i++) {
+	for (i = 0; i < EXT2_SB(sb)->s_groups_count; i++) {
 		struct buffer_head *bh;
 		desc = ext2_get_group_desc (sb, i, NULL);
 		if (!desc)
@@ -576,7 +576,7 @@
 	unlock_super (sb);
 	return bitmap_count;
 #else
-	return le32_to_cpu(sb->u.ext2_sb.s_es->s_free_blocks_count);
+	return le32_to_cpu(EXT2_SB(sb)->s_es->s_free_blocks_count);
 #endif
 }
 
@@ -584,7 +584,7 @@
 				struct super_block * sb,
 				unsigned char * map)
 {
-	return ext2_test_bit ((block - le32_to_cpu(sb->u.ext2_sb.s_es->s_first_data_block)) %
+	return ext2_test_bit ((block - le32_to_cpu(EXT2_SB(sb)->s_es->s_first_data_block)) %
 			 EXT2_BLOCKS_PER_GROUP(sb), map);
 }
 
@@ -651,11 +651,11 @@
 	struct ext2_group_desc * desc;
 	int i;
 
-	es = sb->u.ext2_sb.s_es;
+	es = EXT2_SB(sb)->s_es;
 	desc_count = 0;
 	bitmap_count = 0;
 	desc = NULL;
-	for (i = 0; i < sb->u.ext2_sb.s_groups_count; i++) {
+	for (i = 0; i < EXT2_SB(sb)->s_groups_count; i++) {
 		desc = ext2_get_group_desc (sb, i, NULL);
 		if (!desc)
 			continue;
@@ -685,7 +685,7 @@
 				    "Inode bitmap for group %d is marked free",
 				    i);
 
-		for (j = 0; j < sb->u.ext2_sb.s_itb_per_group; j++)
+		for (j = 0; j < EXT2_SB(sb)->s_itb_per_group; j++)
 			if (!block_in_use (le32_to_cpu(desc->bg_inode_table) + j, sb, bh->b_data))
 				ext2_error (sb, "ext2_check_blocks_bitmap",
 					    "Block #%ld of the inode table in "
diff -Nru a/fs/ext2/dir.c b/fs/ext2/dir.c
--- a/fs/ext2/dir.c	Fri Mar 15 17:51:01 2002
+++ b/fs/ext2/dir.c	Fri Mar 15 17:51:01 2002
@@ -68,7 +68,7 @@
 	struct super_block *sb = dir->i_sb;
 	unsigned chunk_size = ext2_chunk_size(dir);
 	char *kaddr = page_address(page);
-	u32 max_inumber = le32_to_cpu(sb->u.ext2_sb.s_es->s_inodes_count);
+	u32 max_inumber = le32_to_cpu(EXT2_SB(sb)->s_es->s_inodes_count);
 	unsigned offs, rec_len;
 	unsigned limit = PAGE_CACHE_SIZE;
 	ext2_dirent *p;
diff -Nru a/fs/ext2/ialloc.c b/fs/ext2/ialloc.c
--- a/fs/ext2/ialloc.c	Fri Mar 15 17:51:03 2002
+++ b/fs/ext2/ialloc.c	Fri Mar 15 17:51:03 2002
@@ -77,7 +77,7 @@
 					      unsigned int block_group)
 {
 	int i, slot = 0;
-	struct ext2_sb_info *sbi = &sb->u.ext2_sb;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
 	struct buffer_head *bh = sbi->s_inode_bitmap[0];
 
 	if (block_group >= sbi->s_groups_count)
@@ -171,7 +171,7 @@
 	}
 
 	lock_super (sb);
-	es = sb->u.ext2_sb.s_es;
+	es = EXT2_SB(sb)->s_es;
 	is_directory = S_ISDIR(inode->i_mode);
 
 	/* Do this BEFORE marking the inode not in use or returning an error */
@@ -205,7 +205,7 @@
 		mark_buffer_dirty(bh2);
 		es->s_free_inodes_count =
 			cpu_to_le32(le32_to_cpu(es->s_free_inodes_count) + 1);
-		mark_buffer_dirty(sb->u.ext2_sb.s_sbh);
+		mark_buffer_dirty(EXT2_SB(sb)->s_sbh);
 	}
 	mark_buffer_dirty(bh);
 	if (sb->s_flags & MS_SYNCHRONOUS) {
@@ -230,8 +230,8 @@
 
 static int find_group_dir(struct super_block *sb, int parent_group)
 {
-	struct ext2_super_block * es = sb->u.ext2_sb.s_es;
-	int ngroups = sb->u.ext2_sb.s_groups_count;
+	struct ext2_super_block * es = EXT2_SB(sb)->s_es;
+	int ngroups = EXT2_SB(sb)->s_groups_count;
 	int avefreei = le32_to_cpu(es->s_free_inodes_count) / ngroups;
 	struct ext2_group_desc *desc, *best_desc = NULL;
 	struct buffer_head *bh, *best_bh = NULL;
@@ -263,7 +263,7 @@
 
 static int find_group_other(struct super_block *sb, int parent_group)
 {
-	int ngroups = sb->u.ext2_sb.s_groups_count;
+	int ngroups = EXT2_SB(sb)->s_groups_count;
 	struct ext2_group_desc *desc;
 	struct buffer_head *bh;
 	int group, i;
@@ -330,7 +330,7 @@
 
 	ei = EXT2_I(inode);
 	lock_super (sb);
-	es = sb->u.ext2_sb.s_es;
+	es = EXT2_SB(sb)->s_es;
 repeat:
 	if (S_ISDIR(mode))
 		group = find_group_dir(sb, EXT2_I(dir)->i_block_group);
@@ -369,7 +369,7 @@
 
 	es->s_free_inodes_count =
 		cpu_to_le32(le32_to_cpu(es->s_free_inodes_count) - 1);
-	mark_buffer_dirty(sb->u.ext2_sb.s_sbh);
+	mark_buffer_dirty(EXT2_SB(sb)->s_sbh);
 	sb->s_dirt = 1;
 	inode->i_uid = current->fsuid;
 	if (test_opt (sb, GRPID))
@@ -405,7 +405,7 @@
 	ei->i_dir_start_lookup = 0;
 	if (ei->i_flags & EXT2_SYNC_FL)
 		inode->i_flags |= S_SYNC;
-	inode->i_generation = sb->u.ext2_sb.s_next_generation++;
+	inode->i_generation = EXT2_SB(sb)->s_next_generation++;
 	insert_inode_hash(inode);
 	mark_inode_dirty(inode);
 
@@ -457,8 +457,8 @@
 	int i;
 
 	lock_super (sb);
-	es = sb->u.ext2_sb.s_es;
-	for (i = 0; i < sb->u.ext2_sb.s_groups_count; i++) {
+	es = EXT2_SB(sb)->s_es;
+	for (i = 0; i < EXT2_SB(sb)->s_groups_count; i++) {
 		struct ext2_group_desc *desc = ext2_get_group_desc (sb, i, NULL);
 		struct buffer_head *bh;
 		unsigned x;
@@ -480,7 +480,7 @@
 	unlock_super (sb);
 	return desc_count;
 #else
-	return le32_to_cpu(sb->u.ext2_sb.s_es->s_free_inodes_count);
+	return le32_to_cpu(EXT2_SB(sb)->s_es->s_free_inodes_count);
 #endif
 }
 
@@ -488,11 +488,11 @@
 /* Called at mount-time, super-block is locked */
 void ext2_check_inodes_bitmap (struct super_block * sb)
 {
-	struct ext2_super_block * es = sb->u.ext2_sb.s_es;
+	struct ext2_super_block * es = EXT2_SB(sb)->s_es;
 	unsigned long desc_count = 0, bitmap_count = 0;
 	int i;
 
-	for (i = 0; i < sb->u.ext2_sb.s_groups_count; i++) {
+	for (i = 0; i < EXT2_SB(sb)->s_groups_count; i++) {
 		struct ext2_group_desc *desc = ext2_get_group_desc(sb, i, NULL);
 		struct buffer_head *bh;
 		unsigned x;
diff -Nru a/fs/ext2/inode.c b/fs/ext2/inode.c
--- a/fs/ext2/inode.c	Fri Mar 15 17:51:01 2002
+++ b/fs/ext2/inode.c	Fri Mar 15 17:51:01 2002
@@ -303,7 +303,7 @@
 	 * the same cylinder group then.
 	 */
 	return (ei->i_block_group * EXT2_BLOCKS_PER_GROUP(inode->i_sb)) +
-	       le32_to_cpu(inode->i_sb->u.ext2_sb.s_es->s_first_data_block);
+	       le32_to_cpu(EXT2_SB(inode->i_sb)->s_es->s_first_data_block);
 }
 
 /**
@@ -886,7 +886,7 @@
 	*p = NULL;
 	if ((ino != EXT2_ROOT_INO && ino != EXT2_ACL_IDX_INO &&
 	     ino != EXT2_ACL_DATA_INO && ino < EXT2_FIRST_INO(sb)) ||
-	    ino > le32_to_cpu(sb->u.ext2_sb.s_es->s_inodes_count))
+	    ino > le32_to_cpu(EXT2_SB(sb)->s_es->s_inodes_count))
 		goto Einval;
 
 	block_group = (ino - 1) / EXT2_INODES_PER_GROUP(sb);
diff -Nru a/fs/ext2/super.c b/fs/ext2/super.c
--- a/fs/ext2/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/ext2/super.c	Fri Mar 15 17:51:03 2002
@@ -37,10 +37,11 @@
 		 const char * fmt, ...)
 {
 	va_list args;
-	struct ext2_super_block *es = EXT2_SB(sb)->s_es;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
+	struct ext2_super_block *es = sbi->s_es;
 
 	if (!(sb->s_flags & MS_RDONLY)) {
-		sb->u.ext2_sb.s_mount_state |= EXT2_ERROR_FS;
+		sbi->s_mount_state |= EXT2_ERROR_FS;
 		es->s_state =
 			cpu_to_le16(le16_to_cpu(es->s_state) | EXT2_ERROR_FS);
 		ext2_sync_super(sb, es);
@@ -49,14 +50,14 @@
 	vsprintf (error_buf, fmt, args);
 	va_end (args);
 	if (test_opt (sb, ERRORS_PANIC) ||
-	    (le16_to_cpu(sb->u.ext2_sb.s_es->s_errors) == EXT2_ERRORS_PANIC &&
+	    (le16_to_cpu(sbi->s_es->s_errors) == EXT2_ERRORS_PANIC &&
 	     !test_opt (sb, ERRORS_CONT) && !test_opt (sb, ERRORS_RO)))
 		panic ("EXT2-fs panic (device %s): %s: %s\n",
 		       sb->s_id, function, error_buf);
 	printk (KERN_CRIT "EXT2-fs error (device %s): %s: %s\n",
 		sb->s_id, function, error_buf);
 	if (test_opt (sb, ERRORS_RO) ||
-	    (le16_to_cpu(sb->u.ext2_sb.s_es->s_errors) == EXT2_ERRORS_RO &&
+	    (le16_to_cpu(sbi->s_es->s_errors) == EXT2_ERRORS_RO &&
 	     !test_opt (sb, ERRORS_CONT) && !test_opt (sb, ERRORS_PANIC))) {
 		printk ("Remounting filesystem read-only\n");
 		sb->s_flags |= MS_RDONLY;
@@ -67,12 +68,13 @@
 			    const char * fmt, ...)
 {
 	va_list args;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
 
 	if (!(sb->s_flags & MS_RDONLY)) {
-		sb->u.ext2_sb.s_mount_state |= EXT2_ERROR_FS;
-		sb->u.ext2_sb.s_es->s_state =
-			cpu_to_le16(le16_to_cpu(sb->u.ext2_sb.s_es->s_state) | EXT2_ERROR_FS);
-		mark_buffer_dirty(sb->u.ext2_sb.s_sbh);
+		sbi->s_mount_state |= EXT2_ERROR_FS;
+		sbi->s_es->s_state =
+			cpu_to_le16(le16_to_cpu(sbi->s_es->s_state) | EXT2_ERROR_FS);
+		mark_buffer_dirty(sbi->s_sbh);
 		sb->s_dirt = 1;
 	}
 	va_start (args, fmt);
@@ -124,25 +126,28 @@
 {
 	int db_count;
 	int i;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
 
 	if (!(sb->s_flags & MS_RDONLY)) {
-		struct ext2_super_block *es = EXT2_SB(sb)->s_es;
+		struct ext2_super_block *es = sbi->s_es;
 
-		es->s_state = le16_to_cpu(EXT2_SB(sb)->s_mount_state);
+		es->s_state = le16_to_cpu(sbi->s_mount_state);
 		ext2_sync_super(sb, es);
 	}
-	db_count = EXT2_SB(sb)->s_gdb_count;
+	db_count = sbi->s_gdb_count;
 	for (i = 0; i < db_count; i++)
-		if (sb->u.ext2_sb.s_group_desc[i])
-			brelse (sb->u.ext2_sb.s_group_desc[i]);
-	kfree(sb->u.ext2_sb.s_group_desc);
+		if (sbi->s_group_desc[i])
+			brelse (sbi->s_group_desc[i]);
+	kfree(sbi->s_group_desc);
 	for (i = 0; i < EXT2_MAX_GROUP_LOADED; i++)
-		if (sb->u.ext2_sb.s_inode_bitmap[i])
-			brelse (sb->u.ext2_sb.s_inode_bitmap[i]);
+		if (sbi->s_inode_bitmap[i])
+			brelse (sbi->s_inode_bitmap[i]);
 	for (i = 0; i < EXT2_MAX_GROUP_LOADED; i++)
-		if (sb->u.ext2_sb.s_block_bitmap[i])
-			brelse (sb->u.ext2_sb.s_block_bitmap[i]);
-	brelse (sb->u.ext2_sb.s_sbh);
+		if (sbi->s_block_bitmap[i])
+			brelse (sbi->s_block_bitmap[i]);
+	brelse (sbi->s_sbh);
+	sb->u.generic_sbp = NULL;
+	kfree(sbi);
 
 	return;
 }
@@ -333,6 +338,8 @@
 			      int read_only)
 {
 	int res = 0;
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
+
 	if (le32_to_cpu(es->s_rev_level) > EXT2_MAX_SUPP_REV) {
 		printk ("EXT2-fs warning: revision level too high, "
 			"forcing read-only mode\n");
@@ -340,10 +347,10 @@
 	}
 	if (read_only)
 		return res;
-	if (!(sb->u.ext2_sb.s_mount_state & EXT2_VALID_FS))
+	if (!(sbi->s_mount_state & EXT2_VALID_FS))
 		printk ("EXT2-fs warning: mounting unchecked fs, "
 			"running e2fsck is recommended\n");
-	else if ((sb->u.ext2_sb.s_mount_state & EXT2_ERROR_FS))
+	else if ((sbi->s_mount_state & EXT2_ERROR_FS))
 		printk ("EXT2-fs warning: mounting fs with errors, "
 			"running e2fsck is recommended\n");
 	else if ((__s16) le16_to_cpu(es->s_max_mnt_count) >= 0 &&
@@ -363,11 +370,11 @@
 		printk ("[EXT II FS %s, %s, bs=%lu, fs=%lu, gc=%lu, "
 			"bpg=%lu, ipg=%lu, mo=%04lx]\n",
 			EXT2FS_VERSION, EXT2FS_DATE, sb->s_blocksize,
-			sb->u.ext2_sb.s_frag_size,
-			sb->u.ext2_sb.s_groups_count,
+			sbi->s_frag_size,
+			sbi->s_groups_count,
 			EXT2_BLOCKS_PER_GROUP(sb),
 			EXT2_INODES_PER_GROUP(sb),
-			sb->u.ext2_sb.s_mount_opt);
+			sbi->s_mount_opt);
 #ifdef CONFIG_EXT2_CHECK
 	if (test_opt (sb, CHECK)) {
 		ext2_check_blocks_bitmap (sb);
@@ -381,15 +388,16 @@
 {
 	int i;
 	int desc_block = 0;
-	unsigned long block = le32_to_cpu(sb->u.ext2_sb.s_es->s_first_data_block);
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
+	unsigned long block = le32_to_cpu(sbi->s_es->s_first_data_block);
 	struct ext2_group_desc * gdp = NULL;
 
 	ext2_debug ("Checking group descriptors");
 
-	for (i = 0; i < sb->u.ext2_sb.s_groups_count; i++)
+	for (i = 0; i < sbi->s_groups_count; i++)
 	{
 		if ((i % EXT2_DESC_PER_BLOCK(sb)) == 0)
-			gdp = (struct ext2_group_desc *) sb->u.ext2_sb.s_group_desc[desc_block++]->b_data;
+			gdp = (struct ext2_group_desc *) sbi->s_group_desc[desc_block++]->b_data;
 		if (le32_to_cpu(gdp->bg_block_bitmap) < block ||
 		    le32_to_cpu(gdp->bg_block_bitmap) >= block + EXT2_BLOCKS_PER_GROUP(sb))
 		{
@@ -409,7 +417,7 @@
 			return 0;
 		}
 		if (le32_to_cpu(gdp->bg_inode_table) < block ||
-		    le32_to_cpu(gdp->bg_inode_table) + sb->u.ext2_sb.s_itb_per_group >=
+		    le32_to_cpu(gdp->bg_inode_table) + sbi->s_itb_per_group >=
 		    block + EXT2_BLOCKS_PER_GROUP(sb))
 		{
 			ext2_error (sb, "ext2_check_descriptors",
@@ -446,6 +454,7 @@
 static int ext2_fill_super(struct super_block *sb, void *data, int silent)
 {
 	struct buffer_head * bh;
+	struct ext2_sb_info * sbi;
 	struct ext2_super_block * es;
 	unsigned long sb_block = 1;
 	unsigned short resuid = EXT2_DEF_RESUID;
@@ -456,6 +465,12 @@
 	int db_count;
 	int i, j;
 
+	sbi = kmalloc(sizeof(struct ext2_super_block), GFP_KERNEL);
+	if (!sbi)
+		return -ENOMEM;
+	sb->u.generic_sbp = sbi;
+	memset(sbi, 0, sizeof(struct ext2_super_block));
+
 	/*
 	 * See what the current blocksize for the device is, and
 	 * use that as the blocksize.  Otherwise (or if the blocksize
@@ -464,15 +479,15 @@
 	 * sectorsize that is larger than the default.
 	 */
 
-	sb->u.ext2_sb.s_mount_opt = 0;
+	sbi->s_mount_opt = 0;
 	if (!parse_options ((char *) data, &sb_block, &resuid, &resgid,
-	    &sb->u.ext2_sb.s_mount_opt))
-		return -EINVAL;
+	    &sbi->s_mount_opt))
+		goto failed_sbi;
 
 	blocksize = sb_min_blocksize(sb, BLOCK_SIZE);
 	if (!blocksize) {
 		printk ("EXT2-fs: unable to set blocksize\n");
-		return -EINVAL;
+		goto failed_sbi;
 	}
 
 	/*
@@ -487,14 +502,14 @@
 
 	if (!(bh = sb_bread(sb, logic_sb_block))) {
 		printk ("EXT2-fs: unable to read superblock\n");
-		return -EINVAL;
+		goto failed_sbi;
 	}
 	/*
 	 * Note: s_es must be initialized as soon as possible because
 	 *       some ext2 macro-instructions depend on its value
 	 */
 	es = (struct ext2_super_block *) (((char *)bh->b_data) + offset);
-	sb->u.ext2_sb.s_es = es;
+	sbi->s_es = es;
 	sb->s_magic = le16_to_cpu(es->s_magic);
 	if (sb->s_magic != EXT2_SUPER_MAGIC) {
 		if (!silent)
@@ -526,14 +541,14 @@
 		       sb->s_id, i);
 		goto failed_mount;
 	}
-	blocksize = BLOCK_SIZE << le32_to_cpu(EXT2_SB(sb)->s_es->s_log_block_size);
+	blocksize = BLOCK_SIZE << le32_to_cpu(sbi->s_es->s_log_block_size);
 	/* If the blocksize doesn't match, re-read the thing.. */
 	if (sb->s_blocksize != blocksize) {
 		brelse(bh);
 
 		if (!sb_set_blocksize(sb, blocksize)) {
 			printk(KERN_ERR "EXT2-fs: blocksize too small for device.\n");
-			return -EINVAL;
+			goto failed_sbi;
 		}
 
 		logic_sb_block = (sb_block*BLOCK_SIZE) / blocksize;
@@ -545,7 +560,7 @@
 			goto failed_mount;
 		}
 		es = (struct ext2_super_block *) (((char *)bh->b_data) + offset);
-		sb->u.ext2_sb.s_es = es;
+		sbi->s_es = es;
 		if (es->s_magic != le16_to_cpu(EXT2_SUPER_MAGIC)) {
 			printk ("EXT2-fs: Magic mismatch, very weird !\n");
 			goto failed_mount;
@@ -555,46 +570,46 @@
 	sb->s_maxbytes = ext2_max_size(sb->s_blocksize_bits);
 
 	if (le32_to_cpu(es->s_rev_level) == EXT2_GOOD_OLD_REV) {
-		sb->u.ext2_sb.s_inode_size = EXT2_GOOD_OLD_INODE_SIZE;
-		sb->u.ext2_sb.s_first_ino = EXT2_GOOD_OLD_FIRST_INO;
+		sbi->s_inode_size = EXT2_GOOD_OLD_INODE_SIZE;
+		sbi->s_first_ino = EXT2_GOOD_OLD_FIRST_INO;
 	} else {
-		sb->u.ext2_sb.s_inode_size = le16_to_cpu(es->s_inode_size);
-		sb->u.ext2_sb.s_first_ino = le32_to_cpu(es->s_first_ino);
-		if (sb->u.ext2_sb.s_inode_size != EXT2_GOOD_OLD_INODE_SIZE) {
+		sbi->s_inode_size = le16_to_cpu(es->s_inode_size);
+		sbi->s_first_ino = le32_to_cpu(es->s_first_ino);
+		if (sbi->s_inode_size != EXT2_GOOD_OLD_INODE_SIZE) {
 			printk ("EXT2-fs: unsupported inode size: %d\n",
-				sb->u.ext2_sb.s_inode_size);
+				sbi->s_inode_size);
 			goto failed_mount;
 		}
 	}
-	sb->u.ext2_sb.s_frag_size = EXT2_MIN_FRAG_SIZE <<
+	sbi->s_frag_size = EXT2_MIN_FRAG_SIZE <<
 				   le32_to_cpu(es->s_log_frag_size);
-	if (sb->u.ext2_sb.s_frag_size)
-		sb->u.ext2_sb.s_frags_per_block = sb->s_blocksize /
-						  sb->u.ext2_sb.s_frag_size;
+	if (sbi->s_frag_size)
+		sbi->s_frags_per_block = sb->s_blocksize /
+						  sbi->s_frag_size;
 	else
 		sb->s_magic = 0;
-	sb->u.ext2_sb.s_blocks_per_group = le32_to_cpu(es->s_blocks_per_group);
-	sb->u.ext2_sb.s_frags_per_group = le32_to_cpu(es->s_frags_per_group);
-	sb->u.ext2_sb.s_inodes_per_group = le32_to_cpu(es->s_inodes_per_group);
-	sb->u.ext2_sb.s_inodes_per_block = sb->s_blocksize /
+	sbi->s_blocks_per_group = le32_to_cpu(es->s_blocks_per_group);
+	sbi->s_frags_per_group = le32_to_cpu(es->s_frags_per_group);
+	sbi->s_inodes_per_group = le32_to_cpu(es->s_inodes_per_group);
+	sbi->s_inodes_per_block = sb->s_blocksize /
 					   EXT2_INODE_SIZE(sb);
-	sb->u.ext2_sb.s_itb_per_group = sb->u.ext2_sb.s_inodes_per_group /
-				        sb->u.ext2_sb.s_inodes_per_block;
-	sb->u.ext2_sb.s_desc_per_block = sb->s_blocksize /
+	sbi->s_itb_per_group = sbi->s_inodes_per_group /
+				        sbi->s_inodes_per_block;
+	sbi->s_desc_per_block = sb->s_blocksize /
 					 sizeof (struct ext2_group_desc);
-	sb->u.ext2_sb.s_sbh = bh;
+	sbi->s_sbh = bh;
 	if (resuid != EXT2_DEF_RESUID)
-		sb->u.ext2_sb.s_resuid = resuid;
+		sbi->s_resuid = resuid;
 	else
-		sb->u.ext2_sb.s_resuid = le16_to_cpu(es->s_def_resuid);
+		sbi->s_resuid = le16_to_cpu(es->s_def_resuid);
 	if (resgid != EXT2_DEF_RESGID)
-		sb->u.ext2_sb.s_resgid = resgid;
+		sbi->s_resgid = resgid;
 	else
-		sb->u.ext2_sb.s_resgid = le16_to_cpu(es->s_def_resgid);
-	sb->u.ext2_sb.s_mount_state = le16_to_cpu(es->s_state);
-	sb->u.ext2_sb.s_addr_per_block_bits =
+		sbi->s_resgid = le16_to_cpu(es->s_def_resgid);
+	sbi->s_mount_state = le16_to_cpu(es->s_state);
+	sbi->s_addr_per_block_bits =
 		log2 (EXT2_ADDR_PER_BLOCK(sb));
-	sb->u.ext2_sb.s_desc_per_block_bits =
+	sbi->s_desc_per_block_bits =
 		log2 (EXT2_DESC_PER_BLOCK(sb));
 	if (sb->s_magic != EXT2_SUPER_MAGIC) {
 		if (!silent)
@@ -610,45 +625,45 @@
 		goto failed_mount;
 	}
 
-	if (sb->s_blocksize != sb->u.ext2_sb.s_frag_size) {
+	if (sb->s_blocksize != sbi->s_frag_size) {
 		printk ("EXT2-fs: fragsize %lu != blocksize %lu (not supported yet)\n",
-			sb->u.ext2_sb.s_frag_size, sb->s_blocksize);
+			sbi->s_frag_size, sb->s_blocksize);
 		goto failed_mount;
 	}
 
-	if (sb->u.ext2_sb.s_blocks_per_group > sb->s_blocksize * 8) {
+	if (sbi->s_blocks_per_group > sb->s_blocksize * 8) {
 		printk ("EXT2-fs: #blocks per group too big: %lu\n",
-			sb->u.ext2_sb.s_blocks_per_group);
+			sbi->s_blocks_per_group);
 		goto failed_mount;
 	}
-	if (sb->u.ext2_sb.s_frags_per_group > sb->s_blocksize * 8) {
+	if (sbi->s_frags_per_group > sb->s_blocksize * 8) {
 		printk ("EXT2-fs: #fragments per group too big: %lu\n",
-			sb->u.ext2_sb.s_frags_per_group);
+			sbi->s_frags_per_group);
 		goto failed_mount;
 	}
-	if (sb->u.ext2_sb.s_inodes_per_group > sb->s_blocksize * 8) {
+	if (sbi->s_inodes_per_group > sb->s_blocksize * 8) {
 		printk ("EXT2-fs: #inodes per group too big: %lu\n",
-			sb->u.ext2_sb.s_inodes_per_group);
+			sbi->s_inodes_per_group);
 		goto failed_mount;
 	}
 
-	sb->u.ext2_sb.s_groups_count = (le32_to_cpu(es->s_blocks_count) -
+	sbi->s_groups_count = (le32_to_cpu(es->s_blocks_count) -
 				        le32_to_cpu(es->s_first_data_block) +
 				       EXT2_BLOCKS_PER_GROUP(sb) - 1) /
 				       EXT2_BLOCKS_PER_GROUP(sb);
-	db_count = (sb->u.ext2_sb.s_groups_count + EXT2_DESC_PER_BLOCK(sb) - 1) /
+	db_count = (sbi->s_groups_count + EXT2_DESC_PER_BLOCK(sb) - 1) /
 		   EXT2_DESC_PER_BLOCK(sb);
-	sb->u.ext2_sb.s_group_desc = kmalloc (db_count * sizeof (struct buffer_head *), GFP_KERNEL);
-	if (sb->u.ext2_sb.s_group_desc == NULL) {
+	sbi->s_group_desc = kmalloc (db_count * sizeof (struct buffer_head *), GFP_KERNEL);
+	if (sbi->s_group_desc == NULL) {
 		printk ("EXT2-fs: not enough memory\n");
 		goto failed_mount;
 	}
 	for (i = 0; i < db_count; i++) {
-		sb->u.ext2_sb.s_group_desc[i] = sb_bread(sb, logic_sb_block + i + 1);
-		if (!sb->u.ext2_sb.s_group_desc[i]) {
+		sbi->s_group_desc[i] = sb_bread(sb, logic_sb_block + i + 1);
+		if (!sbi->s_group_desc[i]) {
 			for (j = 0; j < i; j++)
-				brelse (sb->u.ext2_sb.s_group_desc[j]);
-			kfree(sb->u.ext2_sb.s_group_desc);
+				brelse (sbi->s_group_desc[j]);
+			kfree(sbi->s_group_desc);
 			printk ("EXT2-fs: unable to read group descriptors\n");
 			goto failed_mount;
 		}
@@ -659,15 +674,15 @@
 		goto failed_mount2;
 	}
 	for (i = 0; i < EXT2_MAX_GROUP_LOADED; i++) {
-		sb->u.ext2_sb.s_inode_bitmap_number[i] = 0;
-		sb->u.ext2_sb.s_inode_bitmap[i] = NULL;
-		sb->u.ext2_sb.s_block_bitmap_number[i] = 0;
-		sb->u.ext2_sb.s_block_bitmap[i] = NULL;
-	}
-	sb->u.ext2_sb.s_loaded_inode_bitmaps = 0;
-	sb->u.ext2_sb.s_loaded_block_bitmaps = 0;
-	sb->u.ext2_sb.s_gdb_count = db_count;
-	get_random_bytes(&sb->u.ext2_sb.s_next_generation, sizeof(u32));
+		sbi->s_inode_bitmap_number[i] = 0;
+		sbi->s_inode_bitmap[i] = NULL;
+		sbi->s_block_bitmap_number[i] = 0;
+		sbi->s_block_bitmap[i] = NULL;
+	}
+	sbi->s_loaded_inode_bitmaps = 0;
+	sbi->s_loaded_block_bitmaps = 0;
+	sbi->s_gdb_count = db_count;
+	get_random_bytes(&sbi->s_next_generation, sizeof(u32));
 	/*
 	 * set up enough so that it can read an inode
 	 */
@@ -687,10 +702,13 @@
 	return 0;
 failed_mount2:
 	for (i = 0; i < db_count; i++)
-		brelse(sb->u.ext2_sb.s_group_desc[i]);
-	kfree(sb->u.ext2_sb.s_group_desc);
+		brelse(sbi->s_group_desc[i]);
+	kfree(sbi->s_group_desc);
 failed_mount:
 	brelse(bh);
+failed_sbi:
+	sb->u.generic_sbp = NULL;
+	kfree(sbi);
 	return -EINVAL;
 }
 
@@ -698,7 +716,7 @@
 			       struct ext2_super_block * es)
 {
 	es->s_wtime = cpu_to_le32(CURRENT_TIME);
-	mark_buffer_dirty(sb->u.ext2_sb.s_sbh);
+	mark_buffer_dirty(EXT2_SB(sb)->s_sbh);
 	sb->s_dirt = 0;
 }
 
@@ -727,7 +745,7 @@
 	struct ext2_super_block * es;
 
 	if (!(sb->s_flags & MS_RDONLY)) {
-		es = sb->u.ext2_sb.s_es;
+		es = EXT2_SB(sb)->s_es;
 
 		if (le16_to_cpu(es->s_state) & EXT2_VALID_FS) {
 			ext2_debug ("setting valid to 0\n");
@@ -743,35 +761,36 @@
 
 int ext2_remount (struct super_block * sb, int * flags, char * data)
 {
+	struct ext2_sb_info * sbi = EXT2_SB(sb);
 	struct ext2_super_block * es;
-	unsigned short resuid = sb->u.ext2_sb.s_resuid;
-	unsigned short resgid = sb->u.ext2_sb.s_resgid;
+	unsigned short resuid = sbi->s_resuid;
+	unsigned short resgid = sbi->s_resgid;
 	unsigned long new_mount_opt;
 	unsigned long tmp;
 
 	/*
 	 * Allow the "check" option to be passed as a remount option.
 	 */
-	new_mount_opt = sb->u.ext2_sb.s_mount_opt;
+	new_mount_opt = sbi->s_mount_opt;
 	if (!parse_options (data, &tmp, &resuid, &resgid,
 			    &new_mount_opt))
 		return -EINVAL;
 
-	sb->u.ext2_sb.s_mount_opt = new_mount_opt;
-	sb->u.ext2_sb.s_resuid = resuid;
-	sb->u.ext2_sb.s_resgid = resgid;
-	es = sb->u.ext2_sb.s_es;
+	sbi->s_mount_opt = new_mount_opt;
+	sbi->s_resuid = resuid;
+	sbi->s_resgid = resgid;
+	es = sbi->s_es;
 	if ((*flags & MS_RDONLY) == (sb->s_flags & MS_RDONLY))
 		return 0;
 	if (*flags & MS_RDONLY) {
 		if (le16_to_cpu(es->s_state) & EXT2_VALID_FS ||
-		    !(sb->u.ext2_sb.s_mount_state & EXT2_VALID_FS))
+		    !(sbi->s_mount_state & EXT2_VALID_FS))
 			return 0;
 		/*
 		 * OK, we are remounting a valid rw partition rdonly, so set
 		 * the rdonly flag and then mark the partition as valid again.
 		 */
-		es->s_state = cpu_to_le16(sb->u.ext2_sb.s_mount_state);
+		es->s_state = cpu_to_le16(sbi->s_mount_state);
 		es->s_mtime = cpu_to_le32(CURRENT_TIME);
 	} else {
 		int ret;
@@ -787,7 +806,7 @@
 		 * store the current valid flag.  (It may have been changed
 		 * by e2fsck since we originally mounted the partition.)
 		 */
-		sb->u.ext2_sb.s_mount_state = le16_to_cpu(es->s_state);
+		sbi->s_mount_state = le16_to_cpu(es->s_state);
 		if (!ext2_setup_super (sb, es, 0))
 			sb->s_flags &= ~MS_RDONLY;
 	}
@@ -797,6 +816,7 @@
 
 int ext2_statfs (struct super_block * sb, struct statfs * buf)
 {
+	struct ext2_sb_info *sbi = EXT2_SB(sb);
 	unsigned long overhead;
 	int i;
 
@@ -811,14 +831,14 @@
 		 * All of the blocks before first_data_block are
 		 * overhead
 		 */
-		overhead = le32_to_cpu(sb->u.ext2_sb.s_es->s_first_data_block);
+		overhead = le32_to_cpu(sbi->s_es->s_first_data_block);
 
 		/*
 		 * Add the overhead attributed to the superblock and
 		 * block group descriptors.  If the sparse superblocks
 		 * feature is turned on, then not all groups have this.
 		 */
-		for (i = 0; i < EXT2_SB(sb)->s_groups_count; i++)
+		for (i = 0; i < sbi->s_groups_count; i++)
 			overhead += ext2_bg_has_super(sb, i) +
 				ext2_bg_num_gdb(sb, i);
 
@@ -826,18 +846,18 @@
 		 * Every block group has an inode bitmap, a block
 		 * bitmap, and an inode table.
 		 */
-		overhead += (sb->u.ext2_sb.s_groups_count *
-			     (2 + sb->u.ext2_sb.s_itb_per_group));
+		overhead += (sbi->s_groups_count *
+			     (2 + sbi->s_itb_per_group));
 	}
 
 	buf->f_type = EXT2_SUPER_MAGIC;
 	buf->f_bsize = sb->s_blocksize;
-	buf->f_blocks = le32_to_cpu(sb->u.ext2_sb.s_es->s_blocks_count) - overhead;
+	buf->f_blocks = le32_to_cpu(sbi->s_es->s_blocks_count) - overhead;
 	buf->f_bfree = ext2_count_free_blocks (sb);
-	buf->f_bavail = buf->f_bfree - le32_to_cpu(sb->u.ext2_sb.s_es->s_r_blocks_count);
-	if (buf->f_bfree < le32_to_cpu(sb->u.ext2_sb.s_es->s_r_blocks_count))
+	buf->f_bavail = buf->f_bfree - le32_to_cpu(sbi->s_es->s_r_blocks_count);
+	if (buf->f_bfree < le32_to_cpu(sbi->s_es->s_r_blocks_count))
 		buf->f_bavail = 0;
-	buf->f_files = le32_to_cpu(sb->u.ext2_sb.s_es->s_inodes_count);
+	buf->f_files = le32_to_cpu(sbi->s_es->s_inodes_count);
 	buf->f_ffree = ext2_count_free_inodes (sb);
 	buf->f_namelen = EXT2_NAME_LEN;
 	return 0;
@@ -853,6 +873,7 @@
 	owner:		THIS_MODULE,
 	name:		"ext2",
 	get_sb:		ext2_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/ext3/super.c b/fs/ext3/super.c
--- a/fs/ext3/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/ext3/super.c	Fri Mar 15 17:51:03 2002
@@ -1778,6 +1778,7 @@
 	owner:		THIS_MODULE,
 	name:		"ext3",
 	get_sb:		ext3_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/fat/fatfs_syms.c b/fs/fat/fatfs_syms.c
--- a/fs/fat/fatfs_syms.c	Fri Mar 15 17:51:01 2002
+++ b/fs/fat/fatfs_syms.c	Fri Mar 15 17:51:01 2002
@@ -24,7 +24,7 @@
 EXPORT_SYMBOL(fat_attach);
 EXPORT_SYMBOL(fat_detach);
 EXPORT_SYMBOL(fat_build_inode);
-EXPORT_SYMBOL(fat_read_super);
+EXPORT_SYMBOL(fat_fill_super);
 EXPORT_SYMBOL(fat_search_long);
 EXPORT_SYMBOL(fat_readdir);
 EXPORT_SYMBOL(fat_scan);
diff -Nru a/fs/fat/inode.c b/fs/fat/inode.c
--- a/fs/fat/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/fat/inode.c	Fri Mar 15 17:51:03 2002
@@ -167,32 +167,36 @@
 
 void fat_put_super(struct super_block *sb)
 {
-	if (MSDOS_SB(sb)->cvf_format->cvf_version) {
-		dec_cvf_format_use_count_by_version(MSDOS_SB(sb)->cvf_format->cvf_version);
-		MSDOS_SB(sb)->cvf_format->unmount_cvf(sb);
+	struct msdos_sb_info *sbi = MSDOS_SB(sb);
+
+	if (sbi->cvf_format->cvf_version) {
+		dec_cvf_format_use_count_by_version(sbi->cvf_format->cvf_version);
+		sbi->cvf_format->unmount_cvf(sb);
 	}
-	if (MSDOS_SB(sb)->fat_bits == 32) {
+	if (sbi->fat_bits == 32) {
 		fat_clusters_flush(sb);
 	}
 	fat_cache_inval_dev(sb);
 	set_blocksize (sb->s_dev,BLOCK_SIZE);
-	if (MSDOS_SB(sb)->nls_disk) {
-		unload_nls(MSDOS_SB(sb)->nls_disk);
-		MSDOS_SB(sb)->nls_disk = NULL;
-		MSDOS_SB(sb)->options.codepage = 0;
-	}
-	if (MSDOS_SB(sb)->nls_io) {
-		unload_nls(MSDOS_SB(sb)->nls_io);
-		MSDOS_SB(sb)->nls_io = NULL;
+	if (sbi->nls_disk) {
+		unload_nls(sbi->nls_disk);
+		sbi->nls_disk = NULL;
+		sbi->options.codepage = 0;
+	}
+	if (sbi->nls_io) {
+		unload_nls(sbi->nls_io);
+		sbi->nls_io = NULL;
 	}
 	/*
 	 * Note: the iocharset option might have been specified
 	 * without enabling nls_io, so check for it here.
 	 */
-	if (MSDOS_SB(sb)->options.iocharset) {
-		kfree(MSDOS_SB(sb)->options.iocharset);
-		MSDOS_SB(sb)->options.iocharset = NULL;
+	if (sbi->options.iocharset) {
+		kfree(sbi->options.iocharset);
+		sbi->options.iocharset = NULL;
 	}
+	sb->u.generic_sbp = NULL;
+	kfree(sbi);
 }
 
 
@@ -582,18 +586,14 @@
 
 /*
  * Read the super block of an MS-DOS FS.
- *
- * Note that this may be called from vfat_read_super
- * with some fields already initialized.
  */
-struct super_block *
-fat_read_super(struct super_block *sb, void *data, int silent,
-		struct inode_operations *fs_dir_inode_ops)
+int fat_fill_super(struct super_block *sb, void *data, int silent,
+		   struct inode_operations *fs_dir_inode_ops, int isvfat)
 {
 	struct inode *root_inode;
 	struct buffer_head *bh;
 	struct fat_boot_sector *b;
-	struct msdos_sb_info *sbi = MSDOS_SB(sb);
+	struct msdos_sb_info *sbi;
 	int logical_sector_size, fat_clusters, debug, cp;
 	unsigned int total_sectors, rootdir_sectors;
 	long error = -EIO;
@@ -602,12 +602,19 @@
 	char cvf_format[21];
 	char cvf_options[101];
 
+	sbi = kmalloc(sizeof(struct msdos_sb_info), GFP_KERNEL);
+	if (!sbi)
+		return -ENOMEM;
+	sb->u.generic_sbp = sbi;
+	memset(sbi, 0, sizeof(struct msdos_sb_info));
+
 	cvf_format[0] = '\0';
 	cvf_options[0] = '\0';
 	sbi->private_data = NULL;
 
 	sb->s_magic = MSDOS_SUPER_MAGIC;
 	sb->s_op = &fat_sops;
+	sbi->options.isvfat = isvfat;
 	sbi->dir_ops = fs_dir_inode_ops;
 	sbi->cvf_format = &default_cvf;
 
@@ -830,10 +837,10 @@
 		sbi->cvf_format = cvf_formats[i];
 		++cvf_format_use_count[i];
 	}
-	return sb;
+	return 0;
 
 out_invalid:
-	error = 0;
+	error = -EINVAL;
 
 out_fail:
 	if (sbi->nls_io)
@@ -845,8 +852,10 @@
 	if (sbi->private_data)
 		kfree(sbi->private_data);
 	sbi->private_data = NULL;
+	sb->u.generic_sbp = NULL;
+	kfree(sbi);
 
-	return ERR_PTR(error);
+	return error;
 }
 
 int fat_statfs(struct super_block *sb,struct statfs *buf)
diff -Nru a/fs/filesystems.c b/fs/filesystems.c
--- a/fs/filesystems.c	Fri Mar 15 17:51:03 2002
+++ b/fs/filesystems.c	Fri Mar 15 17:51:03 2002
@@ -3,39 +3,10 @@
  *
  *  Copyright (C) 1991, 1992  Linus Torvalds
  *
- *  nfsservctl system-call when nfsd is not compiled in.
+ *  table of configured filesystems
  */
 
-#include <linux/config.h>
-#include <linux/module.h>
-#include <linux/time.h>
-#include <linux/smp_lock.h>
-#include <linux/kmod.h>
-#include <linux/nfsd/interface.h>
-#include <linux/linkage.h>
-
-#if ! defined(CONFIG_NFSD)
-struct nfsd_linkage *nfsd_linkage;
-
-long
-asmlinkage sys_nfsservctl(int cmd, void *argp, void *resp)
-{
-	int ret = -ENOSYS;
-	
-#if defined(CONFIG_MODULES)
-	lock_kernel();
-
-	if (nfsd_linkage ||
-	    (request_module ("nfsd") == 0 && nfsd_linkage)) {
-		__MOD_INC_USE_COUNT(nfsd_linkage->owner);
-		unlock_kernel();
-		ret = nfsd_linkage->do_nfsservctl(cmd, argp, resp);
-		__MOD_DEC_USE_COUNT(nfsd_linkage->owner);
-	} else
-		unlock_kernel();
-#endif
-	return ret;
-}
-EXPORT_SYMBOL(nfsd_linkage);
-
-#endif /* CONFIG_NFSD */
+/*
+ * Code will move here from fs/super.c and yes, it will be fs type handling
+ * stuff.
+ */
diff -Nru a/fs/freevxfs/vxfs_super.c b/fs/freevxfs/vxfs_super.c
--- a/fs/freevxfs/vxfs_super.c	Fri Mar 15 17:51:02 2002
+++ b/fs/freevxfs/vxfs_super.c	Fri Mar 15 17:51:02 2002
@@ -237,6 +237,7 @@
 	owner:		THIS_MODULE,
 	name:		"vxfs",
 	get_sb:		vxfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/hfs/super.c b/fs/hfs/super.c
--- a/fs/hfs/super.c	Fri Mar 15 17:51:02 2002
+++ b/fs/hfs/super.c	Fri Mar 15 17:51:02 2002
@@ -105,6 +105,7 @@
 	owner:		THIS_MODULE,
 	name:		"hfs",
 	get_sb:		hfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/hpfs/super.c b/fs/hpfs/super.c
--- a/fs/hpfs/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/hpfs/super.c	Fri Mar 15 17:51:03 2002
@@ -619,6 +619,7 @@
 	owner:		THIS_MODULE,
 	name:		"hpfs",
 	get_sb:		hpfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/inode.c b/fs/inode.c
--- a/fs/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/inode.c	Fri Mar 15 17:51:03 2002
@@ -467,8 +467,7 @@
 
 	if (sb) {
 		spin_lock(&inode_lock);
-		while (inode->i_state & I_DIRTY)
-			sync_one(inode, sync);
+		sync_one(inode, sync);
 		spin_unlock(&inode_lock);
 		if (sync)
 			wait_on_inode(inode);
diff -Nru a/fs/intermezzo/journal_ext2.c b/fs/intermezzo/journal_ext2.c
--- a/fs/intermezzo/journal_ext2.c	Fri Mar 15 17:51:02 2002
+++ b/fs/intermezzo/journal_ext2.c	Fri Mar 15 17:51:02 2002
@@ -27,8 +27,8 @@
 static loff_t presto_e2_freespace(struct presto_cache *cache,
                                          struct super_block *sb)
 {
-        unsigned long freebl = le32_to_cpu(sb->u.ext2_sb.s_es->s_free_blocks_count);
-        unsigned long avail =   freebl - le32_to_cpu(sb->u.ext2_sb.s_es->s_r_blocks_count);
+        unsigned long freebl = le32_to_cpu(EXT2_SB(sb)->s_es->s_free_blocks_count);
+        unsigned long avail =   freebl - le32_to_cpu(EXT2_SB(sb)->s_es->s_r_blocks_count);
 	return (avail <<  EXT2_BLOCK_SIZE_BITS(sb));
 }
 
@@ -41,7 +41,7 @@
              strcmp(fset->fset_cache->cache_type, "ext2"))
                 return NULL;
 
-        avail_kmlblocks = inode->i_sb->u.ext2_sb.s_es->s_free_blocks_count;
+        avail_kmlblocks = EXT2_SB(inode->i_sb)->s_es->s_free_blocks_count;
         
         if ( avail_kmlblocks < 3 ) {
                 return ERR_PTR(-ENOSPC);
diff -Nru a/fs/isofs/inode.c b/fs/isofs/inode.c
--- a/fs/isofs/inode.c	Fri Mar 15 17:51:04 2002
+++ b/fs/isofs/inode.c	Fri Mar 15 17:51:04 2002
@@ -1404,6 +1404,7 @@
 	owner:		THIS_MODULE,
 	name:		"iso9660",
 	get_sb:		isofs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/jffs/inode-v23.c b/fs/jffs/inode-v23.c
--- a/fs/jffs/inode-v23.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs/inode-v23.c	Fri Mar 15 17:51:01 2002
@@ -1763,6 +1763,7 @@
 	owner:		THIS_MODULE,
 	name:		"jffs",
 	get_sb:		jffs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/jffs2/Makefile b/fs/jffs2/Makefile
--- a/fs/jffs2/Makefile	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/Makefile	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 #
 # Makefile for the linux Journalling Flash FileSystem (JFFS) routines.
 #
-# $Id: Makefile,v 1.25 2001/09/25 20:59:41 dwmw2 Exp $
+# $Id: Makefile,v 1.34 2002/03/08 11:27:59 dwmw2 Exp $
 #
 # Note! Dependencies are done automagically by 'make dep', which also
 # removes any old dependencies. DON'T put your own dependencies here
@@ -10,15 +10,20 @@
 # Note 2! The CFLAGS definitions are now in the main makefile...
 
 
-COMPR_OBJS	:= compr.o compr_rubin.o compr_rtime.o pushpull.o \
-			compr_zlib.o
+COMPR_OBJS	:= compr.o compr_rubin.o compr_rtime.o compr_zlib.o
 JFFS2_OBJS	:= dir.o file.o ioctl.o nodelist.o malloc.o \
-	read.o nodemgmt.o readinode.o super.o write.o scan.o gc.o \
-	symlink.o build.o erase.o background.o
+	read.o nodemgmt.o readinode.o write.o scan.o gc.o \
+	symlink.o build.o erase.o background.o fs.o writev.o
+
+LINUX_OBJS-24	:= super-v24.o crc32.o
+LINUX_OBJS-25	:= super.o
+
+NAND_OBJS-$(CONFIG_JFFS2_FS_NAND)	:= wbuf.o
 
 O_TARGET := jffs2.o
 
-obj-y := $(COMPR_OBJS) $(JFFS2_OBJS)
+obj-y := $(COMPR_OBJS) $(JFFS2_OBJS) $(VERS_OBJS) $(NAND_OBJS-y) \
+	$(LINUX_OBJS-$(VERSION)$(PATCHLEVEL))
 obj-m := $(O_TARGET)
 
 include $(TOPDIR)/Rules.make
diff -Nru a/fs/jffs2/README.Locking b/fs/jffs2/README.Locking
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/jffs2/README.Locking	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,116 @@
+	$Id: README.Locking,v 1.4 2002/03/08 16:20:06 dwmw2 Exp $
+
+	JFFS2 LOCKING DOCUMENTATION
+	---------------------------
+
+At least theoretically, JFFS2 does not require the Big Kernel Lock
+(BKL), which was always helpfully obtained for it by Linux 2.4 VFS
+code. It has its own locking, as described below.
+
+This document attempts to describe the existing locking rules for
+JFFS2. It is not expected to remain perfectly up to date, but ought to
+be fairly close.
+
+
+	alloc_sem
+	---------
+
+The alloc_sem is a per-filesystem semaphore, used primarily to ensure
+contiguous allocation of space on the medium. It is automatically
+obtained during space allocations (jffs2_reserve_space()) and freed
+upon write completion (jffs2_complete_reservation()). Note that
+the garbage collector will obtain this right at the beginning of
+jffs2_garbage_collect_pass() and release it at the end, thereby
+preventing any other write activity on the file system during a
+garbage collect pass.
+
+When writing new nodes, the alloc_sem must be held until the new nodes
+have been properly linked into the data structures for the inode to
+which they belong. This is for the benefit of NAND flash - adding new
+nodes to an inode may obsolete old ones, and by holding the alloc_sem
+until this happens we ensure that any data in the write-buffer at the
+time this happens are part of the new node, not just something that
+was written afterwards. Hence, we can ensure the newly-obsoleted nodes
+don't actually get erased until the write-buffer has been flushed to
+the medium.
+
+With the introduction of NAND flash support and the write-buffer, 
+the alloc_sem is also used to protect the wbuf-related members of the
+jffs2_sb_info structure. Atomically reading the wbuf_len member to see
+if the wbuf is currently holding any data is permitted, though.
+
+Ordering constraints: See f->sem.
+
+
+	File Semaphore f->sem
+	---------------------
+
+This is the JFFS2-internal equivalent of the inode semaphore i->i_sem.
+It protects the contents of the jffs2_inode_info private inode data,
+including the linked list of node fragments (but see the notes below on
+erase_completion_lock), etc.
+
+The reason that the i_sem itself isn't used for this purpose is to
+avoid deadlocks with garbage collection -- the VFS will lock the i_sem
+before calling a function which may need to allocate space. The
+allocation may trigger garbage-collection, which may need to move a
+node belonging to the inode which was locked in the first place by the
+VFS. If the garbage collection code were to attempt to lock the i_sem
+of the inode from which it's garbage-collecting a physical node, this
+lead to deadlock, unless we played games with unlocking the i_sem
+before calling the space allocation functions.
+
+Instead of playing such games, we just have an extra internal
+semaphore, which is obtained by the garbage collection code and also
+by the normal file system code _after_ allocation of space.
+
+Ordering constraints: 
+
+	1. Never attempt to allocate space or lock alloc_sem with 
+	   any f->sem held.
+	2. Never attempt to lock two file semaphores in one thread.
+	   No ordering rules have been made for doing so.
+
+
+	erase_completion_lock spinlock
+	------------------------------
+
+This is used to serialise access to the eraseblock lists, to the
+per-eraseblock lists of physical jffs2_raw_node_ref structures, and
+(NB) the per-inode list of physical nodes. The latter is a special
+case - see below.
+
+As the MTD API permits erase-completion callback functions to be
+called from bottom-half (timer) context, and these functions access
+the data structures protected by this lock, it must be locked with
+spin_lock_bh().
+
+Note that the per-inode list of physical nodes (f->nodes) is a special
+case. Any changes to _valid_ nodes (i.e. ->flash_offset & 1 == 0) in
+the list are protected by the file semaphore f->sem. But the erase
+code may remove _obsolete_ nodes from the list while holding only the
+erase_completion_lock. So you can walk the list only while holding the
+erase_completion_lock, and can drop the lock temporarily mid-walk as
+long as the pointer you're holding is to a _valid_ node, not an
+obsolete one.
+
+The erase_completion_lock is also used to protect the c->gc_task
+pointer when the garbage collection thread exits. The code to kill the
+GC thread locks it, sends the signal, then unlocks it - while the GC
+thread itself locks it, zeroes c->gc_task, then unlocks on the exit path.
+
+	node_free_sem
+	-------------
+
+This semaphore is only used by the erase code which frees obsolete
+node references and the jffs2_garbage_collect_deletion_dirent()
+function. The latter function on NAND flash must read _obsolete_ nodes
+to determine whether the 'deletion dirent' under consideration can be
+discarded or whether it is still required to show that an inode has
+been unlinked. Because reading from the flash may sleep, the
+erase_completion_lock cannot be held, so an alternative, more
+heavyweight lock was required to prevent the erase code from freeing
+the jffs2_raw_node_ref structures in question while the garbage
+collection code is looking at them.
+
+Suggestions for alternative solutions to this problem would be welcomed.
diff -Nru a/fs/jffs2/TODO b/fs/jffs2/TODO
--- a/fs/jffs2/TODO	Fri Mar 15 17:51:03 2002
+++ b/fs/jffs2/TODO	Fri Mar 15 17:51:03 2002
@@ -1,8 +1,7 @@
-$Id: TODO,v 1.3 2001/03/01 23:26:48 dwmw2 Exp $
+$Id: TODO,v 1.7 2002/03/11 12:36:59 dwmw2 Exp $
 
- - disable compression in commit_write()? Or at least optimise the 'always write
-	whole page' bit.
- - fix zlib. It's ugly as hell and there are at least three copies in the kernel tree
+ - Locking audit. Even more so now 2.5 took away the BKL.
+ - disable compression in commit_write()?
  - fine-tune the allocation / GC thresholds
  - chattr support - turning on/off and tuning compression per-inode
  - checkpointing (do we need this? scan is quite fast)
@@ -10,11 +9,16 @@
 	mount doesn't have to read the flash twice for large files.
 	Make this a per-inode option, changable with chattr, so you can
 	decide which inodes should be in-core immediately after mount.
- - stop it depending on a block device. mount(8) needs a change for this.
- - make it work on NAND flash. We need to know when we can GC
-	deletion dirents, etc. And think about holes/truncation. It can
-	all be done reasonably simply, but it need implementing.
- - NAND flash will require new dirent/dnode structures on the medium with
-	ECC data in rather than just the CRC we're using ATM.
+ - stop it depending on a block device.
  - test, test, test
+
+ - NAND flash support:
+	- flush_wbuf using GC to fill it, don't just pad.
+	- Deal with write errors. Data don't get lost - we just have to write 
+	  the affected node(s) out again somewhere else.
+	- make fsync flush only if actually required
+	- make sys_sync() work.
+	- reboot notifier
+	- timed flush of old wbuf
+	- fix magical second arg of jffs2_flush_wbuf(). Split into two or more functions instead.
 
diff -Nru a/fs/jffs2/background.c b/fs/jffs2/background.c
--- a/fs/jffs2/background.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/background.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,19 +31,19 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: background.c,v 1.16 2001/10/08 09:22:38 dwmw2 Exp $
+ * $Id: background.c,v 1.23 2002/03/06 12:37:08 dwmw2 Exp $
  *
  */
 
 #define __KERNEL_SYSCALLS__
 
 #include <linux/kernel.h>
-#include <linux/time.h>
 #include <linux/unistd.h>
 #include <linux/jffs2.h>
 #include <linux/mtd/mtd.h>
 #include <linux/interrupt.h>
 #include <linux/completion.h>
+#include <linux/mtd/compatmac.h> /* recalc_sigpending() */
 #include "nodelist.h"
 
 
@@ -106,10 +106,7 @@
 
         sprintf(current->comm, "jffs2_gcd_mtd%d", c->mtd->index);
 
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
-	/* FIXME in the 2.2 backport */
-	current->nice = 10;
-#endif
+	set_user_nice(current, 10);
 
 	for (;;) {
 		spin_lock_irq(&current->sigmask_lock);
diff -Nru a/fs/jffs2/build.c b/fs/jffs2/build.c
--- a/fs/jffs2/build.c	Fri Mar 15 17:51:03 2002
+++ b/fs/jffs2/build.c	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,12 +31,11 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: build.c,v 1.16 2001/03/15 15:38:23 dwmw2 Exp $
+ * $Id: build.c,v 1.32 2002/03/08 15:11:24 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
-#include <linux/jffs2.h>
 #include <linux/slab.h>
 #include "nodelist.h"
 
@@ -51,7 +50,7 @@
  - Scan directory tree from top down, setting nlink in inocaches
  - Scan inocaches for inodes with nlink==0
 */
-int jffs2_build_filesystem(struct jffs2_sb_info *c)
+static int jffs2_build_filesystem(struct jffs2_sb_info *c)
 {
 	int ret;
 	int i;
@@ -59,7 +58,11 @@
 
 	/* First, scan the medium and build all the inode caches with
 	   lists of physical nodes */
+
+	c->flags |= JFFS2_SB_FLAG_MOUNTING;
 	ret = jffs2_scan_medium(c);
+	c->flags &= ~JFFS2_SB_FLAG_MOUNTING;
+
 	if (ret)
 		return ret;
 
@@ -147,6 +150,7 @@
 			D1(printk(KERN_DEBUG "jffs2_build_inode_pass1 ignoring old metadata at 0x%08x\n",
 				  metadata->fn->raw->flash_offset &~3));
 			
+			jffs2_mark_node_obsolete(c, metadata->fn->raw);
 			jffs2_free_full_dnode(metadata->fn);
 			jffs2_free_tmp_dnode_info(metadata);
 			metadata = NULL;
@@ -159,15 +163,25 @@
 			if (!metadata) {
 				metadata = tn;
 			} else {
+				/* This will only happen if it has the _same_ version
+				   number as the existing metadata node. */
 				D1(printk(KERN_DEBUG "jffs2_build_inode_pass1 ignoring new metadata at 0x%08x\n",
 					  tn->fn->raw->flash_offset &~3));
 				
+				jffs2_mark_node_obsolete(c, tn->fn->raw);
 				jffs2_free_full_dnode(tn->fn);
 				jffs2_free_tmp_dnode_info(tn);
 			}
 		}
 	}
-		
+
+	if (ic->scan->version) {
+		/* It's a regular file, so truncate it to the last known
+		   i_size, if necessary */
+		D1(printk(KERN_DEBUG "jffs2_build_inode_pass1 truncating fraglist to 0x%08x\n", ic->scan->isize));
+		jffs2_truncate_fraglist(c, &fraglist, ic->scan->isize);
+	}
+	
 	/* OK. Now clear up */
 	if (metadata) {
 		jffs2_free_full_dnode(metadata->fn);
@@ -201,6 +215,10 @@
 
 		if (child_ic->nlink++ && fd->type == DT_DIR) {
 			printk(KERN_NOTICE "Child dir \"%s\" (ino #%u) of dir ino #%u appears to be a hard link\n", fd->name, fd->ino, ic->ino);
+			if (fd->ino == 1 && ic->ino == 1) {
+				printk(KERN_NOTICE "This is mostly harmless, and probably caused by creating a JFFS2 image\n");
+				printk(KERN_NOTICE "using a buggy version of mkfs.jffs2. Use at least v1.17.\n");
+			}
 			/* What do we do about it? */
 		}
 		D1(printk(KERN_DEBUG "Increased nlink for child \"%s\" (ino #%u)\n", fd->name, fd->ino));
@@ -251,7 +269,58 @@
 	}
 	kfree(ic->scan);
 	ic->scan = NULL;
-	//	jffs2_del_ino_cache(c, ic);
-	//	jffs2_free_inode_cache(ic);
+
+	/*
+	   We don't delete the inocache from the hash list and free it yet. 
+	   The erase code will do that, when all the nodes are completely gone.
+	*/
+
 	return ret;
+}
+
+int jffs2_do_mount_fs(struct jffs2_sb_info *c)
+{
+	int i;
+
+	c->free_size = c->flash_size;
+	c->nr_blocks = c->flash_size / c->sector_size;
+	c->blocks = kmalloc(sizeof(struct jffs2_eraseblock) * c->nr_blocks, GFP_KERNEL);
+	if (!c->blocks)
+		return -ENOMEM;
+	for (i=0; i<c->nr_blocks; i++) {
+		INIT_LIST_HEAD(&c->blocks[i].list);
+		c->blocks[i].offset = i * c->sector_size;
+		c->blocks[i].free_size = c->sector_size;
+		c->blocks[i].dirty_size = 0;
+		c->blocks[i].used_size = 0;
+		c->blocks[i].first_node = NULL;
+		c->blocks[i].last_node = NULL;
+	}
+
+	init_MUTEX(&c->alloc_sem);
+	init_MUTEX(&c->erase_free_sem);
+	init_waitqueue_head(&c->erase_wait);
+	spin_lock_init(&c->erase_completion_lock);
+	spin_lock_init(&c->inocache_lock);
+
+	INIT_LIST_HEAD(&c->clean_list);
+	INIT_LIST_HEAD(&c->dirty_list);
+	INIT_LIST_HEAD(&c->erasable_list);
+	INIT_LIST_HEAD(&c->erasing_list);
+	INIT_LIST_HEAD(&c->erase_pending_list);
+	INIT_LIST_HEAD(&c->erasable_pending_wbuf_list);
+	INIT_LIST_HEAD(&c->erase_complete_list);
+	INIT_LIST_HEAD(&c->free_list);
+	INIT_LIST_HEAD(&c->bad_list);
+	INIT_LIST_HEAD(&c->bad_used_list);
+	c->highest_ino = 1;
+
+	if (jffs2_build_filesystem(c)) {
+		D1(printk(KERN_DEBUG "build_fs failed\n"));
+		jffs2_free_ino_caches(c);
+		jffs2_free_raw_node_refs(c);
+		kfree(c->blocks);
+		return -EIO;
+	}
+	return 0;
 }
diff -Nru a/fs/jffs2/compr.c b/fs/jffs2/compr.c
--- a/fs/jffs2/compr.c	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/compr.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by Arjan van de Ven <arjanv@redhat.com>
  *
@@ -31,24 +31,34 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: compr.c,v 1.17 2001/09/23 09:56:46 dwmw2 Exp $
+ * $Id: compr.c,v 1.23 2002/01/25 01:49:26 dwmw2 Exp $
  *
  */
 
+#ifdef __KERNEL__
 #include <linux/kernel.h>
 #include <linux/string.h>
-#include <linux/types.h>
 #include <linux/errno.h>
+#else 
+#define KERN_DEBUG
+#define KERN_NOTICE
+#define KERN_WARNING
+#define printk printf
+#include <stdio.h>
+#include <stdint.h>
+#include <errno.h>
+#endif
+
 #include <linux/jffs2.h>
 
-int zlib_compress(unsigned char *data_in, unsigned char *cpage_out, __u32 *sourcelen, __u32 *dstlen);
-void zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen);
-int rtime_compress(unsigned char *data_in, unsigned char *cpage_out, __u32 *sourcelen, __u32 *dstlen);
-void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen);
-int rubinmips_compress(unsigned char *data_in, unsigned char *cpage_out, __u32 *sourcelen, __u32 *dstlen);
-void rubinmips_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen);
-int dynrubin_compress(unsigned char *data_in, unsigned char *cpage_out, __u32 *sourcelen, __u32 *dstlen);
-void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, __u32 srclen, __u32 destlen);
+int jffs2_zlib_compress(unsigned char *data_in, unsigned char *cpage_out, uint32_t *sourcelen, uint32_t *dstlen);
+void jffs2_zlib_decompress(unsigned char *data_in, unsigned char *cpage_out, uint32_t srclen, uint32_t destlen);
+int jffs2_rtime_compress(unsigned char *data_in, unsigned char *cpage_out, uint32_t *sourcelen, uint32_t *dstlen);
+void jffs2_rtime_decompress(unsigned char *data_in, unsigned char *cpage_out, uint32_t srclen, uint32_t destlen);
+int jffs2_rubinmips_compress(unsigned char *data_in, unsigned char *cpage_out, uint32_t *sourcelen, uint32_t *dstlen);
+void jffs2_rubinmips_decompress(unsigned char *data_in, unsigned char *cpage_out, uint32_t srclen, uint32_t destlen);
+int jffs2_dynrubin_compress(unsigned char *data_in, unsigned char *cpage_out, uint32_t *sourcelen, uint32_t *dstlen);
+void jffs2_dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, uint32_t srclen, uint32_t destlen);
 
 
 /* jffs2_compress:
@@ -69,28 +79,28 @@
  * *datalen accordingly to show the amount of data which were compressed.
  */
 unsigned char jffs2_compress(unsigned char *data_in, unsigned char *cpage_out, 
-		    __u32 *datalen, __u32 *cdatalen)
+		    uint32_t *datalen, uint32_t *cdatalen)
 {
 	int ret;
 
-	ret = zlib_compress(data_in, cpage_out, datalen, cdatalen);
+	ret = jffs2_zlib_compress(data_in, cpage_out, datalen, cdatalen);
 	if (!ret) {
 		return JFFS2_COMPR_ZLIB;
 	}
 #if 0 /* Disabled 23/9/1. With zlib it hardly ever gets a look in */
-	ret = dynrubin_compress(data_in, cpage_out, datalen, cdatalen);
+	ret = jffs2_dynrubin_compress(data_in, cpage_out, datalen, cdatalen);
 	if (!ret) {
 		return JFFS2_COMPR_DYNRUBIN;
 	}
 #endif
 #if 0 /* Disabled 26/2/1. Obsoleted by dynrubin */
-	ret = rubinmips_compress(data_in, cpage_out, datalen, cdatalen);
+	ret = jffs2_rubinmips_compress(data_in, cpage_out, datalen, cdatalen);
 	if (!ret) {
 		return JFFS2_COMPR_RUBINMIPS;
 	}
 #endif
 	/* rtime does manage to recompress already-compressed data */
-	ret = rtime_compress(data_in, cpage_out, datalen, cdatalen);
+	ret = jffs2_rtime_compress(data_in, cpage_out, datalen, cdatalen);
 	if (!ret) {
 		return JFFS2_COMPR_RTIME;
 	}
@@ -108,7 +118,7 @@
 
 
 int jffs2_decompress(unsigned char comprtype, unsigned char *cdata_in, 
-		     unsigned char *data_out, __u32 cdatalen, __u32 datalen)
+		     unsigned char *data_out, uint32_t cdatalen, uint32_t datalen)
 {
 	switch (comprtype) {
 	case JFFS2_COMPR_NONE:
@@ -121,23 +131,23 @@
 		break;
 
 	case JFFS2_COMPR_ZLIB:
-		zlib_decompress(cdata_in, data_out, cdatalen, datalen);
+		jffs2_zlib_decompress(cdata_in, data_out, cdatalen, datalen);
 		break;
 
 	case JFFS2_COMPR_RTIME:
-		rtime_decompress(cdata_in, data_out, cdatalen, datalen);
+		jffs2_rtime_decompress(cdata_in, data_out, cdatalen, datalen);
 		break;
 
 	case JFFS2_COMPR_RUBINMIPS:
 #if 0 /* Disabled 23/9/1 */
-		rubinmips_decompress(cdata_in, data_out, cdatalen, datalen);
+		jffs2_rubinmips_decompress(cdata_in, data_out, cdatalen, datalen);
 #else
 		printk(KERN_WARNING "JFFS2: Rubinmips compression encountered but support not compiled in!\n");
 #endif
 		break;
 	case JFFS2_COMPR_DYNRUBIN:
 #if 1 /* Phase this one out */
-		dynrubin_decompress(cdata_in, data_out, cdatalen, datalen);
+		jffs2_dynrubin_decompress(cdata_in, data_out, cdatalen, datalen);
 #else
 		printk(KERN_WARNING "JFFS2: Dynrubin compression encountered but support not compiled in!\n");
 #endif
diff -Nru a/fs/jffs2/compr_rtime.c b/fs/jffs2/compr_rtime.c
--- a/fs/jffs2/compr_rtime.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/compr_rtime.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by Arjan van de Ven <arjanv@redhat.com>
  *
@@ -31,7 +31,7 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: compr_rtime.c,v 1.5 2001/03/15 15:38:23 dwmw2 Exp $
+ * $Id: compr_rtime.c,v 1.8 2002/01/25 01:49:26 dwmw2 Exp $
  *
  *
  * Very simple lz77-ish encoder.
@@ -51,8 +51,8 @@
 #include <linux/string.h> 
 
 /* _compress returns the compressed size, -1 if bigger */
-int rtime_compress(unsigned char *data_in, unsigned char *cpage_out, 
-		   __u32 *sourcelen, __u32 *dstlen)
+int jffs2_rtime_compress(unsigned char *data_in, unsigned char *cpage_out, 
+		   uint32_t *sourcelen, uint32_t *dstlen)
 {
 	int positions[256];
 	int outpos = 0;
@@ -91,8 +91,8 @@
 }		   
 
 
-void rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
-		      __u32 srclen, __u32 destlen)
+void jffs2_rtime_decompress(unsigned char *data_in, unsigned char *cpage_out,
+		      uint32_t srclen, uint32_t destlen)
 {
 	int positions[256];
 	int outpos = 0;
diff -Nru a/fs/jffs2/compr_rubin.c b/fs/jffs2/compr_rubin.c
--- a/fs/jffs2/compr_rubin.c	Fri Mar 15 17:51:03 2002
+++ b/fs/jffs2/compr_rubin.c	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by Arjan van de Ven <arjanv@redhat.com>
  *
@@ -31,7 +31,7 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: compr_rubin.c,v 1.13 2001/09/23 10:06:05 rmk Exp $
+ * $Id: compr_rubin.c,v 1.16 2002/01/25 01:49:26 dwmw2 Exp $
  *
  */
 
@@ -43,7 +43,7 @@
 
 
 
-void init_rubin(struct rubin_state *rs, int div, int *bits)
+static void init_rubin(struct rubin_state *rs, int div, int *bits)
 {	
 	int c;
 
@@ -56,7 +56,7 @@
 }
 
 
-int encode(struct rubin_state *rs, long A, long B, int symbol)
+static int encode(struct rubin_state *rs, long A, long B, int symbol)
 {
 
 	long i0, i1;
@@ -91,7 +91,7 @@
 }
 
 
-void end_rubin(struct rubin_state *rs)
+static void end_rubin(struct rubin_state *rs)
 {				
 
 	int i;
@@ -104,7 +104,7 @@
 }
 
 
-void init_decode(struct rubin_state *rs, int div, int *bits)
+static void init_decode(struct rubin_state *rs, int div, int *bits)
 {
 	init_rubin(rs, div, bits);		
 
@@ -151,7 +151,7 @@
 	rs->rec_q = rec_q;
 }
 
-int decode(struct rubin_state *rs, long A, long B)
+static int decode(struct rubin_state *rs, long A, long B)
 {
 	unsigned long p = rs->p, q = rs->q;
 	long i0, threshold;
@@ -212,8 +212,8 @@
 
 
 
-int rubin_do_compress(int bit_divider, int *bits, unsigned char *data_in, 
-		      unsigned char *cpage_out, __u32 *sourcelen, __u32 *dstlen)
+static int rubin_do_compress(int bit_divider, int *bits, unsigned char *data_in, 
+		      unsigned char *cpage_out, uint32_t *sourcelen, uint32_t *dstlen)
 	{
 	int outpos = 0;
 	int pos=0;
@@ -246,20 +246,20 @@
 }		   
 #if 0
 /* _compress returns the compressed size, -1 if bigger */
-int rubinmips_compress(unsigned char *data_in, unsigned char *cpage_out, 
-		   __u32 *sourcelen, __u32 *dstlen)
+int jffs2_rubinmips_compress(unsigned char *data_in, unsigned char *cpage_out, 
+		   uint32_t *sourcelen, uint32_t *dstlen)
 {
 	return rubin_do_compress(BIT_DIVIDER_MIPS, bits_mips, data_in, cpage_out, sourcelen, dstlen);
 }
 #endif
-int dynrubin_compress(unsigned char *data_in, unsigned char *cpage_out, 
-		   __u32 *sourcelen, __u32 *dstlen)
+int jffs2_dynrubin_compress(unsigned char *data_in, unsigned char *cpage_out, 
+		   uint32_t *sourcelen, uint32_t *dstlen)
 {
 	int bits[8];
 	unsigned char histo[256];
 	int i;
 	int ret;
-	__u32 mysrclen, mydstlen;
+	uint32_t mysrclen, mydstlen;
 
 	mysrclen = *sourcelen;
 	mydstlen = *dstlen - 8;
@@ -315,8 +315,8 @@
 	return 0;
 }
 
-void rubin_do_decompress(int bit_divider, int *bits, unsigned char *cdata_in, 
-			 unsigned char *page_out, __u32 srclen, __u32 destlen)
+static void rubin_do_decompress(int bit_divider, int *bits, unsigned char *cdata_in, 
+			 unsigned char *page_out, uint32_t srclen, uint32_t destlen)
 {
 	int outpos = 0;
 	struct rubin_state rs;
@@ -330,14 +330,14 @@
 }		   
 
 
-void rubinmips_decompress(unsigned char *data_in, unsigned char *cpage_out, 
-		   __u32 sourcelen, __u32 dstlen)
+void jffs2_rubinmips_decompress(unsigned char *data_in, unsigned char *cpage_out, 
+		   uint32_t sourcelen, uint32_t dstlen)
 {
 	rubin_do_decompress(BIT_DIVIDER_MIPS, bits_mips, data_in, cpage_out, sourcelen, dstlen);
 }
 
-void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, 
-		   __u32 sourcelen, __u32 dstlen)
+void jffs2_dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out, 
+		   uint32_t sourcelen, uint32_t dstlen)
 {
 	int bits[8];
 	int c;
diff -Nru a/fs/jffs2/compr_rubin.h b/fs/jffs2/compr_rubin.h
--- a/fs/jffs2/compr_rubin.h	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/compr_rubin.h	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /* Rubin encoder/decoder header       */
 /* work started at   : aug   3, 1994  */
 /* last modification : aug  15, 1994  */
-/* $Id: compr_rubin.h,v 1.5 2001/02/26 13:50:01 dwmw2 Exp $ */
+/* $Id: compr_rubin.h,v 1.6 2002/01/25 01:49:26 dwmw2 Exp $ */
 
 #include "pushpull.h"
 
@@ -19,10 +19,3 @@
 	int bit_divider;
 	int bits[8];
 };
-
-
-void init_rubin (struct rubin_state *rs, int div, int *bits);
-int encode (struct rubin_state *, long, long, int);
-void end_rubin (struct rubin_state *);
-void init_decode (struct rubin_state *, int div, int *bits);
-int decode (struct rubin_state *, long, long);
diff -Nru a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c
--- a/fs/jffs2/compr_zlib.c	Fri Mar 15 17:51:00 2002
+++ b/fs/jffs2/compr_zlib.c	Fri Mar 15 17:51:00 2002
@@ -85,7 +85,7 @@
 	vfree(inflate_workspace);
 }
 
-int zlib_compress(unsigned char *data_in, unsigned char *cpage_out, 
+int jffs2_zlib_compress(unsigned char *data_in, unsigned char *cpage_out, 
 		   uint32_t *sourcelen, uint32_t *dstlen)
 {
 	z_stream strm;
@@ -145,7 +145,7 @@
 	return 0;
 }
 
-void zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
+void jffs2_zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
 		      uint32_t srclen, uint32_t destlen)
 {
 	z_stream strm;
diff -Nru a/fs/jffs2/comprtest.c b/fs/jffs2/comprtest.c
--- a/fs/jffs2/comprtest.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/comprtest.c	Fri Mar 15 17:51:01 2002
@@ -1,4 +1,4 @@
-/* $Id: comprtest.c,v 1.4 2001/02/21 14:03:20 dwmw2 Exp $ */
+/* $Id: comprtest.c,v 1.5 2002/01/03 15:20:44 dwmw2 Exp $ */
 
 #include <linux/kernel.h>
 #include <linux/string.h>
@@ -266,13 +266,13 @@
 static unsigned char decomprbuf[TESTDATA_LEN];
 
 int jffs2_decompress(unsigned char comprtype, unsigned char *cdata_in, 
-		     unsigned char *data_out, __u32 cdatalen, __u32 datalen);
+		     unsigned char *data_out, uint32_t cdatalen, uint32_t datalen);
 unsigned char jffs2_compress(unsigned char *data_in, unsigned char *cpage_out, 
-			     __u32 *datalen, __u32 *cdatalen);
+			     uint32_t *datalen, uint32_t *cdatalen);
 
 int init_module(void ) {
 	unsigned char comprtype;
-	__u32 c, d;
+	uint32_t c, d;
 	int ret;
 
 	printk("Original data: %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
diff -Nru a/fs/jffs2/dir.c b/fs/jffs2/dir.c
--- a/fs/jffs2/dir.c	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/dir.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,12 +31,13 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: dir.c,v 1.45.2.5 2002/02/23 14:31:09 dwmw2 Exp $
+ * $Id: dir.c,v 1.68 2002/03/11 12:36:59 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
 #include <linux/slab.h>
+#include <linux/sched.h>
 #include <linux/fs.h>
 #include <linux/crc32.h>
 #include <linux/mtd/compatmac.h> /* For completion */
@@ -44,7 +45,6 @@
 #include <linux/jffs2_fs_i.h>
 #include <linux/jffs2_fs_sb.h>
 #include <linux/time.h>
-#include <linux/smp_lock.h>
 #include "nodelist.h"
 
 static int jffs2_readdir (struct file *, void *, filldir_t);
@@ -65,7 +65,7 @@
 	read:		generic_read_dir,
 	readdir:	jffs2_readdir,
 	ioctl:		jffs2_ioctl,
-	fsync:		jffs2_null_fsync
+	fsync:		jffs2_fsync
 };
 
 
@@ -95,12 +95,11 @@
 	struct jffs2_inode_info *dir_f;
 	struct jffs2_sb_info *c;
 	struct jffs2_full_dirent *fd = NULL, *fd_list;
-	__u32 ino = 0;
+	uint32_t ino = 0;
 	struct inode *inode = NULL;
 
 	D1(printk(KERN_DEBUG "jffs2_lookup()\n"));
 
-	lock_kernel();
 	dir_f = JFFS2_INODE_INFO(dir_i);
 	c = JFFS2_SB_INFO(dir_i->i_sb);
 
@@ -121,12 +120,10 @@
 	if (ino) {
 		inode = iget(dir_i->i_sb, ino);
 		if (!inode) {
-			unlock_kernel();
 			printk(KERN_WARNING "iget() failed for ino #%u\n", ino);
 			return (ERR_PTR(-EIO));
 		}
 	}
-	unlock_kernel();
 
 	d_add(target, inode);
 
@@ -158,8 +155,9 @@
 		offset++;
 	}
 	if (offset == 1) {
-		D1(printk(KERN_DEBUG "Dirent 1: \"..\", ino #%lu\n", parent_ino(filp->f_dentry)));
-		if (filldir(dirent, "..", 2, 1, parent_ino(filp->f_dentry), DT_DIR) < 0)
+		unsigned long pino = parent_ino(filp->f_dentry);
+		D1(printk(KERN_DEBUG "Dirent 1: \"..\", ino #%lu\n", pino));
+		if (filldir(dirent, "..", 2, 1, pino, DT_DIR) < 0)
 			goto out;
 		offset++;
 	}
@@ -193,50 +191,28 @@
 
 /***********************************************************************/
 
+
 static int jffs2_create(struct inode *dir_i, struct dentry *dentry, int mode)
 {
+	struct jffs2_raw_inode *ri;
 	struct jffs2_inode_info *f, *dir_f;
 	struct jffs2_sb_info *c;
 	struct inode *inode;
-	struct jffs2_raw_inode *ri;
-	struct jffs2_raw_dirent *rd;
-	struct jffs2_full_dnode *fn;
-	struct jffs2_full_dirent *fd;
-	int namelen;
-	__u32 alloclen, phys_ofs;
-	__u32 writtenlen;
 	int ret;
 
-	lock_kernel();
 	ri = jffs2_alloc_raw_inode();
-	if (!ri) {
-		unlock_kernel();
+	if (!ri)
 		return -ENOMEM;
-	}
 	
 	c = JFFS2_SB_INFO(dir_i->i_sb);
 
 	D1(printk(KERN_DEBUG "jffs2_create()\n"));
 
-	/* Try to reserve enough space for both node and dirent. 
-	 * Just the node will do for now, though 
-	 */
-	namelen = dentry->d_name.len;
-	ret = jffs2_reserve_space(c, sizeof(*ri), &phys_ofs, &alloclen, ALLOC_NORMAL);
-	D1(printk(KERN_DEBUG "jffs2_create(): reserved 0x%x bytes\n", alloclen));
-	if (ret) {
-		jffs2_free_raw_inode(ri);
-		unlock_kernel();
-		return ret;
-	}
-
 	inode = jffs2_new_inode(dir_i, mode, ri);
 
 	if (IS_ERR(inode)) {
 		D1(printk(KERN_DEBUG "jffs2_new_inode() failed\n"));
 		jffs2_free_raw_inode(ri);
-		jffs2_complete_reservation(c);
-		unlock_kernel();
 		return PTR_ERR(inode);
 	}
 
@@ -246,278 +222,71 @@
 	inode->i_mapping->nrpages = 0;
 
 	f = JFFS2_INODE_INFO(inode);
-
-	ri->data_crc = 0;
-	ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
-
-	fn = jffs2_write_dnode(inode, ri, NULL, 0, phys_ofs, &writtenlen);
-	D1(printk(KERN_DEBUG "jffs2_create created file with mode 0x%x\n", ri->mode));
-	jffs2_free_raw_inode(ri);
-
-	if (IS_ERR(fn)) {
-		D1(printk(KERN_DEBUG "jffs2_write_dnode() failed\n"));
-		/* Eeek. Wave bye bye */
-		up(&f->sem);
-		jffs2_complete_reservation(c);
-		jffs2_clear_inode(inode);
-		unlock_kernel();
-		return PTR_ERR(fn);
-	}
-	/* No data here. Only a metadata node, which will be 
-	   obsoleted by the first data write
-	*/
-	f->metadata = fn;
-
-	/* Work out where to put the dirent node now. */
-	writtenlen = PAD(writtenlen);
-	phys_ofs += writtenlen;
-	alloclen -= writtenlen;
-	up(&f->sem);
-
-	if (alloclen < sizeof(*rd)+namelen) {
-		/* Not enough space left in this chunk. Get some more */
-		jffs2_complete_reservation(c);
-		ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &phys_ofs, &alloclen, ALLOC_NORMAL);
-		
-		if (ret) {
-			/* Eep. */
-			D1(printk(KERN_DEBUG "jffs2_reserve_space() for dirent failed\n"));
-			jffs2_clear_inode(inode);
-			unlock_kernel();
-			return ret;
-		}
-	}
-
-	rd = jffs2_alloc_raw_dirent();
-	if (!rd) {
-		/* Argh. Now we treat it like a normal delete */
-		jffs2_complete_reservation(c);
-		jffs2_clear_inode(inode);
-		unlock_kernel();
-		return -ENOMEM;
-	}
-
 	dir_f = JFFS2_INODE_INFO(dir_i);
-	down(&dir_f->sem);
-
-	rd->magic = JFFS2_MAGIC_BITMASK;
-	rd->nodetype = JFFS2_NODETYPE_DIRENT;
-	rd->totlen = sizeof(*rd) + namelen;
-	rd->hdr_crc = crc32(0, rd, sizeof(struct jffs2_unknown_node)-4);
-
-	rd->pino = dir_i->i_ino;
-	rd->version = ++dir_f->highest_version;
-	rd->ino = inode->i_ino;
-	rd->mctime = CURRENT_TIME;
-	rd->nsize = namelen;
-	rd->type = DT_REG;
-	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
-	rd->name_crc = crc32(0, dentry->d_name.name, namelen);
 
-	fd = jffs2_write_dirent(dir_i, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
+	ret = jffs2_do_create(c, dir_f, f, ri, 
+			      dentry->d_name.name, dentry->d_name.len);
 
-	jffs2_complete_reservation(c);
-
-	if (IS_ERR(fd)) {
-		/* dirent failed to write. Delete the inode normally 
-		   as if it were the final unlink() */
-		jffs2_free_raw_dirent(rd);
-		up(&dir_f->sem);
+	if (ret) {
 		jffs2_clear_inode(inode);
-		unlock_kernel();
-		return PTR_ERR(fd);
+		make_bad_inode(inode);
+		iput(inode);
+		jffs2_free_raw_inode(ri);
+		return ret;
 	}
 
-	dir_i->i_mtime = dir_i->i_ctime = rd->mctime;
-
-	jffs2_free_raw_dirent(rd);
-
-	/* Link the fd into the inode's list, obsoleting an old
-	   one if necessary. */
-	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
-	up(&dir_f->sem);
+	dir_i->i_mtime = dir_i->i_ctime = ri->ctime;
 
+	jffs2_free_raw_inode(ri);
 	d_instantiate(dentry, inode);
 
 	D1(printk(KERN_DEBUG "jffs2_create: Created ino #%lu with mode %o, nlink %d(%d). nrpages %ld\n",
 		  inode->i_ino, inode->i_mode, inode->i_nlink, f->inocache->nlink, inode->i_mapping->nrpages));
-	unlock_kernel();
 	return 0;
 }
 
 /***********************************************************************/
 
-static int jffs2_do_unlink(struct inode *dir_i, struct dentry *dentry, int rename)
-{
-	struct jffs2_inode_info *dir_f, *f;
-	struct jffs2_sb_info *c;
-	struct jffs2_raw_dirent *rd;
-	struct jffs2_full_dirent *fd;
-	__u32 alloclen, phys_ofs;
-	int ret;
-
-	c = JFFS2_SB_INFO(dir_i->i_sb);
-
-	rd = jffs2_alloc_raw_dirent();
-	if (!rd)
-		return -ENOMEM;
-
-	ret = jffs2_reserve_space(c, sizeof(*rd)+dentry->d_name.len, &phys_ofs, &alloclen, ALLOC_DELETION);
-	if (ret) {
-		jffs2_free_raw_dirent(rd);
-		return ret;
-	}
-
-	dir_f = JFFS2_INODE_INFO(dir_i);
-	down(&dir_f->sem);
-
-	/* Build a deletion node */
-	rd->magic = JFFS2_MAGIC_BITMASK;
-	rd->nodetype = JFFS2_NODETYPE_DIRENT;
-	rd->totlen = sizeof(*rd) + dentry->d_name.len;
-	rd->hdr_crc = crc32(0, rd, sizeof(struct jffs2_unknown_node)-4);
-
-	rd->pino = dir_i->i_ino;
-	rd->version = ++dir_f->highest_version;
-	rd->ino = 0;
-	rd->mctime = CURRENT_TIME;
-	rd->nsize = dentry->d_name.len;
-	rd->type = DT_UNKNOWN;
-	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
-	rd->name_crc = crc32(0, dentry->d_name.name, dentry->d_name.len);
-
-	fd = jffs2_write_dirent(dir_i, rd, dentry->d_name.name, dentry->d_name.len, phys_ofs, NULL);
-	
-	jffs2_complete_reservation(c);
-	jffs2_free_raw_dirent(rd);
-
-	if (IS_ERR(fd)) {
-		up(&dir_f->sem);
-		return PTR_ERR(fd);
-	}
-
-	/* File it. This will mark the old one obsolete. */
-	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
-	up(&dir_f->sem);
-	
-	if (!rename) {
-		f = JFFS2_INODE_INFO(dentry->d_inode);
-		down(&f->sem);
-
-		while (f->dents) {
-			/* There can be only deleted ones */
-			fd = f->dents;
-			
-			f->dents = fd->next;
-			
-			if (fd->ino) {
-				printk(KERN_WARNING "Deleting inode #%u with active dentry \"%s\"->ino #%u\n",
-				       f->inocache->ino, fd->name, fd->ino);
-			} else {
-				D1(printk(KERN_DEBUG "Removing deletion dirent for \"%s\" from dir ino #%u\n", fd->name, f->inocache->ino));
-			}
-			jffs2_mark_node_obsolete(c, fd->raw);
-			jffs2_free_full_dirent(fd);
-		}
-
-		f->inocache->nlink--;
-		dentry->d_inode->i_nlink--;
-		up(&f->sem);
-	}
-
-	return 0;
-}
 
 static int jffs2_unlink(struct inode *dir_i, struct dentry *dentry)
 {
-	int res;
-	lock_kernel();
-	res = jffs2_do_unlink(dir_i, dentry, 0);
-	unlock_kernel();
-	return res;
-}
-/***********************************************************************/
-
-static int jffs2_do_link (struct dentry *old_dentry, struct inode *dir_i, struct dentry *dentry, int rename)
-{
-	struct jffs2_inode_info *dir_f, *f;
-	struct jffs2_sb_info *c;
-	struct jffs2_raw_dirent *rd;
-	struct jffs2_full_dirent *fd;
-	__u32 alloclen, phys_ofs;
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(dir_i->i_sb);
+	struct jffs2_inode_info *dir_f = JFFS2_INODE_INFO(dir_i);
+	struct jffs2_inode_info *dead_f = JFFS2_INODE_INFO(dentry->d_inode);
 	int ret;
 
-	c = JFFS2_SB_INFO(dir_i->i_sb);
-
-	rd = jffs2_alloc_raw_dirent();
-	if (!rd)
-		return -ENOMEM;
-
-	ret = jffs2_reserve_space(c, sizeof(*rd)+dentry->d_name.len, &phys_ofs, &alloclen, ALLOC_NORMAL);
-	if (ret) {
-		jffs2_free_raw_dirent(rd);
-		return ret;
-	}
-	
-	dir_f = JFFS2_INODE_INFO(dir_i);
-	down(&dir_f->sem);
-
-	/* Build a deletion node */
-	rd->magic = JFFS2_MAGIC_BITMASK;
-	rd->nodetype = JFFS2_NODETYPE_DIRENT;
-	rd->totlen = sizeof(*rd) + dentry->d_name.len;
-	rd->hdr_crc = crc32(0, rd, sizeof(struct jffs2_unknown_node)-4);
-
-	rd->pino = dir_i->i_ino;
-	rd->version = ++dir_f->highest_version;
-	rd->ino = old_dentry->d_inode->i_ino;
-	rd->mctime = CURRENT_TIME;
-	rd->nsize = dentry->d_name.len;
-
-	/* XXX: This is ugly. */
-	rd->type = (old_dentry->d_inode->i_mode & S_IFMT) >> 12;
-	if (!rd->type) rd->type = DT_REG;
-
-	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
-	rd->name_crc = crc32(0, dentry->d_name.name, dentry->d_name.len);
-
-	fd = jffs2_write_dirent(dir_i, rd, dentry->d_name.name, dentry->d_name.len, phys_ofs, NULL);
-	
-	jffs2_complete_reservation(c);
-	jffs2_free_raw_dirent(rd);
-
-	if (IS_ERR(fd)) {
-		up(&dir_f->sem);
-		return PTR_ERR(fd);
-	}
-
-	/* File it. This will mark the old one obsolete. */
-	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
-	up(&dir_f->sem);
-
-	if (!rename) {
-		f = JFFS2_INODE_INFO(old_dentry->d_inode);
-		down(&f->sem);
-		old_dentry->d_inode->i_nlink = ++f->inocache->nlink;
-		up(&f->sem);
-	}
-	return 0;
+	ret = jffs2_do_unlink(c, dir_f, dentry->d_name.name, 
+			       dentry->d_name.len, dead_f);
+	dentry->d_inode->i_nlink = dead_f->inocache->nlink;
+	return ret;
 }
+/***********************************************************************/
+
 
 static int jffs2_link (struct dentry *old_dentry, struct inode *dir_i, struct dentry *dentry)
 {
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dentry->d_inode->i_sb);
+	struct jffs2_inode_info *f = JFFS2_INODE_INFO(old_dentry->d_inode);
+	struct jffs2_inode_info *dir_f = JFFS2_INODE_INFO(dir_i);
 	int ret;
+	uint8_t type;
 
 	if (S_ISDIR(old_dentry->d_inode->i_mode))
 		return -EPERM;
 
-	lock_kernel();
-	ret = jffs2_do_link(old_dentry, dir_i, dentry, 0);
+	/* XXX: This is ugly */
+	type = (old_dentry->d_inode->i_mode & S_IFMT) >> 12;
+	if (!type) type = DT_REG;
+
+	ret = jffs2_do_link(c, dir_f, f->inocache->ino, type, dentry->d_name.name, dentry->d_name.len);
+
 	if (!ret) {
+		down(&f->sem);
+		old_dentry->d_inode->i_nlink = ++f->inocache->nlink;
+		up(&f->sem);
 		d_instantiate(dentry, old_dentry->d_inode);
 		atomic_inc(&old_dentry->d_inode->i_count);
 	}
-	unlock_kernel();
 	return ret;
 }
 
@@ -533,8 +302,8 @@
 	struct jffs2_full_dnode *fn;
 	struct jffs2_full_dirent *fd;
 	int namelen;
-	__u32 alloclen, phys_ofs;
-	__u32 writtenlen;
+	uint32_t alloclen, phys_ofs;
+	uint32_t writtenlen;
 	int ret;
 
 	/* FIXME: If you care. We'd need to use frags for the target
@@ -542,7 +311,6 @@
 	if (strlen(target) > 254)
 		return -EINVAL;
 
-	lock_kernel();
 	ri = jffs2_alloc_raw_inode();
 
 	if (!ri)
@@ -558,7 +326,6 @@
 
 	if (ret) {
 		jffs2_free_raw_inode(ri);
-		unlock_kernel();
 		return ret;
 	}
 
@@ -567,7 +334,6 @@
 	if (IS_ERR(inode)) {
 		jffs2_free_raw_inode(ri);
 		jffs2_complete_reservation(c);
-		unlock_kernel();
 		return PTR_ERR(inode);
 	}
 
@@ -583,7 +349,7 @@
 	ri->data_crc = crc32(0, target, strlen(target));
 	ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
 	
-	fn = jffs2_write_dnode(inode, ri, target, strlen(target), phys_ofs, &writtenlen);
+	fn = jffs2_write_dnode(c, f, ri, target, strlen(target), phys_ofs, &writtenlen);
 
 	jffs2_free_raw_inode(ri);
 
@@ -592,7 +358,6 @@
 		up(&f->sem);
 		jffs2_complete_reservation(c);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return PTR_ERR(fn);
 	}
 	/* No data here. Only a metadata node, which will be 
@@ -613,7 +378,6 @@
 		if (ret) {
 			/* Eep. */
 			jffs2_clear_inode(inode);
-			unlock_kernel();
 			return ret;
 		}
 	}
@@ -623,7 +387,6 @@
 		/* Argh. Now we treat it like a normal delete */
 		jffs2_complete_reservation(c);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return -ENOMEM;
 	}
 
@@ -644,19 +407,18 @@
 	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
 	rd->name_crc = crc32(0, dentry->d_name.name, namelen);
 
-	fd = jffs2_write_dirent(dir_i, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
-	
-	jffs2_complete_reservation(c);
-	
+	fd = jffs2_write_dirent(c, dir_f, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
+
 	if (IS_ERR(fd)) {
 		/* dirent failed to write. Delete the inode normally 
 		   as if it were the final unlink() */
+		jffs2_complete_reservation(c);
 		jffs2_free_raw_dirent(rd);
 		up(&dir_f->sem);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return PTR_ERR(fd);
 	}
+
 	dir_i->i_mtime = dir_i->i_ctime = rd->mctime;
 
 	jffs2_free_raw_dirent(rd);
@@ -664,10 +426,11 @@
 	/* Link the fd into the inode's list, obsoleting an old
 	   one if necessary. */
 	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
+
 	up(&dir_f->sem);
+	jffs2_complete_reservation(c);
 
 	d_instantiate(dentry, inode);
-	unlock_kernel();
 	return 0;
 }
 
@@ -682,18 +445,15 @@
 	struct jffs2_full_dnode *fn;
 	struct jffs2_full_dirent *fd;
 	int namelen;
-	__u32 alloclen, phys_ofs;
-	__u32 writtenlen;
+	uint32_t alloclen, phys_ofs;
+	uint32_t writtenlen;
 	int ret;
 
 	mode |= S_IFDIR;
 
-	lock_kernel();
 	ri = jffs2_alloc_raw_inode();
-	if (!ri) {
-		unlock_kernel();
+	if (!ri)
 		return -ENOMEM;
-	}
 	
 	c = JFFS2_SB_INFO(dir_i->i_sb);
 
@@ -705,7 +465,6 @@
 
 	if (ret) {
 		jffs2_free_raw_inode(ri);
-		unlock_kernel();
 		return ret;
 	}
 
@@ -714,19 +473,20 @@
 	if (IS_ERR(inode)) {
 		jffs2_free_raw_inode(ri);
 		jffs2_complete_reservation(c);
-		unlock_kernel();
 		return PTR_ERR(inode);
 	}
 
 	inode->i_op = &jffs2_dir_inode_operations;
 	inode->i_fop = &jffs2_dir_operations;
+	/* Directories get nlink 2 at start */
+	inode->i_nlink = 2;
 
 	f = JFFS2_INODE_INFO(inode);
 
 	ri->data_crc = 0;
 	ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
 	
-	fn = jffs2_write_dnode(inode, ri, NULL, 0, phys_ofs, &writtenlen);
+	fn = jffs2_write_dnode(c, f, ri, NULL, 0, phys_ofs, &writtenlen);
 
 	jffs2_free_raw_inode(ri);
 
@@ -735,7 +495,6 @@
 		up(&f->sem);
 		jffs2_complete_reservation(c);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return PTR_ERR(fn);
 	}
 	/* No data here. Only a metadata node, which will be 
@@ -756,7 +515,6 @@
 		if (ret) {
 			/* Eep. */
 			jffs2_clear_inode(inode);
-			unlock_kernel();
 			return ret;
 		}
 	}
@@ -766,7 +524,6 @@
 		/* Argh. Now we treat it like a normal delete */
 		jffs2_complete_reservation(c);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return -ENOMEM;
 	}
 
@@ -787,31 +544,31 @@
 	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
 	rd->name_crc = crc32(0, dentry->d_name.name, namelen);
 
-	fd = jffs2_write_dirent(dir_i, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
-	
-	jffs2_complete_reservation(c);
+	fd = jffs2_write_dirent(c, dir_f, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
 	
 	if (IS_ERR(fd)) {
 		/* dirent failed to write. Delete the inode normally 
 		   as if it were the final unlink() */
+		jffs2_complete_reservation(c);
 		jffs2_free_raw_dirent(rd);
 		up(&dir_f->sem);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return PTR_ERR(fd);
 	}
 
 	dir_i->i_mtime = dir_i->i_ctime = rd->mctime;
+	dir_i->i_nlink++;
 
 	jffs2_free_raw_dirent(rd);
 
 	/* Link the fd into the inode's list, obsoleting an old
 	   one if necessary. */
 	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
+
 	up(&dir_f->sem);
+	jffs2_complete_reservation(c);
 
 	d_instantiate(dentry, inode);
-	unlock_kernel();
 	return 0;
 }
 
@@ -819,16 +576,16 @@
 {
 	struct jffs2_inode_info *f = JFFS2_INODE_INFO(dentry->d_inode);
 	struct jffs2_full_dirent *fd;
+	int ret;
 
-	lock_kernel();
 	for (fd = f->dents ; fd; fd = fd->next) {
-		if (fd->ino) {
-			unlock_kernel();
+		if (fd->ino)
 			return -ENOTEMPTY;
-		}
 	}
-	unlock_kernel();
-	return jffs2_unlink(dir_i, dentry);
+	ret = jffs2_unlink(dir_i, dentry);
+	if (!ret)
+		dir_i->i_nlink--;
+	return ret;
 }
 
 static int jffs2_mknod (struct inode *dir_i, struct dentry *dentry, int mode, int rdev)
@@ -843,16 +600,13 @@
 	int namelen;
 	unsigned short dev;
 	int devlen = 0;
-	__u32 alloclen, phys_ofs;
-	__u32 writtenlen;
+	uint32_t alloclen, phys_ofs;
+	uint32_t writtenlen;
 	int ret;
 
-	lock_kernel();
 	ri = jffs2_alloc_raw_inode();
-	if (!ri) {
-		unlock_kernel();
+	if (!ri)
 		return -ENOMEM;
-	}
 	
 	c = JFFS2_SB_INFO(dir_i->i_sb);
 	
@@ -869,7 +623,6 @@
 
 	if (ret) {
 		jffs2_free_raw_inode(ri);
-		unlock_kernel();
 		return ret;
 	}
 
@@ -878,7 +631,6 @@
 	if (IS_ERR(inode)) {
 		jffs2_free_raw_inode(ri);
 		jffs2_complete_reservation(c);
-		unlock_kernel();
 		return PTR_ERR(inode);
 	}
 	inode->i_op = &jffs2_file_inode_operations;
@@ -894,7 +646,7 @@
 	ri->data_crc = crc32(0, &dev, devlen);
 	ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
 	
-	fn = jffs2_write_dnode(inode, ri, (char *)&dev, devlen, phys_ofs, &writtenlen);
+	fn = jffs2_write_dnode(c, f, ri, (char *)&dev, devlen, phys_ofs, &writtenlen);
 
 	jffs2_free_raw_inode(ri);
 
@@ -903,7 +655,6 @@
 		up(&f->sem);
 		jffs2_complete_reservation(c);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return PTR_ERR(fn);
 	}
 	/* No data here. Only a metadata node, which will be 
@@ -924,7 +675,6 @@
 		if (ret) {
 			/* Eep. */
 			jffs2_clear_inode(inode);
-			unlock_kernel();
 			return ret;
 		}
 	}
@@ -934,7 +684,6 @@
 		/* Argh. Now we treat it like a normal delete */
 		jffs2_complete_reservation(c);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return -ENOMEM;
 	}
 
@@ -958,17 +707,15 @@
 	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
 	rd->name_crc = crc32(0, dentry->d_name.name, namelen);
 
-	fd = jffs2_write_dirent(dir_i, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
-	
-	jffs2_complete_reservation(c);
+	fd = jffs2_write_dirent(c, dir_f, rd, dentry->d_name.name, namelen, phys_ofs, &writtenlen);
 	
 	if (IS_ERR(fd)) {
 		/* dirent failed to write. Delete the inode normally 
 		   as if it were the final unlink() */
+		jffs2_complete_reservation(c);
 		jffs2_free_raw_dirent(rd);
 		up(&dir_f->sem);
 		jffs2_clear_inode(inode);
-		unlock_kernel();
 		return PTR_ERR(fd);
 	}
 
@@ -979,8 +726,9 @@
 	/* Link the fd into the inode's list, obsoleting an old
 	   one if necessary. */
 	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
+
 	up(&dir_f->sem);
-	unlock_kernel();
+	jffs2_complete_reservation(c);
 
 	d_instantiate(dentry, inode);
 
@@ -991,35 +739,54 @@
                         struct inode *new_dir_i, struct dentry *new_dentry)
 {
 	int ret;
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(old_dir_i->i_sb);
+	uint8_t type;
+
 	/* XXX: We probably ought to alloc enough space for
 	   both nodes at the same time. Writing the new link, 
 	   then getting -ENOSPC, is quite bad :)
 	*/
 
 	/* Make a hard link */
-	lock_kernel();
-	ret = jffs2_do_link(old_dentry, new_dir_i, new_dentry, 1);
-	if (ret) {
-		unlock_kernel();
+	
+	/* XXX: This is ugly */
+	type = (old_dentry->d_inode->i_mode & S_IFMT) >> 12;
+	if (!type) type = DT_REG;
+
+	ret = jffs2_do_link(c, JFFS2_INODE_INFO(new_dir_i), 
+			    old_dentry->d_inode->i_ino, type,
+			    new_dentry->d_name.name, new_dentry->d_name.len);
+
+	if (ret)
 		return ret;
-	}
+
+	if (S_ISDIR(old_dentry->d_inode->i_mode))
+		new_dir_i->i_nlink++;
 
 	/* Unlink the original */
-	ret = jffs2_do_unlink(old_dir_i, old_dentry, 1);
-	
+	ret = jffs2_do_unlink(c, JFFS2_INODE_INFO(old_dir_i), 
+		      old_dentry->d_name.name, old_dentry->d_name.len, NULL);
+
+	/* We don't touch inode->i_nlink */
+
 	if (ret) {
 		/* Oh shit. We really ought to make a single node which can do both atomically */
 		struct jffs2_inode_info *f = JFFS2_INODE_INFO(old_dentry->d_inode);
 		down(&f->sem);
-		old_dentry->d_inode->i_nlink = f->inocache->nlink++;
+		old_dentry->d_inode->i_nlink++;
+		f->inocache->nlink++;
 		up(&f->sem);
-		       
+
 		printk(KERN_NOTICE "jffs2_rename(): Link succeeded, unlink failed (err %d). You now have a hard link\n", ret);
 		/* Might as well let the VFS know */
 		d_instantiate(new_dentry, old_dentry->d_inode);
 		atomic_inc(&old_dentry->d_inode->i_count);
+		return ret;
 	}
-	unlock_kernel();
-	return ret;
+
+	if (S_ISDIR(old_dentry->d_inode->i_mode))
+		old_dir_i->i_nlink--;
+
+	return 0;
 }
 
diff -Nru a/fs/jffs2/erase.c b/fs/jffs2/erase.c
--- a/fs/jffs2/erase.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/erase.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,14 +31,15 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: erase.c,v 1.24 2001/12/06 16:38:38 dwmw2 Exp $
+ * $Id: erase.c,v 1.35 2002/03/08 15:11:24 dwmw2 Exp $
  *
  */
+
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/mtd/mtd.h>
-#include <linux/jffs2.h>
 #include <linux/interrupt.h>
+#include <linux/compiler.h>
 #include <linux/crc32.h>
 #include "nodelist.h"
 
@@ -48,12 +49,13 @@
 };
       
 static void jffs2_erase_callback(struct erase_info *);
+static void jffs2_erase_succeeded(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
 static void jffs2_free_all_node_refs(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
 
 void jffs2_erase_block(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb)
 {
-	struct erase_info *instr;
 	int ret;
+	struct erase_info *instr;
 
 	instr = kmalloc(sizeof(struct erase_info) + sizeof(struct erase_priv_struct), GFP_KERNEL);
 	if (!instr) {
@@ -77,10 +79,16 @@
 	((struct erase_priv_struct *)instr->priv)->jeb = jeb;
 	((struct erase_priv_struct *)instr->priv)->c = c;
 
+	/* NAND , read out the fail counter, if possible */
+	if (!jffs2_can_mark_obsolete(c)) 
+		jffs2_nand_read_failcnt(c,jeb);
+		
 	ret = c->mtd->erase(c->mtd, instr);
-	if (!ret) {
+	if (!ret)
 		return;
-	}
+
+	kfree(instr);
+
 	if (ret == -ENOMEM || ret == -EAGAIN) {
 		/* Erase failed immediately. Refile it on the list */
 		D1(printk(KERN_DEBUG "Erase at 0x%08x failed: %d. Refiling on erase_pending_list\n", jeb->offset, ret));
@@ -89,7 +97,6 @@
 		list_add(&jeb->list, &c->erase_pending_list);
 		c->erasing_size -= c->sector_size;
 		spin_unlock_bh(&c->erase_completion_lock);
-		kfree(instr);
 		return;
 	}
 
@@ -97,6 +104,7 @@
 		printk(KERN_WARNING "Erase at 0x%08x failed immediately: -EROFS. Is the sector locked?\n", jeb->offset);
 	else
 		printk(KERN_WARNING "Erase at 0x%08x failed immediately: errno %d\n", jeb->offset, ret);
+
 	spin_lock_bh(&c->erase_completion_lock);
 	list_del(&jeb->list);
 	list_add(&jeb->list, &c->bad_list);
@@ -105,13 +113,14 @@
 	c->erasing_size -= c->sector_size;
 	spin_unlock_bh(&c->erase_completion_lock);
 	wake_up(&c->erase_wait);
-	kfree(instr);
 }
 
 void jffs2_erase_pending_blocks(struct jffs2_sb_info *c)
 {
 	struct jffs2_eraseblock *jeb;
 
+	down(&c->erase_free_sem);
+
 	spin_lock_bh(&c->erase_completion_lock);
 	while (!list_empty(&c->erase_pending_list)) {
 
@@ -130,35 +139,50 @@
 		spin_unlock_bh(&c->erase_completion_lock);
 		
 		jffs2_erase_block(c, jeb);
+
 		/* Be nice */
 		cond_resched();
+
 		spin_lock_bh(&c->erase_completion_lock);
 	}
 	spin_unlock_bh(&c->erase_completion_lock);
 	D1(printk(KERN_DEBUG "jffs2_erase_pending_blocks completed\n"));
+
+	up(&c->erase_free_sem);
 }
 
 
+static void jffs2_erase_succeeded(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb)
+{
+	D1(printk(KERN_DEBUG "Erase completed successfully at 0x%08x\n", jeb->offset));
+	spin_lock(&c->erase_completion_lock);
+	list_del(&jeb->list);
+	list_add_tail(&jeb->list, &c->erase_complete_list);
+	spin_unlock(&c->erase_completion_lock);
+}
+
+
+static inline void jffs2_erase_failed(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb)
+{
+	 spin_lock(&c->erase_completion_lock);
+	 c->erasing_size -= c->sector_size;
+	 c->bad_size += c->sector_size;
+	 list_del(&jeb->list);
+	 list_add(&jeb->list, &c->bad_list);
+	 c->nr_erasing_blocks--;
+	 spin_unlock(&c->erase_completion_lock);
+	 wake_up(&c->erase_wait);
+}	 
+
 static void jffs2_erase_callback(struct erase_info *instr)
 {
 	struct erase_priv_struct *priv = (void *)instr->priv;
 
 	if(instr->state != MTD_ERASE_DONE) {
 		printk(KERN_WARNING "Erase at 0x%08x finished, but state != MTD_ERASE_DONE. State is 0x%x instead.\n", instr->addr, instr->state);
-		spin_lock(&priv->c->erase_completion_lock);
-		priv->c->erasing_size -= priv->c->sector_size;
-		priv->c->bad_size += priv->c->sector_size;
-		list_del(&priv->jeb->list);
-		list_add(&priv->jeb->list, &priv->c->bad_list);
-		priv->c->nr_erasing_blocks--;
-		spin_unlock(&priv->c->erase_completion_lock);
-		wake_up(&priv->c->erase_wait);
+		jffs2_erase_failed(priv->c, priv->jeb);
 	} else {
-		D1(printk(KERN_DEBUG "Erase completed successfully at 0x%08x\n", instr->addr));
-		spin_lock(&priv->c->erase_completion_lock);
-		list_del(&priv->jeb->list);
-		list_add_tail(&priv->jeb->list, &priv->c->erase_complete_list);
-		spin_unlock(&priv->c->erase_completion_lock);
+		jffs2_erase_succeeded(priv->c, priv->jeb);
 	}	
 	/* Make sure someone picks up the block off the erase_complete list */
 	OFNI_BS_2SFFJ(priv->c)->s_dirt = 1;
@@ -263,17 +287,18 @@
 void jffs2_mark_erased_blocks(struct jffs2_sb_info *c)
 {
 	static struct jffs2_unknown_node marker = {
-			magic:		JFFS2_MAGIC_BITMASK,
-			nodetype:	JFFS2_NODETYPE_CLEANMARKER,
-			totlen:		sizeof(struct jffs2_unknown_node)
+		magic:		JFFS2_MAGIC_BITMASK,
+		nodetype:	JFFS2_NODETYPE_CLEANMARKER,
+		totlen:		sizeof(struct jffs2_unknown_node)
 	};
 	struct jffs2_eraseblock *jeb;
-	struct jffs2_raw_node_ref *marker_ref;
+	struct jffs2_raw_node_ref *marker_ref = NULL;
 	unsigned char *ebuf;
-	ssize_t retlen;
+	size_t retlen;
 	int ret;
 
-	marker.hdr_crc = crc32(0, &marker, sizeof(struct jffs2_unknown_node)-4);
+	if (unlikely(!marker.hdr_crc))
+		marker.hdr_crc = crc32(0, &marker, sizeof(struct jffs2_unknown_node)-4);
 
 	spin_lock_bh(&c->erase_completion_lock);
 	while (!list_empty(&c->erase_complete_list)) {
@@ -281,27 +306,28 @@
 		list_del(&jeb->list);
 		spin_unlock_bh(&c->erase_completion_lock);
 
-		marker_ref = jffs2_alloc_raw_node_ref();
-		if (!marker_ref) {
-			printk(KERN_WARNING "Failed to allocate raw node ref for clean marker\n");
-			/* Come back later */
-			jffs2_erase_pending_trigger(c);
-			return;
+		if (!jffs2_cleanmarker_oob(c)) {
+			marker_ref = jffs2_alloc_raw_node_ref();
+			if (!marker_ref) {
+				printk(KERN_WARNING "Failed to allocate raw node ref for clean marker\n");
+				/* Come back later */
+				jffs2_erase_pending_trigger(c);
+				return;
+			}
 		}
-
 		ebuf = kmalloc(PAGE_SIZE, GFP_KERNEL);
 		if (!ebuf) {
 			printk(KERN_WARNING "Failed to allocate page buffer for verifying erase at 0x%08x. Assuming it worked\n", jeb->offset);
 		} else {
-			__u32 ofs = jeb->offset;
+			uint32_t ofs = jeb->offset;
 
 			D1(printk(KERN_DEBUG "Verifying erase at 0x%08x\n", jeb->offset));
 			while(ofs < jeb->offset + c->sector_size) {
-				__u32 readlen = min((__u32)PAGE_SIZE, jeb->offset + c->sector_size - ofs);
+				uint32_t readlen = min((uint32_t)PAGE_SIZE, jeb->offset + c->sector_size - ofs);
 				int i;
 
-				ret = c->mtd->read(c->mtd, ofs, readlen, &retlen, ebuf);
-				if (ret < 0) {
+				ret = jffs2_flash_read(c, ofs, readlen, &retlen, ebuf);
+				if (ret) {
 					printk(KERN_WARNING "Read of newly-erased block at 0x%08x failed: %d. Putting on bad_list\n", ofs, ret);
 					goto bad;
 				}
@@ -315,7 +341,10 @@
 					if (datum + 1) {
 						printk(KERN_WARNING "Newly-erased block contained word 0x%lx at offset 0x%08x\n", datum, ofs + i);
 					bad: 
-						jffs2_free_raw_node_ref(marker_ref);
+						if (!jffs2_cleanmarker_oob(c))
+							jffs2_free_raw_node_ref(marker_ref);
+						else 
+							jffs2_write_nand_badblock( c ,jeb );
 						kfree(ebuf);
 					bad2:
 						spin_lock_bh(&c->erase_completion_lock);
@@ -336,28 +365,40 @@
 					
 		/* Write the erase complete marker */	
 		D1(printk(KERN_DEBUG "Writing erased marker to block at 0x%08x\n", jeb->offset));
-		ret = c->mtd->write(c->mtd, jeb->offset, sizeof(marker), &retlen, (char *)&marker);
-		if (ret) {
-			printk(KERN_WARNING "Write clean marker to block at 0x%08x failed: %d\n",
-			       jeb->offset, ret);
-			goto bad2;
-		}
-		if (retlen != sizeof(marker)) {
-			printk(KERN_WARNING "Short write to newly-erased block at 0x%08x: Wanted %d, got %d\n",
-			       jeb->offset, sizeof(marker), retlen);
-			goto bad2;
-		}
+		if (jffs2_cleanmarker_oob(c)) {
 
-		marker_ref->next_in_ino = NULL;
-		marker_ref->next_phys = NULL;
-		marker_ref->flash_offset = jeb->offset;
-		marker_ref->totlen = PAD(sizeof(marker));
-
-		jeb->first_node = jeb->last_node = marker_ref;
-
-		jeb->free_size = c->sector_size - marker_ref->totlen;
-		jeb->used_size = marker_ref->totlen;
-		jeb->dirty_size = 0;
+			if (jffs2_write_nand_cleanmarker(c, jeb))
+				goto bad2;
+			
+			jeb->first_node = jeb->last_node = NULL;
+			
+			jeb->free_size = c->sector_size;
+			jeb->used_size = 0;
+			jeb->dirty_size = 0;
+		} else {
+			ret = jffs2_flash_write(c, jeb->offset, sizeof(marker), &retlen, (char *)&marker);
+			if (ret) {
+				printk(KERN_WARNING "Write clean marker to block at 0x%08x failed: %d\n",
+				       jeb->offset, ret);
+				goto bad2;
+			}
+			if (retlen != sizeof(marker)) {
+				printk(KERN_WARNING "Short write to newly-erased block at 0x%08x: Wanted %d, got %d\n",
+				       jeb->offset, sizeof(marker), retlen);
+				goto bad2;
+			}
+			
+			marker_ref->next_in_ino = NULL;
+			marker_ref->next_phys = NULL;
+			marker_ref->flash_offset = jeb->offset;
+			marker_ref->totlen = PAD(sizeof(marker));
+			
+			jeb->first_node = jeb->last_node = marker_ref;
+			
+			jeb->free_size = c->sector_size - marker_ref->totlen;
+			jeb->used_size = marker_ref->totlen;
+			jeb->dirty_size = 0;
+		}
 
 		spin_lock_bh(&c->erase_completion_lock);
 		c->erasing_size -= c->sector_size;
diff -Nru a/fs/jffs2/file.c b/fs/jffs2/file.c
--- a/fs/jffs2/file.c	Fri Mar 15 17:51:03 2002
+++ b/fs/jffs2/file.c	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,7 +31,7 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: file.c,v 1.58.2.1 2002/02/23 14:25:36 dwmw2 Exp $
+ * $Id: file.c,v 1.70 2002/03/05 09:55:07 dwmw2 Exp $
  *
  */
 
@@ -39,6 +39,7 @@
 #include <linux/mtd/compatmac.h> /* for min() */
 #include <linux/slab.h>
 #include <linux/fs.h>
+#include <linux/time.h>
 #include <linux/pagemap.h>
 #include <linux/crc32.h>
 #include <linux/jffs2.h>
@@ -48,10 +49,27 @@
 extern loff_t generic_file_llseek(struct file *file, loff_t offset, int origin) __attribute__((weak));
 
 
-int jffs2_null_fsync(struct file *filp, struct dentry *dentry, int datasync)
+int jffs2_fsync(struct file *filp, struct dentry *dentry, int datasync)
 {
-	/* Move along. Nothing to see here */
-	return 0;
+	struct inode *inode = dentry->d_inode;
+	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
+	if (!c->wbuf || !c->wbuf_len)
+		return 0;
+
+	/* flush write buffer and update c->nextblock */
+	
+	/* FIXME NAND */
+	/* At the moment we flush the buffer, to make sure
+	 * that every thing is on the flash.
+	 * maybe we have to think about it to find a smarter
+	 * solution.
+	 */
+	down(&f->sem);
+	jffs2_flush_wbuf(c,2);
+	up(&f->sem);
+			
+	return 0;	
 }
 
 struct file_operations jffs2_file_operations =
@@ -62,7 +80,7 @@
 	write:		generic_file_write,
 	ioctl:		jffs2_ioctl,
 	mmap:		generic_file_mmap,
-	fsync:		jffs2_null_fsync
+	fsync:		jffs2_fsync
 };
 
 /* jffs2_file_inode_operations */
@@ -90,7 +108,7 @@
 	unsigned char *mdata = NULL;
 	int mdatalen = 0;
 	unsigned int ivalid;
-	__u32 phys_ofs, alloclen;
+	uint32_t phys_ofs, alloclen;
 	int ret;
 	D1(printk(KERN_DEBUG "jffs2_setattr(): ino #%lu\n", inode->i_ino));
 	ret = inode_change_ok(inode, iattr);
@@ -132,12 +150,12 @@
 	ret = jffs2_reserve_space(c, sizeof(*ri) + mdatalen, &phys_ofs, &alloclen, ALLOC_NORMAL);
 	if (ret) {
 		jffs2_free_raw_inode(ri);
-		if (S_ISLNK(inode->i_mode))
+		if (S_ISLNK(inode->i_mode & S_IFMT))
 			 kfree(mdata);
 		return ret;
 	}
 	down(&f->sem);
-        ivalid = iattr->ia_valid;
+	ivalid = iattr->ia_valid;
 	
 	ri->magic = JFFS2_MAGIC_BITMASK;
 	ri->nodetype = JFFS2_NODETYPE_INODE;
@@ -175,13 +193,12 @@
 	else
 		ri->data_crc = 0;
 
-	new_metadata = jffs2_write_dnode(inode, ri, mdata, mdatalen, phys_ofs, NULL);
+	new_metadata = jffs2_write_dnode(c, f, ri, mdata, mdatalen, phys_ofs, NULL);
 	if (S_ISLNK(inode->i_mode))
 		kfree(mdata);
-
-	jffs2_complete_reservation(c);
 	
 	if (IS_ERR(new_metadata)) {
+		jffs2_complete_reservation(c);
 		jffs2_free_raw_inode(ri);
 		up(&f->sem);
 		return PTR_ERR(new_metadata);
@@ -214,7 +231,10 @@
 		jffs2_free_full_dnode(old_metadata);
 	}
 	jffs2_free_raw_inode(ri);
+
 	up(&f->sem);
+	jffs2_complete_reservation(c);
+
 	return 0;
 }
 
@@ -222,85 +242,30 @@
 {
 	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
-	struct jffs2_node_frag *frag = f->fraglist;
-	__u32 offset = pg->index << PAGE_CACHE_SHIFT;
-	__u32 end = offset + PAGE_CACHE_SIZE;
 	unsigned char *pg_buf;
 	int ret;
 
-	D1(printk(KERN_DEBUG "jffs2_do_readpage_nolock(): ino #%lu, page at offset 0x%x\n", inode->i_ino, offset));
+	D1(printk(KERN_DEBUG "jffs2_do_readpage_nolock(): ino #%lu, page at offset 0x%lx\n", inode->i_ino, pg->index << PAGE_CACHE_SHIFT));
 
 	if (!PageLocked(pg))
                 PAGE_BUG(pg);
 
-	while(frag && frag->ofs + frag->size  <= offset) {
-		//		D1(printk(KERN_DEBUG "skipping frag %d-%d; before the region we care about\n", frag->ofs, frag->ofs + frag->size));
-		frag = frag->next;
-	}
-
 	pg_buf = kmap(pg);
+	/* FIXME: Can kmap fail? */
 
-	/* XXX FIXME: Where a single physical node actually shows up in two
-	   frags, we read it twice. Don't do that. */
-	/* Now we're pointing at the first frag which overlaps our page */
-	while(offset < end) {
-		D2(printk(KERN_DEBUG "jffs2_readpage: offset %d, end %d\n", offset, end));
-		if (!frag || frag->ofs > offset) {
-			__u32 holesize = end - offset;
-			if (frag) {
-				D1(printk(KERN_NOTICE "Eep. Hole in ino %ld fraglist. frag->ofs = 0x%08x, offset = 0x%08x\n", inode->i_ino, frag->ofs, offset));
-				holesize = min(holesize, frag->ofs - offset);
-				D1(jffs2_print_frag_list(f));
-			}
-			D1(printk(KERN_DEBUG "Filling non-frag hole from %d-%d\n", offset, offset+holesize));
-			memset(pg_buf, 0, holesize);
-			pg_buf += holesize;
-			offset += holesize;
-			continue;
-		} else if (frag->ofs < offset && (offset & (PAGE_CACHE_SIZE-1)) != 0) {
-			D1(printk(KERN_NOTICE "Eep. Overlap in ino #%ld fraglist. frag->ofs = 0x%08x, offset = 0x%08x\n",
-				  inode->i_ino, frag->ofs, offset));
-			D1(jffs2_print_frag_list(f));
-			memset(pg_buf, 0, end - offset);
-			ClearPageUptodate(pg);
-			SetPageError(pg);
-			kunmap(pg);
-			return -EIO;
-		} else if (!frag->node) {
-			__u32 holeend = min(end, frag->ofs + frag->size);
-			D1(printk(KERN_DEBUG "Filling frag hole from %d-%d (frag 0x%x 0x%x)\n", offset, holeend, frag->ofs, frag->ofs + frag->size));
-			memset(pg_buf, 0, holeend - offset);
-			pg_buf += holeend - offset;
-			offset = holeend;
-			frag = frag->next;
-			continue;
-		} else {
-			__u32 readlen;
-			readlen = min(frag->size, end - offset);
-			D1(printk(KERN_DEBUG "Reading %d-%d from node at 0x%x\n", frag->ofs, frag->ofs+readlen, frag->node->raw->flash_offset & ~3));
-			ret = jffs2_read_dnode(c, frag->node, pg_buf, frag->ofs - frag->node->ofs, readlen);
-			D2(printk(KERN_DEBUG "node read done\n"));
-			if (ret) {
-				D1(printk(KERN_DEBUG"jffs2_readpage error %d\n",ret));
-				memset(pg_buf, 0, frag->size);
-				ClearPageUptodate(pg);
-				SetPageError(pg);
-				kunmap(pg);
-				return ret;
-			}
-		}
-		pg_buf += frag->size;
-		offset += frag->size;
-		frag = frag->next;
-		D2(printk(KERN_DEBUG "node read was OK. Looping\n"));
-	}
-	D2(printk(KERN_DEBUG "readpage finishing\n"));
-	SetPageUptodate(pg);
-	ClearPageError(pg);
+	ret = jffs2_read_inode_range(c, f, pg_buf, pg->index << PAGE_CACHE_SHIFT, PAGE_CACHE_SIZE);
 
-	flush_dcache_page(pg);
+	if (ret) {
+		ClearPageUptodate(pg);
+		SetPageError(pg);
+	} else {
+		SetPageUptodate(pg);
+		ClearPageError(pg);
+	}
 
+	flush_dcache_page(pg);
 	kunmap(pg);
+
 	D1(printk(KERN_DEBUG "readpage finished\n"));
 	return 0;
 }
@@ -328,18 +293,18 @@
 {
 	struct inode *inode = filp->f_dentry->d_inode;
 	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
-	__u32 pageofs = pg->index << PAGE_CACHE_SHIFT;
+	uint32_t pageofs = pg->index << PAGE_CACHE_SHIFT;
 	int ret = 0;
 
 	down(&f->sem);
-	D1(printk(KERN_DEBUG "jffs2_prepare_write() nrpages %ld\n", inode->i_mapping->nrpages));
+	D1(printk(KERN_DEBUG "jffs2_prepare_write()\n"));
 
 	if (pageofs > inode->i_size) {
 		/* Make new hole frag from old EOF to new page */
 		struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
 		struct jffs2_raw_inode ri;
 		struct jffs2_full_dnode *fn;
-		__u32 phys_ofs, alloc_len;
+		uint32_t phys_ofs, alloc_len;
 		
 		D1(printk(KERN_DEBUG "Writing new hole frag 0x%x-0x%x between current EOF and new page\n",
 			  (unsigned int)inode->i_size, pageofs));
@@ -361,7 +326,7 @@
 		ri.mode = inode->i_mode;
 		ri.uid = inode->i_uid;
 		ri.gid = inode->i_gid;
-		ri.isize = max((__u32)inode->i_size, pageofs);
+		ri.isize = max((uint32_t)inode->i_size, pageofs);
 		ri.atime = ri.ctime = ri.mtime = CURRENT_TIME;
 		ri.offset = inode->i_size;
 		ri.dsize = pageofs - inode->i_size;
@@ -370,10 +335,11 @@
 		ri.node_crc = crc32(0, &ri, sizeof(ri)-8);
 		ri.data_crc = 0;
 		
-		fn = jffs2_write_dnode(inode, &ri, NULL, 0, phys_ofs, NULL);
-		jffs2_complete_reservation(c);
+		fn = jffs2_write_dnode(c, f, &ri, NULL, 0, phys_ofs, NULL);
+
 		if (IS_ERR(fn)) {
 			ret = PTR_ERR(fn);
+			jffs2_complete_reservation(c);
 			up(&f->sem);
 			return ret;
 		}
@@ -387,9 +353,11 @@
 			D1(printk(KERN_DEBUG "Eep. add_full_dnode_to_inode() failed in prepare_write, returned %d\n", ret));
 			jffs2_mark_node_obsolete(c, fn->raw);
 			jffs2_free_full_dnode(fn);
+			jffs2_complete_reservation(c);
 			up(&f->sem);
 			return ret;
 		}
+		jffs2_complete_reservation(c);
 		inode->i_size = pageofs;
 	}
 	
@@ -397,7 +365,7 @@
 	/* Read in the page if it wasn't already present */
 	if (!Page_Uptodate(pg) && (start || end < PAGE_SIZE))
 		ret = jffs2_do_readpage_nolock(inode, pg);
-	D1(printk(KERN_DEBUG "end prepare_write(). nrpages %ld\n", inode->i_mapping->nrpages));
+	D1(printk(KERN_DEBUG "end prepare_write()\n"));
 	up(&f->sem);
 	return ret;
 }
@@ -410,119 +378,49 @@
 	struct inode *inode = filp->f_dentry->d_inode;
 	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
-	__u32 newsize = max_t(__u32, filp->f_dentry->d_inode->i_size, (pg->index << PAGE_CACHE_SHIFT) + end);
-	__u32 file_ofs = (pg->index << PAGE_CACHE_SHIFT);
-	__u32 writelen = min((__u32)PAGE_CACHE_SIZE, newsize - file_ofs);
 	struct jffs2_raw_inode *ri;
 	int ret = 0;
-	ssize_t writtenlen = 0;
+	uint32_t writtenlen = 0;
 
-	D1(printk(KERN_DEBUG "jffs2_commit_write(): ino #%lu, page at 0x%lx, range %d-%d, nrpages %ld\n", inode->i_ino, pg->index << PAGE_CACHE_SHIFT, start, end, filp->f_dentry->d_inode->i_mapping->nrpages));
+	D1(printk(KERN_DEBUG "jffs2_commit_write(): ino #%lu, page at 0x%lx, range %d-%d\n",
+		  inode->i_ino, pg->index << PAGE_CACHE_SHIFT, start, end));
 
 	ri = jffs2_alloc_raw_inode();
-	if (!ri)
-		return -ENOMEM;
-
-	while(writelen) {
-		struct jffs2_full_dnode *fn;
-		unsigned char *comprbuf = NULL;
-		unsigned char comprtype = JFFS2_COMPR_NONE;
-		__u32 phys_ofs, alloclen;
-		__u32 datalen, cdatalen;
-
-		D2(printk(KERN_DEBUG "jffs2_commit_write() loop: 0x%x to write to 0x%x\n", writelen, file_ofs));
-
-		ret = jffs2_reserve_space(c, sizeof(*ri) + JFFS2_MIN_DATA_LEN, &phys_ofs, &alloclen, ALLOC_NORMAL);
-		if (ret) {
-			SetPageError(pg);
-			D1(printk(KERN_DEBUG "jffs2_reserve_space returned %d\n", ret));
-			break;
-		}
-		down(&f->sem);
-		datalen = writelen;
-		cdatalen = min(alloclen - sizeof(*ri), writelen);
-
-		comprbuf = kmalloc(cdatalen, GFP_KERNEL);
-		if (comprbuf) {
-			comprtype = jffs2_compress(page_address(pg)+ (file_ofs & (PAGE_CACHE_SIZE-1)), comprbuf, &datalen, &cdatalen);
-		}
-		if (comprtype == JFFS2_COMPR_NONE) {
-			/* Either compression failed, or the allocation of comprbuf failed */
-			if (comprbuf)
-				kfree(comprbuf);
-			comprbuf = page_address(pg) + (file_ofs & (PAGE_CACHE_SIZE -1));
-			datalen = cdatalen;
-		}
-		/* Now comprbuf points to the data to be written, be it compressed or not.
-		   comprtype holds the compression type, and comprtype == JFFS2_COMPR_NONE means
-		   that the comprbuf doesn't need to be kfree()d. 
-		*/
-
-		ri->magic = JFFS2_MAGIC_BITMASK;
-		ri->nodetype = JFFS2_NODETYPE_INODE;
-		ri->totlen = sizeof(*ri) + cdatalen;
-		ri->hdr_crc = crc32(0, ri, sizeof(struct jffs2_unknown_node)-4);
-
-		ri->ino = inode->i_ino;
-		ri->version = ++f->highest_version;
-		ri->mode = inode->i_mode;
-		ri->uid = inode->i_uid;
-		ri->gid = inode->i_gid;
-		ri->isize = max((__u32)inode->i_size, file_ofs + datalen);
-		ri->atime = ri->ctime = ri->mtime = CURRENT_TIME;
-		ri->offset = file_ofs;
-		ri->csize = cdatalen;
-		ri->dsize = datalen;
-		ri->compr = comprtype;
-		ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
-		ri->data_crc = crc32(0, comprbuf, cdatalen);
 
-		fn = jffs2_write_dnode(inode, ri, comprbuf, cdatalen, phys_ofs, NULL);
+	if (!ri) {
+		D1(printk(KERN_DEBUG "jffs2_commit_write(): Allocation of raw inode failed\n"));
+		return -ENOMEM;
+	}
 
-		jffs2_complete_reservation(c);
+	/* Set the fields that the generic jffs2_write_inode_range() code can't find */
+	ri->ino = inode->i_ino;
+	ri->mode = inode->i_mode;
+	ri->uid = inode->i_uid;
+	ri->gid = inode->i_gid;
+	ri->isize = (uint32_t)inode->i_size;
+	ri->atime = ri->ctime = ri->mtime = CURRENT_TIME;
+
+	/* We rely on the fact that generic_file_write() currently kmaps the page for us. */
+	ret = jffs2_write_inode_range(c, f, ri, page_address(pg) + start,
+				      (pg->index << PAGE_CACHE_SHIFT) + start, end - start, &writtenlen);
 
-		if (comprtype != JFFS2_COMPR_NONE)
-			kfree(comprbuf);
+	if (ret) {
+		/* There was an error writing. */
+		SetPageError(pg);
+	}
 
-		if (IS_ERR(fn)) {
-			ret = PTR_ERR(fn);
-			up(&f->sem);
-			SetPageError(pg);
-			break;
-		}
-		ret = jffs2_add_full_dnode_to_inode(c, f, fn);
-		if (f->metadata) {
-			jffs2_mark_node_obsolete(c, f->metadata->raw);
-			jffs2_free_full_dnode(f->metadata);
-			f->metadata = NULL;
+	if (writtenlen) {
+		if (inode->i_size < (pg->index << PAGE_CACHE_SHIFT) + start + writtenlen) {
+			inode->i_size = (pg->index << PAGE_CACHE_SHIFT) + start + writtenlen;
+			inode->i_blocks = (inode->i_size + 511) >> 9;
+			
+			inode->i_ctime = inode->i_mtime = ri->ctime;
 		}
-		up(&f->sem);
-		if (ret) {
-			/* Eep */
-			D1(printk(KERN_DEBUG "Eep. add_full_dnode_to_inode() failed in commit_write, returned %d\n", ret));
-			jffs2_mark_node_obsolete(c, fn->raw);
-			jffs2_free_full_dnode(fn);
-			SetPageError(pg);
-			break;
-		}
-		inode->i_size = ri->isize;
-		inode->i_blocks = (inode->i_size + 511) >> 9;
-		inode->i_ctime = inode->i_mtime = ri->ctime;
-		if (!datalen) {
-			printk(KERN_WARNING "Eep. We didn't actually write any bloody data\n");
-			ret = -EIO;
-			SetPageError(pg);
-			break;
-		}
-		D1(printk(KERN_DEBUG "increasing writtenlen by %d\n", datalen));
-		writtenlen += datalen;
-		file_ofs += datalen;
-		writelen -= datalen;
 	}
 
 	jffs2_free_raw_inode(ri);
 
-	if (writtenlen < end) {
+	if (start+writtenlen < end) {
 		/* generic_file_write has written more to the page cache than we've
 		   actually written to the medium. Mark the page !Uptodate so that 
 		   it gets reread */
@@ -530,13 +428,7 @@
 		SetPageError(pg);
 		ClearPageUptodate(pg);
 	}
-	if (writtenlen <= start) {
-		/* We didn't even get to the start of the affected part */
-		ret = ret?ret:-ENOSPC;
-		D1(printk(KERN_DEBUG "jffs2_commit_write(): Only %x bytes written to page. start (%x) not reached, returning %d\n", writtenlen, start, ret));
-	}
-	writtenlen = min(end-start, writtenlen-start);
 
-	D1(printk(KERN_DEBUG "jffs2_commit_write() returning %d. nrpages is %ld\n",writtenlen?writtenlen:ret, inode->i_mapping->nrpages));
+	D1(printk(KERN_DEBUG "jffs2_commit_write() returning %d\n",writtenlen?writtenlen:ret));
 	return writtenlen?writtenlen:ret;
 }
diff -Nru a/fs/jffs2/fs.c b/fs/jffs2/fs.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/jffs2/fs.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,455 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
+ *
+ * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * The original JFFS, from which the design for JFFS2 was derived,
+ * was designed and implemented by Axis Communications AB.
+ *
+ * The contents of this file are subject to the Red Hat eCos Public
+ * License Version 1.1 (the "Licence"); you may not use this file
+ * except in compliance with the Licence.  You may obtain a copy of
+ * the Licence at http://www.redhat.com/
+ *
+ * Software distributed under the Licence is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
+ * See the Licence for the specific language governing rights and
+ * limitations under the Licence.
+ *
+ * The Original Code is JFFS2 - Journalling Flash File System, version 2
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use your
+ * version of this file under the RHEPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the RHEPL or the GPL.
+ *
+ * $Id: fs.c,v 1.4 2002/03/11 12:36:59 dwmw2 Exp $
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/fs.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/mtd/mtd.h>
+#include <linux/pagemap.h>
+#include <linux/slab.h>
+#include "nodelist.h"
+
+int jffs2_statfs(struct super_block *sb, struct statfs *buf)
+{
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
+	unsigned long avail;
+
+	buf->f_type = JFFS2_SUPER_MAGIC;
+	buf->f_bsize = 1 << PAGE_SHIFT;
+	buf->f_blocks = c->flash_size >> PAGE_SHIFT;
+	buf->f_files = 0;
+	buf->f_ffree = 0;
+	buf->f_namelen = JFFS2_MAX_NAME_LEN;
+
+	spin_lock_bh(&c->erase_completion_lock);
+
+	avail = c->dirty_size + c->free_size;
+	if (avail > c->sector_size * JFFS2_RESERVED_BLOCKS_WRITE)
+		avail -= c->sector_size * JFFS2_RESERVED_BLOCKS_WRITE;
+	else
+		avail = 0;
+
+	buf->f_bavail = buf->f_bfree = avail >> PAGE_SHIFT;
+
+#if CONFIG_JFFS2_FS_DEBUG > 0
+	printk(KERN_DEBUG "STATFS:\n");
+	printk(KERN_DEBUG "flash_size: %08x\n", c->flash_size);
+	printk(KERN_DEBUG "used_size: %08x\n", c->used_size);
+	printk(KERN_DEBUG "dirty_size: %08x\n", c->dirty_size);
+	printk(KERN_DEBUG "free_size: %08x\n", c->free_size);
+	printk(KERN_DEBUG "erasing_size: %08x\n", c->erasing_size);
+	printk(KERN_DEBUG "bad_size: %08x\n", c->bad_size);
+	printk(KERN_DEBUG "sector_size: %08x\n", c->sector_size);
+	printk(KERN_DEBUG "jffs2_reserved_blocks size: %08x\n",c->sector_size * JFFS2_RESERVED_BLOCKS_WRITE);
+
+	if (c->nextblock) {
+		printk(KERN_DEBUG "nextblock: 0x%08x\n", c->nextblock->offset);
+	} else {
+		printk(KERN_DEBUG "nextblock: NULL\n");
+	}
+	if (c->gcblock) {
+		printk(KERN_DEBUG "gcblock: 0x%08x\n", c->gcblock->offset);
+	} else {
+		printk(KERN_DEBUG "gcblock: NULL\n");
+	}
+	if (list_empty(&c->clean_list)) {
+		printk(KERN_DEBUG "clean_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->clean_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "clean_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->dirty_list)) {
+		printk(KERN_DEBUG "dirty_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->dirty_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "dirty_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->erasable_list)) {
+		printk(KERN_DEBUG "erasable_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->erasable_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "erasable_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->erasing_list)) {
+		printk(KERN_DEBUG "erasing_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->erasing_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "erasing_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->erase_pending_list)) {
+		printk(KERN_DEBUG "erase_pending_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->erase_pending_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "erase_pending_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->erasable_pending_wbuf_list)) {
+		printk(KERN_DEBUG "erasable_pending_wbuf_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->erasable_pending_wbuf_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "erase_pending_wbuf_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->free_list)) {
+		printk(KERN_DEBUG "free_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->free_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "free_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->bad_list)) {
+		printk(KERN_DEBUG "bad_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->bad_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "bad_list: %08x\n", jeb->offset);
+		}
+	}
+	if (list_empty(&c->bad_used_list)) {
+		printk(KERN_DEBUG "bad_used_list: empty\n");
+	} else {
+		struct list_head *this;
+
+		list_for_each(this, &c->bad_used_list) {
+			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
+			printk(KERN_DEBUG "bad_used_list: %08x\n", jeb->offset);
+		}
+	}
+#endif /* CONFIG_JFFS2_FS_DEBUG */
+
+	spin_unlock_bh(&c->erase_completion_lock);
+
+
+	return 0;
+}
+
+
+void jffs2_clear_inode (struct inode *inode)
+{
+	/* We can forget about this inode for now - drop all 
+	 *  the nodelists associated with it, etc.
+	 */
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
+	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
+	
+	D1(printk(KERN_DEBUG "jffs2_clear_inode(): ino #%lu mode %o\n", inode->i_ino, inode->i_mode));
+
+	jffs2_do_clear_inode(c, f);
+}
+
+void jffs2_read_inode (struct inode *inode)
+{
+	struct jffs2_inode_info *f;
+	struct jffs2_sb_info *c;
+	struct jffs2_raw_inode latest_node;
+	int ret;
+
+	D1(printk(KERN_DEBUG "jffs2_read_inode(): inode->i_ino == %lu\n", inode->i_ino));
+
+	f = JFFS2_INODE_INFO(inode);
+	c = JFFS2_SB_INFO(inode->i_sb);
+
+	jffs2_init_inode_info(f);
+	
+	ret = jffs2_do_read_inode(c, f, inode->i_ino, &latest_node);
+
+	if (ret) {
+		make_bad_inode(inode);
+		up(&f->sem);
+		return;
+	}
+	inode->i_mode = latest_node.mode;
+	inode->i_uid = latest_node.uid;
+	inode->i_gid = latest_node.gid;
+	inode->i_size = latest_node.isize;
+	inode->i_atime = latest_node.atime;
+	inode->i_mtime = latest_node.mtime;
+	inode->i_ctime = latest_node.ctime;
+
+	inode->i_nlink = f->inocache->nlink;
+
+	inode->i_blksize = PAGE_SIZE;
+	inode->i_blocks = (inode->i_size + 511) >> 9;
+	
+	switch (inode->i_mode & S_IFMT) {
+		unsigned short rdev;
+
+	case S_IFLNK:
+		inode->i_op = &jffs2_symlink_inode_operations;
+		break;
+		
+	case S_IFDIR:
+	{
+		struct jffs2_full_dirent *fd;
+
+		for (fd=f->dents; fd; fd = fd->next) {
+			if (fd->type == DT_DIR && fd->ino)
+				inode->i_nlink++;
+		}
+		/* and '..' */
+		inode->i_nlink++;
+		/* Root dir gets i_nlink 3 for some reason */
+		if (inode->i_ino == 1)
+			inode->i_nlink++;
+
+		inode->i_op = &jffs2_dir_inode_operations;
+		inode->i_fop = &jffs2_dir_operations;
+		break;
+	}
+	case S_IFREG:
+		inode->i_op = &jffs2_file_inode_operations;
+		inode->i_fop = &jffs2_file_operations;
+		inode->i_mapping->a_ops = &jffs2_file_address_operations;
+		inode->i_mapping->nrpages = 0;
+		break;
+
+	case S_IFBLK:
+	case S_IFCHR:
+		/* Read the device numbers from the media */
+		D1(printk(KERN_DEBUG "Reading device numbers from flash\n"));
+		if (jffs2_read_dnode(c, f->metadata, (char *)&rdev, 0, sizeof(rdev)) < 0) {
+			/* Eep */
+			printk(KERN_NOTICE "Read device numbers for inode %lu failed\n", (unsigned long)inode->i_ino);
+			jffs2_do_clear_inode(c, f);
+			make_bad_inode(inode);
+			up(&f->sem);
+			return;
+		}			
+
+	case S_IFSOCK:
+	case S_IFIFO:
+		inode->i_op = &jffs2_file_inode_operations;
+		init_special_inode(inode, inode->i_mode, kdev_t_to_nr(mk_kdev(rdev>>8, rdev&0xff)));
+		break;
+
+	default:
+		printk(KERN_WARNING "jffs2_read_inode(): Bogus imode %o for ino %lu\n", inode->i_mode, (unsigned long)inode->i_ino);
+	}
+
+	up(&f->sem);
+
+	D1(printk(KERN_DEBUG "jffs2_read_inode() returning\n"));
+}
+
+
+int jffs2_remount_fs (struct super_block *sb, int *flags, char *data)
+{
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
+
+	if (c->flags & JFFS2_SB_FLAG_RO && !(sb->s_flags & MS_RDONLY))
+		return -EROFS;
+
+	/* We stop if it was running, then restart if it needs to.
+	   This also catches the case where it was stopped and this
+	   is just a remount to restart it */
+	if (!(sb->s_flags & MS_RDONLY))
+		jffs2_stop_garbage_collect_thread(c);
+
+	if (!(*flags & MS_RDONLY))
+		jffs2_start_garbage_collect_thread(c);
+	
+	sb->s_flags = (sb->s_flags & ~MS_RDONLY)|(*flags & MS_RDONLY);
+
+	return 0;
+}
+
+void jffs2_write_super (struct super_block *sb)
+{
+	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
+	sb->s_dirt = 0;
+
+	if (sb->s_flags & MS_RDONLY)
+		return;
+
+	D1(printk("jffs2_write_super(): flush_wbuf before gc-trigger\n"));
+	jffs2_flush_wbuf(c, 2);
+	jffs2_garbage_collect_trigger(c);
+	jffs2_erase_pending_blocks(c);
+	jffs2_mark_erased_blocks(c);
+}
+
+
+/* jffs2_new_inode: allocate a new inode and inocache, add it to the hash,
+   fill in the raw_inode while you're at it. */
+struct inode *jffs2_new_inode (struct inode *dir_i, int mode, struct jffs2_raw_inode *ri)
+{
+	struct inode *inode;
+	struct super_block *sb = dir_i->i_sb;
+	struct jffs2_sb_info *c;
+	struct jffs2_inode_info *f;
+	int ret;
+
+	D1(printk(KERN_DEBUG "jffs2_new_inode(): dir_i %ld, mode 0x%x\n", dir_i->i_ino, mode));
+
+	c = JFFS2_SB_INFO(sb);
+	
+	inode = new_inode(sb);
+	
+	if (!inode)
+		return ERR_PTR(-ENOMEM);
+
+	f = JFFS2_INODE_INFO(inode);
+	jffs2_init_inode_info(f);
+
+	memset(ri, 0, sizeof(*ri));
+	/* Set OS-specific defaults for new inodes */
+	ri->uid = current->fsuid;
+
+	if (dir_i->i_mode & S_ISGID) {
+		ri->gid = dir_i->i_gid;
+		if (S_ISDIR(mode))
+			ri->mode |= S_ISGID;
+	} else {
+		ri->gid = current->fsgid;
+	}
+	ri->mode = mode;
+	ret = jffs2_do_new_inode (c, f, mode, ri);
+	if (ret) {
+		make_bad_inode(inode);
+		iput(inode);
+		return ERR_PTR(ret);
+	}
+	inode->i_nlink = 1;
+	inode->i_ino = ri->ino;
+	inode->i_mode = ri->mode;
+	inode->i_gid = ri->gid;
+	inode->i_uid = ri->uid;
+	inode->i_atime = inode->i_ctime = inode->i_mtime = 
+		ri->atime = ri->mtime = ri->ctime = CURRENT_TIME;
+	inode->i_blksize = PAGE_SIZE;
+	inode->i_blocks = 0;
+	inode->i_size = 0;
+
+	insert_inode_hash(inode);
+
+	return inode;
+}
+
+
+int jffs2_do_fill_super(struct super_block *sb, void *data, int silent)
+{
+	struct jffs2_sb_info *c;
+	struct inode *root_i;
+
+	c = JFFS2_SB_INFO(sb);
+
+	c->sector_size = c->mtd->erasesize;
+	c->flash_size = c->mtd->size;
+
+	if (c->sector_size < 0x10000) {
+		printk(KERN_INFO "jffs2: Erase block size too small (%dKiB). Using 64KiB instead\n",
+		       c->sector_size / 1024);
+		c->sector_size = 0x10000;
+	}
+	if (c->flash_size < 5*c->sector_size) {
+		printk(KERN_ERR "jffs2: Too few erase blocks (%d)\n",
+		       c->flash_size / c->sector_size);
+		return -EINVAL;
+	}
+	if (c->mtd->type == MTD_NANDFLASH) {
+		/* Initialise write buffer */
+		c->wbuf_pagesize = c->mtd->oobblock;
+		c->wbuf_ofs = 0xFFFFFFFF;
+		c->wbuf = kmalloc(c->wbuf_pagesize, GFP_KERNEL);
+		if (!c->wbuf)
+			goto out_mtd;
+	}
+
+	if (jffs2_do_mount_fs(c))
+		goto out_mtd;
+
+	D1(printk(KERN_DEBUG "jffs2_do_fill_super(): Getting root inode\n"));
+	root_i = iget(sb, 1);
+	if (is_bad_inode(root_i)) {
+		D1(printk(KERN_WARNING "get root inode failed\n"));
+		goto out_nodes;
+	}
+
+	D1(printk(KERN_DEBUG "jffs2_do_fill_super(): d_alloc_root()\n"));
+	sb->s_root = d_alloc_root(root_i);
+	if (!sb->s_root)
+		goto out_root_i;
+
+#if LINUX_VERSION_CODE >= 0x20403
+	sb->s_maxbytes = 0xFFFFFFFF;
+#endif
+	sb->s_blocksize = PAGE_CACHE_SIZE;
+	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
+	sb->s_magic = JFFS2_SUPER_MAGIC;
+	if (!(sb->s_flags & MS_RDONLY))
+		jffs2_start_garbage_collect_thread(c);
+	return 0;
+
+ out_root_i:
+	iput(root_i);
+ out_nodes:
+	jffs2_free_ino_caches(c);
+	jffs2_free_raw_node_refs(c);
+	kfree(c->blocks);
+ out_mtd:
+	return -EINVAL;
+}
diff -Nru a/fs/jffs2/gc.c b/fs/jffs2/gc.c
--- a/fs/jffs2/gc.c	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/gc.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,45 +31,47 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: gc.c,v 1.52.2.2 2002/02/23 14:25:36 dwmw2 Exp $
+ * $Id: gc.c,v 1.68 2002/03/08 15:11:24 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
 #include <linux/mtd/mtd.h>
 #include <linux/slab.h>
-#include <linux/jffs2.h>
-#include <linux/time.h>
 #include <linux/interrupt.h>
 #include <linux/pagemap.h>
 #include <linux/crc32.h>
 #include "nodelist.h"
 
 static int jffs2_garbage_collect_metadata(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, 
-					struct inode *inode, struct jffs2_full_dnode *fd);
+					struct jffs2_inode_info *f, struct jffs2_full_dnode *fd);
 static int jffs2_garbage_collect_dirent(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, 
-					struct inode *inode, struct jffs2_full_dirent *fd);
+					struct jffs2_inode_info *f, struct jffs2_full_dirent *fd);
 static int jffs2_garbage_collect_deletion_dirent(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, 
-					struct inode *inode, struct jffs2_full_dirent *fd);
+					struct jffs2_inode_info *f, struct jffs2_full_dirent *fd);
 static int jffs2_garbage_collect_hole(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb,
-				      struct inode *indeo, struct jffs2_full_dnode *fn,
-				      __u32 start, __u32 end);
+				      struct jffs2_inode_info *f, struct jffs2_full_dnode *fn,
+				      uint32_t start, uint32_t end);
 static int jffs2_garbage_collect_dnode(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb,
-				       struct inode *inode, struct jffs2_full_dnode *fn,
-				       __u32 start, __u32 end);
+				       struct jffs2_inode_info *f, struct jffs2_full_dnode *fn,
+				       uint32_t start, uint32_t end);
 
 /* Called with erase_completion_lock held */
 static struct jffs2_eraseblock *jffs2_find_gc_block(struct jffs2_sb_info *c)
 {
 	struct jffs2_eraseblock *ret;
 	struct list_head *nextlist = NULL;
+	int n = jiffies % 128;
 
 	/* Pick an eraseblock to garbage collect next. This is where we'll
 	   put the clever wear-levelling algorithms. Eventually.  */
 	if (!list_empty(&c->bad_used_list) && c->nr_free_blocks > JFFS2_RESERVED_BLOCKS_GCBAD) {
 		D1(printk(KERN_DEBUG "Picking block from bad_used_list to GC next\n"));
 		nextlist = &c->bad_used_list;
-	} else if (jiffies % 100 && !list_empty(&c->dirty_list)) {
+	} else if (n < 100 && !list_empty(&c->erasable_list)) {
+		D1(printk(KERN_DEBUG "Picking block from erasable_list to GC next\n"));
+		nextlist = &c->erasable_list;
+	} else if (n < 126 && !list_empty(&c->dirty_list)) {
 		/* Most of the time, pick one off the dirty list */
 		D1(printk(KERN_DEBUG "Picking block from dirty_list to GC next\n"));
 		nextlist = &c->dirty_list;
@@ -80,9 +82,13 @@
 		D1(printk(KERN_DEBUG "Picking block from dirty_list to GC next (clean_list was empty)\n"));
 
 		nextlist = &c->dirty_list;
+	} else if (!list_empty(&c->erasable_list)) {
+		D1(printk(KERN_DEBUG "Picking block from erasable_list to GC next (clean_list and dirty_list were empty)\n"));
+
+		nextlist = &c->erasable_list;
 	} else {
 		/* Eep. Both were empty */
-		printk(KERN_NOTICE "jffs2: No clean _or_ dirty blocks to GC from! Where are they all?\n");
+		printk(KERN_NOTICE "jffs2: No clean, dirty _or_ erasable blocks to GC from! Where are they all?\n");
 		return NULL;
 	}
 
@@ -109,8 +115,8 @@
 	struct jffs2_node_frag *frag;
 	struct jffs2_full_dnode *fn = NULL;
 	struct jffs2_full_dirent *fd;
-	__u32 start = 0, end = 0, nrfrags = 0;
-	__u32 inum;
+	uint32_t start = 0, end = 0, nrfrags = 0;
+	uint32_t inum;
 	struct inode *inode;
 	int ret = 0;
 
@@ -154,6 +160,8 @@
 	D1(printk(KERN_DEBUG "Going to garbage collect node at 0x%08x\n", raw->flash_offset &~3));
 	if (!raw->next_in_ino) {
 		/* Inode-less node. Clean marker, snapshot or something like that */
+		/* FIXME: If it's something that needs to be copied, including something
+		   we don't grok that has JFFS2_NODETYPE_RWCOMPAT_COPY, we should do so */
 		spin_unlock_bh(&c->erase_completion_lock);
 		jffs2_mark_node_obsolete(c, raw);
 		goto eraseit_lock;
@@ -177,6 +185,7 @@
 
 	f = JFFS2_INODE_INFO(inode);
 	down(&f->sem);
+
 	/* Now we have the lock for this inode. Check that it's still the one at the head
 	   of the list. */
 
@@ -188,7 +197,7 @@
 	/* OK. Looks safe. And nobody can get us now because we have the semaphore. Move the block */
 	if (f->metadata && f->metadata->raw == raw) {
 		fn = f->metadata;
-		ret = jffs2_garbage_collect_metadata(c, jeb, inode, fn);
+		ret = jffs2_garbage_collect_metadata(c, jeb, f, fn);
 		goto upnout;
 	}
 	
@@ -206,10 +215,10 @@
 		/* We found a datanode. Do the GC */
 		if((start >> PAGE_CACHE_SHIFT) < ((end-1) >> PAGE_CACHE_SHIFT)) {
 			/* It crosses a page boundary. Therefore, it must be a hole. */
-			ret = jffs2_garbage_collect_hole(c, jeb, inode, fn, start, end);
+			ret = jffs2_garbage_collect_hole(c, jeb, f, fn, start, end);
 		} else {
 			/* It could still be a hole. But we GC the page this way anyway */
-			ret = jffs2_garbage_collect_dnode(c, jeb, inode, fn, start, end);
+			ret = jffs2_garbage_collect_dnode(c, jeb, f, fn, start, end);
 		}
 		goto upnout;
 	}
@@ -221,11 +230,12 @@
 	}
 
 	if (fd && fd->ino) {
-		ret = jffs2_garbage_collect_dirent(c, jeb, inode, fd);
+		ret = jffs2_garbage_collect_dirent(c, jeb, f, fd);
 	} else if (fd) {
-		ret = jffs2_garbage_collect_deletion_dirent(c, jeb, inode, fd);
+		ret = jffs2_garbage_collect_deletion_dirent(c, jeb, f, fd);
 	} else {
-		printk(KERN_WARNING "Raw node at 0x%08x wasn't in node lists for ino #%lu\n", raw->flash_offset&~3, inode->i_ino);
+		printk(KERN_WARNING "Raw node at 0x%08x wasn't in node lists for ino #%u\n",
+		       raw->flash_offset&~3, f->inocache->ino);
 		if (raw->flash_offset & 1) {
 			printk(KERN_WARNING "But it's obsolete so we don't mind too much\n");
 		} else {
@@ -256,24 +266,25 @@
 }
 
 static int jffs2_garbage_collect_metadata(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, 
-					struct inode *inode, struct jffs2_full_dnode *fn)
+					struct jffs2_inode_info *f, struct jffs2_full_dnode *fn)
 {
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_full_dnode *new_fn;
 	struct jffs2_raw_inode ri;
 	unsigned short dev;
 	char *mdata = NULL, mdatalen = 0;
-	__u32 alloclen, phys_ofs;
+	uint32_t alloclen, phys_ofs;
 	int ret;
 
-	if (S_ISBLK(inode->i_mode) || S_ISCHR(inode->i_mode)) {
+	if (S_ISBLK(JFFS2_F_I_MODE(f)) ||
+	    S_ISCHR(JFFS2_F_I_MODE(f)) ) {
 		/* For these, we don't actually need to read the old node */
-		dev =  (major(inode->i_rdev) << 8) | 
-			minor(inode->i_rdev);
+		/* FIXME: for minor or major > 255. */
+		dev =  ((JFFS2_F_I_RDEV_MAJ(f) << 8) | 
+			JFFS2_F_I_RDEV_MIN(f));
 		mdata = (char *)&dev;
 		mdatalen = sizeof(dev);
 		D1(printk(KERN_DEBUG "jffs2_garbage_collect_metadata(): Writing %d bytes of kdev_t\n", mdatalen));
-	} else if (S_ISLNK(inode->i_mode)) {
+	} else if (S_ISLNK(JFFS2_F_I_MODE(f))) {
 		mdatalen = fn->size;
 		mdata = kmalloc(fn->size, GFP_KERNEL);
 		if (!mdata) {
@@ -303,15 +314,15 @@
 	ri.totlen = sizeof(ri) + mdatalen;
 	ri.hdr_crc = crc32(0, &ri, sizeof(struct jffs2_unknown_node)-4);
 
-	ri.ino = inode->i_ino;
+	ri.ino = f->inocache->ino;
 	ri.version = ++f->highest_version;
-	ri.mode = inode->i_mode;
-	ri.uid = inode->i_uid;
-	ri.gid = inode->i_gid;
-	ri.isize = inode->i_size;
-	ri.atime = inode->i_atime;
-	ri.ctime = inode->i_ctime;
-	ri.mtime = inode->i_mtime;
+	ri.mode = JFFS2_F_I_MODE(f);
+	ri.uid = JFFS2_F_I_UID(f);
+	ri.gid = JFFS2_F_I_GID(f);
+	ri.isize = JFFS2_F_I_SIZE(f);
+	ri.atime = JFFS2_F_I_ATIME(f);
+	ri.ctime = JFFS2_F_I_CTIME(f);
+	ri.mtime = JFFS2_F_I_MTIME(f);
 	ri.offset = 0;
 	ri.csize = mdatalen;
 	ri.dsize = mdatalen;
@@ -319,7 +330,7 @@
 	ri.node_crc = crc32(0, &ri, sizeof(ri)-8);
 	ri.data_crc = crc32(0, mdata, mdatalen);
 
-	new_fn = jffs2_write_dnode(inode, &ri, mdata, mdatalen, phys_ofs, NULL);
+	new_fn = jffs2_write_dnode(c, f, &ri, mdata, mdatalen, phys_ofs, NULL);
 
 	if (IS_ERR(new_fn)) {
 		printk(KERN_WARNING "Error writing new dnode: %ld\n", PTR_ERR(new_fn));
@@ -330,18 +341,17 @@
 	jffs2_free_full_dnode(fn);
 	f->metadata = new_fn;
  out:
-	if (S_ISLNK(inode->i_mode))
+	if (S_ISLNK(JFFS2_F_I_MODE(f)))
 		kfree(mdata);
 	return ret;
 }
 
 static int jffs2_garbage_collect_dirent(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, 
-					struct inode *inode, struct jffs2_full_dirent *fd)
+					struct jffs2_inode_info *f, struct jffs2_full_dirent *fd)
 {
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_full_dirent *new_fd;
 	struct jffs2_raw_dirent rd;
-	__u32 alloclen, phys_ofs;
+	uint32_t alloclen, phys_ofs;
 	int ret;
 
 	rd.magic = JFFS2_MAGIC_BITMASK;
@@ -350,10 +360,10 @@
 	rd.totlen = sizeof(rd) + rd.nsize;
 	rd.hdr_crc = crc32(0, &rd, sizeof(struct jffs2_unknown_node)-4);
 
-	rd.pino = inode->i_ino;
+	rd.pino = f->inocache->ino;
 	rd.version = ++f->highest_version;
 	rd.ino = fd->ino;
-	rd.mctime = max(inode->i_mtime, inode->i_ctime);
+	rd.mctime = max(JFFS2_F_I_MTIME(f), JFFS2_F_I_CTIME(f));
 	rd.type = fd->type;
 	rd.node_crc = crc32(0, &rd, sizeof(rd)-8);
 	rd.name_crc = crc32(0, fd->name, rd.nsize);
@@ -364,7 +374,7 @@
 		       sizeof(rd)+rd.nsize, ret);
 		return ret;
 	}
-	new_fd = jffs2_write_dirent(inode, &rd, fd->name, rd.nsize, phys_ofs, NULL);
+	new_fd = jffs2_write_dirent(c, f, &rd, fd->name, rd.nsize, phys_ofs, NULL);
 
 	if (IS_ERR(new_fd)) {
 		printk(KERN_WARNING "jffs2_write_dirent in garbage_collect_dirent failed: %ld\n", PTR_ERR(new_fd));
@@ -375,19 +385,119 @@
 }
 
 static int jffs2_garbage_collect_deletion_dirent(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, 
-					struct inode *inode, struct jffs2_full_dirent *fd)
+					struct jffs2_inode_info *f, struct jffs2_full_dirent *fd)
 {
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_full_dirent **fdp = &f->dents;
 	int found = 0;
 
-	/* FIXME: When we run on NAND flash, we need to work out whether
-	   this deletion dirent is still needed to actively delete a
-	   'real' dirent with the same name that's still somewhere else
-	   on the flash. For now, we know that we've actually obliterated
-	   all the older dirents when they became obsolete, so we didn't
-	   really need to write the deletion to flash in the first place.
-	*/
+	/* On a medium where we can't actually mark nodes obsolete
+	   pernamently, such as NAND flash, we need to work out
+	   whether this deletion dirent is still needed to actively
+	   delete a 'real' dirent with the same name that's still
+	   somewhere else on the flash. */
+	if (!jffs2_can_mark_obsolete(c)) {
+		struct jffs2_raw_dirent rd;
+		struct jffs2_raw_node_ref *raw;
+		int ret;
+		size_t retlen;
+		int name_len = strlen(fd->name);
+		uint32_t name_crc = crc32(0, fd->name, name_len);
+		char *namebuf = NULL;
+
+		/* Prevent the erase code from nicking the obsolete node refs while
+		   we're looking at them. I really don't like this extra lock but
+		   can't see any alternative. Suggestions on a postcard to... */
+		down(&c->erase_free_sem);
+
+		for (raw = f->inocache->nodes; raw != (void *)f->inocache; raw = raw->next_in_ino) {
+			/* We only care about obsolete ones */
+			if (!(raw->flash_offset & 1))
+				continue;
+
+			/* Doesn't matter if there's one in the same erase block. We're going to 
+			   delete it too at the same time. */
+			if ((raw->flash_offset & ~(c->sector_size-1)) ==
+			    (fd->raw->flash_offset & ~(c->sector_size-1)))
+				continue;
+
+			/* This is an obsolete node belonging to the same directory */
+			ret = jffs2_flash_read(c, raw->flash_offset & ~3, sizeof(struct jffs2_unknown_node), &retlen, (char *)&rd);
+			if (ret) {
+				printk(KERN_WARNING "jffs2_g_c_deletion_dirent(): Read error (%d) reading header from obsolete node at %08x\n", ret, raw->flash_offset & ~3);
+				/* If we can't read it, we don't need to continune to obsolete it. Continue */
+				continue;
+			}
+			if (retlen != sizeof(struct jffs2_unknown_node)) {
+				printk(KERN_WARNING "jffs2_g_c_deletion_dirent(): Short read (%d not %d) reading header from obsolete node at %08x\n",
+				       retlen, sizeof(struct jffs2_unknown_node), raw->flash_offset & ~3);
+				continue;
+			}
+			if (rd.nodetype != JFFS2_NODETYPE_DIRENT ||
+			    PAD(rd.totlen) != PAD(sizeof(rd) + name_len))
+				continue;
+
+			/* OK, it's a dirent node, it's the right length. We have to take a 
+			   closer look at it... */
+			ret = jffs2_flash_read(c, raw->flash_offset & ~3, sizeof(rd), &retlen, (char *)&rd);
+			if (ret) {
+				printk(KERN_WARNING "jffs2_g_c_deletion_dirent(): Read error (%d) reading from obsolete node at %08x\n", ret, raw->flash_offset & ~3);
+				/* If we can't read it, we don't need to continune to obsolete it. Continue */
+				continue;
+			}
+			if (retlen != sizeof(struct jffs2_unknown_node)) {
+				printk(KERN_WARNING "jffs2_g_c_deletion_dirent(): Short read (%d not %d) reading from obsolete node at %08x\n",
+				       retlen, sizeof(struct jffs2_unknown_node), raw->flash_offset & ~3);
+				continue;
+			}
+
+			/* If the name CRC doesn't match, skip */
+			if (rd.name_crc != name_crc)
+				continue;
+			/* If the name length doesn't match, or it's another deletion dirent, skip */
+			if (rd.nsize != name_len || !rd.ino)
+				continue;
+
+			/* OK, check the actual name now */
+			if (!namebuf) {
+				namebuf = kmalloc(name_len + 1, GFP_KERNEL);
+				if (!namebuf) {
+					up(&c->erase_free_sem);
+					return -ENOMEM;
+				}
+			}
+			/* We read the extra byte before it so it's a word-aligned read */
+			ret = jffs2_flash_read(c, (raw->flash_offset & ~3)+sizeof(rd)-1, name_len+1, &retlen, namebuf);
+			if (ret) {
+				printk(KERN_WARNING "jffs2_g_c_deletion_dirent(): Read error (%d) reading name from obsolete node at %08x\n", ret, raw->flash_offset & ~3);
+				/* If we can't read it, we don't need to continune to obsolete it. Continue */
+				continue;
+			}
+			if (retlen != sizeof(rd)) {
+				printk(KERN_WARNING "jffs2_g_c_deletion_dirent(): Short read (%d not %d) reading name from obsolete node at %08x\n",
+				       retlen, name_len, raw->flash_offset & ~3);
+				continue;
+			}
+			if (memcmp(namebuf+1, fd->name, name_len))
+				continue;
+
+			/* OK. The name really does match. There really is still an older node on
+			   the flash which our deletion dirent obsoletes. So we have to write out
+			   a new deletion dirent to replace it */
+			
+			if (namebuf)
+				kfree(namebuf);
+
+			up(&c->erase_free_sem);
+			return jffs2_garbage_collect_dirent(c, jeb, f, fd);
+		}
+
+		up(&c->erase_free_sem);
+
+		if (namebuf) 
+			kfree(namebuf);
+	}
+
+	/* No need for it any more. Just mark it obsolete and remove it from the list */
 	while (*fdp) {
 		if ((*fdp) == fd) {
 			found = 1;
@@ -397,7 +507,7 @@
 		fdp = &(*fdp)->next;
 	}
 	if (!found) {
-		printk(KERN_WARNING "Deletion dirent \"%s\" not found in list for ino #%lu\n", fd->name, inode->i_ino);
+		printk(KERN_WARNING "Deletion dirent \"%s\" not found in list for ino #%u\n", fd->name, f->inocache->ino);
 	}
 	jffs2_mark_node_obsolete(c, fd->raw);
 	jffs2_free_full_dirent(fd);
@@ -405,27 +515,26 @@
 }
 
 static int jffs2_garbage_collect_hole(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb,
-				      struct inode *inode, struct jffs2_full_dnode *fn,
-				      __u32 start, __u32 end)
+				      struct jffs2_inode_info *f, struct jffs2_full_dnode *fn,
+				      uint32_t start, uint32_t end)
 {
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_raw_inode ri;
 	struct jffs2_node_frag *frag;
 	struct jffs2_full_dnode *new_fn;
-	__u32 alloclen, phys_ofs;
+	uint32_t alloclen, phys_ofs;
 	int ret;
 
-	D1(printk(KERN_DEBUG "Writing replacement hole node for ino #%lu from offset 0x%x to 0x%x\n",
-		  inode->i_ino, start, end));
+	D1(printk(KERN_DEBUG "Writing replacement hole node for ino #%u from offset 0x%x to 0x%x\n",
+		  f->inocache->ino, start, end));
 	
 	memset(&ri, 0, sizeof(ri));
 
 	if(fn->frags > 1) {
 		size_t readlen;
-		__u32 crc;
+		uint32_t crc;
 		/* It's partially obsoleted by a later write. So we have to 
 		   write it out again with the _same_ version as before */
-		ret = c->mtd->read(c->mtd, fn->raw->flash_offset & ~3, sizeof(ri), &readlen, (char *)&ri);
+		ret = jffs2_flash_read(c, fn->raw->flash_offset & ~3, sizeof(ri), &readlen, (char *)&ri);
 		if (readlen != sizeof(ri) || ret) {
 			printk(KERN_WARNING "Node read failed in jffs2_garbage_collect_hole. Ret %d, retlen %d. Data will be lost by writing new hold node\n", ret, readlen);
 			goto fill;
@@ -445,14 +554,14 @@
 			printk(KERN_WARNING "jffs2_garbage_collect_hole: Node at 0x%08x had CRC 0x%08x which doesn't match calculated CRC 0x%08x\n",
 			       fn->raw->flash_offset & ~3, ri.node_crc, crc);
 			/* FIXME: We could possibly deal with this by writing new holes for each frag */
-			printk(KERN_WARNING "Data in the range 0x%08x to 0x%08x of inode #%lu will be lost\n", 
-			       start, end, inode->i_ino);
+			printk(KERN_WARNING "Data in the range 0x%08x to 0x%08x of inode #%u will be lost\n", 
+			       start, end, f->inocache->ino);
 			goto fill;
 		}
 		if (ri.compr != JFFS2_COMPR_ZERO) {
 			printk(KERN_WARNING "jffs2_garbage_collect_hole: Node 0x%08x wasn't a hole node!\n", fn->raw->flash_offset & ~3);
-			printk(KERN_WARNING "Data in the range 0x%08x to 0x%08x of inode #%lu will be lost\n", 
-			       start, end, inode->i_ino);
+			printk(KERN_WARNING "Data in the range 0x%08x to 0x%08x of inode #%u will be lost\n", 
+			       start, end, f->inocache->ino);
 			goto fill;
 		}
 	} else {
@@ -462,20 +571,20 @@
 		ri.totlen = sizeof(ri);
 		ri.hdr_crc = crc32(0, &ri, sizeof(struct jffs2_unknown_node)-4);
 
-		ri.ino = inode->i_ino;
+		ri.ino = f->inocache->ino;
 		ri.version = ++f->highest_version;
 		ri.offset = start;
 		ri.dsize = end - start;
 		ri.csize = 0;
 		ri.compr = JFFS2_COMPR_ZERO;
 	}
-	ri.mode = inode->i_mode;
-	ri.uid = inode->i_uid;
-	ri.gid = inode->i_gid;
-	ri.isize = inode->i_size;
-	ri.atime = inode->i_atime;
-	ri.ctime = inode->i_ctime;
-	ri.mtime = inode->i_mtime;
+	ri.mode = JFFS2_F_I_MODE(f);
+	ri.uid = JFFS2_F_I_UID(f);
+	ri.gid = JFFS2_F_I_GID(f);
+	ri.isize = JFFS2_F_I_SIZE(f);
+	ri.atime = JFFS2_F_I_ATIME(f);
+	ri.ctime = JFFS2_F_I_CTIME(f);
+	ri.mtime = JFFS2_F_I_MTIME(f);
 	ri.data_crc = 0;
 	ri.node_crc = crc32(0, &ri, sizeof(ri)-8);
 
@@ -485,7 +594,7 @@
 		       sizeof(ri), ret);
 		return ret;
 	}
-	new_fn = jffs2_write_dnode(inode, &ri, NULL, 0, phys_ofs, NULL);
+	new_fn = jffs2_write_dnode(c, f, &ri, NULL, 0, phys_ofs, NULL);
 
 	if (IS_ERR(new_fn)) {
 		printk(KERN_WARNING "Error writing new hole node: %ld\n", PTR_ERR(new_fn));
@@ -525,23 +634,22 @@
 }
 
 static int jffs2_garbage_collect_dnode(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb,
-				       struct inode *inode, struct jffs2_full_dnode *fn,
-				       __u32 start, __u32 end)
+				       struct jffs2_inode_info *f, struct jffs2_full_dnode *fn,
+				       uint32_t start, uint32_t end)
 {
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_full_dnode *new_fn;
 	struct jffs2_raw_inode ri;
-	__u32 alloclen, phys_ofs, offset, orig_end;	
+	uint32_t alloclen, phys_ofs, offset, orig_end;	
 	int ret = 0;
 	unsigned char *comprbuf = NULL, *writebuf;
 	struct page *pg;
 	unsigned char *pg_ptr;
-
+	/* FIXME: */ struct inode *inode = OFNI_EDONI_2SFFJ(f);
 
 	memset(&ri, 0, sizeof(ri));
 
-	D1(printk(KERN_DEBUG "Writing replacement dnode for ino #%lu from offset 0x%x to 0x%x\n",
-		  inode->i_ino, start, end));
+	D1(printk(KERN_DEBUG "Writing replacement dnode for ino #%u from offset 0x%x to 0x%x\n",
+		  f->inocache->ino, start, end));
 
 	orig_end = end;
 
@@ -561,7 +669,7 @@
 		/* Shitloads of space */
 		/* FIXME: Integrate this properly with GC calculations */
 		start &= ~(PAGE_CACHE_SIZE-1);
-		end = min_t(__u32, start + PAGE_CACHE_SIZE, inode->i_size);
+		end = min_t(uint32_t, start + PAGE_CACHE_SIZE, JFFS2_F_I_SIZE(f));
 		D1(printk(KERN_DEBUG "Plenty of free space, so expanding to write from offset 0x%x to 0x%x\n",
 			  start, end));
 		if (end < orig_end) {
@@ -588,8 +696,8 @@
 
 	offset = start;
 	while(offset < orig_end) {
-		__u32 datalen;
-		__u32 cdatalen;
+		uint32_t datalen;
+		uint32_t cdatalen;
 		char comprtype = JFFS2_COMPR_NONE;
 
 		ret = jffs2_reserve_space_gc(c, sizeof(ri) + JFFS2_MIN_DATA_LEN, &phys_ofs, &alloclen);
@@ -617,15 +725,15 @@
 		ri.totlen = sizeof(ri) + cdatalen;
 		ri.hdr_crc = crc32(0, &ri, sizeof(struct jffs2_unknown_node)-4);
 
-		ri.ino = inode->i_ino;
+		ri.ino = f->inocache->ino;
 		ri.version = ++f->highest_version;
-		ri.mode = inode->i_mode;
-		ri.uid = inode->i_uid;
-		ri.gid = inode->i_gid;
-		ri.isize = inode->i_size;
-		ri.atime = inode->i_atime;
-		ri.ctime = inode->i_ctime;
-		ri.mtime = inode->i_mtime;
+		ri.mode = JFFS2_F_I_MODE(f);
+		ri.uid = JFFS2_F_I_UID(f);
+		ri.gid = JFFS2_F_I_GID(f);
+		ri.isize = JFFS2_F_I_SIZE(f);
+		ri.atime = JFFS2_F_I_ATIME(f);
+		ri.ctime = JFFS2_F_I_CTIME(f);
+		ri.mtime = JFFS2_F_I_MTIME(f);
 		ri.offset = offset;
 		ri.csize = cdatalen;
 		ri.dsize = datalen;
@@ -633,7 +741,7 @@
 		ri.node_crc = crc32(0, &ri, sizeof(ri)-8);
 		ri.data_crc = crc32(0, writebuf, cdatalen);
 	
-		new_fn = jffs2_write_dnode(inode, &ri, writebuf, cdatalen, phys_ofs, NULL);
+		new_fn = jffs2_write_dnode(c, f, &ri, writebuf, cdatalen, phys_ofs, NULL);
 
 		if (IS_ERR(new_fn)) {
 			printk(KERN_WARNING "Error writing new dnode: %ld\n", PTR_ERR(new_fn));
diff -Nru a/fs/jffs2/malloc.c b/fs/jffs2/malloc.c
--- a/fs/jffs2/malloc.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/malloc.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,7 +31,7 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: malloc.c,v 1.16 2001/03/15 15:38:24 dwmw2 Exp $
+ * $Id: malloc.c,v 1.21 2002/03/12 17:36:55 dwmw2 Exp $
  *
  */
 
@@ -49,7 +49,6 @@
 
 /* These are initialised to NULL in the kernel startup code.
    If you're porting to other operating systems, beware */
-static kmem_cache_t *jffs2_inode_cachep;
 static kmem_cache_t *full_dnode_slab;
 static kmem_cache_t *raw_dirent_slab;
 static kmem_cache_t *raw_inode_slab;
@@ -58,89 +57,47 @@
 static kmem_cache_t *node_frag_slab;
 static kmem_cache_t *inode_cache_slab;
 
-void jffs2_free_tmp_dnode_info_list(struct jffs2_tmp_dnode_info *tn)
-{
-	struct jffs2_tmp_dnode_info *next;
-
-	while (tn) {
-		next = tn;
-		tn = tn->next;
-		jffs2_free_full_dnode(next->fn);
-		jffs2_free_tmp_dnode_info(next);
-	}
-}
-
-void jffs2_free_full_dirent_list(struct jffs2_full_dirent *fd)
-{
-	struct jffs2_full_dirent *next;
-
-	while (fd) {
-		next = fd->next;
-		jffs2_free_full_dirent(fd);
-		fd = next;
-	}
-}
-
-struct inode *jffs2_alloc_inode(struct super_block *sb)
-{
-	struct jffs2_inode_info *ei;
-	ei = (struct jffs2_inode_info *)kmem_cache_alloc(jffs2_inode_cachep, SLAB_KERNEL);
-	if (!ei)
-		return NULL;
-	return &ei->vfs_inode;
-}
-
-void jffs2_destroy_inode(struct inode *inode)
-{
-	kmem_cache_free(jffs2_inode_cachep, JFFS2_INODE_INFO(inode));
-}
-
-static void init_once(void * foo, kmem_cache_t * cachep, unsigned long flags)
-{
-	struct jffs2_inode_info *ei = (struct jffs2_inode_info *) foo;
-
-	if ((flags & (SLAB_CTOR_VERIFY|SLAB_CTOR_CONSTRUCTOR)) ==
-	    SLAB_CTOR_CONSTRUCTOR) {
-		init_MUTEX(&ei->sem);
-		inode_init_once(&ei->vfs_inode);
-	}
-}
-
 int __init jffs2_create_slab_caches(void)
 {
-	full_dnode_slab = kmem_cache_create("jffs2_full_dnode", sizeof(struct jffs2_full_dnode), 0, JFFS2_SLAB_POISON, NULL, NULL);
+	full_dnode_slab = kmem_cache_create("jffs2_full_dnode", 
+					    sizeof(struct jffs2_full_dnode),
+					    0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (!full_dnode_slab)
 		goto err;
 
-	raw_dirent_slab = kmem_cache_create("jffs2_raw_dirent", sizeof(struct jffs2_raw_dirent), 0, JFFS2_SLAB_POISON, NULL, NULL);
+	raw_dirent_slab = kmem_cache_create("jffs2_raw_dirent",
+					    sizeof(struct jffs2_raw_dirent),
+					    0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (!raw_dirent_slab)
 		goto err;
 
-	raw_inode_slab = kmem_cache_create("jffs2_raw_inode", sizeof(struct jffs2_raw_inode), 0, JFFS2_SLAB_POISON, NULL, NULL);
+	raw_inode_slab = kmem_cache_create("jffs2_raw_inode",
+					   sizeof(struct jffs2_raw_inode),
+					   0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (!raw_inode_slab)
 		goto err;
 
-	tmp_dnode_info_slab = kmem_cache_create("jffs2_tmp_dnode", sizeof(struct jffs2_tmp_dnode_info), 0, JFFS2_SLAB_POISON, NULL, NULL);
+	tmp_dnode_info_slab = kmem_cache_create("jffs2_tmp_dnode",
+						sizeof(struct jffs2_tmp_dnode_info),
+						0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (!tmp_dnode_info_slab)
 		goto err;
 
-	raw_node_ref_slab = kmem_cache_create("jffs2_raw_node_ref", sizeof(struct jffs2_raw_node_ref), 0, JFFS2_SLAB_POISON, NULL, NULL);
+	raw_node_ref_slab = kmem_cache_create("jffs2_raw_node_ref",
+					      sizeof(struct jffs2_raw_node_ref),
+					      0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (!raw_node_ref_slab)
 		goto err;
 
-	node_frag_slab = kmem_cache_create("jffs2_node_frag", sizeof(struct jffs2_node_frag), 0, JFFS2_SLAB_POISON, NULL, NULL);
+	node_frag_slab = kmem_cache_create("jffs2_node_frag",
+					   sizeof(struct jffs2_node_frag),
+					   0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (!node_frag_slab)
 		goto err;
 
-	jffs2_inode_cachep = kmem_cache_create("jffs2_inode_cache",
-					     sizeof(struct jffs2_inode_info),
-					     0, SLAB_HWCACHE_ALIGN,
-					     init_once, NULL);
-	if (!jffs2_inode_cachep)
-		goto err;
-
-	inode_cache_slab = kmem_cache_create("jffs2_inode", sizeof(struct jffs2_inode_cache), 0, JFFS2_SLAB_POISON, NULL, NULL);
-
+	inode_cache_slab = kmem_cache_create("jffs2_inode_cache",
+					     sizeof(struct jffs2_inode_cache),
+					     0, JFFS2_SLAB_POISON, NULL, NULL);
 	if (inode_cache_slab)
 		return 0;
  err:
@@ -164,9 +121,6 @@
 		kmem_cache_destroy(node_frag_slab);
 	if(inode_cache_slab)
 		kmem_cache_destroy(inode_cache_slab);
-	if(jffs2_inode_cachep)
-		kmem_cache_destroy(jffs2_inode_cachep);
-
 }
 
 struct jffs2_full_dirent *jffs2_alloc_full_dirent(int namesize)
diff -Nru a/fs/jffs2/nodelist.c b/fs/jffs2/nodelist.c
--- a/fs/jffs2/nodelist.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/nodelist.c	Fri Mar 15 17:51:01 2002
@@ -31,14 +31,14 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: nodelist.c,v 1.30.2.3 2002/02/23 14:04:44 dwmw2 Exp $
+ * $Id: nodelist.c,v 1.42 2002/03/11 11:17:29 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
-#include <linux/jffs2.h>
 #include <linux/fs.h>
 #include <linux/mtd/mtd.h>
+#include <linux/interrupt.h>
 #include "nodelist.h"
 
 void jffs2_add_fd_to_list(struct jffs2_sb_info *c, struct jffs2_full_dirent *new, struct jffs2_full_dirent **list)
@@ -89,13 +89,37 @@
         *prev = tn;
 }
 
+static void jffs2_free_tmp_dnode_info_list(struct jffs2_tmp_dnode_info *tn)
+{
+	struct jffs2_tmp_dnode_info *next;
+
+	while (tn) {
+		next = tn;
+		tn = tn->next;
+		jffs2_free_full_dnode(next->fn);
+		jffs2_free_tmp_dnode_info(next);
+	}
+}
+
+static void jffs2_free_full_dirent_list(struct jffs2_full_dirent *fd)
+{
+	struct jffs2_full_dirent *next;
+
+	while (fd) {
+		next = fd->next;
+		jffs2_free_full_dirent(fd);
+		fd = next;
+	}
+}
+
+
 /* Get tmp_dnode_info and full_dirent for all non-obsolete nodes associated
    with this ino, returning the former in order of version */
 
 int jffs2_get_inode_nodes(struct jffs2_sb_info *c, ino_t ino, struct jffs2_inode_info *f,
 			  struct jffs2_tmp_dnode_info **tnp, struct jffs2_full_dirent **fdp,
-			  __u32 *highest_version, __u32 *latest_mctime,
-			  __u32 *mctime_ver)
+			  uint32_t *highest_version, uint32_t *latest_mctime,
+			  uint32_t *mctime_ver)
 {
 	struct jffs2_raw_node_ref *ref = f->inocache->nodes;
 	struct jffs2_tmp_dnode_info *tn, *ret_tn = NULL;
@@ -111,6 +135,9 @@
 	if (!f->inocache->nodes) {
 		printk(KERN_WARNING "Eep. no nodes for ino #%lu\n", ino);
 	}
+
+	spin_lock_bh(&c->erase_completion_lock);
+
 	for (ref = f->inocache->nodes; ref && ref->next_in_ino; ref = ref->next_in_ino) {
 		/* Work out whether it's a data node or a dirent node */
 		if (ref->flash_offset & 1) {
@@ -118,7 +145,12 @@
 			D1(printk(KERN_DEBUG "node at 0x%08x is obsoleted. Ignoring.\n", ref->flash_offset &~3));
 			continue;
 		}
-		err = c->mtd->read(c->mtd, (ref->flash_offset & ~3), min(ref->totlen, sizeof(node)), &retlen, (void *)&node);
+		/* We can hold a pointer to a non-obsolete node without the spinlock,
+		   but _obsolete_ nodes may disappear at any time, if the block
+		   they're in gets erased */
+		spin_unlock_bh(&c->erase_completion_lock);
+
+		err = jffs2_flash_read(c, (ref->flash_offset & ~3), min(ref->totlen, sizeof(node)), &retlen, (void *)&node);
 		if (err) {
 			printk(KERN_WARNING "error %d reading node at 0x%08x in get_inode_nodes()\n", err, (ref->flash_offset) & ~3);
 			goto free_out;
@@ -143,8 +175,10 @@
 			if (node.d.version > *highest_version)
 				*highest_version = node.d.version;
 			if (ref->flash_offset & 1) {
-				/* Obsoleted */
-				continue;
+				/* Obsoleted. This cannot happen, surely? dwmw2 20020308 */
+				printk(KERN_ERR "Dirent node at 0x%08x became obsolete while we weren't looking\n",
+				       ref->flash_offset & ~3);
+				BUG();
 			}
 			fd = jffs2_alloc_full_dirent(node.d.nsize+1);
 			if (!fd) {
@@ -167,7 +201,7 @@
 			   dirent we've already read from the flash
 			*/
 			if (retlen > sizeof(struct jffs2_raw_dirent))
-				memcpy(&fd->name[0], &node.d.name[0], min((__u32)node.d.nsize, (retlen-sizeof(struct jffs2_raw_dirent))));
+				memcpy(&fd->name[0], &node.d.name[0], min((uint32_t)node.d.nsize, (retlen-sizeof(struct jffs2_raw_dirent))));
 				
 			/* Do we need to copy any more of the name directly
 			   from the flash?
@@ -175,7 +209,7 @@
 			if (node.d.nsize + sizeof(struct jffs2_raw_dirent) > retlen) {
 				int already = retlen - sizeof(struct jffs2_raw_dirent);
 					
-				err = c->mtd->read(c->mtd, (ref->flash_offset & ~3) + retlen, 
+				err = jffs2_flash_read(c, (ref->flash_offset & ~3) + retlen, 
 						   node.d.nsize - already, &retlen, &fd->name[already]);
 				if (!err && retlen != node.d.nsize - already)
 					err = -EIO;
@@ -207,9 +241,10 @@
 			D1(printk(KERN_DEBUG "version %d, highest_version now %d\n", node.d.version, *highest_version));
 
 			if (ref->flash_offset & 1) {
-				D1(printk(KERN_DEBUG "obsoleted\n"));
-				/* Obsoleted */
-				continue;
+				/* Obsoleted. This cannot happen, surely? dwmw2 20020308 */
+				printk(KERN_ERR "Inode node at 0x%08x became obsolete while we weren't looking\n",
+				       ref->flash_offset & ~3);
+				BUG();
 			}
 			tn = jffs2_alloc_tmp_dnode_info();
 			if (!tn) {
@@ -254,7 +289,10 @@
 				break;
 			}
 		}
+		spin_lock_bh(&c->erase_completion_lock);
+
 	}
+	spin_unlock_bh(&c->erase_completion_lock);
 	*tnp = ret_tn;
 	*fdp = ret_fd;
 
@@ -272,15 +310,19 @@
 
 	D2(printk(KERN_DEBUG "jffs2_get_ino_cache(): ino %u\n", ino));
 	spin_lock (&c->inocache_lock);
-	ret = c->inocache_list[ino % INOCACHE_HASHSIZE];
-	while (ret && ret->ino < ino) {
-		ret = ret->next;
-	}
 
-	spin_unlock(&c->inocache_lock);
+	if (c->inocache_last && c->inocache_last->ino == ino) {
+		ret = c->inocache_last;
+	} else {
+		ret = c->inocache_list[ino % INOCACHE_HASHSIZE];
+		while (ret && ret->ino < ino) {
+			ret = ret->next;
+		}
 
-	if (ret && ret->ino != ino)
-		ret = NULL;
+		if (ret && ret->ino != ino)
+			ret = NULL;
+	}
+	spin_unlock(&c->inocache_lock);
 
 	D2(printk(KERN_DEBUG "jffs2_get_ino_cache found %p for ino %u\n", ret, ino));
 	return ret;
@@ -299,6 +341,9 @@
 	}
 	new->next = *prev;
 	*prev = new;
+
+	c->inocache_last = new;
+
 	spin_unlock(&c->inocache_lock);
 }
 
@@ -316,6 +361,9 @@
 	if ((*prev) == old) {
 		*prev = old->next;
 	}
+	if (c->inocache_last == old)
+		c->inocache_last = NULL;
+
 	spin_unlock(&c->inocache_lock);
 }
 
@@ -334,6 +382,7 @@
 		}
 		c->inocache_list[i] = NULL;
 	}
+	c->inocache_last = NULL;
 }
 
 void jffs2_free_raw_node_refs(struct jffs2_sb_info *c)
diff -Nru a/fs/jffs2/nodelist.h b/fs/jffs2/nodelist.h
--- a/fs/jffs2/nodelist.h	Fri Mar 15 17:51:03 2002
+++ b/fs/jffs2/nodelist.h	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,16 +31,21 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: nodelist.h,v 1.46.2.1 2002/02/23 14:04:44 dwmw2 Exp $
- * + zlib_init calls from v1.65
+ * $Id: nodelist.h,v 1.68 2002/03/08 11:27:19 dwmw2 Exp $
  *
  */
 
+#ifndef __JFFS2_NODELIST_H__
+#define __JFFS2_NODELIST_H__
+
 #include <linux/config.h>
 #include <linux/fs.h>
 
+#include <linux/mtd/compatmac.h> /* For min/max in older kernels */
+#include <linux/jffs2.h>
 #include <linux/jffs2_fs_sb.h>
 #include <linux/jffs2_fs_i.h>
+#include "os-linux.h"
 
 #ifndef CONFIG_JFFS2_FS_DEBUG
 #define CONFIG_JFFS2_FS_DEBUG 2
@@ -72,10 +77,10 @@
 		for this inode instead. The inode_cache will have NULL in the first
 		word so you know when you've got there :) */
 	struct jffs2_raw_node_ref *next_phys;
-	//	__u32 ino;
-	__u32 flash_offset;
-	__u32 totlen;
-//	__u16 nodetype;
+	//	uint32_t ino;
+	uint32_t flash_offset;
+	uint32_t totlen;
+//	uint16_t nodetype;
 	
         /* flash_offset & 3 always has to be zero, because nodes are
 	   always aligned at 4 bytes. So we have a couple of extra bits
@@ -108,13 +113,16 @@
 		chain. */
 	struct jffs2_inode_cache *next;
 	struct jffs2_raw_node_ref *nodes;
-	__u32 ino;
+	uint32_t ino;
 	int nlink;
 };
 
 struct jffs2_scan_info {
 	struct jffs2_full_dirent *dents;
 	struct jffs2_tmp_dnode_info *tmpnodes;
+	/* Latest i_size info */
+	uint32_t version;
+	uint32_t isize;
 };
 /*
   Larger representation of a raw node, kept in-core only when the 
@@ -124,9 +132,9 @@
 struct jffs2_full_dnode
 {
 	struct jffs2_raw_node_ref *raw;
-	__u32 ofs; /* Don't really need this, but optimisation */
-	__u32 size;
-	__u32 frags; /* Number of fragments which currently refer
+	uint32_t ofs; /* Don't really need this, but optimisation */
+	uint32_t size;
+	uint32_t frags; /* Number of fragments which currently refer
 			to this node. When this reaches zero, 
 			the node is obsolete.
 		     */
@@ -141,15 +149,15 @@
 {
 	struct jffs2_tmp_dnode_info *next;
 	struct jffs2_full_dnode *fn;
-	__u32 version;
+	uint32_t version;
 };       
 
 struct jffs2_full_dirent
 {
 	struct jffs2_raw_node_ref *raw;
 	struct jffs2_full_dirent *next;
-	__u32 version;
-	__u32 ino; /* == zero for unlink */
+	uint32_t version;
+	uint32_t ino; /* == zero for unlink */
 	unsigned int nhash;
 	unsigned char type;
 	unsigned char name[0];
@@ -162,20 +170,20 @@
 {
 	struct jffs2_node_frag *next;
 	struct jffs2_full_dnode *node; /* NULL for holes */
-	__u32 size;
-	__u32 ofs; /* Don't really need this, but optimisation */
-	__u32 node_ofs; /* offset within the physical node */
+	uint32_t size;
+	uint32_t ofs; /* Don't really need this, but optimisation */
+	uint32_t node_ofs; /* offset within the physical node */
 };
 
 struct jffs2_eraseblock
 {
 	struct list_head list;
 	int bad_count;
-	__u32 offset;		/* of this block in the MTD */
+	uint32_t offset;		/* of this block in the MTD */
 
-	__u32 used_size;
-	__u32 dirty_size;
-	__u32 free_size;	/* Note that sector_size - free_size
+	uint32_t used_size;
+	uint32_t dirty_size;
+	uint32_t free_size;	/* Note that sector_size - free_size
 				   is the address of the first free space */
 	struct jffs2_raw_node_ref *first_node;
 	struct jffs2_raw_node_ref *last_node;
@@ -207,7 +215,7 @@
 } while(0)
 
 #define ACCT_PARANOIA_CHECK(jeb) do { \
-		__u32 my_used_size = 0; \
+		uint32_t my_used_size = 0; \
 		struct jffs2_raw_node_ref *ref2 = jeb->first_node; \
 		while (ref2) { \
 			if (!(ref2->flash_offset & 1)) \
@@ -249,8 +257,8 @@
 void jffs2_add_tn_to_list(struct jffs2_tmp_dnode_info *tn, struct jffs2_tmp_dnode_info **list);
 int jffs2_get_inode_nodes(struct jffs2_sb_info *c, ino_t ino, struct jffs2_inode_info *f,
 			  struct jffs2_tmp_dnode_info **tnp, struct jffs2_full_dirent **fdp,
-			  __u32 *highest_version, __u32 *latest_mctime,
-			  __u32 *mctime_ver);
+			  uint32_t *highest_version, uint32_t *latest_mctime,
+			  uint32_t *mctime_ver);
 struct jffs2_inode_cache *jffs2_get_ino_cache(struct jffs2_sb_info *c, int ino);
 void jffs2_add_ino_cache (struct jffs2_sb_info *c, struct jffs2_inode_cache *new);
 void jffs2_del_ino_cache(struct jffs2_sb_info *c, struct jffs2_inode_cache *old);
@@ -258,28 +266,33 @@
 void jffs2_free_raw_node_refs(struct jffs2_sb_info *c);
 
 /* nodemgmt.c */
-int jffs2_reserve_space(struct jffs2_sb_info *c, __u32 minsize, __u32 *ofs, __u32 *len, int prio);
-int jffs2_reserve_space_gc(struct jffs2_sb_info *c, __u32 minsize, __u32 *ofs, __u32 *len);
-int jffs2_add_physical_node_ref(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *new, __u32 len, int dirty);
+int jffs2_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, uint32_t *ofs, uint32_t *len, int prio);
+int jffs2_reserve_space_gc(struct jffs2_sb_info *c, uint32_t minsize, uint32_t *ofs, uint32_t *len);
+int jffs2_add_physical_node_ref(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *new, uint32_t len, int dirty);
 void jffs2_complete_reservation(struct jffs2_sb_info *c);
 void jffs2_mark_node_obsolete(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *raw);
 
 /* write.c */
-struct inode *jffs2_new_inode (struct inode *dir_i, int mode, struct jffs2_raw_inode *ri);
-struct jffs2_full_dnode *jffs2_write_dnode(struct inode *inode, struct jffs2_raw_inode *ri, const unsigned char *data, __u32 datalen, __u32 flash_ofs,  __u32 *writelen);
-struct jffs2_full_dirent *jffs2_write_dirent(struct inode *inode, struct jffs2_raw_dirent *rd, const unsigned char *name, __u32 namelen, __u32 flash_ofs,  __u32 *writelen);
+int jffs2_do_new_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, uint32_t mode, struct jffs2_raw_inode *ri);
+struct jffs2_full_dnode *jffs2_write_dnode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, struct jffs2_raw_inode *ri, const unsigned char *data, uint32_t datalen, uint32_t flash_ofs,  uint32_t *writelen);
+struct jffs2_full_dirent *jffs2_write_dirent(struct jffs2_sb_info *c, struct jffs2_inode_info *f, struct jffs2_raw_dirent *rd, const unsigned char *name, uint32_t namelen, uint32_t flash_ofs,  uint32_t *writelen);
+int jffs2_write_inode_range(struct jffs2_sb_info *c, struct jffs2_inode_info *f,
+			    struct jffs2_raw_inode *ri, unsigned char *buf, 
+			    uint32_t offset, uint32_t writelen, uint32_t *retlen);
+int jffs2_do_create(struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, struct jffs2_inode_info *f, struct jffs2_raw_inode *ri, const char *name, int namelen);
+int jffs2_do_unlink(struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, const char *name, int namelen, struct jffs2_inode_info *dead_f);
+int jffs2_do_link (struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, uint32_t ino, uint8_t type, const char *name, int namelen);
+
 
 /* readinode.c */
-void jffs2_truncate_fraglist (struct jffs2_sb_info *c, struct jffs2_node_frag **list, __u32 size);
+void jffs2_truncate_fraglist (struct jffs2_sb_info *c, struct jffs2_node_frag **list, uint32_t size);
 int jffs2_add_full_dnode_to_fraglist(struct jffs2_sb_info *c, struct jffs2_node_frag **list, struct jffs2_full_dnode *fn);
 int jffs2_add_full_dnode_to_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, struct jffs2_full_dnode *fn);
-void jffs2_read_inode (struct inode *);
-void jffs2_clear_inode (struct inode *);
+int jffs2_do_read_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, 
+			uint32_t ino, struct jffs2_raw_inode *latest_node);
+void jffs2_do_clear_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f);
 
 /* malloc.c */
-void jffs2_free_tmp_dnode_info_list(struct jffs2_tmp_dnode_info *tn);
-void jffs2_free_full_dirent_list(struct jffs2_full_dirent *fd);
-
 int jffs2_create_slab_caches(void);
 void jffs2_destroy_slab_caches(void);
 
@@ -303,47 +316,24 @@
 /* gc.c */
 int jffs2_garbage_collect_pass(struct jffs2_sb_info *c);
 
-/* background.c */
-int jffs2_start_garbage_collect_thread(struct jffs2_sb_info *c);
-void jffs2_stop_garbage_collect_thread(struct jffs2_sb_info *c);
-void jffs2_garbage_collect_trigger(struct jffs2_sb_info *c);
-
-/* dir.c */
-extern struct file_operations jffs2_dir_operations;
-extern struct inode_operations jffs2_dir_inode_operations;
-
-/* file.c */
-extern struct file_operations jffs2_file_operations;
-extern struct inode_operations jffs2_file_inode_operations;
-extern struct address_space_operations jffs2_file_address_operations;
-int jffs2_null_fsync(struct file *, struct dentry *, int);
-int jffs2_setattr (struct dentry *dentry, struct iattr *iattr);
-int jffs2_do_readpage_nolock (struct inode *inode, struct page *pg);
-int jffs2_do_readpage_unlock (struct inode *inode, struct page *pg);
-int jffs2_readpage (struct file *, struct page *);
-int jffs2_prepare_write (struct file *, struct page *, unsigned, unsigned);
-int jffs2_commit_write (struct file *, struct page *, unsigned, unsigned);
-
-/* ioctl.c */
-int jffs2_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
-
 /* read.c */
 int jffs2_read_dnode(struct jffs2_sb_info *c, struct jffs2_full_dnode *fd, unsigned char *buf, int ofs, int len);
+int jffs2_read_inode_range(struct jffs2_sb_info *c, struct jffs2_inode_info *f,
+			   unsigned char *buf, uint32_t offset, uint32_t len);
+char *jffs2_getlink(struct jffs2_sb_info *c, struct jffs2_inode_info *f);
+
 
 /* compr.c */
 unsigned char jffs2_compress(unsigned char *data_in, unsigned char *cpage_out, 
-			     __u32 *datalen, __u32 *cdatalen);
+			     uint32_t *datalen, uint32_t *cdatalen);
 int jffs2_decompress(unsigned char comprtype, unsigned char *cdata_in, 
-		     unsigned char *data_out, __u32 cdatalen, __u32 datalen);
+		     unsigned char *data_out, uint32_t cdatalen, uint32_t datalen);
 
 /* scan.c */
 int jffs2_scan_medium(struct jffs2_sb_info *c);
 
 /* build.c */
-int jffs2_build_filesystem(struct jffs2_sb_info *c);
-
-/* symlink.c */
-extern struct inode_operations jffs2_symlink_inode_operations;
+int jffs2_do_mount_fs(struct jffs2_sb_info *c);
 
 /* erase.c */
 void jffs2_erase_block(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
@@ -351,6 +341,16 @@
 void jffs2_mark_erased_blocks(struct jffs2_sb_info *c);
 void jffs2_erase_pending_trigger(struct jffs2_sb_info *c);
 
+#ifdef CONFIG_JFFS2_FS_NAND
+/* wbuf.c */
+int jffs2_flush_wbuf(struct jffs2_sb_info *c, int pad);
+int jffs2_check_nand_cleanmarker(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
+int jffs2_write_nand_cleanmarker(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
+int jffs2_nand_read_failcnt(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
+#endif
+
 /* compr_zlib.c */
 int jffs2_zlib_init(void);
 void jffs2_zlib_exit(void);
+
+#endif /* __JFFS2_NODELIST_H__ */
diff -Nru a/fs/jffs2/nodemgmt.c b/fs/jffs2/nodemgmt.c
--- a/fs/jffs2/nodemgmt.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/nodemgmt.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,13 +31,12 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: nodemgmt.c,v 1.45.2.1 2002/02/23 14:13:34 dwmw2 Exp $
+ * $Id: nodemgmt.c,v 1.63 2002/03/08 14:54:09 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
 #include <linux/slab.h>
-#include <linux/jffs2.h>
 #include <linux/mtd/mtd.h>
 #include <linux/interrupt.h>
 #include "nodelist.h"
@@ -62,9 +61,9 @@
  *	for the requested allocation.
  */
 
-static int jffs2_do_reserve_space(struct jffs2_sb_info *c,  __u32 minsize, __u32 *ofs, __u32 *len);
+static int jffs2_do_reserve_space(struct jffs2_sb_info *c,  uint32_t minsize, uint32_t *ofs, uint32_t *len);
 
-int jffs2_reserve_space(struct jffs2_sb_info *c, __u32 minsize, __u32 *ofs, __u32 *len, int prio)
+int jffs2_reserve_space(struct jffs2_sb_info *c, uint32_t minsize, uint32_t *ofs, uint32_t *len, int prio)
 {
 	int ret = -EAGAIN;
 	int blocksneeded = JFFS2_RESERVED_BLOCKS_WRITE;
@@ -121,7 +120,7 @@
 	return ret;
 }
 
-int jffs2_reserve_space_gc(struct jffs2_sb_info *c, __u32 minsize, __u32 *ofs, __u32 *len)
+int jffs2_reserve_space_gc(struct jffs2_sb_info *c, uint32_t minsize, uint32_t *ofs, uint32_t *len)
 {
 	int ret = -EAGAIN;
 	minsize = PAD(minsize);
@@ -140,13 +139,21 @@
 }
 
 /* Called with alloc sem _and_ erase_completion_lock */
-static int jffs2_do_reserve_space(struct jffs2_sb_info *c,  __u32 minsize, __u32 *ofs, __u32 *len)
+static int jffs2_do_reserve_space(struct jffs2_sb_info *c,  uint32_t minsize, uint32_t *ofs, uint32_t *len)
 {
 	struct jffs2_eraseblock *jeb = c->nextblock;
 	
  restart:
 	if (jeb && minsize > jeb->free_size) {
 		/* Skip the end of this block and file it as having some dirty space */
+		/* If there's a pending write to it, flush now */
+		if (c->wbuf_len) {
+			spin_unlock_bh(&c->erase_completion_lock);
+			D1(printk(KERN_DEBUG "jffs2_do_reserve_space: Flushing write buffer\n"));			    
+			jffs2_flush_wbuf(c, 1);
+			spin_lock_bh(&c->erase_completion_lock);
+			/* We know nobody's going to have changed nextblock. Just continue */
+		}
 		c->dirty_size += jeb->free_size;
 		c->free_size -= jeb->free_size;
 		jeb->dirty_size += jeb->free_size;
@@ -165,20 +172,44 @@
 
 			DECLARE_WAITQUEUE(wait, current);
 			
+			if (!c->nr_erasing_blocks && 
+			    !list_empty(&c->erasable_list)) {
+				struct jffs2_eraseblock *ejeb;
+
+				ejeb = list_entry(c->erasable_list.next, struct jffs2_eraseblock, list);
+				list_del(&ejeb->list);
+				list_add_tail(&ejeb->list, &c->erase_pending_list);
+				c->nr_erasing_blocks++;
+				D1(printk(KERN_DEBUG "jffs2_do_reserve_space: Triggering erase of erasable block at 0x%08x\n",
+					  ejeb->offset));
+			}
+
+			if (!c->nr_erasing_blocks && 
+			    !list_empty(&c->erasable_pending_wbuf_list)) {
+				D1(printk(KERN_DEBUG "jffs2_do_reserve_space: Flushing write buffer\n"));
+				/* c->nextblock is NULL, no update to c->nextblock allowed */			    
+				spin_unlock_bh(&c->erase_completion_lock);
+				jffs2_flush_wbuf(c, 1);
+				spin_lock_bh(&c->erase_completion_lock);
+				/* Have another go. It'll be on the erasable_list now */
+				return -EAGAIN;
+			}
+
 			if (!c->nr_erasing_blocks) {
-//			if (list_empty(&c->erasing_list) && list_empty(&c->erase_pending_list) && list_empty(c->erase_complete_list)) {
 				/* Ouch. We're in GC, or we wouldn't have got here.
 				   And there's no space left. At all. */
-				printk(KERN_CRIT "Argh. No free space left for GC. nr_erasing_blocks is %d. nr_free_blocks is %d. (erasingempty: %s, erasependingempty: %s)\n", 
-				       c->nr_erasing_blocks, c->nr_free_blocks, list_empty(&c->erasing_list)?"yes":"no", list_empty(&c->erase_pending_list)?"yes":"no");
+				printk(KERN_CRIT "Argh. No free space left for GC. nr_erasing_blocks is %d. nr_free_blocks is %d. (erasableempty: %s, erasingempty: %s, erasependingempty: %s)\n", 
+				       c->nr_erasing_blocks, c->nr_free_blocks, list_empty(&c->erasable_list)?"yes":"no", 
+				       list_empty(&c->erasing_list)?"yes":"no", list_empty(&c->erase_pending_list)?"yes":"no");
 				return -ENOSPC;
 			}
 			/* Make sure this can't deadlock. Someone has to start the erases
 			   of erase_pending blocks */
 			set_current_state(TASK_INTERRUPTIBLE);
 			add_wait_queue(&c->erase_wait, &wait);
-			D1(printk(KERN_DEBUG "Waiting for erases to complete. erasing_blocks is %d. (erasingempty: %s, erasependingempty: %s)\n", 
-				  c->nr_erasing_blocks, list_empty(&c->erasing_list)?"yes":"no", list_empty(&c->erase_pending_list)?"yes":"no"));
+			D1(printk(KERN_DEBUG "Waiting for erases to complete. erasing_blocks is %d. (erasableempty: %s, erasingempty: %s, erasependingempty: %s)\n", 
+				  c->nr_erasing_blocks, list_empty(&c->erasable_list)?"yes":"no",
+				  list_empty(&c->erasing_list)?"yes":"no", list_empty(&c->erase_pending_list)?"yes":"no"));
 			if (!list_empty(&c->erase_pending_list)) {
 				D1(printk(KERN_DEBUG "Triggering pending erases\n"));
 				jffs2_erase_pending_trigger(c);
@@ -200,7 +231,11 @@
 		list_del(next);
 		c->nextblock = jeb = list_entry(next, struct jffs2_eraseblock, list);
 		c->nr_free_blocks--;
-		if (jeb->free_size != c->sector_size - sizeof(struct jffs2_unknown_node)) {
+
+		/* On NAND free_size == sector_size, cleanmarker is in spare area !*/
+		if (jeb->free_size != c->sector_size - 
+			(jffs2_cleanmarker_oob(c)) ? 0 : sizeof(struct jffs2_unknown_node)) {
+
 			printk(KERN_WARNING "Eep. Block 0x%08x taken from free_list had free_size of 0x%08x!!\n", jeb->offset, jeb->free_size);
 			goto restart;
 		}
@@ -209,6 +244,20 @@
 	   enough space */
 	*ofs = jeb->offset + (c->sector_size - jeb->free_size);
 	*len = jeb->free_size;
+
+	if (jeb->used_size == PAD(sizeof(struct jffs2_unknown_node)) &&
+	    !jeb->first_node->next_in_ino) {
+		/* Only node in it beforehand was a CLEANMARKER node (we think). 
+		   So mark it obsolete now that there's going to be another node
+		   in the block. This will reduce used_size to zero but We've 
+		   already set c->nextblock so that jffs2_mark_node_obsolete()
+		   won't try to refile it to the dirty_list.
+		*/
+		spin_unlock_bh(&c->erase_completion_lock);
+		jffs2_mark_node_obsolete(c, jeb->first_node);
+		spin_lock_bh(&c->erase_completion_lock);
+	}
+
 	D1(printk(KERN_DEBUG "jffs2_do_reserve_space(): Giving 0x%x bytes at 0x%x\n", *len, *ofs));
 	return 0;
 }
@@ -216,9 +265,9 @@
 /**
  *	jffs2_add_physical_node_ref - add a physical node reference to the list
  *	@c: superblock info
- *	@ofs: physical location of this physical node
+ *	@new: new node reference to add
  *	@len: length of this physical node
- *	@ino: inode number with which this physical node is associated
+ *	@dirty: dirty flag for new node
  *
  *	Should only be used to report nodes for which space has been allocated 
  *	by jffs2_reserve_space.
@@ -226,12 +275,12 @@
  *	Must be called with the alloc_sem held.
  */
  
-int jffs2_add_physical_node_ref(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *new, __u32 len, int dirty)
+int jffs2_add_physical_node_ref(struct jffs2_sb_info *c, struct jffs2_raw_node_ref *new, uint32_t len, int dirty)
 {
 	struct jffs2_eraseblock *jeb;
 
 	len = PAD(len);
-	jeb = &c->blocks[(new->flash_offset & ~3) / c->sector_size];
+	jeb = &c->blocks[new->flash_offset / c->sector_size];
 	D1(printk(KERN_DEBUG "jffs2_add_physical_node_ref(): Node at 0x%x, size 0x%x\n", new->flash_offset & ~3, len));
 #if 1
 	if (jeb != c->nextblock || (new->flash_offset & ~3) != jeb->offset + (c->sector_size - jeb->free_size)) {
@@ -240,13 +289,14 @@
 		return -EINVAL;
 	}
 #endif
+	spin_lock_bh(&c->erase_completion_lock);
+
 	if (!jeb->first_node)
 		jeb->first_node = new;
 	if (jeb->last_node)
 		jeb->last_node->next_phys = new;
 	jeb->last_node = new;
 
-	spin_lock_bh(&c->erase_completion_lock);
 	jeb->free_size -= len;
 	c->free_size -= len;
 	if (dirty) {
@@ -257,17 +307,26 @@
 		jeb->used_size += len;
 		c->used_size += len;
 	}
-	spin_unlock_bh(&c->erase_completion_lock);
+
 	if (!jeb->free_size && !jeb->dirty_size) {
 		/* If it lives on the dirty_list, jffs2_reserve_space will put it there */
 		D1(printk(KERN_DEBUG "Adding full erase block at 0x%08x to clean_list (free 0x%08x, dirty 0x%08x, used 0x%08x\n",
 			  jeb->offset, jeb->free_size, jeb->dirty_size, jeb->used_size));
+		if (c->wbuf_len) {
+			/* Flush the last write in the block if it's outstanding */
+			spin_unlock_bh(&c->erase_completion_lock);
+			jffs2_flush_wbuf(c, 1);
+			spin_lock_bh(&c->erase_completion_lock);
+		}
+
 		list_add_tail(&jeb->list, &c->clean_list);
 		c->nextblock = NULL;
 	}
 	ACCT_SANITY_CHECK(c,jeb);
 	ACCT_PARANOIA_CHECK(jeb);
 
+	spin_unlock_bh(&c->erase_completion_lock);
+
 	return 0;
 }
 
@@ -285,7 +344,7 @@
 	int blocknr;
 	struct jffs2_unknown_node n;
 	int ret;
-	ssize_t retlen;
+	size_t retlen;
 
 	if(!ref) {
 		printk(KERN_NOTICE "EEEEEK. jffs2_mark_node_obsolete called with NULL node\n");
@@ -327,41 +386,62 @@
 		spin_unlock_bh(&c->erase_completion_lock);
 		return;
 	}
+
 	if (jeb == c->nextblock) {
 		D2(printk(KERN_DEBUG "Not moving nextblock 0x%08x to dirty/erase_pending list\n", jeb->offset));
-	} else if (jeb == c->gcblock) {
-		D2(printk(KERN_DEBUG "Not moving gcblock 0x%08x to dirty/erase_pending list\n", jeb->offset));
-#if 0 /* We no longer do this here. It can screw the wear levelling. If you have a lot of static
-	 data and a few blocks free, and you just create new files and keep deleting/overwriting
-	 them, then you'd keep erasing and reusing those blocks without ever moving stuff around.
-	 So we leave completely obsoleted blocks on the dirty_list and let the GC delete them 
-	 when it finds them there. That way, we still get the 'once in a while, take a clean block'
-	 to spread out the flash usage */
 	} else if (!jeb->used_size) {
-		D1(printk(KERN_DEBUG "Eraseblock at 0x%08x completely dirtied. Removing from (dirty?) list...\n", jeb->offset));
-		list_del(&jeb->list);
-		D1(printk(KERN_DEBUG "...and adding to erase_pending_list\n"));
-		list_add_tail(&jeb->list, &c->erase_pending_list);
-		c->nr_erasing_blocks++;
-		jffs2_erase_pending_trigger(c);
-		//		OFNI_BS_2SFFJ(c)->s_dirt = 1;
+		if (jeb == c->gcblock) {
+			D1(printk(KERN_DEBUG "gcblock at 0x%08x completely dirtied. Clearing gcblock...\n", jeb->offset));
+			c->gcblock = NULL;
+		} else {
+			D1(printk(KERN_DEBUG "Eraseblock at 0x%08x completely dirtied. Removing from (dirty?) list...\n", jeb->offset));
+			list_del(&jeb->list);
+		}
+		if (c->wbuf_len) {
+			D1(printk(KERN_DEBUG "...and adding to erasable_pending_wbuf_list\n"));
+			list_add_tail(&jeb->list, &c->erasable_pending_wbuf_list);
+
+			/* We've changed the rules slightly. After
+			   writing a node you now mustn't drop the
+			   alloc_sem before you've finished all the
+			   list management - this is so that when we
+			   get here, we know that no other nodes have
+			   been written, and the above check on wbuf
+			   is valid - wbuf_len is nonzero IFF the node
+			   which obsoletes this node is still in the
+			   wbuf.
+
+			   So we BUG() if that new rule is broken, to
+			   make sure we catch it and fix it.
+			*/
+			if (!down_trylock(&c->alloc_sem)) {
+				up(&c->alloc_sem);
+				printk(KERN_CRIT "jffs2_mark_node_obsolete() called with wbuf active but alloc_sem not locked!\n");
+				BUG();
+			}
+		} else {
+			D1(printk(KERN_DEBUG "...and adding to erasable_list\n"));
+			list_add_tail(&jeb->list, &c->erasable_list);
+		}
 		D1(printk(KERN_DEBUG "Done OK\n"));
-#endif
+	} else if (jeb == c->gcblock) {
+		D2(printk(KERN_DEBUG "Not moving gcblock 0x%08x to dirty_list\n", jeb->offset));
 	} else if (jeb->dirty_size == ref->totlen) {
 		D1(printk(KERN_DEBUG "Eraseblock at 0x%08x is freshly dirtied. Removing from clean list...\n", jeb->offset));
 		list_del(&jeb->list);
 		D1(printk(KERN_DEBUG "...and adding to dirty_list\n"));
 		list_add_tail(&jeb->list, &c->dirty_list);
 	}
+
 	spin_unlock_bh(&c->erase_completion_lock);
 
-	if (c->mtd->type != MTD_NORFLASH && c->mtd->type != MTD_RAM)
+	if (!jffs2_can_mark_obsolete(c))
 		return;
-	if (OFNI_BS_2SFFJ(c)->s_flags & MS_RDONLY)
+	if (jffs2_is_readonly(c))
 		return;
 
 	D1(printk(KERN_DEBUG "obliterating obsoleted node at 0x%08x\n", ref->flash_offset &~3));
-	ret = c->mtd->read(c->mtd, ref->flash_offset &~3, sizeof(n), &retlen, (char *)&n);
+	ret = jffs2_flash_read(c, ref->flash_offset &~3, sizeof(n), &retlen, (char *)&n);
 	if (ret) {
 		printk(KERN_WARNING "Read error reading from obsoleted node at 0x%08x: %d\n", ref->flash_offset &~3, ret);
 		return;
@@ -379,7 +459,7 @@
 		return;
 	}
 	n.nodetype &= ~JFFS2_NODE_ACCURATE;
-	ret = c->mtd->write(c->mtd, ref->flash_offset&~3, sizeof(n), &retlen, (char *)&n);
+	ret = jffs2_flash_write(c, ref->flash_offset&~3, sizeof(n), &retlen, (char *)&n);
 	if (ret) {
 		printk(KERN_WARNING "Write error in obliterating obsoleted node at 0x%08x: %d\n", ref->flash_offset &~3, ret);
 		return;
diff -Nru a/fs/jffs2/os-linux.h b/fs/jffs2/os-linux.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/jffs2/os-linux.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,170 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2002 Red Hat, Inc.
+ *
+ * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * The original JFFS, from which the design for JFFS2 was derived,
+ * was designed and implemented by Axis Communications AB.
+ *
+ * The contents of this file are subject to the Red Hat eCos Public
+ * License Version 1.1 (the "Licence"); you may not use this file
+ * except in compliance with the Licence.  You may obtain a copy of
+ * the Licence at http://www.redhat.com/
+ *
+ * Software distributed under the Licence is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
+ * See the Licence for the specific language governing rights and
+ * limitations under the Licence.
+ *
+ * The Original Code is JFFS2 - Journalling Flash File System, version 2
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use your
+ * version of this file under the RHEPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the RHEPL or the GPL.
+ *
+ * $Id: os-linux.h,v 1.15 2002/03/08 11:31:48 dwmw2 Exp $
+ *
+ */
+
+#ifndef __JFFS2_OS_LINUX_H__
+#define __JFFS2_OS_LINUX_H__
+#include <linux/version.h>
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,2)
+#define JFFS2_INODE_INFO(i) (list_entry(i, struct jffs2_inode_info, vfs_inode))
+#define OFNI_EDONI_2SFFJ(f)  (&(f)->vfs_inode)
+#define JFFS2_SB_INFO(sb) (&sb->u.jffs2_sb)
+#define OFNI_BS_2SFFJ(c)  ((struct super_block *) ( ((char *)c) - ((char *)(&((struct super_block *)NULL)->u)) ) )
+#elif defined(JFFS2_OUT_OF_KERNEL)
+#define JFFS2_INODE_INFO(i) ((struct jffs2_inode_info *) &(i)->u)
+#define OFNI_EDONI_2SFFJ(f)  ((struct inode *) ( ((char *)f) - ((char *)(&((struct inode *)NULL)->u)) ) )
+#define JFFS2_SB_INFO(sb) ((struct jffs2_sb_info *) &(sb)->u)
+#define OFNI_BS_2SFFJ(c)  ((struct super_block *) ( ((char *)c) - ((char *)(&((struct super_block *)NULL)->u)) ) )
+#else
+#define JFFS2_INODE_INFO(i) (&i->u.jffs2_i)
+#define OFNI_EDONI_2SFFJ(f)  ((struct inode *) ( ((char *)f) - ((char *)(&((struct inode *)NULL)->u)) ) )
+#define JFFS2_SB_INFO(sb) (&sb->u.jffs2_sb)
+#define OFNI_BS_2SFFJ(c)  ((struct super_block *) ( ((char *)c) - ((char *)(&((struct super_block *)NULL)->u)) ) )
+#endif
+
+
+#define JFFS2_F_I_SIZE(f) (OFNI_EDONI_2SFFJ(f)->i_size)
+#define JFFS2_F_I_MODE(f) (OFNI_EDONI_2SFFJ(f)->i_mode)
+#define JFFS2_F_I_UID(f) (OFNI_EDONI_2SFFJ(f)->i_uid)
+#define JFFS2_F_I_GID(f) (OFNI_EDONI_2SFFJ(f)->i_gid)
+#define JFFS2_F_I_CTIME(f) (OFNI_EDONI_2SFFJ(f)->i_ctime)
+#define JFFS2_F_I_MTIME(f) (OFNI_EDONI_2SFFJ(f)->i_mtime)
+#define JFFS2_F_I_ATIME(f) (OFNI_EDONI_2SFFJ(f)->i_atime)
+
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,1)
+#define JFFS2_F_I_RDEV_MIN(f) (minor(OFNI_EDONI_2SFFJ(f)->i_rdev))
+#define JFFS2_F_I_RDEV_MAJ(f) (major(OFNI_EDONI_2SFFJ(f)->i_rdev))
+#else
+#define JFFS2_F_I_RDEV_MIN(f) (MINOR(to_kdev_t(OFNI_EDONI_2SFFJ(f)->i_rdev)))
+#define JFFS2_F_I_RDEV_MAJ(f) (MAJOR(to_kdev_t(OFNI_EDONI_2SFFJ(f)->i_rdev)))
+#endif
+
+static inline void jffs2_init_inode_info(struct jffs2_inode_info *f)
+{
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,2)
+	f->highest_version = 0;
+	f->fraglist = NULL;
+	f->metadata = NULL;
+	f->dents = NULL;
+	f->flags = 0;
+	f->usercompr = 0;
+#else
+	memset(f, 0, sizeof(*f));
+	init_MUTEX_LOCKED(&f->sem);
+#endif
+}
+
+#define jffs2_is_readonly(c) (OFNI_BS_2SFFJ(c)->s_flags & MS_RDONLY)
+
+#ifndef CONFIG_JFFS2_FS_NAND
+#define jffs2_can_mark_obsolete(c) (1)
+#define jffs2_cleanmarker_oob(c) (0)
+#define jffs2_write_nand_cleanmarker(c,jeb) (-EIO)
+
+#define jffs2_flash_write(c, ofs, len, retlen, buf) ((c)->mtd->write((c)->mtd, ofs, len, retlen, buf))
+#define jffs2_flash_read(c, ofs, len, retlen, buf) ((c)->mtd->read((c)->mtd, ofs, len, retlen, buf))
+#define jffs2_flush_wbuf(c, flag) do { ; } while(0)
+#define jffs2_nand_read_failcnt(c,jeb) do { ; } while(0)
+#define jffs2_write_nand_badblock(c,jeb) do { ; } while(0)
+#define jffs2_flash_writev jffs2_flash_direct_writev
+
+#else /* NAND support present */
+
+#define jffs2_can_mark_obsolete(c) (c->mtd->type == MTD_NORFLASH || c->mtd->type == MTD_RAM)
+#define jffs2_cleanmarker_oob(c) (c->mtd->type == MTD_NANDFLASH)
+
+#define jffs2_flash_write_oob(c, ofs, len, retlen, buf) ((c)->mtd->write_oob((c)->mtd, ofs, len, retlen, buf))
+#define jffs2_flash_read_oob(c, ofs, len, retlen, buf) ((c)->mtd->read_oob((c)->mtd, ofs, len, retlen, buf))
+
+
+/* wbuf.c */
+int jffs2_flash_writev(struct jffs2_sb_info *c, const struct iovec *vecs, unsigned long count, loff_t to, size_t *retlen);
+int jffs2_flash_write(struct jffs2_sb_info *c, loff_t ofs, size_t len, size_t *retlen, const u_char *buf);
+int jffs2_flash_read(struct jffs2_sb_info *c, loff_t ofs, size_t len, size_t *retlen, u_char *buf);
+int jffs2_check_oob_empty(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb,int mode);
+int jffs2_check_nand_cleanmarker(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
+int jffs2_write_nand_cleanmarker(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
+int jffs2_write_nand_badblock(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb);
+#endif /* NAND */
+
+/* background.c */
+int jffs2_start_garbage_collect_thread(struct jffs2_sb_info *c);
+void jffs2_stop_garbage_collect_thread(struct jffs2_sb_info *c);
+void jffs2_garbage_collect_trigger(struct jffs2_sb_info *c);
+
+/* dir.c */
+extern struct file_operations jffs2_dir_operations;
+extern struct inode_operations jffs2_dir_inode_operations;
+
+/* file.c */
+extern struct file_operations jffs2_file_operations;
+extern struct inode_operations jffs2_file_inode_operations;
+extern struct address_space_operations jffs2_file_address_operations;
+int jffs2_fsync(struct file *, struct dentry *, int);
+int jffs2_setattr (struct dentry *dentry, struct iattr *iattr);
+int jffs2_do_readpage_nolock (struct inode *inode, struct page *pg);
+int jffs2_do_readpage_unlock (struct inode *inode, struct page *pg);
+int jffs2_readpage (struct file *, struct page *);
+int jffs2_prepare_write (struct file *, struct page *, unsigned, unsigned);
+int jffs2_commit_write (struct file *, struct page *, unsigned, unsigned);
+
+/* ioctl.c */
+int jffs2_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
+
+/* symlink.c */
+extern struct inode_operations jffs2_symlink_inode_operations;
+
+/* fs.c */
+void jffs2_read_inode (struct inode *);
+void jffs2_clear_inode (struct inode *);
+struct inode *jffs2_new_inode (struct inode *dir_i, int mode,
+			       struct jffs2_raw_inode *ri);
+int jffs2_statfs (struct super_block *, struct statfs *);
+void jffs2_write_super (struct super_block *);
+int jffs2_remount_fs (struct super_block *, int *, char *);
+int jffs2_do_fill_super(struct super_block *sb, void *data, int silent);
+
+/* writev.c */
+int jffs2_flash_direct_writev(struct jffs2_sb_info *c, const struct iovec *vecs, 
+		       unsigned long count, loff_t to, size_t *retlen);
+
+/* super.c */
+
+
+#endif /* __JFFS2_OS_LINUX_H__ */
+
+
diff -Nru a/fs/jffs2/pushpull.c b/fs/jffs2/pushpull.c
--- a/fs/jffs2/pushpull.c	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,71 +0,0 @@
-/*
- * JFFS2 -- Journalling Flash File System, Version 2.
- *
- * Copyright (C) 2001 Red Hat, Inc.
- *
- * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
- *
- * The original JFFS, from which the design for JFFS2 was derived,
- * was designed and implemented by Axis Communications AB.
- *
- * The contents of this file are subject to the Red Hat eCos Public
- * License Version 1.1 (the "Licence"); you may not use this file
- * except in compliance with the Licence.  You may obtain a copy of
- * the Licence at http://www.redhat.com/
- *
- * Software distributed under the Licence is distributed on an "AS IS"
- * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
- * See the Licence for the specific language governing rights and
- * limitations under the Licence.
- *
- * The Original Code is JFFS2 - Journalling Flash File System, version 2
- *
- * Alternatively, the contents of this file may be used under the
- * terms of the GNU General Public License version 2 (the "GPL"), in
- * which case the provisions of the GPL are applicable instead of the
- * above.  If you wish to allow the use of your version of this file
- * only under the terms of the GPL and not to allow others to use your
- * version of this file under the RHEPL, indicate your decision by
- * deleting the provisions above and replace them with the notice and
- * other provisions required by the GPL.  If you do not delete the
- * provisions above, a recipient may use your version of this file
- * under either the RHEPL or the GPL.
- *
- * $Id: pushpull.c,v 1.7 2001/09/23 10:04:15 rmk Exp $
- *
- */
-
-#include <linux/string.h>
-#include "pushpull.h"
-#include <linux/errno.h>
-
-void init_pushpull(struct pushpull *pp, char *buf, unsigned buflen, unsigned ofs, unsigned reserve)
-{
-	pp->buf = buf;
-	pp->buflen = buflen;
-	pp->ofs = ofs;
-	pp->reserve = reserve;
-}
-     
-
-int pushbit(struct pushpull *pp, int bit, int use_reserved)
-{
-	if (pp->ofs >= pp->buflen - (use_reserved?0:pp->reserve)) {
-		return -ENOSPC;
-	}
-
-	if (bit) {
-		pp->buf[pp->ofs >> 3] |= (1<<(7-(pp->ofs &7)));
-	}
-	else {
-		pp->buf[pp->ofs >> 3] &= ~(1<<(7-(pp->ofs &7)));
-	}
-	pp->ofs++;
-
-	return 0;
-}
-
-int pushedbits(struct pushpull *pp)
-{
-	return pp->ofs;
-}
diff -Nru a/fs/jffs2/pushpull.h b/fs/jffs2/pushpull.h
--- a/fs/jffs2/pushpull.h	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/pushpull.h	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,12 +31,15 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: pushpull.h,v 1.5 2001/09/23 10:04:15 rmk Exp $
+ * $Id: pushpull.h,v 1.7 2002/03/06 12:37:08 dwmw2 Exp $
  *
  */
 
 #ifndef __PUSHPULL_H__
 #define __PUSHPULL_H__
+
+#include <linux/errno.h>
+
 struct pushpull {
 	unsigned char *buf;
 	unsigned int buflen;
@@ -44,9 +47,36 @@
 	unsigned int reserve;
 };
 
-void init_pushpull(struct pushpull *, char *, unsigned, unsigned, unsigned);
-int pushbit(struct pushpull *pp, int bit, int use_reserved);
-int pushedbits(struct pushpull *pp);
+
+static inline void init_pushpull(struct pushpull *pp, char *buf, unsigned buflen, unsigned ofs, unsigned reserve)
+{
+	pp->buf = buf;
+	pp->buflen = buflen;
+	pp->ofs = ofs;
+	pp->reserve = reserve;
+}
+
+static inline int pushbit(struct pushpull *pp, int bit, int use_reserved)
+{
+	if (pp->ofs >= pp->buflen - (use_reserved?0:pp->reserve)) {
+		return -ENOSPC;
+	}
+
+	if (bit) {
+		pp->buf[pp->ofs >> 3] |= (1<<(7-(pp->ofs &7)));
+	}
+	else {
+		pp->buf[pp->ofs >> 3] &= ~(1<<(7-(pp->ofs &7)));
+	}
+	pp->ofs++;
+
+	return 0;
+}
+
+static inline int pushedbits(struct pushpull *pp)
+{
+	return pp->ofs;
+}
 
 static inline int pullbit(struct pushpull *pp)
 {
diff -Nru a/fs/jffs2/read.c b/fs/jffs2/read.c
--- a/fs/jffs2/read.c	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/read.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,14 +31,14 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: read.c,v 1.13.2.1 2002/02/01 23:32:33 dwmw2 Exp $
+ * $Id: read.c,v 1.22 2002/03/02 22:08:27 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/crc32.h>
-#include <linux/jffs2.h>
+#include <linux/pagemap.h>
 #include <linux/mtd/mtd.h>
 #include "nodelist.h"
 
@@ -46,7 +46,7 @@
 {
 	struct jffs2_raw_inode *ri;
 	size_t readlen;
-	__u32 crc;
+	uint32_t crc;
 	unsigned char *decomprbuf = NULL;
 	unsigned char *readbuf = NULL;
 	int ret = 0;
@@ -55,7 +55,7 @@
 	if (!ri)
 		return -ENOMEM;
 
-	ret = c->mtd->read(c->mtd, fd->raw->flash_offset & ~3, sizeof(*ri), &readlen, (char *)ri);
+	ret = jffs2_flash_read(c, fd->raw->flash_offset & ~3, sizeof(*ri), &readlen, (char *)ri);
 	if (ret) {
 		jffs2_free_raw_inode(ri);
 		printk(KERN_WARNING "Error reading node from 0x%08x: %d\n", fd->raw->flash_offset & ~3, ret);
@@ -124,7 +124,7 @@
 	}
 
 	D2(printk(KERN_DEBUG "Read %d bytes to %p\n", ri->csize, readbuf));
-	ret = c->mtd->read(c->mtd, (fd->raw->flash_offset &~3) + sizeof(*ri), ri->csize, &readlen, readbuf);
+	ret = jffs2_flash_read(c, (fd->raw->flash_offset &~3) + sizeof(*ri), ri->csize, &readlen, readbuf);
 
 	if (!ret && readlen != ri->csize)
 		ret = -EIO;
@@ -160,4 +160,100 @@
 	jffs2_free_raw_inode(ri);
 
 	return ret;
+}
+
+int jffs2_read_inode_range(struct jffs2_sb_info *c, struct jffs2_inode_info *f,
+			   unsigned char *buf, uint32_t offset, uint32_t len)
+{
+	uint32_t end = offset + len;
+	struct jffs2_node_frag *frag = f->fraglist;
+	int ret;
+
+	D1(printk(KERN_DEBUG "jffs2_read_inode_range: ino #%u, range 0x%08x-0x%08x\n",
+		  f->inocache->ino, offset, offset+len));
+
+	while(frag && frag->ofs + frag->size  <= offset) {
+		D2(printk(KERN_DEBUG "skipping frag %d-%d; before the region we care about\n", frag->ofs, frag->ofs + frag->size));
+		frag = frag->next;
+	}
+	/* XXX FIXME: Where a single physical node actually shows up in two
+	   frags, we read it twice. Don't do that. */
+	/* Now we're pointing at the first frag which overlaps our page */
+	while(offset < end) {
+		D2(printk(KERN_DEBUG "jffs2_read_inode_range: offset %d, end %d\n", offset, end));
+		if (!frag || frag->ofs > offset) {
+			uint32_t holesize = end - offset;
+			if (frag) {
+				D1(printk(KERN_NOTICE "Eep. Hole in ino #%u fraglist. frag->ofs = 0x%08x, offset = 0x%08x\n", f->inocache->ino, frag->ofs, offset));
+				holesize = min(holesize, frag->ofs - offset);
+				D1(jffs2_print_frag_list(f));
+			}
+			D1(printk(KERN_DEBUG "Filling non-frag hole from %d-%d\n", offset, offset+holesize));
+			memset(buf, 0, holesize);
+			buf += holesize;
+			offset += holesize;
+			continue;
+		} else if (frag->ofs < offset && (offset & (PAGE_CACHE_SIZE-1)) != 0) {
+			D1(printk(KERN_NOTICE "Eep. Overlap in ino #%u fraglist. frag->ofs = 0x%08x, offset = 0x%08x\n",
+				  f->inocache->ino, frag->ofs, offset));
+			D1(jffs2_print_frag_list(f));
+			memset(buf, 0, end - offset);
+			return -EIO;
+		} else if (!frag->node) {
+			uint32_t holeend = min(end, frag->ofs + frag->size);
+			D1(printk(KERN_DEBUG "Filling frag hole from %d-%d (frag 0x%x 0x%x)\n", offset, holeend, frag->ofs, frag->ofs + frag->size));
+			memset(buf, 0, holeend - offset);
+			buf += holeend - offset;
+			offset = holeend;
+			frag = frag->next;
+			continue;
+		} else {
+			uint32_t readlen;
+			readlen = min(frag->size, end - offset);
+			D1(printk(KERN_DEBUG "Reading %d-%d from node at 0x%x\n", frag->ofs, frag->ofs+readlen, frag->node->raw->flash_offset & ~3));
+			ret = jffs2_read_dnode(c, frag->node, buf, frag->ofs - frag->node->ofs, readlen);
+			D2(printk(KERN_DEBUG "node read done\n"));
+			if (ret) {
+				D1(printk(KERN_DEBUG"jffs2_read_inode_range error %d\n",ret));
+				memset(buf, 0, frag->size);
+				return ret;
+			}
+		}
+		buf += frag->size;
+		offset += frag->size;
+		frag = frag->next;
+		D2(printk(KERN_DEBUG "node read was OK. Looping\n"));
+	}
+	return 0;
+}
+
+/* Core function to read symlink target. */
+char *jffs2_getlink(struct jffs2_sb_info *c, struct jffs2_inode_info *f)
+{
+	char *buf;
+	int ret;
+
+	down(&f->sem);
+
+	if (!f->metadata) {
+		printk(KERN_NOTICE "No metadata for symlink inode #%u\n", f->inocache->ino);
+		up(&f->sem);
+		return ERR_PTR(-EINVAL);
+	}
+	buf = kmalloc(f->metadata->size+1, GFP_USER);
+	if (!buf) {
+		up(&f->sem);
+		return ERR_PTR(-ENOMEM);
+	}
+	buf[f->metadata->size]=0;
+
+	ret = jffs2_read_dnode(c, f->metadata, buf, 0, f->metadata->size);
+
+	up(&f->sem);
+
+	if (ret) {
+		kfree(buf);
+		return ERR_PTR(ret);
+	}
+	return buf;
 }
diff -Nru a/fs/jffs2/readinode.c b/fs/jffs2/readinode.c
--- a/fs/jffs2/readinode.c	Fri Mar 15 17:51:01 2002
+++ b/fs/jffs2/readinode.c	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,19 +31,16 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: readinode.c,v 1.58.2.2 2002/02/23 14:25:37 dwmw2 Exp $
+ * $Id: readinode.c,v 1.71 2002/03/06 12:25:59 dwmw2 Exp $
  *
  */
 
-/* Given an inode, probably with existing list of fragments, add the new node
- * to the fragment list.
- */
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/fs.h>
 #include <linux/crc32.h>
 #include <linux/mtd/mtd.h>
-#include <linux/jffs2.h>
+#include <linux/interrupt.h>
 #include "nodelist.h"
 
 
@@ -64,6 +61,9 @@
 })
 
 
+/* Given an inode, probably with existing list of fragments, add the new node
+ * to the fragment list.
+ */
 int jffs2_add_full_dnode_to_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, struct jffs2_full_dnode *fn)
 {
 	int ret;
@@ -101,7 +101,7 @@
 	
 	struct jffs2_node_frag *this, **prev, *old;
 	struct jffs2_node_frag *newfrag, *newfrag2;
-	__u32 lastend = 0;
+	uint32_t lastend = 0;
 
 
 	newfrag = jffs2_alloc_node_frag();
@@ -222,7 +222,7 @@
 	return 0;
 }
 
-void jffs2_truncate_fraglist (struct jffs2_sb_info *c, struct jffs2_node_frag **list, __u32 size)
+void jffs2_truncate_fraglist (struct jffs2_sb_info *c, struct jffs2_node_frag **list, uint32_t size)
 {
 	D1(printk(KERN_DEBUG "Truncating fraglist to 0x%08x bytes\n", size));
 
@@ -243,68 +243,53 @@
 
 /* Scan the list of all nodes present for this ino, build map of versions, etc. */
 
-void jffs2_read_inode (struct inode *inode)
+int jffs2_do_read_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, 
+			uint32_t ino, struct jffs2_raw_inode *latest_node)
 {
 	struct jffs2_tmp_dnode_info *tn_list, *tn;
 	struct jffs2_full_dirent *fd_list;
-	struct jffs2_inode_info *f;
 	struct jffs2_full_dnode *fn = NULL;
-	struct jffs2_sb_info *c;
-	struct jffs2_raw_inode latest_node;
-	__u32 latest_mctime, mctime_ver;
+	uint32_t crc;
+	uint32_t latest_mctime, mctime_ver;
+	uint32_t mdata_ver = 0;
+	size_t retlen;
 	int ret;
-	ssize_t retlen;
 
-	D1(printk(KERN_DEBUG "jffs2_read_inode(): inode->i_ino == %lu\n", inode->i_ino));
+	D2(printk(KERN_DEBUG "jffs2_do_read_inode(): getting inocache\n"));
 
-	f = JFFS2_INODE_INFO(inode);
-	c = JFFS2_SB_INFO(inode->i_sb);
+	f->inocache = jffs2_get_ino_cache(c, ino);
 
-	f->highest_version = 0;
-	f->fraglist = NULL;
-	f->metadata = NULL;
-	f->dents = NULL;
-	f->flags = 0;
-	f->usercompr = 0;
-	D2(printk(KERN_DEBUG "getting inocache\n"));
-	f->inocache = jffs2_get_ino_cache(c, inode->i_ino);
-	D2(printk(KERN_DEBUG "jffs2_read_inode(): Got inocache at %p\n", f->inocache));
+	D2(printk(KERN_DEBUG "jffs2_do_read_inode(): Got inocache at %p\n", f->inocache));
 
-	if (!f->inocache && inode->i_ino == 1) {
+	if (!f->inocache && ino == 1) {
 		/* Special case - no root inode on medium */
 		f->inocache = jffs2_alloc_inode_cache();
 		if (!f->inocache) {
-			printk(KERN_CRIT "jffs2_read_inode(): Cannot allocate inocache for root inode\n");
-			make_bad_inode(inode);
-			return;
+			printk(KERN_CRIT "jffs2_do_read_inode(): Cannot allocate inocache for root inode\n");
+			return -ENOMEM;
 		}
-		D1(printk(KERN_DEBUG "jffs2_read_inode(): Creating inocache for root inode\n"));
+		D1(printk(KERN_DEBUG "jffs2_do_read_inode(): Creating inocache for root inode\n"));
 		memset(f->inocache, 0, sizeof(struct jffs2_inode_cache));
 		f->inocache->ino = f->inocache->nlink = 1;
 		f->inocache->nodes = (struct jffs2_raw_node_ref *)f->inocache;
 		jffs2_add_ino_cache(c, f->inocache);
 	}
 	if (!f->inocache) {
-		printk(KERN_WARNING "jffs2_read_inode() on nonexistent ino %lu\n", (unsigned long)inode->i_ino);
-		make_bad_inode(inode);
-		return;
+		printk(KERN_WARNING "jffs2_do_read_inode() on nonexistent ino %u\n", ino);
+		return -ENOENT;
 	}
-	D1(printk(KERN_DEBUG "jffs2_read_inode(): ino #%lu nlink is %d\n", (unsigned long)inode->i_ino, f->inocache->nlink));
-	inode->i_nlink = f->inocache->nlink;
+	D1(printk(KERN_DEBUG "jffs2_do_read_inode(): ino #%u nlink is %d\n", ino, f->inocache->nlink));
 
 	/* Grab all nodes relevant to this ino */
-	ret = jffs2_get_inode_nodes(c, inode->i_ino, f, &tn_list, &fd_list, &f->highest_version, &latest_mctime, &mctime_ver);
+	ret = jffs2_get_inode_nodes(c, ino, f, &tn_list, &fd_list, &f->highest_version, &latest_mctime, &mctime_ver);
 
 	if (ret) {
-		printk(KERN_CRIT "jffs2_get_inode_nodes() for ino %lu returned %d\n", inode->i_ino, ret);
-		make_bad_inode(inode);
-		return;
+		printk(KERN_CRIT "jffs2_get_inode_nodes() for ino %u returned %d\n", ino, ret);
+		return ret;
 	}
 	f->dents = fd_list;
 
 	while (tn_list) {
-		static __u32 mdata_ver;
-
 		tn = tn_list;
 
 		fn = tn->fn;
@@ -331,150 +316,106 @@
 	}
 	if (!fn) {
 		/* No data nodes for this inode. */
-		if (inode->i_ino != 1) {
-			printk(KERN_WARNING "jffs2_read_inode(): No data nodes found for ino #%lu\n", inode->i_ino);
+		if (ino != 1) {
+			printk(KERN_WARNING "jffs2_do_read_inode(): No data nodes found for ino #%u\n", ino);
 			if (!fd_list) {
-				make_bad_inode(inode);
-				return;
+				return -EIO;
 			}
-			printk(KERN_WARNING "jffs2_read_inode(): But it has children so we fake some modes for it\n");
+			printk(KERN_WARNING "jffs2_do_read_inode(): But it has children so we fake some modes for it\n");
 		}
-		inode->i_mode = S_IFDIR | S_IRUGO | S_IWUSR | S_IXUGO;
-		latest_node.version = 0;
-		inode->i_atime = inode->i_ctime = inode->i_mtime = CURRENT_TIME;
-		inode->i_nlink = f->inocache->nlink;
-		inode->i_size = 0;
-	} else {
-		__u32 crc;
+		latest_node->mode = S_IFDIR | S_IRUGO | S_IWUSR | S_IXUGO;
+		latest_node->version = 0;
+		latest_node->atime = latest_node->ctime = latest_node->mtime = 0;
+		latest_node->isize = 0;
+		latest_node->gid = 0;
+		latest_node->uid = 0;
+		return 0;
+	}
 
-		ret = c->mtd->read(c->mtd, fn->raw->flash_offset & ~3, sizeof(latest_node), &retlen, (void *)&latest_node);
-		if (ret || retlen != sizeof(latest_node)) {
-			printk(KERN_NOTICE "MTD read in jffs2_read_inode() failed: Returned %d, %ld of %d bytes read\n",
-			       ret, (long)retlen, sizeof(latest_node));
-			jffs2_clear_inode(inode);
-			make_bad_inode(inode);
-			return;
-		}
-
-		crc = crc32(0, &latest_node, sizeof(latest_node)-8);
-		if (crc != latest_node.node_crc) {
-			printk(KERN_NOTICE "CRC failed for read_inode of inode %ld at physical location 0x%x\n", inode->i_ino, fn->raw->flash_offset & ~3);
-			jffs2_clear_inode(inode);
-			make_bad_inode(inode);
-			return;
-		}
-
-		inode->i_mode = latest_node.mode;
-		inode->i_uid = latest_node.uid;
-		inode->i_gid = latest_node.gid;
-		inode->i_size = latest_node.isize;
-		if (S_ISREG(inode->i_mode))
-			jffs2_truncate_fraglist(c, &f->fraglist, latest_node.isize);
-		inode->i_atime = latest_node.atime;
-		inode->i_mtime = latest_node.mtime;
-		inode->i_ctime = latest_node.ctime;
-	}
-
-	/* OK, now the special cases. Certain inode types should
-	   have only one data node, and it's kept as the metadata
-	   node */
-	if (S_ISBLK(inode->i_mode) || S_ISCHR(inode->i_mode) ||
-	    S_ISLNK(inode->i_mode)) {
-		if (f->metadata) {
-			printk(KERN_WARNING "Argh. Special inode #%lu with mode 0%o had metadata node\n", inode->i_ino, inode->i_mode);
-			jffs2_clear_inode(inode);
-			make_bad_inode(inode);
-			return;
-		}
-		if (!f->fraglist) {
-			printk(KERN_WARNING "Argh. Special inode #%lu with mode 0%o has no fragments\n", inode->i_ino, inode->i_mode);
-			jffs2_clear_inode(inode);
-			make_bad_inode(inode);
-			return;
-		}
-		/* ASSERT: f->fraglist != NULL */
-		if (f->fraglist->next) {
-			printk(KERN_WARNING "Argh. Special inode #%lu with mode 0%o had more than one node\n", inode->i_ino, inode->i_mode);
-			/* FIXME: Deal with it - check crc32, check for duplicate node, check times and discard the older one */
-			jffs2_clear_inode(inode);
-			make_bad_inode(inode);
-			return;
-		}
-		/* OK. We're happy */
-		f->metadata = f->fraglist->node;
-		jffs2_free_node_frag(f->fraglist);
-		f->fraglist = NULL;
-	}			
-	    
-	inode->i_blksize = PAGE_SIZE;
-	inode->i_blocks = (inode->i_size + 511) >> 9;
-	
-	switch (inode->i_mode & S_IFMT) {
-		unsigned short rdev;
+	ret = jffs2_flash_read(c, fn->raw->flash_offset & ~3, sizeof(*latest_node), &retlen, (void *)latest_node);
+	if (ret || retlen != sizeof(*latest_node)) {
+		printk(KERN_NOTICE "MTD read in jffs2_do_read_inode() failed: Returned %d, %ld of %d bytes read\n",
+		       ret, (long)retlen, sizeof(*latest_node));
+		/* FIXME: If this fails, there seems to be a memory leak. Find it. */
+		jffs2_do_clear_inode(c, f);
+		return ret?ret:-EIO;
+	}
+
+	crc = crc32(0, latest_node, sizeof(*latest_node)-8);
+	if (crc != latest_node->node_crc) {
+		printk(KERN_NOTICE "CRC failed for read_inode of inode %u at physical location 0x%x\n", ino, fn->raw->flash_offset & ~3);
+		jffs2_do_clear_inode(c, f);
+		return -EIO;
+	}
 
-	case S_IFLNK:
-		inode->i_op = &jffs2_symlink_inode_operations;
-		/* Hack to work around broken isize in old symlink code.
-		   Remove this when dwmw2 comes to his senses and stops
-		   symlinks from being an entirely gratuitous special
-		   case. */
-		if (!inode->i_size)
-			inode->i_size = latest_node.dsize;
-		break;
-		
+	switch(latest_node->mode & S_IFMT) {
 	case S_IFDIR:
-		if (mctime_ver > latest_node.version) {
+		if (mctime_ver > latest_node->version) {
 			/* The times in the latest_node are actually older than
 			   mctime in the latest dirent. Cheat. */
-			inode->i_mtime = inode->i_ctime = inode->i_atime = 
-				latest_mctime;
+			latest_node->ctime = latest_node->mtime = latest_mctime;
 		}
-		inode->i_op = &jffs2_dir_inode_operations;
-		inode->i_fop = &jffs2_dir_operations;
 		break;
 
+			
 	case S_IFREG:
-		inode->i_op = &jffs2_file_inode_operations;
-		inode->i_fop = &jffs2_file_operations;
-		inode->i_mapping->a_ops = &jffs2_file_address_operations;
-		inode->i_mapping->nrpages = 0;
+		/* If it was a regular file, truncate it to the latest node's isize */
+		jffs2_truncate_fraglist(c, &f->fraglist, latest_node->isize);
 		break;
 
+	case S_IFLNK:
+		/* Hack to work around broken isize in old symlink code.
+		   Remove this when dwmw2 comes to his senses and stops
+		   symlinks from being an entirely gratuitous special
+		   case. */
+		if (!latest_node->isize)
+			latest_node->isize = latest_node->dsize;
+		/* fall through... */
+
 	case S_IFBLK:
 	case S_IFCHR:
-		/* Read the device numbers from the media */
-		D1(printk(KERN_DEBUG "Reading device numbers from flash\n"));
-		if (jffs2_read_dnode(c, f->metadata, (char *)&rdev, 0, sizeof(rdev)) < 0) {
-			/* Eep */
-			printk(KERN_NOTICE "Read device numbers for inode %lu failed\n", (unsigned long)inode->i_ino);
-			jffs2_clear_inode(inode);
-			make_bad_inode(inode);
-			return;
-		}			
-
-	case S_IFSOCK:
-	case S_IFIFO:
-		inode->i_op = &jffs2_file_inode_operations;
-		init_special_inode(inode, inode->i_mode, kdev_t_to_nr(mk_kdev(rdev>>8, rdev&0xff)));
+		/* Xertain inode types should have only one data node, and it's
+		   kept as the metadata node */
+		if (f->metadata) {
+			printk(KERN_WARNING "Argh. Special inode #%u with mode 0%o had metadata node\n", ino, latest_node->mode);
+			jffs2_do_clear_inode(c, f);
+			return -EIO;
+		}
+		if (!f->fraglist) {
+			printk(KERN_WARNING "Argh. Special inode #%u with mode 0%o has no fragments\n", ino, latest_node->mode);
+			jffs2_do_clear_inode(c, f);
+			return -EIO;
+		}
+		/* ASSERT: f->fraglist != NULL */
+		if (f->fraglist->next) {
+			printk(KERN_WARNING "Argh. Special inode #%u with mode 0%o had more than one node\n", ino, latest_node->mode);
+			/* FIXME: Deal with it - check crc32, check for duplicate node, check times and discard the older one */
+			jffs2_do_clear_inode(c, f);
+			return -EIO;
+		}
+		/* OK. We're happy */
+		f->metadata = f->fraglist->node;
+		jffs2_free_node_frag(f->fraglist);
+		f->fraglist = NULL;
 		break;
-
-	default:
-		printk(KERN_WARNING "jffs2_read_inode(): Bogus imode %o for ino %lu", inode->i_mode, (unsigned long)inode->i_ino);
 	}
-	D1(printk(KERN_DEBUG "jffs2_read_inode() returning\n"));
+
+	return 0;
 }
 
-void jffs2_clear_inode (struct inode *inode)
+
+void jffs2_do_clear_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f)
 {
-	/* We can forget about this inode for now - drop all 
-	 *  the nodelists associated with it, etc.
-	 */
-	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
 	struct jffs2_node_frag *frag, *frags;
 	struct jffs2_full_dirent *fd, *fds;
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 
-	D1(printk(KERN_DEBUG "jffs2_clear_inode(): ino #%lu mode %o\n", inode->i_ino, inode->i_mode));
+	/* If it's a deleted inode, grab the alloc_sem to keep the
+	   (maybe temporary) BUG() in jffs2_mark_node_obsolete() 
+	   from triggering */
+	if(!f->inocache->nlink)
+		down(&c->alloc_sem);
+
+	down(&f->sem);
 
 	frags = f->fraglist;
 	fds = f->dents;
@@ -487,7 +428,7 @@
 	while (frags) {
 		frag = frags;
 		frags = frag->next;
-		D2(printk(KERN_DEBUG "jffs2_clear_inode: frag at 0x%x-0x%x: node %p, frags %d--\n", frag->ofs, frag->ofs+frag->size, frag->node, frag->node?frag->node->frags:0));
+		D2(printk(KERN_DEBUG "jffs2_do_clear_inode: frag at 0x%x-0x%x: node %p, frags %d--\n", frag->ofs, frag->ofs+frag->size, frag->node, frag->node?frag->node->frags:0));
 
 		if (frag->node && !(--frag->node->frags)) {
 			/* Not a hole, and it's the final remaining frag of this node. Free the node */
@@ -503,10 +444,12 @@
 		fds = fd->next;
 		jffs2_free_full_dirent(fd);
 	}
-	//	if (!f->inocache->nlink) {
-		//		D1(printk(KERN_DEBUG "jffs2_clear_inode() deleting inode #%lu\n", inode->i_ino));
-		//		jffs2_del_ino_cache(JFFS2_SB_INFO(inode->i_sb), f->inocache);
-		//		jffs2_free_inode_cache(f->inocache);
-	//	}
-};
 
+	/* Urgh. Is there a nicer way to do this? */
+	if(!f->inocache->nlink) {
+		up(&f->sem);
+		up(&c->alloc_sem);
+	} else {
+		up(&f->sem);
+	}
+}
diff -Nru a/fs/jffs2/scan.c b/fs/jffs2/scan.c
--- a/fs/jffs2/scan.c	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/scan.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,12 +31,11 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: scan.c,v 1.51.2.2 2002/02/23 13:34:31 dwmw2 Exp $
+ * $Id: scan.c,v 1.69 2002/03/08 11:03:23 dwmw2 Exp $
  *
  */
 #include <linux/kernel.h>
 #include <linux/slab.h>
-#include <linux/jffs2.h>
 #include <linux/mtd/mtd.h>
 #include <linux/pagemap.h>
 #include <linux/crc32.h>
@@ -71,15 +70,21 @@
  * Returning an error will abort the mount - bad checksums etc. should just mark the space
  * as dirty.
  */
-static int jffs2_scan_empty(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, __u32 *ofs, int *noise);
-static int jffs2_scan_inode_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, __u32 *ofs);
-static int jffs2_scan_dirent_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, __u32 *ofs);
-
+static int jffs2_scan_empty(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *ofs, int *noise);
+static int jffs2_scan_inode_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *ofs);
+static int jffs2_scan_dirent_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *ofs);
+
+#define BLK_STATE_ALLFF		0
+#define BLK_STATE_CLEAN		1
+#define BLK_STATE_PARTDIRTY	2
+#define BLK_STATE_CLEANMARKER	3
+#define BLK_STATE_ALLDIRTY	4
+#define BLK_STATE_BADBLOCK	5
 
 int jffs2_scan_medium(struct jffs2_sb_info *c)
 {
 	int i, ret;
-	__u32 empty_blocks = 0;
+	uint32_t empty_blocks = 0, bad_blocks = 0;
 
 	if (!c->blocks) {
 		printk(KERN_WARNING "EEEK! c->blocks is NULL!\n");
@@ -95,7 +100,8 @@
 		ACCT_PARANOIA_CHECK(jeb);
 
 		/* Now decide which list to put it on */
-		if (ret == 1) {
+		switch(ret) {
+		case BLK_STATE_ALLFF:
 			/* 
 			 * Empty block.   Since we can't be sure it 
 			 * was entirely erased, we just queue it for erase
@@ -103,10 +109,12 @@
 			 * is complete.  Meanwhile we still count it as empty
 			 * for later checks.
 			 */
-			list_add(&jeb->list, &c->erase_pending_list);
 			empty_blocks++;
+			list_add(&jeb->list, &c->erase_pending_list);
 			c->nr_erasing_blocks++;
-		} else if (jeb->used_size == PAD(sizeof(struct jffs2_unknown_node)) && !jeb->first_node->next_in_ino) {
+			break;
+
+		case BLK_STATE_CLEANMARKER:
 			/* Only a CLEANMARKER node is valid */
 			if (!jeb->dirty_size) {
 				/* It's actually free */
@@ -118,10 +126,14 @@
 				list_add(&jeb->list, &c->erase_pending_list);
 				c->nr_erasing_blocks++;
 			}
-		} else if (jeb->used_size > c->sector_size - (2*sizeof(struct jffs2_raw_inode))) {
+			break;
+
+		case BLK_STATE_CLEAN:
                         /* Full (or almost full) of clean data. Clean list */
                         list_add(&jeb->list, &c->clean_list);
-                } else if (jeb->used_size) {
+			break;
+
+		case BLK_STATE_PARTDIRTY:
                         /* Some data, but not full. Dirty list. */
                         /* Except that we want to remember the block with most free space,
                            and stick it in the 'nextblock' position to start writing to it.
@@ -131,26 +143,42 @@
                         if (jeb->free_size > 2*sizeof(struct jffs2_raw_inode) && 
                                 (!c->nextblock || c->nextblock->free_size < jeb->free_size)) {
                                 /* Better candidate for the next writes to go to */
-                                if (c->nextblock)
-                                        list_add(&c->nextblock->list, &c->dirty_list);
+                                if (c->nextblock) 
+					list_add(&c->nextblock->list, &c->dirty_list);
                                 c->nextblock = jeb;
                         } else {
                                 list_add(&jeb->list, &c->dirty_list);
                         }
-		} else {
+			break;
+
+		case BLK_STATE_ALLDIRTY:
 			/* Nothing valid - not even a clean marker. Needs erasing. */
                         /* For now we just put it on the erasing list. We'll start the erases later */
-			printk(KERN_NOTICE "JFFS2: Erase block at 0x%08x is not formatted. It will be erased\n", jeb->offset);
+			D1(printk(KERN_NOTICE "JFFS2: Erase block at 0x%08x is not formatted. It will be erased\n", jeb->offset));
                         list_add(&jeb->list, &c->erase_pending_list);
 			c->nr_erasing_blocks++;
+			break;
+			
+		case BLK_STATE_BADBLOCK:
+			D1(printk(KERN_NOTICE "JFFS2: Block at 0x%08x is bad\n", jeb->offset));
+                        list_add(&jeb->list, &c->bad_list);
+			c->bad_size += c->sector_size;
+			c->free_size -= c->sector_size;
+			bad_blocks++;
+			break;
+		default:
+			printk("jffs2_scan_medium(): unknown block state\n");
+			BUG();	
 		}
 	}
+
 	/* Rotate the lists by some number to ensure wear levelling */
 	jffs2_rotate_lists(c);
 
 	if (c->nr_erasing_blocks) {
-		if (!c->used_size && empty_blocks != c->nr_blocks) {
+		if ( !c->used_size && ((empty_blocks+bad_blocks)!= c->nr_blocks || bad_blocks == c->nr_blocks) ) {
 			printk(KERN_NOTICE "Cowardly refusing to erase blocks on filesystem with no valid JFFS2 nodes\n");
+			printk(KERN_NOTICE "empty_blocks %d, bad_blocks %d, c->nr_blocks %d\n",empty_blocks,bad_blocks,c->nr_blocks);
 			return -EIO;
 		}
 		jffs2_erase_pending_trigger(c);
@@ -160,27 +188,62 @@
 
 static int jffs2_scan_eraseblock (struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb) {
 	struct jffs2_unknown_node node;
-	__u32 ofs, prevofs;
-	__u32 hdr_crc, nodetype;
+	uint32_t ofs, prevofs;
+	uint32_t hdr_crc, nodetype;
 	int err;
 	int noise = 0;
+#ifdef CONFIG_JFFS2_FS_NAND
+	int cleanmarkerfound=0;
+#endif
 
 	ofs = jeb->offset;
 	prevofs = jeb->offset - 1;
 
 	D1(printk(KERN_DEBUG "jffs2_scan_eraseblock(): Scanning block at 0x%x\n", ofs));
 
+#ifdef CONFIG_JFFS2_FS_NAND
+	if (jffs2_cleanmarker_oob(c)) {
+		int ret = jffs2_check_nand_cleanmarker(c, jeb);
+		D2(printk(KERN_NOTICE "jffs_check_nand_cleanmarker returned %d\n",ret));
+		/* Even if it's not found, we still scan to see
+		   if the block is empty. We use this information
+		   to decide whether to erase it or not. */
+		switch (ret) {
+		case 0:		cleanmarkerfound = 1; break;
+		case 1: 	break;
+		case 2: 	return BLK_STATE_BADBLOCK;
+		case 3:		return BLK_STATE_ALLDIRTY; /* Block has failed to erase min. once */
+		default: 	return ret;
+		}
+	}
+#endif
 	err = jffs2_scan_empty(c, jeb, &ofs, &noise);
-	if (err) return err;
+	if (err)
+		return err;
+
 	if (ofs == jeb->offset + c->sector_size) {
+#ifdef CONFIG_JFFS2_FS_NAND
+		if (jffs2_cleanmarker_oob(c)) {
+			/* scan oob, take care of cleanmarker */
+			int ret = jffs2_check_oob_empty(c, jeb, cleanmarkerfound);
+			D2(printk(KERN_NOTICE "jffs_check_oob_empty returned %d\n",ret));
+			switch (ret) {
+			case 0:		return cleanmarkerfound ? BLK_STATE_CLEANMARKER : BLK_STATE_ALLFF;
+			case 1: 	return BLK_STATE_ALLDIRTY;
+			case 2: 	return BLK_STATE_BADBLOCK; /* case 2/3 are paranoia checks */
+			case 3:		return BLK_STATE_ALLDIRTY; /* Block has failed to erase min. once */
+			default: 	return ret;
+			}
+		}
+#endif
 		D1(printk(KERN_DEBUG "Block at 0x%08x is empty (erased)\n", jeb->offset));
-		return 1;	/* special return code */
+		return BLK_STATE_ALLFF;	/* OK to erase if all blocks are like this */
 	}
 	
 	noise = 10;
 
 	while(ofs < jeb->offset + c->sector_size) {
-		ssize_t retlen;
+		size_t retlen;
 		ACCT_PARANOIA_CHECK(jeb);
 		
 		if (ofs & 3) {
@@ -202,8 +265,7 @@
 			break;
 		}
 
-		err = c->mtd->read(c->mtd, ofs, sizeof(node), &retlen, (char *)&node);
-		
+		err = jffs2_flash_read(c, ofs, sizeof(node), &retlen, (char *)&node);
 		if (err) {
 			D1(printk(KERN_WARNING "mtd->read(0x%x bytes from 0x%x) returned %d\n", sizeof(node), ofs, err));
 			return err;
@@ -261,7 +323,15 @@
 			continue;
 		}
 
-		switch(node.nodetype | JFFS2_NODE_ACCURATE) {
+		if (!(node.nodetype & JFFS2_NODE_ACCURATE)) {
+			/* Wheee. This is an obsoleted node */
+			D2(printk(KERN_DEBUG "Node at 0x%08x is obsolete. Skipping\n", ofs));
+			DIRTY_SPACE(PAD(node.totlen));
+			ofs += PAD(node.totlen);
+			continue;
+		}
+
+		switch(node.nodetype) {
 		case JFFS2_NODETYPE_INODE:
 			err = jffs2_scan_inode_node(c, jeb, &ofs);
 			if (err) return err;
@@ -304,7 +374,7 @@
 			case JFFS2_FEATURE_ROCOMPAT:
 				printk(KERN_NOTICE "Read-only compatible feature node (0x%04x) found at offset 0x%08x\n", node.nodetype, ofs);
 			        c->flags |= JFFS2_SB_FLAG_RO;
-				if (!(OFNI_BS_2SFFJ(c)->s_flags & MS_RDONLY))
+				if (!(jffs2_is_readonly(c)))
 					return -EROFS;
 				DIRTY_SPACE(PAD(node.totlen));
 				ofs += PAD(node.totlen);
@@ -315,43 +385,54 @@
 				return -EINVAL;
 
 			case JFFS2_FEATURE_RWCOMPAT_DELETE:
-				printk(KERN_NOTICE "Unknown but compatible feature node (0x%04x) found at offset 0x%08x\n", node.nodetype, ofs);
+				D1(printk(KERN_NOTICE "Unknown but compatible feature node (0x%04x) found at offset 0x%08x\n", node.nodetype, ofs));
 				DIRTY_SPACE(PAD(node.totlen));
 				ofs += PAD(node.totlen);
 				break;
 
 			case JFFS2_FEATURE_RWCOMPAT_COPY:
-				printk(KERN_NOTICE "Unknown but compatible feature node (0x%04x) found at offset 0x%08x\n", node.nodetype, ofs);
+				D1(printk(KERN_NOTICE "Unknown but compatible feature node (0x%04x) found at offset 0x%08x\n", node.nodetype, ofs));
 				USED_SPACE(PAD(node.totlen));
 				ofs += PAD(node.totlen);
 				break;
 			}
 		}
 	}
+
+
 	D1(printk(KERN_DEBUG "Block at 0x%08x: free 0x%08x, dirty 0x%08x, used 0x%08x\n", jeb->offset, 
 		  jeb->free_size, jeb->dirty_size, jeb->used_size));
-	return 0;
+
+	if (jeb->used_size == PAD(sizeof(struct jffs2_unknown_node)) && 
+	    !jeb->first_node->next_in_ino && !jeb->dirty_size)
+		return BLK_STATE_CLEANMARKER;
+	else if (jeb->used_size > c->sector_size - (2*sizeof(struct jffs2_raw_inode)))
+		return BLK_STATE_CLEAN;
+	else if (jeb->used_size)
+		return BLK_STATE_PARTDIRTY;
+	else
+		return BLK_STATE_ALLDIRTY;
 }
 
 /* We're pointing at the first empty word on the flash. Scan and account for the whole dirty region */
-static int jffs2_scan_empty(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, __u32 *startofs, int *noise)
+static int jffs2_scan_empty(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *startofs, int *noise)
 {
-	__u32 *buf;
-	__u32 scanlen = (jeb->offset + c->sector_size) - *startofs;
-	__u32 curofs = *startofs;
+	uint32_t *buf;
+	uint32_t scanlen = (jeb->offset + c->sector_size) - *startofs;
+	uint32_t curofs = *startofs;
 	
-	buf = kmalloc(min((__u32)PAGE_SIZE, scanlen), GFP_KERNEL);
+	buf = kmalloc(min((uint32_t)PAGE_SIZE, scanlen), GFP_KERNEL);
 	if (!buf) {
 		printk(KERN_WARNING "Scan buffer allocation failed\n");
 		return -ENOMEM;
 	}
 	while(scanlen) {
-		ssize_t retlen;
+		size_t retlen;
 		int ret, i;
 		
-		ret = c->mtd->read(c->mtd, curofs, min((__u32)PAGE_SIZE, scanlen), &retlen, (char *)buf);
-		if(ret) {
-			D1(printk(KERN_WARNING "jffs2_scan_empty(): Read 0x%x bytes at 0x%08x returned %d\n", min((__u32)PAGE_SIZE, scanlen), curofs, ret));
+		ret = jffs2_flash_read(c, curofs, min((uint32_t)PAGE_SIZE, scanlen), &retlen, (char *)buf);
+		if (ret) {
+			D1(printk(KERN_WARNING "jffs2_scan_empty(): Read 0x%x bytes at 0x%08x returned %d\n", min((uint32_t)PAGE_SIZE, scanlen), curofs, ret));
 			kfree(buf);
 			return ret;
 		}
@@ -363,7 +444,6 @@
 		for (i=0; i<(retlen / 4); i++) {
 			if (buf[i] != 0xffffffff) {
 				curofs += i*4;
-
 				noisy_printk(noise, "jffs2_scan_empty(): Empty block at 0x%08x ends at 0x%08x (with 0x%08x)! Marking dirty\n", *startofs, curofs, buf[i]);
 				DIRTY_SPACE(curofs - (*startofs));
 				*startofs = curofs;
@@ -381,7 +461,7 @@
 	return 0;
 }
 
-static struct jffs2_inode_cache *jffs2_scan_make_ino_cache(struct jffs2_sb_info *c, __u32 ino)
+static struct jffs2_inode_cache *jffs2_scan_make_ino_cache(struct jffs2_sb_info *c, uint32_t ino)
 {
 	struct jffs2_inode_cache *ic;
 
@@ -410,21 +490,21 @@
 	return ic;
 }
 
-static int jffs2_scan_inode_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, __u32 *ofs)
+static int jffs2_scan_inode_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *ofs)
 {
 	struct jffs2_raw_node_ref *raw;
 	struct jffs2_full_dnode *fn;
 	struct jffs2_tmp_dnode_info *tn, **tn_list;
 	struct jffs2_inode_cache *ic;
 	struct jffs2_raw_inode ri;
-	__u32 crc;
-	__u16 oldnodetype;
+	uint32_t crc;
+	uint16_t oldnodetype;
 	int ret;
-	ssize_t retlen;
+	size_t retlen;
 
 	D1(printk(KERN_DEBUG "jffs2_scan_inode_node(): Node at 0x%08x\n", *ofs));
 
-	ret = c->mtd->read(c->mtd, *ofs, sizeof(ri), &retlen, (char *)&ri);
+	ret = jffs2_flash_read(c, *ofs, sizeof(ri), &retlen, (char *)&ri);
 	if (ret) {
 		printk(KERN_NOTICE "jffs2_scan_inode_node(): Read error at 0x%08x: %d\n", *ofs, ret);
 		return ret;
@@ -460,14 +540,14 @@
 	if (ri.csize) {
 		/* Check data CRC too */
 		unsigned char *dbuf;
-		__u32 crc;
+		uint32_t crc;
 
 		dbuf = kmalloc(PAGE_CACHE_SIZE, GFP_KERNEL);
 		if (!dbuf) {
 			printk(KERN_NOTICE "jffs2_scan_inode_node(): allocation of temporary data buffer for CRC check failed\n");
 			return -ENOMEM;
 		}
-		ret = c->mtd->read(c->mtd, *ofs+sizeof(ri), ri.csize, &retlen, dbuf);
+		ret = jffs2_flash_read(c, *ofs+sizeof(ri), ri.csize, &retlen, dbuf);
 		if (ret) {
 			printk(KERN_NOTICE "jffs2_scan_inode_node(): Read error at 0x%08x: %d\n", *ofs+sizeof(ri), ret);
 			kfree(dbuf);
@@ -551,6 +631,13 @@
 	}
 
 	if (ri.nodetype & JFFS2_NODE_ACCURATE) {
+
+		/* Only do fraglist truncation in pass1 for S_IFREG inodes */
+		if (S_ISREG(ri.mode) && ic->scan->version < ri.version) {
+			ic->scan->version = ri.version;
+			ic->scan->isize = ri.isize;
+		}
+
 		memset(fn,0,sizeof(*fn));
 
 		fn->ofs = ri.offset;
@@ -587,20 +674,20 @@
 	return 0;
 }
 
-static int jffs2_scan_dirent_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, __u32 *ofs)
+static int jffs2_scan_dirent_node(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, uint32_t *ofs)
 {
 	struct jffs2_raw_node_ref *raw;
 	struct jffs2_full_dirent *fd;
 	struct jffs2_inode_cache *ic;
 	struct jffs2_raw_dirent rd;
-	__u16 oldnodetype;
+	uint16_t oldnodetype;
 	int ret;
-	__u32 crc;
-	ssize_t retlen;
+	uint32_t crc;
+	size_t retlen;
 
 	D1(printk(KERN_DEBUG "jffs2_scan_dirent_node(): Node at 0x%08x\n", *ofs));
 
-	ret = c->mtd->read(c->mtd, *ofs, sizeof(rd), &retlen, (char *)&rd);
+	ret = jffs2_flash_read(c, *ofs, sizeof(rd), &retlen, (char *)&rd);
 	if (ret) {
 		printk(KERN_NOTICE "jffs2_scan_dirent_node(): Read error at 0x%08x: %d\n", *ofs, ret);
 		return ret;
@@ -632,8 +719,8 @@
 	fd = jffs2_alloc_full_dirent(rd.nsize+1);
 	if (!fd) {
 		return -ENOMEM;
-}
-	ret = c->mtd->read(c->mtd, *ofs + sizeof(rd), rd.nsize, &retlen, &fd->name[0]);
+	}
+	ret = jffs2_flash_read(c, *ofs + sizeof(rd), rd.nsize, &retlen, &fd->name[0]);
 	if (ret) {
 		jffs2_free_full_dirent(fd);
 		printk(KERN_NOTICE "jffs2_scan_dirent_node(): Read error at 0x%08x: %d\n", 
@@ -646,6 +733,7 @@
 		       retlen, *ofs + sizeof(rd), rd.nsize);
 		return -EIO;
 	}
+
 	crc = crc32(0, fd->name, rd.nsize);
 	if (crc != rd.name_crc) {
 		printk(KERN_NOTICE "jffs2_scan_dirent_node(): Name CRC failed on node at 0x%08x: Read 0x%08x, calculated 0x%08x\n",
@@ -690,13 +778,11 @@
 		fd->name[rd.nsize]=0;
 		fd->nhash = full_name_hash(fd->name, rd.nsize);
 		fd->type = rd.type;
-
 		USED_SPACE(PAD(rd.totlen));
 		jffs2_add_fd_to_list(c, fd, &ic->scan->dents);
 	} else {
 		raw->flash_offset |= 1;
 		jffs2_free_full_dirent(fd);
-
 		DIRTY_SPACE(PAD(rd.totlen));
 	} 
 	*ofs += PAD(rd.totlen);
@@ -721,8 +807,9 @@
 	struct list_head *n = head->next;
 
 	list_del(head);
-	while(count--)
+	while(count--) {
 		n = n->next;
+	}
 	list_add(head, n);
 }
 
@@ -743,4 +830,5 @@
 
 	if (c->nr_free_blocks) /* Not that it should ever be zero */
 		rotate_list((&c->free_list), pseudo_random % c->nr_free_blocks);
+
 }
diff -Nru a/fs/jffs2/super.c b/fs/jffs2/super.c
--- a/fs/jffs2/super.c	Fri Mar 15 17:51:02 2002
+++ b/fs/jffs2/super.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,8 +31,7 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: super.c,v 1.48.2.1 2002/02/23 14:13:34 dwmw2 Exp $
- * + zlib_init calls from v1.56
+ * $Id: super.c,v 1.62 2002/03/12 16:23:41 dwmw2 Exp $
  *
  */
 
@@ -50,25 +49,41 @@
 #include <linux/interrupt.h>
 #include "nodelist.h"
 
-#ifndef MTD_BLOCK_MAJOR
-#define MTD_BLOCK_MAJOR 31
-#endif
-
-extern void jffs2_read_inode (struct inode *);
 void jffs2_put_super (struct super_block *);
-void jffs2_write_super (struct super_block *);
-static int jffs2_statfs (struct super_block *, struct statfs *);
-int jffs2_remount_fs (struct super_block *, int *, char *);
-extern void jffs2_clear_inode (struct inode *);
-extern void jffs2_destroy_inode (struct inode *);
-extern struct inode *jffs2_alloc_inode (struct super_block *);
- 
+
+
+static kmem_cache_t *jffs2_inode_cachep;
+
+static struct inode *jffs2_alloc_inode(struct super_block *sb)
+{
+	struct jffs2_inode_info *ei;
+	ei = (struct jffs2_inode_info *)kmem_cache_alloc(jffs2_inode_cachep, SLAB_KERNEL);
+	if (!ei)
+		return NULL;
+	return &ei->vfs_inode;
+}
+
+static void jffs2_destroy_inode(struct inode *inode)
+{
+	kmem_cache_free(jffs2_inode_cachep, JFFS2_INODE_INFO(inode));
+}
+
+static void jffs2_i_init_once(void * foo, kmem_cache_t * cachep, unsigned long flags)
+{
+	struct jffs2_inode_info *ei = (struct jffs2_inode_info *) foo;
+
+	if ((flags & (SLAB_CTOR_VERIFY|SLAB_CTOR_CONSTRUCTOR)) ==
+	    SLAB_CTOR_CONSTRUCTOR) {
+		init_MUTEX(&ei->sem);
+		inode_init_once(&ei->vfs_inode);
+	}
+}
+
 static struct super_operations jffs2_super_operations =
 {
 	alloc_inode:	jffs2_alloc_inode,
 	destroy_inode:	jffs2_destroy_inode,
 	read_inode:	jffs2_read_inode,
-//	delete_inode:	jffs2_delete_inode,
 	put_super:	jffs2_put_super,
 	write_super:	jffs2_write_super,
 	statfs:		jffs2_statfs,
@@ -76,222 +91,37 @@
 	clear_inode:	jffs2_clear_inode
 };
 
-static int jffs2_statfs(struct super_block *sb, struct statfs *buf)
-{
-	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
-	unsigned long avail;
 
-	buf->f_type = JFFS2_SUPER_MAGIC;
-	buf->f_bsize = 1 << PAGE_SHIFT;
-	buf->f_blocks = c->flash_size >> PAGE_SHIFT;
-	buf->f_files = 0;
-	buf->f_ffree = 0;
-	buf->f_namelen = JFFS2_MAX_NAME_LEN;
-
-	spin_lock_bh(&c->erase_completion_lock);
-
-	avail = c->dirty_size + c->free_size;
-	if (avail > c->sector_size * JFFS2_RESERVED_BLOCKS_WRITE)
-		avail -= c->sector_size * JFFS2_RESERVED_BLOCKS_WRITE;
-	else
-		avail = 0;
-
-	buf->f_bavail = buf->f_bfree = avail >> PAGE_SHIFT;
-
-#if CONFIG_JFFS2_FS_DEBUG > 0
-	printk(KERN_DEBUG "STATFS:\n");
-	printk(KERN_DEBUG "flash_size: %08x\n", c->flash_size);
-	printk(KERN_DEBUG "used_size: %08x\n", c->used_size);
-	printk(KERN_DEBUG "dirty_size: %08x\n", c->dirty_size);
-	printk(KERN_DEBUG "free_size: %08x\n", c->free_size);
-	printk(KERN_DEBUG "erasing_size: %08x\n", c->erasing_size);
-	printk(KERN_DEBUG "bad_size: %08x\n", c->bad_size);
-	printk(KERN_DEBUG "sector_size: %08x\n", c->sector_size);
-
-	if (c->nextblock) {
-		printk(KERN_DEBUG "nextblock: 0x%08x\n", c->nextblock->offset);
-	} else {
-		printk(KERN_DEBUG "nextblock: NULL\n");
-	}
-	if (c->gcblock) {
-		printk(KERN_DEBUG "gcblock: 0x%08x\n", c->gcblock->offset);
-	} else {
-		printk(KERN_DEBUG "gcblock: NULL\n");
-	}
-	if (list_empty(&c->clean_list)) {
-		printk(KERN_DEBUG "clean_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->clean_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "clean_list: %08x\n", jeb->offset);
-		}
-	}
-	if (list_empty(&c->dirty_list)) {
-		printk(KERN_DEBUG "dirty_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->dirty_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "dirty_list: %08x\n", jeb->offset);
-		}
-	}
-	if (list_empty(&c->erasing_list)) {
-		printk(KERN_DEBUG "erasing_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->erasing_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "erasing_list: %08x\n", jeb->offset);
-		}
-	}
-	if (list_empty(&c->erase_pending_list)) {
-		printk(KERN_DEBUG "erase_pending_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->erase_pending_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "erase_pending_list: %08x\n", jeb->offset);
-		}
-	}
-	if (list_empty(&c->free_list)) {
-		printk(KERN_DEBUG "free_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->free_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "free_list: %08x\n", jeb->offset);
-		}
-	}
-	if (list_empty(&c->bad_list)) {
-		printk(KERN_DEBUG "bad_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->bad_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "bad_list: %08x\n", jeb->offset);
-		}
-	}
-	if (list_empty(&c->bad_used_list)) {
-		printk(KERN_DEBUG "bad_used_list: empty\n");
-	} else {
-		struct list_head *this;
-
-		list_for_each(this, &c->bad_used_list) {
-			struct jffs2_eraseblock *jeb = list_entry(this, struct jffs2_eraseblock, list);
-			printk(KERN_DEBUG "bad_used_list: %08x\n", jeb->offset);
-		}
-	}
-#endif /* CONFIG_JFFS2_FS_DEBUG */
-
-	spin_unlock_bh(&c->erase_completion_lock);
-
-
-	return 0;
-}
-
-static int jffs2_fill_super(struct super_block *sb, void *data, int silent)
+static int jffs2_blk_fill_super(struct super_block *sb, void *data, int silent)
 {
 	struct jffs2_sb_info *c;
-	struct inode *root_i;
-	int i;
+	int ret;
 
-	D1(printk(KERN_DEBUG "jffs2: read_super for device %s\n", sb->s_id));
+	D1(printk(KERN_DEBUG "jffs2: blk_read_super for device %s\n", sb->s_id));
 
 	if (major(sb->s_dev) != MTD_BLOCK_MAJOR) {
 		if (!silent)
-			printk(KERN_DEBUG "jffs2: attempt to mount non-MTD device %s\n", kdevname(sb->s_dev));
+			printk(KERN_NOTICE "jffs2: attempt to mount non-MTD device %s\n",
+			       sb->s_id);
 		return -EINVAL;
 	}
 
 	c = JFFS2_SB_INFO(sb);
 	memset(c, 0, sizeof(*c));
 	
+	sb->s_op = &jffs2_super_operations;
+
 	c->mtd = get_mtd_device(NULL, minor(sb->s_dev));
 	if (!c->mtd) {
 		D1(printk(KERN_DEBUG "jffs2: MTD device #%u doesn't appear to exist\n", minor(sb->s_dev)));
 		return -EINVAL;
 	}
-	c->sector_size = c->mtd->erasesize;
-	c->free_size = c->flash_size = c->mtd->size;
-	c->nr_blocks = c->mtd->size / c->mtd->erasesize;
-	c->blocks = kmalloc(sizeof(struct jffs2_eraseblock) * c->nr_blocks, GFP_KERNEL);
-	if (!c->blocks)
-		goto out_mtd;
-	for (i=0; i<c->nr_blocks; i++) {
-		INIT_LIST_HEAD(&c->blocks[i].list);
-		c->blocks[i].offset = i * c->sector_size;
-		c->blocks[i].free_size = c->sector_size;
-		c->blocks[i].dirty_size = 0;
-		c->blocks[i].used_size = 0;
-		c->blocks[i].first_node = NULL;
-		c->blocks[i].last_node = NULL;
-	}
-		
-	spin_lock_init(&c->nodelist_lock);
-	init_MUTEX(&c->alloc_sem);
-	init_waitqueue_head(&c->erase_wait);
-	spin_lock_init(&c->erase_completion_lock);
-	spin_lock_init(&c->inocache_lock);
-
-	INIT_LIST_HEAD(&c->clean_list);
-	INIT_LIST_HEAD(&c->dirty_list);
-	INIT_LIST_HEAD(&c->erasing_list);
-	INIT_LIST_HEAD(&c->erase_pending_list);
-	INIT_LIST_HEAD(&c->erase_complete_list);
-	INIT_LIST_HEAD(&c->free_list);
-	INIT_LIST_HEAD(&c->bad_list);
-	INIT_LIST_HEAD(&c->bad_used_list);
-	c->highest_ino = 1;
-
-	c->flags |= JFFS2_SB_FLAG_MOUNTING;
-
-	if (jffs2_build_filesystem(c)) {
-		D1(printk(KERN_DEBUG "build_fs failed\n"));
-		goto out_nodes;
-	}
 
-	c->flags &= ~JFFS2_SB_FLAG_MOUNTING;
+	ret = jffs2_do_fill_super(sb, data, silent);
+	if (ret)
+		put_mtd_device(c->mtd);
 
-	sb->s_op = &jffs2_super_operations;
-
-	D1(printk(KERN_DEBUG "jffs2_read_super(): Getting root inode\n"));
-	root_i = iget(sb, 1);
-	if (is_bad_inode(root_i)) {
-		D1(printk(KERN_WARNING "get root inode failed\n"));
-		goto out_nodes;
-	}
-
-	D1(printk(KERN_DEBUG "jffs2_read_super(): d_alloc_root()\n"));
-	sb->s_root = d_alloc_root(root_i);
-	if (!sb->s_root)
-		goto out_root_i;
-
-#if LINUX_VERSION_CODE >= 0x20403
-	sb->s_maxbytes = 0xFFFFFFFF;
-#endif
-	sb->s_blocksize = PAGE_CACHE_SIZE;
-	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
-	sb->s_magic = JFFS2_SUPER_MAGIC;
-	if (!(sb->s_flags & MS_RDONLY))
-		jffs2_start_garbage_collect_thread(c);
-	return 0;
-
- out_root_i:
-	iput(root_i);
- out_nodes:
-	jffs2_free_ino_caches(c);
-	jffs2_free_raw_node_refs(c);
-	kfree(c->blocks);
- out_mtd:
-	put_mtd_device(c->mtd);
-	return -EINVAL;
+	return ret;
 }
 
 void jffs2_put_super (struct super_block *sb)
@@ -300,8 +130,10 @@
 
 	D2(printk(KERN_DEBUG "jffs2: jffs2_put_super()\n"));
 
+
 	if (!(sb->s_flags & MS_RDONLY))
 		jffs2_stop_garbage_collect_thread(c);
+	jffs2_flush_wbuf(c, 1);
 	jffs2_free_ino_caches(c);
 	jffs2_free_raw_node_refs(c);
 	kfree(c->blocks);
@@ -312,68 +144,36 @@
 	D1(printk(KERN_DEBUG "jffs2_put_super returning\n"));
 }
 
-int jffs2_remount_fs (struct super_block *sb, int *flags, char *data)
-{
-	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
-
-	if (c->flags & JFFS2_SB_FLAG_RO && !(sb->s_flags & MS_RDONLY))
-		return -EROFS;
-
-	/* We stop if it was running, then restart if it needs to.
-	   This also catches the case where it was stopped and this
-	   is just a remount to restart it */
-	if (!(sb->s_flags & MS_RDONLY))
-		jffs2_stop_garbage_collect_thread(c);
-
-	if (!(*flags & MS_RDONLY))
-		jffs2_start_garbage_collect_thread(c);
-	
-	sb->s_flags = (sb->s_flags & ~MS_RDONLY)|(*flags & MS_RDONLY);
-
-	return 0;
-}
-
-void jffs2_write_super (struct super_block *sb)
-{
-	struct jffs2_sb_info *c = JFFS2_SB_INFO(sb);
-	sb->s_dirt = 0;
-
-	if (sb->s_flags & MS_RDONLY)
-		return;
-
-	jffs2_garbage_collect_trigger(c);
-	jffs2_erase_pending_blocks(c);
-	jffs2_mark_erased_blocks(c);
-}
-
 static struct super_block *jffs2_get_sb(struct file_system_type *fs_type,
-	int flags, char *dev_name, void *data)
+					int flags, char *dev_name, void *data)
 {
-	return get_sb_bdev(fs_type, flags, dev_name, data, jffs2_fill_super);
+	return get_sb_bdev(fs_type, flags, dev_name, data, jffs2_blk_fill_super);
 }
-
+ 
 static struct file_system_type jffs2_fs_type = {
 	owner:		THIS_MODULE,
 	name:		"jffs2",
 	get_sb:		jffs2_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
+
+
 static int __init init_jffs2_fs(void)
 {
 	int ret;
 
-	printk(KERN_NOTICE "JFFS2 version 2.1. (C) 2001 Red Hat, Inc., designed by Axis Communications AB.\n");
+	printk(KERN_INFO "JFFS2 version 2.1. (C) 2001, 2002 Red Hat, Inc.\n");
 
-#ifdef JFFS2_OUT_OF_KERNEL
-	/* sanity checks. Could we do these at compile time? */
-	if (sizeof(struct jffs2_sb_info) > sizeof (((struct super_block *)NULL)->u)) {
-		printk(KERN_ERR "JFFS2 error: struct jffs2_sb_info (%d bytes) doesn't fit in the super_block union (%d bytes)\n", 
-		       sizeof(struct jffs2_sb_info), sizeof (((struct super_block *)NULL)->u));
-		return -EIO;
+	jffs2_inode_cachep = kmem_cache_create("jffs2_i",
+					     sizeof(struct jffs2_inode_info),
+					     0, SLAB_HWCACHE_ALIGN,
+					     jffs2_i_init_once, NULL);
+	if (!jffs2_inode_cachep) {
+		printk(KERN_ERR "JFFS2 error: Failed to initialise inode cache\n");
+		return -ENOMEM;
 	}
-#endif
-
 	ret = jffs2_zlib_init();
 	if (ret) {
 		printk(KERN_ERR "JFFS2 error: Failed to initialise zlib workspaces\n");
@@ -394,9 +194,10 @@
 
 static void __exit exit_jffs2_fs(void)
 {
+	unregister_filesystem(&jffs2_fs_type);
 	jffs2_destroy_slab_caches();
 	jffs2_zlib_exit();
-	unregister_filesystem(&jffs2_fs_type);
+	kmem_cache_destroy(jffs2_inode_cachep);
 }
 
 module_init(init_jffs2_fs);
diff -Nru a/fs/jffs2/symlink.c b/fs/jffs2/symlink.c
--- a/fs/jffs2/symlink.c	Fri Mar 15 17:51:00 2002
+++ b/fs/jffs2/symlink.c	Fri Mar 15 17:51:00 2002
@@ -31,7 +31,7 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: symlink.c,v 1.5.2.1 2002/01/15 10:39:06 dwmw2 Exp $
+ * $Id: symlink.c,v 1.9 2002/01/10 09:29:53 dwmw2 Exp $
  *
  */
 
@@ -39,7 +39,6 @@
 #include <linux/kernel.h>
 #include <linux/slab.h>
 #include <linux/fs.h>
-#include <linux/jffs2.h>
 #include "nodelist.h"
 
 int jffs2_readlink(struct dentry *dentry, char *buffer, int buflen);
@@ -52,40 +51,12 @@
 	setattr:	jffs2_setattr
 };
 
-static char *jffs2_getlink(struct dentry *dentry)
-{
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(dentry->d_inode);
-	char *buf;
-	int ret;
-
-	down(&f->sem);
-	if (!f->metadata) {
-		up(&f->sem);
-		printk(KERN_NOTICE "No metadata for symlink inode #%lu\n", dentry->d_inode->i_ino);
-		return ERR_PTR(-EINVAL);
-	}
-	buf = kmalloc(f->metadata->size+1, GFP_USER);
-	if (!buf) {
-		up(&f->sem);
-		return ERR_PTR(-ENOMEM);
-	}
-	buf[f->metadata->size]=0;
-
-	ret = jffs2_read_dnode(JFFS2_SB_INFO(dentry->d_inode->i_sb), f->metadata, buf, 0, f->metadata->size);
-	up(&f->sem);
-	if (ret) {
-		kfree(buf);
-		return ERR_PTR(ret);
-	}
-	return buf;
-
-}
 int jffs2_readlink(struct dentry *dentry, char *buffer, int buflen)
 {
 	unsigned char *kbuf;
 	int ret;
 
-	kbuf = jffs2_getlink(dentry);
+	kbuf = jffs2_getlink(JFFS2_SB_INFO(dentry->d_inode->i_sb), JFFS2_INODE_INFO(dentry->d_inode));
 	if (IS_ERR(kbuf))
 		return PTR_ERR(kbuf);
 
@@ -99,7 +70,7 @@
 	unsigned char *buf;
 	int ret;
 
-	buf = jffs2_getlink(dentry);
+	buf = jffs2_getlink(JFFS2_SB_INFO(dentry->d_inode->i_sb), JFFS2_INODE_INFO(dentry->d_inode));
 
 	if (IS_ERR(buf))
 		return PTR_ERR(buf);
diff -Nru a/fs/jffs2/wbuf.c b/fs/jffs2/wbuf.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/jffs2/wbuf.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,674 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
+ *
+ * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * The original JFFS, from which the design for JFFS2 was derived,
+ * was designed and implemented by Axis Communications AB.
+ *
+ * The contents of this file are subject to the Red Hat eCos Public
+ * License Version 1.1 (the "Licence"); you may not use this file
+ * except in compliance with the Licence.  You may obtain a copy of
+ * the Licence at http://www.redhat.com/
+ *
+ * Software distributed under the Licence is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
+ * See the Licence for the specific language governing rights and
+ * limitations under the Licence.
+ *
+ * The Original Code is JFFS2 - Journalling Flash File System, version 2
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use your
+ * version of this file under the RHEPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the RHEPL or the GPL.
+ *
+ * $Id: wbuf.c,v 1.7 2002/03/08 11:27:59 dwmw2 Exp $
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/mtd/mtd.h>
+#include <linux/interrupt.h>
+#include <linux/crc32.h>
+#include "nodelist.h"
+
+/* FIXME duplicated defines in wbuf.c and nand.c
+ * Constants for out of band layout
+ */
+#define NAND_JFFS2_OOB_BADBPOS		5
+#define NAND_JFFS2_OOB8_FSDAPOS		6
+#define NAND_JFFS2_OOB16_FSDAPOS	8
+#define NAND_JFFS2_OOB8_FSDALEN		2
+#define NAND_JFFS2_OOB16_FSDALEN	8
+
+#define MAX_ERASE_FAILURES 	5
+
+static inline void jffs2_refile_wbuf_blocks(struct jffs2_sb_info *c)
+{
+	struct list_head *this, *next;
+
+	if (list_empty(&c->erasable_pending_wbuf_list))
+		return;
+
+	list_for_each_safe(this, next, &c->erasable_pending_wbuf_list) {
+		list_del(this);
+		list_add_tail(this, &c->erasable_list);
+	}
+}
+
+int jffs2_flush_wbuf(struct jffs2_sb_info *c, int pad)
+{
+	int ret;
+	size_t retlen;
+
+	if(!c->wbuf || !c->wbuf_len)
+		return 0;
+
+	/* claim remaining space on the page
+	   this happens, if we have a change to a new block,
+	   or if fsync forces us to flush the writebuffer.
+	   if we have a switch to next page, we will not have
+	   enough remaining space for this. 
+	*/
+	if (pad) {
+		c->wbuf_len = PAD(c->wbuf_len);
+		
+		if ( c->wbuf_len + sizeof(struct jffs2_unknown_node) < c->wbuf_pagesize) {
+			struct jffs2_unknown_node *padnode = (void *)(c->wbuf + c->wbuf_len);
+			padnode->magic = JFFS2_MAGIC_BITMASK;
+			padnode->nodetype = JFFS2_NODETYPE_PADDING;
+			padnode->totlen = c->wbuf_pagesize - c->wbuf_len;
+			padnode->hdr_crc = crc32(0, padnode, sizeof(*padnode)-4);
+		}
+	}
+	/* else jffs2_flash_writev has actually filled in the rest of the
+	   buffer for us, and will deal with the node refs etc. later. */
+	
+	ret = c->mtd->write(c->mtd, c->wbuf_ofs, c->wbuf_pagesize, &retlen, c->wbuf);
+	
+	if (ret || retlen != c->wbuf_pagesize) {
+		if (ret)
+			printk(KERN_CRIT "jffs2_flush_wbuf(): Write failed with %d\n",ret);
+		else
+			printk(KERN_CRIT "jffs2_flush_wbuf(): Write was short %d instead of %d\n",retlen,c->wbuf_pagesize);
+			
+		ret = -EIO;		
+		/* CHECKME NAND 
+		   So that the caller knows what happened. If
+		   we were called from jffs2_flash_writev(), it'll
+		   know to return failure and _its_ caller will
+		   try again. writev gives back to jffs2_write_xxx 
+		   in write.c. There are the real fixme's
+		 */
+
+		/*  FIXME NAND
+		   If we were called from GC or fsync, there's no repair kit yet
+		*/
+		    
+		return ret; 
+	}
+
+	/* Adjusting free size of next block only, if it's called from fsync ! */
+	if (pad == 2) {
+		D1(printk(KERN_DEBUG "jffs2_flush_wbuf() adjusting free_size of c->nextblock\n"));
+		spin_lock_bh(&c->erase_completion_lock);
+		if (!c->nextblock)
+			BUG();
+		if (c->nextblock->free_size < (c->wbuf_pagesize - c->wbuf_len))
+			BUG();
+		c->nextblock->free_size -= (c->wbuf_pagesize - c->wbuf_len);
+		c->nextblock->dirty_size += (c->wbuf_pagesize - c->wbuf_len);
+		spin_unlock_bh(&c->erase_completion_lock);
+	}
+
+	/* Stick any now-obsoleted blocks on the erase_pending_list */
+	spin_lock_bh(&c->erase_completion_lock);
+	jffs2_refile_wbuf_blocks(c);
+	spin_unlock_bh(&c->erase_completion_lock);
+
+	memset(c->wbuf,0xff,c->wbuf_pagesize);
+	/* adjust write buffer offset, else we get a non contigous write bug */
+	c->wbuf_ofs+= c->wbuf_pagesize;
+	c->wbuf_len = 0;
+	return 0;
+}
+
+#define PAGE_DIV(x) ( (x) & (~(c->wbuf_pagesize - 1)) )
+#define PAGE_MOD(x) ( (x) & (c->wbuf_pagesize - 1) )
+int jffs2_flash_writev(struct jffs2_sb_info *c, const struct iovec *invecs, unsigned long count, loff_t to, size_t *retlen)
+{
+	struct iovec outvecs[3];
+	uint32_t totlen = 0;
+	uint32_t split_ofs = 0;
+	uint32_t old_totlen;
+	int ret, splitvec = -1;
+	int invec, outvec;
+	size_t wbuf_retlen;
+	unsigned char *wbuf_ptr;
+	size_t donelen = 0;
+	uint32_t outvec_to = to;
+
+	/* If not NAND flash, don't bother */
+	if (!c->wbuf)
+		return jffs2_flash_direct_writev(c, invecs, count, to, retlen);
+	
+	/* If wbuf_ofs is not initialized, set it to target adress */
+	if (c->wbuf_ofs == 0xFFFFFFFF) {
+		c->wbuf_ofs = PAGE_DIV(to);
+		c->wbuf_len = PAGE_MOD(to);			
+		memset(c->wbuf,0xff,c->wbuf_pagesize);
+	}
+
+	/* Sanity checks on target address. 
+	   It's permitted to write at PAD(c->wbuf_len+c->wbuf_ofs), 
+	   and it's permitted to write at the beginning of a new 
+	   erase block. Anything else, and you die.
+	   New block starts at xxx000c (0-b = block header)
+	*/
+	if ( (to & ~(c->sector_size-1)) != (c->wbuf_ofs & ~(c->sector_size-1)) ) {
+		/* It's a write to a new block */
+		if (c->wbuf_len) {
+			D1(printk(KERN_DEBUG "jffs2_flash_writev() to 0x%lx causes flush of wbuf at 0x%08x\n", (unsigned long)to, c->wbuf_ofs));
+			ret = jffs2_flush_wbuf(c, 1);
+			if (ret) {
+				/* the underlying layer has to check wbuf_len to do the cleanup */
+				D1(printk(KERN_WARNING "jffs2_flush_wbuf() called from jffs2_flash_writev() failed %d\n", ret));
+				*retlen = 0;
+				return ret;
+			}
+		}
+		/* set pointer to new block */
+		c->wbuf_ofs = PAGE_DIV(to);
+		c->wbuf_len = PAGE_MOD(to);			
+	} 
+
+	if (to != PAD(c->wbuf_ofs + c->wbuf_len)) {
+		/* We're not writing immediately after the writebuffer. Bad. */
+		printk(KERN_CRIT "jffs2_flash_writev(): Non-contiguous write to %08lx\n", (unsigned long)to);
+		if (c->wbuf_len)
+			printk(KERN_CRIT "wbuf was previously %08x-%08x\n",
+					  c->wbuf_ofs, c->wbuf_ofs+c->wbuf_len);
+		BUG();
+	}
+
+	/* Note outvecs[3] above. We know count is never greater than 2 */
+	if (count > 2) {
+		printk(KERN_CRIT "jffs2_flash_writev(): count is %ld\n", count);
+		BUG();
+	}
+
+	invec = 0;
+	outvec = 0;
+
+
+	/* Fill writebuffer first, if already in use */	
+	if (c->wbuf_len) {
+		uint32_t invec_ofs = 0;
+
+		/* adjust alignment offset */ 
+		if (c->wbuf_len != PAGE_MOD(to)) {
+			c->wbuf_len = PAGE_MOD(to);
+			/* take care of alignment to next page */
+			if (!c->wbuf_len)
+				c->wbuf_len = c->wbuf_pagesize;
+		}
+		
+		while(c->wbuf_len < c->wbuf_pagesize) {
+			uint32_t thislen;
+			
+			if (invec == count)
+				goto alldone;
+
+			thislen = c->wbuf_pagesize - c->wbuf_len;
+
+			if (thislen >= invecs[invec].iov_len)
+				thislen = invecs[invec].iov_len;
+	
+			invec_ofs = thislen;
+
+			memcpy(c->wbuf + c->wbuf_len, invecs[invec].iov_base, thislen);
+			c->wbuf_len += thislen;
+			donelen += thislen;
+			/* Get next invec, if actual did not fill the buffer */
+			if (c->wbuf_len < c->wbuf_pagesize) 
+				invec++;
+		}			
+		
+		/* write buffer is full, flush buffer */
+		ret = jffs2_flush_wbuf(c, 0);
+		if (ret) {
+			/* the underlying layer has to check wbuf_len to do the cleanup */
+			D1(printk(KERN_WARNING "jffs2_flush_wbuf() called from jffs2_flash_writev() failed %d\n", ret));
+			*retlen = 0;
+			return ret;
+		}
+		outvec_to += donelen;
+		c->wbuf_ofs = outvec_to;
+		
+		/* All invecs done ? */
+		if (invec == count)
+			goto alldone;
+
+		/* Set up the first outvec, containing the remainder of the
+		   invec we partially used */
+		if (invecs[invec].iov_len > invec_ofs) {
+			outvecs[0].iov_base = invecs[invec].iov_base+invec_ofs;
+			totlen = outvecs[0].iov_len = invecs[invec].iov_len-invec_ofs;
+			if (totlen > c->wbuf_pagesize) {
+				splitvec = outvec;
+				split_ofs = outvecs[0].iov_len - PAGE_MOD(totlen);
+			}
+			outvec++;
+		}
+		invec++;
+	}
+
+	/* OK, now we've flushed the wbuf and the start of the bits
+	   we have been asked to write, now to write the rest.... */
+
+	/* totlen holds the amount of data still to be written */
+	old_totlen = totlen;
+	for ( ; invec < count; invec++,outvec++ ) {
+		outvecs[outvec].iov_base = invecs[invec].iov_base;
+		totlen += outvecs[outvec].iov_len = invecs[invec].iov_len;
+		if (PAGE_DIV(totlen) != PAGE_DIV(old_totlen)) {
+			splitvec = outvec;
+			split_ofs = outvecs[outvec].iov_len - PAGE_MOD(totlen);
+			old_totlen = totlen;
+		}
+	}
+
+	/* Now the outvecs array holds all the remaining data to write */
+	/* Up to splitvec,split_ofs is to be written immediately. The rest
+	   goes into the (now-empty) wbuf */
+
+	if (splitvec != -1) {
+		uint32_t remainder;
+		int ret;
+
+		remainder = outvecs[splitvec].iov_len - split_ofs;
+		outvecs[splitvec].iov_len = split_ofs;
+
+		/* We did cross a page boundary, so we write some now */
+		ret = jffs2_flash_direct_writev(c, outvecs, splitvec+1, outvec_to, &wbuf_retlen); 
+		if (ret < 0 || wbuf_retlen != PAGE_DIV(totlen)) {
+			/* At this point we have no problem,
+			   c->wbuf is empty. 
+			*/
+			*retlen = donelen;
+			return ret;
+		}
+		
+		donelen += wbuf_retlen;
+		c->wbuf_ofs = PAGE_DIV(outvec_to) + PAGE_DIV(totlen);
+
+		if (remainder) {
+			outvecs[splitvec].iov_base += split_ofs;
+			outvecs[splitvec].iov_len = remainder;
+		} else {
+			splitvec++;
+		}
+
+	} else {
+		splitvec = 0;
+	}
+
+	/* Now splitvec points to the start of the bits we have to copy
+	   into the wbuf */
+	wbuf_ptr = c->wbuf;
+
+	for ( ; splitvec < outvec; splitvec++) {
+		/* Don't copy the wbuf into itself */
+		if (outvecs[splitvec].iov_base == c->wbuf)
+			continue;
+		memcpy(wbuf_ptr, outvecs[splitvec].iov_base, outvecs[splitvec].iov_len);
+		wbuf_ptr += outvecs[splitvec].iov_len;
+		donelen += outvecs[splitvec].iov_len;
+	}
+	c->wbuf_len = wbuf_ptr - c->wbuf;
+
+alldone:	
+	*retlen = donelen;
+	return 0;
+}
+
+/*
+	This is the entry for NOR-Flash. We use it also for NAND to flush wbuf
+*/
+int jffs2_flash_write(struct jffs2_sb_info *c, loff_t ofs, size_t len, size_t *retlen, const u_char *buf)
+{
+	return c->mtd->write(c->mtd, ofs, len, retlen, buf);
+}
+
+/*
+	Handle readback from writebuffer and ECC failure return
+*/
+int jffs2_flash_read(struct jffs2_sb_info *c, loff_t ofs, size_t len, size_t *retlen, u_char *buf)
+{
+	loff_t	orbf = 0, owbf = 0, lwbf = 0;
+	int	ret;
+
+	/* Read flash */
+	ret = c->mtd->read(c->mtd, ofs, len, retlen, buf);
+
+	if (!jffs2_can_mark_obsolete(c) && (ret == -EIO) && (*retlen == len) ) {
+		printk(KERN_WARNING "mtd->read(0x%x bytes from 0x%llx) returned ECC error\n", len, ofs);
+		/* 
+		 * We have the raw data without ECC correction in the buffer, maybe 
+		 * we are lucky and all data or parts are correct. We check the node.
+		 * If data are corrupted node check will sort it out.
+		 * We keep this block, it will fail on write or erase and the we
+		 * mark it bad. Or should we do that now? But we should give him a chance.
+		 * Maybe we had a system crash or power loss before the ecc write or  
+		 * a erase was completed.
+		 * So we return success. :)
+		 */
+		 ret = 0;	
+	}
+
+	/* if no writebuffer available or write buffer empty, return */
+	if (!c->wbuf_pagesize || !c->wbuf_len)
+		return ret;
+
+
+	/* if we read in a different block, return */
+	if ( (ofs & ~(c->sector_size-1)) != (c->wbuf_ofs & ~(c->sector_size-1)) ) 
+		return ret;	
+
+	if (ofs >= c->wbuf_ofs) {
+		owbf = (ofs - c->wbuf_ofs);	/* offset in write buffer */
+		if (owbf > c->wbuf_len)		/* is read beyond write buffer ? */
+			return ret;
+		lwbf = c->wbuf_len - owbf;	/* number of bytes to copy */
+		if (lwbf > len)	
+			lwbf = len;
+	} else {	
+		orbf = (c->wbuf_ofs - ofs);	/* offset in read buffer */
+		if (orbf > len)			/* is write beyond write buffer ? */
+			return ret;
+		lwbf = len - orbf; 		/* number of bytes to copy */
+		if (lwbf > c->wbuf_len)	
+			lwbf = c->wbuf_len;
+	}	
+	if (lwbf > 0)
+		memcpy(buf+orbf,c->wbuf+owbf,lwbf);
+
+	return ret;
+}
+
+/*
+ *	Check, if the out of band area is empty
+ */
+int jffs2_check_oob_empty( struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb, int mode)
+{
+	unsigned char *buf;
+	int 	ret = 0;
+	int	i,len,cnt,page;
+	size_t  retlen;
+	int	fsdata_pos,badblock_pos,oob_size;
+
+	oob_size = c->mtd->oobsize;
+
+	switch(c->mtd->ecctype) {
+	case MTD_ECC_SW:		
+		fsdata_pos = (c->wbuf_pagesize == 256) ? NAND_JFFS2_OOB8_FSDAPOS : NAND_JFFS2_OOB16_FSDAPOS;
+		badblock_pos = NAND_JFFS2_OOB_BADBPOS;
+		break;
+	default:
+		D1(printk(KERN_WARNING "jffs2_write_oob_empty(): Invalid ECC type\n"));
+		return -EINVAL;
+	}	
+
+	/* allocate a buffer for all oob data in this sector */
+	len = oob_size * (c->sector_size/c->mtd->oobblock);
+	buf = kmalloc(len, GFP_KERNEL);
+	if (!buf) {
+		printk(KERN_NOTICE "jffs2_check_oob_empty(): allocation of temporary data buffer for oob check failed\n");
+		return -ENOMEM;
+	}
+	/* 
+	 * if mode = 0, we scan for a total empty oob area, else we have
+	 * to take care of the cleanmarker in the first page of the block
+	*/
+	ret = jffs2_flash_read_oob(c, jeb->offset, len , &retlen, buf);
+	if (ret) {
+		D1(printk(KERN_WARNING "jffs2_check_oob_empty(): Read OOB failed %d for block at %08x\n", ret, jeb->offset));
+		goto out;
+	}
+	
+	if (retlen < len) {
+		D1(printk(KERN_WARNING "jffs2_check_oob_empty(): Read OOB return short read "
+			  "(%d bytes not %d) for block at %08x\n", retlen, len, jeb->offset));
+		ret = -EIO;
+		goto out;
+	}
+	
+	/* Special check for first two pages */
+	for (page = 0; page < 2; page += oob_size) {
+		/* Check for bad block marker */
+		if (buf[page+badblock_pos] != 0xff) {
+			D1(printk(KERN_WARNING "jffs2_check_oob_empty(): Bad or failed block at %08x\n",jeb->offset));
+			/* Return 2 for bad and 3 for failed block 
+			   bad goes to list_bad and failed to list_erase */
+			ret = (!page) ? 2 : 3;
+			goto out;
+		}
+		cnt = oob_size;
+		if (mode)
+			cnt -= fsdata_pos;
+		for(i = 0; i < cnt ; i+=sizeof(unsigned short)) {
+			unsigned short dat = *(unsigned short *)(&buf[page+i]);
+			if(dat != 0xffff) {
+				ret = 1; 
+				goto out;
+			}
+		}
+		/* only the first page can contain a cleanmarker !*/
+		mode = 0;
+	}	
+
+	/* we know, we are aligned :) */	
+	for (; page < len; page += sizeof(long)) {
+		unsigned long dat = *(unsigned long *)(&buf[page]);
+		if(dat != -1) {
+			ret = 1; 
+			goto out;
+		}
+	}
+
+out:
+	kfree(buf);	
+	
+	return ret;
+}
+
+int jffs2_check_nand_cleanmarker(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb)
+{
+	struct jffs2_unknown_node n;
+	unsigned char buf[32];
+	unsigned char *p;
+	int ret,i;
+	size_t retlen;
+	int	fsdata_pos,fsdata_len, oob_size, badblock_pos;
+
+	oob_size = c->mtd->oobsize;
+
+	switch(c->mtd->ecctype) {
+	case MTD_ECC_SW:	
+		fsdata_pos = (c->wbuf_pagesize == 256) ? NAND_JFFS2_OOB8_FSDAPOS : NAND_JFFS2_OOB16_FSDAPOS;
+		fsdata_len = (c->wbuf_pagesize == 256) ? NAND_JFFS2_OOB8_FSDALEN : NAND_JFFS2_OOB16_FSDALEN;
+		badblock_pos = NAND_JFFS2_OOB_BADBPOS;
+		break;
+	default:
+		D1(printk(KERN_WARNING "jffs2_write_nand_cleanmarker(): Invalid ECC type\n"));
+		return -EINVAL;
+	}	
+
+	/*
+	*	We read oob data from page 0 and 1 of the block.
+	*	page 0 contains cleanmarker and badblock info
+	*	page 2 contains failure count of this block
+	*/
+	ret = c->mtd->read_oob(c->mtd, jeb->offset, oob_size << 1 , &retlen, buf);
+	
+	if (ret) {
+		D1(printk(KERN_WARNING "jffs2_check_nand_cleanmarker(): Read OOB failed %d for block at %08x\n", ret, jeb->offset));
+		return ret;
+	}
+	if (retlen < (oob_size << 1) ) {
+		D1(printk(KERN_WARNING "jffs2_check_nand_cleanmarker(): Read OOB return short read (%d bytes not %d) for block at %08x\n", retlen, oob_size << 1 , jeb->offset));
+		return -EIO;
+	}
+
+	/* Check for bad block marker */
+	if (buf[badblock_pos] != 0xff) {
+		D1(printk(KERN_WARNING "jffs2_check_nand_cleanmarker(): Bad block at %08x\n",jeb->offset));
+		return 2;
+	}
+
+	/* Check for failure counter in the second page */
+	if (buf[badblock_pos+oob_size] != 0xff) {
+		D1(printk(KERN_WARNING "jffs2_check_nand_cleanmarker(): Block marked as failed at %08x, fail count:%d\n",jeb->offset,buf[badblock_pos+oob_size]));
+		return 3;
+	}
+
+	n.magic = JFFS2_MAGIC_BITMASK;
+	n.nodetype = JFFS2_NODETYPE_CLEANMARKER;
+	n.totlen = 8;
+	p = (unsigned char *) &n;
+	
+	for (i = 0; i < fsdata_len; i++) {
+		if (buf[fsdata_pos+i] != p[i]) {
+			D2(printk(KERN_WARNING "jffs2_check_nand_cleanmarker(): Cleanmarker node not detected in block at %08x\n", jeb->offset));
+			return 1;
+		}
+	}
+	
+	return 0;
+}
+
+int jffs2_write_nand_cleanmarker(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb)
+{
+	struct 	jffs2_unknown_node n;
+	int 	ret;
+	int	fsdata_pos,fsdata_len;
+	size_t 	retlen;
+
+	switch(c->mtd->ecctype) {
+	case MTD_ECC_SW:	
+		fsdata_pos = (c->wbuf_pagesize == 256) ? NAND_JFFS2_OOB8_FSDAPOS : NAND_JFFS2_OOB16_FSDAPOS;
+		fsdata_len = (c->wbuf_pagesize == 256) ? NAND_JFFS2_OOB8_FSDALEN : NAND_JFFS2_OOB16_FSDALEN;
+		break;
+	default:
+		D1(printk(KERN_WARNING "jffs2_write_nand_cleanmarker(): Invalid ECC type\n"));
+		return -EINVAL;
+	}	
+	
+	n.magic = JFFS2_MAGIC_BITMASK;
+	n.nodetype = JFFS2_NODETYPE_CLEANMARKER;
+	n.totlen = 8;
+
+	ret = jffs2_flash_write_oob(c, jeb->offset + fsdata_pos, fsdata_len, &retlen, (unsigned char *)&n);
+	
+	if (ret) {
+		D1(printk(KERN_WARNING "jffs2_write_nand_cleanmarker(): Write failed for block at %08x: error %d\n", jeb->offset, ret));
+		return ret;
+	}
+	if (retlen != fsdata_len) {
+		D1(printk(KERN_WARNING "jffs2_write_nand_cleanmarker(): Short write for block at %08x: %d not %d\n", jeb->offset, retlen, fsdata_len));
+		return ret;
+	}
+	return 0;
+}
+
+/* 
+ * We try to get the failure count of this block.
+ */
+int jffs2_nand_read_failcnt(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb) {
+
+	unsigned char buf[16];
+	int	ret;
+	size_t 	retlen;
+	int	oob_size, badblock_pos;
+
+	oob_size = c->mtd->oobsize;
+
+	switch(c->mtd->ecctype) {
+	case MTD_ECC_SW:	
+		badblock_pos = NAND_JFFS2_OOB_BADBPOS;
+		break;
+	default:
+		D1(printk(KERN_WARNING "jffs2_nand_read_failcnt(): Invalid ECC type\n"));
+		return -EINVAL;
+	}	
+	
+	ret = c->mtd->read_oob(c->mtd, jeb->offset + c->mtd->oobblock, oob_size , &retlen, buf);
+	
+	if (ret) {
+		D1(printk(KERN_WARNING "jffs2_nand_read_failcnt(): Read OOB failed %d for block at %08x\n", ret, jeb->offset));
+		return ret;
+	}
+
+	if (retlen < oob_size) {
+		D1(printk(KERN_WARNING "jffs2_nand_read_failcnt(): Read OOB return short read (%d bytes not %d) for block at %08x\n", retlen, oob_size, jeb->offset));
+		return -EIO;
+	}
+
+	jeb->bad_count =  buf[badblock_pos];	
+	return 0;
+}
+
+/* 
+ * On NAND we try to mark this block bad. We try to write how often
+ * the block was erased and mark it finaly bad, if the count
+ * is > MAX_ERASE_FAILURES. We read this information on mount !
+ * jeb->bad_count contains the count before this erase.
+ * Don't care about failures. This block remains on the erase-pending
+ * or badblock list as long as nobody manipulates the flash with
+ * a bootloader or something like that.
+ */
+
+int jffs2_write_nand_badblock(struct jffs2_sb_info *c, struct jffs2_eraseblock *jeb)
+{
+	unsigned char buf = 0x0;
+	int 	ret,pos;
+	size_t 	retlen;
+
+	switch(c->mtd->ecctype) {
+	case MTD_ECC_SW:	
+		pos = NAND_JFFS2_OOB_BADBPOS;
+		break;
+	default:
+		D1(printk(KERN_WARNING "jffs2_write_nand_badblock(): Invalid ECC type\n"));
+		return -EINVAL;
+	}	
+
+	/* if the count is < max, we try to write the counter to the 2nd page oob area */
+	if( ++jeb->bad_count < MAX_ERASE_FAILURES) {
+		buf = (unsigned char)jeb->bad_count;
+		pos += c->mtd->oobblock;
+	}
+	
+	ret = jffs2_flash_write_oob(c, jeb->offset + pos, 1, &retlen, &buf);
+	
+	if (ret) {
+		D1(printk(KERN_WARNING "jffs2_write_nand_badblock(): Write failed for block at %08x: error %d\n", jeb->offset, ret));
+		return ret;
+	}
+	if (retlen != 1) {
+		D1(printk(KERN_WARNING "jffs2_write_nand_badblock(): Short write for block at %08x: %d not 1\n", jeb->offset, retlen));
+		return ret;
+	}
+	return 0;
+}
+
diff -Nru a/fs/jffs2/write.c b/fs/jffs2/write.c
--- a/fs/jffs2/write.c	Fri Mar 15 17:51:03 2002
+++ b/fs/jffs2/write.c	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,60 +31,35 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: write.c,v 1.30 2001/12/30 16:01:11 dwmw2 Exp $
+ * $Id: write.c,v 1.52 2002/03/08 11:01:43 dwmw2 Exp $
  *
  */
 
 #include <linux/kernel.h>
 #include <linux/fs.h>
 #include <linux/crc32.h>
-#include <linux/jffs2.h>
+#include <linux/slab.h>
 #include <linux/mtd/mtd.h>
 #include "nodelist.h"
 
-/* jffs2_new_inode: allocate a new inode and inocache, add it to the hash,
-   fill in the raw_inode while you're at it. */
-struct inode *jffs2_new_inode (struct inode *dir_i, int mode, struct jffs2_raw_inode *ri)
+
+int jffs2_do_new_inode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, uint32_t mode, struct jffs2_raw_inode *ri)
 {
-	struct inode *inode;
-	struct super_block *sb = dir_i->i_sb;
 	struct jffs2_inode_cache *ic;
-	struct jffs2_sb_info *c;
-	struct jffs2_inode_info *f;
-
-	D1(printk(KERN_DEBUG "jffs2_new_inode(): dir_i %ld, mode 0x%x\n", dir_i->i_ino, mode));
-
-	c = JFFS2_SB_INFO(sb);
-	memset(ri, 0, sizeof(*ri));
 
 	ic = jffs2_alloc_inode_cache();
 	if (!ic) {
-		return ERR_PTR(-ENOMEM);
-	}
-	memset(ic, 0, sizeof(*ic));
-	
-	inode = new_inode(sb);
-	
-	if (!inode) {
-		jffs2_free_inode_cache(ic);
-		return ERR_PTR(-ENOMEM);
+		return -ENOMEM;
 	}
 
-	/* Alloc jffs2_inode_info when that's split in 2.5 */
+	memset(ic, 0, sizeof(*ic));
 
-	f = JFFS2_INODE_INFO(inode);
-	down(&f->sem);
-	f->highest_version = 0;
-	f->fraglist = NULL;
-	f->metadata = NULL;
-	f->dents = NULL;
-	f->flags = 0;
-	f->usercompr = 0;
+	init_MUTEX_LOCKED(&f->sem);
 	f->inocache = ic;
-	inode->i_nlink = f->inocache->nlink = 1;
+	f->inocache->nlink = 1;
 	f->inocache->nodes = (struct jffs2_raw_node_ref *)f->inocache;
-	f->inocache->ino = ri->ino = inode->i_ino = ++c->highest_ino;
-	D1(printk(KERN_DEBUG "jffs2_new_inode(): Assigned ino# %d\n", ri->ino));
+	f->inocache->ino = ri->ino =  ++c->highest_ino;
+	D1(printk(KERN_DEBUG "jffs2_do_new_inode(): Assigned ino# %d\n", ri->ino));
 	jffs2_add_ino_cache(c, f->inocache);
 
 	ri->magic = JFFS2_MAGIC_BITMASK;
@@ -93,65 +68,18 @@
 	ri->hdr_crc = crc32(0, ri, sizeof(struct jffs2_unknown_node)-4);
 	ri->mode = mode;
 	f->highest_version = ri->version = 1;
-	ri->uid = current->fsuid;
-	if (dir_i->i_mode & S_ISGID) {
-		ri->gid = dir_i->i_gid;
-		if (S_ISDIR(mode))
-			ri->mode |= S_ISGID;
-	} else {
-		ri->gid = current->fsgid;
-	}
-	inode->i_mode = ri->mode;
-	inode->i_gid = ri->gid;
-	inode->i_uid = ri->uid;
-	inode->i_atime = inode->i_ctime = inode->i_mtime = 
-		ri->atime = ri->mtime = ri->ctime = CURRENT_TIME;
-	inode->i_blksize = PAGE_SIZE;
-	inode->i_blocks = 0;
-	inode->i_size = 0;
-
-	insert_inode_hash(inode);
-
-	return inode;
-}
-
-/* This ought to be in core MTD code. All registered MTD devices without writev should have
-   this put in place. Bug the MTD maintainer */
-static int mtd_fake_writev(struct mtd_info *mtd, const struct iovec *vecs, unsigned long count, loff_t to, size_t *retlen)
-{
-	unsigned long i;
-	size_t totlen = 0, thislen;
-	int ret = 0;
-
-	for (i=0; i<count; i++) {
-		mtd->write(mtd, to, vecs[i].iov_len, &thislen, vecs[i].iov_base);
-		totlen += thislen;
-		if (ret || thislen != vecs[i].iov_len)
-			break;
-		to += vecs[i].iov_len;
-	}
-	if (retlen)
-		*retlen = totlen;
-	return ret;
-}
 
-
-static inline int mtd_writev(struct mtd_info *mtd, const struct iovec *vecs, unsigned long count, loff_t to, size_t *retlen)
-{
-	if (mtd->writev)
-		return mtd->writev(mtd,vecs,count,to,retlen);
-	else
-		return mtd_fake_writev(mtd, vecs, count, to, retlen);
+	return 0;
 }
 
-static void writecheck(struct mtd_info *mtd, __u32 ofs)
+static void writecheck(struct jffs2_sb_info *c, uint32_t ofs)
 {
 	unsigned char buf[16];
-	ssize_t retlen;
+	size_t retlen;
 	int ret, i;
 
-	ret = mtd->read(mtd, ofs, 16, &retlen, buf);
-	if (ret && retlen != 16) {
+	ret = jffs2_flash_read(c, ofs, 16, &retlen, buf);
+	if (ret || (retlen != 16)) {
 		D1(printk(KERN_DEBUG "read failed or short in writecheck(). ret %d, retlen %d\n", ret, retlen));
 		return;
 	}
@@ -169,22 +97,20 @@
 	}
 }
 
-	
-	
+
 
 /* jffs2_write_dnode - given a raw_inode, allocate a full_dnode for it, 
    write it to the flash, link it into the existing inode/fragment list */
 
-struct jffs2_full_dnode *jffs2_write_dnode(struct inode *inode, struct jffs2_raw_inode *ri, const unsigned char *data, __u32 datalen, __u32 flash_ofs,  __u32 *writelen)
+struct jffs2_full_dnode *jffs2_write_dnode(struct jffs2_sb_info *c, struct jffs2_inode_info *f, struct jffs2_raw_inode *ri, const unsigned char *data, uint32_t datalen, uint32_t flash_ofs,  uint32_t *writelen)
 
 {
-	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_raw_node_ref *raw;
 	struct jffs2_full_dnode *fn;
-	ssize_t retlen;
+	size_t retlen;
 	struct iovec vecs[2];
 	int ret;
+	unsigned long cnt = 2;
 
 	D1(if(ri->hdr_crc != crc32(0, ri, sizeof(struct jffs2_unknown_node)-4)) {
 		printk(KERN_CRIT "Eep. CRC not correct in jffs2_write_dnode()\n");
@@ -196,7 +122,7 @@
 	vecs[1].iov_base = (unsigned char *)data;
 	vecs[1].iov_len = datalen;
 
-	writecheck(c->mtd, flash_ofs);
+	writecheck(c, flash_ofs);
 
 	if (ri->totlen != sizeof(*ri) + datalen) {
 		printk(KERN_WARNING "jffs2_write_dnode: ri->totlen (0x%08x) != sizeof(*ri) (0x%08x) + datalen (0x%08x)\n", ri->totlen, sizeof(*ri), datalen);
@@ -219,7 +145,12 @@
 	fn->frags = 0;
 	fn->raw = raw;
 
-	ret = mtd_writev(c->mtd, vecs, 2, flash_ofs, &retlen);
+	/* check number of valid vecs */
+	if (!datalen || !data)
+		cnt = 1;
+
+	ret = jffs2_flash_writev(c, vecs, cnt, flash_ofs, &retlen);
+		
 	if (ret || (retlen != sizeof(*ri) + datalen)) {
 		printk(KERN_NOTICE "Write of %d bytes at 0x%08x failed. returned %d, retlen %d\n", 
 		       sizeof(*ri)+datalen, flash_ofs, ret, retlen);
@@ -261,18 +192,16 @@
 	return fn;
 }
 
-struct jffs2_full_dirent *jffs2_write_dirent(struct inode *inode, struct jffs2_raw_dirent *rd, const unsigned char *name, __u32 namelen, __u32 flash_ofs,  __u32 *writelen)
+struct jffs2_full_dirent *jffs2_write_dirent(struct jffs2_sb_info *c, struct jffs2_inode_info *f, struct jffs2_raw_dirent *rd, const unsigned char *name, uint32_t namelen, uint32_t flash_ofs,  uint32_t *writelen)
 {
-	struct jffs2_sb_info *c = JFFS2_SB_INFO(inode->i_sb);
-	struct jffs2_inode_info *f = JFFS2_INODE_INFO(inode);
 	struct jffs2_raw_node_ref *raw;
 	struct jffs2_full_dirent *fd;
-	ssize_t retlen;
+	size_t retlen;
 	struct iovec vecs[2];
 	int ret;
 
 	D1(printk(KERN_DEBUG "jffs2_write_dirent(ino #%u, name at *0x%p \"%s\"->ino #%u, name_crc 0x%08x)\n", rd->pino, name, name, rd->ino, rd->name_crc));
-	writecheck(c->mtd, flash_ofs);
+	writecheck(c, flash_ofs);
 
 	D1(if(rd->hdr_crc != crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)) {
 		printk(KERN_CRIT "Eep. CRC not correct in jffs2_write_dirent()\n");
@@ -309,18 +238,18 @@
 	fd->name[namelen]=0;
 	fd->raw = raw;
 
-	ret = mtd_writev(c->mtd, vecs, 2, flash_ofs, &retlen);
-		if (ret || (retlen != sizeof(*rd) + namelen)) {
-			printk(KERN_NOTICE "Write of %d bytes at 0x%08x failed. returned %d, retlen %d\n", 
+	ret = jffs2_flash_writev(c, vecs, 2, flash_ofs, &retlen);
+	if (ret || (retlen != sizeof(*rd) + namelen)) {
+		printk(KERN_NOTICE "Write of %d bytes at 0x%08x failed. returned %d, retlen %d\n", 
 			       sizeof(*rd)+namelen, flash_ofs, ret, retlen);
 		/* Mark the space as dirtied */
-			if (retlen) {
-				jffs2_add_physical_node_ref(c, raw, sizeof(*rd)+namelen, 1);
-				jffs2_mark_node_obsolete(c, raw);
-			} else {
-				printk(KERN_NOTICE "Not marking the space at 0x%08x as dirty because the flash driver returned retlen zero\n", raw->flash_offset);
-				jffs2_free_raw_node_ref(raw);
-			}
+		if (retlen) {
+			jffs2_add_physical_node_ref(c, raw, sizeof(*rd)+namelen, 1);
+			jffs2_mark_node_obsolete(c, raw);
+		} else {
+			printk(KERN_NOTICE "Not marking the space at 0x%08x as dirty because the flash driver returned retlen zero\n", raw->flash_offset);
+			jffs2_free_raw_node_ref(raw);
+		}
 
 		/* Release the full_dnode which is now useless, and return */
 		jffs2_free_full_dirent(fd);
@@ -335,4 +264,344 @@
 
 	f->inocache->nodes = raw;
 	return fd;
+}
+
+/* The OS-specific code fills in the metadata in the jffs2_raw_inode for us, so that
+   we don't have to go digging in struct inode or its equivalent. It should set:
+   mode, uid, gid, (starting)isize, atime, ctime, mtime */
+int jffs2_write_inode_range(struct jffs2_sb_info *c, struct jffs2_inode_info *f,
+			    struct jffs2_raw_inode *ri, unsigned char *buf, 
+			    uint32_t offset, uint32_t writelen, uint32_t *retlen)
+{
+	int ret = 0;
+	uint32_t writtenlen = 0;
+
+       	D1(printk(KERN_DEBUG "jffs2_write_inode_range(): Ino #%u, ofs 0x%x, len 0x%x\n",
+		  f->inocache->ino, offset, writelen));
+		
+	while(writelen) {
+		struct jffs2_full_dnode *fn;
+		unsigned char *comprbuf = NULL;
+		unsigned char comprtype = JFFS2_COMPR_NONE;
+		uint32_t phys_ofs, alloclen;
+		uint32_t datalen, cdatalen;
+
+		D2(printk(KERN_DEBUG "jffs2_commit_write() loop: 0x%x to write to 0x%x\n", writelen, offset));
+
+		ret = jffs2_reserve_space(c, sizeof(*ri) + JFFS2_MIN_DATA_LEN, &phys_ofs, &alloclen, ALLOC_NORMAL);
+		if (ret) {
+			D1(printk(KERN_DEBUG "jffs2_reserve_space returned %d\n", ret));
+			break;
+		}
+		down(&f->sem);
+		datalen = writelen;
+		cdatalen = min(alloclen - sizeof(*ri), writelen);
+
+		comprbuf = kmalloc(cdatalen, GFP_KERNEL);
+		if (comprbuf) {
+			comprtype = jffs2_compress(buf, comprbuf, &datalen, &cdatalen);
+		}
+		if (comprtype == JFFS2_COMPR_NONE) {
+			/* Either compression failed, or the allocation of comprbuf failed */
+			if (comprbuf)
+				kfree(comprbuf);
+			comprbuf = buf;
+			datalen = cdatalen;
+		}
+		/* Now comprbuf points to the data to be written, be it compressed or not.
+		   comprtype holds the compression type, and comprtype == JFFS2_COMPR_NONE means
+		   that the comprbuf doesn't need to be kfree()d. 
+		*/
+
+		ri->magic = JFFS2_MAGIC_BITMASK;
+		ri->nodetype = JFFS2_NODETYPE_INODE;
+		ri->totlen = sizeof(*ri) + cdatalen;
+		ri->hdr_crc = crc32(0, ri, sizeof(struct jffs2_unknown_node)-4);
+
+		ri->ino = f->inocache->ino;
+		ri->version = ++f->highest_version;
+		ri->isize = max(ri->isize, offset + datalen);
+		ri->offset = offset;
+		ri->csize = cdatalen;
+		ri->dsize = datalen;
+		ri->compr = comprtype;
+		ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
+		ri->data_crc = crc32(0, comprbuf, cdatalen);
+
+		fn = jffs2_write_dnode(c, f, ri, comprbuf, cdatalen, phys_ofs, NULL);
+
+		if (comprtype != JFFS2_COMPR_NONE)
+			kfree(comprbuf);
+
+		if (IS_ERR(fn)) {
+			ret = PTR_ERR(fn);
+			up(&f->sem);
+			jffs2_complete_reservation(c);
+			break;
+		}
+		ret = jffs2_add_full_dnode_to_inode(c, f, fn);
+		if (f->metadata) {
+			jffs2_mark_node_obsolete(c, f->metadata->raw);
+			jffs2_free_full_dnode(f->metadata);
+			f->metadata = NULL;
+		}
+		if (ret) {
+			/* Eep */
+			D1(printk(KERN_DEBUG "Eep. add_full_dnode_to_inode() failed in commit_write, returned %d\n", ret));
+			jffs2_mark_node_obsolete(c, fn->raw);
+			jffs2_free_full_dnode(fn);
+
+			up(&f->sem);
+			jffs2_complete_reservation(c);
+			break;
+		}
+		up(&f->sem);
+		jffs2_complete_reservation(c);
+		if (!datalen) {
+			printk(KERN_WARNING "Eep. We didn't actually write any data in jffs2_write_inode_range()\n");
+			ret = -EIO;
+			break;
+		}
+		D1(printk(KERN_DEBUG "increasing writtenlen by %d\n", datalen));
+		writtenlen += datalen;
+		offset += datalen;
+		writelen -= datalen;
+		buf += datalen;
+	}
+	*retlen = writtenlen;
+	return ret;
+}
+
+int jffs2_do_create(struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, struct jffs2_inode_info *f, struct jffs2_raw_inode *ri, const char *name, int namelen)
+{
+	struct jffs2_raw_dirent *rd;
+	struct jffs2_full_dnode *fn;
+	struct jffs2_full_dirent *fd;
+	uint32_t alloclen, phys_ofs;
+	uint32_t writtenlen;
+	int ret;
+
+	/* Try to reserve enough space for both node and dirent. 
+	 * Just the node will do for now, though 
+	 */
+	ret = jffs2_reserve_space(c, sizeof(*ri), &phys_ofs, &alloclen, ALLOC_NORMAL);
+	D1(printk(KERN_DEBUG "jffs2_do_create(): reserved 0x%x bytes\n", alloclen));
+	if (ret)
+		return ret;
+
+	ri->data_crc = 0;
+	ri->node_crc = crc32(0, ri, sizeof(*ri)-8);
+
+	fn = jffs2_write_dnode(c, f, ri, NULL, 0, phys_ofs, &writtenlen);
+
+	D1(printk(KERN_DEBUG "jffs2_do_create created file with mode 0x%x\n", ri->mode));
+
+	if (IS_ERR(fn)) {
+		D1(printk(KERN_DEBUG "jffs2_write_dnode() failed\n"));
+		/* Eeek. Wave bye bye */
+		up(&f->sem);
+		jffs2_complete_reservation(c);
+		return PTR_ERR(fn);
+	}
+	/* No data here. Only a metadata node, which will be 
+	   obsoleted by the first data write
+	*/
+	f->metadata = fn;
+
+	/* Work out where to put the dirent node now. */
+	writtenlen = PAD(writtenlen);
+	phys_ofs += writtenlen;
+	alloclen -= writtenlen;
+	up(&f->sem);
+
+	if (alloclen < sizeof(*rd)+namelen) {
+		/* Not enough space left in this chunk. Get some more */
+		jffs2_complete_reservation(c);
+		ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &phys_ofs, &alloclen, ALLOC_NORMAL);
+		
+		if (ret) {
+			/* Eep. */
+			D1(printk(KERN_DEBUG "jffs2_reserve_space() for dirent failed\n"));
+			return ret;
+		}
+	}
+
+	rd = jffs2_alloc_raw_dirent();
+	if (!rd) {
+		/* Argh. Now we treat it like a normal delete */
+		jffs2_complete_reservation(c);
+		return -ENOMEM;
+	}
+
+	down(&dir_f->sem);
+
+	rd->magic = JFFS2_MAGIC_BITMASK;
+	rd->nodetype = JFFS2_NODETYPE_DIRENT;
+	rd->totlen = sizeof(*rd) + namelen;
+	rd->hdr_crc = crc32(0, rd, sizeof(struct jffs2_unknown_node)-4);
+
+	rd->pino = dir_f->inocache->ino;
+	rd->version = ++dir_f->highest_version;
+	rd->ino = ri->ino;
+	rd->mctime = ri->ctime;
+	rd->nsize = namelen;
+	rd->type = DT_REG;
+	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
+	rd->name_crc = crc32(0, name, namelen);
+
+	fd = jffs2_write_dirent(c, dir_f, rd, name, namelen, phys_ofs, &writtenlen);
+
+	jffs2_free_raw_dirent(rd);
+	
+	if (IS_ERR(fd)) {
+		/* dirent failed to write. Delete the inode normally 
+		   as if it were the final unlink() */
+		jffs2_complete_reservation(c);
+		up(&dir_f->sem);
+		return PTR_ERR(fd);
+	}
+
+	/* Link the fd into the inode's list, obsoleting an old
+	   one if necessary. */
+	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
+
+	jffs2_complete_reservation(c);
+	up(&dir_f->sem);
+
+	return 0;
+}
+
+
+int jffs2_do_unlink(struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, const char *name, int namelen, struct jffs2_inode_info *dead_f)
+{
+	struct jffs2_raw_dirent *rd;
+	struct jffs2_full_dirent *fd;
+	uint32_t alloclen, phys_ofs;
+	int ret;
+
+	rd = jffs2_alloc_raw_dirent();
+	if (!rd)
+		return -ENOMEM;
+
+	ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &phys_ofs, &alloclen, ALLOC_DELETION);
+	if (ret) {
+		jffs2_free_raw_dirent(rd);
+		return ret;
+	}
+
+	down(&dir_f->sem);
+
+	/* Build a deletion node */
+	rd->magic = JFFS2_MAGIC_BITMASK;
+	rd->nodetype = JFFS2_NODETYPE_DIRENT;
+	rd->totlen = sizeof(*rd) + namelen;
+	rd->hdr_crc = crc32(0, rd, sizeof(struct jffs2_unknown_node)-4);
+
+	rd->pino = dir_f->inocache->ino;
+	rd->version = ++dir_f->highest_version;
+	rd->ino = 0;
+	rd->mctime = CURRENT_TIME;
+	rd->nsize = namelen;
+	rd->type = DT_UNKNOWN;
+	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
+	rd->name_crc = crc32(0, name, namelen);
+
+	fd = jffs2_write_dirent(c, dir_f, rd, name, namelen, phys_ofs, NULL);
+	
+	jffs2_free_raw_dirent(rd);
+
+	if (IS_ERR(fd)) {
+		jffs2_complete_reservation(c);
+		up(&dir_f->sem);
+		return PTR_ERR(fd);
+	}
+
+	/* File it. This will mark the old one obsolete. */
+	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
+
+	jffs2_complete_reservation(c);
+	up(&dir_f->sem);
+	
+	if (dead_f) { /* Null if this was a rename not a real unlink */
+
+		down(&dead_f->sem);
+
+		while (dead_f->dents) {
+			/* There can be only deleted ones */
+			fd = dead_f->dents;
+			
+			dead_f->dents = fd->next;
+			
+			if (fd->ino) {
+				printk(KERN_WARNING "Deleting inode #%u with active dentry \"%s\"->ino #%u\n",
+				       dead_f->inocache->ino, fd->name, fd->ino);
+			} else {
+				D1(printk(KERN_DEBUG "Removing deletion dirent for \"%s\" from dir ino #%u\n", fd->name, dead_f->inocache->ino));
+			}
+			jffs2_mark_node_obsolete(c, fd->raw);
+			jffs2_free_full_dirent(fd);
+		}
+
+		dead_f->inocache->nlink--;
+		/* NB: Caller must set inode nlink if appropriate */
+		up(&dead_f->sem);
+	}
+
+	return 0;
+}
+
+
+int jffs2_do_link (struct jffs2_sb_info *c, struct jffs2_inode_info *dir_f, uint32_t ino, uint8_t type, const char *name, int namelen)
+{
+	struct jffs2_raw_dirent *rd;
+	struct jffs2_full_dirent *fd;
+	uint32_t alloclen, phys_ofs;
+	int ret;
+
+	rd = jffs2_alloc_raw_dirent();
+	if (!rd)
+		return -ENOMEM;
+
+	ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &phys_ofs, &alloclen, ALLOC_NORMAL);
+	if (ret) {
+		jffs2_free_raw_dirent(rd);
+		return ret;
+	}
+	
+	down(&dir_f->sem);
+
+	/* Build a deletion node */
+	rd->magic = JFFS2_MAGIC_BITMASK;
+	rd->nodetype = JFFS2_NODETYPE_DIRENT;
+	rd->totlen = sizeof(*rd) + namelen;
+	rd->hdr_crc = crc32(0, rd, sizeof(struct jffs2_unknown_node)-4);
+
+	rd->pino = dir_f->inocache->ino;
+	rd->version = ++dir_f->highest_version;
+	rd->ino = ino;
+	rd->mctime = CURRENT_TIME;
+	rd->nsize = namelen;
+
+	rd->type = type;
+
+	rd->node_crc = crc32(0, rd, sizeof(*rd)-8);
+	rd->name_crc = crc32(0, name, namelen);
+
+	fd = jffs2_write_dirent(c, dir_f, rd, name, namelen, phys_ofs, NULL);
+	
+	jffs2_free_raw_dirent(rd);
+
+	if (IS_ERR(fd)) {
+		jffs2_complete_reservation(c);
+		up(&dir_f->sem);
+		return PTR_ERR(fd);
+	}
+
+	/* File it. This will mark the old one obsolete. */
+	jffs2_add_fd_to_list(c, fd, &dir_f->dents);
+
+	jffs2_complete_reservation(c);
+	up(&dir_f->sem);
+
+	return 0;
 }
diff -Nru a/fs/jffs2/writev.c b/fs/jffs2/writev.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/jffs2/writev.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,74 @@
+/*
+ * JFFS2 -- Journalling Flash File System, Version 2.
+ *
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
+ *
+ * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
+ *
+ * The original JFFS, from which the design for JFFS2 was derived,
+ * was designed and implemented by Axis Communications AB.
+ *
+ * The contents of this file are subject to the Red Hat eCos Public
+ * License Version 1.1 (the "Licence"); you may not use this file
+ * except in compliance with the Licence.  You may obtain a copy of
+ * the Licence at http://www.redhat.com/
+ *
+ * Software distributed under the Licence is distributed on an "AS IS"
+ * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied.
+ * See the Licence for the specific language governing rights and
+ * limitations under the Licence.
+ *
+ * The Original Code is JFFS2 - Journalling Flash File System, version 2
+ *
+ * Alternatively, the contents of this file may be used under the
+ * terms of the GNU General Public License version 2 (the "GPL"), in
+ * which case the provisions of the GPL are applicable instead of the
+ * above.  If you wish to allow the use of your version of this file
+ * only under the terms of the GPL and not to allow others to use your
+ * version of this file under the RHEPL, indicate your decision by
+ * deleting the provisions above and replace them with the notice and
+ * other provisions required by the GPL.  If you do not delete the
+ * provisions above, a recipient may use your version of this file
+ * under either the RHEPL or the GPL.
+ *
+ * $Id: writev.c,v 1.1 2002/03/08 11:27:59 dwmw2 Exp $
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/mtd/mtd.h>
+#include "nodelist.h"
+
+/* This ought to be in core MTD code. All registered MTD devices
+   without writev should have this put in place. Bug the MTD
+   maintainer */
+static inline int mtd_fake_writev(struct mtd_info *mtd, const struct iovec *vecs,
+				  unsigned long count, loff_t to, size_t *retlen)
+{
+	unsigned long i;
+	size_t totlen = 0, thislen;
+	int ret = 0;
+
+	for (i=0; i<count; i++) {
+		if (!vecs[i].iov_len)
+			continue;
+		mtd->write(mtd, to, vecs[i].iov_len, &thislen, vecs[i].iov_base);
+		totlen += thislen;
+		if (ret || thislen != vecs[i].iov_len)
+			break;
+		to += vecs[i].iov_len;
+	}
+	if (retlen)
+		*retlen = totlen;
+	return ret;
+}
+
+int jffs2_flash_direct_writev(struct jffs2_sb_info *c, const struct iovec *vecs,
+			      unsigned long count, loff_t to, size_t *retlen)
+{
+	if (c->mtd->writev)
+		return c->mtd->writev(c->mtd, vecs, count, to, retlen);
+	else
+		return mtd_fake_writev(c->mtd, vecs, count, to, retlen);
+}
+
diff -Nru a/fs/jfs/super.c b/fs/jfs/super.c
--- a/fs/jfs/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/jfs/super.c	Fri Mar 15 17:51:03 2002
@@ -364,6 +364,7 @@
 	owner:		THIS_MODULE,
 	name:		"jfs",
 	get_sb:		jfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/libfs.c b/fs/libfs.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/libfs.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,112 @@
+/*
+ *	fs/libfs.c
+ *	Library for filesystems writers.
+ */
+
+#include <linux/pagemap.h>
+
+int simple_statfs(struct super_block *sb, struct statfs *buf)
+{
+	buf->f_type = sb->s_magic;
+	buf->f_bsize = PAGE_CACHE_SIZE;
+	buf->f_namelen = NAME_MAX;
+	return 0;
+}
+
+/*
+ * Lookup the data. This is trivial - if the dentry didn't already
+ * exist, we know it is negative.
+ */
+
+struct dentry *simple_lookup(struct inode *dir, struct dentry *dentry)
+{
+	d_add(dentry, NULL);
+	return NULL;
+}
+
+int simple_sync_file(struct file * file, struct dentry *dentry, int datasync)
+{
+	return 0;
+}
+
+/*
+ * Directory is locked and all positive dentries in it are safe, since
+ * for ramfs-type trees they can't go away without unlink() or rmdir(),
+ * both impossible due to the lock on directory.
+ */
+
+int dcache_readdir(struct file * filp, void * dirent, filldir_t filldir)
+{
+	int i;
+	struct dentry *dentry = filp->f_dentry;
+
+	i = filp->f_pos;
+	switch (i) {
+		case 0:
+			if (filldir(dirent, ".", 1, i, dentry->d_inode->i_ino, DT_DIR) < 0)
+				break;
+			i++;
+			filp->f_pos++;
+			/* fallthrough */
+		case 1:
+			if (filldir(dirent, "..", 2, i, parent_ino(dentry), DT_DIR) < 0)
+				break;
+			i++;
+			filp->f_pos++;
+			/* fallthrough */
+		default: {
+			struct list_head *list;
+			int j = i-2;
+
+			spin_lock(&dcache_lock);
+			list = dentry->d_subdirs.next;
+
+			for (;;) {
+				if (list == &dentry->d_subdirs) {
+					spin_unlock(&dcache_lock);
+					return 0;
+				}
+				if (!j)
+					break;
+				j--;
+				list = list->next;
+			}
+
+			while(1) {
+				struct dentry *de = list_entry(list, struct dentry, d_child);
+
+				/*
+				 * See comment on top of function on why we
+				 * can just drop the lock here..
+				 */
+				if (!list_empty(&de->d_hash) && de->d_inode) {
+					spin_unlock(&dcache_lock);
+					if (filldir(dirent, de->d_name.name, de->d_name.len, filp->f_pos, de->d_inode->i_ino, DT_UNKNOWN) < 0)
+						break;
+					spin_lock(&dcache_lock);
+				}
+				filp->f_pos++;
+				list = list->next;
+				if (list != &dentry->d_subdirs)
+					continue;
+				spin_unlock(&dcache_lock);
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+ssize_t generic_read_dir(struct file *filp, char *buf, size_t siz, loff_t *ppos)
+{
+	return -EISDIR;
+}
+
+struct file_operations simple_dir_operations = {
+	read:		generic_read_dir,
+	readdir:	dcache_readdir,
+};
+
+struct inode_operations simple_dir_inode_operations = {
+	lookup:		simple_lookup,
+};
diff -Nru a/fs/lockd/svc4proc.c b/fs/lockd/svc4proc.c
--- a/fs/lockd/svc4proc.c	Fri Mar 15 17:51:02 2002
+++ b/fs/lockd/svc4proc.c	Fri Mar 15 17:51:02 2002
@@ -447,11 +447,13 @@
 	if (nlmsvc_ops != NULL) {
 		struct svc_client	*clnt;
 		saddr.sin_addr.s_addr = argp->addr;
+		nlmsvc_ops->exp_readlock();
 		if ((clnt = nlmsvc_ops->exp_getclient(&saddr)) != NULL 
 		 && (host = nlm_lookup_host(clnt, &saddr, 0, 0)) != NULL) {
 			nlmsvc_free_host_resources(host);
 		}
 		nlm_release_host(host);
+		nlmsvc_ops->exp_unlock();
 	}
 
 	return rpc_success;
diff -Nru a/fs/lockd/svcproc.c b/fs/lockd/svcproc.c
--- a/fs/lockd/svcproc.c	Fri Mar 15 17:51:03 2002
+++ b/fs/lockd/svcproc.c	Fri Mar 15 17:51:03 2002
@@ -475,11 +475,13 @@
 	if (nlmsvc_ops != NULL) {
 		struct svc_client	*clnt;
 		saddr.sin_addr.s_addr = argp->addr;	
+		nlmsvc_ops->exp_readlock();
 		if ((clnt = nlmsvc_ops->exp_getclient(&saddr)) != NULL 
 		 && (host = nlm_lookup_host(clnt, &saddr, 0, 0)) != NULL) {
 			nlmsvc_free_host_resources(host);
 		}
 		nlm_release_host(host);
+		nlmsvc_ops->exp_unlock();
 	}
 
 	return rpc_success;
diff -Nru a/fs/minix/bitmap.c b/fs/minix/bitmap.c
--- a/fs/minix/bitmap.c	Fri Mar 15 17:51:02 2002
+++ b/fs/minix/bitmap.c	Fri Mar 15 17:51:02 2002
@@ -52,6 +52,7 @@
 void minix_free_block(struct inode * inode, int block)
 {
 	struct super_block * sb = inode->i_sb;
+	struct minix_sb_info * sbi = minix_sb(sb);
 	struct buffer_head * bh;
 	unsigned int bit,zone;
 
@@ -59,19 +60,19 @@
 		printk("trying to free block on nonexistent device\n");
 		return;
 	}
-	if (block < sb->u.minix_sb.s_firstdatazone ||
-	    block >= sb->u.minix_sb.s_nzones) {
+	if (block < sbi->s_firstdatazone ||
+	    block >= sbi->s_nzones) {
 		printk("trying to free block not in datazone\n");
 		return;
 	}
-	zone = block - sb->u.minix_sb.s_firstdatazone + 1;
+	zone = block - sbi->s_firstdatazone + 1;
 	bit = zone & 8191;
 	zone >>= 13;
-	if (zone >= sb->u.minix_sb.s_zmap_blocks) {
+	if (zone >= sbi->s_zmap_blocks) {
 		printk("minix_free_block: nonexistent bitmap buffer\n");
 		return;
 	}
-	bh = sb->u.minix_sb.s_zmap[zone];
+	bh = sbi->s_zmap[zone];
 	if (!minix_test_and_clear_bit(bit,bh->b_data))
 		printk("free_block (%s:%d): bit already cleared\n",
 		       sb->s_id, block);
@@ -82,6 +83,7 @@
 int minix_new_block(struct inode * inode)
 {
 	struct super_block * sb = inode->i_sb;
+	struct minix_sb_info * sbi = minix_sb(sb);
 	struct buffer_head * bh;
 	int i,j;
 
@@ -92,8 +94,8 @@
 repeat:
 	j = 8192;
 	bh = NULL;
-	for (i = 0; i < sb->u.minix_sb.s_zmap_blocks; i++) {
-		bh = sb->u.minix_sb.s_zmap[i];
+	for (i = 0; i < sbi->s_zmap_blocks; i++) {
+		bh = sbi->s_zmap[i];
 		if ((j = minix_find_first_zero_bit(bh->b_data, 8192)) < 8192)
 			break;
 	}
@@ -104,25 +106,26 @@
 		goto repeat;
 	}
 	mark_buffer_dirty(bh);
-	j += i*8192 + sb->u.minix_sb.s_firstdatazone-1;
-	if (j < sb->u.minix_sb.s_firstdatazone ||
-	    j >= sb->u.minix_sb.s_nzones)
+	j += i*8192 + sbi->s_firstdatazone-1;
+	if (j < sbi->s_firstdatazone ||
+	    j >= sbi->s_nzones)
 		return 0;
 	return j;
 }
 
 unsigned long minix_count_free_blocks(struct super_block *sb)
 {
-	return (count_free(sb->u.minix_sb.s_zmap, sb->u.minix_sb.s_zmap_blocks,
-		sb->u.minix_sb.s_nzones - sb->u.minix_sb.s_firstdatazone + 1)
-		<< sb->u.minix_sb.s_log_zone_size);
+	struct minix_sb_info *sbi = minix_sb(sb);
+	return (count_free(sbi->s_zmap, sbi->s_zmap_blocks,
+		sbi->s_nzones - sbi->s_firstdatazone + 1)
+		<< sbi->s_log_zone_size);
 }
 
 struct minix_inode *
 minix_V1_raw_inode(struct super_block *sb, ino_t ino, struct buffer_head **bh)
 {
 	int block;
-	struct minix_sb_info *sbi = &sb->u.minix_sb;
+	struct minix_sb_info *sbi = minix_sb(sb);
 	struct minix_inode *p;
 
 	if (!ino || ino > sbi->s_ninodes) {
@@ -146,7 +149,7 @@
 minix_V2_raw_inode(struct super_block *sb, ino_t ino, struct buffer_head **bh)
 {
 	int block;
-	struct minix_sb_info *sbi = &sb->u.minix_sb;
+	struct minix_sb_info *sbi = minix_sb(sb);
 	struct minix2_inode *p;
 
 	*bh = NULL;
@@ -198,17 +201,17 @@
 	struct buffer_head * bh;
 	unsigned long ino;
 
-	if (inode->i_ino < 1 || inode->i_ino > inode->i_sb->u.minix_sb.s_ninodes) {
+	if (inode->i_ino < 1 || inode->i_ino > minix_sb(inode->i_sb)->s_ninodes) {
 		printk("free_inode: inode 0 or nonexistent inode\n");
 		return;
 	}
 	ino = inode->i_ino;
-	if ((ino >> 13) >= inode->i_sb->u.minix_sb.s_imap_blocks) {
+	if ((ino >> 13) >= minix_sb(inode->i_sb)->s_imap_blocks) {
 		printk("free_inode: nonexistent imap in superblock\n");
 		return;
 	}
 
-	bh = inode->i_sb->u.minix_sb.s_imap[ino >> 13];
+	bh = minix_sb(inode->i_sb)->s_imap[ino >> 13];
 	minix_clear_inode(inode);
 	clear_inode(inode);
 	if (!minix_test_and_clear_bit(ino & 8191, bh->b_data))
@@ -233,8 +236,8 @@
 	bh = NULL;
 	*error = -ENOSPC;
 	lock_super(sb);
-	for (i = 0; i < sb->u.minix_sb.s_imap_blocks; i++) {
-		bh = inode->i_sb->u.minix_sb.s_imap[i];
+	for (i = 0; i < minix_sb(sb)->s_imap_blocks; i++) {
+		bh = minix_sb(inode->i_sb)->s_imap[i];
 		if ((j = minix_find_first_zero_bit(bh->b_data, 8192)) < 8192)
 			break;
 	}
@@ -251,7 +254,7 @@
 	}
 	mark_buffer_dirty(bh);
 	j += i*8192;
-	if (!j || j > inode->i_sb->u.minix_sb.s_ninodes) {
+	if (!j || j > minix_sb(inode->i_sb)->s_ninodes) {
 		iput(inode);
 		unlock_super(sb);
 		return NULL;
@@ -272,6 +275,6 @@
 
 unsigned long minix_count_free_inodes(struct super_block *sb)
 {
-	return count_free(sb->u.minix_sb.s_imap, sb->u.minix_sb.s_imap_blocks,
-		sb->u.minix_sb.s_ninodes + 1);
+	return count_free(minix_sb(sb)->s_imap, minix_sb(sb)->s_imap_blocks,
+		minix_sb(sb)->s_ninodes + 1);
 }
diff -Nru a/fs/minix/dir.c b/fs/minix/dir.c
--- a/fs/minix/dir.c	Fri Mar 15 17:51:02 2002
+++ b/fs/minix/dir.c	Fri Mar 15 17:51:02 2002
@@ -77,7 +77,7 @@
 	unsigned offset = pos & ~PAGE_CACHE_MASK;
 	unsigned long n = pos >> PAGE_CACHE_SHIFT;
 	unsigned long npages = dir_pages(inode);
-	struct minix_sb_info *sbi = &sb->u.minix_sb;
+	struct minix_sb_info *sbi = minix_sb(sb);
 	unsigned chunk_size = sbi->s_dirsize;
 
 	pos = (pos + chunk_size-1) & ~(chunk_size-1);
@@ -140,7 +140,7 @@
 	int namelen = dentry->d_name.len;
 	struct inode * dir = dentry->d_parent->d_inode;
 	struct super_block * sb = dir->i_sb;
-	struct minix_sb_info * sbi = &sb->u.minix_sb;
+	struct minix_sb_info * sbi = minix_sb(sb);
 	unsigned long n;
 	unsigned long npages = dir_pages(dir);
 	struct page *page = NULL;
@@ -178,7 +178,7 @@
 	const char * name = dentry->d_name.name;
 	int namelen = dentry->d_name.len;
 	struct super_block * sb = dir->i_sb;
-	struct minix_sb_info * sbi = &sb->u.minix_sb;
+	struct minix_sb_info * sbi = minix_sb(sb);
 	struct page *page = NULL;
 	struct minix_dir_entry * de;
 	unsigned long npages = dir_pages(dir);
@@ -236,7 +236,7 @@
 	struct inode *inode = (struct inode*)mapping->host;
 	char *kaddr = (char*)page_address(page);
 	unsigned from = (char*)de - kaddr;
-	unsigned to = from + inode->i_sb->u.minix_sb.s_dirsize;
+	unsigned to = from + minix_sb(inode->i_sb)->s_dirsize;
 	int err;
 
 	lock_page(page);
@@ -256,7 +256,7 @@
 {
 	struct address_space *mapping = inode->i_mapping;
 	struct page *page = grab_cache_page(mapping, 0);
-	struct minix_sb_info * sbi = &inode->i_sb->u.minix_sb;
+	struct minix_sb_info * sbi = minix_sb(inode->i_sb);
 	struct minix_dir_entry * de;
 	char *base;
 	int err;
@@ -291,7 +291,7 @@
 {
 	struct page *page = NULL;
 	unsigned long i, npages = dir_pages(inode);
-	struct minix_sb_info *sbi = &inode->i_sb->u.minix_sb;
+	struct minix_sb_info *sbi = minix_sb(inode->i_sb);
 
 	for (i = 0; i < npages; i++) {
 		char *kaddr;
@@ -334,7 +334,7 @@
 	struct inode *inode)
 {
 	struct inode *dir = (struct inode*)page->mapping->host;
-	struct minix_sb_info *sbi = &dir->i_sb->u.minix_sb;
+	struct minix_sb_info *sbi = minix_sb(dir->i_sb);
 	unsigned from = (char *)de-(char*)page_address(page);
 	unsigned to = from + sbi->s_dirsize;
 	int err;
@@ -354,7 +354,7 @@
 struct minix_dir_entry * minix_dotdot (struct inode *dir, struct page **p)
 {
 	struct page *page = dir_get_page(dir, 0);
-	struct minix_sb_info *sbi = &dir->i_sb->u.minix_sb;
+	struct minix_sb_info *sbi = minix_sb(dir->i_sb);
 	struct minix_dir_entry *de = NULL;
 
 	if (!IS_ERR(page)) {
diff -Nru a/fs/minix/inode.c b/fs/minix/inode.c
--- a/fs/minix/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/minix/inode.c	Fri Mar 15 17:51:03 2002
@@ -36,7 +36,7 @@
 
 static void minix_commit_super(struct super_block * sb)
 {
-	mark_buffer_dirty(sb->u.minix_sb.s_sbh);
+	mark_buffer_dirty(minix_sb(sb)->s_sbh);
 	sb->s_dirt = 0;
 }
 
@@ -45,7 +45,7 @@
 	struct minix_super_block * ms;
 
 	if (!(sb->s_flags & MS_RDONLY)) {
-		ms = sb->u.minix_sb.s_ms;
+		ms = minix_sb(sb)->s_ms;
 
 		if (ms->s_state & MINIX_VALID_FS)
 			ms->s_state &= ~MINIX_VALID_FS;
@@ -58,17 +58,20 @@
 static void minix_put_super(struct super_block *sb)
 {
 	int i;
+	struct minix_sb_info *sbi = minix_sb(sb);
 
 	if (!(sb->s_flags & MS_RDONLY)) {
-		sb->u.minix_sb.s_ms->s_state = sb->u.minix_sb.s_mount_state;
-		mark_buffer_dirty(sb->u.minix_sb.s_sbh);
+		sbi->s_ms->s_state = sbi->s_mount_state;
+		mark_buffer_dirty(sbi->s_sbh);
 	}
-	for (i = 0; i < sb->u.minix_sb.s_imap_blocks; i++)
-		brelse(sb->u.minix_sb.s_imap[i]);
-	for (i = 0; i < sb->u.minix_sb.s_zmap_blocks; i++)
-		brelse(sb->u.minix_sb.s_zmap[i]);
-	brelse (sb->u.minix_sb.s_sbh);
-	kfree(sb->u.minix_sb.s_imap);
+	for (i = 0; i < sbi->s_imap_blocks; i++)
+		brelse(sbi->s_imap[i]);
+	for (i = 0; i < sbi->s_zmap_blocks; i++)
+		brelse(sbi->s_zmap[i]);
+	brelse (sbi->s_sbh);
+	kfree(sbi->s_imap);
+	sb->u.generic_sbp = NULL;
+	kfree(sbi);
 
 	return;
 }
@@ -129,32 +132,33 @@
 
 static int minix_remount (struct super_block * sb, int * flags, char * data)
 {
+	struct minix_sb_info * sbi = minix_sb(sb);
 	struct minix_super_block * ms;
 
-	ms = sb->u.minix_sb.s_ms;
+	ms = sbi->s_ms;
 	if ((*flags & MS_RDONLY) == (sb->s_flags & MS_RDONLY))
 		return 0;
 	if (*flags & MS_RDONLY) {
 		if (ms->s_state & MINIX_VALID_FS ||
-		    !(sb->u.minix_sb.s_mount_state & MINIX_VALID_FS))
+		    !(sbi->s_mount_state & MINIX_VALID_FS))
 			return 0;
 		/* Mounting a rw partition read-only. */
-		ms->s_state = sb->u.minix_sb.s_mount_state;
-		mark_buffer_dirty(sb->u.minix_sb.s_sbh);
+		ms->s_state = sbi->s_mount_state;
+		mark_buffer_dirty(sbi->s_sbh);
 		sb->s_dirt = 1;
 		minix_commit_super(sb);
 	}
 	else {
 	  	/* Mount a partition which is read-only, read-write. */
-		sb->u.minix_sb.s_mount_state = ms->s_state;
+		sbi->s_mount_state = ms->s_state;
 		ms->s_state &= ~MINIX_VALID_FS;
-		mark_buffer_dirty(sb->u.minix_sb.s_sbh);
+		mark_buffer_dirty(sbi->s_sbh);
 		sb->s_dirt = 1;
 
-		if (!(sb->u.minix_sb.s_mount_state & MINIX_VALID_FS))
+		if (!(sbi->s_mount_state & MINIX_VALID_FS))
 			printk ("MINIX-fs warning: remounting unchecked fs, "
 				"running fsck is recommended.\n");
-		else if ((sb->u.minix_sb.s_mount_state & MINIX_ERROR_FS))
+		else if ((sbi->s_mount_state & MINIX_ERROR_FS))
 			printk ("MINIX-fs warning: remounting fs with errors, "
 				"running fsck is recommended.\n");
 	}
@@ -168,7 +172,13 @@
 	struct minix_super_block *ms;
 	int i, block;
 	struct inode *root_inode;
-	struct minix_sb_info *sbi = &s->u.minix_sb;
+	struct minix_sb_info *sbi;
+
+	sbi = kmalloc(sizeof(struct minix_sb_info), GFP_KERNEL);
+	if (!sbi)
+		return -ENOMEM;
+	s->u.generic_sbp = sbi;
+	memset(sbi, 0, sizeof(struct minix_sb_info));
 
 	/* N.B. These should be compile-time tests.
 	   Unfortunately that is impossible. */
@@ -311,19 +321,22 @@
 out_bad_sb:
 	printk("MINIX-fs: unable to read superblock\n");
  out:
+	s->u.generic_sbp = NULL;
+	kfree(sbi);
 	return -EINVAL;
 }
 
 static int minix_statfs(struct super_block *sb, struct statfs *buf)
 {
+	struct minix_sb_info *sbi = minix_sb(sb);
 	buf->f_type = sb->s_magic;
 	buf->f_bsize = sb->s_blocksize;
-	buf->f_blocks = (sb->u.minix_sb.s_nzones - sb->u.minix_sb.s_firstdatazone) << sb->u.minix_sb.s_log_zone_size;
+	buf->f_blocks = (sbi->s_nzones - sbi->s_firstdatazone) << sbi->s_log_zone_size;
 	buf->f_bfree = minix_count_free_blocks(sb);
 	buf->f_bavail = buf->f_bfree;
-	buf->f_files = sb->u.minix_sb.s_ninodes;
+	buf->f_files = sbi->s_ninodes;
 	buf->f_ffree = minix_count_free_inodes(sb);
-	buf->f_namelen = sb->u.minix_sb.s_namelen;
+	buf->f_namelen = sbi->s_namelen;
 	return 0;
 }
 
@@ -567,6 +580,7 @@
 	owner:		THIS_MODULE,
 	name:		"minix",
 	get_sb:		minix_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/minix/itree_v1.c b/fs/minix/itree_v1.c
--- a/fs/minix/itree_v1.c	Fri Mar 15 17:51:03 2002
+++ b/fs/minix/itree_v1.c	Fri Mar 15 17:51:03 2002
@@ -28,7 +28,7 @@
 
 	if (block < 0) {
 		printk("minix_bmap: block<0");
-	} else if (block >= (inode->i_sb->u.minix_sb.s_max_size/BLOCK_SIZE)) {
+	} else if (block >= (minix_sb(inode->i_sb)->s_max_size/BLOCK_SIZE)) {
 		printk("minix_bmap: block>big");
 	} else if (block < 7) {
 		offsets[n++] = block;
diff -Nru a/fs/minix/itree_v2.c b/fs/minix/itree_v2.c
--- a/fs/minix/itree_v2.c	Fri Mar 15 17:51:02 2002
+++ b/fs/minix/itree_v2.c	Fri Mar 15 17:51:02 2002
@@ -28,7 +28,7 @@
 
 	if (block < 0) {
 		printk("minix_bmap: block<0");
-	} else if (block >= (inode->i_sb->u.minix_sb.s_max_size/BLOCK_SIZE)) {
+	} else if (block >= (minix_sb(inode->i_sb)->s_max_size/BLOCK_SIZE)) {
 		printk("minix_bmap: block>big");
 	} else if (block < 7) {
 		offsets[n++] = block;
diff -Nru a/fs/minix/namei.c b/fs/minix/namei.c
--- a/fs/minix/namei.c	Fri Mar 15 17:51:02 2002
+++ b/fs/minix/namei.c	Fri Mar 15 17:51:02 2002
@@ -38,7 +38,7 @@
 	int i;
 	const unsigned char *name;
 
-	i = dentry->d_inode->i_sb->u.minix_sb.s_namelen;
+	i = minix_sb(dentry->d_inode->i_sb)->s_namelen;
 	if (i >= qstr->len)
 		return 0;
 	/* Truncate the name in place, avoids having to define a compare
@@ -63,7 +63,7 @@
 
 	dentry->d_op = dir->i_sb->s_root->d_op;
 
-	if (dentry->d_name.len > dir->i_sb->u.minix_sb.s_namelen)
+	if (dentry->d_name.len > minix_sb(dir->i_sb)->s_namelen)
 		return ERR_PTR(-ENAMETOOLONG);
 
 	ino = minix_inode_by_name(dentry);
@@ -131,7 +131,7 @@
 {
 	struct inode *inode = old_dentry->d_inode;
 
-	if (inode->i_nlink >= inode->i_sb->u.minix_sb.s_link_max)
+	if (inode->i_nlink >= minix_sb(inode->i_sb)->s_link_max)
 		return -EMLINK;
 
 	inode->i_ctime = CURRENT_TIME;
@@ -145,7 +145,7 @@
 	struct inode * inode;
 	int err = -EMLINK;
 
-	if (dir->i_nlink >= dir->i_sb->u.minix_sb.s_link_max)
+	if (dir->i_nlink >= minix_sb(dir->i_sb)->s_link_max)
 		goto out;
 
 	inc_count(dir);
@@ -221,7 +221,7 @@
 static int minix_rename(struct inode * old_dir, struct dentry *old_dentry,
 			   struct inode * new_dir, struct dentry *new_dentry)
 {
-	struct minix_sb_info * info = &old_dir->i_sb->u.minix_sb;
+	struct minix_sb_info * info = minix_sb(old_dir->i_sb);
 	struct inode * old_inode = old_dentry->d_inode;
 	struct inode * new_inode = new_dentry->d_inode;
 	struct page * dir_page = NULL;
diff -Nru a/fs/msdos/msdosfs_syms.c b/fs/msdos/msdosfs_syms.c
--- a/fs/msdos/msdosfs_syms.c	Fri Mar 15 17:51:01 2002
+++ b/fs/msdos/msdosfs_syms.c	Fri Mar 15 17:51:01 2002
@@ -35,6 +35,7 @@
 	owner:		THIS_MODULE,
 	name:		"msdos",
 	get_sb:		msdos_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/msdos/namei.c b/fs/msdos/namei.c
--- a/fs/msdos/namei.c	Fri Mar 15 17:51:03 2002
+++ b/fs/msdos/namei.c	Fri Mar 15 17:51:03 2002
@@ -603,17 +603,14 @@
 
 int msdos_fill_super(struct super_block *sb,void *data, int silent)
 {
-	struct super_block *res;
+	int res;
 
-	MSDOS_SB(sb)->options.isvfat = 0;
-	res = fat_read_super(sb, data, silent, &msdos_dir_inode_operations);
-	if (IS_ERR(res))
-		return PTR_ERR(res);
-	if (res == NULL) {
-		if (!silent)
+	res = fat_fill_super(sb, data, silent, &msdos_dir_inode_operations, 0);
+	if (res) {
+		if (res == -EINVAL && !silent)
 			printk(KERN_INFO "VFS: Can't find a valid"
 			       " MSDOS filesystem on dev %s.\n", sb->s_id);
-		return -EINVAL;
+		return res;
 	}
 
 	sb->s_root->d_op = &msdos_dentry_operations;
diff -Nru a/fs/namei.c b/fs/namei.c
--- a/fs/namei.c	Fri Mar 15 17:51:02 2002
+++ b/fs/namei.c	Fri Mar 15 17:51:02 2002
@@ -686,7 +686,7 @@
 	if (!emul)
 		goto set_it;
 	err = path_lookup(emul, LOOKUP_FOLLOW|LOOKUP_DIRECTORY|LOOKUP_NOALT, &nd);
-	if (err) {
+	if (!err) {
 		mnt = nd.mnt;
 		dentry = nd.dentry;
 	}
diff -Nru a/fs/namespace.c b/fs/namespace.c
--- a/fs/namespace.c	Fri Mar 15 17:51:01 2002
+++ b/fs/namespace.c	Fri Mar 15 17:51:01 2002
@@ -23,7 +23,6 @@
 
 struct vfsmount *do_kern_mount(const char *type, int flags, char *name, void *data);
 int do_remount_sb(struct super_block *sb, int flags, void * data);
-void kill_super(struct super_block *sb);
 int __init init_rootfs(void);
 
 static struct list_head *mount_hashtable;
@@ -152,7 +151,7 @@
 	struct super_block *sb = mnt->mnt_sb;
 	dput(mnt->mnt_root);
 	free_vfsmnt(mnt);
-	kill_super(sb);
+	deactivate_super(sb);
 }
 
 /* iterator */
diff -Nru a/fs/ncpfs/inode.c b/fs/ncpfs/inode.c
--- a/fs/ncpfs/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/ncpfs/inode.c	Fri Mar 15 17:51:03 2002
@@ -315,6 +315,12 @@
 #endif
 	struct ncp_entry_info finfo;
 
+	server = kmalloc(sizeof(struct ncp_server), GFP_KERNEL);
+	if (!server)
+		return -ENOMEM;
+	sb->u.generic_sbp = server;
+	memset(server, 0, sizeof(struct ncp_server));
+
 	error = -EFAULT;
 	if (raw_data == NULL)
 		goto out;
@@ -520,6 +526,8 @@
 	 */
 	fput(ncp_filp);
 out:
+	sb->u.generic_sbp = NULL;
+	kfree(server);
 	return error;
 }
 
@@ -553,7 +561,8 @@
 	if (server->auth.object_name)
 		ncp_kfree_s(server->auth.object_name, server->auth.object_name_len);
 	vfree(server->packet);
-
+	sb->u.generic_sbp = NULL;
+	kfree(server);
 }
 
 static int ncp_statfs(struct super_block *sb, struct statfs *buf)
@@ -744,6 +753,7 @@
 	owner:		THIS_MODULE,
 	name:		"ncpfs",
 	get_sb:		ncp_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 static int __init init_ncp_fs(void)
diff -Nru a/fs/nfs/dir.c b/fs/nfs/dir.c
--- a/fs/nfs/dir.c	Fri Mar 15 17:51:03 2002
+++ b/fs/nfs/dir.c	Fri Mar 15 17:51:03 2002
@@ -614,6 +614,12 @@
 	struct inode *inode;
 	int error = -EACCES;
 
+	if (fhandle->size == 0 || !(fattr->valid & NFS_ATTR_FATTR)) {
+		struct inode *dir = dentry->d_parent->d_inode;
+		error = NFS_PROTO(dir)->lookup(dir, &dentry->d_name, fhandle, fattr);
+		if (error)
+			goto out_err;
+	}
 	inode = nfs_fhget(dentry, fhandle, fattr);
 	if (inode) {
 		d_instantiate(dentry, inode);
@@ -621,6 +627,9 @@
 		error = 0;
 	}
 	return error;
+out_err:
+	d_drop(dentry);
+	return error;
 }
 
 /*
@@ -652,9 +661,9 @@
 	nfs_zap_caches(dir);
 	error = NFS_PROTO(dir)->create(dir, &dentry->d_name,
 					 &attr, 0, &fhandle, &fattr);
-	if (!error && fhandle.size != 0)
+	if (!error)
 		error = nfs_instantiate(dentry, &fhandle, &fattr);
-	if (error || fhandle.size == 0)
+	else
 		d_drop(dentry);
 	unlock_kernel();
 	return error;
@@ -680,9 +689,9 @@
 	nfs_zap_caches(dir);
 	error = NFS_PROTO(dir)->mknod(dir, &dentry->d_name, &attr, rdev,
 					&fhandle, &fattr);
-	if (!error && fhandle.size != 0)
+	if (!error)
 		error = nfs_instantiate(dentry, &fhandle, &fattr);
-	if (error || fhandle.size == 0)
+	else
 		d_drop(dentry);
 	unlock_kernel();
 	return error;
@@ -717,9 +726,9 @@
 	nfs_zap_caches(dir);
 	error = NFS_PROTO(dir)->mkdir(dir, &dentry->d_name, &attr, &fhandle,
 					&fattr);
-	if (!error && fhandle.size != 0)
+	if (!error)
 		error = nfs_instantiate(dentry, &fhandle, &fattr);
-	if (error || fhandle.size == 0)
+	else
 		d_drop(dentry);
 	unlock_kernel();
 	return error;
@@ -930,7 +939,7 @@
 	nfs_zap_caches(dir);
 	error = NFS_PROTO(dir)->symlink(dir, &dentry->d_name, &qsymname,
 					  &attr, &sym_fh, &sym_attr);
-	if (!error && sym_fh.size != 0 && (sym_attr.valid & NFS_ATTR_FATTR)) {
+	if (!error) {
 		error = nfs_instantiate(dentry, &sym_fh, &sym_attr);
 	} else {
 		if (error == -EEXIST)
diff -Nru a/fs/nfs/inode.c b/fs/nfs/inode.c
--- a/fs/nfs/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/nfs/inode.c	Fri Mar 15 17:51:03 2002
@@ -144,7 +144,7 @@
 void
 nfs_put_super(struct super_block *sb)
 {
-	struct nfs_server *server = &sb->u.nfs_sb.s_server;
+	struct nfs_server *server = NFS_SB(sb);
 	struct rpc_clnt	*rpc;
 
 	/*
@@ -169,7 +169,7 @@
 void
 nfs_umount_begin(struct super_block *sb)
 {
-	struct nfs_server *server = &sb->u.nfs_sb.s_server;
+	struct nfs_server *server = NFS_SB(sb);
 	struct rpc_clnt	*rpc;
 
 	/* -EIO all pending I/O */
@@ -225,7 +225,7 @@
 static struct inode *
 nfs_get_root(struct super_block *sb, struct nfs_fh *rootfh)
 {
-	struct nfs_server	*server = &sb->u.nfs_sb.s_server;
+	struct nfs_server	*server = NFS_SB(sb);
 	struct nfs_fattr	fattr;
 	struct inode		*inode;
 	int			error;
@@ -245,16 +245,13 @@
  * and the root file handle obtained from the server's mount
  * daemon. We stash these away in the private superblock fields.
  */
-int nfs_fill_super(struct super_block *sb, void *raw_data, int silent)
+int nfs_fill_super(struct super_block *sb, struct nfs_mount_data *data, int silent)
 {
-	struct nfs_mount_data	*data = (struct nfs_mount_data *) raw_data;
 	struct nfs_server	*server;
 	struct rpc_xprt		*xprt = NULL;
 	struct rpc_clnt		*clnt = NULL;
-	struct nfs_fh		*root = &data->root, fh;
 	struct inode		*root_inode = NULL;
 	unsigned int		authflavor;
-	struct sockaddr_in	srvaddr;
 	struct rpc_timeout	timeparms;
 	struct nfs_fsinfo	fsinfo;
 	int			tcp, version, maxlen;
@@ -262,36 +259,11 @@
 	/* We probably want something more informative here */
 	snprintf(sb->s_id, sizeof(sb->s_id), "%x:%x", major(sb->s_dev), minor(sb->s_dev));
 
-	memset(&sb->u.nfs_sb, 0, sizeof(sb->u.nfs_sb));
-	if (!data)
-		goto out_miss_args;
-
-	memset(&fh, 0, sizeof(fh));
-	if (data->version != NFS_MOUNT_VERSION) {
-		printk("nfs warning: mount version %s than kernel\n",
-			data->version < NFS_MOUNT_VERSION ? "older" : "newer");
-		if (data->version < 2)
-			data->namlen = 0;
-		if (data->version < 3)
-			data->bsize  = 0;
-		if (data->version < 4) {
-			data->flags &= ~NFS_MOUNT_VER3;
-			root = &fh;
-			root->size = NFS2_FHSIZE;
-			memcpy(root->data, data->old_root.data, NFS2_FHSIZE);
-		}
-	}
-
-	/* We now require that the mount process passes the remote address */
-	memcpy(&srvaddr, &data->addr, sizeof(srvaddr));
-	if (srvaddr.sin_addr.s_addr == INADDR_ANY)
-		goto out_no_remote;
-
 	sb->s_magic      = NFS_SUPER_MAGIC;
 	sb->s_op         = &nfs_sops;
 	sb->s_blocksize_bits = 0;
 	sb->s_blocksize  = nfs_block_size(data->bsize, &sb->s_blocksize_bits);
-	server           = &sb->u.nfs_sb.s_server;
+	server           = NFS_SB(sb);
 	server->rsize    = nfs_block_size(data->rsize, NULL);
 	server->wsize    = nfs_block_size(data->wsize, NULL);
 	server->flags    = data->flags & NFS_MOUNT_FLAGMASK;
@@ -352,7 +324,7 @@
 
 	/* Now create transport and client */
 	xprt = xprt_create_proto(tcp? IPPROTO_TCP : IPPROTO_UDP,
-						&srvaddr, &timeparms);
+						&server->addr, &timeparms);
 	if (xprt == NULL)
 		goto out_no_xprt;
 
@@ -383,7 +355,7 @@
 	 * the root fh attributes.
 	 */
 	/* Did getting the root inode fail? */
-	if (!(root_inode = nfs_get_root(sb, root))
+	if (!(root_inode = nfs_get_root(sb, &server->fh))
 	    && (data->flags & NFS_MOUNT_VER3)) {
 		data->flags &= ~NFS_MOUNT_VER3;
 		rpciod_down();
@@ -400,7 +372,7 @@
 	sb->s_root->d_op = &nfs_dentry_operations;
 
 	/* Get some general file system info */
-        if (server->rpc_ops->statfs(server, root, &fsinfo) >= 0) {
+        if (server->rpc_ops->statfs(server, &server->fh, &fsinfo) >= 0) {
 		if (server->namelen == 0)
 			server->namelen = fsinfo.namelen;
 	} else {
@@ -499,13 +471,6 @@
 out_unlock:
 	goto out_fail;
 
-out_no_remote:
-	printk("NFS: mount program didn't pass remote address!\n");
-	goto out_fail;
-
-out_miss_args:
-	printk("nfs_read_super: missing data argument\n");
-
 out_fail:
 	return -EINVAL;
 }
@@ -513,7 +478,7 @@
 static int
 nfs_statfs(struct super_block *sb, struct statfs *buf)
 {
-	struct nfs_server *server = &sb->u.nfs_sb.s_server;
+	struct nfs_server *server = NFS_SB(sb);
 	unsigned char blockbits;
 	unsigned long blockres;
 	struct nfs_fsinfo res;
@@ -561,7 +526,7 @@
 		{ 0, NULL, NULL }
 	};
 	struct proc_nfs_info *nfs_infop;
-	struct nfs_server *nfss = &mnt->mnt_sb->u.nfs_sb.s_server;
+	struct nfs_server *nfss = NFS_SB(mnt->mnt_sb);
 
 	seq_printf(m, ",v%d", nfss->rpc_ops->version);
 	seq_printf(m, ",rsize=%d", nfss->rsize);
@@ -1139,22 +1104,106 @@
  * File system information
  */
 
-/*
- *  Right now we are using get_sb_nodev, but we ought to switch to
- *  get_anon_super() with appropriate comparison function.  The only
- *  question being, when two NFS mounts are the same?  Identical IP
- *  of server + identical root fhandle?  Trond?
- */
+static int nfs_set_super(struct super_block *s, void *data)
+{
+	s->u.generic_sbp = data;
+	return set_anon_super(s, data);
+}
+ 
+static int nfs_compare_super(struct super_block *sb, void *data)
+{
+	struct nfs_server *server = data;
+	struct nfs_server *old = NFS_SB(sb);
+
+	if (old->addr.sin_addr.s_addr != server->addr.sin_addr.s_addr)
+		return 0;
+	if (old->addr.sin_port != server->addr.sin_port)
+		return 0;
+	return !memcmp(&old->fh, &server->fh, sizeof(struct nfs_fh));
+}
+
 static struct super_block *nfs_get_sb(struct file_system_type *fs_type,
-	int flags, char *dev_name, void *data)
+	int flags, char *dev_name, void *raw_data)
+{
+	int error;
+	struct nfs_server *server;
+	struct super_block *s;
+	struct nfs_fh *root;
+	struct nfs_mount_data *data = raw_data;
+
+	if (!data) {
+		printk("nfs_read_super: missing data argument\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	server = kmalloc(sizeof(struct nfs_server), GFP_KERNEL);
+	if (!server)
+		return ERR_PTR(-ENOMEM);
+	memset(server, 0, sizeof(struct nfs_server));
+
+	root = &server->fh;
+	memcpy(root, &data->root, sizeof(*root));
+	if (root->size < sizeof(root->data))
+		memset(root->data+root->size, 0, sizeof(root->data)-root->size);
+
+	if (data->version != NFS_MOUNT_VERSION) {
+		printk("nfs warning: mount version %s than kernel\n",
+			data->version < NFS_MOUNT_VERSION ? "older" : "newer");
+		if (data->version < 2)
+			data->namlen = 0;
+		if (data->version < 3)
+			data->bsize  = 0;
+		if (data->version < 4) {
+			data->flags &= ~NFS_MOUNT_VER3;
+			memset(root, 0, sizeof(*root));
+			root->size = NFS2_FHSIZE;
+			memcpy(root->data, data->old_root.data, NFS2_FHSIZE);
+		}
+	}
+
+	if (root->size > sizeof(root->data)) {
+		printk("nfs_get_sb: invalid root filehandle\n");
+		return ERR_PTR(-EINVAL);
+	}
+	/* We now require that the mount process passes the remote address */
+	memcpy(&server->addr, &data->addr, sizeof(server->addr));
+	if (server->addr.sin_addr.s_addr == INADDR_ANY) {
+		printk("NFS: mount program didn't pass remote address!\n");
+		kfree(server);
+		return ERR_PTR(-EINVAL);
+	}
+
+	s = sget(fs_type, nfs_compare_super, nfs_set_super, server);
+
+	if (IS_ERR(s) || s->s_root) {
+		kfree(server);
+		return s;
+	}
+
+	s->s_flags = flags;
+
+	error = nfs_fill_super(s, data, flags & MS_VERBOSE ? 1 : 0);
+	if (error) {
+		up_write(&s->s_umount);
+		deactivate_super(s);
+		return ERR_PTR(error);
+	}
+	s->s_flags |= MS_ACTIVE;
+	return s;
+}
+
+static void nfs_kill_super(struct super_block *s)
 {
-	return get_sb_nodev(fs_type, flags, data, nfs_fill_super);
+	struct nfs_server *server = NFS_SB(s);
+	kill_anon_super(s);
+	kfree(server);
 }
 
 static struct file_system_type nfs_fs_type = {
 	owner:		THIS_MODULE,
 	name:		"nfs",
 	get_sb:		nfs_get_sb,
+	kill_sb:	nfs_kill_super,
 	fs_flags:	FS_ODD_RENAME,
 };
 
diff -Nru a/fs/nfs/nfs3proc.c b/fs/nfs/nfs3proc.c
--- a/fs/nfs/nfs3proc.c	Fri Mar 15 17:51:03 2002
+++ b/fs/nfs/nfs3proc.c	Fri Mar 15 17:51:03 2002
@@ -17,6 +17,37 @@
 
 #define NFSDBG_FACILITY		NFSDBG_PROC
 
+/* A wrapper to handle the EJUKEBOX error message */
+static int
+nfs3_rpc_wrapper(struct rpc_clnt *clnt, struct rpc_message *msg, int flags)
+{
+	sigset_t oldset;
+	int res;
+	rpc_clnt_sigmask(clnt, &oldset);
+	do {
+		res = rpc_call_sync(clnt, msg, flags);
+		if (res != -EJUKEBOX)
+			break;
+		set_current_state(TASK_INTERRUPTIBLE);
+		schedule_timeout(NFS_JUKEBOX_RETRY_TIME);
+		res = -ERESTARTSYS;
+	} while (!signalled());
+	rpc_clnt_sigunmask(clnt, &oldset);
+	return res;
+}
+
+static inline int
+nfs3_rpc_call_wrapper(struct rpc_clnt *clnt, u32 proc, void *argp, void *resp, int flags)
+{
+	struct rpc_message msg = { proc, argp, resp, NULL };
+	return nfs3_rpc_wrapper(clnt, &msg, flags);
+}
+
+#define rpc_call(clnt, proc, argp, resp, flags) \
+		nfs3_rpc_call_wrapper(clnt, proc, argp, resp, flags)
+#define rpc_call_sync(clnt, msg, flags) \
+		nfs3_rpc_wrapper(clnt, msg, flags)
+
 /*
  * Bare-bones access to getattr: this is for nfs_read_super.
  */
diff -Nru a/fs/nfs/pagelist.c b/fs/nfs/pagelist.c
--- a/fs/nfs/pagelist.c	Fri Mar 15 17:51:02 2002
+++ b/fs/nfs/pagelist.c	Fri Mar 15 17:51:02 2002
@@ -231,7 +231,7 @@
  *
  * Moves a maximum of 'nmax' elements from one list to another.
  * The elements are checked to ensure that they form a contiguous set
- * of pages, and that they originated from the same file.
+ * of pages, and that the RPC credentials are the same.
  */
 int
 nfs_coalesce_requests(struct list_head *head, struct list_head *dst,
@@ -245,7 +245,7 @@
 
 		req = nfs_list_entry(head->next);
 		if (prev) {
-			if (req->wb_file != prev->wb_file)
+			if (req->wb_cred != prev->wb_cred)
 				break;
 			if (page_index(req->wb_page) != page_index(prev->wb_page)+1)
 				break;
@@ -272,14 +272,14 @@
  *
  * Tries to coalesce more requests by traversing the request's wb_list.
  * Moves the resulting list into dst. Requests are guaranteed to be
- * contiguous, and to originate from the same file.
+ * contiguous, and have the same RPC credentials.
  */
 static int
 nfs_scan_forward(struct nfs_page *req, struct list_head *dst, int nmax)
 {
 	struct nfs_server *server = NFS_SERVER(req->wb_inode);
 	struct list_head *pos, *head = req->wb_list_head;
-	struct file *file = req->wb_file;
+	struct rpc_cred *cred = req->wb_cred;
 	unsigned long idx = page_index(req->wb_page) + 1;
 	int npages = 0;
 
@@ -300,7 +300,7 @@
 			break;
 		if (req->wb_offset != 0)
 			break;
-		if (req->wb_file != file)
+		if (req->wb_cred != cred)
 			break;
 	}
 	return npages;
diff -Nru a/fs/nfs/read.c b/fs/nfs/read.c
--- a/fs/nfs/read.c	Fri Mar 15 17:51:00 2002
+++ b/fs/nfs/read.c	Fri Mar 15 17:51:00 2002
@@ -408,6 +408,9 @@
 	dprintk("NFS: %4d nfs_readpage_result, (status %d)\n",
 		task->tk_pid, task->tk_status);
 
+	if (nfs_async_handle_jukebox(task))
+		return;
+
 	nfs_refresh_inode(inode, &data->fattr);
 	while (!list_empty(&data->pages)) {
 		struct nfs_page *req = nfs_list_entry(data->pages.next);
diff -Nru a/fs/nfs/unlink.c b/fs/nfs/unlink.c
--- a/fs/nfs/unlink.c	Fri Mar 15 17:51:03 2002
+++ b/fs/nfs/unlink.c	Fri Mar 15 17:51:03 2002
@@ -123,6 +123,8 @@
 	struct dentry		*dir = data->dir;
 	struct inode		*dir_i;
 
+	if (nfs_async_handle_jukebox(task))
+		return;
 	if (!dir)
 		return;
 	dir_i = dir->d_inode;
diff -Nru a/fs/nfs/write.c b/fs/nfs/write.c
--- a/fs/nfs/write.c	Fri Mar 15 17:51:02 2002
+++ b/fs/nfs/write.c	Fri Mar 15 17:51:02 2002
@@ -764,6 +764,7 @@
 nfs_flush_incompatible(struct file *file, struct page *page)
 {
 	struct inode	*inode = page->mapping->host;
+	struct rpc_cred	*cred = nfs_file_cred(file);
 	struct nfs_page	*req;
 	int		status = 0;
 	/*
@@ -776,7 +777,7 @@
 	 */
 	req = nfs_find_request(inode,page);
 	if (req) {
-		if (req->wb_file != file || req->wb_page != page)
+		if (req->wb_file != file || req->wb_cred != cred || req->wb_page != page)
 			status = nfs_wb_page(inode, page);
 		nfs_release_request(req);
 	}
@@ -1011,6 +1012,9 @@
 	dprintk("NFS: %4d nfs_writeback_done (status %d)\n",
 		task->tk_pid, task->tk_status);
 
+	if (nfs_async_handle_jukebox(task))
+		return;
+
 	/* We can't handle that yet but we check for it nevertheless */
 	if (resp->count < argp->count && task->tk_status >= 0) {
 		static unsigned long    complain;
@@ -1203,6 +1207,9 @@
 
         dprintk("NFS: %4d nfs_commit_done (status %d)\n",
                                 task->tk_pid, task->tk_status);
+
+	if (nfs_async_handle_jukebox(task))
+		return;
 
 	nfs_write_attributes(inode, resp->fattr);
 	while (!list_empty(&data->pages)) {
diff -Nru a/fs/nfsctl.c b/fs/nfsctl.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/nfsctl.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,87 @@
+/*
+ *	fs/nfsctl.c
+ *
+ *	This should eventually move to userland.
+ *
+ */
+#include <linux/config.h>
+#include <linux/file.h>
+#include <linux/fs.h>
+#include <linux/sunrpc/svc.h>
+#include <linux/nfsd/nfsd.h>
+#include <linux/nfsd/syscall.h>
+#include <linux/linkage.h>
+#include <asm/uaccess.h>
+
+/*
+ * open a file on nfsd fs
+ */
+
+struct vfsmount *do_kern_mount(const char *type, int flags, char *name, void *data);
+
+static struct file *do_open(char *name, int flags)
+{
+	struct nameidata nd;
+	int error;
+
+	nd.mnt = do_kern_mount("nfsd", 0, "nfsd", NULL);
+
+	if (IS_ERR(nd.mnt))
+		return (struct file *)nd.mnt;
+
+	nd.dentry = dget(nd.mnt->mnt_root);
+	nd.last_type = LAST_ROOT;
+	nd.flags = 0;
+
+	error = path_walk(name, &nd);
+	if (error)
+		return ERR_PTR(error);
+
+	return dentry_open(nd.dentry, nd.mnt, flags);
+}
+
+static struct {
+	char *name; int wsize; int rsize;
+} map[] = {
+	[NFSCTL_SVC]={"svc", sizeof(struct nfsctl_svc)},
+	[NFSCTL_ADDCLIENT]={"add", sizeof(struct nfsctl_client)},
+	[NFSCTL_DELCLIENT]={"del", sizeof(struct nfsctl_client)},
+	[NFSCTL_EXPORT]={"export", sizeof(struct nfsctl_export)},
+	[NFSCTL_UNEXPORT]={"unexport", sizeof(struct nfsctl_export)},
+#ifdef notyet
+	[NFSCTL_UGIDUPDATE]={"ugid", sizeof(struct nfsctl_uidmap)},
+#endif
+	[NFSCTL_GETFD]={"getfd", sizeof(struct nfsctl_fdparm), NFS_FHSIZE},
+	[NFSCTL_GETFS]={"getfs", sizeof(struct nfsctl_fsparm), sizeof(struct knfsd_fh)},
+};
+
+long
+asmlinkage sys_nfsservctl(int cmd, struct nfsctl_arg *arg, void *res)
+{
+	struct file *file;
+	void *p = &arg->u;
+	int version;
+	int err;
+
+	if (copy_from_user(&version, &arg->ca_version, sizeof(int)))
+		return -EFAULT;
+
+	if (version != NFSCTL_VERSION) {
+		printk(KERN_WARNING "nfsd: incompatible version in syscall.\n");
+		return -EINVAL;
+	}
+
+	if (cmd < 0 || cmd >= sizeof(map)/sizeof(map[0]) || !map[cmd].name)
+		return -EINVAL;
+
+	file = do_open(map[cmd].name, map[cmd].rsize ? O_RDWR : O_WRONLY);	
+	if (IS_ERR(file))
+		return PTR_ERR(file);
+	err = file->f_op->write(file, p, map[cmd].wsize, &file->f_pos);
+	if (err >= 0 && map[cmd].rsize)
+		err = file->f_op->read(file, res, map[cmd].rsize, &file->f_pos);
+	if (err >= 0)
+		err = 0;
+	fput(file);
+	return err;
+}
diff -Nru a/fs/nfsd/export.c b/fs/nfsd/export.c
--- a/fs/nfsd/export.c	Fri Mar 15 17:51:03 2002
+++ b/fs/nfsd/export.c	Fri Mar 15 17:51:03 2002
@@ -52,6 +52,7 @@
 		((((a)>>24) ^ ((a)>>16) ^ ((a)>>8) ^(a)) & CLIENT_HASHMASK)
 /* XXX: is this adequate for 32bit kdev_t ? */
 #define EXPORT_HASH(dev)	(minor(dev) & (NFSCLNT_EXPMAX - 1))
+#define EXPORT_FSID_HASH(fsid)	((fsid) & (NFSCLNT_EXPMAX - 1))
 
 struct svc_clnthash {
 	struct svc_clnthash *	h_next;
@@ -82,6 +83,27 @@
 	return NULL;
 }
 
+/*
+ * Find the client's export entry matching fsid
+ */
+svc_export *
+exp_get_fsid(svc_client *clp, int fsid)
+{
+	struct list_head *head, *p;
+
+
+	if (!clp)
+		return NULL;
+
+	head = &clp->cl_expfsid[EXPORT_FSID_HASH(fsid)];
+	list_for_each(p, head) {
+		svc_export *exp = list_entry(p, svc_export, ex_fsid_hash);
+		if (exp->ex_fsid == fsid)
+			return exp;
+	}
+	return NULL;
+}
+
 svc_export *
 exp_get_by_name(svc_client *clp, struct vfsmount *mnt, struct dentry *dentry)
 {
@@ -192,6 +214,25 @@
 	up_write(&hash_sem);
 }
 
+static void exp_fsid_unhash(struct svc_export *exp)
+{
+
+	if ((exp->ex_flags & NFSEXP_FSID) == 0)
+		return;
+
+	list_del_init(&exp->ex_fsid_hash);
+}
+
+static void exp_fsid_hash(struct svc_client *clp, struct svc_export *exp)
+{
+	struct list_head *head;
+
+	if ((exp->ex_flags & NFSEXP_FSID) == 0)
+		return;
+	head = clp->cl_expfsid + EXPORT_FSID_HASH(exp->ex_fsid);
+	list_add(&exp->ex_fsid_hash, head);
+}
+
 /*
  * Export a file system.
  */
@@ -199,7 +240,8 @@
 exp_export(struct nfsctl_export *nxp)
 {
 	svc_client	*clp;
-	svc_export	*exp, *parent;
+	svc_export	*exp = NULL, *parent;
+	svc_export	*fsid_exp;
 	struct nameidata nd;
 	struct inode	*inode = NULL;
 	int		err;
@@ -215,8 +257,6 @@
 	dprintk("exp_export called for %s:%s (%x/%ld fl %x).\n",
 			nxp->ex_client, nxp->ex_path,
 			nxp->ex_dev, (long) nxp->ex_ino, nxp->ex_flags);
-	dev = to_kdev_t(nxp->ex_dev);
-	ino = nxp->ex_ino;
 
 	/* Try to lock the export table for update */
 	exp_writelock();
@@ -225,30 +265,34 @@
 	if (!(clp = exp_getclientbyname(nxp->ex_client)))
 		goto out_unlock;
 
-	/*
-	 * If there's already an export for this file, assume this
-	 * is just a flag update.
-	 */
-	if ((exp = exp_get(clp, dev, ino)) != NULL) {
-		exp->ex_flags    = nxp->ex_flags;
-		exp->ex_anon_uid = nxp->ex_anon_uid;
-		exp->ex_anon_gid = nxp->ex_anon_gid;
-		err = 0;
-		goto out_unlock;
-	}
 
 	/* Look up the dentry */
 	err = path_lookup(nxp->ex_path, 0, &nd);
 	if (err)
 		goto out_unlock;
-
 	inode = nd.dentry->d_inode;
+	dev = inode->i_dev;
+	ino = inode->i_ino;
 	err = -EINVAL;
-	if (!kdev_same(inode->i_dev, dev) || inode->i_ino != nxp->ex_ino) {
-		printk(KERN_DEBUG "exp_export: i_dev = %02x:%02x, dev = %02x:%02x\n",
-			major(inode->i_dev), minor(inode->i_dev),
-			major(dev), minor(dev)); 
-		/* I'm just being paranoid... */
+
+	exp = exp_get(clp, dev, ino);
+
+	/* must make sure there wont be an ex_fsid clash */
+	if ((nxp->ex_flags & NFSEXP_FSID) &&
+	    (fsid_exp = exp_get_fsid(clp, nxp->ex_dev)) &&
+	    fsid_exp != exp)
+		goto finish;
+
+	if (exp != NULL) {
+		/* just a flags/id/fsid update */
+
+		exp_fsid_unhash(exp);
+		exp->ex_flags    = nxp->ex_flags;
+		exp->ex_anon_uid = nxp->ex_anon_uid;
+		exp->ex_anon_gid = nxp->ex_anon_gid;
+		exp->ex_fsid     = nxp->ex_dev;
+		exp_fsid_hash(clp, exp);
+		err = 0;
 		goto finish;
 	}
 
@@ -285,13 +329,15 @@
 	strcpy(exp->ex_path, nxp->ex_path);
 	exp->ex_client = clp;
 	exp->ex_parent = parent;
-	exp->ex_dentry = nd.dentry;
-	exp->ex_mnt = nd.mnt;
+	exp->ex_mnt = mntget(nd.mnt);
+	exp->ex_dentry = dget(nd.dentry);
 	exp->ex_flags = nxp->ex_flags;
 	exp->ex_dev = dev;
 	exp->ex_ino = ino;
 	exp->ex_anon_uid = nxp->ex_anon_uid;
 	exp->ex_anon_gid = nxp->ex_anon_gid;
+	exp->ex_fsid = nxp->ex_dev;
+
 
 	/* Update parent pointers of all exports */
 	if (parent)
@@ -300,18 +346,16 @@
 	list_add(&exp->ex_hash, clp->cl_export + EXPORT_HASH(dev));
 	list_add_tail(&exp->ex_list, &clp->cl_list);
 
+	exp_fsid_hash(clp, exp);
+
 	err = 0;
 
-	/* Unlock hashtable */
+finish:
+	path_release(&nd);
 out_unlock:
 	exp_writeunlock();
 out:
 	return err;
-
-	/* Release the dentry */
-finish:
-	path_release(&nd);
-	goto out_unlock;
 }
 
 /*
@@ -325,6 +369,9 @@
 	struct vfsmount *mnt;
 	struct inode	*inode;
 
+	list_del(&unexp->ex_list);
+	list_del(&unexp->ex_hash);
+	exp_fsid_unhash(unexp);
 	/* Update parent pointers. */
 	exp_change_parents(unexp->ex_client, unexp, unexp->ex_parent);
 	dentry = unexp->ex_dentry;
@@ -340,8 +387,6 @@
 
 /*
  * Revoke all exports for a given client.
- * This may look very awkward, but we have to do it this way in order
- * to avoid race conditions (aka mind the parent pointer).
  */
 static void
 exp_unexport_all(svc_client *clp)
@@ -352,8 +397,6 @@
 
 	while (!list_empty(p)) {
 		svc_export *exp = list_entry(p->next, svc_export, ex_list);
-		list_del(&exp->ex_list);
-		list_del(&exp->ex_hash);
 		exp_do_unexport(exp);
 	}
 }
@@ -379,8 +422,6 @@
 		kdev_t ex_dev = to_kdev_t(nxp->ex_dev);
 		svc_export *exp = exp_get(clp, ex_dev, nxp->ex_ino);
 		if (exp) {
-			list_del(&exp->ex_hash);
-			list_del(&exp->ex_list);
 			exp_do_unexport(exp);
 			err = 0;
 		}
@@ -433,8 +474,7 @@
 	fh_put(&fh);
 
 out:
-	if (path)
-		path_release(&nd);
+	path_release(&nd);
 	return err;
 }
 
@@ -455,13 +495,19 @@
 
 	for (hp = head; (tmp = *hp) != NULL; hp = &(tmp->h_next)) {
 		if (tmp->h_addr.s_addr == addr) {
+#if 0
+/* If we really want to do this, we need a spin
+lock to protect against multiple access (as we only
+have an exp_readlock) and need to protect
+the code in e_show() that walks this list too.
+*/
 			/* Move client to the front */
 			if (head != hp) {
 				*hp = tmp->h_next;
 				tmp->h_next = *head;
 				*head = tmp;
 			}
-
+#endif
 			return tmp->h_client;
 		}
 	}
@@ -568,7 +614,7 @@
 	{ 0, {"", ""}}
 };
 
-static void exp_flags(struct seq_file *m, int flag)
+static void exp_flags(struct seq_file *m, int flag, int fsid)
 {
 	int first = 0;
 	struct flags *flg;
@@ -578,6 +624,8 @@
 		if (*flg->name[state])
 			seq_printf(m, "%s%s", first++?",":"", flg->name[state]);
 	}
+	if (flag & NFSEXP_FSID)
+		seq_printf(m, "%sfsid=%d", first++?",":"", fsid);
 }
 
 static inline void mangle(struct seq_file *m, const char *s)
@@ -603,7 +651,7 @@
 	seq_putc(m, '\t');
 	mangle(m, clp->cl_ident);
 	seq_putc(m, '(');
-	exp_flags(m, exp->ex_flags);
+	exp_flags(m, exp->ex_flags, exp->ex_fsid);
 	seq_puts(m, ") # ");
 	for (j = 0; j < clp->cl_naddr; j++) {
 		struct svc_clnthash **hp, **head, *tmp;
@@ -673,8 +721,10 @@
 		if (!(clp = kmalloc(sizeof(*clp), GFP_KERNEL)))
 			goto out_unlock;
 		memset(clp, 0, sizeof(*clp));
-		for (i = 0; i < NFSCLNT_EXPMAX; i++)
+		for (i = 0; i < NFSCLNT_EXPMAX; i++) {
 			INIT_LIST_HEAD(&clp->cl_export[i]);
+			INIT_LIST_HEAD(&clp->cl_expfsid[i]);
+		}
 		INIT_LIST_HEAD(&clp->cl_list);
 
 		dprintk("created client %s (%p)\n", ncp->cl_ident, clp);
diff -Nru a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c
--- a/fs/nfsd/nfsctl.c	Fri Mar 15 17:51:01 2002
+++ b/fs/nfsd/nfsctl.c	Fri Mar 15 17:51:01 2002
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/proc_fs.h>
 #include <linux/seq_file.h>
+#include <linux/pagemap.h>
 
 #include <linux/nfs.h>
 #include <linux/sunrpc/svc.h>
@@ -30,20 +31,96 @@
 #include <linux/nfsd/syscall.h>
 
 #include <asm/uaccess.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/init.h>
-
-static int	nfsctl_svc(struct nfsctl_svc *data);
-static int	nfsctl_addclient(struct nfsctl_client *data);
-static int	nfsctl_delclient(struct nfsctl_client *data);
-static int	nfsctl_export(struct nfsctl_export *data);
-static int	nfsctl_unexport(struct nfsctl_export *data);
-static int	nfsctl_getfd(struct nfsctl_fdparm *, __u8 *);
-static int	nfsctl_getfs(struct nfsctl_fsparm *, struct knfsd_fh *);
-#ifdef notyet
-static int	nfsctl_ugidupdate(struct nfsctl_ugidmap *data);
-#endif
+
+/*
+ *	We have a single directory with 8 nodes in it.
+ */
+enum {
+	NFSD_Root = 1,
+	NFSD_Svc,
+	NFSD_Add,
+	NFSD_Del,
+	NFSD_Export,
+	NFSD_Unexport,
+	NFSD_Getfd,
+	NFSD_Getfs,
+	NFSD_List,
+};
+
+/*
+ * write() for these nodes.
+ */
+static ssize_t write_svc(struct file *file, const char *buf, size_t size);
+static ssize_t write_add(struct file *file, const char *buf, size_t size);
+static ssize_t write_del(struct file *file, const char *buf, size_t size);
+static ssize_t write_export(struct file *file, const char *buf, size_t size);
+static ssize_t write_unexport(struct file *file, const char *buf, size_t size);
+static ssize_t write_getfd(struct file *file, const char *buf, size_t size);
+static ssize_t write_getfs(struct file *file, const char *buf, size_t size);
+
+static ssize_t (*write_op[])(struct file *, const char *, size_t) = {
+	[NFSD_Svc] = write_svc,
+	[NFSD_Add] = write_add,
+	[NFSD_Del] = write_del,
+	[NFSD_Export] = write_export,
+	[NFSD_Unexport] = write_unexport,
+	[NFSD_Getfd] = write_getfd,
+	[NFSD_Getfs] = write_getfs,
+};
+
+static ssize_t fs_write(struct file *file, const char *buf, size_t size, loff_t *pos)
+{
+	ino_t ino =  file->f_dentry->d_inode->i_ino;
+	if (ino >= sizeof(write_op)/sizeof(write_op[0]) || !write_op[ino])
+		return -EINVAL;
+	return write_op[ino](file, buf, size);
+}
+
+/*
+ * read(), open() and release() for getfs and getfd (read/write ones).
+ * IO on these is a simple transaction - you open() the file, write() to it
+ * and that generates a (stored) response.  After that read() will simply
+ * access that response.
+ */
+
+static ssize_t TA_read(struct file *file, char *buf, size_t size, loff_t *pos)
+{
+	if (!file->private_data)
+		return 0;
+	if (*pos >= file->f_dentry->d_inode->i_size)
+		return 0;
+	if (*pos + size > file->f_dentry->d_inode->i_size)
+		size = file->f_dentry->d_inode->i_size - *pos;
+	if (copy_to_user(buf, file->private_data + *pos, size))
+		return -EFAULT;
+	*pos += size;
+	return size;
+}
+
+static ssize_t TA_open(struct inode *inode, struct file *file)
+{
+	file->private_data = NULL;
+	return 0;
+}
+
+static ssize_t TA_release(struct inode *inode, struct file *file)
+{
+	void *p = file->private_data;
+	file->private_data = NULL;
+	kfree(p);
+	return 0;
+}
+
+static struct file_operations writer_ops = {
+	write:	fs_write,
+};
+
+static struct file_operations reader_ops = {
+	write:	fs_write,
+	read:	TA_read,
+	open:	TA_open,
+	release:TA_release,
+};
 
 extern struct seq_operations nfs_exports_op;
 static int exports_open(struct inode *inode, struct file *file)
@@ -57,254 +134,277 @@
 	release:	seq_release,
 };
 
-void proc_export_init(void)
-{
-	struct proc_dir_entry *entry;
-	if (!proc_mkdir("fs/nfs", 0))
-		return;
-	entry = create_proc_entry("fs/nfs/exports", 0, NULL);
-	if (entry)
-		entry->proc_fops =  &exports_operations;
-}
+/*
+ *	Description of fs contents.
+ */
+static struct { char *name; struct file_operations *ops; int mode; } files[] = {
+	[NFSD_Svc] = {"svc", &writer_ops, S_IWUSR},
+	[NFSD_Add] = {"add", &writer_ops, S_IWUSR},
+	[NFSD_Del] = {"del", &writer_ops, S_IWUSR},
+	[NFSD_Export] = {"export", &writer_ops, S_IWUSR},
+	[NFSD_Unexport] = {"unexport", &writer_ops, S_IWUSR},
+	[NFSD_Getfd] = {"getfd", &reader_ops, S_IWUSR|S_IRUSR},
+	[NFSD_Getfs] = {"getfs", &reader_ops, S_IWUSR|S_IRUSR},
+	[NFSD_List] = {"exports", &exports_operations, S_IRUGO},
+};
 
-static inline int
-nfsctl_svc(struct nfsctl_svc *data)
-{
-	return nfsd_svc(data->svc_port, data->svc_nthreads);
-}
+/*----------------------------------------------------------------------------*/
+/*
+ * payload - write methods
+ */
 
-static inline int
-nfsctl_addclient(struct nfsctl_client *data)
+static ssize_t write_svc(struct file *file, const char *buf, size_t size)
 {
-	return exp_addclient(data);
+	struct nfsctl_svc data;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	return nfsd_svc(data.svc_port, data.svc_nthreads);
 }
 
-static inline int
-nfsctl_delclient(struct nfsctl_client *data)
+static ssize_t write_add(struct file *file, const char *buf, size_t size)
 {
-	return exp_delclient(data);
+	struct nfsctl_client data;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	return exp_addclient(&data);
 }
 
-static inline int
-nfsctl_export(struct nfsctl_export *data)
+static ssize_t write_del(struct file *file, const char *buf, size_t size)
 {
-	return exp_export(data);
+	struct nfsctl_client data;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	return exp_delclient(&data);
 }
 
-static inline int
-nfsctl_unexport(struct nfsctl_export *data)
+static ssize_t write_export(struct file *file, const char *buf, size_t size)
 {
-	return exp_unexport(data);
+	struct nfsctl_export data;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	return exp_export(&data);
 }
 
-#ifdef notyet
-static inline int
-nfsctl_ugidupdate(nfs_ugidmap *data)
+static ssize_t write_unexport(struct file *file, const char *buf, size_t size)
 {
-	return -EINVAL;
+	struct nfsctl_export data;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	return exp_unexport(&data);
 }
-#endif
 
-static inline int
-nfsctl_getfs(struct nfsctl_fsparm *data, struct knfsd_fh *res)
+static ssize_t write_getfs(struct file *file, const char *buf, size_t size)
 {
-	struct sockaddr_in	*sin;
-	struct svc_client	*clp;
-	int			err = 0;
+	struct nfsctl_fsparm data;
+	struct sockaddr_in *sin;
+	struct svc_client *clp;
+	int err = 0;
+	struct knfsd_fh *res;
 
-	if (data->gd_addr.sa_family != AF_INET)
+	if (file->private_data)
+		return -EINVAL;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	if (data.gd_addr.sa_family != AF_INET)
 		return -EPROTONOSUPPORT;
-	sin = (struct sockaddr_in *)&data->gd_addr;
-	if (data->gd_maxlen > NFS3_FHSIZE)
-		data->gd_maxlen = NFS3_FHSIZE;
+	sin = (struct sockaddr_in *)&data.gd_addr;
+	if (data.gd_maxlen > NFS3_FHSIZE)
+		data.gd_maxlen = NFS3_FHSIZE;
+	res = kmalloc(sizeof(struct knfsd_fh), GFP_KERNEL);
+	if (!res)
+		return -ENOMEM;
+	memset(res, 0, sizeof(struct knfsd_fh));
 	exp_readlock();
 	if (!(clp = exp_getclient(sin)))
 		err = -EPERM;
 	else
-		err = exp_rootfh(clp, data->gd_path, res, data->gd_maxlen);
+		err = exp_rootfh(clp, data.gd_path, res, data.gd_maxlen);
 	exp_readunlock();
+
+	down(&file->f_dentry->d_inode->i_sem);
+	if (file->private_data)
+		err = -EINVAL;
+	if (err)
+		kfree(res);
+	else {
+		file->f_dentry->d_inode->i_size = res->fh_size + (int)&((struct knfsd_fh*)0)->fh_base;
+		file->private_data = res;
+		err = sizeof(data);
+	}
+	up(&file->f_dentry->d_inode->i_sem);
+
 	return err;
 }
 
-static inline int
-nfsctl_getfd(struct nfsctl_fdparm *data, __u8 *res)
+static ssize_t write_getfd(struct file *file, const char *buf, size_t size)
 {
-	struct sockaddr_in	*sin;
-	struct svc_client	*clp;
-	int			err = 0;
-	struct	knfsd_fh	fh;
+	struct nfsctl_fdparm data;
+	struct sockaddr_in *sin;
+	struct svc_client *clp;
+	int err = 0;
+	struct knfsd_fh fh;
+	char *res;
 
-	if (data->gd_addr.sa_family != AF_INET)
+	if (file->private_data)
+		return -EINVAL;
+	if (size < sizeof(data))
+		return -EINVAL;
+	if (copy_from_user(&data, buf, size))
+		return -EFAULT;
+	if (data.gd_addr.sa_family != AF_INET)
 		return -EPROTONOSUPPORT;
-	if (data->gd_version < 2 || data->gd_version > NFSSVC_MAXVERS)
+	if (data.gd_version < 2 || data.gd_version > NFSSVC_MAXVERS)
 		return -EINVAL;
-	sin = (struct sockaddr_in *)&data->gd_addr;
-
+	res = kmalloc(NFS_FHSIZE, GFP_KERNEL);
+	if (!res)
+		return -ENOMEM;
+	sin = (struct sockaddr_in *)&data.gd_addr;
 	exp_readlock();
 	if (!(clp = exp_getclient(sin)))
 		err = -EPERM;
 	else
-		err = exp_rootfh(clp, data->gd_path, &fh, NFS_FHSIZE);
+		err = exp_rootfh(clp, data.gd_path, &fh, NFS_FHSIZE);
 	exp_readunlock();
 
-	if (err == 0) {
-		if (fh.fh_size > NFS_FHSIZE)
-			err = -EINVAL;
-		else {
-			memset(res,0, NFS_FHSIZE);
-			memcpy(res, &fh.fh_base, fh.fh_size);
-		}
+	down(&file->f_dentry->d_inode->i_sem);
+	if (file->private_data)
+		err = -EINVAL;
+	if (!err && fh.fh_size > NFS_FHSIZE)
+		err = -EINVAL;
+	if (err)
+		kfree(res);
+	else {
+		memset(res,0, NFS_FHSIZE);
+		memcpy(res, &fh.fh_base, fh.fh_size);
+		file->f_dentry->d_inode->i_size = NFS_FHSIZE;
+		file->private_data = res;
+		err = sizeof(data);
 	}
+	up(&file->f_dentry->d_inode->i_sem);
 
 	return err;
 }
 
-#ifdef CONFIG_NFSD
-#define handle_sys_nfsservctl sys_nfsservctl
-#endif
-
-static struct {
-	int argsize, respsize;
-}  sizes[] = {
-	/* NFSCTL_SVC        */ { sizeof(struct nfsctl_svc), 0 },
-	/* NFSCTL_ADDCLIENT  */ { sizeof(struct nfsctl_client), 0},
-	/* NFSCTL_DELCLIENT  */ { sizeof(struct nfsctl_client), 0},
-	/* NFSCTL_EXPORT     */ { sizeof(struct nfsctl_export), 0},
-	/* NFSCTL_UNEXPORT   */ { sizeof(struct nfsctl_export), 0},
-	/* NFSCTL_UGIDUPDATE */ { sizeof(struct nfsctl_uidmap), 0},
-	/* NFSCTL_GETFH      */ { sizeof(struct nfsctl_fhparm), NFS_FHSIZE},
-	/* NFSCTL_GETFD      */ { sizeof(struct nfsctl_fdparm), NFS_FHSIZE},
-	/* NFSCTL_GETFS      */ { sizeof(struct nfsctl_fsparm), sizeof(struct knfsd_fh)},
+/*----------------------------------------------------------------------------*/
+/*
+ *	populating the filesystem.
+ */
+
+static struct super_operations s_ops = {
+	statfs:		simple_statfs,
 };
-#define CMD_MAX (sizeof(sizes)/sizeof(sizes[0])-1)
 
-long
-asmlinkage handle_sys_nfsservctl(int cmd, void *opaque_argp, void *opaque_resp)
+static int nfsd_fill_super(struct super_block * sb, void * data, int silent)
 {
-	struct nfsctl_arg *	argp = opaque_argp;
-	union nfsctl_res *	resp = opaque_resp;
-	struct nfsctl_arg *	arg = NULL;
-	union nfsctl_res *	res = NULL;
-	int			err;
-	int			argsize, respsize;
-
-
-	err = -EPERM;
-	if (!capable(CAP_SYS_ADMIN)) {
-		goto done;
-	}
-	err = -EINVAL;
-	if (cmd<0 || cmd > CMD_MAX)
-		goto done;
-	err = -EFAULT;
-	argsize = sizes[cmd].argsize + (int)&((struct nfsctl_arg *)0)->u;
-	respsize = sizes[cmd].respsize;	/* maximum */
-	if (!access_ok(VERIFY_READ, argp, argsize)
-	 || (resp && !access_ok(VERIFY_WRITE, resp, respsize))) {
-		goto done;
-	}
-	err = -ENOMEM;	/* ??? */
-	if (!(arg = kmalloc(sizeof(*arg), GFP_USER)) ||
-	    (resp && !(res = kmalloc(sizeof(*res), GFP_USER)))) {
-		goto done;
-	}
-
-	err = -EINVAL;
-	copy_from_user(arg, argp, argsize);
-	if (arg->ca_version != NFSCTL_VERSION) {
-		printk(KERN_WARNING "nfsd: incompatible version in syscall.\n");
-		goto done;
+	struct inode *inode;
+	struct dentry *root;
+	struct dentry *dentry;
+	int i;
+
+	sb->s_blocksize = PAGE_CACHE_SIZE;
+	sb->s_blocksize_bits = PAGE_CACHE_SHIFT;
+	sb->s_magic = 0x6e667364;
+	sb->s_op = &s_ops;
+
+	inode = new_inode(sb);
+	if (!inode)
+		return -ENOMEM;
+	inode->i_mode = S_IFDIR | 0755;
+	inode->i_uid = inode->i_gid = 0;
+	inode->i_blksize = PAGE_CACHE_SIZE;
+	inode->i_blocks = 0;
+	inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
+	inode->i_op = &simple_dir_inode_operations;
+	inode->i_fop = &simple_dir_operations;
+	root = d_alloc_root(inode);
+	if (!root) {
+		iput(inode);
+		return -ENOMEM;
 	}
-
-	switch(cmd) {
-	case NFSCTL_SVC:
-		err = nfsctl_svc(&arg->ca_svc);
-		break;
-	case NFSCTL_ADDCLIENT:
-		err = nfsctl_addclient(&arg->ca_client);
-		break;
-	case NFSCTL_DELCLIENT:
-		err = nfsctl_delclient(&arg->ca_client);
-		break;
-	case NFSCTL_EXPORT:
-		err = nfsctl_export(&arg->ca_export);
-		break;
-	case NFSCTL_UNEXPORT:
-		err = nfsctl_unexport(&arg->ca_export);
-		break;
-#ifdef notyet
-	case NFSCTL_UGIDUPDATE:
-		err = nfsctl_ugidupdate(&arg->ca_umap);
-		break;
-#endif
-	case NFSCTL_GETFD:
-		err = nfsctl_getfd(&arg->ca_getfd, res->cr_getfh);
-		break;
-	case NFSCTL_GETFS:
-		err = nfsctl_getfs(&arg->ca_getfs, &res->cr_getfs);
-		respsize = res->cr_getfs.fh_size+ (int)&((struct knfsd_fh*)0)->fh_base;
-		break;
-	default:
-		err = -EINVAL;
+	for (i = NFSD_Svc; i <= NFSD_List; i++) {
+		struct qstr name;
+		name.name = files[i].name;
+		name.len = strlen(name.name);
+		name.hash = full_name_hash(name.name, name.len);
+		dentry = d_alloc(root, &name);
+		if (!dentry)
+			goto out;
+		inode = new_inode(sb);
+		if (!inode)
+			goto out;
+		inode->i_mode = S_IFREG | files[i].mode;
+		inode->i_uid = inode->i_gid = 0;
+		inode->i_blksize = PAGE_CACHE_SIZE;
+		inode->i_blocks = 0;
+		inode->i_atime = inode->i_mtime = inode->i_ctime = CURRENT_TIME;
+		inode->i_fop = files[i].ops;
+		inode->i_ino = i;
+		d_add(dentry, inode);
 	}
+	sb->s_root = root;
+	return 0;
 
-	if (!err && resp && respsize)
-		copy_to_user(resp, res, respsize);
-
-done:
-	if (arg)
-		kfree(arg);
-	if (res)
-		kfree(res);
-
-	return err;
+out:
+	d_genocide(root);
+	dput(root);
+	return -ENOMEM;
 }
 
-EXPORT_NO_SYMBOLS;
-MODULE_AUTHOR("Olaf Kirch <okir@monad.swb.de>");
-MODULE_LICENSE("GPL");
+static struct super_block *nfsd_get_sb(struct file_system_type *fs_type,
+	int flags, char *dev_name, void *data)
+{
+	return get_sb_single(fs_type, flags, data, nfsd_fill_super);
+}
 
-#ifdef MODULE
-struct nfsd_linkage nfsd_linkage_s = {
-	do_nfsservctl: handle_sys_nfsservctl,
-	owner: THIS_MODULE,
+static struct file_system_type nfsd_fs_type = {
+	owner:		THIS_MODULE,
+	name:		"nfsd",
+	get_sb:		nfsd_get_sb,
+	kill_sb:	kill_litter_super,
 };
-#endif
 
-/*
- * Initialize the module
- */
-static int __init
-nfsd_init(void)
+static int __init init_nfsd(void)
 {
 	printk(KERN_INFO "Installing knfsd (copyright (C) 1996 okir@monad.swb.de).\n");
-#ifdef MODULE
-	nfsd_linkage = &nfsd_linkage_s;
-#endif
 	nfsd_stat_init();	/* Statistics */
 	nfsd_cache_init();	/* RPC reply cache */
 	nfsd_export_init();	/* Exports table */
 	nfsd_lockd_init();	/* lockd->nfsd callbacks */
-	proc_export_init();
+	if (proc_mkdir("fs/nfs", 0)) {
+		struct proc_dir_entry *entry;
+		entry = create_proc_entry("fs/nfs/exports", 0, NULL);
+		if (entry)
+			entry->proc_fops =  &exports_operations;
+	}
+	register_filesystem(&nfsd_fs_type);
 	return 0;
 }
 
-/*
- * Clean up the mess before unloading the module
- */
-static void __exit
-nfsd_exit(void)
+static void __exit exit_nfsd(void)
 {
-#ifdef MODULE
-	nfsd_linkage = NULL;
-#endif
 	nfsd_export_shutdown();
 	nfsd_cache_shutdown();
 	remove_proc_entry("fs/nfs/exports", NULL);
 	remove_proc_entry("fs/nfs", NULL);
 	nfsd_stat_shutdown();
 	nfsd_lockd_shutdown();
+	unregister_filesystem(&nfsd_fs_type);
 }
 
-module_init(nfsd_init);
-module_exit(nfsd_exit);
+EXPORT_NO_SYMBOLS;
+MODULE_AUTHOR("Olaf Kirch <okir@monad.swb.de>");
+MODULE_LICENSE("GPL");
+module_init(init_nfsd)
+module_exit(exit_nfsd)
diff -Nru a/fs/nfsd/nfsfh.c b/fs/nfsd/nfsfh.c
--- a/fs/nfsd/nfsfh.c	Fri Mar 15 17:51:02 2002
+++ b/fs/nfsd/nfsfh.c	Fri Mar 15 17:51:02 2002
@@ -547,11 +547,13 @@
 	dprintk("nfsd: fh_verify(%s)\n", SVCFH_fmt(fhp));
 
 	if (!fhp->fh_dentry) {
-		kdev_t xdev;
-		ino_t xino;
+		kdev_t xdev = NODEV;
+		ino_t xino = 0;
 		__u32 *datap=NULL;
 		int data_left = fh->fh_size/4;
 		int nfsdev;
+		int fsid = 0;
+
 		error = nfserr_stale;
 		if (rqstp->rq_vers == 3)
 			error = nfserr_badhandle;
@@ -571,6 +573,10 @@
 				xdev = mk_kdev(nfsdev>>16, nfsdev&0xFFFF);
 				xino = *datap++;
 				break;
+			case 1:
+				if ((data_left-=1)<0) goto out;
+				fsid = *datap++;
+				break;
 			default:
 				goto out;
 			}
@@ -586,7 +592,10 @@
 		 * Look up the export entry.
 		 */
 		error = nfserr_stale; 
-		exp = exp_get(rqstp->rq_client, xdev, xino);
+		if (fh->fh_version == 1 && fh->fh_fsid_type == 1)
+			exp = exp_get_fsid(rqstp->rq_client, fsid);
+		else
+			exp = exp_get(rqstp->rq_client, xdev, xino);
 
 		if (!exp) {
 			/* export entry revoked */
@@ -838,12 +847,20 @@
 	} else {
 		fhp->fh_handle.fh_version = 1;
 		fhp->fh_handle.fh_auth_type = 0;
-		fhp->fh_handle.fh_fsid_type = 0;
 		datap = fhp->fh_handle.fh_auth+0;
-		/* fsid_type 0 == 2byte major, 2byte minor, 4byte inode */
-		*datap++ = htonl((major(exp->ex_dev)<<16)| minor(exp->ex_dev));
-		*datap++ = ino_t_to_u32(exp->ex_ino);
-		fhp->fh_handle.fh_size = 3*4;
+		if ((exp->ex_flags & NFSEXP_FSID) &&
+		    (!ref_fh || ref_fh->fh_handle.fh_fsid_type == 1)) {
+			fhp->fh_handle.fh_fsid_type = 1;
+			/* fsid_type 1 == 4 bytes filesystem id */
+			*datap++ = exp->ex_fsid;
+			fhp->fh_handle.fh_size = 2*4;
+		} else {
+			fhp->fh_handle.fh_fsid_type = 0;
+			/* fsid_type 0 == 2byte major, 2byte minor, 4byte inode */
+			*datap++ = htonl((major(exp->ex_dev)<<16)| minor(exp->ex_dev));
+			*datap++ = ino_t_to_u32(exp->ex_ino);
+			fhp->fh_handle.fh_size = 3*4;
+		}
 		if (inode) {
 			int size = fhp->fh_maxsize/4 - 3;
 			fhp->fh_handle.fh_fileid_type =
diff -Nru a/fs/ntfs/fs.c b/fs/ntfs/fs.c
--- a/fs/ntfs/fs.c	Fri Mar 15 17:51:01 2002
+++ b/fs/ntfs/fs.c	Fri Mar 15 17:51:01 2002
@@ -1168,6 +1168,7 @@
 	owner:		THIS_MODULE,
 	name:		"ntfs",
 	get_sb:		ntfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/openpromfs/inode.c b/fs/openpromfs/inode.c
--- a/fs/openpromfs/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/openpromfs/inode.c	Fri Mar 15 17:51:03 2002
@@ -995,20 +995,9 @@
 	}
 }
 
-static int openprom_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = OPENPROM_SUPER_MAGIC;
-	buf->f_bsize = PAGE_SIZE/sizeof(long);	/* ??? */
-	buf->f_bfree = 0;
-	buf->f_bavail = 0;
-	buf->f_ffree = 0;
-	buf->f_namelen = NAME_MAX;
-	return 0;
-}
-
 static struct super_operations openprom_sops = { 
 	read_inode:	openprom_read_inode,
-	statfs:		openprom_statfs,
+	statfs:		simple_statfs,
 };
 
 static int openprom_fill_super(struct super_block *s, void *data, int silent)
@@ -1043,6 +1032,7 @@
 	owner:		THIS_MODULE,
 	name:		"openpromfs",
 	get_sb:		openprom_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 static int __init init_openprom_fs(void)
diff -Nru a/fs/pipe.c b/fs/pipe.c
--- a/fs/pipe.c	Fri Mar 15 17:51:01 2002
+++ b/fs/pipe.c	Fri Mar 15 17:51:01 2002
@@ -589,16 +589,9 @@
  * any operations on the root directory. However, we need a non-trivial
  * d_name - pipe: will go nicely and kill the special-casing in procfs.
  */
-static int pipefs_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = PIPEFS_MAGIC;
-	buf->f_bsize = 1024;
-	buf->f_namelen = 255;
-	return 0;
-}
 
 static struct super_operations pipefs_ops = {
-	statfs:		pipefs_statfs,
+	statfs:		simple_statfs,
 };
 
 static int pipefs_fill_super(struct super_block *sb, void *data, int silent)
@@ -635,6 +628,7 @@
 static struct file_system_type pipe_fs_type = {
 	name:		"pipefs",
 	get_sb:		pipefs_get_sb,
+	kill_sb:	kill_anon_super,
 	fs_flags:	FS_NOMOUNT,
 };
 
diff -Nru a/fs/proc/array.c b/fs/proc/array.c
--- a/fs/proc/array.c	Fri Mar 15 17:51:01 2002
+++ b/fs/proc/array.c	Fri Mar 15 17:51:01 2002
@@ -159,7 +159,7 @@
 		"Uid:\t%d\t%d\t%d\t%d\n"
 		"Gid:\t%d\t%d\t%d\t%d\n",
 		get_task_state(p), p->tgid,
-		p->pid, p->pid ? p->p_opptr->pid : 0, 0,
+		p->pid, p->pid ? p->real_parent->pid : 0, 0,
 		p->uid, p->euid, p->suid, p->fsuid,
 		p->gid, p->egid, p->sgid, p->fsgid);
 	read_unlock(&tasklist_lock);	
@@ -340,7 +340,7 @@
 	nice = task_nice(task);
 
 	read_lock(&tasklist_lock);
-	ppid = task->pid ? task->p_opptr->pid : 0;
+	ppid = task->pid ? task->real_parent->pid : 0;
 	read_unlock(&tasklist_lock);
 	res = sprintf(buffer,"%d (%s) %c %d %d %d %d %d %lu %lu \
 %lu %lu %lu %lu %lu %ld %ld %ld %ld %ld %ld %lu %lu %ld %lu %lu %lu %lu %lu \
diff -Nru a/fs/proc/base.c b/fs/proc/base.c
--- a/fs/proc/base.c	Fri Mar 15 17:51:01 2002
+++ b/fs/proc/base.c	Fri Mar 15 17:51:01 2002
@@ -336,7 +336,7 @@
 };
 
 #define MAY_PTRACE(p) \
-(p==current||(p->p_pptr==current&&(p->ptrace & PT_PTRACED)&&p->state==TASK_STOPPED))
+(p==current||(p->parent==current&&(p->ptrace & PT_PTRACED)&&p->state==TASK_STOPPED))
 
 
 static int mem_open(struct inode* inode, struct file* file)
@@ -730,6 +730,7 @@
 	return inode;
 
 out_unlock:
+	ei->pde = NULL;
 	iput(inode);
 	return NULL;
 }
diff -Nru a/fs/proc/inode.c b/fs/proc/inode.c
--- a/fs/proc/inode.c	Fri Mar 15 17:51:02 2002
+++ b/fs/proc/inode.c	Fri Mar 15 17:51:02 2002
@@ -82,17 +82,6 @@
 	inode->i_mtime = inode->i_atime = inode->i_ctime = CURRENT_TIME;
 }
 
-static int proc_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = PROC_SUPER_MAGIC;
-	buf->f_bsize = PAGE_SIZE/sizeof(long);
-	buf->f_bfree = 0;
-	buf->f_bavail = 0;
-	buf->f_ffree = 0;
-	buf->f_namelen = NAME_MAX;
-	return 0;
-}
-
 static kmem_cache_t * proc_inode_cachep;
 
 static struct inode *proc_alloc_inode(struct super_block *sb)
@@ -135,7 +124,7 @@
 	read_inode:	proc_read_inode,
 	put_inode:	force_delete,
 	delete_inode:	proc_delete_inode,
-	statfs:		proc_statfs,
+	statfs:		simple_statfs,
 };
 
 static int parse_options(char *options,uid_t *uid,gid_t *gid)
diff -Nru a/fs/proc/kcore.c b/fs/proc/kcore.c
--- a/fs/proc/kcore.c	Fri Mar 15 17:51:01 2002
+++ b/fs/proc/kcore.c	Fri Mar 15 17:51:01 2002
@@ -381,8 +381,13 @@
 			return tsz;
 	}
 #endif
-	/* fill the remainder of the buffer from kernel VM space */
-	start = (unsigned long)__va(*fpos - elf_buflen);
+	
+	/*
+	 * Fill the remainder of the buffer from kernel VM space.
+	 * We said in the ELF header that the data which starts
+	 * at 'elf_buflen' is virtual address PAGE_OFFSET. --rmk
+	 */
+	start = PAGE_OFFSET + (*fpos - elf_buflen);
 	if ((tsz = (PAGE_SIZE - (start & ~PAGE_MASK))) > buflen)
 		tsz = buflen;
 		
diff -Nru a/fs/proc/root.c b/fs/proc/root.c
--- a/fs/proc/root.c	Fri Mar 15 17:51:03 2002
+++ b/fs/proc/root.c	Fri Mar 15 17:51:03 2002
@@ -33,6 +33,7 @@
 static struct file_system_type proc_fs_type = {
 	name:		"proc",
 	get_sb:		proc_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 extern int __init proc_init_inodecache(void);
diff -Nru a/fs/qnx4/bitmap.c b/fs/qnx4/bitmap.c
--- a/fs/qnx4/bitmap.c	Fri Mar 15 17:51:03 2002
+++ b/fs/qnx4/bitmap.c	Fri Mar 15 17:51:03 2002
@@ -62,11 +62,11 @@
 
 unsigned long qnx4_count_free_blocks(struct super_block *sb)
 {
-	int start = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_first_xtnt.xtnt_blk) - 1;
+	int start = le32_to_cpu(qnx4_sb(sb)->BitMap->di_first_xtnt.xtnt_blk) - 1;
 	int total = 0;
 	int total_free = 0;
 	int offset = 0;
-	int size = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_size);
+	int size = le32_to_cpu(qnx4_sb(sb)->BitMap->di_size);
 	struct buffer_head *bh;
 
 	while (total < size) {
@@ -87,8 +87,8 @@
 
 int qnx4_is_free(struct super_block *sb, long block)
 {
-	int start = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_first_xtnt.xtnt_blk) - 1;
-	int size = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_size);
+	int start = le32_to_cpu(qnx4_sb(sb)->BitMap->di_first_xtnt.xtnt_blk) - 1;
+	int size = le32_to_cpu(qnx4_sb(sb)->BitMap->di_size);
 	struct buffer_head *bh;
 	const char *g;
 	int ret = -EIO;
@@ -116,8 +116,8 @@
 
 int qnx4_set_bitmap(struct super_block *sb, long block, int busy)
 {
-	int start = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_first_xtnt.xtnt_blk) - 1;
-	int size = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_size);
+	int start = le32_to_cpu(qnx4_sb(sb)->BitMap->di_first_xtnt.xtnt_blk) - 1;
+	int size = le32_to_cpu(qnx4_sb(sb)->BitMap->di_size);
 	struct buffer_head *bh;
 	char *g;
 
diff -Nru a/fs/qnx4/inode.c b/fs/qnx4/inode.c
--- a/fs/qnx4/inode.c	Fri Mar 15 17:51:02 2002
+++ b/fs/qnx4/inode.c	Fri Mar 15 17:51:02 2002
@@ -147,7 +147,7 @@
 {
 	struct qnx4_sb_info *qs;
 
-	qs = &sb->u.qnx4_sb;
+	qs = qnx4_sb(sb);
 	qs->Version = QNX4_VERSION;
 	if (*flags & MS_RDONLY) {
 		return 0;
@@ -280,7 +280,7 @@
 {
 	buf->f_type    = sb->s_magic;
 	buf->f_bsize   = sb->s_blocksize;
-	buf->f_blocks  = le32_to_cpu(sb->u.qnx4_sb.BitMap->di_size) * 8;
+	buf->f_blocks  = le32_to_cpu(qnx4_sb(sb)->BitMap->di_size) * 8;
 	buf->f_bfree   = qnx4_count_free_blocks(sb);
 	buf->f_bavail  = buf->f_bfree;
 	buf->f_namelen = QNX4_NAME_MAX;
@@ -301,12 +301,12 @@
 	int i, j;
 	int found = 0;
 
-	if (*(sb->u.qnx4_sb.sb->RootDir.di_fname) != '/') {
+	if (*(qnx4_sb(sb)->sb->RootDir.di_fname) != '/') {
 		return "no qnx4 filesystem (no root dir).";
 	} else {
 		QNX4DEBUG(("QNX4 filesystem found on dev %s.\n", sb->s_id));
-		rd = le32_to_cpu(sb->u.qnx4_sb.sb->RootDir.di_first_xtnt.xtnt_blk) - 1;
-		rl = le32_to_cpu(sb->u.qnx4_sb.sb->RootDir.di_first_xtnt.xtnt_size);
+		rd = le32_to_cpu(qnx4_sb(sb)->sb->RootDir.di_first_xtnt.xtnt_blk) - 1;
+		rl = le32_to_cpu(qnx4_sb(sb)->sb->RootDir.di_first_xtnt.xtnt_size);
 		for (j = 0; j < rl; j++) {
 			bh = sb_bread(sb, rd + j);	/* root dir, first block */
 			if (bh == NULL) {
@@ -318,8 +318,8 @@
 					QNX4DEBUG(("Rootdir entry found : [%s]\n", rootdir->di_fname));
 					if (!strncmp(rootdir->di_fname, QNX4_BMNAME, sizeof QNX4_BMNAME)) {
 						found = 1;
-						sb->u.qnx4_sb.BitMap = kmalloc( sizeof( struct qnx4_inode_entry ), GFP_KERNEL );
-						memcpy( sb->u.qnx4_sb.BitMap, rootdir, sizeof( struct qnx4_inode_entry ) );	/* keep bitmap inode known */
+						qnx4_sb(sb)->BitMap = kmalloc( sizeof( struct qnx4_inode_entry ), GFP_KERNEL );
+						memcpy( qnx4_sb(sb)->BitMap, rootdir, sizeof( struct qnx4_inode_entry ) );	/* keep bitmap inode known */
 						break;
 					}
 				}
@@ -341,6 +341,13 @@
 	struct buffer_head *bh;
 	struct inode *root;
 	const char *errmsg;
+	struct qnx4_sb_info *qs;
+
+	qs = kmalloc(sizeof(struct qnx4_sb_info), GFP_KERNEL);
+	if (!qs)
+		return -ENOMEM;
+	s->u.generic_sbp = qs;
+	memset(qs, 0, sizeof(struct qnx4_sb_info));
 
 	sb_set_blocksize(s, QNX4_BLOCK_SIZE);
 
@@ -369,8 +376,8 @@
 #ifndef CONFIG_QNX4FS_RW
 	s->s_flags |= MS_RDONLY;	/* Yup, read-only yet */
 #endif
-	s->u.qnx4_sb.sb_buf = bh;
-	s->u.qnx4_sb.sb = (struct qnx4_super_block *) bh->b_data;
+	qnx4_sb(s)->sb_buf = bh;
+	qnx4_sb(s)->sb = (struct qnx4_super_block *) bh->b_data;
 
 
  	/* check before allocating dentries, inodes, .. */
@@ -401,13 +408,17 @@
       out:
 	brelse(bh);
       outnobh:
-
+	kfree(qs);
+	s->u.generic_sbp = NULL;
 	return -EINVAL;
 }
 
 static void qnx4_put_super(struct super_block *sb)
 {
-	kfree( sb->u.qnx4_sb.BitMap );
+	struct qnx4_sb_info *qs = qnx4_sb(sb);
+	kfree( qs->BitMap );
+	kfree( qs );
+	sb->u.generic_sbp = NULL;
 	return;
 }
 
@@ -549,6 +560,7 @@
 	owner:		THIS_MODULE,
 	name:		"qnx4",
 	get_sb:		qnx4_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/ramfs/inode.c b/fs/ramfs/inode.c
--- a/fs/ramfs/inode.c	Fri Mar 15 17:51:02 2002
+++ b/fs/ramfs/inode.c	Fri Mar 15 17:51:02 2002
@@ -38,29 +38,9 @@
 
 static struct super_operations ramfs_ops;
 static struct address_space_operations ramfs_aops;
-static struct file_operations ramfs_dir_operations;
 static struct file_operations ramfs_file_operations;
 static struct inode_operations ramfs_dir_inode_operations;
 
-static int ramfs_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = RAMFS_MAGIC;
-	buf->f_bsize = PAGE_CACHE_SIZE;
-	buf->f_namelen = 255;
-	return 0;
-}
-
-/*
- * Lookup the data. This is trivial - if the dentry didn't already
- * exist, we know it is negative.
- */
-/* SMP-safe */
-static struct dentry * ramfs_lookup(struct inode *dir, struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
 /*
  * Read a page. Again trivial. If it didn't already exist
  * in the page cache, it is zero-filled.
@@ -122,7 +102,7 @@
 			break;
 		case S_IFDIR:
 			inode->i_op = &ramfs_dir_inode_operations;
-			inode->i_fop = &ramfs_dir_operations;
+			inode->i_fop = &simple_dir_operations;
 			break;
 		case S_IFLNK:
 			inode->i_op = &page_symlink_inode_operations;
@@ -284,15 +264,9 @@
 	fsync:		ramfs_sync_file,
 };
 
-static struct file_operations ramfs_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-	fsync:		ramfs_sync_file,
-};
-
 static struct inode_operations ramfs_dir_inode_operations = {
 	create:		ramfs_create,
-	lookup:		ramfs_lookup,
+	lookup:		simple_lookup,
 	link:		ramfs_link,
 	unlink:		ramfs_unlink,
 	symlink:	ramfs_symlink,
@@ -303,7 +277,7 @@
 };
 
 static struct super_operations ramfs_ops = {
-	statfs:		ramfs_statfs,
+	statfs:		simple_statfs,
 	put_inode:	force_delete,
 };
 
@@ -338,12 +312,13 @@
 static struct file_system_type ramfs_fs_type = {
 	name:		"ramfs",
 	get_sb:		ramfs_get_sb,
-	fs_flags:	FS_LITTER,
+	kill_sb:	kill_litter_super,
 };
 static struct file_system_type rootfs_fs_type = {
 	name:		"rootfs",
 	get_sb:		ramfs_get_sb,
-	fs_flags:	FS_NOMOUNT|FS_LITTER,
+	kill_sb:	kill_litter_super,
+	fs_flags:	FS_NOMOUNT,
 };
 
 static int __init init_ramfs_fs(void)
diff -Nru a/fs/read_write.c b/fs/read_write.c
--- a/fs/read_write.c	Fri Mar 15 17:51:03 2002
+++ b/fs/read_write.c	Fri Mar 15 17:51:03 2002
@@ -20,11 +20,6 @@
 	mmap:		generic_file_mmap,
 };
 
-ssize_t generic_read_dir(struct file *filp, char *buf, size_t siz, loff_t *ppos)
-{
-	return -EISDIR;
-}
-
 loff_t generic_file_llseek(struct file *file, loff_t offset, int origin)
 {
 	long long retval;
diff -Nru a/fs/readdir.c b/fs/readdir.c
--- a/fs/readdir.c	Fri Mar 15 17:51:03 2002
+++ b/fs/readdir.c	Fri Mar 15 17:51:03 2002
@@ -33,74 +33,6 @@
 }
 
 /*
- * Directory is locked and all positive dentries in it are safe, since
- * for ramfs-type trees they can't go away without unlink() or rmdir(),
- * both impossible due to the lock on directory.
- */
-
-int dcache_readdir(struct file * filp, void * dirent, filldir_t filldir)
-{
-	int i;
-	struct dentry *dentry = filp->f_dentry;
-
-	i = filp->f_pos;
-	switch (i) {
-		case 0:
-			if (filldir(dirent, ".", 1, i, dentry->d_inode->i_ino, DT_DIR) < 0)
-				break;
-			i++;
-			filp->f_pos++;
-			/* fallthrough */
-		case 1:
-			if (filldir(dirent, "..", 2, i, parent_ino(dentry), DT_DIR) < 0)
-				break;
-			i++;
-			filp->f_pos++;
-			/* fallthrough */
-		default: {
-			struct list_head *list;
-			int j = i-2;
-
-			spin_lock(&dcache_lock);
-			list = dentry->d_subdirs.next;
-
-			for (;;) {
-				if (list == &dentry->d_subdirs) {
-					spin_unlock(&dcache_lock);
-					return 0;
-				}
-				if (!j)
-					break;
-				j--;
-				list = list->next;
-			}
-
-			while(1) {
-				struct dentry *de = list_entry(list, struct dentry, d_child);
-
-				/*
-				 * See comment on top of function on why we
-				 * can just drop the lock here..
-				 */
-				if (!list_empty(&de->d_hash) && de->d_inode) {
-					spin_unlock(&dcache_lock);
-					if (filldir(dirent, de->d_name.name, de->d_name.len, filp->f_pos, de->d_inode->i_ino, DT_UNKNOWN) < 0)
-						break;
-					spin_lock(&dcache_lock);
-				}
-				filp->f_pos++;
-				list = list->next;
-				if (list != &dentry->d_subdirs)
-					continue;
-				spin_unlock(&dcache_lock);
-				break;
-			}
-		}
-	}
-	return 0;
-}
-
-/*
  * Traditional linux readdir() handling..
  *
  * "count=1" is a special case, meaning that the buffer is one
diff -Nru a/fs/reiserfs/super.c b/fs/reiserfs/super.c
--- a/fs/reiserfs/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/reiserfs/super.c	Fri Mar 15 17:51:03 2002
@@ -1193,6 +1193,7 @@
 	owner:		THIS_MODULE,
 	name:		"reiserfs",
 	get_sb:		reiserfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/romfs/inode.c b/fs/romfs/inode.c
--- a/fs/romfs/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/romfs/inode.c	Fri Mar 15 17:51:03 2002
@@ -76,6 +76,17 @@
 
 #include <asm/uaccess.h>
 
+struct romfs_inode_info {
+	unsigned long i_metasize;	/* size of non-data area */
+	unsigned long i_dataoffset;	/* from the start of fs */
+	struct inode vfs_inode;
+};
+
+static inline struct romfs_inode_info *ROMFS_I(struct inode *inode)
+{
+	return list_entry(inode, struct romfs_inode_info, vfs_inode);
+}
+
 static __s32
 romfs_checksum(void *data, int size)
 {
@@ -407,7 +418,7 @@
 	if (offset < inode->i_size) {
 		avail = inode->i_size-offset;
 		readlen = min_t(unsigned long, avail, PAGE_SIZE);
-		if (romfs_copyfrom(inode, buf, inode->u.romfs_i.i_dataoffset+offset, readlen) == readlen) {
+		if (romfs_copyfrom(inode, buf, ROMFS_I(inode)->i_dataoffset+offset, readlen) == readlen) {
 			if (readlen < PAGE_SIZE) {
 				memset(buf + readlen,0,PAGE_SIZE-readlen);
 			}
@@ -488,15 +499,15 @@
         else
                 ino = 0;
 
-        i->u.romfs_i.i_metasize = ino;
-        i->u.romfs_i.i_dataoffset = ino+(i->i_ino&ROMFH_MASK);
+        ROMFS_I(i)->i_metasize = ino;
+        ROMFS_I(i)->i_dataoffset = ino+(i->i_ino&ROMFH_MASK);
 
         /* Compute permissions */
         ino = romfs_modemap[nextfh & ROMFH_TYPE];
 	/* only "normal" files have ops */
 	switch (nextfh & ROMFH_TYPE) {
 		case 1:
-			i->i_size = i->u.romfs_i.i_metasize;
+			i->i_size = ROMFS_I(i)->i_metasize;
 			i->i_op = &romfs_dir_inode_operations;
 			i->i_fop = &romfs_dir_operations;
 			if (nextfh & ROMFH_EXEC)
@@ -540,6 +551,7 @@
 	owner:		THIS_MODULE,
 	name:		"romfs",
 	get_sb:		romfs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/smbfs/inode.c b/fs/smbfs/inode.c
--- a/fs/smbfs/inode.c	Fri Mar 15 17:51:01 2002
+++ b/fs/smbfs/inode.c	Fri Mar 15 17:51:01 2002
@@ -400,7 +400,7 @@
 static int
 smb_show_options(struct seq_file *s, struct vfsmount *m)
 {
-	struct smb_mount_data_kernel *mnt = m->mnt_sb->u.smbfs_sb.mnt;
+	struct smb_mount_data_kernel *mnt = SMB_SB(m->mnt_sb)->mnt;
 	int i;
 
 	for (i = 0; opts[i].name != NULL; i++)
@@ -435,7 +435,7 @@
 static void
 smb_put_super(struct super_block *sb)
 {
-	struct smb_sb_info *server = &(sb->u.smbfs_sb);
+	struct smb_sb_info *server = SMB_SB(sb);
 
 	if (server->sock_file) {
 		smb_dont_catch_keepalive(server);
@@ -457,11 +457,13 @@
 		unload_nls(server->local_nls);
 		server->local_nls = NULL;
 	}
+	sb->u.generic_sbp = NULL;
+	smb_kfree(server);
 }
 
 int smb_fill_super(struct super_block *sb, void *raw_data, int silent)
 {
-	struct smb_sb_info *server = &sb->u.smbfs_sb;
+	struct smb_sb_info *server;
 	struct smb_mount_data_kernel *mnt;
 	struct smb_mount_data *oldmnt;
 	struct inode *root_inode;
@@ -482,6 +484,13 @@
 	sb->s_magic = SMB_SUPER_MAGIC;
 	sb->s_op = &smb_sops;
 
+	server = smb_kmalloc(sizeof(struct smb_sb_info), GFP_KERNEL);
+	if (!server)
+		goto out_no_server;
+	sb->u.generic_sbp = server;
+	memset(server, 0, sizeof(struct smb_sb_info));
+
+	server->super_block = sb;
 	server->mnt = NULL;
 	server->sock_file = NULL;
 	init_MUTEX(&server->sem);
@@ -578,6 +587,8 @@
 out_no_mem:
 	if (!server->mnt)
 		printk(KERN_ERR "smb_fill_super: allocation failure\n");
+	sb->u.generic_sbp = NULL;
+	smb_kfree(server);
 	goto out_fail;
 out_wrong_data:
 	printk(KERN_ERR "smbfs: mount_data version %d is not supported\n", ver);
@@ -586,6 +597,9 @@
 	printk(KERN_ERR "smb_fill_super: missing data argument\n");
 out_fail:
 	return -EINVAL;
+out_no_server:
+	printk(KERN_ERR "smb_fill_super: cannot allocate struct smb_sb_info\n");
+	return -ENOMEM;
 }
 
 static int
@@ -719,6 +733,7 @@
 	owner:		THIS_MODULE,
 	name:		"smbfs",
 	get_sb:		smb_get_sb,
+	kill_sb:	kill_anon_super,
 };
 
 static int __init init_smb_fs(void)
diff -Nru a/fs/smbfs/proc.c b/fs/smbfs/proc.c
--- a/fs/smbfs/proc.c	Fri Mar 15 17:51:01 2002
+++ b/fs/smbfs/proc.c	Fri Mar 15 17:51:01 2002
@@ -2884,7 +2884,7 @@
 int
 smb_proc_dskattr(struct super_block *sb, struct statfs *attr)
 {
-	struct smb_sb_info *server = &(sb->u.smbfs_sb);
+	struct smb_sb_info *server = SMB_SB(sb);
 	int result;
 	char *p;
 	long unit;
diff -Nru a/fs/super.c b/fs/super.c
--- a/fs/super.c	Fri Mar 15 17:51:03 2002
+++ b/fs/super.c	Fri Mar 15 17:51:03 2002
@@ -297,22 +297,6 @@
 /* Superblock refcounting  */
 
 /**
- *	deactivate_super	-	turn an active reference into temporary
- *	@s: superblock to deactivate
- *
- *	Turns an active reference into temporary one.  Returns 0 if there are
- *	other active references, 1 if we had deactivated the last one.
- */
-static inline int deactivate_super(struct super_block *s)
-{
-	if (!atomic_dec_and_lock(&s->s_active, &sb_lock))
-		return 0;
-	s->s_count -= S_BIAS-1;
-	spin_unlock(&sb_lock);
-	return 1;
-}
-
-/**
  *	put_super	-	drop a temporary reference to superblock
  *	@s: superblock in question
  *
@@ -328,6 +312,28 @@
 }
 
 /**
+ *	deactivate_super	-	drop an active reference to superblock
+ *	@s: superblock to deactivate
+ *
+ *	Drops an active reference to superblock, acquiring a temprory one if
+ *	there is no active references left.  In that case we lock superblock,
+ *	tell fs driver to shut it down and drop the temporary reference we
+ *	had just acquired.
+ */
+void deactivate_super(struct super_block *s)
+{
+	struct file_system_type *fs = s->s_type;
+	if (atomic_dec_and_lock(&s->s_active, &sb_lock)) {
+		s->s_count -= S_BIAS-1;
+		spin_unlock(&sb_lock);
+		down_write(&s->s_umount);
+		fs->kill_sb(s);
+		put_filesystem(fs);
+		put_super(s);
+	}
+}
+
+/**
  *	grab_super	- acquire an active reference
  *	@s	- reference we are trying to make active
  *
@@ -376,19 +382,16 @@
 	get_filesystem(type);
 }
 
-static void put_anon_dev(kdev_t dev);
-
 /**
  *	remove_super	-	makes superblock unreachable
  *	@s:	superblock in question
  *
- *	Removes superblock from the lists, unlocks it and drop the reference
- *	@s should have no active references by that time and after
- *	remove_super() it's essentially	in rundown mode - all remaining
- *	references are temporary, no new reference of any sort are going
- *	to appear and all holders of temporary ones will eventually drop them.
- *	At that point superblock itself will be destroyed; all its contents
- *	is already gone.
+ *	Removes superblock from the lists, and unlocks it.  @s should have
+ *	no active references by that time and after remove_super() it's
+ *	essentially in rundown mode - all remaining references are temporary,
+ *	no new references of any sort are going to appear and all holders
+ *	of temporary ones will eventually drop them.  At that point superblock
+ *	itself will be destroyed; all its contents is already gone.
  */
 static void remove_super(struct super_block *s)
 {
@@ -397,7 +400,6 @@
 	list_del(&s->s_instances);
 	spin_unlock(&sb_lock);
 	up_write(&s->s_umount);
-	put_super(s);
 }
 
 static void generic_shutdown_super(struct super_block *sb)
@@ -434,33 +436,37 @@
 	remove_super(sb);
 }
 
-static void shutdown_super(struct super_block *sb)
-{
-	struct file_system_type *fs = sb->s_type;
-	kdev_t dev = sb->s_dev;
-	struct block_device *bdev = sb->s_bdev;
-
-	/* Need to clean after the sucker */
-	if (fs->fs_flags & FS_LITTER && sb->s_root)
-		d_genocide(sb->s_root);
-	generic_shutdown_super(sb);
-	if (bdev) {
-		bd_release(bdev);
-		blkdev_put(bdev, BDEV_FS);
-	} else
-		put_anon_dev(dev);
-}
-
-void kill_super(struct super_block *sb)
+struct super_block *sget(struct file_system_type *type,
+			int (*test)(struct super_block *,void *),
+			int (*set)(struct super_block *,void *),
+			void *data)
 {
-	struct file_system_type *fs = sb->s_type;
+	struct super_block *s = alloc_super();
+	struct list_head *p;
+	int err;
 
-	if (!deactivate_super(sb))
-		return;
+	if (!s)
+		return ERR_PTR(-ENOMEM);
 
-	down_write(&sb->s_umount);
-	shutdown_super(sb);
-	put_filesystem(fs);
+retry:
+	spin_lock(&sb_lock);
+	if (test) list_for_each(p, &type->fs_supers) {
+		struct super_block *old;
+		old = list_entry(p, struct super_block, s_instances);
+		if (!test(old, data))
+			continue;
+		if (!grab_super(old))
+			goto retry;
+		destroy_super(s);
+		return old;
+	}
+	err = set(s, data);
+	if (err) {
+		destroy_super(s);
+		return ERR_PTR(err);
+	}
+	insert_super(s, type);
+	return s;
 }
 
 struct vfsmount *alloc_vfsmnt(char *name);
@@ -615,72 +621,53 @@
 static unsigned long unnamed_dev_in_use[Max_anon/(8*sizeof(unsigned long))];
 static spinlock_t unnamed_dev_lock = SPIN_LOCK_UNLOCKED;/* protects the above */
 
-/**
- *	put_anon_dev	-	release anonymous device number.
- *	@dev:	device in question
- */
-static void put_anon_dev(kdev_t dev)
+int set_anon_super(struct super_block *s, void *data)
 {
+	int dev;
 	spin_lock(&unnamed_dev_lock);
-	clear_bit(minor(dev), unnamed_dev_in_use);
+	dev = find_first_zero_bit(unnamed_dev_in_use, Max_anon);
+	if (dev == Max_anon) {
+		spin_unlock(&unnamed_dev_lock);
+		return -EMFILE;
+	}
+	set_bit(dev, unnamed_dev_in_use);
 	spin_unlock(&unnamed_dev_lock);
+	s->s_dev = mk_kdev(0, dev);
+	return 0;
 }
 
-/**
- *	get_anon_super	-	allocate a superblock for non-device fs
- *	@type:		filesystem type
- *	@compare:	check if existing superblock is what we want
- *	@data:		argument for @compare.
- *
- *	get_anon_super is a helper for non-blockdevice filesystems.
- *	It either finds and returns one of the superblocks of given type
- *	(if it can find one that would satisfy caller) or creates a new
- *	one.  In the either case we return an active reference to superblock
- *	with ->s_umount locked.  If superblock is new it gets a new
- *	anonymous device allocated for it and is inserted into lists -
- *	other initialization is left to caller.
- *
- *	Rather than duplicating all that logics every time when
- *	we want something that doesn't fit "nodev" and "single" we pull
- *	the relevant code into common helper and let ->get_sb() call
- *	it.
- */
 struct super_block *get_anon_super(struct file_system_type *type,
 	int (*compare)(struct super_block *,void *), void *data)
 {
-	struct super_block *s = alloc_super();
-	int dev;
-	struct list_head *p;
-
-	if (!s)
-		return ERR_PTR(-ENOMEM);
-
+	return sget(type, compare, set_anon_super, data);
+}
+ 
+void kill_anon_super(struct super_block *sb)
+{
+	int slot = minor(sb->s_dev);
+	generic_shutdown_super(sb);
 	spin_lock(&unnamed_dev_lock);
-	dev = find_first_zero_bit(unnamed_dev_in_use, Max_anon);
-	if (dev == Max_anon) {
-		spin_unlock(&unnamed_dev_lock);
-		destroy_super(s);
-		return ERR_PTR(-EMFILE);
-	}
-	set_bit(dev, unnamed_dev_in_use);
+	clear_bit(slot, unnamed_dev_in_use);
 	spin_unlock(&unnamed_dev_lock);
+}
 
-retry:
-	spin_lock(&sb_lock);
-	if (compare) list_for_each(p, &type->fs_supers) {
-		struct super_block *old;
-		old = list_entry(p, struct super_block, s_instances);
-		if (!compare(old, data))
-			continue;
-		if (!grab_super(old))
-			goto retry;
-		destroy_super(s);
-		return old;
-	}
+void kill_litter_super(struct super_block *sb)
+{
+	if (sb->s_root)
+		d_genocide(sb->s_root);
+	kill_anon_super(sb);
+}
 
-	s->s_dev = mk_kdev(0, dev);
-	insert_super(s, type);
-	return s;
+static int set_bdev_super(struct super_block *s, void *data)
+{
+	s->s_bdev = data;
+	s->s_dev = to_kdev_t(s->s_bdev->bd_dev);
+	return 0;
+}
+
+static int test_bdev_super(struct super_block *s, void *data)
+{
+	return (void *)s->s_bdev == data;
 }
 
 struct super_block *get_sb_bdev(struct file_system_type *fs_type,
@@ -693,7 +680,6 @@
 	devfs_handle_t de;
 	struct super_block * s;
 	struct nameidata nd;
-	struct list_head *p;
 	kdev_t dev;
 	int error = 0;
 	mode_t mode = FMODE_READ; /* we always need it ;-) */
@@ -711,7 +697,9 @@
 	error = -EACCES;
 	if (nd.mnt->mnt_flags & MNT_NODEV)
 		goto out;
-	bd_acquire(inode);
+	error = bd_acquire(inode);
+	if (error)
+		goto out;
 	bdev = inode->i_bdev;
 	de = devfs_get_handle_from_inode (inode);
 	bdops = devfs_get_ops (de);         /*  Increments module use count  */
@@ -732,50 +720,29 @@
 	if (error)
 		goto out1;
 
-	error = -ENOMEM;
-	s = alloc_super();
-	if (!s)
-		goto out2;
-
-	error = -EBUSY;
-restart:
-	spin_lock(&sb_lock);
-
-	list_for_each(p, &fs_type->fs_supers) {
-		struct super_block *old = sb_entry(p);
-		if (old->s_bdev != bdev)
-			continue;
-		if (!grab_super(old))
-			goto restart;
-		destroy_super(s);
-		if ((flags ^ old->s_flags) & MS_RDONLY) {
-			up_write(&old->s_umount);
-			kill_super(old);
-			old = ERR_PTR(-EBUSY);
+	s = sget(fs_type, test_bdev_super, set_bdev_super, bdev);
+	if (s->s_root) {
+		if ((flags ^ s->s_flags) & MS_RDONLY) {
+			up_write(&s->s_umount);
+			deactivate_super(s);
+			s = ERR_PTR(-EBUSY);
 		}
 		bd_release(bdev);
 		blkdev_put(bdev, BDEV_FS);
-		path_release(&nd);
-		return old;
+	} else {
+		s->s_flags = flags;
+		strncpy(s->s_id, bdevname(dev), sizeof(s->s_id));
+		error = fill_super(s, data, flags & MS_VERBOSE ? 1 : 0);
+		if (error) {
+			up_write(&s->s_umount);
+			deactivate_super(s);
+			s = ERR_PTR(error);
+		} else
+			s->s_flags |= MS_ACTIVE;
 	}
-	s->s_bdev = bdev;
-	s->s_dev = dev;
-	insert_super(s, fs_type);
-	s->s_flags = flags;
-	strncpy(s->s_id, bdevname(dev), sizeof(s->s_id));
-	error = fill_super(s, data, flags & MS_VERBOSE ? 1 : 0);
-	if (error)
-		goto failed;
-	s->s_flags |= MS_ACTIVE;
 	path_release(&nd);
 	return s;
 
-failed:
-	up_write(&s->s_umount);
-	kill_super(s);
-	goto out;
-out2:
-	bd_release(bdev);
 out1:
 	blkdev_put(bdev, BDEV_FS);
 out:
@@ -783,6 +750,14 @@
 	return ERR_PTR(error);
 }
 
+void kill_block_super(struct super_block *sb)
+{
+	struct block_device *bdev = sb->s_bdev;
+	generic_shutdown_super(sb);
+	bd_release(bdev);
+	blkdev_put(bdev, BDEV_FS);
+}
+
 struct super_block *get_sb_nodev(struct file_system_type *fs_type,
 	int flags, void *data,
 	int (*fill_super)(struct super_block *, void *, int))
@@ -798,7 +773,7 @@
 	error = fill_super(s, data, flags & MS_VERBOSE ? 1 : 0);
 	if (error) {
 		up_write(&s->s_umount);
-		kill_super(s);
+		deactivate_super(s);
 		return ERR_PTR(error);
 	}
 	s->s_flags |= MS_ACTIVE;
@@ -824,7 +799,7 @@
 		error = fill_super(s, data, flags & MS_VERBOSE ? 1 : 0);
 		if (error) {
 			up_write(&s->s_umount);
-			kill_super(s);
+			deactivate_super(s);
 			return ERR_PTR(error);
 		}
 		s->s_flags |= MS_ACTIVE;
diff -Nru a/fs/sysv/super.c b/fs/sysv/super.c
--- a/fs/sysv/super.c	Fri Mar 15 17:51:01 2002
+++ b/fs/sysv/super.c	Fri Mar 15 17:51:01 2002
@@ -490,6 +490,7 @@
 	owner:		THIS_MODULE,
 	name:		"sysv",
 	get_sb:		sysv_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
@@ -497,6 +498,7 @@
 	owner:		THIS_MODULE,
 	name:		"v7",
 	get_sb:		v7_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/udf/balloc.c b/fs/udf/balloc.c
--- a/fs/udf/balloc.c	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/balloc.c	Fri Mar 15 17:51:02 2002
@@ -15,7 +15,7 @@
  *		ftp://prep.ai.mit.edu/pub/gnu/GPL
  *	Each contributing author retains all rights to their own work.
  *
- *  (C) 1999-2000 Ben Fennema
+ *  (C) 1999-2001 Ben Fennema
  *  (C) 1999 Stelias Computing Inc
  *
  * HISTORY
@@ -25,11 +25,9 @@
  */
 
 #include "udfdecl.h"
-#include <linux/fs.h>
+
 #include <linux/locks.h>
 #include <linux/quotaops.h>
-#include <linux/udf_fs.h>
-
 #include <asm/bitops.h>
 
 #include "udf_i.h"
@@ -44,15 +42,15 @@
 #define leBPL_to_cpup(x) leNUM_to_cpup(BITS_PER_LONG, x)
 #define leNUM_to_cpup(x,y) xleNUM_to_cpup(x,y)
 #define xleNUM_to_cpup(x,y) (le ## x ## _to_cpup(y))
-#define UintBPL Uint(BITS_PER_LONG)
-#define Uint(x) xUint(x)
-#define xUint(x) Uint ## x
+#define uintBPL_t uint(BITS_PER_LONG)
+#define uint(x) xuint(x)
+#define xuint(x) uint ## x ## _t
 
 extern inline int find_next_one_bit (void * addr, int size, int offset)
 {
-	UintBPL * p = ((UintBPL *) addr) + (offset / BITS_PER_LONG);
-	UintBPL result = offset & ~(BITS_PER_LONG-1);
-	UintBPL tmp;
+	uintBPL_t * p = ((uintBPL_t *) addr) + (offset / BITS_PER_LONG);
+	uintBPL_t result = offset & ~(BITS_PER_LONG-1);
+	uintBPL_t tmp;
 
 	if (offset >= size)
 		return size;
@@ -147,7 +145,7 @@
 
 static void udf_bitmap_free_blocks(struct super_block * sb,
 	struct inode * inode,
-	struct udf_bitmap *bitmap, lb_addr bloc, Uint32 offset, Uint32 count)
+	struct udf_bitmap *bitmap, lb_addr bloc, uint32_t offset, uint32_t count)
 {
 	struct buffer_head * bh = NULL;
 	unsigned long block;
@@ -167,7 +165,7 @@
 		goto error_return;
 	}
 
-	block = bloc.logicalBlockNum + offset + (sizeof(struct SpaceBitmapDesc) << 3);
+	block = bloc.logicalBlockNum + offset + (sizeof(struct spaceBitmapDesc) << 3);
 
 do_more:
 	overflow = 0;
@@ -222,8 +220,8 @@
 
 static int udf_bitmap_prealloc_blocks(struct super_block * sb,
 	struct inode * inode,
-	struct udf_bitmap *bitmap, Uint16 partition, Uint32 first_block,
-	Uint32 block_count)
+	struct udf_bitmap *bitmap, uint16_t partition, uint32_t first_block,
+	uint32_t block_count)
 {
 	int alloc_count = 0;
 	int bit, block, block_group, group_start;
@@ -240,10 +238,10 @@
 
 repeat:
 	nr_groups = (UDF_SB_PARTLEN(sb, partition) +
-		(sizeof(struct SpaceBitmapDesc) << 3) + (sb->s_blocksize * 8) - 1) / (sb->s_blocksize * 8);
-	block = first_block + (sizeof(struct SpaceBitmapDesc) << 3);
+		(sizeof(struct spaceBitmapDesc) << 3) + (sb->s_blocksize * 8) - 1) / (sb->s_blocksize * 8);
+	block = first_block + (sizeof(struct spaceBitmapDesc) << 3);
 	block_group = block >> (sb->s_blocksize_bits + 3);
-	group_start = block_group ? 0 : sizeof(struct SpaceBitmapDesc);
+	group_start = block_group ? 0 : sizeof(struct spaceBitmapDesc);
 
 	bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
 	if (bitmap_nr < 0)
@@ -286,7 +284,7 @@
 
 static int udf_bitmap_new_block(struct super_block * sb,
 	struct inode * inode,
-	struct udf_bitmap *bitmap, Uint16 partition, Uint32 goal, int *err)
+	struct udf_bitmap *bitmap, uint16_t partition, uint32_t goal, int *err)
 {
 	int newbit, bit=0, block, block_group, group_start;
 	int end_goal, nr_groups, bitmap_nr, i;
@@ -302,9 +300,9 @@
 		goal = 0;
 
 	nr_groups = bitmap->s_nr_groups;
-	block = goal + (sizeof(struct SpaceBitmapDesc) << 3);
+	block = goal + (sizeof(struct spaceBitmapDesc) << 3);
 	block_group = block >> (sb->s_blocksize_bits + 3);
-	group_start = block_group ? 0 : sizeof(struct SpaceBitmapDesc);
+	group_start = block_group ? 0 : sizeof(struct spaceBitmapDesc);
 
 	bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
 	if (bitmap_nr < 0)
@@ -344,7 +342,7 @@
 		block_group ++;
 		if (block_group >= nr_groups)
 			block_group = 0;
-		group_start = block_group ? 0 : sizeof(struct SpaceBitmapDesc);
+		group_start = block_group ? 0 : sizeof(struct spaceBitmapDesc);
 
 		bitmap_nr = load_block_bitmap(sb, bitmap, block_group);
 		if (bitmap_nr < 0)
@@ -397,7 +395,7 @@
 	}
 
 	newblock = bit + (block_group << (sb->s_blocksize_bits + 3)) -
-		(sizeof(struct SpaceBitmapDesc) << 3);
+		(sizeof(struct spaceBitmapDesc) << 3);
 
 	if (!udf_clear_bit(bit, bh->b_data))
 	{
@@ -426,13 +424,13 @@
 
 static void udf_table_free_blocks(struct super_block * sb,
 	struct inode * inode,
-	struct inode * table, lb_addr bloc, Uint32 offset, Uint32 count)
+	struct inode * table, lb_addr bloc, uint32_t offset, uint32_t count)
 {
-	Uint32 start, end;
-	Uint32 nextoffset, oextoffset, elen;
+	uint32_t start, end;
+	uint32_t nextoffset, oextoffset, elen;
 	lb_addr nbloc, obloc, eloc;
 	struct buffer_head *obh, *nbh;
-	Sint8 etype;
+	int8_t etype;
 	int i;
 
 	lock_super(sb);
@@ -459,7 +457,7 @@
 	start = bloc.logicalBlockNum + offset;
 	end = bloc.logicalBlockNum + offset + count - 1;
 
-	oextoffset = nextoffset = sizeof(struct UnallocatedSpaceEntry);
+	oextoffset = nextoffset = sizeof(struct unallocSpaceEntry);
 	elen = 0;
 	obloc = nbloc = UDF_I_LOCATION(table);
 
@@ -538,15 +536,15 @@
 		int adsize;
 		short_ad *sad = NULL;
 		long_ad *lad = NULL;
-		struct AllocExtDesc *aed;
+		struct allocExtDesc *aed;
 
 		eloc.logicalBlockNum = start;
-		elen = (EXTENT_RECORDED_ALLOCATED << 30) |
+		elen = EXT_RECORDED_ALLOCATED |
 			(count << sb->s_blocksize_bits);
 
-		if (UDF_I_ALLOCTYPE(table) == ICB_FLAG_AD_SHORT)
+		if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_SHORT)
 			adsize = sizeof(short_ad);
-		else if (UDF_I_ALLOCTYPE(table) == ICB_FLAG_AD_LONG)
+		else if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_LONG)
 			adsize = sizeof(long_ad);
 		else
 		{
@@ -576,27 +574,27 @@
 				udf_release_data(obh);
 				goto error_return;
 			}
-			aed = (struct AllocExtDesc *)(nbh->b_data);
+			aed = (struct allocExtDesc *)(nbh->b_data);
 			aed->previousAllocExtLocation = cpu_to_le32(obloc.logicalBlockNum);
 			if (nextoffset + adsize > sb->s_blocksize)
 			{
 				loffset = nextoffset;
 				aed->lengthAllocDescs = cpu_to_le32(adsize);
 				sptr = (obh)->b_data + nextoffset - adsize;
-				dptr = nbh->b_data + sizeof(struct AllocExtDesc);
+				dptr = nbh->b_data + sizeof(struct allocExtDesc);
 				memcpy(dptr, sptr, adsize);
-				nextoffset = sizeof(struct AllocExtDesc) + adsize;
+				nextoffset = sizeof(struct allocExtDesc) + adsize;
 			}
 			else
 			{
 				loffset = nextoffset + adsize;
 				aed->lengthAllocDescs = cpu_to_le32(0);
 				sptr = (obh)->b_data + nextoffset;
-				nextoffset = sizeof(struct AllocExtDesc);
+				nextoffset = sizeof(struct allocExtDesc);
 	
 				if (memcmp(&UDF_I_LOCATION(table), &obloc, sizeof(lb_addr)))
 				{
-					aed = (struct AllocExtDesc *)(obh)->b_data;
+					aed = (struct allocExtDesc *)(obh)->b_data;
 					aed->lengthAllocDescs =
 						cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
 				}
@@ -606,24 +604,28 @@
 					mark_inode_dirty(table);
 				}
 			}
-			udf_new_tag(nbh->b_data, TID_ALLOC_EXTENT_DESC, 2, 1,
-				nbloc.logicalBlockNum, sizeof(tag));
+			if (UDF_SB_UDFREV(sb) >= 0x0200)
+				udf_new_tag(nbh->b_data, TAG_IDENT_AED, 3, 1,
+					nbloc.logicalBlockNum, sizeof(tag));
+			else
+				udf_new_tag(nbh->b_data, TAG_IDENT_AED, 2, 1,
+					nbloc.logicalBlockNum, sizeof(tag));
 			switch (UDF_I_ALLOCTYPE(table))
 			{
-				case ICB_FLAG_AD_SHORT:
+				case ICBTAG_FLAG_AD_SHORT:
 				{
 					sad = (short_ad *)sptr;
 					sad->extLength = cpu_to_le32(
-						EXTENT_NEXT_EXTENT_ALLOCDECS << 30 |
+						EXT_NEXT_EXTENT_ALLOCDECS |
 						sb->s_blocksize);
 					sad->extPosition = cpu_to_le32(nbloc.logicalBlockNum);
 					break;
 				}
-				case ICB_FLAG_AD_LONG:
+				case ICBTAG_FLAG_AD_LONG:
 				{
 					lad = (long_ad *)sptr;
 					lad->extLength = cpu_to_le32(
-						EXTENT_NEXT_EXTENT_ALLOCDECS << 30 |
+						EXT_NEXT_EXTENT_ALLOCDECS |
 						sb->s_blocksize);
 					lad->extLocation = cpu_to_lelb(nbloc);
 					break;
@@ -644,7 +646,7 @@
 			}
 			else
 			{
-				aed = (struct AllocExtDesc *)nbh->b_data;
+				aed = (struct allocExtDesc *)nbh->b_data;
 				aed->lengthAllocDescs =
 					cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
 				udf_update_tag(nbh->b_data, nextoffset);
@@ -664,28 +666,28 @@
 
 static int udf_table_prealloc_blocks(struct super_block * sb,
 	struct inode * inode,
-	struct inode *table, Uint16 partition, Uint32 first_block,
-	Uint32 block_count)
+	struct inode *table, uint16_t partition, uint32_t first_block,
+	uint32_t block_count)
 {
 	int alloc_count = 0;
-	Uint32 extoffset, elen, adsize;
+	uint32_t extoffset, elen, adsize;
 	lb_addr bloc, eloc;
 	struct buffer_head *bh;
-	Sint8 etype = -1;
+	int8_t etype = -1;
 
 	if (first_block < 0 || first_block >= UDF_SB_PARTLEN(sb, partition))
 		return 0;
 
-	if (UDF_I_ALLOCTYPE(table) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_SHORT)
 		adsize = sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(table) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_LONG)
 		adsize = sizeof(long_ad);
 	else
 		return 0;
 
 	lock_super(sb);
 
-	extoffset = sizeof(struct UnallocatedSpaceEntry);
+	extoffset = sizeof(struct unallocSpaceEntry);
 	bloc = UDF_I_LOCATION(table);
 
 	bh = udf_tread(sb, udf_get_lb_pblock(sb, bloc, 0));
@@ -734,20 +736,20 @@
 
 static int udf_table_new_block(struct super_block * sb,
 	struct inode * inode,
-	struct inode *table, Uint16 partition, Uint32 goal, int *err)
+	struct inode *table, uint16_t partition, uint32_t goal, int *err)
 {
-	Uint32 spread = 0xFFFFFFFF, nspread;
-	Uint32 newblock = 0, adsize;
-	Uint32 extoffset, goal_extoffset, elen, goal_elen = 0;
+	uint32_t spread = 0xFFFFFFFF, nspread = 0xFFFFFFFF;
+	uint32_t newblock = 0, adsize;
+	uint32_t extoffset, goal_extoffset, elen, goal_elen = 0;
 	lb_addr bloc, goal_bloc, eloc, goal_eloc;
 	struct buffer_head *bh, *goal_bh;
-	Sint8 etype;
+	int8_t etype;
 
 	*err = -ENOSPC;
 
-	if (UDF_I_ALLOCTYPE(table) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_SHORT)
 		adsize = sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(table) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(table) == ICBTAG_FLAG_AD_LONG)
 		adsize = sizeof(long_ad);
 	else
 		return newblock;
@@ -757,12 +759,13 @@
 	if (goal < 0 || goal >= UDF_SB_PARTLEN(sb, partition))
 		goal = 0;
 
-	/* We search for the closest matching block to goal. If we find a exact hit,	   we stop. Otherwise we keep going till we run out of extents.
+	/* We search for the closest matching block to goal. If we find a exact hit,
+	   we stop. Otherwise we keep going till we run out of extents.
 	   We store the buffer_head, bloc, and extoffset of the current closest
 	   match and use that when we are done.
 	*/
 
-	extoffset = sizeof(struct UnallocatedSpaceEntry);
+	extoffset = sizeof(struct unallocSpaceEntry);
 	bloc = UDF_I_LOCATION(table);
 
 	goal_bh = bh = udf_tread(sb, udf_get_lb_pblock(sb, bloc, 0));
@@ -845,9 +848,9 @@
 
 inline void udf_free_blocks(struct super_block * sb,
 	struct inode * inode,
-	lb_addr bloc, Uint32 offset, Uint32 count)
+	lb_addr bloc, uint32_t offset, uint32_t count)
 {
-	Uint16 partition = bloc.partitionReferenceNum;
+	uint16_t partition = bloc.partitionReferenceNum;
 
 	if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_BITMAP)
 	{
@@ -879,7 +882,7 @@
 
 inline int udf_prealloc_blocks(struct super_block * sb,
 	struct inode * inode,
-	Uint16 partition, Uint32 first_block, Uint32 block_count)
+	uint16_t partition, uint32_t first_block, uint32_t block_count)
 {
 	if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_BITMAP)
 	{
@@ -911,7 +914,7 @@
 
 inline int udf_new_block(struct super_block * sb,
 	struct inode * inode,
-	Uint16 partition, Uint32 goal, int *err)
+	uint16_t partition, uint32_t goal, int *err)
 {
 	if (UDF_SB_PARTFLAGS(sb, partition) & UDF_PART_FLAG_UNALLOC_BITMAP)
 	{
diff -Nru a/fs/udf/crc.c b/fs/udf/crc.c
--- a/fs/udf/crc.c	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/crc.c	Fri Mar 15 17:51:02 2002
@@ -28,7 +28,7 @@
 
 #include "udfdecl.h"
 
-static Uint16 crc_table[256] = {
+static uint16_t crc_table[256] = {
 	0x0000U, 0x1021U, 0x2042U, 0x3063U, 0x4084U, 0x50a5U, 0x60c6U, 0x70e7U,
 	0x8108U, 0x9129U, 0xa14aU, 0xb16bU, 0xc18cU, 0xd1adU, 0xe1ceU, 0xf1efU,
 	0x1231U, 0x0210U, 0x3273U, 0x2252U, 0x52b5U, 0x4294U, 0x72f7U, 0x62d6U,
@@ -84,8 +84,8 @@
  *	July 21, 1997 - Andrew E. Mileski
  *	Adapted from OSTA-UDF(tm) 1.50 standard.
  */
-extern Uint16
-udf_crc(Uint8 *data, Uint32 size, Uint16 crc)
+extern uint16_t
+udf_crc(uint8_t *data, uint32_t size, uint16_t crc)
 {
 	while (size--)
 		crc = crc_table[(crc >> 8 ^ *(data++)) & 0xffU] ^ (crc << 8);
diff -Nru a/fs/udf/dir.c b/fs/udf/dir.c
--- a/fs/udf/dir.c	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/dir.c	Fri Mar 15 17:51:02 2002
@@ -15,14 +15,14 @@
  *		ftp://prep.ai.mit.edu/pub/gnu/GPL
  *	Each contributing author retains all rights to their own work.
  *
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *
  * HISTORY
  *
  *  10/05/98 dgb  Split directory operations into it's own file
  *                Implemented directory reads via do_udf_readdir
  *  10/06/98      Made directory operations work!
- *  11/17/98      Rewrote directory to support ICB_FLAG_AD_LONG
+ *  11/17/98      Rewrote directory to support ICBTAG_FLAG_AD_LONG
  *  11/25/98 blf  Rewrote directory handling (readdir+lookup) to support reading
  *                across blocks.
  *  12/12/98      Split out the lookup code to namei.c. bulk of directory
@@ -31,16 +31,13 @@
 
 #include "udfdecl.h"
 
-#if defined(__linux__) && defined(__KERNEL__)
-#include <linux/version.h>
-#include "udf_i.h"
-#include "udf_sb.h"
 #include <linux/string.h>
 #include <linux/errno.h>
 #include <linux/mm.h>
 #include <linux/slab.h>
-#include <linux/udf_fs.h>
-#endif
+
+#include "udf_i.h"
+#include "udf_sb.h"
 
 /* Prototypes for file operations */
 static int udf_readdir(struct file *, void *, filldir_t);
@@ -102,19 +99,19 @@
 do_udf_readdir(struct inode * dir, struct file *filp, filldir_t filldir, void *dirent)
 {
 	struct udf_fileident_bh fibh;
-	struct FileIdentDesc *fi=NULL;
-	struct FileIdentDesc cfi;
+	struct fileIdentDesc *fi=NULL;
+	struct fileIdentDesc cfi;
 	int block, iblock;
 	loff_t nf_pos = filp->f_pos - 1;
 	int flen;
 	char fname[255];
 	char *nameptr;
-	Uint16 liu;
-	Uint8 lfi;
+	uint16_t liu;
+	uint8_t lfi;
 	loff_t size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
 	struct buffer_head * bh = NULL, * tmp, * bha[16];
 	lb_addr bloc, eloc;
-	Uint32 extoffset, elen, offset;
+	uint32_t extoffset, elen, offset;
 	int i, num;
 	unsigned int dt_type;
 
@@ -126,15 +123,15 @@
 
 	fibh.soffset = fibh.eoffset = (nf_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
 	if (inode_bmap(dir, nf_pos >> (dir->i_sb->s_blocksize_bits - 2),
-		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == EXTENT_RECORDED_ALLOCATED)
+		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == (EXT_RECORDED_ALLOCATED >> 30))
 	{
 		offset >>= dir->i_sb->s_blocksize_bits;
 		block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
 		if ((++offset << dir->i_sb->s_blocksize_bits) < elen)
 		{
-			if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_SHORT)
+			if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
 				extoffset -= sizeof(short_ad);
-			else if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_LONG)
+			else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
 				extoffset -= sizeof(long_ad);
 		}
 		else
@@ -198,7 +195,7 @@
 		{
 			int poffset;	/* Unpaded ending offset */
 
-			poffset = fibh.soffset + sizeof(struct FileIdentDesc) + liu + lfi;
+			poffset = fibh.soffset + sizeof(struct fileIdentDesc) + liu + lfi;
 
 			if (poffset >= lfi)
 				nameptr = (char *)(fibh.ebh->b_data + poffset - lfi);
@@ -210,19 +207,19 @@
 			}
 		}
 
-		if ( (cfi.fileCharacteristics & FILE_DELETED) != 0 )
+		if ( (cfi.fileCharacteristics & FID_FILE_CHAR_DELETED) != 0 )
 		{
 			if ( !UDF_QUERY_FLAG(dir->i_sb, UDF_FLAG_UNDELETE) )
 				continue;
 		}
 		
-		if ( (cfi.fileCharacteristics & FILE_HIDDEN) != 0 )
+		if ( (cfi.fileCharacteristics & FID_FILE_CHAR_HIDDEN) != 0 )
 		{
 			if ( !UDF_QUERY_FLAG(dir->i_sb, UDF_FLAG_UNHIDE) )
 				continue;
 		}
 
-		if ( cfi.fileCharacteristics & FILE_PARENT )
+		if ( cfi.fileCharacteristics & FID_FILE_CHAR_PARENT )
 		{
 			iblock = parent_ino(filp->f_dentry);
 			flen = 2;
diff -Nru a/fs/udf/directory.c b/fs/udf/directory.c
--- a/fs/udf/directory.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/directory.c	Fri Mar 15 17:51:01 2002
@@ -18,33 +18,20 @@
 
 #include "udfdecl.h"
 
-#if defined(__linux__) && defined(__KERNEL__)
-
 #include <linux/fs.h>
 #include <linux/string.h>
-#include <linux/udf_fs.h>
-
-#else
-
-#include <sys/types.h>
-#include <stdio.h>
-#include <unistd.h>
-
-#endif
-
-#ifdef __KERNEL__
 
-Uint8 * udf_filead_read(struct inode *dir, Uint8 *tmpad, Uint8 ad_size,
+uint8_t * udf_filead_read(struct inode *dir, uint8_t *tmpad, uint8_t ad_size,
 	lb_addr fe_loc, int *pos, int *offset, struct buffer_head **bh, int *error)
 {
 	int loffset = *offset;
 	int block;
-	Uint8 *ad;
+	uint8_t *ad;
 	int remainder;
 
 	*error = 0;
 
-	ad = (Uint8 *)(*bh)->b_data + *offset;
+	ad = (uint8_t *)(*bh)->b_data + *offset;
 	*offset += ad_size;
 
 	if (!ad)
@@ -68,7 +55,7 @@
 		ad = tmpad;
 
 		remainder = dir->i_sb->s_blocksize - loffset;
-		memcpy((Uint8 *)ad, (*bh)->b_data + loffset, remainder);
+		memcpy((uint8_t *)ad, (*bh)->b_data + loffset, remainder);
 
 		udf_release_data(*bh);
 		block = udf_get_lb_pblock(dir->i_sb, fe_loc, ++*pos);
@@ -77,21 +64,21 @@
 		if (!((*bh) = udf_tread(dir->i_sb, block)))
 			return NULL;
 
-		memcpy((Uint8 *)ad + remainder, (*bh)->b_data, ad_size - remainder);
+		memcpy((uint8_t *)ad + remainder, (*bh)->b_data, ad_size - remainder);
 		*offset = ad_size - remainder;
 	}
 	return ad;
 }
 
-struct FileIdentDesc *
+struct fileIdentDesc *
 udf_fileident_read(struct inode *dir, loff_t *nf_pos,
 	struct udf_fileident_bh *fibh,
-	struct FileIdentDesc *cfi,
-	lb_addr *bloc, Uint32 *extoffset, 
-	lb_addr *eloc, Uint32 *elen,
-	Uint32 *offset, struct buffer_head **bh)
+	struct fileIdentDesc *cfi,
+	lb_addr *bloc, uint32_t *extoffset, 
+	lb_addr *eloc, uint32_t *elen,
+	uint32_t *offset, struct buffer_head **bh)
 {
-	struct FileIdentDesc *fi;
+	struct fileIdentDesc *fi;
 	int i, num, block;
 	struct buffer_head * tmp, * bha[16];
 
@@ -102,7 +89,7 @@
 		int lextoffset = *extoffset;
 
 		if (udf_next_aext(dir, bloc, extoffset, eloc, elen, bh, 1) !=
-			EXTENT_RECORDED_ALLOCATED)
+			(EXT_RECORDED_ALLOCATED >> 30))
 		{
 			return NULL;
 		}
@@ -159,14 +146,14 @@
 
 	if (fibh->eoffset <= dir->i_sb->s_blocksize)
 	{
-		memcpy((Uint8 *)cfi, (Uint8 *)fi, sizeof(struct FileIdentDesc));
+		memcpy((uint8_t *)cfi, (uint8_t *)fi, sizeof(struct fileIdentDesc));
 	}
 	else if (fibh->eoffset > dir->i_sb->s_blocksize)
 	{
 		int lextoffset = *extoffset;
 
 		if (udf_next_aext(dir, bloc, extoffset, eloc, elen, bh, 1) !=
-			EXTENT_RECORDED_ALLOCATED)
+			(EXT_RECORDED_ALLOCATED >> 30))
 		{
 			return NULL;
 		}
@@ -186,15 +173,15 @@
 		if (!(fibh->ebh = udf_tread(dir->i_sb, block)))
 			return NULL;
 
-		if (sizeof(struct FileIdentDesc) > - fibh->soffset)
+		if (sizeof(struct fileIdentDesc) > - fibh->soffset)
 		{
 			int fi_len;
 
-			memcpy((Uint8 *)cfi, (Uint8 *)fi, - fibh->soffset);
-			memcpy((Uint8 *)cfi - fibh->soffset, fibh->ebh->b_data,
-				sizeof(struct FileIdentDesc) + fibh->soffset);
+			memcpy((uint8_t *)cfi, (uint8_t *)fi, - fibh->soffset);
+			memcpy((uint8_t *)cfi - fibh->soffset, fibh->ebh->b_data,
+				sizeof(struct fileIdentDesc) + fibh->soffset);
 
-			fi_len = (sizeof(struct FileIdentDesc) + cfi->lengthFileIdent +
+			fi_len = (sizeof(struct fileIdentDesc) + cfi->lengthFileIdent +
 				le16_to_cpu(cfi->lengthOfImpUse) + 3) & ~3;
 
 			*nf_pos += ((fi_len - (fibh->eoffset - fibh->soffset)) >> 2);
@@ -202,25 +189,22 @@
 		}
 		else
 		{
-			memcpy((Uint8 *)cfi, (Uint8 *)fi, sizeof(struct FileIdentDesc));
+			memcpy((uint8_t *)cfi, (uint8_t *)fi, sizeof(struct fileIdentDesc));
 		}
 	}
 	return fi;
 }
-#endif
 
-struct FileIdentDesc * 
+struct fileIdentDesc * 
 udf_get_fileident(void * buffer, int bufsize, int * offset)
 {
-	struct FileIdentDesc *fi;
+	struct fileIdentDesc *fi;
 	int lengthThisIdent;
-	Uint8 * ptr;
+	uint8_t * ptr;
 	int padlen;
 
 	if ( (!buffer) || (!offset) ) {
-#ifdef __KERNEL__
 		udf_debug("invalidparms\n, buffer=%p, offset=%p\n", buffer, offset);
-#endif
 		return NULL;
 	}
 
@@ -229,23 +213,21 @@
 	if ( (*offset > 0) && (*offset < bufsize) ) {
 		ptr += *offset;
 	}
-	fi=(struct FileIdentDesc *)ptr;
-	if (le16_to_cpu(fi->descTag.tagIdent) != TID_FILE_IDENT_DESC)
+	fi=(struct fileIdentDesc *)ptr;
+	if (le16_to_cpu(fi->descTag.tagIdent) != TAG_IDENT_FID)
 	{
-#ifdef __KERNEL__
-		udf_debug("0x%x != TID_FILE_IDENT_DESC\n",
+		udf_debug("0x%x != TAG_IDENT_FID\n",
 			le16_to_cpu(fi->descTag.tagIdent));
 		udf_debug("offset: %u sizeof: %lu bufsize: %u\n",
-			*offset, (unsigned long)sizeof(struct FileIdentDesc), bufsize);
-#endif
+			*offset, (unsigned long)sizeof(struct fileIdentDesc), bufsize);
 		return NULL;
 	}
-	if ( (*offset + sizeof(struct FileIdentDesc)) > bufsize )
+	if ( (*offset + sizeof(struct fileIdentDesc)) > bufsize )
 	{
-		lengthThisIdent = sizeof(struct FileIdentDesc);
+		lengthThisIdent = sizeof(struct fileIdentDesc);
 	}
 	else
-		lengthThisIdent = sizeof(struct FileIdentDesc) +
+		lengthThisIdent = sizeof(struct fileIdentDesc) +
 			fi->lengthFileIdent + le16_to_cpu(fi->lengthOfImpUse);
 
 	/* we need to figure padding, too! */
@@ -261,29 +243,25 @@
 udf_get_fileextent(void * buffer, int bufsize, int * offset)
 {
 	extent_ad * ext;
-	struct FileEntry *fe;
-	Uint8 * ptr;
+	struct fileEntry *fe;
+	uint8_t * ptr;
 
 	if ( (!buffer) || (!offset) )
 	{
-#ifdef __KERNEL__
 		printk(KERN_ERR "udf: udf_get_fileextent() invalidparms\n");
-#endif
 		return NULL;
 	}
 
-	fe = (struct FileEntry *)buffer;
+	fe = (struct fileEntry *)buffer;
 
-	if ( le16_to_cpu(fe->descTag.tagIdent) != TID_FILE_ENTRY )
+	if ( le16_to_cpu(fe->descTag.tagIdent) != TAG_IDENT_FE )
 	{
-#ifdef __KERNEL__
-		udf_debug("0x%x != TID_FILE_ENTRY\n",
+		udf_debug("0x%x != TAG_IDENT_FE\n",
 			le16_to_cpu(fe->descTag.tagIdent));
-#endif
 		return NULL;
 	}
 
-	ptr=(Uint8 *)(fe->extendedAttr) + le32_to_cpu(fe->lengthExtendedAttr);
+	ptr=(uint8_t *)(fe->extendedAttr) + le32_to_cpu(fe->lengthExtendedAttr);
 
 	if ( (*offset > 0) && (*offset < le32_to_cpu(fe->lengthAllocDescs)) )
 	{
@@ -300,17 +278,15 @@
 udf_get_fileshortad(void * buffer, int maxoffset, int *offset, int inc)
 {
 	short_ad * sa;
-	Uint8 * ptr;
+	uint8_t * ptr;
 
 	if ( (!buffer) || (!offset) )
 	{
-#ifdef __KERNEL__
 		printk(KERN_ERR "udf: udf_get_fileshortad() invalidparms\n");
-#endif
 		return NULL;
 	}
 
-	ptr = (Uint8 *)buffer;
+	ptr = (uint8_t *)buffer;
 
 	if ( (*offset > 0) && (*offset < maxoffset) )
 		ptr += *offset;
@@ -328,17 +304,15 @@
 udf_get_filelongad(void * buffer, int maxoffset, int * offset, int inc)
 {
 	long_ad * la;
-	Uint8 * ptr;
+	uint8_t * ptr;
 
 	if ( (!buffer) || !(offset) ) 
 	{
-#ifdef __KERNEL__
 		printk(KERN_ERR "udf: udf_get_filelongad() invalidparms\n");
-#endif
 		return NULL;
 	}
 
-	ptr = (Uint8 *)buffer;
+	ptr = (uint8_t *)buffer;
 
 	if ( (*offset > 0) && (*offset < maxoffset) )
 		ptr += *offset;
diff -Nru a/fs/udf/ecma_167.h b/fs/udf/ecma_167.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/udf/ecma_167.h	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,822 @@
+/*
+ * ecma_167.h
+ *
+ * This file is based on ECMA-167 3rd edition (June 1997)
+ * http://www.ecma.ch
+ *
+ * Copyright (c) 2001-2002  Ben Fennema <bfennema@falcon.csc.calpoly.edu>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+
+#ifndef _ECMA_167_H
+#define _ECMA_167_H 1
+
+/* Character set specification (ECMA 167r3 1/7.2.1) */
+typedef struct
+{
+	uint8_t		charSetType;
+	uint8_t		charSetInfo[63];
+} __attribute__ ((packed)) charspec;
+
+/* Character Set Type (ECMA 167r3 1/7.2.1.1) */
+#define CHARSPEC_TYPE_CS0		0x00	/* (1/7.2.2) */
+#define CHARSPEC_TYPE_CS1		0x01	/* (1/7.2.3) */
+#define CHARSPEC_TYPE_CS2		0x02	/* (1/7.2.4) */
+#define CHARSPEC_TYPE_CS3		0x03	/* (1/7.2.5) */
+#define CHARSPEC_TYPE_CS4		0x04	/* (1/7.2.6) */
+#define CHARSPEC_TYPE_CS5		0x05	/* (1/7.2.7) */
+#define CHARSPEC_TYPE_CS6		0x06	/* (1/7.2.8) */
+#define CHARSPEC_TYPE_CS7		0x07	/* (1/7.2.9) */
+#define CHARSPEC_TYPE_CS8		0x08	/* (1/7.2.10) */
+
+typedef uint8_t		dstring;
+
+/* Timestamp (ECMA 167r3 1/7.3) */
+typedef struct
+{
+	uint16_t	typeAndTimezone;
+	int16_t		year;
+	uint8_t		month;
+	uint8_t		day;
+	uint8_t		hour;
+	uint8_t		minute;
+	uint8_t		second;
+	uint8_t		centiseconds;
+	uint8_t		hundredsOfMicroseconds;
+	uint8_t		microseconds;
+} __attribute__ ((packed)) timestamp;
+
+/* Type and Time Zone (ECMA 167r3 1/7.3.1) */
+#define TIMESTAMP_TYPE_MASK		0xF000
+#define TIMESTAMP_TYPE_CUT		0x0000
+#define TIMESTAMP_TYPE_LOCAL		0x1000
+#define TIMESTAMP_TYPE_AGREEMENT	0x2000
+#define TIMESTAMP_TIMEZONE_MASK		0x0FFF
+
+/* Entity identifier (ECMA 167r3 1/7.4) */
+typedef struct
+{
+	uint8_t		flags;
+	uint8_t		ident[23];
+	uint8_t		identSuffix[8];
+} __attribute__ ((packed)) regid;
+
+/* Flags (ECMA 167r3 1/7.4.1) */
+#define ENTITYID_FLAGS_DIRTY		0x00
+#define ENTITYID_FLAGS_PROTECTED	0x01
+
+/* Volume Structure Descriptor (ECMA 167r3 2/9.1) */
+#define VSD_STD_ID_LEN			5
+struct volStructDesc
+{
+	uint8_t		structType;
+	uint8_t		stdIdent[VSD_STD_ID_LEN];
+	uint8_t		structVersion;
+	uint8_t		structData[2041];
+} __attribute__ ((packed));
+
+/* Standard Identifier (EMCA 167r2 2/9.1.2) */
+#define VSD_STD_ID_NSR02		"NSR02"	/* (3/9.1) */
+
+/* Standard Identifier (ECMA 167r3 2/9.1.2) */
+#define VSD_STD_ID_BEA01		"BEA01"	/* (2/9.2) */
+#define VSD_STD_ID_BOOT2		"BOOT2"	/* (2/9.4) */
+#define VSD_STD_ID_CD001		"CD001"	/* (ECMA-119) */
+#define VSD_STD_ID_CDW02		"CDW02"	/* (ECMA-168) */
+#define VSD_STD_ID_NSR03		"NSR03"	/* (3/9.1) */
+#define VSD_STD_ID_TEA01		"TEA01"	/* (2/9.3) */
+
+/* Beginning Extended Area Descriptor (ECMA 167r3 2/9.2) */
+struct beginningExtendedAreaDesc
+{
+	uint8_t		structType;
+	uint8_t		stdIdent[VSD_STD_ID_LEN];
+	uint8_t		structVersion;
+	uint8_t		structData[2041];
+} __attribute__ ((packed));
+
+/* Terminating Extended Area Descriptor (ECMA 167r3 2/9.3) */
+struct terminatingExtendedAreaDesc
+{
+	uint8_t		structType;
+	uint8_t		stdIdent[VSD_STD_ID_LEN];
+	uint8_t		structVersion;
+	uint8_t		structData[2041];
+} __attribute__ ((packed));
+
+/* Boot Descriptor (ECMA 167r3 2/9.4) */
+struct bootDesc
+{
+	uint8_t		structType;
+	uint8_t		stdIdent[VSD_STD_ID_LEN];
+	uint8_t		structVersion;
+	uint8_t		reserved1;
+	regid		archType;
+	regid		bootIdent;
+	uint32_t	bootExtLocation;
+	uint32_t	bootExtLength;
+	uint64_t	loadAddress;
+	uint64_t	startAddress;
+	timestamp	descCreationDateAndTime;
+	uint16_t	flags;
+	uint8_t		reserved2[32];
+	uint8_t		bootUse[1906];
+} __attribute__ ((packed));
+
+/* Flags (ECMA 167r3 2/9.4.12) */
+#define BOOT_FLAGS_ERASE		0x01
+
+/* Extent Descriptor (ECMA 167r3 3/7.1) */
+typedef struct
+{
+	uint32_t	extLength;
+	uint32_t	extLocation;
+} __attribute__ ((packed)) extent_ad;
+
+/* Descriptor Tag (ECMA 167r3 3/7.2) */
+typedef struct
+{
+	uint16_t	tagIdent;
+	uint16_t	descVersion;
+	uint8_t		tagChecksum;
+	uint8_t		reserved;
+	uint16_t	tagSerialNum;
+	uint16_t	descCRC;
+	uint16_t	descCRCLength;
+	uint32_t	tagLocation;
+} __attribute__ ((packed)) tag;
+
+/* Tag Identifier (ECMA 167r3 3/7.2.1) */
+#define TAG_IDENT_PVD			0x0001
+#define TAG_IDENT_AVDP			0x0002
+#define TAG_IDENT_VDP			0x0003
+#define TAG_IDENT_IUVD			0x0004
+#define TAG_IDENT_PD			0x0005
+#define TAG_IDENT_LVD			0x0006
+#define TAG_IDENT_USD			0x0007
+#define TAG_IDENT_TD			0x0008
+#define TAG_IDENT_LVID			0x0009
+
+/* NSR Descriptor (ECMA 167r3 3/9.1) */
+struct NSRDesc
+{
+	uint8_t		structType;
+	uint8_t		stdIdent[VSD_STD_ID_LEN];
+	uint8_t		structVersion;
+	uint8_t		reserved;
+	uint8_t		structData[2040];
+} __attribute__ ((packed));
+	
+/* Primary Volume Descriptor (ECMA 167r3 3/10.1) */
+struct primaryVolDesc
+{
+	tag		descTag;
+	uint32_t	volDescSeqNum;
+	uint32_t	primaryVolDescNum;
+	dstring		volIdent[32];
+	uint16_t	volSeqNum;
+	uint16_t	maxVolSeqNum;
+	uint16_t	interchangeLvl;
+	uint16_t	maxInterchangeLvl;
+	uint32_t	charSetList;
+	uint32_t	maxCharSetList;
+	dstring		volSetIdent[128];
+	charspec	descCharSet;
+	charspec	explanatoryCharSet;
+	extent_ad	volAbstract;
+	extent_ad	volCopyright;
+	regid		appIdent;
+	timestamp	recordingDateAndTime;
+	regid		impIdent;
+	uint8_t		impUse[64];
+	uint32_t	predecessorVolDescSeqLocation;
+	uint16_t	flags;
+	uint8_t		reserved[22];
+} __attribute__ ((packed));
+
+/* Flags (ECMA 167r3 3/10.1.21) */
+#define PVD_FLAGS_VSID_COMMON		0x0001
+
+/* Anchor Volume Descriptor Pointer (ECMA 167r3 3/10.2) */
+struct anchorVolDescPtr
+{
+	tag		descTag;
+	extent_ad	mainVolDescSeqExt;
+	extent_ad	reserveVolDescSeqExt;
+	uint8_t	 	reserved[480];
+} __attribute__ ((packed));
+
+/* Volume Descriptor Pointer (ECMA 167r3 3/10.3) */
+struct volDescPtr
+{
+	tag		descTag;
+	uint32_t	volDescSeqNum;
+	extent_ad	nextVolDescSeqExt;
+	uint8_t		reserved[484];
+} __attribute__ ((packed));
+
+/* Implementation Use Volume Descriptor (ECMA 167r3 3/10.4) */
+struct impUseVolDesc
+{
+	tag		descTag;
+	uint32_t	volDescSeqNum;
+	regid		impIdent;
+	uint8_t		impUse[460];
+} __attribute__ ((packed));
+
+/* Partition Descriptor (ECMA 167r3 3/10.5) */
+struct partitionDesc
+{
+	tag		descTag;
+	uint32_t	volDescSeqNum;
+	uint16_t	partitionFlags;
+	uint16_t	partitionNumber;
+	regid		partitionContents;
+	uint8_t		partitionContentsUse[128];
+	uint32_t	accessType;
+	uint32_t	partitionStartingLocation;
+	uint32_t	partitionLength;
+	regid		impIdent;
+	uint8_t		impUse[128];
+	uint8_t		reserved[156];
+} __attribute__ ((packed));
+
+/* Partition Flags (ECMA 167r3 3/10.5.3) */
+#define PD_PARTITION_FLAGS_ALLOC	0x0001
+
+/* Partition Contents (ECMA 167r2 3/10.5.3) */
+#define PD_PARTITION_CONTENTS_NSR02	"+NSR02"
+
+/* Partition Contents (ECMA 167r3 3/10.5.5) */
+#define PD_PARTITION_CONTENTS_FDC01	"+FDC01"
+#define PD_PARTITION_CONTENTS_CD001	"+CD001"
+#define PD_PARTITION_CONTENTS_CDW02	"+CDW02"
+#define PD_PARTITION_CONTENTS_NSR03	"+NSR03"
+
+/* Access Type (ECMA 167r3 3/10.5.7) */
+#define PD_ACCESS_TYPE_NONE		0x00000000
+#define PD_ACCESS_TYPE_READ_ONLY	0x00000001
+#define PD_ACCESS_TYPE_WRITE_ONCE	0x00000002
+#define PD_ACCESS_TYPE_REWRITABLE	0x00000003
+#define PD_ACCESS_TYPE_OVERWRITABLE	0x00000004
+
+/* Logical Volume Descriptor (ECMA 167r3 3/10.6) */
+struct logicalVolDesc
+{
+	tag		descTag;
+	uint32_t	volDescSeqNum;
+	charspec	descCharSet;
+	dstring		logicalVolIdent[128];
+	uint32_t	logicalBlockSize;
+	regid		domainIdent;
+	uint8_t		logicalVolContentsUse[16];
+	uint32_t	mapTableLength;
+	uint32_t	numPartitionMaps;
+	regid		impIdent;
+	uint8_t		impUse[128];
+	extent_ad	integritySeqExt;
+	uint8_t		partitionMaps[0];
+} __attribute__ ((packed));
+
+/* Generic Partition Map (ECMA 167r3 3/10.7.1) */
+struct genericPartitionMap
+{
+	uint8_t		partitionMapType;
+	uint8_t		partitionMapLength;
+	uint8_t		partitionMapping[0];
+} __attribute__ ((packed));
+
+/* Partition Map Type (ECMA 167r3 3/10.7.1.1) */
+#define GP_PARTITION_MAP_TYPE_UNDEF	0x00
+#define GP_PARTIITON_MAP_TYPE_1		0x01
+#define GP_PARTITION_MAP_TYPE_2		0x02
+
+/* Type 1 Partition Map (ECMA 167r3 3/10.7.2) */
+struct genericPartitionMap1
+{
+	uint8_t		partitionMapType;
+	uint8_t		partitionMapLength;
+	uint16_t	volSeqNum;
+	uint16_t	partitionNum;
+} __attribute__ ((packed));
+
+/* Type 2 Partition Map (ECMA 167r3 3/10.7.3) */
+struct genericPartitionMap2
+{
+	uint8_t		partitionMapType;
+	uint8_t		partitionMapLength; 
+	uint8_t		partitionIdent[62];
+} __attribute__ ((packed));
+
+/* Unallocated Space Descriptor (ECMA 167r3 3/10.8) */
+struct unallocSpaceDesc
+{
+	tag		descTag;
+	uint32_t	volDescSeqNum;
+	uint32_t	numAllocDescs;
+	extent_ad	allocDescs[0];
+} __attribute__ ((packed));
+
+/* Terminating Descriptor (ECMA 167r3 3/10.9) */
+struct terminatingDesc
+{
+	tag		descTag;
+	uint8_t		reserved[496];
+} __attribute__ ((packed));
+
+/* Logical Volume Integrity Descriptor (ECMA 167r3 3/10.10) */
+struct logicalVolIntegrityDesc
+{
+	tag		descTag;
+	timestamp	recordingDateAndTime;
+	uint32_t	integrityType;
+	extent_ad	nextIntegrityExt;
+	uint8_t		logicalVolContentsUse[32];
+	uint32_t	numOfPartitions;
+	uint32_t	lengthOfImpUse;
+	uint32_t	freeSpaceTable[0];
+	uint32_t	sizeTable[0];
+	uint8_t		impUse[0];
+} __attribute__ ((packed));
+
+/* Integrity Type (ECMA 167r3 3/10.10.3) */
+#define LVID_INTEGRITY_TYPE_OPEN	0x00000000
+#define LVID_INTEGRITY_TYPE_CLOSE	0x00000001
+
+/* Recorded Address (ECMA 167r3 4/7.1) */
+typedef struct 
+{
+	uint32_t	logicalBlockNum;
+	uint16_t	partitionReferenceNum;
+} __attribute__ ((packed)) lb_addr;
+
+/* Short Allocation Descriptor (ECMA 167r3 4/14.14.1) */
+typedef struct
+{
+        uint32_t	extLength;
+        uint32_t	extPosition;
+} __attribute__ ((packed)) short_ad;
+
+/* Long Allocation Descriptor (ECMA 167r3 4/14.14.2) */
+typedef struct
+{
+	uint32_t	extLength;
+	lb_addr		extLocation;
+	uint8_t		impUse[6];
+} __attribute__ ((packed)) long_ad;
+
+/* Extended Allocation Descriptor (ECMA 167r3 4/14.14.3) */
+typedef struct
+{
+	uint32_t	extLength;
+	uint32_t	recordedLength;
+	uint32_t	informationLength;
+	lb_addr		extLocation;
+} __attribute__ ((packed)) ext_ad;
+
+/* Descriptor Tag (ECMA 167r3 4/7.2 - See 3/7.2) */
+
+/* Tag Identifier (ECMA 167r3 4/7.2.1) */
+#define TAG_IDENT_FSD			0x0100
+#define TAG_IDENT_FID			0x0101
+#define TAG_IDENT_AED			0x0102
+#define TAG_IDENT_IE			0x0103
+#define TAG_IDENT_TE			0x0104
+#define TAG_IDENT_FE			0x0105
+#define TAG_IDENT_EAHD			0x0106
+#define TAG_IDENT_USE			0x0107
+#define TAG_IDENT_SBD			0x0108
+#define TAG_IDENT_PIE			0x0109
+#define TAG_IDENT_EFE			0x010A
+
+/* File Set Descriptor (ECMA 167r3 4/14.1) */
+struct fileSetDesc
+{
+	tag		descTag;
+	timestamp	recordingDateAndTime;
+	uint16_t	interchangeLvl;
+	uint16_t	maxInterchangeLvl;
+	uint32_t	charSetList;
+	uint32_t	maxCharSetList;
+	uint32_t	fileSetNum;
+	uint32_t	fileSetDescNum;
+	charspec	logicalVolIdentCharSet;
+	dstring		logicalVolIdent[128];
+	charspec	fileSetCharSet;
+	dstring		fileSetIdent[32];
+	dstring		copyrightFileIdent[32];
+	dstring		abstractFileIdent[32];
+	long_ad		rootDirectoryICB;
+	regid		domainIdent;
+	long_ad		nextExt;
+	long_ad		streamDirectoryICB;
+	uint8_t		reserved[32];
+} __attribute__ ((packed));
+
+/* Partition Header Descriptor (ECMA 167r3 4/14.3) */
+struct partitionHeaderDesc
+{
+	short_ad	unallocSpaceTable;
+	short_ad	unallocSpaceBitmap;
+	short_ad	partitionIntegrityTable;
+	short_ad	freedSpaceTable;
+	short_ad	freedSpaceBitmap;
+	uint8_t		reserved[88];
+} __attribute__ ((packed));
+
+/* File Identifier Descriptor (ECMA 167r3 4/14.4) */
+struct fileIdentDesc
+{
+	tag		descTag;
+	uint16_t	fileVersionNum;
+	uint8_t		fileCharacteristics;
+	uint8_t		lengthFileIdent;
+	long_ad		icb;
+	uint16_t	lengthOfImpUse;
+	uint8_t		impUse[0];
+	uint8_t		fileIdent[0];
+	uint8_t		padding[0];
+} __attribute__ ((packed));
+
+/* File Characteristics (ECMA 167r3 4/14.4.3) */
+#define FID_FILE_CHAR_HIDDEN		0x01
+#define FID_FILE_CHAR_DIRECTORY		0x02
+#define FID_FILE_CHAR_DELETED		0x04
+#define FID_FILE_CHAR_PARENT		0x08
+#define FID_FILE_CHAR_METADATA		0x10
+
+/* Allocation Ext Descriptor (ECMA 167r3 4/14.5) */
+struct allocExtDesc
+{
+	tag		descTag;
+	uint32_t	previousAllocExtLocation;
+	uint32_t	lengthAllocDescs;
+} __attribute__ ((packed));
+
+/* ICB Tag (ECMA 167r3 4/14.6) */
+typedef struct
+{
+	uint32_t	priorRecordedNumDirectEntries;
+	uint16_t	strategyType;
+	uint16_t	strategyParameter;
+	uint16_t	numEntries;
+	uint8_t		reserved;
+	uint8_t		fileType;
+	lb_addr		parentICBLocation;
+	uint16_t	flags;
+} __attribute__ ((packed)) icbtag;
+
+/* Strategy Type (ECMA 167r3 4/14.6.2) */
+#define ICBTAG_STRATEGY_TYPE_UNDEF	0x0000
+#define ICBTAG_STRATEGY_TYPE_1		0x0001
+#define ICBTAG_STRATEGY_TYPE_2		0x0002
+#define ICBTAG_STRATEGY_TYPE_3		0x0003
+#define ICBTAG_STRATEGY_TYPE_4		0x0004
+
+/* File Type (ECMA 167r3 4/14.6.6) */
+#define ICBTAG_FILE_TYPE_UNDEF		0x00
+#define ICBTAG_FILE_TYPE_USE		0x01
+#define ICBTAG_FILE_TYPE_PIE		0x02
+#define ICBTAG_FILE_TYPE_IE		0x03
+#define ICBTAG_FILE_TYPE_DIRECTORY	0x04
+#define ICBTAG_FILE_TYPE_REGULAR	0x05
+#define ICBTAG_FILE_TYPE_BLOCK		0x06
+#define ICBTAG_FILE_TYPE_CHAR		0x07
+#define ICBTAG_FILE_TYPE_EA		0x08
+#define ICBTAG_FILE_TYPE_FIFO		0x09
+#define ICBTAG_FILE_TYPE_SOCKET		0x0A
+#define ICBTAG_FILE_TYPE_TE		0x0B
+#define ICBTAG_FILE_TYPE_SYMLINK	0x0C
+#define ICBTAG_FILE_TYPE_STREAMDIR	0x0D
+
+/* Flags (ECMA 167r3 4/14.6.8) */
+#define ICBTAG_FLAG_AD_MASK		0x0007
+#define ICBTAG_FLAG_AD_SHORT		0x0000
+#define ICBTAG_FLAG_AD_LONG		0x0001
+#define ICBTAG_FLAG_AD_EXTENDED		0x0002
+#define ICBTAG_FLAG_AD_IN_ICB		0x0003
+#define ICBTAG_FLAG_SORTED		0x0008
+#define ICBTAG_FLAG_NONRELOCATABLE	0x0010
+#define ICBTAG_FLAG_ARCHIVE		0x0020
+#define ICBTAG_FLAG_SETUID		0x0040
+#define ICBTAG_FLAG_SETGID		0x0080
+#define ICBTAG_FLAG_STICKY		0x0100
+#define ICBTAG_FLAG_CONTIGUOUS		0x0200
+#define ICBTAG_FLAG_SYSTEM		0x0400
+#define ICBTAG_FLAG_TRANSFORMED		0x0800
+#define ICBTAG_FLAG_MULTIVERSIONS	0x1000
+#define ICBTAG_FLAG_STREAM		0x2000
+
+/* Indirect Entry (ECMA 167r3 4/14.7) */
+struct indirectEntry
+{
+	tag		descTag;
+	icbtag		icbTag;
+	long_ad		indirectICB;
+} __attribute__ ((packed));
+
+/* Terminal Entry (ECMA 167r3 4/14.8) */
+struct terminalEntry
+{
+	tag		descTag;
+	icbtag		icbTag;
+} __attribute__ ((packed));
+
+/* File Entry (ECMA 167r3 4/14.9) */
+struct fileEntry
+{
+	tag		descTag;
+	icbtag		icbTag;
+	uint32_t	uid;
+	uint32_t	gid;
+	uint32_t	permissions;
+	uint16_t	fileLinkCount;
+	uint8_t		recordFormat;
+	uint8_t		recordDisplayAttr;
+	uint32_t	recordLength;
+	uint64_t	informationLength;
+	uint64_t	logicalBlocksRecorded;
+	timestamp	accessTime;
+	timestamp	modificationTime;
+	timestamp	attrTime;
+	uint32_t	checkpoint;
+	long_ad		extendedAttrICB;
+	regid		impIdent;
+	uint64_t	uniqueID;
+	uint32_t	lengthExtendedAttr;
+	uint32_t	lengthAllocDescs;
+	uint8_t		extendedAttr[0];
+	uint8_t		allocDescs[0];
+} __attribute__ ((packed));
+
+/* Permissions (ECMA 167r3 4/14.9.5) */
+#define FE_PERM_O_EXEC			0x00000001U
+#define FE_PERM_O_WRITE			0x00000002U
+#define FE_PERM_O_READ			0x00000004U
+#define FE_PERM_O_CHATTR		0x00000008U
+#define FE_PERM_O_DELETE		0x00000010U
+#define FE_PERM_G_EXEC			0x00000020U
+#define FE_PERM_G_WRITE			0x00000040U
+#define FE_PERM_G_READ			0x00000080U
+#define FE_PERM_G_CHATTR		0x00000100U
+#define FE_PERM_G_DELETE		0x00000200U
+#define FE_PERM_U_EXEC			0x00000400U
+#define FE_PERM_U_WRITE			0x00000800U
+#define FE_PERM_U_READ			0x00001000U
+#define FE_PERM_U_CHATTR		0x00002000U
+#define FE_PERM_U_DELETE		0x00004000U
+
+/* Record Format (ECMA 167r3 4/14.9.7) */
+#define FE_RECORD_FMT_UNDEF		0x00
+#define FE_RECORD_FMT_FIXED_PAD		0x01
+#define FE_RECORD_FMT_FIXED		0x02
+#define FE_RECORD_FMT_VARIABLE8		0x03
+#define FE_RECORD_FMT_VARIABLE16	0x04
+#define FE_RECORD_FMT_VARIABLE16_MSB	0x05
+#define FE_RECORD_FMT_VARIABLE32	0x06
+#define FE_RECORD_FMT_PRINT		0x07
+#define FE_RECORD_FMT_LF		0x08
+#define FE_RECORD_FMT_CR		0x09
+#define FE_RECORD_FMT_CRLF		0x0A
+#define FE_RECORD_FMT_LFCR		0x0B
+
+#define Record Display Attributes (ECMA 167r3 4/14.9.8) */
+#define FE_RECORD_DISPLAY_ATTR_UNDEF	0x00
+#define FE_RECORD_DISPLAY_ATTR_1	0x01
+#define FE_RECORD_DISPLAY_ATTR_2	0x02
+#define FE_RECORD_DISPLAY_ATTR_3	0x03
+
+/* Extended Attribute Header Descriptor (ECMA 167r3 4/14.10.1) */
+struct extendedAttrHeaderDesc
+{
+	tag		descTag;
+	uint32_t	impAttrLocation;
+	uint32_t	appAttrLocation;
+} __attribute__ ((packed));
+
+/* Generic Format (ECMA 167r3 4/14.10.2) */
+struct genericFormat
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint8_t		attrData[0];
+} __attribute__ ((packed));
+
+/* Character Set Information (ECMA 167r3 4/14.10.3) */
+struct charSetInfo
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint32_t	escapeSeqLength;
+	uint8_t		charSetType;
+	uint8_t		escapeSeq[0];
+} __attribute__ ((packed));
+
+/* Alternate Permissions (ECMA 167r3 4/14.10.4) */
+struct altPerms
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint16_t	ownerIdent;
+	uint16_t	groupIdent;
+	uint16_t	permission;
+} __attribute__ ((packed));
+
+/* File Times Extended Attribute (ECMA 167r3 4/14.10.5) */
+struct fileTimesExtAttr
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint32_t	dataLength;
+	uint32_t	fileTimeExistence;
+	uint8_t		fileTimes;
+} __attribute__ ((packed));
+
+/* FileTimeExistence (ECMA 167r3 4/14.10.5.6) */
+#define FTE_CREATION			0x00000001
+#define FTE_DELETION			0x00000004
+#define FTE_EFFECTIVE			0x00000008
+#define FTE_BACKUP			0x00000002
+
+/* Information Times Extended Attribute (ECMA 167r3 4/14.10.6) */
+struct infoTimesExtAttr
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint32_t	dataLength;
+	uint32_t	infoTimeExistence;
+	uint8_t		infoTimes[0];
+} __attribute__ ((packed));
+
+/* Device Specification (ECMA 167r3 4/14.10.7) */
+struct deviceSpec
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint32_t	impUseLength;
+	uint32_t	majorDeviceIdent;
+	uint32_t	minorDeviceIdent;
+	uint8_t		impUse[0];
+} __attribute__ ((packed));
+
+/* Implementation Use Extended Attr (ECMA 167r3 4/14.10.8) */
+struct impUseExtAttr
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint32_t	impUseLength;
+	regid		impIdent;
+	uint8_t		impUse[0];
+} __attribute__ ((packed));
+
+/* Application Use Extended Attribute (ECMA 167r3 4/14.10.9) */
+struct appUseExtAttr
+{
+	uint32_t	attrType;
+	uint8_t		attrSubtype;
+	uint8_t		reserved[3];
+	uint32_t	attrLength;
+	uint32_t	appUseLength;
+	regid		appIdent;
+	uint8_t		appUse[0];
+} __attribute__ ((packed));
+
+#define EXTATTR_CHAR_SET		1
+#define EXTATTR_ALT_PERMS		3
+#define EXTATTR_FILE_TIMES		5
+#define EXTATTR_INFO_TIMES		6
+#define EXTATTR_DEV_SPEC		12
+#define EXTATTR_IMP_USE			2048
+#define EXTATTR_APP_USE			65536
+
+
+/* Unallocated Space Entry (ECMA 167r3 4/14.11) */
+struct unallocSpaceEntry
+{
+	tag		descTag;
+	icbtag		icbTag;
+	uint32_t	lengthAllocDescs;
+	uint8_t		allocDescs[0];
+} __attribute__ ((packed));
+
+/* Space Bitmap Descriptor (ECMA 167r3 4/14.12) */
+struct spaceBitmapDesc
+{
+	tag		descTag;
+	uint32_t	numOfBits;
+	uint32_t	numOfBytes;
+	uint8_t		bitmap[0];
+} __attribute__ ((packed));
+
+/* Partition Integrity Entry (ECMA 167r3 4/14.13) */
+struct partitionIntegrityEntry
+{
+	tag		descTag;
+	icbtag		icbTag;
+	timestamp	recordingDateAndTime;
+	uint8_t		integrityType;
+	uint8_t		reserved[175];
+	regid		impIdent;
+	uint8_t		impUse[256];
+} __attribute__ ((packed));
+
+/* Short Allocation Descriptor (ECMA 167r3 4/14.14.1) */
+
+/* Extent Length (ECMA 167r3 4/14.14.1.1) */
+#define EXT_RECORDED_ALLOCATED		0x00000000
+#define EXT_NOT_RECORDED_ALLOCATED	0x40000000
+#define EXT_NOT_RECORDED_NOT_ALLOCATED	0x80000000
+#define EXT_NEXT_EXTENT_ALLOCDECS	0xC0000000
+
+/* Long Allocation Descriptor (ECMA 167r3 4/14.14.2) */
+
+/* Extended Allocation Descriptor (ECMA 167r3 4/14.14.3) */
+
+/* Logical Volume Header Descriptor (ECMA 167r3 4/14.15) */
+struct logicalVolHeaderDesc
+{
+	uint64_t	uniqueID;
+	uint8_t		reserved[24];
+} __attribute__ ((packed));
+
+/* Path Component (ECMA 167r3 4/14.16.1) */
+struct pathComponent
+{
+	uint8_t		componentType;
+	uint8_t		lengthComponentIdent;
+	uint16_t	componentFileVersionNum;
+	dstring		componentIdent[0];
+} __attribute__ ((packed));
+
+/* File Entry (ECMA 167r3 4/14.17) */
+struct extendedFileEntry
+{
+	tag		descTag;
+	icbtag		icbTag;
+	uint32_t	uid;
+	uint32_t	gid;
+	uint32_t	permissions;
+	uint16_t	fileLinkCount;
+	uint8_t		recordFormat;
+	uint8_t		recordDisplayAttr;
+	uint32_t	recordLength;
+	uint64_t	informationLength;
+	uint64_t	objectSize;
+	uint64_t	logicalBlocksRecorded;
+	timestamp	accessTime;
+	timestamp	modificationTime;
+	timestamp	createTime;
+	timestamp	attrTime;
+	uint32_t	checkpoint;
+	uint32_t	reserved;
+	long_ad		extendedAttrICB;
+	long_ad		streamDirectoryICB;
+	regid		impIdent;
+	uint64_t	uniqueID;
+	uint32_t	lengthExtendedAttr;
+	uint32_t	lengthAllocDescs;
+	uint8_t		extendedAttr[0];
+	uint8_t		allocDescs[0];
+} __attribute__ ((packed));
+
+#endif /* _ECMA_167_H */
diff -Nru a/fs/udf/file.c b/fs/udf/file.c
--- a/fs/udf/file.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/file.c	Fri Mar 15 17:51:01 2002
@@ -16,7 +16,7 @@
  *  Each contributing author retains all rights to their own work.
  *
  *  (C) 1998-1999 Dave Boynton
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *  (C) 1999-2000 Stelias Computing Inc
  *
  * HISTORY
@@ -25,7 +25,7 @@
  *  10/07/98      Switched to using generic_readpage, etc., like isofs
  *                And it works!
  *  12/06/98 blf  Added udf_file_read. uses generic_file_read for all cases but
- *                ICB_FLAG_AD_IN_ICB.
+ *                ICBTAG_FLAG_AD_IN_ICB.
  *  04/06/99      64 bit file handling on 32 bit systems taken from ext2 file.c
  *  05/12/99      Preliminary file write support
  */
@@ -50,6 +50,7 @@
 	struct buffer_head *bh;
 	int block;
 	char *kaddr;
+	int err = 0;
 
 	if (!PageLocked(page))
 		PAGE_BUG(page);
@@ -58,13 +59,20 @@
 	memset(kaddr, 0, PAGE_CACHE_SIZE);
 	block = udf_get_lb_pblock(inode->i_sb, UDF_I_LOCATION(inode), 0);
 	bh = sb_bread(inode->i_sb, block);
+	if (!bh)
+	{
+		SetPageError(page);
+		err = -EIO;
+		goto out;
+	}
 	memcpy(kaddr, bh->b_data + udf_ext0_offset(inode), inode->i_size);
 	brelse(bh);
 	flush_dcache_page(page);
 	SetPageUptodate(page);
+out:
 	kunmap(page);
 	UnlockPage(page);
-	return 0;
+	return err;
 }
 
 static int udf_adinicb_writepage(struct page *page)
@@ -74,6 +82,7 @@
 	struct buffer_head *bh;
 	int block;
 	char *kaddr;
+	int err = 0;
 
 	if (!PageLocked(page))
 		PAGE_BUG(page);
@@ -81,13 +90,20 @@
 	kaddr = kmap(page);
 	block = udf_get_lb_pblock(inode->i_sb, UDF_I_LOCATION(inode), 0);
 	bh = sb_bread(inode->i_sb, block);
+	if (!bh)
+	{
+		SetPageError(page);
+		err = -EIO;
+		goto out;
+	}
 	memcpy(bh->b_data + udf_ext0_offset(inode), kaddr, inode->i_size);
 	mark_buffer_dirty(bh);
 	brelse(bh);
 	SetPageUptodate(page);
+out:
 	kunmap(page);
 	UnlockPage(page);
-	return 0;
+	return err;
 }
 
 static int udf_adinicb_prepare_write(struct file *file, struct page *page, unsigned offset, unsigned to)
@@ -103,19 +119,27 @@
 	struct buffer_head *bh;
 	int block;
 	char *kaddr = page_address(page);
+	int err = 0;
 
 	block = udf_get_lb_pblock(inode->i_sb, UDF_I_LOCATION(inode), 0);
 	bh = sb_bread(inode->i_sb, block);
+	if (!bh)
+	{
+		SetPageError(page);
+		err = -EIO;
+		goto out;
+	}
 	memcpy(bh->b_data + udf_file_entry_alloc_offset(inode) + offset,
-		kaddr + offset, to-offset);
+		kaddr + offset, to - offset);
 	mark_buffer_dirty(bh);
 	brelse(bh);
 	SetPageUptodate(page);
+out:
 	kunmap(page);
 	/* only one page here */
 	if (to > inode->i_size)
 		inode->i_size = to;
-	return 0;
+	return err;
 }
 
 struct address_space_operations udf_adinicb_aops = {
@@ -133,7 +157,7 @@
 	struct inode *inode = file->f_dentry->d_inode;
 	int err, pos;
 
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		if (file->f_flags & O_APPEND)
 			pos = inode->i_size;
@@ -144,7 +168,7 @@
 			pos + count))
 		{
 			udf_expand_file_adinicb(inode, pos + count, &err);
-			if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+			if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 			{
 				udf_debug("udf_expand_adinicb: err=%d\n", err);
 				return err;
@@ -209,7 +233,7 @@
 	int result = -EINVAL;
 	struct buffer_head *bh = NULL;
 	long_ad eaicb;
-	Uint8 *ea = NULL;
+	uint8_t *ea = NULL;
 
 	if ( permission(inode, MAY_READ) != 0 )
 	{
@@ -256,18 +280,18 @@
 
 	if (UDF_I_EXTENDED_FE(inode) == 0)
 	{
-		struct FileEntry *fe;
+		struct fileEntry *fe;
 
-		fe = (struct FileEntry *)bh->b_data;
+		fe = (struct fileEntry *)bh->b_data;
 		eaicb = lela_to_cpu(fe->extendedAttrICB);
 		if (UDF_I_LENEATTR(inode))
 			ea = fe->extendedAttr;
 	}
 	else
 	{
-		struct ExtendedFileEntry *efe;
+		struct extendedFileEntry *efe;
 
-		efe = (struct ExtendedFileEntry *)bh->b_data;
+		efe = (struct extendedFileEntry *)bh->b_data;
 		eaicb = lela_to_cpu(efe->extendedAttrICB);
 		if (UDF_I_LENEATTR(inode))
 			ea = efe->extendedAttr;
diff -Nru a/fs/udf/fsync.c b/fs/udf/fsync.c
--- a/fs/udf/fsync.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/fsync.c	Fri Mar 15 17:51:01 2002
@@ -15,7 +15,7 @@
  *      ftp://prep.ai.mit.edu/pub/gnu/GPL
  *  Each contributing author retains all rights to their own work.
  *
- *  (C) 1999-2000 Ben Fennema
+ *  (C) 1999-2001 Ben Fennema
  *  (C) 1999-2000 Stelias Computing Inc
  *
  * HISTORY
diff -Nru a/fs/udf/ialloc.c b/fs/udf/ialloc.c
--- a/fs/udf/ialloc.c	Fri Mar 15 17:51:03 2002
+++ b/fs/udf/ialloc.c	Fri Mar 15 17:51:03 2002
@@ -15,7 +15,7 @@
  *		ftp://prep.ai.mit.edu/pub/gnu/GPL
  *	Each contributing author retains all rights to their own work.
  *
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *
  * HISTORY
  *
@@ -74,7 +74,7 @@
 	struct super_block *sb;
 	struct inode * inode;
 	int block;
-	Uint32 start = UDF_I_LOCATION(dir).logicalBlockNum;
+	uint32_t start = UDF_I_LOCATION(dir).logicalBlockNum;
 
 	sb = dir->i_sb;
 	inode = new_inode(sb);
@@ -102,9 +102,9 @@
 	UDF_I_STRAT4096(inode) = 0;
 	if (UDF_SB_LVIDBH(sb))
 	{
-		struct LogicalVolHeaderDesc *lvhd;
-		Uint64 uniqueID;
-		lvhd = (struct LogicalVolHeaderDesc *)(UDF_SB_LVID(sb)->logicalVolContentsUse);
+		struct logicalVolHeaderDesc *lvhd;
+		uint64_t uniqueID;
+		lvhd = (struct logicalVolHeaderDesc *)(UDF_SB_LVID(sb)->logicalVolContentsUse);
 		if (S_ISDIR(mode))
 			UDF_SB_LVIDIU(sb)->numDirs =
 				cpu_to_le32(le32_to_cpu(UDF_SB_LVIDIU(sb)->numDirs) + 1);
@@ -143,11 +143,11 @@
 	else
 		UDF_I_EXTENDED_FE(inode) = 0;
 	if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_AD_IN_ICB))
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_IN_ICB;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_IN_ICB;
 	else if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_SHORT;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
 	else
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_LONG;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
 	inode->i_mtime = inode->i_atime = inode->i_ctime =
 		UDF_I_CRTIME(inode) = CURRENT_TIME;
 	UDF_I_UMTIME(inode) = UDF_I_UCTIME(inode) =
diff -Nru a/fs/udf/inode.c b/fs/udf/inode.c
--- a/fs/udf/inode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/udf/inode.c	Fri Mar 15 17:51:03 2002
@@ -16,7 +16,7 @@
  *  Each contributing author retains all rights to their own work.
  *
  *  (C) 1998 Dave Boynton
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *  (C) 1999-2000 Stelias Computing Inc
  *
  * HISTORY
@@ -48,7 +48,7 @@
 
 #define EXTENT_MERGE_SIZE 5
 
-static mode_t udf_convert_permissions(struct FileEntry *);
+static mode_t udf_convert_permissions(struct fileEntry *);
 static int udf_update_inode(struct inode *, int);
 static void udf_fill_inode(struct inode *, struct buffer_head *);
 static struct buffer_head *inode_getblk(struct inode *, long, int *, long *, int *);
@@ -60,7 +60,7 @@
 	 long_ad [EXTENT_MERGE_SIZE], int *);
 static void udf_update_extents(struct inode *,
 	long_ad [EXTENT_MERGE_SIZE], int, int,
-	lb_addr, Uint32, struct buffer_head **);
+	lb_addr, uint32_t, struct buffer_head **);
 static int udf_get_block(struct inode *, sector_t, struct buffer_head *, int);
 
 /*
@@ -83,9 +83,6 @@
 	{
 		lock_kernel();
 		udf_discard_prealloc(inode);
-		/* write the root inode on put, if dirty */
-		if (!inode->i_sb->s_root && inode->i_state & I_DIRTY)
-			udf_update_inode(inode, IS_SYNC(inode));
 		unlock_kernel();
 	}
 }
@@ -127,7 +124,7 @@
 void udf_discard_prealloc(struct inode * inode)
 {
 	if (inode->i_size && inode->i_size != UDF_I_LENEXTENTS(inode) &&
-		UDF_I_ALLOCTYPE(inode) != ICB_FLAG_AD_IN_ICB)
+		UDF_I_ALLOCTYPE(inode) != ICBTAG_FLAG_AD_IN_ICB)
 	{
 		udf_truncate_extents(inode);
 	}
@@ -175,9 +172,9 @@
 	if (!UDF_I_LENALLOC(inode))
 	{
 		if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
-			UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_SHORT;
+			UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
 		else
-			UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_LONG;
+			UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
 		mark_inode_dirty(inode);
 		return;
 	}
@@ -204,9 +201,9 @@
 		0, UDF_I_LENALLOC(inode));
 	UDF_I_LENALLOC(inode) = 0;
 	if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_SHORT;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
 	else
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_LONG;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
 	mark_buffer_dirty_inode(bh, inode);
 	udf_release_data(bh);
 
@@ -221,19 +218,19 @@
 	int newblock;
 	struct buffer_head *sbh = NULL, *dbh = NULL;
 	lb_addr bloc, eloc;
-	Uint32 elen, extoffset;
+	uint32_t elen, extoffset;
 
 	struct udf_fileident_bh sfibh, dfibh;
 	loff_t f_pos = udf_ext0_offset(inode) >> 2;
 	int size = (udf_ext0_offset(inode) + inode->i_size) >> 2;
-	struct FileIdentDesc cfi, *sfi, *dfi;
+	struct fileIdentDesc cfi, *sfi, *dfi;
 
 	if (!inode->i_size)
 	{
 		if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
-			UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_SHORT;
+			UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
 		else
-			UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_LONG;
+			UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
 		mark_inode_dirty(inode);
 		return NULL;
 	}
@@ -277,7 +274,7 @@
 		sfi->descTag.tagLocation = *block;
 		dfibh.soffset = dfibh.eoffset;
 		dfibh.eoffset += (sfibh.eoffset - sfibh.soffset);
-		dfi = (struct FileIdentDesc *)(dbh->b_data + dfibh.soffset);
+		dfi = (struct fileIdentDesc *)(dbh->b_data + dfibh.soffset);
 		if (udf_write_fi(inode, sfi, dfi, &dfibh, sfi->impUse,
 			sfi->fileIdent + sfi->lengthOfImpUse))
 		{
@@ -293,9 +290,9 @@
 
 	UDF_I_LENALLOC(inode) = 0;
 	if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_USE_SHORT_AD))
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_SHORT;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_SHORT;
 	else
-		UDF_I_ALLOCTYPE(inode) = ICB_FLAG_AD_LONG;
+		UDF_I_ALLOCTYPE(inode) = ICBTAG_FLAG_AD_LONG;
 	bloc = UDF_I_LOCATION(inode);
 	eloc.logicalBlockNum = *block;
 	eloc.partitionReferenceNum = UDF_I_LOCATION(inode).partitionReferenceNum;
@@ -392,19 +389,19 @@
 {
 	struct buffer_head *pbh = NULL, *cbh = NULL, *nbh = NULL, *result = NULL;
 	long_ad laarr[EXTENT_MERGE_SIZE];
-	Uint32 pextoffset = 0, cextoffset = 0, nextoffset = 0;
+	uint32_t pextoffset = 0, cextoffset = 0, nextoffset = 0;
 	int count = 0, startnum = 0, endnum = 0;
-	Uint32 elen = 0;
+	uint32_t elen = 0;
 	lb_addr eloc, pbloc, cbloc, nbloc;
 	int c = 1;
-	Uint64 lbcount = 0, b_off = 0;
-	Uint32 newblocknum, newblock, offset = 0;
-	Sint8 etype;
+	uint64_t lbcount = 0, b_off = 0;
+	uint32_t newblocknum, newblock, offset = 0;
+	int8_t etype;
 	int goal = 0, pgoal = UDF_I_LOCATION(inode).logicalBlockNum;
 	char lastblock = 0;
 
 	pextoffset = cextoffset = nextoffset = udf_file_entry_alloc_offset(inode);
-	b_off = (Uint64)block << inode->i_sb->s_blocksize_bits;
+	b_off = (uint64_t)block << inode->i_sb->s_blocksize_bits;
 	pbloc = cbloc = nbloc = UDF_I_LOCATION(inode);
 
 	/* find the extent which contains the block we are looking for.
@@ -441,7 +438,7 @@
 		laarr[c].extLength = (etype << 30) | elen;
 		laarr[c].extLocation = eloc;
 
-		if (etype != EXTENT_NOT_RECORDED_NOT_ALLOCATED)
+		if (etype != (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
 			pgoal = eloc.logicalBlockNum +
 				((elen + inode->i_sb->s_blocksize - 1) >>
 				inode->i_sb->s_blocksize_bits);
@@ -455,11 +452,11 @@
 	/* if the extent is allocated and recorded, return the block
        if the extent is not a multiple of the blocksize, round up */
 
-	if (etype == EXTENT_RECORDED_ALLOCATED)
+	if (etype == (EXT_RECORDED_ALLOCATED >> 30))
 	{
 		if (elen & (inode->i_sb->s_blocksize - 1))
 		{
-			elen = (EXTENT_RECORDED_ALLOCATED << 30) |
+			elen = EXT_RECORDED_ALLOCATED |
 				((elen + inode->i_sb->s_blocksize - 1) &
 				~(inode->i_sb->s_blocksize - 1));
 			etype = udf_write_aext(inode, nbloc, &cextoffset, eloc, elen, nbh, 1);
@@ -487,7 +484,7 @@
 					~(inode->i_sb->s_blocksize - 1);
 		}
 		c = !c;
-		laarr[c].extLength = (EXTENT_NOT_RECORDED_NOT_ALLOCATED << 30) |
+		laarr[c].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED |
 			((offset + 1) << inode->i_sb->s_blocksize_bits);
 		memset(&laarr[c].extLocation, 0x00, sizeof(lb_addr));
 		count ++;
@@ -528,7 +525,7 @@
 
 	/* if the current extent is not recorded but allocated, get the
 		block in the extent corresponding to the requested block */
-	if ((laarr[c].extLength >> 30) == EXTENT_NOT_RECORDED_ALLOCATED)
+	if ((laarr[c].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30))
 		newblocknum = laarr[c].extLocation.logicalBlockNum + offset;
 	else /* otherwise, allocate a new block */
 	{
@@ -594,8 +591,8 @@
 static void udf_split_extents(struct inode *inode, int *c, int offset, int newblocknum,
 	long_ad laarr[EXTENT_MERGE_SIZE], int *endnum)
 {
-	if ((laarr[*c].extLength >> 30) == EXTENT_NOT_RECORDED_ALLOCATED ||
-		(laarr[*c].extLength >> 30) == EXTENT_NOT_RECORDED_NOT_ALLOCATED)
+	if ((laarr[*c].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30) ||
+		(laarr[*c].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
 	{
 		int curr = *c;
 		int blen = ((laarr[curr].extLength & UDF_EXTENT_LENGTH_MASK) +
@@ -617,10 +614,10 @@
 
 		if (offset)
 		{
-			if ((type >> 30) == EXTENT_NOT_RECORDED_ALLOCATED)
+			if ((type >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30))
 			{
 				udf_free_blocks(inode->i_sb, inode, laarr[curr].extLocation, 0, offset);
-				laarr[curr].extLength = (EXTENT_NOT_RECORDED_NOT_ALLOCATED << 30) |
+				laarr[curr].extLength = EXT_NOT_RECORDED_NOT_ALLOCATED |
 					(offset << inode->i_sb->s_blocksize_bits);
 				laarr[curr].extLocation.logicalBlockNum = 0;
 				laarr[curr].extLocation.partitionReferenceNum = 0;
@@ -634,16 +631,16 @@
 		}
 		
 		laarr[curr].extLocation.logicalBlockNum = newblocknum;
-		if ((type >> 30) == EXTENT_NOT_RECORDED_NOT_ALLOCATED)
+		if ((type >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
 			laarr[curr].extLocation.partitionReferenceNum =
 				UDF_I_LOCATION(inode).partitionReferenceNum;
-		laarr[curr].extLength = (EXTENT_RECORDED_ALLOCATED << 30) |
+		laarr[curr].extLength = EXT_RECORDED_ALLOCATED |
 			inode->i_sb->s_blocksize;
 		curr ++;
 
 		if (blen != offset + 1)
 		{
-			if ((type >> 30) == EXTENT_NOT_RECORDED_ALLOCATED)
+			if ((type >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30))
 				laarr[curr].extLocation.logicalBlockNum += (offset + 1);
 			laarr[curr].extLength = type |
 				((blen - (offset + 1)) << inode->i_sb->s_blocksize_bits);
@@ -667,7 +664,7 @@
 	}
 	else
 	{
-		if ((laarr[c+1].extLength >> 30) == EXTENT_NOT_RECORDED_ALLOCATED)
+		if ((laarr[c+1].extLength >> 30) == (EXT_NOT_RECORDED_ALLOCATED >> 30))
 		{
 			start = c+1;
 			length = currlength = (((laarr[c+1].extLength & UDF_EXTENT_LENGTH_MASK) +
@@ -684,7 +681,7 @@
 			if (lastblock)
 				length += UDF_DEFAULT_PREALLOC_BLOCKS;
 		}
-		else if ((laarr[i].extLength >> 30) == EXTENT_NOT_RECORDED_NOT_ALLOCATED)
+		else if ((laarr[i].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
 			length += (((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
 				inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits);
 		else
@@ -703,7 +700,6 @@
 
 		if (numalloc)
 		{
-			UDF_I_LENEXTENTS(inode) += numalloc << inode->i_sb->s_blocksize_bits;
 			if (start == (c+1))
 				laarr[start].extLength +=
 					(numalloc << inode->i_sb->s_blocksize_bits);
@@ -715,7 +711,7 @@
 				laarr[c+1].extLocation.logicalBlockNum = next;
 				laarr[c+1].extLocation.partitionReferenceNum =
 					laarr[c].extLocation.partitionReferenceNum;
-				laarr[c+1].extLength = (EXTENT_NOT_RECORDED_ALLOCATED << 30) |
+				laarr[c+1].extLength = EXT_NOT_RECORDED_ALLOCATED |
 					(numalloc << inode->i_sb->s_blocksize_bits);
 				start = c+1;
 			}
@@ -727,7 +723,7 @@
 
 				if (elen > numalloc)
 				{
-					laarr[c+1].extLength -=
+					laarr[c].extLength -=
 						(numalloc << inode->i_sb->s_blocksize_bits);
 					numalloc = 0;
 				}
@@ -741,6 +737,7 @@
 					(*endnum) --;
 				}
 			}
+			UDF_I_LENEXTENTS(inode) += numalloc << inode->i_sb->s_blocksize_bits;
 		}
 	}
 }
@@ -754,7 +751,7 @@
 	{
 		if ((laarr[i].extLength >> 30) == (laarr[i+1].extLength >> 30))
 		{
-			if (((laarr[i].extLength >> 30) == EXTENT_NOT_RECORDED_NOT_ALLOCATED) ||
+			if (((laarr[i].extLength >> 30) == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30)) ||
 				((laarr[i+1].extLocation.logicalBlockNum - laarr[i].extLocation.logicalBlockNum) ==
 				(((laarr[i].extLength & UDF_EXTENT_LENGTH_MASK) +
 				inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits)))
@@ -791,11 +788,11 @@
 
 static void udf_update_extents(struct inode *inode,
 	long_ad laarr[EXTENT_MERGE_SIZE], int startnum, int endnum,
-	lb_addr pbloc, Uint32 pextoffset, struct buffer_head **pbh)
+	lb_addr pbloc, uint32_t pextoffset, struct buffer_head **pbh)
 {
 	int start = 0, i;
 	lb_addr tmploc;
-	Uint32 tmplen;
+	uint32_t tmplen;
 
 	if (startnum > endnum)
 	{
@@ -858,13 +855,13 @@
 		return;
 
 	lock_kernel();
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		if (inode->i_sb->s_blocksize < (udf_file_entry_alloc_offset(inode) +
 			inode->i_size))
 		{
 			udf_expand_file_adinicb(inode, inode->i_size, &err);
-			if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+			if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 			{
 				inode->i_size = UDF_I_LENALLOC(inode);
 				unlock_kernel();
@@ -931,8 +928,8 @@
 __udf_read_inode(struct inode *inode)
 {
 	struct buffer_head *bh = NULL;
-	struct FileEntry *fe;
-	Uint16 ident;
+	struct fileEntry *fe;
+	uint16_t ident;
 
 	/*
 	 * Set defaults, but the inode is still incomplete!
@@ -959,8 +956,8 @@
 		return;
 	}
 
-	if (ident != TID_FILE_ENTRY && ident != TID_EXTENDED_FILE_ENTRY &&
-		ident != TID_UNALLOCATED_SPACE_ENTRY)
+	if (ident != TAG_IDENT_FE && ident != TAG_IDENT_EFE &&
+		ident != TAG_IDENT_USE)
 	{
 		printk(KERN_ERR "udf: udf_read_inode(ino %ld) failed ident=%d\n",
 			inode->i_ino, ident);
@@ -969,28 +966,28 @@
 		return;
 	}
 
-	fe = (struct FileEntry *)bh->b_data;
+	fe = (struct fileEntry *)bh->b_data;
 
 	if (le16_to_cpu(fe->icbTag.strategyType) == 4096)
 	{
 		struct buffer_head *ibh = NULL, *nbh = NULL;
-		struct IndirectEntry *ie;
+		struct indirectEntry *ie;
 
 		ibh = udf_read_ptagged(inode->i_sb, UDF_I_LOCATION(inode), 1, &ident);
-		if (ident == TID_INDIRECT_ENTRY)
+		if (ident == TAG_IDENT_IE)
 		{
 			if (ibh)
 			{
 				lb_addr loc;
-				ie = (struct IndirectEntry *)ibh->b_data;
+				ie = (struct indirectEntry *)ibh->b_data;
 	
 				loc = lelb_to_cpu(ie->indirectICB.extLocation);
 	
 				if (ie->indirectICB.extLength && 
 					(nbh = udf_read_ptagged(inode->i_sb, loc, 0, &ident)))
 				{
-					if (ident == TID_FILE_ENTRY ||
-						ident == TID_EXTENDED_FILE_ENTRY)
+					if (ident == TAG_IDENT_FE ||
+						ident == TAG_IDENT_EFE)
 					{
 						memcpy(&UDF_I_LOCATION(inode), &loc, sizeof(lb_addr));
 						udf_release_data(bh);
@@ -1026,23 +1023,23 @@
 
 static void udf_fill_inode(struct inode *inode, struct buffer_head *bh)
 {
-	struct FileEntry *fe;
-	struct ExtendedFileEntry *efe;
+	struct fileEntry *fe;
+	struct extendedFileEntry *efe;
 	time_t convtime;
 	long convtime_usec;
 	int offset, alen;
 
 	UDF_I_NEW_INODE(inode) = 0;
 
-	fe = (struct FileEntry *)bh->b_data;
-	efe = (struct ExtendedFileEntry *)bh->b_data;
+	fe = (struct fileEntry *)bh->b_data;
+	efe = (struct extendedFileEntry *)bh->b_data;
 
 	if (le16_to_cpu(fe->icbTag.strategyType) == 4)
 		UDF_I_STRAT4096(inode) = 0;
 	else /* if (le16_to_cpu(fe->icbTag.strategyType) == 4096) */
 		UDF_I_STRAT4096(inode) = 1;
 
-	UDF_I_ALLOCTYPE(inode) = le16_to_cpu(fe->icbTag.flags) & ICB_FLAG_ALLOC_MASK;
+	UDF_I_ALLOCTYPE(inode) = le16_to_cpu(fe->icbTag.flags) & ICBTAG_FLAG_AD_MASK;
 	UDF_I_UMTIME(inode) = 0;
 	UDF_I_UCTIME(inode) = 0;
 	UDF_I_CRTIME(inode) = 0;
@@ -1053,15 +1050,15 @@
 	UDF_I_LENALLOC(inode) = 0;
 	UDF_I_NEXT_ALLOC_BLOCK(inode) = 0;
 	UDF_I_NEXT_ALLOC_GOAL(inode) = 0;
-	if (fe->descTag.tagIdent == TID_EXTENDED_FILE_ENTRY)
+	if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_EFE)
 		UDF_I_EXTENDED_FE(inode) = 1;
-	else if (fe->descTag.tagIdent == TID_FILE_ENTRY)
+	else if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_FE)
 		UDF_I_EXTENDED_FE(inode) = 0;
-	else if (fe->descTag.tagIdent == TID_UNALLOCATED_SPACE_ENTRY)
+	else if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_USE)
 	{
 		UDF_I_LENALLOC(inode) =
 			le32_to_cpu(
-				((struct UnallocatedSpaceEntry *)bh->b_data)->lengthAllocDescs);
+				((struct unallocSpaceEntry *)bh->b_data)->lengthAllocDescs);
 		return;
 	}
 
@@ -1123,7 +1120,7 @@
 		UDF_I_UNIQUE(inode) = le64_to_cpu(fe->uniqueID);
 		UDF_I_LENEATTR(inode) = le32_to_cpu(fe->lengthExtendedAttr);
 		UDF_I_LENALLOC(inode) = le32_to_cpu(fe->lengthAllocDescs);
-		offset = sizeof(struct FileEntry) + UDF_I_LENEATTR(inode);
+		offset = sizeof(struct fileEntry) + UDF_I_LENEATTR(inode);
 		alen = offset + UDF_I_LENALLOC(inode);
 	}
 	else
@@ -1180,13 +1177,13 @@
 		UDF_I_UNIQUE(inode) = le64_to_cpu(efe->uniqueID);
 		UDF_I_LENEATTR(inode) = le32_to_cpu(efe->lengthExtendedAttr);
 		UDF_I_LENALLOC(inode) = le32_to_cpu(efe->lengthAllocDescs);
-		offset = sizeof(struct ExtendedFileEntry) + UDF_I_LENEATTR(inode);
+		offset = sizeof(struct extendedFileEntry) + UDF_I_LENEATTR(inode);
 		alen = offset + UDF_I_LENALLOC(inode);
 	}
 
 	switch (fe->icbTag.fileType)
 	{
-		case FILE_TYPE_DIRECTORY:
+		case ICBTAG_FILE_TYPE_DIRECTORY:
 		{
 			inode->i_op = &udf_dir_inode_operations;
 			inode->i_fop = &udf_dir_operations;
@@ -1194,11 +1191,11 @@
 			inode->i_nlink ++;
 			break;
 		}
-		case FILE_TYPE_REALTIME:
-		case FILE_TYPE_REGULAR:
-		case FILE_TYPE_NONE:
+		case ICBTAG_FILE_TYPE_REALTIME:
+		case ICBTAG_FILE_TYPE_REGULAR:
+		case ICBTAG_FILE_TYPE_UNDEF:
 		{
-			if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+			if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 				inode->i_data.a_ops = &udf_adinicb_aops;
 			else
 				inode->i_data.a_ops = &udf_aops;
@@ -1207,22 +1204,22 @@
 			inode->i_mode |= S_IFREG;
 			break;
 		}
-		case FILE_TYPE_BLOCK:
+		case ICBTAG_FILE_TYPE_BLOCK:
 		{
 			inode->i_mode |= S_IFBLK;
 			break;
 		}
-		case FILE_TYPE_CHAR:
+		case ICBTAG_FILE_TYPE_CHAR:
 		{
 			inode->i_mode |= S_IFCHR;
 			break;
 		}
-		case FILE_TYPE_FIFO:
+		case ICBTAG_FILE_TYPE_FIFO:
 		{
 			init_special_inode(inode, inode->i_mode | S_IFIFO, 0);
 			break;
 		}
-		case FILE_TYPE_SYMLINK:
+		case ICBTAG_FILE_TYPE_SYMLINK:
 		{
 			inode->i_data.a_ops = &udf_symlink_aops;
 			inode->i_op = &page_symlink_inode_operations;
@@ -1240,8 +1237,8 @@
 	if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode))
 	{
 		struct buffer_head *tbh = NULL;
-		struct DeviceSpecificationExtendedAttr *dsea =
-			(struct DeviceSpecificationExtendedAttr *)
+		struct deviceSpec *dsea =
+			(struct deviceSpec *)
 				udf_get_extendedattr(inode, 12, 1, &tbh);
 
 		if (dsea)
@@ -1260,11 +1257,11 @@
 }
 
 static mode_t
-udf_convert_permissions(struct FileEntry *fe)
+udf_convert_permissions(struct fileEntry *fe)
 {
 	mode_t mode;
-	Uint32 permissions;
-	Uint32 flags;
+	uint32_t permissions;
+	uint32_t flags;
 
 	permissions = le32_to_cpu(fe->permissions);
 	flags = le16_to_cpu(fe->icbTag.flags);
@@ -1272,9 +1269,9 @@
 	mode =	(( permissions      ) & S_IRWXO) |
 		(( permissions >> 2 ) & S_IRWXG) |
 		(( permissions >> 4 ) & S_IRWXU) |
-		(( flags & ICB_FLAG_SETUID) ? S_ISUID : 0) |
-		(( flags & ICB_FLAG_SETGID) ? S_ISGID : 0) |
-		(( flags & ICB_FLAG_STICKY) ? S_ISVTX : 0);
+		(( flags & ICBTAG_FLAG_SETUID) ? S_ISUID : 0) |
+		(( flags & ICBTAG_FLAG_SETGID) ? S_ISGID : 0) |
+		(( flags & ICBTAG_FLAG_STICKY) ? S_ISVTX : 0);
 
 	return mode;
 }
@@ -1310,11 +1307,11 @@
 udf_update_inode(struct inode *inode, int do_sync)
 {
 	struct buffer_head *bh = NULL;
-	struct FileEntry *fe;
-	struct ExtendedFileEntry *efe;
-	Uint32 udfperms;
-	Uint16 icbflags;
-	Uint16 crclen;
+	struct fileEntry *fe;
+	struct extendedFileEntry *efe;
+	uint32_t udfperms;
+	uint16_t icbflags;
+	uint16_t crclen;
 	int i;
 	timestamp cpu_time;
 	int err = 0;
@@ -1327,35 +1324,36 @@
 		udf_debug("bread failure\n");
 		return -EIO;
 	}
-	fe = (struct FileEntry *)bh->b_data;
-	efe = (struct ExtendedFileEntry *)bh->b_data;
+	fe = (struct fileEntry *)bh->b_data;
+	efe = (struct extendedFileEntry *)bh->b_data;
 	if (UDF_I_NEW_INODE(inode) == 1)
 	{
 		if (UDF_I_EXTENDED_FE(inode) == 0)
-			memset(bh->b_data, 0x00, sizeof(struct FileEntry));
+			memset(bh->b_data, 0x00, sizeof(struct fileEntry));
 		else
-			memset(bh->b_data, 0x00, sizeof(struct ExtendedFileEntry));
+			memset(bh->b_data, 0x00, sizeof(struct extendedFileEntry));
 		memset(bh->b_data + udf_file_entry_alloc_offset(inode) +
 			UDF_I_LENALLOC(inode), 0x0, inode->i_sb->s_blocksize -
 			udf_file_entry_alloc_offset(inode) - UDF_I_LENALLOC(inode));
 		UDF_I_NEW_INODE(inode) = 0;
 	}
 
-	if (fe->descTag.tagIdent == TID_UNALLOCATED_SPACE_ENTRY)
+	if (le16_to_cpu(fe->descTag.tagIdent) == TAG_IDENT_USE)
 	{
-		struct UnallocatedSpaceEntry *use =
-			(struct UnallocatedSpaceEntry *)bh->b_data;
+		struct unallocSpaceEntry *use =
+			(struct unallocSpaceEntry *)bh->b_data;
 
 		use->lengthAllocDescs = cpu_to_le32(UDF_I_LENALLOC(inode));
-		crclen = sizeof(struct UnallocatedSpaceEntry) + UDF_I_LENALLOC(inode) -
+		crclen = sizeof(struct unallocSpaceEntry) + UDF_I_LENALLOC(inode) -
 			sizeof(tag);
+		use->descTag.tagLocation = cpu_to_le32(UDF_I_LOCATION(inode).logicalBlockNum);
 		use->descTag.descCRCLength = cpu_to_le16(crclen);
 		use->descTag.descCRC = cpu_to_le16(udf_crc((char *)use + sizeof(tag), crclen, 0));
 
 		use->descTag.tagChecksum = 0;
 		for (i=0; i<16; i++)
 			if (i != 4)
-				use->descTag.tagChecksum += ((Uint8 *)&(use->descTag))[i];
+				use->descTag.tagChecksum += ((uint8_t *)&(use->descTag))[i];
 
 		mark_buffer_dirty(bh);
 		udf_release_data(bh);
@@ -1373,9 +1371,9 @@
 			((inode->i_mode & S_IRWXU) << 4);
 
 	udfperms |=	(le32_to_cpu(fe->permissions) &
-			(PERM_O_DELETE | PERM_O_CHATTR |
-			 PERM_G_DELETE | PERM_G_CHATTR |
-			 PERM_U_DELETE | PERM_U_CHATTR));
+			(FE_PERM_O_DELETE | FE_PERM_O_CHATTR |
+			 FE_PERM_G_DELETE | FE_PERM_G_CHATTR |
+			 FE_PERM_U_DELETE | FE_PERM_U_CHATTR));
 	fe->permissions = cpu_to_le32(udfperms);
 
 	if (S_ISDIR(inode->i_mode))
@@ -1387,26 +1385,26 @@
 
 	if (S_ISCHR(inode->i_mode) || S_ISBLK(inode->i_mode))
 	{
-		EntityID *eid;
+		regid *eid;
 		struct buffer_head *tbh = NULL;
-		struct DeviceSpecificationExtendedAttr *dsea =
-			(struct DeviceSpecificationExtendedAttr *)
+		struct deviceSpec *dsea =
+			(struct deviceSpec *)
 				udf_get_extendedattr(inode, 12, 1, &tbh);	
 
 		if (!dsea)
 		{
-			dsea = (struct DeviceSpecificationExtendedAttr *)
+			dsea = (struct deviceSpec *)
 				udf_add_extendedattr(inode,
-					sizeof(struct DeviceSpecificationExtendedAttr) +
-					sizeof(EntityID), 12, 0x3, &tbh);
+					sizeof(struct deviceSpec) +
+					sizeof(regid), 12, 0x3, &tbh);
 			dsea->attrType = 12;
 			dsea->attrSubtype = 1;
-			dsea->attrLength = sizeof(struct DeviceSpecificationExtendedAttr) +
-				sizeof(EntityID);
-			dsea->impUseLength = sizeof(EntityID);
+			dsea->attrLength = sizeof(struct deviceSpec) +
+				sizeof(regid);
+			dsea->impUseLength = sizeof(regid);
 		}
-		eid = (EntityID *)dsea->impUse;
-		memset(eid, 0, sizeof(EntityID));
+		eid = (regid *)dsea->impUse;
+		memset(eid, 0, sizeof(regid));
 		strcpy(eid->ident, UDF_ID_DEVELOPER);
 		eid->identSuffix[0] = UDF_OS_CLASS_UNIX;
 		eid->identSuffix[1] = UDF_OS_ID_LINUX;
@@ -1428,15 +1426,15 @@
 			fe->modificationTime = cpu_to_lets(cpu_time);
 		if (udf_time_to_stamp(&cpu_time, inode->i_ctime, UDF_I_UCTIME(inode)))
 			fe->attrTime = cpu_to_lets(cpu_time);
-		memset(&(fe->impIdent), 0, sizeof(EntityID));
+		memset(&(fe->impIdent), 0, sizeof(regid));
 		strcpy(fe->impIdent.ident, UDF_ID_DEVELOPER);
 		fe->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
 		fe->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
 		fe->uniqueID = cpu_to_le64(UDF_I_UNIQUE(inode));
 		fe->lengthExtendedAttr = cpu_to_le32(UDF_I_LENEATTR(inode));
 		fe->lengthAllocDescs = cpu_to_le32(UDF_I_LENALLOC(inode));
-		fe->descTag.tagIdent = le16_to_cpu(TID_FILE_ENTRY);
-		crclen = sizeof(struct FileEntry);
+		fe->descTag.tagIdent = le16_to_cpu(TAG_IDENT_FE);
+		crclen = sizeof(struct fileEntry);
 	}
 	else
 	{
@@ -1474,15 +1472,15 @@
 		if (udf_time_to_stamp(&cpu_time, inode->i_ctime, UDF_I_UCTIME(inode)))
 			efe->attrTime = cpu_to_lets(cpu_time);
 
-		memset(&(efe->impIdent), 0, sizeof(EntityID));
+		memset(&(efe->impIdent), 0, sizeof(regid));
 		strcpy(efe->impIdent.ident, UDF_ID_DEVELOPER);
 		efe->impIdent.identSuffix[0] = UDF_OS_CLASS_UNIX;
 		efe->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
 		efe->uniqueID = cpu_to_le64(UDF_I_UNIQUE(inode));
 		efe->lengthExtendedAttr = cpu_to_le32(UDF_I_LENEATTR(inode));
 		efe->lengthAllocDescs = cpu_to_le32(UDF_I_LENALLOC(inode));
-		efe->descTag.tagIdent = le16_to_cpu(TID_EXTENDED_FILE_ENTRY);
-		crclen = sizeof(struct ExtendedFileEntry);
+		efe->descTag.tagIdent = le16_to_cpu(TAG_IDENT_EFE);
+		crclen = sizeof(struct extendedFileEntry);
 	}
 	if (UDF_I_STRAT4096(inode))
 	{
@@ -1497,28 +1495,31 @@
 	}
 
 	if (S_ISDIR(inode->i_mode))
-		fe->icbTag.fileType = FILE_TYPE_DIRECTORY;
+		fe->icbTag.fileType = ICBTAG_FILE_TYPE_DIRECTORY;
 	else if (S_ISREG(inode->i_mode))
-		fe->icbTag.fileType = FILE_TYPE_REGULAR;
+		fe->icbTag.fileType = ICBTAG_FILE_TYPE_REGULAR;
 	else if (S_ISLNK(inode->i_mode))
-		fe->icbTag.fileType = FILE_TYPE_SYMLINK;
+		fe->icbTag.fileType = ICBTAG_FILE_TYPE_SYMLINK;
 	else if (S_ISBLK(inode->i_mode))
-		fe->icbTag.fileType = FILE_TYPE_BLOCK;
+		fe->icbTag.fileType = ICBTAG_FILE_TYPE_BLOCK;
 	else if (S_ISCHR(inode->i_mode))
-		fe->icbTag.fileType = FILE_TYPE_CHAR;
+		fe->icbTag.fileType = ICBTAG_FILE_TYPE_CHAR;
 	else if (S_ISFIFO(inode->i_mode))
-		fe->icbTag.fileType = FILE_TYPE_FIFO;
+		fe->icbTag.fileType = ICBTAG_FILE_TYPE_FIFO;
 
 	icbflags =	UDF_I_ALLOCTYPE(inode) |
-			((inode->i_mode & S_ISUID) ? ICB_FLAG_SETUID : 0) |
-			((inode->i_mode & S_ISGID) ? ICB_FLAG_SETGID : 0) |
-			((inode->i_mode & S_ISVTX) ? ICB_FLAG_STICKY : 0) |
+			((inode->i_mode & S_ISUID) ? ICBTAG_FLAG_SETUID : 0) |
+			((inode->i_mode & S_ISGID) ? ICBTAG_FLAG_SETGID : 0) |
+			((inode->i_mode & S_ISVTX) ? ICBTAG_FLAG_STICKY : 0) |
 			(le16_to_cpu(fe->icbTag.flags) &
-				~(ICB_FLAG_ALLOC_MASK | ICB_FLAG_SETUID |
-				ICB_FLAG_SETGID | ICB_FLAG_STICKY));
+				~(ICBTAG_FLAG_AD_MASK | ICBTAG_FLAG_SETUID |
+				ICBTAG_FLAG_SETGID | ICBTAG_FLAG_STICKY));
 
 	fe->icbTag.flags = cpu_to_le16(icbflags);
-	fe->descTag.descVersion = cpu_to_le16(2);
+	if (UDF_SB_UDFREV(inode->i_sb) >= 0x0200)
+		fe->descTag.descVersion = cpu_to_le16(3);
+	else
+		fe->descTag.descVersion = cpu_to_le16(2);
 	fe->descTag.tagSerialNum = cpu_to_le16(UDF_SB_SERIALNUM(inode->i_sb));
 	fe->descTag.tagLocation = cpu_to_le32(UDF_I_LOCATION(inode).logicalBlockNum);
 	crclen += UDF_I_LENEATTR(inode) + UDF_I_LENALLOC(inode) - sizeof(tag);
@@ -1528,7 +1529,7 @@
 	fe->descTag.tagChecksum = 0;
 	for (i=0; i<16; i++)
 		if (i != 4)
-			fe->descTag.tagChecksum += ((Uint8 *)&(fe->descTag))[i];
+			fe->descTag.tagChecksum += ((uint8_t *)&(fe->descTag))[i];
 
 	/* write the data blocks */
 	mark_buffer_dirty(bh);
@@ -1609,14 +1610,14 @@
 	return inode;
 }
 
-Sint8 udf_add_aext(struct inode *inode, lb_addr *bloc, int *extoffset,
-	lb_addr eloc, Uint32 elen, struct buffer_head **bh, int inc)
+int8_t udf_add_aext(struct inode *inode, lb_addr *bloc, int *extoffset,
+	lb_addr eloc, uint32_t elen, struct buffer_head **bh, int inc)
 {
 	int adsize;
 	short_ad *sad = NULL;
 	long_ad *lad = NULL;
-	struct AllocExtDesc *aed;
-	int ret;
+	struct allocExtDesc *aed;
+	int8_t etype;
 
 	if (!(*bh))
 	{
@@ -1629,9 +1630,9 @@
 		}
 	}
 
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
 		adsize = sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
 		adsize = sizeof(long_ad);
 	else
 		return -1;
@@ -1659,7 +1660,7 @@
 		unlock_buffer(nbh);
 		mark_buffer_dirty_inode(nbh, inode);
 
-		aed = (struct AllocExtDesc *)(nbh->b_data);
+		aed = (struct allocExtDesc *)(nbh->b_data);
 		if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT))
 			aed->previousAllocExtLocation = cpu_to_le32(obloc.logicalBlockNum);
 		if (*extoffset + adsize > inode->i_sb->s_blocksize)
@@ -1667,20 +1668,20 @@
 			loffset = *extoffset;
 			aed->lengthAllocDescs = cpu_to_le32(adsize);
 			sptr = (*bh)->b_data + *extoffset - adsize;
-			dptr = nbh->b_data + sizeof(struct AllocExtDesc);
+			dptr = nbh->b_data + sizeof(struct allocExtDesc);
 			memcpy(dptr, sptr, adsize);
-			*extoffset = sizeof(struct AllocExtDesc) + adsize;
+			*extoffset = sizeof(struct allocExtDesc) + adsize;
 		}
 		else
 		{
 			loffset = *extoffset + adsize;
 			aed->lengthAllocDescs = cpu_to_le32(0);
 			sptr = (*bh)->b_data + *extoffset;
-			*extoffset = sizeof(struct AllocExtDesc);
+			*extoffset = sizeof(struct allocExtDesc);
 
 			if (memcmp(&UDF_I_LOCATION(inode), &obloc, sizeof(lb_addr)))
 			{
-				aed = (struct AllocExtDesc *)(*bh)->b_data;
+				aed = (struct allocExtDesc *)(*bh)->b_data;
 				aed->lengthAllocDescs =
 					cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
 			}
@@ -1690,24 +1691,28 @@
 				mark_inode_dirty(inode);
 			}
 		}
-		udf_new_tag(nbh->b_data, TID_ALLOC_EXTENT_DESC, 2, 1,
-			bloc->logicalBlockNum, sizeof(tag));
+		if (UDF_SB_UDFREV(inode->i_sb) >= 0x0200)
+			udf_new_tag(nbh->b_data, TAG_IDENT_AED, 3, 1,
+				bloc->logicalBlockNum, sizeof(tag));
+		else
+			udf_new_tag(nbh->b_data, TAG_IDENT_AED, 2, 1,
+				bloc->logicalBlockNum, sizeof(tag));
 		switch (UDF_I_ALLOCTYPE(inode))
 		{
-			case ICB_FLAG_AD_SHORT:
+			case ICBTAG_FLAG_AD_SHORT:
 			{
 				sad = (short_ad *)sptr;
 				sad->extLength = cpu_to_le32(
-					EXTENT_NEXT_EXTENT_ALLOCDECS << 30 |
+					EXT_NEXT_EXTENT_ALLOCDECS |
 					inode->i_sb->s_blocksize);
 				sad->extPosition = cpu_to_le32(bloc->logicalBlockNum);
 				break;
 			}
-			case ICB_FLAG_AD_LONG:
+			case ICBTAG_FLAG_AD_LONG:
 			{
 				lad = (long_ad *)sptr;
 				lad->extLength = cpu_to_le32(
-					EXTENT_NEXT_EXTENT_ALLOCDECS << 30 |
+					EXT_NEXT_EXTENT_ALLOCDECS |
 					inode->i_sb->s_blocksize);
 				lad->extLocation = cpu_to_lelb(*bloc);
 				memset(lad->impUse, 0x00, sizeof(lad->impUse));
@@ -1717,13 +1722,13 @@
 		if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 			udf_update_tag((*bh)->b_data, loffset);
 		else
-			udf_update_tag((*bh)->b_data, sizeof(struct AllocExtDesc));
+			udf_update_tag((*bh)->b_data, sizeof(struct allocExtDesc));
 		mark_buffer_dirty_inode(*bh, inode);
 		udf_release_data(*bh);
 		*bh = nbh;
 	}
 
-	ret = udf_write_aext(inode, *bloc, extoffset, eloc, elen, *bh, inc);
+	etype = udf_write_aext(inode, *bloc, extoffset, eloc, elen, *bh, inc);
 
 	if (!memcmp(&UDF_I_LOCATION(inode), bloc, sizeof(lb_addr)))
 	{
@@ -1732,21 +1737,21 @@
 	}
 	else
 	{
-		aed = (struct AllocExtDesc *)(*bh)->b_data;
+		aed = (struct allocExtDesc *)(*bh)->b_data;
 		aed->lengthAllocDescs =
 			cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) + adsize);
 		if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 			udf_update_tag((*bh)->b_data, *extoffset + (inc ? 0 : adsize));
 		else
-			udf_update_tag((*bh)->b_data, sizeof(struct AllocExtDesc));
+			udf_update_tag((*bh)->b_data, sizeof(struct allocExtDesc));
 		mark_buffer_dirty_inode(*bh, inode);
 	}
 
-	return ret;
+	return etype;
 }
 
-Sint8 udf_write_aext(struct inode *inode, lb_addr bloc, int *extoffset,
-    lb_addr eloc, Uint32 elen, struct buffer_head *bh, int inc)
+int8_t udf_write_aext(struct inode *inode, lb_addr bloc, int *extoffset,
+    lb_addr eloc, uint32_t elen, struct buffer_head *bh, int inc)
 {
 	int adsize;
 	short_ad *sad = NULL;
@@ -1765,23 +1770,23 @@
 	else
 		atomic_inc(&bh->b_count);
 
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
 		adsize = sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
 		adsize = sizeof(long_ad);
 	else
 		return -1;
 
 	switch (UDF_I_ALLOCTYPE(inode))
 	{
-		case ICB_FLAG_AD_SHORT:
+		case ICBTAG_FLAG_AD_SHORT:
 		{
 			sad = (short_ad *)((bh)->b_data + *extoffset);
 			sad->extLength = cpu_to_le32(elen);
 			sad->extPosition = cpu_to_le32(eloc.logicalBlockNum);
 			break;
 		}
-		case ICB_FLAG_AD_LONG:
+		case ICBTAG_FLAG_AD_LONG:
 		{
 			lad = (long_ad *)((bh)->b_data + *extoffset);
 			lad->extLength = cpu_to_le32(elen);
@@ -1795,9 +1800,9 @@
 	{
 		if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 		{
-			struct AllocExtDesc *aed = (struct AllocExtDesc *)(bh)->b_data;
+			struct allocExtDesc *aed = (struct allocExtDesc *)(bh)->b_data;
 			udf_update_tag((bh)->b_data,
-				le32_to_cpu(aed->lengthAllocDescs) + sizeof(struct AllocExtDesc));
+				le32_to_cpu(aed->lengthAllocDescs) + sizeof(struct allocExtDesc));
 		}
 		mark_buffer_dirty_inode(bh, inode);
 	}
@@ -1813,12 +1818,12 @@
 	return (elen >> 30);
 }
 
-Sint8 udf_next_aext(struct inode *inode, lb_addr *bloc, int *extoffset,
-	lb_addr *eloc, Uint32 *elen, struct buffer_head **bh, int inc)
+int8_t udf_next_aext(struct inode *inode, lb_addr *bloc, int *extoffset,
+	lb_addr *eloc, uint32_t *elen, struct buffer_head **bh, int inc)
 {
-	Uint16 tagIdent;
+	uint16_t tagIdent;
 	int pos, alen;
-	Sint8 etype;
+	int8_t etype;
 
 	if (!(*bh))
 	{
@@ -1831,29 +1836,29 @@
 		}
 	}
 
-	tagIdent = ((tag *)(*bh)->b_data)->tagIdent;
+	tagIdent = le16_to_cpu(((tag *)(*bh)->b_data)->tagIdent);
 
 	if (!memcmp(&UDF_I_LOCATION(inode), bloc, sizeof(lb_addr)))
 	{
-		if (tagIdent == TID_FILE_ENTRY || tagIdent == TID_EXTENDED_FILE_ENTRY ||
+		if (tagIdent == TAG_IDENT_FE || tagIdent == TAG_IDENT_EFE ||
 			UDF_I_NEW_INODE(inode))
 		{
 			pos = udf_file_entry_alloc_offset(inode);
 			alen = UDF_I_LENALLOC(inode) + pos;
 		}
-		else if (tagIdent == TID_UNALLOCATED_SPACE_ENTRY)
+		else if (tagIdent == TAG_IDENT_USE)
 		{
-			pos = sizeof(struct UnallocatedSpaceEntry);
+			pos = sizeof(struct unallocSpaceEntry);
 			alen = UDF_I_LENALLOC(inode) + pos;
 		}
 		else
 			return -1;
 	}
-	else if (tagIdent == TID_ALLOC_EXTENT_DESC)
+	else if (tagIdent == TAG_IDENT_AED)
 	{
-		struct AllocExtDesc *aed = (struct AllocExtDesc *)(*bh)->b_data;
+		struct allocExtDesc *aed = (struct allocExtDesc *)(*bh)->b_data;
 
-		pos = sizeof(struct AllocExtDesc);
+		pos = sizeof(struct allocExtDesc);
 		alen = le32_to_cpu(aed->lengthAllocDescs) + pos;
 	}
 	else
@@ -1864,14 +1869,14 @@
 
 	switch (UDF_I_ALLOCTYPE(inode))
 	{
-		case ICB_FLAG_AD_SHORT:
+		case ICBTAG_FLAG_AD_SHORT:
 		{
 			short_ad *sad;
 
 			if (!(sad = udf_get_fileshortad((*bh)->b_data, alen, extoffset, inc)))
 				return -1;
 
-			if ((etype = le32_to_cpu(sad->extLength) >> 30) == EXTENT_NEXT_EXTENT_ALLOCDECS)
+			if ((etype = le32_to_cpu(sad->extLength) >> 30) == (EXT_NEXT_EXTENT_ALLOCDECS >> 30))
 			{
 				bloc->logicalBlockNum = le32_to_cpu(sad->extPosition);
 				*extoffset = 0;
@@ -1887,14 +1892,14 @@
 			}
 			break;
 		}
-		case ICB_FLAG_AD_LONG:
+		case ICBTAG_FLAG_AD_LONG:
 		{
 			long_ad *lad;
 
 			if (!(lad = udf_get_filelongad((*bh)->b_data, alen, extoffset, inc)))
 				return -1;
 
-			if ((etype = le32_to_cpu(lad->extLength) >> 30) == EXTENT_NEXT_EXTENT_ALLOCDECS)
+			if ((etype = le32_to_cpu(lad->extLength) >> 30) == (EXT_NEXT_EXTENT_ALLOCDECS >> 30))
 			{
 				*bloc = lelb_to_cpu(lad->extLocation);
 				*extoffset = 0;
@@ -1909,11 +1914,11 @@
 			}
 			break;
 		}
-		case ICB_FLAG_AD_IN_ICB:
+		case ICBTAG_FLAG_AD_IN_ICB:
 		{
 			if (UDF_I_LENALLOC(inode) == 0)
 				return -1;
-			etype = EXTENT_RECORDED_ALLOCATED;
+			etype = (EXT_RECORDED_ALLOCATED >> 30);
 			*eloc = UDF_I_LOCATION(inode);
 			*elen = UDF_I_LENALLOC(inode);
 			break;
@@ -1929,18 +1934,18 @@
 
 	udf_debug("Empty Extent, inode=%ld, alloctype=%d, eloc=%d, elen=%d, etype=%d, extoffset=%d\n",
 		inode->i_ino, UDF_I_ALLOCTYPE(inode), eloc->logicalBlockNum, *elen, etype, *extoffset);
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
 		*extoffset -= sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
 		*extoffset -= sizeof(long_ad);
 	return -1;
 }
 
-Sint8 udf_current_aext(struct inode *inode, lb_addr *bloc, int *extoffset,
-	lb_addr *eloc, Uint32 *elen, struct buffer_head **bh, int inc)
+int8_t udf_current_aext(struct inode *inode, lb_addr *bloc, int *extoffset,
+	lb_addr *eloc, uint32_t *elen, struct buffer_head **bh, int inc)
 {
 	int pos, alen;
-	Sint8 etype;
+	int8_t etype;
 
 	if (!(*bh))
 	{
@@ -1956,16 +1961,16 @@
 	if (!memcmp(&UDF_I_LOCATION(inode), bloc, sizeof(lb_addr)))
 	{
 		if (!(UDF_I_EXTENDED_FE(inode)))
-			pos = sizeof(struct FileEntry) + UDF_I_LENEATTR(inode);
+			pos = sizeof(struct fileEntry) + UDF_I_LENEATTR(inode);
 		else
-			pos = sizeof(struct ExtendedFileEntry) + UDF_I_LENEATTR(inode);
+			pos = sizeof(struct extendedFileEntry) + UDF_I_LENEATTR(inode);
 		alen = UDF_I_LENALLOC(inode) + pos;
 	}
 	else
 	{
-		struct AllocExtDesc *aed = (struct AllocExtDesc *)(*bh)->b_data;
+		struct allocExtDesc *aed = (struct allocExtDesc *)(*bh)->b_data;
 
-		pos = sizeof(struct AllocExtDesc);
+		pos = sizeof(struct allocExtDesc);
 		alen = le32_to_cpu(aed->lengthAllocDescs) + pos;
 	}
 
@@ -1974,7 +1979,7 @@
 
 	switch (UDF_I_ALLOCTYPE(inode))
 	{
-		case ICB_FLAG_AD_SHORT:
+		case ICBTAG_FLAG_AD_SHORT:
 		{
 			short_ad *sad;
 
@@ -1987,7 +1992,7 @@
 			*elen = le32_to_cpu(sad->extLength) & UDF_EXTENT_LENGTH_MASK;
 			break;
 		}
-		case ICB_FLAG_AD_LONG:
+		case ICBTAG_FLAG_AD_LONG:
 		{
 			long_ad *lad;
 
@@ -2009,19 +2014,19 @@
 		return etype;
 
 	udf_debug("Empty Extent!\n");
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
 		*extoffset -= sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
 		*extoffset -= sizeof(long_ad);
 	return -1;
 }
 
-Sint8 udf_insert_aext(struct inode *inode, lb_addr bloc, int extoffset,
-	lb_addr neloc, Uint32 nelen, struct buffer_head *bh)
+int8_t udf_insert_aext(struct inode *inode, lb_addr bloc, int extoffset,
+	lb_addr neloc, uint32_t nelen, struct buffer_head *bh)
 {
 	lb_addr oeloc;
-	Uint32 oelen;
-	Sint8 etype;
+	uint32_t oelen;
+	int8_t etype;
 
 	if (!bh)
 	{
@@ -2048,14 +2053,14 @@
 	return (nelen >> 30);
 }
 
-Sint8 udf_delete_aext(struct inode *inode, lb_addr nbloc, int nextoffset,
-	lb_addr eloc, Uint32 elen, struct buffer_head *nbh)
+int8_t udf_delete_aext(struct inode *inode, lb_addr nbloc, int nextoffset,
+	lb_addr eloc, uint32_t elen, struct buffer_head *nbh)
 {
 	struct buffer_head *obh;
 	lb_addr obloc;
 	int oextoffset, adsize;
-	Sint8 etype;
-	struct AllocExtDesc *aed;
+	int8_t etype;
+	struct allocExtDesc *aed;
 
 	if (!(nbh))
 	{
@@ -2071,9 +2076,9 @@
 		atomic_inc(&nbh->b_count);
 	atomic_inc(&nbh->b_count);
 
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
 		adsize = sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
 		adsize = sizeof(long_ad);
 	else
 		adsize = 0;
@@ -2112,13 +2117,13 @@
 		}
 		else
 		{
-			aed = (struct AllocExtDesc *)(obh)->b_data;
+			aed = (struct allocExtDesc *)(obh)->b_data;
 			aed->lengthAllocDescs =
 				cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) - (2*adsize));
 			if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 				udf_update_tag((obh)->b_data, oextoffset - (2*adsize));
 			else
-				udf_update_tag((obh)->b_data, sizeof(struct AllocExtDesc));
+				udf_update_tag((obh)->b_data, sizeof(struct allocExtDesc));
 			mark_buffer_dirty_inode(obh, inode);
 		}
 	}
@@ -2132,13 +2137,13 @@
 		}
 		else
 		{
-			aed = (struct AllocExtDesc *)(obh)->b_data;
+			aed = (struct allocExtDesc *)(obh)->b_data;
 			aed->lengthAllocDescs =
 				cpu_to_le32(le32_to_cpu(aed->lengthAllocDescs) - adsize);
 			if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 				udf_update_tag((obh)->b_data, oextoffset - adsize);
 			else
-				udf_update_tag((obh)->b_data, sizeof(struct AllocExtDesc));
+				udf_update_tag((obh)->b_data, sizeof(struct allocExtDesc));
 			mark_buffer_dirty_inode(obh, inode);
 		}
 	}
@@ -2148,11 +2153,11 @@
 	return (elen >> 30);
 }
 
-Sint8 inode_bmap(struct inode *inode, int block, lb_addr *bloc, Uint32 *extoffset,
-	lb_addr *eloc, Uint32 *elen, Uint32 *offset, struct buffer_head **bh)
+int8_t inode_bmap(struct inode *inode, int block, lb_addr *bloc, uint32_t *extoffset,
+	lb_addr *eloc, uint32_t *elen, uint32_t *offset, struct buffer_head **bh)
 {
-	Uint64 lbcount = 0, bcount = (Uint64)block << inode->i_sb->s_blocksize_bits;
-	Sint8 etype;
+	uint64_t lbcount = 0, bcount = (uint64_t)block << inode->i_sb->s_blocksize_bits;
+	int8_t etype;
 
 	if (block < 0)
 	{
@@ -2188,13 +2193,13 @@
 long udf_block_map(struct inode *inode, long block)
 {
 	lb_addr eloc, bloc;
-	Uint32 offset, extoffset, elen;
+	uint32_t offset, extoffset, elen;
 	struct buffer_head *bh = NULL;
 	int ret;
 
 	lock_kernel();
 
-	if (inode_bmap(inode, block, &bloc, &extoffset, &eloc, &elen, &offset, &bh) == EXTENT_RECORDED_ALLOCATED)
+	if (inode_bmap(inode, block, &bloc, &extoffset, &eloc, &elen, &offset, &bh) == (EXT_RECORDED_ALLOCATED >> 30))
 		ret = udf_get_lb_pblock(inode->i_sb, eloc, offset >> inode->i_sb->s_blocksize_bits);
 	else
 		ret = 0;
diff -Nru a/fs/udf/lowlevel.c b/fs/udf/lowlevel.c
--- a/fs/udf/lowlevel.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/lowlevel.c	Fri Mar 15 17:51:01 2002
@@ -15,7 +15,7 @@
  *		ftp://prep.ai.mit.edu/pub/gnu/GPL
  *	Each contributing author retains all rights to their own work.
  *
- *  (C) 1999-2000 Ben Fennema
+ *  (C) 1999-2001 Ben Fennema
  *
  * HISTORY
  *
diff -Nru a/fs/udf/misc.c b/fs/udf/misc.c
--- a/fs/udf/misc.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/misc.c	Fri Mar 15 17:51:01 2002
@@ -16,7 +16,7 @@
  *	Each contributing author retains all rights to their own work.
  *
  *  (C) 1998 Dave Boynton
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *  (C) 1999-2000 Stelias Computing Inc
  *
  * HISTORY
@@ -26,46 +26,25 @@
 
 #include "udfdecl.h"
 
-#if defined(__linux__) && defined(__KERNEL__)
-
-#include "udf_sb.h"
-#include "udf_i.h"
-
 #include <linux/fs.h>
 #include <linux/string.h>
 #include <linux/udf_fs.h>
 
-#else
-
-#include <sys/types.h>
-#include <stdio.h>
-#include <unistd.h>
-#include <string.h>
-
-int udf_blocksize=0;
-int udf_errno=0;
-
-void 
-udf_setblocksize(int size)
-{
-	udf_blocksize=size;
-}
-#endif
+#include "udf_i.h"
+#include "udf_sb.h"
 
-Uint32
-udf64_low32(Uint64 indat)
+uint32_t
+udf64_low32(uint64_t indat)
 {
 	return indat & 0x00000000FFFFFFFFULL;
 }
 
-Uint32
-udf64_high32(Uint64 indat)
+uint32_t
+udf64_high32(uint64_t indat)
 {
 	return indat >> 32;
 }
 
-#if defined(__linux__) && defined(__KERNEL__)
-
 extern struct buffer_head *
 udf_tgetblk(struct super_block *sb, int block)
 {
@@ -84,11 +63,11 @@
 		return sb_bread(sb, block);
 }
 
-extern struct GenericAttrFormat *
-udf_add_extendedattr(struct inode * inode, Uint32 size, Uint32 type,
-	Uint8 loc, struct buffer_head **bh)
+extern struct genericFormat *
+udf_add_extendedattr(struct inode * inode, uint32_t size, uint32_t type,
+	uint8_t loc, struct buffer_head **bh)
 {
-	Uint8 *ea = NULL, *ad = NULL;
+	uint8_t *ea = NULL, *ad = NULL;
 	long_ad eaicb;
 	int offset;
 
@@ -96,26 +75,26 @@
 
 	if (UDF_I_EXTENDED_FE(inode) == 0)
 	{
-		struct FileEntry *fe;
+		struct fileEntry *fe;
 
-		fe = (struct FileEntry *)(*bh)->b_data;
+		fe = (struct fileEntry *)(*bh)->b_data;
 		eaicb = lela_to_cpu(fe->extendedAttrICB);
-		offset = sizeof(struct FileEntry);
+		offset = sizeof(struct fileEntry);
 	}
 	else
 	{
-		struct ExtendedFileEntry *efe;
+		struct extendedFileEntry *efe;
 
-		efe = (struct ExtendedFileEntry *)(*bh)->b_data;
+		efe = (struct extendedFileEntry *)(*bh)->b_data;
 		eaicb = lela_to_cpu(efe->extendedAttrICB);
-		offset = sizeof(struct ExtendedFileEntry);
+		offset = sizeof(struct extendedFileEntry);
 	}
 
 	ea = &(*bh)->b_data[offset];
 	if (UDF_I_LENEATTR(inode))
 		offset += UDF_I_LENEATTR(inode);
 	else
-		size += sizeof(struct ExtendedAttrHeaderDesc);
+		size += sizeof(struct extendedAttrHeaderDesc);
 
 	ad = &(*bh)->b_data[offset];
 	if (UDF_I_LENALLOC(inode))
@@ -127,8 +106,8 @@
 
 	if (loc & 0x01 && offset >= size)
 	{
-		struct ExtendedAttrHeaderDesc *eahd;
-		eahd = (struct ExtendedAttrHeaderDesc *)ea;
+		struct extendedAttrHeaderDesc *eahd;
+		eahd = (struct extendedAttrHeaderDesc *)ea;
 
 		if (UDF_I_LENALLOC(inode))
 		{
@@ -138,7 +117,7 @@
 		if (UDF_I_LENEATTR(inode))
 		{
 			/* check checksum/crc */
-			if (le16_to_cpu(eahd->descTag.tagIdent) != TID_EXTENDED_ATTRE_HEADER_DESC ||
+			if (le16_to_cpu(eahd->descTag.tagIdent) != TAG_IDENT_EAHD ||
 				le32_to_cpu(eahd->descTag.tagLocation) != UDF_I_LOCATION(inode).logicalBlockNum)
 			{
 				udf_release_data(*bh);
@@ -147,9 +126,9 @@
 		}
 		else
 		{
-			size -= sizeof(struct ExtendedAttrHeaderDesc);
-			UDF_I_LENEATTR(inode) += sizeof(struct ExtendedAttrHeaderDesc);
-			eahd->descTag.tagIdent = cpu_to_le16(TID_EXTENDED_ATTRE_HEADER_DESC);
+			size -= sizeof(struct extendedAttrHeaderDesc);
+			UDF_I_LENEATTR(inode) += sizeof(struct extendedAttrHeaderDesc);
+			eahd->descTag.tagIdent = cpu_to_le16(TAG_IDENT_EAHD);
 			eahd->descTag.descVersion = cpu_to_le16(2);
 			eahd->descTag.tagSerialNum = cpu_to_le16(1);
 			eahd->descTag.tagLocation = cpu_to_le32(UDF_I_LOCATION(inode).logicalBlockNum);
@@ -162,7 +141,7 @@
 		{
 			if (le32_to_cpu(eahd->appAttrLocation) < UDF_I_LENEATTR(inode))
 			{
-				Uint32 aal = le32_to_cpu(eahd->appAttrLocation);
+				uint32_t aal = le32_to_cpu(eahd->appAttrLocation);
 				memmove(&ea[offset - aal + size],
 					&ea[aal], offset - aal);
 				offset -= aal;
@@ -170,7 +149,7 @@
 			}
 			if (le32_to_cpu(eahd->impAttrLocation) < UDF_I_LENEATTR(inode))
 			{
-				Uint32 ial = le32_to_cpu(eahd->impAttrLocation);
+				uint32_t ial = le32_to_cpu(eahd->impAttrLocation);
 				memmove(&ea[offset - ial + size],
 					&ea[ial], offset - ial);
 				offset -= ial;
@@ -181,7 +160,7 @@
 		{
 			if (le32_to_cpu(eahd->appAttrLocation) < UDF_I_LENEATTR(inode))
 			{
-				Uint32 aal = le32_to_cpu(eahd->appAttrLocation);
+				uint32_t aal = le32_to_cpu(eahd->appAttrLocation);
 				memmove(&ea[offset - aal + size],
 					&ea[aal], offset - aal);
 				offset -= aal;
@@ -190,7 +169,7 @@
 		}
 		/* rewrite CRC + checksum of eahd */
 		UDF_I_LENEATTR(inode) += size;
-		return (struct GenericAttrFormat *)&ea[offset];
+		return (struct genericFormat *)&ea[offset];
 	}
 	if (loc & 0x02)
 	{
@@ -199,31 +178,31 @@
 	return NULL;
 }
 
-extern struct GenericAttrFormat *
-udf_get_extendedattr(struct inode * inode, Uint32 type, Uint8 subtype,
+extern struct genericFormat *
+udf_get_extendedattr(struct inode * inode, uint32_t type, uint8_t subtype,
 	struct buffer_head **bh)
 {
-	struct GenericAttrFormat *gaf;
-	Uint8 *ea = NULL;
+	struct genericFormat *gaf;
+	uint8_t *ea = NULL;
 	long_ad eaicb;
-	Uint32 offset;
+	uint32_t offset;
 
 	*bh = udf_tread(inode->i_sb, inode->i_ino);
 
 	if (UDF_I_EXTENDED_FE(inode) == 0)
 	{
-		struct FileEntry *fe;
+		struct fileEntry *fe;
 
-		fe = (struct FileEntry *)(*bh)->b_data;
+		fe = (struct fileEntry *)(*bh)->b_data;
 		eaicb = lela_to_cpu(fe->extendedAttrICB);
 		if (UDF_I_LENEATTR(inode))
 			ea = fe->extendedAttr;
 	}
 	else
 	{
-		struct ExtendedFileEntry *efe;
+		struct extendedFileEntry *efe;
 
-		efe = (struct ExtendedFileEntry *)(*bh)->b_data;
+		efe = (struct extendedFileEntry *)(*bh)->b_data;
 		eaicb = lela_to_cpu(efe->extendedAttrICB);
 		if (UDF_I_LENEATTR(inode))
 			ea = efe->extendedAttr;
@@ -231,11 +210,11 @@
 
 	if (UDF_I_LENEATTR(inode))
 	{
-		struct ExtendedAttrHeaderDesc *eahd;
-		eahd = (struct ExtendedAttrHeaderDesc *)ea;
+		struct extendedAttrHeaderDesc *eahd;
+		eahd = (struct extendedAttrHeaderDesc *)ea;
 
 		/* check checksum/crc */
-		if (le16_to_cpu(eahd->descTag.tagIdent) != TID_EXTENDED_ATTRE_HEADER_DESC ||
+		if (le16_to_cpu(eahd->descTag.tagIdent) != TAG_IDENT_EAHD ||
 			le32_to_cpu(eahd->descTag.tagLocation) != UDF_I_LOCATION(inode).logicalBlockNum)
 		{
 			udf_release_data(*bh);
@@ -243,7 +222,7 @@
 		}
 	
 		if (type < 2048)
-			offset = sizeof(struct ExtendedAttrHeaderDesc);
+			offset = sizeof(struct extendedAttrHeaderDesc);
 		else if (type < 65536)
 			offset = le32_to_cpu(eahd->impAttrLocation);
 		else
@@ -251,7 +230,7 @@
 
 		while (offset < UDF_I_LENEATTR(inode))
 		{
-			gaf = (struct GenericAttrFormat *)&ea[offset];
+			gaf = (struct genericFormat *)&ea[offset];
 			if (le32_to_cpu(gaf->attrType) == type && gaf->attrSubtype == subtype)
 				return gaf;
 			else
@@ -267,22 +246,6 @@
 	return NULL;
 }
 
-extern struct buffer_head *
-udf_read_untagged(struct super_block *sb, Uint32 block, Uint32 offset)
-{
-	struct buffer_head *bh = NULL;
-
-	/* Read the block */
-	bh = udf_tread(sb, block+offset);
-	if (!bh)
-	{
-		printk(KERN_ERR "udf: udf_read_untagged(%p,%d,%d) failed\n",
-			sb, block, offset);
-		return NULL;
-	}
-	return bh;
-}
-
 /*
  * udf_read_tagged
  *
@@ -294,11 +257,11 @@
  *	Written, tested, and released.
  */
 extern struct buffer_head *
-udf_read_tagged(struct super_block *sb, Uint32 block, Uint32 location, Uint16 *ident)
+udf_read_tagged(struct super_block *sb, uint32_t block, uint32_t location, uint16_t *ident)
 {
 	tag *tag_p;
 	struct buffer_head *bh = NULL;
-	register Uint8 checksum;
+	register uint8_t checksum;
 	register int i;
 
 	/* Read the block */
@@ -326,9 +289,9 @@
 	/* Verify the tag checksum */
 	checksum = 0U;
 	for (i = 0; i < 4; i++)
-		checksum += (Uint8)(bh->b_data[i]);
+		checksum += (uint8_t)(bh->b_data[i]);
 	for (i = 5; i < 16; i++)
-		checksum += (Uint8)(bh->b_data[i]);
+		checksum += (uint8_t)(bh->b_data[i]);
 	if (checksum != tag_p->tagChecksum) {
 		printk(KERN_ERR "udf: tag checksum failed block %d\n", block);
 		goto error_out;
@@ -359,7 +322,7 @@
 }
 
 extern struct buffer_head *
-udf_read_ptagged(struct super_block *sb, lb_addr loc, Uint32 offset, Uint16 *ident)
+udf_read_ptagged(struct super_block *sb, lb_addr loc, uint32_t offset, uint16_t *ident)
 {
 	return udf_read_tagged(sb, udf_get_lb_pblock(sb, loc, offset),
 		loc.logicalBlockNum + offset, ident);
@@ -371,8 +334,6 @@
 		brelse(bh);
 }
 
-#endif
-
 void udf_update_tag(char *data, int length)
 {
 	tag *tptr = (tag *)data;
@@ -386,11 +347,11 @@
 
 	for (i=0; i<16; i++)
 		if (i != 4)
-			tptr->tagChecksum += (Uint8)(data[i]);
+			tptr->tagChecksum += (uint8_t)(data[i]);
 }
 
-void udf_new_tag(char *data, Uint16 ident, Uint16 version, Uint16 snum,
-	Uint32 loc, int length)
+void udf_new_tag(char *data, uint16_t ident, uint16_t version, uint16_t snum,
+	uint32_t loc, int length)
 {
 	tag *tptr = (tag *)data;
 	tptr->tagIdent = le16_to_cpu(ident);
@@ -399,114 +360,3 @@
 	tptr->tagLocation = le32_to_cpu(loc);
 	udf_update_tag(data, length);
 }
-
-#ifndef __KERNEL__
-/*
- * udf_read_tagged_data
- *
- * PURPOSE
- *	Read the first block of a tagged descriptor.
- *	Usable from user-land.
- *
- * HISTORY
- *	  10/4/98 dgb: written
- */
-int
-udf_read_tagged_data(char *buffer, int size, int fd, int block, int offset)
-{
-	tag *tag_p;
-	register Uint8 checksum;
-	register int i;
-	unsigned long offs;
-
-	if (!buffer)
-	{
-		udf_errno = 1;
-		return -1;
-	}
-
-	if ( !udf_blocksize )
-	{
-		udf_errno = 2;
-		return -1;
-	}
-
-	if ( size < udf_blocksize )
-	{
-		udf_errno = 3;
-		return -1;
-	}
-	udf_errno = 0;
-	
-	offs = (long)block * udf_blocksize;
-	if ( lseek(fd, offs, SEEK_SET) != offs )
-	{
-		udf_errno = 4;
-		return -1;
-	}
-
-	i = read(fd, buffer, udf_blocksize);
-	if ( i < udf_blocksize )
-	{
-		udf_errno = 5;
-		return -1;
-	}
-
-	tag_p = (tag *)(buffer);
-
-	/* Verify the tag location */
-	if ((block-offset) != tag_p->tagLocation)
-	{
-#ifdef __KERNEL__
-		printk(KERN_ERR "udf: location mismatch block %d, tag %d\n",
-			block, tag_p->tagLocation);
-#else
-		udf_errno = 6;
-#endif
-		goto error_out;
-	}
-	
-	/* Verify the tag checksum */
-	checksum = 0U;
-	for (i = 0; i < 4; i++)
-		checksum += (Uint8)(buffer[i]);
-	for (i = 5; i < 16; i++)
-		checksum += (Uint8)(buffer[i]);
-	if (checksum != tag_p->tagChecksum)
-	{
-#ifdef __KERNEL__
-		printk(KERN_ERR "udf: tag checksum failed\n");
-#else
-		udf_errno = 7;
-#endif
-		goto error_out;
-	}
-
-	/* Verify the tag version */
-	if (tag_p->descVersion != 0x0002U)
-	{
-#ifdef __KERNEL__
-		printk(KERN_ERR "udf: tag version 0x%04x != 0x0002U\n",
-			tag_p->descVersion);
-#else
-		udf_errno = 8;
-#endif
-		goto error_out;
-	}
-
-	/* Verify the descriptor CRC */
-	if (tag_p->descCRC == udf_crc(buffer + 16, tag_p->descCRCLength, 0))
-	{
-		udf_errno = 0;
-		return 0;
-	}
-#ifdef __KERNEL__
-	printk(KERN_ERR "udf: crc failure in udf_read_tagged\n");
-#else
-	udf_errno = 9;
-#endif
-
-error_out:
-	return -1;
-}
-#endif
diff -Nru a/fs/udf/namei.c b/fs/udf/namei.c
--- a/fs/udf/namei.c	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/namei.c	Fri Mar 15 17:51:02 2002
@@ -15,7 +15,7 @@
  *              ftp://prep.ai.mit.edu/pub/gnu/GPL
  *      Each contributing author retains all rights to their own work.
  *
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *  (C) 1999-2000 Stelias Computing Inc
  *
  * HISTORY
@@ -35,7 +35,6 @@
 #include <linux/quotaops.h>
 #include <linux/locks.h>
 #include <linux/smp_lock.h>
-#include <linux/udf_fs.h>
 
 static inline int udf_match(int len, const char * const name, struct qstr *qs)
 {
@@ -44,31 +43,31 @@
 	return !memcmp(name, qs->name, len);
 }
 
-int udf_write_fi(struct inode *inode, struct FileIdentDesc *cfi,
-	struct FileIdentDesc *sfi, struct udf_fileident_bh *fibh,
-	Uint8 *impuse, Uint8 *fileident)
+int udf_write_fi(struct inode *inode, struct fileIdentDesc *cfi,
+	struct fileIdentDesc *sfi, struct udf_fileident_bh *fibh,
+	uint8_t *impuse, uint8_t *fileident)
 {
-	Uint16 crclen = fibh->eoffset - fibh->soffset - sizeof(tag);
-	Uint16 crc;
-	Uint8 checksum = 0;
+	uint16_t crclen = fibh->eoffset - fibh->soffset - sizeof(tag);
+	uint16_t crc;
+	uint8_t checksum = 0;
 	int i;
 	int offset;
-	Uint16 liu = le16_to_cpu(cfi->lengthOfImpUse);
-	Uint8 lfi = cfi->lengthFileIdent;
+	uint16_t liu = le16_to_cpu(cfi->lengthOfImpUse);
+	uint8_t lfi = cfi->lengthFileIdent;
 	int padlen = fibh->eoffset - fibh->soffset - liu - lfi -
-		sizeof(struct FileIdentDesc);
+		sizeof(struct fileIdentDesc);
 
-	offset = fibh->soffset + sizeof(struct FileIdentDesc);
+	offset = fibh->soffset + sizeof(struct fileIdentDesc);
 
 	if (impuse)
 	{
 		if (offset + liu < 0)
-			memcpy((Uint8 *)sfi->impUse, impuse, liu);
+			memcpy((uint8_t *)sfi->impUse, impuse, liu);
 		else if (offset >= 0)
 			memcpy(fibh->ebh->b_data + offset, impuse, liu);
 		else
 		{
-			memcpy((Uint8 *)sfi->impUse, impuse, -offset);
+			memcpy((uint8_t *)sfi->impUse, impuse, -offset);
 			memcpy(fibh->ebh->b_data, impuse - offset, liu + offset);
 		}
 	}
@@ -78,12 +77,12 @@
 	if (fileident)
 	{
 		if (offset + lfi < 0)
-			memcpy((Uint8 *)sfi->fileIdent + liu, fileident, lfi);
+			memcpy((uint8_t *)sfi->fileIdent + liu, fileident, lfi);
 		else if (offset >= 0)
 			memcpy(fibh->ebh->b_data + offset, fileident, lfi);
 		else
 		{
-			memcpy((Uint8 *)sfi->fileIdent + liu, fileident, -offset);
+			memcpy((uint8_t *)sfi->fileIdent + liu, fileident, -offset);
 			memcpy(fibh->ebh->b_data, fileident - offset, lfi + offset);
 		}
 	}
@@ -91,28 +90,28 @@
 	offset += lfi;
 
 	if (offset + padlen < 0)
-		memset((Uint8 *)sfi->padding + liu + lfi, 0x00, padlen);
+		memset((uint8_t *)sfi->padding + liu + lfi, 0x00, padlen);
 	else if (offset >= 0)
 		memset(fibh->ebh->b_data + offset, 0x00, padlen);
 	else
 	{
-		memset((Uint8 *)sfi->padding + liu + lfi, 0x00, -offset);
+		memset((uint8_t *)sfi->padding + liu + lfi, 0x00, -offset);
 		memset(fibh->ebh->b_data, 0x00, padlen + offset);
 	}
 
-	crc = udf_crc((Uint8 *)cfi + sizeof(tag), sizeof(struct FileIdentDesc) -
+	crc = udf_crc((uint8_t *)cfi + sizeof(tag), sizeof(struct fileIdentDesc) -
 		sizeof(tag), 0);
 
 	if (fibh->sbh == fibh->ebh)
-		crc = udf_crc((Uint8 *)sfi->impUse,
-			crclen + sizeof(tag) - sizeof(struct FileIdentDesc), crc);
-	else if (sizeof(struct FileIdentDesc) >= -fibh->soffset)
-		crc = udf_crc(fibh->ebh->b_data + sizeof(struct FileIdentDesc) + fibh->soffset,
-			crclen + sizeof(tag) - sizeof(struct FileIdentDesc), crc);
+		crc = udf_crc((uint8_t *)sfi->impUse,
+			crclen + sizeof(tag) - sizeof(struct fileIdentDesc), crc);
+	else if (sizeof(struct fileIdentDesc) >= -fibh->soffset)
+		crc = udf_crc(fibh->ebh->b_data + sizeof(struct fileIdentDesc) + fibh->soffset,
+			crclen + sizeof(tag) - sizeof(struct fileIdentDesc), crc);
 	else
 	{
-		crc = udf_crc((Uint8 *)sfi->impUse,
-			-fibh->soffset - sizeof(struct FileIdentDesc), crc);
+		crc = udf_crc((uint8_t *)sfi->impUse,
+			-fibh->soffset - sizeof(struct fileIdentDesc), crc);
 		crc = udf_crc(fibh->ebh->b_data, fibh->eoffset, crc);
 	}
 
@@ -121,16 +120,16 @@
 
 	for (i=0; i<16; i++)
 		if (i != 4)
-			checksum += ((Uint8 *)&cfi->descTag)[i];
+			checksum += ((uint8_t *)&cfi->descTag)[i];
 
 	cfi->descTag.tagChecksum = checksum;
-	if (sizeof(struct FileIdentDesc) <= -fibh->soffset)
-		memcpy((Uint8 *)sfi, (Uint8 *)cfi, sizeof(struct FileIdentDesc));
+	if (sizeof(struct fileIdentDesc) <= -fibh->soffset)
+		memcpy((uint8_t *)sfi, (uint8_t *)cfi, sizeof(struct fileIdentDesc));
 	else
 	{
-		memcpy((Uint8 *)sfi, (Uint8 *)cfi, -fibh->soffset);
-		memcpy(fibh->ebh->b_data, (Uint8 *)cfi - fibh->soffset,
-			sizeof(struct FileIdentDesc) + fibh->soffset);
+		memcpy((uint8_t *)sfi, (uint8_t *)cfi, -fibh->soffset);
+		memcpy(fibh->ebh->b_data, (uint8_t *)cfi - fibh->soffset,
+			sizeof(struct fileIdentDesc) + fibh->soffset);
 	}
 
 	if (fibh->sbh != fibh->ebh)
@@ -139,21 +138,21 @@
 	return 0;
 }
 
-static struct FileIdentDesc *
+static struct fileIdentDesc *
 udf_find_entry(struct inode *dir, struct dentry *dentry,
 	struct udf_fileident_bh *fibh,
-	struct FileIdentDesc *cfi)
+	struct fileIdentDesc *cfi)
 {
-	struct FileIdentDesc *fi=NULL;
+	struct fileIdentDesc *fi=NULL;
 	loff_t f_pos;
 	int block, flen;
 	char fname[255];
 	char *nameptr;
-	Uint8 lfi;
-	Uint16 liu;
+	uint8_t lfi;
+	uint16_t liu;
 	loff_t size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
 	lb_addr bloc, eloc;
-	Uint32 extoffset, elen, offset;
+	uint32_t extoffset, elen, offset;
 	struct buffer_head *bh = NULL;
 
 	if (!dir)
@@ -163,15 +162,15 @@
 
 	fibh->soffset = fibh->eoffset = (f_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
 	if (inode_bmap(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2),
-		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == EXTENT_RECORDED_ALLOCATED)
+		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == (EXT_RECORDED_ALLOCATED >> 30))
 	{
 		offset >>= dir->i_sb->s_blocksize_bits;
 		block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
 		if ((++offset << dir->i_sb->s_blocksize_bits) < elen)
 		{
-			if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_SHORT)
+			if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
 				extoffset -= sizeof(short_ad);
-			else if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_LONG)
+			else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
 				extoffset -= sizeof(long_ad);
 		}
 		else
@@ -213,10 +212,10 @@
 		{
 			int poffset;	/* Unpaded ending offset */
 
-			poffset = fibh->soffset + sizeof(struct FileIdentDesc) + liu + lfi;
+			poffset = fibh->soffset + sizeof(struct fileIdentDesc) + liu + lfi;
 
 			if (poffset >= lfi)
-				nameptr = (Uint8 *)(fibh->ebh->b_data + poffset - lfi);
+				nameptr = (uint8_t *)(fibh->ebh->b_data + poffset - lfi);
 			else
 			{
 				nameptr = fname;
@@ -225,13 +224,13 @@
 			}
 		}
 
-		if ( (cfi->fileCharacteristics & FILE_DELETED) != 0 )
+		if ( (cfi->fileCharacteristics & FID_FILE_CHAR_DELETED) != 0 )
 		{
 			if ( !UDF_QUERY_FLAG(dir->i_sb, UDF_FLAG_UNDELETE) )
 				continue;
 		}
 	    
-		if ( (cfi->fileCharacteristics & FILE_HIDDEN) != 0 )
+		if ( (cfi->fileCharacteristics & FID_FILE_CHAR_HIDDEN) != 0 )
 		{
 			if ( !UDF_QUERY_FLAG(dir->i_sb, UDF_FLAG_UNHIDE) )
 				continue;
@@ -292,7 +291,7 @@
 udf_lookup(struct inode *dir, struct dentry *dentry)
 {
 	struct inode *inode = NULL;
-	struct FileIdentDesc cfi, *fi;
+	struct fileIdentDesc cfi, *fi;
 	struct udf_fileident_bh fibh;
 
 	if (dentry->d_name.len > UDF_NAME_LEN)
@@ -330,13 +329,13 @@
 	return NULL;
 }
 
-static struct FileIdentDesc *
+static struct fileIdentDesc *
 udf_add_entry(struct inode *dir, struct dentry *dentry,
 	struct udf_fileident_bh *fibh,
-	struct FileIdentDesc *cfi, int *err)
+	struct fileIdentDesc *cfi, int *err)
 {
 	struct super_block *sb;
-	struct FileIdentDesc *fi=NULL;
+	struct fileIdentDesc *fi=NULL;
 	struct ustr unifilename;
 	char name[UDF_NAME_LEN], fname[UDF_NAME_LEN];
 	int namelen;
@@ -345,11 +344,11 @@
 	char *nameptr;
 	loff_t size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
 	int nfidlen;
-	Uint8 lfi;
-	Uint16 liu;
+	uint8_t lfi;
+	uint16_t liu;
 	int block;
 	lb_addr bloc, eloc;
-	Uint32 extoffset, elen, offset;
+	uint32_t extoffset, elen, offset;
 	struct buffer_head *bh = NULL;
 
 	sb = dir->i_sb;
@@ -390,21 +389,21 @@
 	else
 		namelen = 0;
 
-	nfidlen = (sizeof(struct FileIdentDesc) + namelen + 3) & ~3;
+	nfidlen = (sizeof(struct fileIdentDesc) + namelen + 3) & ~3;
 
 	f_pos = (udf_ext0_offset(dir) >> 2);
 
 	fibh->soffset = fibh->eoffset = (f_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
 	if (inode_bmap(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2),
-		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == EXTENT_RECORDED_ALLOCATED)
+		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == (EXT_RECORDED_ALLOCATED >> 30))
 	{
 		offset >>= dir->i_sb->s_blocksize_bits;
 		block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
 		if ((++offset << dir->i_sb->s_blocksize_bits) < elen)
 		{
-			if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_SHORT)
+			if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
 				extoffset -= sizeof(short_ad);
-			else if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_LONG)
+			else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
 				extoffset -= sizeof(long_ad);
 		}
 		else
@@ -442,7 +441,7 @@
 			{
 				int poffset;	/* Unpaded ending offset */
 	
-				poffset = fibh->soffset + sizeof(struct FileIdentDesc) + liu + lfi;
+				poffset = fibh->soffset + sizeof(struct fileIdentDesc) + liu + lfi;
 	
 				if (poffset >= lfi)
 					nameptr = (char *)(fibh->ebh->b_data + poffset - lfi);
@@ -454,9 +453,9 @@
 				}
 			}
 	
-			if ( (cfi->fileCharacteristics & FILE_DELETED) != 0 )
+			if ( (cfi->fileCharacteristics & FID_FILE_CHAR_DELETED) != 0 )
 			{
-				if (((sizeof(struct FileIdentDesc) + liu + lfi + 3) & ~3) == nfidlen)
+				if (((sizeof(struct fileIdentDesc) + liu + lfi + 3) & ~3) == nfidlen)
 				{
 					udf_release_data(bh);
 					cfi->descTag.tagSerialNum = cpu_to_le16(1);
@@ -492,7 +491,7 @@
 	else
 	{
 		block = udf_get_lb_pblock(dir->i_sb, UDF_I_LOCATION(dir), 0);
-		if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB)
+		if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
 		{
 			fibh->sbh = fibh->ebh = udf_tread(dir->i_sb, block);
 			fibh->soffset = fibh->eoffset = udf_file_entry_alloc_offset(dir);
@@ -506,7 +505,7 @@
 
 	f_pos += nfidlen;
 
-	if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB &&
+	if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB &&
 		sb->s_blocksize - fibh->eoffset < nfidlen)
 	{
 		udf_release_data(bh);
@@ -524,9 +523,9 @@
 		eloc.partitionReferenceNum = UDF_I_LOCATION(dir).partitionReferenceNum;
 		elen = dir->i_sb->s_blocksize;
 		extoffset = udf_file_entry_alloc_offset(dir);
-		if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_SHORT)
+		if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
 			extoffset += sizeof(short_ad);
-		else if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_LONG)
+		else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
 			extoffset += sizeof(long_ad);
 	}
 
@@ -540,13 +539,13 @@
 			fibh->sbh = fibh->ebh;
 		}
 
-		if (UDF_I_ALLOCTYPE(dir) != ICB_FLAG_AD_IN_ICB)
+		if (UDF_I_ALLOCTYPE(dir) != ICBTAG_FLAG_AD_IN_ICB)
 			block = eloc.logicalBlockNum + ((elen - 1) >>
 				dir->i_sb->s_blocksize_bits);
 		else
 			block = UDF_I_LOCATION(dir).logicalBlockNum;
 				
-		fi = (struct FileIdentDesc *)(fibh->sbh->b_data + fibh->soffset);
+		fi = (struct fileIdentDesc *)(fibh->sbh->b_data + fibh->soffset);
 	}
 	else
 	{
@@ -571,7 +570,7 @@
 		if (!(fibh->soffset))
 		{
 			if (udf_next_aext(dir, &bloc, &extoffset, &eloc, &elen, &bh, 1) ==
-				EXTENT_RECORDED_ALLOCATED)
+				(EXT_RECORDED_ALLOCATED >> 30))
 			{
 				block = eloc.logicalBlockNum + ((elen - 1) >>
 					dir->i_sb->s_blocksize_bits);
@@ -581,17 +580,20 @@
 
 			udf_release_data(fibh->sbh);
 			fibh->sbh = fibh->ebh;
-			fi = (struct FileIdentDesc *)(fibh->sbh->b_data);
+			fi = (struct fileIdentDesc *)(fibh->sbh->b_data);
 		}
 		else
 		{
-			fi = (struct FileIdentDesc *)
+			fi = (struct fileIdentDesc *)
 				(fibh->sbh->b_data + sb->s_blocksize + fibh->soffset);
 		}
 	}
 
-	memset(cfi, 0, sizeof(struct FileIdentDesc));
-	udf_new_tag((char *)cfi, TID_FILE_IDENT_DESC, 2, 1, block, sizeof(tag));
+	memset(cfi, 0, sizeof(struct fileIdentDesc));
+	if (UDF_SB_UDFREV(sb) >= 0x0200)
+		udf_new_tag((char *)cfi, TAG_IDENT_FID, 3, 1, block, sizeof(tag));
+	else
+		udf_new_tag((char *)cfi, TAG_IDENT_FID, 2, 1, block, sizeof(tag));
 	cfi->fileVersionNum = cpu_to_le16(1);
 	cfi->lengthFileIdent = namelen;
 	cfi->lengthOfImpUse = cpu_to_le16(0);
@@ -599,7 +601,7 @@
 	{
 		udf_release_data(bh);
 		dir->i_size += nfidlen;
-		if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB)
+		if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
 			UDF_I_LENALLOC(dir) += nfidlen;
 		mark_inode_dirty(dir);
 		return fi;
@@ -615,10 +617,10 @@
 	}
 }
 
-static int udf_delete_entry(struct inode *inode, struct FileIdentDesc *fi,
-	struct udf_fileident_bh *fibh, struct FileIdentDesc *cfi)
+static int udf_delete_entry(struct inode *inode, struct fileIdentDesc *fi,
+	struct udf_fileident_bh *fibh, struct fileIdentDesc *cfi)
 {
-	cfi->fileCharacteristics |= FILE_DELETED;
+	cfi->fileCharacteristics |= FID_FILE_CHAR_DELETED;
 	if (UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT))
 		memset(&(cfi->icb), 0x00, sizeof(long_ad));
 	return udf_write_fi(inode, cfi, fi, fibh, NULL, NULL);
@@ -628,7 +630,7 @@
 {
 	struct udf_fileident_bh fibh;
 	struct inode *inode;
-	struct FileIdentDesc cfi, *fi;
+	struct fileIdentDesc cfi, *fi;
 	int err;
 
 	lock_kernel();
@@ -638,7 +640,7 @@
 		return err;
 	}
 
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 		inode->i_data.a_ops = &udf_adinicb_aops;
 	else
 		inode->i_data.a_ops = &udf_aops;
@@ -657,10 +659,10 @@
 	}
 	cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
 	cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
-	*(Uint32 *)((struct ADImpUse *)cfi.icb.impUse)->impUse =
+	*(uint32_t *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
 		cpu_to_le32(UDF_I_UNIQUE(inode) & 0x00000000FFFFFFFFUL);
 	udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
-	if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		mark_inode_dirty(dir);
 	}
@@ -677,7 +679,7 @@
 	struct inode * inode;
 	struct udf_fileident_bh fibh;
 	int err;
-	struct FileIdentDesc cfi, *fi;
+	struct fileIdentDesc cfi, *fi;
 
 	lock_kernel();
 	err = -EIO;
@@ -697,10 +699,10 @@
 	}
 	cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
 	cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
-	*(Uint32 *)((struct ADImpUse *)cfi.icb.impUse)->impUse =
+	*(uint32_t *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
 		cpu_to_le32(UDF_I_UNIQUE(inode) & 0x00000000FFFFFFFFUL);
 	udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
-	if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		mark_inode_dirty(dir);
 	}
@@ -721,7 +723,7 @@
 	struct inode * inode;
 	struct udf_fileident_bh fibh;
 	int err;
-	struct FileIdentDesc cfi, *fi;
+	struct fileIdentDesc cfi, *fi;
 
 	lock_kernel();
 	err = -EMLINK;
@@ -745,9 +747,9 @@
 	inode->i_nlink = 2;
 	cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
 	cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(dir));
-	*(Uint32 *)((struct ADImpUse *)cfi.icb.impUse)->impUse =
+	*(uint32_t *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
 		cpu_to_le32(UDF_I_UNIQUE(dir) & 0x00000000FFFFFFFFUL);
-	cfi.fileCharacteristics = FILE_DIRECTORY | FILE_PARENT;
+	cfi.fileCharacteristics = FID_FILE_CHAR_DIRECTORY | FID_FILE_CHAR_PARENT;
 	udf_write_fi(inode, &cfi, fi, &fibh, NULL, NULL);
 	udf_release_data(fibh.sbh);
 	inode->i_mode = S_IFDIR | mode;
@@ -764,9 +766,9 @@
 	}
 	cfi.icb.extLength = cpu_to_le32(inode->i_sb->s_blocksize);
 	cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
-	*(Uint32 *)((struct ADImpUse *)cfi.icb.impUse)->impUse =
+	*(uint32_t *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
 		cpu_to_le32(UDF_I_UNIQUE(inode) & 0x00000000FFFFFFFFUL);
-	cfi.fileCharacteristics |= FILE_DIRECTORY;
+	cfi.fileCharacteristics |= FID_FILE_CHAR_DIRECTORY;
 	udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
 	dir->i_nlink++;
 	mark_inode_dirty(dir);
@@ -782,28 +784,28 @@
 
 static int empty_dir(struct inode *dir)
 {
-	struct FileIdentDesc *fi, cfi;
+	struct fileIdentDesc *fi, cfi;
 	struct udf_fileident_bh fibh;
 	loff_t f_pos;
 	loff_t size = (udf_ext0_offset(dir) + dir->i_size) >> 2;
 	int block;
 	lb_addr bloc, eloc;
-	Uint32 extoffset, elen, offset;
+	uint32_t extoffset, elen, offset;
 	struct buffer_head *bh = NULL;
 
 	f_pos = (udf_ext0_offset(dir) >> 2);
 
 	fibh.soffset = fibh.eoffset = (f_pos & ((dir->i_sb->s_blocksize - 1) >> 2)) << 2;
 	if (inode_bmap(dir, f_pos >> (dir->i_sb->s_blocksize_bits - 2),
-		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == EXTENT_RECORDED_ALLOCATED)
+		&bloc, &extoffset, &eloc, &elen, &offset, &bh) == (EXT_RECORDED_ALLOCATED >> 30))
 	{
 		offset >>= dir->i_sb->s_blocksize_bits;
 		block = udf_get_lb_pblock(dir->i_sb, eloc, offset);
 		if ((++offset << dir->i_sb->s_blocksize_bits) < elen)
 		{
-			if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_SHORT)
+			if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_SHORT)
 				extoffset -= sizeof(short_ad);
-			else if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_LONG)
+			else if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_LONG)
 				extoffset -= sizeof(long_ad);
 		}
 		else
@@ -831,7 +833,7 @@
 			return 0;
 		}
 
-		if (cfi.lengthFileIdent && (cfi.fileCharacteristics & FILE_DELETED) == 0)
+		if (cfi.lengthFileIdent && (cfi.fileCharacteristics & FID_FILE_CHAR_DELETED) == 0)
 		{
 			udf_release_data(bh);
 			return 0;
@@ -849,7 +851,7 @@
 	int retval;
 	struct inode * inode = dentry->d_inode;
 	struct udf_fileident_bh fibh;
-	struct FileIdentDesc *fi, cfi;
+	struct fileIdentDesc *fi, cfi;
 
 	retval = -ENOENT;
 	lock_kernel();
@@ -892,8 +894,8 @@
 	int retval;
 	struct inode * inode = dentry->d_inode;
 	struct udf_fileident_bh fibh;
-	struct FileIdentDesc *fi;
-	struct FileIdentDesc cfi;
+	struct fileIdentDesc *fi;
+	struct fileIdentDesc cfi;
 
 	retval = -ENOENT;
 	lock_kernel();
@@ -938,13 +940,13 @@
 static int udf_symlink(struct inode * dir, struct dentry * dentry, const char * symname)
 {
 	struct inode * inode;
-	struct PathComponent *pc;
+	struct pathComponent *pc;
 	char *compstart;
 	struct udf_fileident_bh fibh;
 	struct buffer_head *bh = NULL;
 	int eoffset, elen = 0;
-	struct FileIdentDesc *fi;
-	struct FileIdentDesc cfi;
+	struct fileIdentDesc *fi;
+	struct fileIdentDesc cfi;
 	char *ea;
 	int err;
 	int block;
@@ -957,11 +959,11 @@
 	inode->i_data.a_ops = &udf_symlink_aops;
 	inode->i_op = &page_symlink_inode_operations;
 
-	if (UDF_I_ALLOCTYPE(inode) != ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(inode) != ICBTAG_FLAG_AD_IN_ICB)
 	{
 		struct buffer_head *bh = NULL;
 		lb_addr bloc, eloc;
-		Uint32 elen, extoffset;
+		uint32_t elen, extoffset;
 
 		block = udf_new_block(inode->i_sb, inode,
 			UDF_I_LOCATION(inode).partitionReferenceNum,
@@ -994,7 +996,7 @@
 	ea = bh->b_data + udf_ext0_offset(inode);
 
 	eoffset = inode->i_sb->s_blocksize - udf_ext0_offset(inode);
-	pc = (struct PathComponent *)ea;
+	pc = (struct pathComponent *)ea;
 
 	if (*symname == '/')
 	{
@@ -1006,18 +1008,18 @@
 		pc->componentType = 1;
 		pc->lengthComponentIdent = 0;
 		pc->componentFileVersionNum = 0;
-		pc += sizeof(struct PathComponent);
-		elen += sizeof(struct PathComponent);
+		pc += sizeof(struct pathComponent);
+		elen += sizeof(struct pathComponent);
 	}
 
 	err = -ENAMETOOLONG;
 
 	while (*symname)
 	{
-		if (elen + sizeof(struct PathComponent) > eoffset)
+		if (elen + sizeof(struct pathComponent) > eoffset)
 			goto out_no_entry;
 
-		pc = (struct PathComponent *)(ea + elen);
+		pc = (struct pathComponent *)(ea + elen);
 
 		compstart = (char *)symname;
 
@@ -1039,7 +1041,7 @@
 
 		if (pc->componentType == 5)
 		{
-			if (elen + sizeof(struct PathComponent) + symname - compstart > eoffset)
+			if (elen + sizeof(struct pathComponent) + symname - compstart > eoffset)
 				goto out_no_entry;
 			else
 				pc->lengthComponentIdent = symname - compstart;
@@ -1047,7 +1049,7 @@
 			memcpy(pc->componentIdent, compstart, pc->lengthComponentIdent);
 		}
 
-		elen += sizeof(struct PathComponent) + pc->lengthComponentIdent;
+		elen += sizeof(struct pathComponent) + pc->lengthComponentIdent;
 
 		if (*symname)
 		{
@@ -1060,7 +1062,7 @@
 
 	udf_release_data(bh);
 	inode->i_size = elen;
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 		UDF_I_LENALLOC(inode) = inode->i_size;
 	mark_inode_dirty(inode);
 
@@ -1070,11 +1072,11 @@
 	cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
 	if (UDF_SB_LVIDBH(inode->i_sb))
 	{
-		struct LogicalVolHeaderDesc *lvhd;
-		Uint64 uniqueID;
-		lvhd = (struct LogicalVolHeaderDesc *)(UDF_SB_LVID(inode->i_sb)->logicalVolContentsUse);
+		struct logicalVolHeaderDesc *lvhd;
+		uint64_t uniqueID;
+		lvhd = (struct logicalVolHeaderDesc *)(UDF_SB_LVID(inode->i_sb)->logicalVolContentsUse);
 		uniqueID = le64_to_cpu(lvhd->uniqueID);
-		*(Uint32 *)((struct ADImpUse *)cfi.icb.impUse)->impUse =
+		*(uint32_t *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
 			cpu_to_le32(uniqueID & 0x00000000FFFFFFFFUL);
 		if (!(++uniqueID & 0x00000000FFFFFFFFUL))
 			uniqueID += 16;
@@ -1082,7 +1084,7 @@
 		mark_buffer_dirty(UDF_SB_LVIDBH(inode->i_sb));
 	}
 	udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
-	if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		mark_inode_dirty(dir);
 	}
@@ -1109,7 +1111,7 @@
 	struct inode *inode = old_dentry->d_inode;
 	struct udf_fileident_bh fibh;
 	int err;
-	struct FileIdentDesc cfi, *fi;
+	struct fileIdentDesc cfi, *fi;
 
 	lock_kernel();
 	if (inode->i_nlink >= (256<<sizeof(inode->i_nlink))-1) {
@@ -1125,11 +1127,11 @@
 	cfi.icb.extLocation = cpu_to_lelb(UDF_I_LOCATION(inode));
 	if (UDF_SB_LVIDBH(inode->i_sb))
 	{
-		struct LogicalVolHeaderDesc *lvhd;
-		Uint64 uniqueID;
-		lvhd = (struct LogicalVolHeaderDesc *)(UDF_SB_LVID(inode->i_sb)->logicalVolContentsUse);
+		struct logicalVolHeaderDesc *lvhd;
+		uint64_t uniqueID;
+		lvhd = (struct logicalVolHeaderDesc *)(UDF_SB_LVID(inode->i_sb)->logicalVolContentsUse);
 		uniqueID = le64_to_cpu(lvhd->uniqueID);
-		*(Uint32 *)((struct ADImpUse *)cfi.icb.impUse)->impUse =
+		*(uint32_t *)((struct allocDescImpUse *)cfi.icb.impUse)->impUse =
 			cpu_to_le32(uniqueID & 0x00000000FFFFFFFFUL);
 		if (!(++uniqueID & 0x00000000FFFFFFFFUL))
 			uniqueID += 16;
@@ -1137,7 +1139,7 @@
 		mark_buffer_dirty(UDF_SB_LVIDBH(inode->i_sb));
 	}
 	udf_write_fi(dir, &cfi, fi, &fibh, NULL, NULL);
-	if (UDF_I_ALLOCTYPE(dir) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(dir) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		mark_inode_dirty(dir);
 	}
@@ -1163,7 +1165,7 @@
 	struct inode * old_inode = old_dentry->d_inode;
 	struct inode * new_inode = new_dentry->d_inode;
 	struct udf_fileident_bh ofibh, nfibh;
-	struct FileIdentDesc *ofi = NULL, *nfi = NULL, *dir_fi = NULL, ocfi, ncfi;
+	struct fileIdentDesc *ofi = NULL, *nfi = NULL, *dir_fi = NULL, ocfi, ncfi;
 	struct buffer_head *dir_bh = NULL;
 	int retval = -ENOENT;
 
@@ -1193,7 +1195,7 @@
 	}
 	if (S_ISDIR(old_inode->i_mode))
 	{
-		Uint32 offset = udf_ext0_offset(old_inode);
+		uint32_t offset = udf_ext0_offset(old_inode);
 
 		if (new_inode)
 		{
@@ -1258,9 +1260,9 @@
 	if (dir_bh)
 	{
 		dir_fi->icb.extLocation = lelb_to_cpu(UDF_I_LOCATION(new_dir));
-		udf_update_tag((char *)dir_fi, (sizeof(struct FileIdentDesc) +
+		udf_update_tag((char *)dir_fi, (sizeof(struct fileIdentDesc) +
 			cpu_to_le16(dir_fi->lengthOfImpUse) + 3) & ~3);
-		if (UDF_I_ALLOCTYPE(old_inode) == ICB_FLAG_AD_IN_ICB)
+		if (UDF_I_ALLOCTYPE(old_inode) == ICBTAG_FLAG_AD_IN_ICB)
 		{
 			mark_inode_dirty(old_inode);
 		}
diff -Nru a/fs/udf/osta_udf.h b/fs/udf/osta_udf.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/fs/udf/osta_udf.h	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,271 @@
+/*
+ * osta_udf.h
+ *
+ * This file is based on OSTA UDF(tm) 2.01 (March 15, 2000)
+ * http://www.osta.org
+ *
+ * Copyright (c) 2001-2002  Ben Fennema <bfennema@falcon.csc.calpoly.edu>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU Public License ("GPL").
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include "ecma_167.h"
+
+#ifndef _OSTA_UDF_H
+#define _OSTA_UDF_H 1
+
+/* OSTA CS0 Charspec (UDF 2.01 2.1.2) */
+#define UDF_CHAR_SET_TYPE		0
+#define UDF_CHAR_SET_INFO		"OSTA Compressed Unicode"
+
+/* Entity Identifier (UDF 2.01 2.1.5) */
+/* Identifiers (UDF 2.01 2.1.5.2) */
+#define UDF_ID_DEVELOPER		"*Linux UDFFS"
+#define	UDF_ID_COMPLIANT		"*OSTA UDF Compliant"
+#define UDF_ID_LV_INFO			"*UDF LV Info"
+#define UDF_ID_FREE_EA			"*UDF FreeEASpace"
+#define UDF_ID_FREE_APP_EA		"*UDF FreeAppEASpace"
+#define UDF_ID_DVD_CGMS			"*UDF DVD CGMS Info"
+#define UDF_ID_OS2_EA			"*UDF OS/2 EA"
+#define UDF_ID_OS2_EA_LENGTH		"*UDF OS/2 EALength"
+#define UDF_ID_MAC_VOLUME		"*UDF Mac VolumeInfo"
+#define UDF_ID_MAC_FINDER		"*UDF Mac FinderInfo"
+#define UDF_ID_MAC_UNIQUE		"*UDF Mac UniqueIDTable"
+#define UDF_ID_MAC_RESOURCE		"*UDF Mac ResourceFork"
+#define UDF_ID_VIRTUAL			"*UDF Virtual Partition"
+#define UDF_ID_SPARABLE			"*UDF Sparable Partition"
+#define UDF_ID_ALLOC			"*UDF Virtual Alloc Tbl"
+#define UDF_ID_SPARING			"*UDF Sparing Table"
+
+/* Identifier Suffix (UDF 2.01 2.1.5.3) */
+#define IS_DF_HARD_WRITE_PROTECT	0x01
+#define IS_DF_SOFT_WRITE_PROTECT	0x02
+
+struct UDFIdentSuffix
+{
+	uint16_t	UDFRevision;
+	uint8_t		OSClass;
+	uint8_t		OSIdentifier;
+	uint8_t		reserved[4];
+} __attribute__ ((packed));
+
+struct impIdentSuffix
+{
+	uint8_t		OSClass;
+	uint8_t		OSIdentifier;
+	uint8_t		reserved[6];
+} __attribute__ ((packed));
+
+struct appIdentSuffix
+{
+	uint8_t		impUse[8];
+} __attribute__ ((packed));
+ 
+/* Logical Volume Integrity Descriptor (UDF 2.01 2.2.6) */
+/* Implementation Use (UDF 2.01 2.2.6.4) */
+struct logicalVolIntegrityDescImpUse
+{
+	regid		impIdent;
+	uint32_t	numFiles;
+	uint32_t	numDirs;
+	uint16_t	minUDFReadRev;
+	uint16_t	minUDFWriteRev;
+	uint16_t	maxUDFWriteRev;
+	uint8_t		impUse[0];
+} __attribute__ ((packed));
+
+/* Implementation Use Volume Descriptor (UDF 2.01 2.2.7) */
+/* Implementation Use (UDF 2.01 2.2.7.2) */
+struct impUseVolDescImpUse
+{
+	charspec	LVICharset;
+	dstring		logicalVolIdent[128];
+	dstring		LVInfo1[36];
+	dstring		LVInfo2[36];
+	dstring		LVInfo3[36];
+	regid		impIdent;
+	uint8_t		impUse[128];
+} __attribute__ ((packed));
+
+struct udfPartitionMap2
+{
+	uint8_t		partitionMapType;
+	uint8_t		partitionMapLength;
+	uint8_t		reserved1[2];
+	regid		partIdent;
+	uint16_t	volSeqNum;
+	uint16_t	partitionNum;
+} __attribute__ ((packed));
+
+/* Virtual Partition Map (UDF 2.01 2.2.8) */
+struct virtualPartitionMap
+{
+	uint8_t		partitionMapType;
+	uint8_t		partitionMapLength;
+	uint8_t		reserved1[2];
+	regid		partIdent;
+	uint16_t	volSeqNum;
+	uint16_t	partitionNum;
+	uint8_t		reserved2[24];
+} __attribute__ ((packed));
+
+/* Sparable Partition Map (UDF 2.01 2.2.9) */
+struct sparablePartitionMap
+{
+	uint8_t		partitionMapType;
+	uint8_t		partitionMapLength;
+	uint8_t		reserved1[2];
+	regid		partIdent;
+	uint16_t	volSeqNum;
+	uint16_t	partitionNum;
+	uint16_t	packetLength;
+	uint8_t		numSparingTables;
+	uint8_t		reserved2[1];
+	uint32_t	sizeSparingTable;
+	uint32_t	locSparingTable[4];
+} __attribute__ ((packed));
+
+/* Virtual Allocation Table (UDF 1.5 2.2.10) */
+struct virtualAllocationTable15
+{
+	uint32_t	VirtualSector[0];
+	regid		ident;
+	uint32_t	previousVATICB;
+} __attribute__ ((packed));  
+
+#define ICBTAG_FILE_TYPE_VAT15		0x00U
+
+/* Virtual Allocation Table (UDF 2.01 2.2.10) */
+struct virtualAllocationTable20
+{
+	uint16_t	lengthHeader;
+	uint16_t	lengthImpUse;
+	dstring		logicalVolIdent[128];
+	uint32_t	previousVatICBLoc;
+	uint32_t	numFIDSFiles;
+	uint32_t	numFIDSDirectories;
+	uint16_t	minReadRevision;
+	uint16_t	minWriteRevision;
+	uint16_t	maxWriteRevision;
+	uint16_t	reserved;
+	uint8_t		impUse[0];
+	uint32_t	vatEntry[0];
+} __attribute__ ((packed));
+
+#define ICBTAG_FILE_TYPE_VAT20		0xF8U
+
+/* Sparing Table (UDF 2.01 2.2.11) */
+struct sparingEntry
+{
+	uint32_t	origLocation;
+	uint32_t	mappedLocation;
+} __attribute__ ((packed));
+
+struct sparingTable
+{
+	tag 		descTag;
+	regid		sparingIdent;
+	uint16_t	reallocationTableLen;
+	uint16_t	reserved;
+	uint32_t	sequenceNum;
+	struct sparingEntry
+			mapEntry[0];
+} __attribute__ ((packed));
+
+/* struct long_ad ICB - ADImpUse (UDF 2.01 2.2.4.3) */
+struct allocDescImpUse
+{
+	uint16_t	flags;
+	uint8_t		impUse[4];
+} __attribute__ ((packed));
+
+#define AD_IU_EXT_ERASED		0x0001
+
+/* Real-Time Files (UDF 2.01 6.11) */
+#define ICBTAG_FILE_TYPE_REALTIME	0xF9U
+
+/* Implementation Use Extended Attribute (UDF 2.01 3.3.4.5) */
+/* FreeEASpace (UDF 2.01 3.3.4.5.1.1) */
+struct freeEaSpace
+{
+	uint16_t	headerChecksum;
+	uint8_t		freeEASpace[0];
+} __attribute__ ((packed));
+
+/* DVD Copyright Management Information (UDF 2.01 3.3.4.5.1.2) */
+struct DVDCopyrightImpUse 
+{
+	uint16_t	headerChecksum;
+	uint8_t		CGMSInfo;
+	uint8_t		dataType;
+	uint8_t		protectionSystemInfo[4];
+} __attribute__ ((packed));
+
+/* Application Use Extended Attribute (UDF 2.01 3.3.4.6) */
+/* FreeAppEASpace (UDF 2.01 3.3.4.6.1) */
+struct freeAppEASpace
+{
+	uint16_t	headerChecksum;
+	uint8_t		freeEASpace[0];
+} __attribute__ ((packed));
+
+/* UDF Defined System Stream (UDF 2.01 3.3.7) */
+#define UDF_ID_UNIQUE_ID		"*UDF Unique ID Mapping Data"
+#define UDF_ID_NON_ALLOC		"*UDF Non-Allocatable Space"
+#define UDF_ID_POWER_CAL		"*UDF Power Cal Table"
+#define UDF_ID_BACKUP			"*UDF Backup"
+
+/* Operating System Identifiers (UDF 2.01 6.3) */
+#define UDF_OS_CLASS_UNDEF		0x00U
+#define UDF_OS_CLASS_DOS		0x01U
+#define UDF_OS_CLASS_OS2		0x02U
+#define UDF_OS_CLASS_MAC		0x03U
+#define UDF_OS_CLASS_UNIX		0x04U
+#define UDF_OS_CLASS_WIN9X		0x05U
+#define UDF_OS_CLASS_WINNT		0x06U
+#define UDF_OS_CLASS_OS400		0x07U
+#define UDF_OS_CLASS_BEOS		0x08U
+#define UDF_OS_CLASS_WINCE		0x09U
+
+#define UDF_OS_ID_UNDEF			0x00U
+#define UDF_OS_ID_DOS			0x00U
+#define UDF_OS_ID_OS2			0x00U
+#define UDF_OS_ID_MAC			0x00U
+#define UDF_OS_ID_UNIX			0x00U
+#define UDF_OS_ID_AIX			0x01U
+#define UDF_OS_ID_SOLARIS		0x02U
+#define UDF_OS_ID_HPUX			0x03U
+#define UDF_OS_ID_IRIX			0x04U
+#define UDF_OS_ID_LINUX			0x05U
+#define UDF_OS_ID_MKLINUX		0x06U
+#define UDF_OS_ID_FREEBSD		0x07U
+#define UDF_OS_ID_WIN9X			0x00U
+#define UDF_OS_ID_WINNT			0x00U
+#define UDF_OS_ID_OS400			0x00U
+#define UDF_OS_ID_BEOS			0x00U
+#define UDF_OS_ID_WINCE			0x00U
+
+#endif /* _OSTA_UDF_H */
diff -Nru a/fs/udf/partition.c b/fs/udf/partition.c
--- a/fs/udf/partition.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/partition.c	Fri Mar 15 17:51:01 2002
@@ -15,7 +15,7 @@
  *              ftp://prep.ai.mit.edu/pub/gnu/GPL
  *      Each contributing author retains all rights to their own work.
  *
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *
  * HISTORY
  *
@@ -32,7 +32,7 @@
 #include <linux/udf_fs.h>
 #include <linux/slab.h>
 
-inline Uint32 udf_get_pblock(struct super_block *sb, Uint32 block, Uint16 partition, Uint32 offset)
+inline uint32_t udf_get_pblock(struct super_block *sb, uint32_t block, uint16_t partition, uint32_t offset)
 {
 	if (partition >= UDF_SB_NUMPARTS(sb))
 	{
@@ -46,14 +46,14 @@
 		return UDF_SB_PARTROOT(sb, partition) + block + offset;
 }
 
-Uint32 udf_get_pblock_virt15(struct super_block *sb, Uint32 block, Uint16 partition, Uint32 offset)
+uint32_t udf_get_pblock_virt15(struct super_block *sb, uint32_t block, uint16_t partition, uint32_t offset)
 {
 	struct buffer_head *bh = NULL;
-	Uint32 newblock;
-	Uint32 index;
-	Uint32 loc;
+	uint32_t newblock;
+	uint32_t index;
+	uint32_t loc;
 
-	index = (sb->s_blocksize - UDF_SB_TYPEVIRT(sb,partition).s_start_offset) / sizeof(Uint32);
+	index = (sb->s_blocksize - UDF_SB_TYPEVIRT(sb,partition).s_start_offset) / sizeof(uint32_t);
 
 	if (block > UDF_SB_TYPEVIRT(sb,partition).s_num_entries)
 	{
@@ -65,13 +65,13 @@
 	if (block >= index)
 	{
 		block -= index;
-		newblock = 1 + (block / (sb->s_blocksize / sizeof(Uint32)));
-		index = block % (sb->s_blocksize / sizeof(Uint32));
+		newblock = 1 + (block / (sb->s_blocksize / sizeof(uint32_t)));
+		index = block % (sb->s_blocksize / sizeof(uint32_t));
 	}
 	else
 	{
 		newblock = 0;
-		index = UDF_SB_TYPEVIRT(sb,partition).s_start_offset / sizeof(Uint32) + block;
+		index = UDF_SB_TYPEVIRT(sb,partition).s_start_offset / sizeof(uint32_t) + block;
 	}
 
 	loc = udf_block_map(UDF_SB_VAT(sb), newblock);
@@ -83,7 +83,7 @@
 		return 0xFFFFFFFF;
 	}
 
-	loc = le32_to_cpu(((Uint32 *)bh->b_data)[index]);
+	loc = le32_to_cpu(((uint32_t *)bh->b_data)[index]);
 
 	udf_release_data(bh);
 
@@ -96,22 +96,22 @@
 	return udf_get_pblock(sb, loc, UDF_I_LOCATION(UDF_SB_VAT(sb)).partitionReferenceNum, offset);
 }
 
-inline Uint32 udf_get_pblock_virt20(struct super_block *sb, Uint32 block, Uint16 partition, Uint32 offset)
+inline uint32_t udf_get_pblock_virt20(struct super_block *sb, uint32_t block, uint16_t partition, uint32_t offset)
 {
 	return udf_get_pblock_virt15(sb, block, partition, offset);
 }
 
-Uint32 udf_get_pblock_spar15(struct super_block *sb, Uint32 block, Uint16 partition, Uint32 offset)
+uint32_t udf_get_pblock_spar15(struct super_block *sb, uint32_t block, uint16_t partition, uint32_t offset)
 {
 	int i;
-	struct SparingTable *st = NULL;
-	Uint32 packet = (block + offset) & ~(UDF_SB_TYPESPAR(sb,partition).s_packet_len - 1);
+	struct sparingTable *st = NULL;
+	uint32_t packet = (block + offset) & ~(UDF_SB_TYPESPAR(sb,partition).s_packet_len - 1);
 
 	for (i=0; i<4; i++)
 	{
 		if (UDF_SB_TYPESPAR(sb,partition).s_spar_map[i] != NULL)
 		{
-			st = (struct SparingTable *)UDF_SB_TYPESPAR(sb,partition).s_spar_map[i]->b_data;
+			st = (struct sparingTable *)UDF_SB_TYPESPAR(sb,partition).s_spar_map[i]->b_data;
 			break;
 		}
 	}
@@ -137,9 +137,9 @@
 int udf_relocate_blocks(struct super_block *sb, long old_block, long *new_block)
 {
 	struct udf_sparing_data *sdata;
-	struct SparingTable *st = NULL;
-	SparingEntry mapEntry;
-	Uint32 packet;
+	struct sparingTable *st = NULL;
+	struct sparingEntry mapEntry;
+	uint32_t packet;
 	int i, j, k, l;
 
 	for (i=0; i<UDF_SB_NUMPARTS(sb); i++)
@@ -154,7 +154,7 @@
 			{
 				if (UDF_SB_TYPESPAR(sb,i).s_spar_map[j] != NULL)
 				{
-					st = (struct SparingTable *)sdata->s_spar_map[j]->b_data;
+					st = (struct sparingTable *)sdata->s_spar_map[j]->b_data;
 					break;
 				}
 			}
@@ -170,9 +170,9 @@
 					{
 						if (sdata->s_spar_map[j])
 						{
-							st = (struct SparingTable *)sdata->s_spar_map[j]->b_data;
+							st = (struct sparingTable *)sdata->s_spar_map[j]->b_data;
 							st->mapEntry[k].origLocation = cpu_to_le32(packet);
-							udf_update_tag((char *)st, sizeof(struct SparingTable) + st->reallocationTableLen * sizeof(SparingEntry));
+							udf_update_tag((char *)st, sizeof(struct sparingTable) + st->reallocationTableLen * sizeof(struct sparingEntry));
 							mark_buffer_dirty(sdata->s_spar_map[j]);
 						}
 					}
@@ -197,12 +197,12 @@
 					{
 						if (sdata->s_spar_map[j])
 						{
-							st = (struct SparingTable *)sdata->s_spar_map[j]->b_data;
+							st = (struct sparingTable *)sdata->s_spar_map[j]->b_data;
 							mapEntry = st->mapEntry[l];
 							mapEntry.origLocation = cpu_to_le32(packet);
-							memmove(&st->mapEntry[k+1], &st->mapEntry[k], (l-k)*sizeof(SparingEntry));
+							memmove(&st->mapEntry[k+1], &st->mapEntry[k], (l-k)*sizeof(struct sparingEntry));
 							st->mapEntry[k] = mapEntry;
-							udf_update_tag((char *)st, sizeof(struct SparingTable) + st->reallocationTableLen * sizeof(SparingEntry));
+							udf_update_tag((char *)st, sizeof(struct sparingTable) + st->reallocationTableLen * sizeof(struct sparingEntry));
 							mark_buffer_dirty(sdata->s_spar_map[j]);
 						}
 					}
diff -Nru a/fs/udf/super.c b/fs/udf/super.c
--- a/fs/udf/super.c	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/super.c	Fri Mar 15 17:51:01 2002
@@ -26,7 +26,7 @@
  *  Each contributing author retains all rights to their own work.
  *
  *  (C) 1998 Dave Boynton
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *  (C) 2000 Stelias Computing Inc
  *
  * HISTORY
@@ -106,6 +106,7 @@
 	owner:		THIS_MODULE,
 	name:		"udf",
 	get_sb:		udf_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
@@ -435,7 +436,7 @@
 static int
 udf_vrs(struct super_block *sb, int silent)
 {
-	struct VolStructDesc *vsd = NULL;
+	struct volStructDesc *vsd = NULL;
 	int sector = 32768;
 	int sectorsize;
 	struct buffer_head *bh = NULL;
@@ -447,8 +448,8 @@
 	if (sb->s_blocksize & 511)
 		return 0;
 
-	if (sb->s_blocksize < sizeof(struct VolStructDesc))
-		sectorsize = sizeof(struct VolStructDesc);
+	if (sb->s_blocksize < sizeof(struct volStructDesc))
+		sectorsize = sizeof(struct volStructDesc);
 	else
 		sectorsize = sb->s_blocksize;
 
@@ -465,7 +466,7 @@
 			break;
 
 		/* Look for ISO  descriptors */
-		vsd = (struct VolStructDesc *)(bh->b_data +
+		vsd = (struct volStructDesc *)(bh->b_data +
 			(sector & (sb->s_blocksize - 1)));
 
 		if (vsd->stdIdent[0] == 0)
@@ -473,7 +474,7 @@
 			udf_release_data(bh);
 			break;
 		}
-		else if (!strncmp(vsd->stdIdent, STD_ID_CD001, STD_ID_LEN))
+		else if (!strncmp(vsd->stdIdent, VSD_STD_ID_CD001, VSD_STD_ID_LEN))
 		{
 			iso9660 = sector;
 			switch (vsd->structType)
@@ -498,19 +499,19 @@
 					break;
 			}
 		}
-		else if (!strncmp(vsd->stdIdent, STD_ID_BEA01, STD_ID_LEN))
+		else if (!strncmp(vsd->stdIdent, VSD_STD_ID_BEA01, VSD_STD_ID_LEN))
 		{
 		}
-		else if (!strncmp(vsd->stdIdent, STD_ID_TEA01, STD_ID_LEN))
+		else if (!strncmp(vsd->stdIdent, VSD_STD_ID_TEA01, VSD_STD_ID_LEN))
 		{
 			udf_release_data(bh);
 			break;
 		}
-		else if (!strncmp(vsd->stdIdent, STD_ID_NSR02, STD_ID_LEN))
+		else if (!strncmp(vsd->stdIdent, VSD_STD_ID_NSR02, VSD_STD_ID_LEN))
 		{
 			nsr02 = sector;
 		}
-		else if (!strncmp(vsd->stdIdent, STD_ID_NSR03, STD_ID_LEN))
+		else if (!strncmp(vsd->stdIdent, VSD_STD_ID_NSR03, VSD_STD_ID_LEN))
 		{
 			nsr03 = sector;
 		}
@@ -549,8 +550,8 @@
 {
 	int lastblock = UDF_SB_LASTBLOCK(sb);
 	struct buffer_head *bh = NULL;
-	Uint16 ident;
-	Uint32 location;
+	uint16_t ident;
+	uint32_t location;
 	int i;
 
 	if (lastblock)
@@ -584,7 +585,7 @@
 				udf_release_data(bh);
 			}
 	
-			if (ident == TID_ANCHOR_VOL_DESC_PTR)
+			if (ident == TAG_IDENT_AVDP)
 			{
 				if (location == last[i] - UDF_SB_SESSION(sb))
 				{
@@ -601,7 +602,7 @@
 					udf_debug("Anchor found at block %d, location mismatch %d.\n",
 						last[i], location);
 			}
-			else if (ident == TID_FILE_ENTRY || ident == TID_EXTENDED_FILE_ENTRY)
+			else if (ident == TAG_IDENT_FE || ident == TAG_IDENT_EFE)
 			{
 				lastblock = last[i];
 				UDF_SB_ANCHOR(sb)[3] = 512 + UDF_SB_SESSION(sb);
@@ -619,7 +620,7 @@
 					udf_release_data(bh);
 				}
 	
-				if (ident == TID_ANCHOR_VOL_DESC_PTR &&
+				if (ident == TAG_IDENT_AVDP &&
 					location == last[i] - 256 - UDF_SB_SESSION(sb))
 				{
 					lastblock = last[i];
@@ -638,7 +639,7 @@
 						udf_release_data(bh);
 					}
 	
-					if (ident == TID_ANCHOR_VOL_DESC_PTR &&
+					if (ident == TAG_IDENT_AVDP &&
 						location == udf_variable_to_fixed(last[i]) - 256)
 					{
 						UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
@@ -659,7 +660,7 @@
 			location = le32_to_cpu(((tag *)bh->b_data)->tagLocation);
 			udf_release_data(bh);
 
-			if (ident == TID_ANCHOR_VOL_DESC_PTR && location == 256)
+			if (ident == TAG_IDENT_AVDP && location == 256)
 				UDF_SET_FLAG(sb, UDF_FLAG_VARCONV);
 		}
 	}
@@ -676,8 +677,8 @@
 			else
 			{
 				udf_release_data(bh);
-				if ((ident != TID_ANCHOR_VOL_DESC_PTR) && (i ||
-					(ident != TID_FILE_ENTRY && ident != TID_EXTENDED_FILE_ENTRY)))
+				if ((ident != TAG_IDENT_AVDP) && (i ||
+					(ident != TAG_IDENT_FE && ident != TAG_IDENT_EFE)))
 				{
 					UDF_SB_ANCHOR(sb)[i] = 0;
 				}
@@ -693,7 +694,7 @@
 {
 	struct buffer_head *bh = NULL;
 	long lastblock;
-	Uint16 ident;
+	uint16_t ident;
 
 	if (fileset->logicalBlockNum != 0xFFFFFFFF ||
 		fileset->partitionReferenceNum != 0xFFFF)
@@ -702,7 +703,7 @@
 
 		if (!bh)
 			return 1;
-		else if (ident != TID_FILE_SET_DESC)
+		else if (ident != TAG_IDENT_FSD)
 		{
 			udf_release_data(bh);
 			return 1;
@@ -736,17 +737,17 @@
 
 				switch (ident)
 				{
-					case TID_SPACE_BITMAP_DESC:
+					case TAG_IDENT_SBD:
 					{
-						struct SpaceBitmapDesc *sp;
-						sp = (struct SpaceBitmapDesc *)bh->b_data;
+						struct spaceBitmapDesc *sp;
+						sp = (struct spaceBitmapDesc *)bh->b_data;
 						newfileset.logicalBlockNum += 1 +
-							((le32_to_cpu(sp->numOfBytes) + sizeof(struct SpaceBitmapDesc) - 1)
+							((le32_to_cpu(sp->numOfBytes) + sizeof(struct spaceBitmapDesc) - 1)
 								>> sb->s_blocksize_bits);
 						udf_release_data(bh);
 						break;
 					}
-					case TID_FILE_SET_DESC:
+					case TAG_IDENT_FSD:
 					{
 						*fileset = newfileset;
 						break;
@@ -783,13 +784,13 @@
 static void 
 udf_load_pvoldesc(struct super_block *sb, struct buffer_head *bh)
 {
-	struct PrimaryVolDesc *pvoldesc;
+	struct primaryVolDesc *pvoldesc;
 	time_t recording;
 	long recording_usec;
 	struct ustr instr;
 	struct ustr outstr;
 
-	pvoldesc = (struct PrimaryVolDesc *)bh->b_data;
+	pvoldesc = (struct primaryVolDesc *)bh->b_data;
 
 	if ( udf_stamp_to_time(&recording, &recording_usec,
 		lets_to_cpu(pvoldesc->recordingDateAndTime)) )
@@ -822,9 +823,9 @@
 static void 
 udf_load_fileset(struct super_block *sb, struct buffer_head *bh, lb_addr *root)
 {
-	struct FileSetDesc *fset;
+	struct fileSetDesc *fset;
 
-	fset = (struct FileSetDesc *)bh->b_data;
+	fset = (struct fileSetDesc *)bh->b_data;
 
 	*root = lelb_to_cpu(fset->rootDirectoryICB.extLocation);
 
@@ -837,10 +838,10 @@
 static void 
 udf_load_partdesc(struct super_block *sb, struct buffer_head *bh)
 {
-	struct PartitionDesc *p;
+	struct partitionDesc *p;
 	int i;
 
-	p = (struct PartitionDesc *)bh->b_data;
+	p = (struct partitionDesc *)bh->b_data;
 
 	for (i=0; i<UDF_SB_NUMPARTS(sb); i++)
 	{
@@ -850,34 +851,42 @@
 		{
 			UDF_SB_PARTLEN(sb,i) = le32_to_cpu(p->partitionLength); /* blocks */
 			UDF_SB_PARTROOT(sb,i) = le32_to_cpu(p->partitionStartingLocation) + UDF_SB_SESSION(sb);
-
-			if (!strcmp(p->partitionContents.ident, PARTITION_CONTENTS_NSR02) ||
-				!strcmp(p->partitionContents.ident, PARTITION_CONTENTS_NSR03))
+			if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_READ_ONLY)
+				UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_READ_ONLY;
+			if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_WRITE_ONCE)
+				UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_WRITE_ONCE;
+			if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_REWRITABLE)
+				UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_REWRITABLE;
+			if (le32_to_cpu(p->accessType) == PD_ACCESS_TYPE_OVERWRITABLE)
+				UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_OVERWRITABLE;
+
+			if (!strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR02) ||
+				!strcmp(p->partitionContents.ident, PD_PARTITION_CONTENTS_NSR03))
 			{
-				struct PartitionHeaderDesc *phd;
+				struct partitionHeaderDesc *phd;
 
-				phd = (struct PartitionHeaderDesc *)(p->partitionContentsUse);
-				if (phd->unallocatedSpaceTable.extLength)
+				phd = (struct partitionHeaderDesc *)(p->partitionContentsUse);
+				if (phd->unallocSpaceTable.extLength)
 				{
-					lb_addr loc = { le32_to_cpu(phd->unallocatedSpaceTable.extPosition), i };
+					lb_addr loc = { le32_to_cpu(phd->unallocSpaceTable.extPosition), i };
 
 					UDF_SB_PARTMAPS(sb)[i].s_uspace.s_table =
 						udf_iget(sb, loc);
 					UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_UNALLOC_TABLE;
-					udf_debug("unallocatedSpaceTable (part %d) @ %ld\n",
+					udf_debug("unallocSpaceTable (part %d) @ %ld\n",
 						i, UDF_SB_PARTMAPS(sb)[i].s_uspace.s_table->i_ino);
 				}
-				if (phd->unallocatedSpaceBitmap.extLength)
+				if (phd->unallocSpaceBitmap.extLength)
 				{
 					UDF_SB_ALLOC_BITMAP(sb, i, s_uspace);
 					if (UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap != NULL)
 					{
 						UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap->s_extLength =
-							le32_to_cpu(phd->unallocatedSpaceBitmap.extLength);
+							le32_to_cpu(phd->unallocSpaceBitmap.extLength);
 						UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap->s_extPosition =
-							le32_to_cpu(phd->unallocatedSpaceBitmap.extPosition);
+							le32_to_cpu(phd->unallocSpaceBitmap.extPosition);
 						UDF_SB_PARTFLAGS(sb,i) |= UDF_PART_FLAG_UNALLOC_BITMAP;
-						udf_debug("unallocatedSpaceBitmap (part %d) @ %d\n",
+						udf_debug("unallocSpaceBitmap (part %d) @ %d\n",
 							i, UDF_SB_PARTMAPS(sb)[i].s_uspace.s_bitmap->s_extPosition);
 					}
 				}
@@ -926,22 +935,22 @@
 static int 
 udf_load_logicalvol(struct super_block *sb, struct buffer_head * bh, lb_addr *fileset)
 {
-	struct LogicalVolDesc *lvd;
+	struct logicalVolDesc *lvd;
 	int i, j, offset;
-	Uint8 type;
+	uint8_t type;
 
-	lvd = (struct LogicalVolDesc *)bh->b_data;
+	lvd = (struct logicalVolDesc *)bh->b_data;
 
 	UDF_SB_ALLOC_PARTMAPS(sb, le32_to_cpu(lvd->numPartitionMaps));
 
 	for (i=0,offset=0;
 		 i<UDF_SB_NUMPARTS(sb) && offset<le32_to_cpu(lvd->mapTableLength);
-		 i++,offset+=((struct GenericPartitionMap *)&(lvd->partitionMaps[offset]))->partitionMapLength)
+		 i++,offset+=((struct genericPartitionMap *)&(lvd->partitionMaps[offset]))->partitionMapLength)
 	{
-		type = ((struct GenericPartitionMap *)&(lvd->partitionMaps[offset]))->partitionMapType;
+		type = ((struct genericPartitionMap *)&(lvd->partitionMaps[offset]))->partitionMapType;
 		if (type == 1)
 		{
-			struct GenericPartitionMap1 *gpm1 = (struct GenericPartitionMap1 *)&(lvd->partitionMaps[offset]);
+			struct genericPartitionMap1 *gpm1 = (struct genericPartitionMap1 *)&(lvd->partitionMaps[offset]);
 			UDF_SB_PARTTYPE(sb,i) = UDF_TYPE1_MAP15;
 			UDF_SB_PARTVSN(sb,i) = le16_to_cpu(gpm1->volSeqNum);
 			UDF_SB_PARTNUM(sb,i) = le16_to_cpu(gpm1->partitionNum);
@@ -949,15 +958,15 @@
 		}
 		else if (type == 2)
 		{
-			struct UdfPartitionMap2 *upm2 = (struct UdfPartitionMap2 *)&(lvd->partitionMaps[offset]);
+			struct udfPartitionMap2 *upm2 = (struct udfPartitionMap2 *)&(lvd->partitionMaps[offset]);
 			if (!strncmp(upm2->partIdent.ident, UDF_ID_VIRTUAL, strlen(UDF_ID_VIRTUAL)))
 			{
-				if (le16_to_cpu(((Uint16 *)upm2->partIdent.identSuffix)[0]) == 0x0150)
+				if (le16_to_cpu(((uint16_t *)upm2->partIdent.identSuffix)[0]) == 0x0150)
 				{
 					UDF_SB_PARTTYPE(sb,i) = UDF_VIRTUAL_MAP15;
 					UDF_SB_PARTFUNC(sb,i) = udf_get_pblock_virt15;
 				}
-				else if (le16_to_cpu(((Uint16 *)upm2->partIdent.identSuffix)[0]) == 0x0200)
+				else if (le16_to_cpu(((uint16_t *)upm2->partIdent.identSuffix)[0]) == 0x0200)
 				{
 					UDF_SB_PARTTYPE(sb,i) = UDF_VIRTUAL_MAP20;
 					UDF_SB_PARTFUNC(sb,i) = udf_get_pblock_virt20;
@@ -965,10 +974,10 @@
 			}
 			else if (!strncmp(upm2->partIdent.ident, UDF_ID_SPARABLE, strlen(UDF_ID_SPARABLE)))
 			{
-				Uint32 loc;
-				Uint16 ident;
-				struct SparingTable *st;
-				struct SparablePartitionMap *spm = (struct SparablePartitionMap *)&(lvd->partitionMaps[offset]);
+				uint32_t loc;
+				uint16_t ident;
+				struct sparingTable *st;
+				struct sparablePartitionMap *spm = (struct sparablePartitionMap *)&(lvd->partitionMaps[offset]);
 
 				UDF_SB_PARTTYPE(sb,i) = UDF_SPARABLE_MAP15;
 				UDF_SB_TYPESPAR(sb,i).s_packet_len = le16_to_cpu(spm->packetLength);
@@ -979,7 +988,7 @@
 						udf_read_tagged(sb, loc, loc, &ident);
 					if (UDF_SB_TYPESPAR(sb,i).s_spar_map[j] != NULL)
 					{
-						st = (struct SparingTable *)UDF_SB_TYPESPAR(sb,i).s_spar_map[j]->b_data;
+						st = (struct sparingTable *)UDF_SB_TYPESPAR(sb,i).s_spar_map[j]->b_data;
 						if (ident != 0 ||
 							strncmp(st->sparingIdent.ident, UDF_ID_SPARING, strlen(UDF_ID_SPARING)))
 						{
@@ -1024,12 +1033,12 @@
 udf_load_logicalvolint(struct super_block *sb, extent_ad loc)
 {
 	struct buffer_head *bh = NULL;
-	Uint16 ident;
+	uint16_t ident;
 
 	while (loc.extLength > 0 &&
 		(bh = udf_read_tagged(sb, loc.extLocation,
 			loc.extLocation, &ident)) &&
-		ident == TID_LOGICAL_VOL_INTEGRITY_DESC)
+		ident == TAG_IDENT_LVID)
 	{
 		UDF_SB_LVIDBH(sb) = bh;
 		
@@ -1065,12 +1074,12 @@
 {
 	struct buffer_head *bh = NULL;
 	struct udf_vds_record vds[VDS_POS_LENGTH];
-	struct GenericDesc *gd;
-	struct VolDescPtr *vdp;
+	struct generic_desc *gd;
+	struct volDescPtr *vdp;
 	int done=0;
 	int i,j;
-	Uint32 vdsn;
-	Uint16 ident;
+	uint32_t vdsn;
+	uint16_t ident;
 	long next_s = 0, next_e = 0;
 
 	memset(vds, 0, sizeof(struct udf_vds_record) * VDS_POS_LENGTH);
@@ -1084,56 +1093,56 @@
 			break;
 
 		/* Process each descriptor (ISO 13346 3/8.3-8.4) */
-		gd = (struct GenericDesc *)bh->b_data;
+		gd = (struct generic_desc *)bh->b_data;
 		vdsn = le32_to_cpu(gd->volDescSeqNum);
 		switch (ident)
 		{
-			case TID_PRIMARY_VOL_DESC: /* ISO 13346 3/10.1 */
+			case TAG_IDENT_PVD: /* ISO 13346 3/10.1 */
 				if (vdsn >= vds[VDS_POS_PRIMARY_VOL_DESC].volDescSeqNum)
 				{
 					vds[VDS_POS_PRIMARY_VOL_DESC].volDescSeqNum = vdsn;
 					vds[VDS_POS_PRIMARY_VOL_DESC].block = block;
 				}
 				break;
-			case TID_VOL_DESC_PTR: /* ISO 13346 3/10.3 */
+			case TAG_IDENT_VDP: /* ISO 13346 3/10.3 */
 				if (vdsn >= vds[VDS_POS_VOL_DESC_PTR].volDescSeqNum)
 				{
 					vds[VDS_POS_VOL_DESC_PTR].volDescSeqNum = vdsn;
 					vds[VDS_POS_VOL_DESC_PTR].block = block;
 
-					vdp = (struct VolDescPtr *)bh->b_data;
+					vdp = (struct volDescPtr *)bh->b_data;
 					next_s = le32_to_cpu(vdp->nextVolDescSeqExt.extLocation);
 					next_e = le32_to_cpu(vdp->nextVolDescSeqExt.extLength);
 					next_e = next_e >> sb->s_blocksize_bits;
 					next_e += next_s;
 				}
 				break;
-			case TID_IMP_USE_VOL_DESC: /* ISO 13346 3/10.4 */
+			case TAG_IDENT_IUVD: /* ISO 13346 3/10.4 */
 				if (vdsn >= vds[VDS_POS_IMP_USE_VOL_DESC].volDescSeqNum)
 				{
 					vds[VDS_POS_IMP_USE_VOL_DESC].volDescSeqNum = vdsn;
 					vds[VDS_POS_IMP_USE_VOL_DESC].block = block;
 				}
 				break;
-			case TID_PARTITION_DESC: /* ISO 13346 3/10.5 */
+			case TAG_IDENT_PD: /* ISO 13346 3/10.5 */
 				if (!vds[VDS_POS_PARTITION_DESC].block)
 					vds[VDS_POS_PARTITION_DESC].block = block;
 				break;
-			case TID_LOGICAL_VOL_DESC: /* ISO 13346 3/10.6 */
+			case TAG_IDENT_LVD: /* ISO 13346 3/10.6 */
 				if (vdsn >= vds[VDS_POS_LOGICAL_VOL_DESC].volDescSeqNum)
 				{
 					vds[VDS_POS_LOGICAL_VOL_DESC].volDescSeqNum = vdsn;
 					vds[VDS_POS_LOGICAL_VOL_DESC].block = block;
 				}
 				break;
-			case TID_UNALLOC_SPACE_DESC: /* ISO 13346 3/10.8 */
+			case TAG_IDENT_USD: /* ISO 13346 3/10.8 */
 				if (vdsn >= vds[VDS_POS_UNALLOC_SPACE_DESC].volDescSeqNum)
 				{
 					vds[VDS_POS_UNALLOC_SPACE_DESC].volDescSeqNum = vdsn;
 					vds[VDS_POS_UNALLOC_SPACE_DESC].block = block;
 				}
 				break;
-			case TID_TERMINATING_DESC: /* ISO 13346 3/10.9 */
+			case TAG_IDENT_TD: /* ISO 13346 3/10.9 */
 				vds[VDS_POS_TERMINATING_DESC].block = block;
 				if (next_e)
 				{
@@ -1164,8 +1173,8 @@
 				for (j=vds[i].block+1; j<vds[VDS_POS_TERMINATING_DESC].block; j++)
 				{
 					bh2 = udf_read_tagged(sb, j, j, &ident);
-					gd = (struct GenericDesc *)bh2->b_data;
-					if (ident == TID_PARTITION_DESC)
+					gd = (struct generic_desc *)bh2->b_data;
+					if (ident == TAG_IDENT_PD)
 						udf_load_partdesc(sb, bh2);
 					udf_release_data(bh2);
 				}
@@ -1206,8 +1215,8 @@
 static int
 udf_load_partition(struct super_block *sb, lb_addr *fileset)
 {
-	struct AnchorVolDescPtr *anchor;
-	Uint16 ident;
+	struct anchorVolDescPtr *anchor;
+	uint16_t ident;
 	struct buffer_head *bh;
 	long main_s, main_e, reserve_s, reserve_e;
 	int i, j;
@@ -1220,7 +1229,7 @@
 		if (UDF_SB_ANCHOR(sb)[i] && (bh = udf_read_tagged(sb,
 			UDF_SB_ANCHOR(sb)[i], UDF_SB_ANCHOR(sb)[i], &ident)))
 		{
-			anchor = (struct AnchorVolDescPtr *)bh->b_data;
+			anchor = (struct anchorVolDescPtr *)bh->b_data;
 
 			/* Locate the main sequence */
 			main_s = le32_to_cpu( anchor->mainVolDescSeqExt.extLocation );
@@ -1302,12 +1311,12 @@
 				else if (UDF_SB_PARTTYPE(sb,i) == UDF_VIRTUAL_MAP20)
 				{
 					struct buffer_head *bh = NULL;
-					Uint32 pos;
+					uint32_t pos;
 
 					pos = udf_block_map(UDF_SB_VAT(sb), 0);
 					bh = sb_bread(sb, pos);
 					UDF_SB_TYPEVIRT(sb,i).s_start_offset =
-						le16_to_cpu(((struct VirtualAllocationTable20 *)bh->b_data + udf_ext0_offset(UDF_SB_VAT(sb)))->lengthHeader) +
+						le16_to_cpu(((struct virtualAllocationTable20 *)bh->b_data + udf_ext0_offset(UDF_SB_VAT(sb)))->lengthHeader) +
 							udf_ext0_offset(UDF_SB_VAT(sb));
 					UDF_SB_TYPEVIRT(sb,i).s_num_entries = (UDF_SB_VAT(sb)->i_size -
 						UDF_SB_TYPEVIRT(sb,i).s_start_offset) >> 2;
@@ -1332,7 +1341,7 @@
 		UDF_SB_LVIDIU(sb)->impIdent.identSuffix[1] = UDF_OS_ID_LINUX;
 		if (udf_time_to_stamp(&cpu_time, CURRENT_TIME, CURRENT_UTIME))
 			UDF_SB_LVID(sb)->recordingDateAndTime = cpu_to_lets(cpu_time);
-		UDF_SB_LVID(sb)->integrityType = INTEGRITY_TYPE_OPEN;
+		UDF_SB_LVID(sb)->integrityType = LVID_INTEGRITY_TYPE_OPEN;
 
 		UDF_SB_LVID(sb)->descTag.descCRC =
 			cpu_to_le16(udf_crc((char *)UDF_SB_LVID(sb) + sizeof(tag),
@@ -1342,7 +1351,7 @@
 		for (i=0; i<16; i++)
 			if (i != 4)
 				UDF_SB_LVID(sb)->descTag.tagChecksum +=
-					((Uint8 *)&(UDF_SB_LVID(sb)->descTag))[i];
+					((uint8_t *)&(UDF_SB_LVID(sb)->descTag))[i];
 
 		mark_buffer_dirty(UDF_SB_LVIDBH(sb));
 	}
@@ -1351,7 +1360,7 @@
 static void udf_close_lvid(struct super_block *sb)
 {
 	if (UDF_SB_LVIDBH(sb) &&
-		UDF_SB_LVID(sb)->integrityType == INTEGRITY_TYPE_OPEN)
+		UDF_SB_LVID(sb)->integrityType == LVID_INTEGRITY_TYPE_OPEN)
 	{
 		int i;
 		timestamp cpu_time;
@@ -1366,7 +1375,7 @@
 			UDF_SB_LVIDIU(sb)->minUDFReadRev = cpu_to_le16(UDF_SB_UDFREV(sb));
 		if (UDF_SB_UDFREV(sb) > le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFWriteRev))
 			UDF_SB_LVIDIU(sb)->minUDFWriteRev = cpu_to_le16(UDF_SB_UDFREV(sb));
-		UDF_SB_LVID(sb)->integrityType = INTEGRITY_TYPE_CLOSE;
+		UDF_SB_LVID(sb)->integrityType = LVID_INTEGRITY_TYPE_CLOSE;
 
 		UDF_SB_LVID(sb)->descTag.descCRC =
 			cpu_to_le16(udf_crc((char *)UDF_SB_LVID(sb) + sizeof(tag),
@@ -1376,7 +1385,7 @@
 		for (i=0; i<16; i++)
 			if (i != 4)
 				UDF_SB_LVID(sb)->descTag.tagChecksum +=
-					((Uint8 *)&(UDF_SB_LVID(sb)->descTag))[i];
+					((uint8_t *)&(UDF_SB_LVID(sb)->descTag))[i];
 
 		mark_buffer_dirty(UDF_SB_LVIDBH(sb));
 	}
@@ -1488,9 +1497,9 @@
 
 	if ( UDF_SB_LVIDBH(sb) )
 	{
-		Uint16 minUDFReadRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFReadRev);
-		Uint16 minUDFWriteRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFWriteRev);
-		/* Uint16 maxUDFWriteRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->maxUDFWriteRev); */
+		uint16_t minUDFReadRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFReadRev);
+		uint16_t minUDFWriteRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->minUDFWriteRev);
+		/* uint16_t maxUDFWriteRev = le16_to_cpu(UDF_SB_LVIDIU(sb)->maxUDFWriteRev); */
 
 		if (minUDFReadRev > UDF_MAX_READ_VERSION)
 		{
@@ -1733,11 +1742,11 @@
 	int index;
 	int block = 0, newblock;
 	lb_addr loc;
-	Uint32 bytes;
-	Uint8 value;
-	Uint8 *ptr;
-	Uint16 ident;
-	struct SpaceBitmapDesc *bm;
+	uint32_t bytes;
+	uint8_t value;
+	uint8_t *ptr;
+	uint16_t ident;
+	struct spaceBitmapDesc *bm;
 
 	loc.logicalBlockNum = bitmap->s_extPosition;
 	loc.partitionReferenceNum = UDF_SB_PARTITION(sb);
@@ -1748,17 +1757,17 @@
 		printk(KERN_ERR "udf: udf_count_free failed\n");
 		return 0;
 	}
-	else if (ident != TID_SPACE_BITMAP_DESC)
+	else if (ident != TAG_IDENT_SBD)
 	{
 		udf_release_data(bh);
 		printk(KERN_ERR "udf: udf_count_free failed\n");
 		return 0;
 	}
 
-	bm = (struct SpaceBitmapDesc *)bh->b_data;
+	bm = (struct spaceBitmapDesc *)bh->b_data;
 	bytes = bm->numOfBytes;
-	index = sizeof(struct SpaceBitmapDesc); /* offset in first block only */
-	ptr = (Uint8 *)bh->b_data;
+	index = sizeof(struct spaceBitmapDesc); /* offset in first block only */
+	ptr = (uint8_t *)bh->b_data;
 
 	while ( bytes > 0 )
 	{
@@ -1781,7 +1790,7 @@
 				return accum;
 			}
 			index = 0;
-			ptr = (Uint8 *)bh->b_data;
+			ptr = (uint8_t *)bh->b_data;
 		}
 	}
 	udf_release_data(bh);
@@ -1792,13 +1801,13 @@
 udf_count_free_table(struct super_block *sb, struct inode * table)
 {
 	unsigned int accum = 0;
-	Uint32 extoffset, elen;
+	uint32_t extoffset, elen;
 	lb_addr bloc, eloc;
-	Sint8 etype;
+	int8_t etype;
 	struct buffer_head *bh = NULL;
 
 	bloc = UDF_I_LOCATION(table);
-	extoffset = sizeof(struct UnallocatedSpaceEntry);
+	extoffset = sizeof(struct unallocSpaceEntry);
 
 	while ((etype = udf_next_aext(table, &bloc, &extoffset, &eloc, &elen, &bh, 1)) != -1)
 	{
diff -Nru a/fs/udf/symlink.c b/fs/udf/symlink.c
--- a/fs/udf/symlink.c	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/symlink.c	Fri Mar 15 17:51:02 2002
@@ -15,7 +15,7 @@
  *		ftp://prep.ai.mit.edu/pub/gnu/GPL
  *	Each contributing author retains all rights to their own work.
  *
- *  (C) 1998-2000 Ben Fennema
+ *  (C) 1998-2001 Ben Fennema
  *  (C) 1999 Stelias Computing Inc 
  *
  * HISTORY
@@ -39,13 +39,13 @@
 
 static void udf_pc_to_char(char *from, int fromlen, char *to)
 {
-	struct PathComponent *pc;
+	struct pathComponent *pc;
 	int elen = 0;
 	char *p = to;
 
 	while (elen < fromlen)
 	{
-		pc = (struct PathComponent *)(from + elen);
+		pc = (struct pathComponent *)(from + elen);
 		switch (pc->componentType)
 		{
 			case 1:
@@ -69,7 +69,7 @@
 				p += pc->lengthComponentIdent;
 				*p++ = '/';
 		}
-		elen += sizeof(struct PathComponent) + pc->lengthComponentIdent;
+		elen += sizeof(struct pathComponent) + pc->lengthComponentIdent;
 	}
 	if (p > to+1)
 		p[-1] = '\0';
@@ -86,7 +86,7 @@
 	char *p = kmap(page);
 	
 	lock_kernel();
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB)
 	{
 		bh = udf_tread(inode->i_sb, inode->i_ino);
 
diff -Nru a/fs/udf/truncate.c b/fs/udf/truncate.c
--- a/fs/udf/truncate.c	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/truncate.c	Fri Mar 15 17:51:02 2002
@@ -15,7 +15,7 @@
  *		ftp://prep.ai.mit.edu/pub/gnu/GPL
  *	Each contributing author retains all rights to their own work.
  *
- *  (C) 1999-2000 Ben Fennema
+ *  (C) 1999-2001 Ben Fennema
  *  (C) 1999 Stelias Computing Inc
  *
  * HISTORY
@@ -33,7 +33,7 @@
 #include "udf_sb.h"
 
 static void extent_trunc(struct inode * inode, lb_addr bloc, int extoffset,
-	lb_addr eloc, Sint8 etype, Uint32 elen, struct buffer_head *bh, Uint32 nelen)
+	lb_addr eloc, int8_t etype, uint32_t elen, struct buffer_head *bh, uint32_t nelen)
 {
 	lb_addr neloc = { 0, 0 };
 	int last_block = (elen + inode->i_sb->s_blocksize - 1) >> inode->i_sb->s_blocksize_bits;
@@ -41,7 +41,13 @@
 
 	if (nelen)
 	{
-		neloc = eloc;
+		if (etype == (EXT_NOT_RECORDED_ALLOCATED >> 30))
+		{
+			udf_free_blocks(inode->i_sb, inode, eloc, 0, last_block);
+			etype = (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30);
+		}
+		else
+			neloc = eloc;
 		nelen = (etype << 30) | nelen;
 	}
 
@@ -50,10 +56,10 @@
 		udf_write_aext(inode, bloc, &extoffset, neloc, nelen, bh, 0);
 		if (last_block - first_block > 0)
 		{
-			if (etype == EXTENT_RECORDED_ALLOCATED)
+			if (etype == (EXT_RECORDED_ALLOCATED >> 30))
 				mark_inode_dirty(inode);
 
-			if (etype != EXTENT_NOT_RECORDED_NOT_ALLOCATED)
+			if (etype != (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
 				udf_free_blocks(inode->i_sb, inode, eloc, first_block, last_block - first_block);
 		}
 	}
@@ -62,15 +68,15 @@
 void udf_truncate_extents(struct inode * inode)
 {
 	lb_addr bloc, eloc, neloc = { 0, 0 };
-	Uint32 extoffset, elen, offset, nelen = 0, lelen = 0, lenalloc;
-	Sint8 etype;
+	uint32_t extoffset, elen, offset, nelen = 0, lelen = 0, lenalloc;
+	int8_t etype;
 	int first_block = inode->i_size >> inode->i_sb->s_blocksize_bits;
 	struct buffer_head *bh = NULL;
 	int adsize;
 
-	if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_SHORT)
+	if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_SHORT)
 		adsize = sizeof(short_ad);
-	else if (UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_LONG)
+	else if (UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_LONG)
 		adsize = sizeof(long_ad);
 	else
 		adsize = 0;
@@ -91,11 +97,11 @@
 		if (!memcmp(&UDF_I_LOCATION(inode), &bloc, sizeof(lb_addr)))
 			lenalloc -= udf_file_entry_alloc_offset(inode);
 		else
-			lenalloc -= sizeof(struct AllocExtDesc);
+			lenalloc -= sizeof(struct allocExtDesc);
 
 		while ((etype = udf_current_aext(inode, &bloc, &extoffset, &eloc, &elen, &bh, 0)) != -1)
 		{
-			if (etype == EXTENT_NEXT_EXTENT_ALLOCDECS)
+			if (etype == (EXT_NEXT_EXTENT_ALLOCDECS >> 30))
 			{
 				udf_write_aext(inode, bloc, &extoffset, neloc, nelen, bh, 0);
 				extoffset = 0;
@@ -104,7 +110,7 @@
 					if (!memcmp(&UDF_I_LOCATION(inode), &bloc, sizeof(lb_addr)))
 						memset(bh->b_data, 0x00, udf_file_entry_alloc_offset(inode));
 					else
-						memset(bh->b_data, 0x00, sizeof(struct AllocExtDesc));
+						memset(bh->b_data, 0x00, sizeof(struct allocExtDesc));
 					udf_free_blocks(inode->i_sb, inode, bloc, 0, lelen);
 				}
 				else
@@ -116,13 +122,13 @@
 					}
 					else
 					{
-						struct AllocExtDesc *aed = (struct AllocExtDesc *)(bh->b_data);
+						struct allocExtDesc *aed = (struct allocExtDesc *)(bh->b_data);
 						aed->lengthAllocDescs = cpu_to_le32(lenalloc);
 						if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 							udf_update_tag(bh->b_data, lenalloc +
-								sizeof(struct AllocExtDesc));
+								sizeof(struct allocExtDesc));
 						else
-							udf_update_tag(bh->b_data, sizeof(struct AllocExtDesc));
+							udf_update_tag(bh->b_data, sizeof(struct allocExtDesc));
 						mark_buffer_dirty_inode(bh, inode);
 					}
 				}
@@ -149,7 +155,7 @@
 			if (!memcmp(&UDF_I_LOCATION(inode), &bloc, sizeof(lb_addr)))
 				memset(bh->b_data, 0x00, udf_file_entry_alloc_offset(inode));
 			else
-				memset(bh->b_data, 0x00, sizeof(struct AllocExtDesc));
+				memset(bh->b_data, 0x00, sizeof(struct allocExtDesc));
 			udf_free_blocks(inode->i_sb, inode, bloc, 0, lelen);
 		}
 		else
@@ -161,13 +167,13 @@
 			}
 			else
 			{
-				struct AllocExtDesc *aed = (struct AllocExtDesc *)(bh->b_data);
+				struct allocExtDesc *aed = (struct allocExtDesc *)(bh->b_data);
 				aed->lengthAllocDescs = cpu_to_le32(lenalloc);
 				if (!UDF_QUERY_FLAG(inode->i_sb, UDF_FLAG_STRICT) || UDF_SB_UDFREV(inode->i_sb) >= 0x0201)
 					udf_update_tag(bh->b_data, lenalloc +
-						sizeof(struct AllocExtDesc));
+						sizeof(struct allocExtDesc));
 				else
-					udf_update_tag(bh->b_data, sizeof(struct AllocExtDesc));
+					udf_update_tag(bh->b_data, sizeof(struct allocExtDesc));
 				mark_buffer_dirty_inode(bh, inode);
 			}
 		}
@@ -178,17 +184,17 @@
 		{
 			extoffset -= adsize;
 			etype = udf_next_aext(inode, &bloc, &extoffset, &eloc, &elen, &bh, 1);
-			if (etype == EXTENT_NOT_RECORDED_NOT_ALLOCATED)
+			if (etype == (EXT_NOT_RECORDED_NOT_ALLOCATED >> 30))
 			{
 				extoffset -= adsize;
-				elen = (EXTENT_NOT_RECORDED_NOT_ALLOCATED << 30) | (elen + offset);
+				elen = EXT_NOT_RECORDED_NOT_ALLOCATED | (elen + offset);
 				udf_write_aext(inode, bloc, &extoffset, eloc, elen, bh, 0);
 			}
-			else if (etype == EXTENT_NOT_RECORDED_ALLOCATED)
+			else if (etype == (EXT_NOT_RECORDED_ALLOCATED >> 30))
 			{
 				lb_addr neloc = { 0, 0 };
 				extoffset -= adsize;
-				nelen = (EXTENT_NOT_RECORDED_NOT_ALLOCATED << 30) |
+				nelen = EXT_NOT_RECORDED_NOT_ALLOCATED |
 					((elen + offset + inode->i_sb->s_blocksize - 1) &
 					~(inode->i_sb->s_blocksize - 1));
 				udf_write_aext(inode, bloc, &extoffset, neloc, nelen, bh, 1);
@@ -199,13 +205,13 @@
 				if (elen & (inode->i_sb->s_blocksize - 1))
 				{
 					extoffset -= adsize;
-					elen = (EXTENT_RECORDED_ALLOCATED << 30) |
+					elen = EXT_RECORDED_ALLOCATED |
 						((elen + inode->i_sb->s_blocksize - 1) &
 						~(inode->i_sb->s_blocksize - 1));
 					udf_write_aext(inode, bloc, &extoffset, eloc, elen, bh, 1);
 				}
 				memset(&eloc, 0x00, sizeof(lb_addr));
-				elen = (EXTENT_NOT_RECORDED_NOT_ALLOCATED << 30) | offset;
+				elen = EXT_NOT_RECORDED_NOT_ALLOCATED | offset;
 				udf_add_aext(inode, &bloc, &extoffset, eloc, elen, &bh, 1);
 			}
 		}
diff -Nru a/fs/udf/udf_i.h b/fs/udf/udf_i.h
--- a/fs/udf/udf_i.h	Fri Mar 15 17:51:01 2002
+++ b/fs/udf/udf_i.h	Fri Mar 15 17:51:01 2002
@@ -13,7 +13,7 @@
 #define UDF_I_LENEXTENTS(X)	( UDF_I(X)->i_lenExtents )
 #define UDF_I_UNIQUE(X)		( UDF_I(X)->i_unique )
 #define UDF_I_ALLOCTYPE(X)	( UDF_I(X)->i_alloc_type )
-#define UDF_I_EXTENDED_FE(X)( UDF_I(X)->i_extended_fe )
+#define UDF_I_EXTENDED_FE(X)	( UDF_I(X)->i_extended_fe )
 #define UDF_I_STRAT4096(X)	( UDF_I(X)->i_strat_4096 )
 #define UDF_I_NEW_INODE(X)	( UDF_I(X)->i_new_inode )
 #define UDF_I_NEXT_ALLOC_BLOCK(X)	( UDF_I(X)->i_next_alloc_block )
diff -Nru a/fs/udf/udf_sb.h b/fs/udf/udf_sb.h
--- a/fs/udf/udf_sb.h	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/udf_sb.h	Fri Mar 15 17:51:02 2002
@@ -25,6 +25,10 @@
 #define UDF_PART_FLAG_UNALLOC_TABLE	0x0002
 #define UDF_PART_FLAG_FREED_BITMAP	0x0004
 #define UDF_PART_FLAG_FREED_TABLE	0x0008
+#define UDF_PART_FLAG_READ_ONLY		0x0010
+#define UDF_PART_FLAG_WRITE_ONCE	0x0020
+#define UDF_PART_FLAG_REWRITABLE	0x0040
+#define UDF_PART_FLAG_OVERWRITABLE	0x0080
 
 #define UDF_SB_FREE(X)\
 {\
@@ -54,7 +58,7 @@
 
 #define UDF_SB_ALLOC_BITMAP(X,Y,Z)\
 {\
-	int nr_groups = ((UDF_SB_PARTLEN((X),(Y)) + (sizeof(struct SpaceBitmapDesc) << 3) +\
+	int nr_groups = ((UDF_SB_PARTLEN((X),(Y)) + (sizeof(struct spaceBitmapDesc) << 3) +\
 		((X)->s_blocksize * 8) - 1) / ((X)->s_blocksize * 8));\
 	UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap = kmalloc(sizeof(struct udf_bitmap) +\
 		sizeof(struct buffer_head *) * nr_groups,\
@@ -74,18 +78,18 @@
 }
 
 
-#define UDF_QUERY_FLAG(X,Y)				( UDF_SB(X)->s_flags & ( 1 << (Y) ) )
-#define UDF_SET_FLAG(X,Y)				( UDF_SB(X)->s_flags |= ( 1 << (Y) ) )
-#define UDF_CLEAR_FLAG(X,Y)				( UDF_SB(X)->s_flags &= ~( 1 << (Y) ) )
+#define UDF_QUERY_FLAG(X,Y)			( UDF_SB(X)->s_flags & ( 1 << (Y) ) )
+#define UDF_SET_FLAG(X,Y)			( UDF_SB(X)->s_flags |= ( 1 << (Y) ) )
+#define UDF_CLEAR_FLAG(X,Y)			( UDF_SB(X)->s_flags &= ~( 1 << (Y) ) )
 
 #define UDF_UPDATE_UDFREV(X,Y)			( ((Y) > UDF_SB_UDFREV(X)) ? UDF_SB_UDFREV(X) = (Y) : UDF_SB_UDFREV(X) )
 
-#define UDF_SB_PARTMAPS(X)				( UDF_SB(X)->s_partmaps )
+#define UDF_SB_PARTMAPS(X)			( UDF_SB(X)->s_partmaps )
 #define UDF_SB_PARTTYPE(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_partition_type )
 #define UDF_SB_PARTROOT(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_partition_root )
-#define UDF_SB_PARTLEN(X,Y)				( UDF_SB_PARTMAPS(X)[(Y)].s_partition_len )
-#define UDF_SB_PARTVSN(X,Y)				( UDF_SB_PARTMAPS(X)[(Y)].s_volumeseqnum )
-#define UDF_SB_PARTNUM(X,Y)				( UDF_SB_PARTMAPS(X)[(Y)].s_partition_num )
+#define UDF_SB_PARTLEN(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_partition_len )
+#define UDF_SB_PARTVSN(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_volumeseqnum )
+#define UDF_SB_PARTNUM(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_partition_num )
 #define UDF_SB_TYPESPAR(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_type_specific.s_sparing )
 #define UDF_SB_TYPEVIRT(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_type_specific.s_virtual )
 #define UDF_SB_PARTFUNC(X,Y)			( UDF_SB_PARTMAPS(X)[(Y)].s_partition_func )
@@ -93,23 +97,23 @@
 #define UDF_SB_BITMAP(X,Y,Z,I)			( UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap->s_block_bitmap[I] )
 #define UDF_SB_BITMAP_NR_GROUPS(X,Y,Z)	( UDF_SB_PARTMAPS(X)[(Y)].Z.s_bitmap->s_nr_groups )
 
-#define UDF_SB_VOLIDENT(X)				( UDF_SB(X)->s_volident )
-#define UDF_SB_NUMPARTS(X)				( UDF_SB(X)->s_partitions )
-#define UDF_SB_PARTITION(X)				( UDF_SB(X)->s_partition )
-#define UDF_SB_SESSION(X)				( UDF_SB(X)->s_session )
-#define UDF_SB_ANCHOR(X)				( UDF_SB(X)->s_anchor )
-#define UDF_SB_LASTBLOCK(X)				( UDF_SB(X)->s_lastblock )
-#define UDF_SB_LVIDBH(X)				( UDF_SB(X)->s_lvidbh )
-#define UDF_SB_LVID(X)					( (struct LogicalVolIntegrityDesc *)UDF_SB_LVIDBH(X)->b_data )
-#define UDF_SB_LVIDIU(X)				( (struct LogicalVolIntegrityDescImpUse *)&(UDF_SB_LVID(X)->impUse[UDF_SB_LVID(X)->numOfPartitions * 2 * sizeof(Uint32)/sizeof(Uint8)]) )
-
-#define UDF_SB_UMASK(X)					( UDF_SB(X)->s_umask )
-#define UDF_SB_GID(X)					( UDF_SB(X)->s_gid )
-#define UDF_SB_UID(X)					( UDF_SB(X)->s_uid )
+#define UDF_SB_VOLIDENT(X)			( UDF_SB(X)->s_volident )
+#define UDF_SB_NUMPARTS(X)			( UDF_SB(X)->s_partitions )
+#define UDF_SB_PARTITION(X)			( UDF_SB(X)->s_partition )
+#define UDF_SB_SESSION(X)			( UDF_SB(X)->s_session )
+#define UDF_SB_ANCHOR(X)			( UDF_SB(X)->s_anchor )
+#define UDF_SB_LASTBLOCK(X)			( UDF_SB(X)->s_lastblock )
+#define UDF_SB_LVIDBH(X)			( UDF_SB(X)->s_lvidbh )
+#define UDF_SB_LVID(X)				( (struct logicalVolIntegrityDesc *)UDF_SB_LVIDBH(X)->b_data )
+#define UDF_SB_LVIDIU(X)			( (struct logicalVolIntegrityDescImpUse *)&(UDF_SB_LVID(X)->impUse[le32_to_cpu(UDF_SB_LVID(X)->numOfPartitions) * 2 * sizeof(uint32_t)/sizeof(uint8_t)]) )
+
+#define UDF_SB_UMASK(X)				( UDF_SB(X)->s_umask )
+#define UDF_SB_GID(X)				( UDF_SB(X)->s_gid )
+#define UDF_SB_UID(X)				( UDF_SB(X)->s_uid )
 #define UDF_SB_RECORDTIME(X)			( UDF_SB(X)->s_recordtime )
-#define UDF_SB_SERIALNUM(X)				( UDF_SB(X)->s_serialnum )
-#define UDF_SB_UDFREV(X)				( UDF_SB(X)->s_udfrev )
-#define UDF_SB_FLAGS(X)					( UDF_SB(X)->s_flags )
-#define UDF_SB_VAT(X)					( UDF_SB(X)->s_vat )
+#define UDF_SB_SERIALNUM(X)			( UDF_SB(X)->s_serialnum )
+#define UDF_SB_UDFREV(X)			( UDF_SB(X)->s_udfrev )
+#define UDF_SB_FLAGS(X)				( UDF_SB(X)->s_flags )
+#define UDF_SB_VAT(X)				( UDF_SB(X)->s_vat )
 
 #endif /* __LINUX_UDF_SB_H */
diff -Nru a/fs/udf/udfdecl.h b/fs/udf/udfdecl.h
--- a/fs/udf/udfdecl.h	Fri Mar 15 17:51:03 2002
+++ b/fs/udf/udfdecl.h	Fri Mar 15 17:51:03 2002
@@ -1,50 +1,49 @@
 #ifndef __UDF_DECL_H
 #define __UDF_DECL_H
 
-#include <linux/udf_167.h>
-#include <linux/udf_udf.h>
-#include "udfend.h"
-
 #include <linux/udf_fs.h>
+#include "ecma_167.h"
+#include "osta_udf.h"
 
-#ifdef __KERNEL__
-
+#include <linux/fs.h>
 #include <linux/config.h>
 #include <linux/types.h>
-#include <linux/fs.h>
+
+#ifndef LINUX_VERSION_CODE
+#include <linux/version.h>
+#endif
 
 #if !defined(CONFIG_UDF_FS) && !defined(CONFIG_UDF_FS_MODULE)
 #define CONFIG_UDF_FS_MODULE
-#include <linux/udf_fs_sb.h>
 #include <linux/udf_fs_i.h>
+#include <linux/udf_fs_sb.h>
 #endif
 
+#include "udfend.h"
+
 #define udf_fixed_to_variable(x) ( ( ( (x) >> 5 ) * 39 ) + ( (x) & 0x0000001F ) )
 #define udf_variable_to_fixed(x) ( ( ( (x) / 39 ) << 5 ) + ( (x) % 39 ) )
 
+#define UDF_EXTENT_LENGTH_MASK	0x3FFFFFFF
+#define UDF_EXTENT_FLAG_MASK	0xC0000000
+
+#define UDF_NAME_PAD		4
+#define UDF_NAME_LEN		255
+#define UDF_PATH_LEN		1023
+
 #define CURRENT_UTIME	(xtime.tv_usec)
 
 #define udf_file_entry_alloc_offset(inode)\
 	((UDF_I_EXTENDED_FE(inode) ?\
-		sizeof(struct ExtendedFileEntry) :\
-		sizeof(struct FileEntry)) + UDF_I_LENEATTR(inode))
+		sizeof(struct extendedFileEntry) :\
+		sizeof(struct fileEntry)) + UDF_I_LENEATTR(inode))
 
 #define udf_ext0_offset(inode)\
-	(UDF_I_ALLOCTYPE(inode) == ICB_FLAG_AD_IN_ICB ?\
+	(UDF_I_ALLOCTYPE(inode) == ICBTAG_FLAG_AD_IN_ICB ?\
 		udf_file_entry_alloc_offset(inode) : 0)
 
 #define udf_get_lb_pblock(sb,loc,offset) udf_get_pblock((sb), (loc).logicalBlockNum, (loc).partitionReferenceNum, (offset))
 
-#else
-
-#include <sys/types.h>
-
-#endif /* __KERNEL__ */
-
-
-
-#ifdef __KERNEL__
-
 struct dentry;
 struct inode;
 struct task_struct;
@@ -67,50 +66,38 @@
 	int eoffset;
 };
 
-#endif /* __KERNEL__ */
-
 struct udf_directory_record
 {
-	Uint32	d_parent;
-	Uint32	d_inode;
-	Uint32	d_name[255];
+	uint32_t	d_parent;
+	uint32_t	d_inode;
+	uint32_t	d_name[255];
 };
 
-
 struct udf_vds_record
 {
-	Uint32 block;
-	Uint32 volDescSeqNum;
+	uint32_t block;
+	uint32_t volDescSeqNum;
 };
 
-struct ktm
+struct generic_desc
 {
-	int tm_sec;
-	int tm_min;
-	int tm_hour;
-	int tm_mday;
-	int tm_mon;
-	int tm_year;
-	int tm_isdst;
+	tag		descTag;
+	uint32_t	volDescSeqNum;
 };
 
 struct ustr
 {
-	Uint8 u_cmpID;
-	Uint8 u_name[UDF_NAME_LEN];
-	Uint8 u_len;
-	Uint8 padding;
-	unsigned long u_hash;
+	uint8_t u_cmpID;
+	uint8_t u_name[UDF_NAME_LEN];
+	uint8_t u_len;
 };
 
-#ifdef __KERNEL__
-
 /* super.c */
 extern void udf_error(struct super_block *, const char *, const char *, ...);
 extern void udf_warning(struct super_block *, const char *, const char *, ...);
 
 /* namei.c */
-extern int udf_write_fi(struct inode *inode, struct FileIdentDesc *, struct FileIdentDesc *, struct udf_fileident_bh *, Uint8 *, Uint8 *);
+extern int udf_write_fi(struct inode *inode, struct fileIdentDesc *, struct fileIdentDesc *, struct udf_fileident_bh *, uint8_t *, uint8_t *);
 
 /* file.c */
 extern int udf_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
@@ -128,24 +115,23 @@
 extern void udf_delete_inode(struct inode *);
 extern void udf_write_inode(struct inode *, int);
 extern long udf_block_map(struct inode *, long);
-extern Sint8 inode_bmap(struct inode *, int, lb_addr *, Uint32 *, lb_addr *, Uint32 *, Uint32 *, struct buffer_head **);
-extern Sint8 udf_add_aext(struct inode *, lb_addr *, int *, lb_addr, Uint32, struct buffer_head **, int);
-extern Sint8 udf_write_aext(struct inode *, lb_addr, int *, lb_addr, Uint32, struct buffer_head *, int);
-extern Sint8 udf_insert_aext(struct inode *, lb_addr, int, lb_addr, Uint32, struct buffer_head *);
-extern Sint8 udf_delete_aext(struct inode *, lb_addr, int, lb_addr, Uint32, struct buffer_head *);
-extern Sint8 udf_next_aext(struct inode *, lb_addr *, int *, lb_addr *, Uint32 *, struct buffer_head **, int);
-extern Sint8 udf_current_aext(struct inode *, lb_addr *, int *, lb_addr *, Uint32 *, struct buffer_head **, int);
+extern int8_t inode_bmap(struct inode *, int, lb_addr *, uint32_t *, lb_addr *, uint32_t *, uint32_t *, struct buffer_head **);
+extern int8_t udf_add_aext(struct inode *, lb_addr *, int *, lb_addr, uint32_t, struct buffer_head **, int);
+extern int8_t udf_write_aext(struct inode *, lb_addr, int *, lb_addr, uint32_t, struct buffer_head *, int);
+extern int8_t udf_insert_aext(struct inode *, lb_addr, int, lb_addr, uint32_t, struct buffer_head *);
+extern int8_t udf_delete_aext(struct inode *, lb_addr, int, lb_addr, uint32_t, struct buffer_head *);
+extern int8_t udf_next_aext(struct inode *, lb_addr *, int *, lb_addr *, uint32_t *, struct buffer_head **, int);
+extern int8_t udf_current_aext(struct inode *, lb_addr *, int *, lb_addr *, uint32_t *, struct buffer_head **, int);
 extern void udf_discard_prealloc(struct inode *);
 
 /* misc.c */
 extern int udf_read_tagged_data(char *, int size, int fd, int block, int partref);
 extern struct buffer_head *udf_tgetblk(struct super_block *, int);
 extern struct buffer_head *udf_tread(struct super_block *, int);
-extern struct GenericAttrFormat *udf_add_extendedattr(struct inode *, Uint32, Uint32, Uint8, struct buffer_head **);
-extern struct GenericAttrFormat *udf_get_extendedattr(struct inode *, Uint32, Uint8, struct buffer_head **);
-extern struct buffer_head *udf_read_tagged(struct super_block *, Uint32, Uint32, Uint16 *);
-extern struct buffer_head *udf_read_ptagged(struct super_block *, lb_addr, Uint32, Uint16 *);
-extern struct buffer_head *udf_read_untagged(struct super_block *, Uint32, Uint32);
+extern struct genericFormat *udf_add_extendedattr(struct inode *, uint32_t, uint32_t, uint8_t, struct buffer_head **);
+extern struct genericFormat *udf_get_extendedattr(struct inode *, uint32_t, uint8_t, struct buffer_head **);
+extern struct buffer_head *udf_read_tagged(struct super_block *, uint32_t, uint32_t, uint16_t *);
+extern struct buffer_head *udf_read_ptagged(struct super_block *, lb_addr, uint32_t, uint16_t *);
 extern void udf_release_data(struct buffer_head *);
 
 /* lowlevel.c */
@@ -153,14 +139,14 @@
 extern unsigned long udf_get_last_block(struct super_block *);
 
 /* partition.c */
-extern Uint32 udf_get_pblock(struct super_block *, Uint32, Uint16, Uint32);
-extern Uint32 udf_get_pblock_virt15(struct super_block *, Uint32, Uint16, Uint32);
-extern Uint32 udf_get_pblock_virt20(struct super_block *, Uint32, Uint16, Uint32);
-extern Uint32 udf_get_pblock_spar15(struct super_block *, Uint32, Uint16, Uint32);
+extern uint32_t udf_get_pblock(struct super_block *, uint32_t, uint16_t, uint32_t);
+extern uint32_t udf_get_pblock_virt15(struct super_block *, uint32_t, uint16_t, uint32_t);
+extern uint32_t udf_get_pblock_virt20(struct super_block *, uint32_t, uint16_t, uint32_t);
+extern uint32_t udf_get_pblock_spar15(struct super_block *, uint32_t, uint16_t, uint32_t);
 extern int udf_relocate_blocks(struct super_block *, long, long *);
 
 /* unicode.c */
-extern int udf_get_filename(struct super_block *, Uint8 *, Uint8 *, int);
+extern int udf_get_filename(struct super_block *, uint8_t *, uint8_t *, int);
 
 /* ialloc.c */
 extern void udf_free_inode(struct inode *);
@@ -170,58 +156,51 @@
 extern void udf_truncate_extents(struct inode *);
 
 /* balloc.c */
-extern void udf_free_blocks(struct super_block *, struct inode *, lb_addr, Uint32, Uint32);
-extern int udf_prealloc_blocks(struct super_block *, struct inode *, Uint16, Uint32, Uint32);
-extern int udf_new_block(struct super_block *, struct inode *, Uint16, Uint32, int *);
+extern void udf_free_blocks(struct super_block *, struct inode *, lb_addr, uint32_t, uint32_t);
+extern int udf_prealloc_blocks(struct super_block *, struct inode *, uint16_t, uint32_t, uint32_t);
+extern int udf_new_block(struct super_block *, struct inode *, uint16_t, uint32_t, int *);
 
 /* fsync.c */
 extern int udf_fsync_file(struct file *, struct dentry *, int);
 extern int udf_fsync_inode(struct inode *, int);
 
 /* directory.c */
-extern Uint8 * udf_filead_read(struct inode *, Uint8 *, Uint8, lb_addr, int *, int *, struct buffer_head **, int *);
-extern struct FileIdentDesc * udf_fileident_read(struct inode *, loff_t *, struct udf_fileident_bh *, struct FileIdentDesc *, lb_addr *, Uint32 *, lb_addr *, Uint32 *, Uint32 *, struct buffer_head **);
-
-#endif /* __KERNEL__ */
-
-/* Miscellaneous UDF Prototypes */
+extern uint8_t * udf_filead_read(struct inode *, uint8_t *, uint8_t, lb_addr, int *, int *, struct buffer_head **, int *);
+extern struct fileIdentDesc * udf_fileident_read(struct inode *, loff_t *, struct udf_fileident_bh *, struct fileIdentDesc *, lb_addr *, uint32_t *, lb_addr *, uint32_t *, uint32_t *, struct buffer_head **);
 
 /* unicode.c */
-extern int udf_ustr_to_dchars(Uint8 *, const struct ustr *, int);
-extern int udf_ustr_to_char(Uint8 *, const struct ustr *, int);
+extern int udf_ustr_to_dchars(uint8_t *, const struct ustr *, int);
+extern int udf_ustr_to_char(uint8_t *, const struct ustr *, int);
 extern int udf_ustr_to_dstring(dstring *, const struct ustr *, int);
-extern int udf_dchars_to_ustr(struct ustr *, const Uint8 *, int);
-extern int udf_char_to_ustr(struct ustr *, const Uint8 *, int);
+extern int udf_dchars_to_ustr(struct ustr *, const uint8_t *, int);
+extern int udf_char_to_ustr(struct ustr *, const uint8_t *, int);
 extern int udf_dstring_to_ustr(struct ustr *, const dstring *, int);
-extern int udf_translate_to_linux(Uint8 *, Uint8 *, int, Uint8 *, int);
+extern int udf_translate_to_linux(uint8_t *, uint8_t *, int, uint8_t *, int);
 extern int udf_build_ustr(struct ustr *, dstring *, int);
 extern int udf_build_ustr_exact(struct ustr *, dstring *, int);
 extern int udf_CS0toUTF8(struct ustr *, struct ustr *);
 extern int udf_UTF8toCS0(dstring *, struct ustr *, int);
-#ifdef __KERNEL__
 extern int udf_CS0toNLS(struct nls_table *, struct ustr *, struct ustr *);
 extern int udf_NLStoCS0(struct nls_table *, dstring *, struct ustr *, int);
-#endif
 
 /* crc.c */
-extern Uint16 udf_crc(Uint8 *, Uint32, Uint16);
+extern uint16_t udf_crc(uint8_t *, uint32_t, uint16_t);
 
 /* misc.c */
-extern Uint32 udf64_low32(Uint64);
-extern Uint32 udf64_high32(Uint64);
+extern uint32_t udf64_low32(uint64_t);
+extern uint32_t udf64_high32(uint64_t);
 extern void udf_update_tag(char *, int);
-extern void udf_new_tag(char *, Uint16, Uint16, Uint16, Uint32, int);
+extern void udf_new_tag(char *, uint16_t, uint16_t, uint16_t, uint32_t, int);
 
 /* udftime.c */
 extern time_t *udf_stamp_to_time(time_t *, long *, timestamp);
 extern timestamp *udf_time_to_stamp(timestamp *, time_t, long);
-extern time_t udf_converttime (struct ktm *);
 
 /* directory.c */
-extern struct FileIdentDesc * udf_get_fileident(void * buffer, int bufsize, int * offset);
+extern struct fileIdentDesc * udf_get_fileident(void * buffer, int bufsize, int * offset);
 extern extent_ad * udf_get_fileextent(void * buffer, int bufsize, int * offset);
 extern long_ad * udf_get_filelongad(void * buffer, int bufsize, int * offset, int);
 extern short_ad * udf_get_fileshortad(void * buffer, int bufsize, int * offset, int);
-extern Uint8 * udf_get_filead(struct FileEntry *, Uint8 *, int, int, int, int *);
+extern uint8_t * udf_get_filead(struct fileEntry *, uint8_t *, int, int, int, int *);
 
 #endif /* __UDF_DECL_H */
diff -Nru a/fs/udf/udfend.h b/fs/udf/udfend.h
--- a/fs/udf/udfend.h	Fri Mar 15 17:51:02 2002
+++ b/fs/udf/udfend.h	Fri Mar 15 17:51:02 2002
@@ -1,59 +1,8 @@
 #ifndef __UDF_ENDIAN_H
 #define __UDF_ENDIAN_H
 
-#ifndef __KERNEL__ 
-
-#include <sys/types.h>
-
-#if __BYTE_ORDER == 0
-
-#error "__BYTE_ORDER must be defined"
-
-#elif __BYTE_ORDER == __BIG_ENDIAN
-
-#define le16_to_cpu(x) \
-	((Uint16)((((Uint16)(x) & 0x00FFU) << 8) | \
-		  (((Uint16)(x) & 0xFF00U) >> 8)))
- 
-#define le32_to_cpu(x) \
-	((Uint32)((((Uint32)(x) & 0x000000FFU) << 24) | \
-		  (((Uint32)(x) & 0x0000FF00U) <<  8) | \
-		  (((Uint32)(x) & 0x00FF0000U) >>  8) | \
-		  (((Uint32)(x) & 0xFF000000U) >> 24)))
-
-#define le64_to_cpu(x) \
-	((Uint64)((((Uint64)(x) & 0x00000000000000FFULL) << 56) | \
-		  (((Uint64)(x) & 0x000000000000FF00ULL) << 40) | \
-		  (((Uint64)(x) & 0x0000000000FF0000ULL) << 24) | \
-		  (((Uint64)(x) & 0x00000000FF000000ULL) <<  8) | \
-		  (((Uint64)(x) & 0x000000FF00000000ULL) >>  8) | \
-		  (((Uint64)(x) & 0x0000FF0000000000ULL) >> 24) | \
-		  (((Uint64)(x) & 0x00FF000000000000ULL) >> 40) | \
-		  (((Uint64)(x) & 0xFF00000000000000ULL) >> 56)))		
-
-#define cpu_to_le16(x) (le16_to_cpu(x))
-#define cpu_to_le32(x) (le32_to_cpu(x))
-#define cpu_to_le64(x) (le64_to_cpu(x))
-
-#else /* __BYTE_ORDER == __LITTLE_ENDIAN */
-
-#define le16_to_cpu(x) (x)
-#define le32_to_cpu(x) (x)
-#define le64_to_cpu(x) (x)
-#define cpu_to_le16(x) (x)
-#define cpu_to_le32(x) (x)
-#define cpu_to_le64(x) (x)
-
-#endif /* __BYTE_ORDER == 0 */
-
-#include <string.h>
-
-#else /* __KERNEL__ */
-
 #include <asm/byteorder.h>
 #include <linux/string.h>
-
-#endif /* ! __KERNEL__ */
 
 static inline lb_addr lelb_to_cpu(lb_addr in)
 {
diff -Nru a/fs/udf/udftime.c b/fs/udf/udftime.c
--- a/fs/udf/udftime.c	Fri Mar 15 17:51:03 2002
+++ b/fs/udf/udftime.c	Fri Mar 15 17:51:03 2002
@@ -32,15 +32,8 @@
  *  http://www.boulder.nist.gov/timefreq/pubs/bulletin/leapsecond.htm
  */
 
-#if defined(__linux__) && defined(__KERNEL__)
 #include <linux/types.h>
 #include <linux/kernel.h>
-#else
-#include <stdio.h>
-#include <sys/types.h>
-#include <sys/time.h>
-#endif
-
 #include "udfdecl.h"
 
 #define EPOCH_YEAR 1970
@@ -86,9 +79,7 @@
 /*2038*/ SPY(68,17,0)
 };
 
-#ifdef __KERNEL__
 extern struct timezone sys_tz;
-#endif
 
 #define SECS_PER_HOUR	(60 * 60)
 #define SECS_PER_DAY	(SECS_PER_HOUR * 24)
@@ -97,8 +88,8 @@
 udf_stamp_to_time(time_t *dest, long *dest_usec, timestamp src)
 {
 	int yday;
-	Uint8 type = src.typeAndTimezone >> 12;
-	Sint16 offset;
+	uint8_t type = src.typeAndTimezone >> 12;
+	int16_t offset;
 
 	if (type == 1)
 	{
@@ -134,13 +125,8 @@
 {
 	long int days, rem, y;
 	const unsigned short int *ip;
-	Sint16 offset;
-#ifndef __KERNEL__
-	struct timeval tv;
-	struct timezone sys_tz;
+	int16_t offset;
 
-	gettimeofday(&tv, &sys_tz);
-#endif
 	offset = -sys_tz.tz_minuteswest;
 
 	if (!dest)
diff -Nru a/fs/udf/unicode.c b/fs/udf/unicode.c
--- a/fs/udf/unicode.c	Fri Mar 15 17:51:03 2002
+++ b/fs/udf/unicode.c	Fri Mar 15 17:51:03 2002
@@ -23,20 +23,16 @@
  *	Each contributing author retains all rights to their own work.
  */
 
+#include "udfdecl.h"
 
-#ifdef __KERNEL__
 #include <linux/kernel.h>
 #include <linux/string.h>	/* for memset */
 #include <linux/nls.h>
 #include <linux/udf_fs.h>
-#include "udf_sb.h"
-#else
-#include <string.h>
-#endif
 
-#include "udfdecl.h"
+#include "udf_sb.h"
 
-int udf_ustr_to_dchars(Uint8 *dest, const struct ustr *src, int strlen)
+int udf_ustr_to_dchars(uint8_t *dest, const struct ustr *src, int strlen)
 {
 	if ( (!dest) || (!src) || (!strlen) || (src->u_len > strlen) )
 		return 0;
@@ -45,7 +41,7 @@
 	return src->u_len + 1;
 }
 
-int udf_ustr_to_char(Uint8 *dest, const struct ustr *src, int strlen)
+int udf_ustr_to_char(uint8_t *dest, const struct ustr *src, int strlen)
 {
 	if ( (!dest) || (!src) || (!strlen) || (src->u_len >= strlen) )
 		return 0;
@@ -64,7 +60,7 @@
 		return 0;
 }
 
-int udf_dchars_to_ustr(struct ustr *dest, const Uint8 *src, int strlen)
+int udf_dchars_to_ustr(struct ustr *dest, const uint8_t *src, int strlen)
 {
 	if ( (!dest) || (!src) || (!strlen) || (strlen > UDF_NAME_LEN) )
 		return 0;
@@ -75,7 +71,7 @@
 	return strlen-1;
 }
 
-int udf_char_to_ustr(struct ustr *dest, const Uint8 *src, int strlen)
+int udf_char_to_ustr(struct ustr *dest, const uint8_t *src, int strlen)
 {
 	if ( (!dest) || (!src) || (!strlen) || (strlen >= UDF_NAME_LEN) )
 		return 0;
@@ -152,9 +148,9 @@
  */
 int udf_CS0toUTF8(struct ustr *utf_o, struct ustr *ocu_i)
 {
-	Uint8 *ocu;
-	Uint32 c;
-	Uint8 cmp_id, ocu_len;
+	uint8_t *ocu;
+	uint32_t c;
+	uint8_t cmp_id, ocu_len;
 	int i;
 
 	ocu = ocu_i->u_name;
@@ -173,9 +169,7 @@
 
 	if ((cmp_id != 8) && (cmp_id != 16))
 	{
-#ifdef __KERNEL__
 		printk(KERN_ERR "udf: unknown compression code (%d) stri=%s\n", cmp_id, ocu_i->u_name);
-#endif
 		return 0;
 	}
 
@@ -189,22 +183,20 @@
 
 		/* Compress Unicode to UTF-8 */
 		if (c < 0x80U)
-			utf_o->u_name[utf_o->u_len++] = (Uint8)c;
+			utf_o->u_name[utf_o->u_len++] = (uint8_t)c;
 		else if (c < 0x800U)
 		{
-			utf_o->u_name[utf_o->u_len++] = (Uint8)(0xc0 | (c >> 6));
-			utf_o->u_name[utf_o->u_len++] = (Uint8)(0x80 | (c & 0x3f));
+			utf_o->u_name[utf_o->u_len++] = (uint8_t)(0xc0 | (c >> 6));
+			utf_o->u_name[utf_o->u_len++] = (uint8_t)(0x80 | (c & 0x3f));
 		}
 		else
 		{
-			utf_o->u_name[utf_o->u_len++] = (Uint8)(0xe0 | (c >> 12));
-			utf_o->u_name[utf_o->u_len++] = (Uint8)(0x80 | ((c >> 6) & 0x3f));
-			utf_o->u_name[utf_o->u_len++] = (Uint8)(0x80 | (c & 0x3f));
+			utf_o->u_name[utf_o->u_len++] = (uint8_t)(0xe0 | (c >> 12));
+			utf_o->u_name[utf_o->u_len++] = (uint8_t)(0x80 | ((c >> 6) & 0x3f));
+			utf_o->u_name[utf_o->u_len++] = (uint8_t)(0x80 | (c & 0x3f));
 		}
 	}
 	utf_o->u_cmpID=8;
-	utf_o->u_hash=0L;
-	utf_o->padding=0;
 
 	return utf_o->u_len;
 }
@@ -247,7 +239,7 @@
 	utf_cnt = 0U;
 	for (i = 0U; i < utf->u_len; i++)
 	{
-		c = (Uint8)utf->u_name[i];
+		c = (uint8_t)utf->u_name[i];
 
 		/* Complete a multi-byte UTF-8 character */
 		if (utf_cnt)
@@ -301,7 +293,7 @@
 			if ( 0xffU == max_val )
 			{
 				max_val = 0xffffU;
-				ocu[0] = (Uint8)0x10U;
+				ocu[0] = (uint8_t)0x10U;
 				goto try_again;
 			}
 			goto error_out;
@@ -309,31 +301,28 @@
 
 		if (max_val == 0xffffU)
 		{
-			ocu[++u_len] = (Uint8)(utf_char >> 8);
+			ocu[++u_len] = (uint8_t)(utf_char >> 8);
 		}
-		ocu[++u_len] = (Uint8)(utf_char & 0xffU);
+		ocu[++u_len] = (uint8_t)(utf_char & 0xffU);
 	}
 
 
 	if (utf_cnt)
 	{
 error_out:
-#ifdef __KERNEL__
 		printk(KERN_ERR "udf: bad UTF-8 character\n");
-#endif
 		return 0;
 	}
 
-	ocu[length - 1] = (Uint8)u_len + 1;
+	ocu[length - 1] = (uint8_t)u_len + 1;
 	return u_len + 1;
 }
 
-#ifdef __KERNEL__
 int udf_CS0toNLS(struct nls_table *nls, struct ustr *utf_o, struct ustr *ocu_i)
 {
-	Uint8 *ocu;
-	Uint32 c;
-	Uint8 cmp_id, ocu_len;
+	uint8_t *ocu;
+	uint32_t c;
+	uint8_t cmp_id, ocu_len;
 	int i;
 
 	ocu = ocu_i->u_name;
@@ -367,8 +356,6 @@
 			UDF_NAME_LEN - utf_o->u_len);
 	}
 	utf_o->u_cmpID=8;
-	utf_o->u_hash=0L;
-	utf_o->padding=0;
 
 	return utf_o->u_len;
 }
@@ -376,7 +363,7 @@
 int udf_NLStoCS0(struct nls_table *nls, dstring *ocu, struct ustr *uni, int length)
 {
 	unsigned len, i, max_val;
-	Uint16 uni_char;
+	uint16_t uni_char;
 	int uni_cnt;
 	int u_len = 0;
 
@@ -394,23 +381,23 @@
 		if (len == 2 && max_val == 0xff)
 		{
 			max_val = 0xffffU;
-			ocu[0] = (Uint8)0x10U;
+			ocu[0] = (uint8_t)0x10U;
 			goto try_again;
 		}
 		
 		if (max_val == 0xffffU)
 		{
-			ocu[++u_len] = (Uint8)(uni_char >> 8);
+			ocu[++u_len] = (uint8_t)(uni_char >> 8);
 			i++;
 		}
-		ocu[++u_len] = (Uint8)(uni_char & 0xffU);
+		ocu[++u_len] = (uint8_t)(uni_char & 0xffU);
 	}
 
-	ocu[length - 1] = (Uint8)u_len + 1;
+	ocu[length - 1] = (uint8_t)u_len + 1;
 	return u_len + 1;
 }
 
-int udf_get_filename(struct super_block *sb, Uint8 *sname, Uint8 *dname, int flen)
+int udf_get_filename(struct super_block *sb, uint8_t *sname, uint8_t *dname, int flen)
 {
 	struct ustr filename, unifilename;
 	int len;
@@ -446,20 +433,19 @@
 	}
 	return 0;
 }
-#endif
 
 #define ILLEGAL_CHAR_MARK	'_'
 #define EXT_MARK			'.'
 #define CRC_MARK			'#'
 #define EXT_SIZE			5
 
-int udf_translate_to_linux(Uint8 *newName, Uint8 *udfName, int udfLen, Uint8 *fidName, int fidNameLen)
+int udf_translate_to_linux(uint8_t *newName, uint8_t *udfName, int udfLen, uint8_t *fidName, int fidNameLen)
 {
 	int index, newIndex = 0, needsCRC = 0;	
 	int extIndex = 0, newExtIndex = 0, hasExt = 0;
 	unsigned short valueCRC;
-	Uint8 curr;
-	const Uint8 hexChar[] = "0123456789ABCDEF";
+	uint8_t curr;
+	const uint8_t hexChar[] = "0123456789ABCDEF";
 
 	if (udfName[0] == '.' && (udfLen == 1 ||
 		(udfLen == 2 && udfName[1] == '.')))
@@ -500,7 +486,7 @@
 	}
 	if (needsCRC)
 	{
-		Uint8 ext[EXT_SIZE];
+		uint8_t ext[EXT_SIZE];
 		int localExtIndex = 0;
 
 		if (hasExt)
diff -Nru a/fs/ufs/super.c b/fs/ufs/super.c
--- a/fs/ufs/super.c	Fri Mar 15 17:51:00 2002
+++ b/fs/ufs/super.c	Fri Mar 15 17:51:00 2002
@@ -1018,6 +1018,7 @@
 	owner:		THIS_MODULE,
 	name:		"ufs",
 	get_sb:		ufs_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/fs/vfat/namei.c b/fs/vfat/namei.c
--- a/fs/vfat/namei.c	Fri Mar 15 17:51:01 2002
+++ b/fs/vfat/namei.c	Fri Mar 15 17:51:01 2002
@@ -1285,25 +1285,25 @@
 
 int vfat_fill_super(struct super_block *sb, void *data, int silent)
 {
-	struct super_block *res;
+	int res;
+	struct msdos_sb_info *sbi;
   
-	MSDOS_SB(sb)->options.isvfat = 1;
-	res = fat_read_super(sb, data, silent, &vfat_dir_inode_operations);
-	if (IS_ERR(res))
-		return PTR_ERR(res);
-	if (res == NULL) {
-		if (!silent)
+	res = fat_fill_super(sb, data, silent, &vfat_dir_inode_operations, 1);
+	if (res) {
+		if (res == -EINVAL && !silent)
 			printk(KERN_INFO "VFS: Can't find a valid"
 			       " VFAT filesystem on dev %s.\n", sb->s_id);
-		return -EINVAL;
+		return res;
 	}
 
-	if (parse_options((char *) data, &(MSDOS_SB(sb)->options))) {
-		MSDOS_SB(sb)->options.dotsOK = 0;
-		if (MSDOS_SB(sb)->options.posixfs) {
-			MSDOS_SB(sb)->options.name_check = 's';
+	sbi = MSDOS_SB(sb);
+
+	if (parse_options((char *) data, &(sbi->options))) {
+		sbi->options.dotsOK = 0;
+		if (sbi->options.posixfs) {
+			sbi->options.name_check = 's';
 		}
-		if (MSDOS_SB(sb)->options.name_check != 's') {
+		if (sbi->options.name_check != 's') {
 			sb->s_root->d_op = &vfat_dentry_ops[0];
 		} else {
 			sb->s_root->d_op = &vfat_dentry_ops[2];
diff -Nru a/fs/vfat/vfatfs_syms.c b/fs/vfat/vfatfs_syms.c
--- a/fs/vfat/vfatfs_syms.c	Fri Mar 15 17:51:03 2002
+++ b/fs/vfat/vfatfs_syms.c	Fri Mar 15 17:51:03 2002
@@ -21,6 +21,7 @@
 	owner:		THIS_MODULE,
 	name:		"vfat",
 	get_sb:		vfat_get_sb,
+	kill_sb:	kill_block_super,
 	fs_flags:	FS_REQUIRES_DEV,
 };
 
diff -Nru a/include/asm-arm/arch-ebsa110/system.h b/include/asm-arm/arch-ebsa110/system.h
--- a/include/asm-arm/arch-ebsa110/system.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/arch-ebsa110/system.h	Fri Mar 15 17:51:01 2002
@@ -17,29 +17,34 @@
  * will stop our MCLK signal (which provides the clock for the glue
  * logic, and therefore the timer interrupt).
  *
- * Instead, we spin, waiting for either hlt_counter or need_resched()
- * to be set.  If we have been spinning for 2cs, then we drop the
- * core clock down to the memory clock.
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
  */
 static void arch_idle(void)
 {
-	unsigned long start_idle;
+	const char *irq_stat = (char *)0xff000000;
+	long flags;
 
-	start_idle = jiffies;
+	if (!hlt_counter)
+		return;
 
 	do {
-		if (need_resched() || hlt_counter)
-			goto slow_out;
-	} while (time_before(jiffies, start_idle + HZ/50));
-
-	cpu_do_idle(IDLE_CLOCK_SLOW);
-
-	while (!need_resched() && !hlt_counter) {
-		/* do nothing slowly */
-	}
-
-	cpu_do_idle(IDLE_CLOCK_FAST);
-slow_out:
+		/* disable interrupts */
+		cli();
+		/* check need_resched here to avoid races */
+		if (need_resched()) {
+			sti();
+			return;
+		}
+		/* disable clock switching */
+		asm volatile ("mcr%? p15, 0, ip, c15, c2, 2");
+		/* wait for an interrupt to occur */
+		while (!*irq_stat);
+		/* enable clock switching */
+		asm volatile ("mcr%? p15, 0, ip, c15, c1, 2");
+		/* allow the interrupt to happen */
+		sti();
+	} while (!need_resched());
 }
 
 #define arch_reset(mode)	cpu_reset(0x80000000)
diff -Nru a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
--- a/include/asm-arm/cpu-multi32.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/cpu-multi32.h	Fri Mar 15 17:51:01 2002
@@ -107,18 +107,12 @@
 		 */
 		void (*set_pte)(pte_t *ptep, pte_t pte);
 	} pgtable;
-
-	struct {	/* other */
-		void (*clear_user_page)(void *page, unsigned long u_addr);
-		void (*copy_user_page)(void *to, void *from, unsigned long u_addr);
-	} misc;
 } processor;
 
 extern const struct processor arm6_processor_functions;
 extern const struct processor arm7_processor_functions;
 extern const struct processor sa110_processor_functions;
 
-#define cpu_data_abort(pc)			processor._data_abort(pc)
 #define cpu_check_bugs()			processor._check_bugs()
 #define cpu_proc_init()				processor._proc_init()
 #define cpu_proc_fin()				processor._proc_fin()
@@ -140,9 +134,6 @@
 #define cpu_set_pgd(pgd)			processor.pgtable.set_pgd(pgd)
 #define cpu_set_pmd(pmdp, pmd)			processor.pgtable.set_pmd(pmdp, pmd)
 #define cpu_set_pte(ptep, pte)			processor.pgtable.set_pte(ptep, pte)
-
-#define cpu_copy_user_page(to,from,uaddr)	processor.misc.copy_user_page(to,from,uaddr)
-#define cpu_clear_user_page(page,uaddr)		processor.misc.clear_user_page(page,uaddr)
 
 #define cpu_switch_mm(pgd,tsk)			cpu_set_pgd(__virt_to_phys((unsigned long)(pgd)))
 
diff -Nru a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h
--- a/include/asm-arm/cpu-single.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/cpu-single.h	Fri Mar 15 17:51:01 2002
@@ -22,7 +22,6 @@
  * function pointers for this lot.  Otherwise, we can optimise the
  * table away.
  */
-#define cpu_data_abort			__cpu_fn(CPU_ABRT,_abort)
 #define cpu_check_bugs			__cpu_fn(CPU_NAME,_check_bugs)
 #define cpu_proc_init			__cpu_fn(CPU_NAME,_proc_init)
 #define cpu_proc_fin			__cpu_fn(CPU_NAME,_proc_fin)
@@ -40,8 +39,6 @@
 #define cpu_set_pgd			__cpu_fn(CPU_NAME,_set_pgd)
 #define cpu_set_pmd			__cpu_fn(CPU_NAME,_set_pmd)
 #define cpu_set_pte			__cpu_fn(CPU_NAME,_set_pte)
-#define cpu_copy_user_page		__cpu_fn(MMU_ARCH,_copy_user_page)
-#define cpu_clear_user_page		__cpu_fn(MMU_ARCH,_clear_user_page)
 
 #ifndef __ASSEMBLY__
 
@@ -73,9 +70,6 @@
 extern void cpu_set_pgd(unsigned long pgd_phys);
 extern void cpu_set_pmd(pmd_t *pmdp, pmd_t pmd);
 extern void cpu_set_pte(pte_t *ptep, pte_t pte);
-
-extern void cpu_copy_user_page(void *to, void *from, unsigned long u_addr);
-extern void cpu_clear_user_page(void *page, unsigned long u_addr);
 
 extern volatile void cpu_reset(unsigned long addr);
 
diff -Nru a/include/asm-arm/glue.h b/include/asm-arm/glue.h
--- a/include/asm-arm/glue.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/glue.h	Fri Mar 15 17:51:01 2002
@@ -24,14 +24,21 @@
 #endif
 #define __glue(name,fn)		____glue(name,fn)
 
-/*
- * Select MMU TLB handling.
- */
+
 
 /*
- * ARMv3 MMU
+ *	MMU TLB Model
+ *	=============
+ *
+ *	We have the following to choose from:
+ *	  v3    - ARMv3
+ *	  v4    - ARMv4 without write buffer
+ *	  v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
+ *	  v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  */
 #undef _TLB
+#undef MULTI_TLB
+
 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
 # ifdef _TLB
 #  define MULTI_TLB 1
@@ -40,9 +47,6 @@
 # endif
 #endif
 
-/*
- * ARMv4 MMU without write buffer
- */
 #if defined(CONFIG_CPU_ARM720T)
 # ifdef _TLB
 #  define MULTI_TLB 1
@@ -51,9 +55,6 @@
 # endif
 #endif
 
-/*
- * ARMv4 MMU with write buffer, with invalidate I TLB entry instruction
- */
 #if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
     defined(CONFIG_CPU_ARM926T) || defined(CONFIG_CPU_ARM1020) || \
     defined(CONFIG_CPU_XSCALE)
@@ -64,15 +65,142 @@
 # endif
 #endif
 
-/*
- * ARMv4 MMU with write buffer, without invalidate I TLB entry instruction
- */
 #if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
 # ifdef _TLB
 #  define MULTI_TLB 1
 # else
 #  define _TLB v4wb
 # endif
+#endif
+
+#ifndef _TLB
+#error Unknown TLB model
+#endif
+
+
+
+/*
+ *	Data Abort Model
+ *	================
+ *
+ *	We have the following to choose from:
+ *	  arm6          - ARM6 style
+ *	  arm7		- ARM7 style
+ *	  v4_early	- ARMv4 without Thumb early abort handler
+ *	  v4t_late	- ARMv4 with Thumb late abort handler
+ *	  v4t_early	- ARMv4 with Thumb early abort handler
+ *	  v5ej_early	- ARMv5 with Thumb and Java early abort handler
+ */
+#undef CPU_ABORT_HANDLER
+#undef MULTI_ABORT
+
+#if defined(CONFIG_CPU_ARM610)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER cpu_arm6_data_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM710)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER cpu_arm7_data_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM720T)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v4t_late_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v4_early_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
+    defined(CONFIG_CPU_ARM1020) || defined(CONFIG_CPU_XSCALE)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v4t_early_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM926T)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v5ej_early_abort
+# endif
+#endif
+
+#ifndef CPU_ABORT_HANDLER
+#error Unknown data abort handler type
+#endif
+
+
+/*
+ *	User Space Model
+ *	================
+ *
+ *	This section selects the correct set of functions for dealing with
+ *	page-based copying and clearing for user space for the particular
+ *	processor(s) we're building for.
+ *
+ *	We have the following to choose from:
+ *	  v3		- ARMv3
+ *	  v4		- ARMv4 without minicache
+ *	  v4_mc		- ARMv4 with minicache
+ *	  v5te_mc	- ARMv5TE with minicache
+ */
+#undef _USER
+#undef MULTI_USER
+
+#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v3
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM720T) || defined(CONFIG_CPU_ARM920T) || \
+    defined(CONFIG_CPU_ARM922T) || defined(CONFIG_CPU_ARM926T) || \
+    defined(CONFIG_CPU_SA110)   || defined(CONFIG_CPU_ARM1020)
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v4
+# endif
+#endif
+
+#if defined(CONFIG_CPU_SA1100)
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v4_mc
+# endif
+#endif
+
+#if defined(CONFIG_CPU_XSCALE)
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v5te_mc
+# endif
+#endif
+
+#ifndef _USER
+#error Unknown user operations model
 #endif
 
 #endif
diff -Nru a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
--- a/include/asm-arm/mach/pci.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-arm/mach/pci.h	Fri Mar 15 17:51:03 2002
@@ -19,12 +19,6 @@
 	/* Setup bus resources */
 	void		(*setup_resources)(struct resource **);
 
-	/*
-	 * This is the offset of PCI memory base registers
-	 * to physical memory.
-	 */
-	unsigned long	mem_offset;
-
 	/* IRQ swizzle */
 	u8		(*swizzle)(struct pci_dev *dev, u8 *pin);
 
diff -Nru a/include/asm-arm/page.h b/include/asm-arm/page.h
--- a/include/asm-arm/page.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/page.h	Fri Mar 15 17:51:01 2002
@@ -1,50 +1,68 @@
 #ifndef _ASMARM_PAGE_H
 #define _ASMARM_PAGE_H
 
-#include <asm/proc/page.h>
-
-#define PAGE_SIZE	(1UL << PAGE_SHIFT)
-#define PAGE_MASK	(~(PAGE_SIZE-1))
+#include <linux/config.h>
 
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
-#define STRICT_MM_TYPECHECKS
+#include <asm/glue.h>
 
-#define clear_page(page)	memzero((void *)(page), PAGE_SIZE)
-extern void copy_page(void *to, void *from);
+struct cpu_user_fns {
+	void (*cpu_clear_user_page)(void *p, unsigned long user);
+	void (*cpu_copy_user_page)(void *to, const void *from,
+				   unsigned long user);
+};
+
+#ifdef MULTI_USER
+extern struct cpu_user_fns cpu_user;
+
+#define __cpu_clear_user_page	cpu_user.cpu_clear_user_page
+#define __cpu_copy_user_page	cpu_user.cpu_copy_user_page
+
+#else
+
+#define __cpu_clear_user_page	__glue(_USER,_clear_user_page)
+#define __cpu_copy_user_page	__glue(_USER,_copy_user_page)
+
+extern void __cpu_clear_user_page(void *p, unsigned long user);
+extern void __cpu_copy_user_page(void *to, const void *from,
+				 unsigned long user);
+#endif
 
 #define clear_user_page(addr,vaddr)			\
 	do {						\
 		preempt_disable();			\
-		cpu_clear_user_page(addr, vaddr);	\
+		__cpu_clear_user_page(addr, vaddr);	\
 		preempt_enable();			\
 	} while (0)
 
 #define copy_user_page(to,from,vaddr)			\
 	do {						\
 		preempt_disable();			\
-		cpu_copy_user_page(to, from, vaddr);	\
+		__cpu_copy_user_page(to, from, vaddr);	\
 		preempt_enable();			\
 	} while (0)
 
+#define clear_page(page)	memzero((void *)(page), PAGE_SIZE)
+extern void copy_page(void *to, void *from);
+
+#undef STRICT_MM_TYPECHECKS
+
 #ifdef STRICT_MM_TYPECHECKS
 /*
  * These are used to make use of C type-checking..
  */
 typedef struct { unsigned long pte; } pte_t;
 typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
 typedef struct { unsigned long pgprot; } pgprot_t;
 
 #define pte_val(x)      ((x).pte)
 #define pmd_val(x)      ((x).pmd)
-#define pgd_val(x)      ((x).pgd)
 #define pgprot_val(x)   ((x).pgprot)
 
 #define __pte(x)        ((pte_t) { (x) } )
 #define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
 #define __pgprot(x)     ((pgprot_t) { (x) } )
 
 #else
@@ -53,25 +71,29 @@
  */
 typedef unsigned long pte_t;
 typedef unsigned long pmd_t;
-typedef unsigned long pgd_t;
 typedef unsigned long pgprot_t;
 
 #define pte_val(x)      (x)
 #define pmd_val(x)      (x)
-#define pgd_val(x)      (x)
 #define pgprot_val(x)   (x)
 
 #define __pte(x)        (x)
 #define __pmd(x)        (x)
-#define __pgd(x)        (x)
 #define __pgprot(x)     (x)
 
-#endif
+#endif /* STRICT_MM_TYPECHECKS */
 #endif /* !__ASSEMBLY__ */
+#endif /* __KERNEL__ */
+
+#include <asm/proc/page.h>
+
+#define PAGE_SIZE		(1UL << PAGE_SHIFT)
+#define PAGE_MASK		(~(PAGE_SIZE-1))
 
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)	(((addr)+PAGE_SIZE-1)&PAGE_MASK)
 
+#ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
 #ifdef CONFIG_DEBUG_BUGVERBOSE
@@ -105,7 +127,6 @@
 
 #endif /* !__ASSEMBLY__ */
 
-#include <linux/config.h>
 #include <asm/arch/memory.h>
 
 #define __pa(x)			__virt_to_phys((unsigned long)(x))
@@ -120,6 +141,6 @@
 #define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
 				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
-#endif
+#endif /* __KERNEL__ */
 
 #endif
diff -Nru a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
--- a/include/asm-arm/pgtable.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-arm/pgtable.h	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/include/asm-arm/pgtable.h
  *
- *  Copyright (C) 2000-2001 Russell King
+ *  Copyright (C) 2000-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -19,7 +19,11 @@
  * PGDIR_SHIFT determines what a third-level page table entry can map
  */
 #define PMD_SHIFT		20
+#ifdef CONFIG_CPU_32
+#define PGDIR_SHIFT		21
+#else
 #define PGDIR_SHIFT		20
+#endif
 
 #define LIBRARY_TEXT_START	0x0c000000
 
@@ -93,7 +97,6 @@
 
 #define pmd_none(pmd)		(!pmd_val(pmd))
 #define pmd_present(pmd)	(pmd_val(pmd))
-#define pmd_clear(pmdp)		set_pmd(pmdp, __pmd(0))
 
 /*
  * Permanent address of a page. We never have highmem, so this is trivial.
@@ -106,18 +109,10 @@
  */
 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 {
-	pte_t pte;
-	pte_val(pte) = physpage | pgprot_val(pgprot);
-	return pte;
+	return __pte(physpage | pgprot_val(pgprot));
 }
 
-#define mk_pte(page,pgprot)				\
-({							\
-	pte_t __pte;					\
-	pte_val(__pte) = __pa(page_address(page)) +	\
-			   pgprot_val(pgprot);		\
-	__pte;						\
-})
+#define mk_pte(page,pgprot)	mk_pte_phys(__pa(page_address(page)), pgprot)
 
 /*
  * The "pgd_xxx()" functions here are trivial for a folded two-level
@@ -127,7 +122,7 @@
 #define pgd_none(pgd)		(0)
 #define pgd_bad(pgd)		(0)
 #define pgd_present(pgd)	(1)
-#define pgd_clear(pgdp)
+#define pgd_clear(pgdp)		do { } while (0)
 
 #define page_pte_prot(page,prot)	mk_pte(page, prot)
 #define page_pte(page)		mk_pte(page, __pgprot(0))
@@ -147,15 +142,6 @@
 /* Find an entry in the third-level page table.. */
 #define __pte_index(addr)	(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 
-#define pmd_page(dir)		((struct page *)__pmd_page(dir))
-
-#define __pte_offset(dir, addr)	((pte_t *)__pmd_page(*(dir)) + __pte_index(addr))
-#define pte_offset_kernel	__pte_offset
-#define pte_offset_map		__pte_offset
-#define pte_offset_map_nested	__pte_offset
-#define pte_unmap(pte)		do { } while (0)
-#define pte_unmap_nested(pte)	do { } while (0)
-
 #include <asm/proc/pgtable.h>
 
 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
@@ -181,8 +167,6 @@
 #define kern_addr_valid(addr)	(1)
 
 #include <asm-generic/pgtable.h>
-
-extern void pgtable_cache_init(void);
 
 /*
  * remap a physical address `phys' of size `size' with page protection `prot'
diff -Nru a/include/asm-arm/proc-armo/page.h b/include/asm-arm/proc-armo/page.h
--- a/include/asm-arm/proc-armo/page.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-arm/proc-armo/page.h	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/include/asm-arm/proc-armo/page.h
  *
- *  Copyright (C) 1995, 1996 Russell King
+ *  Copyright (C) 1995-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -20,5 +20,21 @@
 #endif
 
 #define EXEC_PAGESIZE   32768
+
+#ifndef __ASSEMBLY__
+#ifdef STRICT_MM_TYPECHECKS
+
+typedef struct { unsigned long pgd; } pgd_t;
+
+#define pgd_val(x)	((x).pgd)
+
+#else
+
+typedef unsigned long pgd_t;
+
+#define pgd_val(x)	(x)
+
+#endif
+#endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_PROC_PAGE_H */
diff -Nru a/include/asm-arm/proc-armo/pgalloc.h b/include/asm-arm/proc-armo/pgalloc.h
--- a/include/asm-arm/proc-armo/pgalloc.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-arm/proc-armo/pgalloc.h	Fri Mar 15 17:51:02 2002
@@ -1,32 +1,22 @@
 /*
  *  linux/include/asm-arm/proc-armo/pgalloc.h
  *
- *  Copyright (C) 2001 Russell King
+ *  Copyright (C) 2001-2002 Russell King
  *
  * Page table allocation/freeing primitives for 26-bit ARM processors.
  */
 
-/* unfortunately, this includes linux/mm.h and the rest of the universe. */
 #include <linux/slab.h>
 
 extern kmem_cache_t *pte_cache;
 
-/*
- * Allocate one PTE table.
- *
- * Note that we keep the processor copy of the PTE entries separate
- * from the Linux copy.  The processor copies are offset by -PTRS_PER_PTE
- * words from the Linux copy.
- */
-static inline pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address)
+static inline pte_t *
+pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
 {
 	return kmem_cache_alloc(pte_cache, GFP_KERNEL);
 }
 
-/*
- * Free one PTE table.
- */
-static inline void pte_free_slow(pte_t *pte)
+static inline void pte_free_kernel(pte_t *pte)
 {
 	if (pte)
 		kmem_cache_free(pte_cache, pte);
@@ -39,9 +29,16 @@
  * If 'mm' is the init tasks mm, then we are doing a vmalloc, and we
  * need to set stuff up correctly for it.
  */
-#define pmd_populate(mm,pmdp,pte)				\
-	do {							\
-		set_pmd(pmdp, __mk_pmd(pte, _PAGE_TABLE));	\
-	} while (0)
-
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
+{
+	set_pmd(pmdp, __mk_pmd(ptep, _PAGE_TABLE));
+}
 
+/*
+ * We use the old 2.5.5-rmk1 hack for this.
+ * This is not truely correct, but should be functional.
+ */
+#define pte_alloc_one(mm,addr)	((struct page *)pte_alloc_one_kernel(mm,addr))
+#define pte_free(pte)		pte_free_kernel((pte_t *)pte)
+#define pmd_populate(mm,pmdp,ptep) pmd_populate_kernel(mm,pmdp,(pte_t *)ptep)
diff -Nru a/include/asm-arm/proc-armo/pgtable.h b/include/asm-arm/proc-armo/pgtable.h
--- a/include/asm-arm/proc-armo/pgtable.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-arm/proc-armo/pgtable.h	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/include/asm-arm/proc-armo/pgtable.h
  *
- *  Copyright (C) 1995-2001 Russell King
+ *  Copyright (C) 1995-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -32,6 +32,7 @@
 
 #define pmd_bad(pmd)		((pmd_val(pmd) & 0xfc000002))
 #define set_pmd(pmdp,pmd)	((*(pmdp)) = (pmd))
+#define pmd_clear(pmdp)		set_pmd(pmdp, __pmd(0))
 
 static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
 {
@@ -48,6 +49,12 @@
 	return __phys_to_virt(pmd_val(pmd) & ~_PAGE_TABLE);
 }
 
+#define pte_offset_kernel(dir,addr)	(pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_offset_map(dir,addr)	(pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_offset_map_nested(dir,addr)	(pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_unmap(pte)			do { } while (0)
+#define pte_unmap_nested(pte)		do { } while (0)
+
 #define set_pte(pteptr, pteval)	((*(pteptr)) = (pteval))
 
 #define _PAGE_PRESENT	0x01
@@ -89,11 +96,11 @@
 static inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) &= ~_PAGE_CLEAN;    return pte; }
 static inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) &= ~_PAGE_OLD;      return pte; }
 
-#define pte_alloc_kernel        pte_alloc
-
 /*
  * We don't store cache state bits in the page table here.
  */
 #define pgprot_noncached(prot)	(prot)
+
+extern void pgtable_cache_init(void);
 
 #endif /* __ASM_PROC_PGTABLE_H */
diff -Nru a/include/asm-arm/proc-armv/cache.h b/include/asm-arm/proc-armv/cache.h
--- a/include/asm-arm/proc-armv/cache.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-arm/proc-armv/cache.h	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/include/asm-arm/proc-armv/cache.h
  *
- *  Copyright (C) 1999-2001 Russell King
+ *  Copyright (C) 1999-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -134,7 +134,8 @@
 #define clean_dcache_range(_s,_e)	cpu_dcache_clean_range((_s),(_e))
 #define flush_dcache_range(_s,_e)	cpu_cache_clean_invalidate_range((_s),(_e),0)
 
-#define mapping_mapped(map)	((map)->i_mmap || (map)->i_mmap_shared)
+#define mapping_mapped(map)	(!list_empty(&(map)->i_mmap) || \
+				 !list_empty(&(map)->i_mmap_shared))
 
 /*
  * flush_dcache_page is used when the kernel has written to the page
@@ -204,7 +205,7 @@
  *	TLB Management
  *	==============
  *
- *	The arch/arm/mm/tlb-*.S files implement this methods.
+ *	The arch/arm/mm/tlb-*.S files implement these methods.
  *
  *	The TLB specific code is expected to perform whatever tests it
  *	needs to determine if it should invalidate the TLB for each
diff -Nru a/include/asm-arm/proc-armv/page.h b/include/asm-arm/proc-armv/page.h
--- a/include/asm-arm/proc-armv/page.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/proc-armv/page.h	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/include/asm-arm/proc-armv/page.h
  *
- *  Copyright (C) 1995, 1996 Russell King
+ *  Copyright (C) 1995-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -14,5 +14,24 @@
 #define PAGE_SHIFT	12
 
 #define EXEC_PAGESIZE   4096
+
+#ifndef __ASSEMBLY__
+#ifdef STRICT_MM_TYPECHECKS
+
+typedef struct {
+	unsigned long pgd0;
+	unsigned long pgd1;
+} pgd_t;
+
+#define pgd_val(x)	((x).pgd0)
+
+#else
+
+typedef unsigned long pgd_t[2];
+
+#define pgd_val(x)	((x)[0])
+
+#endif
+#endif /* __ASSEMBLY__ */
 
 #endif /* __ASM_PROC_PAGE_H */
diff -Nru a/include/asm-arm/proc-armv/pgalloc.h b/include/asm-arm/proc-armv/pgalloc.h
--- a/include/asm-arm/proc-armv/pgalloc.h	Fri Mar 15 17:51:00 2002
+++ b/include/asm-arm/proc-armv/pgalloc.h	Fri Mar 15 17:51:00 2002
@@ -1,43 +1,72 @@
 /*
  *  linux/include/asm-arm/proc-armv/pgalloc.h
  *
- *  Copyright (C) 2001 Russell King
+ *  Copyright (C) 2001-2002 Russell King
  *
  * Page table allocation/freeing primitives for 32-bit ARM processors.
  */
-
-/* unfortunately, this includes linux/mm.h and the rest of the universe. */
-#include <linux/slab.h>
-
-extern kmem_cache_t *pte_cache;
+#include "pgtable.h"
 
 /*
  * Allocate one PTE table.
  *
- * Note that we keep the processor copy of the PTE entries separate
- * from the Linux copy.  The processor copies are offset by -PTRS_PER_PTE
- * words from the Linux copy.
+ * This actually allocates two hardware PTE tables, but we wrap this up
+ * into one table thus:
+ *
+ *  +------------+
+ *  |  h/w pt 0  |
+ *  +------------+
+ *  |  h/w pt 1  |
+ *  +------------+
+ *  | Linux pt 0 |
+ *  +------------+
+ *  | Linux pt 1 |
+ *  +------------+
  */
 static inline pte_t *
 pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
 {
+	int count = 0;
 	pte_t *pte;
 
-	pte = kmem_cache_alloc(pte_cache, GFP_KERNEL);
-	if (pte)
+	do {
+		pte = (pte_t *)__get_free_page(GFP_KERNEL);
+		if (!pte) {
+			current->state = TASK_UNINTERRUPTIBLE;
+			schedule_timeout(HZ);
+		}
+	} while (!pte && (count++ < 10));
+
+	if (pte) {
+		clear_page(pte);
+		clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE);
 		pte += PTRS_PER_PTE;
+	}
+
 	return pte;
 }
 
 static inline struct page *
 pte_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-	pte_t *pte;
+	struct page *pte;
+	int count = 0;
 
-	pte = kmem_cache_alloc(pte_cache, GFP_KERNEL);
-	if (pte)
-		pte += PTRS_PER_PTE;
-	return (struct page *)pte;
+	do {
+		pte = alloc_pages(GFP_KERNEL, 0);
+		if (!pte) {
+			current->state = TASK_UNINTERRUPTIBLE;
+			schedule_timeout(HZ);
+		}
+	} while (!pte && (count++ < 10));
+
+	if (pte) {
+		void *page = page_address(pte);
+		clear_page(page);
+		clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+	}
+
+	return pte;
 }
 
 /*
@@ -47,34 +76,49 @@
 {
 	if (pte) {
 		pte -= PTRS_PER_PTE;
-		kmem_cache_free(pte_cache, pte);
+		free_page((unsigned long)pte);
 	}
 }
 
 static inline void pte_free(struct page *pte)
 {
-	pte_t *_pte = (pte_t *)pte;
-	if (pte) {
-		_pte -= PTRS_PER_PTE;
-		kmem_cache_free(pte_cache, _pte);
-	}
+	__free_page(pte);
 }
 
 /*
  * Populate the pmdp entry with a pointer to the pte.  This pmd is part
  * of the mm address space.
  *
- * If 'mm' is the init tasks mm, then we are doing a vmalloc, and we
- * need to set stuff up correctly for it.
+ * Ensure that we always set both PMD entries.
  */
-#define pmd_populate_kernel(mm,pmdp,pte)			\
-	do {							\
-		BUG_ON(mm != &init_mm);				\
-		set_pmd(pmdp, __mk_pmd(pte, _PAGE_KERNEL_TABLE));\
-	} while (0)
-
-#define pmd_populate(mm,pmdp,pte)				\
-	do {							\
-		BUG_ON(mm == &init_mm);				\
-		set_pmd(pmdp, __mk_pmd(pte, _PAGE_USER_TABLE));	\
-	} while (0)
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
+{
+	unsigned long pte_ptr = (unsigned long)ptep;
+	pmd_t pmd;
+
+	BUG_ON(mm != &init_mm);
+
+	/*
+	 * The pmd must be loaded with the physical
+	 * address of the PTE table
+	 */
+	pte_ptr -= PTRS_PER_PTE * sizeof(void *);
+	pmd_val(pmd) = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
+	set_pmd(pmdp, pmd);
+	pmd_val(pmd) += 256 * sizeof(pte_t);
+	set_pmd(pmdp + 1, pmd);
+}
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
+{
+	pmd_t pmd;
+
+	BUG_ON(mm == &init_mm);
+
+	pmd_val(pmd) = __pa(page_address(ptep)) | _PAGE_USER_TABLE;
+	set_pmd(pmdp, pmd);
+	pmd_val(pmd) += 256 * sizeof(pte_t);
+	set_pmd(pmdp + 1, pmd);
+}
diff -Nru a/include/asm-arm/proc-armv/pgtable.h b/include/asm-arm/proc-armv/pgtable.h
--- a/include/asm-arm/proc-armv/pgtable.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/proc-armv/pgtable.h	Fri Mar 15 17:51:01 2002
@@ -1,7 +1,7 @@
 /*
  *  linux/include/asm-arm/proc-armv/pgtable.h
  *
- *  Copyright (C) 1995-2001 Russell King
+ *  Copyright (C) 1995-2002 Russell King
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,12 +16,17 @@
 #define __ASM_PROC_PGTABLE_H
 
 /*
- * entries per page directory level: they are two-level, so
- * we don't really have any PMD directory.
+ * We pull a couple of tricks here:
+ *  1. We wrap the PMD into the PGD.
+ *  2. We lie about the size of the PTE and PGD.
+ * Even though we have 256 PTE entries and 4096 PGD entries, we tell
+ * Linux that we actually have 512 PTE entries and 2048 PGD entries.
+ * Each "Linux" PGD entry is made up of two hardware PGD entries, and
+ * each PTE table is actually two hardware PTE tables.
  */
-#define PTRS_PER_PTE		256
+#define PTRS_PER_PTE		512
 #define PTRS_PER_PMD		1
-#define PTRS_PER_PGD		4096
+#define PTRS_PER_PGD		2048
 
 /*
  * Hardware page table definitions.
@@ -109,33 +114,30 @@
 #define pmd_bad(pmd)		(pmd_val(pmd) & 2)
 #define set_pmd(pmdp,pmd)	cpu_set_pmd(pmdp, pmd)
 
-static inline pmd_t __mk_pmd(pte_t *ptep, unsigned long prot)
+static inline void pmd_clear(pmd_t *pmdp)
 {
-	unsigned long pte_ptr = (unsigned long)ptep;
-	pmd_t pmd;
-
-	pte_ptr -= PTRS_PER_PTE * sizeof(void *);
-
-	/*
-	 * The pmd must be loaded with the physical
-	 * address of the PTE table
-	 */
-	pmd_val(pmd) = __virt_to_phys(pte_ptr) | prot;
-
-	return pmd;
+	set_pmd(pmdp, __pmd(0));
+	set_pmd(pmdp + 1, __pmd(0));
 }
 
-static inline unsigned long __pmd_page(pmd_t pmd)
+static inline pte_t *pmd_page_kernel(pmd_t pmd)
 {
 	unsigned long ptr;
 
 	ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
-
 	ptr += PTRS_PER_PTE * sizeof(void *);
 
-	return __phys_to_virt(ptr);
+	return __va(ptr);
 }
 
+#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
+
+#define pte_offset_kernel(dir,addr)	(pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_offset_map(dir,addr)	(pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_offset_map_nested(dir,addr)	(pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_unmap(pte)			do { } while (0)
+#define pte_unmap_nested(pte)		do { } while (0)
+
 #define set_pte(ptep, pte)	cpu_set_pte(ptep,pte)
 
 /*
@@ -182,6 +184,8 @@
  * Mark the prot value as uncacheable and unbufferable.
  */
 #define pgprot_noncached(prot)	__pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
+
+#define pgtable_cache_init() do { } while (0)
 
 #endif /* __ASSEMBLY__ */
 
diff -Nru a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
--- a/include/asm-arm/proc-fns.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-arm/proc-fns.h	Fri Mar 15 17:51:03 2002
@@ -28,8 +28,6 @@
 
 /*
  * CPU_NAME - the prefix for CPU related functions
- * CPU_ABRT - the prefix for the CPU abort decoding function
- * MMU_ARCH - the prefix for copy_user_page/clear_user_page
  */
 
 #ifdef CONFIG_CPU_32
@@ -40,8 +38,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm6
-#   define CPU_ABRT cpu_arm6
-#   define MMU_ARCH armv3
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM710
@@ -50,8 +46,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm7
-#   define CPU_ABRT cpu_arm7
-#   define MMU_ARCH armv3
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM720T
@@ -60,8 +54,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm720
-#   define CPU_ABRT armv4t_late
-#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM920T
@@ -70,8 +62,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm920
-#   define CPU_ABRT armv4t_early
-#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM922T
@@ -80,8 +70,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm922
-#   define CPU_ABRT armv4t_early
-#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM926T
@@ -90,8 +78,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm926
-#   define CPU_ABRT armv5ej_early
-#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_SA110
@@ -100,8 +86,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_sa110
-#   define CPU_ABRT armv4_early
-#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_SA1100
@@ -110,8 +94,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_sa1100
-#   define CPU_ABRT armv4_early
-#   define MMU_ARCH armv4_mc
 #  endif
 # endif
 # ifdef CONFIG_CPU_ARM1020
@@ -120,8 +102,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_arm1020
-#   define CPU_ABRT armv4t_early
-#   define MMU_ARCH armv4
 #  endif
 # endif
 # ifdef CONFIG_CPU_XSCALE
@@ -130,8 +110,6 @@
 #   define MULTI_CPU
 #  else
 #   define CPU_NAME cpu_xscale
-#   define CPU_ABRT armv4t_early
-#   define MMU_ARCH armv5te
 #  endif
 # endif
 #endif
diff -Nru a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
--- a/include/asm-arm/procinfo.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-arm/procinfo.h	Fri Mar 15 17:51:01 2002
@@ -15,6 +15,7 @@
 #include <asm/proc-fns.h>
 
 struct cpu_tlb_fns;
+struct cpu_user_fns;
 struct processor;
 
 struct proc_info_item {
@@ -32,21 +33,22 @@
  *  arch/arm/mm/proc-*.S and arch/arm/kernel/head-armv.S
  */
 struct proc_info_list {
-	unsigned int	 cpu_val;
-	unsigned int	 cpu_mask;
-	unsigned long	 __cpu_mmu_flags;	/* used by head-armv.S */
-	unsigned long	 __cpu_flush;		/* used by head-armv.S */
-	const char	 *arch_name;
-	const char	 *elf_name;
-	unsigned int	 elf_hwcap;
-	struct proc_info_item *info;
-	struct processor *proc;
-	struct cpu_tlb_fns *tlb;
+	unsigned int		cpu_val;
+	unsigned int		cpu_mask;
+	unsigned long		__cpu_mmu_flags;	/* used by head-armv.S */
+	unsigned long		__cpu_flush;		/* used by head-armv.S */
+	const char		*arch_name;
+	const char		*elf_name;
+	unsigned int		elf_hwcap;
+	struct proc_info_item	*info;
+	struct processor	*proc;
+	struct cpu_tlb_fns	*tlb;
+	struct cpu_user_fns	*user;
 };
 
 #endif	/* __ASSEMBLY__ */
 
-#define PROC_INFO_SZ	40
+#define PROC_INFO_SZ	44
 
 #define HWCAP_SWP	 1
 #define HWCAP_HALF	 2
diff -Nru a/include/asm-i386/acpi.h b/include/asm-i386/acpi.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-i386/acpi.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,83 @@
+/*
+ *  asm-i386/acpi.h
+ *
+ *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
+ *  Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#ifndef _ASM_ACPI_H
+#define _ASM_ACPI_H
+
+#ifdef __KERNEL__
+
+#ifdef CONFIG_ACPI_BOOT
+
+/* Fixmap pages to reserve for ACPI boot-time tables (see fixmap.h) */
+#define FIX_ACPI_PAGES		4
+
+char * __acpi_map_table (unsigned long phys_addr, unsigned long size);
+extern int acpi_find_rsdp (unsigned long *phys_addr);
+extern int acpi_parse_madt (unsigned long phys_addr, unsigned long size);
+
+#endif /*CONFIG_ACPI_BOOT*/
+
+#ifdef CONFIG_ACPI_PCI
+int acpi_get_interrupt_model (int *type);
+#endif /*CONFIG_ACPI_PCI*/
+
+
+#ifdef CONFIG_ACPI_SLEEP
+
+extern unsigned long saved_eip;
+extern unsigned long saved_esp;
+extern unsigned long saved_ebp;
+extern unsigned long saved_ebx;
+extern unsigned long saved_esi;
+extern unsigned long saved_edi;
+
+static inline void acpi_save_register_state(unsigned long return_point)
+{
+	saved_eip = return_point;
+	asm volatile ("movl %%esp,(%0)" : "=m" (saved_esp));
+	asm volatile ("movl %%ebp,(%0)" : "=m" (saved_ebp));
+	asm volatile ("movl %%ebx,(%0)" : "=m" (saved_ebx));
+	asm volatile ("movl %%edi,(%0)" : "=m" (saved_edi));
+	asm volatile ("movl %%esi,(%0)" : "=m" (saved_esi));
+}
+
+#define acpi_restore_register_state()	do {} while (0)
+
+/* routines for saving/restoring kernel state */
+extern int acpi_save_state_mem(void);
+extern int acpi_save_state_disk(void);
+extern void acpi_restore_state_mem(void);
+
+extern unsigned long acpi_wakeup_address;
+
+/* early initialization routine */
+extern void acpi_reserve_bootmem(void);
+
+#endif /*CONFIG_ACPI_SLEEP*/
+
+
+#endif /*__KERNEL__*/
+
+#endif /*_ASM_ACPI_H*/
diff -Nru a/include/asm-i386/fixmap.h b/include/asm-i386/fixmap.h
--- a/include/asm-i386/fixmap.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-i386/fixmap.h	Fri Mar 15 17:51:01 2002
@@ -15,6 +15,7 @@
 
 #include <linux/config.h>
 #include <linux/kernel.h>
+#include <asm/acpi.h>
 #include <asm/apicdef.h>
 #include <asm/page.h>
 #ifdef CONFIG_HIGHMEM
@@ -61,9 +62,16 @@
 	FIX_LI_PCIA,	/* Lithium PCI Bridge A */
 	FIX_LI_PCIB,	/* Lithium PCI Bridge B */
 #endif
+#ifdef CONFIG_X86_F00F_BUG
+	FIX_F00F_IDT,	/* Virtual mapping for IDT */
+#endif
 #ifdef CONFIG_HIGHMEM
 	FIX_KMAP_BEGIN,	/* reserved pte's for temporary kernel mappings */
 	FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
+#endif
+#ifdef CONFIG_ACPI_BOOT
+	FIX_ACPI_BEGIN,
+	FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
 #endif
 	__end_of_permanent_fixed_addresses,
 	/* temporary boot-time mappings, used before ioremap() is functional */
diff -Nru a/include/asm-i386/irq.h b/include/asm-i386/irq.h
--- a/include/asm-i386/irq.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-i386/irq.h	Fri Mar 15 17:51:01 2002
@@ -23,7 +23,11 @@
  * Since vectors 0x00-0x1f are used/reserved for the CPU,
  * the usable vector space is 0x20-0xff (224 vectors)
  */
+#ifdef CONFIG_X86_IO_APIC
 #define NR_IRQS 224
+#else
+#define NR_IRQS 16
+#endif
 
 static __inline__ int irq_cannonicalize(int irq)
 {
diff -Nru a/include/asm-i386/mman.h b/include/asm-i386/mman.h
--- a/include/asm-i386/mman.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-i386/mman.h	Fri Mar 15 17:51:01 2002
@@ -4,6 +4,7 @@
 #define PROT_READ	0x1		/* page can be read */
 #define PROT_WRITE	0x2		/* page can be written */
 #define PROT_EXEC	0x4		/* page can be executed */
+#define PROT_SEM	0x8		/* page may be used for atomic ops */
 #define PROT_NONE	0x0		/* page can not be accessed */
 
 #define MAP_SHARED	0x01		/* Share changes */
diff -Nru a/include/asm-i386/pci.h b/include/asm-i386/pci.h
--- a/include/asm-i386/pci.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-i386/pci.h	Fri Mar 15 17:51:03 2002
@@ -19,6 +19,11 @@
 #define PCIBIOS_MIN_IO		0x1000
 #define PCIBIOS_MIN_MEM		(pci_mem_start)
 
+void pcibios_config_init(void);
+struct pci_bus * pcibios_scan_root(int bus);
+extern int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value);
+extern int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value);
+
 void pcibios_set_master(struct pci_dev *dev);
 void pcibios_penalize_isa_irq(int irq);
 struct irq_routing_table *pcibios_get_irq_routing_table(void);
diff -Nru a/include/asm-i386/pgalloc.h b/include/asm-i386/pgalloc.h
--- a/include/asm-i386/pgalloc.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-i386/pgalloc.h	Fri Mar 15 17:51:01 2002
@@ -223,4 +223,6 @@
 	/* i386 does not keep any page table caches in TLB */
 }
 
+#define check_pgt_cache()	do { } while (0)
+
 #endif /* _I386_PGALLOC_H */
diff -Nru a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h
--- a/include/asm-i386/unistd.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-i386/unistd.h	Fri Mar 15 17:51:03 2002
@@ -244,6 +244,7 @@
 #define __NR_fremovexattr	237
 #define __NR_tkill		238
 #define __NR_sendfile64		239
+#define __NR_futex		240
 
 /* user-visible error numbers are in the range -1 - -124: see <asm-i386/errno.h> */
 
diff -Nru a/include/asm-ia64/a.out.h b/include/asm-ia64/a.out.h
--- a/include/asm-ia64/a.out.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/a.out.h	Fri Mar 15 17:51:02 2002
@@ -7,8 +7,8 @@
  * probably would be better to clean up binfmt_elf.c so it does not
  * necessarily depend on there being a.out support.
  *
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/types.h>
@@ -31,7 +31,7 @@
 
 #ifdef __KERNEL__
 # include <asm/page.h>
-# define STACK_TOP	(0x8000000000000000UL + (1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE)
+# define STACK_TOP	(0x6000000000000000UL + (1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE)
 # define IA64_RBS_BOT	(STACK_TOP - 0x80000000L + PAGE_SIZE)	/* bottom of reg. backing store */
 #endif
 
diff -Nru a/include/asm-ia64/acpi-ext.h b/include/asm-ia64/acpi-ext.h
--- a/include/asm-ia64/acpi-ext.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/acpi-ext.h	Fri Mar 15 17:51:01 2002
@@ -13,7 +13,9 @@
  *	ACPI 2.0 specification
  */
 
+#include <linux/config.h>
 #include <linux/types.h>
+#include <linux/mm.h>
 
 #pragma	pack(1)
 #define ACPI_RSDP_SIG "RSD PTR " /* Trailing space required */
@@ -24,7 +26,7 @@
 	char oem_id[6];
 	u8 revision;
 	u32 rsdt;
-	u32 lenth;
+	u32 length;
 	struct acpi_xsdt *xsdt;
 	u8 ext_checksum;
 	u8 reserved[3];
@@ -96,7 +98,7 @@
 	struct acpi_rsdt *rsdt;
 } acpi_rsdp_t;
 
-typedef struct {
+typedef struct acpi_rsdt {
 	acpi_desc_table_hdr_t header;
 	u8 reserved[4];
 	unsigned long entry_ptrs[1];	/* Not really . . . */
@@ -151,15 +153,15 @@
 #define MADT_PCAT_COMPAT	(1<<0)
 
 /* acpi 2.0 MADT structure types */
-#define ACPI20_ENTRY_LOCAL_APIC                 0
-#define ACPI20_ENTRY_IO_APIC                    1
-#define ACPI20_ENTRY_INT_SRC_OVERRIDE           2
-#define ACPI20_ENTRY_NMI_SOURCE                 3
-#define ACPI20_ENTRY_LOCAL_APIC_NMI             4
-#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE   5
-#define ACPI20_ENTRY_IO_SAPIC                   6
-#define ACPI20_ENTRY_LOCAL_SAPIC                7
-#define ACPI20_ENTRY_PLATFORM_INT_SOURCE        8
+#define ACPI20_ENTRY_LOCAL_APIC			0
+#define ACPI20_ENTRY_IO_APIC			1
+#define ACPI20_ENTRY_INT_SRC_OVERRIDE		2
+#define ACPI20_ENTRY_NMI_SOURCE			3
+#define ACPI20_ENTRY_LOCAL_APIC_NMI		4
+#define ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE	5
+#define ACPI20_ENTRY_IO_SAPIC			6
+#define ACPI20_ENTRY_LOCAL_SAPIC		7
+#define ACPI20_ENTRY_PLATFORM_INT_SOURCE	8
 
 typedef struct acpi20_entry_lsapic {
 	u8 type;
@@ -190,16 +192,132 @@
 } acpi20_entry_platform_src_t;
 
 /* constants for interrupt routing API for device drivers */
-#define	ACPI20_ENTRY_PIS_PMI	1
-#define	ACPI20_ENTRY_PIS_INIT	2
-#define	ACPI20_ENTRY_PIS_CPEI	3
-#define	ACPI_MAX_PLATFORM_IRQS	4
+#define ACPI20_ENTRY_PIS_PMI	1
+#define ACPI20_ENTRY_PIS_INIT	2
+#define ACPI20_ENTRY_PIS_CPEI	3
+#define ACPI_MAX_PLATFORM_IRQS	4
+
+#define ACPI_SPCRT_SIG	"SPCR"
+#define ACPI_SPCRT_SIG_LEN 4
+
+#define ACPI_DBGPT_SIG	"DBGP"
+#define ACPI_DBGPT_SIG_LEN 4
 
 extern int acpi20_parse(acpi20_rsdp_t *);
+extern int acpi20_early_parse(acpi20_rsdp_t *);
 extern int acpi_parse(acpi_rsdp_t *);
 extern const char *acpi_get_sysname (void);
 extern int acpi_request_vector(u32 int_type);
-
 extern void (*acpi_idle) (void);	/* power-management idle function, if any */
+#ifdef CONFIG_NUMA
+extern cnodeid_t paddr_to_nid(unsigned long paddr);
+#endif
+
+/*
+ * ACPI 2.0 SRAT Table
+ * http://www.microsoft.com/HWDEV/design/SRAT.htm
+ */
+
+typedef struct acpi_srat {
+	acpi_desc_table_hdr_t header;
+	u32 table_revision;
+	u64 reserved;
+} acpi_srat_t;
+
+typedef struct srat_cpu_affinity {
+	u8 type;
+	u8 length;
+	u8 proximity_domain;
+	u8 apic_id;
+	u32 flags;
+	u8 local_sapic_eid;
+	u8 reserved[7];
+} srat_cpu_affinity_t;
+
+typedef struct srat_memory_affinity {
+	u8 type;
+	u8 length;
+	u8 proximity_domain;
+	u8 reserved[5];
+	u32 base_addr_lo;
+	u32 base_addr_hi;
+	u32 length_lo;
+	u32 length_hi;
+	u32 memory_type;
+	u32 flags;
+	u64 reserved2;
+} srat_memory_affinity_t;
+
+/* ACPI 2.0 SRAT structure */
+#define ACPI_SRAT_SIG "SRAT"
+#define ACPI_SRAT_SIG_LEN 4
+#define ACPI_SRAT_REVISION 1
+
+#define SRAT_CPU_STRUCTURE		0
+#define SRAT_MEMORY_STRUCTURE		1
+
+/* Only 1 flag for cpu affinity structure! */
+#define SRAT_CPU_FLAGS_ENABLED			0x00000001
+
+#define SRAT_MEMORY_FLAGS_ENABLED		0x00000001
+#define SRAT_MEMORY_FLAGS_HOTREMOVABLE		0x00000002
+
+/* ACPI 2.0 address range types */
+#define ACPI_ADDRESS_RANGE_MEMORY	1
+#define ACPI_ADDRESS_RANGE_RESERVED	2
+#define ACPI_ADDRESS_RANGE_ACPI		3
+#define ACPI_ADDRESS_RANGE_NVS		4
+
+#define NODE_ARRAY_INDEX(x)	((x) / 8)	/* 8 bits/char */
+#define NODE_ARRAY_OFFSET(x)	((x) % 8)	/* 8 bits/char */
+#define MAX_PXM_DOMAINS		(256)
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * List of node memory chunks. Filled when parsing SRAT table to
+ * obtain information about memory nodes.
+*/
+
+struct node_memory_chunk_s {
+	unsigned long start_paddr;
+	unsigned long size;
+	int pxm;			// proximity domain of node
+	int nid;			// which cnode contains this chunk?
+	int bank;			// which mem bank on this node
+};
+
+extern struct node_memory_chunk_s node_memory_chunk[PLAT_MAXCLUMPS];	// temporary?
+
+struct node_cpuid_s {
+	u16	phys_id;		/* id << 8 | eid */
+	int	pxm;			// proximity domain of cpu
+	int	nid;
+};
+extern struct node_cpuid_s node_cpuid[NR_CPUS];
+
+extern int pxm_to_nid_map[MAX_PXM_DOMAINS]; /* _PXM to logical node ID map */
+extern int nid_to_pxm_map[PLAT_MAX_COMPACT_NODES]; /* logical node ID to _PXM map */
+extern int numnodes;			/* total number of nodes in system */
+extern int num_memory_chunks;		/* total number of memory chunks */
+
+/*
+ * ACPI 2.0 SLIT Table
+ * http://devresource.hp.com/devresource/Docs/TechPapers/IA64/slit.pdf
+ */
+
+typedef struct acpi_slit {
+	acpi_desc_table_hdr_t header;
+	u64 localities;
+	u8 entries[1];			/* dummy, real size = locality^2 */
+} acpi_slit_t;
+
+extern u8 acpi20_slit[PLAT_MAX_COMPACT_NODES * PLAT_MAX_COMPACT_NODES];
+
+#define ACPI_SLIT_SIG "SLIT"
+#define ACPI_SLIT_SIG_LEN 4
+#define ACPI_SLIT_REVISION 1
+#define ACPI_SLIT_LOCAL 10
+#endif /* CONFIG_DISCONTIGMEM */
+
 #pragma	pack()
 #endif /* _ASM_IA64_ACPI_EXT_H */
diff -Nru a/include/asm-ia64/asmmacro.h b/include/asm-ia64/asmmacro.h
--- a/include/asm-ia64/asmmacro.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/asmmacro.h	Fri Mar 15 17:51:02 2002
@@ -3,7 +3,7 @@
 
 /*
  * Copyright (C) 2000-2001 Hewlett-Packard Co
- * Copyright (C) 2000-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #define ENTRY(name)				\
diff -Nru a/include/asm-ia64/bitops.h b/include/asm-ia64/bitops.h
--- a/include/asm-ia64/bitops.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/bitops.h	Fri Mar 15 17:51:03 2002
@@ -2,10 +2,15 @@
 #define _ASM_IA64_BITOPS_H
 
 /*
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *
+ * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64 O(1)
+ *	    scheduler patch
  */
 
+#include <linux/types.h>
+
 #include <asm/system.h>
 
 /**
@@ -57,10 +62,10 @@
 }
 
 /*
- * clear_bit() doesn't provide any barrier for the compiler.
+ * clear_bit() has "acquire" semantics.
  */
 #define smp_mb__before_clear_bit()	smp_mb()
-#define smp_mb__after_clear_bit()	smp_mb()
+#define smp_mb__after_clear_bit()	do { /* skip */; } while (0)
 
 /**
  * clear_bit - Clears a bit in memory
@@ -89,6 +94,17 @@
 }
 
 /**
+ * __clear_bit - Clears a bit in memory (non-atomic version)
+ */
+static __inline__ void
+__clear_bit (int nr, volatile void *addr)
+{
+	volatile __u32 *p = (__u32 *) addr + (nr >> 5);
+	__u32 m = 1 << (nr & 31);
+	*p &= ~m;
+}
+
+/**
  * change_bit - Toggle a bit in memory
  * @nr: Bit to clear
  * @addr: Address to start counting from
@@ -264,12 +280,11 @@
 }
 
 /**
- * ffz - find the first zero bit in a memory region
- * @x: The address to start the search at
+ * ffz - find the first zero bit in a long word
+ * @x: The long word to find the bit in
  *
- * Returns the bit-number (0..63) of the first (least significant) zero bit, not
- * the number of the byte containing a bit.  Undefined if no zero exists, so
- * code should check against ~0UL first...
+ * Returns the bit-number (0..63) of the first (least significant) zero bit.  Undefined if
+ * no zero exists, so code should check against ~0UL first...
  */
 static inline unsigned long
 ffz (unsigned long x)
@@ -280,6 +295,21 @@
 	return result;
 }
 
+/**
+ * __ffs - find first bit in word.
+ * @x: The word to search
+ *
+ * Undefined if no bit exists, so code should check against 0 first.
+ */
+static __inline__ unsigned long
+__ffs (unsigned long x)
+{
+	unsigned long result;
+
+	__asm__ ("popcnt %0=%1" : "=r" (result) : "r" ((x - 1) & ~x));
+	return result;
+}
+
 #ifdef __KERNEL__
 
 /*
@@ -357,6 +387,8 @@
 	tmp = *p;
 found_first:
 	tmp |= ~0UL << size;
+	if (tmp == ~0UL)		/* any bits zero? */
+		return result + size;	/* nope */
 found_middle:
 	return result + ffz(tmp);
 }
@@ -366,8 +398,53 @@
  */
 #define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
 
+/*
+ * Find next bit in a bitmap reasonably efficiently..
+ */
+static inline int
+find_next_bit (void *addr, unsigned long size, unsigned long offset)
+{
+	unsigned long *p = ((unsigned long *) addr) + (offset >> 6);
+	unsigned long result = offset & ~63UL;
+	unsigned long tmp;
+
+	if (offset >= size)
+		return size;
+	size -= result;
+	offset &= 63UL;
+	if (offset) {
+		tmp = *(p++);
+		tmp &= ~0UL << offset;
+		if (size < 64)
+			goto found_first;
+		if (tmp)
+			goto found_middle;
+		size -= 64;
+		result += 64;
+	}
+	while (size & ~63UL) {
+		if ((tmp = *(p++)))
+			goto found_middle;
+		result += 64;
+		size -= 64;
+	}
+	if (!size)
+		return result;
+	tmp = *p;
+  found_first:
+	tmp &= ~0UL >> (64-size);
+	if (tmp == 0UL)		/* Are any bits set? */
+		return result + size; /* Nope. */
+  found_middle:
+	return result + __ffs(tmp);
+}
+
+#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
+
 #ifdef __KERNEL__
 
+#define __clear_bit(nr, addr)        clear_bit(nr, addr)
+
 #define ext2_set_bit                 test_and_set_bit
 #define ext2_clear_bit               test_and_clear_bit
 #define ext2_test_bit                test_bit
@@ -380,6 +457,16 @@
 #define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
 #define minix_test_bit(nr,addr)			test_bit(nr,addr)
 #define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
+
+static inline int
+sched_find_first_bit (unsigned long *b)
+{
+	if (unlikely(b[0]))
+		return __ffs(b[0]);
+	if (unlikely(b[1]))
+		return 64 + __ffs(b[1]);
+	return __ffs(b[2]) + 128;
+}
 
 #endif /* __KERNEL__ */
 
diff -Nru a/include/asm-ia64/cache.h b/include/asm-ia64/cache.h
--- a/include/asm-ia64/cache.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/cache.h	Fri Mar 15 17:51:03 2002
@@ -5,7 +5,7 @@
 
 /*
  * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 /* Bytes per L1 (data) cache line.  */
diff -Nru a/include/asm-ia64/checksum.h b/include/asm-ia64/checksum.h
--- a/include/asm-ia64/checksum.h	Fri Mar 15 17:51:00 2002
+++ b/include/asm-ia64/checksum.h	Fri Mar 15 17:51:00 2002
@@ -89,11 +89,4 @@
 	return ~sum;
 }
 
-#define _HAVE_ARCH_IPV6_CSUM
-extern unsigned short int csum_ipv6_magic (struct in6_addr *saddr,
-					   struct in6_addr *daddr,
-					   __u16 len,
-					   unsigned short proto,
-					   unsigned int sum);
-
 #endif /* _ASM_IA64_CHECKSUM_H */
diff -Nru a/include/asm-ia64/current.h b/include/asm-ia64/current.h
--- a/include/asm-ia64/current.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/current.h	Fri Mar 15 17:51:02 2002
@@ -3,7 +3,7 @@
 
 /*
  * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 /* In kernel mode, thread pointer (r13) is used to point to the
diff -Nru a/include/asm-ia64/elf.h b/include/asm-ia64/elf.h
--- a/include/asm-ia64/elf.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/elf.h	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,8 @@
 /*
  * ELF archtecture specific definitions.
  *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <asm/fpu.h>
@@ -25,7 +25,10 @@
 
 #define USE_ELF_CORE_DUMP
 
-/* always align to 64KB to allow for future page sizes of up to 64KB: */
+/* Least-significant four bits of ELF header's e_flags are OS-specific.  The bits are
+   interpreted as follows by Linux: */
+#define EF_IA_64_LINUX_EXECUTABLE_STACK	0x1	/* is stack (& heap) executable by default? */
+
 #define ELF_EXEC_PAGESIZE	PAGE_SIZE
 
 /*
@@ -82,7 +85,9 @@
 #define ELF_PLATFORM	0
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+struct elf64_hdr;
+extern void ia64_set_personality (struct elf64_hdr *elf_ex, int ibcs2_interpreter);
+#define SET_PERSONALITY(ex, ibcs2)	ia64_set_personality(&(ex), ibcs2)
 #endif
 
 #endif /* _ASM_IA64_ELF_H */
diff -Nru a/include/asm-ia64/hardirq.h b/include/asm-ia64/hardirq.h
--- a/include/asm-ia64/hardirq.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/hardirq.h	Fri Mar 15 17:51:02 2002
@@ -2,8 +2,8 @@
 #define _ASM_IA64_HARDIRQ_H
 
 /*
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/config.h>
@@ -25,8 +25,8 @@
 
 #define local_softirq_pending()		(local_cpu_data->softirq_pending)
 #define local_ksoftirqd_task()		(local_cpu_data->ksoftirqd)
-#define local_irq_count()		(local_cpu_data->irq_stat.f.irq_count)
-#define local_bh_count()		(local_cpu_data->irq_stat.f.bh_count)
+#define really_local_irq_count()	(local_cpu_data->irq_stat.f.irq_count)	/* XXX fix me */
+#define really_local_bh_count()		(local_cpu_data->irq_stat.f.bh_count)	/* XXX fix me */
 #define local_syscall_count()		/* unused on IA-64 */
 #define local_nmi_count()		0
 
@@ -38,11 +38,11 @@
 #define in_irq()			(local_cpu_data->irq_stat.f.irq_count != 0)
 
 #ifndef CONFIG_SMP
-# define local_hardirq_trylock()	(local_irq_count() == 0)
+# define local_hardirq_trylock()	(really_local_irq_count() == 0)
 # define local_hardirq_endlock()	do { } while (0)
 
-# define local_irq_enter(irq)		(local_irq_count()++)
-# define local_irq_exit(irq)		(local_irq_count()--)
+# define local_irq_enter(irq)		(really_local_irq_count()++)
+# define local_irq_exit(irq)		(really_local_irq_count()--)
 
 # define synchronize_irq()		barrier()
 #else
@@ -70,6 +70,7 @@
 	/* if we didn't own the irq lock, just ignore.. */
 	if (global_irq_holder == cpu) {
 		global_irq_holder = NO_PROC_ID;
+		smp_mb__before_clear_bit();	/* need barrier before releasing lock... */
 		clear_bit(0,&global_irq_lock);
         }
 }
@@ -77,7 +78,7 @@
 static inline void
 local_irq_enter (int irq)
 {
-	local_irq_count()++;
+	really_local_irq_count()++;
 
 	while (test_bit(0,&global_irq_lock)) {
 		/* nothing */;
@@ -87,13 +88,13 @@
 static inline void
 local_irq_exit (int irq)
 {
-	local_irq_count()--;
+	really_local_irq_count()--;
 }
 
 static inline int
 local_hardirq_trylock (void)
 {
-	return !local_irq_count() && !test_bit(0,&global_irq_lock);
+	return !really_local_irq_count() && !test_bit(0,&global_irq_lock);
 }
 
 #define local_hardirq_endlock()		do { } while (0)
diff -Nru a/include/asm-ia64/ia32.h b/include/asm-ia64/ia32.h
--- a/include/asm-ia64/ia32.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/ia32.h	Fri Mar 15 17:51:03 2002
@@ -5,7 +5,7 @@
 
 #ifdef CONFIG_IA32_SUPPORT
 
-#include <linux/param.h>
+#include <linux/binfmts.h>
 
 /*
  * 32 bit structures for IA32 support.
@@ -474,6 +474,8 @@
 	unsigned int seg_not_present:1;
 	unsigned int useable:1;
 };
+
+struct linux_binprm;
 
 extern void ia32_gdt_init (void);
 extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
diff -Nru a/include/asm-ia64/io.h b/include/asm-ia64/io.h
--- a/include/asm-ia64/io.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/io.h	Fri Mar 15 17:51:01 2002
@@ -69,6 +69,22 @@
  */
 #define __ia64_mf_a()	__asm__ __volatile__ ("mf.a" ::: "memory")
 
+/**
+ * __ia64_mmiob - I/O space memory barrier
+ *
+ * Acts as a memory mapped I/O barrier for platforms that queue writes to
+ * I/O space.  This ensures that subsequent writes to I/O space arrive after
+ * all previous writes.  For most ia64 platforms, this is a simple
+ * 'mf.a' instruction, so the address is ignored.  For other platforms,
+ * the address may be required to ensure proper ordering of writes to I/O space
+ * since a 'dummy' read might be necessary to barrier the write operation.
+ */
+static inline void
+__ia64_mmiob (void)
+{
+	__ia64_mf_a();
+}
+
 static inline const unsigned long
 __ia64_get_io_port_base (void)
 {
@@ -271,6 +287,7 @@
 #define __outb		platform_outb
 #define __outw		platform_outw
 #define __outl		platform_outl
+#define __mmiob         platform_mmiob
 
 #define inb		__inb
 #define inw		__inw
@@ -284,6 +301,7 @@
 #define outsb		__outsb
 #define outsw		__outsw
 #define outsl		__outsl
+#define mmiob           __mmiob
 
 /*
  * The address passed to these functions are ioremap()ped already.
@@ -408,5 +426,11 @@
 #define memset_io(addr,c,len) \
   __ia64_memset_c_io((unsigned long)(addr),0x0101010101010101UL*(u8)(c),(len))
 
+
+#define dma_cache_inv(_start,_size)             do { } while (0)
+#define dma_cache_wback(_start,_size)           do { } while (0)
+#define dma_cache_wback_inv(_start,_size)       do { } while (0)
+
 # endif /* __KERNEL__ */
+
 #endif /* _ASM_IA64_IO_H */
diff -Nru a/include/asm-ia64/irq.h b/include/asm-ia64/irq.h
--- a/include/asm-ia64/irq.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/irq.h	Fri Mar 15 17:51:03 2002
@@ -2,9 +2,9 @@
 #define _ASM_IA64_IRQ_H
 
 /*
- * Copyright (C) 1999-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 1999-2000, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
  *
  * 11/24/98	S.Eranian 	updated TIMER_IRQ and irq_cannonicalize
  * 01/20/99	S.Eranian	added keyboard interrupt
@@ -27,5 +27,6 @@
 extern void disable_irq (unsigned int);
 extern void disable_irq_nosync (unsigned int);
 extern void enable_irq (unsigned int);
+extern void set_irq_affinity_info (int irq, int dest, int redir);
 
 #endif /* _ASM_IA64_IRQ_H */
diff -Nru a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
--- a/include/asm-ia64/machvec.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/machvec.h	Fri Mar 15 17:51:01 2002
@@ -20,6 +20,7 @@
 struct irq_desc;
 
 typedef void ia64_mv_setup_t (char **);
+typedef void ia64_mv_cpu_init_t(void);
 typedef void ia64_mv_irq_init_t (void);
 typedef void ia64_mv_pci_fixup_t (int);
 typedef unsigned long ia64_mv_map_nr_t (unsigned long);
@@ -59,6 +60,7 @@
 typedef void ia64_mv_outb_t (unsigned char, unsigned long);
 typedef void ia64_mv_outw_t (unsigned short, unsigned long);
 typedef void ia64_mv_outl_t (unsigned int, unsigned long);
+typedef void ia64_mv_mmiob_t (void);
 
 extern void machvec_noop (void);
 
@@ -77,6 +79,7 @@
 # else
 #  define platform_name		ia64_mv.name
 #  define platform_setup	ia64_mv.setup
+#  define platform_cpu_init	ia64_mv.cpu_init
 #  define platform_irq_init	ia64_mv.irq_init
 #  define platform_map_nr	ia64_mv.map_nr
 #  define platform_mca_init	ia64_mv.mca_init
@@ -105,11 +108,13 @@
 #  define platform_outb		ia64_mv.outb
 #  define platform_outw		ia64_mv.outw
 #  define platform_outl		ia64_mv.outl
+#  define platofrm_mmiob        ia64_mv.mmiob
 # endif
 
 struct ia64_machine_vector {
 	const char *name;
 	ia64_mv_setup_t *setup;
+	ia64_mv_cpu_init_t *cpu_init;
 	ia64_mv_irq_init_t *irq_init;
 	ia64_mv_pci_fixup_t *pci_fixup;
 	ia64_mv_map_nr_t *map_nr;
@@ -137,6 +142,7 @@
 	ia64_mv_outb_t *outb;
 	ia64_mv_outw_t *outw;
 	ia64_mv_outl_t *outl;
+	ia64_mv_mmiob_t *mmiob;
 };
 
 #define MACHVEC_INIT(name)			\
@@ -170,7 +176,8 @@
 	platform_inl,				\
 	platform_outb,				\
 	platform_outw,				\
-	platform_outl				\
+	platform_outl,				\
+        platform_mmiob                          \
 }
 
 extern struct ia64_machine_vector ia64_mv;
@@ -201,6 +208,9 @@
 #ifndef platform_setup
 # define platform_setup		((ia64_mv_setup_t *) machvec_noop)
 #endif
+#ifndef platform_cpu_init
+# define platform_cpu_init	((ia64_mv_cpu_init_t *) machvec_noop)
+#endif
 #ifndef platform_irq_init
 # define platform_irq_init	((ia64_mv_irq_init_t *) machvec_noop)
 #endif
@@ -281,6 +291,9 @@
 #endif
 #ifndef platform_outl
 # define platform_outl		__ia64_outl
+#endif
+#ifndef platform_mmiob
+# define platform_mmiob         __ia64_mmiob
 #endif
 
 #endif /* _ASM_IA64_MACHVEC_H */
diff -Nru a/include/asm-ia64/machvec_sn1.h b/include/asm-ia64/machvec_sn1.h
--- a/include/asm-ia64/machvec_sn1.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/machvec_sn1.h	Fri Mar 15 17:51:03 2002
@@ -1,7 +1,40 @@
+/*
+ * Copyright (c) 2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
 #ifndef _ASM_IA64_MACHVEC_SN1_h
 #define _ASM_IA64_MACHVEC_SN1_h
 
 extern ia64_mv_setup_t sn1_setup;
+extern ia64_mv_cpu_init_t sn_cpu_init;
 extern ia64_mv_irq_init_t sn1_irq_init;
 extern ia64_mv_map_nr_t sn1_map_nr;
 extern ia64_mv_send_ipi_t sn1_send_IPI;
@@ -13,6 +46,7 @@
 extern ia64_mv_outb_t sn1_outb;
 extern ia64_mv_outw_t sn1_outw;
 extern ia64_mv_outl_t sn1_outl;
+extern ia64_mv_mmiob_t sn_mmiob;
 extern ia64_mv_pci_alloc_consistent	sn1_pci_alloc_consistent;
 extern ia64_mv_pci_free_consistent	sn1_pci_free_consistent;
 extern ia64_mv_pci_map_single		sn1_pci_map_single;
@@ -32,6 +66,7 @@
  */
 #define platform_name		"sn1"
 #define platform_setup		sn1_setup
+#define platform_cpu_init	sn_cpu_init
 #define platform_irq_init	sn1_irq_init
 #define platform_map_nr		sn1_map_nr
 #define platform_send_ipi	sn1_send_IPI
@@ -43,6 +78,7 @@
 #define platform_outb		sn1_outb
 #define platform_outw		sn1_outw
 #define platform_outl		sn1_outl
+#define platform_mmiob          sn_mmiob
 #define platform_pci_dma_init	machvec_noop
 #define platform_pci_alloc_consistent	sn1_pci_alloc_consistent
 #define platform_pci_free_consistent	sn1_pci_free_consistent
diff -Nru a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/machvec_sn2.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#ifndef _ASM_IA64_MACHVEC_SN2_H
+#define _ASM_IA64_MACHVEC_SN2_H
+
+extern ia64_mv_setup_t sn1_setup;
+extern ia64_mv_cpu_init_t sn_cpu_init;
+extern ia64_mv_irq_init_t sn1_irq_init;
+extern ia64_mv_map_nr_t sn2_map_nr;
+extern ia64_mv_send_ipi_t sn2_send_IPI;
+extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
+extern ia64_mv_irq_desc sn1_irq_desc;
+extern ia64_mv_irq_to_vector sn1_irq_to_vector;
+extern ia64_mv_local_vector_to_irq sn1_local_vector_to_irq;
+extern ia64_mv_valid_irq sn1_valid_irq;
+extern ia64_mv_pci_fixup_t sn1_pci_fixup;
+#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */
+extern ia64_mv_inb_t sn1_inb;
+extern ia64_mv_inw_t sn1_inw;
+extern ia64_mv_inl_t sn1_inl;
+extern ia64_mv_outb_t sn1_outb;
+extern ia64_mv_outw_t sn1_outw;
+extern ia64_mv_outl_t sn1_outl;
+#endif
+extern ia64_mv_pci_alloc_consistent	sn1_pci_alloc_consistent;
+extern ia64_mv_pci_free_consistent	sn1_pci_free_consistent;
+extern ia64_mv_pci_map_single		sn1_pci_map_single;
+extern ia64_mv_pci_unmap_single		sn1_pci_unmap_single;
+extern ia64_mv_pci_map_sg		sn1_pci_map_sg;
+extern ia64_mv_pci_unmap_sg		sn1_pci_unmap_sg;
+extern ia64_mv_pci_dma_sync_single	sn1_pci_dma_sync_single;
+extern ia64_mv_pci_dma_sync_sg		sn1_pci_dma_sync_sg;
+extern ia64_mv_pci_dma_address		sn1_dma_address;
+
+/*
+ * This stuff has dual use!
+ *
+ * For a generic kernel, the macros are used to initialize the
+ * platform's machvec structure.  When compiling a non-generic kernel,
+ * the macros are used directly.
+ */
+#define platform_name		"sn2"
+#define platform_setup		sn1_setup
+#define platform_cpu_init	sn_cpu_init
+#define platform_irq_init	sn1_irq_init
+#define platform_map_nr		sn2_map_nr
+#define platform_send_ipi	sn2_send_IPI
+#define platform_global_tlb_purge       sn2_global_tlb_purge
+#define platform_pci_fixup	sn1_pci_fixup
+#ifdef Colin /* We are using the same is Generic IA64 calls defined in io.h */
+#define platform_inb		sn1_inb
+#define platform_inw		sn1_inw
+#define platform_inl		sn1_inl
+#define platform_outb		sn1_outb
+#define platform_outw		sn1_outw
+#define platform_outl		sn1_outl
+#endif
+#define platform_irq_desc	sn1_irq_desc
+#define platform_irq_to_vector	sn1_irq_to_vector
+#define platform_local_vector_to_irq	sn1_local_vector_to_irq
+#define platform_valid_irq	sn1_valid_irq
+#define platform_pci_dma_init	machvec_noop
+#define platform_pci_alloc_consistent	sn1_pci_alloc_consistent
+#define platform_pci_free_consistent	sn1_pci_free_consistent
+#define platform_pci_map_single		sn1_pci_map_single
+#define platform_pci_unmap_single	sn1_pci_unmap_single
+#define platform_pci_map_sg		sn1_pci_map_sg
+#define platform_pci_unmap_sg		sn1_pci_unmap_sg
+#define platform_pci_dma_sync_single	sn1_pci_dma_sync_single
+#define platform_pci_dma_sync_sg	sn1_pci_dma_sync_sg
+#define platform_pci_dma_address	sn1_dma_address
+
+#endif /* _ASM_IA64_MACHVEC_SN2_H */
diff -Nru a/include/asm-ia64/mca.h b/include/asm-ia64/mca.h
--- a/include/asm-ia64/mca.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/mca.h	Fri Mar 15 17:51:02 2002
@@ -7,9 +7,6 @@
  * Copyright (C) Srinivasa Thirumalachar (sprasad@engr.sgi.com)
  */
 
-/* XXX use this temporary define for MP systems trying to INIT */
-#undef SAL_MPINIT_WORKAROUND
-
 #ifndef _ASM_IA64_MCA_H
 #define _ASM_IA64_MCA_H
 
@@ -101,12 +98,19 @@
 	IA64_MCA_HALT		=	-3	/* System to be halted by SAL */
 };
 
+enum {
+	IA64_MCA_SAME_CONTEXT	=	0x0,	/* SAL to return to same context */
+	IA64_MCA_NEW_CONTEXT	=	-1	/* SAL to return to new context */
+};
+
 typedef struct ia64_mca_os_to_sal_state_s {
 	u64		imots_os_status;	/*   OS status to SAL as to what happened
 						 *   with the MCA handling.
 						 */
 	u64		imots_sal_gp;		/* GP of the SAL - physical */
-	u64		imots_new_min_state;	/* Pointer to structure containing
+	u64		imots_context;		/* 0 if return to same context
+						   1 if return to new context */
+	u64		*imots_new_min_state;	/* Pointer to structure containing
 						 * new values of registers in the min state
 						 * save area.
 						 */
@@ -127,12 +131,19 @@
 extern void ia64_mca_wakeup_int_handler(int,void *,struct pt_regs *);
 extern void ia64_mca_cmc_int_handler(int,void *,struct pt_regs *);
 extern void ia64_mca_cpe_int_handler(int,void *,struct pt_regs *);
-extern void ia64_log_print(int,prfunc_t);
+extern int  ia64_log_print(int,prfunc_t);
 extern void ia64_mca_cmc_vector_setup(void);
 extern void ia64_mca_check_errors( void );
 extern u64  ia64_log_get(int, prfunc_t);
 
 #define PLATFORM_CALL(fn, args)	printk("Platform call TBD\n")
+
+#define platform_mem_dev_err_print ia64_log_prt_oem_data
+#define platform_pci_bus_err_print ia64_log_prt_oem_data
+#define platform_pci_comp_err_print ia64_log_prt_oem_data
+#define platform_plat_specific_err_print ia64_log_prt_oem_data
+#define platform_host_ctlr_err_print ia64_log_prt_oem_data
+#define platform_plat_bus_err_print ia64_log_prt_oem_data
 
 #undef	MCA_TEST
 
diff -Nru a/include/asm-ia64/mca_asm.h b/include/asm-ia64/mca_asm.h
--- a/include/asm-ia64/mca_asm.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/mca_asm.h	Fri Mar 15 17:51:03 2002
@@ -6,6 +6,8 @@
  * Copyright (C) Srinivasa Thirumalachar <sprasad@engr.sgi.com>
  * Copyright (C) 2000 Hewlett-Packard Co.
  * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
  */
 #ifndef _ASM_IA64_MCA_ASM_H
 #define _ASM_IA64_MCA_ASM_H
@@ -24,7 +26,7 @@
  *	1. Lop off bits 61 thru 63 in the virtual address
  */
 #define INST_VA_TO_PA(addr)							\
-	dep	addr	= 0, addr, 61, 3;
+	dep	addr	= 0, addr, 61, 3
 /*
  * This macro converts a data virtual address to a physical address
  * Right now for simulation purposes the virtual addresses are
@@ -32,7 +34,7 @@
  *	1. Lop off bits 61 thru 63 in the virtual address
  */
 #define DATA_VA_TO_PA(addr)							\
-	dep	addr	= 0, addr, 61, 3;
+	dep	addr	= 0, addr, 61, 3
 /*
  * This macro converts a data physical address to a virtual address
  * Right now for simulation purposes the virtual addresses are
@@ -41,7 +43,7 @@
  */
 #define DATA_PA_TO_VA(addr,temp)							\
 	mov	temp	= 0x7	;;							\
-	dep	addr	= temp, addr, 61, 3;;
+	dep	addr	= temp, addr, 61, 3
 
 /*
  * This macro jumps to the instruction at the given virtual address
@@ -112,8 +114,8 @@
 	;;										\
 	mov	cr.iip = temp2;								\
 	mov	cr.ifs = r0;								\
-	DATA_VA_TO_PA(sp)								\
-	DATA_VA_TO_PA(gp)								\
+	DATA_VA_TO_PA(sp);								\
+	DATA_VA_TO_PA(gp);								\
 	;;										\
 	srlz.i;										\
 	;;										\
@@ -130,8 +132,7 @@
  * translations turned on.
  *	1.	Get the old saved psr
  *
- *	2.	Clear the interrupt enable and interrupt state collection bits
- *		in the current psr.
+ *	2.	Clear the interrupt state collection bit in the current psr.
  *
  *	3.	Set the instruction translation bit back in the old psr
  *		Note we have to do this since we are right now saving only the
@@ -140,9 +141,11 @@
  *
  *	4.	Set ipsr to this old_psr with "it" bit set and "bn" = 1.
  *
- *	5.	Set iip to the virtual address of the next instruction bundle.
+ *	5.	Reset the current thread pointer (r13).
  *
- *	6.	Do an rfi to move ipsr to psr and iip to ip.
+ *	6.	Set iip to the virtual address of the next instruction bundle.
+ *
+ *	7.	Do an rfi to move ipsr to psr and iip to ip.
  */
 
 #define VIRTUAL_MODE_ENTER(temp1, temp2, start_addr, old_psr)	\
@@ -156,6 +159,10 @@
 	mov	ar.rsc = 0;					\
 	;;							\
 	srlz.d;							\
+	mov	r13 = ar.k6;					\
+	;;							\
+	DATA_PA_TO_VA(r13,temp1);				\
+	;;							\
 	mov	temp2 = ar.bspstore;				\
 	;;							\
 	DATA_PA_TO_VA(temp2,temp1);				\
@@ -170,8 +177,6 @@
 	;;							\
 	mov	temp2 = 1;					\
 	;;							\
-	dep	temp1 = temp2, temp1, PSR_I,  1;		\
-	;;							\
 	dep	temp1 = temp2, temp1, PSR_IC, 1;		\
 	;;							\
 	dep	temp1 = temp2, temp1, PSR_IT, 1;		\
@@ -195,7 +200,7 @@
 	nop	1;						\
 	nop	2;						\
 	nop	1;						\
-	rfi;							\
+	rfi							\
 	;;
 
 /*
diff -Nru a/include/asm-ia64/mman.h b/include/asm-ia64/mman.h
--- a/include/asm-ia64/mman.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/mman.h	Fri Mar 15 17:51:03 2002
@@ -2,13 +2,14 @@
 #define _ASM_IA64_MMAN_H
 
 /*
- * Copyright (C) 1998-2000 Hewlett-Packard Co
- * Copyright (C) 1998-2000 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2000, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #define PROT_READ	0x1		/* page can be read */
 #define PROT_WRITE	0x2		/* page can be written */
 #define PROT_EXEC	0x4		/* page can be executed */
+#define PROT_SEM	0x8		/* page may be used for atomic ops */
 #define PROT_NONE	0x0		/* page can not be accessed */
 
 #define MAP_SHARED	0x01		/* Share changes */
@@ -23,8 +24,6 @@
 #define MAP_EXECUTABLE	0x1000		/* mark it as an executable */
 #define MAP_LOCKED	0x2000		/* pages are locked */
 #define MAP_NORESERVE	0x4000		/* don't check for reservations */
-#define MAP_WRITECOMBINED 0x10000	/* write-combine the area */
-#define MAP_NONCACHED	0x20000		/* don't cache the memory */
 
 #define MS_ASYNC	1		/* sync memory asynchronously */
 #define MS_INVALIDATE	2		/* invalidate the caches */
diff -Nru a/include/asm-ia64/offsets.h b/include/asm-ia64/offsets.h
--- a/include/asm-ia64/offsets.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/offsets.h	Fri Mar 15 17:51:03 2002
@@ -6,25 +6,16 @@
  * This file was generated by arch/ia64/tools/print_offsets.awk.
  *
  */
-#define PT_PTRACED_BIT		0
-#define PT_TRACESYS_BIT		1
-#define IA64_TASK_SIZE			3408	/* 0xd50 */
+#define IA64_TASK_SIZE			3936	/* 0xf60 */
+#define IA64_THREAD_INFO_SIZE		24	/* 0x18 */
 #define IA64_PT_REGS_SIZE		400	/* 0x190 */
 #define IA64_SWITCH_STACK_SIZE		560	/* 0x230 */
 #define IA64_SIGINFO_SIZE		128	/* 0x80 */
-#define IA64_CPU_SIZE			16384	/* 0x4000 */
+#define IA64_CPU_SIZE			224	/* 0xe0 */
 #define SIGFRAME_SIZE			2816	/* 0xb00 */
 #define UNW_FRAME_INFO_SIZE		448	/* 0x1c0 */
 
-#define IA64_TASK_PTRACE_OFFSET		48	/* 0x30 */
-#define IA64_TASK_SIGPENDING_OFFSET	16	/* 0x10 */
-#define IA64_TASK_NEED_RESCHED_OFFSET	40	/* 0x28 */
-#define IA64_TASK_PROCESSOR_OFFSET	100	/* 0x64 */
-#define IA64_TASK_THREAD_OFFSET		976	/* 0x3d0 */
-#define IA64_TASK_THREAD_KSP_OFFSET	976	/* 0x3d0 */
-#define IA64_TASK_PFM_MUST_BLOCK_OFFSET	1600	/* 0x640 */
-#define IA64_TASK_PID_OFFSET		220	/* 0xdc */
-#define IA64_TASK_MM_OFFSET		88	/* 0x58 */
+#define IA64_TASK_THREAD_KSP_OFFSET	1480	/* 0x5c8 */
 #define IA64_PT_REGS_CR_IPSR_OFFSET	0	/* 0x0 */
 #define IA64_PT_REGS_CR_IIP_OFFSET	8	/* 0x8 */
 #define IA64_PT_REGS_CR_IFS_OFFSET	16	/* 0x10 */
@@ -134,8 +125,5 @@
 #define IA64_SIGFRAME_SIGCONTEXT_OFFSET	160	/* 0xa0 */
 #define IA64_CLONE_VFORK		16384	/* 0x4000 */
 #define IA64_CLONE_VM			256	/* 0x100 */
-#define IA64_CPU_IRQ_COUNT_OFFSET	0	/* 0x0 */
-#define IA64_CPU_BH_COUNT_OFFSET	4	/* 0x4 */
-#define IA64_CPU_PHYS_STACKED_SIZE_P8_OFFSET 12	/* 0xc */
 
 #endif /* _ASM_IA64_OFFSETS_H */
diff -Nru a/include/asm-ia64/page.h b/include/asm-ia64/page.h
--- a/include/asm-ia64/page.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/page.h	Fri Mar 15 17:51:01 2002
@@ -3,8 +3,8 @@
 /*
  * Pagetable related stuff.
  *
- * Copyright (C) 1998, 1999 Hewlett-Packard Co
- * Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998, 1999, 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/config.h>
@@ -39,6 +39,22 @@
 
 extern void clear_page (void *page);
 extern void copy_page (void *to, void *from);
+
+/*
+ * clear_user_page() and copy_user_page() can't be inline functions because
+ * flush_dcache_page() can't be defined until later...
+ */
+#define clear_user_page(addr, vaddr, page)	\
+do {						\
+	clear_page(addr);			\
+	flush_dcache_page(page);		\
+} while (0)
+
+#define copy_user_page(to, from, vaddr, page)	\
+do {						\
+	copy_page((to), (from));		\
+	flush_dcache_page(page);		\
+} while (0)
 
 /*
  * Note: the MAP_NR_*() macro can't use __pa() because MAP_NR_*(X) MUST
diff -Nru a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
--- a/include/asm-ia64/pal.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/pal.h	Fri Mar 15 17:51:01 2002
@@ -88,10 +88,10 @@
 typedef s64				pal_status_t;
 
 #define PAL_STATUS_SUCCESS		0	/* No error */
-#define PAL_STATUS_UNIMPLEMENTED	-1	/* Unimplemented procedure */
-#define PAL_STATUS_EINVAL		-2	/* Invalid argument */
-#define PAL_STATUS_ERROR		-3	/* Error */
-#define PAL_STATUS_CACHE_INIT_FAIL	-4	/* Could not initialize the
+#define PAL_STATUS_UNIMPLEMENTED	(-1)	/* Unimplemented procedure */
+#define PAL_STATUS_EINVAL		(-2)	/* Invalid argument */
+#define PAL_STATUS_ERROR		(-3)	/* Error */
+#define PAL_STATUS_CACHE_INIT_FAIL	(-4)	/* Could not initialize the
 						 * specified level and type of
 						 * cache without sideeffects
 						 * and "restrict" was 1
diff -Nru a/include/asm-ia64/pci.h b/include/asm-ia64/pci.h
--- a/include/asm-ia64/pci.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/pci.h	Fri Mar 15 17:51:03 2002
@@ -1,10 +1,11 @@
 #ifndef _ASM_IA64_PCI_H
 #define _ASM_IA64_PCI_H
 
+#include <linux/mm.h>
 #include <linux/slab.h>
+#include <linux/spinlock.h>
 #include <linux/string.h>
 #include <linux/types.h>
-#include <linux/spinlock.h>
 
 #include <asm/io.h>
 #include <asm/scatterlist.h>
@@ -21,6 +22,13 @@
 
 struct pci_dev;
 
+/*
+ * The PCI address space does equal the physical memory address space.
+ * The networking and block device layers use this boolean for bounce
+ * buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS	(1)
+
 static inline void
 pcibios_set_master (struct pci_dev *dev)
 {
@@ -79,7 +87,7 @@
 /* The ia64 platform always supports 64-bit addressing. */
 #define pci_dac_dma_supported(pci_dev, mask)	(1)
 
-#define pci_dac_page_to_dma(dev,pg,off,dir)	((dma64_addr_t) page_to_bus(pg) + (off))
+#define pci_dac_page_to_dma(dev,pg,off,dir)	((dma_addr_t) page_to_bus(pg) + (off))
 #define pci_dac_dma_to_page(dev,dma_addr)	(virt_to_page(bus_to_virt(dma_addr)))
 #define pci_dac_dma_to_offset(dev,dma_addr)	((dma_addr) & ~PAGE_MASK)
 #define pci_dac_dma_sync_single(dev,dma_addr,len,dir)	do { /* nothing */ } while (0)
diff -Nru a/include/asm-ia64/perfmon.h b/include/asm-ia64/perfmon.h
--- a/include/asm-ia64/perfmon.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/perfmon.h	Fri Mar 15 17:51:03 2002
@@ -1,55 +1,177 @@
 /*
- * Copyright (C) 2001 Hewlett-Packard Co
- * Copyright (C) 2001 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
+ *               Stephane Eranian <eranian@hpl.hp.com>
  */
 
 #ifndef _ASM_IA64_PERFMON_H
 #define _ASM_IA64_PERFMON_H
 
-#include <linux/types.h>
+/*
+ * perfmon comamnds supported on all CPU models
+ */
+#define PFM_WRITE_PMCS		0x01
+#define PFM_WRITE_PMDS		0x02
+#define PFM_READ_PMDS		0x03
+#define PFM_STOP		0x04
+#define PFM_START		0x05
+#define PFM_ENABLE		0x06
+#define PFM_DISABLE		0x07
+#define PFM_CREATE_CONTEXT	0x08
+#define PFM_DESTROY_CONTEXT	0x09
+#define PFM_RESTART		0x0a
+#define PFM_PROTECT_CONTEXT	0x0b
+#define PFM_GET_FEATURES	0x0c
+#define PFM_DEBUG		0x0d
+#define PFM_UNPROTECT_CONTEXT	0x0e
+
+
+/*
+ * CPU model specific commands (may not be supported on all models)
+ */
+#define PFM_WRITE_IBRS		0x20
+#define PFM_WRITE_DBRS		0x21
+
+/*
+ * context flags
+ */
+#define PFM_FL_INHERIT_NONE	 0x00	/* never inherit a context across fork (default) */
+#define PFM_FL_INHERIT_ONCE	 0x01	/* clone pfm_context only once across fork() */
+#define PFM_FL_INHERIT_ALL	 0x02	/* always clone pfm_context across fork() */
+#define PFM_FL_NOTIFY_BLOCK    	 0x04	/* block task on user level notifications */
+#define PFM_FL_SYSTEM_WIDE	 0x08	/* create a system wide context */
+
+/*
+ * PMC flags
+ */
+#define PFM_REGFL_OVFL_NOTIFY	0x1	/* send notification on overflow */
+
+/*
+ * PMD/PMC/IBR/DBR return flags (ignored on input)
+ *
+ * Those flags are used on output and must be checked in case EAGAIN is returned
+ * by any of the calls using a pfarg_reg_t or pfarg_dbreg_t structure.
+ */
+#define PFM_REG_RETFL_NOTAVAIL	(1U<<31) /* set if register is implemented but not available */
+#define PFM_REG_RETFL_EINVAL	(1U<<30) /* set if register entry is invalid */
+#define PFM_REG_RETFL_MASK	(PFM_REG_RETFL_NOTAVAIL|PFM_REG_RETFL_EINVAL)
+
+#define PFM_REG_HAS_ERROR(flag)	(((flag) & PFM_REG_RETFL_MASK) != 0)
 
 /*
  * Request structure used to define a context
  */
 typedef struct {
-	unsigned long smpl_entries;	/* how many entries in sampling buffer */
-	unsigned long smpl_regs;	/* which pmds to record on overflow */
-	void	      *smpl_vaddr;	/* returns address of BTB buffer */
+	unsigned long ctx_smpl_entries;	/* how many entries in sampling buffer */
+	unsigned long ctx_smpl_regs[4];	/* which pmds to record on overflow */
 
-	pid_t	      notify_pid;	/* which process to notify on overflow */
-	int	      notify_sig; 	/* XXX: not used anymore */
+	pid_t	      ctx_notify_pid;	/* which process to notify on overflow */
+	int	      ctx_flags;	/* noblock/block, inherit flags */
+	void	      *ctx_smpl_vaddr;	/* returns address of BTB buffer */
 
-	int	      flags;		/* NOBLOCK/BLOCK/ INHERIT flags (will replace API flags) */
-} pfreq_context_t;
+	unsigned long ctx_cpu_mask;	/* on which CPU to enable perfmon (systemwide) */
+
+	unsigned long reserved[8];	/* for future use */
+} pfarg_context_t;
 
 /*
  * Request structure used to write/read a PMC or PMD
  */
 typedef struct {
-	unsigned long	reg_num;	/* which register */
+	unsigned int	reg_num;	/* which register */
+	unsigned int	reg_flags;	/* PMC: notify/don't notify. PMD/PMC: return flags */
 	unsigned long	reg_value;	/* configuration (PMC) or initial value (PMD) */
-	unsigned long	reg_smpl_reset;	/* reset of sampling buffer overflow (large) */
-	unsigned long	reg_ovfl_reset;	/* reset on counter overflow (small) */
-	int		reg_flags;	/* (PMD): notify/don't notify */
-} pfreq_reg_t;
+
+	unsigned long	reg_long_reset;	/* reset after sampling buffer overflow (large) */
+	unsigned long	reg_short_reset;/* reset after counter overflow (small) */
+
+	unsigned long	reg_reset_pmds[4]; /* which other counters to reset on overflow */
+
+	unsigned long   reserved[16];	/* for future use */
+} pfarg_reg_t;
+
+typedef struct {
+	unsigned int	dbreg_num;	/* which register */
+	unsigned int	dbreg_flags;	/* dbregs return flags */
+	unsigned long	dbreg_value;	/* configuration (PMC) or initial value (PMD) */
+	unsigned long	reserved[6];
+} pfarg_dbreg_t;
+
+typedef struct {			
+	unsigned int	ft_version;	/* perfmon: major [16-31], minor [0-15] */
+	unsigned int	ft_smpl_version;/* sampling format: major [16-31], minor [0-15] */
+	unsigned long	reserved[4];	/* for future use */
+} pfarg_features_t;
 
 /*
- * main request structure passed by user
- */
-typedef union {
-	pfreq_context_t	pfr_ctx;	/* request to configure a context */
-	pfreq_reg_t	pfr_reg;	/* request to configure a PMD/PMC */
-} perfmon_req_t;
+ * This header is at the beginning of the sampling buffer returned to the user.
+ * It is exported as Read-Only at this point. It is directly followed by the
+ * first record.
+ */
+typedef struct {
+	unsigned int	hdr_version;		/* contains perfmon version (smpl format diffs) */
+	unsigned int	reserved;
+	unsigned long	hdr_entry_size;		/* size of one entry in bytes */
+	unsigned long	hdr_count;		/* how many valid entries */
+	unsigned long	hdr_pmds[4];		/* which pmds are recorded */
+} perfmon_smpl_hdr_t;
+
+/*
+ * Define the version numbers for both perfmon as a whole and the sampling buffer format.
+ */
+#define PFM_VERSION_MAJ		1U
+#define PFM_VERSION_MIN		0U
+#define PFM_VERSION		(((PFM_VERSION_MAJ&0xffff)<<16)|(PFM_VERSION_MIN & 0xffff))
+
+#define PFM_SMPL_VERSION_MAJ	1U
+#define PFM_SMPL_VERSION_MIN	0U
+#define PFM_SMPL_VERSION	(((PFM_SMPL_VERSION_MAJ&0xffff)<<16)|(PFM_SMPL_VERSION_MIN & 0xffff))
+
+
+#define PFM_VERSION_MAJOR(x)	(((x)>>16) & 0xffff)
+#define PFM_VERSION_MINOR(x)	((x) & 0xffff)
+
+/*
+ * Entry header in the sampling buffer.
+ * The header is directly followed with the PMDS saved in increasing index 
+ * order: PMD4, PMD5, .... How many PMDs are present is determined by the 
+ * user program during context creation.
+ *
+ * XXX: in this version of the entry, only up to 64 registers can be recorded
+ * This should be enough for quite some time. Always check sampling format
+ * before parsing entries!
+ *
+ * Inn the case where multiple counters have overflowed at the same time, the 
+ * rate field indicate the initial value of the first PMD, based on the index.
+ * For instance, if PMD2 and PMD5 have ovewrflowed for this entry, the rate field
+ * will show the initial value of PMD2.
+ */
+typedef struct {
+	int		pid;		/* identification of process */
+	int		cpu;		/* which cpu was used */
+	unsigned long	rate;		/* initial value of overflowed counter */
+	unsigned long	stamp;		/* timestamp */
+	unsigned long	ip;		/* where did the overflow interrupt happened */
+	unsigned long	regs;		/* bitmask of which registers overflowed */
+	unsigned long   period;		/* sampling period used by overflowed counter (smallest pmd index) */
+} perfmon_smpl_entry_t;
+
+extern int perfmonctl(pid_t pid, int cmd, void *arg, int narg);
 
 #ifdef __KERNEL__
 
 extern void pfm_save_regs (struct task_struct *);
 extern void pfm_load_regs (struct task_struct *);
 
-extern int pfm_inherit (struct task_struct *, struct pt_regs *);
+extern int  pfm_inherit (struct task_struct *, struct pt_regs *);
 extern void pfm_context_exit (struct task_struct *);
 extern void pfm_flush_regs (struct task_struct *);
 extern void pfm_cleanup_notifiers (struct task_struct *);
+extern void pfm_cleanup_owners (struct task_struct *);
+extern int  pfm_use_debug_registers(struct task_struct *);
+extern int  pfm_release_debug_registers(struct task_struct *);
+extern int  pfm_cleanup_smpl_buf(struct task_struct *);
+extern void pfm_syst_wide_update_task(struct task_struct *, int);
+extern void pfm_ovfl_block_reset (void);
 
 #endif /* __KERNEL__ */
 
diff -Nru a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h
--- a/include/asm-ia64/pgalloc.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/pgalloc.h	Fri Mar 15 17:51:01 2002
@@ -30,7 +30,6 @@
  */
 #define pgd_quicklist		(local_cpu_data->pgd_quick)
 #define pmd_quicklist		(local_cpu_data->pmd_quick)
-#define pte_quicklist		(local_cpu_data->pte_quick)
 #define pgtable_cache_size	(local_cpu_data->pgtable_cache_sz)
 
 static inline pgd_t*
@@ -108,27 +107,29 @@
 }
 
 static inline void
-pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte)
+pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, struct page *pte)
+{
+	pmd_val(*pmd_entry) = page_to_phys(pte);
+}
+
+static inline void
+pmd_populate_kernel (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte)
 {
 	pmd_val(*pmd_entry) = __pa(pte);
 }
 
-static inline pte_t*
-pte_alloc_one_fast (struct mm_struct *mm, unsigned long addr)
+static inline struct page *
+pte_alloc_one (struct mm_struct *mm, unsigned long addr)
 {
-	unsigned long *ret = (unsigned long *)pte_quicklist;
+	struct page *pte = alloc_pages(GFP_KERNEL, 0);
 
-	if (__builtin_expect(ret != NULL, 1)) {
-		pte_quicklist = (unsigned long *)(*ret);
-		ret[0] = 0;
-		--pgtable_cache_size;
-	}
-	return (pte_t *)ret;
+	if (__builtin_expect(pte != NULL, 1))
+		clear_page(page_address(pte));
+	return pte;
 }
 
-
-static inline pte_t*
-pte_alloc_one (struct mm_struct *mm, unsigned long addr)
+static inline pte_t *
+pte_alloc_one_kernel (struct mm_struct *mm, unsigned long addr)
 {
 	pte_t *pte = (pte_t *) __get_free_page(GFP_KERNEL);
 
@@ -138,16 +139,45 @@
 }
 
 static inline void
-pte_free (pte_t *pte)
+pte_free (struct page *pte)
 {
-	*(unsigned long *)pte = (unsigned long) pte_quicklist;
-	pte_quicklist = (unsigned long *) pte;
-	++pgtable_cache_size;
+	__free_page(pte);
+}
+
+static inline void
+pte_free_kernel (pte_t *pte)
+{
+	free_page((unsigned long) pte);
 }
 
 extern int do_check_pgt_cache (int, int);
 
 /*
+ * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
+ * information.  However, we use this macro to take care of any (delayed) i-cache flushing
+ * that may be necessary.
+ */
+static inline void
+update_mmu_cache (struct vm_area_struct *vma, unsigned long vaddr, pte_t pte)
+{
+	unsigned long addr;
+	struct page *page;
+
+	if (!pte_exec(pte))
+		return;				/* not an executable page... */
+
+	page = pte_page(pte);
+	/* don't use VADDR: it may not be mapped on this CPU (or may have just been flushed): */
+	addr = (unsigned long) page_address(page);
+
+	if (test_bit(PG_arch_1, &page->flags))
+		return;				/* i-cache is already coherent with d-cache */
+
+	flush_icache_range(addr, addr + PAGE_SIZE);
+	set_bit(PG_arch_1, &page->flags);	/* mark page as clean */
+}
+
+/*
  * Now for some TLB flushing routines.  This is the kind of stuff that
  * can be very expensive, so try to avoid them whenever possible.
  */
@@ -210,65 +240,6 @@
 		printk("flush_tlb_pgtables: can't flush across regions!!\n");
 	vma.vm_mm = mm;
 	flush_tlb_range(&vma, ia64_thash(start), ia64_thash(end));
-}
-
-/*
- * Now for some cache flushing routines.  This is the kind of stuff
- * that can be very expensive, so try to avoid them whenever possible.
- */
-
-/* Caches aren't brain-dead on the IA-64. */
-#define flush_cache_all()			do { } while (0)
-#define flush_cache_mm(mm)			do { } while (0)
-#define flush_cache_range(vma, start, end)	do { } while (0)
-#define flush_cache_page(vma, vmaddr)		do { } while (0)
-#define flush_page_to_ram(page)			do { } while (0)
-
-extern void flush_icache_range (unsigned long start, unsigned long end);
-
-static inline void
-flush_dcache_page (struct page *page)
-{
-	clear_bit(PG_arch_1, &page->flags);
-}
-
-static inline void
-clear_user_page (void *addr, unsigned long vaddr, struct page *page)
-{
-	clear_page(addr);
-	flush_dcache_page(page);
-}
-
-static inline void
-copy_user_page (void *to, void *from, unsigned long vaddr, struct page *page)
-{
-	copy_page(to, from);
-	flush_dcache_page(page);
-}
-
-/*
- * IA-64 doesn't have any external MMU info: the page tables contain all the necessary
- * information.  However, we use this macro to take care of any (delayed) i-cache flushing
- * that may be necessary.
- */
-static inline void
-update_mmu_cache (struct vm_area_struct *vma, unsigned long vaddr, pte_t pte)
-{
-	unsigned long addr;
-	struct page *page;
-
-	if (!pte_exec(pte))
-		return;				/* not an executable page... */
-
-	page = pte_page(pte);
-	/* don't use VADDR: it may not be mapped on this CPU (or may have just been flushed): */
-	addr = (unsigned long) page_address(page);
-
-	if (test_bit(PG_arch_1, &page->flags))
-		return;				/* i-cache is already coherent with d-cache */
-
-	flush_icache_range(addr, addr + PAGE_SIZE);
-	set_bit(PG_arch_1, &page->flags);	/* mark page as clean */
 }
 
 #endif /* _ASM_IA64_PGALLOC_H */
diff -Nru a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
--- a/include/asm-ia64/pgtable.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/pgtable.h	Fri Mar 15 17:51:02 2002
@@ -8,7 +8,7 @@
  * This hopefully works with any (fixed) IA-64 page-size, as defined
  * in <asm/page.h> (currently 8192).
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
@@ -108,19 +108,15 @@
 /*
  * All the normal masks have the "page accessed" bits on, as any time
  * they are used, the page is accessed. They are cleared only by the
- * page-out routines.  On the other hand, we do NOT turn on the
- * execute bit on pages that are mapped writable.  For those pages, we
- * turn on the X bit only when the program attempts to actually
- * execute code in such a page (it's a "lazy execute bit", if you
- * will).  This lets reduce the amount of i-cache flushing we have to
- * do for data pages such as stack and heap pages.
+ * page-out routines.
  */
 #define PAGE_NONE	__pgprot(_PAGE_PROTNONE | _PAGE_A)
 #define PAGE_SHARED	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
 #define PAGE_READONLY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
-#define PAGE_COPY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
+#define PAGE_COPY	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
 #define PAGE_GATE	__pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
 #define PAGE_KERNEL	__pgprot(__DIRTY_BITS  | _PAGE_PL_0 | _PAGE_AR_RWX)
+#define PAGE_KERNELRX	__pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
 
 # ifndef __ASSEMBLY__
 
@@ -152,8 +148,8 @@
 #define __S011	PAGE_SHARED
 #define __S100	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
 #define __S101	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
-#define __S110	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
-#define __S111	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
+#define __S110	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
+#define __S111	__pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
 
 #define pgd_ERROR(e)	printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
 #define pmd_ERROR(e)	printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
@@ -161,8 +157,7 @@
 
 
 /*
- * Some definitions to translate between mem_map, PTEs, and page
- * addresses:
+ * Some definitions to translate between mem_map, PTEs, and page addresses:
  */
 
 
@@ -173,6 +168,7 @@
 	return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
 }
 
+#ifndef CONFIG_DISCONTIGMEM
 /*
  * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
  * memory.  For the return value to be meaningful, ADDR must be >=
@@ -188,6 +184,8 @@
  */
 #define kern_addr_valid(addr)	(1)
 
+#endif
+
 /*
  * Now come the defines and routines to manage and access the three-level
  * page table.
@@ -211,12 +209,12 @@
  * Conversion functions: convert a page and protection to a page entry,
  * and a page entry and page directory to the page they refer to.
  */
-#define mk_pte(page,pgprot)							\
-({										\
-	pte_t __pte;								\
-										\
-	pte_val(__pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot);	\
-	__pte;									\
+#define mk_pte(page,pgprot)						\
+({									\
+	pte_t __pte;							\
+									\
+	pte_val(__pte) = (page_to_phys(page)) | pgprot_val(pgprot);	\
+	__pte;								\
 })
 
 /* This takes a physical page address that is used by the remapping functions */
@@ -232,14 +230,17 @@
 #define pte_none(pte) 			(!pte_val(pte))
 #define pte_present(pte)		(pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
 #define pte_clear(pte)			(pte_val(*(pte)) = 0UL)
+#ifndef CONFIG_DISCONTIGMEM
 /* pte_page() returns the "struct page *" corresponding to the PTE: */
-#define pte_page(pte)			(mem_map + (unsigned long) ((pte_val(pte) & _PFN_MASK) >> PAGE_SHIFT))
+#define pte_page(pte)			virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
+#endif
 
 #define pmd_none(pmd)			(!pmd_val(pmd))
 #define pmd_bad(pmd)			(!ia64_phys_addr_valid(pmd_val(pmd)))
 #define pmd_present(pmd)		(pmd_val(pmd) != 0UL)
 #define pmd_clear(pmdp)			(pmd_val(*(pmdp)) = 0UL)
-#define pmd_page(pmd)			((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
+#define pmd_page_kernel(pmd)		((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
+#define pmd_page(pmd)			virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
 
 #define pgd_none(pgd)			(!pgd_val(pgd))
 #define pgd_bad(pgd)			(!ia64_phys_addr_valid(pgd_val(pgd)))
@@ -339,9 +340,16 @@
 #define pmd_offset(dir,addr) \
 	((pmd_t *) pgd_page(*(dir)) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
 
-/* Find an entry in the third-level page table.. */
-#define pte_offset(dir,addr) \
-	((pte_t *) pmd_page(*(dir)) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+/*
+ * Find an entry in the third-level page table.  This looks more complicated than it
+ * should be because some platforms place page tables in high memory.
+ */
+#define __pte_offset(addr)	 	(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir,addr)	((pte_t *) pmd_page_kernel(*(dir)) + __pte_offset(addr))
+#define pte_offset_map(dir,addr)	pte_offset_kernel(dir, addr)
+#define pte_offset_map_nested(dir,addr)	pte_offset_map(dir, addr)
+#define pte_unmap(pte)			do { } while (0)
+#define pte_unmap_nested(pte)		do { } while (0)
 
 /* atomic versions of the some PTE manipulations: */
 
@@ -418,22 +426,6 @@
 	return pte_val(a) == pte_val(b);
 }
 
-/*
- * Macros to check the type of access that triggered a page fault.
- */
-
-static inline int
-is_write_access (int access_type)
-{
-	return (access_type & 0x2);
-}
-
-static inline int
-is_exec_access (int access_type)
-{
-	return (access_type & 0x4);
-}
-
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 extern void paging_init (void);
 
@@ -447,6 +439,33 @@
 #define PageSkip(page)		(0)
 
 #define io_remap_page_range remap_page_range	/* XXX is this right? */
+
+
+/*
+ * Now for some cache flushing routines.  This is the kind of stuff that can be very
+ * expensive, so try to avoid them whenever possible.
+ */
+
+/* Caches aren't brain-dead on the IA-64. */
+#define flush_cache_all()			do { } while (0)
+#define flush_cache_mm(mm)			do { } while (0)
+#define flush_cache_range(vma, start, end)	do { } while (0)
+#define flush_cache_page(vma, vmaddr)		do { } while (0)
+#define flush_page_to_ram(page)			do { } while (0)
+#define flush_icache_page(vma,page)		do { } while (0)
+
+#define flush_dcache_page(page)			\
+do {						\
+	clear_bit(PG_arch_1, &page->flags);	\
+} while (0)
+
+extern void flush_icache_range (unsigned long start, unsigned long end);
+
+#define flush_icache_user_range(vma, page, user_addr, len)			\
+do {										\
+	unsigned long _addr = page_address(page) + ((user_addr) & ~PAGE_MASK);	\
+	flush_icache_range(_addr, _addr + (len));				\
+} while (0)
 
 /*
  * ZERO_PAGE is a global shared page that is always zero: used
diff -Nru a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
--- a/include/asm-ia64/processor.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/processor.h	Fri Mar 15 17:51:02 2002
@@ -2,9 +2,9 @@
 #define _ASM_IA64_PROCESSOR_H
 
 /*
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998-2001 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  *
@@ -15,6 +15,8 @@
 
 #include <linux/config.h>
 
+#include <linux/compiler.h>
+
 #include <asm/ptrace.h>
 #include <asm/kregs.h>
 #include <asm/system.h>
@@ -27,7 +29,6 @@
  */
 #define IA64_NUM_PMC_REGS	32
 #define IA64_NUM_PMD_REGS	32
-#define IA64_NUM_PMD_COUNTERS	4
 
 #define DEFAULT_MAP_BASE	0x2000000000000000
 #define DEFAULT_TASK_SIZE	0xa000000000000000
@@ -170,6 +171,7 @@
 #define IA64_THREAD_KRBS_SYNCED	(__IA64_UL(1) << 5)	/* krbs synced with process vm? */
 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6)	/* don't log any fpswa faults */
 #define IA64_THREAD_FPEMU_SIGFPE  (__IA64_UL(1) << 7)	/* send a SIGFPE for fpswa faults */
+#define IA64_THREAD_XSTACK	(__IA64_UL(1) << 8)	/* stack executable by default? */
 
 #define IA64_THREAD_UAC_SHIFT	3
 #define IA64_THREAD_UAC_MASK	(IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
@@ -184,9 +186,14 @@
  */
 #define IA64_USEC_PER_CYC_SHIFT	41
 
+#define __HAVE_ARCH_PER_CPU
+
+#define THIS_CPU(var)	(var)
+
 #ifndef __ASSEMBLY__
 
 #include <linux/threads.h>
+#include <linux/cache.h>
 
 #include <asm/fpu.h>
 #include <asm/offsets.h>
@@ -195,6 +202,11 @@
 #include <asm/unwind.h>
 #include <asm/atomic.h>
 
+extern unsigned long __per_cpu_offset[NR_CPUS];
+
+#define per_cpu(var, cpu)	(*(__typeof__(&(var))) ((void *) &(var) + __per_cpu_offset[cpu]))
+#define this_cpu(var)		(var)
+
 /* like above but expressed as bitfields for more efficient access: */
 struct ia64_psr {
 	__u64 reserved0 : 1;
@@ -238,7 +250,7 @@
  * CPU type, hardware bug flags, and per-CPU state.  Frequently used
  * state comes earlier:
  */
-struct cpuinfo_ia64 {
+extern struct cpuinfo_ia64 {
 	/* irq_stat must be 64-bit aligned */
 	union {
 		struct {
@@ -248,12 +260,10 @@
 		__u64 irq_and_bh_counts;
 	} irq_stat;
 	__u32 softirq_pending;
-	__u32 phys_stacked_size_p8;	/* size of physical stacked registers + 8 */
 	__u64 itm_delta;	/* # of clock cycles between clock ticks */
 	__u64 itm_next;		/* interval timer mask value to use for next clock tick */
 	__u64 *pgd_quick;
 	__u64 *pmd_quick;
-	__u64 *pte_quick;
 	__u64 pgtable_cache_sz;
 	/* CPUID-derived information: */
 	__u64 ppn;
@@ -275,39 +285,22 @@
 	__u32 ptce_stride[2];
 	struct task_struct *ksoftirqd;	/* kernel softirq daemon for this CPU */
 #ifdef CONFIG_SMP
+	int cpu;
 	__u64 loops_per_jiffy;
 	__u64 ipi_count;
 	__u64 prof_counter;
 	__u64 prof_multiplier;
-	__u64 ipi_operation;
+	__u32 pfm_syst_wide;
+	__u32 pfm_dcr_pp;
 #endif
-#ifdef CONFIG_NUMA
-	struct cpuinfo_ia64 *cpu_data[NR_CPUS];
-#endif
-} __attribute__ ((aligned (PAGE_SIZE))) ;
+} cpu_info __per_cpu_data;
 
 /*
  * The "local" data pointer.  It points to the per-CPU data of the currently executing
  * CPU, much like "current" points to the per-task data of the currently executing task.
  */
-#define local_cpu_data		((struct cpuinfo_ia64 *) PERCPU_ADDR)
-
-/*
- * On NUMA systems, cpu_data for each cpu is allocated during cpu_init() & is allocated on
- * the node that contains the cpu. This minimizes off-node memory references.  cpu_data
- * for each cpu contains an array of pointers to the cpu_data structures of each of the
- * other cpus.
- *
- * On non-NUMA systems, cpu_data is a static array allocated at compile time.  References
- * to the cpu_data of another cpu is done by direct references to the appropriate entry of
- * the array.
- */
-#ifdef CONFIG_NUMA
-# define cpu_data(cpu)		local_cpu_data->cpu_data_ptrs[cpu]
-#else
-  extern struct cpuinfo_ia64 _cpu_data[NR_CPUS];
-# define cpu_data(cpu)		(&_cpu_data[cpu])
-#endif
+#define local_cpu_data		(&this_cpu(cpu_info))
+#define cpu_data(cpu)		(&per_cpu(cpu_info, cpu))
 
 extern void identify_cpu (struct cpuinfo_ia64 *);
 extern void print_cpu_info (struct cpuinfo_ia64 *);
@@ -343,8 +336,8 @@
 struct siginfo;
 
 struct thread_struct {
+	__u64 flags;			/* various thread flags (see IA64_THREAD_*) */
 	__u64 ksp;			/* kernel stack pointer */
-	unsigned long flags;		/* various flags */
 	__u64 map_base;			/* base address for get_unmapped_area() */
 	__u64 task_size;		/* limit for task size */
 	struct siginfo *siginfo;	/* current siginfo struct for ptrace() */
@@ -366,10 +359,12 @@
 #ifdef CONFIG_PERFMON
 	__u64 pmc[IA64_NUM_PMC_REGS];
 	__u64 pmd[IA64_NUM_PMD_REGS];
-	unsigned long pfm_must_block;	/* non-zero if we need to block on overflow */
+	unsigned long pfm_ovfl_block_reset;/* non-zero if we need to block or reset regs on ovfl */
 	void *pfm_context;		/* pointer to detailed PMU context */
-	atomic_t pfm_notifiers_check;	/* indicate if release_thread much check tasklist */
-# define INIT_THREAD_PM		{0, }, {0, }, 0, 0, {0},
+	atomic_t pfm_notifiers_check;	/* when >0, will cleanup ctx_notify_task in tasklist */
+	atomic_t pfm_owners_check;	/* when >0, will cleanup ctx_owner in tasklist */
+	void *pfm_smpl_buf_list;	/* list of sampling buffers to vfree */
+# define INIT_THREAD_PM		{0, }, {0, }, 0, NULL, {0}, {0}, NULL,
 #else
 # define INIT_THREAD_PM
 #endif
@@ -378,17 +373,17 @@
 	struct ia64_fpreg fph[96];	/* saved/loaded on demand */
 };
 
-#define INIT_THREAD {					\
-	0,				/* ksp */	\
-	0,				/* flags */	\
-	DEFAULT_MAP_BASE,		/* map_base */	\
-	DEFAULT_TASK_SIZE,		/* task_size */	\
-	0,				/* siginfo */	\
-	INIT_THREAD_IA32				\
-	INIT_THREAD_PM					\
-	{0, },				/* dbr */	\
-	{0, },				/* ibr */	\
-	{{{{0}}}, }			/* fph */	\
+#define INIT_THREAD {				\
+	flags:		0,			\
+	ksp:		0,			\
+	map_base:	DEFAULT_MAP_BASE,	\
+	task_size:	DEFAULT_TASK_SIZE,	\
+	siginfo:	0,			\
+	INIT_THREAD_IA32			\
+	INIT_THREAD_PM				\
+	dbr:		{0, },			\
+	ibr:		{0, },			\
+	fph:		{{{{0}}}, }		\
 }
 
 #define start_thread(regs,new_ip,new_sp) do {							\
@@ -398,6 +393,7 @@
 	ia64_psr(regs)->cpl = 3;	/* set user mode */					\
 	ia64_psr(regs)->ri = 0;		/* clear return slot number */				\
 	ia64_psr(regs)->is = 0;		/* IA-64 instruction set */				\
+	ia64_psr(regs)->sp = 1;		/* enforce secure perfmon */				\
 	regs->cr_iip = new_ip;									\
 	regs->ar_rsc = 0xf;		/* eager mode, privilege level 3 */			\
 	regs->ar_rnat = 0;									\
@@ -542,11 +538,6 @@
 extern void ia32_load_state (struct task_struct *task);
 #endif
 
-#ifdef CONFIG_PERFMON
-extern void ia64_save_pm_regs (struct task_struct *task);
-extern void ia64_load_pm_regs (struct task_struct *task);
-#endif
-
 #define ia64_fph_enable()	asm volatile (";; rsm psr.dfh;; srlz.d;;" ::: "memory");
 #define ia64_fph_disable()	asm volatile (";; ssm psr.dfh;; srlz.d;;" ::: "memory");
 
@@ -808,15 +799,12 @@
  * Note that the only way T can block is through a call to schedule() -> switch_to().
  */
 static inline unsigned long
-thread_saved_pc (struct thread_struct *t)
+thread_saved_pc (struct task_struct *t)
 {
 	struct unw_frame_info info;
 	unsigned long ip;
 
-	/* XXX ouch: Linus, please pass the task pointer to thread_saved_pc() instead! */
-	struct task_struct *p = (void *) ((unsigned long) t - IA64_TASK_THREAD_OFFSET);
-
-	unw_init_from_blocked_task(&info, p);
+	unw_init_from_blocked_task(&info, t);
 	if (unw_unwind(&info) < 0)
 		return 0;
 	unw_get_ip(&info, &ip);
@@ -828,16 +816,6 @@
  */
 #define current_text_addr() \
 	({ void *_pc; asm volatile ("mov %0=ip" : "=r" (_pc)); _pc; })
-
-#define THREAD_SIZE	IA64_STK_OFFSET
-/* NOTE: The task struct and the stacks are allocated together.  */
-#define alloc_task_struct() \
-        ((struct task_struct *) __get_free_pages(GFP_KERNEL, IA64_TASK_STRUCT_LOG_NUM_PAGES))
-#define free_task_struct(p)	free_pages((unsigned long)(p), IA64_TASK_STRUCT_LOG_NUM_PAGES)
-#define get_task_struct(tsk)	atomic_inc(&virt_to_page(tsk)->count)
-
-#define init_task	(init_task_union.task)
-#define init_stack	(init_task_union.stack)
 
 /*
  * Set the correctable machine check vector register
diff -Nru a/include/asm-ia64/ptrace.h b/include/asm-ia64/ptrace.h
--- a/include/asm-ia64/ptrace.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/ptrace.h	Fri Mar 15 17:51:03 2002
@@ -2,9 +2,9 @@
 #define _ASM_IA64_PTRACE_H
 
 /*
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1998, 1999 Stephane Eranian <eranian@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ *	Stephane Eranian <eranian@hpl.hp.com>
  *
  * 12/07/98	S. Eranian	added pt_regs & switch_stack
  * 12/21/98	D. Mosberger	updated to match latest code
@@ -39,7 +39,9 @@
  *	      |	(growing upwards)    |	 |
  *            |			     |	 |
  *	      +----------------------+	 |  ---	IA64_RBS_OFFSET
- *	      |			     |	 |  ^
+ *            |  struct thread_info  |	 |  ^
+ *	      +----------------------+	 |  |
+ *	      |			     |	 |  |
  *            |  struct task_struct  |	 |  |
  * current -> |			     |   |  |
  *	      +----------------------+ -------
@@ -58,19 +60,19 @@
  * (including register backing store and memory stack):
  */
 #if defined(CONFIG_IA64_PAGE_SIZE_4KB)
-# define IA64_TASK_STRUCT_LOG_NUM_PAGES		3
+# define KERNEL_STACK_SIZE_ORDER		3
 #elif defined(CONFIG_IA64_PAGE_SIZE_8KB)
-# define IA64_TASK_STRUCT_LOG_NUM_PAGES		2
+# define KERNEL_STACK_SIZE_ORDER		2
 #elif defined(CONFIG_IA64_PAGE_SIZE_16KB)
-# define IA64_TASK_STRUCT_LOG_NUM_PAGES		1
+# define KERNEL_STACK_SIZE_ORDER		1
 #else
-# define IA64_TASK_STRUCT_LOG_NUM_PAGES		0
+# define KERNEL_STACK_SIZE_ORDER		0
 #endif
 
-#define IA64_RBS_OFFSET			((IA64_TASK_SIZE + 15) & ~15)
-#define IA64_STK_OFFSET			((1 << IA64_TASK_STRUCT_LOG_NUM_PAGES)*PAGE_SIZE)
+#define IA64_RBS_OFFSET			((IA64_TASK_SIZE + IA64_THREAD_INFO_SIZE + 15) & ~15)
+#define IA64_STK_OFFSET			((1 << KERNEL_STACK_SIZE_ORDER)*PAGE_SIZE)
 
-#define INIT_TASK_SIZE			IA64_STK_OFFSET
+#define KERNEL_STACK_SIZE		IA64_STK_OFFSET
 
 #ifndef __ASSEMBLY__
 
@@ -247,8 +249,34 @@
 
 #endif /* !__KERNEL__ */
 
+/* pt_all_user_regs is used for PTRACE_GETREGS PTRACE_SETREGS */
+struct pt_all_user_regs {
+	unsigned long nat;
+	unsigned long cr_iip;
+	unsigned long cfm;
+	unsigned long cr_ipsr;
+	unsigned long pr;
+
+	unsigned long gr[32];
+	unsigned long br[8];
+	unsigned long ar[128];
+	struct ia64_fpreg fr[128];
+};
+
 #endif /* !__ASSEMBLY__ */
 
+/* indices to application-registers array in pt_all_user_regs */
+#define PT_AUR_RSC	16
+#define PT_AUR_BSP	17
+#define PT_AUR_BSPSTORE	18
+#define PT_AUR_RNAT	19
+#define PT_AUR_CCV	32
+#define PT_AUR_UNAT	36
+#define PT_AUR_FPSR	40
+#define PT_AUR_PFS	64
+#define PT_AUR_LC	65
+#define PT_AUR_EC	66
+
 /*
  * The numbers chosen here are somewhat arbitrary but absolutely MUST
  * not overlap with any of the number assigned in <linux/ptrace.h>.
@@ -256,5 +284,12 @@
 #define PTRACE_SINGLEBLOCK	12	/* resume execution until next branch */
 #define PTRACE_GETSIGINFO	13	/* get child's siginfo structure */
 #define PTRACE_SETSIGINFO	14	/* set child's siginfo structure */
+#define PTRACE_GETREGS		18	/* get all registers (pt_all_user_regs) in one shot */
+#define PTRACE_SETREGS		19	/* set all registers (pt_all_user_regs) in one shot */
+
+#define PTRACE_SETOPTIONS	21
+
+/* options set using PTRACE_SETOPTIONS */
+#define PTRACE_O_TRACESYSGOOD	0x00000001
 
 #endif /* _ASM_IA64_PTRACE_H */
diff -Nru a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
--- a/include/asm-ia64/sal.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sal.h	Fri Mar 15 17:51:03 2002
@@ -8,11 +8,14 @@
  * Abstraction Layer".
  *
  * Copyright (C) 2001 Intel
+ * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
  * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
  * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
  * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
  *
+ * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
+ *		    revision of the SAL spec.
  * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
  *                  revision of the SAL spec.
  * 99/09/29 davidm	Updated for SAL 2.6.
@@ -149,6 +152,7 @@
 #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK		(1 << 0)
 #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT	(1 << 1)
 #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT	(1 << 2)
+#define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT	 	(1 << 3)
 
 typedef struct ia64_sal_desc_platform_feature {
 	u8 type;
@@ -227,6 +231,10 @@
 	SAL_VECTOR_OS_BOOT_RENDEZ	= 2
 };
 
+/* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
+#define	SAL_MC_PARAM_RZ_ALWAYS		0x1
+#define	SAL_MC_PARAM_BINIT_ESCALATE	0x10
+
 /*
 ** Definition of the SAL Error Log from the SAL spec
 */
@@ -515,12 +523,12 @@
     {
         u16 vendor_id;
         u16 device_id;
-        u16 class_code;
+	u8  class_code[3];
         u8  func_num;
         u8  dev_num;
         u8  bus_num;
         u8  seg_num;
-        u8  reserved[6];
+        u8  reserved[5];
     }               comp_info;
     u32             num_mem_regs;
     u32             num_io_regs;
@@ -775,5 +783,7 @@
 		*scratch_buf_size_needed = isrv.v1;
 	return isrv.status;
 }
+
+extern unsigned long sal_platform_features;
 
 #endif /* _ASM_IA64_PAL_H */
diff -Nru a/include/asm-ia64/scatterlist.h b/include/asm-ia64/scatterlist.h
--- a/include/asm-ia64/scatterlist.h	Fri Mar 15 17:51:00 2002
+++ b/include/asm-ia64/scatterlist.h	Fri Mar 15 17:51:00 2002
@@ -2,7 +2,7 @@
 #define _ASM_IA64_SCATTERLIST_H
 
 /*
- * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
+ * Copyright (C) 1998-1999, 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
@@ -12,7 +12,6 @@
 	/* These two are only valid if ADDRESS member of this struct is NULL.  */
 	struct page *page;
 	unsigned int offset;
-
 	unsigned int length;	/* buffer length */
 };
 
diff -Nru a/include/asm-ia64/sigcontext.h b/include/asm-ia64/sigcontext.h
--- a/include/asm-ia64/sigcontext.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sigcontext.h	Fri Mar 15 17:51:01 2002
@@ -56,7 +56,9 @@
 	unsigned long		sc_rbs_base;	/* NULL or new base of sighandler's rbs */
 	unsigned long		sc_loadrs;	/* see description above */
 
-	unsigned long		sc_rsvd[14];	/* reserved for future use */
+	unsigned long		sc_ar25;	/* rsvd for scratch use */
+	unsigned long		sc_ar26;	/* rsvd for scratch use */
+	unsigned long		sc_rsvd[12];	/* reserved for future use */
 	/*
 	 * The mask must come last so we can increase _NSIG_WORDS
 	 * without breaking binary compatibility.
diff -Nru a/include/asm-ia64/siginfo.h b/include/asm-ia64/siginfo.h
--- a/include/asm-ia64/siginfo.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/siginfo.h	Fri Mar 15 17:51:02 2002
@@ -2,8 +2,8 @@
 #define _ASM_IA64_SIGINFO_H
 
 /*
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/types.h>
@@ -57,7 +57,7 @@
 		struct {
 			void *_addr;		/* faulting insn/memory ref. */
 			int _imm;		/* immediate value for "break" */
-			int _pad0;
+			unsigned int _flags;	/* see below */
 			unsigned long _isr;	/* isr */
 		} _sigfault;
 
@@ -70,7 +70,7 @@
 		struct {
 			pid_t _pid;		/* which child */
 			uid_t _uid;		/* sender's uid */
-			unsigned long _pfm_ovfl_counters; /* which PMU counter overflowed */
+			unsigned long _pfm_ovfl_counters[4]; /* which PMU counter overflowed */
 		} _sigprof;
 	} _sifields;
 } siginfo_t;
@@ -88,12 +88,23 @@
 #define si_ptr		_sifields._rt._sigval.sival_ptr
 #define si_addr		_sifields._sigfault._addr
 #define si_imm		_sifields._sigfault._imm	/* as per UNIX SysV ABI spec */
-#define si_isr		_sifields._sigfault._isr	/* valid if si_code==FPE_FLTxxx */
+#define si_flags	_sifields._sigfault._flags
+/*
+ * si_isr is valid for SIGILL, SIGFPE, SIGSEGV, SIGBUS, and SIGTRAP provided that
+ * si_code is non-zero and __ISR_VALID is set in si_flags.
+ */
+#define si_isr		_sifields._sigfault._isr
 #define si_band		_sifields._sigpoll._band
 #define si_fd		_sifields._sigpoll._fd
 #define si_pfm_ovfl	_sifields._sigprof._pfm_ovfl_counters
 
 /*
+ * Flag values for si_flags:
+ */
+#define __ISR_VALID_BIT	0
+#define __ISR_VALID	(1 << __ISR_VALID_BIT)
+
+/*
  * si_code values
  * Positive values for kernel-generated signals.
  */
@@ -119,12 +130,13 @@
 
 #define SI_USER		0		/* sent by kill, sigsend, raise */
 #define SI_KERNEL	0x80		/* sent by the kernel from somewhere */
-#define SI_QUEUE	-1		/* sent by sigqueue */
+#define SI_QUEUE	(-1)		/* sent by sigqueue */
 #define SI_TIMER __SI_CODE(__SI_TIMER,-2) /* sent by timer expiration */
-#define SI_MESGQ	-3		/* sent by real time mesq state change */
-#define SI_ASYNCIO	-4		/* sent by AIO completion */
-#define SI_SIGIO	-5		/* sent by queued SIGIO */
-#define SI_TKILL	-6		/* sent by tkill system call */
+#define SI_MESGQ	(-3)		/* sent by real time mesq state change */
+#define SI_ASYNCIO	(-4)		/* sent by AIO completion */
+#define SI_SIGIO	(-5)		/* sent by queued SIGIO */
+#define SI_TKILL	(-6)		/* sent by tkill system call */
+#define SI_DETHREAD	(-7)		/* sent by execve() killing subsidiary threads */
 
 #define SI_FROMUSER(siptr)	((siptr)->si_code <= 0)
 #define SI_FROMKERNEL(siptr)	((siptr)->si_code > 0)
diff -Nru a/include/asm-ia64/signal.h b/include/asm-ia64/signal.h
--- a/include/asm-ia64/signal.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/signal.h	Fri Mar 15 17:51:01 2002
@@ -115,6 +115,7 @@
 #define SA_PROBE		SA_ONESHOT
 #define SA_SAMPLE_RANDOM	SA_RESTART
 #define SA_SHIRQ		0x04000000
+#define SA_PERCPU_IRQ		0x02000000
 
 #endif /* __KERNEL__ */
 
diff -Nru a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
--- a/include/asm-ia64/smp.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/smp.h	Fri Mar 15 17:51:03 2002
@@ -3,7 +3,7 @@
  *
  * Copyright (C) 1999 VA Linux Systems
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
- * Copyright (C) 2001 Hewlett-Packard Co
+ * Copyright (C) 2001-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #ifndef _ASM_IA64_SMP_H
@@ -27,7 +27,7 @@
 #define SMP_IRQ_REDIRECTION	(1 << 0)
 #define SMP_IPI_REDIRECTION	(1 << 1)
 
-#define smp_processor_id()	(current->processor)
+#define smp_processor_id()	(current_thread_info()->cpu)
 
 extern struct smp_boot_data {
 	int cpu_count;
@@ -110,17 +110,13 @@
 
 #define NO_PROC_ID		0xffffffff	/* no processor magic marker */
 
-/*
- * Extra overhead to move a task from one cpu to another (due to TLB and cache misses).
- * Expressed in "negative nice value" units (larger number means higher priority/penalty).
- */
-#define PROC_CHANGE_PENALTY	20
-
 extern void __init init_smp_config (void);
 extern void smp_do_timer (struct pt_regs *regs);
 
 extern int smp_call_function_single (int cpuid, void (*func) (void *info), void *info,
 				     int retry, int wait);
+extern void smp_send_reschedule (int cpu);
+extern void smp_send_reschedule_all (void);
 
 
 #endif /* CONFIG_SMP */
diff -Nru a/include/asm-ia64/smplock.h b/include/asm-ia64/smplock.h
--- a/include/asm-ia64/smplock.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/smplock.h	Fri Mar 15 17:51:01 2002
@@ -12,29 +12,36 @@
 
 extern spinlock_t kernel_flag;
 
-#define kernel_locked()		spin_is_locked(&kernel_flag)
+#ifdef CONFIG_SMP
+# define kernel_locked()	spin_is_locked(&kernel_flag)
+# define check_irq_holder(cpu)			\
+do {						\
+	if (global_irq_holder == (cpu))		\
+		BUG();				\
+} while (0)
+#else
+# define kernel_locked()	(1)
+#endif
 
 /*
  * Release global kernel lock and global interrupt lock
  */
-static __inline__ void
-release_kernel_lock(struct task_struct *task, int cpu)
-{
-	if (task->lock_depth >= 0)
-		spin_unlock(&kernel_flag);
-	release_irqlock(cpu);
-	__sti();
-}
+#define release_kernel_lock(task, cpu)		\
+do {						\
+	if (unlikely(task->lock_depth >= 0)) {	\
+		spin_unlock(&kernel_flag);	\
+		check_irq_holder(cpu);		\
+	}					\
+} while (0)
 
 /*
  * Re-acquire the kernel lock
  */
-static __inline__ void
-reacquire_kernel_lock(struct task_struct *task)
-{
-	if (task->lock_depth >= 0)
-		spin_lock(&kernel_flag);
-}
+#define reacquire_kernel_lock(task)		\
+do {						\
+	if (unlikely(task->lock_depth >= 0))	\
+		spin_lock(&kernel_flag);	\
+} while (0)
 
 /*
  * Getting the big kernel lock.
diff -Nru a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
--- a/include/asm-ia64/sn/addrs.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/addrs.h	Fri Mar 15 17:51:02 2002
@@ -1,40 +1,42 @@
-/* $Id$
+
+/*
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
+ * Copyright (c) 1992-1999,2001 Silicon Graphics, Inc.  All rights reserved.
  */
-#ifndef _ASM_SN_ADDRS_H
-#define _ASM_SN_ADDRS_H
 
-#include <linux/config.h>
 
-#if _LANGUAGE_C
-#include <linux/types.h>
-#endif /* _LANGUAGE_C */
-
-#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-#include <asm/addrspace.h>
-#include <asm/reg.h>
-#include <asm/sn/kldir.h>
-#endif	/* CONFIG_IA64_SGI_SN1 */
+#ifndef _ASM_IA64_SN_ADDRS_H
+#define _ASM_IA64_SN_ADDRS_H
+
+#include <linux/config.h>
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined (CONFIG_IA64_SGI_SN1)
 #include <asm/sn/sn1/addrs.h>
-#endif
+#elif defined (CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/addrs.h>
+#else
+#error <<<BOMB! addrs.h defined only for SN1, or SN2 >>>
+#endif /* !SN1 && !SN2 */
 
+#ifndef __ASSEMBLY__
+#include <asm/sn/types.h>
+#endif 
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define PS_UINT_CAST		(__psunsigned_t)
 #define UINT64_CAST		(uint64_t)
-
+#ifdef CONFIG_IA64_SGI_SN2
+#define HUBREG_CAST		(volatile mmr_t *)
+#else
 #define HUBREG_CAST		(volatile hubreg_t *)
+#endif
 
-#elif _LANGUAGE_ASSEMBLY
+#elif __ASSEMBLY__
 
 #define PS_UINT_CAST
 #define UINT64_CAST
@@ -43,18 +45,6 @@
 #endif
 
 
-#define NASID_GET_META(_n)	((_n) >> NASID_LOCAL_BITS)
-#if defined CONFIG_SGI_IP35 || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define NASID_GET_LOCAL(_n)	((_n) & 0x7f)
-#endif
-#define NASID_MAKE(_m, _l)	(((_m) << NASID_LOCAL_BITS) | (_l))
-
-#define NODE_ADDRSPACE_MASK	(NODE_ADDRSPACE_SIZE - 1)
-#define TO_NODE_ADDRSPACE(_pa)	(UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
-
-#define CHANGE_ADDR_NASID(_pa, _nasid)	\
-		((UINT64_CAST (_pa) & ~NASID_MASK) | \
-		 (UINT64_CAST(_nasid) <<  NASID_SHFT))
 
 
 /*
@@ -62,7 +52,11 @@
  * node's address space.
  */
 
+#ifdef CONFIG_IA64_SGI_SN2	/* SN2 has an extra AS field between node offset and node id (nasid) */
+#define NODE_OFFSET(_n)		(UINT64_CAST (_n) << NASID_SHFT)
+#else
 #define NODE_OFFSET(_n)		(UINT64_CAST (_n) << NODE_SIZE_BITS)
+#endif
 
 #define NODE_CAC_BASE(_n)	(CAC_BASE   + NODE_OFFSET(_n))
 #define NODE_HSPEC_BASE(_n)	(HSPEC_BASE + NODE_OFFSET(_n))
@@ -118,11 +112,6 @@
 /*
  * The following define the major position-independent aliases used
  * in SN.
- *	UALIAS -- 256MB in size, reads in the UALIAS result in
- *			uncached references to the memory of the reader's node.
- *	CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
- *			depending on which CPU does the access to provide
- *			all CPUs with unique uncached memory at low addresses.
  *	LBOOT  -- 256MB in size, reads in the LBOOT area result in
  *			uncached references to the local hub's boot prom and
  *			other directory-bus connected devices.
@@ -130,17 +119,7 @@
  *			references to the local hub's registers.
  */
 
-#define UALIAS_BASE		HSPEC_BASE
-#define UALIAS_SIZE		0x10000000	/* 256 Megabytes */
-#define CPU_UALIAS		0x20000		/* 128 Kilobytes */
-#define UALIAS_CPU_SIZE		(CPU_UALIAS / CPUS_PER_NODE)
-#define UALIAS_LIMIT		(UALIAS_BASE + UALIAS_SIZE)
-
-/*
- * The bottom of ualias space is flipped depending on whether you're
- * processor 0 or 1 within a node.
- */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined CONFIG_IA64_SGI_SN1
 #define LREG_BASE		(HSPEC_BASE + 0x10000000)
 #define LREG_SIZE		0x8000000  /* 128 MB */
 #define LREG_LIMIT		(LREG_BASE + LREG_SIZE)
@@ -151,7 +130,11 @@
 #endif
 
 #define	HUB_REGISTER_WIDGET	1
+#ifdef CONFIG_IA64_SGI_SN2
+#define IALIAS_BASE		LOCAL_SWIN_BASE(HUB_REGISTER_WIDGET)
+#else
 #define IALIAS_BASE		NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
+#endif
 #define IALIAS_SIZE		0x800000	/* 8 Megabytes */
 #define IS_IALIAS(_a)		(((_a) >= IALIAS_BASE) &&		\
 				 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
@@ -160,7 +143,7 @@
  * Macro for referring to Hub's RBOOT space
  */
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined CONFIG_IA64_SGI_SN1
 
 #define NODE_LREG_BASE(_n)	(NODE_HSPEC_BASE(_n) + 0x30000000)
 #define NODE_LREG_LIMIT(_n)	(NODE_LREG_BASE(_n) + LREG_SIZE)
@@ -172,168 +155,6 @@
 
 #endif
 
-/*
- * Macros for referring the Hub's back door space
- *
- *   These macros correctly process addresses in any node's space.
- *   WARNING: They won't work in assembler.
- *
- *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
- *                  entry corresponding to a physical (Cac or Uncac) address.
- *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
- *   BDPRT_ENTRY    returns the address of the double-word protection entry
- *                  corresponding to the page containing the physical address.
- *   BDPRT_ENTRY_S  Stores the value into the protection entry.
- *   BDPRT_ENTRY_L  Load the value from the protection entry.
- *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
- *                  double-word at a specified physical address.
- *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
- *                  quad-word at a specified physical address.
- */
-#define NODE_BDOOR_BASE(_n)	(NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
-
-#define NODE_BDECC_BASE(_n)	(NODE_BDOOR_BASE(_n))
-#define NODE_BDDIR_BASE(_n)	(NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-/*
- * Bedrock's directory entries are a single word:  no low/high
- */
-
-#define BDDIR_ENTRY(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE * 7 / 8  		    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDDIR_UPPER_MASK)
-
-#ifdef BRINGUP
-        /* minimize source changes by mapping *_LO() & *_HI()   */
-#define BDDIR_ENTRY_LO(_pa)     BDDIR_ENTRY(_pa)
-#define BDDIR_ENTRY_HI(_pa)     BDDIR_ENTRY(_pa)
-#endif /* BRINGUP */
-
-#define BDDIR_PAGE_MASK		(BDDIR_UPPER_MASK & 0x7ffff << 11)
-#define BDDIR_PAGE_BASE_MASK	(UINT64_CAST 0xfffffffffffff800)
-
-#ifdef _LANGUAGE_C
-
-#define BDPRT_ENTRY_ADDR(_pa, _rgn)      ((uint64_t *) ( (HSPEC_BASE +       \
-                                 NODE_ADDRSPACE_SIZE * 7 / 8 + 0x408)       | \
-                                (UINT64_CAST (_pa)      & NASID_MASK)        | \
-                                (UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK)   | \
-                                (UINT64_CAST (_pa) >> 3 & 0x3 << 4)          | \
-                                ((_rgn) & 0x1e) << 5))
-
-static __inline uint64_t BDPRT_ENTRY_L(paddr_t pa,uint32_t rgn) {
-	uint64_t word=*BDPRT_ENTRY_ADDR(pa,rgn);
-
-	if(rgn&0x20)			/*If the region is > 32, move it down*/
-		word = word >> 32;
-	if(rgn&0x1)			/*If the region is odd, get that part */
-		word = word >> 16;
-	word = word & 0xffff;		/*Get the 16 bits we are interested in*/
-
-	return word;
-}
-
-static __inline void BDPRT_ENTRY_S(paddr_t pa,uint32_t rgn,uint64_t val) {
-        uint64_t *addr=(uint64_t *)BDPRT_ENTRY_ADDR(pa,rgn);
-        uint64_t word,mask;
-
-        word=*addr;
-	mask=0;
-	if(rgn&0x1) {
-		mask|=0x0000ffff0000ffff;
-		val=val<<16;
-	}
-	else
-		mask|=0xffff0000ffff0000;
-	if(rgn&0x20) {
-		mask|=0x00000000ffffffff;
-		val=val<<32;
-	}
-	else
-		mask|=0xffffffff00000000;
-	word &= mask;
-	word |= val;
-
-	*(addr++)=word;
-	addr++;
-        *(addr++)=word;
-        addr++;
-        *(addr++)=word;
-        addr++;
-        *addr=word;
-}
-#endif	/*_LANGUAGE_C*/
-
-#define BDCNT_ENTRY(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE * 7 / 8 + 0x8    	    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDDIR_PAGE_MASK   | \
-				 UINT64_CAST (_pa) >> 3 & 0x3 << 4)
-
-
-#ifdef    BRINGUP
-  /* little endian packing of ecc bytes requires a swizzle */ 
-  /* this is problemmatic for memory_init_ecc              */
-#endif /* BRINGUP */
-#define BDECC_ENTRY(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE * 5 / 8 		    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
-				   		        ^ 0x7ULL)
-
-#define BDECC_SCRUB(_pa)	(HSPEC_BASE +				      \
-				  NODE_ADDRSPACE_SIZE / 2 		    | \
-				 UINT64_CAST (_pa)	& NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
-				   		        ^ 0x7ULL)
-
-  /* address for Halfword backdoor ecc access. Note that   */
-  /* ecc bytes are packed in little endian order           */
-#define BDECC_ENTRY_H(_pa)	(HSPEC_BASE +                                 \
-				  NODE_ADDRSPACE_SIZE * 5 / 8		    | \
-				 UINT64_CAST (_pa)	 & NASID_MASK	    | \
-				 UINT64_CAST (_pa) >> 3 & BDECC_UPPER_MASK    \
-				   		        ^ 0x6ULL)
-
-/*
- * Macro to convert a back door directory, protection, page counter, or ecc
- * address into the raw physical address of the associated cache line
- * or protection page.
- */
-
-#define BDDIR_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK            | \
-				 (UINT64_CAST (_ba) & BDDIR_UPPER_MASK) << 3)
-
-#ifdef BRINGUP
-/*
- * This can't be done since there are 4 entries per address so you'd end up
- * mapping back to 4 different physical addrs.
- */
-  
-#define BDPRT_TO_MEM(_ba) 	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \
-				 (UINT64_CAST (_ba) & 0x3 << 4) << 3)
-#endif
-
-#define BDCNT_TO_MEM(_ba) 	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 (UINT64_CAST (_ba) & BDDIR_PAGE_MASK) << 3 | \
-				 (UINT64_CAST (_ba) & 0x3 << 4) << 3)
-
-#define BDECC_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 ((UINT64_CAST (_ba) ^ 0x7ULL)                \
-				                    & BDECC_UPPER_MASK) << 3 )
-
-#define BDECC_H_TO_MEM(_ba)	(UINT64_CAST  (_ba) & NASID_MASK	    | \
-				 ((UINT64_CAST (_ba) ^ 0x6ULL)                \
-				                    & BDECC_UPPER_MASK) << 3 )
-
-#define BDADDR_IS_DIR(_ba)	((UINT64_CAST  (_ba) & 0x8) == 0)
-#define BDADDR_IS_PRT(_ba)	((UINT64_CAST  (_ba) & 0x408) == 0x408)
-#define BDADDR_IS_CNT(_ba)	((UINT64_CAST  (_ba) & 0x8) == 0x8)
-
-#endif /* CONFIG_SGI_IP35 */
-
 
 /*
  * The following macros produce the correct base virtual address for
@@ -344,6 +165,36 @@
  * for _x.
  */
 
+
+#ifdef CONFIG_IA64_SGI_SN2
+/*
+ * SN2 has II mmr's located inside small window space like SN0 & SN1,
+ * but has all other non-II mmr's located at the top of big window
+ * space, unlike SN0 & SN1.
+ */
+#define LOCAL_HUB_BASE(_x)	(LOCAL_MMR_ADDR(_x) | (((~(_x)) & BWIN_TOP)>>8))
+#define REMOTE_HUB_BASE(_x)						\
+        (UNCACHED | GLOBAL_MMR_SPACE |                                  \
+        (((~(_x)) & BWIN_TOP)>>8)    |                                       \
+        (((~(_x)) & BWIN_TOP)>>9)    | (_x))
+
+#define LOCAL_HUB(_x) (HUBREG_CAST LOCAL_HUB_BASE(_x))
+#define REMOTE_HUB(_n, _x)						\
+	(HUBREG_CAST (REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT))))
+
+#else	/* not CONFIG_IA64_SGI_SN2 */
+
+#define LOCAL_HUB(_x)		(HUBREG_CAST (IALIAS_BASE + (_x)))
+#define REMOTE_HUB(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
+					      0x800000 + (_x)))
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define LOCAL_HSPEC(_x)		(HUBREG_CAST (LREG_BASE + (_x)))
+#define REMOTE_HSPEC(_n, _x)		(HUBREG_CAST (RREG_BASE(_n) + (_x)))
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+
 /*
  * WARNING:
  *	When certain Hub chip workaround are defined, it's not sufficient
@@ -352,17 +203,29 @@
  *	Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
  *	They're always safe.
  */
+#ifdef CONFIG_IA64_SGI_SN2
+#define LOCAL_HUB_ADDR(_x)							\
+	(((_x) & BWIN_TOP) ? (HUBREG_CAST (LOCAL_MMR_ADDR(_x)))		\
+	: (HUBREG_CAST (IALIAS_BASE + (_x))))
+#define REMOTE_HUB_ADDR(_n, _x)						\
+	(((_x) & BWIN_TOP) ? (HUBREG_CAST (GLOBAL_MMR_ADDR(_n, _x)))	\
+	: (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x))))
+#else
 #define LOCAL_HUB_ADDR(_x)	(HUBREG_CAST (IALIAS_BASE + (_x)))
 #define REMOTE_HUB_ADDR(_n, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
 					      0x800000 + (_x)))
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#endif
+#if CONFIG_IA64_SGI_SN1
 #define REMOTE_HUB_PI_ADDR(_n, _sn, _x)	(HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +	\
 					      0x800000 + PIREG(_x, _sn)))
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN1
 #define LOCAL_HSPEC_ADDR(_x)		(HUBREG_CAST (LREG_BASE + (_x)))
 #define REMOTE_HSPEC_ADDR(_n, _x)	(HUBREG_CAST (RREG_BASE(_n) + (_x)))
-#endif /* CONFIG_SGI_IP35 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define HUB_L(_a)			*(_a)
 #define	HUB_S(_a, _d)			*(_a) = (_d)
@@ -374,14 +237,14 @@
 #define REMOTE_HUB_PI_L(_n, _sn, _r)	HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
 #define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#ifdef CONFIG_IA64_SGI_SN1
 #define LOCAL_HSPEC_L(_r)	     HUB_L(LOCAL_HSPEC_ADDR(_r))
 #define LOCAL_HSPEC_S(_r, _d)	     HUB_S(LOCAL_HSPEC_ADDR(_r), (_d))
 #define REMOTE_HSPEC_L(_n, _r)	     HUB_L(REMOTE_HSPEC_ADDR((_n), (_r)))
 #define REMOTE_HSPEC_S(_n, _r, _d)   HUB_S(REMOTE_HSPEC_ADDR((_n), (_r)), (_d))
-#endif /* CONFIG_SGI_IP35 */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /*
  * The following macros are used to get to a hub/bridge register, given
@@ -410,13 +273,8 @@
 #define ARCS_SPB_SIZE		0x0400
 
 #define KLDIR_OFFSET		0x2000
-#ifndef __ia64
 #define KLDIR_ADDR(nasid)						\
-	TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
-#else
-#define KLDIR_ADDR(nasid)                                               \
-        TO_NODE_CAC((nasid), KLDIR_OFFSET)
-#endif
+	TO_NODE_CAC((nasid), KLDIR_OFFSET)
 #define KLDIR_SIZE		0x0400
 
 
@@ -439,7 +297,7 @@
 #define	KLI_KERN_XP		8
 #define	KLI_KERN_PARTID		9
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define KLD_BASE(nasid)		((kldir_ent_t *) KLDIR_ADDR(nasid))
 #define KLD_LAUNCH(nasid)	(KLD_BASE(nasid) + KLI_LAUNCH)
@@ -453,85 +311,23 @@
 #define	KLD_KERN_XP(nasid)	(KLD_BASE(nasid) + KLI_KERN_XP)
 #define	KLD_KERN_PARTID(nasid)	(KLD_BASE(nasid) + KLI_KERN_PARTID)
 
-#define LAUNCH_OFFSET(nasid, slice)					\
-	(KLD_LAUNCH(nasid)->offset +					\
-	 KLD_LAUNCH(nasid)->stride * (slice))
-#define LAUNCH_ADDR(nasid, slice)					\
-	TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
-#define LAUNCH_SIZE(nasid)	KLD_LAUNCH(nasid)->size
-
-#define NMI_OFFSET(nasid, slice)					\
-	(KLD_NMI(nasid)->offset +					\
-	 KLD_NMI(nasid)->stride * (slice))
-#define NMI_ADDR(nasid, slice)						\
-	TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
-#define NMI_SIZE(nasid)	KLD_NMI(nasid)->size
-
+#ifndef CONFIG_IA64_SGI_SN2
 #define KLCONFIG_OFFSET(nasid)	KLD_KLCONFIG(nasid)->offset
+#else
+#define KLCONFIG_OFFSET(nasid) \
+	ia64_sn_get_klconfig_addr(nasid)
+#endif /* CONFIG_IA64_SGI_SN2 */
+
 #define KLCONFIG_ADDR(nasid)						\
-	TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
+	TO_NODE_CAC((nasid), KLCONFIG_OFFSET(nasid))
 #define KLCONFIG_SIZE(nasid)	KLD_KLCONFIG(nasid)->size
 
 #define GDA_ADDR(nasid)		KLD_GDA(nasid)->pointer
 #define GDA_SIZE(nasid)		KLD_GDA(nasid)->size
 
-#define SYMMON_STK_OFFSET(nasid, slice)					\
-	(KLD_SYMMON_STK(nasid)->offset +				\
-	 KLD_SYMMON_STK(nasid)->stride * (slice))
-#define SYMMON_STK_STRIDE(nasid)	KLD_SYMMON_STK(nasid)->stride
-
-#define SYMMON_STK_ADDR(nasid, slice)					\
-	TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
-
-#define SYMMON_STK_SIZE(nasid)	KLD_SYMMON_STK(nasid)->stride
-
-#define SYMMON_STK_END(nasid)	(SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
-
-/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
- * relocatable program
- */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-/* update master.d/sn1_elspec.dbg, SN1/addrs.h/DEBUGUNIX_ADDR, and
- * DBGLOADADDR in symmon's Makefile when changing this */
-#define UNIX_DEBUG_LOADADDR     0x310000
-#elif defined(SN0XXL)
-#define UNIX_DEBUG_LOADADDR     0x360000
-#else
-#define	UNIX_DEBUG_LOADADDR	0x300000
-#endif
-#define	SYMMON_LOADADDR(nasid)						\
-	TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
-
-#define FREEMEM_OFFSET(nasid)	KLD_FREEMEM(nasid)->offset
-#define FREEMEM_ADDR(nasid)	SYMMON_STK_END(nasid)
-/*
- * XXX
- * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
- * Also, it should take into account what prom thinks to be a safe
- * address
-	PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
- */
-#define FREEMEM_SIZE(nasid)	KLD_FREEMEM(nasid)->size
-
-#define PI_ERROR_OFFSET(nasid)	KLD_PI_ERROR(nasid)->offset
-#define PI_ERROR_ADDR(nasid)						\
-	TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
-#define PI_ERROR_SIZE(nasid)	KLD_PI_ERROR(nasid)->size
-
 #define NODE_OFFSET_TO_K0(_nasid, _off)					\
 	(PAGE_OFFSET | NODE_OFFSET(_nasid) | (_off))
-#define K0_TO_NODE_OFFSET(_k0addr)					\
-	((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
-
-#define KERN_VARS_ADDR(nasid)	KLD_KERN_VARS(nasid)->pointer
-#define KERN_VARS_SIZE(nasid)	KLD_KERN_VARS(nasid)->size
-
-#define	KERN_XP_ADDR(nasid)	KLD_KERN_XP(nasid)->pointer
-#define	KERN_XP_SIZE(nasid)	KLD_KERN_XP(nasid)->size
-
-#define GPDA_ADDR(nasid)	TO_NODE_CAC(nasid, GPDA_OFFSET)
-
-#endif /* _LANGUAGE_C */
 
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_ADDRS_H */
+#endif /* _ASM_IA64_SN_ADDRS_H */
diff -Nru a/include/asm-ia64/sn/agent.h b/include/asm-ia64/sn/agent.h
--- a/include/asm-ia64/sn/agent.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,47 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * This file has definitions for the hub and snac interfaces.
- *
- * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_SGI_SN_AGENT_H
-#define _ASM_SGI_SN_AGENT_H
-
-#include <linux/config.h>
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-//#include <asm/sn/io.h>
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/bedrock.h>
-#endif	/* CONFIG_SGI_IP35 */
-
-/*
- * NIC register macros
- */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define HUB_NIC_ADDR(_cpuid) 						   \
-	REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cputocnode(_cpuid)),       \
-		LB_MICROLAN_CTL)
-#endif
-
-#define SET_HUB_NIC(_my_cpuid, _val) 				  	   \
-	(HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
-
-#define SET_MY_HUB_NIC(_v) 					           \
-	SET_HUB_NIC(cpuid(), (_v))
-
-#define GET_HUB_NIC(_my_cpuid) 						   \
-	(HUB_L(HUB_NIC_ADDR(_my_cpuid)))
-
-#define GET_MY_HUB_NIC() 						   \
-	GET_HUB_NIC(cpuid())
-
-#endif /* _ASM_SGI_SN_AGENT_H */
diff -Nru a/include/asm-ia64/sn/alenlist.h b/include/asm-ia64/sn/alenlist.h
--- a/include/asm-ia64/sn/alenlist.h	Fri Mar 15 17:51:00 2002
+++ b/include/asm-ia64/sn/alenlist.h	Fri Mar 15 17:51:00 2002
@@ -4,11 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_ALENLIST_H
-#define _ASM_SN_ALENLIST_H
+#ifndef _ASM_IA64_SN_ALENLIST_H
+#define _ASM_IA64_SN_ALENLIST_H
+
+#include <linux/types.h>
 
 /* Definition of Address/Length List */
 
@@ -51,7 +52,7 @@
 
 
 /* Return codes from alenlist routines.  */
-#define ALENLIST_FAILURE -1
+#define ALENLIST_FAILURE (-1)
 #define ALENLIST_SUCCESS 0
 
 
@@ -201,4 +202,4 @@
 }
 #endif
 
-#endif /* _ASM_SN_ALENLIST_H */
+#endif /* _ASM_IA64_SN_ALENLIST_H */
diff -Nru a/include/asm-ia64/sn/arc/hinv.h b/include/asm-ia64/sn/arc/hinv.h
--- a/include/asm-ia64/sn/arc/hinv.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/arc/hinv.h	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
diff -Nru a/include/asm-ia64/sn/arc/types.h b/include/asm-ia64/sn/arc/types.h
--- a/include/asm-ia64/sn/arc/types.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/arc/types.h	Fri Mar 15 17:51:03 2002
@@ -4,7 +4,7 @@
  * for more details.
  *
  * Copyright 1999 Ralf Baechle (ralf@gnu.org)
- * Copyright 1999 Silicon Graphics, Inc.
+ * Copyright 1999,2001 Silicon Graphics, Inc.
  */
 #ifndef _ASM_SN_ARC_TYPES_H
 #define _ASM_SN_ARC_TYPES_H
diff -Nru a/include/asm-ia64/sn/arch.h b/include/asm-ia64/sn/arch.h
--- a/include/asm-ia64/sn/arch.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/arch.h	Fri Mar 15 17:51:02 2002
@@ -6,180 +6,50 @@
  *
  * SGI specific setup.
  *
- * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
+ * Copyright (C) 1995-1997,1999,2001-2002 Silicon Graphics, Inc.  All rights reserved.
  * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
  */
-#ifndef _ASM_SN_ARCH_H
-#define _ASM_SN_ARCH_H
+#ifndef _ASM_IA64_SN_ARCH_H
+#define _ASM_IA64_SN_ARCH_H
 
-#include <linux/types.h>
 #include <linux/config.h>
-
+#include <linux/threads.h>
+#include <linux/mmzone.h>
 #include <asm/sn/types.h>
-#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_SGI_IP37) || defined(CONFIG_IA64_GENERIC)
+
+#if defined(CONFIG_IA64_SGI_SN1) 
 #include <asm/sn/sn1/arch.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/arch.h>
 #endif
 
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#if defined(CONFIG_IA64_SGI_SN1) 
+typedef u64	bdrkreg_t;
+#elif defined(CONFIG_IA64_SGI_SN2)
+typedef u64	shubreg_t;
+#endif
+
 typedef u64	hubreg_t;
+typedef u64	mmr_t;
 typedef u64	nic_t;
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-typedef u64     bdrkreg_t;
-#endif	/* CONFIG_SGI_xxxxx */
-#endif	/* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define CPUS_PER_NODE		4	/* CPUs on a single hub */
-#define CPUS_PER_NODE_SHFT	2	/* Bits to shift in the node number */
-#define CPUS_PER_SUBNODE	2	/* CPUs on a single hub PI */
-#endif
-#define CNODE_NUM_CPUS(_cnode)		(NODEPDA(_cnode)->node_num_cpus)
 
 #define CNODE_TO_CPU_BASE(_cnode)	(NODEPDA(_cnode)->node_first_cpu)
 
-#define makespnum(_nasid, _slice)					\
-		(((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-
-/*
- * There are 2 very similar macros for dealing with "slices". Make sure
- * you use the right one. 
- * Unfortunately, on all platforms except IP35 (currently), the 2 macros 
- * are interchangible. 
- *
- * On IP35, there are 4 cpus per node. Each cpu is refered to by it's slice.
- * The slices are numbered 0 thru 3. 
- *
- * There are also 2 PI interfaces per node. Each PI interface supports 2 cpus.
- * The term "local slice" specifies the cpu number relative to the PI.
- *
- * The cpus on the node are numbered:
- *	slice	localslice
- *	  0          0
- *	  1          1
- *	  2          0
- *	  3          1
- *
- *	cputoslice - returns a number 0..3 that is the slice of the specified cpu.
- *	cputolocalslice - returns a number 0..1 that identifies the local slice of
- *			the cpu within it's PI interface.
- */
-#ifdef LATER
-	/* These are dummied up for now ..... */
-#define cputocnode(cpu)				\
-               (pdaindr[(cpu)].p_nodeid)
-#define cputonasid(cpu)				\
-               (pdaindr[(cpu)].p_nasid)
-#define cputoslice(cpu)				\
-               (ASSERT(pdaindr[(cpu)].pda), (pdaindr[(cpu)].pda->p_slice))
-#define cputolocalslice(cpu)			\
-               (ASSERT(pdaindr[(cpu)].pda), (LOCALCPU(pdaindr[(cpu)].pda->p_slice)))
-#define cputosubnode(cpu)			\
-		(ASSERT(pdaindr[(cpu)].pda), (SUBNODE(pdaindr[(cpu)].pda->p_slice)))
-#else
-#define cputocnode(cpu) 0
-#define cputonasid(cpu) 0
-#define cputoslice(cpu) 0
-#define cputolocalslice(cpu) 0
-#define cputosubnode(cpu) 0
-#endif	/* LATER */
-#endif	/* CONFIG_SGI_IP35 */
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
-#define INVALID_NASID		(nasid_t)-1
-#define INVALID_CNODEID		(cnodeid_t)-1
-#define INVALID_PNODEID		(pnodeid_t)-1
-#define INVALID_MODULE		(moduleid_t)-1
-#define	INVALID_PARTID		(partid_t)-1
-
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-extern int     get_slice(void);
-extern cpuid_t get_cnode_cpu(cnodeid_t);
-extern int get_cpu_slice(cpuid_t);
-extern cpuid_t cnodetocpu(cnodeid_t);
-// extern cpuid_t cnode_slice_to_cpuid(cnodeid_t, int);
-
-extern int cnode_exists(cnodeid_t cnode);
-extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
-#endif	/* CONFIG_IP35 */
-
-extern nasid_t get_nasid(void);
-extern cnodeid_t get_cpu_cnode(int);
-extern int get_cpu_slice(cpuid_t);
-
-/*
- * NO ONE should access these arrays directly.  The only reason we refer to
- * them here is to avoid the procedure call that would be required in the
- * macros below.  (Really want private data members here :-)
- */
-extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
-extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
-
-/*
- * These macros are used by various parts of the kernel to convert
- * between the three different kinds of node numbering.   At least some
- * of them may change to procedure calls in the future, but the macros
- * will continue to work.  Don't use the arrays above directly.
- */
-
-#define	NASID_TO_REGION(nnode)	      	\
-    ((nnode) >> \
-     (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
-
-#ifndef __ia64
-extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
-extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
-extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
-
-#if !defined(DEBUG)
-
-#define NASID_TO_COMPACT_NODEID(nnode)	(nasid_to_compact_node[nnode])
-#define COMPACT_TO_NASID_NODEID(cnode)	(compact_to_nasid_node[cnode])
-#define CPUID_TO_COMPACT_NODEID(cpu)	(cpuid_to_compact_node[(cpu)])
-#else
-
-/*
- * These functions can do type checking and fail if they need to return
- * a bad nodeid, but they're not as fast so just use 'em for debug kernels.
- */
-cnodeid_t nasid_to_compact_nodeid(nasid_t nasid);
-nasid_t compact_to_nasid_nodeid(cnodeid_t cnode);
-
-#define NASID_TO_COMPACT_NODEID(nnode)	nasid_to_compact_nodeid(nnode)
-#define COMPACT_TO_NASID_NODEID(cnode)	compact_to_nasid_nodeid(cnode)
-#define CPUID_TO_COMPACT_NODEID(cpu)	(cpuid_to_compact_node[(cpu)])
-#endif
-
-#else
-
-/*
- * IA64 specific nasid and cnode ids.
- */
 #define NASID_TO_COMPACT_NODEID(nasid)  (nasid_to_cnodeid(nasid))
 #define COMPACT_TO_NASID_NODEID(cnode)  (cnodeid_to_nasid(cnode))
-#define CPUID_TO_COMPACT_NODEID(cpu)    (cpuid_to_cnodeid(cpu))
 
-#endif /* #ifndef __ia64 */
 
-extern int node_getlastslot(cnodeid_t);
+#define INVALID_NASID		((nasid_t)-1)
+#define INVALID_CNODEID		((cnodeid_t)-1)
+#define INVALID_PNODEID		((pnodeid_t)-1)
+#define INVALID_MODULE		((moduleid_t)-1)
+#define	INVALID_PARTID		((partid_t)-1)
 
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+extern cpuid_t cnodetocpu(cnodeid_t);
+void   sn_flush_all_caches(long addr, long bytes);
 
-#define SLOT_BITMASK    	(MAX_MEM_SLOTS - 1)
-#define SLOT_SIZE		(1LL<<SLOT_SHIFT)
+extern int     is_fine_dirmode(void);
 
-#define node_getnumslots(node)	(MAX_MEM_SLOTS)
-#define NODE_MAX_MEM_SIZE	SLOT_SIZE * MAX_MEM_SLOTS
 
-/*
- * New stuff in here from Irix sys/pfdat.h.
- */
-#define	SLOT_PFNSHIFT		(SLOT_SHIFT - PAGE_SHIFT)
-#define	PFN_NASIDSHFT		(NASID_SHFT - PAGE_SHIFT)
-#define mkpfn(nasid, off)	(((pfn_t)(nasid) << PFN_NASIDSHFT) | (off))
-#define slot_getbasepfn(node,slot) \
-		(mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT))
-#endif /* _ASM_SN_ARCH_H */
+#endif /* _ASM_IA64_SN_ARCH_H */
diff -Nru a/include/asm-ia64/sn/ate_utils.h b/include/asm-ia64/sn/ate_utils.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/ate_utils.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,51 @@
+#ifndef _ASM_IA64_SN_ATE_UTILS_H
+#define _ASM_IA64_SN_ATE_UTILS_H
+
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+/*
+ *	struct map	X[]	.m_size		.m_addr
+ *			---	------------	-----------
+ *			[0]	mapsize(X)	unused
+ *				# X[] unused
+ *			[1]	map lock *	mapwant sv_t *
+ *				map access	wait for free map space
+ *
+ *	  mapstart(X)-> [2]	# units		unit number
+ *			 :	    :		  :
+ *			[ ]	    0
+ */
+
+#include <linux/types.h>
+
+#define ulong_t uint64_t
+
+struct map
+{
+	unsigned long m_size;	/* number of units available */
+	unsigned long m_addr;	/* address of first available unit */
+};
+
+#define mapstart(X)		&X[2]		/* start of map array */
+
+#define mapsize(X)		X[0].m_size	/* number of empty slots */
+						/* remaining in map array */
+#define maplock(X)		(((spinlock_t *) X[1].m_size))
+
+#define mapout(X)		((sv_t *) X[1].m_addr)
+
+
+extern ulong_t atealloc(struct map *, size_t);
+extern struct map *atemapalloc(ulong_t);
+extern void atefree(struct map *, size_t, ulong_t);
+extern void atemapfree(struct map *);
+
+#endif /* _ASM_IA64_SN_ATE_UTILS_H  */
+
diff -Nru a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/bte.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,88 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_BTE_H
+#define _ASM_IA64_SN_BTE_H
+
+#ident "$Revision: $"
+
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+#include <asm/sn/io.h>
+
+#define L1_CACHE_MASK (L1_CACHE_BYTES - 1)	/* Mask to retrieve
+						 * the offset into this
+						 * cache line.*/
+
+/* BTE status register only supports 16 bits for length field */
+#define BTE_LEN_MASK ((1 << 16) - 1)
+
+/*
+ * Constants used in determining the best and worst case transfer
+ * times. To help explain the two, the following graph of transfer
+ * status vs time may help.
+ *
+ *     active +------------------:-+  :
+ *  status    |                  : |  :
+ *       idle +__________________:_+=======
+ *            0 Time           MaxT  MinT
+ *
+ *  Therefore, MaxT is the maximum thoeretical rate for transfering
+ *  the request block (assuming ideal circumstances)
+ *
+ *  MinT is the minimum theoretical rate for transferring the
+ *  requested block (assuming maximum link distance and contention)
+ *
+ *  The following defines are the inverse of the above.  They are
+ *  used for calculating the MaxT time and MinT time given the 
+ *  number of lines in the transfer.
+ */
+#define BTE_MAXT_LINES_PER_SECOND 800
+#define BTE_MINT_LINES_PER_SECOND 600
+
+
+/* Define hardware */
+#define BTES_PER_NODE 2
+
+/* Define hardware modes */
+#define BTE_NOTIFY (IBCT_NOTIFY)
+#define BTE_NORMAL BTE_NOTIFY
+#define BTE_ZERO_FILL (BTE_NOTIFY | IBCT_ZFIL_MODE)
+
+/* Use a reserved bit to let the caller specify a wait for any BTE */
+#define BTE_WACQUIRE (0x4000)
+
+/*
+ * Structure defining a bte.  An instance of this
+ * structure is created in the nodepda for each
+ * bte on that node (as defined by BTES_PER_NODE)
+ * This structure contains everything necessary
+ * to work with a BTE.
+ */
+typedef struct bteinfo_s {
+	u64 volatile notify ____cacheline_aligned;
+	char *bte_base_addr ____cacheline_aligned;
+	spinlock_t spinlock;
+	u64 idealTransferTimeout;
+	u64 idealTransferTimeoutReached;
+	u64 mostRecentSrc;
+	u64 mostRecentDest;
+	u64 mostRecentLen;
+	u64 mostRecentMode;
+	u64 volatile *mostRecentNotification;
+} bteinfo_t;
+
+/* Possible results from bte_copy and bte_unaligned_copy */
+typedef enum {
+	BTE_SUCCESS,		/* 0 is success */
+	BTEFAIL_NOTAVAIL,	/* BTE not available */
+	BTEFAIL_ERROR,		/* Generic error */
+	BTEFAIL_DIR		/* Diretory error */
+} bte_result_t;
+
+#endif				/* _ASM_IA64_SN_BTE_H */
diff -Nru a/include/asm-ia64/sn/bte_copy.h b/include/asm-ia64/sn/bte_copy.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/bte_copy.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,311 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * 
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_BTE_COPY_H
+#define _ASM_IA64_SN_BTE_COPY_H
+
+#ident "$Revision: $"
+
+#include <asm/sn/bte.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/pda.h>
+#include <asm/delay.h>
+
+/*
+ * BTE_LOCKING support - Undefining the following line will
+ * adapt the bte_copy code to support one bte per cpu in
+ * synchronous mode.  Even if bte_copy is called with a
+ * notify address, the bte will spin and wait for the transfer
+ * to complete.  By defining the following, spin_locks and
+ * busy checks are placed around the initiation of a BTE
+ * transfer and multiple bte's per cpu are supported.
+ */
+#define CONFIG_IA64_SGI_BTE_LOCKING 1
+
+/*
+ * Some macros to simplify reading.
+ *
+ * Start with macros to locate the BTE control registers.
+ */
+
+#define BTEREG_LNSTAT_ADDR (bte->bte_base_addr)
+#define BTEREG_SOURCE_ADDR (bte->bte_base_addr + IIO_IBSA0 - IIO_IBLS0)
+#define BTEREG_DEST_ADDR (bte->bte_base_addr + IIO_IBDA0 - IIO_IBLS0)
+#define BTEREG_CTRL_ADDR (bte->bte_base_addr + IIO_IBCT0 - IIO_IBLS0)
+#define BTEREG_NOTIF_ADDR (bte->bte_base_addr + IIO_IBNA0 - IIO_IBLS0)
+
+/* Some macros to force the IBCT0 value valid. */
+
+#define BTE_VALID_MODES BTE_NOTIFY
+#define BTE_VLD_MODE(x) (x & BTE_VALID_MODES)
+
+// #define DEBUG_BTE
+// #define DEBUG_BTE_VERBOSE
+// #define DEBUG_TIME_BTE
+
+#ifdef DEBUG_BTE
+#  define DPRINTK(x) printk x	// Terse
+#  ifdef DEBUG_BTE_VERBOSE
+#    define DPRINTKV(x) printk x	// Verbose
+#  else
+#    define DPRINTKV(x)
+#  endif
+#else
+#  define DPRINTK(x)
+#  define DPRINTKV(x)
+#endif
+
+#ifdef DEBUG_TIME_BTE
+extern u64 BteSetupTime;
+extern u64 BteTransferTime;
+extern u64 BteTeardownTime;
+extern u64 BteExecuteTime;
+#endif
+
+/*
+ * bte_copy(src, dest, len, mode, notification)
+ *
+ * use the block transfer engine to move kernel
+ * memory from src to dest using the assigned mode.
+ *
+ * Paramaters:
+ *   src - physical address of the transfer source.
+ *   dest - physical address of the transfer destination.
+ *   len - number of bytes to transfer from source to dest.
+ *   mode - hardware defined.  See reference information
+ *          for IBCT0/1 in the SHUB Programmers Reference
+ *   notification - kernel virtual address of the notification cache
+ *                  line.  If NULL, the default is used and
+ *                  the bte_copy is synchronous.
+ *
+ * NOTE:  This function requires src, dest, and len to
+ * be cache line aligned.
+ */
+extern __inline__ bte_result_t
+bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
+{
+#ifdef CONFIG_IA64_SGI_BTE_LOCKING
+	int bte_to_use;
+#endif
+
+#ifdef DEBUG_TIME_BTE
+	u64 invokeTime = 0;
+	u64 completeTime = 0;
+	u64 xferStartTime = 0;
+	u64 xferCompleteTime = 0;
+#endif
+	u64 transferSize;
+	bteinfo_t *bte;
+
+#ifdef DEBUG_TIME_BTE
+	invokeTime = ia64_get_itc();
+#endif
+
+	DPRINTK(("bte_copy (0x%lx, 0x%lx, 0x%lx, 0x%lx, 0x%lx)\n",
+		 src, dest, len, mode, notification));
+
+	if (len == 0) {
+		return (BTE_SUCCESS);
+	}
+
+	ASSERT(!((len & L1_CACHE_MASK) ||
+		 (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK)));
+
+	ASSERT(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT));
+
+#ifdef CONFIG_IA64_SGI_BTE_LOCKING
+	{
+		bte_to_use = 0;
+
+		/* Attempt to lock one of the BTE interfaces */
+		while ((*pda.cpubte[bte_to_use]->
+			mostRecentNotification & IBLS_BUSY)
+		       &&
+		       (!(spin_trylock
+			  (&(pda.cpubte[bte_to_use]->spinlock))))
+		       && (bte_to_use < BTES_PER_NODE)) {
+			bte_to_use++;
+		}
+
+		if ((bte_to_use >= BTES_PER_NODE) &&
+		    !(mode & BTE_WACQUIRE)) {
+			return (BTEFAIL_NOTAVAIL);
+		}
+
+		/* Wait until a bte is available. */
+	}
+	while (bte_to_use >= BTES_PER_NODE);
+
+	bte = pda.cpubte[bte_to_use];
+	DPRINTKV(("Got a lock on bte %d\n", bte_to_use));
+#else
+	/* Assuming one BTE per CPU. */
+	bte = pda.cpubte[0];
+#endif
+
+	/*
+	 * The following are removed for optimization but is
+	 * available in the event that the SHUB exhibits
+	 * notification problems similar to the hub, bedrock et al.
+	 *
+	 * bte->mostRecentSrc = src;
+	 * bte->mostRecentDest = dest;
+	 * bte->mostRecentLen = len;
+	 * bte->mostRecentMode = mode;
+	 */
+	if (notification == NULL) {
+		/* User does not want to be notified. */
+		bte->mostRecentNotification = &bte->notify;
+	} else {
+		bte->mostRecentNotification = notification;
+	}
+
+	/* Calculate the number of cache lines to transfer. */
+	transferSize = ((len >> L1_CACHE_SHIFT) & BTE_LEN_MASK);
+
+	DPRINTKV(("Calculated transfer size of %d cache lines\n",
+		  transferSize));
+
+	/* Initialize the notification to a known value. */
+	*bte->mostRecentNotification = -1L;
+
+
+	DPRINTKV(("Before, status is 0x%lx and notify is 0x%lx\n",
+		  HUB_L(BTEREG_LNSTAT_ADDR),
+		  *bte->mostRecentNotification));
+
+	/* Set the status reg busy bit and transfer length */
+	DPRINTKV(("IBLS - HUB_S(0x%lx, 0x%lx)\n",
+		  BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize));
+	HUB_S(BTEREG_LNSTAT_ADDR, IBLS_BUSY | transferSize);
+
+
+	DPRINTKV(("After setting status, status is 0x%lx and notify is 0x%lx\n", HUB_L(BTEREG_LNSTAT_ADDR), *bte->mostRecentNotification));
+
+	/* Set the source and destination registers */
+	DPRINTKV(("IBSA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_SOURCE_ADDR,
+		  src));
+	HUB_S(BTEREG_SOURCE_ADDR, src);
+	DPRINTKV(("IBDA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_DEST_ADDR, dest));
+	HUB_S(BTEREG_DEST_ADDR, dest);
+
+
+	/* Set the notification register */
+	DPRINTKV(("IBNA - HUB_S(0x%lx, 0x%lx)\n", BTEREG_NOTIF_ADDR,
+		  __pa(bte->mostRecentNotification)));
+	HUB_S(BTEREG_NOTIF_ADDR, (__pa(bte->mostRecentNotification)));
+
+
+	DPRINTKV(("Set Notify, status is 0x%lx and notify is 0x%lx\n",
+		  HUB_L(BTEREG_LNSTAT_ADDR),
+		  *bte->mostRecentNotification));
+
+	/* Initiate the transfer */
+	DPRINTKV(("IBCT - HUB_S(0x%lx, 0x%lx)\n", BTEREG_CTRL_ADDR, mode));
+#ifdef DEBUG_TIME_BTE
+	xferStartTime = ia64_get_itc();
+#endif
+	HUB_S(BTEREG_CTRL_ADDR, BTE_VLD_MODE(mode));
+
+	DPRINTKV(("Initiated, status is 0x%lx and notify is 0x%lx\n",
+		  HUB_L(BTEREG_LNSTAT_ADDR),
+		  *bte->mostRecentNotification));
+
+	// >>> Temporarily work around not getting a notification
+	// from medusa.
+	// *bte->mostRecentNotification = HUB_L(bte->bte_base_addr);
+
+	if (notification == NULL) {
+		/*
+		 * Calculate our timeout
+		 *
+		 * What are we doing here?  We are trying to determine
+		 * the fastest time the BTE could have transfered our
+		 * block of data.  By takine the clock frequency (ticks/sec)
+		 * divided by the BTE MaxT Transfer Rate (lines/sec)
+		 * times the transfer size (lines), we get a tick
+		 * offset from current time that the transfer should
+		 * complete.
+		 *
+		 * Why do this?  We are watching for a notification
+		 * failure from the BTE.  This behaviour has been
+		 * seen in the SN0 and SN1 hardware on rare circumstances
+		 * and is expected in SN2.  By checking at the
+		 * ideal transfer timeout, we minimize our time
+		 * delay from hardware completing our request and
+		 * our detecting the failure.
+		 */
+		bte->idealTransferTimeout = jiffies +
+		    (HZ / BTE_MAXT_LINES_PER_SECOND * transferSize);
+
+		while ((IBLS_BUSY & bte->notify)) {
+			/*
+			 * Notification Workaround: When the max
+			 * theoretical time has elapsed, read the hub
+			 * status register into the notification area.
+			 * This fakes the shub performing the copy.
+			 */
+			if (jiffies > bte->idealTransferTimeout) {
+				bte->notify = HUB_L(bte->bte_base_addr);
+				bte->idealTransferTimeoutReached++;
+				bte->idealTransferTimeout = jiffies +
+				    (HZ / BTE_MAXT_LINES_PER_SECOND *
+				     (bte->notify & BTE_LEN_MASK));
+			}
+		}
+#ifdef DEBUG_TIME_BTE
+		xferCompleteTime = ia64_get_itc();
+#endif
+		if (bte->notify & IBLS_ERROR) {
+			/* >>> Need to do real error checking. */
+			transferSize = 0;
+
+#ifdef CONFIG_IA64_SGI_BTE_LOCKING
+			spin_unlock(&(bte->spinlock));
+#endif
+			return (BTEFAIL_ERROR);
+		}
+
+	}
+#ifdef CONFIG_IA64_SGI_BTE_LOCKING
+	spin_unlock(&(bte->spinlock));
+#endif
+#ifdef DEBUG_TIME_BTE
+	completeTime = ia64_get_itc();
+
+	BteSetupTime = xferStartTime - invokeTime;
+	BteTransferTime = xferCompleteTime - xferStartTime;
+	BteTeardownTime = completeTime - xferCompleteTime;
+	BteExecuteTime = completeTime - invokeTime;
+#endif
+	return (BTE_SUCCESS);
+}
+
+/*
+ * Define the bte_unaligned_copy as an extern.
+ */
+extern bte_result_t bte_unaligned_copy(u64, u64, u64, u64, char *);
+
+/*
+ * The following is the prefered way of calling bte_unaligned_copy
+ * If the copy is fully cache line aligned, then bte_copy is
+ * used instead.  Since bte_copy is inlined, this saves a call
+ * stack.  NOTE: bte_copy is called synchronously and does block
+ * until the transfer is complete.  In order to get the asynch
+ * version of bte_copy, you must perform this check yourself.
+ */
+#define BTE_UNALIGNED_COPY(src, dest, len, mode, bteBlock) \
+	if ((len & L1_CACHE_MASK) || \
+	    (src & L1_CACHE_MASK) || \
+	    (dest & L1_CACHE_MASK)) { \
+		bte_unaligned_copy (src, dest, len, mode, bteBlock); \
+	} else { \
+		bte_copy(src, dest, len, mode, NULL); \
+	}
+
+#endif				/* _ASM_IA64_SN_BTE_COPY_H */
diff -Nru a/include/asm-ia64/sn/cdl.h b/include/asm-ia64/sn/cdl.h
--- a/include/asm-ia64/sn/cdl.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/cdl.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_CDL_H
-#define _ASM_SN_CDL_H
+#ifndef _ASM_IA64_SN_CDL_H
+#define _ASM_IA64_SN_CDL_H
 
 #include <asm/sn/sgi.h>
 
@@ -193,4 +192,4 @@
 void		async_attach_signal_done(async_attach_t);
 void		async_attach_waitall(async_attach_t);
 
-#endif	/* _ASM_SN_CDL_H */
+#endif /* _ASM_IA64_SN_CDL_H */
diff -Nru a/include/asm-ia64/sn/clksupport.h b/include/asm-ia64/sn/clksupport.h
--- a/include/asm-ia64/sn/clksupport.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/clksupport.h	Fri Mar 15 17:51:03 2002
@@ -4,61 +4,60 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-
-#ifndef  _ASM_KSYS_CLKSUPPORT_H
-#define _ASM_KSYS_CLKSUPPORT_H
-
-/* #include <sys/mips_addrspace.h> */
-
-#if SN
-#include <asm/sn/agent.h>
-#include <asm/sn/intr_public.h>
-typedef hubreg_t clkreg_t;
-extern nasid_t master_nasid;
-
-#define GET_LOCAL_RTC		(clkreg_t)LOCAL_HUB_L(PI_RT_COUNT)
-#define DISABLE_TMO_INTR()	if  (cpuid_to_localslice(cpuid())) \
-					REMOTE_HUB_PI_S(get_nasid(),\
-						cputosubnode(cpuid()),\
-						PI_RT_COMPARE_B, 0); \
-				else \
-					REMOTE_HUB_PI_S(get_nasid(),\
-						cputosubnode(cpuid()),\
-						PI_RT_COMPARE_A, 0);
-
-/* This is a hack; we really need to figure these values out dynamically */
-/* 
- * Since 800 ns works very well with various HUB frequencies, such as
- * 360, 380, 390 and 400 MHZ, we use 800 ns rtc cycle time.
- */
-#define NSEC_PER_CYCLE		800
-#define CYCLE_PER_SEC		(NSEC_PER_SEC/NSEC_PER_CYCLE)
 /*
- * Number of cycles per profiling intr 
+ * This file contains definitions for accessing a platform supported high resolution
+ * clock. The clock is monitonically increasing and can be accessed from any node
+ * in the system. The clock is synchronized across nodes - all nodes see the
+ * same value.
+ * 
+ *	RTC_COUNTER_ADDR - contains the address of the counter 
+ *
+ *	GET_RTC_COUNTER() - macro to read the value of the clock
+ *
+ *	RTC_CYCLES_PER_SEC - clock frequency in ticks per second	
+ *
  */
-#define CLK_FCLOCK_FAST_FREQ	1250
-#define CLK_FCLOCK_SLOW_FREQ	0
-/* The is the address that the user will use to mmap the cycle counter */
-#define CLK_CYCLE_ADDRESS_FOR_USER LOCAL_HUB_ADDR(PI_RT_COUNT)
-
-#elif IP30
-#include <sys/cpu.h>
-typedef heartreg_t clkreg_t;
-#define NSEC_PER_CYCLE		80
-#define CYCLE_PER_SEC		(NSEC_PER_SEC/NSEC_PER_CYCLE)
-#define GET_LOCAL_RTC	*((volatile clkreg_t *)PHYS_TO_COMPATK1(HEART_COUNT))
-#define DISABLE_TMO_INTR()
-#define CLK_CYCLE_ADDRESS_FOR_USER PHYS_TO_K1(HEART_COUNT)
-#define CLK_FCLOCK_SLOW_FREQ (CYCLE_PER_SEC / HZ)
+
+#ifndef _ASM_IA64_SN_CLKSUPPORT_H
+#define _ASM_IA64_SN_CLKSUPPORT_H
+
+#include <linux/config.h>
+#include <asm/sn/arch.h>
+#include <asm/sn/addrs.h>
+
+typedef long clkreg_t;
+extern long sn_rtc_cycles_per_second;
+
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/bedrock.h>
+#include <asm/sn/sn1/hubpi_next.h>
+/* clocks are not synchronized yet on SN1  - used node 0 (problem if no NASID 0) */
+#define RTC_COUNTER_ADDR	((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COUNTER))
+#define RTC_COMPARE_A_ADDR      ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_A))
+#define RTC_COMPARE_B_ADDR      ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_COMPARE_B))
+#define RTC_INT_PENDING_A_ADDR  ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_A))
+#define RTC_INT_PENDING_B_ADDR  ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_PEND_B))
+#define RTC_INT_ENABLED_A_ADDR  ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_A))
+#define RTC_INT_ENABLED_B_ADDR  ((clkreg_t*)REMOTE_HUB_ADDR(0, PI_RT_INT_EN_B))
+#else
+#include <asm/sn/sn2/shub_mmr.h>
+#define RTC_COUNTER_ADDR	((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
+#define RTC_COMPARE_A_ADDR      ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
+#define RTC_COMPARE_B_ADDR      ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
+#define RTC_INT_PENDING_A_ADDR  ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
+#define RTC_INT_PENDING_B_ADDR  ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
+#define RTC_INT_ENABLED_A_ADDR  ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
+#define RTC_INT_ENABLED_B_ADDR  ((clkreg_t*)LOCAL_MMR_ADDR(SH_RTC))
 #endif
 
-/* Prototypes */
-extern void init_timebase(void);
-extern void fastick_maint(struct eframe_s *);
-extern int audioclock;
-extern int prfclk_enabled_cnt;
-#endif  /* _ASM_KSYS_CLKSUPPORT_H */
+
+#define GET_RTC_COUNTER()	(*RTC_COUNTER_ADDR)
+#define rtc_time()		GET_RTC_COUNTER()
+
+#define RTC_CYCLES_PER_SEC	sn_rtc_cycles_per_second
+
+#endif /* _ASM_IA64_SN_CLKSUPPORT_H */
diff -Nru a/include/asm-ia64/sn/dmamap.h b/include/asm-ia64/sn/dmamap.h
--- a/include/asm-ia64/sn/dmamap.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/dmamap.h	Fri Mar 15 17:51:02 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_DMAMAP_H
-#define _ASM_SN_DMAMAP_H
+#ifndef _ASM_IA64_SN_DMAMAP_H
+#define _ASM_IA64_SN_DMAMAP_H
 
 #include <asm/sn/sv.h>
 
@@ -70,7 +69,6 @@
 extern int a24_mapsize;
 extern int a32_mapsize;
 
-extern lock_t dmamaplock;
 extern sv_t dmamapout;
 
 #ifdef __cplusplus
@@ -87,4 +85,4 @@
 
 #define	DMAMAP_FLAGS	0x7
 
-#endif /* _ASM_SN_DMAMAP_H */
+#endif /* _ASM_IA64_SN_DMAMAP_H */
diff -Nru a/include/asm-ia64/sn/driver.h b/include/asm-ia64/sn/driver.h
--- a/include/asm-ia64/sn/driver.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/driver.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_DRIVER_H
-#define _ASM_SN_DRIVER_H
+#ifndef _ASM_IA64_SN_DRIVER_H
+#define _ASM_IA64_SN_DRIVER_H
+
+#include <linux/devfs_fs_kernel.h>
+#include <asm/types.h>
 
 /*
 ** Interface for device driver handle management.
@@ -18,133 +20,77 @@
 */
 
 typedef struct device_driver_s *device_driver_t;
-#define DEVICE_DRIVER_NONE (device_driver_t)NULL
 
 /* == Driver thread priority support == */
 typedef int ilvl_t;
-/* default driver thread priority level */
-#define DRIVER_THREAD_PRI_DEFAULT	(ilvl_t)230
-/* invalid driver thread priority level */
-#define DRIVER_THREAD_PRI_INVALID	(ilvl_t)-1
-
-/* Associate a thread priority with a driver */
-extern int device_driver_thread_pri_set(device_driver_t driver,
-					ilvl_t pri);
-
-/* Get the thread priority associated with the driver */
-extern ilvl_t device_driver_thread_pri_get(device_driver_t driver);
-
-/* Get the thread priority for a driver from the sysgen paramters */
-extern ilvl_t device_driver_sysgen_thread_pri_get(char *driver_prefix);
-
-/* Initialize device driver functions. */
-extern void device_driver_init(void);
-
-
-/* Allocate a driver handle */
-extern device_driver_t device_driver_alloc(char *prefix);
-
-
-/* Free a driver handle */
-extern void device_driver_free(device_driver_t driver);
-
-
-/* Given a device driver prefix, return a handle to the driver. */
-extern device_driver_t device_driver_get(char *prefix);
-
-/* Given a device, return a handle to the driver. */
-extern device_driver_t device_driver_getbydev(devfs_handle_t device);
 
-struct cdevsw;
-struct bdevsw;
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct eframe_s;
+struct piomap;
+struct dmamap;
+
+typedef __psunsigned_t iobush_t;
+
+/* interrupt function */
+typedef void	       *intr_arg_t;
+typedef void		intr_func_f(intr_arg_t);
+typedef intr_func_f    *intr_func_t;
+
+#define	INTR_ARG(n)	((intr_arg_t)(__psunsigned_t)(n))
+
+/* system interrupt resource handle -- returned from intr_alloc */
+typedef struct intr_s *intr_t;
+#define INTR_HANDLE_NONE ((intr_t)0)
 
-/* Associate a driver with bdevsw/cdevsw pointers. */
-extern int
-device_driver_devsw_put(device_driver_t driver,
-			struct bdevsw *my_bdevsw,
-			struct cdevsw *my_cdevsw);
-
-
-/* Given a driver, return the corresponding bdevsw and cdevsw pointers. */
-extern void
-device_driver_devsw_get(	device_driver_t driver, 
-				struct bdevsw **bdevswp,
-				struct cdevsw **cdevswp);
-
-/* Given a driver, return its name (prefix). */
-extern void device_driver_name_get(device_driver_t driver, char *buffer, int length);
+/*
+ * restore interrupt level value, returned from intr_block_level
+ * for use with intr_unblock_level.
+ */
+typedef void *rlvl_t;
 
 
 /* 
- * A descriptor for every static device driver in the system.
- * lboot creates a table of these and places in in master.c.
- * device_driver_init runs through this table during initialization
- * in order to "register" every static device driver.
+ * A basic, platform-independent description of I/O requirements for
+ * a device. This structure is usually formed by lboot based on information 
+ * in configuration files.  It contains information about PIO, DMA, and
+ * interrupt requirements for a specific instance of a device.
+ *
+ * The pio description is currently unused.
+ *
+ * The dma description describes bandwidth characteristics and bandwidth
+ * allocation requirements. (TBD)
+ *
+ * The Interrupt information describes the priority of interrupt, desired 
+ * destination, policy (TBD), whether this is an error interrupt, etc.  
+ * For now, interrupts are targeted to specific CPUs.
  */
-typedef struct static_device_driver_desc_s {
-	char 		*sdd_prefix;
-	struct bdevsw 	*sdd_bdevsw;
-	struct cdevsw 	*sdd_cdevsw;
-} *static_device_driver_desc_t;
-
-extern struct static_device_driver_desc_s static_device_driver_table[];
-extern int static_devsw_count;
 
+typedef struct device_desc_s {
+	/* pio description (currently none) */
 
-/*====== administration support ========== */
-/* structure of each entry in the table created by lboot for
- * device / driver administration
-*/
-typedef struct dev_admin_info_s {
-	char	*dai_name;		/* name of the device or driver
-					 * prefix 
-					 */
-	char	*dai_param_name;	/* device or driver parameter name */
-	char	*dai_param_val;		/* value of the parameter */
-} dev_admin_info_t;
-
-
-/* Update all the administrative hints associated with the device */
-extern void 	device_admin_info_update(devfs_handle_t	dev_vhdl);
-
-/* Update all the administrative hints associated with the device driver */
-extern void	device_driver_admin_info_update(device_driver_t	driver);
-
-/* Get a particular administrative hint associated with a device */
-extern char 	*device_admin_info_get(devfs_handle_t	dev_vhdl,
-				       char		*info_lbl);
-
-/* Associate a particular administrative hint for a device */
-extern int	device_admin_info_set(devfs_handle_t	dev_vhdl,
-				      char		*info_lbl,
-				      char		*info_val);
-
-/* Get a particular administrative hint associated with a device driver*/
-extern char 	*device_driver_admin_info_get(char	*driver_prefix,	
-					      char	*info_name);
-
-/* Associate a particular administrative hint for a device driver*/
-extern int	device_driver_admin_info_set(char	*driver_prefix,
-					     char	*driver_info_lbl,
-					     char	*driver_info_val);
+	/* dma description */
+	/* TBD: allocated badwidth requirements */
 
-/* Initialize the extended device administrative hint table */
-extern void	device_admin_table_init(void);
-
-/* Add a hint corresponding to a device to the extended device administrative
- * hint table.
- */
-extern void	device_admin_table_update(char *dev_name,
-					  char *param_name,
-					  char *param_val);
-
-/* Initialize the extended device driver administrative hint table */
-extern void	device_driver_admin_table_init(void);
-
-/* Add a hint corresponding to a device to the extended device driver 
- * administrative hint table.
- */
-extern void	device_driver_admin_table_update(char *drv_prefix,
-						 char *param_name,
-						 char *param_val);	
-#endif /* _ASM_SN_DRIVER_H */
+	/* interrupt description */
+	devfs_handle_t	intr_target;	/* Hardware locator string */
+	int 		intr_policy;	/* TBD */
+	ilvl_t		intr_swlevel;	/* software level for blocking intr */
+	char		*intr_name;	/* name of interrupt, if any */
+
+	int		flags;
+} *device_desc_t;
+
+/* flag values */
+#define	D_INTR_ISERR	0x1		/* interrupt is for error handling */
+#define D_IS_ASSOC	0x2		/* descriptor is associated with a dev */
+#define D_INTR_NOTHREAD	0x4		/* Interrupt handler isn't threaded. */
+
+#define INTR_SWLEVEL_NOTHREAD_DEFAULT 	0	/* Default
+						 * Interrupt level in case of
+						 * non-threaded interrupt 
+						 * handlers
+						 */
+#endif /* _ASM_IA64_SN_DRIVER_H */
diff -Nru a/include/asm-ia64/sn/eeprom.h b/include/asm-ia64/sn/eeprom.h
--- a/include/asm-ia64/sn/eeprom.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/eeprom.h	Fri Mar 15 17:51:03 2002
@@ -6,11 +6,10 @@
  *
  * Public interface for reading Atmel EEPROMs via L1 system controllers
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_EEPROM_H
-#define _ASM_SN_EEPROM_H
+#ifndef _ASM_IA64_SN_EEPROM_H
+#define _ASM_IA64_SN_EEPROM_H
 
 #include <asm/sn/sgi.h>
 #include <asm/sn/vector.h>
@@ -385,14 +384,8 @@
 		          ( IO_BRICK, NASID_GET((r)), (v), 0 ) \
 		      : nic_bridge_vertex_info((v), (r)) )
 
-#ifdef BRINGUP /* will we read mfg info from IOC3's that aren't
-		* part of IO7 cards, or aren't in I/O bricks? */
-#define IOC3_VERTEX_MFG_INFO(v, r, e) \
-    eeprom_vertex_info_set( IO_IO7, NASID_GET((r)), (v), 0 )
-#endif /* BRINGUP */
-
 #define HUB_UID_GET(n,v,p)	cbrick_uid_get((n),(p))
 #define ROUTER_UID_GET(d,p)	rbrick_uid_get(get_nasid(),(d),(p))
 #define XBOW_UID_GET(n,p)	iobrick_uid_get((n),(p))
 
-#endif /* _ASM_SN_EEPROM_H */
+#endif /* _ASM_IA64_SN_EEPROM_H */
diff -Nru a/include/asm-ia64/sn/fetchop.h b/include/asm-ia64/sn/fetchop.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/fetchop.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,40 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_FETCHOP_H
+#define _ASM_IA64_SN_FETCHOP_H
+
+#define FETCHOP_BASENAME	"sgi_fetchop"
+#define FETCHOP_FULLNAME	"/dev/sgi_fetchop"
+
+
+
+#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
+
+#define FETCHOP_LOAD		0
+#define FETCHOP_INCREMENT	8
+#define FETCHOP_DECREMENT	16
+#define FETCHOP_CLEAR		24
+
+#define FETCHOP_STORE		0
+#define FETCHOP_AND		24
+#define FETCHOP_OR		32
+
+#define FETCHOP_CLEAR_CACHE	56
+
+#define FETCHOP_LOAD_OP(addr, op) ( \
+         *(long *)((char*) (addr) + (op)))
+
+#define FETCHOP_STORE_OP(addr, op, x) ( \
+         *(long *)((char*) (addr) + (op)) = \
+              (long) (x))
+
+#endif /* _ASM_IA64_SN_FETCHOP_H */
+
diff -Nru a/include/asm-ia64/sn/gda.h b/include/asm-ia64/sn/gda.h
--- a/include/asm-ia64/sn/gda.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/gda.h	Fri Mar 15 17:51:01 2002
@@ -6,16 +6,17 @@
  *
  * Derived from IRIX <sys/SN/gda.h>.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  *
  * gda.h -- Contains the data structure for the global data area,
  * 	The GDA contains information communicated between the
  *	PROM, SYMMON, and the kernel. 
  */
-#ifndef _ASM_SN_GDA_H
-#define _ASM_SN_GDA_H
+#ifndef _ASM_IA64_SN_GDA_H
+#define _ASM_IA64_SN_GDA_H
 
 #include <asm/sn/addrs.h>
+#include <asm/sn/sn_cpuid.h>
 
 #define GDA_MAGIC	0x58464552
 
@@ -42,7 +43,7 @@
 #define G_PARTIDOFF	40
 #define G_TABLEOFF	128
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 typedef struct gda {
 	u32	g_magic;	/* GDA magic number */
@@ -68,7 +69,7 @@
 
 #define GDA ((gda_t*) GDA_ADDR(get_nasid()))
 
-#endif /* __LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 /*
  * Define:	PART_GDA_VERSION
  * Purpose:	Define the minimum version of the GDA required, lower 
@@ -105,4 +106,4 @@
 #define PROMOP_BIST1		0x0800		/* keep track of which BIST ran */
 #define PROMOP_BIST2		0x1000		/* keep track of which BIST ran */
 
-#endif /* _ASM_SN_GDA_H */
+#endif /* _ASM_IA64_SN_GDA_H */
diff -Nru a/include/asm-ia64/sn/hack.h b/include/asm-ia64/sn/hack.h
--- a/include/asm-ia64/sn/hack.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/hack.h	Fri Mar 15 17:51:01 2002
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 
-#ifndef _ASM_SN_HACK_H
-#define _ASM_SN_HACK_H
+#ifndef _ASM_IA64_SN_HACK_H
+#define _ASM_IA64_SN_HACK_H
 
 #include <asm/sn/types.h>
 #include <asm/uaccess.h>		/* for copy_??_user */
@@ -32,7 +31,6 @@
 #include <linux/devfs_fs_kernel.h>
 
 #define DELAY(a)
-#define cpuid() 0
 
 /************************************************
  * Routines redefined to use linux equivalents. *
@@ -59,14 +57,14 @@
 #define spl7	splhi()
 #define splx(s)
 
-extern void * kmem_alloc_node(register size_t, register int, cnodeid_t);
-extern void * kmem_zalloc(size_t, int);
-extern void * kmem_zalloc_node(register size_t, register int, cnodeid_t );
-extern void * kmem_zone_alloc(register zone_t *, int);
-extern zone_t * kmem_zone_init(register int , char *);
-extern void kmem_zone_free(register zone_t *, void *);
+extern void * snia_kmem_alloc_node(register size_t, register int, cnodeid_t);
+extern void * snia_kmem_zalloc(size_t, int);
+extern void * snia_kmem_zalloc_node(register size_t, register int, cnodeid_t );
+extern void * snia_kmem_zone_alloc(register zone_t *, int);
+extern zone_t * snia_kmem_zone_init(register int , char *);
+extern void snia_kmem_zone_free(register zone_t *, void *);
 extern int is_specified(char *);
 extern int cap_able(uint64_t);
 extern int compare_and_swap_ptr(void **, void *, void *);
 
-#endif	/* _ASM_SN_HACK_H */
+#endif /* _ASM_IA64_SN_HACK_H */
diff -Nru a/include/asm-ia64/sn/hcl.h b/include/asm-ia64/sn/hcl.h
--- a/include/asm-ia64/sn/hcl.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/hcl.h	Fri Mar 15 17:51:02 2002
@@ -4,13 +4,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_HCL_H
-#define _ASM_SN_HCL_H
+#ifndef _ASM_IA64_SN_HCL_H
+#define _ASM_IA64_SN_HCL_H
+
+#include <asm/sn/sgi.h>
+#include <asm/sn/invent.h>
+#include <linux/devfs_fs_kernel.h>
 
-extern spinlock_t hcl_spinlock;
 extern devfs_handle_t hcl_handle; /* HCL driver */
 extern devfs_handle_t hwgraph_root;
 extern devfs_handle_t linux_busnum;
@@ -93,7 +95,6 @@
 extern devfs_handle_t hwgraph_char_device_get(devfs_handle_t);
 extern graph_error_t hwgraph_char_device_add(devfs_handle_t, char *, char *, devfs_handle_t *);
 extern int hwgraph_path_add(devfs_handle_t, char *, devfs_handle_t *);
-extern struct file_operations * hwgraph_bdevsw_get(devfs_handle_t);
 extern int hwgraph_info_add_LBL(devfs_handle_t, char *, arbitrary_info_t);
 extern int hwgraph_info_get_LBL(devfs_handle_t, char *, arbitrary_info_t *);
 extern int hwgraph_info_replace_LBL(devfs_handle_t, char *, arbitrary_info_t,
@@ -111,4 +112,4 @@
 
 
 
-#endif /* _ASM_SN_HCL_H */
+#endif /* _ASM_IA64_SN_HCL_H */
diff -Nru a/include/asm-ia64/sn/hcl_util.h b/include/asm-ia64/sn/hcl_util.h
--- a/include/asm-ia64/sn/hcl_util.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/hcl_util.h	Fri Mar 15 17:51:01 2002
@@ -4,12 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_HCL_UTIL_H
-#define _ASM_SN_HCL_UTIL_H
+#ifndef _ASM_IA64_SN_HCL_UTIL_H
+#define _ASM_IA64_SN_HCL_UTIL_H
+
+#include <linux/devfs_fs_kernel.h>
 
 extern char * dev_to_name(devfs_handle_t, char *, uint);
 extern int device_master_set(devfs_handle_t, devfs_handle_t);
@@ -17,8 +18,5 @@
 extern cnodeid_t master_node_get(devfs_handle_t);
 extern cnodeid_t nodevertex_to_cnodeid(devfs_handle_t);
 extern void mark_nodevertex_as_node(devfs_handle_t, cnodeid_t);
-extern void device_info_set(devfs_handle_t, void *);
-extern void *device_info_get(devfs_handle_t);
-
 
-#endif _ASM_SN_HCL_UTIL_H
+#endif /* _ASM_IA64_SN_HCL_UTIL_H */
diff -Nru a/include/asm-ia64/sn/hires_clock.h b/include/asm-ia64/sn/hires_clock.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/hires_clock.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,52 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.
+ *
+ * SGI Hi Resolution Clock
+ *
+ * SGI SN platforms provide a high resolution clock that is
+ * synchronized across all nodes. The clock can be memory mapped
+ * and directly read from user space.
+ *
+ * Access to the clock is thru the following:
+ *       (error checking not shown)
+ *
+ * (Note: should library routines be provided to encapsulate this??)
+ *
+ *	int		fd:
+ *	volatile long	*clk;
+ *
+ *	fd = open (HIRES_FULLNAME, O_RDONLY);
+ *	clk = mmap(0, getpagesize(), PROT_READ, MAP_SHARED, fd, 0);
+ *	clk += ioctl(fd, HIRES_IOCQGETOFFSET, 0);
+ *
+ * At this point, clk is a pointer to the high resolution clock.
+ *
+ * The clock period can be obtained via:
+ *
+ *	long	picosec_per_tick;
+ *	picosec_per_tick = ioctl(fd, HIRES_IOCQGETPICOSEC, 0);
+ */
+
+#ifndef _ASM_IA64_SN_HIRES_CLOCK_H
+#define _ASM_IA64_SN_HIRES_CLOCK_H
+
+
+#define HIRES_BASENAME	"sgi_hires_clock"
+#define HIRES_FULLNAME  "/dev/sgi_hires_clock"
+#define HIRES_IOC_BASE	's'
+
+
+/* Get page offset of hires timer */
+#define HIRES_IOCQGETOFFSET	_IO( HIRES_IOC_BASE, 0 )
+
+/* get clock period in picoseconds per tick */
+#define HIRES_IOCQGETPICOSEC	_IO( HIRES_IOC_BASE, 1 )
+
+/* get number of significant bits in clock counter */
+#define HIRES_IOCQGETCLOCKBITS	_IO( HIRES_IOC_BASE, 2 )
+
+#endif /* _ASM_IA64_SN_HIRES_CLOCK_H */
diff -Nru a/include/asm-ia64/sn/hubspc.h b/include/asm-ia64/sn/hubspc.h
--- a/include/asm-ia64/sn/hubspc.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,25 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_HUBSPC_H
-#define _ASM_SN_HUBSPC_H
-
-typedef enum {
-        HUBSPC_REFCOUNTERS,
-	HUBSPC_PROM
-} hubspc_subdevice_t;
-
-
-/*
- * Reference Counters
- */
-
-extern int refcounters_attach(devfs_handle_t hub);
-
-#endif /* _ASM_SN_HUBSPC_H */        
diff -Nru a/include/asm-ia64/sn/hwcntrs.h b/include/asm-ia64/sn/hwcntrs.h
--- a/include/asm-ia64/sn/hwcntrs.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,97 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_HWCNTRS_H
-#define _ASM_SN_HWCNTRS_H
-
-
-typedef  uint64_t refcnt_t;
-
-#define SN0_REFCNT_MAX_COUNTERS 64
-
-typedef struct sn0_refcnt_set {
-	refcnt_t    refcnt[SN0_REFCNT_MAX_COUNTERS];
-        uint64_t  flags;
-        uint64_t  reserved[4];
-} sn0_refcnt_set_t;
-
-typedef struct sn0_refcnt_buf {
-	sn0_refcnt_set_t   refcnt_set;
-	uint64_t         paddr;
-        uint64_t         page_size;
-        cnodeid_t          cnodeid;         /* cnodeid + pad[3] use 64 bits */
-        uint16_t           pad[3];
-        uint64_t         reserved[4];
-} sn0_refcnt_buf_t;
-
-typedef struct sn0_refcnt_args {
-	uint64_t          vaddr;
-	uint64_t          len;
-	sn0_refcnt_buf_t*   buf;
-        uint64_t          reserved[4];
-} sn0_refcnt_args_t;
-
-/*
- * Info needed by the user level program
- * to mmap the refcnt buffer
- */
-
-#define RCB_INFO_GET  1
-#define RCB_SLOT_GET  2
-
-typedef struct rcb_info {
-        uint64_t  rcb_len;                  /* total refcnt buffer len in bytes */
-
-        int         rcb_sw_sets;              /* number of sw counter sets in buffer */
-        int         rcb_sw_counters_per_set;  /* sw counters per set -- numnodes */
-        int         rcb_sw_counter_size;      /* sizeof(refcnt_t) -- size of sw cntr */
-
-        int         rcb_base_pages;           /* number of base pages in node */
-        int         rcb_base_page_size;       /* sw base page size */        
-        uint64_t  rcb_base_paddr;           /* base physical address for this node */
-
-        int         rcb_cnodeid;              /* cnodeid for this node */
-        int         rcb_granularity;          /* hw page size used for counter sets */
-        uint        rcb_hw_counter_max;       /* max hwcounter count (width mask) */
-        int         rcb_diff_threshold;       /* current node differential threshold */
-        int         rcb_abs_threshold;        /* current node absolute threshold */
-        int         rcb_num_slots;            /* physmem slots */
-        
-        int         rcb_reserved[512];
-        
-} rcb_info_t;
-
-typedef struct rcb_slot {
-        uint64_t  base;
-        uint64_t  size;
-} rcb_slot_t;
-
-#if defined(__KERNEL__)
-typedef struct sn0_refcnt_args_32 {
-	uint64_t    vaddr;
-	uint64_t    len;
-	app32_ptr_t   buf;
-        uint64_t    reserved[4];
-} sn0_refcnt_args_32_t;
-
-/* Defines and Macros  */
-/* A set of reference counts are for 4k bytes of physical memory */
-#define	NBPREFCNTP	0x1000	
-#define	BPREFCNTPSHIFT	12
-#define bytes_to_refcntpages(x)	(((__psunsigned_t)(x)+(NBPREFCNTP-1))>>BPREFCNTPSHIFT)
-#define refcntpage_offset(x)	((__psunsigned_t)(x)&((NBPP-1)&~(NBPREFCNTP-1)))
-#define align_to_refcntpage(x)	((__psunsigned_t)(x)&(~(NBPREFCNTP-1)))
-
-extern void migr_refcnt_read(sn0_refcnt_buf_t*);
-extern void migr_refcnt_read_extended(sn0_refcnt_buf_t*);
-extern int migr_refcnt_enabled(void);
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_SN_HWCNTRS_H */
diff -Nru a/include/asm-ia64/sn/idle.h b/include/asm-ia64/sn/idle.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/idle.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,54 @@
+#ifndef _ASM_IA64_SN_IDLE_H
+#define _ASM_IA64_SN_IDLE_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <asm/sn/leds.h>
+#include <asm/sn/simulator.h>
+
+static __inline__ void
+snidle(void) {
+
+#ifdef CONFIG_IA64_SGI_AUTOTEST
+	{
+		extern int	autotest_enabled;
+		if (autotest_enabled) {
+			extern void llsc_main(int, long, long);
+			llsc_main(smp_processor_id(), 0xe000000000000000LL, 0xe000000001000000LL);
+		}
+	}
+#endif
+	
+	if (pda.idle_flag == 0) {
+		/* 
+		 * Turn the activity LED off.
+		 */
+		set_led_bits(0, LED_CPU_ACTIVITY);
+	}
+
+#ifdef CONFIG_IA64_SGI_SN_SIM
+	if (IS_RUNNING_ON_SIMULATOR())
+		SIMULATOR_SLEEP();
+#endif
+
+	pda.idle_flag = 1;
+}
+
+static __inline__ void
+snidleoff(void) {
+	/* 
+	 * Turn the activity LED on.
+	 */
+	set_led_bits(LED_CPU_ACTIVITY, LED_CPU_ACTIVITY);
+
+	pda.idle_flag = 0;
+}
+
+#endif /* _ASM_IA64_SN_IDLE_H */
diff -Nru a/include/asm-ia64/sn/ifconfig_net.h b/include/asm-ia64/sn/ifconfig_net.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/ifconfig_net.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_IFCONFIG_NET_H
+#define _ASM_IA64_SN_IFCONFIG_NET_H
+
+#define NETCONFIG_FILE "/tmp/ifconfig_net"
+#define POUND_CHAR                   '#'
+#define MAX_LINE_LEN 128
+#define MAXPATHLEN 128
+
+struct ifname_num {
+	long next_eth;
+	long next_fddi;
+	long next_hip;
+	long next_tr;
+	long next_fc;
+	long size;
+};
+
+struct ifname_MAC {
+	char name[16];
+	unsigned char           dev_addr[7];
+	unsigned char           addr_len;       /* hardware address length      */
+};
+
+#endif /* _ASM_IA64_SN_IFCONFIG_NET_H */
diff -Nru a/include/asm-ia64/sn/intr.h b/include/asm-ia64/sn/intr.h
--- a/include/asm-ia64/sn/intr.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/intr.h	Fri Mar 15 17:51:02 2002
@@ -4,250 +4,17 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_INTR_H
-#define _ASM_SN_INTR_H
-
-/* Subnode wildcard */
-#define SUBNODE_ANY		-1
-
-/* Number of interrupt levels associated with each interrupt register. */
-#define N_INTPEND_BITS		64
-
-#define INT_PEND0_BASELVL	0
-#define INT_PEND1_BASELVL	64
-
-#define	N_INTPENDJUNK_BITS	8
-#define	INTPENDJUNK_CLRBIT	0x80
+#ifndef _ASM_IA64_SN_INTR_H
+#define _ASM_IA64_SN_INTR_H
 
 #include <linux/config.h>
-#include <asm/sn/intr_public.h>
-
-#if LANGUAGE_C
-
-#define II_NAMELEN	24
-
-/*
- * Dispatch table entry - contains information needed to call an interrupt
- * routine.
- */
-typedef struct intr_vector_s {
-	intr_func_t	iv_func;	/* Interrupt handler function */
-	intr_func_t	iv_prefunc;	/* Interrupt handler prologue func */
-	void		*iv_arg;	/* Argument to pass to handler */
-#ifdef LATER
-	thd_int_t		iv_tinfo;	/* Thread info */
-#endif
-	cpuid_t			iv_mustruncpu;	/* Where we must run. */
-} intr_vector_t;
-
-/* Interrupt information table. */
-typedef struct intr_info_s {
-	xtalk_intr_setfunc_t	ii_setfunc;	/* Function to set the interrupt
-						 * destination and level register.
-						 * It returns 0 (success) or an
-						 * error code.
-						 */
-	void			*ii_cookie;	/* arg passed to setfunc */
-	devfs_handle_t		ii_owner_dev;	/* device that owns this intr */
-	char			ii_name[II_NAMELEN];	/* Name of this intr. */
-	int			ii_flags;	/* informational flags */
-} intr_info_t;
-
-#define iv_tflags	iv_tinfo.thd_flags
-#define iv_isync	iv_tinfo.thd_isync
-#define iv_lat		iv_tinfo.thd_latstats
-#define iv_thread	iv_tinfo.thd_ithread
-#define iv_pri		iv_tinfo.thd_pri
-
-#define THD_CREATED	0x00000001	/*
-					 * We've created a thread for this
-					 * interrupt.
-					 */
-
-/*
- * Bits for ii_flags:
- */
-#define II_UNRESERVE	0
-#define II_RESERVE	1		/* Interrupt reserved. 			*/
-#define II_INUSE	2		/* Interrupt connected 			*/
-#define II_ERRORINT	4		/* INterrupt is an error condition 	*/
-#define II_THREADED	8		/* Interrupt handler is threaded.	*/
-
-/*
- * Interrupt level wildcard
- */
-#define INTRCONNECT_ANYBIT	-1
-
-/*
- * This structure holds information needed both to call and to maintain
- * interrupts.  The two are in separate arrays for the locality benefits.
- * Since there's only one set of vectors per hub chip (but more than one
- * CPU, the lock to change the vector tables must be here rather than in
- * the PDA.
- */
-
-typedef struct intr_vecblk_s {
-	intr_vector_t	vectors[N_INTPEND_BITS];  /* information needed to
-						     call an intr routine. */
-	intr_info_t	info[N_INTPEND_BITS];	  /* information needed only
-						     to maintain interrupts. */
-	spinlock_t	vector_lock;		  /* Lock for this and the
-						     masks in the PDA. */
-	splfunc_t	vector_spl;		  /* vector_lock req'd spl */
-	int		vector_state;		  /* Initialized to zero.
-						     Set to INTR_INITED
-						     by hubintr_init.
-						   */
-	int		vector_count;		  /* Number of vectors
-						   * reserved.
-						   */
-	int		cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are
-						   * connected to each CPU
-						   */
-	int		ithreads_enabled;	  /* Are interrupt threads
-						   * initialized on this node.
-						   * and block?
-						   */
-} intr_vecblk_t;
-
-/* Possible values for vector_state: */
-#define VECTOR_UNINITED	0
-#define VECTOR_INITED	1
-#define VECTOR_SET	2
-
-#define hub_intrvect0	private.p_intmasks.dispatch0->vectors
-#define hub_intrvect1	private.p_intmasks.dispatch1->vectors
-#define hub_intrinfo0	private.p_intmasks.dispatch0->info
-#define hub_intrinfo1	private.p_intmasks.dispatch1->info
-
-/*
- * Macros to manipulate the interrupt register on the calling hub chip.
- */
-
-#define LOCAL_HUB_SEND_INTR(_level)	LOCAL_HUB_S(PI_INT_PEND_MOD, \
-						    (0x100|(_level)))
-#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \
-		REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level)))
-
-#define REMOTE_CPU_SEND_INTR(_cpuid, _level) 					\
-		REMOTE_HUB_PI_S(cputonasid(_cpuid),				\
-			SUBNODE(cputoslice(_cpuid)),				\
-			PI_INT_PEND_MOD, (0x100|(_level)))
-
-/*
- * When clearing the interrupt, make sure this clear does make it 
- * to the hub. Otherwise we could end up losing interrupts.
- * We do an uncached load of the int_pend0 register to ensure this.
- */
-
-#define LOCAL_HUB_CLR_INTR(_level)	  \
-                LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)),	\
-                LOCAL_HUB_L(PI_INT_PEND0)
-#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \
-		REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)),	\
-                REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0)
-
-/* Special support for use by gfx driver only.  Supports special gfx hub interrupt. */
-extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg);
-
-void setrtvector(intr_func_t func);
-
-/*
- * Interrupt blocking
- */
-extern void intr_block_bit(cpuid_t cpu, int bit);
-extern void intr_unblock_bit(cpuid_t cpu, int bit);
-
-#endif /* LANGUAGE_C */
-
-/*
- * Hard-coded interrupt levels:
- */
-
-/*
- *	L0 = SW1
- *	L1 = SW2
- *	L2 = INT_PEND0
- *	L3 = INT_PEND1
- *	L4 = RTC
- *	L5 = Profiling Timer
- *	L6 = Hub Errors
- *	L7 = Count/Compare (T5 counters)
- */
-
-
-/* INT_PEND0 hard-coded bits. */
-#ifdef DEBUG_INTR_TSTAMP
-/* hard coded interrupt level for interrupt latency test interrupt */
-#define	CPU_INTRLAT_B	62
-#define	CPU_INTRLAT_A	61
-#endif
-
-/* Hardcoded bits required by software. */
-#define MSC_MESG_INTR	9
-#define CPU_ACTION_B	8
-#define CPU_ACTION_A	7
-
-/* These are determined by hardware: */
-#define CC_PEND_B	6
-#define CC_PEND_A	5
-#define UART_INTR	4
-#define PG_MIG_INTR	3
-#define GFX_INTR_B	2
-#define GFX_INTR_A	1
-#define RESERVED_INTR	0
-
-/* INT_PEND1 hard-coded bits: */
-#define MSC_PANIC_INTR	63
-#define NI_ERROR_INTR	62
-#define MD_COR_ERR_INTR	61
-#define COR_ERR_INTR_B	60
-#define COR_ERR_INTR_A	59
-#define CLK_ERR_INTR	58
-
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-# define NACK_INT_B	57
-# define NACK_INT_A	56
-# define LB_ERROR	55
-# define XB_ERROR	54
-#else
-	<< BOMB! >>  Must define IP27 or IP35 or IP37
-#endif
-
-#define BRIDGE_ERROR_INTR 53	/* Setup by PROM to catch Bridge Errors */
-
-#define IP27_INTR_0	52	/* Reserved for PROM use */
-#define IP27_INTR_1	51	/*   (do not use in Kernel) */
-#define IP27_INTR_2	50
-#define IP27_INTR_3	49
-#define IP27_INTR_4	48
-#define IP27_INTR_5	47
-#define IP27_INTR_6	46
-#define IP27_INTR_7	45
-
-#define	TLB_INTR_B	44	/* used for tlb flush random */
-#define	TLB_INTR_A	43
-
-#define LLP_PFAIL_INTR_B 42	/* see ml/SN/SN0/sysctlr.c */
-#define LLP_PFAIL_INTR_A 41
-
-#define NI_BRDCAST_ERR_B 40
-#define NI_BRDCAST_ERR_A 39
-
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-# define IO_ERROR_INTR	38	/* set up by prom */
-# define DEBUG_INTR_B	37	/* used by symmon to stop all cpus */
-# define DEBUG_INTR_A	36
-#endif
 
-#ifdef CONFIG_IA64_SGI_SN1
-// These aren't strictly accurate or complete.  See the
-// Synergy Spec. for details.
-#define SGI_UART_IRQ	(65)
-#define SGI_HUB_ERROR_IRQ	(182)
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/intr.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/intr.h>
 #endif
 
-#endif /* _ASM_SN_INTR_H */
+#endif /* _ASM_IA64_SN_INTR_H */
diff -Nru a/include/asm-ia64/sn/intr_public.h b/include/asm-ia64/sn/intr_public.h
--- a/include/asm-ia64/sn/intr_public.h	Fri Mar 15 17:51:04 2002
+++ b/include/asm-ia64/sn/intr_public.h	Fri Mar 15 17:51:04 2002
@@ -4,56 +4,16 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_INTR_PUBLIC_H__
-#define _ASM_SN_INTR_PUBLIC_H__
+#ifndef _ASM_IA64_SN_INTR_PUBLIC_H
+#define _ASM_IA64_SN_INTR_PUBLIC_H
 
 #include <linux/config.h>
 
-/* REMEMBER: If you change these, the whole world needs to be recompiled.
- * It would also require changing the hubspl.s code and SN0/intr.c
- * Currently, the spl code has no support for multiple INTPEND1 masks.
- */
-
-#define	N_INTPEND0_MASKS	1
-#define	N_INTPEND1_MASKS	1
-
-#define INTPEND0_MAXMASK	(N_INTPEND0_MASKS - 1)
-#define INTPEND1_MAXMASK	(N_INTPEND1_MASKS - 1)
-
-#if _LANGUAGE_C
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/arch.h>
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/intr_public.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
 #endif
-#include <asm/sn/arch.h>
-
-struct intr_vecblk_s;	/* defined in asm/sn/intr.h */
-
-/*
- * The following are necessary to create the illusion of a CEL
- * on the IP27 hub.  We'll add more priority levels soon, but for
- * now, any interrupt in a particular band effectively does an spl.
- * These must be in the PDA since they're different for each processor.
- * Users of this structure must hold the vector_lock in the appropriate vector
- * block before modifying the mask arrays.  There's only one vector block
- * for each Hub so a lock in the PDA wouldn't be adequate.
- */
-typedef struct hub_intmasks_s {
-	/*
-	 * The masks are stored with the lowest-priority (most inclusive)
-	 * in the lowest-numbered masks (i.e., 0, 1, 2...).
-	 */
-	/* INT_PEND0: */
-	hubreg_t		intpend0_masks[N_INTPEND0_MASKS]; 
-	/* INT_PEND1: */
-	hubreg_t		intpend1_masks[N_INTPEND1_MASKS];
-	/* INT_PEND0: */
-	struct intr_vecblk_s	*dispatch0;	
-	/* INT_PEND1: */
-	struct intr_vecblk_s	*dispatch1;
-} hub_intmasks_t;
 
-#endif /* _LANGUAGE_C */
-#endif /* _ASM_SN_INTR_PUBLIC_H__ */
+#endif /* _ASM_IA64_SN_INTR_PUBLIC_H */
diff -Nru a/include/asm-ia64/sn/invent.h b/include/asm-ia64/sn/invent.h
--- a/include/asm-ia64/sn/invent.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/invent.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_INVENT_H
-#define _ASM_SN_INVENT_H
+#ifndef _ASM_IA64_SN_INVENT_H
+#define _ASM_IA64_SN_INVENT_H
+
+#include <linux/types.h>
+#include <linux/devfs_fs_kernel.h>
 
 /*
  * sys/sn/invent.h --  Kernel Hardware Inventory
@@ -743,4 +745,4 @@
 					int);
 extern int device_controller_num_get(	devfs_handle_t);
 #endif /* __KERNEL__ */
-#endif /* _ASM_SN_INVENT_H */
+#endif /* _ASM_IA64_SN_INVENT_H */
diff -Nru a/include/asm-ia64/sn/io.h b/include/asm-ia64/sn/io.h
--- a/include/asm-ia64/sn/io.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/io.h	Fri Mar 15 17:51:01 2002
@@ -1,21 +1,17 @@
-
-/* $Id: io.h,v 1.2 2000/02/02 16:35:57 ralf Exp $
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Copyright (C) 2000 Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.
  */
-#ifndef _ASM_SN_IO_H
-#define _ASM_SN_IO_H
+#ifndef _ASM_IA64_SN_IO_H
+#define _ASM_IA64_SN_IO_H
 
 #include <linux/config.h>
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/addrs.h>
-#endif
+#include <asm/sn/addrs.h>
 
 /* Because we only have PCI I/O ports.  */
 #define IIO_ITTE_BASE	0x400160	/* base of translation table entries */
@@ -51,17 +47,35 @@
 #define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
 
 /*
- * Macro which takes the widget number, and returns the 
+ * Macro which takes the widget number, and returns the
  * IO PRB address of that widget.
- * value _x is expected to be a widget number in the range 
+ * value _x is expected to be a widget number in the range
  * 0, 8 - 0xF
  */
 #define	IIO_IOPRB(_x)	(IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
 			(_x) : \
 			(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/bedrock.h>
 #include <asm/sn/sn1/hubio.h>
+#include <asm/sn/sn1/hubio_next.h>
+#include <asm/sn/sn1/hubmd.h>
+#include <asm/sn/sn1/hubmd_next.h>
+#include <asm/sn/sn1/hubpi.h>
+#include <asm/sn/sn1/hubpi_next.h>
+#include <asm/sn/sn1/hublb.h>
+#include <asm/sn/sn1/hublb_next.h>
+#include <asm/sn/sn1/hubni.h>
+#include <asm/sn/sn1/hubni_next.h>
+#include <asm/sn/sn1/hubxb.h>
+#include <asm/sn/sn1/hubxb_next.h>
+#include <asm/sn/sn1/hubstat.h>
+#include <asm/sn/sn1/hubdev.h>
+#include <asm/sn/sn1/synergy.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/shub.h>
+#include <asm/sn/sn2/shubio.h>
 #endif
 
-#endif /* _ASM_SN_IO_H */
+#endif /* _ASM_IA64_SN_IO_H */
diff -Nru a/include/asm-ia64/sn/iobus.h b/include/asm-ia64/sn/iobus.h
--- a/include/asm-ia64/sn/iobus.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,185 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_IOBUS_H
-#define _ASM_SN_IOBUS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct eframe_s;
-struct piomap;
-struct dmamap;
-
-
-/* for ilvl_t interrupt level, for use with intr_block_level.  Can't
- * typedef twice without causing warnings, and some users of this header
- * file do not already include driver.h, but expect ilvl_t to be defined,
- * while others include both, leading to the warning ...
- */
-
-#include <asm/types.h>
-#include <asm/sn/driver.h>
-
-
-typedef __psunsigned_t iobush_t;
-
-#if __KERNEL__
-/* adapter handle */
-typedef devfs_handle_t adap_t;
-#endif
-
-
-/* interrupt function */
-typedef void	       *intr_arg_t;
-typedef void		intr_func_f(intr_arg_t);
-typedef intr_func_f    *intr_func_t;
-
-#define	INTR_ARG(n)	((intr_arg_t)(__psunsigned_t)(n))
-
-/* system interrupt resource handle -- returned from intr_alloc */
-typedef struct intr_s *intr_t;
-#define INTR_HANDLE_NONE ((intr_t)0)
-
-/*
- * restore interrupt level value, returned from intr_block_level
- * for use with intr_unblock_level.
- */
-typedef void *rlvl_t;
-
-
-/* 
- * A basic, platform-independent description of I/O requirements for
- * a device. This structure is usually formed by lboot based on information 
- * in configuration files.  It contains information about PIO, DMA, and
- * interrupt requirements for a specific instance of a device.
- *
- * The pio description is currently unused.
- *
- * The dma description describes bandwidth characteristics and bandwidth
- * allocation requirements. (TBD)
- *
- * The Interrupt information describes the priority of interrupt, desired 
- * destination, policy (TBD), whether this is an error interrupt, etc.  
- * For now, interrupts are targeted to specific CPUs.
- */
-
-typedef struct device_desc_s {
-	/* pio description (currently none) */
-
-	/* dma description */
-	/* TBD: allocated badwidth requirements */
-
-	/* interrupt description */
-	devfs_handle_t	intr_target;	/* Hardware locator string */
-	int 		intr_policy;	/* TBD */
-	ilvl_t		intr_swlevel;	/* software level for blocking intr */
-	char		*intr_name;	/* name of interrupt, if any */
-
-	int		flags;
-} *device_desc_t;
-
-/* flag values */
-#define	D_INTR_ISERR	0x1		/* interrupt is for error handling */
-#define D_IS_ASSOC	0x2		/* descriptor is associated with a dev */
-#define D_INTR_NOTHREAD	0x4		/* Interrupt handler isn't threaded. */
-
-#define INTR_SWLEVEL_NOTHREAD_DEFAULT 	0	/* Default
-						 * Interrupt level in case of
-						 * non-threaded interrupt 
-						 * handlers
-						 */
-/* 
- * Drivers use these interfaces to manage device descriptors.
- *
- * To examine defaults:
- *	desc = device_desc_default_get(dev);
- *	device_desc_*_get(desc);
- *
- * To modify defaults:
- *	desc = device_desc_default_get(dev);
- *	device_desc_*_set(desc);
- *
- * To eliminate defaults:
- *	device_desc_default_set(dev, NULL);
- *
- * To override defaults:
- *	desc = device_desc_dup(dev);
- *	device_desc_*_set(desc,...);
- *	use device_desc in calls
- *	device_desc_free(desc);
- *
- * Software must not set or eliminate default device descriptors for a device while
- * concurrently get'ing, dup'ing or using them.  Default device descriptors can be 
- * changed only for a device that is quiescent.  In general, device drivers have no
- * need to permanently change defaults anyway -- they just override defaults, when
- * necessary.
- */
-extern device_desc_t	device_desc_dup(devfs_handle_t dev);
-extern void		device_desc_free(device_desc_t device_desc);
-extern device_desc_t	device_desc_default_get(devfs_handle_t dev);
-extern void		device_desc_default_set(devfs_handle_t dev, device_desc_t device_desc);
-
-extern devfs_handle_t	device_desc_intr_target_get(device_desc_t device_desc);
-extern int		device_desc_intr_policy_get(device_desc_t device_desc);
-extern ilvl_t		device_desc_intr_swlevel_get(device_desc_t device_desc);
-extern char *		device_desc_intr_name_get(device_desc_t device_desc);
-extern int		device_desc_flags_get(device_desc_t device_desc);
-
-extern void		device_desc_intr_target_set(device_desc_t device_desc, devfs_handle_t target);
-extern void		device_desc_intr_policy_set(device_desc_t device_desc, int policy);
-extern void		device_desc_intr_swlevel_set(device_desc_t device_desc, ilvl_t swlevel);
-extern void		device_desc_intr_name_set(device_desc_t device_desc, char *name);
-extern void		device_desc_flags_set(device_desc_t device_desc, int flags);
-
-
-/* IO state */
-#ifdef COMMENT
-#define IO_STATE_EMPTY			0x01	/* non-existent */
-#define IO_STATE_INITIALIZING		0x02	/* being initialized */
-#define IO_STATE_ATTACHING   		0x04    /* becoming active */
-#define IO_STATE_ACTIVE      		0x08    /* active */
-#define IO_STATE_DETACHING   		0x10    /* becoming inactive */
-#define IO_STATE_INACTIVE    		0x20    /* not in use */
-#define IO_STATE_ERROR			0x40    /* problems */
-#define IO_STATE_BAD_HARDWARE		0x80	/* broken hardware */
-#endif
-
-struct edt;
-
-
-/* return codes */
-#define RC_OK				0	
-#define RC_ERROR			1
-
-/* bus configuration management op code */
-#define IOBUS_CONFIG_ATTACH		0	/* vary on */
-#define IOBUS_CONFIG_DETACH		1	/* vary off */
-#define IOBUS_CONFIG_RECOVER		2	/* clear error then vary on */
-
-/* get low-level PIO handle */
-extern int pio_geth(struct piomap*, int bus, int bus_id, int subtype, 
-	iopaddr_t addr, int size);	
-
-/* get low-level DMA handle */
-extern int dma_geth(struct dmamap*, int bus_type, int bus_id, int dma_type, 
-	int npages, int page_size, int flags);	
-
-#ifdef __cplusplus
-}
-#endif
-
-/*
- * Macros for page number and page offsets, using ps as page size
- */
-#define x_pnum(addr, ps) ((__psunsigned_t)(addr) / (__psunsigned_t)(ps))
-#define x_poff(addr, ps) ((__psunsigned_t)(addr) & ((__psunsigned_t)(ps) - 1))
-
-#endif /* _ASM_SN_IOBUS_H */
diff -Nru a/include/asm-ia64/sn/ioc3.h b/include/asm-ia64/sn/ioc3.h
--- a/include/asm-ia64/sn/ioc3.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/ioc3.h	Fri Mar 15 17:51:02 2002
@@ -1,10 +1,44 @@
+/*
+ * Copyright (c) 2002 Silicon Graphics, Inc.  All Rights Reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
 /* $Id: ioc3.h,v 1.2 2000/11/16 19:49:17 pfg Exp $
  *
  * Copyright (C) 1999 Ralf Baechle
  * This file is part of the Linux driver for the SGI IOC3.
  */
-#ifndef IOC3_H
-#define IOC3_H
+#ifndef _ASM_IA64_SN_IOC3_H
+#define _ASM_IA64_SN_IOC3_H
+
+#include <asm/types.h>
 
 /* SUPERIO uart register map */
 typedef volatile struct ioc3_uartregs {
@@ -668,4 +702,4 @@
 #define IOC3_VENDOR_ID_NUM	0x10A9
 #define IOC3_DEVICE_ID_NUM	0x0003
 
-#endif /* IOC3_H */
+#endif /* _ASM_IA64_SN_IOC3_H */
diff -Nru a/include/asm-ia64/sn/ioerror.h b/include/asm-ia64/sn/ioerror.h
--- a/include/asm-ia64/sn/ioerror.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/ioerror.h	Fri Mar 15 17:51:02 2002
@@ -4,13 +4,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_IOERROR_H
-#define _ASM_SN_IOERROR_H
+#ifndef _ASM_IA64_SN_IOERROR_H
+#define _ASM_IA64_SN_IOERROR_H
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+#include <asm/sn/types.h>
 
 /*
  * Macros defining the various Errors to be handled as part of
@@ -162,7 +164,6 @@
 #define	IOERROR_FIELDVALID(e,f)	(((e)->ie_v.iev_b.ievb_ ## f) != 0)
 #define	IOERROR_GETVALUE(e,f)	(ASSERT(IOERROR_FIELDVALID(e,f)),((e)->ie_ ## f))
 
-#if	IP27 || IP35
 /* hub code likes to call the SysAD address "hubaddr" ... */
 #define	ie_hubaddr	ie_sysioaddr
 #define	ievb_hubaddr	ievb_sysioaddr
@@ -178,7 +179,6 @@
     MODE_DEVREENABLE		/* Reenable pass                */
 } ioerror_mode_t;
 
-#endif				/* C || C++ */
 
 typedef int             error_handler_f(void *, int, ioerror_mode_t, ioerror_t *);
 typedef void           *error_handler_arg_t;
@@ -193,4 +193,4 @@
 #define	IOERR_PRINTF(x)
 #endif				/* ERROR_DEBUG */
 
-#endif				/* _ASM_SN_IOERROR_H */
+#endif /* _ASM_IA64_SN_IOERROR_H */
diff -Nru a/include/asm-ia64/sn/ioerror_handling.h b/include/asm-ia64/sn/ioerror_handling.h
--- a/include/asm-ia64/sn/ioerror_handling.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/ioerror_handling.h	Fri Mar 15 17:51:03 2002
@@ -1,16 +1,17 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_IOERROR_HANDLING_H
-#define _ASM_SN_IOERROR_HANDLING_H
+#ifndef _ASM_IA64_SN_IOERROR_HANDLING_H
+#define _ASM_IA64_SN_IOERROR_HANDLING_H
 
 #include <linux/config.h>
+#include <linux/types.h>
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/sgi.h>
 
 #if __KERNEL__
 
@@ -264,7 +265,7 @@
 	 * one.								 
 	 */								 
 	if (v_error_skip_env_get(v, error_env) != GRAPH_SUCCESS) {	 
-		error_env = kmem_zalloc(sizeof(label_t), KM_NOSLEEP);	 
+		error_env = snia_kmem_zalloc(sizeof(label_t), KM_NOSLEEP);	 
 		/* Unable to allocate memory for jum buffer. This should 
 		 * be a very rare occurrence.				 
 		 */							 
@@ -302,4 +303,4 @@
 #endif
 
 #endif /* __KERNEL__ */
-#endif /* _ASM_SN_IOERROR_HANDLING_H */
+#endif /* _ASM_IA64_SN_IOERROR_HANDLING_H */
diff -Nru a/include/asm-ia64/sn/iograph.h b/include/asm-ia64/sn/iograph.h
--- a/include/asm-ia64/sn/iograph.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/iograph.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_IOGRAPH_H
-#define _ASM_SN_IOGRAPH_H
+#ifndef _ASM_IA64_SN_IOGRAPH_H
+#define _ASM_IA64_SN_IOGRAPH_H
 
 /*
  * During initialization, platform-dependent kernel code establishes some
@@ -68,6 +67,7 @@
 #define EDGE_LBL_HPC			"hpc"
 #define EDGE_LBL_GFX			"gfx"
 #define EDGE_LBL_HUB			"hub"		/* For SN0 */
+#define EDGE_LBL_SYNERGY		"synergy"	/* For SNIA only */
 #define EDGE_LBL_IBUS			"ibus"		/* For EVEREST */
 #define EDGE_LBL_INTERCONNECT		"link"
 #define EDGE_LBL_IO			"io"
@@ -216,4 +216,4 @@
 };
 
 
-#endif /* _ASM_SN_IOGRAPH_H */
+#endif /* _ASM_IA64_SN_IOGRAPH_H */
diff -Nru a/include/asm-ia64/sn/klclock.h b/include/asm-ia64/sn/klclock.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/klclock.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,60 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 2001 Silicon Graphics, Inc. All rights reserved.
+ * Copyright (C) 2001 by Ralf Baechle
+ */
+#ifndef _ASM_IA64_SN_KLCLOCK_H
+#define _ASM_IA64_SN_KLCLOCK_H
+
+#include <asm/sn/ioc3.h>
+
+#define RTC_BASE_ADDR		(unsigned char *)(nvram_base)
+
+/* Defines for the SGS-Thomson M48T35 clock */
+#define RTC_SGS_WRITE_ENABLE    0x80
+#define RTC_SGS_READ_PROTECT    0x40
+#define RTC_SGS_YEAR_ADDR       (RTC_BASE_ADDR + 0x7fffL)
+#define RTC_SGS_MONTH_ADDR      (RTC_BASE_ADDR + 0x7ffeL)
+#define RTC_SGS_DATE_ADDR       (RTC_BASE_ADDR + 0x7ffdL)
+#define RTC_SGS_DAY_ADDR        (RTC_BASE_ADDR + 0x7ffcL)
+#define RTC_SGS_HOUR_ADDR       (RTC_BASE_ADDR + 0x7ffbL)
+#define RTC_SGS_MIN_ADDR        (RTC_BASE_ADDR + 0x7ffaL)
+#define RTC_SGS_SEC_ADDR        (RTC_BASE_ADDR + 0x7ff9L)
+#define RTC_SGS_CONTROL_ADDR    (RTC_BASE_ADDR + 0x7ff8L)
+
+/* Defines for the Dallas DS1386 */
+#define RTC_DAL_UPDATE_ENABLE   0x80
+#define RTC_DAL_UPDATE_DISABLE  0x00
+#define RTC_DAL_YEAR_ADDR       (RTC_BASE_ADDR + 0xaL)
+#define RTC_DAL_MONTH_ADDR      (RTC_BASE_ADDR + 0x9L)
+#define RTC_DAL_DATE_ADDR       (RTC_BASE_ADDR + 0x8L)
+#define RTC_DAL_DAY_ADDR        (RTC_BASE_ADDR + 0x6L)
+#define RTC_DAL_HOUR_ADDR       (RTC_BASE_ADDR + 0x4L)
+#define RTC_DAL_MIN_ADDR        (RTC_BASE_ADDR + 0x2L)
+#define RTC_DAL_SEC_ADDR        (RTC_BASE_ADDR + 0x1L)
+#define RTC_DAL_CONTROL_ADDR    (RTC_BASE_ADDR + 0xbL)
+#define RTC_DAL_USER_ADDR       (RTC_BASE_ADDR + 0xeL)
+
+/* Defines for the Dallas DS1742 */
+#define RTC_DS1742_WRITE_ENABLE    0x80
+#define RTC_DS1742_READ_ENABLE     0x40
+#define RTC_DS1742_UPDATE_DISABLE  0x00
+#define RTC_DS1742_YEAR_ADDR       (RTC_BASE_ADDR + 0x7ffL)
+#define RTC_DS1742_MONTH_ADDR      (RTC_BASE_ADDR + 0x7feL)
+#define RTC_DS1742_DATE_ADDR       (RTC_BASE_ADDR + 0x7fdL)
+#define RTC_DS1742_DAY_ADDR        (RTC_BASE_ADDR + 0x7fcL)
+#define RTC_DS1742_HOUR_ADDR       (RTC_BASE_ADDR + 0x7fbL)
+#define RTC_DS1742_MIN_ADDR        (RTC_BASE_ADDR + 0x7faL)
+#define RTC_DS1742_SEC_ADDR        (RTC_BASE_ADDR + 0x7f9L)
+#define RTC_DS1742_CONTROL_ADDR    (RTC_BASE_ADDR + 0x7f8L)
+#define RTC_DS1742_USER_ADDR       (RTC_BASE_ADDR + 0x0L)
+
+#define BCD_TO_INT(x) (((x>>4) * 10) + (x & 0xf))
+#define INT_TO_BCD(x) (((x / 10)<<4) + (x % 10))
+
+#define YRREF	1970 
+
+#endif /* _ASM_IA64_SN_KLCLOCK_H  */
diff -Nru a/include/asm-ia64/sn/klconfig.h b/include/asm-ia64/sn/klconfig.h
--- a/include/asm-ia64/sn/klconfig.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/klconfig.h	Fri Mar 15 17:51:02 2002
@@ -6,11 +6,11 @@
  *
  * Derived from IRIX <sys/SN/klconfig.h>.
  *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1992-1997,1999,2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef	_ASM_SN_KLCONFIG_H
-#define	_ASM_SN_KLCONFIG_H
+#ifndef _ASM_IA64_SN_KLCONFIG_H
+#define _ASM_IA64_SN_KLCONFIG_H
 
 #include <linux/config.h>
 
@@ -38,20 +38,22 @@
 #include <asm/sn/types.h>
 #include <asm/sn/slotnum.h>
 #include <asm/sn/router.h>
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #include <asm/sn/sgi.h>
-#include <asm/sn/sn1/addrs.h>
+#include <asm/sn/addrs.h>
 #include <asm/sn/vector.h>
-#include <asm/sn/agent.h>
-// #include <sys/graph.h>
-// #include <asm/sn/arc/types.h>
 #include <asm/sn/arc/hinv.h>
 #include <asm/sn/xtalk/xbow.h>
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/kldir.h>
 #include <asm/sn/sn_fru.h>
 
-#endif  /* CONFIG_SGI_IP35 ... */
+#ifdef CONFIG_IA64_SGI_SN1
+#include <asm/sn/sn1/hubmd_next.h>
+#endif
+
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn2/shub_md.h>
+#endif
 
 #define KLCFGINFO_MAGIC	0xbeedbabe
 
@@ -59,19 +61,11 @@
 
 #define	MAX_MODULE_ID		255
 #define SIZE_PAD		4096 /* 4k padding for structures */
-#if (defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)) && defined(BRINGUP) /* MAX_SLOTS_PER_NODE??? */
 /* 
  * 1 NODE brick, 3 Router bricks (1 local, 1 meta, 1 repeater),
  * 6 XIO Widgets, 1 Xbow, 1 gfx
  */
 #define MAX_SLOTS_PER_NODE	(1 + 3 + 6 + 1 + 1) 
-#else
-/* 
- * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets, 
- * 2 Midplanes assuming no pci card cages 
- */
-#define MAX_SLOTS_PER_NODE	(1 + 2 + 6 + 2) 
-#endif
 
 /* XXX if each node is guranteed to have some memory */
 
@@ -349,7 +343,7 @@
 #define KLCLASS(_x) ((_x) & KLCLASS_MASK)
 
 /*
- * IP27 board types
+ * board types
  */
 
 #define KLTYPE_MASK	0x0f
@@ -357,11 +351,7 @@
 #define KLTYPE_EMPTY	0x00
 
 #define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
-#define KLTYPE_IP27	(KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#define KLTYPE_IP35	KLTYPE_IP27
-#define KLTYPE_IP37	KLTYPE_IP35
-#endif
+#define KLTYPE_SNIA	(KLCLASS_CPU | 0x1)
 
 #define KLTYPE_WEIRDIO	(KLCLASS_IO  | 0x0)
 #define KLTYPE_BASEIO	(KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
@@ -949,7 +939,6 @@
 extern int	config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
 extern int	config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
 extern int	config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
-extern klcpu_t *get_cpuinfo(cpuid_t cpu);
 extern int 	update_klcfg_cpuinfo(nasid_t, int);
 extern void 	board_to_path(lboard_t *brd, char *path);
 extern moduleid_t get_module_id(nasid_t nasid);
@@ -963,4 +952,4 @@
 extern nasid_t	get_actual_nasid(lboard_t *brd) ;
 extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
 
-#endif /* _ASM_SN_KLCONFIG_H */
+#endif /* _ASM_IA64_SN_KLCONFIG_H */
diff -Nru a/include/asm-ia64/sn/kldir.h b/include/asm-ia64/sn/kldir.h
--- a/include/asm-ia64/sn/kldir.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/kldir.h	Fri Mar 15 17:51:03 2002
@@ -1,18 +1,16 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
  * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
  *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1992-1997,1999,2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SN_KLDIR_H
-#define _ASM_SN_KLDIR_H
+#ifndef _ASM_IA64_SN_KLDIR_H
+#define _ASM_IA64_SN_KLDIR_H
 
-#include <linux/config.h>
 #include <asm/sn/sgi.h>
 
 /*
@@ -125,16 +123,16 @@
  * 0x0   (0K)              +-----------------------------------------+
  */
 
-#ifdef LANGUAGE_ASSEMBLY
+#ifdef __ASSEMBLY__
 #define KLDIR_OFF_MAGIC			0x00
 #define KLDIR_OFF_OFFSET		0x08
 #define KLDIR_OFF_POINTER		0x10
 #define KLDIR_OFF_SIZE			0x18
 #define KLDIR_OFF_COUNT			0x20
 #define KLDIR_OFF_STRIDE		0x28
-#endif /* LANGUAGE_ASSEMBLY */
+#endif /* __ASSEMBLY__ */
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 typedef struct kldir_ent_s {
 	u64		magic;		/* Indicates validity of entry      */
 	off_t		offset;		/* Offset from start of node space  */
@@ -146,19 +144,220 @@
 	/* NOTE: These 16 bytes are used in the Partition KLDIR
 	   entry to store partition info. Refer to klpart.h for this. */
 } kldir_ent_t;
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 
 #define KLDIR_ENT_SIZE			0x40
 #define KLDIR_MAX_ENTRIES		(0x400 / 0x40)
 
+
+
 /*
- * The actual offsets of each memory area are machine-dependent
+ * The upper portion of the memory map applies during boot
+ * only and is overwritten by IRIX/SYMMON.  The minimum memory bank
+ * size on IP35 is 64M, which provides a limit on the amount of space
+ * the PROM can assume it has available.
+ *
+ * Most of the addresses below are defined as macros in this file, or
+ * in SN/addrs.h or SN/SN1/addrs.h.
+ *
+ *                                    MEMORY MAP PER NODE
+ *
+ * 0x4000000 (64M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      IO7 TEXT/DATA/BSS/stack            |
+ * 0x3000000 (48M)         +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x2102000 (>33M)        +-----------------------------------------+
+ *                         |      IP35 Topology (PCFG) + misc data   |
+ * 0x2000000 (32M)         +-----------------------------------------+
+ *                         |      IO7 BUFFERS FOR FLASH ENET IOC3    |
+ * 0x1F80000 (31.5M)       +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x1C00000 (28M)         +-----------------------------------------+
+ *                         |      IP35 PROM TEXT/DATA/BSS/stack      |
+ * 0x1A00000 (26M)         +-----------------------------------------+
+ *                         |      Routing temp. space                |
+ * 0x1800000 (24M)         +-----------------------------------------+
+ *                         |      Diagnostics temp. space            |
+ * 0x1500000 (21M)         +-----------------------------------------+
+ *                         |      Free                               |
+ * 0x1400000 (20M)         +-----------------------------------------+
+ *                         |      IO7 PROM temporary copy            |
+ * 0x1300000 (19M)         +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Free                               |
+ *                         |      (UNIX DATA starts above 0x1000000) |
+ *                         |                                         |
+ *                         +-----------------------------------------+
+ *                         |      UNIX DEBUG Version                 |
+ * 0x0310000 (3.1M)        +-----------------------------------------+
+ *                         |      SYMMON, loaded just below UNIX     |
+ *                         |      (For UNIX Debug only)              |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x006C000 (432K)        +-----------------------------------------+
+ *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
+ *                         |      (For UNIX Debug only)              |
+ * 0x004C000 (304K)        +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      UNIX NON-DEBUG Version             |
+ * 0x0040000 (256K)        +-----------------------------------------+
+ *
+ *
+ * The lower portion of the memory map contains information that is
+ * permanent and is used by the IP35PROM, IO7PROM and IRIX.
+ *
+ * 0x40000 (256K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      KLCONFIG (64K)                     |
+ *                         |                                         |
+ * 0x30000 (192K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      PI Error Spools (64K)              |
+ *                         |                                         |
+ * 0x20000 (128K)          +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x19000 (100K)          +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 3)|
+ * 0x18800 (98K)           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 3)	     |
+ * 0x18400 (97K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 3)         |
+ * 0x18000 (96K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x13c00 (79K)           +-----------------------------------------+
+ *                         |      GPDA (8k)                          |
+ * 0x11c00 (71K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 2)|
+ * 0x10800 (66k)	   +-----------------------------------------+
+ *			   |      cache error eframe (CPU 2)	     |
+ * 0x10400 (65K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 2)         |
+ * 0x10000 (64K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ * 0x0b400 (45K)           +-----------------------------------------+
+ *                         |      GDA (1k)                           |
+ * 0x0b000 (44K)           +-----------------------------------------+
+ *                         |      NMI Eframe areas (4)       	     |
+ * 0x0a000 (40K)           +-----------------------------------------+
+ *                         |      NMI Register save areas (4)        |
+ * 0x09000 (36K)           +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 1)|
+ * 0x08800 (34K)           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 1)	     |
+ * 0x08400 (33K)           +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 1)         |
+ * 0x08000 (32K)           +-----------------------------------------+
+ *                         |                                         |
+ *                         |                                         |
+ *                         |      Unused                             |
+ *                         |                                         |
+ *                         |                                         |
+ * 0x04000 (16K)           +-----------------------------------------+
+ *                         |      NMI Handler (Protected Page)       |
+ * 0x03000 (12K)           +-----------------------------------------+
+ *                         |      ARCS PVECTORS (master node only)   |
+ * 0x02c00 (11K)           +-----------------------------------------+
+ *                         |      ARCS TVECTORS (master node only)   |
+ * 0x02800 (10K)           +-----------------------------------------+
+ *                         |      LAUNCH [NUM_CPU]                   |
+ * 0x02400 (9K)            +-----------------------------------------+
+ *                         |      Low memory directory (KLDIR)       |
+ * 0x02000 (8K)            +-----------------------------------------+
+ *                         |      ARCS SPB (1K)                      |
+ * 0x01000 (4K)            +-----------------------------------------+
+ *                         |      Early cache Exception stack (CPU 0)|
+ * 0x00800 (2k)	           +-----------------------------------------+
+ *			   |      cache error eframe (CPU 0)	     |
+ * 0x00400 (1K)            +-----------------------------------------+
+ *                         |      Exception Handlers (CPU 0)         |
+ * 0x00000 (0K)            +-----------------------------------------+
+ */
+
+/*
+ * NOTE:  To change the kernel load address, you must update:
+ *  - the appropriate elspec files in irix/kern/master.d
+ *  - NODEBUGUNIX_ADDR in SN/SN1/addrs.h
+ *  - IP27_FREEMEM_OFFSET below
+ *  - KERNEL_START_OFFSET below (if supporting cells)
  */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#include <asm/sn/sn1/kldir.h>
-#else
-#error "kldir.h is currently defined for IP27 and IP35 platforms only"
-#endif
 
-#endif /* _ASM_SN_KLDIR_H */
+
+/*
+ * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
+ * we define here.  Since it's set up in the prom.  We can't redefine it later
+ * and expect more space to be allocated.  The way to find out the true size
+ * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
+ * for a particular node.
+ */
+#define SYMMON_STACK_SIZE		0x8000
+
+#if defined (PROM) || defined (SABLE)
+
+/*
+ * These defines are prom version dependent.  No code other than the IP35
+ * prom should attempt to use these values.
+ */
+#define IP27_LAUNCH_OFFSET		0x2400
+#define IP27_LAUNCH_SIZE		0x400
+#define IP27_LAUNCH_COUNT		4
+#define IP27_LAUNCH_STRIDE		0x100 /* could be as small as 0x80 */
+
+#define IP27_KLCONFIG_OFFSET		0x30000
+#define IP27_KLCONFIG_SIZE		0x10000
+#define IP27_KLCONFIG_COUNT		1
+#define IP27_KLCONFIG_STRIDE		0
+
+#define IP27_NMI_OFFSET			0x3000
+#define IP27_NMI_SIZE			0x100
+#define IP27_NMI_COUNT			4
+#define IP27_NMI_STRIDE			0x40
+
+#define IP27_PI_ERROR_OFFSET		0x20000
+#define IP27_PI_ERROR_SIZE		0x10000
+#define IP27_PI_ERROR_COUNT		1
+#define IP27_PI_ERROR_STRIDE		0
+
+#define IP27_SYMMON_STK_OFFSET		0x4c000
+#define IP27_SYMMON_STK_SIZE		0x20000
+#define IP27_SYMMON_STK_COUNT		4
+/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
+#define IP27_SYMMON_STK_STRIDE		0x8000
+
+#define IP27_FREEMEM_OFFSET		0x40000
+#define IP27_FREEMEM_SIZE		(-1)
+#define IP27_FREEMEM_COUNT		1
+#define IP27_FREEMEM_STRIDE		0
+
+#endif /* PROM || SABLE*/
+/*
+ * There will be only one of these in a partition so the IO7 must set it up.
+ */
+#define IO6_GDA_OFFSET			0xb000
+#define IO6_GDA_SIZE			0x400
+#define IO6_GDA_COUNT			1
+#define IO6_GDA_STRIDE			0
+
+/*
+ * save area of kernel nmi regs in the prom format
+ */
+#define IP27_NMI_KREGS_OFFSET		0x9000
+#define IP27_NMI_KREGS_CPU_SIZE		0x400
+/*
+ * save area of kernel nmi regs in eframe format 
+ */
+#define IP27_NMI_EFRAME_OFFSET		0xa000
+#define IP27_NMI_EFRAME_SIZE		0x400
+
+#define GPDA_OFFSET			0x11c00
+
+#endif /* _ASM_IA64_SN_KLDIR_H */
diff -Nru a/include/asm-ia64/sn/ksys/elsc.h b/include/asm-ia64/sn/ksys/elsc.h
--- a/include/asm-ia64/sn/ksys/elsc.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/ksys/elsc.h	Fri Mar 15 17:51:02 2002
@@ -4,36 +4,16 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 #ifndef _ASM_SN_KSYS_ELSC_H
 #define _ASM_SN_KSYS_ELSC_H
 
-#include <linux/config.h>
-
-#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #include <asm/sn/ksys/l1.h>
-#endif
-
-// #include <asm/sn/ksys/i2c.h>
 
-#define ELSC_I2C_ADDR		0x08
-#define ELSC_I2C_HUB0		0x09
-#define ELSC_I2C_HUB1		0x0a
-#define ELSC_I2C_HUB2		0x0b
-#define ELSC_I2C_HUB3		0x0c
-
-#define ELSC_PACKET_MAX		96
 #define ELSC_ACP_MAX		86		/* 84+cr+lf */
 #define ELSC_LINE_MAX		(ELSC_ACP_MAX - 2)
 
-/*
- * ELSC character queue type for I/O
- */
-
-#define ELSC_QSIZE	128		/* Power of 2 is more efficient */
-
 typedef sc_cq_t elsc_cq_t;
 
 /*
@@ -49,14 +29,11 @@
 int	elsc_msg_callback(elsc_t *e,
 			  void (*callback)(void *callback_data, char *msg),
 			  void *callback_data);
-#ifdef LATER
 char   *elsc_errmsg(int code);
 
 int	elsc_nvram_write(elsc_t *e, int addr, char *buf, int len);
 int	elsc_nvram_read(elsc_t *e, int addr, char *buf, int len);
 int	elsc_nvram_magic(elsc_t *e);
-#endif
-
 int	elsc_command(elsc_t *e, int only_if_message);
 int	elsc_parse(elsc_t *e, char *p1, char *p2, char *p3);
 int	elsc_ust_write(elsc_t *e, uchar_t c);
@@ -69,10 +46,8 @@
  */
 
 int	elsc_version(elsc_t *e, char *result);
-#ifdef LATER
 int	elsc_debug_set(elsc_t *e, u_char byte1, u_char byte2);
 int	elsc_debug_get(elsc_t *e, u_char *byte1, u_char *byte2);
-#endif
 int	elsc_module_set(elsc_t *e, int module);
 int	elsc_module_get(elsc_t *e);
 int	elsc_partition_set(elsc_t *e, int partition);
@@ -85,13 +60,10 @@
 int	elsc_cell_get(elsc_t *e);
 int	elsc_bist_set(elsc_t *e, char bist_status);
 char	elsc_bist_get(elsc_t *e);
-int	elsc_lock(elsc_t *e,
-		  int retry_interval_usec,
-		  int timeout_usec, u_char lock_val);
+int	elsc_lock(elsc_t *e, int retry_interval_usec, int timeout_usec, u_char lock_val);
 int	elsc_unlock(elsc_t *e);
 int	elsc_display_char(elsc_t *e, int led, int chr);
 int	elsc_display_digit(elsc_t *e, int led, int num, int l_case);
-#ifdef LATER
 int	elsc_display_mesg(elsc_t *e, char *chr);	/* 8-char input */
 int	elsc_password_set(elsc_t *e, char *password);	/* 4-char input */
 int	elsc_password_get(elsc_t *e, char *password);	/* 4-char output */
@@ -102,7 +74,6 @@
 int	elsc_system_reset(elsc_t *e);
 int	elsc_dip_switches(elsc_t *e);
 int	elsc_nic_get(elsc_t *e, uint64_t *nic, int verbose);
-#endif
 
 int	_elsc_hbt(elsc_t *e, int ival, int rdly);
 
@@ -110,29 +81,8 @@
 #define	elsc_hbt_disable(e)		_elsc_hbt(e, 0, 0)
 #define	elsc_hbt_send(e)		_elsc_hbt(e, 0, 1)
 
-/*
- * Routines for using the ELSC as a UART.  There's a version of each
- * routine that takes a pointer to an elsc_t, and another version that
- * gets the pointer by calling a user-supplied global routine "get_elsc".
- * The latter version is useful when the elsc is employed for stdio.
- */
-
-#define ELSCUART_FLASH		0x3c			/* LED pattern */
-
 elsc_t	       *get_elsc(void);
 
-int	elscuart_probe(void);
-void	elscuart_init(void *);
-int	elscuart_poll(void);
-int	elscuart_readc(void);
-int	elscuart_getc(void);
-int	elscuart_putc(int);
-int	elscuart_puts(char *);
-char   *elscuart_gets(char *, int);
-int	elscuart_flush(void);
-
-
-
 /*
  * Error codes
  *
@@ -142,23 +92,23 @@
 
 #define ELSC_ERROR_NONE			0
 
-#define ELSC_ERROR_CMD_SEND	       -100	/* Error sending command    */
-#define ELSC_ERROR_CMD_CHECKSUM	       -101	/* Command checksum bad     */
-#define ELSC_ERROR_CMD_UNKNOWN	       -102	/* Unknown command          */
-#define ELSC_ERROR_CMD_ARGS	       -103	/* Invalid argument(s)      */
-#define ELSC_ERROR_CMD_PERM	       -104	/* Permission denied	    */
-#define ELSC_ERROR_CMD_STATE	       -105	/* not allowed in this state*/
-
-#define ELSC_ERROR_RESP_TIMEOUT	       -110	/* ELSC response timeout    */
-#define ELSC_ERROR_RESP_CHECKSUM       -111	/* Response checksum bad    */
-#define ELSC_ERROR_RESP_FORMAT	       -112	/* Response format error    */
-#define ELSC_ERROR_RESP_DIR	       -113	/* Response direction error */
-
-#define ELSC_ERROR_MSG_LOST	       -120	/* Queue full; msg. lost    */
-#define ELSC_ERROR_LOCK_TIMEOUT	       -121	/* ELSC response timeout    */
-#define ELSC_ERROR_DATA_SEND	       -122	/* Error sending data       */
-#define ELSC_ERROR_NIC		       -123	/* NIC processing error     */
-#define ELSC_ERROR_NVMAGIC	       -124	/* Bad magic no. in NVRAM   */
-#define ELSC_ERROR_MODULE	       -125	/* Moduleid processing err  */
+#define ELSC_ERROR_CMD_SEND	       (-100)	/* Error sending command    */
+#define ELSC_ERROR_CMD_CHECKSUM	       (-101)	/* Command checksum bad     */
+#define ELSC_ERROR_CMD_UNKNOWN	       (-102)	/* Unknown command          */
+#define ELSC_ERROR_CMD_ARGS	       (-103)	/* Invalid argument(s)      */
+#define ELSC_ERROR_CMD_PERM	       (-104)	/* Permission denied	    */
+#define ELSC_ERROR_CMD_STATE	       (-105)	/* not allowed in this state*/
+
+#define ELSC_ERROR_RESP_TIMEOUT	       (-110)	/* ELSC response timeout    */
+#define ELSC_ERROR_RESP_CHECKSUM       (-111)	/* Response checksum bad    */
+#define ELSC_ERROR_RESP_FORMAT	       (-112)	/* Response format error    */
+#define ELSC_ERROR_RESP_DIR	       (-113)	/* Response direction error */
+
+#define ELSC_ERROR_MSG_LOST	       (-120)	/* Queue full; msg. lost    */
+#define ELSC_ERROR_LOCK_TIMEOUT	       (-121)	/* ELSC response timeout    */
+#define ELSC_ERROR_DATA_SEND	       (-122)	/* Error sending data       */
+#define ELSC_ERROR_NIC		       (-123)	/* NIC processing error     */
+#define ELSC_ERROR_NVMAGIC	       (-124)	/* Bad magic no. in NVRAM   */
+#define ELSC_ERROR_MODULE	       (-125)	/* Moduleid processing err  */
 
 #endif /* _ASM_SN_KSYS_ELSC_H */
diff -Nru a/include/asm-ia64/sn/ksys/i2c.h b/include/asm-ia64/sn/ksys/i2c.h
--- a/include/asm-ia64/sn/ksys/i2c.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,77 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_KSYS_I2C_H
-#define _ASM_SN_KSYS_I2C_H
-
-#if _STANDALONE
-# include "rtc.h"
-#else
-# define rtc_time()	(GET_LOCAL_RTC * NSEC_PER_CYCLE / 1000)
-# define rtc_sleep	us_delay
-# define rtc_time_t	uint64_t
-#endif
-
-typedef u_char			i2c_addr_t;	/* 7-bit address            */
-
-int		i2c_init(nasid_t);
-
-int		i2c_probe(nasid_t nasid, rtc_time_t timeout);
-
-int		i2c_arb(nasid_t, rtc_time_t timeout, rtc_time_t *token_start);
-
-int		i2c_master_xmit(nasid_t,
-				i2c_addr_t addr,
-				u_char *buf,
-				int len_max,
-				int *len_ptr,
-				rtc_time_t timeout,
-				int only_if_message);
-
-int		i2c_master_recv(nasid_t,
-				i2c_addr_t addr,
-				u_char *buf,
-				int len_max,
-				int *len_ptr,
-				int emblen,
-				rtc_time_t timeout,
-				int only_if_message);
-
-int		i2c_master_xmit_recv(nasid_t,
-				     i2c_addr_t addr,
-				     u_char *xbuf,
-				     int xlen_max,
-				     int *xlen_ptr,
-				     u_char *rbuf,
-				     int rlen_max,
-				     int *rlen_ptr,
-				     int emblen,
-				     rtc_time_t timeout,
-				     int only_if_message);
-
-char	       *i2c_errmsg(int code);
-
-/*
- * Error codes
- */
-
-#define I2C_ERROR_NONE		 0
-#define I2C_ERROR_INIT		-1	/* Initialization error             */
-#define I2C_ERROR_STATE		-2	/* Unexpected chip state	    */
-#define I2C_ERROR_NAK		-3	/* Addressed slave not responding   */
-#define I2C_ERROR_TO_ARB	-4	/* Timeout waiting for sysctlr arb  */
-#define I2C_ERROR_TO_BUSY	-5	/* Timeout waiting for busy bus     */
-#define I2C_ERROR_TO_SENDA	-6	/* Timeout sending address byte     */
-#define I2C_ERROR_TO_SENDD	-7	/* Timeout sending data byte        */
-#define I2C_ERROR_TO_RECVA	-8	/* Timeout receiving address byte   */
-#define I2C_ERROR_TO_RECVD	-9	/* Timeout receiving data byte      */
-#define I2C_ERROR_NO_MESSAGE	-10	/* No message was waiting	    */
-#define I2C_ERROR_NO_ELSC	-11	/* ELSC is disabled for access 	    */ 	
-
-#endif /* _ASM_SN_KSYS_I2C_H */
diff -Nru a/include/asm-ia64/sn/ksys/l1.h b/include/asm-ia64/sn/ksys/l1.h
--- a/include/asm-ia64/sn/ksys/l1.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/ksys/l1.h	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 
 #ifndef _ASM_SN_KSYS_L1_H
@@ -13,7 +12,8 @@
 
 #include <asm/sn/vector.h>
 #include <asm/sn/addrs.h>
-#include <asm/sn/sn1/bedrock.h>
+#include <asm/atomic.h>
+#include <asm/sn/sv.h>
 
 #define BRL1_QSIZE	128	/* power of 2 is more efficient */
 #define BRL1_BUFSZ	264	/* needs to be large enough
@@ -39,7 +39,7 @@
  * This value can't be confused with a network vector because the least-
  * significant nibble of a network vector cannot be greater than 8.
  */
-#define BRL1_LOCALUART	((net_vec_t)0xf)
+#define BRL1_LOCALHUB_UART	((net_vec_t)0xf)
 
 /* L1<->Bedrock reserved subchannels */
 
@@ -71,7 +71,14 @@
 
 
 struct l1sc_s;     
-typedef void (*brl1_notif_t)(struct l1sc_s *, int);
+/* Saved off interrupt frame */
+typedef struct brl1_intr_frame {
+	int bf_irq;		/* irq received */
+	void *bf_dev_id;	/* device information */
+	struct pt_regs *bf_regs; /* register frame */
+} brl1_intr_frame_t;
+
+typedef void (*brl1_notif_t)(int, void *, struct pt_regs *, struct l1sc_s *, int);
 typedef int  (*brl1_uartf_t)(struct l1sc_s *);
 
 /* structure for controlling a subchannel */
@@ -90,6 +97,7 @@
 				 * continue */
     brl1_notif_t rx_notify;	/* notify higher layer that a packet has been
 				 * received */
+    brl1_intr_frame_t irq_frame; /* saved off irq information */
 } brl1_sch_t;
 
 /* br<->l1 protocol states */
@@ -101,7 +109,7 @@
 #define BRL1_RESET	7
 
 
-#ifndef _LANGUAGE_ASSEMBLY
+#ifndef __ASSEMBLY__
 
 /*
  * l1sc_t structure-- tracks protocol state, open subchannels, etc.
@@ -118,6 +126,8 @@
     brl1_uartf_t putc_f;	/* pointer to UART putc function */
     brl1_uartf_t getc_f;	/* pointer to UART getc function */
 
+    spinlock_t   send_lock;     /* arbitrates send synchronization */
+    spinlock_t   recv_lock;     /* arbitrates uart receive access */
     spinlock_t	 subch_lock;	/* arbitrates subchannel allocation */
     cpuid_t	 intr_cpu;	/* cpu that receives L1 interrupts */
 
@@ -327,15 +337,6 @@
 void	sc_init( l1sc_t *sc, nasid_t nasid, net_vec_t uart );
 void	sc_intr_enable( l1sc_t *sc );
 
-int	_elscuart_putc( l1sc_t *sc, int c );
-int	_elscuart_getc( l1sc_t *sc );
-int	_elscuart_poll( l1sc_t *sc );
-int	_elscuart_readc( l1sc_t *sc );
-int	_elscuart_flush( l1sc_t *sc );
-int	_elscuart_probe( l1sc_t *sc );
-void	_elscuart_init( l1sc_t *sc );
-void	elscuart_syscon_listen( l1sc_t *sc );
-
 int	elsc_rack_bay_get(l1sc_t *e, uint *rack, uint *bay);
 int	elsc_rack_bay_type_get(l1sc_t *e, uint *rack, 
 			       uint *bay, uint *brick_type);
@@ -357,5 +358,5 @@
 int	iobrick_sc_version( l1sc_t *sc, char *result );
 
 
-#endif /* !_LANGUAGE_ASSEMBLY */
+#endif /* !__ASSEMBLY__ */
 #endif /* _ASM_SN_KSYS_L1_H */
diff -Nru a/include/asm-ia64/sn/labelcl.h b/include/asm-ia64/sn/labelcl.h
--- a/include/asm-ia64/sn/labelcl.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/labelcl.h	Fri Mar 15 17:51:03 2002
@@ -4,15 +4,16 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_LABELCL_H
-#define _ASM_SN_LABELCL_H
+#ifndef _ASM_IA64_SN_LABELCL_H
+#define _ASM_IA64_SN_LABELCL_H
+
+#include <asm/sn/hcl.h>
 
 #define LABELCL_MAGIC 0x4857434c	/* 'HWLC' */
 #define LABEL_LENGTH_MAX 256		/* Includes NULL char */
-#define INFO_DESC_PRIVATE -1      	/* default */
+#define INFO_DESC_PRIVATE (-1)      	/* default */
 #define INFO_DESC_EXPORT  0       	/* export info itself */
 
 /*
@@ -90,4 +91,4 @@
 extern int labelcl_info_get_IDX(struct devfs_entry *, int, arbitrary_info_t *);
 extern struct devfs_entry *device_info_connectpt_get(struct devfs_entry *);
 
-#endif /* _ASM_SN_LABELCL_H */
+#endif /* _ASM_IA64_SN_LABELCL_H */
diff -Nru a/include/asm-ia64/sn/leds.h b/include/asm-ia64/sn/leds.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/leds.h	Fri Mar 15 17:51:01 2002
@@ -0,0 +1,42 @@
+#ifndef _ASM_IA64_SN_LEDS_H
+#define _ASM_IA64_SN_LEDS_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+#include <asm/smp.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/pda.h>
+
+#ifdef CONFIG_IA64_SGI_SN1
+#define LED0		0xc0000b00100000c0LL	/* ZZZ fixme */
+#define LED_CPU_SHIFT	3
+#else
+#include <asm/sn/sn2/shub.h>
+#define LED0		(LOCAL_MMR_ADDR(SH_REAL_JUNK_BUS_LED0))
+#define LED_CPU_SHIFT	16
+#endif
+
+#define LED_CPU_HEARTBEAT	0x01
+#define LED_CPU_ACTIVITY	0x02
+#define LED_MASK_AUTOTEST	0xfe
+
+/*
+ * Basic macros for flashing the LEDS on an SGI, SN1.
+ */
+
+static __inline__ void
+set_led_bits(u8 value, u8 mask)
+{
+	pda.led_state = (pda.led_state & ~mask) | (value & mask);
+	*pda.led_address = (long) pda.led_state;
+}
+
+#endif /* _ASM_IA64_SN_LEDS_H */
+
diff -Nru a/include/asm-ia64/sn/mca.h b/include/asm-ia64/sn/mca.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/mca.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,128 @@
+/*
+ * File:	mca.h
+ * Purpose:	Machine check handling specific to the SN platform defines
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ * 
+ * This program is free software; you can redistribute it and/or modify it 
+ * under the terms of version 2 of the GNU General Public License 
+ * as published by the Free Software Foundation.
+ * 
+ * This program is distributed in the hope that it would be useful, but 
+ * WITHOUT ANY WARRANTY; without even the implied warranty of 
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+ * 
+ * Further, this software is distributed without any warranty that it is 
+ * free of the rightful claim of any third person regarding infringement 
+ * or the like.  Any license provided herein, whether implied or 
+ * otherwise, applies only to this software file.  Patent licenses, if 
+ * any, provided herein do not apply to combinations of this program with 
+ * other software, or any other product whatsoever.
+ * 
+ * You should have received a copy of the GNU General Public 
+ * License along with this program; if not, write the Free Software 
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ * 
+ * Contact information:  Silicon Graphics, Inc., 1600 Amphitheatre Pkwy, 
+ * Mountain View, CA  94043, or:
+ * 
+ * http://www.sgi.com 
+ * 
+ * For further information regarding this notice, see: 
+ * 
+ * http://oss.sgi.com/projects/GenInfo/NoticeExplan
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <asm/sal.h>
+#include <asm/mca.h>
+
+#ifdef CONFIG_IA64_SGI_SN
+
+typedef u64 __uint64_t;
+
+typedef struct {
+	__uint64_t sh_event_occurred;
+	__uint64_t sh_first_error;
+	__uint64_t sh_event_overflow;
+	__uint64_t sh_pi_first_error;
+	__uint64_t sh_pi_error_summary;
+	__uint64_t sh_pi_error_overflow;
+	__uint64_t sh_pi_error_detail_1;
+	__uint64_t sh_pi_error_detail_2;
+	__uint64_t sh_pi_hw_time_stamp;
+	__uint64_t sh_pi_uncorrected_detail_1;
+	__uint64_t sh_pi_uncorrected_detail_2;
+	__uint64_t sh_pi_uncorrected_detail_3;
+	__uint64_t sh_pi_uncorrected_detail_4;
+	__uint64_t sh_pi_uncor_time_stamp;
+	__uint64_t sh_pi_corrected_detail_1;
+	__uint64_t sh_pi_corrected_detail_2;
+	__uint64_t sh_pi_corrected_detail_3;
+	__uint64_t sh_pi_corrected_detail_4;
+	__uint64_t sh_pi_cor_time_stamp;
+	__uint64_t sh_mem_error_summary;
+	__uint64_t sh_mem_error_overflow;
+	__uint64_t sh_misc_err_hdr_lower;
+	__uint64_t sh_misc_err_hdr_upper;
+	__uint64_t sh_dir_uc_err_hdr_lower;
+	__uint64_t sh_dir_uc_err_hdr_upper;
+	__uint64_t sh_dir_cor_err_hdr_lower;
+	__uint64_t sh_dir_cor_err_hdr_upper;
+	__uint64_t sh_mem_error_mask;
+	__uint64_t sh_md_uncor_time_stamp;
+	__uint64_t sh_md_cor_time_stamp;
+	__uint64_t sh_md_hw_time_stamp;
+	__uint64_t sh_xn_error_summary;
+	__uint64_t sh_xn_first_error;
+	__uint64_t sh_xn_error_overflow;
+	__uint64_t sh_xniilb_error_summary;
+	__uint64_t sh_xniilb_first_error;
+	__uint64_t sh_xniilb_error_overflow;
+	__uint64_t sh_xniilb_error_detail_1;
+	__uint64_t sh_xniilb_error_detail_2;
+	__uint64_t sh_xniilb_error_detail_3;
+	__uint64_t sh_xnpi_error_summary;
+	__uint64_t sh_xnpi_first_error;
+	__uint64_t sh_xnpi_error_overflow;
+	__uint64_t sh_xnpi_error_detail_1;
+	__uint64_t sh_xnmd_error_summary;
+	__uint64_t sh_xnmd_first_error;
+	__uint64_t sh_xnmd_error_overflow;
+	__uint64_t sh_xnmd_ecc_err_report;
+	__uint64_t sh_xnmd_error_detail_1;
+	__uint64_t sh_lb_error_summary;
+	__uint64_t sh_lb_first_error;
+	__uint64_t sh_lb_error_overflow;
+	__uint64_t sh_lb_error_detail_1;
+	__uint64_t sh_lb_error_detail_2;
+	__uint64_t sh_lb_error_detail_3;
+	__uint64_t sh_lb_error_detail_4;
+	__uint64_t sh_lb_error_detail_5;
+} sal_log_shub_state_t;
+
+typedef struct {
+sal_log_section_hdr_t header;
+	struct
+	{
+		__uint64_t    err_status      : 1,
+		guid            : 1,
+		oem_data        : 1,
+		reserved        : 61;
+	} valid;
+	__uint64_t             err_status;
+	efi_guid_t      guid;
+	__uint64_t shub_nic;
+	sal_log_shub_state_t    shub_state;
+} sal_log_plat_info_t;
+
+
+extern void sal_log_plat_print(int header_len, int sect_len, u8 *p_data, prfunc_t prfunc);
+
+#ifdef platform_plat_specific_err_print
+#undef platform_plat_specific_err_print
+#endif
+#define platform_plat_specific_err_print sal_log_plat_print
+
+#endif /* CONFIG_IA64_SGI_SN */
diff -Nru a/include/asm-ia64/sn/mem_refcnt.h b/include/asm-ia64/sn/mem_refcnt.h
--- a/include/asm-ia64/sn/mem_refcnt.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,26 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_MEM_REFCNT_H
-#define _ASM_SN_MEM_REFCNT_H
-
-extern int mem_refcnt_attach(devfs_handle_t hub);
-extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp);
-extern int mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp);
-extern int mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot);
-extern int mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt);
-extern int mem_refcnt_ioctl(devfs_handle_t dev,
-                 int cmd,
-                 void *arg,
-                 int mode,
-                 cred_t *cred_p,
-                 int *rvalp);
-        
-
-#endif /* _ASM_SN_MEM_REFCNT_H */
diff -Nru a/include/asm-ia64/sn/mmtimer_private.h b/include/asm-ia64/sn/mmtimer_private.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/mmtimer_private.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,42 @@
+/*
+ * Intel Multimedia Timer device interface
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ *
+ * Helper file for the SN implementation of mmtimers
+ *
+ * 11/01/01 - jbarnes - initial revision
+ */
+
+#ifndef _SN_MMTIMER_PRIVATE_H
+
+#define RTC_BITS 55 /* 55 bits for this implementation */
+#define NUM_COMPARATORS 2 /* two comparison registers in SN1 */
+
+/*
+ * Check for an interrupt and clear the pending bit if
+ * one is waiting.
+ */
+#define MMTIMER_INT_PENDING(x) (x ? *(RTC_INT_PENDING_B_ADDR) : *(RTC_INT_PENDING_A_ADDR))
+
+/*
+ * Set interrupts on RTC 'x' to 'v' (true or false)
+ */
+#define MMTIMER_SET_INT(x,v) (x ? (*(RTC_INT_ENABLED_B_ADDR) = (unsigned long)(v)) : (*(RTC_INT_ENABLED_A_ADDR) = (unsigned long)(v)))
+
+#define MMTIMER_ENABLE_INT(x) MMTIMER_SET_INT(x, 1)
+#define MMTIMER_DISABLE_INT(x) MMTIMER_SET_INT(x, 0)
+
+typedef struct mmtimer {
+	spinlock_t timer_lock;
+	unsigned long periodic;
+	int signo;
+	volatile unsigned long *compare;
+	struct task_struct *process;
+} mmtimer_t;
+
+#endif /* _SN_LINUX_MMTIMER_PRIVATE_H */
diff -Nru a/include/asm-ia64/sn/mmzone.h b/include/asm-ia64/sn/mmzone.h
--- a/include/asm-ia64/sn/mmzone.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,113 +0,0 @@
-/*
- * Written by Kanoj Sarcar (kanoj@sgi.com) Jan 2000
- * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
- */
-#ifndef _LINUX_ASM_SN_MMZONE_H
-#define _LINUX_ASM_SN_MMZONE_H
-
-#include <linux/config.h>
-
-#include <asm/sn/mmzone_sn1.h>
-#include <asm/sn/sn_cpuid.h>
-
-/*
- * Memory is conceptually divided into chunks. A chunk is either
- * completely present, or else the kernel assumes it is completely
- * absent. Each node consists of a number of contiguous chunks.
- */
-
-#define CHUNKMASK       	(~(CHUNKSZ - 1))
-#define CHUNKNUM(vaddr)        	(__pa(vaddr) >> CHUNKSHIFT)
-#define PCHUNKNUM(paddr)        ((paddr) >> CHUNKSHIFT)
-
-#define MAXCHUNKS      		(MAXNODES * MAX_CHUNKS_PER_NODE)
-
-extern int chunktonid[];
-#define CHUNKTONID(cnum)       (chunktonid[cnum])
-
-typedef struct plat_pglist_data {
-       pg_data_t       gendata;		/* try to keep this first. */
-       unsigned long   virtstart;
-       unsigned long   size;
-} plat_pg_data_t;
-
-extern plat_pg_data_t plat_node_data[];
-
-extern int numa_debug(void);
-
-/*
- * The foll two will move into linux/mmzone.h RSN.
- */
-#define NODE_START(n)  plat_node_data[(n)].virtstart
-#define NODE_SIZE(n)   plat_node_data[(n)].size
-
-#define KVADDR_TO_NID(kaddr) \
-       ((CHUNKTONID(CHUNKNUM((kaddr))) != -1) ? (CHUNKTONID(CHUNKNUM((kaddr)))) : \
-       (printk("DISCONTIGBUG: %s line %d addr 0x%lx", __FILE__, __LINE__, \
-       (unsigned long)(kaddr)), numa_debug()))
-#if 0
-#define KVADDR_TO_NID(kaddr) CHUNKTONID(CHUNKNUM((kaddr)))
-#endif
-
-/* These 2 macros should never be used if KVADDR_TO_NID(kaddr) is -1 */
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr) \
-                       NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
-
-/*
- * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory
- * and returns the kaddr corresponding to first physical page in the
- * node's mem_map.
- */
-#define LOCAL_BASE_ADDR(kaddr) NODE_START(KVADDR_TO_NID(kaddr))
-
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * Return a pointer to the node data for node n.
- * Assume that n is the compact node id.
- */
-#define NODE_DATA(n)   (&((plat_node_data + (n))->gendata))
-
-/*
- * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
- */
-#define NODE_MEM_MAP(nid)      (NODE_DATA((nid))->node_mem_map)
-
-/* This macro should never be used if KVADDR_TO_NID(kaddr) is -1 */
-#define LOCAL_MAP_NR(kvaddr) \
-        (((unsigned long)(kvaddr)-LOCAL_BASE_ADDR((kvaddr))) >> PAGE_SHIFT)
-#define MAP_NR_SN1(kaddr)   (LOCAL_MAP_NR((kaddr)) + \
-                (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
-                sizeof(mem_map_t)))
-#if 0
-#define MAP_NR_VALID(kaddr)   (LOCAL_MAP_NR((kaddr)) + \
-                (((unsigned long)ADDR_TO_MAPBASE((kaddr)) - PAGE_OFFSET) / \
-                sizeof(mem_map_t)))
-#define MAP_NR_SN1(kaddr)	((KVADDR_TO_NID(kaddr) == -1) ? (max_mapnr + 1) :\
-				MAP_NR_VALID(kaddr))
-#endif
-
-/* FIXME */
-#define sn1_pte_pagenr(x)		MAP_NR_SN1(PAGE_OFFSET + (unsigned long)((pte_val(x)&_PFN_MASK) & PAGE_MASK))
-#define pte_page(pte)			(mem_map + sn1_pte_pagenr(pte))
-/* FIXME */
-
-#define kern_addr_valid(addr)   ((KVADDR_TO_NID((unsigned long)addr) >= \
-        numnodes) ? 0 : (test_bit(LOCAL_MAP_NR((addr)), \
-        NODE_DATA(KVADDR_TO_NID((unsigned long)addr))->valid_addr_bitmap)))
-
-#define virt_to_page(kaddr)	(mem_map + MAP_NR_SN1(kaddr))
-
-#else /* CONFIG_DISCONTIGMEM */
-
-#define MAP_NR_SN1(addr)	(((unsigned long) (addr) - PAGE_OFFSET) >> PAGE_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
-
-#define numa_node_id()		cpuid_to_cnodeid(smp_processor_id())
-
-#endif /* !_LINUX_ASM_SN_MMZONE_H */
diff -Nru a/include/asm-ia64/sn/mmzone_default.h b/include/asm-ia64/sn/mmzone_default.h
--- a/include/asm-ia64/sn/mmzone_default.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,15 +0,0 @@
-/*
- * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
- */
-
-#define MAXNODES                16
-#define MAXNASIDS               16
-
-#define CHUNKSZ                (8*1024*1024)
-#define CHUNKSHIFT              23      /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
-
-#define CNODEID_TO_NASID(n)	n
-#define NASID_TO_CNODEID(n)     n
-
-#define MAX_CHUNKS_PER_NODE     8
-
diff -Nru a/include/asm-ia64/sn/mmzone_sn1.h b/include/asm-ia64/sn/mmzone_sn1.h
--- a/include/asm-ia64/sn/mmzone_sn1.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,105 +0,0 @@
-#ifndef _ASM_IA64_MMZONE_SN1_H
-#define _ASM_IA64_MMZONE_SN1_H
-
-#include <linux/config.h>
-
-/*
- * Copyright, 2000, Silicon Graphics, sprasad@engr.sgi.com
- */
-/* Maximum configuration supported by SNIA hardware. There are other
- * restrictions that may limit us to a smaller max configuration.
- */
-#define MAXNODES                128
-#define MAXNASIDS		128
-
-#define CHUNKSZ                (64*1024*1024)
-#define CHUNKSHIFT              26      /* 2 ^^ CHUNKSHIFT == CHUNKSZ */
-
-extern int 	cnodeid_map[] ;
-extern int	nasid_map[] ;
-
-#define CNODEID_TO_NASID(n)	(cnodeid_map[(n)])
-#define NASID_TO_CNODEID(n)     (nasid_map[(n)])
-
-#define MAX_CHUNKS_PER_NODE     128
-
-
-/*
- * These are a bunch of sn1 hw specific defines. For now, keep it 
- * in this file. If it gets too diverse we may want to create a 
- * mmhwdefs_sn1.h
- */
-
-/*
- * Structure of the mem config of the node as a SN1 MI reg
- * Medusa supports this reg config.
- */
-
-typedef struct node_memmap_s
-{
-        unsigned int    b0      :1,     /* 0 bank 0 present */
-                        b1      :1,     /* 1 bank 1 present */
-                        r01     :2,     /* 2-3 reserved */
-                        b01size :4,     /* 4-7 Size of bank 0 and 1 */
-                        b2      :1,     /* 8 bank 2 present */
-                        b3      :1,     /* 9 bank 3 present */
-                        r23     :2,     /* 10-11 reserved */
-                        b23size :4,     /* 12-15 Size of bank 2 and 3 */
-                        b4      :1,     /* 16 bank 4 present */
-                        b5      :1,     /* 17 bank 5 present */
-                        r45     :2,     /* 18-19 reserved */
-                        b45size :4,     /* 20-23 Size of bank 4 and 5 */
-                        b6      :1,     /* 24 bank 6 present */
-                        b7      :1,     /* 25 bank 7 present */
-                        r67     :2,     /* 26-27 reserved */
-                        b67size :4;     /* 28-31 Size of bank 6 and 7 */
-} node_memmap_t ;
-
-#define GBSHIFT                 30
-#define MBSHIFT                 20
-
-/*
- * SN1 Arch defined values
- */
-#define SN1_MAX_BANK_PER_NODE   8
-#define SN1_BANK_PER_NODE_SHIFT 3       /* derived from SN1_MAX_BANK_PER_NODE */
-#define SN1_NODE_ADDR_SHIFT     (GBSHIFT+3)             /* 8GB */
-#define SN1_BANK_ADDR_SHIFT     (SN1_NODE_ADDR_SHIFT-SN1_BANK_PER_NODE_SHIFT)
-
-#define SN1_BANK_SIZE_SHIFT     (MBSHIFT+6)     /* 64 MB */
-#define SN1_MIN_BANK_SIZE_SHIFT SN1_BANK_SIZE_SHIFT
-
-/*
- * BankSize nibble to bank size mapping
- *
- *      1 - 64 MB
- *      2 - 128 MB
- *      3 - 256 MB
- *      4 - 512 MB
- *      5 - 1024 MB (1GB)
- */
-
-/* fixme - this macro breaks for bsize 6-8 and 0 */
-
-#ifdef CONFIG_IA64_SGI_SN1_SIM
-/* Support the medusa hack for 8M/16M/32M nodes */
-#define BankSizeBytes(bsize)            ((bsize<6) ? (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT)) :\
-					 (1<<((bsize-9)+MBSHIFT)))
-#else
-#define BankSizeBytes(bsize)            (1<<((bsize-1)+SN1_BANK_SIZE_SHIFT))
-#endif
-
-#define BankSizeToEFIPages(bsize)       ((BankSizeBytes(bsize)) >> 12)
-
-#define GetPhysAddr(n,b)                (((u64)n<<SN1_NODE_ADDR_SHIFT) | \
-                                                ((u64)b<<SN1_BANK_ADDR_SHIFT))
-
-#define GetNasId(paddr)			((u64)(paddr) >> SN1_NODE_ADDR_SHIFT)
-
-#define GetBankId(paddr)						\
-				(((u64)(paddr) >> SN1_BANK_ADDR_SHIFT) & 7)
-
-#define SN1_MAX_BANK_SIZE		((u64)BankSizeBytes(5))
-#define SN1_BANK_SIZE_MASK		(~(SN1_MAX_BANK_SIZE-1))
-
-#endif /* _ASM_IA64_MMZONE_SN1_H */
diff -Nru a/include/asm-ia64/sn/module.h b/include/asm-ia64/sn/module.h
--- a/include/asm-ia64/sn/module.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/module.h	Fri Mar 15 17:51:02 2002
@@ -1,31 +1,24 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_MODULE_H
-#define _ASM_SN_MODULE_H
+#ifndef _ASM_IA64_SN_MODULE_H
+#define _ASM_IA64_SN_MODULE_H
 
 #ifdef	__cplusplus
 extern "C" {
 #endif
 
-#include <linux/config.h>
 
 #include <asm/sn/systeminfo.h>
 #include <asm/sn/klconfig.h>
 #include <asm/sn/ksys/elsc.h>
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#ifdef BRINGUP /* max. number of modules?  Should be about 300.*/
-#define MODULE_MAX			56
-#endif /* BRINGUP */
+#define MODULE_MAX			128
 #define MODULE_MAX_NODES		1
-#endif /* CONFIG_SGI_IP35 */
 #define MODULE_HIST_CNT			16
 #define MAX_MODULE_LEN			16
 
@@ -39,8 +32,6 @@
 #define MODULE_FORMAT_LONG	2
 
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-
 /*
  *	Module id format
  *
@@ -134,17 +125,6 @@
 				 ((_m2)&(MODULE_RACK_MASK|MODULE_BPOS_MASK)))
 #define MODULE_MATCH(_m1, _m2)	(MODULE_CMP((_m1),(_m2)) == 0)
 
-#else
-
-/*
- * Some code that uses this macro will not be conditionally compiled.
- */
-#define MODULE_GET_BTCHAR(_m)	('?')
-#define MODULE_CMP(_m1, _m2)	((_m1) - (_m2))
-#define MODULE_MATCH(_m1, _m2)	(MODULE_CMP((_m1),(_m2)) == 0)
-
-#endif /* CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
 typedef struct module_s module_t;
 
 struct module_s {
@@ -205,4 +185,4 @@
 }
 #endif
 
-#endif /* _ASM_SN_MODULE_H */
+#endif /* _ASM_IA64_SN_MODULE_H */
diff -Nru a/include/asm-ia64/sn/nag.h b/include/asm-ia64/sn/nag.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/nag.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,32 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+*/
+
+
+#ifndef _ASM_IA64_SN_NAG_H
+#define _ASM_IA64_SN_NAG_H
+
+
+#define NAG(mesg...) \
+do {										\
+	static unsigned int how_broken = 1;					\
+	static unsigned int threshold = 1;					\
+	if (how_broken == threshold) {						\
+		if (threshold < 10000)						\
+			threshold *= 10;					\
+		if (how_broken > 1)						\
+			printk(KERN_WARNING "%u times: ", how_broken);		\
+		else								\
+			printk(KERN_WARNING);					\
+		printk(mesg);							\
+	}									\
+	how_broken++;								\
+} while (0)
+
+
+#endif /* _ASM_IA64_SN_NAG_H */
diff -Nru a/include/asm-ia64/sn/nic.h b/include/asm-ia64/sn/nic.h
--- a/include/asm-ia64/sn/nic.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/nic.h	Fri Mar 15 17:51:02 2002
@@ -4,13 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_NIC_H
-#define _ASM_SN_NIC_H
+#ifndef _ASM_IA64_SN_NIC_H
+#define _ASM_IA64_SN_NIC_H
 
 #include <asm/types.h>
+#include <asm/sn/types.h>
+#include <linux/devfs_fs_kernel.h>
 
 #define MCR_DATA(x)			((int) ((x) & 1))
 #define MCR_DONE(x)			((x) & 2)
@@ -125,4 +126,4 @@
 extern nic_vmce_t	nic_vmc_add(char *, nic_vmc_func *);
 extern void		nic_vmc_del(nic_vmce_t);
 
-#endif /* _ASM_SN_NIC_H */
+#endif /* _ASM_IA64_SN_NIC_H */
diff -Nru a/include/asm-ia64/sn/nodemask.h b/include/asm-ia64/sn/nodemask.h
--- a/include/asm-ia64/sn/nodemask.h	Fri Mar 15 17:51:04 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,330 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_NODEMASK_H
-#define _ASM_SN_NODEMASK_H
-
-#if defined(__KERNEL__) || defined(_KMEMUSER)
-
-#include <linux/config.h>
-
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-#include <asm/sn/sn1/arch.h>    /* needed for MAX_COMPACT_NODES */
-#endif
-
-#define CNODEMASK_BOOTED_MASK		boot_cnodemask
-#define CNODEMASK_BIPW    64
-
-#if !defined(SN0XXL) && !defined(CONFIG_SGI_IP35) && !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-			/* MAXCPUS 128p (64 nodes) or less */
-
-#define CNODEMASK_SIZE    1
-typedef uint64_t cnodemask_t;
-
-#define CNODEMASK_WORD(p,w)     (p)
-#define CNODEMASK_SET_WORD(p,w,val)     (p) = val
-#define CNODEMASK_CLRALL(p)     (p) = 0
-#define CNODEMASK_SETALL(p)     (p) = ~((cnodemask_t)0)
-#define CNODEMASK_IS_ZERO(p)	((p) == 0)
-#define CNODEMASK_IS_NONZERO(p)	((p) != 0)
-#define CNODEMASK_NOTEQ(p, q)	((p) != (q))
-#define CNODEMASK_EQ(p, q)      ((p) == (q))
-#define CNODEMASK_LSB_ISONE(p)  ((p) & 0x1ULL)
-
-#define CNODEMASK_ZERO()        ((cnodemask_t)0)
-#define CNODEMASK_CVTB(bit)     (1ULL << (bit))
-#define CNODEMASK_SETB(p, bit)	((p) |= 1ULL << (bit))
-#define CNODEMASK_CLRB(p, bit)	((p) &= ~(1ULL << (bit)))
-#define CNODEMASK_TSTB(p, bit)	((p) & (1ULL << (bit)))
-
-#define CNODEMASK_SETM(p, q)	((p) |= (q))
-#define CNODEMASK_CLRM(p, q)	((p) &= ~(q))
-#define CNODEMASK_ANDM(p, q)	((p) &= (q))
-#define CNODEMASK_TSTM(p, q)	((p) & (q))
-
-#define CNODEMASK_CPYNOTM(p, q)	((p) = ~(q))
-#define CNODEMASK_CPY(p, q)     ((p) = (q))
-#define CNODEMASK_ORNOTM(p, q)	((p) |= ~(q))
-#define CNODEMASK_SHIFTL(p)     ((p) <<= 1)
-#define CNODEMASK_SHIFTR(p)     ((p) >>= 1)
-#define CNODEMASK_SHIFTL_PTR(p)     (*(p) <<= 1)
-#define CNODEMASK_SHIFTR_PTR(p)     (*(p) >>= 1)
-
-/* Atomically set or clear a particular bit */
-#define CNODEMASK_ATOMSET_BIT(p, bit) atomicSetUlong((cnodemask_t *)&(p), (1ULL<<(bit))) 
-#define CNODEMASK_ATOMCLR_BIT(p, bit) atomicClearUlong((cnodemask_t *)&(p), (1ULL<<(bit)))
-
-/* Atomically set or clear a collection of bits */
-#define CNODEMASK_ATOMSET(p, q)  atomicSetUlong((cnodemask_t *)&(p), q)
-#define CNODEMASK_ATOMCLR(p, q)  atomicClearUlong((cnodemask_t *)&(p), q)
-
-/* Atomically set or clear a collection of bits, returning the old value */
-#define CNODEMASK_ATOMSET_MASK(__old, p, q)	{ \
-		(__old) = atomicSetUlong((cnodemask_t *)&(p), q); \
-}
-#define CNODEMASK_ATOMCLR_MASK(__old, p, q)	{ \
-		(__old) = atomicClearUlong((cnodemask_t *)&(p),q); \
-}
-
-#define CNODEMASK_FROM_NUMNODES(n)	((~(cnodemask_t)0)>>(CNODEMASK_BIPW-(n)))
-
-#else  /* SN0XXL || SN1 - MAXCPUS > 128 */
-
-#define CNODEMASK_SIZE    (MAX_COMPACT_NODES / CNODEMASK_BIPW)
-
-typedef struct {
-        uint64_t _bits[CNODEMASK_SIZE];
-} cnodemask_t;
-
-#define CNODEMASK_WORD(p,w)  \
-	((w >= 0 && w < CNODEMASK_SIZE) ? (p)._bits[(w)] : 0)
-#define CNODEMASK_SET_WORD(p,w,val)  { 				\
-	if (w >= 0 && w < CNODEMASK_SIZE) 			\
-		(p)._bits[(w)] = val;				\
-}
-
-#define CNODEMASK_CLRALL(p)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = 0;                               \
-}
-
-#define CNODEMASK_SETALL(p)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = ~(0);                            \
-}
-
-#define CNODEMASK_LSB_ISONE(p)  ((p)._bits[0] & 0x1ULL)
-
-
-#define CNODEMASK_SETM(p,q)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] |= ((q)._bits[i]);                 \
-}
-
-#define CNODEMASK_CLRM(p,q)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] &= ~((q)._bits[i]);                \
-}
-
-#define CNODEMASK_ANDM(p,q)       {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] &= ((q)._bits[i]);                 \
-}
-
-#define CNODEMASK_CPY(p, q)  {					\
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = (q)._bits[i];	                \
-}
-
-#define CNODEMASK_CPYNOTM(p,q)    {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] = ~((q)._bits[i]);                 \
-}
-
-#define CNODEMASK_ORNOTM(p,q)     {                             \
-        int i;                                                  \
-                                                                \
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)                  \
-                (p)._bits[i] |= ~((q)._bits[i]);                \
-}
-
-#define CNODEMASK_INDEX(bit)      ((bit) >> 6)
-#define CNODEMASK_SHFT(bit)       ((bit) & 0x3f)
-
-
-#define CNODEMASK_SETB(p, bit)	 				\
-	(p)._bits[CNODEMASK_INDEX(bit)] |= (1ULL << CNODEMASK_SHFT(bit))
-
-
-#define CNODEMASK_CLRB(p, bit)					\
-	(p)._bits[CNODEMASK_INDEX(bit)] &= ~(1ULL << CNODEMASK_SHFT(bit)) 
-
-
-#define CNODEMASK_TSTB(p, bit)		\
-	((p)._bits[CNODEMASK_INDEX(bit)] & (1ULL << CNODEMASK_SHFT(bit))) 
-
-/** Probably should add atomic update for entire cnodemask_t struct **/
-
-/* Atomically set or clear a particular bit */
-#define CNODEMASK_ATOMSET_BIT(p, bit) \
-        (atomicSetUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit))));
-#define CNODEMASK_ATOMCLR_BIT(__old, p, bit) \
-        (atomicClearUlong((unsigned long *)&(p)._bits[CNODEMASK_INDEX(bit)], (1ULL << CNODEMASK_SHFT(bit))));
-
-/* Atomically set or clear a collection of bits */
-#define CNODEMASK_ATOMSET(p, q) { \
-        int i;				\
-					\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \
-	      atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]);  \
-        }				\
-}
-#define CNODEMASK_ATOMCLR(p, q) { \
-        int i;				\
-                        		\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) {	\
-	      atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \
-        }				\
-}
-
-/* Atomically set or clear a collection of bits, returning the old value */
-#define CNODEMASK_ATOMSET_MASK(__old, p, q)  { \
-        int i;				\
-					\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) { \
-           (__old)._bits[i] =	 \
-	      atomicSetUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]);  \
-        }				\
-}
-#define CNODEMASK_ATOMCLR_MASK(__old, p, q) {					\
-        int i;				\
-                        		\
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++) {	\
-           (__old)._bits[i] =				\
-	      atomicClearUlong((unsigned long *)&(p)._bits[i], (q)._bits[i]); \
-        }				\
-}
-
-__inline static cnodemask_t CNODEMASK_CVTB(int bit) 
-{
-	cnodemask_t __tmp;
-	CNODEMASK_CLRALL(__tmp);
-	CNODEMASK_SETB(__tmp,bit);
-	return(__tmp);
-}
-
-
-__inline static cnodemask_t CNODEMASK_ZERO(void)
-{
-	cnodemask_t __tmp;
-	CNODEMASK_CLRALL(__tmp);
-	return(__tmp);
-}
-
-__inline static int CNODEMASK_IS_ZERO (cnodemask_t p)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != 0)
-                        return 0;
-        return 1;
-}
-
-__inline static int CNODEMASK_IS_NONZERO (cnodemask_t p)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != 0)
-                        return 1;
-        return 0;
-}
-
-__inline static int CNODEMASK_NOTEQ (cnodemask_t p, cnodemask_t q)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != q._bits[i])
-                        return 1;
-        return 0;
-}
-
-__inline static int CNODEMASK_EQ (cnodemask_t p, cnodemask_t q)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] != q._bits[i])
-                        return 0;
-        return 1;
-}
-
-
-__inline static int CNODEMASK_TSTM (cnodemask_t p, cnodemask_t q)
-{
-        int i;
-
-        for (i = 0 ; i < CNODEMASK_SIZE ; i++)
-                if (p._bits[i] & q._bits[i])
-                        return 1;
-        return 0;
-}
-
-__inline static void CNODEMASK_SHIFTL_PTR (cnodemask_t *p)
-{
-        int i;
-        uint64_t upper;
-
-        /*
-         * shift words starting with the last word
-         * of the vector and work backward to the first
-         * word updating the low order bits with the
-         * high order bit of the prev word.
-         */
-        for (i=(CNODEMASK_SIZE-1); i > 0; --i) {
-	   upper = (p->_bits[i-1] & (1ULL<<(CNODEMASK_BIPW-1))) ? 1 : 0;
-           p->_bits[i] <<= 1;
-           p->_bits[i] |= upper;
-        }
-        p->_bits[i] <<= 1;
-}
-
-__inline static void CNODEMASK_SHIFTR_PTR (cnodemask_t *p)
-{
-        int i;
-        uint64_t lower;
-
-        /*
-         * shift words starting with the first word
-         * of the vector and work forward to the last
-         * word updating the high order bit with the
-         * low order bit of the next word.
-         */
-        for (i=0; i < (CNODEMASK_SIZE-2); ++i) {
-	   lower = (p->_bits[i+1] & (0x1)) ? 1 : 0;
-           p->_bits[i] >>= 1;
-           p->_bits[i] |= (lower<<((CNODEMASK_BIPW-1)));
-        }
-        p->_bits[i] >>= 1;
-}
-
-__inline static cnodemask_t CNODEMASK_FROM_NUMNODES(int n)
-{
-	cnodemask_t __tmp;
-	int i;
-	CNODEMASK_CLRALL(__tmp);
-	for (i=0; i<n; i++) {
-		CNODEMASK_SETB(__tmp, i);
-	}
-	return(__tmp);
-}
-
-#endif /* SN0XXL || SN1 */
-
-extern cnodemask_t boot_cnodemask;
-
-#endif /* __KERNEL__ || _KMEMUSER */
-
-#endif /* _ASM_SN_NODEMASK_H */
diff -Nru a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
--- a/include/asm-ia64/sn/nodepda.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/nodepda.h	Fri Mar 15 17:51:01 2002
@@ -1,32 +1,28 @@
-/* $Id$
- *
+/*
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_NODEPDA_H
-#define _ASM_SN_NODEPDA_H
+#ifndef _ASM_IA64_SN_NODEPDA_H
+#define _ASM_IA64_SN_NODEPDA_H
 
-#ifdef	__cplusplus
-extern "C" {
-#endif
 
 #include <linux/config.h>
-
-#include <asm/sn/agent.h>
+#include <asm/irq.h>
 #include <asm/sn/intr.h>
 #include <asm/sn/router.h>
-#include <asm/sn/synergy.h>
-/* #include <SN/klkernvars.h> */
-#ifdef LATER
-typedef struct module_s module_t;       /* Avoids sys/SN/module.h */
-#else
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/synergy.h>
+#endif
+#include <asm/sn/pda.h>
 #include <asm/sn/module.h>
+#include <asm/sn/bte.h>
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/hubstat.h>
 #endif
-/* #include <SN/slotnum.h> */
 
 /*
  * NUMA Node-Specific Data structures are defined in this file.
@@ -37,26 +33,16 @@
 /*
  * Subnode PDA structures. Each node needs a few data structures that 
  * correspond to the PIs on the HUB chip that supports the node.
- *
- * WARNING!!!! 6.5.x compatibility requirements prevent us from
- * changing or reordering fields in the following structure for IP27.
- * It is essential that the data mappings not change for IP27 platforms.
- * It is OK to add fields that are IP35 specific if they are under #ifdef IP35.
  */
+#if defined(CONFIG_IA64_SGI_SN1)
 struct subnodepda_s {
 	intr_vecblk_t	intr_dispatch0;
 	intr_vecblk_t	intr_dispatch1;
-	uint64_t	next_prof_timeout;
-	int		prof_count;
 };
 
-
 typedef struct subnodepda_s subnode_pda_t;
 
 
-struct ptpool_s;
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
 struct synergy_perf_s;
 #endif
 
@@ -65,8 +51,6 @@
  * Node-specific data structure.
  *
  * One of these structures is allocated on each node of a NUMA system.
- * Non-NUMA systems are considered to be systems with one node, and
- * hence there will be one of this structure for the entire system.
  *
  * This structure provides a convenient way of keeping together 
  * all per-node data structures. 
@@ -74,119 +58,13 @@
 
 
 
-#ifdef LATER
-/*
- * The following structure is contained in the nodepda & contains
- * a lock & queue-head for sanon pages that belong to the node.
- * See the anon manager for more details.
- */
-typedef struct {
-	lock_t  sal_lock;
-	plist_t sal_listhead;
-} sanon_list_head_t;
-#endif
 struct nodepda_s {
 
-#ifdef	NUMA_BASE
-
-	/* 
-	 * Pointer to this node's copy of Nodepdaindr 
-	 */
-	struct nodepda_s	**pernode_pdaindr; 
-
-	/*
-         * Data used for migration control
-         */
-	struct migr_control_data_s *mcd; 
-
-	/*
-         * Data used for replication control
-         */
-	struct repl_control_data_s *rcd;
-
-        /*
-         * Numa statistics
-         */
-	struct numa_stats_s *numa_stats;
-
-        /*
-         * Load distribution
-         */
-        uint memfit_assign;
-
-        /*
-         * New extended memory reference counters
-         */
-        void *migr_refcnt_counterbase;
-        void *migr_refcnt_counterbuffer;
-        size_t migr_refcnt_cbsize;
-        int  migr_refcnt_numsets;
-
-        /*
-         * mem_tick quiescing lock
-         */
-        uint mem_tick_lock;
-
-        /*
-         * Migration candidate set
-         * by migration prologue intr handler
-         */
-        uint64_t migr_candidate;
-
-	/*
-	 * Each node gets its own syswait counter to remove contention
-	 * on the global one.
-	 */
-#ifdef	LATER
-	struct syswait syswait;
-#endif
-
-#endif	/* NUMA_BASE */
-	/*
-	 * Node-specific Zone structures.
-	 */
-#ifdef LATER
-	zoneset_element_t	node_zones;
-	pg_data_t	node_pg_data;	/* VM page data structures */ 
-	plist_t	error_discard_plist;
-#endif
-	uint		error_discard_count;
-	uint		error_page_count;
-	uint		error_cleaned_count;
-	spinlock_t	error_discard_lock;
 
-	/* Information needed for SN Hub chip interrupt handling. */
-	subnode_pda_t	snpda[NUM_SUBNODES];
-	/* Distributed kernel support */
-#ifdef	LATER
-	kern_vars_t	kern_vars;
-#endif
-	/* Vector operation support */
-	/* Change this to a sleep lock? */
-	spinlock_t	vector_lock;
-	/* State of the vector unit for this node */
-	char		vector_unit_busy;
 	cpuid_t         node_first_cpu; /* Starting cpu number for node */
-	ushort          node_num_cpus;  /* Number of cpus present       */
-
-	/* node utlbmiss info */
-  	spinlock_t		node_utlbswitchlock;
-	volatile cpumask_t	node_utlbmiss_flush;
-	volatile signed char	node_need_utlbmiss_patch;
-	volatile char		node_utlbmiss_patched;
-	nodepda_router_info_t	*npda_rip_first;
-	nodepda_router_info_t	**npda_rip_last;
-	int		dependent_routers;
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-	int			synergy_perf_enabled;
-        int       		synergy_perf_freq;
-	spinlock_t		synergy_perf_lock;
-        uint64_t       		synergy_inactive_intervals;
-        uint64_t       		synergy_active_intervals;
-        struct synergy_perf_s	*synergy_perf_data;
-        struct synergy_perf_s	*synergy_perf_first; /* reporting consistency .. */
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
+					/* WARNING: no guarantee that   */
+					/*  the second cpu on a node is */
+					/*  node_first_cpu+1.           */
 
 	devfs_handle_t 	xbow_vhdl;
 	nasid_t		xbow_peer;	/* NASID of our peer hub on xbow */
@@ -194,84 +72,67 @@
 	slotid_t	slotdesc;
 	moduleid_t	module_id;	/* Module ID (redundant local copy) */
 	module_t	*module;	/* Pointer to containing module */
-	int		hub_chip_rev;	/* Rev of my Hub chip */
-	char		nasid_mask[NASID_MASK_BYTES];
-					/* Need a copy of the nasid mask
-					 * on every node */
 	xwidgetnum_t 	basew_id;
 	devfs_handle_t 	basew_xc;
-	spinlock_t	fprom_lock;
-	char		ni_error_print; /* For printing ni error state
-					 * only once during system panic
-					 */
-#ifdef	LATER
-	md_perf_monitor_t node_md_perfmon;
-	hubstat_t	hubstats;
 	int		hubticks;
-	sbe_info_t	*sbe_info;	/* ECC single-bit error statistics */
-#endif	/* LATER */
-	int		huberror_ticks;
-
-	router_queue_t  *visited_router_q;
-	router_queue_t	*bfs_router_q; 
-					/* Used for router traversal */
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-	router_map_ent_t router_map[MAX_RTR_BREADTH];
-#endif
-	int		num_routers;	/* Total routers in the system */
+	int		num_routers;	/* XXX not setup! Total routers in the system */
 
-        char		membank_flavor;
-	                                /* Indicates what sort of memory 
-					 * banks are present on this node
-					 */
 	
 	char		*hwg_node_name;	/* hwgraph node name */
-
-	struct widget_info_t *widget_info;	/* Node as xtalk widget */
 	devfs_handle_t	node_vertex;	/* Hwgraph vertex for this node */
 
 	void 		*pdinfo;	/* Platform-dependent per-node info */
-	uint64_t	*dump_stack;	/* Dump stack during nmi handling */
-	int		dump_count;	/* To allow only one cpu-per-node */
-#ifdef	LATER
-	io_perf_monitor_t node_io_perfmon;
-#endif
 
-	/*
-	 * Each node gets its own pdcount counter to remove contention
-	 * on the global one.
-	 */
-
-	int pdcount;			/* count of pdinserted pages */
 
-#ifdef	NUMA_BASE
-	void		*cached_global_pool;	/* pointer to cached vmpool */
-#endif /* NUMA_BASE */
+	nodepda_router_info_t	*npda_rip_first;
+	nodepda_router_info_t	**npda_rip_last;
 
-#ifdef	LATER
-	sanon_list_head_t sanon_list_head;	/* head for sanon pages */	
-#endif
-#ifdef	NUMA_BASE
-	struct ptpool_s	*ptpool;	/* ptpool for this node */
-#endif /* NUMA_BASE */
 
 	/*
 	 * The BTEs on this node are shared by the local cpus
 	 */
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
-#ifdef	LATER
-	bteinfo_t	*node_bte_info[BTES_PER_NODE];
-#endif
-#endif
+	bteinfo_t	node_bte_info[BTES_PER_NODE];
+
+#if defined(CONFIG_IA64_SGI_SN1)
+	subnode_pda_t	snpda[NUM_SUBNODES];
+	/*
+	 * New extended memory reference counters
+ 	 */
+	void			*migr_refcnt_counterbase;
+	void			*migr_refcnt_counterbuffer;
+	size_t			migr_refcnt_cbsize;
+	int			migr_refcnt_numsets;
+	hubstat_t		hubstats;
+	int			synergy_perf_enabled;
+        int       		synergy_perf_freq;
+	spinlock_t		synergy_perf_lock;
+        uint64_t       		synergy_inactive_intervals;
+        uint64_t       		synergy_active_intervals;
+        struct synergy_perf_s	*synergy_perf_data;
+        struct synergy_perf_s	*synergy_perf_first; /* reporting consistency .. */
+#endif /* CONFIG_IA64_SGI_SN1 */
+
+	/* 
+	 * Array of pointers to the nodepdas for each node.
+	 */
+	struct nodepda_s	*pernode_pdaindr[MAX_COMPACT_NODES]; 
+
 };
 
 typedef struct nodepda_s nodepda_t;
 
+#ifdef CONFIG_IA64_SGI_SN2
+struct irqpda_s {
+	int num_irq_used;
+	char irq_flags[NR_IRQS];
+};
+
+typedef struct irqpda_s irqpda_t;
+
+#endif /* CONFIG_IA64_SGI_SN2 */
+
 
-#define NODE_MODULEID(_node)	(NODEPDA(_node)->module_id)
-#define NODE_SLOTID(_node)	(NODEPDA(_node)->slotdesc)
 
-#ifdef	NUMA_BASE
 /*
  * Access Functions for node PDA.
  * Since there is one nodepda for each node, we need a convenient mechanism
@@ -279,180 +140,49 @@
  * The next set of definitions provides this.
  * Routines are expected to use 
  *
- *	nodepda		-> to access PDA for the node on which code is running
- *	subnodepda	-> to access subnode PDA for the node on which code is running
+ *	nodepda			-> to access node PDA for the node on which code is running
+ *	subnodepda		-> to access subnode PDA for the subnode on which code is running
  *
- *	NODEPDA(x)	-> to access node PDA for cnodeid 'x'
- *	SUBNODEPDA(x,s)	-> to access subnode PDA for cnodeid/slice 'x'
- */
-
-#ifdef	LATER
-#define	nodepda		private.p_nodepda	/* Ptr to this node's PDA */
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-#define subnodepda	private.p_subnodepda	/* Ptr to this node's subnode PDA */
-#endif
-
-#else
-/*
- * Until we have a shared node local area defined, do it this way ..
- * like in Caliase space.  See above.
- */
-extern nodepda_t        *nodepda;
-extern subnode_pda_t	*subnodepda;
-#endif
-
-/* 
- * Nodepdaindr[]
- * This is a private data structure for use only in early initialization.
- * All users of nodepda should use the macro NODEPDA(nodenum) to get
- * the suitable nodepda structure.
- * This macro has the advantage of not requiring #ifdefs for NUMA and
- * non-NUMA code.
- */
-extern nodepda_t	*Nodepdaindr[]; 
-/*
- * NODEPDA_GLOBAL(x) macro should ONLY be used during early initialization.
- * Once meminit is complete, NODEPDA(x) is ready to use.
- * During early init, the system fills up Nodepdaindr.  By the time we
- * are in meminit(), all nodepdas are initialized, and hence
- * we can fill up the node_pdaindr array in each nodepda structure.
+ *	NODEPDA(cnode)		-> to access node PDA for cnodeid 
+ *	SUBNODEPDA(cnode,sn)	-> to access subnode PDA for cnodeid/subnode
  */
-#define	NODEPDA_GLOBAL(x)	Nodepdaindr[x]
 
-/*
- * Returns a pointer to a given node's nodepda.
- */
-#define	NODEPDA(x)		(nodepda->pernode_pdaindr[x])
+#define	nodepda		pda.p_nodepda		/* Ptr to this node's PDA */
+#define	NODEPDA(cnode)		(nodepda->pernode_pdaindr[cnode])
 
-/*
- * Returns a pointer to a given node/slice's subnodepda.
- *	SUBNODEPDA(cnode, subnode) - uses cnode as first arg
- *	SNPDA(npda, subnode)	   - uses pointer to nodepda as first arg
- */
-#define	SUBNODEPDA(x,sn)	(&nodepda->pernode_pdaindr[x]->snpda[sn])
+#if defined(CONFIG_IA64_SGI_SN1)
+#define subnodepda	pda.p_subnodepda	/* Ptr to this node's subnode PDA */
+#define	SUBNODEPDA(cnode,sn)	(&(NODEPDA(cnode)->snpda[sn]))
 #define	SNPDA(npda,sn)		(&(npda)->snpda[sn])
+#endif
 
-#define NODEPDA_ERROR_FOOTPRINT(node, cpu) \
-                   (&(NODEPDA(node)->error_stamp[cpu]))
-#define NODEPDA_MDP_MON(node)	(&(NODEPDA(node)->node_md_perfmon))
-#define NODEPDA_IOP_MON(node)	(&(NODEPDA(node)->node_io_perfmon))
 
 /*
  * Macros to access data structures inside nodepda 
  */
-#if NUMA_MIGR_CONTROL
-#define NODEPDA_MCD(node) (NODEPDA(node)->mcd)
-#endif /* NUMA_MIGR_CONTROL */
-
-#if NUMA_REPL_CONTROL
-#define NODEPDA_RCD(node) (NODEPDA(node)->rcd)
-#endif /* NUMA_REPL_CONTROL */
-
-#if (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL)
-#define NODEPDA_LRS(node) (NODEPDA(node)->lrs)
-#endif /* (NUMA_MIGR_CONTROL || NUMA_REPL_CONTROL) */
+#define NODE_MODULEID(cnode)	(NODEPDA(cnode)->module_id)
+#define NODE_SLOTID(cnode)	(NODEPDA(cnode)->slotdesc)
 
-/* 
- * Exported functions
- */
-extern nodepda_t *nodepda_alloc(void);
 
-#else	/* !NUMA_BASE */
 /*
- * For a single-node system we will just have one global nodepda pointer
- * allocated at startup.  The global nodepda will point to this nodepda 
- * structure.
+ * Quickly convert a compact node ID into a hwgraph vertex
  */
-extern nodepda_t	*Nodepdaindr; 
+#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex)
 
-/*
- * On non-NUMA systems, NODEPDA_GLOBAL and NODEPDA macros collapse to
- * be the same.
- */
-#define	NODEPDA_GLOBAL(x)	Nodepdaindr
 
 /*
- * Returns a pointer to a given node's nodepda.
+ * Check if given a compact node id the corresponding node has all the
+ * cpus disabled. 
  */
-#define	NODEPDA(x)	Nodepdaindr
+#define is_headless_node(cnode)		((cnode == CNODEID_NONE) ||			\
+					 (node_data(cnode)->active_cpu_count == 0))
 
 /*
- * nodepda can also be defined as private.p_nodepda.
- * But on non-NUMA systems, there is only one nodepda, and there is
- * no reason to go through the PDA to access this pointer.
- * Hence nodepda aliases to the global nodepda directly.
- *
- * Routines should use nodepda to access the local node's PDA.
- */
-#define	nodepda		(Nodepdaindr)
-
-#endif	/* NUMA_BASE */
-
-/* Quickly convert a compact node ID into a hwgraph vertex */
-#define cnodeid_to_vertex(cnodeid) (NODEPDA(cnodeid)->node_vertex)
-
-
-/* Check if given a compact node id the corresponding node has all the
- * cpus disabled. 
- */
-#define is_headless_node(_cnode)	((_cnode == CNODEID_NONE) || \
-					 (CNODE_NUM_CPUS(_cnode) == 0))
-/* Check if given a node vertex handle the corresponding node has all the
+ * Check if given a node vertex handle the corresponding node has all the
  * cpus disabled. 
  */
 #define is_headless_node_vertex(_nodevhdl) \
 			is_headless_node(nodevertex_to_cnodeid(_nodevhdl))
 
-#ifdef	__cplusplus
-}
-#endif
-
-#ifdef NUMA_BASE
-/*
- * To remove contention on the global syswait counter each node will have
- * its own.  Each clock tick the clock cpu will re-calculate the global
- * syswait counter by summing from each of the nodes.  The other cpus will
- * continue to read the global one during their clock ticks.   This does 
- * present a problem when a thread increments the count on one node and wakes
- * up on a different node and decrements it there.  Eventually the count could
- * overflow if this happens continually for a long period.  To prevent this
- * second_thread() periodically preserves the current syswait state and
- * resets the counters.
- */
-#define ADD_SYSWAIT(_field)	atomicAddInt(&nodepda->syswait._field, 1)
-#define SUB_SYSWAIT(_field)	atomicAddInt(&nodepda->syswait._field, -1)
-#else
-#define ADD_SYSWAIT(_field)				\
-{							\
-	ASSERT(syswait._field >= 0);			\
-	atomicAddInt(&syswait._field, 1);		\
-}
-#define SUB_SYSWAIT(_field)				\
-{							\
-	ASSERT(syswait._field > 0);			\
-	atomicAddInt(&syswait._field, -1);		\
-}
-#endif /* NUMA_BASE */
-
-#ifdef NUMA_BASE
-/*
- * Another global variable to remove contention from: pdcount.
- * See above comments for SYSWAIT.
- */
-#define ADD_PDCOUNT(_n)					\
-{							\
-	atomicAddInt(&nodepda->pdcount, _n);		\
-	if (_n > 0 && !pdflag)				\
-		pdflag = 1;				\
-}
-#else
-#define ADD_PDCOUNT(_n)					\
-{							\
-	ASSERT(&pdcount >= 0);				\
-	atomicAddInt(&pdcount, _n);			\
-	if (_n > 0 && !pdflag)				\
-		pdflag = 1;				\
-}
-#endif /* NUMA_BASE */
 
-#endif /* _ASM_SN_NODEPDA_H */
+#endif /* _ASM_IA64_SN_NODEPDA_H */
diff -Nru a/include/asm-ia64/sn/pci/bridge.h b/include/asm-ia64/sn/pci/bridge.h
--- a/include/asm-ia64/sn/pci/bridge.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/pci/bridge.h	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_BRIDGE_H
 #define _ASM_SN_PCI_BRIDGE_H
@@ -53,7 +52,7 @@
  *    Bridge address map
  */
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
 
 #ifdef __cplusplus
 extern "C" {
@@ -373,7 +372,7 @@
 				    ds:2,	/* Data size	  */
 				    gbr:1,	/* GBR enable	  */
 				    vbpm:1,	/* VBPM message	  */
-				    error:1,	/* Error occurred  */
+				    error:1,	/* Error occurred */
 				    barr:1,	/* Barrier op	  */
 				    rsvd:8;
 	} berr_st;
@@ -638,7 +637,7 @@
 
 
 #define berr_field	berr_un.berr_st
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 /*
  * The values of these macros can and should be crosschecked
@@ -903,10 +902,10 @@
 #define BRIDGE_DEVIO_2MB	0x00200000	/* Device IO Offset (0..1) */
 #define BRIDGE_DEVIO_1MB	0x00100000	/* Device IO Offset (2..7) */
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define BRIDGE_DEVIO(x)		((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #define BRIDGE_EXTERNAL_FLASH	0x00C00000	/* External Flash PROMS */
 
@@ -971,6 +970,10 @@
 #define BRIDGE_CTRL_CLR_RLLP_CNT	(0x1 << 11)
 #define BRIDGE_CTRL_CLR_TLLP_CNT	(0x1 << 10)
 #define BRIDGE_CTRL_SYS_END		(0x1 << 9)
+#define BRIDGE_CTRL_BUS_SPEED(n)        ((n) << 4)
+#define BRIDGE_CTRL_BUS_SPEED_MASK      (BRIDGE_CTRL_BUS_SPEED(0x3))
+#define BRIDGE_CTRL_BUS_SPEED_33        0x00
+#define BRIDGE_CTRL_BUS_SPEED_66        0x10
 #define BRIDGE_CTRL_MAX_TRANS(n)	((n) << 4)
 #define BRIDGE_CTRL_MAX_TRANS_MASK	(BRIDGE_CTRL_MAX_TRANS(0x1f))
 #define BRIDGE_CTRL_WIDGET_ID(n)	((n) << 0)
@@ -1296,14 +1299,14 @@
 #define PCI32_MAPPED_BASE		BRIDGE_DMA_MAPPED_BASE
 #define PCI32_DIRECT_BASE		BRIDGE_DMA_DIRECT_BASE
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define IS_PCI32_LOCAL(x)	((uint64_t)(x) < PCI32_MAPPED_BASE)
 #define IS_PCI32_MAPPED(x)	((uint64_t)(x) < PCI32_DIRECT_BASE && \
 					(uint64_t)(x) >= PCI32_MAPPED_BASE)
 #define IS_PCI32_DIRECT(x)	((uint64_t)(x) >= PCI32_MAPPED_BASE)
 #define IS_PCI64(x)		((uint64_t)(x) >= PCI64_BASE)
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 /*
  * The GIO address space.
@@ -1318,13 +1321,13 @@
 #define GIO_MAPPED_BASE			BRIDGE_DMA_MAPPED_BASE
 #define GIO_DIRECT_BASE			BRIDGE_DMA_DIRECT_BASE
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define IS_GIO_LOCAL(x)		((uint64_t)(x) < GIO_MAPPED_BASE)
 #define IS_GIO_MAPPED(x)	((uint64_t)(x) < GIO_DIRECT_BASE && \
 					(uint64_t)(x) >= GIO_MAPPED_BASE)
 #define IS_GIO_DIRECT(x)	((uint64_t)(x) >= GIO_MAPPED_BASE)
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 /* PCI to xtalk mapping */
 
@@ -1347,7 +1350,7 @@
 #define PCI64_ATTR_RMF_MASK	0x00ff000000000000
 #define PCI64_ATTR_RMF_SHFT	48
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* Address translation entry for mapped pci32 accesses */
 typedef union ate_u {
     uint64_t		    ent;
@@ -1375,7 +1378,7 @@
 	uint64_t		valid:1;
     } field;
 } ate_t;
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #define ATE_V		(1 << 0)
 #define ATE_CO		(1 << 1)
@@ -1401,7 +1404,7 @@
 #define is_xbridge(bridge) \
         (XWIDGET_PART_NUM(bridge->b_wid_id) == XBRIDGE_WIDGET_PART_NUM)
 
-#if	LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* ========================================================================
  */
diff -Nru a/include/asm-ia64/sn/pci/pci_bus_cvlink.h b/include/asm-ia64/sn/pci/pci_bus_cvlink.h
--- a/include/asm-ia64/sn/pci/pci_bus_cvlink.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/pci/pci_bus_cvlink.h	Fri Mar 15 17:51:03 2002
@@ -4,12 +4,36 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_CVLINK_H
 #define _ASM_SN_PCI_CVLINK_H
 
+#include <asm/sn/types.h>
+#include <asm/sn/hack.h>
+#include <asm/sn/sgi.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/iograph.h>
+#include <asm/param.h>
+#include <asm/sn/pio.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/sn_private.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/invent.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/hcl_util.h>
+#include <asm/sn/intr.h>
+#include <asm/sn/xtalk/xtalkaddrs.h>
+#include <asm/sn/klconfig.h>
+#include <asm/sn/io.h>
+
+#include <asm/sn/pci/pciio.h>
+#include <asm/sn/pci/pcibr.h>
+#include <asm/sn/pci/pcibr_private.h>
+
+#define MAX_PCI_XWIDGET 256
+#define MAX_ATE_MAPS 1024
+
 #define SET_PCIA64(dev) \
 	(((struct sn1_device_sysdata *)((dev)->sysdata))->isa64) = 1
 #define IS_PCIA64(dev)	(((dev)->dma_mask == 0xffffffffffffffffUL) || \
@@ -17,6 +41,12 @@
 #define IS_PCI32G(dev)	((dev)->dma_mask >= 0xffffffff)
 #define IS_PCI32L(dev)	((dev)->dma_mask < 0xffffffff)
 
+#define PCIDEV_VERTEX(pci_dev) \
+	(((struct sn1_device_sysdata *)((pci_dev)->sysdata))->vhdl)
+
+#define PCIBUS_VERTEX(pci_bus) \
+	(((struct sn1_widget_sysdata *)((pci_bus)->sysdata))->vhdl)
+
 struct sn1_widget_sysdata {
         devfs_handle_t  vhdl;
 };
@@ -24,6 +54,8 @@
 struct sn1_device_sysdata {
         devfs_handle_t  vhdl;
 	int		isa64;
+	volatile unsigned int *dma_buf_sync;
+	volatile unsigned int *xbow_buf_sync;
 };
 
 struct sn1_dma_maps_s{
diff -Nru a/include/asm-ia64/sn/pci/pci_defs.h b/include/asm-ia64/sn/pci/pci_defs.h
--- a/include/asm-ia64/sn/pci/pci_defs.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/pci/pci_defs.h	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCI_DEFS_H
 #define _ASM_SN_PCI_PCI_DEFS_H
diff -Nru a/include/asm-ia64/sn/pci/pciba.h b/include/asm-ia64/sn/pci/pciba.h
--- a/include/asm-ia64/sn/pci/pciba.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/pci/pciba.h	Fri Mar 15 17:51:01 2002
@@ -1,24 +1,33 @@
-/* $Id$
+/* 
+ * This file is subject to the terms and conditions of the GNU General
+ * Public License.  See the file "COPYING" in the main directory of
+ * this archive for more details.
  *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
+ * Copyright (C) 1997, 2001 Silicon Graphics, Inc. All rights reserved.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
  */
+
 #ifndef _ASM_SN_PCI_PCIBA_H
 #define _ASM_SN_PCI_PCIBA_H
 
-/*
- * These are all the HACKS from ioccom.h ..
- */
-#define IOCPARM_MASK    0xff            /* parameters must be < 256 bytes */
-#define IOC_VOID        0x20000000      /* no parameters */
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+
+/* for application compatibility with IRIX (why do I bother?) */
+
+#ifndef __KERNEL__
+typedef u_int8_t uint8_t;
+typedef u_int16_t uint16_t;
+typedef u_int32_t uint32_t;
+#endif
+
+#define PCI_CFG_VENDOR_ID	PCI_VENDOR_ID
+#define PCI_CFG_COMMAND		PCI_COMMAND
+#define PCI_CFG_REV_ID		PCI_REVISION_ID
+#define PCI_CFG_HEADER_TYPE	PCI_HEADER_TYPE
+#define PCI_CFG_BASE_ADDR(n)	PCI_BASE_ADDRESS_##n
 
-/*
- * The above needs to be modified and follow LINUX ...
- */
 
 /* /hw/.../pci/[slot]/config accepts ioctls to read
  * and write specific registers as follows:
@@ -69,18 +78,11 @@
 /* PCIIOCGETBASE(n): arg is ptr to a 32-bit int,
  * which will get the value of the BASE<n> register.
  */
+
+/* FIXME chadt: this doesn't tell me whether or not this will work
+   with non-constant 'n.'  */
 #define	PCIIOCGETBASE(n)	PCIIOCCFGRD(uint32_t,PCI_CFG_BASE_ADDR(n))
 
-/* /hw/.../pci/[slot]/intr accepts an ioctl to
- * set up user level interrupt handling as follows:
- *
- * "n" is a bitmap of which of the four PCI interrupt
- * lines are of interest, using PCIIO_INTR_LINE_[ABCD].
- */
-#define	PCIIOCSETULI(n)		_IOWR(1,n,struct uliargs)
-#if _KERNEL
-#define PCIIOCSETULI32(n)	_IOWR(1,n,struct uliargs32)
-#endif
 
 /* /hw/.../pci/[slot]/dma accepts ioctls to allocate
  * and free physical memory for use in user-triggered
@@ -93,11 +95,20 @@
  * both the size of the request and the flag values
  * to be used in setting up the DMA.
  *
+
+FIXME chadt: gonna have to revisit this: what flags would an IRIXer like to
+ have available?
+
  * Any flags normally useful in pciio_dmamap
- * or pciio_dmatrans function calls can6 be used here.
- */
+ * or pciio_dmatrans function calls can6 be used here.  */
 #define	PCIIOCDMAALLOC_REQUEST_PACK(flags,size)		\
 	((((uint64_t)(flags))<<32)|			\
 	 (((uint64_t)(size))&0xFFFFFFFF))
+
+
+#ifdef __KERNEL__
+extern int pciba_init(void);
+#endif
+
 
 #endif	/* _ASM_SN_PCI_PCIBA_H */
diff -Nru a/include/asm-ia64/sn/pci/pcibr.h b/include/asm-ia64/sn/pci/pcibr.h
--- a/include/asm-ia64/sn/pci/pcibr.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/pci/pcibr.h	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIBR_H
 #define _ASM_SN_PCI_PCIBR_H
@@ -13,7 +12,7 @@
 #if defined(__KERNEL__)
 
 #include <asm/sn/dmamap.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/pio.h>
 
 #include <asm/sn/pci/pciio.h>
@@ -31,7 +30,7 @@
 #define PCIBR_INTR_BLOCKED		0x40000000
 #define PCIBR_INTR_BUSY			0x80000000
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* =====================================================================
  *    opaque types used by pcibr's xtalk bus provider
@@ -183,10 +182,7 @@
 
 extern void		pcibr_intr_free(pcibr_intr_t intr);
 
-extern int		pcibr_intr_connect(pcibr_intr_t intr,
-					   intr_func_t intr_func,
-					   intr_arg_t intr_arg,
-					   void *thread);
+extern int		pcibr_intr_connect(pcibr_intr_t intr);
 
 extern void		pcibr_intr_disconnect(pcibr_intr_t intr);
 
@@ -349,7 +345,7 @@
 
 extern int		pcibr_asic_rev(devfs_handle_t);
 
-#endif 	/* _LANGUAGE_C */
+#endif 	/* __ASSEMBLY__ */
 #endif	/* #if defined(__KERNEL__) */
 /* 
  * Some useful ioctls into the pcibr driver
@@ -390,10 +386,34 @@
 /*
  * Structures for requesting PCI bridge information and receiving a response
  */
-typedef struct pcibr_slot_info_req_s *pcibr_slot_info_req_t;
+typedef struct pcibr_slot_req_s *pcibr_slot_req_t;
+typedef struct pcibr_slot_up_resp_s *pcibr_slot_up_resp_t;
+typedef struct pcibr_slot_down_resp_s *pcibr_slot_down_resp_t;
 typedef struct pcibr_slot_info_resp_s *pcibr_slot_info_resp_t;
 typedef struct pcibr_slot_func_info_resp_s *pcibr_slot_func_info_resp_t;
 
+#define L1_QSIZE                128      /* our L1 message buffer size */
+struct pcibr_slot_req_s {
+    int                      req_slot;
+    union {
+        pcibr_slot_up_resp_t     up;
+        pcibr_slot_down_resp_t   down;
+        pcibr_slot_info_resp_t   query;
+        void                    *any;
+    }                       req_respp;
+    int                     req_size;
+};
+
+struct pcibr_slot_up_resp_s {
+    int                     resp_sub_errno;
+    char                    resp_l1_msg[L1_QSIZE + 1];
+};
+
+struct pcibr_slot_down_resp_s {
+    int                     resp_sub_errno;
+    char                    resp_l1_msg[L1_QSIZE + 1];
+};
+
 struct pcibr_slot_info_req_s {
    int                      req_slot;
    pcibr_slot_info_resp_t   req_respp;
@@ -454,7 +474,40 @@
         int                     resp_f_att_det_error;
 
     } resp_func[8];
-
 };
+
+
+/*
+ * PCI specific errors, interpreted by pciconfig command
+ */
+
+/* EPERM                          1    */
+#define PCI_SLOT_ALREADY_UP       2     /* slot already up */
+#define PCI_SLOT_ALREADY_DOWN     3     /* slot already down */
+#define PCI_IS_SYS_CRITICAL       4     /* slot is system critical */
+/* EIO                            5    */
+/* ENXIO                          6    */
+#define PCI_L1_ERR                7     /* L1 console command error */
+#define PCI_NOT_A_BRIDGE          8     /* device is not a bridge */
+#define PCI_SLOT_IN_SHOEHORN      9     /* slot is in a shorhorn */
+#define PCI_NOT_A_SLOT           10     /* slot is invalid */
+#define PCI_RESP_AREA_TOO_SMALL  11     /* slot is invalid */
+/* ENOMEM                        12    */
+#define PCI_NO_DRIVER            13     /* no driver for device */
+/* EFAULT                        14    */
+#define PCI_EMPTY_33MHZ          15     /* empty 33 MHz bus */
+/* EBUSY                         16    */
+#define PCI_SLOT_RESET_ERR       17     /* slot reset error */
+#define PCI_SLOT_INFO_INIT_ERR   18     /* slot info init error */
+/* ENODEV                        19    */
+#define PCI_SLOT_ADDR_INIT_ERR   20     /* slot addr space init error */
+#define PCI_SLOT_DEV_INIT_ERR    21     /* slot device init error */
+/* EINVAL                        22    */
+#define PCI_SLOT_GUEST_INIT_ERR  23     /* slot guest info init error */
+#define PCI_SLOT_RRB_ALLOC_ERR   24     /* slot initial rrb alloc error */
+#define PCI_SLOT_DRV_ATTACH_ERR  25     /* driver attach error */
+#define PCI_SLOT_DRV_DETACH_ERR  26     /* driver detach error */
+/* ERANGE                        34    */
+/* EUNATCH                       42    */
 
 #endif				/* _ASM_SN_PCI_PCIBR_H */
diff -Nru a/include/asm-ia64/sn/pci/pcibr_private.h b/include/asm-ia64/sn/pci/pcibr_private.h
--- a/include/asm-ia64/sn/pci/pcibr_private.h	Fri Mar 15 17:51:00 2002
+++ b/include/asm-ia64/sn/pci/pcibr_private.h	Fri Mar 15 17:51:00 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIBR_PRIVATE_H
 #define _ASM_SN_PCI_PCIBR_PRIVATE_H
@@ -16,6 +15,7 @@
  * should ever peek into this file.
  */
 
+#include <asm/sn/pci/pcibr.h>
 #include <asm/sn/pci/pciio_private.h>
 #include <asm/sn/ksys/l1.h>
 
@@ -100,9 +100,6 @@
 #define	bi_flags	bi_pi.pi_flags	/* PCIBR_INTR flags */
 #define	bi_dev		bi_pi.pi_dev	/* associated pci card */
 #define	bi_lines	bi_pi.pi_lines	/* which PCI interrupt line(s) */
-#define	bi_func		bi_pi.pi_func	/* handler function (when connected) */
-#define	bi_arg		bi_pi.pi_arg	/* handler parameter (when connected) */
-#define bi_tinfo	bi_pi.pi_tinfo	/* Thread info (when connected) */
 #define bi_mustruncpu	bi_pi.pi_mustruncpu /* Where we must run. */
 #define bi_irq		bi_pi.pi_irq	/* IRQ assigned. */
 #define bi_cpu		bi_pi.pi_cpu	/* cpu assigned. */
@@ -173,14 +170,17 @@
  */
 
 struct pcibr_soft_s {
-    devfs_handle_t            bs_conn;	/* xtalk connection point */
-    devfs_handle_t            bs_vhdl;	/* vertex owned by pcibr */
+    devfs_handle_t          bs_conn;		/* xtalk connection point */
+    devfs_handle_t          bs_vhdl;		/* vertex owned by pcibr */
     int                     bs_int_enable;	/* Mask of enabled intrs */
-    bridge_t               *bs_base;	/* PIO pointer to Bridge chip */
-    char                   *bs_name;	/* hw graph name */
-    xwidgetnum_t            bs_xid;	/* Bridge's xtalk ID number */
-    devfs_handle_t            bs_master;	/* xtalk master vertex */
-    xwidgetnum_t            bs_mxid;	/* master's xtalk ID number */
+    bridge_t               *bs_base;		/* PIO pointer to Bridge chip */
+    char                   *bs_name;		/* hw graph name */
+    xwidgetnum_t            bs_xid;		/* Bridge's xtalk ID number */
+    devfs_handle_t          bs_master;		/* xtalk master vertex */
+    xwidgetnum_t            bs_mxid;		/* master's xtalk ID number */
+    pciio_slot_t            bs_first_slot;      /* first existing slot */
+    pciio_slot_t            bs_last_slot;       /* last existing slot */
+
 
     iopaddr_t               bs_dir_xbase;	/* xtalk address for 32-bit PCI direct map */
     xwidgetnum_t	    bs_dir_xport;	/* xtalk port for 32-bit PCI direct map */
@@ -190,7 +190,7 @@
     short		    bs_int_ate_size;	/* number of internal ates */
     short		    bs_xbridge;		/* if 1 then xbridge */
 
-    int                     bs_rev_num;	/* revision number of Bridge */
+    int                     bs_rev_num;		/* revision number of Bridge */
 
     unsigned                bs_dma_flags;	/* revision-implied DMA flags */
 
@@ -253,6 +253,7 @@
 	struct {
 	    pciio_space_t           bssd_space;
 	    iopaddr_t               bssd_base;
+            int                     bssd_ref_cnt;
 	} bss_devio;
 
 	/* Shadow value for Device(x) register,
@@ -312,7 +313,9 @@
     int                     bs_rrb_fixed;
     int			    bs_rrb_avail[2];
     int			    bs_rrb_res[8];
-    int			    bs_rrb_valid[16];
+    int                     bs_rrb_res_dflt[8];
+    int                     bs_rrb_valid[16];
+    int                     bs_rrb_valid_dflt[16];
 
     struct {
 	/* Each Bridge interrupt bit has a single XIO
@@ -433,5 +436,42 @@
 
 #define pcibr_soft_get(v)       ((pcibr_soft_t)hwgraph_fastinfo_get((v)))
 #define pcibr_soft_set(v,i)     (hwgraph_fastinfo_set((v), (arbitrary_info_t)(i)))
+
+/* Use io spin locks. This ensures that all the PIO writes from a particular
+ * CPU to a particular IO device are synched before the start of the next
+ * set of PIO operations to the same device.
+ */
+#define pcibr_lock(pcibr_soft)		io_splock(&pcibr_soft->bs_lock)
+#define pcibr_unlock(pcibr_soft,s)	io_spunlock(&pcibr_soft->bs_lock,s)
+
+/*
+ * mem alloc/free macros
+ */
+#define NEWAf(ptr,n,f)	(ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), (f&PCIIO_NOSLEEP)?KM_NOSLEEP:KM_SLEEP))
+#define NEWA(ptr,n)	(ptr = snia_kmem_zalloc((n)*sizeof (*(ptr)), KM_SLEEP))
+#define DELA(ptr,n)	(kfree(ptr))
+
+#define NEWf(ptr,f)	NEWAf(ptr,1,f)
+#define NEW(ptr)	NEWA(ptr,1)
+#define DEL(ptr)	DELA(ptr,1)
+
+typedef volatile unsigned *cfg_p;
+typedef volatile bridgereg_t *reg_p;
+
+#define PCIBR_RRB_SLOT_VIRTUAL  8
+#define PCIBR_VALID_SLOT(s)     (s < 8)
+#define PCIBR_D64_BASE_UNSET    (0xFFFFFFFFFFFFFFFF)
+#define PCIBR_D32_BASE_UNSET    (0xFFFFFFFF)
+#define INFO_LBL_PCIBR_ASIC_REV "_pcibr_asic_rev"
+
+#define PCIBR_SOFT_LIST 1
+#if PCIBR_SOFT_LIST
+typedef struct pcibr_list_s *pcibr_list_p;
+struct pcibr_list_s {
+	pcibr_list_p            bl_next;
+	pcibr_soft_t            bl_soft;
+	devfs_handle_t          bl_vhdl;
+};
+#endif /* PCIBR_SOFT_LIST */
 
 #endif				/* _ASM_SN_PCI_PCIBR_PRIVATE_H */
diff -Nru a/include/asm-ia64/sn/pci/pciio.h b/include/asm-ia64/sn/pci/pciio.h
--- a/include/asm-ia64/sn/pci/pciio.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/pci/pciio.h	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIIO_H
 #define _ASM_SN_PCI_PCIIO_H
@@ -15,25 +14,22 @@
  */
 
 #include <asm/sn/ioerror.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/hcl.h>
 
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
+#ifndef __ASSEMBLY__
 
 #include <asm/sn/dmamap.h>
 #include <asm/sn/alenlist.h>
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
 typedef int pciio_vendor_id_t;
 
-#define PCIIO_VENDOR_ID_NONE	-1
+#define PCIIO_VENDOR_ID_NONE	(-1)
 
 typedef int pciio_device_id_t;
 
-#define PCIIO_DEVICE_ID_NONE	-1
+#define PCIIO_DEVICE_ID_NONE	(-1)
 
 typedef uint8_t pciio_bus_t;       /* PCI bus number (0..255) */
 typedef uint8_t pciio_slot_t;      /* PCI slot number (0..31, 255) */
@@ -387,10 +383,7 @@
 pciio_intr_free_f       (pciio_intr_t intr_hdl);
 
 typedef int
-pciio_intr_connect_f    (pciio_intr_t intr_hdl,		/* pciio intr resource handle */
-			 intr_func_t intr_func,		/* pciio intr handler */
-			 intr_arg_t intr_arg,	/* arg to intr handler */
-			 void *thread);	/* intr thread to use */
+pciio_intr_connect_f    (pciio_intr_t intr_hdl);	/* pciio intr resource handle */
 
 typedef void
 pciio_intr_disconnect_f (pciio_intr_t intr_hdl);
@@ -729,8 +722,5 @@
 extern int              pciio_error_handler(devfs_handle_t, int, ioerror_mode_t, ioerror_t *);
 extern int		pciio_dma_enabled(devfs_handle_t);
 
-#ifdef __cplusplus
-};
-#endif
 #endif				/* C or C++ */
 #endif				/* _ASM_SN_PCI_PCIIO_H */
diff -Nru a/include/asm-ia64/sn/pci/pciio_private.h b/include/asm-ia64/sn/pci/pciio_private.h
--- a/include/asm-ia64/sn/pci/pciio_private.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/pci/pciio_private.h	Fri Mar 15 17:51:01 2002
@@ -4,12 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 #ifndef _ASM_SN_PCI_PCIIO_PRIVATE_H
 #define _ASM_SN_PCI_PCIIO_PRIVATE_H
 
+#include <asm/sn/pci/pciio.h>
+
 /*
  * pciio_private.h -- private definitions for pciio
  * PCI drivers should NOT include this file.
@@ -48,11 +49,6 @@
     devfs_handle_t            pi_dev;	/* associated pci card */
     device_desc_t	    pi_dev_desc;	/* override device descriptor */
     pciio_intr_line_t       pi_lines;	/* which interrupt line(s) */
-    intr_func_t             pi_func;	/* handler function (when connected) */
-    intr_arg_t              pi_arg;	/* handler parameter (when connected) */
-#ifdef LATER
-    thd_int_t               pi_tinfo;	/* Thread info (when connected) */
-#endif
     cpuid_t                 pi_mustruncpu; /* Where we must run. */
     int                     pi_irq;     /* IRQ assigned */
     int                     pi_cpu;     /* cpu assigned */
@@ -84,6 +80,8 @@
 	pciio_space_t		w_space;
 	iopaddr_t		w_base;
 	size_t			w_size;
+        int                     w_devio_index;  /* DevIO[] register used to
+                                                   access this window */
     }			    c_window[6];
 
     unsigned		    c_rbase;	/* EXPANSION ROM base addr */
diff -Nru a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/pda.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,80 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_PDA_H
+#define _ASM_IA64_SN_PDA_H
+
+#include <linux/config.h>
+#include <linux/cache.h>
+#include <asm/system.h>
+#include <asm/processor.h>
+#include <asm/page.h>
+#include <asm/sn/bte.h>
+
+
+/*
+ * CPU-specific data structure.
+ *
+ * One of these structures is allocated for each cpu of a NUMA system.
+ *
+ * This structure provides a convenient way of keeping together 
+ * all SN per-cpu data structures. 
+ */
+
+
+
+typedef struct pda_s {
+
+	/* Having a pointer in the begining of PDA tends to increase
+	 * the chance of having this pointer in cache. (Yes something
+	 * else gets pushed out). Doing this reduces the number of memory
+	 * access to all nodepda variables to be one
+	 */
+	struct nodepda_s *p_nodepda;		/* Pointer to Per node PDA */
+	struct subnodepda_s *p_subnodepda;	/* Pointer to CPU  subnode PDA */
+
+	/*
+	 * Support for blinking SN LEDs
+	 */
+	long		*led_address;
+	u8		led_state;
+	char		hb_state;	/* supports blinking heartbeat leds */
+	unsigned int	hb_count;
+
+	unsigned int	idle_flag;
+	
+#ifdef CONFIG_IA64_SGI_SN2
+	struct irqpda_s *p_irqpda;			/* Pointer to CPU irq data */
+#endif
+	volatile unsigned long *bedrock_rev_id;
+	volatile unsigned long *pio_write_status_addr;
+
+	bteinfo_t *cpubte[BTES_PER_NODE];
+} pda_t;
+
+
+#define CACHE_ALIGN(x)	(((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
+
+/*
+ * PDA
+ * Per-cpu private data area for each cpu. The PDA is located immediately after
+ * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
+ * cpu but only a small amout of the page is actually used. We put the SNIA PDA
+ * in the same page as the cpu_data area. Note that there is a check in the setup
+ * code to verify that we dont overflow the page.
+ *
+ * Seems like we should should cache-line align the pda so that any changes in the
+ * size of the cpu_data area dont change cache layout. Should we align to 32, 64, 128
+ * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
+ */
+#define CPU_DATA_END	CACHE_ALIGN((long)&(((struct cpuinfo_ia64*)0)->platform_specific))
+#define PDAADDR		(PERCPU_ADDR+CPU_DATA_END)
+
+#define pda		(*((pda_t *) PDAADDR))
+
+
+#endif /* _ASM_IA64_SN_PDA_H */
diff -Nru a/include/asm-ia64/sn/pio.h b/include/asm-ia64/sn/pio.h
--- a/include/asm-ia64/sn/pio.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/pio.h	Fri Mar 15 17:51:01 2002
@@ -4,15 +4,14 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_PIO_H
-#define _ASM_SN_PIO_H
+#ifndef _ASM_IA64_SN_PIO_H
+#define _ASM_IA64_SN_PIO_H
 
 #include <linux/types.h>
 #include <asm/sn/sgi.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 
 /*
  * pioaddr_t	- The kernel virtual address that a PIO can be done upon.
@@ -143,7 +142,7 @@
 #define LAN_RAM         2
 #define LAN_IO          3
 
-#define PIOREG_NULL	-1
+#define PIOREG_NULL	(-1)
 
 /* standard flags values for pio_map routines,
  * including {xtalk,pciio}_piomap calls.
@@ -156,4 +155,4 @@
 
 #define	PIOMAP_FLAGS	0x7
 
-#endif	/* _ASM_SN_PIO_H */
+#endif	/* _ASM_IA64_SN_PIO_H */
diff -Nru a/include/asm-ia64/sn/pio_flush.h b/include/asm-ia64/sn/pio_flush.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/pio_flush.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,65 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#include <linux/config.h>
+
+#ifndef _ASM_IA64_PIO_FLUSH_H
+#define _ASM_IA64_PIO_FLUSH_H
+
+/*
+ * This macro flushes all outstanding PIOs performed by this cpu to the 
+ * intended destination SHUB.  This in essence ensures that all PIO's
+ * issues by this cpu has landed at it's destination.
+ *
+ * This macro expects the caller:
+ *	1.  The thread is locked.
+ *	2.  All prior PIO operations has been fenced.
+ *
+ */
+
+#if defined (CONFIG_IA64_SGI_SN)
+
+#include <asm/sn/pda.h>
+
+#if defined (CONFIG_IA64_SGI_SN2)
+
+#define PIO_FLUSH() \
+	{ \
+	while ( !((volatile unsigned long) (*pda.pio_write_status_addr)) & 0x8000000000000000) { \
+			udelay(5); \
+	} \
+	__ia64_mf_a(); \
+	}
+
+#elif defined (CONFIG_IA64_SGI_SN1)
+
+/*
+ * For SN1 we need to first read any local Bedrock's MMR and then poll on the 
+ * Synergy MMR.
+ */
+#define PIO_FLUSH() \
+	{ \
+	(volatile unsigned long) (*pda.bedrock_rev_id); \
+	while (!(volatile unsigned long) (*pda.pio_write_status_addr)) { \
+		udelay(5); \
+	} \
+	__ia64_mf_a(); \
+	} 
+#endif
+#else
+/*
+ * For all ARCHITECTURE type, this is a NOOP.
+ */
+
+#define PIO_FLUSH()
+
+#endif
+
+#endif /* _ASM_IA64_PIO_FLUSH_H */
diff -Nru a/include/asm-ia64/sn/prio.h b/include/asm-ia64/sn/prio.h
--- a/include/asm-ia64/sn/prio.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/prio.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_PRIO_H
-#define _ASM_SN_PRIO_H
+#ifndef _ASM_IA64_SN_PRIO_H
+#define _ASM_IA64_SN_PRIO_H
+
+#include <linux/types.h>
 
 /*
  * Priority I/O function prototypes and macro definitions
@@ -33,6 +34,6 @@
 
 /* Error returns */
 #define PRIO_SUCCESS     0
-#define PRIO_FAIL       -1 
+#define PRIO_FAIL       (-1) 
 
-#endif /* _ASM_SN_PRIO_H */
+#endif /* _ASM_IA64_SN_PRIO_H */
diff -Nru a/include/asm-ia64/sn/router.h b/include/asm-ia64/sn/router.h
--- a/include/asm-ia64/sn/router.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/router.h	Fri Mar 15 17:51:02 2002
@@ -1,19 +1,665 @@
+
 /* $Id$
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_ROUTER_H
+#define _ASM_IA64_SN_ROUTER_H
+
+/*
+ * Router Register definitions
+ *
+ * Macro argument _L always stands for a link number (1 to 8, inclusive).
+ */
+
+#ifndef __ASSEMBLY__
+
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/vector.h>
+#include <asm/sn/slotnum.h>
+#include <asm/sn/arch.h>
+
+typedef uint64_t	router_reg_t;
+
+#define MAX_ROUTERS	64
+
+#define MAX_ROUTER_PATH	80
+
+#define ROUTER_REG_CAST		(volatile router_reg_t *)
+#define PS_UINT_CAST		(__psunsigned_t)
+#define UINT64_CAST		(uint64_t)
+typedef signed char port_no_t;	 /* Type for router port number      */
+
+#else 
+
+#define ROUTERREG_CAST
+#define PS_UINT_CAST
+#define UINT64_CAST
+
+#endif /* __ASSEMBLY__ */
+
+#define MAX_ROUTER_PORTS (8)	 /* Max. number of ports on a router */
+
+#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1)	/* for 0 based references */
+
+#define PORT_INVALID (-1)	 /* Invalid port number              */
+
+#define	IS_META(_rp)	((_rp)->flags & PCFG_ROUTER_META)
+
+#define	IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)
+
+/*
+ * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
+ * port to generate an output port.
+ *
+ * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
+ * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
+ *
+ * These are written to work on unsigned data.
  */
-#ifndef _ASM_SN_ROUTER_H
-#define _ASM_SN_ROUTER_H
 
-#include <linux/config.h>
+#define RR_TURN(_L, count)	((_L) + (count) > MAX_ROUTER_PORTS ?	\
+				 (_L) + (count) - MAX_ROUTER_PORTS :	\
+				 (_L) + (count))
+
+#define RR_DISTANCE(_LS, _LD)	((_LD) >= (_LS) ?			\
+				 (_LD) - (_LS) :			\
+				 (_LD) + MAX_ROUTER_PORTS - (_LS))
+
+/* Router register addresses */
+
+#define RR_STATUS_REV_ID	0x00000	/* Status register and Revision ID  */
+#define RR_PORT_RESET		0x00008	/* Multiple port reset              */
+#define RR_PROT_CONF		0x00010	/* Inter-partition protection conf. */
+#define RR_GLOBAL_PORT_DEF	0x00018 /* Global Port definitions          */
+#define RR_GLOBAL_PARMS0	0x00020	/* Parameters shared by all 8 ports */
+#define RR_GLOBAL_PARMS1	0x00028	/* Parameters shared by all 8 ports */
+#define RR_DIAG_PARMS		0x00030	/* Parameters for diag. testing     */
+#define RR_DEBUG_ADDR		0x00038 /* Debug address select - debug port*/
+#define RR_LB_TO_L2		0x00040 /* Local Block to L2 cntrl intf reg */ 
+#define RR_L2_TO_LB		0x00048 /* L2 cntrl intf to Local Block reg */
+#define RR_JBUS_CONTROL		0x00050 /* read/write timing for JBUS intf  */
+
+#define RR_SCRATCH_REG0		0x00100	/* Scratch 0 is 64 bits */
+#define RR_SCRATCH_REG1		0x00108	/* Scratch 1 is 64 bits */
+#define RR_SCRATCH_REG2		0x00110	/* Scratch 2 is 64 bits */
+#define RR_SCRATCH_REG3		0x00118	/* Scratch 3 is 1 bit */
+#define RR_SCRATCH_REG4		0x00120	/* Scratch 4 is 1 bit */
+
+#define RR_JBUS0(_D)		(((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses   */
+#define RR_JBUS1(_D)		(((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses   */
+
+#define RR_SCRATCH_REG0_WZ	0x00500	/* Scratch 0 is 64 bits */
+#define RR_SCRATCH_REG1_WZ	0x00508	/* Scratch 1 is 64 bits */
+#define RR_SCRATCH_REG2_WZ	0x00510	/* Scratch 2 is 64 bits */
+#define RR_SCRATCH_REG3_SZ	0x00518	/* Scratch 3 is 1 bit */
+#define RR_SCRATCH_REG4_SZ	0x00520	/* Scratch 4 is 1 bit */
+
+#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
+/* Port-specific registers (_L is the link number from 1 to 8) */
+
+#define RR_PORT_PARMS(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters     */
+#define RR_STATUS_ERROR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs  */
+#define RR_CHANNEL_TEST(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
+#define RR_RESET_MASK(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask  */
+#define RR_HISTOGRAM0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
+#define RR_HISTOGRAM1(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
+#define RR_HISTOGRAM0_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
+#define RR_HISTOGRAM1_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
+#define RR_ERROR_CLEAR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors  */
+#define RR_GLOBAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
+#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
+#define RR_LOCAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
+#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))
+
+#define RR_META_ENTRIES		16
+
+#define RR_LOCAL_ENTRIES	128
+
+/*
+ * RR_STATUS_REV_ID mask and shift definitions
+ */
+
+#define RSRI_INPORT_SHFT	52
+#define RSRI_INPORT_MASK	(UINT64_CAST 0xf << 52)
+#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
+#define RSRI_LINKWORKING(_L)	(UINT64_CAST 1 << (35 + 2 * (_L)))
+#define RSRI_LINKRESETFAIL(_L)	(UINT64_CAST 1 << (34 + 2 * (_L)))
+#define RSRI_LSTAT_SHFT(_L)	(34 + 2 * (_L))
+#define RSRI_LSTAT_MASK(_L)	(UINT64_CAST 0x3 << 34 + 2 * (_L))
+#define RSRI_LOCALSBERROR	(UINT64_CAST 1 << 35)
+#define RSRI_LOCALSTUCK		(UINT64_CAST 1 << 34)
+#define RSRI_LOCALBADVEC	(UINT64_CAST 1 << 33)
+#define RSRI_LOCALTAILERR	(UINT64_CAST 1 << 32)
+#define RSRI_LOCAL_SHFT 	32
+#define RSRI_LOCAL_MASK		(UINT64_CAST 0xf << 32)
+#define RSRI_CHIPREV_SHFT	28
+#define RSRI_CHIPREV_MASK	(UINT64_CAST 0xf << 28)
+#define RSRI_CHIPID_SHFT	12
+#define RSRI_CHIPID_MASK	(UINT64_CAST 0xffff << 12)
+#define RSRI_MFGID_SHFT		1
+#define RSRI_MFGID_MASK		(UINT64_CAST 0x7ff << 1)
+
+#define RSRI_LSTAT_WENTDOWN	0
+#define RSRI_LSTAT_RESETFAIL	1
+#define RSRI_LSTAT_LINKUP	2
+#define RSRI_LSTAT_NOTUSED	3
+
+/*
+ * RR_PORT_RESET mask definitions
+ */
+
+#define RPRESET_WARM		(UINT64_CAST 1 << 9)
+#define RPRESET_LINK(_L)	(UINT64_CAST 1 << (_L))
+#define RPRESET_LOCAL		(UINT64_CAST 1)
+
+/*
+ * RR_PROT_CONF mask and shift definitions
+ */
+
+#define RPCONF_DIRCMPDIS_SHFT	13
+#define RPCONF_DIRCMPDIS_MASK	(UINT64_CAST 1 << 13)
+#define RPCONF_FORCELOCAL	(UINT64_CAST 1 << 12)
+#define RPCONF_FLOCAL_SHFT	12
+#define RPCONF_METAID_SHFT	8
+#define RPCONF_METAID_MASK	(UINT64_CAST 0xf << 8)
+#define RPCONF_RESETOK(_L)	(UINT64_CAST 1 << ((_L) - 1))
+
+/*
+ * RR_GLOBAL_PORT_DEF mask and shift definitions
+ */
+
+#define RGPD_MGLBLNHBR_ID_SHFT	12	/* -global neighbor ID */
+#define RGPD_MGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 12)
+#define RGPD_MGLBLNHBR_VLD_SHFT	11	/* -global neighbor Valid */
+#define RGPD_MGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 11)
+#define RGPD_MGLBLPORT_SHFT	8	/* -global neighbor Port */
+#define RGPD_MGLBLPORT_MASK	(UINT64_CAST 0x7 << 8)
+#define RGPD_PGLBLNHBR_ID_SHFT	4	/* +global neighbor ID */
+#define RGPD_PGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 4)
+#define RGPD_PGLBLNHBR_VLD_SHFT	3	/* +global neighbor Valid */
+#define RGPD_PGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 3)
+#define RGPD_PGLBLPORT_SHFT	0	/* +global neighbor Port */
+#define RGPD_PGLBLPORT_MASK	(UINT64_CAST 0x7 << 0)
+
+#define GLBL_PARMS_REGS		2	/* Two Global Parms registers */
+
+/*
+ * RR_GLOBAL_PARMS0 mask and shift definitions
+ */
+
+#define RGPARM0_ARB_VALUE_SHFT	54	/* Local Block Arbitration State */
+#define RGPARM0_ARB_VALUE_MASK	(UINT64_CAST 0x7 << 54)
+#define RGPARM0_ROTATEARB_SHFT	53	/* Rotate Local Block Arbitration */
+#define RGPARM0_ROTATEARB_MASK	(UINT64_CAST 0x1 << 53)
+#define RGPARM0_FAIREN_SHFT	52	/* Fairness logic Enable */
+#define RGPARM0_FAIREN_MASK	(UINT64_CAST 0x1 << 52)
+#define RGPARM0_LOCGNTTO_SHFT	40	/* Local grant timeout */
+#define RGPARM0_LOCGNTTO_MASK	(UINT64_CAST 0xfff << 40)
+#define RGPARM0_DATELINE_SHFT	38	/* Dateline crossing router */
+#define RGPARM0_DATELINE_MASK	(UINT64_CAST 0x1 << 38)
+#define RGPARM0_MAXRETRY_SHFT	28	/* Max retry count */
+#define RGPARM0_MAXRETRY_MASK	(UINT64_CAST 0x3ff << 28)
+#define RGPARM0_URGWRAP_SHFT	20	/* Urgent wrap */
+#define RGPARM0_URGWRAP_MASK	(UINT64_CAST 0xff << 20)
+#define RGPARM0_DEADLKTO_SHFT	16	/* Deadlock timeout */
+#define RGPARM0_DEADLKTO_MASK	(UINT64_CAST 0xf << 16)
+#define RGPARM0_URGVAL_SHFT	12	/* Urgent value */
+#define RGPARM0_URGVAL_MASK	(UINT64_CAST 0xf << 12)
+#define RGPARM0_VCHSELEN_SHFT	11	/* VCH_SEL_EN */
+#define RGPARM0_VCHSELEN_MASK	(UINT64_CAST 0x1 << 11)
+#define RGPARM0_LOCURGTO_SHFT	9	/* Local urgent timeout */
+#define RGPARM0_LOCURGTO_MASK	(UINT64_CAST 0x3 << 9)
+#define RGPARM0_TAILVAL_SHFT	5	/* Tail value */
+#define RGPARM0_TAILVAL_MASK	(UINT64_CAST 0xf << 5)
+#define RGPARM0_CLOCK_SHFT	1	/* Global clock select */
+#define RGPARM0_CLOCK_MASK	(UINT64_CAST 0xf << 1)
+#define RGPARM0_BYPEN_SHFT	0
+#define RGPARM0_BYPEN_MASK	(UINT64_CAST 1)	/* Bypass enable */
+
+/*
+ * RR_GLOBAL_PARMS1 shift and mask definitions
+ */
+
+#define RGPARM1_TTOWRAP_SHFT	12	/* Tail timeout wrap */
+#define RGPARM1_TTOWRAP_MASK	(UINT64_CAST 0xfffff << 12)
+#define RGPARM1_AGERATE_SHFT	8	/* Age rate */
+#define RGPARM1_AGERATE_MASK	(UINT64_CAST 0xf << 8)
+#define RGPARM1_JSWSTAT_SHFT	0	/* JTAG Sw Register bits */
+#define RGPARM1_JSWSTAT_MASK	(UINT64_CAST 0xff << 0)
+
+/*
+ * RR_DIAG_PARMS mask and shift definitions
+ */
+
+#define RDPARM_ABSHISTOGRAM	(UINT64_CAST 1 << 17)	/* Absolute histgrm */
+#define RDPARM_DEADLOCKRESET	(UINT64_CAST 1 << 16)	/* Reset on deadlck */
+#define RDPARM_DISABLE(_L)	(UINT64_CAST 1 << ((_L) +  7))
+#define RDPARM_SENDERROR(_L)	(UINT64_CAST 1 << ((_L) -  1))
+
+/*
+ * RR_DEBUG_ADDR mask and shift definitions
+ */
+
+#define RDA_DATA_SHFT		10	/* Observed debug data */
+#define RDA_DATA_MASK		(UINT64_CAST 0xffff << 10)
+#define RDA_ADDR_SHFT		0	/* debug address for data */
+#define RDA_ADDR_MASK		(UINT64_CAST 0x3ff << 0)
+
+/*
+ * RR_LB_TO_L2 mask and shift definitions
+ */
+
+#define RLBTOL2_DATA_VLD_SHFT	32	/* data is valid for JTAG controller */
+#define RLBTOL2_DATA_VLD_MASK	(UINT64_CAST 0x1 << 32)
+#define RLBTOL2_DATA_SHFT	0	/* data bits for JTAG controller */
+#define RLBTOL2_DATA_MASK	(UINT64_CAST 0xffffffff)
+
+/*
+ * RR_L2_TO_LB mask and shift definitions
+ */
+
+#define RL2TOLB_DATA_VLD_SHFT	33	/* data is valid from JTAG controller */
+#define RL2TOLB_DATA_VLD_MASK	(UINT64_CAST 0x1 << 33)
+#define RL2TOLB_PARITY_SHFT	32	/* sw implemented parity for data */
+#define RL2TOLB_PARITY_MASK	(UINT64_CAST 0x1 << 32)
+#define RL2TOLB_DATA_SHFT	0	/* data bits from JTAG controller */
+#define RL2TOLB_DATA_MASK	(UINT64_CAST 0xffffffff)
+
+/*
+ * RR_JBUS_CONTROL mask and shift definitions
+ */
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
-#include <asm/sn/sn1/router.h>
+#define RJC_POS_BITS_SHFT	20	/* Router position bits */
+#define RJC_POS_BITS_MASK	(UINT64_CAST 0xf << 20)
+#define RJC_RD_DATA_STROBE_SHFT	16	/* count when read data is strobed in */
+#define RJC_RD_DATA_STROBE_MASK	(UINT64_CAST 0xf << 16)
+#define RJC_WE_OE_HOLD_SHFT	8	/* time OE or WE is held */
+#define RJC_WE_OE_HOLD_MASK	(UINT64_CAST 0xff << 8)
+#define RJC_ADDR_SET_HLD_SHFT	0	/* time address driven around OE/WE */
+#define RJC_ADDR_SET_HLD_MASK	(UINT64_CAST 0xff)
+
+/*
+ * RR_SCRATCH_REGx mask and shift definitions
+ *  note: these fields represent a software convention, and are not
+ *        understood/interpreted by the hardware. 
+ */
+
+#define	RSCR0_BOOTED_SHFT	63
+#define	RSCR0_BOOTED_MASK	(UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT)
+#define RSCR0_LOCALID_SHFT	56
+#define RSCR0_LOCALID_MASK	(UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT)
+#define	RSCR0_UNUSED_SHFT	48
+#define	RSCR0_UNUSED_MASK	(UINT64_CAST 0xff << RSCR0_UNUSED_SHFT)
+#define RSCR0_NIC_SHFT		0
+#define RSCR0_NIC_MASK		(UINT64_CAST 0xffffffffffff)
+
+#define RSCR1_MODID_SHFT	0
+#define RSCR1_MODID_MASK	(UINT64_CAST 0xffff)
+
+/*
+ * RR_VECTOR_HW_BAR mask and shift definitions
+ */
+
+#define BAR_TX_SHFT		27	/* Barrier in trans(m)it when read */
+#define BAR_TX_MASK		(UINT64_CAST 1 << BAR_TX_SHFT)
+#define BAR_VLD_SHFT		26	/* Valid Configuration */
+#define BAR_VLD_MASK		(UINT64_CAST 1 << BAR_VLD_SHFT)
+#define BAR_SEQ_SHFT		24	/* Sequence number */
+#define BAR_SEQ_MASK		(UINT64_CAST 3 << BAR_SEQ_SHFT)
+#define BAR_LEAFSTATE_SHFT	18	/* Leaf State */
+#define BAR_LEAFSTATE_MASK	(UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT)
+#define BAR_PARENT_SHFT		14	/* Parent Port */
+#define BAR_PARENT_MASK		(UINT64_CAST 0xf << BAR_PARENT_SHFT)
+#define BAR_CHILDREN_SHFT	6	/* Child Select port bits */
+#define BAR_CHILDREN_MASK	(UINT64_CAST 0xff << BAR_CHILDREN_SHFT)
+#define BAR_LEAFCOUNT_SHFT	0	/* Leaf Count to trigger parent */
+#define BAR_LEAFCOUNT_MASK	(UINT64_CAST 0x3f)
+
+/*
+ * RR_PORT_PARMS(_L) mask and shift definitions
+ */
+
+#define RPPARM_MIPRESETEN_SHFT	29	/* Message In Progress reset enable */
+#define RPPARM_MIPRESETEN_MASK	(UINT64_CAST 0x1 << 29)
+#define RPPARM_UBAREN_SHFT	28	/* Enable user barrier requests */
+#define RPPARM_UBAREN_MASK	(UINT64_CAST 0x1 << 28)
+#define RPPARM_OUTPDTO_SHFT	24	/* Output Port Deadlock TO value */
+#define RPPARM_OUTPDTO_MASK	(UINT64_CAST 0xf << 24)
+#define RPPARM_PORTMATE_SHFT	21	/* Port Mate for the port */
+#define RPPARM_PORTMATE_MASK	(UINT64_CAST 0x7 << 21)
+#define RPPARM_HISTEN_SHFT	20	/* Histogram counter enable */
+#define RPPARM_HISTEN_MASK	(UINT64_CAST 0x1 << 20)
+#define RPPARM_HISTSEL_SHFT	18
+#define RPPARM_HISTSEL_MASK	(UINT64_CAST 0x3 << 18)
+#define RPPARM_DAMQHS_SHFT	16
+#define RPPARM_DAMQHS_MASK	(UINT64_CAST 0x3 << 16)
+#define RPPARM_NULLTO_SHFT	10
+#define RPPARM_NULLTO_MASK	(UINT64_CAST 0x3f << 10)
+#define RPPARM_MAXBURST_SHFT	0
+#define RPPARM_MAXBURST_MASK	(UINT64_CAST 0x3ff)
+
+/*
+ * NOTE: Normally the kernel tracks only UTILIZATION statistics.
+ * The other 2 should not be used, except during any experimentation
+ * with the router.
+ */
+#define RPPARM_HISTSEL_AGE	0	/* Histogram age characterization.  */
+#define RPPARM_HISTSEL_UTIL	1	/* Histogram link utilization 	    */
+#define RPPARM_HISTSEL_DAMQ	2	/* Histogram DAMQ characterization. */
+
+/*
+ * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions
+ */
+#define RSERR_POWERNOK		(UINT64_CAST 1 << 38)
+#define RSERR_PORT_DEADLOCK     (UINT64_CAST 1 << 37)
+#define RSERR_WARMRESET         (UINT64_CAST 1 << 36)
+#define RSERR_LINKRESET         (UINT64_CAST 1 << 35)
+#define RSERR_RETRYTIMEOUT      (UINT64_CAST 1 << 34)
+#define RSERR_FIFOOVERFLOW	(UINT64_CAST 1 << 33)
+#define RSERR_ILLEGALPORT	(UINT64_CAST 1 << 32)
+#define RSERR_DEADLOCKTO_SHFT	28
+#define RSERR_DEADLOCKTO_MASK	(UINT64_CAST 0xf << 28)
+#define RSERR_RECVTAILTO_SHFT	24
+#define RSERR_RECVTAILTO_MASK	(UINT64_CAST 0xf << 24)
+#define RSERR_RETRYCNT_SHFT	16
+#define RSERR_RETRYCNT_MASK	(UINT64_CAST 0xff << 16)
+#define RSERR_CBERRCNT_SHFT	8
+#define RSERR_CBERRCNT_MASK	(UINT64_CAST 0xff << 8)
+#define RSERR_SNERRCNT_SHFT	0
+#define RSERR_SNERRCNT_MASK	(UINT64_CAST 0xff << 0)
+
+
+#define PORT_STATUS_UP		(1 << 0)	/* Router link up */
+#define PORT_STATUS_FENCE	(1 << 1)	/* Router link fenced */
+#define PORT_STATUS_RESETFAIL	(1 << 2)	/* Router link didnot 
+						 * come out of reset */
+#define PORT_STATUS_DISCFAIL	(1 << 3)	/* Router link failed after 
+						 * out of reset but before
+						 * router tables were
+						 * programmed
+						 */
+#define PORT_STATUS_KERNFAIL	(1 << 4)	/* Router link failed
+						 * after reset and the 
+						 * router tables were
+						 * programmed
+						 */
+#define PORT_STATUS_UNDEF	(1 << 5)	/* Unable to pinpoint
+						 * why the router link
+						 * went down
+						 */	
+#define PROBE_RESULT_BAD	(-1)		/* Set if any of the router
+						 * links failed after reset
+						 */
+#define PROBE_RESULT_GOOD	(0)		/* Set if all the router links
+						 * which came out of reset 
+						 * are up
+						 */
+
+/* Should be enough for 256 CPUs */
+#define MAX_RTR_BREADTH		64		/* Max # of routers possible */
+
+/* Get the require set of bits in a var. corr to a sequence of bits  */
+#define GET_FIELD(var, fname) \
+        ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT)
+/* Set the require set of bits in a var. corr to a sequence of bits  */
+#define SET_FIELD(var, fname, fval) \
+        ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT)
+
+
+#ifndef __ASSEMBLY__
+
+typedef struct router_map_ent_s {
+	uint64_t	nic;
+	moduleid_t	module;
+	slotid_t	slot;
+} router_map_ent_t;
+
+struct rr_status_error_fmt {
+	uint64_t	rserr_unused		: 30,
+			rserr_fifooverflow	: 1,
+			rserr_illegalport	: 1,
+			rserr_deadlockto	: 4,
+			rserr_recvtailto	: 4,
+			rserr_retrycnt		: 8,
+			rserr_cberrcnt		: 8,
+			rserr_snerrcnt		: 8;
+};
+
+/*
+ * This type is used to store "absolute" counts of router events
+ */
+typedef int	router_count_t;
+
+/* All utilizations are on a scale from 0 - 1023. */
+#define RP_BYPASS_UTIL	0
+#define RP_RCV_UTIL	1
+#define RP_SEND_UTIL	2
+#define RP_TOTAL_PKTS	3	/* Free running clock/packet counter */
+
+#define RP_NUM_UTILS	3
+
+#define RP_HIST_REGS	2
+#define RP_NUM_BUCKETS  4
+#define RP_HIST_TYPES	3
+
+#define RP_AGE0		0
+#define RP_AGE1		1
+#define RP_AGE2		2
+#define RP_AGE3		3
+
+
+#define RR_UTIL_SCALE	1024
+
+/*
+ * Router port-oriented information
+ */
+typedef struct router_port_info_s {
+	router_reg_t	rp_histograms[RP_HIST_REGS];/* Port usage info */
+	router_reg_t	rp_port_error;		/* Port error info */
+	router_count_t	rp_retry_errors;	/* Total retry errors */
+	router_count_t	rp_sn_errors;		/* Total sn errors */
+	router_count_t	rp_cb_errors;		/* Total cb errors */
+	int		rp_overflows;		/* Total count overflows */
+	int		rp_excess_err;		/* Port has excessive errors */
+	ushort		rp_util[RP_NUM_BUCKETS];/* Port utilization */
+} router_port_info_t;
+
+#define ROUTER_INFO_VERSION	7
+
+struct lboard_s;
+
+/*
+ * Router information
+ */
+typedef struct router_info_s {
+	char		ri_version;	/* structure version		    */
+	cnodeid_t	ri_cnode;	/* cnode of its legal guardian hub  */
+	nasid_t		ri_nasid;	/* Nasid of same 		    */
+	char		ri_ledcache;	/* Last LED bitmap		    */
+	char		ri_leds;	/* Current LED bitmap		    */
+	char		ri_portmask;	/* Active port bitmap		    */
+	router_reg_t	ri_stat_rev_id;	/* Status rev ID value		    */
+	net_vec_t	ri_vector;	/* vector from guardian to router   */
+	int		ri_writeid;	/* router's vector write ID	    */
+	int64_t	ri_timebase;	/* Time of first sample		    */
+	int64_t	ri_timestamp;	/* Time of last sample		    */
+	router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info      */
+	moduleid_t	ri_module;	/* Which module are we in?	    */
+	slotid_t	ri_slotnum;	/* Which slot are we in?	    */
+	router_reg_t	ri_glbl_parms[GLBL_PARMS_REGS];
+					/* Global parms0&1 register contents*/
+	devfs_handle_t	ri_vertex;	/* hardware graph vertex            */
+	router_reg_t	ri_prot_conf;	/* protection config. register	    */
+	int64_t	ri_per_minute;	/* Ticks per minute		    */
+
+	/*
+	 * Everything below here is for kernel use only and may change at	
+	 * at any time with or without a change in teh revision number
+	 *
+	 * Any pointers or things that come and go with DEBUG must go at
+ 	 * the bottom of the structure, below the user stuff.
+	 */
+	char		ri_hist_type;   /* histogram type		    */
+	devfs_handle_t	ri_guardian;	/* guardian node for the router	    */
+	int64_t	ri_last_print;	/* When did we last print	    */
+	char		ri_print;	/* Should we print 		    */
+	char 		ri_just_blink;	/* Should we blink the LEDs         */
+	
+#ifdef DEBUG
+	int64_t	ri_deltatime;	/* Time it took to sample	    */
 #endif
+	spinlock_t	ri_lock;	/* Lock for access to router info   */
+	net_vec_t	*ri_vecarray;	/* Pointer to array of vectors	    */
+	struct lboard_s	*ri_brd;	/* Pointer to board structure	    */
+	char *		ri_name;	/* This board's hwg path 	    */
+        unsigned char	ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a 
+					message to availmon */
+} router_info_t;
+
+
+/* Router info location specifiers */
+
+#define RIP_PROMLOG			2	/* Router info in promlog */
+#define RIP_CONSOLE			4	/* Router info on console */
+
+#define ROUTER_INFO_PRINT(_rip,_where)	(_rip->ri_print |= _where)	
+					/* Set the field used to check if a 
+					 * router info can be printed
+					 */
+#define IS_ROUTER_INFO_PRINTED(_rip,_where)	\
+					(_rip->ri_print & _where)	
+					/* Was the router info printed to
+					 * the given location (_where) ?
+					 * Mainly used to prevent duplicate
+					 * router error states.
+					 */
+#define ROUTER_INFO_LOCK(_rip,_s)	_s = mutex_spinlock(&(_rip->ri_lock))
+					/* Take the lock on router info
+					 * to gain exclusive access
+					 */
+#define ROUTER_INFO_UNLOCK(_rip,_s)	mutex_spinunlock(&(_rip->ri_lock),_s)
+					/* Release the lock on router info */
+/* 
+ * Router info hanging in the nodepda 
+ */
+typedef struct nodepda_router_info_s {
+	devfs_handle_t 	router_vhdl;	/* vertex handle of the router 	    */
+	short		router_port;	/* port thru which we entered       */
+	short		router_portmask;
+	moduleid_t	router_module;	/* module in which router is there  */
+	slotid_t	router_slot;	/* router slot			    */
+	unsigned char	router_type;	/* kind of router 		    */
+	net_vec_t	router_vector;	/* vector from the guardian node    */
+
+	router_info_t	*router_infop;	/* info hanging off the hwg vertex  */
+	struct nodepda_router_info_s *router_next;
+	                                /* pointer to next element 	    */
+} nodepda_router_info_t;
+
+#define ROUTER_NAME_SIZE	20	/* Max size of a router name */
+
+#define NORMAL_ROUTER_NAME	"normal_router"
+#define NULL_ROUTER_NAME	"null_router"
+#define META_ROUTER_NAME	"meta_router"
+#define REPEATER_ROUTER_NAME	"repeater_router"
+#define UNKNOWN_ROUTER_NAME	"unknown_router" 
+
+/* The following definitions are needed by the router traversing
+ * code either using the hardware graph or using vector operations.
+ */
+/* Structure of the router queue element */
+typedef struct router_elt_s {
+	union {
+		/* queue element structure during router probing */
+		struct {
+			/* number-in-a-can (unique) for the router */
+			nic_t		nic;	
+			/* vector route from the master hub to 
+			 * this router.
+			 */
+			net_vec_t	vec;	
+			/* port status */
+			uint64_t	status;	
+			char		port_status[MAX_ROUTER_PORTS + 1];
+		} r_elt;
+		/* queue element structure during router guardian 
+		 * assignment
+		 */
+		struct {
+			/* vertex handle for the router */
+			devfs_handle_t	vhdl;
+			/* guardian for this router */
+			devfs_handle_t	guard;	
+			/* vector router from the guardian to the router */
+			net_vec_t	vec;
+		} k_elt;
+	} u;
+	                        /* easy to use port status interpretation */
+} router_elt_t;
+
+/* structure of the router queue */
+
+typedef struct router_queue_s {
+	char		head;	/* Point where a queue element is inserted */
+	char		tail;	/* Point where a queue element is removed */
+	int		type;
+	router_elt_t	array[MAX_RTR_BREADTH];
+	                        /* Entries for queue elements */
+} router_queue_t;
+
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * RR_HISTOGRAM(_L) mask and shift definitions
+ * There are two 64 bit histogram registers, so the following macros take
+ * into account dealing with an array of 4 32 bit values indexed by _x
+ */
+
+#define RHIST_BUCKET_SHFT(_x)	(32 * ((_x) & 0x1))
+#define RHIST_BUCKET_MASK(_x)	(UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1))
+#define RHIST_GET_BUCKET(_x, _reg)	\
+	((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x))
+
+/*
+ * RR_RESET_MASK(_L) mask and shift definitions
+ */
+
+#define RRM_RESETOK(_L)		(UINT64_CAST 1 << ((_L) - 1))
+#define RRM_RESETOK_ALL		ALL_PORTS
+
+/*
+ * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions
+ */
+
+#define RTABLE_SHFT(_L)		(4 * ((_L) - 1))
+#define RTABLE_MASK(_L)		(UINT64_CAST 0x7 << RTABLE_SHFT(_L))
+
+
+#define	ROUTERINFO_STKSZ	4096
+
+#ifndef __ASSEMBLY__
+
+int router_reg_read(router_info_t *rip, int regno, router_reg_t *val);
+int router_reg_write(router_info_t *rip, int regno, router_reg_t val);
+int router_get_info(devfs_handle_t routerv, router_info_t *, int);
+int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip);
+int router_set_leds(router_info_t *rip);
+void router_print_state(router_info_t *rip, int level,
+		   void (*pf)(int, char *, ...),int print_where);
+void capture_router_stats(router_info_t *rip);
+
+
+int 	probe_routers(void);
+void 	get_routername(unsigned char brd_type,char *rtrname);
+void 	router_guardians_set(devfs_handle_t hwgraph_root);
+int 	router_hist_reselect(router_info_t *, int64_t);
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_ROUTER_H */
+#endif /* _ASM_IA64_SN_ROUTER_H */
diff -Nru a/include/asm-ia64/sn/sgi.h b/include/asm-ia64/sn/sgi.h
--- a/include/asm-ia64/sn/sgi.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sgi.h	Fri Mar 15 17:51:01 2002
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 
-#ifndef _ASM_SN_SGI_H
-#define _ASM_SN_SGI_H
+#ifndef _ASM_IA64_SN_SGI_H
+#define _ASM_IA64_SN_SGI_H
 
 #include <linux/config.h>
 
@@ -95,9 +94,6 @@
 				 bigger. This is NULL-terminated  */
 };
 
-#define MIN(_a,_b)		((_a)<(_b)?(_a):(_b))
-
-typedef uint32_t app32_ptr_t;	/* needed by edt.h */
 typedef int64_t  __psint_t;	/* needed by klgraph.c */
 
 typedef enum { B_FALSE, B_TRUE } boolean_t;
@@ -105,8 +101,6 @@
 #define ctob(x)			((uint64_t)(x)*NBPC)
 #define btoc(x)			(((uint64_t)(x)+(NBPC-1))/NBPC)
 
-typedef __psunsigned_t nic_data_t;
-
 
 /*
 ** Possible return values from graph routines.
@@ -129,10 +123,6 @@
 					 * calls */
 #define XG_WIDGET_PART_NUM      0xC102          /* KONA/xt_regs.h     XG_XT_PART_NUM_VALUE */
 
-#ifndef TO_PHYS_MASK
-#define TO_PHYS_MASK 0x0000000fffffffff
-#endif
-
 typedef uint64_t vhandl_t;
 
 
@@ -159,7 +149,7 @@
 typedef uint64_t mrlock_t;	/* needed by devsupport.c */
 
 #define HUB_PIO_CONVEYOR 0x1
-#define CNODEID_NONE (cnodeid_t)-1
+#define CNODEID_NONE ((cnodeid_t)-1)
 #define XTALK_PCI_PART_NUM "030-1275-"
 #define kdebug 0
 
@@ -177,7 +167,7 @@
 #define kern_free(x)		kfree(x)
 
 typedef cpuid_t cpu_cookie_t;
-#define CPU_NONE		-1
+#define CPU_NONE		(-1)
 
 /*
  * mutext support mapping
@@ -225,9 +215,6 @@
         } } while(0)
 #endif	/* DISABLE_ASSERT */
 
-#define PRINT_WARNING(x...)	do { printk("WARNING : "); printk(x); } while(0)
-#define PRINT_NOTICE(x...)	do { printk("NOTICE : "); printk(x); } while(0)
-#define PRINT_ALERT(x...)	do { printk("ALERT : "); printk(x); } while(0)
 #define PRINT_PANIC		panic
 
 #ifdef CONFIG_SMP
@@ -238,4 +225,4 @@
 
 #include <asm/sn/hack.h>	/* for now */
 
-#endif	/* _ASM_SN_SGI_H */
+#endif /* _ASM_IA64_SN_SGI_H */
diff -Nru a/include/asm-ia64/sn/simulator.h b/include/asm-ia64/sn/simulator.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/simulator.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,27 @@
+#ifndef _ASM_IA64_SN_SIMULATOR_H
+#define _ASM_IA64_SN_SIMULATOR_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN_SIM
+
+#define SNMAGIC 0xaeeeeeee8badbeefL
+#define IS_RUNNING_ON_SIMULATOR() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
+
+#define SIMULATOR_SLEEP()	asm("nop.i 0x8beef")
+
+#else
+
+#define IS_RUNNING_ON_SIMULATOR()	(0)
+#define SIMULATOR_SLEEP()
+
+#endif
+
+#endif /* _ASM_IA64_SN_SIMULATOR_H */
diff -Nru a/include/asm-ia64/sn/slotnum.h b/include/asm-ia64/sn/slotnum.h
--- a/include/asm-ia64/sn/slotnum.h	Fri Mar 15 17:51:04 2002
+++ b/include/asm-ia64/sn/slotnum.h	Fri Mar 15 17:51:04 2002
@@ -4,22 +4,23 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SLOTNUM_H
-#define _ASM_SN_SLOTNUM_H
+#ifndef _ASM_IA64_SN_SLOTNUM_H
+#define _ASM_IA64_SN_SLOTNUM_H
 
 #include <linux/config.h>
 
 typedef	unsigned char slotid_t;
 
-#if defined (CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined (CONFIG_IA64_SGI_SN1)
 #include <asm/sn/sn1/slotnum.h>
+#elif defined (CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/slotnum.h>
 #else
 
 #error <<BOMB! slotnum defined only for SN0 and SN1 >>
 
-#endif /* !CONFIG_SGI_IP35 && !CONFIG_IA64_SGI_SN1 */
+#endif /* !CONFIG_IA64_SGI_SN1 */
 
-#endif /* _ASM_SN_SLOTNUM_H */
+#endif /* _ASM_IA64_SN_SLOTNUM_H */
diff -Nru a/include/asm-ia64/sn/sn1/addrs.h b/include/asm-ia64/sn/sn1/addrs.h
--- a/include/asm-ia64/sn/sn1/addrs.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/addrs.h	Fri Mar 15 17:51:03 2002
@@ -4,19 +4,21 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_ADDRS_H
-#define _ASM_SN_SN1_ADDRS_H
+#ifndef _ASM_IA64_SN_SN1_ADDRS_H
+#define _ASM_IA64_SN_SN1_ADDRS_H
 
+#include <linux/config.h>
+
+#ifdef CONFIG_IA64_SGI_SN1
 /*
- * IP35 (on a TRex) Address map
+ * SN1 (on a TRex) Address map
  *
  * This file contains a set of definitions and macros which are used
  * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
- * and UNCAC) used by the IP35 architecture.  It also contains addresses
+ * and UNCAC) used by the SN1 architecture.  It also contains addresses
  * for "major" statically locatable PROM/Kernel data structures, such as
  * the partition table, the configuration data structure, etc.
  * We make an implicit assumption that the processor using this file
@@ -32,7 +34,6 @@
  *	 appropriately.
  */
 
-#include <linux/config.h>
 
 /*
  * Some of the macros here need to be casted to appropriate types when used
@@ -40,22 +41,14 @@
  * use some new ANSI preprocessor stuff to paste these on where needed.
  */
 
-#if defined(_RUN_UNCACHED)
-#define CAC_BASE		0x9600000000000000
-#else
-#ifndef __ia64
-#define CAC_BASE		0xa800000000000000
-#else
 #define CAC_BASE                0xe000000000000000
-#endif
-#endif
-
 #define HSPEC_BASE              0xc0000b0000000000
 #define HSPEC_SWIZ_BASE         0xc000030000000000
 #define IO_BASE                 0xc0000a0000000000
 #define IO_SWIZ_BASE            0xc000020000000000
-#define MSPEC_BASE              0xc000000000000000
+#define MSPEC_BASE              0xc000090000000000
 #define UNCAC_BASE              0xc000000000000000
+#define TO_PHYS_MASK		0x000000ffffffffff
 
 #define TO_PHYS(x)		(	      ((x) & TO_PHYS_MASK))
 #define TO_CAC(x)		(CAC_BASE   | ((x) & TO_PHYS_MASK))
@@ -109,18 +102,14 @@
 #define NASID_GET(_pa)		(int) ((UINT64_CAST (_pa) >>		\
 					NASID_SHFT) & NASID_BITMASK)
 
-#if _LANGUAGE_C && !defined(_STANDALONE)
-#ifndef REAL_HARDWARE
-#define NODE_SWIN_BASE(nasid, widget) RAW_NODE_SWIN_BASE(nasid, widget)
-#else
+#ifndef __ASSEMBLY__
 #define NODE_SWIN_BASE(nasid, widget)					\
 	((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)		\
 	: RAW_NODE_SWIN_BASE(nasid, widget))
-#endif
 #else
 #define NODE_SWIN_BASE(nasid, widget) \
      (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /*
  * The following definitions pertain to the IO special address
@@ -155,7 +144,7 @@
 
 /*
  * The following define the major position-independent aliases used
- * in IP27.
+ * in SN1.
  *	CALIAS -- Varies in size, points to the first n bytes of memory
  *		  	on the reader's node.
  */
@@ -169,11 +158,6 @@
 
 #define SN0_WIDGET_BASE(_nasid, _wid)	(NODE_SWIN_BASE((_nasid), (_wid)))
 
-#if _LANGUAGE_C
-#define KERN_NMI_ADDR(nasid, slice)					\
-                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + 	\
-				  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
-#endif /* _LANGUAGE_C */
 
 
 /*
@@ -197,7 +181,7 @@
 #define KL_UART_CMD	LOCAL_HSPEC(HSPEC_UART_0)	/* UART command reg */
 #define KL_UART_DATA	LOCAL_HSPEC(HSPEC_UART_1)	/* UART data reg */
 
-#if !_LANGUAGE_ASSEMBLY
+#if !__ASSEMBLY__
 /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
  * CACHE_ERR_SP_PTR could either contain an address to the stack, or
  * the stack could start at CACHE_ERR_SP_PTR
@@ -210,28 +194,9 @@
 #define CACHE_ERR_SP		(CACHE_ERR_SP_PTR - 16)
 #define CACHE_ERR_AREA_SIZE	(ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
 
-#endif	/* !_LANGUAGE_ASSEMBLY */
+#endif	/* !__ASSEMBLY__ */
+
 
-/* Each CPU accesses UALIAS at a different physaddr, on 32k boundaries
- * This determines the locations of the exception vectors
- */
-#define UALIAS_FLIP_BASE	UALIAS_BASE
-#define UALIAS_FLIP_SHIFT	15
-#define UALIAS_FLIP_ADDR(_x)	((_x) ^ (cputoslice(getcpuid())<<UALIAS_FLIP_SHIFT))
-
-#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-#define EX_HANDLER_OFFSET(slice) ((slice) << UALIAS_FLIP_SHIFT)
-#endif
-#define EX_HANDLER_ADDR(nasid, slice)					\
-	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
-#define EX_HANDLER_SIZE		0x0400
-
-#if !defined(CONFIG_IA64_SGI_SN1) && !defined(CONFIG_IA64_GENERIC)
-#define EX_FRAME_OFFSET(slice)	((slice) << UALIAS_FLIP_SHIFT | 0x400)
-#endif
-#define EX_FRAME_ADDR(nasid, slice)					\
-	PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
-#define EX_FRAME_SIZE		0x0c00
 
 #define _ARCSPROM
 
@@ -241,7 +206,7 @@
  * The PROM needs to pass the device base address and the
  * device pci cfg space address to the device drivers during
  * install. The COMPONENT->Key field is used for this purpose.
- * Macros needed by IP27 device drivers to convert the
+ * Macros needed by SN1 device drivers to convert the
  * COMPONENT->Key field to the respective base address.
  * Key field looks as follows:
  *
@@ -256,7 +221,7 @@
  * is in place.
  */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #define uchar unsigned char
 
@@ -301,8 +266,9 @@
 #define PUT_INSTALL_STATUS(c,s)		c->Revision = s
 #define GET_INSTALL_STATUS(c)		c->Revision
 
-#endif /* LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 #endif /* _STANDALONE */
+#endif /* CONFIG_IA64_SGI_SN1 */
 
-#endif /* _ASM_SN_SN1_ADDRS_H */
+#endif /* _ASM_IA64_SN_SN1_ADDRS_H */
diff -Nru a/include/asm-ia64/sn/sn1/arch.h b/include/asm-ia64/sn/sn1/arch.h
--- a/include/asm-ia64/sn/sn1/arch.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn1/arch.h	Fri Mar 15 17:51:01 2002
@@ -4,29 +4,29 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_ARCH_H
-#define _ASM_SN_SN1_ARCH_H
+#ifndef _ASM_IA64_SN_SN1_ARCH_H
+#define _ASM_IA64_SN_SN1_ARCH_H
 
 #if defined(N_MODE)
 #error "ERROR constants defined only for M-mode"
 #endif
 
+#include <linux/threads.h>
+#include <asm/types.h>
+
+#define CPUS_PER_NODE           4       /* CPUs on a single hub */
+#define CPUS_PER_SUBNODE        2       /* CPUs on a single hub PI */
+
 /*
  * This is the maximum number of NASIDS that can be present in a system.
+ * This include ALL nodes in ALL partitions connected via NUMALINK.
  * (Highest NASID plus one.)
  */
 #define MAX_NASIDS              128
 
 /*
- * MAXCPUS refers to the maximum number of CPUs in a single kernel.
- * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
- */
-#define MAXCPUS                 512
-
-/*
  * This is the maximum number of nodes that can be part of a kernel.
  * Effectively, it's the maximum number of compact node ids (cnodeid_t).
  * This is not necessarily the same as MAX_NASIDS.
@@ -40,6 +40,19 @@
 #define MAX_NONPREMIUM_REGIONS  16
 #define MAX_PREMIUM_REGIONS     MAX_REGIONS
 
+/*
+ * Slot constants for IP35
+ */
+
+#define MAX_MEM_SLOTS    8                     /* max slots per node */
+
+#if defined(N_MODE)
+#error "N-mode not supported"
+#endif
+
+#define SLOT_SHIFT              (30)
+#define SLOT_MIN_MEM_SIZE       (64*1024*1024)
+
 
 /*
  * MAX_PARITIONS refers to the maximum number of logically defined 
@@ -51,17 +64,14 @@
 #define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
 
 /*
- * Slot constants for IP35
+ * New stuff in here from Irix sys/pfdat.h.
  */
+#define SLOT_PFNSHIFT           (SLOT_SHIFT - PAGE_SHIFT)
+#define PFN_NASIDSHFT           (NASID_SHFT - PAGE_SHIFT)
+#define slot_getbasepfn(node,slot)  (mkpfn(COMPACT_TO_NASID_NODEID(node), slot<<SLOT_PFNSHIFT))
+#define mkpfn(nasid, off)       (((pfn_t)(nasid) << PFN_NASIDSHFT) | (off))
 
-#define MAX_MEM_SLOTS    8                     /* max slots per node */
-
-#if defined(N_MODE)
-#error "N-mode not supported"
-#endif
 
-#define SLOT_SHIFT      	(30)
-#define SLOT_MIN_MEM_SIZE	(64*1024*1024)
 
 /*
  * two PIs per bedrock, two CPUs per PI
@@ -76,4 +86,4 @@
 #define TO_SLICE(subn, local)	(((subn) << SUBNODE_SHFT) | \
 				 ((local) << LOCALCPU_SHFT))
 
-#endif /* _ASM_SN_SN1_ARCH_H */
+#endif /* _ASM_IA64_SN_SN1_ARCH_H */
diff -Nru a/include/asm-ia64/sn/sn1/bedrock.h b/include/asm-ia64/sn/sn1/bedrock.h
--- a/include/asm-ia64/sn/sn1/bedrock.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/bedrock.h	Fri Mar 15 17:51:03 2002
@@ -4,14 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_BEDROCK_H
-#define _ASM_SN_SN1_BEDROCK_H
+#ifndef _ASM_IA64_SN_SN1_BEDROCK_H
+#define _ASM_IA64_SN_SN1_BEDROCK_H
 
-#include <linux/config.h>
 
 /* The secret password; used to release protection */
 #define HUB_PASSWORD		0x53474972756c6573ull
@@ -24,7 +22,6 @@
 
 #define MAX_HUB_PATH		80
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #include <asm/sn/arch.h>
 #include <asm/sn/sn1/addrs.h>
 #include <asm/sn/sn1/hubpi.h>
@@ -40,19 +37,13 @@
 #include <asm/sn/sn1/hublb_next.h>
 #include <asm/sn/sn1/hubxb_next.h>
 
-#else /* ! CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 */
-
-<< BOMB! CONFIG_SGI_IP35 is only defined for IP35 >>
-
-#endif /* defined(CONFIG_SGI_IP35) */
-
 /* Translation of uncached attributes */
 #define	UATTR_HSPEC	0
 #define	UATTR_IO	1
 #define	UATTR_MSPEC	2
 #define	UATTR_UNCAC	3
 
-#if _LANGUAGE_ASSEMBLY
+#if __ASSEMBLY__
 
 /*
  * Get nasid into register, r (uses at)
@@ -63,9 +54,9 @@
 	and	r, LRI_NODEID_MASK;			\
 	dsrl	r, LRI_NODEID_SHFT
 
-#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* __ASSEMBLY__ */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 #include <asm/sn/xtalk/xwidget.h>
 
@@ -78,6 +69,6 @@
 void capture_hub_stats(cnodeid_t, struct nodepda_s *);
 void init_hub_stats(cnodeid_t, struct nodepda_s *);
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_SN1_BEDROCK_H */
+#endif /* _ASM_IA64_SN_SN1_BEDROCK_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubdev.h b/include/asm-ia64/sn/sn1/hubdev.h
--- a/include/asm-ia64/sn/sn1/hubdev.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/sn1/hubdev.h	Fri Mar 15 17:51:02 2002
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_HUBDEV_H
-#define _ASM_SN_SN1_HUBDEV_H
+#ifndef _ASM_IA64_SN_SN1_HUBDEV_H
+#define _ASM_IA64_SN_SN1_HUBDEV_H
 
 extern void hubdev_init(void);
 extern void hubdev_register(int (*attach_method)(devfs_handle_t));
@@ -19,4 +18,4 @@
 extern caddr_t hubdev_prombase_get(devfs_handle_t hub);
 extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub);
 
-#endif /* _ASM_SN_SN1_HUBDEV_H */
+#endif /* _ASM_IA64_SN_SN1_HUBDEV_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubio.h b/include/asm-ia64/sn/sn1/hubio.h
--- a/include/asm-ia64/sn/sn1/hubio.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/hubio.h	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /************************************************************************
@@ -20,8 +19,8 @@
  ************************************************************************/
 
 
-#ifndef _ASM_SN_SN1_HUBIO_H
-#define _ASM_SN_SN1_HUBIO_H
+#ifndef _ASM_IA64_SN_SN1_HUBIO_H
+#define _ASM_IA64_SN_SN1_HUBIO_H
 
 
 #define    IIO_WID                   0x00400000    /*
@@ -762,7 +761,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -2942,15 +2941,15 @@
 typedef union ii_ilct_u {
 	bdrkreg_t	ii_ilct_regval;
 	struct  {
-		bdrkreg_t	i_rsvd                    :	 9;
-		bdrkreg_t	i_test_err_capture        :	 1;
-		bdrkreg_t	i_test_clear              :	 1;
-		bdrkreg_t	i_test_flit               :	 3;
-		bdrkreg_t	i_test_cberr              :	 1;
-		bdrkreg_t	i_test_valid              :	 1;
-		bdrkreg_t	i_test_data               :	20;
-		bdrkreg_t	i_test_mask               :	 8;
-		bdrkreg_t	i_test_seed               :	20;
+		bdrkreg_t	i_test_seed		  :	20;
+		bdrkreg_t	i_test_mask		  :	 8;
+		bdrkreg_t	i_test_data		  :	20;
+		bdrkreg_t	i_test_valid		  :	 1;
+		bdrkreg_t	i_test_cberr		  :	 1;
+		bdrkreg_t	i_test_flit		  :	 3;
+		bdrkreg_t	i_test_clear		  :	 1;
+		bdrkreg_t	i_test_err_capture	  :	 1;
+		bdrkreg_t	i_rsvd			  :	 9;
 	} ii_ilct_fld_s;
 } ii_ilct_u_t;
 
@@ -4935,7 +4934,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -5014,4 +5013,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBIO_H */
+#endif /* _ASM_IA64_SN_SN1_HUBIO_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubio_next.h b/include/asm-ia64/sn/sn1/hubio_next.h
--- a/include/asm-ia64/sn/sn1/hubio_next.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn1/hubio_next.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBIO_NEXT_H
-#define _ASM_SN_SN1_HUBIO_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBIO_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBIO_NEXT_H
 
 /*
  * Slightly friendlier names for some common registers.
@@ -64,7 +63,7 @@
 #define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
 #define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
 #define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
-#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
+#define IIO_BTE_OFF_1  (IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
 
 /* BTE register offsets from base */
 #define BTEOFF_STAT             0
@@ -78,11 +77,16 @@
 /* names used in hub_diags.c; carried over from SN0 */
 #define IIO_BASE_BTE0   IIO_IBLS_0		
 #define IIO_BASE_BTE1   IIO_IBLS_1		
-#if 0
-#define IIO_BASE        IIO_WID
-#define IIO_BASE_PERF   IIO_IPCR   /* IO Performance Control */
-#define IIO_PERF_CNT    IIO_IPPR   /* IO Performance Profiling */
-#endif
+
+/*
+ * Macro which takes the widget number, and returns the 
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range 
+ * 0, 8 - 0xF
+ */
+#define	IIO_IOPRB(_x)	(IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+			(_x) : \
+			(_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
 
 
 /* GFX Flow Control Node/Widget Register */
@@ -139,7 +143,7 @@
  * redefined big window 7 as small window 0.
  XXX does this still apply for SN1??
  */
-#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
 
 /*
  * Use the top big window as a surrogate for the first small window
@@ -343,7 +347,7 @@
  * CRBs.
  */
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /*
  * Easy access macros for CRBs, all 4 registers (A-D)
@@ -389,7 +393,7 @@
 #define icrbd_context   ii_icrb0_d_fld_s.id_context
 #define d_regvalue	ii_icrb0_d_regval
 
-#endif /* LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /* Number of widgets supported by hub */
 #define HUB_NUM_WIDGET          9
@@ -399,7 +403,7 @@
 #define HUB_WIDGET_PART_NUM     0xc110
 #define MAX_HUBS_PER_XBOW       2
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* A few more #defines for backwards compatibility */
 #define iprb_t          ii_iprb0_u_t
 #define iprb_regval     ii_iprb0_regval
@@ -430,11 +434,11 @@
 #define IO_PERF_SETS	32
 
 #if __KERNEL__
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* XXX moved over from SN/SN0/hubio.h -- each should be checked for SN1 */
 #include <asm/sn/alenlist.h>
 #include <asm/sn/dmamap.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/xtalk/xtalk.h>
 
 /* Bit for the widget in inbound access register */
@@ -699,12 +703,9 @@
 
 extern int
 hub_intr_connect(       hub_intr_t intr_hdl,    /* xtalk intr resource hndl */
-                        intr_func_t intr_func,  /* xtalk intr handler */
-                        void *intr_arg,         /* arg to intr handler */
                         xtalk_intr_setfunc_t setfunc,
                                                 /* func to set intr hw */
-                        void *setfunc_arg,      /* arg to setfunc */
-                        void *thread);          /* intr thread to use */
+                        void *setfunc_arg);     /* arg to setfunc */
 
 extern void
 hub_intr_disconnect(hub_intr_t intr_hdl);
@@ -756,6 +757,6 @@
 extern void hub_widgetdev_shutdown(devfs_handle_t, int);
 extern int  hub_dma_enabled(devfs_handle_t);
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 #endif /* _KERNEL */
-#endif  /* _ASM_SN_SN1_HUBIO_NEXT_H */
+#endif  /* _ASM_IA64_SN_SN1_HUBIO_NEXT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hublb.h b/include/asm-ia64/sn/sn1/hublb.h
--- a/include/asm-ia64/sn/sn1/hublb.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/sn1/hublb.h	Fri Mar 15 17:51:02 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
 /************************************************************************
@@ -20,8 +19,8 @@
  ************************************************************************/
 
 
-#ifndef _ASM_SN_SN1_HUBLB_H
-#define _ASM_SN_SN1_HUBLB_H
+#ifndef _ASM_IA64_SN_SN1_HUBLB_H
+#define _ASM_IA64_SN_SN1_HUBLB_H
 
 
 #define    LB_REV_ID                 0x00600000    /*
@@ -251,7 +250,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -1593,7 +1592,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -1605,4 +1604,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBLB_H */
+#endif /* _ASM_IA64_SN_SN1_HUBLB_H */
diff -Nru a/include/asm-ia64/sn/sn1/hublb_next.h b/include/asm-ia64/sn/sn1/hublb_next.h
--- a/include/asm-ia64/sn/sn1/hublb_next.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn1/hublb_next.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBLB_NEXT_H
-#define _ASM_SN_SN1_HUBLB_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBLB_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBLB_NEXT_H
 
 /**********************************************************************
 
@@ -107,4 +106,4 @@
 #define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
 #define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
 
-#endif	/* _ASM_SN_SN1_HUBLB_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBLB_NEXT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubmd.h b/include/asm-ia64/sn/sn1/hubmd.h
--- a/include/asm-ia64/sn/sn1/hubmd.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/hubmd.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBMD_H
-#define _ASM_SN_SN1_HUBMD_H
+#ifndef _ASM_IA64_SN_SN1_HUBMD_H
+#define _ASM_IA64_SN_SN1_HUBMD_H
 
 
 /************************************************************************
@@ -315,7 +314,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -2140,7 +2139,7 @@
  * corresponds to the valid bit, and bit 1 of each two-bit field        *
  * corresponds to the overrun bit.                                      *
  * The rule for the valid bit is that it gets set whenever that error   *
- * occurs, regardless of whether a higher priority error has occurred.   *
+ * occurs, regardless of whether a higher priority error has occurred.  *
  * The rule for the overrun bit is that it gets set whenever we are     *
  * unable to record the address information for this particular         *
  * error, due to a previous error of the same or higher priority.       *
@@ -2463,7 +2462,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -2474,4 +2473,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBMD_H */
+#endif /* _ASM_IA64_SN_SN1_HUBMD_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubmd_next.h b/include/asm-ia64/sn/sn1/hubmd_next.h
--- a/include/asm-ia64/sn/sn1/hubmd_next.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn1/hubmd_next.h	Fri Mar 15 17:51:01 2002
@@ -4,13 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBMD_NEXT_H
-#define _ASM_SN_SN1_HUBMD_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBMD_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBMD_NEXT_H
 
-#ifdef BRINGUP
 /* XXX moved over from SN/SN0/hubmd.h -- each should be checked for SN1 */
 /* In fact, most of this stuff is wrong. Some is correct, such as
  * MD_PAGE_SIZE and MD_PAGE_NUM_SHFT.
@@ -147,7 +145,7 @@
 #define MD_SPROT_REFCNT_GET(value) ( \
         ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 #ifdef LITTLE_ENDIAN
 
 typedef union md_perf_sel {
@@ -171,9 +169,8 @@
 } md_perf_sel_t;
 
 #endif
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#endif /* BRINGUP */
 
 /* Like SN0, SN1 supports a mostly-flat address space with 8
    CPU-visible, evenly spaced, contiguous regions, or "software
@@ -300,7 +297,7 @@
 
 ***********************************************************************/
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* Standard Directory Entries */
 
@@ -533,7 +530,7 @@
 	struct	md_pdir_sparse_fmt	pds_fmt;
 } md_pdir_t;
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 
 /**********************************************************************
@@ -568,7 +565,7 @@
 #define MD_DIR_WAIT		(UINT64_CAST 0x6)	/* ptr format, hw-defined */
 #define MD_DIR_POISONED		(UINT64_CAST 0x7)	/* ptr format, hw-defined */
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* Convert format and state fields into a single "cacheline state" value, defined above */
 
@@ -578,7 +575,7 @@
    MD_DIR_SHARED)
 #define MD_DIR_STATE(x) MD_FMT_ST_TO_STATE(MD_DIR_FORMAT(x), MD_DIR_STVAL(x))
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 
 
@@ -812,4 +809,4 @@
 
 #define MFC_ADDR_SHFT		6
 
-#endif  /* _ASM_SN_SN1_HUBMD_NEXT_H */
+#endif  /* _ASM_IA64_SN_SN1_HUBMD_NEXT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubni.h b/include/asm-ia64/sn/sn1/hubni.h
--- a/include/asm-ia64/sn/sn1/hubni.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/hubni.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBNI_H
-#define _ASM_SN_SN1_HUBNI_H
+#ifndef _ASM_IA64_SN_SN1_HUBNI_H
+#define _ASM_IA64_SN_SN1_HUBNI_H
 
 
 /************************************************************************
@@ -1000,7 +999,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -1615,7 +1614,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -1779,4 +1778,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBNI_H */
+#endif /* _ASM_IA64_SN_SN1_HUBNI_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubni_next.h b/include/asm-ia64/sn/sn1/hubni_next.h
--- a/include/asm-ia64/sn/sn1/hubni_next.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/hubni_next.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBNI_NEXT_H
-#define _ASM_SN_SN1_HUBNI_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBNI_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBNI_NEXT_H
 
 #define NI_LOCAL_ENTRIES        128
 #define NI_META_ENTRIES        1
@@ -67,7 +66,7 @@
 				 NPE_EXTLONG_MASK | NPE_EXTSHORT_MASK |\
 				 NPE_FIFOOVFLOW_MASK | NPE_TAILTO_MASK)
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /* NI_PORT_HEADER[AB] registers (not automatically generated) */
 
 #ifdef LITTLE_ENDIAN
@@ -172,4 +171,4 @@
 				 0x6 << NPP_NULL_TIMEOUT_SHFT | \
 				 0x3f0 << NPP_MAX_BURST_SHFT)
 
-#endif  /* _ASM_SN_SN1_HUBNI_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBNI_NEXT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubpi.h b/include/asm-ia64/sn/sn1/hubpi.h
--- a/include/asm-ia64/sn/sn1/hubpi.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/sn1/hubpi.h	Fri Mar 15 17:51:02 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBPI_H
-#define _ASM_SN_SN1_HUBPI_H
+#ifndef _ASM_IA64_SN_SN1_HUBPI_H
+#define _ASM_IA64_SN_SN1_HUBPI_H
 
 /************************************************************************
  *                                                                      *
@@ -551,7 +550,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -4248,7 +4247,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -4261,4 +4260,4 @@
 #define PI_GFX_PAGE_ENABLE	0x0000010000000000LL
 
 
-#endif /* _ASM_SN_SN1_HUBPI_H */
+#endif /* _ASM_IA64_SN_SN1_HUBPI_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubpi_next.h b/include/asm-ia64/sn/sn1/hubpi_next.h
--- a/include/asm-ia64/sn/sn1/hubpi_next.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/sn1/hubpi_next.h	Fri Mar 15 17:51:02 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBPI_NEXT_H
-#define _ASM_SN_SN1_HUBPI_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBPI_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBPI_NEXT_H
 
 
 /* define for remote PI_1 space. It is always half of a node_addressspace
@@ -54,7 +53,7 @@
     ((sts) & (PI_CRB_STS_I | PI_CRB_STS_H) | \
      ((sts) & (PI_CRB_STS_A | PI_CRB_STS_R)) >> 1)
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /*
  * format of error stack and error status registers.
  */
@@ -329,4 +328,4 @@
 /* Error stack address shift, for use with pi_stk_fmt.sk_addr */
 #define ERR_STK_ADDR_SHFT	3
 
-#endif /* _ASM_SN_SN1_HUBPI_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBPI_NEXT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubspc.h b/include/asm-ia64/sn/sn1/hubspc.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/hubspc.h	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,24 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_HUBSPC_H
+#define _ASM_IA64_SN_SN1_HUBSPC_H
+
+typedef enum {
+        HUBSPC_REFCOUNTERS,
+	HUBSPC_PROM
+} hubspc_subdevice_t;
+
+
+/*
+ * Reference Counters
+ */
+
+extern int refcounters_attach(devfs_handle_t hub);
+
+#endif /* _ASM_IA64_SN_SN1_HUBSPC_H */        
diff -Nru a/include/asm-ia64/sn/sn1/hubstat.h b/include/asm-ia64/sn/sn1/hubstat.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/hubstat.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,56 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000 - 2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN1_HUBSTAT_H
+#define _ASM_IA64_SN_SN1_HUBSTAT_H
+
+typedef int64_t 	hub_count_t;
+
+#define HUBSTAT_VERSION	1
+
+typedef struct hubstat_s {
+        char            hs_version;		/* structure version    */
+        cnodeid_t       hs_cnode;       	/* cnode of this hub    */
+        nasid_t         hs_nasid;       	/* Nasid of same        */	
+	int64_t		hs_timebase;		/* Time of first sample */
+	int64_t		hs_timestamp;		/* Time of last sample	*/
+	int64_t		hs_per_minute;		/* Ticks per minute 	*/
+
+	union {
+		hubreg_t	hs_niu_stat_rev_id; /* SN0: Status rev ID */
+		hubreg_t	hs_niu_port_status; /* SN1: Port status */
+	} hs_niu;
+
+        hub_count_t	hs_ni_retry_errors;	/* Total retry errors   */
+        hub_count_t	hs_ni_sn_errors;	/* Total sn errors      */
+        hub_count_t	hs_ni_cb_errors;	/* Total cb errors      */
+        int		hs_ni_overflows;	/* NI count overflows   */
+        hub_count_t	hs_ii_sn_errors;	/* Total sn errors      */
+        hub_count_t	hs_ii_cb_errors;	/* Total cb errors      */
+        int		hs_ii_overflows;	/* II count overflows   */
+
+	/*
+	 * Anything below this comment is intended for kernel internal-use
+	 * only and may be changed at any time.
+	 *
+	 * Any members that contain pointers or are conditionally compiled
+	 * need to be below here also.
+	 */
+        int64_t		hs_last_print;		/* When we last printed */
+        char		hs_print;		/* Should we print      */
+
+	char	       *hs_name;		/* This hub's name */
+	unsigned char	hs_maint;		/* Should we print to availmon */
+} hubstat_t;
+
+#define       hs_ni_stat_rev_id       hs_niu.hs_niu_stat_rev_id
+#define       hs_ni_port_status       hs_niu.hs_niu_port_status
+
+extern struct file_operations hub_mon_fops;
+
+#endif /* _ASM_IA64_SN_SN1_HUBSTAT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubxb.h b/include/asm-ia64/sn/sn1/hubxb.h
--- a/include/asm-ia64/sn/sn1/hubxb.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/hubxb.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBXB_H
-#define _ASM_SN_SN1_HUBXB_H
+#ifndef _ASM_IA64_SN_SN1_HUBXB_H
+#define _ASM_IA64_SN_SN1_HUBXB_H
 
 /************************************************************************
  *                                                                      *
@@ -273,7 +272,7 @@
 
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /************************************************************************
  *                                                                      *
@@ -1247,7 +1246,7 @@
 
 
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 /************************************************************************
  *                                                                      *
@@ -1286,4 +1285,4 @@
 
 
 
-#endif /* _ASM_SN_SN1_HUBXB_H */
+#endif /* _ASM_IA64_SN_SN1_HUBXB_H */
diff -Nru a/include/asm-ia64/sn/sn1/hubxb_next.h b/include/asm-ia64/sn/sn1/hubxb_next.h
--- a/include/asm-ia64/sn/sn1/hubxb_next.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/sn1/hubxb_next.h	Fri Mar 15 17:51:02 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SN1_HUBXB_NEXT_H
-#define _ASM_SN_SN1_HUBXB_NEXT_H
+#ifndef _ASM_IA64_SN_SN1_HUBXB_NEXT_H
+#define _ASM_IA64_SN_SN1_HUBXB_NEXT_H
 
 /* XB_FIRST_ERROR fe_source field encoding */
 #define XVE_SOURCE_POQ0 0xf	/* 1111 */
@@ -30,4 +29,4 @@
 #define XBP_RESET_DEFAULTS	0x0008000080000021LL
 #define XBP_ACTIVE_DEFAULTS	0x00080000fffff021LL
 
-#endif	/* _ASM_SN_SN1_HUBXB_NEXT_H */
+#endif /* _ASM_IA64_SN_SN1_HUBXB_NEXT_H */
diff -Nru a/include/asm-ia64/sn/sn1/hwcntrs.h b/include/asm-ia64/sn/sn1/hwcntrs.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/hwcntrs.h	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,96 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_HWCNTRS_H
+#define _ASM_IA64_SN_SN1_HWCNTRS_H
+
+
+typedef  uint64_t refcnt_t;
+
+#define SN0_REFCNT_MAX_COUNTERS 64
+
+typedef struct sn0_refcnt_set {
+	refcnt_t    refcnt[SN0_REFCNT_MAX_COUNTERS];
+        uint64_t  flags;
+        uint64_t  reserved[4];
+} sn0_refcnt_set_t;
+
+typedef struct sn0_refcnt_buf {
+	sn0_refcnt_set_t   refcnt_set;
+	uint64_t         paddr;
+        uint64_t         page_size;
+        cnodeid_t          cnodeid;         /* cnodeid + pad[3] use 64 bits */
+        uint16_t           pad[3];
+        uint64_t         reserved[4];
+} sn0_refcnt_buf_t;
+
+typedef struct sn0_refcnt_args {
+	uint64_t          vaddr;
+	uint64_t          len;
+	sn0_refcnt_buf_t*   buf;
+        uint64_t          reserved[4];
+} sn0_refcnt_args_t;
+
+/*
+ * Info needed by the user level program
+ * to mmap the refcnt buffer
+ */
+
+#define RCB_INFO_GET  1
+#define RCB_SLOT_GET  2
+
+typedef struct rcb_info {
+        uint64_t  rcb_len;                  /* total refcnt buffer len in bytes */
+
+        int         rcb_sw_sets;              /* number of sw counter sets in buffer */
+        int         rcb_sw_counters_per_set;  /* sw counters per set -- num_compact_nodes */
+        int         rcb_sw_counter_size;      /* sizeof(refcnt_t) -- size of sw cntr */
+
+        int         rcb_base_pages;           /* number of base pages in node */
+        int         rcb_base_page_size;       /* sw base page size */        
+        uint64_t  rcb_base_paddr;           /* base physical address for this node */
+
+        int         rcb_cnodeid;              /* cnodeid for this node */
+        int         rcb_granularity;          /* hw page size used for counter sets */
+        uint        rcb_hw_counter_max;       /* max hwcounter count (width mask) */
+        int         rcb_diff_threshold;       /* current node differential threshold */
+        int         rcb_abs_threshold;        /* current node absolute threshold */
+        int         rcb_num_slots;            /* physmem slots */
+        
+        int         rcb_reserved[512];
+        
+} rcb_info_t;
+
+typedef struct rcb_slot {
+        uint64_t  base;
+        uint64_t  size;
+} rcb_slot_t;
+
+#if defined(__KERNEL__)
+typedef struct sn0_refcnt_args_32 {
+	uint64_t    vaddr;
+	uint64_t    len;
+	app32_ptr_t   buf;
+        uint64_t    reserved[4];
+} sn0_refcnt_args_32_t;
+
+/* Defines and Macros  */
+/* A set of reference counts are for 4k bytes of physical memory */
+#define	NBPREFCNTP	0x1000	
+#define	BPREFCNTPSHIFT	12
+#define bytes_to_refcntpages(x)	(((__psunsigned_t)(x)+(NBPREFCNTP-1))>>BPREFCNTPSHIFT)
+#define refcntpage_offset(x)	((__psunsigned_t)(x)&((NBPP-1)&~(NBPREFCNTP-1)))
+#define align_to_refcntpage(x)	((__psunsigned_t)(x)&(~(NBPREFCNTP-1)))
+
+extern void migr_refcnt_read(sn0_refcnt_buf_t*);
+extern void migr_refcnt_read_extended(sn0_refcnt_buf_t*);
+extern int migr_refcnt_enabled(void);
+
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_IA64_SN_SN1_HWCNTRS_H */
diff -Nru a/include/asm-ia64/sn/sn1/intr.h b/include/asm-ia64/sn/sn1/intr.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/intr.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,237 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_INTR_H
+#define _ASM_IA64_SN_SN1_INTR_H
+
+/* Subnode wildcard */
+#define SUBNODE_ANY		(-1)
+
+/* Number of interrupt levels associated with each interrupt register. */
+#define N_INTPEND_BITS		64
+
+#define INT_PEND0_BASELVL	0
+#define INT_PEND1_BASELVL	64
+
+#define	N_INTPENDJUNK_BITS	8
+#define	INTPENDJUNK_CLRBIT	0x80
+
+#include <asm/sn/intr_public.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/xtalk/xtalk.h>
+#include <asm/sn/hack.h>
+
+#ifndef __ASSEMBLY__
+#define II_NAMELEN	24
+
+/*
+ * Dispatch table entry - contains information needed to call an interrupt
+ * routine.
+ */
+typedef struct intr_vector_s {
+	intr_func_t	iv_func;	/* Interrupt handler function */
+	intr_func_t	iv_prefunc;	/* Interrupt handler prologue func */
+	void		*iv_arg;	/* Argument to pass to handler */
+	cpuid_t			iv_mustruncpu;	/* Where we must run. */
+} intr_vector_t;
+
+/* Interrupt information table. */
+typedef struct intr_info_s {
+	xtalk_intr_setfunc_t	ii_setfunc;	/* Function to set the interrupt
+						 * destination and level register.
+						 * It returns 0 (success) or an
+						 * error code.
+						 */
+	void			*ii_cookie;	/* arg passed to setfunc */
+	devfs_handle_t		ii_owner_dev;	/* device that owns this intr */
+	char			ii_name[II_NAMELEN];	/* Name of this intr. */
+	int			ii_flags;	/* informational flags */
+} intr_info_t;
+
+
+#define THD_CREATED	0x00000001	/*
+					 * We've created a thread for this
+					 * interrupt.
+					 */
+
+/*
+ * Bits for ii_flags:
+ */
+#define II_UNRESERVE	0
+#define II_RESERVE	1		/* Interrupt reserved. 			*/
+#define II_INUSE	2		/* Interrupt connected 			*/
+#define II_ERRORINT	4		/* INterrupt is an error condition 	*/
+#define II_THREADED	8		/* Interrupt handler is threaded.	*/
+
+/*
+ * Interrupt level wildcard
+ */
+#define INTRCONNECT_ANYBIT	(-1)
+
+/*
+ * This structure holds information needed both to call and to maintain
+ * interrupts.  The two are in separate arrays for the locality benefits.
+ * Since there's only one set of vectors per hub chip (but more than one
+ * CPU, the lock to change the vector tables must be here rather than in
+ * the PDA.
+ */
+
+typedef struct intr_vecblk_s {
+	intr_vector_t	vectors[N_INTPEND_BITS];  /* information needed to
+						     call an intr routine. */
+	intr_info_t	info[N_INTPEND_BITS];	  /* information needed only
+						     to maintain interrupts. */
+	spinlock_t	vector_lock;		  /* Lock for this and the
+						     masks in the PDA. */
+	splfunc_t	vector_spl;		  /* vector_lock req'd spl */
+	int		vector_state;		  /* Initialized to zero.
+						     Set to INTR_INITED
+						     by hubintr_init.
+						   */
+	int		vector_count;		  /* Number of vectors
+						   * reserved.
+						   */
+	int		cpu_count[CPUS_PER_SUBNODE]; /* How many interrupts are
+						   * connected to each CPU
+						   */
+	int		ithreads_enabled;	  /* Are interrupt threads
+						   * initialized on this node.
+						   * and block?
+						   */
+} intr_vecblk_t;
+
+/* Possible values for vector_state: */
+#define VECTOR_UNINITED	0
+#define VECTOR_INITED	1
+#define VECTOR_SET	2
+
+#define hub_intrvect0	private.p_intmasks.dispatch0->vectors
+#define hub_intrvect1	private.p_intmasks.dispatch1->vectors
+#define hub_intrinfo0	private.p_intmasks.dispatch0->info
+#define hub_intrinfo1	private.p_intmasks.dispatch1->info
+
+/*
+ * Macros to manipulate the interrupt register on the calling hub chip.
+ */
+
+#define LOCAL_HUB_SEND_INTR(_level)	LOCAL_HUB_S(PI_INT_PEND_MOD, \
+						    (0x100|(_level)))
+#define REMOTE_HUB_PI_SEND_INTR(_hub, _sn, _level) \
+		REMOTE_HUB_PI_S((_hub), _sn, PI_INT_PEND_MOD, (0x100|(_level)))
+
+#define REMOTE_CPU_SEND_INTR(_cpuid, _level) 					\
+		REMOTE_HUB_PI_S(cpuid_to_nasid(_cpuid),				\
+			SUBNODE(cpuid_to_slice(_cpuid)),				\
+			PI_INT_PEND_MOD, (0x100|(_level)))
+
+/*
+ * When clearing the interrupt, make sure this clear does make it 
+ * to the hub. Otherwise we could end up losing interrupts.
+ * We do an uncached load of the int_pend0 register to ensure this.
+ */
+
+#define LOCAL_HUB_CLR_INTR(_level)	  \
+                LOCAL_HUB_S(PI_INT_PEND_MOD, (_level)),	\
+                LOCAL_HUB_L(PI_INT_PEND0)
+#define REMOTE_HUB_PI_CLR_INTR(_hub, _sn, _level) \
+		REMOTE_HUB_PI_S((_hub), (_sn), PI_INT_PEND_MOD, (_level)),	\
+                REMOTE_HUB_PI_L((_hub), (_sn), PI_INT_PEND0)
+
+/* Special support for use by gfx driver only.  Supports special gfx hub interrupt. */
+extern void install_gfxintr(cpuid_t cpu, ilvl_t swlevel, intr_func_t intr_func, void *intr_arg);
+
+void setrtvector(intr_func_t func);
+
+/*
+ * Interrupt blocking
+ */
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Hard-coded interrupt levels:
+ */
+
+/*
+ *	L0 = SW1
+ *	L1 = SW2
+ *	L2 = INT_PEND0
+ *	L3 = INT_PEND1
+ *	L4 = RTC
+ *	L5 = Profiling Timer
+ *	L6 = Hub Errors
+ *	L7 = Count/Compare (T5 counters)
+ */
+
+
+/* INT_PEND0 hard-coded bits. */
+#ifdef DEBUG_INTR_TSTAMP
+/* hard coded interrupt level for interrupt latency test interrupt */
+#define	CPU_INTRLAT_B	62
+#define	CPU_INTRLAT_A	61
+#endif
+
+/* Hardcoded bits required by software. */
+#define MSC_MESG_INTR	9
+#define CPU_ACTION_B	8
+#define CPU_ACTION_A	7
+
+/* These are determined by hardware: */
+#define CC_PEND_B	6
+#define CC_PEND_A	5
+#define UART_INTR	4
+#define PG_MIG_INTR	3
+#define GFX_INTR_B	2
+#define GFX_INTR_A	1
+#define RESERVED_INTR	0
+
+/* INT_PEND1 hard-coded bits: */
+#define MSC_PANIC_INTR	63
+#define NI_ERROR_INTR	62
+#define MD_COR_ERR_INTR	61
+#define COR_ERR_INTR_B	60
+#define COR_ERR_INTR_A	59
+#define CLK_ERR_INTR	58
+
+# define NACK_INT_B	57
+# define NACK_INT_A	56
+# define LB_ERROR	55
+# define XB_ERROR	54
+
+#define BRIDGE_ERROR_INTR 53	/* Setup by PROM to catch Bridge Errors */
+
+#define IP27_INTR_0	52	/* Reserved for PROM use */
+#define IP27_INTR_1	51	/*   (do not use in Kernel) */
+#define IP27_INTR_2	50
+#define IP27_INTR_3	49
+#define IP27_INTR_4	48
+#define IP27_INTR_5	47
+#define IP27_INTR_6	46
+#define IP27_INTR_7	45
+
+#define	TLB_INTR_B	44	/* used for tlb flush random */
+#define	TLB_INTR_A	43
+
+#define LLP_PFAIL_INTR_B 42	/* see ml/SN/SN0/sysctlr.c */
+#define LLP_PFAIL_INTR_A 41
+
+#define NI_BRDCAST_ERR_B 40
+#define NI_BRDCAST_ERR_A 39
+
+# define IO_ERROR_INTR	38	/* set up by prom */
+# define DEBUG_INTR_B	37	/* used by symmon to stop all cpus */
+# define DEBUG_INTR_A	36
+
+// These aren't strictly accurate or complete.  See the
+// Synergy Spec. for details.
+#define SGI_UART_IRQ	(65)
+#define SGI_HUB_ERROR_IRQ	(182)
+
+#endif /* _ASM_IA64_SN_SN1_INTR_H */
diff -Nru a/include/asm-ia64/sn/sn1/intr_public.h b/include/asm-ia64/sn/sn1/intr_public.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/intr_public.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,53 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_INTR_PUBLIC_H
+#define _ASM_IA64_SN_SN1_INTR_PUBLIC_H
+
+/* REMEMBER: If you change these, the whole world needs to be recompiled.
+ * It would also require changing the hubspl.s code and SN0/intr.c
+ * Currently, the spl code has no support for multiple INTPEND1 masks.
+ */
+
+#define	N_INTPEND0_MASKS	1
+#define	N_INTPEND1_MASKS	1
+
+#define INTPEND0_MAXMASK	(N_INTPEND0_MASKS - 1)
+#define INTPEND1_MAXMASK	(N_INTPEND1_MASKS - 1)
+
+#ifndef __ASSEMBLY__
+#include <asm/sn/arch.h>
+
+struct intr_vecblk_s;	/* defined in asm/sn/intr.h */
+
+/*
+ * The following are necessary to create the illusion of a CEL
+ * on the IP27 hub.  We'll add more priority levels soon, but for
+ * now, any interrupt in a particular band effectively does an spl.
+ * These must be in the PDA since they're different for each processor.
+ * Users of this structure must hold the vector_lock in the appropriate vector
+ * block before modifying the mask arrays.  There's only one vector block
+ * for each Hub so a lock in the PDA wouldn't be adequate.
+ */
+typedef struct hub_intmasks_s {
+	/*
+	 * The masks are stored with the lowest-priority (most inclusive)
+	 * in the lowest-numbered masks (i.e., 0, 1, 2...).
+	 */
+	/* INT_PEND0: */
+	hubreg_t		intpend0_masks[N_INTPEND0_MASKS]; 
+	/* INT_PEND1: */
+	hubreg_t		intpend1_masks[N_INTPEND1_MASKS];
+	/* INT_PEND0: */
+	struct intr_vecblk_s	*dispatch0;	
+	/* INT_PEND1: */
+	struct intr_vecblk_s	*dispatch1;
+} hub_intmasks_t;
+
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_IA64_SN_SN1_INTR_PUBLIC_H */
diff -Nru a/include/asm-ia64/sn/sn1/ip27config.h b/include/asm-ia64/sn/sn1/ip27config.h
--- a/include/asm-ia64/sn/sn1/ip27config.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/ip27config.h	Fri Mar 15 17:51:03 2002
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_IP27CONFIG_H
-#define _ASM_SN_SN1_IP27CONFIG_H
+#ifndef _ASM_IA64_SN_SN1_IP27CONFIG_H
+#define _ASM_IA64_SN_SN1_IP27CONFIG_H
 
 
 /*
@@ -50,7 +49,7 @@
  */
 #define IP27_RTC_FREQ			1250	/* 800ns cycle time */
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 typedef	struct ip27config_s {		/* KEEP IN SYNC w/ start.s & below  */
     uint		time_const;	/* Time constant 		    */
@@ -110,9 +109,9 @@
  */
 #define CONFIG_12P4I_NODE(n)	(0)
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#if _LANGUAGE_ASSEMBLY
+#if __ASSEMBLY__
 	.struct		0		/* KEEP IN SYNC WITH C structure */
 
 ip27c_time_const:	.word	0
@@ -137,7 +136,7 @@
 ip27c_pvers_rev:	.word	0
 
 ip27c_config_type:	.word 	0	/* To recognize special configs */
-#endif /* _LANGUAGE_ASSEMBLY */
+#endif /* __ASSEMBLY__ */
 
 /*
  * R10000 Configuration Cycle - These define the SYSAD values used
@@ -245,7 +244,7 @@
 
 #define CONFIG_FREQ_RTC	IP27C_KHZ(IP27_RTC_FREQ)
 
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 
 /* we are going to define all the known configs is a table
  * for building hex images we will pull out the particular
@@ -258,7 +257,7 @@
  */
 
 /* these numbers are as the are ordered in the table below */
-#define	IP27_CONFIG_UNKNOWN -1
+#define	IP27_CONFIG_UNKNOWN (-1)
 #define IP27_CONFIG_SN1_1MB_200_400_200_TABLE 0
 #define IP27_CONFIG_SN00_4MB_100_200_133_TABLE 1
 #define IP27_CONFIG_SN1_4MB_200_400_267_TABLE 2
@@ -500,9 +499,9 @@
 #define CONFIG_FPROM_WR	ip_config_table[IP27_CONFIG_SN1_4MB_180_360_240_TABLE].fprom_wr
 #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#if _LANGUAGE_ASSEMBLY
+#if __ASSEMBLY__
 
 /* these need to be in here since we need assembly definitions
  * for building hex images (as required by start.s)
@@ -653,6 +652,6 @@
 #define CONFIG_FPROM_WR CONFIG_FPROM_ENABLE
 #endif /* IP27_CONFIG_SN1_4MB_180_360_240 */
 
-#endif /* _LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_SN1_IP27CONFIG_H */
+#endif /* _ASM_IA64_SN_SN1_IP27CONFIG_H */
diff -Nru a/include/asm-ia64/sn/sn1/kldir.h b/include/asm-ia64/sn/sn1/kldir.h
--- a/include/asm-ia64/sn/sn1/kldir.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,222 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef _ASM_SN_SN1_KLDIR_H
-#define _ASM_SN_SN1_KLDIR_H
-
-/*
- * The upper portion of the memory map applies during boot
- * only and is overwritten by IRIX/SYMMON.  The minimum memory bank
- * size on IP35 is 64M, which provides a limit on the amount of space
- * the PROM can assume it has available.
- *
- * Most of the addresses below are defined as macros in this file, or
- * in SN/addrs.h or SN/SN1/addrs.h.
- *
- *                                    MEMORY MAP PER NODE
- *
- * 0x4000000 (64M)         +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      IO7 TEXT/DATA/BSS/stack            |
- * 0x3000000 (48M)         +-----------------------------------------+
- *                         |      Free                               |
- * 0x2102000 (>33M)        +-----------------------------------------+
- *                         |      IP35 Topology (PCFG) + misc data   |
- * 0x2000000 (32M)         +-----------------------------------------+
- *                         |      IO7 BUFFERS FOR FLASH ENET IOC3    |
- * 0x1F80000 (31.5M)       +-----------------------------------------+
- *                         |      Free                               |
- * 0x1C00000 (28M)         +-----------------------------------------+
- *                         |      IP35 PROM TEXT/DATA/BSS/stack      |
- * 0x1A00000 (26M)         +-----------------------------------------+
- *                         |      Routing temp. space                |
- * 0x1800000 (24M)         +-----------------------------------------+
- *                         |      Diagnostics temp. space            |
- * 0x1500000 (21M)         +-----------------------------------------+
- *                         |      Free                               |
- * 0x1400000 (20M)         +-----------------------------------------+
- *                         |      IO7 PROM temporary copy            |
- * 0x1300000 (19M)         +-----------------------------------------+
- *                         |                                         |
- *                         |      Free                               |
- *                         |      (UNIX DATA starts above 0x1000000) |
- *                         |                                         |
- *                         +-----------------------------------------+
- *                         |      UNIX DEBUG Version                 |
- * 0x0310000 (3.1M)        +-----------------------------------------+
- *                         |      SYMMON, loaded just below UNIX     |
- *                         |      (For UNIX Debug only)              |
- *                         |                                         |
- *                         |                                         |
- * 0x006C000 (432K)        +-----------------------------------------+
- *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
- *                         |      (For UNIX Debug only)              |
- * 0x004C000 (304K)        +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      UNIX NON-DEBUG Version             |
- * 0x0040000 (256K)        +-----------------------------------------+
- *
- *
- * The lower portion of the memory map contains information that is
- * permanent and is used by the IP35PROM, IO7PROM and IRIX.
- *
- * 0x40000 (256K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      KLCONFIG (64K)                     |
- *                         |                                         |
- * 0x30000 (192K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      PI Error Spools (64K)              |
- *                         |                                         |
- * 0x20000 (128K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- * 0x19000 (100K)          +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 3)|
- * 0x18800 (98K)           +-----------------------------------------+
- *			   |      cache error eframe (CPU 3)	     |
- * 0x18400 (97K)           +-----------------------------------------+
- *                         |      Exception Handlers (CPU 3)         |
- * 0x18000 (96K)           +-----------------------------------------+
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- * 0x13c00 (79K)           +-----------------------------------------+
- *                         |      GPDA (8k)                          |
- * 0x11c00 (71K)           +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 2)|
- * 0x10800 (66k)	   +-----------------------------------------+
- *			   |      cache error eframe (CPU 2)	     |
- * 0x10400 (65K)           +-----------------------------------------+
- *                         |      Exception Handlers (CPU 2)         |
- * 0x10000 (64K)           +-----------------------------------------+
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- * 0x0b400 (45K)           +-----------------------------------------+
- *                         |      GDA (1k)                           |
- * 0x0b000 (44K)           +-----------------------------------------+
- *                         |      NMI Eframe areas (4)       	     |
- * 0x0a000 (40K)           +-----------------------------------------+
- *                         |      NMI Register save areas (4)        |
- * 0x09000 (36K)           +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 1)|
- * 0x08800 (34K)           +-----------------------------------------+
- *			   |      cache error eframe (CPU 1)	     |
- * 0x08400 (33K)           +-----------------------------------------+
- *                         |      Exception Handlers (CPU 1)         |
- * 0x08000 (32K)           +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      Unused                             |
- *                         |                                         |
- *                         |                                         |
- * 0x04000 (16K)           +-----------------------------------------+
- *                         |      NMI Handler (Protected Page)       |
- * 0x03000 (12K)           +-----------------------------------------+
- *                         |      ARCS PVECTORS (master node only)   |
- * 0x02c00 (11K)           +-----------------------------------------+
- *                         |      ARCS TVECTORS (master node only)   |
- * 0x02800 (10K)           +-----------------------------------------+
- *                         |      LAUNCH [NUM_CPU]                   |
- * 0x02400 (9K)            +-----------------------------------------+
- *                         |      Low memory directory (KLDIR)       |
- * 0x02000 (8K)            +-----------------------------------------+
- *                         |      ARCS SPB (1K)                      |
- * 0x01000 (4K)            +-----------------------------------------+
- *                         |      Early cache Exception stack (CPU 0)|
- * 0x00800 (2k)	           +-----------------------------------------+
- *			   |      cache error eframe (CPU 0)	     |
- * 0x00400 (1K)            +-----------------------------------------+
- *                         |      Exception Handlers (CPU 0)         |
- * 0x00000 (0K)            +-----------------------------------------+
- */
-
-/*
- * NOTE:  To change the kernel load address, you must update:
- *  - the appropriate elspec files in irix/kern/master.d
- *  - NODEBUGUNIX_ADDR in SN/SN1/addrs.h
- *  - IP27_FREEMEM_OFFSET below
- *  - KERNEL_START_OFFSET below (if supporting cells)
- */
-
-
-/*
- * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
- * we define here.  Since it's set up in the prom.  We can't redefine it later
- * and expect more space to be allocated.  The way to find out the true size
- * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
- * for a particular node.
- */
-#define SYMMON_STACK_SIZE		0x8000
-
-#if defined (PROM) || defined (SABLE)
-
-/*
- * These defines are prom version dependent.  No code other than the IP35
- * prom should attempt to use these values.
- */
-#define IP27_LAUNCH_OFFSET		0x2400
-#define IP27_LAUNCH_SIZE		0x400
-#define IP27_LAUNCH_COUNT		4
-#define IP27_LAUNCH_STRIDE		0x100 /* could be as small as 0x80 */
-
-#define IP27_KLCONFIG_OFFSET		0x30000
-#define IP27_KLCONFIG_SIZE		0x10000
-#define IP27_KLCONFIG_COUNT		1
-#define IP27_KLCONFIG_STRIDE		0
-
-#define IP27_NMI_OFFSET			0x3000
-#define IP27_NMI_SIZE			0x100
-#define IP27_NMI_COUNT			4
-#define IP27_NMI_STRIDE			0x40
-
-#define IP27_PI_ERROR_OFFSET		0x20000
-#define IP27_PI_ERROR_SIZE		0x10000
-#define IP27_PI_ERROR_COUNT		1
-#define IP27_PI_ERROR_STRIDE		0
-
-#define IP27_SYMMON_STK_OFFSET		0x4c000
-#define IP27_SYMMON_STK_SIZE		0x20000
-#define IP27_SYMMON_STK_COUNT		4
-/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
-#define IP27_SYMMON_STK_STRIDE		0x8000
-
-#define IP27_FREEMEM_OFFSET		0x40000
-#define IP27_FREEMEM_SIZE		-1
-#define IP27_FREEMEM_COUNT		1
-#define IP27_FREEMEM_STRIDE		0
-
-#endif /* PROM || SABLE*/
-/*
- * There will be only one of these in a partition so the IO7 must set it up.
- */
-#define IO6_GDA_OFFSET			0xb000
-#define IO6_GDA_SIZE			0x400
-#define IO6_GDA_COUNT			1
-#define IO6_GDA_STRIDE			0
-
-/*
- * save area of kernel nmi regs in the prom format
- */
-#define IP27_NMI_KREGS_OFFSET		0x9000
-#define IP27_NMI_KREGS_CPU_SIZE		0x400
-/*
- * save area of kernel nmi regs in eframe format 
- */
-#define IP27_NMI_EFRAME_OFFSET		0xa000
-#define IP27_NMI_EFRAME_SIZE		0x400
-
-#define GPDA_OFFSET			0x11c00
-
-#endif /* _ASM_SN_SN1_KLDIR_H */
diff -Nru a/include/asm-ia64/sn/sn1/leds.h b/include/asm-ia64/sn/sn1/leds.h
--- a/include/asm-ia64/sn/sn1/leds.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,35 +0,0 @@
-#ifndef _ASM_SN_SN1_LED_H
-#define _ASM_SN_SN1_LED_H
-
-/*
- * Copyright (C) 2000 Silicon Graphics, Inc
- * Copyright (C) 2000 Jack Steiner (steiner@sgi.com)
- */
-
-#include <asm/smp.h>
-
-#define LED0		0xc0000b00100000c0LL	/* ZZZ fixme */
-
-
-
-#define LED_AP_START	0x01		/* AP processor started */
-#define LED_AP_IDLE	0x01
-
-/*
- * Basic macros for flashing the LEDS on an SGI, SN1.
- */
-
-extern __inline__ void
-HUB_SET_LED(int val)
-{
-	long	*ledp;
-	int	eid;
-
-	eid = hard_smp_processor_id() & 3;
-	ledp = (long*) (LED0 + (eid<<3));
-	*ledp = val;
-}
-
-
-#endif /* _ASM_SN_SN1_LED_H */
-
diff -Nru a/include/asm-ia64/sn/sn1/mem_refcnt.h b/include/asm-ia64/sn/sn1/mem_refcnt.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/mem_refcnt.h	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,25 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_MEM_REFCNT_H
+#define _ASM_IA64_SN_SN1_MEM_REFCNT_H
+
+extern int mem_refcnt_attach(devfs_handle_t hub);
+extern int mem_refcnt_open(devfs_handle_t *devp, mode_t oflag, int otyp, cred_t *crp);
+extern int mem_refcnt_close(devfs_handle_t dev, int oflag, int otyp, cred_t *crp);
+extern int mem_refcnt_mmap(devfs_handle_t dev, vhandl_t *vt, off_t off, size_t len, uint prot);
+extern int mem_refcnt_unmap(devfs_handle_t dev, vhandl_t *vt);
+extern int mem_refcnt_ioctl(devfs_handle_t dev,
+                 int cmd,
+                 void *arg,
+                 int mode,
+                 cred_t *cred_p,
+                 int *rvalp);
+        
+
+#endif /* _ASM_IA64_SN_SN1_MEM_REFCNT_H */
diff -Nru a/include/asm-ia64/sn/sn1/mmzone_sn1.h b/include/asm-ia64/sn/sn1/mmzone_sn1.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/mmzone_sn1.h	Fri Mar 15 17:51:03 2002
@@ -0,0 +1,149 @@
+#ifndef _ASM_IA64_SN_MMZONE_SN1_H
+#define _ASM_IA64_SN_MMZONE_SN1_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+
+
+/*
+ * SGI SN1 Arch defined values
+ *
+ * 	An SN1 physical address is broken down as follows:
+ *
+ *             +-----------------------------------------+
+ *             |         |    |      |   node offset     |
+ *             | unused  | AS | node |-------------------|
+ *             |         |    |      | cn | clump offset |
+ *             +-----------------------------------------+
+ *              6       4 4  4 3    3 3  3 2            0
+ *              3       4 3  0 9    3 2  0 9            0
+ *
+ *		bits 63-44	Unused - must be zero
+ *		bits 43-40	Address space ID. Cached memory has a value of 0.
+ *				Chipset & IO addresses have non-zero values.
+ *		bits 39-33	Node number. Note that some configurations do NOT
+ *				have a node zero.
+ *		bits 32-0	Node offset.
+ *
+ *	The node offset can be further broken down as:
+ *		bits 32-30	Clump (bank) number.
+ *		bits 29-0	Clump (bank) offset.
+ *
+ *	A node consists of up to 8 clumps (banks) of memory. A clump may be empty, or may be
+ *	populated with a single contiguous block of memory starting at clump
+ *	offset 0. The size of the block is (2**n) * 64MB, where 0<n<5.
+ *
+ *
+ * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with
+ *	 "SN_" are intended for internal use only and should not be used in
+ *	 any platform independent code. 
+ *
+ *	 This file is also responsible for exporting the following definitions:
+ *		cnodeid_t	Define a compact node id. 
+ */
+
+typedef signed short cnodeid_t;
+
+#define SN1_BANKS_PER_NODE		8
+#define SN1_NODE_SIZE			(8UL*1024*1024*1024)	/* 8 GB per node */
+#define SN1_BANK_SIZE			(SN1_NODE_SIZE/SN1_BANKS_PER_NODE)
+#define SN1_NODE_SHIFT			33
+#define SN1_NODE_MASK			0x7fUL
+#define SN1_NODE_OFFSET_MASK		(SN1_NODE_SIZE-1)
+#define SN1_NODE_NUMBER(addr)		(((unsigned long)(addr) >> SN1_NODE_SHIFT) & SN1_NODE_MASK)
+#define SN1_NODE_CLUMP_NUMBER(addr)	(((unsigned long)(addr) >>30) & 7)
+#define SN1_NODE_OFFSET(addr)		(((unsigned long)(addr)) & SN1_NODE_OFFSET_MASK)
+#define SN1_KADDR(nasid, offset)	(((unsigned long)(nasid)<<SN1_NODE_SHIFT) | (offset) | PAGE_OFFSET)
+
+
+#define PLAT_MAX_NODE_NUMBER		128			/* Maximum node number +1 */
+#define PLAT_MAX_COMPACT_NODES		128			/* Maximum number of nodes in SSI */
+
+#define PLAT_MAX_PHYS_MEMORY		(1UL << 40)
+
+
+
+/*
+ * On the SN platforms, a clump is the same as a memory bank.
+ */
+#define PLAT_CLUMPS_PER_NODE		SN1_BANKS_PER_NODE
+#define PLAT_CLUMP_OFFSET(addr)		((unsigned long)(addr) & 0x3fffffffUL)
+#define PLAT_CLUMPSIZE                  (SN1_NODE_SIZE/PLAT_CLUMPS_PER_NODE)
+#define PLAT_MAXCLUMPS			(PLAT_CLUMPS_PER_NODE*PLAT_MAX_COMPACT_NODES)
+
+
+
+
+/*
+ * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a
+ * valid cacheable identity mapped RAM memory address.
+ * Note that the RAM may or may not actually be present!!
+ */
+#define SN1_VALID_KERN_ADDR_MASK	0xffffff0000000000UL
+#define SN1_VALID_KERN_ADDR_VALUE	0xe000000000000000UL
+#define PLAT_VALID_MEM_KADDR(kaddr)	(((unsigned long)(kaddr) & SN1_VALID_KERN_ADDR_MASK) == SN1_VALID_KERN_ADDR_VALUE)
+
+
+
+/*
+ * Memory is conceptually divided into chunks. A chunk is either
+ * completely present, or else the kernel assumes it is completely
+ * absent. Each node consists of a number of possibly discontiguous chunks.
+ */
+#define SN1_CHUNKSHIFT			26			/* 64 MB */
+#define SN1_CHUNKSIZE			(1UL << SN1_CHUNKSHIFT)
+#define PLAT_CHUNKNUM(addr)		(((addr) & (PLAT_MAX_PHYS_MEMORY-1)) >> SN1_CHUNKSHIFT)
+
+
+/*
+ * Given a kaddr, find the nid (compact nodeid)
+ */
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+#define DISCONBUG(kaddr)		panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx",	 	\
+						__LINE__, __FILE__, (long)(kaddr))
+
+#define KVADDR_TO_NID(kaddr)		({long _ktn=(long)(kaddr);					\
+						kern_addr_valid(_ktn) ? 				\
+						local_node_data->physical_node_map[SN1_NODE_NUMBER(_ktn)] :\
+						(DISCONBUG(_ktn), 0UL);})
+#else
+#define KVADDR_TO_NID(kaddr)		(local_node_data->physical_node_map[SN1_NODE_NUMBER(kaddr)])
+#endif
+
+
+
+/*
+ * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry
+ * for the first page of the clump.
+ */
+#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr)		({long _kmmi=(long)(kaddr);				\
+							KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE +	\
+							SN1_NODE_CLUMP_NUMBER(_kmmi);})
+
+
+/*
+ * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on
+ * nodes so that they dont alias to the same line in the cache as the previous allocated structure.
+ * This macro takes an address of the end of previous allocation, rounds it to a page boundary & 
+ * changes the node number.
+ */
+#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr)	SN1_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]),	\
+						  (SN1_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)
+
+
+
+
+/*
+ * Convert a proximity domain number (from the ACPI tables) into a physical node number.
+ */
+
+#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm)	(pxm)
+
+#endif /* _ASM_IA64_SN_MMZONE_SN1_H */
diff -Nru a/include/asm-ia64/sn/sn1/promlog.h b/include/asm-ia64/sn/sn1/promlog.h
--- a/include/asm-ia64/sn/sn1/promlog.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,85 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef	_ASM_SN_SN1_PROMLOG_H
-#define	_ASM_SN_SN1_PROMLOG_H
-
-#include <asm/sn/fprom.h>
-
-#define PROMLOG_MAGIC			0x504c4f49
-#define PROMLOG_VERSION			1
-
-#define PROMLOG_OFFSET_MAGIC		0x10
-#define PROMLOG_OFFSET_VERSION		0x14
-#define PROMLOG_OFFSET_SEQUENCE		0x18
-#define PROMLOG_OFFSET_ENTRY0		0x100
-
-#define PROMLOG_ERROR_NONE		0
-#define PROMLOG_ERROR_PROM	       -1
-#define PROMLOG_ERROR_MAGIC	       -2
-#define PROMLOG_ERROR_CORRUPT	       -3
-#define PROMLOG_ERROR_BOL	       -4
-#define PROMLOG_ERROR_EOL	       -5
-#define PROMLOG_ERROR_POS	       -6
-#define PROMLOG_ERROR_REPLACE	       -7
-#define PROMLOG_ERROR_COMPACT	       -8
-#define PROMLOG_ERROR_FULL	       -9
-#define PROMLOG_ERROR_ARG	       -10
-#define PROMLOG_ERROR_UNUSED	       -11	  	
-
-#define PROMLOG_TYPE_UNUSED		0xf
-#define PROMLOG_TYPE_LOG		3
-#define PROMLOG_TYPE_LIST		2
-#define PROMLOG_TYPE_VAR		1
-#define PROMLOG_TYPE_DELETED		0
-
-#define PROMLOG_TYPE_ANY		98
-#define PROMLOG_TYPE_INVALID		99
-
-#define PROMLOG_KEY_MAX			14
-#define PROMLOG_VALUE_MAX		47
-#define PROMLOG_CPU_MAX			4
-
-typedef struct promlog_header_s {
-    unsigned int	unused[4];
-    unsigned int	magic;
-    unsigned int	version;
-    unsigned int	sequence;
-} promlog_header_t;
-
-typedef unsigned int promlog_pos_t;
-
-typedef struct promlog_ent_s {		/* PROM individual entry */
-    uint		type		: 4;
-    uint		cpu_num		: 4;
-    char		key[PROMLOG_KEY_MAX + 1];
-
-    char		value[PROMLOG_VALUE_MAX + 1];
-
-} promlog_ent_t;
-
-typedef struct promlog_s {		/* Activation handle */
-    fprom_t		f;
-    int			sector_base;
-    int			cpu_num;
-
-    int			active;		/* Active sector, 0 or 1 */
-
-    promlog_pos_t	log_start;
-    promlog_pos_t	log_end;
-
-    promlog_pos_t	alt_start;
-    promlog_pos_t	alt_end;
-
-    promlog_pos_t	pos;
-    promlog_ent_t	ent;
-} promlog_t;
-
-#endif /* _ASM_SN_SN1_PROMLOG_H */
diff -Nru a/include/asm-ia64/sn/sn1/router.h b/include/asm-ia64/sn/sn1/router.h
--- a/include/asm-ia64/sn/sn1/router.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,670 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef	_ASM_SN_SN1_ROUTER_H
-#define	_ASM_SN_SN1_ROUTER_H
-
-/*
- * Router Register definitions
- *
- * Macro argument _L always stands for a link number (1 to 8, inclusive).
- */
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
-#include <asm/sn/vector.h>
-#include <asm/sn/slotnum.h>
-#include <asm/sn/arch.h>
-
-typedef uint64_t	router_reg_t;
-
-#define MAX_ROUTERS	64
-
-#define MAX_ROUTER_PATH	80
-
-#define ROUTER_REG_CAST		(volatile router_reg_t *)
-#define PS_UINT_CAST		(__psunsigned_t)
-#define UINT64_CAST		(uint64_t)
-typedef signed char port_no_t;	 /* Type for router port number      */
-
-#elif _LANGUAGE_ASSEMBLY
-
-#define ROUTERREG_CAST
-#define PS_UINT_CAST
-#define UINT64_CAST
-
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#define MAX_ROUTER_PORTS (8)	 /* Max. number of ports on a router */
-
-#define ALL_PORTS ((1 << MAX_ROUTER_PORTS) - 1)	/* for 0 based references */
-
-#define PORT_INVALID (-1)	 /* Invalid port number              */
-
-#define	IS_META(_rp)	((_rp)->flags & PCFG_ROUTER_META)
-
-#define	IS_REPEATER(_rp)((_rp)->flags & PCFG_ROUTER_REPEATER)
-
-/*
- * RR_TURN makes a given number of clockwise turns (0 to 7) from an inport
- * port to generate an output port.
- *
- * RR_DISTANCE returns the number of turns necessary (0 to 7) to go from
- * an input port (_L1 = 1 to 8) to an output port ( _L2 = 1 to 8).
- *
- * These are written to work on unsigned data.
- */
-
-#define RR_TURN(_L, count)	((_L) + (count) > MAX_ROUTER_PORTS ?	\
-				 (_L) + (count) - MAX_ROUTER_PORTS :	\
-				 (_L) + (count))
-
-#define RR_DISTANCE(_LS, _LD)	((_LD) >= (_LS) ?			\
-				 (_LD) - (_LS) :			\
-				 (_LD) + MAX_ROUTER_PORTS - (_LS))
-
-/* Router register addresses */
-
-#define RR_STATUS_REV_ID	0x00000	/* Status register and Revision ID  */
-#define RR_PORT_RESET		0x00008	/* Multiple port reset              */
-#define RR_PROT_CONF		0x00010	/* Inter-partition protection conf. */
-#define RR_GLOBAL_PORT_DEF	0x00018 /* Global Port definitions          */
-#define RR_GLOBAL_PARMS0	0x00020	/* Parameters shared by all 8 ports */
-#define RR_GLOBAL_PARMS1	0x00028	/* Parameters shared by all 8 ports */
-#define RR_DIAG_PARMS		0x00030	/* Parameters for diag. testing     */
-#define RR_DEBUG_ADDR		0x00038 /* Debug address select - debug port*/
-#define RR_LB_TO_L2		0x00040 /* Local Block to L2 cntrl intf reg */ 
-#define RR_L2_TO_LB		0x00048 /* L2 cntrl intf to Local Block reg */
-#define RR_JBUS_CONTROL		0x00050 /* read/write timing for JBUS intf  */
-
-#define RR_SCRATCH_REG0		0x00100	/* Scratch 0 is 64 bits */
-#define RR_SCRATCH_REG1		0x00108	/* Scratch 1 is 64 bits */
-#define RR_SCRATCH_REG2		0x00110	/* Scratch 2 is 64 bits */
-#define RR_SCRATCH_REG3		0x00118	/* Scratch 3 is 1 bit */
-#define RR_SCRATCH_REG4		0x00120	/* Scratch 4 is 1 bit */
-
-#define RR_JBUS0(_D)		(((_D) & 0x7) << 3 | 0x00200) /* JBUS0 addresses   */
-#define RR_JBUS1(_D)		(((_D) & 0x7) << 3 | 0x00240) /* JBUS1 addresses   */
-
-#define RR_SCRATCH_REG0_WZ	0x00500	/* Scratch 0 is 64 bits */
-#define RR_SCRATCH_REG1_WZ	0x00508	/* Scratch 1 is 64 bits */
-#define RR_SCRATCH_REG2_WZ	0x00510	/* Scratch 2 is 64 bits */
-#define RR_SCRATCH_REG3_SZ	0x00518	/* Scratch 3 is 1 bit */
-#define RR_SCRATCH_REG4_SZ	0x00520	/* Scratch 4 is 1 bit */
-
-#define RR_VECTOR_HW_BAR(context) (0x08000 | (context)<<3) /* barrier config registers */
-/* Port-specific registers (_L is the link number from 1 to 8) */
-
-#define RR_PORT_PARMS(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0000) /* LLP parameters     */
-#define RR_STATUS_ERROR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0008) /* Port-related errs  */
-#define RR_CHANNEL_TEST(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0010) /* Port LLP chan test */
-#define RR_RESET_MASK(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0018) /* Remote reset mask  */
-#define RR_HISTOGRAM0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0020) /* Port usage histgrm */
-#define RR_HISTOGRAM1(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0028) /* Port usage histgrm */
-#define RR_HISTOGRAM0_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0030) /* Port usage histgrm */
-#define RR_HISTOGRAM1_WC(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0038) /* Port usage histgrm */
-#define RR_ERROR_CLEAR(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0088) /* Read/clear errors  */
-#define RR_GLOBAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0100) /* starting address of global table for this port */
-#define RR_GLOBAL_TABLE(_L, _x) (RR_GLOBAL_TABLE0(_L) + ((_x) << 3))
-#define RR_LOCAL_TABLE0(_L)	(((_L+1) & 0xe) << 15 | ((_L+1) & 0x1) << 11 | 0x0200) /* starting address of local table for this port */
-#define RR_LOCAL_TABLE(_L, _x) (RR_LOCAL_TABLE0(_L) + ((_x) << 3))
-
-#define RR_META_ENTRIES		16
-
-#define RR_LOCAL_ENTRIES	128
-
-/*
- * RR_STATUS_REV_ID mask and shift definitions
- */
-
-#define RSRI_INPORT_SHFT	52
-#define RSRI_INPORT_MASK	(UINT64_CAST 0xf << 52)
-#define RSRI_LINKWORKING_BIT(_L) (35 + 2 * (_L))
-#define RSRI_LINKWORKING(_L)	(UINT64_CAST 1 << (35 + 2 * (_L)))
-#define RSRI_LINKRESETFAIL(_L)	(UINT64_CAST 1 << (34 + 2 * (_L)))
-#define RSRI_LSTAT_SHFT(_L)	(34 + 2 * (_L))
-#define RSRI_LSTAT_MASK(_L)	(UINT64_CAST 0x3 << 34 + 2 * (_L))
-#define RSRI_LOCALSBERROR	(UINT64_CAST 1 << 35)
-#define RSRI_LOCALSTUCK		(UINT64_CAST 1 << 34)
-#define RSRI_LOCALBADVEC	(UINT64_CAST 1 << 33)
-#define RSRI_LOCALTAILERR	(UINT64_CAST 1 << 32)
-#define RSRI_LOCAL_SHFT 	32
-#define RSRI_LOCAL_MASK		(UINT64_CAST 0xf << 32)
-#define RSRI_CHIPREV_SHFT	28
-#define RSRI_CHIPREV_MASK	(UINT64_CAST 0xf << 28)
-#define RSRI_CHIPID_SHFT	12
-#define RSRI_CHIPID_MASK	(UINT64_CAST 0xffff << 12)
-#define RSRI_MFGID_SHFT		1
-#define RSRI_MFGID_MASK		(UINT64_CAST 0x7ff << 1)
-
-#define RSRI_LSTAT_WENTDOWN	0
-#define RSRI_LSTAT_RESETFAIL	1
-#define RSRI_LSTAT_LINKUP	2
-#define RSRI_LSTAT_NOTUSED	3
-
-/*
- * RR_PORT_RESET mask definitions
- */
-
-#define RPRESET_WARM		(UINT64_CAST 1 << 9)
-#define RPRESET_LINK(_L)	(UINT64_CAST 1 << (_L))
-#define RPRESET_LOCAL		(UINT64_CAST 1)
-
-/*
- * RR_PROT_CONF mask and shift definitions
- */
-
-#define RPCONF_DIRCMPDIS_SHFT	13
-#define RPCONF_DIRCMPDIS_MASK	(UINT64_CAST 1 << 13)
-#define RPCONF_FORCELOCAL	(UINT64_CAST 1 << 12)
-#define RPCONF_FLOCAL_SHFT	12
-#define RPCONF_METAID_SHFT	8
-#define RPCONF_METAID_MASK	(UINT64_CAST 0xf << 8)
-#define RPCONF_RESETOK(_L)	(UINT64_CAST 1 << ((_L) - 1))
-
-/*
- * RR_GLOBAL_PORT_DEF mask and shift definitions
- */
-
-#define RGPD_MGLBLNHBR_ID_SHFT	12	/* -global neighbor ID */
-#define RGPD_MGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 12)
-#define RGPD_MGLBLNHBR_VLD_SHFT	11	/* -global neighbor Valid */
-#define RGPD_MGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 11)
-#define RGPD_MGLBLPORT_SHFT	8	/* -global neighbor Port */
-#define RGPD_MGLBLPORT_MASK	(UINT64_CAST 0x7 << 8)
-#define RGPD_PGLBLNHBR_ID_SHFT	4	/* +global neighbor ID */
-#define RGPD_PGLBLNHBR_ID_MASK	(UINT64_CAST 0xf << 4)
-#define RGPD_PGLBLNHBR_VLD_SHFT	3	/* +global neighbor Valid */
-#define RGPD_PGLBLNHBR_VLD_MASK	(UINT64_CAST 0x1 << 3)
-#define RGPD_PGLBLPORT_SHFT	0	/* +global neighbor Port */
-#define RGPD_PGLBLPORT_MASK	(UINT64_CAST 0x7 << 0)
-
-#define GLBL_PARMS_REGS		2	/* Two Global Parms registers */
-
-/*
- * RR_GLOBAL_PARMS0 mask and shift definitions
- */
-
-#define RGPARM0_ARB_VALUE_SHFT	54	/* Local Block Arbitration State */
-#define RGPARM0_ARB_VALUE_MASK	(UINT64_CAST 0x7 << 54)
-#define RGPARM0_ROTATEARB_SHFT	53	/* Rotate Local Block Arbitration */
-#define RGPARM0_ROTATEARB_MASK	(UINT64_CAST 0x1 << 53)
-#define RGPARM0_FAIREN_SHFT	52	/* Fairness logic Enable */
-#define RGPARM0_FAIREN_MASK	(UINT64_CAST 0x1 << 52)
-#define RGPARM0_LOCGNTTO_SHFT	40	/* Local grant timeout */
-#define RGPARM0_LOCGNTTO_MASK	(UINT64_CAST 0xfff << 40)
-#define RGPARM0_DATELINE_SHFT	38	/* Dateline crossing router */
-#define RGPARM0_DATELINE_MASK	(UINT64_CAST 0x1 << 38)
-#define RGPARM0_MAXRETRY_SHFT	28	/* Max retry count */
-#define RGPARM0_MAXRETRY_MASK	(UINT64_CAST 0x3ff << 28)
-#define RGPARM0_URGWRAP_SHFT	20	/* Urgent wrap */
-#define RGPARM0_URGWRAP_MASK	(UINT64_CAST 0xff << 20)
-#define RGPARM0_DEADLKTO_SHFT	16	/* Deadlock timeout */
-#define RGPARM0_DEADLKTO_MASK	(UINT64_CAST 0xf << 16)
-#define RGPARM0_URGVAL_SHFT	12	/* Urgent value */
-#define RGPARM0_URGVAL_MASK	(UINT64_CAST 0xf << 12)
-#define RGPARM0_VCHSELEN_SHFT	11	/* VCH_SEL_EN */
-#define RGPARM0_VCHSELEN_MASK	(UINT64_CAST 0x1 << 11)
-#define RGPARM0_LOCURGTO_SHFT	9	/* Local urgent timeout */
-#define RGPARM0_LOCURGTO_MASK	(UINT64_CAST 0x3 << 9)
-#define RGPARM0_TAILVAL_SHFT	5	/* Tail value */
-#define RGPARM0_TAILVAL_MASK	(UINT64_CAST 0xf << 5)
-#define RGPARM0_CLOCK_SHFT	1	/* Global clock select */
-#define RGPARM0_CLOCK_MASK	(UINT64_CAST 0xf << 1)
-#define RGPARM0_BYPEN_SHFT	0
-#define RGPARM0_BYPEN_MASK	(UINT64_CAST 1)	/* Bypass enable */
-
-/*
- * RR_GLOBAL_PARMS1 shift and mask definitions
- */
-
-#define RGPARM1_TTOWRAP_SHFT	12	/* Tail timeout wrap */
-#define RGPARM1_TTOWRAP_MASK	(UINT64_CAST 0xfffff << 12)
-#define RGPARM1_AGERATE_SHFT	8	/* Age rate */
-#define RGPARM1_AGERATE_MASK	(UINT64_CAST 0xf << 8)
-#define RGPARM1_JSWSTAT_SHFT	0	/* JTAG Sw Register bits */
-#define RGPARM1_JSWSTAT_MASK	(UINT64_CAST 0xff << 0)
-
-/*
- * RR_DIAG_PARMS mask and shift definitions
- */
-
-#define RDPARM_ABSHISTOGRAM	(UINT64_CAST 1 << 17)	/* Absolute histgrm */
-#define RDPARM_DEADLOCKRESET	(UINT64_CAST 1 << 16)	/* Reset on deadlck */
-#define RDPARM_DISABLE(_L)	(UINT64_CAST 1 << ((_L) +  7))
-#define RDPARM_SENDERROR(_L)	(UINT64_CAST 1 << ((_L) -  1))
-
-/*
- * RR_DEBUG_ADDR mask and shift definitions
- */
-
-#define RDA_DATA_SHFT		10	/* Observed debug data */
-#define RDA_DATA_MASK		(UINT64_CAST 0xffff << 10)
-#define RDA_ADDR_SHFT		0	/* debug address for data */
-#define RDA_ADDR_MASK		(UINT64_CAST 0x3ff << 0)
-
-/*
- * RR_LB_TO_L2 mask and shift definitions
- */
-
-#define RLBTOL2_DATA_VLD_SHFT	32	/* data is valid for JTAG controller */
-#define RLBTOL2_DATA_VLD_MASK	(UINT64_CAST 0x1 << 32)
-#define RLBTOL2_DATA_SHFT	0	/* data bits for JTAG controller */
-#define RLBTOL2_DATA_MASK	(UINT64_CAST 0xffffffff)
-
-/*
- * RR_L2_TO_LB mask and shift definitions
- */
-
-#define RL2TOLB_DATA_VLD_SHFT	33	/* data is valid from JTAG controller */
-#define RL2TOLB_DATA_VLD_MASK	(UINT64_CAST 0x1 << 33)
-#define RL2TOLB_PARITY_SHFT	32	/* sw implemented parity for data */
-#define RL2TOLB_PARITY_MASK	(UINT64_CAST 0x1 << 32)
-#define RL2TOLB_DATA_SHFT	0	/* data bits from JTAG controller */
-#define RL2TOLB_DATA_MASK	(UINT64_CAST 0xffffffff)
-
-/*
- * RR_JBUS_CONTROL mask and shift definitions
- */
-
-#define RJC_POS_BITS_SHFT	20	/* Router position bits */
-#define RJC_POS_BITS_MASK	(UINT64_CAST 0xf << 20)
-#define RJC_RD_DATA_STROBE_SHFT	16	/* count when read data is strobed in */
-#define RJC_RD_DATA_STROBE_MASK	(UINT64_CAST 0xf << 16)
-#define RJC_WE_OE_HOLD_SHFT	8	/* time OE or WE is held */
-#define RJC_WE_OE_HOLD_MASK	(UINT64_CAST 0xff << 8)
-#define RJC_ADDR_SET_HLD_SHFT	0	/* time address driven around OE/WE */
-#define RJC_ADDR_SET_HLD_MASK	(UINT64_CAST 0xff)
-
-/*
- * RR_SCRATCH_REGx mask and shift definitions
- *  note: these fields represent a software convention, and are not
- *        understood/interpreted by the hardware. 
- */
-
-#define	RSCR0_BOOTED_SHFT	63
-#define	RSCR0_BOOTED_MASK	(UINT64_CAST 0x1 << RSCR0_BOOTED_SHFT)
-#define RSCR0_LOCALID_SHFT	56
-#define RSCR0_LOCALID_MASK	(UINT64_CAST 0x7f << RSCR0_LOCALID_SHFT)
-#define	RSCR0_UNUSED_SHFT	48
-#define	RSCR0_UNUSED_MASK	(UINT64_CAST 0xff << RSCR0_UNUSED_SHFT)
-#define RSCR0_NIC_SHFT		0
-#define RSCR0_NIC_MASK		(UINT64_CAST 0xffffffffffff)
-
-#define RSCR1_MODID_SHFT	0
-#define RSCR1_MODID_MASK	(UINT64_CAST 0xffff)
-
-/*
- * RR_VECTOR_HW_BAR mask and shift definitions
- */
-
-#define BAR_TX_SHFT		27	/* Barrier in trans(m)it when read */
-#define BAR_TX_MASK		(UINT64_CAST 1 << BAR_TX_SHFT)
-#define BAR_VLD_SHFT		26	/* Valid Configuration */
-#define BAR_VLD_MASK		(UINT64_CAST 1 << BAR_VLD_SHFT)
-#define BAR_SEQ_SHFT		24	/* Sequence number */
-#define BAR_SEQ_MASK		(UINT64_CAST 3 << BAR_SEQ_SHFT)
-#define BAR_LEAFSTATE_SHFT	18	/* Leaf State */
-#define BAR_LEAFSTATE_MASK	(UINT64_CAST 0x3f << BAR_LEAFSTATE_SHFT)
-#define BAR_PARENT_SHFT		14	/* Parent Port */
-#define BAR_PARENT_MASK		(UINT64_CAST 0xf << BAR_PARENT_SHFT)
-#define BAR_CHILDREN_SHFT	6	/* Child Select port bits */
-#define BAR_CHILDREN_MASK	(UINT64_CAST 0xff << BAR_CHILDREN_SHFT)
-#define BAR_LEAFCOUNT_SHFT	0	/* Leaf Count to trigger parent */
-#define BAR_LEAFCOUNT_MASK	(UINT64_CAST 0x3f)
-
-/*
- * RR_PORT_PARMS(_L) mask and shift definitions
- */
-
-#define RPPARM_MIPRESETEN_SHFT	29	/* Message In Progress reset enable */
-#define RPPARM_MIPRESETEN_MASK	(UINT64_CAST 0x1 << 29)
-#define RPPARM_UBAREN_SHFT	28	/* Enable user barrier requests */
-#define RPPARM_UBAREN_MASK	(UINT64_CAST 0x1 << 28)
-#define RPPARM_OUTPDTO_SHFT	24	/* Output Port Deadlock TO value */
-#define RPPARM_OUTPDTO_MASK	(UINT64_CAST 0xf << 24)
-#define RPPARM_PORTMATE_SHFT	21	/* Port Mate for the port */
-#define RPPARM_PORTMATE_MASK	(UINT64_CAST 0x7 << 21)
-#define RPPARM_HISTEN_SHFT	20	/* Histogram counter enable */
-#define RPPARM_HISTEN_MASK	(UINT64_CAST 0x1 << 20)
-#define RPPARM_HISTSEL_SHFT	18
-#define RPPARM_HISTSEL_MASK	(UINT64_CAST 0x3 << 18)
-#define RPPARM_DAMQHS_SHFT	16
-#define RPPARM_DAMQHS_MASK	(UINT64_CAST 0x3 << 16)
-#define RPPARM_NULLTO_SHFT	10
-#define RPPARM_NULLTO_MASK	(UINT64_CAST 0x3f << 10)
-#define RPPARM_MAXBURST_SHFT	0
-#define RPPARM_MAXBURST_MASK	(UINT64_CAST 0x3ff)
-
-/*
- * NOTE: Normally the kernel tracks only UTILIZATION statistics.
- * The other 2 should not be used, except during any experimentation
- * with the router.
- */
-#define RPPARM_HISTSEL_AGE	0	/* Histogram age characterization.  */
-#define RPPARM_HISTSEL_UTIL	1	/* Histogram link utilization 	    */
-#define RPPARM_HISTSEL_DAMQ	2	/* Histogram DAMQ characterization. */
-
-/*
- * RR_STATUS_ERROR(_L) and RR_ERROR_CLEAR(_L) mask and shift definitions
- */
-#define RSERR_POWERNOK		(UINT64_CAST 1 << 38)
-#define RSERR_PORT_DEADLOCK     (UINT64_CAST 1 << 37)
-#define RSERR_WARMRESET         (UINT64_CAST 1 << 36)
-#define RSERR_LINKRESET         (UINT64_CAST 1 << 35)
-#define RSERR_RETRYTIMEOUT      (UINT64_CAST 1 << 34)
-#define RSERR_FIFOOVERFLOW	(UINT64_CAST 1 << 33)
-#define RSERR_ILLEGALPORT	(UINT64_CAST 1 << 32)
-#define RSERR_DEADLOCKTO_SHFT	28
-#define RSERR_DEADLOCKTO_MASK	(UINT64_CAST 0xf << 28)
-#define RSERR_RECVTAILTO_SHFT	24
-#define RSERR_RECVTAILTO_MASK	(UINT64_CAST 0xf << 24)
-#define RSERR_RETRYCNT_SHFT	16
-#define RSERR_RETRYCNT_MASK	(UINT64_CAST 0xff << 16)
-#define RSERR_CBERRCNT_SHFT	8
-#define RSERR_CBERRCNT_MASK	(UINT64_CAST 0xff << 8)
-#define RSERR_SNERRCNT_SHFT	0
-#define RSERR_SNERRCNT_MASK	(UINT64_CAST 0xff << 0)
-
-
-#define PORT_STATUS_UP		(1 << 0)	/* Router link up */
-#define PORT_STATUS_FENCE	(1 << 1)	/* Router link fenced */
-#define PORT_STATUS_RESETFAIL	(1 << 2)	/* Router link didnot 
-						 * come out of reset */
-#define PORT_STATUS_DISCFAIL	(1 << 3)	/* Router link failed after 
-						 * out of reset but before
-						 * router tables were
-						 * programmed
-						 */
-#define PORT_STATUS_KERNFAIL	(1 << 4)	/* Router link failed
-						 * after reset and the 
-						 * router tables were
-						 * programmed
-						 */
-#define PORT_STATUS_UNDEF	(1 << 5)	/* Unable to pinpoint
-						 * why the router link
-						 * went down
-						 */	
-#define PROBE_RESULT_BAD	(-1)		/* Set if any of the router
-						 * links failed after reset
-						 */
-#define PROBE_RESULT_GOOD	(0)		/* Set if all the router links
-						 * which came out of reset 
-						 * are up
-						 */
-
-/* Should be enough for 256 CPUs */
-#define MAX_RTR_BREADTH		64		/* Max # of routers possible */
-
-/* Get the require set of bits in a var. corr to a sequence of bits  */
-#define GET_FIELD(var, fname) \
-        ((var) >> fname##_SHFT & fname##_MASK >> fname##_SHFT)
-/* Set the require set of bits in a var. corr to a sequence of bits  */
-#define SET_FIELD(var, fname, fval) \
-        ((var) = (var) & ~fname##_MASK | (uint64_t) (fval) << fname##_SHFT)
-
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-
-typedef struct router_map_ent_s {
-	uint64_t	nic;
-	moduleid_t	module;
-	slotid_t	slot;
-} router_map_ent_t;
-
-struct rr_status_error_fmt {
-	uint64_t	rserr_unused		: 30,
-			rserr_fifooverflow	: 1,
-			rserr_illegalport	: 1,
-			rserr_deadlockto	: 4,
-			rserr_recvtailto	: 4,
-			rserr_retrycnt		: 8,
-			rserr_cberrcnt		: 8,
-			rserr_snerrcnt		: 8;
-};
-
-/*
- * This type is used to store "absolute" counts of router events
- */
-typedef int	router_count_t;
-
-/* All utilizations are on a scale from 0 - 1023. */
-#define RP_BYPASS_UTIL	0
-#define RP_RCV_UTIL	1
-#define RP_SEND_UTIL	2
-#define RP_TOTAL_PKTS	3	/* Free running clock/packet counter */
-
-#define RP_NUM_UTILS	3
-
-#define RP_HIST_REGS	2
-#define RP_NUM_BUCKETS  4
-#define RP_HIST_TYPES	3
-
-#define RP_AGE0		0
-#define RP_AGE1		1
-#define RP_AGE2		2
-#define RP_AGE3		3
-
-
-#define RR_UTIL_SCALE	1024
-
-/*
- * Router port-oriented information
- */
-typedef struct router_port_info_s {
-	router_reg_t	rp_histograms[RP_HIST_REGS];/* Port usage info */
-	router_reg_t	rp_port_error;		/* Port error info */
-	router_count_t	rp_retry_errors;	/* Total retry errors */
-	router_count_t	rp_sn_errors;		/* Total sn errors */
-	router_count_t	rp_cb_errors;		/* Total cb errors */
-	int		rp_overflows;		/* Total count overflows */
-	int		rp_excess_err;		/* Port has excessive errors */
-	ushort		rp_util[RP_NUM_BUCKETS];/* Port utilization */
-} router_port_info_t;
-
-#define ROUTER_INFO_VERSION	7
-
-struct lboard_s;
-
-/*
- * Router information
- */
-typedef struct router_info_s {
-	char		ri_version;	/* structure version		    */
-	cnodeid_t	ri_cnode;	/* cnode of its legal guardian hub  */
-	nasid_t		ri_nasid;	/* Nasid of same 		    */
-	char		ri_ledcache;	/* Last LED bitmap		    */
-	char		ri_leds;	/* Current LED bitmap		    */
-	char		ri_portmask;	/* Active port bitmap		    */
-	router_reg_t	ri_stat_rev_id;	/* Status rev ID value		    */
-	net_vec_t	ri_vector;	/* vector from guardian to router   */
-	int		ri_writeid;	/* router's vector write ID	    */
-	int64_t	ri_timebase;	/* Time of first sample		    */
-	int64_t	ri_timestamp;	/* Time of last sample		    */
-	router_port_info_t ri_port[MAX_ROUTER_PORTS]; /* per port info      */
-	moduleid_t	ri_module;	/* Which module are we in?	    */
-	slotid_t	ri_slotnum;	/* Which slot are we in?	    */
-	router_reg_t	ri_glbl_parms[GLBL_PARMS_REGS];
-					/* Global parms0&1 register contents*/
-	devfs_handle_t	ri_vertex;	/* hardware graph vertex            */
-	router_reg_t	ri_prot_conf;	/* protection config. register	    */
-	int64_t	ri_per_minute;	/* Ticks per minute		    */
-
-	/*
-	 * Everything below here is for kernel use only and may change at	
-	 * at any time with or without a change in teh revision number
-	 *
-	 * Any pointers or things that come and go with DEBUG must go at
- 	 * the bottom of the structure, below the user stuff.
-	 */
-	char		ri_hist_type;   /* histogram type		    */
-	devfs_handle_t	ri_guardian;	/* guardian node for the router	    */
-	int64_t	ri_last_print;	/* When did we last print	    */
-	char		ri_print;	/* Should we print 		    */
-	char 		ri_just_blink;	/* Should we blink the LEDs         */
-	
-#ifdef DEBUG
-	int64_t	ri_deltatime;	/* Time it took to sample	    */
-#endif
-	spinlock_t	ri_lock;	/* Lock for access to router info   */
-	net_vec_t	*ri_vecarray;	/* Pointer to array of vectors	    */
-	struct lboard_s	*ri_brd;	/* Pointer to board structure	    */
-	char *		ri_name;	/* This board's hwg path 	    */
-        unsigned char	ri_port_maint[MAX_ROUTER_PORTS]; /* should we send a 
-					message to availmon */
-} router_info_t;
-
-
-/* Router info location specifiers */
-
-#define RIP_PROMLOG			2	/* Router info in promlog */
-#define RIP_CONSOLE			4	/* Router info on console */
-
-#define ROUTER_INFO_PRINT(_rip,_where)	(_rip->ri_print |= _where)	
-					/* Set the field used to check if a 
-					 * router info can be printed
-					 */
-#define IS_ROUTER_INFO_PRINTED(_rip,_where)	\
-					(_rip->ri_print & _where)	
-					/* Was the router info printed to
-					 * the given location (_where) ?
-					 * Mainly used to prevent duplicate
-					 * router error states.
-					 */
-#define ROUTER_INFO_LOCK(_rip,_s)	_s = mutex_spinlock(&(_rip->ri_lock))
-					/* Take the lock on router info
-					 * to gain exclusive access
-					 */
-#define ROUTER_INFO_UNLOCK(_rip,_s)	mutex_spinunlock(&(_rip->ri_lock),_s)
-					/* Release the lock on router info */
-/* 
- * Router info hanging in the nodepda 
- */
-typedef struct nodepda_router_info_s {
-	devfs_handle_t 	router_vhdl;	/* vertex handle of the router 	    */
-	short		router_port;	/* port thru which we entered       */
-	short		router_portmask;
-	moduleid_t	router_module;	/* module in which router is there  */
-	slotid_t	router_slot;	/* router slot			    */
-	unsigned char	router_type;	/* kind of router 		    */
-	net_vec_t	router_vector;	/* vector from the guardian node    */
-
-	router_info_t	*router_infop;	/* info hanging off the hwg vertex  */
-	struct nodepda_router_info_s *router_next;
-	                                /* pointer to next element 	    */
-} nodepda_router_info_t;
-
-#define ROUTER_NAME_SIZE	20	/* Max size of a router name */
-
-#define NORMAL_ROUTER_NAME	"normal_router"
-#define NULL_ROUTER_NAME	"null_router"
-#define META_ROUTER_NAME	"meta_router"
-#define REPEATER_ROUTER_NAME	"repeater_router"
-#define UNKNOWN_ROUTER_NAME	"unknown_router" 
-
-/* The following definitions are needed by the router traversing
- * code either using the hardware graph or using vector operations.
- */
-/* Structure of the router queue element */
-typedef struct router_elt_s {
-	union {
-		/* queue element structure during router probing */
-		struct {
-			/* number-in-a-can (unique) for the router */
-			nic_t		nic;	
-			/* vector route from the master hub to 
-			 * this router.
-			 */
-			net_vec_t	vec;	
-			/* port status */
-			uint64_t	status;	
-			char		port_status[MAX_ROUTER_PORTS + 1];
-		} r_elt;
-		/* queue element structure during router guardian 
-		 * assignment
-		 */
-		struct {
-			/* vertex handle for the router */
-			devfs_handle_t	vhdl;
-			/* guardian for this router */
-			devfs_handle_t	guard;	
-			/* vector router from the guardian to the router */
-			net_vec_t	vec;
-		} k_elt;
-	} u;
-	                        /* easy to use port status interpretation */
-} router_elt_t;
-
-/* structure of the router queue */
-
-typedef struct router_queue_s {
-	char		head;	/* Point where a queue element is inserted */
-	char		tail;	/* Point where a queue element is removed */
-	int		type;
-	router_elt_t	array[MAX_RTR_BREADTH];
-	                        /* Entries for queue elements */
-} router_queue_t;
-
-
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-/*
- * RR_HISTOGRAM(_L) mask and shift definitions
- * There are two 64 bit histogram registers, so the following macros take
- * into account dealing with an array of 4 32 bit values indexed by _x
- */
-
-#define RHIST_BUCKET_SHFT(_x)	(32 * ((_x) & 0x1))
-#define RHIST_BUCKET_MASK(_x)	(UINT64_CAST 0xffffffff << RHIST_BUCKET_SHFT((_x) & 0x1))
-#define RHIST_GET_BUCKET(_x, _reg)	\
-	((RHIST_BUCKET_MASK(_x) & ((_reg)[(_x) >> 1])) >> RHIST_BUCKET_SHFT(_x))
-
-/*
- * RR_RESET_MASK(_L) mask and shift definitions
- */
-
-#define RRM_RESETOK(_L)		(UINT64_CAST 1 << ((_L) - 1))
-#define RRM_RESETOK_ALL		ALL_PORTS
-
-/*
- * RR_META_TABLE(_x) and RR_LOCAL_TABLE(_x) mask and shift definitions
- */
-
-#define RTABLE_SHFT(_L)		(4 * ((_L) - 1))
-#define RTABLE_MASK(_L)		(UINT64_CAST 0x7 << RTABLE_SHFT(_L))
-
-
-#define	ROUTERINFO_STKSZ	4096
-
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
-#if defined(_LANGUAGE_C_PLUS_PLUS)
-extern "C" {
-#endif
-
-int router_reg_read(router_info_t *rip, int regno, router_reg_t *val);
-int router_reg_write(router_info_t *rip, int regno, router_reg_t val);
-int router_get_info(devfs_handle_t routerv, router_info_t *, int);
-int router_init(cnodeid_t cnode,int writeid, nodepda_router_info_t *npda_rip);
-int router_set_leds(router_info_t *rip);
-void router_print_state(router_info_t *rip, int level,
-		   void (*pf)(int, char *, ...),int print_where);
-void capture_router_stats(router_info_t *rip);
-
-
-int 	probe_routers(void);
-void 	get_routername(unsigned char brd_type,char *rtrname);
-void 	router_guardians_set(devfs_handle_t hwgraph_root);
-int 	router_hist_reselect(router_info_t *, int64_t);
-#if defined(_LANGUAGE_C_PLUS_PLUS)
-}
-#endif
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
-
-#endif /* _ASM_SN_SN1_ROUTER_H */
diff -Nru a/include/asm-ia64/sn/sn1/slotnum.h b/include/asm-ia64/sn/sn1/slotnum.h
--- a/include/asm-ia64/sn/sn1/slotnum.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn1/slotnum.h	Fri Mar 15 17:51:03 2002
@@ -4,12 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef _ASM_SN_SN1_SLOTNUM_H
-#define _ASM_SN_SN1_SLOTNUM_H
+#ifndef _ASM_IA64_SN_SN1_SLOTNUM_H
+#define _ASM_IA64_SN_SN1_SLOTNUM_H
 
 #define SLOTNUM_MAXLENGTH	16
 
@@ -85,4 +84,4 @@
 
 #endif /* __KERNEL__ */
 
-#endif /* _ASM_SN_SN1_SLOTNUM_H */
+#endif /* _ASM_IA64_SN_SN1_SLOTNUM_H */
diff -Nru a/include/asm-ia64/sn/sn1/sn1.h b/include/asm-ia64/sn/sn1/sn1.h
--- a/include/asm-ia64/sn/sn1/sn1.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,34 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-/*
- * sn1.h -- hardware specific defines for sn1 boards
- * The defines used here are used to limit the size of 
- * various datastructures in the PROM. eg. KLCFGINFO, MPCONF etc.
- */
-
-#ifndef _ASM_SN_SN1_SN1_H
-#define _ASM_SN_SN1_SN1_H
-
-extern xwidgetnum_t hub_widget_id(nasid_t);
-extern nasid_t get_nasid(void);
-extern int	get_slice(void);
-extern int     is_fine_dirmode(void);
-extern hubreg_t get_hub_chiprev(nasid_t nasid);
-extern hubreg_t get_region(cnodeid_t);
-extern hubreg_t nasid_to_region(nasid_t);
-extern int      verify_snchip_rev(void);
-extern void 	ni_reset_port(void);
-
-#ifdef SN1_USE_POISON_BITS
-extern int hub_bte_poison_ok(void);
-#endif /* SN1_USE_POISON_BITS */
-
-#endif /* _ASM_SN_SN1_SN1_H */
diff -Nru a/include/asm-ia64/sn/sn1/sn_private.h b/include/asm-ia64/sn/sn1/sn_private.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/sn_private.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,292 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN1_SN_PRIVATE_H
+#define _ASM_IA64_SN_SN1_SN_PRIVATE_H
+
+#include <asm/sn/nodepda.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xtalk_private.h>
+
+extern nasid_t master_nasid;
+
+/* promif.c */
+#ifdef	LATER
+extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes);
+#endif
+extern void he_arcs_set_vectors(void);
+extern void mem_init(void);
+#ifdef	LATER
+extern int cpu_enabled(cpuid_t);
+#endif
+extern void cpu_unenable(cpuid_t);
+extern nasid_t get_lowest_nasid(void);
+extern __psunsigned_t get_master_bridge_base(void);
+extern void set_master_bridge_base(void);
+extern int check_nasid_equiv(nasid_t, nasid_t);
+extern nasid_t get_console_nasid(void);
+extern char get_console_pcislot(void);
+#ifdef	LATER
+extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
+#endif
+
+extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
+
+/* memsupport.c */
+extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
+extern int memory_present(paddr_t);
+extern int memory_read_accessible(paddr_t);
+extern int memory_write_accessible(paddr_t);
+extern void memory_set_access(paddr_t, int, int);
+extern void show_dir_state(paddr_t, void (*)(char *, ...));
+extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
+extern void set_dir_owner(paddr_t, int);
+extern void set_dir_state(paddr_t, int);
+extern void set_dir_state_POISONED(paddr_t);
+extern void set_dir_state_UNOWNED(paddr_t);
+extern int is_POISONED_dir_state(paddr_t);
+extern int is_UNOWNED_dir_state(paddr_t);
+extern void get_dir_ent(paddr_t paddr, int *state,
+			uint64_t *vec_ptr, hubreg_t *elo);
+
+/* intr.c */
+extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
+extern void intr_unreserve_level(cpuid_t cpu, int level);
+extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
+			intr_func_t intr_prefunc);
+extern int intr_disconnect_level(cpuid_t cpu, int bit);
+extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
+			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
+			      char *intr_name,int *resp_bit);
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+extern void setrtvector(intr_func_t);
+extern void install_cpuintr(cpuid_t cpu);
+extern void install_dbgintr(cpuid_t cpu);
+extern void install_tlbintr(cpuid_t cpu);
+extern void hub_migrintr_init(cnodeid_t /*cnode*/);
+extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
+extern int cause_intr_disconnect(int level);
+extern void intr_reserve_hardwired(cnodeid_t);
+extern void intr_clear_all(nasid_t);
+extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
+
+/* error_dump.c */
+extern char *hub_rrb_err_type[];
+extern char *hub_wrb_err_type[];
+
+void nmi_dump(void);
+void install_cpu_nmi_handler(int slice);
+
+/* klclock.c */
+extern void hub_rtc_init(cnodeid_t);
+
+/* bte.c */
+void bte_lateinit(void);
+void bte_wait_for_xfer_completion(void *);
+
+/* klgraph.c */
+void klhwg_add_all_nodes(devfs_handle_t);
+void klhwg_add_all_modules(devfs_handle_t);
+
+/* klidbg.c */
+void install_klidbg_functions(void);
+
+/* klnuma.c */
+extern void replicate_kernel_text(int numnodes);
+extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
+extern void setup_replication_mask(int maxnodes);
+
+/* init.c */
+extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
+extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
+extern void init_platform_pda(cpuid_t cpu);
+extern void per_cpu_init(void);
+#ifdef	LATER
+extern cpumask_t boot_cpumask;
+#endif
+extern int is_fine_dirmode(void);
+extern void update_node_information(cnodeid_t);
+ 
+#ifdef	LATER
+/* clksupport.c */
+extern void early_counter_intr(eframe_t *);
+#endif
+
+/* hubio.c */
+extern void hubio_init(void);
+extern void hub_merge_clean(nasid_t nasid);
+extern void hub_set_piomode(nasid_t nasid, int conveyor);
+
+/* huberror.c */
+extern void hub_error_init(cnodeid_t);
+extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
+extern void hubni_error_handler(char *, int);
+extern int check_ni_errors(void);
+
+/* Used for debugger to signal upper software a breakpoint has taken place */
+
+extern void		*debugger_update;
+extern __psunsigned_t	debugger_stopped;
+
+/* 
+ * IP27 piomap, created by hub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_piomap_s by generic xtalk routines.
+ */
+struct hub_piomap_s {
+	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
+	devfs_handle_t		hpio_hub;	/* which hub's mapping registers are set up */
+	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
+	char			hpio_bigwin_num;/* if big window map, which one */
+	int 			hpio_flags;	/* defined below */
+};
+/* hub_piomap flags */
+#define HUB_PIOMAP_IS_VALID		0x1
+#define HUB_PIOMAP_IS_BIGWINDOW		0x2
+#define HUB_PIOMAP_IS_FIXED		0x4
+
+#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
+#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
+#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
+
+#if TBD
+ /* Ensure that hpio_xtalk_info is first */
+ #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0)
+#endif
+
+
+/* 
+ * IP27 dmamap, created by hub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_dmamap_s by generic xtalk routines.
+ */
+struct hub_dmamap_s {
+	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
+	devfs_handle_t		hdma_hub;	/* which hub we go through */
+	int			hdma_flags;	/* defined below */
+};
+/* hub_dmamap flags */
+#define HUB_DMAMAP_IS_VALID		0x1
+#define HUB_DMAMAP_USED			0x2
+#define	HUB_DMAMAP_IS_FIXED		0x4
+
+#if TBD
+ /* Ensure that hdma_xtalk_info is first */
+ #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0)
+#endif
+
+/* 
+ * IP27 interrupt handle, created by hub_intr_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_intr_s by generic xtalk routines.
+ */
+struct hub_intr_s {
+	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
+	ilvl_t			i_swlevel;	/* software level for blocking intr */
+	cpuid_t			i_cpuid;	/* which cpu */
+	int			i_bit;		/* which bit */
+	int			i_flags;
+};
+/* flag values */
+#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
+#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
+
+#if TBD
+ /* Ensure that i_xtalk_info is first */
+ #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0)
+#endif
+
+
+/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */
+/* TBD: IP27-dependent stuff currently in nodepda.h should be here */
+typedef struct hubinfo_s {
+	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
+	cnodeid_t			h_cnodeid;	/* compact nodeid */
+	nasid_t				h_nasid;	/* nasid */
+
+	/* structures for PIO management */
+	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
+	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
+	sv_t				h_bwwait;	/* wait for big window to free */
+	spinlock_t			h_bwlock;	/* guard big window piomap's */
+	spinlock_t			h_crblock;      /* gaurd CRB error handling */
+	int				h_num_big_window_fixed;	/* count number of FIXED maps */
+	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
+	hub_intr_t			hub_ii_errintr;
+} *hubinfo_t;
+
+#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
+
+#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
+
+#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
+
+/*
+ * Hub info PIO map access functions.
+ */
+#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
+			(&hinfo->h_big_window_piomap[win])
+#define	hubinfo_swin_piomap_get(hinfo, win)	\
+			(&hinfo->h_small_window_piomap[win])
+	
+/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */
+/* TBD: IP27-dependent stuff currently in pda.h should be here */
+typedef struct cpuinfo_s {
+#ifdef	LATER
+	pda_t		*ci_cpupda;	/* pointer to CPU's private data area */
+#endif
+	cpuid_t		ci_cpuid;	/* CPU ID */
+} *cpuinfo_t;
+
+#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
+
+#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
+
+/* Special initialization function for xswitch vertices created during startup. */
+extern void xswitch_vertex_init(devfs_handle_t xswitch);
+
+extern xtalk_provider_t hub_provider;
+
+/* du.c */
+int ducons_write(char *buf, int len);
+
+/* memerror.c */
+
+extern void install_eccintr(cpuid_t cpu);
+extern void memerror_get_stats(cnodeid_t cnode,
+			       int *bank_stats, int *bank_stats_max);
+extern void probe_md_errors(nasid_t);
+/* sysctlr.c */
+extern void sysctlr_init(void);
+extern void sysctlr_power_off(int sdonly);
+extern void sysctlr_keepalive(void);
+
+#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
+
+/* Useful definitions to get the memory dimm given a physical
+ * address.
+ */
+#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
+extern void membank_pathname_get(paddr_t,char *);
+
+/* To redirect the output into the error buffer */
+#define errbuf_print(_s)	printf("#%s",_s)
+
+extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
+void bootstrap(void);
+
+/* sndrv.c */
+extern int sndrv_attach(devfs_handle_t vertex);
+
+#endif /* _ASM_IA64_SN_SN1_SN_PRIVATE_H */
diff -Nru a/include/asm-ia64/sn/sn1/synergy.h b/include/asm-ia64/sn/sn1/synergy.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn1/synergy.h	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,187 @@
+#ifndef _ASM_IA64_SN_SN1_SYNERGY_H
+#define _ASM_IA64_SN_SN1_SYNERGY_H
+
+#include <asm/io.h>
+#include <asm/sn/hcl.h>
+#include <asm/sn/addrs.h>
+#include <asm/sn/intr_public.h>
+
+
+/*
+ * Definitions for the synergy asic driver
+ * 
+ * These are for SGI platforms only.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#define SYNERGY_L4_BYTES		(64UL*1024*1024)
+#define SYNERGY_L4_WAYS			8
+#define SYNERGY_L4_BYTES_PER_WAY	(SYNERGY_L4_BYTES/SYNERGY_L4_WAYS)
+#define SYNERGY_BLOCK_SIZE		512UL
+
+
+#define SSPEC_BASE	(0xe0000000000UL)
+#define LB_REG_BASE	(SSPEC_BASE + 0x0)
+
+#define VEC_MASK3A_ADDR	(0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK3B_ADDR	(0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK3A	(0x2a0)
+#define VEC_MASK3B	(0x2a8)
+
+#define VEC_MASK2A_ADDR	(0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK2B_ADDR	(0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK2A	(0x2b0)
+#define VEC_MASK2B	(0x2b8)
+
+#define VEC_MASK1A_ADDR	(0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK1B_ADDR	(0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK1A	(0x2c0)
+#define VEC_MASK1B	(0x2c8)
+
+#define VEC_MASK0A_ADDR	(0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK0B_ADDR	(0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define VEC_MASK0A	(0x2d0)
+#define VEC_MASK0B	(0x2d8)
+
+#define GBL_PERF_A_ADDR (0x330 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+#define GBL_PERF_B_ADDR (0x338 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
+
+#define WRITE_LOCAL_SYNERGY_REG(addr, value)	__synergy_out(addr, value)
+
+#define HUB_L(_a)               *(_a)
+#define HUB_S(_a, _d)           *(_a) = (_d)
+
+#define HSPEC_SYNERGY0_0        0x04000000    /* Synergy0 Registers     */
+#define HSPEC_SYNERGY1_0        0x05000000    /* Synergy1 Registers     */
+#define HS_SYNERGY_STRIDE       (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
+#define REMOTE_HSPEC(_n, _x)    (HUBREG_CAST (RREG_BASE(_n) + (_x)))
+
+#define RREG_BASE(_n)           (NODE_LREG_BASE(_n))
+#define NODE_LREG_BASE(_n)      (NODE_HSPEC_BASE(_n) + 0x30000000)
+#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
+#ifndef HSPEC_BASE
+#define HSPEC_BASE              (SYN_UNCACHED_SPACE | HSPEC_BASE_SYN)
+#endif
+#define SYN_UNCACHED_SPACE      0xc000000000000000
+#define HSPEC_BASE_SYN          0x00000b0000000000
+#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
+#define NODE_SIZE_BITS		33
+
+#define SYN_TAG_DISABLE_WAY	(SSPEC_BASE+0xae0)
+
+
+#define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg))
+
+#define REMOTE_SYNERGY_LOAD(nasid, fsb, reg)  __remote_synergy_in(nasid, fsb, reg)
+#define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
+
+static inline uint64_t
+__remote_synergy_in(int nasid, int fsb, uint64_t reg) {
+	volatile uint64_t *addr;
+
+	addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, reg));
+	return (*addr);
+}
+
+static inline void
+__remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) {
+	volatile uint64_t *addr;
+
+        addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, (reg<<2)));
+        *(addr+0) = value >> 48;
+        *(addr+1) = value >> 32;
+        *(addr+2) = value >> 16;
+        *(addr+3) = value;
+        __ia64_mf_a();
+}
+
+/* XX this doesn't make a lot of sense. Which fsb?  */
+static inline void
+__synergy_out(unsigned long addr, unsigned long value)
+{
+	volatile unsigned long *adr = (unsigned long *)
+			(addr | __IA64_UNCACHED_OFFSET);
+
+	*adr = value;
+	__ia64_mf_a();
+}
+
+#define READ_LOCAL_SYNERGY_REG(addr)	__synergy_in(addr)
+
+/* XX this doesn't make a lot of sense. Which fsb? */
+static inline unsigned long
+__synergy_in(unsigned long addr)
+{
+	unsigned long ret, *adr = (unsigned long *)
+			(addr | __IA64_UNCACHED_OFFSET);
+
+	ret = *adr;
+	__ia64_mf_a();
+	return ret;
+}
+
+struct sn1_intr_action {
+	void (*handler)(int, void *, struct pt_regs *);
+	void *intr_arg;
+	unsigned long flags;
+	struct sn1_intr_action * next;
+};
+
+typedef struct synergy_da_s {
+	hub_intmasks_t	s_intmasks;
+}synergy_da_t;
+
+struct sn1_cnode_action_list {
+	spinlock_t action_list_lock;
+	struct sn1_intr_action *action_list;
+};
+
+/*
+ * ioctl cmds for node/hub/synergy/[01]/mon for synergy
+ * perf monitoring are defined in sndrv.h
+ */
+
+/* multiplex the counters every 10 timer interrupts */ 
+#define SYNERGY_PERF_FREQ_DEFAULT 10
+
+/* macros for synergy "mon" device ioctl handler */
+#define SYNERGY_PERF_INFO(_s, _f)	(arbitrary_info_t)(((_s) << 16)|(_f))
+#define SYNERGY_PERF_INFO_CNODE(_x)	(cnodeid_t)(((uint64_t)_x) >> 16)
+#define SYNERGY_PERF_INFO_FSB(_x)	(((uint64_t)_x) & 1)
+
+/* synergy perf control registers */
+#define PERF_CNTL0_A            0xab0UL /* control A on FSB0 */
+#define PERF_CNTL0_B            0xab8UL /* control B on FSB0 */
+#define PERF_CNTL1_A            0xac0UL /* control A on FSB1 */
+#define PERF_CNTL1_B            0xac8UL /* control B on FSB1 */
+
+/* synergy perf counters */
+#define PERF_CNTR0_A            0xad0UL /* counter A on FSB0 */
+#define PERF_CNTR0_B            0xad8UL /* counter B on FSB0 */
+#define PERF_CNTR1_A            0xaf0UL /* counter A on FSB1 */
+#define PERF_CNTR1_B            0xaf8UL /* counter B on FSB1 */
+
+/* Synergy perf data. Each nodepda keeps a list of these */
+struct synergy_perf_s {
+        uint64_t        intervals;      /* count of active intervals for this event */
+        uint64_t        total_intervals;/* snapshot of total intervals */
+        uint64_t        modesel;        /* mode and sel bits, both A and B registers */
+        struct synergy_perf_s *next;	/* next in circular linked list */
+        uint64_t        counts[2];      /* [0] is synergy-A counter, [1] synergy-B counter */
+};
+
+typedef struct synergy_perf_s synergy_perf_t;
+
+typedef struct synergy_info_s synergy_info_t;
+
+extern void synergy_perf_init(void);
+extern void synergy_perf_update(int);
+extern struct file_operations synergy_mon_fops;
+
+#endif /* _ASM_IA64_SN_SN1_SYNERGY_H */
diff -Nru a/include/asm-ia64/sn/sn1/uart16550.h b/include/asm-ia64/sn/sn1/uart16550.h
--- a/include/asm-ia64/sn/sn1/uart16550.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,228 +0,0 @@
-/* $Id$
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-
-#ifndef _ASM_SN_SN1_UART16550_H
-#define _ASM_SN_SN1_UART16550_H
-
-
-/*
- * Definitions for 16550  chip
- */
-
-	/* defined as offsets from the data register */
-#define REG_DAT     0   /* receive/transmit data */
-#define REG_ICR     1   /* interrupt control register */
-#define REG_ISR     2   /* interrupt status register */
-#define REG_FCR     2   /* fifo control register */
-#define REG_LCR     3   /* line control register */
-#define REG_MCR     4   /* modem control register */
-#define REG_LSR     5   /* line status register */
-#define REG_MSR     6   /* modem status register */
-#define REG_SCR     7   /* Scratch register      */
-#define REG_DLL     0   /* divisor latch (lsb) */
-#define REG_DLH     1   /* divisor latch (msb) */
-#define REG_EFR		2	/* 16650 enhanced feature register */
-
-/*
- * 16450/16550 Registers Structure.
- */
-
-/* Line Control Register */
-#define		LCR_WLS0	0x01	/*word length select bit 0 */	
-#define		LCR_WLS1	0x02	/*word length select bit 2 */	
-#define		LCR_STB	0x04		/* number of stop bits */
-#define		LCR_PEN	0x08		/* parity enable */
-#define		LCR_EPS	0x10		/* even parity select */
-#define		LCR_SETBREAK 0x40	/* break key */
-#define		LCR_DLAB	0x80	/* divisor latch access bit */
-#define 	LCR_RXLEN   0x03    /* # of data bits per received/xmitted char */
-#define 	LCR_STOP1   0x00
-#define 	LCR_STOP2   0x04
-#define 	LCR_PAREN   0x08
-#define 	LCR_PAREVN  0x10
-#define 	LCR_PARMARK 0x20
-#define 	LCR_SNDBRK  0x40
-#define 	LCR_DLAB    0x80
-
-
-#define		LCR_BITS5	0x00	/* 5 bits per char */
-#define		LCR_BITS6	0x01	/* 6 bits per char */
-#define		LCR_BITS7	0x02	/* 7 bits per char */
-#define		LCR_BITS8	0x03	/* 8 bits per char */
-
-#define		LCR_MASK_BITS_CHAR 		0x03
-#define 	LCR_MASK_STOP_BITS		0x04
-#define		LCR_MASK_PARITY_BITS	0x18
-
-
-/* Line Status Register */
-#define		LSR_RCA	0x01		/* data ready */
-#define		LSR_OVRRUN	0x02	/* overrun error */
-#define		LSR_PARERR	0x04	/* parity error */
-#define		LSR_FRMERR	0x08	/* framing error */
-#define		LSR_BRKDET 	0x10	/* a break has arrived */
-#define		LSR_XHRE	0x20	/* tx hold reg is now empty */
-#define		LSR_XSRE	0x40	/* tx shift reg is now empty */
-#define		LSR_RFBE	0x80	/* rx FIFO Buffer error */
-
-/* Interrupt Status Regisger */
-#define		ISR_MSTATUS	0x00
-#define		ISR_TxRDY	0x02
-#define		ISR_RxRDY	0x04
-#define		ISR_ERROR_INTR	0x08
-#define		ISR_FFTMOUT 0x0c	/* FIFO Timeout */
-#define		ISR_RSTATUS 0x06	/* Receiver Line status */
-
-/* Interrupt Enable Register */
-#define		ICR_RIEN	0x01	/* Received Data Ready */
-#define		ICR_TIEN	0x02	/* Tx Hold Register Empty */
-#define		ICR_SIEN	0x04	/* Receiver Line Status */
-#define		ICR_MIEN	0x08	/* Modem Status */
-
-/* Modem Control Register */
-#define		MCR_DTR		0x01	/* Data Terminal Ready */
-#define		MCR_RTS		0x02	/* Request To Send */
-#define		MCR_OUT1	0x04	/* Aux output - not used */
-#define		MCR_OUT2	0x08	/* turns intr to 386 on/off */	
-#define		MCR_LOOP	0x10	/* loopback for diagnostics */
-#define		MCR_AFE 	0x20	/* Auto flow control enable */
-
-/* Modem Status Register */
-#define		MSR_DCTS	0x01	/* Delta Clear To Send */
-#define		MSR_DDSR	0x02	/* Delta Data Set Ready */
-#define		MSR_DRI		0x04	/* Trail Edge Ring Indicator */
-#define		MSR_DDCD	0x08	/* Delta Data Carrier Detect */
-#define		MSR_CTS		0x10	/* Clear To Send */
-#define		MSR_DSR		0x20	/* Data Set Ready */
-#define		MSR_RI		0x40	/* Ring Indicator */
-#define		MSR_DCD		0x80	/* Data Carrier Detect */
-
-#define 	DELTAS(x) 	((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD))
-#define 	STATES(x) 	((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD))
-
-
-#define		FCR_FIFOEN	0x01	/* enable receive/transmit fifo */
-#define		FCR_RxFIFO	0x02	/* enable receive fifo */
-#define		FCR_TxFIFO	0x04	/* enable transmit fifo */
-#define 	FCR_MODE1	0x08	/* change to mode 1 */
-#define		RxLVL0		0x00	/* Rx fifo level at 1	*/
-#define		RxLVL1		0x40	/* Rx fifo level at 4 */
-#define		RxLVL2		0x80	/* Rx fifo level at 8 */
-#define		RxLVL3		0xc0	/* Rx fifo level at 14 */
-
-#define 	FIFOEN		(FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) 
-
-#define		FCT_TxMASK	0x30	/* mask for Tx trigger */
-#define		FCT_RxMASK	0xc0	/* mask for Rx trigger */
-
-/* enhanced festures register */
-#define		EFR_SFLOW	0x0f	/* various S/w Flow Controls */
-#define 	EFR_EIC		0x10	/* Enhanced Interrupt Control bit */
-#define 	EFR_SCD		0x20	/* Special Character Detect */
-#define 	EFR_RTS		0x40	/* RTS flow control */
-#define 	EFR_CTS		0x80	/* CTS flow control */
-
-/* Rx Tx software flow controls in 16650 enhanced mode */
-#define		SFLOW_Tx0	0x00	/* no Xmit flow control */
-#define		SFLOW_Tx1	0x08	/* Transmit Xon1, Xoff1 */
-#define		SFLOW_Tx2	0x04	/* Transmit Xon2, Xoff2 */
-#define		SFLOW_Tx3	0x0c	/* Transmit Xon1,Xon2, Xoff1,Xoff2 */
-#define		SFLOW_Rx0	0x00	/* no Rcv flow control */
-#define		SFLOW_Rx1	0x02	/* Receiver compares Xon1, Xoff1 */
-#define		SFLOW_Rx2	0x01	/* Receiver compares Xon2, Xoff2 */
-
-#define	ASSERT_DTR(x)		(x |= MCR_DTR)
-#define	ASSERT_RTS(x)		(x |= MCR_RTS)
-#define DU_RTS_ASSERTED(x)  (((x) & MCR_RTS) != 0)
-#define DU_RTS_ASSERT(x)    ((x) |= MCR_RTS)
-#define DU_RTS_DEASSERT(x)  ((x) &= ~MCR_RTS)
-
-
-/*
- * ioctl(fd, I_STR, arg)
- * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI
- */
-#define SIOC        ('z' << 8)  /* z for z85130 */
-#define SIOC_EXTCLK (SIOC | 1)  /* select/de-select external clock */
-#define SIOC_RS422  (SIOC | 2)  /* select/de-select RS422 protocol */
-#define SIOC_ITIMER (SIOC | 3)  /* upstream timer adjustment */
-#define SIOC_LOOPBACK   (SIOC | 4)  /* diagnostic loopback test mode */
-
-
-/* channel control register */
-#define	DMA_INT_MASK		0xe0	/* ring intr mask */
-#define DMA_INT_TH25		0x20	/* 25% threshold */
-#define DMA_INT_TH50		0x40	/* 50% threshold */
-#define DMA_INT_TH75		0x60	/* 75% threshold */
-#define DMA_INT_EMPTY		0x80	/* ring buffer empty */
-#define DMA_INT_NEMPTY		0xa0	/* ring buffer not empty */
-#define DMA_INT_FULL		0xc0	/* ring buffer full */
-#define DMA_INT_NFULL		0xe0	/* ring buffer not full */
-
-#define DMA_CHANNEL_RESET	0x400	/* reset dma channel */
-#define DMA_ENABLE			0x200	/* enable DMA */
-
-/* peripheral controller intr status bits applicable to serial ports */
-#define ISA_SERIAL0_MASK 		0x03f00000	/* mask for port #1 intrs */
-#define ISA_SERIAL0_DIR			0x00100000	/* device intr request */
-#define ISA_SERIAL0_Tx_THIR		0x00200000	/* Transmit DMA threshold */
-#define ISA_SERIAL0_Tx_PREQ		0x00400000	/* Transmit DMA pair req */
-#define ISA_SERIAL0_Tx_MEMERR	0x00800000	/* Transmit DMA memory err */
-#define ISA_SERIAL0_Rx_THIR		0x01000000	/* Receive DMA threshold  */
-#define ISA_SERIAL0_Rx_OVERRUN	0x02000000	/* Receive DMA over-run  */
-
-#define ISA_SERIAL1_MASK 		0xfc000000	/* mask for port #1 intrs */
-#define ISA_SERIAL1_DIR			0x04000000	/* device intr request */
-#define ISA_SERIAL1_Tx_THIR		0x08000000	/* Transmit DMA threshold */
-#define ISA_SERIAL1_Tx_PREQ		0x10000000	/* Transmit DMA pair req */
-#define ISA_SERIAL1_Tx_MEMERR	0x20000000	/* Transmit DMA memory err */
-#define ISA_SERIAL1_Rx_THIR		0x40000000	/* Receive DMA threshold  */
-#define ISA_SERIAL1_Rx_OVERRUN	0x80000000	/* Receive DMA over-run  */
-
-#define MAX_RING_BLOCKS		128			/* 4096/32 */
-#define MAX_RING_SIZE		4096
-
-/* DMA Input Control Byte */
-#define	DMA_IC_OVRRUN	0x01	/* overrun error */
-#define	DMA_IC_PARERR	0x02	/* parity error */
-#define	DMA_IC_FRMERR	0x04	/* framing error */
-#define	DMA_IC_BRKDET 	0x08	/* a break has arrived */
-#define DMA_IC_VALID	0x80	/* pair is valid */
-
-/* DMA Output Control Byte */
-#define DMA_OC_TxINTR	0x20	/* set Tx intr after processing byte */
-#define DMA_OC_INVALID	0x00	/* invalid pair */
-#define DMA_OC_WTHR		0x40	/* Write byte to THR */
-#define DMA_OC_WMCR		0x80	/* Write byte to MCR */
-#define DMA_OC_DELAY	0xc0	/* time delay before next xmit */
-
-/* ring id's */
-#define RID_SERIAL0_TX	0x4		/* serial port 0, transmit ring buffer */
-#define RID_SERIAL0_RX	0x5		/* serial port 0, receive ring buffer */
-#define RID_SERIAL1_TX	0x6		/* serial port 1, transmit ring buffer */
-#define RID_SERIAL1_RX	0x7		/* serial port 1, receive ring buffer */
-
-#define CLOCK_XIN			22
-#define PRESCALER_DIVISOR	3
-#define CLOCK_ACE			7333333
-
-/*
- * increment the ring offset. One way to do this would be to add b'100000.
- * this would let the offset value roll over automatically when it reaches
- * its maximum value (127). However when we use the offset, we must use
- * the appropriate bits only by masking with 0xfe0.
- * The other option is to shift the offset right by 5 bits and look at its
- * value. Then increment if required and shift back
- * note: 127 * 2^5 = 4064
- */
-#define INC_RING_POINTER(x) \
-	( ((x & 0xffe0) < 4064) ? (x += 32) : 0 )
-
-#endif /* _ASM_SN_SN1_UART16550_H */
diff -Nru a/include/asm-ia64/sn/sn2/addrs.h b/include/asm-ia64/sn/sn2/addrs.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/addrs.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,153 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN2_ADDRS_H
+#define _ASM_IA64_SN_SN2_ADDRS_H
+
+/* McKinley Address Format:
+ *
+ *   4 4       3 3  3 3
+ *   9 8       8 7  6 5             0
+ *  +-+---------+----+--------------+
+ *  |0| Node ID | AS | Node Offset  |
+ *  +-+---------+----+--------------+
+ *
+ *   Node ID: If bit 38 = 1, is ICE, else is SHUB
+ *   AS: Address Space Identifier. Used only if bit 38 = 0.
+ *     b'00: Local Resources and MMR space
+ *           bit 35
+ *               0: Local resources space
+ *                  node id:
+ *                        0: IA64/NT compatibility space
+ *                        2: Local MMR Space
+ *                        4: Local memory, regardless of local node id
+ *               1: Global MMR space
+ *     b'01: GET space.
+ *     b'10: AMO space.
+ *     b'11: Cacheable memory space.
+ *
+ *   NodeOffset: byte offset
+ */
+
+#ifndef __ASSEMBLY__
+typedef union ia64_sn2_pa {
+	struct {
+		unsigned long off  : 36;
+		unsigned long as   : 2;
+		unsigned long nasid: 11;
+		unsigned long fill : 15;
+	} f;
+	unsigned long l;
+	void *p;
+} ia64_sn2_pa_t;
+#endif
+
+#define TO_PHYS_MASK		0x0001ffcfffffffff	/* Note - clear AS bits */
+
+
+/* Regions determined by AS */
+#define LOCAL_MMR_SPACE		0xc000008000000000	/* Local MMR space */
+#define LOCAL_MEM_SPACE		0xc000010000000000	/* Local Memory space */
+#define GLOBAL_MMR_SPACE	0xc000000800000000	/* Global MMR space */
+#define GET_SPACE		0xc000001000000000	/* GET space */
+#define AMO_SPACE		0xc000002000000000	/* AMO space */
+#define CACHEABLE_MEM_SPACE	0xe000003000000000	/* Cacheable memory space */
+#define UNCACHED                0xc000000000000000      /* UnCacheable memory space */
+
+/* SN2 address macros */
+#define NID_SHFT		38
+#define LOCAL_MMR_ADDR(a)	(UNCACHED | LOCAL_MMR_SPACE | (a))
+#define LOCAL_MEM_ADDR(a)	(LOCAL_MEM_SPACE | (a))
+#define REMOTE_ADDR(n,a)	((((unsigned long)(n))<<NID_SHFT) | (a))
+#define GLOBAL_MMR_ADDR(n,a)	(UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
+#define GET_ADDR(n,a)		(GET_SPACE | REMOTE_ADDR(n,a))
+#define AMO_ADDR(n,a)		(UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a))
+#define GLOBAL_MEM_ADDR(n,a)	(CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a))
+
+/* non-II mmr's start at top of big window space (4G) */
+#define BWIN_TOP		0x0000000100000000
+
+/*
+ * general address defines - for code common to SN0/SN1/SN2
+ */
+#define CAC_BASE		CACHEABLE_MEM_SPACE			/* cacheable memory space */
+#define IO_BASE			(UNCACHED | GLOBAL_MMR_SPACE)		/* lower 4G maps II's XIO space */
+#define AMO_BASE		(UNCACHED | AMO_SPACE)			/* fetch & op space */
+#define MSPEC_BASE		AMO_BASE				/* fetch & op space */
+#define UNCAC_BASE		(UNCACHED | CACHEABLE_MEM_SPACE)	/* uncached global memory */
+#define GET_BASE		GET_SPACE				/* momentarily coherent remote mem. */
+#define CALIAS_BASE             LOCAL_CACHEABLE_BASE			/* cached node-local memory */
+#define UALIAS_BASE             (UNCACHED | LOCAL_CACHEABLE_BASE)	/* uncached node-local memory */
+
+#define TO_PHYS(x)              (              ((x) & TO_PHYS_MASK))
+#define TO_CAC(x)               (CAC_BASE    | ((x) & TO_PHYS_MASK))
+#define TO_UNCAC(x)             (UNCAC_BASE  | ((x) & TO_PHYS_MASK))
+#define TO_MSPEC(x)             (MSPEC_BASE  | ((x) & TO_PHYS_MASK))
+#define TO_GET(x)		(GET_BASE    | ((x) & TO_PHYS_MASK))
+#define TO_CALIAS(x)            (CALIAS_BASE | TO_NODE_ADDRSPACE(x))
+#define TO_UALIAS(x)            (UALIAS_BASE | TO_NODE_ADDRSPACE(x))
+#define NODE_SIZE_BITS		36	/* node offset : bits <35:0> */
+#define BWIN_SIZE_BITS		29	/* big window size: 512M */
+#define NASID_BITS		11	/* bits <48:38> */
+#define NASID_BITMASK		(0x7ffULL)
+#define NASID_SHFT		NID_SHFT
+#define NASID_META_BITS		0	/* ???? */
+#define NASID_LOCAL_BITS	7	/* same router as SN1 */
+
+#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
+#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
+#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
+                                        NASID_SHFT) & NASID_BITMASK)
+
+#define CHANGE_NASID(n,x)	({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;})
+
+#ifndef __ASSEMBLY__
+#define NODE_SWIN_BASE(nasid, widget)                                   \
+        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
+        : RAW_NODE_SWIN_BASE(nasid, widget))
+#else
+#define NODE_SWIN_BASE(nasid, widget) \
+     (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
+#define LOCAL_SWIN_BASE(widget) \
+	(UNCACHED | LOCAL_MMR_SPACE | ((UINT64_CAST (widget) << SWIN_SIZE_BITS)))
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The following definitions pertain to the IO special address
+ * space.  They define the location of the big and little windows
+ * of any given node.
+ */
+
+#define BWIN_INDEX_BITS         3
+#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
+#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
+#define BWIN_WIDGET_MASK        0x7
+#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
+#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
+                        (UINT64_CAST (bigwin) << BWIN_SIZE_BITS))
+
+#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
+#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
+
+/*
+ * Verify if addr belongs to large window address of node with "nasid"
+ *
+ *
+ * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
+ * address
+ *
+ *
+ */
+
+#define NODE_BWIN_ADDR(nasid, addr)     \
+                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
+                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
+                                BWIN_SIZE)))
+
+#endif	/* _ASM_IA64_SN_SN2_ADDRS_H */
diff -Nru a/include/asm-ia64/sn/sn2/arch.h b/include/asm-ia64/sn/sn2/arch.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/arch.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,66 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN2_ARCH_H
+#define _ASM_IA64_SN_SN2_ARCH_H
+
+#include <asm/types.h>
+
+
+#define CPUS_PER_NODE           4       /* CPUs on a single hub */
+#define CPUS_PER_SUBNODE        4       /* CPUs on a single hub PI */
+
+
+/*
+ * This is the maximum number of NASIDS that can be present in a system.
+ * (Highest NASID plus one.)
+ */
+#define MAX_NASIDS              2048
+
+
+/*
+ * This is the maximum number of nodes that can be part of a kernel.
+ * Effectively, it's the maximum number of compact node ids (cnodeid_t).
+ * This is not necessarily the same as MAX_NASIDS.
+ */
+#define MAX_COMPACT_NODES       128
+
+/*
+ * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
+ */
+#define	MAX_REGIONS		64
+#define MAX_NONPREMIUM_REGIONS  16
+#define MAX_PREMIUM_REGIONS     MAX_REGIONS
+
+
+/*
+ * MAX_PARITIONS refers to the maximum number of logically defined 
+ * partitions the system can support.
+ */
+#define MAX_PARTITIONS		MAX_REGIONS
+
+
+#define NASID_MASK_BYTES	((MAX_NASIDS + 7) / 8)
+
+
+/*
+ * 1 FSB per SHUB, with up to 4 cpus per FSB.
+ */
+#define NUM_SUBNODES	1
+#define SUBNODE_SHFT	0
+#define SUBNODE_MASK	(0x0 << SUBNODE_SHFT)
+#define LOCALCPU_SHFT	0
+#define LOCALCPU_MASK	(0x3 << LOCALCPU_SHFT)
+#define SUBNODE(slice)	(((slice) & SUBNODE_MASK) >> SUBNODE_SHFT)
+#define LOCALCPU(slice)	(((slice) & LOCALCPU_MASK) >> LOCALCPU_SHFT)
+#define TO_SLICE(subn, local)	(((subn) << SUBNODE_SHFT) | \
+				 ((local) << LOCALCPU_SHFT))
+
+typedef u64 mmr_t;
+
+#endif /* _ASM_IA64_SN_SN2_ARCH_H */
diff -Nru a/include/asm-ia64/sn/sn2/intr.h b/include/asm-ia64/sn/sn2/intr.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/intr.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,25 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN2_INTR_H
+#define _ASM_IA64_SN_SN2_INTR_H
+
+#define SGI_UART_VECTOR (0xe9)
+#define SGI_SHUB_ERROR_VECTOR   (0xea)
+
+// These two IRQ's are used by partitioning.
+#define SGI_XPC_NOTIFY			(0xe7)
+#define SGI_XPART_ACTIVATE		(0x30)
+
+#define IA64_SN2_FIRST_DEVICE_VECTOR	(0x31)
+#define IA64_SN2_LAST_DEVICE_VECTOR	(0xe6)
+
+#define SN2_IRQ_RESERVED        (0x1)
+#define SN2_IRQ_CONNECTED       (0x2)
+
+#endif /* _ASM_IA64_SN_SN2_INTR_H */
diff -Nru a/include/asm-ia64/sn/sn2/mmzone_sn2.h b/include/asm-ia64/sn/sn2/mmzone_sn2.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/mmzone_sn2.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,165 @@
+#ifndef _ASM_IA64_SN_MMZONE_SN2_H
+#define _ASM_IA64_SN_MMZONE_SN2_H
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#include <linux/config.h>
+
+
+/*
+ * SGI SN2 Arch defined values
+ *
+ * 	An SN2 physical address is broken down as follows:
+ *
+ *             +-----------------------------------------+
+ *             |         |      |    |   node offset     |
+ *             | unused  | node | AS |-------------------|
+ *             |         |      |    | cn | clump offset |
+ *             +-----------------------------------------+
+ *              6       4 4    3 3  3 3  3 3            0
+ *              3       9 8    8 7  6 5  4 3            0
+ *
+ *		bits 63-49	Unused - must be zero
+ *		bits 48-38	Node number. Note that some configurations do NOT
+ *				have a node zero.
+ *		bits 37-36	Address space ID. Cached memory has a value of 3 (!!!).
+ *				Chipset & IO addresses have other values.
+ *				  (Yikes!! The hardware folks hate us...)
+ *		bits 35-0	Node offset.
+ *
+ *	The node offset can be further broken down as:
+ *		bits 35-34	Clump (bank) number.
+ *		bits 33-0	Clump (bank) offset.
+ *
+ *	A node consists of up to 4 clumps (banks) of memory. A clump may be empty, or may be
+ *	populated with a single contiguous block of memory starting at clump
+ *	offset 0. The size of the block is (2**n) * 64MB, where 0<n<9.
+ *
+ *	Important notes:
+ *		- IO space addresses are embedded with the range of valid memory addresses.
+ *		- All cached memory addresses have bits 36 & 37 set to 1's.
+ *		- There is no physical address 0.
+ *
+ * NOTE: This file exports symbols prefixed with "PLAT_". Symbols prefixed with
+ *	 "SN_" are intended for internal use only and should not be used in
+ *	 any platform independent code. 
+ *
+ *	 This file is also responsible for exporting the following definitions:
+ *		cnodeid_t	Define a compact node id. 
+ */
+
+typedef signed short cnodeid_t;
+
+#define SN2_BANKS_PER_NODE		4
+#define SN2_NODE_SIZE			(64UL*1024*1024*1024)	/* 64GB per node */
+#define SN2_BANK_SIZE			(SN2_NODE_SIZE/SN2_BANKS_PER_NODE)
+#define SN2_NODE_SHIFT			38
+#define SN2_NODE_MASK			0x7ffUL
+#define SN2_NODE_OFFSET_MASK		(SN2_NODE_SIZE-1)
+#define SN2_NODE_NUMBER(addr)		(((unsigned long)(addr) >> SN2_NODE_SHIFT) & SN2_NODE_MASK)
+#define SN2_NODE_CLUMP_NUMBER(kaddr)	(((unsigned long)(kaddr) >>34) & 3)
+#define SN2_NODE_OFFSET(addr)		(((unsigned long)(addr)) & SN2_NODE_OFFSET_MASK)
+#define SN2_KADDR(nasid, offset)	(((unsigned long)(nasid)<<SN2_NODE_SHIFT) | (offset) | SN2_PAGE_OFFSET)
+#define SN2_PAGE_OFFSET			0xe000003000000000UL      /* Cacheable memory space */
+
+
+#define PLAT_MAX_NODE_NUMBER		2048			/* Maximum node number + 1 */
+#define PLAT_MAX_COMPACT_NODES		128			/* Maximum number of nodes in SSI system */
+
+#define PLAT_MAX_PHYS_MEMORY		(1UL << 49)
+
+
+
+/*
+ * On the SN platforms, a clump is the same as a memory bank.
+ */
+#define PLAT_CLUMPS_PER_NODE		SN2_BANKS_PER_NODE
+#define PLAT_CLUMP_OFFSET(addr)		((unsigned long)(addr) & 0x3ffffffffUL)
+#define PLAT_CLUMPSIZE			(SN2_NODE_SIZE/PLAT_CLUMPS_PER_NODE)
+#define PLAT_MAXCLUMPS			(PLAT_CLUMPS_PER_NODE * PLAT_MAX_COMPACT_NODES)
+
+
+
+/*
+ * PLAT_VALID_MEM_KADDR returns a boolean to indicate if a kaddr is potentially a
+ * valid cacheable identity mapped RAM memory address.
+ * Note that the RAM may or may not actually be present!!
+ */
+#define SN2_VALID_KERN_ADDR_MASK	0xffff003000000000UL
+#define SN2_VALID_KERN_ADDR_VALUE	0xe000003000000000UL
+#define PLAT_VALID_MEM_KADDR(kaddr)	(((unsigned long)(kaddr) & SN2_VALID_KERN_ADDR_MASK) == SN2_VALID_KERN_ADDR_VALUE)
+
+
+
+/*
+ * Memory is conceptually divided into chunks. A chunk is either
+ * completely present, or else the kernel assumes it is completely
+ * absent. Each node consists of a number of possibly contiguous chunks.
+ */
+#define SN2_CHUNKSHIFT			25			/* 32 MB */
+#define SN2_CHUNKSIZE			(1UL << SN2_CHUNKSHIFT)
+#define PLAT_CHUNKNUM(addr)		({unsigned long _p=(unsigned long)(addr);		\
+						(((_p&SN2_NODE_MASK)>>2) | 			\
+						(_p&SN2_NODE_OFFSET_MASK)) >>SN2_CHUNKSHIFT;})
+
+/*
+ * Given a kaddr, find the nid (compact nodeid)
+ */
+#ifdef CONFIG_IA64_SGI_SN_DEBUG
+#define DISCONBUG(kaddr)		panic("DISCONTIG BUG: line %d, %s. kaddr 0x%lx",	 	\
+						__LINE__, __FILE__, (long)(kaddr))
+
+#define KVADDR_TO_NID(kaddr)		({long _ktn=(long)(kaddr);					\
+						kern_addr_valid(_ktn) ? 				\
+						local_node_data->physical_node_map[SN2_NODE_NUMBER(_ktn)] :	\
+						(DISCONBUG(_ktn), 0UL);})
+#else
+#define KVADDR_TO_NID(kaddr)		(local_node_data->physical_node_map[SN2_NODE_NUMBER(kaddr)])
+#endif
+
+
+
+/*
+ * Given a kaddr, find the index into the clump_mem_map_base array of the page struct entry 
+ * for the first page of the clump.
+ */
+#define PLAT_CLUMP_MEM_MAP_INDEX(kaddr)		({long _kmmi=(long)(kaddr);				\
+							KVADDR_TO_NID(_kmmi) * PLAT_CLUMPS_PER_NODE +	\
+							SN2_NODE_CLUMP_NUMBER(_kmmi);})
+
+
+
+/*
+ * Calculate a "goal" value to be passed to __alloc_bootmem_node for allocating structures on
+ * nodes so that they dont alias to the same line in the cache as the previous allocated structure.
+ * This macro takes an address of the end of previous allocation, rounds it to a page boundary & 
+ * changes the node number.
+ */
+#define PLAT_BOOTMEM_ALLOC_GOAL(cnode,kaddr)	SN2_KADDR(PLAT_PXM_TO_PHYS_NODE_NUMBER(nid_to_pxm_map[cnodeid]),       \
+						 (SN2_NODE_OFFSET(kaddr) + PAGE_SIZE - 1) >> PAGE_SHIFT << PAGE_SHIFT)
+
+
+
+
+/*
+ * Convert a proximity domain number (from the ACPI tables) into a physical node number.
+ *	Note: on SN2, the promity domain number is the same as bits [8:1] of the NASID. The following
+ *	algorithm relies on:
+ *		- bit 0 of the NASID for cpu nodes is always 0
+ *		- bits [10:9] of all NASIDs in a partition are always the same
+ *		- hard_smp_processor_id return the SAPIC of the current cpu &
+ *			bits 0..11 contain the NASID.
+ *
+ *	All of this complexity is because MS architectually limited proximity domain numbers to
+ *	8 bits. 
+ */
+
+#define PLAT_PXM_TO_PHYS_NODE_NUMBER(pxm)	(((pxm)<<1) | (hard_smp_processor_id() & 0x300))
+
+#endif /* _ASM_IA64_SN_MMZONE_SN2_H */
diff -Nru a/include/asm-ia64/sn/sn2/shub.h b/include/asm-ia64/sn/sn2/shub.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/shub.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,44 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN2_SHUB_H
+#define _ASM_IA64_SN_SN2_SHUB_H
+
+#include <asm/sn/sn2/shub_mmr.h>		/* shub mmr addresses and formats */
+#include <asm/sn/sn2/shub_md.h>	
+#include <asm/sn/sn2/shubio.h>	
+#ifndef __ASSEMBLY__
+#include <asm/sn/sn2/shub_mmr_t.h>		/* shub mmr struct defines */
+#endif
+
+/*
+ * Junk Bus Address Space
+ *   The junk bus is used to access the PROM, LED's, and UART. It's 
+ *   accessed through the local block MMR space. The data path is
+ *   16 bits wide. This space requires address bits 31-27 to be set, and
+ *   is further divided by address bits 26:15.
+ *   The LED addresses are write-only. To read the LEDs, you need to use
+ *   SH_JUNK_BUS_LED0-3, defined in shub_mmr.h
+ *		
+ */
+#define SH_REAL_JUNK_BUS_LED0           0x7fed00000
+#define SH_REAL_JUNK_BUS_LED1           0x7fed10000
+#define SH_REAL_JUNK_BUS_LED2           0x7fed20000
+#define SH_REAL_JUNK_BUS_LED3           0x7fed30000
+#define SH_JUNK_BUS_UART0               0x7fed40000
+#define SH_JUNK_BUS_UART1               0x7fed40008
+#define SH_JUNK_BUS_UART2               0x7fed40010
+#define SH_JUNK_BUS_UART3               0x7fed40018
+#define SH_JUNK_BUS_UART4               0x7fed40020
+#define SH_JUNK_BUS_UART5               0x7fed40028
+#define SH_JUNK_BUS_UART6               0x7fed40030
+#define SH_JUNK_BUS_UART7               0x7fed40038
+
+#endif /* _ASM_IA64_SN_SN2_SHUB_H */
diff -Nru a/include/asm-ia64/sn/sn2/shub_md.h b/include/asm-ia64/sn/sn2/shub_md.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/shub_md.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,278 @@
+/**************************************************************************
+ *                                                                        *
+ *  Copyright (C) 2001 Silicon Graphics, Inc. All rights reserved.        *
+ *                                                                        *
+ *  These coded instructions, statements, and computer programs  contain  *
+ *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
+ *  are protected by Federal copyright law.  They  may  not be disclosed  *
+ *  to  third  parties  or copied or duplicated in any form, in whole or  *
+ *  in part, without the prior written consent of Silicon Graphics, Inc.  *
+ *                                                                        *
+ **************************************************************************/
+
+#ifndef _SHUB_MD_H
+#define _SHUB_MD_H
+
+/* SN2 supports a mostly-flat address space with 4 CPU-visible, evenly spaced, 
+   contiguous regions, or "software banks".  On SN2, software bank n begins at 
+   addresses n * 16GB, 0 <= n < 4.  Each bank has a 16GB address space.  If 
+   the 4 dimms do not use up this space there will be holes between the 
+   banks.  Even with these holes the whole memory space within a bank is
+   not addressable address space.  The top 1/32 of each bank is directory
+   memory space and is accessible through bist only.
+
+   Physically a SN2 node board contains 2 daughter cards with 8 dimm sockets
+   each.  A total of 16 dimm sockets arranged as 4 "DIMM banks" of 4 dimms 
+   each.  The data is stripped across the 4 memory busses so all dimms within 
+   a dimm bank must have identical capacity dimms.  Memory is increased or 
+   decreased in sets of 4.  Each dimm bank has 2 dimms on each side.
+
+             Physical Dimm Bank layout.
+                  DTR Card0
+                 ------------
+   Dimm Bank 3   |  MemYL3  |   CS 3
+                 |  MemXL3  |
+                 |----------|
+   Dimm Bank 2   |  MemYL2  |   CS 2
+                 |  MemXL2  |
+                 |----------|
+   Dimm Bank 1   |  MemYL1  |   CS 1
+                 |  MemXL1  |
+                 |----------|
+   Dimm Bank 0   |  MemYL0  |   CS 0 
+                 |  MemXL0  |
+                 ------------
+                  |       |
+                  BUS     BUS
+                  XL      YL
+                  |       |
+                 ------------
+                 |   SHUB   |
+                 |    MD    |
+                 ------------
+                  |       |
+                  BUS     BUS
+                  XR      YR
+                  |       |
+                 ------------
+   Dimm Bank 0   |  MemXR0  |   CS 0
+                 |  MemYR0  |
+                 |----------|
+   Dimm Bank 1   |  MemXR1  |   CS 1
+                 |  MemYR1  |
+                 |----------|
+   Dimm Bank 2   |  MemXR2  |   CS 2
+                 |  MemYR2  |
+                 |----------|
+   Dimm Bank 3   |  MemXR3  |   CS 3
+                 |  MemYR3  |
+                 ------------
+                  DTR Card1
+
+   The dimms can be 1 or 2 sided dimms.  The size and bankness is defined  
+   separately for each dimm bank in the sh_[x,y,jnr]_dimm_cfg MMR register.
+
+   Normally software bank 0 would map directly to physical dimm bank 0.  The 
+   software banks can map to the different physical dimm banks via the 
+   DIMM[0-3]_CS field in SH_[x,y,jnr]_DIMM_CFG for each dimm slot.   
+
+   All the PROM's data structures (promlog variables, klconfig, etc.)
+   track memory by the physical dimm bank number.  The kernel usually
+   tracks memory by the software bank number.
+
+ */
+
+
+/* Preprocessor macros */
+#define MD_MEM_BANKS		4
+#define MD_PHYS_BANKS_PER_DIMM  2                  /* dimms may be 2 sided. */
+#define MD_NUM_PHYS_BANKS       (MD_MEM_BANKS * MD_PHYS_BANKS_PER_DIMM)
+#define MD_DIMMS_IN_SLOT	4  /* 4 dimms in each dimm bank.  aka slot */
+
+/* Address bits 35,34 control dimm bank access. */
+#define MD_BANK_SHFT       	34     
+#define MD_BANK_MASK       	(UINT64_CAST 0x3 << MD_BANK_SHFT )
+#define MD_BANK_GET(addr)  	(((addr) & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define MD_BANK_SIZE       	(UINT64_CAST 0x1 << MD_BANK_SHFT ) /* 16 gb */
+#define MD_BANK_OFFSET(_b) 	(UINT64_CAST (_b) << MD_BANK_SHFT)
+
+/*Address bit 12 selects side of dimm if 2bnk dimms present. */
+#define MD_PHYS_BANK_SEL_SHFT   12
+#define MD_PHYS_BANK_SEL_MASK   (UINT64_CAST 0x1 << MD_PHYS_BANK_SEL_SHFT)
+
+/* Address bit 7 determines if data resides on X or Y memory system. 
+ * If addr Bit 7 is set the data resides on Y memory system and
+ * the corresponing directory entry reside on the X. 
+ */
+#define MD_X_OR_Y_SEL_SHFT	7	
+#define MD_X_OR_Y_SEL_MASK	(1 << MD_X_OR_Y_SEL_SHFT)	
+
+/* Address bit 8 determines which directory entry of the pair the address
+ * corresponds to.  If addr Bit 8 is set DirB corresponds to the memory address.
+ */
+#define MD_DIRA_OR_DIRB_SEL_SHFT	8
+#define MD_DIRA_OR_DIRB_SEL_MASK  	(1 << MD_DIRA_OR_DIRB_SEL_SHFT)	
+
+/* Address bit 11 determines if corresponding directory entry resides 
+ * on Left or Right memory bus.  If addr Bit 11 is set the corresponding 
+ * directory entry resides on Right memory bus.
+ */
+#define MD_L_OR_R_SEL_SHFT	11
+#define MD_L_OR_R_SEL_MASK	(1 << MD_L_OR_R_SEL_SHFT)	
+
+/* DRAM sizes. */
+#define MD_SZ_64_Mb		0x0
+#define MD_SZ_128_Mb		0x1
+#define MD_SZ_256_Mb		0x2
+#define MD_SZ_512_Mb		0x3
+#define MD_SZ_1024_Mb		0x4
+#define MD_SZ_2048_Mb	 	0x5
+#define MD_SZ_UNUSED		0x7
+
+#define MD_DIMM_SIZE_BYTES(_size, _2bk) (				 \
+		( (_size) == 7 ? 0 : ( 0x4000000L << (_size)) << (_2bk)))\
+
+#define MD_DIMM_SIZE_MBYTES(_size, _2bk) (				 \
+	 	( (_size) == 7 ? 0 : ( 0x40L << (_size) ) << (_2bk)))  	 \
+
+/* The top 1/32 of each bank is directory memory, and not accessable
+ * via normal reads and writes */
+#define MD_DIMM_USER_SIZE(_size)	((_size) * 31 / 32)
+
+/* Minimum size of a populated bank is 64M (62M usable) */
+#define MIN_BANK_SIZE		MD_DIMM_USER_SIZE((64 * 0x100000))
+#define MIN_BANK_STRING		"62"
+
+
+/*Possible values for FREQ field in sh_[x,y,jnr]_dimm_cfg regs */
+#define MD_DIMM_100_CL2_0 	0x0
+#define MD_DIMM_133_CL2_0 	0x1
+#define MD_DIMM_133_CL2_5 	0x2
+#define MD_DIMM_160_CL2_0 	0x3
+#define MD_DIMM_160_CL2_5 	0x4
+#define MD_DIMM_160_CL3_0 	0x5
+#define MD_DIMM_200_CL2_0 	0x6
+#define MD_DIMM_200_CL2_5 	0x7
+#define MD_DIMM_200_CL3_0 	0x8
+
+/* DIMM_CFG fields */
+#define MD_DIMM_SHFT(_dimm)	((_dimm) << 3)
+#define MD_DIMM_SIZE_MASK(_dimm)					\
+		(SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK << 			\
+		(MD_DIMM_SHFT(_dimm)))
+
+#define MD_DIMM_2BK_MASK(_dimm)						\
+		(SH_JNR_DIMM_CFG_DIMM0_2BK_MASK << 			\
+		MD_DIMM_SHFT(_dimm))
+
+#define MD_DIMM_REV_MASK(_dimm)						\
+		(SH_JNR_DIMM_CFG_DIMM0_REV_MASK << 			\
+		MD_DIMM_SHFT(_dimm))
+
+#define MD_DIMM_CS_MASK(_dimm)						\
+		(SH_JNR_DIMM_CFG_DIMM0_CS_MASK << 			\
+		MD_DIMM_SHFT(_dimm))
+
+#define MD_DIMM_SIZE(_dimm, _cfg)					\
+		(((_cfg) & MD_DIMM_SIZE_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT))
+
+#define MD_DIMM_TWO_SIDED(_dimm,_cfg)					\
+		( ((_cfg) & MD_DIMM_2BK_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT))
+
+#define MD_DIMM_REVERSED(_dimm,_cfg) 					\
+		(((_cfg) & MD_DIMM_REV_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_REV_SHFT))
+
+#define MD_DIMM_CS(_dimm,_cfg)						\
+		(((_cfg) & MD_DIMM_CS_MASK(_dimm))			\
+		>> (MD_DIMM_SHFT(_dimm)+SH_JNR_DIMM_CFG_DIMM0_CS_SHFT))
+
+
+
+/* Macros to set MMRs that must be set identically to others. */
+#define MD_SET_DIMM_CFG(_n, _value) {					\
+		REMOTE_HUB_S(_n, SH_X_DIMM_CFG,_value);			\
+                REMOTE_HUB_S(_n, SH_Y_DIMM_CFG, _value);		\
+                REMOTE_HUB_S(_n, SH_JNR_DIMM_CFG, _value);}
+
+#define MD_SET_DQCT_CFG(_n, _value) {					\
+		REMOTE_HUB_S(_n, SH_X_DQCT_CFG,_value);			\
+		REMOTE_HUB_S(_n, SH_Y_DQCT_CFG,_value); }
+
+#define MD_SET_CFG(_n, _value) {					\
+		REMOTE_HUB_S(_n, SH_X_CFG,_value);			\
+		REMOTE_HUB_S(_n, SH_Y_CFG,_value);} 
+
+#define MD_SET_REFRESH_CONTROL(_n, _value) {				\
+		REMOTE_HUB_S(_n, SH_X_REFRESH_CONTROL, _value);		\
+		REMOTE_HUB_S(_n, SH_Y_REFRESH_CONTROL, _value);}
+
+#define MD_SET_DQ_MMR_DIR_COFIG(_n, _value) {				\
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_CONFIG, _value);	\
+                REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_CONFIG, _value);}
+
+#define MD_SET_PIOWD_DIR_ENTRYS(_n, _value) {				\
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY, _value);\
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY, _value);}
+
+/* 
+ * There are 12 Node Presence MMRs, 4 in each primary DQ and 4 in the
+ * LB.  The data in the left and right DQ MMRs and the LB must match.
+ */
+#define MD_SET_PRESENT_VEC(_n, _vec, _value) {				   \
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
+			 _value);					   \
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRESVEC0+((_vec)*0x10),\
+			 _value);					   \
+		REMOTE_HUB_S(_n, SH_SHUBS_PRESENT0+((_vec)*0x80), _value);}
+/*
+ * There are 16 Privilege Vector MMRs, 8 in each primary DQ.  The data
+ * in the corresponding left and right DQ MMRs must match.  Each MMR
+ * pair is used for a single partition.
+ */
+#define MD_SET_PRI_VEC(_n, _vec, _value) {				  \
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
+			 _value);					  \
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_PRIVEC0+((_vec)*0x10),\
+			 _value);}
+/*
+ * There are 16 Local/Remote MMRs, 8 in each primary DQ.  The data in
+ * the corresponding left and right DQ MMRs must match.  Each MMR pair
+ * is used for a single partition.
+ */
+#define MD_SET_LOC_VEC(_n, _vec, _value) {				\
+		REMOTE_HUB_S(_n, SH_MD_DQLP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
+			 _value);					\
+		REMOTE_HUB_S(_n, SH_MD_DQRP_MMR_DIR_LOCVEC0+((_vec)*0x10),\
+			 _value);}
+
+/* Memory BIST CMDS */
+#define MD_DIMM_INIT_MODE_SET	0x0
+#define MD_DIMM_INIT_REFRESH	0x1
+#define MD_DIMM_INIT_PRECHARGE	0x2
+#define MD_DIMM_INIT_BURST_TERM	0x6
+#define MD_DIMM_INIT_NOP	0x7
+#define MD_DIMM_BIST_READ	0x10
+#define MD_FILL_DIR		0x20
+#define MD_FILL_DATA		0x30
+#define MD_FILL_DIR_ACCESS	0X40
+#define MD_READ_DIR_PAIR	0x50
+#define MD_READ_DIR_TAG		0x60
+
+/* SH_MMRBIST_CTL macros */
+#define MD_BIST_FAIL(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) &		\
+                SH_MMRBIST_CTL_FAIL_MASK)
+
+#define MD_BIST_IN_PROGRESS(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & 	\
+                SH_MMRBIST_CTL_IN_PROGRESS_MASK)
+
+#define MD_BIST_MEM_IDLE(_n); (REMOTE_HUB_L(_n, SH_MMRBIST_CTL) & 	\
+                SH_MMRBIST_CTL_MEM_IDLE_MASK)
+
+/* SH_MMRBIST_ERR macros */
+#define MD_BIST_MISCOMPARE(_n) (REMOTE_HUB_L(_n, SH_MMRBIST_ERR) &	\
+		SH_MMRBIST_ERR_DETECTED_MASK)
+
+#endif	/* _SHUB_MD_H */
diff -Nru a/include/asm-ia64/sn/sn2/shub_mmr.h b/include/asm-ia64/sn/sn2/shub_mmr.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/shub_mmr.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,31597 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_H
+#define _ASM_IA64_SN_SN2_SHUB_MMR_H
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_BINIT_CONTROL"                    */
+/*                          FSB BINIT# Control                          */
+/* ==================================================================== */
+
+#define SH_FSB_BINIT_CONTROL                     0x0000000120010000
+#define SH_FSB_BINIT_CONTROL_MASK                0x0000000000000001
+#define SH_FSB_BINIT_CONTROL_INIT                0x0000000000000000
+
+/*   SH_FSB_BINIT_CONTROL_BINIT                                         */
+/*   Description:  Assert the FSB's BINIT# Signal                       */
+#define SH_FSB_BINIT_CONTROL_BINIT_SHFT          0
+#define SH_FSB_BINIT_CONTROL_BINIT_MASK          0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_RESET_CONTROL"                    */
+/*                          FSB Reset Control                           */
+/* ==================================================================== */
+
+#define SH_FSB_RESET_CONTROL                     0x0000000120010080
+#define SH_FSB_RESET_CONTROL_MASK                0x0000000000000001
+#define SH_FSB_RESET_CONTROL_INIT                0x0000000000000000
+
+/*   SH_FSB_RESET_CONTROL_RESET                                         */
+/*   Description:  Assert the FSB's RESET# Signal                       */
+#define SH_FSB_RESET_CONTROL_RESET_SHFT          0
+#define SH_FSB_RESET_CONTROL_RESET_MASK          0x0000000000000001
+
+/* ==================================================================== */
+/*                Register "SH_FSB_SYSTEM_AGENT_CONFIG"                 */
+/*                    FSB System Agent Configuration                    */
+/* ==================================================================== */
+
+#define SH_FSB_SYSTEM_AGENT_CONFIG               0x0000000120010100
+#define SH_FSB_SYSTEM_AGENT_CONFIG_MASK          0x00003fff0187fff9
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INIT          0x0000000000000000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN                            */
+/*   Description:  RCNT/SCNT Assertion Enabled                          */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_SHFT 0
+#define SH_FSB_SYSTEM_AGENT_CONFIG_RCNT_SCNT_EN_MASK 0x0000000000000001
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN                          */
+/*   Description:  BERR Assertion Enabled for Bus Errors                */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_SHFT 3
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_ASSERT_EN_MASK 0x0000000000000008
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN                        */
+/*   Description:  BERR Sampling Enabled                                */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_SHFT 4
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BERR_SAMPLING_EN_MASK 0x0000000000000010
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN                         */
+/*   Description:  BINIT Assertion Enabled                              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_SHFT 5
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_ASSERT_EN_MASK 0x0000000000000020
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN                       */
+/*   Description:  stutter FSB request assertion                        */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_SHFT 6
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BNR_THROTTLING_EN_MASK 0x0000000000000040
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN                           */
+/*   Description:  use short duration hang timeout                      */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_SHFT 7
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SHORT_HANG_EN_MASK 0x0000000000000080
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA                           */
+/*   Description:  Interrupt Acknowledge Response Data                  */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_SHFT 8
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_RSP_DATA_MASK 0x000000000000ff00
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP                            */
+/*   Description:  IO Transaction Response                              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_SHFT 16
+#define SH_FSB_SYSTEM_AGENT_CONFIG_IO_TRANS_RSP_MASK 0x0000000000010000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP                          */
+/*   Description:  External Task Priority Register (xTPR) Transaction   */
+/*  Response                                                            */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_SHFT 17
+#define SH_FSB_SYSTEM_AGENT_CONFIG_XTPR_TRANS_RSP_MASK 0x0000000000020000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP                          */
+/*   Description:  Interrupt Acknowledge Transaction Response           */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_SHFT 18
+#define SH_FSB_SYSTEM_AGENT_CONFIG_INTA_TRANS_RSP_MASK 0x0000000000040000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_TDOT                                    */
+/*   Description:  Throttle Data-bus Ownership Transitions              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_SHFT     23
+#define SH_FSB_SYSTEM_AGENT_CONFIG_TDOT_MASK     0x0000000000800000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN                        */
+/*   Description:  serialize processor transactions                     */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_SHFT 24
+#define SH_FSB_SYSTEM_AGENT_CONFIG_SERIALIZE_FSB_EN_MASK 0x0000000001000000
+
+/*   SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES                     */
+/*   Description:  FSB error binit enables                              */
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_SHFT 32
+#define SH_FSB_SYSTEM_AGENT_CONFIG_BINIT_EVENT_ENABLES_MASK 0x00003fff00000000
+
+/* ==================================================================== */
+/*                     Register "SH_FSB_VGA_REMAP"                      */
+/*                     FSB VGA Address Space Remap                      */
+/* ==================================================================== */
+
+#define SH_FSB_VGA_REMAP                         0x0000000120010180
+#define SH_FSB_VGA_REMAP_MASK                    0x4001fffffffe0000
+#define SH_FSB_VGA_REMAP_INIT                    0x0000000000000000
+
+/*   SH_FSB_VGA_REMAP_OFFSET                                            */
+/*   Description:  VGA Remap Node Offset                                */
+#define SH_FSB_VGA_REMAP_OFFSET_SHFT             17
+#define SH_FSB_VGA_REMAP_OFFSET_MASK             0x0000000ffffe0000
+
+/*   SH_FSB_VGA_REMAP_ASID                                              */
+/*   Description:  VGA Remap Address Space ID                           */
+#define SH_FSB_VGA_REMAP_ASID_SHFT               36
+#define SH_FSB_VGA_REMAP_ASID_MASK               0x0000003000000000
+
+/*   SH_FSB_VGA_REMAP_NID                                               */
+/*   Description:  VGA Remap Node ID                                    */
+#define SH_FSB_VGA_REMAP_NID_SHFT                38
+#define SH_FSB_VGA_REMAP_NID_MASK                0x0001ffc000000000
+
+/*   SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED                             */
+/*   Description:  VGA Remapping Enabled                                */
+#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_SHFT 62
+#define SH_FSB_VGA_REMAP_VGA_REMAPPING_ENABLED_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_FSB_RESET_STATUS"                    */
+/*                           FSB Reset Status                           */
+/* ==================================================================== */
+
+#define SH_FSB_RESET_STATUS                      0x0000000120020000
+#define SH_FSB_RESET_STATUS_MASK                 0x0000000000000001
+#define SH_FSB_RESET_STATUS_INIT                 0x0000000000000000
+
+/*   SH_FSB_RESET_STATUS_RESET_IN_PROGRESS                              */
+/*   Description:  Reset in Progress                                    */
+#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_SHFT 0
+#define SH_FSB_RESET_STATUS_RESET_IN_PROGRESS_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*               Register "SH_FSB_SYMMETRIC_AGENT_STATUS"               */
+/*                      FSB Symmetric Agent Status                      */
+/* ==================================================================== */
+
+#define SH_FSB_SYMMETRIC_AGENT_STATUS            0x0000000120020080
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_MASK       0x0000000000000007
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_INIT       0x0000000000000000
+
+/*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE                         */
+/*   Description:  CPU 0 Active.                                        */
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_SHFT 0
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_0_ACTIVE_MASK 0x0000000000000001
+
+/*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE                         */
+/*   Description:  CPU 1 Active.                                        */
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_SHFT 1
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPU_1_ACTIVE_MASK 0x0000000000000002
+
+/*   SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY                           */
+/*   Description:  The Processors are Ready                             */
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_SHFT 2
+#define SH_FSB_SYMMETRIC_AGENT_STATUS_CPUS_READY_MASK 0x0000000000000004
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_0"                   */
+/*                Graphics-write Credit Count for CPU 0                 */
+/* ==================================================================== */
+
+#define SH_GFX_CREDIT_COUNT_0                    0x0000000120030000
+#define SH_GFX_CREDIT_COUNT_0_MASK               0x80000000000fffff
+#define SH_GFX_CREDIT_COUNT_0_INIT               0x000000000000003f
+
+/*   SH_GFX_CREDIT_COUNT_0_COUNT                                        */
+/*   Description:  Credit Count                                         */
+#define SH_GFX_CREDIT_COUNT_0_COUNT_SHFT         0
+#define SH_GFX_CREDIT_COUNT_0_COUNT_MASK         0x00000000000fffff
+
+/*   SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE                              */
+/*   Description:  Reset GFX state                                      */
+#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_SHFT 63
+#define SH_GFX_CREDIT_COUNT_0_RESET_GFX_STATE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_1"                   */
+/*                Graphics-write Credit Count for CPU 1                 */
+/* ==================================================================== */
+
+#define SH_GFX_CREDIT_COUNT_1                    0x0000000120030080
+#define SH_GFX_CREDIT_COUNT_1_MASK               0x80000000000fffff
+#define SH_GFX_CREDIT_COUNT_1_INIT               0x000000000000003f
+
+/*   SH_GFX_CREDIT_COUNT_1_COUNT                                        */
+/*   Description:  Credit Count                                         */
+#define SH_GFX_CREDIT_COUNT_1_COUNT_SHFT         0
+#define SH_GFX_CREDIT_COUNT_1_COUNT_MASK         0x00000000000fffff
+
+/*   SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE                              */
+/*   Description:  Reset GFX state                                      */
+#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_SHFT 63
+#define SH_GFX_CREDIT_COUNT_1_RESET_GFX_STATE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_0"                    */
+/*         Graphics credit mode amd message ordering for CPU 0          */
+/* ==================================================================== */
+
+#define SH_GFX_MODE_CNTRL_0                      0x0000000120030100
+#define SH_GFX_MODE_CNTRL_0_MASK                 0x0000000000000007
+#define SH_GFX_MODE_CNTRL_0_INIT                 0x0000000000000003
+
+/*   SH_GFX_MODE_CNTRL_0_DWORD_CREDITS                                  */
+/*   Description:  GFX credits are tracked by D-words                   */
+#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_SHFT   0
+#define SH_GFX_MODE_CNTRL_0_DWORD_CREDITS_MASK   0x0000000000000001
+
+/*   SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS                             */
+/*   Description:  GFX credits are tracked by D-words and messages      */
+#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_SHFT 1
+#define SH_GFX_MODE_CNTRL_0_MIXED_MODE_CREDITS_MASK 0x0000000000000002
+
+/*   SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING                               */
+/*   Description:  GFX message routing order                            */
+#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_SHFT 2
+#define SH_GFX_MODE_CNTRL_0_RELAXED_ORDERING_MASK 0x0000000000000004
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_1"                    */
+/*         Graphics credit mode amd message ordering for CPU 1          */
+/* ==================================================================== */
+
+#define SH_GFX_MODE_CNTRL_1                      0x0000000120030180
+#define SH_GFX_MODE_CNTRL_1_MASK                 0x0000000000000007
+#define SH_GFX_MODE_CNTRL_1_INIT                 0x0000000000000003
+
+/*   SH_GFX_MODE_CNTRL_1_DWORD_CREDITS                                  */
+/*   Description:  GFX credits are tracked by D-words                   */
+#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_SHFT   0
+#define SH_GFX_MODE_CNTRL_1_DWORD_CREDITS_MASK   0x0000000000000001
+
+/*   SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS                             */
+/*   Description:  GFX credits are tracked by D-words and messages      */
+#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_SHFT 1
+#define SH_GFX_MODE_CNTRL_1_MIXED_MODE_CREDITS_MASK 0x0000000000000002
+
+/*   SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING                               */
+/*   Description:  GFX message routing order                            */
+#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_SHFT 2
+#define SH_GFX_MODE_CNTRL_1_RELAXED_ORDERING_MASK 0x0000000000000004
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_0"                 */
+/*              Graphics-write Skid Credit Count for CPU 0              */
+/* ==================================================================== */
+
+#define SH_GFX_SKID_CREDIT_COUNT_0               0x0000000120030200
+#define SH_GFX_SKID_CREDIT_COUNT_0_MASK          0x00000000000fffff
+#define SH_GFX_SKID_CREDIT_COUNT_0_INIT          0x0000000000000030
+
+/*   SH_GFX_SKID_CREDIT_COUNT_0_SKID                                    */
+/*   Description:  Skid Credit Count                                    */
+#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_SHFT     0
+#define SH_GFX_SKID_CREDIT_COUNT_0_SKID_MASK     0x00000000000fffff
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_1"                 */
+/*              Graphics-write Skid Credit Count for CPU 1              */
+/* ==================================================================== */
+
+#define SH_GFX_SKID_CREDIT_COUNT_1               0x0000000120030280
+#define SH_GFX_SKID_CREDIT_COUNT_1_MASK          0x00000000000fffff
+#define SH_GFX_SKID_CREDIT_COUNT_1_INIT          0x0000000000000030
+
+/*   SH_GFX_SKID_CREDIT_COUNT_1_SKID                                    */
+/*   Description:  Skid Credit Count                                    */
+#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_SHFT     0
+#define SH_GFX_SKID_CREDIT_COUNT_1_SKID_MASK     0x00000000000fffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_0"                    */
+/*                 Graphics-write Stall Limit for CPU 0                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_LIMIT_0                     0x0000000120030300
+#define SH_GFX_STALL_LIMIT_0_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_LIMIT_0_INIT                0x0000000000010000
+
+/*   SH_GFX_STALL_LIMIT_0_LIMIT                                         */
+/*   Description:  Graphics Stall Limit for CPU 0                       */
+#define SH_GFX_STALL_LIMIT_0_LIMIT_SHFT          0
+#define SH_GFX_STALL_LIMIT_0_LIMIT_MASK          0x0000000003ffffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_1"                    */
+/*                 Graphics-write Stall Limit for CPU 1                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_LIMIT_1                     0x0000000120030380
+#define SH_GFX_STALL_LIMIT_1_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_LIMIT_1_INIT                0x0000000000010000
+
+/*   SH_GFX_STALL_LIMIT_1_LIMIT                                         */
+/*   Description:  Graphics Stall Limit for CPU 1                       */
+#define SH_GFX_STALL_LIMIT_1_LIMIT_SHFT          0
+#define SH_GFX_STALL_LIMIT_1_LIMIT_MASK          0x0000000003ffffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_0"                    */
+/*                 Graphics-write Stall Timer for CPU 0                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_TIMER_0                     0x0000000120030400
+#define SH_GFX_STALL_TIMER_0_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_TIMER_0_INIT                0x0000000000000000
+
+/*   SH_GFX_STALL_TIMER_0_TIMER_VALUE                                   */
+/*   Description:  Timer Value                                          */
+#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_SHFT    0
+#define SH_GFX_STALL_TIMER_0_TIMER_VALUE_MASK    0x0000000003ffffff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_1"                    */
+/*                 Graphics-write Stall Timer for CPU 1                 */
+/* ==================================================================== */
+
+#define SH_GFX_STALL_TIMER_1                     0x0000000120030480
+#define SH_GFX_STALL_TIMER_1_MASK                0x0000000003ffffff
+#define SH_GFX_STALL_TIMER_1_INIT                0x0000000000000000
+
+/*   SH_GFX_STALL_TIMER_1_TIMER_VALUE                                   */
+/*   Description:  Timer Value                                          */
+#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_SHFT    0
+#define SH_GFX_STALL_TIMER_1_TIMER_VALUE_MASK    0x0000000003ffffff
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_0"                      */
+/*                   Graphics-write Window for CPU 0                    */
+/* ==================================================================== */
+
+#define SH_GFX_WINDOW_0                          0x0000000120030500
+#define SH_GFX_WINDOW_0_MASK                     0x8000000fff000000
+#define SH_GFX_WINDOW_0_INIT                     0x0000000000000000
+
+/*   SH_GFX_WINDOW_0_BASE_ADDR                                          */
+/*   Description:  Base Address for CPU 0's 16 MB Graphics Window       */
+#define SH_GFX_WINDOW_0_BASE_ADDR_SHFT           24
+#define SH_GFX_WINDOW_0_BASE_ADDR_MASK           0x0000000fff000000
+
+/*   SH_GFX_WINDOW_0_GFX_WINDOW_EN                                      */
+/*   Description:  Graphics Window Enabled                              */
+#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_SHFT       63
+#define SH_GFX_WINDOW_0_GFX_WINDOW_EN_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_1"                      */
+/*                   Graphics-write Window for CPU 1                    */
+/* ==================================================================== */
+
+#define SH_GFX_WINDOW_1                          0x0000000120030580
+#define SH_GFX_WINDOW_1_MASK                     0x8000000fff000000
+#define SH_GFX_WINDOW_1_INIT                     0x0000000000000000
+
+/*   SH_GFX_WINDOW_1_BASE_ADDR                                          */
+/*   Description:  Base Address for CPU 1's 16 MB Graphics Window       */
+#define SH_GFX_WINDOW_1_BASE_ADDR_SHFT           24
+#define SH_GFX_WINDOW_1_BASE_ADDR_MASK           0x0000000fff000000
+
+/*   SH_GFX_WINDOW_1_GFX_WINDOW_EN                                      */
+/*   Description:  Graphics Window Enabled                              */
+#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_SHFT       63
+#define SH_GFX_WINDOW_1_GFX_WINDOW_EN_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
+/*               Graphics-write Interrupt Limit for CPU 0               */
+/* ==================================================================== */
+
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0           0x0000000120030600
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_MASK      0x00000000000000ff
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INIT      0x0000000000000040
+
+/*   SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT               */
+/*   Description:  GFX Interrupt Timer Limit                            */
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_SHFT 0
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_0_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
+/*               Graphics-write Interrupt Limit for CPU 1               */
+/* ==================================================================== */
+
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1           0x0000000120030680
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_MASK      0x00000000000000ff
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INIT      0x0000000000000040
+
+/*   SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT               */
+/*   Description:  GFX Interrupt Timer Limit                            */
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_SHFT 0
+#define SH_GFX_INTERRUPT_TIMER_LIMIT_1_INTERRUPT_TIMER_LIMIT_MASK 0x00000000000000ff
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_0"                   */
+/*                   Graphics Write Status for CPU 0                    */
+/* ==================================================================== */
+
+#define SH_GFX_WRITE_STATUS_0                    0x0000000120040000
+#define SH_GFX_WRITE_STATUS_0_MASK               0x8000000000000001
+#define SH_GFX_WRITE_STATUS_0_INIT               0x0000000000000000
+
+/*   SH_GFX_WRITE_STATUS_0_BUSY                                         */
+/*   Description:  Busy                                                 */
+#define SH_GFX_WRITE_STATUS_0_BUSY_SHFT          0
+#define SH_GFX_WRITE_STATUS_0_BUSY_MASK          0x0000000000000001
+
+/*   SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL                          */
+/*   Description:  Re-enable GFX stall logic for this processor         */
+#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_SHFT 63
+#define SH_GFX_WRITE_STATUS_0_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_1"                   */
+/*                   Graphics Write Status for CPU 1                    */
+/* ==================================================================== */
+
+#define SH_GFX_WRITE_STATUS_1                    0x0000000120040080
+#define SH_GFX_WRITE_STATUS_1_MASK               0x8000000000000001
+#define SH_GFX_WRITE_STATUS_1_INIT               0x0000000000000000
+
+/*   SH_GFX_WRITE_STATUS_1_BUSY                                         */
+/*   Description:  Busy                                                 */
+#define SH_GFX_WRITE_STATUS_1_BUSY_SHFT          0
+#define SH_GFX_WRITE_STATUS_1_BUSY_MASK          0x0000000000000001
+
+/*   SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL                          */
+/*   Description:  Re-enable GFX stall logic for this processor         */
+#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_SHFT 63
+#define SH_GFX_WRITE_STATUS_1_RE_ENABLE_GFX_STALL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT0"                         */
+/*                    SHub II Interrupt 0 Registers                     */
+/* ==================================================================== */
+
+#define SH_II_INT0                               0x0000000110000000
+#define SH_II_INT0_MASK                          0x00000000000001ff
+#define SH_II_INT0_INIT                          0x0000000000000000
+
+/*   SH_II_INT0_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_II_INT0_IDX_SHFT                      0
+#define SH_II_INT0_IDX_MASK                      0x00000000000000ff
+
+/*   SH_II_INT0_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_II_INT0_SEND_SHFT                     8
+#define SH_II_INT0_SEND_MASK                     0x0000000000000100
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_CONFIG"                     */
+/*                 SHub II Interrupt 0 Config Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT0_CONFIG                        0x0000000110000080
+#define SH_II_INT0_CONFIG_MASK                   0x0003ffffffefffff
+#define SH_II_INT0_CONFIG_INIT                   0x0000000000000000
+
+/*   SH_II_INT0_CONFIG_TYPE                                             */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_II_INT0_CONFIG_TYPE_SHFT              0
+#define SH_II_INT0_CONFIG_TYPE_MASK              0x0000000000000007
+
+/*   SH_II_INT0_CONFIG_AGT                                              */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_II_INT0_CONFIG_AGT_SHFT               3
+#define SH_II_INT0_CONFIG_AGT_MASK               0x0000000000000008
+
+/*   SH_II_INT0_CONFIG_PID                                              */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_II_INT0_CONFIG_PID_SHFT               4
+#define SH_II_INT0_CONFIG_PID_MASK               0x00000000000ffff0
+
+/*   SH_II_INT0_CONFIG_BASE                                             */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_II_INT0_CONFIG_BASE_SHFT              21
+#define SH_II_INT0_CONFIG_BASE_MASK              0x0003ffffffe00000
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_ENABLE"                     */
+/*                 SHub II Interrupt 0 Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT0_ENABLE                        0x0000000110000200
+#define SH_II_INT0_ENABLE_MASK                   0x0000000000000001
+#define SH_II_INT0_ENABLE_INIT                   0x0000000000000000
+
+/*   SH_II_INT0_ENABLE_II_ENABLE                                        */
+/*   Description:  Enable II Interrupt                                  */
+#define SH_II_INT0_ENABLE_II_ENABLE_SHFT         0
+#define SH_II_INT0_ENABLE_II_ENABLE_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT1"                         */
+/*                    SHub II Interrupt 1 Registers                     */
+/* ==================================================================== */
+
+#define SH_II_INT1                               0x0000000110000100
+#define SH_II_INT1_MASK                          0x00000000000001ff
+#define SH_II_INT1_INIT                          0x0000000000000000
+
+/*   SH_II_INT1_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_II_INT1_IDX_SHFT                      0
+#define SH_II_INT1_IDX_MASK                      0x00000000000000ff
+
+/*   SH_II_INT1_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_II_INT1_SEND_SHFT                     8
+#define SH_II_INT1_SEND_MASK                     0x0000000000000100
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_CONFIG"                     */
+/*                 SHub II Interrupt 1 Config Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT1_CONFIG                        0x0000000110000180
+#define SH_II_INT1_CONFIG_MASK                   0x0003ffffffefffff
+#define SH_II_INT1_CONFIG_INIT                   0x0000000000000000
+
+/*   SH_II_INT1_CONFIG_TYPE                                             */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_II_INT1_CONFIG_TYPE_SHFT              0
+#define SH_II_INT1_CONFIG_TYPE_MASK              0x0000000000000007
+
+/*   SH_II_INT1_CONFIG_AGT                                              */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_II_INT1_CONFIG_AGT_SHFT               3
+#define SH_II_INT1_CONFIG_AGT_MASK               0x0000000000000008
+
+/*   SH_II_INT1_CONFIG_PID                                              */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_II_INT1_CONFIG_PID_SHFT               4
+#define SH_II_INT1_CONFIG_PID_MASK               0x00000000000ffff0
+
+/*   SH_II_INT1_CONFIG_BASE                                             */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_II_INT1_CONFIG_BASE_SHFT              21
+#define SH_II_INT1_CONFIG_BASE_MASK              0x0003ffffffe00000
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_ENABLE"                     */
+/*                 SHub II Interrupt 1 Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_II_INT1_ENABLE                        0x0000000110000280
+#define SH_II_INT1_ENABLE_MASK                   0x0000000000000001
+#define SH_II_INT1_ENABLE_INIT                   0x0000000000000000
+
+/*   SH_II_INT1_ENABLE_II_ENABLE                                        */
+/*   Description:  Enable II 1 Interrupt                                */
+#define SH_II_INT1_ENABLE_II_ENABLE_SHFT         0
+#define SH_II_INT1_ENABLE_II_ENABLE_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_INT_NODE_ID_CONFIG"                   */
+/*                 SHub Interrupt Node ID Configuration                 */
+/* ==================================================================== */
+
+#define SH_INT_NODE_ID_CONFIG                    0x0000000110000300
+#define SH_INT_NODE_ID_CONFIG_MASK               0x0000000000000fff
+#define SH_INT_NODE_ID_CONFIG_INIT               0x0000000000000000
+
+/*   SH_INT_NODE_ID_CONFIG_NODE_ID                                      */
+/*   Description:  Node ID for interrupt messages                       */
+#define SH_INT_NODE_ID_CONFIG_NODE_ID_SHFT       0
+#define SH_INT_NODE_ID_CONFIG_NODE_ID_MASK       0x00000000000007ff
+
+/*   SH_INT_NODE_ID_CONFIG_ID_SEL                                       */
+/*   Description:  Select node id for interrupt messages                */
+#define SH_INT_NODE_ID_CONFIG_ID_SEL_SHFT        11
+#define SH_INT_NODE_ID_CONFIG_ID_SEL_MASK        0x0000000000000800
+
+/* ==================================================================== */
+/*                        Register "SH_IPI_INT"                         */
+/*               SHub Inter-Processor Interrupt Registers               */
+/* ==================================================================== */
+
+#define SH_IPI_INT                               0x0000000110000380
+#define SH_IPI_INT_MASK                          0x8ff3ffffffefffff
+#define SH_IPI_INT_INIT                          0x0000000000000000
+
+/*   SH_IPI_INT_TYPE                                                    */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_IPI_INT_TYPE_SHFT                     0
+#define SH_IPI_INT_TYPE_MASK                     0x0000000000000007
+
+/*   SH_IPI_INT_AGT                                                     */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_IPI_INT_AGT_SHFT                      3
+#define SH_IPI_INT_AGT_MASK                      0x0000000000000008
+
+/*   SH_IPI_INT_PID                                                     */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_IPI_INT_PID_SHFT                      4
+#define SH_IPI_INT_PID_MASK                      0x00000000000ffff0
+
+/*   SH_IPI_INT_BASE                                                    */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_IPI_INT_BASE_SHFT                     21
+#define SH_IPI_INT_BASE_MASK                     0x0003ffffffe00000
+
+/*   SH_IPI_INT_IDX                                                     */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_IPI_INT_IDX_SHFT                      52
+#define SH_IPI_INT_IDX_MASK                      0x0ff0000000000000
+
+/*   SH_IPI_INT_SEND                                                    */
+/*   Description:  Send Interrupt Message to PI, This generates a puls  */
+#define SH_IPI_INT_SEND_SHFT                     63
+#define SH_IPI_INT_SEND_MASK                     0x8000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_IPI_INT_ENABLE"                     */
+/*           SHub Inter-Processor Interrupt Enable Registers            */
+/* ==================================================================== */
+
+#define SH_IPI_INT_ENABLE                        0x0000000110000400
+#define SH_IPI_INT_ENABLE_MASK                   0x0000000000000001
+#define SH_IPI_INT_ENABLE_INIT                   0x0000000000000000
+
+/*   SH_IPI_INT_ENABLE_PIO_ENABLE                                       */
+/*   Description:  Enable PIO Interrupt                                 */
+#define SH_IPI_INT_ENABLE_PIO_ENABLE_SHFT        0
+#define SH_IPI_INT_ENABLE_PIO_ENABLE_MASK        0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_CONFIG"                    */
+/*                   SHub Local Interrupt 0 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT0_CONFIG                     0x0000000110000480
+#define SH_LOCAL_INT0_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT0_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT0_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT0_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT0_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT0_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT0_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT0_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT0_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT0_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT0_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT0_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT0_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT0_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT0_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT0_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT0_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_ENABLE"                    */
+/*                    SHub Local Interrupt 0 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT0_ENABLE                     0x0000000110000500
+#define SH_LOCAL_INT0_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT0_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT0_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT0_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT0_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT0_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT0_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT0_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT0_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT0_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT0_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT0_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT0_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT0_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT0_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT0_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT0_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT0_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT0_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT0_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT0_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT0_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT0_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT0_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT0_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT0_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT0_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT0_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT0_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT0_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_CONFIG"                    */
+/*                   SHub Local Interrupt 1 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT1_CONFIG                     0x0000000110000580
+#define SH_LOCAL_INT1_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT1_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT1_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT1_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT1_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT1_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT1_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT1_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT1_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT1_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT1_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT1_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT1_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT1_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT1_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT1_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT1_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_ENABLE"                    */
+/*                    SHub Local Interrupt 1 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT1_ENABLE                     0x0000000110000600
+#define SH_LOCAL_INT1_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT1_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT1_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT1_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT1_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT1_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT1_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT1_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT1_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT1_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT1_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT1_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT1_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT1_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT1_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT1_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT1_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT1_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT1_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT1_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT1_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT1_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT1_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT1_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT1_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT1_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT1_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT1_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT1_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT1_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT1_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT1_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT1_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_CONFIG"                    */
+/*                   SHub Local Interrupt 2 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT2_CONFIG                     0x0000000110000680
+#define SH_LOCAL_INT2_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT2_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT2_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT2_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT2_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT2_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT2_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT2_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT2_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT2_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT2_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT2_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT2_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT2_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT2_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT2_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT2_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_ENABLE"                    */
+/*                    SHub Local Interrupt 2 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT2_ENABLE                     0x0000000110000700
+#define SH_LOCAL_INT2_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT2_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT2_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT2_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT2_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT2_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT2_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT2_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT2_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT2_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT2_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT2_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT2_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT2_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT2_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT2_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT2_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT2_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT2_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT2_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT2_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT2_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT2_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT2_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT2_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT2_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT2_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT2_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT2_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT2_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT2_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT2_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT2_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_CONFIG"                    */
+/*                   SHub Local Interrupt 3 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT3_CONFIG                     0x0000000110000780
+#define SH_LOCAL_INT3_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT3_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT3_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT3_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT3_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT3_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT3_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT3_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT3_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT3_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT3_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT3_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT3_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT3_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT3_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT3_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT3_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_ENABLE"                    */
+/*                    SHub Local Interrupt 3 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT3_ENABLE                     0x0000000110000800
+#define SH_LOCAL_INT3_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT3_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT3_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT3_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT3_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT3_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT3_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT3_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT3_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT3_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT3_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT3_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT3_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT3_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT3_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT3_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT3_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT3_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT3_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT3_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT3_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT3_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT3_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT3_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT3_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT3_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT3_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT3_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT3_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT3_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT3_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT3_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT3_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_CONFIG"                    */
+/*                   SHub Local Interrupt 4 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT4_CONFIG                     0x0000000110000880
+#define SH_LOCAL_INT4_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT4_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT4_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT4_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT4_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT4_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT4_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT4_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT4_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT4_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT4_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT4_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT4_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT4_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT4_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT4_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT4_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_ENABLE"                    */
+/*                    SHub Local Interrupt 4 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT4_ENABLE                     0x0000000110000900
+#define SH_LOCAL_INT4_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT4_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT4_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT4_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT4_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT4_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT4_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT4_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT4_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT4_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT4_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT4_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT4_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT4_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT4_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT4_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT4_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT4_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT4_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT4_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT4_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT4_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT4_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT4_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT4_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT4_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT4_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT4_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT4_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT4_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT4_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT4_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT4_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_CONFIG"                    */
+/*                   SHub Local Interrupt 5 Registers                   */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT5_CONFIG                     0x0000000110000980
+#define SH_LOCAL_INT5_CONFIG_MASK                0x0ff3ffffffefffff
+#define SH_LOCAL_INT5_CONFIG_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT5_CONFIG_TYPE                                          */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_LOCAL_INT5_CONFIG_TYPE_SHFT           0
+#define SH_LOCAL_INT5_CONFIG_TYPE_MASK           0x0000000000000007
+
+/*   SH_LOCAL_INT5_CONFIG_AGT                                           */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_LOCAL_INT5_CONFIG_AGT_SHFT            3
+#define SH_LOCAL_INT5_CONFIG_AGT_MASK            0x0000000000000008
+
+/*   SH_LOCAL_INT5_CONFIG_PID                                           */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_LOCAL_INT5_CONFIG_PID_SHFT            4
+#define SH_LOCAL_INT5_CONFIG_PID_MASK            0x00000000000ffff0
+
+/*   SH_LOCAL_INT5_CONFIG_BASE                                          */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_LOCAL_INT5_CONFIG_BASE_SHFT           21
+#define SH_LOCAL_INT5_CONFIG_BASE_MASK           0x0003ffffffe00000
+
+/*   SH_LOCAL_INT5_CONFIG_IDX                                           */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_LOCAL_INT5_CONFIG_IDX_SHFT            52
+#define SH_LOCAL_INT5_CONFIG_IDX_MASK            0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_ENABLE"                    */
+/*                    SHub Local Interrupt 5 Enable                     */
+/* ==================================================================== */
+
+#define SH_LOCAL_INT5_ENABLE                     0x0000000110000a00
+#define SH_LOCAL_INT5_ENABLE_MASK                0x000000000000f7ff
+#define SH_LOCAL_INT5_ENABLE_INIT                0x0000000000000000
+
+/*   SH_LOCAL_INT5_ENABLE_PI_HW_INT                                     */
+/*   Description:  Enable PI Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_SHFT      0
+#define SH_LOCAL_INT5_ENABLE_PI_HW_INT_MASK      0x0000000000000001
+
+/*   SH_LOCAL_INT5_ENABLE_MD_HW_INT                                     */
+/*   Description:  Enable MD Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_SHFT      1
+#define SH_LOCAL_INT5_ENABLE_MD_HW_INT_MASK      0x0000000000000002
+
+/*   SH_LOCAL_INT5_ENABLE_XN_HW_INT                                     */
+/*   Description:  Enable XN Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_SHFT      2
+#define SH_LOCAL_INT5_ENABLE_XN_HW_INT_MASK      0x0000000000000004
+
+/*   SH_LOCAL_INT5_ENABLE_LB_HW_INT                                     */
+/*   Description:  Enable LB Hardware interrupt                         */
+#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_SHFT      3
+#define SH_LOCAL_INT5_ENABLE_LB_HW_INT_MASK      0x0000000000000008
+
+/*   SH_LOCAL_INT5_ENABLE_II_HW_INT                                     */
+/*   Description:  Enable II wrapper Hardware interrupt                 */
+#define SH_LOCAL_INT5_ENABLE_II_HW_INT_SHFT      4
+#define SH_LOCAL_INT5_ENABLE_II_HW_INT_MASK      0x0000000000000010
+
+/*   SH_LOCAL_INT5_ENABLE_PI_CE_INT                                     */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_SHFT      5
+#define SH_LOCAL_INT5_ENABLE_PI_CE_INT_MASK      0x0000000000000020
+
+/*   SH_LOCAL_INT5_ENABLE_MD_CE_INT                                     */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_SHFT      6
+#define SH_LOCAL_INT5_ENABLE_MD_CE_INT_MASK      0x0000000000000040
+
+/*   SH_LOCAL_INT5_ENABLE_XN_CE_INT                                     */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_SHFT      7
+#define SH_LOCAL_INT5_ENABLE_XN_CE_INT_MASK      0x0000000000000080
+
+/*   SH_LOCAL_INT5_ENABLE_PI_UCE_INT                                    */
+/*   Description:  Enable PI Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_SHFT     8
+#define SH_LOCAL_INT5_ENABLE_PI_UCE_INT_MASK     0x0000000000000100
+
+/*   SH_LOCAL_INT5_ENABLE_MD_UCE_INT                                    */
+/*   Description:  Enable MD Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_SHFT     9
+#define SH_LOCAL_INT5_ENABLE_MD_UCE_INT_MASK     0x0000000000000200
+
+/*   SH_LOCAL_INT5_ENABLE_XN_UCE_INT                                    */
+/*   Description:  Enable XN Correctable Error Interrupt                */
+#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_SHFT     10
+#define SH_LOCAL_INT5_ENABLE_XN_UCE_INT_MASK     0x0000000000000400
+
+/*   SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT                           */
+/*   Description:  Enable System Shutdown Interrupt                     */
+#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 12
+#define SH_LOCAL_INT5_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000001000
+
+/*   SH_LOCAL_INT5_ENABLE_UART_INT                                      */
+/*   Description:  Enable Junk Bus UART Interrupt                       */
+#define SH_LOCAL_INT5_ENABLE_UART_INT_SHFT       13
+#define SH_LOCAL_INT5_ENABLE_UART_INT_MASK       0x0000000000002000
+
+/*   SH_LOCAL_INT5_ENABLE_L1_NMI_INT                                    */
+/*   Description:  Enable L1 Controller NMI Interrupt                   */
+#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_SHFT     14
+#define SH_LOCAL_INT5_ENABLE_L1_NMI_INT_MASK     0x0000000000004000
+
+/*   SH_LOCAL_INT5_ENABLE_STOP_CLOCK                                    */
+/*   Description:  Stop Clock Interrupt                                 */
+#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_SHFT     15
+#define SH_LOCAL_INT5_ENABLE_STOP_CLOCK_MASK     0x0000000000008000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_CONFIG"                  */
+/*              SHub Processor 0 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC0_ERR_INT_CONFIG                  0x0000000110000a80
+#define SH_PROC0_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC0_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC0_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC0_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC0_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC0_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC0_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC0_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC0_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC0_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC0_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC0_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC0_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC0_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC0_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC0_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC0_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_CONFIG"                  */
+/*              SHub Processor 1 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC1_ERR_INT_CONFIG                  0x0000000110000b00
+#define SH_PROC1_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC1_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC1_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC1_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC1_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC1_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC1_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC1_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC1_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC1_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC1_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC1_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC1_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC1_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC1_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC1_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC1_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_CONFIG"                  */
+/*              SHub Processor 2 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC2_ERR_INT_CONFIG                  0x0000000110000b80
+#define SH_PROC2_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC2_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC2_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC2_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC2_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC2_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC2_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC2_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC2_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC2_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC2_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC2_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC2_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC2_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC2_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC2_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC2_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_CONFIG"                  */
+/*              SHub Processor 3 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#define SH_PROC3_ERR_INT_CONFIG                  0x0000000110000c00
+#define SH_PROC3_ERR_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC3_ERR_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC3_ERR_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC3_ERR_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC3_ERR_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC3_ERR_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC3_ERR_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC3_ERR_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC3_ERR_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC3_ERR_INT_CONFIG_PID_SHFT         4
+#define SH_PROC3_ERR_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC3_ERR_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC3_ERR_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC3_ERR_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC3_ERR_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC3_ERR_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC3_ERR_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_CONFIG"                  */
+/*            SHub Processor 0 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC0_ADV_INT_CONFIG                  0x0000000110000c80
+#define SH_PROC0_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC0_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC0_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC0_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC0_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC0_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC0_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC0_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC0_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC0_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC0_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC0_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC0_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC0_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC0_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC0_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC0_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_CONFIG"                  */
+/*            SHub Processor 1 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC1_ADV_INT_CONFIG                  0x0000000110000d00
+#define SH_PROC1_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC1_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC1_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC1_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC1_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC1_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC1_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC1_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC1_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC1_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC1_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC1_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC1_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC1_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC1_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC1_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC1_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_CONFIG"                  */
+/*            SHub Processor 2 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC2_ADV_INT_CONFIG                  0x0000000110000d80
+#define SH_PROC2_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC2_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC2_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC2_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC2_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC2_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC2_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC2_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC2_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC2_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC2_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC2_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC2_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC2_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC2_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC2_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC2_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_CONFIG"                  */
+/*            SHub Processor 3 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#define SH_PROC3_ADV_INT_CONFIG                  0x0000000110000e00
+#define SH_PROC3_ADV_INT_CONFIG_MASK             0x0ff3ffffffefffff
+#define SH_PROC3_ADV_INT_CONFIG_INIT             0x0000000000000000
+
+/*   SH_PROC3_ADV_INT_CONFIG_TYPE                                       */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROC3_ADV_INT_CONFIG_TYPE_SHFT        0
+#define SH_PROC3_ADV_INT_CONFIG_TYPE_MASK        0x0000000000000007
+
+/*   SH_PROC3_ADV_INT_CONFIG_AGT                                        */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROC3_ADV_INT_CONFIG_AGT_SHFT         3
+#define SH_PROC3_ADV_INT_CONFIG_AGT_MASK         0x0000000000000008
+
+/*   SH_PROC3_ADV_INT_CONFIG_PID                                        */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROC3_ADV_INT_CONFIG_PID_SHFT         4
+#define SH_PROC3_ADV_INT_CONFIG_PID_MASK         0x00000000000ffff0
+
+/*   SH_PROC3_ADV_INT_CONFIG_BASE                                       */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROC3_ADV_INT_CONFIG_BASE_SHFT        21
+#define SH_PROC3_ADV_INT_CONFIG_BASE_MASK        0x0003ffffffe00000
+
+/*   SH_PROC3_ADV_INT_CONFIG_IDX                                        */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROC3_ADV_INT_CONFIG_IDX_SHFT         52
+#define SH_PROC3_ADV_INT_CONFIG_IDX_MASK         0x0ff0000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_ENABLE"                  */
+/*          SHub Processor 0 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC0_ERR_INT_ENABLE                  0x0000000110000e80
+#define SH_PROC0_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC0_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE                           */
+/*   Description:  Enable Processor 0 Error Interrupt                   */
+#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_SHFT 0
+#define SH_PROC0_ERR_INT_ENABLE_PROC0_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_ENABLE"                  */
+/*          SHub Processor 1 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC1_ERR_INT_ENABLE                  0x0000000110000f00
+#define SH_PROC1_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC1_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE                           */
+/*   Description:  Enable Processor 1 Error Interrupt                   */
+#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_SHFT 0
+#define SH_PROC1_ERR_INT_ENABLE_PROC1_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_ENABLE"                  */
+/*          SHub Processor 2 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC2_ERR_INT_ENABLE                  0x0000000110000f80
+#define SH_PROC2_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC2_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE                           */
+/*   Description:  Enable Processor 2 Error Interrupt                   */
+#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_SHFT 0
+#define SH_PROC2_ERR_INT_ENABLE_PROC2_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_ENABLE"                  */
+/*          SHub Processor 3 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#define SH_PROC3_ERR_INT_ENABLE                  0x0000000110001000
+#define SH_PROC3_ERR_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC3_ERR_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE                           */
+/*   Description:  Enable Processor 3 Error Interrupt                   */
+#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_SHFT 0
+#define SH_PROC3_ERR_INT_ENABLE_PROC3_ERR_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_ENABLE"                  */
+/*         SHub Processor 0 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC0_ADV_INT_ENABLE                  0x0000000110001080
+#define SH_PROC0_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC0_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE                           */
+/*   Description:  Enable Processor 0 Advisory Interrupt                */
+#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_SHFT 0
+#define SH_PROC0_ADV_INT_ENABLE_PROC0_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_ENABLE"                  */
+/*         SHub Processor 1 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC1_ADV_INT_ENABLE                  0x0000000110001100
+#define SH_PROC1_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC1_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE                           */
+/*   Description:  Enable Processor 1 Advisory Interrupt                */
+#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_SHFT 0
+#define SH_PROC1_ADV_INT_ENABLE_PROC1_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_ENABLE"                  */
+/*         SHub Processor 2 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC2_ADV_INT_ENABLE                  0x0000000110001180
+#define SH_PROC2_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC2_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE                           */
+/*   Description:  Enable Processor 2 Advisory Interrupt                */
+#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_SHFT 0
+#define SH_PROC2_ADV_INT_ENABLE_PROC2_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_ENABLE"                  */
+/*         SHub Processor 3 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#define SH_PROC3_ADV_INT_ENABLE                  0x0000000110001200
+#define SH_PROC3_ADV_INT_ENABLE_MASK             0x0000000000000001
+#define SH_PROC3_ADV_INT_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE                           */
+/*   Description:  Enable Processor 3 Advisory Interrupt                */
+#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_SHFT 0
+#define SH_PROC3_ADV_INT_ENABLE_PROC3_ADV_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_CONFIG"                   */
+/*            SHub Profile Interrupt Configuration Registers            */
+/* ==================================================================== */
+
+#define SH_PROFILE_INT_CONFIG                    0x0000000110001280
+#define SH_PROFILE_INT_CONFIG_MASK               0x0ff3ffffffefffff
+#define SH_PROFILE_INT_CONFIG_INIT               0x0000000000000000
+
+/*   SH_PROFILE_INT_CONFIG_TYPE                                         */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_PROFILE_INT_CONFIG_TYPE_SHFT          0
+#define SH_PROFILE_INT_CONFIG_TYPE_MASK          0x0000000000000007
+
+/*   SH_PROFILE_INT_CONFIG_AGT                                          */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_PROFILE_INT_CONFIG_AGT_SHFT           3
+#define SH_PROFILE_INT_CONFIG_AGT_MASK           0x0000000000000008
+
+/*   SH_PROFILE_INT_CONFIG_PID                                          */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_PROFILE_INT_CONFIG_PID_SHFT           4
+#define SH_PROFILE_INT_CONFIG_PID_MASK           0x00000000000ffff0
+
+/*   SH_PROFILE_INT_CONFIG_BASE                                         */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_PROFILE_INT_CONFIG_BASE_SHFT          21
+#define SH_PROFILE_INT_CONFIG_BASE_MASK          0x0003ffffffe00000
+
+/*   SH_PROFILE_INT_CONFIG_IDX                                          */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_PROFILE_INT_CONFIG_IDX_SHFT           52
+#define SH_PROFILE_INT_CONFIG_IDX_MASK           0x0ff0000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_ENABLE"                   */
+/*               SHub Profile Interrupt Enable Registers                */
+/* ==================================================================== */
+
+#define SH_PROFILE_INT_ENABLE                    0x0000000110001300
+#define SH_PROFILE_INT_ENABLE_MASK               0x0000000000000001
+#define SH_PROFILE_INT_ENABLE_INIT               0x0000000000000000
+
+/*   SH_PROFILE_INT_ENABLE_PROFILE_ENABLE                               */
+/*   Description:  Enable Profile Interrupt                             */
+#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_SHFT 0
+#define SH_PROFILE_INT_ENABLE_PROFILE_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_CONFIG"                     */
+/*                SHub RTC 0 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC0_INT_CONFIG                       0x0000000110001380
+#define SH_RTC0_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC0_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC0_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC0_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC0_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC0_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC0_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC0_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC0_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC0_INT_CONFIG_PID_SHFT              4
+#define SH_RTC0_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC0_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC0_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC0_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC0_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC0_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC0_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_ENABLE"                     */
+/*                SHub RTC 0 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC0_INT_ENABLE                       0x0000000110001400
+#define SH_RTC0_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC0_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC0_INT_ENABLE_RTC0_ENABLE                                     */
+/*   Description:  Enable RTC 0 Interrupt                               */
+#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_SHFT      0
+#define SH_RTC0_INT_ENABLE_RTC0_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC1_INT_CONFIG                       0x0000000110001480
+#define SH_RTC1_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC1_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC1_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC1_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC1_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC1_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC1_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC1_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC1_INT_CONFIG_PID_SHFT              4
+#define SH_RTC1_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC1_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC1_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC1_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC1_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC1_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC1_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC1_INT_ENABLE                       0x0000000110001500
+#define SH_RTC1_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC1_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC1_INT_ENABLE_RTC1_ENABLE                                     */
+/*   Description:  Enable RTC 1 Interrupt                               */
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_SHFT      0
+#define SH_RTC1_INT_ENABLE_RTC1_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC2_INT_CONFIG                       0x0000000110001580
+#define SH_RTC2_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC2_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC2_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC2_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC2_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC2_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC2_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC2_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC2_INT_CONFIG_PID_SHFT              4
+#define SH_RTC2_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC2_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC2_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC2_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC2_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC2_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC2_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC2_INT_ENABLE                       0x0000000110001600
+#define SH_RTC2_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC2_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC2_INT_ENABLE_RTC2_ENABLE                                     */
+/*   Description:  Enable RTC 2 Interrupt                               */
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_SHFT      0
+#define SH_RTC2_INT_ENABLE_RTC2_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC3_INT_CONFIG                       0x0000000110001680
+#define SH_RTC3_INT_CONFIG_MASK                  0x0ff3ffffffefffff
+#define SH_RTC3_INT_CONFIG_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_CONFIG_TYPE                                            */
+/*   Description:  Type of Interrupt: 0=INT, 2=PMI, 4=NMI, 5=INIT       */
+#define SH_RTC3_INT_CONFIG_TYPE_SHFT             0
+#define SH_RTC3_INT_CONFIG_TYPE_MASK             0x0000000000000007
+
+/*   SH_RTC3_INT_CONFIG_AGT                                             */
+/*   Description:  Agent, must be 0 for SHub                            */
+#define SH_RTC3_INT_CONFIG_AGT_SHFT              3
+#define SH_RTC3_INT_CONFIG_AGT_MASK              0x0000000000000008
+
+/*   SH_RTC3_INT_CONFIG_PID                                             */
+/*   Description:  Processor ID, same setting as on targeted McKinley  */
+#define SH_RTC3_INT_CONFIG_PID_SHFT              4
+#define SH_RTC3_INT_CONFIG_PID_MASK              0x00000000000ffff0
+
+/*   SH_RTC3_INT_CONFIG_BASE                                            */
+/*   Description:  Optional interrupt vector area, 2MB aligned          */
+#define SH_RTC3_INT_CONFIG_BASE_SHFT             21
+#define SH_RTC3_INT_CONFIG_BASE_MASK             0x0003ffffffe00000
+
+/*   SH_RTC3_INT_CONFIG_IDX                                             */
+/*   Description:  Targeted McKinley interrupt vector                   */
+#define SH_RTC3_INT_CONFIG_IDX_SHFT              52
+#define SH_RTC3_INT_CONFIG_IDX_MASK              0x0ff0000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#define SH_RTC3_INT_ENABLE                       0x0000000110001700
+#define SH_RTC3_INT_ENABLE_MASK                  0x0000000000000001
+#define SH_RTC3_INT_ENABLE_INIT                  0x0000000000000000
+
+/*   SH_RTC3_INT_ENABLE_RTC3_ENABLE                                     */
+/*   Description:  Enable RTC 3 Interrupt                               */
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_SHFT      0
+#define SH_RTC3_INT_ENABLE_RTC3_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+
+#define SH_EVENT_OCCURRED                        0x0000000110010000
+#define SH_EVENT_OCCURRED_MASK                   0x000000007fffffff
+#define SH_EVENT_OCCURRED_INIT                   0x0000000000000000
+
+/*   SH_EVENT_OCCURRED_PI_HW_INT                                        */
+/*   Description:  Pending PI Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_PI_HW_INT_SHFT         0
+#define SH_EVENT_OCCURRED_PI_HW_INT_MASK         0x0000000000000001
+
+/*   SH_EVENT_OCCURRED_MD_HW_INT                                        */
+/*   Description:  Pending MD Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_MD_HW_INT_SHFT         1
+#define SH_EVENT_OCCURRED_MD_HW_INT_MASK         0x0000000000000002
+
+/*   SH_EVENT_OCCURRED_XN_HW_INT                                        */
+/*   Description:  Pending XN Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_XN_HW_INT_SHFT         2
+#define SH_EVENT_OCCURRED_XN_HW_INT_MASK         0x0000000000000004
+
+/*   SH_EVENT_OCCURRED_LB_HW_INT                                        */
+/*   Description:  Pending LB Hardware interrupt                        */
+#define SH_EVENT_OCCURRED_LB_HW_INT_SHFT         3
+#define SH_EVENT_OCCURRED_LB_HW_INT_MASK         0x0000000000000008
+
+/*   SH_EVENT_OCCURRED_II_HW_INT                                        */
+/*   Description:  Pending II wrapper Hardware interrupt                */
+#define SH_EVENT_OCCURRED_II_HW_INT_SHFT         4
+#define SH_EVENT_OCCURRED_II_HW_INT_MASK         0x0000000000000010
+
+/*   SH_EVENT_OCCURRED_PI_CE_INT                                        */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_PI_CE_INT_SHFT         5
+#define SH_EVENT_OCCURRED_PI_CE_INT_MASK         0x0000000000000020
+
+/*   SH_EVENT_OCCURRED_MD_CE_INT                                        */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_MD_CE_INT_SHFT         6
+#define SH_EVENT_OCCURRED_MD_CE_INT_MASK         0x0000000000000040
+
+/*   SH_EVENT_OCCURRED_XN_CE_INT                                        */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_XN_CE_INT_SHFT         7
+#define SH_EVENT_OCCURRED_XN_CE_INT_MASK         0x0000000000000080
+
+/*   SH_EVENT_OCCURRED_PI_UCE_INT                                       */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_PI_UCE_INT_SHFT        8
+#define SH_EVENT_OCCURRED_PI_UCE_INT_MASK        0x0000000000000100
+
+/*   SH_EVENT_OCCURRED_MD_UCE_INT                                       */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_MD_UCE_INT_SHFT        9
+#define SH_EVENT_OCCURRED_MD_UCE_INT_MASK        0x0000000000000200
+
+/*   SH_EVENT_OCCURRED_XN_UCE_INT                                       */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OCCURRED_XN_UCE_INT_SHFT        10
+#define SH_EVENT_OCCURRED_XN_UCE_INT_MASK        0x0000000000000400
+
+/*   SH_EVENT_OCCURRED_PROC0_ADV_INT                                    */
+/*   Description:  Pending Processor 0 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC0_ADV_INT_SHFT     11
+#define SH_EVENT_OCCURRED_PROC0_ADV_INT_MASK     0x0000000000000800
+
+/*   SH_EVENT_OCCURRED_PROC1_ADV_INT                                    */
+/*   Description:  Pending Processor 1 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC1_ADV_INT_SHFT     12
+#define SH_EVENT_OCCURRED_PROC1_ADV_INT_MASK     0x0000000000001000
+
+/*   SH_EVENT_OCCURRED_PROC2_ADV_INT                                    */
+/*   Description:  Pending Processor 2 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC2_ADV_INT_SHFT     13
+#define SH_EVENT_OCCURRED_PROC2_ADV_INT_MASK     0x0000000000002000
+
+/*   SH_EVENT_OCCURRED_PROC3_ADV_INT                                    */
+/*   Description:  Pending Processor 3 Advisory Interrupt               */
+#define SH_EVENT_OCCURRED_PROC3_ADV_INT_SHFT     14
+#define SH_EVENT_OCCURRED_PROC3_ADV_INT_MASK     0x0000000000004000
+
+/*   SH_EVENT_OCCURRED_PROC0_ERR_INT                                    */
+/*   Description:  Pending Processor 0 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC0_ERR_INT_SHFT     15
+#define SH_EVENT_OCCURRED_PROC0_ERR_INT_MASK     0x0000000000008000
+
+/*   SH_EVENT_OCCURRED_PROC1_ERR_INT                                    */
+/*   Description:  Pending Processor 1 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC1_ERR_INT_SHFT     16
+#define SH_EVENT_OCCURRED_PROC1_ERR_INT_MASK     0x0000000000010000
+
+/*   SH_EVENT_OCCURRED_PROC2_ERR_INT                                    */
+/*   Description:  Pending Processor 2 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC2_ERR_INT_SHFT     17
+#define SH_EVENT_OCCURRED_PROC2_ERR_INT_MASK     0x0000000000020000
+
+/*   SH_EVENT_OCCURRED_PROC3_ERR_INT                                    */
+/*   Description:  Pending Processor 3 Error Interrupt                  */
+#define SH_EVENT_OCCURRED_PROC3_ERR_INT_SHFT     18
+#define SH_EVENT_OCCURRED_PROC3_ERR_INT_MASK     0x0000000000040000
+
+/*   SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT                              */
+/*   Description:  Pending System Shutdown Interrupt                    */
+#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_SHFT 19
+#define SH_EVENT_OCCURRED_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
+
+/*   SH_EVENT_OCCURRED_UART_INT                                         */
+/*   Description:  Pending Junk Bus UART Interrupt                      */
+#define SH_EVENT_OCCURRED_UART_INT_SHFT          20
+#define SH_EVENT_OCCURRED_UART_INT_MASK          0x0000000000100000
+
+/*   SH_EVENT_OCCURRED_L1_NMI_INT                                       */
+/*   Description:  Pending L1 Controller NMI Interrupt                  */
+#define SH_EVENT_OCCURRED_L1_NMI_INT_SHFT        21
+#define SH_EVENT_OCCURRED_L1_NMI_INT_MASK        0x0000000000200000
+
+/*   SH_EVENT_OCCURRED_STOP_CLOCK                                       */
+/*   Description:  Pending Stop Clock Interrupt                         */
+#define SH_EVENT_OCCURRED_STOP_CLOCK_SHFT        22
+#define SH_EVENT_OCCURRED_STOP_CLOCK_MASK        0x0000000000400000
+
+/*   SH_EVENT_OCCURRED_RTC0_INT                                         */
+/*   Description:  Pending RTC 0 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC0_INT_SHFT          23
+#define SH_EVENT_OCCURRED_RTC0_INT_MASK          0x0000000000800000
+
+/*   SH_EVENT_OCCURRED_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC1_INT_SHFT          24
+#define SH_EVENT_OCCURRED_RTC1_INT_MASK          0x0000000001000000
+
+/*   SH_EVENT_OCCURRED_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC2_INT_SHFT          25
+#define SH_EVENT_OCCURRED_RTC2_INT_MASK          0x0000000002000000
+
+/*   SH_EVENT_OCCURRED_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OCCURRED_RTC3_INT_SHFT          26
+#define SH_EVENT_OCCURRED_RTC3_INT_MASK          0x0000000004000000
+
+/*   SH_EVENT_OCCURRED_PROFILE_INT                                      */
+/*   Description:  Pending Profile Interrupt                            */
+#define SH_EVENT_OCCURRED_PROFILE_INT_SHFT       27
+#define SH_EVENT_OCCURRED_PROFILE_INT_MASK       0x0000000008000000
+
+/*   SH_EVENT_OCCURRED_IPI_INT                                          */
+/*   Description:  Pending IPI Interrupt                                */
+#define SH_EVENT_OCCURRED_IPI_INT_SHFT           28
+#define SH_EVENT_OCCURRED_IPI_INT_MASK           0x0000000010000000
+
+/*   SH_EVENT_OCCURRED_II_INT0                                          */
+/*   Description:  Pending II 0 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT0_SHFT           29
+#define SH_EVENT_OCCURRED_II_INT0_MASK           0x0000000020000000
+
+/*   SH_EVENT_OCCURRED_II_INT1                                          */
+/*   Description:  Pending II 1 Interrupt                               */
+#define SH_EVENT_OCCURRED_II_INT1_SHFT           30
+#define SH_EVENT_OCCURRED_II_INT1_MASK           0x0000000040000000
+
+/* ==================================================================== */
+/*                  Register "SH_EVENT_OCCURRED_ALIAS"                  */
+/*                 SHub Interrupt Event Occurred Alias                  */
+/* ==================================================================== */
+
+#define SH_EVENT_OCCURRED_ALIAS                  0x0000000110010008
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OVERFLOW"                     */
+/*                SHub Interrupt Event Occurred Overflow                */
+/* ==================================================================== */
+
+#define SH_EVENT_OVERFLOW                        0x0000000110010080
+#define SH_EVENT_OVERFLOW_MASK                   0x000000000fffffff
+#define SH_EVENT_OVERFLOW_INIT                   0x0000000000000000
+
+/*   SH_EVENT_OVERFLOW_PI_HW_INT                                        */
+/*   Description:  Pending PI Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_PI_HW_INT_SHFT         0
+#define SH_EVENT_OVERFLOW_PI_HW_INT_MASK         0x0000000000000001
+
+/*   SH_EVENT_OVERFLOW_MD_HW_INT                                        */
+/*   Description:  Pending MD Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_MD_HW_INT_SHFT         1
+#define SH_EVENT_OVERFLOW_MD_HW_INT_MASK         0x0000000000000002
+
+/*   SH_EVENT_OVERFLOW_XN_HW_INT                                        */
+/*   Description:  Pending XN Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_XN_HW_INT_SHFT         2
+#define SH_EVENT_OVERFLOW_XN_HW_INT_MASK         0x0000000000000004
+
+/*   SH_EVENT_OVERFLOW_LB_HW_INT                                        */
+/*   Description:  Pending LB Hardware interrupt                        */
+#define SH_EVENT_OVERFLOW_LB_HW_INT_SHFT         3
+#define SH_EVENT_OVERFLOW_LB_HW_INT_MASK         0x0000000000000008
+
+/*   SH_EVENT_OVERFLOW_II_HW_INT                                        */
+/*   Description:  Pending II wrapper Hardware interrupt                */
+#define SH_EVENT_OVERFLOW_II_HW_INT_SHFT         4
+#define SH_EVENT_OVERFLOW_II_HW_INT_MASK         0x0000000000000010
+
+/*   SH_EVENT_OVERFLOW_PI_CE_INT                                        */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_PI_CE_INT_SHFT         5
+#define SH_EVENT_OVERFLOW_PI_CE_INT_MASK         0x0000000000000020
+
+/*   SH_EVENT_OVERFLOW_MD_CE_INT                                        */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_MD_CE_INT_SHFT         6
+#define SH_EVENT_OVERFLOW_MD_CE_INT_MASK         0x0000000000000040
+
+/*   SH_EVENT_OVERFLOW_XN_CE_INT                                        */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_XN_CE_INT_SHFT         7
+#define SH_EVENT_OVERFLOW_XN_CE_INT_MASK         0x0000000000000080
+
+/*   SH_EVENT_OVERFLOW_PI_UCE_INT                                       */
+/*   Description:  Pending PI Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_PI_UCE_INT_SHFT        8
+#define SH_EVENT_OVERFLOW_PI_UCE_INT_MASK        0x0000000000000100
+
+/*   SH_EVENT_OVERFLOW_MD_UCE_INT                                       */
+/*   Description:  Pending MD Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_MD_UCE_INT_SHFT        9
+#define SH_EVENT_OVERFLOW_MD_UCE_INT_MASK        0x0000000000000200
+
+/*   SH_EVENT_OVERFLOW_XN_UCE_INT                                       */
+/*   Description:  Pending XN Correctable Error Interrupt               */
+#define SH_EVENT_OVERFLOW_XN_UCE_INT_SHFT        10
+#define SH_EVENT_OVERFLOW_XN_UCE_INT_MASK        0x0000000000000400
+
+/*   SH_EVENT_OVERFLOW_PROC0_ADV_INT                                    */
+/*   Description:  Pending Processor 0 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_SHFT     11
+#define SH_EVENT_OVERFLOW_PROC0_ADV_INT_MASK     0x0000000000000800
+
+/*   SH_EVENT_OVERFLOW_PROC1_ADV_INT                                    */
+/*   Description:  Pending Processor 1 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_SHFT     12
+#define SH_EVENT_OVERFLOW_PROC1_ADV_INT_MASK     0x0000000000001000
+
+/*   SH_EVENT_OVERFLOW_PROC2_ADV_INT                                    */
+/*   Description:  Pending Processor 2 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_SHFT     13
+#define SH_EVENT_OVERFLOW_PROC2_ADV_INT_MASK     0x0000000000002000
+
+/*   SH_EVENT_OVERFLOW_PROC3_ADV_INT                                    */
+/*   Description:  Pending Processor 3 Advisory Interrupt               */
+#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_SHFT     14
+#define SH_EVENT_OVERFLOW_PROC3_ADV_INT_MASK     0x0000000000004000
+
+/*   SH_EVENT_OVERFLOW_PROC0_ERR_INT                                    */
+/*   Description:  Pending Processor 0 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_SHFT     15
+#define SH_EVENT_OVERFLOW_PROC0_ERR_INT_MASK     0x0000000000008000
+
+/*   SH_EVENT_OVERFLOW_PROC1_ERR_INT                                    */
+/*   Description:  Pending Processor 1 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_SHFT     16
+#define SH_EVENT_OVERFLOW_PROC1_ERR_INT_MASK     0x0000000000010000
+
+/*   SH_EVENT_OVERFLOW_PROC2_ERR_INT                                    */
+/*   Description:  Pending Processor 2 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_SHFT     17
+#define SH_EVENT_OVERFLOW_PROC2_ERR_INT_MASK     0x0000000000020000
+
+/*   SH_EVENT_OVERFLOW_PROC3_ERR_INT                                    */
+/*   Description:  Pending Processor 3 Error Interrupt                  */
+#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_SHFT     18
+#define SH_EVENT_OVERFLOW_PROC3_ERR_INT_MASK     0x0000000000040000
+
+/*   SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT                              */
+/*   Description:  Pending System Shutdown Interrupt                    */
+#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_SHFT 19
+#define SH_EVENT_OVERFLOW_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000080000
+
+/*   SH_EVENT_OVERFLOW_UART_INT                                         */
+/*   Description:  Pending Junk Bus UART Interrupt                      */
+#define SH_EVENT_OVERFLOW_UART_INT_SHFT          20
+#define SH_EVENT_OVERFLOW_UART_INT_MASK          0x0000000000100000
+
+/*   SH_EVENT_OVERFLOW_L1_NMI_INT                                       */
+/*   Description:  Pending L1 Controller NMI Interrupt                  */
+#define SH_EVENT_OVERFLOW_L1_NMI_INT_SHFT        21
+#define SH_EVENT_OVERFLOW_L1_NMI_INT_MASK        0x0000000000200000
+
+/*   SH_EVENT_OVERFLOW_STOP_CLOCK                                       */
+/*   Description:  Pending Stop Clock Interrupt                         */
+#define SH_EVENT_OVERFLOW_STOP_CLOCK_SHFT        22
+#define SH_EVENT_OVERFLOW_STOP_CLOCK_MASK        0x0000000000400000
+
+/*   SH_EVENT_OVERFLOW_RTC0_INT                                         */
+/*   Description:  Pending RTC 0 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC0_INT_SHFT          23
+#define SH_EVENT_OVERFLOW_RTC0_INT_MASK          0x0000000000800000
+
+/*   SH_EVENT_OVERFLOW_RTC1_INT                                         */
+/*   Description:  Pending RTC 1 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC1_INT_SHFT          24
+#define SH_EVENT_OVERFLOW_RTC1_INT_MASK          0x0000000001000000
+
+/*   SH_EVENT_OVERFLOW_RTC2_INT                                         */
+/*   Description:  Pending RTC 2 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC2_INT_SHFT          25
+#define SH_EVENT_OVERFLOW_RTC2_INT_MASK          0x0000000002000000
+
+/*   SH_EVENT_OVERFLOW_RTC3_INT                                         */
+/*   Description:  Pending RTC 3 Interrupt                              */
+#define SH_EVENT_OVERFLOW_RTC3_INT_SHFT          26
+#define SH_EVENT_OVERFLOW_RTC3_INT_MASK          0x0000000004000000
+
+/*   SH_EVENT_OVERFLOW_PROFILE_INT                                      */
+/*   Description:  Pending Profile Interrupt                            */
+#define SH_EVENT_OVERFLOW_PROFILE_INT_SHFT       27
+#define SH_EVENT_OVERFLOW_PROFILE_INT_MASK       0x0000000008000000
+
+/* ==================================================================== */
+/*                  Register "SH_EVENT_OVERFLOW_ALIAS"                  */
+/*             SHub Interrupt Event Occurred Overflow Alias             */
+/* ==================================================================== */
+
+#define SH_EVENT_OVERFLOW_ALIAS                  0x0000000110010088
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_TIME"                      */
+/*                           Junk Bus Timing                            */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_TIME                         0x0000000110020000
+#define SH_JUNK_BUS_TIME_MASK                    0x00000000ffffffff
+#define SH_JUNK_BUS_TIME_INIT                    0x0000000040404040
+
+/*   SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD                                  */
+/*   Description:  Fprom_Setup_Hold                                     */
+#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_SHFT   0
+#define SH_JUNK_BUS_TIME_FPROM_SETUP_HOLD_MASK   0x00000000000000ff
+
+/*   SH_JUNK_BUS_TIME_FPROM_ENABLE                                      */
+/*   Description:  Fprom_Enable                                         */
+#define SH_JUNK_BUS_TIME_FPROM_ENABLE_SHFT       8
+#define SH_JUNK_BUS_TIME_FPROM_ENABLE_MASK       0x000000000000ff00
+
+/*   SH_JUNK_BUS_TIME_UART_SETUP_HOLD                                   */
+/*   Description:  Uart_Setup_Hold                                      */
+#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_SHFT    16
+#define SH_JUNK_BUS_TIME_UART_SETUP_HOLD_MASK    0x0000000000ff0000
+
+/*   SH_JUNK_BUS_TIME_UART_ENABLE                                       */
+/*   Description:  Uart_Enable                                          */
+#define SH_JUNK_BUS_TIME_UART_ENABLE_SHFT        24
+#define SH_JUNK_BUS_TIME_UART_ENABLE_MASK        0x00000000ff000000
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_LATCH_TIME"                     */
+/*                        Junk Bus Latch Timing                         */
+/* ==================================================================== */
+
+#define SH_JUNK_LATCH_TIME                       0x0000000110020080
+#define SH_JUNK_LATCH_TIME_MASK                  0x0000000000000007
+#define SH_JUNK_LATCH_TIME_INIT                  0x0000000000000002
+
+/*   SH_JUNK_LATCH_TIME_SETUP_HOLD                                      */
+/*   Description:  Setup and Hold Time                                  */
+#define SH_JUNK_LATCH_TIME_SETUP_HOLD_SHFT       0
+#define SH_JUNK_LATCH_TIME_SETUP_HOLD_MASK       0x0000000000000007
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_NACK_RESET"                     */
+/*                     Junk Bus Nack Counter Reset                      */
+/* ==================================================================== */
+
+#define SH_JUNK_NACK_RESET                       0x0000000110020100
+#define SH_JUNK_NACK_RESET_MASK                  0x0000000000000001
+#define SH_JUNK_NACK_RESET_INIT                  0x0000000000000000
+
+/*   SH_JUNK_NACK_RESET_PULSE                                           */
+/*   Description:  Junk bus nack counter reset                          */
+#define SH_JUNK_NACK_RESET_PULSE_SHFT            0
+#define SH_JUNK_NACK_RESET_PULSE_MASK            0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED0"                      */
+/*                            Junk Bus LED0                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED0                         0x0000000110030000
+#define SH_JUNK_BUS_LED0_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED0_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED0_LED0_DATA                                         */
+/*   Description:  LED0_data                                            */
+#define SH_JUNK_BUS_LED0_LED0_DATA_SHFT          0
+#define SH_JUNK_BUS_LED0_LED0_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED1"                      */
+/*                            Junk Bus LED1                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED1                         0x0000000110030080
+#define SH_JUNK_BUS_LED1_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED1_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED1_LED1_DATA                                         */
+/*   Description:  LED1_data                                            */
+#define SH_JUNK_BUS_LED1_LED1_DATA_SHFT          0
+#define SH_JUNK_BUS_LED1_LED1_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED2"                      */
+/*                            Junk Bus LED2                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED2                         0x0000000110030100
+#define SH_JUNK_BUS_LED2_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED2_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED2_LED2_DATA                                         */
+/*   Description:  LED2_data                                            */
+#define SH_JUNK_BUS_LED2_LED2_DATA_SHFT          0
+#define SH_JUNK_BUS_LED2_LED2_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED3"                      */
+/*                            Junk Bus LED3                             */
+/* ==================================================================== */
+
+#define SH_JUNK_BUS_LED3                         0x0000000110030180
+#define SH_JUNK_BUS_LED3_MASK                    0x00000000000000ff
+#define SH_JUNK_BUS_LED3_INIT                    0x0000000000000000
+
+/*   SH_JUNK_BUS_LED3_LED3_DATA                                         */
+/*   Description:  LED3_data                                            */
+#define SH_JUNK_BUS_LED3_LED3_DATA_SHFT          0
+#define SH_JUNK_BUS_LED3_LED3_DATA_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                   Register "SH_JUNK_ERROR_STATUS"                    */
+/*                        Junk Bus Error Status                         */
+/* ==================================================================== */
+
+#define SH_JUNK_ERROR_STATUS                     0x0000000110030200
+#define SH_JUNK_ERROR_STATUS_MASK                0x1fff7fffffffffff
+#define SH_JUNK_ERROR_STATUS_INIT                0x0000000000000000
+
+/*   SH_JUNK_ERROR_STATUS_ADDRESS                                       */
+/*   Description:  Failing junk bus address                             */
+#define SH_JUNK_ERROR_STATUS_ADDRESS_SHFT        0
+#define SH_JUNK_ERROR_STATUS_ADDRESS_MASK        0x00007fffffffffff
+
+/*   SH_JUNK_ERROR_STATUS_CMD                                           */
+/*   Description:  Junk bus command                                     */
+#define SH_JUNK_ERROR_STATUS_CMD_SHFT            48
+#define SH_JUNK_ERROR_STATUS_CMD_MASK            0x00ff000000000000
+
+/*   SH_JUNK_ERROR_STATUS_MODE                                          */
+/*   Description:  Mode                                                 */
+#define SH_JUNK_ERROR_STATUS_MODE_SHFT           56
+#define SH_JUNK_ERROR_STATUS_MODE_MASK           0x0100000000000000
+
+/*   SH_JUNK_ERROR_STATUS_STATUS                                        */
+/*   Description:  Status                                               */
+#define SH_JUNK_ERROR_STATUS_STATUS_SHFT         57
+#define SH_JUNK_ERROR_STATUS_STATUS_MASK         0x1e00000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_STAT                          0x0000000150000000
+#define SH_NI0_LLP_STAT_MASK                     0x000000000000000f
+#define SH_NI0_LLP_STAT_INIT                     0x0000000000000000
+
+/*   SH_NI0_LLP_STAT_LINK_RESET_STATE                                   */
+/*   Description:  Status of LLP link.                                  */
+#define SH_NI0_LLP_STAT_LINK_RESET_STATE_SHFT    0
+#define SH_NI0_LLP_STAT_LINK_RESET_STATE_MASK    0x000000000000000f
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_RESET                         0x0000000150000008
+#define SH_NI0_LLP_RESET_MASK                    0x0000000000000003
+#define SH_NI0_LLP_RESET_INIT                    0x0000000000000000
+
+/*   SH_NI0_LLP_RESET_LINK                                              */
+/*   Description:  Send Link Reset. Generates a pulse.                  */
+#define SH_NI0_LLP_RESET_LINK_SHFT               0
+#define SH_NI0_LLP_RESET_LINK_MASK               0x0000000000000001
+
+/*   SH_NI0_LLP_RESET_WARM                                              */
+/*   Description:  Send Warm Reset. Generates a pulse.                  */
+#define SH_NI0_LLP_RESET_WARM_SHFT               1
+#define SH_NI0_LLP_RESET_WARM_MASK               0x0000000000000002
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_RESET_EN                      0x0000000150000010
+#define SH_NI0_LLP_RESET_EN_MASK                 0x0000000000000001
+#define SH_NI0_LLP_RESET_EN_INIT                 0x0000000000000001
+
+/*   SH_NI0_LLP_RESET_EN_OK                                             */
+/*   Description:  Allow LLP warm reset to reset SHUB                   */
+#define SH_NI0_LLP_RESET_EN_OK_SHFT              0
+#define SH_NI0_LLP_RESET_EN_OK_MASK              0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CHAN_MODE                     0x0000000150000018
+#define SH_NI0_LLP_CHAN_MODE_MASK                0x000000000000001f
+#define SH_NI0_LLP_CHAN_MODE_INIT                0x0000000000000000
+
+/*   SH_NI0_LLP_CHAN_MODE_BITMODE32                                     */
+/*   Description:  Enables 32-bit (plus sideband) channel phits         */
+#define SH_NI0_LLP_CHAN_MODE_BITMODE32_SHFT      0
+#define SH_NI0_LLP_CHAN_MODE_BITMODE32_MASK      0x0000000000000001
+
+/*   SH_NI0_LLP_CHAN_MODE_AC_ENCODE                                     */
+/*   Description:  Enables nearly dc-free encoding for AC-coupling      */
+#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_SHFT      1
+#define SH_NI0_LLP_CHAN_MODE_AC_ENCODE_MASK      0x0000000000000002
+
+/*   SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING                                 */
+/*   Description:  Enables automatic tuning of channel skew.            */
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_SHFT  2
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_TUNING_MASK  0x0000000000000004
+
+/*   SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD                             */
+/*   Description:  Enables remote fine tune updates                     */
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008
+
+/*   SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD                                */
+/*   Description:  Enables quadrature clock in the pfssd                */
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4
+#define SH_NI0_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CONFIG                        0x0000000150000020
+#define SH_NI0_LLP_CONFIG_MASK                   0x0000003fffffffff
+#define SH_NI0_LLP_CONFIG_INIT                   0x00000007fc6ffd00
+
+/*   SH_NI0_LLP_CONFIG_MAXBURST                                         */
+#define SH_NI0_LLP_CONFIG_MAXBURST_SHFT          0
+#define SH_NI0_LLP_CONFIG_MAXBURST_MASK          0x00000000000003ff
+
+/*   SH_NI0_LLP_CONFIG_MAXRETRY                                         */
+#define SH_NI0_LLP_CONFIG_MAXRETRY_SHFT          10
+#define SH_NI0_LLP_CONFIG_MAXRETRY_MASK          0x00000000000ffc00
+
+/*   SH_NI0_LLP_CONFIG_NULLTIMEOUT                                      */
+#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_SHFT       20
+#define SH_NI0_LLP_CONFIG_NULLTIMEOUT_MASK       0x0000000003f00000
+
+/*   SH_NI0_LLP_CONFIG_FTU_TIME                                         */
+#define SH_NI0_LLP_CONFIG_FTU_TIME_SHFT          26
+#define SH_NI0_LLP_CONFIG_FTU_TIME_MASK          0x0000003ffc000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_TEST_CTL                      0x0000000150000028
+#define SH_NI0_LLP_TEST_CTL_MASK                 0x7ff3f3ffffffffff
+#define SH_NI0_LLP_TEST_CTL_INIT                 0x000000000a5fffff
+
+/*   SH_NI0_LLP_TEST_CTL_PATTERN                                        */
+/*   Description:  Send channel data pattern                            */
+#define SH_NI0_LLP_TEST_CTL_PATTERN_SHFT         0
+#define SH_NI0_LLP_TEST_CTL_PATTERN_MASK         0x000000ffffffffff
+
+/*   SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE                                 */
+/*   Description:  Enables continuous send of data                      */
+#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_SHFT  40
+#define SH_NI0_LLP_TEST_CTL_SEND_TEST_MODE_MASK  0x0000030000000000
+
+/*   SH_NI0_LLP_TEST_CTL_WIRE_SEL                                       */
+#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_SHFT        44
+#define SH_NI0_LLP_TEST_CTL_WIRE_SEL_MASK        0x0003f00000000000
+
+/*   SH_NI0_LLP_TEST_CTL_LFSR_MODE                                      */
+#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_SHFT       52
+#define SH_NI0_LLP_TEST_CTL_LFSR_MODE_MASK       0x0030000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_NOISE_MODE                                     */
+#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_SHFT      54
+#define SH_NI0_LLP_TEST_CTL_NOISE_MODE_MASK      0x00c0000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_ARMCAPTURE                                     */
+/*   Description:  Enable Capture of Next MicroPacket                   */
+#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_SHFT      56
+#define SH_NI0_LLP_TEST_CTL_ARMCAPTURE_MASK      0x0100000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_CAPTURECBONLY                                  */
+/*   Description:  Only capture a micropacket with a Check Byte error  */
+#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_SHFT   57
+#define SH_NI0_LLP_TEST_CTL_CAPTURECBONLY_MASK   0x0200000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_SENDCBERROR                                    */
+/*   Description:  Sends a single error                                 */
+#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_SHFT     58
+#define SH_NI0_LLP_TEST_CTL_SENDCBERROR_MASK     0x0400000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_SENDSNERROR                                    */
+/*   Description:  Sends a single sequence number error                 */
+#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_SHFT     59
+#define SH_NI0_LLP_TEST_CTL_SENDSNERROR_MASK     0x0800000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_FAKESNERROR                                    */
+/*   Description:  Causes receiver to pretend it saw a sn error         */
+#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_SHFT     60
+#define SH_NI0_LLP_TEST_CTL_FAKESNERROR_MASK     0x1000000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_CAPTURED                                       */
+/*   Description:  Indicates a Valid Micropacket was captured           */
+#define SH_NI0_LLP_TEST_CTL_CAPTURED_SHFT        61
+#define SH_NI0_LLP_TEST_CTL_CAPTURED_MASK        0x2000000000000000
+
+/*   SH_NI0_LLP_TEST_CTL_CBERROR                                        */
+/*   Description:  Indicates a Micropacket with a CB error was capture  */
+#define SH_NI0_LLP_TEST_CTL_CBERROR_SHFT         62
+#define SH_NI0_LLP_TEST_CTL_CBERROR_MASK         0x4000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CAPT_WD1                      0x0000000150000030
+#define SH_NI0_LLP_CAPT_WD1_MASK                 0xffffffffffffffff
+#define SH_NI0_LLP_CAPT_WD1_INIT                 0x0000000000000000
+
+/*   SH_NI0_LLP_CAPT_WD1_DATA                                           */
+/*   Description:  low order 64-bit captured word                       */
+#define SH_NI0_LLP_CAPT_WD1_DATA_SHFT            0
+#define SH_NI0_LLP_CAPT_WD1_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CAPT_WD2                      0x0000000150000038
+#define SH_NI0_LLP_CAPT_WD2_MASK                 0xffffffffffffffff
+#define SH_NI0_LLP_CAPT_WD2_INIT                 0x0000000000000000
+
+/*   SH_NI0_LLP_CAPT_WD2_DATA                                           */
+/*   Description:  high order 64-bit captured word                      */
+#define SH_NI0_LLP_CAPT_WD2_DATA_SHFT            0
+#define SH_NI0_LLP_CAPT_WD2_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_CAPT_SBCB                     0x0000000150000040
+#define SH_NI0_LLP_CAPT_SBCB_MASK                0x0000001fffffffff
+#define SH_NI0_LLP_CAPT_SBCB_INIT                0x0000000000000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN                               */
+/*   Description:  sideband and sequence                                */
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff
+
+/*   SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC                                */
+/*   Description:  CRC                                                  */
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16
+#define SH_NI0_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000
+
+/*   SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS                               */
+/*   Description:  All CB errors have been sent                         */
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS                               */
+/*   Description:  All SN errors have been sent                         */
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33
+#define SH_NI0_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS                              */
+/*   Description:  All faked SN errors have been sent                   */
+#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34
+#define SH_NI0_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW                                */
+/*   Description:  wire charge counter overflowed, valid if llp_mode e  */
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000
+
+/*   SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW                               */
+/*   Description:  wire charge counter underflowed, valid if llp_mode   */
+/*  enabled                                                             */
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36
+#define SH_NI0_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_ERR"                       */
+/* ==================================================================== */
+
+#define SH_NI0_LLP_ERR                           0x0000000150000048
+#define SH_NI0_LLP_ERR_MASK                      0x001fffffffffffff
+#define SH_NI0_LLP_ERR_INIT                      0x0000000000000000
+
+/*   SH_NI0_LLP_ERR_RX_SN_ERR_COUNT                                     */
+/*   Description:  Counts the sequence number errors received           */
+#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_SHFT      0
+#define SH_NI0_LLP_ERR_RX_SN_ERR_COUNT_MASK      0x00000000000000ff
+
+/*   SH_NI0_LLP_ERR_RX_CB_ERR_COUNT                                     */
+/*   Description:  Counts the check byte errors received                */
+#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_SHFT      8
+#define SH_NI0_LLP_ERR_RX_CB_ERR_COUNT_MASK      0x000000000000ff00
+
+/*   SH_NI0_LLP_ERR_RETRY_COUNT                                         */
+/*   Description:  Counts the retries                                   */
+#define SH_NI0_LLP_ERR_RETRY_COUNT_SHFT          16
+#define SH_NI0_LLP_ERR_RETRY_COUNT_MASK          0x0000000000ff0000
+
+/*   SH_NI0_LLP_ERR_RETRY_TIMEOUT                                       */
+/*   Description:  Indicates a retry timeout has occured                */
+#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_SHFT        24
+#define SH_NI0_LLP_ERR_RETRY_TIMEOUT_MASK        0x0000000001000000
+
+/*   SH_NI0_LLP_ERR_RCV_LINK_RESET                                      */
+/*   Description:  Indicates a link reset has been received             */
+#define SH_NI0_LLP_ERR_RCV_LINK_RESET_SHFT       25
+#define SH_NI0_LLP_ERR_RCV_LINK_RESET_MASK       0x0000000002000000
+
+/*   SH_NI0_LLP_ERR_SQUASH                                              */
+/*   Description:  Indicates a micropacket was squashed                 */
+#define SH_NI0_LLP_ERR_SQUASH_SHFT               26
+#define SH_NI0_LLP_ERR_SQUASH_MASK               0x0000000004000000
+
+/*   SH_NI0_LLP_ERR_POWER_NOT_OK                                        */
+/*   Description:  Detects and traps a loss of power_OK                 */
+#define SH_NI0_LLP_ERR_POWER_NOT_OK_SHFT         27
+#define SH_NI0_LLP_ERR_POWER_NOT_OK_MASK         0x0000000008000000
+
+/*   SH_NI0_LLP_ERR_WIRE_CNT                                            */
+/*   Description:  counts the errors detected on a single wire test     */
+#define SH_NI0_LLP_ERR_WIRE_CNT_SHFT             28
+#define SH_NI0_LLP_ERR_WIRE_CNT_MASK             0x000ffffff0000000
+
+/*   SH_NI0_LLP_ERR_WIRE_OVERFLOW                                       */
+/*   Description:  wire_error_cnt has overflowed                        */
+#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_SHFT        52
+#define SH_NI0_LLP_ERR_WIRE_OVERFLOW_MASK        0x0010000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_STAT                          0x0000000150002000
+#define SH_NI1_LLP_STAT_MASK                     0x000000000000000f
+#define SH_NI1_LLP_STAT_INIT                     0x0000000000000000
+
+/*   SH_NI1_LLP_STAT_LINK_RESET_STATE                                   */
+/*   Description:  Status of LLP link.                                  */
+#define SH_NI1_LLP_STAT_LINK_RESET_STATE_SHFT    0
+#define SH_NI1_LLP_STAT_LINK_RESET_STATE_MASK    0x000000000000000f
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_RESET                         0x0000000150002008
+#define SH_NI1_LLP_RESET_MASK                    0x0000000000000003
+#define SH_NI1_LLP_RESET_INIT                    0x0000000000000000
+
+/*   SH_NI1_LLP_RESET_LINK                                              */
+/*   Description:  Send Link Reset. Generates a pulse.                  */
+#define SH_NI1_LLP_RESET_LINK_SHFT               0
+#define SH_NI1_LLP_RESET_LINK_MASK               0x0000000000000001
+
+/*   SH_NI1_LLP_RESET_WARM                                              */
+/*   Description:  Send Warm Reset. Generates a pulse.                  */
+#define SH_NI1_LLP_RESET_WARM_SHFT               1
+#define SH_NI1_LLP_RESET_WARM_MASK               0x0000000000000002
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_RESET_EN                      0x0000000150002010
+#define SH_NI1_LLP_RESET_EN_MASK                 0x0000000000000001
+#define SH_NI1_LLP_RESET_EN_INIT                 0x0000000000000001
+
+/*   SH_NI1_LLP_RESET_EN_OK                                             */
+/*   Description:  Allow LLP warm reset to reset SHUB                   */
+#define SH_NI1_LLP_RESET_EN_OK_SHFT              0
+#define SH_NI1_LLP_RESET_EN_OK_MASK              0x0000000000000001
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CHAN_MODE                     0x0000000150002018
+#define SH_NI1_LLP_CHAN_MODE_MASK                0x000000000000001f
+#define SH_NI1_LLP_CHAN_MODE_INIT                0x0000000000000000
+
+/*   SH_NI1_LLP_CHAN_MODE_BITMODE32                                     */
+/*   Description:  Enables 32-bit (plus sideband) channel phits         */
+#define SH_NI1_LLP_CHAN_MODE_BITMODE32_SHFT      0
+#define SH_NI1_LLP_CHAN_MODE_BITMODE32_MASK      0x0000000000000001
+
+/*   SH_NI1_LLP_CHAN_MODE_AC_ENCODE                                     */
+/*   Description:  Enables nearly dc-free encoding for AC-coupling      */
+#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_SHFT      1
+#define SH_NI1_LLP_CHAN_MODE_AC_ENCODE_MASK      0x0000000000000002
+
+/*   SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING                                 */
+/*   Description:  Enables automatic tuning of channel skew.            */
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_SHFT  2
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_TUNING_MASK  0x0000000000000004
+
+/*   SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD                             */
+/*   Description:  Enables remote fine tune updates                     */
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_SHFT 3
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_RMT_FT_UPD_MASK 0x0000000000000008
+
+/*   SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD                                */
+/*   Description:  Enables quadrature clock in the pfssd                */
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_SHFT 4
+#define SH_NI1_LLP_CHAN_MODE_ENABLE_CLKQUAD_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CONFIG                        0x0000000150002020
+#define SH_NI1_LLP_CONFIG_MASK                   0x0000003fffffffff
+#define SH_NI1_LLP_CONFIG_INIT                   0x00000007fc6ffd00
+
+/*   SH_NI1_LLP_CONFIG_MAXBURST                                         */
+#define SH_NI1_LLP_CONFIG_MAXBURST_SHFT          0
+#define SH_NI1_LLP_CONFIG_MAXBURST_MASK          0x00000000000003ff
+
+/*   SH_NI1_LLP_CONFIG_MAXRETRY                                         */
+#define SH_NI1_LLP_CONFIG_MAXRETRY_SHFT          10
+#define SH_NI1_LLP_CONFIG_MAXRETRY_MASK          0x00000000000ffc00
+
+/*   SH_NI1_LLP_CONFIG_NULLTIMEOUT                                      */
+#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_SHFT       20
+#define SH_NI1_LLP_CONFIG_NULLTIMEOUT_MASK       0x0000000003f00000
+
+/*   SH_NI1_LLP_CONFIG_FTU_TIME                                         */
+#define SH_NI1_LLP_CONFIG_FTU_TIME_SHFT          26
+#define SH_NI1_LLP_CONFIG_FTU_TIME_MASK          0x0000003ffc000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_TEST_CTL                      0x0000000150002028
+#define SH_NI1_LLP_TEST_CTL_MASK                 0x7ff3f3ffffffffff
+#define SH_NI1_LLP_TEST_CTL_INIT                 0x000000000a5fffff
+
+/*   SH_NI1_LLP_TEST_CTL_PATTERN                                        */
+/*   Description:  Send channel data pattern                            */
+#define SH_NI1_LLP_TEST_CTL_PATTERN_SHFT         0
+#define SH_NI1_LLP_TEST_CTL_PATTERN_MASK         0x000000ffffffffff
+
+/*   SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE                                 */
+/*   Description:  Enables continuous send of data                      */
+#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_SHFT  40
+#define SH_NI1_LLP_TEST_CTL_SEND_TEST_MODE_MASK  0x0000030000000000
+
+/*   SH_NI1_LLP_TEST_CTL_WIRE_SEL                                       */
+#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_SHFT        44
+#define SH_NI1_LLP_TEST_CTL_WIRE_SEL_MASK        0x0003f00000000000
+
+/*   SH_NI1_LLP_TEST_CTL_LFSR_MODE                                      */
+#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_SHFT       52
+#define SH_NI1_LLP_TEST_CTL_LFSR_MODE_MASK       0x0030000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_NOISE_MODE                                     */
+#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_SHFT      54
+#define SH_NI1_LLP_TEST_CTL_NOISE_MODE_MASK      0x00c0000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_ARMCAPTURE                                     */
+/*   Description:  Enable Capture of Next MicroPacket                   */
+#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_SHFT      56
+#define SH_NI1_LLP_TEST_CTL_ARMCAPTURE_MASK      0x0100000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_CAPTURECBONLY                                  */
+/*   Description:  Only capture a micropacket with a Check Byte error  */
+#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_SHFT   57
+#define SH_NI1_LLP_TEST_CTL_CAPTURECBONLY_MASK   0x0200000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_SENDCBERROR                                    */
+/*   Description:  Sends a single error                                 */
+#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_SHFT     58
+#define SH_NI1_LLP_TEST_CTL_SENDCBERROR_MASK     0x0400000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_SENDSNERROR                                    */
+/*   Description:  Sends a single sequence number error                 */
+#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_SHFT     59
+#define SH_NI1_LLP_TEST_CTL_SENDSNERROR_MASK     0x0800000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_FAKESNERROR                                    */
+/*   Description:  Causes receiver to pretend it saw a sn error         */
+#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_SHFT     60
+#define SH_NI1_LLP_TEST_CTL_FAKESNERROR_MASK     0x1000000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_CAPTURED                                       */
+/*   Description:  Indicates a Valid Micropacket was captured           */
+#define SH_NI1_LLP_TEST_CTL_CAPTURED_SHFT        61
+#define SH_NI1_LLP_TEST_CTL_CAPTURED_MASK        0x2000000000000000
+
+/*   SH_NI1_LLP_TEST_CTL_CBERROR                                        */
+/*   Description:  Indicates a Micropacket with a CB error was capture  */
+#define SH_NI1_LLP_TEST_CTL_CBERROR_SHFT         62
+#define SH_NI1_LLP_TEST_CTL_CBERROR_MASK         0x4000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CAPT_WD1                      0x0000000150002030
+#define SH_NI1_LLP_CAPT_WD1_MASK                 0xffffffffffffffff
+#define SH_NI1_LLP_CAPT_WD1_INIT                 0x0000000000000000
+
+/*   SH_NI1_LLP_CAPT_WD1_DATA                                           */
+/*   Description:  low order 64-bit captured word                       */
+#define SH_NI1_LLP_CAPT_WD1_DATA_SHFT            0
+#define SH_NI1_LLP_CAPT_WD1_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CAPT_WD2                      0x0000000150002038
+#define SH_NI1_LLP_CAPT_WD2_MASK                 0xffffffffffffffff
+#define SH_NI1_LLP_CAPT_WD2_INIT                 0x0000000000000000
+
+/*   SH_NI1_LLP_CAPT_WD2_DATA                                           */
+/*   Description:  high order 64-bit captured word                      */
+#define SH_NI1_LLP_CAPT_WD2_DATA_SHFT            0
+#define SH_NI1_LLP_CAPT_WD2_DATA_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_CAPT_SBCB                     0x0000000150002040
+#define SH_NI1_LLP_CAPT_SBCB_MASK                0x0000001fffffffff
+#define SH_NI1_LLP_CAPT_SBCB_INIT                0x0000000000000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN                               */
+/*   Description:  sideband and sequence                                */
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_SHFT 0
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVSBSN_MASK 0x000000000000ffff
+
+/*   SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC                                */
+/*   Description:  CRC                                                  */
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_SHFT 16
+#define SH_NI1_LLP_CAPT_SBCB_CAPTUREDRCVCRC_MASK 0x00000000ffff0000
+
+/*   SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS                               */
+/*   Description:  All CB errors have been sent                         */
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_SHFT 32
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLCBERRORS_MASK 0x0000000100000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS                               */
+/*   Description:  All SN errors have been sent                         */
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_SHFT 33
+#define SH_NI1_LLP_CAPT_SBCB_SENTALLSNERRORS_MASK 0x0000000200000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS                              */
+/*   Description:  All faked SN errors have been sent                   */
+#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_SHFT 34
+#define SH_NI1_LLP_CAPT_SBCB_FAKEDALLSNERRORS_MASK 0x0000000400000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW                                */
+/*   Description:  wire charge counter overflowed, valid if llp_mode e  */
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_SHFT 35
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEOVERFLOW_MASK 0x0000000800000000
+
+/*   SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW                               */
+/*   Description:  wire charge counter underflowed, valid if llp_mode   */
+/*  enabled                                                             */
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_SHFT 36
+#define SH_NI1_LLP_CAPT_SBCB_CHARGEUNDERFLOW_MASK 0x0000001000000000
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_ERR"                       */
+/* ==================================================================== */
+
+#define SH_NI1_LLP_ERR                           0x0000000150002048
+#define SH_NI1_LLP_ERR_MASK                      0x001fffffffffffff
+#define SH_NI1_LLP_ERR_INIT                      0x0000000000000000
+
+/*   SH_NI1_LLP_ERR_RX_SN_ERR_COUNT                                     */
+/*   Description:  Counts the sequence number errors received           */
+#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_SHFT      0
+#define SH_NI1_LLP_ERR_RX_SN_ERR_COUNT_MASK      0x00000000000000ff
+
+/*   SH_NI1_LLP_ERR_RX_CB_ERR_COUNT                                     */
+/*   Description:  Counts the check byte errors received                */
+#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_SHFT      8
+#define SH_NI1_LLP_ERR_RX_CB_ERR_COUNT_MASK      0x000000000000ff00
+
+/*   SH_NI1_LLP_ERR_RETRY_COUNT                                         */
+/*   Description:  Counts the retries                                   */
+#define SH_NI1_LLP_ERR_RETRY_COUNT_SHFT          16
+#define SH_NI1_LLP_ERR_RETRY_COUNT_MASK          0x0000000000ff0000
+
+/*   SH_NI1_LLP_ERR_RETRY_TIMEOUT                                       */
+/*   Description:  Indicates a retry timeout has occured                */
+#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_SHFT        24
+#define SH_NI1_LLP_ERR_RETRY_TIMEOUT_MASK        0x0000000001000000
+
+/*   SH_NI1_LLP_ERR_RCV_LINK_RESET                                      */
+/*   Description:  Indicates a link reset has been received             */
+#define SH_NI1_LLP_ERR_RCV_LINK_RESET_SHFT       25
+#define SH_NI1_LLP_ERR_RCV_LINK_RESET_MASK       0x0000000002000000
+
+/*   SH_NI1_LLP_ERR_SQUASH                                              */
+/*   Description:  Indicates a micropacket was squashed                 */
+#define SH_NI1_LLP_ERR_SQUASH_SHFT               26
+#define SH_NI1_LLP_ERR_SQUASH_MASK               0x0000000004000000
+
+/*   SH_NI1_LLP_ERR_POWER_NOT_OK                                        */
+/*   Description:  Detects and traps a loss of power_OK                 */
+#define SH_NI1_LLP_ERR_POWER_NOT_OK_SHFT         27
+#define SH_NI1_LLP_ERR_POWER_NOT_OK_MASK         0x0000000008000000
+
+/*   SH_NI1_LLP_ERR_WIRE_CNT                                            */
+/*   Description:  counts the errors detected on a single wire test     */
+#define SH_NI1_LLP_ERR_WIRE_CNT_SHFT             28
+#define SH_NI1_LLP_ERR_WIRE_CNT_MASK             0x000ffffff0000000
+
+/*   SH_NI1_LLP_ERR_WIRE_OVERFLOW                                       */
+/*   Description:  wire_error_cnt has overflowed                        */
+#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_SHFT        52
+#define SH_NI1_LLP_ERR_WIRE_OVERFLOW_MASK        0x0010000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW              0x0000000150001010
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW              0x0000000150001020
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_LLP_DEBIT_FLOW                  0x0000000150001030
+#define SH_XNNI0_LLP_DEBIT_FLOW_MASK             0x1f1f1f1f1f1f1f1f
+#define SH_XNNI0_LLP_DEBIT_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN                              */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP                              */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN                              */
+/*   Description:  vc1 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP                              */
+/*   Description:  vc1 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN                              */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP                              */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN                              */
+/*   Description:  vc3 debit dynamic value                              */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000
+
+/*   SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP                              */
+/*   Description:  vc3 debit captured value                             */
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56
+#define SH_XNNI0_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_0_FLOW                     0x0000000150001040
+#define SH_XNNI0_LINK_0_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_0_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD                            */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED                          */
+/*   Description:  Force Credit on vc0 from debit cntr                  */
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST                               */
+/*   Description:  vc0 Limit Test                                       */
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN                                */
+/*   Description:  Dynamic vc0 credit value                             */
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP                                */
+/*   Description:  Captured vc0 credit                                  */
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24
+#define SH_XNNI0_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_1_FLOW                     0x0000000150001050
+#define SH_XNNI0_LINK_1_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_1_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD                            */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED                          */
+/*   Description:  Force Credit on vc1 from debit cntr                  */
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST                               */
+/*   Description:  vc1 Limit Test                                       */
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN                                */
+/*   Description:  Dynamic vc1 credit value                             */
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP                                */
+/*   Description:  Captured vc1 credit                                  */
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24
+#define SH_XNNI0_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_2_FLOW                     0x0000000150001060
+#define SH_XNNI0_LINK_2_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_2_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD                            */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED                          */
+/*   Description:  Force Credit on vc2 from debit cntr                  */
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST                               */
+/*   Description:  vc2 Limit Test                                       */
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN                                */
+/*   Description:  Dynamic vc2 credit value                             */
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP                                */
+/*   Description:  Captured vc2 credit                                  */
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24
+#define SH_XNNI0_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_LINK_3_FLOW                     0x0000000150001070
+#define SH_XNNI0_LINK_3_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI0_LINK_3_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD                            */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED                          */
+/*   Description:  Force Credit on vc3 from debit cntr                  */
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI0_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST                               */
+/*   Description:  vc3 Limit Test                                       */
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN                                */
+/*   Description:  Dynamic vc3 credit value                             */
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP                                */
+/*   Description:  Captured vc3 credit                                  */
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24
+#define SH_XNNI0_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW              0x0000000150003010
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_LLP_TO_FIFO02_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW              0x0000000150003020
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_MASK         0x3f3f003f3f00bfbf
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_INIT         0x0000000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_LLP_TO_FIFO13_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_LLP_DEBIT_FLOW                  0x0000000150003030
+#define SH_XNNI1_LLP_DEBIT_FLOW_MASK             0x1f1f1f1f1f1f1f1f
+#define SH_XNNI1_LLP_DEBIT_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN                              */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_SHFT 0
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_DYN_MASK 0x000000000000001f
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP                              */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_SHFT 8
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC0_CAP_MASK 0x0000000000001f00
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN                              */
+/*   Description:  vc1 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_SHFT 16
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_DYN_MASK 0x00000000001f0000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP                              */
+/*   Description:  vc1 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_SHFT 24
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC1_CAP_MASK 0x000000001f000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN                              */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_DYN_MASK 0x0000001f00000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP                              */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC2_CAP_MASK 0x00001f0000000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN                              */
+/*   Description:  vc3 debit dynamic value                              */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_SHFT 48
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_DYN_MASK 0x001f000000000000
+
+/*   SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP                              */
+/*   Description:  vc3 debit captured value                             */
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_SHFT 56
+#define SH_XNNI1_LLP_DEBIT_FLOW_DEBIT_VC3_CAP_MASK 0x1f00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_0_FLOW                     0x0000000150003040
+#define SH_XNNI1_LINK_0_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_0_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD                            */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED                          */
+/*   Description:  Force Credit on vc0 from debit cntr                  */
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_0_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST                               */
+/*   Description:  vc0 Limit Test                                       */
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_SHFT 8
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN                                */
+/*   Description:  Dynamic vc0 credit value                             */
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_SHFT 16
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP                                */
+/*   Description:  Captured vc0 credit                                  */
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_SHFT 24
+#define SH_XNNI1_LINK_0_FLOW_CREDIT_VC0_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_1_FLOW                     0x0000000150003050
+#define SH_XNNI1_LINK_1_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_1_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD                            */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED                          */
+/*   Description:  Force Credit on vc1 from debit cntr                  */
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_1_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST                               */
+/*   Description:  vc1 Limit Test                                       */
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_SHFT 8
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN                                */
+/*   Description:  Dynamic vc1 credit value                             */
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_SHFT 16
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP                                */
+/*   Description:  Captured vc1 credit                                  */
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_SHFT 24
+#define SH_XNNI1_LINK_1_FLOW_CREDIT_VC1_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_2_FLOW                     0x0000000150003060
+#define SH_XNNI1_LINK_2_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_2_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD                            */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED                          */
+/*   Description:  Force Credit on vc2 from debit cntr                  */
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_2_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST                               */
+/*   Description:  vc2 Limit Test                                       */
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_SHFT 8
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN                                */
+/*   Description:  Dynamic vc2 credit value                             */
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_SHFT 16
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP                                */
+/*   Description:  Captured vc2 credit                                  */
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_SHFT 24
+#define SH_XNNI1_LINK_2_FLOW_CREDIT_VC2_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_LINK_3_FLOW                     0x0000000150003070
+#define SH_XNNI1_LINK_3_FLOW_MASK                0x000000007f7f7fbf
+#define SH_XNNI1_LINK_3_FLOW_INIT                0x0000000000001800
+
+/*   SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD                            */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED                          */
+/*   Description:  Force Credit on vc3 from debit cntr                  */
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI1_LINK_3_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST                               */
+/*   Description:  vc3 Limit Test                                       */
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_SHFT 8
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_TEST_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN                                */
+/*   Description:  Dynamic vc3 credit value                             */
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_SHFT 16
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_DYN_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP                                */
+/*   Description:  Captured vc3 credit                                  */
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_SHFT 24
+#define SH_XNNI1_LINK_3_FLOW_CREDIT_VC3_CAP_MASK 0x000000007f000000
+
+/* ==================================================================== */
+/*                    Register "SH_IILB_LOCAL_TABLE"                    */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_IILB_LOCAL_TABLE                      0x0000000150020000
+#define SH_IILB_LOCAL_TABLE_MASK                 0x800000000000003f
+#define SH_IILB_LOCAL_TABLE_MEMDEPTH             128
+#define SH_IILB_LOCAL_TABLE_INIT                 0x0000000000000000
+
+/*   SH_IILB_LOCAL_TABLE_DIR0                                           */
+/*   Description:  Direction field for next chip                        */
+#define SH_IILB_LOCAL_TABLE_DIR0_SHFT            0
+#define SH_IILB_LOCAL_TABLE_DIR0_MASK            0x000000000000000f
+
+/*   SH_IILB_LOCAL_TABLE_V0                                             */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_IILB_LOCAL_TABLE_V0_SHFT              4
+#define SH_IILB_LOCAL_TABLE_V0_MASK              0x0000000000000010
+
+/*   SH_IILB_LOCAL_TABLE_NI_SEL0                                        */
+/*   Description:  ni select for requests                               */
+#define SH_IILB_LOCAL_TABLE_NI_SEL0_SHFT         5
+#define SH_IILB_LOCAL_TABLE_NI_SEL0_MASK         0x0000000000000020
+
+/*   SH_IILB_LOCAL_TABLE_VALID                                          */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_IILB_LOCAL_TABLE_VALID_SHFT           63
+#define SH_IILB_LOCAL_TABLE_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_IILB_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_IILB_GLOBAL_TABLE                     0x0000000150020400
+#define SH_IILB_GLOBAL_TABLE_MASK                0x800000000000003f
+#define SH_IILB_GLOBAL_TABLE_MEMDEPTH            16
+#define SH_IILB_GLOBAL_TABLE_INIT                0x0000000000000000
+
+/*   SH_IILB_GLOBAL_TABLE_DIR0                                          */
+/*   Description:  Direction field for next chip                        */
+#define SH_IILB_GLOBAL_TABLE_DIR0_SHFT           0
+#define SH_IILB_GLOBAL_TABLE_DIR0_MASK           0x000000000000000f
+
+/*   SH_IILB_GLOBAL_TABLE_V0                                            */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_IILB_GLOBAL_TABLE_V0_SHFT             4
+#define SH_IILB_GLOBAL_TABLE_V0_MASK             0x0000000000000010
+
+/*   SH_IILB_GLOBAL_TABLE_NI_SEL0                                       */
+/*   Description:  ni select for requests                               */
+#define SH_IILB_GLOBAL_TABLE_NI_SEL0_SHFT        5
+#define SH_IILB_GLOBAL_TABLE_NI_SEL0_MASK        0x0000000000000020
+
+/*   SH_IILB_GLOBAL_TABLE_VALID                                         */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_IILB_GLOBAL_TABLE_VALID_SHFT          63
+#define SH_IILB_GLOBAL_TABLE_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_OVER_RIDE_TABLE"                  */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_IILB_OVER_RIDE_TABLE                  0x0000000150020480
+#define SH_IILB_OVER_RIDE_TABLE_MASK             0x800000000000003f
+#define SH_IILB_OVER_RIDE_TABLE_INIT             0x8000000000000000
+
+/*   SH_IILB_OVER_RIDE_TABLE_DIR0                                       */
+/*   Description:  Direction field for next chip                        */
+#define SH_IILB_OVER_RIDE_TABLE_DIR0_SHFT        0
+#define SH_IILB_OVER_RIDE_TABLE_DIR0_MASK        0x000000000000000f
+
+/*   SH_IILB_OVER_RIDE_TABLE_V0                                         */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_IILB_OVER_RIDE_TABLE_V0_SHFT          4
+#define SH_IILB_OVER_RIDE_TABLE_V0_MASK          0x0000000000000010
+
+/*   SH_IILB_OVER_RIDE_TABLE_NI_SEL0                                    */
+/*   Description:  ni select                                            */
+#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_SHFT     5
+#define SH_IILB_OVER_RIDE_TABLE_NI_SEL0_MASK     0x0000000000000020
+
+/*   SH_IILB_OVER_RIDE_TABLE_ENABLE                                     */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_IILB_OVER_RIDE_TABLE_ENABLE_SHFT      63
+#define SH_IILB_OVER_RIDE_TABLE_ENABLE_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_IILB_RSP_PLANE_HINT                   0x0000000150020488
+#define SH_IILB_RSP_PLANE_HINT_MASK              0x0000000000000000
+#define SH_IILB_RSP_PLANE_HINT_INIT              0x0000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_PI_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_PI_LOCAL_TABLE                        0x0000000150021000
+#define SH_PI_LOCAL_TABLE_MASK                   0x8000000000003f3f
+#define SH_PI_LOCAL_TABLE_MEMDEPTH               128
+#define SH_PI_LOCAL_TABLE_INIT                   0x0000000000000000
+
+/*   SH_PI_LOCAL_TABLE_DIR0                                             */
+/*   Description:  Direction field for next chip                        */
+#define SH_PI_LOCAL_TABLE_DIR0_SHFT              0
+#define SH_PI_LOCAL_TABLE_DIR0_MASK              0x000000000000000f
+
+/*   SH_PI_LOCAL_TABLE_V0                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_LOCAL_TABLE_V0_SHFT                4
+#define SH_PI_LOCAL_TABLE_V0_MASK                0x0000000000000010
+
+/*   SH_PI_LOCAL_TABLE_NI_SEL0                                          */
+/*   Description:  ni select for requests                               */
+#define SH_PI_LOCAL_TABLE_NI_SEL0_SHFT           5
+#define SH_PI_LOCAL_TABLE_NI_SEL0_MASK           0x0000000000000020
+
+/*   SH_PI_LOCAL_TABLE_DIR1                                             */
+#define SH_PI_LOCAL_TABLE_DIR1_SHFT              8
+#define SH_PI_LOCAL_TABLE_DIR1_MASK              0x0000000000000f00
+
+/*   SH_PI_LOCAL_TABLE_V1                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_LOCAL_TABLE_V1_SHFT                12
+#define SH_PI_LOCAL_TABLE_V1_MASK                0x0000000000001000
+
+/*   SH_PI_LOCAL_TABLE_NI_SEL1                                          */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_PI_LOCAL_TABLE_NI_SEL1_SHFT           13
+#define SH_PI_LOCAL_TABLE_NI_SEL1_MASK           0x0000000000002000
+
+/*   SH_PI_LOCAL_TABLE_VALID                                            */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_PI_LOCAL_TABLE_VALID_SHFT             63
+#define SH_PI_LOCAL_TABLE_VALID_MASK             0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_PI_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_PI_GLOBAL_TABLE                       0x0000000150021400
+#define SH_PI_GLOBAL_TABLE_MASK                  0x8000000000003f3f
+#define SH_PI_GLOBAL_TABLE_MEMDEPTH              16
+#define SH_PI_GLOBAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_PI_GLOBAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_PI_GLOBAL_TABLE_DIR0_SHFT             0
+#define SH_PI_GLOBAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_PI_GLOBAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_GLOBAL_TABLE_V0_SHFT               4
+#define SH_PI_GLOBAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_PI_GLOBAL_TABLE_NI_SEL0                                         */
+/*   Description:  ni select for requests                               */
+#define SH_PI_GLOBAL_TABLE_NI_SEL0_SHFT          5
+#define SH_PI_GLOBAL_TABLE_NI_SEL0_MASK          0x0000000000000020
+
+/*   SH_PI_GLOBAL_TABLE_DIR1                                            */
+#define SH_PI_GLOBAL_TABLE_DIR1_SHFT             8
+#define SH_PI_GLOBAL_TABLE_DIR1_MASK             0x0000000000000f00
+
+/*   SH_PI_GLOBAL_TABLE_V1                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_GLOBAL_TABLE_V1_SHFT               12
+#define SH_PI_GLOBAL_TABLE_V1_MASK               0x0000000000001000
+
+/*   SH_PI_GLOBAL_TABLE_NI_SEL1                                         */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_PI_GLOBAL_TABLE_NI_SEL1_SHFT          13
+#define SH_PI_GLOBAL_TABLE_NI_SEL1_MASK          0x0000000000002000
+
+/*   SH_PI_GLOBAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_PI_GLOBAL_TABLE_VALID_SHFT            63
+#define SH_PI_GLOBAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_PI_OVER_RIDE_TABLE                    0x0000000150021480
+#define SH_PI_OVER_RIDE_TABLE_MASK               0x8000000000003f3f
+#define SH_PI_OVER_RIDE_TABLE_INIT               0x8000000000002000
+
+/*   SH_PI_OVER_RIDE_TABLE_DIR0                                         */
+/*   Description:  Direction field for next chip                        */
+#define SH_PI_OVER_RIDE_TABLE_DIR0_SHFT          0
+#define SH_PI_OVER_RIDE_TABLE_DIR0_MASK          0x000000000000000f
+
+/*   SH_PI_OVER_RIDE_TABLE_V0                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_OVER_RIDE_TABLE_V0_SHFT            4
+#define SH_PI_OVER_RIDE_TABLE_V0_MASK            0x0000000000000010
+
+/*   SH_PI_OVER_RIDE_TABLE_NI_SEL0                                      */
+/*   Description:  ni select                                            */
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_SHFT       5
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL0_MASK       0x0000000000000020
+
+/*   SH_PI_OVER_RIDE_TABLE_DIR1                                         */
+#define SH_PI_OVER_RIDE_TABLE_DIR1_SHFT          8
+#define SH_PI_OVER_RIDE_TABLE_DIR1_MASK          0x0000000000000f00
+
+/*   SH_PI_OVER_RIDE_TABLE_V1                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_PI_OVER_RIDE_TABLE_V1_SHFT            12
+#define SH_PI_OVER_RIDE_TABLE_V1_MASK            0x0000000000001000
+
+/*   SH_PI_OVER_RIDE_TABLE_NI_SEL1                                      */
+/*   Description:  ni select                                            */
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_SHFT       13
+#define SH_PI_OVER_RIDE_TABLE_NI_SEL1_MASK       0x0000000000002000
+
+/*   SH_PI_OVER_RIDE_TABLE_ENABLE                                       */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_PI_OVER_RIDE_TABLE_ENABLE_SHFT        63
+#define SH_PI_OVER_RIDE_TABLE_ENABLE_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_PI_RSP_PLANE_HINT                     0x0000000150021488
+#define SH_PI_RSP_PLANE_HINT_MASK                0x0000000000000001
+#define SH_PI_RSP_PLANE_HINT_INIT                0x0000000000000000
+
+/*   SH_PI_RSP_PLANE_HINT_INVERT                                        */
+/*   Description:  Invert Response Plane Hint                           */
+#define SH_PI_RSP_PLANE_HINT_INVERT_SHFT         0
+#define SH_PI_RSP_PLANE_HINT_INVERT_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI0_LOCAL_TABLE                       0x0000000150022000
+#define SH_NI0_LOCAL_TABLE_MASK                  0x800000000000001f
+#define SH_NI0_LOCAL_TABLE_MEMDEPTH              128
+#define SH_NI0_LOCAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_NI0_LOCAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI0_LOCAL_TABLE_DIR0_SHFT             0
+#define SH_NI0_LOCAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_NI0_LOCAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI0_LOCAL_TABLE_V0_SHFT               4
+#define SH_NI0_LOCAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_NI0_LOCAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI0_LOCAL_TABLE_VALID_SHFT            63
+#define SH_NI0_LOCAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI0_GLOBAL_TABLE                      0x0000000150022400
+#define SH_NI0_GLOBAL_TABLE_MASK                 0x800000000000001f
+#define SH_NI0_GLOBAL_TABLE_MEMDEPTH             16
+#define SH_NI0_GLOBAL_TABLE_INIT                 0x0000000000000000
+
+/*   SH_NI0_GLOBAL_TABLE_DIR0                                           */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI0_GLOBAL_TABLE_DIR0_SHFT            0
+#define SH_NI0_GLOBAL_TABLE_DIR0_MASK            0x000000000000000f
+
+/*   SH_NI0_GLOBAL_TABLE_V0                                             */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI0_GLOBAL_TABLE_V0_SHFT              4
+#define SH_NI0_GLOBAL_TABLE_V0_MASK              0x0000000000000010
+
+/*   SH_NI0_GLOBAL_TABLE_VALID                                          */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI0_GLOBAL_TABLE_VALID_SHFT           63
+#define SH_NI0_GLOBAL_TABLE_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_NI0_OVER_RIDE_TABLE                   0x0000000150022480
+#define SH_NI0_OVER_RIDE_TABLE_MASK              0x800000000000001f
+#define SH_NI0_OVER_RIDE_TABLE_INIT              0x8000000000000000
+
+/*   SH_NI0_OVER_RIDE_TABLE_DIR0                                        */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI0_OVER_RIDE_TABLE_DIR0_SHFT         0
+#define SH_NI0_OVER_RIDE_TABLE_DIR0_MASK         0x000000000000000f
+
+/*   SH_NI0_OVER_RIDE_TABLE_V0                                          */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI0_OVER_RIDE_TABLE_V0_SHFT           4
+#define SH_NI0_OVER_RIDE_TABLE_V0_MASK           0x0000000000000010
+
+/*   SH_NI0_OVER_RIDE_TABLE_ENABLE                                      */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_NI0_OVER_RIDE_TABLE_ENABLE_SHFT       63
+#define SH_NI0_OVER_RIDE_TABLE_ENABLE_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_NI0_RSP_PLANE_HINT                    0x0000000150022488
+#define SH_NI0_RSP_PLANE_HINT_MASK               0x0000000000000000
+#define SH_NI0_RSP_PLANE_HINT_INIT               0x0000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI1_LOCAL_TABLE                       0x0000000150023000
+#define SH_NI1_LOCAL_TABLE_MASK                  0x800000000000001f
+#define SH_NI1_LOCAL_TABLE_MEMDEPTH              128
+#define SH_NI1_LOCAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_NI1_LOCAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI1_LOCAL_TABLE_DIR0_SHFT             0
+#define SH_NI1_LOCAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_NI1_LOCAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI1_LOCAL_TABLE_V0_SHFT               4
+#define SH_NI1_LOCAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_NI1_LOCAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI1_LOCAL_TABLE_VALID_SHFT            63
+#define SH_NI1_LOCAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_NI1_GLOBAL_TABLE                      0x0000000150023400
+#define SH_NI1_GLOBAL_TABLE_MASK                 0x800000000000001f
+#define SH_NI1_GLOBAL_TABLE_MEMDEPTH             16
+#define SH_NI1_GLOBAL_TABLE_INIT                 0x0000000000000000
+
+/*   SH_NI1_GLOBAL_TABLE_DIR0                                           */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI1_GLOBAL_TABLE_DIR0_SHFT            0
+#define SH_NI1_GLOBAL_TABLE_DIR0_MASK            0x000000000000000f
+
+/*   SH_NI1_GLOBAL_TABLE_V0                                             */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI1_GLOBAL_TABLE_V0_SHFT              4
+#define SH_NI1_GLOBAL_TABLE_V0_MASK              0x0000000000000010
+
+/*   SH_NI1_GLOBAL_TABLE_VALID                                          */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_NI1_GLOBAL_TABLE_VALID_SHFT           63
+#define SH_NI1_GLOBAL_TABLE_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_NI1_OVER_RIDE_TABLE                   0x0000000150023480
+#define SH_NI1_OVER_RIDE_TABLE_MASK              0x800000000000001f
+#define SH_NI1_OVER_RIDE_TABLE_INIT              0x8000000000000000
+
+/*   SH_NI1_OVER_RIDE_TABLE_DIR0                                        */
+/*   Description:  Direction field for next chip                        */
+#define SH_NI1_OVER_RIDE_TABLE_DIR0_SHFT         0
+#define SH_NI1_OVER_RIDE_TABLE_DIR0_MASK         0x000000000000000f
+
+/*   SH_NI1_OVER_RIDE_TABLE_V0                                          */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_NI1_OVER_RIDE_TABLE_V0_SHFT           4
+#define SH_NI1_OVER_RIDE_TABLE_V0_MASK           0x0000000000000010
+
+/*   SH_NI1_OVER_RIDE_TABLE_ENABLE                                      */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_NI1_OVER_RIDE_TABLE_ENABLE_SHFT       63
+#define SH_NI1_OVER_RIDE_TABLE_ENABLE_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_NI1_RSP_PLANE_HINT                    0x0000000150023488
+#define SH_NI1_RSP_PLANE_HINT_MASK               0x0000000000000000
+#define SH_NI1_RSP_PLANE_HINT_INIT               0x0000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#define SH_MD_LOCAL_TABLE                        0x0000000150024000
+#define SH_MD_LOCAL_TABLE_MASK                   0x8000000000003f3f
+#define SH_MD_LOCAL_TABLE_MEMDEPTH               128
+#define SH_MD_LOCAL_TABLE_INIT                   0x0000000000000000
+
+/*   SH_MD_LOCAL_TABLE_DIR0                                             */
+/*   Description:  Direction field for next chip                        */
+#define SH_MD_LOCAL_TABLE_DIR0_SHFT              0
+#define SH_MD_LOCAL_TABLE_DIR0_MASK              0x000000000000000f
+
+/*   SH_MD_LOCAL_TABLE_V0                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_LOCAL_TABLE_V0_SHFT                4
+#define SH_MD_LOCAL_TABLE_V0_MASK                0x0000000000000010
+
+/*   SH_MD_LOCAL_TABLE_NI_SEL0                                          */
+/*   Description:  ni select for requests                               */
+#define SH_MD_LOCAL_TABLE_NI_SEL0_SHFT           5
+#define SH_MD_LOCAL_TABLE_NI_SEL0_MASK           0x0000000000000020
+
+/*   SH_MD_LOCAL_TABLE_DIR1                                             */
+#define SH_MD_LOCAL_TABLE_DIR1_SHFT              8
+#define SH_MD_LOCAL_TABLE_DIR1_MASK              0x0000000000000f00
+
+/*   SH_MD_LOCAL_TABLE_V1                                               */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_LOCAL_TABLE_V1_SHFT                12
+#define SH_MD_LOCAL_TABLE_V1_MASK                0x0000000000001000
+
+/*   SH_MD_LOCAL_TABLE_NI_SEL1                                          */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_MD_LOCAL_TABLE_NI_SEL1_SHFT           13
+#define SH_MD_LOCAL_TABLE_NI_SEL1_MASK           0x0000000000002000
+
+/*   SH_MD_LOCAL_TABLE_VALID                                            */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_MD_LOCAL_TABLE_VALID_SHFT             63
+#define SH_MD_LOCAL_TABLE_VALID_MASK             0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#define SH_MD_GLOBAL_TABLE                       0x0000000150024400
+#define SH_MD_GLOBAL_TABLE_MASK                  0x8000000000003f3f
+#define SH_MD_GLOBAL_TABLE_MEMDEPTH              16
+#define SH_MD_GLOBAL_TABLE_INIT                  0x0000000000000000
+
+/*   SH_MD_GLOBAL_TABLE_DIR0                                            */
+/*   Description:  Direction field for next chip                        */
+#define SH_MD_GLOBAL_TABLE_DIR0_SHFT             0
+#define SH_MD_GLOBAL_TABLE_DIR0_MASK             0x000000000000000f
+
+/*   SH_MD_GLOBAL_TABLE_V0                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_GLOBAL_TABLE_V0_SHFT               4
+#define SH_MD_GLOBAL_TABLE_V0_MASK               0x0000000000000010
+
+/*   SH_MD_GLOBAL_TABLE_NI_SEL0                                         */
+/*   Description:  ni select for requests                               */
+#define SH_MD_GLOBAL_TABLE_NI_SEL0_SHFT          5
+#define SH_MD_GLOBAL_TABLE_NI_SEL0_MASK          0x0000000000000020
+
+/*   SH_MD_GLOBAL_TABLE_DIR1                                            */
+#define SH_MD_GLOBAL_TABLE_DIR1_SHFT             8
+#define SH_MD_GLOBAL_TABLE_DIR1_MASK             0x0000000000000f00
+
+/*   SH_MD_GLOBAL_TABLE_V1                                              */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_GLOBAL_TABLE_V1_SHFT               12
+#define SH_MD_GLOBAL_TABLE_V1_MASK               0x0000000000001000
+
+/*   SH_MD_GLOBAL_TABLE_NI_SEL1                                         */
+/*   Description:  ni select for plane-hint 1                           */
+#define SH_MD_GLOBAL_TABLE_NI_SEL1_SHFT          13
+#define SH_MD_GLOBAL_TABLE_NI_SEL1_MASK          0x0000000000002000
+
+/*   SH_MD_GLOBAL_TABLE_VALID                                           */
+/*   Description:  Indicates that this entry is valid                   */
+#define SH_MD_GLOBAL_TABLE_VALID_SHFT            63
+#define SH_MD_GLOBAL_TABLE_VALID_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#define SH_MD_OVER_RIDE_TABLE                    0x0000000150024480
+#define SH_MD_OVER_RIDE_TABLE_MASK               0x8000000000003f3f
+#define SH_MD_OVER_RIDE_TABLE_INIT               0x8000000000002000
+
+/*   SH_MD_OVER_RIDE_TABLE_DIR0                                         */
+/*   Description:  Direction field for next chip                        */
+#define SH_MD_OVER_RIDE_TABLE_DIR0_SHFT          0
+#define SH_MD_OVER_RIDE_TABLE_DIR0_MASK          0x000000000000000f
+
+/*   SH_MD_OVER_RIDE_TABLE_V0                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_OVER_RIDE_TABLE_V0_SHFT            4
+#define SH_MD_OVER_RIDE_TABLE_V0_MASK            0x0000000000000010
+
+/*   SH_MD_OVER_RIDE_TABLE_NI_SEL0                                      */
+/*   Description:  ni select                                            */
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_SHFT       5
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL0_MASK       0x0000000000000020
+
+/*   SH_MD_OVER_RIDE_TABLE_DIR1                                         */
+#define SH_MD_OVER_RIDE_TABLE_DIR1_SHFT          8
+#define SH_MD_OVER_RIDE_TABLE_DIR1_MASK          0x0000000000000f00
+
+/*   SH_MD_OVER_RIDE_TABLE_V1                                           */
+/*   Description:  Low bit of virtual channel for next chip             */
+#define SH_MD_OVER_RIDE_TABLE_V1_SHFT            12
+#define SH_MD_OVER_RIDE_TABLE_V1_MASK            0x0000000000001000
+
+/*   SH_MD_OVER_RIDE_TABLE_NI_SEL1                                      */
+/*   Description:  ni select                                            */
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_SHFT       13
+#define SH_MD_OVER_RIDE_TABLE_NI_SEL1_MASK       0x0000000000002000
+
+/*   SH_MD_OVER_RIDE_TABLE_ENABLE                                       */
+/*   Description:  Indicates that this entry is enabled                 */
+#define SH_MD_OVER_RIDE_TABLE_ENABLE_SHFT        63
+#define SH_MD_OVER_RIDE_TABLE_ENABLE_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#define SH_MD_RSP_PLANE_HINT                     0x0000000150024488
+#define SH_MD_RSP_PLANE_HINT_MASK                0x0000000000000001
+#define SH_MD_RSP_PLANE_HINT_INIT                0x0000000000000000
+
+/*   SH_MD_RSP_PLANE_HINT_INVERT                                        */
+/*   Description:  Invert Response Plane Hint                           */
+#define SH_MD_RSP_PLANE_HINT_INVERT_SHFT         0
+#define SH_MD_RSP_PLANE_HINT_INVERT_MASK         0x0000000000000001
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LIQ_CTL"                       */
+/*                       Local Block LIQ Control                        */
+/* ==================================================================== */
+
+#define SH_LB_LIQ_CTL                            0x0000000110040000
+#define SH_LB_LIQ_CTL_MASK                       0x0000000000070f1f
+#define SH_LB_LIQ_CTL_INIT                       0x0000000000000000
+
+/*   SH_LB_LIQ_CTL_LIQ_REQ_CTL                                          */
+/*   Description:  LIQ Request Control                                  */
+#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_SHFT           0
+#define SH_LB_LIQ_CTL_LIQ_REQ_CTL_MASK           0x000000000000001f
+
+/*   SH_LB_LIQ_CTL_LIQ_RPL_CTL                                          */
+/*   Description:  LIQ Reply Control                                    */
+#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_SHFT           8
+#define SH_LB_LIQ_CTL_LIQ_RPL_CTL_MASK           0x0000000000000f00
+
+/*   SH_LB_LIQ_CTL_FORCE_RQ_CREDIT                                      */
+/*   Description:  Force request credit                                 */
+#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_SHFT       16
+#define SH_LB_LIQ_CTL_FORCE_RQ_CREDIT_MASK       0x0000000000010000
+
+/*   SH_LB_LIQ_CTL_FORCE_RP_CREDIT                                      */
+/*   Description:  Force reply credit                                   */
+#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_SHFT       17
+#define SH_LB_LIQ_CTL_FORCE_RP_CREDIT_MASK       0x0000000000020000
+
+/*   SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT                                   */
+/*   Description:  Force linvv credit                                   */
+#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_SHFT    18
+#define SH_LB_LIQ_CTL_FORCE_LINVV_CREDIT_MASK    0x0000000000040000
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LOQ_CTL"                       */
+/*                       Local Block LOQ Control                        */
+/* ==================================================================== */
+
+#define SH_LB_LOQ_CTL                            0x0000000110040080
+#define SH_LB_LOQ_CTL_MASK                       0x0000000000000003
+#define SH_LB_LOQ_CTL_INIT                       0x0000000000000000
+
+/*   SH_LB_LOQ_CTL_LOQ_REQ_CTL                                          */
+/*   Description:  LOQ Request Control                                  */
+#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_SHFT           0
+#define SH_LB_LOQ_CTL_LOQ_REQ_CTL_MASK           0x0000000000000001
+
+/*   SH_LB_LOQ_CTL_LOQ_RPL_CTL                                          */
+/*   Description:  LOQ Reply Control                                    */
+#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_SHFT           1
+#define SH_LB_LOQ_CTL_LOQ_RPL_CTL_MASK           0x0000000000000002
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REP_CREDIT_CNT"                  */
+/*               Maximum number of reply credits from XN                */
+/* ==================================================================== */
+
+#define SH_LB_MAX_REP_CREDIT_CNT                 0x0000000110040100
+#define SH_LB_MAX_REP_CREDIT_CNT_MASK            0x000000000000001f
+#define SH_LB_MAX_REP_CREDIT_CNT_INIT            0x000000000000001f
+
+/*   SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT                                   */
+/*   Description:  Max reply credits                                    */
+#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_SHFT    0
+#define SH_LB_MAX_REP_CREDIT_CNT_MAX_CNT_MASK    0x000000000000001f
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REQ_CREDIT_CNT"                  */
+/*              Maximum number of request credits from XN               */
+/* ==================================================================== */
+
+#define SH_LB_MAX_REQ_CREDIT_CNT                 0x0000000110040180
+#define SH_LB_MAX_REQ_CREDIT_CNT_MASK            0x000000000000001f
+#define SH_LB_MAX_REQ_CREDIT_CNT_INIT            0x000000000000001f
+
+/*   SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT                                   */
+/*   Description:  Max request credits                                  */
+#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_SHFT    0
+#define SH_LB_MAX_REQ_CREDIT_CNT_MAX_CNT_MASK    0x000000000000001f
+
+/* ==================================================================== */
+/*                      Register "SH_PIO_TIME_OUT"                      */
+/*                    Local Block PIO time out value                    */
+/* ==================================================================== */
+
+#define SH_PIO_TIME_OUT                          0x0000000110040200
+#define SH_PIO_TIME_OUT_MASK                     0x000000000000ffff
+#define SH_PIO_TIME_OUT_INIT                     0x0000000000000400
+
+/*   SH_PIO_TIME_OUT_VALUE                                              */
+/*   Description:  PIO time out value                                   */
+#define SH_PIO_TIME_OUT_VALUE_SHFT               0
+#define SH_PIO_TIME_OUT_VALUE_MASK               0x000000000000ffff
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_NACK_RESET"                     */
+/*               Local Block PIO Reset for nack counters                */
+/* ==================================================================== */
+
+#define SH_PIO_NACK_RESET                        0x0000000110040280
+#define SH_PIO_NACK_RESET_MASK                   0x0000000000000001
+#define SH_PIO_NACK_RESET_INIT                   0x0000000000000000
+
+/*   SH_PIO_NACK_RESET_PULSE                                            */
+/*   Description:  PIO nack counter reset                               */
+#define SH_PIO_NACK_RESET_PULSE_SHFT             0
+#define SH_PIO_NACK_RESET_PULSE_MASK             0x0000000000000001
+
+/* ==================================================================== */
+/*                 Register "SH_CONVEYOR_BELT_TIME_OUT"                 */
+/*               Local Block conveyor belt time out value               */
+/* ==================================================================== */
+
+#define SH_CONVEYOR_BELT_TIME_OUT                0x0000000110040300
+#define SH_CONVEYOR_BELT_TIME_OUT_MASK           0x0000000000000fff
+#define SH_CONVEYOR_BELT_TIME_OUT_INIT           0x0000000000000000
+
+/*   SH_CONVEYOR_BELT_TIME_OUT_VALUE                                    */
+/*   Description:  Conveyor belt time out value                         */
+#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_SHFT     0
+#define SH_CONVEYOR_BELT_TIME_OUT_VALUE_MASK     0x0000000000000fff
+
+/* ==================================================================== */
+/*                    Register "SH_LB_CREDIT_STATUS"                    */
+/*                    Credit Counter Status Register                    */
+/* ==================================================================== */
+
+#define SH_LB_CREDIT_STATUS                      0x0000000110050000
+#define SH_LB_CREDIT_STATUS_MASK                 0x000000000ffff3df
+#define SH_LB_CREDIT_STATUS_INIT                 0x0000000000000000
+
+/*   SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT                                  */
+/*   Description:  LIQ request queue credit counter                     */
+#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_SHFT   0
+#define SH_LB_CREDIT_STATUS_LIQ_RQ_CREDIT_MASK   0x000000000000001f
+
+/*   SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT                                  */
+/*   Description:  LIQ reply queue credit counter                       */
+#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_SHFT   6
+#define SH_LB_CREDIT_STATUS_LIQ_RP_CREDIT_MASK   0x00000000000003c0
+
+/*   SH_LB_CREDIT_STATUS_LINVV_CREDIT                                   */
+/*   Description:  LINVV credit counter                                 */
+#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_SHFT    12
+#define SH_LB_CREDIT_STATUS_LINVV_CREDIT_MASK    0x000000000003f000
+
+/*   SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT                                  */
+/*   Description:  LOQ request queue credit counter                     */
+#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_SHFT   18
+#define SH_LB_CREDIT_STATUS_LOQ_RQ_CREDIT_MASK   0x00000000007c0000
+
+/*   SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT                                  */
+/*   Description:  LOQ reply queue credit counter                       */
+#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_SHFT   23
+#define SH_LB_CREDIT_STATUS_LOQ_RP_CREDIT_MASK   0x000000000f800000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_LOCAL_SEL"                   */
+/*                         LB Debug Port Select                         */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_LOCAL_SEL                    0x0000000110050080
+#define SH_LB_DEBUG_LOCAL_SEL_MASK               0xf777777777777777
+#define SH_LB_DEBUG_LOCAL_SEL_INIT               0x0000000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL                          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL                           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL                          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL                           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL                          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL                           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL                          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL                           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL                          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL                           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL                          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL                           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL                          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL                           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL                          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL                           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_LB_DEBUG_LOCAL_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE                               */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_SHFT 63
+#define SH_LB_DEBUG_LOCAL_SEL_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_PERF_SEL"                    */
+/*                   LB Debug Port Performance Select                   */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_PERF_SEL                     0x0000000110050100
+#define SH_LB_DEBUG_PERF_SEL_MASK                0x7777777777777777
+#define SH_LB_DEBUG_PERF_SEL_INIT                0x0000000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL                           */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL                            */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL                           */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL                            */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL                           */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL                            */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL                           */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL                            */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL                           */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL                            */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL                           */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL                            */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL                           */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL                            */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL                           */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL                            */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_LB_DEBUG_PERF_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_TRIG_SEL"                    */
+/*                       LB Debug Trigger Select                        */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_TRIG_SEL                     0x0000000110050180
+#define SH_LB_DEBUG_TRIG_SEL_MASK                0x7777777777777777
+#define SH_LB_DEBUG_TRIG_SEL_INIT                0x0000000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL                          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL                           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL                          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL                           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL                          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL                           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL                          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL                           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL                          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL                           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL                          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL                           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL                          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL                           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL                          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL                           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_LB_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_1"                    */
+/*                  LB Error capture information: HDR1                  */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_1                     0x0000000110050200
+#define SH_LB_ERROR_DETAIL_1_MASK                0x8003073fff3fffff
+#define SH_LB_ERROR_DETAIL_1_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_1_COMMAND                                       */
+/*   Description:  COMMAND                                              */
+#define SH_LB_ERROR_DETAIL_1_COMMAND_SHFT        0
+#define SH_LB_ERROR_DETAIL_1_COMMAND_MASK        0x00000000000000ff
+
+/*   SH_LB_ERROR_DETAIL_1_SUPPL                                         */
+/*   Description:  SUPPLMENTAL                                          */
+#define SH_LB_ERROR_DETAIL_1_SUPPL_SHFT          8
+#define SH_LB_ERROR_DETAIL_1_SUPPL_MASK          0x00000000003fff00
+
+/*   SH_LB_ERROR_DETAIL_1_SOURCE                                        */
+/*   Description:  SOURCE                                               */
+#define SH_LB_ERROR_DETAIL_1_SOURCE_SHFT         24
+#define SH_LB_ERROR_DETAIL_1_SOURCE_MASK         0x0000003fff000000
+
+/*   SH_LB_ERROR_DETAIL_1_DEST                                          */
+/*   Description:  DEST                                                 */
+#define SH_LB_ERROR_DETAIL_1_DEST_SHFT           40
+#define SH_LB_ERROR_DETAIL_1_DEST_MASK           0x0000070000000000
+
+/*   SH_LB_ERROR_DETAIL_1_HDR_ERR                                       */
+/*   Description:  HDR_ERR                                              */
+#define SH_LB_ERROR_DETAIL_1_HDR_ERR_SHFT        48
+#define SH_LB_ERROR_DETAIL_1_HDR_ERR_MASK        0x0001000000000000
+
+/*   SH_LB_ERROR_DETAIL_1_DATA_ERR                                      */
+/*   Description:  DATA_ERR                                             */
+#define SH_LB_ERROR_DETAIL_1_DATA_ERR_SHFT       49
+#define SH_LB_ERROR_DETAIL_1_DATA_ERR_MASK       0x0002000000000000
+
+/*   SH_LB_ERROR_DETAIL_1_VALID                                         */
+/*   Description:  VALID                                                */
+#define SH_LB_ERROR_DETAIL_1_VALID_SHFT          63
+#define SH_LB_ERROR_DETAIL_1_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_2"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_2                     0x0000000110050280
+#define SH_LB_ERROR_DETAIL_2_MASK                0x00007fffffffffff
+#define SH_LB_ERROR_DETAIL_2_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_2_ADDRESS                                       */
+/*   Description:  ADDRESS                                              */
+#define SH_LB_ERROR_DETAIL_2_ADDRESS_SHFT        0
+#define SH_LB_ERROR_DETAIL_2_ADDRESS_MASK        0x00007fffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_3"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_3                     0x0000000110050300
+#define SH_LB_ERROR_DETAIL_3_MASK                0xffffffffffffffff
+#define SH_LB_ERROR_DETAIL_3_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_3_DATA                                          */
+/*   Description:  DATA                                                 */
+#define SH_LB_ERROR_DETAIL_3_DATA_SHFT           0
+#define SH_LB_ERROR_DETAIL_3_DATA_MASK           0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_4"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_4                     0x0000000110050380
+#define SH_LB_ERROR_DETAIL_4_MASK                0xffffffffffffffff
+#define SH_LB_ERROR_DETAIL_4_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_4_ROUTE                                         */
+/*   Description:  ROUTE                                                */
+#define SH_LB_ERROR_DETAIL_4_ROUTE_SHFT          0
+#define SH_LB_ERROR_DETAIL_4_ROUTE_MASK          0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_5"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_DETAIL_5                     0x0000000110050400
+#define SH_LB_ERROR_DETAIL_5_MASK                0x000000000000007f
+#define SH_LB_ERROR_DETAIL_5_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_DETAIL_5_READ_RETRY                                    */
+/*   Description:  Read retry error                                     */
+#define SH_LB_ERROR_DETAIL_5_READ_RETRY_SHFT     0
+#define SH_LB_ERROR_DETAIL_5_READ_RETRY_MASK     0x0000000000000001
+
+/*   SH_LB_ERROR_DETAIL_5_PTC1_WRITE                                    */
+/*   Description:  PTC1 write error                                     */
+#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_SHFT     1
+#define SH_LB_ERROR_DETAIL_5_PTC1_WRITE_MASK     0x0000000000000002
+
+/*   SH_LB_ERROR_DETAIL_5_WRITE_RETRY                                   */
+/*   Description:  Write retry error                                    */
+#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_SHFT    2
+#define SH_LB_ERROR_DETAIL_5_WRITE_RETRY_MASK    0x0000000000000004
+
+/*   SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW                              */
+/*   Description:  Nack A counter overflow error                        */
+#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_SHFT 3
+#define SH_LB_ERROR_DETAIL_5_COUNT_A_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW                              */
+/*   Description:  Nack B counter overflow error                        */
+#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_SHFT 4
+#define SH_LB_ERROR_DETAIL_5_COUNT_B_OVERFLOW_MASK 0x0000000000000010
+
+/*   SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT                                */
+/*   Description:  Nack A counter timeout error                         */
+#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_SHFT 5
+#define SH_LB_ERROR_DETAIL_5_NACK_A_TIMEOUT_MASK 0x0000000000000020
+
+/*   SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT                                */
+/*   Description:  Nack B counter timeout error                         */
+#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_SHFT 6
+#define SH_LB_ERROR_DETAIL_5_NACK_B_TIMEOUT_MASK 0x0000000000000040
+
+/* ==================================================================== */
+/*                     Register "SH_LB_ERROR_MASK"                      */
+/*                            LB Error Mask                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_MASK                         0x0000000110050480
+#define SH_LB_ERROR_MASK_MASK                    0x00000000007fffff
+#define SH_LB_ERROR_MASK_INIT                    0x00000000007fffff
+
+/*   SH_LB_ERROR_MASK_RQ_BAD_CMD                                        */
+/*   Description:  RQ_BAD_CMD                                           */
+#define SH_LB_ERROR_MASK_RQ_BAD_CMD_SHFT         0
+#define SH_LB_ERROR_MASK_RQ_BAD_CMD_MASK         0x0000000000000001
+
+/*   SH_LB_ERROR_MASK_RP_BAD_CMD                                        */
+/*   Description:  RP_BAD_CMD                                           */
+#define SH_LB_ERROR_MASK_RP_BAD_CMD_SHFT         1
+#define SH_LB_ERROR_MASK_RP_BAD_CMD_MASK         0x0000000000000002
+
+/*   SH_LB_ERROR_MASK_RQ_SHORT                                          */
+/*   Description:  RQ_SHORT                                             */
+#define SH_LB_ERROR_MASK_RQ_SHORT_SHFT           2
+#define SH_LB_ERROR_MASK_RQ_SHORT_MASK           0x0000000000000004
+
+/*   SH_LB_ERROR_MASK_RP_SHORT                                          */
+/*   Description:  RP_SHORT                                             */
+#define SH_LB_ERROR_MASK_RP_SHORT_SHFT           3
+#define SH_LB_ERROR_MASK_RP_SHORT_MASK           0x0000000000000008
+
+/*   SH_LB_ERROR_MASK_RQ_LONG                                           */
+/*   Description:  RQ_LONG                                              */
+#define SH_LB_ERROR_MASK_RQ_LONG_SHFT            4
+#define SH_LB_ERROR_MASK_RQ_LONG_MASK            0x0000000000000010
+
+/*   SH_LB_ERROR_MASK_RP_LONG                                           */
+/*   Description:  RP_LONG                                              */
+#define SH_LB_ERROR_MASK_RP_LONG_SHFT            5
+#define SH_LB_ERROR_MASK_RP_LONG_MASK            0x0000000000000020
+
+/*   SH_LB_ERROR_MASK_RQ_BAD_DATA                                       */
+/*   Description:  RQ_BAD_DATA                                          */
+#define SH_LB_ERROR_MASK_RQ_BAD_DATA_SHFT        6
+#define SH_LB_ERROR_MASK_RQ_BAD_DATA_MASK        0x0000000000000040
+
+/*   SH_LB_ERROR_MASK_RP_BAD_DATA                                       */
+/*   Description:  RP_BAD_DATA                                          */
+#define SH_LB_ERROR_MASK_RP_BAD_DATA_SHFT        7
+#define SH_LB_ERROR_MASK_RP_BAD_DATA_MASK        0x0000000000000080
+
+/*   SH_LB_ERROR_MASK_RQ_BAD_ADDR                                       */
+/*   Description:  RQ_BAD_ADDR                                          */
+#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_SHFT        8
+#define SH_LB_ERROR_MASK_RQ_BAD_ADDR_MASK        0x0000000000000100
+
+/*   SH_LB_ERROR_MASK_RQ_TIME_OUT                                       */
+/*   Description:  RQ_TIME_OUT                                          */
+#define SH_LB_ERROR_MASK_RQ_TIME_OUT_SHFT        9
+#define SH_LB_ERROR_MASK_RQ_TIME_OUT_MASK        0x0000000000000200
+
+/*   SH_LB_ERROR_MASK_LINVV_OVERFLOW                                    */
+/*   Description:  LINVV_OVERFLOW                                       */
+#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_SHFT     10
+#define SH_LB_ERROR_MASK_LINVV_OVERFLOW_MASK     0x0000000000000400
+
+/*   SH_LB_ERROR_MASK_UNEXPECTED_LINV                                   */
+/*   Description:  UNEXPECTED_LINV                                      */
+#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_SHFT    11
+#define SH_LB_ERROR_MASK_UNEXPECTED_LINV_MASK    0x0000000000000800
+
+/*   SH_LB_ERROR_MASK_PTC_1_TIMEOUT                                     */
+/*   Description:  PTC_1 Time out                                       */
+#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_SHFT      12
+#define SH_LB_ERROR_MASK_PTC_1_TIMEOUT_MASK      0x0000000000001000
+
+/*   SH_LB_ERROR_MASK_JUNK_BUS_ERR                                      */
+/*   Description:  Junk Bus error                                       */
+#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_SHFT       13
+#define SH_LB_ERROR_MASK_JUNK_BUS_ERR_MASK       0x0000000000002000
+
+/*   SH_LB_ERROR_MASK_PIO_CB_ERR                                        */
+/*   Description:  PIO Conveyor Belt operation error                    */
+#define SH_LB_ERROR_MASK_PIO_CB_ERR_SHFT         14
+#define SH_LB_ERROR_MASK_PIO_CB_ERR_MASK         0x0000000000004000
+
+/*   SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR                             */
+/*   Description:  Vector request Route data was invalid                */
+#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_SHFT 15
+#define SH_LB_ERROR_MASK_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
+
+/*   SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR                             */
+/*   Description:  Vector reply Route data was invalid                  */
+#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_SHFT 16
+#define SH_LB_ERROR_MASK_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
+
+/*   SH_LB_ERROR_MASK_GCLK_DROP                                         */
+/*   Description:  Gclk drop error                                      */
+#define SH_LB_ERROR_MASK_GCLK_DROP_SHFT          17
+#define SH_LB_ERROR_MASK_GCLK_DROP_MASK          0x0000000000020000
+
+/*   SH_LB_ERROR_MASK_RQ_FIFO_ERROR                                     */
+/*   Description:  Request queue FIFO error                             */
+#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_SHFT      18
+#define SH_LB_ERROR_MASK_RQ_FIFO_ERROR_MASK      0x0000000000040000
+
+/*   SH_LB_ERROR_MASK_RP_FIFO_ERROR                                     */
+/*   Description:  Reply queue FIFO error                               */
+#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_SHFT      19
+#define SH_LB_ERROR_MASK_RP_FIFO_ERROR_MASK      0x0000000000080000
+
+/*   SH_LB_ERROR_MASK_UNEXP_VALID                                       */
+/*   Description:  Unexpected valid error                               */
+#define SH_LB_ERROR_MASK_UNEXP_VALID_SHFT        20
+#define SH_LB_ERROR_MASK_UNEXP_VALID_MASK        0x0000000000100000
+
+/*   SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW                                */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_SHFT 21
+#define SH_LB_ERROR_MASK_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
+
+/*   SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW                                */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_SHFT 22
+#define SH_LB_ERROR_MASK_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_OVERFLOW"                    */
+/*                          LB Error Overflow                           */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_OVERFLOW                     0x0000000110050500
+#define SH_LB_ERROR_OVERFLOW_MASK                0x00000000007fffff
+#define SH_LB_ERROR_OVERFLOW_INIT                0x0000000000000000
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL                              */
+/*   Description:  RQ_BAD_CMD_OVRFL                                     */
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_SHFT 0
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_CMD_OVRFL_MASK 0x0000000000000001
+
+/*   SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL                              */
+/*   Description:  RP_BAD_CMD_OVRFL                                     */
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_SHFT 1
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_CMD_OVRFL_MASK 0x0000000000000002
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL                                */
+/*   Description:  RQ_SHORT_OVRFL                                       */
+#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_SHFT 2
+#define SH_LB_ERROR_OVERFLOW_RQ_SHORT_OVRFL_MASK 0x0000000000000004
+
+/*   SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL                                */
+/*   Description:  RP_SHORT_OVRFL                                       */
+#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_SHFT 3
+#define SH_LB_ERROR_OVERFLOW_RP_SHORT_OVRFL_MASK 0x0000000000000008
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL                                 */
+/*   Description:  RQ_LONG_OVRFL                                        */
+#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_SHFT  4
+#define SH_LB_ERROR_OVERFLOW_RQ_LONG_OVRFL_MASK  0x0000000000000010
+
+/*   SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL                                 */
+/*   Description:  RP_LONG_OVRFL                                        */
+#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_SHFT  5
+#define SH_LB_ERROR_OVERFLOW_RP_LONG_OVRFL_MASK  0x0000000000000020
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL                             */
+/*   Description:  RQ_BAD_DATA_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_SHFT 6
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_DATA_OVRFL_MASK 0x0000000000000040
+
+/*   SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL                             */
+/*   Description:  RP_BAD_DATA_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_SHFT 7
+#define SH_LB_ERROR_OVERFLOW_RP_BAD_DATA_OVRFL_MASK 0x0000000000000080
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL                             */
+/*   Description:  RQ_BAD_ADDR_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_SHFT 8
+#define SH_LB_ERROR_OVERFLOW_RQ_BAD_ADDR_OVRFL_MASK 0x0000000000000100
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL                             */
+/*   Description:  RQ_TIME_OUT_OVRFL                                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_SHFT 9
+#define SH_LB_ERROR_OVERFLOW_RQ_TIME_OUT_OVRFL_MASK 0x0000000000000200
+
+/*   SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL                          */
+/*   Description:  LINVV_OVERFLOW_OVRFL                                 */
+#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_SHFT 10
+#define SH_LB_ERROR_OVERFLOW_LINVV_OVERFLOW_OVRFL_MASK 0x0000000000000400
+
+/*   SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL                         */
+/*   Description:  UNEXPECTED_LINV_OVRFL                                */
+#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_SHFT 11
+#define SH_LB_ERROR_OVERFLOW_UNEXPECTED_LINV_OVRFL_MASK 0x0000000000000800
+
+/*   SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL                           */
+/*   Description:  PTC_1 Time out overflow                              */
+#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_SHFT 12
+#define SH_LB_ERROR_OVERFLOW_PTC_1_TIMEOUT_OVRFL_MASK 0x0000000000001000
+
+/*   SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL                            */
+/*   Description:  Junk Bus error overflow                              */
+#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_SHFT 13
+#define SH_LB_ERROR_OVERFLOW_JUNK_BUS_ERR_OVRFL_MASK 0x0000000000002000
+
+/*   SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL                              */
+/*   Description:  PIO Conveyor Belt operation error overflow           */
+#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_SHFT 14
+#define SH_LB_ERROR_OVERFLOW_PIO_CB_ERR_OVRFL_MASK 0x0000000000004000
+
+/*   SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL                   */
+/*   Description:  Vector request Route data was invalid overflow       */
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_SHFT 15
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RQ_ROUTE_ERROR_OVRFL_MASK 0x0000000000008000
+
+/*   SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL                   */
+/*   Description:  Vector reply Route data was invalid overflow         */
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_SHFT 16
+#define SH_LB_ERROR_OVERFLOW_VECTOR_RP_ROUTE_ERROR_OVRFL_MASK 0x0000000000010000
+
+/*   SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL                               */
+/*   Description:  Gclk drop error overflow                             */
+#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_SHFT 17
+#define SH_LB_ERROR_OVERFLOW_GCLK_DROP_OVRFL_MASK 0x0000000000020000
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL                           */
+/*   Description:  Request queue FIFO error overflow                    */
+#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_SHFT 18
+#define SH_LB_ERROR_OVERFLOW_RQ_FIFO_ERROR_OVRFL_MASK 0x0000000000040000
+
+/*   SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL                           */
+/*   Description:  Reply queue FIFO error overflow                      */
+#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_SHFT 19
+#define SH_LB_ERROR_OVERFLOW_RP_FIFO_ERROR_OVRFL_MASK 0x0000000000080000
+
+/*   SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL                             */
+/*   Description:  Unexpected valid error overflow                      */
+#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_SHFT 20
+#define SH_LB_ERROR_OVERFLOW_UNEXP_VALID_OVRFL_MASK 0x0000000000100000
+
+/*   SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL                      */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_SHFT 21
+#define SH_LB_ERROR_OVERFLOW_RQ_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000200000
+
+/*   SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL                      */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_SHFT 22
+#define SH_LB_ERROR_OVERFLOW_RP_CREDIT_OVERFLOW_OVRFL_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                Register "SH_LB_ERROR_OVERFLOW_ALIAS"                 */
+/*                          LB Error Overflow                           */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_OVERFLOW_ALIAS               0x0000000110050508
+
+/* ==================================================================== */
+/*                    Register "SH_LB_ERROR_SUMMARY"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_SUMMARY                      0x0000000110050580
+#define SH_LB_ERROR_SUMMARY_MASK                 0x00000000007fffff
+#define SH_LB_ERROR_SUMMARY_INIT                 0x0000000000000000
+
+/*   SH_LB_ERROR_SUMMARY_RQ_BAD_CMD                                     */
+/*   Description:  RQ_BAD_CMD                                           */
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_SHFT      0
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_CMD_MASK      0x0000000000000001
+
+/*   SH_LB_ERROR_SUMMARY_RP_BAD_CMD                                     */
+/*   Description:  RP_BAD_CMD                                           */
+#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_SHFT      1
+#define SH_LB_ERROR_SUMMARY_RP_BAD_CMD_MASK      0x0000000000000002
+
+/*   SH_LB_ERROR_SUMMARY_RQ_SHORT                                       */
+/*   Description:  RQ_SHORT                                             */
+#define SH_LB_ERROR_SUMMARY_RQ_SHORT_SHFT        2
+#define SH_LB_ERROR_SUMMARY_RQ_SHORT_MASK        0x0000000000000004
+
+/*   SH_LB_ERROR_SUMMARY_RP_SHORT                                       */
+/*   Description:  RP_SHORT                                             */
+#define SH_LB_ERROR_SUMMARY_RP_SHORT_SHFT        3
+#define SH_LB_ERROR_SUMMARY_RP_SHORT_MASK        0x0000000000000008
+
+/*   SH_LB_ERROR_SUMMARY_RQ_LONG                                        */
+/*   Description:  RQ_LONG                                              */
+#define SH_LB_ERROR_SUMMARY_RQ_LONG_SHFT         4
+#define SH_LB_ERROR_SUMMARY_RQ_LONG_MASK         0x0000000000000010
+
+/*   SH_LB_ERROR_SUMMARY_RP_LONG                                        */
+/*   Description:  RP_LONG                                              */
+#define SH_LB_ERROR_SUMMARY_RP_LONG_SHFT         5
+#define SH_LB_ERROR_SUMMARY_RP_LONG_MASK         0x0000000000000020
+
+/*   SH_LB_ERROR_SUMMARY_RQ_BAD_DATA                                    */
+/*   Description:  RQ_BAD_DATA                                          */
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_SHFT     6
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_DATA_MASK     0x0000000000000040
+
+/*   SH_LB_ERROR_SUMMARY_RP_BAD_DATA                                    */
+/*   Description:  RP_BAD_DATA                                          */
+#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_SHFT     7
+#define SH_LB_ERROR_SUMMARY_RP_BAD_DATA_MASK     0x0000000000000080
+
+/*   SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR                                    */
+/*   Description:  RQ_BAD_ADDR                                          */
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_SHFT     8
+#define SH_LB_ERROR_SUMMARY_RQ_BAD_ADDR_MASK     0x0000000000000100
+
+/*   SH_LB_ERROR_SUMMARY_RQ_TIME_OUT                                    */
+/*   Description:  RQ_TIME_OUT                                          */
+#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_SHFT     9
+#define SH_LB_ERROR_SUMMARY_RQ_TIME_OUT_MASK     0x0000000000000200
+
+/*   SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW                                 */
+/*   Description:  LINVV_OVERFLOW                                       */
+#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_SHFT  10
+#define SH_LB_ERROR_SUMMARY_LINVV_OVERFLOW_MASK  0x0000000000000400
+
+/*   SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV                                */
+/*   Description:  UNEXPECTED_LINV                                      */
+#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_SHFT 11
+#define SH_LB_ERROR_SUMMARY_UNEXPECTED_LINV_MASK 0x0000000000000800
+
+/*   SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT                                  */
+/*   Description:  PTC_1 Time out                                       */
+#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_SHFT   12
+#define SH_LB_ERROR_SUMMARY_PTC_1_TIMEOUT_MASK   0x0000000000001000
+
+/*   SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR                                   */
+/*   Description:  Junk Bus error                                       */
+#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_SHFT    13
+#define SH_LB_ERROR_SUMMARY_JUNK_BUS_ERR_MASK    0x0000000000002000
+
+/*   SH_LB_ERROR_SUMMARY_PIO_CB_ERR                                     */
+/*   Description:  PIO Conveyor Belt operation error                    */
+#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_SHFT      14
+#define SH_LB_ERROR_SUMMARY_PIO_CB_ERR_MASK      0x0000000000004000
+
+/*   SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR                          */
+/*   Description:  Vector request Route data was invalid                */
+#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_SHFT 15
+#define SH_LB_ERROR_SUMMARY_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
+
+/*   SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR                          */
+/*   Description:  Vector reply Route data was invalid                  */
+#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_SHFT 16
+#define SH_LB_ERROR_SUMMARY_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
+
+/*   SH_LB_ERROR_SUMMARY_GCLK_DROP                                      */
+/*   Description:  Gclk drop error                                      */
+#define SH_LB_ERROR_SUMMARY_GCLK_DROP_SHFT       17
+#define SH_LB_ERROR_SUMMARY_GCLK_DROP_MASK       0x0000000000020000
+
+/*   SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR                                  */
+/*   Description:  Request queue FIFO error                             */
+#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_SHFT   18
+#define SH_LB_ERROR_SUMMARY_RQ_FIFO_ERROR_MASK   0x0000000000040000
+
+/*   SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR                                  */
+/*   Description:  Reply queue FIFO error                               */
+#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_SHFT   19
+#define SH_LB_ERROR_SUMMARY_RP_FIFO_ERROR_MASK   0x0000000000080000
+
+/*   SH_LB_ERROR_SUMMARY_UNEXP_VALID                                    */
+/*   Description:  Unexpected valid error                               */
+#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_SHFT     20
+#define SH_LB_ERROR_SUMMARY_UNEXP_VALID_MASK     0x0000000000100000
+
+/*   SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW                             */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_SHFT 21
+#define SH_LB_ERROR_SUMMARY_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
+
+/*   SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW                             */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_SHFT 22
+#define SH_LB_ERROR_SUMMARY_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                 Register "SH_LB_ERROR_SUMMARY_ALIAS"                 */
+/*                         LB Error Bits Alias                          */
+/* ==================================================================== */
+
+#define SH_LB_ERROR_SUMMARY_ALIAS                0x0000000110050588
+
+/* ==================================================================== */
+/*                     Register "SH_LB_FIRST_ERROR"                     */
+/*                            LB First Error                            */
+/* ==================================================================== */
+
+#define SH_LB_FIRST_ERROR                        0x0000000110050600
+#define SH_LB_FIRST_ERROR_MASK                   0x00000000007fffff
+#define SH_LB_FIRST_ERROR_INIT                   0x0000000000000000
+
+/*   SH_LB_FIRST_ERROR_RQ_BAD_CMD                                       */
+/*   Description:  RQ_BAD_CMD                                           */
+#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_SHFT        0
+#define SH_LB_FIRST_ERROR_RQ_BAD_CMD_MASK        0x0000000000000001
+
+/*   SH_LB_FIRST_ERROR_RP_BAD_CMD                                       */
+/*   Description:  RP_BAD_CMD                                           */
+#define SH_LB_FIRST_ERROR_RP_BAD_CMD_SHFT        1
+#define SH_LB_FIRST_ERROR_RP_BAD_CMD_MASK        0x0000000000000002
+
+/*   SH_LB_FIRST_ERROR_RQ_SHORT                                         */
+/*   Description:  RQ_SHORT                                             */
+#define SH_LB_FIRST_ERROR_RQ_SHORT_SHFT          2
+#define SH_LB_FIRST_ERROR_RQ_SHORT_MASK          0x0000000000000004
+
+/*   SH_LB_FIRST_ERROR_RP_SHORT                                         */
+/*   Description:  RP_SHORT                                             */
+#define SH_LB_FIRST_ERROR_RP_SHORT_SHFT          3
+#define SH_LB_FIRST_ERROR_RP_SHORT_MASK          0x0000000000000008
+
+/*   SH_LB_FIRST_ERROR_RQ_LONG                                          */
+/*   Description:  RQ_LONG                                              */
+#define SH_LB_FIRST_ERROR_RQ_LONG_SHFT           4
+#define SH_LB_FIRST_ERROR_RQ_LONG_MASK           0x0000000000000010
+
+/*   SH_LB_FIRST_ERROR_RP_LONG                                          */
+/*   Description:  RP_LONG                                              */
+#define SH_LB_FIRST_ERROR_RP_LONG_SHFT           5
+#define SH_LB_FIRST_ERROR_RP_LONG_MASK           0x0000000000000020
+
+/*   SH_LB_FIRST_ERROR_RQ_BAD_DATA                                      */
+/*   Description:  RQ_BAD_DATA                                          */
+#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_SHFT       6
+#define SH_LB_FIRST_ERROR_RQ_BAD_DATA_MASK       0x0000000000000040
+
+/*   SH_LB_FIRST_ERROR_RP_BAD_DATA                                      */
+/*   Description:  RP_BAD_DATA                                          */
+#define SH_LB_FIRST_ERROR_RP_BAD_DATA_SHFT       7
+#define SH_LB_FIRST_ERROR_RP_BAD_DATA_MASK       0x0000000000000080
+
+/*   SH_LB_FIRST_ERROR_RQ_BAD_ADDR                                      */
+/*   Description:  RQ_BAD_ADDR                                          */
+#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_SHFT       8
+#define SH_LB_FIRST_ERROR_RQ_BAD_ADDR_MASK       0x0000000000000100
+
+/*   SH_LB_FIRST_ERROR_RQ_TIME_OUT                                      */
+/*   Description:  RQ_TIME_OUT                                          */
+#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_SHFT       9
+#define SH_LB_FIRST_ERROR_RQ_TIME_OUT_MASK       0x0000000000000200
+
+/*   SH_LB_FIRST_ERROR_LINVV_OVERFLOW                                   */
+/*   Description:  LINVV_OVERFLOW                                       */
+#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_SHFT    10
+#define SH_LB_FIRST_ERROR_LINVV_OVERFLOW_MASK    0x0000000000000400
+
+/*   SH_LB_FIRST_ERROR_UNEXPECTED_LINV                                  */
+/*   Description:  UNEXPECTED_LINV                                      */
+#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_SHFT   11
+#define SH_LB_FIRST_ERROR_UNEXPECTED_LINV_MASK   0x0000000000000800
+
+/*   SH_LB_FIRST_ERROR_PTC_1_TIMEOUT                                    */
+/*   Description:  PTC_1 Time out                                       */
+#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_SHFT     12
+#define SH_LB_FIRST_ERROR_PTC_1_TIMEOUT_MASK     0x0000000000001000
+
+/*   SH_LB_FIRST_ERROR_JUNK_BUS_ERR                                     */
+/*   Description:  Junk Bus error                                       */
+#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_SHFT      13
+#define SH_LB_FIRST_ERROR_JUNK_BUS_ERR_MASK      0x0000000000002000
+
+/*   SH_LB_FIRST_ERROR_PIO_CB_ERR                                       */
+/*   Description:  PIO Conveyor Belt operation error                    */
+#define SH_LB_FIRST_ERROR_PIO_CB_ERR_SHFT        14
+#define SH_LB_FIRST_ERROR_PIO_CB_ERR_MASK        0x0000000000004000
+
+/*   SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR                            */
+/*   Description:  Vector request Route data was invalid                */
+#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_SHFT 15
+#define SH_LB_FIRST_ERROR_VECTOR_RQ_ROUTE_ERROR_MASK 0x0000000000008000
+
+/*   SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR                            */
+/*   Description:  Vector reply Route data was invalid                  */
+#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_SHFT 16
+#define SH_LB_FIRST_ERROR_VECTOR_RP_ROUTE_ERROR_MASK 0x0000000000010000
+
+/*   SH_LB_FIRST_ERROR_GCLK_DROP                                        */
+/*   Description:  Gclk drop error                                      */
+#define SH_LB_FIRST_ERROR_GCLK_DROP_SHFT         17
+#define SH_LB_FIRST_ERROR_GCLK_DROP_MASK         0x0000000000020000
+
+/*   SH_LB_FIRST_ERROR_RQ_FIFO_ERROR                                    */
+/*   Description:  Request queue FIFO error                             */
+#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_SHFT     18
+#define SH_LB_FIRST_ERROR_RQ_FIFO_ERROR_MASK     0x0000000000040000
+
+/*   SH_LB_FIRST_ERROR_RP_FIFO_ERROR                                    */
+/*   Description:  Reply queue FIFO error                               */
+#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_SHFT     19
+#define SH_LB_FIRST_ERROR_RP_FIFO_ERROR_MASK     0x0000000000080000
+
+/*   SH_LB_FIRST_ERROR_UNEXP_VALID                                      */
+/*   Description:  Unexpected valid error                               */
+#define SH_LB_FIRST_ERROR_UNEXP_VALID_SHFT       20
+#define SH_LB_FIRST_ERROR_UNEXP_VALID_MASK       0x0000000000100000
+
+/*   SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW                               */
+/*   Description:  Request queue credit overflow                        */
+#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_SHFT 21
+#define SH_LB_FIRST_ERROR_RQ_CREDIT_OVERFLOW_MASK 0x0000000000200000
+
+/*   SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW                               */
+/*   Description:  Reply queue credit overflow                          */
+#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_SHFT 22
+#define SH_LB_FIRST_ERROR_RP_CREDIT_OVERFLOW_MASK 0x0000000000400000
+
+/* ==================================================================== */
+/*                     Register "SH_LB_LAST_CREDIT"                     */
+/*                    Credit counter status register                    */
+/* ==================================================================== */
+
+#define SH_LB_LAST_CREDIT                        0x0000000110050680
+#define SH_LB_LAST_CREDIT_MASK                   0x000000000ffff3df
+#define SH_LB_LAST_CREDIT_INIT                   0x0000000000000000
+
+/*   SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT                                    */
+/*   Description:  LIQ request queue credit counter                     */
+#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_SHFT     0
+#define SH_LB_LAST_CREDIT_LIQ_RQ_CREDIT_MASK     0x000000000000001f
+
+/*   SH_LB_LAST_CREDIT_LIQ_RP_CREDIT                                    */
+/*   Description:  LIQ reply queue credit counter                       */
+#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_SHFT     6
+#define SH_LB_LAST_CREDIT_LIQ_RP_CREDIT_MASK     0x00000000000003c0
+
+/*   SH_LB_LAST_CREDIT_LINVV_CREDIT                                     */
+/*   Description:  LINVV credit counter                                 */
+#define SH_LB_LAST_CREDIT_LINVV_CREDIT_SHFT      12
+#define SH_LB_LAST_CREDIT_LINVV_CREDIT_MASK      0x000000000003f000
+
+/*   SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT                                    */
+/*   Description:  LOQ request queue credit counter                     */
+#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_SHFT     18
+#define SH_LB_LAST_CREDIT_LOQ_RQ_CREDIT_MASK     0x00000000007c0000
+
+/*   SH_LB_LAST_CREDIT_LOQ_RP_CREDIT                                    */
+/*   Description:  LOQ reply queue credit counter                       */
+#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_SHFT     23
+#define SH_LB_LAST_CREDIT_LOQ_RP_CREDIT_MASK     0x000000000f800000
+
+/* ==================================================================== */
+/*                     Register "SH_LB_NACK_STATUS"                     */
+/*                     Nack Counter Status Register                     */
+/* ==================================================================== */
+
+#define SH_LB_NACK_STATUS                        0x0000000110050700
+#define SH_LB_NACK_STATUS_MASK                   0x3fffffff0fff0fff
+#define SH_LB_NACK_STATUS_INIT                   0x0000000000000000
+
+/*   SH_LB_NACK_STATUS_PIO_NACK_A                                       */
+/*   Description:  PIO nackA counter                                    */
+#define SH_LB_NACK_STATUS_PIO_NACK_A_SHFT        0
+#define SH_LB_NACK_STATUS_PIO_NACK_A_MASK        0x0000000000000fff
+
+/*   SH_LB_NACK_STATUS_PIO_NACK_B                                       */
+/*   Description:  PIO nackA counter                                    */
+#define SH_LB_NACK_STATUS_PIO_NACK_B_SHFT        16
+#define SH_LB_NACK_STATUS_PIO_NACK_B_MASK        0x000000000fff0000
+
+/*   SH_LB_NACK_STATUS_JUNK_NACK                                        */
+/*   Description:  Junk bus nack counter                                */
+#define SH_LB_NACK_STATUS_JUNK_NACK_SHFT         32
+#define SH_LB_NACK_STATUS_JUNK_NACK_MASK         0x0000ffff00000000
+
+/*   SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT                                 */
+/*   Description:  Conveyor belt time out counter                       */
+#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_SHFT  48
+#define SH_LB_NACK_STATUS_CB_TIMEOUT_COUNT_MASK  0x0fff000000000000
+
+/*   SH_LB_NACK_STATUS_CB_STATE                                         */
+/*   Description:  Conveyor belt state                                  */
+#define SH_LB_NACK_STATUS_CB_STATE_SHFT          60
+#define SH_LB_NACK_STATUS_CB_STATE_MASK          0x3000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_LB_TRIGGER_COMPARE"                   */
+/*                    LB Test-point Trigger Compare                     */
+/* ==================================================================== */
+
+#define SH_LB_TRIGGER_COMPARE                    0x0000000110050780
+#define SH_LB_TRIGGER_COMPARE_MASK               0x00000000ffffffff
+#define SH_LB_TRIGGER_COMPARE_INIT               0x0000000000000000
+
+/*   SH_LB_TRIGGER_COMPARE_MASK                                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_LB_TRIGGER_COMPARE_MASK_SHFT          0
+#define SH_LB_TRIGGER_COMPARE_MASK_MASK          0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_LB_TRIGGER_DATA"                     */
+/*                  LB Test-point Trigger Compare Data                  */
+/* ==================================================================== */
+
+#define SH_LB_TRIGGER_DATA                       0x0000000110050800
+#define SH_LB_TRIGGER_DATA_MASK                  0x00000000ffffffff
+#define SH_LB_TRIGGER_DATA_INIT                  0x00000000ffffffff
+
+/*   SH_LB_TRIGGER_DATA_COMPARE_PATTERN                                 */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_SHFT  0
+#define SH_LB_TRIGGER_DATA_COMPARE_PATTERN_MASK  0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_CONFIG"                      */
+/*              PI Adaptive Error Correction Configuration              */
+/* ==================================================================== */
+
+#define SH_PI_AEC_CONFIG                         0x0000000120050000
+#define SH_PI_AEC_CONFIG_MASK                    0x0000000000000007
+#define SH_PI_AEC_CONFIG_INIT                    0x0000000000000000
+
+/*   SH_PI_AEC_CONFIG_MODE                                              */
+/*   Description:  AEC Operation Mode                                   */
+#define SH_PI_AEC_CONFIG_MODE_SHFT               0
+#define SH_PI_AEC_CONFIG_MODE_MASK               0x0000000000000007
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_ERROR_MASK"                    */
+/*                          PI AFI Error Mask                           */
+/* ==================================================================== */
+
+#define SH_PI_AFI_ERROR_MASK                     0x0000000120050080
+#define SH_PI_AFI_ERROR_MASK_MASK                0x00000007ffe00000
+#define SH_PI_AFI_ERROR_MASK_INIT                0x00000007ffe00000
+
+/*   SH_PI_AFI_ERROR_MASK_HUNG_BUS                                      */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_SHFT       21
+#define SH_PI_AFI_ERROR_MASK_HUNG_BUS_MASK       0x0000000000200000
+
+/*   SH_PI_AFI_ERROR_MASK_RSP_PARITY                                    */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_SHFT     22
+#define SH_PI_AFI_ERROR_MASK_RSP_PARITY_MASK     0x0000000000400000
+
+/*   SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN                                   */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_SHFT    23
+#define SH_PI_AFI_ERROR_MASK_IOQ_OVERRUN_MASK    0x0000000000800000
+
+/*   SH_PI_AFI_ERROR_MASK_REQ_FORMAT                                    */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_SHFT     24
+#define SH_PI_AFI_ERROR_MASK_REQ_FORMAT_MASK     0x0000000001000000
+
+/*   SH_PI_AFI_ERROR_MASK_ADDR_ACCESS                                   */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_SHFT    25
+#define SH_PI_AFI_ERROR_MASK_ADDR_ACCESS_MASK    0x0000000002000000
+
+/*   SH_PI_AFI_ERROR_MASK_REQ_PARITY                                    */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_SHFT     26
+#define SH_PI_AFI_ERROR_MASK_REQ_PARITY_MASK     0x0000000004000000
+
+/*   SH_PI_AFI_ERROR_MASK_ADDR_PARITY                                   */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_SHFT    27
+#define SH_PI_AFI_ERROR_MASK_ADDR_PARITY_MASK    0x0000000008000000
+
+/*   SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE                                  */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_SHFT   28
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_DQE_MASK   0x0000000010000000
+
+/*   SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE                                  */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_SHFT   29
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_UCE_MASK   0x0000000020000000
+
+/*   SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE                                   */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_SHFT    30
+#define SH_PI_AFI_ERROR_MASK_SHUB_FSB_CE_MASK    0x0000000040000000
+
+/*   SH_PI_AFI_ERROR_MASK_LIVELOCK                                      */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_AFI_ERROR_MASK_LIVELOCK_SHFT       31
+#define SH_PI_AFI_ERROR_MASK_LIVELOCK_MASK       0x0000000080000000
+
+/*   SH_PI_AFI_ERROR_MASK_BAD_SNOOP                                     */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_SHFT      32
+#define SH_PI_AFI_ERROR_MASK_BAD_SNOOP_MASK      0x0000000100000000
+
+/*   SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS                                  */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_SHFT   33
+#define SH_PI_AFI_ERROR_MASK_FSB_TBL_MISS_MASK   0x0000000200000000
+
+/*   SH_PI_AFI_ERROR_MASK_MSG_LEN                                       */
+/*   Description:  Runt or Obese message received from SIC              */
+#define SH_PI_AFI_ERROR_MASK_MSG_LEN_SHFT        34
+#define SH_PI_AFI_ERROR_MASK_MSG_LEN_MASK        0x0000000400000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_AFI_TEST_POINT_COMPARE"                */
+/*                      PI AFI Test Point Compare                       */
+/* ==================================================================== */
+
+#define SH_PI_AFI_TEST_POINT_COMPARE             0x0000000120050100
+#define SH_PI_AFI_TEST_POINT_COMPARE_MASK        0xffffffffffffffff
+#define SH_PI_AFI_TEST_POINT_COMPARE_INIT        0xffffffff00000000
+
+/*   SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK                          */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN                       */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_AFI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_AFI_TEST_POINT_SELECT"                */
+/*                       PI AFI Test Point Select                       */
+/* ==================================================================== */
+
+#define SH_PI_AFI_TEST_POINT_SELECT              0x0000000120050180
+#define SH_PI_AFI_TEST_POINT_SELECT_MASK         0xff7f7f7f7f7f7f7f
+#define SH_PI_AFI_TEST_POINT_SELECT_INIT         0x0000000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                    */
+/*   Description:  Nibble 0: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x000000000000000f
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                     */
+/*   Description:  Nibble 0: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                    */
+/*   Description:  Nibble 1: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000f00
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                     */
+/*   Description:  Nibble 1: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                    */
+/*   Description:  Nibble 2: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x00000000000f0000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                     */
+/*   Description:  Nibble 2: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                    */
+/*   Description:  Nibble 3: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x000000000f000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                     */
+/*   Description:  Nibble 3: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                    */
+/*   Description:  Nibble 4: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000f00000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                     */
+/*   Description:  Nibble 4: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                    */
+/*   Description:  Nibble 5: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x00000f0000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                     */
+/*   Description:  Nibble 5: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                    */
+/*   Description:  Nibble 6: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x000f000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                     */
+/*   Description:  Nibble 6: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                    */
+/*   Description:  Nibble 7: Word Select                                */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0f00000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                     */
+/*   Description:  Nibble 7: Nibble Select                              */
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_AFI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE                         */
+/*   Description:  Trigger Enabled                                      */
+#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_AFI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*            Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT      0x0000000120050200
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_MASK 0x7f7f7f7f7f7f7f7f
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL           */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x000000000000000f
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL            */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL           */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000f00
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL            */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL           */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x00000000000f0000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL            */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL           */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x000000000f000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL            */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL           */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000f00000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL            */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL           */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x00000f0000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL            */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL           */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x000f000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL            */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL           */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0f00000000000000
+
+/*   SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL            */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_AFI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_AUTO_REPLY_ENABLE"                  */
+/*                         PI Auto Reply Enable                         */
+/* ==================================================================== */
+
+#define SH_PI_AUTO_REPLY_ENABLE                  0x0000000120050280
+#define SH_PI_AUTO_REPLY_ENABLE_MASK             0x0000000000000001
+#define SH_PI_AUTO_REPLY_ENABLE_INIT             0x0000000000000000
+
+/*   SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE                          */
+/*   Description:  Auto Reply Enabled                                   */
+#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_SHFT 0
+#define SH_PI_AUTO_REPLY_ENABLE_AUTO_REPLY_ENABLE_MASK 0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_PI_CAM_CONTROL"                     */
+/*                      CRB CAM MMR Access Control                      */
+/* ==================================================================== */
+
+#define SH_PI_CAM_CONTROL                        0x0000000120050300
+#define SH_PI_CAM_CONTROL_MASK                   0x800000000000037f
+#define SH_PI_CAM_CONTROL_INIT                   0x0000000000000000
+
+/*   SH_PI_CAM_CONTROL_CAM_INDX                                         */
+/*   Description:  CRB CAM Index to perform read/write on.              */
+#define SH_PI_CAM_CONTROL_CAM_INDX_SHFT          0
+#define SH_PI_CAM_CONTROL_CAM_INDX_MASK          0x000000000000007f
+
+/*   SH_PI_CAM_CONTROL_CAM_WRITE                                        */
+/*   Description:  Is CRB CAM MMR function a write.                     */
+#define SH_PI_CAM_CONTROL_CAM_WRITE_SHFT         8
+#define SH_PI_CAM_CONTROL_CAM_WRITE_MASK         0x0000000000000100
+
+/*   SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR                                */
+/*   Description:  Clear RRB read tranfer pending.                      */
+#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_SHFT 9
+#define SH_PI_CAM_CONTROL_RRB_RD_XFER_CLEAR_MASK 0x0000000000000200
+
+/*   SH_PI_CAM_CONTROL_START                                            */
+/*   Description:  Start CRB CAM read/write operation                   */
+#define SH_PI_CAM_CONTROL_START_SHFT             63
+#define SH_PI_CAM_CONTROL_START_MASK             0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_COMPARE"               */
+/*                      PI CRBC Test Point Compare                      */
+/* ==================================================================== */
+
+#define SH_PI_CRBC_TEST_POINT_COMPARE            0x0000000120050380
+#define SH_PI_CRBC_TEST_POINT_COMPARE_MASK       0xffffffffffffffff
+#define SH_PI_CRBC_TEST_POINT_COMPARE_INIT       0xffffffff00000000
+
+/*   SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN                      */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_CRBC_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_SELECT"                */
+/*                      PI CRBC Test Point Select                       */
+/* ==================================================================== */
+
+#define SH_PI_CRBC_TEST_POINT_SELECT             0x0000000120050400
+#define SH_PI_CRBC_TEST_POINT_SELECT_MASK        0xf777777777777777
+#define SH_PI_CRBC_TEST_POINT_SELECT_INIT        0x0000000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                   */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                    */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                   */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                    */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                   */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                    */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                   */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                    */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                   */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                    */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                   */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                    */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                   */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                    */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                   */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                    */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBC_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE                        */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_CRBC_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT     0x0000000120050480
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_CRBP_ERROR_MASK"                   */
+/*                          PI CRBP Error Mask                          */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_ERROR_MASK                    0x0000000120050500
+#define SH_PI_CRBP_ERROR_MASK_MASK               0x00000000001fffff
+#define SH_PI_CRBP_ERROR_MASK_INIT               0x00000000001fffff
+
+/*   SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR                                */
+/*   Description:  Mask detection internal protocol table misses        */
+#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_SHFT 0
+#define SH_PI_CRBP_ERROR_MASK_FSB_PROTO_ERR_MASK 0x0000000000000001
+
+/*   SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR                                   */
+/*   Description:  Mask graphic reply error detection                   */
+#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_SHFT    1
+#define SH_PI_CRBP_ERROR_MASK_GFX_RP_ERR_MASK    0x0000000000000002
+
+/*   SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR                                 */
+/*   Description:  Mask detection of external protocol table misses     */
+#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_SHFT  2
+#define SH_PI_CRBP_ERROR_MASK_XB_PROTO_ERR_MASK  0x0000000000000004
+
+/*   SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR                                   */
+/*   Description:  Mask memory error reply message detection            */
+#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_SHFT    3
+#define SH_PI_CRBP_ERROR_MASK_MEM_RP_ERR_MASK    0x0000000000000008
+
+/*   SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR                                   */
+/*   Description:  Mask PIO reply error message detection               */
+#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_SHFT    4
+#define SH_PI_CRBP_ERROR_MASK_PIO_RP_ERR_MASK    0x0000000000000010
+
+/*   SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR                                   */
+/*   Description:  Mask memory time-out detection                       */
+#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_SHFT    5
+#define SH_PI_CRBP_ERROR_MASK_MEM_TO_ERR_MASK    0x0000000000000020
+
+/*   SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR                                   */
+/*   Description:  Mask PIO time-out detection                          */
+#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_SHFT    6
+#define SH_PI_CRBP_ERROR_MASK_PIO_TO_ERR_MASK    0x0000000000000040
+
+/*   SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE                                 */
+/*   Description:  Mask un-correctable ECC error detection              */
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_SHFT  7
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_UCE_MASK  0x0000000000000080
+
+/*   SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE                                  */
+/*   Description:  Mask correctable ECC error detection                 */
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_SHFT   8
+#define SH_PI_CRBP_ERROR_MASK_FSB_SHUB_CE_MASK   0x0000000000000100
+
+/*   SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR                                */
+/*   Description:  Mask detection of color errors                       */
+#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_SHFT 9
+#define SH_PI_CRBP_ERROR_MASK_MSG_COLOR_ERR_MASK 0x0000000000000200
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW                                */
+/*   Description:  Mask MD Request input buffer over flow error         */
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT 10
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW                                */
+/*   Description:  Mask MD Reply input buffer over flow error           */
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_SHFT 11
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_Q_OFLOW_MASK 0x0000000000000800
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW                                */
+/*   Description:  Mask XN Request input buffer over flow error         */
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT 12
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW                                */
+/*   Description:  Mask XN Reply input buffer over flow error           */
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_SHFT 13
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_Q_OFLOW_MASK 0x0000000000002000
+
+/*   SH_PI_CRBP_ERROR_MASK_NACK_OFLOW                                   */
+/*   Description:  Mask NACK over flow error                            */
+#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_SHFT    14
+#define SH_PI_CRBP_ERROR_MASK_NACK_OFLOW_MASK    0x0000000000004000
+
+/*   SH_PI_CRBP_ERROR_MASK_GFX_INT_0                                    */
+/*   Description:  Mask GFX transfer interrupt for CPU 0                */
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_SHFT     15
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_0_MASK     0x0000000000008000
+
+/*   SH_PI_CRBP_ERROR_MASK_GFX_INT_1                                    */
+/*   Description:  Mask GFX transfer interrupt for CPU 1                */
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_SHFT     16
+#define SH_PI_CRBP_ERROR_MASK_GFX_INT_1_MASK     0x0000000000010000
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW                              */
+/*   Description:  Mask MD Request Credit Overflow Error                */
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_CRBP_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW                              */
+/*   Description:  Mask MD Reply Credit Overflow Error                  */
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_CRBP_ERROR_MASK_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW                              */
+/*   Description:  Mask XN Request Credit Overflow Error                */
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_CRBP_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW                              */
+/*   Description:  Mask XN Reply Credit Overflow Error                  */
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_CRBP_ERROR_MASK_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/* ==================================================================== */
+/*                Register "SH_PI_CRBP_FSB_PIPE_COMPARE"                */
+/*                        CRBP FSB Pipe Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_FSB_PIPE_COMPARE              0x0000000120050580
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_MASK         0x001fffffffffffff
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_INIT         0x0000000000000000
+
+/*   SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS                        */
+/*   Description:  Address A or B to compare against                    */
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_SHFT 0
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_ADDRESS_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ                            */
+/*   Description:  REQa or REQb value to compare against                */
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_SHFT 47
+#define SH_PI_CRBP_FSB_PIPE_COMPARE_COMPARE_REQ_MASK 0x001f800000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_FSB_PIPE_MASK"                  */
+/*                          CRBP Compare Mask                           */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_FSB_PIPE_MASK                 0x0000000120050600
+#define SH_PI_CRBP_FSB_PIPE_MASK_MASK            0x001fffffffffffff
+#define SH_PI_CRBP_FSB_PIPE_MASK_INIT            0x0000000000000000
+
+/*   SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK                      */
+/*   Description:  Address A or B mask values                           */
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_SHFT 0
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK                          */
+/*   Description:  REQa or REQb mask values                             */
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_SHFT 47
+#define SH_PI_CRBP_FSB_PIPE_MASK_COMPARE_REQ_MASK_MASK 0x001f800000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_COMPARE"               */
+/*                      PI CRBP Test Point Compare                      */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_TEST_POINT_COMPARE            0x0000000120050680
+#define SH_PI_CRBP_TEST_POINT_COMPARE_MASK       0xffffffffffffffff
+#define SH_PI_CRBP_TEST_POINT_COMPARE_INIT       0xffffffff00000000
+
+/*   SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN                      */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_CRBP_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_SELECT"                */
+/*                      PI CRBP Test Point Select                       */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_TEST_POINT_SELECT             0x0000000120050700
+#define SH_PI_CRBP_TEST_POINT_SELECT_MASK        0xf777777777777777
+#define SH_PI_CRBP_TEST_POINT_SELECT_INIT        0x0000000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                   */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                    */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                   */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                    */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                   */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                    */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                   */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                    */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                   */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                    */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                   */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                    */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                   */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                    */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                   */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                    */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBP_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE                        */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_CRBP_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBP Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT     0x0000000120050780
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_MASK 0x7777777777777777
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_INIT 0x0000000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL          */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL          */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL          */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL          */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL          */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL          */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL          */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL          */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_0"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0             0x0000000120050800
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_MASK        0x007fffffffffffff
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_INIT        0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS                       */
+/*   Description:  Address to compare against                           */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_ADDRESS_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND                       */
+/*   Description:  SN2NET Command to compare against                    */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_SHFT 47
+#define SH_PI_CRBP_XB_PIPE_COMPARE_0_COMPARE_COMMAND_MASK 0x007f800000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_1"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1             0x0000000120050880
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_MASK        0x000001ff3fff3fff
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_INIT        0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE                        */
+/*   Description:  Source to compare against                            */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SOURCE_MASK 0x0000000000003fff
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL                  */
+/*   Description:  Supplemental to compare against                      */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_SHFT 16
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_SUPPLEMENTAL_MASK 0x000000003fff0000
+
+/*   SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO                          */
+/*   Description:  Echo to compare against                              */
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_SHFT 32
+#define SH_PI_CRBP_XB_PIPE_COMPARE_1_COMPARE_ECHO_MASK 0x000001ff00000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_0"                 */
+/*                     CRBP Compare Mask Register 1                     */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_MASK_0                0x0000000120050900
+#define SH_PI_CRBP_XB_PIPE_MASK_0_MASK           0x007fffffffffffff
+#define SH_PI_CRBP_XB_PIPE_MASK_0_INIT           0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK                     */
+/*   Description:  Address to compare against                           */
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_ADDRESS_MASK_MASK 0x00007fffffffffff
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK                     */
+/*   Description:  SN2NET Command to compare against                    */
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_SHFT 47
+#define SH_PI_CRBP_XB_PIPE_MASK_0_COMPARE_COMMAND_MASK_MASK 0x007f800000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_1"                 */
+/*                 CRBP XB Pipe Compare Mask Register 1                 */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_XB_PIPE_MASK_1                0x0000000120050980
+#define SH_PI_CRBP_XB_PIPE_MASK_1_MASK           0x000001ff3fff3fff
+#define SH_PI_CRBP_XB_PIPE_MASK_1_INIT           0x0000000000000000
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK                      */
+/*   Description:  Source to compare against                            */
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_SHFT 0
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SOURCE_MASK_MASK 0x0000000000003fff
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK                */
+/*   Description:  Supplemental to compare against                      */
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_SHFT 16
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_SUPPLEMENTAL_MASK_MASK 0x000000003fff0000
+
+/*   SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK                        */
+/*   Description:  Echo to compare against                              */
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_SHFT 32
+#define SH_PI_CRBP_XB_PIPE_MASK_1_COMPARE_ECHO_MASK_MASK 0x000001ff00000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_DPC_QUEUE_CONFIG"                   */
+/*                       DPC Queue Configuration                        */
+/* ==================================================================== */
+
+#define SH_PI_DPC_QUEUE_CONFIG                   0x0000000120050a00
+#define SH_PI_DPC_QUEUE_CONFIG_MASK              0x000000001f1f1f1f
+#define SH_PI_DPC_QUEUE_CONFIG_INIT              0x000000000c010c01
+
+/*   SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL                               */
+/*   Description:  DXB WTL Command Queue Almost Empty Level             */
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_SHFT 0
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AE_LEVEL_MASK 0x000000000000001f
+
+/*   SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH                              */
+/*   Description:  DXB WTL Command Queue Almost Full Threshold          */
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_SHFT 8
+#define SH_PI_DPC_QUEUE_CONFIG_DWCQ_AF_THRESH_MASK 0x0000000000001f00
+
+/*   SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL                               */
+/*   Description:  FSB WTL Command Queue Almost Empty Level             */
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_SHFT 16
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AE_LEVEL_MASK 0x00000000001f0000
+
+/*   SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH                              */
+/*   Description:  FSB WTL Command Queue Almost Full Threshold          */
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_SHFT 24
+#define SH_PI_DPC_QUEUE_CONFIG_FWCQ_AF_THRESH_MASK 0x000000001f000000
+
+/* ==================================================================== */
+/*                     Register "SH_PI_ERROR_MASK"                      */
+/*                            PI Error Mask                             */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_MASK                         0x0000000120050a80
+#define SH_PI_ERROR_MASK_MASK                    0x00000007ffffffff
+#define SH_PI_ERROR_MASK_INIT                    0x00000007ffffffff
+
+/*   SH_PI_ERROR_MASK_FSB_PROTO_ERR                                     */
+/*   Description:  Mask detection of internal protocol table misses     */
+#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_SHFT      0
+#define SH_PI_ERROR_MASK_FSB_PROTO_ERR_MASK      0x0000000000000001
+
+/*   SH_PI_ERROR_MASK_GFX_RP_ERR                                        */
+/*   Description:  Mask graphic reply error message error detection     */
+#define SH_PI_ERROR_MASK_GFX_RP_ERR_SHFT         1
+#define SH_PI_ERROR_MASK_GFX_RP_ERR_MASK         0x0000000000000002
+
+/*   SH_PI_ERROR_MASK_XB_PROTO_ERR                                      */
+/*   Description:  Mask detection of external protocol table misses     */
+#define SH_PI_ERROR_MASK_XB_PROTO_ERR_SHFT       2
+#define SH_PI_ERROR_MASK_XB_PROTO_ERR_MASK       0x0000000000000004
+
+/*   SH_PI_ERROR_MASK_MEM_RP_ERR                                        */
+/*   Description:  Mask memory reply error detection                    */
+#define SH_PI_ERROR_MASK_MEM_RP_ERR_SHFT         3
+#define SH_PI_ERROR_MASK_MEM_RP_ERR_MASK         0x0000000000000008
+
+/*   SH_PI_ERROR_MASK_PIO_RP_ERR                                        */
+/*   Description:  Mask PIO reply error detection                       */
+#define SH_PI_ERROR_MASK_PIO_RP_ERR_SHFT         4
+#define SH_PI_ERROR_MASK_PIO_RP_ERR_MASK         0x0000000000000010
+
+/*   SH_PI_ERROR_MASK_MEM_TO_ERR                                        */
+/*   Description:  Mask CRB time-out errors                             */
+#define SH_PI_ERROR_MASK_MEM_TO_ERR_SHFT         5
+#define SH_PI_ERROR_MASK_MEM_TO_ERR_MASK         0x0000000000000020
+
+/*   SH_PI_ERROR_MASK_PIO_TO_ERR                                        */
+/*   Description:  Mask PIO time-out errors                             */
+#define SH_PI_ERROR_MASK_PIO_TO_ERR_SHFT         6
+#define SH_PI_ERROR_MASK_PIO_TO_ERR_MASK         0x0000000000000040
+
+/*   SH_PI_ERROR_MASK_FSB_SHUB_UCE                                      */
+/*   Description:  Mask un-correctable ECC error detection              */
+#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_SHFT       7
+#define SH_PI_ERROR_MASK_FSB_SHUB_UCE_MASK       0x0000000000000080
+
+/*   SH_PI_ERROR_MASK_FSB_SHUB_CE                                       */
+/*   Description:  Mask correctable ECC error detection                 */
+#define SH_PI_ERROR_MASK_FSB_SHUB_CE_SHFT        8
+#define SH_PI_ERROR_MASK_FSB_SHUB_CE_MASK        0x0000000000000100
+
+/*   SH_PI_ERROR_MASK_MSG_COLOR_ERR                                     */
+/*   Description:  Mask message color error detection                   */
+#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_SHFT      9
+#define SH_PI_ERROR_MASK_MSG_COLOR_ERR_MASK      0x0000000000000200
+
+/*   SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW                                     */
+/*   Description:  Mask MD Request input buffer over flow error         */
+#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_SHFT      10
+#define SH_PI_ERROR_MASK_MD_RQ_Q_OFLOW_MASK      0x0000000000000400
+
+/*   SH_PI_ERROR_MASK_MD_RP_Q_OFLOW                                     */
+/*   Description:  Mask MD Reply input buffer over flow error           */
+#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_SHFT      11
+#define SH_PI_ERROR_MASK_MD_RP_Q_OFLOW_MASK      0x0000000000000800
+
+/*   SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW                                     */
+/*   Description:  Mask XN Request input buffer over flow error         */
+#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_SHFT      12
+#define SH_PI_ERROR_MASK_XN_RQ_Q_OFLOW_MASK      0x0000000000001000
+
+/*   SH_PI_ERROR_MASK_XN_RP_Q_OFLOW                                     */
+/*   Description:  Mask XN Reply input buffer over flow error           */
+#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_SHFT      13
+#define SH_PI_ERROR_MASK_XN_RP_Q_OFLOW_MASK      0x0000000000002000
+
+/*   SH_PI_ERROR_MASK_NACK_OFLOW                                        */
+/*   Description:  Mask NACK over flow error                            */
+#define SH_PI_ERROR_MASK_NACK_OFLOW_SHFT         14
+#define SH_PI_ERROR_MASK_NACK_OFLOW_MASK         0x0000000000004000
+
+/*   SH_PI_ERROR_MASK_GFX_INT_0                                         */
+/*   Description:  Mask GFX transfer interrupt for CPU 0                */
+#define SH_PI_ERROR_MASK_GFX_INT_0_SHFT          15
+#define SH_PI_ERROR_MASK_GFX_INT_0_MASK          0x0000000000008000
+
+/*   SH_PI_ERROR_MASK_GFX_INT_1                                         */
+/*   Description:  Mask GFX transfer interrupt for CPU 1                */
+#define SH_PI_ERROR_MASK_GFX_INT_1_SHFT          16
+#define SH_PI_ERROR_MASK_GFX_INT_1_MASK          0x0000000000010000
+
+/*   SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW                                   */
+/*   Description:  Mask MD Request Credit Overflow Error                */
+#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_SHFT    17
+#define SH_PI_ERROR_MASK_MD_RQ_CRD_OFLOW_MASK    0x0000000000020000
+
+/*   SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW                                   */
+/*   Description:  Mask MD Reply Credit Overflow Error                  */
+#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_SHFT    18
+#define SH_PI_ERROR_MASK_MD_RP_CRD_OFLOW_MASK    0x0000000000040000
+
+/*   SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW                                   */
+/*   Description:  Mask XN Request Credit Overflow Error                */
+#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_SHFT    19
+#define SH_PI_ERROR_MASK_XN_RQ_CRD_OFLOW_MASK    0x0000000000080000
+
+/*   SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW                                   */
+/*   Description:  Mask XN Reply Credit Overflow Error                  */
+#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_SHFT    20
+#define SH_PI_ERROR_MASK_XN_RP_CRD_OFLOW_MASK    0x0000000000100000
+
+/*   SH_PI_ERROR_MASK_HUNG_BUS                                          */
+/*   Description:  Mask FSB hung error                                  */
+#define SH_PI_ERROR_MASK_HUNG_BUS_SHFT           21
+#define SH_PI_ERROR_MASK_HUNG_BUS_MASK           0x0000000000200000
+
+/*   SH_PI_ERROR_MASK_RSP_PARITY                                        */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_ERROR_MASK_RSP_PARITY_SHFT         22
+#define SH_PI_ERROR_MASK_RSP_PARITY_MASK         0x0000000000400000
+
+/*   SH_PI_ERROR_MASK_IOQ_OVERRUN                                       */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_ERROR_MASK_IOQ_OVERRUN_SHFT        23
+#define SH_PI_ERROR_MASK_IOQ_OVERRUN_MASK        0x0000000000800000
+
+/*   SH_PI_ERROR_MASK_REQ_FORMAT                                        */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_ERROR_MASK_REQ_FORMAT_SHFT         24
+#define SH_PI_ERROR_MASK_REQ_FORMAT_MASK         0x0000000001000000
+
+/*   SH_PI_ERROR_MASK_ADDR_ACCESS                                       */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_ERROR_MASK_ADDR_ACCESS_SHFT        25
+#define SH_PI_ERROR_MASK_ADDR_ACCESS_MASK        0x0000000002000000
+
+/*   SH_PI_ERROR_MASK_REQ_PARITY                                        */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_ERROR_MASK_REQ_PARITY_SHFT         26
+#define SH_PI_ERROR_MASK_REQ_PARITY_MASK         0x0000000004000000
+
+/*   SH_PI_ERROR_MASK_ADDR_PARITY                                       */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_ERROR_MASK_ADDR_PARITY_SHFT        27
+#define SH_PI_ERROR_MASK_ADDR_PARITY_MASK        0x0000000008000000
+
+/*   SH_PI_ERROR_MASK_SHUB_FSB_DQE                                      */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_SHFT       28
+#define SH_PI_ERROR_MASK_SHUB_FSB_DQE_MASK       0x0000000010000000
+
+/*   SH_PI_ERROR_MASK_SHUB_FSB_UCE                                      */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_SHFT       29
+#define SH_PI_ERROR_MASK_SHUB_FSB_UCE_MASK       0x0000000020000000
+
+/*   SH_PI_ERROR_MASK_SHUB_FSB_CE                                       */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_MASK_SHUB_FSB_CE_SHFT        30
+#define SH_PI_ERROR_MASK_SHUB_FSB_CE_MASK        0x0000000040000000
+
+/*   SH_PI_ERROR_MASK_LIVELOCK                                          */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_ERROR_MASK_LIVELOCK_SHFT           31
+#define SH_PI_ERROR_MASK_LIVELOCK_MASK           0x0000000080000000
+
+/*   SH_PI_ERROR_MASK_BAD_SNOOP                                         */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_ERROR_MASK_BAD_SNOOP_SHFT          32
+#define SH_PI_ERROR_MASK_BAD_SNOOP_MASK          0x0000000100000000
+
+/*   SH_PI_ERROR_MASK_FSB_TBL_MISS                                      */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_ERROR_MASK_FSB_TBL_MISS_SHFT       33
+#define SH_PI_ERROR_MASK_FSB_TBL_MISS_MASK       0x0000000200000000
+
+/*   SH_PI_ERROR_MASK_MSG_LENGTH                                        */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_ERROR_MASK_MSG_LENGTH_SHFT         34
+#define SH_PI_ERROR_MASK_MSG_LENGTH_MASK         0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_CONFIG"                 */
+/*                    PI Express Reply Configuration                    */
+/* ==================================================================== */
+
+#define SH_PI_EXPRESS_REPLY_CONFIG               0x0000000120050b00
+#define SH_PI_EXPRESS_REPLY_CONFIG_MASK          0x0000000000000007
+#define SH_PI_EXPRESS_REPLY_CONFIG_INIT          0x0000000000000001
+
+/*   SH_PI_EXPRESS_REPLY_CONFIG_MODE                                    */
+/*   Description:  Express Reply Mode                                   */
+#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_SHFT     0
+#define SH_PI_EXPRESS_REPLY_CONFIG_MODE_MASK     0x0000000000000007
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_VALUE"                  */
+/*                          FSB Compare Value                           */
+/* ==================================================================== */
+
+#define SH_PI_FSB_COMPARE_VALUE                  0x0000000120050c00
+#define SH_PI_FSB_COMPARE_VALUE_MASK             0xffffffffffffffff
+#define SH_PI_FSB_COMPARE_VALUE_INIT             0x0000000000000000
+
+/*   SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE                              */
+/*   Description:  Compare value                                        */
+#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_SHFT 0
+#define SH_PI_FSB_COMPARE_VALUE_COMPARE_VALUE_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_MASK"                   */
+/*                           FSB Compare Mask                           */
+/* ==================================================================== */
+
+#define SH_PI_FSB_COMPARE_MASK                   0x0000000120050b80
+#define SH_PI_FSB_COMPARE_MASK_MASK              0xffffffffffffffff
+#define SH_PI_FSB_COMPARE_MASK_INIT              0x0000000000000000
+
+/*   SH_PI_FSB_COMPARE_MASK_MASK_VALUE                                  */
+/*   Description:  Mask value                                           */
+#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_SHFT   0
+#define SH_PI_FSB_COMPARE_MASK_MASK_VALUE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_PI_FSB_ERROR_INJECTION"                 */
+/*                     Inject an Error onto the FSB                     */
+/* ==================================================================== */
+
+#define SH_PI_FSB_ERROR_INJECTION                0x0000000120050c80
+#define SH_PI_FSB_ERROR_INJECTION_MASK           0x000000070fff03ff
+#define SH_PI_FSB_ERROR_INJECTION_INIT           0x0000000000000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB                             */
+/*   Description:  Inject a RP# Parity Error onto the FSB               */
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_SHFT 0
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_TO_FSB_MASK 0x0000000000000001
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB                            */
+/*   Description:  Inject an AP[0]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_SHFT 1
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_TO_FSB_MASK 0x0000000000000002
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB                            */
+/*   Description:  Inject an AP[1]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_SHFT 2
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_TO_FSB_MASK 0x0000000000000004
+
+/*   SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB                            */
+/*   Description:  Inject a RSP# Parity Error onto the FSB              */
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_SHFT 3
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_TO_FSB_MASK 0x0000000000000008
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB                            */
+/*   Description:  Inject a Correctable Error in Doubleword 0 onto the  */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_SHFT 4
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_TO_FSB_MASK 0x0000000000000010
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB                           */
+/*   Description:  Inject an Uncorrectable Error in Doubleword 0 onto   */
+/*  the FSB                                                             */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_SHFT 5
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_TO_FSB_MASK 0x0000000000000020
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB                            */
+/*   Description:  Inject a Correctable Error in Doubleword 1 onto the  */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_SHFT 6
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_TO_FSB_MASK 0x0000000000000040
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB                           */
+/*   Description:  Inject an Uncorrectable Error in Doubleword 1 onto   */
+/*  the FSB                                                             */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_SHFT 7
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_TO_FSB_MASK 0x0000000000000080
+
+/*   SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB                            */
+/*   Description:  Inject an IP[0]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_SHFT 8
+#define SH_PI_FSB_ERROR_INJECTION_IP0_PE_TO_FSB_MASK 0x0000000000000100
+
+/*   SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB                            */
+/*   Description:  Inject an IP[1]# Parity Error onto the FSB           */
+#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_SHFT 9
+#define SH_PI_FSB_ERROR_INJECTION_IP1_PE_TO_FSB_MASK 0x0000000000000200
+
+/*   SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB                           */
+/*   Description:  Inject a RP# Parity Error When Sampling the FSB      */
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_SHFT 16
+#define SH_PI_FSB_ERROR_INJECTION_RP_PE_FROM_FSB_MASK 0x0000000000010000
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB                          */
+/*   Description:  Inject an AP[0]# Parity Error When Sampling the FSB  */
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_SHFT 17
+#define SH_PI_FSB_ERROR_INJECTION_AP0_PE_FROM_FSB_MASK 0x0000000000020000
+
+/*   SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB                          */
+/*   Description:  Inject an AP[1]# Parity Error When Sampling the FSB  */
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_SHFT 18
+#define SH_PI_FSB_ERROR_INJECTION_AP1_PE_FROM_FSB_MASK 0x0000000000040000
+
+/*   SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB                          */
+/*   Description:  Inject a RSP# Parity Error When Sampling the FSB     */
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_SHFT 19
+#define SH_PI_FSB_ERROR_INJECTION_RSP_PE_FROM_FSB_MASK 0x0000000000080000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_SHFT 20
+#define SH_PI_FSB_ERROR_INJECTION_DW0_CE_FROM_FSB_MASK 0x0000000000100000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_SHFT 21
+#define SH_PI_FSB_ERROR_INJECTION_DW0_UCE_FROM_FSB_MASK 0x0000000000200000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_SHFT 22
+#define SH_PI_FSB_ERROR_INJECTION_DW1_CE_FROM_FSB_MASK 0x0000000000400000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_SHFT 23
+#define SH_PI_FSB_ERROR_INJECTION_DW1_UCE_FROM_FSB_MASK 0x0000000000800000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_SHFT 24
+#define SH_PI_FSB_ERROR_INJECTION_DW2_CE_FROM_FSB_MASK 0x0000000001000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_SHFT 25
+#define SH_PI_FSB_ERROR_INJECTION_DW2_UCE_FROM_FSB_MASK 0x0000000002000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB                          */
+/*   Description:  Inject a Correctable Error in Doubleword 0 of SIC D  */
+/*  ata Packet 0                                                        */
+#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_SHFT 26
+#define SH_PI_FSB_ERROR_INJECTION_DW3_CE_FROM_FSB_MASK 0x0000000004000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB                         */
+/*   Description:  Inject a Uncorrectable Error in Doubleword 0 of SIC  */
+/*   Data Packet 0                                                      */
+#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_SHFT 27
+#define SH_PI_FSB_ERROR_INJECTION_DW3_UCE_FROM_FSB_MASK 0x0000000008000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN                              */
+/*   Description:  Inject an ioq overrun Error on the FSB               */
+#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_SHFT 32
+#define SH_PI_FSB_ERROR_INJECTION_IOQ_OVERRUN_MASK 0x0000000100000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_LIVELOCK                                 */
+/*   Description:  Inject a livelock Error on the FSB                   */
+#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_SHFT  33
+#define SH_PI_FSB_ERROR_INJECTION_LIVELOCK_MASK  0x0000000200000000
+
+/*   SH_PI_FSB_ERROR_INJECTION_BUS_HANG                                 */
+/*   Description:  Inject an bus hang on the FSB                        */
+#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_SHFT  34
+#define SH_PI_FSB_ERROR_INJECTION_BUS_HANG_MASK  0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_CONFIG"                */
+/*             MD-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REPLY_VC_CONFIG              0x0000000120050d00
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_MASK         0xc000000000003fff
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_INIT         0x000000000000088c
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH                              */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH                             */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS                            */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT                           */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS                  */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_MD2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_CONFIG"               */
+/*            MD-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG            0x0000000120050d80
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MASK       0xc000000000003fff
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_INIT       0x000000000000088c
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH                            */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH                           */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS                          */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT                         */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS                */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_MD2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_QUEUE_ERROR_INJECTION"                */
+/*                       PI Queue Error Injection                       */
+/* ==================================================================== */
+
+#define SH_PI_QUEUE_ERROR_INJECTION              0x0000000120050e00
+#define SH_PI_QUEUE_ERROR_INJECTION_MASK         0x00000000000000ff
+#define SH_PI_QUEUE_ERROR_INJECTION_INIT         0x0000000000000000
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q                              */
+#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_SHFT 0
+#define SH_PI_QUEUE_ERROR_INJECTION_DAT_DFR_Q_MASK 0x0000000000000001
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q                         */
+#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_SHFT 1
+#define SH_PI_QUEUE_ERROR_INJECTION_DXB_WTL_CMND_Q_MASK 0x0000000000000002
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q                         */
+#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_SHFT 2
+#define SH_PI_QUEUE_ERROR_INJECTION_FSB_WTL_CMND_Q_MASK 0x0000000000000004
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR                           */
+#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_SHFT 3
+#define SH_PI_QUEUE_ERROR_INJECTION_MDPI_RPY_BFR_MASK 0x0000000000000008
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR                               */
+#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_SHFT 4
+#define SH_PI_QUEUE_ERROR_INJECTION_PTC_INTR_MASK 0x0000000000000010
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q                             */
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_SHFT 5
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_KILL_Q_MASK 0x0000000000000020
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q                              */
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_SHFT 6
+#define SH_PI_QUEUE_ERROR_INJECTION_RXL_RDY_Q_MASK 0x0000000000000040
+
+/*   SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR                           */
+#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_SHFT 7
+#define SH_PI_QUEUE_ERROR_INJECTION_XNPI_RPY_BFR_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                 Register "SH_PI_TEST_POINT_COMPARE"                  */
+/*                        PI Test Point Compare                         */
+/* ==================================================================== */
+
+#define SH_PI_TEST_POINT_COMPARE                 0x0000000120050e80
+#define SH_PI_TEST_POINT_COMPARE_MASK            0xffffffffffffffff
+#define SH_PI_TEST_POINT_COMPARE_INIT            0xffffffff00000000
+
+/*   SH_PI_TEST_POINT_COMPARE_COMPARE_MASK                              */
+/*   Description:  Mask to select test point data for trigger generati  */
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_SHFT 0
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_MASK_MASK 0x00000000ffffffff
+
+/*   SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN                           */
+/*   Description:  Pattern of test point data to cause trigger          */
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_SHFT 32
+#define SH_PI_TEST_POINT_COMPARE_COMPARE_PATTERN_MASK 0xffffffff00000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_TEST_POINT_SELECT"                  */
+/*                         PI Test Point Select                         */
+/* ==================================================================== */
+
+#define SH_PI_TEST_POINT_SELECT                  0x0000000120050f00
+#define SH_PI_TEST_POINT_SELECT_MASK             0xf777777777777777
+#define SH_PI_TEST_POINT_SELECT_INIT             0x0000000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL                        */
+/*   Description:  Nibble 0 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 0
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 0                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_PI_TEST_POINT_SELECT_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL                        */
+/*   Description:  Nibble 1 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 8
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 1                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_PI_TEST_POINT_SELECT_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL                        */
+/*   Description:  Nibble 2 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 16
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 2                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_PI_TEST_POINT_SELECT_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL                        */
+/*   Description:  Nibble 3 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 24
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 3                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_PI_TEST_POINT_SELECT_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL                        */
+/*   Description:  Nibble 4 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 32
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 4                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_PI_TEST_POINT_SELECT_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL                        */
+/*   Description:  Nibble 5 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 40
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 5                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_PI_TEST_POINT_SELECT_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL                        */
+/*   Description:  Nibble 6 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 48
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 6                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_PI_TEST_POINT_SELECT_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL                        */
+/*   Description:  Nibble 7 data is from Chiplet X                      */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 56
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL                         */
+/*   Description:  Nibble X is routed to Nibble 7                       */
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_PI_TEST_POINT_SELECT_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/*   SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE                             */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_SHFT 63
+#define SH_PI_TEST_POINT_SELECT_TRIGGER_ENABLE_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*              Register "SH_PI_TEST_POINT_TRIGGER_SELECT"              */
+/*                     PI Test Point Trigger Select                     */
+/* ==================================================================== */
+
+#define SH_PI_TEST_POINT_TRIGGER_SELECT          0x0000000120050f80
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_MASK     0x7777777777777777
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_INIT     0x0000000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL               */
+/*   Description:  Nibble 0 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_SHFT 0
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_CHIPLET_SEL_MASK 0x0000000000000007
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL                */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL               */
+/*   Description:  Nibble 1 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_SHFT 8
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_CHIPLET_SEL_MASK 0x0000000000000700
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL                */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL               */
+/*   Description:  Nibble 2 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_SHFT 16
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_CHIPLET_SEL_MASK 0x0000000000070000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL                */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL               */
+/*   Description:  Nibble 3 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_SHFT 24
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_CHIPLET_SEL_MASK 0x0000000007000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL                */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL               */
+/*   Description:  Nibble 4 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_SHFT 32
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_CHIPLET_SEL_MASK 0x0000000700000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL                */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL               */
+/*   Description:  Nibble 5 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_SHFT 40
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_CHIPLET_SEL_MASK 0x0000070000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL                */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL               */
+/*   Description:  Nibble 6 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_SHFT 48
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_CHIPLET_SEL_MASK 0x0007000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL                */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL               */
+/*   Description:  Nibble 7 Chiplet select                              */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_SHFT 56
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_CHIPLET_SEL_MASK 0x0700000000000000
+
+/*   SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL                */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_PI_TEST_POINT_TRIGGER_SELECT_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_CONFIG"                */
+/*             XN-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REPLY_VC_CONFIG              0x0000000120051000
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_MASK         0xc000000000003fff
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_INIT         0x000000000000068c
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH                              */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH                             */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS                            */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT                           */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS                  */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_XN2PI_REPLY_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_CONFIG"               */
+/*            XN-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG            0x0000000120051080
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MASK       0xc000000000003fff
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_INIT       0x000000000000068c
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH                            */
+/*   Description:  Depth of header Buffer                               */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_SHFT 0
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_HDR_DEPTH_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH                           */
+/*   Description:  Number of data buffers Available                     */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_SHFT 4
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_DATA_DEPTH_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS                          */
+/*   Description:  Maximum credits from sender                          */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_SHFT 8
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_MAX_CREDITS_MASK 0x0000000000003f00
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT                         */
+/*   Description:  Send an extra credit to sender                       */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_SHFT 62
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_FORCE_CREDIT_MASK 0x4000000000000000
+
+/*   SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS                */
+/*   Description:  Capture credit and status information                */
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_SHFT 63
+#define SH_PI_XN2PI_REQUEST_VC_CONFIG_CAPTURE_CREDIT_STATUS_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_STATUS"                      */
+/*                 PI Adaptive Error Correction Status                  */
+/* ==================================================================== */
+
+#define SH_PI_AEC_STATUS                         0x0000000120060000
+#define SH_PI_AEC_STATUS_MASK                    0x0000000000000007
+#define SH_PI_AEC_STATUS_INIT                    0x0000000000000000
+
+/*   SH_PI_AEC_STATUS_STATE                                             */
+/*   Description:  AEC State                                            */
+#define SH_PI_AEC_STATUS_STATE_SHFT              0
+#define SH_PI_AEC_STATUS_STATE_MASK              0x0000000000000007
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_FIRST_ERROR"                   */
+/*                          PI AFI First Error                          */
+/* ==================================================================== */
+
+#define SH_PI_AFI_FIRST_ERROR                    0x0000000120060080
+#define SH_PI_AFI_FIRST_ERROR_MASK               0x00000007ffe00180
+#define SH_PI_AFI_FIRST_ERROR_INIT               0x0000000000000000
+
+/*   SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE                                 */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_SHFT  7
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_UCE_MASK  0x0000000000000080
+
+/*   SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE                                  */
+/*   Description:  A correctable ECC error was detected                 */
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_SHFT   8
+#define SH_PI_AFI_FIRST_ERROR_FSB_SHUB_CE_MASK   0x0000000000000100
+
+/*   SH_PI_AFI_FIRST_ERROR_HUNG_BUS                                     */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_SHFT      21
+#define SH_PI_AFI_FIRST_ERROR_HUNG_BUS_MASK      0x0000000000200000
+
+/*   SH_PI_AFI_FIRST_ERROR_RSP_PARITY                                   */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_SHFT    22
+#define SH_PI_AFI_FIRST_ERROR_RSP_PARITY_MASK    0x0000000000400000
+
+/*   SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN                                  */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_SHFT   23
+#define SH_PI_AFI_FIRST_ERROR_IOQ_OVERRUN_MASK   0x0000000000800000
+
+/*   SH_PI_AFI_FIRST_ERROR_REQ_FORMAT                                   */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_SHFT    24
+#define SH_PI_AFI_FIRST_ERROR_REQ_FORMAT_MASK    0x0000000001000000
+
+/*   SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS                                  */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_SHFT   25
+#define SH_PI_AFI_FIRST_ERROR_ADDR_ACCESS_MASK   0x0000000002000000
+
+/*   SH_PI_AFI_FIRST_ERROR_REQ_PARITY                                   */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_SHFT    26
+#define SH_PI_AFI_FIRST_ERROR_REQ_PARITY_MASK    0x0000000004000000
+
+/*   SH_PI_AFI_FIRST_ERROR_ADDR_PARITY                                  */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_SHFT   27
+#define SH_PI_AFI_FIRST_ERROR_ADDR_PARITY_MASK   0x0000000008000000
+
+/*   SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE                                 */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_SHFT  28
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_DQE_MASK  0x0000000010000000
+
+/*   SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE                                 */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_SHFT  29
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_UCE_MASK  0x0000000020000000
+
+/*   SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE                                  */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_SHFT   30
+#define SH_PI_AFI_FIRST_ERROR_SHUB_FSB_CE_MASK   0x0000000040000000
+
+/*   SH_PI_AFI_FIRST_ERROR_LIVELOCK                                     */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_SHFT      31
+#define SH_PI_AFI_FIRST_ERROR_LIVELOCK_MASK      0x0000000080000000
+
+/*   SH_PI_AFI_FIRST_ERROR_BAD_SNOOP                                    */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_SHFT     32
+#define SH_PI_AFI_FIRST_ERROR_BAD_SNOOP_MASK     0x0000000100000000
+
+/*   SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS                                 */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_SHFT  33
+#define SH_PI_AFI_FIRST_ERROR_FSB_TBL_MISS_MASK  0x0000000200000000
+
+/*   SH_PI_AFI_FIRST_ERROR_MSG_LEN                                      */
+/*   Description:  Runt or Obese message received from SIC              */
+#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_SHFT       34
+#define SH_PI_AFI_FIRST_ERROR_MSG_LEN_MASK       0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_CAM_ADDRESS_READ_DATA"                */
+/*                    CRB CAM MMR Address Read Data                     */
+/* ==================================================================== */
+
+#define SH_PI_CAM_ADDRESS_READ_DATA              0x0000000120060100
+#define SH_PI_CAM_ADDRESS_READ_DATA_MASK         0x8000ffffffffffff
+#define SH_PI_CAM_ADDRESS_READ_DATA_INIT         0x0000000000000000
+
+/*   SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR                               */
+/*   Description:  CRB CAM Address Read Data.                           */
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_SHFT 0
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_MASK 0x0000ffffffffffff
+
+/*   SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL                           */
+/*   Description:  CRB CAM Address Read Data Valid.                     */
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_SHFT 63
+#define SH_PI_CAM_ADDRESS_READ_DATA_CAM_ADDR_VAL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_LPRA_READ_DATA"                  */
+/*                      CRB CAM MMR LPRA Read Data                      */
+/* ==================================================================== */
+
+#define SH_PI_CAM_LPRA_READ_DATA                 0x0000000120060180
+#define SH_PI_CAM_LPRA_READ_DATA_MASK            0xffffffffffffffff
+#define SH_PI_CAM_LPRA_READ_DATA_INIT            0x0000000000000000
+
+/*   SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA                                  */
+/*   Description:  CRB CAM LPRA read data.                              */
+#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_SHFT   0
+#define SH_PI_CAM_LPRA_READ_DATA_CAM_LPRA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_STATE_READ_DATA"                 */
+/*                     CRB CAM MMR State Read Data                      */
+/* ==================================================================== */
+
+#define SH_PI_CAM_STATE_READ_DATA                0x0000000120060200
+#define SH_PI_CAM_STATE_READ_DATA_MASK           0x8003ffff0000003f
+#define SH_PI_CAM_STATE_READ_DATA_INIT           0x0000000000000000
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_STATE                                */
+/*   Description:  CRB CAM State read data.                             */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_SHFT 0
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_MASK 0x000000000000000f
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_TO                                   */
+/*   Description:  CRB CAM Time-out Status.                             */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_SHFT    4
+#define SH_PI_CAM_STATE_READ_DATA_CAM_TO_MASK    0x0000000000000010
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND                        */
+/*   Description:  CRB CAM State Read Pending.                          */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_SHFT 5
+#define SH_PI_CAM_STATE_READ_DATA_CAM_STATE_RD_PEND_MASK 0x0000000000000020
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_LPRA                                 */
+/*   Description:  CRB LPRA Overflow Data.                              */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_SHFT  32
+#define SH_PI_CAM_STATE_READ_DATA_CAM_LPRA_MASK  0x0003ffff00000000
+
+/*   SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL                          */
+/*   Description:  CRB CAM MMR read data is valid.                      */
+#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_SHFT 63
+#define SH_PI_CAM_STATE_READ_DATA_CAM_RD_DATA_VAL_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_1"                  */
+/*                      PI Corrected Error Detail                       */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_1                 0x0000000120060280
+#define SH_PI_CORRECTED_DETAIL_1_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_1_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_1_ADDRESS                                   */
+/*   Description:  Address of Message that logged Correctable Error     */
+#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_SHFT    0
+#define SH_PI_CORRECTED_DETAIL_1_ADDRESS_MASK    0x0000ffffffffffff
+
+/*   SH_PI_CORRECTED_DETAIL_1_SYNDROME                                  */
+/*   Description:  Syndrome for double word data with Correctable Erro  */
+#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_SHFT   48
+#define SH_PI_CORRECTED_DETAIL_1_SYNDROME_MASK   0x00ff000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_1_DEP                                       */
+/*   Description:  DEP code for Double word in error                    */
+#define SH_PI_CORRECTED_DETAIL_1_DEP_SHFT        56
+#define SH_PI_CORRECTED_DETAIL_1_DEP_MASK        0xff00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_2"                  */
+/*                     PI Corrected Error Detail 2                      */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_2                 0x0000000120060300
+#define SH_PI_CORRECTED_DETAIL_2_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_2_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_2_DATA                                      */
+/*   Description:  Double word data in error                            */
+#define SH_PI_CORRECTED_DETAIL_2_DATA_SHFT       0
+#define SH_PI_CORRECTED_DETAIL_2_DATA_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_3"                  */
+/*                     PI Corrected Error Detail 3                      */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_3                 0x0000000120060380
+#define SH_PI_CORRECTED_DETAIL_3_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_3_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_3_ADDRESS                                   */
+/*   Description:  Address of Message that logged Correctable Error     */
+#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_SHFT    0
+#define SH_PI_CORRECTED_DETAIL_3_ADDRESS_MASK    0x0000ffffffffffff
+
+/*   SH_PI_CORRECTED_DETAIL_3_SYNDROME                                  */
+/*   Description:  Syndrome for double word data with Correctable Erro  */
+#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_SHFT   48
+#define SH_PI_CORRECTED_DETAIL_3_SYNDROME_MASK   0x00ff000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_3_DEP                                       */
+/*   Description:  DEP code for Double word in error                    */
+#define SH_PI_CORRECTED_DETAIL_3_DEP_SHFT        56
+#define SH_PI_CORRECTED_DETAIL_3_DEP_MASK        0xff00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_4"                  */
+/*                     PI Corrected Error Detail 4                      */
+/* ==================================================================== */
+
+#define SH_PI_CORRECTED_DETAIL_4                 0x0000000120060400
+#define SH_PI_CORRECTED_DETAIL_4_MASK            0xffffffffffffffff
+#define SH_PI_CORRECTED_DETAIL_4_INIT            0x0000000000000000
+
+/*   SH_PI_CORRECTED_DETAIL_4_DATA                                      */
+/*   Description:  Double word data in error                            */
+#define SH_PI_CORRECTED_DETAIL_4_DATA_SHFT       0
+#define SH_PI_CORRECTED_DETAIL_4_DATA_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PI_CRBP_FIRST_ERROR"                   */
+/*                         PI CRBP First Error                          */
+/* ==================================================================== */
+
+#define SH_PI_CRBP_FIRST_ERROR                   0x0000000120060480
+#define SH_PI_CRBP_FIRST_ERROR_MASK              0x00000000001fffff
+#define SH_PI_CRBP_FIRST_ERROR_INIT              0x0000000000000000
+
+/*   SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR                               */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_SHFT 0
+#define SH_PI_CRBP_FIRST_ERROR_FSB_PROTO_ERR_MASK 0x0000000000000001
+
+/*   SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR                                  */
+/*   Description:  CRB's XB pipe received a GFX error reply             */
+#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_SHFT   1
+#define SH_PI_CRBP_FIRST_ERROR_GFX_RP_ERR_MASK   0x0000000000000002
+
+/*   SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR                                */
+/*   Description:  CRB's XB pipe detected protocol table miss           */
+#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_SHFT 2
+#define SH_PI_CRBP_FIRST_ERROR_XB_PROTO_ERR_MASK 0x0000000000000004
+
+/*   SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR                                  */
+/*   Description:  CRB's XB pipe received a memory error reply message  */
+#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_SHFT   3
+#define SH_PI_CRBP_FIRST_ERROR_MEM_RP_ERR_MASK   0x0000000000000008
+
+/*   SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR                                  */
+/*   Description:  CRB's XB pipe received a PIO error reply message     */
+#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_SHFT   4
+#define SH_PI_CRBP_FIRST_ERROR_PIO_RP_ERR_MASK   0x0000000000000010
+
+/*   SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR                                  */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_SHFT   5
+#define SH_PI_CRBP_FIRST_ERROR_MEM_TO_ERR_MASK   0x0000000000000020
+
+/*   SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR                                  */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_SHFT   6
+#define SH_PI_CRBP_FIRST_ERROR_PIO_TO_ERR_MASK   0x0000000000000040
+
+/*   SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE                                */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_SHFT 7
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_UCE_MASK 0x0000000000000080
+
+/*   SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE                                 */
+/*   Description:  A correctable ECC error was detected                 */
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_SHFT  8
+#define SH_PI_CRBP_FIRST_ERROR_FSB_SHUB_CE_MASK  0x0000000000000100
+
+/*   SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR                               */
+/*   Description:  Message color was wrong                              */
+#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_SHFT 9
+#define SH_PI_CRBP_FIRST_ERROR_MSG_COLOR_ERR_MASK 0x0000000000000200
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW                               */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT 10
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK 0x0000000000000400
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW                               */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT 11
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_Q_OFLOW_MASK 0x0000000000000800
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW                               */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT 12
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK 0x0000000000001000
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW                               */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT 13
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_Q_OFLOW_MASK 0x0000000000002000
+
+/*   SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW                                  */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_SHFT   14
+#define SH_PI_CRBP_FIRST_ERROR_NACK_OFLOW_MASK   0x0000000000004000
+
+/*   SH_PI_CRBP_FIRST_ERROR_GFX_INT_0                                   */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_SHFT    15
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_0_MASK    0x0000000000008000
+
+/*   SH_PI_CRBP_FIRST_ERROR_GFX_INT_1                                   */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_SHFT    16
+#define SH_PI_CRBP_FIRST_ERROR_GFX_INT_1_MASK    0x0000000000010000
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW                             */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_CRBP_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW                             */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_CRBP_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW                             */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_CRBP_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW                             */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_CRBP_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_1"                    */
+/*                          PI Error Detail 1                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_DETAIL_1                     0x0000000120060500
+#define SH_PI_ERROR_DETAIL_1_MASK                0xffffffffffffffff
+#define SH_PI_ERROR_DETAIL_1_INIT                0x0000000000000000
+
+/*   SH_PI_ERROR_DETAIL_1_STATUS                                        */
+/*   Description:  Error Detail 1                                       */
+#define SH_PI_ERROR_DETAIL_1_STATUS_SHFT         0
+#define SH_PI_ERROR_DETAIL_1_STATUS_MASK         0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_2"                    */
+/*                          PI Error Detail 2                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_DETAIL_2                     0x0000000120060580
+#define SH_PI_ERROR_DETAIL_2_MASK                0xffffffffffffffff
+#define SH_PI_ERROR_DETAIL_2_INIT                0x0000000000000000
+
+/*   SH_PI_ERROR_DETAIL_2_STATUS                                        */
+/*   Description:  Error Status                                         */
+#define SH_PI_ERROR_DETAIL_2_STATUS_SHFT         0
+#define SH_PI_ERROR_DETAIL_2_STATUS_MASK         0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_OVERFLOW"                    */
+/*                          PI Error Overflow                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_OVERFLOW                     0x0000000120060600
+#define SH_PI_ERROR_OVERFLOW_MASK                0x00000007ffffffff
+#define SH_PI_ERROR_OVERFLOW_INIT                0x0000000000000000
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR                                 */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_SHFT  0
+#define SH_PI_ERROR_OVERFLOW_FSB_PROTO_ERR_MASK  0x0000000000000001
+
+/*   SH_PI_ERROR_OVERFLOW_GFX_RP_ERR                                    */
+/*   Description:  CRB's XB pipe received another GFX reply error mess  */
+#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_SHFT     1
+#define SH_PI_ERROR_OVERFLOW_GFX_RP_ERR_MASK     0x0000000000000002
+
+/*   SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR                                  */
+/*   Description:  CRB's XB pipe detected another protocol table miss  */
+#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_SHFT   2
+#define SH_PI_ERROR_OVERFLOW_XB_PROTO_ERR_MASK   0x0000000000000004
+
+/*   SH_PI_ERROR_OVERFLOW_MEM_RP_ERR                                    */
+/*   Description:  CRB's XB pipe received another memory reply error m  */
+#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_SHFT     3
+#define SH_PI_ERROR_OVERFLOW_MEM_RP_ERR_MASK     0x0000000000000008
+
+/*   SH_PI_ERROR_OVERFLOW_PIO_RP_ERR                                    */
+/*   Description:  CRB's XB pipe received another PIO reply error mess  */
+#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_SHFT     4
+#define SH_PI_ERROR_OVERFLOW_PIO_RP_ERR_MASK     0x0000000000000010
+
+/*   SH_PI_ERROR_OVERFLOW_MEM_TO_ERR                                    */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_SHFT     5
+#define SH_PI_ERROR_OVERFLOW_MEM_TO_ERR_MASK     0x0000000000000020
+
+/*   SH_PI_ERROR_OVERFLOW_PIO_TO_ERR                                    */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_SHFT     6
+#define SH_PI_ERROR_OVERFLOW_PIO_TO_ERR_MASK     0x0000000000000040
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE                                  */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_SHFT   7
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_UCE_MASK   0x0000000000000080
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE                                   */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_SHFT    8
+#define SH_PI_ERROR_OVERFLOW_FSB_SHUB_CE_MASK    0x0000000000000100
+
+/*   SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR                                 */
+/*   Description:  Message color was not correct                        */
+#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_SHFT  9
+#define SH_PI_ERROR_OVERFLOW_MSG_COLOR_ERR_MASK  0x0000000000000200
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW                                 */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_SHFT  10
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_Q_OFLOW_MASK  0x0000000000000400
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW                                 */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_SHFT  11
+#define SH_PI_ERROR_OVERFLOW_MD_RP_Q_OFLOW_MASK  0x0000000000000800
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW                                 */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_SHFT  12
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_Q_OFLOW_MASK  0x0000000000001000
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW                                 */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_SHFT  13
+#define SH_PI_ERROR_OVERFLOW_XN_RP_Q_OFLOW_MASK  0x0000000000002000
+
+/*   SH_PI_ERROR_OVERFLOW_NACK_OFLOW                                    */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_SHFT     14
+#define SH_PI_ERROR_OVERFLOW_NACK_OFLOW_MASK     0x0000000000004000
+
+/*   SH_PI_ERROR_OVERFLOW_GFX_INT_0                                     */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_SHFT      15
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_0_MASK      0x0000000000008000
+
+/*   SH_PI_ERROR_OVERFLOW_GFX_INT_1                                     */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_SHFT      16
+#define SH_PI_ERROR_OVERFLOW_GFX_INT_1_MASK      0x0000000000010000
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW                               */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_ERROR_OVERFLOW_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW                               */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_ERROR_OVERFLOW_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW                               */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_ERROR_OVERFLOW_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW                               */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_ERROR_OVERFLOW_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/*   SH_PI_ERROR_OVERFLOW_HUNG_BUS                                      */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_SHFT       21
+#define SH_PI_ERROR_OVERFLOW_HUNG_BUS_MASK       0x0000000000200000
+
+/*   SH_PI_ERROR_OVERFLOW_RSP_PARITY                                    */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_SHFT     22
+#define SH_PI_ERROR_OVERFLOW_RSP_PARITY_MASK     0x0000000000400000
+
+/*   SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN                                   */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_SHFT    23
+#define SH_PI_ERROR_OVERFLOW_IOQ_OVERRUN_MASK    0x0000000000800000
+
+/*   SH_PI_ERROR_OVERFLOW_REQ_FORMAT                                    */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_SHFT     24
+#define SH_PI_ERROR_OVERFLOW_REQ_FORMAT_MASK     0x0000000001000000
+
+/*   SH_PI_ERROR_OVERFLOW_ADDR_ACCESS                                   */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_SHFT    25
+#define SH_PI_ERROR_OVERFLOW_ADDR_ACCESS_MASK    0x0000000002000000
+
+/*   SH_PI_ERROR_OVERFLOW_REQ_PARITY                                    */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_SHFT     26
+#define SH_PI_ERROR_OVERFLOW_REQ_PARITY_MASK     0x0000000004000000
+
+/*   SH_PI_ERROR_OVERFLOW_ADDR_PARITY                                   */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_SHFT    27
+#define SH_PI_ERROR_OVERFLOW_ADDR_PARITY_MASK    0x0000000008000000
+
+/*   SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE                                  */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_SHFT   28
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_DQE_MASK   0x0000000010000000
+
+/*   SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE                                  */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_SHFT   29
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_UCE_MASK   0x0000000020000000
+
+/*   SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE                                   */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_SHFT    30
+#define SH_PI_ERROR_OVERFLOW_SHUB_FSB_CE_MASK    0x0000000040000000
+
+/*   SH_PI_ERROR_OVERFLOW_LIVELOCK                                      */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_ERROR_OVERFLOW_LIVELOCK_SHFT       31
+#define SH_PI_ERROR_OVERFLOW_LIVELOCK_MASK       0x0000000080000000
+
+/*   SH_PI_ERROR_OVERFLOW_BAD_SNOOP                                     */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_SHFT      32
+#define SH_PI_ERROR_OVERFLOW_BAD_SNOOP_MASK      0x0000000100000000
+
+/*   SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS                                  */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_SHFT   33
+#define SH_PI_ERROR_OVERFLOW_FSB_TBL_MISS_MASK   0x0000000200000000
+
+/*   SH_PI_ERROR_OVERFLOW_MSG_LENGTH                                    */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_SHFT     34
+#define SH_PI_ERROR_OVERFLOW_MSG_LENGTH_MASK     0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_ERROR_OVERFLOW_ALIAS"                 */
+/*                       PI Error Overflow Alias                        */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_OVERFLOW_ALIAS               0x0000000120060608
+
+/* ==================================================================== */
+/*                    Register "SH_PI_ERROR_SUMMARY"                    */
+/*                           PI Error Summary                           */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_SUMMARY                      0x0000000120060680
+#define SH_PI_ERROR_SUMMARY_MASK                 0x00000007ffffffff
+#define SH_PI_ERROR_SUMMARY_INIT                 0x0000000000000000
+
+/*   SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR                                  */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_SHFT   0
+#define SH_PI_ERROR_SUMMARY_FSB_PROTO_ERR_MASK   0x0000000000000001
+
+/*   SH_PI_ERROR_SUMMARY_GFX_RP_ERR                                     */
+/*   Description:  Graphic reply error message received                 */
+#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_SHFT      1
+#define SH_PI_ERROR_SUMMARY_GFX_RP_ERR_MASK      0x0000000000000002
+
+/*   SH_PI_ERROR_SUMMARY_XB_PROTO_ERR                                   */
+/*   Description:  CRB's XB pipe detected protocol table miss           */
+#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_SHFT    2
+#define SH_PI_ERROR_SUMMARY_XB_PROTO_ERR_MASK    0x0000000000000004
+
+/*   SH_PI_ERROR_SUMMARY_MEM_RP_ERR                                     */
+/*   Description:  Memory reply error message received                  */
+#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_SHFT      3
+#define SH_PI_ERROR_SUMMARY_MEM_RP_ERR_MASK      0x0000000000000008
+
+/*   SH_PI_ERROR_SUMMARY_PIO_RP_ERR                                     */
+/*   Description:  PIO error reply message received                     */
+#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_SHFT      4
+#define SH_PI_ERROR_SUMMARY_PIO_RP_ERR_MASK      0x0000000000000010
+
+/*   SH_PI_ERROR_SUMMARY_MEM_TO_ERR                                     */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_SHFT      5
+#define SH_PI_ERROR_SUMMARY_MEM_TO_ERR_MASK      0x0000000000000020
+
+/*   SH_PI_ERROR_SUMMARY_PIO_TO_ERR                                     */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_SHFT      6
+#define SH_PI_ERROR_SUMMARY_PIO_TO_ERR_MASK      0x0000000000000040
+
+/*   SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE                                   */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_SHFT    7
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_UCE_MASK    0x0000000000000080
+
+/*   SH_PI_ERROR_SUMMARY_FSB_SHUB_CE                                    */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_SHFT     8
+#define SH_PI_ERROR_SUMMARY_FSB_SHUB_CE_MASK     0x0000000000000100
+
+/*   SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR                                  */
+/*   Description:  Message color was wrong                              */
+#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_SHFT   9
+#define SH_PI_ERROR_SUMMARY_MSG_COLOR_ERR_MASK   0x0000000000000200
+
+/*   SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW                                  */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_SHFT   10
+#define SH_PI_ERROR_SUMMARY_MD_RQ_Q_OFLOW_MASK   0x0000000000000400
+
+/*   SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW                                  */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_SHFT   11
+#define SH_PI_ERROR_SUMMARY_MD_RP_Q_OFLOW_MASK   0x0000000000000800
+
+/*   SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW                                  */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_SHFT   12
+#define SH_PI_ERROR_SUMMARY_XN_RQ_Q_OFLOW_MASK   0x0000000000001000
+
+/*   SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW                                  */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_SHFT   13
+#define SH_PI_ERROR_SUMMARY_XN_RP_Q_OFLOW_MASK   0x0000000000002000
+
+/*   SH_PI_ERROR_SUMMARY_NACK_OFLOW                                     */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_SHFT      14
+#define SH_PI_ERROR_SUMMARY_NACK_OFLOW_MASK      0x0000000000004000
+
+/*   SH_PI_ERROR_SUMMARY_GFX_INT_0                                      */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_ERROR_SUMMARY_GFX_INT_0_SHFT       15
+#define SH_PI_ERROR_SUMMARY_GFX_INT_0_MASK       0x0000000000008000
+
+/*   SH_PI_ERROR_SUMMARY_GFX_INT_1                                      */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_ERROR_SUMMARY_GFX_INT_1_SHFT       16
+#define SH_PI_ERROR_SUMMARY_GFX_INT_1_MASK       0x0000000000010000
+
+/*   SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW                                */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_SHFT 17
+#define SH_PI_ERROR_SUMMARY_MD_RQ_CRD_OFLOW_MASK 0x0000000000020000
+
+/*   SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW                                */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_SHFT 18
+#define SH_PI_ERROR_SUMMARY_MD_RP_CRD_OFLOW_MASK 0x0000000000040000
+
+/*   SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW                                */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_SHFT 19
+#define SH_PI_ERROR_SUMMARY_XN_RQ_CRD_OFLOW_MASK 0x0000000000080000
+
+/*   SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW                                */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_SHFT 20
+#define SH_PI_ERROR_SUMMARY_XN_RP_CRD_OFLOW_MASK 0x0000000000100000
+
+/*   SH_PI_ERROR_SUMMARY_HUNG_BUS                                       */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_ERROR_SUMMARY_HUNG_BUS_SHFT        21
+#define SH_PI_ERROR_SUMMARY_HUNG_BUS_MASK        0x0000000000200000
+
+/*   SH_PI_ERROR_SUMMARY_RSP_PARITY                                     */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_ERROR_SUMMARY_RSP_PARITY_SHFT      22
+#define SH_PI_ERROR_SUMMARY_RSP_PARITY_MASK      0x0000000000400000
+
+/*   SH_PI_ERROR_SUMMARY_IOQ_OVERRUN                                    */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_SHFT     23
+#define SH_PI_ERROR_SUMMARY_IOQ_OVERRUN_MASK     0x0000000000800000
+
+/*   SH_PI_ERROR_SUMMARY_REQ_FORMAT                                     */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_SHFT      24
+#define SH_PI_ERROR_SUMMARY_REQ_FORMAT_MASK      0x0000000001000000
+
+/*   SH_PI_ERROR_SUMMARY_ADDR_ACCESS                                    */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_SHFT     25
+#define SH_PI_ERROR_SUMMARY_ADDR_ACCESS_MASK     0x0000000002000000
+
+/*   SH_PI_ERROR_SUMMARY_REQ_PARITY                                     */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_ERROR_SUMMARY_REQ_PARITY_SHFT      26
+#define SH_PI_ERROR_SUMMARY_REQ_PARITY_MASK      0x0000000004000000
+
+/*   SH_PI_ERROR_SUMMARY_ADDR_PARITY                                    */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_SHFT     27
+#define SH_PI_ERROR_SUMMARY_ADDR_PARITY_MASK     0x0000000008000000
+
+/*   SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE                                   */
+/*   Description:  SHUB_FSB_DQE error                                   */
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_SHFT    28
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_DQE_MASK    0x0000000010000000
+
+/*   SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE                                   */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_SHFT    29
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_UCE_MASK    0x0000000020000000
+
+/*   SH_PI_ERROR_SUMMARY_SHUB_FSB_CE                                    */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_SHFT     30
+#define SH_PI_ERROR_SUMMARY_SHUB_FSB_CE_MASK     0x0000000040000000
+
+/*   SH_PI_ERROR_SUMMARY_LIVELOCK                                       */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_ERROR_SUMMARY_LIVELOCK_SHFT        31
+#define SH_PI_ERROR_SUMMARY_LIVELOCK_MASK        0x0000000080000000
+
+/*   SH_PI_ERROR_SUMMARY_BAD_SNOOP                                      */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_SHFT       32
+#define SH_PI_ERROR_SUMMARY_BAD_SNOOP_MASK       0x0000000100000000
+
+/*   SH_PI_ERROR_SUMMARY_FSB_TBL_MISS                                   */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_SHFT    33
+#define SH_PI_ERROR_SUMMARY_FSB_TBL_MISS_MASK    0x0000000200000000
+
+/*   SH_PI_ERROR_SUMMARY_MSG_LENGTH                                     */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_SHFT      34
+#define SH_PI_ERROR_SUMMARY_MSG_LENGTH_MASK      0x0000000400000000
+
+/* ==================================================================== */
+/*                 Register "SH_PI_ERROR_SUMMARY_ALIAS"                 */
+/*                        PI Error Summary Alias                        */
+/* ==================================================================== */
+
+#define SH_PI_ERROR_SUMMARY_ALIAS                0x0000000120060688
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_STATUS"                 */
+/*                       PI Express Reply Status                        */
+/* ==================================================================== */
+
+#define SH_PI_EXPRESS_REPLY_STATUS               0x0000000120060700
+#define SH_PI_EXPRESS_REPLY_STATUS_MASK          0x0000000000000007
+#define SH_PI_EXPRESS_REPLY_STATUS_INIT          0x0000000000000000
+
+/*   SH_PI_EXPRESS_REPLY_STATUS_STATE                                   */
+/*   Description:  Express Reply State                                  */
+#define SH_PI_EXPRESS_REPLY_STATUS_STATE_SHFT    0
+#define SH_PI_EXPRESS_REPLY_STATUS_STATE_MASK    0x0000000000000007
+
+/* ==================================================================== */
+/*                     Register "SH_PI_FIRST_ERROR"                     */
+/*                            PI First Error                            */
+/* ==================================================================== */
+
+#define SH_PI_FIRST_ERROR                        0x0000000120060780
+#define SH_PI_FIRST_ERROR_MASK                   0x00000007ffffffff
+#define SH_PI_FIRST_ERROR_INIT                   0x0000000000000000
+
+/*   SH_PI_FIRST_ERROR_FSB_PROTO_ERR                                    */
+/*   Description:  CRB's FSB pipe detected protocol table miss          */
+#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_SHFT     0
+#define SH_PI_FIRST_ERROR_FSB_PROTO_ERR_MASK     0x0000000000000001
+
+/*   SH_PI_FIRST_ERROR_GFX_RP_ERR                                       */
+/*   Description:  Graphics error reply message received                */
+#define SH_PI_FIRST_ERROR_GFX_RP_ERR_SHFT        1
+#define SH_PI_FIRST_ERROR_GFX_RP_ERR_MASK        0x0000000000000002
+
+/*   SH_PI_FIRST_ERROR_XB_PROTO_ERR                                     */
+/*   Description:  CRB's XB pipe detected protocol table miss           */
+#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_SHFT      2
+#define SH_PI_FIRST_ERROR_XB_PROTO_ERR_MASK      0x0000000000000004
+
+/*   SH_PI_FIRST_ERROR_MEM_RP_ERR                                       */
+/*   Description:  Memory reply error message received                  */
+#define SH_PI_FIRST_ERROR_MEM_RP_ERR_SHFT        3
+#define SH_PI_FIRST_ERROR_MEM_RP_ERR_MASK        0x0000000000000008
+
+/*   SH_PI_FIRST_ERROR_PIO_RP_ERR                                       */
+/*   Description:  PIO reply error message received                     */
+#define SH_PI_FIRST_ERROR_PIO_RP_ERR_SHFT        4
+#define SH_PI_FIRST_ERROR_PIO_RP_ERR_MASK        0x0000000000000010
+
+/*   SH_PI_FIRST_ERROR_MEM_TO_ERR                                       */
+/*   Description:  CRB's XB pipe detected a CRB time-out                */
+#define SH_PI_FIRST_ERROR_MEM_TO_ERR_SHFT        5
+#define SH_PI_FIRST_ERROR_MEM_TO_ERR_MASK        0x0000000000000020
+
+/*   SH_PI_FIRST_ERROR_PIO_TO_ERR                                       */
+/*   Description:  CRB's XB pipe detected a PIO time-out                */
+#define SH_PI_FIRST_ERROR_PIO_TO_ERR_SHFT        6
+#define SH_PI_FIRST_ERROR_PIO_TO_ERR_MASK        0x0000000000000040
+
+/*   SH_PI_FIRST_ERROR_FSB_SHUB_UCE                                     */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_SHFT      7
+#define SH_PI_FIRST_ERROR_FSB_SHUB_UCE_MASK      0x0000000000000080
+
+/*   SH_PI_FIRST_ERROR_FSB_SHUB_CE                                      */
+/*   Description:  A correctable ECC error was detected                 */
+#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_SHFT       8
+#define SH_PI_FIRST_ERROR_FSB_SHUB_CE_MASK       0x0000000000000100
+
+/*   SH_PI_FIRST_ERROR_MSG_COLOR_ERR                                    */
+/*   Description:  Message color was wrong                              */
+#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_SHFT     9
+#define SH_PI_FIRST_ERROR_MSG_COLOR_ERR_MASK     0x0000000000000200
+
+/*   SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW                                    */
+/*   Description:  MD Request input buffer over flow error              */
+#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_SHFT     10
+#define SH_PI_FIRST_ERROR_MD_RQ_Q_OFLOW_MASK     0x0000000000000400
+
+/*   SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW                                    */
+/*   Description:  MD Reply input buffer over flow error                */
+#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_SHFT     11
+#define SH_PI_FIRST_ERROR_MD_RP_Q_OFLOW_MASK     0x0000000000000800
+
+/*   SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW                                    */
+/*   Description:  XN Request input buffer over flow error              */
+#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_SHFT     12
+#define SH_PI_FIRST_ERROR_XN_RQ_Q_OFLOW_MASK     0x0000000000001000
+
+/*   SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW                                    */
+/*   Description:  XN Reply input buffer over flow error                */
+#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_SHFT     13
+#define SH_PI_FIRST_ERROR_XN_RP_Q_OFLOW_MASK     0x0000000000002000
+
+/*   SH_PI_FIRST_ERROR_NACK_OFLOW                                       */
+/*   Description:  NACK over flow error                                 */
+#define SH_PI_FIRST_ERROR_NACK_OFLOW_SHFT        14
+#define SH_PI_FIRST_ERROR_NACK_OFLOW_MASK        0x0000000000004000
+
+/*   SH_PI_FIRST_ERROR_GFX_INT_0                                        */
+/*   Description:  GFX transfer interrupt for CPU 0                     */
+#define SH_PI_FIRST_ERROR_GFX_INT_0_SHFT         15
+#define SH_PI_FIRST_ERROR_GFX_INT_0_MASK         0x0000000000008000
+
+/*   SH_PI_FIRST_ERROR_GFX_INT_1                                        */
+/*   Description:  GFX transfer interrupt for CPU 1                     */
+#define SH_PI_FIRST_ERROR_GFX_INT_1_SHFT         16
+#define SH_PI_FIRST_ERROR_GFX_INT_1_MASK         0x0000000000010000
+
+/*   SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW                                  */
+/*   Description:  MD Request Credit Overflow Error                     */
+#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_SHFT   17
+#define SH_PI_FIRST_ERROR_MD_RQ_CRD_OFLOW_MASK   0x0000000000020000
+
+/*   SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW                                  */
+/*   Description:  MD Reply Credit Overflow Error                       */
+#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_SHFT   18
+#define SH_PI_FIRST_ERROR_MD_RP_CRD_OFLOW_MASK   0x0000000000040000
+
+/*   SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW                                  */
+/*   Description:  XN Request Credit Overflow Error                     */
+#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_SHFT   19
+#define SH_PI_FIRST_ERROR_XN_RQ_CRD_OFLOW_MASK   0x0000000000080000
+
+/*   SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW                                  */
+/*   Description:  XN Reply Credit Overflow Error                       */
+#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_SHFT   20
+#define SH_PI_FIRST_ERROR_XN_RP_CRD_OFLOW_MASK   0x0000000000100000
+
+/*   SH_PI_FIRST_ERROR_HUNG_BUS                                         */
+/*   Description:  FSB is hung                                          */
+#define SH_PI_FIRST_ERROR_HUNG_BUS_SHFT          21
+#define SH_PI_FIRST_ERROR_HUNG_BUS_MASK          0x0000000000200000
+
+/*   SH_PI_FIRST_ERROR_RSP_PARITY                                       */
+/*   Description:  Parity error detecte during response phase           */
+#define SH_PI_FIRST_ERROR_RSP_PARITY_SHFT        22
+#define SH_PI_FIRST_ERROR_RSP_PARITY_MASK        0x0000000000400000
+
+/*   SH_PI_FIRST_ERROR_IOQ_OVERRUN                                      */
+/*   Description:  Over run error detected on IOQ                       */
+#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_SHFT       23
+#define SH_PI_FIRST_ERROR_IOQ_OVERRUN_MASK       0x0000000000800000
+
+/*   SH_PI_FIRST_ERROR_REQ_FORMAT                                       */
+/*   Description:  FSB request format not supported                     */
+#define SH_PI_FIRST_ERROR_REQ_FORMAT_SHFT        24
+#define SH_PI_FIRST_ERROR_REQ_FORMAT_MASK        0x0000000001000000
+
+/*   SH_PI_FIRST_ERROR_ADDR_ACCESS                                      */
+/*   Description:  Access to Address is not supported                   */
+#define SH_PI_FIRST_ERROR_ADDR_ACCESS_SHFT       25
+#define SH_PI_FIRST_ERROR_ADDR_ACCESS_MASK       0x0000000002000000
+
+/*   SH_PI_FIRST_ERROR_REQ_PARITY                                       */
+/*   Description:  Parity error detected during request phase           */
+#define SH_PI_FIRST_ERROR_REQ_PARITY_SHFT        26
+#define SH_PI_FIRST_ERROR_REQ_PARITY_MASK        0x0000000004000000
+
+/*   SH_PI_FIRST_ERROR_ADDR_PARITY                                      */
+/*   Description:  Parity error detected on address                     */
+#define SH_PI_FIRST_ERROR_ADDR_PARITY_SHFT       27
+#define SH_PI_FIRST_ERROR_ADDR_PARITY_MASK       0x0000000008000000
+
+/*   SH_PI_FIRST_ERROR_SHUB_FSB_DQE                                     */
+/*   Description:  SHUB_FSB_DQE                                         */
+#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_SHFT      28
+#define SH_PI_FIRST_ERROR_SHUB_FSB_DQE_MASK      0x0000000010000000
+
+/*   SH_PI_FIRST_ERROR_SHUB_FSB_UCE                                     */
+/*   Description:  An un-correctable ECC error was detected             */
+#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_SHFT      29
+#define SH_PI_FIRST_ERROR_SHUB_FSB_UCE_MASK      0x0000000020000000
+
+/*   SH_PI_FIRST_ERROR_SHUB_FSB_CE                                      */
+/*   Description:  An correctable ECC error was detected                */
+#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_SHFT       30
+#define SH_PI_FIRST_ERROR_SHUB_FSB_CE_MASK       0x0000000040000000
+
+/*   SH_PI_FIRST_ERROR_LIVELOCK                                         */
+/*   Description:  AFI livelock error was detected                      */
+#define SH_PI_FIRST_ERROR_LIVELOCK_SHFT          31
+#define SH_PI_FIRST_ERROR_LIVELOCK_MASK          0x0000000080000000
+
+/*   SH_PI_FIRST_ERROR_BAD_SNOOP                                        */
+/*   Description:  AFI bad snoop error was detected                     */
+#define SH_PI_FIRST_ERROR_BAD_SNOOP_SHFT         32
+#define SH_PI_FIRST_ERROR_BAD_SNOOP_MASK         0x0000000100000000
+
+/*   SH_PI_FIRST_ERROR_FSB_TBL_MISS                                     */
+/*   Description:  AFI FSB request table miss error was detected        */
+#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_SHFT      33
+#define SH_PI_FIRST_ERROR_FSB_TBL_MISS_MASK      0x0000000200000000
+
+/*   SH_PI_FIRST_ERROR_MSG_LENGTH                                       */
+/*   Description:  Message length error on received message from SIC    */
+#define SH_PI_FIRST_ERROR_MSG_LENGTH_SHFT        34
+#define SH_PI_FIRST_ERROR_MSG_LENGTH_MASK        0x0000000400000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FIRST_ERROR_ALIAS"                  */
+/*                         PI First Error Alias                         */
+/* ==================================================================== */
+
+#define SH_PI_FIRST_ERROR_ALIAS                  0x0000000120060788
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2MD_REPLY_VC_STATUS"                */
+/*                PI-to-MD Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_PI2MD_REPLY_VC_STATUS              0x0000000120060900
+#define SH_PI_PI2MD_REPLY_VC_STATUS_MASK         0x000000000000003f
+#define SH_PI_PI2MD_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT                        */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2MD_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2MD_REQUEST_VC_STATUS"               */
+/*               PI-to-MD Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_PI2MD_REQUEST_VC_STATUS            0x0000000120060980
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_MASK       0x000000000000003f
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT                      */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2MD_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2XN_REPLY_VC_STATUS"                */
+/*                PI-to-XN Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_PI2XN_REPLY_VC_STATUS              0x0000000120060a00
+#define SH_PI_PI2XN_REPLY_VC_STATUS_MASK         0x000000000000003f
+#define SH_PI_PI2XN_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT                        */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2XN_REPLY_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2XN_REQUEST_VC_STATUS"               */
+/*               PI-to-XN Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_PI2XN_REQUEST_VC_STATUS            0x0000000120060a80
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_MASK       0x000000000000003f
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT                      */
+/*   Description:  Status of output credits                             */
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_SHFT 0
+#define SH_PI_PI2XN_REQUEST_VC_STATUS_OUTPUT_CRD_STAT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_1"                 */
+/*                    PI Uncorrected Error Detail 1                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_1               0x0000000120060b00
+#define SH_PI_UNCORRECTED_DETAIL_1_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_1_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_1_ADDRESS                                 */
+/*   Description:  Address of Message that logged Uncorrectable Error  */
+#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_SHFT  0
+#define SH_PI_UNCORRECTED_DETAIL_1_ADDRESS_MASK  0x0000ffffffffffff
+
+/*   SH_PI_UNCORRECTED_DETAIL_1_SYNDROME                                */
+/*   Description:  Syndrome for double word data with Uncorrectable Er  */
+#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_SHFT 48
+#define SH_PI_UNCORRECTED_DETAIL_1_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_1_DEP                                     */
+/*   Description:  DEP for Double word in error                         */
+#define SH_PI_UNCORRECTED_DETAIL_1_DEP_SHFT      56
+#define SH_PI_UNCORRECTED_DETAIL_1_DEP_MASK      0xff00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_2"                 */
+/*                    PI Uncorrected Error Detail 2                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_2               0x0000000120060b80
+#define SH_PI_UNCORRECTED_DETAIL_2_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_2_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_2_DATA                                    */
+/*   Description:  Double word data in error                            */
+#define SH_PI_UNCORRECTED_DETAIL_2_DATA_SHFT     0
+#define SH_PI_UNCORRECTED_DETAIL_2_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_3"                 */
+/*                    PI Uncorrected Error Detail 3                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_3               0x0000000120060c00
+#define SH_PI_UNCORRECTED_DETAIL_3_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_3_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_3_ADDRESS                                 */
+/*   Description:  Address of Message that logged Uncorrectable Error  */
+#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_SHFT  0
+#define SH_PI_UNCORRECTED_DETAIL_3_ADDRESS_MASK  0x0000ffffffffffff
+
+/*   SH_PI_UNCORRECTED_DETAIL_3_SYNDROME                                */
+/*   Description:  Syndrome for double word data with Uncorrectable Er  */
+#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_SHFT 48
+#define SH_PI_UNCORRECTED_DETAIL_3_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_3_DEP                                     */
+/*   Description:  DCP for Double word in error                         */
+#define SH_PI_UNCORRECTED_DETAIL_3_DEP_SHFT      56
+#define SH_PI_UNCORRECTED_DETAIL_3_DEP_MASK      0xff00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_4"                 */
+/*                    PI Uncorrected Error Detail 4                     */
+/* ==================================================================== */
+
+#define SH_PI_UNCORRECTED_DETAIL_4               0x0000000120060c80
+#define SH_PI_UNCORRECTED_DETAIL_4_MASK          0xffffffffffffffff
+#define SH_PI_UNCORRECTED_DETAIL_4_INIT          0x0000000000000000
+
+/*   SH_PI_UNCORRECTED_DETAIL_4_DATA                                    */
+/*   Description:  Double word data in error                            */
+#define SH_PI_UNCORRECTED_DETAIL_4_DATA_SHFT     0
+#define SH_PI_UNCORRECTED_DETAIL_4_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_STATUS"                */
+/*                MD-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REPLY_VC_STATUS              0x0000000120060800
+#define SH_PI_MD2PI_REPLY_VC_STATUS_MASK         0x0000000000000fff
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT                     */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT                     */
+/*   Description:  Status of data credits                               */
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT                       */
+/*   Description:  Status of MD Reply Input Queue                       */
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_MD2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_STATUS"               */
+/*               MD-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_MD2PI_REQUEST_VC_STATUS            0x0000000120060880
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_MASK       0x0000000000000fff
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT                   */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT                   */
+/*   Description:  Status of input data credits                         */
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT                     */
+/*   Description:  Status of MD Request Input Queue                     */
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_MD2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_STATUS"                */
+/*                XN-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REPLY_VC_STATUS              0x0000000120060d00
+#define SH_PI_XN2PI_REPLY_VC_STATUS_MASK         0x0000000000000fff
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INIT         0x0000000000000000
+
+/*   SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT                     */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT                     */
+/*   Description:  Status of input data credits                         */
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT                       */
+/*   Description:  Status of XN Reply Input Queue                       */
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_XN2PI_REPLY_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_STATUS"               */
+/*               XN-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#define SH_PI_XN2PI_REQUEST_VC_STATUS            0x0000000120060d80
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_MASK       0x0000000000000fff
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INIT       0x0000000000000000
+
+/*   SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT                   */
+/*   Description:  Status of input header credits                       */
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_SHFT 0
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_HDR_CRD_STAT_MASK 0x000000000000000f
+
+/*   SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT                   */
+/*   Description:  Status of input data credits                         */
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_SHFT 4
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_DAT_CRD_STAT_MASK 0x00000000000000f0
+
+/*   SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT                     */
+/*   Description:  Status of XN Request Input Queue                     */
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_SHFT 8
+#define SH_PI_XN2PI_REQUEST_VC_STATUS_INPUT_QUEUE_STAT_MASK 0x0000000000000f00
+
+/* ==================================================================== */
+/*                     Register "SH_XNPI_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNPI_SIC_FLOW                         0x0000000150030000
+#define SH_XNPI_SIC_FLOW_MASK                    0x9f1f1f1f1f1f9f9f
+#define SH_XNPI_SIC_FLOW_INIT                    0x0000080000080000
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD                                */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED                              */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD                                */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00
+
+/*   SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED                              */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST                                   */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_SHFT    16
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_TEST_MASK    0x00000000001f0000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN                                    */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_SHFT     24
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_DYN_MASK     0x000000001f000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP                                    */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_SHFT     32
+#define SH_XNPI_SIC_FLOW_CREDIT_VC0_CAP_MASK     0x0000001f00000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST                                   */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_SHFT    40
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_TEST_MASK    0x00001f0000000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN                                    */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_SHFT     48
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_DYN_MASK     0x001f000000000000
+
+/*   SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP                                    */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_SHFT     56
+#define SH_XNPI_SIC_FLOW_CREDIT_VC2_CAP_MASK     0x1f00000000000000
+
+/*   SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT                                */
+#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63
+#define SH_XNPI_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNPI_TO_NI0_PORT_FLOW                 0x0000000150030010
+#define SH_XNPI_TO_NI0_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNPI_TO_NI0_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNPI_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNPI_TO_NI1_PORT_FLOW                 0x0000000150030020
+#define SH_XNPI_TO_NI1_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNPI_TO_NI1_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNPI_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_TO_IILB_PORT_FLOW                0x0000000150030030
+#define SH_XNPI_TO_IILB_PORT_FLOW_MASK           0x3f3f003f3f00bfbf
+#define SH_XNPI_TO_IILB_PORT_FLOW_INIT           0x0000000000000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNPI_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNPI_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO            0x0000000150030040
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNPI_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO            0x0000000150030050
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNPI_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO           0x0000000150030060
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_MASK      0x00001f1f3f3f3f3f
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_INIT      0x00000c0c00000000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN                       */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP                       */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN                       */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP                       */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST                      */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST                      */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNPI_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XNMD_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNMD_SIC_FLOW                         0x0000000150030100
+#define SH_XNMD_SIC_FLOW_MASK                    0x9f1f1f1f1f1f9f9f
+#define SH_XNMD_SIC_FLOW_INIT                    0x0000090000090000
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD                                */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000001f
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED                              */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_SIC_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD                                */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000001f00
+
+/*   SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED                              */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_SIC_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST                                   */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_SHFT    16
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_TEST_MASK    0x00000000001f0000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN                                    */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_SHFT     24
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_DYN_MASK     0x000000001f000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP                                    */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_SHFT     32
+#define SH_XNMD_SIC_FLOW_CREDIT_VC0_CAP_MASK     0x0000001f00000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST                                   */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_SHFT    40
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_TEST_MASK    0x00001f0000000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN                                    */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_SHFT     48
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_DYN_MASK     0x001f000000000000
+
+/*   SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP                                    */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_SHFT     56
+#define SH_XNMD_SIC_FLOW_CREDIT_VC2_CAP_MASK     0x1f00000000000000
+
+/*   SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT                                */
+#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_SHFT 63
+#define SH_XNMD_SIC_FLOW_DISABLE_BYPASS_OUT_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNMD_TO_NI0_PORT_FLOW                 0x0000000150030110
+#define SH_XNMD_TO_NI0_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNMD_TO_NI0_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_TO_NI0_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNMD_TO_NI0_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNMD_TO_NI1_PORT_FLOW                 0x0000000150030120
+#define SH_XNMD_TO_NI1_PORT_FLOW_MASK            0x3f3f003f3f00bfbf
+#define SH_XNMD_TO_NI1_PORT_FLOW_INIT            0x0000000000000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD                        */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED                      */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD                        */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED                      */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_TO_NI1_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN                            */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP                            */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN                            */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP                            */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNMD_TO_NI1_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_TO_IILB_PORT_FLOW                0x0000000150030130
+#define SH_XNMD_TO_IILB_PORT_FLOW_MASK           0x3f3f003f3f00bfbf
+#define SH_XNMD_TO_IILB_PORT_FLOW_INIT           0x0000000000000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNMD_TO_IILB_PORT_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_SHFT 24
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_DYN_MASK 0x000000003f000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_SHFT 32
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC0_CAP_MASK 0x0000003f00000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_SHFT 48
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_DYN_MASK 0x003f000000000000
+
+/*   SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_SHFT 56
+#define SH_XNMD_TO_IILB_PORT_FLOW_CREDIT_VC2_CAP_MASK 0x3f00000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO            0x0000000150030140
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNMD_FR_NI0_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO            0x0000000150030150
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_MASK       0x00001f1f3f3f3f3f
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_INIT       0x00000c0c00000000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN                        */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP                        */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN                        */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP                        */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST                       */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST                       */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNMD_FR_NI1_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO           0x0000000150030160
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_MASK      0x00001f1f3f3f3f3f
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_INIT      0x00000c0c00000000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN                       */
+/*   Description:  vc0 fifo entry dynamic value                         */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_SHFT 0
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_DYN_MASK 0x000000000000003f
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP                       */
+/*   Description:  vc0 fifo entry captured value                        */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_SHFT 8
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_CAP_MASK 0x0000000000003f00
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN                       */
+/*   Description:  vc2 fifo entry dynamic value                         */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_SHFT 16
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_DYN_MASK 0x00000000003f0000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP                       */
+/*   Description:  vc2 fifo entry  captured value                       */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_SHFT 24
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_CAP_MASK 0x000000003f000000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST                      */
+/*   Description:  vc0 test credits limit                               */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_SHFT 32
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC0_TEST_MASK 0x0000001f00000000
+
+/*   SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST                      */
+/*   Description:  vc2 test credits limit                               */
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_SHFT 40
+#define SH_XNMD_FR_IILB_PORT_FLOW_FIFO_ENTRY_VC2_TEST_MASK 0x00001f0000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNII_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNII_INTRA_FLOW                       0x0000000150030200
+#define SH_XNII_INTRA_FLOW_MASK                  0x7f7f7f7f7f7fbfbf
+#define SH_XNII_INTRA_FLOW_INIT                  0x00003f00003f0000
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD                              */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                            */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNII_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD                              */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                            */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNII_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST                                 */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_SHFT  16
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_TEST_MASK  0x00000000007f0000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN                                  */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_SHFT   24
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_DYN_MASK   0x000000007f000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP                                  */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_SHFT   32
+#define SH_XNII_INTRA_FLOW_CREDIT_VC0_CAP_MASK   0x0000007f00000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST                                 */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_SHFT  40
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_TEST_MASK  0x00007f0000000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN                                  */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_SHFT   48
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_DYN_MASK   0x007f000000000000
+
+/*   SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP                                  */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_SHFT   56
+#define SH_XNII_INTRA_FLOW_CREDIT_VC2_CAP_MASK   0x7f00000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNLB_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNLB_INTRA_FLOW                       0x0000000150030210
+#define SH_XNLB_INTRA_FLOW_MASK                  0xff7f7f7f7f7fbfbf
+#define SH_XNLB_INTRA_FLOW_INIT                  0x0000080000100000
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                              */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                            */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                              */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                            */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNLB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST                                 */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT  16
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_TEST_MASK  0x00000000007f0000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN                                  */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT   24
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_DYN_MASK   0x000000007f000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP                                  */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT   32
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC0_CAP_MASK   0x0000007f00000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST                                 */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT  40
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_TEST_MASK  0x00007f0000000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN                                  */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT   48
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_DYN_MASK   0x007f000000000000
+
+/*   SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP                                  */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT   56
+#define SH_XNLB_INTRA_FLOW_CREDIT_VC2_CAP_MASK   0x7f00000000000000
+
+/*   SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN                               */
+#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_SHFT 63
+#define SH_XNLB_INTRA_FLOW_DISABLE_BYPASS_IN_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT        0x0000000150030220
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT        0x0000000150030230
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT         0x0000000150030240
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_MASK    0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_INIT    0x0000000000000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD                      */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                    */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD                      */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                    */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN                           */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP                           */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN                           */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP                           */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT       0x0000000150030250
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_MASK  0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_INIT  0x0000000000000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                    */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                  */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                    */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                  */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN                         */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP                         */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN                         */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP                         */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT         0x0000000150030260
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_MASK    0x7f7f007f7f00bfbf
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_INIT    0x0000000000000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD                      */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                    */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD                      */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                    */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN                           */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP                           */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN                           */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP                           */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT       0x0000000150030270
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT       0x0000000150030280
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT        0x0000000150030290
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_MASK   0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_INIT   0x000000000c00000c
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST                         */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN                          */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP                          */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST                         */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN                          */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP                          */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT"            */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT      0x00000001500302a0
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_MASK 0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_INIT 0x000000000c00000c
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST                       */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN                        */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP                        */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST                       */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN                        */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP                        */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT        0x00000001500302b0
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_MASK   0x00007f7f7f7f7f7f
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_INIT   0x000000000c00000c
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST                         */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN                          */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP                          */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST                         */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN                          */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP                          */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT          0x0000000150030300
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT          0x0000000150030310
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT        0x0000000150030320
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT         0x0000000150030330
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT         0x0000000150030340
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT       0x0000000150030350
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_0_INTRANI_FLOW                  0x0000000150030360
+#define SH_XNNI0_0_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_0_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD                         */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED                       */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI0_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_1_INTRANI_FLOW                  0x0000000150030370
+#define SH_XNNI0_1_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_1_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD                         */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED                       */
+/*   Description:  Force Credit on VC1 from debit cntr                  */
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI0_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_2_INTRANI_FLOW                  0x0000000150030380
+#define SH_XNNI0_2_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_2_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD                         */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED                       */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI0_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI0_3_INTRANI_FLOW                  0x0000000150030390
+#define SH_XNNI0_3_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI0_3_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD                         */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED                       */
+/*   Description:  Force Credit on VC3 from debit cntr                  */
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI0_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNNI0_VCSWITCH_FLOW                   0x00000001500303a0
+#define SH_XNNI0_VCSWITCH_FLOW_MASK              0x0000000701010101
+#define SH_XNNI0_VCSWITCH_FLOW_INIT              0x0000000000000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH                   */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0
+#define SH_XNNI0_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001
+
+/*   SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8
+#define SH_XNNI0_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100
+
+/*   SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16
+#define SH_XNNI0_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH                          */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24
+#define SH_XNNI0_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN                      */
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT                     */
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33
+#define SH_XNNI0_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000
+
+/*   SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES                                */
+#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34
+#define SH_XNNI0_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_TIMER_REG"                     */
+/* ==================================================================== */
+
+#define SH_XNNI0_TIMER_REG                       0x00000001500303b0
+#define SH_XNNI0_TIMER_REG_MASK                  0x0000000100ffffff
+#define SH_XNNI0_TIMER_REG_INIT                  0x0000000000ffffff
+
+/*   SH_XNNI0_TIMER_REG_TIMEOUT_REG                                     */
+/*   Description:  Master Timeout Counter                               */
+#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_SHFT      0
+#define SH_XNNI0_TIMER_REG_TIMEOUT_REG_MASK      0x0000000000ffffff
+
+/*   SH_XNNI0_TIMER_REG_LINKCLEANUP_REG                                 */
+/*   Description:  Link Clean Up                                        */
+#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_SHFT  32
+#define SH_XNNI0_TIMER_REG_LINKCLEANUP_REG_MASK  0x0000000100000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_FIFO02_FLOW                     0x00000001500303c0
+#define SH_XNNI0_FIFO02_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI0_FIFO02_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_SHFT  8
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_SHFT  16
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC0_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_SHFT  32
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_SHFT  40
+#define SH_XNNI0_FIFO02_FLOW_COUNT_VC2_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_FIFO13_FLOW                     0x00000001500303d0
+#define SH_XNNI0_FIFO13_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI0_FIFO13_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_SHFT  8
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_SHFT  16
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC1_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_SHFT  32
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_SHFT  40
+#define SH_XNNI0_FIFO13_FLOW_COUNT_VC3_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI0_NI_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNNI0_NI_FLOW                         0x00000001500303e0
+#define SH_XNNI0_NI_FLOW_MASK                    0xff0fff0fff0fff0f
+#define SH_XNNI0_NI_FLOW_INIT                    0x0000000000000000
+
+/*   SH_XNNI0_NI_FLOW_VC0_LIMIT                                         */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC0_LIMIT_SHFT          0
+#define SH_XNNI0_NI_FLOW_VC0_LIMIT_MASK          0x000000000000000f
+
+/*   SH_XNNI0_NI_FLOW_VC0_DYN                                           */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC0_DYN_SHFT            8
+#define SH_XNNI0_NI_FLOW_VC0_DYN_MASK            0x0000000000000f00
+
+/*   SH_XNNI0_NI_FLOW_VC0_CAP                                           */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC0_CAP_SHFT            12
+#define SH_XNNI0_NI_FLOW_VC0_CAP_MASK            0x000000000000f000
+
+/*   SH_XNNI0_NI_FLOW_VC1_LIMIT                                         */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC1_LIMIT_SHFT          16
+#define SH_XNNI0_NI_FLOW_VC1_LIMIT_MASK          0x00000000000f0000
+
+/*   SH_XNNI0_NI_FLOW_VC1_DYN                                           */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC1_DYN_SHFT            24
+#define SH_XNNI0_NI_FLOW_VC1_DYN_MASK            0x000000000f000000
+
+/*   SH_XNNI0_NI_FLOW_VC1_CAP                                           */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC1_CAP_SHFT            28
+#define SH_XNNI0_NI_FLOW_VC1_CAP_MASK            0x00000000f0000000
+
+/*   SH_XNNI0_NI_FLOW_VC2_LIMIT                                         */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC2_LIMIT_SHFT          32
+#define SH_XNNI0_NI_FLOW_VC2_LIMIT_MASK          0x0000000f00000000
+
+/*   SH_XNNI0_NI_FLOW_VC2_DYN                                           */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC2_DYN_SHFT            40
+#define SH_XNNI0_NI_FLOW_VC2_DYN_MASK            0x00000f0000000000
+
+/*   SH_XNNI0_NI_FLOW_VC2_CAP                                           */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC2_CAP_SHFT            44
+#define SH_XNNI0_NI_FLOW_VC2_CAP_MASK            0x0000f00000000000
+
+/*   SH_XNNI0_NI_FLOW_VC3_LIMIT                                         */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI0_NI_FLOW_VC3_LIMIT_SHFT          48
+#define SH_XNNI0_NI_FLOW_VC3_LIMIT_MASK          0x000f000000000000
+
+/*   SH_XNNI0_NI_FLOW_VC3_DYN                                           */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI0_NI_FLOW_VC3_DYN_SHFT            56
+#define SH_XNNI0_NI_FLOW_VC3_DYN_MASK            0x0f00000000000000
+
+/*   SH_XNNI0_NI_FLOW_VC3_CAP                                           */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI0_NI_FLOW_VC3_CAP_SHFT            60
+#define SH_XNNI0_NI_FLOW_VC3_CAP_MASK            0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNNI0_DEAD_FLOW                       0x00000001500303f0
+#define SH_XNNI0_DEAD_FLOW_MASK                  0xff0fff0fff0fff0f
+#define SH_XNNI0_DEAD_FLOW_INIT                  0x0000000000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC0_LIMIT                                       */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_SHFT        0
+#define SH_XNNI0_DEAD_FLOW_VC0_LIMIT_MASK        0x000000000000000f
+
+/*   SH_XNNI0_DEAD_FLOW_VC0_DYN                                         */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC0_DYN_SHFT          8
+#define SH_XNNI0_DEAD_FLOW_VC0_DYN_MASK          0x0000000000000f00
+
+/*   SH_XNNI0_DEAD_FLOW_VC0_CAP                                         */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC0_CAP_SHFT          12
+#define SH_XNNI0_DEAD_FLOW_VC0_CAP_MASK          0x000000000000f000
+
+/*   SH_XNNI0_DEAD_FLOW_VC1_LIMIT                                       */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_SHFT        16
+#define SH_XNNI0_DEAD_FLOW_VC1_LIMIT_MASK        0x00000000000f0000
+
+/*   SH_XNNI0_DEAD_FLOW_VC1_DYN                                         */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC1_DYN_SHFT          24
+#define SH_XNNI0_DEAD_FLOW_VC1_DYN_MASK          0x000000000f000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC1_CAP                                         */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC1_CAP_SHFT          28
+#define SH_XNNI0_DEAD_FLOW_VC1_CAP_MASK          0x00000000f0000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC2_LIMIT                                       */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_SHFT        32
+#define SH_XNNI0_DEAD_FLOW_VC2_LIMIT_MASK        0x0000000f00000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC2_DYN                                         */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC2_DYN_SHFT          40
+#define SH_XNNI0_DEAD_FLOW_VC2_DYN_MASK          0x00000f0000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC2_CAP                                         */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC2_CAP_SHFT          44
+#define SH_XNNI0_DEAD_FLOW_VC2_CAP_MASK          0x0000f00000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC3_LIMIT                                       */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_SHFT        48
+#define SH_XNNI0_DEAD_FLOW_VC3_LIMIT_MASK        0x000f000000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC3_DYN                                         */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI0_DEAD_FLOW_VC3_DYN_SHFT          56
+#define SH_XNNI0_DEAD_FLOW_VC3_DYN_MASK          0x0f00000000000000
+
+/*   SH_XNNI0_DEAD_FLOW_VC3_CAP                                         */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI0_DEAD_FLOW_VC3_CAP_SHFT          60
+#define SH_XNNI0_DEAD_FLOW_VC3_CAP_MASK          0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#define SH_XNNI0_INJECT_AGE                      0x0000000150030400
+#define SH_XNNI0_INJECT_AGE_MASK                 0x000000000000ffff
+#define SH_XNNI0_INJECT_AGE_INIT                 0x0000000000000000
+
+/*   SH_XNNI0_INJECT_AGE_REQUEST_INJECT                                 */
+/*   Description:  Value of AGE field for outgoing requests             */
+#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_SHFT  0
+#define SH_XNNI0_INJECT_AGE_REQUEST_INJECT_MASK  0x00000000000000ff
+
+/*   SH_XNNI0_INJECT_AGE_REPLY_INJECT                                   */
+/*   Description:  Value of AGE field for outgoing replies              */
+#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_SHFT    8
+#define SH_XNNI0_INJECT_AGE_REPLY_INJECT_MASK    0x000000000000ff00
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT          0x0000000150030500
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT          0x0000000150030510
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_MASK     0x7f7f007f7f00bfbf
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_INIT     0x0000000000000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD                       */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                     */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD                       */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                     */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN                            */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP                            */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN                            */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP                            */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT        0x0000000150030520
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_MASK   0x7f7f007f7f00bfbf
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_INIT   0x0000000000000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD                     */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED                   */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD                     */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_SHFT 8
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x0000000000003f00
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED                   */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 15
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000008000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN                          */
+/*   Description:  vc0 debit dynamic value                              */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_SHFT 24
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_DYN_MASK 0x000000007f000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP                          */
+/*   Description:  vc0 debit captured value                             */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_SHFT 32
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC0_CAP_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN                          */
+/*   Description:  vc2 debit dynamic value                              */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_SHFT 48
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_DYN_MASK 0x007f000000000000
+
+/*   SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP                          */
+/*   Description:  vc2 debit captured value                             */
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_SHFT 56
+#define SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT_VC2_CAP_MASK 0x7f00000000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT         0x0000000150030530
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT         0x0000000150030540
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_MASK    0x00007f7f7f7f7f7f
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_INIT    0x000000000c00000c
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST                          */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN                           */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP                           */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST                          */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN                           */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP                           */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*            Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT       0x0000000150030550
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_MASK  0x00007f7f7f7f7f7f
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_INIT  0x000000000c00000c
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST                        */
+/*   Description:  vc0 credit_test                                      */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_SHFT 0
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_TEST_MASK 0x000000000000007f
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN                         */
+/*   Description:  vc0 credit dynamic value                             */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_SHFT 8
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_DYN_MASK 0x0000000000007f00
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP                         */
+/*   Description:  vc0 credit captured value                            */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_SHFT 16
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC0_CAP_MASK 0x00000000007f0000
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST                        */
+/*   Description:  vc2 credit_test                                      */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_SHFT 24
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_TEST_MASK 0x000000007f000000
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN                         */
+/*   Description:  vc2 credit dynamic value                             */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_SHFT 32
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_DYN_MASK 0x0000007f00000000
+
+/*   SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP                         */
+/*   Description:  vc2 credit captured value                            */
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_SHFT 40
+#define SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT_VC2_CAP_MASK 0x00007f0000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_0_INTRANI_FLOW                  0x0000000150030560
+#define SH_XNNI1_0_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_0_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD                         */
+/*   Description:  vc0 withhold                                         */
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_SHFT 0
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED                       */
+/*   Description:  Force Credit on VC0 from debit cntr                  */
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_SHFT 7
+#define SH_XNNI1_0_INTRANI_FLOW_DEBIT_VC0_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_1_INTRANI_FLOW                  0x0000000150030570
+#define SH_XNNI1_1_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_1_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD                         */
+/*   Description:  vc1 withhold                                         */
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_SHFT 0
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED                       */
+/*   Description:  Force Credit on VC1 from debit cntr                  */
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_SHFT 7
+#define SH_XNNI1_1_INTRANI_FLOW_DEBIT_VC1_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_2_INTRANI_FLOW                  0x0000000150030580
+#define SH_XNNI1_2_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_2_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD                         */
+/*   Description:  vc2 withhold                                         */
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_SHFT 0
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED                       */
+/*   Description:  Force Credit on VC2 from debit cntr                  */
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_SHFT 7
+#define SH_XNNI1_2_INTRANI_FLOW_DEBIT_VC2_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNNI1_3_INTRANI_FLOW                  0x0000000150030590
+#define SH_XNNI1_3_INTRANI_FLOW_MASK             0x00000000000000bf
+#define SH_XNNI1_3_INTRANI_FLOW_INIT             0x0000000000000000
+
+/*   SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD                         */
+/*   Description:  vc3 withhold                                         */
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_SHFT 0
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_WITHHOLD_MASK 0x000000000000003f
+
+/*   SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED                       */
+/*   Description:  Force Credit on VC3 from debit cntr                  */
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_SHFT 7
+#define SH_XNNI1_3_INTRANI_FLOW_DEBIT_VC3_FORCE_CRED_MASK 0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNNI1_VCSWITCH_FLOW                   0x00000001500305a0
+#define SH_XNNI1_VCSWITCH_FLOW_MASK              0x0000000701010101
+#define SH_XNNI1_VCSWITCH_FLOW_INIT              0x0000000000000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH                   */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_SHFT 0
+#define SH_XNNI1_VCSWITCH_FLOW_NI_VCFIFO_DATELINE_SWITCH_MASK 0x0000000000000001
+
+/*   SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_SHFT 8
+#define SH_XNNI1_VCSWITCH_FLOW_PI_VCFIFO_SWITCH_MASK 0x0000000000000100
+
+/*   SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH                            */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_SHFT 16
+#define SH_XNNI1_VCSWITCH_FLOW_MD_VCFIFO_SWITCH_MASK 0x0000000000010000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH                          */
+/*   Description:  Swap VC0/2 with VC1/3                                */
+#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_SHFT 24
+#define SH_XNNI1_VCSWITCH_FLOW_IILB_VCFIFO_SWITCH_MASK 0x0000000001000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN                      */
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_SHFT 32
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_IN_MASK 0x0000000100000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT                     */
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_SHFT 33
+#define SH_XNNI1_VCSWITCH_FLOW_DISABLE_SYNC_BYPASS_OUT_MASK 0x0000000200000000
+
+/*   SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES                                */
+#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_SHFT 34
+#define SH_XNNI1_VCSWITCH_FLOW_ASYNC_FIFOES_MASK 0x0000000400000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_TIMER_REG"                     */
+/* ==================================================================== */
+
+#define SH_XNNI1_TIMER_REG                       0x00000001500305b0
+#define SH_XNNI1_TIMER_REG_MASK                  0x0000000100ffffff
+#define SH_XNNI1_TIMER_REG_INIT                  0x0000000000ffffff
+
+/*   SH_XNNI1_TIMER_REG_TIMEOUT_REG                                     */
+/*   Description:  Master Timeout Counter                               */
+#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_SHFT      0
+#define SH_XNNI1_TIMER_REG_TIMEOUT_REG_MASK      0x0000000000ffffff
+
+/*   SH_XNNI1_TIMER_REG_LINKCLEANUP_REG                                 */
+/*   Description:  Link Clean Up                                        */
+#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_SHFT  32
+#define SH_XNNI1_TIMER_REG_LINKCLEANUP_REG_MASK  0x0000000100000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_FIFO02_FLOW                     0x00000001500305c0
+#define SH_XNNI1_FIFO02_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI1_FIFO02_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_SHFT 0
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_SHFT  8
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_SHFT  16
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC0_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_SHFT 24
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_SHFT  32
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_SHFT  40
+#define SH_XNNI1_FIFO02_FLOW_COUNT_VC2_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_FIFO13_FLOW                     0x00000001500305d0
+#define SH_XNNI1_FIFO13_FLOW_MASK                0x00000f0f0f0f0f0f
+#define SH_XNNI1_FIFO13_FLOW_INIT                0x0000000000000000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_SHFT 0
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_LIMIT_MASK 0x000000000000000f
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN                                 */
+/*   Description:  dynamic counter value                                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_SHFT  8
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_DYN_MASK  0x0000000000000f00
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_SHFT  16
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC1_CAP_MASK  0x00000000000f0000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT                               */
+/*   Description:  limit reg zero disables functionality                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_SHFT 24
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_LIMIT_MASK 0x000000000f000000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN                                 */
+/*   Description:  counter dynamic value                                */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_SHFT  32
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_DYN_MASK  0x0000000f00000000
+
+/*   SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP                                 */
+/*   Description:  captured counter value                               */
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_SHFT  40
+#define SH_XNNI1_FIFO13_FLOW_COUNT_VC3_CAP_MASK  0x00000f0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI1_NI_FLOW"                      */
+/* ==================================================================== */
+
+#define SH_XNNI1_NI_FLOW                         0x00000001500305e0
+#define SH_XNNI1_NI_FLOW_MASK                    0xff0fff0fff0fff0f
+#define SH_XNNI1_NI_FLOW_INIT                    0x0000000000000000
+
+/*   SH_XNNI1_NI_FLOW_VC0_LIMIT                                         */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC0_LIMIT_SHFT          0
+#define SH_XNNI1_NI_FLOW_VC0_LIMIT_MASK          0x000000000000000f
+
+/*   SH_XNNI1_NI_FLOW_VC0_DYN                                           */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC0_DYN_SHFT            8
+#define SH_XNNI1_NI_FLOW_VC0_DYN_MASK            0x0000000000000f00
+
+/*   SH_XNNI1_NI_FLOW_VC0_CAP                                           */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC0_CAP_SHFT            12
+#define SH_XNNI1_NI_FLOW_VC0_CAP_MASK            0x000000000000f000
+
+/*   SH_XNNI1_NI_FLOW_VC1_LIMIT                                         */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC1_LIMIT_SHFT          16
+#define SH_XNNI1_NI_FLOW_VC1_LIMIT_MASK          0x00000000000f0000
+
+/*   SH_XNNI1_NI_FLOW_VC1_DYN                                           */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC1_DYN_SHFT            24
+#define SH_XNNI1_NI_FLOW_VC1_DYN_MASK            0x000000000f000000
+
+/*   SH_XNNI1_NI_FLOW_VC1_CAP                                           */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC1_CAP_SHFT            28
+#define SH_XNNI1_NI_FLOW_VC1_CAP_MASK            0x00000000f0000000
+
+/*   SH_XNNI1_NI_FLOW_VC2_LIMIT                                         */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC2_LIMIT_SHFT          32
+#define SH_XNNI1_NI_FLOW_VC2_LIMIT_MASK          0x0000000f00000000
+
+/*   SH_XNNI1_NI_FLOW_VC2_DYN                                           */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC2_DYN_SHFT            40
+#define SH_XNNI1_NI_FLOW_VC2_DYN_MASK            0x00000f0000000000
+
+/*   SH_XNNI1_NI_FLOW_VC2_CAP                                           */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC2_CAP_SHFT            44
+#define SH_XNNI1_NI_FLOW_VC2_CAP_MASK            0x0000f00000000000
+
+/*   SH_XNNI1_NI_FLOW_VC3_LIMIT                                         */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI1_NI_FLOW_VC3_LIMIT_SHFT          48
+#define SH_XNNI1_NI_FLOW_VC3_LIMIT_MASK          0x000f000000000000
+
+/*   SH_XNNI1_NI_FLOW_VC3_DYN                                           */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI1_NI_FLOW_VC3_DYN_SHFT            56
+#define SH_XNNI1_NI_FLOW_VC3_DYN_MASK            0x0f00000000000000
+
+/*   SH_XNNI1_NI_FLOW_VC3_CAP                                           */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI1_NI_FLOW_VC3_CAP_SHFT            60
+#define SH_XNNI1_NI_FLOW_VC3_CAP_MASK            0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#define SH_XNNI1_DEAD_FLOW                       0x00000001500305f0
+#define SH_XNNI1_DEAD_FLOW_MASK                  0xff0fff0fff0fff0f
+#define SH_XNNI1_DEAD_FLOW_INIT                  0x0000000000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC0_LIMIT                                       */
+/*   Description:  vc0 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_SHFT        0
+#define SH_XNNI1_DEAD_FLOW_VC0_LIMIT_MASK        0x000000000000000f
+
+/*   SH_XNNI1_DEAD_FLOW_VC0_DYN                                         */
+/*   Description:  vc0 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC0_DYN_SHFT          8
+#define SH_XNNI1_DEAD_FLOW_VC0_DYN_MASK          0x0000000000000f00
+
+/*   SH_XNNI1_DEAD_FLOW_VC0_CAP                                         */
+/*   Description:  vc0 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC0_CAP_SHFT          12
+#define SH_XNNI1_DEAD_FLOW_VC0_CAP_MASK          0x000000000000f000
+
+/*   SH_XNNI1_DEAD_FLOW_VC1_LIMIT                                       */
+/*   Description:  vc1 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_SHFT        16
+#define SH_XNNI1_DEAD_FLOW_VC1_LIMIT_MASK        0x00000000000f0000
+
+/*   SH_XNNI1_DEAD_FLOW_VC1_DYN                                         */
+/*   Description:  vc1 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC1_DYN_SHFT          24
+#define SH_XNNI1_DEAD_FLOW_VC1_DYN_MASK          0x000000000f000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC1_CAP                                         */
+/*   Description:  vc1 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC1_CAP_SHFT          28
+#define SH_XNNI1_DEAD_FLOW_VC1_CAP_MASK          0x00000000f0000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC2_LIMIT                                       */
+/*   Description:  vc2 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_SHFT        32
+#define SH_XNNI1_DEAD_FLOW_VC2_LIMIT_MASK        0x0000000f00000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC2_DYN                                         */
+/*   Description:  vc2 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC2_DYN_SHFT          40
+#define SH_XNNI1_DEAD_FLOW_VC2_DYN_MASK          0x00000f0000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC2_CAP                                         */
+/*   Description:  vc2 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC2_CAP_SHFT          44
+#define SH_XNNI1_DEAD_FLOW_VC2_CAP_MASK          0x0000f00000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC3_LIMIT                                       */
+/*   Description:  vc3 limit reg, zero disables functionality           */
+#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_SHFT        48
+#define SH_XNNI1_DEAD_FLOW_VC3_LIMIT_MASK        0x000f000000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC3_DYN                                         */
+/*   Description:  vc3 counter dynamic value                            */
+#define SH_XNNI1_DEAD_FLOW_VC3_DYN_SHFT          56
+#define SH_XNNI1_DEAD_FLOW_VC3_DYN_MASK          0x0f00000000000000
+
+/*   SH_XNNI1_DEAD_FLOW_VC3_CAP                                         */
+/*   Description:  vc3 counter captured value                           */
+#define SH_XNNI1_DEAD_FLOW_VC3_CAP_SHFT          60
+#define SH_XNNI1_DEAD_FLOW_VC3_CAP_MASK          0xf000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#define SH_XNNI1_INJECT_AGE                      0x0000000150030600
+#define SH_XNNI1_INJECT_AGE_MASK                 0x000000000000ffff
+#define SH_XNNI1_INJECT_AGE_INIT                 0x0000000000000000
+
+/*   SH_XNNI1_INJECT_AGE_REQUEST_INJECT                                 */
+/*   Description:  Value of AGE field for outgoing requests             */
+#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_SHFT  0
+#define SH_XNNI1_INJECT_AGE_REQUEST_INJECT_MASK  0x00000000000000ff
+
+/*   SH_XNNI1_INJECT_AGE_REPLY_INJECT                                   */
+/*   Description:  Value of AGE field for outgoing replies              */
+#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_SHFT    8
+#define SH_XNNI1_INJECT_AGE_REPLY_INJECT_MASK    0x000000000000ff00
+
+/* ==================================================================== */
+/*                      Register "SH_XN_DEBUG_SEL"                      */
+/*                         XN Debug Port Select                         */
+/* ==================================================================== */
+
+#define SH_XN_DEBUG_SEL                          0x0000000150031000
+#define SH_XN_DEBUG_SEL_MASK                     0xf777777777777777
+#define SH_XN_DEBUG_SEL_INIT                     0x0000000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL                                    */
+/*   Description:  Nibble 0 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_SHFT     0
+#define SH_XN_DEBUG_SEL_NIBBLE0_RLM_SEL_MASK     0x0000000000000007
+
+/*   SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                                 */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT  4
+#define SH_XN_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK  0x0000000000000070
+
+/*   SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL                                    */
+/*   Description:  Nibble 1 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_SHFT     8
+#define SH_XN_DEBUG_SEL_NIBBLE1_RLM_SEL_MASK     0x0000000000000700
+
+/*   SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                                 */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT  12
+#define SH_XN_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK  0x0000000000007000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL                                    */
+/*   Description:  Nibble 2 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_SHFT     16
+#define SH_XN_DEBUG_SEL_NIBBLE2_RLM_SEL_MASK     0x0000000000070000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                                 */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT  20
+#define SH_XN_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK  0x0000000000700000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL                                    */
+/*   Description:  Nibble 3 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_SHFT     24
+#define SH_XN_DEBUG_SEL_NIBBLE3_RLM_SEL_MASK     0x0000000007000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                                 */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT  28
+#define SH_XN_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK  0x0000000070000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL                                    */
+/*   Description:  Nibble 4 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_SHFT     32
+#define SH_XN_DEBUG_SEL_NIBBLE4_RLM_SEL_MASK     0x0000000700000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                                 */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT  36
+#define SH_XN_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK  0x0000007000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL                                    */
+/*   Description:  Nibble 5 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_SHFT     40
+#define SH_XN_DEBUG_SEL_NIBBLE5_RLM_SEL_MASK     0x0000070000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                                 */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT  44
+#define SH_XN_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK  0x0000700000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL                                    */
+/*   Description:  Nibble 6 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_SHFT     48
+#define SH_XN_DEBUG_SEL_NIBBLE6_RLM_SEL_MASK     0x0007000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                                 */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT  52
+#define SH_XN_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK  0x0070000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL                                    */
+/*   Description:  Nibble 7 RLM select                                  */
+#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_SHFT     56
+#define SH_XN_DEBUG_SEL_NIBBLE7_RLM_SEL_MASK     0x0700000000000000
+
+/*   SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                                 */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT  60
+#define SH_XN_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK  0x7000000000000000
+
+/*   SH_XN_DEBUG_SEL_TRIGGER_ENABLE                                     */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_SHFT      63
+#define SH_XN_DEBUG_SEL_TRIGGER_ENABLE_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XN_DEBUG_TRIG_SEL"                    */
+/*                       XN Debug trigger Select                        */
+/* ==================================================================== */
+
+#define SH_XN_DEBUG_TRIG_SEL                     0x0000000150031020
+#define SH_XN_DEBUG_TRIG_SEL_MASK                0x7777777777777777
+#define SH_XN_DEBUG_TRIG_SEL_INIT                0x0000000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL                              */
+/*   Description:  Nibble 0 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_SHFT 0
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_RLM_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL                           */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_SHFT 4
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL                              */
+/*   Description:  Nibble 1 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_SHFT 8
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_RLM_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL                           */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_SHFT 12
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL                              */
+/*   Description:  Nibble 2 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_SHFT 16
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_RLM_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL                           */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_SHFT 20
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL                              */
+/*   Description:  Nibble 3 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_SHFT 24
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_RLM_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL                           */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_SHFT 28
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL                              */
+/*   Description:  Nibble 4 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_SHFT 32
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_RLM_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL                           */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_SHFT 36
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL                              */
+/*   Description:  Nibble 5 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_SHFT 40
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_RLM_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL                           */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_SHFT 44
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL                              */
+/*   Description:  Nibble 6 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_SHFT 48
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_RLM_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL                           */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_SHFT 52
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL                              */
+/*   Description:  Nibble 7 RLM select                                  */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_SHFT 56
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_RLM_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL                           */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_SHFT 60
+#define SH_XN_DEBUG_TRIG_SEL_TRIGGER7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XN_TRIGGER_COMPARE"                   */
+/*                           XN Debug Compare                           */
+/* ==================================================================== */
+
+#define SH_XN_TRIGGER_COMPARE                    0x0000000150031040
+#define SH_XN_TRIGGER_COMPARE_MASK               0x00000000ffffffff
+#define SH_XN_TRIGGER_COMPARE_INIT               0x0000000000000000
+
+/*   SH_XN_TRIGGER_COMPARE_MASK                                         */
+/*   Description:  Mask to select Debug bits for trigger generation     */
+#define SH_XN_TRIGGER_COMPARE_MASK_SHFT          0
+#define SH_XN_TRIGGER_COMPARE_MASK_MASK          0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_XN_TRIGGER_DATA"                     */
+/*                        XN Debug Compare Data                         */
+/* ==================================================================== */
+
+#define SH_XN_TRIGGER_DATA                       0x0000000150031050
+#define SH_XN_TRIGGER_DATA_MASK                  0x00000000ffffffff
+#define SH_XN_TRIGGER_DATA_INIT                  0x00000000ffffffff
+
+/*   SH_XN_TRIGGER_DATA_COMPARE_PATTERN                                 */
+/*   Description:  debug bit pattern for trigger generation             */
+#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_SHFT  0
+#define SH_XN_TRIGGER_DATA_COMPARE_PATTERN_MASK  0x00000000ffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_XN_IILB_DEBUG_SEL"                    */
+/*                      XN IILB Debug Port Select                       */
+/* ==================================================================== */
+
+#define SH_XN_IILB_DEBUG_SEL                     0x0000000150031060
+#define SH_XN_IILB_DEBUG_SEL_MASK                0x7777777777777777
+#define SH_XN_IILB_DEBUG_SEL_INIT                0x0000000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL                             */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                            */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL                             */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                            */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL                             */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                            */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL                             */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                            */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL                             */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                            */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL                             */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                            */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL                             */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                            */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL                             */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                            */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_IILB_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_PI_DEBUG_SEL"                     */
+/*                       XN PI Debug Port Select                        */
+/* ==================================================================== */
+
+#define SH_XN_PI_DEBUG_SEL                       0x00000001500310a0
+#define SH_XN_PI_DEBUG_SEL_MASK                  0x7777777777777777
+#define SH_XN_PI_DEBUG_SEL_INIT                  0x0000000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL                               */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                              */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_PI_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL                               */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                              */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_PI_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL                               */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                              */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_PI_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL                               */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                              */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_PI_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL                               */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                              */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_PI_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL                               */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                              */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_PI_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL                               */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                              */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_PI_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL                               */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                              */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_PI_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_DEBUG_SEL"                     */
+/*                       XN MD Debug Port Select                        */
+/* ==================================================================== */
+
+#define SH_XN_MD_DEBUG_SEL                       0x0000000150031080
+#define SH_XN_MD_DEBUG_SEL_MASK                  0x7777777777777777
+#define SH_XN_MD_DEBUG_SEL_INIT                  0x0000000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL                               */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                              */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_MD_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL                               */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                              */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_MD_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL                               */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                              */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_MD_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL                               */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                              */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_MD_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL                               */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                              */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_MD_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL                               */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                              */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_MD_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL                               */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                              */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_MD_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL                               */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                              */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_MD_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI0_DEBUG_SEL"                    */
+/*                       XN NI0 Debug Port Select                       */
+/* ==================================================================== */
+
+#define SH_XN_NI0_DEBUG_SEL                      0x00000001500310c0
+#define SH_XN_NI0_DEBUG_SEL_MASK                 0x7777777777777777
+#define SH_XN_NI0_DEBUG_SEL_INIT                 0x0000000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL                              */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                             */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL                              */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                             */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL                              */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                             */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL                              */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                             */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL                              */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                             */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL                              */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                             */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL                              */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                             */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL                              */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                             */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_NI0_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI1_DEBUG_SEL"                    */
+/*                       XN NI1 Debug Port Select                       */
+/* ==================================================================== */
+
+#define SH_XN_NI1_DEBUG_SEL                      0x00000001500310e0
+#define SH_XN_NI1_DEBUG_SEL_MASK                 0x7777777777777777
+#define SH_XN_NI1_DEBUG_SEL_INIT                 0x0000000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL                              */
+/*   Description:  Nibble 0 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_SHFT 0
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_INPUT_SEL_MASK 0x0000000000000007
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL                             */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_SHFT 4
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE0_NIBBLE_SEL_MASK 0x0000000000000070
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL                              */
+/*   Description:  Nibble 1 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_SHFT 8
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_INPUT_SEL_MASK 0x0000000000000700
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL                             */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_SHFT 12
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE1_NIBBLE_SEL_MASK 0x0000000000007000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL                              */
+/*   Description:  Nibble 2 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_SHFT 16
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_INPUT_SEL_MASK 0x0000000000070000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL                             */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_SHFT 20
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE2_NIBBLE_SEL_MASK 0x0000000000700000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL                              */
+/*   Description:  Nibble 3 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_SHFT 24
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_INPUT_SEL_MASK 0x0000000007000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL                             */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_SHFT 28
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE3_NIBBLE_SEL_MASK 0x0000000070000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL                              */
+/*   Description:  Nibble 4 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_SHFT 32
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_INPUT_SEL_MASK 0x0000000700000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL                             */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_SHFT 36
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE4_NIBBLE_SEL_MASK 0x0000007000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL                              */
+/*   Description:  Nibble 5 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_SHFT 40
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_INPUT_SEL_MASK 0x0000070000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL                             */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_SHFT 44
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE5_NIBBLE_SEL_MASK 0x0000700000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL                              */
+/*   Description:  Nibble 6 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_SHFT 48
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_INPUT_SEL_MASK 0x0007000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL                             */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_SHFT 52
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE6_NIBBLE_SEL_MASK 0x0070000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL                              */
+/*   Description:  Nibble 7 input select                                */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_SHFT 56
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_INPUT_SEL_MASK 0x0700000000000000
+
+/*   SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL                             */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_SHFT 60
+#define SH_XN_NI1_DEBUG_SEL_NIBBLE7_NIBBLE_SEL_MASK 0x7000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA0"                */
+/*                 IILB compare LB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_EXP_DATA0              0x0000000150031100
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_LB_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA1"                */
+/*                 IILB compare LB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_EXP_DATA1              0x0000000150031110
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_LB_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE0"                 */
+/*                    IILB compare LB input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_ENABLE0                0x0000000150031120
+#define SH_XN_IILB_LB_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_LB_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE1"                 */
+/*                    IILB compare LB input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_LB_CMP_ENABLE1                0x0000000150031130
+#define SH_XN_IILB_LB_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_LB_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_LB_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_LB_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA0"                */
+/*                 IILB compare II input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_EXP_DATA0              0x0000000150031140
+#define SH_XN_IILB_II_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_II_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA1"                */
+/*                 IILB compare II input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_EXP_DATA1              0x0000000150031150
+#define SH_XN_IILB_II_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_II_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE0"                 */
+/*                    IILB compare II input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_ENABLE0                0x0000000150031160
+#define SH_XN_IILB_II_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_II_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE1"                 */
+/*                    IILB compare II input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_II_CMP_ENABLE1                0x0000000150031170
+#define SH_XN_IILB_II_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_II_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_II_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_II_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA0"                */
+/*                 IILB compare MD input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_EXP_DATA0              0x0000000150031180
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_MD_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA1"                */
+/*                 IILB compare MD input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_EXP_DATA1              0x0000000150031190
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_MD_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE0"                 */
+/*                    IILB compare MD input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_ENABLE0                0x00000001500311a0
+#define SH_XN_IILB_MD_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_MD_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE1"                 */
+/*                    IILB compare MD input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_MD_CMP_ENABLE1                0x00000001500311b0
+#define SH_XN_IILB_MD_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_MD_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_MD_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_MD_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA0"                */
+/*                 IILB compare PI input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_EXP_DATA0              0x00000001500311c0
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_IILB_PI_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA1"                */
+/*                 IILB compare PI input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_EXP_DATA1              0x00000001500311d0
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_IILB_PI_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE0"                 */
+/*                    IILB compare PI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_ENABLE0                0x00000001500311e0
+#define SH_XN_IILB_PI_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_IILB_PI_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE1"                 */
+/*                    IILB compare PI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_IILB_PI_CMP_ENABLE1                0x00000001500311f0
+#define SH_XN_IILB_PI_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_IILB_PI_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_IILB_PI_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_IILB_PI_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA0"                */
+/*                IILB compare NI0 input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0             0x0000000150031200
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_IILB_NI0_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA1"                */
+/*                IILB compare NI0 input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1             0x0000000150031210
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_IILB_NI0_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE0"                 */
+/*                    IILB compare NI0 input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_ENABLE0               0x0000000150031220
+#define SH_XN_IILB_NI0_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_IILB_NI0_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE1"                 */
+/*                    IILB compare NI0 input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI0_CMP_ENABLE1               0x0000000150031230
+#define SH_XN_IILB_NI0_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI0_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_IILB_NI0_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA0"                */
+/*                IILB compare NI1 input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0             0x0000000150031240
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_IILB_NI1_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA1"                */
+/*                IILB compare NI1 input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1             0x0000000150031250
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_IILB_NI1_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE0"                 */
+/*                    IILB compare NI1 input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_ENABLE0               0x0000000150031260
+#define SH_XN_IILB_NI1_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_IILB_NI1_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE1"                 */
+/*                    IILB compare NI1 input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_IILB_NI1_CMP_ENABLE1               0x0000000150031270
+#define SH_XN_IILB_NI1_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_IILB_NI1_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_IILB_NI1_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA0"                */
+/*                 MD compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_EXP_DATA0              0x0000000150031500
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_MD_IILB_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA1"                */
+/*                 MD compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_EXP_DATA1              0x0000000150031510
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_MD_IILB_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE0"                 */
+/*                    MD compare IILB input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_ENABLE0                0x0000000150031520
+#define SH_XN_MD_IILB_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_MD_IILB_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE1"                 */
+/*                    MD compare IILB input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_IILB_CMP_ENABLE1                0x0000000150031530
+#define SH_XN_MD_IILB_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_MD_IILB_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_MD_IILB_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_MD_IILB_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA0"                 */
+/*                 MD compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_EXP_DATA0               0x0000000150031540
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_MD_NI0_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA1"                 */
+/*                 MD compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_EXP_DATA1               0x0000000150031550
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_MD_NI0_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE0"                  */
+/*                     MD compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_ENABLE0                 0x0000000150031560
+#define SH_XN_MD_NI0_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_MD_NI0_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE1"                  */
+/*                     MD compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI0_CMP_ENABLE1                 0x0000000150031570
+#define SH_XN_MD_NI0_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI0_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI0_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_MD_NI0_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA0"                 */
+/*                 MD compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_EXP_DATA0               0x0000000150031580
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_MD_NI1_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA1"                 */
+/*                 MD compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_EXP_DATA1               0x0000000150031590
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_MD_NI1_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE0"                  */
+/*                     MD compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_ENABLE0                 0x00000001500315a0
+#define SH_XN_MD_NI1_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_MD_NI1_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE1"                  */
+/*                     MD compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_NI1_CMP_ENABLE1                 0x00000001500315b0
+#define SH_XN_MD_NI1_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_MD_NI1_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_MD_NI1_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_MD_NI1_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR0"                 */
+/*                MD compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_EXP_HDR0                0x00000001500315c0
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_MASK           0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_INIT           0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_EXP_HDR0_DATA                                     */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_SHFT      0
+#define SH_XN_MD_SIC_CMP_EXP_HDR0_DATA_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR1"                 */
+/*                MD compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_EXP_HDR1                0x00000001500315d0
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_MASK           0x000003ffffffffff
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_INIT           0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_EXP_HDR1_DATA                                     */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_SHFT      0
+#define SH_XN_MD_SIC_CMP_EXP_HDR1_DATA_MASK      0x000003ffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0"                */
+/*                    MD compare SIC header enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0             0x00000001500315e0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_MASK        0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_INIT        0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE                                */
+/*   Description:  Enable0                                              */
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1"                */
+/*                    MD compare SIC header enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1             0x00000001500315f0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_MASK        0x000003ffffffffff
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_INIT        0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE                                */
+/*   Description:  Enable1                                              */
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0
+#define SH_XN_MD_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA0"                   */
+/*                         MD compare SIC data0                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA0                   0x0000000150031600
+#define SH_XN_MD_SIC_CMP_DATA0_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA0_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA0_DATA0                                       */
+/*   Description:  Data0                                                */
+#define SH_XN_MD_SIC_CMP_DATA0_DATA0_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA0_DATA0_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA1"                   */
+/*                         MD compare SIC data1                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA1                   0x0000000150031610
+#define SH_XN_MD_SIC_CMP_DATA1_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA1_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA1_DATA1                                       */
+/*   Description:  Data1                                                */
+#define SH_XN_MD_SIC_CMP_DATA1_DATA1_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA1_DATA1_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA2"                   */
+/*                         MD compare SIC data2                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA2                   0x0000000150031620
+#define SH_XN_MD_SIC_CMP_DATA2_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA2_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA2_DATA2                                       */
+/*   Description:  Data2                                                */
+#define SH_XN_MD_SIC_CMP_DATA2_DATA2_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA2_DATA2_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA3"                   */
+/*                         MD compare SIC data3                         */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA3                   0x0000000150031630
+#define SH_XN_MD_SIC_CMP_DATA3_MASK              0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA3_INIT              0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA3_DATA3                                       */
+/*   Description:  Data3                                                */
+#define SH_XN_MD_SIC_CMP_DATA3_DATA3_SHFT        0
+#define SH_XN_MD_SIC_CMP_DATA3_DATA3_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0"               */
+/*                     MD enable compare SIC data0                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0            0x0000000150031640
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0                         */
+/*   Description:  Data0                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1"               */
+/*                     MD enable compare SIC data1                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1            0x0000000150031650
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1                         */
+/*   Description:  Data1                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2"               */
+/*                     MD enable compare SIC data2                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2            0x0000000150031660
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2                         */
+/*   Description:  Data2                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3"               */
+/*                     MD enable compare SIC data3                      */
+/* ==================================================================== */
+
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3            0x0000000150031670
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_MASK       0xffffffffffffffff
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_INIT       0x0000000000000000
+
+/*   SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3                         */
+/*   Description:  Data3                                                */
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0
+#define SH_XN_MD_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA0"                */
+/*                 PI compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_EXP_DATA0              0x0000000150031300
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_PI_IILB_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA1"                */
+/*                 PI compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_EXP_DATA1              0x0000000150031310
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_PI_IILB_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE0"                 */
+/*                    PI compare IILB input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_ENABLE0                0x0000000150031320
+#define SH_XN_PI_IILB_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_PI_IILB_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE1"                 */
+/*                    PI compare IILB input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_IILB_CMP_ENABLE1                0x0000000150031330
+#define SH_XN_PI_IILB_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_PI_IILB_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_PI_IILB_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_PI_IILB_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA0"                 */
+/*                 PI compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_EXP_DATA0               0x0000000150031340
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_PI_NI0_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA1"                 */
+/*                 PI compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_EXP_DATA1               0x0000000150031350
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_PI_NI0_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE0"                  */
+/*                     PI compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_ENABLE0                 0x0000000150031360
+#define SH_XN_PI_NI0_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_PI_NI0_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE1"                  */
+/*                     PI compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI0_CMP_ENABLE1                 0x0000000150031370
+#define SH_XN_PI_NI0_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI0_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI0_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_PI_NI0_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA0"                 */
+/*                 PI compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_EXP_DATA0               0x0000000150031380
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_PI_NI1_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA1"                 */
+/*                 PI compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_EXP_DATA1               0x0000000150031390
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_PI_NI1_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE0"                  */
+/*                     PI compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_ENABLE0                 0x00000001500313a0
+#define SH_XN_PI_NI1_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_PI_NI1_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE1"                  */
+/*                     PI compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_NI1_CMP_ENABLE1                 0x00000001500313b0
+#define SH_XN_PI_NI1_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_PI_NI1_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_PI_NI1_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_PI_NI1_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR0"                 */
+/*                PI compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_EXP_HDR0                0x00000001500313c0
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_MASK           0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_INIT           0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_EXP_HDR0_DATA                                     */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_SHFT      0
+#define SH_XN_PI_SIC_CMP_EXP_HDR0_DATA_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR1"                 */
+/*                PI compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_EXP_HDR1                0x00000001500313d0
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_MASK           0x000003ffffffffff
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_INIT           0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_EXP_HDR1_DATA                                     */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_SHFT      0
+#define SH_XN_PI_SIC_CMP_EXP_HDR1_DATA_MASK      0x000003ffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0"                */
+/*                    PI compare SIC header enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0             0x00000001500313e0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_MASK        0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_INIT        0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE                                */
+/*   Description:  Enable0                                              */
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_SHFT 0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE0_ENABLE_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1"                */
+/*                    PI compare SIC header enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1             0x00000001500313f0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_MASK        0x000003ffffffffff
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_INIT        0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE                                */
+/*   Description:  Enable1                                              */
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_SHFT 0
+#define SH_XN_PI_SIC_CMP_HDR_ENABLE1_ENABLE_MASK 0x000003ffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA0"                   */
+/*                         PI compare SIC data0                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA0                   0x0000000150031400
+#define SH_XN_PI_SIC_CMP_DATA0_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA0_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA0_DATA0                                       */
+/*   Description:  Data0                                                */
+#define SH_XN_PI_SIC_CMP_DATA0_DATA0_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA0_DATA0_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA1"                   */
+/*                         PI compare SIC data1                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA1                   0x0000000150031410
+#define SH_XN_PI_SIC_CMP_DATA1_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA1_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA1_DATA1                                       */
+/*   Description:  Data1                                                */
+#define SH_XN_PI_SIC_CMP_DATA1_DATA1_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA1_DATA1_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA2"                   */
+/*                         PI compare SIC data2                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA2                   0x0000000150031420
+#define SH_XN_PI_SIC_CMP_DATA2_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA2_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA2_DATA2                                       */
+/*   Description:  Data2                                                */
+#define SH_XN_PI_SIC_CMP_DATA2_DATA2_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA2_DATA2_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA3"                   */
+/*                         PI compare SIC data3                         */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA3                   0x0000000150031430
+#define SH_XN_PI_SIC_CMP_DATA3_MASK              0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA3_INIT              0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA3_DATA3                                       */
+/*   Description:  Data3                                                */
+#define SH_XN_PI_SIC_CMP_DATA3_DATA3_SHFT        0
+#define SH_XN_PI_SIC_CMP_DATA3_DATA3_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0"               */
+/*                     PI enable compare SIC data0                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0            0x0000000150031440
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0                         */
+/*   Description:  Data0                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE0_DATA_ENABLE0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1"               */
+/*                     PI enable compare SIC data1                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1            0x0000000150031450
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1                         */
+/*   Description:  Data1                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE1_DATA_ENABLE1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2"               */
+/*                     PI enable compare SIC data2                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2            0x0000000150031460
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2                         */
+/*   Description:  Data2                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE2_DATA_ENABLE2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3"               */
+/*                     PI enable compare SIC data3                      */
+/* ==================================================================== */
+
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3            0x0000000150031470
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_MASK       0xffffffffffffffff
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_INIT       0x0000000000000000
+
+/*   SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3                         */
+/*   Description:  Data3                                                */
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_SHFT 0
+#define SH_XN_PI_SIC_CMP_DATA_ENABLE3_DATA_ENABLE3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA0"                */
+/*                NI0 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0             0x0000000150031700
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_NI0_IILB_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA1"                */
+/*                NI0 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1             0x0000000150031710
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_NI0_IILB_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE0"                 */
+/*                    NI0 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_ENABLE0               0x0000000150031720
+#define SH_XN_NI0_IILB_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_NI0_IILB_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE1"                 */
+/*                    NI0 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_NI0_IILB_CMP_ENABLE1               0x0000000150031730
+#define SH_XN_NI0_IILB_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_IILB_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_NI0_IILB_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_EXP_DATA0               0x0000000150031740
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI0_PI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_EXP_DATA1               0x0000000150031750
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI0_PI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE0"                  */
+/*                     NI0 compare PI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_ENABLE0                 0x0000000150031760
+#define SH_XN_NI0_PI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI0_PI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE1"                  */
+/*                     NI0 compare PI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_PI_CMP_ENABLE1                 0x0000000150031770
+#define SH_XN_NI0_PI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI0_PI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_PI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI0_PI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA0"                 */
+/*                 NI0 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_EXP_DATA0               0x0000000150031780
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI0_MD_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA1"                 */
+/*                 NI0 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_EXP_DATA1               0x0000000150031790
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI0_MD_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE0"                  */
+/*                     NI0 compare MD input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_ENABLE0                 0x00000001500317a0
+#define SH_XN_NI0_MD_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI0_MD_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE1"                  */
+/*                     NI0 compare MD input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_MD_CMP_ENABLE1                 0x00000001500317b0
+#define SH_XN_NI0_MD_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI0_MD_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_MD_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI0_MD_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_EXP_DATA0               0x00000001500317c0
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI0_NI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_EXP_DATA1               0x00000001500317d0
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI0_NI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE0"                  */
+/*                     NI0 compare NI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_ENABLE0                 0x00000001500317e0
+#define SH_XN_NI0_NI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI0_NI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE1"                  */
+/*                     NI0 compare NI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_NI_CMP_ENABLE1                 0x00000001500317f0
+#define SH_XN_NI0_NI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI0_NI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI0_NI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI0_NI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA0"                */
+/*                 NI0 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0              0x0000000150031800
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_NI0_LLP_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA1"                */
+/*                 NI0 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1              0x0000000150031810
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_NI0_LLP_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE0"                 */
+/*                    NI0 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_ENABLE0                0x0000000150031820
+#define SH_XN_NI0_LLP_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_NI0_LLP_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE1"                 */
+/*                    NI0 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI0_LLP_CMP_ENABLE1                0x0000000150031830
+#define SH_XN_NI0_LLP_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_NI0_LLP_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_NI0_LLP_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA0"                */
+/*                NI1 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0             0x0000000150031900
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_MASK        0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_INIT        0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA                                  */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_SHFT   0
+#define SH_XN_NI1_IILB_CMP_EXP_DATA0_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA1"                */
+/*                NI1 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1             0x0000000150031910
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_MASK        0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_INIT        0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA                                  */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_SHFT   0
+#define SH_XN_NI1_IILB_CMP_EXP_DATA1_DATA_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE0"                 */
+/*                    NI1 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_ENABLE0               0x0000000150031920
+#define SH_XN_NI1_IILB_CMP_ENABLE0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_ENABLE0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE                                  */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_SHFT   0
+#define SH_XN_NI1_IILB_CMP_ENABLE0_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE1"                 */
+/*                    NI1 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#define SH_XN_NI1_IILB_CMP_ENABLE1               0x0000000150031930
+#define SH_XN_NI1_IILB_CMP_ENABLE1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_IILB_CMP_ENABLE1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE                                  */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_SHFT   0
+#define SH_XN_NI1_IILB_CMP_ENABLE1_ENABLE_MASK   0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_EXP_DATA0               0x0000000150031940
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI1_PI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_EXP_DATA1               0x0000000150031950
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI1_PI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE0"                  */
+/*                     NI1 compare PI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_ENABLE0                 0x0000000150031960
+#define SH_XN_NI1_PI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI1_PI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE1"                  */
+/*                     NI1 compare PI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_PI_CMP_ENABLE1                 0x0000000150031970
+#define SH_XN_NI1_PI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI1_PI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_PI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI1_PI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA0"                 */
+/*                 NI1 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_EXP_DATA0               0x0000000150031980
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI1_MD_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA1"                 */
+/*                 NI1 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_EXP_DATA1               0x0000000150031990
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI1_MD_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE0"                  */
+/*                     NI1 compare MD input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_ENABLE0                 0x00000001500319a0
+#define SH_XN_NI1_MD_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI1_MD_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE1"                  */
+/*                     NI1 compare MD input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_MD_CMP_ENABLE1                 0x00000001500319b0
+#define SH_XN_NI1_MD_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI1_MD_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_MD_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI1_MD_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_EXP_DATA0               0x00000001500319c0
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_MASK          0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_EXP_DATA0_DATA                                    */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_SHFT     0
+#define SH_XN_NI1_NI_CMP_EXP_DATA0_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_EXP_DATA1               0x00000001500319d0
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_MASK          0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_INIT          0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_EXP_DATA1_DATA                                    */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_SHFT     0
+#define SH_XN_NI1_NI_CMP_EXP_DATA1_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE0"                  */
+/*                     NI1 compare NI input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_ENABLE0                 0x00000001500319e0
+#define SH_XN_NI1_NI_CMP_ENABLE0_MASK            0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_ENABLE0_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_ENABLE0_ENABLE                                    */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_SHFT     0
+#define SH_XN_NI1_NI_CMP_ENABLE0_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE1"                  */
+/*                     NI1 compare NI input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_NI_CMP_ENABLE1                 0x00000001500319f0
+#define SH_XN_NI1_NI_CMP_ENABLE1_MASK            0xffffffffffffffff
+#define SH_XN_NI1_NI_CMP_ENABLE1_INIT            0x0000000000000000
+
+/*   SH_XN_NI1_NI_CMP_ENABLE1_ENABLE                                    */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_SHFT     0
+#define SH_XN_NI1_NI_CMP_ENABLE1_ENABLE_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA0"                */
+/*                 NI1 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0              0x0000000150031a00
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_MASK         0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_INIT         0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA                                   */
+/*   Description:  Expected data 0                                      */
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_SHFT    0
+#define SH_XN_NI1_LLP_CMP_EXP_DATA0_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA1"                */
+/*                 NI1 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1              0x0000000150031a10
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_MASK         0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_INIT         0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA                                   */
+/*   Description:  Expected data 1                                      */
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_SHFT    0
+#define SH_XN_NI1_LLP_CMP_EXP_DATA1_DATA_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE0"                 */
+/*                    NI1 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_ENABLE0                0x0000000150031a20
+#define SH_XN_NI1_LLP_CMP_ENABLE0_MASK           0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_ENABLE0_INIT           0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE                                   */
+/*   Description:  Enable0                                              */
+#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_SHFT    0
+#define SH_XN_NI1_LLP_CMP_ENABLE0_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE1"                 */
+/*                    NI1 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#define SH_XN_NI1_LLP_CMP_ENABLE1                0x0000000150031a30
+#define SH_XN_NI1_LLP_CMP_ENABLE1_MASK           0xffffffffffffffff
+#define SH_XN_NI1_LLP_CMP_ENABLE1_INIT           0x0000000000000000
+
+/*   SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE                                   */
+/*   Description:  Enable1                                              */
+#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_SHFT    0
+#define SH_XN_NI1_LLP_CMP_ENABLE1_ENABLE_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC_INJ_REG                      0x0000000150032000
+#define SH_XNPI_ECC_INJ_REG_MASK                 0xf0fff0fff0fff0ff
+#define SH_XNPI_ECC_INJ_REG_INIT                 0x0000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE0                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE0_SHFT           0
+#define SH_XNPI_ECC_INJ_REG_BYTE0_MASK           0x00000000000000ff
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT0                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_SHFT     12
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT0_MASK     0x0000000000001000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT0                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_SHFT      13
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT0_MASK      0x0000000000002000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT  14
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT0_MASK  0x0000000000004000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0                                  */
+/*   Description:  Replace Checkbyte Continuous                         */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_SHFT   15
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT0_MASK   0x0000000000008000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE1                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE1_SHFT           16
+#define SH_XNPI_ECC_INJ_REG_BYTE1_MASK           0x0000000000ff0000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT1                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_SHFT     28
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT1_MASK     0x0000000010000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT1                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_SHFT      29
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT1_MASK      0x0000000020000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT  30
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT1_MASK  0x0000000040000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_SHFT   31
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT1_MASK   0x0000000080000000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE2                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE2_SHFT           32
+#define SH_XNPI_ECC_INJ_REG_BYTE2_MASK           0x000000ff00000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT2                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_SHFT     44
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT2_MASK     0x0000100000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT2                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_SHFT      45
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT2_MASK      0x0000200000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2                                 */
+/*   Description:  Replace Checkbyte OneShot                            */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT  46
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT2_MASK  0x0000400000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_SHFT   47
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT2_MASK   0x0000800000000000
+
+/*   SH_XNPI_ECC_INJ_REG_BYTE3                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNPI_ECC_INJ_REG_BYTE3_SHFT           48
+#define SH_XNPI_ECC_INJ_REG_BYTE3_MASK           0x00ff000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_1SHOT3                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_SHFT     60
+#define SH_XNPI_ECC_INJ_REG_DATA_1SHOT3_MASK     0x1000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CONT3                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_SHFT      61
+#define SH_XNPI_ECC_INJ_REG_DATA_CONT3_MASK      0x2000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3                                 */
+/*   Description:  Replace Checkbyte One-Shot                           */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT  62
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_1SHOT3_MASK  0x4000000000000000
+
+/*   SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_SHFT   63
+#define SH_XNPI_ECC_INJ_REG_DATA_CB_CONT3_MASK   0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC0_INJ_MASK_REG                0x0000000150032008
+#define SH_XNPI_ECC0_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC0_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0
+#define SH_XNPI_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC1_INJ_MASK_REG                0x0000000150032010
+#define SH_XNPI_ECC1_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC1_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0
+#define SH_XNPI_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC2_INJ_MASK_REG                0x0000000150032018
+#define SH_XNPI_ECC2_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC2_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0
+#define SH_XNPI_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNPI_ECC3_INJ_MASK_REG                0x0000000150032020
+#define SH_XNPI_ECC3_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNPI_ECC3_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0
+#define SH_XNPI_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC_INJ_REG                      0x0000000150032030
+#define SH_XNMD_ECC_INJ_REG_MASK                 0xf0fff0fff0fff0ff
+#define SH_XNMD_ECC_INJ_REG_INIT                 0x0000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE0                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE0_SHFT           0
+#define SH_XNMD_ECC_INJ_REG_BYTE0_MASK           0x00000000000000ff
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT0                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_SHFT     12
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT0_MASK     0x0000000000001000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT0                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_SHFT      13
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT0_MASK      0x0000000000002000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_SHFT  14
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT0_MASK  0x0000000000004000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0                                  */
+/*   Description:  Replace Checkbyte Continuous                         */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_SHFT   15
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT0_MASK   0x0000000000008000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE1                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE1_SHFT           16
+#define SH_XNMD_ECC_INJ_REG_BYTE1_MASK           0x0000000000ff0000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT1                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_SHFT     28
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT1_MASK     0x0000000010000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT1                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_SHFT      29
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT1_MASK      0x0000000020000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1                                 */
+/*   Description:  Replace Checkbyte One Shot                           */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_SHFT  30
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT1_MASK  0x0000000040000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_SHFT   31
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT1_MASK   0x0000000080000000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE2                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE2_SHFT           32
+#define SH_XNMD_ECC_INJ_REG_BYTE2_MASK           0x000000ff00000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT2                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_SHFT     44
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT2_MASK     0x0000100000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT2                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_SHFT      45
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT2_MASK      0x0000200000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2                                 */
+/*   Description:  Replace Checkbyte OneShot                            */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_SHFT  46
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT2_MASK  0x0000400000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_SHFT   47
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT2_MASK   0x0000800000000000
+
+/*   SH_XNMD_ECC_INJ_REG_BYTE3                                          */
+/*   Description:  Replacement Checkbyte                                */
+#define SH_XNMD_ECC_INJ_REG_BYTE3_SHFT           48
+#define SH_XNMD_ECC_INJ_REG_BYTE3_MASK           0x00ff000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_1SHOT3                                    */
+/*   Description:  1 shot mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_SHFT     60
+#define SH_XNMD_ECC_INJ_REG_DATA_1SHOT3_MASK     0x1000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CONT3                                     */
+/*   Description:  toggle mask data                                     */
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_SHFT      61
+#define SH_XNMD_ECC_INJ_REG_DATA_CONT3_MASK      0x2000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3                                 */
+/*   Description:  Replace Checkbyte One-Shot                           */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_SHFT  62
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_1SHOT3_MASK  0x4000000000000000
+
+/*   SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3                                  */
+/*   Description:  Replace Checkbyte Continous                          */
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_SHFT   63
+#define SH_XNMD_ECC_INJ_REG_DATA_CB_CONT3_MASK   0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC0_INJ_MASK_REG                0x0000000150032038
+#define SH_XNMD_ECC0_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC0_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_SHFT 0
+#define SH_XNMD_ECC0_INJ_MASK_REG_MASK_ECC0_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC1_INJ_MASK_REG                0x0000000150032040
+#define SH_XNMD_ECC1_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC1_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_SHFT 0
+#define SH_XNMD_ECC1_INJ_MASK_REG_MASK_ECC1_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC2_INJ_MASK_REG                0x0000000150032048
+#define SH_XNMD_ECC2_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC2_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_SHFT 0
+#define SH_XNMD_ECC2_INJ_MASK_REG_MASK_ECC2_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC3_INJ_MASK_REG                0x0000000150032050
+#define SH_XNMD_ECC3_INJ_MASK_REG_MASK           0xffffffffffffffff
+#define SH_XNMD_ECC3_INJ_MASK_REG_INIT           0x0000000000000000
+
+/*   SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3                                */
+/*   Description:  Replacement Data                                     */
+#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_SHFT 0
+#define SH_XNMD_ECC3_INJ_MASK_REG_MASK_ECC3_MASK 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ECC_ERR_REPORT"                   */
+/* ==================================================================== */
+
+#define SH_XNMD_ECC_ERR_REPORT                   0x0000000150032058
+#define SH_XNMD_ECC_ERR_REPORT_MASK              0x0001000100010001
+#define SH_XNMD_ECC_ERR_REPORT_INIT              0x0000000000000000
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_SHFT 0
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_SHFT 16
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE1_MASK 0x0000000000010000
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_SHFT 32
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3                                */
+/*   Description:  Disable Error Correction                             */
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_SHFT 48
+#define SH_XNMD_ECC_ERR_REPORT_ECC_DISABLE3_MASK 0x0001000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_1"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_1                   0x0000000150040500
+#define SH_NI0_ERROR_SUMMARY_1_MASK              0xffffffffffffffff
+#define SH_NI0_ERROR_SUMMARY_1_INIT              0xffffffffffffffff
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0                      */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2                      */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0                      */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2                      */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP                     */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP                     */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP                     */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP                     */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH                    */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH                    */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH                    */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH                    */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT                  */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT                  */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT                  */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT                  */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0                     */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2                     */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0                   */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2                   */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0                     */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2                     */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0                     */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1                     */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2                     */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3                     */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP                    */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP                    */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP                  */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP                  */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP                    */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP                    */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP                    */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP                    */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH                   */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH                   */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH                 */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH                 */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH                   */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH                   */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT                 */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT                 */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT               */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT               */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT                 */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT                 */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT                 */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT                 */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT                 */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT                 */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0                     */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2                     */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1                     */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3                     */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0                         */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1                         */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2                         */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3                         */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_SUMMARY_1_ALIAS"                */
+/*                     ni0 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_1_ALIAS             0x0000000150040508
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_2"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_2                   0x0000000150040510
+#define SH_NI0_ERROR_SUMMARY_2_MASK              0x7fffffff003fffff
+#define SH_NI0_ERROR_SUMMARY_2_INIT              0x7fffffff003fffff
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI                                */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI                                */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD                                */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB                              */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI0_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0                            */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1                            */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2                            */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3                            */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH                             */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI0_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR                         */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_SUMMARY_2_ALIAS"                */
+/*                     ni0 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_SUMMARY_2_ALIAS             0x0000000150040518
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_1"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_1                  0x0000000150040520
+#define SH_NI0_ERROR_OVERFLOW_1_MASK             0xffffffffffffffff
+#define SH_NI0_ERROR_OVERFLOW_1_INIT             0xffffffffffffffff
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0                     */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2                     */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0                     */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2                     */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0                    */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2                    */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0                  */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2                  */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0                    */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2                    */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0                    */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1                    */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2                    */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3                    */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0                    */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2                    */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1                    */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3                    */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0                        */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1                        */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2                        */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3                        */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_OVERFLOW_1_ALIAS"               */
+/*                    ni0 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_1_ALIAS            0x0000000150040528
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_2"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_2                  0x0000000150040530
+#define SH_NI0_ERROR_OVERFLOW_2_MASK             0x7fffffff003fffff
+#define SH_NI0_ERROR_OVERFLOW_2_INIT             0x7fffffff003fffff
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI                               */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI                               */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD                               */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB                             */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI0_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP                   */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP                   */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP                   */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP                   */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH                  */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH                  */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH                  */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH                  */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT                */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT                */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT                */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT                */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP                  */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP                  */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP                */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP                */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP                  */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP                  */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP                  */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP                  */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH                 */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH                 */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH               */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH               */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH                 */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH                 */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT               */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT               */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT             */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT             */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT               */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT               */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT               */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT               */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT               */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT               */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0                           */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1                           */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2                           */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3                           */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH                            */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR                             */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI0_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR                        */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI0_ERROR_OVERFLOW_2_ALIAS"               */
+/*                    ni0 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_OVERFLOW_2_ALIAS            0x0000000150040538
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_1"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_MASK_1                      0x0000000150040540
+#define SH_NI0_ERROR_MASK_1_MASK                 0xffffffffffffffff
+#define SH_NI0_ERROR_MASK_1_INIT                 0xffffffffffffffff
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0                         */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2                         */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0                         */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2                         */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP                        */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP                        */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP                        */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP                        */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH                       */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH                       */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH                       */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH                       */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT                     */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT                     */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT                     */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT                     */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0                        */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2                        */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0                      */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2                      */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0                        */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2                        */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0                        */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1                        */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2                        */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3                        */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP                       */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP                       */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP                     */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP                     */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP                       */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP                       */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP                       */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP                       */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH                      */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH                      */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH                    */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH                    */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH                      */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH                      */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT                    */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT                    */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                  */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                  */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT                    */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT                    */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT                    */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT                    */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT                    */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT                    */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0                        */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2                        */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1                        */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3                        */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0                            */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1                            */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2                            */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3                            */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_2"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_MASK_2                      0x0000000150040550
+#define SH_NI0_ERROR_MASK_2_MASK                 0x7fffffff003fffff
+#define SH_NI0_ERROR_MASK_2_INIT                 0x7fffffff003fffff
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI                                   */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_SHFT    0
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCNI_MASK    0x0000000000000001
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI                                   */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_SHFT    1
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCPI_MASK    0x0000000000000002
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD                                   */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_SHFT    2
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCMD_MASK    0x0000000000000004
+
+/*   SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB                                 */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT  3
+#define SH_NI0_ERROR_MASK_2_ILLEGAL_VCIILB_MASK  0x0000000000000008
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0                               */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1                               */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2                               */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3                               */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH                                */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_ERROR_MASK_2_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_SHFT  61
+#define SH_NI0_ERROR_MASK_2_LUT_READ_ERROR_MASK  0x2000000000000000
+
+/*   SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR                            */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_1"                    */
+/*                        ni0  First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_FIRST_ERROR_1                     0x0000000150040560
+#define SH_NI0_FIRST_ERROR_1_MASK                0xffffffffffffffff
+#define SH_NI0_FIRST_ERROR_1_INIT                0xffffffffffffffff
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0                        */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2                        */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0                        */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2                        */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0                       */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2                       */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0                     */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2                     */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0                       */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2                       */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0                       */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1                       */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2                       */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3                       */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0                       */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2                       */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1                       */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3                       */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0                           */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1                           */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2                           */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3                           */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI0_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_2"                    */
+/*                         ni0 First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI0_FIRST_ERROR_2                     0x0000000150040570
+#define SH_NI0_FIRST_ERROR_2_MASK                0x7fffffff003fffff
+#define SH_NI0_FIRST_ERROR_2_INIT                0x7fffffff003fffff
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI                                  */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT   0
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCNI_MASK   0x0000000000000001
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI                                  */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT   1
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCPI_MASK   0x0000000000000002
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD                                  */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT   2
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCMD_MASK   0x0000000000000004
+
+/*   SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB                                */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI0_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP                      */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP                      */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP                      */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP                      */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH                     */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH                     */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH                     */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH                     */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT                   */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT                   */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT                   */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT                   */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP                     */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP                     */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP                   */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP                   */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP                     */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP                     */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP                     */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP                     */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH                    */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH                    */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                  */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                  */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH                    */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH                    */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                  */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                  */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                  */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                  */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                  */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                  */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                  */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                  */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI0_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0                              */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1                              */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2                              */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3                              */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI0_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH                               */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI0_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR                                */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI0_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR                           */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI0_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_1"                   */
+/*                ni0 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_DETAIL_1                    0x0000000150040580
+#define SH_NI0_ERROR_DETAIL_1_MASK               0xffffffffffffffff
+#define SH_NI0_ERROR_DETAIL_1_INIT               0x0000000000000000
+
+/*   SH_NI0_ERROR_DETAIL_1_HEADER                                       */
+/*   Description:  Header bits 63:0                                     */
+#define SH_NI0_ERROR_DETAIL_1_HEADER_SHFT        0
+#define SH_NI0_ERROR_DETAIL_1_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_2"                   */
+/*               ni0 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_DETAIL_2                    0x0000000150040590
+#define SH_NI0_ERROR_DETAIL_2_MASK               0xffffffffffffffff
+#define SH_NI0_ERROR_DETAIL_2_INIT               0x0000000000000000
+
+/*   SH_NI0_ERROR_DETAIL_2_HEADER                                       */
+/*   Description:  Header bits 127:64                                   */
+#define SH_NI0_ERROR_DETAIL_2_HEADER_SHFT        0
+#define SH_NI0_ERROR_DETAIL_2_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_1"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_1                   0x0000000150040600
+#define SH_NI1_ERROR_SUMMARY_1_MASK              0xffffffffffffffff
+#define SH_NI1_ERROR_SUMMARY_1_INIT              0xffffffffffffffff
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0                      */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2                      */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0                      */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2                      */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP                     */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP                     */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP                     */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP                     */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH                    */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH                    */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH                    */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH                    */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT                  */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT                  */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT                  */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT                  */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT                        */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT                        */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0                     */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2                     */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0                   */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2                   */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0                     */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2                     */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0                     */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1                     */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2                     */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3                     */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP                    */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP                    */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP                  */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP                  */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP                    */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP                    */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP                    */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP                    */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH                   */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH                   */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH                 */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH                 */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH                   */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH                   */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT                 */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT                 */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT               */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT               */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT                 */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT                 */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT                 */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT                 */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT                 */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT                 */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_SUMMARY_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0                     */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2                     */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1                     */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3                     */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0                         */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1                         */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2                         */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3                         */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_ERROR_SUMMARY_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_SUMMARY_1_ALIAS"                */
+/*                     ni1 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_1_ALIAS             0x0000000150040608
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_2"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_2                   0x0000000150040610
+#define SH_NI1_ERROR_SUMMARY_2_MASK              0x7fffffff003fffff
+#define SH_NI1_ERROR_SUMMARY_2_INIT              0x7fffffff003fffff
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI                                */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI                                */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD                                */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB                              */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI1_ERROR_SUMMARY_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_SUMMARY_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0                            */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1                            */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2                            */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3                            */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_ERROR_SUMMARY_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH                             */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_ERROR_SUMMARY_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI1_ERROR_SUMMARY_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR                         */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_ERROR_SUMMARY_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_SUMMARY_2_ALIAS"                */
+/*                     ni1 Error Summary Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_SUMMARY_2_ALIAS             0x0000000150040618
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_1"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_1                  0x0000000150040620
+#define SH_NI1_ERROR_OVERFLOW_1_MASK             0xffffffffffffffff
+#define SH_NI1_ERROR_OVERFLOW_1_INIT             0xffffffffffffffff
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0                     */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2                     */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0                     */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2                     */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP                    */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP                    */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP                    */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP                    */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH                   */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH                   */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH                   */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH                   */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT                 */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT                 */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT                 */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT                 */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT                       */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT                       */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0                    */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2                    */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0                  */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2                  */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0                    */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2                    */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0                    */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1                    */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2                    */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3                    */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP                   */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP                   */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP                 */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP                 */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP                   */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP                   */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP                   */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP                   */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH                  */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH                  */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH                */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH                */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH                  */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH                  */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT                */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT                */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT              */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT              */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT                */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT                */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT                */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT                */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT                */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT                */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_OVERFLOW_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0                    */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2                    */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1                    */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3                    */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0                        */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1                        */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2                        */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3                        */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_ERROR_OVERFLOW_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_OVERFLOW_1_ALIAS"               */
+/*                    ni1 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_1_ALIAS            0x0000000150040628
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_2"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_2                  0x0000000150040630
+#define SH_NI1_ERROR_OVERFLOW_2_MASK             0x7fffffff003fffff
+#define SH_NI1_ERROR_OVERFLOW_2_INIT             0x7fffffff003fffff
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI                               */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_SHFT 0
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCNI_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI                               */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_SHFT 1
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCPI_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD                               */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_SHFT 2
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCMD_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB                             */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI1_ERROR_OVERFLOW_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP                   */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP                   */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP                   */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP                   */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH                  */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH                  */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH                  */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH                  */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT                */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT                */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT                */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT                */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT                      */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT                      */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP                  */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP                  */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP                */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP                */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP                  */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP                  */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP                  */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP                  */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH                 */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH                 */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH               */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH               */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH                 */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH                 */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT               */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT               */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT             */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT             */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT               */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT               */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT               */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT               */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT               */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT               */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_OVERFLOW_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0                           */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1                           */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2                           */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3                           */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_ERROR_OVERFLOW_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH                            */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_ERROR_OVERFLOW_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR                             */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI1_ERROR_OVERFLOW_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR                        */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_ERROR_OVERFLOW_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*               Register "SH_NI1_ERROR_OVERFLOW_2_ALIAS"               */
+/*                    ni1 Error Overflow Bits Alias                     */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_OVERFLOW_2_ALIAS            0x0000000150040638
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_1"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_MASK_1                      0x0000000150040640
+#define SH_NI1_ERROR_MASK_1_MASK                 0xffffffffffffffff
+#define SH_NI1_ERROR_MASK_1_INIT                 0xffffffffffffffff
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0                         */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2                         */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0                         */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2                         */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP                        */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP                        */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP                        */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP                        */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH                       */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH                       */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH                       */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH                       */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT                     */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT                     */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT                     */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT                     */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT                           */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_MASK_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_MASK_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT                           */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_MASK_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0                        */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2                        */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0                      */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2                      */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0                        */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2                        */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0                        */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1                        */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2                        */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3                        */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP                       */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP                       */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP                     */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP                     */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP                       */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP                       */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP                       */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP                       */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH                      */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH                      */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH                    */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH                    */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH                      */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH                      */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT                    */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT                    */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                  */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                  */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT                    */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT                    */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT                    */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT                    */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT                    */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT                    */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_MASK_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0                        */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2                        */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1                        */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3                        */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0                            */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1                            */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2                            */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3                            */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_ERROR_MASK_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_2"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_MASK_2                      0x0000000150040650
+#define SH_NI1_ERROR_MASK_2_MASK                 0x7fffffff003fffff
+#define SH_NI1_ERROR_MASK_2_INIT                 0x7fffffff003fffff
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI                                   */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_SHFT    0
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCNI_MASK    0x0000000000000001
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI                                   */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_SHFT    1
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCPI_MASK    0x0000000000000002
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD                                   */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_SHFT    2
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCMD_MASK    0x0000000000000004
+
+/*   SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB                                 */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_SHFT  3
+#define SH_NI1_ERROR_MASK_2_ILLEGAL_VCIILB_MASK  0x0000000000000008
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_ERROR_MASK_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0                               */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1                               */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2                               */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3                               */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_ERROR_MASK_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH                                */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_ERROR_MASK_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_ERROR_MASK_2_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_SHFT  61
+#define SH_NI1_ERROR_MASK_2_LUT_READ_ERROR_MASK  0x2000000000000000
+
+/*   SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR                            */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_ERROR_MASK_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_1"                    */
+/*                        ni1  First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_FIRST_ERROR_1                     0x0000000150040660
+#define SH_NI1_FIRST_ERROR_1_MASK                0xffffffffffffffff
+#define SH_NI1_FIRST_ERROR_1_INIT                0xffffffffffffffff
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0                        */
+/*   Description:  Fifo 02 debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_SHFT 0
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2                        */
+/*   Description:  Fifo 02 debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_SHFT 1
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0                        */
+/*   Description:  Fifo 13 debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_SHFT 2
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2                        */
+/*   Description:  Fifo 13 debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_SHFT 3
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP                       */
+/*   Description:  Fifo 02 vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP                       */
+/*   Description:  Fifo 02 vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP                       */
+/*   Description:  Fifo 13 vc1 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP                       */
+/*   Description:  Fifo 13 vc3 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH                      */
+/*   Description:  Fifo 02 vc0 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH                      */
+/*   Description:  Fifo 02 vc2 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH                      */
+/*   Description:  Fifo 13 vc1 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH                      */
+/*   Description:  Fifo 13 vc3 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT                    */
+/*   Description:  Fifo 02 vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT                    */
+/*   Description:  Fifo 02 vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT                    */
+/*   Description:  Fifo 13 vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT                    */
+/*   Description:  Fifo 13 vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 0                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 1                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT                          */
+/*   Description:  VC0 credit overflow 2                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 0                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 1                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT                          */
+/*   Description:  VC2 credit overflow 2                                */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0                       */
+/*   Description:  PI Fifo debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_SHFT 22
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT0_MASK 0x0000000000400000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2                       */
+/*   Description:  PI Fifo debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_SHFT 23
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_DEBIT2_MASK 0x0000000000800000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0                     */
+/*   Description:  IILB Fifo debit0 overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_SHFT 24
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT0_MASK 0x0000000001000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2                     */
+/*   Description:  IILB Fifo debit2 overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_SHFT 25
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_DEBIT2_MASK 0x0000000002000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0                       */
+/*   Description:  MD Fifo debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_SHFT 26
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT0_MASK 0x0000000004000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2                       */
+/*   Description:  MD Fifo debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_SHFT 27
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_DEBIT2_MASK 0x0000000008000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0                       */
+/*   Description:  NI Fifo debit0 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_SHFT 28
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT0_MASK 0x0000000010000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1                       */
+/*   Description:  NI Fifo debit1 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_SHFT 29
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT1_MASK 0x0000000020000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2                       */
+/*   Description:  NI Fifo debit2 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_SHFT 30
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT2_MASK 0x0000000040000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3                       */
+/*   Description:  NI Fifo debit3 overflow                              */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_SHFT 31
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_DEBIT3_MASK 0x0000000080000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP                      */
+/*   Description:  PI Fifo vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP                      */
+/*   Description:  PI Fifo vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP                    */
+/*   Description:  IILB Fifo vc0 pop overflow                           */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP                    */
+/*   Description:  IILB Fifo vc2 pop overflow                           */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP                      */
+/*   Description:  MD Fifo vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP                      */
+/*   Description:  MD Fifo vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP                      */
+/*   Description:  NI Fifo vc0 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP                      */
+/*   Description:  NI Fifo vc2 pop overflow                             */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH                     */
+/*   Description:  PI Fifo vc0 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH                     */
+/*   Description:  PI Fifo vc2 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH                   */
+/*   Description:  IILB Fifo vc0 push overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH                   */
+/*   Description:  IILB Fifo vc2 push overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH                     */
+/*   Description:  MD Fifo vc0 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH                     */
+/*   Description:  MD Fifo vc2 push overflow                            */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT                   */
+/*   Description:  PI Fifo vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT                   */
+/*   Description:  PI Fifo vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT                 */
+/*   Description:  IILB Fifo vc0 credit overflow                        */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT                 */
+/*   Description:  IILB Fifo vc2 credit overflow                        */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT                   */
+/*   Description:  MD Fifo vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT                   */
+/*   Description:  MD Fifo vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT                   */
+/*   Description:  NI Fifo vc0 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT                   */
+/*   Description:  NI Fifo vc1 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT                   */
+/*   Description:  NI Fifo vc2 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT                   */
+/*   Description:  NI Fifo vc3 credit overflow                          */
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_FIRST_ERROR_1_OVERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0                       */
+/*   Description:  Fifo02 vc0 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_SHFT 56
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2                       */
+/*   Description:  Fifo02 vc2 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_SHFT 57
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO02_VC2_MASK 0x0200000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1                       */
+/*   Description:  Fifo13 vc1 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_SHFT 58
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC1_MASK 0x0400000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3                       */
+/*   Description:  Fifo13 vc3 tail timeout                              */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_SHFT 59
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_FIFO13_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0                           */
+/*   Description:  NI vc0 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_SHFT 60
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC0_MASK 0x1000000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1                           */
+/*   Description:  NI vc1 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_SHFT 61
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC1_MASK 0x2000000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2                           */
+/*   Description:  NI vc2 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_SHFT 62
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC2_MASK 0x4000000000000000
+
+/*   SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3                           */
+/*   Description:  NI vc3 tail timeout                                  */
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_SHFT 63
+#define SH_NI1_FIRST_ERROR_1_TAIL_TIMEOUT_NI_VC3_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_2"                    */
+/*                         ni1 First Error Bits                         */
+/* ==================================================================== */
+
+#define SH_NI1_FIRST_ERROR_2                     0x0000000150040670
+#define SH_NI1_FIRST_ERROR_2_MASK                0x7fffffff003fffff
+#define SH_NI1_FIRST_ERROR_2_INIT                0x7fffffff003fffff
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI                                  */
+/*   Description:  Illegal VC NI                                        */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_SHFT   0
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCNI_MASK   0x0000000000000001
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI                                  */
+/*   Description:  Illegal VC PI                                        */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_SHFT   1
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCPI_MASK   0x0000000000000002
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD                                  */
+/*   Description:  Illegal VC MD                                        */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_SHFT   2
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCMD_MASK   0x0000000000000004
+
+/*   SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB                                */
+/*   Description:  Illegal VC IILB                                      */
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_SHFT 3
+#define SH_NI1_FIRST_ERROR_2_ILLEGAL_VCIILB_MASK 0x0000000000000008
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP                      */
+/*   Description:  Fifo 02 vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_SHFT 4
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_POP_MASK 0x0000000000000010
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP                      */
+/*   Description:  Fifo 02 vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_SHFT 5
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_POP_MASK 0x0000000000000020
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP                      */
+/*   Description:  Fifo 13 vc1 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_SHFT 6
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_POP_MASK 0x0000000000000040
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP                      */
+/*   Description:  Fifo 13 vc3 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_SHFT 7
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_POP_MASK 0x0000000000000080
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH                     */
+/*   Description:  Fifo 02 vc0 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_SHFT 8
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_PUSH_MASK 0x0000000000000100
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH                     */
+/*   Description:  Fifo 02 vc2 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_SHFT 9
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_PUSH_MASK 0x0000000000000200
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH                     */
+/*   Description:  Fifo 13 vc1 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_SHFT 10
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC1_PUSH_MASK 0x0000000000000400
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH                     */
+/*   Description:  Fifo 13 vc3 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_SHFT 11
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC3_PUSH_MASK 0x0000000000000800
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT                   */
+/*   Description:  Fifo 02 vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_SHFT 12
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT                   */
+/*   Description:  Fifo 02 vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_SHFT 13
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO02_VC2_CREDIT_MASK 0x0000000000002000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT                   */
+/*   Description:  Fifo 13 vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_SHFT 14
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC0_CREDIT_MASK 0x0000000000004000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT                   */
+/*   Description:  Fifo 13 vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_SHFT 15
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_FIFO13_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 0                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_SHFT 16
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC0_CREDIT_MASK 0x0000000000010000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 1                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_SHFT 17
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC0_CREDIT_MASK 0x0000000000020000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT                         */
+/*   Description:  VC0 credit underflow 2                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_SHFT 18
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC0_CREDIT_MASK 0x0000000000040000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 0                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_SHFT 19
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW0_VC2_CREDIT_MASK 0x0000000000080000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 1                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_SHFT 20
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW1_VC2_CREDIT_MASK 0x0000000000100000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT                         */
+/*   Description:  VC2 credit underflow 2                               */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_SHFT 21
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW2_VC2_CREDIT_MASK 0x0000000000200000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP                     */
+/*   Description:  PI Fifo vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_SHFT 32
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_POP_MASK 0x0000000100000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP                     */
+/*   Description:  PI Fifo vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_SHFT 33
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_POP_MASK 0x0000000200000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP                   */
+/*   Description:  IILB Fifo vc0 pop underflow                          */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_SHFT 34
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_POP_MASK 0x0000000400000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP                   */
+/*   Description:  IILB Fifo vc2 pop underflow                          */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_SHFT 35
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_POP_MASK 0x0000000800000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP                     */
+/*   Description:  MD Fifo vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_SHFT 36
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_POP_MASK 0x0000001000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP                     */
+/*   Description:  MD Fifo vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_SHFT 37
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_POP_MASK 0x0000002000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP                     */
+/*   Description:  NI Fifo vc0 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_SHFT 38
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_POP_MASK 0x0000004000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP                     */
+/*   Description:  NI Fifo vc2 pop underflow                            */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_SHFT 39
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_POP_MASK 0x0000008000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH                    */
+/*   Description:  PI Fifo vc0 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_SHFT 40
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_PUSH_MASK 0x0000010000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH                    */
+/*   Description:  PI Fifo vc2 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_SHFT 41
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_PUSH_MASK 0x0000020000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH                  */
+/*   Description:  IILB Fifo vc0 push underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_SHFT 42
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_PUSH_MASK 0x0000040000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH                  */
+/*   Description:  IILB Fifo vc2 push underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_SHFT 43
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_PUSH_MASK 0x0000080000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH                    */
+/*   Description:  MD Fifo vc0 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_SHFT 44
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_PUSH_MASK 0x0000100000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH                    */
+/*   Description:  MD Fifo vc2 push underflow                           */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_SHFT 45
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_PUSH_MASK 0x0000200000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT                  */
+/*   Description:  PI Fifo vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_SHFT 46
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT                  */
+/*   Description:  PI Fifo vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_SHFT 47
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_PI_FIFO_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT                */
+/*   Description:  IILB Fifo vc0 credit underflow                       */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_SHFT 48
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC0_CREDIT_MASK 0x0001000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT                */
+/*   Description:  IILB Fifo vc2 credit underflow                       */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_SHFT 49
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_IILB_FIFO_VC2_CREDIT_MASK 0x0002000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT                  */
+/*   Description:  MD Fifo vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_SHFT 50
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC0_CREDIT_MASK 0x0004000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT                  */
+/*   Description:  MD Fifo vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_SHFT 51
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_MD_FIFO_VC2_CREDIT_MASK 0x0008000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT                  */
+/*   Description:  NI Fifo vc0 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_SHFT 52
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC0_CREDIT_MASK 0x0010000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT                  */
+/*   Description:  NI Fifo vc1 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_SHFT 53
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC1_CREDIT_MASK 0x0020000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT                  */
+/*   Description:  NI Fifo vc2 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_SHFT 54
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC2_CREDIT_MASK 0x0040000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT                  */
+/*   Description:  NI Fifo vc3 credit underflow                         */
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_SHFT 55
+#define SH_NI1_FIRST_ERROR_2_UNDERFLOW_NI_FIFO_VC3_CREDIT_MASK 0x0080000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0                              */
+/*   Description:  llp deadlock vc0                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_SHFT 56
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC0_MASK 0x0100000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1                              */
+/*   Description:  llp deadlock vc1                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_SHFT 57
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC1_MASK 0x0200000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2                              */
+/*   Description:  llp deadlock vc2                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_SHFT 58
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC2_MASK 0x0400000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3                              */
+/*   Description:  llp deadlock vc3                                     */
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_SHFT 59
+#define SH_NI1_FIRST_ERROR_2_LLP_DEADLOCK_VC3_MASK 0x0800000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH                               */
+/*   Description:  chiplet nomatch                                      */
+#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_SHFT 60
+#define SH_NI1_FIRST_ERROR_2_CHIPLET_NOMATCH_MASK 0x1000000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR                                */
+/*   Description:  LUT Read Error                                       */
+#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_SHFT 61
+#define SH_NI1_FIRST_ERROR_2_LUT_READ_ERROR_MASK 0x2000000000000000
+
+/*   SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR                           */
+/*   Description:  Retry Timeout Error                                  */
+#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_SHFT 62
+#define SH_NI1_FIRST_ERROR_2_RETRY_TIMEOUT_ERROR_MASK 0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_1"                   */
+/*                ni1 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_DETAIL_1                    0x0000000150040680
+#define SH_NI1_ERROR_DETAIL_1_MASK               0xffffffffffffffff
+#define SH_NI1_ERROR_DETAIL_1_INIT               0x0000000000000000
+
+/*   SH_NI1_ERROR_DETAIL_1_HEADER                                       */
+/*   Description:  Header bits 63:0                                     */
+#define SH_NI1_ERROR_DETAIL_1_HEADER_SHFT        0
+#define SH_NI1_ERROR_DETAIL_1_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_2"                   */
+/*               ni1 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_DETAIL_2                    0x0000000150040690
+#define SH_NI1_ERROR_DETAIL_2_MASK               0xffffffffffffffff
+#define SH_NI1_ERROR_DETAIL_2_INIT               0x0000000000000000
+
+/*   SH_NI1_ERROR_DETAIL_2_HEADER                                       */
+/*   Description:  Header bits 127:64                                   */
+#define SH_NI1_ERROR_DETAIL_2_HEADER_SHFT        0
+#define SH_NI1_ERROR_DETAIL_2_HEADER_MASK        0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_1"                  */
+/*                       Corrected error details                        */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_1                 0x0000000150040070
+#define SH_XN_CORRECTED_DETAIL_1_MASK            0x0fff0fff0fff0fff
+#define SH_XN_CORRECTED_DETAIL_1_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME                             */
+/*   Description:  ECC0 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC0_WC                                   */
+/*   Description:  ECC0 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_SHFT    8
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_WC_MASK    0x0000000000000300
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC0_VC                                   */
+/*   Description:  ECC0 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_SHFT    10
+#define SH_XN_CORRECTED_DETAIL_1_ECC0_VC_MASK    0x0000000000000c00
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME                             */
+/*   Description:  ECC1 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC1_WC                                   */
+/*   Description:  ECC1 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_SHFT    24
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_WC_MASK    0x0000000003000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC1_VC                                   */
+/*   Description:  ECC1 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_SHFT    26
+#define SH_XN_CORRECTED_DETAIL_1_ECC1_VC_MASK    0x000000000c000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME                             */
+/*   Description:  ECC2 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC2_WC                                   */
+/*   Description:  ECC2 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_SHFT    40
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_WC_MASK    0x0000030000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC2_VC                                   */
+/*   Description:  ECC2 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_SHFT    42
+#define SH_XN_CORRECTED_DETAIL_1_ECC2_VC_MASK    0x00000c0000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME                             */
+/*   Description:  ECC3 Syndrome                                        */
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC3_WC                                   */
+/*   Description:  ECC3 Word Count                                      */
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_SHFT    56
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_WC_MASK    0x0300000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_1_ECC3_VC                                   */
+/*   Description:  ECC3 Virtual Channel                                 */
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_SHFT    58
+#define SH_XN_CORRECTED_DETAIL_1_ECC3_VC_MASK    0x0c00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_2"                  */
+/*                         Corrected error data                         */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_2                 0x0000000150040080
+#define SH_XN_CORRECTED_DETAIL_2_MASK            0xffffffffffffffff
+#define SH_XN_CORRECTED_DETAIL_2_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_2_DATA                                      */
+/*   Description:  ECC data                                             */
+#define SH_XN_CORRECTED_DETAIL_2_DATA_SHFT       0
+#define SH_XN_CORRECTED_DETAIL_2_DATA_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_3"                  */
+/*                       Corrected error header0                        */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_3                 0x0000000150040090
+#define SH_XN_CORRECTED_DETAIL_3_MASK            0xffffffffffffffff
+#define SH_XN_CORRECTED_DETAIL_3_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_3_HEADER0                                   */
+/*   Description:  ECC header0 (bits 63 - 0)                            */
+#define SH_XN_CORRECTED_DETAIL_3_HEADER0_SHFT    0
+#define SH_XN_CORRECTED_DETAIL_3_HEADER0_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_4"                  */
+/*                       Corrected error header1                        */
+/* ==================================================================== */
+
+#define SH_XN_CORRECTED_DETAIL_4                 0x00000001500400a0
+#define SH_XN_CORRECTED_DETAIL_4_MASK            0xc00003ffffffffff
+#define SH_XN_CORRECTED_DETAIL_4_INIT            0x0000000000000000
+
+/*   SH_XN_CORRECTED_DETAIL_4_HEADER1                                   */
+/*   Description:  ECC header1 (bits 104 - 64)                          */
+#define SH_XN_CORRECTED_DETAIL_4_HEADER1_SHFT    0
+#define SH_XN_CORRECTED_DETAIL_4_HEADER1_MASK    0x000003ffffffffff
+
+/*   SH_XN_CORRECTED_DETAIL_4_ERR_GROUP                                 */
+/*   Description:  Error group                                          */
+#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_SHFT  62
+#define SH_XN_CORRECTED_DETAIL_4_ERR_GROUP_MASK  0xc000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_1"                 */
+/*                      Uncorrected error details                       */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_1               0x00000001500400b0
+#define SH_XN_UNCORRECTED_DETAIL_1_MASK          0x0fff0fff0fff0fff
+#define SH_XN_UNCORRECTED_DETAIL_1_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME                           */
+/*   Description:  ECC0 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_SHFT 0
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_SYNDROME_MASK 0x00000000000000ff
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC                                 */
+/*   Description:  ECC0 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_SHFT  8
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_WC_MASK  0x0000000000000300
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC                                 */
+/*   Description:  ECC0 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_SHFT  10
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC0_VC_MASK  0x0000000000000c00
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME                           */
+/*   Description:  ECC1 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_SHFT 16
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_SYNDROME_MASK 0x0000000000ff0000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC                                 */
+/*   Description:  ECC1 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_SHFT  24
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_WC_MASK  0x0000000003000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC                                 */
+/*   Description:  ECC1 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_SHFT  26
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC1_VC_MASK  0x000000000c000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME                           */
+/*   Description:  ECC2 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_SHFT 32
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_SYNDROME_MASK 0x000000ff00000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC                                 */
+/*   Description:  ECC2 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_SHFT  40
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_WC_MASK  0x0000030000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC                                 */
+/*   Description:  ECC2 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_SHFT  42
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC2_VC_MASK  0x00000c0000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME                           */
+/*   Description:  ECC3 Syndrome                                        */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_SHFT 48
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_SYNDROME_MASK 0x00ff000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC                                 */
+/*   Description:  ECC3 Word Count                                      */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_SHFT  56
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_WC_MASK  0x0300000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC                                 */
+/*   Description:  ECC3 Virtual Channel                                 */
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_SHFT  58
+#define SH_XN_UNCORRECTED_DETAIL_1_ECC3_VC_MASK  0x0c00000000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_2"                 */
+/*                        Uncorrected error data                        */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_2               0x00000001500400c0
+#define SH_XN_UNCORRECTED_DETAIL_2_MASK          0xffffffffffffffff
+#define SH_XN_UNCORRECTED_DETAIL_2_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_2_DATA                                    */
+/*   Description:  ECC data                                             */
+#define SH_XN_UNCORRECTED_DETAIL_2_DATA_SHFT     0
+#define SH_XN_UNCORRECTED_DETAIL_2_DATA_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_3"                 */
+/*                      Uncorrected error header0                       */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_3               0x00000001500400d0
+#define SH_XN_UNCORRECTED_DETAIL_3_MASK          0xffffffffffffffff
+#define SH_XN_UNCORRECTED_DETAIL_3_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_3_HEADER0                                 */
+/*   Description:  ECC header0 (bits 63 - 0)                            */
+#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_SHFT  0
+#define SH_XN_UNCORRECTED_DETAIL_3_HEADER0_MASK  0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_4"                 */
+/*                      Uncorrected error header1                       */
+/* ==================================================================== */
+
+#define SH_XN_UNCORRECTED_DETAIL_4               0x00000001500400e0
+#define SH_XN_UNCORRECTED_DETAIL_4_MASK          0xc00003ffffffffff
+#define SH_XN_UNCORRECTED_DETAIL_4_INIT          0x0000000000000000
+
+/*   SH_XN_UNCORRECTED_DETAIL_4_HEADER1                                 */
+/*   Description:  ECC header1 (bits 104 - 64)                          */
+#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_SHFT  0
+#define SH_XN_UNCORRECTED_DETAIL_4_HEADER1_MASK  0x000003ffffffffff
+
+/*   SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP                               */
+/*   Description:  Error group                                          */
+#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_SHFT 62
+#define SH_XN_UNCORRECTED_DETAIL_4_ERR_GROUP_MASK 0xc000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (md)                      */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_DETAIL_1                   0x00000001500400f0
+#define SH_XNMD_ERROR_DETAIL_1_MASK              0x00000000000007ff
+#define SH_XNMD_ERROR_DETAIL_1_INIT              0x0000000000000000
+
+/*   SH_XNMD_ERROR_DETAIL_1_LUT_ADDR                                    */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_SHFT     0
+#define SH_XNMD_ERROR_DETAIL_1_LUT_ADDR_MASK     0x00000000000007ff
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (pi)                      */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_DETAIL_1                   0x0000000150040100
+#define SH_XNPI_ERROR_DETAIL_1_MASK              0x00000000000007ff
+#define SH_XNPI_ERROR_DETAIL_1_INIT              0x0000000000000000
+
+/*   SH_XNPI_ERROR_DETAIL_1_LUT_ADDR                                    */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_SHFT     0
+#define SH_XNPI_ERROR_DETAIL_1_LUT_ADDR_MASK     0x00000000000007ff
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_1"                  */
+/*                    Chiplet NoMatch header [63:0]                     */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_DETAIL_1                 0x0000000150040110
+#define SH_XNIILB_ERROR_DETAIL_1_MASK            0xffffffffffffffff
+#define SH_XNIILB_ERROR_DETAIL_1_INIT            0x0000000000000000
+
+/*   SH_XNIILB_ERROR_DETAIL_1_HEADER                                    */
+/*   Description:  header bits [63:0]                                   */
+#define SH_XNIILB_ERROR_DETAIL_1_HEADER_SHFT     0
+#define SH_XNIILB_ERROR_DETAIL_1_HEADER_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_2"                  */
+/*                   Chiplet NoMatch header [127:64]                    */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_DETAIL_2                 0x0000000150040120
+#define SH_XNIILB_ERROR_DETAIL_2_MASK            0xffffffffffffffff
+#define SH_XNIILB_ERROR_DETAIL_2_INIT            0x0000000000000000
+
+/*   SH_XNIILB_ERROR_DETAIL_2_HEADER                                    */
+/*   Description:  header bits [127:64]                                 */
+#define SH_XNIILB_ERROR_DETAIL_2_HEADER_SHFT     0
+#define SH_XNIILB_ERROR_DETAIL_2_HEADER_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_3"                  */
+/*                     Look Up Table Address (iilb)                     */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_DETAIL_3                 0x0000000150040130
+#define SH_XNIILB_ERROR_DETAIL_3_MASK            0x00000000000007ff
+#define SH_XNIILB_ERROR_DETAIL_3_INIT            0x0000000000000000
+
+/*   SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR                                  */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_SHFT   0
+#define SH_XNIILB_ERROR_DETAIL_3_LUT_ADDR_MASK   0x00000000000007ff
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni0)                      */
+/* ==================================================================== */
+
+#define SH_NI0_ERROR_DETAIL_3                    0x0000000150040140
+#define SH_NI0_ERROR_DETAIL_3_MASK               0x00000000000007ff
+#define SH_NI0_ERROR_DETAIL_3_INIT               0x0000000000000000
+
+/*   SH_NI0_ERROR_DETAIL_3_LUT_ADDR                                     */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_SHFT      0
+#define SH_NI0_ERROR_DETAIL_3_LUT_ADDR_MASK      0x00000000000007ff
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni1)                      */
+/* ==================================================================== */
+
+#define SH_NI1_ERROR_DETAIL_3                    0x0000000150040150
+#define SH_NI1_ERROR_DETAIL_3_MASK               0x00000000000007ff
+#define SH_NI1_ERROR_DETAIL_3_INIT               0x0000000000000000
+
+/*   SH_NI1_ERROR_DETAIL_3_LUT_ADDR                                     */
+/*   Description:  Look Up Table Read Address                           */
+#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_SHFT      0
+#define SH_NI1_ERROR_DETAIL_3_LUT_ADDR_MASK      0x00000000000007ff
+
+/* ==================================================================== */
+/*                    Register "SH_XN_ERROR_SUMMARY"                    */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_SUMMARY                      0x0000000150040000
+#define SH_XN_ERROR_SUMMARY_MASK                 0x0000003fffffffff
+#define SH_XN_ERROR_SUMMARY_INIT                 0x0000003fffffffff
+
+/*   SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW                               */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_SHFT 0
+#define SH_XN_ERROR_SUMMARY_NI0_POP_OVERFLOW_MASK 0x0000000000000001
+
+/*   SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW                              */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_SHFT 1
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
+
+/*   SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW                            */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW                             */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_ERROR_SUMMARY_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW                              */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_SHFT 4
+#define SH_XN_ERROR_SUMMARY_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
+
+/*   SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW                             */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_ERROR_SUMMARY_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW                           */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_ERROR_SUMMARY_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR                                  */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_SHFT   7
+#define SH_XN_ERROR_SUMMARY_NI0_LLP_ERROR_MASK   0x0000000000000080
+
+/*   SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR                                 */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_SHFT  8
+#define SH_XN_ERROR_SUMMARY_NI0_PIPE_ERROR_MASK  0x0000000000000100
+
+/*   SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW                               */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_SHFT 9
+#define SH_XN_ERROR_SUMMARY_NI1_POP_OVERFLOW_MASK 0x0000000000000200
+
+/*   SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW                              */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_SHFT 10
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
+
+/*   SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW                            */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW                             */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_ERROR_SUMMARY_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW                              */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_SHFT 13
+#define SH_XN_ERROR_SUMMARY_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW                             */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_ERROR_SUMMARY_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW                           */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_ERROR_SUMMARY_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR                                  */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_SHFT   16
+#define SH_XN_ERROR_SUMMARY_NI1_LLP_ERROR_MASK   0x0000000000010000
+
+/*   SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR                                 */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_SHFT  17
+#define SH_XN_ERROR_SUMMARY_NI1_PIPE_ERROR_MASK  0x0000000000020000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW                           */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW                            */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_ERROR_SUMMARY_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW                        */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_ERROR_SUMMARY_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW                          */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_ERROR_SUMMARY_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR                                 */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_SHFT  22
+#define SH_XN_ERROR_SUMMARY_XNMD_SBE_ERROR_MASK  0x0000000000400000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR                                 */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_SHFT  23
+#define SH_XN_ERROR_SUMMARY_XNMD_UCE_ERROR_MASK  0x0000000000800000
+
+/*   SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR                                 */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_SHFT  24
+#define SH_XN_ERROR_SUMMARY_XNMD_LUT_ERROR_MASK  0x0000000001000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW                           */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW                            */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_ERROR_SUMMARY_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW                        */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_ERROR_SUMMARY_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW                          */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_ERROR_SUMMARY_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR                                 */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_SHFT  29
+#define SH_XN_ERROR_SUMMARY_XNPI_SBE_ERROR_MASK  0x0000000020000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR                                 */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_SHFT  30
+#define SH_XN_ERROR_SUMMARY_XNPI_UCE_ERROR_MASK  0x0000000040000000
+
+/*   SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR                                 */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_SHFT  31
+#define SH_XN_ERROR_SUMMARY_XNPI_LUT_ERROR_MASK  0x0000000080000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW                            */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_ERROR_SUMMARY_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW                           */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW                             */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW                          */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_ERROR_SUMMARY_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW                            */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_ERROR_SUMMARY_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT                            */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_ERROR_SUMMARY_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_ERRORS_ALIAS"                     */
+/* ==================================================================== */
+
+#define SH_XN_ERRORS_ALIAS                       0x0000000150040008
+
+/* ==================================================================== */
+/*                   Register "SH_XN_ERROR_OVERFLOW"                    */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_OVERFLOW                     0x0000000150040020
+#define SH_XN_ERROR_OVERFLOW_MASK                0x0000003fffffffff
+#define SH_XN_ERROR_OVERFLOW_INIT                0x0000003fffffffff
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW                              */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_SHFT 0
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_OVERFLOW_MASK 0x0000000000000001
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW                             */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_SHFT 1
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW                           */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW                            */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_ERROR_OVERFLOW_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW                             */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_SHFT 4
+#define SH_XN_ERROR_OVERFLOW_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW                            */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_ERROR_OVERFLOW_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW                          */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_ERROR_OVERFLOW_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR                                 */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_SHFT  7
+#define SH_XN_ERROR_OVERFLOW_NI0_LLP_ERROR_MASK  0x0000000000000080
+
+/*   SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR                                */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_SHFT 8
+#define SH_XN_ERROR_OVERFLOW_NI0_PIPE_ERROR_MASK 0x0000000000000100
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW                              */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_SHFT 9
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_OVERFLOW_MASK 0x0000000000000200
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW                             */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_SHFT 10
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW                           */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW                            */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_ERROR_OVERFLOW_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW                             */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_SHFT 13
+#define SH_XN_ERROR_OVERFLOW_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW                            */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_ERROR_OVERFLOW_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW                          */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_ERROR_OVERFLOW_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR                                 */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_SHFT  16
+#define SH_XN_ERROR_OVERFLOW_NI1_LLP_ERROR_MASK  0x0000000000010000
+
+/*   SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR                                */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_SHFT 17
+#define SH_XN_ERROR_OVERFLOW_NI1_PIPE_ERROR_MASK 0x0000000000020000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW                          */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW                           */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_ERROR_OVERFLOW_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW                       */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_ERROR_OVERFLOW_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW                         */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_ERROR_OVERFLOW_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR                                */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_SHFT 22
+#define SH_XN_ERROR_OVERFLOW_XNMD_SBE_ERROR_MASK 0x0000000000400000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR                                */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_SHFT 23
+#define SH_XN_ERROR_OVERFLOW_XNMD_UCE_ERROR_MASK 0x0000000000800000
+
+/*   SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR                                */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_SHFT 24
+#define SH_XN_ERROR_OVERFLOW_XNMD_LUT_ERROR_MASK 0x0000000001000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW                          */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW                           */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_ERROR_OVERFLOW_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW                       */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_ERROR_OVERFLOW_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW                         */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_ERROR_OVERFLOW_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR                                */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_SHFT 29
+#define SH_XN_ERROR_OVERFLOW_XNPI_SBE_ERROR_MASK 0x0000000020000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR                                */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_SHFT 30
+#define SH_XN_ERROR_OVERFLOW_XNPI_UCE_ERROR_MASK 0x0000000040000000
+
+/*   SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR                                */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_SHFT 31
+#define SH_XN_ERROR_OVERFLOW_XNPI_LUT_ERROR_MASK 0x0000000080000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW                           */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_ERROR_OVERFLOW_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW                          */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW                            */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW                         */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_ERROR_OVERFLOW_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW                           */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_ERROR_OVERFLOW_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT                           */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_ERROR_OVERFLOW_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                Register "SH_XN_ERROR_OVERFLOW_ALIAS"                 */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_OVERFLOW_ALIAS               0x0000000150040028
+
+/* ==================================================================== */
+/*                     Register "SH_XN_ERROR_MASK"                      */
+/* ==================================================================== */
+
+#define SH_XN_ERROR_MASK                         0x0000000150040040
+#define SH_XN_ERROR_MASK_MASK                    0x0000003fffffffff
+#define SH_XN_ERROR_MASK_INIT                    0x0000003fffffffff
+
+/*   SH_XN_ERROR_MASK_NI0_POP_OVERFLOW                                  */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_SHFT   0
+#define SH_XN_ERROR_MASK_NI0_POP_OVERFLOW_MASK   0x0000000000000001
+
+/*   SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW                                 */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_SHFT  1
+#define SH_XN_ERROR_MASK_NI0_PUSH_OVERFLOW_MASK  0x0000000000000002
+
+/*   SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW                               */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_ERROR_MASK_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW                                */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_ERROR_MASK_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW                                 */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_SHFT  4
+#define SH_XN_ERROR_MASK_NI0_POP_UNDERFLOW_MASK  0x0000000000000010
+
+/*   SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW                                */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_ERROR_MASK_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW                              */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_ERROR_MASK_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_ERROR_MASK_NI0_LLP_ERROR                                     */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_SHFT      7
+#define SH_XN_ERROR_MASK_NI0_LLP_ERROR_MASK      0x0000000000000080
+
+/*   SH_XN_ERROR_MASK_NI0_PIPE_ERROR                                    */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_SHFT     8
+#define SH_XN_ERROR_MASK_NI0_PIPE_ERROR_MASK     0x0000000000000100
+
+/*   SH_XN_ERROR_MASK_NI1_POP_OVERFLOW                                  */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_SHFT   9
+#define SH_XN_ERROR_MASK_NI1_POP_OVERFLOW_MASK   0x0000000000000200
+
+/*   SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW                                 */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_SHFT  10
+#define SH_XN_ERROR_MASK_NI1_PUSH_OVERFLOW_MASK  0x0000000000000400
+
+/*   SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW                               */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_ERROR_MASK_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW                                */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_ERROR_MASK_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW                                 */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_SHFT  13
+#define SH_XN_ERROR_MASK_NI1_POP_UNDERFLOW_MASK  0x0000000000002000
+
+/*   SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW                                */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_ERROR_MASK_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW                              */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_ERROR_MASK_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_ERROR_MASK_NI1_LLP_ERROR                                     */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_SHFT      16
+#define SH_XN_ERROR_MASK_NI1_LLP_ERROR_MASK      0x0000000000010000
+
+/*   SH_XN_ERROR_MASK_NI1_PIPE_ERROR                                    */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_SHFT     17
+#define SH_XN_ERROR_MASK_NI1_PIPE_ERROR_MASK     0x0000000000020000
+
+/*   SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW                              */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW                               */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_ERROR_MASK_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW                           */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_ERROR_MASK_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW                             */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_ERROR_MASK_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_ERROR_MASK_XNMD_SBE_ERROR                                    */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_SHFT     22
+#define SH_XN_ERROR_MASK_XNMD_SBE_ERROR_MASK     0x0000000000400000
+
+/*   SH_XN_ERROR_MASK_XNMD_UCE_ERROR                                    */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_SHFT     23
+#define SH_XN_ERROR_MASK_XNMD_UCE_ERROR_MASK     0x0000000000800000
+
+/*   SH_XN_ERROR_MASK_XNMD_LUT_ERROR                                    */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_SHFT     24
+#define SH_XN_ERROR_MASK_XNMD_LUT_ERROR_MASK     0x0000000001000000
+
+/*   SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW                              */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW                               */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_ERROR_MASK_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW                           */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_ERROR_MASK_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW                             */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_ERROR_MASK_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_ERROR_MASK_XNPI_SBE_ERROR                                    */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_SHFT     29
+#define SH_XN_ERROR_MASK_XNPI_SBE_ERROR_MASK     0x0000000020000000
+
+/*   SH_XN_ERROR_MASK_XNPI_UCE_ERROR                                    */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_SHFT     30
+#define SH_XN_ERROR_MASK_XNPI_UCE_ERROR_MASK     0x0000000040000000
+
+/*   SH_XN_ERROR_MASK_XNPI_LUT_ERROR                                    */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_SHFT     31
+#define SH_XN_ERROR_MASK_XNPI_LUT_ERROR_MASK     0x0000000080000000
+
+/*   SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW                               */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_ERROR_MASK_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW                              */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_ERROR_MASK_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW                                */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_ERROR_MASK_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW                             */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_ERROR_MASK_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW                               */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_ERROR_MASK_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT                               */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_ERROR_MASK_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                     Register "SH_XN_FIRST_ERROR"                     */
+/* ==================================================================== */
+
+#define SH_XN_FIRST_ERROR                        0x0000000150040060
+#define SH_XN_FIRST_ERROR_MASK                   0x0000003fffffffff
+#define SH_XN_FIRST_ERROR_INIT                   0x0000003fffffffff
+
+/*   SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW                                 */
+/*   Description:  NI0 pop overflow                                     */
+#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_SHFT  0
+#define SH_XN_FIRST_ERROR_NI0_POP_OVERFLOW_MASK  0x0000000000000001
+
+/*   SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW                                */
+/*   Description:  NI0 push overflow                                    */
+#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_SHFT 1
+#define SH_XN_FIRST_ERROR_NI0_PUSH_OVERFLOW_MASK 0x0000000000000002
+
+/*   SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW                              */
+/*   Description:  NI0 credit overflow                                  */
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_SHFT 2
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_OVERFLOW_MASK 0x0000000000000004
+
+/*   SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW                               */
+/*   Description:  NI0 debit overflow                                   */
+#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_SHFT 3
+#define SH_XN_FIRST_ERROR_NI0_DEBIT_OVERFLOW_MASK 0x0000000000000008
+
+/*   SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW                                */
+/*   Description:  NI0 pop underflow                                    */
+#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_SHFT 4
+#define SH_XN_FIRST_ERROR_NI0_POP_UNDERFLOW_MASK 0x0000000000000010
+
+/*   SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW                               */
+/*   Description:  NI0 push underflow                                   */
+#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_SHFT 5
+#define SH_XN_FIRST_ERROR_NI0_PUSH_UNDERFLOW_MASK 0x0000000000000020
+
+/*   SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW                             */
+/*   Description:  NI0 credit underflow                                 */
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_SHFT 6
+#define SH_XN_FIRST_ERROR_NI0_CREDIT_UNDERFLOW_MASK 0x0000000000000040
+
+/*   SH_XN_FIRST_ERROR_NI0_LLP_ERROR                                    */
+/*   Description:  NI0 llp error                                        */
+#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_SHFT     7
+#define SH_XN_FIRST_ERROR_NI0_LLP_ERROR_MASK     0x0000000000000080
+
+/*   SH_XN_FIRST_ERROR_NI0_PIPE_ERROR                                   */
+/*   Description:  NI0 Pipe in/out errors                               */
+#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_SHFT    8
+#define SH_XN_FIRST_ERROR_NI0_PIPE_ERROR_MASK    0x0000000000000100
+
+/*   SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW                                 */
+/*   Description:  NI1 pop overflow                                     */
+#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_SHFT  9
+#define SH_XN_FIRST_ERROR_NI1_POP_OVERFLOW_MASK  0x0000000000000200
+
+/*   SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW                                */
+/*   Description:  NI1 push overflow                                    */
+#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_SHFT 10
+#define SH_XN_FIRST_ERROR_NI1_PUSH_OVERFLOW_MASK 0x0000000000000400
+
+/*   SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW                              */
+/*   Description:  NI1 credit overflow                                  */
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_SHFT 11
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_OVERFLOW_MASK 0x0000000000000800
+
+/*   SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW                               */
+/*   Description:  NI1 debit overflow                                   */
+#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_SHFT 12
+#define SH_XN_FIRST_ERROR_NI1_DEBIT_OVERFLOW_MASK 0x0000000000001000
+
+/*   SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW                                */
+/*   Description:  NI1 pop underflow                                    */
+#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_SHFT 13
+#define SH_XN_FIRST_ERROR_NI1_POP_UNDERFLOW_MASK 0x0000000000002000
+
+/*   SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW                               */
+/*   Description:  NI1 push underflow                                   */
+#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_SHFT 14
+#define SH_XN_FIRST_ERROR_NI1_PUSH_UNDERFLOW_MASK 0x0000000000004000
+
+/*   SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW                             */
+/*   Description:  NI1 credit underflow                                 */
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_SHFT 15
+#define SH_XN_FIRST_ERROR_NI1_CREDIT_UNDERFLOW_MASK 0x0000000000008000
+
+/*   SH_XN_FIRST_ERROR_NI1_LLP_ERROR                                    */
+/*   Description:  NI1 llp error                                        */
+#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_SHFT     16
+#define SH_XN_FIRST_ERROR_NI1_LLP_ERROR_MASK     0x0000000000010000
+
+/*   SH_XN_FIRST_ERROR_NI1_PIPE_ERROR                                   */
+/*   Description:  NI1 pipe in/out error                                */
+#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_SHFT    17
+#define SH_XN_FIRST_ERROR_NI1_PIPE_ERROR_MASK    0x0000000000020000
+
+/*   SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW                             */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_SHFT 18
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_OVERFLOW_MASK 0x0000000000040000
+
+/*   SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW                              */
+/*   Description:  XNMD debit overflow                                  */
+#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_SHFT 19
+#define SH_XN_FIRST_ERROR_XNMD_DEBIT_OVERFLOW_MASK 0x0000000000080000
+
+/*   SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW                          */
+/*   Description:  XNMD data buffer overflow                            */
+#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_SHFT 20
+#define SH_XN_FIRST_ERROR_XNMD_DATA_BUFF_OVERFLOW_MASK 0x0000000000100000
+
+/*   SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW                            */
+/*   Description:  XNMD credit underflow                                */
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_SHFT 21
+#define SH_XN_FIRST_ERROR_XNMD_CREDIT_UNDERFLOW_MASK 0x0000000000200000
+
+/*   SH_XN_FIRST_ERROR_XNMD_SBE_ERROR                                   */
+/*   Description:  XNMD single bit error                                */
+#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_SHFT    22
+#define SH_XN_FIRST_ERROR_XNMD_SBE_ERROR_MASK    0x0000000000400000
+
+/*   SH_XN_FIRST_ERROR_XNMD_UCE_ERROR                                   */
+/*   Description:  XNMD uncorrectable error                             */
+#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_SHFT    23
+#define SH_XN_FIRST_ERROR_XNMD_UCE_ERROR_MASK    0x0000000000800000
+
+/*   SH_XN_FIRST_ERROR_XNMD_LUT_ERROR                                   */
+/*   Description:  XNMD look up table error                             */
+#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_SHFT    24
+#define SH_XN_FIRST_ERROR_XNMD_LUT_ERROR_MASK    0x0000000001000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW                             */
+/*   Description:  XNMD credit overflow                                 */
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_SHFT 25
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_OVERFLOW_MASK 0x0000000002000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW                              */
+/*   Description:  XNPI debit overflow                                  */
+#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_SHFT 26
+#define SH_XN_FIRST_ERROR_XNPI_DEBIT_OVERFLOW_MASK 0x0000000004000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW                          */
+/*   Description:  XNPI data buffer overflow                            */
+#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_SHFT 27
+#define SH_XN_FIRST_ERROR_XNPI_DATA_BUFF_OVERFLOW_MASK 0x0000000008000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW                            */
+/*   Description:  XNPI credit underflow                                */
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_SHFT 28
+#define SH_XN_FIRST_ERROR_XNPI_CREDIT_UNDERFLOW_MASK 0x0000000010000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_SBE_ERROR                                   */
+/*   Description:  XNPI single bit error                                */
+#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_SHFT    29
+#define SH_XN_FIRST_ERROR_XNPI_SBE_ERROR_MASK    0x0000000020000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_UCE_ERROR                                   */
+/*   Description:  XNPI uncorrectable error                             */
+#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_SHFT    30
+#define SH_XN_FIRST_ERROR_XNPI_UCE_ERROR_MASK    0x0000000040000000
+
+/*   SH_XN_FIRST_ERROR_XNPI_LUT_ERROR                                   */
+/*   Description:  XNPI look up table error                             */
+#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_SHFT    31
+#define SH_XN_FIRST_ERROR_XNPI_LUT_ERROR_MASK    0x0000000080000000
+
+/*   SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW                              */
+/*   Description:  IILB debit overflow                                  */
+#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_SHFT 32
+#define SH_XN_FIRST_ERROR_IILB_DEBIT_OVERFLOW_MASK 0x0000000100000000
+
+/*   SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW                             */
+/*   Description:  IILB credit overflow                                 */
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_SHFT 33
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_OVERFLOW_MASK 0x0000000200000000
+
+/*   SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW                               */
+/*   Description:  IILB fifo overflow                                   */
+#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_SHFT 34
+#define SH_XN_FIRST_ERROR_IILB_FIFO_OVERFLOW_MASK 0x0000000400000000
+
+/*   SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW                            */
+/*   Description:  IILB credit underflow                                */
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_SHFT 35
+#define SH_XN_FIRST_ERROR_IILB_CREDIT_UNDERFLOW_MASK 0x0000000800000000
+
+/*   SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW                              */
+/*   Description:  IILB fifo underflow                                  */
+#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_SHFT 36
+#define SH_XN_FIRST_ERROR_IILB_FIFO_UNDERFLOW_MASK 0x0000001000000000
+
+/*   SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT                              */
+/*   Description:  IILB chiplet nomatch or lut read error               */
+#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_SHFT 37
+#define SH_XN_FIRST_ERROR_IILB_CHIPLET_OR_LUT_MASK 0x0000002000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNIILB_ERROR_SUMMARY"                  */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_SUMMARY                  0x0000000150040200
+#define SH_XNIILB_ERROR_SUMMARY_MASK             0xffffffffffffffff
+#define SH_XNIILB_ERROR_SUMMARY_INIT             0xffffffffffffffff
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0                         */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2                         */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0                         */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2                         */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0                            */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2                            */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0                           */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2                           */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0                            */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2                            */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0                           */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2                           */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN                  */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN                */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN                  */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN                 */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN                 */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN                  */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN                */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN                  */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN                 */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN                 */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN                 */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN               */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN                 */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN                */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN                */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN                 */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN               */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN                 */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN                */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN                */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0                         */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2                         */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0                       */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2                       */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0                         */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2                         */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0                        */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2                        */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0                        */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2                        */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT                 */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT                 */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT                 */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT                 */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT               */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT               */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT                */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT                */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT                */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT                */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH                            */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_ERROR_SUMMARY_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR                             */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XNIILB_ERRORS_ALIAS"                   */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERRORS_ALIAS                   0x0000000150040208
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_OVERFLOW"                  */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_OVERFLOW                 0x0000000150040220
+#define SH_XNIILB_ERROR_OVERFLOW_MASK            0xffffffffffffffff
+#define SH_XNIILB_ERROR_OVERFLOW_INIT            0xffffffffffffffff
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0                        */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2                        */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0                        */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2                        */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0                           */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2                           */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0                          */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2                          */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0                           */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2                           */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0                          */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2                          */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN                 */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN               */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN                 */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN                */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN                */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN                 */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN               */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN                 */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN                */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN                */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN                */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN              */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN                */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN               */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN               */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN                */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN              */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN                */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN               */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN               */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0                        */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2                        */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0                      */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2                      */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0                        */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2                        */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0                       */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2                       */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0                       */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2                       */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT                */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT                */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT              */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT               */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT               */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT               */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT               */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT               */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT               */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT             */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT             */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT              */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT              */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT              */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT              */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH                           */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_ERROR_OVERFLOW_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR                            */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*              Register "SH_XNIILB_ERROR_OVERFLOW_ALIAS"               */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_OVERFLOW_ALIAS           0x0000000150040228
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_ERROR_MASK"                    */
+/* ==================================================================== */
+
+#define SH_XNIILB_ERROR_MASK                     0x0000000150040240
+#define SH_XNIILB_ERROR_MASK_MASK                0xffffffffffffffff
+#define SH_XNIILB_ERROR_MASK_INIT                0xffffffffffffffff
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0                            */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2                            */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0                            */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2                            */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0                               */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2                               */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0                              */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2                              */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0                               */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2                               */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0                              */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2                              */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN                     */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN                   */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN                     */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN                    */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN                    */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN                     */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN                   */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN                     */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN                    */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN                    */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN                    */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN                  */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN                    */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN                   */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN                   */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN                    */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN                  */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN                    */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN                   */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN                   */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0                            */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2                            */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0                          */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2                          */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0                            */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2                            */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0                           */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2                           */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0                           */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2                           */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT                    */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT                    */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT                    */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT                    */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT                  */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT                  */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT                   */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT                   */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT                   */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT                   */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH                               */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_ERROR_MASK_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_ERROR_MASK_LUT_READ_ERROR                                */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_ERROR_MASK_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_FIRST_ERROR"                   */
+/* ==================================================================== */
+
+#define SH_XNIILB_FIRST_ERROR                    0x0000000150040260
+#define SH_XNIILB_FIRST_ERROR_MASK               0xffffffffffffffff
+#define SH_XNIILB_FIRST_ERROR_INIT               0xffffffffffffffff
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0                           */
+/*   Description:  II debit0 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_SHFT 0
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT0_MASK 0x0000000000000001
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2                           */
+/*   Description:  II debit2 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_SHFT 1
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_DEBIT2_MASK 0x0000000000000002
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0                           */
+/*   Description:  LB debit0 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_SHFT 2
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT0_MASK 0x0000000000000004
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2                           */
+/*   Description:  LB debit2 overflow                                   */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_SHFT 3
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_DEBIT2_MASK 0x0000000000000008
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0                              */
+/*   Description:  II VC0 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_SHFT 4
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC0_MASK 0x0000000000000010
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2                              */
+/*   Description:  II VC2 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_SHFT 5
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_II_VC2_MASK 0x0000000000000020
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0                             */
+/*   Description:  II VC0 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_SHFT 6
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC0_MASK 0x0000000000000040
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2                             */
+/*   Description:  II VC2 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_SHFT 7
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_II_VC2_MASK 0x0000000000000080
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0                              */
+/*   Description:  LB VC0 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_SHFT 8
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2                              */
+/*   Description:  LB VC2 fifo overflow                                 */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_SHFT 9
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_LB_VC2_MASK 0x0000000000000200
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0                             */
+/*   Description:  LB VC0 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_SHFT 10
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC0_MASK 0x0000000000000400
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2                             */
+/*   Description:  LB VC2 fifo underflow                                */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_SHFT 11
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_LB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN                    */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_SHFT 12
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000001000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN                  */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_SHFT 13
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000002000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN                    */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_SHFT 14
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000000004000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN                   */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_SHFT 15
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000000008000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN                   */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_SHFT 16
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000000010000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN                    */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_SHFT 17
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000000020000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN                  */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_SHFT 18
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000000040000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN                    */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_SHFT 19
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000000080000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN                   */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_SHFT 20
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000000100000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN                   */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_SHFT 21
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000000200000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN                   */
+/*   Description:  PI VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_SHFT 22
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_IN_MASK 0x0000000000400000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN                 */
+/*   Description:  IILB VC0 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_SHFT 23
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_IN_MASK 0x0000000000800000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN                   */
+/*   Description:  MD VC0 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_SHFT 24
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_IN_MASK 0x0000000001000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN                  */
+/*   Description:  NI0 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_SHFT 25
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_IN_MASK 0x0000000002000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN                  */
+/*   Description:  NI1 VC0 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_SHFT 26
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_IN_MASK 0x0000000004000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN                   */
+/*   Description:  PI VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_SHFT 27
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_IN_MASK 0x0000000008000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN                 */
+/*   Description:  IILB VC2 credit overflow Pipe In                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_SHFT 28
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_IN_MASK 0x0000000010000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN                   */
+/*   Description:  MD VC2 credit overflow Pipe In                       */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_SHFT 29
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_IN_MASK 0x0000000020000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN                  */
+/*   Description:  NI0 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_SHFT 30
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_IN_MASK 0x0000000040000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN                  */
+/*   Description:  NI1 VC2 credit overflow Pipe In                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_SHFT 31
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_IN_MASK 0x0000000080000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0                           */
+/*   Description:  PI Fifo Debit0 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_SHFT 32
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT0_MASK 0x0000000100000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2                           */
+/*   Description:  PI Fifo Debit2 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_SHFT 33
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_DEBIT2_MASK 0x0000000200000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0                         */
+/*   Description:  IILB Fifo Debit0 overflow                            */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 34
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000400000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2                         */
+/*   Description:  IILB Fifo Debit2 overflow                            */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 35
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000000800000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0                           */
+/*   Description:  MD Fifo Debit0 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_SHFT 36
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT0_MASK 0x0000001000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2                           */
+/*   Description:  MD Fifo Debit2 overflow                              */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_SHFT 37
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_DEBIT2_MASK 0x0000002000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0                          */
+/*   Description:  NI0 Fifo Debit0 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 38
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000004000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2                          */
+/*   Description:  NI0 Fifo Debit2 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 39
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000008000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0                          */
+/*   Description:  NI1 Fifo Debit0 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 40
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000010000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2                          */
+/*   Description:  NI1 Fifo Debit2 overflow                             */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 41
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000020000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_SHFT 42
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0000040000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT                   */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_SHFT 43
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0000080000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_SHFT 44
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0000100000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT                   */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_SHFT 45
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0000200000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_SHFT 46
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0000400000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT                 */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_SHFT 47
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0000800000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_SHFT 48
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0001000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT                  */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_SHFT 49
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0002000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_SHFT 50
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x0004000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT                  */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_SHFT 51
+#define SH_XNIILB_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x0008000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT                  */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_SHFT 52
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC0_CREDIT_OUT_MASK 0x0010000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT                  */
+/*   Description:  PI VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_SHFT 53
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_PI_VC2_CREDIT_OUT_MASK 0x0020000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT                  */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_SHFT 54
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC0_CREDIT_OUT_MASK 0x0040000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT                  */
+/*   Description:  MD VC0 Credit overflow Pipe Out                      */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_SHFT 55
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_MD_VC2_CREDIT_OUT_MASK 0x0080000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT                */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_SHFT 56
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_OUT_MASK 0x0100000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT                */
+/*   Description:  IILB VC0 Credit overflow Pipe Out                    */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_SHFT 57
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_OUT_MASK 0x0200000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT                 */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_SHFT 58
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_OUT_MASK 0x0400000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT                 */
+/*   Description:  NI0 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_SHFT 59
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_OUT_MASK 0x0800000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT                 */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_SHFT 60
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_OUT_MASK 0x1000000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT                 */
+/*   Description:  NI1 VC0 Credit overflow Pipe Out                     */
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_SHFT 61
+#define SH_XNIILB_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_OUT_MASK 0x2000000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH                              */
+/*   Description:  chiplet nomatch                                      */
+#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_SHFT 62
+#define SH_XNIILB_FIRST_ERROR_CHIPLET_NOMATCH_MASK 0x4000000000000000
+
+/*   SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR                               */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_SHFT 63
+#define SH_XNIILB_FIRST_ERROR_LUT_READ_ERROR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNPI_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_SUMMARY                    0x0000000150040300
+#define SH_XNPI_ERROR_SUMMARY_MASK               0x0003ffffffffffff
+#define SH_XNPI_ERROR_SUMMARY_INIT               0x0003ffffffffffff
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0                             */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2                             */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0                             */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2                             */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0                            */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2                            */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT                          */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT                          */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0                        */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2                        */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR                               */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18
+#define SH_XNPI_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0                            */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1                            */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2                            */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3                            */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0                                 */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_SHFT  23
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR0_MASK  0x0000000000800000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1                                 */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_SHFT  24
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR1_MASK  0x0000000001000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2                                 */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_SHFT  25
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR2_MASK  0x0000000002000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3                                 */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_SHFT  26
+#define SH_XNPI_ERROR_SUMMARY_UNCOR_ERROR3_MASK  0x0000000004000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0                           */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2                           */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0                          */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2                          */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0                          */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2                          */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0                         */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2                         */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT                      */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT                      */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT                      */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT                      */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT                     */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT                     */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO                  */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNPI_ERRORS_ALIAS"                    */
+/* ==================================================================== */
+
+#define SH_XNPI_ERRORS_ALIAS                     0x0000000150040308
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_OVERFLOW                   0x0000000150040320
+#define SH_XNPI_ERROR_OVERFLOW_MASK              0x0003ffffffffffff
+#define SH_XNPI_ERROR_OVERFLOW_INIT              0x0003ffffffffffff
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0                           */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2                           */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0                           */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2                           */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0                          */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2                          */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT                        */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT                        */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0                       */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2                       */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18
+#define SH_XNPI_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0                           */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1                           */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2                           */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3                           */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0                                */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1                                */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2                                */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3                                */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26
+#define SH_XNPI_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0                         */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2                         */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0                         */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2                         */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0                         */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2                         */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0                        */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2                        */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT                    */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT                    */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT                    */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT                    */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT                   */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT                   */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO                 */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_ERROR_OVERFLOW_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_OVERFLOW_ALIAS             0x0000000150040328
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#define SH_XNPI_ERROR_MASK                       0x0000000150040340
+#define SH_XNPI_ERROR_MASK_MASK                  0x0003ffffffffffff
+#define SH_XNPI_ERROR_MASK_INIT                  0x0003ffffffffffff
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0                                */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2                                */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0                                */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2                                */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0                               */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2                               */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT                             */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT                             */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0                           */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2                           */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_ERROR_MASK_LUT_READ_ERROR                                  */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_SHFT   18
+#define SH_XNPI_ERROR_MASK_LUT_READ_ERROR_MASK   0x0000000000040000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0                               */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1                               */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2                               */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3                               */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR0                                    */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_SHFT     23
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR0_MASK     0x0000000000800000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR1                                    */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_SHFT     24
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR1_MASK     0x0000000001000000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR2                                    */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_SHFT     25
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR2_MASK     0x0000000002000000
+
+/*   SH_XNPI_ERROR_MASK_UNCOR_ERROR3                                    */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_SHFT     26
+#define SH_XNPI_ERROR_MASK_UNCOR_ERROR3_MASK     0x0000000004000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0                              */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2                              */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0                             */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2                             */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0                             */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2                             */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0                            */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2                            */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT                         */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT                         */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT                         */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT                         */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT                        */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT                        */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO                     */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#define SH_XNPI_FIRST_ERROR                      0x0000000150040360
+#define SH_XNPI_FIRST_ERROR_MASK                 0x0003ffffffffffff
+#define SH_XNPI_FIRST_ERROR_INIT                 0x0003ffffffffffff
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0                              */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2                              */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0                              */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2                              */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0                             */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2                             */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT                           */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT                           */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0                          */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2                          */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNPI_FIRST_ERROR_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_SHFT  18
+#define SH_XNPI_FIRST_ERROR_LUT_READ_ERROR_MASK  0x0000000000040000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0                              */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1                              */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2                              */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3                              */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNPI_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR0                                   */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_SHFT    23
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR0_MASK    0x0000000000800000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR1                                   */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_SHFT    24
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR1_MASK    0x0000000001000000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR2                                   */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_SHFT    25
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR2_MASK    0x0000000002000000
+
+/*   SH_XNPI_FIRST_ERROR_UNCOR_ERROR3                                   */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_SHFT    26
+#define SH_XNPI_FIRST_ERROR_UNCOR_ERROR3_MASK    0x0000000004000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0                            */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2                            */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0                            */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2                            */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0                            */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2                            */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0                           */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2                           */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT                       */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT                       */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT                       */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT                       */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT                      */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT                      */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNPI_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO                    */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNPI_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNMD_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_SUMMARY                    0x0000000150040400
+#define SH_XNMD_ERROR_SUMMARY_MASK               0x0003ffffffffffff
+#define SH_XNMD_ERROR_SUMMARY_INIT               0x0003ffffffffffff
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0                             */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2                             */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0                             */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2                             */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0                            */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2                            */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT                          */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT                          */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0                        */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2                        */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR                               */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_SHFT 18
+#define SH_XNMD_ERROR_SUMMARY_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0                            */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1                            */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2                            */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3                            */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_ERROR_SUMMARY_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0                                 */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_SHFT  23
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR0_MASK  0x0000000000800000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1                                 */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_SHFT  24
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR1_MASK  0x0000000001000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2                                 */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_SHFT  25
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR2_MASK  0x0000000002000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3                                 */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_SHFT  26
+#define SH_XNMD_ERROR_SUMMARY_UNCOR_ERROR3_MASK  0x0000000004000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0                           */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2                           */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0                          */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2                          */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0                          */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2                          */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0                         */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2                         */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT                      */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT                      */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT                      */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT                      */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT                     */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_ERROR_SUMMARY_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT                     */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO                  */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_ERROR_SUMMARY_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XNMD_ERRORS_ALIAS"                    */
+/* ==================================================================== */
+
+#define SH_XNMD_ERRORS_ALIAS                     0x0000000150040408
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_OVERFLOW                   0x0000000150040420
+#define SH_XNMD_ERROR_OVERFLOW_MASK              0x0003ffffffffffff
+#define SH_XNMD_ERROR_OVERFLOW_INIT              0x0003ffffffffffff
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0                           */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0                            */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2                           */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2                            */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0                           */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0                            */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2                           */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2                            */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0                          */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0                           */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2                          */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2                           */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT                        */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT                         */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT                        */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT                         */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0                       */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2                       */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR                              */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_SHFT 18
+#define SH_XNMD_ERROR_OVERFLOW_LUT_READ_ERROR_MASK 0x0000000000040000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0                           */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1                           */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2                           */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3                           */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_ERROR_OVERFLOW_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0                                */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_SHFT 23
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR0_MASK 0x0000000000800000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1                                */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_SHFT 24
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR1_MASK 0x0000000001000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2                                */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_SHFT 25
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR2_MASK 0x0000000002000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3                                */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_SHFT 26
+#define SH_XNMD_ERROR_OVERFLOW_UNCOR_ERROR3_MASK 0x0000000004000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0                         */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0                          */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2                         */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2                          */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0                         */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2                         */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0                         */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2                         */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0                        */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2                        */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT                    */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT                     */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT                    */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT                     */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT                    */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT                     */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT                    */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT                     */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT                   */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT                    */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT                   */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_ERROR_OVERFLOW_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT                    */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO                 */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_ERROR_OVERFLOW_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_ERROR_OVERFLOW_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_OVERFLOW_ALIAS             0x0000000150040428
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#define SH_XNMD_ERROR_MASK                       0x0000000150040440
+#define SH_XNMD_ERROR_MASK_MASK                  0x0003ffffffffffff
+#define SH_XNMD_ERROR_MASK_INIT                  0x0003ffffffffffff
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0                                */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2                                */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0                                */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2                                */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0                               */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2                               */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT                             */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT                             */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_ERROR_MASK_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0                           */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2                           */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_ERROR_MASK_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_ERROR_MASK_LUT_READ_ERROR                                  */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_SHFT   18
+#define SH_XNMD_ERROR_MASK_LUT_READ_ERROR_MASK   0x0000000000040000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0                               */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1                               */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2                               */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3                               */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_ERROR_MASK_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR0                                    */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_SHFT     23
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR0_MASK     0x0000000000800000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR1                                    */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_SHFT     24
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR1_MASK     0x0000000001000000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR2                                    */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_SHFT     25
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR2_MASK     0x0000000002000000
+
+/*   SH_XNMD_ERROR_MASK_UNCOR_ERROR3                                    */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_SHFT     26
+#define SH_XNMD_ERROR_MASK_UNCOR_ERROR3_MASK     0x0000000004000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0                              */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2                              */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_ERROR_MASK_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0                             */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2                             */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0                             */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2                             */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0                            */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2                            */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT                         */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT                         */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT                         */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT                         */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_ERROR_MASK_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT                        */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_ERROR_MASK_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT                        */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_ERROR_MASK_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO                     */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_ERROR_MASK_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#define SH_XNMD_FIRST_ERROR                      0x0000000150040460
+#define SH_XNMD_FIRST_ERROR_MASK                 0x0003ffffffffffff
+#define SH_XNMD_FIRST_ERROR_INIT                 0x0003ffffffffffff
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0                              */
+/*   Description:  NI0 VC0 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_SHFT 0
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_MASK 0x0000000000000001
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0                               */
+/*   Description:  NI0 VC0 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_SHFT 1
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_MASK 0x0000000000000002
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2                              */
+/*   Description:  NI0 VC2 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_SHFT 2
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_MASK 0x0000000000000004
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2                               */
+/*   Description:  NI0 VC2 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_SHFT 3
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_MASK 0x0000000000000008
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0                              */
+/*   Description:  NI1 VC0 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_SHFT 4
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_MASK 0x0000000000000010
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0                               */
+/*   Description:  NI1 VC0 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_SHFT 5
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_MASK 0x0000000000000020
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2                              */
+/*   Description:  NI1 VC2 fifo underflow                               */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_SHFT 6
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_MASK 0x0000000000000040
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2                               */
+/*   Description:  NI1 VC2 fifo overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_SHFT 7
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_MASK 0x0000000000000080
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0                             */
+/*   Description:  IILB VC0 fifo underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_SHFT 8
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_MASK 0x0000000000000100
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0                              */
+/*   Description:  IILB VC0 fifo overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_SHFT 9
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_MASK 0x0000000000000200
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2                             */
+/*   Description:  IILB VC2 fifo underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_SHFT 10
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_MASK 0x0000000000000400
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2                              */
+/*   Description:  IILB VC2 fifo overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_SHFT 11
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_MASK 0x0000000000000800
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT                           */
+/*   Description:  VC0 Credit underflow                                 */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_SHFT 12
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC0_CREDIT_MASK 0x0000000000001000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT                            */
+/*   Description:  VC0 Credit overflow                                  */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_SHFT 13
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC0_CREDIT_MASK 0x0000000000002000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT                           */
+/*   Description:  VC2 Credit underflow                                 */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_SHFT 14
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_VC2_CREDIT_MASK 0x0000000000004000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT                            */
+/*   Description:  VC2 Credit overflow                                  */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_SHFT 15
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_VC2_CREDIT_MASK 0x0000000000008000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0                          */
+/*   Description:  VC0 Data Buffer overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_SHFT 16
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC0_MASK 0x0000000000010000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2                          */
+/*   Description:  VC2 Data Buffer overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_SHFT 17
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_DATABUFF_VC2_MASK 0x0000000000020000
+
+/*   SH_XNMD_FIRST_ERROR_LUT_READ_ERROR                                 */
+/*   Description:  LUT Read Error                                       */
+#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_SHFT  18
+#define SH_XNMD_FIRST_ERROR_LUT_READ_ERROR_MASK  0x0000000000040000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0                              */
+/*   Description:  Single Bit Error in Bits 63:0                        */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_SHFT 19
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR0_MASK 0x0000000000080000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1                              */
+/*   Description:  Single Bit Error in Bits 127:64                      */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_SHFT 20
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR1_MASK 0x0000000000100000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2                              */
+/*   Description:  Single Bit Error in Bits 191:128                     */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_SHFT 21
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR2_MASK 0x0000000000200000
+
+/*   SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3                              */
+/*   Description:  Single Bit Error in Bits 255:192                     */
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_SHFT 22
+#define SH_XNMD_FIRST_ERROR_SINGLE_BIT_ERROR3_MASK 0x0000000000400000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR0                                   */
+/*   Description:  Uncorrectable Error in Bits 63:0                     */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_SHFT    23
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR0_MASK    0x0000000000800000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR1                                   */
+/*   Description:  Uncorrectable Error in Bits 127:64                   */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_SHFT    24
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR1_MASK    0x0000000001000000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR2                                   */
+/*   Description:  Uncorrectable Error in Bits 191:128                  */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_SHFT    25
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR2_MASK    0x0000000002000000
+
+/*   SH_XNMD_FIRST_ERROR_UNCOR_ERROR3                                   */
+/*   Description:  Uncorrectable Error in Bits 255:192                  */
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_SHFT    26
+#define SH_XNMD_FIRST_ERROR_UNCOR_ERROR3_MASK    0x0000000004000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0                            */
+/*   Description:  SIC Counter 0 Underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_SHFT 27
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR0_MASK 0x0000000008000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0                             */
+/*   Description:  SIC Counter 0 Overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_SHFT 28
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR0_MASK 0x0000000010000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2                            */
+/*   Description:  SIC Counter 2 Underflow                              */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_SHFT 29
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_SIC_CNTR2_MASK 0x0000000020000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2                             */
+/*   Description:  SIC Counter 2 Overflow                               */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_SHFT 30
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_SIC_CNTR2_MASK 0x0000000040000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0                            */
+/*   Description:  NI0 Debit 0 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_SHFT 31
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT0_MASK 0x0000000080000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2                            */
+/*   Description:  NI0 Debit 2 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_SHFT 32
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_DEBIT2_MASK 0x0000000100000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0                            */
+/*   Description:  NI1 Debit 0 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_SHFT 33
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT0_MASK 0x0000000200000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2                            */
+/*   Description:  NI1 Debit 2 Overflow                                 */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_SHFT 34
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_DEBIT2_MASK 0x0000000400000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0                           */
+/*   Description:  IILB Debit 0 Overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_SHFT 35
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT0_MASK 0x0000000800000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2                           */
+/*   Description:  IILB Debit 2 Overflow                                */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_SHFT 36
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_DEBIT2_MASK 0x0000001000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT                       */
+/*   Description:  NI0 VC0 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_SHFT 37
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC0_CREDIT_MASK 0x0000002000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT                        */
+/*   Description:  NI0 VC0 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_SHFT 38
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC0_CREDIT_MASK 0x0000004000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT                       */
+/*   Description:  NI0 VC2 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_SHFT 39
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI0_VC2_CREDIT_MASK 0x0000008000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT                        */
+/*   Description:  NI0 VC2 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_SHFT 40
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI0_VC2_CREDIT_MASK 0x0000010000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT                       */
+/*   Description:  NI1 VC0 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_SHFT 41
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC0_CREDIT_MASK 0x0000020000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT                        */
+/*   Description:  NI1 VC0 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_SHFT 42
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC0_CREDIT_MASK 0x0000040000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT                       */
+/*   Description:  NI1 VC2 Credit Underflow                             */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_SHFT 43
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_NI1_VC2_CREDIT_MASK 0x0000080000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT                        */
+/*   Description:  NI1 VC2 Credit Overflow                              */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_SHFT 44
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_NI1_VC2_CREDIT_MASK 0x0000100000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT                      */
+/*   Description:  IILB VC0 Credit Underflow                            */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_SHFT 45
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC0_CREDIT_MASK 0x0000200000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT                       */
+/*   Description:  IILB VC0 Credit Overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_SHFT 46
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC0_CREDIT_MASK 0x0000400000000000
+
+/*   SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT                      */
+/*   Description:  IILB VC2 Credit Underflow                            */
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_SHFT 47
+#define SH_XNMD_FIRST_ERROR_UNDERFLOW_IILB_VC2_CREDIT_MASK 0x0000800000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT                       */
+/*   Description:  IILB VC2 Credit Overflow                             */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_SHFT 48
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_IILB_VC2_CREDIT_MASK 0x0001000000000000
+
+/*   SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO                    */
+/*   Description:  Header Cancel Fifo Overflow                          */
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_SHFT 49
+#define SH_XNMD_FIRST_ERROR_OVERFLOW_HEADER_CANCEL_FIFO_MASK 0x0002000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE0"                   */
+/*                 Automatic Maintenance Reply Enable 0                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_ENABLE0                    0x0000000110061000
+#define SH_AUTO_REPLY_ENABLE0_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_ENABLE0_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_ENABLE0_ENABLE0                                      */
+/*   Description:  Enable 0                                             */
+#define SH_AUTO_REPLY_ENABLE0_ENABLE0_SHFT       0
+#define SH_AUTO_REPLY_ENABLE0_ENABLE0_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE1"                   */
+/*                 Automatic Maintenance Reply Enable 1                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_ENABLE1                    0x0000000110061080
+#define SH_AUTO_REPLY_ENABLE1_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_ENABLE1_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_ENABLE1_ENABLE1                                      */
+/*   Description:  Enable 1                                             */
+#define SH_AUTO_REPLY_ENABLE1_ENABLE1_SHFT       0
+#define SH_AUTO_REPLY_ENABLE1_ENABLE1_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER0"                   */
+/*                 Automatic Maintenance Reply Header 0                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_HEADER0                    0x0000000110061100
+#define SH_AUTO_REPLY_HEADER0_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_HEADER0_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_HEADER0_HEADER0                                      */
+/*   Description:  Header 0                                             */
+#define SH_AUTO_REPLY_HEADER0_HEADER0_SHFT       0
+#define SH_AUTO_REPLY_HEADER0_HEADER0_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER1"                   */
+/*                 Automatic Maintenance Reply Header 1                 */
+/* ==================================================================== */
+
+#define SH_AUTO_REPLY_HEADER1                    0x0000000110061180
+#define SH_AUTO_REPLY_HEADER1_MASK               0xffffffffffffffff
+#define SH_AUTO_REPLY_HEADER1_INIT               0x0000000000000000
+
+/*   SH_AUTO_REPLY_HEADER1_HEADER1                                      */
+/*   Description:  Header 1                                             */
+#define SH_AUTO_REPLY_HEADER1_HEADER1_SHFT       0
+#define SH_AUTO_REPLY_HEADER1_HEADER1_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RP_AUTO_REPLY"                  */
+/*         Enable Automatic Maintenance Reply From Reply Queue          */
+/* ==================================================================== */
+
+#define SH_ENABLE_RP_AUTO_REPLY                  0x0000000110061200
+#define SH_ENABLE_RP_AUTO_REPLY_MASK             0x0000000000000001
+#define SH_ENABLE_RP_AUTO_REPLY_INIT             0x0000000000000000
+
+/*   SH_ENABLE_RP_AUTO_REPLY_ENABLE                                     */
+/*   Description:  Enable Reply Auto Reply                              */
+#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_SHFT      0
+#define SH_ENABLE_RP_AUTO_REPLY_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RQ_AUTO_REPLY"                  */
+/*        Enable Automatic Maintenance Reply From Request Queue         */
+/* ==================================================================== */
+
+#define SH_ENABLE_RQ_AUTO_REPLY                  0x0000000110061280
+#define SH_ENABLE_RQ_AUTO_REPLY_MASK             0x0000000000000001
+#define SH_ENABLE_RQ_AUTO_REPLY_INIT             0x0000000000000000
+
+/*   SH_ENABLE_RQ_AUTO_REPLY_ENABLE                                     */
+/*   Description:  Enable Request Auto Reply                            */
+#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_SHFT      0
+#define SH_ENABLE_RQ_AUTO_REPLY_ENABLE_MASK      0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_REDIRECT_INVAL"                     */
+/*               Redirect invalidate to LB instead of PI                */
+/* ==================================================================== */
+
+#define SH_REDIRECT_INVAL                        0x0000000110061300
+#define SH_REDIRECT_INVAL_MASK                   0x0000000000000001
+#define SH_REDIRECT_INVAL_INIT                   0x0000000000000000
+
+/*   SH_REDIRECT_INVAL_REDIRECT                                         */
+/*   Description:  Redirect invalidates to LB instead of PI             */
+#define SH_REDIRECT_INVAL_REDIRECT_SHFT          0
+#define SH_REDIRECT_INVAL_REDIRECT_MASK          0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_CNTRL"                     */
+/*                 Diagnostic Message Control Register                  */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_CNTRL                        0x0000000110062000
+#define SH_DIAG_MSG_CNTRL_MASK                   0xc000000000003fff
+#define SH_DIAG_MSG_CNTRL_INIT                   0x0000000000000000
+
+/*   SH_DIAG_MSG_CNTRL_MSG_LENGTH                                       */
+/*   Description:  Message data payload length, 0 - 63                  */
+#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_SHFT        0
+#define SH_DIAG_MSG_CNTRL_MSG_LENGTH_MASK        0x000000000000003f
+
+/*   SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT                               */
+/*   Description:  Point message that the error bit would be activated  */
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_SHFT 6
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_POINT_MASK 0x0000000000000fc0
+
+/*   SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE                              */
+/*   Description:  Enable ERROR_INJECT_POINT field                      */
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_SHFT 12
+#define SH_DIAG_MSG_CNTRL_ERROR_INJECT_ENABLE_MASK 0x0000000000001000
+
+/*   SH_DIAG_MSG_CNTRL_PORT                                             */
+/*   Description:  0 = request port, 1 = reply port                     */
+#define SH_DIAG_MSG_CNTRL_PORT_SHFT              13
+#define SH_DIAG_MSG_CNTRL_PORT_MASK              0x0000000000002000
+
+/*   SH_DIAG_MSG_CNTRL_START                                            */
+/*   Description:  Start                                                */
+#define SH_DIAG_MSG_CNTRL_START_SHFT             62
+#define SH_DIAG_MSG_CNTRL_START_MASK             0x4000000000000000
+
+/*   SH_DIAG_MSG_CNTRL_BUSY                                             */
+/*   Description:  Busy                                                 */
+#define SH_DIAG_MSG_CNTRL_BUSY_SHFT              63
+#define SH_DIAG_MSG_CNTRL_BUSY_MASK              0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA0L                       0x0000000110062080
+#define SH_DIAG_MSG_DATA0L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA0L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA0L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA0L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA0L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA0U                       0x0000000110062100
+#define SH_DIAG_MSG_DATA0U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA0U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA0U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA0U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA0U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA1L                       0x0000000110062180
+#define SH_DIAG_MSG_DATA1L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA1L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA1L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA1L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA1L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA1U                       0x0000000110062200
+#define SH_DIAG_MSG_DATA1U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA1U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA1U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA1U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA1U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA2L                       0x0000000110062280
+#define SH_DIAG_MSG_DATA2L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA2L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA2L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA2L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA2L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA2U                       0x0000000110062300
+#define SH_DIAG_MSG_DATA2U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA2U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA2U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA2U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA2U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA3L                       0x0000000110062380
+#define SH_DIAG_MSG_DATA3L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA3L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA3L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA3L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA3L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA3U                       0x0000000110062400
+#define SH_DIAG_MSG_DATA3U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA3U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA3U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA3U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA3U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA4L                       0x0000000110062480
+#define SH_DIAG_MSG_DATA4L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA4L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA4L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA4L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA4L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA4U                       0x0000000110062500
+#define SH_DIAG_MSG_DATA4U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA4U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA4U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA4U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA4U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA5L                       0x0000000110062580
+#define SH_DIAG_MSG_DATA5L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA5L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA5L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA5L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA5L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA5U                       0x0000000110062600
+#define SH_DIAG_MSG_DATA5U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA5U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA5U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA5U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA5U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA6L                       0x0000000110062680
+#define SH_DIAG_MSG_DATA6L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA6L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA6L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA6L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA6L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA6U                       0x0000000110062700
+#define SH_DIAG_MSG_DATA6U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA6U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA6U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA6U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA6U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA7L                       0x0000000110062780
+#define SH_DIAG_MSG_DATA7L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA7L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA7L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA7L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA7L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA7U                       0x0000000110062800
+#define SH_DIAG_MSG_DATA7U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA7U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA7U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA7U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA7U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA8L                       0x0000000110062880
+#define SH_DIAG_MSG_DATA8L_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA8L_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA8L_DATA_LOWER                                      */
+/*   Description:  Lower 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA8L_DATA_LOWER_SHFT       0
+#define SH_DIAG_MSG_DATA8L_DATA_LOWER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_DATA8U                       0x0000000110062900
+#define SH_DIAG_MSG_DATA8U_MASK                  0xffffffffffffffff
+#define SH_DIAG_MSG_DATA8U_INIT                  0x0000000000000000
+
+/*   SH_DIAG_MSG_DATA8U_DATA_UPPER                                      */
+/*   Description:  Upper 64 bits of Diagnositic Message Data            */
+#define SH_DIAG_MSG_DATA8U_DATA_UPPER_SHFT       0
+#define SH_DIAG_MSG_DATA8U_DATA_UPPER_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR0"                      */
+/*              Diagnostice Data, lower 64 bits of header               */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_HDR0                         0x0000000110062980
+#define SH_DIAG_MSG_HDR0_MASK                    0xffffffffffffffff
+#define SH_DIAG_MSG_HDR0_INIT                    0x0000000000000000
+
+/*   SH_DIAG_MSG_HDR0_HEADER0                                           */
+/*   Description:  Lower 64 bits of Diagnositic Message Header          */
+#define SH_DIAG_MSG_HDR0_HEADER0_SHFT            0
+#define SH_DIAG_MSG_HDR0_HEADER0_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR1"                      */
+/*              Diagnostice Data, upper 64 bits of header               */
+/* ==================================================================== */
+
+#define SH_DIAG_MSG_HDR1                         0x0000000110062a00
+#define SH_DIAG_MSG_HDR1_MASK                    0xffffffffffffffff
+#define SH_DIAG_MSG_HDR1_INIT                    0x0000000000000000
+
+/*   SH_DIAG_MSG_HDR1_HEADER1                                           */
+/*   Description:  Upper 64 bits of Diagnositic Message Header          */
+#define SH_DIAG_MSG_HDR1_HEADER1_SHFT            0
+#define SH_DIAG_MSG_HDR1_HEADER1_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_DEBUG_SELECT"                      */
+/*                        SHub Debug Port Select                        */
+/* ==================================================================== */
+
+#define SH_DEBUG_SELECT                          0x0000000110063000
+#define SH_DEBUG_SELECT_MASK                     0x8fffffffffffffff
+#define SH_DEBUG_SELECT_INIT                     0x0000e38e38e38e38
+
+/*   SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL                                 */
+/*   Description:  Nibble0_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_SHFT  0
+#define SH_DEBUG_SELECT_NIBBLE0_NIBBLE_SEL_MASK  0x0000000000000007
+
+/*   SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL                                */
+/*   Description:  Nibble0_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_SHFT 3
+#define SH_DEBUG_SELECT_NIBBLE0_CHIPLET_SEL_MASK 0x0000000000000038
+
+/*   SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL                                 */
+/*   Description:  Nibble1_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_SHFT  6
+#define SH_DEBUG_SELECT_NIBBLE1_NIBBLE_SEL_MASK  0x00000000000001c0
+
+/*   SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL                                */
+/*   Description:  Nibble1_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_SHFT 9
+#define SH_DEBUG_SELECT_NIBBLE1_CHIPLET_SEL_MASK 0x0000000000000e00
+
+/*   SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL                                 */
+/*   Description:  Nibble2_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_SHFT  12
+#define SH_DEBUG_SELECT_NIBBLE2_NIBBLE_SEL_MASK  0x0000000000007000
+
+/*   SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL                                */
+/*   Description:  Nibble2_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_SHFT 15
+#define SH_DEBUG_SELECT_NIBBLE2_CHIPLET_SEL_MASK 0x0000000000038000
+
+/*   SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL                                 */
+/*   Description:  Nibble3_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_SHFT  18
+#define SH_DEBUG_SELECT_NIBBLE3_NIBBLE_SEL_MASK  0x00000000001c0000
+
+/*   SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL                                */
+/*   Description:  Nibble3_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_SHFT 21
+#define SH_DEBUG_SELECT_NIBBLE3_CHIPLET_SEL_MASK 0x0000000000e00000
+
+/*   SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL                                 */
+/*   Description:  Nibble4_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_SHFT  24
+#define SH_DEBUG_SELECT_NIBBLE4_NIBBLE_SEL_MASK  0x0000000007000000
+
+/*   SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL                                */
+/*   Description:  Nibble4_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_SHFT 27
+#define SH_DEBUG_SELECT_NIBBLE4_CHIPLET_SEL_MASK 0x0000000038000000
+
+/*   SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL                                 */
+/*   Description:  Nibble5_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_SHFT  30
+#define SH_DEBUG_SELECT_NIBBLE5_NIBBLE_SEL_MASK  0x00000001c0000000
+
+/*   SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL                                */
+/*   Description:  Nibble5_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_SHFT 33
+#define SH_DEBUG_SELECT_NIBBLE5_CHIPLET_SEL_MASK 0x0000000e00000000
+
+/*   SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL                                 */
+/*   Description:  Nibble6_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_SHFT  36
+#define SH_DEBUG_SELECT_NIBBLE6_NIBBLE_SEL_MASK  0x0000007000000000
+
+/*   SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL                                */
+/*   Description:  Nibble6_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_SHFT 39
+#define SH_DEBUG_SELECT_NIBBLE6_CHIPLET_SEL_MASK 0x0000038000000000
+
+/*   SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL                                 */
+/*   Description:  Nibble7_nibble_select                                */
+#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_SHFT  42
+#define SH_DEBUG_SELECT_NIBBLE7_NIBBLE_SEL_MASK  0x00001c0000000000
+
+/*   SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL                                */
+/*   Description:  Nibble7_chiplet_select                               */
+#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_SHFT 45
+#define SH_DEBUG_SELECT_NIBBLE7_CHIPLET_SEL_MASK 0x0000e00000000000
+
+/*   SH_DEBUG_SELECT_DEBUG_II_SEL                                       */
+/*   Description:  Select bits to II port                               */
+#define SH_DEBUG_SELECT_DEBUG_II_SEL_SHFT        48
+#define SH_DEBUG_SELECT_DEBUG_II_SEL_MASK        0x0007000000000000
+
+/*   SH_DEBUG_SELECT_SEL_II                                             */
+/*   Description:  Select II to debug port                              */
+#define SH_DEBUG_SELECT_SEL_II_SHFT              51
+#define SH_DEBUG_SELECT_SEL_II_MASK              0x0ff8000000000000
+
+/*   SH_DEBUG_SELECT_TRIGGER_ENABLE                                     */
+/*   Description:  Enable trigger on bit 32 of Analyzer data            */
+#define SH_DEBUG_SELECT_TRIGGER_ENABLE_SHFT      63
+#define SH_DEBUG_SELECT_TRIGGER_ENABLE_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_TRIGGER_COMPARE_MASK"                  */
+/*                      SHub Trigger Compare Mask                       */
+/* ==================================================================== */
+
+#define SH_TRIGGER_COMPARE_MASK                  0x0000000110063080
+#define SH_TRIGGER_COMPARE_MASK_MASK             0x00000000ffffffff
+#define SH_TRIGGER_COMPARE_MASK_INIT             0x0000000000000000
+
+/*   SH_TRIGGER_COMPARE_MASK_MASK                                       */
+/*   Description:  SHub Trigger Compare Mask                            */
+#define SH_TRIGGER_COMPARE_MASK_MASK_SHFT        0
+#define SH_TRIGGER_COMPARE_MASK_MASK_MASK        0x00000000ffffffff
+
+/* ==================================================================== */
+/*                Register "SH_TRIGGER_COMPARE_PATTERN"                 */
+/*                     SHub Trigger Compare Pattern                     */
+/* ==================================================================== */
+
+#define SH_TRIGGER_COMPARE_PATTERN               0x0000000110063100
+#define SH_TRIGGER_COMPARE_PATTERN_MASK          0x00000000ffffffff
+#define SH_TRIGGER_COMPARE_PATTERN_INIT          0x0000000000000000
+
+/*   SH_TRIGGER_COMPARE_PATTERN_DATA                                    */
+/*   Description:  SHub Trigger Compare Pattern                         */
+#define SH_TRIGGER_COMPARE_PATTERN_DATA_SHFT     0
+#define SH_TRIGGER_COMPARE_PATTERN_DATA_MASK     0x00000000ffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_TRIGGER_SEL"                       */
+/*                  Trigger select for SHUB debug port                  */
+/* ==================================================================== */
+
+#define SH_TRIGGER_SEL                           0x0000000110063180
+#define SH_TRIGGER_SEL_MASK                      0x7777777777777777
+#define SH_TRIGGER_SEL_INIT                      0x0000000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL                                   */
+/*   Description:  Nibble 0 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_SHFT    0
+#define SH_TRIGGER_SEL_NIBBLE0_INPUT_SEL_MASK    0x0000000000000007
+
+/*   SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL                                  */
+/*   Description:  Nibble 0 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_SHFT   4
+#define SH_TRIGGER_SEL_NIBBLE0_NIBBLE_SEL_MASK   0x0000000000000070
+
+/*   SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL                                   */
+/*   Description:  Nibble 1 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_SHFT    8
+#define SH_TRIGGER_SEL_NIBBLE1_INPUT_SEL_MASK    0x0000000000000700
+
+/*   SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL                                  */
+/*   Description:  Nibble 1 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_SHFT   12
+#define SH_TRIGGER_SEL_NIBBLE1_NIBBLE_SEL_MASK   0x0000000000007000
+
+/*   SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL                                   */
+/*   Description:  Nibble 2 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_SHFT    16
+#define SH_TRIGGER_SEL_NIBBLE2_INPUT_SEL_MASK    0x0000000000070000
+
+/*   SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL                                  */
+/*   Description:  Nibble 2 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_SHFT   20
+#define SH_TRIGGER_SEL_NIBBLE2_NIBBLE_SEL_MASK   0x0000000000700000
+
+/*   SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL                                   */
+/*   Description:  Nibble 3 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_SHFT    24
+#define SH_TRIGGER_SEL_NIBBLE3_INPUT_SEL_MASK    0x0000000007000000
+
+/*   SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL                                  */
+/*   Description:  Nibble 3 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_SHFT   28
+#define SH_TRIGGER_SEL_NIBBLE3_NIBBLE_SEL_MASK   0x0000000070000000
+
+/*   SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL                                   */
+/*   Description:  Nibble 4 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_SHFT    32
+#define SH_TRIGGER_SEL_NIBBLE4_INPUT_SEL_MASK    0x0000000700000000
+
+/*   SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL                                  */
+/*   Description:  Nibble 4 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_SHFT   36
+#define SH_TRIGGER_SEL_NIBBLE4_NIBBLE_SEL_MASK   0x0000007000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL                                   */
+/*   Description:  Nibble 5 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_SHFT    40
+#define SH_TRIGGER_SEL_NIBBLE5_INPUT_SEL_MASK    0x0000070000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL                                  */
+/*   Description:  Nibble 5 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_SHFT   44
+#define SH_TRIGGER_SEL_NIBBLE5_NIBBLE_SEL_MASK   0x0000700000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL                                   */
+/*   Description:  Nibble 6 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_SHFT    48
+#define SH_TRIGGER_SEL_NIBBLE6_INPUT_SEL_MASK    0x0007000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL                                  */
+/*   Description:  Nibble 6 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_SHFT   52
+#define SH_TRIGGER_SEL_NIBBLE6_NIBBLE_SEL_MASK   0x0070000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL                                   */
+/*   Description:  Nibble 7 input select                                */
+#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_SHFT    56
+#define SH_TRIGGER_SEL_NIBBLE7_INPUT_SEL_MASK    0x0700000000000000
+
+/*   SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL                                  */
+/*   Description:  Nibble 7 Nibble select                               */
+#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_SHFT   60
+#define SH_TRIGGER_SEL_NIBBLE7_NIBBLE_SEL_MASK   0x7000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_STOP_CLK_CONTROL"                    */
+/*                          Stop Clock Control                          */
+/* ==================================================================== */
+
+#define SH_STOP_CLK_CONTROL                      0x0000000110064000
+#define SH_STOP_CLK_CONTROL_MASK                 0x00000000000000ff
+#define SH_STOP_CLK_CONTROL_INIT                 0x00000000000000e0
+
+/*   SH_STOP_CLK_CONTROL_STIMULUS                                       */
+/*   Description:  Counter stimulus                                     */
+#define SH_STOP_CLK_CONTROL_STIMULUS_SHFT        0
+#define SH_STOP_CLK_CONTROL_STIMULUS_MASK        0x000000000000001f
+
+/*   SH_STOP_CLK_CONTROL_EVENT                                          */
+/*   Description:  Counter event select (0-greater than, 1-equal)       */
+#define SH_STOP_CLK_CONTROL_EVENT_SHFT           5
+#define SH_STOP_CLK_CONTROL_EVENT_MASK           0x0000000000000020
+
+/*   SH_STOP_CLK_CONTROL_POLARITY                                       */
+/*   Description:  Counter polarity select (0-negative edge, 1-positiv  */
+/*  e edge)                                                             */
+#define SH_STOP_CLK_CONTROL_POLARITY_SHFT        6
+#define SH_STOP_CLK_CONTROL_POLARITY_MASK        0x0000000000000040
+
+/*   SH_STOP_CLK_CONTROL_MODE                                           */
+/*   Description:  Counter mode select (0-internal, 1-external)         */
+#define SH_STOP_CLK_CONTROL_MODE_SHFT            7
+#define SH_STOP_CLK_CONTROL_MODE_MASK            0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_STOP_CLK_DELAY_PHASE"                  */
+/*                        Stop Clock Delay Phase                        */
+/* ==================================================================== */
+
+#define SH_STOP_CLK_DELAY_PHASE                  0x0000000110064080
+#define SH_STOP_CLK_DELAY_PHASE_MASK             0x00000000000000ff
+#define SH_STOP_CLK_DELAY_PHASE_INIT             0x0000000000000000
+
+/*   SH_STOP_CLK_DELAY_PHASE_DELAY                                      */
+/*   Description:  Delay phase                                          */
+#define SH_STOP_CLK_DELAY_PHASE_DELAY_SHFT       0
+#define SH_STOP_CLK_DELAY_PHASE_DELAY_MASK       0x00000000000000ff
+
+/* ==================================================================== */
+/*                      Register "SH_TSF_ARM_MASK"                      */
+/*                 Trigger sequencing facility arm mask                 */
+/* ==================================================================== */
+
+#define SH_TSF_ARM_MASK                          0x0000000110065000
+#define SH_TSF_ARM_MASK_MASK                     0xffffffffffffffff
+#define SH_TSF_ARM_MASK_INIT                     0x0000000000000000
+
+/*   SH_TSF_ARM_MASK_MASK                                               */
+/*   Description:  Trigger sequencing facility arm mask                 */
+#define SH_TSF_ARM_MASK_MASK_SHFT                0
+#define SH_TSF_ARM_MASK_MASK_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_COUNTER_PRESETS"                   */
+/*             Trigger sequencing facility counter presets              */
+/* ==================================================================== */
+
+#define SH_TSF_COUNTER_PRESETS                   0x0000000110065080
+#define SH_TSF_COUNTER_PRESETS_MASK              0xffffffffffffffff
+#define SH_TSF_COUNTER_PRESETS_INIT              0x0000000000000000
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_32                                    */
+/*   Description:  Trigger sequencing facility counter 32               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_32_SHFT     0
+#define SH_TSF_COUNTER_PRESETS_COUNT_32_MASK     0x00000000ffffffff
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_16                                    */
+/*   Description:  Trigger sequencing facility counter 16               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_16_SHFT     32
+#define SH_TSF_COUNTER_PRESETS_COUNT_16_MASK     0x0000ffff00000000
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_8B                                    */
+/*   Description:  Trigger sequencing facility counter 8b               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_8B_SHFT     48
+#define SH_TSF_COUNTER_PRESETS_COUNT_8B_MASK     0x00ff000000000000
+
+/*   SH_TSF_COUNTER_PRESETS_COUNT_8A                                    */
+/*   Description:  Trigger sequencing facility counter 8a               */
+#define SH_TSF_COUNTER_PRESETS_COUNT_8A_SHFT     56
+#define SH_TSF_COUNTER_PRESETS_COUNT_8A_MASK     0xff00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_DECREMENT_CTL"                    */
+/*        Trigger sequencing facility counter decrement control         */
+/* ==================================================================== */
+
+#define SH_TSF_DECREMENT_CTL                     0x0000000110065100
+#define SH_TSF_DECREMENT_CTL_MASK                0x000000000000ffff
+#define SH_TSF_DECREMENT_CTL_INIT                0x0000000000000000
+
+/*   SH_TSF_DECREMENT_CTL_CTL                                           */
+/*   Description:  Trigger sequencing facility counter decrement contr  */
+#define SH_TSF_DECREMENT_CTL_CTL_SHFT            0
+#define SH_TSF_DECREMENT_CTL_CTL_MASK            0x000000000000ffff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DIAG_MSG_CTL"                    */
+/*        Trigger sequencing facility diagnostic message control        */
+/* ==================================================================== */
+
+#define SH_TSF_DIAG_MSG_CTL                      0x0000000110065180
+#define SH_TSF_DIAG_MSG_CTL_MASK                 0x00000000000000ff
+#define SH_TSF_DIAG_MSG_CTL_INIT                 0x0000000000000000
+
+/*   SH_TSF_DIAG_MSG_CTL_ENABLE                                         */
+/*   Description:  Trigger sequencing facility diagnostic message cont  */
+#define SH_TSF_DIAG_MSG_CTL_ENABLE_SHFT          0
+#define SH_TSF_DIAG_MSG_CTL_ENABLE_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DISARM_MASK"                     */
+/*               Trigger sequencing facility disarm mask                */
+/* ==================================================================== */
+
+#define SH_TSF_DISARM_MASK                       0x0000000110065200
+#define SH_TSF_DISARM_MASK_MASK                  0xffffffffffffffff
+#define SH_TSF_DISARM_MASK_INIT                  0x0000000000000000
+
+/*   SH_TSF_DISARM_MASK_MASK                                            */
+/*   Description:  Trigger sequencing facility disarm mask              */
+#define SH_TSF_DISARM_MASK_MASK_SHFT             0
+#define SH_TSF_DISARM_MASK_MASK_MASK             0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_TSF_ENABLE_CTL"                     */
+/*          Trigger sequencing facility counter enable control          */
+/* ==================================================================== */
+
+#define SH_TSF_ENABLE_CTL                        0x0000000110065280
+#define SH_TSF_ENABLE_CTL_MASK                   0x000000000000ffff
+#define SH_TSF_ENABLE_CTL_INIT                   0x0000000000000000
+
+/*   SH_TSF_ENABLE_CTL_CTL                                              */
+/*   Description:  Trigger sequencing facility counter enable control  */
+#define SH_TSF_ENABLE_CTL_CTL_SHFT               0
+#define SH_TSF_ENABLE_CTL_CTL_MASK               0x000000000000ffff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_SOFTWARE_ARM"                    */
+/*               Trigger sequencing facility software arm               */
+/* ==================================================================== */
+
+#define SH_TSF_SOFTWARE_ARM                      0x0000000110065300
+#define SH_TSF_SOFTWARE_ARM_MASK                 0x00000000000000ff
+#define SH_TSF_SOFTWARE_ARM_INIT                 0x0000000000000000
+
+/*   SH_TSF_SOFTWARE_ARM_BIT0                                           */
+/*   Description:  Trigger sequencing facility software arm bit 0       */
+#define SH_TSF_SOFTWARE_ARM_BIT0_SHFT            0
+#define SH_TSF_SOFTWARE_ARM_BIT0_MASK            0x0000000000000001
+
+/*   SH_TSF_SOFTWARE_ARM_BIT1                                           */
+/*   Description:  Trigger sequencing facility software arm bit 1       */
+#define SH_TSF_SOFTWARE_ARM_BIT1_SHFT            1
+#define SH_TSF_SOFTWARE_ARM_BIT1_MASK            0x0000000000000002
+
+/*   SH_TSF_SOFTWARE_ARM_BIT2                                           */
+/*   Description:  Trigger sequencing facility software arm bit 2       */
+#define SH_TSF_SOFTWARE_ARM_BIT2_SHFT            2
+#define SH_TSF_SOFTWARE_ARM_BIT2_MASK            0x0000000000000004
+
+/*   SH_TSF_SOFTWARE_ARM_BIT3                                           */
+/*   Description:  Trigger sequencing facility software arm bit 3       */
+#define SH_TSF_SOFTWARE_ARM_BIT3_SHFT            3
+#define SH_TSF_SOFTWARE_ARM_BIT3_MASK            0x0000000000000008
+
+/*   SH_TSF_SOFTWARE_ARM_BIT4                                           */
+/*   Description:  Trigger sequencing facility software arm bit 4       */
+#define SH_TSF_SOFTWARE_ARM_BIT4_SHFT            4
+#define SH_TSF_SOFTWARE_ARM_BIT4_MASK            0x0000000000000010
+
+/*   SH_TSF_SOFTWARE_ARM_BIT5                                           */
+/*   Description:  Trigger sequencing facility software arm bit 5       */
+#define SH_TSF_SOFTWARE_ARM_BIT5_SHFT            5
+#define SH_TSF_SOFTWARE_ARM_BIT5_MASK            0x0000000000000020
+
+/*   SH_TSF_SOFTWARE_ARM_BIT6                                           */
+/*   Description:  Trigger sequencing facility software arm bit 6       */
+#define SH_TSF_SOFTWARE_ARM_BIT6_SHFT            6
+#define SH_TSF_SOFTWARE_ARM_BIT6_MASK            0x0000000000000040
+
+/*   SH_TSF_SOFTWARE_ARM_BIT7                                           */
+/*   Description:  Trigger sequencing facility software arm bit 7       */
+#define SH_TSF_SOFTWARE_ARM_BIT7_SHFT            7
+#define SH_TSF_SOFTWARE_ARM_BIT7_MASK            0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_SOFTWARE_DISARM"                   */
+/*             Trigger sequencing facility software disarm              */
+/* ==================================================================== */
+
+#define SH_TSF_SOFTWARE_DISARM                   0x0000000110065380
+#define SH_TSF_SOFTWARE_DISARM_MASK              0x00000000000000ff
+#define SH_TSF_SOFTWARE_DISARM_INIT              0x0000000000000000
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT0                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 0    */
+#define SH_TSF_SOFTWARE_DISARM_BIT0_SHFT         0
+#define SH_TSF_SOFTWARE_DISARM_BIT0_MASK         0x0000000000000001
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT1                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 1    */
+#define SH_TSF_SOFTWARE_DISARM_BIT1_SHFT         1
+#define SH_TSF_SOFTWARE_DISARM_BIT1_MASK         0x0000000000000002
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT2                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 2    */
+#define SH_TSF_SOFTWARE_DISARM_BIT2_SHFT         2
+#define SH_TSF_SOFTWARE_DISARM_BIT2_MASK         0x0000000000000004
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT3                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 3    */
+#define SH_TSF_SOFTWARE_DISARM_BIT3_SHFT         3
+#define SH_TSF_SOFTWARE_DISARM_BIT3_MASK         0x0000000000000008
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT4                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 4    */
+#define SH_TSF_SOFTWARE_DISARM_BIT4_SHFT         4
+#define SH_TSF_SOFTWARE_DISARM_BIT4_MASK         0x0000000000000010
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT5                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 5    */
+#define SH_TSF_SOFTWARE_DISARM_BIT5_SHFT         5
+#define SH_TSF_SOFTWARE_DISARM_BIT5_MASK         0x0000000000000020
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT6                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 6    */
+#define SH_TSF_SOFTWARE_DISARM_BIT6_SHFT         6
+#define SH_TSF_SOFTWARE_DISARM_BIT6_MASK         0x0000000000000040
+
+/*   SH_TSF_SOFTWARE_DISARM_BIT7                                        */
+/*   Description:  Trigger sequencing facility software disarm bit 7    */
+#define SH_TSF_SOFTWARE_DISARM_BIT7_SHFT         7
+#define SH_TSF_SOFTWARE_DISARM_BIT7_MASK         0x0000000000000080
+
+/* ==================================================================== */
+/*                 Register "SH_TSF_SOFTWARE_TRIGGERED"                 */
+/*            Trigger sequencing facility software triggered            */
+/* ==================================================================== */
+
+#define SH_TSF_SOFTWARE_TRIGGERED                0x0000000110065400
+#define SH_TSF_SOFTWARE_TRIGGERED_MASK           0x00000000000000ff
+#define SH_TSF_SOFTWARE_TRIGGERED_INIT           0x0000000000000000
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT0                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_SHFT      0
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT0_MASK      0x0000000000000001
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT1                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_SHFT      1
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT1_MASK      0x0000000000000002
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT2                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_SHFT      2
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT2_MASK      0x0000000000000004
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT3                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_SHFT      3
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT3_MASK      0x0000000000000008
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT4                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_SHFT      4
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT4_MASK      0x0000000000000010
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT5                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_SHFT      5
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT5_MASK      0x0000000000000020
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT6                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_SHFT      6
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT6_MASK      0x0000000000000040
+
+/*   SH_TSF_SOFTWARE_TRIGGERED_BIT7                                     */
+/*   Description:  Trigger sequencing facility software triggered bit   */
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_SHFT      7
+#define SH_TSF_SOFTWARE_TRIGGERED_BIT7_MASK      0x0000000000000080
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_TRIGGER_MASK"                    */
+/*               Trigger sequencing facility trigger mask               */
+/* ==================================================================== */
+
+#define SH_TSF_TRIGGER_MASK                      0x0000000110065480
+#define SH_TSF_TRIGGER_MASK_MASK                 0xffffffffffffffff
+#define SH_TSF_TRIGGER_MASK_INIT                 0x0000000000000000
+
+/*   SH_TSF_TRIGGER_MASK_MASK                                           */
+/*   Description:  Trigger sequencing facility trigger mask             */
+#define SH_TSF_TRIGGER_MASK_MASK_SHFT            0
+#define SH_TSF_TRIGGER_MASK_MASK_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_VEC_DATA"                        */
+/*                  Vector Write Request Message Data                   */
+/* ==================================================================== */
+
+#define SH_VEC_DATA                              0x0000000110066000
+#define SH_VEC_DATA_MASK                         0xffffffffffffffff
+#define SH_VEC_DATA_INIT                         0x0000000000000000
+
+/*   SH_VEC_DATA_DATA                                                   */
+/*   Description:  Data                                                 */
+#define SH_VEC_DATA_DATA_SHFT                    0
+#define SH_VEC_DATA_DATA_MASK                    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_PARMS"                        */
+/*                  Vector Message Parameters Register                  */
+/* ==================================================================== */
+
+#define SH_VEC_PARMS                             0x0000000110066080
+#define SH_VEC_PARMS_MASK                        0xc0003ffffffffffb
+#define SH_VEC_PARMS_INIT                        0x0000000000000000
+
+/*   SH_VEC_PARMS_TYPE                                                  */
+/*   Description:  Vector Request Message Type                          */
+#define SH_VEC_PARMS_TYPE_SHFT                   0
+#define SH_VEC_PARMS_TYPE_MASK                   0x0000000000000001
+
+/*   SH_VEC_PARMS_NI_PORT                                               */
+/*   Description:  Network Interface Port Select                        */
+#define SH_VEC_PARMS_NI_PORT_SHFT                1
+#define SH_VEC_PARMS_NI_PORT_MASK                0x0000000000000002
+
+/*   SH_VEC_PARMS_ADDRESS                                               */
+/*   Description:  Address[37:6]                                        */
+#define SH_VEC_PARMS_ADDRESS_SHFT                3
+#define SH_VEC_PARMS_ADDRESS_MASK                0x00000007fffffff8
+
+/*   SH_VEC_PARMS_PIO_ID                                                */
+/*   Description:  PIO ID                                               */
+#define SH_VEC_PARMS_PIO_ID_SHFT                 35
+#define SH_VEC_PARMS_PIO_ID_MASK                 0x00003ff800000000
+
+/*   SH_VEC_PARMS_START                                                 */
+/*   Description:  Start                                                */
+#define SH_VEC_PARMS_START_SHFT                  62
+#define SH_VEC_PARMS_START_MASK                  0x4000000000000000
+
+/*   SH_VEC_PARMS_BUSY                                                  */
+/*   Description:  Busy                                                 */
+#define SH_VEC_PARMS_BUSY_SHFT                   63
+#define SH_VEC_PARMS_BUSY_MASK                   0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_ROUTE"                        */
+/*                     Vector Request Message Route                     */
+/* ==================================================================== */
+
+#define SH_VEC_ROUTE                             0x0000000110066100
+#define SH_VEC_ROUTE_MASK                        0xffffffffffffffff
+#define SH_VEC_ROUTE_INIT                        0x0000000000000000
+
+/*   SH_VEC_ROUTE_ROUTE                                                 */
+/*   Description:  Route                                                */
+#define SH_VEC_ROUTE_ROUTE_SHFT                  0
+#define SH_VEC_ROUTE_ROUTE_MASK                  0xffffffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_CPU_PERM"                        */
+/*                    CPU MMR Access Permission Bits                    */
+/* ==================================================================== */
+
+#define SH_CPU_PERM                              0x0000000110060000
+#define SH_CPU_PERM_MASK                         0xffffffffffffffff
+#define SH_CPU_PERM_INIT                         0xffffffffffffffff
+
+/*   SH_CPU_PERM_ACCESS_BITS                                            */
+/*   Description:  Access Bits                                          */
+#define SH_CPU_PERM_ACCESS_BITS_SHFT             0
+#define SH_CPU_PERM_ACCESS_BITS_MASK             0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_CPU_PERM_OVR"                      */
+/*                  CPU MMR Access Permission Override                  */
+/* ==================================================================== */
+
+#define SH_CPU_PERM_OVR                          0x0000000110060080
+#define SH_CPU_PERM_OVR_MASK                     0xffffffffffffffff
+#define SH_CPU_PERM_OVR_INIT                     0x0000000000000000
+
+/*   SH_CPU_PERM_OVR_OVERRIDE                                           */
+/*   Description:  Override                                             */
+#define SH_CPU_PERM_OVR_OVERRIDE_SHFT            0
+#define SH_CPU_PERM_OVR_OVERRIDE_MASK            0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_EXT_IO_PERM"                       */
+/*                External IO MMR Access Permission Bits                */
+/* ==================================================================== */
+
+#define SH_EXT_IO_PERM                           0x0000000110060100
+#define SH_EXT_IO_PERM_MASK                      0xffffffffffffffff
+#define SH_EXT_IO_PERM_INIT                      0x0000000000000000
+
+/*   SH_EXT_IO_PERM_ACCESS_BITS                                         */
+/*   Description:  Access Bits                                          */
+#define SH_EXT_IO_PERM_ACCESS_BITS_SHFT          0
+#define SH_EXT_IO_PERM_ACCESS_BITS_MASK          0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_EXT_IOI_ACCESS"                     */
+/*             External IO Interrupt Access Permission Bits             */
+/* ==================================================================== */
+
+#define SH_EXT_IOI_ACCESS                        0x0000000110060180
+#define SH_EXT_IOI_ACCESS_MASK                   0xffffffffffffffff
+#define SH_EXT_IOI_ACCESS_INIT                   0xffffffffffffffff
+
+/*   SH_EXT_IOI_ACCESS_ACCESS_BITS                                      */
+/*   Description:  Access Bits                                          */
+#define SH_EXT_IOI_ACCESS_ACCESS_BITS_SHFT       0
+#define SH_EXT_IOI_ACCESS_ACCESS_BITS_MASK       0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_GC_FIL_CTRL"                       */
+/*                   SHub Global Clock Filter Control                   */
+/* ==================================================================== */
+
+#define SH_GC_FIL_CTRL                           0x0000000110060200
+#define SH_GC_FIL_CTRL_MASK                      0x03ff3ff3ff1fff1f
+#define SH_GC_FIL_CTRL_INIT                      0x0000000000000000
+
+/*   SH_GC_FIL_CTRL_OFFSET                                              */
+/*   Description:  Offset                                               */
+#define SH_GC_FIL_CTRL_OFFSET_SHFT               0
+#define SH_GC_FIL_CTRL_OFFSET_MASK               0x000000000000001f
+
+/*   SH_GC_FIL_CTRL_MASK_COUNTER                                        */
+/*   Description:  Mask Counter                                         */
+#define SH_GC_FIL_CTRL_MASK_COUNTER_SHFT         8
+#define SH_GC_FIL_CTRL_MASK_COUNTER_MASK         0x00000000000fff00
+
+/*   SH_GC_FIL_CTRL_MASK_ENABLE                                         */
+/*   Description:  Mask Enable                                          */
+#define SH_GC_FIL_CTRL_MASK_ENABLE_SHFT          20
+#define SH_GC_FIL_CTRL_MASK_ENABLE_MASK          0x0000000000100000
+
+/*   SH_GC_FIL_CTRL_DROPOUT_COUNTER                                     */
+/*   Description:  Dropout Counter                                      */
+#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_SHFT      24
+#define SH_GC_FIL_CTRL_DROPOUT_COUNTER_MASK      0x00000003ff000000
+
+/*   SH_GC_FIL_CTRL_DROPOUT_THRESH                                      */
+/*   Description:  Dropout threshold                                    */
+#define SH_GC_FIL_CTRL_DROPOUT_THRESH_SHFT       36
+#define SH_GC_FIL_CTRL_DROPOUT_THRESH_MASK       0x00003ff000000000
+
+/*   SH_GC_FIL_CTRL_ERROR_COUNTER                                       */
+/*   Description:  Error counter                                        */
+#define SH_GC_FIL_CTRL_ERROR_COUNTER_SHFT        48
+#define SH_GC_FIL_CTRL_ERROR_COUNTER_MASK        0x03ff000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_GC_SRC_CTRL"                       */
+/*                      SHub Global Clock Control                       */
+/* ==================================================================== */
+
+#define SH_GC_SRC_CTRL                           0x0000000110060280
+#define SH_GC_SRC_CTRL_MASK                      0x0000000313ff3ff1
+#define SH_GC_SRC_CTRL_INIT                      0x0000000100000000
+
+/*   SH_GC_SRC_CTRL_ENABLE_COUNTER                                      */
+/*   Description:  Enable Counter                                       */
+#define SH_GC_SRC_CTRL_ENABLE_COUNTER_SHFT       0
+#define SH_GC_SRC_CTRL_ENABLE_COUNTER_MASK       0x0000000000000001
+
+/*   SH_GC_SRC_CTRL_MAX_COUNT                                           */
+/*   Description:  Max Count                                            */
+#define SH_GC_SRC_CTRL_MAX_COUNT_SHFT            4
+#define SH_GC_SRC_CTRL_MAX_COUNT_MASK            0x0000000000003ff0
+
+/*   SH_GC_SRC_CTRL_COUNTER                                             */
+/*   Description:  Counter                                              */
+#define SH_GC_SRC_CTRL_COUNTER_SHFT              16
+#define SH_GC_SRC_CTRL_COUNTER_MASK              0x0000000003ff0000
+
+/*   SH_GC_SRC_CTRL_TOGGLE_BIT                                          */
+/*   Description:  Toggle bit                                           */
+#define SH_GC_SRC_CTRL_TOGGLE_BIT_SHFT           28
+#define SH_GC_SRC_CTRL_TOGGLE_BIT_MASK           0x0000000010000000
+
+/*   SH_GC_SRC_CTRL_SOURCE_SEL                                          */
+/*   Description:  Source select (0=ext., 1=Int., 2=SHUB)               */
+#define SH_GC_SRC_CTRL_SOURCE_SEL_SHFT           32
+#define SH_GC_SRC_CTRL_SOURCE_SEL_MASK           0x0000000300000000
+
+/* ==================================================================== */
+/*                       Register "SH_HARD_RESET"                       */
+/*                           SHub Hard Reset                            */
+/* ==================================================================== */
+
+#define SH_HARD_RESET                            0x0000000110060300
+#define SH_HARD_RESET_MASK                       0x0000000000000001
+#define SH_HARD_RESET_INIT                       0x0000000000000000
+
+/*   SH_HARD_RESET_HARD_RESET                                           */
+/*   Description:  Hard Reset                                           */
+#define SH_HARD_RESET_HARD_RESET_SHFT            0
+#define SH_HARD_RESET_HARD_RESET_MASK            0x0000000000000001
+
+/* ==================================================================== */
+/*                        Register "SH_IO_PERM"                         */
+/*                    II MMR Access Permission Bits                     */
+/* ==================================================================== */
+
+#define SH_IO_PERM                               0x0000000110060380
+#define SH_IO_PERM_MASK                          0xffffffffffffffff
+#define SH_IO_PERM_INIT                          0x0000000000000000
+
+/*   SH_IO_PERM_ACCESS_BITS                                             */
+/*   Description:  Access Bits                                          */
+#define SH_IO_PERM_ACCESS_BITS_SHFT              0
+#define SH_IO_PERM_ACCESS_BITS_MASK              0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_IOI_ACCESS"                       */
+/*                 II Interrupt Access Permission Bits                  */
+/* ==================================================================== */
+
+#define SH_IOI_ACCESS                            0x0000000110060400
+#define SH_IOI_ACCESS_MASK                       0xffffffffffffffff
+#define SH_IOI_ACCESS_INIT                       0xffffffffffffffff
+
+/*   SH_IOI_ACCESS_ACCESS_BITS                                          */
+/*   Description:  Access Bits                                          */
+#define SH_IOI_ACCESS_ACCESS_BITS_SHFT           0
+#define SH_IOI_ACCESS_ACCESS_BITS_MASK           0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#define SH_IPI_ACCESS                            0x0000000110060480
+#define SH_IPI_ACCESS_MASK                       0xffffffffffffffff
+#define SH_IPI_ACCESS_INIT                       0xffffffffffffffff
+
+/*   SH_IPI_ACCESS_ACCESS_BITS                                          */
+/*   Description:  Access Bits                                          */
+#define SH_IPI_ACCESS_ACCESS_BITS_SHFT           0
+#define SH_IPI_ACCESS_ACCESS_BITS_MASK           0xffffffffffffffff
+
+/* ==================================================================== */
+/*                      Register "SH_JTAG_CONFIG"                       */
+/*                       SHub JTAG configuration                        */
+/* ==================================================================== */
+
+#define SH_JTAG_CONFIG                           0x0000000110060500
+#define SH_JTAG_CONFIG_MASK                      0x00ffffffffffffff
+#define SH_JTAG_CONFIG_INIT                      0x0000000000000000
+
+/*   SH_JTAG_CONFIG_MD_CLK_SEL                                          */
+/*   Description:  Select divide freq of DRAMCLK                        */
+#define SH_JTAG_CONFIG_MD_CLK_SEL_SHFT           0
+#define SH_JTAG_CONFIG_MD_CLK_SEL_MASK           0x0000000000000003
+
+/*   SH_JTAG_CONFIG_NI_CLK_SEL                                          */
+/*   Description:  Selects clock source for NICLK domain                */
+#define SH_JTAG_CONFIG_NI_CLK_SEL_SHFT           2
+#define SH_JTAG_CONFIG_NI_CLK_SEL_MASK           0x0000000000000004
+
+/*   SH_JTAG_CONFIG_II_CLK_SEL                                          */
+/*   Description:  Selects clock source for IOCLK domain                */
+#define SH_JTAG_CONFIG_II_CLK_SEL_SHFT           3
+#define SH_JTAG_CONFIG_II_CLK_SEL_MASK           0x0000000000000018
+
+/*   SH_JTAG_CONFIG_WRT90_TARGET                                        */
+/*   Description:  wrt90_target                                         */
+#define SH_JTAG_CONFIG_WRT90_TARGET_SHFT         5
+#define SH_JTAG_CONFIG_WRT90_TARGET_MASK         0x000000000007ffe0
+
+/*   SH_JTAG_CONFIG_WRT90_OVERRIDER                                     */
+/*   Description:  wrt90_overrideR                                      */
+#define SH_JTAG_CONFIG_WRT90_OVERRIDER_SHFT      19
+#define SH_JTAG_CONFIG_WRT90_OVERRIDER_MASK      0x0000000000080000
+
+/*   SH_JTAG_CONFIG_WRT90_OVERRIDE                                      */
+/*   Description:  wrt90_override                                       */
+#define SH_JTAG_CONFIG_WRT90_OVERRIDE_SHFT       20
+#define SH_JTAG_CONFIG_WRT90_OVERRIDE_MASK       0x0000000000100000
+
+/*   SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY                                */
+/*   Description:  jtag_mci_reset_delay                                 */
+#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_SHFT 21
+#define SH_JTAG_CONFIG_JTAG_MCI_RESET_DELAY_MASK 0x0000000001e00000
+
+/*   SH_JTAG_CONFIG_JTAG_MCI_TARGET                                     */
+/*   Description:  jtag_mci_target                                      */
+#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_SHFT      25
+#define SH_JTAG_CONFIG_JTAG_MCI_TARGET_MASK      0x0000007ffe000000
+
+/*   SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE                                   */
+/*   Description:  jtag_mci_override                                    */
+#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_SHFT    39
+#define SH_JTAG_CONFIG_JTAG_MCI_OVERRIDE_MASK    0x0000008000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH                                */
+/*   Description:  0=depth 8, 1=depth1                                  */
+#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_SHFT 40
+#define SH_JTAG_CONFIG_FSB_CONFIG_IOQ_DEPTH_MASK 0x0000010000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT                             */
+/*   Description:  Enable sampling of BINIT                             */
+#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_SHFT 41
+#define SH_JTAG_CONFIG_FSB_CONFIG_SAMPLE_BINIT_MASK 0x0000020000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING                       */
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_SHFT 42
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BUS_PARKING_MASK 0x0000040000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO                              */
+#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_SHFT 43
+#define SH_JTAG_CONFIG_FSB_CONFIG_CLOCK_RATIO_MASK 0x0000f80000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE                          */
+/*   Description:  Output tristate control                              */
+#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_SHFT 48
+#define SH_JTAG_CONFIG_FSB_CONFIG_OUTPUT_TRISTATE_MASK 0x000f000000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST                              */
+/*   Description:  Enables BIST                                         */
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_SHFT 52
+#define SH_JTAG_CONFIG_FSB_CONFIG_ENABLE_BIST_MASK 0x0010000000000000
+
+/*   SH_JTAG_CONFIG_FSB_CONFIG_AUX                                      */
+/*   Description:  Enables BIST                                         */
+#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_SHFT       53
+#define SH_JTAG_CONFIG_FSB_CONFIG_AUX_MASK       0x0060000000000000
+
+/*   SH_JTAG_CONFIG_GTL_CONFIG_RE                                       */
+/*   Description:  Reference Enable selection for GTL io                */
+#define SH_JTAG_CONFIG_GTL_CONFIG_RE_SHFT        55
+#define SH_JTAG_CONFIG_GTL_CONFIG_RE_MASK        0x0080000000000000
+
+/* ==================================================================== */
+/*                        Register "SH_SHUB_ID"                         */
+/*                            SHub ID Number                            */
+/* ==================================================================== */
+
+#define SH_SHUB_ID                               0x0000000110060580
+#define SH_SHUB_ID_MASK                          0x011f37ffffffffff
+#define SH_SHUB_ID_INIT                          0x0010300000000000
+
+/*   SH_SHUB_ID_FORCE1                                                  */
+/*   Description:  Must be 1                                            */
+#define SH_SHUB_ID_FORCE1_SHFT                   0
+#define SH_SHUB_ID_FORCE1_MASK                   0x0000000000000001
+
+/*   SH_SHUB_ID_MANUFACTURER                                            */
+/*   Description:  Manufacturer                                         */
+#define SH_SHUB_ID_MANUFACTURER_SHFT             1
+#define SH_SHUB_ID_MANUFACTURER_MASK             0x0000000000000ffe
+
+/*   SH_SHUB_ID_PART_NUMBER                                             */
+/*   Description:  Part Number                                          */
+#define SH_SHUB_ID_PART_NUMBER_SHFT              12
+#define SH_SHUB_ID_PART_NUMBER_MASK              0x000000000ffff000
+
+/*   SH_SHUB_ID_REVISION                                                */
+/*   Description:  Revision                                             */
+#define SH_SHUB_ID_REVISION_SHFT                 28
+#define SH_SHUB_ID_REVISION_MASK                 0x00000000f0000000
+
+/*   SH_SHUB_ID_NODE_ID                                                 */
+/*   Description:  Node Identification                                  */
+#define SH_SHUB_ID_NODE_ID_SHFT                  32
+#define SH_SHUB_ID_NODE_ID_MASK                  0x000007ff00000000
+
+/*   SH_SHUB_ID_SHARING_MODE                                            */
+/*   Description:  Sharing mode (Coherency Domain Size)                 */
+#define SH_SHUB_ID_SHARING_MODE_SHFT             44
+#define SH_SHUB_ID_SHARING_MODE_MASK             0x0000300000000000
+
+/*   SH_SHUB_ID_NODES_PER_BIT                                           */
+/*   Description:  Nodes per bit definition for MMR access              */
+#define SH_SHUB_ID_NODES_PER_BIT_SHFT            48
+#define SH_SHUB_ID_NODES_PER_BIT_MASK            0x001f000000000000
+
+/*   SH_SHUB_ID_NI_PORT                                                 */
+/*   Description:  NI port of vector reference, 0 = NI0, 1 = NI1        */
+#define SH_SHUB_ID_NI_PORT_SHFT                  56
+#define SH_SHUB_ID_NI_PORT_MASK                  0x0100000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT0"                     */
+/*         Shubs 0 - 63 Present. Used for invalidate generation         */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT0                        0x0000000110060600
+#define SH_SHUBS_PRESENT0_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT0_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT0_SHUBS_PRESENT0                                   */
+/*   Description:  Shubs 0 - 63 Present configuration                   */
+#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_SHFT    0
+#define SH_SHUBS_PRESENT0_SHUBS_PRESENT0_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT1"                     */
+/*        Shubs 64 - 127 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT1                        0x0000000110060680
+#define SH_SHUBS_PRESENT1_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT1_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT1_SHUBS_PRESENT1                                   */
+/*   Description:  Shubs 64 - 127 Present configuration                 */
+#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_SHFT    0
+#define SH_SHUBS_PRESENT1_SHUBS_PRESENT1_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT2"                     */
+/*       Shubs 128 - 191 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT2                        0x0000000110060700
+#define SH_SHUBS_PRESENT2_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT2_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT2_SHUBS_PRESENT2                                   */
+/*   Description:  Shubs 128 - 191 Present configuration                */
+#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_SHFT    0
+#define SH_SHUBS_PRESENT2_SHUBS_PRESENT2_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT3"                     */
+/*       Shubs 192 - 255 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#define SH_SHUBS_PRESENT3                        0x0000000110060780
+#define SH_SHUBS_PRESENT3_MASK                   0xffffffffffffffff
+#define SH_SHUBS_PRESENT3_INIT                   0xffffffffffffffff
+
+/*   SH_SHUBS_PRESENT3_SHUBS_PRESENT3                                   */
+/*   Description:  Shubs 192 - 255 Present configuration                */
+#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_SHFT    0
+#define SH_SHUBS_PRESENT3_SHUBS_PRESENT3_MASK    0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_SOFT_RESET"                       */
+/*                           SHub Soft Reset                            */
+/* ==================================================================== */
+
+#define SH_SOFT_RESET                            0x0000000110060800
+#define SH_SOFT_RESET_MASK                       0x0000000000000001
+#define SH_SOFT_RESET_INIT                       0x0000000000000000
+
+/*   SH_SOFT_RESET_SOFT_RESET                                           */
+/*   Description:  Soft Reset                                           */
+#define SH_SOFT_RESET_SOFT_RESET_SHFT            0
+#define SH_SOFT_RESET_SOFT_RESET_MASK            0x0000000000000001
+
+/* ==================================================================== */
+/*                      Register "SH_FIRST_ERROR"                       */
+/*                    Shub Global First Error Flags                     */
+/* ==================================================================== */
+
+#define SH_FIRST_ERROR                           0x0000000110071000
+#define SH_FIRST_ERROR_MASK                      0x000000000007ffff
+#define SH_FIRST_ERROR_INIT                      0x0000000000000000
+
+/*   SH_FIRST_ERROR_FIRST_ERROR                                         */
+/*   Description:  Chiplet with first error                             */
+#define SH_FIRST_ERROR_FIRST_ERROR_SHFT          0
+#define SH_FIRST_ERROR_FIRST_ERROR_MASK          0x000000000007ffff
+
+/* ==================================================================== */
+/*                    Register "SH_II_HW_TIME_STAMP"                    */
+/*                     II hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_II_HW_TIME_STAMP                      0x0000000110071080
+#define SH_II_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_II_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_II_HW_TIME_STAMP_TIME                                           */
+/*   Description:  II hardware error time stamp                         */
+#define SH_II_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_II_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_II_HW_TIME_STAMP_VALID                                          */
+/*   Description:  II hardware error time stamp valid                   */
+#define SH_II_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_II_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_LB_HW_TIME_STAMP"                    */
+/*                     LB hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_LB_HW_TIME_STAMP                      0x0000000110071100
+#define SH_LB_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_LB_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_LB_HW_TIME_STAMP_TIME                                           */
+/*   Description:  LB hardware error time stamp                         */
+#define SH_LB_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_LB_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_LB_HW_TIME_STAMP_VALID                                          */
+/*   Description:  LB hardware error time stamp valid                   */
+#define SH_LB_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_LB_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_COR_TIME_STAMP"                    */
+/*                   MD correctable error time stamp                    */
+/* ==================================================================== */
+
+#define SH_MD_COR_TIME_STAMP                     0x0000000110071180
+#define SH_MD_COR_TIME_STAMP_MASK                0xffffffffffffffff
+#define SH_MD_COR_TIME_STAMP_INIT                0x0000000000000000
+
+/*   SH_MD_COR_TIME_STAMP_TIME                                          */
+/*   Description:  MD correctable error time stamp                      */
+#define SH_MD_COR_TIME_STAMP_TIME_SHFT           0
+#define SH_MD_COR_TIME_STAMP_TIME_MASK           0x7fffffffffffffff
+
+/*   SH_MD_COR_TIME_STAMP_VALID                                         */
+/*   Description:  MD correctable error time stamp valid                */
+#define SH_MD_COR_TIME_STAMP_VALID_SHFT          63
+#define SH_MD_COR_TIME_STAMP_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_HW_TIME_STAMP"                    */
+/*                     MD hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_MD_HW_TIME_STAMP                      0x0000000110071200
+#define SH_MD_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_MD_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_MD_HW_TIME_STAMP_TIME                                           */
+/*   Description:  MD hardware error time stamp                         */
+#define SH_MD_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_MD_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_MD_HW_TIME_STAMP_VALID                                          */
+/*   Description:  MD hardware error time stamp valid                   */
+#define SH_MD_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_MD_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_UNCOR_TIME_STAMP"                   */
+/*                  MD uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#define SH_MD_UNCOR_TIME_STAMP                   0x0000000110071280
+#define SH_MD_UNCOR_TIME_STAMP_MASK              0xffffffffffffffff
+#define SH_MD_UNCOR_TIME_STAMP_INIT              0x0000000000000000
+
+/*   SH_MD_UNCOR_TIME_STAMP_TIME                                        */
+/*   Description:  MD uncorrectable error time stamp                    */
+#define SH_MD_UNCOR_TIME_STAMP_TIME_SHFT         0
+#define SH_MD_UNCOR_TIME_STAMP_TIME_MASK         0x7fffffffffffffff
+
+/*   SH_MD_UNCOR_TIME_STAMP_VALID                                       */
+/*   Description:  MD uncorrectable error time stamp valid              */
+#define SH_MD_UNCOR_TIME_STAMP_VALID_SHFT        63
+#define SH_MD_UNCOR_TIME_STAMP_VALID_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PI_COR_TIME_STAMP"                    */
+/*                   PI correctable error time stamp                    */
+/* ==================================================================== */
+
+#define SH_PI_COR_TIME_STAMP                     0x0000000110071300
+#define SH_PI_COR_TIME_STAMP_MASK                0xffffffffffffffff
+#define SH_PI_COR_TIME_STAMP_INIT                0x0000000000000000
+
+/*   SH_PI_COR_TIME_STAMP_TIME                                          */
+/*   Description:  PI correctable error time stamp                      */
+#define SH_PI_COR_TIME_STAMP_TIME_SHFT           0
+#define SH_PI_COR_TIME_STAMP_TIME_MASK           0x7fffffffffffffff
+
+/*   SH_PI_COR_TIME_STAMP_VALID                                         */
+/*   Description:  PI correctable error time stamp valid                */
+#define SH_PI_COR_TIME_STAMP_VALID_SHFT          63
+#define SH_PI_COR_TIME_STAMP_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_PI_HW_TIME_STAMP"                    */
+/*                     PI hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_PI_HW_TIME_STAMP                      0x0000000110071380
+#define SH_PI_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_PI_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_PI_HW_TIME_STAMP_TIME                                           */
+/*   Description:  PI hardware error time stamp                         */
+#define SH_PI_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_PI_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_PI_HW_TIME_STAMP_VALID                                          */
+/*   Description:  PI hardware error time stamp valid                   */
+#define SH_PI_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_PI_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PI_UNCOR_TIME_STAMP"                   */
+/*                  PI uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#define SH_PI_UNCOR_TIME_STAMP                   0x0000000110071400
+#define SH_PI_UNCOR_TIME_STAMP_MASK              0xffffffffffffffff
+#define SH_PI_UNCOR_TIME_STAMP_INIT              0x0000000000000000
+
+/*   SH_PI_UNCOR_TIME_STAMP_TIME                                        */
+/*   Description:  PI uncorrectable error time stamp                    */
+#define SH_PI_UNCOR_TIME_STAMP_TIME_SHFT         0
+#define SH_PI_UNCOR_TIME_STAMP_TIME_MASK         0x7fffffffffffffff
+
+/*   SH_PI_UNCOR_TIME_STAMP_VALID                                       */
+/*   Description:  PI uncorrectable error time stamp valid              */
+#define SH_PI_UNCOR_TIME_STAMP_VALID_SHFT        63
+#define SH_PI_UNCOR_TIME_STAMP_VALID_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_TIME_STAMP"                  */
+/*                      Proc 0 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC0_ADV_TIME_STAMP                  0x0000000110071480
+#define SH_PROC0_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC0_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC0_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 0 advisory time stamp                      */
+#define SH_PROC0_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC0_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC0_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 0 advisory time stamp valid                */
+#define SH_PROC0_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC0_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_TIME_STAMP"                  */
+/*                       Proc 0 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC0_ERR_TIME_STAMP                  0x0000000110071500
+#define SH_PROC0_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC0_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC0_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 0 error time stamp                         */
+#define SH_PROC0_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC0_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC0_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 0 error time stamp valid                   */
+#define SH_PROC0_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC0_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_TIME_STAMP"                  */
+/*                      Proc 1 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC1_ADV_TIME_STAMP                  0x0000000110071580
+#define SH_PROC1_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC1_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC1_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 1 advisory time stamp                      */
+#define SH_PROC1_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC1_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC1_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 1 advisory time stamp valid                */
+#define SH_PROC1_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC1_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_TIME_STAMP"                  */
+/*                       Proc 1 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC1_ERR_TIME_STAMP                  0x0000000110071600
+#define SH_PROC1_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC1_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC1_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 1 error time stamp                         */
+#define SH_PROC1_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC1_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC1_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 1 error time stamp valid                   */
+#define SH_PROC1_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC1_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_TIME_STAMP"                  */
+/*                      Proc 2 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC2_ADV_TIME_STAMP                  0x0000000110071680
+#define SH_PROC2_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC2_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC2_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 2 advisory time stamp                      */
+#define SH_PROC2_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC2_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC2_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 2 advisory time stamp valid                */
+#define SH_PROC2_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC2_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_TIME_STAMP"                  */
+/*                       Proc 2 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC2_ERR_TIME_STAMP                  0x0000000110071700
+#define SH_PROC2_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC2_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC2_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 2 error time stamp                         */
+#define SH_PROC2_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC2_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC2_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 2 error time stamp valid                   */
+#define SH_PROC2_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC2_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_TIME_STAMP"                  */
+/*                      Proc 3 advisory time stamp                      */
+/* ==================================================================== */
+
+#define SH_PROC3_ADV_TIME_STAMP                  0x0000000110071780
+#define SH_PROC3_ADV_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC3_ADV_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC3_ADV_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 3 advisory time stamp                      */
+#define SH_PROC3_ADV_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC3_ADV_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC3_ADV_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 3 advisory time stamp valid                */
+#define SH_PROC3_ADV_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC3_ADV_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_TIME_STAMP"                  */
+/*                       Proc 3 error time stamp                        */
+/* ==================================================================== */
+
+#define SH_PROC3_ERR_TIME_STAMP                  0x0000000110071800
+#define SH_PROC3_ERR_TIME_STAMP_MASK             0xffffffffffffffff
+#define SH_PROC3_ERR_TIME_STAMP_INIT             0x0000000000000000
+
+/*   SH_PROC3_ERR_TIME_STAMP_TIME                                       */
+/*   Description:  Processor 3 error time stamp                         */
+#define SH_PROC3_ERR_TIME_STAMP_TIME_SHFT        0
+#define SH_PROC3_ERR_TIME_STAMP_TIME_MASK        0x7fffffffffffffff
+
+/*   SH_PROC3_ERR_TIME_STAMP_VALID                                      */
+/*   Description:  Processor 3 error time stamp valid                   */
+#define SH_PROC3_ERR_TIME_STAMP_VALID_SHFT       63
+#define SH_PROC3_ERR_TIME_STAMP_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_XN_COR_TIME_STAMP"                    */
+/*                   XN correctable error time stamp                    */
+/* ==================================================================== */
+
+#define SH_XN_COR_TIME_STAMP                     0x0000000110071880
+#define SH_XN_COR_TIME_STAMP_MASK                0xffffffffffffffff
+#define SH_XN_COR_TIME_STAMP_INIT                0x0000000000000000
+
+/*   SH_XN_COR_TIME_STAMP_TIME                                          */
+/*   Description:  XN correctable error time stamp                      */
+#define SH_XN_COR_TIME_STAMP_TIME_SHFT           0
+#define SH_XN_COR_TIME_STAMP_TIME_MASK           0x7fffffffffffffff
+
+/*   SH_XN_COR_TIME_STAMP_VALID                                         */
+/*   Description:  XN correctable error time stamp valid                */
+#define SH_XN_COR_TIME_STAMP_VALID_SHFT          63
+#define SH_XN_COR_TIME_STAMP_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_XN_HW_TIME_STAMP"                    */
+/*                     XN hardware error time stamp                     */
+/* ==================================================================== */
+
+#define SH_XN_HW_TIME_STAMP                      0x0000000110071900
+#define SH_XN_HW_TIME_STAMP_MASK                 0xffffffffffffffff
+#define SH_XN_HW_TIME_STAMP_INIT                 0x0000000000000000
+
+/*   SH_XN_HW_TIME_STAMP_TIME                                           */
+/*   Description:  XN hardware error time stamp                         */
+#define SH_XN_HW_TIME_STAMP_TIME_SHFT            0
+#define SH_XN_HW_TIME_STAMP_TIME_MASK            0x7fffffffffffffff
+
+/*   SH_XN_HW_TIME_STAMP_VALID                                          */
+/*   Description:  XN hardware error time stamp valid                   */
+#define SH_XN_HW_TIME_STAMP_VALID_SHFT           63
+#define SH_XN_HW_TIME_STAMP_VALID_MASK           0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_XN_UNCOR_TIME_STAMP"                   */
+/*                  XN uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#define SH_XN_UNCOR_TIME_STAMP                   0x0000000110071980
+#define SH_XN_UNCOR_TIME_STAMP_MASK              0xffffffffffffffff
+#define SH_XN_UNCOR_TIME_STAMP_INIT              0x0000000000000000
+
+/*   SH_XN_UNCOR_TIME_STAMP_TIME                                        */
+/*   Description:  XN uncorrectable error time stamp                    */
+#define SH_XN_UNCOR_TIME_STAMP_TIME_SHFT         0
+#define SH_XN_UNCOR_TIME_STAMP_TIME_MASK         0x7fffffffffffffff
+
+/*   SH_XN_UNCOR_TIME_STAMP_VALID                                       */
+/*   Description:  XN uncorrectable error time stamp valid              */
+#define SH_XN_UNCOR_TIME_STAMP_VALID_SHFT        63
+#define SH_XN_UNCOR_TIME_STAMP_VALID_MASK        0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_DEBUG_PORT"                       */
+/*                           SHub Debug Port                            */
+/* ==================================================================== */
+
+#define SH_DEBUG_PORT                            0x0000000110072000
+#define SH_DEBUG_PORT_MASK                       0x00000000ffffffff
+#define SH_DEBUG_PORT_INIT                       0x0000000000000000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE0                                        */
+/*   Description:  Debug port nibble 0                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE0_SHFT         0
+#define SH_DEBUG_PORT_DEBUG_NIBBLE0_MASK         0x000000000000000f
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE1                                        */
+/*   Description:  Debug port nibble 1                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE1_SHFT         4
+#define SH_DEBUG_PORT_DEBUG_NIBBLE1_MASK         0x00000000000000f0
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE2                                        */
+/*   Description:  Debug port nibble 2                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE2_SHFT         8
+#define SH_DEBUG_PORT_DEBUG_NIBBLE2_MASK         0x0000000000000f00
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE3                                        */
+/*   Description:  Debug port nibble 3                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE3_SHFT         12
+#define SH_DEBUG_PORT_DEBUG_NIBBLE3_MASK         0x000000000000f000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE4                                        */
+/*   Description:  Debug port nibble 4                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE4_SHFT         16
+#define SH_DEBUG_PORT_DEBUG_NIBBLE4_MASK         0x00000000000f0000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE5                                        */
+/*   Description:  Debug port nibble 5                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE5_SHFT         20
+#define SH_DEBUG_PORT_DEBUG_NIBBLE5_MASK         0x0000000000f00000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE6                                        */
+/*   Description:  Debug port nibble 6                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE6_SHFT         24
+#define SH_DEBUG_PORT_DEBUG_NIBBLE6_MASK         0x000000000f000000
+
+/*   SH_DEBUG_PORT_DEBUG_NIBBLE7                                        */
+/*   Description:  Debug port nibble 7                                  */
+#define SH_DEBUG_PORT_DEBUG_NIBBLE7_SHFT         28
+#define SH_DEBUG_PORT_DEBUG_NIBBLE7_MASK         0x00000000f0000000
+
+/* ==================================================================== */
+/*                     Register "SH_II_DEBUG_DATA"                      */
+/*                            II Debug Data                             */
+/* ==================================================================== */
+
+#define SH_II_DEBUG_DATA                         0x0000000110072080
+#define SH_II_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_II_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_II_DEBUG_DATA_II_DATA                                           */
+/*   Description:  II debug data                                        */
+#define SH_II_DEBUG_DATA_II_DATA_SHFT            0
+#define SH_II_DEBUG_DATA_II_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                   Register "SH_II_WRAP_DEBUG_DATA"                   */
+/*                      SHub II Wrapper Debug Data                      */
+/* ==================================================================== */
+
+#define SH_II_WRAP_DEBUG_DATA                    0x0000000110072100
+#define SH_II_WRAP_DEBUG_DATA_MASK               0x00000000ffffffff
+#define SH_II_WRAP_DEBUG_DATA_INIT               0x0000000000000000
+
+/*   SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA                                 */
+/*   Description:  II wrapper debug data                                */
+#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_SHFT  0
+#define SH_II_WRAP_DEBUG_DATA_II_WRAP_DATA_MASK  0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_LB_DEBUG_DATA"                      */
+/*                          SHub LB Debug Data                          */
+/* ==================================================================== */
+
+#define SH_LB_DEBUG_DATA                         0x0000000110072180
+#define SH_LB_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_LB_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_LB_DEBUG_DATA_LB_DATA                                           */
+/*   Description:  LB debug data                                        */
+#define SH_LB_DEBUG_DATA_LB_DATA_SHFT            0
+#define SH_LB_DEBUG_DATA_LB_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_MD_DEBUG_DATA"                      */
+/*                          SHub MD Debug Data                          */
+/* ==================================================================== */
+
+#define SH_MD_DEBUG_DATA                         0x0000000110072200
+#define SH_MD_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_MD_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_MD_DEBUG_DATA_MD_DATA                                           */
+/*   Description:  MD debug data                                        */
+#define SH_MD_DEBUG_DATA_MD_DATA_SHFT            0
+#define SH_MD_DEBUG_DATA_MD_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_PI_DEBUG_DATA"                      */
+/*                          SHub PI Debug Data                          */
+/* ==================================================================== */
+
+#define SH_PI_DEBUG_DATA                         0x0000000110072280
+#define SH_PI_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_PI_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_PI_DEBUG_DATA_PI_DATA                                           */
+/*   Description:  PI Debug Data                                        */
+#define SH_PI_DEBUG_DATA_PI_DATA_SHFT            0
+#define SH_PI_DEBUG_DATA_PI_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_XN_DEBUG_DATA"                      */
+/*                          SHub XN Debug Data                          */
+/* ==================================================================== */
+
+#define SH_XN_DEBUG_DATA                         0x0000000110072300
+#define SH_XN_DEBUG_DATA_MASK                    0x00000000ffffffff
+#define SH_XN_DEBUG_DATA_INIT                    0x0000000000000000
+
+/*   SH_XN_DEBUG_DATA_XN_DATA                                           */
+/*   Description:  XN debug data                                        */
+#define SH_XN_DEBUG_DATA_XN_DATA_SHFT            0
+#define SH_XN_DEBUG_DATA_XN_DATA_MASK            0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_ARMED_STATE"                     */
+/*                Trigger sequencing facility arm state                 */
+/* ==================================================================== */
+
+#define SH_TSF_ARMED_STATE                       0x0000000110073000
+#define SH_TSF_ARMED_STATE_MASK                  0x00000000000000ff
+#define SH_TSF_ARMED_STATE_INIT                  0x0000000000000000
+
+/*   SH_TSF_ARMED_STATE_STATE                                           */
+/*   Description:  Trigger sequencing facility armed state              */
+#define SH_TSF_ARMED_STATE_STATE_SHFT            0
+#define SH_TSF_ARMED_STATE_STATE_MASK            0x00000000000000ff
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_COUNTER_VALUE"                    */
+/*              Trigger sequencing facility counter value               */
+/* ==================================================================== */
+
+#define SH_TSF_COUNTER_VALUE                     0x0000000110073080
+#define SH_TSF_COUNTER_VALUE_MASK                0xffffffffffffffff
+#define SH_TSF_COUNTER_VALUE_INIT                0x0000000000000000
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_32                                      */
+/*   Description:  Trigger sequencing facility counter 32               */
+#define SH_TSF_COUNTER_VALUE_COUNT_32_SHFT       0
+#define SH_TSF_COUNTER_VALUE_COUNT_32_MASK       0x00000000ffffffff
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_16                                      */
+/*   Description:  Trigger sequencing facility counter 16               */
+#define SH_TSF_COUNTER_VALUE_COUNT_16_SHFT       32
+#define SH_TSF_COUNTER_VALUE_COUNT_16_MASK       0x0000ffff00000000
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_8B                                      */
+/*   Description:  Trigger sequencing facility counter 8b               */
+#define SH_TSF_COUNTER_VALUE_COUNT_8B_SHFT       48
+#define SH_TSF_COUNTER_VALUE_COUNT_8B_MASK       0x00ff000000000000
+
+/*   SH_TSF_COUNTER_VALUE_COUNT_8A                                      */
+/*   Description:  Trigger sequencing facility counter 8a               */
+#define SH_TSF_COUNTER_VALUE_COUNT_8A_SHFT       56
+#define SH_TSF_COUNTER_VALUE_COUNT_8A_MASK       0xff00000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_TRIGGERED_STATE"                   */
+/*             Trigger sequencing facility triggered state              */
+/* ==================================================================== */
+
+#define SH_TSF_TRIGGERED_STATE                   0x0000000110073100
+#define SH_TSF_TRIGGERED_STATE_MASK              0x00000000000000ff
+#define SH_TSF_TRIGGERED_STATE_INIT              0x0000000000000000
+
+/*   SH_TSF_TRIGGERED_STATE_STATE                                       */
+/*   Description:  Trigger sequencing facility triggered state          */
+#define SH_TSF_TRIGGERED_STATE_STATE_SHFT        0
+#define SH_TSF_TRIGGERED_STATE_STATE_MASK        0x00000000000000ff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RDDATA"                       */
+/*                      Vector Reply Message Data                       */
+/* ==================================================================== */
+
+#define SH_VEC_RDDATA                            0x0000000110074000
+#define SH_VEC_RDDATA_MASK                       0xffffffffffffffff
+#define SH_VEC_RDDATA_INIT                       0x0000000000000000
+
+/*   SH_VEC_RDDATA_DATA                                                 */
+/*   Description:  Data                                                 */
+#define SH_VEC_RDDATA_DATA_SHFT                  0
+#define SH_VEC_RDDATA_DATA_MASK                  0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RETURN"                       */
+/*                  Vector Reply Message Return Route                   */
+/* ==================================================================== */
+
+#define SH_VEC_RETURN                            0x0000000110074080
+#define SH_VEC_RETURN_MASK                       0xffffffffffffffff
+#define SH_VEC_RETURN_INIT                       0x0000000000000000
+
+/*   SH_VEC_RETURN_ROUTE                                                */
+/*   Description:  Route                                                */
+#define SH_VEC_RETURN_ROUTE_SHFT                 0
+#define SH_VEC_RETURN_ROUTE_MASK                 0xffffffffffffffff
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_STATUS"                       */
+/*                     Vector Reply Message Status                      */
+/* ==================================================================== */
+
+#define SH_VEC_STATUS                            0x0000000110074100
+#define SH_VEC_STATUS_MASK                       0xcfffffffffffffff
+#define SH_VEC_STATUS_INIT                       0x0000000000000000
+
+/*   SH_VEC_STATUS_TYPE                                                 */
+/*   Description:  Type                                                 */
+#define SH_VEC_STATUS_TYPE_SHFT                  0
+#define SH_VEC_STATUS_TYPE_MASK                  0x0000000000000007
+
+/*   SH_VEC_STATUS_ADDRESS                                              */
+/*   Description:  Address                                              */
+#define SH_VEC_STATUS_ADDRESS_SHFT               3
+#define SH_VEC_STATUS_ADDRESS_MASK               0x00000007fffffff8
+
+/*   SH_VEC_STATUS_PIO_ID                                               */
+/*   Description:  PIO ID                                               */
+#define SH_VEC_STATUS_PIO_ID_SHFT                35
+#define SH_VEC_STATUS_PIO_ID_MASK                0x00003ff800000000
+
+/*   SH_VEC_STATUS_SOURCE                                               */
+/*   Description:  Source                                               */
+#define SH_VEC_STATUS_SOURCE_SHFT                46
+#define SH_VEC_STATUS_SOURCE_MASK                0x0fffc00000000000
+
+/*   SH_VEC_STATUS_OVERRUN                                              */
+/*   Description:  Overrun                                              */
+#define SH_VEC_STATUS_OVERRUN_SHFT               62
+#define SH_VEC_STATUS_OVERRUN_MASK               0x4000000000000000
+
+/*   SH_VEC_STATUS_STATUS_VALID                                         */
+/*   Description:  Status_Valid                                         */
+#define SH_VEC_STATUS_STATUS_VALID_SHFT          63
+#define SH_VEC_STATUS_STATUS_VALID_MASK          0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_VEC_STATUS_ALIAS"                    */
+/*                  Vector Reply Message Status Alias                   */
+/* ==================================================================== */
+
+#define SH_VEC_STATUS_ALIAS                      0x0000000110074108
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT0_CONTROL"               */
+/*                    Performance Counter 0 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT0_CONTROL            0x0000000110080000
+#define SH_PERFORMANCE_COUNT0_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT0_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 0 up stimulus                                */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 0 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 0 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE                              */
+/*   Description:  Counter 0 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT0_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 0 down stimulus                              */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 0 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 0 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE                              */
+/*   Description:  Counter 0 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT0_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 0 enable increment                           */
+#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT0_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 0 enable decrement                           */
+#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT0_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 0 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT0_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT1_CONTROL"               */
+/*                    Performance Counter 1 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT1_CONTROL            0x0000000110090000
+#define SH_PERFORMANCE_COUNT1_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT1_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 1 up stimulus                                */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 1 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 1 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE                              */
+/*   Description:  Counter 1 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT1_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 1 down stimulus                              */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 1 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 1 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE                              */
+/*   Description:  Counter 1 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT1_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 1 enable increment                           */
+#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT1_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 1 enable decrement                           */
+#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT1_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 1 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT1_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT2_CONTROL"               */
+/*                    Performance Counter 2 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT2_CONTROL            0x00000001100a0000
+#define SH_PERFORMANCE_COUNT2_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT2_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 2 up stimulus                                */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 2 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 2 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE                              */
+/*   Description:  Counter 2 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT2_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 2 down stimulus                              */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 2 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 2 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE                              */
+/*   Description:  Counter 2 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT2_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 2 enable increment                           */
+#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT2_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 2 enable decrement                           */
+#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT2_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 2 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT2_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT3_CONTROL"               */
+/*                    Performance Counter 3 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT3_CONTROL            0x00000001100b0000
+#define SH_PERFORMANCE_COUNT3_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT3_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 3 up stimulus                                */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 3 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 3 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE                              */
+/*   Description:  Counter 3 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT3_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 3 down stimulus                              */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 3 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 3 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE                              */
+/*   Description:  Counter 3 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT3_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 3 enable increment                           */
+#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT3_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 3 enable decrement                           */
+#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT3_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 3 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT3_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT4_CONTROL"               */
+/*                    Performance Counter 4 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT4_CONTROL            0x00000001100c0000
+#define SH_PERFORMANCE_COUNT4_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT4_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 4 up stimulus                                */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 4 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 4 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE                              */
+/*   Description:  Counter 4 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT4_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 4 down stimulus                              */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 4 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 4 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE                              */
+/*   Description:  Counter 4 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT4_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 4 enable increment                           */
+#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT4_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 4 enable decrement                           */
+#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT4_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 4 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT4_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT5_CONTROL"               */
+/*                    Performance Counter 5 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT5_CONTROL            0x00000001100d0000
+#define SH_PERFORMANCE_COUNT5_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT5_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 5 up stimulus                                */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 5 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 5 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE                              */
+/*   Description:  Counter 5 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT5_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 5 down stimulus                              */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 5 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 5 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE                              */
+/*   Description:  Counter 5 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT5_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 5 enable increment                           */
+#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT5_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 5 enable decrement                           */
+#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT5_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 5 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT5_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT6_CONTROL"               */
+/*                    Performance Counter 6 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT6_CONTROL            0x00000001100e0000
+#define SH_PERFORMANCE_COUNT6_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT6_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 6 up stimulus                                */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 6 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 6 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE                              */
+/*   Description:  Counter 6 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT6_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 6 down stimulus                              */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 6 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 6 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE                              */
+/*   Description:  Counter 6 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT6_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 6 enable increment                           */
+#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT6_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 6 enable decrement                           */
+#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT6_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 6 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT6_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT7_CONTROL"               */
+/*                    Performance Counter 7 Control                     */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNT7_CONTROL            0x00000001100f0000
+#define SH_PERFORMANCE_COUNT7_CONTROL_MASK       0x000000000007ffff
+#define SH_PERFORMANCE_COUNT7_CONTROL_INIT       0x000000000000b8b8
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS                          */
+/*   Description:  Counter 7 up stimulus                                */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_SHFT 0
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_STIMULUS_MASK 0x000000000000001f
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT                             */
+/*   Description:  Counter 7 up event select (1-greater than, 0-equal)  */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_SHFT 5
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_EVENT_MASK 0x0000000000000020
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY                          */
+/*   Description:  Counter 7 up polarity select (1-negative edge, 0-po  */
+/*  sitive edge)                                                        */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_SHFT 6
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_POLARITY_MASK 0x0000000000000040
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE                              */
+/*   Description:  Counter 7 up mode select (1-internal, 0-external)    */
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_SHFT 7
+#define SH_PERFORMANCE_COUNT7_CONTROL_UP_MODE_MASK 0x0000000000000080
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS                          */
+/*   Description:  Counter 7 down stimulus                              */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_SHFT 8
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_STIMULUS_MASK 0x0000000000001f00
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT                             */
+/*   Description:  Counter 7 down event select (1-greater than, 0-equa  */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_SHFT 13
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_EVENT_MASK 0x0000000000002000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY                          */
+/*   Description:  Counter 7 down polarity select (1-negative edge, 0-  */
+/*  positive edge)                                                      */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_SHFT 14
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_POLARITY_MASK 0x0000000000004000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE                              */
+/*   Description:  Counter 7 down mode select (1-internal, 0-external)  */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_SHFT 15
+#define SH_PERFORMANCE_COUNT7_CONTROL_DN_MODE_MASK 0x0000000000008000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE                           */
+/*   Description:  Counter 7 enable increment                           */
+#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_SHFT 16
+#define SH_PERFORMANCE_COUNT7_CONTROL_INC_ENABLE_MASK 0x0000000000010000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE                           */
+/*   Description:  Counter 7 enable decrement                           */
+#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_SHFT 17
+#define SH_PERFORMANCE_COUNT7_CONTROL_DEC_ENABLE_MASK 0x0000000000020000
+
+/*   SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE                      */
+/*   Description:  Counter 7 enable peak detection                      */
+#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_SHFT 18
+#define SH_PERFORMANCE_COUNT7_CONTROL_PEAK_DET_ENABLE_MASK 0x0000000000040000
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_DN_CONTROL"                   */
+/*                     Profile Counter Down Control                     */
+/* ==================================================================== */
+
+#define SH_PROFILE_DN_CONTROL                    0x0000000110100000
+#define SH_PROFILE_DN_CONTROL_MASK               0x00000000000000ff
+#define SH_PROFILE_DN_CONTROL_INIT               0x00000000000000b8
+
+/*   SH_PROFILE_DN_CONTROL_STIMULUS                                     */
+/*   Description:  Counter stimulus                                     */
+#define SH_PROFILE_DN_CONTROL_STIMULUS_SHFT      0
+#define SH_PROFILE_DN_CONTROL_STIMULUS_MASK      0x000000000000001f
+
+/*   SH_PROFILE_DN_CONTROL_EVENT                                        */
+/*   Description:  Counter event select (1-greater than, 0-equal)       */
+#define SH_PROFILE_DN_CONTROL_EVENT_SHFT         5
+#define SH_PROFILE_DN_CONTROL_EVENT_MASK         0x0000000000000020
+
+/*   SH_PROFILE_DN_CONTROL_POLARITY                                     */
+/*   Description:  Counter polarity select (1-negative edge, 0-positiv  */
+/*  e edge)                                                             */
+#define SH_PROFILE_DN_CONTROL_POLARITY_SHFT      6
+#define SH_PROFILE_DN_CONTROL_POLARITY_MASK      0x0000000000000040
+
+/*   SH_PROFILE_DN_CONTROL_MODE                                         */
+/*   Description:  Counter mode select (1-internal, 0-external)         */
+#define SH_PROFILE_DN_CONTROL_MODE_SHFT          7
+#define SH_PROFILE_DN_CONTROL_MODE_MASK          0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_PROFILE_PEAK_CONTROL"                  */
+/*                     Profile Counter Peak Control                     */
+/* ==================================================================== */
+
+#define SH_PROFILE_PEAK_CONTROL                  0x0000000110100080
+#define SH_PROFILE_PEAK_CONTROL_MASK             0x0000000000000068
+#define SH_PROFILE_PEAK_CONTROL_INIT             0x0000000000000060
+
+/*   SH_PROFILE_PEAK_CONTROL_STIMULUS                                   */
+/*   Description:  Counter stimulus                                     */
+#define SH_PROFILE_PEAK_CONTROL_STIMULUS_SHFT    3
+#define SH_PROFILE_PEAK_CONTROL_STIMULUS_MASK    0x0000000000000008
+
+/*   SH_PROFILE_PEAK_CONTROL_EVENT                                      */
+/*   Description:  Counter event select (0-greater than, 1-equal)       */
+#define SH_PROFILE_PEAK_CONTROL_EVENT_SHFT       5
+#define SH_PROFILE_PEAK_CONTROL_EVENT_MASK       0x0000000000000020
+
+/*   SH_PROFILE_PEAK_CONTROL_POLARITY                                   */
+/*   Description:  Counter polarity select (0-negative edge, 1-positiv  */
+/*  e edge)                                                             */
+#define SH_PROFILE_PEAK_CONTROL_POLARITY_SHFT    6
+#define SH_PROFILE_PEAK_CONTROL_POLARITY_MASK    0x0000000000000040
+
+/* ==================================================================== */
+/*                     Register "SH_PROFILE_RANGE"                      */
+/*                        Profile Counter Range                         */
+/* ==================================================================== */
+
+#define SH_PROFILE_RANGE                         0x0000000110100100
+#define SH_PROFILE_RANGE_MASK                    0xffffffffffffffff
+#define SH_PROFILE_RANGE_INIT                    0x0000000000000000
+
+/*   SH_PROFILE_RANGE_RANGE0                                            */
+/*   Description:  Profiling range 0                                    */
+#define SH_PROFILE_RANGE_RANGE0_SHFT             0
+#define SH_PROFILE_RANGE_RANGE0_MASK             0x00000000000000ff
+
+/*   SH_PROFILE_RANGE_RANGE1                                            */
+/*   Description:  Profiling range 1                                    */
+#define SH_PROFILE_RANGE_RANGE1_SHFT             8
+#define SH_PROFILE_RANGE_RANGE1_MASK             0x000000000000ff00
+
+/*   SH_PROFILE_RANGE_RANGE2                                            */
+/*   Description:  Profiling range 2                                    */
+#define SH_PROFILE_RANGE_RANGE2_SHFT             16
+#define SH_PROFILE_RANGE_RANGE2_MASK             0x0000000000ff0000
+
+/*   SH_PROFILE_RANGE_RANGE3                                            */
+/*   Description:  Profiling range 3                                    */
+#define SH_PROFILE_RANGE_RANGE3_SHFT             24
+#define SH_PROFILE_RANGE_RANGE3_MASK             0x00000000ff000000
+
+/*   SH_PROFILE_RANGE_RANGE4                                            */
+/*   Description:  Profiling range 4                                    */
+#define SH_PROFILE_RANGE_RANGE4_SHFT             32
+#define SH_PROFILE_RANGE_RANGE4_MASK             0x000000ff00000000
+
+/*   SH_PROFILE_RANGE_RANGE5                                            */
+/*   Description:  Profiling range 5                                    */
+#define SH_PROFILE_RANGE_RANGE5_SHFT             40
+#define SH_PROFILE_RANGE_RANGE5_MASK             0x0000ff0000000000
+
+/*   SH_PROFILE_RANGE_RANGE6                                            */
+/*   Description:  Profiling range 6                                    */
+#define SH_PROFILE_RANGE_RANGE6_SHFT             48
+#define SH_PROFILE_RANGE_RANGE6_MASK             0x00ff000000000000
+
+/*   SH_PROFILE_RANGE_RANGE7                                            */
+/*   Description:  Profiling range 7                                    */
+#define SH_PROFILE_RANGE_RANGE7_SHFT             56
+#define SH_PROFILE_RANGE_RANGE7_MASK             0xff00000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_UP_CONTROL"                   */
+/*                      Profile Counter Up Control                      */
+/* ==================================================================== */
+
+#define SH_PROFILE_UP_CONTROL                    0x0000000110100180
+#define SH_PROFILE_UP_CONTROL_MASK               0x00000000000000ff
+#define SH_PROFILE_UP_CONTROL_INIT               0x00000000000000b8
+
+/*   SH_PROFILE_UP_CONTROL_STIMULUS                                     */
+/*   Description:  Counter stimulus                                     */
+#define SH_PROFILE_UP_CONTROL_STIMULUS_SHFT      0
+#define SH_PROFILE_UP_CONTROL_STIMULUS_MASK      0x000000000000001f
+
+/*   SH_PROFILE_UP_CONTROL_EVENT                                        */
+/*   Description:  Counter event select (1-greater than, 0-equal)       */
+#define SH_PROFILE_UP_CONTROL_EVENT_SHFT         5
+#define SH_PROFILE_UP_CONTROL_EVENT_MASK         0x0000000000000020
+
+/*   SH_PROFILE_UP_CONTROL_POLARITY                                     */
+/*   Description:  Counter polarity select (1-negative edge, 0-positiv  */
+/*  e edge)                                                             */
+#define SH_PROFILE_UP_CONTROL_POLARITY_SHFT      6
+#define SH_PROFILE_UP_CONTROL_POLARITY_MASK      0x0000000000000040
+
+/*   SH_PROFILE_UP_CONTROL_MODE                                         */
+/*   Description:  Counter mode select (1-internal, 0-external)         */
+#define SH_PROFILE_UP_CONTROL_MODE_SHFT          7
+#define SH_PROFILE_UP_CONTROL_MODE_MASK          0x0000000000000080
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER0"                  */
+/*                        Performance Counter 0                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER0                  0x0000000110110000
+#define SH_PERFORMANCE_COUNTER0_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER0_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER0_COUNT                                      */
+/*   Description:  Counter 0                                            */
+#define SH_PERFORMANCE_COUNTER0_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER0_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER1"                  */
+/*                        Performance Counter 1                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER1                  0x0000000110120000
+#define SH_PERFORMANCE_COUNTER1_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER1_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER1_COUNT                                      */
+/*   Description:  Counter 1                                            */
+#define SH_PERFORMANCE_COUNTER1_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER1_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER2"                  */
+/*                        Performance Counter 2                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER2                  0x0000000110130000
+#define SH_PERFORMANCE_COUNTER2_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER2_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER2_COUNT                                      */
+/*   Description:  Counter 2                                            */
+#define SH_PERFORMANCE_COUNTER2_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER2_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER3"                  */
+/*                        Performance Counter 3                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER3                  0x0000000110140000
+#define SH_PERFORMANCE_COUNTER3_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER3_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER3_COUNT                                      */
+/*   Description:  Counter 3                                            */
+#define SH_PERFORMANCE_COUNTER3_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER3_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER4"                  */
+/*                        Performance Counter 4                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER4                  0x0000000110150000
+#define SH_PERFORMANCE_COUNTER4_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER4_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER4_COUNT                                      */
+/*   Description:  Counter 4                                            */
+#define SH_PERFORMANCE_COUNTER4_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER4_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER5"                  */
+/*                        Performance Counter 5                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER5                  0x0000000110160000
+#define SH_PERFORMANCE_COUNTER5_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER5_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER5_COUNT                                      */
+/*   Description:  Counter 5                                            */
+#define SH_PERFORMANCE_COUNTER5_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER5_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER6"                  */
+/*                        Performance Counter 6                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER6                  0x0000000110170000
+#define SH_PERFORMANCE_COUNTER6_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER6_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER6_COUNT                                      */
+/*   Description:  Counter 6                                            */
+#define SH_PERFORMANCE_COUNTER6_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER6_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER7"                  */
+/*                        Performance Counter 7                         */
+/* ==================================================================== */
+
+#define SH_PERFORMANCE_COUNTER7                  0x0000000110180000
+#define SH_PERFORMANCE_COUNTER7_MASK             0x00000000ffffffff
+#define SH_PERFORMANCE_COUNTER7_INIT             0x0000000000000000
+
+/*   SH_PERFORMANCE_COUNTER7_COUNT                                      */
+/*   Description:  Counter 7                                            */
+#define SH_PERFORMANCE_COUNTER7_COUNT_SHFT       0
+#define SH_PERFORMANCE_COUNTER7_COUNT_MASK       0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_PROFILE_COUNTER"                     */
+/*                           Profile Counter                            */
+/* ==================================================================== */
+
+#define SH_PROFILE_COUNTER                       0x0000000110190000
+#define SH_PROFILE_COUNTER_MASK                  0x00000000000000ff
+#define SH_PROFILE_COUNTER_INIT                  0x0000000000000000
+
+/*   SH_PROFILE_COUNTER_COUNTER                                         */
+/*   Description:  Counter Value                                        */
+#define SH_PROFILE_COUNTER_COUNTER_SHFT          0
+#define SH_PROFILE_COUNTER_COUNTER_MASK          0x00000000000000ff
+
+/* ==================================================================== */
+/*                      Register "SH_PROFILE_PEAK"                      */
+/*                         Profile Peak Counter                         */
+/* ==================================================================== */
+
+#define SH_PROFILE_PEAK                          0x0000000110190080
+#define SH_PROFILE_PEAK_MASK                     0x00000000000000ff
+#define SH_PROFILE_PEAK_INIT                     0x0000000000000000
+
+/*   SH_PROFILE_PEAK_COUNTER                                            */
+/*   Description:  Counter Value                                        */
+#define SH_PROFILE_PEAK_COUNTER_SHFT             0
+#define SH_PROFILE_PEAK_COUNTER_MASK             0x00000000000000ff
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_0"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#define SH_PTC_0                                 0x00000001101a0000
+#define SH_PTC_0_MASK                            0x80000000fffffffd
+#define SH_PTC_0_INIT                            0x0000000000000000
+
+/*   SH_PTC_0_A                                                         */
+/*   Description:  Type                                                 */
+#define SH_PTC_0_A_SHFT                          0
+#define SH_PTC_0_A_MASK                          0x0000000000000001
+
+/*   SH_PTC_0_PS                                                        */
+/*   Description:  Page Size                                            */
+#define SH_PTC_0_PS_SHFT                         2
+#define SH_PTC_0_PS_MASK                         0x00000000000000fc
+
+/*   SH_PTC_0_RID                                                       */
+/*   Description:  Region ID                                            */
+#define SH_PTC_0_RID_SHFT                        8
+#define SH_PTC_0_RID_MASK                        0x00000000ffffff00
+
+/*   SH_PTC_0_START                                                     */
+/*   Description:  Start                                                */
+#define SH_PTC_0_START_SHFT                      63
+#define SH_PTC_0_START_MASK                      0x8000000000000000
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_1"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#define SH_PTC_1                                 0x00000001101a0080
+#define SH_PTC_1_MASK                            0x9ffffffffffff000
+#define SH_PTC_1_INIT                            0x0000000000000000
+
+/*   SH_PTC_1_VPN                                                       */
+/*   Description:  Virtual page number                                  */
+#define SH_PTC_1_VPN_SHFT                        12
+#define SH_PTC_1_VPN_MASK                        0x1ffffffffffff000
+
+/*   SH_PTC_1_START                                                     */
+/*   Description:  PTC_1 Start                                          */
+#define SH_PTC_1_START_SHFT                      63
+#define SH_PTC_1_START_MASK                      0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_PTC_PARMS"                        */
+/*                       PTC Time-out parmaeters                        */
+/* ==================================================================== */
+
+#define SH_PTC_PARMS                             0x00000001101a0100
+#define SH_PTC_PARMS_MASK                        0x0000000fffffffff
+#define SH_PTC_PARMS_INIT                        0x00000007ffffffff
+
+/*   SH_PTC_PARMS_PTC_TO_WRAP                                           */
+/*   Description:  PTC time-out period                                  */
+#define SH_PTC_PARMS_PTC_TO_WRAP_SHFT            0
+#define SH_PTC_PARMS_PTC_TO_WRAP_MASK            0x0000000000ffffff
+
+/*   SH_PTC_PARMS_PTC_TO_VAL                                            */
+/*   Description:  PTC time-out valid                                   */
+#define SH_PTC_PARMS_PTC_TO_VAL_SHFT             24
+#define SH_PTC_PARMS_PTC_TO_VAL_MASK             0x0000000fff000000
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPA"                        */
+/*                  RTC Compare Value for Processor A                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPA                              0x00000001101b0000
+#define SH_INT_CMPA_MASK                         0x007fffffffffffff
+#define SH_INT_CMPA_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPA_REAL_TIME_CMPA                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPA_REAL_TIME_CMPA_SHFT          0
+#define SH_INT_CMPA_REAL_TIME_CMPA_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPB                              0x00000001101b0080
+#define SH_INT_CMPB_MASK                         0x007fffffffffffff
+#define SH_INT_CMPB_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPB_REAL_TIME_CMPB                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPB_REAL_TIME_CMPB_SHFT          0
+#define SH_INT_CMPB_REAL_TIME_CMPB_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPC                              0x00000001101b0100
+#define SH_INT_CMPC_MASK                         0x007fffffffffffff
+#define SH_INT_CMPC_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPC_REAL_TIME_CMPC                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPC_REAL_TIME_CMPC_SHFT          0
+#define SH_INT_CMPC_REAL_TIME_CMPC_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#define SH_INT_CMPD                              0x00000001101b0180
+#define SH_INT_CMPD_MASK                         0x007fffffffffffff
+#define SH_INT_CMPD_INIT                         0x0000000000000000
+
+/*   SH_INT_CMPD_REAL_TIME_CMPD                                         */
+/*   Description:  Real Time Clock Compare                              */
+#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT          0
+#define SH_INT_CMPD_REAL_TIME_CMPD_MASK          0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_INT_PROF"                        */
+/*                      Profile Compare Registers                       */
+/* ==================================================================== */
+
+#define SH_INT_PROF                              0x00000001101b0200
+#define SH_INT_PROF_MASK                         0x00000000ffffffff
+#define SH_INT_PROF_INIT                         0x0000000000000000
+
+/*   SH_INT_PROF_PROFILE_COMPARE                                        */
+/*   Description:  Profile Compare                                      */
+#define SH_INT_PROF_PROFILE_COMPARE_SHFT         0
+#define SH_INT_PROF_PROFILE_COMPARE_MASK         0x00000000ffffffff
+
+/* ==================================================================== */
+/*                          Register "SH_RTC"                           */
+/*                           Real-time Clock                            */
+/* ==================================================================== */
+
+#define SH_RTC                                   0x00000001101c0000
+#define SH_RTC_MASK                              0x007fffffffffffff
+#define SH_RTC_INIT                              0x0000000000000000
+
+/*   SH_RTC_REAL_TIME_CLOCK                                             */
+/*   Description:  Real-time Clock                                      */
+#define SH_RTC_REAL_TIME_CLOCK_SHFT              0
+#define SH_RTC_REAL_TIME_CLOCK_MASK              0x007fffffffffffff
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH0"                        */
+/*                          Scratch Register 0                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH0                              0x00000001101d0000
+#define SH_SCRATCH0_MASK                         0xffffffffffffffff
+#define SH_SCRATCH0_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH0_SCRATCH0                                               */
+/*   Description:  Scratch register 0                                   */
+#define SH_SCRATCH0_SCRATCH0_SHFT                0
+#define SH_SCRATCH0_SCRATCH0_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH0_ALIAS"                     */
+/*                   Scratch Register 0 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH0_ALIAS                        0x00000001101d0008
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH1"                        */
+/*                          Scratch Register 1                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH1                              0x00000001101d0080
+#define SH_SCRATCH1_MASK                         0xffffffffffffffff
+#define SH_SCRATCH1_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH1_SCRATCH1                                               */
+/*   Description:  Scratch register 1                                   */
+#define SH_SCRATCH1_SCRATCH1_SHFT                0
+#define SH_SCRATCH1_SCRATCH1_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH1_ALIAS"                     */
+/*                   Scratch Register 1 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH1_ALIAS                        0x00000001101d0088
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH2"                        */
+/*                          Scratch Register 2                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH2                              0x00000001101d0100
+#define SH_SCRATCH2_MASK                         0xffffffffffffffff
+#define SH_SCRATCH2_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH2_SCRATCH2                                               */
+/*   Description:  Scratch register 2                                   */
+#define SH_SCRATCH2_SCRATCH2_SHFT                0
+#define SH_SCRATCH2_SCRATCH2_MASK                0xffffffffffffffff
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH2_ALIAS"                     */
+/*                   Scratch Register 2 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH2_ALIAS                        0x00000001101d0108
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH3"                        */
+/*                          Scratch Register 3                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH3                              0x00000001101d0180
+#define SH_SCRATCH3_MASK                         0x0000000000000001
+#define SH_SCRATCH3_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH3_SCRATCH3                                               */
+/*   Description:  Scratch register 3                                   */
+#define SH_SCRATCH3_SCRATCH3_SHFT                0
+#define SH_SCRATCH3_SCRATCH3_MASK                0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH3_ALIAS"                     */
+/*                   Scratch Register 3 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH3_ALIAS                        0x00000001101d0188
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH4"                        */
+/*                          Scratch Register 4                          */
+/* ==================================================================== */
+
+#define SH_SCRATCH4                              0x00000001101d0200
+#define SH_SCRATCH4_MASK                         0x0000000000000001
+#define SH_SCRATCH4_INIT                         0x0000000000000000
+
+/*   SH_SCRATCH4_SCRATCH4                                               */
+/*   Description:  Scratch register 4                                   */
+#define SH_SCRATCH4_SCRATCH4_SHFT                0
+#define SH_SCRATCH4_SCRATCH4_MASK                0x0000000000000001
+
+/* ==================================================================== */
+/*                     Register "SH_SCRATCH4_ALIAS"                     */
+/*                   Scratch Register 4 Alias Address                   */
+/* ==================================================================== */
+
+#define SH_SCRATCH4_ALIAS                        0x00000001101d0208
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_MESSAGE_CONTROL"                   */
+/*               Coherent Request Buffer Message Control                */
+/* ==================================================================== */
+
+#define SH_CRB_MESSAGE_CONTROL                   0x0000000120000000
+#define SH_CRB_MESSAGE_CONTROL_MASK              0xffffffff00000fff
+#define SH_CRB_MESSAGE_CONTROL_INIT              0x0000000000000006
+
+/*   SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE                     */
+/*   Description:  System Coherence Enabled                             */
+#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_SHFT 0
+#define SH_CRB_MESSAGE_CONTROL_SYSTEM_COHERENCE_ENABLE_MASK 0x0000000000000001
+
+/*   SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE            */
+/*   Description:  Speculative Read Requests to Local Memory Enabled    */
+#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_SHFT 1
+#define SH_CRB_MESSAGE_CONTROL_LOCAL_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000002
+
+/*   SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE           */
+/*   Description:  Speculative Read Requests to Remote Memory Enabled  */
+#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_SHFT 2
+#define SH_CRB_MESSAGE_CONTROL_REMOTE_SPECULATIVE_MESSAGE_ENABLE_MASK 0x0000000000000004
+
+/*   SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR                               */
+/*   Description:  Define color of message                              */
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_SHFT 3
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_MASK 0x0000000000000008
+
+/*   SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE                        */
+/*   Description:  Enable color message processing                      */
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_SHFT 4
+#define SH_CRB_MESSAGE_CONTROL_MESSAGE_COLOR_ENABLE_MASK 0x0000000000000010
+
+/*   SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE           */
+/*   Description:  Enable FSB RRB Mismatch check                        */
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 5
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000020
+
+/*   SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE           */
+/*   Description:  Enable FSB WRB Mismatch check                        */
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 6
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000040
+
+/*   SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE           */
+/*   Description:  Enable FSB IRB Mismatch check                        */
+#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_SHFT 7
+#define SH_CRB_MESSAGE_CONTROL_IRB_ATTRIBUTE_MISMATCH_FSB_ENABLE_MASK 0x0000000000000080
+
+/*   SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE            */
+/*   Description:  Enable XB RRB Mismatch check                         */
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 8
+#define SH_CRB_MESSAGE_CONTROL_RRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000100
+
+/*   SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE            */
+/*   Description:  Enable XB WRB Mismatch check                         */
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_SHFT 9
+#define SH_CRB_MESSAGE_CONTROL_WRB_ATTRIBUTE_MISMATCH_XB_ENABLE_MASK 0x0000000000000200
+
+/*   SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES                       */
+/*   Description:  ignor residual write data                            */
+#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_SHFT 10
+#define SH_CRB_MESSAGE_CONTROL_SUPPRESS_BOGUS_WRITES_MASK 0x0000000000000400
+
+/*   SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION                  */
+/*   Description:  enable IVACK reply consolidation                     */
+#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_SHFT 11
+#define SH_CRB_MESSAGE_CONTROL_ENABLE_IVACK_CONSOLIDATION_MASK 0x0000000000000800
+
+/*   SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT                           */
+/*   Description:  IVACK stall counter                                  */
+#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_SHFT 32
+#define SH_CRB_MESSAGE_CONTROL_IVACK_STALL_COUNT_MASK 0x0000ffff00000000
+
+/*   SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL                      */
+/*   Description:  IVACK throttling limit/timer control                 */
+#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_SHFT 48
+#define SH_CRB_MESSAGE_CONTROL_IVACK_THROTTLE_CONTROL_MASK 0xffff000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_CRB_NACK_LIMIT"                     */
+/*                            CRB Nack Limit                            */
+/* ==================================================================== */
+
+#define SH_CRB_NACK_LIMIT                        0x0000000120000080
+#define SH_CRB_NACK_LIMIT_MASK                   0x800000000000ffff
+#define SH_CRB_NACK_LIMIT_INIT                   0x0000000000000000
+
+/*   SH_CRB_NACK_LIMIT_LIMIT                                            */
+/*   Description:  Nack Count Limit                                     */
+#define SH_CRB_NACK_LIMIT_LIMIT_SHFT             0
+#define SH_CRB_NACK_LIMIT_LIMIT_MASK             0x0000000000000fff
+
+/*   SH_CRB_NACK_LIMIT_PRI_FREQ                                         */
+/*   Description:  Frequency at which priority count is incremented     */
+#define SH_CRB_NACK_LIMIT_PRI_FREQ_SHFT          12
+#define SH_CRB_NACK_LIMIT_PRI_FREQ_MASK          0x000000000000f000
+
+/*   SH_CRB_NACK_LIMIT_ENABLE                                           */
+/*   Description:  Enable NACK limit detection                          */
+#define SH_CRB_NACK_LIMIT_ENABLE_SHFT            63
+#define SH_CRB_NACK_LIMIT_ENABLE_MASK            0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_TIMEOUT_PRESCALE"                  */
+/*               Coherent Request Buffer Timeout Prescale               */
+/* ==================================================================== */
+
+#define SH_CRB_TIMEOUT_PRESCALE                  0x0000000120000100
+#define SH_CRB_TIMEOUT_PRESCALE_MASK             0x00000000ffffffff
+#define SH_CRB_TIMEOUT_PRESCALE_INIT             0x0000000000000000
+
+/*   SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR                             */
+/*   Description:  CRB Time-out Prescale Factor                         */
+#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_SHFT 0
+#define SH_CRB_TIMEOUT_PRESCALE_SCALING_FACTOR_MASK 0x00000000ffffffff
+
+/* ==================================================================== */
+/*                    Register "SH_CRB_TIMEOUT_SKID"                    */
+/*              Coherent Request Buffer Timeout Skid Limit              */
+/* ==================================================================== */
+
+#define SH_CRB_TIMEOUT_SKID                      0x0000000120000180
+#define SH_CRB_TIMEOUT_SKID_MASK                 0x800000000000003f
+#define SH_CRB_TIMEOUT_SKID_INIT                 0x0000000000000007
+
+/*   SH_CRB_TIMEOUT_SKID_SKID                                           */
+/*   Description:  CRB Time-out Skid                                    */
+#define SH_CRB_TIMEOUT_SKID_SKID_SHFT            0
+#define SH_CRB_TIMEOUT_SKID_SKID_MASK            0x000000000000003f
+
+/*   SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT                               */
+/*   Description:  Reset Skid counter                                   */
+#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_SHFT 63
+#define SH_CRB_TIMEOUT_SKID_RESET_SKID_COUNT_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_0"                  */
+/*                    Memory Write Status for CPU 0                     */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_0                 0x0000000120070000
+#define SH_MEMORY_WRITE_STATUS_0_MASK            0x000000000000003f
+#define SH_MEMORY_WRITE_STATUS_0_INIT            0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT                       */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_1"                  */
+/*                    Memory Write Status for CPU 1                     */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_1                 0x0000000120070080
+#define SH_MEMORY_WRITE_STATUS_1_MASK            0x000000000000003f
+#define SH_MEMORY_WRITE_STATUS_1_INIT            0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT                       */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_0"                   */
+/*                      PIO Write Status for CPU 0                      */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_0                    0x0000000120070200
+#define SH_PIO_WRITE_STATUS_0_MASK               0xbf03ffffffffffff
+#define SH_PIO_WRITE_STATUS_0_INIT               0x8000000000000000
+
+/*   SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR                            */
+/*   Description:  More than one PIO write error occured                */
+#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_SHFT 0
+#define SH_PIO_WRITE_STATUS_0_MULTI_WRITE_ERROR_MASK 0x0000000000000001
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK                               */
+/*   Description:  Deaklock response detected                           */
+#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_SHFT 1
+#define SH_PIO_WRITE_STATUS_0_WRITE_DEADLOCK_MASK 0x0000000000000002
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_ERROR                                  */
+/*   Description:  Error response detected                              */
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_SHFT   2
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_MASK   0x0000000000000004
+
+/*   SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS                          */
+/*   Description:  Address associated with error response               */
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_SHFT 3
+#define SH_PIO_WRITE_STATUS_0_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8
+
+/*   SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT                          */
+/*   Description:  Count of currently pending PIO writes                */
+#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_SHFT 56
+#define SH_PIO_WRITE_STATUS_0_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
+
+/*   SH_PIO_WRITE_STATUS_0_WRITES_OK                                    */
+/*   Description:  No pending writes or errors                          */
+#define SH_PIO_WRITE_STATUS_0_WRITES_OK_SHFT     63
+#define SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK     0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_1"                   */
+/*                      PIO Write Status for CPU 1                      */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_1                    0x0000000120070280
+#define SH_PIO_WRITE_STATUS_1_MASK               0xbf03ffffffffffff
+#define SH_PIO_WRITE_STATUS_1_INIT               0x8000000000000000
+
+/*   SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR                            */
+/*   Description:  More than one PIO write error occured                */
+#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_SHFT 0
+#define SH_PIO_WRITE_STATUS_1_MULTI_WRITE_ERROR_MASK 0x0000000000000001
+
+/*   SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK                               */
+/*   Description:  Deaklock response detected                           */
+#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_SHFT 1
+#define SH_PIO_WRITE_STATUS_1_WRITE_DEADLOCK_MASK 0x0000000000000002
+
+/*   SH_PIO_WRITE_STATUS_1_WRITE_ERROR                                  */
+/*   Description:  Error response detected                              */
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_SHFT   2
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_MASK   0x0000000000000004
+
+/*   SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS                          */
+/*   Description:  Address associated with error response               */
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_SHFT 3
+#define SH_PIO_WRITE_STATUS_1_WRITE_ERROR_ADDRESS_MASK 0x0003fffffffffff8
+
+/*   SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT                          */
+/*   Description:  Count of currently pending PIO writes                */
+#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_SHFT 56
+#define SH_PIO_WRITE_STATUS_1_PENDING_WRITE_COUNT_MASK 0x3f00000000000000
+
+/*   SH_PIO_WRITE_STATUS_1_WRITES_OK                                    */
+/*   Description:  No pending writes or errors                          */
+#define SH_PIO_WRITE_STATUS_1_WRITES_OK_SHFT     63
+#define SH_PIO_WRITE_STATUS_1_WRITES_OK_MASK     0x8000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_PIO_WRITE_STATUS_0_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_0_ALIAS              0x0000000120070208
+
+/* ==================================================================== */
+/*                Register "SH_PIO_WRITE_STATUS_1_ALIAS"                */
+/* ==================================================================== */
+
+#define SH_PIO_WRITE_STATUS_1_ALIAS              0x0000000120070288
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_0"             */
+/*            Memory Write Status for CPU 0. OS access only             */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0        0x0000000120070400
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_MASK   0x800000000000003f
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_INIT   0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT              */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR                            */
+/*   Description:  Clear pending write count                            */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_SHFT 63
+#define SH_MEMORY_WRITE_STATUS_NON_USER_0_CLEAR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_1"             */
+/*            Memory Write Status for CPU 1. OS access only             */
+/* ==================================================================== */
+
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1        0x0000000120070480
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_MASK   0x800000000000003f
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_INIT   0x0000000000000000
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT              */
+/*   Description:  Pending Write Count                                  */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_SHFT 0
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_PENDING_WRITE_COUNT_MASK 0x000000000000003f
+
+/*   SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR                            */
+/*   Description:  Clear pending write count                            */
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_SHFT 63
+#define SH_MEMORY_WRITE_STATUS_NON_USER_1_CLEAR_MASK 0x8000000000000000
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_ERR"                       */
+/*                  Error capture for bist read errors                  */
+/* ==================================================================== */
+
+#define SH_MMRBIST_ERR                           0x0000000100000080
+#define SH_MMRBIST_ERR_MASK                      0x00000071ffffffff
+#define SH_MMRBIST_ERR_INIT                      0x0000000000000000
+
+/*   SH_MMRBIST_ERR_ADDR                                                */
+/*   Description:  dword address of bist error                          */
+#define SH_MMRBIST_ERR_ADDR_SHFT                 0
+#define SH_MMRBIST_ERR_ADDR_MASK                 0x00000001ffffffff
+
+/*   SH_MMRBIST_ERR_DETECTED                                            */
+/*   Description:  error detected flag                                  */
+#define SH_MMRBIST_ERR_DETECTED_SHFT             36
+#define SH_MMRBIST_ERR_DETECTED_MASK             0x0000001000000000
+
+/*   SH_MMRBIST_ERR_MULTIPLE_DETECTED                                   */
+/*   Description:  multiple errors detected flag                        */
+#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_SHFT    37
+#define SH_MMRBIST_ERR_MULTIPLE_DETECTED_MASK    0x0000002000000000
+
+/*   SH_MMRBIST_ERR_CANCELLED                                           */
+/*   Description:  mmr/bist was cancelled                               */
+#define SH_MMRBIST_ERR_CANCELLED_SHFT            38
+#define SH_MMRBIST_ERR_CANCELLED_MASK            0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_LOWER"                   */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#define SH_MISC_ERR_HDR_LOWER                    0x0000000100000088
+#define SH_MISC_ERR_HDR_LOWER_MASK               0x93fffffffffffff8
+#define SH_MISC_ERR_HDR_LOWER_INIT               0x0000000000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_ADDR                                         */
+/*   Description:  upper bits of reference address                      */
+#define SH_MISC_ERR_HDR_LOWER_ADDR_SHFT          3
+#define SH_MISC_ERR_HDR_LOWER_ADDR_MASK          0x0000000ffffffff8
+
+/*   SH_MISC_ERR_HDR_LOWER_CMD                                          */
+/*   Description:  command of reference                                 */
+#define SH_MISC_ERR_HDR_LOWER_CMD_SHFT           36
+#define SH_MISC_ERR_HDR_LOWER_CMD_MASK           0x00000ff000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_SRC                                          */
+/*   Description:  source node of reference                             */
+#define SH_MISC_ERR_HDR_LOWER_SRC_SHFT           44
+#define SH_MISC_ERR_HDR_LOWER_SRC_MASK           0x03fff00000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_WRITE                                        */
+/*   Description:  reference is a write                                 */
+#define SH_MISC_ERR_HDR_LOWER_WRITE_SHFT         60
+#define SH_MISC_ERR_HDR_LOWER_WRITE_MASK         0x1000000000000000
+
+/*   SH_MISC_ERR_HDR_LOWER_VALID                                        */
+/*   Description:  set when capture occurs                              */
+#define SH_MISC_ERR_HDR_LOWER_VALID_SHFT         63
+#define SH_MISC_ERR_HDR_LOWER_VALID_MASK         0x8000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_UPPER"                   */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#define SH_MISC_ERR_HDR_UPPER                    0x0000000100000090
+#define SH_MISC_ERR_HDR_UPPER_MASK               0x000000001ff000ff
+#define SH_MISC_ERR_HDR_UPPER_INIT               0x0000000000000000
+
+/*   SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL                                 */
+/*   Description:  indicates a directory protocol error captured        */
+#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_SHFT  0
+#define SH_MISC_ERR_HDR_UPPER_DIR_PROTOCOL_MASK  0x0000000000000001
+
+/*   SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD                                  */
+/*   Description:  indicates an illegal command error captured          */
+#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_SHFT   1
+#define SH_MISC_ERR_HDR_UPPER_ILLEGAL_CMD_MASK   0x0000000000000002
+
+/*   SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR                                */
+/*   Description:  indicates a non-existent memory error captured       */
+#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_SHFT 2
+#define SH_MISC_ERR_HDR_UPPER_NONEXIST_ADDR_MASK 0x0000000000000004
+
+/*   SH_MISC_ERR_HDR_UPPER_RMW_UC                                       */
+/*   Description:  indicates an uncorrectable store rmw                 */
+#define SH_MISC_ERR_HDR_UPPER_RMW_UC_SHFT        3
+#define SH_MISC_ERR_HDR_UPPER_RMW_UC_MASK        0x0000000000000008
+
+/*   SH_MISC_ERR_HDR_UPPER_RMW_COR                                      */
+/*   Description:  indicates a correctable store rmw                    */
+#define SH_MISC_ERR_HDR_UPPER_RMW_COR_SHFT       4
+#define SH_MISC_ERR_HDR_UPPER_RMW_COR_MASK       0x0000000000000010
+
+/*   SH_MISC_ERR_HDR_UPPER_DIR_ACC                                      */
+/*   Description:  indicates a data request to directory memory error   */
+/*  captured                                                            */
+#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_SHFT       5
+#define SH_MISC_ERR_HDR_UPPER_DIR_ACC_MASK       0x0000000000000020
+
+/*   SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE                                  */
+/*   Description:  indicates a pkt size error from pi                   */
+#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_SHFT   6
+#define SH_MISC_ERR_HDR_UPPER_PI_PKT_SIZE_MASK   0x0000000000000040
+
+/*   SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE                                  */
+/*   Description:  indicates a pkt size error from xn                   */
+#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_SHFT   7
+#define SH_MISC_ERR_HDR_UPPER_XN_PKT_SIZE_MASK   0x0000000000000080
+
+/*   SH_MISC_ERR_HDR_UPPER_ECHO                                         */
+#define SH_MISC_ERR_HDR_UPPER_ECHO_SHFT          20
+#define SH_MISC_ERR_HDR_UPPER_ECHO_MASK          0x000000001ff00000
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#define SH_DIR_UC_ERR_HDR_LOWER                  0x0000000100000098
+#define SH_DIR_UC_ERR_HDR_LOWER_MASK             0x93fffffffffffff8
+#define SH_DIR_UC_ERR_HDR_LOWER_INIT             0x0000000000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_ADDR                                       */
+/*   Description:  upper bits of reference address                      */
+#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_SHFT        3
+#define SH_DIR_UC_ERR_HDR_LOWER_ADDR_MASK        0x0000000ffffffff8
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_CMD                                        */
+/*   Description:  command of reference                                 */
+#define SH_DIR_UC_ERR_HDR_LOWER_CMD_SHFT         36
+#define SH_DIR_UC_ERR_HDR_LOWER_CMD_MASK         0x00000ff000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_SRC                                        */
+/*   Description:  source node of reference                             */
+#define SH_DIR_UC_ERR_HDR_LOWER_SRC_SHFT         44
+#define SH_DIR_UC_ERR_HDR_LOWER_SRC_MASK         0x03fff00000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_WRITE                                      */
+/*   Description:  reference is a write                                 */
+#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_SHFT       60
+#define SH_DIR_UC_ERR_HDR_LOWER_WRITE_MASK       0x1000000000000000
+
+/*   SH_DIR_UC_ERR_HDR_LOWER_VALID                                      */
+/*   Description:  set when capture occurs                              */
+#define SH_DIR_UC_ERR_HDR_LOWER_VALID_SHFT       63
+#define SH_DIR_UC_ERR_HDR_LOWER_VALID_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#define SH_DIR_UC_ERR_HDR_UPPER                  0x00000001000000a0
+#define SH_DIR_UC_ERR_HDR_UPPER_MASK             0x000000001ff00008
+#define SH_DIR_UC_ERR_HDR_UPPER_INIT             0x0000000000000000
+
+/*   SH_DIR_UC_ERR_HDR_UPPER_DIR_UC                                     */
+/*   Description:  indicates uncorrectable directory error captured     */
+#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_SHFT      3
+#define SH_DIR_UC_ERR_HDR_UPPER_DIR_UC_MASK      0x0000000000000008
+
+/*   SH_DIR_UC_ERR_HDR_UPPER_ECHO                                       */
+#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_SHFT        20
+#define SH_DIR_UC_ERR_HDR_UPPER_ECHO_MASK        0x000000001ff00000
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#define SH_DIR_COR_ERR_HDR_LOWER                 0x00000001000000a8
+#define SH_DIR_COR_ERR_HDR_LOWER_MASK            0x93fffffffffffff8
+#define SH_DIR_COR_ERR_HDR_LOWER_INIT            0x0000000000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_ADDR                                      */
+/*   Description:  upper bits of reference address                      */
+#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_SHFT       3
+#define SH_DIR_COR_ERR_HDR_LOWER_ADDR_MASK       0x0000000ffffffff8
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_CMD                                       */
+/*   Description:  command of reference                                 */
+#define SH_DIR_COR_ERR_HDR_LOWER_CMD_SHFT        36
+#define SH_DIR_COR_ERR_HDR_LOWER_CMD_MASK        0x00000ff000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_SRC                                       */
+/*   Description:  source node of reference                             */
+#define SH_DIR_COR_ERR_HDR_LOWER_SRC_SHFT        44
+#define SH_DIR_COR_ERR_HDR_LOWER_SRC_MASK        0x03fff00000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_WRITE                                     */
+/*   Description:  reference is a write                                 */
+#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_SHFT      60
+#define SH_DIR_COR_ERR_HDR_LOWER_WRITE_MASK      0x1000000000000000
+
+/*   SH_DIR_COR_ERR_HDR_LOWER_VALID                                     */
+/*   Description:  set when capture occurs                              */
+#define SH_DIR_COR_ERR_HDR_LOWER_VALID_SHFT      63
+#define SH_DIR_COR_ERR_HDR_LOWER_VALID_MASK      0x8000000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#define SH_DIR_COR_ERR_HDR_UPPER                 0x00000001000000b0
+#define SH_DIR_COR_ERR_HDR_UPPER_MASK            0x000000001ff00100
+#define SH_DIR_COR_ERR_HDR_UPPER_INIT            0x0000000000000000
+
+/*   SH_DIR_COR_ERR_HDR_UPPER_DIR_COR                                   */
+/*   Description:  indicates correctable directory error captured       */
+#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_SHFT    8
+#define SH_DIR_COR_ERR_HDR_UPPER_DIR_COR_MASK    0x0000000000000100
+
+/*   SH_DIR_COR_ERR_HDR_UPPER_ECHO                                      */
+#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_SHFT       20
+#define SH_DIR_COR_ERR_HDR_UPPER_ECHO_MASK       0x000000001ff00000
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_SUMMARY"                    */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_SUMMARY                     0x00000001000000b8
+#define SH_MEM_ERROR_SUMMARY_MASK                0x00000007f77777ff
+#define SH_MEM_ERROR_SUMMARY_INIT                0x0000000000000000
+
+/*   SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD                                   */
+/*   Description:  illegal command error                                */
+#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_SHFT    0
+#define SH_MEM_ERROR_SUMMARY_ILLEGAL_CMD_MASK    0x0000000000000001
+
+/*   SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR                                 */
+/*   Description:  non-existent memory error                            */
+#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_SHFT  1
+#define SH_MEM_ERROR_SUMMARY_NONEXIST_ADDR_MASK  0x0000000000000002
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR                                 */
+/*   Description:  directory protocol error in dqlp                     */
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_SHFT  2
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_PERR_MASK  0x0000000000000004
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR                                 */
+/*   Description:  directory protocol error in dqrp                     */
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_SHFT  3
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_PERR_MASK  0x0000000000000008
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC                                   */
+/*   Description:  uncorrectable directory error in dqlp                */
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_SHFT    4
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_UC_MASK    0x0000000000000010
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR                                  */
+/*   Description:  correctable directory error in dqlp                  */
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_SHFT   5
+#define SH_MEM_ERROR_SUMMARY_DQLP_DIR_COR_MASK   0x0000000000000020
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC                                   */
+/*   Description:  uncorrectable directory error in dqrp                */
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_SHFT    6
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_UC_MASK    0x0000000000000040
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR                                  */
+/*   Description:  correctable directory error in dqrp                  */
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_SHFT   7
+#define SH_MEM_ERROR_SUMMARY_DQRP_DIR_COR_MASK   0x0000000000000080
+
+/*   SH_MEM_ERROR_SUMMARY_ACX_INT_HW                                    */
+/*   Description:  hardware interrupt from acx                          */
+#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_SHFT     8
+#define SH_MEM_ERROR_SUMMARY_ACX_INT_HW_MASK     0x0000000000000100
+
+/*   SH_MEM_ERROR_SUMMARY_ACY_INT_HW                                    */
+/*   Description:  hardware interrupt from acy                          */
+#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_SHFT     9
+#define SH_MEM_ERROR_SUMMARY_ACY_INT_HW_MASK     0x0000000000000200
+
+/*   SH_MEM_ERROR_SUMMARY_DIR_ACC                                       */
+/*   Description:  directory memory access error                        */
+#define SH_MEM_ERROR_SUMMARY_DIR_ACC_SHFT        10
+#define SH_MEM_ERROR_SUMMARY_DIR_ACC_MASK        0x0000000000000400
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqlp                    */
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_SHFT    12
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_UC_MASK    0x0000000000001000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_INT_COR                                  */
+/*   Description:  correctable interrupt from dqlp                      */
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_SHFT   13
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_COR_MASK   0x0000000000002000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLP_INT_HW                                   */
+/*   Description:  hardware interrupt from dqlp                         */
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_SHFT    14
+#define SH_MEM_ERROR_SUMMARY_DQLP_INT_HW_MASK    0x0000000000004000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLS_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqls                    */
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_SHFT    16
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_UC_MASK    0x0000000000010000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLS_INT_COR                                  */
+/*   Description:  correctable interrupt from dqls                      */
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_SHFT   17
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_COR_MASK   0x0000000000020000
+
+/*   SH_MEM_ERROR_SUMMARY_DQLS_INT_HW                                   */
+/*   Description:  hardware interrupt from dqls                         */
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_SHFT    18
+#define SH_MEM_ERROR_SUMMARY_DQLS_INT_HW_MASK    0x0000000000040000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqrp                    */
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_SHFT    20
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_UC_MASK    0x0000000000100000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_INT_COR                                  */
+/*   Description:  correctable interrupt from dqrp                      */
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_SHFT   21
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_COR_MASK   0x0000000000200000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRP_INT_HW                                   */
+/*   Description:  hardware interrupt from dqrp                         */
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_SHFT    22
+#define SH_MEM_ERROR_SUMMARY_DQRP_INT_HW_MASK    0x0000000000400000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRS_INT_UC                                   */
+/*   Description:  uncorrectable interrupt from dqrs                    */
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_SHFT    24
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_UC_MASK    0x0000000001000000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRS_INT_COR                                  */
+/*   Description:  correctable interrupt from dqrs                      */
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_SHFT   25
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_COR_MASK   0x0000000002000000
+
+/*   SH_MEM_ERROR_SUMMARY_DQRS_INT_HW                                   */
+/*   Description:  hardware interrupt from dqrs                         */
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_SHFT    26
+#define SH_MEM_ERROR_SUMMARY_DQRS_INT_HW_MASK    0x0000000004000000
+
+/*   SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW                             */
+/*   Description:  too many reply packets came from pi                  */
+#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_SHFT 28
+#define SH_MEM_ERROR_SUMMARY_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
+
+/*   SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW                             */
+/*   Description:  too many reply packets came from xn                  */
+#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_SHFT 29
+#define SH_MEM_ERROR_SUMMARY_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
+
+/*   SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW                           */
+/*   Description:  too many request packets came from pi                */
+#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_SHFT 30
+#define SH_MEM_ERROR_SUMMARY_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
+
+/*   SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW                           */
+/*   Description:  too many request packets came from xn                */
+#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_SHFT 31
+#define SH_MEM_ERROR_SUMMARY_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
+
+/*   SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT                         */
+/*   Description:  red black scheme did not clean up soon enough        */
+#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_SHFT 32
+#define SH_MEM_ERROR_SUMMARY_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
+
+/*   SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE                                   */
+/*   Description:  received data bearing packet from pi with wrong siz  */
+#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_SHFT    33
+#define SH_MEM_ERROR_SUMMARY_PI_PKT_SIZE_MASK    0x0000000200000000
+
+/*   SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE                                   */
+/*   Description:  received data bearing packet from xn with wrong siz  */
+#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_SHFT    34
+#define SH_MEM_ERROR_SUMMARY_XN_PKT_SIZE_MASK    0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_MEM_ERROR_SUMMARY_ALIAS"                 */
+/*                    Memory error flags clear alias                    */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_SUMMARY_ALIAS               0x00000001000000c0
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_OVERFLOW"                   */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_OVERFLOW                    0x00000001000000c8
+#define SH_MEM_ERROR_OVERFLOW_MASK               0x00000007f77777ff
+#define SH_MEM_ERROR_OVERFLOW_INIT               0x0000000000000000
+
+/*   SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD                                  */
+/*   Description:  illegal command error                                */
+#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_SHFT   0
+#define SH_MEM_ERROR_OVERFLOW_ILLEGAL_CMD_MASK   0x0000000000000001
+
+/*   SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR                                */
+/*   Description:  non-existent memory error                            */
+#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_SHFT 1
+#define SH_MEM_ERROR_OVERFLOW_NONEXIST_ADDR_MASK 0x0000000000000002
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR                                */
+/*   Description:  directory protocol error in dqlp                     */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_SHFT 2
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_PERR_MASK 0x0000000000000004
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR                                */
+/*   Description:  directory protocol error in dqrp                     */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_SHFT 3
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_PERR_MASK 0x0000000000000008
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC                                  */
+/*   Description:  uncorrectable directory error in dqlp                */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_SHFT   4
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_UC_MASK   0x0000000000000010
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR                                 */
+/*   Description:  correctable directory error in dqlp                  */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_SHFT  5
+#define SH_MEM_ERROR_OVERFLOW_DQLP_DIR_COR_MASK  0x0000000000000020
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC                                  */
+/*   Description:  uncorrectable directory error in dqrp                */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_SHFT   6
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_UC_MASK   0x0000000000000040
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR                                 */
+/*   Description:  correctable directory error in dqrp                  */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_SHFT  7
+#define SH_MEM_ERROR_OVERFLOW_DQRP_DIR_COR_MASK  0x0000000000000080
+
+/*   SH_MEM_ERROR_OVERFLOW_ACX_INT_HW                                   */
+/*   Description:  hardware interrupt from acx                          */
+#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_SHFT    8
+#define SH_MEM_ERROR_OVERFLOW_ACX_INT_HW_MASK    0x0000000000000100
+
+/*   SH_MEM_ERROR_OVERFLOW_ACY_INT_HW                                   */
+/*   Description:  hardware interrupt from acy                          */
+#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_SHFT    9
+#define SH_MEM_ERROR_OVERFLOW_ACY_INT_HW_MASK    0x0000000000000200
+
+/*   SH_MEM_ERROR_OVERFLOW_DIR_ACC                                      */
+/*   Description:  directory memory access error                        */
+#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_SHFT       10
+#define SH_MEM_ERROR_OVERFLOW_DIR_ACC_MASK       0x0000000000000400
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqlp                    */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_SHFT   12
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_UC_MASK   0x0000000000001000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR                                 */
+/*   Description:  correctable interrupt from dqlp                      */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_SHFT  13
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_COR_MASK  0x0000000000002000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW                                  */
+/*   Description:  hardware interrupt from dqlp                         */
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_SHFT   14
+#define SH_MEM_ERROR_OVERFLOW_DQLP_INT_HW_MASK   0x0000000000004000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqls                    */
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_SHFT   16
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_UC_MASK   0x0000000000010000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR                                 */
+/*   Description:  correctable interrupt from dqls                      */
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_SHFT  17
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_COR_MASK  0x0000000000020000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW                                  */
+/*   Description:  hardware interrupt from dqls                         */
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_SHFT   18
+#define SH_MEM_ERROR_OVERFLOW_DQLS_INT_HW_MASK   0x0000000000040000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqrp                    */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_SHFT   20
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_UC_MASK   0x0000000000100000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR                                 */
+/*   Description:  correctable interrupt from dqrp                      */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_SHFT  21
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_COR_MASK  0x0000000000200000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW                                  */
+/*   Description:  hardware interrupt from dqrp                         */
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_SHFT   22
+#define SH_MEM_ERROR_OVERFLOW_DQRP_INT_HW_MASK   0x0000000000400000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC                                  */
+/*   Description:  uncorrectable interrupt from dqrs                    */
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_SHFT   24
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_UC_MASK   0x0000000001000000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR                                 */
+/*   Description:  correctable interrupt from dqrs                      */
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_SHFT  25
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_COR_MASK  0x0000000002000000
+
+/*   SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW                                  */
+/*   Description:  hardware interrupt from dqrs                         */
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_SHFT   26
+#define SH_MEM_ERROR_OVERFLOW_DQRS_INT_HW_MASK   0x0000000004000000
+
+/*   SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW                            */
+/*   Description:  too many reply packets came from pi                  */
+#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_SHFT 28
+#define SH_MEM_ERROR_OVERFLOW_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
+
+/*   SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW                            */
+/*   Description:  too many reply packets came from xn                  */
+#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_SHFT 29
+#define SH_MEM_ERROR_OVERFLOW_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
+
+/*   SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW                          */
+/*   Description:  too many request packets came from pi                */
+#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_SHFT 30
+#define SH_MEM_ERROR_OVERFLOW_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
+
+/*   SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW                          */
+/*   Description:  too many request packets came from xn                */
+#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_SHFT 31
+#define SH_MEM_ERROR_OVERFLOW_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
+
+/*   SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT                        */
+/*   Description:  red black scheme did not clean up soon enough        */
+#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_SHFT 32
+#define SH_MEM_ERROR_OVERFLOW_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
+
+/*   SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE                                  */
+/*   Description:  received data bearing packet from pi with wrong siz  */
+#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_SHFT   33
+#define SH_MEM_ERROR_OVERFLOW_PI_PKT_SIZE_MASK   0x0000000200000000
+
+/*   SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE                                  */
+/*   Description:  received data bearing packet from xn with wrong siz  */
+#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_SHFT   34
+#define SH_MEM_ERROR_OVERFLOW_XN_PKT_SIZE_MASK   0x0000000400000000
+
+/* ==================================================================== */
+/*                Register "SH_MEM_ERROR_OVERFLOW_ALIAS"                */
+/*                    Memory error flags clear alias                    */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_OVERFLOW_ALIAS              0x00000001000000d0
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_ERROR_MASK"                     */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#define SH_MEM_ERROR_MASK                        0x00000001000000d8
+#define SH_MEM_ERROR_MASK_MASK                   0x00000007f77777ff
+#define SH_MEM_ERROR_MASK_INIT                   0x00000007f77773ff
+
+/*   SH_MEM_ERROR_MASK_ILLEGAL_CMD                                      */
+/*   Description:  illegal command error                                */
+#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_SHFT       0
+#define SH_MEM_ERROR_MASK_ILLEGAL_CMD_MASK       0x0000000000000001
+
+/*   SH_MEM_ERROR_MASK_NONEXIST_ADDR                                    */
+/*   Description:  non-existent memory error                            */
+#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_SHFT     1
+#define SH_MEM_ERROR_MASK_NONEXIST_ADDR_MASK     0x0000000000000002
+
+/*   SH_MEM_ERROR_MASK_DQLP_DIR_PERR                                    */
+/*   Description:  directory protocol error in dqlp                     */
+#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_SHFT     2
+#define SH_MEM_ERROR_MASK_DQLP_DIR_PERR_MASK     0x0000000000000004
+
+/*   SH_MEM_ERROR_MASK_DQRP_DIR_PERR                                    */
+/*   Description:  directory protocol error in dqrp                     */
+#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_SHFT     3
+#define SH_MEM_ERROR_MASK_DQRP_DIR_PERR_MASK     0x0000000000000008
+
+/*   SH_MEM_ERROR_MASK_DQLP_DIR_UC                                      */
+/*   Description:  uncorrectable directory error in dqlp                */
+#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_SHFT       4
+#define SH_MEM_ERROR_MASK_DQLP_DIR_UC_MASK       0x0000000000000010
+
+/*   SH_MEM_ERROR_MASK_DQLP_DIR_COR                                     */
+/*   Description:  correctable directory error in dqlp                  */
+#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_SHFT      5
+#define SH_MEM_ERROR_MASK_DQLP_DIR_COR_MASK      0x0000000000000020
+
+/*   SH_MEM_ERROR_MASK_DQRP_DIR_UC                                      */
+/*   Description:  uncorrectable directory error in dqrp                */
+#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_SHFT       6
+#define SH_MEM_ERROR_MASK_DQRP_DIR_UC_MASK       0x0000000000000040
+
+/*   SH_MEM_ERROR_MASK_DQRP_DIR_COR                                     */
+/*   Description:  correctable directory error in dqrp                  */
+#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_SHFT      7
+#define SH_MEM_ERROR_MASK_DQRP_DIR_COR_MASK      0x0000000000000080
+
+/*   SH_MEM_ERROR_MASK_ACX_INT_HW                                       */
+/*   Description:  hardware interrupt from acx                          */
+#define SH_MEM_ERROR_MASK_ACX_INT_HW_SHFT        8
+#define SH_MEM_ERROR_MASK_ACX_INT_HW_MASK        0x0000000000000100
+
+/*   SH_MEM_ERROR_MASK_ACY_INT_HW                                       */
+/*   Description:  hardware interrupt from acy                          */
+#define SH_MEM_ERROR_MASK_ACY_INT_HW_SHFT        9
+#define SH_MEM_ERROR_MASK_ACY_INT_HW_MASK        0x0000000000000200
+
+/*   SH_MEM_ERROR_MASK_DIR_ACC                                          */
+/*   Description:  directory memory access error                        */
+#define SH_MEM_ERROR_MASK_DIR_ACC_SHFT           10
+#define SH_MEM_ERROR_MASK_DIR_ACC_MASK           0x0000000000000400
+
+/*   SH_MEM_ERROR_MASK_DQLP_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqlp                    */
+#define SH_MEM_ERROR_MASK_DQLP_INT_UC_SHFT       12
+#define SH_MEM_ERROR_MASK_DQLP_INT_UC_MASK       0x0000000000001000
+
+/*   SH_MEM_ERROR_MASK_DQLP_INT_COR                                     */
+/*   Description:  correctable interrupt from dqlp                      */
+#define SH_MEM_ERROR_MASK_DQLP_INT_COR_SHFT      13
+#define SH_MEM_ERROR_MASK_DQLP_INT_COR_MASK      0x0000000000002000
+
+/*   SH_MEM_ERROR_MASK_DQLP_INT_HW                                      */
+/*   Description:  hardware interrupt from dqlp                         */
+#define SH_MEM_ERROR_MASK_DQLP_INT_HW_SHFT       14
+#define SH_MEM_ERROR_MASK_DQLP_INT_HW_MASK       0x0000000000004000
+
+/*   SH_MEM_ERROR_MASK_DQLS_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqls                    */
+#define SH_MEM_ERROR_MASK_DQLS_INT_UC_SHFT       16
+#define SH_MEM_ERROR_MASK_DQLS_INT_UC_MASK       0x0000000000010000
+
+/*   SH_MEM_ERROR_MASK_DQLS_INT_COR                                     */
+/*   Description:  correctable interrupt from dqls                      */
+#define SH_MEM_ERROR_MASK_DQLS_INT_COR_SHFT      17
+#define SH_MEM_ERROR_MASK_DQLS_INT_COR_MASK      0x0000000000020000
+
+/*   SH_MEM_ERROR_MASK_DQLS_INT_HW                                      */
+/*   Description:  hardware interrupt from dqls                         */
+#define SH_MEM_ERROR_MASK_DQLS_INT_HW_SHFT       18
+#define SH_MEM_ERROR_MASK_DQLS_INT_HW_MASK       0x0000000000040000
+
+/*   SH_MEM_ERROR_MASK_DQRP_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqrp                    */
+#define SH_MEM_ERROR_MASK_DQRP_INT_UC_SHFT       20
+#define SH_MEM_ERROR_MASK_DQRP_INT_UC_MASK       0x0000000000100000
+
+/*   SH_MEM_ERROR_MASK_DQRP_INT_COR                                     */
+/*   Description:  correctable interrupt from dqrp                      */
+#define SH_MEM_ERROR_MASK_DQRP_INT_COR_SHFT      21
+#define SH_MEM_ERROR_MASK_DQRP_INT_COR_MASK      0x0000000000200000
+
+/*   SH_MEM_ERROR_MASK_DQRP_INT_HW                                      */
+/*   Description:  hardware interrupt from dqrp                         */
+#define SH_MEM_ERROR_MASK_DQRP_INT_HW_SHFT       22
+#define SH_MEM_ERROR_MASK_DQRP_INT_HW_MASK       0x0000000000400000
+
+/*   SH_MEM_ERROR_MASK_DQRS_INT_UC                                      */
+/*   Description:  uncorrectable interrupt from dqrs                    */
+#define SH_MEM_ERROR_MASK_DQRS_INT_UC_SHFT       24
+#define SH_MEM_ERROR_MASK_DQRS_INT_UC_MASK       0x0000000001000000
+
+/*   SH_MEM_ERROR_MASK_DQRS_INT_COR                                     */
+/*   Description:  correctable interrupt from dqrs                      */
+#define SH_MEM_ERROR_MASK_DQRS_INT_COR_SHFT      25
+#define SH_MEM_ERROR_MASK_DQRS_INT_COR_MASK      0x0000000002000000
+
+/*   SH_MEM_ERROR_MASK_DQRS_INT_HW                                      */
+/*   Description:  hardware interrupt from dqrs                         */
+#define SH_MEM_ERROR_MASK_DQRS_INT_HW_SHFT       26
+#define SH_MEM_ERROR_MASK_DQRS_INT_HW_MASK       0x0000000004000000
+
+/*   SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW                                */
+/*   Description:  too many reply packets came from pi                  */
+#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_SHFT 28
+#define SH_MEM_ERROR_MASK_PI_REPLY_OVERFLOW_MASK 0x0000000010000000
+
+/*   SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW                                */
+/*   Description:  too many reply packets came from xn                  */
+#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_SHFT 29
+#define SH_MEM_ERROR_MASK_XN_REPLY_OVERFLOW_MASK 0x0000000020000000
+
+/*   SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW                              */
+/*   Description:  too many request packets came from pi                */
+#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_SHFT 30
+#define SH_MEM_ERROR_MASK_PI_REQUEST_OVERFLOW_MASK 0x0000000040000000
+
+/*   SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW                              */
+/*   Description:  too many request packets came from xn                */
+#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_SHFT 31
+#define SH_MEM_ERROR_MASK_XN_REQUEST_OVERFLOW_MASK 0x0000000080000000
+
+/*   SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT                            */
+/*   Description:  red black scheme did not clean up soon enough        */
+#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_SHFT 32
+#define SH_MEM_ERROR_MASK_RED_BLACK_ERR_TIMEOUT_MASK 0x0000000100000000
+
+/*   SH_MEM_ERROR_MASK_PI_PKT_SIZE                                      */
+/*   Description:  received data bearing packet from pi with wrong siz  */
+#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_SHFT       33
+#define SH_MEM_ERROR_MASK_PI_PKT_SIZE_MASK       0x0000000200000000
+
+/*   SH_MEM_ERROR_MASK_XN_PKT_SIZE                                      */
+/*   Description:  received data bearing packet from xn with wrong siz  */
+#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_SHFT       34
+#define SH_MEM_ERROR_MASK_XN_PKT_SIZE_MASK       0x0000000400000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#define SH_X_DIMM_CFG                            0x0000000100010000
+#define SH_X_DIMM_CFG_MASK                       0x0000000f7f7f7f7f
+#define SH_X_DIMM_CFG_INIT                       0x000000026f4f2f0f
+
+/*   SH_X_DIMM_CFG_DIMM0_SIZE                                           */
+/*   Description:  DIMM 0 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM0_SIZE_SHFT            0
+#define SH_X_DIMM_CFG_DIMM0_SIZE_MASK            0x0000000000000007
+
+/*   SH_X_DIMM_CFG_DIMM0_2BK                                            */
+/*   Description:  DIMM 0 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM0_2BK_SHFT             3
+#define SH_X_DIMM_CFG_DIMM0_2BK_MASK             0x0000000000000008
+
+/*   SH_X_DIMM_CFG_DIMM0_REV                                            */
+/*   Description:  DIMM 0 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM0_REV_SHFT             4
+#define SH_X_DIMM_CFG_DIMM0_REV_MASK             0x0000000000000010
+
+/*   SH_X_DIMM_CFG_DIMM0_CS                                             */
+/*   Description:  DIMM 0 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM0_CS_SHFT              5
+#define SH_X_DIMM_CFG_DIMM0_CS_MASK              0x0000000000000060
+
+/*   SH_X_DIMM_CFG_DIMM1_SIZE                                           */
+/*   Description:  DIMM 1 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM1_SIZE_SHFT            8
+#define SH_X_DIMM_CFG_DIMM1_SIZE_MASK            0x0000000000000700
+
+/*   SH_X_DIMM_CFG_DIMM1_2BK                                            */
+/*   Description:  DIMM 1 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM1_2BK_SHFT             11
+#define SH_X_DIMM_CFG_DIMM1_2BK_MASK             0x0000000000000800
+
+/*   SH_X_DIMM_CFG_DIMM1_REV                                            */
+/*   Description:  DIMM 1 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM1_REV_SHFT             12
+#define SH_X_DIMM_CFG_DIMM1_REV_MASK             0x0000000000001000
+
+/*   SH_X_DIMM_CFG_DIMM1_CS                                             */
+/*   Description:  DIMM 1 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM1_CS_SHFT              13
+#define SH_X_DIMM_CFG_DIMM1_CS_MASK              0x0000000000006000
+
+/*   SH_X_DIMM_CFG_DIMM2_SIZE                                           */
+/*   Description:  DIMM 2 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM2_SIZE_SHFT            16
+#define SH_X_DIMM_CFG_DIMM2_SIZE_MASK            0x0000000000070000
+
+/*   SH_X_DIMM_CFG_DIMM2_2BK                                            */
+/*   Description:  DIMM 2 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM2_2BK_SHFT             19
+#define SH_X_DIMM_CFG_DIMM2_2BK_MASK             0x0000000000080000
+
+/*   SH_X_DIMM_CFG_DIMM2_REV                                            */
+/*   Description:  DIMM 2 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM2_REV_SHFT             20
+#define SH_X_DIMM_CFG_DIMM2_REV_MASK             0x0000000000100000
+
+/*   SH_X_DIMM_CFG_DIMM2_CS                                             */
+/*   Description:  DIMM 2 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM2_CS_SHFT              21
+#define SH_X_DIMM_CFG_DIMM2_CS_MASK              0x0000000000600000
+
+/*   SH_X_DIMM_CFG_DIMM3_SIZE                                           */
+/*   Description:  DIMM 3 DRAM size                                     */
+#define SH_X_DIMM_CFG_DIMM3_SIZE_SHFT            24
+#define SH_X_DIMM_CFG_DIMM3_SIZE_MASK            0x0000000007000000
+
+/*   SH_X_DIMM_CFG_DIMM3_2BK                                            */
+/*   Description:  DIMM 3 has two physical banks                        */
+#define SH_X_DIMM_CFG_DIMM3_2BK_SHFT             27
+#define SH_X_DIMM_CFG_DIMM3_2BK_MASK             0x0000000008000000
+
+/*   SH_X_DIMM_CFG_DIMM3_REV                                            */
+/*   Description:  DIMM 3 physical banks reversed                       */
+#define SH_X_DIMM_CFG_DIMM3_REV_SHFT             28
+#define SH_X_DIMM_CFG_DIMM3_REV_MASK             0x0000000010000000
+
+/*   SH_X_DIMM_CFG_DIMM3_CS                                             */
+/*   Description:  DIMM 3 chip select, addr[35:34] match                */
+#define SH_X_DIMM_CFG_DIMM3_CS_SHFT              29
+#define SH_X_DIMM_CFG_DIMM3_CS_MASK              0x0000000060000000
+
+/*   SH_X_DIMM_CFG_FREQ                                                 */
+/*   Description:  DIMM frequency select                                */
+#define SH_X_DIMM_CFG_FREQ_SHFT                  32
+#define SH_X_DIMM_CFG_FREQ_MASK                  0x0000000f00000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#define SH_Y_DIMM_CFG                            0x0000000100010008
+#define SH_Y_DIMM_CFG_MASK                       0x0000000f7f7f7f7f
+#define SH_Y_DIMM_CFG_INIT                       0x000000026f4f2f0f
+
+/*   SH_Y_DIMM_CFG_DIMM0_SIZE                                           */
+/*   Description:  DIMM 0 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM0_SIZE_SHFT            0
+#define SH_Y_DIMM_CFG_DIMM0_SIZE_MASK            0x0000000000000007
+
+/*   SH_Y_DIMM_CFG_DIMM0_2BK                                            */
+/*   Description:  DIMM 0 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM0_2BK_SHFT             3
+#define SH_Y_DIMM_CFG_DIMM0_2BK_MASK             0x0000000000000008
+
+/*   SH_Y_DIMM_CFG_DIMM0_REV                                            */
+/*   Description:  DIMM 0 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM0_REV_SHFT             4
+#define SH_Y_DIMM_CFG_DIMM0_REV_MASK             0x0000000000000010
+
+/*   SH_Y_DIMM_CFG_DIMM0_CS                                             */
+/*   Description:  DIMM 0 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM0_CS_SHFT              5
+#define SH_Y_DIMM_CFG_DIMM0_CS_MASK              0x0000000000000060
+
+/*   SH_Y_DIMM_CFG_DIMM1_SIZE                                           */
+/*   Description:  DIMM 1 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM1_SIZE_SHFT            8
+#define SH_Y_DIMM_CFG_DIMM1_SIZE_MASK            0x0000000000000700
+
+/*   SH_Y_DIMM_CFG_DIMM1_2BK                                            */
+/*   Description:  DIMM 1 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM1_2BK_SHFT             11
+#define SH_Y_DIMM_CFG_DIMM1_2BK_MASK             0x0000000000000800
+
+/*   SH_Y_DIMM_CFG_DIMM1_REV                                            */
+/*   Description:  DIMM 1 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM1_REV_SHFT             12
+#define SH_Y_DIMM_CFG_DIMM1_REV_MASK             0x0000000000001000
+
+/*   SH_Y_DIMM_CFG_DIMM1_CS                                             */
+/*   Description:  DIMM 1 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM1_CS_SHFT              13
+#define SH_Y_DIMM_CFG_DIMM1_CS_MASK              0x0000000000006000
+
+/*   SH_Y_DIMM_CFG_DIMM2_SIZE                                           */
+/*   Description:  DIMM 2 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM2_SIZE_SHFT            16
+#define SH_Y_DIMM_CFG_DIMM2_SIZE_MASK            0x0000000000070000
+
+/*   SH_Y_DIMM_CFG_DIMM2_2BK                                            */
+/*   Description:  DIMM 2 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM2_2BK_SHFT             19
+#define SH_Y_DIMM_CFG_DIMM2_2BK_MASK             0x0000000000080000
+
+/*   SH_Y_DIMM_CFG_DIMM2_REV                                            */
+/*   Description:  DIMM 2 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM2_REV_SHFT             20
+#define SH_Y_DIMM_CFG_DIMM2_REV_MASK             0x0000000000100000
+
+/*   SH_Y_DIMM_CFG_DIMM2_CS                                             */
+/*   Description:  DIMM 2 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM2_CS_SHFT              21
+#define SH_Y_DIMM_CFG_DIMM2_CS_MASK              0x0000000000600000
+
+/*   SH_Y_DIMM_CFG_DIMM3_SIZE                                           */
+/*   Description:  DIMM 3 DRAM size                                     */
+#define SH_Y_DIMM_CFG_DIMM3_SIZE_SHFT            24
+#define SH_Y_DIMM_CFG_DIMM3_SIZE_MASK            0x0000000007000000
+
+/*   SH_Y_DIMM_CFG_DIMM3_2BK                                            */
+/*   Description:  DIMM 3 has two physical banks                        */
+#define SH_Y_DIMM_CFG_DIMM3_2BK_SHFT             27
+#define SH_Y_DIMM_CFG_DIMM3_2BK_MASK             0x0000000008000000
+
+/*   SH_Y_DIMM_CFG_DIMM3_REV                                            */
+/*   Description:  DIMM 3 physical banks reversed                       */
+#define SH_Y_DIMM_CFG_DIMM3_REV_SHFT             28
+#define SH_Y_DIMM_CFG_DIMM3_REV_MASK             0x0000000010000000
+
+/*   SH_Y_DIMM_CFG_DIMM3_CS                                             */
+/*   Description:  DIMM 3 chip select, addr[35:34] match                */
+#define SH_Y_DIMM_CFG_DIMM3_CS_SHFT              29
+#define SH_Y_DIMM_CFG_DIMM3_CS_MASK              0x0000000060000000
+
+/*   SH_Y_DIMM_CFG_FREQ                                                 */
+/*   Description:  DIMM frequency select                                */
+#define SH_Y_DIMM_CFG_FREQ_SHFT                  32
+#define SH_Y_DIMM_CFG_FREQ_MASK                  0x0000000f00000000
+
+/* ==================================================================== */
+/*                      Register "SH_JNR_DIMM_CFG"                      */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#define SH_JNR_DIMM_CFG                          0x0000000100010010
+#define SH_JNR_DIMM_CFG_MASK                     0x0000000f7f7f7f7f
+#define SH_JNR_DIMM_CFG_INIT                     0x000000026f4f2f0f
+
+/*   SH_JNR_DIMM_CFG_DIMM0_SIZE                                         */
+/*   Description:  DIMM 0 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM0_SIZE_SHFT          0
+#define SH_JNR_DIMM_CFG_DIMM0_SIZE_MASK          0x0000000000000007
+
+/*   SH_JNR_DIMM_CFG_DIMM0_2BK                                          */
+/*   Description:  DIMM 0 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM0_2BK_SHFT           3
+#define SH_JNR_DIMM_CFG_DIMM0_2BK_MASK           0x0000000000000008
+
+/*   SH_JNR_DIMM_CFG_DIMM0_REV                                          */
+/*   Description:  DIMM 0 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM0_REV_SHFT           4
+#define SH_JNR_DIMM_CFG_DIMM0_REV_MASK           0x0000000000000010
+
+/*   SH_JNR_DIMM_CFG_DIMM0_CS                                           */
+/*   Description:  DIMM 0 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM0_CS_SHFT            5
+#define SH_JNR_DIMM_CFG_DIMM0_CS_MASK            0x0000000000000060
+
+/*   SH_JNR_DIMM_CFG_DIMM1_SIZE                                         */
+/*   Description:  DIMM 1 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM1_SIZE_SHFT          8
+#define SH_JNR_DIMM_CFG_DIMM1_SIZE_MASK          0x0000000000000700
+
+/*   SH_JNR_DIMM_CFG_DIMM1_2BK                                          */
+/*   Description:  DIMM 1 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM1_2BK_SHFT           11
+#define SH_JNR_DIMM_CFG_DIMM1_2BK_MASK           0x0000000000000800
+
+/*   SH_JNR_DIMM_CFG_DIMM1_REV                                          */
+/*   Description:  DIMM 1 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM1_REV_SHFT           12
+#define SH_JNR_DIMM_CFG_DIMM1_REV_MASK           0x0000000000001000
+
+/*   SH_JNR_DIMM_CFG_DIMM1_CS                                           */
+/*   Description:  DIMM 1 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM1_CS_SHFT            13
+#define SH_JNR_DIMM_CFG_DIMM1_CS_MASK            0x0000000000006000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_SIZE                                         */
+/*   Description:  DIMM 2 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM2_SIZE_SHFT          16
+#define SH_JNR_DIMM_CFG_DIMM2_SIZE_MASK          0x0000000000070000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_2BK                                          */
+/*   Description:  DIMM 2 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM2_2BK_SHFT           19
+#define SH_JNR_DIMM_CFG_DIMM2_2BK_MASK           0x0000000000080000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_REV                                          */
+/*   Description:  DIMM 2 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM2_REV_SHFT           20
+#define SH_JNR_DIMM_CFG_DIMM2_REV_MASK           0x0000000000100000
+
+/*   SH_JNR_DIMM_CFG_DIMM2_CS                                           */
+/*   Description:  DIMM 2 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM2_CS_SHFT            21
+#define SH_JNR_DIMM_CFG_DIMM2_CS_MASK            0x0000000000600000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_SIZE                                         */
+/*   Description:  DIMM 3 DRAM size                                     */
+#define SH_JNR_DIMM_CFG_DIMM3_SIZE_SHFT          24
+#define SH_JNR_DIMM_CFG_DIMM3_SIZE_MASK          0x0000000007000000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_2BK                                          */
+/*   Description:  DIMM 3 has two physical banks                        */
+#define SH_JNR_DIMM_CFG_DIMM3_2BK_SHFT           27
+#define SH_JNR_DIMM_CFG_DIMM3_2BK_MASK           0x0000000008000000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_REV                                          */
+/*   Description:  DIMM 3 physical banks reversed                       */
+#define SH_JNR_DIMM_CFG_DIMM3_REV_SHFT           28
+#define SH_JNR_DIMM_CFG_DIMM3_REV_MASK           0x0000000010000000
+
+/*   SH_JNR_DIMM_CFG_DIMM3_CS                                           */
+/*   Description:  DIMM 3 chip select, addr[35:34] match                */
+#define SH_JNR_DIMM_CFG_DIMM3_CS_SHFT            29
+#define SH_JNR_DIMM_CFG_DIMM3_CS_MASK            0x0000000060000000
+
+/*   SH_JNR_DIMM_CFG_FREQ                                               */
+/*   Description:  DIMM frequency select                                */
+#define SH_JNR_DIMM_CFG_FREQ_SHFT                32
+#define SH_JNR_DIMM_CFG_FREQ_MASK                0x0000000f00000000
+
+/* ==================================================================== */
+/*                      Register "SH_X_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#define SH_X_PHASE_CFG                           0x0000000100010018
+#define SH_X_PHASE_CFG_MASK                      0x7fffffffffffffff
+#define SH_X_PHASE_CFG_INIT                      0x0000000000000000
+
+/*   SH_X_PHASE_CFG_LD_A                                                */
+/*   Description:  Address, control load core clock A latch             */
+#define SH_X_PHASE_CFG_LD_A_SHFT                 0
+#define SH_X_PHASE_CFG_LD_A_MASK                 0x000000000000001f
+
+/*   SH_X_PHASE_CFG_LD_B                                                */
+/*   Description:  Address, control load core clock B latch             */
+#define SH_X_PHASE_CFG_LD_B_SHFT                 5
+#define SH_X_PHASE_CFG_LD_B_MASK                 0x00000000000003e0
+
+/*   SH_X_PHASE_CFG_DQ_LD_A                                             */
+/*   Description:  DATA MCI load core clock A latch                     */
+#define SH_X_PHASE_CFG_DQ_LD_A_SHFT              10
+#define SH_X_PHASE_CFG_DQ_LD_A_MASK              0x0000000000007c00
+
+/*   SH_X_PHASE_CFG_DQ_LD_B                                             */
+/*   Description:  DATA MCI load core clock B latch                     */
+#define SH_X_PHASE_CFG_DQ_LD_B_SHFT              15
+#define SH_X_PHASE_CFG_DQ_LD_B_MASK              0x00000000000f8000
+
+/*   SH_X_PHASE_CFG_HOLD                                                */
+/*   Description:  Hold request on core clock phase                     */
+#define SH_X_PHASE_CFG_HOLD_SHFT                 20
+#define SH_X_PHASE_CFG_HOLD_MASK                 0x0000000001f00000
+
+/*   SH_X_PHASE_CFG_HOLD_REQ                                            */
+/*   Description:  Hold next request on core clock phase                */
+#define SH_X_PHASE_CFG_HOLD_REQ_SHFT             25
+#define SH_X_PHASE_CFG_HOLD_REQ_MASK             0x000000003e000000
+
+/*   SH_X_PHASE_CFG_ADD_CP                                              */
+/*   Description:  add delay clock period to dqct delay chain on phase  */
+#define SH_X_PHASE_CFG_ADD_CP_SHFT               30
+#define SH_X_PHASE_CFG_ADD_CP_MASK               0x00000007c0000000
+
+/*   SH_X_PHASE_CFG_BUBBLE_EN                                           */
+/*   Description:  bubble, idle core clock to wait for memory clock     */
+#define SH_X_PHASE_CFG_BUBBLE_EN_SHFT            35
+#define SH_X_PHASE_CFG_BUBBLE_EN_MASK            0x000000f800000000
+
+/*   SH_X_PHASE_CFG_PHA_BUBBLE                                          */
+/*   Description:  MMR phaseA bubble value                              */
+#define SH_X_PHASE_CFG_PHA_BUBBLE_SHFT           40
+#define SH_X_PHASE_CFG_PHA_BUBBLE_MASK           0x0000070000000000
+
+/*   SH_X_PHASE_CFG_PHB_BUBBLE                                          */
+/*   Description:  MMR phaseB bubble value                              */
+#define SH_X_PHASE_CFG_PHB_BUBBLE_SHFT           43
+#define SH_X_PHASE_CFG_PHB_BUBBLE_MASK           0x0000380000000000
+
+/*   SH_X_PHASE_CFG_PHC_BUBBLE                                          */
+/*   Description:  MMR phaseC bubble value                              */
+#define SH_X_PHASE_CFG_PHC_BUBBLE_SHFT           46
+#define SH_X_PHASE_CFG_PHC_BUBBLE_MASK           0x0001c00000000000
+
+/*   SH_X_PHASE_CFG_PHD_BUBBLE                                          */
+/*   Description:  MMR phaseD bubble value                              */
+#define SH_X_PHASE_CFG_PHD_BUBBLE_SHFT           49
+#define SH_X_PHASE_CFG_PHD_BUBBLE_MASK           0x000e000000000000
+
+/*   SH_X_PHASE_CFG_PHE_BUBBLE                                          */
+/*   Description:  MMR phaseE bubble value                              */
+#define SH_X_PHASE_CFG_PHE_BUBBLE_SHFT           52
+#define SH_X_PHASE_CFG_PHE_BUBBLE_MASK           0x0070000000000000
+
+/*   SH_X_PHASE_CFG_SEL_A                                               */
+/*   Description:  address,control select A memory clock latch          */
+#define SH_X_PHASE_CFG_SEL_A_SHFT                55
+#define SH_X_PHASE_CFG_SEL_A_MASK                0x0780000000000000
+
+/*   SH_X_PHASE_CFG_DQ_SEL_A                                            */
+/*   Description:  DATA MCI select A memory clock latch                 */
+#define SH_X_PHASE_CFG_DQ_SEL_A_SHFT             59
+#define SH_X_PHASE_CFG_DQ_SEL_A_MASK             0x7800000000000000
+
+/* ==================================================================== */
+/*                         Register "SH_X_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_X_CFG                                 0x0000000100010020
+#define SH_X_CFG_MASK                            0xffffffffffffffff
+#define SH_X_CFG_INIT                            0x108443103322100c
+
+/*   SH_X_CFG_MODE_SERIAL                                               */
+/*   Description:  Arbque arbitration in serial mode                    */
+#define SH_X_CFG_MODE_SERIAL_SHFT                0
+#define SH_X_CFG_MODE_SERIAL_MASK                0x0000000000000001
+
+/*   SH_X_CFG_DIRC_RANDOM_REPLACEMENT                                   */
+/*   Description:  Directory cache random replacement                   */
+#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_SHFT    1
+#define SH_X_CFG_DIRC_RANDOM_REPLACEMENT_MASK    0x0000000000000002
+
+/*   SH_X_CFG_DIR_COUNTER_INIT                                          */
+/*   Description:  Dir counter initial value                            */
+#define SH_X_CFG_DIR_COUNTER_INIT_SHFT           2
+#define SH_X_CFG_DIR_COUNTER_INIT_MASK           0x00000000000000fc
+
+/*   SH_X_CFG_TA_DLYS                                                   */
+/*   Description:  Turn around delays                                   */
+#define SH_X_CFG_TA_DLYS_SHFT                    8
+#define SH_X_CFG_TA_DLYS_MASK                    0x000000ffffffff00
+
+/*   SH_X_CFG_DA_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a data read request                */
+#define SH_X_CFG_DA_BB_CLR_SHFT                  40
+#define SH_X_CFG_DA_BB_CLR_MASK                  0x00000f0000000000
+
+/*   SH_X_CFG_DC_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a directory cache read request     */
+#define SH_X_CFG_DC_BB_CLR_SHFT                  44
+#define SH_X_CFG_DC_BB_CLR_MASK                  0x0000f00000000000
+
+/*   SH_X_CFG_WT_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for all write request                  */
+#define SH_X_CFG_WT_BB_CLR_SHFT                  48
+#define SH_X_CFG_WT_BB_CLR_MASK                  0x000f000000000000
+
+/*   SH_X_CFG_SSO_WT_EN                                                 */
+/*   Description:  Simultaneous switching enabled on output data pins  */
+#define SH_X_CFG_SSO_WT_EN_SHFT                  52
+#define SH_X_CFG_SSO_WT_EN_MASK                  0x0010000000000000
+
+/*   SH_X_CFG_TRCD2_EN                                                  */
+/*   Description:  Trcd, ras to cas delay of 2 CPs enabled              */
+#define SH_X_CFG_TRCD2_EN_SHFT                   53
+#define SH_X_CFG_TRCD2_EN_MASK                   0x0020000000000000
+
+/*   SH_X_CFG_TRCD4_EN                                                  */
+/*   Description:  Trcd, ras to case delay of 4 CPs enabled             */
+#define SH_X_CFG_TRCD4_EN_SHFT                   54
+#define SH_X_CFG_TRCD4_EN_MASK                   0x0040000000000000
+
+/*   SH_X_CFG_REQ_CNTR_DIS                                              */
+/*   Description:  Request delay counter disabled                       */
+#define SH_X_CFG_REQ_CNTR_DIS_SHFT               55
+#define SH_X_CFG_REQ_CNTR_DIS_MASK               0x0080000000000000
+
+/*   SH_X_CFG_REQ_CNTR_VAL                                              */
+/*   Description:  Request counter delay value in CPs                   */
+#define SH_X_CFG_REQ_CNTR_VAL_SHFT               56
+#define SH_X_CFG_REQ_CNTR_VAL_MASK               0x3f00000000000000
+
+/*   SH_X_CFG_INV_CAS_ADDR                                              */
+/*   Description:  Invert cas address bits 3 to 7                       */
+#define SH_X_CFG_INV_CAS_ADDR_SHFT               62
+#define SH_X_CFG_INV_CAS_ADDR_MASK               0x4000000000000000
+
+/*   SH_X_CFG_CLR_DIR_CACHE                                             */
+/*   Description:  Clear directory cache tags                           */
+#define SH_X_CFG_CLR_DIR_CACHE_SHFT              63
+#define SH_X_CFG_CLR_DIR_CACHE_MASK              0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_X_DQCT_CFG                            0x0000000100010028
+#define SH_X_DQCT_CFG_MASK                       0x0000000000ffffff
+#define SH_X_DQCT_CFG_INIT                       0x0000000000585418
+
+/*   SH_X_DQCT_CFG_RD_SEL                                               */
+/*   Description:  Read data select                                     */
+#define SH_X_DQCT_CFG_RD_SEL_SHFT                0
+#define SH_X_DQCT_CFG_RD_SEL_MASK                0x000000000000000f
+
+/*   SH_X_DQCT_CFG_WT_SEL                                               */
+/*   Description:  Write data select                                    */
+#define SH_X_DQCT_CFG_WT_SEL_SHFT                4
+#define SH_X_DQCT_CFG_WT_SEL_MASK                0x00000000000000f0
+
+/*   SH_X_DQCT_CFG_DTA_RD_SEL                                           */
+/*   Description:  Data ready read select                               */
+#define SH_X_DQCT_CFG_DTA_RD_SEL_SHFT            8
+#define SH_X_DQCT_CFG_DTA_RD_SEL_MASK            0x0000000000000f00
+
+/*   SH_X_DQCT_CFG_DTA_WT_SEL                                           */
+/*   Description:  Data ready write select                              */
+#define SH_X_DQCT_CFG_DTA_WT_SEL_SHFT            12
+#define SH_X_DQCT_CFG_DTA_WT_SEL_MASK            0x000000000000f000
+
+/*   SH_X_DQCT_CFG_DIR_RD_SEL                                           */
+/*   Description:  Dir ready read select                                */
+#define SH_X_DQCT_CFG_DIR_RD_SEL_SHFT            16
+#define SH_X_DQCT_CFG_DIR_RD_SEL_MASK            0x00000000000f0000
+
+/*   SH_X_DQCT_CFG_MDIR_RD_SEL                                          */
+/*   Description:  Dir ready read select                                */
+#define SH_X_DQCT_CFG_MDIR_RD_SEL_SHFT           20
+#define SH_X_DQCT_CFG_MDIR_RD_SEL_MASK           0x0000000000f00000
+
+/* ==================================================================== */
+/*                   Register "SH_X_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#define SH_X_REFRESH_CONTROL                     0x0000000100010030
+#define SH_X_REFRESH_CONTROL_MASK                0x000000000fffffff
+#define SH_X_REFRESH_CONTROL_INIT                0x00000000009cc300
+
+/*   SH_X_REFRESH_CONTROL_ENABLE                                        */
+/*   Description:  Refresh enable                                       */
+#define SH_X_REFRESH_CONTROL_ENABLE_SHFT         0
+#define SH_X_REFRESH_CONTROL_ENABLE_MASK         0x00000000000000ff
+
+/*   SH_X_REFRESH_CONTROL_INTERVAL                                      */
+/*   Description:  Refresh interval in core CPs                         */
+#define SH_X_REFRESH_CONTROL_INTERVAL_SHFT       8
+#define SH_X_REFRESH_CONTROL_INTERVAL_MASK       0x000000000001ff00
+
+/*   SH_X_REFRESH_CONTROL_HOLD                                          */
+/*   Description:  Refresh hold                                         */
+#define SH_X_REFRESH_CONTROL_HOLD_SHFT           17
+#define SH_X_REFRESH_CONTROL_HOLD_MASK           0x00000000007e0000
+
+/*   SH_X_REFRESH_CONTROL_INTERLEAVE                                    */
+/*   Description:  Refresh interleave                                   */
+#define SH_X_REFRESH_CONTROL_INTERLEAVE_SHFT     23
+#define SH_X_REFRESH_CONTROL_INTERLEAVE_MASK     0x0000000000800000
+
+/*   SH_X_REFRESH_CONTROL_HALF_RATE                                     */
+/*   Description:  Refresh half rate                                    */
+#define SH_X_REFRESH_CONTROL_HALF_RATE_SHFT      24
+#define SH_X_REFRESH_CONTROL_HALF_RATE_MASK      0x000000000f000000
+
+/* ==================================================================== */
+/*                      Register "SH_Y_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#define SH_Y_PHASE_CFG                           0x0000000100010038
+#define SH_Y_PHASE_CFG_MASK                      0x7fffffffffffffff
+#define SH_Y_PHASE_CFG_INIT                      0x0000000000000000
+
+/*   SH_Y_PHASE_CFG_LD_A                                                */
+/*   Description:  Address, control load core clock A latch             */
+#define SH_Y_PHASE_CFG_LD_A_SHFT                 0
+#define SH_Y_PHASE_CFG_LD_A_MASK                 0x000000000000001f
+
+/*   SH_Y_PHASE_CFG_LD_B                                                */
+/*   Description:  Address, control load core clock B latch             */
+#define SH_Y_PHASE_CFG_LD_B_SHFT                 5
+#define SH_Y_PHASE_CFG_LD_B_MASK                 0x00000000000003e0
+
+/*   SH_Y_PHASE_CFG_DQ_LD_A                                             */
+/*   Description:  DATA MCI load core clock A latch                     */
+#define SH_Y_PHASE_CFG_DQ_LD_A_SHFT              10
+#define SH_Y_PHASE_CFG_DQ_LD_A_MASK              0x0000000000007c00
+
+/*   SH_Y_PHASE_CFG_DQ_LD_B                                             */
+/*   Description:  DATA MCI load core clock B latch                     */
+#define SH_Y_PHASE_CFG_DQ_LD_B_SHFT              15
+#define SH_Y_PHASE_CFG_DQ_LD_B_MASK              0x00000000000f8000
+
+/*   SH_Y_PHASE_CFG_HOLD                                                */
+/*   Description:  Hold request on core clock phase                     */
+#define SH_Y_PHASE_CFG_HOLD_SHFT                 20
+#define SH_Y_PHASE_CFG_HOLD_MASK                 0x0000000001f00000
+
+/*   SH_Y_PHASE_CFG_HOLD_REQ                                            */
+/*   Description:  Hold next request on core clock phase                */
+#define SH_Y_PHASE_CFG_HOLD_REQ_SHFT             25
+#define SH_Y_PHASE_CFG_HOLD_REQ_MASK             0x000000003e000000
+
+/*   SH_Y_PHASE_CFG_ADD_CP                                              */
+/*   Description:  add delay clock period to dqct delay chain on phase  */
+#define SH_Y_PHASE_CFG_ADD_CP_SHFT               30
+#define SH_Y_PHASE_CFG_ADD_CP_MASK               0x00000007c0000000
+
+/*   SH_Y_PHASE_CFG_BUBBLE_EN                                           */
+/*   Description:  bubble, idle core clock to wait for memory clock     */
+#define SH_Y_PHASE_CFG_BUBBLE_EN_SHFT            35
+#define SH_Y_PHASE_CFG_BUBBLE_EN_MASK            0x000000f800000000
+
+/*   SH_Y_PHASE_CFG_PHA_BUBBLE                                          */
+/*   Description:  MMR phaseA bubble value                              */
+#define SH_Y_PHASE_CFG_PHA_BUBBLE_SHFT           40
+#define SH_Y_PHASE_CFG_PHA_BUBBLE_MASK           0x0000070000000000
+
+/*   SH_Y_PHASE_CFG_PHB_BUBBLE                                          */
+/*   Description:  MMR phaseB bubble value                              */
+#define SH_Y_PHASE_CFG_PHB_BUBBLE_SHFT           43
+#define SH_Y_PHASE_CFG_PHB_BUBBLE_MASK           0x0000380000000000
+
+/*   SH_Y_PHASE_CFG_PHC_BUBBLE                                          */
+/*   Description:  MMR phaseC bubble value                              */
+#define SH_Y_PHASE_CFG_PHC_BUBBLE_SHFT           46
+#define SH_Y_PHASE_CFG_PHC_BUBBLE_MASK           0x0001c00000000000
+
+/*   SH_Y_PHASE_CFG_PHD_BUBBLE                                          */
+/*   Description:  MMR phaseD bubble value                              */
+#define SH_Y_PHASE_CFG_PHD_BUBBLE_SHFT           49
+#define SH_Y_PHASE_CFG_PHD_BUBBLE_MASK           0x000e000000000000
+
+/*   SH_Y_PHASE_CFG_PHE_BUBBLE                                          */
+/*   Description:  MMR phaseE bubble value                              */
+#define SH_Y_PHASE_CFG_PHE_BUBBLE_SHFT           52
+#define SH_Y_PHASE_CFG_PHE_BUBBLE_MASK           0x0070000000000000
+
+/*   SH_Y_PHASE_CFG_SEL_A                                               */
+/*   Description:  address,control select A memory clock latch          */
+#define SH_Y_PHASE_CFG_SEL_A_SHFT                55
+#define SH_Y_PHASE_CFG_SEL_A_MASK                0x0780000000000000
+
+/*   SH_Y_PHASE_CFG_DQ_SEL_A                                            */
+/*   Description:  DATA MCI select A memory clock latch                 */
+#define SH_Y_PHASE_CFG_DQ_SEL_A_SHFT             59
+#define SH_Y_PHASE_CFG_DQ_SEL_A_MASK             0x7800000000000000
+
+/* ==================================================================== */
+/*                         Register "SH_Y_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_Y_CFG                                 0x0000000100010040
+#define SH_Y_CFG_MASK                            0xffffffffffffffff
+#define SH_Y_CFG_INIT                            0x108443103322100c
+
+/*   SH_Y_CFG_MODE_SERIAL                                               */
+/*   Description:  Arbque arbitration in serial mode                    */
+#define SH_Y_CFG_MODE_SERIAL_SHFT                0
+#define SH_Y_CFG_MODE_SERIAL_MASK                0x0000000000000001
+
+/*   SH_Y_CFG_DIRC_RANDOM_REPLACEMENT                                   */
+/*   Description:  Directory cache random replacement                   */
+#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_SHFT    1
+#define SH_Y_CFG_DIRC_RANDOM_REPLACEMENT_MASK    0x0000000000000002
+
+/*   SH_Y_CFG_DIR_COUNTER_INIT                                          */
+/*   Description:  Dir counter initial value                            */
+#define SH_Y_CFG_DIR_COUNTER_INIT_SHFT           2
+#define SH_Y_CFG_DIR_COUNTER_INIT_MASK           0x00000000000000fc
+
+/*   SH_Y_CFG_TA_DLYS                                                   */
+/*   Description:  Turn around delays                                   */
+#define SH_Y_CFG_TA_DLYS_SHFT                    8
+#define SH_Y_CFG_TA_DLYS_MASK                    0x000000ffffffff00
+
+/*   SH_Y_CFG_DA_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a data read request                */
+#define SH_Y_CFG_DA_BB_CLR_SHFT                  40
+#define SH_Y_CFG_DA_BB_CLR_MASK                  0x00000f0000000000
+
+/*   SH_Y_CFG_DC_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for a directory cache read request     */
+#define SH_Y_CFG_DC_BB_CLR_SHFT                  44
+#define SH_Y_CFG_DC_BB_CLR_MASK                  0x0000f00000000000
+
+/*   SH_Y_CFG_WT_BB_CLR                                                 */
+/*   Description:  Bank busy CPs for all write request                  */
+#define SH_Y_CFG_WT_BB_CLR_SHFT                  48
+#define SH_Y_CFG_WT_BB_CLR_MASK                  0x000f000000000000
+
+/*   SH_Y_CFG_SSO_WT_EN                                                 */
+/*   Description:  Simultaneous switching enabled on output data pins  */
+#define SH_Y_CFG_SSO_WT_EN_SHFT                  52
+#define SH_Y_CFG_SSO_WT_EN_MASK                  0x0010000000000000
+
+/*   SH_Y_CFG_TRCD2_EN                                                  */
+/*   Description:  Trcd, ras to cas delay of 2 CPs enabled              */
+#define SH_Y_CFG_TRCD2_EN_SHFT                   53
+#define SH_Y_CFG_TRCD2_EN_MASK                   0x0020000000000000
+
+/*   SH_Y_CFG_TRCD4_EN                                                  */
+/*   Description:  Trcd, ras to case delay of 4 CPs enabled             */
+#define SH_Y_CFG_TRCD4_EN_SHFT                   54
+#define SH_Y_CFG_TRCD4_EN_MASK                   0x0040000000000000
+
+/*   SH_Y_CFG_REQ_CNTR_DIS                                              */
+/*   Description:  Request delay counter disabled                       */
+#define SH_Y_CFG_REQ_CNTR_DIS_SHFT               55
+#define SH_Y_CFG_REQ_CNTR_DIS_MASK               0x0080000000000000
+
+/*   SH_Y_CFG_REQ_CNTR_VAL                                              */
+/*   Description:  Request counter delay value in CPs                   */
+#define SH_Y_CFG_REQ_CNTR_VAL_SHFT               56
+#define SH_Y_CFG_REQ_CNTR_VAL_MASK               0x3f00000000000000
+
+/*   SH_Y_CFG_INV_CAS_ADDR                                              */
+/*   Description:  Invert cas address bits 3 to 7                       */
+#define SH_Y_CFG_INV_CAS_ADDR_SHFT               62
+#define SH_Y_CFG_INV_CAS_ADDR_MASK               0x4000000000000000
+
+/*   SH_Y_CFG_CLR_DIR_CACHE                                             */
+/*   Description:  Clear directory cache tags                           */
+#define SH_Y_CFG_CLR_DIR_CACHE_SHFT              63
+#define SH_Y_CFG_CLR_DIR_CACHE_MASK              0x8000000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#define SH_Y_DQCT_CFG                            0x0000000100010048
+#define SH_Y_DQCT_CFG_MASK                       0x0000000000ffffff
+#define SH_Y_DQCT_CFG_INIT                       0x0000000000585418
+
+/*   SH_Y_DQCT_CFG_RD_SEL                                               */
+/*   Description:  Read data select                                     */
+#define SH_Y_DQCT_CFG_RD_SEL_SHFT                0
+#define SH_Y_DQCT_CFG_RD_SEL_MASK                0x000000000000000f
+
+/*   SH_Y_DQCT_CFG_WT_SEL                                               */
+/*   Description:  Write data select                                    */
+#define SH_Y_DQCT_CFG_WT_SEL_SHFT                4
+#define SH_Y_DQCT_CFG_WT_SEL_MASK                0x00000000000000f0
+
+/*   SH_Y_DQCT_CFG_DTA_RD_SEL                                           */
+/*   Description:  Data ready read select                               */
+#define SH_Y_DQCT_CFG_DTA_RD_SEL_SHFT            8
+#define SH_Y_DQCT_CFG_DTA_RD_SEL_MASK            0x0000000000000f00
+
+/*   SH_Y_DQCT_CFG_DTA_WT_SEL                                           */
+/*   Description:  Data ready write select                              */
+#define SH_Y_DQCT_CFG_DTA_WT_SEL_SHFT            12
+#define SH_Y_DQCT_CFG_DTA_WT_SEL_MASK            0x000000000000f000
+
+/*   SH_Y_DQCT_CFG_DIR_RD_SEL                                           */
+/*   Description:  Dir ready read select                                */
+#define SH_Y_DQCT_CFG_DIR_RD_SEL_SHFT            16
+#define SH_Y_DQCT_CFG_DIR_RD_SEL_MASK            0x00000000000f0000
+
+/*   SH_Y_DQCT_CFG_MDIR_RD_SEL                                          */
+/*   Description:  Dir ready read select                                */
+#define SH_Y_DQCT_CFG_MDIR_RD_SEL_SHFT           20
+#define SH_Y_DQCT_CFG_MDIR_RD_SEL_MASK           0x0000000000f00000
+
+/* ==================================================================== */
+/*                   Register "SH_Y_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#define SH_Y_REFRESH_CONTROL                     0x0000000100010050
+#define SH_Y_REFRESH_CONTROL_MASK                0x000000000fffffff
+#define SH_Y_REFRESH_CONTROL_INIT                0x00000000009cc300
+
+/*   SH_Y_REFRESH_CONTROL_ENABLE                                        */
+/*   Description:  Refresh enable                                       */
+#define SH_Y_REFRESH_CONTROL_ENABLE_SHFT         0
+#define SH_Y_REFRESH_CONTROL_ENABLE_MASK         0x00000000000000ff
+
+/*   SH_Y_REFRESH_CONTROL_INTERVAL                                      */
+/*   Description:  Refresh interval in core CPs                         */
+#define SH_Y_REFRESH_CONTROL_INTERVAL_SHFT       8
+#define SH_Y_REFRESH_CONTROL_INTERVAL_MASK       0x000000000001ff00
+
+/*   SH_Y_REFRESH_CONTROL_HOLD                                          */
+/*   Description:  Refresh hold                                         */
+#define SH_Y_REFRESH_CONTROL_HOLD_SHFT           17
+#define SH_Y_REFRESH_CONTROL_HOLD_MASK           0x00000000007e0000
+
+/*   SH_Y_REFRESH_CONTROL_INTERLEAVE                                    */
+/*   Description:  Refresh interleave                                   */
+#define SH_Y_REFRESH_CONTROL_INTERLEAVE_SHFT     23
+#define SH_Y_REFRESH_CONTROL_INTERLEAVE_MASK     0x0000000000800000
+
+/*   SH_Y_REFRESH_CONTROL_HALF_RATE                                     */
+/*   Description:  Refresh half rate                                    */
+#define SH_Y_REFRESH_CONTROL_HALF_RATE_SHFT      24
+#define SH_Y_REFRESH_CONTROL_HALF_RATE_MASK      0x000000000f000000
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_RED_BLACK"                      */
+/*                     MD fairness watchdog timers                      */
+/* ==================================================================== */
+
+#define SH_MEM_RED_BLACK                         0x0000000100010058
+#define SH_MEM_RED_BLACK_MASK                    0x000fffffffffffff
+#define SH_MEM_RED_BLACK_INIT                    0x0000000040000400
+
+/*   SH_MEM_RED_BLACK_TIME                                              */
+/*   Description:  Clocks to tag references with a given color          */
+#define SH_MEM_RED_BLACK_TIME_SHFT               0
+#define SH_MEM_RED_BLACK_TIME_MASK               0x000000000000ffff
+
+/*   SH_MEM_RED_BLACK_ERR_TIME                                          */
+/*   Description:  Max clocks to wait after red/black change for old c  */
+/*  olor to clear.                                                      */
+#define SH_MEM_RED_BLACK_ERR_TIME_SHFT           16
+#define SH_MEM_RED_BLACK_ERR_TIME_MASK           0x000fffffffff0000
+
+/* ==================================================================== */
+/*                      Register "SH_MISC_MEM_CFG"                      */
+/* ==================================================================== */
+
+#define SH_MISC_MEM_CFG                          0x0000000100010060
+#define SH_MISC_MEM_CFG_MASK                     0x0013f1f1fff3f3ff
+#define SH_MISC_MEM_CFG_INIT                     0x0000000000010107
+
+/*   SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE                              */
+/*   Description:  enables the use of express headers from md to pi     */
+#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_SHFT 0
+#define SH_MISC_MEM_CFG_EXPRESS_HEADER_ENABLE_MASK 0x0000000000000001
+
+/*   SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE                                 */
+/*   Description:  enables the use of speculative headers from md to p  */
+#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_SHFT  1
+#define SH_MISC_MEM_CFG_SPEC_HEADER_ENABLE_MASK  0x0000000000000002
+
+/*   SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE                                  */
+/*   Description:  enables bypass path for requests going through ac    */
+#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_SHFT   2
+#define SH_MISC_MEM_CFG_JNR_BYPASS_ENABLE_MASK   0x0000000000000004
+
+/*   SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI                                   */
+/*   Description:  disables a one clock delay of XN read data           */
+#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_SHFT    3
+#define SH_MISC_MEM_CFG_XN_RD_SAME_AS_PI_MASK    0x0000000000000008
+
+/*   SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD                         */
+/*   Description:  point at which data writes get higher priority       */
+#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_SHFT 4
+#define SH_MISC_MEM_CFG_LOW_WRITE_BUFFER_THRESHOLD_MASK 0x00000000000003f0
+
+/*   SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD                        */
+/*   Description:  point at which dir cache writes get higher priority  */
+#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_SHFT 12
+#define SH_MISC_MEM_CFG_LOW_VICTIM_BUFFER_THRESHOLD_MASK 0x000000000003f000
+
+/*   SH_MISC_MEM_CFG_THROTTLE_CNT                                       */
+/*   Description:  number of clocks between accepting references        */
+#define SH_MISC_MEM_CFG_THROTTLE_CNT_SHFT        20
+#define SH_MISC_MEM_CFG_THROTTLE_CNT_MASK        0x000000000ff00000
+
+/*   SH_MISC_MEM_CFG_DISABLED_READ_TNUMS                                */
+/*   Description:  number of read tnums to take out of circulation      */
+#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_SHFT 28
+#define SH_MISC_MEM_CFG_DISABLED_READ_TNUMS_MASK 0x00000001f0000000
+
+/*   SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS                               */
+/*   Description:  number of write tnums to take out of circulation     */
+#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_SHFT 36
+#define SH_MISC_MEM_CFG_DISABLED_WRITE_TNUMS_MASK 0x000001f000000000
+
+/*   SH_MISC_MEM_CFG_DISABLED_VICTIMS                                   */
+/*   Description:  number of dir cache victim buffers to take out of c  */
+/*  irculation in each quadrant of the MD                               */
+#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_SHFT    44
+#define SH_MISC_MEM_CFG_DISABLED_VICTIMS_MASK    0x0003f00000000000
+
+/*   SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE                              */
+/*   Description:  enables plane alternating for replies to XN          */
+#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_SHFT 52
+#define SH_MISC_MEM_CFG_ALTERNATE_XN_RP_PLANE_MASK 0x0010000000000000
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_RQ_CRD_CTL"                     */
+/*                  pio_rq Credit Circulation Control                   */
+/* ==================================================================== */
+
+#define SH_PIO_RQ_CRD_CTL                        0x0000000100010068
+#define SH_PIO_RQ_CRD_CTL_MASK                   0x000000000000003f
+#define SH_PIO_RQ_CRD_CTL_INIT                   0x0000000000000002
+
+/*   SH_PIO_RQ_CRD_CTL_DEPTH                                            */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_PIO_RQ_CRD_CTL_DEPTH_SHFT             0
+#define SH_PIO_RQ_CRD_CTL_DEPTH_MASK             0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RQ_CRD_CTL"                    */
+/*                 pi_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_PI_MD_RQ_CRD_CTL                      0x0000000100010070
+#define SH_PI_MD_RQ_CRD_CTL_MASK                 0x000000000000003f
+#define SH_PI_MD_RQ_CRD_CTL_INIT                 0x0000000000000008
+
+/*   SH_PI_MD_RQ_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_PI_MD_RQ_CRD_CTL_DEPTH_SHFT           0
+#define SH_PI_MD_RQ_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RP_CRD_CTL"                    */
+/*                 pi_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_PI_MD_RP_CRD_CTL                      0x0000000100010078
+#define SH_PI_MD_RP_CRD_CTL_MASK                 0x000000000000003f
+#define SH_PI_MD_RP_CRD_CTL_INIT                 0x0000000000000004
+
+/*   SH_PI_MD_RP_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_PI_MD_RP_CRD_CTL_DEPTH_SHFT           0
+#define SH_PI_MD_RP_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RQ_CRD_CTL"                    */
+/*                 xn_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_RQ_CRD_CTL                      0x0000000100010080
+#define SH_XN_MD_RQ_CRD_CTL_MASK                 0x000000000000003f
+#define SH_XN_MD_RQ_CRD_CTL_INIT                 0x0000000000000008
+
+/*   SH_XN_MD_RQ_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_XN_MD_RQ_CRD_CTL_DEPTH_SHFT           0
+#define SH_XN_MD_RQ_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RP_CRD_CTL"                    */
+/*                 xn_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#define SH_XN_MD_RP_CRD_CTL                      0x0000000100010088
+#define SH_XN_MD_RP_CRD_CTL_MASK                 0x000000000000003f
+#define SH_XN_MD_RP_CRD_CTL_INIT                 0x0000000000000004
+
+/*   SH_XN_MD_RP_CRD_CTL_DEPTH                                          */
+/*   Description:  Total depth of buffering (in sic packets)            */
+#define SH_XN_MD_RP_CRD_CTL_DEPTH_SHFT           0
+#define SH_XN_MD_RP_CRD_CTL_DEPTH_MASK           0x000000000000003f
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG0                                0x0000000100020000
+#define SH_X_TAG0_MASK                           0x00000000000fffff
+#define SH_X_TAG0_INIT                           0x0000000000000000
+
+/*   SH_X_TAG0_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG0_TAG_SHFT                       0
+#define SH_X_TAG0_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG1                                0x0000000100020008
+#define SH_X_TAG1_MASK                           0x00000000000fffff
+#define SH_X_TAG1_INIT                           0x0000000000000000
+
+/*   SH_X_TAG1_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG1_TAG_SHFT                       0
+#define SH_X_TAG1_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG2                                0x0000000100020010
+#define SH_X_TAG2_MASK                           0x00000000000fffff
+#define SH_X_TAG2_INIT                           0x0000000000000000
+
+/*   SH_X_TAG2_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG2_TAG_SHFT                       0
+#define SH_X_TAG2_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG3                                0x0000000100020018
+#define SH_X_TAG3_MASK                           0x00000000000fffff
+#define SH_X_TAG3_INIT                           0x0000000000000000
+
+/*   SH_X_TAG3_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG3_TAG_SHFT                       0
+#define SH_X_TAG3_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG4                                0x0000000100020020
+#define SH_X_TAG4_MASK                           0x00000000000fffff
+#define SH_X_TAG4_INIT                           0x0000000000000000
+
+/*   SH_X_TAG4_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG4_TAG_SHFT                       0
+#define SH_X_TAG4_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG5                                0x0000000100020028
+#define SH_X_TAG5_MASK                           0x00000000000fffff
+#define SH_X_TAG5_INIT                           0x0000000000000000
+
+/*   SH_X_TAG5_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG5_TAG_SHFT                       0
+#define SH_X_TAG5_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG6                                0x0000000100020030
+#define SH_X_TAG6_MASK                           0x00000000000fffff
+#define SH_X_TAG6_INIT                           0x0000000000000000
+
+/*   SH_X_TAG6_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG6_TAG_SHFT                       0
+#define SH_X_TAG6_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_X_TAG7                                0x0000000100020038
+#define SH_X_TAG7_MASK                           0x00000000000fffff
+#define SH_X_TAG7_INIT                           0x0000000000000000
+
+/*   SH_X_TAG7_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_X_TAG7_TAG_SHFT                       0
+#define SH_X_TAG7_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG0                                0x0000000100020040
+#define SH_Y_TAG0_MASK                           0x00000000000fffff
+#define SH_Y_TAG0_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG0_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG0_TAG_SHFT                       0
+#define SH_Y_TAG0_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG1                                0x0000000100020048
+#define SH_Y_TAG1_MASK                           0x00000000000fffff
+#define SH_Y_TAG1_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG1_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG1_TAG_SHFT                       0
+#define SH_Y_TAG1_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG2                                0x0000000100020050
+#define SH_Y_TAG2_MASK                           0x00000000000fffff
+#define SH_Y_TAG2_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG2_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG2_TAG_SHFT                       0
+#define SH_Y_TAG2_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG3                                0x0000000100020058
+#define SH_Y_TAG3_MASK                           0x00000000000fffff
+#define SH_Y_TAG3_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG3_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG3_TAG_SHFT                       0
+#define SH_Y_TAG3_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG4                                0x0000000100020060
+#define SH_Y_TAG4_MASK                           0x00000000000fffff
+#define SH_Y_TAG4_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG4_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG4_TAG_SHFT                       0
+#define SH_Y_TAG4_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG5                                0x0000000100020068
+#define SH_Y_TAG5_MASK                           0x00000000000fffff
+#define SH_Y_TAG5_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG5_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG5_TAG_SHFT                       0
+#define SH_Y_TAG5_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG6                                0x0000000100020070
+#define SH_Y_TAG6_MASK                           0x00000000000fffff
+#define SH_Y_TAG6_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG6_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG6_TAG_SHFT                       0
+#define SH_Y_TAG6_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#define SH_Y_TAG7                                0x0000000100020078
+#define SH_Y_TAG7_MASK                           0x00000000000fffff
+#define SH_Y_TAG7_INIT                           0x0000000000000000
+
+/*   SH_Y_TAG7_TAG                                                      */
+/*   Description:  Valid + Tag Address                                  */
+#define SH_Y_TAG7_TAG_SHFT                       0
+#define SH_Y_TAG7_TAG_MASK                       0x00000000000fffff
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_BASE"                      */
+/*                        mmr/bist base address                         */
+/* ==================================================================== */
+
+#define SH_MMRBIST_BASE                          0x0000000100020080
+#define SH_MMRBIST_BASE_MASK                     0x0003fffffffffff8
+#define SH_MMRBIST_BASE_INIT                     0x0000000000000000
+
+/*   SH_MMRBIST_BASE_DWORD_ADDR                                         */
+/*   Description:  bits 49:3 of the memory address                      */
+#define SH_MMRBIST_BASE_DWORD_ADDR_SHFT          3
+#define SH_MMRBIST_BASE_DWORD_ADDR_MASK          0x0003fffffffffff8
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_CTL"                       */
+/*                          Bist base address                           */
+/* ==================================================================== */
+
+#define SH_MMRBIST_CTL                           0x0000000100020088
+#define SH_MMRBIST_CTL_MASK                      0x0000177f7fffffff
+#define SH_MMRBIST_CTL_INIT                      0x0000000000000000
+
+/*   SH_MMRBIST_CTL_BLOCK_LENGTH                                        */
+/*   Description:  number of dwords in operation                        */
+#define SH_MMRBIST_CTL_BLOCK_LENGTH_SHFT         0
+#define SH_MMRBIST_CTL_BLOCK_LENGTH_MASK         0x000000007fffffff
+
+/*   SH_MMRBIST_CTL_CMD                                                 */
+/*   Description:  mmr/bist function                                    */
+#define SH_MMRBIST_CTL_CMD_SHFT                  32
+#define SH_MMRBIST_CTL_CMD_MASK                  0x0000007f00000000
+
+/*   SH_MMRBIST_CTL_IN_PROGRESS                                         */
+/*   Description:  writing a 1 starts operation, hardware clears on co  */
+/*  mpletion                                                            */
+#define SH_MMRBIST_CTL_IN_PROGRESS_SHFT          40
+#define SH_MMRBIST_CTL_IN_PROGRESS_MASK          0x0000010000000000
+
+/*   SH_MMRBIST_CTL_FAIL                                                */
+/*   Description:  mmr/bist had a data or address error                 */
+#define SH_MMRBIST_CTL_FAIL_SHFT                 41
+#define SH_MMRBIST_CTL_FAIL_MASK                 0x0000020000000000
+
+/*   SH_MMRBIST_CTL_MEM_IDLE                                            */
+/*   Description:  all memory activity is complete                      */
+#define SH_MMRBIST_CTL_MEM_IDLE_SHFT             42
+#define SH_MMRBIST_CTL_MEM_IDLE_MASK             0x0000040000000000
+
+/*   SH_MMRBIST_CTL_RESET_STATE                                         */
+/*   Description:  writing a 1 resets mmrbist hardware, hardware clear  */
+/*  s on completion                                                     */
+#define SH_MMRBIST_CTL_RESET_STATE_SHFT          44
+#define SH_MMRBIST_CTL_RESET_STATE_MASK          0x0000100000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_DATA_CFG"                    */
+/*                configuration for md debug data muxes                 */
+/* ==================================================================== */
+
+#define SH_MD_DBUG_DATA_CFG                      0x0000000100020100
+#define SH_MD_DBUG_DATA_CFG_MASK                 0x7777777777777777
+#define SH_MD_DBUG_DATA_CFG_INIT                 0x0000000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble0              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_SHFT 0
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_SHFT  4
+#define SH_MD_DBUG_DATA_CFG_NIBBLE0_NIBBLE_MASK  0x0000000000000070
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble1              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_SHFT 8
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_SHFT  12
+#define SH_MD_DBUG_DATA_CFG_NIBBLE1_NIBBLE_MASK  0x0000000000007000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble2              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_SHFT 16
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_SHFT  20
+#define SH_MD_DBUG_DATA_CFG_NIBBLE2_NIBBLE_MASK  0x0000000000700000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble3              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_SHFT 24
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_SHFT  28
+#define SH_MD_DBUG_DATA_CFG_NIBBLE3_NIBBLE_MASK  0x0000000070000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble4              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_SHFT 32
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_SHFT  36
+#define SH_MD_DBUG_DATA_CFG_NIBBLE4_NIBBLE_MASK  0x0000007000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble5              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_SHFT 40
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_SHFT  44
+#define SH_MD_DBUG_DATA_CFG_NIBBLE5_NIBBLE_MASK  0x0000700000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble6              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_SHFT 48
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_SHFT  52
+#define SH_MD_DBUG_DATA_CFG_NIBBLE6_NIBBLE_MASK  0x0070000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET                                */
+/*   Description:  selects which md chiplet drives nibble7              */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_SHFT 56
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000
+
+/*   SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE                                 */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_SHFT  60
+#define SH_MD_DBUG_DATA_CFG_NIBBLE7_NIBBLE_MASK  0x7000000000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DBUG_TRIGGER_CFG"                   */
+/*                 configuration for md debug triggers                  */
+/* ==================================================================== */
+
+#define SH_MD_DBUG_TRIGGER_CFG                   0x0000000100020108
+#define SH_MD_DBUG_TRIGGER_CFG_MASK              0xf777777777777777
+#define SH_MD_DBUG_TRIGGER_CFG_INIT              0x0000000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble0              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_SHFT 0
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_CHIPLET_MASK 0x0000000000000007
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_SHFT 4
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE0_NIBBLE_MASK 0x0000000000000070
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble1              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_SHFT 8
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_CHIPLET_MASK 0x0000000000000700
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_SHFT 12
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE1_NIBBLE_MASK 0x0000000000007000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble2              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_SHFT 16
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_CHIPLET_MASK 0x0000000000070000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_SHFT 20
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE2_NIBBLE_MASK 0x0000000000700000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble3              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_SHFT 24
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_CHIPLET_MASK 0x0000000007000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_SHFT 28
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE3_NIBBLE_MASK 0x0000000070000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble4              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_SHFT 32
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_CHIPLET_MASK 0x0000000700000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_SHFT 36
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE4_NIBBLE_MASK 0x0000007000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble5              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_SHFT 40
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_CHIPLET_MASK 0x0000070000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_SHFT 44
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE5_NIBBLE_MASK 0x0000700000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble6              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_SHFT 48
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_CHIPLET_MASK 0x0007000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_SHFT 52
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE6_NIBBLE_MASK 0x0070000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET                             */
+/*   Description:  selects which md chiplet drives nibble7              */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_SHFT 56
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_CHIPLET_MASK 0x0700000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE                              */
+/*   Description:  selects which nibble from selected chiplet drives n  */
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_SHFT 60
+#define SH_MD_DBUG_TRIGGER_CFG_NIBBLE7_NIBBLE_MASK 0x7000000000000000
+
+/*   SH_MD_DBUG_TRIGGER_CFG_ENABLE                                      */
+/*   Description:  enables triggering on pattern match                  */
+#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_SHFT       63
+#define SH_MD_DBUG_TRIGGER_CFG_ENABLE_MASK       0x8000000000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_COMPARE"                     */
+/*                  md debug compare pattern and mask                   */
+/* ==================================================================== */
+
+#define SH_MD_DBUG_COMPARE                       0x0000000100020110
+#define SH_MD_DBUG_COMPARE_MASK                  0xffffffffffffffff
+#define SH_MD_DBUG_COMPARE_INIT                  0x0000000000000000
+
+/*   SH_MD_DBUG_COMPARE_PATTERN                                         */
+/*   Description:  pattern against which to compare dbug data for trig  */
+#define SH_MD_DBUG_COMPARE_PATTERN_SHFT          0
+#define SH_MD_DBUG_COMPARE_PATTERN_MASK          0x00000000ffffffff
+
+/*   SH_MD_DBUG_COMPARE_MASK                                            */
+/*   Description:  bits to include in compare of dbug data for trigger  */
+#define SH_MD_DBUG_COMPARE_MASK_SHFT             32
+#define SH_MD_DBUG_COMPARE_MASK_MASK             0xffffffff00000000
+
+/* ==================================================================== */
+/*                     Register "SH_X_MOD_DBUG_SEL"                     */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#define SH_X_MOD_DBUG_SEL                        0x0000000100020118
+#define SH_X_MOD_DBUG_SEL_MASK                   0x03ffffffffffffff
+#define SH_X_MOD_DBUG_SEL_INIT                   0x0000000000000000
+
+/*   SH_X_MOD_DBUG_SEL_TAG_SEL                                          */
+/*   Description:  tagmgr select                                        */
+#define SH_X_MOD_DBUG_SEL_TAG_SEL_SHFT           0
+#define SH_X_MOD_DBUG_SEL_TAG_SEL_MASK           0x00000000000000ff
+
+/*   SH_X_MOD_DBUG_SEL_WBQ_SEL                                          */
+/*   Description:  wbqtg select                                         */
+#define SH_X_MOD_DBUG_SEL_WBQ_SEL_SHFT           8
+#define SH_X_MOD_DBUG_SEL_WBQ_SEL_MASK           0x000000000000ff00
+
+/*   SH_X_MOD_DBUG_SEL_ARB_SEL                                          */
+/*   Description:  arbque select                                        */
+#define SH_X_MOD_DBUG_SEL_ARB_SEL_SHFT           16
+#define SH_X_MOD_DBUG_SEL_ARB_SEL_MASK           0x0000000000ff0000
+
+/*   SH_X_MOD_DBUG_SEL_ATL_SEL                                          */
+/*   Description:  aintl select                                         */
+#define SH_X_MOD_DBUG_SEL_ATL_SEL_SHFT           24
+#define SH_X_MOD_DBUG_SEL_ATL_SEL_MASK           0x00000007ff000000
+
+/*   SH_X_MOD_DBUG_SEL_ATR_SEL                                          */
+/*   Description:  aintr select                                         */
+#define SH_X_MOD_DBUG_SEL_ATR_SEL_SHFT           35
+#define SH_X_MOD_DBUG_SEL_ATR_SEL_MASK           0x00003ff800000000
+
+/*   SH_X_MOD_DBUG_SEL_DQL_SEL                                          */
+/*   Description:  dqctr select                                         */
+#define SH_X_MOD_DBUG_SEL_DQL_SEL_SHFT           46
+#define SH_X_MOD_DBUG_SEL_DQL_SEL_MASK           0x000fc00000000000
+
+/*   SH_X_MOD_DBUG_SEL_DQR_SEL                                          */
+/*   Description:  dqctl select                                         */
+#define SH_X_MOD_DBUG_SEL_DQR_SEL_SHFT           52
+#define SH_X_MOD_DBUG_SEL_DQR_SEL_MASK           0x03f0000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_DBUG_SEL"                       */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#define SH_X_DBUG_SEL                            0x0000000100020120
+#define SH_X_DBUG_SEL_MASK                       0x0000000000ffffff
+#define SH_X_DBUG_SEL_INIT                       0x0000000000000000
+
+/*   SH_X_DBUG_SEL_DBG_SEL                                              */
+/*   Description:  debug select                                         */
+#define SH_X_DBUG_SEL_DBG_SEL_SHFT               0
+#define SH_X_DBUG_SEL_DBG_SEL_MASK               0x0000000000ffffff
+
+/* ==================================================================== */
+/*                      Register "SH_X_LADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#define SH_X_LADDR_CMP                           0x0000000100020128
+#define SH_X_LADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_X_LADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_X_LADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_X_LADDR_CMP_CMP_VAL_SHFT              0
+#define SH_X_LADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_X_LADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_X_LADDR_CMP_MASK_VAL_SHFT             32
+#define SH_X_LADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                      Register "SH_X_RADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#define SH_X_RADDR_CMP                           0x0000000100020130
+#define SH_X_RADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_X_RADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_X_RADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_X_RADDR_CMP_CMP_VAL_SHFT              0
+#define SH_X_RADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_X_RADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_X_RADDR_CMP_MASK_VAL_SHFT             32
+#define SH_X_RADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_CMP"                        */
+/*                        MD acx tagmgr compare                         */
+/* ==================================================================== */
+
+#define SH_X_TAG_CMP                             0x0000000100020138
+#define SH_X_TAG_CMP_MASK                        0x007fffffffffffff
+#define SH_X_TAG_CMP_INIT                        0x0000000000000000
+
+/*   SH_X_TAG_CMP_CMD                                                   */
+/*   Description:  Command compare value                                */
+#define SH_X_TAG_CMP_CMD_SHFT                    0
+#define SH_X_TAG_CMP_CMD_MASK                    0x00000000000000ff
+
+/*   SH_X_TAG_CMP_ADDR                                                  */
+/*   Description:  Address compare value                                */
+#define SH_X_TAG_CMP_ADDR_SHFT                   8
+#define SH_X_TAG_CMP_ADDR_MASK                   0x000001ffffffff00
+
+/*   SH_X_TAG_CMP_SRC                                                   */
+/*   Description:  Source compare value                                 */
+#define SH_X_TAG_CMP_SRC_SHFT                    41
+#define SH_X_TAG_CMP_SRC_MASK                    0x007ffe0000000000
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_MASK"                       */
+/*                          MD acx tagmgr mask                          */
+/* ==================================================================== */
+
+#define SH_X_TAG_MASK                            0x0000000100020140
+#define SH_X_TAG_MASK_MASK                       0x007fffffffffffff
+#define SH_X_TAG_MASK_INIT                       0x0000000000000000
+
+/*   SH_X_TAG_MASK_CMD                                                  */
+/*   Description:  Command compare value                                */
+#define SH_X_TAG_MASK_CMD_SHFT                   0
+#define SH_X_TAG_MASK_CMD_MASK                   0x00000000000000ff
+
+/*   SH_X_TAG_MASK_ADDR                                                 */
+/*   Description:  Address compare value                                */
+#define SH_X_TAG_MASK_ADDR_SHFT                  8
+#define SH_X_TAG_MASK_ADDR_MASK                  0x000001ffffffff00
+
+/*   SH_X_TAG_MASK_SRC                                                  */
+/*   Description:  Source compare value                                 */
+#define SH_X_TAG_MASK_SRC_SHFT                   41
+#define SH_X_TAG_MASK_SRC_MASK                   0x007ffe0000000000
+
+/* ==================================================================== */
+/*                     Register "SH_Y_MOD_DBUG_SEL"                     */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#define SH_Y_MOD_DBUG_SEL                        0x0000000100020148
+#define SH_Y_MOD_DBUG_SEL_MASK                   0x03ffffffffffffff
+#define SH_Y_MOD_DBUG_SEL_INIT                   0x0000000000000000
+
+/*   SH_Y_MOD_DBUG_SEL_TAG_SEL                                          */
+/*   Description:  tagmgr select                                        */
+#define SH_Y_MOD_DBUG_SEL_TAG_SEL_SHFT           0
+#define SH_Y_MOD_DBUG_SEL_TAG_SEL_MASK           0x00000000000000ff
+
+/*   SH_Y_MOD_DBUG_SEL_WBQ_SEL                                          */
+/*   Description:  wbqtg select                                         */
+#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_SHFT           8
+#define SH_Y_MOD_DBUG_SEL_WBQ_SEL_MASK           0x000000000000ff00
+
+/*   SH_Y_MOD_DBUG_SEL_ARB_SEL                                          */
+/*   Description:  arbque select                                        */
+#define SH_Y_MOD_DBUG_SEL_ARB_SEL_SHFT           16
+#define SH_Y_MOD_DBUG_SEL_ARB_SEL_MASK           0x0000000000ff0000
+
+/*   SH_Y_MOD_DBUG_SEL_ATL_SEL                                          */
+/*   Description:  aintl select                                         */
+#define SH_Y_MOD_DBUG_SEL_ATL_SEL_SHFT           24
+#define SH_Y_MOD_DBUG_SEL_ATL_SEL_MASK           0x00000007ff000000
+
+/*   SH_Y_MOD_DBUG_SEL_ATR_SEL                                          */
+/*   Description:  aintr select                                         */
+#define SH_Y_MOD_DBUG_SEL_ATR_SEL_SHFT           35
+#define SH_Y_MOD_DBUG_SEL_ATR_SEL_MASK           0x00003ff800000000
+
+/*   SH_Y_MOD_DBUG_SEL_DQL_SEL                                          */
+/*   Description:  dqctr select                                         */
+#define SH_Y_MOD_DBUG_SEL_DQL_SEL_SHFT           46
+#define SH_Y_MOD_DBUG_SEL_DQL_SEL_MASK           0x000fc00000000000
+
+/*   SH_Y_MOD_DBUG_SEL_DQR_SEL                                          */
+/*   Description:  dqctl select                                         */
+#define SH_Y_MOD_DBUG_SEL_DQR_SEL_SHFT           52
+#define SH_Y_MOD_DBUG_SEL_DQR_SEL_MASK           0x03f0000000000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DBUG_SEL"                       */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#define SH_Y_DBUG_SEL                            0x0000000100020150
+#define SH_Y_DBUG_SEL_MASK                       0x0000000000ffffff
+#define SH_Y_DBUG_SEL_INIT                       0x0000000000000000
+
+/*   SH_Y_DBUG_SEL_DBG_SEL                                              */
+/*   Description:  debug select                                         */
+#define SH_Y_DBUG_SEL_DBG_SEL_SHFT               0
+#define SH_Y_DBUG_SEL_DBG_SEL_MASK               0x0000000000ffffff
+
+/* ==================================================================== */
+/*                      Register "SH_Y_LADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#define SH_Y_LADDR_CMP                           0x0000000100020158
+#define SH_Y_LADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_Y_LADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_Y_LADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_Y_LADDR_CMP_CMP_VAL_SHFT              0
+#define SH_Y_LADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_Y_LADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_Y_LADDR_CMP_MASK_VAL_SHFT             32
+#define SH_Y_LADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                      Register "SH_Y_RADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#define SH_Y_RADDR_CMP                           0x0000000100020160
+#define SH_Y_RADDR_CMP_MASK                      0x0fffffff0fffffff
+#define SH_Y_RADDR_CMP_INIT                      0x0000000000000000
+
+/*   SH_Y_RADDR_CMP_CMP_VAL                                             */
+/*   Description:  Compare value                                        */
+#define SH_Y_RADDR_CMP_CMP_VAL_SHFT              0
+#define SH_Y_RADDR_CMP_CMP_VAL_MASK              0x000000000fffffff
+
+/*   SH_Y_RADDR_CMP_MASK_VAL                                            */
+/*   Description:  Mask value                                           */
+#define SH_Y_RADDR_CMP_MASK_VAL_SHFT             32
+#define SH_Y_RADDR_CMP_MASK_VAL_MASK             0x0fffffff00000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_CMP"                        */
+/*                        MD acy tagmgr compare                         */
+/* ==================================================================== */
+
+#define SH_Y_TAG_CMP                             0x0000000100020168
+#define SH_Y_TAG_CMP_MASK                        0x007fffffffffffff
+#define SH_Y_TAG_CMP_INIT                        0x0000000000000000
+
+/*   SH_Y_TAG_CMP_CMD                                                   */
+/*   Description:  Command compare value                                */
+#define SH_Y_TAG_CMP_CMD_SHFT                    0
+#define SH_Y_TAG_CMP_CMD_MASK                    0x00000000000000ff
+
+/*   SH_Y_TAG_CMP_ADDR                                                  */
+/*   Description:  Address compare value                                */
+#define SH_Y_TAG_CMP_ADDR_SHFT                   8
+#define SH_Y_TAG_CMP_ADDR_MASK                   0x000001ffffffff00
+
+/*   SH_Y_TAG_CMP_SRC                                                   */
+/*   Description:  Source compare value                                 */
+#define SH_Y_TAG_CMP_SRC_SHFT                    41
+#define SH_Y_TAG_CMP_SRC_MASK                    0x007ffe0000000000
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_MASK"                       */
+/*                          MD acy tagmgr mask                          */
+/* ==================================================================== */
+
+#define SH_Y_TAG_MASK                            0x0000000100020170
+#define SH_Y_TAG_MASK_MASK                       0x007fffffffffffff
+#define SH_Y_TAG_MASK_INIT                       0x0000000000000000
+
+/*   SH_Y_TAG_MASK_CMD                                                  */
+/*   Description:  Command compare value                                */
+#define SH_Y_TAG_MASK_CMD_SHFT                   0
+#define SH_Y_TAG_MASK_CMD_MASK                   0x00000000000000ff
+
+/*   SH_Y_TAG_MASK_ADDR                                                 */
+/*   Description:  Address compare value                                */
+#define SH_Y_TAG_MASK_ADDR_SHFT                  8
+#define SH_Y_TAG_MASK_ADDR_MASK                  0x000001ffffffff00
+
+/*   SH_Y_TAG_MASK_SRC                                                  */
+/*   Description:  Source compare value                                 */
+#define SH_Y_TAG_MASK_SRC_SHFT                   41
+#define SH_Y_TAG_MASK_SRC_MASK                   0x007ffe0000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_JNR_DBUG_DATA_CFG"                  */
+/*              configuration for md jnr debug data muxes               */
+/* ==================================================================== */
+
+#define SH_MD_JNR_DBUG_DATA_CFG                  0x0000000100020178
+#define SH_MD_JNR_DBUG_DATA_CFG_MASK             0x0000000077777777
+#define SH_MD_JNR_DBUG_DATA_CFG_INIT             0x0000000000000000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL                                */
+/*   Description:  selects which nibble drives nibble0                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_SHFT 0
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE0_SEL_MASK 0x0000000000000007
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL                                */
+/*   Description:  selects which nibble drives nibble1                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_SHFT 4
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE1_SEL_MASK 0x0000000000000070
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL                                */
+/*   Description:  selects which nibble drives nibble2                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_SHFT 8
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE2_SEL_MASK 0x0000000000000700
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL                                */
+/*   Description:  selects which nibble drives nibble3                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_SHFT 12
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE3_SEL_MASK 0x0000000000007000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL                                */
+/*   Description:  selects which nibble drives nibble4                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_SHFT 16
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE4_SEL_MASK 0x0000000000070000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL                                */
+/*   Description:  selects which nibble drives nibble5                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_SHFT 20
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE5_SEL_MASK 0x0000000000700000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL                                */
+/*   Description:  selects which nibble drives nibble6                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_SHFT 24
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE6_SEL_MASK 0x0000000007000000
+
+/*   SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL                                */
+/*   Description:  selects which nibble drives nibble7                  */
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_SHFT 28
+#define SH_MD_JNR_DBUG_DATA_CFG_NIBBLE7_SEL_MASK 0x0000000070000000
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LAST_CREDIT"                     */
+/*                 captures last credit values on reset                 */
+/* ==================================================================== */
+
+#define SH_MD_LAST_CREDIT                        0x0000000100020180
+#define SH_MD_LAST_CREDIT_MASK                   0x0000003f3f3f3f3f
+#define SH_MD_LAST_CREDIT_INIT                   0x0000000000000000
+
+/*   SH_MD_LAST_CREDIT_RQ_TO_PI                                         */
+/*   Description:  capture of request credits to pi                     */
+#define SH_MD_LAST_CREDIT_RQ_TO_PI_SHFT          0
+#define SH_MD_LAST_CREDIT_RQ_TO_PI_MASK          0x000000000000003f
+
+/*   SH_MD_LAST_CREDIT_RP_TO_PI                                         */
+/*   Description:  capture of reply credits to pi                       */
+#define SH_MD_LAST_CREDIT_RP_TO_PI_SHFT          8
+#define SH_MD_LAST_CREDIT_RP_TO_PI_MASK          0x0000000000003f00
+
+/*   SH_MD_LAST_CREDIT_RQ_TO_XN                                         */
+/*   Description:  capture of request credits to xn                     */
+#define SH_MD_LAST_CREDIT_RQ_TO_XN_SHFT          16
+#define SH_MD_LAST_CREDIT_RQ_TO_XN_MASK          0x00000000003f0000
+
+/*   SH_MD_LAST_CREDIT_RP_TO_XN                                         */
+/*   Description:  capture of reply credits to xn                       */
+#define SH_MD_LAST_CREDIT_RP_TO_XN_SHFT          24
+#define SH_MD_LAST_CREDIT_RP_TO_XN_MASK          0x000000003f000000
+
+/*   SH_MD_LAST_CREDIT_TO_LB                                            */
+/*   Description:  capture of credits to pi                             */
+#define SH_MD_LAST_CREDIT_TO_LB_SHFT             32
+#define SH_MD_LAST_CREDIT_TO_LB_MASK             0x0000003f00000000
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_ADDR"                    */
+/*                   Address capture address register                   */
+/* ==================================================================== */
+
+#define SH_MEM_CAPTURE_ADDR                      0x0000000100020300
+#define SH_MEM_CAPTURE_ADDR_MASK                 0x00000ffffffffff8
+#define SH_MEM_CAPTURE_ADDR_INIT                 0x0000000000000000
+
+/*   SH_MEM_CAPTURE_ADDR_ADDR                                           */
+/*   Description:  upper bits of address                                */
+#define SH_MEM_CAPTURE_ADDR_ADDR_SHFT            3
+#define SH_MEM_CAPTURE_ADDR_ADDR_MASK            0x0000000ffffffff8
+
+/*   SH_MEM_CAPTURE_ADDR_CMD                                            */
+/*   Description:  command of reference                                 */
+#define SH_MEM_CAPTURE_ADDR_CMD_SHFT             36
+#define SH_MEM_CAPTURE_ADDR_CMD_MASK             0x00000ff000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_MASK"                    */
+/*                    Address capture mask register                     */
+/* ==================================================================== */
+
+#define SH_MEM_CAPTURE_MASK                      0x0000000100020308
+#define SH_MEM_CAPTURE_MASK_MASK                 0x00003ffffffffff8
+#define SH_MEM_CAPTURE_MASK_INIT                 0x0000000000000000
+
+/*   SH_MEM_CAPTURE_MASK_ADDR                                           */
+/*   Description:  upper bits of address                                */
+#define SH_MEM_CAPTURE_MASK_ADDR_SHFT            3
+#define SH_MEM_CAPTURE_MASK_ADDR_MASK            0x0000000ffffffff8
+
+/*   SH_MEM_CAPTURE_MASK_CMD                                            */
+/*   Description:  command of reference                                 */
+#define SH_MEM_CAPTURE_MASK_CMD_SHFT             36
+#define SH_MEM_CAPTURE_MASK_CMD_MASK             0x00000ff000000000
+
+/*   SH_MEM_CAPTURE_MASK_ENABLE_LOCAL                                   */
+/*   Description:  capture references originating locally               */
+#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_SHFT    44
+#define SH_MEM_CAPTURE_MASK_ENABLE_LOCAL_MASK    0x0000100000000000
+
+/*   SH_MEM_CAPTURE_MASK_ENABLE_REMOTE                                  */
+/*   Description:  capture references originating remotely              */
+#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_SHFT   45
+#define SH_MEM_CAPTURE_MASK_ENABLE_REMOTE_MASK   0x0000200000000000
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_HDR"                     */
+/*                   Address capture header register                    */
+/* ==================================================================== */
+
+#define SH_MEM_CAPTURE_HDR                       0x0000000100020310
+#define SH_MEM_CAPTURE_HDR_MASK                  0xfffffffffffffff8
+#define SH_MEM_CAPTURE_HDR_INIT                  0x0000000000000000
+
+/*   SH_MEM_CAPTURE_HDR_ADDR                                            */
+/*   Description:  upper bits of reference address                      */
+#define SH_MEM_CAPTURE_HDR_ADDR_SHFT             3
+#define SH_MEM_CAPTURE_HDR_ADDR_MASK             0x0000000ffffffff8
+
+/*   SH_MEM_CAPTURE_HDR_CMD                                             */
+/*   Description:  command of reference                                 */
+#define SH_MEM_CAPTURE_HDR_CMD_SHFT              36
+#define SH_MEM_CAPTURE_HDR_CMD_MASK              0x00000ff000000000
+
+/*   SH_MEM_CAPTURE_HDR_SRC                                             */
+/*   Description:  source node of reference                             */
+#define SH_MEM_CAPTURE_HDR_SRC_SHFT              44
+#define SH_MEM_CAPTURE_HDR_SRC_MASK              0x03fff00000000000
+
+/*   SH_MEM_CAPTURE_HDR_CNTR                                            */
+/*   Description:  increments on every capture                          */
+#define SH_MEM_CAPTURE_HDR_CNTR_SHFT             58
+#define SH_MEM_CAPTURE_HDR_CNTR_MASK             0xfc00000000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_CONFIG                0x0000000100030000
+#define SH_MD_DQLP_MMR_DIR_CONFIG_MASK           0x000000000000001f
+#define SH_MD_DQLP_MMR_DIR_CONFIG_INIT           0x0000000000000010
+
+/*   SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE                                 */
+/*   Description:  system size code                                     */
+#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_SHFT  0
+#define SH_MD_DQLP_MMR_DIR_CONFIG_SYS_SIZE_MASK  0x0000000000000007
+
+/*   SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC                                */
+/*   Description:  enable directory ecc correction                      */
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008
+
+/*   SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS                               */
+/*   Description:  enable local poisoning for dir table fall-through    */
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4
+#define SH_MD_DQLP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0              0x0000000100030100
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC0_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1              0x0000000100030110
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC1_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2              0x0000000100030120
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC2_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3              0x0000000100030130
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_MASK         0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_INIT         0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_PRESVEC3_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0               0x0000000100030200
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC0_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1               0x0000000100030210
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC1_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2               0x0000000100030220
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC2_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3               0x0000000100030230
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC3_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4               0x0000000100030240
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC4_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5               0x0000000100030250
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC5_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6               0x0000000100030260
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC6_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7               0x0000000100030270
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_MASK          0xffffffffffffffff
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_LOCVEC7_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0               0x0000000100030300
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC0_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC0_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1               0x0000000100030310
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC1_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC1_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2               0x0000000100030320
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC2_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC2_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3               0x0000000100030330
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC3_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC3_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4               0x0000000100030340
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC4_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC4_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5               0x0000000100030350
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC5_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC5_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6               0x0000000100030360
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC6_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC6_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7               0x0000000100030370
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_MASK          0x000000000fffffff
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC7_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_SHFT       0
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_PRIVEC7_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_TIMER                 0x0000000100030400
+#define SH_MD_DQLP_MMR_DIR_TIMER_MASK            0x00000000003fffff
+#define SH_MD_DQLP_MMR_DIR_TIMER_INIT            0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV                                 */
+/*   Description:  timer divide register                                */
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_SHFT  0
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_DIV_MASK  0x0000000000000fff
+
+/*   SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN                                  */
+/*   Description:  timer enable                                         */
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_SHFT   12
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_EN_MASK   0x0000000000001000
+
+/*   SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR                                 */
+/*   Description:  value of current timer                               */
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_SHFT  13
+#define SH_MD_DQLP_MMR_DIR_TIMER_TIMER_CUR_MASK  0x00000000003fe000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY           0x0000000100031000
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_MASK      0x03ffffffffffffff
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_INIT      0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA                                */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB                                */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI                                 */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT  52
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_PRI_MASK  0x0070000000000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC                                 */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT  55
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY_ACC_MASK  0x0380000000000000
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC             0x0000000100031010
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_MASK        0x0000000000003fff
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_INIT        0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA                                  */
+/*   Description:  XOR bits for directory ECC group 1                   */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_SHFT   0
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCA_MASK   0x000000000000007f
+
+/*   SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB                                  */
+/*   Description:  XOR bits for directory ECC group 2                   */
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_SHFT   7
+#define SH_MD_DQLP_MMR_PIOWD_DIR_ECC_ECCB_MASK   0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY         0x0000000100032000
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC           0x0000000100032010
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQLP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY         0x0000000100032800
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC           0x0000000100032810
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQLP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XCERR1                    0x0000000100033000
+#define SH_MD_DQLP_MMR_XCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_XCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_XCERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_XCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQLP_MMR_XCERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQLP_MMR_XCERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_XCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_XCERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_XCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XCERR2                    0x0000000100033010
+#define SH_MD_DQLP_MMR_XCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_XCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_XCERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_XCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQLP_MMR_XCERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQLP_MMR_XCERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XUERR1                    0x0000000100033020
+#define SH_MD_DQLP_MMR_XUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_XUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_XUERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_XUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQLP_MMR_XUERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQLP_MMR_XUERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_XUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_XUERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_XUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XUERR2                    0x0000000100033030
+#define SH_MD_DQLP_MMR_XUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_XUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_XUERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_XUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_XUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQLP_MMR_XUERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_XUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_XUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQLP_MMR_XUERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_XUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XPERR                     0x0000000100033040
+#define SH_MD_DQLP_MMR_XPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQLP_MMR_XPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQLP_MMR_XPERR_DIR_SHFT            0
+#define SH_MD_DQLP_MMR_XPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_XPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQLP_MMR_XPERR_CMD_SHFT            26
+#define SH_MD_DQLP_MMR_XPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQLP_MMR_XPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQLP_MMR_XPERR_SRC_SHFT            34
+#define SH_MD_DQLP_MMR_XPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQLP_MMR_XPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQLP_MMR_XPERR_PRIGE_SHFT          48
+#define SH_MD_DQLP_MMR_XPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQLP_MMR_XPERR_PRIV_SHFT           49
+#define SH_MD_DQLP_MMR_XPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_XPERR_COR_SHFT            50
+#define SH_MD_DQLP_MMR_XPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_XPERR_UNC_SHFT            51
+#define SH_MD_DQLP_MMR_XPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_XPERR_MYBIT_SHFT          52
+#define SH_MD_DQLP_MMR_XPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQLP_MMR_XPERR_VAL_SHFT            60
+#define SH_MD_DQLP_MMR_XPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQLP_MMR_XPERR_MORE_SHFT           61
+#define SH_MD_DQLP_MMR_XPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQLP_MMR_XPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQLP_MMR_XPERR_ARM_SHFT            62
+#define SH_MD_DQLP_MMR_XPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YCERR1                    0x0000000100033800
+#define SH_MD_DQLP_MMR_YCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_YCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_YCERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_YCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQLP_MMR_YCERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQLP_MMR_YCERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_YCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_YCERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_YCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YCERR2                    0x0000000100033810
+#define SH_MD_DQLP_MMR_YCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_YCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_YCERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_YCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQLP_MMR_YCERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQLP_MMR_YCERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YUERR1                    0x0000000100033820
+#define SH_MD_DQLP_MMR_YUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQLP_MMR_YUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQLP_MMR_YUERR1_GRP1_SHFT          0
+#define SH_MD_DQLP_MMR_YUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQLP_MMR_YUERR1_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQLP_MMR_YUERR1_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQLP_MMR_YUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQLP_MMR_YUERR1_ARM_SHFT           38
+#define SH_MD_DQLP_MMR_YUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YUERR2                    0x0000000100033830
+#define SH_MD_DQLP_MMR_YUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQLP_MMR_YUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQLP_MMR_YUERR2_GRP2_SHFT          0
+#define SH_MD_DQLP_MMR_YUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQLP_MMR_YUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQLP_MMR_YUERR2_VAL_SHFT           36
+#define SH_MD_DQLP_MMR_YUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQLP_MMR_YUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQLP_MMR_YUERR2_MORE_SHFT          37
+#define SH_MD_DQLP_MMR_YUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YPERR                     0x0000000100033840
+#define SH_MD_DQLP_MMR_YPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQLP_MMR_YPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQLP_MMR_YPERR_DIR_SHFT            0
+#define SH_MD_DQLP_MMR_YPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQLP_MMR_YPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQLP_MMR_YPERR_CMD_SHFT            26
+#define SH_MD_DQLP_MMR_YPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQLP_MMR_YPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQLP_MMR_YPERR_SRC_SHFT            34
+#define SH_MD_DQLP_MMR_YPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQLP_MMR_YPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQLP_MMR_YPERR_PRIGE_SHFT          48
+#define SH_MD_DQLP_MMR_YPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQLP_MMR_YPERR_PRIV_SHFT           49
+#define SH_MD_DQLP_MMR_YPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQLP_MMR_YPERR_COR_SHFT            50
+#define SH_MD_DQLP_MMR_YPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQLP_MMR_YPERR_UNC_SHFT            51
+#define SH_MD_DQLP_MMR_YPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_YPERR_MYBIT_SHFT          52
+#define SH_MD_DQLP_MMR_YPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQLP_MMR_YPERR_VAL_SHFT            60
+#define SH_MD_DQLP_MMR_YPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQLP_MMR_YPERR_MORE_SHFT           61
+#define SH_MD_DQLP_MMR_YPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQLP_MMR_YPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQLP_MMR_YPERR_ARM_SHFT            62
+#define SH_MD_DQLP_MMR_YPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG               0x0000000100034000
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_MASK          0x00000000ffffffff
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0                                    */
+/*   Description:  command trigger 0                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_SHFT     0
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD0_MASK     0x00000000000000ff
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1                                    */
+/*   Description:  command trigger 1                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_SHFT     8
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD1_MASK     0x000000000000ff00
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2                                    */
+/*   Description:  command trigger 2                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_SHFT     16
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD2_MASK     0x0000000000ff0000
+
+/*   SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3                                    */
+/*   Description:  command trigger 3                                    */
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_SHFT     24
+#define SH_MD_DQLP_MMR_DIR_CMDTRIG_CMD3_MASK     0x00000000ff000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG               0x0000000100034010
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MASK          0x000003ffffffffff
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_SHFT      22
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_SHFT    24
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_SHFT    25
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_SHFT    34
+#define SH_MD_DQLP_MMR_DIR_TBLTRIG_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_DIR_TBLMASK               0x0000000100034020
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_MASK          0x000003ffffffffff
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_SHFT      0
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_SHFT      14
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_SHFT      22
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_SHFT    24
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_SHFT    25
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_SHFT    34
+#define SH_MD_DQLP_MMR_DIR_TBLMASK_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_H                   0x0000000100038000
+#define SH_MD_DQLP_MMR_XBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQLP_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_XBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQLP_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLP_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQLP_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_L                   0x0000000100038010
+#define SH_MD_DQLP_MMR_XBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQLP_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_XBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQLP_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_ERR_H               0x0000000100038020
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_XBIST_ERR_L               0x0000000100038030
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_H                   0x0000000100038800
+#define SH_MD_DQLP_MMR_YBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQLP_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_YBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQLP_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLP_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQLP_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_L                   0x0000000100038810
+#define SH_MD_DQLP_MMR_YBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQLP_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQLP_MMR_YBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLP_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQLP_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLP_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQLP_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_ERR_H               0x0000000100038820
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLP_MMR_YBIST_ERR_L               0x0000000100038830
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLP_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLP_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_H                   0x0000000100048000
+#define SH_MD_DQLS_MMR_XBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_XBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQLS_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLS_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQLS_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_L                   0x0000000100048010
+#define SH_MD_DQLS_MMR_XBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_XBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQLS_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_ERR_H               0x0000000100048020
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XBIST_ERR_L               0x0000000100048030
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_H                   0x0000000100048800
+#define SH_MD_DQLS_MMR_YBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_YBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQLS_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQLS_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQLS_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_L                   0x0000000100048810
+#define SH_MD_DQLS_MMR_YBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQLS_MMR_YBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQLS_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQLS_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQLS_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQLS_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_ERR_H               0x0000000100048820
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_YBIST_ERR_L               0x0000000100048830
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQLS_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQLS_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_JNR_DEBUG                 0x0000000100049000
+#define SH_MD_DQLS_MMR_JNR_DEBUG_MASK            0x0000000000000003
+#define SH_MD_DQLS_MMR_JNR_DEBUG_INIT            0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_JNR_DEBUG_PX                                        */
+/*   Description:  select 0=pi 1=xn side                                */
+#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_SHFT         0
+#define SH_MD_DQLS_MMR_JNR_DEBUG_PX_MASK         0x0000000000000001
+
+/*   SH_MD_DQLS_MMR_JNR_DEBUG_RW                                        */
+/*   Description:  select 0=read 1=write side                           */
+#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_SHFT         1
+#define SH_MD_DQLS_MMR_JNR_DEBUG_RW_MASK         0x0000000000000002
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_XAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#define SH_MD_DQLS_MMR_XAMOPW_ERR                0x000000010004a000
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_MASK           0x0000000103ff03ff
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_INIT           0x0000000000000000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN                                     */
+/*   Description:  store data syndrome                                  */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_SHFT      0
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SSYN_MASK      0x00000000000000ff
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR                                     */
+/*   Description:  correctable ecc errror on store data                 */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_SHFT      8
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SCOR_MASK      0x0000000000000100
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC                                     */
+/*   Description:  uncorrectable ecc errror on store data               */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_SHFT      9
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_SUNC_MASK      0x0000000000000200
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN                                     */
+/*   Description:  memory read data syndrome                            */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_SHFT      16
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RSYN_MASK      0x0000000000ff0000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR                                     */
+/*   Description:  correctable ecc errror on read data                  */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_SHFT      24
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RCOR_MASK      0x0000000001000000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC                                     */
+/*   Description:  uncorrectable ecc errror on read data                */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_SHFT      25
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_RUNC_MASK      0x0000000002000000
+
+/*   SH_MD_DQLS_MMR_XAMOPW_ERR_ARM                                      */
+/*   Description:  writing 1 arms ecc error capture                     */
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_SHFT       32
+#define SH_MD_DQLS_MMR_XAMOPW_ERR_ARM_MASK       0x0000000100000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_CONFIG                0x0000000100050000
+#define SH_MD_DQRP_MMR_DIR_CONFIG_MASK           0x000000000000001f
+#define SH_MD_DQRP_MMR_DIR_CONFIG_INIT           0x0000000000000010
+
+/*   SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE                                 */
+/*   Description:  system size code                                     */
+#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_SHFT  0
+#define SH_MD_DQRP_MMR_DIR_CONFIG_SYS_SIZE_MASK  0x0000000000000007
+
+/*   SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC                                */
+/*   Description:  enable directory ecc correction                      */
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_SHFT 3
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRECC_MASK 0x0000000000000008
+
+/*   SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS                               */
+/*   Description:  enable local poisoning for dir table fall-through    */
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_SHFT 4
+#define SH_MD_DQRP_MMR_DIR_CONFIG_EN_DIRPOIS_MASK 0x0000000000000010
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0              0x0000000100050100
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC0_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1              0x0000000100050110
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC1_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2              0x0000000100050120
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC2_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3              0x0000000100050130
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_MASK         0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_INIT         0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC                                    */
+/*   Description:  node presence bits, 1=present                        */
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_PRESVEC3_VEC_MASK     0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0               0x0000000100050200
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC0_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1               0x0000000100050210
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC1_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2               0x0000000100050220
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC2_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3               0x0000000100050230
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC3_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4               0x0000000100050240
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC4_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5               0x0000000100050250
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC5_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6               0x0000000100050260
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC6_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7               0x0000000100050270
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_MASK          0xffffffffffffffff
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC                                     */
+/*   Description:  1 node is local                                      */
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_LOCVEC7_VEC_MASK      0xffffffffffffffff
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0               0x0000000100050300
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC0_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC0_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1               0x0000000100050310
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC1_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC1_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2               0x0000000100050320
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC2_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC2_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3               0x0000000100050330
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC3_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC3_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4               0x0000000100050340
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC4_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC4_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5               0x0000000100050350
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC5_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC5_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6               0x0000000100050360
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC6_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC6_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7               0x0000000100050370
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_MASK          0x000000000fffffff
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC7_IN                                      */
+/*   Description:  in partition privileges, locvec bit=1                */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_SHFT       0
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_IN_MASK       0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT                                     */
+/*   Description:  out of partition privileges, locvec bit=0            */
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_PRIVEC7_OUT_MASK      0x000000000fffc000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_TIMER                 0x0000000100050400
+#define SH_MD_DQRP_MMR_DIR_TIMER_MASK            0x00000000003fffff
+#define SH_MD_DQRP_MMR_DIR_TIMER_INIT            0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV                                 */
+/*   Description:  timer divide register                                */
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_SHFT  0
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_DIV_MASK  0x0000000000000fff
+
+/*   SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN                                  */
+/*   Description:  timer enable                                         */
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_SHFT   12
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_EN_MASK   0x0000000000001000
+
+/*   SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR                                 */
+/*   Description:  value of current timer                               */
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_SHFT  13
+#define SH_MD_DQRP_MMR_DIR_TIMER_TIMER_CUR_MASK  0x00000000003fe000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY           0x0000000100051000
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_MASK      0x03ffffffffffffff
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_INIT      0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA                                */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB                                */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI                                 */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_SHFT  52
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_PRI_MASK  0x0070000000000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC                                 */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_SHFT  55
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY_ACC_MASK  0x0380000000000000
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC             0x0000000100051010
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_MASK        0x0000000000003fff
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_INIT        0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA                                  */
+/*   Description:  XOR bits for directory ECC group 1                   */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_SHFT   0
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCA_MASK   0x000000000000007f
+
+/*   SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB                                  */
+/*   Description:  XOR bits for directory ECC group 2                   */
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_SHFT   7
+#define SH_MD_DQRP_MMR_PIOWD_DIR_ECC_ECCB_MASK   0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY         0x0000000100052000
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC           0x0000000100052010
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQRP_MMR_XPIORD_XDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY         0x0000000100052800
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_MASK    0x0fffffffffffffff
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_INIT    0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA                              */
+/*   Description:  directory entry A                                    */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_SHFT 0
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRA_MASK 0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB                              */
+/*   Description:  directory entry B                                    */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_SHFT 26
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_DIRB_MASK 0x000ffffffc000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI                               */
+/*   Description:  directory priority                                   */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_SHFT 52
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_PRI_MASK 0x0070000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC                               */
+/*   Description:  directory access bits                                */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_SHFT 55
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_ACC_MASK 0x0380000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR                               */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_SHFT 58
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_COR_MASK 0x0400000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC                               */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_SHFT 59
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY_UNC_MASK 0x0800000000000000
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC           0x0000000100052810
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_MASK      0x0000000000003fff
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_INIT      0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA                                */
+/*   Description:  group 1 ecc                                          */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_SHFT 0
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCA_MASK 0x000000000000007f
+
+/*   SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB                                */
+/*   Description:  group 2 ecc                                          */
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_SHFT 7
+#define SH_MD_DQRP_MMR_YPIORD_YDIR_ECC_ECCB_MASK 0x0000000000003f80
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XCERR1                    0x0000000100053000
+#define SH_MD_DQRP_MMR_XCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_XCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_XCERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_XCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQRP_MMR_XCERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQRP_MMR_XCERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_XCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_XCERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_XCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XCERR2                    0x0000000100053010
+#define SH_MD_DQRP_MMR_XCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_XCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_XCERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_XCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQRP_MMR_XCERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQRP_MMR_XCERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XUERR1                    0x0000000100053020
+#define SH_MD_DQRP_MMR_XUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_XUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_XUERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_XUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQRP_MMR_XUERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQRP_MMR_XUERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_XUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_XUERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_XUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XUERR2                    0x0000000100053030
+#define SH_MD_DQRP_MMR_XUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_XUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_XUERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_XUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_XUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQRP_MMR_XUERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_XUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_XUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQRP_MMR_XUERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_XUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XPERR                     0x0000000100053040
+#define SH_MD_DQRP_MMR_XPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQRP_MMR_XPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQRP_MMR_XPERR_DIR_SHFT            0
+#define SH_MD_DQRP_MMR_XPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_XPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQRP_MMR_XPERR_CMD_SHFT            26
+#define SH_MD_DQRP_MMR_XPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQRP_MMR_XPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQRP_MMR_XPERR_SRC_SHFT            34
+#define SH_MD_DQRP_MMR_XPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQRP_MMR_XPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQRP_MMR_XPERR_PRIGE_SHFT          48
+#define SH_MD_DQRP_MMR_XPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQRP_MMR_XPERR_PRIV_SHFT           49
+#define SH_MD_DQRP_MMR_XPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_XPERR_COR_SHFT            50
+#define SH_MD_DQRP_MMR_XPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_XPERR_UNC_SHFT            51
+#define SH_MD_DQRP_MMR_XPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_XPERR_MYBIT_SHFT          52
+#define SH_MD_DQRP_MMR_XPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQRP_MMR_XPERR_VAL_SHFT            60
+#define SH_MD_DQRP_MMR_XPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQRP_MMR_XPERR_MORE_SHFT           61
+#define SH_MD_DQRP_MMR_XPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQRP_MMR_XPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQRP_MMR_XPERR_ARM_SHFT            62
+#define SH_MD_DQRP_MMR_XPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YCERR1                    0x0000000100053800
+#define SH_MD_DQRP_MMR_YCERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_YCERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YCERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_YCERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_YCERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YCERR1_VAL                                          */
+/*   Description:  correctable ecc error in group 1 bits                */
+#define SH_MD_DQRP_MMR_YCERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YCERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YCERR1_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 1       */
+#define SH_MD_DQRP_MMR_YCERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YCERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_YCERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_YCERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_YCERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YCERR2                    0x0000000100053810
+#define SH_MD_DQRP_MMR_YCERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_YCERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YCERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_YCERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_YCERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YCERR2_VAL                                          */
+/*   Description:  correctable ecc error in group 2 bits                */
+#define SH_MD_DQRP_MMR_YCERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YCERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YCERR2_MORE                                         */
+/*   Description:  more than one correctable ecc error in group 2       */
+#define SH_MD_DQRP_MMR_YCERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YCERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YUERR1                    0x0000000100053820
+#define SH_MD_DQRP_MMR_YUERR1_MASK               0x0000007fffffffff
+#define SH_MD_DQRP_MMR_YUERR1_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YUERR1_GRP1                                         */
+/*   Description:  ecc group 1 bits                                     */
+#define SH_MD_DQRP_MMR_YUERR1_GRP1_SHFT          0
+#define SH_MD_DQRP_MMR_YUERR1_GRP1_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YUERR1_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 1 bits              */
+#define SH_MD_DQRP_MMR_YUERR1_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YUERR1_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YUERR1_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 1     */
+#define SH_MD_DQRP_MMR_YUERR1_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YUERR1_MORE_MASK          0x0000002000000000
+
+/*   SH_MD_DQRP_MMR_YUERR1_ARM                                          */
+/*   Description:  writing 1 arms uncorrectable ecc error capture       */
+#define SH_MD_DQRP_MMR_YUERR1_ARM_SHFT           38
+#define SH_MD_DQRP_MMR_YUERR1_ARM_MASK           0x0000004000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YUERR2                    0x0000000100053830
+#define SH_MD_DQRP_MMR_YUERR2_MASK               0x0000003fffffffff
+#define SH_MD_DQRP_MMR_YUERR2_INIT               0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YUERR2_GRP2                                         */
+/*   Description:  ecc group 2 bits                                     */
+#define SH_MD_DQRP_MMR_YUERR2_GRP2_SHFT          0
+#define SH_MD_DQRP_MMR_YUERR2_GRP2_MASK          0x0000000fffffffff
+
+/*   SH_MD_DQRP_MMR_YUERR2_VAL                                          */
+/*   Description:  uncorrectable ecc error in group 2 bits              */
+#define SH_MD_DQRP_MMR_YUERR2_VAL_SHFT           36
+#define SH_MD_DQRP_MMR_YUERR2_VAL_MASK           0x0000001000000000
+
+/*   SH_MD_DQRP_MMR_YUERR2_MORE                                         */
+/*   Description:  more than one uncorrectable ecc error in group 2     */
+#define SH_MD_DQRP_MMR_YUERR2_MORE_SHFT          37
+#define SH_MD_DQRP_MMR_YUERR2_MORE_MASK          0x0000002000000000
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YPERR                     0x0000000100053840
+#define SH_MD_DQRP_MMR_YPERR_MASK                0x7fffffffffffffff
+#define SH_MD_DQRP_MMR_YPERR_INIT                0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_DIR                                           */
+/*   Description:  directory entry                                      */
+#define SH_MD_DQRP_MMR_YPERR_DIR_SHFT            0
+#define SH_MD_DQRP_MMR_YPERR_DIR_MASK            0x0000000003ffffff
+
+/*   SH_MD_DQRP_MMR_YPERR_CMD                                           */
+/*   Description:  incoming command                                     */
+#define SH_MD_DQRP_MMR_YPERR_CMD_SHFT            26
+#define SH_MD_DQRP_MMR_YPERR_CMD_MASK            0x00000003fc000000
+
+/*   SH_MD_DQRP_MMR_YPERR_SRC                                           */
+/*   Description:  source node of dir operation                         */
+#define SH_MD_DQRP_MMR_YPERR_SRC_SHFT            34
+#define SH_MD_DQRP_MMR_YPERR_SRC_MASK            0x0000fffc00000000
+
+/*   SH_MD_DQRP_MMR_YPERR_PRIGE                                         */
+/*   Description:  priority was greater-equal                           */
+#define SH_MD_DQRP_MMR_YPERR_PRIGE_SHFT          48
+#define SH_MD_DQRP_MMR_YPERR_PRIGE_MASK          0x0001000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_PRIV                                          */
+/*   Description:  access privilege bit                                 */
+#define SH_MD_DQRP_MMR_YPERR_PRIV_SHFT           49
+#define SH_MD_DQRP_MMR_YPERR_PRIV_MASK           0x0002000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_COR                                           */
+/*   Description:  correctable ecc error                                */
+#define SH_MD_DQRP_MMR_YPERR_COR_SHFT            50
+#define SH_MD_DQRP_MMR_YPERR_COR_MASK            0x0004000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_UNC                                           */
+/*   Description:  uncorrectable ecc error                              */
+#define SH_MD_DQRP_MMR_YPERR_UNC_SHFT            51
+#define SH_MD_DQRP_MMR_YPERR_UNC_MASK            0x0008000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_MYBIT                                         */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_YPERR_MYBIT_SHFT          52
+#define SH_MD_DQRP_MMR_YPERR_MYBIT_MASK          0x0ff0000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_VAL                                           */
+/*   Description:  protocol error info valid                            */
+#define SH_MD_DQRP_MMR_YPERR_VAL_SHFT            60
+#define SH_MD_DQRP_MMR_YPERR_VAL_MASK            0x1000000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_MORE                                          */
+/*   Description:  more than one protocol error                         */
+#define SH_MD_DQRP_MMR_YPERR_MORE_SHFT           61
+#define SH_MD_DQRP_MMR_YPERR_MORE_MASK           0x2000000000000000
+
+/*   SH_MD_DQRP_MMR_YPERR_ARM                                           */
+/*   Description:  writing 1 arms error capture                         */
+#define SH_MD_DQRP_MMR_YPERR_ARM_SHFT            62
+#define SH_MD_DQRP_MMR_YPERR_ARM_MASK            0x4000000000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG               0x0000000100054000
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_MASK          0x00000000ffffffff
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0                                    */
+/*   Description:  command trigger 0                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_SHFT     0
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD0_MASK     0x00000000000000ff
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1                                    */
+/*   Description:  command trigger 1                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_SHFT     8
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD1_MASK     0x000000000000ff00
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2                                    */
+/*   Description:  command trigger 2                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_SHFT     16
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD2_MASK     0x0000000000ff0000
+
+/*   SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3                                    */
+/*   Description:  command trigger 3                                    */
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_SHFT     24
+#define SH_MD_DQRP_MMR_DIR_CMDTRIG_CMD3_MASK     0x00000000ff000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG               0x0000000100054010
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MASK          0x000003ffffffffff
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_SHFT      22
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_SHFT    24
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_SHFT    25
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_SHFT    34
+#define SH_MD_DQRP_MMR_DIR_TBLTRIG_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_DIR_TBLMASK               0x0000000100054020
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_MASK          0x000003ffffffffff
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_SRC                                     */
+/*   Description:  source of request                                    */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_SHFT      0
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_SRC_MASK      0x0000000000003fff
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_CMD                                     */
+/*   Description:  incoming request                                     */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_SHFT      14
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_CMD_MASK      0x00000000003fc000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_ACC                                     */
+/*   Description:  uncorrectable error, privilege bit                   */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_SHFT      22
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_ACC_MASK      0x0000000000c00000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE                                   */
+/*   Description:  priority greater-equal                               */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_SHFT    24
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_PRIGE_MASK    0x0000000001000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST                                   */
+/*   Description:  shrd,sxro,sub-state                                  */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_SHFT    25
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_DIRST_MASK    0x00000003fe000000
+
+/*   SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT                                   */
+/*   Description:  ptreq,timeq,timlast,timspec,onlyme,anytim,ptrii,src  */
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_SHFT    34
+#define SH_MD_DQRP_MMR_DIR_TBLMASK_MYBIT_MASK    0x000003fc00000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_H                   0x0000000100058000
+#define SH_MD_DQRP_MMR_XBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQRP_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_XBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQRP_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRP_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQRP_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_L                   0x0000000100058010
+#define SH_MD_DQRP_MMR_XBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQRP_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_XBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQRP_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_ERR_H               0x0000000100058020
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_XBIST_ERR_L               0x0000000100058030
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_H                   0x0000000100058800
+#define SH_MD_DQRP_MMR_YBIST_H_MASK              0x00000700ffffffff
+#define SH_MD_DQRP_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_YBIST_H_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQRP_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRP_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQRP_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_L                   0x0000000100058810
+#define SH_MD_DQRP_MMR_YBIST_L_MASK              0x00000300ffffffff
+#define SH_MD_DQRP_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQRP_MMR_YBIST_L_PAT_MASK          0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRP_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQRP_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRP_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQRP_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_ERR_H               0x0000000100058820
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRP_MMR_YBIST_ERR_L               0x0000000100058830
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_MASK          0x00000300ffffffff
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_PAT_MASK      0x00000000ffffffff
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRP_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRP_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_H                   0x0000000100068000
+#define SH_MD_DQRS_MMR_XBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_H_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_XBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_XBIST_H_INV_SHFT          40
+#define SH_MD_DQRS_MMR_XBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_XBIST_H_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_XBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRS_MMR_XBIST_H_ARM_SHFT          42
+#define SH_MD_DQRS_MMR_XBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_L                   0x0000000100068010
+#define SH_MD_DQRS_MMR_XBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_L_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_XBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_XBIST_L_INV_SHFT          40
+#define SH_MD_DQRS_MMR_XBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_XBIST_L_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_XBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_ERR_H               0x0000000100068020
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_XBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_XBIST_ERR_L               0x0000000100068030
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_XBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_XBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_H                   0x0000000100068800
+#define SH_MD_DQRS_MMR_YBIST_H_MASK              0x000007ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_H_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_H_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_H_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_YBIST_H_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_H_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_YBIST_H_INV_SHFT          40
+#define SH_MD_DQRS_MMR_YBIST_H_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_H_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_YBIST_H_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_YBIST_H_ROT_MASK          0x0000020000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_H_ARM                                         */
+/*   Description:  writing 1 arms data miscompare capture               */
+#define SH_MD_DQRS_MMR_YBIST_H_ARM_SHFT          42
+#define SH_MD_DQRS_MMR_YBIST_H_ARM_MASK          0x0000040000000000
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_L                   0x0000000100068810
+#define SH_MD_DQRS_MMR_YBIST_L_MASK              0x000003ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_L_INIT              0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_L_PAT                                         */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_L_PAT_SHFT          0
+#define SH_MD_DQRS_MMR_YBIST_L_PAT_MASK          0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_L_INV                                         */
+/*   Description:  invert data pattern in next cycle                    */
+#define SH_MD_DQRS_MMR_YBIST_L_INV_SHFT          40
+#define SH_MD_DQRS_MMR_YBIST_L_INV_MASK          0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_L_ROT                                         */
+/*   Description:  rotate left data pattern in next cycle               */
+#define SH_MD_DQRS_MMR_YBIST_L_ROT_SHFT          41
+#define SH_MD_DQRS_MMR_YBIST_L_ROT_MASK          0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_ERR_H               0x0000000100068820
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_H_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_H_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_H_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_YBIST_ERR_H_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YBIST_ERR_L               0x0000000100068830
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_MASK          0x000003ffffffffff
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_INIT          0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_L_PAT                                     */
+/*   Description:  data pattern                                         */
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_SHFT      0
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_PAT_MASK      0x000000ffffffffff
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_L_VAL                                     */
+/*   Description:  bist data miscompare                                 */
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_SHFT      40
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_VAL_MASK      0x0000010000000000
+
+/*   SH_MD_DQRS_MMR_YBIST_ERR_L_MORE                                    */
+/*   Description:  more than one bist data miscompare                   */
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_SHFT     41
+#define SH_MD_DQRS_MMR_YBIST_ERR_L_MORE_MASK     0x0000020000000000
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_JNR_DEBUG                 0x0000000100069000
+#define SH_MD_DQRS_MMR_JNR_DEBUG_MASK            0x0000000000000003
+#define SH_MD_DQRS_MMR_JNR_DEBUG_INIT            0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_JNR_DEBUG_PX                                        */
+/*   Description:  select 0=pi 1=xn side                                */
+#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_SHFT         0
+#define SH_MD_DQRS_MMR_JNR_DEBUG_PX_MASK         0x0000000000000001
+
+/*   SH_MD_DQRS_MMR_JNR_DEBUG_RW                                        */
+/*   Description:  select 0=read 1=write side                           */
+#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_SHFT         1
+#define SH_MD_DQRS_MMR_JNR_DEBUG_RW_MASK         0x0000000000000002
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_YAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#define SH_MD_DQRS_MMR_YAMOPW_ERR                0x000000010006a000
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_MASK           0x0000000103ff03ff
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_INIT           0x0000000000000000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN                                     */
+/*   Description:  store data syndrome                                  */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_SHFT      0
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SSYN_MASK      0x00000000000000ff
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR                                     */
+/*   Description:  correctable ecc errror on store data                 */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_SHFT      8
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SCOR_MASK      0x0000000000000100
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC                                     */
+/*   Description:  uncorrectable ecc errror on store data               */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_SHFT      9
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_SUNC_MASK      0x0000000000000200
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN                                     */
+/*   Description:  memory read data syndrome                            */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_SHFT      16
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RSYN_MASK      0x0000000000ff0000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR                                     */
+/*   Description:  correctable ecc errror on read data                  */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_SHFT      24
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RCOR_MASK      0x0000000001000000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC                                     */
+/*   Description:  uncorrectable ecc errror on read data                */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_SHFT      25
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_RUNC_MASK      0x0000000002000000
+
+/*   SH_MD_DQRS_MMR_YAMOPW_ERR_ARM                                      */
+/*   Description:  writing 1 arms ecc error capture                     */
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_SHFT       32
+#define SH_MD_DQRS_MMR_YAMOPW_ERR_ARM_MASK       0x0000000100000000
+
+
+#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_H */
diff -Nru a/include/asm-ia64/sn/sn2/shub_mmr_t.h b/include/asm-ia64/sn/sn2/shub_mmr_t.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/shub_mmr_t.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,27385 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 2001-2002 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+
+
+#ifndef _ASM_IA64_SN_SN2_SHUB_MMR_T_H
+#define _ASM_IA64_SN_SN2_SHUB_MMR_T_H
+
+#include <asm/sn/arch.h>
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_BINIT_CONTROL"                    */
+/*                          FSB BINIT# Control                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_binit_control_u {
+	mmr_t	sh_fsb_binit_control_regval;
+	struct {
+		mmr_t	binit       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_fsb_binit_control_s;
+} sh_fsb_binit_control_u_t;
+#else
+typedef union sh_fsb_binit_control_u {
+	mmr_t	sh_fsb_binit_control_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	binit       : 1;
+	} sh_fsb_binit_control_s;
+} sh_fsb_binit_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_FSB_RESET_CONTROL"                    */
+/*                          FSB Reset Control                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_reset_control_u {
+	mmr_t	sh_fsb_reset_control_regval;
+	struct {
+		mmr_t	reset       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_fsb_reset_control_s;
+} sh_fsb_reset_control_u_t;
+#else
+typedef union sh_fsb_reset_control_u {
+	mmr_t	sh_fsb_reset_control_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	reset       : 1;
+	} sh_fsb_reset_control_s;
+} sh_fsb_reset_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_FSB_SYSTEM_AGENT_CONFIG"                 */
+/*                    FSB System Agent Configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_system_agent_config_u {
+	mmr_t	sh_fsb_system_agent_config_regval;
+	struct {
+		mmr_t	rcnt_scnt_en        : 1;
+		mmr_t	reserved_0          : 2;
+		mmr_t	berr_assert_en      : 1;
+		mmr_t	berr_sampling_en    : 1;
+		mmr_t	binit_assert_en     : 1;
+		mmr_t	bnr_throttling_en   : 1;
+		mmr_t	short_hang_en       : 1;
+		mmr_t	inta_rsp_data       : 8;
+		mmr_t	io_trans_rsp        : 1;
+		mmr_t	xtpr_trans_rsp      : 1;
+		mmr_t	inta_trans_rsp      : 1;
+		mmr_t	reserved_1          : 4;
+		mmr_t	tdot                : 1;
+		mmr_t	serialize_fsb_en    : 1;
+		mmr_t	reserved_2          : 7;
+		mmr_t	binit_event_enables : 14;
+		mmr_t	reserved_3          : 18;
+	} sh_fsb_system_agent_config_s;
+} sh_fsb_system_agent_config_u_t;
+#else
+typedef union sh_fsb_system_agent_config_u {
+	mmr_t	sh_fsb_system_agent_config_regval;
+	struct {
+		mmr_t	reserved_3          : 18;
+		mmr_t	binit_event_enables : 14;
+		mmr_t	reserved_2          : 7;
+		mmr_t	serialize_fsb_en    : 1;
+		mmr_t	tdot                : 1;
+		mmr_t	reserved_1          : 4;
+		mmr_t	inta_trans_rsp      : 1;
+		mmr_t	xtpr_trans_rsp      : 1;
+		mmr_t	io_trans_rsp        : 1;
+		mmr_t	inta_rsp_data       : 8;
+		mmr_t	short_hang_en       : 1;
+		mmr_t	bnr_throttling_en   : 1;
+		mmr_t	binit_assert_en     : 1;
+		mmr_t	berr_sampling_en    : 1;
+		mmr_t	berr_assert_en      : 1;
+		mmr_t	reserved_0          : 2;
+		mmr_t	rcnt_scnt_en        : 1;
+	} sh_fsb_system_agent_config_s;
+} sh_fsb_system_agent_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_FSB_VGA_REMAP"                      */
+/*                     FSB VGA Address Space Remap                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_vga_remap_u {
+	mmr_t	sh_fsb_vga_remap_regval;
+	struct {
+		mmr_t	reserved_0            : 17;
+		mmr_t	offset                : 19;
+		mmr_t	asid                  : 2;
+		mmr_t	nid                   : 11;
+		mmr_t	reserved_1            : 13;
+		mmr_t	vga_remapping_enabled : 1;
+		mmr_t	reserved_2            : 1;
+	} sh_fsb_vga_remap_s;
+} sh_fsb_vga_remap_u_t;
+#else
+typedef union sh_fsb_vga_remap_u {
+	mmr_t	sh_fsb_vga_remap_regval;
+	struct {
+		mmr_t	reserved_2            : 1;
+		mmr_t	vga_remapping_enabled : 1;
+		mmr_t	reserved_1            : 13;
+		mmr_t	nid                   : 11;
+		mmr_t	asid                  : 2;
+		mmr_t	offset                : 19;
+		mmr_t	reserved_0            : 17;
+	} sh_fsb_vga_remap_s;
+} sh_fsb_vga_remap_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_FSB_RESET_STATUS"                    */
+/*                           FSB Reset Status                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_reset_status_u {
+	mmr_t	sh_fsb_reset_status_regval;
+	struct {
+		mmr_t	reset_in_progress : 1;
+		mmr_t	reserved_0        : 63;
+	} sh_fsb_reset_status_s;
+} sh_fsb_reset_status_u_t;
+#else
+typedef union sh_fsb_reset_status_u {
+	mmr_t	sh_fsb_reset_status_regval;
+	struct {
+		mmr_t	reserved_0        : 63;
+		mmr_t	reset_in_progress : 1;
+	} sh_fsb_reset_status_s;
+} sh_fsb_reset_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_FSB_SYMMETRIC_AGENT_STATUS"               */
+/*                      FSB Symmetric Agent Status                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_fsb_symmetric_agent_status_u {
+	mmr_t	sh_fsb_symmetric_agent_status_regval;
+	struct {
+		mmr_t	cpu_0_active : 1;
+		mmr_t	cpu_1_active : 1;
+		mmr_t	cpus_ready   : 1;
+		mmr_t	reserved_0   : 61;
+	} sh_fsb_symmetric_agent_status_s;
+} sh_fsb_symmetric_agent_status_u_t;
+#else
+typedef union sh_fsb_symmetric_agent_status_u {
+	mmr_t	sh_fsb_symmetric_agent_status_regval;
+	struct {
+		mmr_t	reserved_0   : 61;
+		mmr_t	cpus_ready   : 1;
+		mmr_t	cpu_1_active : 1;
+		mmr_t	cpu_0_active : 1;
+	} sh_fsb_symmetric_agent_status_s;
+} sh_fsb_symmetric_agent_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_0"                   */
+/*                Graphics-write Credit Count for CPU 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_credit_count_0_u {
+	mmr_t	sh_gfx_credit_count_0_regval;
+	struct {
+		mmr_t	count           : 20;
+		mmr_t	reserved_0      : 43;
+		mmr_t	reset_gfx_state : 1;
+	} sh_gfx_credit_count_0_s;
+} sh_gfx_credit_count_0_u_t;
+#else
+typedef union sh_gfx_credit_count_0_u {
+	mmr_t	sh_gfx_credit_count_0_regval;
+	struct {
+		mmr_t	reset_gfx_state : 1;
+		mmr_t	reserved_0      : 43;
+		mmr_t	count           : 20;
+	} sh_gfx_credit_count_0_s;
+} sh_gfx_credit_count_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_CREDIT_COUNT_1"                   */
+/*                Graphics-write Credit Count for CPU 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_credit_count_1_u {
+	mmr_t	sh_gfx_credit_count_1_regval;
+	struct {
+		mmr_t	count           : 20;
+		mmr_t	reserved_0      : 43;
+		mmr_t	reset_gfx_state : 1;
+	} sh_gfx_credit_count_1_s;
+} sh_gfx_credit_count_1_u_t;
+#else
+typedef union sh_gfx_credit_count_1_u {
+	mmr_t	sh_gfx_credit_count_1_regval;
+	struct {
+		mmr_t	reset_gfx_state : 1;
+		mmr_t	reserved_0      : 43;
+		mmr_t	count           : 20;
+	} sh_gfx_credit_count_1_s;
+} sh_gfx_credit_count_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_0"                    */
+/*         Graphics credit mode amd message ordering for CPU 0          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_mode_cntrl_0_u {
+	mmr_t	sh_gfx_mode_cntrl_0_regval;
+	struct {
+		mmr_t	dword_credits      : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	reserved_0         : 61;
+	} sh_gfx_mode_cntrl_0_s;
+} sh_gfx_mode_cntrl_0_u_t;
+#else
+typedef union sh_gfx_mode_cntrl_0_u {
+	mmr_t	sh_gfx_mode_cntrl_0_regval;
+	struct {
+		mmr_t	reserved_0         : 61;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	dword_credits      : 1;
+	} sh_gfx_mode_cntrl_0_s;
+} sh_gfx_mode_cntrl_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_GFX_MODE_CNTRL_1"                    */
+/*         Graphics credit mode amd message ordering for CPU 1          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_mode_cntrl_1_u {
+	mmr_t	sh_gfx_mode_cntrl_1_regval;
+	struct {
+		mmr_t	dword_credits      : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	reserved_0         : 61;
+	} sh_gfx_mode_cntrl_1_s;
+} sh_gfx_mode_cntrl_1_u_t;
+#else
+typedef union sh_gfx_mode_cntrl_1_u {
+	mmr_t	sh_gfx_mode_cntrl_1_regval;
+	struct {
+		mmr_t	reserved_0         : 61;
+		mmr_t	relaxed_ordering   : 1;
+		mmr_t	mixed_mode_credits : 1;
+		mmr_t	dword_credits      : 1;
+	} sh_gfx_mode_cntrl_1_s;
+} sh_gfx_mode_cntrl_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_0"                 */
+/*              Graphics-write Skid Credit Count for CPU 0              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_skid_credit_count_0_u {
+	mmr_t	sh_gfx_skid_credit_count_0_regval;
+	struct {
+		mmr_t	skid        : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_gfx_skid_credit_count_0_s;
+} sh_gfx_skid_credit_count_0_u_t;
+#else
+typedef union sh_gfx_skid_credit_count_0_u {
+	mmr_t	sh_gfx_skid_credit_count_0_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	skid        : 20;
+	} sh_gfx_skid_credit_count_0_s;
+} sh_gfx_skid_credit_count_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_GFX_SKID_CREDIT_COUNT_1"                 */
+/*              Graphics-write Skid Credit Count for CPU 1              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_skid_credit_count_1_u {
+	mmr_t	sh_gfx_skid_credit_count_1_regval;
+	struct {
+		mmr_t	skid        : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_gfx_skid_credit_count_1_s;
+} sh_gfx_skid_credit_count_1_u_t;
+#else
+typedef union sh_gfx_skid_credit_count_1_u {
+	mmr_t	sh_gfx_skid_credit_count_1_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	skid        : 20;
+	} sh_gfx_skid_credit_count_1_s;
+} sh_gfx_skid_credit_count_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_0"                    */
+/*                 Graphics-write Stall Limit for CPU 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_limit_0_u {
+	mmr_t	sh_gfx_stall_limit_0_regval;
+	struct {
+		mmr_t	limit       : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_limit_0_s;
+} sh_gfx_stall_limit_0_u_t;
+#else
+typedef union sh_gfx_stall_limit_0_u {
+	mmr_t	sh_gfx_stall_limit_0_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	limit       : 26;
+	} sh_gfx_stall_limit_0_s;
+} sh_gfx_stall_limit_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_LIMIT_1"                    */
+/*                 Graphics-write Stall Limit for CPU 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_limit_1_u {
+	mmr_t	sh_gfx_stall_limit_1_regval;
+	struct {
+		mmr_t	limit       : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_limit_1_s;
+} sh_gfx_stall_limit_1_u_t;
+#else
+typedef union sh_gfx_stall_limit_1_u {
+	mmr_t	sh_gfx_stall_limit_1_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	limit       : 26;
+	} sh_gfx_stall_limit_1_s;
+} sh_gfx_stall_limit_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_0"                    */
+/*                 Graphics-write Stall Timer for CPU 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_timer_0_u {
+	mmr_t	sh_gfx_stall_timer_0_regval;
+	struct {
+		mmr_t	timer_value : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_timer_0_s;
+} sh_gfx_stall_timer_0_u_t;
+#else
+typedef union sh_gfx_stall_timer_0_u {
+	mmr_t	sh_gfx_stall_timer_0_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	timer_value : 26;
+	} sh_gfx_stall_timer_0_s;
+} sh_gfx_stall_timer_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_STALL_TIMER_1"                    */
+/*                 Graphics-write Stall Timer for CPU 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_stall_timer_1_u {
+	mmr_t	sh_gfx_stall_timer_1_regval;
+	struct {
+		mmr_t	timer_value : 26;
+		mmr_t	reserved_0  : 38;
+	} sh_gfx_stall_timer_1_s;
+} sh_gfx_stall_timer_1_u_t;
+#else
+typedef union sh_gfx_stall_timer_1_u {
+	mmr_t	sh_gfx_stall_timer_1_regval;
+	struct {
+		mmr_t	reserved_0  : 38;
+		mmr_t	timer_value : 26;
+	} sh_gfx_stall_timer_1_s;
+} sh_gfx_stall_timer_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_0"                      */
+/*                   Graphics-write Window for CPU 0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_window_0_u {
+	mmr_t	sh_gfx_window_0_regval;
+	struct {
+		mmr_t	reserved_0    : 24;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_1    : 27;
+		mmr_t	gfx_window_en : 1;
+	} sh_gfx_window_0_s;
+} sh_gfx_window_0_u_t;
+#else
+typedef union sh_gfx_window_0_u {
+	mmr_t	sh_gfx_window_0_regval;
+	struct {
+		mmr_t	gfx_window_en : 1;
+		mmr_t	reserved_1    : 27;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_0    : 24;
+	} sh_gfx_window_0_s;
+} sh_gfx_window_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GFX_WINDOW_1"                      */
+/*                   Graphics-write Window for CPU 1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_window_1_u {
+	mmr_t	sh_gfx_window_1_regval;
+	struct {
+		mmr_t	reserved_0    : 24;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_1    : 27;
+		mmr_t	gfx_window_en : 1;
+	} sh_gfx_window_1_s;
+} sh_gfx_window_1_u_t;
+#else
+typedef union sh_gfx_window_1_u {
+	mmr_t	sh_gfx_window_1_regval;
+	struct {
+		mmr_t	gfx_window_en : 1;
+		mmr_t	reserved_1    : 27;
+		mmr_t	base_addr     : 12;
+		mmr_t	reserved_0    : 24;
+	} sh_gfx_window_1_s;
+} sh_gfx_window_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_0"               */
+/*               Graphics-write Interrupt Limit for CPU 0               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_interrupt_timer_limit_0_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
+	struct {
+		mmr_t	interrupt_timer_limit : 8;
+		mmr_t	reserved_0            : 56;
+	} sh_gfx_interrupt_timer_limit_0_s;
+} sh_gfx_interrupt_timer_limit_0_u_t;
+#else
+typedef union sh_gfx_interrupt_timer_limit_0_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_0_regval;
+	struct {
+		mmr_t	reserved_0            : 56;
+		mmr_t	interrupt_timer_limit : 8;
+	} sh_gfx_interrupt_timer_limit_0_s;
+} sh_gfx_interrupt_timer_limit_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_GFX_INTERRUPT_TIMER_LIMIT_1"               */
+/*               Graphics-write Interrupt Limit for CPU 1               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_interrupt_timer_limit_1_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
+	struct {
+		mmr_t	interrupt_timer_limit : 8;
+		mmr_t	reserved_0            : 56;
+	} sh_gfx_interrupt_timer_limit_1_s;
+} sh_gfx_interrupt_timer_limit_1_u_t;
+#else
+typedef union sh_gfx_interrupt_timer_limit_1_u {
+	mmr_t	sh_gfx_interrupt_timer_limit_1_regval;
+	struct {
+		mmr_t	reserved_0            : 56;
+		mmr_t	interrupt_timer_limit : 8;
+	} sh_gfx_interrupt_timer_limit_1_s;
+} sh_gfx_interrupt_timer_limit_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_0"                   */
+/*                   Graphics Write Status for CPU 0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_write_status_0_u {
+	mmr_t	sh_gfx_write_status_0_regval;
+	struct {
+		mmr_t	busy                : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	re_enable_gfx_stall : 1;
+	} sh_gfx_write_status_0_s;
+} sh_gfx_write_status_0_u_t;
+#else
+typedef union sh_gfx_write_status_0_u {
+	mmr_t	sh_gfx_write_status_0_regval;
+	struct {
+		mmr_t	re_enable_gfx_stall : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	busy                : 1;
+	} sh_gfx_write_status_0_s;
+} sh_gfx_write_status_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_GFX_WRITE_STATUS_1"                   */
+/*                   Graphics Write Status for CPU 1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gfx_write_status_1_u {
+	mmr_t	sh_gfx_write_status_1_regval;
+	struct {
+		mmr_t	busy                : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	re_enable_gfx_stall : 1;
+	} sh_gfx_write_status_1_s;
+} sh_gfx_write_status_1_u_t;
+#else
+typedef union sh_gfx_write_status_1_u {
+	mmr_t	sh_gfx_write_status_1_regval;
+	struct {
+		mmr_t	re_enable_gfx_stall : 1;
+		mmr_t	reserved_0          : 62;
+		mmr_t	busy                : 1;
+	} sh_gfx_write_status_1_s;
+} sh_gfx_write_status_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT0"                         */
+/*                    SHub II Interrupt 0 Registers                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int0_u {
+	mmr_t	sh_ii_int0_regval;
+	struct {
+		mmr_t	idx         : 8;
+		mmr_t	send        : 1;
+		mmr_t	reserved_0  : 55;
+	} sh_ii_int0_s;
+} sh_ii_int0_u_t;
+#else
+typedef union sh_ii_int0_u {
+	mmr_t	sh_ii_int0_regval;
+	struct {
+		mmr_t	reserved_0  : 55;
+		mmr_t	send        : 1;
+		mmr_t	idx         : 8;
+	} sh_ii_int0_s;
+} sh_ii_int0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_CONFIG"                     */
+/*                 SHub II Interrupt 0 Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int0_config_u {
+	mmr_t	sh_ii_int0_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 14;
+	} sh_ii_int0_config_s;
+} sh_ii_int0_config_u_t;
+#else
+typedef union sh_ii_int0_config_u {
+	mmr_t	sh_ii_int0_config_regval;
+	struct {
+		mmr_t	reserved_1  : 14;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_ii_int0_config_s;
+} sh_ii_int0_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT0_ENABLE"                     */
+/*                 SHub II Interrupt 0 Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int0_enable_u {
+	mmr_t	sh_ii_int0_enable_regval;
+	struct {
+		mmr_t	ii_enable   : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ii_int0_enable_s;
+} sh_ii_int0_enable_u_t;
+#else
+typedef union sh_ii_int0_enable_u {
+	mmr_t	sh_ii_int0_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ii_enable   : 1;
+	} sh_ii_int0_enable_s;
+} sh_ii_int0_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_II_INT1"                         */
+/*                    SHub II Interrupt 1 Registers                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int1_u {
+	mmr_t	sh_ii_int1_regval;
+	struct {
+		mmr_t	idx         : 8;
+		mmr_t	send        : 1;
+		mmr_t	reserved_0  : 55;
+	} sh_ii_int1_s;
+} sh_ii_int1_u_t;
+#else
+typedef union sh_ii_int1_u {
+	mmr_t	sh_ii_int1_regval;
+	struct {
+		mmr_t	reserved_0  : 55;
+		mmr_t	send        : 1;
+		mmr_t	idx         : 8;
+	} sh_ii_int1_s;
+} sh_ii_int1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_CONFIG"                     */
+/*                 SHub II Interrupt 1 Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int1_config_u {
+	mmr_t	sh_ii_int1_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 14;
+	} sh_ii_int1_config_s;
+} sh_ii_int1_config_u_t;
+#else
+typedef union sh_ii_int1_config_u {
+	mmr_t	sh_ii_int1_config_regval;
+	struct {
+		mmr_t	reserved_1  : 14;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_ii_int1_config_s;
+} sh_ii_int1_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_INT1_ENABLE"                     */
+/*                 SHub II Interrupt 1 Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_int1_enable_u {
+	mmr_t	sh_ii_int1_enable_regval;
+	struct {
+		mmr_t	ii_enable   : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ii_int1_enable_s;
+} sh_ii_int1_enable_u_t;
+#else
+typedef union sh_ii_int1_enable_u {
+	mmr_t	sh_ii_int1_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ii_enable   : 1;
+	} sh_ii_int1_enable_s;
+} sh_ii_int1_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_INT_NODE_ID_CONFIG"                   */
+/*                 SHub Interrupt Node ID Configuration                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_node_id_config_u {
+	mmr_t	sh_int_node_id_config_regval;
+	struct {
+		mmr_t	node_id     : 11;
+		mmr_t	id_sel      : 1;
+		mmr_t	reserved_0  : 52;
+	} sh_int_node_id_config_s;
+} sh_int_node_id_config_u_t;
+#else
+typedef union sh_int_node_id_config_u {
+	mmr_t	sh_int_node_id_config_regval;
+	struct {
+		mmr_t	reserved_0  : 52;
+		mmr_t	id_sel      : 1;
+		mmr_t	node_id     : 11;
+	} sh_int_node_id_config_s;
+} sh_int_node_id_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_IPI_INT"                         */
+/*               SHub Inter-Processor Interrupt Registers               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ipi_int_u {
+	mmr_t	sh_ipi_int_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 3;
+		mmr_t	send        : 1;
+	} sh_ipi_int_s;
+} sh_ipi_int_u_t;
+#else
+typedef union sh_ipi_int_u {
+	mmr_t	sh_ipi_int_regval;
+	struct {
+		mmr_t	send        : 1;
+		mmr_t	reserved_2  : 3;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_ipi_int_s;
+} sh_ipi_int_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_IPI_INT_ENABLE"                     */
+/*           SHub Inter-Processor Interrupt Enable Registers            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ipi_int_enable_u {
+	mmr_t	sh_ipi_int_enable_regval;
+	struct {
+		mmr_t	pio_enable  : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ipi_int_enable_s;
+} sh_ipi_int_enable_u_t;
+#else
+typedef union sh_ipi_int_enable_u {
+	mmr_t	sh_ipi_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	pio_enable  : 1;
+	} sh_ipi_int_enable_s;
+} sh_ipi_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_CONFIG"                    */
+/*                   SHub Local Interrupt 0 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int0_config_u {
+	mmr_t	sh_local_int0_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int0_config_s;
+} sh_local_int0_config_u_t;
+#else
+typedef union sh_local_int0_config_u {
+	mmr_t	sh_local_int0_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int0_config_s;
+} sh_local_int0_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT0_ENABLE"                    */
+/*                    SHub Local Interrupt 0 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int0_enable_u {
+	mmr_t	sh_local_int0_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int0_enable_s;
+} sh_local_int0_enable_u_t;
+#else
+typedef union sh_local_int0_enable_u {
+	mmr_t	sh_local_int0_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int0_enable_s;
+} sh_local_int0_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_CONFIG"                    */
+/*                   SHub Local Interrupt 1 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int1_config_u {
+	mmr_t	sh_local_int1_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int1_config_s;
+} sh_local_int1_config_u_t;
+#else
+typedef union sh_local_int1_config_u {
+	mmr_t	sh_local_int1_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int1_config_s;
+} sh_local_int1_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT1_ENABLE"                    */
+/*                    SHub Local Interrupt 1 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int1_enable_u {
+	mmr_t	sh_local_int1_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int1_enable_s;
+} sh_local_int1_enable_u_t;
+#else
+typedef union sh_local_int1_enable_u {
+	mmr_t	sh_local_int1_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int1_enable_s;
+} sh_local_int1_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_CONFIG"                    */
+/*                   SHub Local Interrupt 2 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int2_config_u {
+	mmr_t	sh_local_int2_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int2_config_s;
+} sh_local_int2_config_u_t;
+#else
+typedef union sh_local_int2_config_u {
+	mmr_t	sh_local_int2_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int2_config_s;
+} sh_local_int2_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT2_ENABLE"                    */
+/*                    SHub Local Interrupt 2 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int2_enable_u {
+	mmr_t	sh_local_int2_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int2_enable_s;
+} sh_local_int2_enable_u_t;
+#else
+typedef union sh_local_int2_enable_u {
+	mmr_t	sh_local_int2_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int2_enable_s;
+} sh_local_int2_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_CONFIG"                    */
+/*                   SHub Local Interrupt 3 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int3_config_u {
+	mmr_t	sh_local_int3_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int3_config_s;
+} sh_local_int3_config_u_t;
+#else
+typedef union sh_local_int3_config_u {
+	mmr_t	sh_local_int3_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int3_config_s;
+} sh_local_int3_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT3_ENABLE"                    */
+/*                    SHub Local Interrupt 3 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int3_enable_u {
+	mmr_t	sh_local_int3_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int3_enable_s;
+} sh_local_int3_enable_u_t;
+#else
+typedef union sh_local_int3_enable_u {
+	mmr_t	sh_local_int3_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int3_enable_s;
+} sh_local_int3_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_CONFIG"                    */
+/*                   SHub Local Interrupt 4 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int4_config_u {
+	mmr_t	sh_local_int4_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int4_config_s;
+} sh_local_int4_config_u_t;
+#else
+typedef union sh_local_int4_config_u {
+	mmr_t	sh_local_int4_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int4_config_s;
+} sh_local_int4_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT4_ENABLE"                    */
+/*                    SHub Local Interrupt 4 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int4_enable_u {
+	mmr_t	sh_local_int4_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int4_enable_s;
+} sh_local_int4_enable_u_t;
+#else
+typedef union sh_local_int4_enable_u {
+	mmr_t	sh_local_int4_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int4_enable_s;
+} sh_local_int4_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_CONFIG"                    */
+/*                   SHub Local Interrupt 5 Registers                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int5_config_u {
+	mmr_t	sh_local_int5_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_local_int5_config_s;
+} sh_local_int5_config_u_t;
+#else
+typedef union sh_local_int5_config_u {
+	mmr_t	sh_local_int5_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_local_int5_config_s;
+} sh_local_int5_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LOCAL_INT5_ENABLE"                    */
+/*                    SHub Local Interrupt 5 Enable                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_local_int5_enable_u {
+	mmr_t	sh_local_int5_enable_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	reserved_1          : 48;
+	} sh_local_int5_enable_s;
+} sh_local_int5_enable_u_t;
+#else
+typedef union sh_local_int5_enable_u {
+	mmr_t	sh_local_int5_enable_regval;
+	struct {
+		mmr_t	reserved_1          : 48;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	reserved_0          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_local_int5_enable_s;
+} sh_local_int5_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_CONFIG"                  */
+/*              SHub Processor 0 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_err_int_config_u {
+	mmr_t	sh_proc0_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc0_err_int_config_s;
+} sh_proc0_err_int_config_u_t;
+#else
+typedef union sh_proc0_err_int_config_u {
+	mmr_t	sh_proc0_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc0_err_int_config_s;
+} sh_proc0_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_CONFIG"                  */
+/*              SHub Processor 1 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_err_int_config_u {
+	mmr_t	sh_proc1_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc1_err_int_config_s;
+} sh_proc1_err_int_config_u_t;
+#else
+typedef union sh_proc1_err_int_config_u {
+	mmr_t	sh_proc1_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc1_err_int_config_s;
+} sh_proc1_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_CONFIG"                  */
+/*              SHub Processor 2 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_err_int_config_u {
+	mmr_t	sh_proc2_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc2_err_int_config_s;
+} sh_proc2_err_int_config_u_t;
+#else
+typedef union sh_proc2_err_int_config_u {
+	mmr_t	sh_proc2_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc2_err_int_config_s;
+} sh_proc2_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_CONFIG"                  */
+/*              SHub Processor 3 Error Interrupt Registers              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_err_int_config_u {
+	mmr_t	sh_proc3_err_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc3_err_int_config_s;
+} sh_proc3_err_int_config_u_t;
+#else
+typedef union sh_proc3_err_int_config_u {
+	mmr_t	sh_proc3_err_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc3_err_int_config_s;
+} sh_proc3_err_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_CONFIG"                  */
+/*            SHub Processor 0 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_adv_int_config_u {
+	mmr_t	sh_proc0_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc0_adv_int_config_s;
+} sh_proc0_adv_int_config_u_t;
+#else
+typedef union sh_proc0_adv_int_config_u {
+	mmr_t	sh_proc0_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc0_adv_int_config_s;
+} sh_proc0_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_CONFIG"                  */
+/*            SHub Processor 1 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_adv_int_config_u {
+	mmr_t	sh_proc1_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc1_adv_int_config_s;
+} sh_proc1_adv_int_config_u_t;
+#else
+typedef union sh_proc1_adv_int_config_u {
+	mmr_t	sh_proc1_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc1_adv_int_config_s;
+} sh_proc1_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_CONFIG"                  */
+/*            SHub Processor 2 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_adv_int_config_u {
+	mmr_t	sh_proc2_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc2_adv_int_config_s;
+} sh_proc2_adv_int_config_u_t;
+#else
+typedef union sh_proc2_adv_int_config_u {
+	mmr_t	sh_proc2_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc2_adv_int_config_s;
+} sh_proc2_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_CONFIG"                  */
+/*            SHub Processor 3 Advisory Interrupt Registers             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_adv_int_config_u {
+	mmr_t	sh_proc3_adv_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_proc3_adv_int_config_s;
+} sh_proc3_adv_int_config_u_t;
+#else
+typedef union sh_proc3_adv_int_config_u {
+	mmr_t	sh_proc3_adv_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_proc3_adv_int_config_s;
+} sh_proc3_adv_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_INT_ENABLE"                  */
+/*          SHub Processor 0 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_err_int_enable_u {
+	mmr_t	sh_proc0_err_int_enable_regval;
+	struct {
+		mmr_t	proc0_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc0_err_int_enable_s;
+} sh_proc0_err_int_enable_u_t;
+#else
+typedef union sh_proc0_err_int_enable_u {
+	mmr_t	sh_proc0_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc0_err_enable : 1;
+	} sh_proc0_err_int_enable_s;
+} sh_proc0_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_INT_ENABLE"                  */
+/*          SHub Processor 1 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_err_int_enable_u {
+	mmr_t	sh_proc1_err_int_enable_regval;
+	struct {
+		mmr_t	proc1_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc1_err_int_enable_s;
+} sh_proc1_err_int_enable_u_t;
+#else
+typedef union sh_proc1_err_int_enable_u {
+	mmr_t	sh_proc1_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc1_err_enable : 1;
+	} sh_proc1_err_int_enable_s;
+} sh_proc1_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_INT_ENABLE"                  */
+/*          SHub Processor 2 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_err_int_enable_u {
+	mmr_t	sh_proc2_err_int_enable_regval;
+	struct {
+		mmr_t	proc2_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc2_err_int_enable_s;
+} sh_proc2_err_int_enable_u_t;
+#else
+typedef union sh_proc2_err_int_enable_u {
+	mmr_t	sh_proc2_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc2_err_enable : 1;
+	} sh_proc2_err_int_enable_s;
+} sh_proc2_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_INT_ENABLE"                  */
+/*          SHub Processor 3 Error Interrupt Enable Registers           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_err_int_enable_u {
+	mmr_t	sh_proc3_err_int_enable_regval;
+	struct {
+		mmr_t	proc3_err_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc3_err_int_enable_s;
+} sh_proc3_err_int_enable_u_t;
+#else
+typedef union sh_proc3_err_int_enable_u {
+	mmr_t	sh_proc3_err_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc3_err_enable : 1;
+	} sh_proc3_err_int_enable_s;
+} sh_proc3_err_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_INT_ENABLE"                  */
+/*         SHub Processor 0 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_adv_int_enable_u {
+	mmr_t	sh_proc0_adv_int_enable_regval;
+	struct {
+		mmr_t	proc0_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc0_adv_int_enable_s;
+} sh_proc0_adv_int_enable_u_t;
+#else
+typedef union sh_proc0_adv_int_enable_u {
+	mmr_t	sh_proc0_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc0_adv_enable : 1;
+	} sh_proc0_adv_int_enable_s;
+} sh_proc0_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_INT_ENABLE"                  */
+/*         SHub Processor 1 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_adv_int_enable_u {
+	mmr_t	sh_proc1_adv_int_enable_regval;
+	struct {
+		mmr_t	proc1_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc1_adv_int_enable_s;
+} sh_proc1_adv_int_enable_u_t;
+#else
+typedef union sh_proc1_adv_int_enable_u {
+	mmr_t	sh_proc1_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc1_adv_enable : 1;
+	} sh_proc1_adv_int_enable_s;
+} sh_proc1_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_INT_ENABLE"                  */
+/*         SHub Processor 2 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_adv_int_enable_u {
+	mmr_t	sh_proc2_adv_int_enable_regval;
+	struct {
+		mmr_t	proc2_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc2_adv_int_enable_s;
+} sh_proc2_adv_int_enable_u_t;
+#else
+typedef union sh_proc2_adv_int_enable_u {
+	mmr_t	sh_proc2_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc2_adv_enable : 1;
+	} sh_proc2_adv_int_enable_s;
+} sh_proc2_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_INT_ENABLE"                  */
+/*         SHub Processor 3 Advisory Interrupt Enable Registers         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_adv_int_enable_u {
+	mmr_t	sh_proc3_adv_int_enable_regval;
+	struct {
+		mmr_t	proc3_adv_enable : 1;
+		mmr_t	reserved_0       : 63;
+	} sh_proc3_adv_int_enable_s;
+} sh_proc3_adv_int_enable_u_t;
+#else
+typedef union sh_proc3_adv_int_enable_u {
+	mmr_t	sh_proc3_adv_int_enable_regval;
+	struct {
+		mmr_t	reserved_0       : 63;
+		mmr_t	proc3_adv_enable : 1;
+	} sh_proc3_adv_int_enable_s;
+} sh_proc3_adv_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_CONFIG"                   */
+/*            SHub Profile Interrupt Configuration Registers            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_int_config_u {
+	mmr_t	sh_profile_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_profile_int_config_s;
+} sh_profile_int_config_u_t;
+#else
+typedef union sh_profile_int_config_u {
+	mmr_t	sh_profile_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_profile_int_config_s;
+} sh_profile_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_INT_ENABLE"                   */
+/*               SHub Profile Interrupt Enable Registers                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_int_enable_u {
+	mmr_t	sh_profile_int_enable_regval;
+	struct {
+		mmr_t	profile_enable : 1;
+		mmr_t	reserved_0     : 63;
+	} sh_profile_int_enable_s;
+} sh_profile_int_enable_u_t;
+#else
+typedef union sh_profile_int_enable_u {
+	mmr_t	sh_profile_int_enable_regval;
+	struct {
+		mmr_t	reserved_0     : 63;
+		mmr_t	profile_enable : 1;
+	} sh_profile_int_enable_s;
+} sh_profile_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_CONFIG"                     */
+/*                SHub RTC 0 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc0_int_config_u {
+	mmr_t	sh_rtc0_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc0_int_config_s;
+} sh_rtc0_int_config_u_t;
+#else
+typedef union sh_rtc0_int_config_u {
+	mmr_t	sh_rtc0_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc0_int_config_s;
+} sh_rtc0_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC0_INT_ENABLE"                     */
+/*                SHub RTC 0 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc0_int_enable_u {
+	mmr_t	sh_rtc0_int_enable_regval;
+	struct {
+		mmr_t	rtc0_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc0_int_enable_s;
+} sh_rtc0_int_enable_u_t;
+#else
+typedef union sh_rtc0_int_enable_u {
+	mmr_t	sh_rtc0_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc0_enable : 1;
+	} sh_rtc0_int_enable_s;
+} sh_rtc0_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_CONFIG"                     */
+/*                SHub RTC 1 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc1_int_config_u {
+	mmr_t	sh_rtc1_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc1_int_config_s;
+} sh_rtc1_int_config_u_t;
+#else
+typedef union sh_rtc1_int_config_u {
+	mmr_t	sh_rtc1_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc1_int_config_s;
+} sh_rtc1_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC1_INT_ENABLE"                     */
+/*                SHub RTC 1 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc1_int_enable_u {
+	mmr_t	sh_rtc1_int_enable_regval;
+	struct {
+		mmr_t	rtc1_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc1_int_enable_s;
+} sh_rtc1_int_enable_u_t;
+#else
+typedef union sh_rtc1_int_enable_u {
+	mmr_t	sh_rtc1_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc1_enable : 1;
+	} sh_rtc1_int_enable_s;
+} sh_rtc1_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_CONFIG"                     */
+/*                SHub RTC 2 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc2_int_config_u {
+	mmr_t	sh_rtc2_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc2_int_config_s;
+} sh_rtc2_int_config_u_t;
+#else
+typedef union sh_rtc2_int_config_u {
+	mmr_t	sh_rtc2_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc2_int_config_s;
+} sh_rtc2_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC2_INT_ENABLE"                     */
+/*                SHub RTC 2 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc2_int_enable_u {
+	mmr_t	sh_rtc2_int_enable_regval;
+	struct {
+		mmr_t	rtc2_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc2_int_enable_s;
+} sh_rtc2_int_enable_u_t;
+#else
+typedef union sh_rtc2_int_enable_u {
+	mmr_t	sh_rtc2_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc2_enable : 1;
+	} sh_rtc2_int_enable_s;
+} sh_rtc2_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_CONFIG"                     */
+/*                SHub RTC 3 Interrupt Config Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc3_int_config_u {
+	mmr_t	sh_rtc3_int_config_regval;
+	struct {
+		mmr_t	type        : 3;
+		mmr_t	agt         : 1;
+		mmr_t	pid         : 16;
+		mmr_t	reserved_0  : 1;
+		mmr_t	base        : 29;
+		mmr_t	reserved_1  : 2;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_2  : 4;
+	} sh_rtc3_int_config_s;
+} sh_rtc3_int_config_u_t;
+#else
+typedef union sh_rtc3_int_config_u {
+	mmr_t	sh_rtc3_int_config_regval;
+	struct {
+		mmr_t	reserved_2  : 4;
+		mmr_t	idx         : 8;
+		mmr_t	reserved_1  : 2;
+		mmr_t	base        : 29;
+		mmr_t	reserved_0  : 1;
+		mmr_t	pid         : 16;
+		mmr_t	agt         : 1;
+		mmr_t	type        : 3;
+	} sh_rtc3_int_config_s;
+} sh_rtc3_int_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_RTC3_INT_ENABLE"                     */
+/*                SHub RTC 3 Interrupt Enable Registers                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc3_int_enable_u {
+	mmr_t	sh_rtc3_int_enable_regval;
+	struct {
+		mmr_t	rtc3_enable : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_rtc3_int_enable_s;
+} sh_rtc3_int_enable_u_t;
+#else
+typedef union sh_rtc3_int_enable_u {
+	mmr_t	sh_rtc3_int_enable_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	rtc3_enable : 1;
+	} sh_rtc3_int_enable_s;
+} sh_rtc3_int_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OCCURRED"                     */
+/*                    SHub Interrupt Event Occurred                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_event_occurred_u {
+	mmr_t	sh_event_occurred_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	profile_int         : 1;
+		mmr_t	ipi_int             : 1;
+		mmr_t	ii_int0             : 1;
+		mmr_t	ii_int1             : 1;
+		mmr_t	reserved_0          : 33;
+	} sh_event_occurred_s;
+} sh_event_occurred_u_t;
+#else
+typedef union sh_event_occurred_u {
+	mmr_t	sh_event_occurred_regval;
+	struct {
+		mmr_t	reserved_0          : 33;
+		mmr_t	ii_int1             : 1;
+		mmr_t	ii_int0             : 1;
+		mmr_t	ipi_int             : 1;
+		mmr_t	profile_int         : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_event_occurred_s;
+} sh_event_occurred_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_EVENT_OVERFLOW"                     */
+/*                SHub Interrupt Event Occurred Overflow                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_event_overflow_u {
+	mmr_t	sh_event_overflow_regval;
+	struct {
+		mmr_t	pi_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	profile_int         : 1;
+		mmr_t	reserved_0          : 36;
+	} sh_event_overflow_s;
+} sh_event_overflow_u_t;
+#else
+typedef union sh_event_overflow_u {
+	mmr_t	sh_event_overflow_regval;
+	struct {
+		mmr_t	reserved_0          : 36;
+		mmr_t	profile_int         : 1;
+		mmr_t	rtc3_int            : 1;
+		mmr_t	rtc2_int            : 1;
+		mmr_t	rtc1_int            : 1;
+		mmr_t	rtc0_int            : 1;
+		mmr_t	stop_clock          : 1;
+		mmr_t	l1_nmi_int          : 1;
+		mmr_t	uart_int            : 1;
+		mmr_t	system_shutdown_int : 1;
+		mmr_t	proc3_err_int       : 1;
+		mmr_t	proc2_err_int       : 1;
+		mmr_t	proc1_err_int       : 1;
+		mmr_t	proc0_err_int       : 1;
+		mmr_t	proc3_adv_int       : 1;
+		mmr_t	proc2_adv_int       : 1;
+		mmr_t	proc1_adv_int       : 1;
+		mmr_t	proc0_adv_int       : 1;
+		mmr_t	xn_uce_int          : 1;
+		mmr_t	md_uce_int          : 1;
+		mmr_t	pi_uce_int          : 1;
+		mmr_t	xn_ce_int           : 1;
+		mmr_t	md_ce_int           : 1;
+		mmr_t	pi_ce_int           : 1;
+		mmr_t	ii_hw_int           : 1;
+		mmr_t	lb_hw_int           : 1;
+		mmr_t	xn_hw_int           : 1;
+		mmr_t	md_hw_int           : 1;
+		mmr_t	pi_hw_int           : 1;
+	} sh_event_overflow_s;
+} sh_event_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_TIME"                      */
+/*                           Junk Bus Timing                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_time_u {
+	mmr_t	sh_junk_bus_time_regval;
+	struct {
+		mmr_t	fprom_setup_hold : 8;
+		mmr_t	fprom_enable     : 8;
+		mmr_t	uart_setup_hold  : 8;
+		mmr_t	uart_enable      : 8;
+		mmr_t	reserved_0       : 32;
+	} sh_junk_bus_time_s;
+} sh_junk_bus_time_u_t;
+#else
+typedef union sh_junk_bus_time_u {
+	mmr_t	sh_junk_bus_time_regval;
+	struct {
+		mmr_t	reserved_0       : 32;
+		mmr_t	uart_enable      : 8;
+		mmr_t	uart_setup_hold  : 8;
+		mmr_t	fprom_enable     : 8;
+		mmr_t	fprom_setup_hold : 8;
+	} sh_junk_bus_time_s;
+} sh_junk_bus_time_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_LATCH_TIME"                     */
+/*                        Junk Bus Latch Timing                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_latch_time_u {
+	mmr_t	sh_junk_latch_time_regval;
+	struct {
+		mmr_t	setup_hold  : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_junk_latch_time_s;
+} sh_junk_latch_time_u_t;
+#else
+typedef union sh_junk_latch_time_u {
+	mmr_t	sh_junk_latch_time_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	setup_hold  : 3;
+	} sh_junk_latch_time_s;
+} sh_junk_latch_time_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_JUNK_NACK_RESET"                     */
+/*                     Junk Bus Nack Counter Reset                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_nack_reset_u {
+	mmr_t	sh_junk_nack_reset_regval;
+	struct {
+		mmr_t	pulse       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_junk_nack_reset_s;
+} sh_junk_nack_reset_u_t;
+#else
+typedef union sh_junk_nack_reset_u {
+	mmr_t	sh_junk_nack_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	pulse       : 1;
+	} sh_junk_nack_reset_s;
+} sh_junk_nack_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED0"                      */
+/*                            Junk Bus LED0                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led0_u {
+	mmr_t	sh_junk_bus_led0_regval;
+	struct {
+		mmr_t	led0_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led0_s;
+} sh_junk_bus_led0_u_t;
+#else
+typedef union sh_junk_bus_led0_u {
+	mmr_t	sh_junk_bus_led0_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led0_data   : 8;
+	} sh_junk_bus_led0_s;
+} sh_junk_bus_led0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED1"                      */
+/*                            Junk Bus LED1                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led1_u {
+	mmr_t	sh_junk_bus_led1_regval;
+	struct {
+		mmr_t	led1_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led1_s;
+} sh_junk_bus_led1_u_t;
+#else
+typedef union sh_junk_bus_led1_u {
+	mmr_t	sh_junk_bus_led1_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led1_data   : 8;
+	} sh_junk_bus_led1_s;
+} sh_junk_bus_led1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED2"                      */
+/*                            Junk Bus LED2                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led2_u {
+	mmr_t	sh_junk_bus_led2_regval;
+	struct {
+		mmr_t	led2_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led2_s;
+} sh_junk_bus_led2_u_t;
+#else
+typedef union sh_junk_bus_led2_u {
+	mmr_t	sh_junk_bus_led2_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led2_data   : 8;
+	} sh_junk_bus_led2_s;
+} sh_junk_bus_led2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_JUNK_BUS_LED3"                      */
+/*                            Junk Bus LED3                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_bus_led3_u {
+	mmr_t	sh_junk_bus_led3_regval;
+	struct {
+		mmr_t	led3_data   : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_junk_bus_led3_s;
+} sh_junk_bus_led3_u_t;
+#else
+typedef union sh_junk_bus_led3_u {
+	mmr_t	sh_junk_bus_led3_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	led3_data   : 8;
+	} sh_junk_bus_led3_s;
+} sh_junk_bus_led3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_JUNK_ERROR_STATUS"                    */
+/*                        Junk Bus Error Status                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_junk_error_status_u {
+	mmr_t	sh_junk_error_status_regval;
+	struct {
+		mmr_t	address     : 47;
+		mmr_t	reserved_0  : 1;
+		mmr_t	cmd         : 8;
+		mmr_t	mode        : 1;
+		mmr_t	status      : 4;
+		mmr_t	reserved_1  : 3;
+	} sh_junk_error_status_s;
+} sh_junk_error_status_u_t;
+#else
+typedef union sh_junk_error_status_u {
+	mmr_t	sh_junk_error_status_regval;
+	struct {
+		mmr_t	reserved_1  : 3;
+		mmr_t	status      : 4;
+		mmr_t	mode        : 1;
+		mmr_t	cmd         : 8;
+		mmr_t	reserved_0  : 1;
+		mmr_t	address     : 47;
+	} sh_junk_error_status_s;
+} sh_junk_error_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_stat_u {
+	mmr_t	sh_ni0_llp_stat_regval;
+	struct {
+		mmr_t	link_reset_state : 4;
+		mmr_t	reserved_0       : 60;
+	} sh_ni0_llp_stat_s;
+} sh_ni0_llp_stat_u_t;
+#else
+typedef union sh_ni0_llp_stat_u {
+	mmr_t	sh_ni0_llp_stat_regval;
+	struct {
+		mmr_t	reserved_0       : 60;
+		mmr_t	link_reset_state : 4;
+	} sh_ni0_llp_stat_s;
+} sh_ni0_llp_stat_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_reset_u {
+	mmr_t	sh_ni0_llp_reset_regval;
+	struct {
+		mmr_t	link        : 1;
+		mmr_t	warm        : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_ni0_llp_reset_s;
+} sh_ni0_llp_reset_u_t;
+#else
+typedef union sh_ni0_llp_reset_u {
+	mmr_t	sh_ni0_llp_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	warm        : 1;
+		mmr_t	link        : 1;
+	} sh_ni0_llp_reset_s;
+} sh_ni0_llp_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_reset_en_u {
+	mmr_t	sh_ni0_llp_reset_en_regval;
+	struct {
+		mmr_t	ok          : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ni0_llp_reset_en_s;
+} sh_ni0_llp_reset_en_u_t;
+#else
+typedef union sh_ni0_llp_reset_en_u {
+	mmr_t	sh_ni0_llp_reset_en_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ok          : 1;
+	} sh_ni0_llp_reset_en_s;
+} sh_ni0_llp_reset_en_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_chan_mode_u {
+	mmr_t	sh_ni0_llp_chan_mode_regval;
+	struct {
+		mmr_t	bitmode32         : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	reserved_0        : 59;
+	} sh_ni0_llp_chan_mode_s;
+} sh_ni0_llp_chan_mode_u_t;
+#else
+typedef union sh_ni0_llp_chan_mode_u {
+	mmr_t	sh_ni0_llp_chan_mode_regval;
+	struct {
+		mmr_t	reserved_0        : 59;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	bitmode32         : 1;
+	} sh_ni0_llp_chan_mode_s;
+} sh_ni0_llp_chan_mode_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI0_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_config_u {
+	mmr_t	sh_ni0_llp_config_regval;
+	struct {
+		mmr_t	maxburst    : 10;
+		mmr_t	maxretry    : 10;
+		mmr_t	nulltimeout : 6;
+		mmr_t	ftu_time    : 12;
+		mmr_t	reserved_0  : 26;
+	} sh_ni0_llp_config_s;
+} sh_ni0_llp_config_u_t;
+#else
+typedef union sh_ni0_llp_config_u {
+	mmr_t	sh_ni0_llp_config_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	ftu_time    : 12;
+		mmr_t	nulltimeout : 6;
+		mmr_t	maxretry    : 10;
+		mmr_t	maxburst    : 10;
+	} sh_ni0_llp_config_s;
+} sh_ni0_llp_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_test_ctl_u {
+	mmr_t	sh_ni0_llp_test_ctl_regval;
+	struct {
+		mmr_t	pattern        : 40;
+		mmr_t	send_test_mode : 2;
+		mmr_t	reserved_0     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	noise_mode     : 2;
+		mmr_t	armcapture     : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	captured       : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	reserved_2     : 1;
+	} sh_ni0_llp_test_ctl_s;
+} sh_ni0_llp_test_ctl_u_t;
+#else
+typedef union sh_ni0_llp_test_ctl_u {
+	mmr_t	sh_ni0_llp_test_ctl_regval;
+	struct {
+		mmr_t	reserved_2     : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	captured       : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	armcapture     : 1;
+		mmr_t	noise_mode     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	reserved_1     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	send_test_mode : 2;
+		mmr_t	pattern        : 40;
+	} sh_ni0_llp_test_ctl_s;
+} sh_ni0_llp_test_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_capt_wd1_u {
+	mmr_t	sh_ni0_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd1_s;
+} sh_ni0_llp_capt_wd1_u_t;
+#else
+typedef union sh_ni0_llp_capt_wd1_u {
+	mmr_t	sh_ni0_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd1_s;
+} sh_ni0_llp_capt_wd1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_capt_wd2_u {
+	mmr_t	sh_ni0_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd2_s;
+} sh_ni0_llp_capt_wd2_u_t;
+#else
+typedef union sh_ni0_llp_capt_wd2_u {
+	mmr_t	sh_ni0_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni0_llp_capt_wd2_s;
+} sh_ni0_llp_capt_wd2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_capt_sbcb_u {
+	mmr_t	sh_ni0_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	capturedrcvsbsn  : 16;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	reserved_0       : 27;
+	} sh_ni0_llp_capt_sbcb_s;
+} sh_ni0_llp_capt_sbcb_u_t;
+#else
+typedef union sh_ni0_llp_capt_sbcb_u {
+	mmr_t	sh_ni0_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	reserved_0       : 27;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	capturedrcvsbsn  : 16;
+	} sh_ni0_llp_capt_sbcb_s;
+} sh_ni0_llp_capt_sbcb_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI0_LLP_ERR"                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_llp_err_u {
+	mmr_t	sh_ni0_llp_err_regval;
+	struct {
+		mmr_t	rx_sn_err_count : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	retry_count     : 8;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	squash          : 1;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	reserved_0      : 11;
+	} sh_ni0_llp_err_s;
+} sh_ni0_llp_err_u_t;
+#else
+typedef union sh_ni0_llp_err_u {
+	mmr_t	sh_ni0_llp_err_regval;
+	struct {
+		mmr_t	reserved_0      : 11;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	squash          : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	retry_count     : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	rx_sn_err_count : 8;
+	} sh_ni0_llp_err_s;
+} sh_ni0_llp_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_STAT"                      */
+/*               This register describes the LLP status.                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_stat_u {
+	mmr_t	sh_ni1_llp_stat_regval;
+	struct {
+		mmr_t	link_reset_state : 4;
+		mmr_t	reserved_0       : 60;
+	} sh_ni1_llp_stat_s;
+} sh_ni1_llp_stat_u_t;
+#else
+typedef union sh_ni1_llp_stat_u {
+	mmr_t	sh_ni1_llp_stat_regval;
+	struct {
+		mmr_t	reserved_0       : 60;
+		mmr_t	link_reset_state : 4;
+	} sh_ni1_llp_stat_s;
+} sh_ni1_llp_stat_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_RESET"                      */
+/*           Writing issues a reset to the network interface            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_reset_u {
+	mmr_t	sh_ni1_llp_reset_regval;
+	struct {
+		mmr_t	link        : 1;
+		mmr_t	warm        : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_ni1_llp_reset_s;
+} sh_ni1_llp_reset_u_t;
+#else
+typedef union sh_ni1_llp_reset_u {
+	mmr_t	sh_ni1_llp_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	warm        : 1;
+		mmr_t	link        : 1;
+	} sh_ni1_llp_reset_s;
+} sh_ni1_llp_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_RESET_EN"                    */
+/*                 Controls LLP warm reset propagation                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_reset_en_u {
+	mmr_t	sh_ni1_llp_reset_en_regval;
+	struct {
+		mmr_t	ok          : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_ni1_llp_reset_en_s;
+} sh_ni1_llp_reset_en_u_t;
+#else
+typedef union sh_ni1_llp_reset_en_u {
+	mmr_t	sh_ni1_llp_reset_en_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	ok          : 1;
+	} sh_ni1_llp_reset_en_s;
+} sh_ni1_llp_reset_en_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CHAN_MODE"                    */
+/*              Sets the signaling mode of LLP and channel              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_chan_mode_u {
+	mmr_t	sh_ni1_llp_chan_mode_regval;
+	struct {
+		mmr_t	bitmode32         : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	reserved_0        : 59;
+	} sh_ni1_llp_chan_mode_s;
+} sh_ni1_llp_chan_mode_u_t;
+#else
+typedef union sh_ni1_llp_chan_mode_u {
+	mmr_t	sh_ni1_llp_chan_mode_regval;
+	struct {
+		mmr_t	reserved_0        : 59;
+		mmr_t	enable_clkquad    : 1;
+		mmr_t	enable_rmt_ft_upd : 1;
+		mmr_t	enable_tuning     : 1;
+		mmr_t	ac_encode         : 1;
+		mmr_t	bitmode32         : 1;
+	} sh_ni1_llp_chan_mode_s;
+} sh_ni1_llp_chan_mode_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_NI1_LLP_CONFIG"                     */
+/*              Sets the configuration of LLP and channel               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_config_u {
+	mmr_t	sh_ni1_llp_config_regval;
+	struct {
+		mmr_t	maxburst    : 10;
+		mmr_t	maxretry    : 10;
+		mmr_t	nulltimeout : 6;
+		mmr_t	ftu_time    : 12;
+		mmr_t	reserved_0  : 26;
+	} sh_ni1_llp_config_s;
+} sh_ni1_llp_config_u_t;
+#else
+typedef union sh_ni1_llp_config_u {
+	mmr_t	sh_ni1_llp_config_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	ftu_time    : 12;
+		mmr_t	nulltimeout : 6;
+		mmr_t	maxretry    : 10;
+		mmr_t	maxburst    : 10;
+	} sh_ni1_llp_config_s;
+} sh_ni1_llp_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_TEST_CTL"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_test_ctl_u {
+	mmr_t	sh_ni1_llp_test_ctl_regval;
+	struct {
+		mmr_t	pattern        : 40;
+		mmr_t	send_test_mode : 2;
+		mmr_t	reserved_0     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	noise_mode     : 2;
+		mmr_t	armcapture     : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	captured       : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	reserved_2     : 1;
+	} sh_ni1_llp_test_ctl_s;
+} sh_ni1_llp_test_ctl_u_t;
+#else
+typedef union sh_ni1_llp_test_ctl_u {
+	mmr_t	sh_ni1_llp_test_ctl_regval;
+	struct {
+		mmr_t	reserved_2     : 1;
+		mmr_t	cberror        : 1;
+		mmr_t	captured       : 1;
+		mmr_t	fakesnerror    : 1;
+		mmr_t	sendsnerror    : 1;
+		mmr_t	sendcberror    : 1;
+		mmr_t	capturecbonly  : 1;
+		mmr_t	armcapture     : 1;
+		mmr_t	noise_mode     : 2;
+		mmr_t	lfsr_mode      : 2;
+		mmr_t	reserved_1     : 2;
+		mmr_t	wire_sel       : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	send_test_mode : 2;
+		mmr_t	pattern        : 40;
+	} sh_ni1_llp_test_ctl_s;
+} sh_ni1_llp_test_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD1"                    */
+/*                    low order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_capt_wd1_u {
+	mmr_t	sh_ni1_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd1_s;
+} sh_ni1_llp_capt_wd1_u_t;
+#else
+typedef union sh_ni1_llp_capt_wd1_u {
+	mmr_t	sh_ni1_llp_capt_wd1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd1_s;
+} sh_ni1_llp_capt_wd1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LLP_CAPT_WD2"                    */
+/*                   high order 64-bit captured word                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_capt_wd2_u {
+	mmr_t	sh_ni1_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd2_s;
+} sh_ni1_llp_capt_wd2_u_t;
+#else
+typedef union sh_ni1_llp_capt_wd2_u {
+	mmr_t	sh_ni1_llp_capt_wd2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_ni1_llp_capt_wd2_s;
+} sh_ni1_llp_capt_wd2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_LLP_CAPT_SBCB"                    */
+/*                 captured sideband, sequence, and CRC                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_capt_sbcb_u {
+	mmr_t	sh_ni1_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	capturedrcvsbsn  : 16;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	reserved_0       : 27;
+	} sh_ni1_llp_capt_sbcb_s;
+} sh_ni1_llp_capt_sbcb_u_t;
+#else
+typedef union sh_ni1_llp_capt_sbcb_u {
+	mmr_t	sh_ni1_llp_capt_sbcb_regval;
+	struct {
+		mmr_t	reserved_0       : 27;
+		mmr_t	chargeunderflow  : 1;
+		mmr_t	chargeoverflow   : 1;
+		mmr_t	fakedallsnerrors : 1;
+		mmr_t	sentallsnerrors  : 1;
+		mmr_t	sentallcberrors  : 1;
+		mmr_t	capturedrcvcrc   : 16;
+		mmr_t	capturedrcvsbsn  : 16;
+	} sh_ni1_llp_capt_sbcb_s;
+} sh_ni1_llp_capt_sbcb_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_NI1_LLP_ERR"                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_llp_err_u {
+	mmr_t	sh_ni1_llp_err_regval;
+	struct {
+		mmr_t	rx_sn_err_count : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	retry_count     : 8;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	squash          : 1;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	reserved_0      : 11;
+	} sh_ni1_llp_err_s;
+} sh_ni1_llp_err_u_t;
+#else
+typedef union sh_ni1_llp_err_u {
+	mmr_t	sh_ni1_llp_err_regval;
+	struct {
+		mmr_t	reserved_0      : 11;
+		mmr_t	wire_overflow   : 1;
+		mmr_t	wire_cnt        : 24;
+		mmr_t	power_not_ok    : 1;
+		mmr_t	squash          : 1;
+		mmr_t	rcv_link_reset  : 1;
+		mmr_t	retry_timeout   : 1;
+		mmr_t	retry_count     : 8;
+		mmr_t	rx_cb_err_count : 8;
+		mmr_t	rx_sn_err_count : 8;
+	} sh_ni1_llp_err_s;
+} sh_ni1_llp_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni0_llp_to_fifo02_flow_s;
+} sh_xnni0_llp_to_fifo02_flow_u_t;
+#else
+typedef union sh_xnni0_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_llp_to_fifo02_flow_s;
+} sh_xnni0_llp_to_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI0_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni0_llp_to_fifo13_flow_s;
+} sh_xnni0_llp_to_fifo13_flow_u_t;
+#else
+typedef union sh_xnni0_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni0_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_llp_to_fifo13_flow_s;
+} sh_xnni0_llp_to_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_llp_debit_flow_u {
+	mmr_t	sh_xnni0_llp_debit_flow_regval;
+	struct {
+		mmr_t	debit_vc0_dyn : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_7    : 3;
+	} sh_xnni0_llp_debit_flow_s;
+} sh_xnni0_llp_debit_flow_u_t;
+#else
+typedef union sh_xnni0_llp_debit_flow_u {
+	mmr_t	sh_xnni0_llp_debit_flow_regval;
+	struct {
+		mmr_t	reserved_7    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_dyn : 5;
+	} sh_xnni0_llp_debit_flow_s;
+} sh_xnni0_llp_debit_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_0_flow_u {
+	mmr_t	sh_xnni0_link_0_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_0_flow_s;
+} sh_xnni0_link_0_flow_u_t;
+#else
+typedef union sh_xnni0_link_0_flow_u {
+	mmr_t	sh_xnni0_link_0_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_link_0_flow_s;
+} sh_xnni0_link_0_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_1_flow_u {
+	mmr_t	sh_xnni0_link_1_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_1_flow_s;
+} sh_xnni0_link_1_flow_u_t;
+#else
+typedef union sh_xnni0_link_1_flow_u {
+	mmr_t	sh_xnni0_link_1_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni0_link_1_flow_s;
+} sh_xnni0_link_1_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_2_flow_u {
+	mmr_t	sh_xnni0_link_2_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_2_flow_s;
+} sh_xnni0_link_2_flow_u_t;
+#else
+typedef union sh_xnni0_link_2_flow_u {
+	mmr_t	sh_xnni0_link_2_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni0_link_2_flow_s;
+} sh_xnni0_link_2_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_link_3_flow_u {
+	mmr_t	sh_xnni0_link_3_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni0_link_3_flow_s;
+} sh_xnni0_link_3_flow_u_t;
+#else
+typedef union sh_xnni0_link_3_flow_u {
+	mmr_t	sh_xnni0_link_3_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni0_link_3_flow_s;
+} sh_xnni0_link_3_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO02_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni1_llp_to_fifo02_flow_s;
+} sh_xnni1_llp_to_fifo02_flow_u_t;
+#else
+typedef union sh_xnni1_llp_to_fifo02_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_llp_to_fifo02_flow_s;
+} sh_xnni1_llp_to_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XNNI1_LLP_TO_FIFO13_FLOW"                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnni1_llp_to_fifo13_flow_s;
+} sh_xnni1_llp_to_fifo13_flow_u_t;
+#else
+typedef union sh_xnni1_llp_to_fifo13_flow_u {
+	mmr_t	sh_xnni1_llp_to_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_llp_to_fifo13_flow_s;
+} sh_xnni1_llp_to_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_LLP_DEBIT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_llp_debit_flow_u {
+	mmr_t	sh_xnni1_llp_debit_flow_regval;
+	struct {
+		mmr_t	debit_vc0_dyn : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_7    : 3;
+	} sh_xnni1_llp_debit_flow_s;
+} sh_xnni1_llp_debit_flow_u_t;
+#else
+typedef union sh_xnni1_llp_debit_flow_u {
+	mmr_t	sh_xnni1_llp_debit_flow_regval;
+	struct {
+		mmr_t	reserved_7    : 3;
+		mmr_t	debit_vc3_cap : 5;
+		mmr_t	reserved_6    : 3;
+		mmr_t	debit_vc3_dyn : 5;
+		mmr_t	reserved_5    : 3;
+		mmr_t	debit_vc2_cap : 5;
+		mmr_t	reserved_4    : 3;
+		mmr_t	debit_vc2_dyn : 5;
+		mmr_t	reserved_3    : 3;
+		mmr_t	debit_vc1_cap : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	debit_vc1_dyn : 5;
+		mmr_t	reserved_1    : 3;
+		mmr_t	debit_vc0_cap : 5;
+		mmr_t	reserved_0    : 3;
+		mmr_t	debit_vc0_dyn : 5;
+	} sh_xnni1_llp_debit_flow_s;
+} sh_xnni1_llp_debit_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_0_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_0_flow_u {
+	mmr_t	sh_xnni1_link_0_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_0_flow_s;
+} sh_xnni1_link_0_flow_u_t;
+#else
+typedef union sh_xnni1_link_0_flow_u {
+	mmr_t	sh_xnni1_link_0_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_link_0_flow_s;
+} sh_xnni1_link_0_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_1_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_1_flow_u {
+	mmr_t	sh_xnni1_link_1_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_1_flow_s;
+} sh_xnni1_link_1_flow_u_t;
+#else
+typedef union sh_xnni1_link_1_flow_u {
+	mmr_t	sh_xnni1_link_1_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc1_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc1_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc1_test      : 7;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni1_link_1_flow_s;
+} sh_xnni1_link_1_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_2_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_2_flow_u {
+	mmr_t	sh_xnni1_link_2_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_2_flow_s;
+} sh_xnni1_link_2_flow_u_t;
+#else
+typedef union sh_xnni1_link_2_flow_u {
+	mmr_t	sh_xnni1_link_2_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni1_link_2_flow_s;
+} sh_xnni1_link_2_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_LINK_3_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_link_3_flow_u {
+	mmr_t	sh_xnni1_link_3_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_3           : 33;
+	} sh_xnni1_link_3_flow_s;
+} sh_xnni1_link_3_flow_u_t;
+#else
+typedef union sh_xnni1_link_3_flow_u {
+	mmr_t	sh_xnni1_link_3_flow_regval;
+	struct {
+		mmr_t	reserved_3           : 33;
+		mmr_t	credit_vc3_cap       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc3_dyn       : 7;
+		mmr_t	reserved_1           : 1;
+		mmr_t	credit_vc3_test      : 7;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni1_link_3_flow_s;
+} sh_xnni1_link_3_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_IILB_LOCAL_TABLE"                    */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_local_table_u {
+	mmr_t	sh_iilb_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	valid       : 1;
+	} sh_iilb_local_table_s;
+} sh_iilb_local_table_u_t;
+#else
+typedef union sh_iilb_local_table_u {
+	mmr_t	sh_iilb_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_iilb_local_table_s;
+} sh_iilb_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_IILB_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_global_table_u {
+	mmr_t	sh_iilb_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	valid       : 1;
+	} sh_iilb_global_table_s;
+} sh_iilb_global_table_u_t;
+#else
+typedef union sh_iilb_global_table_u {
+	mmr_t	sh_iilb_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_iilb_global_table_s;
+} sh_iilb_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_OVER_RIDE_TABLE"                  */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_over_ride_table_u {
+	mmr_t	sh_iilb_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	enable      : 1;
+	} sh_iilb_over_ride_table_s;
+} sh_iilb_over_ride_table_u_t;
+#else
+typedef union sh_iilb_over_ride_table_u {
+	mmr_t	sh_iilb_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 57;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_iilb_over_ride_table_s;
+} sh_iilb_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_IILB_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_iilb_rsp_plane_hint_u {
+	mmr_t	sh_iilb_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_iilb_rsp_plane_hint_s;
+} sh_iilb_rsp_plane_hint_u_t;
+#else
+typedef union sh_iilb_rsp_plane_hint_u {
+	mmr_t	sh_iilb_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_iilb_rsp_plane_hint_s;
+} sh_iilb_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_local_table_u {
+	mmr_t	sh_pi_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_pi_local_table_s;
+} sh_pi_local_table_u_t;
+#else
+typedef union sh_pi_local_table_u {
+	mmr_t	sh_pi_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_pi_local_table_s;
+} sh_pi_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_global_table_u {
+	mmr_t	sh_pi_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_pi_global_table_s;
+} sh_pi_global_table_u_t;
+#else
+typedef union sh_pi_global_table_u {
+	mmr_t	sh_pi_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_pi_global_table_s;
+} sh_pi_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_over_ride_table_u {
+	mmr_t	sh_pi_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	enable      : 1;
+	} sh_pi_over_ride_table_s;
+} sh_pi_over_ride_table_u_t;
+#else
+typedef union sh_pi_over_ride_table_u {
+	mmr_t	sh_pi_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_pi_over_ride_table_s;
+} sh_pi_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_rsp_plane_hint_u {
+	mmr_t	sh_pi_rsp_plane_hint_regval;
+	struct {
+		mmr_t	invert      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_pi_rsp_plane_hint_s;
+} sh_pi_rsp_plane_hint_u_t;
+#else
+typedef union sh_pi_rsp_plane_hint_u {
+	mmr_t	sh_pi_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	invert      : 1;
+	} sh_pi_rsp_plane_hint_s;
+} sh_pi_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_local_table_u {
+	mmr_t	sh_ni0_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni0_local_table_s;
+} sh_ni0_local_table_u_t;
+#else
+typedef union sh_ni0_local_table_u {
+	mmr_t	sh_ni0_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni0_local_table_s;
+} sh_ni0_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_global_table_u {
+	mmr_t	sh_ni0_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni0_global_table_s;
+} sh_ni0_global_table_u_t;
+#else
+typedef union sh_ni0_global_table_u {
+	mmr_t	sh_ni0_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni0_global_table_s;
+} sh_ni0_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_over_ride_table_u {
+	mmr_t	sh_ni0_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	enable      : 1;
+	} sh_ni0_over_ride_table_s;
+} sh_ni0_over_ride_table_u_t;
+#else
+typedef union sh_ni0_over_ride_table_u {
+	mmr_t	sh_ni0_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni0_over_ride_table_s;
+} sh_ni0_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_rsp_plane_hint_u {
+	mmr_t	sh_ni0_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni0_rsp_plane_hint_s;
+} sh_ni0_rsp_plane_hint_u_t;
+#else
+typedef union sh_ni0_rsp_plane_hint_u {
+	mmr_t	sh_ni0_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni0_rsp_plane_hint_s;
+} sh_ni0_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_local_table_u {
+	mmr_t	sh_ni1_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni1_local_table_s;
+} sh_ni1_local_table_u_t;
+#else
+typedef union sh_ni1_local_table_u {
+	mmr_t	sh_ni1_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni1_local_table_s;
+} sh_ni1_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_GLOBAL_TABLE"                    */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_global_table_u {
+	mmr_t	sh_ni1_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	valid       : 1;
+	} sh_ni1_global_table_s;
+} sh_ni1_global_table_u_t;
+#else
+typedef union sh_ni1_global_table_u {
+	mmr_t	sh_ni1_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni1_global_table_s;
+} sh_ni1_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_over_ride_table_u {
+	mmr_t	sh_ni1_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	enable      : 1;
+	} sh_ni1_over_ride_table_s;
+} sh_ni1_over_ride_table_u_t;
+#else
+typedef union sh_ni1_over_ride_table_u {
+	mmr_t	sh_ni1_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 58;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_ni1_over_ride_table_s;
+} sh_ni1_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_RSP_PLANE_HINT"                   */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_rsp_plane_hint_u {
+	mmr_t	sh_ni1_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni1_rsp_plane_hint_s;
+} sh_ni1_rsp_plane_hint_u_t;
+#else
+typedef union sh_ni1_rsp_plane_hint_u {
+	mmr_t	sh_ni1_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 64;
+	} sh_ni1_rsp_plane_hint_s;
+} sh_ni1_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LOCAL_TABLE"                     */
+/*                          local lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_local_table_u {
+	mmr_t	sh_md_local_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_md_local_table_s;
+} sh_md_local_table_u_t;
+#else
+typedef union sh_md_local_table_u {
+	mmr_t	sh_md_local_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_md_local_table_s;
+} sh_md_local_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_GLOBAL_TABLE"                     */
+/*                         global lookup table                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_global_table_u {
+	mmr_t	sh_md_global_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	valid       : 1;
+	} sh_md_global_table_s;
+} sh_md_global_table_u_t;
+#else
+typedef union sh_md_global_table_u {
+	mmr_t	sh_md_global_table_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_md_global_table_s;
+} sh_md_global_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_OVER_RIDE_TABLE"                   */
+/*              If enabled, bypass the Global/Local tables              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_over_ride_table_u {
+	mmr_t	sh_md_over_ride_table_regval;
+	struct {
+		mmr_t	dir0        : 4;
+		mmr_t	v0          : 1;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	reserved_0  : 2;
+		mmr_t	dir1        : 4;
+		mmr_t	v1          : 1;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	enable      : 1;
+	} sh_md_over_ride_table_s;
+} sh_md_over_ride_table_u_t;
+#else
+typedef union sh_md_over_ride_table_u {
+	mmr_t	sh_md_over_ride_table_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_1  : 49;
+		mmr_t	ni_sel1     : 1;
+		mmr_t	v1          : 1;
+		mmr_t	dir1        : 4;
+		mmr_t	reserved_0  : 2;
+		mmr_t	ni_sel0     : 1;
+		mmr_t	v0          : 1;
+		mmr_t	dir0        : 4;
+	} sh_md_over_ride_table_s;
+} sh_md_over_ride_table_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_RSP_PLANE_HINT"                    */
+/*  If enabled, invert incoming response only plane hint bit before lo  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_rsp_plane_hint_u {
+	mmr_t	sh_md_rsp_plane_hint_regval;
+	struct {
+		mmr_t	invert      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_md_rsp_plane_hint_s;
+} sh_md_rsp_plane_hint_u_t;
+#else
+typedef union sh_md_rsp_plane_hint_u {
+	mmr_t	sh_md_rsp_plane_hint_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	invert      : 1;
+	} sh_md_rsp_plane_hint_s;
+} sh_md_rsp_plane_hint_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LIQ_CTL"                       */
+/*                       Local Block LIQ Control                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_liq_ctl_u {
+	mmr_t	sh_lb_liq_ctl_regval;
+	struct {
+		mmr_t	liq_req_ctl        : 5;
+		mmr_t	reserved_0         : 3;
+		mmr_t	liq_rpl_ctl        : 4;
+		mmr_t	reserved_1         : 4;
+		mmr_t	force_rq_credit    : 1;
+		mmr_t	force_rp_credit    : 1;
+		mmr_t	force_linvv_credit : 1;
+		mmr_t	reserved_2         : 45;
+	} sh_lb_liq_ctl_s;
+} sh_lb_liq_ctl_u_t;
+#else
+typedef union sh_lb_liq_ctl_u {
+	mmr_t	sh_lb_liq_ctl_regval;
+	struct {
+		mmr_t	reserved_2         : 45;
+		mmr_t	force_linvv_credit : 1;
+		mmr_t	force_rp_credit    : 1;
+		mmr_t	force_rq_credit    : 1;
+		mmr_t	reserved_1         : 4;
+		mmr_t	liq_rpl_ctl        : 4;
+		mmr_t	reserved_0         : 3;
+		mmr_t	liq_req_ctl        : 5;
+	} sh_lb_liq_ctl_s;
+} sh_lb_liq_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_LB_LOQ_CTL"                       */
+/*                       Local Block LOQ Control                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_loq_ctl_u {
+	mmr_t	sh_lb_loq_ctl_regval;
+	struct {
+		mmr_t	loq_req_ctl : 1;
+		mmr_t	loq_rpl_ctl : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_lb_loq_ctl_s;
+} sh_lb_loq_ctl_u_t;
+#else
+typedef union sh_lb_loq_ctl_u {
+	mmr_t	sh_lb_loq_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	loq_rpl_ctl : 1;
+		mmr_t	loq_req_ctl : 1;
+	} sh_lb_loq_ctl_s;
+} sh_lb_loq_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REP_CREDIT_CNT"                  */
+/*               Maximum number of reply credits from XN                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_max_rep_credit_cnt_u {
+	mmr_t	sh_lb_max_rep_credit_cnt_regval;
+	struct {
+		mmr_t	max_cnt     : 5;
+		mmr_t	reserved_0  : 59;
+	} sh_lb_max_rep_credit_cnt_s;
+} sh_lb_max_rep_credit_cnt_u_t;
+#else
+typedef union sh_lb_max_rep_credit_cnt_u {
+	mmr_t	sh_lb_max_rep_credit_cnt_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	max_cnt     : 5;
+	} sh_lb_max_rep_credit_cnt_s;
+} sh_lb_max_rep_credit_cnt_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_LB_MAX_REQ_CREDIT_CNT"                  */
+/*              Maximum number of request credits from XN               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_max_req_credit_cnt_u {
+	mmr_t	sh_lb_max_req_credit_cnt_regval;
+	struct {
+		mmr_t	max_cnt     : 5;
+		mmr_t	reserved_0  : 59;
+	} sh_lb_max_req_credit_cnt_s;
+} sh_lb_max_req_credit_cnt_u_t;
+#else
+typedef union sh_lb_max_req_credit_cnt_u {
+	mmr_t	sh_lb_max_req_credit_cnt_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	max_cnt     : 5;
+	} sh_lb_max_req_credit_cnt_s;
+} sh_lb_max_req_credit_cnt_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_PIO_TIME_OUT"                      */
+/*                    Local Block PIO time out value                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_time_out_u {
+	mmr_t	sh_pio_time_out_regval;
+	struct {
+		mmr_t	value       : 16;
+		mmr_t	reserved_0  : 48;
+	} sh_pio_time_out_s;
+} sh_pio_time_out_u_t;
+#else
+typedef union sh_pio_time_out_u {
+	mmr_t	sh_pio_time_out_regval;
+	struct {
+		mmr_t	reserved_0  : 48;
+		mmr_t	value       : 16;
+	} sh_pio_time_out_s;
+} sh_pio_time_out_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_NACK_RESET"                     */
+/*               Local Block PIO Reset for nack counters                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_nack_reset_u {
+	mmr_t	sh_pio_nack_reset_regval;
+	struct {
+		mmr_t	pulse       : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_pio_nack_reset_s;
+} sh_pio_nack_reset_u_t;
+#else
+typedef union sh_pio_nack_reset_u {
+	mmr_t	sh_pio_nack_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	pulse       : 1;
+	} sh_pio_nack_reset_s;
+} sh_pio_nack_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_CONVEYOR_BELT_TIME_OUT"                 */
+/*               Local Block conveyor belt time out value               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_conveyor_belt_time_out_u {
+	mmr_t	sh_conveyor_belt_time_out_regval;
+	struct {
+		mmr_t	value       : 12;
+		mmr_t	reserved_0  : 52;
+	} sh_conveyor_belt_time_out_s;
+} sh_conveyor_belt_time_out_u_t;
+#else
+typedef union sh_conveyor_belt_time_out_u {
+	mmr_t	sh_conveyor_belt_time_out_regval;
+	struct {
+		mmr_t	reserved_0  : 52;
+		mmr_t	value       : 12;
+	} sh_conveyor_belt_time_out_s;
+} sh_conveyor_belt_time_out_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_CREDIT_STATUS"                    */
+/*                    Credit Counter Status Register                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_credit_status_u {
+	mmr_t	sh_lb_credit_status_regval;
+	struct {
+		mmr_t	liq_rq_credit : 5;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_1    : 2;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	reserved_2    : 36;
+	} sh_lb_credit_status_s;
+} sh_lb_credit_status_u_t;
+#else
+typedef union sh_lb_credit_status_u {
+	mmr_t	sh_lb_credit_status_regval;
+	struct {
+		mmr_t	reserved_2    : 36;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	reserved_1    : 2;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rq_credit : 5;
+	} sh_lb_credit_status_s;
+} sh_lb_credit_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_LOCAL_SEL"                   */
+/*                         LB Debug Port Select                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_local_sel_u {
+	mmr_t	sh_lb_debug_local_sel_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_lb_debug_local_sel_s;
+} sh_lb_debug_local_sel_u_t;
+#else
+typedef union sh_lb_debug_local_sel_u {
+	mmr_t	sh_lb_debug_local_sel_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_lb_debug_local_sel_s;
+} sh_lb_debug_local_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_PERF_SEL"                    */
+/*                   LB Debug Port Performance Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_perf_sel_u {
+	mmr_t	sh_lb_debug_perf_sel_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_15         : 1;
+	} sh_lb_debug_perf_sel_s;
+} sh_lb_debug_perf_sel_u_t;
+#else
+typedef union sh_lb_debug_perf_sel_u {
+	mmr_t	sh_lb_debug_perf_sel_regval;
+	struct {
+		mmr_t	reserved_15         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_lb_debug_perf_sel_s;
+} sh_lb_debug_perf_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_DEBUG_TRIG_SEL"                    */
+/*                       LB Debug Trigger Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_trig_sel_u {
+	mmr_t	sh_lb_debug_trig_sel_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_lb_debug_trig_sel_s;
+} sh_lb_debug_trig_sel_u_t;
+#else
+typedef union sh_lb_debug_trig_sel_u {
+	mmr_t	sh_lb_debug_trig_sel_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_lb_debug_trig_sel_s;
+} sh_lb_debug_trig_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_1"                    */
+/*                  LB Error capture information: HDR1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_1_u {
+	mmr_t	sh_lb_error_detail_1_regval;
+	struct {
+		mmr_t	command     : 8;
+		mmr_t	suppl       : 14;
+		mmr_t	reserved_0  : 2;
+		mmr_t	source      : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	dest        : 3;
+		mmr_t	reserved_2  : 5;
+		mmr_t	hdr_err     : 1;
+		mmr_t	data_err    : 1;
+		mmr_t	reserved_3  : 13;
+		mmr_t	valid       : 1;
+	} sh_lb_error_detail_1_s;
+} sh_lb_error_detail_1_u_t;
+#else
+typedef union sh_lb_error_detail_1_u {
+	mmr_t	sh_lb_error_detail_1_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_3  : 13;
+		mmr_t	data_err    : 1;
+		mmr_t	hdr_err     : 1;
+		mmr_t	reserved_2  : 5;
+		mmr_t	dest        : 3;
+		mmr_t	reserved_1  : 2;
+		mmr_t	source      : 14;
+		mmr_t	reserved_0  : 2;
+		mmr_t	suppl       : 14;
+		mmr_t	command     : 8;
+	} sh_lb_error_detail_1_s;
+} sh_lb_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_2"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_2_u {
+	mmr_t	sh_lb_error_detail_2_regval;
+	struct {
+		mmr_t	address     : 47;
+		mmr_t	reserved_0  : 17;
+	} sh_lb_error_detail_2_s;
+} sh_lb_error_detail_2_u_t;
+#else
+typedef union sh_lb_error_detail_2_u {
+	mmr_t	sh_lb_error_detail_2_regval;
+	struct {
+		mmr_t	reserved_0  : 17;
+		mmr_t	address     : 47;
+	} sh_lb_error_detail_2_s;
+} sh_lb_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_3"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_3_u {
+	mmr_t	sh_lb_error_detail_3_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_lb_error_detail_3_s;
+} sh_lb_error_detail_3_u_t;
+#else
+typedef union sh_lb_error_detail_3_u {
+	mmr_t	sh_lb_error_detail_3_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_lb_error_detail_3_s;
+} sh_lb_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_4"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_4_u {
+	mmr_t	sh_lb_error_detail_4_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_lb_error_detail_4_s;
+} sh_lb_error_detail_4_u_t;
+#else
+typedef union sh_lb_error_detail_4_u {
+	mmr_t	sh_lb_error_detail_4_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_lb_error_detail_4_s;
+} sh_lb_error_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_DETAIL_5"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_detail_5_u {
+	mmr_t	sh_lb_error_detail_5_regval;
+	struct {
+		mmr_t	read_retry       : 1;
+		mmr_t	ptc1_write       : 1;
+		mmr_t	write_retry      : 1;
+		mmr_t	count_a_overflow : 1;
+		mmr_t	count_b_overflow : 1;
+		mmr_t	nack_a_timeout   : 1;
+		mmr_t	nack_b_timeout   : 1;
+		mmr_t	reserved_0       : 57;
+	} sh_lb_error_detail_5_s;
+} sh_lb_error_detail_5_u_t;
+#else
+typedef union sh_lb_error_detail_5_u {
+	mmr_t	sh_lb_error_detail_5_regval;
+	struct {
+		mmr_t	reserved_0       : 57;
+		mmr_t	nack_b_timeout   : 1;
+		mmr_t	nack_a_timeout   : 1;
+		mmr_t	count_b_overflow : 1;
+		mmr_t	count_a_overflow : 1;
+		mmr_t	write_retry      : 1;
+		mmr_t	ptc1_write       : 1;
+		mmr_t	read_retry       : 1;
+	} sh_lb_error_detail_5_s;
+} sh_lb_error_detail_5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_ERROR_MASK"                      */
+/*                            LB Error Mask                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_mask_u {
+	mmr_t	sh_lb_error_mask_regval;
+	struct {
+		mmr_t	rq_bad_cmd            : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	reserved_0            : 41;
+	} sh_lb_error_mask_s;
+} sh_lb_error_mask_u_t;
+#else
+typedef union sh_lb_error_mask_u {
+	mmr_t	sh_lb_error_mask_regval;
+	struct {
+		mmr_t	reserved_0            : 41;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_bad_cmd            : 1;
+	} sh_lb_error_mask_s;
+} sh_lb_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_ERROR_OVERFLOW"                    */
+/*                          LB Error Overflow                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_overflow_u {
+	mmr_t	sh_lb_error_overflow_regval;
+	struct {
+		mmr_t	rq_bad_cmd_ovrfl            : 1;
+		mmr_t	rp_bad_cmd_ovrfl            : 1;
+		mmr_t	rq_short_ovrfl              : 1;
+		mmr_t	rp_short_ovrfl              : 1;
+		mmr_t	rq_long_ovrfl               : 1;
+		mmr_t	rp_long_ovrfl               : 1;
+		mmr_t	rq_bad_data_ovrfl           : 1;
+		mmr_t	rp_bad_data_ovrfl           : 1;
+		mmr_t	rq_bad_addr_ovrfl           : 1;
+		mmr_t	rq_time_out_ovrfl           : 1;
+		mmr_t	linvv_overflow_ovrfl        : 1;
+		mmr_t	unexpected_linv_ovrfl       : 1;
+		mmr_t	ptc_1_timeout_ovrfl         : 1;
+		mmr_t	junk_bus_err_ovrfl          : 1;
+		mmr_t	pio_cb_err_ovrfl            : 1;
+		mmr_t	vector_rq_route_error_ovrfl : 1;
+		mmr_t	vector_rp_route_error_ovrfl : 1;
+		mmr_t	gclk_drop_ovrfl             : 1;
+		mmr_t	rq_fifo_error_ovrfl         : 1;
+		mmr_t	rp_fifo_error_ovrfl         : 1;
+		mmr_t	unexp_valid_ovrfl           : 1;
+		mmr_t	rq_credit_overflow_ovrfl    : 1;
+		mmr_t	rp_credit_overflow_ovrfl    : 1;
+		mmr_t	reserved_0                  : 41;
+	} sh_lb_error_overflow_s;
+} sh_lb_error_overflow_u_t;
+#else
+typedef union sh_lb_error_overflow_u {
+	mmr_t	sh_lb_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0                  : 41;
+		mmr_t	rp_credit_overflow_ovrfl    : 1;
+		mmr_t	rq_credit_overflow_ovrfl    : 1;
+		mmr_t	unexp_valid_ovrfl           : 1;
+		mmr_t	rp_fifo_error_ovrfl         : 1;
+		mmr_t	rq_fifo_error_ovrfl         : 1;
+		mmr_t	gclk_drop_ovrfl             : 1;
+		mmr_t	vector_rp_route_error_ovrfl : 1;
+		mmr_t	vector_rq_route_error_ovrfl : 1;
+		mmr_t	pio_cb_err_ovrfl            : 1;
+		mmr_t	junk_bus_err_ovrfl          : 1;
+		mmr_t	ptc_1_timeout_ovrfl         : 1;
+		mmr_t	unexpected_linv_ovrfl       : 1;
+		mmr_t	linvv_overflow_ovrfl        : 1;
+		mmr_t	rq_time_out_ovrfl           : 1;
+		mmr_t	rq_bad_addr_ovrfl           : 1;
+		mmr_t	rp_bad_data_ovrfl           : 1;
+		mmr_t	rq_bad_data_ovrfl           : 1;
+		mmr_t	rp_long_ovrfl               : 1;
+		mmr_t	rq_long_ovrfl               : 1;
+		mmr_t	rp_short_ovrfl              : 1;
+		mmr_t	rq_short_ovrfl              : 1;
+		mmr_t	rp_bad_cmd_ovrfl            : 1;
+		mmr_t	rq_bad_cmd_ovrfl            : 1;
+	} sh_lb_error_overflow_s;
+} sh_lb_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_ERROR_SUMMARY"                    */
+/*                            LB Error Bits                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_error_summary_u {
+	mmr_t	sh_lb_error_summary_regval;
+	struct {
+		mmr_t	rq_bad_cmd            : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	reserved_0            : 41;
+	} sh_lb_error_summary_s;
+} sh_lb_error_summary_u_t;
+#else
+typedef union sh_lb_error_summary_u {
+	mmr_t	sh_lb_error_summary_regval;
+	struct {
+		mmr_t	reserved_0            : 41;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_bad_cmd            : 1;
+	} sh_lb_error_summary_s;
+} sh_lb_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_FIRST_ERROR"                     */
+/*                            LB First Error                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_first_error_u {
+	mmr_t	sh_lb_first_error_regval;
+	struct {
+		mmr_t	rq_bad_cmd            : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	reserved_0            : 41;
+	} sh_lb_first_error_s;
+} sh_lb_first_error_u_t;
+#else
+typedef union sh_lb_first_error_u {
+	mmr_t	sh_lb_first_error_regval;
+	struct {
+		mmr_t	reserved_0            : 41;
+		mmr_t	rp_credit_overflow    : 1;
+		mmr_t	rq_credit_overflow    : 1;
+		mmr_t	unexp_valid           : 1;
+		mmr_t	rp_fifo_error         : 1;
+		mmr_t	rq_fifo_error         : 1;
+		mmr_t	gclk_drop             : 1;
+		mmr_t	vector_rp_route_error : 1;
+		mmr_t	vector_rq_route_error : 1;
+		mmr_t	pio_cb_err            : 1;
+		mmr_t	junk_bus_err          : 1;
+		mmr_t	ptc_1_timeout         : 1;
+		mmr_t	unexpected_linv       : 1;
+		mmr_t	linvv_overflow        : 1;
+		mmr_t	rq_time_out           : 1;
+		mmr_t	rq_bad_addr           : 1;
+		mmr_t	rp_bad_data           : 1;
+		mmr_t	rq_bad_data           : 1;
+		mmr_t	rp_long               : 1;
+		mmr_t	rq_long               : 1;
+		mmr_t	rp_short              : 1;
+		mmr_t	rq_short              : 1;
+		mmr_t	rp_bad_cmd            : 1;
+		mmr_t	rq_bad_cmd            : 1;
+	} sh_lb_first_error_s;
+} sh_lb_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_LAST_CREDIT"                     */
+/*                    Credit counter status register                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_last_credit_u {
+	mmr_t	sh_lb_last_credit_regval;
+	struct {
+		mmr_t	liq_rq_credit : 5;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_1    : 2;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	reserved_2    : 36;
+	} sh_lb_last_credit_s;
+} sh_lb_last_credit_u_t;
+#else
+typedef union sh_lb_last_credit_u {
+	mmr_t	sh_lb_last_credit_regval;
+	struct {
+		mmr_t	reserved_2    : 36;
+		mmr_t	loq_rp_credit : 5;
+		mmr_t	loq_rq_credit : 5;
+		mmr_t	linvv_credit  : 6;
+		mmr_t	reserved_1    : 2;
+		mmr_t	liq_rp_credit : 4;
+		mmr_t	reserved_0    : 1;
+		mmr_t	liq_rq_credit : 5;
+	} sh_lb_last_credit_s;
+} sh_lb_last_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_NACK_STATUS"                     */
+/*                     Nack Counter Status Register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_nack_status_u {
+	mmr_t	sh_lb_nack_status_regval;
+	struct {
+		mmr_t	pio_nack_a       : 12;
+		mmr_t	reserved_0       : 4;
+		mmr_t	pio_nack_b       : 12;
+		mmr_t	reserved_1       : 4;
+		mmr_t	junk_nack        : 16;
+		mmr_t	cb_timeout_count : 12;
+		mmr_t	cb_state         : 2;
+		mmr_t	reserved_2       : 2;
+	} sh_lb_nack_status_s;
+} sh_lb_nack_status_u_t;
+#else
+typedef union sh_lb_nack_status_u {
+	mmr_t	sh_lb_nack_status_regval;
+	struct {
+		mmr_t	reserved_2       : 2;
+		mmr_t	cb_state         : 2;
+		mmr_t	cb_timeout_count : 12;
+		mmr_t	junk_nack        : 16;
+		mmr_t	reserved_1       : 4;
+		mmr_t	pio_nack_b       : 12;
+		mmr_t	reserved_0       : 4;
+		mmr_t	pio_nack_a       : 12;
+	} sh_lb_nack_status_s;
+} sh_lb_nack_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_LB_TRIGGER_COMPARE"                   */
+/*                    LB Test-point Trigger Compare                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_trigger_compare_u {
+	mmr_t	sh_lb_trigger_compare_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_lb_trigger_compare_s;
+} sh_lb_trigger_compare_u_t;
+#else
+typedef union sh_lb_trigger_compare_u {
+	mmr_t	sh_lb_trigger_compare_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	mask        : 32;
+	} sh_lb_trigger_compare_s;
+} sh_lb_trigger_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_TRIGGER_DATA"                     */
+/*                  LB Test-point Trigger Compare Data                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_trigger_data_u {
+	mmr_t	sh_lb_trigger_data_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	reserved_0      : 32;
+	} sh_lb_trigger_data_s;
+} sh_lb_trigger_data_u_t;
+#else
+typedef union sh_lb_trigger_data_u {
+	mmr_t	sh_lb_trigger_data_regval;
+	struct {
+		mmr_t	reserved_0      : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_lb_trigger_data_s;
+} sh_lb_trigger_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_CONFIG"                      */
+/*              PI Adaptive Error Correction Configuration              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_aec_config_u {
+	mmr_t	sh_pi_aec_config_regval;
+	struct {
+		mmr_t	mode        : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_aec_config_s;
+} sh_pi_aec_config_u_t;
+#else
+typedef union sh_pi_aec_config_u {
+	mmr_t	sh_pi_aec_config_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	mode        : 3;
+	} sh_pi_aec_config_s;
+} sh_pi_aec_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_ERROR_MASK"                    */
+/*                          PI AFI Error Mask                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_error_mask_u {
+	mmr_t	sh_pi_afi_error_mask_regval;
+	struct {
+		mmr_t	reserved_0   : 21;
+		mmr_t	hung_bus     : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	msg_len      : 1;
+		mmr_t	reserved_1   : 29;
+	} sh_pi_afi_error_mask_s;
+} sh_pi_afi_error_mask_u_t;
+#else
+typedef union sh_pi_afi_error_mask_u {
+	mmr_t	sh_pi_afi_error_mask_regval;
+	struct {
+		mmr_t	reserved_1   : 29;
+		mmr_t	msg_len      : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	hung_bus     : 1;
+		mmr_t	reserved_0   : 21;
+	} sh_pi_afi_error_mask_s;
+} sh_pi_afi_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_AFI_TEST_POINT_COMPARE"                */
+/*                      PI AFI Test Point Compare                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_test_point_compare_u {
+	mmr_t	sh_pi_afi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_afi_test_point_compare_s;
+} sh_pi_afi_test_point_compare_u_t;
+#else
+typedef union sh_pi_afi_test_point_compare_u {
+	mmr_t	sh_pi_afi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_afi_test_point_compare_s;
+} sh_pi_afi_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_AFI_TEST_POINT_SELECT"                */
+/*                       PI AFI Test Point Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_test_point_select_u {
+	mmr_t	sh_pi_afi_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 4;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble1_chiplet_sel : 4;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble2_chiplet_sel : 4;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble3_chiplet_sel : 4;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble4_chiplet_sel : 4;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble5_chiplet_sel : 4;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble6_chiplet_sel : 4;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble7_chiplet_sel : 4;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_afi_test_point_select_s;
+} sh_pi_afi_test_point_select_u_t;
+#else
+typedef union sh_pi_afi_test_point_select_u {
+	mmr_t	sh_pi_afi_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	nibble7_chiplet_sel : 4;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	nibble6_chiplet_sel : 4;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	nibble5_chiplet_sel : 4;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	nibble4_chiplet_sel : 4;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	nibble3_chiplet_sel : 4;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	nibble2_chiplet_sel : 4;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	nibble1_chiplet_sel : 4;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	nibble0_chiplet_sel : 4;
+	} sh_pi_afi_test_point_select_s;
+} sh_pi_afi_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_PI_AFI_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_test_point_trigger_select_u {
+	mmr_t	sh_pi_afi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 4;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger1_chiplet_sel : 4;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger2_chiplet_sel : 4;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger3_chiplet_sel : 4;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger4_chiplet_sel : 4;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger5_chiplet_sel : 4;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger6_chiplet_sel : 4;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger7_chiplet_sel : 4;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+	} sh_pi_afi_test_point_trigger_select_s;
+} sh_pi_afi_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_afi_test_point_trigger_select_u {
+	mmr_t	sh_pi_afi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	trigger7_chiplet_sel : 4;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	trigger6_chiplet_sel : 4;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	trigger5_chiplet_sel : 4;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	trigger4_chiplet_sel : 4;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	trigger3_chiplet_sel : 4;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	trigger2_chiplet_sel : 4;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	trigger1_chiplet_sel : 4;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	trigger0_chiplet_sel : 4;
+	} sh_pi_afi_test_point_trigger_select_s;
+} sh_pi_afi_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_AUTO_REPLY_ENABLE"                  */
+/*                         PI Auto Reply Enable                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_auto_reply_enable_u {
+	mmr_t	sh_pi_auto_reply_enable_regval;
+	struct {
+		mmr_t	auto_reply_enable : 1;
+		mmr_t	reserved_0        : 63;
+	} sh_pi_auto_reply_enable_s;
+} sh_pi_auto_reply_enable_u_t;
+#else
+typedef union sh_pi_auto_reply_enable_u {
+	mmr_t	sh_pi_auto_reply_enable_regval;
+	struct {
+		mmr_t	reserved_0        : 63;
+		mmr_t	auto_reply_enable : 1;
+	} sh_pi_auto_reply_enable_s;
+} sh_pi_auto_reply_enable_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_CAM_CONTROL"                     */
+/*                      CRB CAM MMR Access Control                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_control_u {
+	mmr_t	sh_pi_cam_control_regval;
+	struct {
+		mmr_t	cam_indx          : 7;
+		mmr_t	reserved_0        : 1;
+		mmr_t	cam_write         : 1;
+		mmr_t	rrb_rd_xfer_clear : 1;
+		mmr_t	reserved_1        : 53;
+		mmr_t	start             : 1;
+	} sh_pi_cam_control_s;
+} sh_pi_cam_control_u_t;
+#else
+typedef union sh_pi_cam_control_u {
+	mmr_t	sh_pi_cam_control_regval;
+	struct {
+		mmr_t	start             : 1;
+		mmr_t	reserved_1        : 53;
+		mmr_t	rrb_rd_xfer_clear : 1;
+		mmr_t	cam_write         : 1;
+		mmr_t	reserved_0        : 1;
+		mmr_t	cam_indx          : 7;
+	} sh_pi_cam_control_s;
+} sh_pi_cam_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_COMPARE"               */
+/*                      PI CRBC Test Point Compare                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbc_test_point_compare_u {
+	mmr_t	sh_pi_crbc_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_crbc_test_point_compare_s;
+} sh_pi_crbc_test_point_compare_u_t;
+#else
+typedef union sh_pi_crbc_test_point_compare_u {
+	mmr_t	sh_pi_crbc_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_crbc_test_point_compare_s;
+} sh_pi_crbc_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBC_TEST_POINT_SELECT"                */
+/*                      PI CRBC Test Point Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbc_test_point_select_u {
+	mmr_t	sh_pi_crbc_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_crbc_test_point_select_s;
+} sh_pi_crbc_test_point_select_u_t;
+#else
+typedef union sh_pi_crbc_test_point_select_u {
+	mmr_t	sh_pi_crbc_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_pi_crbc_test_point_select_s;
+} sh_pi_crbc_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBC_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBC Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbc_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbc_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_pi_crbc_test_point_trigger_select_s;
+} sh_pi_crbc_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_crbc_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbc_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_pi_crbc_test_point_trigger_select_s;
+} sh_pi_crbc_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_CRBP_ERROR_MASK"                   */
+/*                          PI CRBP Error Mask                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_error_mask_u {
+	mmr_t	sh_pi_crbp_error_mask_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	reserved_0      : 43;
+	} sh_pi_crbp_error_mask_s;
+} sh_pi_crbp_error_mask_u_t;
+#else
+typedef union sh_pi_crbp_error_mask_u {
+	mmr_t	sh_pi_crbp_error_mask_regval;
+	struct {
+		mmr_t	reserved_0      : 43;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_crbp_error_mask_s;
+} sh_pi_crbp_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_CRBP_FSB_PIPE_COMPARE"                */
+/*                        CRBP FSB Pipe Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_fsb_pipe_compare_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_compare_regval;
+	struct {
+		mmr_t	compare_address : 47;
+		mmr_t	compare_req     : 6;
+		mmr_t	reserved_0      : 11;
+	} sh_pi_crbp_fsb_pipe_compare_s;
+} sh_pi_crbp_fsb_pipe_compare_u_t;
+#else
+typedef union sh_pi_crbp_fsb_pipe_compare_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_compare_regval;
+	struct {
+		mmr_t	reserved_0      : 11;
+		mmr_t	compare_req     : 6;
+		mmr_t	compare_address : 47;
+	} sh_pi_crbp_fsb_pipe_compare_s;
+} sh_pi_crbp_fsb_pipe_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_FSB_PIPE_MASK"                  */
+/*                          CRBP Compare Mask                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_fsb_pipe_mask_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_mask_regval;
+	struct {
+		mmr_t	compare_address_mask : 47;
+		mmr_t	compare_req_mask     : 6;
+		mmr_t	reserved_0           : 11;
+	} sh_pi_crbp_fsb_pipe_mask_s;
+} sh_pi_crbp_fsb_pipe_mask_u_t;
+#else
+typedef union sh_pi_crbp_fsb_pipe_mask_u {
+	mmr_t	sh_pi_crbp_fsb_pipe_mask_regval;
+	struct {
+		mmr_t	reserved_0           : 11;
+		mmr_t	compare_req_mask     : 6;
+		mmr_t	compare_address_mask : 47;
+	} sh_pi_crbp_fsb_pipe_mask_s;
+} sh_pi_crbp_fsb_pipe_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_COMPARE"               */
+/*                      PI CRBP Test Point Compare                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_test_point_compare_u {
+	mmr_t	sh_pi_crbp_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_crbp_test_point_compare_s;
+} sh_pi_crbp_test_point_compare_u_t;
+#else
+typedef union sh_pi_crbp_test_point_compare_u {
+	mmr_t	sh_pi_crbp_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_crbp_test_point_compare_s;
+} sh_pi_crbp_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_TEST_POINT_SELECT"                */
+/*                      PI CRBP Test Point Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_test_point_select_u {
+	mmr_t	sh_pi_crbp_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_crbp_test_point_select_s;
+} sh_pi_crbp_test_point_select_u_t;
+#else
+typedef union sh_pi_crbp_test_point_select_u {
+	mmr_t	sh_pi_crbp_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_pi_crbp_test_point_select_s;
+} sh_pi_crbp_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*           Register "SH_PI_CRBP_TEST_POINT_TRIGGER_SELECT"            */
+/*                  PI CRBP Test Point Trigger Select                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbp_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_pi_crbp_test_point_trigger_select_s;
+} sh_pi_crbp_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_crbp_test_point_trigger_select_u {
+	mmr_t	sh_pi_crbp_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_pi_crbp_test_point_trigger_select_s;
+} sh_pi_crbp_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_0"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_compare_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_0_regval;
+	struct {
+		mmr_t	compare_address : 47;
+		mmr_t	compare_command : 8;
+		mmr_t	reserved_0      : 9;
+	} sh_pi_crbp_xb_pipe_compare_0_s;
+} sh_pi_crbp_xb_pipe_compare_0_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_compare_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_0_regval;
+	struct {
+		mmr_t	reserved_0      : 9;
+		mmr_t	compare_command : 8;
+		mmr_t	compare_address : 47;
+	} sh_pi_crbp_xb_pipe_compare_0_s;
+} sh_pi_crbp_xb_pipe_compare_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_CRBP_XB_PIPE_COMPARE_1"                */
+/*                         CRBP XB Pipe Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_compare_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_1_regval;
+	struct {
+		mmr_t	compare_source       : 14;
+		mmr_t	reserved_0           : 2;
+		mmr_t	compare_supplemental : 14;
+		mmr_t	reserved_1           : 2;
+		mmr_t	compare_echo         : 9;
+		mmr_t	reserved_2           : 23;
+	} sh_pi_crbp_xb_pipe_compare_1_s;
+} sh_pi_crbp_xb_pipe_compare_1_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_compare_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_compare_1_regval;
+	struct {
+		mmr_t	reserved_2           : 23;
+		mmr_t	compare_echo         : 9;
+		mmr_t	reserved_1           : 2;
+		mmr_t	compare_supplemental : 14;
+		mmr_t	reserved_0           : 2;
+		mmr_t	compare_source       : 14;
+	} sh_pi_crbp_xb_pipe_compare_1_s;
+} sh_pi_crbp_xb_pipe_compare_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_0"                 */
+/*                     CRBP Compare Mask Register 1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_mask_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_0_regval;
+	struct {
+		mmr_t	compare_address_mask : 47;
+		mmr_t	compare_command_mask : 8;
+		mmr_t	reserved_0           : 9;
+	} sh_pi_crbp_xb_pipe_mask_0_s;
+} sh_pi_crbp_xb_pipe_mask_0_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_mask_0_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_0_regval;
+	struct {
+		mmr_t	reserved_0           : 9;
+		mmr_t	compare_command_mask : 8;
+		mmr_t	compare_address_mask : 47;
+	} sh_pi_crbp_xb_pipe_mask_0_s;
+} sh_pi_crbp_xb_pipe_mask_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CRBP_XB_PIPE_MASK_1"                 */
+/*                 CRBP XB Pipe Compare Mask Register 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_xb_pipe_mask_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_1_regval;
+	struct {
+		mmr_t	compare_source_mask       : 14;
+		mmr_t	reserved_0                : 2;
+		mmr_t	compare_supplemental_mask : 14;
+		mmr_t	reserved_1                : 2;
+		mmr_t	compare_echo_mask         : 9;
+		mmr_t	reserved_2                : 23;
+	} sh_pi_crbp_xb_pipe_mask_1_s;
+} sh_pi_crbp_xb_pipe_mask_1_u_t;
+#else
+typedef union sh_pi_crbp_xb_pipe_mask_1_u {
+	mmr_t	sh_pi_crbp_xb_pipe_mask_1_regval;
+	struct {
+		mmr_t	reserved_2                : 23;
+		mmr_t	compare_echo_mask         : 9;
+		mmr_t	reserved_1                : 2;
+		mmr_t	compare_supplemental_mask : 14;
+		mmr_t	reserved_0                : 2;
+		mmr_t	compare_source_mask       : 14;
+	} sh_pi_crbp_xb_pipe_mask_1_s;
+} sh_pi_crbp_xb_pipe_mask_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_DPC_QUEUE_CONFIG"                   */
+/*                       DPC Queue Configuration                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_dpc_queue_config_u {
+	mmr_t	sh_pi_dpc_queue_config_regval;
+	struct {
+		mmr_t	dwcq_ae_level  : 5;
+		mmr_t	reserved_0     : 3;
+		mmr_t	dwcq_af_thresh : 5;
+		mmr_t	reserved_1     : 3;
+		mmr_t	fwcq_ae_level  : 5;
+		mmr_t	reserved_2     : 3;
+		mmr_t	fwcq_af_thresh : 5;
+		mmr_t	reserved_3     : 35;
+	} sh_pi_dpc_queue_config_s;
+} sh_pi_dpc_queue_config_u_t;
+#else
+typedef union sh_pi_dpc_queue_config_u {
+	mmr_t	sh_pi_dpc_queue_config_regval;
+	struct {
+		mmr_t	reserved_3     : 35;
+		mmr_t	fwcq_af_thresh : 5;
+		mmr_t	reserved_2     : 3;
+		mmr_t	fwcq_ae_level  : 5;
+		mmr_t	reserved_1     : 3;
+		mmr_t	dwcq_af_thresh : 5;
+		mmr_t	reserved_0     : 3;
+		mmr_t	dwcq_ae_level  : 5;
+	} sh_pi_dpc_queue_config_s;
+} sh_pi_dpc_queue_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_ERROR_MASK"                      */
+/*                            PI Error Mask                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_mask_u {
+	mmr_t	sh_pi_error_mask_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_error_mask_s;
+} sh_pi_error_mask_u_t;
+#else
+typedef union sh_pi_error_mask_u {
+	mmr_t	sh_pi_error_mask_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_error_mask_s;
+} sh_pi_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_CONFIG"                 */
+/*                    PI Express Reply Configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_express_reply_config_u {
+	mmr_t	sh_pi_express_reply_config_regval;
+	struct {
+		mmr_t	mode        : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_express_reply_config_s;
+} sh_pi_express_reply_config_u_t;
+#else
+typedef union sh_pi_express_reply_config_u {
+	mmr_t	sh_pi_express_reply_config_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	mode        : 3;
+	} sh_pi_express_reply_config_s;
+} sh_pi_express_reply_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_VALUE"                  */
+/*                          FSB Compare Value                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_fsb_compare_value_u {
+	mmr_t	sh_pi_fsb_compare_value_regval;
+	struct {
+		mmr_t	compare_value : 64;
+	} sh_pi_fsb_compare_value_s;
+} sh_pi_fsb_compare_value_u_t;
+#else
+typedef union sh_pi_fsb_compare_value_u {
+	mmr_t	sh_pi_fsb_compare_value_regval;
+	struct {
+		mmr_t	compare_value : 64;
+	} sh_pi_fsb_compare_value_s;
+} sh_pi_fsb_compare_value_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_FSB_COMPARE_MASK"                   */
+/*                           FSB Compare Mask                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_fsb_compare_mask_u {
+	mmr_t	sh_pi_fsb_compare_mask_regval;
+	struct {
+		mmr_t	mask_value  : 64;
+	} sh_pi_fsb_compare_mask_s;
+} sh_pi_fsb_compare_mask_u_t;
+#else
+typedef union sh_pi_fsb_compare_mask_u {
+	mmr_t	sh_pi_fsb_compare_mask_regval;
+	struct {
+		mmr_t	mask_value  : 64;
+	} sh_pi_fsb_compare_mask_s;
+} sh_pi_fsb_compare_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_FSB_ERROR_INJECTION"                 */
+/*                     Inject an Error onto the FSB                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_fsb_error_injection_u {
+	mmr_t	sh_pi_fsb_error_injection_regval;
+	struct {
+		mmr_t	rp_pe_to_fsb     : 1;
+		mmr_t	ap0_pe_to_fsb    : 1;
+		mmr_t	ap1_pe_to_fsb    : 1;
+		mmr_t	rsp_pe_to_fsb    : 1;
+		mmr_t	dw0_ce_to_fsb    : 1;
+		mmr_t	dw0_uce_to_fsb   : 1;
+		mmr_t	dw1_ce_to_fsb    : 1;
+		mmr_t	dw1_uce_to_fsb   : 1;
+		mmr_t	ip0_pe_to_fsb    : 1;
+		mmr_t	ip1_pe_to_fsb    : 1;
+		mmr_t	reserved_0       : 6;
+		mmr_t	rp_pe_from_fsb   : 1;
+		mmr_t	ap0_pe_from_fsb  : 1;
+		mmr_t	ap1_pe_from_fsb  : 1;
+		mmr_t	rsp_pe_from_fsb  : 1;
+		mmr_t	dw0_ce_from_fsb  : 1;
+		mmr_t	dw0_uce_from_fsb : 1;
+		mmr_t	dw1_ce_from_fsb  : 1;
+		mmr_t	dw1_uce_from_fsb : 1;
+		mmr_t	dw2_ce_from_fsb  : 1;
+		mmr_t	dw2_uce_from_fsb : 1;
+		mmr_t	dw3_ce_from_fsb  : 1;
+		mmr_t	dw3_uce_from_fsb : 1;
+		mmr_t	reserved_1       : 4;
+		mmr_t	ioq_overrun      : 1;
+		mmr_t	livelock         : 1;
+		mmr_t	bus_hang         : 1;
+		mmr_t	reserved_2       : 29;
+	} sh_pi_fsb_error_injection_s;
+} sh_pi_fsb_error_injection_u_t;
+#else
+typedef union sh_pi_fsb_error_injection_u {
+	mmr_t	sh_pi_fsb_error_injection_regval;
+	struct {
+		mmr_t	reserved_2       : 29;
+		mmr_t	bus_hang         : 1;
+		mmr_t	livelock         : 1;
+		mmr_t	ioq_overrun      : 1;
+		mmr_t	reserved_1       : 4;
+		mmr_t	dw3_uce_from_fsb : 1;
+		mmr_t	dw3_ce_from_fsb  : 1;
+		mmr_t	dw2_uce_from_fsb : 1;
+		mmr_t	dw2_ce_from_fsb  : 1;
+		mmr_t	dw1_uce_from_fsb : 1;
+		mmr_t	dw1_ce_from_fsb  : 1;
+		mmr_t	dw0_uce_from_fsb : 1;
+		mmr_t	dw0_ce_from_fsb  : 1;
+		mmr_t	rsp_pe_from_fsb  : 1;
+		mmr_t	ap1_pe_from_fsb  : 1;
+		mmr_t	ap0_pe_from_fsb  : 1;
+		mmr_t	rp_pe_from_fsb   : 1;
+		mmr_t	reserved_0       : 6;
+		mmr_t	ip1_pe_to_fsb    : 1;
+		mmr_t	ip0_pe_to_fsb    : 1;
+		mmr_t	dw1_uce_to_fsb   : 1;
+		mmr_t	dw1_ce_to_fsb    : 1;
+		mmr_t	dw0_uce_to_fsb   : 1;
+		mmr_t	dw0_ce_to_fsb    : 1;
+		mmr_t	rsp_pe_to_fsb    : 1;
+		mmr_t	ap1_pe_to_fsb    : 1;
+		mmr_t	ap0_pe_to_fsb    : 1;
+		mmr_t	rp_pe_to_fsb     : 1;
+	} sh_pi_fsb_error_injection_s;
+} sh_pi_fsb_error_injection_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_CONFIG"                */
+/*             MD-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_reply_vc_config_u {
+	mmr_t	sh_pi_md2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_md2pi_reply_vc_config_s;
+} sh_pi_md2pi_reply_vc_config_u_t;
+#else
+typedef union sh_pi_md2pi_reply_vc_config_u {
+	mmr_t	sh_pi_md2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_md2pi_reply_vc_config_s;
+} sh_pi_md2pi_reply_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_CONFIG"               */
+/*            MD-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_request_vc_config_u {
+	mmr_t	sh_pi_md2pi_request_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_md2pi_request_vc_config_s;
+} sh_pi_md2pi_request_vc_config_u_t;
+#else
+typedef union sh_pi_md2pi_request_vc_config_u {
+	mmr_t	sh_pi_md2pi_request_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_md2pi_request_vc_config_s;
+} sh_pi_md2pi_request_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_QUEUE_ERROR_INJECTION"                */
+/*                       PI Queue Error Injection                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_queue_error_injection_u {
+	mmr_t	sh_pi_queue_error_injection_regval;
+	struct {
+		mmr_t	dat_dfr_q      : 1;
+		mmr_t	dxb_wtl_cmnd_q : 1;
+		mmr_t	fsb_wtl_cmnd_q : 1;
+		mmr_t	mdpi_rpy_bfr   : 1;
+		mmr_t	ptc_intr       : 1;
+		mmr_t	rxl_kill_q     : 1;
+		mmr_t	rxl_rdy_q      : 1;
+		mmr_t	xnpi_rpy_bfr   : 1;
+		mmr_t	reserved_0     : 56;
+	} sh_pi_queue_error_injection_s;
+} sh_pi_queue_error_injection_u_t;
+#else
+typedef union sh_pi_queue_error_injection_u {
+	mmr_t	sh_pi_queue_error_injection_regval;
+	struct {
+		mmr_t	reserved_0     : 56;
+		mmr_t	xnpi_rpy_bfr   : 1;
+		mmr_t	rxl_rdy_q      : 1;
+		mmr_t	rxl_kill_q     : 1;
+		mmr_t	ptc_intr       : 1;
+		mmr_t	mdpi_rpy_bfr   : 1;
+		mmr_t	fsb_wtl_cmnd_q : 1;
+		mmr_t	dxb_wtl_cmnd_q : 1;
+		mmr_t	dat_dfr_q      : 1;
+	} sh_pi_queue_error_injection_s;
+} sh_pi_queue_error_injection_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_TEST_POINT_COMPARE"                  */
+/*                        PI Test Point Compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_test_point_compare_u {
+	mmr_t	sh_pi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_mask    : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_pi_test_point_compare_s;
+} sh_pi_test_point_compare_u_t;
+#else
+typedef union sh_pi_test_point_compare_u {
+	mmr_t	sh_pi_test_point_compare_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	compare_mask    : 32;
+	} sh_pi_test_point_compare_s;
+} sh_pi_test_point_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_TEST_POINT_SELECT"                  */
+/*                         PI Test Point Select                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_test_point_select_u {
+	mmr_t	sh_pi_test_point_select_regval;
+	struct {
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_pi_test_point_select_s;
+} sh_pi_test_point_select_u_t;
+#else
+typedef union sh_pi_test_point_select_u {
+	mmr_t	sh_pi_test_point_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	nibble0_chiplet_sel : 3;
+	} sh_pi_test_point_select_s;
+} sh_pi_test_point_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_PI_TEST_POINT_TRIGGER_SELECT"              */
+/*                     PI Test Point Trigger Select                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_test_point_trigger_select_u {
+	mmr_t	sh_pi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	trigger0_chiplet_sel : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_15          : 1;
+	} sh_pi_test_point_trigger_select_s;
+} sh_pi_test_point_trigger_select_u_t;
+#else
+typedef union sh_pi_test_point_trigger_select_u {
+	mmr_t	sh_pi_test_point_trigger_select_regval;
+	struct {
+		mmr_t	reserved_15          : 1;
+		mmr_t	trigger7_nibble_sel  : 3;
+		mmr_t	reserved_14          : 1;
+		mmr_t	trigger7_chiplet_sel : 3;
+		mmr_t	reserved_13          : 1;
+		mmr_t	trigger6_nibble_sel  : 3;
+		mmr_t	reserved_12          : 1;
+		mmr_t	trigger6_chiplet_sel : 3;
+		mmr_t	reserved_11          : 1;
+		mmr_t	trigger5_nibble_sel  : 3;
+		mmr_t	reserved_10          : 1;
+		mmr_t	trigger5_chiplet_sel : 3;
+		mmr_t	reserved_9           : 1;
+		mmr_t	trigger4_nibble_sel  : 3;
+		mmr_t	reserved_8           : 1;
+		mmr_t	trigger4_chiplet_sel : 3;
+		mmr_t	reserved_7           : 1;
+		mmr_t	trigger3_nibble_sel  : 3;
+		mmr_t	reserved_6           : 1;
+		mmr_t	trigger3_chiplet_sel : 3;
+		mmr_t	reserved_5           : 1;
+		mmr_t	trigger2_nibble_sel  : 3;
+		mmr_t	reserved_4           : 1;
+		mmr_t	trigger2_chiplet_sel : 3;
+		mmr_t	reserved_3           : 1;
+		mmr_t	trigger1_nibble_sel  : 3;
+		mmr_t	reserved_2           : 1;
+		mmr_t	trigger1_chiplet_sel : 3;
+		mmr_t	reserved_1           : 1;
+		mmr_t	trigger0_nibble_sel  : 3;
+		mmr_t	reserved_0           : 1;
+		mmr_t	trigger0_chiplet_sel : 3;
+	} sh_pi_test_point_trigger_select_s;
+} sh_pi_test_point_trigger_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_CONFIG"                */
+/*             XN-to-PI Reply Virtual Channel Configuration             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_reply_vc_config_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_xn2pi_reply_vc_config_s;
+} sh_pi_xn2pi_reply_vc_config_u_t;
+#else
+typedef union sh_pi_xn2pi_reply_vc_config_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_xn2pi_reply_vc_config_s;
+} sh_pi_xn2pi_reply_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_CONFIG"               */
+/*            XN-to-PI Request Virtual Channel Configuration            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_request_vc_config_u {
+	mmr_t	sh_pi_xn2pi_request_vc_config_regval;
+	struct {
+		mmr_t	hdr_depth             : 4;
+		mmr_t	data_depth            : 4;
+		mmr_t	max_credits           : 6;
+		mmr_t	reserved_0            : 48;
+		mmr_t	force_credit          : 1;
+		mmr_t	capture_credit_status : 1;
+	} sh_pi_xn2pi_request_vc_config_s;
+} sh_pi_xn2pi_request_vc_config_u_t;
+#else
+typedef union sh_pi_xn2pi_request_vc_config_u {
+	mmr_t	sh_pi_xn2pi_request_vc_config_regval;
+	struct {
+		mmr_t	capture_credit_status : 1;
+		mmr_t	force_credit          : 1;
+		mmr_t	reserved_0            : 48;
+		mmr_t	max_credits           : 6;
+		mmr_t	data_depth            : 4;
+		mmr_t	hdr_depth             : 4;
+	} sh_pi_xn2pi_request_vc_config_s;
+} sh_pi_xn2pi_request_vc_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_AEC_STATUS"                      */
+/*                 PI Adaptive Error Correction Status                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_aec_status_u {
+	mmr_t	sh_pi_aec_status_regval;
+	struct {
+		mmr_t	state       : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_aec_status_s;
+} sh_pi_aec_status_u_t;
+#else
+typedef union sh_pi_aec_status_u {
+	mmr_t	sh_pi_aec_status_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	state       : 3;
+	} sh_pi_aec_status_s;
+} sh_pi_aec_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_AFI_FIRST_ERROR"                   */
+/*                          PI AFI First Error                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_afi_first_error_u {
+	mmr_t	sh_pi_afi_first_error_regval;
+	struct {
+		mmr_t	reserved_0   : 7;
+		mmr_t	fsb_shub_uce : 1;
+		mmr_t	fsb_shub_ce  : 1;
+		mmr_t	reserved_1   : 12;
+		mmr_t	hung_bus     : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	msg_len      : 1;
+		mmr_t	reserved_2   : 29;
+	} sh_pi_afi_first_error_s;
+} sh_pi_afi_first_error_u_t;
+#else
+typedef union sh_pi_afi_first_error_u {
+	mmr_t	sh_pi_afi_first_error_regval;
+	struct {
+		mmr_t	reserved_2   : 29;
+		mmr_t	msg_len      : 1;
+		mmr_t	fsb_tbl_miss : 1;
+		mmr_t	bad_snoop    : 1;
+		mmr_t	livelock     : 1;
+		mmr_t	shub_fsb_ce  : 1;
+		mmr_t	shub_fsb_uce : 1;
+		mmr_t	shub_fsb_dqe : 1;
+		mmr_t	addr_parity  : 1;
+		mmr_t	req_parity   : 1;
+		mmr_t	addr_access  : 1;
+		mmr_t	req_format   : 1;
+		mmr_t	ioq_overrun  : 1;
+		mmr_t	rsp_parity   : 1;
+		mmr_t	hung_bus     : 1;
+		mmr_t	reserved_1   : 12;
+		mmr_t	fsb_shub_ce  : 1;
+		mmr_t	fsb_shub_uce : 1;
+		mmr_t	reserved_0   : 7;
+	} sh_pi_afi_first_error_s;
+} sh_pi_afi_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_CAM_ADDRESS_READ_DATA"                */
+/*                    CRB CAM MMR Address Read Data                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_address_read_data_u {
+	mmr_t	sh_pi_cam_address_read_data_regval;
+	struct {
+		mmr_t	cam_addr     : 48;
+		mmr_t	reserved_0   : 15;
+		mmr_t	cam_addr_val : 1;
+	} sh_pi_cam_address_read_data_s;
+} sh_pi_cam_address_read_data_u_t;
+#else
+typedef union sh_pi_cam_address_read_data_u {
+	mmr_t	sh_pi_cam_address_read_data_regval;
+	struct {
+		mmr_t	cam_addr_val : 1;
+		mmr_t	reserved_0   : 15;
+		mmr_t	cam_addr     : 48;
+	} sh_pi_cam_address_read_data_s;
+} sh_pi_cam_address_read_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_LPRA_READ_DATA"                  */
+/*                      CRB CAM MMR LPRA Read Data                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_lpra_read_data_u {
+	mmr_t	sh_pi_cam_lpra_read_data_regval;
+	struct {
+		mmr_t	cam_lpra    : 64;
+	} sh_pi_cam_lpra_read_data_s;
+} sh_pi_cam_lpra_read_data_u_t;
+#else
+typedef union sh_pi_cam_lpra_read_data_u {
+	mmr_t	sh_pi_cam_lpra_read_data_regval;
+	struct {
+		mmr_t	cam_lpra    : 64;
+	} sh_pi_cam_lpra_read_data_s;
+} sh_pi_cam_lpra_read_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CAM_STATE_READ_DATA"                 */
+/*                     CRB CAM MMR State Read Data                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cam_state_read_data_u {
+	mmr_t	sh_pi_cam_state_read_data_regval;
+	struct {
+		mmr_t	cam_state         : 4;
+		mmr_t	cam_to            : 1;
+		mmr_t	cam_state_rd_pend : 1;
+		mmr_t	reserved_0        : 26;
+		mmr_t	cam_lpra          : 18;
+		mmr_t	reserved_1        : 13;
+		mmr_t	cam_rd_data_val   : 1;
+	} sh_pi_cam_state_read_data_s;
+} sh_pi_cam_state_read_data_u_t;
+#else
+typedef union sh_pi_cam_state_read_data_u {
+	mmr_t	sh_pi_cam_state_read_data_regval;
+	struct {
+		mmr_t	cam_rd_data_val   : 1;
+		mmr_t	reserved_1        : 13;
+		mmr_t	cam_lpra          : 18;
+		mmr_t	reserved_0        : 26;
+		mmr_t	cam_state_rd_pend : 1;
+		mmr_t	cam_to            : 1;
+		mmr_t	cam_state         : 4;
+	} sh_pi_cam_state_read_data_s;
+} sh_pi_cam_state_read_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_1"                  */
+/*                      PI Corrected Error Detail                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_1_u {
+	mmr_t	sh_pi_corrected_detail_1_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_corrected_detail_1_s;
+} sh_pi_corrected_detail_1_u_t;
+#else
+typedef union sh_pi_corrected_detail_1_u {
+	mmr_t	sh_pi_corrected_detail_1_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_corrected_detail_1_s;
+} sh_pi_corrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_2"                  */
+/*                     PI Corrected Error Detail 2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_2_u {
+	mmr_t	sh_pi_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_2_s;
+} sh_pi_corrected_detail_2_u_t;
+#else
+typedef union sh_pi_corrected_detail_2_u {
+	mmr_t	sh_pi_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_2_s;
+} sh_pi_corrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_3"                  */
+/*                     PI Corrected Error Detail 3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_3_u {
+	mmr_t	sh_pi_corrected_detail_3_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_corrected_detail_3_s;
+} sh_pi_corrected_detail_3_u_t;
+#else
+typedef union sh_pi_corrected_detail_3_u {
+	mmr_t	sh_pi_corrected_detail_3_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_corrected_detail_3_s;
+} sh_pi_corrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_PI_CORRECTED_DETAIL_4"                  */
+/*                     PI Corrected Error Detail 4                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_corrected_detail_4_u {
+	mmr_t	sh_pi_corrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_4_s;
+} sh_pi_corrected_detail_4_u_t;
+#else
+typedef union sh_pi_corrected_detail_4_u {
+	mmr_t	sh_pi_corrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_corrected_detail_4_s;
+} sh_pi_corrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_CRBP_FIRST_ERROR"                   */
+/*                         PI CRBP First Error                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_crbp_first_error_u {
+	mmr_t	sh_pi_crbp_first_error_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	reserved_0      : 43;
+	} sh_pi_crbp_first_error_s;
+} sh_pi_crbp_first_error_u_t;
+#else
+typedef union sh_pi_crbp_first_error_u {
+	mmr_t	sh_pi_crbp_first_error_regval;
+	struct {
+		mmr_t	reserved_0      : 43;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_crbp_first_error_s;
+} sh_pi_crbp_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_1"                    */
+/*                          PI Error Detail 1                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_detail_1_u {
+	mmr_t	sh_pi_error_detail_1_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_1_s;
+} sh_pi_error_detail_1_u_t;
+#else
+typedef union sh_pi_error_detail_1_u {
+	mmr_t	sh_pi_error_detail_1_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_1_s;
+} sh_pi_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_DETAIL_2"                    */
+/*                          PI Error Detail 2                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_detail_2_u {
+	mmr_t	sh_pi_error_detail_2_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_2_s;
+} sh_pi_error_detail_2_u_t;
+#else
+typedef union sh_pi_error_detail_2_u {
+	mmr_t	sh_pi_error_detail_2_regval;
+	struct {
+		mmr_t	status      : 64;
+	} sh_pi_error_detail_2_s;
+} sh_pi_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_ERROR_OVERFLOW"                    */
+/*                          PI Error Overflow                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_overflow_u {
+	mmr_t	sh_pi_error_overflow_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_error_overflow_s;
+} sh_pi_error_overflow_u_t;
+#else
+typedef union sh_pi_error_overflow_u {
+	mmr_t	sh_pi_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_error_overflow_s;
+} sh_pi_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_ERROR_SUMMARY"                    */
+/*                           PI Error Summary                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_error_summary_u {
+	mmr_t	sh_pi_error_summary_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_error_summary_s;
+} sh_pi_error_summary_u_t;
+#else
+typedef union sh_pi_error_summary_u {
+	mmr_t	sh_pi_error_summary_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_error_summary_s;
+} sh_pi_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_EXPRESS_REPLY_STATUS"                 */
+/*                       PI Express Reply Status                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_express_reply_status_u {
+	mmr_t	sh_pi_express_reply_status_regval;
+	struct {
+		mmr_t	state       : 3;
+		mmr_t	reserved_0  : 61;
+	} sh_pi_express_reply_status_s;
+} sh_pi_express_reply_status_u_t;
+#else
+typedef union sh_pi_express_reply_status_u {
+	mmr_t	sh_pi_express_reply_status_regval;
+	struct {
+		mmr_t	reserved_0  : 61;
+		mmr_t	state       : 3;
+	} sh_pi_express_reply_status_s;
+} sh_pi_express_reply_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_FIRST_ERROR"                     */
+/*                            PI First Error                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_first_error_u {
+	mmr_t	sh_pi_first_error_regval;
+	struct {
+		mmr_t	fsb_proto_err   : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	msg_length      : 1;
+		mmr_t	reserved_0      : 29;
+	} sh_pi_first_error_s;
+} sh_pi_first_error_u_t;
+#else
+typedef union sh_pi_first_error_u {
+	mmr_t	sh_pi_first_error_regval;
+	struct {
+		mmr_t	reserved_0      : 29;
+		mmr_t	msg_length      : 1;
+		mmr_t	fsb_tbl_miss    : 1;
+		mmr_t	bad_snoop       : 1;
+		mmr_t	livelock        : 1;
+		mmr_t	shub_fsb_ce     : 1;
+		mmr_t	shub_fsb_uce    : 1;
+		mmr_t	shub_fsb_dqe    : 1;
+		mmr_t	addr_parity     : 1;
+		mmr_t	req_parity      : 1;
+		mmr_t	addr_access     : 1;
+		mmr_t	req_format      : 1;
+		mmr_t	ioq_overrun     : 1;
+		mmr_t	rsp_parity      : 1;
+		mmr_t	hung_bus        : 1;
+		mmr_t	xn_rp_crd_oflow : 1;
+		mmr_t	xn_rq_crd_oflow : 1;
+		mmr_t	md_rp_crd_oflow : 1;
+		mmr_t	md_rq_crd_oflow : 1;
+		mmr_t	gfx_int_1       : 1;
+		mmr_t	gfx_int_0       : 1;
+		mmr_t	nack_oflow      : 1;
+		mmr_t	xn_rp_q_oflow   : 1;
+		mmr_t	xn_rq_q_oflow   : 1;
+		mmr_t	md_rp_q_oflow   : 1;
+		mmr_t	md_rq_q_oflow   : 1;
+		mmr_t	msg_color_err   : 1;
+		mmr_t	fsb_shub_ce     : 1;
+		mmr_t	fsb_shub_uce    : 1;
+		mmr_t	pio_to_err      : 1;
+		mmr_t	mem_to_err      : 1;
+		mmr_t	pio_rp_err      : 1;
+		mmr_t	mem_rp_err      : 1;
+		mmr_t	xb_proto_err    : 1;
+		mmr_t	gfx_rp_err      : 1;
+		mmr_t	fsb_proto_err   : 1;
+	} sh_pi_first_error_s;
+} sh_pi_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2MD_REPLY_VC_STATUS"                */
+/*                PI-to-MD Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2md_reply_vc_status_u {
+	mmr_t	sh_pi_pi2md_reply_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2md_reply_vc_status_s;
+} sh_pi_pi2md_reply_vc_status_u_t;
+#else
+typedef union sh_pi_pi2md_reply_vc_status_u {
+	mmr_t	sh_pi_pi2md_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2md_reply_vc_status_s;
+} sh_pi_pi2md_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2MD_REQUEST_VC_STATUS"               */
+/*               PI-to-MD Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2md_request_vc_status_u {
+	mmr_t	sh_pi_pi2md_request_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2md_request_vc_status_s;
+} sh_pi_pi2md_request_vc_status_u_t;
+#else
+typedef union sh_pi_pi2md_request_vc_status_u {
+	mmr_t	sh_pi_pi2md_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2md_request_vc_status_s;
+} sh_pi_pi2md_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_PI2XN_REPLY_VC_STATUS"                */
+/*                PI-to-XN Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2xn_reply_vc_status_u {
+	mmr_t	sh_pi_pi2xn_reply_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2xn_reply_vc_status_s;
+} sh_pi_pi2xn_reply_vc_status_u_t;
+#else
+typedef union sh_pi_pi2xn_reply_vc_status_u {
+	mmr_t	sh_pi_pi2xn_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2xn_reply_vc_status_s;
+} sh_pi_pi2xn_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_PI2XN_REQUEST_VC_STATUS"               */
+/*               PI-to-XN Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_pi2xn_request_vc_status_u {
+	mmr_t	sh_pi_pi2xn_request_vc_status_regval;
+	struct {
+		mmr_t	output_crd_stat : 6;
+		mmr_t	reserved_0      : 58;
+	} sh_pi_pi2xn_request_vc_status_s;
+} sh_pi_pi2xn_request_vc_status_u_t;
+#else
+typedef union sh_pi_pi2xn_request_vc_status_u {
+	mmr_t	sh_pi_pi2xn_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0      : 58;
+		mmr_t	output_crd_stat : 6;
+	} sh_pi_pi2xn_request_vc_status_s;
+} sh_pi_pi2xn_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_1"                 */
+/*                    PI Uncorrected Error Detail 1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_1_u {
+	mmr_t	sh_pi_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_uncorrected_detail_1_s;
+} sh_pi_uncorrected_detail_1_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_1_u {
+	mmr_t	sh_pi_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_uncorrected_detail_1_s;
+} sh_pi_uncorrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_2"                 */
+/*                    PI Uncorrected Error Detail 2                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_2_u {
+	mmr_t	sh_pi_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_2_s;
+} sh_pi_uncorrected_detail_2_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_2_u {
+	mmr_t	sh_pi_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_2_s;
+} sh_pi_uncorrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_3"                 */
+/*                    PI Uncorrected Error Detail 3                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_3_u {
+	mmr_t	sh_pi_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	address     : 48;
+		mmr_t	syndrome    : 8;
+		mmr_t	dep         : 8;
+	} sh_pi_uncorrected_detail_3_s;
+} sh_pi_uncorrected_detail_3_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_3_u {
+	mmr_t	sh_pi_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	dep         : 8;
+		mmr_t	syndrome    : 8;
+		mmr_t	address     : 48;
+	} sh_pi_uncorrected_detail_3_s;
+} sh_pi_uncorrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_UNCORRECTED_DETAIL_4"                 */
+/*                    PI Uncorrected Error Detail 4                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncorrected_detail_4_u {
+	mmr_t	sh_pi_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_4_s;
+} sh_pi_uncorrected_detail_4_u_t;
+#else
+typedef union sh_pi_uncorrected_detail_4_u {
+	mmr_t	sh_pi_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_pi_uncorrected_detail_4_s;
+} sh_pi_uncorrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_MD2PI_REPLY_VC_STATUS"                */
+/*                MD-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_reply_vc_status_u {
+	mmr_t	sh_pi_md2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_md2pi_reply_vc_status_s;
+} sh_pi_md2pi_reply_vc_status_u_t;
+#else
+typedef union sh_pi_md2pi_reply_vc_status_u {
+	mmr_t	sh_pi_md2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_md2pi_reply_vc_status_s;
+} sh_pi_md2pi_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_MD2PI_REQUEST_VC_STATUS"               */
+/*               MD-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md2pi_request_vc_status_u {
+	mmr_t	sh_pi_md2pi_request_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_md2pi_request_vc_status_s;
+} sh_pi_md2pi_request_vc_status_u_t;
+#else
+typedef union sh_pi_md2pi_request_vc_status_u {
+	mmr_t	sh_pi_md2pi_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_md2pi_request_vc_status_s;
+} sh_pi_md2pi_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_PI_XN2PI_REPLY_VC_STATUS"                */
+/*                XN-to-PI Reply Virtual Channel Status                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_reply_vc_status_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_xn2pi_reply_vc_status_s;
+} sh_pi_xn2pi_reply_vc_status_u_t;
+#else
+typedef union sh_pi_xn2pi_reply_vc_status_u {
+	mmr_t	sh_pi_xn2pi_reply_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_xn2pi_reply_vc_status_s;
+} sh_pi_xn2pi_reply_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PI_XN2PI_REQUEST_VC_STATUS"               */
+/*               XN-to-PI Request Virtual Channel Status                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_xn2pi_request_vc_status_u {
+	mmr_t	sh_pi_xn2pi_request_vc_status_regval;
+	struct {
+		mmr_t	input_hdr_crd_stat : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	reserved_0         : 52;
+	} sh_pi_xn2pi_request_vc_status_s;
+} sh_pi_xn2pi_request_vc_status_u_t;
+#else
+typedef union sh_pi_xn2pi_request_vc_status_u {
+	mmr_t	sh_pi_xn2pi_request_vc_status_regval;
+	struct {
+		mmr_t	reserved_0         : 52;
+		mmr_t	input_queue_stat   : 4;
+		mmr_t	input_dat_crd_stat : 4;
+		mmr_t	input_hdr_crd_stat : 4;
+	} sh_pi_xn2pi_request_vc_status_s;
+} sh_pi_xn2pi_request_vc_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNPI_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_sic_flow_u {
+	mmr_t	sh_xnpi_sic_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 5;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_7           : 2;
+		mmr_t	disable_bypass_out   : 1;
+	} sh_xnpi_sic_flow_s;
+} sh_xnpi_sic_flow_u_t;
+#else
+typedef union sh_xnpi_sic_flow_u {
+	mmr_t	sh_xnpi_sic_flow_regval;
+	struct {
+		mmr_t	disable_bypass_out   : 1;
+		mmr_t	reserved_7           : 2;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_withhold   : 5;
+	} sh_xnpi_sic_flow_s;
+} sh_xnpi_sic_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_to_ni0_port_flow_u {
+	mmr_t	sh_xnpi_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnpi_to_ni0_port_flow_s;
+} sh_xnpi_to_ni0_port_flow_u_t;
+#else
+typedef union sh_xnpi_to_ni0_port_flow_u {
+	mmr_t	sh_xnpi_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnpi_to_ni0_port_flow_s;
+} sh_xnpi_to_ni0_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_to_ni1_port_flow_u {
+	mmr_t	sh_xnpi_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnpi_to_ni1_port_flow_s;
+} sh_xnpi_to_ni1_port_flow_u_t;
+#else
+typedef union sh_xnpi_to_ni1_port_flow_u {
+	mmr_t	sh_xnpi_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnpi_to_ni1_port_flow_s;
+} sh_xnpi_to_ni1_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_to_iilb_port_flow_u {
+	mmr_t	sh_xnpi_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnpi_to_iilb_port_flow_s;
+} sh_xnpi_to_iilb_port_flow_u_t;
+#else
+typedef union sh_xnpi_to_iilb_port_flow_u {
+	mmr_t	sh_xnpi_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnpi_to_iilb_port_flow_s;
+} sh_xnpi_to_iilb_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnpi_fr_ni0_port_flow_fifo_s;
+} sh_xnpi_fr_ni0_port_flow_fifo_u_t;
+#else
+typedef union sh_xnpi_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnpi_fr_ni0_port_flow_fifo_s;
+} sh_xnpi_fr_ni0_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNPI_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnpi_fr_ni1_port_flow_fifo_s;
+} sh_xnpi_fr_ni1_port_flow_fifo_u_t;
+#else
+typedef union sh_xnpi_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnpi_fr_ni1_port_flow_fifo_s;
+} sh_xnpi_fr_ni1_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNPI_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnpi_fr_iilb_port_flow_fifo_s;
+} sh_xnpi_fr_iilb_port_flow_fifo_u_t;
+#else
+typedef union sh_xnpi_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnpi_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnpi_fr_iilb_port_flow_fifo_s;
+} sh_xnpi_fr_iilb_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNMD_SIC_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_sic_flow_u {
+	mmr_t	sh_xnmd_sic_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 5;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_7           : 2;
+		mmr_t	disable_bypass_out   : 1;
+	} sh_xnmd_sic_flow_s;
+} sh_xnmd_sic_flow_u_t;
+#else
+typedef union sh_xnmd_sic_flow_u {
+	mmr_t	sh_xnmd_sic_flow_regval;
+	struct {
+		mmr_t	disable_bypass_out   : 1;
+		mmr_t	reserved_7           : 2;
+		mmr_t	credit_vc2_cap       : 5;
+		mmr_t	reserved_6           : 3;
+		mmr_t	credit_vc2_dyn       : 5;
+		mmr_t	reserved_5           : 3;
+		mmr_t	credit_vc2_test      : 5;
+		mmr_t	reserved_4           : 3;
+		mmr_t	credit_vc0_cap       : 5;
+		mmr_t	reserved_3           : 3;
+		mmr_t	credit_vc0_dyn       : 5;
+		mmr_t	reserved_2           : 3;
+		mmr_t	credit_vc0_test      : 5;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 2;
+		mmr_t	debit_vc2_withhold   : 5;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 2;
+		mmr_t	debit_vc0_withhold   : 5;
+	} sh_xnmd_sic_flow_s;
+} sh_xnmd_sic_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI0_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_to_ni0_port_flow_u {
+	mmr_t	sh_xnmd_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnmd_to_ni0_port_flow_s;
+} sh_xnmd_to_ni0_port_flow_u_t;
+#else
+typedef union sh_xnmd_to_ni0_port_flow_u {
+	mmr_t	sh_xnmd_to_ni0_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnmd_to_ni0_port_flow_s;
+} sh_xnmd_to_ni0_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_NI1_PORT_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_to_ni1_port_flow_u {
+	mmr_t	sh_xnmd_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnmd_to_ni1_port_flow_s;
+} sh_xnmd_to_ni1_port_flow_u_t;
+#else
+typedef union sh_xnmd_to_ni1_port_flow_u {
+	mmr_t	sh_xnmd_to_ni1_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnmd_to_ni1_port_flow_s;
+} sh_xnmd_to_ni1_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_TO_IILB_PORT_FLOW"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_to_iilb_port_flow_u {
+	mmr_t	sh_xnmd_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_2           : 8;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_6           : 2;
+	} sh_xnmd_to_iilb_port_flow_s;
+} sh_xnmd_to_iilb_port_flow_u_t;
+#else
+typedef union sh_xnmd_to_iilb_port_flow_u {
+	mmr_t	sh_xnmd_to_iilb_port_flow_regval;
+	struct {
+		mmr_t	reserved_6           : 2;
+		mmr_t	credit_vc2_cap       : 6;
+		mmr_t	reserved_5           : 2;
+		mmr_t	credit_vc2_dyn       : 6;
+		mmr_t	reserved_4           : 10;
+		mmr_t	credit_vc0_cap       : 6;
+		mmr_t	reserved_3           : 2;
+		mmr_t	credit_vc0_dyn       : 6;
+		mmr_t	reserved_2           : 8;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnmd_to_iilb_port_flow_s;
+} sh_xnmd_to_iilb_port_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI0_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnmd_fr_ni0_port_flow_fifo_s;
+} sh_xnmd_fr_ni0_port_flow_fifo_u_t;
+#else
+typedef union sh_xnmd_fr_ni0_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni0_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnmd_fr_ni0_port_flow_fifo_s;
+} sh_xnmd_fr_ni0_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XNMD_FR_NI1_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnmd_fr_ni1_port_flow_fifo_s;
+} sh_xnmd_fr_ni1_port_flow_fifo_u_t;
+#else
+typedef union sh_xnmd_fr_ni1_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_ni1_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnmd_fr_ni1_port_flow_fifo_s;
+} sh_xnmd_fr_ni1_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNMD_FR_IILB_PORT_FLOW_FIFO"               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	entry_vc0_dyn  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_5     : 19;
+	} sh_xnmd_fr_iilb_port_flow_fifo_s;
+} sh_xnmd_fr_iilb_port_flow_fifo_u_t;
+#else
+typedef union sh_xnmd_fr_iilb_port_flow_fifo_u {
+	mmr_t	sh_xnmd_fr_iilb_port_flow_fifo_regval;
+	struct {
+		mmr_t	reserved_5     : 19;
+		mmr_t	entry_vc2_test : 5;
+		mmr_t	reserved_4     : 3;
+		mmr_t	entry_vc0_test : 5;
+		mmr_t	reserved_3     : 2;
+		mmr_t	entry_vc2_cap  : 6;
+		mmr_t	reserved_2     : 2;
+		mmr_t	entry_vc2_dyn  : 6;
+		mmr_t	reserved_1     : 2;
+		mmr_t	entry_vc0_cap  : 6;
+		mmr_t	reserved_0     : 2;
+		mmr_t	entry_vc0_dyn  : 6;
+	} sh_xnmd_fr_iilb_port_flow_fifo_s;
+} sh_xnmd_fr_iilb_port_flow_fifo_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNII_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnii_intra_flow_u {
+	mmr_t	sh_xnii_intra_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_7           : 1;
+	} sh_xnii_intra_flow_s;
+} sh_xnii_intra_flow_u_t;
+#else
+typedef union sh_xnii_intra_flow_u {
+	mmr_t	sh_xnii_intra_flow_regval;
+	struct {
+		mmr_t	reserved_7           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnii_intra_flow_s;
+} sh_xnii_intra_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNLB_INTRA_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnlb_intra_flow_u {
+	mmr_t	sh_xnlb_intra_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	disable_bypass_in    : 1;
+	} sh_xnlb_intra_flow_s;
+} sh_xnlb_intra_flow_u_t;
+#else
+typedef union sh_xnlb_intra_flow_u {
+	mmr_t	sh_xnlb_intra_flow_regval;
+	struct {
+		mmr_t	disable_bypass_in    : 1;
+		mmr_t	credit_vc2_cap       : 7;
+		mmr_t	reserved_6           : 1;
+		mmr_t	credit_vc2_dyn       : 7;
+		mmr_t	reserved_5           : 1;
+		mmr_t	credit_vc2_test      : 7;
+		mmr_t	reserved_4           : 1;
+		mmr_t	credit_vc0_cap       : 7;
+		mmr_t	reserved_3           : 1;
+		mmr_t	credit_vc0_dyn       : 7;
+		mmr_t	reserved_2           : 1;
+		mmr_t	credit_vc0_test      : 7;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnlb_intra_flow_s;
+} sh_xnlb_intra_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI0_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_ni0_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni0_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_ni0_intra_flow_debit_s;
+} sh_xniilb_to_ni0_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_ni0_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni0_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_ni0_intra_flow_debit_s;
+} sh_xniilb_to_ni0_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_NI1_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_ni1_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni1_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_ni1_intra_flow_debit_s;
+} sh_xniilb_to_ni1_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_ni1_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_ni1_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_ni1_intra_flow_debit_s;
+} sh_xniilb_to_ni1_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_md_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_md_intra_flow_debit_s;
+} sh_xniilb_to_md_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_md_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_md_intra_flow_debit_s;
+} sh_xniilb_to_md_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_iilb_intra_flow_debit_s;
+} sh_xniilb_to_iilb_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_iilb_intra_flow_debit_s;
+} sh_xniilb_to_iilb_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xniilb_to_pi_intra_flow_debit_s;
+} sh_xniilb_to_pi_intra_flow_debit_u_t;
+#else
+typedef union sh_xniilb_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xniilb_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xniilb_to_pi_intra_flow_debit_s;
+} sh_xniilb_to_pi_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI0_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_ni0_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni0_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_ni0_intra_flow_credit_s;
+} sh_xniilb_fr_ni0_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_ni0_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni0_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_ni0_intra_flow_credit_s;
+} sh_xniilb_fr_ni0_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_NI1_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_ni1_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni1_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_ni1_intra_flow_credit_s;
+} sh_xniilb_fr_ni1_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_ni1_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_ni1_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_ni1_intra_flow_credit_s;
+} sh_xniilb_fr_ni1_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_MD_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_md_intra_flow_credit_s;
+} sh_xniilb_fr_md_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_md_intra_flow_credit_s;
+} sh_xniilb_fr_md_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNIILB_FR_IILB_INTRA_FLOW_CREDIT"            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_iilb_intra_flow_credit_s;
+} sh_xniilb_fr_iilb_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_iilb_intra_flow_credit_s;
+} sh_xniilb_fr_iilb_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNIILB_FR_PI_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xniilb_fr_pi_intra_flow_credit_s;
+} sh_xniilb_fr_pi_intra_flow_credit_u_t;
+#else
+typedef union sh_xniilb_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xniilb_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xniilb_fr_pi_intra_flow_credit_s;
+} sh_xniilb_fr_pi_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni0_to_pi_intra_flow_debit_s;
+} sh_xnni0_to_pi_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni0_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni0_to_pi_intra_flow_debit_s;
+} sh_xnni0_to_pi_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI0_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni0_to_md_intra_flow_debit_s;
+} sh_xnni0_to_md_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni0_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni0_to_md_intra_flow_debit_s;
+} sh_xnni0_to_md_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni0_to_iilb_intra_flow_debit_s;
+} sh_xnni0_to_iilb_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni0_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni0_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni0_to_iilb_intra_flow_debit_s;
+} sh_xnni0_to_iilb_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni0_fr_pi_intra_flow_credit_s;
+} sh_xnni0_fr_pi_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni0_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni0_fr_pi_intra_flow_credit_s;
+} sh_xnni0_fr_pi_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI0_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni0_fr_md_intra_flow_credit_s;
+} sh_xnni0_fr_md_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni0_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni0_fr_md_intra_flow_credit_s;
+} sh_xnni0_fr_md_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNNI0_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni0_fr_iilb_intra_flow_credit_s;
+} sh_xnni0_fr_iilb_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni0_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni0_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni0_fr_iilb_intra_flow_credit_s;
+} sh_xnni0_fr_iilb_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_0_intrani_flow_u {
+	mmr_t	sh_xnni0_0_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_0_intrani_flow_s;
+} sh_xnni0_0_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_0_intrani_flow_u {
+	mmr_t	sh_xnni0_0_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni0_0_intrani_flow_s;
+} sh_xnni0_0_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_1_intrani_flow_u {
+	mmr_t	sh_xnni0_1_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_1_intrani_flow_s;
+} sh_xnni0_1_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_1_intrani_flow_u {
+	mmr_t	sh_xnni0_1_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni0_1_intrani_flow_s;
+} sh_xnni0_1_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_2_intrani_flow_u {
+	mmr_t	sh_xnni0_2_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_2_intrani_flow_s;
+} sh_xnni0_2_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_2_intrani_flow_u {
+	mmr_t	sh_xnni0_2_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni0_2_intrani_flow_s;
+} sh_xnni0_2_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_3_intrani_flow_u {
+	mmr_t	sh_xnni0_3_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni0_3_intrani_flow_s;
+} sh_xnni0_3_intrani_flow_u_t;
+#else
+typedef union sh_xnni0_3_intrani_flow_u {
+	mmr_t	sh_xnni0_3_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni0_3_intrani_flow_s;
+} sh_xnni0_3_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI0_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_vcswitch_flow_u {
+	mmr_t	sh_xnni0_vcswitch_flow_regval;
+	struct {
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	reserved_4                : 29;
+	} sh_xnni0_vcswitch_flow_s;
+} sh_xnni0_vcswitch_flow_u_t;
+#else
+typedef union sh_xnni0_vcswitch_flow_u {
+	mmr_t	sh_xnni0_vcswitch_flow_regval;
+	struct {
+		mmr_t	reserved_4                : 29;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+	} sh_xnni0_vcswitch_flow_s;
+} sh_xnni0_vcswitch_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_TIMER_REG"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_timer_reg_u {
+	mmr_t	sh_xnni0_timer_reg_regval;
+	struct {
+		mmr_t	timeout_reg     : 24;
+		mmr_t	reserved_0      : 8;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_1      : 31;
+	} sh_xnni0_timer_reg_s;
+} sh_xnni0_timer_reg_u_t;
+#else
+typedef union sh_xnni0_timer_reg_u {
+	mmr_t	sh_xnni0_timer_reg_regval;
+	struct {
+		mmr_t	reserved_1      : 31;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_0      : 8;
+		mmr_t	timeout_reg     : 24;
+	} sh_xnni0_timer_reg_s;
+} sh_xnni0_timer_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fifo02_flow_u {
+	mmr_t	sh_xnni0_fifo02_flow_regval;
+	struct {
+		mmr_t	count_vc0_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni0_fifo02_flow_s;
+} sh_xnni0_fifo02_flow_u_t;
+#else
+typedef union sh_xnni0_fifo02_flow_u {
+	mmr_t	sh_xnni0_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_limit : 4;
+	} sh_xnni0_fifo02_flow_s;
+} sh_xnni0_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI0_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_fifo13_flow_u {
+	mmr_t	sh_xnni0_fifo13_flow_regval;
+	struct {
+		mmr_t	count_vc1_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni0_fifo13_flow_s;
+} sh_xnni0_fifo13_flow_u_t;
+#else
+typedef union sh_xnni0_fifo13_flow_u {
+	mmr_t	sh_xnni0_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_limit : 4;
+	} sh_xnni0_fifo13_flow_s;
+} sh_xnni0_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI0_NI_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_ni_flow_u {
+	mmr_t	sh_xnni0_ni_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni0_ni_flow_s;
+} sh_xnni0_ni_flow_u_t;
+#else
+typedef union sh_xnni0_ni_flow_u {
+	mmr_t	sh_xnni0_ni_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni0_ni_flow_s;
+} sh_xnni0_ni_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_dead_flow_u {
+	mmr_t	sh_xnni0_dead_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni0_dead_flow_s;
+} sh_xnni0_dead_flow_u_t;
+#else
+typedef union sh_xnni0_dead_flow_u {
+	mmr_t	sh_xnni0_dead_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni0_dead_flow_s;
+} sh_xnni0_dead_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI0_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni0_inject_age_u {
+	mmr_t	sh_xnni0_inject_age_regval;
+	struct {
+		mmr_t	request_inject : 8;
+		mmr_t	reply_inject   : 8;
+		mmr_t	reserved_0     : 48;
+	} sh_xnni0_inject_age_s;
+} sh_xnni0_inject_age_u_t;
+#else
+typedef union sh_xnni0_inject_age_u {
+	mmr_t	sh_xnni0_inject_age_regval;
+	struct {
+		mmr_t	reserved_0     : 48;
+		mmr_t	reply_inject   : 8;
+		mmr_t	request_inject : 8;
+	} sh_xnni0_inject_age_s;
+} sh_xnni0_inject_age_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_PI_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni1_to_pi_intra_flow_debit_s;
+} sh_xnni1_to_pi_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni1_to_pi_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_pi_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni1_to_pi_intra_flow_debit_s;
+} sh_xnni1_to_pi_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_XNNI1_TO_MD_INTRA_FLOW_DEBIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni1_to_md_intra_flow_debit_s;
+} sh_xnni1_to_md_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni1_to_md_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_md_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni1_to_md_intra_flow_debit_s;
+} sh_xnni1_to_md_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_TO_IILB_INTRA_FLOW_DEBIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	vc0_withhold   : 6;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_6     : 1;
+	} sh_xnni1_to_iilb_intra_flow_debit_s;
+} sh_xnni1_to_iilb_intra_flow_debit_u_t;
+#else
+typedef union sh_xnni1_to_iilb_intra_flow_debit_u {
+	mmr_t	sh_xnni1_to_iilb_intra_flow_debit_regval;
+	struct {
+		mmr_t	reserved_6     : 1;
+		mmr_t	vc2_cap        : 7;
+		mmr_t	reserved_5     : 1;
+		mmr_t	vc2_dyn        : 7;
+		mmr_t	reserved_4     : 9;
+		mmr_t	vc0_cap        : 7;
+		mmr_t	reserved_3     : 1;
+		mmr_t	vc0_dyn        : 7;
+		mmr_t	reserved_2     : 8;
+		mmr_t	vc2_force_cred : 1;
+		mmr_t	reserved_1     : 1;
+		mmr_t	vc2_withhold   : 6;
+		mmr_t	vc0_force_cred : 1;
+		mmr_t	reserved_0     : 1;
+		mmr_t	vc0_withhold   : 6;
+	} sh_xnni1_to_iilb_intra_flow_debit_s;
+} sh_xnni1_to_iilb_intra_flow_debit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_PI_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni1_fr_pi_intra_flow_credit_s;
+} sh_xnni1_fr_pi_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni1_fr_pi_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_pi_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni1_fr_pi_intra_flow_credit_s;
+} sh_xnni1_fr_pi_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_XNNI1_FR_MD_INTRA_FLOW_CREDIT"              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni1_fr_md_intra_flow_credit_s;
+} sh_xnni1_fr_md_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni1_fr_md_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_md_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni1_fr_md_intra_flow_credit_s;
+} sh_xnni1_fr_md_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*            Register "SH_XNNI1_FR_IILB_INTRA_FLOW_CREDIT"             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	vc0_test    : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_5  : 17;
+	} sh_xnni1_fr_iilb_intra_flow_credit_s;
+} sh_xnni1_fr_iilb_intra_flow_credit_u_t;
+#else
+typedef union sh_xnni1_fr_iilb_intra_flow_credit_u {
+	mmr_t	sh_xnni1_fr_iilb_intra_flow_credit_regval;
+	struct {
+		mmr_t	reserved_5  : 17;
+		mmr_t	vc2_cap     : 7;
+		mmr_t	reserved_4  : 1;
+		mmr_t	vc2_dyn     : 7;
+		mmr_t	reserved_3  : 1;
+		mmr_t	vc2_test    : 7;
+		mmr_t	reserved_2  : 1;
+		mmr_t	vc0_cap     : 7;
+		mmr_t	reserved_1  : 1;
+		mmr_t	vc0_dyn     : 7;
+		mmr_t	reserved_0  : 1;
+		mmr_t	vc0_test    : 7;
+	} sh_xnni1_fr_iilb_intra_flow_credit_s;
+} sh_xnni1_fr_iilb_intra_flow_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_0_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_0_intrani_flow_u {
+	mmr_t	sh_xnni1_0_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc0_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_0_intrani_flow_s;
+} sh_xnni1_0_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_0_intrani_flow_u {
+	mmr_t	sh_xnni1_0_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc0_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc0_withhold   : 6;
+	} sh_xnni1_0_intrani_flow_s;
+} sh_xnni1_0_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_1_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_1_intrani_flow_u {
+	mmr_t	sh_xnni1_1_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc1_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_1_intrani_flow_s;
+} sh_xnni1_1_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_1_intrani_flow_u {
+	mmr_t	sh_xnni1_1_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc1_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc1_withhold   : 6;
+	} sh_xnni1_1_intrani_flow_s;
+} sh_xnni1_1_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_2_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_2_intrani_flow_u {
+	mmr_t	sh_xnni1_2_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc2_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_2_intrani_flow_s;
+} sh_xnni1_2_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_2_intrani_flow_u {
+	mmr_t	sh_xnni1_2_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc2_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc2_withhold   : 6;
+	} sh_xnni1_2_intrani_flow_s;
+} sh_xnni1_2_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_3_INTRANI_FLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_3_intrani_flow_u {
+	mmr_t	sh_xnni1_3_intrani_flow_regval;
+	struct {
+		mmr_t	debit_vc3_withhold   : 6;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_1           : 56;
+	} sh_xnni1_3_intrani_flow_s;
+} sh_xnni1_3_intrani_flow_u_t;
+#else
+typedef union sh_xnni1_3_intrani_flow_u {
+	mmr_t	sh_xnni1_3_intrani_flow_regval;
+	struct {
+		mmr_t	reserved_1           : 56;
+		mmr_t	debit_vc3_force_cred : 1;
+		mmr_t	reserved_0           : 1;
+		mmr_t	debit_vc3_withhold   : 6;
+	} sh_xnni1_3_intrani_flow_s;
+} sh_xnni1_3_intrani_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNNI1_VCSWITCH_FLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_vcswitch_flow_u {
+	mmr_t	sh_xnni1_vcswitch_flow_regval;
+	struct {
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	reserved_4                : 29;
+	} sh_xnni1_vcswitch_flow_s;
+} sh_xnni1_vcswitch_flow_u_t;
+#else
+typedef union sh_xnni1_vcswitch_flow_u {
+	mmr_t	sh_xnni1_vcswitch_flow_regval;
+	struct {
+		mmr_t	reserved_4                : 29;
+		mmr_t	async_fifoes              : 1;
+		mmr_t	disable_sync_bypass_out   : 1;
+		mmr_t	disable_sync_bypass_in    : 1;
+		mmr_t	reserved_3                : 7;
+		mmr_t	iilb_vcfifo_switch        : 1;
+		mmr_t	reserved_2                : 7;
+		mmr_t	md_vcfifo_switch          : 1;
+		mmr_t	reserved_1                : 7;
+		mmr_t	pi_vcfifo_switch          : 1;
+		mmr_t	reserved_0                : 7;
+		mmr_t	ni_vcfifo_dateline_switch : 1;
+	} sh_xnni1_vcswitch_flow_s;
+} sh_xnni1_vcswitch_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_TIMER_REG"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_timer_reg_u {
+	mmr_t	sh_xnni1_timer_reg_regval;
+	struct {
+		mmr_t	timeout_reg     : 24;
+		mmr_t	reserved_0      : 8;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_1      : 31;
+	} sh_xnni1_timer_reg_s;
+} sh_xnni1_timer_reg_u_t;
+#else
+typedef union sh_xnni1_timer_reg_u {
+	mmr_t	sh_xnni1_timer_reg_regval;
+	struct {
+		mmr_t	reserved_1      : 31;
+		mmr_t	linkcleanup_reg : 1;
+		mmr_t	reserved_0      : 8;
+		mmr_t	timeout_reg     : 24;
+	} sh_xnni1_timer_reg_s;
+} sh_xnni1_timer_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO02_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fifo02_flow_u {
+	mmr_t	sh_xnni1_fifo02_flow_regval;
+	struct {
+		mmr_t	count_vc0_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni1_fifo02_flow_s;
+} sh_xnni1_fifo02_flow_u_t;
+#else
+typedef union sh_xnni1_fifo02_flow_u {
+	mmr_t	sh_xnni1_fifo02_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc2_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc2_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc2_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc0_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc0_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc0_limit : 4;
+	} sh_xnni1_fifo02_flow_s;
+} sh_xnni1_fifo02_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNNI1_FIFO13_FLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_fifo13_flow_u {
+	mmr_t	sh_xnni1_fifo13_flow_regval;
+	struct {
+		mmr_t	count_vc1_limit : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_5      : 20;
+	} sh_xnni1_fifo13_flow_s;
+} sh_xnni1_fifo13_flow_u_t;
+#else
+typedef union sh_xnni1_fifo13_flow_u {
+	mmr_t	sh_xnni1_fifo13_flow_regval;
+	struct {
+		mmr_t	reserved_5      : 20;
+		mmr_t	count_vc3_cap   : 4;
+		mmr_t	reserved_4      : 4;
+		mmr_t	count_vc3_dyn   : 4;
+		mmr_t	reserved_3      : 4;
+		mmr_t	count_vc3_limit : 4;
+		mmr_t	reserved_2      : 4;
+		mmr_t	count_vc1_cap   : 4;
+		mmr_t	reserved_1      : 4;
+		mmr_t	count_vc1_dyn   : 4;
+		mmr_t	reserved_0      : 4;
+		mmr_t	count_vc1_limit : 4;
+	} sh_xnni1_fifo13_flow_s;
+} sh_xnni1_fifo13_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XNNI1_NI_FLOW"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_ni_flow_u {
+	mmr_t	sh_xnni1_ni_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni1_ni_flow_s;
+} sh_xnni1_ni_flow_u_t;
+#else
+typedef union sh_xnni1_ni_flow_u {
+	mmr_t	sh_xnni1_ni_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni1_ni_flow_s;
+} sh_xnni1_ni_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_DEAD_FLOW"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_dead_flow_u {
+	mmr_t	sh_xnni1_dead_flow_regval;
+	struct {
+		mmr_t	vc0_limit   : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	vc3_cap     : 4;
+	} sh_xnni1_dead_flow_s;
+} sh_xnni1_dead_flow_u_t;
+#else
+typedef union sh_xnni1_dead_flow_u {
+	mmr_t	sh_xnni1_dead_flow_regval;
+	struct {
+		mmr_t	vc3_cap     : 4;
+		mmr_t	vc3_dyn     : 4;
+		mmr_t	reserved_3  : 4;
+		mmr_t	vc3_limit   : 4;
+		mmr_t	vc2_cap     : 4;
+		mmr_t	vc2_dyn     : 4;
+		mmr_t	reserved_2  : 4;
+		mmr_t	vc2_limit   : 4;
+		mmr_t	vc1_cap     : 4;
+		mmr_t	vc1_dyn     : 4;
+		mmr_t	reserved_1  : 4;
+		mmr_t	vc1_limit   : 4;
+		mmr_t	vc0_cap     : 4;
+		mmr_t	vc0_dyn     : 4;
+		mmr_t	reserved_0  : 4;
+		mmr_t	vc0_limit   : 4;
+	} sh_xnni1_dead_flow_s;
+} sh_xnni1_dead_flow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNNI1_INJECT_AGE"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnni1_inject_age_u {
+	mmr_t	sh_xnni1_inject_age_regval;
+	struct {
+		mmr_t	request_inject : 8;
+		mmr_t	reply_inject   : 8;
+		mmr_t	reserved_0     : 48;
+	} sh_xnni1_inject_age_s;
+} sh_xnni1_inject_age_u_t;
+#else
+typedef union sh_xnni1_inject_age_u {
+	mmr_t	sh_xnni1_inject_age_regval;
+	struct {
+		mmr_t	reserved_0     : 48;
+		mmr_t	reply_inject   : 8;
+		mmr_t	request_inject : 8;
+	} sh_xnni1_inject_age_s;
+} sh_xnni1_inject_age_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_XN_DEBUG_SEL"                      */
+/*                         XN Debug Port Select                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_debug_sel_u {
+	mmr_t	sh_xn_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_rlm_sel    : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_rlm_sel    : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_rlm_sel    : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_rlm_sel    : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_rlm_sel    : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_rlm_sel    : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_rlm_sel    : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_rlm_sel    : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	trigger_enable     : 1;
+	} sh_xn_debug_sel_s;
+} sh_xn_debug_sel_u_t;
+#else
+typedef union sh_xn_debug_sel_u {
+	mmr_t	sh_xn_debug_sel_regval;
+	struct {
+		mmr_t	trigger_enable     : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_rlm_sel    : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_rlm_sel    : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_rlm_sel    : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_rlm_sel    : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_rlm_sel    : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_rlm_sel    : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_rlm_sel    : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_rlm_sel    : 3;
+	} sh_xn_debug_sel_s;
+} sh_xn_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_DEBUG_TRIG_SEL"                    */
+/*                       XN Debug trigger Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_debug_trig_sel_u {
+	mmr_t	sh_xn_debug_trig_sel_regval;
+	struct {
+		mmr_t	trigger0_rlm_sel    : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	trigger0_nibble_sel : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	trigger1_rlm_sel    : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	trigger1_nibble_sel : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	trigger2_rlm_sel    : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	trigger2_nibble_sel : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	trigger3_rlm_sel    : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	trigger3_nibble_sel : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	trigger4_rlm_sel    : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	trigger4_nibble_sel : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	trigger5_rlm_sel    : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	trigger5_nibble_sel : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	trigger6_rlm_sel    : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	trigger6_nibble_sel : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	trigger7_rlm_sel    : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	trigger7_nibble_sel : 3;
+		mmr_t	reserved_15         : 1;
+	} sh_xn_debug_trig_sel_s;
+} sh_xn_debug_trig_sel_u_t;
+#else
+typedef union sh_xn_debug_trig_sel_u {
+	mmr_t	sh_xn_debug_trig_sel_regval;
+	struct {
+		mmr_t	reserved_15         : 1;
+		mmr_t	trigger7_nibble_sel : 3;
+		mmr_t	reserved_14         : 1;
+		mmr_t	trigger7_rlm_sel    : 3;
+		mmr_t	reserved_13         : 1;
+		mmr_t	trigger6_nibble_sel : 3;
+		mmr_t	reserved_12         : 1;
+		mmr_t	trigger6_rlm_sel    : 3;
+		mmr_t	reserved_11         : 1;
+		mmr_t	trigger5_nibble_sel : 3;
+		mmr_t	reserved_10         : 1;
+		mmr_t	trigger5_rlm_sel    : 3;
+		mmr_t	reserved_9          : 1;
+		mmr_t	trigger4_nibble_sel : 3;
+		mmr_t	reserved_8          : 1;
+		mmr_t	trigger4_rlm_sel    : 3;
+		mmr_t	reserved_7          : 1;
+		mmr_t	trigger3_nibble_sel : 3;
+		mmr_t	reserved_6          : 1;
+		mmr_t	trigger3_rlm_sel    : 3;
+		mmr_t	reserved_5          : 1;
+		mmr_t	trigger2_nibble_sel : 3;
+		mmr_t	reserved_4          : 1;
+		mmr_t	trigger2_rlm_sel    : 3;
+		mmr_t	reserved_3          : 1;
+		mmr_t	trigger1_nibble_sel : 3;
+		mmr_t	reserved_2          : 1;
+		mmr_t	trigger1_rlm_sel    : 3;
+		mmr_t	reserved_1          : 1;
+		mmr_t	trigger0_nibble_sel : 3;
+		mmr_t	reserved_0          : 1;
+		mmr_t	trigger0_rlm_sel    : 3;
+	} sh_xn_debug_trig_sel_s;
+} sh_xn_debug_trig_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_TRIGGER_COMPARE"                   */
+/*                           XN Debug Compare                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_trigger_compare_u {
+	mmr_t	sh_xn_trigger_compare_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_xn_trigger_compare_s;
+} sh_xn_trigger_compare_u_t;
+#else
+typedef union sh_xn_trigger_compare_u {
+	mmr_t	sh_xn_trigger_compare_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	mask        : 32;
+	} sh_xn_trigger_compare_s;
+} sh_xn_trigger_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_TRIGGER_DATA"                     */
+/*                        XN Debug Compare Data                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_trigger_data_u {
+	mmr_t	sh_xn_trigger_data_regval;
+	struct {
+		mmr_t	compare_pattern : 32;
+		mmr_t	reserved_0      : 32;
+	} sh_xn_trigger_data_s;
+} sh_xn_trigger_data_u_t;
+#else
+typedef union sh_xn_trigger_data_u {
+	mmr_t	sh_xn_trigger_data_regval;
+	struct {
+		mmr_t	reserved_0      : 32;
+		mmr_t	compare_pattern : 32;
+	} sh_xn_trigger_data_s;
+} sh_xn_trigger_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_IILB_DEBUG_SEL"                    */
+/*                      XN IILB Debug Port Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_debug_sel_u {
+	mmr_t	sh_xn_iilb_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_iilb_debug_sel_s;
+} sh_xn_iilb_debug_sel_u_t;
+#else
+typedef union sh_xn_iilb_debug_sel_u {
+	mmr_t	sh_xn_iilb_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_iilb_debug_sel_s;
+} sh_xn_iilb_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_PI_DEBUG_SEL"                     */
+/*                       XN PI Debug Port Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_debug_sel_u {
+	mmr_t	sh_xn_pi_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_pi_debug_sel_s;
+} sh_xn_pi_debug_sel_u_t;
+#else
+typedef union sh_xn_pi_debug_sel_u {
+	mmr_t	sh_xn_pi_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_pi_debug_sel_s;
+} sh_xn_pi_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_DEBUG_SEL"                     */
+/*                       XN MD Debug Port Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_debug_sel_u {
+	mmr_t	sh_xn_md_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_md_debug_sel_s;
+} sh_xn_md_debug_sel_u_t;
+#else
+typedef union sh_xn_md_debug_sel_u {
+	mmr_t	sh_xn_md_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_md_debug_sel_s;
+} sh_xn_md_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI0_DEBUG_SEL"                    */
+/*                       XN NI0 Debug Port Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_debug_sel_u {
+	mmr_t	sh_xn_ni0_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_ni0_debug_sel_s;
+} sh_xn_ni0_debug_sel_u_t;
+#else
+typedef union sh_xn_ni0_debug_sel_u {
+	mmr_t	sh_xn_ni0_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_ni0_debug_sel_s;
+} sh_xn_ni0_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_NI1_DEBUG_SEL"                    */
+/*                       XN NI1 Debug Port Select                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_debug_sel_u {
+	mmr_t	sh_xn_ni1_debug_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_xn_ni1_debug_sel_s;
+} sh_xn_ni1_debug_sel_u_t;
+#else
+typedef union sh_xn_ni1_debug_sel_u {
+	mmr_t	sh_xn_ni1_debug_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_xn_ni1_debug_sel_s;
+} sh_xn_ni1_debug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA0"                */
+/*                 IILB compare LB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data0_s;
+} sh_xn_iilb_lb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data0_s;
+} sh_xn_iilb_lb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_LB_CMP_EXP_DATA1"                */
+/*                 IILB compare LB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data1_s;
+} sh_xn_iilb_lb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_lb_cmp_exp_data1_s;
+} sh_xn_iilb_lb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE0"                 */
+/*                    IILB compare LB input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable0_s;
+} sh_xn_iilb_lb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable0_s;
+} sh_xn_iilb_lb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_LB_CMP_ENABLE1"                 */
+/*                    IILB compare LB input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_lb_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable1_s;
+} sh_xn_iilb_lb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_lb_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_lb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_lb_cmp_enable1_s;
+} sh_xn_iilb_lb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA0"                */
+/*                 IILB compare II input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data0_s;
+} sh_xn_iilb_ii_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data0_s;
+} sh_xn_iilb_ii_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_II_CMP_EXP_DATA1"                */
+/*                 IILB compare II input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data1_s;
+} sh_xn_iilb_ii_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ii_cmp_exp_data1_s;
+} sh_xn_iilb_ii_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE0"                 */
+/*                    IILB compare II input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable0_s;
+} sh_xn_iilb_ii_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable0_s;
+} sh_xn_iilb_ii_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_II_CMP_ENABLE1"                 */
+/*                    IILB compare II input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ii_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable1_s;
+} sh_xn_iilb_ii_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_ii_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ii_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ii_cmp_enable1_s;
+} sh_xn_iilb_ii_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA0"                */
+/*                 IILB compare MD input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data0_s;
+} sh_xn_iilb_md_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data0_s;
+} sh_xn_iilb_md_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_MD_CMP_EXP_DATA1"                */
+/*                 IILB compare MD input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data1_s;
+} sh_xn_iilb_md_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_md_cmp_exp_data1_s;
+} sh_xn_iilb_md_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE0"                 */
+/*                    IILB compare MD input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable0_s;
+} sh_xn_iilb_md_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable0_s;
+} sh_xn_iilb_md_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_MD_CMP_ENABLE1"                 */
+/*                    IILB compare MD input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_md_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable1_s;
+} sh_xn_iilb_md_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_md_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_md_cmp_enable1_s;
+} sh_xn_iilb_md_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA0"                */
+/*                 IILB compare PI input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data0_s;
+} sh_xn_iilb_pi_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data0_s;
+} sh_xn_iilb_pi_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_PI_CMP_EXP_DATA1"                */
+/*                 IILB compare PI input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data1_s;
+} sh_xn_iilb_pi_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_pi_cmp_exp_data1_s;
+} sh_xn_iilb_pi_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE0"                 */
+/*                    IILB compare PI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable0_s;
+} sh_xn_iilb_pi_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable0_s;
+} sh_xn_iilb_pi_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_IILB_PI_CMP_ENABLE1"                 */
+/*                    IILB compare PI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_pi_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable1_s;
+} sh_xn_iilb_pi_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_pi_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_pi_cmp_enable1_s;
+} sh_xn_iilb_pi_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA0"                */
+/*                IILB compare NI0 input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data0_s;
+} sh_xn_iilb_ni0_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data0_s;
+} sh_xn_iilb_ni0_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI0_CMP_EXP_DATA1"                */
+/*                IILB compare NI0 input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data1_s;
+} sh_xn_iilb_ni0_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni0_cmp_exp_data1_s;
+} sh_xn_iilb_ni0_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE0"                 */
+/*                    IILB compare NI0 input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable0_s;
+} sh_xn_iilb_ni0_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable0_s;
+} sh_xn_iilb_ni0_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI0_CMP_ENABLE1"                 */
+/*                    IILB compare NI0 input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable1_s;
+} sh_xn_iilb_ni0_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni0_cmp_enable1_s;
+} sh_xn_iilb_ni0_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA0"                */
+/*                IILB compare NI1 input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data0_s;
+} sh_xn_iilb_ni1_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data0_s;
+} sh_xn_iilb_ni1_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_IILB_NI1_CMP_EXP_DATA1"                */
+/*                IILB compare NI1 input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data1_s;
+} sh_xn_iilb_ni1_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_iilb_ni1_cmp_exp_data1_s;
+} sh_xn_iilb_ni1_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE0"                 */
+/*                    IILB compare NI1 input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable0_s;
+} sh_xn_iilb_ni1_cmp_enable0_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable0_s;
+} sh_xn_iilb_ni1_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_IILB_NI1_CMP_ENABLE1"                 */
+/*                    IILB compare NI1 input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_iilb_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable1_s;
+} sh_xn_iilb_ni1_cmp_enable1_u_t;
+#else
+typedef union sh_xn_iilb_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_iilb_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_iilb_ni1_cmp_enable1_s;
+} sh_xn_iilb_ni1_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA0"                */
+/*                 MD compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data0_s;
+} sh_xn_md_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data0_s;
+} sh_xn_md_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_IILB_CMP_EXP_DATA1"                */
+/*                 MD compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data1_s;
+} sh_xn_md_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_iilb_cmp_exp_data1_s;
+} sh_xn_md_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE0"                 */
+/*                    MD compare IILB input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable0_s;
+} sh_xn_md_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable0_s;
+} sh_xn_md_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_IILB_CMP_ENABLE1"                 */
+/*                    MD compare IILB input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable1_s;
+} sh_xn_md_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_md_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_md_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_iilb_cmp_enable1_s;
+} sh_xn_md_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA0"                 */
+/*                 MD compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data0_s;
+} sh_xn_md_ni0_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data0_s;
+} sh_xn_md_ni0_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI0_CMP_EXP_DATA1"                 */
+/*                 MD compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data1_s;
+} sh_xn_md_ni0_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni0_cmp_exp_data1_s;
+} sh_xn_md_ni0_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE0"                  */
+/*                     MD compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable0_s;
+} sh_xn_md_ni0_cmp_enable0_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable0_s;
+} sh_xn_md_ni0_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI0_CMP_ENABLE1"                  */
+/*                     MD compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable1_s;
+} sh_xn_md_ni0_cmp_enable1_u_t;
+#else
+typedef union sh_xn_md_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni0_cmp_enable1_s;
+} sh_xn_md_ni0_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA0"                 */
+/*                 MD compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data0_s;
+} sh_xn_md_ni1_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data0_s;
+} sh_xn_md_ni1_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_MD_NI1_CMP_EXP_DATA1"                 */
+/*                 MD compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data1_s;
+} sh_xn_md_ni1_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_md_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_ni1_cmp_exp_data1_s;
+} sh_xn_md_ni1_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE0"                  */
+/*                     MD compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable0_s;
+} sh_xn_md_ni1_cmp_enable0_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable0_s;
+} sh_xn_md_ni1_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_NI1_CMP_ENABLE1"                  */
+/*                     MD compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable1_s;
+} sh_xn_md_ni1_cmp_enable1_u_t;
+#else
+typedef union sh_xn_md_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_md_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_ni1_cmp_enable1_s;
+} sh_xn_md_ni1_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR0"                 */
+/*                MD compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_sic_cmp_exp_hdr0_s;
+} sh_xn_md_sic_cmp_exp_hdr0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_md_sic_cmp_exp_hdr0_s;
+} sh_xn_md_sic_cmp_exp_hdr0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_MD_SIC_CMP_EXP_HDR1"                 */
+/*                MD compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	data        : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_md_sic_cmp_exp_hdr1_s;
+} sh_xn_md_sic_cmp_exp_hdr1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_md_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	data        : 42;
+	} sh_xn_md_sic_cmp_exp_hdr1_s;
+} sh_xn_md_sic_cmp_exp_hdr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE0"                */
+/*                    MD compare SIC header enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_sic_cmp_hdr_enable0_s;
+} sh_xn_md_sic_cmp_hdr_enable0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_md_sic_cmp_hdr_enable0_s;
+} sh_xn_md_sic_cmp_hdr_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_HDR_ENABLE1"                */
+/*                    MD compare SIC header enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	enable      : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_md_sic_cmp_hdr_enable1_s;
+} sh_xn_md_sic_cmp_hdr_enable1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	enable      : 42;
+	} sh_xn_md_sic_cmp_hdr_enable1_s;
+} sh_xn_md_sic_cmp_hdr_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA0"                   */
+/*                         MD compare SIC data0                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data0_u {
+	mmr_t	sh_xn_md_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_md_sic_cmp_data0_s;
+} sh_xn_md_sic_cmp_data0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data0_u {
+	mmr_t	sh_xn_md_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_md_sic_cmp_data0_s;
+} sh_xn_md_sic_cmp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA1"                   */
+/*                         MD compare SIC data1                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data1_u {
+	mmr_t	sh_xn_md_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_md_sic_cmp_data1_s;
+} sh_xn_md_sic_cmp_data1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data1_u {
+	mmr_t	sh_xn_md_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_md_sic_cmp_data1_s;
+} sh_xn_md_sic_cmp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA2"                   */
+/*                         MD compare SIC data2                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data2_u {
+	mmr_t	sh_xn_md_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_md_sic_cmp_data2_s;
+} sh_xn_md_sic_cmp_data2_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data2_u {
+	mmr_t	sh_xn_md_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_md_sic_cmp_data2_s;
+} sh_xn_md_sic_cmp_data2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_MD_SIC_CMP_DATA3"                   */
+/*                         MD compare SIC data3                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data3_u {
+	mmr_t	sh_xn_md_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_md_sic_cmp_data3_s;
+} sh_xn_md_sic_cmp_data3_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data3_u {
+	mmr_t	sh_xn_md_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_md_sic_cmp_data3_s;
+} sh_xn_md_sic_cmp_data3_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE0"               */
+/*                     MD enable compare SIC data0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_md_sic_cmp_data_enable0_s;
+} sh_xn_md_sic_cmp_data_enable0_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_md_sic_cmp_data_enable0_s;
+} sh_xn_md_sic_cmp_data_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE1"               */
+/*                     MD enable compare SIC data1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_md_sic_cmp_data_enable1_s;
+} sh_xn_md_sic_cmp_data_enable1_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_md_sic_cmp_data_enable1_s;
+} sh_xn_md_sic_cmp_data_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE2"               */
+/*                     MD enable compare SIC data2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_md_sic_cmp_data_enable2_s;
+} sh_xn_md_sic_cmp_data_enable2_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_md_sic_cmp_data_enable2_s;
+} sh_xn_md_sic_cmp_data_enable2_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_MD_SIC_CMP_DATA_ENABLE3"               */
+/*                     MD enable compare SIC data3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_md_sic_cmp_data_enable3_s;
+} sh_xn_md_sic_cmp_data_enable3_u_t;
+#else
+typedef union sh_xn_md_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_md_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_md_sic_cmp_data_enable3_s;
+} sh_xn_md_sic_cmp_data_enable3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA0"                */
+/*                 PI compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data0_s;
+} sh_xn_pi_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data0_s;
+} sh_xn_pi_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_IILB_CMP_EXP_DATA1"                */
+/*                 PI compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data1_s;
+} sh_xn_pi_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_iilb_cmp_exp_data1_s;
+} sh_xn_pi_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE0"                 */
+/*                    PI compare IILB input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable0_s;
+} sh_xn_pi_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable0_s;
+} sh_xn_pi_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_IILB_CMP_ENABLE1"                 */
+/*                    PI compare IILB input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable1_s;
+} sh_xn_pi_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_pi_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_pi_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_iilb_cmp_enable1_s;
+} sh_xn_pi_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA0"                 */
+/*                 PI compare NI0 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data0_s;
+} sh_xn_pi_ni0_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data0_s;
+} sh_xn_pi_ni0_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI0_CMP_EXP_DATA1"                 */
+/*                 PI compare NI0 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data1_s;
+} sh_xn_pi_ni0_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni0_cmp_exp_data1_s;
+} sh_xn_pi_ni0_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE0"                  */
+/*                     PI compare NI0 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable0_s;
+} sh_xn_pi_ni0_cmp_enable0_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable0_s;
+} sh_xn_pi_ni0_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI0_CMP_ENABLE1"                  */
+/*                     PI compare NI0 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable1_s;
+} sh_xn_pi_ni0_cmp_enable1_u_t;
+#else
+typedef union sh_xn_pi_ni0_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni0_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni0_cmp_enable1_s;
+} sh_xn_pi_ni0_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA0"                 */
+/*                 PI compare NI1 input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data0_s;
+} sh_xn_pi_ni1_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_exp_data0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data0_s;
+} sh_xn_pi_ni1_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_PI_NI1_CMP_EXP_DATA1"                 */
+/*                 PI compare NI1 input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data1_s;
+} sh_xn_pi_ni1_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_exp_data1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_ni1_cmp_exp_data1_s;
+} sh_xn_pi_ni1_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE0"                  */
+/*                     PI compare NI1 input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable0_s;
+} sh_xn_pi_ni1_cmp_enable0_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_enable0_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable0_s;
+} sh_xn_pi_ni1_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_NI1_CMP_ENABLE1"                  */
+/*                     PI compare NI1 input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable1_s;
+} sh_xn_pi_ni1_cmp_enable1_u_t;
+#else
+typedef union sh_xn_pi_ni1_cmp_enable1_u {
+	mmr_t	sh_xn_pi_ni1_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_ni1_cmp_enable1_s;
+} sh_xn_pi_ni1_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR0"                 */
+/*                PI compare SIC input expected header0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_sic_cmp_exp_hdr0_s;
+} sh_xn_pi_sic_cmp_exp_hdr0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_exp_hdr0_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_pi_sic_cmp_exp_hdr0_s;
+} sh_xn_pi_sic_cmp_exp_hdr0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_PI_SIC_CMP_EXP_HDR1"                 */
+/*                PI compare SIC input expected header1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	data        : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_pi_sic_cmp_exp_hdr1_s;
+} sh_xn_pi_sic_cmp_exp_hdr1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_exp_hdr1_u {
+	mmr_t	sh_xn_pi_sic_cmp_exp_hdr1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	data        : 42;
+	} sh_xn_pi_sic_cmp_exp_hdr1_s;
+} sh_xn_pi_sic_cmp_exp_hdr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE0"                */
+/*                    PI compare SIC header enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_sic_cmp_hdr_enable0_s;
+} sh_xn_pi_sic_cmp_hdr_enable0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_hdr_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_pi_sic_cmp_hdr_enable0_s;
+} sh_xn_pi_sic_cmp_hdr_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_HDR_ENABLE1"                */
+/*                    PI compare SIC header enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	enable      : 42;
+		mmr_t	reserved_0  : 22;
+	} sh_xn_pi_sic_cmp_hdr_enable1_s;
+} sh_xn_pi_sic_cmp_hdr_enable1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_hdr_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_hdr_enable1_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	enable      : 42;
+	} sh_xn_pi_sic_cmp_hdr_enable1_s;
+} sh_xn_pi_sic_cmp_hdr_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA0"                   */
+/*                         PI compare SIC data0                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_pi_sic_cmp_data0_s;
+} sh_xn_pi_sic_cmp_data0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data0_regval;
+	struct {
+		mmr_t	data0       : 64;
+	} sh_xn_pi_sic_cmp_data0_s;
+} sh_xn_pi_sic_cmp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA1"                   */
+/*                         PI compare SIC data1                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_pi_sic_cmp_data1_s;
+} sh_xn_pi_sic_cmp_data1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data1_regval;
+	struct {
+		mmr_t	data1       : 64;
+	} sh_xn_pi_sic_cmp_data1_s;
+} sh_xn_pi_sic_cmp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA2"                   */
+/*                         PI compare SIC data2                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_pi_sic_cmp_data2_s;
+} sh_xn_pi_sic_cmp_data2_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data2_regval;
+	struct {
+		mmr_t	data2       : 64;
+	} sh_xn_pi_sic_cmp_data2_s;
+} sh_xn_pi_sic_cmp_data2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_PI_SIC_CMP_DATA3"                   */
+/*                         PI compare SIC data3                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_pi_sic_cmp_data3_s;
+} sh_xn_pi_sic_cmp_data3_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data3_regval;
+	struct {
+		mmr_t	data3       : 64;
+	} sh_xn_pi_sic_cmp_data3_s;
+} sh_xn_pi_sic_cmp_data3_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE0"               */
+/*                     PI enable compare SIC data0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_pi_sic_cmp_data_enable0_s;
+} sh_xn_pi_sic_cmp_data_enable0_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable0_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable0_regval;
+	struct {
+		mmr_t	data_enable0 : 64;
+	} sh_xn_pi_sic_cmp_data_enable0_s;
+} sh_xn_pi_sic_cmp_data_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE1"               */
+/*                     PI enable compare SIC data1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_pi_sic_cmp_data_enable1_s;
+} sh_xn_pi_sic_cmp_data_enable1_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable1_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable1_regval;
+	struct {
+		mmr_t	data_enable1 : 64;
+	} sh_xn_pi_sic_cmp_data_enable1_s;
+} sh_xn_pi_sic_cmp_data_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE2"               */
+/*                     PI enable compare SIC data2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_pi_sic_cmp_data_enable2_s;
+} sh_xn_pi_sic_cmp_data_enable2_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable2_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable2_regval;
+	struct {
+		mmr_t	data_enable2 : 64;
+	} sh_xn_pi_sic_cmp_data_enable2_s;
+} sh_xn_pi_sic_cmp_data_enable2_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_PI_SIC_CMP_DATA_ENABLE3"               */
+/*                     PI enable compare SIC data3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_pi_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_pi_sic_cmp_data_enable3_s;
+} sh_xn_pi_sic_cmp_data_enable3_u_t;
+#else
+typedef union sh_xn_pi_sic_cmp_data_enable3_u {
+	mmr_t	sh_xn_pi_sic_cmp_data_enable3_regval;
+	struct {
+		mmr_t	data_enable3 : 64;
+	} sh_xn_pi_sic_cmp_data_enable3_s;
+} sh_xn_pi_sic_cmp_data_enable3_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA0"                */
+/*                NI0 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data0_s;
+} sh_xn_ni0_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data0_s;
+} sh_xn_ni0_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI0_IILB_CMP_EXP_DATA1"                */
+/*                NI0 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data1_s;
+} sh_xn_ni0_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_iilb_cmp_exp_data1_s;
+} sh_xn_ni0_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE0"                 */
+/*                    NI0 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable0_s;
+} sh_xn_ni0_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable0_s;
+} sh_xn_ni0_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_IILB_CMP_ENABLE1"                 */
+/*                    NI0 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable1_s;
+} sh_xn_ni0_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_iilb_cmp_enable1_s;
+} sh_xn_ni0_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data0_s;
+} sh_xn_ni0_pi_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data0_s;
+} sh_xn_ni0_pi_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_PI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data1_s;
+} sh_xn_ni0_pi_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_pi_cmp_exp_data1_s;
+} sh_xn_ni0_pi_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE0"                  */
+/*                     NI0 compare PI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable0_s;
+} sh_xn_ni0_pi_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable0_s;
+} sh_xn_ni0_pi_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_PI_CMP_ENABLE1"                  */
+/*                     NI0 compare PI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable1_s;
+} sh_xn_ni0_pi_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_pi_cmp_enable1_s;
+} sh_xn_ni0_pi_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA0"                 */
+/*                 NI0 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data0_s;
+} sh_xn_ni0_md_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data0_s;
+} sh_xn_ni0_md_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_MD_CMP_EXP_DATA1"                 */
+/*                 NI0 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data1_s;
+} sh_xn_ni0_md_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_md_cmp_exp_data1_s;
+} sh_xn_ni0_md_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE0"                  */
+/*                     NI0 compare MD input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable0_s;
+} sh_xn_ni0_md_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable0_s;
+} sh_xn_ni0_md_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_MD_CMP_ENABLE1"                  */
+/*                     NI0 compare MD input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable1_s;
+} sh_xn_ni0_md_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_md_cmp_enable1_s;
+} sh_xn_ni0_md_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA0"                 */
+/*                 NI0 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data0_s;
+} sh_xn_ni0_ni_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data0_s;
+} sh_xn_ni0_ni_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_NI_CMP_EXP_DATA1"                 */
+/*                 NI0 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data1_s;
+} sh_xn_ni0_ni_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_ni_cmp_exp_data1_s;
+} sh_xn_ni0_ni_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE0"                  */
+/*                     NI0 compare NI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable0_s;
+} sh_xn_ni0_ni_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable0_s;
+} sh_xn_ni0_ni_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_NI_CMP_ENABLE1"                  */
+/*                     NI0 compare NI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable1_s;
+} sh_xn_ni0_ni_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_ni_cmp_enable1_s;
+} sh_xn_ni0_ni_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA0"                */
+/*                 NI0 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data0_s;
+} sh_xn_ni0_llp_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data0_s;
+} sh_xn_ni0_llp_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI0_LLP_CMP_EXP_DATA1"                */
+/*                 NI0 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data1_s;
+} sh_xn_ni0_llp_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni0_llp_cmp_exp_data1_s;
+} sh_xn_ni0_llp_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE0"                 */
+/*                    NI0 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable0_s;
+} sh_xn_ni0_llp_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable0_s;
+} sh_xn_ni0_llp_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI0_LLP_CMP_ENABLE1"                 */
+/*                    NI0 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni0_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable1_s;
+} sh_xn_ni0_llp_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni0_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni0_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni0_llp_cmp_enable1_s;
+} sh_xn_ni0_llp_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA0"                */
+/*                NI1 compare IILB input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data0_s;
+} sh_xn_ni1_iilb_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data0_s;
+} sh_xn_ni1_iilb_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_XN_NI1_IILB_CMP_EXP_DATA1"                */
+/*                NI1 compare IILB input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data1_s;
+} sh_xn_ni1_iilb_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_iilb_cmp_exp_data1_s;
+} sh_xn_ni1_iilb_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE0"                 */
+/*                    NI1 compare IILB input enable0                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable0_s;
+} sh_xn_ni1_iilb_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable0_s;
+} sh_xn_ni1_iilb_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_IILB_CMP_ENABLE1"                 */
+/*                    NI1 compare IILB input enable1                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable1_s;
+} sh_xn_ni1_iilb_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_iilb_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_iilb_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_iilb_cmp_enable1_s;
+} sh_xn_ni1_iilb_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare PI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data0_s;
+} sh_xn_ni1_pi_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data0_s;
+} sh_xn_ni1_pi_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_PI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare PI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data1_s;
+} sh_xn_ni1_pi_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_pi_cmp_exp_data1_s;
+} sh_xn_ni1_pi_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE0"                  */
+/*                     NI1 compare PI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable0_s;
+} sh_xn_ni1_pi_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable0_s;
+} sh_xn_ni1_pi_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_PI_CMP_ENABLE1"                  */
+/*                     NI1 compare PI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable1_s;
+} sh_xn_ni1_pi_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_pi_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_pi_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_pi_cmp_enable1_s;
+} sh_xn_ni1_pi_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA0"                 */
+/*                 NI1 compare MD input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data0_s;
+} sh_xn_ni1_md_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data0_s;
+} sh_xn_ni1_md_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_MD_CMP_EXP_DATA1"                 */
+/*                 NI1 compare MD input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data1_s;
+} sh_xn_ni1_md_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_md_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_md_cmp_exp_data1_s;
+} sh_xn_ni1_md_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE0"                  */
+/*                     NI1 compare MD input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable0_s;
+} sh_xn_ni1_md_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable0_s;
+} sh_xn_ni1_md_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_MD_CMP_ENABLE1"                  */
+/*                     NI1 compare MD input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable1_s;
+} sh_xn_ni1_md_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_md_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_md_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_md_cmp_enable1_s;
+} sh_xn_ni1_md_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA0"                 */
+/*                 NI1 compare NI input expected data0                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data0_s;
+} sh_xn_ni1_ni_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data0_s;
+} sh_xn_ni1_ni_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_NI_CMP_EXP_DATA1"                 */
+/*                 NI1 compare NI input expected data1                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data1_s;
+} sh_xn_ni1_ni_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_ni_cmp_exp_data1_s;
+} sh_xn_ni1_ni_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE0"                  */
+/*                     NI1 compare NI input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable0_s;
+} sh_xn_ni1_ni_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable0_s;
+} sh_xn_ni1_ni_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_NI_CMP_ENABLE1"                  */
+/*                     NI1 compare NI input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable1_s;
+} sh_xn_ni1_ni_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_ni_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_ni_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_ni_cmp_enable1_s;
+} sh_xn_ni1_ni_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA0"                */
+/*                 NI1 compare LLP input expected data0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data0_s;
+} sh_xn_ni1_llp_cmp_exp_data0_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_exp_data0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data0_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data0_s;
+} sh_xn_ni1_llp_cmp_exp_data0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_NI1_LLP_CMP_EXP_DATA1"                */
+/*                 NI1 compare LLP input expected data1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data1_s;
+} sh_xn_ni1_llp_cmp_exp_data1_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_exp_data1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_exp_data1_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_ni1_llp_cmp_exp_data1_s;
+} sh_xn_ni1_llp_cmp_exp_data1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE0"                 */
+/*                    NI1 compare LLP input enable0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable0_s;
+} sh_xn_ni1_llp_cmp_enable0_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_enable0_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable0_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable0_s;
+} sh_xn_ni1_llp_cmp_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_NI1_LLP_CMP_ENABLE1"                 */
+/*                    NI1 compare LLP input enable1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_ni1_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable1_s;
+} sh_xn_ni1_llp_cmp_enable1_u_t;
+#else
+typedef union sh_xn_ni1_llp_cmp_enable1_u {
+	mmr_t	sh_xn_ni1_llp_cmp_enable1_regval;
+	struct {
+		mmr_t	enable      : 64;
+	} sh_xn_ni1_llp_cmp_enable1_s;
+} sh_xn_ni1_llp_cmp_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc_inj_reg_u {
+	mmr_t	sh_xnpi_ecc_inj_reg_regval;
+	struct {
+		mmr_t	byte0          : 8;
+		mmr_t	reserved_0     : 4;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	byte1          : 8;
+		mmr_t	reserved_1     : 4;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	byte2          : 8;
+		mmr_t	reserved_2     : 4;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	byte3          : 8;
+		mmr_t	reserved_3     : 4;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cb_cont3  : 1;
+	} sh_xnpi_ecc_inj_reg_s;
+} sh_xnpi_ecc_inj_reg_u_t;
+#else
+typedef union sh_xnpi_ecc_inj_reg_u {
+	mmr_t	sh_xnpi_ecc_inj_reg_regval;
+	struct {
+		mmr_t	data_cb_cont3  : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	reserved_3     : 4;
+		mmr_t	byte3          : 8;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	reserved_2     : 4;
+		mmr_t	byte2          : 8;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	reserved_1     : 4;
+		mmr_t	byte1          : 8;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	reserved_0     : 4;
+		mmr_t	byte0          : 8;
+	} sh_xnpi_ecc_inj_reg_s;
+} sh_xnpi_ecc_inj_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnpi_ecc0_inj_mask_reg_s;
+} sh_xnpi_ecc0_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnpi_ecc0_inj_mask_reg_s;
+} sh_xnpi_ecc0_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnpi_ecc1_inj_mask_reg_s;
+} sh_xnpi_ecc1_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnpi_ecc1_inj_mask_reg_s;
+} sh_xnpi_ecc1_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnpi_ecc2_inj_mask_reg_s;
+} sh_xnpi_ecc2_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnpi_ecc2_inj_mask_reg_s;
+} sh_xnpi_ecc2_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNPI_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnpi_ecc3_inj_mask_reg_s;
+} sh_xnpi_ecc3_inj_mask_reg_u_t;
+#else
+typedef union sh_xnpi_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnpi_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnpi_ecc3_inj_mask_reg_s;
+} sh_xnpi_ecc3_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ECC_INJ_REG"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc_inj_reg_u {
+	mmr_t	sh_xnmd_ecc_inj_reg_regval;
+	struct {
+		mmr_t	byte0          : 8;
+		mmr_t	reserved_0     : 4;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	byte1          : 8;
+		mmr_t	reserved_1     : 4;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	byte2          : 8;
+		mmr_t	reserved_2     : 4;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	byte3          : 8;
+		mmr_t	reserved_3     : 4;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cb_cont3  : 1;
+	} sh_xnmd_ecc_inj_reg_s;
+} sh_xnmd_ecc_inj_reg_u_t;
+#else
+typedef union sh_xnmd_ecc_inj_reg_u {
+	mmr_t	sh_xnmd_ecc_inj_reg_regval;
+	struct {
+		mmr_t	data_cb_cont3  : 1;
+		mmr_t	data_cb_1shot3 : 1;
+		mmr_t	data_cont3     : 1;
+		mmr_t	data_1shot3    : 1;
+		mmr_t	reserved_3     : 4;
+		mmr_t	byte3          : 8;
+		mmr_t	data_cb_cont2  : 1;
+		mmr_t	data_cb_1shot2 : 1;
+		mmr_t	data_cont2     : 1;
+		mmr_t	data_1shot2    : 1;
+		mmr_t	reserved_2     : 4;
+		mmr_t	byte2          : 8;
+		mmr_t	data_cb_cont1  : 1;
+		mmr_t	data_cb_1shot1 : 1;
+		mmr_t	data_cont1     : 1;
+		mmr_t	data_1shot1    : 1;
+		mmr_t	reserved_1     : 4;
+		mmr_t	byte1          : 8;
+		mmr_t	data_cb_cont0  : 1;
+		mmr_t	data_cb_1shot0 : 1;
+		mmr_t	data_cont0     : 1;
+		mmr_t	data_1shot0    : 1;
+		mmr_t	reserved_0     : 4;
+		mmr_t	byte0          : 8;
+	} sh_xnmd_ecc_inj_reg_s;
+} sh_xnmd_ecc_inj_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC0_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnmd_ecc0_inj_mask_reg_s;
+} sh_xnmd_ecc0_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc0_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc0_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc0   : 64;
+	} sh_xnmd_ecc0_inj_mask_reg_s;
+} sh_xnmd_ecc0_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC1_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnmd_ecc1_inj_mask_reg_s;
+} sh_xnmd_ecc1_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc1_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc1_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc1   : 64;
+	} sh_xnmd_ecc1_inj_mask_reg_s;
+} sh_xnmd_ecc1_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC2_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnmd_ecc2_inj_mask_reg_s;
+} sh_xnmd_ecc2_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc2_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc2_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc2   : 64;
+	} sh_xnmd_ecc2_inj_mask_reg_s;
+} sh_xnmd_ecc2_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNMD_ECC3_INJ_MASK_REG"                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnmd_ecc3_inj_mask_reg_s;
+} sh_xnmd_ecc3_inj_mask_reg_u_t;
+#else
+typedef union sh_xnmd_ecc3_inj_mask_reg_u {
+	mmr_t	sh_xnmd_ecc3_inj_mask_reg_regval;
+	struct {
+		mmr_t	mask_ecc3   : 64;
+	} sh_xnmd_ecc3_inj_mask_reg_s;
+} sh_xnmd_ecc3_inj_mask_reg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ECC_ERR_REPORT"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_ecc_err_report_u {
+	mmr_t	sh_xnmd_ecc_err_report_regval;
+	struct {
+		mmr_t	ecc_disable0 : 1;
+		mmr_t	reserved_0   : 15;
+		mmr_t	ecc_disable1 : 1;
+		mmr_t	reserved_1   : 15;
+		mmr_t	ecc_disable2 : 1;
+		mmr_t	reserved_2   : 15;
+		mmr_t	ecc_disable3 : 1;
+		mmr_t	reserved_3   : 15;
+	} sh_xnmd_ecc_err_report_s;
+} sh_xnmd_ecc_err_report_u_t;
+#else
+typedef union sh_xnmd_ecc_err_report_u {
+	mmr_t	sh_xnmd_ecc_err_report_regval;
+	struct {
+		mmr_t	reserved_3   : 15;
+		mmr_t	ecc_disable3 : 1;
+		mmr_t	reserved_2   : 15;
+		mmr_t	ecc_disable2 : 1;
+		mmr_t	reserved_1   : 15;
+		mmr_t	ecc_disable1 : 1;
+		mmr_t	reserved_0   : 15;
+		mmr_t	ecc_disable0 : 1;
+	} sh_xnmd_ecc_err_report_s;
+} sh_xnmd_ecc_err_report_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_1"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_summary_1_u {
+	mmr_t	sh_ni0_error_summary_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_error_summary_1_s;
+} sh_ni0_error_summary_1_u_t;
+#else
+typedef union sh_ni0_error_summary_1_u {
+	mmr_t	sh_ni0_error_summary_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_error_summary_1_s;
+} sh_ni0_error_summary_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_SUMMARY_2"                   */
+/*                       ni0  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_summary_2_u {
+	mmr_t	sh_ni0_error_summary_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_error_summary_2_s;
+} sh_ni0_error_summary_2_u_t;
+#else
+typedef union sh_ni0_error_summary_2_u {
+	mmr_t	sh_ni0_error_summary_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_error_summary_2_s;
+} sh_ni0_error_summary_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_1"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_overflow_1_u {
+	mmr_t	sh_ni0_error_overflow_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_error_overflow_1_s;
+} sh_ni0_error_overflow_1_u_t;
+#else
+typedef union sh_ni0_error_overflow_1_u {
+	mmr_t	sh_ni0_error_overflow_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_error_overflow_1_s;
+} sh_ni0_error_overflow_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI0_ERROR_OVERFLOW_2"                  */
+/*                       ni0  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_overflow_2_u {
+	mmr_t	sh_ni0_error_overflow_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_error_overflow_2_s;
+} sh_ni0_error_overflow_2_u_t;
+#else
+typedef union sh_ni0_error_overflow_2_u {
+	mmr_t	sh_ni0_error_overflow_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_error_overflow_2_s;
+} sh_ni0_error_overflow_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_1"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_mask_1_u {
+	mmr_t	sh_ni0_error_mask_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_error_mask_1_s;
+} sh_ni0_error_mask_1_u_t;
+#else
+typedef union sh_ni0_error_mask_1_u {
+	mmr_t	sh_ni0_error_mask_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_error_mask_1_s;
+} sh_ni0_error_mask_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI0_ERROR_MASK_2"                    */
+/*                         ni0  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_mask_2_u {
+	mmr_t	sh_ni0_error_mask_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_error_mask_2_s;
+} sh_ni0_error_mask_2_u_t;
+#else
+typedef union sh_ni0_error_mask_2_u {
+	mmr_t	sh_ni0_error_mask_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_error_mask_2_s;
+} sh_ni0_error_mask_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_1"                    */
+/*                        ni0  First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_first_error_1_u {
+	mmr_t	sh_ni0_first_error_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni0_first_error_1_s;
+} sh_ni0_first_error_1_u_t;
+#else
+typedef union sh_ni0_first_error_1_u {
+	mmr_t	sh_ni0_first_error_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni0_first_error_1_s;
+} sh_ni0_first_error_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_FIRST_ERROR_2"                    */
+/*                         ni0 First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_first_error_2_u {
+	mmr_t	sh_ni0_first_error_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni0_first_error_2_s;
+} sh_ni0_first_error_2_u_t;
+#else
+typedef union sh_ni0_first_error_2_u {
+	mmr_t	sh_ni0_first_error_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni0_first_error_2_s;
+} sh_ni0_first_error_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_1"                   */
+/*                ni0 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_detail_1_u {
+	mmr_t	sh_ni0_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_1_s;
+} sh_ni0_error_detail_1_u_t;
+#else
+typedef union sh_ni0_error_detail_1_u {
+	mmr_t	sh_ni0_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_1_s;
+} sh_ni0_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_2"                   */
+/*               ni0 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_detail_2_u {
+	mmr_t	sh_ni0_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_2_s;
+} sh_ni0_error_detail_2_u_t;
+#else
+typedef union sh_ni0_error_detail_2_u {
+	mmr_t	sh_ni0_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni0_error_detail_2_s;
+} sh_ni0_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_1"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_summary_1_u {
+	mmr_t	sh_ni1_error_summary_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_error_summary_1_s;
+} sh_ni1_error_summary_1_u_t;
+#else
+typedef union sh_ni1_error_summary_1_u {
+	mmr_t	sh_ni1_error_summary_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_error_summary_1_s;
+} sh_ni1_error_summary_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_SUMMARY_2"                   */
+/*                       ni1  Error Summary Bits                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_summary_2_u {
+	mmr_t	sh_ni1_error_summary_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_error_summary_2_s;
+} sh_ni1_error_summary_2_u_t;
+#else
+typedef union sh_ni1_error_summary_2_u {
+	mmr_t	sh_ni1_error_summary_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_error_summary_2_s;
+} sh_ni1_error_summary_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_1"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_overflow_1_u {
+	mmr_t	sh_ni1_error_overflow_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_error_overflow_1_s;
+} sh_ni1_error_overflow_1_u_t;
+#else
+typedef union sh_ni1_error_overflow_1_u {
+	mmr_t	sh_ni1_error_overflow_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_error_overflow_1_s;
+} sh_ni1_error_overflow_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_NI1_ERROR_OVERFLOW_2"                  */
+/*                       ni1  Error Overflow Bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_overflow_2_u {
+	mmr_t	sh_ni1_error_overflow_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_error_overflow_2_s;
+} sh_ni1_error_overflow_2_u_t;
+#else
+typedef union sh_ni1_error_overflow_2_u {
+	mmr_t	sh_ni1_error_overflow_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_error_overflow_2_s;
+} sh_ni1_error_overflow_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_1"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_mask_1_u {
+	mmr_t	sh_ni1_error_mask_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_error_mask_1_s;
+} sh_ni1_error_mask_1_u_t;
+#else
+typedef union sh_ni1_error_mask_1_u {
+	mmr_t	sh_ni1_error_mask_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_error_mask_1_s;
+} sh_ni1_error_mask_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_NI1_ERROR_MASK_2"                    */
+/*                         ni1  Error Mask Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_mask_2_u {
+	mmr_t	sh_ni1_error_mask_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_error_mask_2_s;
+} sh_ni1_error_mask_2_u_t;
+#else
+typedef union sh_ni1_error_mask_2_u {
+	mmr_t	sh_ni1_error_mask_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_error_mask_2_s;
+} sh_ni1_error_mask_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_1"                    */
+/*                        ni1  First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_first_error_1_u {
+	mmr_t	sh_ni1_first_error_1_regval;
+	struct {
+		mmr_t	overflow_fifo02_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc3           : 1;
+	} sh_ni1_first_error_1_s;
+} sh_ni1_first_error_1_u_t;
+#else
+typedef union sh_ni1_first_error_1_u {
+	mmr_t	sh_ni1_first_error_1_regval;
+	struct {
+		mmr_t	tail_timeout_ni_vc3           : 1;
+		mmr_t	tail_timeout_ni_vc2           : 1;
+		mmr_t	tail_timeout_ni_vc1           : 1;
+		mmr_t	tail_timeout_ni_vc0           : 1;
+		mmr_t	tail_timeout_fifo13_vc3       : 1;
+		mmr_t	tail_timeout_fifo13_vc1       : 1;
+		mmr_t	tail_timeout_fifo02_vc2       : 1;
+		mmr_t	tail_timeout_fifo02_vc0       : 1;
+		mmr_t	overflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	overflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_credit   : 1;
+		mmr_t	overflow_md_fifo_vc0_credit   : 1;
+		mmr_t	overflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	overflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	overflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	overflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	overflow_md_fifo_vc2_push     : 1;
+		mmr_t	overflow_md_fifo_vc0_push     : 1;
+		mmr_t	overflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	overflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	overflow_pi_fifo_vc2_push     : 1;
+		mmr_t	overflow_pi_fifo_vc0_push     : 1;
+		mmr_t	overflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	overflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	overflow_md_fifo_vc2_pop      : 1;
+		mmr_t	overflow_md_fifo_vc0_pop      : 1;
+		mmr_t	overflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	overflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	overflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	overflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	overflow_ni_fifo_debit3       : 1;
+		mmr_t	overflow_ni_fifo_debit2       : 1;
+		mmr_t	overflow_ni_fifo_debit1       : 1;
+		mmr_t	overflow_ni_fifo_debit0       : 1;
+		mmr_t	overflow_md_fifo_debit2       : 1;
+		mmr_t	overflow_md_fifo_debit0       : 1;
+		mmr_t	overflow_iilb_fifo_debit2     : 1;
+		mmr_t	overflow_iilb_fifo_debit0     : 1;
+		mmr_t	overflow_pi_fifo_debit2       : 1;
+		mmr_t	overflow_pi_fifo_debit0       : 1;
+		mmr_t	overflow2_vc2_credit          : 1;
+		mmr_t	overflow1_vc2_credit          : 1;
+		mmr_t	overflow0_vc2_credit          : 1;
+		mmr_t	overflow2_vc0_credit          : 1;
+		mmr_t	overflow1_vc0_credit          : 1;
+		mmr_t	overflow0_vc0_credit          : 1;
+		mmr_t	overflow_fifo13_vc2_credit    : 1;
+		mmr_t	overflow_fifo13_vc0_credit    : 1;
+		mmr_t	overflow_fifo02_vc2_credit    : 1;
+		mmr_t	overflow_fifo02_vc0_credit    : 1;
+		mmr_t	overflow_fifo13_vc3_push      : 1;
+		mmr_t	overflow_fifo13_vc1_push      : 1;
+		mmr_t	overflow_fifo02_vc2_push      : 1;
+		mmr_t	overflow_fifo02_vc0_push      : 1;
+		mmr_t	overflow_fifo13_vc3_pop       : 1;
+		mmr_t	overflow_fifo13_vc1_pop       : 1;
+		mmr_t	overflow_fifo02_vc2_pop       : 1;
+		mmr_t	overflow_fifo02_vc0_pop       : 1;
+		mmr_t	overflow_fifo13_debit2        : 1;
+		mmr_t	overflow_fifo13_debit0        : 1;
+		mmr_t	overflow_fifo02_debit2        : 1;
+		mmr_t	overflow_fifo02_debit0        : 1;
+	} sh_ni1_first_error_1_s;
+} sh_ni1_first_error_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_FIRST_ERROR_2"                    */
+/*                         ni1 First Error Bits                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_first_error_2_u {
+	mmr_t	sh_ni1_first_error_2_regval;
+	struct {
+		mmr_t	illegal_vcni                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	reserved_1                     : 1;
+	} sh_ni1_first_error_2_s;
+} sh_ni1_first_error_2_u_t;
+#else
+typedef union sh_ni1_first_error_2_u {
+	mmr_t	sh_ni1_first_error_2_regval;
+	struct {
+		mmr_t	reserved_1                     : 1;
+		mmr_t	retry_timeout_error            : 1;
+		mmr_t	lut_read_error                 : 1;
+		mmr_t	chiplet_nomatch                : 1;
+		mmr_t	llp_deadlock_vc3               : 1;
+		mmr_t	llp_deadlock_vc2               : 1;
+		mmr_t	llp_deadlock_vc1               : 1;
+		mmr_t	llp_deadlock_vc0               : 1;
+		mmr_t	underflow_ni_fifo_vc3_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc2_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc1_credit   : 1;
+		mmr_t	underflow_ni_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_credit   : 1;
+		mmr_t	underflow_md_fifo_vc0_credit   : 1;
+		mmr_t	underflow_iilb_fifo_vc2_credit : 1;
+		mmr_t	underflow_iilb_fifo_vc0_credit : 1;
+		mmr_t	underflow_pi_fifo_vc2_credit   : 1;
+		mmr_t	underflow_pi_fifo_vc0_credit   : 1;
+		mmr_t	underflow_md_fifo_vc2_push     : 1;
+		mmr_t	underflow_md_fifo_vc0_push     : 1;
+		mmr_t	underflow_iilb_fifo_vc2_push   : 1;
+		mmr_t	underflow_iilb_fifo_vc0_push   : 1;
+		mmr_t	underflow_pi_fifo_vc2_push     : 1;
+		mmr_t	underflow_pi_fifo_vc0_push     : 1;
+		mmr_t	underflow_ni_fifo_vc2_pop      : 1;
+		mmr_t	underflow_ni_fifo_vc0_pop      : 1;
+		mmr_t	underflow_md_fifo_vc2_pop      : 1;
+		mmr_t	underflow_md_fifo_vc0_pop      : 1;
+		mmr_t	underflow_iilb_fifo_vc2_pop    : 1;
+		mmr_t	underflow_iilb_fifo_vc0_pop    : 1;
+		mmr_t	underflow_pi_fifo_vc2_pop      : 1;
+		mmr_t	underflow_pi_fifo_vc0_pop      : 1;
+		mmr_t	reserved_0                     : 10;
+		mmr_t	underflow2_vc2_credit          : 1;
+		mmr_t	underflow1_vc2_credit          : 1;
+		mmr_t	underflow0_vc2_credit          : 1;
+		mmr_t	underflow2_vc0_credit          : 1;
+		mmr_t	underflow1_vc0_credit          : 1;
+		mmr_t	underflow0_vc0_credit          : 1;
+		mmr_t	underflow_fifo13_vc2_credit    : 1;
+		mmr_t	underflow_fifo13_vc0_credit    : 1;
+		mmr_t	underflow_fifo02_vc2_credit    : 1;
+		mmr_t	underflow_fifo02_vc0_credit    : 1;
+		mmr_t	underflow_fifo13_vc3_push      : 1;
+		mmr_t	underflow_fifo13_vc1_push      : 1;
+		mmr_t	underflow_fifo02_vc2_push      : 1;
+		mmr_t	underflow_fifo02_vc0_push      : 1;
+		mmr_t	underflow_fifo13_vc3_pop       : 1;
+		mmr_t	underflow_fifo13_vc1_pop       : 1;
+		mmr_t	underflow_fifo02_vc2_pop       : 1;
+		mmr_t	underflow_fifo02_vc0_pop       : 1;
+		mmr_t	illegal_vciilb                 : 1;
+		mmr_t	illegal_vcmd                   : 1;
+		mmr_t	illegal_vcpi                   : 1;
+		mmr_t	illegal_vcni                   : 1;
+	} sh_ni1_first_error_2_s;
+} sh_ni1_first_error_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_1"                   */
+/*                ni1 Chiplet no match header bits 63:0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_detail_1_u {
+	mmr_t	sh_ni1_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_1_s;
+} sh_ni1_error_detail_1_u_t;
+#else
+typedef union sh_ni1_error_detail_1_u {
+	mmr_t	sh_ni1_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_1_s;
+} sh_ni1_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_2"                   */
+/*               ni1 Chiplet no match header bits 127:64                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_detail_2_u {
+	mmr_t	sh_ni1_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_2_s;
+} sh_ni1_error_detail_2_u_t;
+#else
+typedef union sh_ni1_error_detail_2_u {
+	mmr_t	sh_ni1_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_ni1_error_detail_2_s;
+} sh_ni1_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_1"                  */
+/*                       Corrected error details                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_1_u {
+	mmr_t	sh_xn_corrected_detail_1_regval;
+	struct {
+		mmr_t	ecc0_syndrome : 8;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	reserved_3    : 4;
+	} sh_xn_corrected_detail_1_s;
+} sh_xn_corrected_detail_1_u_t;
+#else
+typedef union sh_xn_corrected_detail_1_u {
+	mmr_t	sh_xn_corrected_detail_1_regval;
+	struct {
+		mmr_t	reserved_3    : 4;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_syndrome : 8;
+	} sh_xn_corrected_detail_1_s;
+} sh_xn_corrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_2"                  */
+/*                         Corrected error data                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_2_u {
+	mmr_t	sh_xn_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_corrected_detail_2_s;
+} sh_xn_corrected_detail_2_u_t;
+#else
+typedef union sh_xn_corrected_detail_2_u {
+	mmr_t	sh_xn_corrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_corrected_detail_2_s;
+} sh_xn_corrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_3"                  */
+/*                       Corrected error header0                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_3_u {
+	mmr_t	sh_xn_corrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_corrected_detail_3_s;
+} sh_xn_corrected_detail_3_u_t;
+#else
+typedef union sh_xn_corrected_detail_3_u {
+	mmr_t	sh_xn_corrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_corrected_detail_3_s;
+} sh_xn_corrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XN_CORRECTED_DETAIL_4"                  */
+/*                       Corrected error header1                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_corrected_detail_4_u {
+	mmr_t	sh_xn_corrected_detail_4_regval;
+	struct {
+		mmr_t	header1     : 42;
+		mmr_t	reserved_0  : 20;
+		mmr_t	err_group   : 2;
+	} sh_xn_corrected_detail_4_s;
+} sh_xn_corrected_detail_4_u_t;
+#else
+typedef union sh_xn_corrected_detail_4_u {
+	mmr_t	sh_xn_corrected_detail_4_regval;
+	struct {
+		mmr_t	err_group   : 2;
+		mmr_t	reserved_0  : 20;
+		mmr_t	header1     : 42;
+	} sh_xn_corrected_detail_4_s;
+} sh_xn_corrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_1"                 */
+/*                      Uncorrected error details                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_1_u {
+	mmr_t	sh_xn_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	ecc0_syndrome : 8;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	reserved_3    : 4;
+	} sh_xn_uncorrected_detail_1_s;
+} sh_xn_uncorrected_detail_1_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_1_u {
+	mmr_t	sh_xn_uncorrected_detail_1_regval;
+	struct {
+		mmr_t	reserved_3    : 4;
+		mmr_t	ecc3_vc       : 2;
+		mmr_t	ecc3_wc       : 2;
+		mmr_t	ecc3_syndrome : 8;
+		mmr_t	reserved_2    : 4;
+		mmr_t	ecc2_vc       : 2;
+		mmr_t	ecc2_wc       : 2;
+		mmr_t	ecc2_syndrome : 8;
+		mmr_t	reserved_1    : 4;
+		mmr_t	ecc1_vc       : 2;
+		mmr_t	ecc1_wc       : 2;
+		mmr_t	ecc1_syndrome : 8;
+		mmr_t	reserved_0    : 4;
+		mmr_t	ecc0_vc       : 2;
+		mmr_t	ecc0_wc       : 2;
+		mmr_t	ecc0_syndrome : 8;
+	} sh_xn_uncorrected_detail_1_s;
+} sh_xn_uncorrected_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_2"                 */
+/*                        Uncorrected error data                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_2_u {
+	mmr_t	sh_xn_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_uncorrected_detail_2_s;
+} sh_xn_uncorrected_detail_2_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_2_u {
+	mmr_t	sh_xn_uncorrected_detail_2_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_xn_uncorrected_detail_2_s;
+} sh_xn_uncorrected_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_3"                 */
+/*                      Uncorrected error header0                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_3_u {
+	mmr_t	sh_xn_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_uncorrected_detail_3_s;
+} sh_xn_uncorrected_detail_3_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_3_u {
+	mmr_t	sh_xn_uncorrected_detail_3_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_xn_uncorrected_detail_3_s;
+} sh_xn_uncorrected_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_XN_UNCORRECTED_DETAIL_4"                 */
+/*                      Uncorrected error header1                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncorrected_detail_4_u {
+	mmr_t	sh_xn_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	header1     : 42;
+		mmr_t	reserved_0  : 20;
+		mmr_t	err_group   : 2;
+	} sh_xn_uncorrected_detail_4_s;
+} sh_xn_uncorrected_detail_4_u_t;
+#else
+typedef union sh_xn_uncorrected_detail_4_u {
+	mmr_t	sh_xn_uncorrected_detail_4_regval;
+	struct {
+		mmr_t	err_group   : 2;
+		mmr_t	reserved_0  : 20;
+		mmr_t	header1     : 42;
+	} sh_xn_uncorrected_detail_4_s;
+} sh_xn_uncorrected_detail_4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (md)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_detail_1_u {
+	mmr_t	sh_xnmd_error_detail_1_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_xnmd_error_detail_1_s;
+} sh_xnmd_error_detail_1_u_t;
+#else
+typedef union sh_xnmd_error_detail_1_u {
+	mmr_t	sh_xnmd_error_detail_1_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_xnmd_error_detail_1_s;
+} sh_xnmd_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_DETAIL_1"                   */
+/*                      Look Up Table Address (pi)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_detail_1_u {
+	mmr_t	sh_xnpi_error_detail_1_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_xnpi_error_detail_1_s;
+} sh_xnpi_error_detail_1_u_t;
+#else
+typedef union sh_xnpi_error_detail_1_u {
+	mmr_t	sh_xnpi_error_detail_1_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_xnpi_error_detail_1_s;
+} sh_xnpi_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_1"                  */
+/*                    Chiplet NoMatch header [63:0]                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_detail_1_u {
+	mmr_t	sh_xniilb_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_1_s;
+} sh_xniilb_error_detail_1_u_t;
+#else
+typedef union sh_xniilb_error_detail_1_u {
+	mmr_t	sh_xniilb_error_detail_1_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_1_s;
+} sh_xniilb_error_detail_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_2"                  */
+/*                   Chiplet NoMatch header [127:64]                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_detail_2_u {
+	mmr_t	sh_xniilb_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_2_s;
+} sh_xniilb_error_detail_2_u_t;
+#else
+typedef union sh_xniilb_error_detail_2_u {
+	mmr_t	sh_xniilb_error_detail_2_regval;
+	struct {
+		mmr_t	header      : 64;
+	} sh_xniilb_error_detail_2_s;
+} sh_xniilb_error_detail_2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_DETAIL_3"                  */
+/*                     Look Up Table Address (iilb)                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_detail_3_u {
+	mmr_t	sh_xniilb_error_detail_3_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_xniilb_error_detail_3_s;
+} sh_xniilb_error_detail_3_u_t;
+#else
+typedef union sh_xniilb_error_detail_3_u {
+	mmr_t	sh_xniilb_error_detail_3_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_xniilb_error_detail_3_s;
+} sh_xniilb_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI0_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni0)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni0_error_detail_3_u {
+	mmr_t	sh_ni0_error_detail_3_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_ni0_error_detail_3_s;
+} sh_ni0_error_detail_3_u_t;
+#else
+typedef union sh_ni0_error_detail_3_u {
+	mmr_t	sh_ni0_error_detail_3_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_ni0_error_detail_3_s;
+} sh_ni0_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_NI1_ERROR_DETAIL_3"                   */
+/*                     Look Up Table Address (ni1)                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ni1_error_detail_3_u {
+	mmr_t	sh_ni1_error_detail_3_regval;
+	struct {
+		mmr_t	lut_addr    : 11;
+		mmr_t	reserved_0  : 53;
+	} sh_ni1_error_detail_3_s;
+} sh_ni1_error_detail_3_u_t;
+#else
+typedef union sh_ni1_error_detail_3_u {
+	mmr_t	sh_ni1_error_detail_3_regval;
+	struct {
+		mmr_t	reserved_0  : 53;
+		mmr_t	lut_addr    : 11;
+	} sh_ni1_error_detail_3_s;
+} sh_ni1_error_detail_3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_ERROR_SUMMARY"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_error_summary_u {
+	mmr_t	sh_xn_error_summary_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_error_summary_s;
+} sh_xn_error_summary_u_t;
+#else
+typedef union sh_xn_error_summary_u {
+	mmr_t	sh_xn_error_summary_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_error_summary_s;
+} sh_xn_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_ERROR_OVERFLOW"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_error_overflow_u {
+	mmr_t	sh_xn_error_overflow_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_error_overflow_s;
+} sh_xn_error_overflow_u_t;
+#else
+typedef union sh_xn_error_overflow_u {
+	mmr_t	sh_xn_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_error_overflow_s;
+} sh_xn_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XN_ERROR_MASK"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_error_mask_u {
+	mmr_t	sh_xn_error_mask_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_error_mask_s;
+} sh_xn_error_mask_u_t;
+#else
+typedef union sh_xn_error_mask_u {
+	mmr_t	sh_xn_error_mask_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_error_mask_s;
+} sh_xn_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XN_FIRST_ERROR"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_first_error_u {
+	mmr_t	sh_xn_first_error_regval;
+	struct {
+		mmr_t	ni0_pop_overflow        : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	reserved_0              : 26;
+	} sh_xn_first_error_s;
+} sh_xn_first_error_u_t;
+#else
+typedef union sh_xn_first_error_u {
+	mmr_t	sh_xn_first_error_regval;
+	struct {
+		mmr_t	reserved_0              : 26;
+		mmr_t	iilb_chiplet_or_lut     : 1;
+		mmr_t	iilb_fifo_underflow     : 1;
+		mmr_t	iilb_credit_underflow   : 1;
+		mmr_t	iilb_fifo_overflow      : 1;
+		mmr_t	iilb_credit_overflow    : 1;
+		mmr_t	iilb_debit_overflow     : 1;
+		mmr_t	xnpi_lut_error          : 1;
+		mmr_t	xnpi_uce_error          : 1;
+		mmr_t	xnpi_sbe_error          : 1;
+		mmr_t	xnpi_credit_underflow   : 1;
+		mmr_t	xnpi_data_buff_overflow : 1;
+		mmr_t	xnpi_debit_overflow     : 1;
+		mmr_t	xnpi_credit_overflow    : 1;
+		mmr_t	xnmd_lut_error          : 1;
+		mmr_t	xnmd_uce_error          : 1;
+		mmr_t	xnmd_sbe_error          : 1;
+		mmr_t	xnmd_credit_underflow   : 1;
+		mmr_t	xnmd_data_buff_overflow : 1;
+		mmr_t	xnmd_debit_overflow     : 1;
+		mmr_t	xnmd_credit_overflow    : 1;
+		mmr_t	ni1_pipe_error          : 1;
+		mmr_t	ni1_llp_error           : 1;
+		mmr_t	ni1_credit_underflow    : 1;
+		mmr_t	ni1_push_underflow      : 1;
+		mmr_t	ni1_pop_underflow       : 1;
+		mmr_t	ni1_debit_overflow      : 1;
+		mmr_t	ni1_credit_overflow     : 1;
+		mmr_t	ni1_push_overflow       : 1;
+		mmr_t	ni1_pop_overflow        : 1;
+		mmr_t	ni0_pipe_error          : 1;
+		mmr_t	ni0_llp_error           : 1;
+		mmr_t	ni0_credit_underflow    : 1;
+		mmr_t	ni0_push_underflow      : 1;
+		mmr_t	ni0_pop_underflow       : 1;
+		mmr_t	ni0_debit_overflow      : 1;
+		mmr_t	ni0_credit_overflow     : 1;
+		mmr_t	ni0_push_overflow       : 1;
+		mmr_t	ni0_pop_overflow        : 1;
+	} sh_xn_first_error_s;
+} sh_xn_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNIILB_ERROR_SUMMARY"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_summary_u {
+	mmr_t	sh_xniilb_error_summary_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_error_summary_s;
+} sh_xniilb_error_summary_u_t;
+#else
+typedef union sh_xniilb_error_summary_u {
+	mmr_t	sh_xniilb_error_summary_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_error_summary_s;
+} sh_xniilb_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_XNIILB_ERROR_OVERFLOW"                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_overflow_u {
+	mmr_t	sh_xniilb_error_overflow_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_error_overflow_s;
+} sh_xniilb_error_overflow_u_t;
+#else
+typedef union sh_xniilb_error_overflow_u {
+	mmr_t	sh_xniilb_error_overflow_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_error_overflow_s;
+} sh_xniilb_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_ERROR_MASK"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_error_mask_u {
+	mmr_t	sh_xniilb_error_mask_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_error_mask_s;
+} sh_xniilb_error_mask_u_t;
+#else
+typedef union sh_xniilb_error_mask_u {
+	mmr_t	sh_xniilb_error_mask_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_error_mask_s;
+} sh_xniilb_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNIILB_FIRST_ERROR"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xniilb_first_error_u {
+	mmr_t	sh_xniilb_first_error_regval;
+	struct {
+		mmr_t	overflow_ii_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	lut_read_error                : 1;
+	} sh_xniilb_first_error_s;
+} sh_xniilb_first_error_u_t;
+#else
+typedef union sh_xniilb_first_error_u {
+	mmr_t	sh_xniilb_first_error_regval;
+	struct {
+		mmr_t	lut_read_error                : 1;
+		mmr_t	chiplet_nomatch               : 1;
+		mmr_t	underflow_ni1_vc2_credit_out  : 1;
+		mmr_t	underflow_ni1_vc0_credit_out  : 1;
+		mmr_t	underflow_ni0_vc2_credit_out  : 1;
+		mmr_t	underflow_ni0_vc0_credit_out  : 1;
+		mmr_t	underflow_iilb_vc2_credit_out : 1;
+		mmr_t	underflow_iilb_vc0_credit_out : 1;
+		mmr_t	underflow_md_vc2_credit_out   : 1;
+		mmr_t	underflow_md_vc0_credit_out   : 1;
+		mmr_t	underflow_pi_vc2_credit_out   : 1;
+		mmr_t	underflow_pi_vc0_credit_out   : 1;
+		mmr_t	overflow_ni1_vc2_credit_out   : 1;
+		mmr_t	overflow_ni1_vc0_credit_out   : 1;
+		mmr_t	overflow_ni0_vc2_credit_out   : 1;
+		mmr_t	overflow_ni0_vc0_credit_out   : 1;
+		mmr_t	overflow_iilb_vc2_credit_out  : 1;
+		mmr_t	overflow_iilb_vc0_credit_out  : 1;
+		mmr_t	overflow_md_vc2_credit_out    : 1;
+		mmr_t	overflow_md_vc0_credit_out    : 1;
+		mmr_t	overflow_pi_vc2_credit_out    : 1;
+		mmr_t	overflow_pi_vc0_credit_out    : 1;
+		mmr_t	overflow_ni1_debit2           : 1;
+		mmr_t	overflow_ni1_debit0           : 1;
+		mmr_t	overflow_ni0_debit2           : 1;
+		mmr_t	overflow_ni0_debit0           : 1;
+		mmr_t	overflow_md_debit2            : 1;
+		mmr_t	overflow_md_debit0            : 1;
+		mmr_t	overflow_iilb_debit2          : 1;
+		mmr_t	overflow_iilb_debit0          : 1;
+		mmr_t	overflow_pi_debit2            : 1;
+		mmr_t	overflow_pi_debit0            : 1;
+		mmr_t	underflow_ni1_vc2_credit_in   : 1;
+		mmr_t	underflow_ni0_vc2_credit_in   : 1;
+		mmr_t	underflow_md_vc2_credit_in    : 1;
+		mmr_t	underflow_iilb_vc2_credit_in  : 1;
+		mmr_t	underflow_pi_vc2_credit_in    : 1;
+		mmr_t	underflow_ni1_vc0_credit_in   : 1;
+		mmr_t	underflow_ni0_vc0_credit_in   : 1;
+		mmr_t	underflow_md_vc0_credit_in    : 1;
+		mmr_t	underflow_iilb_vc0_credit_in  : 1;
+		mmr_t	underflow_pi_vc0_credit_in    : 1;
+		mmr_t	overflow_ni1_vc2_credit_in    : 1;
+		mmr_t	overflow_ni0_vc2_credit_in    : 1;
+		mmr_t	overflow_md_vc2_credit_in     : 1;
+		mmr_t	overflow_iilb_vc2_credit_in   : 1;
+		mmr_t	overflow_pi_vc2_credit_in     : 1;
+		mmr_t	overflow_ni1_vc0_credit_in    : 1;
+		mmr_t	overflow_ni0_vc0_credit_in    : 1;
+		mmr_t	overflow_md_vc0_credit_in     : 1;
+		mmr_t	overflow_iilb_vc0_credit_in   : 1;
+		mmr_t	overflow_pi_vc0_credit_in     : 1;
+		mmr_t	underflow_lb_vc2              : 1;
+		mmr_t	underflow_lb_vc0              : 1;
+		mmr_t	overflow_lb_vc2               : 1;
+		mmr_t	overflow_lb_vc0               : 1;
+		mmr_t	underflow_ii_vc2              : 1;
+		mmr_t	underflow_ii_vc0              : 1;
+		mmr_t	overflow_ii_vc2               : 1;
+		mmr_t	overflow_ii_vc0               : 1;
+		mmr_t	overflow_lb_debit2            : 1;
+		mmr_t	overflow_lb_debit0            : 1;
+		mmr_t	overflow_ii_debit2            : 1;
+		mmr_t	overflow_ii_debit0            : 1;
+	} sh_xniilb_first_error_s;
+} sh_xniilb_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNPI_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_summary_u {
+	mmr_t	sh_xnpi_error_summary_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_error_summary_s;
+} sh_xnpi_error_summary_u_t;
+#else
+typedef union sh_xnpi_error_summary_u {
+	mmr_t	sh_xnpi_error_summary_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_error_summary_s;
+} sh_xnpi_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNPI_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_overflow_u {
+	mmr_t	sh_xnpi_error_overflow_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_error_overflow_s;
+} sh_xnpi_error_overflow_u_t;
+#else
+typedef union sh_xnpi_error_overflow_u {
+	mmr_t	sh_xnpi_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_error_overflow_s;
+} sh_xnpi_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_error_mask_u {
+	mmr_t	sh_xnpi_error_mask_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_error_mask_s;
+} sh_xnpi_error_mask_u_t;
+#else
+typedef union sh_xnpi_error_mask_u {
+	mmr_t	sh_xnpi_error_mask_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_error_mask_s;
+} sh_xnpi_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNPI_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnpi_first_error_u {
+	mmr_t	sh_xnpi_first_error_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnpi_first_error_s;
+} sh_xnpi_first_error_u_t;
+#else
+typedef union sh_xnpi_first_error_u {
+	mmr_t	sh_xnpi_first_error_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnpi_first_error_s;
+} sh_xnpi_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XNMD_ERROR_SUMMARY"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_summary_u {
+	mmr_t	sh_xnmd_error_summary_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_error_summary_s;
+} sh_xnmd_error_summary_u_t;
+#else
+typedef union sh_xnmd_error_summary_u {
+	mmr_t	sh_xnmd_error_summary_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_error_summary_s;
+} sh_xnmd_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XNMD_ERROR_OVERFLOW"                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_overflow_u {
+	mmr_t	sh_xnmd_error_overflow_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_error_overflow_s;
+} sh_xnmd_error_overflow_u_t;
+#else
+typedef union sh_xnmd_error_overflow_u {
+	mmr_t	sh_xnmd_error_overflow_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_error_overflow_s;
+} sh_xnmd_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_ERROR_MASK"                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_error_mask_u {
+	mmr_t	sh_xnmd_error_mask_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_error_mask_s;
+} sh_xnmd_error_mask_u_t;
+#else
+typedef union sh_xnmd_error_mask_u {
+	mmr_t	sh_xnmd_error_mask_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_error_mask_s;
+} sh_xnmd_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XNMD_FIRST_ERROR"                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xnmd_first_error_u {
+	mmr_t	sh_xnmd_first_error_regval;
+	struct {
+		mmr_t	underflow_ni0_vc0           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	reserved_0                  : 14;
+	} sh_xnmd_first_error_s;
+} sh_xnmd_first_error_u_t;
+#else
+typedef union sh_xnmd_first_error_u {
+	mmr_t	sh_xnmd_first_error_regval;
+	struct {
+		mmr_t	reserved_0                  : 14;
+		mmr_t	overflow_header_cancel_fifo : 1;
+		mmr_t	overflow_iilb_vc2_credit    : 1;
+		mmr_t	underflow_iilb_vc2_credit   : 1;
+		mmr_t	overflow_iilb_vc0_credit    : 1;
+		mmr_t	underflow_iilb_vc0_credit   : 1;
+		mmr_t	overflow_ni1_vc2_credit     : 1;
+		mmr_t	underflow_ni1_vc2_credit    : 1;
+		mmr_t	overflow_ni1_vc0_credit     : 1;
+		mmr_t	underflow_ni1_vc0_credit    : 1;
+		mmr_t	overflow_ni0_vc2_credit     : 1;
+		mmr_t	underflow_ni0_vc2_credit    : 1;
+		mmr_t	overflow_ni0_vc0_credit     : 1;
+		mmr_t	underflow_ni0_vc0_credit    : 1;
+		mmr_t	overflow_iilb_debit2        : 1;
+		mmr_t	overflow_iilb_debit0        : 1;
+		mmr_t	overflow_ni1_debit2         : 1;
+		mmr_t	overflow_ni1_debit0         : 1;
+		mmr_t	overflow_ni0_debit2         : 1;
+		mmr_t	overflow_ni0_debit0         : 1;
+		mmr_t	overflow_sic_cntr2          : 1;
+		mmr_t	underflow_sic_cntr2         : 1;
+		mmr_t	overflow_sic_cntr0          : 1;
+		mmr_t	underflow_sic_cntr0         : 1;
+		mmr_t	uncor_error3                : 1;
+		mmr_t	uncor_error2                : 1;
+		mmr_t	uncor_error1                : 1;
+		mmr_t	uncor_error0                : 1;
+		mmr_t	single_bit_error3           : 1;
+		mmr_t	single_bit_error2           : 1;
+		mmr_t	single_bit_error1           : 1;
+		mmr_t	single_bit_error0           : 1;
+		mmr_t	lut_read_error              : 1;
+		mmr_t	overflow_databuff_vc2       : 1;
+		mmr_t	overflow_databuff_vc0       : 1;
+		mmr_t	overflow_vc2_credit         : 1;
+		mmr_t	underflow_vc2_credit        : 1;
+		mmr_t	overflow_vc0_credit         : 1;
+		mmr_t	underflow_vc0_credit        : 1;
+		mmr_t	overflow_iilb_vc2           : 1;
+		mmr_t	underflow_iilb_vc2          : 1;
+		mmr_t	overflow_iilb_vc0           : 1;
+		mmr_t	underflow_iilb_vc0          : 1;
+		mmr_t	overflow_ni1_vc2            : 1;
+		mmr_t	underflow_ni1_vc2           : 1;
+		mmr_t	overflow_ni1_vc0            : 1;
+		mmr_t	underflow_ni1_vc0           : 1;
+		mmr_t	overflow_ni0_vc2            : 1;
+		mmr_t	underflow_ni0_vc2           : 1;
+		mmr_t	overflow_ni0_vc0            : 1;
+		mmr_t	underflow_ni0_vc0           : 1;
+	} sh_xnmd_first_error_s;
+} sh_xnmd_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE0"                   */
+/*                 Automatic Maintenance Reply Enable 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_enable0_u {
+	mmr_t	sh_auto_reply_enable0_regval;
+	struct {
+		mmr_t	enable0     : 64;
+	} sh_auto_reply_enable0_s;
+} sh_auto_reply_enable0_u_t;
+#else
+typedef union sh_auto_reply_enable0_u {
+	mmr_t	sh_auto_reply_enable0_regval;
+	struct {
+		mmr_t	enable0     : 64;
+	} sh_auto_reply_enable0_s;
+} sh_auto_reply_enable0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_ENABLE1"                   */
+/*                 Automatic Maintenance Reply Enable 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_enable1_u {
+	mmr_t	sh_auto_reply_enable1_regval;
+	struct {
+		mmr_t	enable1     : 64;
+	} sh_auto_reply_enable1_s;
+} sh_auto_reply_enable1_u_t;
+#else
+typedef union sh_auto_reply_enable1_u {
+	mmr_t	sh_auto_reply_enable1_regval;
+	struct {
+		mmr_t	enable1     : 64;
+	} sh_auto_reply_enable1_s;
+} sh_auto_reply_enable1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER0"                   */
+/*                 Automatic Maintenance Reply Header 0                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_header0_u {
+	mmr_t	sh_auto_reply_header0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_auto_reply_header0_s;
+} sh_auto_reply_header0_u_t;
+#else
+typedef union sh_auto_reply_header0_u {
+	mmr_t	sh_auto_reply_header0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_auto_reply_header0_s;
+} sh_auto_reply_header0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_AUTO_REPLY_HEADER1"                   */
+/*                 Automatic Maintenance Reply Header 1                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_auto_reply_header1_u {
+	mmr_t	sh_auto_reply_header1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_auto_reply_header1_s;
+} sh_auto_reply_header1_u_t;
+#else
+typedef union sh_auto_reply_header1_u {
+	mmr_t	sh_auto_reply_header1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_auto_reply_header1_s;
+} sh_auto_reply_header1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RP_AUTO_REPLY"                  */
+/*         Enable Automatic Maintenance Reply From Reply Queue          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_enable_rp_auto_reply_u {
+	mmr_t	sh_enable_rp_auto_reply_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_enable_rp_auto_reply_s;
+} sh_enable_rp_auto_reply_u_t;
+#else
+typedef union sh_enable_rp_auto_reply_u {
+	mmr_t	sh_enable_rp_auto_reply_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	enable      : 1;
+	} sh_enable_rp_auto_reply_s;
+} sh_enable_rp_auto_reply_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_ENABLE_RQ_AUTO_REPLY"                  */
+/*        Enable Automatic Maintenance Reply From Request Queue         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_enable_rq_auto_reply_u {
+	mmr_t	sh_enable_rq_auto_reply_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_enable_rq_auto_reply_s;
+} sh_enable_rq_auto_reply_u_t;
+#else
+typedef union sh_enable_rq_auto_reply_u {
+	mmr_t	sh_enable_rq_auto_reply_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	enable      : 1;
+	} sh_enable_rq_auto_reply_s;
+} sh_enable_rq_auto_reply_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_REDIRECT_INVAL"                     */
+/*               Redirect invalidate to LB instead of PI                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_redirect_inval_u {
+	mmr_t	sh_redirect_inval_regval;
+	struct {
+		mmr_t	redirect    : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_redirect_inval_s;
+} sh_redirect_inval_u_t;
+#else
+typedef union sh_redirect_inval_u {
+	mmr_t	sh_redirect_inval_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	redirect    : 1;
+	} sh_redirect_inval_s;
+} sh_redirect_inval_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_CNTRL"                     */
+/*                 Diagnostic Message Control Register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_cntrl_u {
+	mmr_t	sh_diag_msg_cntrl_regval;
+	struct {
+		mmr_t	msg_length          : 6;
+		mmr_t	error_inject_point  : 6;
+		mmr_t	error_inject_enable : 1;
+		mmr_t	port                : 1;
+		mmr_t	reserved_0          : 48;
+		mmr_t	start               : 1;
+		mmr_t	busy                : 1;
+	} sh_diag_msg_cntrl_s;
+} sh_diag_msg_cntrl_u_t;
+#else
+typedef union sh_diag_msg_cntrl_u {
+	mmr_t	sh_diag_msg_cntrl_regval;
+	struct {
+		mmr_t	busy                : 1;
+		mmr_t	start               : 1;
+		mmr_t	reserved_0          : 48;
+		mmr_t	port                : 1;
+		mmr_t	error_inject_enable : 1;
+		mmr_t	error_inject_point  : 6;
+		mmr_t	msg_length          : 6;
+	} sh_diag_msg_cntrl_s;
+} sh_diag_msg_cntrl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data0l_u {
+	mmr_t	sh_diag_msg_data0l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data0l_s;
+} sh_diag_msg_data0l_u_t;
+#else
+typedef union sh_diag_msg_data0l_u {
+	mmr_t	sh_diag_msg_data0l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data0l_s;
+} sh_diag_msg_data0l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA0U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data0u_u {
+	mmr_t	sh_diag_msg_data0u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data0u_s;
+} sh_diag_msg_data0u_u_t;
+#else
+typedef union sh_diag_msg_data0u_u {
+	mmr_t	sh_diag_msg_data0u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data0u_s;
+} sh_diag_msg_data0u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data1l_u {
+	mmr_t	sh_diag_msg_data1l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data1l_s;
+} sh_diag_msg_data1l_u_t;
+#else
+typedef union sh_diag_msg_data1l_u {
+	mmr_t	sh_diag_msg_data1l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data1l_s;
+} sh_diag_msg_data1l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA1U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data1u_u {
+	mmr_t	sh_diag_msg_data1u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data1u_s;
+} sh_diag_msg_data1u_u_t;
+#else
+typedef union sh_diag_msg_data1u_u {
+	mmr_t	sh_diag_msg_data1u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data1u_s;
+} sh_diag_msg_data1u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data2l_u {
+	mmr_t	sh_diag_msg_data2l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data2l_s;
+} sh_diag_msg_data2l_u_t;
+#else
+typedef union sh_diag_msg_data2l_u {
+	mmr_t	sh_diag_msg_data2l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data2l_s;
+} sh_diag_msg_data2l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA2U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data2u_u {
+	mmr_t	sh_diag_msg_data2u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data2u_s;
+} sh_diag_msg_data2u_u_t;
+#else
+typedef union sh_diag_msg_data2u_u {
+	mmr_t	sh_diag_msg_data2u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data2u_s;
+} sh_diag_msg_data2u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data3l_u {
+	mmr_t	sh_diag_msg_data3l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data3l_s;
+} sh_diag_msg_data3l_u_t;
+#else
+typedef union sh_diag_msg_data3l_u {
+	mmr_t	sh_diag_msg_data3l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data3l_s;
+} sh_diag_msg_data3l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA3U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data3u_u {
+	mmr_t	sh_diag_msg_data3u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data3u_s;
+} sh_diag_msg_data3u_u_t;
+#else
+typedef union sh_diag_msg_data3u_u {
+	mmr_t	sh_diag_msg_data3u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data3u_s;
+} sh_diag_msg_data3u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data4l_u {
+	mmr_t	sh_diag_msg_data4l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data4l_s;
+} sh_diag_msg_data4l_u_t;
+#else
+typedef union sh_diag_msg_data4l_u {
+	mmr_t	sh_diag_msg_data4l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data4l_s;
+} sh_diag_msg_data4l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA4U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data4u_u {
+	mmr_t	sh_diag_msg_data4u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data4u_s;
+} sh_diag_msg_data4u_u_t;
+#else
+typedef union sh_diag_msg_data4u_u {
+	mmr_t	sh_diag_msg_data4u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data4u_s;
+} sh_diag_msg_data4u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data5l_u {
+	mmr_t	sh_diag_msg_data5l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data5l_s;
+} sh_diag_msg_data5l_u_t;
+#else
+typedef union sh_diag_msg_data5l_u {
+	mmr_t	sh_diag_msg_data5l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data5l_s;
+} sh_diag_msg_data5l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA5U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data5u_u {
+	mmr_t	sh_diag_msg_data5u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data5u_s;
+} sh_diag_msg_data5u_u_t;
+#else
+typedef union sh_diag_msg_data5u_u {
+	mmr_t	sh_diag_msg_data5u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data5u_s;
+} sh_diag_msg_data5u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data6l_u {
+	mmr_t	sh_diag_msg_data6l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data6l_s;
+} sh_diag_msg_data6l_u_t;
+#else
+typedef union sh_diag_msg_data6l_u {
+	mmr_t	sh_diag_msg_data6l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data6l_s;
+} sh_diag_msg_data6l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA6U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data6u_u {
+	mmr_t	sh_diag_msg_data6u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data6u_s;
+} sh_diag_msg_data6u_u_t;
+#else
+typedef union sh_diag_msg_data6u_u {
+	mmr_t	sh_diag_msg_data6u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data6u_s;
+} sh_diag_msg_data6u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data7l_u {
+	mmr_t	sh_diag_msg_data7l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data7l_s;
+} sh_diag_msg_data7l_u_t;
+#else
+typedef union sh_diag_msg_data7l_u {
+	mmr_t	sh_diag_msg_data7l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data7l_s;
+} sh_diag_msg_data7l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA7U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data7u_u {
+	mmr_t	sh_diag_msg_data7u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data7u_s;
+} sh_diag_msg_data7u_u_t;
+#else
+typedef union sh_diag_msg_data7u_u {
+	mmr_t	sh_diag_msg_data7u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data7u_s;
+} sh_diag_msg_data7u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8L"                     */
+/*                    Diagnostic Data, lower 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data8l_u {
+	mmr_t	sh_diag_msg_data8l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data8l_s;
+} sh_diag_msg_data8l_u_t;
+#else
+typedef union sh_diag_msg_data8l_u {
+	mmr_t	sh_diag_msg_data8l_regval;
+	struct {
+		mmr_t	data_lower  : 64;
+	} sh_diag_msg_data8l_s;
+} sh_diag_msg_data8l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_DIAG_MSG_DATA8U"                     */
+/*                   Diagnostice Data, upper 64 bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_data8u_u {
+	mmr_t	sh_diag_msg_data8u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data8u_s;
+} sh_diag_msg_data8u_u_t;
+#else
+typedef union sh_diag_msg_data8u_u {
+	mmr_t	sh_diag_msg_data8u_regval;
+	struct {
+		mmr_t	data_upper  : 64;
+	} sh_diag_msg_data8u_s;
+} sh_diag_msg_data8u_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR0"                      */
+/*              Diagnostice Data, lower 64 bits of header               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_hdr0_u {
+	mmr_t	sh_diag_msg_hdr0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_diag_msg_hdr0_s;
+} sh_diag_msg_hdr0_u_t;
+#else
+typedef union sh_diag_msg_hdr0_u {
+	mmr_t	sh_diag_msg_hdr0_regval;
+	struct {
+		mmr_t	header0     : 64;
+	} sh_diag_msg_hdr0_s;
+} sh_diag_msg_hdr0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_DIAG_MSG_HDR1"                      */
+/*              Diagnostice Data, upper 64 bits of header               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_diag_msg_hdr1_u {
+	mmr_t	sh_diag_msg_hdr1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_diag_msg_hdr1_s;
+} sh_diag_msg_hdr1_u_t;
+#else
+typedef union sh_diag_msg_hdr1_u {
+	mmr_t	sh_diag_msg_hdr1_regval;
+	struct {
+		mmr_t	header1     : 64;
+	} sh_diag_msg_hdr1_s;
+} sh_diag_msg_hdr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_DEBUG_SELECT"                      */
+/*                        SHub Debug Port Select                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_debug_select_u {
+	mmr_t	sh_debug_select_regval;
+	struct {
+		mmr_t	nibble0_nibble_sel  : 3;
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	debug_ii_sel        : 3;
+		mmr_t	sel_ii              : 9;
+		mmr_t	reserved_0          : 3;
+		mmr_t	trigger_enable      : 1;
+	} sh_debug_select_s;
+} sh_debug_select_u_t;
+#else
+typedef union sh_debug_select_u {
+	mmr_t	sh_debug_select_regval;
+	struct {
+		mmr_t	trigger_enable      : 1;
+		mmr_t	reserved_0          : 3;
+		mmr_t	sel_ii              : 9;
+		mmr_t	debug_ii_sel        : 3;
+		mmr_t	nibble7_chiplet_sel : 3;
+		mmr_t	nibble7_nibble_sel  : 3;
+		mmr_t	nibble6_chiplet_sel : 3;
+		mmr_t	nibble6_nibble_sel  : 3;
+		mmr_t	nibble5_chiplet_sel : 3;
+		mmr_t	nibble5_nibble_sel  : 3;
+		mmr_t	nibble4_chiplet_sel : 3;
+		mmr_t	nibble4_nibble_sel  : 3;
+		mmr_t	nibble3_chiplet_sel : 3;
+		mmr_t	nibble3_nibble_sel  : 3;
+		mmr_t	nibble2_chiplet_sel : 3;
+		mmr_t	nibble2_nibble_sel  : 3;
+		mmr_t	nibble1_chiplet_sel : 3;
+		mmr_t	nibble1_nibble_sel  : 3;
+		mmr_t	nibble0_chiplet_sel : 3;
+		mmr_t	nibble0_nibble_sel  : 3;
+	} sh_debug_select_s;
+} sh_debug_select_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TRIGGER_COMPARE_MASK"                  */
+/*                      SHub Trigger Compare Mask                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_trigger_compare_mask_u {
+	mmr_t	sh_trigger_compare_mask_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_trigger_compare_mask_s;
+} sh_trigger_compare_mask_u_t;
+#else
+typedef union sh_trigger_compare_mask_u {
+	mmr_t	sh_trigger_compare_mask_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	mask        : 32;
+	} sh_trigger_compare_mask_s;
+} sh_trigger_compare_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_TRIGGER_COMPARE_PATTERN"                 */
+/*                     SHub Trigger Compare Pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_trigger_compare_pattern_u {
+	mmr_t	sh_trigger_compare_pattern_regval;
+	struct {
+		mmr_t	data        : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_trigger_compare_pattern_s;
+} sh_trigger_compare_pattern_u_t;
+#else
+typedef union sh_trigger_compare_pattern_u {
+	mmr_t	sh_trigger_compare_pattern_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	data        : 32;
+	} sh_trigger_compare_pattern_s;
+} sh_trigger_compare_pattern_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_TRIGGER_SEL"                       */
+/*                  Trigger select for SHUB debug port                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_trigger_sel_u {
+	mmr_t	sh_trigger_sel_regval;
+	struct {
+		mmr_t	nibble0_input_sel  : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_15        : 1;
+	} sh_trigger_sel_s;
+} sh_trigger_sel_u_t;
+#else
+typedef union sh_trigger_sel_u {
+	mmr_t	sh_trigger_sel_regval;
+	struct {
+		mmr_t	reserved_15        : 1;
+		mmr_t	nibble7_nibble_sel : 3;
+		mmr_t	reserved_14        : 1;
+		mmr_t	nibble7_input_sel  : 3;
+		mmr_t	reserved_13        : 1;
+		mmr_t	nibble6_nibble_sel : 3;
+		mmr_t	reserved_12        : 1;
+		mmr_t	nibble6_input_sel  : 3;
+		mmr_t	reserved_11        : 1;
+		mmr_t	nibble5_nibble_sel : 3;
+		mmr_t	reserved_10        : 1;
+		mmr_t	nibble5_input_sel  : 3;
+		mmr_t	reserved_9         : 1;
+		mmr_t	nibble4_nibble_sel : 3;
+		mmr_t	reserved_8         : 1;
+		mmr_t	nibble4_input_sel  : 3;
+		mmr_t	reserved_7         : 1;
+		mmr_t	nibble3_nibble_sel : 3;
+		mmr_t	reserved_6         : 1;
+		mmr_t	nibble3_input_sel  : 3;
+		mmr_t	reserved_5         : 1;
+		mmr_t	nibble2_nibble_sel : 3;
+		mmr_t	reserved_4         : 1;
+		mmr_t	nibble2_input_sel  : 3;
+		mmr_t	reserved_3         : 1;
+		mmr_t	nibble1_nibble_sel : 3;
+		mmr_t	reserved_2         : 1;
+		mmr_t	nibble1_input_sel  : 3;
+		mmr_t	reserved_1         : 1;
+		mmr_t	nibble0_nibble_sel : 3;
+		mmr_t	reserved_0         : 1;
+		mmr_t	nibble0_input_sel  : 3;
+	} sh_trigger_sel_s;
+} sh_trigger_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_STOP_CLK_CONTROL"                    */
+/*                          Stop Clock Control                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_stop_clk_control_u {
+	mmr_t	sh_stop_clk_control_regval;
+	struct {
+		mmr_t	stimulus    : 5;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	mode        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_stop_clk_control_s;
+} sh_stop_clk_control_u_t;
+#else
+typedef union sh_stop_clk_control_u {
+	mmr_t	sh_stop_clk_control_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	mode        : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	stimulus    : 5;
+	} sh_stop_clk_control_s;
+} sh_stop_clk_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_STOP_CLK_DELAY_PHASE"                  */
+/*                        Stop Clock Delay Phase                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_stop_clk_delay_phase_u {
+	mmr_t	sh_stop_clk_delay_phase_regval;
+	struct {
+		mmr_t	delay       : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_stop_clk_delay_phase_s;
+} sh_stop_clk_delay_phase_u_t;
+#else
+typedef union sh_stop_clk_delay_phase_u {
+	mmr_t	sh_stop_clk_delay_phase_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	delay       : 8;
+	} sh_stop_clk_delay_phase_s;
+} sh_stop_clk_delay_phase_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_TSF_ARM_MASK"                      */
+/*                 Trigger sequencing facility arm mask                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_arm_mask_u {
+	mmr_t	sh_tsf_arm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_arm_mask_s;
+} sh_tsf_arm_mask_u_t;
+#else
+typedef union sh_tsf_arm_mask_u {
+	mmr_t	sh_tsf_arm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_arm_mask_s;
+} sh_tsf_arm_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_COUNTER_PRESETS"                   */
+/*             Trigger sequencing facility counter presets              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_counter_presets_u {
+	mmr_t	sh_tsf_counter_presets_regval;
+	struct {
+		mmr_t	count_32    : 32;
+		mmr_t	count_16    : 16;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_8a    : 8;
+	} sh_tsf_counter_presets_s;
+} sh_tsf_counter_presets_u_t;
+#else
+typedef union sh_tsf_counter_presets_u {
+	mmr_t	sh_tsf_counter_presets_regval;
+	struct {
+		mmr_t	count_8a    : 8;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_16    : 16;
+		mmr_t	count_32    : 32;
+	} sh_tsf_counter_presets_s;
+} sh_tsf_counter_presets_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_DECREMENT_CTL"                    */
+/*        Trigger sequencing facility counter decrement control         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_decrement_ctl_u {
+	mmr_t	sh_tsf_decrement_ctl_regval;
+	struct {
+		mmr_t	ctl         : 16;
+		mmr_t	reserved_0  : 48;
+	} sh_tsf_decrement_ctl_s;
+} sh_tsf_decrement_ctl_u_t;
+#else
+typedef union sh_tsf_decrement_ctl_u {
+	mmr_t	sh_tsf_decrement_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 48;
+		mmr_t	ctl         : 16;
+	} sh_tsf_decrement_ctl_s;
+} sh_tsf_decrement_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DIAG_MSG_CTL"                    */
+/*        Trigger sequencing facility diagnostic message control        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_diag_msg_ctl_u {
+	mmr_t	sh_tsf_diag_msg_ctl_regval;
+	struct {
+		mmr_t	enable      : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_diag_msg_ctl_s;
+} sh_tsf_diag_msg_ctl_u_t;
+#else
+typedef union sh_tsf_diag_msg_ctl_u {
+	mmr_t	sh_tsf_diag_msg_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	enable      : 8;
+	} sh_tsf_diag_msg_ctl_s;
+} sh_tsf_diag_msg_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_DISARM_MASK"                     */
+/*               Trigger sequencing facility disarm mask                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_disarm_mask_u {
+	mmr_t	sh_tsf_disarm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_disarm_mask_s;
+} sh_tsf_disarm_mask_u_t;
+#else
+typedef union sh_tsf_disarm_mask_u {
+	mmr_t	sh_tsf_disarm_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_disarm_mask_s;
+} sh_tsf_disarm_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_TSF_ENABLE_CTL"                     */
+/*          Trigger sequencing facility counter enable control          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_enable_ctl_u {
+	mmr_t	sh_tsf_enable_ctl_regval;
+	struct {
+		mmr_t	ctl         : 16;
+		mmr_t	reserved_0  : 48;
+	} sh_tsf_enable_ctl_s;
+} sh_tsf_enable_ctl_u_t;
+#else
+typedef union sh_tsf_enable_ctl_u {
+	mmr_t	sh_tsf_enable_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 48;
+		mmr_t	ctl         : 16;
+	} sh_tsf_enable_ctl_s;
+} sh_tsf_enable_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_SOFTWARE_ARM"                    */
+/*               Trigger sequencing facility software arm               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_software_arm_u {
+	mmr_t	sh_tsf_software_arm_regval;
+	struct {
+		mmr_t	bit0        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit7        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_software_arm_s;
+} sh_tsf_software_arm_u_t;
+#else
+typedef union sh_tsf_software_arm_u {
+	mmr_t	sh_tsf_software_arm_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	bit7        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit0        : 1;
+	} sh_tsf_software_arm_s;
+} sh_tsf_software_arm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_SOFTWARE_DISARM"                   */
+/*             Trigger sequencing facility software disarm              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_software_disarm_u {
+	mmr_t	sh_tsf_software_disarm_regval;
+	struct {
+		mmr_t	bit0        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit7        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_software_disarm_s;
+} sh_tsf_software_disarm_u_t;
+#else
+typedef union sh_tsf_software_disarm_u {
+	mmr_t	sh_tsf_software_disarm_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	bit7        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit0        : 1;
+	} sh_tsf_software_disarm_s;
+} sh_tsf_software_disarm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_TSF_SOFTWARE_TRIGGERED"                 */
+/*            Trigger sequencing facility software triggered            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_software_triggered_u {
+	mmr_t	sh_tsf_software_triggered_regval;
+	struct {
+		mmr_t	bit0        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit7        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_software_triggered_s;
+} sh_tsf_software_triggered_u_t;
+#else
+typedef union sh_tsf_software_triggered_u {
+	mmr_t	sh_tsf_software_triggered_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	bit7        : 1;
+		mmr_t	bit6        : 1;
+		mmr_t	bit5        : 1;
+		mmr_t	bit4        : 1;
+		mmr_t	bit3        : 1;
+		mmr_t	bit2        : 1;
+		mmr_t	bit1        : 1;
+		mmr_t	bit0        : 1;
+	} sh_tsf_software_triggered_s;
+} sh_tsf_software_triggered_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_TRIGGER_MASK"                    */
+/*               Trigger sequencing facility trigger mask               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_trigger_mask_u {
+	mmr_t	sh_tsf_trigger_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_trigger_mask_s;
+} sh_tsf_trigger_mask_u_t;
+#else
+typedef union sh_tsf_trigger_mask_u {
+	mmr_t	sh_tsf_trigger_mask_regval;
+	struct {
+		mmr_t	mask        : 64;
+	} sh_tsf_trigger_mask_s;
+} sh_tsf_trigger_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_VEC_DATA"                        */
+/*                  Vector Write Request Message Data                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_data_u {
+	mmr_t	sh_vec_data_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_data_s;
+} sh_vec_data_u_t;
+#else
+typedef union sh_vec_data_u {
+	mmr_t	sh_vec_data_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_data_s;
+} sh_vec_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_PARMS"                        */
+/*                  Vector Message Parameters Register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_parms_u {
+	mmr_t	sh_vec_parms_regval;
+	struct {
+		mmr_t	type        : 1;
+		mmr_t	ni_port     : 1;
+		mmr_t	reserved_0  : 1;
+		mmr_t	address     : 32;
+		mmr_t	pio_id      : 11;
+		mmr_t	reserved_1  : 16;
+		mmr_t	start       : 1;
+		mmr_t	busy        : 1;
+	} sh_vec_parms_s;
+} sh_vec_parms_u_t;
+#else
+typedef union sh_vec_parms_u {
+	mmr_t	sh_vec_parms_regval;
+	struct {
+		mmr_t	busy        : 1;
+		mmr_t	start       : 1;
+		mmr_t	reserved_1  : 16;
+		mmr_t	pio_id      : 11;
+		mmr_t	address     : 32;
+		mmr_t	reserved_0  : 1;
+		mmr_t	ni_port     : 1;
+		mmr_t	type        : 1;
+	} sh_vec_parms_s;
+} sh_vec_parms_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_ROUTE"                        */
+/*                     Vector Request Message Route                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_route_u {
+	mmr_t	sh_vec_route_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_route_s;
+} sh_vec_route_u_t;
+#else
+typedef union sh_vec_route_u {
+	mmr_t	sh_vec_route_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_route_s;
+} sh_vec_route_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_CPU_PERM"                        */
+/*                    CPU MMR Access Permission Bits                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_cpu_perm_u {
+	mmr_t	sh_cpu_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_cpu_perm_s;
+} sh_cpu_perm_u_t;
+#else
+typedef union sh_cpu_perm_u {
+	mmr_t	sh_cpu_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_cpu_perm_s;
+} sh_cpu_perm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_CPU_PERM_OVR"                      */
+/*                  CPU MMR Access Permission Override                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_cpu_perm_ovr_u {
+	mmr_t	sh_cpu_perm_ovr_regval;
+	struct {
+		mmr_t	override    : 64;
+	} sh_cpu_perm_ovr_s;
+} sh_cpu_perm_ovr_u_t;
+#else
+typedef union sh_cpu_perm_ovr_u {
+	mmr_t	sh_cpu_perm_ovr_regval;
+	struct {
+		mmr_t	override    : 64;
+	} sh_cpu_perm_ovr_s;
+} sh_cpu_perm_ovr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_EXT_IO_PERM"                       */
+/*                External IO MMR Access Permission Bits                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ext_io_perm_u {
+	mmr_t	sh_ext_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_io_perm_s;
+} sh_ext_io_perm_u_t;
+#else
+typedef union sh_ext_io_perm_u {
+	mmr_t	sh_ext_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_io_perm_s;
+} sh_ext_io_perm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_EXT_IOI_ACCESS"                     */
+/*             External IO Interrupt Access Permission Bits             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ext_ioi_access_u {
+	mmr_t	sh_ext_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_ioi_access_s;
+} sh_ext_ioi_access_u_t;
+#else
+typedef union sh_ext_ioi_access_u {
+	mmr_t	sh_ext_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ext_ioi_access_s;
+} sh_ext_ioi_access_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GC_FIL_CTRL"                       */
+/*                   SHub Global Clock Filter Control                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gc_fil_ctrl_u {
+	mmr_t	sh_gc_fil_ctrl_regval;
+	struct {
+		mmr_t	offset          : 5;
+		mmr_t	reserved_0      : 3;
+		mmr_t	mask_counter    : 12;
+		mmr_t	mask_enable     : 1;
+		mmr_t	reserved_1      : 3;
+		mmr_t	dropout_counter : 10;
+		mmr_t	reserved_2      : 2;
+		mmr_t	dropout_thresh  : 10;
+		mmr_t	reserved_3      : 2;
+		mmr_t	error_counter   : 10;
+		mmr_t	reserved_4      : 6;
+	} sh_gc_fil_ctrl_s;
+} sh_gc_fil_ctrl_u_t;
+#else
+typedef union sh_gc_fil_ctrl_u {
+	mmr_t	sh_gc_fil_ctrl_regval;
+	struct {
+		mmr_t	reserved_4      : 6;
+		mmr_t	error_counter   : 10;
+		mmr_t	reserved_3      : 2;
+		mmr_t	dropout_thresh  : 10;
+		mmr_t	reserved_2      : 2;
+		mmr_t	dropout_counter : 10;
+		mmr_t	reserved_1      : 3;
+		mmr_t	mask_enable     : 1;
+		mmr_t	mask_counter    : 12;
+		mmr_t	reserved_0      : 3;
+		mmr_t	offset          : 5;
+	} sh_gc_fil_ctrl_s;
+} sh_gc_fil_ctrl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_GC_SRC_CTRL"                       */
+/*                      SHub Global Clock Control                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_gc_src_ctrl_u {
+	mmr_t	sh_gc_src_ctrl_regval;
+	struct {
+		mmr_t	enable_counter : 1;
+		mmr_t	reserved_0     : 3;
+		mmr_t	max_count      : 10;
+		mmr_t	reserved_1     : 2;
+		mmr_t	counter        : 10;
+		mmr_t	reserved_2     : 2;
+		mmr_t	toggle_bit     : 1;
+		mmr_t	reserved_3     : 3;
+		mmr_t	source_sel     : 2;
+		mmr_t	reserved_4     : 30;
+	} sh_gc_src_ctrl_s;
+} sh_gc_src_ctrl_u_t;
+#else
+typedef union sh_gc_src_ctrl_u {
+	mmr_t	sh_gc_src_ctrl_regval;
+	struct {
+		mmr_t	reserved_4     : 30;
+		mmr_t	source_sel     : 2;
+		mmr_t	reserved_3     : 3;
+		mmr_t	toggle_bit     : 1;
+		mmr_t	reserved_2     : 2;
+		mmr_t	counter        : 10;
+		mmr_t	reserved_1     : 2;
+		mmr_t	max_count      : 10;
+		mmr_t	reserved_0     : 3;
+		mmr_t	enable_counter : 1;
+	} sh_gc_src_ctrl_s;
+} sh_gc_src_ctrl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_HARD_RESET"                       */
+/*                           SHub Hard Reset                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_hard_reset_u {
+	mmr_t	sh_hard_reset_regval;
+	struct {
+		mmr_t	hard_reset  : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_hard_reset_s;
+} sh_hard_reset_u_t;
+#else
+typedef union sh_hard_reset_u {
+	mmr_t	sh_hard_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	hard_reset  : 1;
+	} sh_hard_reset_s;
+} sh_hard_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_IO_PERM"                         */
+/*                    II MMR Access Permission Bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_io_perm_u {
+	mmr_t	sh_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_io_perm_s;
+} sh_io_perm_u_t;
+#else
+typedef union sh_io_perm_u {
+	mmr_t	sh_io_perm_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_io_perm_s;
+} sh_io_perm_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_IOI_ACCESS"                       */
+/*                 II Interrupt Access Permission Bits                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ioi_access_u {
+	mmr_t	sh_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ioi_access_s;
+} sh_ioi_access_u_t;
+#else
+typedef union sh_ioi_access_u {
+	mmr_t	sh_ioi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ioi_access_s;
+} sh_ioi_access_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_IPI_ACCESS"                       */
+/*                 CPU interrupt Access Permission Bits                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ipi_access_u {
+	mmr_t	sh_ipi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ipi_access_s;
+} sh_ipi_access_u_t;
+#else
+typedef union sh_ipi_access_u {
+	mmr_t	sh_ipi_access_regval;
+	struct {
+		mmr_t	access_bits : 64;
+	} sh_ipi_access_s;
+} sh_ipi_access_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_JTAG_CONFIG"                       */
+/*                       SHub JTAG configuration                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_jtag_config_u {
+	mmr_t	sh_jtag_config_regval;
+	struct {
+		mmr_t	md_clk_sel                    : 2;
+		mmr_t	ni_clk_sel                    : 1;
+		mmr_t	ii_clk_sel                    : 2;
+		mmr_t	wrt90_target                  : 14;
+		mmr_t	wrt90_overrider               : 1;
+		mmr_t	wrt90_override                : 1;
+		mmr_t	jtag_mci_reset_delay          : 4;
+		mmr_t	jtag_mci_target               : 14;
+		mmr_t	jtag_mci_override             : 1;
+		mmr_t	fsb_config_ioq_depth          : 1;
+		mmr_t	fsb_config_sample_binit       : 1;
+		mmr_t	fsb_config_enable_bus_parking : 1;
+		mmr_t	fsb_config_clock_ratio        : 5;
+		mmr_t	fsb_config_output_tristate    : 4;
+		mmr_t	fsb_config_enable_bist        : 1;
+		mmr_t	fsb_config_aux                : 2;
+		mmr_t	gtl_config_re                 : 1;
+		mmr_t	reserved_0                    : 8;
+	} sh_jtag_config_s;
+} sh_jtag_config_u_t;
+#else
+typedef union sh_jtag_config_u {
+	mmr_t	sh_jtag_config_regval;
+	struct {
+		mmr_t	reserved_0                    : 8;
+		mmr_t	gtl_config_re                 : 1;
+		mmr_t	fsb_config_aux                : 2;
+		mmr_t	fsb_config_enable_bist        : 1;
+		mmr_t	fsb_config_output_tristate    : 4;
+		mmr_t	fsb_config_clock_ratio        : 5;
+		mmr_t	fsb_config_enable_bus_parking : 1;
+		mmr_t	fsb_config_sample_binit       : 1;
+		mmr_t	fsb_config_ioq_depth          : 1;
+		mmr_t	jtag_mci_override             : 1;
+		mmr_t	jtag_mci_target               : 14;
+		mmr_t	jtag_mci_reset_delay          : 4;
+		mmr_t	wrt90_override                : 1;
+		mmr_t	wrt90_overrider               : 1;
+		mmr_t	wrt90_target                  : 14;
+		mmr_t	ii_clk_sel                    : 2;
+		mmr_t	ni_clk_sel                    : 1;
+		mmr_t	md_clk_sel                    : 2;
+	} sh_jtag_config_s;
+} sh_jtag_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SHUB_ID"                         */
+/*                            SHub ID Number                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shub_id_u {
+	mmr_t	sh_shub_id_regval;
+	struct {
+		mmr_t	force1        : 1;
+		mmr_t	manufacturer  : 11;
+		mmr_t	part_number   : 16;
+		mmr_t	revision      : 4;
+		mmr_t	node_id       : 11;
+		mmr_t	reserved_0    : 1;
+		mmr_t	sharing_mode  : 2;
+		mmr_t	reserved_1    : 2;
+		mmr_t	nodes_per_bit : 5;
+		mmr_t	reserved_2    : 3;
+		mmr_t	ni_port       : 1;
+		mmr_t	reserved_3    : 7;
+	} sh_shub_id_s;
+} sh_shub_id_u_t;
+#else
+typedef union sh_shub_id_u {
+	mmr_t	sh_shub_id_regval;
+	struct {
+		mmr_t	reserved_3    : 7;
+		mmr_t	ni_port       : 1;
+		mmr_t	reserved_2    : 3;
+		mmr_t	nodes_per_bit : 5;
+		mmr_t	reserved_1    : 2;
+		mmr_t	sharing_mode  : 2;
+		mmr_t	reserved_0    : 1;
+		mmr_t	node_id       : 11;
+		mmr_t	revision      : 4;
+		mmr_t	part_number   : 16;
+		mmr_t	manufacturer  : 11;
+		mmr_t	force1        : 1;
+	} sh_shub_id_s;
+} sh_shub_id_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT0"                     */
+/*         Shubs 0 - 63 Present. Used for invalidate generation         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present0_u {
+	mmr_t	sh_shubs_present0_regval;
+	struct {
+		mmr_t	shubs_present0 : 64;
+	} sh_shubs_present0_s;
+} sh_shubs_present0_u_t;
+#else
+typedef union sh_shubs_present0_u {
+	mmr_t	sh_shubs_present0_regval;
+	struct {
+		mmr_t	shubs_present0 : 64;
+	} sh_shubs_present0_s;
+} sh_shubs_present0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT1"                     */
+/*        Shubs 64 - 127 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present1_u {
+	mmr_t	sh_shubs_present1_regval;
+	struct {
+		mmr_t	shubs_present1 : 64;
+	} sh_shubs_present1_s;
+} sh_shubs_present1_u_t;
+#else
+typedef union sh_shubs_present1_u {
+	mmr_t	sh_shubs_present1_regval;
+	struct {
+		mmr_t	shubs_present1 : 64;
+	} sh_shubs_present1_s;
+} sh_shubs_present1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT2"                     */
+/*       Shubs 128 - 191 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present2_u {
+	mmr_t	sh_shubs_present2_regval;
+	struct {
+		mmr_t	shubs_present2 : 64;
+	} sh_shubs_present2_s;
+} sh_shubs_present2_u_t;
+#else
+typedef union sh_shubs_present2_u {
+	mmr_t	sh_shubs_present2_regval;
+	struct {
+		mmr_t	shubs_present2 : 64;
+	} sh_shubs_present2_s;
+} sh_shubs_present2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_SHUBS_PRESENT3"                     */
+/*       Shubs 192 - 255 Present. Used for invalidate generation        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_shubs_present3_u {
+	mmr_t	sh_shubs_present3_regval;
+	struct {
+		mmr_t	shubs_present3 : 64;
+	} sh_shubs_present3_s;
+} sh_shubs_present3_u_t;
+#else
+typedef union sh_shubs_present3_u {
+	mmr_t	sh_shubs_present3_regval;
+	struct {
+		mmr_t	shubs_present3 : 64;
+	} sh_shubs_present3_s;
+} sh_shubs_present3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_SOFT_RESET"                       */
+/*                           SHub Soft Reset                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_soft_reset_u {
+	mmr_t	sh_soft_reset_regval;
+	struct {
+		mmr_t	soft_reset  : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_soft_reset_s;
+} sh_soft_reset_u_t;
+#else
+typedef union sh_soft_reset_u {
+	mmr_t	sh_soft_reset_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	soft_reset  : 1;
+	} sh_soft_reset_s;
+} sh_soft_reset_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_FIRST_ERROR"                       */
+/*                    Shub Global First Error Flags                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_first_error_u {
+	mmr_t	sh_first_error_regval;
+	struct {
+		mmr_t	first_error : 19;
+		mmr_t	reserved_0  : 45;
+	} sh_first_error_s;
+} sh_first_error_u_t;
+#else
+typedef union sh_first_error_u {
+	mmr_t	sh_first_error_regval;
+	struct {
+		mmr_t	reserved_0  : 45;
+		mmr_t	first_error : 19;
+	} sh_first_error_s;
+} sh_first_error_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_II_HW_TIME_STAMP"                    */
+/*                     II hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_hw_time_stamp_u {
+	mmr_t	sh_ii_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_ii_hw_time_stamp_s;
+} sh_ii_hw_time_stamp_u_t;
+#else
+typedef union sh_ii_hw_time_stamp_u {
+	mmr_t	sh_ii_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_ii_hw_time_stamp_s;
+} sh_ii_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_LB_HW_TIME_STAMP"                    */
+/*                     LB hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_hw_time_stamp_u {
+	mmr_t	sh_lb_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_lb_hw_time_stamp_s;
+} sh_lb_hw_time_stamp_u_t;
+#else
+typedef union sh_lb_hw_time_stamp_u {
+	mmr_t	sh_lb_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_lb_hw_time_stamp_s;
+} sh_lb_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_COR_TIME_STAMP"                    */
+/*                   MD correctable error time stamp                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_cor_time_stamp_u {
+	mmr_t	sh_md_cor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_md_cor_time_stamp_s;
+} sh_md_cor_time_stamp_u_t;
+#else
+typedef union sh_md_cor_time_stamp_u {
+	mmr_t	sh_md_cor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_md_cor_time_stamp_s;
+} sh_md_cor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_HW_TIME_STAMP"                    */
+/*                     MD hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_hw_time_stamp_u {
+	mmr_t	sh_md_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_md_hw_time_stamp_s;
+} sh_md_hw_time_stamp_u_t;
+#else
+typedef union sh_md_hw_time_stamp_u {
+	mmr_t	sh_md_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_md_hw_time_stamp_s;
+} sh_md_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_UNCOR_TIME_STAMP"                   */
+/*                  MD uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_uncor_time_stamp_u {
+	mmr_t	sh_md_uncor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_md_uncor_time_stamp_s;
+} sh_md_uncor_time_stamp_u_t;
+#else
+typedef union sh_md_uncor_time_stamp_u {
+	mmr_t	sh_md_uncor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_md_uncor_time_stamp_s;
+} sh_md_uncor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PI_COR_TIME_STAMP"                    */
+/*                   PI correctable error time stamp                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_cor_time_stamp_u {
+	mmr_t	sh_pi_cor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_pi_cor_time_stamp_s;
+} sh_pi_cor_time_stamp_u_t;
+#else
+typedef union sh_pi_cor_time_stamp_u {
+	mmr_t	sh_pi_cor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_pi_cor_time_stamp_s;
+} sh_pi_cor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_HW_TIME_STAMP"                    */
+/*                     PI hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_hw_time_stamp_u {
+	mmr_t	sh_pi_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_pi_hw_time_stamp_s;
+} sh_pi_hw_time_stamp_u_t;
+#else
+typedef union sh_pi_hw_time_stamp_u {
+	mmr_t	sh_pi_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_pi_hw_time_stamp_s;
+} sh_pi_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PI_UNCOR_TIME_STAMP"                   */
+/*                  PI uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_uncor_time_stamp_u {
+	mmr_t	sh_pi_uncor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_pi_uncor_time_stamp_s;
+} sh_pi_uncor_time_stamp_u_t;
+#else
+typedef union sh_pi_uncor_time_stamp_u {
+	mmr_t	sh_pi_uncor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_pi_uncor_time_stamp_s;
+} sh_pi_uncor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ADV_TIME_STAMP"                  */
+/*                      Proc 0 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_adv_time_stamp_u {
+	mmr_t	sh_proc0_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc0_adv_time_stamp_s;
+} sh_proc0_adv_time_stamp_u_t;
+#else
+typedef union sh_proc0_adv_time_stamp_u {
+	mmr_t	sh_proc0_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc0_adv_time_stamp_s;
+} sh_proc0_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC0_ERR_TIME_STAMP"                  */
+/*                       Proc 0 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc0_err_time_stamp_u {
+	mmr_t	sh_proc0_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc0_err_time_stamp_s;
+} sh_proc0_err_time_stamp_u_t;
+#else
+typedef union sh_proc0_err_time_stamp_u {
+	mmr_t	sh_proc0_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc0_err_time_stamp_s;
+} sh_proc0_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ADV_TIME_STAMP"                  */
+/*                      Proc 1 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_adv_time_stamp_u {
+	mmr_t	sh_proc1_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc1_adv_time_stamp_s;
+} sh_proc1_adv_time_stamp_u_t;
+#else
+typedef union sh_proc1_adv_time_stamp_u {
+	mmr_t	sh_proc1_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc1_adv_time_stamp_s;
+} sh_proc1_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC1_ERR_TIME_STAMP"                  */
+/*                       Proc 1 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc1_err_time_stamp_u {
+	mmr_t	sh_proc1_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc1_err_time_stamp_s;
+} sh_proc1_err_time_stamp_u_t;
+#else
+typedef union sh_proc1_err_time_stamp_u {
+	mmr_t	sh_proc1_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc1_err_time_stamp_s;
+} sh_proc1_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ADV_TIME_STAMP"                  */
+/*                      Proc 2 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_adv_time_stamp_u {
+	mmr_t	sh_proc2_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc2_adv_time_stamp_s;
+} sh_proc2_adv_time_stamp_u_t;
+#else
+typedef union sh_proc2_adv_time_stamp_u {
+	mmr_t	sh_proc2_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc2_adv_time_stamp_s;
+} sh_proc2_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC2_ERR_TIME_STAMP"                  */
+/*                       Proc 2 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc2_err_time_stamp_u {
+	mmr_t	sh_proc2_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc2_err_time_stamp_s;
+} sh_proc2_err_time_stamp_u_t;
+#else
+typedef union sh_proc2_err_time_stamp_u {
+	mmr_t	sh_proc2_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc2_err_time_stamp_s;
+} sh_proc2_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ADV_TIME_STAMP"                  */
+/*                      Proc 3 advisory time stamp                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_adv_time_stamp_u {
+	mmr_t	sh_proc3_adv_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc3_adv_time_stamp_s;
+} sh_proc3_adv_time_stamp_u_t;
+#else
+typedef union sh_proc3_adv_time_stamp_u {
+	mmr_t	sh_proc3_adv_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc3_adv_time_stamp_s;
+} sh_proc3_adv_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROC3_ERR_TIME_STAMP"                  */
+/*                       Proc 3 error time stamp                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_proc3_err_time_stamp_u {
+	mmr_t	sh_proc3_err_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_proc3_err_time_stamp_s;
+} sh_proc3_err_time_stamp_u_t;
+#else
+typedef union sh_proc3_err_time_stamp_u {
+	mmr_t	sh_proc3_err_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_proc3_err_time_stamp_s;
+} sh_proc3_err_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_XN_COR_TIME_STAMP"                    */
+/*                   XN correctable error time stamp                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_cor_time_stamp_u {
+	mmr_t	sh_xn_cor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_xn_cor_time_stamp_s;
+} sh_xn_cor_time_stamp_u_t;
+#else
+typedef union sh_xn_cor_time_stamp_u {
+	mmr_t	sh_xn_cor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_xn_cor_time_stamp_s;
+} sh_xn_cor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_HW_TIME_STAMP"                    */
+/*                     XN hardware error time stamp                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_hw_time_stamp_u {
+	mmr_t	sh_xn_hw_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_xn_hw_time_stamp_s;
+} sh_xn_hw_time_stamp_u_t;
+#else
+typedef union sh_xn_hw_time_stamp_u {
+	mmr_t	sh_xn_hw_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_xn_hw_time_stamp_s;
+} sh_xn_hw_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_XN_UNCOR_TIME_STAMP"                   */
+/*                  XN uncorrectable error time stamp                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_uncor_time_stamp_u {
+	mmr_t	sh_xn_uncor_time_stamp_regval;
+	struct {
+		mmr_t	time        : 63;
+		mmr_t	valid       : 1;
+	} sh_xn_uncor_time_stamp_s;
+} sh_xn_uncor_time_stamp_u_t;
+#else
+typedef union sh_xn_uncor_time_stamp_u {
+	mmr_t	sh_xn_uncor_time_stamp_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	time        : 63;
+	} sh_xn_uncor_time_stamp_s;
+} sh_xn_uncor_time_stamp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_DEBUG_PORT"                       */
+/*                           SHub Debug Port                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_debug_port_u {
+	mmr_t	sh_debug_port_regval;
+	struct {
+		mmr_t	debug_nibble0 : 4;
+		mmr_t	debug_nibble1 : 4;
+		mmr_t	debug_nibble2 : 4;
+		mmr_t	debug_nibble3 : 4;
+		mmr_t	debug_nibble4 : 4;
+		mmr_t	debug_nibble5 : 4;
+		mmr_t	debug_nibble6 : 4;
+		mmr_t	debug_nibble7 : 4;
+		mmr_t	reserved_0    : 32;
+	} sh_debug_port_s;
+} sh_debug_port_u_t;
+#else
+typedef union sh_debug_port_u {
+	mmr_t	sh_debug_port_regval;
+	struct {
+		mmr_t	reserved_0    : 32;
+		mmr_t	debug_nibble7 : 4;
+		mmr_t	debug_nibble6 : 4;
+		mmr_t	debug_nibble5 : 4;
+		mmr_t	debug_nibble4 : 4;
+		mmr_t	debug_nibble3 : 4;
+		mmr_t	debug_nibble2 : 4;
+		mmr_t	debug_nibble1 : 4;
+		mmr_t	debug_nibble0 : 4;
+	} sh_debug_port_s;
+} sh_debug_port_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_II_DEBUG_DATA"                      */
+/*                            II Debug Data                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_debug_data_u {
+	mmr_t	sh_ii_debug_data_regval;
+	struct {
+		mmr_t	ii_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_ii_debug_data_s;
+} sh_ii_debug_data_u_t;
+#else
+typedef union sh_ii_debug_data_u {
+	mmr_t	sh_ii_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	ii_data     : 32;
+	} sh_ii_debug_data_s;
+} sh_ii_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_II_WRAP_DEBUG_DATA"                   */
+/*                      SHub II Wrapper Debug Data                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ii_wrap_debug_data_u {
+	mmr_t	sh_ii_wrap_debug_data_regval;
+	struct {
+		mmr_t	ii_wrap_data : 32;
+		mmr_t	reserved_0   : 32;
+	} sh_ii_wrap_debug_data_s;
+} sh_ii_wrap_debug_data_u_t;
+#else
+typedef union sh_ii_wrap_debug_data_u {
+	mmr_t	sh_ii_wrap_debug_data_regval;
+	struct {
+		mmr_t	reserved_0   : 32;
+		mmr_t	ii_wrap_data : 32;
+	} sh_ii_wrap_debug_data_s;
+} sh_ii_wrap_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_LB_DEBUG_DATA"                      */
+/*                          SHub LB Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_lb_debug_data_u {
+	mmr_t	sh_lb_debug_data_regval;
+	struct {
+		mmr_t	lb_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_lb_debug_data_s;
+} sh_lb_debug_data_u_t;
+#else
+typedef union sh_lb_debug_data_u {
+	mmr_t	sh_lb_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	lb_data     : 32;
+	} sh_lb_debug_data_s;
+} sh_lb_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MD_DEBUG_DATA"                      */
+/*                          SHub MD Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_debug_data_u {
+	mmr_t	sh_md_debug_data_regval;
+	struct {
+		mmr_t	md_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_md_debug_data_s;
+} sh_md_debug_data_u_t;
+#else
+typedef union sh_md_debug_data_u {
+	mmr_t	sh_md_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	md_data     : 32;
+	} sh_md_debug_data_s;
+} sh_md_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PI_DEBUG_DATA"                      */
+/*                          SHub PI Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_debug_data_u {
+	mmr_t	sh_pi_debug_data_regval;
+	struct {
+		mmr_t	pi_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_pi_debug_data_s;
+} sh_pi_debug_data_u_t;
+#else
+typedef union sh_pi_debug_data_u {
+	mmr_t	sh_pi_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	pi_data     : 32;
+	} sh_pi_debug_data_s;
+} sh_pi_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_XN_DEBUG_DATA"                      */
+/*                          SHub XN Debug Data                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_debug_data_u {
+	mmr_t	sh_xn_debug_data_regval;
+	struct {
+		mmr_t	xn_data     : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_xn_debug_data_s;
+} sh_xn_debug_data_u_t;
+#else
+typedef union sh_xn_debug_data_u {
+	mmr_t	sh_xn_debug_data_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	xn_data     : 32;
+	} sh_xn_debug_data_s;
+} sh_xn_debug_data_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_TSF_ARMED_STATE"                     */
+/*                Trigger sequencing facility arm state                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_armed_state_u {
+	mmr_t	sh_tsf_armed_state_regval;
+	struct {
+		mmr_t	state       : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_armed_state_s;
+} sh_tsf_armed_state_u_t;
+#else
+typedef union sh_tsf_armed_state_u {
+	mmr_t	sh_tsf_armed_state_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	state       : 8;
+	} sh_tsf_armed_state_s;
+} sh_tsf_armed_state_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_TSF_COUNTER_VALUE"                    */
+/*              Trigger sequencing facility counter value               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_counter_value_u {
+	mmr_t	sh_tsf_counter_value_regval;
+	struct {
+		mmr_t	count_32    : 32;
+		mmr_t	count_16    : 16;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_8a    : 8;
+	} sh_tsf_counter_value_s;
+} sh_tsf_counter_value_u_t;
+#else
+typedef union sh_tsf_counter_value_u {
+	mmr_t	sh_tsf_counter_value_regval;
+	struct {
+		mmr_t	count_8a    : 8;
+		mmr_t	count_8b    : 8;
+		mmr_t	count_16    : 16;
+		mmr_t	count_32    : 32;
+	} sh_tsf_counter_value_s;
+} sh_tsf_counter_value_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_TSF_TRIGGERED_STATE"                   */
+/*             Trigger sequencing facility triggered state              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_tsf_triggered_state_u {
+	mmr_t	sh_tsf_triggered_state_regval;
+	struct {
+		mmr_t	state       : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_tsf_triggered_state_s;
+} sh_tsf_triggered_state_u_t;
+#else
+typedef union sh_tsf_triggered_state_u {
+	mmr_t	sh_tsf_triggered_state_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	state       : 8;
+	} sh_tsf_triggered_state_s;
+} sh_tsf_triggered_state_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RDDATA"                       */
+/*                      Vector Reply Message Data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_rddata_u {
+	mmr_t	sh_vec_rddata_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_rddata_s;
+} sh_vec_rddata_u_t;
+#else
+typedef union sh_vec_rddata_u {
+	mmr_t	sh_vec_rddata_regval;
+	struct {
+		mmr_t	data        : 64;
+	} sh_vec_rddata_s;
+} sh_vec_rddata_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_RETURN"                       */
+/*                  Vector Reply Message Return Route                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_return_u {
+	mmr_t	sh_vec_return_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_return_s;
+} sh_vec_return_u_t;
+#else
+typedef union sh_vec_return_u {
+	mmr_t	sh_vec_return_regval;
+	struct {
+		mmr_t	route       : 64;
+	} sh_vec_return_s;
+} sh_vec_return_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_VEC_STATUS"                       */
+/*                     Vector Reply Message Status                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_vec_status_u {
+	mmr_t	sh_vec_status_regval;
+	struct {
+		mmr_t	type         : 3;
+		mmr_t	address      : 32;
+		mmr_t	pio_id       : 11;
+		mmr_t	source       : 14;
+		mmr_t	reserved_0   : 2;
+		mmr_t	overrun      : 1;
+		mmr_t	status_valid : 1;
+	} sh_vec_status_s;
+} sh_vec_status_u_t;
+#else
+typedef union sh_vec_status_u {
+	mmr_t	sh_vec_status_regval;
+	struct {
+		mmr_t	status_valid : 1;
+		mmr_t	overrun      : 1;
+		mmr_t	reserved_0   : 2;
+		mmr_t	source       : 14;
+		mmr_t	pio_id       : 11;
+		mmr_t	address      : 32;
+		mmr_t	type         : 3;
+	} sh_vec_status_s;
+} sh_vec_status_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT0_CONTROL"               */
+/*                    Performance Counter 0 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count0_control_u {
+	mmr_t	sh_performance_count0_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count0_control_s;
+} sh_performance_count0_control_u_t;
+#else
+typedef union sh_performance_count0_control_u {
+	mmr_t	sh_performance_count0_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count0_control_s;
+} sh_performance_count0_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT1_CONTROL"               */
+/*                    Performance Counter 1 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count1_control_u {
+	mmr_t	sh_performance_count1_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count1_control_s;
+} sh_performance_count1_control_u_t;
+#else
+typedef union sh_performance_count1_control_u {
+	mmr_t	sh_performance_count1_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count1_control_s;
+} sh_performance_count1_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT2_CONTROL"               */
+/*                    Performance Counter 2 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count2_control_u {
+	mmr_t	sh_performance_count2_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count2_control_s;
+} sh_performance_count2_control_u_t;
+#else
+typedef union sh_performance_count2_control_u {
+	mmr_t	sh_performance_count2_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count2_control_s;
+} sh_performance_count2_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT3_CONTROL"               */
+/*                    Performance Counter 3 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count3_control_u {
+	mmr_t	sh_performance_count3_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count3_control_s;
+} sh_performance_count3_control_u_t;
+#else
+typedef union sh_performance_count3_control_u {
+	mmr_t	sh_performance_count3_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count3_control_s;
+} sh_performance_count3_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT4_CONTROL"               */
+/*                    Performance Counter 4 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count4_control_u {
+	mmr_t	sh_performance_count4_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count4_control_s;
+} sh_performance_count4_control_u_t;
+#else
+typedef union sh_performance_count4_control_u {
+	mmr_t	sh_performance_count4_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count4_control_s;
+} sh_performance_count4_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT5_CONTROL"               */
+/*                    Performance Counter 5 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count5_control_u {
+	mmr_t	sh_performance_count5_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count5_control_s;
+} sh_performance_count5_control_u_t;
+#else
+typedef union sh_performance_count5_control_u {
+	mmr_t	sh_performance_count5_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count5_control_s;
+} sh_performance_count5_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT6_CONTROL"               */
+/*                    Performance Counter 6 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count6_control_u {
+	mmr_t	sh_performance_count6_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count6_control_s;
+} sh_performance_count6_control_u_t;
+#else
+typedef union sh_performance_count6_control_u {
+	mmr_t	sh_performance_count6_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count6_control_s;
+} sh_performance_count6_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_PERFORMANCE_COUNT7_CONTROL"               */
+/*                    Performance Counter 7 Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_count7_control_u {
+	mmr_t	sh_performance_count7_control_regval;
+	struct {
+		mmr_t	up_stimulus     : 5;
+		mmr_t	up_event        : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_mode         : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	reserved_0      : 45;
+	} sh_performance_count7_control_s;
+} sh_performance_count7_control_u_t;
+#else
+typedef union sh_performance_count7_control_u {
+	mmr_t	sh_performance_count7_control_regval;
+	struct {
+		mmr_t	reserved_0      : 45;
+		mmr_t	peak_det_enable : 1;
+		mmr_t	dec_enable      : 1;
+		mmr_t	inc_enable      : 1;
+		mmr_t	dn_mode         : 1;
+		mmr_t	dn_polarity     : 1;
+		mmr_t	dn_event        : 1;
+		mmr_t	dn_stimulus     : 5;
+		mmr_t	up_mode         : 1;
+		mmr_t	up_polarity     : 1;
+		mmr_t	up_event        : 1;
+		mmr_t	up_stimulus     : 5;
+	} sh_performance_count7_control_s;
+} sh_performance_count7_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_DN_CONTROL"                   */
+/*                     Profile Counter Down Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_dn_control_u {
+	mmr_t	sh_profile_dn_control_regval;
+	struct {
+		mmr_t	stimulus    : 5;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	mode        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_dn_control_s;
+} sh_profile_dn_control_u_t;
+#else
+typedef union sh_profile_dn_control_u {
+	mmr_t	sh_profile_dn_control_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	mode        : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	stimulus    : 5;
+	} sh_profile_dn_control_s;
+} sh_profile_dn_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PROFILE_PEAK_CONTROL"                  */
+/*                     Profile Counter Peak Control                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_peak_control_u {
+	mmr_t	sh_profile_peak_control_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	stimulus    : 1;
+		mmr_t	reserved_1  : 1;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	reserved_2  : 57;
+	} sh_profile_peak_control_s;
+} sh_profile_peak_control_u_t;
+#else
+typedef union sh_profile_peak_control_u {
+	mmr_t	sh_profile_peak_control_regval;
+	struct {
+		mmr_t	reserved_2  : 57;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	reserved_1  : 1;
+		mmr_t	stimulus    : 1;
+		mmr_t	reserved_0  : 3;
+	} sh_profile_peak_control_s;
+} sh_profile_peak_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PROFILE_RANGE"                      */
+/*                        Profile Counter Range                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_range_u {
+	mmr_t	sh_profile_range_regval;
+	struct {
+		mmr_t	range0      : 8;
+		mmr_t	range1      : 8;
+		mmr_t	range2      : 8;
+		mmr_t	range3      : 8;
+		mmr_t	range4      : 8;
+		mmr_t	range5      : 8;
+		mmr_t	range6      : 8;
+		mmr_t	range7      : 8;
+	} sh_profile_range_s;
+} sh_profile_range_u_t;
+#else
+typedef union sh_profile_range_u {
+	mmr_t	sh_profile_range_regval;
+	struct {
+		mmr_t	range7      : 8;
+		mmr_t	range6      : 8;
+		mmr_t	range5      : 8;
+		mmr_t	range4      : 8;
+		mmr_t	range3      : 8;
+		mmr_t	range2      : 8;
+		mmr_t	range1      : 8;
+		mmr_t	range0      : 8;
+	} sh_profile_range_s;
+} sh_profile_range_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PROFILE_UP_CONTROL"                   */
+/*                      Profile Counter Up Control                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_up_control_u {
+	mmr_t	sh_profile_up_control_regval;
+	struct {
+		mmr_t	stimulus    : 5;
+		mmr_t	event       : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	mode        : 1;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_up_control_s;
+} sh_profile_up_control_u_t;
+#else
+typedef union sh_profile_up_control_u {
+	mmr_t	sh_profile_up_control_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	mode        : 1;
+		mmr_t	polarity    : 1;
+		mmr_t	event       : 1;
+		mmr_t	stimulus    : 5;
+	} sh_profile_up_control_s;
+} sh_profile_up_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER0"                  */
+/*                        Performance Counter 0                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter0_u {
+	mmr_t	sh_performance_counter0_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter0_s;
+} sh_performance_counter0_u_t;
+#else
+typedef union sh_performance_counter0_u {
+	mmr_t	sh_performance_counter0_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter0_s;
+} sh_performance_counter0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER1"                  */
+/*                        Performance Counter 1                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter1_u {
+	mmr_t	sh_performance_counter1_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter1_s;
+} sh_performance_counter1_u_t;
+#else
+typedef union sh_performance_counter1_u {
+	mmr_t	sh_performance_counter1_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter1_s;
+} sh_performance_counter1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER2"                  */
+/*                        Performance Counter 2                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter2_u {
+	mmr_t	sh_performance_counter2_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter2_s;
+} sh_performance_counter2_u_t;
+#else
+typedef union sh_performance_counter2_u {
+	mmr_t	sh_performance_counter2_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter2_s;
+} sh_performance_counter2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER3"                  */
+/*                        Performance Counter 3                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter3_u {
+	mmr_t	sh_performance_counter3_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter3_s;
+} sh_performance_counter3_u_t;
+#else
+typedef union sh_performance_counter3_u {
+	mmr_t	sh_performance_counter3_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter3_s;
+} sh_performance_counter3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER4"                  */
+/*                        Performance Counter 4                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter4_u {
+	mmr_t	sh_performance_counter4_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter4_s;
+} sh_performance_counter4_u_t;
+#else
+typedef union sh_performance_counter4_u {
+	mmr_t	sh_performance_counter4_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter4_s;
+} sh_performance_counter4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER5"                  */
+/*                        Performance Counter 5                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter5_u {
+	mmr_t	sh_performance_counter5_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter5_s;
+} sh_performance_counter5_u_t;
+#else
+typedef union sh_performance_counter5_u {
+	mmr_t	sh_performance_counter5_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter5_s;
+} sh_performance_counter5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER6"                  */
+/*                        Performance Counter 6                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter6_u {
+	mmr_t	sh_performance_counter6_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter6_s;
+} sh_performance_counter6_u_t;
+#else
+typedef union sh_performance_counter6_u {
+	mmr_t	sh_performance_counter6_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter6_s;
+} sh_performance_counter6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_PERFORMANCE_COUNTER7"                  */
+/*                        Performance Counter 7                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_performance_counter7_u {
+	mmr_t	sh_performance_counter7_regval;
+	struct {
+		mmr_t	count       : 32;
+		mmr_t	reserved_0  : 32;
+	} sh_performance_counter7_s;
+} sh_performance_counter7_u_t;
+#else
+typedef union sh_performance_counter7_u {
+	mmr_t	sh_performance_counter7_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	count       : 32;
+	} sh_performance_counter7_s;
+} sh_performance_counter7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PROFILE_COUNTER"                     */
+/*                           Profile Counter                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_counter_u {
+	mmr_t	sh_profile_counter_regval;
+	struct {
+		mmr_t	counter     : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_counter_s;
+} sh_profile_counter_u_t;
+#else
+typedef union sh_profile_counter_u {
+	mmr_t	sh_profile_counter_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	counter     : 8;
+	} sh_profile_counter_s;
+} sh_profile_counter_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_PROFILE_PEAK"                      */
+/*                         Profile Peak Counter                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_profile_peak_u {
+	mmr_t	sh_profile_peak_regval;
+	struct {
+		mmr_t	counter     : 8;
+		mmr_t	reserved_0  : 56;
+	} sh_profile_peak_s;
+} sh_profile_peak_u_t;
+#else
+typedef union sh_profile_peak_u {
+	mmr_t	sh_profile_peak_regval;
+	struct {
+		mmr_t	reserved_0  : 56;
+		mmr_t	counter     : 8;
+	} sh_profile_peak_s;
+} sh_profile_peak_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_0"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ptc_0_u {
+	mmr_t	sh_ptc_0_regval;
+	struct {
+		mmr_t	a           : 1;
+		mmr_t	reserved_0  : 1;
+		mmr_t	ps          : 6;
+		mmr_t	rid         : 24;
+		mmr_t	reserved_1  : 31;
+		mmr_t	start       : 1;
+	} sh_ptc_0_s;
+} sh_ptc_0_u_t;
+#else
+typedef union sh_ptc_0_u {
+	mmr_t	sh_ptc_0_regval;
+	struct {
+		mmr_t	start       : 1;
+		mmr_t	reserved_1  : 31;
+		mmr_t	rid         : 24;
+		mmr_t	ps          : 6;
+		mmr_t	reserved_0  : 1;
+		mmr_t	a           : 1;
+	} sh_ptc_0_s;
+} sh_ptc_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_PTC_1"                          */
+/*       Puge Translation Cache Message Configuration Information       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ptc_1_u {
+	mmr_t	sh_ptc_1_regval;
+	struct {
+		mmr_t	reserved_0  : 12;
+		mmr_t	vpn         : 49;
+		mmr_t	reserved_1  : 2;
+		mmr_t	start       : 1;
+	} sh_ptc_1_s;
+} sh_ptc_1_u_t;
+#else
+typedef union sh_ptc_1_u {
+	mmr_t	sh_ptc_1_regval;
+	struct {
+		mmr_t	start       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	vpn         : 49;
+		mmr_t	reserved_0  : 12;
+	} sh_ptc_1_s;
+} sh_ptc_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_PTC_PARMS"                        */
+/*                       PTC Time-out parmaeters                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_ptc_parms_u {
+	mmr_t	sh_ptc_parms_regval;
+	struct {
+		mmr_t	ptc_to_wrap : 24;
+		mmr_t	ptc_to_val  : 12;
+		mmr_t	reserved_0  : 28;
+	} sh_ptc_parms_s;
+} sh_ptc_parms_u_t;
+#else
+typedef union sh_ptc_parms_u {
+	mmr_t	sh_ptc_parms_regval;
+	struct {
+		mmr_t	reserved_0  : 28;
+		mmr_t	ptc_to_val  : 12;
+		mmr_t	ptc_to_wrap : 24;
+	} sh_ptc_parms_s;
+} sh_ptc_parms_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPA"                        */
+/*                  RTC Compare Value for Processor A                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpa_u {
+	mmr_t	sh_int_cmpa_regval;
+	struct {
+		mmr_t	real_time_cmpa : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpa_s;
+} sh_int_cmpa_u_t;
+#else
+typedef union sh_int_cmpa_u {
+	mmr_t	sh_int_cmpa_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpa : 55;
+	} sh_int_cmpa_s;
+} sh_int_cmpa_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPB"                        */
+/*                  RTC Compare Value for Processor B                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpb_u {
+	mmr_t	sh_int_cmpb_regval;
+	struct {
+		mmr_t	real_time_cmpb : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpb_s;
+} sh_int_cmpb_u_t;
+#else
+typedef union sh_int_cmpb_u {
+	mmr_t	sh_int_cmpb_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpb : 55;
+	} sh_int_cmpb_s;
+} sh_int_cmpb_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPC"                        */
+/*                  RTC Compare Value for Processor C                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpc_u {
+	mmr_t	sh_int_cmpc_regval;
+	struct {
+		mmr_t	real_time_cmpc : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpc_s;
+} sh_int_cmpc_u_t;
+#else
+typedef union sh_int_cmpc_u {
+	mmr_t	sh_int_cmpc_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpc : 55;
+	} sh_int_cmpc_s;
+} sh_int_cmpc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_CMPD"                        */
+/*                  RTC Compare Value for Processor D                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_cmpd_u {
+	mmr_t	sh_int_cmpd_regval;
+	struct {
+		mmr_t	real_time_cmpd : 55;
+		mmr_t	reserved_0     : 9;
+	} sh_int_cmpd_s;
+} sh_int_cmpd_u_t;
+#else
+typedef union sh_int_cmpd_u {
+	mmr_t	sh_int_cmpd_regval;
+	struct {
+		mmr_t	reserved_0     : 9;
+		mmr_t	real_time_cmpd : 55;
+	} sh_int_cmpd_s;
+} sh_int_cmpd_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_INT_PROF"                        */
+/*                      Profile Compare Registers                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_int_prof_u {
+	mmr_t	sh_int_prof_regval;
+	struct {
+		mmr_t	profile_compare : 32;
+		mmr_t	reserved_0      : 32;
+	} sh_int_prof_s;
+} sh_int_prof_u_t;
+#else
+typedef union sh_int_prof_u {
+	mmr_t	sh_int_prof_regval;
+	struct {
+		mmr_t	reserved_0      : 32;
+		mmr_t	profile_compare : 32;
+	} sh_int_prof_s;
+} sh_int_prof_u_t;
+#endif
+
+/* ==================================================================== */
+/*                          Register "SH_RTC"                           */
+/*                           Real-time Clock                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_rtc_u {
+	mmr_t	sh_rtc_regval;
+	struct {
+		mmr_t	real_time_clock : 55;
+		mmr_t	reserved_0      : 9;
+	} sh_rtc_s;
+} sh_rtc_u_t;
+#else
+typedef union sh_rtc_u {
+	mmr_t	sh_rtc_regval;
+	struct {
+		mmr_t	reserved_0      : 9;
+		mmr_t	real_time_clock : 55;
+	} sh_rtc_s;
+} sh_rtc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH0"                        */
+/*                          Scratch Register 0                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch0_u {
+	mmr_t	sh_scratch0_regval;
+	struct {
+		mmr_t	scratch0    : 64;
+	} sh_scratch0_s;
+} sh_scratch0_u_t;
+#else
+typedef union sh_scratch0_u {
+	mmr_t	sh_scratch0_regval;
+	struct {
+		mmr_t	scratch0    : 64;
+	} sh_scratch0_s;
+} sh_scratch0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH1"                        */
+/*                          Scratch Register 1                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch1_u {
+	mmr_t	sh_scratch1_regval;
+	struct {
+		mmr_t	scratch1    : 64;
+	} sh_scratch1_s;
+} sh_scratch1_u_t;
+#else
+typedef union sh_scratch1_u {
+	mmr_t	sh_scratch1_regval;
+	struct {
+		mmr_t	scratch1    : 64;
+	} sh_scratch1_s;
+} sh_scratch1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH2"                        */
+/*                          Scratch Register 2                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch2_u {
+	mmr_t	sh_scratch2_regval;
+	struct {
+		mmr_t	scratch2    : 64;
+	} sh_scratch2_s;
+} sh_scratch2_u_t;
+#else
+typedef union sh_scratch2_u {
+	mmr_t	sh_scratch2_regval;
+	struct {
+		mmr_t	scratch2    : 64;
+	} sh_scratch2_s;
+} sh_scratch2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH3"                        */
+/*                          Scratch Register 3                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch3_u {
+	mmr_t	sh_scratch3_regval;
+	struct {
+		mmr_t	scratch3    : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_scratch3_s;
+} sh_scratch3_u_t;
+#else
+typedef union sh_scratch3_u {
+	mmr_t	sh_scratch3_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	scratch3    : 1;
+	} sh_scratch3_s;
+} sh_scratch3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                        Register "SH_SCRATCH4"                        */
+/*                          Scratch Register 4                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_scratch4_u {
+	mmr_t	sh_scratch4_regval;
+	struct {
+		mmr_t	scratch4    : 1;
+		mmr_t	reserved_0  : 63;
+	} sh_scratch4_s;
+} sh_scratch4_u_t;
+#else
+typedef union sh_scratch4_u {
+	mmr_t	sh_scratch4_regval;
+	struct {
+		mmr_t	reserved_0  : 63;
+		mmr_t	scratch4    : 1;
+	} sh_scratch4_s;
+} sh_scratch4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_MESSAGE_CONTROL"                   */
+/*               Coherent Request Buffer Message Control                */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_message_control_u {
+	mmr_t	sh_crb_message_control_regval;
+	struct {
+		mmr_t	system_coherence_enable           : 1;
+		mmr_t	local_speculative_message_enable  : 1;
+		mmr_t	remote_speculative_message_enable : 1;
+		mmr_t	message_color                     : 1;
+		mmr_t	message_color_enable              : 1;
+		mmr_t	rrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	wrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	irb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	rrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	wrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	suppress_bogus_writes             : 1;
+		mmr_t	enable_ivack_consolidation        : 1;
+		mmr_t	reserved_0                        : 20;
+		mmr_t	ivack_stall_count                 : 16;
+		mmr_t	ivack_throttle_control            : 16;
+	} sh_crb_message_control_s;
+} sh_crb_message_control_u_t;
+#else
+typedef union sh_crb_message_control_u {
+	mmr_t	sh_crb_message_control_regval;
+	struct {
+		mmr_t	ivack_throttle_control            : 16;
+		mmr_t	ivack_stall_count                 : 16;
+		mmr_t	reserved_0                        : 20;
+		mmr_t	enable_ivack_consolidation        : 1;
+		mmr_t	suppress_bogus_writes             : 1;
+		mmr_t	wrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	rrb_attribute_mismatch_xb_enable  : 1;
+		mmr_t	irb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	wrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	rrb_attribute_mismatch_fsb_enable : 1;
+		mmr_t	message_color_enable              : 1;
+		mmr_t	message_color                     : 1;
+		mmr_t	remote_speculative_message_enable : 1;
+		mmr_t	local_speculative_message_enable  : 1;
+		mmr_t	system_coherence_enable           : 1;
+	} sh_crb_message_control_s;
+} sh_crb_message_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_CRB_NACK_LIMIT"                     */
+/*                            CRB Nack Limit                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_nack_limit_u {
+	mmr_t	sh_crb_nack_limit_regval;
+	struct {
+		mmr_t	limit       : 12;
+		mmr_t	pri_freq    : 4;
+		mmr_t	reserved_0  : 47;
+		mmr_t	enable      : 1;
+	} sh_crb_nack_limit_s;
+} sh_crb_nack_limit_u_t;
+#else
+typedef union sh_crb_nack_limit_u {
+	mmr_t	sh_crb_nack_limit_regval;
+	struct {
+		mmr_t	enable      : 1;
+		mmr_t	reserved_0  : 47;
+		mmr_t	pri_freq    : 4;
+		mmr_t	limit       : 12;
+	} sh_crb_nack_limit_s;
+} sh_crb_nack_limit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_CRB_TIMEOUT_PRESCALE"                  */
+/*               Coherent Request Buffer Timeout Prescale               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_timeout_prescale_u {
+	mmr_t	sh_crb_timeout_prescale_regval;
+	struct {
+		mmr_t	scaling_factor : 32;
+		mmr_t	reserved_0     : 32;
+	} sh_crb_timeout_prescale_s;
+} sh_crb_timeout_prescale_u_t;
+#else
+typedef union sh_crb_timeout_prescale_u {
+	mmr_t	sh_crb_timeout_prescale_regval;
+	struct {
+		mmr_t	reserved_0     : 32;
+		mmr_t	scaling_factor : 32;
+	} sh_crb_timeout_prescale_s;
+} sh_crb_timeout_prescale_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_CRB_TIMEOUT_SKID"                    */
+/*              Coherent Request Buffer Timeout Skid Limit              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_crb_timeout_skid_u {
+	mmr_t	sh_crb_timeout_skid_regval;
+	struct {
+		mmr_t	skid             : 6;
+		mmr_t	reserved_0       : 57;
+		mmr_t	reset_skid_count : 1;
+	} sh_crb_timeout_skid_s;
+} sh_crb_timeout_skid_u_t;
+#else
+typedef union sh_crb_timeout_skid_u {
+	mmr_t	sh_crb_timeout_skid_regval;
+	struct {
+		mmr_t	reset_skid_count : 1;
+		mmr_t	reserved_0       : 57;
+		mmr_t	skid             : 6;
+	} sh_crb_timeout_skid_s;
+} sh_crb_timeout_skid_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_0"                  */
+/*                    Memory Write Status for CPU 0                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_0_u {
+	mmr_t	sh_memory_write_status_0_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 58;
+	} sh_memory_write_status_0_s;
+} sh_memory_write_status_0_u_t;
+#else
+typedef union sh_memory_write_status_0_u {
+	mmr_t	sh_memory_write_status_0_regval;
+	struct {
+		mmr_t	reserved_0          : 58;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_0_s;
+} sh_memory_write_status_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MEMORY_WRITE_STATUS_1"                  */
+/*                    Memory Write Status for CPU 1                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_1_u {
+	mmr_t	sh_memory_write_status_1_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 58;
+	} sh_memory_write_status_1_s;
+} sh_memory_write_status_1_u_t;
+#else
+typedef union sh_memory_write_status_1_u {
+	mmr_t	sh_memory_write_status_1_regval;
+	struct {
+		mmr_t	reserved_0          : 58;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_1_s;
+} sh_memory_write_status_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_0"                   */
+/*                      PIO Write Status for CPU 0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_write_status_0_u {
+	mmr_t	sh_pio_write_status_0_regval;
+	struct {
+		mmr_t	multi_write_error   : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	write_error         : 1;
+		mmr_t	write_error_address : 47;
+		mmr_t	reserved_0          : 6;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_1          : 1;
+		mmr_t	writes_ok           : 1;
+	} sh_pio_write_status_0_s;
+} sh_pio_write_status_0_u_t;
+#else
+typedef union sh_pio_write_status_0_u {
+	mmr_t	sh_pio_write_status_0_regval;
+	struct {
+		mmr_t	writes_ok           : 1;
+		mmr_t	reserved_1          : 1;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 6;
+		mmr_t	write_error_address : 47;
+		mmr_t	write_error         : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	multi_write_error   : 1;
+	} sh_pio_write_status_0_s;
+} sh_pio_write_status_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_PIO_WRITE_STATUS_1"                   */
+/*                      PIO Write Status for CPU 1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_write_status_1_u {
+	mmr_t	sh_pio_write_status_1_regval;
+	struct {
+		mmr_t	multi_write_error   : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	write_error         : 1;
+		mmr_t	write_error_address : 47;
+		mmr_t	reserved_0          : 6;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_1          : 1;
+		mmr_t	writes_ok           : 1;
+	} sh_pio_write_status_1_s;
+} sh_pio_write_status_1_u_t;
+#else
+typedef union sh_pio_write_status_1_u {
+	mmr_t	sh_pio_write_status_1_regval;
+	struct {
+		mmr_t	writes_ok           : 1;
+		mmr_t	reserved_1          : 1;
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 6;
+		mmr_t	write_error_address : 47;
+		mmr_t	write_error         : 1;
+		mmr_t	write_deadlock      : 1;
+		mmr_t	multi_write_error   : 1;
+	} sh_pio_write_status_1_s;
+} sh_pio_write_status_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_0"             */
+/*            Memory Write Status for CPU 0. OS access only             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_non_user_0_u {
+	mmr_t	sh_memory_write_status_non_user_0_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 57;
+		mmr_t	clear               : 1;
+	} sh_memory_write_status_non_user_0_s;
+} sh_memory_write_status_non_user_0_u_t;
+#else
+typedef union sh_memory_write_status_non_user_0_u {
+	mmr_t	sh_memory_write_status_non_user_0_regval;
+	struct {
+		mmr_t	clear               : 1;
+		mmr_t	reserved_0          : 57;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_non_user_0_s;
+} sh_memory_write_status_non_user_0_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MEMORY_WRITE_STATUS_NON_USER_1"             */
+/*            Memory Write Status for CPU 1. OS access only             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_memory_write_status_non_user_1_u {
+	mmr_t	sh_memory_write_status_non_user_1_regval;
+	struct {
+		mmr_t	pending_write_count : 6;
+		mmr_t	reserved_0          : 57;
+		mmr_t	clear               : 1;
+	} sh_memory_write_status_non_user_1_s;
+} sh_memory_write_status_non_user_1_u_t;
+#else
+typedef union sh_memory_write_status_non_user_1_u {
+	mmr_t	sh_memory_write_status_non_user_1_regval;
+	struct {
+		mmr_t	clear               : 1;
+		mmr_t	reserved_0          : 57;
+		mmr_t	pending_write_count : 6;
+	} sh_memory_write_status_non_user_1_s;
+} sh_memory_write_status_non_user_1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_ERR"                       */
+/*                  Error capture for bist read errors                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mmrbist_err_u {
+	mmr_t	sh_mmrbist_err_regval;
+	struct {
+		mmr_t	addr              : 33;
+		mmr_t	reserved_0        : 3;
+		mmr_t	detected          : 1;
+		mmr_t	multiple_detected : 1;
+		mmr_t	cancelled         : 1;
+		mmr_t	reserved_1        : 25;
+	} sh_mmrbist_err_s;
+} sh_mmrbist_err_u_t;
+#else
+typedef union sh_mmrbist_err_u {
+	mmr_t	sh_mmrbist_err_regval;
+	struct {
+		mmr_t	reserved_1        : 25;
+		mmr_t	cancelled         : 1;
+		mmr_t	multiple_detected : 1;
+		mmr_t	detected          : 1;
+		mmr_t	reserved_0        : 3;
+		mmr_t	addr              : 33;
+	} sh_mmrbist_err_s;
+} sh_mmrbist_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_LOWER"                   */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_misc_err_hdr_lower_u {
+	mmr_t	sh_misc_err_hdr_lower_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	valid       : 1;
+	} sh_misc_err_hdr_lower_s;
+} sh_misc_err_hdr_lower_u_t;
+#else
+typedef union sh_misc_err_hdr_lower_u {
+	mmr_t	sh_misc_err_hdr_lower_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_misc_err_hdr_lower_s;
+} sh_misc_err_hdr_lower_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MISC_ERR_HDR_UPPER"                   */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_misc_err_hdr_upper_u {
+	mmr_t	sh_misc_err_hdr_upper_regval;
+	struct {
+		mmr_t	dir_protocol  : 1;
+		mmr_t	illegal_cmd   : 1;
+		mmr_t	nonexist_addr : 1;
+		mmr_t	rmw_uc        : 1;
+		mmr_t	rmw_cor       : 1;
+		mmr_t	dir_acc       : 1;
+		mmr_t	pi_pkt_size   : 1;
+		mmr_t	xn_pkt_size   : 1;
+		mmr_t	reserved_0    : 12;
+		mmr_t	echo          : 9;
+		mmr_t	reserved_1    : 35;
+	} sh_misc_err_hdr_upper_s;
+} sh_misc_err_hdr_upper_u_t;
+#else
+typedef union sh_misc_err_hdr_upper_u {
+	mmr_t	sh_misc_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_1    : 35;
+		mmr_t	echo          : 9;
+		mmr_t	reserved_0    : 12;
+		mmr_t	xn_pkt_size   : 1;
+		mmr_t	pi_pkt_size   : 1;
+		mmr_t	dir_acc       : 1;
+		mmr_t	rmw_cor       : 1;
+		mmr_t	rmw_uc        : 1;
+		mmr_t	nonexist_addr : 1;
+		mmr_t	illegal_cmd   : 1;
+		mmr_t	dir_protocol  : 1;
+	} sh_misc_err_hdr_upper_s;
+} sh_misc_err_hdr_upper_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_uc_err_hdr_lower_u {
+	mmr_t	sh_dir_uc_err_hdr_lower_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	valid       : 1;
+	} sh_dir_uc_err_hdr_lower_s;
+} sh_dir_uc_err_hdr_lower_u_t;
+#else
+typedef union sh_dir_uc_err_hdr_lower_u {
+	mmr_t	sh_dir_uc_err_hdr_lower_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_dir_uc_err_hdr_lower_s;
+} sh_dir_uc_err_hdr_lower_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_DIR_UC_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_uc_err_hdr_upper_u {
+	mmr_t	sh_dir_uc_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	dir_uc      : 1;
+		mmr_t	reserved_1  : 16;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_2  : 35;
+	} sh_dir_uc_err_hdr_upper_s;
+} sh_dir_uc_err_hdr_upper_u_t;
+#else
+typedef union sh_dir_uc_err_hdr_upper_u {
+	mmr_t	sh_dir_uc_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_2  : 35;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_1  : 16;
+		mmr_t	dir_uc      : 1;
+		mmr_t	reserved_0  : 3;
+	} sh_dir_uc_err_hdr_upper_s;
+} sh_dir_uc_err_hdr_upper_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_LOWER"                  */
+/*                       Header capture register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_cor_err_hdr_lower_u {
+	mmr_t	sh_dir_cor_err_hdr_lower_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	reserved_1  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	valid       : 1;
+	} sh_dir_cor_err_hdr_lower_s;
+} sh_dir_cor_err_hdr_lower_u_t;
+#else
+typedef union sh_dir_cor_err_hdr_lower_u {
+	mmr_t	sh_dir_cor_err_hdr_lower_regval;
+	struct {
+		mmr_t	valid       : 1;
+		mmr_t	reserved_2  : 2;
+		mmr_t	write       : 1;
+		mmr_t	reserved_1  : 2;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_dir_cor_err_hdr_lower_s;
+} sh_dir_cor_err_hdr_lower_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_DIR_COR_ERR_HDR_UPPER"                  */
+/*           Error header capture packet and protocol errors            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_dir_cor_err_hdr_upper_u {
+	mmr_t	sh_dir_cor_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_0  : 8;
+		mmr_t	dir_cor     : 1;
+		mmr_t	reserved_1  : 11;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_2  : 35;
+	} sh_dir_cor_err_hdr_upper_s;
+} sh_dir_cor_err_hdr_upper_u_t;
+#else
+typedef union sh_dir_cor_err_hdr_upper_u {
+	mmr_t	sh_dir_cor_err_hdr_upper_regval;
+	struct {
+		mmr_t	reserved_2  : 35;
+		mmr_t	echo        : 9;
+		mmr_t	reserved_1  : 11;
+		mmr_t	dir_cor     : 1;
+		mmr_t	reserved_0  : 8;
+	} sh_dir_cor_err_hdr_upper_s;
+} sh_dir_cor_err_hdr_upper_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_SUMMARY"                    */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_error_summary_u {
+	mmr_t	sh_mem_error_summary_regval;
+	struct {
+		mmr_t	illegal_cmd           : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	reserved_5            : 29;
+	} sh_mem_error_summary_s;
+} sh_mem_error_summary_u_t;
+#else
+typedef union sh_mem_error_summary_u {
+	mmr_t	sh_mem_error_summary_regval;
+	struct {
+		mmr_t	reserved_5            : 29;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	illegal_cmd           : 1;
+	} sh_mem_error_summary_s;
+} sh_mem_error_summary_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MEM_ERROR_OVERFLOW"                   */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_error_overflow_u {
+	mmr_t	sh_mem_error_overflow_regval;
+	struct {
+		mmr_t	illegal_cmd           : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	reserved_5            : 29;
+	} sh_mem_error_overflow_s;
+} sh_mem_error_overflow_u_t;
+#else
+typedef union sh_mem_error_overflow_u {
+	mmr_t	sh_mem_error_overflow_regval;
+	struct {
+		mmr_t	reserved_5            : 29;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	illegal_cmd           : 1;
+	} sh_mem_error_overflow_s;
+} sh_mem_error_overflow_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_ERROR_MASK"                     */
+/*                          Memory error flags                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_error_mask_u {
+	mmr_t	sh_mem_error_mask_regval;
+	struct {
+		mmr_t	illegal_cmd           : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	reserved_5            : 29;
+	} sh_mem_error_mask_s;
+} sh_mem_error_mask_u_t;
+#else
+typedef union sh_mem_error_mask_u {
+	mmr_t	sh_mem_error_mask_regval;
+	struct {
+		mmr_t	reserved_5            : 29;
+		mmr_t	xn_pkt_size           : 1;
+		mmr_t	pi_pkt_size           : 1;
+		mmr_t	red_black_err_timeout : 1;
+		mmr_t	xn_request_overflow   : 1;
+		mmr_t	pi_request_overflow   : 1;
+		mmr_t	xn_reply_overflow     : 1;
+		mmr_t	pi_reply_overflow     : 1;
+		mmr_t	reserved_4            : 1;
+		mmr_t	dqrs_int_hw           : 1;
+		mmr_t	dqrs_int_cor          : 1;
+		mmr_t	dqrs_int_uc           : 1;
+		mmr_t	reserved_3            : 1;
+		mmr_t	dqrp_int_hw           : 1;
+		mmr_t	dqrp_int_cor          : 1;
+		mmr_t	dqrp_int_uc           : 1;
+		mmr_t	reserved_2            : 1;
+		mmr_t	dqls_int_hw           : 1;
+		mmr_t	dqls_int_cor          : 1;
+		mmr_t	dqls_int_uc           : 1;
+		mmr_t	reserved_1            : 1;
+		mmr_t	dqlp_int_hw           : 1;
+		mmr_t	dqlp_int_cor          : 1;
+		mmr_t	dqlp_int_uc           : 1;
+		mmr_t	reserved_0            : 1;
+		mmr_t	dir_acc               : 1;
+		mmr_t	acy_int_hw            : 1;
+		mmr_t	acx_int_hw            : 1;
+		mmr_t	dqrp_dir_cor          : 1;
+		mmr_t	dqrp_dir_uc           : 1;
+		mmr_t	dqlp_dir_cor          : 1;
+		mmr_t	dqlp_dir_uc           : 1;
+		mmr_t	dqrp_dir_perr         : 1;
+		mmr_t	dqlp_dir_perr         : 1;
+		mmr_t	nonexist_addr         : 1;
+		mmr_t	illegal_cmd           : 1;
+	} sh_mem_error_mask_s;
+} sh_mem_error_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_dimm_cfg_u {
+	mmr_t	sh_x_dimm_cfg_regval;
+	struct {
+		mmr_t	dimm0_size  : 3;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	reserved_3  : 1;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_4  : 28;
+	} sh_x_dimm_cfg_s;
+} sh_x_dimm_cfg_u_t;
+#else
+typedef union sh_x_dimm_cfg_u {
+	mmr_t	sh_x_dimm_cfg_regval;
+	struct {
+		mmr_t	reserved_4  : 28;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_3  : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_size  : 3;
+	} sh_x_dimm_cfg_s;
+} sh_x_dimm_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DIMM_CFG"                       */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_dimm_cfg_u {
+	mmr_t	sh_y_dimm_cfg_regval;
+	struct {
+		mmr_t	dimm0_size  : 3;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	reserved_3  : 1;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_4  : 28;
+	} sh_y_dimm_cfg_s;
+} sh_y_dimm_cfg_u_t;
+#else
+typedef union sh_y_dimm_cfg_u {
+	mmr_t	sh_y_dimm_cfg_regval;
+	struct {
+		mmr_t	reserved_4  : 28;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_3  : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_size  : 3;
+	} sh_y_dimm_cfg_s;
+} sh_y_dimm_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_JNR_DIMM_CFG"                      */
+/*                       AC Mem Config Registers                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_jnr_dimm_cfg_u {
+	mmr_t	sh_jnr_dimm_cfg_regval;
+	struct {
+		mmr_t	dimm0_size  : 3;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	reserved_3  : 1;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_4  : 28;
+	} sh_jnr_dimm_cfg_s;
+} sh_jnr_dimm_cfg_u_t;
+#else
+typedef union sh_jnr_dimm_cfg_u {
+	mmr_t	sh_jnr_dimm_cfg_regval;
+	struct {
+		mmr_t	reserved_4  : 28;
+		mmr_t	freq        : 4;
+		mmr_t	reserved_3  : 1;
+		mmr_t	dimm3_cs    : 2;
+		mmr_t	dimm3_rev   : 1;
+		mmr_t	dimm3_2bk   : 1;
+		mmr_t	dimm3_size  : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	dimm2_cs    : 2;
+		mmr_t	dimm2_rev   : 1;
+		mmr_t	dimm2_2bk   : 1;
+		mmr_t	dimm2_size  : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	dimm1_cs    : 2;
+		mmr_t	dimm1_rev   : 1;
+		mmr_t	dimm1_2bk   : 1;
+		mmr_t	dimm1_size  : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	dimm0_cs    : 2;
+		mmr_t	dimm0_rev   : 1;
+		mmr_t	dimm0_2bk   : 1;
+		mmr_t	dimm0_size  : 3;
+	} sh_jnr_dimm_cfg_s;
+} sh_jnr_dimm_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_X_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_phase_cfg_u {
+	mmr_t	sh_x_phase_cfg_regval;
+	struct {
+		mmr_t	ld_a        : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	hold        : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	bubble_en   : 5;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	sel_a       : 4;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	reserved_0  : 1;
+	} sh_x_phase_cfg_s;
+} sh_x_phase_cfg_u_t;
+#else
+typedef union sh_x_phase_cfg_u {
+	mmr_t	sh_x_phase_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	sel_a       : 4;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	bubble_en   : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	hold        : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	ld_a        : 5;
+	} sh_x_phase_cfg_s;
+} sh_x_phase_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_cfg_u {
+	mmr_t	sh_x_cfg_regval;
+	struct {
+		mmr_t	mode_serial             : 1;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	clr_dir_cache           : 1;
+	} sh_x_cfg_s;
+} sh_x_cfg_u_t;
+#else
+typedef union sh_x_cfg_u {
+	mmr_t	sh_x_cfg_regval;
+	struct {
+		mmr_t	clr_dir_cache           : 1;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	mode_serial             : 1;
+	} sh_x_cfg_s;
+} sh_x_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_dqct_cfg_u {
+	mmr_t	sh_x_dqct_cfg_regval;
+	struct {
+		mmr_t	rd_sel      : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	reserved_0  : 40;
+	} sh_x_dqct_cfg_s;
+} sh_x_dqct_cfg_u_t;
+#else
+typedef union sh_x_dqct_cfg_u {
+	mmr_t	sh_x_dqct_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	rd_sel      : 4;
+	} sh_x_dqct_cfg_s;
+} sh_x_dqct_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_X_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_refresh_control_u {
+	mmr_t	sh_x_refresh_control_regval;
+	struct {
+		mmr_t	enable      : 8;
+		mmr_t	interval    : 9;
+		mmr_t	hold        : 6;
+		mmr_t	interleave  : 1;
+		mmr_t	half_rate   : 4;
+		mmr_t	reserved_0  : 36;
+	} sh_x_refresh_control_s;
+} sh_x_refresh_control_u_t;
+#else
+typedef union sh_x_refresh_control_u {
+	mmr_t	sh_x_refresh_control_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	half_rate   : 4;
+		mmr_t	interleave  : 1;
+		mmr_t	hold        : 6;
+		mmr_t	interval    : 9;
+		mmr_t	enable      : 8;
+	} sh_x_refresh_control_s;
+} sh_x_refresh_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_Y_PHASE_CFG"                       */
+/*                      AC Phase Config Registers                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_phase_cfg_u {
+	mmr_t	sh_y_phase_cfg_regval;
+	struct {
+		mmr_t	ld_a        : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	hold        : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	bubble_en   : 5;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	sel_a       : 4;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	reserved_0  : 1;
+	} sh_y_phase_cfg_s;
+} sh_y_phase_cfg_u_t;
+#else
+typedef union sh_y_phase_cfg_u {
+	mmr_t	sh_y_phase_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	dq_sel_a    : 4;
+		mmr_t	sel_a       : 4;
+		mmr_t	phe_bubble  : 3;
+		mmr_t	phd_bubble  : 3;
+		mmr_t	phc_bubble  : 3;
+		mmr_t	phb_bubble  : 3;
+		mmr_t	pha_bubble  : 3;
+		mmr_t	bubble_en   : 5;
+		mmr_t	add_cp      : 5;
+		mmr_t	hold_req    : 5;
+		mmr_t	hold        : 5;
+		mmr_t	dq_ld_b     : 5;
+		mmr_t	dq_ld_a     : 5;
+		mmr_t	ld_b        : 5;
+		mmr_t	ld_a        : 5;
+	} sh_y_phase_cfg_s;
+} sh_y_phase_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_CFG"                          */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_cfg_u {
+	mmr_t	sh_y_cfg_regval;
+	struct {
+		mmr_t	mode_serial             : 1;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	clr_dir_cache           : 1;
+	} sh_y_cfg_s;
+} sh_y_cfg_u_t;
+#else
+typedef union sh_y_cfg_u {
+	mmr_t	sh_y_cfg_regval;
+	struct {
+		mmr_t	clr_dir_cache           : 1;
+		mmr_t	inv_cas_addr            : 1;
+		mmr_t	req_cntr_val            : 6;
+		mmr_t	req_cntr_dis            : 1;
+		mmr_t	trcd4_en                : 1;
+		mmr_t	trcd2_en                : 1;
+		mmr_t	sso_wt_en               : 1;
+		mmr_t	wt_bb_clr               : 4;
+		mmr_t	dc_bb_clr               : 4;
+		mmr_t	da_bb_clr               : 4;
+		mmr_t	ta_dlys                 : 32;
+		mmr_t	dir_counter_init        : 6;
+		mmr_t	dirc_random_replacement : 1;
+		mmr_t	mode_serial             : 1;
+	} sh_y_cfg_s;
+} sh_y_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DQCT_CFG"                       */
+/*                         AC Config Registers                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_dqct_cfg_u {
+	mmr_t	sh_y_dqct_cfg_regval;
+	struct {
+		mmr_t	rd_sel      : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	reserved_0  : 40;
+	} sh_y_dqct_cfg_s;
+} sh_y_dqct_cfg_u_t;
+#else
+typedef union sh_y_dqct_cfg_u {
+	mmr_t	sh_y_dqct_cfg_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	mdir_rd_sel : 4;
+		mmr_t	dir_rd_sel  : 4;
+		mmr_t	dta_wt_sel  : 4;
+		mmr_t	dta_rd_sel  : 4;
+		mmr_t	wt_sel      : 4;
+		mmr_t	rd_sel      : 4;
+	} sh_y_dqct_cfg_s;
+} sh_y_dqct_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_Y_REFRESH_CONTROL"                    */
+/*                       Refresh Control Register                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_refresh_control_u {
+	mmr_t	sh_y_refresh_control_regval;
+	struct {
+		mmr_t	enable      : 8;
+		mmr_t	interval    : 9;
+		mmr_t	hold        : 6;
+		mmr_t	interleave  : 1;
+		mmr_t	half_rate   : 4;
+		mmr_t	reserved_0  : 36;
+	} sh_y_refresh_control_s;
+} sh_y_refresh_control_u_t;
+#else
+typedef union sh_y_refresh_control_u {
+	mmr_t	sh_y_refresh_control_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	half_rate   : 4;
+		mmr_t	interleave  : 1;
+		mmr_t	hold        : 6;
+		mmr_t	interval    : 9;
+		mmr_t	enable      : 8;
+	} sh_y_refresh_control_s;
+} sh_y_refresh_control_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MEM_RED_BLACK"                      */
+/*                     MD fairness watchdog timers                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_red_black_u {
+	mmr_t	sh_mem_red_black_regval;
+	struct {
+		mmr_t	time        : 16;
+		mmr_t	err_time    : 36;
+		mmr_t	reserved_0  : 12;
+	} sh_mem_red_black_s;
+} sh_mem_red_black_u_t;
+#else
+typedef union sh_mem_red_black_u {
+	mmr_t	sh_mem_red_black_regval;
+	struct {
+		mmr_t	reserved_0  : 12;
+		mmr_t	err_time    : 36;
+		mmr_t	time        : 16;
+	} sh_mem_red_black_s;
+} sh_mem_red_black_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MISC_MEM_CFG"                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_misc_mem_cfg_u {
+	mmr_t	sh_misc_mem_cfg_regval;
+	struct {
+		mmr_t	express_header_enable       : 1;
+		mmr_t	spec_header_enable          : 1;
+		mmr_t	jnr_bypass_enable           : 1;
+		mmr_t	xn_rd_same_as_pi            : 1;
+		mmr_t	low_write_buffer_threshold  : 6;
+		mmr_t	reserved_0                  : 2;
+		mmr_t	low_victim_buffer_threshold : 6;
+		mmr_t	reserved_1                  : 2;
+		mmr_t	throttle_cnt                : 8;
+		mmr_t	disabled_read_tnums         : 5;
+		mmr_t	reserved_2                  : 3;
+		mmr_t	disabled_write_tnums        : 5;
+		mmr_t	reserved_3                  : 3;
+		mmr_t	disabled_victims            : 6;
+		mmr_t	reserved_4                  : 2;
+		mmr_t	alternate_xn_rp_plane       : 1;
+		mmr_t	reserved_5                  : 11;
+	} sh_misc_mem_cfg_s;
+} sh_misc_mem_cfg_u_t;
+#else
+typedef union sh_misc_mem_cfg_u {
+	mmr_t	sh_misc_mem_cfg_regval;
+	struct {
+		mmr_t	reserved_5                  : 11;
+		mmr_t	alternate_xn_rp_plane       : 1;
+		mmr_t	reserved_4                  : 2;
+		mmr_t	disabled_victims            : 6;
+		mmr_t	reserved_3                  : 3;
+		mmr_t	disabled_write_tnums        : 5;
+		mmr_t	reserved_2                  : 3;
+		mmr_t	disabled_read_tnums         : 5;
+		mmr_t	throttle_cnt                : 8;
+		mmr_t	reserved_1                  : 2;
+		mmr_t	low_victim_buffer_threshold : 6;
+		mmr_t	reserved_0                  : 2;
+		mmr_t	low_write_buffer_threshold  : 6;
+		mmr_t	xn_rd_same_as_pi            : 1;
+		mmr_t	jnr_bypass_enable           : 1;
+		mmr_t	spec_header_enable          : 1;
+		mmr_t	express_header_enable       : 1;
+	} sh_misc_mem_cfg_s;
+} sh_misc_mem_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_PIO_RQ_CRD_CTL"                     */
+/*                  pio_rq Credit Circulation Control                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pio_rq_crd_ctl_u {
+	mmr_t	sh_pio_rq_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_pio_rq_crd_ctl_s;
+} sh_pio_rq_crd_ctl_u_t;
+#else
+typedef union sh_pio_rq_crd_ctl_u {
+	mmr_t	sh_pio_rq_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_pio_rq_crd_ctl_s;
+} sh_pio_rq_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RQ_CRD_CTL"                    */
+/*                 pi_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md_rq_crd_ctl_u {
+	mmr_t	sh_pi_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_pi_md_rq_crd_ctl_s;
+} sh_pi_md_rq_crd_ctl_u_t;
+#else
+typedef union sh_pi_md_rq_crd_ctl_u {
+	mmr_t	sh_pi_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_pi_md_rq_crd_ctl_s;
+} sh_pi_md_rq_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_PI_MD_RP_CRD_CTL"                    */
+/*                 pi_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_pi_md_rp_crd_ctl_u {
+	mmr_t	sh_pi_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_pi_md_rp_crd_ctl_s;
+} sh_pi_md_rp_crd_ctl_u_t;
+#else
+typedef union sh_pi_md_rp_crd_ctl_u {
+	mmr_t	sh_pi_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_pi_md_rp_crd_ctl_s;
+} sh_pi_md_rp_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RQ_CRD_CTL"                    */
+/*                 xn_md_rq Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_rq_crd_ctl_u {
+	mmr_t	sh_xn_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_xn_md_rq_crd_ctl_s;
+} sh_xn_md_rq_crd_ctl_u_t;
+#else
+typedef union sh_xn_md_rq_crd_ctl_u {
+	mmr_t	sh_xn_md_rq_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_xn_md_rq_crd_ctl_s;
+} sh_xn_md_rq_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_XN_MD_RP_CRD_CTL"                    */
+/*                 xn_md_rp Credit Circulation Control                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_xn_md_rp_crd_ctl_u {
+	mmr_t	sh_xn_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	depth       : 6;
+		mmr_t	reserved_0  : 58;
+	} sh_xn_md_rp_crd_ctl_s;
+} sh_xn_md_rp_crd_ctl_u_t;
+#else
+typedef union sh_xn_md_rp_crd_ctl_u {
+	mmr_t	sh_xn_md_rp_crd_ctl_regval;
+	struct {
+		mmr_t	reserved_0  : 58;
+		mmr_t	depth       : 6;
+	} sh_xn_md_rp_crd_ctl_s;
+} sh_xn_md_rp_crd_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag0_u {
+	mmr_t	sh_x_tag0_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag0_s;
+} sh_x_tag0_u_t;
+#else
+typedef union sh_x_tag0_u {
+	mmr_t	sh_x_tag0_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag0_s;
+} sh_x_tag0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag1_u {
+	mmr_t	sh_x_tag1_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag1_s;
+} sh_x_tag1_u_t;
+#else
+typedef union sh_x_tag1_u {
+	mmr_t	sh_x_tag1_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag1_s;
+} sh_x_tag1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag2_u {
+	mmr_t	sh_x_tag2_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag2_s;
+} sh_x_tag2_u_t;
+#else
+typedef union sh_x_tag2_u {
+	mmr_t	sh_x_tag2_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag2_s;
+} sh_x_tag2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag3_u {
+	mmr_t	sh_x_tag3_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag3_s;
+} sh_x_tag3_u_t;
+#else
+typedef union sh_x_tag3_u {
+	mmr_t	sh_x_tag3_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag3_s;
+} sh_x_tag3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag4_u {
+	mmr_t	sh_x_tag4_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag4_s;
+} sh_x_tag4_u_t;
+#else
+typedef union sh_x_tag4_u {
+	mmr_t	sh_x_tag4_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag4_s;
+} sh_x_tag4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag5_u {
+	mmr_t	sh_x_tag5_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag5_s;
+} sh_x_tag5_u_t;
+#else
+typedef union sh_x_tag5_u {
+	mmr_t	sh_x_tag5_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag5_s;
+} sh_x_tag5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag6_u {
+	mmr_t	sh_x_tag6_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag6_s;
+} sh_x_tag6_u_t;
+#else
+typedef union sh_x_tag6_u {
+	mmr_t	sh_x_tag6_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag6_s;
+} sh_x_tag6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_X_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag7_u {
+	mmr_t	sh_x_tag7_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_x_tag7_s;
+} sh_x_tag7_u_t;
+#else
+typedef union sh_x_tag7_u {
+	mmr_t	sh_x_tag7_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_x_tag7_s;
+} sh_x_tag7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG0"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag0_u {
+	mmr_t	sh_y_tag0_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag0_s;
+} sh_y_tag0_u_t;
+#else
+typedef union sh_y_tag0_u {
+	mmr_t	sh_y_tag0_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag0_s;
+} sh_y_tag0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG1"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag1_u {
+	mmr_t	sh_y_tag1_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag1_s;
+} sh_y_tag1_u_t;
+#else
+typedef union sh_y_tag1_u {
+	mmr_t	sh_y_tag1_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag1_s;
+} sh_y_tag1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG2"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag2_u {
+	mmr_t	sh_y_tag2_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag2_s;
+} sh_y_tag2_u_t;
+#else
+typedef union sh_y_tag2_u {
+	mmr_t	sh_y_tag2_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag2_s;
+} sh_y_tag2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG3"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag3_u {
+	mmr_t	sh_y_tag3_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag3_s;
+} sh_y_tag3_u_t;
+#else
+typedef union sh_y_tag3_u {
+	mmr_t	sh_y_tag3_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag3_s;
+} sh_y_tag3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG4"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag4_u {
+	mmr_t	sh_y_tag4_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag4_s;
+} sh_y_tag4_u_t;
+#else
+typedef union sh_y_tag4_u {
+	mmr_t	sh_y_tag4_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag4_s;
+} sh_y_tag4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG5"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag5_u {
+	mmr_t	sh_y_tag5_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag5_s;
+} sh_y_tag5_u_t;
+#else
+typedef union sh_y_tag5_u {
+	mmr_t	sh_y_tag5_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag5_s;
+} sh_y_tag5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG6"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag6_u {
+	mmr_t	sh_y_tag6_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag6_s;
+} sh_y_tag6_u_t;
+#else
+typedef union sh_y_tag6_u {
+	mmr_t	sh_y_tag6_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag6_s;
+} sh_y_tag6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                         Register "SH_Y_TAG7"                         */
+/*                           AC tag Registers                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag7_u {
+	mmr_t	sh_y_tag7_regval;
+	struct {
+		mmr_t	tag         : 20;
+		mmr_t	reserved_0  : 44;
+	} sh_y_tag7_s;
+} sh_y_tag7_u_t;
+#else
+typedef union sh_y_tag7_u {
+	mmr_t	sh_y_tag7_regval;
+	struct {
+		mmr_t	reserved_0  : 44;
+		mmr_t	tag         : 20;
+	} sh_y_tag7_s;
+} sh_y_tag7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_BASE"                      */
+/*                        mmr/bist base address                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mmrbist_base_u {
+	mmr_t	sh_mmrbist_base_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	dword_addr  : 47;
+		mmr_t	reserved_1  : 14;
+	} sh_mmrbist_base_s;
+} sh_mmrbist_base_u_t;
+#else
+typedef union sh_mmrbist_base_u {
+	mmr_t	sh_mmrbist_base_regval;
+	struct {
+		mmr_t	reserved_1  : 14;
+		mmr_t	dword_addr  : 47;
+		mmr_t	reserved_0  : 3;
+	} sh_mmrbist_base_s;
+} sh_mmrbist_base_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_MMRBIST_CTL"                       */
+/*                          Bist base address                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mmrbist_ctl_u {
+	mmr_t	sh_mmrbist_ctl_regval;
+	struct {
+		mmr_t	block_length : 31;
+		mmr_t	reserved_0   : 1;
+		mmr_t	cmd          : 7;
+		mmr_t	reserved_1   : 1;
+		mmr_t	in_progress  : 1;
+		mmr_t	fail         : 1;
+		mmr_t	mem_idle     : 1;
+		mmr_t	reserved_2   : 1;
+		mmr_t	reset_state  : 1;
+		mmr_t	reserved_3   : 19;
+	} sh_mmrbist_ctl_s;
+} sh_mmrbist_ctl_u_t;
+#else
+typedef union sh_mmrbist_ctl_u {
+	mmr_t	sh_mmrbist_ctl_regval;
+	struct {
+		mmr_t	reserved_3   : 19;
+		mmr_t	reset_state  : 1;
+		mmr_t	reserved_2   : 1;
+		mmr_t	mem_idle     : 1;
+		mmr_t	fail         : 1;
+		mmr_t	in_progress  : 1;
+		mmr_t	reserved_1   : 1;
+		mmr_t	cmd          : 7;
+		mmr_t	reserved_0   : 1;
+		mmr_t	block_length : 31;
+	} sh_mmrbist_ctl_s;
+} sh_mmrbist_ctl_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_DATA_CFG"                    */
+/*                configuration for md debug data muxes                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dbug_data_cfg_u {
+	mmr_t	sh_md_dbug_data_cfg_regval;
+	struct {
+		mmr_t	nibble0_chiplet : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	reserved_15     : 1;
+	} sh_md_dbug_data_cfg_s;
+} sh_md_dbug_data_cfg_u_t;
+#else
+typedef union sh_md_dbug_data_cfg_u {
+	mmr_t	sh_md_dbug_data_cfg_regval;
+	struct {
+		mmr_t	reserved_15     : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_chiplet : 3;
+	} sh_md_dbug_data_cfg_s;
+} sh_md_dbug_data_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DBUG_TRIGGER_CFG"                   */
+/*                 configuration for md debug triggers                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dbug_trigger_cfg_u {
+	mmr_t	sh_md_dbug_trigger_cfg_regval;
+	struct {
+		mmr_t	nibble0_chiplet : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	enable          : 1;
+	} sh_md_dbug_trigger_cfg_s;
+} sh_md_dbug_trigger_cfg_u_t;
+#else
+typedef union sh_md_dbug_trigger_cfg_u {
+	mmr_t	sh_md_dbug_trigger_cfg_regval;
+	struct {
+		mmr_t	enable          : 1;
+		mmr_t	nibble7_nibble  : 3;
+		mmr_t	reserved_14     : 1;
+		mmr_t	nibble7_chiplet : 3;
+		mmr_t	reserved_13     : 1;
+		mmr_t	nibble6_nibble  : 3;
+		mmr_t	reserved_12     : 1;
+		mmr_t	nibble6_chiplet : 3;
+		mmr_t	reserved_11     : 1;
+		mmr_t	nibble5_nibble  : 3;
+		mmr_t	reserved_10     : 1;
+		mmr_t	nibble5_chiplet : 3;
+		mmr_t	reserved_9      : 1;
+		mmr_t	nibble4_nibble  : 3;
+		mmr_t	reserved_8      : 1;
+		mmr_t	nibble4_chiplet : 3;
+		mmr_t	reserved_7      : 1;
+		mmr_t	nibble3_nibble  : 3;
+		mmr_t	reserved_6      : 1;
+		mmr_t	nibble3_chiplet : 3;
+		mmr_t	reserved_5      : 1;
+		mmr_t	nibble2_nibble  : 3;
+		mmr_t	reserved_4      : 1;
+		mmr_t	nibble2_chiplet : 3;
+		mmr_t	reserved_3      : 1;
+		mmr_t	nibble1_nibble  : 3;
+		mmr_t	reserved_2      : 1;
+		mmr_t	nibble1_chiplet : 3;
+		mmr_t	reserved_1      : 1;
+		mmr_t	nibble0_nibble  : 3;
+		mmr_t	reserved_0      : 1;
+		mmr_t	nibble0_chiplet : 3;
+	} sh_md_dbug_trigger_cfg_s;
+} sh_md_dbug_trigger_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MD_DBUG_COMPARE"                     */
+/*                  md debug compare pattern and mask                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dbug_compare_u {
+	mmr_t	sh_md_dbug_compare_regval;
+	struct {
+		mmr_t	pattern     : 32;
+		mmr_t	mask        : 32;
+	} sh_md_dbug_compare_s;
+} sh_md_dbug_compare_u_t;
+#else
+typedef union sh_md_dbug_compare_u {
+	mmr_t	sh_md_dbug_compare_regval;
+	struct {
+		mmr_t	mask        : 32;
+		mmr_t	pattern     : 32;
+	} sh_md_dbug_compare_s;
+} sh_md_dbug_compare_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_X_MOD_DBUG_SEL"                     */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_mod_dbug_sel_u {
+	mmr_t	sh_x_mod_dbug_sel_regval;
+	struct {
+		mmr_t	tag_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	arb_sel     : 8;
+		mmr_t	atl_sel     : 11;
+		mmr_t	atr_sel     : 11;
+		mmr_t	dql_sel     : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	reserved_0  : 6;
+	} sh_x_mod_dbug_sel_s;
+} sh_x_mod_dbug_sel_u_t;
+#else
+typedef union sh_x_mod_dbug_sel_u {
+	mmr_t	sh_x_mod_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	dql_sel     : 6;
+		mmr_t	atr_sel     : 11;
+		mmr_t	atl_sel     : 11;
+		mmr_t	arb_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	tag_sel     : 8;
+	} sh_x_mod_dbug_sel_s;
+} sh_x_mod_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_DBUG_SEL"                       */
+/*                         MD acx debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_dbug_sel_u {
+	mmr_t	sh_x_dbug_sel_regval;
+	struct {
+		mmr_t	dbg_sel     : 24;
+		mmr_t	reserved_0  : 40;
+	} sh_x_dbug_sel_s;
+} sh_x_dbug_sel_u_t;
+#else
+typedef union sh_x_dbug_sel_u {
+	mmr_t	sh_x_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	dbg_sel     : 24;
+	} sh_x_dbug_sel_s;
+} sh_x_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_X_LADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_laddr_cmp_u {
+	mmr_t	sh_x_laddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_x_laddr_cmp_s;
+} sh_x_laddr_cmp_u_t;
+#else
+typedef union sh_x_laddr_cmp_u {
+	mmr_t	sh_x_laddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_x_laddr_cmp_s;
+} sh_x_laddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_X_RADDR_CMP"                       */
+/*                        MD acx address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_raddr_cmp_u {
+	mmr_t	sh_x_raddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_x_raddr_cmp_s;
+} sh_x_raddr_cmp_u_t;
+#else
+typedef union sh_x_raddr_cmp_u {
+	mmr_t	sh_x_raddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_x_raddr_cmp_s;
+} sh_x_raddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_CMP"                        */
+/*                        MD acx tagmgr compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag_cmp_u {
+	mmr_t	sh_x_tag_cmp_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_x_tag_cmp_s;
+} sh_x_tag_cmp_u_t;
+#else
+typedef union sh_x_tag_cmp_u {
+	mmr_t	sh_x_tag_cmp_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_x_tag_cmp_s;
+} sh_x_tag_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_X_TAG_MASK"                       */
+/*                          MD acx tagmgr mask                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_x_tag_mask_u {
+	mmr_t	sh_x_tag_mask_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_x_tag_mask_s;
+} sh_x_tag_mask_u_t;
+#else
+typedef union sh_x_tag_mask_u {
+	mmr_t	sh_x_tag_mask_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_x_tag_mask_s;
+} sh_x_tag_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_Y_MOD_DBUG_SEL"                     */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_mod_dbug_sel_u {
+	mmr_t	sh_y_mod_dbug_sel_regval;
+	struct {
+		mmr_t	tag_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	arb_sel     : 8;
+		mmr_t	atl_sel     : 11;
+		mmr_t	atr_sel     : 11;
+		mmr_t	dql_sel     : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	reserved_0  : 6;
+	} sh_y_mod_dbug_sel_s;
+} sh_y_mod_dbug_sel_u_t;
+#else
+typedef union sh_y_mod_dbug_sel_u {
+	mmr_t	sh_y_mod_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	dqr_sel     : 6;
+		mmr_t	dql_sel     : 6;
+		mmr_t	atr_sel     : 11;
+		mmr_t	atl_sel     : 11;
+		mmr_t	arb_sel     : 8;
+		mmr_t	wbq_sel     : 8;
+		mmr_t	tag_sel     : 8;
+	} sh_y_mod_dbug_sel_s;
+} sh_y_mod_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_DBUG_SEL"                       */
+/*                         MD acy debug select                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_dbug_sel_u {
+	mmr_t	sh_y_dbug_sel_regval;
+	struct {
+		mmr_t	dbg_sel     : 24;
+		mmr_t	reserved_0  : 40;
+	} sh_y_dbug_sel_s;
+} sh_y_dbug_sel_u_t;
+#else
+typedef union sh_y_dbug_sel_u {
+	mmr_t	sh_y_dbug_sel_regval;
+	struct {
+		mmr_t	reserved_0  : 40;
+		mmr_t	dbg_sel     : 24;
+	} sh_y_dbug_sel_s;
+} sh_y_dbug_sel_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_Y_LADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_laddr_cmp_u {
+	mmr_t	sh_y_laddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_y_laddr_cmp_s;
+} sh_y_laddr_cmp_u_t;
+#else
+typedef union sh_y_laddr_cmp_u {
+	mmr_t	sh_y_laddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_y_laddr_cmp_s;
+} sh_y_laddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                      Register "SH_Y_RADDR_CMP"                       */
+/*                        MD acy address compare                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_raddr_cmp_u {
+	mmr_t	sh_y_raddr_cmp_regval;
+	struct {
+		mmr_t	cmp_val     : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_1  : 4;
+	} sh_y_raddr_cmp_s;
+} sh_y_raddr_cmp_u_t;
+#else
+typedef union sh_y_raddr_cmp_u {
+	mmr_t	sh_y_raddr_cmp_regval;
+	struct {
+		mmr_t	reserved_1  : 4;
+		mmr_t	mask_val    : 28;
+		mmr_t	reserved_0  : 4;
+		mmr_t	cmp_val     : 28;
+	} sh_y_raddr_cmp_s;
+} sh_y_raddr_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_CMP"                        */
+/*                        MD acy tagmgr compare                         */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag_cmp_u {
+	mmr_t	sh_y_tag_cmp_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_y_tag_cmp_s;
+} sh_y_tag_cmp_u_t;
+#else
+typedef union sh_y_tag_cmp_u {
+	mmr_t	sh_y_tag_cmp_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_y_tag_cmp_s;
+} sh_y_tag_cmp_u_t;
+#endif
+
+/* ==================================================================== */
+/*                       Register "SH_Y_TAG_MASK"                       */
+/*                          MD acy tagmgr mask                          */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_y_tag_mask_u {
+	mmr_t	sh_y_tag_mask_regval;
+	struct {
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	src         : 14;
+		mmr_t	reserved_0  : 9;
+	} sh_y_tag_mask_s;
+} sh_y_tag_mask_u_t;
+#else
+typedef union sh_y_tag_mask_u {
+	mmr_t	sh_y_tag_mask_regval;
+	struct {
+		mmr_t	reserved_0  : 9;
+		mmr_t	src         : 14;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+	} sh_y_tag_mask_s;
+} sh_y_tag_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_JNR_DBUG_DATA_CFG"                  */
+/*              configuration for md jnr debug data muxes               */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_jnr_dbug_data_cfg_u {
+	mmr_t	sh_md_jnr_dbug_data_cfg_regval;
+	struct {
+		mmr_t	nibble0_sel : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	nibble1_sel : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	nibble2_sel : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	nibble3_sel : 3;
+		mmr_t	reserved_3  : 1;
+		mmr_t	nibble4_sel : 3;
+		mmr_t	reserved_4  : 1;
+		mmr_t	nibble5_sel : 3;
+		mmr_t	reserved_5  : 1;
+		mmr_t	nibble6_sel : 3;
+		mmr_t	reserved_6  : 1;
+		mmr_t	nibble7_sel : 3;
+		mmr_t	reserved_7  : 33;
+	} sh_md_jnr_dbug_data_cfg_s;
+} sh_md_jnr_dbug_data_cfg_u_t;
+#else
+typedef union sh_md_jnr_dbug_data_cfg_u {
+	mmr_t	sh_md_jnr_dbug_data_cfg_regval;
+	struct {
+		mmr_t	reserved_7  : 33;
+		mmr_t	nibble7_sel : 3;
+		mmr_t	reserved_6  : 1;
+		mmr_t	nibble6_sel : 3;
+		mmr_t	reserved_5  : 1;
+		mmr_t	nibble5_sel : 3;
+		mmr_t	reserved_4  : 1;
+		mmr_t	nibble4_sel : 3;
+		mmr_t	reserved_3  : 1;
+		mmr_t	nibble3_sel : 3;
+		mmr_t	reserved_2  : 1;
+		mmr_t	nibble2_sel : 3;
+		mmr_t	reserved_1  : 1;
+		mmr_t	nibble1_sel : 3;
+		mmr_t	reserved_0  : 1;
+		mmr_t	nibble0_sel : 3;
+	} sh_md_jnr_dbug_data_cfg_s;
+} sh_md_jnr_dbug_data_cfg_u_t;
+#endif
+
+/* ==================================================================== */
+/*                     Register "SH_MD_LAST_CREDIT"                     */
+/*                 captures last credit values on reset                 */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_last_credit_u {
+	mmr_t	sh_md_last_credit_regval;
+	struct {
+		mmr_t	rq_to_pi    : 6;
+		mmr_t	reserved_0  : 2;
+		mmr_t	rp_to_pi    : 6;
+		mmr_t	reserved_1  : 2;
+		mmr_t	rq_to_xn    : 6;
+		mmr_t	reserved_2  : 2;
+		mmr_t	rp_to_xn    : 6;
+		mmr_t	reserved_3  : 2;
+		mmr_t	to_lb       : 6;
+		mmr_t	reserved_4  : 26;
+	} sh_md_last_credit_s;
+} sh_md_last_credit_u_t;
+#else
+typedef union sh_md_last_credit_u {
+	mmr_t	sh_md_last_credit_regval;
+	struct {
+		mmr_t	reserved_4  : 26;
+		mmr_t	to_lb       : 6;
+		mmr_t	reserved_3  : 2;
+		mmr_t	rp_to_xn    : 6;
+		mmr_t	reserved_2  : 2;
+		mmr_t	rq_to_xn    : 6;
+		mmr_t	reserved_1  : 2;
+		mmr_t	rp_to_pi    : 6;
+		mmr_t	reserved_0  : 2;
+		mmr_t	rq_to_pi    : 6;
+	} sh_md_last_credit_s;
+} sh_md_last_credit_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_ADDR"                    */
+/*                   Address capture address register                   */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_capture_addr_u {
+	mmr_t	sh_mem_capture_addr_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	reserved_1  : 20;
+	} sh_mem_capture_addr_s;
+} sh_mem_capture_addr_u_t;
+#else
+typedef union sh_mem_capture_addr_u {
+	mmr_t	sh_mem_capture_addr_regval;
+	struct {
+		mmr_t	reserved_1  : 20;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_mem_capture_addr_s;
+} sh_mem_capture_addr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_MASK"                    */
+/*                    Address capture mask register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_capture_mask_u {
+	mmr_t	sh_mem_capture_mask_regval;
+	struct {
+		mmr_t	reserved_0    : 3;
+		mmr_t	addr          : 33;
+		mmr_t	cmd           : 8;
+		mmr_t	enable_local  : 1;
+		mmr_t	enable_remote : 1;
+		mmr_t	reserved_1    : 18;
+	} sh_mem_capture_mask_s;
+} sh_mem_capture_mask_u_t;
+#else
+typedef union sh_mem_capture_mask_u {
+	mmr_t	sh_mem_capture_mask_regval;
+	struct {
+		mmr_t	reserved_1    : 18;
+		mmr_t	enable_remote : 1;
+		mmr_t	enable_local  : 1;
+		mmr_t	cmd           : 8;
+		mmr_t	addr          : 33;
+		mmr_t	reserved_0    : 3;
+	} sh_mem_capture_mask_s;
+} sh_mem_capture_mask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                    Register "SH_MEM_CAPTURE_HDR"                     */
+/*                   Address capture header register                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_mem_capture_hdr_u {
+	mmr_t	sh_mem_capture_hdr_regval;
+	struct {
+		mmr_t	reserved_0  : 3;
+		mmr_t	addr        : 33;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	cntr        : 6;
+	} sh_mem_capture_hdr_s;
+} sh_mem_capture_hdr_u_t;
+#else
+typedef union sh_mem_capture_hdr_u {
+	mmr_t	sh_mem_capture_hdr_regval;
+	struct {
+		mmr_t	cntr        : 6;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	addr        : 33;
+		mmr_t	reserved_0  : 3;
+	} sh_mem_capture_hdr_s;
+} sh_mem_capture_hdr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_config_u {
+	mmr_t	sh_md_dqlp_mmr_dir_config_regval;
+	struct {
+		mmr_t	sys_size    : 3;
+		mmr_t	en_direcc   : 1;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	reserved_0  : 59;
+	} sh_md_dqlp_mmr_dir_config_s;
+} sh_md_dqlp_mmr_dir_config_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_config_u {
+	mmr_t	sh_md_dqlp_mmr_dir_config_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	en_direcc   : 1;
+		mmr_t	sys_size    : 3;
+	} sh_md_dqlp_mmr_dir_config_s;
+} sh_md_dqlp_mmr_dir_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec0_s;
+} sh_md_dqlp_mmr_dir_presvec0_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec0_s;
+} sh_md_dqlp_mmr_dir_presvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec1_s;
+} sh_md_dqlp_mmr_dir_presvec1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec1_s;
+} sh_md_dqlp_mmr_dir_presvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec2_s;
+} sh_md_dqlp_mmr_dir_presvec2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec2_s;
+} sh_md_dqlp_mmr_dir_presvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec3_s;
+} sh_md_dqlp_mmr_dir_presvec3_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_presvec3_s;
+} sh_md_dqlp_mmr_dir_presvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec0_s;
+} sh_md_dqlp_mmr_dir_locvec0_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec0_s;
+} sh_md_dqlp_mmr_dir_locvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec1_s;
+} sh_md_dqlp_mmr_dir_locvec1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec1_s;
+} sh_md_dqlp_mmr_dir_locvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec2_s;
+} sh_md_dqlp_mmr_dir_locvec2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec2_s;
+} sh_md_dqlp_mmr_dir_locvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec3_s;
+} sh_md_dqlp_mmr_dir_locvec3_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec3_s;
+} sh_md_dqlp_mmr_dir_locvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec4_s;
+} sh_md_dqlp_mmr_dir_locvec4_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec4_s;
+} sh_md_dqlp_mmr_dir_locvec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec5_s;
+} sh_md_dqlp_mmr_dir_locvec5_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec5_s;
+} sh_md_dqlp_mmr_dir_locvec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec6_s;
+} sh_md_dqlp_mmr_dir_locvec6_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec6_s;
+} sh_md_dqlp_mmr_dir_locvec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec7_s;
+} sh_md_dqlp_mmr_dir_locvec7_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqlp_mmr_dir_locvec7_s;
+} sh_md_dqlp_mmr_dir_locvec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec0_s;
+} sh_md_dqlp_mmr_dir_privec0_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec0_s;
+} sh_md_dqlp_mmr_dir_privec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec1_s;
+} sh_md_dqlp_mmr_dir_privec1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec1_s;
+} sh_md_dqlp_mmr_dir_privec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec2_s;
+} sh_md_dqlp_mmr_dir_privec2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec2_s;
+} sh_md_dqlp_mmr_dir_privec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec3_s;
+} sh_md_dqlp_mmr_dir_privec3_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec3_s;
+} sh_md_dqlp_mmr_dir_privec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec4_s;
+} sh_md_dqlp_mmr_dir_privec4_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec4_s;
+} sh_md_dqlp_mmr_dir_privec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec5_s;
+} sh_md_dqlp_mmr_dir_privec5_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec5_s;
+} sh_md_dqlp_mmr_dir_privec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec6_s;
+} sh_md_dqlp_mmr_dir_privec6_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec6_s;
+} sh_md_dqlp_mmr_dir_privec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqlp_mmr_dir_privec7_s;
+} sh_md_dqlp_mmr_dir_privec7_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqlp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqlp_mmr_dir_privec7_s;
+} sh_md_dqlp_mmr_dir_privec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqlp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	timer_div   : 12;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_cur   : 9;
+		mmr_t	reserved_0  : 42;
+	} sh_md_dqlp_mmr_dir_timer_s;
+} sh_md_dqlp_mmr_dir_timer_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqlp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	reserved_0  : 42;
+		mmr_t	timer_cur   : 9;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_div   : 12;
+	} sh_md_dqlp_mmr_dir_timer_s;
+} sh_md_dqlp_mmr_dir_timer_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	reserved_0  : 6;
+	} sh_md_dqlp_mmr_piowd_dir_entry_s;
+} sh_md_dqlp_mmr_piowd_dir_entry_u_t;
+#else
+typedef union sh_md_dqlp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqlp_mmr_piowd_dir_entry_s;
+} sh_md_dqlp_mmr_piowd_dir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQLP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqlp_mmr_piowd_dir_ecc_s;
+} sh_md_dqlp_mmr_piowd_dir_ecc_u_t;
+#else
+typedef union sh_md_dqlp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqlp_mmr_piowd_dir_ecc_s;
+} sh_md_dqlp_mmr_piowd_dir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqlp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqlp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqlp_mmr_xpiord_xdir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqlp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqlp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqlp_mmr_xpiord_xdir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqlp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqlp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqlp_mmr_ypiord_ydir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQLP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqlp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqlp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqlp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqlp_mmr_ypiord_ydir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_xcerr1_s;
+} sh_md_dqlp_mmr_xcerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_xcerr1_s;
+} sh_md_dqlp_mmr_xcerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_xcerr2_s;
+} sh_md_dqlp_mmr_xcerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_xcerr2_s;
+} sh_md_dqlp_mmr_xcerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_xuerr1_s;
+} sh_md_dqlp_mmr_xuerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_xuerr1_s;
+} sh_md_dqlp_mmr_xuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_xuerr2_s;
+} sh_md_dqlp_mmr_xuerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_xuerr2_s;
+} sh_md_dqlp_mmr_xuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xperr_u {
+	mmr_t	sh_md_dqlp_mmr_xperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqlp_mmr_xperr_s;
+} sh_md_dqlp_mmr_xperr_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xperr_u {
+	mmr_t	sh_md_dqlp_mmr_xperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqlp_mmr_xperr_s;
+} sh_md_dqlp_mmr_xperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_ycerr1_s;
+} sh_md_dqlp_mmr_ycerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_ycerr1_s;
+} sh_md_dqlp_mmr_ycerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_ycerr2_s;
+} sh_md_dqlp_mmr_ycerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqlp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_ycerr2_s;
+} sh_md_dqlp_mmr_ycerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqlp_mmr_yuerr1_s;
+} sh_md_dqlp_mmr_yuerr1_u_t;
+#else
+typedef union sh_md_dqlp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqlp_mmr_yuerr1_s;
+} sh_md_dqlp_mmr_yuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqlp_mmr_yuerr2_s;
+} sh_md_dqlp_mmr_yuerr2_u_t;
+#else
+typedef union sh_md_dqlp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqlp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqlp_mmr_yuerr2_s;
+} sh_md_dqlp_mmr_yuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQLP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_yperr_u {
+	mmr_t	sh_md_dqlp_mmr_yperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqlp_mmr_yperr_s;
+} sh_md_dqlp_mmr_yperr_u_t;
+#else
+typedef union sh_md_dqlp_mmr_yperr_u {
+	mmr_t	sh_md_dqlp_mmr_yperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqlp_mmr_yperr_s;
+} sh_md_dqlp_mmr_yperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	cmd0        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd3        : 8;
+		mmr_t	reserved_0  : 32;
+	} sh_md_dqlp_mmr_dir_cmdtrig_s;
+} sh_md_dqlp_mmr_dir_cmdtrig_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	cmd3        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd0        : 8;
+	} sh_md_dqlp_mmr_dir_cmdtrig_s;
+} sh_md_dqlp_mmr_dir_cmdtrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqlp_mmr_dir_tbltrig_s;
+} sh_md_dqlp_mmr_dir_tbltrig_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqlp_mmr_dir_tbltrig_s;
+} sh_md_dqlp_mmr_dir_tbltrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqlp_mmr_dir_tblmask_s;
+} sh_md_dqlp_mmr_dir_tblmask_u_t;
+#else
+typedef union sh_md_dqlp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqlp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqlp_mmr_dir_tblmask_s;
+} sh_md_dqlp_mmr_dir_tblmask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqlp_mmr_xbist_h_s;
+} sh_md_dqlp_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_h_s;
+} sh_md_dqlp_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_xbist_l_s;
+} sh_md_dqlp_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_l_s;
+} sh_md_dqlp_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_xbist_err_h_s;
+} sh_md_dqlp_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_err_h_s;
+} sh_md_dqlp_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_xbist_err_l_s;
+} sh_md_dqlp_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_xbist_err_l_s;
+} sh_md_dqlp_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqlp_mmr_ybist_h_s;
+} sh_md_dqlp_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_h_s;
+} sh_md_dqlp_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_ybist_l_s;
+} sh_md_dqlp_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_l_s;
+} sh_md_dqlp_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_ybist_err_h_s;
+} sh_md_dqlp_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_err_h_s;
+} sh_md_dqlp_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqlp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqlp_mmr_ybist_err_l_s;
+} sh_md_dqlp_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqlp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqlp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqlp_mmr_ybist_err_l_s;
+} sh_md_dqlp_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqls_mmr_xbist_h_s;
+} sh_md_dqls_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_h_s;
+} sh_md_dqls_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_xbist_l_s;
+} sh_md_dqls_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_l_s;
+} sh_md_dqls_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_xbist_err_h_s;
+} sh_md_dqls_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_err_h_s;
+} sh_md_dqls_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_xbist_err_l_s;
+} sh_md_dqls_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_xbist_err_l_s;
+} sh_md_dqls_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqls_mmr_ybist_h_s;
+} sh_md_dqls_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_h_s;
+} sh_md_dqls_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQLS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_ybist_l_s;
+} sh_md_dqls_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_l_s;
+} sh_md_dqls_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_ybist_err_h_s;
+} sh_md_dqls_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_err_h_s;
+} sh_md_dqls_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQLS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqls_mmr_ybist_err_l_s;
+} sh_md_dqls_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqls_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqls_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqls_mmr_ybist_err_l_s;
+} sh_md_dqls_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqls_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	px          : 1;
+		mmr_t	rw          : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_md_dqls_mmr_jnr_debug_s;
+} sh_md_dqls_mmr_jnr_debug_u_t;
+#else
+typedef union sh_md_dqls_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqls_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	rw          : 1;
+		mmr_t	px          : 1;
+	} sh_md_dqls_mmr_jnr_debug_s;
+} sh_md_dqls_mmr_jnr_debug_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQLS_MMR_XAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqls_mmr_xamopw_err_u {
+	mmr_t	sh_md_dqls_mmr_xamopw_err_regval;
+	struct {
+		mmr_t	ssyn        : 8;
+		mmr_t	scor        : 1;
+		mmr_t	sunc        : 1;
+		mmr_t	reserved_0  : 6;
+		mmr_t	rsyn        : 8;
+		mmr_t	rcor        : 1;
+		mmr_t	runc        : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_2  : 31;
+	} sh_md_dqls_mmr_xamopw_err_s;
+} sh_md_dqls_mmr_xamopw_err_u_t;
+#else
+typedef union sh_md_dqls_mmr_xamopw_err_u {
+	mmr_t	sh_md_dqls_mmr_xamopw_err_regval;
+	struct {
+		mmr_t	reserved_2  : 31;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	runc        : 1;
+		mmr_t	rcor        : 1;
+		mmr_t	rsyn        : 8;
+		mmr_t	reserved_0  : 6;
+		mmr_t	sunc        : 1;
+		mmr_t	scor        : 1;
+		mmr_t	ssyn        : 8;
+	} sh_md_dqls_mmr_xamopw_err_s;
+} sh_md_dqls_mmr_xamopw_err_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_CONFIG"                 */
+/*                     DQ directory config register                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_config_u {
+	mmr_t	sh_md_dqrp_mmr_dir_config_regval;
+	struct {
+		mmr_t	sys_size    : 3;
+		mmr_t	en_direcc   : 1;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	reserved_0  : 59;
+	} sh_md_dqrp_mmr_dir_config_s;
+} sh_md_dqrp_mmr_dir_config_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_config_u {
+	mmr_t	sh_md_dqrp_mmr_dir_config_regval;
+	struct {
+		mmr_t	reserved_0  : 59;
+		mmr_t	en_dirpois  : 1;
+		mmr_t	en_direcc   : 1;
+		mmr_t	sys_size    : 3;
+	} sh_md_dqrp_mmr_dir_config_s;
+} sh_md_dqrp_mmr_dir_config_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC0"                */
+/*                      node [63:0] presence bits                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec0_s;
+} sh_md_dqrp_mmr_dir_presvec0_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec0_s;
+} sh_md_dqrp_mmr_dir_presvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC1"                */
+/*                     node [127:64] presence bits                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec1_s;
+} sh_md_dqrp_mmr_dir_presvec1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec1_s;
+} sh_md_dqrp_mmr_dir_presvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC2"                */
+/*                     node [191:128] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec2_s;
+} sh_md_dqrp_mmr_dir_presvec2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec2_s;
+} sh_md_dqrp_mmr_dir_presvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRESVEC3"                */
+/*                     node [255:192] presence bits                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec3_s;
+} sh_md_dqrp_mmr_dir_presvec3_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_presvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_presvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_presvec3_s;
+} sh_md_dqrp_mmr_dir_presvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC0"                 */
+/*                        local vector for acc=0                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec0_s;
+} sh_md_dqrp_mmr_dir_locvec0_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec0_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec0_s;
+} sh_md_dqrp_mmr_dir_locvec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC1"                 */
+/*                        local vector for acc=1                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec1_s;
+} sh_md_dqrp_mmr_dir_locvec1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec1_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec1_s;
+} sh_md_dqrp_mmr_dir_locvec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC2"                 */
+/*                        local vector for acc=2                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec2_s;
+} sh_md_dqrp_mmr_dir_locvec2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec2_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec2_s;
+} sh_md_dqrp_mmr_dir_locvec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC3"                 */
+/*                        local vector for acc=3                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec3_s;
+} sh_md_dqrp_mmr_dir_locvec3_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec3_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec3_s;
+} sh_md_dqrp_mmr_dir_locvec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC4"                 */
+/*                        local vector for acc=4                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec4_s;
+} sh_md_dqrp_mmr_dir_locvec4_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec4_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec4_s;
+} sh_md_dqrp_mmr_dir_locvec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC5"                 */
+/*                        local vector for acc=5                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec5_s;
+} sh_md_dqrp_mmr_dir_locvec5_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec5_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec5_s;
+} sh_md_dqrp_mmr_dir_locvec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC6"                 */
+/*                        local vector for acc=6                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec6_s;
+} sh_md_dqrp_mmr_dir_locvec6_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec6_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec6_s;
+} sh_md_dqrp_mmr_dir_locvec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_LOCVEC7"                 */
+/*                        local vector for acc=7                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec7_s;
+} sh_md_dqrp_mmr_dir_locvec7_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_locvec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_locvec7_regval;
+	struct {
+		mmr_t	vec         : 64;
+	} sh_md_dqrp_mmr_dir_locvec7_s;
+} sh_md_dqrp_mmr_dir_locvec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC0"                 */
+/*                      privilege vector for acc=0                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec0_s;
+} sh_md_dqrp_mmr_dir_privec0_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec0_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec0_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec0_s;
+} sh_md_dqrp_mmr_dir_privec0_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC1"                 */
+/*                      privilege vector for acc=1                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec1_s;
+} sh_md_dqrp_mmr_dir_privec1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec1_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec1_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec1_s;
+} sh_md_dqrp_mmr_dir_privec1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC2"                 */
+/*                      privilege vector for acc=2                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec2_s;
+} sh_md_dqrp_mmr_dir_privec2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec2_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec2_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec2_s;
+} sh_md_dqrp_mmr_dir_privec2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC3"                 */
+/*                      privilege vector for acc=3                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec3_s;
+} sh_md_dqrp_mmr_dir_privec3_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec3_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec3_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec3_s;
+} sh_md_dqrp_mmr_dir_privec3_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC4"                 */
+/*                      privilege vector for acc=4                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec4_s;
+} sh_md_dqrp_mmr_dir_privec4_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec4_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec4_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec4_s;
+} sh_md_dqrp_mmr_dir_privec4_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC5"                 */
+/*                      privilege vector for acc=5                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec5_s;
+} sh_md_dqrp_mmr_dir_privec5_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec5_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec5_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec5_s;
+} sh_md_dqrp_mmr_dir_privec5_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC6"                 */
+/*                      privilege vector for acc=6                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec6_s;
+} sh_md_dqrp_mmr_dir_privec6_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec6_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec6_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec6_s;
+} sh_md_dqrp_mmr_dir_privec6_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_PRIVEC7"                 */
+/*                      privilege vector for acc=7                      */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	in          : 14;
+		mmr_t	out         : 14;
+		mmr_t	reserved_0  : 36;
+	} sh_md_dqrp_mmr_dir_privec7_s;
+} sh_md_dqrp_mmr_dir_privec7_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_privec7_u {
+	mmr_t	sh_md_dqrp_mmr_dir_privec7_regval;
+	struct {
+		mmr_t	reserved_0  : 36;
+		mmr_t	out         : 14;
+		mmr_t	in          : 14;
+	} sh_md_dqrp_mmr_dir_privec7_s;
+} sh_md_dqrp_mmr_dir_privec7_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRP_MMR_DIR_TIMER"                  */
+/*                            MD SXRO timer                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqrp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	timer_div   : 12;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_cur   : 9;
+		mmr_t	reserved_0  : 42;
+	} sh_md_dqrp_mmr_dir_timer_s;
+} sh_md_dqrp_mmr_dir_timer_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_timer_u {
+	mmr_t	sh_md_dqrp_mmr_dir_timer_regval;
+	struct {
+		mmr_t	reserved_0  : 42;
+		mmr_t	timer_cur   : 9;
+		mmr_t	timer_en    : 1;
+		mmr_t	timer_div   : 12;
+	} sh_md_dqrp_mmr_dir_timer_s;
+} sh_md_dqrp_mmr_dir_timer_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_PIOWD_DIR_ENTRY"               */
+/*                       directory pio write data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	reserved_0  : 6;
+	} sh_md_dqrp_mmr_piowd_dir_entry_s;
+} sh_md_dqrp_mmr_piowd_dir_entry_u_t;
+#else
+typedef union sh_md_dqrp_mmr_piowd_dir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 6;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqrp_mmr_piowd_dir_entry_s;
+} sh_md_dqrp_mmr_piowd_dir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*               Register "SH_MD_DQRP_MMR_PIOWD_DIR_ECC"                */
+/*                        directory ecc register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqrp_mmr_piowd_dir_ecc_s;
+} sh_md_dqrp_mmr_piowd_dir_ecc_u_t;
+#else
+typedef union sh_md_dqrp_mmr_piowd_dir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_piowd_dir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqrp_mmr_piowd_dir_ecc_s;
+} sh_md_dqrp_mmr_piowd_dir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ENTRY"              */
+/*                      x directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqrp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xpiord_xdir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqrp_mmr_xpiord_xdir_entry_s;
+} sh_md_dqrp_mmr_xpiord_xdir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_XPIORD_XDIR_ECC"               */
+/*                           x directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqrp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xpiord_xdir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_xpiord_xdir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqrp_mmr_xpiord_xdir_ecc_s;
+} sh_md_dqrp_mmr_xpiord_xdir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*             Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ENTRY"              */
+/*                      y directory pio read data                       */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	dira        : 26;
+		mmr_t	dirb        : 26;
+		mmr_t	pri         : 3;
+		mmr_t	acc         : 3;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	reserved_0  : 4;
+	} sh_md_dqrp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ypiord_ydir_entry_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_entry_regval;
+	struct {
+		mmr_t	reserved_0  : 4;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	acc         : 3;
+		mmr_t	pri         : 3;
+		mmr_t	dirb        : 26;
+		mmr_t	dira        : 26;
+	} sh_md_dqrp_mmr_ypiord_ydir_entry_s;
+} sh_md_dqrp_mmr_ypiord_ydir_entry_u_t;
+#endif
+
+/* ==================================================================== */
+/*              Register "SH_MD_DQRP_MMR_YPIORD_YDIR_ECC"               */
+/*                           y directory ecc                            */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	ecca        : 7;
+		mmr_t	eccb        : 7;
+		mmr_t	reserved_0  : 50;
+	} sh_md_dqrp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ypiord_ydir_ecc_u {
+	mmr_t	sh_md_dqrp_mmr_ypiord_ydir_ecc_regval;
+	struct {
+		mmr_t	reserved_0  : 50;
+		mmr_t	eccb        : 7;
+		mmr_t	ecca        : 7;
+	} sh_md_dqrp_mmr_ypiord_ydir_ecc_s;
+} sh_md_dqrp_mmr_ypiord_ydir_ecc_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_xcerr1_s;
+} sh_md_dqrp_mmr_xcerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xcerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_xcerr1_s;
+} sh_md_dqrp_mmr_xcerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_xcerr2_s;
+} sh_md_dqrp_mmr_xcerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xcerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xcerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_xcerr2_s;
+} sh_md_dqrp_mmr_xcerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_xuerr1_s;
+} sh_md_dqrp_mmr_xuerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_xuerr1_s;
+} sh_md_dqrp_mmr_xuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_xuerr2_s;
+} sh_md_dqrp_mmr_xuerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_xuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_xuerr2_s;
+} sh_md_dqrp_mmr_xuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_XPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xperr_u {
+	mmr_t	sh_md_dqrp_mmr_xperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqrp_mmr_xperr_s;
+} sh_md_dqrp_mmr_xperr_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xperr_u {
+	mmr_t	sh_md_dqrp_mmr_xperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqrp_mmr_xperr_s;
+} sh_md_dqrp_mmr_xperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR1"                   */
+/*              correctable dir ecc group 1 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_ycerr1_s;
+} sh_md_dqrp_mmr_ycerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ycerr1_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_ycerr1_s;
+} sh_md_dqrp_mmr_ycerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YCERR2"                   */
+/*              correctable dir ecc group 2 error register              */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_ycerr2_s;
+} sh_md_dqrp_mmr_ycerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ycerr2_u {
+	mmr_t	sh_md_dqrp_mmr_ycerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_ycerr2_s;
+} sh_md_dqrp_mmr_ycerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR1"                   */
+/*             uncorrectable dir ecc group 1 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	grp1        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 25;
+	} sh_md_dqrp_mmr_yuerr1_s;
+} sh_md_dqrp_mmr_yuerr1_u_t;
+#else
+typedef union sh_md_dqrp_mmr_yuerr1_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr1_regval;
+	struct {
+		mmr_t	reserved_0  : 25;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp1        : 36;
+	} sh_md_dqrp_mmr_yuerr1_s;
+} sh_md_dqrp_mmr_yuerr1_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YUERR2"                   */
+/*             uncorrectable dir ecc group 2 error register             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	grp2        : 36;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 26;
+	} sh_md_dqrp_mmr_yuerr2_s;
+} sh_md_dqrp_mmr_yuerr2_u_t;
+#else
+typedef union sh_md_dqrp_mmr_yuerr2_u {
+	mmr_t	sh_md_dqrp_mmr_yuerr2_regval;
+	struct {
+		mmr_t	reserved_0  : 26;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	grp2        : 36;
+	} sh_md_dqrp_mmr_yuerr2_s;
+} sh_md_dqrp_mmr_yuerr2_u_t;
+#endif
+
+/* ==================================================================== */
+/*                   Register "SH_MD_DQRP_MMR_YPERR"                    */
+/*                       protocol error register                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_yperr_u {
+	mmr_t	sh_md_dqrp_mmr_yperr_regval;
+	struct {
+		mmr_t	dir         : 26;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+		mmr_t	prige       : 1;
+		mmr_t	priv        : 1;
+		mmr_t	cor         : 1;
+		mmr_t	unc         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 1;
+	} sh_md_dqrp_mmr_yperr_s;
+} sh_md_dqrp_mmr_yperr_u_t;
+#else
+typedef union sh_md_dqrp_mmr_yperr_u {
+	mmr_t	sh_md_dqrp_mmr_yperr_regval;
+	struct {
+		mmr_t	reserved_0  : 1;
+		mmr_t	arm         : 1;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	mybit       : 8;
+		mmr_t	unc         : 1;
+		mmr_t	cor         : 1;
+		mmr_t	priv        : 1;
+		mmr_t	prige       : 1;
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	dir         : 26;
+	} sh_md_dqrp_mmr_yperr_s;
+} sh_md_dqrp_mmr_yperr_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_CMDTRIG"                 */
+/*                             cmd triggers                             */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	cmd0        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd3        : 8;
+		mmr_t	reserved_0  : 32;
+	} sh_md_dqrp_mmr_dir_cmdtrig_s;
+} sh_md_dqrp_mmr_dir_cmdtrig_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_cmdtrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_cmdtrig_regval;
+	struct {
+		mmr_t	reserved_0  : 32;
+		mmr_t	cmd3        : 8;
+		mmr_t	cmd2        : 8;
+		mmr_t	cmd1        : 8;
+		mmr_t	cmd0        : 8;
+	} sh_md_dqrp_mmr_dir_cmdtrig_s;
+} sh_md_dqrp_mmr_dir_cmdtrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLTRIG"                 */
+/*                          dir table trigger                           */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrp_mmr_dir_tbltrig_s;
+} sh_md_dqrp_mmr_dir_tbltrig_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_tbltrig_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tbltrig_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqrp_mmr_dir_tbltrig_s;
+} sh_md_dqrp_mmr_dir_tbltrig_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_DIR_TBLMASK"                 */
+/*                        dir table trigger mask                        */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	src         : 14;
+		mmr_t	cmd         : 8;
+		mmr_t	acc         : 2;
+		mmr_t	prige       : 1;
+		mmr_t	dirst       : 9;
+		mmr_t	mybit       : 8;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrp_mmr_dir_tblmask_s;
+} sh_md_dqrp_mmr_dir_tblmask_u_t;
+#else
+typedef union sh_md_dqrp_mmr_dir_tblmask_u {
+	mmr_t	sh_md_dqrp_mmr_dir_tblmask_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	mybit       : 8;
+		mmr_t	dirst       : 9;
+		mmr_t	prige       : 1;
+		mmr_t	acc         : 2;
+		mmr_t	cmd         : 8;
+		mmr_t	src         : 14;
+	} sh_md_dqrp_mmr_dir_tblmask_s;
+} sh_md_dqrp_mmr_dir_tblmask_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqrp_mmr_xbist_h_s;
+} sh_md_dqrp_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_h_s;
+} sh_md_dqrp_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_xbist_l_s;
+} sh_md_dqrp_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_l_s;
+} sh_md_dqrp_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_xbist_err_h_s;
+} sh_md_dqrp_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_err_h_s;
+} sh_md_dqrp_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_xbist_err_l_s;
+} sh_md_dqrp_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_xbist_err_l_s;
+} sh_md_dqrp_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 21;
+	} sh_md_dqrp_mmr_ybist_h_s;
+} sh_md_dqrp_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_1  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_h_s;
+} sh_md_dqrp_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRP_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_ybist_l_s;
+} sh_md_dqrp_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_l_s;
+} sh_md_dqrp_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_ybist_err_h_s;
+} sh_md_dqrp_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_err_h_s;
+} sh_md_dqrp_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRP_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 32;
+		mmr_t	reserved_0  : 8;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_1  : 22;
+	} sh_md_dqrp_mmr_ybist_err_l_s;
+} sh_md_dqrp_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqrp_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrp_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_1  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	reserved_0  : 8;
+		mmr_t	pat         : 32;
+	} sh_md_dqrp_mmr_ybist_err_l_s;
+} sh_md_dqrp_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqrs_mmr_xbist_h_s;
+} sh_md_dqrs_mmr_xbist_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_h_s;
+} sh_md_dqrs_mmr_xbist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_XBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_xbist_l_s;
+} sh_md_dqrs_mmr_xbist_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_l_s;
+} sh_md_dqrs_mmr_xbist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_xbist_err_h_s;
+} sh_md_dqrs_mmr_xbist_err_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_err_h_s;
+} sh_md_dqrs_mmr_xbist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_XBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_xbist_err_l_s;
+} sh_md_dqrs_mmr_xbist_err_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_xbist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_xbist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_xbist_err_l_s;
+} sh_md_dqrs_mmr_xbist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_H"                   */
+/*                    rising edge bist/fill pattern                     */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_0  : 21;
+	} sh_md_dqrs_mmr_ybist_h_s;
+} sh_md_dqrs_mmr_ybist_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_h_regval;
+	struct {
+		mmr_t	reserved_0  : 21;
+		mmr_t	arm         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_h_s;
+} sh_md_dqrs_mmr_ybist_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                  Register "SH_MD_DQRS_MMR_YBIST_L"                   */
+/*                    falling edge bist/fill pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	inv         : 1;
+		mmr_t	rot         : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_ybist_l_s;
+} sh_md_dqrs_mmr_ybist_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	rot         : 1;
+		mmr_t	inv         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_l_s;
+} sh_md_dqrs_mmr_ybist_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_H"                 */
+/*                    rising edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_ybist_err_h_s;
+} sh_md_dqrs_mmr_ybist_err_h_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_err_h_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_h_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_err_h_s;
+} sh_md_dqrs_mmr_ybist_err_h_u_t;
+#endif
+
+/* ==================================================================== */
+/*                Register "SH_MD_DQRS_MMR_YBIST_ERR_L"                 */
+/*                   falling edge bist error pattern                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	pat         : 40;
+		mmr_t	val         : 1;
+		mmr_t	more        : 1;
+		mmr_t	reserved_0  : 22;
+	} sh_md_dqrs_mmr_ybist_err_l_s;
+} sh_md_dqrs_mmr_ybist_err_l_u_t;
+#else
+typedef union sh_md_dqrs_mmr_ybist_err_l_u {
+	mmr_t	sh_md_dqrs_mmr_ybist_err_l_regval;
+	struct {
+		mmr_t	reserved_0  : 22;
+		mmr_t	more        : 1;
+		mmr_t	val         : 1;
+		mmr_t	pat         : 40;
+	} sh_md_dqrs_mmr_ybist_err_l_s;
+} sh_md_dqrs_mmr_ybist_err_l_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_JNR_DEBUG"                  */
+/*                    joiner/fct debug configuration                    */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqrs_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	px          : 1;
+		mmr_t	rw          : 1;
+		mmr_t	reserved_0  : 62;
+	} sh_md_dqrs_mmr_jnr_debug_s;
+} sh_md_dqrs_mmr_jnr_debug_u_t;
+#else
+typedef union sh_md_dqrs_mmr_jnr_debug_u {
+	mmr_t	sh_md_dqrs_mmr_jnr_debug_regval;
+	struct {
+		mmr_t	reserved_0  : 62;
+		mmr_t	rw          : 1;
+		mmr_t	px          : 1;
+	} sh_md_dqrs_mmr_jnr_debug_s;
+} sh_md_dqrs_mmr_jnr_debug_u_t;
+#endif
+
+/* ==================================================================== */
+/*                 Register "SH_MD_DQRS_MMR_YAMOPW_ERR"                 */
+/*                  amo/partial rmw ecc error register                  */
+/* ==================================================================== */
+
+#ifdef LITTLE_ENDIAN
+typedef union sh_md_dqrs_mmr_yamopw_err_u {
+	mmr_t	sh_md_dqrs_mmr_yamopw_err_regval;
+	struct {
+		mmr_t	ssyn        : 8;
+		mmr_t	scor        : 1;
+		mmr_t	sunc        : 1;
+		mmr_t	reserved_0  : 6;
+		mmr_t	rsyn        : 8;
+		mmr_t	rcor        : 1;
+		mmr_t	runc        : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_2  : 31;
+	} sh_md_dqrs_mmr_yamopw_err_s;
+} sh_md_dqrs_mmr_yamopw_err_u_t;
+#else
+typedef union sh_md_dqrs_mmr_yamopw_err_u {
+	mmr_t	sh_md_dqrs_mmr_yamopw_err_regval;
+	struct {
+		mmr_t	reserved_2  : 31;
+		mmr_t	arm         : 1;
+		mmr_t	reserved_1  : 6;
+		mmr_t	runc        : 1;
+		mmr_t	rcor        : 1;
+		mmr_t	rsyn        : 8;
+		mmr_t	reserved_0  : 6;
+		mmr_t	sunc        : 1;
+		mmr_t	scor        : 1;
+		mmr_t	ssyn        : 8;
+	} sh_md_dqrs_mmr_yamopw_err_s;
+} sh_md_dqrs_mmr_yamopw_err_u_t;
+#endif
+
+
+#endif /* _ASM_IA64_SN_SN2_SHUB_MMR_T_H */
diff -Nru a/include/asm-ia64/sn/sn2/shubio.h b/include/asm-ia64/sn/sn2/shubio.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/shubio.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,3639 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN2_SHUBIO_H
+#define _ASM_IA64_SN_SN2_SHUBIO_H
+
+#include <asm/sn/arch.h>
+
+#define HUB_WIDGET_ID_MAX 0xf
+#define IIO_NUM_ITTES   7
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+#define    IIO_WID                   0x00400000    /* Crosstalk Widget Identification */
+                                                   /* This register is also accessible from
+                                                    * Crosstalk at address 0x0.  */
+#define    IIO_WSTAT                 0x00400008    /* Crosstalk Widget Status */
+#define    IIO_WCR                   0x00400020    /* Crosstalk Widget Control Register */
+#define    IIO_ILAPR                 0x00400100    /* IO Local Access Protection Register */
+#define    IIO_ILAPO                 0x00400108    /* IO Local Access Protection Override */
+#define    IIO_IOWA                  0x00400110    /* IO Outbound Widget Access */
+#define    IIO_IIWA                  0x00400118    /* IO Inbound Widget Access */
+#define    IIO_IIDEM                 0x00400120    /* IO Inbound Device Error Mask */
+#define    IIO_ILCSR                 0x00400128    /* IO LLP Control and Status Register */
+#define    IIO_ILLR                  0x00400130    /* IO LLP Log Register    */
+#define    IIO_IIDSR                 0x00400138    /* IO Interrupt Destination */
+
+#define    IIO_IGFX0                 0x00400140    /* IO Graphics Node-Widget Map 0 */
+#define    IIO_IGFX1                 0x00400148    /* IO Graphics Node-Widget Map 1 */
+
+#define    IIO_ISCR0                 0x00400150    /* IO Scratch Register 0 */
+#define    IIO_ISCR1                 0x00400158    /* IO Scratch Register 1 */
+
+#define    IIO_ITTE1                 0x00400160    /* IO Translation Table Entry 1 */
+#define    IIO_ITTE2                 0x00400168    /* IO Translation Table Entry 2 */
+#define    IIO_ITTE3                 0x00400170    /* IO Translation Table Entry 3 */
+#define    IIO_ITTE4                 0x00400178    /* IO Translation Table Entry 4 */
+#define    IIO_ITTE5                 0x00400180    /* IO Translation Table Entry 5 */
+#define    IIO_ITTE6                 0x00400188    /* IO Translation Table Entry 6 */
+#define    IIO_ITTE7                 0x00400190    /* IO Translation Table Entry 7 */
+
+#define    IIO_IPRB0                 0x00400198    /* IO PRB Entry 0         */
+#define    IIO_IPRB8                 0x004001A0    /* IO PRB Entry 8         */
+#define    IIO_IPRB9                 0x004001A8    /* IO PRB Entry 9         */
+#define    IIO_IPRBA                 0x004001B0    /* IO PRB Entry A         */
+#define    IIO_IPRBB                 0x004001B8    /* IO PRB Entry B         */
+#define    IIO_IPRBC                 0x004001C0    /* IO PRB Entry C         */
+#define    IIO_IPRBD                 0x004001C8    /* IO PRB Entry D         */
+#define    IIO_IPRBE                 0x004001D0    /* IO PRB Entry E         */
+#define    IIO_IPRBF                 0x004001D8    /* IO PRB Entry F         */
+
+#define    IIO_IXCC                  0x004001E0    /* IO Crosstalk Credit Count Timeout */
+#define    IIO_IMEM                  0x004001E8    /* IO Miscellaneous Error Mask */
+#define    IIO_IXTT                  0x004001F0    /* IO Crosstalk Timeout Threshold */
+#define    IIO_IECLR                 0x004001F8    /* IO Error Clear Register */
+#define    IIO_IBCR                  0x00400200    /* IO BTE Control Register */
+
+#define    IIO_IXSM                  0x00400208    /* IO Crosstalk Spurious Message */
+#define    IIO_IXSS                  0x00400210    /* IO Crosstalk Spurious Sideband */
+
+#define    IIO_ILCT                  0x00400218    /* IO LLP Channel Test    */
+
+#define    IIO_IIEPH1                0x00400220    /* IO Incoming Error Packet Header, Part 1 */
+#define    IIO_IIEPH2                0x00400228    /* IO Incoming Error Packet Header, Part 2 */
+
+
+#define    IIO_ISLAPR                0x00400230    /* IO SXB Local Access Protection Regster */
+#define    IIO_ISLAPO                0x00400238    /* IO SXB Local Access Protection Override */
+
+#define    IIO_IWI                   0x00400240    /* IO Wrapper Interrupt Register */
+#define    IIO_IWEL                  0x00400248    /* IO Wrapper Error Log Register */
+#define    IIO_IWC                   0x00400250    /* IO Wrapper Control Register */
+#define    IIO_IWS                   0x00400258    /* IO Wrapper Status Register */
+#define    IIO_IWEIM                 0x00400260    /* IO Wrapper Error Interrupt Masking Register */
+
+#define    IIO_IPCA                  0x00400300    /* IO PRB Counter Adjust */
+
+#define    IIO_IPRTE0_A              0x00400308    /* IO PIO Read Address Table Entry 0, Part A */
+#define    IIO_IPRTE1_A              0x00400310    /* IO PIO Read Address Table Entry 1, Part A */
+#define    IIO_IPRTE2_A              0x00400318    /* IO PIO Read Address Table Entry 2, Part A */
+#define    IIO_IPRTE3_A               0x00400320    /* IO PIO Read Address Table Entry 3, Part A */
+#define    IIO_IPRTE4_A               0x00400328    /* IO PIO Read Address Table Entry 4, Part A */
+#define    IIO_IPRTE5_A               0x00400330    /* IO PIO Read Address Table Entry 5, Part A */
+#define    IIO_IPRTE6_A               0x00400338    /* IO PIO Read Address Table Entry 6, Part A */
+#define    IIO_IPRTE7_A               0x00400340    /* IO PIO Read Address Table Entry 7, Part A */
+
+#define    IIO_IPRTE0_B              0x00400348    /* IO PIO Read Address Table Entry 0, Part B */
+#define    IIO_IPRTE1_B              0x00400350    /* IO PIO Read Address Table Entry 1, Part B */
+#define    IIO_IPRTE2_B              0x00400358    /* IO PIO Read Address Table Entry 2, Part B */
+#define    IIO_IPRTE3_B               0x00400360    /* IO PIO Read Address Table Entry 3, Part B */
+#define    IIO_IPRTE4_B               0x00400368    /* IO PIO Read Address Table Entry 4, Part B */
+#define    IIO_IPRTE5_B               0x00400370    /* IO PIO Read Address Table Entry 5, Part B */
+#define    IIO_IPRTE6_B               0x00400378    /* IO PIO Read Address Table Entry 6, Part B */
+#define    IIO_IPRTE7_B               0x00400380    /* IO PIO Read Address Table Entry 7, Part B */
+
+#define    IIO_IPDR                  0x00400388    /* IO PIO Deallocation Register */
+#define    IIO_ICDR                  0x00400390    /* IO CRB Entry Deallocation Register */
+#define    IIO_IFDR                  0x00400398    /* IO IOQ FIFO Depth Register */
+#define    IIO_IIAP                  0x004003A0    /* IO IIQ Arbitration Parameters */
+#define    IIO_ICMR                  0x004003A8    /* IO CRB Management Register */
+#define    IIO_ICCR                  0x004003B0    /* IO CRB Control Register */
+#define    IIO_ICTO                  0x004003B8    /* IO CRB Timeout         */
+#define    IIO_ICTP                  0x004003C0    /* IO CRB Timeout Prescalar */
+
+#define    IIO_ICRB0_A               0x00400400    /* IO CRB Entry 0_A       */
+#define    IIO_ICRB0_B               0x00400408    /* IO CRB Entry 0_B       */
+#define    IIO_ICRB0_C               0x00400410    /* IO CRB Entry 0_C       */
+#define    IIO_ICRB0_D               0x00400418    /* IO CRB Entry 0_D       */
+#define    IIO_ICRB0_E               0x00400420    /* IO CRB Entry 0_E       */
+
+#define    IIO_ICRB1_A               0x00400430    /* IO CRB Entry 1_A       */
+#define    IIO_ICRB1_B               0x00400438    /* IO CRB Entry 1_B       */
+#define    IIO_ICRB1_C               0x00400440    /* IO CRB Entry 1_C       */
+#define    IIO_ICRB1_D               0x00400448    /* IO CRB Entry 1_D       */
+#define    IIO_ICRB1_E               0x00400450    /* IO CRB Entry 1_E       */
+
+#define    IIO_ICRB2_A               0x00400460    /* IO CRB Entry 2_A       */
+#define    IIO_ICRB2_B               0x00400468    /* IO CRB Entry 2_B       */
+#define    IIO_ICRB2_C               0x00400470    /* IO CRB Entry 2_C       */
+#define    IIO_ICRB2_D               0x00400478    /* IO CRB Entry 2_D       */
+#define    IIO_ICRB2_E               0x00400480    /* IO CRB Entry 2_E       */
+
+#define    IIO_ICRB3_A               0x00400490    /* IO CRB Entry 3_A       */
+#define    IIO_ICRB3_B               0x00400498    /* IO CRB Entry 3_B       */
+#define    IIO_ICRB3_C               0x004004a0    /* IO CRB Entry 3_C       */
+#define    IIO_ICRB3_D               0x004004a8    /* IO CRB Entry 3_D       */
+#define    IIO_ICRB3_E               0x004004b0    /* IO CRB Entry 3_E       */
+
+#define    IIO_ICRB4_A               0x004004c0    /* IO CRB Entry 4_A       */
+#define    IIO_ICRB4_B               0x004004c8    /* IO CRB Entry 4_B       */
+#define    IIO_ICRB4_C               0x004004d0    /* IO CRB Entry 4_C       */
+#define    IIO_ICRB4_D               0x004004d8    /* IO CRB Entry 4_D       */
+#define    IIO_ICRB4_E               0x004004e0    /* IO CRB Entry 4_E       */
+
+#define    IIO_ICRB5_A               0x004004f0    /* IO CRB Entry 5_A       */
+#define    IIO_ICRB5_B               0x004004f8    /* IO CRB Entry 5_B       */
+#define    IIO_ICRB5_C               0x00400500    /* IO CRB Entry 5_C       */
+#define    IIO_ICRB5_D               0x00400508    /* IO CRB Entry 5_D       */
+#define    IIO_ICRB5_E               0x00400510    /* IO CRB Entry 5_E       */
+
+#define    IIO_ICRB6_A               0x00400520    /* IO CRB Entry 6_A       */
+#define    IIO_ICRB6_B               0x00400528    /* IO CRB Entry 6_B       */
+#define    IIO_ICRB6_C               0x00400530    /* IO CRB Entry 6_C       */
+#define    IIO_ICRB6_D               0x00400538    /* IO CRB Entry 6_D       */
+#define    IIO_ICRB6_E               0x00400540    /* IO CRB Entry 6_E       */
+
+#define    IIO_ICRB7_A               0x00400550    /* IO CRB Entry 7_A       */
+#define    IIO_ICRB7_B               0x00400558    /* IO CRB Entry 7_B       */
+#define    IIO_ICRB7_C               0x00400560    /* IO CRB Entry 7_C       */
+#define    IIO_ICRB7_D               0x00400568    /* IO CRB Entry 7_D       */
+#define    IIO_ICRB7_E               0x00400570    /* IO CRB Entry 7_E       */
+
+#define    IIO_ICRB8_A               0x00400580    /* IO CRB Entry 8_A       */
+#define    IIO_ICRB8_B               0x00400588    /* IO CRB Entry 8_B       */
+#define    IIO_ICRB8_C               0x00400590    /* IO CRB Entry 8_C       */
+#define    IIO_ICRB8_D               0x00400598    /* IO CRB Entry 8_D       */
+#define    IIO_ICRB8_E               0x004005a0    /* IO CRB Entry 8_E       */
+
+#define    IIO_ICRB9_A               0x004005b0    /* IO CRB Entry 9_A       */
+#define    IIO_ICRB9_B               0x004005b8    /* IO CRB Entry 9_B       */
+#define    IIO_ICRB9_C               0x004005c0    /* IO CRB Entry 9_C       */
+#define    IIO_ICRB9_D               0x004005c8    /* IO CRB Entry 9_D       */
+#define    IIO_ICRB9_E               0x004005d0    /* IO CRB Entry 9_E       */
+
+#define    IIO_ICRBA_A               0x004005e0    /* IO CRB Entry A_A       */
+#define    IIO_ICRBA_B               0x004005e8    /* IO CRB Entry A_B       */
+#define    IIO_ICRBA_C               0x004005f0    /* IO CRB Entry A_C       */
+#define    IIO_ICRBA_D               0x004005f8    /* IO CRB Entry A_D       */
+#define    IIO_ICRBA_E               0x00400600    /* IO CRB Entry A_E       */
+
+#define    IIO_ICRBB_A               0x00400610    /* IO CRB Entry B_A       */
+#define    IIO_ICRBB_B               0x00400618    /* IO CRB Entry B_B       */
+#define    IIO_ICRBB_C               0x00400620    /* IO CRB Entry B_C       */
+#define    IIO_ICRBB_D               0x00400628    /* IO CRB Entry B_D       */
+#define    IIO_ICRBB_E               0x00400630    /* IO CRB Entry B_E       */
+
+#define    IIO_ICRBC_A               0x00400640    /* IO CRB Entry C_A       */
+#define    IIO_ICRBC_B               0x00400648    /* IO CRB Entry C_B       */
+#define    IIO_ICRBC_C               0x00400650    /* IO CRB Entry C_C       */
+#define    IIO_ICRBC_D               0x00400658    /* IO CRB Entry C_D       */
+#define    IIO_ICRBC_E               0x00400660    /* IO CRB Entry C_E       */
+
+#define    IIO_ICRBD_A               0x00400670    /* IO CRB Entry D_A       */
+#define    IIO_ICRBD_B               0x00400678    /* IO CRB Entry D_B       */
+#define    IIO_ICRBD_C               0x00400680    /* IO CRB Entry D_C       */
+#define    IIO_ICRBD_D               0x00400688    /* IO CRB Entry D_D       */
+#define    IIO_ICRBD_E               0x00400690    /* IO CRB Entry D_E       */
+
+#define    IIO_ICRBE_A               0x004006a0    /* IO CRB Entry E_A       */
+#define    IIO_ICRBE_B               0x004006a8    /* IO CRB Entry E_B       */
+#define    IIO_ICRBE_C               0x004006b0    /* IO CRB Entry E_C       */
+#define    IIO_ICRBE_D               0x004006b8    /* IO CRB Entry E_D       */
+#define    IIO_ICRBE_E               0x004006c0    /* IO CRB Entry E_E       */
+
+#define    IIO_ICSML                 0x00400700    /* IO CRB Spurious Message Low */
+#define    IIO_ICSMM                 0x00400708    /* IO CRB Spurious Message Middle */
+#define    IIO_ICSMH                 0x00400710    /* IO CRB Spurious Message High */
+
+#define    IIO_IDBSS                 0x00400718    /* IO Debug Submenu Select */
+
+#define    IIO_IBLS0                 0x00410000    /* IO BTE Length Status 0 */
+#define    IIO_IBSA0                 0x00410008    /* IO BTE Source Address 0 */
+#define    IIO_IBDA0                 0x00410010    /* IO BTE Destination Address 0 */
+#define    IIO_IBCT0                 0x00410018    /* IO BTE Control Terminate 0 */
+#define    IIO_IBNA0                 0x00410020    /* IO BTE Notification Address 0 */
+#define    IIO_IBIA0                 0x00410028    /* IO BTE Interrupt Address 0 */
+#define    IIO_IBLS1                 0x00420000    /* IO BTE Length Status 1 */
+#define    IIO_IBSA1                 0x00420008    /* IO BTE Source Address 1 */
+#define    IIO_IBDA1                 0x00420010    /* IO BTE Destination Address 1 */
+#define    IIO_IBCT1                 0x00420018    /* IO BTE Control Terminate 1 */
+#define    IIO_IBNA1                 0x00420020    /* IO BTE Notification Address 1 */
+#define    IIO_IBIA1                 0x00420028    /* IO BTE Interrupt Address 1 */
+
+#define    IIO_IPCR                  0x00430000    /* IO Performance Control */
+#define    IIO_IPPR                  0x00430008    /* IO Performance Profiling */
+
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register echoes some information from the         *
+ * LB_REV_ID register. It is available through Crosstalk as described   *
+ * above. The REV_NUM and MFG_NUM fields receive their values from      *
+ * the REVISION and MANUFACTURER fields in the LB_REV_ID register.      *
+ * The PART_NUM field's value is the Crosstalk device ID number that    *
+ * Steve Miller assigned to the SHub chip.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wid_u {
+	shubreg_t	ii_wid_regval;
+	struct	{
+		shubreg_t	w_rsvd_1		  :	 1;
+		shubreg_t	w_mfg_num		  :	11;
+		shubreg_t	w_part_num		  :	16;
+		shubreg_t	w_rev_num		  :	 4;
+		shubreg_t	w_rsvd			  :	32;
+	} ii_wid_fld_s;
+} ii_wid_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  The fields in this register are set upon detection of an error      *
+ * and cleared by various mechanisms, as explained in the               *
+ * description.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wstat_u {
+	shubreg_t	ii_wstat_regval;
+	struct	{
+		shubreg_t	w_pending		  :	 4;
+		shubreg_t	w_xt_crd_to		  :	 1;
+		shubreg_t	w_xt_tail_to		  :	 1;
+		shubreg_t	w_rsvd_3		  :	 3;
+		shubreg_t       w_tx_mx_rty               :      1;
+		shubreg_t	w_rsvd_2		  :	 6;
+		shubreg_t	w_llp_tx_cnt		  :	 8;
+		shubreg_t	w_rsvd_1		  :	 8;
+		shubreg_t	w_crazy			  :	 1;
+		shubreg_t	w_rsvd			  :	31;
+	} ii_wstat_fld_s;
+} ii_wstat_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This is a read-write enabled register. It controls     *
+ * various aspects of the Crosstalk flow control.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_wcr_u {
+	shubreg_t	ii_wcr_regval;
+	struct	{
+		shubreg_t	w_wid			  :	 4;
+		shubreg_t	w_tag			  :	 1;
+		shubreg_t	w_rsvd_1		  :	 8;
+		shubreg_t	w_dst_crd		  :	 3;
+		shubreg_t	w_f_bad_pkt		  :	 1;
+		shubreg_t	w_dir_con		  :	 1;
+		shubreg_t	w_e_thresh		  :	 5;
+		shubreg_t	w_rsvd			  :	41;
+	} ii_wcr_fld_s;
+} ii_wcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register's value is a bit vector that guards      *
+ * access to local registers within the II as well as to external       *
+ * Crosstalk widgets. Each bit in the register corresponds to a         *
+ * particular region in the system; a region consists of one, two or    *
+ * four nodes (depending on the value of the REGION_SIZE field in the   *
+ * LB_REV_ID register, which is documented in Section 8.3.1.1). The     *
+ * protection provided by this register applies to PIO read             *
+ * operations as well as PIO write operations. The II will perform a    *
+ * PIO read or write request only if the bit for the requestor's        *
+ * region is set; otherwise, the II will not perform the requested      *
+ * operation and will return an error response. When a PIO read or      *
+ * write request targets an external Crosstalk widget, then not only    *
+ * must the bit for the requestor's region be set in the ILAPR, but     *
+ * also the target widget's bit in the IOWA register must be set in     *
+ * order for the II to perform the requested operation; otherwise,      *
+ * the II will return an error response. Hence, the protection          *
+ * provided by the IOWA register supplements the protection provided    *
+ * by the ILAPR for requests that target external Crosstalk widgets.    *
+ * This register itself can be accessed only by the nodes whose         *
+ * region ID bits are enabled in this same register. It can also be     *
+ * accessed through the IAlias space by the local processors.           *
+ * The reset value of this register allows access by all nodes.         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapr_u {
+	shubreg_t	ii_ilapr_regval;
+	struct  {
+		shubreg_t	i_region                  :	64;
+	} ii_ilapr_fld_s;
+} ii_ilapr_u_t;
+
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  A write to this register of the 64-bit value           *
+ * "SGIrules" in ASCII, will cause the bit in the ILAPR register        *
+ * corresponding to the region of the requestor to be set (allow        *
+ * access). A write of any other value will be ignored. Access          *
+ * protection for this register is "SGIrules".                          *
+ * This register can also be accessed through the IAlias space.         *
+ * However, this access will not change the access permissions in the   *
+ * ILAPR.                                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilapo_u {
+	shubreg_t	ii_ilapo_regval;
+	struct	{
+		shubreg_t	i_io_ovrride            :	64;
+	} ii_ilapo_fld_s;
+} ii_ilapo_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register qualifies all the PIO and Graphics writes launched    *
+ * from the SHUB towards a widget.                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iowa_u {
+	shubreg_t	ii_iowa_regval;
+	struct	{
+		shubreg_t	i_w0_oac		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 7;
+                shubreg_t       i_wx_oac                  :      8;
+		shubreg_t	i_rsvd			  :	48;
+	} ii_iowa_fld_s;
+} ii_iowa_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the requests launched      *
+ * from a widget towards the Shub. This register is intended to be      *
+ * used by software in case of misbehaving widgets.                     *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiwa_u {
+	shubreg_t	ii_iiwa_regval;
+	struct  {
+		shubreg_t	i_w0_iac                  :	 1;
+		shubreg_t	i_rsvd_1		  :	 7;
+		shubreg_t	i_wx_iac		  :	 8;
+		shubreg_t	i_rsvd			  :	48;
+	} ii_iiwa_fld_s;
+} ii_iiwa_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the operations launched    *
+ * from a widget towards the SHub. It allows individual access          *
+ * control for up to 8 devices per widget. A device refers to           *
+ * individual DMA master hosted by a widget.                            *
+ * The bits in each field of this register are cleared by the Shub      *
+ * upon detection of an error which requires the device to be           *
+ * disabled. These fields assume that 0=TNUM=7 (i.e., Bridge-centric    *
+ * Crosstalk). Whether or not a device has access rights to this        *
+ * Shub is determined by an AND of the device enable bit in the         *
+ * appropriate field of this register and the corresponding bit in      *
+ * the Wx_IAC field (for the widget which this device belongs to).      *
+ * The bits in this field are set by writing a 1 to them. Incoming      *
+ * replies from Crosstalk are not subject to this access control        *
+ * mechanism.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidem_u {
+	shubreg_t	ii_iidem_regval;
+	struct	{
+		shubreg_t	i_w8_dxs		  :	 8;
+		shubreg_t	i_w9_dxs		  :	 8;
+		shubreg_t	i_wa_dxs		  :	 8;
+		shubreg_t	i_wb_dxs		  :	 8;
+		shubreg_t	i_wc_dxs		  :	 8;
+		shubreg_t	i_wd_dxs		  :	 8;
+		shubreg_t	i_we_dxs		  :	 8;
+		shubreg_t	i_wf_dxs		  :	 8;
+	} ii_iidem_fld_s;
+} ii_iidem_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the various programmable fields necessary    *
+ * for controlling and observing the LLP signals.                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilcsr_u {
+	shubreg_t	ii_ilcsr_regval;
+	struct  {
+		shubreg_t	i_nullto                  :	 6;
+		shubreg_t	i_rsvd_4		  :	 2;
+		shubreg_t	i_wrmrst		  :	 1;
+		shubreg_t	i_rsvd_3		  :	 1;
+		shubreg_t	i_llp_en		  :	 1;
+		shubreg_t	i_bm8			  :	 1;
+		shubreg_t	i_llp_stat		  :	 2;
+		shubreg_t	i_remote_power		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 1;
+		shubreg_t	i_maxrtry		  :	10;
+		shubreg_t	i_d_avail_sel		  :	 2;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_maxbrst		  :	10;
+                shubreg_t       i_rsvd                    :     22;
+
+	} ii_ilcsr_fld_s;
+} ii_ilcsr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This is simply a status registers that monitors the LLP error       *
+ * rate.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_illr_u {
+	shubreg_t	ii_illr_regval;
+	struct	{
+		shubreg_t	i_sn_cnt		  :	16;
+		shubreg_t	i_cb_cnt		  :	16;
+		shubreg_t	i_rsvd			  :	32;
+	} ii_illr_fld_s;
+} ii_illr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  All II-detected non-BTE error interrupts are           *
+ * specified via this register.                                         *
+ * NOTE: The PI interrupt register address is hardcoded in the II. If   *
+ * PI_ID==0, then the II sends an interrupt request (Duplonet PWRI      *
+ * packet) to address offset 0x0180_0090 within the local register      *
+ * address space of PI0 on the node specified by the NODE field. If     *
+ * PI_ID==1, then the II sends the interrupt request to address         *
+ * offset 0x01A0_0090 within the local register address space of PI1    *
+ * on the node specified by the NODE field.                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iidsr_u {
+	shubreg_t	ii_iidsr_regval;
+	struct  {
+		shubreg_t	i_level                   :	 8;
+		shubreg_t	i_pi_id			  :	 1;
+		shubreg_t	i_node			  :	11;
+		shubreg_t       i_rsvd_3                  :      4;
+		shubreg_t	i_enable		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_int_sent		  :	 1;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t	i_pi0_forward_int	  :	 1;
+		shubreg_t	i_pi1_forward_int	  :	 1;
+		shubreg_t	i_rsvd			  :	30;
+	} ii_iidsr_fld_s;
+} ii_iidsr_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx0_u {
+	shubreg_t	ii_igfx0_regval;
+	struct	{
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t       i_pi_id                   :      1;
+		shubreg_t	i_n_num			  :	12;
+		shubreg_t       i_p_num                   :      1;
+		shubreg_t       i_rsvd                    :     46;
+	} ii_igfx0_fld_s;
+} ii_igfx0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this register. This register is used     *
+ * for matching up the incoming responses from the graphics widget to   *
+ * the processor that initiated the graphics operation. The             *
+ * write-responses are converted to graphics credits and returned to    *
+ * the processor so that the processor interface can manage the flow    *
+ * control.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_igfx1_u {
+	shubreg_t	ii_igfx1_regval;
+	struct  {
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t       i_pi_id                   :      1;
+		shubreg_t	i_n_num			  :	12;
+		shubreg_t       i_p_num                   :      1;
+		shubreg_t       i_rsvd                    :     46;
+	} ii_igfx1_fld_s;
+} ii_igfx1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr0_u {
+	shubreg_t	ii_iscr0_regval;
+	struct  {
+		shubreg_t	i_scratch                 :	64;
+	} ii_iscr0_fld_s;
+} ii_iscr0_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are two instances of this registers. These registers are      *
+ * used as scratch registers for software use.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iscr1_u {
+	shubreg_t	ii_iscr1_regval;
+	struct  {
+		shubreg_t	i_scratch                 :	64;
+	} ii_iscr1_fld_s;
+} ii_iscr1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       * 
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte1_u {
+	shubreg_t	ii_itte1_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t	i_iosp			  :	 1;
+		shubreg_t	i_rsvd			  :	51;
+	} ii_itte1_fld_s;
+} ii_itte1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte2_u {
+	shubreg_t	ii_itte2_regval;
+	struct	{
+		shubreg_t	i_offset		  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_w_num			  :	 4;
+		shubreg_t	i_iosp			  :	 1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte2_fld_s;
+} ii_itte2_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte3_u {
+	shubreg_t	ii_itte3_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte3_fld_s;
+} ii_itte3_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the SHub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte4_u {
+	shubreg_t	ii_itte4_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte4_fld_s;
+} ii_itte4_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a SHub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte5_u {
+	shubreg_t	ii_itte5_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte5_fld_s;
+} ii_itte5_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the Shub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte6_u {
+	shubreg_t	ii_itte6_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t       i_rsvd_1                  :      3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte6_fld_s;
+} ii_itte6_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are seven instances of translation table entry   *
+ * registers. Each register maps a Shub Big Window to a 48-bit          *
+ * address on Crosstalk.                                                *
+ * For M-mode (128 nodes, 8 GBytes/node), SysAD[31:29] (Big Window      *
+ * number) are used to select one of these 7 registers. The Widget      *
+ * number field is then derived from the W_NUM field for synthesizing   *
+ * a Crosstalk packet. The 5 bits of OFFSET are concatenated with       *
+ * SysAD[28:0] to form Crosstalk[33:0]. The upper Crosstalk[47:34]      *
+ * are padded with zeros. Although the maximum Crosstalk space          *
+ * addressable by the Shub is thus the lower 16 GBytes per widget       *
+ * (M-mode), however only <SUP >7</SUP>/<SUB >32nds</SUB> of this       *
+ * space can be accessed.                                               *
+ * For the N-mode (256 nodes, 4 GBytes/node), SysAD[30:28] (Big         *
+ * Window number) are used to select one of these 7 registers. The      *
+ * Widget number field is then derived from the W_NUM field for         *
+ * synthesizing a Crosstalk packet. The 5 bits of OFFSET are            *
+ * concatenated with SysAD[27:0] to form Crosstalk[33:0]. The IOSP      *
+ * field is used as Crosstalk[47], and remainder of the Crosstalk       *
+ * address bits (Crosstalk[46:34]) are always zero. While the maximum   *
+ * Crosstalk space addressable by the SHub is thus the lower            *
+ * 8-GBytes per widget (N-mode), only <SUP >7</SUP>/<SUB >32nds</SUB>   *
+ * of this space can be accessed.                                       *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_itte7_u {
+	shubreg_t	ii_itte7_regval;
+	struct  {
+		shubreg_t	i_offset                  :	 5;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t       i_w_num                   :      4;
+		shubreg_t       i_iosp                    :      1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_itte7_fld_s;
+} ii_itte7_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb0_u {
+	shubreg_t	ii_iprb0_regval;
+	struct  {
+		shubreg_t	i_c                       :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t       i_rsvd_2                  :      2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprb0_fld_s;
+} ii_iprb0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb8_u {
+	shubreg_t	ii_iprb8_regval;
+	struct  {
+		shubreg_t	i_c                       :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t       i_rsvd_2                  :      2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t       i_rsvd_1                  :      2;
+		shubreg_t       i_m                       :      2;
+		shubreg_t       i_f                       :      1;
+		shubreg_t       i_of_cnt                  :      5;
+		shubreg_t       i_error                   :      1;
+		shubreg_t       i_rd_to                   :      1;
+		shubreg_t       i_spur_wr                 :      1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t       i_rsvd                    :     11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprb8_fld_s;
+} ii_iprb8_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprb9_u {
+	shubreg_t	ii_iprb9_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprb9_fld_s;
+} ii_iprb9_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.        *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprba_u {
+	shubreg_t	ii_iprba_regval;
+	struct  {
+		shubreg_t	i_c                       :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t       i_rsvd_2                  :      2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprba_fld_s;
+} ii_iprba_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbb_u {
+	shubreg_t	ii_iprbb_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbb_fld_s;
+} ii_iprbb_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbc_u {
+	shubreg_t	ii_iprbc_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbc_fld_s;
+} ii_iprbc_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbd_u {
+	shubreg_t	ii_iprbd_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbd_fld_s;
+} ii_iprbd_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of SHub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbe_u {
+	shubreg_t	ii_iprbe_regval;
+	struct	{
+		shubreg_t	i_c			  :	 8;
+		shubreg_t	i_na			  :	14;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_nb			  :	14;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_m			  :	 2;
+		shubreg_t	i_f			  :	 1;
+		shubreg_t	i_of_cnt		  :	 5;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rd_to			  :	 1;
+		shubreg_t	i_spur_wr		  :	 1;
+		shubreg_t	i_spur_rd		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+		shubreg_t	i_mult_err		  :	 1;
+	} ii_iprbe_fld_s;
+} ii_iprbe_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 9 instances of this register, one per        *
+ * actual widget in this implementation of Shub and Crossbow.           *
+ * Note: Crossbow only has ports for Widgets 8 through F, widget 0      *
+ * refers to Crossbow's internal space.                                 *
+ * This register contains the state elements per widget that are        *
+ * necessary to manage the PIO flow control on Crosstalk and on the     *
+ * Router Network. See the PIO Flow Control chapter for a complete      *
+ * description of this register                                         *
+ * The SPUR_WR bit requires some explanation. When this register is     *
+ * written, the new value of the C field is captured in an internal     *
+ * register so the hardware can remember what the programmer wrote      *
+ * into the credit counter. The SPUR_WR bit sets whenever the C field   *
+ * increments above this stored value, which indicates that there       *
+ * have been more responses received than requests sent. The SPUR_WR    *
+ * bit cannot be cleared until a value is written to the IPRBx          *
+ * register; the write will correct the C field and capture its new     *
+ * value in the internal register. Even if IECLR[E_PRB_x] is set, the   *
+ * SPUR_WR bit will persist if IPRBx hasn't yet been written.           *
+ * .                                                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprbf_u {
+        shubreg_t       ii_iprbf_regval;
+        struct  {
+                shubreg_t       i_c                       :      8;
+                shubreg_t       i_na                      :     14;
+                shubreg_t       i_rsvd_2                  :      2;
+                shubreg_t       i_nb                      :     14;
+                shubreg_t       i_rsvd_1                  :      2;
+                shubreg_t       i_m                       :      2;
+                shubreg_t       i_f                       :      1;
+                shubreg_t       i_of_cnt                  :      5;
+                shubreg_t       i_error                   :      1;
+                shubreg_t       i_rd_to                   :      1;
+                shubreg_t       i_spur_wr                 :      1;
+                shubreg_t       i_spur_rd                 :      1;
+                shubreg_t       i_rsvd                    :     11;
+                shubreg_t       i_mult_err                :      1;
+        } ii_iprbe_fld_s;
+} ii_iprbf_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register specifies the timeout value to use for monitoring     *
+ * Crosstalk credits which are used outbound to Crosstalk. An           *
+ * internal counter called the Crosstalk Credit Timeout Counter         *
+ * increments every 128 II clocks. The counter starts counting          *
+ * anytime the credit count drops below a threshold, and resets to      *
+ * zero (stops counting) anytime the credit count is at or above the    *
+ * threshold. The threshold is 1 credit in direct connect mode and 2    *
+ * in Crossbow connect mode. When the internal Crosstalk Credit         *
+ * Timeout Counter reaches the value programmed in this register, a     *
+ * Crosstalk Credit Timeout has occurred. The internal counter is not   *
+ * readable from software, and stops counting at its maximum value,     *
+ * so it cannot cause more than one interrupt.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixcc_u {
+	shubreg_t	ii_ixcc_regval;
+	struct  {
+		shubreg_t	i_time_out                :	26;
+		shubreg_t	i_rsvd			  :	38;
+	} ii_ixcc_fld_s;
+} ii_ixcc_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register qualifies all the PIO and DMA            *
+ * operations launched from widget 0 towards the SHub. In               *
+ * addition, it also qualifies accesses by the BTE streams.             *
+ * The bits in each field of this register are cleared by the SHub      *
+ * upon detection of an error which requires widget 0 or the BTE        *
+ * streams to be terminated. Whether or not widget x has access         *
+ * rights to this SHub is determined by an AND of the device            *
+ * enable bit in the appropriate field of this register and bit 0 in    *
+ * the Wx_IAC field. The bits in this field are set by writing a 1 to   *
+ * them. Incoming replies from Crosstalk are not subject to this        *
+ * access control mechanism.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_imem_u {
+	shubreg_t	ii_imem_regval;
+	struct  {
+		shubreg_t	i_w0_esd                  :	 1;
+		shubreg_t	i_rsvd_3		  :	 3;
+		shubreg_t	i_b0_esd		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_b1_esd		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_clr_precise		  :	 1;
+		shubreg_t       i_rsvd                    :     51;
+	} ii_imem_fld_s;
+} ii_imem_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register specifies the timeout value to use for   *
+ * monitoring Crosstalk tail flits coming into the Shub in the          *
+ * TAIL_TO field. An internal counter associated with this register     *
+ * is incremented every 128 II internal clocks (7 bits). The counter    *
+ * starts counting anytime a header micropacket is received and stops   *
+ * counting (and resets to zero) any time a micropacket with a Tail     *
+ * bit is received. Once the counter reaches the threshold value        *
+ * programmed in this register, it generates an interrupt to the        *
+ * processor that is programmed into the IIDSR. The counter saturates   *
+ * (does not roll over) at its maximum value, so it cannot cause        *
+ * another interrupt until after it is cleared.                         *
+ * The register also contains the Read Response Timeout values. The     *
+ * Prescalar is 23 bits, and counts II clocks. An internal counter      *
+ * increments on every II clock and when it reaches the value in the    *
+ * Prescalar field, all IPRTE registers with their valid bits set       *
+ * have their Read Response timers bumped. Whenever any of them match   *
+ * the value in the RRSP_TO field, a Read Response Timeout has          *
+ * occurred, and error handling occurs as described in the Error        *
+ * Handling section of this document.                                   *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixtt_u {
+	shubreg_t	ii_ixtt_regval;
+	struct  {
+		shubreg_t	i_tail_to                 :	26;
+		shubreg_t	i_rsvd_1		  :	 6;
+		shubreg_t	i_rrsp_ps		  :	23;
+		shubreg_t	i_rrsp_to		  :	 5;
+		shubreg_t	i_rsvd			  :	 4;
+	} ii_ixtt_fld_s;
+} ii_ixtt_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing a 1 to the fields of this register clears the appropriate   *
+ * error bits in other areas of SHub. Note that when the                *
+ * E_PRB_x bits are used to clear error bits in PRB registers,          *
+ * SPUR_RD and SPUR_WR may persist, because they require additional     *
+ * action to clear them. See the IPRBx and IXSS Register                *
+ * specifications.                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ieclr_u {
+	shubreg_t	ii_ieclr_regval;
+	struct  {
+		shubreg_t	i_e_prb_0                 :	 1;
+		shubreg_t	i_rsvd			  :	 7;
+		shubreg_t	i_e_prb_8		  :	 1;
+		shubreg_t	i_e_prb_9		  :	 1;
+		shubreg_t	i_e_prb_a		  :	 1;
+		shubreg_t	i_e_prb_b		  :	 1;
+		shubreg_t	i_e_prb_c		  :	 1;
+		shubreg_t	i_e_prb_d		  :	 1;
+		shubreg_t	i_e_prb_e		  :	 1;
+		shubreg_t	i_e_prb_f		  :	 1;
+		shubreg_t	i_e_crazy		  :	 1;
+		shubreg_t	i_e_bte_0		  :	 1;
+		shubreg_t	i_e_bte_1		  :	 1;
+		shubreg_t	i_reserved_1		  :	10;
+		shubreg_t	i_spur_rd_hdr		  :	 1;
+		shubreg_t	i_cam_intr_to		  :	 1;
+		shubreg_t	i_cam_overflow		  :	 1;
+		shubreg_t	i_cam_read_miss		  :	 1;
+		shubreg_t	i_ioq_rep_underflow	  :	 1;
+		shubreg_t	i_ioq_req_underflow	  :	 1;
+		shubreg_t	i_ioq_rep_overflow	  :	 1;
+		shubreg_t	i_ioq_req_overflow	  :	 1;
+		shubreg_t	i_iiq_rep_overflow	  :	 1;
+		shubreg_t	i_iiq_req_overflow	  :	 1;
+		shubreg_t	i_ii_xn_rep_cred_overflow :	 1;
+		shubreg_t	i_ii_xn_req_cred_overflow :	 1;
+		shubreg_t	i_ii_xn_invalid_cmd	  :	 1;
+		shubreg_t	i_xn_ii_invalid_cmd	  :	 1;
+		shubreg_t	i_reserved_2		  :	21;
+	} ii_ieclr_fld_s;
+} ii_ieclr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register controls both BTEs. SOFT_RESET is intended for        *
+ * recovery after an error. COUNT controls the total number of CRBs     *
+ * that both BTEs (combined) can use, which affects total BTE           *
+ * bandwidth.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibcr_u {
+	shubreg_t	ii_ibcr_regval;
+	struct  {
+		shubreg_t	i_count                   :	 4;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_soft_reset		  :	 1;
+		shubreg_t	i_rsvd			  :	55;
+	} ii_ibcr_fld_s;
+} ii_ibcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the header of a spurious read response       *
+ * received from Crosstalk. A spurious read response is defined as a    *
+ * read response received by II from a widget for which (1) the SIDN    *
+ * has a value between 1 and 7, inclusive (II never sends requests to   *
+ * these widgets (2) there is no valid IPRTE register which             *
+ * corresponds to the TNUM, or (3) the widget indicated in SIDN is      *
+ * not the same as the widget recorded in the IPRTE register            *
+ * referenced by the TNUM. If this condition is true, and if the        *
+ * IXSS[VALID] bit is clear, then the header of the spurious read       *
+ * response is capture in IXSM and IXSS, and IXSS[VALID] is set. The    *
+ * errant header is thereby captured, and no further spurious read      *
+ * respones are captured until IXSS[VALID] is cleared by setting the    *
+ * appropriate bit in IECLR.Everytime a spurious read response is       *
+ * detected, the SPUR_RD bit of the PRB corresponding to the incoming   *
+ * message's SIDN field is set. This always happens, regarless of       *
+ * whether a header is captured. The programmer should check            *
+ * IXSM[SIDN] to determine which widget sent the spurious response,     *
+ * because there may be more than one SPUR_RD bit set in the PRB        *
+ * registers. The widget indicated by IXSM[SIDN] was the first          *
+ * spurious read response to be received since the last time            *
+ * IXSS[VALID] was clear. The SPUR_RD bit of the corresponding PRB      *
+ * will be set. Any SPUR_RD bits in any other PRB registers indicate    *
+ * spurious messages from other widets which were detected after the    *
+ * header was captured..                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixsm_u {
+	shubreg_t	ii_ixsm_regval;
+	struct  {
+		shubreg_t	i_byte_en                 :	32;
+		shubreg_t	i_reserved		  :	 1;
+		shubreg_t	i_tag			  :	 3;
+		shubreg_t	i_alt_pactyp		  :	 4;
+		shubreg_t	i_bo			  :	 1;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_vbpm			  :	 1;
+		shubreg_t	i_gbr			  :	 1;
+		shubreg_t	i_ds			  :	 2;
+		shubreg_t	i_ct			  :	 1;
+		shubreg_t	i_tnum			  :	 5;
+		shubreg_t	i_pactyp		  :	 4;
+		shubreg_t	i_sidn			  :	 4;
+		shubreg_t	i_didn			  :	 4;
+	} ii_ixsm_fld_s;
+} ii_ixsm_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the sideband bits of a spurious read         *
+ * response received from Crosstalk.                                    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ixss_u {
+	shubreg_t	ii_ixss_regval;
+	struct  {
+		shubreg_t	i_sideband                :	 8;
+		shubreg_t	i_rsvd			  :	55;
+		shubreg_t	i_valid			  :	 1;
+	} ii_ixss_fld_s;
+} ii_ixss_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register enables software to access the II LLP's test port.    *
+ * Refer to the LLP 2.5 documentation for an explanation of the test    *
+ * port. Software can write to this register to program the values      *
+ * for the control fields (TestErrCapture, TestClear, TestFlit,         *
+ * TestMask and TestSeed). Similarly, software can read from this       *
+ * register to obtain the values of the test port's status outputs      *
+ * (TestCBerr, TestValid and TestData).                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ilct_u {
+	shubreg_t	ii_ilct_regval;
+	struct  {
+		shubreg_t	i_test_seed               :	20;
+		shubreg_t	i_test_mask               :	 8;
+		shubreg_t	i_test_data               :	20;
+		shubreg_t	i_test_valid              :	 1;
+		shubreg_t	i_test_cberr              :	 1;
+		shubreg_t	i_test_flit               :	 3;
+		shubreg_t	i_test_clear              :	 1;
+		shubreg_t	i_test_err_capture        :	 1;
+		shubreg_t	i_rsvd                    :	 9;
+	} ii_ilct_fld_s;
+} ii_ilct_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  If the II detects an illegal incoming Duplonet packet (request or   *
+ * reply) when VALID==0 in the IIEPH1 register, then it saves the       *
+ * contents of the packet's header flit in the IIEPH1 and IIEPH2        *
+ * registers, sets the VALID bit in IIEPH1, clears the OVERRUN bit,     *
+ * and assigns a value to the ERR_TYPE field which indicates the        *
+ * specific nature of the error. The II recognizes four different       *
+ * types of errors: short request packets (ERR_TYPE==2), short reply    *
+ * packets (ERR_TYPE==3), long request packets (ERR_TYPE==4) and long   *
+ * reply packets (ERR_TYPE==5). The encodings for these types of        *
+ * errors were chosen to be consistent with the same types of errors    *
+ * indicated by the ERR_TYPE field in the LB_ERROR_HDR1 register (in    *
+ * the LB unit). If the II detects an illegal incoming Duplonet         *
+ * packet when VALID==1 in the IIEPH1 register, then it merely sets     *
+ * the OVERRUN bit to indicate that a subsequent error has happened,    *
+ * and does nothing further.                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph1_u {
+	shubreg_t	ii_iieph1_regval;
+	struct	{
+		shubreg_t	i_command		  :	 7;
+		shubreg_t	i_rsvd_5		  :	 1;
+		shubreg_t	i_suppl			  :	14;
+		shubreg_t	i_rsvd_4		  :	 1;
+		shubreg_t	i_source		  :	14;
+		shubreg_t	i_rsvd_3		  :	 1;
+		shubreg_t	i_err_type		  :	 4;
+		shubreg_t	i_rsvd_2		  :	 4;
+		shubreg_t	i_overrun		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_valid			  :	 1;
+		shubreg_t	i_rsvd			  :	13;
+	} ii_iieph1_fld_s;
+} ii_iieph1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register holds the Address field from the header flit of an    *
+ * incoming erroneous Duplonet packet, along with the tail bit which    *
+ * accompanied this header flit. This register is essentially an        *
+ * extension of IIEPH1. Two registers were necessary because the 64     *
+ * bits available in only a single register were insufficient to        *
+ * capture the entire header flit of an erroneous packet.               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iieph2_u {
+	shubreg_t	ii_iieph2_regval;
+	struct  {
+		shubreg_t	i_rsvd_0		  :	 3;
+		shubreg_t	i_address                 :	47;
+		shubreg_t	i_rsvd_1		  :	10;
+		shubreg_t	i_tail			  :	 1;
+		shubreg_t	i_rsvd			  :	 3;
+	} ii_iieph2_fld_s;
+} ii_iieph2_u_t;
+
+
+/******************************/
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register's value is a bit vector that guards access from SXBs  *
+ * to local registers within the II as well as to external Crosstalk    *
+ * widgets								*
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapr_u {
+	shubreg_t	ii_islapr_regval;
+	struct  {
+		shubreg_t	i_region		  :	64;
+	} ii_islapr_fld_s;
+} ii_islapr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register of the 56-bit value "Pup+Bun" will cause	*
+ * the bit in the ISLAPR register corresponding to the region of the	*
+ * requestor to be set (access allowed).				(
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_islapo_u {
+	shubreg_t	ii_islapo_regval;
+	struct  {
+		shubreg_t	i_io_sbx_ovrride	  :	56;
+		shubreg_t	i_rsvd			  :	 8;
+	} ii_islapo_fld_s;
+} ii_islapo_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Determines how long the wrapper will wait aftr an interrupt is	*
+ * initially issued from the II before it times out the outstanding	*
+ * interrupt and drops it from the interrupt queue.			* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwi_u {
+	shubreg_t	ii_iwi_regval;
+	struct  {
+		shubreg_t	i_prescale		  :	24;
+		shubreg_t	i_rsvd			  :	 8;
+		shubreg_t	i_timeout		  :	 8;
+		shubreg_t	i_rsvd1			  :	 8;
+		shubreg_t	i_intrpt_retry_period	  :	 8;
+		shubreg_t	i_rsvd2			  :	 8;
+	} ii_iwi_fld_s;
+} ii_iwi_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Log errors which have occurred in the II wrapper. The errors are	*
+ * cleared by writing to the IECLR register.				* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwel_u {
+	shubreg_t	ii_iwel_regval;
+	struct  {
+		shubreg_t	i_intr_timed_out	  :	 1;
+		shubreg_t	i_rsvd			  :	 7;
+		shubreg_t	i_cam_overflow		  :	 1;
+		shubreg_t	i_cam_read_miss		  :	 1;
+		shubreg_t	i_rsvd1			  :	 2;
+		shubreg_t	i_ioq_rep_underflow	  :	 1;
+		shubreg_t	i_ioq_req_underflow	  :	 1;
+		shubreg_t	i_ioq_rep_overflow	  :	 1;
+		shubreg_t	i_ioq_req_overflow	  :	 1;
+		shubreg_t	i_iiq_rep_overflow	  :	 1;
+		shubreg_t	i_iiq_req_overflow	  :	 1;
+		shubreg_t	i_rsvd2			  :	 6;
+		shubreg_t	i_ii_xn_rep_cred_over_under:	 1;
+		shubreg_t	i_ii_xn_req_cred_over_under:	 1;
+		shubreg_t	i_rsvd3			  :	 6;
+		shubreg_t	i_ii_xn_invalid_cmd	  :	 1;
+		shubreg_t	i_xn_ii_invalid_cmd	  :	 1;
+		shubreg_t	i_rsvd4			  :	30;
+	} ii_iwel_fld_s;
+} ii_iwel_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Controls the II wrapper.						* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iwc_u {
+	shubreg_t	ii_iwc_regval;
+	struct  {
+		shubreg_t	i_dma_byte_swap		  :	 1;
+		shubreg_t	i_rsvd			  :	 3;
+		shubreg_t	i_cam_read_lines_reset	  :	 1;
+		shubreg_t	i_rsvd1			  :	 3;
+		shubreg_t	i_ii_xn_cred_over_under_log:	 1;
+		shubreg_t	i_rsvd2			  :	19;
+		shubreg_t	i_xn_rep_iq_depth	  :	 5;
+		shubreg_t	i_rsvd3			  :	 3;
+		shubreg_t	i_xn_req_iq_depth	  :	 5;
+		shubreg_t	i_rsvd4			  :	 3;
+		shubreg_t	i_iiq_depth		  :	 6;
+		shubreg_t	i_rsvd5			  :	12;
+		shubreg_t	i_force_rep_cred	  :	 1;
+		shubreg_t	i_force_req_cred	  :	 1;
+	} ii_iwc_fld_s;
+} ii_iwc_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Status in the II wrapper.						* 
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iws_u {
+	shubreg_t	ii_iws_regval;
+	struct  {
+		shubreg_t	i_xn_rep_iq_credits	  :	 5;
+		shubreg_t	i_rsvd			  :	 3;
+		shubreg_t	i_xn_req_iq_credits	  :	 5;
+		shubreg_t	i_rsvd1			  :	51;
+	} ii_iws_fld_s;
+} ii_iws_u_t;
+
+/************************************************************************
+ *                                                                      *
+ *  Masks errors in the IWEL register.					*
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iweim_u {
+	shubreg_t	ii_iweim_regval;
+	struct  {
+		shubreg_t	i_intr_timed_out	  :	 1;
+		shubreg_t	i_rsvd			  :	 7;
+		shubreg_t	i_cam_overflow		  :	 1;
+		shubreg_t	i_cam_read_miss		  :	 1;
+		shubreg_t	i_rsvd1			  :	 2;
+		shubreg_t	i_ioq_rep_underflow	  :	 1;
+		shubreg_t	i_ioq_req_underflow	  :	 1;
+		shubreg_t	i_ioq_rep_overflow	  :	 1;
+		shubreg_t	i_ioq_req_overflow	  :	 1;
+		shubreg_t	i_iiq_rep_overflow	  :	 1;
+		shubreg_t	i_iiq_req_overflow	  :	 1;
+		shubreg_t	i_rsvd2			  :	 6;
+		shubreg_t	i_ii_xn_rep_cred_overflow :	 1;
+		shubreg_t	i_ii_xn_req_cred_overflow :	 1;
+		shubreg_t	i_rsvd3			  :	 6;
+		shubreg_t	i_ii_xn_invalid_cmd	  :	 1;
+		shubreg_t	i_xn_ii_invalid_cmd	  :	 1;
+		shubreg_t	i_rsvd4			  :	30;
+	} ii_iweim_fld_s;
+} ii_iweim_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a particular field in the           *
+ * corresponding widget's PRB entry to be adjusted up or down by 1.     *
+ * This counter should be used when recovering from error and reset     *
+ * conditions. Note that software would be capable of causing           *
+ * inadvertent overflow or underflow of these counters.                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipca_u {
+	shubreg_t	ii_ipca_regval;
+	struct  {
+		shubreg_t	i_wid                     :	 4;
+		shubreg_t	i_adjust		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_field			  :	 2;
+		shubreg_t	i_rsvd			  :	54;
+	} ii_ipca_fld_s;
+} ii_ipca_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+typedef union ii_iprte0a_u {
+	shubreg_t	ii_iprte0a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} ii_iprte0a_fld_s;
+} ii_iprte0a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1a_u {
+	shubreg_t	ii_iprte1a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} ii_iprte1a_fld_s;
+} ii_iprte1a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2a_u {
+	shubreg_t	ii_iprte2a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} ii_iprte2a_fld_s;
+} ii_iprte2a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3a_u {
+	shubreg_t	ii_iprte3a_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte3a_fld_s;
+} ii_iprte3a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4a_u {
+	shubreg_t	ii_iprte4a_regval;
+	struct	{
+		shubreg_t	i_rsvd_1		  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte4a_fld_s;
+} ii_iprte4a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5a_u {
+	shubreg_t	ii_iprte5a_regval;
+	struct	{
+		shubreg_t	i_rsvd_1		  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte5a_fld_s;
+} ii_iprte5a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6a_u {
+	shubreg_t	ii_iprte6a_regval;
+	struct	{
+		shubreg_t	i_rsvd_1		  :	54;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t	i_vld			  :	 1;
+	} ii_iprte6a_fld_s;
+} ii_iprte6a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7a_u {
+        shubreg_t       ii_iprte7a_regval;
+        struct  {
+                shubreg_t       i_rsvd_1                  :     54;
+                shubreg_t       i_widget                  :      4;
+                shubreg_t       i_to_cnt                  :      5;
+                shubreg_t       i_vld                     :      1;
+        } ii_iprtea7_fld_s;
+} ii_iprte7a_u_t;
+
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+
+typedef union ii_iprte0b_u {
+	shubreg_t	ii_iprte0b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte0b_fld_s;
+} ii_iprte0b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte1b_u {
+	shubreg_t	ii_iprte1b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte1b_fld_s;
+} ii_iprte1b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte2b_u {
+	shubreg_t	ii_iprte2b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte2b_fld_s;
+} ii_iprte2b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte3b_u {
+	shubreg_t	ii_iprte3b_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte3b_fld_s;
+} ii_iprte3b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte4b_u {
+	shubreg_t	ii_iprte4b_regval;
+	struct	{
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte4b_fld_s;
+} ii_iprte4b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte5b_u {
+	shubreg_t	ii_iprte5b_regval;
+	struct	{
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+	} ii_iprte5b_fld_s;
+} ii_iprte5b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte6b_u {
+	shubreg_t	ii_iprte6b_regval;
+	struct	{
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+
+	} ii_iprte6b_fld_s;
+} ii_iprte6b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  There are 8 instances of this register. This register contains      *
+ * the information that the II has to remember once it has launched a   *
+ * PIO Read operation. The contents are used to form the correct        *
+ * Router Network packet and direct the Crosstalk reply to the          *
+ * appropriate processor.                                               *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iprte7b_u {
+        shubreg_t       ii_iprte7b_regval;
+        struct  {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_address		  :	47;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t       i_source                  :     11;
+        } ii_iprte7b_fld_s;
+} ii_iprte7b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  SHub II contains a feature which did not exist in      *
+ * the Hub which automatically cleans up after a Read Response          *
+ * timeout, including deallocation of the IPRTE and recovery of IBuf    *
+ * space. The inclusion of this register in SHub is for backward        *
+ * compatibility                                                        *
+ * A write to this register causes an entry from the table of           *
+ * outstanding PIO Read Requests to be freed and returned to the        *
+ * stack of free entries. This register is used in handling the         *
+ * timeout errors that result in a PIO Reply never returning from       *
+ * Crosstalk.                                                           *
+ * Note that this register does not affect the contents of the IPRTE    *
+ * registers. The Valid bits in those registers have to be              *
+ * specifically turned off by software.                                 *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipdr_u {
+	shubreg_t	ii_ipdr_regval;
+	struct  {
+		shubreg_t	i_te                      :	 3;
+		shubreg_t	i_rsvd_1		  :	 1;
+		shubreg_t	i_pnd			  :	 1;
+		shubreg_t	i_init_rpcnt		  :	 1;
+		shubreg_t	i_rsvd			  :	58;
+	} ii_ipdr_fld_s;
+} ii_ipdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  A write to this register causes a CRB entry to be returned to the   *
+ * queue of free CRBs. The entry should have previously been cleared    *
+ * (mark bit) via backdoor access to the pertinent CRB entry. This      *
+ * register is used in the last step of handling the errors that are    *
+ * captured and marked in CRB entries.  Briefly: 1) first error for     *
+ * DMA write from a particular device, and first error for a            *
+ * particular BTE stream, lead to a marked CRB entry, and processor     *
+ * interrupt, 2) software reads the error information captured in the   *
+ * CRB entry, and presumably takes some corrective action, 3)           *
+ * software clears the mark bit, and finally 4) software writes to      *
+ * the ICDR register to return the CRB entry to the list of free CRB    *
+ * entries.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icdr_u {
+	shubreg_t	ii_icdr_regval;
+	struct  {
+		shubreg_t	i_crb_num                 :	 4;
+		shubreg_t	i_pnd			  :	 1;
+		shubreg_t       i_rsvd                    :     59;
+	} ii_icdr_fld_s;
+} ii_icdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register provides debug access to two FIFOs inside of II.      *
+ * Both IOQ_MAX* fields of this register contain the instantaneous      *
+ * depth (in units of the number of available entries) of the           *
+ * associated IOQ FIFO.  A read of this register will return the        *
+ * number of free entries on each FIFO at the time of the read.  So     *
+ * when a FIFO is idle, the associated field contains the maximum       *
+ * depth of the FIFO.  This register is writable for debug reasons      *
+ * and is intended to be written with the maximum desired FIFO depth    *
+ * while the FIFO is idle. Software must assure that II is idle when    *
+ * this register is written. If there are any active entries in any     *
+ * of these FIFOs when this register is written, the results are        *
+ * undefined.                                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ifdr_u {
+	shubreg_t	ii_ifdr_regval;
+	struct  {
+		shubreg_t	i_ioq_max_rq              :	 7;
+		shubreg_t	i_set_ioq_rq		  :	 1;
+		shubreg_t	i_ioq_max_rp		  :	 7;
+		shubreg_t	i_set_ioq_rp		  :	 1;
+		shubreg_t	i_rsvd			  :	48;
+	} ii_ifdr_fld_s;
+} ii_ifdr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the II to become sluggish in removing          *
+ * messages from its inbound queue (IIQ). This will cause messages to   *
+ * back up in either virtual channel. Disabling the "molasses" mode     *
+ * subsequently allows the II to be tested under stress. In the         *
+ * sluggish ("Molasses") mode, the localized effects of congestion      *
+ * can be observed.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iiap_u {
+        shubreg_t       ii_iiap_regval;
+        struct  {
+                shubreg_t       i_rq_mls                  :      6;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_rp_mls		  :	 6;
+		shubreg_t       i_rsvd                    :     50;
+        } ii_iiap_fld_s;
+} ii_iiap_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows several parameters of CRB operation to be      *
+ * set. Note that writing to this register can have catastrophic side   *
+ * effects, if the CRB is not quiescent, i.e. if the CRB is             *
+ * processing protocol messages when the write occurs.                  *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icmr_u {
+	shubreg_t	ii_icmr_regval;
+	struct  {
+		shubreg_t	i_sp_msg                  :	 1;
+		shubreg_t	i_rd_hdr		  :	 1;
+		shubreg_t	i_rsvd_4		  :	 2;
+		shubreg_t	i_c_cnt			  :	 4;
+		shubreg_t	i_rsvd_3		  :	 4;
+		shubreg_t	i_clr_rqpd		  :	 1;
+		shubreg_t	i_clr_rppd		  :	 1;
+		shubreg_t	i_rsvd_2		  :	 2;
+		shubreg_t	i_fc_cnt		  :	 4;
+		shubreg_t	i_crb_vld		  :	15;
+		shubreg_t	i_crb_mark		  :	15;
+		shubreg_t	i_rsvd_1		  :	 2;
+		shubreg_t	i_precise		  :	 1;
+		shubreg_t	i_rsvd			  :	11;
+	} ii_icmr_fld_s;
+} ii_icmr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows control of the table portion of the CRB        *
+ * logic via software. Control operations from this register have       *
+ * priority over all incoming Crosstalk or BTE requests.                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_iccr_u {
+	shubreg_t	ii_iccr_regval;
+	struct  {
+		shubreg_t	i_crb_num                 :	 4;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_cmd			  :	 8;
+		shubreg_t	i_pending		  :	 1;
+		shubreg_t	i_rsvd			  :	47;
+	} ii_iccr_fld_s;
+} ii_iccr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the maximum timeout value to be programmed.    *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icto_u {
+	shubreg_t	ii_icto_regval;
+	struct  {
+		shubreg_t	i_timeout                 :	 8;
+		shubreg_t	i_rsvd			  :	56;
+	} ii_icto_fld_s;
+} ii_icto_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register allows the timeout prescalar to be programmed. An     *
+ * internal counter is associated with this register. When the          *
+ * internal counter reaches the value of the PRESCALE field, the        *
+ * timer registers in all valid CRBs are incremented (CRBx_D[TIMEOUT]   *
+ * field). The internal counter resets to zero, and then continues      *
+ * counting.                                                            *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ictp_u {
+	shubreg_t	ii_ictp_regval;
+	struct  {
+		shubreg_t	i_prescale                :	24;
+		shubreg_t	i_rsvd			  :	40;
+	} ii_ictp_fld_s;
+} ii_ictp_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ * The CRB Entry registers can be conceptualized as rows and columns    *
+ * (illustrated in the table above). Each row contains the 4            *
+ * registers required for a single CRB Entry. The first doubleword      *
+ * (column) for each entry is labeled A, and the second doubleword      *
+ * (higher address) is labeled B, the third doubleword is labeled C,    *
+ * the fourth doubleword is labeled D and the fifth doubleword is       *
+ * labeled E. All CRB entries have their addresses on a quarter         *
+ * cacheline aligned boundary.                   *
+ * Upon reset, only the following fields are initialized: valid         *
+ * (VLD), priority count, timeout, timeout valid, and context valid.    *
+ * All other bits should be cleared by software before use (after       *
+ * recovering any potential error state from before the reset).         *
+ * The following four tables summarize the format for the four          *
+ * registers that are used for each ICRB# Entry.                        *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_a_u {
+	shubreg_t	ii_icrb0_a_regval;
+	struct  {
+		shubreg_t	ia_iow                    :	 1;
+		shubreg_t	ia_vld			  :	 1;
+		shubreg_t	ia_addr			  :	47;
+		shubreg_t	ia_tnum			  :	 5;
+		shubreg_t	ia_sidn			  :	 4;
+		shubreg_t       ia_rsvd                   :      6;
+	} ii_icrb0_a_fld_s;
+} ii_icrb0_a_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_b_u {
+	shubreg_t	ii_icrb0_b_regval;
+	struct	{
+		shubreg_t	ib_xt_err		  :	 1;
+		shubreg_t	ib_mark			  :	 1;
+		shubreg_t	ib_ln_uce		  :	 1;
+		shubreg_t	ib_errcode		  :	 3;
+		shubreg_t	ib_error		  :	 1;
+		shubreg_t	ib_stall__bte_1		  :	 1;
+		shubreg_t	ib_stall__bte_0		  :	 1;
+		shubreg_t	ib_stall__intr		  :	 1;
+		shubreg_t	ib_stall_ib		  :	 1;
+		shubreg_t	ib_intvn		  :	 1;
+		shubreg_t	ib_wb			  :	 1;
+		shubreg_t	ib_hold			  :	 1;
+		shubreg_t	ib_ack			  :	 1;
+		shubreg_t	ib_resp			  :	 1;
+		shubreg_t	ib_ack_cnt		  :	11;
+		shubreg_t	ib_rsvd			  :	 7;
+		shubreg_t	ib_exc			  :	 5;
+		shubreg_t	ib_init			  :	 3;
+		shubreg_t	ib_imsg			  :	 8;
+		shubreg_t	ib_imsgtype		  :	 2;
+		shubreg_t	ib_use_old		  :	 1;
+		shubreg_t	ib_rsvd_1		  :	11;
+	} ii_icrb0_b_fld_s;
+} ii_icrb0_b_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_c_u {
+	shubreg_t	ii_icrb0_c_regval;
+	struct	{
+		shubreg_t	ic_source		  :	15;
+		shubreg_t	ic_size			  :	 2;
+		shubreg_t	ic_ct			  :	 1;
+		shubreg_t	ic_bte_num		  :	 1;
+		shubreg_t	ic_gbr			  :	 1;
+		shubreg_t	ic_resprqd		  :	 1;
+		shubreg_t	ic_bo			  :	 1;
+		shubreg_t	ic_suppl		  :	15;
+		shubreg_t	ic_rsvd			  :	27;
+	} ii_icrb0_c_fld_s;
+} ii_icrb0_c_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_d_u {
+	shubreg_t	ii_icrb0_d_regval;
+	struct  {
+		shubreg_t	id_pa_be                  :	43;
+		shubreg_t	id_bte_op		  :	 1;
+		shubreg_t	id_pr_psc		  :	 4;
+		shubreg_t	id_pr_cnt		  :	 4;
+		shubreg_t	id_sleep		  :	 1;
+		shubreg_t	id_rsvd			  :	11;
+	} ii_icrb0_d_fld_s;
+} ii_icrb0_d_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  There are 15 CRB Entries (ICRB0 to ICRBE) that are     *
+ * used for Crosstalk operations (both cacheline and partial            *
+ * operations) or BTE/IO. Because the CRB entries are very wide, five   *
+ * registers (_A to _E) are required to read and write each entry.      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icrb0_e_u {
+	shubreg_t	ii_icrb0_e_regval;
+	struct  {
+		shubreg_t	ie_timeout                :	 8;
+		shubreg_t	ie_context		  :	15;
+		shubreg_t	ie_rsvd			  :	 1;
+		shubreg_t	ie_tvld			  :	 1;
+		shubreg_t	ie_cvld			  :	 1;
+		shubreg_t	ie_rsvd_0		  :	38;
+	} ii_icrb0_e_fld_s;
+} ii_icrb0_e_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the lower 64 bits of the header of the       *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsml_u {
+	shubreg_t	ii_icsml_regval;
+	struct  {
+		shubreg_t	i_tt_addr                 :	47;
+		shubreg_t	i_newsuppl_ex		  :	14;
+		shubreg_t	i_reserved		  :	 2;
+		shubreg_t       i_overflow                :      1;
+	} ii_icsml_fld_s;
+} ii_icsml_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the middle 64 bits of the header of the      *
+ * spurious message captured by II. Valid when the SP_MSG bit in ICMR   *
+ * register is set.                                                     *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmm_u {
+	shubreg_t	ii_icsmm_regval;
+	struct  {
+		shubreg_t	i_tt_ack_cnt              :	11;
+		shubreg_t	i_reserved		  :	53;
+	} ii_icsmm_fld_s;
+} ii_icsmm_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the microscopic state, all the inputs to     *
+ * the protocol table, captured with the spurious message. Valid when   *
+ * the SP_MSG bit in the ICMR register is set.                          *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_icsmh_u {
+	shubreg_t	ii_icsmh_regval;
+	struct  {
+		shubreg_t	i_tt_vld                  :	 1;
+		shubreg_t	i_xerr			  :	 1;
+		shubreg_t	i_ft_cwact_o		  :	 1;
+		shubreg_t	i_ft_wact_o		  :	 1;
+		shubreg_t       i_ft_active_o             :      1;
+		shubreg_t	i_sync			  :	 1;
+		shubreg_t	i_mnusg			  :	 1;
+		shubreg_t	i_mnusz			  :	 1;
+		shubreg_t	i_plusz			  :	 1;
+		shubreg_t	i_plusg			  :	 1;
+		shubreg_t	i_tt_exc		  :	 5;
+		shubreg_t	i_tt_wb			  :	 1;
+		shubreg_t	i_tt_hold		  :	 1;
+		shubreg_t	i_tt_ack		  :	 1;
+		shubreg_t	i_tt_resp		  :	 1;
+		shubreg_t	i_tt_intvn		  :	 1;
+		shubreg_t	i_g_stall_bte1		  :	 1;
+		shubreg_t	i_g_stall_bte0		  :	 1;
+		shubreg_t	i_g_stall_il		  :	 1;
+		shubreg_t	i_g_stall_ib		  :	 1;
+		shubreg_t	i_tt_imsg		  :	 8;
+		shubreg_t	i_tt_imsgtype		  :	 2;
+		shubreg_t	i_tt_use_old		  :	 1;
+		shubreg_t	i_tt_respreqd		  :	 1;
+		shubreg_t	i_tt_bte_num		  :	 1;
+		shubreg_t	i_cbn			  :	 1;
+		shubreg_t	i_match			  :	 1;
+		shubreg_t	i_rpcnt_lt_34		  :	 1;
+		shubreg_t	i_rpcnt_ge_34		  :	 1;
+		shubreg_t	i_rpcnt_lt_18		  :	 1;
+		shubreg_t	i_rpcnt_ge_18		  :	 1;
+		shubreg_t       i_rpcnt_lt_2              :      1;
+		shubreg_t	i_rpcnt_ge_2		  :	 1;
+		shubreg_t	i_rqcnt_lt_18		  :	 1;
+		shubreg_t	i_rqcnt_ge_18		  :	 1;
+		shubreg_t	i_rqcnt_lt_2		  :	 1;
+		shubreg_t	i_rqcnt_ge_2		  :	 1;
+		shubreg_t	i_tt_device		  :	 7;
+		shubreg_t	i_tt_init		  :	 3;
+		shubreg_t	i_reserved		  :	 5;
+	} ii_icsmh_fld_s;
+} ii_icsmh_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  The Shub DEBUG unit provides a 3-bit selection signal to the        *
+ * II core and a 3-bit selection signal to the fsbclk domain in the II  *
+ * wrapper.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_idbss_u {
+	shubreg_t	ii_idbss_regval;
+	struct  {
+		shubreg_t	i_iioclk_core_submenu     :	 3;
+		shubreg_t	i_rsvd			  :	 5;
+		shubreg_t	i_fsbclk_wrapper_submenu  :	 3;
+		shubreg_t	i_rsvd_1		  :	 5;
+		shubreg_t	i_iioclk_menu		  :	 5;
+		shubreg_t	i_rsvd_2		  :	43;
+	} ii_idbss_fld_s;
+} ii_idbss_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls0_u {
+	shubreg_t	ii_ibls0_regval;
+	struct	{
+		shubreg_t	i_length		  :	16;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_busy			  :	 1;
+		shubreg_t       i_rsvd                    :     43;
+	} ii_ibls0_fld_s;
+} ii_ibls0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa0_u {
+	shubreg_t	ii_ibsa0_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	42;
+		shubreg_t       i_rsvd                    :     15;
+	} ii_ibsa0_fld_s;
+} ii_ibsa0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda0_u {
+	shubreg_t	ii_ibda0_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	42;
+		shubreg_t	i_rsvd			  :	15;
+	} ii_ibda0_fld_s;
+} ii_ibda0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct0_u {
+	shubreg_t	ii_ibct0_regval;
+	struct  {
+		shubreg_t	i_zerofill                :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_notify		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t       i_poison                  :      1;
+		shubreg_t       i_rsvd                    :     55;
+	} ii_ibct0_fld_s;
+} ii_ibct0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna0_u {
+	shubreg_t	ii_ibna0_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	42;
+		shubreg_t	i_rsvd			  :	15;
+	} ii_ibna0_fld_s;
+} ii_ibna0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia0_u {
+	shubreg_t	ii_ibia0_regval;
+	struct  {
+		shubreg_t	i_rsvd_2                   :	 1;
+		shubreg_t	i_node_id		  :	11;
+		shubreg_t	i_rsvd_1		  :	 4;
+		shubreg_t	i_level			  :	 7;
+		shubreg_t       i_rsvd                    :     41;
+	} ii_ibia0_fld_s;
+} ii_ibia0_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ * Description:  This register is used to set up the length for a       *
+ * transfer and then to monitor the progress of that transfer. This     *
+ * register needs to be initialized before a transfer is started. A     *
+ * legitimate write to this register will set the Busy bit, clear the   *
+ * Error bit, and initialize the length to the value desired.           *
+ * While the transfer is in progress, hardware will decrement the       *
+ * length field with each successful block that is copied. Once the     *
+ * transfer completes, hardware will clear the Busy bit. The length     *
+ * field will also contain the number of cache lines left to be         *
+ * transferred.                                                         *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibls1_u {
+	shubreg_t	ii_ibls1_regval;
+	struct  {
+		shubreg_t	i_length                  :	16;
+		shubreg_t	i_error			  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_busy			  :	 1;
+		shubreg_t       i_rsvd                    :     43;
+	} ii_ibls1_fld_s;
+} ii_ibls1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibsa1_u {
+	shubreg_t	ii_ibsa1_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	33;
+		shubreg_t	i_rsvd			  :	24;
+	} ii_ibsa1_fld_s;
+} ii_ibsa1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register should be loaded before a transfer is started. The    *
+ * address to be loaded in bits 39:0 is the 40-bit TRex+ physical       *
+ * address as described in Section 1.3, Figure2 and Figure3. Since      *
+ * the bottom 7 bits of the address are always taken to be zero, BTE    *
+ * transfers are always cacheline-aligned.                              *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibda1_u {
+	shubreg_t	ii_ibda1_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	33;
+		shubreg_t	i_rsvd			  :	24;
+	} ii_ibda1_fld_s;
+} ii_ibda1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  Writing to this register sets up the attributes of the transfer     *
+ * and initiates the transfer operation. Reading this register has      *
+ * the side effect of terminating any transfer in progress. Note:       *
+ * stopping a transfer midstream could have an adverse impact on the    *
+ * other BTE. If a BTE stream has to be stopped (due to error           *
+ * handling for example), both BTE streams should be stopped and        *
+ * their transfers discarded.                                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibct1_u {
+	shubreg_t	ii_ibct1_regval;
+	struct  {
+		shubreg_t	i_zerofill                :	 1;
+		shubreg_t	i_rsvd_2		  :	 3;
+		shubreg_t	i_notify		  :	 1;
+		shubreg_t	i_rsvd_1		  :	 3;
+		shubreg_t	i_poison		  :	 1;
+		shubreg_t	i_rsvd			  :	55;
+	} ii_ibct1_fld_s;
+} ii_ibct1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the address to which the WINV is sent.       *
+ * This address has to be cache line aligned.                           *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibna1_u {
+	shubreg_t	ii_ibna1_regval;
+	struct  {
+		shubreg_t	i_rsvd_1                  :	 7;
+		shubreg_t	i_addr			  :	33;
+		shubreg_t       i_rsvd                    :     24;
+	} ii_ibna1_fld_s;
+} ii_ibna1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register contains the programmable level as well as the node   *
+ * ID and PI unit of the processor to which the interrupt will be       *
+ * sent.                                                                *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ibia1_u {
+	shubreg_t	ii_ibia1_regval;
+	struct  {
+		shubreg_t	i_pi_id                   :	 1;
+		shubreg_t	i_node_id		  :	 8;
+		shubreg_t	i_rsvd_1		  :	 7;
+		shubreg_t	i_level			  :	 7;
+		shubreg_t	i_rsvd			  :	41;
+	} ii_ibia1_fld_s;
+} ii_ibia1_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *  This register defines the resources that feed information into      *
+ * the two performance counters located in the IO Performance           *
+ * Profiling Register. There are 17 different quantities that can be    *
+ * measured. Given these 17 different options, the two performance      *
+ * counters have 15 of them in common; menu selections 0 through 0xE    *
+ * are identical for each performance counter. As for the other two     *
+ * options, one is available from one performance counter and the       *
+ * other is available from the other performance counter. Hence, the    *
+ * II supports all 17*16=272 possible combinations of quantities to     *
+ * measure.                                                             *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ipcr_u {
+	shubreg_t	ii_ipcr_regval;
+	struct  {
+		shubreg_t	i_ippr0_c                 :	 4;
+		shubreg_t	i_ippr1_c		  :	 4;
+		shubreg_t	i_icct			  :	 8;
+		shubreg_t       i_rsvd                    :     48;
+	} ii_ipcr_fld_s;
+} ii_ipcr_u_t;
+
+
+/************************************************************************
+ *                                                                      *
+ *                                                                      *
+ *                                                                      *
+ ************************************************************************/
+
+typedef union ii_ippr_u {
+	shubreg_t	ii_ippr_regval;
+	struct  {
+		shubreg_t	i_ippr0                   :	32;
+		shubreg_t	i_ippr1			  :	32;
+	} ii_ippr_fld_s;
+} ii_ippr_u_t;
+
+
+#endif /* __ASSEMBLY__ */
+
+/**************************************************************************
+ *                                                                        *
+ * The following defines which were not formed into structures are        *
+ * probably indentical to another register, and the name of the           *
+ * register is provided against each of these registers. This             *
+ * information needs to be checked carefully                              *
+ *                                                                        *
+ *           IIO_ICRB1_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB1_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB1_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB1_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB1_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB2_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB2_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB2_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB2_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB2_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB3_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB3_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB3_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB3_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB3_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB4_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB4_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB4_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB4_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB4_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB5_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB5_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB5_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB5_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB5_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB6_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB6_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB6_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB6_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB6_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB7_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB7_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB7_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB7_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB7_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB8_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB8_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB8_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB8_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB8_E                IIO_ICRB0_E                       *
+ *           IIO_ICRB9_A                IIO_ICRB0_A                       *
+ *           IIO_ICRB9_B                IIO_ICRB0_B                       *
+ *           IIO_ICRB9_C                IIO_ICRB0_C                       *
+ *           IIO_ICRB9_D                IIO_ICRB0_D                       *
+ *           IIO_ICRB9_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBA_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBA_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBA_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBA_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBA_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBB_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBB_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBB_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBB_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBB_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBC_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBC_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBC_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBC_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBC_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBD_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBD_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBD_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBD_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBD_E                IIO_ICRB0_E                       *
+ *           IIO_ICRBE_A                IIO_ICRB0_A                       *
+ *           IIO_ICRBE_B                IIO_ICRB0_B                       *
+ *           IIO_ICRBE_C                IIO_ICRB0_C                       *
+ *           IIO_ICRBE_D                IIO_ICRB0_D                       *
+ *           IIO_ICRBE_E                IIO_ICRB0_E                       *
+ *                                                                        *
+ **************************************************************************/
+
+
+/*
+ * Slightly friendlier names for some common registers.
+ */
+#define IIO_WIDGET              IIO_WID      /* Widget identification */
+#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
+#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
+#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
+#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
+#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
+#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
+#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
+#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
+#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
+#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
+#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
+#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
+#define IIO_IGFX_0 		IIO_IGFX0
+#define IIO_IGFX_1 		IIO_IGFX1
+#define IIO_IBCT_0		IIO_IBCT0
+#define IIO_IBCT_1		IIO_IBCT1
+#define IIO_IBLS_0		IIO_IBLS0
+#define IIO_IBLS_1		IIO_IBLS1
+#define IIO_IBSA_0		IIO_IBSA0
+#define IIO_IBSA_1		IIO_IBSA1
+#define IIO_IBDA_0		IIO_IBDA0
+#define IIO_IBDA_1		IIO_IBDA1
+#define IIO_IBNA_0		IIO_IBNA0
+#define IIO_IBNA_1		IIO_IBNA1
+#define IIO_IBIA_0		IIO_IBIA0
+#define IIO_IBIA_1		IIO_IBIA1
+#define IIO_IOPRB_0		IIO_IPRB0
+
+#define IIO_PRTE_A(_x)		(IIO_IPRTE0_A + (8 * (_x)))
+#define IIO_PRTE_B(_x)		(IIO_IPRTE0_B + (8 * (_x)))
+#define IIO_NUM_PRTES		8	/* Total number of PRB table entries */
+#define IIO_WIDPRTE_A(x)	IIO_PRTE_A(((x) - 8)) /* widget ID to its PRTE num */
+#define IIO_WIDPRTE_B(x)	IIO_PRTE_B(((x) - 8)) /* widget ID to its PRTE num */
+
+#define IIO_NUM_IPRBS 		(9) 
+
+#define IIO_LLP_CSR_IS_UP               0x00002000
+#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
+#define IIO_LLP_CSR_LLP_STAT_SHFT       12
+
+#define IIO_LLP_CB_MAX  0xffff	/* in ILLR CB_CNT, Max Check Bit errors */
+#define IIO_LLP_SN_MAX  0xffff	/* in ILLR SN_CNT, Max Sequence Number errors */
+
+/* key to IIO_PROTECT_OVRRD */
+#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
+
+/* BTE register names */
+#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
+#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
+#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
+#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
+#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
+#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
+#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
+#define IIO_BTE_OFF_1   	(IIO_IBLS_1 - IIO_IBLS_0) /* Offset from base to BTE 1 */
+
+/* BTE register offsets from base */
+#define BTEOFF_STAT             0
+#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
+#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
+#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
+#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
+#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
+
+
+/* names used in shub diags */
+#define IIO_BASE_BTE0   IIO_IBLS_0		
+#define IIO_BASE_BTE1   IIO_IBLS_1		
+
+/*
+ * Macro which takes the widget number, and returns the
+ * IO PRB address of that widget.
+ * value _x is expected to be a widget number in the range
+ * 0, 8 - 0xF
+ */
+#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
+                        (_x) : \
+                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
+
+
+/* GFX Flow Control Node/Widget Register */
+#define IIO_IGFX_W_NUM_BITS	4	/* size of widget num field */
+#define IIO_IGFX_W_NUM_MASK	((1<<IIO_IGFX_W_NUM_BITS)-1)
+#define IIO_IGFX_W_NUM_SHIFT	0
+#define IIO_IGFX_PI_NUM_BITS	1	/* size of PI num field */
+#define IIO_IGFX_PI_NUM_MASK	((1<<IIO_IGFX_PI_NUM_BITS)-1)
+#define IIO_IGFX_PI_NUM_SHIFT	4
+#define IIO_IGFX_N_NUM_BITS	8	/* size of node num field */
+#define IIO_IGFX_N_NUM_MASK	((1<<IIO_IGFX_N_NUM_BITS)-1)
+#define IIO_IGFX_N_NUM_SHIFT	5
+#define IIO_IGFX_P_NUM_BITS	1	/* size of processor num field */
+#define IIO_IGFX_P_NUM_MASK	((1<<IIO_IGFX_P_NUM_BITS)-1)
+#define IIO_IGFX_P_NUM_SHIFT	16
+#define IIO_IGFX_INIT(widget, pi, node, cpu)				(\
+	(((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |	 \
+	(((pi)     & IIO_IGFX_PI_NUM_MASK)<< IIO_IGFX_PI_NUM_SHIFT)|	 \
+	(((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |	 \
+	(((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT))
+
+
+/* Scratch registers (all bits available) */
+#define IIO_SCRATCH_REG0        IIO_ISCR0
+#define IIO_SCRATCH_REG1        IIO_ISCR1
+#define IIO_SCRATCH_MASK        0xffffffffffffffff
+
+#define IIO_SCRATCH_BIT0_0      0x0000000000000001
+#define IIO_SCRATCH_BIT0_1      0x0000000000000002
+#define IIO_SCRATCH_BIT0_2      0x0000000000000004
+#define IIO_SCRATCH_BIT0_3      0x0000000000000008
+#define IIO_SCRATCH_BIT0_4      0x0000000000000010
+#define IIO_SCRATCH_BIT0_5      0x0000000000000020
+#define IIO_SCRATCH_BIT0_6      0x0000000000000040
+#define IIO_SCRATCH_BIT0_7      0x0000000000000080
+#define IIO_SCRATCH_BIT0_8      0x0000000000000100
+#define IIO_SCRATCH_BIT0_9      0x0000000000000200
+#define IIO_SCRATCH_BIT0_A      0x0000000000000400
+
+#define IIO_SCRATCH_BIT1_0      0x0000000000000001
+#define IIO_SCRATCH_BIT1_1      0x0000000000000002
+/* IO Translation Table Entries */
+#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
+                                        /* Hw manuals number them 1..7! */
+/*
+ * IIO_IMEM Register fields.
+ */
+#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
+#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
+#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
+
+/*
+ * As a permanent workaround for a bug in the PI side of the shub, we've
+ * redefined big window 7 as small window 0.
+ XXX does this still apply for SN1??
+ */
+#define HUB_NUM_BIG_WINDOW      (IIO_NUM_ITTES - 1)
+
+/*
+ * Use the top big window as a surrogate for the first small window
+ */
+#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
+
+#define ILCSR_WARM_RESET        0x100
+
+/*
+ * CRB manipulation macros
+ *      The CRB macros are slightly complicated, since there are up to
+ *      four registers associated with each CRB entry.
+ */
+#define IIO_NUM_CRBS            15      /* Number of CRBs */
+#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
+#define IIO_ICRB_OFFSET         8
+#define IIO_ICRB_0              IIO_ICRB0_A
+#define IIO_ICRB_ADDR_SHFT	2	/* Shift to get proper address */
+/* XXX - This is now tuneable:
+        #define IIO_FIRST_PC_ENTRY 12
+ */
+
+#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (6 * IIO_ICRB_OFFSET * (_x)))
+#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
+#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
+#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
+#define IIO_ICRB_E(_x)  (IIO_ICRB_A(_x) + 4*IIO_ICRB_OFFSET)
+
+#define TNUM_TO_WIDGET_DEV(_tnum)	(_tnum & 0x7)
+
+/*
+ * values for "ecode" field
+ */
+#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
+#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
+#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
+                                         * e.g. WINV to a Read only line. */
+#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
+#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
+#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
+#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
+#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
+
+/*
+ * Values for field imsgtype
+ */
+#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
+#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
+#define IIO_ICRB_IMSGT_SN1NET   2       /* Incoming message from SN1 net */
+#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
+
+/*
+ * values for field initiator.
+ */
+#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
+#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
+#define IIO_ICRB_INIT_SN1NET    0x2     /* Message originated in SN1net */
+#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
+#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
+
+/*
+ * Number of credits Hub widget has while sending req/response to
+ * xbow.
+ * Value of 3 is required by Xbow 1.1
+ * We may be able to increase this to 4 with Xbow 1.2.
+ */
+#define       HUBII_XBOW_CREDIT       3
+#define       HUBII_XBOW_REV2_CREDIT  4
+
+/*
+ * Number of credits that xtalk devices should use when communicating
+ * with a SHub (depth of SHub's queue).
+ */
+#define HUB_CREDIT 4
+
+/*
+ * Some IIO_PRB fields
+ */
+#define IIO_PRB_MULTI_ERR	(1LL << 63)
+#define IIO_PRB_SPUR_RD		(1LL << 51)
+#define IIO_PRB_SPUR_WR		(1LL << 50)
+#define IIO_PRB_RD_TO		(1LL << 49)
+#define IIO_PRB_ERROR		(1LL << 48)
+
+/*************************************************************************
+
+ Some of the IIO field masks and shifts are defined here.
+ This is in order to maintain compatibility in SN0 and SN1 code
+ 
+**************************************************************************/
+
+/*
+ * ICMR register fields
+ * (Note: the IIO_ICMR_P_CNT and IIO_ICMR_PC_VLD from Hub are not
+ * present in SHub)
+ */
+
+#define IIO_ICMR_CRB_VLD_SHFT   20
+#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
+
+#define IIO_ICMR_FC_CNT_SHFT    16
+#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
+
+#define IIO_ICMR_C_CNT_SHFT     4
+#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
+
+#define IIO_ICMR_PRECISE        (1UL << 52)
+#define IIO_ICMR_CLR_RPPD       (1UL << 13)
+#define IIO_ICMR_CLR_RQPD       (1UL << 12)
+
+/*
+ * IIO PIO Deallocation register field masks : (IIO_IPDR)
+ XXX present but not needed in bedrock?  See the manual.
+ */
+#define IIO_IPDR_PND    (1 << 4)
+
+/*
+ * IIO CRB deallocation register field masks: (IIO_ICDR)
+ */
+#define IIO_ICDR_PND    (1 << 4)
+
+/* 
+ * IO BTE Length/Status (IIO_IBLS) register bit field definitions
+ */
+#define IBLS_BUSY		(0x1 << 20)
+#define IBLS_ERROR_SHFT		16
+#define IBLS_ERROR		(0x1 << IBLS_ERROR_SHFT)
+#define IBLS_LENGTH_MASK	0xffff
+
+/*
+ * IO BTE Control/Terminate register (IBCT) register bit field definitions
+ */
+#define IBCT_POISON		(0x1 << 8)
+#define IBCT_NOTIFY		(0x1 << 4)
+#define IBCT_ZFIL_MODE		(0x1 << 0)
+
+/*
+ * IIO Incoming Error Packet Header (IIO_IIEPH1/IIO_IIEPH2)
+ */
+#define IIEPH1_VALID		(1 << 44)
+#define IIEPH1_OVERRUN		(1 << 40)
+#define IIEPH1_ERR_TYPE_SHFT	32
+#define IIEPH1_ERR_TYPE_MASK	0xf
+#define IIEPH1_SOURCE_SHFT	20
+#define IIEPH1_SOURCE_MASK	11
+#define IIEPH1_SUPPL_SHFT	8
+#define IIEPH1_SUPPL_MASK	11
+#define IIEPH1_CMD_SHFT		0
+#define IIEPH1_CMD_MASK		7
+
+#define IIEPH2_TAIL		(1 << 40)
+#define IIEPH2_ADDRESS_SHFT	0
+#define IIEPH2_ADDRESS_MASK	38
+
+#define IIEPH1_ERR_SHORT_REQ	2
+#define IIEPH1_ERR_SHORT_REPLY	3
+#define IIEPH1_ERR_LONG_REQ	4
+#define IIEPH1_ERR_LONG_REPLY	5
+
+/*
+ * IO Error Clear register bit field definitions
+ */
+#define IECLR_PI1_FWD_INT	(1 << 31)  /* clear PI1_FORWARD_INT in iidsr */
+#define IECLR_PI0_FWD_INT	(1 << 30)  /* clear PI0_FORWARD_INT in iidsr */
+#define IECLR_SPUR_RD_HDR	(1 << 29)  /* clear valid bit in ixss reg */
+#define IECLR_BTE1		(1 << 18)  /* clear bte error 1 */
+#define IECLR_BTE0		(1 << 17)  /* clear bte error 0 */
+#define IECLR_CRAZY		(1 << 16)  /* clear crazy bit in wstat reg */
+#define IECLR_PRB_F		(1 << 15)  /* clear err bit in PRB_F reg */
+#define IECLR_PRB_E		(1 << 14)  /* clear err bit in PRB_E reg */
+#define IECLR_PRB_D		(1 << 13)  /* clear err bit in PRB_D reg */
+#define IECLR_PRB_C		(1 << 12)  /* clear err bit in PRB_C reg */
+#define IECLR_PRB_B		(1 << 11)  /* clear err bit in PRB_B reg */
+#define IECLR_PRB_A		(1 << 10)  /* clear err bit in PRB_A reg */
+#define IECLR_PRB_9		(1 << 9)   /* clear err bit in PRB_9 reg */
+#define IECLR_PRB_8		(1 << 8)   /* clear err bit in PRB_8 reg */
+#define IECLR_PRB_0		(1 << 0)   /* clear err bit in PRB_0 reg */
+
+/*
+ * IIO CRB control register Fields: IIO_ICCR 
+ */
+#define	IIO_ICCR_PENDING	(0x10000)
+#define	IIO_ICCR_CMD_MASK	(0xFF)
+#define	IIO_ICCR_CMD_SHFT	(7)
+#define	IIO_ICCR_CMD_NOP	(0x0)	/* No Op */
+#define	IIO_ICCR_CMD_WAKE	(0x100) /* Reactivate CRB entry and process */
+#define	IIO_ICCR_CMD_TIMEOUT	(0x200)	/* Make CRB timeout & mark invalid */
+#define	IIO_ICCR_CMD_EJECT	(0x400)	/* Contents of entry written to memory 
+					 * via a WB
+					 */
+#define	IIO_ICCR_CMD_FLUSH	(0x800)
+
+/*
+ *
+ * CRB Register description.
+ *
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
+ *
+ * Many of the fields in CRB are status bits used by hardware
+ * for implementation of the protocol. It's very dangerous to
+ * mess around with the CRB registers.
+ *
+ * It's OK to read the CRB registers and try to make sense out of the
+ * fields in CRB.
+ *
+ * Updating CRB requires all activities in Hub IIO to be quiesced.
+ * otherwise, a write to CRB could corrupt other CRB entries.
+ * CRBs are here only as a back door peek to shub IIO's status.
+ * Quiescing implies  no dmas no PIOs
+ * either directly from the cpu or from sn0net.
+ * this is not something that can be done easily. So, AVOID updating
+ * CRBs.
+ */
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Easy access macros for CRBs, all 4 registers (A-D)
+ */
+typedef ii_icrb0_a_u_t icrba_t;
+#define a_lnetuce       ii_icrb0_a_fld_s.ia_ln_uce
+#define a_mark          ii_icrb0_a_fld_s.ia_mark
+#define a_xerr          ii_icrb0_a_fld_s.ia_xt_err
+#define a_sidn          ii_icrb0_a_fld_s.ia_sidn
+#define a_tnum          ii_icrb0_a_fld_s.ia_tnum
+#define a_addr          ii_icrb0_a_fld_s.ia_addr
+#define a_valid         ii_icrb0_a_fld_s.ia_vld
+#define a_iow           ii_icrb0_a_fld_s.ia_iow
+#define a_regvalue	ii_icrb0_a_regval
+
+typedef ii_icrb0_b_u_t icrbb_t;
+#define b_error         ii_icrb0_b_fld_s.ib_error
+#define b_ecode         ii_icrb0_b_fld_s.ib_errcode
+#define b_cohtrans      ii_icrb0_b_fld_s.ib_ct
+#define b_xtsize        ii_icrb0_b_fld_s.ib_size
+#define b_source        ii_icrb0_b_fld_s.ib_source
+#define b_imsgtype      ii_icrb0_b_fld_s.ib_imsgtype
+#define b_imsg          ii_icrb0_b_fld_s.ib_imsg
+#define b_initiator     ii_icrb0_b_fld_s.ib_init
+#define b_regvalue	ii_icrb0_b_regval
+
+typedef ii_icrb0_c_u_t icrbc_t;
+#define c_btenum        ii_icrb0_c_fld_s.ic_bte_num
+#define c_pricnt        ii_icrb0_c_fld_s.ic_pr_cnt
+#define c_pripsc        ii_icrb0_c_fld_s.ic_pr_psc
+#define c_bteaddr       ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
+#define c_benable       ii_icrb0_c_fld_s.ic_pa_be /* ic_pa_be fld has 2 names*/
+#define c_suppl         ii_icrb0_c_fld_s.ic_suppl
+#define c_barrop        ii_icrb0_c_fld_s.ic_bo
+#define c_doresp        ii_icrb0_c_fld_s.ic_resprqd
+#define c_gbr           ii_icrb0_c_fld_s.ic_gbr
+#define c_regvalue	ii_icrb0_c_regval
+
+typedef ii_icrb0_d_u_t icrbd_t;
+#define d_bteop         ii_icrb0_d_fld_s.id_bte_op
+#define icrbd_ctxtvld   ii_icrb0_d_fld_s.id_cvld
+#define icrbd_toutvld   ii_icrb0_d_fld_s.id_tvld
+#define icrbd_context   ii_icrb0_d_fld_s.id_context
+#define d_regvalue	ii_icrb0_d_regval
+
+#endif /* __ASSEMBLY__ */
+
+/* Number of widgets supported by shub */
+#define HUB_NUM_WIDGET          9
+#define HUB_WIDGET_ID_MIN       0x8
+#define HUB_WIDGET_ID_MAX       0xf
+
+#define HUB_WIDGET_PART_NUM     0xc120
+#define MAX_HUBS_PER_XBOW       2
+
+#ifndef __ASSEMBLY__
+/* A few more #defines for backwards compatibility */
+#define iprb_t          ii_iprb0_u_t
+#define iprb_regval     ii_iprb0_regval
+#define iprb_mult_err	ii_iprb0_fld_s.i_mult_err
+#define iprb_spur_rd	ii_iprb0_fld_s.i_spur_rd
+#define iprb_spur_wr	ii_iprb0_fld_s.i_spur_wr
+#define iprb_rd_to	ii_iprb0_fld_s.i_rd_to
+#define iprb_ovflow     ii_iprb0_fld_s.i_of_cnt
+#define iprb_error      ii_iprb0_fld_s.i_error
+#define iprb_ff         ii_iprb0_fld_s.i_f
+#define iprb_mode       ii_iprb0_fld_s.i_m
+#define iprb_bnakctr    ii_iprb0_fld_s.i_nb
+#define iprb_anakctr    ii_iprb0_fld_s.i_na
+#define iprb_xtalkctr   ii_iprb0_fld_s.i_c
+#endif
+
+#define LNK_STAT_WORKING        0x2		/* LLP is working */
+
+#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
+#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
+#define IIO_WSTAT_TXRETRY_MASK  (0x7F)   /* should be 0xFF?? */
+#define IIO_WSTAT_TXRETRY_SHFT  (16)
+#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
+                                          IIO_WSTAT_TXRETRY_MASK)
+
+/* Number of II perf. counters we can multiplex at once */
+
+#define IO_PERF_SETS	32
+
+#if __KERNEL__
+#ifndef __ASSEMBLY__
+#include <asm/sn/alenlist.h>
+#include <asm/sn/dmamap.h>
+#include <asm/sn/driver.h>
+#include <asm/sn/xtalk/xtalk.h>
+
+/* Bit for the widget in inbound access register */
+#define IIO_IIWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+/* Bit for the widget in outbound access register */
+#define IIO_IOWA_WIDGET(_w)     ((uint64_t)(1ULL << _w))
+
+/* NOTE: The following define assumes that we are going to get
+ * widget numbers from 8 thru F and the device numbers within
+ * widget from 0 thru 7.
+ */
+#define IIO_IIDEM_WIDGETDEV_MASK(w, d)  ((uint64_t)(1ULL << (8 * ((w) - 8) + (d))))
+
+/* IO Interrupt Destination Register */
+#define IIO_IIDSR_SENT_SHIFT    28
+#define IIO_IIDSR_SENT_MASK     0x10000000
+#define IIO_IIDSR_ENB_SHIFT     24
+#define IIO_IIDSR_ENB_MASK      0x01000000
+#define IIO_IIDSR_NODE_SHIFT    8
+#define IIO_IIDSR_NODE_MASK     0x0000ff00
+#define IIO_IIDSR_PI_ID_SHIFT   8
+#define IIO_IIDSR_PI_ID_MASK    0x00000010
+#define IIO_IIDSR_LVL_SHIFT     0
+#define IIO_IIDSR_LVL_MASK      0x0000007f
+
+/* Xtalk timeout threshhold register (IIO_IXTT) */
+#define IXTT_RRSP_TO_SHFT	55	   /* read response timeout */
+#define IXTT_RRSP_TO_MASK	(0x1FULL << IXTT_RRSP_TO_SHFT)
+#define IXTT_RRSP_PS_SHFT	32	   /* read responsed TO prescalar */
+#define IXTT_RRSP_PS_MASK	(0x7FFFFFULL << IXTT_RRSP_PS_SHFT)
+#define IXTT_TAIL_TO_SHFT	0	   /* tail timeout counter threshold */
+#define IXTT_TAIL_TO_MASK	(0x3FFFFFFULL << IXTT_TAIL_TO_SHFT)
+
+/*
+ * The IO LLP control status register and widget control register
+ */
+
+typedef union hubii_wcr_u {
+        uint64_t      wcr_reg_value;
+        struct {
+	  uint64_t	wcr_widget_id:   4,     /* LLP crossbar credit */
+			wcr_tag_mode:	 1,	/* Tag mode */
+			wcr_rsvd1:	 8,	/* Reserved */
+			wcr_xbar_crd:	 3,	/* LLP crossbar credit */
+			wcr_f_bad_pkt:	 1,	/* Force bad llp pkt enable */
+			wcr_dir_con:	 1,	/* widget direct connect */
+			wcr_e_thresh:	 5,	/* elasticity threshold */
+			wcr_rsvd:	41;	/* unused */
+        } wcr_fields_s;
+} hubii_wcr_t;
+
+#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
+
+/* The structures below are defined to extract and modify the ii
+performance registers */
+
+/* io_perf_sel allows the caller to specify what tests will be
+   performed */
+
+typedef union io_perf_sel {
+        uint64_t perf_sel_reg;
+        struct {
+               uint64_t	perf_ippr0 :  4,
+				perf_ippr1 :  4,
+				perf_icct  :  8,
+				perf_rsvd  : 48;
+        } perf_sel_bits;
+} io_perf_sel_t;
+
+/* io_perf_cnt is to extract the count from the shub registers. Due to
+   hardware problems there is only one counter, not two. */
+
+typedef union io_perf_cnt {
+        uint64_t      perf_cnt;
+        struct {
+               uint64_t	perf_cnt   : 20,
+				perf_rsvd2 : 12,
+				perf_rsvd1 : 32;
+        } perf_cnt_bits;
+
+} io_perf_cnt_t;
+
+typedef union iprte_a {
+	shubreg_t	entry;
+	struct {
+		shubreg_t	i_rsvd_1                  :	 3;
+		shubreg_t	i_addr			  :	38;
+		shubreg_t	i_init			  :	 3;
+		shubreg_t	i_source		  :	 8;
+		shubreg_t	i_rsvd			  :	 2;
+		shubreg_t	i_widget		  :	 4;
+		shubreg_t	i_to_cnt		  :	 5;
+		shubreg_t       i_vld                     :      1;
+	} iprte_fields;
+} iprte_a_t;
+
+
+/* PIO MANAGEMENT */
+typedef struct hub_piomap_s *hub_piomap_t;
+
+extern hub_piomap_t
+hub_piomap_alloc(devfs_handle_t dev,      /* set up mapping for this device */
+                device_desc_t dev_desc, /* device descriptor */
+                iopaddr_t xtalk_addr,   /* map for this xtalk_addr range */
+                size_t byte_count,
+                size_t byte_count_max,  /* maximum size of a mapping */
+                unsigned flags);                /* defined in sys/pio.h */
+
+extern void hub_piomap_free(hub_piomap_t hub_piomap);
+
+extern caddr_t
+hub_piomap_addr(hub_piomap_t hub_piomap,        /* mapping resources */
+                iopaddr_t xtalk_addr,           /* map for this xtalk addr */
+                size_t byte_count);             /* map this many bytes */
+
+extern void
+hub_piomap_done(hub_piomap_t hub_piomap);
+
+extern caddr_t
+hub_piotrans_addr(      devfs_handle_t dev,       /* translate to this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        iopaddr_t xtalk_addr,   /* Crosstalk address */
+                        size_t byte_count,      /* map this many bytes */
+                        unsigned flags);        /* (currently unused) */
+
+/* DMA MANAGEMENT */
+typedef struct hub_dmamap_s *hub_dmamap_t;
+
+extern hub_dmamap_t
+hub_dmamap_alloc(       devfs_handle_t dev,       /* set up mappings for dev */
+                        device_desc_t dev_desc, /* device descriptor */
+                        size_t byte_count_max,  /* max size of a mapping */
+                        unsigned flags);        /* defined in dma.h */
+
+extern void
+hub_dmamap_free(hub_dmamap_t dmamap);
+
+extern iopaddr_t
+hub_dmamap_addr(        hub_dmamap_t dmamap,    /* use mapping resources */
+                        paddr_t paddr,          /* map for this address */
+                        size_t byte_count);     /* map this many bytes */
+
+extern alenlist_t
+hub_dmamap_list(        hub_dmamap_t dmamap,    /* use mapping resources */
+                        alenlist_t alenlist,    /* map this Addr/Length List */
+                        unsigned flags);
+
+extern void
+hub_dmamap_done(        hub_dmamap_t dmamap);   /* done w/ mapping resources */
+
+extern iopaddr_t
+hub_dmatrans_addr(      devfs_handle_t dev,       /* translate for this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        paddr_t paddr,          /* system physical address */
+                        size_t byte_count,      /* length */
+                        unsigned flags);                /* defined in dma.h */
+
+extern alenlist_t
+hub_dmatrans_list(      devfs_handle_t dev,       /* translate for this device */
+                        device_desc_t dev_desc, /* device descriptor */
+                        alenlist_t palenlist,   /* system addr/length list */
+                        unsigned flags);                /* defined in dma.h */
+
+extern void
+hub_dmamap_drain(       hub_dmamap_t map);
+
+extern void
+hub_dmaaddr_drain(      devfs_handle_t vhdl,
+                        paddr_t addr,
+                        size_t bytes);
+
+extern void
+hub_dmalist_drain(      devfs_handle_t vhdl,
+                        alenlist_t list);
+
+
+/* INTERRUPT MANAGEMENT */
+typedef struct hub_intr_s *hub_intr_t;
+
+extern hub_intr_t
+hub_intr_alloc( devfs_handle_t dev,               /* which device */
+                device_desc_t dev_desc,         /* device descriptor */
+                devfs_handle_t owner_dev);        /* owner of this interrupt */
+
+extern hub_intr_t
+hub_intr_alloc_nothd(devfs_handle_t dev,          /* which device */
+                device_desc_t dev_desc,         /* device descriptor */
+                devfs_handle_t owner_dev);        /* owner of this interrupt */
+
+extern void
+hub_intr_free(hub_intr_t intr_hdl);
+
+extern int
+hub_intr_connect(       hub_intr_t intr_hdl,    /* xtalk intr resource hndl */
+                        xtalk_intr_setfunc_t setfunc,
+                                                /* func to set intr hw */
+                        void *setfunc_arg);     /* arg to setfunc */
+
+extern void
+hub_intr_disconnect(hub_intr_t intr_hdl);
+
+extern devfs_handle_t
+hub_intr_cpu_get(hub_intr_t intr_hdl);
+
+/* CONFIGURATION MANAGEMENT */
+
+extern void
+hub_provider_startup(devfs_handle_t hub);
+
+extern void
+hub_provider_shutdown(devfs_handle_t hub);
+
+#define HUB_PIO_CONVEYOR        0x1     /* PIO in conveyor belt mode */
+#define HUB_PIO_FIRE_N_FORGET   0x2     /* PIO in fire-and-forget mode */
+
+/* Flags that make sense to hub_widget_flags_set */
+#define HUB_WIDGET_FLAGS        (                               \
+				 HUB_PIO_CONVEYOR       |       \
+				 HUB_PIO_FIRE_N_FORGET          \
+				)
+
+
+typedef int     hub_widget_flags_t;
+
+/* Set the PIO mode for a widget.  These two functions perform the
+ * same operation, but hub_device_flags_set() takes a hardware graph
+ * vertex while hub_widget_flags_set() takes a nasid and widget
+ * number.  In most cases, hub_device_flags_set() should be used.
+ */
+extern int      hub_widget_flags_set(nasid_t            nasid,
+                                     xwidgetnum_t       widget_num,
+                                     hub_widget_flags_t flags);
+
+/* Depending on the flags set take the appropriate actions */
+extern int      hub_device_flags_set(devfs_handle_t       widget_dev,
+                                     hub_widget_flags_t flags);
+                                                    
+
+/* Error Handling. */
+extern int hub_ioerror_handler(devfs_handle_t, int, int, struct io_error_s *);
+extern int kl_ioerror_handler(cnodeid_t, cnodeid_t, cpuid_t,
+                              int, paddr_t, caddr_t, ioerror_mode_t);
+extern void hub_widget_reset(devfs_handle_t, xwidgetnum_t);
+extern int hub_error_devenable(devfs_handle_t, int, int);
+extern void hub_widgetdev_enable(devfs_handle_t, int);
+extern void hub_widgetdev_shutdown(devfs_handle_t, int);
+extern int  hub_dma_enabled(devfs_handle_t);
+
+/* hubdev */
+extern void hubdev_init(void);
+extern void hubdev_register(int (*attach_method)(devfs_handle_t));
+extern int hubdev_unregister(int (*attach_method)(devfs_handle_t));
+extern int hubdev_docallouts(devfs_handle_t hub);
+
+extern caddr_t hubdev_prombase_get(devfs_handle_t hub);
+extern cnodeid_t hubdev_cnodeid_get(devfs_handle_t hub);
+
+#endif /* __ASSEMBLY__ */
+#endif /* _KERNEL */
+#endif /* _ASM_IA64_SN_SN2_SHUBIO_H */
+
diff -Nru a/include/asm-ia64/sn/sn2/slotnum.h b/include/asm-ia64/sn/sn2/slotnum.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/slotnum.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,41 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (c) 1992 - 1997,2001 Silicon Graphics, Inc.  All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_SN2_SLOTNUM_H
+#define _ASM_IA64_SN_SN2_SLOTNUM_H
+
+#define SLOTNUM_MAXLENGTH	16
+
+/*
+ * This file defines IO widget to slot/device assignments.
+ */
+
+
+/* This determines module to pnode mapping. */
+
+#define NODESLOTS_PER_MODULE		1
+#define NODESLOTS_PER_MODULE_SHFT	1
+
+#define SLOTNUM_NODE_CLASS	0x00	/* Node   */
+#define SLOTNUM_ROUTER_CLASS	0x10	/* Router */
+#define SLOTNUM_XTALK_CLASS	0x20	/* Xtalk  */
+#define SLOTNUM_MIDPLANE_CLASS	0x30	/* Midplane */
+#define SLOTNUM_XBOW_CLASS	0x40	/* Xbow  */
+#define SLOTNUM_KNODE_CLASS	0x50	/* Kego node */
+#define SLOTNUM_PCI_CLASS	0x60	/* PCI widgets on XBridge */
+#define SLOTNUM_INVALID_CLASS	0xf0	/* Invalid */
+
+#define SLOTNUM_CLASS_MASK	0xf0
+#define SLOTNUM_SLOT_MASK	0x0f
+
+#define SLOTNUM_GETCLASS(_sn)	((_sn) & SLOTNUM_CLASS_MASK)
+#define SLOTNUM_GETSLOT(_sn)	((_sn) & SLOTNUM_SLOT_MASK)
+
+
+#endif /* _ASM_IA64_SN_SN2_SLOTNUM_H */
diff -Nru a/include/asm-ia64/sn/sn2/sn_private.h b/include/asm-ia64/sn/sn2/sn_private.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn2/sn_private.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,251 @@
+/* $Id$
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+#ifndef _ASM_IA64_SN_SN2_SN_PRIVATE_H
+#define _ASM_IA64_SN_SN2_SN_PRIVATE_H
+
+#include <asm/sn/nodepda.h>
+#include <asm/sn/io.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xtalk_private.h>
+
+extern nasid_t master_nasid;
+
+/* promif.c */
+extern void he_arcs_set_vectors(void);
+extern void mem_init(void);
+extern void cpu_unenable(cpuid_t);
+extern nasid_t get_lowest_nasid(void);
+extern __psunsigned_t get_master_bridge_base(void);
+extern void set_master_bridge_base(void);
+extern int check_nasid_equiv(nasid_t, nasid_t);
+extern nasid_t get_console_nasid(void);
+extern char get_console_pcislot(void);
+
+extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
+
+/* memsupport.c */
+extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
+extern int memory_present(paddr_t);
+extern int memory_read_accessible(paddr_t);
+extern int memory_write_accessible(paddr_t);
+extern void memory_set_access(paddr_t, int, int);
+extern void show_dir_state(paddr_t, void (*)(char *, ...));
+extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
+extern void set_dir_owner(paddr_t, int);
+extern void set_dir_state(paddr_t, int);
+extern void set_dir_state_POISONED(paddr_t);
+extern void set_dir_state_UNOWNED(paddr_t);
+extern int is_POISONED_dir_state(paddr_t);
+extern int is_UNOWNED_dir_state(paddr_t);
+extern void get_dir_ent(paddr_t paddr, int *state,
+			uint64_t *vec_ptr, hubreg_t *elo);
+
+/* intr.c */
+extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
+extern void intr_unreserve_level(cpuid_t cpu, int level);
+extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
+			intr_func_t intr_prefunc);
+extern int intr_disconnect_level(cpuid_t cpu, int bit);
+extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
+			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
+			      char *intr_name,int *resp_bit);
+extern void intr_block_bit(cpuid_t cpu, int bit);
+extern void intr_unblock_bit(cpuid_t cpu, int bit);
+extern void setrtvector(intr_func_t);
+extern void install_cpuintr(cpuid_t cpu);
+extern void install_dbgintr(cpuid_t cpu);
+extern void install_tlbintr(cpuid_t cpu);
+extern void hub_migrintr_init(cnodeid_t /*cnode*/);
+extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
+extern int cause_intr_disconnect(int level);
+extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
+
+/* error_dump.c */
+extern char *hub_rrb_err_type[];
+extern char *hub_wrb_err_type[];
+
+void nmi_dump(void);
+void install_cpu_nmi_handler(int slice);
+
+/* klclock.c */
+extern void hub_rtc_init(cnodeid_t);
+
+/* bte.c */
+void bte_lateinit(void);
+void bte_wait_for_xfer_completion(void *);
+
+/* klgraph.c */
+void klhwg_add_all_nodes(devfs_handle_t);
+void klhwg_add_all_modules(devfs_handle_t);
+
+/* klidbg.c */
+void install_klidbg_functions(void);
+
+/* klnuma.c */
+extern void replicate_kernel_text(int numnodes);
+extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
+extern void setup_replication_mask(int maxnodes);
+
+/* init.c */
+extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
+extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
+extern void init_platform_pda(cpuid_t cpu);
+extern void per_cpu_init(void);
+extern int is_fine_dirmode(void);
+extern void update_node_information(cnodeid_t);
+ 
+/* shubio.c */
+extern void hubio_init(void);
+extern void hub_merge_clean(nasid_t nasid);
+extern void hub_set_piomode(nasid_t nasid, int conveyor);
+
+/* shuberror.c */
+extern void hub_error_init(cnodeid_t);
+extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
+extern void hubni_error_handler(char *, int);
+extern int check_ni_errors(void);
+
+/* Used for debugger to signal upper software a breakpoint has taken place */
+
+extern void		*debugger_update;
+extern __psunsigned_t	debugger_stopped;
+
+/* 
+ * piomap, created by shub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_piomap_s by generic xtalk routines.
+ */
+struct hub_piomap_s {
+	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
+	devfs_handle_t		hpio_hub;	/* which shub's mapping registers are set up */
+	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
+	char			hpio_bigwin_num;/* if big window map, which one */
+	int 			hpio_flags;	/* defined below */
+};
+/* hub_piomap flags */
+#define HUB_PIOMAP_IS_VALID		0x1
+#define HUB_PIOMAP_IS_BIGWINDOW		0x2
+#define HUB_PIOMAP_IS_FIXED		0x4
+
+#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
+#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
+#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
+
+/* 
+ * dmamap, created by shub_pio_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_dmamap_s by generic xtalk routines.
+ */
+struct hub_dmamap_s {
+	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
+	devfs_handle_t		hdma_hub;	/* which shub we go through */
+	int			hdma_flags;	/* defined below */
+};
+/* shub_dmamap flags */
+#define HUB_DMAMAP_IS_VALID		0x1
+#define HUB_DMAMAP_USED			0x2
+#define	HUB_DMAMAP_IS_FIXED		0x4
+
+/* 
+ * interrupt handle, created by shub_intr_alloc.
+ * xtalk_info MUST BE FIRST, since this structure is cast to a
+ * xtalk_intr_s by generic xtalk routines.
+ */
+struct hub_intr_s {
+	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
+	ilvl_t			i_swlevel;	/* software level for blocking intr */
+	cpuid_t			i_cpuid;	/* which cpu */
+	int			i_bit;		/* which bit */
+	int			i_flags;
+};
+/* flag values */
+#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
+#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
+
+typedef struct hubinfo_s {
+	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
+	cnodeid_t			h_cnodeid;	/* compact nodeid */
+	nasid_t				h_nasid;	/* nasid */
+
+	/* structures for PIO management */
+	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
+	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
+	sv_t				h_bwwait;	/* wait for big window to free */
+	spinlock_t			h_bwlock;	/* guard big window piomap's */
+	spinlock_t			h_crblock;      /* gaurd CRB error handling */
+	int				h_num_big_window_fixed;	/* count number of FIXED maps */
+	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
+	hub_intr_t			hub_ii_errintr;
+} *hubinfo_t;
+
+#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
+
+#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
+
+#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
+
+/*
+ * Hub info PIO map access functions.
+ */
+#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
+			(&hinfo->h_big_window_piomap[win])
+#define	hubinfo_swin_piomap_get(hinfo, win)	\
+			(&hinfo->h_small_window_piomap[win])
+	
+/* cpu-specific information stored under INFO_LBL_CPU_INFO */
+typedef struct cpuinfo_s {
+	cpuid_t		ci_cpuid;	/* CPU ID */
+} *cpuinfo_t;
+
+#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
+
+#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
+	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
+
+/* Special initialization function for xswitch vertices created during startup. */
+extern void xswitch_vertex_init(devfs_handle_t xswitch);
+
+extern xtalk_provider_t hub_provider;
+
+/* du.c */
+int ducons_write(char *buf, int len);
+
+/* memerror.c */
+
+extern void install_eccintr(cpuid_t cpu);
+extern void memerror_get_stats(cnodeid_t cnode,
+			       int *bank_stats, int *bank_stats_max);
+extern void probe_md_errors(nasid_t);
+/* sysctlr.c */
+extern void sysctlr_init(void);
+extern void sysctlr_power_off(int sdonly);
+extern void sysctlr_keepalive(void);
+
+#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
+
+/* Useful definitions to get the memory dimm given a physical
+ * address.
+ */
+#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
+#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
+extern void membank_pathname_get(paddr_t,char *);
+
+/* To redirect the output into the error buffer */
+#define errbuf_print(_s)	printf("#%s",_s)
+
+extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
+void bootstrap(void);
+
+/* sndrv.c */
+extern int sndrv_attach(devfs_handle_t vertex);
+
+#endif /* _ASM_IA64_SN_SN2_SN_PRIVATE_H */
diff -Nru a/include/asm-ia64/sn/sn_cpuid.h b/include/asm-ia64/sn/sn_cpuid.h
--- a/include/asm-ia64/sn/sn_cpuid.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn_cpuid.h	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Jack Steiner (steiner@sgi.com)
+ * Copyright (C) 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
 
 
@@ -13,8 +12,13 @@
 #define _ASM_IA64_SN_SN_CPUID_H
 
 #include <linux/config.h>
-#include <asm/processor.h>
-#include <asm/sn/mmzone_sn1.h>
+#include <linux/smp.h>
+#include <linux/sched.h>
+#include <linux/mmzone.h>
+#include <asm/sn/types.h>
+#include <asm/current.h>
+#include <asm/nodedata.h>
+
 
 /*
  * Functions for converting between cpuids, nodeids and NASIDs.
@@ -46,10 +50,15 @@
  *				* not real efficient - dont use in perf critical code
  *
  *         LID - processor defined register (see PRM V2).
+ *
+ *           On SN1
  *		31:24 - id   Contains the NASID
  *		23:16 - eid  Contains 0-3 to identify the cpu on the node
  *				bit 17 - synergy number
  *				bit 16 - FSB slot number 
+ *           On SN2
+ *		31:28 - id   Contains 0-3 to identify the cpu on the node
+ *		27:16 - eid  Contains the NASID
  *
  *
  *
@@ -70,15 +79,15 @@
  *                |                       |
  *             -------                 -------
  *             |     |                 |     |
- *             |  0  |                 |  1  |         SYNERGY
+ *             |  0  |                 |  1  |         SYNERGY (SN1 only)
  *             |     |                 |     |
  *             -------                 -------
  *                |                       |
  *                |                       |
  *             -------------------------------
  *             |                             |
- *             |         BEDROCK             |        NASID   (0..127)
- *             |                             |        CNODEID (0..numnodes-1)
+ *             |         BEDROCK / SHUB      |        NASID   (0..MAX_NASIDS)
+ *             |                             |        CNODEID (0..num_compact_nodes-1)
  *             |                             |
  *             |                             |
  *             -------------------------------
@@ -91,10 +100,25 @@
 #define cpu_physical_id(cpuid)			((ia64_get_lid() >> 16) & 0xffff)
 #endif
 
+#ifdef CONFIG_IA64_SGI_SN1
+/*
+ * macros for some of these exist in sn/addrs.h & sn/arch.h, etc. However, 
+ * trying #include these files here causes circular dependencies.
+ */
 #define cpu_physical_id_to_nasid(cpi)		((cpi) >> 8)
 #define cpu_physical_id_to_synergy(cpi)		(((cpi) >> 1) & 1)
 #define cpu_physical_id_to_fsb_slot(cpi)	((cpi) & 1)
 #define cpu_physical_id_to_slice(cpi)		((cpi) & 3)
+#define get_nasid()				((ia64_get_lid() >> 24))
+#define get_slice()				((ia64_get_lid() >> 16) & 3)
+#define get_node_number(addr)			(((unsigned long)(addr)>>33) & 0x7f)
+#else
+#define cpu_physical_id_to_nasid(cpi)		((cpi) &0xfff)
+#define cpu_physical_id_to_slice(cpi)		((cpi>>12) & 3)
+#define get_nasid()				((ia64_get_lid() >> 16) & 0xfff)
+#define get_slice()				((ia64_get_lid() >> 28) & 0xf)
+#define get_node_number(addr)			(((unsigned long)(addr)>>38) & 0x7ff)
+#endif
 
 /*
  * NOTE: id & eid refer to Intels definitions of the LID register
@@ -118,15 +142,12 @@
 
 
 
+#ifdef CONFIG_IA64_SGI_SN1
 /*
  * cpuid_to_fsb_slot  - convert a cpuid to the fsb slot number that it is in.
  *   (there are 2 cpus per FSB. This function returns 0 or 1)
  */
-static __inline__ int
-cpuid_to_fsb_slot(int cpuid)
-{
-	return cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid));
-}
+#define cpuid_to_fsb_slot(cpuid)	(cpu_physical_id_to_fsb_slot(cpu_physical_id(cpuid)))
 
 
 /*
@@ -134,108 +155,75 @@
  *   (there are 2 synergies per node. Function returns 0 or 1 to
  *    specify which synergy the cpu is on)
  */
-static __inline__ int
-cpuid_to_synergy(int cpuid)
-{
-	return cpu_physical_id_to_synergy(cpu_physical_id(cpuid));
-}
+#define cpuid_to_synergy(cpuid)		(cpu_physical_id_to_synergy(cpu_physical_id(cpuid)))
 
+#endif
 
 /*
  * cpuid_to_slice  - convert a cpuid to the slice that it resides on
  *  There are 4 cpus per node. This function returns 0 .. 3)
  */
-static __inline__ int
-cpuid_to_slice(int cpuid)
-{
-	return cpu_physical_id_to_slice(cpu_physical_id(cpuid));
-}
+#define cpuid_to_slice(cpuid)		(cpu_physical_id_to_slice(cpu_physical_id(cpuid)))
 
 
 /*
  * cpuid_to_nasid  - convert a cpuid to the NASID that it resides on
  */
-static __inline__ int
-cpuid_to_nasid(int cpuid)
-{
-	return cpu_physical_id_to_nasid(cpu_physical_id(cpuid));
-}
+#define cpuid_to_nasid(cpuid)		(cpu_physical_id_to_nasid(cpu_physical_id(cpuid)))
 
 
 /*
  * cpuid_to_cnodeid  - convert a cpuid to the cnode that it resides on
  */
-static __inline__ int
-cpuid_to_cnodeid(int cpuid)
-{
-	return nasid_map[cpuid_to_nasid(cpuid)];
-}
+#define cpuid_to_cnodeid(cpuid)		(local_node_data->physical_node_map[cpuid_to_nasid(cpuid)])
+
 
 /*
  * cnodeid_to_nasid - convert a cnodeid to a NASID
+ *	Macro relies on pg_data for a node being on the node itself.
+ *	Just extract the NASID from the pointer.
+ *
  */
-static __inline__ int
-cnodeid_to_nasid(int cnodeid)
-{
-	if (nasid_map[cnodeid_map[cnodeid]] != cnodeid)
-		panic("cnodeid_to_nasid, cnode = %d", cnodeid);
-	return cnodeid_map[cnodeid];
-}
+#define cnodeid_to_nasid(cnodeid)	(get_node_number(local_node_data->pg_data_ptrs[cnodeid]))
+ 
 
 /*
  * nasid_to_cnodeid - convert a NASID to a cnodeid
  */
-static __inline__ int
-nasid_to_cnodeid(int nasid)
-{
-	if (cnodeid_map[nasid_map[nasid]] != nasid)
-		panic("nasid_to_cnodeid");
-	return nasid_map[nasid];
-}
+#define nasid_to_cnodeid(nasid)		(local_node_data->physical_node_map[nasid])
 
 
 /*
  * cnode_slice_to_cpuid - convert a codeid & slice to a cpuid
  */
-static __inline__ int
-cnode_slice_to_cpuid(int cnodeid, int slice) {
-	return(id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),slice));
-}
+#define cnode_slice_to_cpuid(cnodeid,slice) (id_eid_to_cpuid(cnodeid_to_nasid(cnodeid),(slice)))
+ 
 
 /*
  * cpuid_to_subnode - convert a cpuid to the subnode it resides on.
  *   slice 0 & 1 are on subnode 0
  *   slice 2 & 3 are on subnode 1.
  */
-static __inline__ int
-cpuid_to_subnode(int cpuid) {
-	int ret = cpuid_to_slice(cpuid);
-	if (ret < 2) return 0;
-	else return 1;
-}
+#define cpuid_to_subnode(cpuid)		((cpuid_to_slice(cpuid)<2) ? 0 : 1)
+ 
 
 /*
  * cpuid_to_localslice - convert a cpuid to a local slice
  *    slice 0 & 2 are local slice 0
  *    slice 1 & 3 are local slice 1
  */
-static __inline__ int
-cpuid_to_localslice(int cpuid) {
-	return(cpuid_to_slice(cpuid) & 1);
-}
-
-static __inline__ int
-cnodeid_to_cpuid(int cnode) {
-	int cpu;
-
-	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
-		if (cpuid_to_cnodeid(cpu) == cnode) {
-			break;
-		}
-	}
-	if (cpu == smp_num_cpus) cpu = -1;
-	return cpu;
-}
+#define cpuid_to_localslice(cpuid)	(cpuid_to_slice(cpuid) & 1)
+ 
+
+#define smp_physical_node_id()			(cpuid_to_nasid(smp_processor_id()))
+
+
+/*
+ * cnodeid_to_cpuid - convert a cnode  to a cpuid of a cpu on the node.
+ *	returns -1 if no cpus exist on the node
+ */
+extern int cnodeid_to_cpuid(int cnode);
 
 
 #endif /* _ASM_IA64_SN_SN_CPUID_H */
+
diff -Nru a/include/asm-ia64/sn/sn_fru.h b/include/asm-ia64/sn/sn_fru.h
--- a/include/asm-ia64/sn/sn_fru.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn_fru.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,11 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 1999-2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Patrick Gefre
+ * Copyright (C) 1992 - 1997, 1999-2001 Silicon Graphics, Inc. 
+ * All rights reserved.
  */
-#ifndef _ASM_SN_SN_FRU_H
-#define _ASM_SN_SN_FRU_H
+#ifndef _ASM_IA64_SN_SN_FRU_H
+#define _ASM_IA64_SN_SN_FRU_H
 
 #define MAX_DIMMS			8	 /* max # of dimm banks */
 #define MAX_PCIDEV			8	 /* max # of pci devices on a pci bus */
@@ -42,5 +42,5 @@
 } kf_pci_bus_t;
 
 
-#endif	/* _ASM_SN_SN_FRU_H */
+#endif /* _ASM_IA64_SN_SN_FRU_H */
 
diff -Nru a/include/asm-ia64/sn/sn_pio_sync.h b/include/asm-ia64/sn/sn_pio_sync.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sn_pio_sync.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,53 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001-2002 Silicon Graphics, Inc. All rights reserved.
+ */
+
+
+#ifndef _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H
+#define _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H
+
+#include <linux/config.h>
+#ifdef CONFIG_IA64_SGI_SN2
+#include <asm/sn/sn_cpuid.h>
+#include <asm/sn/sn2/addrs.h>
+#include <asm/sn/sn2/shub_mmr.h>
+#include <asm/sn/sn2/shub_mmr_t.h>
+
+/*
+ * This macro flushes all outstanding PIOs performed by this cpu to the 
+ * intended destination SHUB.  This in essence ensures that all PIO's
+ * issues by this cpu has landed at it's destination.
+ *
+ * This macro expects the caller:
+ *	1.  The thread is locked.
+ *	2.  All prior PIO operations has been fenced with __ia64_mf_a().
+ *
+ * The expectation is that get_slice() will return either 0 or 2.
+ * When we have multi-core cpu's, the expectation is get_slice() will 
+ * return either 0,1 or 2,3.
+ */
+
+#define SN_PIO_WRITE_SYNC \
+	{ \
+		volatile unsigned long sn_pio_writes_done; \
+	do { \
+		sn_pio_writes_done = (volatile unsigned long) (SH_PIO_WRITE_STATUS_0_WRITES_OK_MASK & HUB_L( (unsigned long *)GLOBAL_MMR_ADDR(get_nasid(), (get_slice() < 2) ? SH_PIO_WRITE_STATUS_0 : SH_PIO_WRITE_STATUS_1 ))); \
+	} while (!sn_pio_writes_done); \
+	__ia64_mf_a(); \
+	}
+#else
+
+/*
+ * For all ARCHITECTURE type, this is a NOOP.
+ */
+
+#define SN_PIO_WRITE_SYNC
+
+#endif
+
+#endif /* _ASM_IA64_SN_SN_PIO_WRITE_SYNC_H */
diff -Nru a/include/asm-ia64/sn/sn_private.h b/include/asm-ia64/sn/sn_private.h
--- a/include/asm-ia64/sn/sn_private.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/sn_private.h	Fri Mar 15 17:51:01 2002
@@ -4,299 +4,20 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_PRIVATE_H
-#define _ASM_SN_PRIVATE_H
+#ifndef _ASM_IA64_SN_SN_PRIVATE_H
+#define _ASM_IA64_SN_SN_PRIVATE_H
 
+#include <linux/config.h>
 #include <asm/sn/nodepda.h>
 #include <asm/sn/xtalk/xwidget.h>
 #include <asm/sn/xtalk/xtalk_private.h>
 
-extern nasid_t master_nasid;
-
-extern hubreg_t get_region(cnodeid_t);
-extern hubreg_t	nasid_to_region(nasid_t);
-/* promif.c */
-#ifdef	LATER
-extern cpuid_t cpu_node_probe(cpumask_t *cpumask, int *numnodes);
-#endif
-extern void he_arcs_set_vectors(void);
-extern void mem_init(void);
-#ifdef	LATER
-extern int cpu_enabled(cpuid_t);
-#endif
-extern void cpu_unenable(cpuid_t);
-extern nasid_t get_lowest_nasid(void);
-extern __psunsigned_t get_master_bridge_base(void);
-extern void set_master_bridge_base(void);
-extern int check_nasid_equiv(nasid_t, nasid_t);
-extern nasid_t get_console_nasid(void);
-extern char get_console_pcislot(void);
-#ifdef	LATER
-extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
-#endif
-
-extern int is_master_nasid_widget(nasid_t test_nasid, xwidgetnum_t test_wid);
-
-/* memsupport.c */
-extern void poison_state_alter_range(__psunsigned_t start, int len, int poison);
-extern int memory_present(paddr_t);
-extern int memory_read_accessible(paddr_t);
-extern int memory_write_accessible(paddr_t);
-extern void memory_set_access(paddr_t, int, int);
-extern void show_dir_state(paddr_t, void (*)(char *, ...));
-extern void check_dir_state(nasid_t, int, void (*)(char *, ...));
-extern void set_dir_owner(paddr_t, int);
-extern void set_dir_state(paddr_t, int);
-extern void set_dir_state_POISONED(paddr_t);
-extern void set_dir_state_UNOWNED(paddr_t);
-extern int is_POISONED_dir_state(paddr_t);
-extern int is_UNOWNED_dir_state(paddr_t);
-extern void get_dir_ent(paddr_t paddr, int *state,
-			uint64_t *vec_ptr, hubreg_t *elo);
-
-/* intr.c */
-#if defined(NEW_INTERRUPTS)
-extern int intr_reserve_level(cpuid_t cpu, int level, int err, devfs_handle_t owner_dev, char *name);
-extern void intr_unreserve_level(cpuid_t cpu, int level);
-extern int intr_connect_level(cpuid_t cpu, int bit, ilvl_t mask_no, 
-			intr_func_t intr_func, void *intr_arg,
-			intr_func_t intr_prefunc);
-extern int intr_disconnect_level(cpuid_t cpu, int bit);
-extern cpuid_t intr_heuristic(devfs_handle_t dev, device_desc_t dev_desc,
-			      int req_bit,int intr_resflags,devfs_handle_t owner_dev,
-			      char *intr_name,int *resp_bit);
-#endif	/* NEW_INTERRUPTS */
-extern void intr_block_bit(cpuid_t cpu, int bit);
-extern void intr_unblock_bit(cpuid_t cpu, int bit);
-extern void setrtvector(intr_func_t);
-extern void install_cpuintr(cpuid_t cpu);
-extern void install_dbgintr(cpuid_t cpu);
-extern void install_tlbintr(cpuid_t cpu);
-extern void hub_migrintr_init(cnodeid_t /*cnode*/);
-extern int cause_intr_connect(int level, intr_func_t handler, uint intr_spl_mask);
-extern int cause_intr_disconnect(int level);
-extern void intr_reserve_hardwired(cnodeid_t);
-extern void intr_clear_all(nasid_t);
-extern void intr_dumpvec(cnodeid_t cnode, void (*pf)(char *, ...));
-extern int protected_broadcast(hubreg_t intrbit);
-
-/* error_dump.c */
-extern char *hub_rrb_err_type[];
-extern char *hub_wrb_err_type[];
-
-void nmi_dump(void);
-void install_cpu_nmi_handler(int slice);
-
-/* klclock.c */
-extern void hub_rtc_init(cnodeid_t);
-
-/* bte.c */
-void bte_lateinit(void);
-void bte_wait_for_xfer_completion(void *);
-
-/* klgraph.c */
-void klhwg_add_all_nodes(devfs_handle_t);
-void klhwg_add_all_modules(devfs_handle_t);
-
-/* klidbg.c */
-void install_klidbg_functions(void);
-
-/* klnuma.c */
-extern void replicate_kernel_text(int numnodes);
-extern __psunsigned_t get_freemem_start(cnodeid_t cnode);
-extern void setup_replication_mask(int maxnodes);
-
-/* init.c */
-extern cnodeid_t get_compact_nodeid(void);	/* get compact node id */
-#ifdef	LATER
-extern void init_platform_nodepda(nodepda_t *npda, cnodeid_t node);
-extern void init_platform_pda(pda_t *ppda, cpuid_t cpu);
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/sn_private.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#include <asm/sn/sn2/sn_private.h>
 #endif
-extern void per_cpu_init(void);
-extern void per_hub_init(cnodeid_t);
-#ifdef	LATER
-extern cpumask_t boot_cpumask;
-#endif
-extern int is_fine_dirmode(void);
-extern void update_node_information(cnodeid_t);
- 
-#ifdef	LATER
-/* clksupport.c */
-extern void early_counter_intr(eframe_t *);
-#endif
-
-/* hubio.c */
-extern void hubio_init(void);
-extern void hub_merge_clean(nasid_t nasid);
-extern void hub_set_piomode(nasid_t nasid, int conveyor);
-
-/* huberror.c */
-extern void hub_error_init(cnodeid_t);
-extern void dump_error_spool(cpuid_t cpu, void (*pf)(char *, ...));
-extern void hubni_error_handler(char *, int);
-extern int check_ni_errors(void);
-
-/* Used for debugger to signal upper software a breakpoint has taken place */
-
-extern void		*debugger_update;
-extern __psunsigned_t	debugger_stopped;
-
-/* 
- * IP27 piomap, created by hub_pio_alloc.
- * xtalk_info MUST BE FIRST, since this structure is cast to a
- * xtalk_piomap_s by generic xtalk routines.
- */
-struct hub_piomap_s {
-	struct xtalk_piomap_s	hpio_xtalk_info;/* standard crosstalk pio info */
-	devfs_handle_t		hpio_hub;	/* which hub's mapping registers are set up */
-	short			hpio_holdcnt;	/* count of current users of bigwin mapping */
-	char			hpio_bigwin_num;/* if big window map, which one */
-	int 			hpio_flags;	/* defined below */
-};
-/* hub_piomap flags */
-#define HUB_PIOMAP_IS_VALID		0x1
-#define HUB_PIOMAP_IS_BIGWINDOW		0x2
-#define HUB_PIOMAP_IS_FIXED		0x4
-
-#define	hub_piomap_xt_piomap(hp)	(&hp->hpio_xtalk_info)
-#define	hub_piomap_hub_v(hp)	(hp->hpio_hub)
-#define	hub_piomap_winnum(hp)	(hp->hpio_bigwin_num)
-
-#if TBD
- /* Ensure that hpio_xtalk_info is first */
- #assert (&(((struct hub_piomap_s *)0)->hpio_xtalk_info) == 0)
-#endif
-
-
-/* 
- * IP27 dmamap, created by hub_pio_alloc.
- * xtalk_info MUST BE FIRST, since this structure is cast to a
- * xtalk_dmamap_s by generic xtalk routines.
- */
-struct hub_dmamap_s {
-	struct xtalk_dmamap_s	hdma_xtalk_info;/* standard crosstalk dma info */
-	devfs_handle_t		hdma_hub;	/* which hub we go through */
-	int			hdma_flags;	/* defined below */
-};
-/* hub_dmamap flags */
-#define HUB_DMAMAP_IS_VALID		0x1
-#define HUB_DMAMAP_USED			0x2
-#define	HUB_DMAMAP_IS_FIXED		0x4
-
-#if TBD
- /* Ensure that hdma_xtalk_info is first */
- #assert (&(((struct hub_dmamap_s *)0)->hdma_xtalk_info) == 0)
-#endif
-
-/* 
- * IP27 interrupt handle, created by hub_intr_alloc.
- * xtalk_info MUST BE FIRST, since this structure is cast to a
- * xtalk_intr_s by generic xtalk routines.
- */
-struct hub_intr_s {
-	struct xtalk_intr_s	i_xtalk_info;	/* standard crosstalk intr info */
-	ilvl_t			i_swlevel;	/* software level for blocking intr */
-	cpuid_t			i_cpuid;	/* which cpu */
-	int			i_bit;		/* which bit */
-	int			i_flags;
-};
-/* flag values */
-#define HUB_INTR_IS_ALLOCED	0x1	/* for debug: allocated */
-#define HUB_INTR_IS_CONNECTED	0x4	/* for debug: connected to a software driver */
-
-#if TBD
- /* Ensure that i_xtalk_info is first */
- #assert (&(((struct hub_intr_s *)0)->i_xtalk_info) == 0)
-#endif
-
-
-/* IP27 hub-specific information stored under INFO_LBL_HUB_INFO */
-/* TBD: IP27-dependent stuff currently in nodepda.h should be here */
-typedef struct hubinfo_s {
-	nodepda_t			*h_nodepda;	/* pointer to node's private data area */
-	cnodeid_t			h_cnodeid;	/* compact nodeid */
-	nasid_t				h_nasid;	/* nasid */
-
-	/* structures for PIO management */
-	xwidgetnum_t			h_widgetid;	/* my widget # (as viewed from xbow) */
-	struct hub_piomap_s		h_small_window_piomap[HUB_WIDGET_ID_MAX+1];
-	sv_t				h_bwwait;	/* wait for big window to free */
-	spinlock_t			h_bwlock;	/* guard big window piomap's */
-	spinlock_t			h_crblock;      /* gaurd CRB error handling */
-	int				h_num_big_window_fixed;	/* count number of FIXED maps */
-	struct hub_piomap_s		h_big_window_piomap[HUB_NUM_BIG_WINDOW];
-	hub_intr_t			hub_ii_errintr;
-} *hubinfo_t;
-
-#define hubinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
-	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t *)infoptr))
-
-#define hubinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
-	(vhdl, INFO_LBL_NODE_INFO, (arbitrary_info_t)infoptr)
-
-#define	hubinfo_to_hubv(hinfo, hub_v)	(hinfo->h_nodepda->node_vertex)
-
-/*
- * Hub info PIO map access functions.
- */
-#define	hubinfo_bwin_piomap_get(hinfo, win) 	\
-			(&hinfo->h_big_window_piomap[win])
-#define	hubinfo_swin_piomap_get(hinfo, win)	\
-			(&hinfo->h_small_window_piomap[win])
-	
-/* IP27 cpu-specific information stored under INFO_LBL_CPU_INFO */
-/* TBD: IP27-dependent stuff currently in pda.h should be here */
-typedef struct cpuinfo_s {
-#ifdef	LATER
-	pda_t		*ci_cpupda;	/* pointer to CPU's private data area */
-#endif
-	cpuid_t		ci_cpuid;	/* CPU ID */
-} *cpuinfo_t;
-
-#define cpuinfo_get(vhdl, infoptr) ((void)hwgraph_info_get_LBL \
-	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t *)infoptr))
-
-#define cpuinfo_set(vhdl, infoptr) (void)hwgraph_info_add_LBL \
-	(vhdl, INFO_LBL_CPU_INFO, (arbitrary_info_t)infoptr)
-
-/* Special initialization function for xswitch vertices created during startup. */
-extern void xswitch_vertex_init(devfs_handle_t xswitch);
-
-extern xtalk_provider_t hub_provider;
-
-/* du.c */
-int ducons_write(char *buf, int len);
-
-/* memerror.c */
-
-extern void install_eccintr(cpuid_t cpu);
-extern void memerror_get_stats(cnodeid_t cnode,
-			       int *bank_stats, int *bank_stats_max);
-extern void probe_md_errors(nasid_t);
-/* sysctlr.c */
-extern void sysctlr_init(void);
-extern void sysctlr_power_off(int sdonly);
-extern void sysctlr_keepalive(void);
-
-#define valid_cpuid(_x)		(((_x) >= 0) && ((_x) < maxcpus))
-
-/* Useful definitions to get the memory dimm given a physical
- * address.
- */
-#define paddr_dimm(_pa)		((_pa & MD_BANK_MASK) >> MD_BANK_SHFT)
-#define paddr_cnode(_pa)	(NASID_TO_COMPACT_NODEID(NASID_GET(_pa)))
-extern void membank_pathname_get(paddr_t,char *);
-
-/* To redirect the output into the error buffer */
-#define errbuf_print(_s)	printf("#%s",_s)
-
-extern void crbx(nasid_t nasid, void (*pf)(char *, ...));
-void bootstrap(void);
-
-/* sndrv.c */
-extern int sndrv_attach(devfs_handle_t vertex);
 
-#endif /* _ASM_SN_PRIVATE_H */
+#endif /* _ASM_IA64_SN_SN_PRIVATE_H */
diff -Nru a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
--- a/include/asm-ia64/sn/sn_sal.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/sn_sal.h	Fri Mar 15 17:51:03 2002
@@ -1,25 +1,81 @@
-#ifndef _ASM_IA64_SN_SAL_H
-#define _ASM_IA64_SN_SAL_H
+#ifndef _ASM_IA64_SN_SN_SAL_H
+#define _ASM_IA64_SN_SN_SAL_H
 
 /*
  * System Abstraction Layer definitions for IA64
  *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
  *
- * Copyright (C) 2000, Silicon Graphics.
- * Copyright (C) 2000. Jack Steiner (steiner@sgi.com)
+ * Copyright (c) 2000-2002 Silicon Graphics, Inc.  All rights reserved.
  */
 
 
 #include <asm/sal.h>
+#include <asm/sn/sn_cpuid.h>
 
 
 // SGI Specific Calls
 #define  SN_SAL_POD_MODE                           0x02000001
 #define  SN_SAL_SYSTEM_RESET                       0x02000002
 #define  SN_SAL_PROBE                              0x02000003
+#define  SN_SAL_GET_CONSOLE_NASID                  0x02000004
+#define	 SN_SAL_GET_KLCONFIG_ADDR		   0x02000005
+#define  SN_SAL_LOG_CE				   0x02000006
+#define  SN_SAL_REGISTER_CE			   0x02000007
 
 
 u64 ia64_sn_probe_io_slot(long paddr, long size, void *data_ptr);
 
+/*
+ * Returns the master console nasid, if the call fails, return an illegal
+ * value.
+ */
+static inline u64
+ia64_sn_get_console_nasid(void)
+{
+	struct ia64_sal_retval ret_stuff;
+
+	ret_stuff.status = (uint64_t)0;
+	ret_stuff.v0 = (uint64_t)0;
+	ret_stuff.v1 = (uint64_t)0;
+	ret_stuff.v2 = (uint64_t)0;
+	SAL_CALL(ret_stuff, SN_SAL_GET_CONSOLE_NASID, 0, 0, 0, 0, 0, 0, 0);
+
+	if (ret_stuff.status < 0)
+		return ret_stuff.status;
+
+	/* Master console nasid is in 'v0' */
+	return ret_stuff.v0;
+}
+
+static inline u64
+ia64_sn_get_klconfig_addr(nasid_t nasid)
+{
+	struct ia64_sal_retval ret_stuff;
+	extern u64 klgraph_addr[];
+	int cnodeid;
+
+	cnodeid = nasid_to_cnodeid(nasid);
+	if (klgraph_addr[cnodeid] == 0) {
+		ret_stuff.status = (uint64_t)0;
+		ret_stuff.v0 = (uint64_t)0;
+		ret_stuff.v1 = (uint64_t)0;
+		ret_stuff.v2 = (uint64_t)0;
+		SAL_CALL(ret_stuff, SN_SAL_GET_KLCONFIG_ADDR, (u64)nasid, 0, 0, 0, 0, 0, 0);
+
+		/*
+	 	* We should panic if a valid cnode nasid does not produce
+	 	* a klconfig address.
+	 	*/
+		if (ret_stuff.status != 0) {
+			panic("ia64_sn_get_klconfig_addr: Returned error %lx\n", ret_stuff.status);
+		}
+
+		klgraph_addr[cnodeid] = ret_stuff.v0;
+	}
+	return(klgraph_addr[cnodeid]);
 
-#endif /* _ASM_IA64_SN_SN1_SAL_H */
+}
+#endif /* _ASM_IA64_SN_SN_SAL_H */
diff -Nru a/include/asm-ia64/sn/snconfig.h b/include/asm-ia64/sn/snconfig.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/snconfig.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,18 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_IA64_SN_SNCONFIG_H
+#define _ASM_IA64_SN_SNCONFIG_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_IA64_SGI_SN1)
+#include <asm/sn/sn1/ip27config.h>
+#elif defined(CONFIG_IA64_SGI_SN2)
+#endif
+
+#endif /* _ASM_IA64_SN_SNCONFIG_H */
diff -Nru a/include/asm-ia64/sn/sndrv.h b/include/asm-ia64/sn/sndrv.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/sndrv.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,39 @@
+#ifndef _ASM_IA64_SN_SNDRV_H
+#define _ASM_IA64_SN_SNDRV_H
+
+/* ioctl commands */
+#define SNDRV_GET_ROUTERINFO		1
+#define SNDRV_GET_INFOSIZE		2
+#define SNDRV_GET_HUBINFO		3
+#define SNDRV_GET_FLASHLOGSIZE		4
+#define SNDRV_SET_FLASHSYNC		5
+#define SNDRV_GET_FLASHLOGDATA		6
+#define SNDRV_GET_FLASHLOGALL		7
+
+#define SNDRV_SET_HISTOGRAM_TYPE	14
+
+#define SNDRV_ELSC_COMMAND		19
+#define	SNDRV_CLEAR_LOG			20
+#define	SNDRV_INIT_LOG			21
+#define	SNDRV_GET_PIMM_PSC		22
+#define SNDRV_SET_PARTITION		23
+#define SNDRV_GET_PARTITION		24
+
+/* see synergy_perf_ioctl() */
+#define SNDRV_GET_SYNERGY_VERSION	30
+#define SNDRV_GET_SYNERGY_STATUS	31
+#define SNDRV_GET_SYNERGYINFO		32
+#define SNDRV_SYNERGY_APPEND		33
+#define SNDRV_SYNERGY_ENABLE		34
+#define SNDRV_SYNERGY_FREQ		35
+
+/* Devices */
+#define SNDRV_UKNOWN_DEVICE		-1
+#define SNDRV_ROUTER_DEVICE		1
+#define SNDRV_HUB_DEVICE		2
+#define SNDRV_ELSC_NVRAM_DEVICE		3
+#define SNDRV_ELSC_CONTROLLER_DEVICE	4
+#define SNDRV_SYSCTL_SUBCH		5
+#define SNDRV_SYNERGY_DEVICE		6
+
+#endif /* _ASM_IA64_SN_SNDRV_H */
diff -Nru a/include/asm-ia64/sn/sv.h b/include/asm-ia64/sn/sv.h
--- a/include/asm-ia64/sn/sv.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/sv.h	Fri Mar 15 17:51:02 2002
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2000 Silicon Graphics, Inc.  All rights reserved
+ * Copyright (C) 2000-2001 Silicon Graphics, Inc.  All rights reserved
  *
  * This implemenation of synchronization variables is heavily based on
  * one done by Steve Lord <lord@sgi.com>
@@ -11,8 +11,8 @@
  * Paul Cassella <pwc@sgi.com>
  */
 
-#ifndef SV_H
-#define SV_H
+#ifndef _ASM_IA64_SN_SV_H
+#define _ASM_IA64_SN_SV_H
 
 #include <linux/spinlock.h>
 #include <asm/semaphore.h>
@@ -150,4 +150,4 @@
 #undef _SV_ASSERT
 #endif
 
-#endif
+#endif /* _ASM_IA64_SN_SV_H */
diff -Nru a/include/asm-ia64/sn/synergy.h b/include/asm-ia64/sn/synergy.h
--- a/include/asm-ia64/sn/synergy.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,168 +0,0 @@
-#ifndef ASM_IA64_SN_SYNERGY_H
-#define ASM_IA64_SN_SYNERGY_H
-
-#include <linux/config.h>
-
-#include "asm/io.h"
-#include "asm/sn/nodepda.h"
-#include "asm/sn/intr_public.h"
-
-
-/*
- * Definitions for the synergy asic driver
- * 
- * These are for SGI platforms only.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc
- * Copyright (C) 2000 Alan Mayer (ajm@sgi.com)
- */
-
-
-#define SSPEC_BASE	(0xe0000000000)
-#define LB_REG_BASE	(SSPEC_BASE + 0x0)
-
-#define VEC_MASK3A_ADDR	(0x2a0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK3B_ADDR	(0x2a8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK3A	(0x2a0)
-#define VEC_MASK3B	(0x2a8)
-
-#define VEC_MASK2A_ADDR	(0x2b0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK2B_ADDR	(0x2b8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK2A	(0x2b0)
-#define VEC_MASK2B	(0x2b8)
-
-#define VEC_MASK1A_ADDR	(0x2c0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK1B_ADDR	(0x2c8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK1A	(0x2c0)
-#define VEC_MASK1B	(0x2c8)
-
-#define VEC_MASK0A_ADDR	(0x2d0 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK0B_ADDR	(0x2d8 + LB_REG_BASE + __IA64_UNCACHED_OFFSET)
-#define VEC_MASK0A	(0x2d0)
-#define VEC_MASK0B	(0x2d8)
-
-#define WRITE_LOCAL_SYNERGY_REG(addr, value)	__synergy_out(addr, value)
-
-#define HUBREG_CAST             (volatile hubreg_t *)
-#define HUB_L(_a)               *(_a)
-#define HUB_S(_a, _d)           *(_a) = (_d)
-
-#define HSPEC_SYNERGY0_0        0x04000000    /* Synergy0 Registers     */
-#define HSPEC_SYNERGY1_0        0x05000000    /* Synergy1 Registers     */
-#define HS_SYNERGY_STRIDE       (HSPEC_SYNERGY1_0 - HSPEC_SYNERGY0_0)
-#define REMOTE_HSPEC(_n, _x)    (HUBREG_CAST (RREG_BASE(_n) + (_x)))
-
-#define RREG_BASE(_n)           (NODE_LREG_BASE(_n))
-#define NODE_LREG_BASE(_n)      (NODE_HSPEC_BASE(_n) + 0x30000000)
-#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
-#ifndef HSPEC_BASE
-#define HSPEC_BASE              (SYN_UNCACHED_SPACE | HSPEC_BASE_SYN)
-#endif
-#define SYN_UNCACHED_SPACE      0xc000000000000000
-#define HSPEC_BASE_SYN          0x00000b0000000000
-#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
-#define NODE_SIZE_BITS		33
-
-
-#define RSYN_REG_OFFSET(fsb, reg) (((fsb) ? HSPEC_SYNERGY1_0 : HSPEC_SYNERGY0_0) | (reg))
-
-#define REMOTE_SYNERGY_LOAD(nasid, fsb, reg)  __remote_synergy_in(nasid, fsb, reg)
-#define REMOTE_SYNERGY_STORE(nasid, fsb, reg, val) __remote_synergy_out(nasid, fsb, reg, val)
-
-extern inline uint64_t
-__remote_synergy_in(int nasid, int fsb, uint64_t reg) {
-	volatile uint64_t *addr;
-
-	addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, reg));
-	return (*addr);
-}
-
-extern inline void
-__remote_synergy_out(int nasid, int fsb, uint64_t reg, uint64_t value) {
-	volatile uint64_t *addr;
-
-        addr = (uint64_t *)(RREG_BASE(nasid) + RSYN_REG_OFFSET(fsb, (reg<<2)));
-        *(addr+0) = value >> 48;
-        *(addr+1) = value >> 32;
-        *(addr+2) = value >> 16;
-        *(addr+3) = value;
-        __ia64_mf_a();
-}
-
-/* XX this doesn't make a lot of sense. Which fsb?  */
-extern inline void
-__synergy_out(unsigned long addr, unsigned long value)
-{
-	volatile unsigned long *adr = (unsigned long *)
-			(addr | __IA64_UNCACHED_OFFSET);
-
-	*adr = value;
-	__ia64_mf_a();
-}
-
-#define READ_LOCAL_SYNERGY_REG(addr)	__synergy_in(addr)
-
-/* XX this doesn't make a lot of sense. Which fsb? */
-extern inline unsigned long
-__synergy_in(unsigned long addr)
-{
-	unsigned long ret, *adr = (unsigned long *)
-			(addr | __IA64_UNCACHED_OFFSET);
-
-	ret = *adr;
-	__ia64_mf_a();
-	return ret;
-}
-
-struct sn1_intr_action {
-	void (*handler)(int, void *, struct pt_regs *);
-	void *intr_arg;
-	unsigned long flags;
-	struct sn1_intr_action * next;
-};
-
-typedef struct synergy_da_s {
-	hub_intmasks_t	s_intmasks;
-}synergy_da_t;
-
-struct sn1_cnode_action_list {
-	spinlock_t action_list_lock;
-	struct sn1_intr_action *action_list;
-};
-
-#if defined(CONFIG_IA64_SGI_SYNERGY_PERF)
-
-/* multiplex the counters every 10 timer interrupts */ 
-#define SYNERGY_PERF_FREQ_DEFAULT 10
-
-/* synergy perf control registers */
-#define PERF_CNTL0_A            0xab0UL /* control A on FSB0 */
-#define PERF_CNTL0_B            0xab8UL /* control B on FSB0 */
-#define PERF_CNTL1_A            0xac0UL /* control A on FSB1 */
-#define PERF_CNTL1_B            0xac8UL /* control B on FSB1 */
-
-/* synergy perf counters */
-#define PERF_CNTR0_A            0xad0UL /* counter A on FSB0 */
-#define PERF_CNTR0_B            0xad8UL /* counter B on FSB0 */
-#define PERF_CNTR1_A            0xaf0UL /* counter A on FSB1 */
-#define PERF_CNTR1_B            0xaf8UL /* counter B on FSB1 */
-
-/* Synergy perf data. Each nodepda keeps a list of these */
-struct synergy_perf_s {
-        uint64_t        intervals;      /* count of active intervals for this event */
-        uint64_t        modesel;        /* mode and sel bits, both A and B registers */
-        struct synergy_perf_s *next;	/* next in circular linked list */
-        uint64_t        counts[2];      /* [0] is synergy-A counter, [1] synergy-B counter */
-};
-
-typedef struct synergy_perf_s synergy_perf_t;
-
-extern void synergy_perf_init(void);
-extern void synergy_perf_update(int);
-
-#endif /* CONFIG_IA64_SGI_SYNERGY_PERF */
-
-
-/* Temporary defintions for testing: */
-
-#endif ASM_IA64_SN_SYNERGY_H
diff -Nru a/include/asm-ia64/sn/systeminfo.h b/include/asm-ia64/sn/systeminfo.h
--- a/include/asm-ia64/sn/systeminfo.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/systeminfo.h	Fri Mar 15 17:51:03 2002
@@ -4,11 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_SYSTEMINFO_H
-#define _ASM_SN_SYSTEMINFO_H
+#ifndef _ASM_IA64_SN_SYSTEMINFO_H
+#define _ASM_IA64_SN_SYSTEMINFO_H
+
+#include <linux/types.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -69,4 +70,4 @@
 }
 #endif
 
-#endif /* _ASM_SN_SYSTEMINFO_H */
+#endif /* _ASM_IA64_SN_SYSTEMINFO_H */
diff -Nru a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h
--- a/include/asm-ia64/sn/types.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/types.h	Fri Mar 15 17:51:02 2002
@@ -3,30 +3,27 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 1999,2001-2002 Silicon Graphics, Inc.  All Rights Reserved.
  * Copyright (C) 1999 by Ralf Baechle
  */
-#ifndef _ASM_SN_TYPES_H
-#define _ASM_SN_TYPES_H
+#ifndef _ASM_IA64_SN_TYPES_H
+#define _ASM_IA64_SN_TYPES_H
 
 #include <linux/types.h>
 
 typedef unsigned long 	cpuid_t;
 typedef unsigned long 	cpumask_t;
-/* typedef unsigned long	cnodemask_t; */
 typedef signed short	nasid_t;	/* node id in numa-as-id space */
-typedef signed short	cnodeid_t;	/* node id in compact-id space */
 typedef signed char	partid_t;	/* partition ID type */
 typedef signed short	moduleid_t;	/* user-visible module number type */
 typedef signed short	cmoduleid_t;	/* kernel compact module id type */
 typedef unsigned char	clusterid_t;	/* Clusterid of the cell */
 
-#define __psunsigned_t uint64_t
-#define lock_t uint64_t
+typedef uint64_t __psunsigned_t;
 
 typedef unsigned long iopaddr_t;
 typedef unsigned char uchar_t;
 typedef unsigned long paddr_t;
 typedef unsigned long pfn_t;
 
-#endif /* _ASM_SN_TYPES_H */
+#endif /* _ASM_IA64_SN_TYPES_H */
diff -Nru a/include/asm-ia64/sn/uart16550.h b/include/asm-ia64/sn/uart16550.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/sn/uart16550.h	Fri Mar 15 17:51:02 2002
@@ -0,0 +1,227 @@
+/*
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc. All rights reserved.
+ */
+
+#ifndef _ASM_IA64_SN_UART16550_H
+#define _ASM_IA64_SN_UART16550_H
+
+
+/*
+ * Definitions for 16550  chip
+ */
+
+	/* defined as offsets from the data register */
+#define REG_DAT     0   /* receive/transmit data */
+#define REG_ICR     1   /* interrupt control register */
+#define REG_ISR     2   /* interrupt status register */
+#define REG_FCR     2   /* fifo control register */
+#define REG_LCR     3   /* line control register */
+#define REG_MCR     4   /* modem control register */
+#define REG_LSR     5   /* line status register */
+#define REG_MSR     6   /* modem status register */
+#define REG_SCR     7   /* Scratch register      */
+#define REG_DLL     0   /* divisor latch (lsb) */
+#define REG_DLH     1   /* divisor latch (msb) */
+#define REG_EFR		2	/* 16650 enhanced feature register */
+
+/*
+ * 16450/16550 Registers Structure.
+ */
+
+/* Line Control Register */
+#define		LCR_WLS0	0x01	/*word length select bit 0 */	
+#define		LCR_WLS1	0x02	/*word length select bit 2 */	
+#define		LCR_STB	0x04		/* number of stop bits */
+#define		LCR_PEN	0x08		/* parity enable */
+#define		LCR_EPS	0x10		/* even parity select */
+#define		LCR_SETBREAK 0x40	/* break key */
+#define		LCR_DLAB	0x80	/* divisor latch access bit */
+#define 	LCR_RXLEN   0x03    /* # of data bits per received/xmitted char */
+#define 	LCR_STOP1   0x00
+#define 	LCR_STOP2   0x04
+#define 	LCR_PAREN   0x08
+#define 	LCR_PAREVN  0x10
+#define 	LCR_PARMARK 0x20
+#define 	LCR_SNDBRK  0x40
+#define 	LCR_DLAB    0x80
+
+
+#define		LCR_BITS5	0x00	/* 5 bits per char */
+#define		LCR_BITS6	0x01	/* 6 bits per char */
+#define		LCR_BITS7	0x02	/* 7 bits per char */
+#define		LCR_BITS8	0x03	/* 8 bits per char */
+
+#define		LCR_MASK_BITS_CHAR 		0x03
+#define 	LCR_MASK_STOP_BITS		0x04
+#define		LCR_MASK_PARITY_BITS	0x18
+
+
+/* Line Status Register */
+#define		LSR_RCA	0x01		/* data ready */
+#define		LSR_OVRRUN	0x02	/* overrun error */
+#define		LSR_PARERR	0x04	/* parity error */
+#define		LSR_FRMERR	0x08	/* framing error */
+#define		LSR_BRKDET 	0x10	/* a break has arrived */
+#define		LSR_XHRE	0x20	/* tx hold reg is now empty */
+#define		LSR_XSRE	0x40	/* tx shift reg is now empty */
+#define		LSR_RFBE	0x80	/* rx FIFO Buffer error */
+
+/* Interrupt Status Regisger */
+#define		ISR_MSTATUS	0x00
+#define		ISR_TxRDY	0x02
+#define		ISR_RxRDY	0x04
+#define		ISR_ERROR_INTR	0x08
+#define		ISR_FFTMOUT 0x0c	/* FIFO Timeout */
+#define		ISR_RSTATUS 0x06	/* Receiver Line status */
+
+/* Interrupt Enable Register */
+#define		ICR_RIEN	0x01	/* Received Data Ready */
+#define		ICR_TIEN	0x02	/* Tx Hold Register Empty */
+#define		ICR_SIEN	0x04	/* Receiver Line Status */
+#define		ICR_MIEN	0x08	/* Modem Status */
+
+/* Modem Control Register */
+#define		MCR_DTR		0x01	/* Data Terminal Ready */
+#define		MCR_RTS		0x02	/* Request To Send */
+#define		MCR_OUT1	0x04	/* Aux output - not used */
+#define		MCR_OUT2	0x08	/* turns intr to 386 on/off */	
+#define		MCR_LOOP	0x10	/* loopback for diagnostics */
+#define		MCR_AFE 	0x20	/* Auto flow control enable */
+
+/* Modem Status Register */
+#define		MSR_DCTS	0x01	/* Delta Clear To Send */
+#define		MSR_DDSR	0x02	/* Delta Data Set Ready */
+#define		MSR_DRI		0x04	/* Trail Edge Ring Indicator */
+#define		MSR_DDCD	0x08	/* Delta Data Carrier Detect */
+#define		MSR_CTS		0x10	/* Clear To Send */
+#define		MSR_DSR		0x20	/* Data Set Ready */
+#define		MSR_RI		0x40	/* Ring Indicator */
+#define		MSR_DCD		0x80	/* Data Carrier Detect */
+
+#define 	DELTAS(x) 	((x)&(MSR_DCTS|MSR_DDSR|MSR_DRI|MSR_DDCD))
+#define 	STATES(x) 	((x)(MSR_CTS|MSR_DSR|MSR_RI|MSR_DCD))
+
+
+#define		FCR_FIFOEN	0x01	/* enable receive/transmit fifo */
+#define		FCR_RxFIFO	0x02	/* enable receive fifo */
+#define		FCR_TxFIFO	0x04	/* enable transmit fifo */
+#define 	FCR_MODE1	0x08	/* change to mode 1 */
+#define		RxLVL0		0x00	/* Rx fifo level at 1	*/
+#define		RxLVL1		0x40	/* Rx fifo level at 4 */
+#define		RxLVL2		0x80	/* Rx fifo level at 8 */
+#define		RxLVL3		0xc0	/* Rx fifo level at 14 */
+
+#define 	FIFOEN		(FCR_FIFOEN | FCR_RxFIFO | FCR_TxFIFO | RxLVL3 | FCR_MODE1) 
+
+#define		FCT_TxMASK	0x30	/* mask for Tx trigger */
+#define		FCT_RxMASK	0xc0	/* mask for Rx trigger */
+
+/* enhanced festures register */
+#define		EFR_SFLOW	0x0f	/* various S/w Flow Controls */
+#define 	EFR_EIC		0x10	/* Enhanced Interrupt Control bit */
+#define 	EFR_SCD		0x20	/* Special Character Detect */
+#define 	EFR_RTS		0x40	/* RTS flow control */
+#define 	EFR_CTS		0x80	/* CTS flow control */
+
+/* Rx Tx software flow controls in 16650 enhanced mode */
+#define		SFLOW_Tx0	0x00	/* no Xmit flow control */
+#define		SFLOW_Tx1	0x08	/* Transmit Xon1, Xoff1 */
+#define		SFLOW_Tx2	0x04	/* Transmit Xon2, Xoff2 */
+#define		SFLOW_Tx3	0x0c	/* Transmit Xon1,Xon2, Xoff1,Xoff2 */
+#define		SFLOW_Rx0	0x00	/* no Rcv flow control */
+#define		SFLOW_Rx1	0x02	/* Receiver compares Xon1, Xoff1 */
+#define		SFLOW_Rx2	0x01	/* Receiver compares Xon2, Xoff2 */
+
+#define	ASSERT_DTR(x)		(x |= MCR_DTR)
+#define	ASSERT_RTS(x)		(x |= MCR_RTS)
+#define DU_RTS_ASSERTED(x)  (((x) & MCR_RTS) != 0)
+#define DU_RTS_ASSERT(x)    ((x) |= MCR_RTS)
+#define DU_RTS_DEASSERT(x)  ((x) &= ~MCR_RTS)
+
+
+/*
+ * ioctl(fd, I_STR, arg)
+ * use the SIOC_RS422 and SIOC_EXTCLK combination to support MIDI
+ */
+#define SIOC        ('z' << 8)  /* z for z85130 */
+#define SIOC_EXTCLK (SIOC | 1)  /* select/de-select external clock */
+#define SIOC_RS422  (SIOC | 2)  /* select/de-select RS422 protocol */
+#define SIOC_ITIMER (SIOC | 3)  /* upstream timer adjustment */
+#define SIOC_LOOPBACK   (SIOC | 4)  /* diagnostic loopback test mode */
+
+
+/* channel control register */
+#define	DMA_INT_MASK		0xe0	/* ring intr mask */
+#define DMA_INT_TH25		0x20	/* 25% threshold */
+#define DMA_INT_TH50		0x40	/* 50% threshold */
+#define DMA_INT_TH75		0x60	/* 75% threshold */
+#define DMA_INT_EMPTY		0x80	/* ring buffer empty */
+#define DMA_INT_NEMPTY		0xa0	/* ring buffer not empty */
+#define DMA_INT_FULL		0xc0	/* ring buffer full */
+#define DMA_INT_NFULL		0xe0	/* ring buffer not full */
+
+#define DMA_CHANNEL_RESET	0x400	/* reset dma channel */
+#define DMA_ENABLE			0x200	/* enable DMA */
+
+/* peripheral controller intr status bits applicable to serial ports */
+#define ISA_SERIAL0_MASK 		0x03f00000	/* mask for port #1 intrs */
+#define ISA_SERIAL0_DIR			0x00100000	/* device intr request */
+#define ISA_SERIAL0_Tx_THIR		0x00200000	/* Transmit DMA threshold */
+#define ISA_SERIAL0_Tx_PREQ		0x00400000	/* Transmit DMA pair req */
+#define ISA_SERIAL0_Tx_MEMERR	0x00800000	/* Transmit DMA memory err */
+#define ISA_SERIAL0_Rx_THIR		0x01000000	/* Receive DMA threshold  */
+#define ISA_SERIAL0_Rx_OVERRUN	0x02000000	/* Receive DMA over-run  */
+
+#define ISA_SERIAL1_MASK 		0xfc000000	/* mask for port #1 intrs */
+#define ISA_SERIAL1_DIR			0x04000000	/* device intr request */
+#define ISA_SERIAL1_Tx_THIR		0x08000000	/* Transmit DMA threshold */
+#define ISA_SERIAL1_Tx_PREQ		0x10000000	/* Transmit DMA pair req */
+#define ISA_SERIAL1_Tx_MEMERR	0x20000000	/* Transmit DMA memory err */
+#define ISA_SERIAL1_Rx_THIR		0x40000000	/* Receive DMA threshold  */
+#define ISA_SERIAL1_Rx_OVERRUN	0x80000000	/* Receive DMA over-run  */
+
+#define MAX_RING_BLOCKS		128			/* 4096/32 */
+#define MAX_RING_SIZE		4096
+
+/* DMA Input Control Byte */
+#define	DMA_IC_OVRRUN	0x01	/* overrun error */
+#define	DMA_IC_PARERR	0x02	/* parity error */
+#define	DMA_IC_FRMERR	0x04	/* framing error */
+#define	DMA_IC_BRKDET 	0x08	/* a break has arrived */
+#define DMA_IC_VALID	0x80	/* pair is valid */
+
+/* DMA Output Control Byte */
+#define DMA_OC_TxINTR	0x20	/* set Tx intr after processing byte */
+#define DMA_OC_INVALID	0x00	/* invalid pair */
+#define DMA_OC_WTHR		0x40	/* Write byte to THR */
+#define DMA_OC_WMCR		0x80	/* Write byte to MCR */
+#define DMA_OC_DELAY	0xc0	/* time delay before next xmit */
+
+/* ring id's */
+#define RID_SERIAL0_TX	0x4		/* serial port 0, transmit ring buffer */
+#define RID_SERIAL0_RX	0x5		/* serial port 0, receive ring buffer */
+#define RID_SERIAL1_TX	0x6		/* serial port 1, transmit ring buffer */
+#define RID_SERIAL1_RX	0x7		/* serial port 1, receive ring buffer */
+
+#define CLOCK_XIN			22
+#define PRESCALER_DIVISOR	3
+#define CLOCK_ACE			7333333
+
+/*
+ * increment the ring offset. One way to do this would be to add b'100000.
+ * this would let the offset value roll over automatically when it reaches
+ * its maximum value (127). However when we use the offset, we must use
+ * the appropriate bits only by masking with 0xfe0.
+ * The other option is to shift the offset right by 5 bits and look at its
+ * value. Then increment if required and shift back
+ * note: 127 * 2^5 = 4064
+ */
+#define INC_RING_POINTER(x) \
+	( ((x & 0xffe0) < 4064) ? (x += 32) : 0 )
+
+#endif /* _ASM_IA64_SN_UART16550_H */
diff -Nru a/include/asm-ia64/sn/vector.h b/include/asm-ia64/sn/vector.h
--- a/include/asm-ia64/sn/vector.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/vector.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,10 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992 - 1997, 2000-2002 Silicon Graphics, Inc. All rights reserved.
  */
-#ifndef _ASM_SN_VECTOR_H
-#define _ASM_SN_VECTOR_H
+#ifndef _ASM_IA64_SN_VECTOR_H
+#define _ASM_IA64_SN_VECTOR_H
 
 #include <linux/config.h>
 
@@ -37,7 +36,7 @@
 
 #endif /* RTL */
 
-#if defined(CONFIG_SGI_IP35) || defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
+#if defined(CONFIG_IA64_SGI_SN1) || defined(CONFIG_IA64_GENERIC)
 #define VECTOR_PARMS		LB_VECTOR_PARMS
 #define VECTOR_ROUTE		LB_VECTOR_ROUTE
 #define VECTOR_DATA		LB_VECTOR_DATA
@@ -66,19 +65,22 @@
 #define VS_ERROR_MASK		LVS_ERROR_MASK
 #endif
 
-#define NET_ERROR_NONE          0       /* No error             */
-#define NET_ERROR_HARDWARE     -1       /* Hardware error       */
-#define NET_ERROR_OVERRUN      -2       /* Extra response(s)    */
-#define NET_ERROR_REPLY        -3       /* Reply parms mismatch */
-#define NET_ERROR_ADDRESS      -4       /* Addr error response  */
-#define NET_ERROR_COMMAND      -5       /* Cmd error response   */
-#define NET_ERROR_PROT         -6       /* Prot error response  */
-#define NET_ERROR_TIMEOUT      -7       /* Too many retries     */
-#define NET_ERROR_VECTOR       -8       /* Invalid vector/path  */
-#define NET_ERROR_ROUTERLOCK   -9       /* Timeout locking rtr  */
-#define NET_ERROR_INVAL	       -10	/* Invalid vector request */
+#define NET_ERROR_NONE		0	/* No error		*/
+#define NET_ERROR_HARDWARE	(-1)	/* Hardware error	*/
+#define NET_ERROR_OVERRUN	(-2)	/* Extra response(s)	*/
+#define NET_ERROR_REPLY		(-3)	/* Reply parms mismatch */
+#define NET_ERROR_ADDRESS	(-4)	/* Addr error response	*/
+#define NET_ERROR_COMMAND	(-5)	/* Cmd error response	*/
+#define NET_ERROR_PROT		(-6)	/* Prot error response	*/
+#define NET_ERROR_TIMEOUT	(-7)	/* Too many retries	*/
+#define NET_ERROR_VECTOR	(-8)	/* Invalid vector/path	*/
+#define NET_ERROR_ROUTERLOCK	(-9)	/* Timeout locking rtr	*/
+#define NET_ERROR_INVAL		(-10)	/* Invalid vector request */
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#include <asm/sn/types.h>
 
-#if defined(_LANGUAGE_C) || defined(_LANGUAGE_C_PLUS_PLUS)
 typedef uint64_t              net_reg_t;
 typedef uint64_t              net_vec_t;
 
@@ -114,6 +116,6 @@
 	int addr, net_reg_t *value);
 #endif
 
-#endif /* _LANGUAGE_C || _LANGUAGE_C_PLUS_PLUS */
+#endif /* __ASSEMBLY__ */
 
-#endif /* _ASM_SN_VECTOR_H */
+#endif /* _ASM_IA64_SN_VECTOR_H */
diff -Nru a/include/asm-ia64/sn/xtalk/xbow.h b/include/asm-ia64/sn/xtalk/xbow.h
--- a/include/asm-ia64/sn/xtalk/xbow.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/xtalk/xbow.h	Fri Mar 15 17:51:02 2002
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_SN_XTALK_XBOW_H
@@ -17,7 +17,7 @@
 #include <asm/sn/xtalk/xtalk.h>
 #include <asm/sn/xtalk/xwidget.h>
 #include <asm/sn/xtalk/xswitch.h>
-#ifdef LANGUAGE_C
+#ifndef __ASSEMBLY__
 #include <asm/sn/xtalk/xbow_info.h>
 #endif
 
@@ -46,7 +46,7 @@
 
 #define MAX_XBOW_NAME 	16
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 typedef uint32_t      xbowreg_t;
 
 #define XBOWCONST	(xbowreg_t)
@@ -236,7 +236,7 @@
 /* offset of arbitration register, given source widget id */
 #define XBOW_ARB_OFF(wid) 	(XBOW_ARB_IS_UPPER(wid) ? 0x1c : 0x24)
 
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #define	XBOW_WID_ID		WIDGET_ID
 #define	XBOW_WID_STAT		WIDGET_STATUS
@@ -402,7 +402,7 @@
 	(XWIDGET_PART_NUM(XWIDGET_ID_READ(nasid, 0)) == XXBOW_WIDGET_PART_NUM)
 
 
-#ifdef _LANGUAGE_C
+#ifndef __ASSEMBLY__
 /*
  * XBOW Widget 0 Register formats.
  * Format for many of these registers are similar to the standard
@@ -891,5 +891,5 @@
 
 #endif				/* MACROFIELD_LINE */
 
-#endif				/* _LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 #endif                          /* _ASM_SN_SN_XTALK_XBOW_H */
diff -Nru a/include/asm-ia64/sn/xtalk/xbow_info.h b/include/asm-ia64/sn/xtalk/xbow_info.h
--- a/include/asm-ia64/sn/xtalk/xbow_info.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/xtalk/xbow_info.h	Fri Mar 15 17:51:01 2002
@@ -4,11 +4,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 #ifndef _ASM_SN_XTALK_XBOW_INFO_H
 #define _ASM_SN_XTALK_XBOW_INFO_H
+
+#include <linux/types.h>
+#include <linux/devfs_fs_kernel.h>
 
 #define XBOW_PERF_MODES	       0x03
 #define XBOW_PERF_COUNTERS     0x02
diff -Nru a/include/asm-ia64/sn/xtalk/xswitch.h b/include/asm-ia64/sn/xtalk/xswitch.h
--- a/include/asm-ia64/sn/xtalk/xswitch.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/xtalk/xswitch.h	Fri Mar 15 17:51:03 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997,2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 #ifndef _ASM_SN_XTALK_XSWITCH_H
 #define _ASM_SN_XTALK_XSWITCH_H
@@ -16,7 +15,10 @@
  * xtalk bus providers.
  */
 
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
+
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/xtalk/xtalk.h>
 
 typedef struct xswitch_info_s *xswitch_info_t;
 
@@ -54,6 +56,6 @@
 extern int		xswitch_id_get(devfs_handle_t vhdl);
 extern void		xswitch_id_set(devfs_handle_t vhdl,int xbow_num);
 
-#endif				/* LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #endif				/* _ASM_SN_XTALK_XSWITCH_H */
diff -Nru a/include/asm-ia64/sn/xtalk/xtalk.h b/include/asm-ia64/sn/xtalk/xtalk.h
--- a/include/asm-ia64/sn/xtalk/xtalk.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/sn/xtalk/xtalk.h	Fri Mar 15 17:51:01 2002
@@ -4,8 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 #ifndef _ASM_SN_XTALK_XTALK_H
 #define _ASM_SN_XTALK_XTALK_H
@@ -18,19 +17,19 @@
  */
 typedef char            xwidgetnum_t;	/* xtalk widget number  (0..15) */
 
-#define XWIDGET_NONE		-1
+#define XWIDGET_NONE		(-1)
 
 typedef int xwidget_part_num_t;	/* xtalk widget part number */
 
-#define XWIDGET_PART_NUM_NONE	-1
+#define XWIDGET_PART_NUM_NONE	(-1)
 
 typedef int             xwidget_rev_num_t;	/* xtalk widget revision number */
 
-#define XWIDGET_REV_NUM_NONE	-1
+#define XWIDGET_REV_NUM_NONE	(-1)
 
 typedef int xwidget_mfg_num_t;	/* xtalk widget manufacturing ID */
 
-#define XWIDGET_MFG_NUM_NONE	-1
+#define XWIDGET_MFG_NUM_NONE	(-1)
 
 typedef struct xtalk_piomap_s *xtalk_piomap_t;
 
@@ -57,7 +56,7 @@
 #include <asm/sn/types.h>
 #include <asm/sn/alenlist.h>
 #include <asm/sn/ioerror.h>
-#include <asm/sn/iobus.h>
+#include <asm/sn/driver.h>
 #include <asm/sn/dmamap.h>
 
 struct xwidget_hwid_s;
@@ -205,14 +204,8 @@
 
 typedef int
 xtalk_intr_connect_f    (xtalk_intr_t intr_hdl,		/* xtalk intr resource handle */
-			 intr_func_t intr_func,		/* xtalk intr handler */
-			 void *intr_arg,	/* arg to intr handler */
 			 xtalk_intr_setfunc_f *setfunc,		/* func to set intr hw */
-			 void *setfunc_arg,	/* arg to setfunc. This must be */
-							/* sufficient to determine which */
-							/* interrupt on which board needs */
-							/* to be set. */
-			 void *thread);		/* which intr thread to use */
+			 void *setfunc_arg);	/* arg to setfunc */
 
 typedef void
 xtalk_intr_disconnect_f (xtalk_intr_t intr_hdl);
@@ -400,7 +393,6 @@
 
 extern int		xtalk_device_powerup(devfs_handle_t, xwidgetnum_t);
 extern int		xtalk_device_shutdown(devfs_handle_t, xwidgetnum_t);
-extern int		xtalk_device_inquiry(devfs_handle_t, xwidgetnum_t);
 
 #endif				/* __KERNEL__ */
 #endif				/* _ASM_SN_XTALK_XTALK_H */
diff -Nru a/include/asm-ia64/sn/xtalk/xtalk_private.h b/include/asm-ia64/sn/xtalk/xtalk_private.h
--- a/include/asm-ia64/sn/xtalk/xtalk_private.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/sn/xtalk/xtalk_private.h	Fri Mar 15 17:51:03 2002
@@ -4,13 +4,15 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
+ * Copyright (C) 1992-1997, 2000-2002 Silicon Graphics, Inc.  All Rights Reserved.
  */
 #ifndef _ASM_SN_XTALK_XTALK_PRIVATE_H
 #define _ASM_SN_XTALK_XTALK_PRIVATE_H
 
 #include <asm/sn/ioerror.h>        /* for error function and arg types */
+#include <linux/devfs_fs_kernel.h>
+#include <asm/sn/xtalk/xwidget.h>
+#include <asm/sn/xtalk/xtalk.h>
 
 /*
  * xtalk_private.h -- private definitions for xtalk
diff -Nru a/include/asm-ia64/sn/xtalk/xtalkaddrs.h b/include/asm-ia64/sn/xtalk/xtalkaddrs.h
--- a/include/asm-ia64/sn/xtalk/xtalkaddrs.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/sn/xtalk/xtalkaddrs.h	Fri Mar 15 17:51:02 2002
@@ -4,13 +4,12 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef _ASM_SN_XTALK_XTALKADDRS_H
 #define _ASM_SN_XTALK_XTALKADDRS_H
 
-#include <linux/config.h>
 
 /*
  * CrossTalk to SN0 Hub addressing support
@@ -60,19 +59,15 @@
  * This looks very much like a REMOTE_HUB access, except the nodeID
  * is in a different place, and the highest xtalk bit is set.
  */
-
 /* Hub-specific xtalk definitions */
 
 #define HX_MEM_BIT		0L	/* Hub's idea of xtalk memory access */
 #define HX_IO_BIT		1L	/* Hub's idea of xtalk register access */
 #define HX_ACCTYPE_SHIFT	47
 
-#if CONFIG_SGI_IP35 || CONFIG_IA64_SGI_SN1 || CONFIG_IA64_GENERIC
 #define HX_NODE_SHIFT		39
-#endif
 
 #define HX_BIGWIN_SHIFT		28
-
 #define HX_SWIN_SHIFT		23
 
 #define HX_LOCACC		0L	/* local access */
diff -Nru a/include/asm-ia64/sn/xtalk/xwidget.h b/include/asm-ia64/sn/xtalk/xwidget.h
--- a/include/asm-ia64/sn/xtalk/xwidget.h	Fri Mar 15 17:51:00 2002
+++ b/include/asm-ia64/sn/xtalk/xwidget.h	Fri Mar 15 17:51:00 2002
@@ -4,7 +4,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
+ * Copyright (C) 1992 - 1997, 2000-2001 Silicon Graphics, Inc.
  * Copyright (C) 2000 by Colin Ngam
  */
 #ifndef __ASM_SN_XTALK_XWIDGET_H__
@@ -15,9 +15,9 @@
  */
 
 #include <asm/sn/xtalk/xtalk.h>
-#if LANGUAGE_C
+#ifndef __ASSEMBLY__
 #include <asm/sn/cdl.h>
-#endif /* LANGUAGE_C */
+#endif /* __ASSEMBLY__ */
 
 #ifdef LITTLE_ENDIAN
 #define WIDGET_ID			0x00
@@ -115,7 +115,7 @@
  * widget target flush register are widget dependent thus will not be
  * defined here
  */
-#if _LANGUAGE_C
+#ifndef __ASSEMBLY__
 typedef uint32_t      widgetreg_t;
 
 /* widget configuration registers */
@@ -267,9 +267,6 @@
 					 async_attach_t aa);
 
 extern int		xwidget_unregister(devfs_handle_t);
-extern void	        xwidget_error_register(devfs_handle_t xwidget,
-						error_handler_f * efunc,
-						error_handler_arg_t einfo);
 
 extern void             xwidget_reset(devfs_handle_t xwidget);
 extern void             xwidget_gfx_reset(devfs_handle_t xwidget);
@@ -289,6 +286,9 @@
 extern xwidget_rev_num_t xwidget_info_rev_num_get(xwidget_info_t xwidget_info);
 extern xwidget_mfg_num_t xwidget_info_mfg_num_get(xwidget_info_t xwidget_info);
 
+extern xwidgetnum_t hub_widget_id(nasid_t);
+
+
 
 /*
  * TBD: DELETE THIS ENTIRE STRUCTURE!  Equivalent is now in
@@ -303,6 +303,6 @@
 } v_widget_t;
 #endif				/* _KERNEL */
 
-#endif				/* _LANGUAGE_C */
+#endif				/* __ASSEMBLY__ */
 
 #endif				/* __ASM_SN_XTALK_XWIDGET_H__ */
diff -Nru a/include/asm-ia64/softirq.h b/include/asm-ia64/softirq.h
--- a/include/asm-ia64/softirq.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/softirq.h	Fri Mar 15 17:51:02 2002
@@ -3,21 +3,21 @@
 
 /*
  * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 #include <asm/hardirq.h>
 
-#define __local_bh_enable()	do { barrier(); local_bh_count()--; } while (0)
+#define __local_bh_enable()	do { barrier(); really_local_bh_count()--; } while (0)
 
-#define local_bh_disable()	do { local_bh_count()++; barrier(); } while (0)
+#define local_bh_disable()	do { really_local_bh_count()++; barrier(); } while (0)
 #define local_bh_enable()								\
 do {											\
 	__local_bh_enable();								\
-	if (__builtin_expect(local_softirq_pending(), 0) && local_bh_count() == 0)	\
+	if (__builtin_expect(local_softirq_pending(), 0) && really_local_bh_count() == 0)	\
 		do_softirq();								\
 } while (0)
 
 
-#define in_softirq()		(local_bh_count() != 0)
+#define in_softirq()		(really_local_bh_count() != 0)
 
 #endif /* _ASM_IA64_SOFTIRQ_H */
diff -Nru a/include/asm-ia64/spinlock.h b/include/asm-ia64/spinlock.h
--- a/include/asm-ia64/spinlock.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/spinlock.h	Fri Mar 15 17:51:01 2002
@@ -2,8 +2,8 @@
 #define _ASM_IA64_SPINLOCK_H
 
 /*
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  *
  * This file is used for SMP configurations only.
@@ -31,7 +31,7 @@
  * rather than a simple xchg to avoid writing the cache-line when
  * there is contention.
  */
-#define spin_lock(x)									\
+#define _raw_spin_lock(x)								\
 {											\
 	register char *addr __asm__ ("r31") = (char *) &(x)->lock;			\
 											\
@@ -49,7 +49,7 @@
 		: "ar.ccv", "ar.pfs", "b7", "p15", "r28", "r29", "r30", "memory");	\
 }
 
-#define spin_trylock(x)									\
+#define _raw_spin_trylock(x)								\
 ({											\
 	register long result;								\
 											\
@@ -62,7 +62,7 @@
 })
 
 #define spin_is_locked(x)	((x)->lock != 0)
-#define spin_unlock(x)		do { barrier(); ((spinlock_t *) x)->lock = 0;} while (0)
+#define _raw_spin_unlock(x)	do { barrier(); ((spinlock_t *) x)->lock = 0;} while (0)
 #define spin_unlock_wait(x)	do { barrier(); } while ((x)->lock)
 
 #else /* !NEW_LOCK */
@@ -79,7 +79,7 @@
  * rather than a simple xchg to avoid writing the cache-line when
  * there is contention.
  */
-#define spin_lock(x) __asm__ __volatile__ (			\
+#define _raw_spin_lock(x) __asm__ __volatile__ (		\
 	"mov ar.ccv = r0\n"					\
 	"mov r29 = 1\n"						\
 	";;\n"							\
@@ -93,11 +93,11 @@
 	"cmp4.eq p0,p7 = r0, r2\n"				\
 	"(p7) br.cond.spnt.few 1b\n"				\
 	";;\n"							\
-	:: "r"(&(x)->lock) : "r2", "r29", "memory")
+	:: "r"(&(x)->lock) : "ar.ccv", "p7", "r2", "r29", "memory")
 
 #define spin_is_locked(x)	((x)->lock != 0)
-#define spin_unlock(x)		do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
-#define spin_trylock(x)		(cmpxchg_acq(&(x)->lock, 0, 1) == 0)
+#define _raw_spin_unlock(x)	do { barrier(); ((spinlock_t *) x)->lock = 0; } while (0)
+#define _raw_spin_trylock(x)	(cmpxchg_acq(&(x)->lock, 0, 1) == 0)
 #define spin_unlock_wait(x)	do { barrier(); } while ((x)->lock)
 
 #endif /* !NEW_LOCK */
@@ -110,7 +110,7 @@
 
 #define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
 
-#define read_lock(rw)								\
+#define _raw_read_lock(rw)							\
 do {										\
 	int tmp = 0;								\
 	__asm__ __volatile__ ("1:\tfetchadd4.acq %0 = [%1], 1\n"		\
@@ -128,10 +128,10 @@
 			      ";;\n"						\
 			      ".previous\n"					\
 			      : "=&r" (tmp)					\
-			      : "r" (rw): "memory");				\
+			      : "r" (rw) : "p6", "memory");			\
 } while(0)
 
-#define read_unlock(rw)								\
+#define _raw_read_unlock(rw)							\
 do {										\
 	int tmp = 0;								\
 	__asm__ __volatile__ ("fetchadd4.rel %0 = [%1], -1\n"			\
@@ -140,7 +140,7 @@
 			      : "memory");					\
 } while(0)
 
-#define write_lock(rw)								\
+#define _raw_write_lock(rw)							\
 do {										\
  	__asm__ __volatile__ (							\
 		"mov ar.ccv = r0\n"						\
@@ -156,13 +156,13 @@
 		"cmp4.eq p0,p7 = r0, r2\n"					\
 		"(p7) br.cond.spnt.few 1b\n"					\
 		";;\n"								\
-		:: "r"(rw) : "r2", "r29", "memory");				\
+		:: "r"(rw) : "ar.ccv", "p7", "r2", "r29", "memory");		\
 } while(0)
 
-/*
- * clear_bit() has "acq" semantics; we're really need "rel" semantics,
- * but for simplicity, we simply do a fence for now...
- */
-#define write_unlock(x)				({clear_bit(31, (x)); mb();})
+#define _raw_write_unlock(x)								\
+({											\
+	smp_mb__before_clear_bit();	/* need barrier before releasing lock... */	\
+	clear_bit(31, (x));								\
+})
 
 #endif /*  _ASM_IA64_SPINLOCK_H */
diff -Nru a/include/asm-ia64/system.h b/include/asm-ia64/system.h
--- a/include/asm-ia64/system.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ia64/system.h	Fri Mar 15 17:51:03 2002
@@ -7,8 +7,8 @@
  * on information published in the Processor Abstraction Layer
  * and the System Abstraction Layer manual.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
- * Copyright (C) 1998-2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
  * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
  */
@@ -232,7 +232,7 @@
 		_tmp = __bad_increment_for_ia64_fetch_and_add();		\
 		break;								\
 	}									\
-	(__typeof__(*v)) (_tmp + (i));	/* return new value */			\
+	(__typeof__(*(v))) (_tmp + (i));	/* return new value */		\
 })
 
 /*
@@ -373,42 +373,54 @@
  * newly created thread returns directly to
  * ia64_ret_from_syscall_clear_r8.
  */
-extern struct task_struct *ia64_switch_to (void *next_task);
+extern void ia64_switch_to (void *next_task);
+
+struct task_struct;
 
 extern void ia64_save_extra (struct task_struct *task);
 extern void ia64_load_extra (struct task_struct *task);
 
-#define __switch_to(prev,next,last) do {						\
+#if defined(CONFIG_SMP) && defined(CONFIG_PERFMON)
+# define PERFMON_IS_SYSWIDE() (local_cpu_data->pfm_syst_wide != 0)
+#else
+# define PERFMON_IS_SYSWIDE() (0)
+#endif
+
+#define __switch_to(prev,next) do {							\
 	if (((prev)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID))	\
-	    || IS_IA32_PROCESS(ia64_task_regs(prev)))					\
+	    || IS_IA32_PROCESS(ia64_task_regs(prev)) || PERFMON_IS_SYSWIDE())		\
 		ia64_save_extra(prev);							\
 	if (((next)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID))	\
-	    || IS_IA32_PROCESS(ia64_task_regs(next)))					\
+	    || IS_IA32_PROCESS(ia64_task_regs(next)) || PERFMON_IS_SYSWIDE())		\
 		ia64_load_extra(next);							\
-	(last) = ia64_switch_to((next));						\
+	ia64_switch_to((next));								\
 } while (0)
 
 #ifdef CONFIG_SMP
-  /*
-   * In the SMP case, we save the fph state when context-switching
-   * away from a thread that modified fph.  This way, when the thread
-   * gets scheduled on another CPU, the CPU can pick up the state from
-   * task->thread.fph, avoiding the complication of having to fetch
-   * the latest fph state from another CPU.
-   */
-# define switch_to(prev,next,last) do {						\
+
+/* Return true if this CPU can call the console drivers in printk() */
+#define arch_consoles_callable() (cpu_online_map & (1UL << smp_processor_id()))
+
+/*
+ * In the SMP case, we save the fph state when context-switching
+ * away from a thread that modified fph.  This way, when the thread
+ * gets scheduled on another CPU, the CPU can pick up the state from
+ * task->thread.fph, avoiding the complication of having to fetch
+ * the latest fph state from another CPU.
+ */
+# define switch_to(prev,next) do {						\
 	if (ia64_psr(ia64_task_regs(prev))->mfh) {				\
 		ia64_psr(ia64_task_regs(prev))->mfh = 0;			\
 		(prev)->thread.flags |= IA64_THREAD_FPH_VALID;			\
 		__ia64_save_fpu((prev)->thread.fph);				\
 	}									\
 	ia64_psr(ia64_task_regs(prev))->dfh = 1;				\
-	__switch_to(prev,next,last);						\
+	__switch_to(prev,next);							\
   } while (0)
 #else
-# define switch_to(prev,next,last) do {						\
+# define switch_to(prev,next) do {						\
 	ia64_psr(ia64_task_regs(next))->dfh = (ia64_get_fpu_owner() != (next));	\
-	__switch_to(prev,next,last);						\
+	__switch_to(prev,next);							\
 } while (0)
 #endif
 
diff -Nru a/include/asm-ia64/thread_info.h b/include/asm-ia64/thread_info.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/asm-ia64/thread_info.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,69 @@
+/*
+ * Copyright (C) 2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
+ */
+#ifndef _ASM_IA64_THREAD_INFO_H
+#define _ASM_IA64_THREAD_INFO_H
+
+#include <asm/offsets.h>
+#include <asm/processor.h>
+#include <asm/ptrace.h>
+
+#define TI_EXEC_DOMAIN	0x00
+#define TI_FLAGS	0x08
+#define TI_CPU		0x0c
+#define TI_ADDR_LIMI	0x10
+
+#ifndef __ASSEMBLY__
+
+/*
+ * On IA-64, we want to keep the task structure and kernel stack together, so they can be
+ * mapped by a single TLB entry and so they can be addressed by the "current" pointer
+ * without having to do pointer masking.
+ */
+struct thread_info {
+	struct exec_domain *exec_domain;/* execution domain */
+	__u32 flags;			/* thread_info flags (see TIF_*) */
+	__u32 cpu;			/* current CPU */
+	mm_segment_t addr_limit;	/* user-level address space limit */
+};
+
+#define INIT_THREAD_SIZE		/* tell sched.h not to declare the thread_union */
+#define THREAD_SIZE			KERNEL_STACK_SIZE
+
+#define INIT_THREAD_INFO(ti)			\
+{						\
+	exec_domain:	&default_exec_domain,	\
+	flags:		0,			\
+	cpu:		0,			\
+	addr_limit:	KERNEL_DS,		\
+}
+
+/* how to get the thread information struct from C */
+#define current_thread_info() ((struct thread_info *) ((char *) current + IA64_TASK_SIZE))
+
+#endif /* !__ASSEMBLY */
+
+/*
+ * thread information flags
+ * - these are process state flags that various assembly files may need to access
+ * - pending work-to-be-done flags are in least-significant 16 bits, other flags
+ *   in top 16 bits
+ */
+#define TIF_NOTIFY_RESUME	0	/* resumption notification requested */
+#define TIF_SIGPENDING		1	/* signal pending */
+#define TIF_NEED_RESCHED	2	/* rescheduling necessary */
+#define TIF_SYSCALL_TRACE	3	/* syscall trace active */
+#define TIF_POLLING_NRFLAG	16	/* true if poll_idle() is polling TIF_NEED_RESCHED */
+
+#define TIF_WORK_MASK		0x7	/* like TIF_ALLWORK_BITS but sans TIF_SYSCALL_TRACE */
+#define TIF_ALLWORK_MASK	0xf	/* bits 0..3 are "work to do on user-return" bits */
+
+#define _TIF_SYSCALL_TRACE	(1 << TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME	(1 << TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING		(1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED	(1 << TIF_NEED_RESCHED)
+#define _TIF_USEDFPU		(1 << TIF_USEDFPU)
+#define _TIF_POLLING_NRFLAG	(1 << TIF_POLLING_NRFLAG)
+
+#endif /* _ASM_IA64_THREAD_INFO_H */
diff -Nru a/include/asm-ia64/uaccess.h b/include/asm-ia64/uaccess.h
--- a/include/asm-ia64/uaccess.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-ia64/uaccess.h	Fri Mar 15 17:51:02 2002
@@ -26,8 +26,8 @@
  * associated and, if so, sets r8 to -EFAULT and clears r9 to 0 and
  * then resumes execution at the continuation point.
  *
- * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
- * Copyright (C) 1998, 1999, 2001 David Mosberger-Tang <davidm@hpl.hp.com>
+ * Copyright (C) 1998, 1999, 2001-2002 Hewlett-Packard Co
+ *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
 #include <linux/errno.h>
@@ -45,8 +45,8 @@
 #define VERIFY_WRITE	1
 
 #define get_ds()  (KERNEL_DS)
-#define get_fs()  (current->addr_limit)
-#define set_fs(x) (current->addr_limit = (x))
+#define get_fs()  (current_thread_info()->addr_limit)
+#define set_fs(x) (current_thread_info()->addr_limit = (x))
 
 #define segment_eq(a,b)	((a).seg == (b).seg)
 
@@ -319,5 +319,23 @@
 
 extern struct exception_fixup search_exception_table (unsigned long addr);
 extern void handle_exception (struct pt_regs *regs, struct exception_fixup fixup);
+
+#ifdef GAS_HAS_LOCAL_TAGS
+#define SEARCH_EXCEPTION_TABLE(regs) search_exception_table(regs->cr_iip + ia64_psr(regs)->ri);
+#else
+#define SEARCH_EXCEPTION_TABLE(regs) search_exception_table(regs->cr_iip);
+#endif
+
+static inline int
+done_with_exception (struct pt_regs *regs)
+{
+	struct exception_fixup fix;
+	fix = SEARCH_EXCEPTION_TABLE(regs);
+	if (fix.cont) {
+		handle_exception(regs, fix);
+		return 1;
+	}
+	return 0;
+}
 
 #endif /* _ASM_IA64_UACCESS_H */
diff -Nru a/include/asm-ia64/unistd.h b/include/asm-ia64/unistd.h
--- a/include/asm-ia64/unistd.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ia64/unistd.h	Fri Mar 15 17:51:01 2002
@@ -4,7 +4,7 @@
 /*
  * IA-64 Linux syscall numbers and inline-functions.
  *
- * Copyright (C) 1998-2001 Hewlett-Packard Co
+ * Copyright (C) 1998-2002 Hewlett-Packard Co
  *	David Mosberger-Tang <davidm@hpl.hp.com>
  */
 
@@ -109,9 +109,9 @@
 #define __NR_syslog			1117
 #define __NR_setitimer			1118
 #define __NR_getitimer			1119
-#define __NR_old_stat			1120
-#define __NR_old_lstat			1121
-#define __NR_old_fstat			1122
+/* 1120 was __NR_old_stat */
+/* 1121 was __NR_old_lstat */
+/* 1122 was __NR_old_fstat */
 #define __NR_vhangup			1123
 #define __NR_lchown			1124
 #define __NR_vm86			1125
@@ -206,7 +206,19 @@
 #define __NR_getdents64			1214
 #define __NR_getunwind			1215
 #define __NR_readahead			1216
-#define __NR_tkill			1217
+#define __NR_setxattr			1217
+#define __NR_lsetxattr			1218
+#define __NR_fsetxattr			1219
+#define __NR_getxattr			1220
+#define __NR_lgetxattr			1221
+#define __NR_fgetxattr			1222
+#define __NR_listxattr			1223
+#define __NR_llistxattr			1224
+#define __NR_flistxattr			1225
+#define __NR_removexattr		1226
+#define __NR_lremovexattr		1227
+#define __NR_fremovexattr		1228
+#define __NR_tkill			1229
 
 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)
 
@@ -281,6 +293,8 @@
 }
 
 #ifdef __KERNEL_SYSCALLS__
+
+struct rusage;
 
 static inline _syscall0(int,sync)
 static inline _syscall0(pid_t,setsid)
diff -Nru a/include/asm-ppc/mman.h b/include/asm-ppc/mman.h
--- a/include/asm-ppc/mman.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-ppc/mman.h	Fri Mar 15 17:51:03 2002
@@ -7,6 +7,7 @@
 #define PROT_READ	0x1		/* page can be read */
 #define PROT_WRITE	0x2		/* page can be written */
 #define PROT_EXEC	0x4		/* page can be executed */
+#define PROT_SEM	0x8		/* page may be used for atomic ops */
 #define PROT_NONE	0x0		/* page can not be accessed */
 
 #define MAP_SHARED	0x01		/* Share changes */
diff -Nru a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
--- a/include/asm-ppc/unistd.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-ppc/unistd.h	Fri Mar 15 17:51:01 2002
@@ -228,6 +228,7 @@
 #define __NR_removexattr	218
 #define __NR_lremovexattr	219
 #define __NR_fremovexattr	220
+#define __NR_futex		221
 
 #define __NR(n)	#n
 
diff -Nru a/include/asm-sparc/mman.h b/include/asm-sparc/mman.h
--- a/include/asm-sparc/mman.h	Fri Mar 15 17:51:04 2002
+++ b/include/asm-sparc/mman.h	Fri Mar 15 17:51:04 2002
@@ -7,6 +7,7 @@
 #define PROT_READ	0x1		/* page can be read */
 #define PROT_WRITE	0x2		/* page can be written */
 #define PROT_EXEC	0x4		/* page can be executed */
+#define PROT_SEM	0x8		/* page may be used for atomic ops */
 #define PROT_NONE	0x0		/* page can not be accessed */
 
 #define MAP_SHARED	0x01		/* Share changes */
diff -Nru a/include/asm-sparc/siginfo.h b/include/asm-sparc/siginfo.h
--- a/include/asm-sparc/siginfo.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc/siginfo.h	Fri Mar 15 17:51:01 2002
@@ -113,6 +113,7 @@
 #define SI_ASYNCIO	-4		/* sent by AIO completion */
 #define SI_SIGIO	-5		/* sent by queued SIGIO */
 #define SI_TKILL	-6		/* sent by tkill system call */
+#define SI_DETHREAD	-7		/* sent by execve() killing subsidiary threads */
 
 #define SI_FROMUSER(siptr)	((siptr)->si_code <= 0)
 #define SI_FROMKERNEL(siptr)	((siptr)->si_code > 0)
diff -Nru a/include/asm-sparc/unistd.h b/include/asm-sparc/unistd.h
--- a/include/asm-sparc/unistd.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc/unistd.h	Fri Mar 15 17:51:01 2002
@@ -155,9 +155,9 @@
 #define __NR_rmdir              137 /* Common                                      */
 #define __NR_utimes             138 /* SunOS Specific                              */
 #define __NR_stat64		139 /* Linux sparc32 Specific			   */
-/* #define __NR_adjtime         140    SunOS Specific                              */
+#define __NR_sendfile64         140 /* adjtime under SunOS                         */
 #define __NR_getpeername        141 /* Common                                      */
-/* #define __NR_gethostid       142    SunOS Specific                              */
+#define __NR_futex              142 /* gethostid under SunOS                       */
 #define __NR_gettid             143 /* ENOSYS under SunOS                          */
 #define __NR_getrlimit          144 /* Common                                      */
 #define __NR_setrlimit          145 /* Common                                      */
diff -Nru a/include/asm-sparc64/bitops.h b/include/asm-sparc64/bitops.h
--- a/include/asm-sparc64/bitops.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc64/bitops.h	Fri Mar 15 17:51:01 2002
@@ -7,6 +7,7 @@
 #ifndef _SPARC64_BITOPS_H
 #define _SPARC64_BITOPS_H
 
+#include <linux/compiler.h>
 #include <asm/byteorder.h>
 
 extern long ___test_and_set_bit(unsigned long nr, volatile void *addr);
@@ -100,6 +101,23 @@
 }
 
 #ifdef __KERNEL__
+
+/*
+ * Every architecture must define this function. It's the fastest
+ * way of searching a 140-bit bitmap where the first 100 bits are
+ * unlikely to be set. It's guaranteed that at least one of the 140
+ * bits is cleared.
+ */
+static inline int sched_find_first_bit(unsigned long *b)
+{
+	if (unlikely(b[0]))
+		return __ffs(b[0]);
+	if (unlikely(((unsigned int)b[1])))
+		return __ffs(b[1]) + 64;
+	if (b[1] >> 32)
+		return __ffs(b[1] >> 32) + 96;
+	return __ffs(b[2]) + 128;
+}
 
 /*
  * ffs: find first bit set. This is defined the same way as
diff -Nru a/include/asm-sparc64/current.h b/include/asm-sparc64/current.h
--- a/include/asm-sparc64/current.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc64/current.h	Fri Mar 15 17:51:01 2002
@@ -3,6 +3,6 @@
 
 #include <asm/thread_info.h>
 
-#define current		(current_thread_info()->task)
+register struct task_struct *current asm("g4");
 
 #endif /* !(_SPARC64_CURRENT_H) */
diff -Nru a/include/asm-sparc64/fhc.h b/include/asm-sparc64/fhc.h
--- a/include/asm-sparc64/fhc.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-sparc64/fhc.h	Fri Mar 15 17:51:02 2002
@@ -86,10 +86,10 @@
 #define  FHC_BSR_NIA		0x0000001c /* Jumper, bit 18 in PROM space       */
 #define  FHC_BSR_SI		0x00000001 /* Spare input pin value              */
 #define FHC_PREGS_ECC	0x40UL	/* FHC ECC Control Register (16 bits) */
-#define FHC_PREGS_JCTRL	0x50UL	/* FHC JTAG Control Register */
+#define FHC_PREGS_JCTRL	0xf0UL	/* FHC JTAG Control Register */
 #define  FHC_JTAG_CTRL_MENAB	0x80000000 /* Indicates this is JTAG Master	 */
 #define  FHC_JTAG_CTRL_MNONE	0x40000000 /* Indicates no JTAG Master present	 */
-#define FHC_PREGS_JCMD	0x60UL	/* FHC JTAG Command Register */
+#define FHC_PREGS_JCMD	0x100UL	/* FHC JTAG Command Register */
 	unsigned long			ireg;	/* FHC IGN reg */
 #define FHC_IREG_IGN	0x00UL	/* This FHC's IGN */
 	unsigned long			ffregs;	/* FHC fanfail regs */
diff -Nru a/include/asm-sparc64/head.h b/include/asm-sparc64/head.h
--- a/include/asm-sparc64/head.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-sparc64/head.h	Fri Mar 15 17:51:02 2002
@@ -4,6 +4,8 @@
 
 #include <asm/pstate.h>
 
-#define KERNBASE    0x400000
+#define KERNBASE	0x400000
+
+#define	PTREGS_OFF	(STACK_BIAS + REGWIN_SZ)
 
 #endif /* !(_SPARC64_HEAD_H) */
diff -Nru a/include/asm-sparc64/mman.h b/include/asm-sparc64/mman.h
--- a/include/asm-sparc64/mman.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-sparc64/mman.h	Fri Mar 15 17:51:03 2002
@@ -7,6 +7,7 @@
 #define PROT_READ	0x1		/* page can be read */
 #define PROT_WRITE	0x2		/* page can be written */
 #define PROT_EXEC	0x4		/* page can be executed */
+#define PROT_SEM	0x8		/* page may be used for atomic ops */
 #define PROT_NONE	0x0		/* page can not be accessed */
 
 #define MAP_SHARED	0x01		/* Share changes */
diff -Nru a/include/asm-sparc64/mmu_context.h b/include/asm-sparc64/mmu_context.h
--- a/include/asm-sparc64/mmu_context.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-sparc64/mmu_context.h	Fri Mar 15 17:51:03 2002
@@ -27,25 +27,6 @@
 #include <asm/system.h>
 #include <asm/spitfire.h>
 
-/*
- * Every architecture must define this function. It's the fastest
- * way of searching a 168-bit bitmap where the first 128 bits are
- * unlikely to be set. It's guaranteed that at least one of the 168
- * bits is cleared.
- */
-#if MAX_RT_PRIO != 128 || MAX_PRIO != 168
-# error update this function.
-#endif
-
-static inline int sched_find_first_bit(unsigned long *b)
-{
-	if (unlikely(b[0]))
-		return __ffs(b[0]);
-	if (unlikely(b[1]))
-		return __ffs(b[1]) + 64;
-	return __ffs(b[2]) + 128;
-}
-
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
 {
 }
diff -Nru a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h
--- a/include/asm-sparc64/page.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-sparc64/page.h	Fri Mar 15 17:51:03 2002
@@ -106,12 +106,10 @@
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)	(((addr)+PAGE_SIZE-1)&PAGE_MASK)
 
-#ifndef __ASSEMBLY__
-/* Do prdele, look what happens to be in %g4... */
-register unsigned long PAGE_OFFSET asm("g4");
-#else
+/* We used to stick this into a hard-coded global register (%g4)
+ * but that does not make sense anymore.
+ */
 #define PAGE_OFFSET		0xFFFFF80000000000
-#endif
 
 #define __pa(x)			((unsigned long)(x) - PAGE_OFFSET)
 #define __va(x)			((void *)((unsigned long) (x) + PAGE_OFFSET))
diff -Nru a/include/asm-sparc64/pci.h b/include/asm-sparc64/pci.h
--- a/include/asm-sparc64/pci.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc64/pci.h	Fri Mar 15 17:51:01 2002
@@ -201,6 +201,10 @@
 			       enum pci_mmap_state mmap_state,
 			       int write_combine);
 
+/* Platform specific MWI support. */
+#define HAVE_ARCH_PCI_MWI
+extern int pcibios_prep_mwi(struct pci_dev *dev);
+
 #endif /* __KERNEL__ */
 
 #endif /* __SPARC64_PCI_H */
diff -Nru a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h
--- a/include/asm-sparc64/pgalloc.h	Fri Mar 15 17:51:02 2002
+++ b/include/asm-sparc64/pgalloc.h	Fri Mar 15 17:51:02 2002
@@ -10,95 +10,6 @@
 #include <asm/spitfire.h>
 #include <asm/pgtable.h>
 
-/* Cache and TLB flush operations. */
-
-/* These are the same regardless of whether this is an SMP kernel or not. */
-#define flush_cache_mm(__mm) \
-	do { if ((__mm) == current->mm) flushw_user(); } while(0)
-extern void flush_cache_range(struct vm_area_struct *, unsigned long, unsigned long);
-#define flush_cache_page(vma, page) \
-	flush_cache_mm((vma)->vm_mm)
-
-/* This is unnecessary on the SpitFire since D-CACHE is write-through. */
-#define flush_page_to_ram(page)			do { } while (0)
-
-/* 
- * On spitfire, the icache doesn't snoop local stores and we don't
- * use block commit stores (which invalidate icache lines) during
- * module load, so we need this.
- */
-extern void flush_icache_range(unsigned long start, unsigned long end);
-
-extern void __flush_dcache_page(void *addr, int flush_icache);
-extern void __flush_icache_page(unsigned long);
-extern void flush_dcache_page_impl(struct page *page);
-#ifdef CONFIG_SMP
-extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
-extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
-#else
-#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
-#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
-#endif
-
-extern void flush_dcache_page(struct page *page);
-
-extern void __flush_dcache_range(unsigned long start, unsigned long end);
-
-extern void __flush_cache_all(void);
-
-extern void __flush_tlb_all(void);
-extern void __flush_tlb_mm(unsigned long context, unsigned long r);
-extern void __flush_tlb_range(unsigned long context, unsigned long start,
-			      unsigned long r, unsigned long end,
-			      unsigned long pgsz, unsigned long size);
-extern void __flush_tlb_page(unsigned long context, unsigned long page, unsigned long r);
-
-#ifndef CONFIG_SMP
-
-#define flush_cache_all()	__flush_cache_all()
-#define flush_tlb_all()		__flush_tlb_all()
-
-#define flush_tlb_mm(__mm) \
-do { if(CTX_VALID((__mm)->context)) \
-	__flush_tlb_mm(CTX_HWBITS((__mm)->context), SECONDARY_CONTEXT); \
-} while(0)
-
-#define flush_tlb_range(__vma, start, end) \
-do { if(CTX_VALID((__vma)->vm_mm->context)) { \
-	unsigned long __start = (start)&PAGE_MASK; \
-	unsigned long __end = PAGE_ALIGN(end); \
-	__flush_tlb_range(CTX_HWBITS((__vma)->vm_mm->context), __start, \
-			  SECONDARY_CONTEXT, __end, PAGE_SIZE, \
-			  (__end - __start)); \
-     } \
-} while(0)
-
-#define flush_tlb_page(vma, page) \
-do { struct mm_struct *__mm = (vma)->vm_mm; \
-     if(CTX_VALID(__mm->context)) \
-	__flush_tlb_page(CTX_HWBITS(__mm->context), (page)&PAGE_MASK, \
-			 SECONDARY_CONTEXT); \
-} while(0)
-
-#else /* CONFIG_SMP */
-
-extern void smp_flush_cache_all(void);
-extern void smp_flush_tlb_all(void);
-extern void smp_flush_tlb_mm(struct mm_struct *mm);
-extern void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-				unsigned long end);
-extern void smp_flush_tlb_page(struct mm_struct *mm, unsigned long page);
-
-#define flush_cache_all()	smp_flush_cache_all()
-#define flush_tlb_all()		smp_flush_tlb_all()
-#define flush_tlb_mm(mm)	smp_flush_tlb_mm(mm)
-#define flush_tlb_range(vma, start, end) \
-	smp_flush_tlb_range(vma, start, end)
-#define flush_tlb_page(vma, page) \
-	smp_flush_tlb_page((vma)->vm_mm, page)
-
-#endif /* ! CONFIG_SMP */
-
 #define VPTE_BASE_SPITFIRE	0xfffffffe00000000
 #if 1
 #define VPTE_BASE_CHEETAH	VPTE_BASE_SPITFIRE
@@ -106,7 +17,7 @@
 #define VPTE_BASE_CHEETAH	0xffe0000000000000
 #endif
 
-extern __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start,
+static __inline__ void flush_tlb_pgtables(struct mm_struct *mm, unsigned long start,
 					  unsigned long end)
 {
 	/* Note the signed type.  */
@@ -154,7 +65,7 @@
 
 #ifndef CONFIG_SMP
 
-extern __inline__ void free_pgd_fast(pgd_t *pgd)
+static __inline__ void free_pgd_fast(pgd_t *pgd)
 {
 	struct page *page = virt_to_page(pgd);
 
@@ -169,7 +80,7 @@
 	preempt_enable();
 }
 
-extern __inline__ pgd_t *get_pgd_fast(void)
+static __inline__ pgd_t *get_pgd_fast(void)
 {
         struct page *ret;
 
@@ -212,7 +123,7 @@
 
 #else /* CONFIG_SMP */
 
-extern __inline__ void free_pgd_fast(pgd_t *pgd)
+static __inline__ void free_pgd_fast(pgd_t *pgd)
 {
 	preempt_disable();
 	*(unsigned long *)pgd = (unsigned long) pgd_quicklist;
@@ -221,7 +132,7 @@
 	preempt_enable();
 }
 
-extern __inline__ pgd_t *get_pgd_fast(void)
+static __inline__ pgd_t *get_pgd_fast(void)
 {
 	unsigned long *ret;
 
@@ -240,7 +151,7 @@
 	return (pgd_t *)ret;
 }
 
-extern __inline__ void free_pgd_slow(pgd_t *pgd)
+static __inline__ void free_pgd_slow(pgd_t *pgd)
 {
 	free_page((unsigned long)pgd);
 }
@@ -257,23 +168,15 @@
 
 #define pgd_populate(MM, PGD, PMD)	pgd_set(PGD, PMD)
 
-extern __inline__ pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-	pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL);
-	if (pmd)
-		memset(pmd, 0, PAGE_SIZE);
-	return pmd;
-}
-
-extern __inline__ pmd_t *pmd_alloc_one_fast(struct mm_struct *mm, unsigned long address)
+static __inline__ pmd_t *pmd_alloc_one_fast(struct mm_struct *mm, unsigned long address)
 {
 	unsigned long *ret;
 	int color = 0;
 
+	preempt_disable();
 	if (pte_quicklist[color] == NULL)
 		color = 1;
 
-	preempt_disable();
 	if((ret = (unsigned long *)pte_quicklist[color]) != NULL) {
 		pte_quicklist[color] = (unsigned long *)(*ret);
 		ret[0] = 0;
@@ -284,7 +187,20 @@
 	return (pmd_t *)ret;
 }
 
-extern __inline__ void free_pmd_fast(pmd_t *pmd)
+static __inline__ pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
+{
+	pmd_t *pmd;
+
+	pmd = pmd_alloc_one_fast(mm, address);
+	if (!pmd) {
+		pmd = (pmd_t *)__get_free_page(GFP_KERNEL);
+		if (pmd)
+			memset(pmd, 0, PAGE_SIZE);
+	}
+	return pmd;
+}
+
+static __inline__ void free_pmd_fast(pmd_t *pmd)
 {
 	unsigned long color = DCACHE_COLOR((unsigned long)pmd);
 
@@ -295,16 +211,19 @@
 	preempt_enable();
 }
 
-extern __inline__ void free_pmd_slow(pmd_t *pmd)
+static __inline__ void free_pmd_slow(pmd_t *pmd)
 {
 	free_page((unsigned long)pmd);
 }
 
-#define pmd_populate(MM, PMD, PTE)	pmd_set(PMD, PTE)
+#define pmd_populate_kernel(MM, PMD, PTE)	pmd_set(PMD, PTE)
+#define pmd_populate(MM,PMD,PTE_PAGE)		\
+	pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
 
-extern pte_t *pte_alloc_one(struct mm_struct *mm, unsigned long address);
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address);
+#define pte_alloc_one(MM,ADDR)	virt_to_page(pte_alloc_one_kernel(MM,ADDR))
 
-extern __inline__ pte_t *pte_alloc_one_fast(struct mm_struct *mm, unsigned long address)
+static __inline__ pte_t *pte_alloc_one_fast(struct mm_struct *mm, unsigned long address)
 {
 	unsigned long color = VPTE_COLOR(address);
 	unsigned long *ret;
@@ -319,7 +238,7 @@
 	return (pte_t *)ret;
 }
 
-extern __inline__ void free_pte_fast(pte_t *pte)
+static __inline__ void free_pte_fast(pte_t *pte)
 {
 	unsigned long color = DCACHE_COLOR((unsigned long)pte);
 
@@ -330,16 +249,15 @@
 	preempt_enable();
 }
 
-extern __inline__ void free_pte_slow(pte_t *pte)
+static __inline__ void free_pte_slow(pte_t *pte)
 {
 	free_page((unsigned long)pte);
 }
 
-#define pte_free(pte)		free_pte_fast(pte)
+#define pte_free_kernel(pte)	free_pte_fast(pte)
+#define pte_free(pte)		free_pte_fast(page_address(pte))
 #define pmd_free(pmd)		free_pmd_fast(pmd)
 #define pgd_free(pgd)		free_pgd_fast(pgd)
 #define pgd_alloc(mm)		get_pgd_fast()
-
-extern int do_check_pgt_cache(int, int);
 
 #endif /* _SPARC64_PGALLOC_H */
diff -Nru a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
--- a/include/asm-sparc64/pgtable.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc64/pgtable.h	Fri Mar 15 17:51:01 2002
@@ -36,6 +36,95 @@
 #define LOW_OBP_ADDRESS		0x00000000f0000000
 #define HI_OBP_ADDRESS		0x0000000100000000
 
+#ifndef __ASSEMBLY__
+
+/* Cache and TLB flush operations. */
+
+/* These are the same regardless of whether this is an SMP kernel or not. */
+#define flush_cache_mm(__mm) \
+	do { if ((__mm) == current->mm) flushw_user(); } while(0)
+extern void flush_cache_range(struct vm_area_struct *, unsigned long, unsigned long);
+#define flush_cache_page(vma, page) \
+	flush_cache_mm((vma)->vm_mm)
+
+
+/* 
+ * On spitfire, the icache doesn't snoop local stores and we don't
+ * use block commit stores (which invalidate icache lines) during
+ * module load, so we need this.
+ */
+extern void flush_icache_range(unsigned long start, unsigned long end);
+
+extern void __flush_dcache_page(void *addr, int flush_icache);
+extern void __flush_icache_page(unsigned long);
+extern void flush_dcache_page_impl(struct page *page);
+#ifdef CONFIG_SMP
+extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
+extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
+#else
+#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
+#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
+#endif
+
+extern void __flush_dcache_range(unsigned long start, unsigned long end);
+
+extern void __flush_cache_all(void);
+
+extern void __flush_tlb_all(void);
+extern void __flush_tlb_mm(unsigned long context, unsigned long r);
+extern void __flush_tlb_range(unsigned long context, unsigned long start,
+			      unsigned long r, unsigned long end,
+			      unsigned long pgsz, unsigned long size);
+extern void __flush_tlb_page(unsigned long context, unsigned long page, unsigned long r);
+
+#ifndef CONFIG_SMP
+
+#define flush_cache_all()	__flush_cache_all()
+#define flush_tlb_all()		__flush_tlb_all()
+
+#define flush_tlb_mm(__mm) \
+do { if(CTX_VALID((__mm)->context)) \
+	__flush_tlb_mm(CTX_HWBITS((__mm)->context), SECONDARY_CONTEXT); \
+} while(0)
+
+#define flush_tlb_range(__vma, start, end) \
+do { if(CTX_VALID((__vma)->vm_mm->context)) { \
+	unsigned long __start = (start)&PAGE_MASK; \
+	unsigned long __end = PAGE_ALIGN(end); \
+	__flush_tlb_range(CTX_HWBITS((__vma)->vm_mm->context), __start, \
+			  SECONDARY_CONTEXT, __end, PAGE_SIZE, \
+			  (__end - __start)); \
+     } \
+} while(0)
+
+#define flush_tlb_page(vma, page) \
+do { struct mm_struct *__mm = (vma)->vm_mm; \
+     if(CTX_VALID(__mm->context)) \
+	__flush_tlb_page(CTX_HWBITS(__mm->context), (page)&PAGE_MASK, \
+			 SECONDARY_CONTEXT); \
+} while(0)
+
+#else /* CONFIG_SMP */
+
+extern void smp_flush_cache_all(void);
+extern void smp_flush_tlb_all(void);
+extern void smp_flush_tlb_mm(struct mm_struct *mm);
+extern void smp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
+				unsigned long end);
+extern void smp_flush_tlb_page(struct mm_struct *mm, unsigned long page);
+
+#define flush_cache_all()	smp_flush_cache_all()
+#define flush_tlb_all()		smp_flush_tlb_all()
+#define flush_tlb_mm(mm)	smp_flush_tlb_mm(mm)
+#define flush_tlb_range(vma, start, end) \
+	smp_flush_tlb_range(vma, start, end)
+#define flush_tlb_page(vma, page) \
+	smp_flush_tlb_page((vma)->vm_mm, page)
+
+#endif /* ! CONFIG_SMP */
+
+#endif /* ! __ASSEMBLY__ */
+
 /* XXX All of this needs to be rethought so we can take advantage
  * XXX cheetah's full 64-bit virtual address space, ie. no more hole
  * XXX in the middle like on spitfire. -DaveM
@@ -215,7 +304,8 @@
 	(pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
 #define pgd_set(pgdp, pmdp)	\
 	(pgd_val(*(pgdp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
-#define pmd_page(pmd)			((unsigned long) __va((pmd_val(pmd)<<11UL)))
+#define __pmd_page(pmd)			((unsigned long) __va((pmd_val(pmd)<<11UL)))
+#define pmd_page(pmd) 			virt_to_page((void *)__pmd_page(pmd))
 #define pgd_page(pgd)			((unsigned long) __va((pgd_val(pgd)<<11UL)))
 #define pte_none(pte) 			(!pte_val(pte))
 #define pte_present(pte)		(pte_val(pte) & _PAGE_PRESENT)
@@ -264,8 +354,13 @@
 					((address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD-1)))
 
 /* Find an entry in the third-level page table.. */
-#define pte_offset(dir, address)	((pte_t *) pmd_page(*(dir)) + \
+#define __pte_offset(dir, address)	((pte_t *) __pmd_page(*(dir)) + \
 					((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+#define pte_offset_kernel		__pte_offset
+#define pte_offset_map			__pte_offset
+#define pte_offset_map_nested		__pte_offset
+#define pte_unmap(pte)			do { } while (0)
+#define pte_unmap_nested(pte)		do { } while (0)
 
 extern pgd_t swapper_pg_dir[1];
 
@@ -312,10 +407,10 @@
 		return addr & _PAGE_PADDR;
 	if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
 		return prom_virt_to_phys(addr, 0);
-	pgdp = pgd_offset_k (addr);
-	pmdp = pmd_offset (pgdp, addr);
-	ptep = pte_offset (pmdp, addr);
-	return pte_val (*ptep) & _PAGE_PADDR;
+	pgdp = pgd_offset_k(addr);
+	pmdp = pmd_offset(pgdp, addr);
+	ptep = pte_offset_kernel(pmdp, addr);
+	return pte_val(*ptep) & _PAGE_PADDR;
 }
 
 extern __inline__ unsigned long
@@ -350,11 +445,18 @@
 extern unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, unsigned long, unsigned long, unsigned long);
 #define HAVE_ARCH_FB_UNMAPPED_AREA
 
-#endif /* !(__ASSEMBLY__) */
-
 /*
  * No page table caches to initialise
  */
 #define pgtable_cache_init()	do { } while (0)
+
+extern void check_pgt_cache(void);
+
+extern void flush_dcache_page(struct page *page);
+
+/* This is unnecessary on the SpitFire since D-CACHE is write-through. */
+#define flush_page_to_ram(page)			do { } while (0)
+
+#endif /* !(__ASSEMBLY__) */
 
 #endif /* !(_SPARC64_PGTABLE_H) */
diff -Nru a/include/asm-sparc64/pil.h b/include/asm-sparc64/pil.h
--- a/include/asm-sparc64/pil.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-sparc64/pil.h	Fri Mar 15 17:51:03 2002
@@ -3,19 +3,24 @@
 #define _SPARC64_PIL_H
 
 /* To avoid some locking problems, we hard allocate certain PILs
- * for SMP cross call messages.  cli() does not block the cross
- * call delivery, so when SMP locking is an issue we reschedule
- * the event into a PIL interrupt which is blocked by cli().
+ * for SMP cross call messages that must do a etrap/rtrap.
  *
- * XXX In fact the whole set of PILs used for hardware interrupts
- * XXX may be allocated in this manner.  All of the devices can
- * XXX happily sit at the same PIL.  We would then need only two
- * XXX PILs, one for devices and one for the CPU local timer tick.
+ * A cli() does not block the cross call delivery, so when SMP
+ * locking is an issue we reschedule the event into a PIL interrupt
+ * which is blocked by cli().
+ *
+ * In fact any XCALL which has to etrap/rtrap has a problem because
+ * it is difficult to prevent rtrap from running BH's, and that would
+ * need to be done if the XCALL arrived while %pil==15.
  */
-#define PIL_MIGRATE	1
+#define PIL_SMP_CALL_FUNC	1
+#define PIL_SMP_RECEIVE_SIGNAL	2
+#define PIL_SMP_CAPTURE		3
 
 #ifndef __ASSEMBLY__
-#define PIL_RESERVED(PIL)	((PIL) == PIL_MIGRATE)
+#define PIL_RESERVED(PIL)	((PIL) == PIL_SMP_CALL_FUNC || \
+				 (PIL) == PIL_SMP_RECEIVE_SIGNAL || \
+				 (PIL) == PIL_SMP_CAPTURE)
 #endif
 
 #endif /* !(_SPARC64_PIL_H) */
diff -Nru a/include/asm-sparc64/siginfo.h b/include/asm-sparc64/siginfo.h
--- a/include/asm-sparc64/siginfo.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-sparc64/siginfo.h	Fri Mar 15 17:51:03 2002
@@ -173,6 +173,7 @@
 #define SI_ASYNCIO	-4		/* sent by AIO completion */
 #define SI_SIGIO	-5		/* sent by queued SIGIO */
 #define SI_TKILL	-6		/* sent by tkill system call */
+#define SI_DETHREAD	-7		/* sent by execve() killing subsidiary threads */
 
 #define SI_FROMUSER(siptr)	((siptr)->si_code <= 0)
 #define SI_FROMKERNEL(siptr)	((siptr)->si_code > 0)
diff -Nru a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
--- a/include/asm-sparc64/system.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc64/system.h	Fri Mar 15 17:51:01 2002
@@ -172,7 +172,7 @@
 	 * not preserve it's value.  Hairy, but it lets us remove 2 loads
 	 * and 2 stores in this critical code path.  -DaveM
 	 */
-#define switch_to(prev, next, last)						\
+#define switch_to(prev, next)							\
 do {	CHECK_LOCKS(prev);							\
 	if (test_thread_flag(TIF_PERFCTR)) {					\
 		unsigned long __tmp;						\
@@ -193,27 +193,28 @@
 	"stx	%%i6, [%%sp + 2047 + 0x70]\n\t"					\
 	"stx	%%i7, [%%sp + 2047 + 0x78]\n\t"					\
 	"rdpr	%%wstate, %%o5\n\t"						\
-	"stx	%%o6, [%%g6 + %3]\n\t"						\
-	"stb	%%o5, [%%g6 + %2]\n\t"						\
+	"stx	%%o6, [%%g6 + %2]\n\t"						\
+	"stb	%%o5, [%%g6 + %1]\n\t"						\
 	"rdpr	%%cwp, %%o5\n\t"						\
-	"stb	%%o5, [%%g6 + %5]\n\t"						\
-	"mov	%1, %%g6\n\t"							\
-	"ldub	[%1 + %5], %%g1\n\t"						\
+	"stb	%%o5, [%%g6 + %4]\n\t"						\
+	"mov	%0, %%g6\n\t"							\
+	"ldub	[%0 + %4], %%g1\n\t"						\
 	"wrpr	%%g1, %%cwp\n\t"						\
-	"ldx	[%%g6 + %3], %%o6\n\t"						\
-	"ldub	[%%g6 + %2], %%o5\n\t"						\
-	"ldx	[%%g6 + %4], %%o7\n\t"						\
+	"ldx	[%%g6 + %2], %%o6\n\t"						\
+	"ldub	[%%g6 + %1], %%o5\n\t"						\
+	"ldx	[%%g6 + %3], %%o7\n\t"						\
 	"mov	%%g6, %%l2\n\t"							\
 	"wrpr	%%o5, 0x0, %%wstate\n\t"					\
 	"ldx	[%%sp + 2047 + 0x70], %%i6\n\t"					\
 	"ldx	[%%sp + 2047 + 0x78], %%i7\n\t"					\
 	"wrpr	%%g0, 0x94, %%pstate\n\t"					\
 	"mov	%%l2, %%g6\n\t"							\
+	"ldx	[%%g6 + %6], %%g4\n\t"						\
 	"wrpr	%%g0, 0x96, %%pstate\n\t"					\
-	"andcc	%%o7, %6, %%g0\n\t"						\
+	"andcc	%%o7, %5, %%g0\n\t"						\
 	"bne,pn	%%icc, ret_from_syscall\n\t"					\
-	" ldx	[%%g5 + %7], %0\n\t"						\
-	: "=&r" (last)								\
+	" nop\n\t"								\
+	: /* no outputs */							\
 	: "r" (next->thread_info),						\
 	  "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_FLAGS), "i" (TI_CWP),		\
 	  "i" (_TIF_NEWCHILD), "i" (TI_TASK)					\
diff -Nru a/include/asm-sparc64/thread_info.h b/include/asm-sparc64/thread_info.h
--- a/include/asm-sparc64/thread_info.h	Fri Mar 15 17:51:03 2002
+++ b/include/asm-sparc64/thread_info.h	Fri Mar 15 17:51:03 2002
@@ -28,6 +28,7 @@
 
 #include <asm/ptrace.h>
 #include <asm/types.h>
+#include <asm/page.h>
 
 struct task_struct;
 struct exec_domain;
diff -Nru a/include/asm-sparc64/unistd.h b/include/asm-sparc64/unistd.h
--- a/include/asm-sparc64/unistd.h	Fri Mar 15 17:51:01 2002
+++ b/include/asm-sparc64/unistd.h	Fri Mar 15 17:51:01 2002
@@ -155,9 +155,9 @@
 #define __NR_rmdir              137 /* Common                                      */
 #define __NR_utimes             138 /* SunOS Specific                              */
 /* #define __NR_stat64		139    Linux sparc32 Specific			   */
-/* #define __NR_adjtime         140    SunOS Specific                              */
+#define __NR_sendfile64         140 /* adjtime under SunOS                         */
 #define __NR_getpeername        141 /* Common                                      */
-/* #define __NR_gethostid       142    SunOS Specific                              */
+#define __NR_futex              142 /* gethostid under SunOS                       */
 #define __NR_gettid             143 /* ENOSYS under SunOS                          */
 #define __NR_getrlimit		144 /* Common                                      */
 #define __NR_setrlimit          145 /* Common                                      */
diff -Nru a/include/linux/acpi.h b/include/linux/acpi.h
--- a/include/linux/acpi.h	Fri Mar 15 17:51:00 2002
+++ b/include/linux/acpi.h	Fri Mar 15 17:51:00 2002
@@ -1,180 +1,390 @@
 /*
- *  acpi.h - ACPI driver interface
+ * acpi.h - ACPI Interface
  *
- *  Copyright (C) 1999 Andrew Henroid
+ * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  */
 
 #ifndef _LINUX_ACPI_H
 #define _LINUX_ACPI_H
 
-#include <linux/types.h>
-#include <linux/ioctl.h>
-#ifdef __KERNEL__
-#include <linux/sched.h>
-#include <linux/wait.h>
-#endif /* __KERNEL__ */
+#ifndef _LINUX
+#define _LINUX
+#endif
+
+#include "../../drivers/acpi/include/acpi.h"
+#include <asm/acpi.h>
+
+
+/* --------------------------------------------------------------------------
+                             Boot-Time Table Parsing
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_ACPI_BOOT
+
+/* Root System Description Pointer (RSDP) */
+
+struct acpi_table_rsdp {
+	char			signature[8];
+	u8			checksum;
+	char			oem_id[6];
+	u8			revision;
+	u32			rsdt_address;
+} __attribute__ ((packed));
+
+struct acpi20_table_rsdp {
+	char			signature[8];
+	u8			checksum;
+	char			oem_id[6];
+	u8			revision;
+	u32			rsdt_address;
+	u32			length;
+	u64			xsdt_address;
+	u8			ext_checksum;
+	u8			reserved[3];
+} __attribute__ ((packed));
+
+/* Common table header */
+
+struct acpi_table_header {
+	char			signature[4];
+	u32			length;
+	u8			revision;
+	u8			checksum;
+	char			oem_id[6];
+	char			oem_table_id[8];
+	u32			oem_revision;
+	char			asl_compiler_id[4];
+	u32			asl_compiler_revision;
+} __attribute__ ((packed));
+
+typedef struct {
+	u8			type;
+	u8			length;
+} acpi_table_entry_header __attribute__ ((packed));
+
+/* Root System Description Table (RSDT) */
+
+struct acpi_table_rsdt {
+	struct acpi_table_header header;
+	u32			entry[1];
+} __attribute__ ((packed));
+
+/* Extended System Description Table (XSDT) */
+
+struct acpi_table_xsdt {
+	struct acpi_table_header header;
+	u64			entry[1];
+} __attribute__ ((packed));
+
+/* Multiple APIC Description Table (MADT) */
+
+struct acpi_table_madt {
+	struct acpi_table_header header;
+	u32			lapic_address;
+	struct {
+		u32			pcat_compat:1;
+		u32			reserved:31;
+	}			flags;
+} __attribute__ ((packed));
+
+enum acpi_madt_entry_id {
+	ACPI_MADT_LAPIC = 0,
+	ACPI_MADT_IOAPIC,
+	ACPI_MADT_INT_SRC_OVR,
+	ACPI_MADT_NMI_SRC,
+	ACPI_MADT_LAPIC_NMI,
+	ACPI_MADT_LAPIC_ADDR_OVR,
+	ACPI_MADT_IOSAPIC,
+	ACPI_MADT_LSAPIC,
+	ACPI_MADT_PLAT_INT_SRC,
+	ACPI_MADT_ENTRY_COUNT
+};
+
+typedef struct {
+	u16			polarity:2;
+	u16			trigger:2;
+	u16			reserved:12;
+} acpi_interrupt_flags __attribute__ ((packed));
+
+struct acpi_table_lapic {
+	acpi_table_entry_header	header;
+	u8			acpi_id;
+	u8			id;
+	struct {
+		u32			enabled:1;
+		u32			reserved:31;
+	}			flags;
+} __attribute__ ((packed));
+
+struct acpi_table_ioapic {
+	acpi_table_entry_header	header;
+	u8			id;
+	u8			reserved;
+	u32			address;
+	u32			global_irq_base;
+} __attribute__ ((packed));
+
+struct acpi_table_int_src_ovr {
+	acpi_table_entry_header	header;
+	u8			bus;
+	u8			bus_irq;
+	u32			global_irq;
+	acpi_interrupt_flags	flags;
+} __attribute__ ((packed));
+
+struct acpi_table_nmi_src {
+	acpi_table_entry_header	header;
+	acpi_interrupt_flags	flags;
+	u32			global_irq;
+} __attribute__ ((packed));
+
+struct acpi_table_lapic_nmi {
+	acpi_table_entry_header	header;
+	u8			acpi_id;
+	acpi_interrupt_flags	flags;
+	u8			lint;
+} __attribute__ ((packed));
+
+struct acpi_table_lapic_addr_ovr {
+	acpi_table_entry_header	header;
+	u8			reserved[2];
+	u64			address;
+} __attribute__ ((packed));
+
+struct acpi_table_iosapic {
+	acpi_table_entry_header	header;
+	u8			id;
+	u8			reserved;
+	u32			global_irq_base;
+	u64			address;
+} __attribute__ ((packed));
+
+struct acpi_table_lsapic {
+	acpi_table_entry_header	header;
+	u8			acpi_id;
+	u8			id;
+	u8			eid;
+	u8			reserved[3];
+	struct {
+		u32			enabled:1;
+		u32			reserved:31;
+	}			flags;
+} __attribute__ ((packed));
+
+struct acpi_table_plat_int_src {
+	acpi_table_entry_header	header;
+	acpi_interrupt_flags	flags;
+	u8			type;	/* See acpi_interrupt_type */
+	u8			id;
+	u8			eid;
+	u8			iosapic_vector;
+	u32			global_irq;
+	u32			reserved;
+} __attribute__ ((packed));
+
+enum acpi_interrupt_id {
+	ACPI_INTERRUPT_PMI	= 1,
+	ACPI_INTERRUPT_INIT,
+	ACPI_INTERRUPT_CPEI,
+	ACPI_INTERRUPT_COUNT
+};
 
 /*
- * Device states
+ * System Resource Affinity Table (SRAT)
+ *   see http://www.microsoft.com/hwdev/design/srat.htm
  */
-typedef enum {
-	ACPI_D0, /* fully-on */
-	ACPI_D1, /* partial-on */
-	ACPI_D2, /* partial-on */
-	ACPI_D3, /* fully-off */
-} acpi_dstate_t;
-
-typedef enum {
-	ACPI_S0, /* working state */
-	ACPI_S1, /* power-on suspend */
-	ACPI_S2, /* suspend to ram, with devices */
-	ACPI_S3, /* suspend to ram */
-	ACPI_S4, /* suspend to disk */
-	ACPI_S5, /* soft-off */
-} acpi_sstate_t;
-
-/* RSDP location */
-#define ACPI_BIOS_ROM_BASE (0x0e0000)
-#define ACPI_BIOS_ROM_END  (0x100000)
-
-/* Table signatures */
-#define ACPI_RSDP1_SIG 0x20445352 /* 'RSD ' */
-#define ACPI_RSDP2_SIG 0x20525450 /* 'PTR ' */
-#define ACPI_RSDT_SIG  0x54445352 /* 'RSDT' */
-#define ACPI_FADT_SIG  0x50434146 /* 'FACP' */
-#define ACPI_DSDT_SIG  0x54445344 /* 'DSDT' */
-#define ACPI_FACS_SIG  0x53434146 /* 'FACS' */
-
-#define ACPI_SIG_LEN		4
-#define ACPI_FADT_SIGNATURE	"FACP"
-
-/* PM1_STS/EN flags */
-#define ACPI_TMR    0x0001
-#define ACPI_BM	    0x0010
-#define ACPI_GBL    0x0020
-#define ACPI_PWRBTN 0x0100
-#define ACPI_SLPBTN 0x0200
-#define ACPI_RTC    0x0400
-#define ACPI_WAK    0x8000
-
-/* PM1_CNT flags */
-#define ACPI_SCI_EN   0x0001
-#define ACPI_BM_RLD   0x0002
-#define ACPI_GBL_RLS  0x0004
-#define ACPI_SLP_TYP0 0x0400
-#define ACPI_SLP_TYP1 0x0800
-#define ACPI_SLP_TYP2 0x1000
-#define ACPI_SLP_EN   0x2000
-
-#define ACPI_SLP_TYP_MASK  0x1c00
-#define ACPI_SLP_TYP_SHIFT 10
-
-/* PM_TMR masks */
-#define ACPI_TMR_VAL_EXT 0x00000100
-#define ACPI_TMR_MASK	 0x00ffffff
-#define ACPI_TMR_HZ	 3579545 /* 3.58 MHz */
-#define ACPI_TMR_KHZ	 (ACPI_TMR_HZ / 1000)
-
-#define ACPI_MICROSEC_TO_TMR_TICKS(val) \
-  (((val) * (ACPI_TMR_KHZ)) / 1000)
-
-/* PM2_CNT flags */
-#define ACPI_ARB_DIS 0x01
-
-/* FADT flags */
-#define ACPI_WBINVD	  0x00000001
-#define ACPI_WBINVD_FLUSH 0x00000002
-#define ACPI_PROC_C1	  0x00000004
-#define ACPI_P_LVL2_UP	  0x00000008
-#define ACPI_PWR_BUTTON	  0x00000010
-#define ACPI_SLP_BUTTON	  0x00000020
-#define ACPI_FIX_RTC	  0x00000040
-#define ACPI_RTC_64	  0x00000080
-#define ACPI_TMR_VAL_EXT  0x00000100
-#define ACPI_DCK_CAP	  0x00000200
-
-/* FADT BOOT_ARCH flags */
-#define FADT_BOOT_ARCH_LEGACY_DEVICES	0x0001
-#define FADT_BOOT_ARCH_KBD_CONTROLLER	0x0002
-
-/* FACS flags */
-#define ACPI_S4BIOS	  0x00000001
-
-/* processor block offsets */
-#define ACPI_P_CNT	  0x00000000
-#define ACPI_P_LVL2	  0x00000004
-#define ACPI_P_LVL3	  0x00000005
-
-/* C-state latencies (microseconds) */
-#define ACPI_MAX_P_LVL2_LAT 100
-#define ACPI_MAX_P_LVL3_LAT 1000
-#define ACPI_INFINITE_LAT   (~0UL)
+
+struct acpi_table_srat {
+	struct acpi_table_header header;
+	u32			table_revision;
+	u64			reserved;
+} __attribute__ ((packed));
+
+enum acpi_srat_entry_id {
+	ACPI_SRAT_PROCESSOR_AFFINITY = 0,
+	ACPI_SRAT_MEMORY_AFFINITY,
+	ACPI_SRAT_ENTRY_COUNT
+};
+
+struct acpi_table_processor_affinity {
+	acpi_table_entry_header	header;
+	u8			proximity_domain;
+	u8			apic_id;
+	struct {
+		u32			enabled:1;
+		u32			reserved:31;
+	}			flags;
+	u8			lsapic_eid;
+	u8			reserved[7];
+} __attribute__ ((packed));
+
+struct acpi_table_memory_affinity {
+	acpi_table_entry_header	header;
+	u8			proximity_domain;
+	u8			reserved1[5];
+	u32			base_addr_lo;
+	u32			base_addr_hi;
+	u32			length_lo;
+	u32			length_hi;
+	u32			memory_type;	/* See acpi_address_range_id */
+	struct {
+		u32			enabled:1;
+		u32			hot_pluggable:1;
+		u32			reserved:30;
+	}			flags;
+	u64			reserved2;
+} __attribute__ ((packed));
+
+enum acpi_address_range_id {
+	ACPI_ADDRESS_RANGE_MEMORY = 1,
+	ACPI_ADDRESS_RANGE_RESERVED = 2,
+	ACPI_ADDRESS_RANGE_ACPI = 3,
+	ACPI_ADDRESS_RANGE_NVS	= 4,
+	ACPI_ADDRESS_RANGE_COUNT
+};
 
 /*
- * Sysctl declarations
+ * System Locality Information Table (SLIT)
+ *   see http://devresource.hp.com/devresource/docs/techpapers/ia64/slit.pdf
  */
 
-enum
-{
-	CTL_ACPI = 10
+struct acpi_table_slit {
+	struct acpi_table_header header;
+	u64			localities;
+	u8			entry[1];	/* real size = localities^2 */
 };
 
-enum
-{
-	ACPI_FADT = 1,
+/* Smart Battery Description Table (SBST) */
+
+struct acpi_table_sbst {
+	struct acpi_table_header header;
+	u32			warning;	/* Warn user */
+	u32			low;		/* Critical sleep */
+	u32			critical;	/* Critical shutdown */
+} __attribute__ ((packed));
+
+/* Embedded Controller Boot Resources Table (ECDT) */
+
+/* TBD: acpi_generic_address
+struct acpi_table_ecdt {
+	struct acpi_table_header header;
+	acpi_generic_address	ec_control;
+	acpi_generic_address	ec_data;
+	u32			uid;
+	u8			gpe_bit;
+	char			*ec_id;
+} __attribute__ ((packed));
+*/
+
+/* Table Handlers */
+
+enum acpi_table_id {
+	ACPI_TABLE_UNKNOWN = 0,
+	ACPI_APIC,
+	ACPI_BOOT,
+	ACPI_DBGP,
 	ACPI_DSDT,
-	ACPI_PM1_ENABLE,
-	ACPI_GPE_ENABLE,
-	ACPI_GPE_LEVEL,
-	ACPI_EVENT,
-	ACPI_P_BLK,
-	ACPI_ENTER_LVL2_LAT,
-	ACPI_ENTER_LVL3_LAT,
-	ACPI_P_LVL2_LAT,
-	ACPI_P_LVL3_LAT,
-	ACPI_C1_TIME,
-	ACPI_C2_TIME,
-	ACPI_C3_TIME,
-	ACPI_C1_COUNT,
-	ACPI_C2_COUNT,
-	ACPI_C3_COUNT,
-	ACPI_S0_SLP_TYP,
-	ACPI_S1_SLP_TYP,
-	ACPI_S5_SLP_TYP,
-	ACPI_SLEEP,
+	ACPI_ECDT,
+	ACPI_ETDT,
+	ACPI_FACP,
 	ACPI_FACS,
-	ACPI_XSDT,
-	ACPI_PMTIMER,
-	ACPI_BATT,
+	ACPI_OEMX,
+	ACPI_PSDT,
+	ACPI_SBST,
+	ACPI_SLIT,
+	ACPI_SPCR,
+	ACPI_SRAT,
+	ACPI_SSDT,
+	ACPI_SPMI,
+	ACPI_TABLE_COUNT
 };
 
-#define ACPI_SLP_TYP_DISABLED	(~0UL)
+typedef int (*acpi_table_handler) (unsigned long phys_addr, unsigned long size);
 
-#ifdef __KERNEL__
+extern acpi_table_handler acpi_table_ops[ACPI_TABLE_COUNT];
 
-/* routines for saving/restoring kernel state */
-FASTCALL(extern unsigned long acpi_save_state_mem(unsigned long return_point));
-FASTCALL(extern int acpi_save_state_disk(unsigned long return_point));
-extern void acpi_restore_state(void);
+typedef int (*acpi_madt_entry_handler) (acpi_table_entry_header *header);
 
-extern unsigned long acpi_wakeup_address;
+struct acpi_boot_flags {
+	u8		madt:1;
+	u8		reserved:7;
+};
 
-#endif /* __KERNEL__ */
+int acpi_table_init (char *cmdline);
+int acpi_table_parse (enum acpi_table_id, acpi_table_handler);
+int acpi_table_parse_madt (enum acpi_table_id, acpi_madt_entry_handler);
+void acpi_table_print (struct acpi_table_header *, unsigned long);
+void acpi_table_print_madt_entry (acpi_table_entry_header *);
+
+#endif /*CONFIG_ACPI_BOOT*/
+
+
+/* --------------------------------------------------------------------------
+                           PCI Interrupt Routing (PRT)
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_ACPI_PCI
+
+#define ACPI_PCI_ROUTING_PIC	0
+#define ACPI_PCI_ROUTING_IOAPIC 1
+#define ACPI_PCI_ROUTING_IOSAPIC 2
+
+struct acpi_prt_entry {
+	struct list_head	node;
+	struct {
+		u8			seg;
+		u8			bus;
+		u8			dev;
+		u8			pin;
+	}			id;
+	struct {
+		acpi_handle		handle;
+		u32			index;
+	}			source;
+};
+
+struct acpi_prt_list {
+	int			count;
+	struct list_head	entries;
+};
+
+extern struct acpi_prt_list	acpi_prts;
+
+struct pci_dev;
+
+int acpi_prt_get_irq (struct pci_dev *dev, u8 pin, int *irq);
+int acpi_prt_set_irq (struct pci_dev *dev, u8 pin, int irq);
+
+#endif /*CONFIG_ACPI_PCI*/
+
+
+/* --------------------------------------------------------------------------
+                            ACPI Interpreter (Core)
+   -------------------------------------------------------------------------- */
+
+#ifdef CONFIG_ACPI_INTERPRETER
 
 int acpi_init(void);
 
-#endif /* _LINUX_ACPI_H */
+#endif /*CONFIG_ACPI_INTERPRETER*/
+
+
+#endif /*_LINUX_ACPI_H*/
diff -Nru a/include/linux/cramfs_fs_sb.h b/include/linux/cramfs_fs_sb.h
--- a/include/linux/cramfs_fs_sb.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/cramfs_fs_sb.h	Fri Mar 15 17:51:02 2002
@@ -12,4 +12,9 @@
 			unsigned long flags;
 };
 
+static inline struct cramfs_sb_info *CRAMFS_SB(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
+
 #endif
diff -Nru a/include/linux/dnotify.h b/include/linux/dnotify.h
--- a/include/linux/dnotify.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/dnotify.h	Fri Mar 15 17:51:01 2002
@@ -13,6 +13,7 @@
 						   see linux/fcntl.h */
 	int			dn_fd;
 	struct file *		dn_filp;
+	fl_owner_t		dn_owner;
 };
 
 #define DNOTIFY_MAGIC	0x444E4F54
diff -Nru a/include/linux/efs_fs.h b/include/linux/efs_fs.h
--- a/include/linux/efs_fs.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/efs_fs.h	Fri Mar 15 17:51:03 2002
@@ -29,6 +29,7 @@
 
 #include <linux/fs.h>
 #include <linux/efs_fs_i.h>
+#include <linux/efs_fs_sb.h>
 #include <linux/efs_dir.h>
 
 #ifndef MIN
@@ -42,7 +43,11 @@
 {
 	return list_entry(inode, struct efs_inode_info, vfs_inode);
 }
-#define SUPER_INFO(s)				&((s)->u.efs_sb)
+
+static inline struct efs_sb_info *SUPER_INFO(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
 
 extern struct inode_operations efs_dir_inode_operations;
 extern struct file_operations efs_dir_operations;
diff -Nru a/include/linux/ethtool.h b/include/linux/ethtool.h
--- a/include/linux/ethtool.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/ethtool.h	Fri Mar 15 17:51:02 2002
@@ -72,6 +72,144 @@
 	u32	len; /* in bytes */
 	u8	data[0];
 };
+
+/* for configuring coalescing parameters of chip */
+struct ethtool_coalesce {
+	u32	cmd;	/* ETHTOOL_{G,S}COALESCE */
+
+	/* How many usecs to delay an RX interrupt after
+	 * a packet arrives.  If 0, only rx_max_coalesced_frames
+	 * is used.
+	 */
+	u32	rx_coalesce_usecs;
+
+	/* How many packets to delay an RX interrupt after
+	 * a packet arrives.  If 0, only rx_coalesce_usecs is
+	 * used.  It is illegal to set both usecs and max frames
+	 * to zero as this would cause RX interrupts to never be
+	 * generated.
+	 */
+	u32	rx_max_coalesced_frames;
+
+	/* Same as above two parameters, except that these values
+	 * apply while an IRQ is being services by the host.  Not
+	 * all cards support this feature and the values are ignored
+	 * in that case.
+	 */
+	u32	rx_coalesce_usecs_irq;
+	u32	rx_max_coalesced_frames_irq;
+
+	/* How many usecs to delay a TX interrupt after
+	 * a packet is sent.  If 0, only tx_max_coalesced_frames
+	 * is used.
+	 */
+	u32	tx_coalesce_usecs;
+
+	/* How many packets to delay a TX interrupt after
+	 * a packet is sent.  If 0, only tx_coalesce_usecs is
+	 * used.  It is illegal to set both usecs and max frames
+	 * to zero as this would cause TX interrupts to never be
+	 * generated.
+	 */
+	u32	tx_max_coalesced_frames;
+
+	/* Same as above two parameters, except that these values
+	 * apply while an IRQ is being services by the host.  Not
+	 * all cards support this feature and the values are ignored
+	 * in that case.
+	 */
+	u32	tx_coalesce_usecs_irq;
+	u32	tx_max_coalesced_frames_irq;
+
+	/* How many usecs to delay in-memory statistics
+	 * block updates.  Some drivers do not have an in-memory
+	 * statistic block, and in such cases this value is ignored.
+	 * This value must not be zero.
+	 */
+	u32	stats_block_coalesce_usecs;
+
+	/* Adaptive RX/TX coalescing is an algorithm implemented by
+	 * some drivers to improve latency under low packet rates and
+	 * improve throughput under high packet rates.  Some drivers
+	 * only implement one of RX or TX adaptive coalescing.  Anything
+	 * not implemented by the driver causes these values to be
+	 * silently ignored.
+	 */
+	u32	use_adaptive_rx_coalesce;
+	u32	use_adaptive_tx_coalesce;
+
+	/* When the packet rate (measured in packets per second)
+	 * is below pkt_rate_low, the {rx,tx}_*_low parameters are
+	 * used.
+	 */
+	u32	pkt_rate_low;
+	u32	rx_coalesce_usecs_low;
+	u32	rx_max_coalesced_frames_low;
+	u32	tx_coalesce_usecs_low;
+	u32	tx_max_coalesced_frames_low;
+
+	/* When the packet rate is below pkt_rate_high but above
+	 * pkt_rate_low (both measured in packets per second) the
+	 * normal {rx,tx}_* coalescing parameters are used.
+	 */
+
+	/* When the packet rate is (measured in packets per second)
+	 * is above pkt_rate_high, the {rx,tx}_*_high parameters are
+	 * used.
+	 */
+	u32	pkt_rate_high;
+	u32	rx_coalesce_usecs_high;
+	u32	rx_max_coalesced_frames_high;
+	u32	tx_coalesce_usecs_high;
+	u32	tx_max_coalesced_frames_high;
+
+	/* How often to do adaptive coalescing packet rate sampling,
+	 * measured in seconds.  Must not be zero.
+	 */
+	u32	rate_sample_interval;
+};
+
+/* for configuring RX/TX ring parameters */
+struct ethtool_ringparam {
+	u32	cmd;	/* ETHTOOL_{G,S}RINGPARAM */
+
+	/* Read only attributes.  These indicate the maximum number
+	 * of pending RX/TX ring entries the driver will allow the
+	 * user to set.
+	 */
+	u32	rx_max_pending;
+	u32	rx_mini_max_pending;
+	u32	rx_jumbo_max_pending;
+	u32	tx_max_pending;
+
+	/* Values changeable by the user.  The valid values are
+	 * in the range 1 to the "*_max_pending" counterpart above.
+	 */
+	u32	rx_pending;
+	u32	rx_mini_pending;
+	u32	rx_jumbo_pending;
+	u32	tx_pending;
+};
+
+/* for configuring link flow control parameters */
+struct ethtool_pauseparam {
+	u32	cmd;	/* ETHTOOL_{G,S}PAUSEPARAM */
+
+	/* If the link is being auto-negotiated (via ethtool_cmd.autoneg
+	 * being true) the user may set 'autonet' here non-zero to have the
+	 * pause parameters be auto-negotiated too.  In such a case, the
+	 * {rx,tx}_pause values below determine what capabilities are
+	 * advertised.
+	 *
+	 * If 'autoneg' is zero or the link is not being auto-negotiated,
+	 * then {rx,tx}_pause force the driver to use/not-use pause
+	 * flow control.
+	 */
+	u32	autoneg;
+	u32	rx_pause;
+	u32	tx_pause;
+};
+
 /* CMDs currently supported */
 #define ETHTOOL_GSET		0x00000001 /* Get settings. */
 #define ETHTOOL_SSET		0x00000002 /* Set settings, privileged. */
@@ -82,9 +220,23 @@
 #define ETHTOOL_GMSGLVL		0x00000007 /* Get driver message level */
 #define ETHTOOL_SMSGLVL		0x00000008 /* Set driver msg level, priv. */
 #define ETHTOOL_NWAY_RST	0x00000009 /* Restart autonegotiation, priv. */
-#define ETHTOOL_GLINK		0x0000000a /* Get link status */
+#define ETHTOOL_GLINK		0x0000000a /* Get link status (ethtool_value) */
 #define ETHTOOL_GEEPROM		0x0000000b /* Get EEPROM data */
 #define ETHTOOL_SEEPROM		0x0000000c /* Set EEPROM data */
+#define ETHTOOL_GCOALESCE	0x0000000e /* Get coalesce config */
+#define ETHTOOL_SCOALESCE	0x0000000f /* Set coalesce config */
+#define ETHTOOL_GRINGPARAM	0x00000010 /* Get ring parameters */
+#define ETHTOOL_SRINGPARAM	0x00000011 /* Set ring parameters */
+#define ETHTOOL_GPAUSEPARAM	0x00000012 /* Get pause parameters */
+#define ETHTOOL_SPAUSEPARAM	0x00000013 /* Set pause parameters */
+#define ETHTOOL_GRXCSUM		0x00000014 /* Get RX hw csum enable (ethtool_value) */
+#define ETHTOOL_SRXCSUM		0x00000015 /* Set RX hw csum enable (ethtool_value) */
+#define ETHTOOL_GTXCSUM		0x00000016 /* Get TX hw csum enable (ethtool_value) */
+#define ETHTOOL_STXCSUM		0x00000017 /* Set TX hw csum enable (ethtool_value) */
+#define ETHTOOL_GSG		0x00000018 /* Get scatter-gather enable
+					    * (ethtool_value) */
+#define ETHTOOL_SSG		0x00000019 /* Set scatter-gather enable
+					    * (ethtool_value) */
 
 /* compatibility with older code */
 #define SPARC_ETH_GSET		ETHTOOL_GSET
diff -Nru a/include/linux/ext2_fs.h b/include/linux/ext2_fs.h
--- a/include/linux/ext2_fs.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/ext2_fs.h	Fri Mar 15 17:51:01 2002
@@ -17,6 +17,7 @@
 #define _LINUX_EXT2_FS_H
 
 #include <linux/types.h>
+#include <linux/ext2_fs_sb.h>
 
 /*
  * The second extended filesystem constants/structures
@@ -70,6 +71,18 @@
  */
 #define EXT2_SUPER_MAGIC	0xEF53
 
+#ifdef __KERNEL__
+static inline struct ext2_sb_info *EXT2_SB(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
+#else
+/* Assume that user mode programs are passing in an ext2fs superblock, not
+ * a kernel struct super_block.  This will allow us to call the feature-test
+ * macros from user land. */
+#define EXT2_SB(sb)	(sb)
+#endif
+
 /*
  * Maximal count of links to a file
  */
@@ -94,9 +107,9 @@
 # define EXT2_BLOCK_SIZE_BITS(s)	((s)->s_log_block_size + 10)
 #endif
 #ifdef __KERNEL__
-#define	EXT2_ADDR_PER_BLOCK_BITS(s)	((s)->u.ext2_sb.s_addr_per_block_bits)
-#define EXT2_INODE_SIZE(s)		((s)->u.ext2_sb.s_inode_size)
-#define EXT2_FIRST_INO(s)		((s)->u.ext2_sb.s_first_ino)
+#define	EXT2_ADDR_PER_BLOCK_BITS(s)	(EXT2_SB(s)->s_addr_per_block_bits)
+#define EXT2_INODE_SIZE(s)		(EXT2_SB(s)->s_inode_size)
+#define EXT2_FIRST_INO(s)		(EXT2_SB(s)->s_first_ino)
 #else
 #define EXT2_INODE_SIZE(s)	(((s)->s_rev_level == EXT2_GOOD_OLD_REV) ? \
 				 EXT2_GOOD_OLD_INODE_SIZE : \
@@ -113,8 +126,8 @@
 #define	EXT2_MAX_FRAG_SIZE		4096
 #define EXT2_MIN_FRAG_LOG_SIZE		  10
 #ifdef __KERNEL__
-# define EXT2_FRAG_SIZE(s)		((s)->u.ext2_sb.s_frag_size)
-# define EXT2_FRAGS_PER_BLOCK(s)	((s)->u.ext2_sb.s_frags_per_block)
+# define EXT2_FRAG_SIZE(s)		(EXT2_SB(s)->s_frag_size)
+# define EXT2_FRAGS_PER_BLOCK(s)	(EXT2_SB(s)->s_frags_per_block)
 #else
 # define EXT2_FRAG_SIZE(s)		(EXT2_MIN_FRAG_SIZE << (s)->s_log_frag_size)
 # define EXT2_FRAGS_PER_BLOCK(s)	(EXT2_BLOCK_SIZE(s) / EXT2_FRAG_SIZE(s))
@@ -161,10 +174,10 @@
  * Macro-instructions used to manage group descriptors
  */
 #ifdef __KERNEL__
-# define EXT2_BLOCKS_PER_GROUP(s)	((s)->u.ext2_sb.s_blocks_per_group)
-# define EXT2_DESC_PER_BLOCK(s)		((s)->u.ext2_sb.s_desc_per_block)
-# define EXT2_INODES_PER_GROUP(s)	((s)->u.ext2_sb.s_inodes_per_group)
-# define EXT2_DESC_PER_BLOCK_BITS(s)	((s)->u.ext2_sb.s_desc_per_block_bits)
+# define EXT2_BLOCKS_PER_GROUP(s)	(EXT2_SB(s)->s_blocks_per_group)
+# define EXT2_DESC_PER_BLOCK(s)		(EXT2_SB(s)->s_desc_per_block)
+# define EXT2_INODES_PER_GROUP(s)	(EXT2_SB(s)->s_inodes_per_group)
+# define EXT2_DESC_PER_BLOCK_BITS(s)	(EXT2_SB(s)->s_desc_per_block_bits)
 #else
 # define EXT2_BLOCKS_PER_GROUP(s)	((s)->s_blocks_per_group)
 # define EXT2_DESC_PER_BLOCK(s)		(EXT2_BLOCK_SIZE(s) / sizeof (struct ext2_group_desc))
@@ -317,7 +330,7 @@
 
 #define clear_opt(o, opt)		o &= ~EXT2_MOUNT_##opt
 #define set_opt(o, opt)			o |= EXT2_MOUNT_##opt
-#define test_opt(sb, opt)		((sb)->u.ext2_sb.s_mount_opt & \
+#define test_opt(sb, opt)		(EXT2_SB(sb)->s_mount_opt & \
 					 EXT2_MOUNT_##opt)
 /*
  * Maximal mount counts between two filesystem checks
@@ -394,15 +407,6 @@
 	__u16	s_padding1;
 	__u32	s_reserved[204];	/* Padding to the end of the block */
 };
-
-#ifdef __KERNEL__
-#define EXT2_SB(sb)	(&((sb)->u.ext2_sb))
-#else
-/* Assume that user mode programs are passing in an ext2fs superblock, not
- * a kernel struct super_block.  This will allow us to call the feature-test
- * macros from user land. */
-#define EXT2_SB(sb)	(sb)
-#endif
 
 /*
  * Codes for operating systems
diff -Nru a/include/linux/fs.h b/include/linux/fs.h
--- a/include/linux/fs.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/fs.h	Fri Mar 15 17:51:02 2002
@@ -92,7 +92,6 @@
 			   * FS_NO_DCACHE is not set.
 			   */
 #define FS_NOMOUNT	16 /* Never mount from userland */
-#define FS_LITTER	32 /* Keeps the tree in dcache */
 #define FS_ODD_RENAME	32768	/* Temporary stuff; will go away as soon
 				  * as nfs_rename() will be cleaned up
 				  */
@@ -290,8 +289,6 @@
 
 #include <linux/pipe_fs_i.h>
 /* #include <linux/umsdos_fs_i.h> */
-#include <linux/romfs_fs_i.h>
-#include <linux/cramfs_fs_sb.h>
 
 /*
  * Attribute flags.  These should be or-ed together to figure out what
@@ -455,8 +452,6 @@
 	unsigned int		i_attr_flags;
 	__u32			i_generation;
 	union {
-		/* struct umsdos_inode_info	umsdos_i; */
-		struct romfs_inode_info		romfs_i;
 		void				*generic_ip;
 	} u;
 };
@@ -650,28 +645,19 @@
 #define MNT_FORCE	0x00000001	/* Attempt to forcibily umount */
 #define MNT_DETACH	0x00000002	/* Just detach from the tree */
 
-#include <linux/minix_fs_sb.h>
-#include <linux/ext2_fs_sb.h>
 #include <linux/ext3_fs_sb.h>
 #include <linux/hpfs_fs_sb.h>
 #include <linux/ntfs_fs_sb.h>
-#include <linux/msdos_fs_sb.h>
 #include <linux/iso_fs_sb.h>
-#include <linux/nfs_fs_sb.h>
 #include <linux/sysv_fs_sb.h>
 #include <linux/affs_fs_sb.h>
 #include <linux/ufs_fs_sb.h>
-#include <linux/efs_fs_sb.h>
 #include <linux/romfs_fs_sb.h>
-#include <linux/smb_fs_sb.h>
 #include <linux/hfs_fs_sb.h>
 #include <linux/adfs_fs_sb.h>
-#include <linux/qnx4_fs_sb.h>
 #include <linux/reiserfs_fs_sb.h>
 #include <linux/bfs_fs_sb.h>
 #include <linux/udf_fs_sb.h>
-#include <linux/ncp_fs_sb.h>
-#include <linux/cramfs_fs_sb.h>
 #include <linux/jffs2_fs_sb.h>
 
 extern struct list_head super_blocks;
@@ -708,30 +694,21 @@
 	char s_id[32];				/* Informational name */
 
 	union {
-		struct minix_sb_info	minix_sb;
-		struct ext2_sb_info	ext2_sb;
 		struct ext3_sb_info	ext3_sb;
 		struct hpfs_sb_info	hpfs_sb;
 		struct ntfs_sb_info	ntfs_sb;
-		struct msdos_sb_info	msdos_sb;
 		struct isofs_sb_info	isofs_sb;
-		struct nfs_sb_info	nfs_sb;
 		struct sysv_sb_info	sysv_sb;
 		struct affs_sb_info	affs_sb;
 		struct ufs_sb_info	ufs_sb;
-		struct efs_sb_info	efs_sb;
 		struct shmem_sb_info	shmem_sb;
 		struct romfs_sb_info	romfs_sb;
-		struct smb_sb_info	smbfs_sb;
 		struct hfs_sb_info	hfs_sb;
 		struct adfs_sb_info	adfs_sb;
-		struct qnx4_sb_info	qnx4_sb;
 		struct reiserfs_sb_info	reiserfs_sb;
 		struct bfs_sb_info	bfs_sb;
 		struct udf_sb_info	udf_sb;
-		struct ncp_sb_info	ncpfs_sb;
 		struct jffs2_sb_info	jffs2_sb;
-		struct cramfs_sb_info	cramfs_sb;
 		void			*generic_sbp;
 	} u;
 	/*
@@ -944,6 +921,7 @@
 	const char *name;
 	int fs_flags;
 	struct super_block *(*get_sb) (struct file_system_type *, int, char *, void *);
+	void (*kill_sb) (struct super_block *);
 	struct module *owner;
 	struct file_system_type * next;
 	struct list_head fs_supers;
@@ -958,6 +936,15 @@
 struct super_block *get_sb_nodev(struct file_system_type *fs_type,
 	int flags, void *data,
 	int (*fill_super)(struct super_block *, void *, int));
+void kill_block_super(struct super_block *sb);
+void kill_anon_super(struct super_block *sb);
+void kill_litter_super(struct super_block *sb);
+void deactivate_super(struct super_block *sb);
+int set_anon_super(struct super_block *s, void *data);
+struct super_block *sget(struct file_system_type *type,
+			int (*test)(struct super_block *,void *),
+			int (*set)(struct super_block *,void *),
+			void *data);
 
 /* Alas, no aliases. Too much hassle with bringing module.h everywhere */
 #define fops_get(fops) \
@@ -1463,7 +1450,6 @@
 extern loff_t no_llseek(struct file *file, loff_t offset, int origin);
 extern loff_t generic_file_llseek(struct file *file, loff_t offset, int origin);
 extern loff_t remote_llseek(struct file *file, loff_t offset, int origin);
-extern ssize_t generic_read_dir(struct file *, char *, size_t, loff_t *);
 extern int generic_file_open(struct inode * inode, struct file * filp);
 
 extern struct file_operations generic_ro_fops;
@@ -1475,7 +1461,6 @@
 extern struct inode_operations page_symlink_inode_operations;
 
 extern int vfs_readdir(struct file *, filldir_t, void *);
-extern int dcache_readdir(struct file *, void *, filldir_t);
 
 extern int vfs_stat(char *, struct kstat *);
 extern int vfs_lstat(char *, struct kstat *);
@@ -1487,6 +1472,12 @@
 extern kdev_t ROOT_DEV;
 extern char root_device_name[];
 
+extern int dcache_readdir(struct file *, void *, filldir_t);
+extern int simple_statfs(struct super_block *, struct statfs *);
+extern struct dentry *simple_lookup(struct inode *, struct dentry *);
+extern ssize_t generic_read_dir(struct file *, char *, size_t, loff_t *);
+extern struct file_operations simple_dir_operations;
+extern struct inode_operations simple_dir_inode_operations;
 
 extern void show_buffers(void);
 
diff -Nru a/include/linux/futex.h b/include/linux/futex.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/linux/futex.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,8 @@
+#ifndef _LINUX_FUTEX_H
+#define _LINUX_FUTEX_H
+
+/* Second argument to futex syscall */
+#define FUTEX_UP (0)
+#define FUTEX_DOWN (1)
+
+#endif
diff -Nru a/include/linux/hash.h b/include/linux/hash.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/linux/hash.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,58 @@
+#ifndef _LINUX_HASH_H
+#define _LINUX_HASH_H
+/* Fast hashing routine for a long.
+   (C) 2002 William Lee Irwin III, IBM */
+
+/*
+ * Knuth recommends primes in approximately golden ratio to the maximum
+ * integer representable by a machine word for multiplicative hashing.
+ * Chuck Lever verified the effectiveness of this technique:
+ * http://www.citi.umich.edu/techreports/reports/citi-tr-00-1.pdf
+ *
+ * These primes are chosen to be bit-sparse, that is operations on
+ * them can use shifts and additions instead of multiplications for
+ * machines where multiplications are slow.
+ */
+#if BITS_PER_LONG == 32
+/* 2^31 + 2^29 - 2^25 + 2^22 - 2^19 - 2^16 + 1 */
+#define GOLDEN_RATIO_PRIME 0x9e370001UL
+#elif BITS_PER_LONG == 64
+/*  2^63 + 2^61 - 2^57 + 2^54 - 2^51 - 2^18 + 1 */
+#define GOLDEN_RATIO_PRIME 0x9e37fffffffc0001UL
+#else
+#error Define GOLDEN_RATIO_PRIME for your wordsize.
+#endif
+
+static inline unsigned long hash_long(unsigned long val, unsigned int bits)
+{
+	unsigned long hash = val;
+
+#if BITS_PER_LONG == 64
+	/*  Sigh, gcc can't optimise this alone like it does for 32 bits. */
+	unsigned long n = hash;
+	n <<= 18;
+	hash -= n;
+	n <<= 33;
+	hash -= n;
+	n <<= 3;
+	hash += n;
+	n <<= 3;
+	hash -= n;
+	n <<= 4;
+	hash += n;
+	n <<= 2;
+	hash += n;
+#else
+	/* On some cpus multiply is faster, on others gcc will do shifts */
+	hash *= GOLDEN_RATIO_PRIME;
+#endif
+
+	/* High bits are more random, so use them. */
+	return hash >> (BITS_PER_LONG - bits);
+}
+	
+static inline unsigned long hash_ptr(void *ptr, unsigned int bits)
+{
+	return hash_long((unsigned long)ptr, bits);
+}
+#endif /* _LINUX_HASH_H */
diff -Nru a/include/linux/hdreg.h b/include/linux/hdreg.h
--- a/include/linux/hdreg.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/hdreg.h	Fri Mar 15 17:51:03 2002
@@ -354,7 +354,6 @@
 
 #define HDIO_GET_BUSSTATE	0x031a	/* get the bus state of the hwif */
 #define HDIO_TRISTATE_HWIF	0x031b	/* execute a channel tristate */
-#define HDIO_DRIVE_RESET	0x031c	/* execute a device reset */
 #define HDIO_DRIVE_TASK		0x031e	/* execute task and special drive command */
 #define HDIO_DRIVE_CMD		0x031f	/* execute a special drive command */
 
@@ -368,9 +367,7 @@
 #define HDIO_SET_NOWERR		0x0325	/* change ignore-write-error flag */
 #define HDIO_SET_DMA		0x0326	/* change use-dma flag */
 #define HDIO_SET_PIO_MODE	0x0327	/* reconfig interface to new speed */
-#define HDIO_SCAN_HWIF		0x0328	/* register and (re)scan interface */
 #define HDIO_SET_NICE		0x0329	/* set nice flags */
-#define HDIO_UNREGISTER_HWIF	0x032a  /* unregister interface */
 #define HDIO_SET_WCACHE		0x032b	/* change write cache enable-disable */
 #define HDIO_SET_ACOUSTIC	0x032c	/* change acoustic behavior */
 #define HDIO_SET_BUSSTATE	0x032d	/* set the bus state of the hwif */
@@ -644,18 +641,5 @@
 #define IDE_NICE_0		(2)	/* when sure that it won't affect us */
 #define IDE_NICE_1		(3)	/* when probably won't affect us much */
 #define IDE_NICE_2		(4)	/* when we know it's on our expense */
-
-#ifdef __KERNEL__
-/*
- * These routines are used for kernel command line parameters from main.c:
- */
-#include <linux/config.h>
-
-#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
-int ide_register(int io_port, int ctl_port, int irq);
-void ide_unregister(unsigned int);
-#endif /* CONFIG_BLK_DEV_IDE || CONFIG_BLK_DEV_IDE_MODULE */
-
-#endif  /* __KERNEL__ */
 
 #endif	/* _LINUX_HDREG_H */
diff -Nru a/include/linux/ide.h b/include/linux/ide.h
--- a/include/linux/ide.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/ide.h	Fri Mar 15 17:51:01 2002
@@ -240,11 +240,6 @@
 } hw_regs_t;
 
 /*
- * Register new hardware with ide
- */
-int ide_register_hw(hw_regs_t *hw, struct hwif_s **hwifp);
-
-/*
  * Set up hw_regs_t structure before calling ide_register_hw (optional)
  */
 void ide_setup_ports(hw_regs_t *hw,
@@ -337,6 +332,7 @@
 	unsigned autotune	: 2;	/* 1=autotune, 2=noautotune, 0=default */
 	unsigned remap_0_to_1	: 2;	/* 0=remap if ezdrive, 1=remap, 2=noremap */
 	unsigned ata_flash	: 1;	/* 1=present, 0=default */
+	unsigned blocked        : 1;	/* 1=powermanagment told us not to do anything, so sleep nicely */
 	unsigned	addressing;	/* : 2; 0=28-bit, 1=48-bit, 2=64-bit */
 	byte		scsi;		/* 0=default, 1=skip current ide-subdriver for ide-scsi emulation */
 	select_t	select;		/* basic drive/head select reg value */
@@ -507,6 +503,12 @@
 } ide_hwif_t;
 
 /*
+ * Register new hardware with ide
+ */
+extern int ide_register_hw(hw_regs_t *hw, struct hwif_s **hwifp);
+extern void ide_unregister(ide_hwif_t *hwif);
+
+/*
  * Status returned from various ide_ functions
  */
 typedef enum {
@@ -744,12 +746,6 @@
 ide_drive_t *get_info_ptr (kdev_t i_rdev);
 
 /*
- * Start a reset operation for an IDE interface.
- * The caller should return immediately after invoking this.
- */
-ide_startstop_t ide_do_reset (ide_drive_t *);
-
-/*
  * Re-Start an operation for an IDE interface.
  * The caller should return immediately after invoking this.
  */
@@ -951,7 +947,7 @@
 ide_startstop_t ide_dma_intr (ide_drive_t *drive);
 int check_drive_lists (ide_drive_t *drive, int good_bad);
 int ide_dmaproc (ide_dma_action_t func, ide_drive_t *drive);
-int ide_release_dma (ide_hwif_t *hwif);
+extern void ide_release_dma(ide_hwif_t *hwif);
 void ide_setup_dma (ide_hwif_t *hwif, unsigned long dmabase, unsigned int num_ports) __init;
 #endif
 
diff -Nru a/include/linux/if_ec.h b/include/linux/if_ec.h
--- a/include/linux/if_ec.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/if_ec.h	Fri Mar 15 17:51:01 2002
@@ -53,6 +53,7 @@
   unsigned char port;
   unsigned char station;
   unsigned char net;
+  unsigned short num;
 };
 
 #define ec_sk(__sk) ((struct econet_opt *)(__sk)->protinfo)
diff -Nru a/include/linux/if_pppox.h b/include/linux/if_pppox.h
--- a/include/linux/if_pppox.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/if_pppox.h	Fri Mar 15 17:51:01 2002
@@ -127,6 +127,7 @@
 	union {
 		struct pppoe_opt pppoe;
 	} proto;
+	unsigned short		num;
 };
 #define pppoe_dev	proto.pppoe.dev
 #define pppoe_pa	proto.pppoe.pa
diff -Nru a/include/linux/if_vlan.h b/include/linux/if_vlan.h
--- a/include/linux/if_vlan.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/if_vlan.h	Fri Mar 15 17:51:01 2002
@@ -52,70 +52,16 @@
    unsigned short       h_vlan_encapsulated_proto; /* packet type ID field (or len) */
 };
 
-/*  Find a VLAN device by the MAC address of it's Ethernet device, and
- *  it's VLAN ID.  The default configuration is to have VLAN's scope
- *  to be box-wide, so the MAC will be ignored.  The mac will only be
- *  looked at if we are configured to have a seperate set of VLANs per
- *  each MAC addressable interface.  Note that this latter option does
- *  NOT follow the spec for VLANs, but may be useful for doing very
- *  large quantities of VLAN MUX/DEMUX onto FrameRelay or ATM PVCs.
- */
-struct net_device *find_802_1Q_vlan_dev(struct net_device* real_dev,
-                                        unsigned short VID); /* vlan.c */
+#define VLAN_VID_MASK	0xfff
 
 /* found in af_inet.c */
 extern int (*vlan_ioctl_hook)(unsigned long arg);
 
-/* found in vlan_dev.c */
-struct net_device_stats* vlan_dev_get_stats(struct net_device* dev);
-int vlan_dev_rebuild_header(struct sk_buff *skb);
-int vlan_skb_recv(struct sk_buff *skb, struct net_device *dev,
-                  struct packet_type* ptype);
-int vlan_dev_hard_header(struct sk_buff *skb, struct net_device *dev,
-                         unsigned short type, void *daddr, void *saddr,
-                         unsigned len);
-int vlan_dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev);
-int vlan_dev_change_mtu(struct net_device *dev, int new_mtu);
-int vlan_dev_set_mac_address(struct net_device *dev, void* addr);
-int vlan_dev_open(struct net_device* dev);
-int vlan_dev_stop(struct net_device* dev);
-int vlan_dev_init(struct net_device* dev);
-void vlan_dev_destruct(struct net_device* dev);
-void vlan_dev_copy_and_sum(struct sk_buff *dest, unsigned char *src,
-                           int length, int base);
-int vlan_dev_set_ingress_priority(char* dev_name, __u32 skb_prio, short vlan_prio);
-int vlan_dev_set_egress_priority(char* dev_name, __u32 skb_prio, short vlan_prio);
-int vlan_dev_set_vlan_flag(char* dev_name, __u32 flag, short flag_val);
-
-/* VLAN multicast stuff */
-/* Delete all of the MC list entries from this vlan device.  Also deals
- * with the underlying device...
- */
-void vlan_flush_mc_list(struct net_device* dev);
-/* copy the mc_list into the vlan_info structure. */
-void vlan_copy_mc_list(struct dev_mc_list* mc_list, struct vlan_dev_info* vlan_info);
-/** dmi is a single entry into a dev_mc_list, a single node.  mc_list is
- *  an entire list, and we'll iterate through it.
- */
-int vlan_should_add_mc(struct dev_mc_list *dmi, struct dev_mc_list *mc_list);
-/** Taken from Gleb + Lennert's VLAN code, and modified... */
-void vlan_dev_set_multicast_list(struct net_device *vlan_dev);
-
-int vlan_collection_add_vlan(struct vlan_collection* vc, unsigned short vlan_id,
-                             unsigned short flags);
-int vlan_collection_remove_vlan(struct vlan_collection* vc,
-                                struct net_device* vlan_dev);
-int vlan_collection_remove_vlan_id(struct vlan_collection* vc, unsigned short vlan_id);
-
-/* found in vlan.c */
-/* Our listing of VLAN group(s) */
-extern struct vlan_group* p802_1Q_vlan_list;
-
 #define VLAN_NAME "vlan"
 
 /* if this changes, algorithm will have to be reworked because this
  * depends on completely exhausting the VLAN identifier space.  Thus
- * it gives constant time look-up, but it many cases it wastes memory.
+ * it gives constant time look-up, but in many cases it wastes memory.
  */
 #define VLAN_GROUP_ARRAY_LEN 4096
 
@@ -170,56 +116,73 @@
 
 /* inline functions */
 
-/* Used in vlan_skb_recv */
-static inline struct sk_buff *vlan_check_reorder_header(struct sk_buff *skb)
+static inline struct net_device_stats *vlan_dev_get_stats(struct net_device *dev)
 {
-	if (VLAN_DEV_INFO(skb->dev)->flags & 1) {
-		skb = skb_share_check(skb, GFP_ATOMIC);
-		if (skb) {
-			/* Lifted from Gleb's VLAN code... */
-			memmove(skb->data - ETH_HLEN,
-				skb->data - VLAN_ETH_HLEN, 12);
-			skb->mac.raw += VLAN_HLEN;
-		}
-	}
-
-	return skb;
+	return &(VLAN_DEV_INFO(dev)->dev_stats);
 }
 
-static inline unsigned short vlan_dev_get_egress_qos_mask(struct net_device* dev,
-							  struct sk_buff* skb)
+static inline __u32 vlan_get_ingress_priority(struct net_device *dev,
+					      unsigned short vlan_tag)
 {
-	struct vlan_priority_tci_mapping *mp =
-		VLAN_DEV_INFO(dev)->egress_priority_map[(skb->priority & 0xF)];
+	struct vlan_dev_info *vip = VLAN_DEV_INFO(dev);
 
-	while (mp) {
-		if (mp->priority == skb->priority) {
-			return mp->vlan_qos; /* This should already be shifted to mask
-					      * correctly with the VLAN's TCI
-					      */
-		}
-		mp = mp->next;
-	}
-	return 0;
+	return vip->ingress_priority_map[(vlan_tag >> 13) & 0x7];
 }
 
-static inline int vlan_dmi_equals(struct dev_mc_list *dmi1,
-                                  struct dev_mc_list *dmi2)
-{
-	return ((dmi1->dmi_addrlen == dmi2->dmi_addrlen) &&
-		(memcmp(dmi1->dmi_addr, dmi2->dmi_addr, dmi1->dmi_addrlen) == 0));
-}
+/* VLAN tx hw acceleration helpers. */
+struct vlan_skb_tx_cookie {
+	u32	magic;
+	u32	vlan_tag;
+};
 
-static inline void vlan_destroy_mc_list(struct dev_mc_list *mc_list)
+#define VLAN_TX_COOKIE_MAGIC	0x564c414e	/* "VLAN" in ascii. */
+#define VLAN_TX_SKB_CB(__skb)	((struct vlan_skb_tx_cookie *)&((__skb)->cb[0]))
+#define vlan_tx_tag_present(__skb) \
+	(VLAN_TX_SKB_CB(__skb)->magic == VLAN_TX_COOKIE_MAGIC)
+#define vlan_tx_tag_get(__skb)	(VLAN_TX_SKB_CB(__skb)->vlan_tag)
+
+/* VLAN rx hw acceleration helper.  This acts like netif_rx().  */
+static inline int vlan_hwaccel_rx(struct sk_buff *skb, struct vlan_group *grp,
+				  unsigned short vlan_tag)
 {
-	struct dev_mc_list *dmi = mc_list;
-	struct dev_mc_list *next;
+	struct net_device_stats *stats;
 
-	while(dmi) {
-		next = dmi->next;
-		kfree(dmi);
-		dmi = next;
+	skb->dev = grp->vlan_devices[vlan_tag & VLAN_VID_MASK];
+	if (skb->dev == NULL) {
+		kfree_skb(skb);
+
+		/* Not NET_RX_DROP, this is not being dropped
+		 * due to congestion.
+		 */
+		return 0;
 	}
+
+	skb->dev->last_rx = jiffies;
+
+	stats = vlan_dev_get_stats(skb->dev);
+	stats->rx_packets++;
+	stats->rx_bytes += skb->len;
+
+	skb->priority = vlan_get_ingress_priority(skb->dev, vlan_tag);
+	switch (skb->pkt_type) {
+	case PACKET_BROADCAST:
+		break;
+
+	case PACKET_MULTICAST:
+		stats->multicast++;
+		break;
+
+	case PACKET_OTHERHOST:
+		/* Our lower layer thinks this is not local, let's make sure.
+		 * This allows the VLAN to have a different MAC than the underlying
+		 * device, and still route correctly.
+		 */
+		if (!memcmp(skb->mac.ethernet->h_dest, skb->dev->dev_addr, ETH_ALEN))
+			skb->pkt_type = PACKET_HOST;
+		break;
+	};
+
+	return netif_rx(skb);
 }
 
 #endif /* __KERNEL__ */
diff -Nru a/include/linux/init_task.h b/include/linux/init_task.h
--- a/include/linux/init_task.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/init_task.h	Fri Mar 15 17:51:01 2002
@@ -53,10 +53,11 @@
     active_mm:		&init_mm,					\
     run_list:		LIST_HEAD_INIT(tsk.run_list),			\
     time_slice:		HZ,						\
-    next_task:		&tsk,						\
-    prev_task:		&tsk,						\
-    p_opptr:		&tsk,						\
-    p_pptr:		&tsk,						\
+    tasks:		LIST_HEAD_INIT(tsk.tasks),			\
+    real_parent:	&tsk,						\
+    parent:		&tsk,						\
+    children:		LIST_HEAD_INIT(tsk.children),			\
+    sibling:		LIST_HEAD_INIT(tsk.sibling),			\
     thread_group:	LIST_HEAD_INIT(tsk.thread_group),		\
     wait_chldexit:	__WAIT_QUEUE_HEAD_INITIALIZER(tsk.wait_chldexit),\
     real_timer:		{						\
diff -Nru a/include/linux/ip.h b/include/linux/ip.h
--- a/include/linux/ip.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/ip.h	Fri Mar 15 17:51:02 2002
@@ -116,17 +116,24 @@
 #define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
 
 struct inet_opt {
+	/* Socket demultiplex comparisons on incoming packets. */
+	__u32			daddr;		/* Foreign IPv4 addr */
+	__u32			rcv_saddr;	/* Bound local IPv4 addr */
+	__u16			dport;		/* Destination port */
+	__u16			num;		/* Local port */
+	__u32			saddr;		/* Sending source */
 	int			ttl;		/* TTL setting */
 	int			tos;		/* TOS */
 	unsigned	   	cmsg_flags;
 	struct ip_options	*opt;
+	__u16			sport;		/* Source port */
 	unsigned char		hdrincl;	/* Include headers ? */
 	__u8			mc_ttl;		/* Multicasting TTL */
 	__u8			mc_loop;	/* Loopback */
+	__u8			pmtudisc;
+	__u16			id;		/* ID counter for DF pkts */
 	unsigned		recverr : 1,
 				freebind : 1;
-	__u16			id;		/* ID counter for DF pkts */
-	__u8			pmtudisc;
 	int			mc_index;	/* Multicast device index */
 	__u32			mc_addr;
 	struct ip_mc_socklist	*mc_list;	/* Group array */
diff -Nru a/include/linux/jffs2.h b/include/linux/jffs2.h
--- a/include/linux/jffs2.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/jffs2.h	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
  * JFFS2 -- Journalling Flash File System, Version 2.
  *
- * Copyright (C) 2001 Red Hat, Inc.
+ * Copyright (C) 2001, 2002 Red Hat, Inc.
  *
  * Created by David Woodhouse <dwmw2@cambridge.redhat.com>
  *
@@ -31,14 +31,13 @@
  * provisions above, a recipient may use your version of this file
  * under either the RHEPL or the GPL.
  *
- * $Id: jffs2.h,v 1.19 2001/10/09 13:20:23 dwmw2 Exp $
+ * $Id: jffs2.h,v 1.23 2002/02/21 17:03:45 dwmw2 Exp $
  *
  */
 
 #ifndef __LINUX_JFFS2_H__
 #define __LINUX_JFFS2_H__
 
-#include <asm/types.h>
 #define JFFS2_SUPER_MAGIC 0x72b6
 
 /* Values we may expect to find in the 'magic' field */
@@ -78,16 +77,12 @@
 #define JFFS2_NODETYPE_DIRENT (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 1)
 #define JFFS2_NODETYPE_INODE (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 2)
 #define JFFS2_NODETYPE_CLEANMARKER (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
+#define JFFS2_NODETYPE_PADDING (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 4)
 
 // Maybe later...
 //#define JFFS2_NODETYPE_CHECKPOINT (JFFS2_FEATURE_RWCOMPAT_DELETE | JFFS2_NODE_ACCURATE | 3)
 //#define JFFS2_NODETYPE_OPTIONS (JFFS2_FEATURE_RWCOMPAT_COPY | JFFS2_NODE_ACCURATE | 4)
 
-/* Same as the non_ECC versions, but with extra space for real 
- * ECC instead of just the checksum. For use on NAND flash 
- */
-//#define JFFS2_NODETYPE_DIRENT_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 5)
-//#define JFFS2_NODETYPE_INODE_ECC (JFFS2_FEATURE_INCOMPAT | JFFS2_NODE_ACCURATE | 6)
 
 #define JFFS2_INO_FLAG_PREREAD	  1	/* Do read_inode() for this one at 
 					   mount time, don't wait for it to 
@@ -99,28 +94,28 @@
 struct jffs2_unknown_node
 {
 	/* All start like this */
-	__u16 magic;
-	__u16 nodetype;
-	__u32 totlen; /* So we can skip over nodes we don't grok */
-	__u32 hdr_crc;
+	uint16_t magic;
+	uint16_t nodetype;
+	uint32_t totlen; /* So we can skip over nodes we don't grok */
+	uint32_t hdr_crc;
 } __attribute__((packed));
 
 struct jffs2_raw_dirent
 {
-	__u16 magic;
-	__u16 nodetype;	/* == JFFS_NODETYPE_DIRENT */
-	__u32 totlen;
-	__u32 hdr_crc;
-	__u32 pino;
-	__u32 version;
-	__u32 ino; /* == zero for unlink */
-	__u32 mctime;
-	__u8 nsize;
-	__u8 type;
-	__u8 unused[2];
-	__u32 node_crc;
-	__u32 name_crc;
-	__u8 name[0];
+	uint16_t magic;
+	uint16_t nodetype;	/* == JFFS_NODETYPE_DIRENT */
+	uint32_t totlen;
+	uint32_t hdr_crc;
+	uint32_t pino;
+	uint32_t version;
+	uint32_t ino; /* == zero for unlink */
+	uint32_t mctime;
+	uint8_t nsize;
+	uint8_t type;
+	uint8_t unused[2];
+	uint32_t node_crc;
+	uint32_t name_crc;
+	uint8_t name[0];
 } __attribute__((packed));
 
 /* The JFFS2 raw inode structure: Used for storage on physical media.  */
@@ -131,28 +126,28 @@
 */
 struct jffs2_raw_inode
 {
-	__u16 magic;      /* A constant magic number.  */
-	__u16 nodetype;   /* == JFFS_NODETYPE_INODE */
-	__u32 totlen;     /* Total length of this node (inc data, etc.) */
-	__u32 hdr_crc;
-	__u32 ino;        /* Inode number.  */
-	__u32 version;    /* Version number.  */
-	__u32 mode;       /* The file's type or mode.  */
-	__u16 uid;        /* The file's owner.  */
-	__u16 gid;        /* The file's group.  */
-	__u32 isize;      /* Total resultant size of this inode (used for truncations)  */
-	__u32 atime;      /* Last access time.  */
-	__u32 mtime;      /* Last modification time.  */
-	__u32 ctime;      /* Change time.  */
-	__u32 offset;     /* Where to begin to write.  */
-	__u32 csize;      /* (Compressed) data size */
-	__u32 dsize;	  /* Size of the node's data. (after decompression) */
-	__u8 compr;       /* Compression algorithm used */
-	__u8 usercompr;	  /* Compression algorithm requested by the user */
-	__u16 flags;	  /* See JFFS2_INO_FLAG_* */
-	__u32 data_crc;   /* CRC for the (compressed) data.  */
-	__u32 node_crc;   /* CRC for the raw inode (excluding data)  */
-//	__u8 data[dsize];
+	uint16_t magic;      /* A constant magic number.  */
+	uint16_t nodetype;   /* == JFFS_NODETYPE_INODE */
+	uint32_t totlen;     /* Total length of this node (inc data, etc.) */
+	uint32_t hdr_crc;
+	uint32_t ino;        /* Inode number.  */
+	uint32_t version;    /* Version number.  */
+	uint32_t mode;       /* The file's type or mode.  */
+	uint16_t uid;        /* The file's owner.  */
+	uint16_t gid;        /* The file's group.  */
+	uint32_t isize;      /* Total resultant size of this inode (used for truncations)  */
+	uint32_t atime;      /* Last access time.  */
+	uint32_t mtime;      /* Last modification time.  */
+	uint32_t ctime;      /* Change time.  */
+	uint32_t offset;     /* Where to begin to write.  */
+	uint32_t csize;      /* (Compressed) data size */
+	uint32_t dsize;	     /* Size of the node's data. (after decompression) */
+	uint8_t compr;       /* Compression algorithm used */
+	uint8_t usercompr;   /* Compression algorithm requested by the user */
+	uint16_t flags;	     /* See JFFS2_INO_FLAG_* */
+	uint32_t data_crc;   /* CRC for the (compressed) data.  */
+	uint32_t node_crc;   /* CRC for the raw inode (excluding data)  */
+//	uint8_t data[dsize];
 } __attribute__((packed));
 
 union jffs2_node_union {
diff -Nru a/include/linux/jffs2_fs_i.h b/include/linux/jffs2_fs_i.h
--- a/include/linux/jffs2_fs_i.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/jffs2_fs_i.h	Fri Mar 15 17:51:01 2002
@@ -1,22 +1,11 @@
-/* $Id: jffs2_fs_i.h,v 1.8 2001/04/18 13:05:28 dwmw2 Exp $ */
+/* $Id: jffs2_fs_i.h,v 1.12 2002/03/06 13:59:21 dwmw2 Exp $ */
 
 #ifndef _JFFS2_FS_I
 #define _JFFS2_FS_I
 
-/* Include the pipe_inode_info at the beginning so that we can still
-   use the storage space in the inode when we have a pipe inode.
-   This sucks.
-*/
-
-#undef THISSUCKS /* Only for 2.2 */
-#ifdef THISSUCKS
-#include <linux/pipe_fs_i.h>
-#endif
+#include <linux/version.h>
 
 struct jffs2_inode_info {
-#ifdef THISSUCKS
-        struct pipe_inode_info pipecrap;
-#endif
 	/* We need an internal semaphore similar to inode->i_sem.
 	   Unfortunately, we can't used the existing one, because
 	   either the GC would deadlock, or we'd have to release it
@@ -26,7 +15,7 @@
 	struct semaphore sem;
 
 	/* The highest (datanode) version number used for this ino */
-	__u32 highest_version;
+	uint32_t highest_version;
 
 	/* List of data fragments which make up the file */
 	struct jffs2_node_frag *fraglist;
@@ -44,23 +33,11 @@
 	/* Some stuff we just have to keep in-core at all times, for each inode. */
 	struct jffs2_inode_cache *inocache;
 
-	/* Keep a pointer to the last physical node in the list. We don't 
-	   use the doubly-linked lists because we don't want to increase
-	   the memory usage that much. This is simpler */
-	//	struct jffs2_raw_node_ref *lastnode;
-	__u16 flags;
-	__u8 usercompr;
+	uint16_t flags;
+	uint8_t usercompr;
+#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,2)
 	struct inode vfs_inode;
-};
-
-#ifdef JFFS2_OUT_OF_KERNEL
-#define JFFS2_INODE_INFO(i) ((struct jffs2_inode_info *) &(i)->u)
-#else
-static inline struct jffs2_inode_info *JFFS2_INODE_INFO(struct inode *inode)
-{
-	return list_entry(inode, struct jffs2_inode_info, vfs_inode);
-}
 #endif
+};
 
 #endif /* _JFFS2_FS_I */
-
diff -Nru a/include/linux/jffs2_fs_sb.h b/include/linux/jffs2_fs_sb.h
--- a/include/linux/jffs2_fs_sb.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/jffs2_fs_sb.h	Fri Mar 15 17:51:01 2002
@@ -1,4 +1,4 @@
-/* $Id: jffs2_fs_sb.h,v 1.16.2.1 2002/02/23 14:13:34 dwmw2 Exp $ */
+/* $Id: jffs2_fs_sb.h,v 1.25 2002/03/08 15:11:24 dwmw2 Exp $ */
 
 #ifndef _JFFS2_FS_SB
 #define _JFFS2_FS_SB
@@ -9,7 +9,7 @@
 #include <asm/semaphore.h>
 #include <linux/list.h>
 
-#define INOCACHE_HASHSIZE 1
+#define INOCACHE_HASHSIZE 14
 
 #define JFFS2_SB_FLAG_RO 1
 #define JFFS2_SB_FLAG_MOUNTING 2
@@ -21,36 +21,30 @@
 struct jffs2_sb_info {
 	struct mtd_info *mtd;
 
-	__u32 highest_ino;
+	uint32_t highest_ino;
 	unsigned int flags;
-	spinlock_t nodelist_lock;
 
-	//	pid_t thread_pid;		/* GC thread's PID */
 	struct task_struct *gc_task;	/* GC task struct */
 	struct semaphore gc_thread_start; /* GC thread start mutex */
 	struct completion gc_thread_exit; /* GC thread exit completion port */
-	//	__u32 gc_minfree_threshold;	/* GC trigger thresholds */
-	//	__u32 gc_maxdirty_threshold;
 
 	struct semaphore alloc_sem;	/* Used to protect all the following 
 					   fields, and also to protect against
 					   out-of-order writing of nodes.
 					   And GC.
 					*/
-	__u32 flash_size;
-	__u32 used_size;
-	__u32 dirty_size;
-	__u32 free_size;
-	__u32 erasing_size;
-	__u32 bad_size;
-	__u32 sector_size;
-	//	__u32 min_free_size;
-	//	__u32 max_chunk_size;
+	uint32_t flash_size;
+	uint32_t used_size;
+	uint32_t dirty_size;
+	uint32_t free_size;
+	uint32_t erasing_size;
+	uint32_t bad_size;
+	uint32_t sector_size;
 
-	__u32 nr_free_blocks;
-	__u32 nr_erasing_blocks;
+	uint32_t nr_free_blocks;
+	uint32_t nr_erasing_blocks;
 
-	__u32 nr_blocks;
+	uint32_t nr_blocks;
 	struct jffs2_eraseblock *blocks;	/* The whole array of blocks. Used for getting blocks 
 						 * from the offset (blocks[ofs / sector_size]) */
 	struct jffs2_eraseblock *nextblock;	/* The block we're currently filling */
@@ -59,8 +53,10 @@
 
 	struct list_head clean_list;		/* Blocks 100% full of clean data */
 	struct list_head dirty_list;		/* Blocks with some dirty space */
+	struct list_head erasable_list;		/* Blocks which are completely dirty, and need erasing */
+	struct list_head erasable_pending_wbuf_list;	/* Blocks which need erasing but only after the current wbuf is flushed */
 	struct list_head erasing_list;		/* Blocks which are currently erasing */
-	struct list_head erase_pending_list;	/* Blocks which need erasing */
+	struct list_head erase_pending_list;	/* Blocks which need erasing now */
 	struct list_head erase_complete_list;	/* Blocks which are erased and need the clean marker written to them */
 	struct list_head free_list;		/* Blocks which are free and ready to be used */
 	struct list_head bad_list;		/* Bad blocks. */
@@ -69,16 +65,22 @@
 	spinlock_t erase_completion_lock;	/* Protect free_list and erasing_list 
 						   against erase completion handler */
 	wait_queue_head_t erase_wait;		/* For waiting for erases to complete */
+
 	struct jffs2_inode_cache *inocache_list[INOCACHE_HASHSIZE];
 	spinlock_t inocache_lock;
+	/* This _really_ speeds up mounts. */
+	struct jffs2_inode_cache *inocache_last;
+	
+	/* Sem to allow jffs2_garbage_collect_deletion_dirent to
+	   drop the erase_completion_lock while it's holding a pointer 
+	   to an obsoleted node. I don't like this. Alternatives welcomed. */
+	struct semaphore erase_free_sem;
+
+	/* Write-behind buffer for NAND flash */
+	unsigned char *wbuf;
+	uint32_t wbuf_ofs;
+	uint32_t wbuf_len;
+	uint32_t wbuf_pagesize;
 };
-
-#ifdef JFFS2_OUT_OF_KERNEL
-#define JFFS2_SB_INFO(sb) ((struct jffs2_sb_info *) &(sb)->u)
-#else
-#define JFFS2_SB_INFO(sb) (&sb->u.jffs2_sb)
-#endif
-
-#define OFNI_BS_2SFFJ(c)  ((struct super_block *) ( ((char *)c) - ((char *)(&((struct super_block *)NULL)->u)) ) )
 
 #endif /* _JFFS2_FB_SB */
diff -Nru a/include/linux/minix_fs.h b/include/linux/minix_fs.h
--- a/include/linux/minix_fs.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/minix_fs.h	Fri Mar 15 17:51:01 2002
@@ -32,7 +32,7 @@
 #define MINIX_V1		0x0001		/* original minix fs */
 #define MINIX_V2		0x0002		/* minix V2 fs */
 
-#define INODE_VERSION(inode)	inode->i_sb->u.minix_sb.s_version
+#define INODE_VERSION(inode)	minix_sb(inode->i_sb)->s_version
 
 /*
  * This is the original minix inode layout on disk.
@@ -90,6 +90,7 @@
 #ifdef __KERNEL__
 
 #include <linux/minix_fs_i.h>
+#include <linux/minix_fs_sb.h>
 
 /*
  * change the define below to 0 if you want names > info->s_namelen chars to be
@@ -130,6 +131,11 @@
 extern struct file_operations minix_file_operations;
 extern struct file_operations minix_dir_operations;
 extern struct dentry_operations minix_dentry_operations;
+
+static inline struct minix_sb_info *minix_sb(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
 
 static inline struct minix_inode_info *minix_i(struct inode *inode)
 {
diff -Nru a/include/linux/mm.h b/include/linux/mm.h
--- a/include/linux/mm.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/mm.h	Fri Mar 15 17:51:01 2002
@@ -104,7 +104,7 @@
 #define VM_DONTEXPAND	0x00040000	/* Cannot expand with mremap() */
 #define VM_RESERVED	0x00080000	/* Don't unmap it from swap_out */
 
-#define VM_STACK_FLAGS	0x00000177
+#define VM_STACK_FLAGS	(0x00000100 | VM_DATA_DEFAULT_FLAGS)
 
 #define VM_READHINTMASK			(VM_SEQ_READ | VM_RAND_READ)
 #define VM_ClearReadHint(v)		(v)->vm_flags &= ~VM_READHINTMASK
diff -Nru a/include/linux/mmzone.h b/include/linux/mmzone.h
--- a/include/linux/mmzone.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/mmzone.h	Fri Mar 15 17:51:01 2002
@@ -51,8 +51,7 @@
 	/*
 	 * wait_table		-- the array holding the hash table
 	 * wait_table_size	-- the size of the hash table array
-	 * wait_table_shift	-- wait_table_size
-	 * 				== BITS_PER_LONG (1 << wait_table_bits)
+	 * wait_table_bits	-- wait_table_size == (1 << wait_table_bits)
 	 *
 	 * The purpose of all these is to keep track of the people
 	 * waiting for a page to become available and make them
@@ -75,7 +74,7 @@
 	 */
 	wait_queue_head_t	* wait_table;
 	unsigned long		wait_table_size;
-	unsigned long		wait_table_shift;
+	unsigned long		wait_table_bits;
 
 	/*
 	 * Discontig memory support fields.
diff -Nru a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h
--- a/include/linux/msdos_fs.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/msdos_fs.h	Fri Mar 15 17:51:03 2002
@@ -5,6 +5,7 @@
  * The MS-DOS filesystem constants/structures
  */
 #include <linux/msdos_fs_i.h>
+#include <linux/msdos_fs_sb.h>
 
 #include <asm/byteorder.h>
 
@@ -53,7 +54,11 @@
 #define MSDOS_VALID_MODE (S_IFREG | S_IFDIR | S_IRWXU | S_IRWXG | S_IRWXO)
 	/* valid file mode bits */
 
-#define MSDOS_SB(s) (&((s)->u.msdos_sb))
+static inline struct msdos_sb_info *MSDOS_SB(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
+
 static inline struct msdos_inode_info *MSDOS_I(struct inode *inode)
 {
 	return list_entry(inode, struct msdos_inode_info, vfs_inode);
@@ -282,9 +287,8 @@
 extern void fat_delete_inode(struct inode *inode);
 extern void fat_clear_inode(struct inode *inode);
 extern void fat_put_super(struct super_block *sb);
-extern struct super_block *
-fat_read_super(struct super_block *sb, void *data, int silent,
-	       struct inode_operations *fs_dir_inode_ops);
+int fat_fill_super(struct super_block *sb, void *data, int silent,
+		   struct inode_operations *fs_dir_inode_ops, int isvfat);
 extern int fat_statfs(struct super_block *sb, struct statfs *buf);
 extern void fat_write_inode(struct inode *inode, int wait);
 extern int fat_notify_change(struct dentry * dentry, struct iattr * attr);
diff -Nru a/include/linux/ncp_fs.h b/include/linux/ncp_fs.h
--- a/include/linux/ncp_fs.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/ncp_fs.h	Fri Mar 15 17:51:02 2002
@@ -13,6 +13,7 @@
 #include <linux/types.h>
 
 #include <linux/ncp_fs_i.h>
+#include <linux/ncp_fs_sb.h>
 #include <linux/ipx.h>
 #include <linux/ncp_no.h>
 
@@ -190,7 +191,10 @@
 #define NCP_SUPER_MAGIC  0x564c
 
 
-#define NCP_SBP(sb)		(&((sb)->u.ncpfs_sb))
+static inline struct ncp_server *NCP_SBP(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
 
 #define NCP_SERVER(inode)	NCP_SBP((inode)->i_sb)
 static inline struct ncp_inode_info *NCP_FINFO(struct inode *inode)
diff -Nru a/include/linux/ncp_fs_sb.h b/include/linux/ncp_fs_sb.h
--- a/include/linux/ncp_fs_sb.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/ncp_fs_sb.h	Fri Mar 15 17:51:01 2002
@@ -81,8 +81,6 @@
 	unsigned int flags;
 };
 
-#define ncp_sb_info	ncp_server
-
 #define NCP_FLAG_UTF8	1
 
 #define NCP_CLR_FLAG(server, flag)	((server)->flags &= ~(flag))
diff -Nru a/include/linux/netdevice.h b/include/linux/netdevice.h
--- a/include/linux/netdevice.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/netdevice.h	Fri Mar 15 17:51:03 2002
@@ -40,6 +40,7 @@
 #endif
 
 struct divert_blk;
+struct vlan_group;
 
 #define HAVE_ALLOC_NETDEV		/* feature macro: alloc_xxxdev
 					   functions are available. */
@@ -205,7 +206,8 @@
 	__LINK_STATE_START,
 	__LINK_STATE_PRESENT,
 	__LINK_STATE_SCHED,
-	__LINK_STATE_NOCARRIER
+	__LINK_STATE_NOCARRIER,
+	__LINK_STATE_RX_SCHED
 };
 
 
@@ -329,6 +331,10 @@
 	void                    *ip6_ptr;       /* IPv6 specific data */
 	void			*ec_ptr;	/* Econet specific data	*/
 
+	struct list_head	poll_list;	/* Link to poll list	*/
+	int			quota;
+	int			weight;
+
 	struct Qdisc		*qdisc;
 	struct Qdisc		*qdisc_sleeping;
 	struct Qdisc		*qdisc_list;
@@ -357,6 +363,10 @@
 #define NETIF_F_DYNALLOC	16	/* Self-dectructable device. */
 #define NETIF_F_HIGHDMA		32	/* Can DMA to high memory. */
 #define NETIF_F_FRAGLIST	64	/* Scatter/gather IO. */
+#define NETIF_F_HW_VLAN_TX	128	/* Transmit VLAN hw acceleration */
+#define NETIF_F_HW_VLAN_RX	256	/* Receive VLAN hw acceleration */
+#define NETIF_F_HW_VLAN_FILTER	512	/* Receive filtering on VLAN */
+#define NETIF_F_VLAN_CHALLENGED	1024	/* Device cannot handle VLAN packets */
 
 	/* Called after device is detached from network. */
 	void			(*uninit)(struct net_device *dev);
@@ -368,6 +378,7 @@
 	int			(*stop)(struct net_device *dev);
 	int			(*hard_start_xmit) (struct sk_buff *skb,
 						    struct net_device *dev);
+	int			(*poll) (struct net_device *dev, int *quota);
 	int			(*hard_header) (struct sk_buff *skb,
 						struct net_device *dev,
 						unsigned short type,
@@ -398,6 +409,13 @@
 #define HAVE_TX_TIMEOUT
 	void			(*tx_timeout) (struct net_device *dev);
 
+	void			(*vlan_rx_register)(struct net_device *dev,
+						    struct vlan_group *grp);
+	void			(*vlan_rx_add_vid)(struct net_device *dev,
+						   unsigned short vid);
+	void			(*vlan_rx_kill_vid)(struct net_device *dev,
+						    unsigned short vid);
+
 	int			(*hard_header_parse)(struct sk_buff *skb,
 						     unsigned char *haddr);
 	int			(*neigh_setup)(struct net_device *dev, struct neigh_parms *);
@@ -480,8 +498,11 @@
 	int			cng_level;
 	int			avg_blog;
 	struct sk_buff_head	input_pkt_queue;
+	struct list_head	poll_list;
 	struct net_device	*output_queue;
 	struct sk_buff		*completion_queue;
+
+	struct net_device	backlog_dev;	/* Sorry. 8) */
 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
 
 
@@ -535,6 +556,7 @@
 	return test_bit(__LINK_STATE_START, &dev->state);
 }
 
+
 /* Use this variant when it is known for sure that it
  * is executing from interrupt context.
  */
@@ -566,6 +588,8 @@
 extern void		net_call_rx_atomic(void (*fn)(void));
 #define HAVE_NETIF_RX 1
 extern int		netif_rx(struct sk_buff *skb);
+#define HAVE_NETIF_RECEIVE_SKB 1
+extern int		netif_receive_skb(struct sk_buff *skb);
 extern int		dev_ioctl(unsigned int cmd, void *);
 extern int		dev_change_flags(struct net_device *, unsigned);
 extern void		dev_queue_xmit_nit(struct sk_buff *skb, struct net_device *dev);
@@ -683,6 +707,78 @@
 #define netif_msg_rx_status(p)	((p)->msg_enable & NETIF_MSG_RX_STATUS)
 #define netif_msg_pktdata(p)	((p)->msg_enable & NETIF_MSG_PKTDATA)
 
+/* Schedule rx intr now? */
+
+static inline int netif_rx_schedule_prep(struct net_device *dev)
+{
+	return netif_running(dev) &&
+		!test_and_set_bit(__LINK_STATE_RX_SCHED, &dev->state);
+}
+
+/* Add interface to tail of rx poll list. This assumes that _prep has
+ * already been called and returned 1.
+ */
+
+static inline void __netif_rx_schedule(struct net_device *dev)
+{
+	unsigned long flags;
+	int cpu = smp_processor_id();
+
+	local_irq_save(flags);
+	dev_hold(dev);
+	list_add_tail(&dev->poll_list, &softnet_data[cpu].poll_list);
+	if (dev->quota < 0)
+		dev->quota += dev->weight;
+	else
+		dev->quota = dev->weight;
+	__cpu_raise_softirq(cpu, NET_RX_SOFTIRQ);
+	local_irq_restore(flags);
+}
+
+/* Try to reschedule poll. Called by irq handler. */
+
+static inline void netif_rx_schedule(struct net_device *dev)
+{
+	if (netif_rx_schedule_prep(dev))
+		__netif_rx_schedule(dev);
+}
+
+/* Try to reschedule poll. Called by dev->poll() after netif_rx_complete().
+ * Do not inline this?
+ */
+static inline int netif_rx_reschedule(struct net_device *dev, int undo)
+{
+	if (netif_rx_schedule_prep(dev)) {
+		unsigned long flags;
+		int cpu = smp_processor_id();
+
+		dev->quota += undo;
+
+		local_irq_save(flags);
+		list_add_tail(&dev->poll_list, &softnet_data[cpu].poll_list);
+		__cpu_raise_softirq(cpu, NET_RX_SOFTIRQ);
+		local_irq_restore(flags);
+		return 1;
+	}
+	return 0;
+}
+
+/* Remove interface from poll list: it must be in the poll list
+ * on current cpu. This primitive is called by dev->poll(), when
+ * it completes the work. The device cannot be out of poll list at this
+ * moment, it is BUG().
+ */
+static inline void netif_rx_complete(struct net_device *dev)
+{
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (!test_bit(__LINK_STATE_RX_SCHED, &dev->state)) BUG();
+	list_del(&dev->poll_list);
+	clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
+	local_irq_restore(flags);
+}
+
 /* These functions live elsewhere (drivers/net/net_init.c, but related) */
 
 extern void		ether_setup(struct net_device *dev);
@@ -707,6 +803,7 @@
 extern int		netdev_register_fc(struct net_device *dev, void (*stimul)(struct net_device *dev));
 extern void		netdev_unregister_fc(int bit);
 extern int		netdev_max_backlog;
+extern int		weight_p;
 extern unsigned long	netdev_fc_xoff;
 extern atomic_t netdev_dropping;
 extern int		netdev_set_master(struct net_device *dev, struct net_device *master);
diff -Nru a/include/linux/netfilter_arp/arp_tables.h b/include/linux/netfilter_arp/arp_tables.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/linux/netfilter_arp/arp_tables.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,342 @@
+/*
+ * 	Format of an ARP firewall descriptor
+ *
+ * 	src, tgt, src_mask, tgt_mask, arpop, arpop_mask are always stored in
+ *	network byte order.
+ * 	flags are stored in host byte order (of course).
+ */
+
+#ifndef _ARPTABLES_H
+#define _ARPTABLES_H
+
+#ifdef __KERNEL__
+#include <linux/if.h>
+#include <linux/types.h>
+#include <linux/in.h>
+#include <linux/if_arp.h>
+#include <linux/skbuff.h>
+#endif
+
+#include <linux/netfilter_arp.h>
+
+#define ARPT_FUNCTION_MAXNAMELEN 30
+#define ARPT_TABLE_MAXNAMELEN 32
+
+#define ARPT_DEV_ADDR_LEN_MAX 16
+
+struct arpt_devaddr_info {
+	char addr[ARPT_DEV_ADDR_LEN_MAX];
+	char mask[ARPT_DEV_ADDR_LEN_MAX];
+};
+
+/* Yes, Virginia, you have to zero the padding. */
+struct arpt_arp {
+	/* Source and target IP addr */
+	struct in_addr src, tgt;
+	/* Mask for src and target IP addr */
+	struct in_addr smsk, tmsk;
+
+	/* Device hw address length, src+target device addresses */
+	u_int8_t arhln, arhln_mask;
+	struct arpt_devaddr_info src_devaddr;
+	struct arpt_devaddr_info tgt_devaddr;
+
+	/* ARP operation code. */
+	u_int16_t arpop, arpop_mask;
+
+	/* ARP hardware address and protocol address format. */
+	u_int16_t arhrd, arhrd_mask;
+	u_int16_t arpro, arpro_mask;
+
+	/* The protocol address length is only accepted if it is 4
+	 * so there is no use in offering a way to do filtering on it.
+	 */
+
+	char iniface[IFNAMSIZ], outiface[IFNAMSIZ];
+	unsigned char iniface_mask[IFNAMSIZ], outiface_mask[IFNAMSIZ];
+
+	/* Flags word */
+	u_int8_t flags;
+	/* Inverse flags */
+	u_int16_t invflags;
+};
+
+struct arpt_entry_target
+{
+	union {
+		struct {
+			u_int16_t target_size;
+
+			/* Used by userspace */
+			char name[ARPT_FUNCTION_MAXNAMELEN];
+		} user;
+		struct {
+			u_int16_t target_size;
+
+			/* Used inside the kernel */
+			struct arpt_target *target;
+		} kernel;
+
+		/* Total length */
+		u_int16_t target_size;
+	} u;
+
+	unsigned char data[0];
+};
+
+struct arpt_standard_target
+{
+	struct arpt_entry_target target;
+	int verdict;
+};
+
+struct arpt_counters
+{
+	u_int64_t pcnt, bcnt;			/* Packet and byte counters */
+};
+
+/* Values for "flag" field in struct arpt_ip (general arp structure).
+ * No flags defined yet.
+ */
+#define ARPT_F_MASK		0x00	/* All possible flag bits mask. */
+
+/* Values for "inv" field in struct arpt_arp. */
+#define ARPT_INV_VIA_IN		0x0001	/* Invert the sense of IN IFACE. */
+#define ARPT_INV_VIA_OUT	0x0002	/* Invert the sense of OUT IFACE */
+#define ARPT_INV_SRCIP		0x0004	/* Invert the sense of SRC IP. */
+#define ARPT_INV_TGTIP		0x0008	/* Invert the sense of TGT IP. */
+#define ARPT_INV_SRCDEVADDR	0x0010	/* Invert the sense of SRC DEV ADDR. */
+#define ARPT_INV_TGTDEVADDR	0x0020	/* Invert the sense of TGT DEV ADDR. */
+#define ARPT_INV_ARPOP		0x0040	/* Invert the sense of ARP OP. */
+#define ARPT_INV_ARPHRD		0x0080	/* Invert the sense of ARP HRD. */
+#define ARPT_INV_ARPPRO		0x0100	/* Invert the sense of ARP PRO. */
+#define ARPT_INV_ARPHLN		0x0200	/* Invert the sense of ARP HLN. */
+#define ARPT_INV_MASK		0x007F	/* All possible flag bits mask. */
+
+/* This structure defines each of the firewall rules.  Consists of 3
+   parts which are 1) general ARP header stuff 2) match specific
+   stuff 3) the target to perform if the rule matches */
+struct arpt_entry
+{
+	struct arpt_arp arp;
+
+	/* Size of arpt_entry + matches */
+	u_int16_t target_offset;
+	/* Size of arpt_entry + matches + target */
+	u_int16_t next_offset;
+
+	/* Back pointer */
+	unsigned int comefrom;
+
+	/* Packet and byte counters. */
+	struct arpt_counters counters;
+
+	/* The matches (if any), then the target. */
+	unsigned char elems[0];
+};
+
+/*
+ * New IP firewall options for [gs]etsockopt at the RAW IP level.
+ * Unlike BSD Linux inherits IP options so you don't have to use a raw
+ * socket for this. Instead we check rights in the calls.
+ */
+#define ARPT_BASE_CTL		96	/* base for firewall socket options */
+
+#define ARPT_SO_SET_REPLACE		(ARPT_BASE_CTL)
+#define ARPT_SO_SET_ADD_COUNTERS	(ARPT_BASE_CTL + 1)
+#define ARPT_SO_SET_MAX			ARPT_SO_SET_ADD_COUNTERS
+
+#define ARPT_SO_GET_INFO		(ARPT_BASE_CTL)
+#define ARPT_SO_GET_ENTRIES		(ARPT_BASE_CTL + 1)
+#define ARPT_SO_GET_MAX			ARPT_SO_GET_ENTRIES
+
+/* CONTINUE verdict for targets */
+#define ARPT_CONTINUE 0xFFFFFFFF
+
+/* For standard target */
+#define ARPT_RETURN (-NF_MAX_VERDICT - 1)
+
+/* The argument to ARPT_SO_GET_INFO */
+struct arpt_getinfo
+{
+	/* Which table: caller fills this in. */
+	char name[ARPT_TABLE_MAXNAMELEN];
+
+	/* Kernel fills these in. */
+	/* Which hook entry points are valid: bitmask */
+	unsigned int valid_hooks;
+
+	/* Hook entry points: one per netfilter hook. */
+	unsigned int hook_entry[NF_ARP_NUMHOOKS];
+
+	/* Underflow points. */
+	unsigned int underflow[NF_ARP_NUMHOOKS];
+
+	/* Number of entries */
+	unsigned int num_entries;
+
+	/* Size of entries. */
+	unsigned int size;
+};
+
+/* The argument to ARPT_SO_SET_REPLACE. */
+struct arpt_replace
+{
+	/* Which table. */
+	char name[ARPT_TABLE_MAXNAMELEN];
+
+	/* Which hook entry points are valid: bitmask.  You can't
+           change this. */
+	unsigned int valid_hooks;
+
+	/* Number of entries */
+	unsigned int num_entries;
+
+	/* Total size of new entries */
+	unsigned int size;
+
+	/* Hook entry points. */
+	unsigned int hook_entry[NF_ARP_NUMHOOKS];
+
+	/* Underflow points. */
+	unsigned int underflow[NF_ARP_NUMHOOKS];
+
+	/* Information about old entries: */
+	/* Number of counters (must be equal to current number of entries). */
+	unsigned int num_counters;
+	/* The old entries' counters. */
+	struct arpt_counters *counters;
+
+	/* The entries (hang off end: not really an array). */
+	struct arpt_entry entries[0];
+};
+
+/* The argument to ARPT_SO_ADD_COUNTERS. */
+struct arpt_counters_info
+{
+	/* Which table. */
+	char name[ARPT_TABLE_MAXNAMELEN];
+
+	unsigned int num_counters;
+
+	/* The counters (actually `number' of these). */
+	struct arpt_counters counters[0];
+};
+
+/* The argument to ARPT_SO_GET_ENTRIES. */
+struct arpt_get_entries
+{
+	/* Which table: user fills this in. */
+	char name[ARPT_TABLE_MAXNAMELEN];
+
+	/* User fills this in: total entry size. */
+	unsigned int size;
+
+	/* The entries. */
+	struct arpt_entry entrytable[0];
+};
+
+/* Standard return verdict, or do jump. */
+#define ARPT_STANDARD_TARGET ""
+/* Error verdict. */
+#define ARPT_ERROR_TARGET "ERROR"
+
+/* Helper functions */
+static __inline__ struct arpt_entry_target *arpt_get_target(struct arpt_entry *e)
+{
+	return (void *)e + e->target_offset;
+}
+
+/* fn returns 0 to continue iteration */
+#define ARPT_ENTRY_ITERATE(entries, size, fn, args...)		\
+({								\
+	unsigned int __i;					\
+	int __ret = 0;						\
+	struct arpt_entry *__entry;				\
+								\
+	for (__i = 0; __i < (size); __i += __entry->next_offset) { \
+		__entry = (void *)(entries) + __i;		\
+								\
+		__ret = fn(__entry , ## args);			\
+		if (__ret != 0)					\
+			break;					\
+	}							\
+	__ret;							\
+})
+
+/*
+ *	Main firewall chains definitions and global var's definitions.
+ */
+#ifdef __KERNEL__
+
+/* Registration hooks for targets. */
+struct arpt_target
+{
+	struct list_head list;
+
+	const char name[ARPT_FUNCTION_MAXNAMELEN];
+
+	/* Returns verdict. */
+	unsigned int (*target)(struct sk_buff **pskb,
+			       unsigned int hooknum,
+			       const struct net_device *in,
+			       const struct net_device *out,
+			       const void *targinfo,
+			       void *userdata);
+
+	/* Called when user tries to insert an entry of this type:
+           hook_mask is a bitmask of hooks from which it can be
+           called. */
+	/* Should return true or false. */
+	int (*checkentry)(const char *tablename,
+			  const struct arpt_entry *e,
+			  void *targinfo,
+			  unsigned int targinfosize,
+			  unsigned int hook_mask);
+
+	/* Called when entry of this type deleted. */
+	void (*destroy)(void *targinfo, unsigned int targinfosize);
+
+	/* Set this to THIS_MODULE if you are a module, otherwise NULL */
+	struct module *me;
+};
+
+extern int arpt_register_target(struct arpt_target *target);
+extern void arpt_unregister_target(struct arpt_target *target);
+
+/* Furniture shopping... */
+struct arpt_table
+{
+	struct list_head list;
+
+	/* A unique name... */
+	char name[ARPT_TABLE_MAXNAMELEN];
+
+	/* Seed table: copied in register_table */
+	struct arpt_replace *table;
+
+	/* What hooks you will enter on */
+	unsigned int valid_hooks;
+
+	/* Lock for the curtain */
+	rwlock_t lock;
+
+	/* Man behind the curtain... */
+	struct arpt_table_info *private;
+
+	/* Set this to THIS_MODULE if you are a module, otherwise NULL */
+	struct module *me;
+};
+
+extern int arpt_register_table(struct arpt_table *table);
+extern void arpt_unregister_table(struct arpt_table *table);
+extern unsigned int arpt_do_table(struct sk_buff **pskb,
+				  unsigned int hook,
+				  const struct net_device *in,
+				  const struct net_device *out,
+				  struct arpt_table *table,
+				  void *userdata);
+
+#define ARPT_ALIGN(s) (((s) + (__alignof__(struct arpt_entry)-1)) & ~(__alignof__(struct arpt_entry)-1))
+#endif /*__KERNEL__*/
+#endif /* _ARPTABLES_H */
diff -Nru a/include/linux/netfilter_arp.h b/include/linux/netfilter_arp.h
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/include/linux/netfilter_arp.h	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,19 @@
+#ifndef __LINUX_ARP_NETFILTER_H
+#define __LINUX_ARP_NETFILTER_H
+
+/* ARP-specific defines for netfilter.
+ * (C)2002 Rusty Russell IBM -- This code is GPL.
+ */
+
+#include <linux/config.h>
+#include <linux/netfilter.h>
+
+/* There is no PF_ARP. */
+#define NF_ARP		0
+
+/* ARP Hooks */
+#define NF_ARP_IN	0
+#define NF_ARP_OUT	1
+#define NF_ARP_NUMHOOKS	2
+
+#endif /* __LINUX_ARP_NETFILTER_H */
diff -Nru a/include/linux/netfilter_ipv4/ip_conntrack.h b/include/linux/netfilter_ipv4/ip_conntrack.h
--- a/include/linux/netfilter_ipv4/ip_conntrack.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/netfilter_ipv4/ip_conntrack.h	Fri Mar 15 17:51:02 2002
@@ -82,10 +82,7 @@
 #endif
 
 #include <linux/netfilter_ipv4/ip_conntrack_ftp.h>
-
-#if defined(CONFIG_IP_NF_IRC) || defined(CONFIG_IP_NF_IRC_MODULE)
 #include <linux/netfilter_ipv4/ip_conntrack_irc.h>
-#endif
 
 struct ip_conntrack
 {
@@ -125,9 +122,7 @@
 
 	union {
 		struct ip_ct_ftp ct_ftp_info;
-#if defined(CONFIG_IP_NF_IRC) || defined(CONFIG_IP_NF_IRC_MODULE)
 		struct ip_ct_irc ct_irc_info;
-#endif
 	} help;
 
 #ifdef CONFIG_IP_NF_NAT_NEEDED
diff -Nru a/include/linux/netfilter_ipv4/ip_nat.h b/include/linux/netfilter_ipv4/ip_nat.h
--- a/include/linux/netfilter_ipv4/ip_nat.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/netfilter_ipv4/ip_nat.h	Fri Mar 15 17:51:03 2002
@@ -11,8 +11,13 @@
 	IP_NAT_MANIP_DST
 };
 
+#ifndef CONFIG_IP_NF_NAT_LOCAL
 /* SRC manip occurs only on POST_ROUTING */
 #define HOOK2MANIP(hooknum) ((hooknum) != NF_IP_POST_ROUTING)
+#else
+/* SRC manip occurs POST_ROUTING or LOCAL_IN */
+#define HOOK2MANIP(hooknum) ((hooknum) != NF_IP_POST_ROUTING && (hooknum) != NF_IP_LOCAL_IN)
+#endif
 
 /* 2.3.19 (I hope) will define this in linux/netfilter_ipv4.h. */
 #ifndef SO_ORIGINAL_DST
diff -Nru a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
--- a/include/linux/nfs_fs.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/nfs_fs.h	Fri Mar 15 17:51:02 2002
@@ -14,8 +14,11 @@
 #include <linux/mm.h>
 #include <linux/pagemap.h>
 
+#include <linux/nfs_fs_sb.h>
+
 #include <linux/sunrpc/debug.h>
 #include <linux/sunrpc/auth.h>
+#include <linux/sunrpc/clnt.h>
 
 #include <linux/nfs.h>
 #include <linux/nfs2.h>
@@ -173,9 +176,10 @@
 {
 	return list_entry(inode, struct nfs_inode, vfs_inode);
 }
+#define NFS_SB(s)		((struct nfs_server *)(s->u.generic_sbp))
 
 #define NFS_FH(inode)			(&NFS_I(inode)->fh)
-#define NFS_SERVER(inode)		(&(inode)->i_sb->u.nfs_sb.s_server)
+#define NFS_SERVER(inode)		(NFS_SB(inode->i_sb))
 #define NFS_CLIENT(inode)		(NFS_SERVER(inode)->client)
 #define NFS_PROTO(inode)		(NFS_SERVER(inode)->rpc_ops)
 #define NFS_REQUESTLIST(inode)		(NFS_SERVER(inode)->rw_requests)
@@ -418,6 +422,29 @@
 		wait_event(wq, condition);				\
 	__retval;							\
 })
+
+#ifdef CONFIG_NFS_V3
+
+#define NFS_JUKEBOX_RETRY_TIME (5 * HZ)
+static inline int
+nfs_async_handle_jukebox(struct rpc_task *task)
+{
+	if (task->tk_status != -EJUKEBOX)
+		return 0;
+	task->tk_status = 0;
+	rpc_restart_call(task);
+	rpc_delay(task, NFS_JUKEBOX_RETRY_TIME);
+	return 1;
+}
+
+#else
+
+static inline int
+nfs_async_handle_jukebox(struct rpc_task *task)
+{
+	return 0;
+}
+#endif /* CONFIG_NFS_V3 */
 
 #endif /* __KERNEL__ */
 
diff -Nru a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
--- a/include/linux/nfs_fs_sb.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/nfs_fs_sb.h	Fri Mar 15 17:51:03 2002
@@ -27,13 +27,8 @@
 				lru_dirty,
 				lru_commit,
 				lru_busy;
-};
-
-/*
- * nfs super-block data in memory
- */
-struct nfs_sb_info {
-	struct nfs_server	s_server;
+	struct nfs_fh		fh;
+	struct sockaddr_in	addr;
 };
 
 #endif
diff -Nru a/include/linux/nfs_page.h b/include/linux/nfs_page.h
--- a/include/linux/nfs_page.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/nfs_page.h	Fri Mar 15 17:51:01 2002
@@ -13,6 +13,7 @@
 #include <linux/list.h>
 #include <linux/mm.h>
 #include <linux/wait.h>
+#include <linux/nfs_fs_sb.h>
 #include <linux/sunrpc/auth.h>
 #include <linux/nfs_xdr.h>
 
diff -Nru a/include/linux/nfsd/export.h b/include/linux/nfsd/export.h
--- a/include/linux/nfsd/export.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/nfsd/export.h	Fri Mar 15 17:51:01 2002
@@ -39,7 +39,8 @@
 #define NFSEXP_NOSUBTREECHECK	0x0400
 #define	NFSEXP_NOAUTHNLM	0x0800		/* Don't authenticate NLM requests - just trust */
 #define NFSEXP_MSNFS		0x1000	/* do silly things that MS clients expect */
-#define NFSEXP_ALLFLAGS		0x1FFF
+#define NFSEXP_FSID		0x2000
+#define NFSEXP_ALLFLAGS		0x3FFF
 
 
 #ifdef __KERNEL__
@@ -55,11 +56,13 @@
 	struct in_addr		cl_addr[NFSCLNT_ADDRMAX];
 	struct svc_uidmap *	cl_umap;
 	struct list_head	cl_export[NFSCLNT_EXPMAX];
+	struct list_head	cl_expfsid[NFSCLNT_EXPMAX];
 	struct list_head	cl_list;
 };
 
 struct svc_export {
 	struct list_head	ex_hash;
+	struct list_head	ex_fsid_hash;
 	struct list_head	ex_list;
 	char			ex_path[NFS_MAXPATHLEN+1];
 	struct svc_export *	ex_parent;
@@ -71,6 +74,7 @@
 	ino_t			ex_ino;
 	uid_t			ex_anon_uid;
 	gid_t			ex_anon_gid;
+	int			ex_fsid;
 };
 
 #define EX_SECURE(exp)		(!((exp)->ex_flags & NFSEXP_INSECURE_PORT))
@@ -91,6 +95,7 @@
 struct svc_client *	exp_getclient(struct sockaddr_in *sin);
 void			exp_putclient(struct svc_client *clp);
 struct svc_export *	exp_get(struct svc_client *clp, kdev_t dev, ino_t ino);
+struct svc_export *	exp_get_fsid(struct svc_client *clp, int fsid);
 struct svc_export *	exp_get_by_name(struct svc_client *clp,
 					struct vfsmount *mnt,
 					struct dentry *dentry);
diff -Nru a/include/linux/nfsd/interface.h b/include/linux/nfsd/interface.h
--- a/include/linux/nfsd/interface.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/nfsd/interface.h	Fri Mar 15 17:51:03 2002
@@ -10,17 +10,4 @@
 #ifndef LINUX_NFSD_INTERFACE_H
 #define LINUX_NFSD_INTERFACE_H
 
-#include <linux/config.h>
-
-#ifndef CONFIG_NFSD
-#ifdef CONFIG_MODULES
-
-extern struct nfsd_linkage {
-	long (*do_nfsservctl)(int cmd, void *argp, void *resp);
-	struct module *owner;
-} * nfsd_linkage;
-
-#endif
-#endif
-
 #endif /* LINUX_NFSD_INTERFACE_H */
diff -Nru a/include/linux/nfsd/syscall.h b/include/linux/nfsd/syscall.h
--- a/include/linux/nfsd/syscall.h	Fri Mar 15 17:51:04 2002
+++ b/include/linux/nfsd/syscall.h	Fri Mar 15 17:51:04 2002
@@ -133,7 +133,7 @@
  * Kernel syscall implementation.
  */
 #if defined(CONFIG_NFSD) || defined(CONFIG_NFSD_MODULE)
-extern asmlinkage long	sys_nfsservctl(int, void *, void *);
+extern asmlinkage long	sys_nfsservctl(int, struct nfsctl_arg *, void *);
 #else
 #define sys_nfsservctl		sys_ni_syscall
 #endif
diff -Nru a/include/linux/pci.h b/include/linux/pci.h
--- a/include/linux/pci.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/pci.h	Fri Mar 15 17:51:03 2002
@@ -567,7 +567,6 @@
 #define HAVE_PCI_SET_MWI
 int pci_set_mwi(struct pci_dev *dev);
 void pci_clear_mwi(struct pci_dev *dev);
-int pdev_set_mwi(struct pci_dev *dev);
 int pci_set_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask);
 int pci_assign_resource(struct pci_dev *dev, int i);
diff -Nru a/include/linux/pci_ids.h b/include/linux/pci_ids.h
--- a/include/linux/pci_ids.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/pci_ids.h	Fri Mar 15 17:51:03 2002
@@ -383,11 +383,14 @@
 #define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
 #define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
 #define PCI_DEVICE_ID_AMD_VIPER_7414	0x7414
-#define PCI_DEVICE_ID_AMD_VIPER_7440	0x7440
-#define PCI_DEVICE_ID_AMD_VIPER_7441	0x7441
-#define PCI_DEVICE_ID_AMD_VIPER_7443	0x7443
-#define PCI_DEVICE_ID_AMD_VIPER_7448	0x7448
-#define PCI_DEVICE_ID_AMD_VIPER_7449	0x7449
+#define PCI_DEVICE_ID_AMD_OPUS_7440	0x7440
+#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
+#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
+#define PCI_DEVICE_ID_AMD_OPUS_7448	0x7448
+#define PCI_DEVICE_ID_AMD_OPUS_7449	0x7449
+#define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_AUDIO	0x746d
 
 #define PCI_VENDOR_ID_TRIDENT		0x1023
 #define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
diff -Nru a/include/linux/qnx4_fs.h b/include/linux/qnx4_fs.h
--- a/include/linux/qnx4_fs.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/qnx4_fs.h	Fri Mar 15 17:51:03 2002
@@ -97,6 +97,13 @@
 #define QNX4DEBUG(X) (void) 0
 #endif
 
+struct qnx4_sb_info {
+	struct buffer_head	*sb_buf;	/* superblock buffer */
+	struct qnx4_super_block	*sb;		/* our superblock */
+	unsigned int		Version;	/* may be useful */
+	struct qnx4_inode_entry	*BitMap;	/* useful */
+};
+
 struct qnx4_inode_info {
 	struct qnx4_inode_entry raw;
 	unsigned long mmu_private;
@@ -125,6 +132,11 @@
 extern int qnx4_sync_file(struct file *file, struct dentry *dentry, int);
 extern int qnx4_sync_inode(struct inode *inode);
 extern int qnx4_get_block(struct inode *inode, sector_t iblock, struct buffer_head *bh, int create);
+
+static inline struct qnx4_sb_info *qnx4_sb(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
 
 static inline struct qnx4_inode_info *qnx4_i(struct inode *inode)
 {
diff -Nru a/include/linux/qnx4_fs_sb.h b/include/linux/qnx4_fs_sb.h
--- a/include/linux/qnx4_fs_sb.h	Fri Mar 15 17:51:03 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,27 +0,0 @@
-/*
- *  Name                         : qnx4_fs_sb.h
- *  Author                       : Richard Frowijn
- *  Function                     : qnx4 superblock definitions
- *  Version                      : 1.0.2
- *  Last modified                : 2000-01-06
- * 
- *  History                      : 23-03-1998 created
- * 
- */
-#ifndef _QNX4_FS_SB
-#define _QNX4_FS_SB
-
-#include <linux/qnx4_fs.h>
-
-/*
- * qnx4 super-block data in memory
- */
-
-struct qnx4_sb_info {
-	struct buffer_head	*sb_buf;	/* superblock buffer */
-	struct qnx4_super_block	*sb;		/* our superblock */
-	unsigned int		Version;	/* may be useful */
-	struct qnx4_inode_entry	*BitMap;	/* useful */
-};
-
-#endif
diff -Nru a/include/linux/romfs_fs_i.h b/include/linux/romfs_fs_i.h
--- a/include/linux/romfs_fs_i.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,11 +0,0 @@
-#ifndef __ROMFS_FS_I
-#define __ROMFS_FS_I
-
-/* inode in-kernel data */
-
-struct romfs_inode_info {
-	unsigned long i_metasize;	/* size of non-data area */
-	unsigned long i_dataoffset;	/* from the start of fs */
-};
-
-#endif
diff -Nru a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
--- a/include/linux/rtnetlink.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/rtnetlink.h	Fri Mar 15 17:51:03 2002
@@ -440,12 +440,14 @@
 #define IFLA_COST IFLA_COST
 	IFLA_PRIORITY,
 #define IFLA_PRIORITY IFLA_PRIORITY
-	IFLA_MASTER
+	IFLA_MASTER,
 #define IFLA_MASTER IFLA_MASTER
+	IFLA_WIRELESS,		/* Wireless Extension event - see wireless.h */
+#define IFLA_WIRELESS IFLA_WIRELESS
 };
 
 
-#define IFLA_MAX IFLA_MASTER
+#define IFLA_MAX IFLA_WIRELESS
 
 #define IFLA_RTA(r)  ((struct rtattr*)(((char*)(r)) + NLMSG_ALIGN(sizeof(struct ifinfomsg))))
 #define IFLA_PAYLOAD(n) NLMSG_PAYLOAD(n,sizeof(struct ifinfomsg))
diff -Nru a/include/linux/sched.h b/include/linux/sched.h
--- a/include/linux/sched.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/sched.h	Fri Mar 15 17:51:01 2002
@@ -250,7 +250,7 @@
 	unsigned long cpus_allowed;
 	unsigned int time_slice;
 
-	struct task_struct *next_task, *prev_task;
+	struct list_head tasks;
 
 	struct mm_struct *mm, *active_mm;
 	struct list_head local_pages;
@@ -274,9 +274,12 @@
 	/* 
 	 * pointers to (original) parent process, youngest child, younger sibling,
 	 * older sibling, respectively.  (p->father can be replaced with 
-	 * p->p_pptr->pid)
+	 * p->parent->pid)
 	 */
-	struct task_struct *p_opptr, *p_pptr, *p_cptr, *p_ysptr, *p_osptr;
+	struct task_struct *real_parent; /* real parent process (when being debugged) */
+	struct task_struct *parent;	/* parent process */
+	struct list_head children;	/* list of my children */
+	struct list_head sibling;	/* linkage in my parent's children list */
 	struct list_head thread_group;
 
 	/* PID hash table linkage. */
@@ -715,30 +718,48 @@
 	__ret;								\
 })
 
-#define REMOVE_LINKS(p) do { \
-	(p)->next_task->prev_task = (p)->prev_task; \
-	(p)->prev_task->next_task = (p)->next_task; \
-	if ((p)->p_osptr) \
-		(p)->p_osptr->p_ysptr = (p)->p_ysptr; \
-	if ((p)->p_ysptr) \
-		(p)->p_ysptr->p_osptr = (p)->p_osptr; \
-	else \
-		(p)->p_pptr->p_cptr = (p)->p_osptr; \
+#define remove_parent(p)	list_del_init(&(p)->sibling)
+#define add_parent(p, parent)	list_add_tail(&(p)->sibling,&(parent)->children)
+
+#define REMOVE_LINKS(p) do {				\
+	list_del_init(&(p)->tasks);			\
+	remove_parent(p);				\
 	} while (0)
 
-#define SET_LINKS(p) do { \
-	(p)->next_task = &init_task; \
-	(p)->prev_task = init_task.prev_task; \
-	init_task.prev_task->next_task = (p); \
-	init_task.prev_task = (p); \
-	(p)->p_ysptr = NULL; \
-	if (((p)->p_osptr = (p)->p_pptr->p_cptr) != NULL) \
-		(p)->p_osptr->p_ysptr = p; \
-	(p)->p_pptr->p_cptr = p; \
+#define SET_LINKS(p) do {				\
+	list_add_tail(&(p)->tasks,&init_task.tasks);	\
+	add_parent(p, (p)->parent);			\
 	} while (0)
 
+static inline struct task_struct *eldest_child(struct task_struct *p)
+{
+	if (list_empty(&p->children)) return NULL;
+	return list_entry(p->children.next,struct task_struct,sibling);
+}
+
+static inline struct task_struct *youngest_child(struct task_struct *p)
+{
+	if (list_empty(&p->children)) return NULL;
+	return list_entry(p->children.prev,struct task_struct,sibling);
+}
+
+static inline struct task_struct *older_sibling(struct task_struct *p)
+{
+	if (p->sibling.prev==&p->parent->children) return NULL;
+	return list_entry(p->sibling.prev,struct task_struct,sibling);
+}
+
+static inline struct task_struct *younger_sibling(struct task_struct *p)
+{
+	if (p->sibling.next==&p->parent->children) return NULL;
+	return list_entry(p->sibling.next,struct task_struct,sibling);
+}
+
+#define next_task(p)	list_entry((p)->tasks.next, struct task_struct, tasks)
+#define prev_task(p)	list_entry((p)->tasks.prev, struct task_struct, tasks)
+
 #define for_each_task(p) \
-	for (p = &init_task ; (p = p->next_task) != &init_task ; )
+	for (p = &init_task ; (p = next_task(p)) != &init_task ; )
 
 #define for_each_thread(task) \
 	for (task = next_thread(current) ; task != current ; task = next_thread(task))
diff -Nru a/include/linux/smb_fs.h b/include/linux/smb_fs.h
--- a/include/linux/smb_fs.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/smb_fs.h	Fri Mar 15 17:51:03 2002
@@ -11,6 +11,7 @@
 
 #include <linux/smb.h>
 #include <linux/smb_fs_i.h>
+#include <linux/smb_fs_sb.h>
 
 /*
  * ioctl commands
@@ -28,6 +29,11 @@
 #include <linux/vmalloc.h>
 #include <linux/smb_mount.h>
 #include <asm/unaligned.h>
+
+static inline struct smb_sb_info *SMB_SB(struct super_block *sb)
+{
+	return sb->u.generic_sbp;
+}
 
 static inline struct smb_inode_info *SMB_I(struct inode *inode)
 {
diff -Nru a/include/linux/smb_fs_sb.h b/include/linux/smb_fs_sb.h
--- a/include/linux/smb_fs_sb.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/smb_fs_sb.h	Fri Mar 15 17:51:02 2002
@@ -15,10 +15,9 @@
 #include <linux/smb.h>
 
 /* structure access macros */
-#define server_from_inode(inode) (&(inode)->i_sb->u.smbfs_sb)
-#define server_from_dentry(dentry) (&(dentry)->d_sb->u.smbfs_sb)
-#define SB_of(server) ((struct super_block *) ((char *)(server) - \
-	(unsigned long)(&((struct super_block *)0)->u.smbfs_sb)))
+#define server_from_inode(inode) SMB_SB((inode)->i_sb)
+#define server_from_dentry(dentry) SMB_SB((dentry)->d_sb)
+#define SB_of(server) ((server)->super_block)
 
 struct smb_sb_info {
         enum smb_conn_state state;
@@ -55,6 +54,7 @@
 	char *name_buf;
 
 	struct smb_ops *ops;
+	struct super_block *super_block;
 };
 
 
diff -Nru a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h
--- a/include/linux/sunrpc/svcsock.h	Fri Mar 15 17:51:02 2002
+++ b/include/linux/sunrpc/svcsock.h	Fri Mar 15 17:51:02 2002
@@ -22,7 +22,7 @@
 
 	struct svc_serv *	sk_server;	/* service for this socket */
 	unsigned char		sk_inuse;	/* use count */
-	unsigned int		sk_flags;
+	unsigned long		sk_flags;
 #define	SK_BUSY		0			/* enqueued/receiving */
 #define	SK_CONN		1			/* conn pending */
 #define	SK_CLOSE	2			/* dead or dying */
diff -Nru a/include/linux/sysctl.h b/include/linux/sysctl.h
--- a/include/linux/sysctl.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/sysctl.h	Fri Mar 15 17:51:01 2002
@@ -202,7 +202,8 @@
 	NET_CORE_NO_CONG_THRESH=13,
 	NET_CORE_NO_CONG=14,
 	NET_CORE_LO_CONG=15,
-	NET_CORE_MOD_CONG=16
+	NET_CORE_MOD_CONG=16,
+	NET_CORE_DEV_WEIGHT=17
 };
 
 /* /proc/sys/net/ethernet */
diff -Nru a/include/linux/udf_167.h b/include/linux/udf_167.h
--- a/include/linux/udf_167.h	Fri Mar 15 17:51:02 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,786 +0,0 @@
-#if !defined(_LINUX_UDF_167_H)
-#define _LINUX_UDF_167_H
-/*
- * udf_167.h
- *
- * DESCRIPTION
- *	Definitions from the ECMA 167 standard.
- *	http://www.ecma.ch/
- *
- *	These abbreviations are used to keep the symbols short:
- *		Alloc	Allocation
- *		App	Application
- *		Attr	Attribute
- *		Char	Characters
- *		Desc	Descriptor
- *		Descs	Descriptors
- *		Ext	Extent
- *		Ident	Identifier
- *		Imp	Implementation
- *		Lvl	Level
- *		Max	Maximum
- *		Num	Number
- *		Ptr	Pointer
- *		Seq	Sequence
- *		Std	Standard
- *		Struct	Structure
- *		Vol	Volume
- *	The symbols are otherwise identical to the standard, and the
- *	sections of the standard to refer to are indicated.
- *
- * CONTACTS
- *	E-mail regarding any portion of the Linux UDF file system should be
- *	directed to the development team mailing list (run by majordomo):
- *		linux_udf@hpesjro.fc.hp.com
- *
- * COPYRIGHT
- *	This file is distributed under the terms of the GNU General Public
- *	License (GPL). Copies of the GPL can be obtained from:
- *		ftp://prep.ai.mit.edu/pub/gnu/GPL
- *	Each contributing author retains all rights to their own work.
- *
- * HISTORY
- *	July 12, 1997 - Andrew E. Mileski
- *	Adapted from the ECMA-167 standard.
- *
- * 10/2/98 dgb	Adaptation
- * 10/4/98 	Changes by HJA Sandkuyl
- * 10/7/98	Changed FILE_EXISTENCE to FILE_HIDDEN, per UDF 2.0 spec
- * 11/26/98	Modifed some entries for UDF 1.5/2.0
- * 11/26/98 bf  Fixed typos, non-linux types, more structures
- * 12/5/98 dgb  Adjusted structure and content of include files.
- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#define Uint8	__u8
-#define Sint8	__s8
-#define Uint16	__u16
-#define Sint16	__s16
-#define Uint32	__u32
-#define Sint32	__s32
-#define Uint64	__u64
-#define Sint64	__s64
-typedef Uint8	dstring;
-#else
-#define Uint8	unsigned char
-#define Sint8	char
-#define Uint16	unsigned short
-#define Sint16	short
-#define Uint32	unsigned int
-#define Sint32	int
-#define Uint64	unsigned long long
-#define Sint64	long long
-typedef Uint8	dstring;
-#endif
-
-/* make sure all structures are packed! */
-#pragma pack(1)
-
-/* CS0 Charspec (ECMA 167 1/7.2.1) */
-typedef struct {
-	Uint8 charSetType;
-	Uint8 charSetInfo[63];
-} charspec;
-
-/* Timestamp (ECMA 167 1/7.3) */
-typedef struct {
-	Uint16 typeAndTimezone;
-	Uint16 year;
-	Uint8 month;
-	Uint8 day;
-	Uint8 hour;
-	Uint8 minute;
-	Uint8 second;
-	Uint8 centiseconds;
-	Uint8 hundredsOfMicroseconds;
-	Uint8 microseconds;
-} timestamp;
-
-/* Timestamp types (ECMA 167 1/7.3.1) */
-#define TIMESTAMP_TYPE_CUT		0x0000U
-#define TIMESTAMP_TYPE_LOCAL		0x0001U
-#define TIMESTAMP_TYPE_AGREEMENT	0x0002U
-
-/* Entity Identifier (ECMA 167 1/7.4) */
-typedef struct {
-	Uint8 flags;
-	Uint8 ident[23];
-	Uint8 identSuffix[8];
-} EntityID;
-#define regid EntityID
-
-/* Entity identifier flags (ECMA 167 1/7.4.1) */
-#define ENTITYID_FLAGS_DIRTY		0x01U
-#define ENTITYID_FLAGS_PROTECTED	0x02U
-
-/* Volume Structure Descriptor (ECMA 167 2/9.1) */
-#define STD_ID_LEN	5
-struct VolStructDesc {
-	Uint8 structType;
-	Uint8 stdIdent[STD_ID_LEN];
-	Uint8 structVersion;
-	Uint8 structData[2041];
-};
-
-/* Std structure identifiers (ECMA 167 2/9.1.2) */
-#define STD_ID_BEA01	"BEA01"
-#define STD_ID_BOOT2	"BOOT2"
-#define STD_ID_CD001	"CD001"
-#define STD_ID_CDW02	"CDW02"
-#define STD_ID_NSR02	"NSR02"
-#define STD_ID_NSR03	"NSR03"
-#define STD_ID_TEA01	"TEA01"
-
-/* Beginning Extended Area Descriptor (ECMA 167 2/9.2) */
-struct BeginningExtendedAreaDesc {
-	Uint8 structType;
-	Uint8 stdIdent[STD_ID_LEN];
-	Uint8 structVersion;
-	Uint8 structData[2041];
-};
-
-/* Terminating Extended Area Descriptor (ECMA 167 2/9.3) */
-struct TerminatingExtendedAreaDesc {
-	Uint8 structType;
-	Uint8 stdIdent[STD_ID_LEN];
-	Uint8 structVersion;
-	Uint8 structData[2041];
-};
-
-/* Boot Descriptor (ECMA 167 2/9.4) */
-struct BootDesc {
-	Uint8 structType;
-	Uint8 stdIdent[STD_ID_LEN];
-	Uint8 structVersion;
-	Uint8 reserved1;
-	EntityID architectureType;
-	EntityID bootIdent;
-	Uint32 bootExtLocation;
-	Uint32 bootExtLength;
-	Uint64 loadAddress;
-	Uint64 startAddress;
-	timestamp descCreationDateAndTime;
-	Uint16 flags;
-	Uint8 reserved2[32];
-	Uint8 bootUse[1906];
-};
-
-/* Boot flags (ECMA 167 2/9.4.12) */
-#define BOOT_FLAGS_ERASE	1
-
-/* Extent Descriptor (ECMA 167 3/7.1) */
-typedef struct {
-	Uint32 extLength;
-	Uint32 extLocation;
-} extent_ad;
-
-/* Descriptor Tag (ECMA 167 3/7.2) */
-typedef struct {
-	Uint16 tagIdent;
-	Uint16 descVersion;
-	Uint8 tagChecksum;
-	Uint8 reserved;
-	Uint16 tagSerialNum;
-	Uint16 descCRC;
-	Uint16 descCRCLength;
-	Uint32 tagLocation;
-} tag;
-
-/* Tag Identifiers (ECMA 167 3/7.2.1) */
-#define TID_UNUSED_DESC			0x0000U
-#define TID_PRIMARY_VOL_DESC		0x0001U
-#define TID_ANCHOR_VOL_DESC_PTR		0x0002U
-#define TID_VOL_DESC_PTR		0x0003U
-#define TID_IMP_USE_VOL_DESC		0x0004U
-#define TID_PARTITION_DESC		0x0005U
-#define TID_LOGICAL_VOL_DESC		0x0006U
-#define TID_UNALLOC_SPACE_DESC		0x0007U
-#define TID_TERMINATING_DESC		0x0008U
-#define TID_LOGICAL_VOL_INTEGRITY_DESC	0x0009U
-
-/* Tag Identifiers (ECMA 167 4/7.2.1) */
-#define TID_FILE_SET_DESC		0x0100U
-#define TID_FILE_IDENT_DESC		0x0101U
-#define TID_ALLOC_EXTENT_DESC		0x0102U
-#define TID_INDIRECT_ENTRY		0x0103U
-#define TID_TERMINAL_ENTRY		0x0104U
-#define TID_FILE_ENTRY			0x0105U
-#define TID_EXTENDED_ATTRE_HEADER_DESC	0x0106U
-#define TID_UNALLOCATED_SPACE_ENTRY	0x0107U
-#define TID_SPACE_BITMAP_DESC		0x0108U
-#define TID_PARTITION_INTEGRITY_ENTRY	0x0109U
-#define TID_EXTENDED_FILE_ENTRY		0x010AU
-
-/* NSR Descriptor (ECMA 167 3/9.1) */
-struct NSRDesc {
-	Uint8 structType;
-	Uint8 stdIdent[STD_ID_LEN];
-	Uint8 structVersion;
-	Uint8 reserved;
-	Uint8 structData[2040];
-};
-	
-/* Primary Volume Descriptor (ECMA 167 3/10.1) */
-struct PrimaryVolDesc {
-	tag descTag;
-	Uint32 volDescSeqNum;
-	Uint32 primaryVolDescNum;
-	dstring volIdent[32];
-	Uint16 volSeqNum;
-	Uint16 maxVolSeqNum;
-	Uint16 interchangeLvl;
-	Uint16 maxInterchangeLvl;
-	Uint32 charSetList;
-	Uint32 maxCharSetList;
-	dstring volSetIdent[128];
-	charspec descCharSet;
-	charspec explanatoryCharSet;
-	extent_ad volAbstract;
-	extent_ad volCopyright;
-	EntityID appIdent;
-	timestamp recordingDateAndTime;
-	EntityID impIdent;
-	Uint8 impUse[64];
-	Uint32 predecessorVolDescSeqLocation;
-	Uint16 flags;
-	Uint8 reserved[22];
-};
-
-/* Primary volume descriptor flags (ECMA 167 3/10.1.21) */
-#define VOL_SET_IDENT	1
-
-/* Anchor Volume Descriptor Pointer (ECMA 167 3/10.2) */
-struct AnchorVolDescPtr {
-	tag descTag;
-	extent_ad mainVolDescSeqExt;
-	extent_ad reserveVolDescSeqExt;
-	Uint8 reserved[480];
-};
-
-/* Volume Descriptor Pointer (ECMA 167 3/10.3) */
-struct VolDescPtr {
-	tag descTag;
-	Uint32 volDescSeqNum;
-	extent_ad nextVolDescSeqExt;
-	Uint8 reserved[484];
-};
-
-/* Implementation Use Volume Descriptor (ECMA 167 3/10.4) */
-struct ImpUseVolDesc {
-	tag descTag;
-	Uint32 volDescSeqNum;
-	EntityID impIdent;
-	Uint8 impUse[460];
-};
-
-/* Partition Descriptor (ECMA 167 3/10.5) */
-struct PartitionDesc {
-	tag descTag;
-	Uint32 volDescSeqNum;
-	Uint16 partitionFlags;
-	Uint16 partitionNumber;
-	EntityID partitionContents;
-	Uint8 partitionContentsUse[128];
-	Uint32 accessType;
-	Uint32 partitionStartingLocation;
-	Uint32 partitionLength;
-	EntityID impIdent;
-	Uint8 impUse[128];
-	Uint8 reserved[156];
-};
-
-/* Partition Flags (ECMA 167 3/10.5.3) */
-#define PARTITION_FLAGS_ALLOC	1
-
-/* Partition Contents (ECMA 167 3/10.5.5) */
-#define PARTITION_CONTENTS_FDC01	"+FDC01"
-#define PARTITION_CONTENTS_CD001	"+CD001"
-#define PARTITION_CONTENTS_CDW02	"+CDW02"
-#define PARTITION_CONTENTS_NSR02	"+NSR02"
-#define PARTITION_CONTENTS_NSR03	"+NSR03"
-
-/* Partition Access Types (ECMA 167 3/10.5.7) */
-#define PARTITION_ACCESS_NONE	0
-#define PARTITION_ACCESS_R	1
-#define PARTITION_ACCESS_WO	2
-#define PARTITION_ACCESS_RW	3
-#define PARTITION_ACCESS_OW	4
-
-/* Logical Volume Descriptor (ECMA 167 3/10.6) */
-struct LogicalVolDesc {
-	tag descTag;
-	Uint32 volDescSeqNum;
-	charspec descCharSet;
-	dstring logicalVolIdent[128];
-	Uint32 logicalBlockSize;
-	EntityID domainIdent;
-	Uint8 logicalVolContentsUse[16]; /* used to find fileset */
-	Uint32 mapTableLength;
-	Uint32 numPartitionMaps;
-	EntityID impIdent;
-	Uint8 impUse[128];
-	extent_ad integritySeqExt;
-	Uint8 partitionMaps[0];
-};
-
-/* Generic Partition Map (ECMA 167 3/10.7.1) */
-struct GenericPartitionMap {
-	Uint8 partitionMapType;
-	Uint8 partitionMapLength;
-	Uint8 partitionMapping[0];
-};
-
-/* Partition Map Type (ECMA 167 3/10.7.1.1) */
-#define PARTITION_MAP_TYPE_NONE		0
-#define PARTITION_MAP_TYPE_1		1
-#define PARTITION_MAP_TYPE_2		2
-
-/* Type 1 Partition Map (ECMA 167 3/10.7.2) */
-struct GenericPartitionMap1 {
-	Uint8 partitionMapType;
-	Uint8 partitionMapLength;
-	Uint16 volSeqNum;
-	Uint16 partitionNum;
-};
-
-/* Type 2 Partition Map (ECMA 167 3/10.7.3) */
-struct GenericPartitionMap2 {
-	Uint8 partitionMapType; /* 2 */
-	Uint8 partitionMapLength; 
-	Uint8 partitionIdent[62];
-};
-
-/* Unallocated Space Descriptor (ECMA 167 3/10.8) */
-struct UnallocatedSpaceDesc {
-	tag descTag;
-	Uint32 volDescSeqNum;
-	Uint32 numAllocDescs;
-	extent_ad allocDescs[0];
-};
-
-/* Terminating Descriptor (ECMA 3/10.9) */
-struct TerminatingDesc {
-	tag descTag;
-	Uint8 reserved[496];
-};
-
-struct GenericDesc
-{
-        tag descTag;
-        Uint32 volDescSeqNum;
-};
-
-/* Logical Volume Integrity Descriptor (ECMA 167 3/10.10) */
-struct LogicalVolIntegrityDesc {
-	tag descTag;
-	timestamp recordingDateAndTime;
-	Uint32 integrityType;
-	extent_ad nextIntegrityExt;
-	Uint8 logicalVolContentsUse[32];
-	Uint32 numOfPartitions;
-	Uint32 lengthOfImpUse;
-	Uint32 freeSpaceTable[0];
-	Uint32 sizeTable[0];
-	Uint8 impUse[0];
-};
-
-/* Integrity Types (ECMA 167 3/10.10.3) */
-#define INTEGRITY_TYPE_OPEN	0
-#define INTEGRITY_TYPE_CLOSE	1
-
-/* Recorded Address (ECMA 167 4/7.1) */
-typedef struct {
-	Uint32 logicalBlockNum;
-	Uint16 partitionReferenceNum;
-} lb_addr;
-
-/* Extent interpretation (ECMA 167 4/14.14.1.1) */
-#define EXTENT_RECORDED_ALLOCATED               0x00
-#define EXTENT_NOT_RECORDED_ALLOCATED           0x01
-#define EXTENT_NOT_RECORDED_NOT_ALLOCATED       0x02
-#define EXTENT_NEXT_EXTENT_ALLOCDECS            0x03
-
-/* Long Allocation Descriptor (ECMA 167 4/14.14.2) */
-typedef struct {
-	Uint32 extLength;
-	lb_addr extLocation;
-	Uint8 impUse[6];
-} long_ad;
-	/* upper 2 bits of extLength indicate type */
-
-/* File Set Descriptor (ECMA 167 4/14.1) */
-struct FileSetDesc {
-	tag descTag;
-	timestamp recordingDateAndTime;
-	Uint16 interchangeLvl;
-	Uint16 maxInterchangeLvl;
-	Uint32 charSetList;
-	Uint32 maxCharSetList;
-	Uint32 fileSetNum;
-	Uint32 fileSetDescNum;
-	charspec logicalVolIdentCharSet;
-	dstring logicalVolIdent[128];
-	charspec fileSetCharSet;
-	dstring fileSetIdent[32];
-	dstring copyrightFileIdent[32];
-	dstring abstractFileIdent[32];
-	long_ad rootDirectoryICB;
-	EntityID domainIdent;
-	long_ad nextExt;
-	long_ad streamDirectoryICB;
-	Uint8 reserved[32];
-};
-
-/* Short Allocation Descriptor (ECMA 167 4/14.14.1) */
-typedef struct {
-	Uint32 extLength;
-	Uint32 extPosition;
-} short_ad;
-
-/* Partition Header Descriptor (ECMA 167 4/14.3) */
-struct PartitionHeaderDesc {
-	short_ad unallocatedSpaceTable;
-	short_ad unallocatedSpaceBitmap;
-	short_ad partitionIntegrityTable;
-	short_ad freedSpaceTable;
-	short_ad freedSpaceBitmap;
-	Uint8 reserved[88];
-};
-
-/* File Identifier Descriptor (ECMA 167 4/14.4) */
-struct FileIdentDesc
-{
-	tag descTag;
-	Uint16 fileVersionNum; /* 1 */
-	Uint8 fileCharacteristics;
-	Uint8 lengthFileIdent;
-	long_ad icb;
-	Uint16 lengthOfImpUse;
-	Uint8 impUse[0];
-	Uint8 fileIdent[0];
-	Uint8 padding[0];
-};
-
-/* File Characteristics (ECMA 167 4/14.4.3) */
-#define FILE_HIDDEN	1
-#define FILE_DIRECTORY	2
-#define FILE_DELETED	4
-#define FILE_PARENT	8
-#define FILE_METADATA	0x10 /* UDF 2.0 */
-
-/* Allocation Ext Descriptor (ECMA 167 4/14.5) */
-struct AllocExtDesc
-{
-	tag descTag;
-	Uint32 previousAllocExtLocation;
-	Uint32 lengthAllocDescs;
-};
-
-/* ICB Tag (ECMA 167 4/14.6) */
-typedef struct {
-	Uint32 priorRecordedNumDirectEntries;
-	Uint16 strategyType;
-	Uint16 strategyParameter;
-	Uint16 numEntries;
-	Uint8 reserved;
-	Uint8 fileType;
-	lb_addr parentICBLocation;
-	Uint16 flags;
-} icbtag;
-
-/* ICB File Type (ECMA 167 4/14.6.6) */
-#define FILE_TYPE_NONE		0x00U
-#define FILE_TYPE_UNALLOC	0x01U
-#define FILE_TYPE_INTEGRITY	0x02U
-#define FILE_TYPE_INDIRECT	0x03U
-#define FILE_TYPE_DIRECTORY	0x04U
-#define FILE_TYPE_REGULAR	0x05U
-#define FILE_TYPE_BLOCK		0x06U
-#define FILE_TYPE_CHAR		0x07U
-#define FILE_TYPE_EXTENDED	0x08U
-#define FILE_TYPE_FIFO		0x09U
-#define FILE_TYPE_SOCKET	0x0aU
-#define FILE_TYPE_TERMINAL	0x0bU
-#define FILE_TYPE_SYMLINK	0x0cU
-#define FILE_TYPE_STREAMDIR	0x0dU /* ECMA 167 4/13 */
-
-/* ICB Flags (ECMA 167 4/14.6.8) */
-#define ICB_FLAG_ALLOC_MASK	0x0007U
-#define ICB_FLAG_SORTED		0x0008U
-#define ICB_FLAG_NONRELOCATABLE	0x0010U
-#define ICB_FLAG_ARCHIVE	0x0020U
-#define ICB_FLAG_SETUID		0x0040U
-#define ICB_FLAG_SETGID		0x0080U
-#define ICB_FLAG_STICKY		0x0100U
-#define ICB_FLAG_CONTIGUOUS	0x0200U
-#define ICB_FLAG_SYSTEM		0x0400U
-#define ICB_FLAG_TRANSFORMED	0x0800U
-#define ICB_FLAG_MULTIVERSIONS	0x1000U
-
-/* ICB Flags Allocation type(ECMA 167 4/14.6.8) */
-#define ICB_FLAG_AD_SHORT	0
-#define ICB_FLAG_AD_LONG	1
-#define ICB_FLAG_AD_EXTENDED	2
-#define ICB_FLAG_AD_IN_ICB	3
-
-/* Indirect Entry (ECMA 167 4/14.7) */
-struct IndirectEntry {
-	tag descTag;
-	icbtag icbTag;
-	long_ad indirectICB;
-};
-
-/* Terminal Entry (ECMA 167 4/14.8) */
-struct TerminalEntry {
-	tag descTag;
-	icbtag icbTag;
-};
-
-/* File Entry (ECMA 167 4/14.9) */
-struct FileEntry {
-	tag			descTag;
-	icbtag		icbTag;
-	Uint32		uid;
-	Uint32		gid;
-	Uint32		permissions;
-	Uint16		fileLinkCount;
-	Uint8		recordFormat;
-	Uint8		recordDisplayAttr;
-	Uint32		recordLength;
-	Uint64		informationLength;
-	Uint64		logicalBlocksRecorded;
-	timestamp	accessTime;
-	timestamp	modificationTime;
-	timestamp	attrTime;
-	Uint32		checkpoint;
-	long_ad		extendedAttrICB;
-	EntityID	impIdent;
-	Uint64		uniqueID; /* 0= root, 16- (2^32-1) */
-	Uint32		lengthExtendedAttr;
-	Uint32		lengthAllocDescs;
-	Uint8		extendedAttr[0];
-	Uint8		allocDescs[0];
-};
-
-/* File Permissions (ECMA 167 4/14.9.5) */
-#define PERM_O_EXEC	0x00000001U
-#define PERM_O_WRITE	0x00000002U
-#define PERM_O_READ	0x00000004U
-#define PERM_O_CHATTR	0x00000008U
-#define PERM_O_DELETE	0x00000010U
-#define PERM_G_EXEC	0x00000020U
-#define PERM_G_WRITE	0x00000040U
-#define PERM_G_READ	0x00000080U
-#define PERM_G_CHATTR	0x00000100U
-#define PERM_G_DELETE	0x00000200U
-#define PERM_U_EXEC	0x00000400U
-#define PERM_U_WRITE	0x00000800U
-#define PERM_U_READ	0x00001000U
-#define PERM_U_CHATTR	0x00002000U
-#define PERM_U_DELETE	0x00004000U
-
-/* File Record Format (ECMA 167 4/14.9.7) */
-#define RECORD_FMT_NONE			0
-#define RECORD_FMT_FIXED_PAD		1
-#define RECORD_FMT_FIXED		2
-#define RECORD_FMT_VARIABLE8		3
-#define RECORD_FMT_VARIABLE16		4
-#define RECORD_FMT_VARIABLE16_MSB	5
-#define RECORD_FMT_VARIABLE32		6
-#define RECORD_FMT_PRINT		7
-#define RECORD_FMT_LF			8
-#define RECORD_FMT_CR			9
-#define RECORD_FMT_CRLF			10
-#define RECORD_FMT_LFCR			10
-
-/* Extended Attribute Header Descriptor (ECMA 167 4/14.10.1) */
-struct ExtendedAttrHeaderDesc {
-	tag descTag;
-	Uint32 impAttrLocation;
-	Uint32 appAttrLocation;
-};
-
-/* Generic Attribute Format (ECMA 4/14.10.2) */
-struct GenericAttrFormat {
-	Uint32 attrType;
-	Uint8 attrSubtype;
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint8 attrData[0];
-};
-
-/* Character Set Attribute Format (ECMA 4/14.10.3) */
-struct CharSetAttrFormat {
-	Uint32 attrType;		/* 1 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint32 escapeSeqLength;
-	Uint8 charSetType;
-	Uint8 escapeSeq[0];
-};
-
-/* Alternate Permissions (ECMA 167 4/14.10.4) */
-struct AlternatePermissionsExtendedAttr {
-	Uint32 attrType;		/* 3 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint16 ownerIdent;
-	Uint16 groupIdent;
-	Uint16 permission;
-};
-
-/* File Times Extended Attribute (ECMA 167 4/14.10.5) */
-struct FileTimesExtendedAttr {
-	Uint32 attrType;		/* 5 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint32 dataLength;
-	Uint32 fileTimeExistence;
-	Uint8 fileTimes;
-};
-
-/* FileTimeExistence (ECMA 167 4/14.10.5.6) */
-#define FTE_CREATION	0
-#define FTE_DELETION	2
-#define FTE_EFFECTIVE	3
-#define FTE_BACKUP	5
-
-/* Information Times Extended Attribute (ECMA 167 4/14.10.6) */
-struct InfoTimesExtendedAttr {
-	Uint32 attrType;		/* 6 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint32 dataLength;
-	Uint32 infoTimeExistence;
-	Uint8 infoTimes[0];
-};
-
-/* Device Specification Extended Attribute (ECMA 167 4/14.10.7) */
-struct DeviceSpecificationExtendedAttr {
-	Uint32 attrType;		/* 12 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint32 impUseLength;
-	Uint32 majorDeviceIdent;
-	Uint32 minorDeviceIdent;
-	Uint8 impUse[0];
-};
-
-/* Implementation Use Extended Attr (ECMA 167 4/14.10.8) */
-struct ImpUseExtendedAttr {
-	Uint32 attrType;		/* 2048 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint32 impUseLength;
-	EntityID impIdent;
-	Uint8 impUse[0];
-};
-
-/* Application Use Extended Attribute (ECMA 167 4/14.10.9) */
-struct AppUseExtendedAttr {
-	Uint32 attrType;		/* 65536 */
-	Uint8 attrSubtype;		/* 1 */
-	Uint8 reserved[3];
-	Uint32 attrLength;
-	Uint32 appUseLength;
-	EntityID appIdent;
-	Uint8 appUse[0];
-};
-
-#define EXTATTR_CHAR_SET	1
-#define EXTATTR_ALT_PERMS	3
-#define EXTATTR_FILE_TIMES	5
-#define EXTATTR_INFO_TIMES	6
-#define EXTATTR_DEV_SPEC	12
-#define EXTATTR_IMP_USE		2048
-#define EXTATTR_APP_USE		65536
-
-
-/* Unallocated Space Entry (ECMA 167 4/14.11) */
-struct UnallocatedSpaceEntry {
-	tag descTag;
-	icbtag icbTag;
-	Uint32 lengthAllocDescs;
-	Uint8 allocDescs[0];
-};
-
-/* Space Bitmap Descriptor (ECMA 167 4/14.12) */
-struct SpaceBitmapDesc {
-	tag descTag;
-	Uint32 numOfBits;
-	Uint32 numOfBytes;
-	Uint8 bitmap[0];
-};
-
-/* Partition Integrity Entry (ECMA 167 4/14.13) */
-struct PartitionIntegrityEntry {
-	tag descTag;
-	icbtag icbTag;
-	timestamp recordingDateAndTime;
-	Uint8 integrityType;
-	Uint8 reserved[175];
-	EntityID impIdent;
-	Uint8 impUse[256];
-};
-
-/* Extended Allocation Descriptor (ECMA 167 4/14.14.3) */
-typedef struct { /* ECMA 167 4/14.14.3 */
-	Uint32 extLength;
-	Uint32 recordedLength;
-	Uint32 informationLength;
-	lb_addr extLocation;
-} ext_ad;
-
-/* Logical Volume Header Descriptor (ECMA 167 4/14.5) */
-struct LogicalVolHeaderDesc {
-	Uint64 uniqueID;
-	Uint8 reserved[24];
-};
-
-/* Path Component (ECMA 167 4/14.16.1) */
-struct PathComponent {
-	Uint8 componentType;
-	Uint8 lengthComponentIdent;
-	Uint16 componentFileVersionNum;
-	dstring componentIdent[0];
-};
-
-/* File Entry (ECMA 167 4/14.17) */
-struct ExtendedFileEntry {
-	tag			descTag;
-	icbtag		icbTag;
-	Uint32		uid;
-	Uint32		gid;
-	Uint32		permissions;
-	Uint16		fileLinkCount;
-	Uint8		recordFormat;
-	Uint8		recordDisplayAttr;
-	Uint32		recordLength;
-	Uint64		informationLength;
-	Uint64		objectSize;
-	Uint64		logicalBlocksRecorded;
-	timestamp	accessTime;
-	timestamp	modificationTime;
-	timestamp	createTime;
-	timestamp	attrTime;
-	Uint32		checkpoint;
-	Uint32		reserved;
-	long_ad		extendedAttrICB;
-	long_ad		streamDirectoryICB;
-	EntityID	impIdent;
-	Uint64		uniqueID;
-	Uint32		lengthExtendedAttr;
-	Uint32		lengthAllocDescs;
-	Uint8		extendedAttr[0];
-	Uint8		allocDescs[0];
-};
-#pragma pack()
-
-#endif /* !defined(_LINUX_UDF_167_H) */
diff -Nru a/include/linux/udf_fs.h b/include/linux/udf_fs.h
--- a/include/linux/udf_fs.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/udf_fs.h	Fri Mar 15 17:51:01 2002
@@ -31,14 +31,14 @@
  *
  */
 
-#if !defined(_LINUX_UDF_FS_H)
-#define _LINUX_UDF_FS_H
+#ifndef _UDF_FS_H
+#define _UDF_FS_H 1
 
 #define UDF_PREALLOCATE
 #define UDF_DEFAULT_PREALLOC_BLOCKS	8
 
-#define UDFFS_DATE			"2001/10/10"
-#define UDFFS_VERSION			"0.9.5"
+#define UDFFS_DATE			"2002/03/11"
+#define UDFFS_VERSION			"0.9.6"
 
 #if !defined(UDFFS_RW)
 
@@ -66,4 +66,4 @@
 #define udf_info(f, a...) \
 		printk (KERN_INFO "UDF-fs INFO " f, ##a);
 
-#endif /* !defined(_LINUX_UDF_FS_H) */
+#endif /* _UDF_FS_H */
diff -Nru a/include/linux/udf_fs_i.h b/include/linux/udf_fs_i.h
--- a/include/linux/udf_fs_i.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/udf_fs_i.h	Fri Mar 15 17:51:01 2002
@@ -15,17 +15,17 @@
  *	Each contributing author retains all rights to their own work.
  */
 
-#if !defined(_LINUX_UDF_FS_I_H)
-#define _LINUX_UDF_FS_I_H
+#ifndef _UDF_FS_I_H
+#define _UDF_FS_I_H 1
 
 #ifdef __KERNEL__
 
-#ifndef _LINUX_UDF_167_H
+#ifndef _ECMA_167_H
 typedef struct
 {
 	__u32 logicalBlockNum;
 	__u16 partitionReferenceNum;
-} lb_addr;
+} __attribute__ ((packed)) lb_addr;
 #endif
 
 struct udf_inode_info
@@ -59,4 +59,4 @@
 #define UDF_GETVOLIDENT _IOR('l', 0x42, void *)
 #define UDF_RELOCATE_BLOCKS _IOWR('l', 0x43, long)
 
-#endif /* !defined(_LINUX_UDF_FS_I_H) */
+#endif /* _UDF_FS_I_H */
diff -Nru a/include/linux/udf_fs_sb.h b/include/linux/udf_fs_sb.h
--- a/include/linux/udf_fs_sb.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/udf_fs_sb.h	Fri Mar 15 17:51:03 2002
@@ -15,8 +15,8 @@
  *	Each contributing author retains all rights to their own work.
  */
 
-#if !defined(_LINUX_UDF_FS_SB_H)
-#define _LINUX_UDF_FS_SB_H
+#ifndef _UDF_FS_SB_H
+#define _UDF_FS_SB_H 1
 
 #pragma pack(1)
 
@@ -115,4 +115,4 @@
 	struct inode		*s_vat;
 };
 
-#endif /* !defined(_LINUX_UDF_FS_SB_H) */
+#endif /* _UDF_FS_SB_H */
diff -Nru a/include/linux/udf_udf.h b/include/linux/udf_udf.h
--- a/include/linux/udf_udf.h	Fri Mar 15 17:51:01 2002
+++ /dev/null	Wed Dec 31 16:00:00 1969
@@ -1,231 +0,0 @@
-#if !defined(_LINUX_UDF_UDF_H)
-#define _LINUX_UDF_UDF_H
-/*
- * udf_udf.h
- *
- * PURPOSE
- *	OSTA-UDF(tm) format specification [based on ECMA 167 standard].
- *	http://www.osta.org/
- *
- * CONTACTS
- *	E-mail regarding any portion of the Linux UDF file system should be
- *	directed to the development team mailing list (run by majordomo):
- *		linux_udf@hpesjro.fc.hp.com
- *
- * COPYRIGHT
- *	This file is distributed under the terms of the GNU General Public
- *	License (GPL). Copies of the GPL can be obtained from:
- *		ftp://prep.ai.mit.edu/pub/gnu/GPL
- *	Each contributing author retains all rights to their own work.
- *
- * HISTORY
- *	July 1, 1997 - Andrew E. Mileski
- *	Written, tested, and released.
- *
- * 10/2/98 dgb	changed UDF_ID_DEVELOPER
- * 11/26/98 bf  changed UDF_ID_DEVELOPER, 
- * 12/5/98 dgb  updated include file hierarchy, more UDF definitions
- */
-
-/* based on ECMA 167 structure definitions */
-#include <linux/udf_167.h>
-
-#pragma pack(1)
-
-/* -------- Basic types and constants ----------- */
-/* UDF character set (UDF 1.50 2.1.2) */
-#define UDF_CHAR_SET_TYPE	0
-#define UDF_CHAR_SET_INFO	"OSTA Compressed Unicode"
-
-#define UDF_ID_DEVELOPER	"*Linux UDFFS"
- 
-/* UDF 1.02 2.2.6.4 */
-struct LogicalVolIntegrityDescImpUse
-{
-	EntityID	impIdent;
-	Uint32		numFiles;
-	Uint32		numDirs;
-	Uint16		minUDFReadRev;
-	Uint16		minUDFWriteRev;
-	Uint16		maxUDFWriteRev;
-};
-
-/* UDF 1.02 2.2.7.2 */
-/* LVInformation may be present in ImpUseVolDesc.impUse */
-struct ImpUseVolDescImpUse
-{
-	charspec	LVICharset;
-	dstring		logicalVolIdent[128];
-	dstring		LVInfo1[36];
-	dstring		LVInfo2[36];
-	dstring		LVInfo3[36];
-	EntityID	impIdent;
-	Uint8		impUse[128];
-};
-
-struct UdfPartitionMap2
-{
-        Uint8           partitionMapType;
-        Uint8           partitionMapLength;
-        Uint8           reserved1[2];
-        EntityID        partIdent;
-        Uint16          volSeqNum;
-        Uint16          partitionNum;
-        Uint8           reserved2[24];
-};
-
-/* UDF 1.5 2.2.8 */
-struct VirtualPartitionMap
-{
-	Uint8		partitionMapType;	/* 2 */
-	Uint8		partitionMapLength;	/* 64 */
-	Uint8		reserved1[2];		/* #00 */
-	EntityID	partIdent;
-	Uint16		volSeqNum;
-	Uint16		partitionNum;
-	Uint8		reserved2[24];		/* #00 */
-};
-
-/* UDF 1.5 2.2.9 */
-struct SparablePartitionMap
-{
-	Uint8		partitionMapType;	/* 2 */
-	Uint8		partitionMapLength;	/* 64 */
-	Uint8		reserved1[2];		/* #00 */
-	EntityID	partIdent;		/* Flags = 0 */
-						/* Id = UDF_ID_SPARABLE */
-						/* IdSuf = 2.1.5.3 */
-	Uint16		volSeqNum;
-	Uint16		partitionNum;
-	Uint16		packetLength;		/* 32 */
-	Uint8		numSparingTables;
-	Uint8		reserved2[1];		/* #00 */
-	Uint32		sizeSparingTable;
-	Uint32		locSparingTable[4];
-};
- 
-/* DVD Copyright Management Info, see UDF 1.02 3.3.4.5.1.2 */
-/* when ImpUseExtendedAttr.impIdent= "*UDF DVD CGMS Info" */
-struct DVDCopyrightImpUse {
-	Uint16 headerChecksum;
-	Uint8  CGMSInfo;
-	Uint8  dataType;
-	Uint8  protectionSystemInfo[4];
-};
-
-/* the impUse of long_ad used in AllocDescs  - UDF 1.02 2.3.10.1 */
-struct ADImpUse
-{
-	Uint16 flags;
-	Uint8  impUse[4];
-};
-
-/* UDF 1.02 2.3.10.1 */
-#define UDF_EXTENT_LENGTH_MASK		0x3FFFFFFF
-#define UDF_EXTENT_FLAG_MASK		0xc0000000
-#define UDF_EXTENT_FLAG_ERASED		0x40000000
-
-/* 
- * Important!  VirtualAllocationTables are 
- * very different between 1.5 and 2.0!
- */
-
-/* ----------- 1.5 ------------- */
-/* UDF 1.5 2.2.10 */
-#define FILE_TYPE_VAT15		0x0U
-
-/* UDF 1.5 2.2.10 - VAT layout: */
-struct VirutalAllocationTable15 {
-	Uint32 VirtualSector[0];
-	EntityID	ident;
-	Uint32	previousVATICB;
-   };  
-/* where number of VirtualSector's is (VATSize-36)/4 */
-
-/* ----------- 2.0 ------------- */
-/* UDF 2.0 2.2.10 */
-#define FILE_TYPE_VAT20		0xf8U
-
-/* UDF 2.0 2.2.10 (different from 1.5!) */
-struct VirtualAllocationTable20 {
-	Uint16 lengthHeader;
-	Uint16 lengthImpUse;
-	dstring logicalVolIdent[128];
-	Uint32	previousVatICBLoc;
-	Uint32  numFIDSFiles;
-	Uint32  numFIDSDirectories; /* non-parent */
-	Uint16  minReadRevision;
-	Uint16	minWriteRevision;
-	Uint16  maxWriteRevision;
-	Uint16  reserved;
-	Uint8	impUse[0];
-	Uint32  vatEntry[0];
-};
-
-/* ----------- 2.01 ------------- */
-/* UDF 2.01 6.11 */
-#define FILE_TYPE_REALTIME	0xf9U
-
-/* Sparing maps, see UDF 1.5 2.2.11 */
-typedef struct {
-	Uint32  origLocation;
-	Uint32  mappedLocation;
-} SparingEntry;
-
-/* sparing maps, see UDF 2.0 2.2.11 */
-struct SparingTable {
-	tag 	descTag;
-	EntityID sparingIdent; /* *UDF Sparing Table */
-	Uint16   reallocationTableLen;
-	Uint16   reserved;	/* #00 */
-	Uint32   sequenceNum;
-	SparingEntry mapEntry[0];
-};
-
-/* Entity Identifiers (UDF 1.50 6.1) */
-#define	UDF_ID_COMPLIANT	"*OSTA UDF Compliant"
-#define UDF_ID_LV_INFO		"*UDF LV Info"
-#define UDF_ID_FREE_EA		"*UDF FreeEASpace"
-#define UDF_ID_FREE_APP_EA	"*UDF FreeAppEASpace"
-#define UDF_ID_DVD_CGMS		"*UDF DVD CGMS Info"
-#define UDF_ID_OS2_EA		"*UDF OS/2 EA"
-#define UDF_ID_OS2_EA_LENGTH	"*UDF OS/2 EALength"
-#define UDF_ID_MAC_VOLUME	"*UDF Mac VolumeInfo"
-#define UDF_ID_MAC_FINDER	"*UDF Mac FinderInfo"
-#define UDF_ID_MAC_UNIQUE	"*UDF Mac UniqueIDTable"
-#define UDF_ID_MAC_RESOURCE	"*UDF Mac ResourceFork"
-#define UDF_ID_VIRTUAL		"*UDF Virtual Partition"
-#define UDF_ID_SPARABLE		"*UDF Sparable Partition"
-#define UDF_ID_ALLOC		"*UDF Virtual Alloc Tbl"
-#define UDF_ID_SPARING		"*UDF Sparing Table"
-
-/* Operating System Identifiers (UDF 1.50 6.3) */
-#define UDF_OS_CLASS_UNDEF	0x00U
-#define UDF_OS_CLASS_DOS	0x01U
-#define UDF_OS_CLASS_OS2	0x02U
-#define UDF_OS_CLASS_MAC	0x03U
-#define UDF_OS_CLASS_UNIX	0x04U
-#define UDF_OS_CLASS_WIN95	0x05U
-#define UDF_OS_CLASS_WINNT	0x06U
-#define UDF_OS_ID_UNDEF		0x00U
-#define UDF_OS_ID_DOS		0x00U
-#define UDF_OS_ID_OS2		0x00U
-#define UDF_OS_ID_MAC		0x00U
-#define UDF_OS_ID_UNIX		0x00U
-#define UDF_OS_ID_WIN95		0x00U
-#define UDF_OS_ID_WINNT		0x00U
-#define UDF_OS_ID_AIX		0x01U
-#define UDF_OS_ID_SOLARIS	0x02U
-#define UDF_OS_ID_HPUX		0x03U
-#define UDF_OS_ID_IRIX		0x04U
-#define UDF_OS_ID_LINUX		0x05U
-#define UDF_OS_ID_MKLINUX	0x06U
-#define UDF_OS_ID_FREEBSD	0x07U
-
-#define UDF_NAME_PAD	4
-#define UDF_NAME_LEN	255
-#define UDF_PATH_LEN	1023
-
-#pragma pack()
-
-#endif /* !defined(_LINUX_UDF_FMT_H) */
diff -Nru a/include/linux/videodev.h b/include/linux/videodev.h
--- a/include/linux/videodev.h	Fri Mar 15 17:51:03 2002
+++ b/include/linux/videodev.h	Fri Mar 15 17:51:03 2002
@@ -4,6 +4,18 @@
 #include <linux/types.h>
 #include <linux/version.h>
 
+#if 0
+/*
+ * v4l2 is still work-in-progress, integration planed for 2.5.x
+ *   v4l2 project homepage:   http://www.thedirks.org/v4l2/
+ *   patches available from:  http://bytesex.org/patches/
+ */ 
+# define HAVE_V4L2 1
+# include <linux/videodev2.h>
+#else
+# undef HAVE_V4L2
+#endif
+
 #ifdef __KERNEL__
 
 #include <linux/poll.h>
@@ -13,24 +25,25 @@
 struct video_device
 {
 	struct module *owner;
-	char name[32];
-	int type;
+     	char name[32];
+ 	int type;       /* v4l1 */
+ 	int type2;      /* v4l2 */
 	int hardware;
+	int minor;
 
-	int (*open)(struct video_device *, int mode);
-	void (*close)(struct video_device *);
-	long (*read)(struct video_device *, char *, unsigned long, int noblock);
-	/* Do we need a write method ? */
-	long (*write)(struct video_device *, const char *, unsigned long, int noblock);
-#if LINUX_VERSION_CODE >= 0x020100
-	unsigned int (*poll)(struct video_device *, struct file *, poll_table *);
-#endif
-	int (*ioctl)(struct video_device *, unsigned int , void *);
-	int (*mmap)(struct vm_area_struct *vma, struct video_device *, const char *, unsigned long);
-	int (*initialize)(struct video_device *);	
+ 	/* new interface -- we will use file_operations directly
+ 	 * like soundcore does.
+ 	 * kernel_ioctl() will be called by video_generic_ioctl.
+ 	 * video_generic_ioctl() does the userspace copying of the
+ 	 * ioctl arguments */
+ 	struct file_operations *fops;
+ 	int (*kernel_ioctl)(struct inode *inode, struct file *file,
+ 			    unsigned int cmd, void *arg);
 	void *priv;		/* Used to be 'private' but that upsets C++ */
-	int busy;
-	int minor;
+
+	/* for videodev.c intenal usage -- don't touch */
+	int users;
+	struct semaphore lock;
 	devfs_handle_t devfs_handle;
 };
 
@@ -43,8 +56,13 @@
 #define VFL_TYPE_VTX		3
 
 extern void video_unregister_device(struct video_device *);
-#endif
+extern struct video_device* video_devdata(struct file*);
 
+extern int video_exclusive_open(struct inode *inode, struct file *file);
+extern int video_exclusive_release(struct inode *inode, struct file *file);
+extern int video_generic_ioctl(struct inode *inode, struct file *file,
+			       unsigned int cmd, unsigned long arg);
+#endif /* __KERNEL__ */
 
 #define VID_TYPE_CAPTURE	1	/* Can capture */
 #define VID_TYPE_TUNER		2	/* Can tune */
@@ -150,6 +168,7 @@
 #define VIDEO_AUDIO_VOLUME	4
 #define VIDEO_AUDIO_BASS	8
 #define VIDEO_AUDIO_TREBLE	16	
+#define VIDEO_AUDIO_BALANCE	32
 	char    name[16];
 #define VIDEO_SOUND_MONO	1
 #define VIDEO_SOUND_STEREO	2
@@ -379,4 +398,10 @@
 #define VID_HARDWARE_MEYE	32	/* Sony Vaio MotionEye cameras */
 #define VID_HARDWARE_CPIA2	33
 
-#endif
+#endif /* __LINUX_VIDEODEV_H */
+
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ * End:
+ */
diff -Nru a/include/linux/wireless.h b/include/linux/wireless.h
--- a/include/linux/wireless.h	Fri Mar 15 17:51:01 2002
+++ b/include/linux/wireless.h	Fri Mar 15 17:51:01 2002
@@ -1,10 +1,10 @@
 /*
  * This file define a set of standard wireless extensions
  *
- * Version :	13	6.12.01
+ * Version :	14	25.1.02
  *
  * Authors :	Jean Tourrilhes - HPL - <jt@hpl.hp.com>
- * Copyright (c) 1997-2001 Jean Tourrilhes, All Rights Reserved.
+ * Copyright (c) 1997-2002 Jean Tourrilhes, All Rights Reserved.
  */
 
 #ifndef _LINUX_WIRELESS_H
@@ -40,7 +40,7 @@
  *	# include/linux/netdevice.h (one place)
  *	# include/linux/proc_fs.h (one place)
  *
- * New driver API (2001 -> onward) :
+ * New driver API (2002 -> onward) :
  * -------------------------------
  * This file is only concerned with the user space API and common definitions.
  * The new driver API is defined and documented in :
@@ -49,6 +49,11 @@
  * Note as well that /proc/net/wireless implementation has now moved in :
  *	# include/linux/wireless.c
  *
+ * Wireless Events (2002 -> onward) :
+ * --------------------------------
+ * Events are defined at the end of this file, and implemented in :
+ *	# include/linux/wireless.c
+ *
  * Other comments :
  * --------------
  * Do not add here things that are redundant with other mechanisms
@@ -75,7 +80,7 @@
  * (there is some stuff that will be added in the future...)
  * I just plan to increment with each new version.
  */
-#define WIRELESS_EXT	13
+#define WIRELESS_EXT	14
 
 /*
  * Changes :
@@ -141,6 +146,13 @@
  *	- Document creation of new driver API.
  *	- Extract union iwreq_data from struct iwreq (for new driver API).
  *	- Rename SIOCSIWNAME as SIOCSIWCOMMIT
+ *
+ * V13 to V14
+ * ----------
+ *	- Wireless Events support : define struct iw_event
+ *	- Define additional specific event numbers
+ *	- Add "addr" and "param" fields in union iwreq_data
+ *	- AP scanning stuff (SIOCSIWSCAN and friends)
  */
 
 /**************************** CONSTANTS ****************************/
@@ -175,6 +187,8 @@
 #define SIOCSIWAP	0x8B14		/* set access point MAC addresses */
 #define SIOCGIWAP	0x8B15		/* get access point MAC addresses */
 #define SIOCGIWAPLIST	0x8B17		/* get list of access point in range */
+#define SIOCSIWSCAN	0x8B18		/* trigger scanning */
+#define SIOCGIWSCAN	0x8B19		/* get scanning results */
 
 /* 802.11 specific support */
 #define SIOCSIWESSID	0x8B1A		/* set ESSID (network name) */
@@ -238,6 +252,15 @@
 #define IW_IS_SET(cmd)	(!((cmd) & 0x1))
 #define IW_IS_GET(cmd)	((cmd) & 0x1)
 
+/* ----------------------- WIRELESS EVENTS ----------------------- */
+/* Those are *NOT* ioctls, do not issue request on them !!! */
+/* Most events use the same identifier as ioctl requests */
+
+#define IWEVTXDROP	0x8C00		/* Packet dropped to excessive retry */
+#define IWEVQUAL	0x8C01		/* Quality part of statistics */
+
+#define IWEVFIRST	0x8C00
+
 /* ------------------------- PRIVATE INFO ------------------------- */
 /*
  * The following is used with SIOCGIWPRIV. It allow a driver to define
@@ -340,6 +363,19 @@
 #define IW_RETRY_MAX		0x0002	/* Value is a maximum */
 #define IW_RETRY_RELATIVE	0x0004	/* Value is not in seconds/ms/us */
 
+/* Scanning request flags */
+#define IW_SCAN_DEFAULT		0x0000	/* Default scan of the driver */
+#define IW_SCAN_ALL_ESSID	0x0001	/* Scan all ESSIDs */
+#define IW_SCAN_THIS_ESSID	0x0002	/* Scan only this ESSID */
+#define IW_SCAN_ALL_FREQ	0x0004	/* Scan all Frequencies */
+#define IW_SCAN_THIS_FREQ	0x0008	/* Scan only this Frequency */
+#define IW_SCAN_ALL_MODE	0x0010	/* Scan all Modes */
+#define IW_SCAN_THIS_MODE	0x0020	/* Scan only this Mode */
+#define IW_SCAN_ALL_RATE	0x0040	/* Scan all Bit-Rates */
+#define IW_SCAN_THIS_RATE	0x0080	/* Scan only this Bit-Rate */
+/* Maximum size of returned data */
+#define IW_SCAN_MAX_DATA	4096	/* In bytes */
+
 /****************************** TYPES ******************************/
 
 /* --------------------------- SUBTYPES --------------------------- */
@@ -466,9 +502,12 @@
 
 	struct iw_point	encoding;	/* Encoding stuff : tokens */
 	struct iw_param	power;		/* PM duration/timeout */
+	struct iw_quality qual;		/* Quality part of statistics */
 
 	struct sockaddr	ap_addr;	/* Access point address */
+	struct sockaddr	addr;		/* Destination address (hw) */
 
+	struct iw_param	param;		/* Other small parameters */
 	struct iw_point	data;		/* Other large parameters */
 };
 
@@ -595,5 +634,36 @@
 	__u16		get_args;	/* Type and number of args */
 	char		name[IFNAMSIZ];	/* Name of the extension */
 };
+
+/* ----------------------- WIRELESS EVENTS ----------------------- */
+/*
+ * Wireless events are carried through the rtnetlink socket to user
+ * space. They are encapsulated in the IFLA_WIRELESS field of
+ * a RTM_NEWLINK message.
+ */
+
+/*
+ * A Wireless Event. Contains basically the same data as the ioctl...
+ */
+struct iw_event
+{
+	__u16		len;			/* Real lenght of this stuff */
+	__u16		cmd;			/* Wireless IOCTL */
+	union iwreq_data	u;		/* IOCTL fixed payload */
+};
+
+/* Size of the Event prefix (including padding and alignement junk) */
+#define IW_EV_LCP_LEN	(sizeof(struct iw_event) - sizeof(union iwreq_data))
+/* Size of the various events */
+#define IW_EV_CHAR_LEN	(IW_EV_LCP_LEN + IFNAMSIZ)
+#define IW_EV_UINT_LEN	(IW_EV_LCP_LEN + sizeof(__u32))
+#define IW_EV_FREQ_LEN	(IW_EV_LCP_LEN + sizeof(struct iw_freq))
+#define IW_EV_POINT_LEN	(IW_EV_LCP_LEN + sizeof(struct iw_point))
+#define IW_EV_PARAM_LEN	(IW_EV_LCP_LEN + sizeof(struct iw_param))
+#define IW_EV_ADDR_LEN	(IW_EV_LCP_LEN + sizeof(struct sockaddr))
+#define IW_EV_QUAL_LEN	(IW_EV_LCP_LEN + sizeof(struct iw_quality))
+
+/* Note : in the case of iw_point, the extra data will come at the
+ * end of the event */
 
 #endif	/* _LINUX_WIRELESS_H */
diff -Nru a/include/net/ip.h b/include/net/ip.h
--- a/include/net/ip.h	Fri Mar 15 17:51:03 2002
+++ b/include/net/ip.h	Fri Mar 15 17:51:03 2002
@@ -197,7 +197,8 @@
 		 * does not change, they drop every other packet in
 		 * a TCP stream using header compression.
 		 */
-		iph->id = (sk && sk->daddr) ? htons(inet_sk(sk)->id++) : 0;
+		iph->id = (sk && inet_sk(sk)->daddr) ?
+					htons(inet_sk(sk)->id++) : 0;
 	} else
 		__ip_select_ident(iph, dst);
 }
diff -Nru a/include/net/iw_handler.h b/include/net/iw_handler.h
--- a/include/net/iw_handler.h	Fri Mar 15 17:51:01 2002
+++ b/include/net/iw_handler.h	Fri Mar 15 17:51:01 2002
@@ -1,10 +1,10 @@
 /*
  * This file define the new driver API for Wireless Extensions
  *
- * Version :	2	6.12.01
+ * Version :	3	17.1.02
  *
  * Authors :	Jean Tourrilhes - HPL - <jt@hpl.hp.com>
- * Copyright (c) 2001 Jean Tourrilhes, All Rights Reserved.
+ * Copyright (c) 2001-2002 Jean Tourrilhes, All Rights Reserved.
  */
 
 #ifndef _IW_HANDLER_H
@@ -33,7 +33,7 @@
  *	o The user space interface is tied to ioctl because of the use
  *	  copy_to/from_user.
  *
- * New driver API (2001 -> onward) :
+ * New driver API (2002 -> onward) :
  * -------------------------------
  * The new driver API is just a bunch of standard functions (handlers),
  * each handling a specific Wireless Extension. The driver just export
@@ -206,7 +206,18 @@
  * will be needed...
  * I just plan to increment with each new version.
  */
-#define IW_HANDLER_VERSION	2
+#define IW_HANDLER_VERSION	3
+
+/*
+ * Changes :
+ *
+ * V2 to V3
+ * --------
+ *	- Move event definition in <linux/wireless.h>
+ *	- Add Wireless Event support :
+ *		o wireless_send_event() prototype
+ *		o iwe_stream_add_event/point() inline functions
+ */
 
 /**************************** CONSTANTS ****************************/
 
@@ -225,6 +236,7 @@
 #define IW_HEADER_TYPE_POINT	6	/* struct iw_point */
 #define IW_HEADER_TYPE_PARAM	7	/* struct iw_param */
 #define IW_HEADER_TYPE_ADDR	8	/* struct sockaddr */
+#define IW_HEADER_TYPE_QUAL	9	/* struct iw_quality */
 
 /* Handling flags */
 /* Most are not implemented. I just use them as a reminder of some
@@ -303,25 +315,6 @@
 	 * 'struct net_device' to here, to minimise bloat. */
 };
 
-/* ----------------------- WIRELESS EVENTS ----------------------- */
-/*
- * Currently we don't support events, so let's just plan for the
- * future...
- */
-
-/*
- * A Wireless Event.
- */
-// How do we define short header ? We don't want a flag on length.
-// Probably a flag on event ? Highest bit to zero...
-struct iw_event
-{
-	__u16		length;			/* Lenght of this stuff */
-	__u16		event;			/* Wireless IOCTL */
-	union	iwreq_data	header;		/* IOCTL fixed payload */
-	char		extra[0];		/* Optional IOCTL data */
-};
-
 /* ---------------------- IOCTL DESCRIPTION ---------------------- */
 /*
  * One of the main goal of the new interface is to deal entirely with
@@ -369,6 +362,88 @@
 extern int wireless_process_ioctl(struct ifreq *ifr, unsigned int cmd);
 
 /* Second : functions that may be called by driver modules */
-/* None yet */
 
-#endif	/* _LINUX_WIRELESS_H */
+/* Send a single event to user space */
+extern void wireless_send_event(struct net_device *	dev,
+				unsigned int		cmd,
+				union iwreq_data *	wrqu,
+				char *			extra);
+
+/* We may need a function to send a stream of events to user space.
+ * More on that later... */
+
+/************************* INLINE FUNTIONS *************************/
+/*
+ * Function that are so simple that it's more efficient inlining them
+ */
+
+/*------------------------------------------------------------------*/
+/*
+ * Wrapper to add an Wireless Event to a stream of events.
+ */
+static inline char *
+iwe_stream_add_event(char *	stream,		/* Stream of events */
+		     char *	ends,		/* End of stream */
+		     struct iw_event *iwe,	/* Payload */
+		     int	event_len)	/* Real size of payload */
+{
+	/* Check if it's possible */
+	if((stream + event_len) < ends) {
+		iwe->len = event_len;
+		memcpy(stream, (char *) iwe, event_len);
+		stream += event_len;
+	}
+	return stream;
+}
+
+/*------------------------------------------------------------------*/
+/*
+ * Wrapper to add an short Wireless Event containing a pointer to a
+ * stream of events.
+ */
+static inline char *
+iwe_stream_add_point(char *	stream,		/* Stream of events */
+		     char *	ends,		/* End of stream */
+		     struct iw_event *iwe,	/* Payload */
+		     char *	extra)
+{
+	int	event_len = IW_EV_POINT_LEN + iwe->u.data.length;
+	/* Check if it's possible */
+	if((stream + event_len) < ends) {
+		iwe->len = event_len;
+		memcpy(stream, (char *) iwe, IW_EV_POINT_LEN);
+		memcpy(stream + IW_EV_POINT_LEN, extra, iwe->u.data.length);
+		stream += event_len;
+	}
+	return stream;
+}
+
+/*------------------------------------------------------------------*/
+/*
+ * Wrapper to add a value to a Wireless Event in a stream of events.
+ * Be careful, this one is tricky to use properly :
+ * At the first run, you need to have (value = event + IW_EV_LCP_LEN).
+ */
+static inline char *
+iwe_stream_add_value(char *	event,		/* Event in the stream */
+		     char *	value,		/* Value in event */
+		     char *	ends,		/* End of stream */
+		     struct iw_event *iwe,	/* Payload */
+		     int	event_len)	/* Real size of payload */
+{
+	/* Don't duplicate LCP */
+	event_len -= IW_EV_LCP_LEN;
+
+	/* Check if it's possible */
+	if((value + event_len) < ends) {
+		/* Add new value */
+		memcpy(value, (char *) iwe + IW_EV_LCP_LEN, event_len);
+		value += event_len;
+		/* Patch LCP */
+		iwe->len = value - event;
+		memcpy(event, (char *) iwe, IW_EV_LCP_LEN);
+	}
+	return value;
+}
+
+#endif	/* _IW_HANDLER_H */
diff -Nru a/include/net/sock.h b/include/net/sock.h
--- a/include/net/sock.h	Fri Mar 15 17:51:01 2002
+++ b/include/net/sock.h	Fri Mar 15 17:51:01 2002
@@ -83,28 +83,22 @@
 } while(0);
 
 struct sock {
-	/* Socket demultiplex comparisons on incoming packets. */
-	__u32			daddr;		/* Foreign IPv4 addr			*/
-	__u32			rcv_saddr;	/* Bound local IPv4 addr		*/
-	__u16			dport;		/* Destination port			*/
-	unsigned short		num;		/* Local port				*/
-	int			bound_dev_if;	/* Bound device index if != 0		*/
-
+	/* Begin of struct sock/struct tcp_tw_bucket shared layout */
+	volatile unsigned char	state,		/* Connection state */
+				zapped;		/* ax25 & ipx means !linked */
+	unsigned char		reuse;		/* SO_REUSEADDR setting */
+	unsigned char		shutdown;
+	int			bound_dev_if;	/* Bound device index if != 0 */
 	/* Main hash linkage for various protocol lookup tables. */
 	struct sock		*next;
 	struct sock		**pprev;
 	struct sock		*bind_next;
 	struct sock		**bind_pprev;
-
-	volatile unsigned char	state,		/* Connection state			*/
-				zapped;		/* In ax25 & ipx means not linked	*/
-	__u16			sport;		/* Source port				*/
-
-	unsigned short		family;		/* Address family			*/
-	unsigned char		reuse;		/* SO_REUSEADDR setting			*/
-	unsigned char		shutdown;
 	atomic_t		refcnt;		/* Reference count			*/
-
+	unsigned short		family;		/* Address family */
+	/* End of struct sock/struct tcp_tw_bucket shared layout */
+	unsigned char		use_write_queue;
+	unsigned char		userlocks;
 	socket_lock_t		lock;		/* Synchronizer...			*/
 	int			rcvbuf;		/* Size of receive buffer in bytes	*/
 
@@ -118,7 +112,6 @@
 	atomic_t		omem_alloc;	/* "o" is "option" or "other" */
 	int			wmem_queued;	/* Persistent queue size */
 	int			forward_alloc;	/* Space allocated forward. */
-	__u32			saddr;		/* Sending source			*/
 	unsigned int		allocation;	/* Allocation mode			*/
 	int			sndbuf;		/* Size of send buffer in bytes		*/
 	struct sock		*prev;
@@ -137,9 +130,7 @@
 				bsdism;
 	unsigned char		debug;
 	unsigned char		rcvtstamp;
-	unsigned char		use_write_queue;
-	unsigned char		userlocks;
-	/* Hole of 3 bytes. Try to pack. */
+	/* Hole of 1 byte. Try to pack. */
 	int			route_caps;
 	int			proc;
 	unsigned long	        lingertime;
@@ -759,16 +750,13 @@
 
 #define SOCK_MIN_SNDBUF 2048
 #define SOCK_MIN_RCVBUF 256
-/* Must be less or equal SOCK_MIN_SNDBUF */
-#define SOCK_MIN_WRITE_SPACE	SOCK_MIN_SNDBUF
 
 /*
  *	Default write policy as shown to user space via poll/select/SIGIO
- *	Kernel internally doesn't use the MIN_WRITE_SPACE threshold.
  */
 static inline int sock_writeable(struct sock *sk) 
 {
-	return sock_wspace(sk) >= SOCK_MIN_WRITE_SPACE;
+	return atomic_read(&sk->wmem_alloc) < (sk->sndbuf / 2);
 }
 
 static inline int gfp_any(void)
diff -Nru a/include/net/tcp.h b/include/net/tcp.h
--- a/include/net/tcp.h	Fri Mar 15 17:51:01 2002
+++ b/include/net/tcp.h	Fri Mar 15 17:51:01 2002
@@ -53,7 +53,7 @@
  *	2) If all sockets have sk->reuse set, and none of them are in
  *	   TCP_LISTEN state, the port may be shared.
  *	   Failing that, goto test 3.
- *	3) If all sockets are bound to a specific sk->rcv_saddr local
+ *	3) If all sockets are bound to a specific inet_sk(sk)->rcv_saddr local
  *	   address, and none of them are the same, the port may be
  *	   shared.
  *	   Failing this, the port cannot be shared.
@@ -162,23 +162,26 @@
 	 * XXX Yes I know this is gross, but I'd have to edit every single
 	 * XXX networking file if I created a "struct sock_header". -DaveM
 	 */
-	__u32			daddr;
-	__u32			rcv_saddr;
-	__u16			dport;
-	unsigned short		num;
+	volatile unsigned char	state,		/* Connection state	      */
+				substate;	/* "zapped" -> "substate"     */
+	unsigned char		reuse;		/* SO_REUSEADDR setting       */
+	unsigned char		rcv_wscale;	/* also TW bucket specific    */
 	int			bound_dev_if;
+	/* Main hash linkage for various protocol lookup tables. */
 	struct sock		*next;
 	struct sock		**pprev;
 	struct sock		*bind_next;
 	struct sock		**bind_pprev;
-	unsigned char		state,
-				substate; /* "zapped" is replaced with "substate" */
-	__u16			sport;
-	unsigned short		family;
-	unsigned char		reuse,
-				rcv_wscale; /* It is also TW bucket specific */
 	atomic_t		refcnt;
-
+	unsigned short		family;
+	/* End of struct sock/struct tcp_tw_bucket shared layout */
+	__u16			sport;
+	/* Socket demultiplex comparisons on incoming packets. */
+	/* these five are in inet_opt */
+	__u32			daddr;
+	__u32			rcv_saddr;
+	__u16			dport;
+	__u16			num;
 	/* And these are ours. */
 	int			hashent;
 	int			timeout;
@@ -236,20 +239,20 @@
 	__u64 __name = (((__u64)(__daddr))<<32)|((__u64)(__saddr));
 #endif /* __BIG_ENDIAN */
 #define TCP_IPV4_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
-	(((*((__u64 *)&((__sk)->daddr)))== (__cookie))	&&		\
-	 ((*((__u32 *)&((__sk)->dport)))== (__ports))   &&		\
+	(((*((__u64 *)&(inet_sk(__sk)->daddr)))== (__cookie))	&&	\
+	 ((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports))   &&	\
 	 (!((__sk)->bound_dev_if) || ((__sk)->bound_dev_if == (__dif))))
 #else /* 32-bit arch */
 #define TCP_V4_ADDR_COOKIE(__name, __saddr, __daddr)
 #define TCP_IPV4_MATCH(__sk, __cookie, __saddr, __daddr, __ports, __dif)\
-	(((__sk)->daddr			== (__saddr))	&&		\
-	 ((__sk)->rcv_saddr		== (__daddr))	&&		\
-	 ((*((__u32 *)&((__sk)->dport)))== (__ports))   &&		\
+	((inet_sk(__sk)->daddr			== (__saddr))	&&	\
+	 (inet_sk(__sk)->rcv_saddr		== (__daddr))	&&	\
+	 ((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports))	&&	\
 	 (!((__sk)->bound_dev_if) || ((__sk)->bound_dev_if == (__dif))))
 #endif /* 64-bit arch */
 
 #define TCP_IPV6_MATCH(__sk, __saddr, __daddr, __ports, __dif)	   \
-	(((*((__u32 *)&((__sk)->dport)))== (__ports))   	&& \
+	(((*((__u32 *)&(inet_sk(__sk)->dport)))== (__ports))   	&& \
 	 ((__sk)->family		== AF_INET6)		&& \
 	 !ipv6_addr_cmp(&inet6_sk(__sk)->daddr, (__saddr))	&& \
 	 !ipv6_addr_cmp(&inet6_sk(__sk)->rcv_saddr, (__daddr))	&& \
@@ -263,7 +266,7 @@
 
 static __inline__ int tcp_sk_listen_hashfn(struct sock *sk)
 {
-	return tcp_lhashfn(sk->num);
+	return tcp_lhashfn(inet_sk(sk)->num);
 }
 
 #define MAX_TCP_HEADER	(128 + MAX_HEADER)
diff -Nru a/include/net/udp.h b/include/net/udp.h
--- a/include/net/udp.h	Fri Mar 15 17:51:03 2002
+++ b/include/net/udp.h	Fri Mar 15 17:51:03 2002
@@ -23,6 +23,7 @@
 #define _UDP_H
 
 #include <linux/udp.h>
+#include <linux/ip.h>
 #include <net/sock.h>
 
 #define UDP_HTABLE_SIZE		128
@@ -41,7 +42,7 @@
 	struct sock *sk = udp_hash[num & (UDP_HTABLE_SIZE - 1)];
 
 	for(; sk != NULL; sk = sk->next) {
-		if(sk->num == num)
+		if (inet_sk(sk)->num == num)
 			return 1;
 	}
 	return 0;
diff -Nru a/kernel/Makefile b/kernel/Makefile
--- a/kernel/Makefile	Fri Mar 15 17:51:02 2002
+++ b/kernel/Makefile	Fri Mar 15 17:51:02 2002
@@ -15,7 +15,7 @@
 obj-y     = sched.o dma.o fork.o exec_domain.o panic.o printk.o \
 	    module.o exit.o itimer.o info.o time.o softirq.o resource.o \
 	    sysctl.o acct.o capability.o ptrace.o timer.o user.o \
-	    signal.o sys.o kmod.o context.o 
+	    signal.o sys.o kmod.o context.o futex.o
 
 obj-$(CONFIG_UID16) += uid16.o
 obj-$(CONFIG_MODULES) += ksyms.o
diff -Nru a/kernel/acct.c b/kernel/acct.c
--- a/kernel/acct.c	Fri Mar 15 17:51:01 2002
+++ b/kernel/acct.c	Fri Mar 15 17:51:01 2002
@@ -72,19 +72,29 @@
 /*
  * External references and all of the globals.
  */
-
-static volatile int acct_active;
-static volatile int acct_needcheck;
-static struct file *acct_file;
-static struct timer_list acct_timer;
 static void do_acct_process(long, struct file *);
 
 /*
+ * This structure is used so that all the data protected by lock
+ * can be placed in the same cache line as the lock.  This primes
+ * the cache line to have the data after getting the lock.
+ */
+struct acct_glbs {
+	spinlock_t		lock;
+	volatile int		active;
+	volatile int		needcheck;
+	struct file		*file;
+	struct timer_list	timer;
+};
+
+static struct acct_glbs acct_globals __cacheline_aligned = {SPIN_LOCK_UNLOCKED};
+
+/*
  * Called whenever the timer says to check the free space.
  */
 static void acct_timeout(unsigned long unused)
 {
-	acct_needcheck = 1;
+	acct_globals.needcheck = 1;
 }
 
 /*
@@ -96,11 +106,11 @@
 	int res;
 	int act;
 
-	lock_kernel();
-	res = acct_active;
-	if (!file || !acct_needcheck)
+	spin_lock(&acct_globals.lock);
+	res = acct_globals.active;
+	if (!file || !acct_globals.needcheck)
 		goto out;
-	unlock_kernel();
+	spin_unlock(&acct_globals.lock);
 
 	/* May block */
 	if (vfs_statfs(file->f_dentry->d_inode->i_sb, &sbuf))
@@ -114,39 +124,76 @@
 		act = 0;
 
 	/*
-	 * If some joker switched acct_file under us we'ld better be
+	 * If some joker switched acct_globals.file under us we'ld better be
 	 * silent and _not_ touch anything.
 	 */
-	lock_kernel();
-	if (file != acct_file) {
+	spin_lock(&acct_globals.lock);
+	if (file != acct_globals.file) {
 		if (act)
 			res = act>0;
 		goto out;
 	}
 
-	if (acct_active) {
+	if (acct_globals.active) {
 		if (act < 0) {
-			acct_active = 0;
+			acct_globals.active = 0;
 			printk(KERN_INFO "Process accounting paused\n");
 		}
 	} else {
 		if (act > 0) {
-			acct_active = 1;
+			acct_globals.active = 1;
 			printk(KERN_INFO "Process accounting resumed\n");
 		}
 	}
 
-	del_timer(&acct_timer);
-	acct_needcheck = 0;
-	acct_timer.expires = jiffies + ACCT_TIMEOUT*HZ;
-	add_timer(&acct_timer);
-	res = acct_active;
+	del_timer(&acct_globals.timer);
+	acct_globals.needcheck = 0;
+	acct_globals.timer.expires = jiffies + ACCT_TIMEOUT*HZ;
+	add_timer(&acct_globals.timer);
+	res = acct_globals.active;
 out:
-	unlock_kernel();
+	spin_unlock(&acct_globals.lock);
 	return res;
 }
 
 /*
+ * Close the old accouting file (if currently open) and then replace
+ * it with file (if non-NULL).
+ *
+ * NOTE: acct_globals.lock MUST be held on entry and exit.
+ */
+void acct_file_reopen(struct file *file)
+{
+	struct file *old_acct = NULL;
+
+	BUG_ON(!spin_is_locked(&acct_globals.lock));
+
+	if (acct_globals.file) {
+		old_acct = acct_globals.file;
+		del_timer(&acct_globals.timer);
+		acct_globals.active = 0;
+		acct_globals.needcheck = 0;
+		acct_globals.file = NULL;
+	}
+	if (file) {
+		acct_globals.file = file;
+		acct_globals.needcheck = 0;
+		acct_globals.active = 1;
+		/* It's been deleted if it was used before so this is safe */
+		init_timer(&acct_globals.timer);
+		acct_globals.timer.function = acct_timeout;
+		acct_globals.timer.expires = jiffies + ACCT_TIMEOUT*HZ;
+		add_timer(&acct_globals.timer);
+	}
+	if (old_acct) {
+		spin_unlock(&acct_globals.lock);
+		do_acct_process(0, old_acct);
+		filp_close(old_acct, NULL);
+		spin_lock(&acct_globals.lock);
+	}
+}
+
+/*
  *  sys_acct() is the only system call needed to implement process
  *  accounting. It takes the name of the file where accounting records
  *  should be written. If the filename is NULL, accounting will be
@@ -154,71 +201,53 @@
  */
 asmlinkage long sys_acct(const char *name)
 {
-	struct file *file = NULL, *old_acct = NULL;
+	struct file *file = NULL;
 	char *tmp;
-	int error;
 
 	if (!capable(CAP_SYS_PACCT))
 		return -EPERM;
 
 	if (name) {
 		tmp = getname(name);
-		error = PTR_ERR(tmp);
-		if (IS_ERR(tmp))
-			goto out;
+		if (IS_ERR(tmp)) {
+			return (PTR_ERR(tmp));
+		}
 		/* Difference from BSD - they don't do O_APPEND */
 		file = filp_open(tmp, O_WRONLY|O_APPEND, 0);
 		putname(tmp);
 		if (IS_ERR(file)) {
-			error = PTR_ERR(file);
-			goto out;
+			return (PTR_ERR(file));
+		}
+		if (!S_ISREG(file->f_dentry->d_inode->i_mode)) {
+			filp_close(file, NULL);
+			return (-EACCES);
 		}
-		error = -EACCES;
-		if (!S_ISREG(file->f_dentry->d_inode->i_mode)) 
-			goto out_err;
-
-		error = -EIO;
-		if (!file->f_op->write) 
-			goto out_err;
-	}
 
-	error = 0;
-	lock_kernel();
-	if (acct_file) {
-		old_acct = acct_file;
-		del_timer(&acct_timer);
-		acct_active = 0;
-		acct_needcheck = 0;
-		acct_file = NULL;
-	}
-	if (name) {
-		acct_file = file;
-		acct_needcheck = 0;
-		acct_active = 1;
-		/* It's been deleted if it was used before so this is safe */
-		init_timer(&acct_timer);
-		acct_timer.function = acct_timeout;
-		acct_timer.expires = jiffies + ACCT_TIMEOUT*HZ;
-		add_timer(&acct_timer);
-	}
-	unlock_kernel();
-	if (old_acct) {
-		do_acct_process(0,old_acct);
-		filp_close(old_acct, NULL);
+		if (!file->f_op->write) {
+			filp_close(file, NULL);
+			return (-EIO);
+		}
 	}
-out:
-	return error;
-out_err:
-	filp_close(file, NULL);
-	goto out;
+
+	spin_lock(&acct_globals.lock);
+	acct_file_reopen(file);
+	spin_unlock(&acct_globals.lock);
+
+	return (0);
 }
 
+/*
+ * If the accouting is turned on for a file in the filesystem pointed
+ * to by sb, turn accouting off.
+ */
 void acct_auto_close(struct super_block *sb)
 {
-	lock_kernel();
-	if (acct_file && acct_file->f_dentry->d_inode->i_sb == sb)
-		sys_acct(NULL);
-	unlock_kernel();
+	spin_lock(&acct_globals.lock);
+	if (acct_globals.file &&
+	    acct_globals.file->f_dentry->d_inode->i_sb == sb) {
+		acct_file_reopen((struct file *)NULL);
+	}
+	spin_unlock(&acct_globals.lock);
 }
 
 /*
@@ -277,6 +306,7 @@
 	struct acct ac;
 	mm_segment_t fs;
 	unsigned long vsize;
+	unsigned long flim;
 
 	/*
 	 * First check to see if there is enough free_space to continue
@@ -294,7 +324,8 @@
 	strncpy(ac.ac_comm, current->comm, ACCT_COMM);
 	ac.ac_comm[ACCT_COMM - 1] = '\0';
 
-	ac.ac_btime = CT_TO_SECS(current->start_time) + (xtime.tv_sec - (jiffies / HZ));
+	ac.ac_btime = CT_TO_SECS(current->start_time) +
+		(xtime.tv_sec - (jiffies / HZ));
 	ac.ac_etime = encode_comp_t(jiffies - current->start_time);
 	ac.ac_utime = encode_comp_t(current->times.tms_utime);
 	ac.ac_stime = encode_comp_t(current->times.tms_stime);
@@ -338,8 +369,14 @@
          */
 	fs = get_fs();
 	set_fs(KERNEL_DS);
+	/*
+ 	 * Accounting records are not subject to resource limits.
+ 	 */
+	flim = current->rlim[RLIMIT_FSIZE].rlim_cur;
+	current->rlim[RLIMIT_FSIZE].rlim_cur = RLIM_INFINITY;
 	file->f_op->write(file, (char *)&ac,
 			       sizeof(struct acct), &file->f_pos);
+	current->rlim[RLIMIT_FSIZE].rlim_cur = flim;
 	set_fs(fs);
 }
 
@@ -349,15 +386,15 @@
 int acct_process(long exitcode)
 {
 	struct file *file = NULL;
-	lock_kernel();
-	if (acct_file) {
-		file = acct_file;
+	spin_lock(&acct_globals.lock);
+	if (acct_globals.file) {
+		file = acct_globals.file;
 		get_file(file);
-		unlock_kernel();
-		do_acct_process(exitcode, acct_file);
+		spin_unlock(&acct_globals.lock);
+		do_acct_process(exitcode, file);
 		fput(file);
 	} else
-		unlock_kernel();
+		spin_unlock(&acct_globals.lock);
 	return 0;
 }
 
diff -Nru a/kernel/exit.c b/kernel/exit.c
--- a/kernel/exit.c	Fri Mar 15 17:51:02 2002
+++ b/kernel/exit.c	Fri Mar 15 17:51:02 2002
@@ -91,10 +91,10 @@
 	for_each_task(p) {
 		if ((p == ignored_task) || (p->pgrp != pgrp) ||
 		    (p->state == TASK_ZOMBIE) ||
-		    (p->p_pptr->pid == 1))
+		    (p->parent->pid == 1))
 			continue;
-		if ((p->p_pptr->pgrp != pgrp) &&
-		    (p->p_pptr->session == p->session)) {
+		if ((p->parent->pgrp != pgrp) &&
+		    (p->parent->session == p->session)) {
 			read_unlock(&tasklist_lock);
  			return 0;
 		}
@@ -144,8 +144,8 @@
 
 	/* Reparent to init */
 	REMOVE_LINKS(current);
-	current->p_pptr = child_reaper;
-	current->p_opptr = child_reaper;
+	current->parent = child_reaper;
+	current->real_parent = child_reaper;
 	SET_LINKS(current);
 
 	/* Set the exit signal to SIGCHLD so we signal init on exit */
@@ -217,16 +217,16 @@
 		reaper = child_reaper;
 
 	for_each_task(p) {
-		if (p->p_opptr == father) {
+		if (p->real_parent == father) {
 			/* We dont want people slaying init */
 			p->exit_signal = SIGCHLD;
 			p->self_exec_id++;
 
 			/* Make sure we're not reparenting to ourselves */
 			if (p == reaper)
-				p->p_opptr = child_reaper;
+				p->real_parent = child_reaper;
 			else
-				p->p_opptr = reaper;
+				p->real_parent = reaper;
 
 			if (p->pdeath_signal) send_sig(p->pdeath_signal, p, 0);
 		}
@@ -400,7 +400,7 @@
 	 * is about to become orphaned.
 	 */
 	 
-	t = current->p_pptr;
+	t = current->parent;
 	
 	if ((t->pgrp != current->pgrp) &&
 	    (t->session == current->session) &&
@@ -445,17 +445,12 @@
 	write_lock_irq(&tasklist_lock);
 	current->state = TASK_ZOMBIE;
 	do_notify_parent(current, current->exit_signal);
-	while (current->p_cptr != NULL) {
-		p = current->p_cptr;
-		current->p_cptr = p->p_osptr;
-		p->p_ysptr = NULL;
+	while ((p = eldest_child(current))) {
+		list_del_init(&p->sibling);
 		p->ptrace = 0;
 
-		p->p_pptr = p->p_opptr;
-		p->p_osptr = p->p_pptr->p_cptr;
-		if (p->p_osptr)
-			p->p_osptr->p_ysptr = p;
-		p->p_pptr->p_cptr = p;
+		p->parent = p->real_parent;
+		list_add_tail(&p->sibling,&p->parent->children);
 		if (p->state == TASK_ZOMBIE)
 			do_notify_parent(p, p->exit_signal);
 		/*
@@ -568,7 +563,9 @@
 	tsk = current;
 	do {
 		struct task_struct *p;
-	 	for (p = tsk->p_cptr ; p ; p = p->p_osptr) {
+		struct list_head *_p;
+		list_for_each(_p,&tsk->children) {
+			p = list_entry(_p,struct task_struct,sibling);
 			if (pid>0) {
 				if (p->pid != pid)
 					continue;
@@ -595,6 +592,12 @@
 				if (!(options & WUNTRACED) && !(p->ptrace & PT_PTRACED))
 					continue;
 				read_unlock(&tasklist_lock);
+
+				/* move to end of parent's list to avoid starvation */
+				write_lock_irq(&tasklist_lock);
+				remove_parent(p);
+				add_parent(p, p->parent);
+				write_unlock_irq(&tasklist_lock);
 				retval = ru ? getrusage(p, RUSAGE_BOTH, ru) : 0; 
 				if (!retval && stat_addr) 
 					retval = put_user((p->exit_code << 8) | 0x7f, stat_addr);
@@ -613,11 +616,11 @@
 				if (retval)
 					goto end_wait4; 
 				retval = p->pid;
-				if (p->p_opptr != p->p_pptr) {
+				if (p->real_parent != p->parent) {
 					write_lock_irq(&tasklist_lock);
-					REMOVE_LINKS(p);
-					p->p_pptr = p->p_opptr;
-					SET_LINKS(p);
+					remove_parent(p);
+					p->parent = p->real_parent;
+					add_parent(p, p->parent);
 					do_notify_parent(p, SIGCHLD);
 					write_unlock_irq(&tasklist_lock);
 				} else
diff -Nru a/kernel/fork.c b/kernel/fork.c
--- a/kernel/fork.c	Fri Mar 15 17:51:01 2002
+++ b/kernel/fork.c	Fri Mar 15 17:51:01 2002
@@ -666,7 +666,8 @@
 
 	INIT_LIST_HEAD(&p->run_list);
 
-	p->p_cptr = NULL;
+	INIT_LIST_HEAD(&p->children);
+	INIT_LIST_HEAD(&p->sibling);
 	init_waitqueue_head(&p->wait_chldexit);
 	p->vfork_done = NULL;
 	if (clone_flags & CLONE_VFORK) {
@@ -766,12 +767,12 @@
 	write_lock_irq(&tasklist_lock);
 
 	/* CLONE_PARENT re-uses the old parent */
-	p->p_opptr = current->p_opptr;
-	p->p_pptr = current->p_pptr;
+	p->real_parent = current->real_parent;
+	p->parent = current->parent;
 	if (!(clone_flags & CLONE_PARENT)) {
-		p->p_opptr = current;
+		p->real_parent = current;
 		if (!(p->ptrace & PT_PTRACED))
-			p->p_pptr = current;
+			p->parent = current;
 	}
 
 	if (clone_flags & CLONE_THREAD) {
diff -Nru a/kernel/futex.c b/kernel/futex.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/kernel/futex.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,232 @@
+/*
+ *  Fast Userspace Mutexes (which I call "Futexes!").
+ *  (C) Rusty Russell, IBM 2002
+ *
+ *  Thanks to Ben LaHaise for yelling "hashed waitqueues" loudly
+ *  enough at me, Linus for the original (flawed) idea, Matthew
+ *  Kirkwood for proof-of-concept implementation.
+ *
+ *  "The futexes are also cursed."
+ *  "But they come in a choice of three flavours!"
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/hash.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/futex.h>
+#include <linux/highmem.h>
+#include <asm/atomic.h>
+
+/* These mutexes are a very simple counter: the winner is the one who
+   decrements from 1 to 0.  The counter starts at 1 when the lock is
+   free.  A value other than 0 or 1 means someone may be sleeping.
+   This is simple enough to work on all architectures, but has the
+   problem that if we never "up" the semaphore it could eventually
+   wrap around. */
+
+/* FIXME: This may be way too small. --RR */
+#define FUTEX_HASHBITS 6
+
+/* We use this instead of a normal wait_queue_t, so we can wake only
+   the relevent ones (hashed queues may be shared) */
+struct futex_q {
+	struct list_head list;
+	struct task_struct *task;
+	/* Page struct and offset within it. */
+	struct page *page;
+	unsigned int offset;
+};
+
+/* The key for the hash is the address + index + offset within page */
+static struct list_head futex_queues[1<<FUTEX_HASHBITS];
+static spinlock_t futex_lock = SPIN_LOCK_UNLOCKED;
+
+static inline struct list_head *hash_futex(struct page *page,
+					   unsigned long offset)
+{
+	unsigned long h;
+
+	/* struct page is shared, so we can hash on its address */
+	h = (unsigned long)page + offset;
+	return &futex_queues[hash_long(h, FUTEX_HASHBITS)];
+}
+
+static inline void wake_one_waiter(struct list_head *head,
+				   struct page *page,
+				   unsigned int offset)
+{
+	struct list_head *i;
+
+	spin_lock(&futex_lock);
+	list_for_each(i, head) {
+		struct futex_q *this = list_entry(i, struct futex_q, list);
+
+		if (this->page == page && this->offset == offset) {
+			wake_up_process(this->task);
+			break;
+		}
+	}
+	spin_unlock(&futex_lock);
+}
+
+/* Add at end to avoid starvation */
+static inline void queue_me(struct list_head *head,
+			    struct futex_q *q,
+			    struct page *page,
+			    unsigned int offset)
+{
+	q->task = current;
+	q->page = page;
+	q->offset = offset;
+
+	spin_lock(&futex_lock);
+	list_add_tail(&q->list, head);
+	spin_unlock(&futex_lock);
+}
+
+static inline void unqueue_me(struct futex_q *q)
+{
+	spin_lock(&futex_lock);
+	list_del(&q->list);
+	spin_unlock(&futex_lock);
+}
+
+/* Get kernel address of the user page and pin it. */
+static struct page *pin_page(unsigned long page_start)
+{
+	struct mm_struct *mm = current->mm;
+	struct page *page;
+	int err;
+
+	down_read(&mm->mmap_sem);
+	err = get_user_pages(current, current->mm, page_start,
+			     1 /* one page */,
+			     1 /* writable */,
+			     0 /* don't force */,
+			     &page,
+			     NULL /* don't return vmas */);
+	up_read(&mm->mmap_sem);
+
+	if (err < 0)
+		return ERR_PTR(err);
+	return page;
+}
+
+/* Try to decrement the user count to zero. */
+static int decrement_to_zero(struct page *page, unsigned int offset)
+{
+	atomic_t *count;
+	int ret = 0;
+
+	count = kmap(page) + offset;
+	/* If we take the semaphore from 1 to 0, it's ours.  If it's
+           zero, decrement anyway, to indicate we are waiting.  If
+           it's negative, don't decrement so we don't wrap... */
+	if (atomic_read(count) >= 0 && atomic_dec_and_test(count))
+		ret = 1;
+	kunmap(page);
+	return ret;
+}
+
+/* Simplified from arch/ppc/kernel/semaphore.c: Paul M. is a genius. */
+static int futex_down(struct list_head *head, struct page *page, int offset)
+{
+	int retval = 0;
+	struct futex_q q;
+
+	current->state = TASK_INTERRUPTIBLE;
+	queue_me(head, &q, page, offset);
+
+	while (!decrement_to_zero(page, offset)) {
+		if (signal_pending(current)) {
+			retval = -EINTR;
+			break;
+		}
+		schedule();
+		current->state = TASK_INTERRUPTIBLE;
+	}
+	current->state = TASK_RUNNING;
+	unqueue_me(&q);
+	/* If we were signalled, we might have just been woken: we
+	   must wake another one.  Otherwise we need to wake someone
+	   else (if they are waiting) so they drop the count below 0,
+	   and when we "up" in userspace, we know there is a
+	   waiter. */
+	wake_one_waiter(head, page, offset);
+	return retval;
+}
+
+static int futex_up(struct list_head *head, struct page *page, int offset)
+{
+	atomic_t *count;
+
+	count = kmap(page) + offset;
+	atomic_set(count, 1);
+	smp_wmb();
+	kunmap(page);
+	wake_one_waiter(head, page, offset);
+	return 0;
+}
+
+asmlinkage int sys_futex(void *uaddr, int op)
+{
+	int ret;
+	unsigned long pos_in_page;
+	struct list_head *head;
+	struct page *page;
+
+	pos_in_page = ((unsigned long)uaddr) % PAGE_SIZE;
+
+	/* Must be "naturally" aligned, and not on page boundary. */
+	if ((pos_in_page % __alignof__(atomic_t)) != 0
+	    || pos_in_page + sizeof(atomic_t) > PAGE_SIZE)
+		return -EINVAL;
+
+	/* Simpler if it doesn't vanish underneath us. */
+	page = pin_page((unsigned long)uaddr - pos_in_page);
+	if (IS_ERR(page))
+		return PTR_ERR(page);
+
+	head = hash_futex(page, pos_in_page);
+	switch (op) {
+	case FUTEX_UP:
+		ret = futex_up(head, page, pos_in_page);
+		break;
+	case FUTEX_DOWN:
+		ret = futex_down(head, page, pos_in_page);
+		break;
+	/* Add other lock types here... */
+	default:
+		ret = -EINVAL;
+	}
+	put_page(page);
+
+	return ret;
+}
+
+static int __init init(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(futex_queues); i++)
+		INIT_LIST_HEAD(&futex_queues[i]);
+	return 0;
+}
+__initcall(init);
diff -Nru a/kernel/ksyms.c b/kernel/ksyms.c
--- a/kernel/ksyms.c	Fri Mar 15 17:51:01 2002
+++ b/kernel/ksyms.c	Fri Mar 15 17:51:01 2002
@@ -283,11 +283,21 @@
 EXPORT_SYMBOL(lock_may_read);
 EXPORT_SYMBOL(lock_may_write);
 EXPORT_SYMBOL(dcache_readdir);
+EXPORT_SYMBOL(simple_statfs);
+EXPORT_SYMBOL(simple_lookup);
+EXPORT_SYMBOL(simple_dir_operations);
+EXPORT_SYMBOL(simple_dir_inode_operations);
 EXPORT_SYMBOL(fd_install);
 EXPORT_SYMBOL(put_unused_fd);
 EXPORT_SYMBOL(get_sb_bdev);
+EXPORT_SYMBOL(kill_block_super);
 EXPORT_SYMBOL(get_sb_nodev);
 EXPORT_SYMBOL(get_sb_single);
+EXPORT_SYMBOL(kill_anon_super);
+EXPORT_SYMBOL(kill_litter_super);
+EXPORT_SYMBOL(deactivate_super);
+EXPORT_SYMBOL(sget);
+EXPORT_SYMBOL(set_anon_super);
 
 /* for stackable file systems (lofs, wrapfs, cryptfs, etc.) */
 EXPORT_SYMBOL(default_llseek);
diff -Nru a/kernel/printk.c b/kernel/printk.c
--- a/kernel/printk.c	Fri Mar 15 17:51:03 2002
+++ b/kernel/printk.c	Fri Mar 15 17:51:03 2002
@@ -29,7 +29,7 @@
 
 #include <asm/uaccess.h>
 
-#ifdef CONFIG_MULTIQUAD
+#if defined(CONFIG_MULTIQUAD) || defined(CONFIG_IA64)
 #define LOG_BUF_LEN	(65536)
 #elif defined(CONFIG_SMP)
 #define LOG_BUF_LEN	(32768)
diff -Nru a/kernel/ptrace.c b/kernel/ptrace.c
--- a/kernel/ptrace.c	Fri Mar 15 17:51:03 2002
+++ b/kernel/ptrace.c	Fri Mar 15 17:51:03 2002
@@ -24,7 +24,7 @@
 	if (!(child->ptrace & PT_PTRACED))
 		return -ESRCH;
 
-	if (child->p_pptr != current)
+	if (child->parent != current)
 		return -ESRCH;
 
 	if (!kill) {
@@ -70,9 +70,9 @@
 	task_unlock(task);
 
 	write_lock_irq(&tasklist_lock);
-	if (task->p_pptr != current) {
+	if (task->parent != current) {
 		REMOVE_LINKS(task);
-		task->p_pptr = current;
+		task->parent = current;
 		SET_LINKS(task);
 	}
 	write_unlock_irq(&tasklist_lock);
@@ -98,7 +98,7 @@
 	child->exit_code = data;
 	write_lock_irq(&tasklist_lock);
 	REMOVE_LINKS(child);
-	child->p_pptr = child->p_opptr;
+	child->parent = child->real_parent;
 	SET_LINKS(child);
 	write_unlock_irq(&tasklist_lock);
 
diff -Nru a/kernel/sched.c b/kernel/sched.c
--- a/kernel/sched.c	Fri Mar 15 17:51:02 2002
+++ b/kernel/sched.c	Fri Mar 15 17:51:02 2002
@@ -140,6 +140,7 @@
  */
 struct runqueue {
 	spinlock_t lock;
+	spinlock_t frozen;
 	unsigned long nr_running, nr_switches, expired_timestamp;
 	task_t *curr, *idle;
 	prio_array_t *active, *expired, arrays[2];
@@ -400,7 +401,7 @@
 #if CONFIG_SMP || CONFIG_PREEMPT
 asmlinkage void schedule_tail(void)
 {
-	spin_unlock_irq(&this_rq()->lock);
+	spin_unlock_irq(&this_rq()->frozen);
 }
 #endif
 
@@ -518,12 +519,14 @@
 	busiest = NULL;
 	max_load = 1;
 	for (i = 0; i < smp_num_cpus; i++) {
-		rq_src = cpu_rq(cpu_logical_map(i));
-		if (idle || (rq_src->nr_running < this_rq->prev_nr_running[i]))
+		int logical = cpu_logical_map(i);
+
+		rq_src = cpu_rq(logical);
+		if (idle || (rq_src->nr_running < this_rq->prev_nr_running[logical]))
 			load = rq_src->nr_running;
 		else
-			load = this_rq->prev_nr_running[i];
-		this_rq->prev_nr_running[i] = rq_src->nr_running;
+			load = this_rq->prev_nr_running[logical];
+		this_rq->prev_nr_running[logical] = rq_src->nr_running;
 
 		if ((load > max_load) && (rq_src != this_rq)) {
 			busiest = rq_src;
@@ -590,7 +593,7 @@
 #define CAN_MIGRATE_TASK(p,rq,this_cpu)					\
 	((jiffies - (p)->sleep_timestamp > cache_decay_ticks) &&	\
 		((p) != (rq)->curr) &&					\
-			(tmp->cpus_allowed & (1 << (this_cpu))))
+			((p)->cpus_allowed & (1 << (this_cpu))))
 
 	if (!CAN_MIGRATE_TASK(tmp, busiest, this_cpu)) {
 		curr = curr->next;
@@ -808,16 +811,22 @@
 	if (likely(prev != next)) {
 		rq->nr_switches++;
 		rq->curr = next;
+		spin_lock(&rq->frozen);
+		spin_unlock(&rq->lock);
+
 		context_switch(prev, next);
+
 		/*
 		 * The runqueue pointer might be from another CPU
 		 * if the new task was last running on a different
 		 * CPU - thus re-load it.
 		 */
-		barrier();
+		mb();
 		rq = this_rq();
+		spin_unlock_irq(&rq->frozen);
+	} else {
+		spin_unlock_irq(&rq->lock);
 	}
-	spin_unlock_irq(&rq->lock);
 
 	reacquire_kernel_lock(current);
 	preempt_enable_no_resched();
@@ -1311,6 +1320,7 @@
 static void show_task(task_t * p)
 {
 	unsigned long free = 0;
+	task_t *relative;
 	int state;
 	static const char * stat_nam[] = { "R", "S", "D", "Z", "T", "W" };
 
@@ -1337,17 +1347,17 @@
 			n++;
 		free = (unsigned long) n - (unsigned long)(p+1);
 	}
-	printk("%5lu %5d %6d ", free, p->pid, p->p_pptr->pid);
-	if (p->p_cptr)
-		printk("%5d ", p->p_cptr->pid);
+	printk("%5lu %5d %6d ", free, p->pid, p->parent->pid);
+	if ((relative = eldest_child(p)))
+		printk("%5d ", relative->pid);
 	else
 		printk("      ");
-	if (p->p_ysptr)
-		printk("%7d", p->p_ysptr->pid);
+	if ((relative = younger_sibling(p)))
+		printk("%7d", relative->pid);
 	else
 		printk("       ");
-	if (p->p_osptr)
-		printk(" %5d", p->p_osptr->pid);
+	if ((relative = older_sibling(p)))
+		printk(" %5d", relative->pid);
 	else
 		printk("      ");
 	if (!p->mm)
@@ -1463,6 +1473,7 @@
 		rq->active = rq->arrays;
 		rq->expired = rq->arrays + 1;
 		spin_lock_init(&rq->lock);
+		spin_lock_init(&rq->frozen);
 		INIT_LIST_HEAD(&rq->migration_queue);
 
 		for (j = 0; j < 2; j++) {
@@ -1649,19 +1660,31 @@
 
 void __init migration_init(void)
 {
+	unsigned long tmp, orig_cache_decay_ticks;
 	int cpu;
 
-	for (cpu = 0; cpu < smp_num_cpus; cpu++)
+	tmp = 0;
+	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
 		if (kernel_thread(migration_thread, NULL,
 				CLONE_FS | CLONE_FILES | CLONE_SIGNAL) < 0)
 			BUG();
+		tmp |= (1UL << cpu_logical_map(cpu));
+	}
+
+	migration_mask = tmp;
+
+	orig_cache_decay_ticks = cache_decay_ticks;
+	cache_decay_ticks = 0;
 
-	migration_mask = (1 << smp_num_cpus) - 1;
+	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
+		int logical = cpu_logical_map(cpu);
 
-	for (cpu = 0; cpu < smp_num_cpus; cpu++)
-		while (!cpu_rq(cpu)->migration_thread)
+		while (!cpu_rq(logical)->migration_thread)
 			schedule_timeout(2);
+	}
 	if (migration_mask)
 		BUG();
+
+	cache_decay_ticks = orig_cache_decay_ticks;
 }
 #endif
diff -Nru a/kernel/signal.c b/kernel/signal.c
--- a/kernel/signal.c	Fri Mar 15 17:51:02 2002
+++ b/kernel/signal.c	Fri Mar 15 17:51:02 2002
@@ -804,8 +804,8 @@
 	info.si_code = why;
 	info.si_status = status;
 
-	send_sig_info(sig, &info, tsk->p_pptr);
-	wake_up_parent(tsk->p_pptr);
+	send_sig_info(sig, &info, tsk->parent);
+	wake_up_parent(tsk->parent);
 }
 
 
diff -Nru a/kernel/sys.c b/kernel/sys.c
--- a/kernel/sys.c	Fri Mar 15 17:51:01 2002
+++ b/kernel/sys.c	Fri Mar 15 17:51:01 2002
@@ -839,7 +839,7 @@
 	if (!p)
 		goto out;
 
-	if (p->p_pptr == current || p->p_opptr == current) {
+	if (p->parent == current || p->real_parent == current) {
 		err = -EPERM;
 		if (p->session != current->session)
 			goto out;
diff -Nru a/kernel/timer.c b/kernel/timer.c
--- a/kernel/timer.c	Fri Mar 15 17:51:02 2002
+++ b/kernel/timer.c	Fri Mar 15 17:51:02 2002
@@ -742,14 +742,14 @@
 	struct task_struct * me = current;
 	struct task_struct * parent;
 
-	parent = me->p_opptr;
+	parent = me->real_parent;
 	for (;;) {
 		pid = parent->pid;
 #if CONFIG_SMP
 {
 		struct task_struct *old = parent;
 		mb();
-		parent = me->p_opptr;
+		parent = me->real_parent;
 		if (old != parent)
 			continue;
 }
diff -Nru a/mm/Makefile b/mm/Makefile
--- a/mm/Makefile	Fri Mar 15 17:51:03 2002
+++ b/mm/Makefile	Fri Mar 15 17:51:03 2002
@@ -14,6 +14,6 @@
 obj-y	 := memory.o mmap.o filemap.o mprotect.o mlock.o mremap.o \
 	    vmalloc.o slab.o bootmem.o swap.o vmscan.o page_io.o \
 	    page_alloc.o swap_state.o swapfile.o numa.o oom_kill.o \
-	    shmem.o highmem.o mempool.o
+	    shmem.o highmem.o mempool.o msync.o mincore.o
 
 include $(TOPDIR)/Rules.make
diff -Nru a/mm/filemap.c b/mm/filemap.c
--- a/mm/filemap.c	Fri Mar 15 17:51:02 2002
+++ b/mm/filemap.c	Fri Mar 15 17:51:02 2002
@@ -25,6 +25,7 @@
 #include <linux/iobuf.h>
 #include <linux/compiler.h>
 #include <linux/fs.h>
+#include <linux/hash.h>
 
 #include <asm/pgalloc.h>
 #include <asm/uaccess.h>
@@ -550,7 +551,7 @@
 	spin_lock(&pagecache_lock);
 
         while (!list_empty(&mapping->dirty_pages)) {
-		struct page *page = list_entry(mapping->dirty_pages.next, struct page, list);
+		struct page *page = list_entry(mapping->dirty_pages.prev, struct page, list);
 
 		list_del(&page->list);
 		list_add(&page->list, &mapping->locked_pages);
@@ -773,32 +774,8 @@
 static inline wait_queue_head_t *page_waitqueue(struct page *page)
 {
 	const zone_t *zone = page_zone(page);
-	wait_queue_head_t *wait = zone->wait_table;
-	unsigned long hash = (unsigned long)page;
 
-#if BITS_PER_LONG == 64
-	/*  Sigh, gcc can't optimise this alone like it does for 32 bits. */
-	unsigned long n = hash;
-	n <<= 18;
-	hash -= n;
-	n <<= 33;
-	hash -= n;
-	n <<= 3;
-	hash += n;
-	n <<= 3;
-	hash -= n;
-	n <<= 4;
-	hash += n;
-	n <<= 2;
-	hash += n;
-#else
-	/* On some cpus multiply is faster, on others gcc will do shifts */
-	hash *= GOLDEN_RATIO_PRIME;
-#endif
-
-	hash >>= zone->wait_table_shift;
-
-	return &wait[hash];
+	return &zone->wait_table[hash_ptr(page, zone->wait_table_bits)];
 }
 
 /* 
@@ -2082,107 +2059,6 @@
 	return NULL;
 }
 
-/* Called with mm->page_table_lock held to protect against other
- * threads/the swapper from ripping pte's out from under us.
- */
-static inline int filemap_sync_pte(pte_t *ptep, pmd_t *pmdp, struct vm_area_struct *vma,
-	unsigned long address, unsigned int flags)
-{
-	pte_t pte = *ptep;
-
-	if (pte_present(pte)) {
-		struct page *page = pte_page(pte);
-		if (VALID_PAGE(page) && !PageReserved(page) && ptep_test_and_clear_dirty(ptep)) {
-			flush_tlb_page(vma, address);
-			set_page_dirty(page);
-		}
-	}
-	return 0;
-}
-
-static inline int filemap_sync_pte_range(pmd_t * pmd,
-	unsigned long address, unsigned long end, 
-	struct vm_area_struct *vma, unsigned int flags)
-{
-	pte_t *pte;
-	int error;
-
-	if (pmd_none(*pmd))
-		return 0;
-	if (pmd_bad(*pmd)) {
-		pmd_ERROR(*pmd);
-		pmd_clear(pmd);
-		return 0;
-	}
-	pte = pte_offset_map(pmd, address);
-	if ((address & PMD_MASK) != (end & PMD_MASK))
-		end = (address & PMD_MASK) + PMD_SIZE;
-	error = 0;
-	do {
-		error |= filemap_sync_pte(pte, pmd, vma, address, flags);
-		address += PAGE_SIZE;
-		pte++;
-	} while (address && (address < end));
-
-	pte_unmap(pte - 1);
-
-	return error;
-}
-
-static inline int filemap_sync_pmd_range(pgd_t * pgd,
-	unsigned long address, unsigned long end, 
-	struct vm_area_struct *vma, unsigned int flags)
-{
-	pmd_t * pmd;
-	int error;
-
-	if (pgd_none(*pgd))
-		return 0;
-	if (pgd_bad(*pgd)) {
-		pgd_ERROR(*pgd);
-		pgd_clear(pgd);
-		return 0;
-	}
-	pmd = pmd_offset(pgd, address);
-	if ((address & PGDIR_MASK) != (end & PGDIR_MASK))
-		end = (address & PGDIR_MASK) + PGDIR_SIZE;
-	error = 0;
-	do {
-		error |= filemap_sync_pte_range(pmd, address, end, vma, flags);
-		address = (address + PMD_SIZE) & PMD_MASK;
-		pmd++;
-	} while (address && (address < end));
-	return error;
-}
-
-int filemap_sync(struct vm_area_struct * vma, unsigned long address,
-	size_t size, unsigned int flags)
-{
-	pgd_t * dir;
-	unsigned long end = address + size;
-	int error = 0;
-
-	/* Aquire the lock early; it may be possible to avoid dropping
-	 * and reaquiring it repeatedly.
-	 */
-	spin_lock(&vma->vm_mm->page_table_lock);
-
-	dir = pgd_offset(vma->vm_mm, address);
-	flush_cache_range(vma, address, end);
-	if (address >= end)
-		BUG();
-	do {
-		error |= filemap_sync_pmd_range(dir, address, end, vma, flags);
-		address = (address + PGDIR_SIZE) & PGDIR_MASK;
-		dir++;
-	} while (address && (address < end));
-	flush_tlb_range(vma, end - size, end);
-
-	spin_unlock(&vma->vm_mm->page_table_lock);
-
-	return error;
-}
-
 static struct vm_operations_struct generic_file_vm_ops = {
 	nopage:		filemap_nopage,
 };
@@ -2205,107 +2081,6 @@
 	return 0;
 }
 
-/*
- * The msync() system call.
- */
-
-/*
- * MS_SYNC syncs the entire file - including mappings.
- *
- * MS_ASYNC initiates writeout of just the dirty mapped data.
- * This provides no guarantee of file integrity - things like indirect
- * blocks may not have started writeout.  MS_ASYNC is primarily useful
- * where the application knows that it has finished with the data and
- * wishes to intelligently schedule its own I/O traffic.
- */
-static int msync_interval(struct vm_area_struct * vma,
-	unsigned long start, unsigned long end, int flags)
-{
-	int ret = 0;
-	struct file * file = vma->vm_file;
-
-	if (file && (vma->vm_flags & VM_SHARED)) {
-		ret = filemap_sync(vma, start, end-start, flags);
-
-		if (!ret && (flags & (MS_SYNC|MS_ASYNC))) {
-			struct inode * inode = file->f_dentry->d_inode;
-
-			down(&inode->i_sem);
-			ret = filemap_fdatasync(inode->i_mapping);
-			if (flags & MS_SYNC) {
-				int err;
-
-				if (file->f_op && file->f_op->fsync) {
-					err = file->f_op->fsync(file, file->f_dentry, 1);
-					if (err && !ret)
-						ret = err;
-				}
-				err = filemap_fdatawait(inode->i_mapping);
-				if (err && !ret)
-					ret = err;
-			}
-			up(&inode->i_sem);
-		}
-	}
-	return ret;
-}
-
-asmlinkage long sys_msync(unsigned long start, size_t len, int flags)
-{
-	unsigned long end;
-	struct vm_area_struct * vma;
-	int unmapped_error, error = -EINVAL;
-
-	down_read(&current->mm->mmap_sem);
-	if (start & ~PAGE_MASK)
-		goto out;
-	len = (len + ~PAGE_MASK) & PAGE_MASK;
-	end = start + len;
-	if (end < start)
-		goto out;
-	if (flags & ~(MS_ASYNC | MS_INVALIDATE | MS_SYNC))
-		goto out;
-	error = 0;
-	if (end == start)
-		goto out;
-	/*
-	 * If the interval [start,end) covers some unmapped address ranges,
-	 * just ignore them, but return -EFAULT at the end.
-	 */
-	vma = find_vma(current->mm, start);
-	unmapped_error = 0;
-	for (;;) {
-		/* Still start < end. */
-		error = -EFAULT;
-		if (!vma)
-			goto out;
-		/* Here start < vma->vm_end. */
-		if (start < vma->vm_start) {
-			unmapped_error = -EFAULT;
-			start = vma->vm_start;
-		}
-		/* Here vma->vm_start <= start < vma->vm_end. */
-		if (end <= vma->vm_end) {
-			if (start < end) {
-				error = msync_interval(vma, start, end, flags);
-				if (error)
-					goto out;
-			}
-			error = unmapped_error;
-			goto out;
-		}
-		/* Here vma->vm_start <= start < vma->vm_end < end. */
-		error = msync_interval(vma, start, vma->vm_end, flags);
-		if (error)
-			goto out;
-		start = vma->vm_end;
-		vma = vma->vm_next;
-	}
-out:
-	up_read(&current->mm->mmap_sem);
-	return error;
-}
-
 static inline void setup_read_behavior(struct vm_area_struct * vma,
 	int behavior)
 {
@@ -2654,160 +2429,6 @@
 
 out:
 	up_write(&current->mm->mmap_sem);
-	return error;
-}
-
-/*
- * Later we can get more picky about what "in core" means precisely.
- * For now, simply check to see if the page is in the page cache,
- * and is up to date; i.e. that no page-in operation would be required
- * at this time if an application were to map and access this page.
- */
-static unsigned char mincore_page(struct vm_area_struct * vma,
-	unsigned long pgoff)
-{
-	unsigned char present = 0;
-	struct address_space * as = vma->vm_file->f_dentry->d_inode->i_mapping;
-	struct page * page, ** hash = page_hash(as, pgoff);
-
-	spin_lock(&pagecache_lock);
-	page = __find_page_nolock(as, pgoff, *hash);
-	if ((page) && (Page_Uptodate(page)))
-		present = 1;
-	spin_unlock(&pagecache_lock);
-
-	return present;
-}
-
-static long mincore_vma(struct vm_area_struct * vma,
-	unsigned long start, unsigned long end, unsigned char * vec)
-{
-	long error, i, remaining;
-	unsigned char * tmp;
-
-	error = -ENOMEM;
-	if (!vma->vm_file)
-		return error;
-
-	start = ((start - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
-	if (end > vma->vm_end)
-		end = vma->vm_end;
-	end = ((end - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
-
-	error = -EAGAIN;
-	tmp = (unsigned char *) __get_free_page(GFP_KERNEL);
-	if (!tmp)
-		return error;
-
-	/* (end - start) is # of pages, and also # of bytes in "vec */
-	remaining = (end - start),
-
-	error = 0;
-	for (i = 0; remaining > 0; remaining -= PAGE_SIZE, i++) {
-		int j = 0;
-		long thispiece = (remaining < PAGE_SIZE) ?
-						remaining : PAGE_SIZE;
-
-		while (j < thispiece)
-			tmp[j++] = mincore_page(vma, start++);
-
-		if (copy_to_user(vec + PAGE_SIZE * i, tmp, thispiece)) {
-			error = -EFAULT;
-			break;
-		}
-	}
-
-	free_page((unsigned long) tmp);
-	return error;
-}
-
-/*
- * The mincore(2) system call.
- *
- * mincore() returns the memory residency status of the pages in the
- * current process's address space specified by [addr, addr + len).
- * The status is returned in a vector of bytes.  The least significant
- * bit of each byte is 1 if the referenced page is in memory, otherwise
- * it is zero.
- *
- * Because the status of a page can change after mincore() checks it
- * but before it returns to the application, the returned vector may
- * contain stale information.  Only locked pages are guaranteed to
- * remain in memory.
- *
- * return values:
- *  zero    - success
- *  -EFAULT - vec points to an illegal address
- *  -EINVAL - addr is not a multiple of PAGE_CACHE_SIZE,
- *		or len has a nonpositive value
- *  -ENOMEM - Addresses in the range [addr, addr + len] are
- *		invalid for the address space of this process, or
- *		specify one or more pages which are not currently
- *		mapped
- *  -EAGAIN - A kernel resource was temporarily unavailable.
- */
-asmlinkage long sys_mincore(unsigned long start, size_t len,
-	unsigned char * vec)
-{
-	int index = 0;
-	unsigned long end;
-	struct vm_area_struct * vma;
-	int unmapped_error = 0;
-	long error = -EINVAL;
-
-	down_read(&current->mm->mmap_sem);
-
-	if (start & ~PAGE_CACHE_MASK)
-		goto out;
-	len = (len + ~PAGE_CACHE_MASK) & PAGE_CACHE_MASK;
-	end = start + len;
-	if (end < start)
-		goto out;
-
-	error = 0;
-	if (end == start)
-		goto out;
-
-	/*
-	 * If the interval [start,end) covers some unmapped address
-	 * ranges, just ignore them, but return -ENOMEM at the end.
-	 */
-	vma = find_vma(current->mm, start);
-	for (;;) {
-		/* Still start < end. */
-		error = -ENOMEM;
-		if (!vma)
-			goto out;
-
-		/* Here start < vma->vm_end. */
-		if (start < vma->vm_start) {
-			unmapped_error = -ENOMEM;
-			start = vma->vm_start;
-		}
-
-		/* Here vma->vm_start <= start < vma->vm_end. */
-		if (end <= vma->vm_end) {
-			if (start < end) {
-				error = mincore_vma(vma, start, end,
-							&vec[index]);
-				if (error)
-					goto out;
-			}
-			error = unmapped_error;
-			goto out;
-		}
-
-		/* Here vma->vm_start <= start < vma->vm_end < end. */
-		error = mincore_vma(vma, start, vma->vm_end, &vec[index]);
-		if (error)
-			goto out;
-		index += (vma->vm_end - start) >> PAGE_CACHE_SHIFT;
-		start = vma->vm_end;
-		vma = vma->vm_next;
-	}
-
-out:
-	up_read(&current->mm->mmap_sem);
 	return error;
 }
 
diff -Nru a/mm/memory.c b/mm/memory.c
--- a/mm/memory.c	Fri Mar 15 17:51:03 2002
+++ b/mm/memory.c	Fri Mar 15 17:51:03 2002
@@ -140,6 +140,9 @@
 		page_dir++;
 	} while (--nr);
 	spin_unlock(&mm->page_table_lock);
+
+	/* keep the page table cache within bounds */
+	check_pgt_cache();
 }
 
 pte_t * pte_alloc_map(struct mm_struct *mm, pmd_t *pmd, unsigned long address)
diff -Nru a/mm/mincore.c b/mm/mincore.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/mm/mincore.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,175 @@
+/*
+ *	linux/mm/mincore.c
+ *
+ * Copyright (C) 1994-1999  Linus Torvalds
+ */
+
+/*
+ * The mincore() system call.
+ */
+#include <linux/slab.h>
+#include <linux/pagemap.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+
+/*
+ * Later we can get more picky about what "in core" means precisely.
+ * For now, simply check to see if the page is in the page cache,
+ * and is up to date; i.e. that no page-in operation would be required
+ * at this time if an application were to map and access this page.
+ */
+static unsigned char mincore_page(struct vm_area_struct * vma,
+	unsigned long pgoff)
+{
+	unsigned char present = 0;
+	struct address_space * as = vma->vm_file->f_dentry->d_inode->i_mapping;
+	struct page * page, ** hash = page_hash(as, pgoff);
+
+	page = __find_get_page(as, pgoff, hash);
+	if (page) {
+		present = Page_Uptodate(page);
+		page_cache_release(page);
+	}
+
+	return present;
+}
+
+static long mincore_vma(struct vm_area_struct * vma,
+	unsigned long start, unsigned long end, unsigned char * vec)
+{
+	long error, i, remaining;
+	unsigned char * tmp;
+
+	error = -ENOMEM;
+	if (!vma->vm_file)
+		return error;
+
+	start = ((start - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
+	if (end > vma->vm_end)
+		end = vma->vm_end;
+	end = ((end - vma->vm_start) >> PAGE_SHIFT) + vma->vm_pgoff;
+
+	error = -EAGAIN;
+	tmp = (unsigned char *) __get_free_page(GFP_KERNEL);
+	if (!tmp)
+		return error;
+
+	/* (end - start) is # of pages, and also # of bytes in "vec */
+	remaining = (end - start),
+
+	error = 0;
+	for (i = 0; remaining > 0; remaining -= PAGE_SIZE, i++) {
+		int j = 0;
+		long thispiece = (remaining < PAGE_SIZE) ?
+						remaining : PAGE_SIZE;
+
+		while (j < thispiece)
+			tmp[j++] = mincore_page(vma, start++);
+
+		if (copy_to_user(vec + PAGE_SIZE * i, tmp, thispiece)) {
+			error = -EFAULT;
+			break;
+		}
+	}
+
+	free_page((unsigned long) tmp);
+	return error;
+}
+
+/*
+ * The mincore(2) system call.
+ *
+ * mincore() returns the memory residency status of the pages in the
+ * current process's address space specified by [addr, addr + len).
+ * The status is returned in a vector of bytes.  The least significant
+ * bit of each byte is 1 if the referenced page is in memory, otherwise
+ * it is zero.
+ *
+ * Because the status of a page can change after mincore() checks it
+ * but before it returns to the application, the returned vector may
+ * contain stale information.  Only locked pages are guaranteed to
+ * remain in memory.
+ *
+ * return values:
+ *  zero    - success
+ *  -EFAULT - vec points to an illegal address
+ *  -EINVAL - addr is not a multiple of PAGE_CACHE_SIZE,
+ *		or len has a nonpositive value
+ *  -ENOMEM - Addresses in the range [addr, addr + len] are
+ *		invalid for the address space of this process, or
+ *		specify one or more pages which are not currently
+ *		mapped
+ *  -EAGAIN - A kernel resource was temporarily unavailable.
+ */
+asmlinkage long sys_mincore(unsigned long start, size_t len,
+	unsigned char * vec)
+{
+	int index = 0;
+	unsigned long end;
+	struct vm_area_struct * vma;
+	int unmapped_error = 0;
+	long error = -EINVAL;
+
+	down_read(&current->mm->mmap_sem);
+
+	if (start & ~PAGE_CACHE_MASK)
+		goto out;
+	len = (len + ~PAGE_CACHE_MASK) & PAGE_CACHE_MASK;
+	end = start + len;
+	if (end < start)
+		goto out;
+
+	error = -EFAULT;
+	if (!access_ok(VERIFY_WRITE, (unsigned long) vec, len >> PAGE_SHIFT))
+		goto out;
+
+	error = 0;
+	if (end == start)
+		goto out;
+
+	/*
+	 * If the interval [start,end) covers some unmapped address
+	 * ranges, just ignore them, but return -ENOMEM at the end.
+	 */
+	vma = find_vma(current->mm, start);
+	for (;;) {
+		/* Still start < end. */
+		error = -ENOMEM;
+		if (!vma)
+			goto out;
+
+		/* Here start < vma->vm_end. */
+		if (start < vma->vm_start) {
+			unmapped_error = -ENOMEM;
+			start = vma->vm_start;
+		}
+
+		/* Here vma->vm_start <= start < vma->vm_end. */
+		if (end <= vma->vm_end) {
+			if (start < end) {
+				error = mincore_vma(vma, start, end,
+							&vec[index]);
+				if (error)
+					goto out;
+			}
+			error = unmapped_error;
+			goto out;
+		}
+
+		/* Here vma->vm_start <= start < vma->vm_end < end. */
+		error = mincore_vma(vma, start, vma->vm_end, &vec[index]);
+		if (error)
+			goto out;
+		index += (vma->vm_end - start) >> PAGE_CACHE_SHIFT;
+		start = vma->vm_end;
+		vma = vma->vm_next;
+	}
+
+out:
+	up_read(&current->mm->mmap_sem);
+	return error;
+}
diff -Nru a/mm/mprotect.c b/mm/mprotect.c
--- a/mm/mprotect.c	Fri Mar 15 17:51:02 2002
+++ b/mm/mprotect.c	Fri Mar 15 17:51:02 2002
@@ -280,7 +280,7 @@
 	end = start + len;
 	if (end < start)
 		return -EINVAL;
-	if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC))
+	if (prot & ~(PROT_READ | PROT_WRITE | PROT_EXEC | PROT_SEM))
 		return -EINVAL;
 	if (end == start)
 		return 0;
diff -Nru a/mm/msync.c b/mm/msync.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/mm/msync.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,217 @@
+/*
+ *	linux/mm/msync.c
+ *
+ * Copyright (C) 1994-1999  Linus Torvalds
+ */
+
+/*
+ * The msync() system call.
+ */
+#include <linux/slab.h>
+#include <linux/pagemap.h>
+#include <linux/mm.h>
+#include <linux/mman.h>
+
+#include <asm/pgtable.h>
+#include <asm/pgalloc.h>
+
+/*
+ * Called with mm->page_table_lock held to protect against other
+ * threads/the swapper from ripping pte's out from under us.
+ */
+static int filemap_sync_pte(pte_t *ptep, struct vm_area_struct *vma,
+	unsigned long address, unsigned int flags)
+{
+	pte_t pte = *ptep;
+
+	if (pte_present(pte) && pte_dirty(pte)) {
+		struct page *page = pte_page(pte);
+		if (VALID_PAGE(page) && !PageReserved(page) && ptep_test_and_clear_dirty(ptep)) {
+			flush_tlb_page(vma, address);
+			set_page_dirty(page);
+		}
+	}
+	return 0;
+}
+
+static inline int filemap_sync_pte_range(pmd_t * pmd,
+	unsigned long address, unsigned long end, 
+	struct vm_area_struct *vma, unsigned int flags)
+{
+	pte_t *pte;
+	int error;
+
+	if (pmd_none(*pmd))
+		return 0;
+	if (pmd_bad(*pmd)) {
+		pmd_ERROR(*pmd);
+		pmd_clear(pmd);
+		return 0;
+	}
+	pte = pte_offset_map(pmd, address);
+	if ((address & PMD_MASK) != (end & PMD_MASK))
+		end = (address & PMD_MASK) + PMD_SIZE;
+	error = 0;
+	do {
+		error |= filemap_sync_pte(pte, vma, address, flags);
+		address += PAGE_SIZE;
+		pte++;
+	} while (address && (address < end));
+
+	pte_unmap(pte - 1);
+
+	return error;
+}
+
+static inline int filemap_sync_pmd_range(pgd_t * pgd,
+	unsigned long address, unsigned long end, 
+	struct vm_area_struct *vma, unsigned int flags)
+{
+	pmd_t * pmd;
+	int error;
+
+	if (pgd_none(*pgd))
+		return 0;
+	if (pgd_bad(*pgd)) {
+		pgd_ERROR(*pgd);
+		pgd_clear(pgd);
+		return 0;
+	}
+	pmd = pmd_offset(pgd, address);
+	if ((address & PGDIR_MASK) != (end & PGDIR_MASK))
+		end = (address & PGDIR_MASK) + PGDIR_SIZE;
+	error = 0;
+	do {
+		error |= filemap_sync_pte_range(pmd, address, end, vma, flags);
+		address = (address + PMD_SIZE) & PMD_MASK;
+		pmd++;
+	} while (address && (address < end));
+	return error;
+}
+
+int filemap_sync(struct vm_area_struct * vma, unsigned long address,
+	size_t size, unsigned int flags)
+{
+	pgd_t * dir;
+	unsigned long end = address + size;
+	int error = 0;
+
+	/* Aquire the lock early; it may be possible to avoid dropping
+	 * and reaquiring it repeatedly.
+	 */
+	spin_lock(&vma->vm_mm->page_table_lock);
+
+	dir = pgd_offset(vma->vm_mm, address);
+	flush_cache_range(vma, address, end);
+	if (address >= end)
+		BUG();
+	do {
+		error |= filemap_sync_pmd_range(dir, address, end, vma, flags);
+		address = (address + PGDIR_SIZE) & PGDIR_MASK;
+		dir++;
+	} while (address && (address < end));
+	flush_tlb_range(vma, end - size, end);
+
+	spin_unlock(&vma->vm_mm->page_table_lock);
+
+	return error;
+}
+
+/*
+ * MS_SYNC syncs the entire file - including mappings.
+ *
+ * MS_ASYNC initiates writeout of just the dirty mapped data.
+ * This provides no guarantee of file integrity - things like indirect
+ * blocks may not have started writeout.  MS_ASYNC is primarily useful
+ * where the application knows that it has finished with the data and
+ * wishes to intelligently schedule its own I/O traffic.
+ */
+static int msync_interval(struct vm_area_struct * vma,
+	unsigned long start, unsigned long end, int flags)
+{
+	int ret = 0;
+	struct file * file = vma->vm_file;
+
+	if (file && (vma->vm_flags & VM_SHARED)) {
+		ret = filemap_sync(vma, start, end-start, flags);
+
+		if (!ret && (flags & (MS_SYNC|MS_ASYNC))) {
+			struct inode * inode = file->f_dentry->d_inode;
+
+			down(&inode->i_sem);
+			ret = filemap_fdatasync(inode->i_mapping);
+			if (flags & MS_SYNC) {
+				int err;
+
+				if (file->f_op && file->f_op->fsync) {
+					err = file->f_op->fsync(file, file->f_dentry, 1);
+					if (err && !ret)
+						ret = err;
+				}
+				err = filemap_fdatawait(inode->i_mapping);
+				if (err && !ret)
+					ret = err;
+			}
+			up(&inode->i_sem);
+		}
+	}
+	return ret;
+}
+
+asmlinkage long sys_msync(unsigned long start, size_t len, int flags)
+{
+	unsigned long end;
+	struct vm_area_struct * vma;
+	int unmapped_error, error = -EINVAL;
+
+	down_read(&current->mm->mmap_sem);
+	if (start & ~PAGE_MASK)
+		goto out;
+	len = (len + ~PAGE_MASK) & PAGE_MASK;
+	end = start + len;
+	if (end < start)
+		goto out;
+	if (flags & ~(MS_ASYNC | MS_INVALIDATE | MS_SYNC))
+		goto out;
+	error = 0;
+	if (end == start)
+		goto out;
+	/*
+	 * If the interval [start,end) covers some unmapped address ranges,
+	 * just ignore them, but return -EFAULT at the end.
+	 */
+	vma = find_vma(current->mm, start);
+	unmapped_error = 0;
+	for (;;) {
+		/* Still start < end. */
+		error = -EFAULT;
+		if (!vma)
+			goto out;
+		/* Here start < vma->vm_end. */
+		if (start < vma->vm_start) {
+			unmapped_error = -EFAULT;
+			start = vma->vm_start;
+		}
+		/* Here vma->vm_start <= start < vma->vm_end. */
+		if (end <= vma->vm_end) {
+			if (start < end) {
+				error = msync_interval(vma, start, end, flags);
+				if (error)
+					goto out;
+			}
+			error = unmapped_error;
+			goto out;
+		}
+		/* Here vma->vm_start <= start < vma->vm_end < end. */
+		error = msync_interval(vma, start, vma->vm_end, flags);
+		if (error)
+			goto out;
+		start = vma->vm_end;
+		vma = vma->vm_next;
+	}
+out:
+	up_read(&current->mm->mmap_sem);
+	return error;
+}
+
+
diff -Nru a/mm/page_alloc.c b/mm/page_alloc.c
--- a/mm/page_alloc.c	Fri Mar 15 17:51:01 2002
+++ b/mm/page_alloc.c	Fri Mar 15 17:51:01 2002
@@ -776,8 +776,8 @@
 		 * per zone.
 		 */
 		zone->wait_table_size = wait_table_size(size);
-		zone->wait_table_shift =
-			BITS_PER_LONG - wait_table_bits(zone->wait_table_size);
+		zone->wait_table_bits =
+			wait_table_bits(zone->wait_table_size);
 		zone->wait_table = (wait_queue_head_t *)
 			alloc_bootmem_node(pgdat, zone->wait_table_size
 						* sizeof(wait_queue_head_t));
diff -Nru a/mm/shmem.c b/mm/shmem.c
--- a/mm/shmem.c	Fri Mar 15 17:51:03 2002
+++ b/mm/shmem.c	Fri Mar 15 17:51:03 2002
@@ -42,7 +42,6 @@
 static struct address_space_operations shmem_aops;
 static struct file_operations shmem_file_operations;
 static struct inode_operations shmem_inode_operations;
-static struct file_operations shmem_dir_operations;
 static struct inode_operations shmem_dir_inode_operations;
 static struct vm_operations_struct shmem_vm_ops;
 
@@ -708,7 +707,7 @@
 		case S_IFDIR:
 			inode->i_nlink++;
 			inode->i_op = &shmem_dir_inode_operations;
-			inode->i_fop = &shmem_dir_operations;
+			inode->i_fop = &simple_dir_operations;
 			break;
 		case S_IFLNK:
 			break;
@@ -758,6 +757,11 @@
 	long		status;
 	int		err;
 
+	if ((ssize_t) count < 0)
+		return -EINVAL;
+
+	if (!access_ok(VERIFY_READ, buf, count))
+		return -EFAULT;
 
 	down(&inode->i_sem);
 
@@ -971,17 +975,6 @@
 }
 
 /*
- * Lookup the data. This is trivial - if the dentry didn't already
- * exist, we know it is negative.
- */
-/* SMP-safe */
-static struct dentry * shmem_lookup(struct inode *dir, struct dentry *dentry)
-{
-	d_add(dentry, NULL);
-	return NULL;
-}
-
-/*
  * File creation. Allocate an inode, and we're done..
  */
 /* SMP-safe */
@@ -1021,6 +1014,9 @@
 {
 	struct inode *inode = old_dentry->d_inode;
 
+	if (S_ISDIR(inode->i_mode))
+		return -EPERM;
+
 	inode->i_ctime = dir->i_ctime = dir->i_mtime = CURRENT_TIME;
 	inode->i_nlink++;
 	atomic_inc(&inode->i_count);	/* New dentry reference */
@@ -1111,16 +1107,14 @@
 	char *kaddr;
 	struct shmem_inode_info * info;
 
+	len = strlen(symname) + 1;
+	if (len > PAGE_CACHE_SIZE)
+		return -ENAMETOOLONG;
+
 	inode = shmem_get_inode(dir->i_sb, S_IFLNK|S_IRWXUGO, 0);
 	if (!inode)
 		return -ENOSPC;
 
-	len = strlen(symname) + 1;
-	if (len > PAGE_CACHE_SIZE) {
-		iput(inode);
-		return -ENAMETOOLONG;
-	}
-		
 	info = SHMEM_I(inode);
 	inode->i_size = len-1;
 	if (len <= sizeof(struct shmem_inode_info)) {
@@ -1201,7 +1195,7 @@
 	follow_link:	shmem_follow_link,
 };
 
-static int shmem_parse_options(char *options, int *mode, unsigned long * blocks, unsigned long *inodes)
+static int shmem_parse_options(char *options, int *mode, uid_t *uid, gid_t *gid, unsigned long * blocks, unsigned long *inodes)
 {
 	char *this_char, *value, *rest;
 
@@ -1213,7 +1207,7 @@
 			*value++ = 0;
 		} else {
 			printk(KERN_ERR 
-			    "shmem_parse_options: No value for option '%s'\n", 
+			    "tmpfs: No value for mount option '%s'\n", 
 			    this_char);
 			return 1;
 		}
@@ -1238,8 +1232,20 @@
 			*mode = simple_strtoul(value,&rest,8);
 			if (*rest)
 				goto bad_val;
+		} else if (!strcmp(this_char,"uid")) {
+			if (!uid)
+				continue;
+			*uid = simple_strtoul(value,&rest,0);
+			if (*rest)
+				goto bad_val;
+		} else if (!strcmp(this_char,"gid")) {
+			if (!gid)
+				continue;
+			*gid = simple_strtoul(value,&rest,0);
+			if (*rest)
+				goto bad_val;
 		} else {
-			printk(KERN_ERR "shmem_parse_options: Bad option %s\n",
+			printk(KERN_ERR "tmpfs: Bad mount option %s\n",
 			       this_char);
 			return 1;
 		}
@@ -1247,7 +1253,7 @@
 	return 0;
 
 bad_val:
-	printk(KERN_ERR "shmem_parse_options: Bad value '%s' for option '%s'\n", 
+	printk(KERN_ERR "tmpfs: Bad value '%s' for mount option '%s'\n", 
 	       value, this_char);
 	return 1;
 
@@ -1259,7 +1265,7 @@
 	unsigned long max_blocks = sbinfo->max_blocks;
 	unsigned long max_inodes = sbinfo->max_inodes;
 
-	if (shmem_parse_options (data, NULL, &max_blocks, &max_inodes))
+	if (shmem_parse_options (data, NULL, NULL, NULL, &max_blocks, &max_inodes))
 		return -EINVAL;
 	return shmem_set_size(sbinfo, max_blocks, max_inodes);
 }
@@ -1276,6 +1282,8 @@
 	struct dentry * root;
 	unsigned long blocks, inodes;
 	int mode   = S_IRWXUGO | S_ISVTX;
+	uid_t uid = current->fsuid;
+	gid_t gid = current->fsgid;
 	struct shmem_sb_info *sbinfo = SHMEM_SB(sb);
 	struct sysinfo si;
 
@@ -1287,10 +1295,8 @@
 	blocks = inodes = si.totalram / 2;
 
 #ifdef CONFIG_TMPFS
-	if (shmem_parse_options (data, &mode, &blocks, &inodes)) {
-		printk(KERN_ERR "tmpfs invalid option\n");
+	if (shmem_parse_options (data, &mode, &uid, &gid, &blocks, &inodes))
 		return -EINVAL;
-	}
 #endif
 
 	spin_lock_init (&sbinfo->stat_lock);
@@ -1307,6 +1313,8 @@
 	if (!inode)
 		return -ENOMEM;
 
+	inode->i_uid = uid;
+	inode->i_gid = gid;
 	root = d_alloc_root(inode);
 	if (!root) {
 		iput(inode);
@@ -1376,18 +1384,10 @@
 	truncate:	shmem_truncate,
 };
 
-static struct file_operations shmem_dir_operations = {
-	read:		generic_read_dir,
-	readdir:	dcache_readdir,
-#ifdef CONFIG_TMPFS
-	fsync:		shmem_sync_file,
-#endif
-};
-
 static struct inode_operations shmem_dir_inode_operations = {
 #ifdef CONFIG_TMPFS
 	create:		shmem_create,
-	lookup:		shmem_lookup,
+	lookup:		simple_lookup,
 	link:		shmem_link,
 	unlink:		shmem_unlink,
 	symlink:	shmem_symlink,
@@ -1425,20 +1425,21 @@
 	owner:		THIS_MODULE,
 	name:		"shmem",
 	get_sb:		shmem_get_sb,
-	fs_flags:	FS_LITTER,
+	kill_sb:	kill_litter_super,
 };
 static struct file_system_type tmpfs_fs_type = {
 	owner:		THIS_MODULE,
 	name:		"tmpfs",
 	get_sb:		shmem_get_sb,
-	fs_flags:	FS_LITTER,
+	kill_sb:	kill_litter_super,
 };
 #else
 static struct file_system_type tmpfs_fs_type = {
 	owner:		THIS_MODULE,
 	name:		"tmpfs",
 	get_sb:		shmem_get_sb,
-	fs_flags:	FS_LITTER|FS_NOMOUNT,
+	kill_sb:	kill_litter_super,
+	fs_flags:	FS_NOMOUNT,
 };
 #endif
 static struct vfsmount *shm_mnt;
diff -Nru a/net/8021q/vlan.c b/net/8021q/vlan.c
--- a/net/8021q/vlan.c	Fri Mar 15 17:51:02 2002
+++ b/net/8021q/vlan.c	Fri Mar 15 17:51:02 2002
@@ -8,7 +8,9 @@
  * 
  * Fixes:
  *              Fix for packet capture - Nick Eggleston <nick@dccinc.com>;
- *
+ *		Add HW acceleration hooks - David S. Miller <davem@redhat.com>;
+ *		Correct all the locking - David S. Miller <davem@redhat.com>;
+ *		Use hash table for VLAN groups - David S. Miller <davem@redhat.com>
  *
  *		This program is free software; you can redistribute it and/or
  *		modify it under the terms of the GNU General Public License
@@ -37,12 +39,15 @@
 /* Global VLAN variables */
 
 /* Our listing of VLAN group(s) */
-struct vlan_group *p802_1Q_vlan_list;
+struct vlan_group *vlan_group_hash[VLAN_GRP_HASH_SIZE];
+spinlock_t vlan_group_lock = SPIN_LOCK_UNLOCKED;
+#define vlan_grp_hashfn(IDX)	((((IDX) >> VLAN_GRP_HASH_SHIFT) ^ (IDX)) & VLAN_GRP_HASH_MASK)
 
 static char vlan_fullname[] = "802.1Q VLAN Support";
 static unsigned int vlan_version = 1;
-static unsigned int vlan_release = 6;
-static char vlan_copyright[] = " Ben Greear <greearb@candelatech.com>";
+static unsigned int vlan_release = 7;
+static char vlan_copyright[] = "Ben Greear <greearb@candelatech.com>";
+static char vlan_buggyright[] = "David S. Miller <davem@redhat.com>";
 
 static int vlan_device_event(struct notifier_block *, unsigned long, void *);
 
@@ -55,9 +60,6 @@
 /* Determines interface naming scheme. */
 unsigned short vlan_name_type = VLAN_NAME_TYPE_RAW_PLUS_VID_NO_PAD;
 
-/* Counter for how many NON-VLAN protos we've received on a VLAN. */
-unsigned long vlan_bad_proto_recvd = 0;
-
 /* DO reorder the header by default */
 unsigned short vlan_default_dev_flags = 1;
 
@@ -83,6 +85,8 @@
 
 	printk(VLAN_INF "%s v%u.%u %s\n",
 	       vlan_fullname, vlan_version, vlan_release, vlan_copyright);
+	printk(VLAN_INF "All bugs added by %s\n",
+	       vlan_buggyright);
 
 	/* proc file system initialization */
 	err = vlan_proc_init();
@@ -100,71 +104,83 @@
 
 	vlan_ioctl_hook = vlan_ioctl_handler;
 
-	printk(VLAN_INF "%s Initialization complete.\n", VLAN_NAME);
 	return 0;
 }
 
 /*
- * Cleanup of groups before exit
- */
-
-static void vlan_group_cleanup(void)
-{
-	struct vlan_group *grp = NULL;
-	struct vlan_group *nextgroup;
-
-	for (grp = p802_1Q_vlan_list; (grp != NULL);) {
-		nextgroup = grp->next;
-		kfree(grp);
-		grp = nextgroup;
-	}
-	p802_1Q_vlan_list = NULL;
-}
-
-/*
  *     Module 'remove' entry point.
  *     o delete /proc/net/router directory and static entries.
  */ 
 static void __exit vlan_cleanup_module(void)
 {
+	int i;
+
+	/* This table must be empty if there are no module
+	 * references left.
+	 */
+	for (i = 0; i < VLAN_GRP_HASH_SIZE; i++) {
+		if (vlan_group_hash[i] != NULL)
+			BUG();
+	}
+
 	/* Un-register us from receiving netdevice events */
 	unregister_netdevice_notifier(&vlan_notifier_block);
 
 	dev_remove_pack(&vlan_packet_type);
 	vlan_proc_cleanup();
-	vlan_group_cleanup();
 	vlan_ioctl_hook = NULL;
 }
 
 module_init(vlan_proto_init);
 module_exit(vlan_cleanup_module);
 
-/**  Will search linearly for now, based on device index.  Could
- * hash, or directly link, this some day. --Ben
- * TODO:  Potential performance issue here.  Linear search where N is
- *        the number of 'real' devices used by VLANs.
- */
-struct vlan_group* vlan_find_group(int real_dev_ifindex)
+/* Must be invoked with vlan_group_lock held. */
+static struct vlan_group *__vlan_find_group(int real_dev_ifindex)
 {
-	struct vlan_group *grp = NULL;
+	struct vlan_group *grp;
 
-	br_read_lock_bh(BR_NETPROTO_LOCK);
-	for (grp = p802_1Q_vlan_list;
-	     ((grp != NULL) && (grp->real_dev_ifindex != real_dev_ifindex));
+	for (grp = vlan_group_hash[vlan_grp_hashfn(real_dev_ifindex)];
+	     grp != NULL;
 	     grp = grp->next) {
-		/* nothing */ ;
+		if (grp->real_dev_ifindex == real_dev_ifindex)
+			break;
 	}
-	br_read_unlock_bh(BR_NETPROTO_LOCK);
 
 	return grp;
 }
 
-/*  Find the protocol handler.  Assumes VID < 0xFFF.
+/* Must hold vlan_group_lock. */
+static void __grp_hash(struct vlan_group *grp)
+{
+	struct vlan_group **head;
+
+	head = &vlan_group_hash[vlan_grp_hashfn(grp->real_dev_ifindex)];
+	grp->next = *head;
+	*head = grp;
+}
+
+/* Must hold vlan_group_lock. */
+static void __grp_unhash(struct vlan_group *grp)
+{
+	struct vlan_group *next, **pprev;
+
+	pprev = &vlan_group_hash[vlan_grp_hashfn(grp->real_dev_ifindex)];
+	next = *pprev;
+	while (next != grp) {
+		pprev = &next->next;
+		next = *pprev;
+	}
+	*pprev = grp->next;
+}
+
+/*  Find the protocol handler.  Assumes VID < VLAN_VID_MASK.
+ *
+ * Must be invoked with vlan_group_lock held.
  */
-struct net_device *find_802_1Q_vlan_dev(struct net_device *real_dev,
-                                        unsigned short VID)
+struct net_device *__find_vlan_dev(struct net_device *real_dev,
+				   unsigned short VID)
 {
-	struct vlan_group *grp = vlan_find_group(real_dev->ifindex);
+	struct vlan_group *grp = __vlan_find_group(real_dev->ifindex);
 
 	if (grp)
                 return grp->vlan_devices[VID];
@@ -172,109 +188,143 @@
 	return NULL;
 }
 
-/** This method will explicitly do a dev_put on the device if do_dev_put
- * is TRUE.  This gets around a difficulty with reference counting, and
- * the unregister-by-name (below).  If do_locks is true, it will grab
- * a lock before un-registering.  If do_locks is false, it is assumed that
- * the lock has already been grabbed externally...  --Ben
+/* This returns 0 if everything went fine.
+ * It will return 1 if the group was killed as a result.
+ * A negative return indicates failure.
+ *
+ * The RTNL lock must be held.
  */
-int unregister_802_1Q_vlan_dev(int real_dev_ifindex, unsigned short vlan_id,
-			       int do_dev_put, int do_locks)
+static int unregister_vlan_dev(struct net_device *real_dev,
+			       unsigned short vlan_id)
 {
 	struct net_device *dev = NULL;
+	int real_dev_ifindex = real_dev->ifindex;
 	struct vlan_group *grp;
+	int i, ret;
 
 #ifdef VLAN_DEBUG
 	printk(VLAN_DBG __FUNCTION__ ": VID: %i\n", vlan_id);
 #endif
 
 	/* sanity check */
-	if ((vlan_id >= 0xFFF) || (vlan_id <= 0))
+	if ((vlan_id >= VLAN_VID_MASK) || (vlan_id <= 0))
 		return -EINVAL;
 
-	grp = vlan_find_group(real_dev_ifindex);
+	spin_lock_bh(&vlan_group_lock);
+	grp = __vlan_find_group(real_dev_ifindex);
+	spin_unlock_bh(&vlan_group_lock);
+
+	ret = 0;
+
 	if (grp) {
 		dev = grp->vlan_devices[vlan_id];
 		if (dev) {
 			/* Remove proc entry */
 			vlan_proc_rem_dev(dev);
 
-			/* Take it out of our own structures */
-			grp->vlan_devices[vlan_id] = NULL;
+			/* Take it out of our own structures, but be sure to
+			 * interlock with HW accelerating devices or SW vlan
+			 * input packet processing.
+			 */
+			if (real_dev->features &
+			    (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER)) {
+				real_dev->vlan_rx_kill_vid(real_dev, vlan_id);
+			} else {
+				br_write_lock(BR_NETPROTO_LOCK);
+				grp->vlan_devices[vlan_id] = NULL;
+				br_write_unlock(BR_NETPROTO_LOCK);
+			}
 
-			/* Take it out of the global list of devices.
-			 *  NOTE:  This deletes dev, don't access it again!!
+			/* Caller unregisters (and if necessary, puts)
+			 * VLAN device, but we get rid of the reference to
+			 * real_dev here.
 			 */
+			dev_put(real_dev);
 
-			if (do_dev_put)
-				dev_put(dev);
+			/* If the group is now empty, kill off the
+			 * group.
+			 */
+			for (i = 0; i < VLAN_VID_MASK; i++)
+				if (grp->vlan_devices[i])
+					break;
+
+			if (i == VLAN_VID_MASK) {
+				if (real_dev->features & NETIF_F_HW_VLAN_RX)
+					real_dev->vlan_rx_register(real_dev, NULL);
+
+				spin_lock_bh(&vlan_group_lock);
+				__grp_unhash(grp);
+				spin_unlock_bh(&vlan_group_lock);
 
-			/* TODO:  Please review this code. */
-			if (do_locks) {
-				rtnl_lock();
-				unregister_netdevice(dev);
-				rtnl_unlock();
-			} else {
-				unregister_netdevice(dev);
+				ret = 1;
 			}
 
 			MOD_DEC_USE_COUNT;
 		}
 	}
-        
-        return 0;
+
+        return ret;
 }
 
-int unregister_802_1Q_vlan_device(const char *vlan_IF_name)
+static int unregister_vlan_device(const char *vlan_IF_name)
 {
 	struct net_device *dev = NULL;
+	int ret;
 
-#ifdef VLAN_DEBUG
-	printk(VLAN_DBG __FUNCTION__ ": unregister VLAN by name, name -:%s:-\n",
-	       vlan_IF_name);
-#endif
 
 	dev = dev_get_by_name(vlan_IF_name);
+	ret = -EINVAL;
 	if (dev) {
 		if (dev->priv_flags & IFF_802_1Q_VLAN) {
-			return unregister_802_1Q_vlan_dev(
-				VLAN_DEV_INFO(dev)->real_dev->ifindex,
-				(unsigned short)(VLAN_DEV_INFO(dev)->vlan_id),
-				1 /* do dev_put */, 1 /* do locking */);
+			rtnl_lock();
+
+			ret = unregister_vlan_dev(VLAN_DEV_INFO(dev)->real_dev,
+						  VLAN_DEV_INFO(dev)->vlan_id);
+
+			dev_put(dev);
+			unregister_netdevice(dev);
+
+			rtnl_unlock();
+
+			if (ret == 1)
+				ret = 0;
 		} else {
 			printk(VLAN_ERR __FUNCTION__
 			       ": ERROR:	Tried to remove a non-vlan device "
 			       "with VLAN code, name: %s  priv_flags: %hX\n",
 			       dev->name, dev->priv_flags);
 			dev_put(dev);
-			return -EPERM;
+			ret = -EPERM;
 		}
 	} else {
 #ifdef VLAN_DEBUG
 		printk(VLAN_DBG __FUNCTION__ ": WARNING: Could not find dev.\n");
 #endif
-		return -EINVAL;
+		ret = -EINVAL;
 	}
+
+	return ret;
 }
 
 /*  Attach a VLAN device to a mac address (ie Ethernet Card).
  *  Returns the device that was created, or NULL if there was
  *  an error of some kind.
  */
-struct net_device *register_802_1Q_vlan_device(const char* eth_IF_name,
+static struct net_device *register_vlan_device(const char *eth_IF_name,
 					       unsigned short VLAN_ID)
 {
 	struct vlan_group *grp;
 	struct net_device *new_dev;
 	struct net_device *real_dev; /* the ethernet device */
 	int malloc_size = 0;
+	int r;
 
 #ifdef VLAN_DEBUG
 	printk(VLAN_DBG __FUNCTION__ ": if_name -:%s:-	vid: %i\n",
 	       eth_IF_name, VLAN_ID);
 #endif
 
-	if (VLAN_ID >= 0xfff)
+	if (VLAN_ID >= VLAN_VID_MASK)
 		goto out_ret_null;
 
 	/* find the device relating to eth_IF_name. */
@@ -282,14 +332,47 @@
 	if (!real_dev)
 		goto out_ret_null;
 
-	/* TODO:  Make sure this device can really handle having a VLAN attached
-	 * to it...
+	if (real_dev->features & NETIF_F_VLAN_CHALLENGED) {
+		printk(VLAN_DBG __FUNCTION__ ": VLANs not supported on %s.\n",
+		       real_dev->name);
+		goto out_put_dev;
+	}
+
+	if ((real_dev->features & NETIF_F_HW_VLAN_RX) &&
+	    (real_dev->vlan_rx_register == NULL ||
+	     real_dev->vlan_rx_kill_vid == NULL)) {
+		printk(VLAN_DBG __FUNCTION__ ": Device %s has buggy VLAN hw accel.\n",
+		       real_dev->name);
+		goto out_put_dev;
+	}
+
+	if ((real_dev->features & NETIF_F_HW_VLAN_FILTER) &&
+	    (real_dev->vlan_rx_add_vid == NULL ||
+	     real_dev->vlan_rx_kill_vid == NULL)) {
+		printk(VLAN_DBG __FUNCTION__ ": Device %s has buggy VLAN hw accel.\n",
+		       real_dev->name);
+		goto out_put_dev;
+	}
+
+	/* From this point on, all the data structures must remain
+	 * consistent.
+	 */
+	rtnl_lock();
+
+	/* The real device must be up and operating in order to
+	 * assosciate a VLAN device with it.
 	 */
-	if (find_802_1Q_vlan_dev(real_dev, VLAN_ID)) {
+	if (!(real_dev->flags & IFF_UP))
+		goto out_unlock;
+
+	spin_lock_bh(&vlan_group_lock);
+	r = (__find_vlan_dev(real_dev, VLAN_ID) != NULL);
+	spin_unlock_bh(&vlan_group_lock);
+
+	if (r) {
 		/* was already registered. */
 		printk(VLAN_DBG __FUNCTION__ ": ALREADY had VLAN registered\n");
-		dev_put(real_dev);
-		return NULL;
+		goto out_unlock;
 	}
 
 	malloc_size = (sizeof(struct net_device));
@@ -298,15 +381,14 @@
 		     new_dev, malloc_size);
 
 	if (new_dev == NULL)
-		goto out_put_dev;
+		goto out_unlock;
 
 	memset(new_dev, 0, malloc_size);
 
-	/* set us up to not use a Qdisc, as the underlying Hardware device
+	/* Set us up to have no queue, as the underlying Hardware device
 	 * can do all the queueing we could want.
 	 */
-	/* new_dev->qdisc_sleeping = &noqueue_qdisc;   Not needed it seems. */
-	new_dev->tx_queue_len = 0; /* This should effectively give us no queue. */
+	new_dev->tx_queue_len = 0;
 
 	/* Gotta set up the fields for the device. */
 #ifdef VLAN_DEBUG
@@ -368,8 +450,11 @@
 	/* TODO: maybe just assign it to be ETHERNET? */
 	new_dev->type = real_dev->type;
 
-	/* Regular ethernet + 4 bytes (18 total). */
-	new_dev->hard_header_len = VLAN_HLEN + real_dev->hard_header_len;
+	new_dev->hard_header_len = real_dev->hard_header_len;
+	if (!(real_dev->features & NETIF_F_HW_VLAN_TX)) {
+		/* Regular ethernet + 4 bytes (18 total). */
+		new_dev->hard_header_len += VLAN_HLEN;
+	}
 
 	new_dev->priv = kmalloc(sizeof(struct vlan_dev_info),
 				GFP_KERNEL);
@@ -377,10 +462,8 @@
 		     new_dev->priv,
 		     sizeof(struct vlan_dev_info));
 	    
-	if (new_dev->priv == NULL) {
-		kfree(new_dev);
-		goto out_put_dev;
-	}
+	if (new_dev->priv == NULL)
+		goto out_free_newdev;
 
 	memset(new_dev->priv, 0, sizeof(struct vlan_dev_info));
 
@@ -390,15 +473,21 @@
 
 	new_dev->open = vlan_dev_open;
 	new_dev->stop = vlan_dev_stop;
-	new_dev->hard_header = vlan_dev_hard_header;
 
-	new_dev->hard_start_xmit = vlan_dev_hard_start_xmit;
-	new_dev->rebuild_header = vlan_dev_rebuild_header;
+	if (real_dev->features & NETIF_F_HW_VLAN_TX) {
+		new_dev->hard_header = real_dev->hard_header;
+		new_dev->hard_start_xmit = vlan_dev_hwaccel_hard_start_xmit;
+		new_dev->rebuild_header = real_dev->rebuild_header;
+	} else {
+		new_dev->hard_header = vlan_dev_hard_header;
+		new_dev->hard_start_xmit = vlan_dev_hard_start_xmit;
+		new_dev->rebuild_header = vlan_dev_rebuild_header;
+	}
 	new_dev->hard_header_parse = real_dev->hard_header_parse;
 	new_dev->set_mac_address = vlan_dev_set_mac_address;
 	new_dev->set_multicast_list = vlan_dev_set_multicast_list;
 
-	VLAN_DEV_INFO(new_dev)->vlan_id = VLAN_ID; /* 1 through 0xFFF */
+	VLAN_DEV_INFO(new_dev)->vlan_id = VLAN_ID; /* 1 through VLAN_VID_MASK */
 	VLAN_DEV_INFO(new_dev)->real_dev = real_dev;
 	VLAN_DEV_INFO(new_dev)->dent = NULL;
 	VLAN_DEV_INFO(new_dev)->flags = vlan_default_dev_flags;
@@ -411,37 +500,39 @@
 	/* So, got the sucker initialized, now lets place
 	 * it into our local structure.
 	 */
-	grp = vlan_find_group(real_dev->ifindex);
+	spin_lock_bh(&vlan_group_lock);
+	grp = __vlan_find_group(real_dev->ifindex);
+	spin_unlock_bh(&vlan_group_lock);
+
+	/* Note, we are running under the RTNL semaphore
+	 * so it cannot "appear" on us.
+	 */
 	if (!grp) { /* need to add a new group */
 		grp = kmalloc(sizeof(struct vlan_group), GFP_KERNEL);
-		VLAN_MEM_DBG("grp malloc, addr: %p  size: %i\n",
-			     grp, sizeof(struct vlan_group));
-		if (!grp) {
-			kfree(new_dev->priv);
-			VLAN_FMEM_DBG("new_dev->priv free, addr: %p\n",
-				      new_dev->priv);
-			kfree(new_dev);
-			VLAN_FMEM_DBG("new_dev free, addr: %p\n", new_dev);
-
-			goto out_put_dev;
-		}
+		if (!grp)
+			goto out_free_newdev_priv;
 					
-		printk(KERN_ALERT "VLAN REGISTER:  Allocated new group.\n");
+		/* printk(KERN_ALERT "VLAN REGISTER:  Allocated new group.\n"); */
 		memset(grp, 0, sizeof(struct vlan_group));
 		grp->real_dev_ifindex = real_dev->ifindex;
 
-		br_write_lock_bh(BR_NETPROTO_LOCK);
-		grp->next = p802_1Q_vlan_list;
-		p802_1Q_vlan_list = grp;
-		br_write_unlock_bh(BR_NETPROTO_LOCK);
+		spin_lock_bh(&vlan_group_lock);
+		__grp_hash(grp);
+		spin_unlock_bh(&vlan_group_lock);
+
+		if (real_dev->features & NETIF_F_HW_VLAN_RX)
+			real_dev->vlan_rx_register(real_dev, grp);
 	}
 	    
 	grp->vlan_devices[VLAN_ID] = new_dev;
+
 	vlan_proc_add_dev(new_dev); /* create it's proc entry */
 
-	/* TODO: Please check this: RTNL   --Ben */
-	rtnl_lock();
+	if (real_dev->features & NETIF_F_HW_VLAN_FILTER)
+		real_dev->vlan_rx_add_vid(real_dev, VLAN_ID);
+
 	register_netdevice(new_dev);
+
 	rtnl_unlock();
 	    
 	/* NOTE:  We have a reference to the real device,
@@ -453,6 +544,15 @@
 #endif
 	return new_dev;
 
+out_free_newdev_priv:
+	kfree(new_dev->priv);
+
+out_free_newdev:
+	kfree(new_dev);
+
+out_unlock:
+	rtnl_unlock();
+
 out_put_dev:
 	dev_put(real_dev);
 
@@ -464,78 +564,78 @@
 {
 	struct net_device *dev = (struct net_device *)(ptr);
 	struct vlan_group *grp = NULL;
-	int i = 0;
+	int i, flgs;
 	struct net_device *vlandev = NULL;
 
+	spin_lock_bh(&vlan_group_lock);
+	grp = __vlan_find_group(dev->ifindex);
+	spin_unlock_bh(&vlan_group_lock);
+
+	if (!grp)
+		goto out;
+
+	/* It is OK that we do not hold the group lock right now,
+	 * as we run under the RTNL lock.
+	 */
+
 	switch (event) {
 	case NETDEV_CHANGEADDR:
-		/* Ignore for now */
-		break;
-
 	case NETDEV_GOING_DOWN:
 		/* Ignore for now */
 		break;
 
 	case NETDEV_DOWN:
-		/* TODO:  Please review this code. */
-		/* put all related VLANs in the down state too. */
-		for (grp = p802_1Q_vlan_list; grp != NULL; grp = grp->next) {
-			int flgs = 0;
-
-			for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
-				vlandev = grp->vlan_devices[i];
-				if (!vlandev ||
-				    (VLAN_DEV_INFO(vlandev)->real_dev != dev) ||
-				    (!(vlandev->flags & IFF_UP)))
-					continue;
-
-				flgs = vlandev->flags;
-				flgs &= ~IFF_UP;
-				dev_change_flags(vlandev, flgs);
-			}
+		/* Put all VLANs for this dev in the down state too.  */
+		for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
+			vlandev = grp->vlan_devices[i];
+			if (!vlandev)
+				continue;
+
+			flgs = vlandev->flags;
+			if (!(flgs & IFF_UP))
+				continue;
+
+			dev_change_flags(vlandev, flgs & ~IFF_UP);
 		}
 		break;
 
 	case NETDEV_UP:
-		/* TODO:  Please review this code. */
-		/* put all related VLANs in the down state too. */
-		for (grp = p802_1Q_vlan_list; grp != NULL; grp = grp->next) {
-			int flgs;
-
-			for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
-				vlandev = grp->vlan_devices[i];
-				if (!vlandev ||
-				    (VLAN_DEV_INFO(vlandev)->real_dev != dev) ||
-				    (vlandev->flags & IFF_UP))
-					continue;
+		/* Put all VLANs for this dev in the up state too.  */
+		for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
+			vlandev = grp->vlan_devices[i];
+			if (!vlandev)
+				continue;
 				
-				flgs = vlandev->flags;
-				flgs |= IFF_UP;
-				dev_change_flags(vlandev, flgs);
-			}
+			flgs = vlandev->flags;
+			if (flgs & IFF_UP)
+				continue;
+
+			dev_change_flags(vlandev, flgs | IFF_UP);
 		}
 		break;
 		
 	case NETDEV_UNREGISTER:
-		/* TODO:  Please review this code. */
-		/* delete all related VLANs. */
-		for (grp = p802_1Q_vlan_list; grp != NULL; grp = grp->next) {
-			for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
-				vlandev = grp->vlan_devices[i];
-				if (!vlandev ||
-				    (VLAN_DEV_INFO(vlandev)->real_dev != dev))
-					continue;
-
-				unregister_802_1Q_vlan_dev(
-					VLAN_DEV_INFO(vlandev)->real_dev->ifindex,
-					VLAN_DEV_INFO(vlandev)->vlan_id,
-					0, 0);
-				vlandev = NULL;
-			}
+		/* Delete all VLANs for this dev. */
+		for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
+			int ret;
+
+			vlandev = grp->vlan_devices[i];
+			if (!vlandev)
+				continue;
+
+			ret = unregister_vlan_dev(dev,
+						  VLAN_DEV_INFO(vlandev)->vlan_id);
+
+			unregister_netdev(vlandev);
+
+			/* Group was destroyed? */
+			if (ret == 1)
+				break;
 		}
 		break;
 	};
 
+out:
 	return NOTIFY_DONE;
 }
 
@@ -612,7 +712,7 @@
 		 * talk to:  args.dev1	 We also have the
 		 * VLAN ID:  args.u.VID
 		 */
-		if (register_802_1Q_vlan_device(args.device1, args.u.VID)) {
+		if (register_vlan_device(args.device1, args.u.VID)) {
 			err = 0;
 		} else {
 			err = -EINVAL;
@@ -623,7 +723,7 @@
 		/* Here, the args.dev1 is the actual VLAN we want
 		 * to get rid of.
 		 */
-		err = unregister_802_1Q_vlan_device(args.device1);
+		err = unregister_vlan_device(args.device1);
 		break;
 
 	default:
@@ -636,4 +736,4 @@
 	return err;
 }
 
-
+MODULE_LICENSE("GPL");
diff -Nru a/net/8021q/vlan.h b/net/8021q/vlan.h
--- a/net/8021q/vlan.h	Fri Mar 15 17:51:01 2002
+++ b/net/8021q/vlan.h	Fri Mar 15 17:51:01 2002
@@ -30,14 +30,48 @@
 
 extern unsigned short vlan_name_type;
 
-/* Counter for how many NON-VLAN protos we've received on a VLAN. */
-extern unsigned long vlan_bad_proto_recvd;
-
 int vlan_ioctl_handler(unsigned long arg);
 
-/* Add some headers for the public VLAN methods. */
-int unregister_802_1Q_vlan_device(const char* vlan_IF_name);
-struct net_device *register_802_1Q_vlan_device(const char* eth_IF_name,
-                                               unsigned short VID);
+#define VLAN_GRP_HASH_SHIFT	5
+#define VLAN_GRP_HASH_SIZE	(1 << VLAN_GRP_HASH_SHIFT)
+#define VLAN_GRP_HASH_MASK	(VLAN_GRP_HASH_SIZE - 1)
+extern struct vlan_group *vlan_group_hash[VLAN_GRP_HASH_SIZE];
+extern spinlock_t vlan_group_lock;
+
+/*  Find a VLAN device by the MAC address of it's Ethernet device, and
+ *  it's VLAN ID.  The default configuration is to have VLAN's scope
+ *  to be box-wide, so the MAC will be ignored.  The mac will only be
+ *  looked at if we are configured to have a seperate set of VLANs per
+ *  each MAC addressable interface.  Note that this latter option does
+ *  NOT follow the spec for VLANs, but may be useful for doing very
+ *  large quantities of VLAN MUX/DEMUX onto FrameRelay or ATM PVCs.
+ *
+ *  Must be invoked with vlan_group_lock held and that lock MUST NOT
+ *  be dropped until a reference is obtained on the returned device.
+ *  You may drop the lock earlier if you are running under the RTNL
+ *  semaphore, however.
+ */
+struct net_device *__find_vlan_dev(struct net_device* real_dev,
+				   unsigned short VID); /* vlan.c */
+
+/* found in vlan_dev.c */
+int vlan_dev_rebuild_header(struct sk_buff *skb);
+int vlan_skb_recv(struct sk_buff *skb, struct net_device *dev,
+                  struct packet_type* ptype);
+int vlan_dev_hard_header(struct sk_buff *skb, struct net_device *dev,
+                         unsigned short type, void *daddr, void *saddr,
+                         unsigned len);
+int vlan_dev_hard_start_xmit(struct sk_buff *skb, struct net_device *dev);
+int vlan_dev_hwaccel_hard_start_xmit(struct sk_buff *skb, struct net_device *dev);
+int vlan_dev_change_mtu(struct net_device *dev, int new_mtu);
+int vlan_dev_set_mac_address(struct net_device *dev, void* addr);
+int vlan_dev_open(struct net_device* dev);
+int vlan_dev_stop(struct net_device* dev);
+int vlan_dev_init(struct net_device* dev);
+void vlan_dev_destruct(struct net_device* dev);
+int vlan_dev_set_ingress_priority(char* dev_name, __u32 skb_prio, short vlan_prio);
+int vlan_dev_set_egress_priority(char* dev_name, __u32 skb_prio, short vlan_prio);
+int vlan_dev_set_vlan_flag(char* dev_name, __u32 flag, short flag_val);
+void vlan_dev_set_multicast_list(struct net_device *vlan_dev);
 
 #endif /* !(__BEN_VLAN_802_1Q_INC__) */
diff -Nru a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c
--- a/net/8021q/vlan_dev.c	Fri Mar 15 17:51:03 2002
+++ b/net/8021q/vlan_dev.c	Fri Mar 15 17:51:03 2002
@@ -38,12 +38,6 @@
 #include <linux/if_vlan.h>
 #include <net/ip.h>
 
-struct net_device_stats *vlan_dev_get_stats(struct net_device *dev)
-{
-	return &(((struct vlan_dev_info *)(dev->priv))->dev_stats);
-}
-
-
 /*
  *	Rebuild the Ethernet MAC header. This is called after an ARP
  *	(or in future other address resolution) has completed on this
@@ -78,6 +72,21 @@
 	return 0;
 }
 
+static inline struct sk_buff *vlan_check_reorder_header(struct sk_buff *skb)
+{
+	if (VLAN_DEV_INFO(skb->dev)->flags & 1) {
+		skb = skb_share_check(skb, GFP_ATOMIC);
+		if (skb) {
+			/* Lifted from Gleb's VLAN code... */
+			memmove(skb->data - ETH_HLEN,
+				skb->data - VLAN_ETH_HLEN, 12);
+			skb->mac.raw += VLAN_HLEN;
+		}
+	}
+
+	return skb;
+}
+
 /*
  *	Determine the packet's protocol ID. The rule here is that we 
  *	assume 802.3 if the type field is short enough to be a length.
@@ -113,7 +122,7 @@
 	/* vlan_TCI = ntohs(get_unaligned(&vhdr->h_vlan_TCI)); */
 	vlan_TCI = ntohs(vhdr->h_vlan_TCI);
 
-	vid = (vlan_TCI & 0xFFF);
+	vid = (vlan_TCI & VLAN_VID_MASK);
 
 #ifdef VLAN_DEBUG
 	printk(VLAN_DBG __FUNCTION__ ": skb: %p vlan_id: %hx\n",
@@ -124,11 +133,18 @@
 	 * and then go on as usual.
 	 */
 
-	/* we have 12 bits of vlan ID. */
-	/* If it's NULL, we will tag it to be junked below */
-	skb->dev = find_802_1Q_vlan_dev(dev, vid);
+	/* We have 12 bits of vlan ID.
+	 *
+	 * We must not drop the vlan_group_lock until we hold a
+	 * reference to the device (netif_rx does that) or we
+	 * fail.
+	 */
 
+	spin_lock_bh(&vlan_group_lock);
+	skb->dev = __find_vlan_dev(dev, vid);
 	if (!skb->dev) {
+		spin_unlock_bh(&vlan_group_lock);
+
 #ifdef VLAN_DEBUG
 		printk(VLAN_DBG __FUNCTION__ ": ERROR:	No net_device for VID: %i on dev: %s [%i]\n",
 		       (unsigned int)(vid), dev->name, dev->ifindex);
@@ -137,6 +153,8 @@
 		return -1;
 	}
 
+	skb->dev->last_rx = jiffies;
+
 	/* Bump the rx counters for the VLAN device. */
 	stats = vlan_dev_get_stats(skb->dev);
 	stats->rx_packets++;
@@ -149,6 +167,8 @@
 	 */
 
 	if (dev != VLAN_DEV_INFO(skb->dev)->real_dev) {
+		spin_unlock_bh(&vlan_group_lock);
+
 #ifdef VLAN_DEBUG
 		printk(VLAN_DBG __FUNCTION__ ": dropping skb: %p because came in on wrong device, dev: %s  real_dev: %s, skb_dev: %s\n",
 		       skb, dev->name, VLAN_DEV_INFO(skb->dev)->real_dev->name, skb->dev->name);
@@ -161,7 +181,7 @@
 	/*
 	 * Deal with ingress priority mapping.
 	 */
-	skb->priority = VLAN_DEV_INFO(skb->dev)->ingress_priority_map[(ntohs(vhdr->h_vlan_TCI) >> 13) & 0x7];
+	skb->priority = vlan_get_ingress_priority(skb->dev, ntohs(vhdr->h_vlan_TCI));
 
 #ifdef VLAN_DEBUG
 	printk(VLAN_DBG __FUNCTION__ ": priority: %lu  for TCI: %hu (hbo)\n",
@@ -174,9 +194,12 @@
 	switch (skb->pkt_type) {
 	case PACKET_BROADCAST: /* Yeah, stats collect these together.. */
 		// stats->broadcast ++; // no such counter :-(
+		break;
+
 	case PACKET_MULTICAST:
 		stats->multicast++;
 		break;
+
 	case PACKET_OTHERHOST: 
 		/* Our lower layer thinks this is not local, let's make sure.
 		 * This allows the VLAN to have a different MAC than the underlying
@@ -215,6 +238,7 @@
 			/* TODO:  Add a more specific counter here. */
 			stats->rx_errors++;
 		}
+		spin_unlock_bh(&vlan_group_lock);
 		return 0;
 	}
 
@@ -243,6 +267,7 @@
 			/* TODO:  Add a more specific counter here. */
 			stats->rx_errors++;
 		}
+		spin_unlock_bh(&vlan_group_lock);
 		return 0;
 	}
 
@@ -265,6 +290,24 @@
 		/* TODO:  Add a more specific counter here. */
 		stats->rx_errors++;
 	}
+	spin_unlock_bh(&vlan_group_lock);
+	return 0;
+}
+
+static inline unsigned short vlan_dev_get_egress_qos_mask(struct net_device* dev,
+							  struct sk_buff* skb)
+{
+	struct vlan_priority_tci_mapping *mp =
+		VLAN_DEV_INFO(dev)->egress_priority_map[(skb->priority & 0xF)];
+
+	while (mp) {
+		if (mp->priority == skb->priority) {
+			return mp->vlan_qos; /* This should already be shifted to mask
+					      * correctly with the VLAN's TCI
+					      */
+		}
+		mp = mp->next;
+	}
 	return 0;
 }
 
@@ -396,8 +439,9 @@
 	 */
 
 	if (veth->h_vlan_proto != __constant_htons(ETH_P_8021Q)) {
+		unsigned short veth_TCI;
+
 		/* This is not a VLAN frame...but we can fix that! */
-		unsigned short veth_TCI = 0;
 		VLAN_DEV_INFO(dev)->cnt_encap_on_xmit++;
 
 #ifdef VLAN_DEBUG
@@ -453,65 +497,44 @@
 	       veth->h_vlan_proto, veth->h_vlan_TCI, veth->h_vlan_encapsulated_proto);
 #endif
 
-	dev_queue_xmit(skb);
 	stats->tx_packets++; /* for statics only */
 	stats->tx_bytes += skb->len;
-	return 0;
-}
 
-int vlan_dev_change_mtu(struct net_device *dev, int new_mtu)
-{
-	/* TODO: gotta make sure the underlying layer can handle it,
-	 * maybe an IFF_VLAN_CAPABLE flag for devices?
-	 */
-	if (VLAN_DEV_INFO(dev)->real_dev->mtu < new_mtu)
-		return -ERANGE;
-
-	dev->mtu = new_mtu;
+	dev_queue_xmit(skb);
 
-	return new_mtu;
+	return 0;
 }
 
-int vlan_dev_open(struct net_device *dev)
+int vlan_dev_hwaccel_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
-	if (!(VLAN_DEV_INFO(dev)->real_dev->flags & IFF_UP))
-		return -ENETDOWN;
+	struct net_device_stats *stats = vlan_dev_get_stats(dev);
+	struct vlan_skb_tx_cookie *cookie;
 
-	return 0;
-}
+	stats->tx_packets++;
+	stats->tx_bytes += skb->len;
 
-int vlan_dev_stop(struct net_device *dev)
-{
-	vlan_flush_mc_list(dev);
-	return 0;
-}
+	skb->dev = VLAN_DEV_INFO(dev)->real_dev;
+	cookie = VLAN_TX_SKB_CB(skb);
+	cookie->magic = VLAN_TX_COOKIE_MAGIC;
+	cookie->vlan_tag = (VLAN_DEV_INFO(dev)->vlan_id |
+			    vlan_dev_get_egress_qos_mask(dev, skb));
+
+	dev_queue_xmit(skb);
 
-int vlan_dev_init(struct net_device *dev)
-{
-	/* TODO:  figure this out, maybe do nothing?? */
 	return 0;
 }
 
-void vlan_dev_destruct(struct net_device *dev)
+int vlan_dev_change_mtu(struct net_device *dev, int new_mtu)
 {
-	if (dev) {
-		vlan_flush_mc_list(dev);
-		if (dev->priv) {
-			dev_put(VLAN_DEV_INFO(dev)->real_dev);
-			if (VLAN_DEV_INFO(dev)->dent) {
-				printk(KERN_ERR __FUNCTION__ ": dent is NOT NULL!\n");
-
-				/* If we ever get here, there is a serious bug
-				 * that must be fixed.
-				 */
-			}
+	/* TODO: gotta make sure the underlying layer can handle it,
+	 * maybe an IFF_VLAN_CAPABLE flag for devices?
+	 */
+	if (VLAN_DEV_INFO(dev)->real_dev->mtu < new_mtu)
+		return -ERANGE;
 
-			kfree(dev->priv);
+	dev->mtu = new_mtu;
 
-			VLAN_FMEM_DBG("dev->priv free, addr: %p\n", dev->priv);
-			dev->priv = NULL;
-		}
-	}
+	return new_mtu;
 }
 
 int vlan_dev_set_ingress_priority(char *dev_name, __u32 skb_prio, short vlan_prio)
@@ -642,6 +665,124 @@
 	return 0;
 }
 
+static inline int vlan_dmi_equals(struct dev_mc_list *dmi1,
+                                  struct dev_mc_list *dmi2)
+{
+	return ((dmi1->dmi_addrlen == dmi2->dmi_addrlen) &&
+		(memcmp(dmi1->dmi_addr, dmi2->dmi_addr, dmi1->dmi_addrlen) == 0));
+}
+
+/** dmi is a single entry into a dev_mc_list, a single node.  mc_list is
+ *  an entire list, and we'll iterate through it.
+ */
+static int vlan_should_add_mc(struct dev_mc_list *dmi, struct dev_mc_list *mc_list)
+{
+	struct dev_mc_list *idmi;
+
+	for (idmi = mc_list; idmi != NULL; ) {
+		if (vlan_dmi_equals(dmi, idmi)) {
+			if (dmi->dmi_users > idmi->dmi_users)
+				return 1;
+			else
+				return 0;
+		} else {
+			idmi = idmi->next;
+		}
+	}
+
+	return 1;
+}
+
+static inline void vlan_destroy_mc_list(struct dev_mc_list *mc_list)
+{
+	struct dev_mc_list *dmi = mc_list;
+	struct dev_mc_list *next;
+
+	while(dmi) {
+		next = dmi->next;
+		kfree(dmi);
+		dmi = next;
+	}
+}
+
+static void vlan_copy_mc_list(struct dev_mc_list *mc_list, struct vlan_dev_info *vlan_info)
+{
+	struct dev_mc_list *dmi, *new_dmi;
+
+	vlan_destroy_mc_list(vlan_info->old_mc_list);
+	vlan_info->old_mc_list = NULL;
+
+	for (dmi = mc_list; dmi != NULL; dmi = dmi->next) {
+		new_dmi = kmalloc(sizeof(*new_dmi), GFP_ATOMIC);
+		if (new_dmi == NULL) {
+			printk(KERN_ERR "vlan: cannot allocate memory. "
+			       "Multicast may not work properly from now.\n");
+			return;
+		}
+
+		/* Copy whole structure, then make new 'next' pointer */
+		*new_dmi = *dmi;
+		new_dmi->next = vlan_info->old_mc_list;
+		vlan_info->old_mc_list = new_dmi;
+	}
+}
+
+static void vlan_flush_mc_list(struct net_device *dev)
+{
+	struct dev_mc_list *dmi = dev->mc_list;
+
+	while (dmi) {
+		dev_mc_delete(dev, dmi->dmi_addr, dmi->dmi_addrlen, 0);
+		printk(KERN_INFO "%s: del %.2x:%.2x:%.2x:%.2x:%.2x:%.2x mcast address from vlan interface\n",
+		       dev->name,
+		       dmi->dmi_addr[0],
+		       dmi->dmi_addr[1],
+		       dmi->dmi_addr[2],
+		       dmi->dmi_addr[3],
+		       dmi->dmi_addr[4],
+		       dmi->dmi_addr[5]);
+		dmi = dev->mc_list;
+	}
+
+	/* dev->mc_list is NULL by the time we get here. */
+	vlan_destroy_mc_list(VLAN_DEV_INFO(dev)->old_mc_list);
+	VLAN_DEV_INFO(dev)->old_mc_list = NULL;
+}
+
+int vlan_dev_open(struct net_device *dev)
+{
+	if (!(VLAN_DEV_INFO(dev)->real_dev->flags & IFF_UP))
+		return -ENETDOWN;
+
+	return 0;
+}
+
+int vlan_dev_stop(struct net_device *dev)
+{
+	vlan_flush_mc_list(dev);
+	return 0;
+}
+
+int vlan_dev_init(struct net_device *dev)
+{
+	/* TODO:  figure this out, maybe do nothing?? */
+	return 0;
+}
+
+void vlan_dev_destruct(struct net_device *dev)
+{
+	if (dev) {
+		vlan_flush_mc_list(dev);
+		if (dev->priv) {
+			if (VLAN_DEV_INFO(dev)->dent)
+				BUG();
+
+			kfree(dev->priv);
+			dev->priv = NULL;
+		}
+	}
+}
+
 /** Taken from Gleb + Lennert's VLAN code, and modified... */
 void vlan_dev_set_multicast_list(struct net_device *vlan_dev)
 {
@@ -706,69 +847,4 @@
 		/* save multicast list */
 		vlan_copy_mc_list(vlan_dev->mc_list, VLAN_DEV_INFO(vlan_dev));
 	}
-}
-
-/** dmi is a single entry into a dev_mc_list, a single node.  mc_list is
- *  an entire list, and we'll iterate through it.
- */
-int vlan_should_add_mc(struct dev_mc_list *dmi, struct dev_mc_list *mc_list)
-{
-	struct dev_mc_list *idmi;
-
-	for (idmi = mc_list; idmi != NULL; ) {
-		if (vlan_dmi_equals(dmi, idmi)) {
-			if (dmi->dmi_users > idmi->dmi_users)
-				return 1;
-			else
-				return 0;
-		} else {
-			idmi = idmi->next;
-		}
-	}
-
-	return 1;
-}
-
-void vlan_copy_mc_list(struct dev_mc_list *mc_list, struct vlan_dev_info *vlan_info)
-{
-	struct dev_mc_list *dmi, *new_dmi;
-
-	vlan_destroy_mc_list(vlan_info->old_mc_list);
-	vlan_info->old_mc_list = NULL;
-
-	for (dmi = mc_list; dmi != NULL; dmi = dmi->next) {
-		new_dmi = kmalloc(sizeof(*new_dmi), GFP_ATOMIC);
-		if (new_dmi == NULL) {
-			printk(KERN_ERR "vlan: cannot allocate memory. "
-			       "Multicast may not work properly from now.\n");
-			return;
-		}
-
-		/* Copy whole structure, then make new 'next' pointer */
-		*new_dmi = *dmi;
-		new_dmi->next = vlan_info->old_mc_list;
-		vlan_info->old_mc_list = new_dmi;
-	}
-}
-
-void vlan_flush_mc_list(struct net_device *dev)
-{
-	struct dev_mc_list *dmi = dev->mc_list;
-
-	while (dmi) {
-		dev_mc_delete(dev, dmi->dmi_addr, dmi->dmi_addrlen, 0);
-		printk(KERN_INFO "%s: del %.2x:%.2x:%.2x:%.2x:%.2x:%.2x mcast address from vlan interface\n",
-		       dev->name,
-		       dmi->dmi_addr[0],
-		       dmi->dmi_addr[1],
-		       dmi->dmi_addr[2],
-		       dmi->dmi_addr[3],
-		       dmi->dmi_addr[4],
-		       dmi->dmi_addr[5]);
-		dmi = dev->mc_list;
-	}
-
-	/* dev->mc_list is NULL by the time we get here. */
-	vlan_destroy_mc_list(VLAN_DEV_INFO(dev)->old_mc_list);
-	VLAN_DEV_INFO(dev)->old_mc_list = NULL;
 }
diff -Nru a/net/8021q/vlanproc.c b/net/8021q/vlanproc.c
--- a/net/8021q/vlanproc.c	Fri Mar 15 17:51:02 2002
+++ b/net/8021q/vlanproc.c	Fri Mar 15 17:51:02 2002
@@ -272,7 +272,7 @@
 {
 	struct net_device *vlandev = NULL;
 	struct vlan_group *grp = NULL;
-	int i = 0;
+	int h, i;
 	char *nm_type = NULL;
 	struct vlan_dev_info *dev_info = NULL;
 
@@ -292,46 +292,34 @@
 		nm_type = "UNKNOWN";
 	}
 
-	cnt += sprintf(buf + cnt, "Name-Type: %s  bad_proto_recvd: %lu\n",
-		       nm_type, vlan_bad_proto_recvd);
+	cnt += sprintf(buf + cnt, "Name-Type: %s\n", nm_type);
 
-	for (grp = p802_1Q_vlan_list; grp != NULL; grp = grp->next) {
-		/* loop through all devices for this device */
-#ifdef VLAN_DEBUG
-		printk(VLAN_DBG __FUNCTION__ ": found a group, addr: %p\n",grp);
-#endif
-		for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
-			vlandev = grp->vlan_devices[i];
-			if (!vlandev)
-				continue;
-#ifdef VLAN_DEBUG
-			printk(VLAN_DBG __FUNCTION__
-			       ": found a vlan_dev, addr: %p\n", vlandev);
-#endif
-			if ((cnt + 100) > VLAN_PROC_BUFSZ) {
-				if ((cnt+strlen(term_msg)) < VLAN_PROC_BUFSZ)
-					cnt += sprintf(buf+cnt, "%s", term_msg);
-
-				return cnt;
-			}
-			if (!vlandev->priv) {
-				printk(KERN_ERR __FUNCTION__
-				       ": ERROR: vlandev->priv is NULL\n");
-				continue;
+	spin_lock_bh(&vlan_group_lock);
+	for (h = 0; h < VLAN_GRP_HASH_SIZE; h++) {
+		for (grp = vlan_group_hash[h]; grp != NULL; grp = grp->next) {
+			for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
+				vlandev = grp->vlan_devices[i];
+				if (!vlandev)
+					continue;
+
+				if ((cnt + 100) > VLAN_PROC_BUFSZ) {
+					if ((cnt+strlen(term_msg)) < VLAN_PROC_BUFSZ)
+						cnt += sprintf(buf+cnt, "%s", term_msg);
+
+					goto out;
+				}
+
+				dev_info = VLAN_DEV_INFO(vlandev);
+				cnt += sprintf(buf + cnt, "%-15s| %d  | %s\n",
+					       vlandev->name,
+					       dev_info->vlan_id,
+					       dev_info->real_dev->name);
 			}
-
-			dev_info = VLAN_DEV_INFO(vlandev);
-
-#ifdef VLAN_DEBUG
-			printk(VLAN_DBG __FUNCTION__
-			       ": got a good vlandev, addr: %p\n",
-			       VLAN_DEV_INFO(vlandev));
-#endif
-			cnt += sprintf(buf + cnt, "%-15s| %d  | %s\n",
-				       vlandev->name, dev_info->vlan_id,
-				       dev_info->real_dev->name);
 		}
 	}
+out:
+	spin_unlock_bh(&vlan_group_lock);
+
 	return cnt;
 }
 
@@ -365,11 +353,7 @@
 	int cnt = 0;
 	int i;
 
-#ifdef VLAN_DEBUG
-	printk(VLAN_DBG __FUNCTION__ ": vlandev: %p\n", vlandev);
-#endif
-
-	if ((vlandev == NULL) || (!vlandev->priv_flags & IFF_802_1Q_VLAN))
+	if ((vlandev == NULL) || (!(vlandev->priv_flags & IFF_802_1Q_VLAN)))
 		return 0;
 
 	dev_info = VLAN_DEV_INFO(vlandev);
@@ -426,7 +410,7 @@
 
 	cnt += sprintf(buf + cnt, "EGRESSS priority Mappings: ");
 
-	for (i = 0; i<16; i++) {
+	for (i = 0; i < 16; i++) {
 		mp = dev_info->egress_priority_map[i];
 		while (mp) {
 			cnt += sprintf(buf + cnt, "%lu:%hu ",
diff -Nru a/net/Config.in b/net/Config.in
--- a/net/Config.in	Fri Mar 15 17:51:02 2002
+++ b/net/Config.in	Fri Mar 15 17:51:02 2002
@@ -44,10 +44,8 @@
 	 tristate '    Multi-Protocol Over ATM (MPOA) support' CONFIG_ATM_MPOA
       fi
    fi
-
-   dep_tristate '802.1Q VLAN Support (EXPERIMENTAL)' CONFIG_VLAN_8021Q $CONFIG_EXPERIMENTAL
-
 fi
+tristate '802.1Q VLAN Support' CONFIG_VLAN_8021Q
 
 comment ' '
 tristate 'The IPX protocol' CONFIG_IPX
diff -Nru a/net/core/dev.c b/net/core/dev.c
--- a/net/core/dev.c	Fri Mar 15 17:51:03 2002
+++ b/net/core/dev.c	Fri Mar 15 17:51:03 2002
@@ -798,6 +798,19 @@
 
 	clear_bit(__LINK_STATE_START, &dev->state);
 
+	/* Synchronize to scheduled poll. We cannot touch poll list,
+	 * it can be even on different cpu. So just clear netif_running(),
+	 * and wait when poll really will happen. Actually, the best place
+	 * for this is inside dev->stop() after device stopped its irq
+	 * engine, but this requires more changes in devices. */
+
+	smp_mb__after_clear_bit(); /* Commit netif_running(). */
+	while (test_bit(__LINK_STATE_RX_SCHED, &dev->state)) {
+		/* No hurry. */
+		current->state = TASK_INTERRUPTIBLE;
+		schedule_timeout(1);
+	}
+
 	/*
 	 *	Call the device specific close. This cannot fail.
 	 *	Only if device is UP
@@ -1072,6 +1085,7 @@
   =======================================================================*/
 
 int netdev_max_backlog = 300;
+int weight_p = 64;            /* old backlog weight */
 /* These numbers are selected based on intuition and some
  * experimentatiom, if you have more scientific way of doing this
  * please go ahead and fix things.
@@ -1237,13 +1251,11 @@
 enqueue:
 			dev_hold(skb->dev);
 			__skb_queue_tail(&queue->input_pkt_queue,skb);
-			/* Runs from irqs or BH's, no need to wake BH */
-			cpu_raise_softirq(this_cpu, NET_RX_SOFTIRQ);
 			local_irq_restore(flags);
 #ifndef OFFLINE_SAMPLE
 			get_sample_stats(this_cpu);
 #endif
-			return softnet_data[this_cpu].cng_level;
+			return queue->cng_level;
 		}
 
 		if (queue->throttle) {
@@ -1253,6 +1265,8 @@
 				netdev_wakeup();
 #endif
 		}
+
+		netif_rx_schedule(&queue->backlog_dev);
 		goto enqueue;
 	}
 
@@ -1308,19 +1322,12 @@
 	return ret;
 }
 
-/* Reparent skb to master device. This function is called
- * only from net_rx_action under BR_NETPROTO_LOCK. It is misuse
- * of BR_NETPROTO_LOCK, but it is OK for now.
- */
 static __inline__ void skb_bond(struct sk_buff *skb)
 {
 	struct net_device *dev = skb->dev;
-	
-	if (dev->master) {
-		dev_hold(dev->master);
+
+	if (dev->master)
 		skb->dev = dev->master;
-		dev_put(dev);
-	}
 }
 
 static void net_tx_action(struct softirq_action *h)
@@ -1416,121 +1423,138 @@
 }
 #endif   /* CONFIG_NET_DIVERT */
 
-
-static void net_rx_action(struct softirq_action *h)
+int netif_receive_skb(struct sk_buff *skb)
 {
-	int this_cpu = smp_processor_id();
-	struct softnet_data *queue = &softnet_data[this_cpu];
-	unsigned long start_time = jiffies;
-	int bugdet = netdev_max_backlog;
-
-	br_read_lock(BR_NETPROTO_LOCK);
-
-	for (;;) {
-		struct sk_buff *skb;
-		struct net_device *rx_dev;
-
-		local_irq_disable();
-		skb = __skb_dequeue(&queue->input_pkt_queue);
-		local_irq_enable();
+	struct packet_type *ptype, *pt_prev;
+	int ret = NET_RX_DROP;
+	unsigned short type = skb->protocol;
 
-		if (skb == NULL)
-			break;
+	if (skb->stamp.tv_sec == 0)
+		do_gettimeofday(&skb->stamp);
 
-		skb_bond(skb);
+	skb_bond(skb);
 
-		rx_dev = skb->dev;
+	netdev_rx_stat[smp_processor_id()].total++;
 
 #ifdef CONFIG_NET_FASTROUTE
-		if (skb->pkt_type == PACKET_FASTROUTE) {
-			netdev_rx_stat[this_cpu].fastroute_deferred_out++;
-			dev_queue_xmit(skb);
-			dev_put(rx_dev);
-			continue;
-		}
+	if (skb->pkt_type == PACKET_FASTROUTE) {
+		netdev_rx_stat[smp_processor_id()].fastroute_deferred_out++;
+		return dev_queue_xmit(skb);
+	}
 #endif
-		skb->h.raw = skb->nh.raw = skb->data;
-		{
-			struct packet_type *ptype, *pt_prev;
-			unsigned short type = skb->protocol;
 
-			pt_prev = NULL;
-			for (ptype = ptype_all; ptype; ptype = ptype->next) {
-				if (!ptype->dev || ptype->dev == skb->dev) {
-					if (pt_prev) {
-						if (!pt_prev->data) {
-							deliver_to_old_ones(pt_prev, skb, 0);
-						} else {
-							atomic_inc(&skb->users);
-							pt_prev->func(skb,
-								      skb->dev,
-								      pt_prev);
-						}
-					}
-					pt_prev = ptype;
+	skb->h.raw = skb->nh.raw = skb->data;
+
+	pt_prev = NULL;
+	for (ptype = ptype_all; ptype; ptype = ptype->next) {
+		if (!ptype->dev || ptype->dev == skb->dev) {
+			if (pt_prev) {
+				if (!pt_prev->data) {
+					ret = deliver_to_old_ones(pt_prev, skb, 0);
+				} else {
+					atomic_inc(&skb->users);
+					ret = pt_prev->func(skb, skb->dev, pt_prev);
 				}
 			}
+			pt_prev = ptype;
+		}
+	}
 
 #ifdef CONFIG_NET_DIVERT
-			if (skb->dev->divert && skb->dev->divert->divert)
-				handle_diverter(skb);
+	if (skb->dev->divert && skb->dev->divert->divert)
+		ret = handle_diverter(skb);
 #endif /* CONFIG_NET_DIVERT */
-
 			
 #if defined(CONFIG_BRIDGE) || defined(CONFIG_BRIDGE_MODULE)
-			if (skb->dev->br_port != NULL &&
-			    br_handle_frame_hook != NULL) {
-				handle_bridge(skb, pt_prev);
-				dev_put(rx_dev);
-				continue;
-			}
+	if (skb->dev->br_port != NULL &&
+	    br_handle_frame_hook != NULL) {
+		return handle_bridge(skb, pt_prev);
+	}
 #endif
 
-			for (ptype=ptype_base[ntohs(type)&15];ptype;ptype=ptype->next) {
-				if (ptype->type == type &&
-				    (!ptype->dev || ptype->dev == skb->dev)) {
-					if (pt_prev) {
-						if (!pt_prev->data)
-							deliver_to_old_ones(pt_prev, skb, 0);
-						else {
-							atomic_inc(&skb->users);
-							pt_prev->func(skb,
-								      skb->dev,
-								      pt_prev);
-						}
-					}
-					pt_prev = ptype;
+	for (ptype=ptype_base[ntohs(type)&15];ptype;ptype=ptype->next) {
+		if (ptype->type == type &&
+		    (!ptype->dev || ptype->dev == skb->dev)) {
+			if (pt_prev) {
+				if (!pt_prev->data) {
+					ret = deliver_to_old_ones(pt_prev, skb, 0);
+				} else {
+					atomic_inc(&skb->users);
+					ret = pt_prev->func(skb, skb->dev, pt_prev);
 				}
 			}
+			pt_prev = ptype;
+		}
+	}
 
-			if (pt_prev) {
-				if (!pt_prev->data)
-					deliver_to_old_ones(pt_prev, skb, 1);
-				else
-					pt_prev->func(skb, skb->dev, pt_prev);
-			} else
-				kfree_skb(skb);
+	if (pt_prev) {
+		if (!pt_prev->data) {
+			ret = deliver_to_old_ones(pt_prev, skb, 1);
+		} else {
+			ret = pt_prev->func(skb, skb->dev, pt_prev);
 		}
+	} else {
+		kfree_skb(skb);
+		/* Jamal, now you will not able to escape explaining
+		 * me how you were going to use this. :-)
+		 */
+		ret = NET_RX_DROP;
+	}
 
-		dev_put(rx_dev);
+	return ret;
+}
 
-		if (bugdet-- < 0 || jiffies - start_time > 1)
-			goto softnet_break;
+static int process_backlog(struct net_device *backlog_dev, int *budget)
+{
+	int work = 0;
+	int quota = min(backlog_dev->quota, *budget);
+	int this_cpu = smp_processor_id();
+	struct softnet_data *queue = &softnet_data[this_cpu];
+	unsigned long start_time = jiffies;
+
+	for (;;) {
+		struct sk_buff *skb;
+		struct net_device *dev;
+
+		local_irq_disable();
+		skb = __skb_dequeue(&queue->input_pkt_queue);
+		if (skb == NULL)
+			goto job_done;
+		local_irq_enable();
+
+		dev = skb->dev;
+
+		netif_receive_skb(skb);
+
+		dev_put(dev);
+
+		work++;
+
+		if (work >= quota || jiffies - start_time > 1)
+			break;
 
 #ifdef CONFIG_NET_HW_FLOWCONTROL
-	if (queue->throttle && queue->input_pkt_queue.qlen < no_cong_thresh ) {
-		if (atomic_dec_and_test(&netdev_dropping)) {
-			queue->throttle = 0;
-			netdev_wakeup();
-			goto softnet_break;
+		if (queue->throttle && queue->input_pkt_queue.qlen < no_cong_thresh ) {
+			if (atomic_dec_and_test(&netdev_dropping)) {
+				queue->throttle = 0;
+				netdev_wakeup();
+				break;
+			}
 		}
-	}
 #endif
-
 	}
-	br_read_unlock(BR_NETPROTO_LOCK);
 
-	local_irq_disable();
+	backlog_dev->quota -= work;
+	*budget -= work;
+	return -1;
+
+job_done:
+	backlog_dev->quota -= work;
+	*budget -= work;
+
+	list_del(&backlog_dev->poll_list);
+	clear_bit(__LINK_STATE_RX_SCHED, &backlog_dev->state);
+
 	if (queue->throttle) {
 		queue->throttle = 0;
 #ifdef CONFIG_NET_HW_FLOWCONTROL
@@ -1539,21 +1563,53 @@
 #endif
 	}
 	local_irq_enable();
+	return 0;
+}
 
-	NET_PROFILE_LEAVE(softnet_process);
-	return;
+static void net_rx_action(struct softirq_action *h)
+{
+	int this_cpu = smp_processor_id();
+	struct softnet_data *queue = &softnet_data[this_cpu];
+	unsigned long start_time = jiffies;
+	int budget = netdev_max_backlog;
 
-softnet_break:
+	br_read_lock(BR_NETPROTO_LOCK);
+	local_irq_disable();
+
+	while (!list_empty(&queue->poll_list)) {
+		struct net_device *dev;
+
+		if (budget <= 0 || jiffies - start_time > 1)
+			goto softnet_break;
+
+		local_irq_enable();
+
+		dev = list_entry(queue->poll_list.next, struct net_device, poll_list);
+
+		if (dev->quota <= 0 || dev->poll(dev, &budget)) {
+			local_irq_disable();
+			list_del(&dev->poll_list);
+			list_add_tail(&dev->poll_list, &queue->poll_list);
+			if (dev->quota < 0)
+				dev->quota += dev->weight;
+			else
+				dev->quota = dev->weight;
+		} else {
+			dev_put(dev);
+			local_irq_disable();
+		}
+	}
+
+	local_irq_enable();
 	br_read_unlock(BR_NETPROTO_LOCK);
+	return;
 
-	local_irq_disable();
+softnet_break:
 	netdev_rx_stat[this_cpu].time_squeeze++;
-	/* This already runs in BH context, no need to wake up BH's */
-	cpu_raise_softirq(this_cpu, NET_RX_SOFTIRQ);
-	local_irq_enable();
+	__cpu_raise_softirq(this_cpu, NET_RX_SOFTIRQ);
 
-	NET_PROFILE_LEAVE(softnet_process);
-	return;
+	local_irq_enable();
+	br_read_unlock(BR_NETPROTO_LOCK);
 }
 
 static gifconf_func_t * gifconf_list [NPROTO];
@@ -2626,6 +2682,7 @@
 	if (!dev_boot_phase)
 		return 0;
 
+
 #ifdef CONFIG_NET_DIVERT
 	dv_init();
 #endif /* CONFIG_NET_DIVERT */
@@ -2643,8 +2700,13 @@
 		queue->cng_level = 0;
 		queue->avg_blog = 10; /* arbitrary non-zero */
 		queue->completion_queue = NULL;
+		INIT_LIST_HEAD(&queue->poll_list);
+		set_bit(__LINK_STATE_START, &queue->backlog_dev.state);
+		queue->backlog_dev.weight = weight_p;
+		queue->backlog_dev.poll = process_backlog;
+		atomic_set(&queue->backlog_dev.refcnt, 1);
 	}
-	
+
 #ifdef CONFIG_NET_PROFILE
 	net_profile_init();
 	NET_PROFILE_REGISTER(dev_queue_xmit);
@@ -2744,7 +2806,6 @@
 #ifdef CONFIG_NET_SCHED
 	pktsched_init();
 #endif
-
 	/*
 	 *	Initialise network devices
 	 */
diff -Nru a/net/core/sysctl_net_core.c b/net/core/sysctl_net_core.c
--- a/net/core/sysctl_net_core.c	Fri Mar 15 17:51:02 2002
+++ b/net/core/sysctl_net_core.c	Fri Mar 15 17:51:02 2002
@@ -12,6 +12,7 @@
 #ifdef CONFIG_SYSCTL
 
 extern int netdev_max_backlog;
+extern int weight_p;
 extern int no_cong_thresh;
 extern int no_cong;
 extern int lo_cong;
@@ -46,6 +47,9 @@
 	 &proc_dointvec},
 	{NET_CORE_RMEM_DEFAULT, "rmem_default",
 	 &sysctl_rmem_default, sizeof(int), 0644, NULL,
+	 &proc_dointvec},
+	{NET_CORE_DEV_WEIGHT, "dev_weight",
+	 &weight_p, sizeof(int), 0644, NULL,
 	 &proc_dointvec},
 	{NET_CORE_MAX_BACKLOG, "netdev_max_backlog",
 	 &netdev_max_backlog, sizeof(int), 0644, NULL,
diff -Nru a/net/core/wireless.c b/net/core/wireless.c
--- a/net/core/wireless.c	Fri Mar 15 17:51:03 2002
+++ b/net/core/wireless.c	Fri Mar 15 17:51:03 2002
@@ -2,7 +2,7 @@
  * This file implement the Wireless Extensions APIs.
  *
  * Authors :	Jean Tourrilhes - HPL - <jt@hpl.hp.com>
- * Copyright (c) 1997-2001 Jean Tourrilhes, All Rights Reserved.
+ * Copyright (c) 1997-2002 Jean Tourrilhes, All Rights Reserved.
  *
  * (As all part of the Linux kernel, this file is GPL)
  */
@@ -25,6 +25,14 @@
  *	o Added iw_handler handling ;-)
  *	o Added standard ioctl description
  *	o Initial dumb commit strategy based on orinoco.c
+ *
+ * v3 - 19.12.01 - Jean II
+ *	o Make sure we don't go out of standard_ioctl[] in ioctl_standard_call
+ *	o Fix /proc/net/wireless to handle __u8 to __s8 change in iwqual
+ *	o Add event dispatcher function
+ *	o Add event description
+ *	o Propagate events as rtnetlink IFLA_WIRELESS option
+ *	o Generate event on selected SET requests
  */
 
 /***************************** INCLUDES *****************************/
@@ -33,6 +41,7 @@
 #include <linux/config.h>		/* Not needed ??? */
 #include <linux/types.h>		/* off_t */
 #include <linux/netdevice.h>		/* struct ifreq, dev_get_by_name() */
+#include <linux/rtnetlink.h>		/* rtnetlink stuff */
 
 #include <linux/wireless.h>		/* Pretty obvious */
 #include <net/iw_handler.h>		/* New driver API */
@@ -44,14 +53,23 @@
 
 /* Debuging stuff */
 #undef WE_IOCTL_DEBUG		/* Debug IOCTL API */
+#undef WE_EVENT_DEBUG		/* Debug Event dispatcher */
+
+/* Options */
+#define WE_EVENT_NETLINK	/* Propagate events using rtnetlink */
+#define WE_SET_EVENT		/* Generate an event on some set commands */
 
 /************************* GLOBAL VARIABLES *************************/
 /*
  * You should not use global variables, because or re-entrancy.
  * On our case, it's only const, so it's OK...
  */
+/*
+ * Meta-data about all the standard Wireless Extension request we
+ * know about.
+ */
 static const struct iw_ioctl_description	standard_ioctl[] = {
-	/* SIOCSIWCOMMIT (internal) */
+	/* SIOCSIWCOMMIT */
 	{ IW_HEADER_TYPE_NULL, 0, 0, 0, 0, 0},
 	/* SIOCGIWNAME */
 	{ IW_HEADER_TYPE_CHAR, 0, 0, 0, 0, IW_DESCR_FLAG_DUMP},
@@ -99,10 +117,10 @@
 	{ IW_HEADER_TYPE_NULL, 0, 0, 0, 0, 0},
 	/* SIOCGIWAPLIST */
 	{ IW_HEADER_TYPE_POINT, 0, (sizeof(struct sockaddr) + sizeof(struct iw_quality)), 0, IW_MAX_AP, 0},
-	/* -- hole -- */
-	{ IW_HEADER_TYPE_NULL, 0, 0, 0, 0, 0},
-	/* -- hole -- */
-	{ IW_HEADER_TYPE_NULL, 0, 0, 0, 0, 0},
+	/* SIOCSIWSCAN */
+	{ IW_HEADER_TYPE_PARAM, 0, 0, 0, 0, 0},
+	/* SIOCGIWSCAN */
+	{ IW_HEADER_TYPE_POINT, 0, 1, 0, IW_SCAN_MAX_DATA, 0},
 	/* SIOCSIWESSID */
 	{ IW_HEADER_TYPE_POINT, 0, 1, 0, IW_ESSID_MAX_SIZE, IW_DESCR_FLAG_EVENT},
 	/* SIOCGIWESSID */
@@ -136,7 +154,7 @@
 	/* SIOCGIWRETRY */
 	{ IW_HEADER_TYPE_PARAM, 0, 0, 0, 0, 0},
 	/* SIOCSIWENCODE */
-	{ IW_HEADER_TYPE_POINT, 4, 1, 0, IW_ENCODING_TOKEN_MAX, IW_DESCR_FLAG_EVENT | IW_DESCR_FLAG_RESTRICT},
+	{ IW_HEADER_TYPE_POINT, 0, 1, 0, IW_ENCODING_TOKEN_MAX, IW_DESCR_FLAG_EVENT | IW_DESCR_FLAG_RESTRICT},
 	/* SIOCGIWENCODE */
 	{ IW_HEADER_TYPE_POINT, 0, 1, 0, IW_ENCODING_TOKEN_MAX, IW_DESCR_FLAG_DUMP | IW_DESCR_FLAG_RESTRICT},
 	/* SIOCSIWPOWER */
@@ -144,9 +162,38 @@
 	/* SIOCGIWPOWER */
 	{ IW_HEADER_TYPE_PARAM, 0, 0, 0, 0, 0},
 };
+static const int standard_ioctl_num = (sizeof(standard_ioctl) /
+				       sizeof(struct iw_ioctl_description));
+
+/*
+ * Meta-data about all the additional standard Wireless Extension events
+ * we know about.
+ */
+static const struct iw_ioctl_description	standard_event[] = {
+	/* IWEVTXDROP */
+	{ IW_HEADER_TYPE_ADDR, 0, 0, 0, 0, 0},
+	/* IWEVQUAL */
+	{ IW_HEADER_TYPE_QUAL, 0, 0, 0, 0, 0},
+};
+static const int standard_event_num = (sizeof(standard_event) /
+				       sizeof(struct iw_ioctl_description));
 
 /* Size (in bytes) of the various private data types */
-char priv_type_size[] = { 0, 1, 1, 0, 4, 4, 0, 0 };
+static const char priv_type_size[] = { 0, 1, 1, 0, 4, 4, 0, 0 };
+
+/* Size (in bytes) of various events */
+static const int event_type_size[] = {
+	IW_EV_LCP_LEN,
+	0,
+	IW_EV_CHAR_LEN,
+	0,
+	IW_EV_UINT_LEN,
+	IW_EV_FREQ_LEN,
+	IW_EV_POINT_LEN,		/* Without variable payload */
+	IW_EV_PARAM_LEN,
+	IW_EV_ADDR_LEN,
+	IW_EV_QUAL_LEN,
+};
 
 /************************ COMMON SUBROUTINES ************************/
 /*
@@ -162,7 +209,8 @@
 static inline iw_handler get_handler(struct net_device *dev,
 				     unsigned int cmd)
 {
-	unsigned int	index;		/* MUST be unsigned */
+	/* Don't "optimise" the following variable, it will crash */
+	unsigned int	index;		/* *MUST* be unsigned */
 
 	/* Check if we have some wireless handlers defined */
 	if(dev->wireless_handlers == NULL)
@@ -269,9 +317,9 @@
 			       stats->status,
 			       stats->qual.qual,
 			       stats->qual.updated & 1 ? '.' : ' ',
-			       stats->qual.level,
+			       ((__u8) stats->qual.level),
 			       stats->qual.updated & 2 ? '.' : ' ',
-			       stats->qual.noise,
+			       ((__u8) stats->qual.noise),
 			       stats->qual.updated & 4 ? '.' : ' ',
 			       stats->discard.nwid,
 			       stats->discard.code,
@@ -423,12 +471,14 @@
 	int					ret = -EINVAL;
 
 	/* Get the description of the IOCTL */
+	if((cmd - SIOCIWFIRST) >= standard_ioctl_num)
+		return -EOPNOTSUPP;
 	descr = &(standard_ioctl[cmd - SIOCIWFIRST]);
 
 #ifdef WE_IOCTL_DEBUG
-	printk(KERN_DEBUG "%s : Found standard handler for 0x%04X\n",
+	printk(KERN_DEBUG "%s (WE) : Found standard handler for 0x%04X\n",
 	       ifr->ifr_name, cmd);
-	printk(KERN_DEBUG "Header type : %d, token type : %d, token_size : %d, max_token : %d\n", descr->header_type, descr->token_type, descr->token_size, descr->max_tokens);
+	printk(KERN_DEBUG "%s (WE) : Header type : %d, Token type : %d, size : %d, token : %d\n", dev->name, descr->header_type, descr->token_type, descr->token_size, descr->max_tokens);
 #endif	/* WE_IOCTL_DEBUG */
 
 	/* Prepare the call */
@@ -437,8 +487,16 @@
 
 	/* Check if we have a pointer to user space data or not */
 	if(descr->header_type != IW_HEADER_TYPE_POINT) {
+
 		/* No extra arguments. Trivial to handle */
 		ret = handler(dev, &info, &(iwr->u), NULL);
+
+#ifdef WE_SET_EVENT
+		/* Generate an event to notify listeners of the change */
+		if((descr->flags & IW_DESCR_FLAG_EVENT) &&
+		   ((ret == 0) || (ret == -EIWCOMMIT)))
+			wireless_send_event(dev, cmd, &(iwr->u), NULL);
+#endif	/* WE_SET_EVENT */
 	} else {
 		char *	extra;
 		int	err;
@@ -466,8 +524,8 @@
 		}
 
 #ifdef WE_IOCTL_DEBUG
-		printk(KERN_DEBUG "Malloc %d bytes\n",
-		       descr->max_tokens * descr->token_size);
+		printk(KERN_DEBUG "%s (WE) : Malloc %d bytes\n",
+		       dev->name, descr->max_tokens * descr->token_size);
 #endif	/* WE_IOCTL_DEBUG */
 
 		/* Always allocate for max space. Easier, and won't last
@@ -488,7 +546,8 @@
 				return -EFAULT;
 			}
 #ifdef WE_IOCTL_DEBUG
-			printk(KERN_DEBUG "Got %d bytes\n",
+			printk(KERN_DEBUG "%s (WE) : Got %d bytes\n",
+			       dev->name,
 			       iwr->u.data.length * descr->token_size);
 #endif	/* WE_IOCTL_DEBUG */
 		}
@@ -504,11 +563,26 @@
 			if (err)
 				ret =  -EFAULT;				   
 #ifdef WE_IOCTL_DEBUG
-			printk(KERN_DEBUG "Wrote %d bytes\n",
+			printk(KERN_DEBUG "%s (WE) : Wrote %d bytes\n",
+			       dev->name,
 			       iwr->u.data.length * descr->token_size);
 #endif	/* WE_IOCTL_DEBUG */
 		}
 
+#ifdef WE_SET_EVENT
+		/* Generate an event to notify listeners of the change */
+		if((descr->flags & IW_DESCR_FLAG_EVENT) &&
+		   ((ret == 0) || (ret == -EIWCOMMIT))) {
+			if(descr->flags & IW_DESCR_FLAG_RESTRICT)
+				/* If the event is restricted, don't
+				 * export the payload */
+				wireless_send_event(dev, cmd, &(iwr->u), NULL);
+			else
+				wireless_send_event(dev, cmd, &(iwr->u),
+						    extra);
+		}
+#endif	/* WE_SET_EVENT */
+
 		/* Cleanup - I told you it wasn't that long ;-) */
 		kfree(extra);
 	}
@@ -558,11 +632,12 @@
 		}
 
 #ifdef WE_IOCTL_DEBUG
-	printk(KERN_DEBUG "%s : Found private handler for 0x%04X\n",
+	printk(KERN_DEBUG "%s (WE) : Found private handler for 0x%04X\n",
 	       ifr->ifr_name, cmd);
 	if(descr) {
-		printk(KERN_DEBUG "Name %s, set %X, get %X\n",
-		       descr->name, descr->set_args, descr->get_args);
+		printk(KERN_DEBUG "%s (WE) : Name %s, set %X, get %X\n",
+		       dev->name, descr->name,
+		       descr->set_args, descr->get_args);
 	}
 #endif	/* WE_IOCTL_DEBUG */
 
@@ -617,7 +692,8 @@
 		}
 
 #ifdef WE_IOCTL_DEBUG
-		printk(KERN_DEBUG "Malloc %d bytes\n", extra_size);
+		printk(KERN_DEBUG "%s (WE) : Malloc %d bytes\n",
+		       dev->name, extra_size);
 #endif	/* WE_IOCTL_DEBUG */
 
 		/* Always allocate for max space. Easier, and won't last
@@ -636,7 +712,8 @@
 				return -EFAULT;
 			}
 #ifdef WE_IOCTL_DEBUG
-			printk(KERN_DEBUG "Got %d elem\n", iwr->u.data.length);
+			printk(KERN_DEBUG "%s (WE) : Got %d elem\n",
+			       dev->name, iwr->u.data.length);
 #endif	/* WE_IOCTL_DEBUG */
 		}
 
@@ -650,8 +727,8 @@
 			if (err)
 				ret =  -EFAULT;				   
 #ifdef WE_IOCTL_DEBUG
-			printk(KERN_DEBUG "Wrote %d elem\n",
-			       iwr->u.data.length);
+			printk(KERN_DEBUG "%s (WE) : Wrote %d elem\n",
+			       dev->name, iwr->u.data.length);
 #endif	/* WE_IOCTL_DEBUG */
 		}
 
@@ -730,4 +807,178 @@
 	}
 	/* Not reached */
 	return -EINVAL;
+}
+
+/************************* EVENT PROCESSING *************************/
+/*
+ * Process events generated by the wireless layer or the driver.
+ * Most often, the event will be propagated through rtnetlink
+ */
+
+#ifdef WE_EVENT_NETLINK
+/* "rtnl" is defined in net/core/rtnetlink.c, but we need it here.
+ * It is declared in <linux/rtnetlink.h> */
+
+/* ---------------------------------------------------------------- */
+/*
+ * Fill a rtnetlink message with our event data.
+ * Note that we propage only the specified event and don't dump the
+ * current wireless config. Dumping the wireless config is far too
+ * expensive (for each parameter, the driver need to query the hardware).
+ */
+static inline int rtnetlink_fill_iwinfo(struct sk_buff *	skb,
+					struct net_device *	dev,
+					int			type,
+					char *			event,
+					int			event_len)
+{
+	struct ifinfomsg *r;
+	struct nlmsghdr  *nlh;
+	unsigned char	 *b = skb->tail;
+
+	nlh = NLMSG_PUT(skb, 0, 0, type, sizeof(*r));
+	r = NLMSG_DATA(nlh);
+	r->ifi_family = AF_UNSPEC;
+	r->ifi_type = dev->type;
+	r->ifi_index = dev->ifindex;
+	r->ifi_flags = dev->flags;
+	r->ifi_change = 0;	/* Wireless changes don't affect those flags */
+
+	/* Add the wireless events in the netlink packet */
+	RTA_PUT(skb, IFLA_WIRELESS,
+		event_len, event);
+
+	nlh->nlmsg_len = skb->tail - b;
+	return skb->len;
+
+nlmsg_failure:
+rtattr_failure:
+	skb_trim(skb, b - skb->data);
+	return -1;
+}
+
+/* ---------------------------------------------------------------- */
+/*
+ * Create and broadcast and send it on the standard rtnetlink socket
+ * This is a pure clone rtmsg_ifinfo() in net/core/rtnetlink.c
+ * Andrzej Krzysztofowicz mandated that I used a IFLA_XXX field
+ * within a RTM_NEWLINK event.
+ */
+static inline void rtmsg_iwinfo(struct net_device *	dev,
+				char *			event,
+				int			event_len)
+{
+	struct sk_buff *skb;
+	int size = NLMSG_GOODSIZE;
+
+	skb = alloc_skb(size, GFP_ATOMIC);
+	if (!skb)
+		return;
+
+	if (rtnetlink_fill_iwinfo(skb, dev, RTM_NEWLINK,
+				  event, event_len) < 0) {
+		kfree_skb(skb);
+		return;
+	}
+	NETLINK_CB(skb).dst_groups = RTMGRP_LINK;
+	netlink_broadcast(rtnl, skb, 0, RTMGRP_LINK, GFP_ATOMIC);
+}
+#endif	/* WE_EVENT_NETLINK */
+
+/* ---------------------------------------------------------------- */
+/*
+ * Main event dispatcher. Called from other parts and drivers.
+ * Send the event on the apropriate channels.
+ * May be called from interrupt context.
+ */
+void wireless_send_event(struct net_device *	dev,
+			 unsigned int		cmd,
+			 union iwreq_data *	wrqu,
+			 char *			extra)
+{
+	const struct iw_ioctl_description *	descr = NULL;
+	int extra_len = 0;
+	struct iw_event  *event;		/* Mallocated whole event */
+	int event_len;				/* Its size */
+	int hdr_len;				/* Size of the event header */
+	/* Don't "optimise" the following variable, it will crash */
+	unsigned	cmd_index;		/* *MUST* be unsigned */
+
+	/* Get the description of the IOCTL */
+	if(cmd <= SIOCIWLAST) {
+		cmd_index = cmd - SIOCIWFIRST;
+		if(cmd_index < standard_ioctl_num)
+			descr = &(standard_ioctl[cmd_index]);
+	} else {
+		cmd_index = cmd - IWEVFIRST;
+		if(cmd_index < standard_event_num)
+			descr = &(standard_event[cmd_index]);
+	}
+	/* Don't accept unknown events */
+	if(descr == NULL) {
+		/* Note : we don't return an error to the driver, because
+		 * the driver would not know what to do about it. It can't
+		 * return an error to the user, because the event is not
+		 * initiated by a user request.
+		 * The best the driver could do is to log an error message.
+		 * We will do it ourselves instead...
+		 */
+	  	printk(KERN_ERR "%s (WE) : Invalid Wireless Event (0x%04X)\n",
+		       dev->name, cmd);
+		return;
+	}
+#ifdef WE_EVENT_DEBUG
+	printk(KERN_DEBUG "%s (WE) : Got event 0x%04X\n",
+	       dev->name, cmd);
+	printk(KERN_DEBUG "%s (WE) : Header type : %d, Token type : %d, size : %d, token : %d\n", dev->name, descr->header_type, descr->token_type, descr->token_size, descr->max_tokens);
+#endif	/* WE_EVENT_DEBUG */
+
+	/* Check extra parameters and set extra_len */
+	if(descr->header_type == IW_HEADER_TYPE_POINT) {
+		/* Check if number of token fits within bounds */
+		if(wrqu->data.length > descr->max_tokens) {
+		  	printk(KERN_ERR "%s (WE) : Wireless Event too big (%d)\n", dev->name, wrqu->data.length);
+			return;
+		}
+		if(wrqu->data.length < descr->min_tokens) {
+		  	printk(KERN_ERR "%s (WE) : Wireless Event too small (%d)\n", dev->name, wrqu->data.length);
+			return;
+		}
+		/* Calculate extra_len - extra is NULL for restricted events */
+		if(extra != NULL)
+			extra_len = wrqu->data.length * descr->token_size;
+#ifdef WE_EVENT_DEBUG
+		printk(KERN_DEBUG "%s (WE) : Event 0x%04X, tokens %d, extra_len %d\n", dev->name, cmd, wrqu->data.length, extra_len);
+#endif	/* WE_EVENT_DEBUG */
+	}
+
+	/* Total length of the event */
+	hdr_len = event_type_size[descr->header_type];
+	event_len = hdr_len + extra_len;
+
+#ifdef WE_EVENT_DEBUG
+	printk(KERN_DEBUG "%s (WE) : Event 0x%04X, hdr_len %d, event_len %d\n", dev->name, cmd, hdr_len, event_len);
+#endif	/* WE_EVENT_DEBUG */
+
+	/* Create temporary buffer to hold the event */
+	event = kmalloc(event_len, GFP_ATOMIC);
+	if(event == NULL)
+		return;
+
+	/* Fill event */
+	event->len = event_len;
+	event->cmd = cmd;
+	memcpy(&event->u, wrqu, hdr_len - IW_EV_LCP_LEN);
+	if(extra != NULL)
+		memcpy(((char *) event) + hdr_len, extra, extra_len);
+
+#ifdef WE_EVENT_NETLINK
+	/* rtnetlink event channel */
+	rtmsg_iwinfo(dev, (char *) event, event_len);
+#endif	/* WE_EVENT_NETLINK */
+
+	/* Cleanup */
+	kfree(event);
+
+	return;		/* Always success, I guess ;-) */
 }
diff -Nru a/net/econet/af_econet.c b/net/econet/af_econet.c
--- a/net/econet/af_econet.c	Fri Mar 15 17:51:03 2002
+++ b/net/econet/af_econet.c	Fri Mar 15 17:51:03 2002
@@ -554,7 +554,7 @@
 	memset(eo, 0, sizeof(*eo));
 	sk->zapped=0;
 	sk->family = PF_ECONET;
-	sk->num = protocol;
+	eo->num = protocol;
 
 	sklist_insert_socket(&econet_sklist, sk);
 	return(0);
diff -Nru a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c
--- a/net/ipv4/af_inet.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv4/af_inet.c	Fri Mar 15 17:51:01 2002
@@ -270,14 +270,15 @@
 
 static int inet_autobind(struct sock *sk)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	/* We may need to bind the socket. */
 	lock_sock(sk);
-	if (sk->num == 0) {
+	if (!inet->num) {
 		if (sk->prot->get_port(sk, 0) != 0) {
 			release_sock(sk);
 			return -EAGAIN;
 		}
-		sk->sport = htons(sk->num);
+		inet->sport = htons(inet->num);
 	}
 	release_sock(sk);
 	return 0;
@@ -397,7 +398,7 @@
 	inet = inet_sk(sk);
 
 	if (SOCK_RAW == sock->type) {
-		sk->num = protocol;
+		inet->num = protocol;
 		if (IPPROTO_RAW == protocol)
 			inet->hdrincl = 1;
 	}
@@ -430,13 +431,13 @@
 	atomic_inc(&inet_sock_nr);
 #endif
 
-	if (sk->num) {
+	if (inet->num) {
 		/* It assumes that any protocol which allows
 		 * the user to assign a number at socket
 		 * creation time automatically
 		 * shares.
 		 */
-		sk->sport = htons(sk->num);
+		inet->sport = htons(inet->num);
 
 		/* Add to protocol hash chains. */
 		sk->prot->hash(sk);
@@ -551,28 +552,27 @@
 
 	/* Check these errors (active socket, double bind). */
 	err = -EINVAL;
-	if ((sk->state != TCP_CLOSE)			||
-	    (sk->num != 0))
+	if (sk->state != TCP_CLOSE || inet->num)
 		goto out;
 
-	sk->rcv_saddr = sk->saddr = addr->sin_addr.s_addr;
+	inet->rcv_saddr = inet->saddr = addr->sin_addr.s_addr;
 	if (chk_addr_ret == RTN_MULTICAST || chk_addr_ret == RTN_BROADCAST)
-		sk->saddr = 0;  /* Use device */
+		inet->saddr = 0;  /* Use device */
 
 	/* Make sure we are allowed to bind here. */
 	if (sk->prot->get_port(sk, snum) != 0) {
-		sk->saddr = sk->rcv_saddr = 0;
+		inet->saddr = inet->rcv_saddr = 0;
 		err = -EADDRINUSE;
 		goto out;
 	}
 
-	if (sk->rcv_saddr)
+	if (inet->rcv_saddr)
 		sk->userlocks |= SOCK_BINDADDR_LOCK;
 	if (snum)
 		sk->userlocks |= SOCK_BINDPORT_LOCK;
-	sk->sport = htons(sk->num);
-	sk->daddr = 0;
-	sk->dport = 0;
+	inet->sport = htons(inet->num);
+	inet->daddr = 0;
+	inet->dport = 0;
 	sk_dst_reset(sk);
 	err = 0;
 out:
@@ -588,7 +588,7 @@
 	if (uaddr->sa_family == AF_UNSPEC)
 		return sk->prot->disconnect(sk, flags);
 
-	if (sk->num==0 && inet_autobind(sk) != 0)
+	if (!inet_sk(sk)->num && inet_autobind(sk))
 		return -EAGAIN;
 	return sk->prot->connect(sk, (struct sockaddr *)uaddr, addr_len);
 }
@@ -627,6 +627,7 @@
 			int addr_len, int flags)
 {
 	struct sock *sk=sock->sk;
+	struct inet_opt *inet = inet_sk(sk);
 	int err;
 	long timeo;
 
@@ -655,10 +656,10 @@
 			goto out;
 
 		err = -EAGAIN;
-		if (sk->num == 0) {
+		if (!inet->num) {
 			if (sk->prot->get_port(sk, 0) != 0)
 				goto out;
-			sk->sport = htons(sk->num);
+			inet->sport = htons(inet->num);
 		}
 
 		err = sk->prot->connect(sk, uaddr, addr_len);
@@ -748,21 +749,22 @@
 		 int *uaddr_len, int peer)
 {
 	struct sock *sk		= sock->sk;
+	struct inet_opt *inet	= inet_sk(sk);
 	struct sockaddr_in *sin	= (struct sockaddr_in *)uaddr;
   
 	sin->sin_family = AF_INET;
 	if (peer) {
-		if (!sk->dport)
+		if (!inet->dport)
 			return -ENOTCONN;
 		if (((1<<sk->state)&(TCPF_CLOSE|TCPF_SYN_SENT)) && peer == 1)
 			return -ENOTCONN;
-		sin->sin_port = sk->dport;
-		sin->sin_addr.s_addr = sk->daddr;
+		sin->sin_port = inet->dport;
+		sin->sin_addr.s_addr = inet->daddr;
 	} else {
-		__u32 addr = sk->rcv_saddr;
+		__u32 addr = inet->rcv_saddr;
 		if (!addr)
-			addr = sk->saddr;
-		sin->sin_port = sk->sport;
+			addr = inet->saddr;
+		sin->sin_port = inet->sport;
 		sin->sin_addr.s_addr = addr;
 	}
 	*uaddr_len = sizeof(*sin);
@@ -792,7 +794,7 @@
 	struct sock *sk = sock->sk;
 
 	/* We may need to bind the socket. */
-	if (sk->num==0 && inet_autobind(sk) != 0)
+	if (!inet_sk(sk)->num && inet_autobind(sk))
 		return -EAGAIN;
 
 	return sk->prot->sendmsg(sk, msg, size);
diff -Nru a/net/ipv4/arp.c b/net/ipv4/arp.c
--- a/net/ipv4/arp.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/arp.c	Fri Mar 15 17:51:02 2002
@@ -112,7 +112,7 @@
 #include <asm/system.h>
 #include <asm/uaccess.h>
 
-
+#include <linux/netfilter_arp.h>
 
 /*
  *	Interface to generic neighbour cache.
@@ -561,7 +561,8 @@
 	arp_ptr+=dev->addr_len;
 	memcpy(arp_ptr, &dest_ip, 4);
 
-	dev_queue_xmit(skb);
+	/* Send it off, maybe filter it using firewalling first.  */
+	NF_HOOK(NF_ARP, NF_ARP_OUT, skb, NULL, dev, dev_queue_xmit);
 	return;
 
 out:
@@ -574,45 +575,31 @@
 }
 
 /*
- *	Receive an arp request by the device layer.
+ *	Process an arp request.
  */
 
-int arp_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt)
+int arp_process(struct sk_buff *skb)
 {
-	struct arphdr *arp = skb->nh.arph;
-	unsigned char *arp_ptr= (unsigned char *)(arp+1);
+	struct net_device *dev = skb->dev;
+	struct in_device *in_dev = in_dev_get(dev);
+	struct arphdr *arp;
+	unsigned char *arp_ptr;
 	struct rtable *rt;
 	unsigned char *sha, *tha;
 	u32 sip, tip;
 	u16 dev_type = dev->type;
 	int addr_type;
-	struct in_device *in_dev = in_dev_get(dev);
 	struct neighbour *n;
 
-/*
- *	The hardware length of the packet should match the hardware length
- *	of the device.  Similarly, the hardware types should match.  The
- *	device should be ARP-able.  Also, if pln is not 4, then the lookup
- *	is not from an IP number.  We can't currently handle this, so toss
- *	it. 
- */  
-	if (in_dev == NULL ||
-	    arp->ar_hln != dev->addr_len    || 
-	    dev->flags & IFF_NOARP ||
-	    skb->pkt_type == PACKET_OTHERHOST ||
-	    skb->pkt_type == PACKET_LOOPBACK ||
-	    arp->ar_pln != 4)
+	/* arp_rcv below verifies the ARP header, verifies the device
+	 * is ARP'able, and linearizes the SKB (if needed).
+	 */
+
+	if (in_dev == NULL)
 		goto out;
 
-	if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL)
-		goto out_of_mem;
-
-	if (skb_is_nonlinear(skb)) {
-		if (skb_linearize(skb, GFP_ATOMIC) != 0)
-			goto freeskb;
-		arp = skb->nh.arph;
-		arp_ptr= (unsigned char *)(arp+1);
-	}
+	arp = skb->nh.arph;
+	arp_ptr= (unsigned char *)(arp+1);
 
 	switch (dev_type) {
 	default:	
@@ -827,13 +814,41 @@
 out:
 	if (in_dev)
 		in_dev_put(in_dev);
-freeskb:
 	kfree_skb(skb);
-out_of_mem:
 	return 0;
 }
 
 
+/*
+ *	Receive an arp request from the device layer.
+ */
+
+int arp_rcv(struct sk_buff *skb, struct net_device *dev, struct packet_type *pt)
+{
+	struct arphdr *arp = skb->nh.arph;
+
+	if (arp->ar_hln != dev->addr_len ||
+	    dev->flags & IFF_NOARP ||
+	    skb->pkt_type == PACKET_OTHERHOST ||
+	    skb->pkt_type == PACKET_LOOPBACK ||
+	    arp->ar_pln != 4)
+		goto freeskb;
+
+	if ((skb = skb_share_check(skb, GFP_ATOMIC)) == NULL)
+		goto out_of_mem;
+
+	if (skb_is_nonlinear(skb)) {
+		if (skb_linearize(skb, GFP_ATOMIC) != 0)
+			goto freeskb;
+	}
+
+	return NF_HOOK(NF_ARP, NF_ARP_IN, skb, dev, NULL, arp_process);
+
+freeskb:
+	kfree_skb(skb);
+out_of_mem:
+	return 0;
+}
 
 /*
  *	User level interface (ioctl, /proc)
diff -Nru a/net/ipv4/ip_input.c b/net/ipv4/ip_input.c
--- a/net/ipv4/ip_input.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv4/ip_input.c	Fri Mar 15 17:51:01 2002
@@ -166,7 +166,7 @@
 		/* If socket is bound to an interface, only report
 		 * the packet if it came  from that interface.
 		 */
-		if (sk && sk->num == protocol 
+		if (sk && inet_sk(sk)->num == protocol 
 		    && ((sk->bound_dev_if == 0) 
 			|| (sk->bound_dev_if == skb->dev->ifindex))) {
 			if (skb->nh.iph->frag_off & htons(IP_MF|IP_OFFSET)) {
diff -Nru a/net/ipv4/ip_output.c b/net/ipv4/ip_output.c
--- a/net/ipv4/ip_output.c	Fri Mar 15 17:51:03 2002
+++ b/net/ipv4/ip_output.c	Fri Mar 15 17:51:03 2002
@@ -135,9 +135,10 @@
 	iph->version  = 4;
 	iph->ihl      = 5;
 	iph->tos      = inet->tos;
-	iph->frag_off = 0;
 	if (ip_dont_fragment(sk, &rt->u.dst))
-		iph->frag_off |= htons(IP_DF);
+		iph->frag_off = __constant_htons(IP_DF);
+	else
+		iph->frag_off = 0;
 	iph->ttl      = inet->ttl;
 	iph->daddr    = rt->rt_dst;
 	iph->saddr    = rt->rt_src;
@@ -308,9 +309,6 @@
 	if (skb->len > rt->u.dst.pmtu)
 		goto fragment;
 
-	if (ip_dont_fragment(sk, &rt->u.dst))
-		iph->frag_off |= __constant_htons(IP_DF);
-
 	ip_select_ident(iph, &rt->u.dst, sk);
 
 	/* Add an IP checksum. */
@@ -324,7 +322,6 @@
 		/* Reject packet ONLY if TCP might fragment
 		 * it itself, if were careful enough.
 		 */
-		iph->frag_off |= __constant_htons(IP_DF);
 		NETDEBUG(printk(KERN_DEBUG "sending pkt_too_big to self\n"));
 
 		icmp_send(skb, ICMP_DEST_UNREACH, ICMP_FRAG_NEEDED,
@@ -360,7 +357,7 @@
 		u32 daddr;
 
 		/* Use correct destination address if we have options. */
-		daddr = sk->daddr;
+		daddr = inet->daddr;
 		if(opt && opt->srr)
 			daddr = opt->faddr;
 
@@ -368,7 +365,7 @@
 		 * keep trying until route appears or the connection times itself
 		 * out.
 		 */
-		if (ip_route_output(&rt, daddr, sk->saddr,
+		if (ip_route_output(&rt, daddr, inet->saddr,
 				    RT_CONN_FLAGS(sk),
 				    sk->bound_dev_if))
 			goto no_route;
@@ -385,7 +382,10 @@
 	iph = (struct iphdr *) skb_push(skb, sizeof(struct iphdr) + (opt ? opt->optlen : 0));
 	*((__u16 *)iph)	= htons((4 << 12) | (5 << 8) | (inet->tos & 0xff));
 	iph->tot_len = htons(skb->len);
-	iph->frag_off = 0;
+	if (ip_dont_fragment(sk, &rt->u.dst))
+		iph->frag_off = __constant_htons(IP_DF);
+	else
+		iph->frag_off = 0;
 	iph->ttl      = inet->ttl;
 	iph->protocol = sk->protocol;
 	iph->saddr    = rt->rt_src;
@@ -395,7 +395,7 @@
 
 	if(opt && opt->optlen) {
 		iph->ihl += opt->optlen >> 2;
-		ip_options_build(skb, opt, sk->daddr, rt, 0);
+		ip_options_build(skb, opt, inet->daddr, rt, 0);
 	}
 
 	return NF_HOOK(PF_INET, NF_IP_LOCAL_OUT, skb, NULL, rt->u.dst.dev,
@@ -452,7 +452,7 @@
 
 	mtu = rt->u.dst.pmtu;
 	if (ip_dont_fragment(sk, &rt->u.dst))
-		df = htons(IP_DF);
+		df = __constant_htons(IP_DF);
 
 	length -= sizeof(struct iphdr);
 
@@ -471,7 +471,7 @@
 	}
 
 	if (length + fragheaderlen > 0xFFFF) {
-		ip_local_error(sk, EMSGSIZE, rt->rt_dst, sk->dport, mtu);
+		ip_local_error(sk, EMSGSIZE, rt->rt_dst, inet->dport, mtu);
 		return -EMSGSIZE;
 	}
 
@@ -503,7 +503,7 @@
 	 */
 
 	if (offset > 0 && inet->pmtudisc == IP_PMTUDISC_DO) { 
-		ip_local_error(sk, EMSGSIZE, rt->rt_dst, sk->dport, mtu);
+		ip_local_error(sk, EMSGSIZE, rt->rt_dst, inet->dport, mtu);
  		return -EMSGSIZE;
 	}
 	if (flags&MSG_PROBE)
@@ -573,7 +573,7 @@
 				/*
 				 *	Any further fragments will have MF set.
 				 */
-				mf = htons(IP_MF);
+				mf = __constant_htons(IP_MF);
 			}
 			if (rt->rt_type == RTN_MULTICAST)
 				iph->ttl = inet->mc_ttl;
@@ -659,7 +659,8 @@
 			return ip_build_xmit_slow(sk,getfrag,frag,length,ipc,rt,flags); 
 	} else {
 		if (length > rt->u.dst.dev->mtu) {
-			ip_local_error(sk, EMSGSIZE, rt->rt_dst, sk->dport, rt->u.dst.dev->mtu);
+			ip_local_error(sk, EMSGSIZE, rt->rt_dst, inet->dport,
+				       rt->u.dst.dev->mtu);
 			return -EMSGSIZE;
 		}
 	}
@@ -671,7 +672,7 @@
 	 */
 	df = 0;
 	if (ip_dont_fragment(sk, &rt->u.dst))
-		df = htons(IP_DF);
+		df = __constant_htons(IP_DF);
 
 	/* 
 	 *	Fast path for unfragmented frames without options. 
@@ -775,7 +776,7 @@
 	 */
 
 	offset = (ntohs(iph->frag_off) & IP_OFFSET) << 3;
-	not_last_frag = iph->frag_off & htons(IP_MF);
+	not_last_frag = iph->frag_off & __constant_htons(IP_MF);
 
 	/*
 	 *	Keep copying data until we run out.
@@ -860,7 +861,7 @@
 		 *		   last fragment then keep MF on each bit
 		 */
 		if (left > 0 || not_last_frag)
-			iph->frag_off |= htons(IP_MF);
+			iph->frag_off |= __constant_htons(IP_MF);
 		ptr += len;
 		offset += len;
 
diff -Nru a/net/ipv4/ip_sockglue.c b/net/ipv4/ip_sockglue.c
--- a/net/ipv4/ip_sockglue.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/ip_sockglue.c	Fri Mar 15 17:51:02 2002
@@ -193,7 +193,7 @@
 {
 	struct ip_ra_chain *ra, *new_ra, **rap;
 
-	if (sk->type != SOCK_RAW || sk->num == IPPROTO_RAW)
+	if (sk->type != SOCK_RAW || inet_sk(sk)->num == IPPROTO_RAW)
 		return -EINVAL;
 
 	new_ra = on ? kmalloc(sizeof(*new_ra), GFP_KERNEL) : NULL;
@@ -435,7 +435,7 @@
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
 				if (sk->family == PF_INET ||
 				    (!((1<<sk->state)&(TCPF_LISTEN|TCPF_CLOSE))
-				     && sk->daddr != LOOPBACK4_IPV6)) {
+				     && inet->daddr != LOOPBACK4_IPV6)) {
 #endif
 					if (opt)
 						tp->ext_header_len = opt->optlen;
@@ -771,8 +771,8 @@
 			if (inet->cmsg_flags & IP_CMSG_PKTINFO) {
 				struct in_pktinfo info;
 
-				info.ipi_addr.s_addr = sk->rcv_saddr;
-				info.ipi_spec_dst.s_addr = sk->rcv_saddr;
+				info.ipi_addr.s_addr = inet->rcv_saddr;
+				info.ipi_spec_dst.s_addr = inet->rcv_saddr;
 				info.ipi_ifindex = inet->mc_index;
 				put_cmsg(&msg, SOL_IP, IP_PKTINFO, sizeof(info), &info);
 			}
diff -Nru a/net/ipv4/ipmr.c b/net/ipv4/ipmr.c
--- a/net/ipv4/ipmr.c	Fri Mar 15 17:51:03 2002
+++ b/net/ipv4/ipmr.c	Fri Mar 15 17:51:03 2002
@@ -855,7 +855,7 @@
 	switch(optname)
 	{
 		case MRT_INIT:
-			if(sk->type!=SOCK_RAW || sk->num!=IPPROTO_IGMP)
+			if(sk->type!=SOCK_RAW || inet_sk(sk)->num!=IPPROTO_IGMP)
 				return -EOPNOTSUPP;
 			if(optlen!=sizeof(int))
 				return -ENOPROTOOPT;
diff -Nru a/net/ipv4/netfilter/Config.in b/net/ipv4/netfilter/Config.in
--- a/net/ipv4/netfilter/Config.in	Fri Mar 15 17:51:03 2002
+++ b/net/ipv4/netfilter/Config.in	Fri Mar 15 17:51:03 2002
@@ -47,6 +47,7 @@
       define_bool CONFIG_IP_NF_NAT_NEEDED y
       dep_tristate '    MASQUERADE target support' CONFIG_IP_NF_TARGET_MASQUERADE $CONFIG_IP_NF_NAT
       dep_tristate '    REDIRECT target support' CONFIG_IP_NF_TARGET_REDIRECT $CONFIG_IP_NF_NAT
+      bool '    NAT of local connections' CONFIG_IP_NF_NAT_LOCAL
       if [ "$CONFIG_EXPERIMENTAL" = "y" ]; then
         dep_tristate '    Basic SNMP-ALG support (EXPERIMENTAL)' CONFIG_IP_NF_NAT_SNMP_BASIC $CONFIG_IP_NF_NAT
       fi
@@ -75,10 +76,13 @@
     dep_tristate '    MARK target support' CONFIG_IP_NF_TARGET_MARK $CONFIG_IP_NF_MANGLE
   fi
   dep_tristate '  LOG target support' CONFIG_IP_NF_TARGET_LOG $CONFIG_IP_NF_IPTABLES
-  if [ "$CONFIG_NETLINK" != "n" ]; then
-     dep_tristate '  ULOG target support' CONFIG_IP_NF_TARGET_ULOG $CONFIG_NETLINK $CONFIG_IP_NF_IPTABLES
-  fi
+  dep_tristate '  ULOG target support' CONFIG_IP_NF_TARGET_ULOG $CONFIG_IP_NF_IPTABLES
   dep_tristate '  TCPMSS target support' CONFIG_IP_NF_TARGET_TCPMSS $CONFIG_IP_NF_IPTABLES
+fi
+
+tristate 'ARP tables support' CONFIG_IP_NF_ARPTABLES
+if [ "$CONFIG_IP_NF_ARPTABLES" != "n" ]; then
+  dep_tristate '  ARP packet filtering' CONFIG_IP_NF_ARPFILTER $CONFIG_IP_NF_ARPTABLES 
 fi
 
 # Backwards compatibility modules: only if you don't build in the others.
diff -Nru a/net/ipv4/netfilter/Makefile b/net/ipv4/netfilter/Makefile
--- a/net/ipv4/netfilter/Makefile	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/netfilter/Makefile	Fri Mar 15 17:51:02 2002
@@ -9,7 +9,7 @@
 
 O_TARGET := netfilter.o
 
-export-objs = ip_conntrack_standalone.o ip_conntrack_ftp.o ip_fw_compat.o ip_nat_standalone.o ip_tables.o
+export-objs = ip_conntrack_standalone.o ip_conntrack_ftp.o ip_fw_compat.o ip_nat_standalone.o ip_tables.o arp_tables.o
 
 # Multipart objects.
 list-multi		:= ip_conntrack.o iptable_nat.o ipfwadm.o ipchains.o
@@ -31,15 +31,13 @@
 # connection tracking
 obj-$(CONFIG_IP_NF_CONNTRACK) += ip_conntrack.o
 
-# IRC support
-obj-$(CONFIG_IP_NF_IRC) += ip_conntrack_irc.o
-obj-$(CONFIG_IP_NF_NAT_IRC) += ip_nat_irc.o
-
 # connection tracking helpers
 obj-$(CONFIG_IP_NF_FTP) += ip_conntrack_ftp.o
+obj-$(CONFIG_IP_NF_IRC) += ip_conntrack_irc.o
 
 # NAT helpers 
 obj-$(CONFIG_IP_NF_NAT_FTP) += ip_nat_ftp.o
+obj-$(CONFIG_IP_NF_NAT_IRC) += ip_nat_irc.o
 
 # generic IP tables 
 obj-$(CONFIG_IP_NF_IPTABLES) += ip_tables.o
@@ -76,6 +74,12 @@
 obj-$(CONFIG_IP_NF_TARGET_LOG) += ipt_LOG.o
 obj-$(CONFIG_IP_NF_TARGET_ULOG) += ipt_ULOG.o
 obj-$(CONFIG_IP_NF_TARGET_TCPMSS) += ipt_TCPMSS.o
+
+# generic ARP tables
+obj-$(CONFIG_IP_NF_ARPTABLES) += arp_tables.o
+
+# just filtering instance of ARP tables for now
+obj-$(CONFIG_IP_NF_ARPFILTER) += arptable_filter.o
 
 # backwards compatibility 
 obj-$(CONFIG_IP_NF_COMPAT_IPCHAINS) += ipchains.o
diff -Nru a/net/ipv4/netfilter/arp_tables.c b/net/ipv4/netfilter/arp_tables.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/net/ipv4/netfilter/arp_tables.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,1313 @@
+/*
+ * Packet matching code for ARP packets.
+ *
+ * Based heavily, if not almost entirely, upon ip_tables.c framework.
+ *
+ * Some ARP specific bits are:
+ *
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ *
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/skbuff.h>
+#include <linux/netdevice.h>
+#include <linux/if_arp.h>
+#include <linux/kmod.h>
+#include <linux/vmalloc.h>
+#include <linux/proc_fs.h>
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include <asm/uaccess.h>
+#include <asm/semaphore.h>
+
+#include <linux/netfilter_arp/arp_tables.h>
+
+/*#define DEBUG_ARP_TABLES*/
+/*#define DEBUG_ARP_TABLES_USER*/
+
+#ifdef DEBUG_ARP_TABLES
+#define dprintf(format, args...)  printk(format , ## args)
+#else
+#define dprintf(format, args...)
+#endif
+
+#ifdef DEBUG_ARP_TABLES_USER
+#define duprintf(format, args...) printk(format , ## args)
+#else
+#define duprintf(format, args...)
+#endif
+
+#ifdef CONFIG_NETFILTER_DEBUG
+#define ARP_NF_ASSERT(x)					\
+do {								\
+	if (!(x))						\
+		printk("ARP_NF_ASSERT: %s:%s:%u\n",		\
+		       __FUNCTION__, __FILE__, __LINE__);	\
+} while(0)
+#else
+#define ARP_NF_ASSERT(x)
+#endif
+#define SMP_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
+
+static DECLARE_MUTEX(arpt_mutex);
+
+#define ASSERT_READ_LOCK(x) ARP_NF_ASSERT(down_trylock(&arpt_mutex) != 0)
+#define ASSERT_WRITE_LOCK(x) ARP_NF_ASSERT(down_trylock(&arpt_mutex) != 0)
+#include <linux/netfilter_ipv4/lockhelp.h>
+#include <linux/netfilter_ipv4/listhelp.h>
+
+struct arpt_table_info {
+	unsigned int size;
+	unsigned int number;
+	unsigned int initial_entries;
+	unsigned int hook_entry[NF_ARP_NUMHOOKS];
+	unsigned int underflow[NF_ARP_NUMHOOKS];
+	char entries[0] __attribute__((aligned(SMP_CACHE_BYTES)));
+};
+
+static LIST_HEAD(arpt_target);
+static LIST_HEAD(arpt_tables);
+#define ADD_COUNTER(c,b,p) do { (c).bcnt += (b); (c).pcnt += (p); } while(0)
+
+#ifdef CONFIG_SMP
+#define TABLE_OFFSET(t,p) (SMP_ALIGN((t)->size)*(p))
+#else
+#define TABLE_OFFSET(t,p) 0
+#endif
+
+static inline int arp_devaddr_compare(const struct arpt_devaddr_info *ap,
+				      char *hdr_addr, int len)
+{
+	int i, ret;
+
+	if (len > ARPT_DEV_ADDR_LEN_MAX)
+		len = ARPT_DEV_ADDR_LEN_MAX;
+
+	ret = 0;
+	for (i = 0; i < len; i++)
+		ret |= (hdr_addr[i] ^ ap->addr[i]) & ap->mask[i];
+
+	return (ret != 0);
+}
+
+/* Returns whether packet matches rule or not. */
+static inline int arp_packet_match(const struct arphdr *arphdr,
+				   struct net_device *dev,
+				   const char *indev,
+				   const char *outdev,
+				   const struct arpt_arp *arpinfo)
+{
+	char *arpptr = (char *)(arphdr + 1);
+	char *src_devaddr, *tgt_devaddr;
+	u32 *src_ipaddr, *tgt_ipaddr;
+	int i, ret;
+
+#define FWINV(bool,invflg) ((bool) ^ !!(arpinfo->invflags & invflg))
+
+	if (FWINV((arphdr->ar_op & arpinfo->arpop_mask) != arpinfo->arpop,
+		  ARPT_INV_ARPOP)) {
+		dprintf("ARP operation field mismatch.\n");
+		dprintf("ar_op: %04x info->arpop: %04x info->arpop_mask: %04x\n",
+			arphdr->ar_op, arpinfo->arpop, arpinfo->arpop_mask);
+		return 0;
+	}
+
+	if (FWINV((arphdr->ar_hrd & arpinfo->arhrd_mask) != arpinfo->arhrd,
+		  ARPT_INV_ARPHRD)) {
+		dprintf("ARP hardware address format mismatch.\n");
+		dprintf("ar_hrd: %04x info->arhrd: %04x info->arhrd_mask: %04x\n",
+			arphdr->ar_hrd, arpinfo->arhrd, arpinfo->arhrd_mask);
+		return 0;
+	}
+
+	if (FWINV((arphdr->ar_pro & arpinfo->arpro_mask) != arpinfo->arpro,
+		  ARPT_INV_ARPPRO)) {
+		dprintf("ARP protocol address format mismatch.\n");
+		dprintf("ar_pro: %04x info->arpro: %04x info->arpro_mask: %04x\n",
+			arphdr->ar_pro, arpinfo->arpro, arpinfo->arpro_mask);
+		return 0;
+	}
+
+	if (FWINV((arphdr->ar_hln & arpinfo->arhln_mask) != arpinfo->arhln,
+		  ARPT_INV_ARPHLN)) {
+		dprintf("ARP hardware address length mismatch.\n");
+		dprintf("ar_hln: %02x info->arhln: %02x info->arhln_mask: %02x\n",
+			arphdr->ar_hln, arpinfo->arhln, arpinfo->arhln_mask);
+	}
+
+	src_devaddr = arpptr;
+	arpptr += dev->addr_len;
+	src_ipaddr = (u32 *) arpptr;
+	arpptr += sizeof(u32);
+	tgt_devaddr = arpptr;
+	arpptr += dev->addr_len;
+	tgt_ipaddr = (u32 *) arpptr;
+
+	if (FWINV(arp_devaddr_compare(&arpinfo->src_devaddr, src_devaddr, dev->addr_len),
+		  ARPT_INV_SRCDEVADDR) ||
+	    FWINV(arp_devaddr_compare(&arpinfo->tgt_devaddr, tgt_devaddr, dev->addr_len),
+		  ARPT_INV_TGTDEVADDR)) {
+		dprintf("Source or target device address mismatch.\n");
+
+		return 0;
+	}
+
+	if (FWINV(((*src_ipaddr) & arpinfo->smsk.s_addr) != arpinfo->src.s_addr,
+		  ARPT_INV_SRCIP) ||
+	    FWINV((((*tgt_ipaddr) & arpinfo->tmsk.s_addr) != arpinfo->tgt.s_addr),
+		  ARPT_INV_TGTIP)) {
+		dprintf("Source or target IP address mismatch.\n");
+
+		dprintf("SRC: %u.%u.%u.%u. Mask: %u.%u.%u.%u. Target: %u.%u.%u.%u.%s\n",
+			NIPQUAD(*src_ipaddr),
+			NIPQUAD(arpinfo->smsk.s_addr),
+			NIPQUAD(arpinfo->src.s_addr),
+			arpinfo->invflags & ARPT_INV_SRCIP ? " (INV)" : "");
+		dprintf("TGT: %u.%u.%u.%u Mask: %u.%u.%u.%u Target: %u.%u.%u.%u.%s\n",
+			NIPQUAD(*tgt_ipaddr),
+			NIPQUAD(arpinfo->tmsk.s_addr),
+			NIPQUAD(arpinfo->tgt.s_addr),
+			arpinfo->invflags & ARPT_INV_TGTIP ? " (INV)" : "");
+		return 0;
+	}
+
+	/* Look for ifname matches; this should unroll nicely. */
+	for (i = 0, ret = 0; i < IFNAMSIZ/sizeof(unsigned long); i++) {
+		ret |= (((const unsigned long *)indev)[i]
+			^ ((const unsigned long *)arpinfo->iniface)[i])
+			& ((const unsigned long *)arpinfo->iniface_mask)[i];
+	}
+
+	if (FWINV(ret != 0, ARPT_INV_VIA_IN)) {
+		dprintf("VIA in mismatch (%s vs %s).%s\n",
+			indev, arpinfo->iniface,
+			arpinfo->invflags&ARPT_INV_VIA_IN ?" (INV)":"");
+		return 0;
+	}
+
+	for (i = 0, ret = 0; i < IFNAMSIZ/sizeof(unsigned long); i++) {
+		ret |= (((const unsigned long *)outdev)[i]
+			^ ((const unsigned long *)arpinfo->outiface)[i])
+			& ((const unsigned long *)arpinfo->outiface_mask)[i];
+	}
+
+	if (FWINV(ret != 0, ARPT_INV_VIA_OUT)) {
+		dprintf("VIA out mismatch (%s vs %s).%s\n",
+			outdev, arpinfo->outiface,
+			arpinfo->invflags&ARPT_INV_VIA_OUT ?" (INV)":"");
+		return 0;
+	}
+
+	return 1;
+}
+
+static inline int arp_checkentry(const struct arpt_arp *arp)
+{
+	if (arp->flags & ~ARPT_F_MASK) {
+		duprintf("Unknown flag bits set: %08X\n",
+			 arp->flags & ~ARPT_F_MASK);
+		return 0;
+	}
+	if (arp->invflags & ~ARPT_INV_MASK) {
+		duprintf("Unknown invflag bits set: %08X\n",
+			 arp->invflags & ~ARPT_INV_MASK);
+		return 0;
+	}
+
+	return 1;
+}
+
+static unsigned int arpt_error(struct sk_buff **pskb,
+			       unsigned int hooknum,
+			       const struct net_device *in,
+			       const struct net_device *out,
+			       const void *targinfo,
+			       void *userinfo)
+{
+	if (net_ratelimit())
+		printk("arp_tables: error: '%s'\n", (char *)targinfo);
+
+	return NF_DROP;
+}
+
+static inline struct arpt_entry *get_entry(void *base, unsigned int offset)
+{
+	return (struct arpt_entry *)(base + offset);
+}
+
+unsigned int arpt_do_table(struct sk_buff **pskb,
+			   unsigned int hook,
+			   const struct net_device *in,
+			   const struct net_device *out,
+			   struct arpt_table *table,
+			   void *userdata)
+{
+	static const char nulldevname[IFNAMSIZ] = { 0 };
+	unsigned int verdict = NF_DROP;
+	struct arphdr *arp = (*pskb)->nh.arph;
+	int hotdrop = 0;
+	struct arpt_entry *e, *back;
+	const char *indev, *outdev;
+	void *table_base;
+
+	indev = in ? in->name : nulldevname;
+	outdev = out ? out->name : nulldevname;
+
+	read_lock_bh(&table->lock);
+	table_base = (void *)table->private->entries
+		+ TABLE_OFFSET(table->private,
+			       cpu_number_map(smp_processor_id()));
+	e = get_entry(table_base, table->private->hook_entry[hook]);
+	back = get_entry(table_base, table->private->underflow[hook]);
+
+	do {
+		if (arp_packet_match(arp, (*pskb)->dev, indev, outdev, &e->arp)) {
+			struct arpt_entry_target *t;
+			int hdr_len;
+
+			hdr_len = sizeof(*arp) + (2 * sizeof(struct in_addr)) +
+				(2 * (*pskb)->dev->addr_len);
+			ADD_COUNTER(e->counters, hdr_len, 1);
+
+			t = arpt_get_target(e);
+
+			/* Standard target? */
+			if (!t->u.kernel.target->target) {
+				int v;
+
+				v = ((struct arpt_standard_target *)t)->verdict;
+				if (v < 0) {
+					/* Pop from stack? */
+					if (v != ARPT_RETURN) {
+						verdict = (unsigned)(-v) - 1;
+						break;
+					}
+					e = back;
+					back = get_entry(table_base,
+							 back->comefrom);
+					continue;
+				}
+				if (table_base + v
+				    != (void *)e + e->next_offset) {
+					/* Save old back ptr in next entry */
+					struct arpt_entry *next
+						= (void *)e + e->next_offset;
+					next->comefrom =
+						(void *)back - table_base;
+
+					/* set back pointer to next entry */
+					back = next;
+				}
+
+				e = get_entry(table_base, v);
+			} else {
+				/* Targets which reenter must return
+				 * abs. verdicts
+				 */
+				verdict = t->u.kernel.target->target(pskb,
+								     hook,
+								     in, out,
+								     t->data,
+								     userdata);
+
+				/* Target might have changed stuff. */
+				arp = (*pskb)->nh.arph;
+
+				if (verdict == ARPT_CONTINUE)
+					e = (void *)e + e->next_offset;
+				else
+					/* Verdict */
+					break;
+			}
+		} else {
+			e = (void *)e + e->next_offset;
+		}
+	} while (!hotdrop);
+	read_unlock_bh(&table->lock);
+
+	if (hotdrop)
+		return NF_DROP;
+	else
+		return verdict;
+}
+
+static inline void *find_inlist_lock_noload(struct list_head *head,
+					    const char *name,
+					    int *error,
+					    struct semaphore *mutex)
+{
+	void *ret;
+
+	*error = down_interruptible(mutex);
+	if (*error != 0)
+		return NULL;
+
+	ret = list_named_find(head, name);
+	if (!ret) {
+		*error = -ENOENT;
+		up(mutex);
+	}
+	return ret;
+}
+
+#ifndef CONFIG_KMOD
+#define find_inlist_lock(h,n,p,e,m) find_inlist_lock_noload((h),(n),(e),(m))
+#else
+static void *
+find_inlist_lock(struct list_head *head,
+		 const char *name,
+		 const char *prefix,
+		 int *error,
+		 struct semaphore *mutex)
+{
+	void *ret;
+
+	ret = find_inlist_lock_noload(head, name, error, mutex);
+	if (!ret) {
+		char modulename[ARPT_FUNCTION_MAXNAMELEN + strlen(prefix) + 1];
+		strcpy(modulename, prefix);
+		strcat(modulename, name);
+		duprintf("find_inlist: loading `%s'.\n", modulename);
+		request_module(modulename);
+		ret = find_inlist_lock_noload(head, name, error, mutex);
+	}
+
+	return ret;
+}
+#endif
+
+static inline struct arpt_table *find_table_lock(const char *name, int *error, struct semaphore *mutex)
+{
+	return find_inlist_lock(&arpt_tables, name, "arptable_", error, mutex);
+}
+
+static inline struct arpt_target *find_target_lock(const char *name, int *error, struct semaphore *mutex)
+{
+	return find_inlist_lock(&arpt_target, name, "arpt_", error, mutex);
+}
+
+/* All zeroes == unconditional rule. */
+static inline int unconditional(const struct arpt_arp *arp)
+{
+	unsigned int i;
+
+	for (i = 0; i < sizeof(*arp)/sizeof(__u32); i++)
+		if (((__u32 *)arp)[i])
+			return 0;
+
+	return 1;
+}
+
+/* Figures out from what hook each rule can be called: returns 0 if
+ * there are loops.  Puts hook bitmask in comefrom.
+ */
+static int mark_source_chains(struct arpt_table_info *newinfo, unsigned int valid_hooks)
+{
+	unsigned int hook;
+
+	/* No recursion; use packet counter to save back ptrs (reset
+	 * to 0 as we leave), and comefrom to save source hook bitmask.
+	 */
+	for (hook = 0; hook < NF_ARP_NUMHOOKS; hook++) {
+		unsigned int pos = newinfo->hook_entry[hook];
+		struct arpt_entry *e
+			= (struct arpt_entry *)(newinfo->entries + pos);
+
+		if (!(valid_hooks & (1 << hook)))
+			continue;
+
+		/* Set initial back pointer. */
+		e->counters.pcnt = pos;
+
+		for (;;) {
+			struct arpt_standard_target *t
+				= (void *)arpt_get_target(e);
+
+			if (e->comefrom & (1 << NF_ARP_NUMHOOKS)) {
+				printk("arptables: loop hook %u pos %u %08X.\n",
+				       hook, pos, e->comefrom);
+				return 0;
+			}
+			e->comefrom
+				|= ((1 << hook) | (1 << NF_ARP_NUMHOOKS));
+
+			/* Unconditional return/END. */
+			if (e->target_offset == sizeof(struct arpt_entry)
+			    && (strcmp(t->target.u.user.name,
+				       ARPT_STANDARD_TARGET) == 0)
+			    && t->verdict < 0
+			    && unconditional(&e->arp)) {
+				unsigned int oldpos, size;
+
+				/* Return: backtrack through the last
+				 * big jump.
+				 */
+				do {
+					e->comefrom ^= (1<<NF_ARP_NUMHOOKS);
+					oldpos = pos;
+					pos = e->counters.pcnt;
+					e->counters.pcnt = 0;
+
+					/* We're at the start. */
+					if (pos == oldpos)
+						goto next;
+
+					e = (struct arpt_entry *)
+						(newinfo->entries + pos);
+				} while (oldpos == pos + e->next_offset);
+
+				/* Move along one */
+				size = e->next_offset;
+				e = (struct arpt_entry *)
+					(newinfo->entries + pos + size);
+				e->counters.pcnt = pos;
+				pos += size;
+			} else {
+				int newpos = t->verdict;
+
+				if (strcmp(t->target.u.user.name,
+					   ARPT_STANDARD_TARGET) == 0
+				    && newpos >= 0) {
+					/* This a jump; chase it. */
+					duprintf("Jump rule %u -> %u\n",
+						 pos, newpos);
+				} else {
+					/* ... this is a fallthru */
+					newpos = pos + e->next_offset;
+				}
+				e = (struct arpt_entry *)
+					(newinfo->entries + newpos);
+				e->counters.pcnt = pos;
+				pos = newpos;
+			}
+		}
+		next:
+		duprintf("Finished chain %u\n", hook);
+	}
+	return 1;
+}
+
+static inline int standard_check(const struct arpt_entry_target *t,
+				 unsigned int max_offset)
+{
+	struct arpt_standard_target *targ = (void *)t;
+
+	/* Check standard info. */
+	if (t->u.target_size
+	    != ARPT_ALIGN(sizeof(struct arpt_standard_target))) {
+		duprintf("arpt_standard_check: target size %u != %Zu\n",
+			 t->u.target_size,
+			 ARPT_ALIGN(sizeof(struct arpt_standard_target)));
+		return 0;
+	}
+
+	if (targ->verdict >= 0
+	    && targ->verdict > max_offset - sizeof(struct arpt_entry)) {
+		duprintf("arpt_standard_check: bad verdict (%i)\n",
+			 targ->verdict);
+		return 0;
+	}
+
+	if (targ->verdict < -NF_MAX_VERDICT - 1) {
+		duprintf("arpt_standard_check: bad negative verdict (%i)\n",
+			 targ->verdict);
+		return 0;
+	}
+	return 1;
+}
+
+static struct arpt_target arpt_standard_target;
+
+static inline int check_entry(struct arpt_entry *e, const char *name, unsigned int size,
+			      unsigned int *i)
+{
+	struct arpt_entry_target *t;
+	struct arpt_target *target;
+	int ret;
+
+	if (!arp_checkentry(&e->arp)) {
+		duprintf("arp_tables: arp check failed %p %s.\n", e, name);
+		return -EINVAL;
+	}
+
+	t = arpt_get_target(e);
+	target = find_target_lock(t->u.user.name, &ret, &arpt_mutex);
+	if (!target) {
+		duprintf("check_entry: `%s' not found\n", t->u.user.name);
+		goto out;
+	}
+	if (target->me)
+		__MOD_INC_USE_COUNT(target->me);
+	t->u.kernel.target = target;
+	up(&arpt_mutex);
+
+	if (t->u.kernel.target == &arpt_standard_target) {
+		if (!standard_check(t, size)) {
+			ret = -EINVAL;
+			goto out;
+		}
+	} else if (t->u.kernel.target->checkentry
+		   && !t->u.kernel.target->checkentry(name, e, t->data,
+						      t->u.target_size
+						      - sizeof(*t),
+						      e->comefrom)) {
+		if (t->u.kernel.target->me)
+			__MOD_DEC_USE_COUNT(t->u.kernel.target->me);
+		duprintf("arp_tables: check failed for `%s'.\n",
+			 t->u.kernel.target->name);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	(*i)++;
+	return 0;
+
+out:
+	return ret;
+}
+
+static inline int check_entry_size_and_hooks(struct arpt_entry *e,
+					     struct arpt_table_info *newinfo,
+					     unsigned char *base,
+					     unsigned char *limit,
+					     const unsigned int *hook_entries,
+					     const unsigned int *underflows,
+					     unsigned int *i)
+{
+	unsigned int h;
+
+	if ((unsigned long)e % __alignof__(struct arpt_entry) != 0
+	    || (unsigned char *)e + sizeof(struct arpt_entry) >= limit) {
+		duprintf("Bad offset %p\n", e);
+		return -EINVAL;
+	}
+
+	if (e->next_offset
+	    < sizeof(struct arpt_entry) + sizeof(struct arpt_entry_target)) {
+		duprintf("checking: element %p size %u\n",
+			 e, e->next_offset);
+		return -EINVAL;
+	}
+
+	/* Check hooks & underflows */
+	for (h = 0; h < NF_ARP_NUMHOOKS; h++) {
+		if ((unsigned char *)e - base == hook_entries[h])
+			newinfo->hook_entry[h] = hook_entries[h];
+		if ((unsigned char *)e - base == underflows[h])
+			newinfo->underflow[h] = underflows[h];
+	}
+
+	/* FIXME: underflows must be unconditional, standard verdicts
+           < 0 (not ARPT_RETURN). --RR */
+
+	/* Clear counters and comefrom */
+	e->counters = ((struct arpt_counters) { 0, 0 });
+	e->comefrom = 0;
+
+	(*i)++;
+	return 0;
+}
+
+static inline int cleanup_entry(struct arpt_entry *e, unsigned int *i)
+{
+	struct arpt_entry_target *t;
+
+	if (i && (*i)-- == 0)
+		return 1;
+
+	t = arpt_get_target(e);
+	if (t->u.kernel.target->destroy)
+		t->u.kernel.target->destroy(t->data,
+					    t->u.target_size - sizeof(*t));
+	if (t->u.kernel.target->me)
+		__MOD_DEC_USE_COUNT(t->u.kernel.target->me);
+
+	return 0;
+}
+
+/* Checks and translates the user-supplied table segment (held in
+ * newinfo).
+ */
+static int translate_table(const char *name,
+			   unsigned int valid_hooks,
+			   struct arpt_table_info *newinfo,
+			   unsigned int size,
+			   unsigned int number,
+			   const unsigned int *hook_entries,
+			   const unsigned int *underflows)
+{
+	unsigned int i;
+	int ret;
+
+	newinfo->size = size;
+	newinfo->number = number;
+
+	/* Init all hooks to impossible value. */
+	for (i = 0; i < NF_ARP_NUMHOOKS; i++) {
+		newinfo->hook_entry[i] = 0xFFFFFFFF;
+		newinfo->underflow[i] = 0xFFFFFFFF;
+	}
+
+	duprintf("translate_table: size %u\n", newinfo->size);
+	i = 0;
+
+	/* Walk through entries, checking offsets. */
+	ret = ARPT_ENTRY_ITERATE(newinfo->entries, newinfo->size,
+				 check_entry_size_and_hooks,
+				 newinfo,
+				 newinfo->entries,
+				 newinfo->entries + size,
+				 hook_entries, underflows, &i);
+	duprintf("translate_table: ARPT_ENTRY_ITERATE gives %d\n", ret);
+	if (ret != 0)
+		return ret;
+
+	if (i != number) {
+		duprintf("translate_table: %u not %u entries\n",
+			 i, number);
+		return -EINVAL;
+	}
+
+	/* Check hooks all assigned */
+	for (i = 0; i < NF_ARP_NUMHOOKS; i++) {
+		/* Only hooks which are valid */
+		if (!(valid_hooks & (1 << i)))
+			continue;
+		if (newinfo->hook_entry[i] == 0xFFFFFFFF) {
+			duprintf("Invalid hook entry %u %u\n",
+				 i, hook_entries[i]);
+			return -EINVAL;
+		}
+		if (newinfo->underflow[i] == 0xFFFFFFFF) {
+			duprintf("Invalid underflow %u %u\n",
+				 i, underflows[i]);
+			return -EINVAL;
+		}
+	}
+
+	if (!mark_source_chains(newinfo, valid_hooks)) {
+		duprintf("Looping hook\n");
+		return -ELOOP;
+	}
+
+	/* Finally, each sanity check must pass */
+	i = 0;
+	ret = ARPT_ENTRY_ITERATE(newinfo->entries, newinfo->size,
+				 check_entry, name, size, &i);
+
+	if (ret != 0) {
+		ARPT_ENTRY_ITERATE(newinfo->entries, newinfo->size,
+				   cleanup_entry, &i);
+		return ret;
+	}
+
+	/* And one copy for every other CPU */
+	for (i = 1; i < smp_num_cpus; i++) {
+		memcpy(newinfo->entries + SMP_ALIGN(newinfo->size)*i,
+		       newinfo->entries,
+		       SMP_ALIGN(newinfo->size));
+	}
+
+	return ret;
+}
+
+static struct arpt_table_info *replace_table(struct arpt_table *table,
+					     unsigned int num_counters,
+					     struct arpt_table_info *newinfo,
+					     int *error)
+{
+	struct arpt_table_info *oldinfo;
+
+	/* Do the substitution. */
+	write_lock_bh(&table->lock);
+	/* Check inside lock: is the old number correct? */
+	if (num_counters != table->private->number) {
+		duprintf("num_counters != table->private->number (%u/%u)\n",
+			 num_counters, table->private->number);
+		write_unlock_bh(&table->lock);
+		*error = -EAGAIN;
+		return NULL;
+	}
+	oldinfo = table->private;
+	table->private = newinfo;
+	newinfo->initial_entries = oldinfo->initial_entries;
+	write_unlock_bh(&table->lock);
+
+	return oldinfo;
+}
+
+/* Gets counters. */
+static inline int add_entry_to_counter(const struct arpt_entry *e,
+				       struct arpt_counters total[],
+				       unsigned int *i)
+{
+	ADD_COUNTER(total[*i], e->counters.bcnt, e->counters.pcnt);
+
+	(*i)++;
+	return 0;
+}
+
+static void get_counters(const struct arpt_table_info *t,
+			 struct arpt_counters counters[])
+{
+	unsigned int cpu;
+	unsigned int i;
+
+	for (cpu = 0; cpu < smp_num_cpus; cpu++) {
+		i = 0;
+		ARPT_ENTRY_ITERATE(t->entries + TABLE_OFFSET(t, cpu),
+				   t->size,
+				   add_entry_to_counter,
+				   counters,
+				   &i);
+	}
+}
+
+static int copy_entries_to_user(unsigned int total_size,
+				struct arpt_table *table,
+				void *userptr)
+{
+	unsigned int off, num, countersize;
+	struct arpt_entry *e;
+	struct arpt_counters *counters;
+	int ret = 0;
+
+	/* We need atomic snapshot of counters: rest doesn't change
+	 * (other than comefrom, which userspace doesn't care
+	 * about).
+	 */
+	countersize = sizeof(struct arpt_counters) * table->private->number;
+	counters = vmalloc(countersize);
+
+	if (counters == NULL)
+		return -ENOMEM;
+
+	/* First, sum counters... */
+	memset(counters, 0, countersize);
+	write_lock_bh(&table->lock);
+	get_counters(table->private, counters);
+	write_unlock_bh(&table->lock);
+
+	/* ... then copy entire thing from CPU 0... */
+	if (copy_to_user(userptr, table->private->entries, total_size) != 0) {
+		ret = -EFAULT;
+		goto free_counters;
+	}
+
+	/* FIXME: use iterator macros --RR */
+	/* ... then go back and fix counters and names */
+	for (off = 0, num = 0; off < total_size; off += e->next_offset, num++){
+		struct arpt_entry_target *t;
+
+		e = (struct arpt_entry *)(table->private->entries + off);
+		if (copy_to_user(userptr + off
+				 + offsetof(struct arpt_entry, counters),
+				 &counters[num],
+				 sizeof(counters[num])) != 0) {
+			ret = -EFAULT;
+			goto free_counters;
+		}
+
+		t = arpt_get_target(e);
+		if (copy_to_user(userptr + off + e->target_offset
+				 + offsetof(struct arpt_entry_target,
+					    u.user.name),
+				 t->u.kernel.target->name,
+				 strlen(t->u.kernel.target->name)+1) != 0) {
+			ret = -EFAULT;
+			goto free_counters;
+		}
+	}
+
+ free_counters:
+	vfree(counters);
+	return ret;
+}
+
+static int get_entries(const struct arpt_get_entries *entries,
+		       struct arpt_get_entries *uptr)
+{
+	int ret;
+	struct arpt_table *t;
+
+	t = find_table_lock(entries->name, &ret, &arpt_mutex);
+	if (t) {
+		duprintf("t->private->number = %u\n",
+			 t->private->number);
+		if (entries->size == t->private->size)
+			ret = copy_entries_to_user(t->private->size,
+						   t, uptr->entrytable);
+		else {
+			duprintf("get_entries: I've got %u not %u!\n",
+				 t->private->size,
+				 entries->size);
+			ret = -EINVAL;
+		}
+		up(&arpt_mutex);
+	} else
+		duprintf("get_entries: Can't find %s!\n",
+			 entries->name);
+
+	return ret;
+}
+
+static int do_replace(void *user, unsigned int len)
+{
+	int ret;
+	struct arpt_replace tmp;
+	struct arpt_table *t;
+	struct arpt_table_info *newinfo, *oldinfo;
+	struct arpt_counters *counters;
+
+	if (copy_from_user(&tmp, user, sizeof(tmp)) != 0)
+		return -EFAULT;
+
+	/* Hack: Causes ipchains to give correct error msg --RR */
+	if (len != sizeof(tmp) + tmp.size)
+		return -ENOPROTOOPT;
+
+	/* Pedantry: prevent them from hitting BUG() in vmalloc.c --RR */
+	if ((SMP_ALIGN(tmp.size) >> PAGE_SHIFT) + 2 > num_physpages)
+		return -ENOMEM;
+
+	newinfo = vmalloc(sizeof(struct arpt_table_info)
+			  + SMP_ALIGN(tmp.size) * smp_num_cpus);
+	if (!newinfo)
+		return -ENOMEM;
+
+	if (copy_from_user(newinfo->entries, user + sizeof(tmp),
+			   tmp.size) != 0) {
+		ret = -EFAULT;
+		goto free_newinfo;
+	}
+
+	counters = vmalloc(tmp.num_counters * sizeof(struct arpt_counters));
+	if (!counters) {
+		ret = -ENOMEM;
+		goto free_newinfo;
+	}
+	memset(counters, 0, tmp.num_counters * sizeof(struct arpt_counters));
+
+	ret = translate_table(tmp.name, tmp.valid_hooks,
+			      newinfo, tmp.size, tmp.num_entries,
+			      tmp.hook_entry, tmp.underflow);
+	if (ret != 0)
+		goto free_newinfo_counters;
+
+	duprintf("arp_tables: Translated table\n");
+
+	t = find_table_lock(tmp.name, &ret, &arpt_mutex);
+	if (!t)
+		goto free_newinfo_counters_untrans;
+
+	/* You lied! */
+	if (tmp.valid_hooks != t->valid_hooks) {
+		duprintf("Valid hook crap: %08X vs %08X\n",
+			 tmp.valid_hooks, t->valid_hooks);
+		ret = -EINVAL;
+		goto free_newinfo_counters_untrans_unlock;
+	}
+
+	oldinfo = replace_table(t, tmp.num_counters, newinfo, &ret);
+	if (!oldinfo)
+		goto free_newinfo_counters_untrans_unlock;
+
+	/* Update module usage count based on number of rules */
+	duprintf("do_replace: oldnum=%u, initnum=%u, newnum=%u\n",
+		oldinfo->number, oldinfo->initial_entries, newinfo->number);
+	if (t->me && (oldinfo->number <= oldinfo->initial_entries) &&
+ 	    (newinfo->number > oldinfo->initial_entries))
+		__MOD_INC_USE_COUNT(t->me);
+	else if (t->me && (oldinfo->number > oldinfo->initial_entries) &&
+	 	 (newinfo->number <= oldinfo->initial_entries))
+		__MOD_DEC_USE_COUNT(t->me);
+
+	/* Get the old counters. */
+	get_counters(oldinfo, counters);
+	/* Decrease module usage counts and free resource */
+	ARPT_ENTRY_ITERATE(oldinfo->entries, oldinfo->size, cleanup_entry,NULL);
+	vfree(oldinfo);
+	/* Silent error: too late now. */
+	copy_to_user(tmp.counters, counters,
+		     sizeof(struct arpt_counters) * tmp.num_counters);
+	vfree(counters);
+	up(&arpt_mutex);
+	return 0;
+
+ free_newinfo_counters_untrans_unlock:
+	up(&arpt_mutex);
+ free_newinfo_counters_untrans:
+	ARPT_ENTRY_ITERATE(newinfo->entries, newinfo->size, cleanup_entry, NULL);
+ free_newinfo_counters:
+	vfree(counters);
+ free_newinfo:
+	vfree(newinfo);
+	return ret;
+}
+
+/* We're lazy, and add to the first CPU; overflow works its fey magic
+ * and everything is OK.
+ */
+static inline int add_counter_to_entry(struct arpt_entry *e,
+				       const struct arpt_counters addme[],
+				       unsigned int *i)
+{
+
+	ADD_COUNTER(e->counters, addme[*i].bcnt, addme[*i].pcnt);
+
+	(*i)++;
+	return 0;
+}
+
+static int do_add_counters(void *user, unsigned int len)
+{
+	unsigned int i;
+	struct arpt_counters_info tmp, *paddc;
+	struct arpt_table *t;
+	int ret;
+
+	if (copy_from_user(&tmp, user, sizeof(tmp)) != 0)
+		return -EFAULT;
+
+	if (len != sizeof(tmp) + tmp.num_counters*sizeof(struct arpt_counters))
+		return -EINVAL;
+
+	paddc = vmalloc(len);
+	if (!paddc)
+		return -ENOMEM;
+
+	if (copy_from_user(paddc, user, len) != 0) {
+		ret = -EFAULT;
+		goto free;
+	}
+
+	t = find_table_lock(tmp.name, &ret, &arpt_mutex);
+	if (!t)
+		goto free;
+
+	write_lock_bh(&t->lock);
+	if (t->private->number != paddc->num_counters) {
+		ret = -EINVAL;
+		goto unlock_up_free;
+	}
+
+	i = 0;
+	ARPT_ENTRY_ITERATE(t->private->entries,
+			   t->private->size,
+			   add_counter_to_entry,
+			   paddc->counters,
+			   &i);
+ unlock_up_free:
+	write_unlock_bh(&t->lock);
+	up(&arpt_mutex);
+ free:
+	vfree(paddc);
+
+	return ret;
+}
+
+static int do_arpt_set_ctl(struct sock *sk, int cmd, void *user, unsigned int len)
+{
+	int ret;
+
+	if (!capable(CAP_NET_ADMIN))
+		return -EPERM;
+
+	switch (cmd) {
+	case ARPT_SO_SET_REPLACE:
+		ret = do_replace(user, len);
+		break;
+
+	case ARPT_SO_SET_ADD_COUNTERS:
+		ret = do_add_counters(user, len);
+		break;
+
+	default:
+		duprintf("do_arpt_set_ctl:  unknown request %i\n", cmd);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int do_arpt_get_ctl(struct sock *sk, int cmd, void *user, int *len)
+{
+	int ret;
+
+	if (!capable(CAP_NET_ADMIN))
+		return -EPERM;
+
+	switch (cmd) {
+	case ARPT_SO_GET_INFO: {
+		char name[ARPT_TABLE_MAXNAMELEN];
+		struct arpt_table *t;
+
+		if (*len != sizeof(struct arpt_getinfo)) {
+			duprintf("length %u != %Zu\n", *len,
+				 sizeof(struct arpt_getinfo));
+			ret = -EINVAL;
+			break;
+		}
+
+		if (copy_from_user(name, user, sizeof(name)) != 0) {
+			ret = -EFAULT;
+			break;
+		}
+		name[ARPT_TABLE_MAXNAMELEN-1] = '\0';
+		t = find_table_lock(name, &ret, &arpt_mutex);
+		if (t) {
+			struct arpt_getinfo info;
+
+			info.valid_hooks = t->valid_hooks;
+			memcpy(info.hook_entry, t->private->hook_entry,
+			       sizeof(info.hook_entry));
+			memcpy(info.underflow, t->private->underflow,
+			       sizeof(info.underflow));
+			info.num_entries = t->private->number;
+			info.size = t->private->size;
+			strcpy(info.name, name);
+
+			if (copy_to_user(user, &info, *len) != 0)
+				ret = -EFAULT;
+			else
+				ret = 0;
+
+			up(&arpt_mutex);
+		}
+	}
+	break;
+
+	case ARPT_SO_GET_ENTRIES: {
+		struct arpt_get_entries get;
+
+		if (*len < sizeof(get)) {
+			duprintf("get_entries: %u < %Zu\n", *len, sizeof(get));
+			ret = -EINVAL;
+		} else if (copy_from_user(&get, user, sizeof(get)) != 0) {
+			ret = -EFAULT;
+		} else if (*len != sizeof(struct arpt_get_entries) + get.size) {
+			duprintf("get_entries: %u != %Zu\n", *len,
+				 sizeof(struct arpt_get_entries) + get.size);
+			ret = -EINVAL;
+		} else
+			ret = get_entries(&get, user);
+		break;
+	}
+
+	default:
+		duprintf("do_arpt_get_ctl: unknown request %i\n", cmd);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+/* Registration hooks for targets. */
+int arpt_register_target(struct arpt_target *target)
+{
+	int ret;
+
+	MOD_INC_USE_COUNT;
+	ret = down_interruptible(&arpt_mutex);
+	if (ret != 0) {
+		MOD_DEC_USE_COUNT;
+		return ret;
+	}
+	if (!list_named_insert(&arpt_target, target)) {
+		duprintf("arpt_register_target: `%s' already in list!\n",
+			 target->name);
+		ret = -EINVAL;
+		MOD_DEC_USE_COUNT;
+	}
+	up(&arpt_mutex);
+	return ret;
+}
+
+void arpt_unregister_target(struct arpt_target *target)
+{
+	down(&arpt_mutex);
+	LIST_DELETE(&arpt_target, target);
+	up(&arpt_mutex);
+	MOD_DEC_USE_COUNT;
+}
+
+int arpt_register_table(struct arpt_table *table)
+{
+	int ret;
+	struct arpt_table_info *newinfo;
+	static struct arpt_table_info bootstrap
+		= { 0, 0, 0, { 0 }, { 0 }, { } };
+
+	MOD_INC_USE_COUNT;
+	newinfo = vmalloc(sizeof(struct arpt_table_info)
+			  + SMP_ALIGN(table->table->size) * smp_num_cpus);
+	if (!newinfo) {
+		ret = -ENOMEM;
+		MOD_DEC_USE_COUNT;
+		return ret;
+	}
+	memcpy(newinfo->entries, table->table->entries, table->table->size);
+
+	ret = translate_table(table->name, table->valid_hooks,
+			      newinfo, table->table->size,
+			      table->table->num_entries,
+			      table->table->hook_entry,
+			      table->table->underflow);
+	duprintf("arpt_register_table: translate table gives %d\n", ret);
+	if (ret != 0) {
+		vfree(newinfo);
+		MOD_DEC_USE_COUNT;
+		return ret;
+	}
+
+	ret = down_interruptible(&arpt_mutex);
+	if (ret != 0) {
+		vfree(newinfo);
+		MOD_DEC_USE_COUNT;
+		return ret;
+	}
+
+	/* Don't autoload: we'd eat our tail... */
+	if (list_named_find(&arpt_tables, table->name)) {
+		ret = -EEXIST;
+		goto free_unlock;
+	}
+
+	/* Simplifies replace_table code. */
+	table->private = &bootstrap;
+	if (!replace_table(table, 0, newinfo, &ret))
+		goto free_unlock;
+
+	duprintf("table->private->number = %u\n",
+		 table->private->number);
+	
+	/* save number of initial entries */
+	table->private->initial_entries = table->private->number;
+
+	table->lock = RW_LOCK_UNLOCKED;
+	list_prepend(&arpt_tables, table);
+
+ unlock:
+	up(&arpt_mutex);
+	return ret;
+
+ free_unlock:
+	vfree(newinfo);
+	MOD_DEC_USE_COUNT;
+	goto unlock;
+}
+
+void arpt_unregister_table(struct arpt_table *table)
+{
+	down(&arpt_mutex);
+	LIST_DELETE(&arpt_tables, table);
+	up(&arpt_mutex);
+
+	/* Decrease module usage counts and free resources */
+	ARPT_ENTRY_ITERATE(table->private->entries, table->private->size,
+			   cleanup_entry, NULL);
+	vfree(table->private);
+	MOD_DEC_USE_COUNT;
+}
+
+/* The built-in targets: standard (NULL) and error. */
+static struct arpt_target arpt_standard_target
+= { { NULL, NULL }, ARPT_STANDARD_TARGET, NULL, NULL, NULL };
+static struct arpt_target arpt_error_target
+= { { NULL, NULL }, ARPT_ERROR_TARGET, arpt_error, NULL, NULL };
+
+static struct nf_sockopt_ops arpt_sockopts
+= { { NULL, NULL }, PF_INET, ARPT_BASE_CTL, ARPT_SO_SET_MAX+1, do_arpt_set_ctl,
+    ARPT_BASE_CTL, ARPT_SO_GET_MAX+1, do_arpt_get_ctl, 0, NULL  };
+
+#ifdef CONFIG_PROC_FS
+static inline int print_name(const struct arpt_table *t,
+			     off_t start_offset, char *buffer, int length,
+			     off_t *pos, unsigned int *count)
+{
+	if ((*count)++ >= start_offset) {
+		unsigned int namelen;
+
+		namelen = sprintf(buffer + *pos, "%s\n", t->name);
+		if (*pos + namelen > length) {
+			/* Stop iterating */
+			return 1;
+		}
+		*pos += namelen;
+	}
+	return 0;
+}
+
+static int arpt_get_tables(char *buffer, char **start, off_t offset, int length)
+{
+	off_t pos = 0;
+	unsigned int count = 0;
+
+	if (down_interruptible(&arpt_mutex) != 0)
+		return 0;
+
+	LIST_FIND(&arpt_tables, print_name, struct arpt_table *,
+		  offset, buffer, length, &pos, &count);
+
+	up(&arpt_mutex);
+
+	/* `start' hack - see fs/proc/generic.c line ~105 */
+	*start=(char *)((unsigned long)count-offset);
+	return pos;
+}
+#endif /*CONFIG_PROC_FS*/
+
+static int __init init(void)
+{
+	int ret;
+
+	/* Noone else will be downing sem now, so we won't sleep */
+	down(&arpt_mutex);
+	list_append(&arpt_target, &arpt_standard_target);
+	list_append(&arpt_target, &arpt_error_target);
+	up(&arpt_mutex);
+
+	/* Register setsockopt */
+	ret = nf_register_sockopt(&arpt_sockopts);
+	if (ret < 0) {
+		duprintf("Unable to register sockopts.\n");
+		return ret;
+	}
+
+#ifdef CONFIG_PROC_FS
+	{
+		struct proc_dir_entry *proc;
+
+		proc = proc_net_create("arp_tables_names", 0, arpt_get_tables);
+		if (!proc) {
+			nf_unregister_sockopt(&arpt_sockopts);
+			return -ENOMEM;
+		}
+		proc->owner = THIS_MODULE;
+	}
+#endif
+
+	printk("arp_tables: (C) 2002 David S. Miller\n");
+	return 0;
+}
+
+static void __exit fini(void)
+{
+	nf_unregister_sockopt(&arpt_sockopts);
+#ifdef CONFIG_PROC_FS
+	proc_net_remove("arp_tables_names");
+#endif
+}
+
+EXPORT_SYMBOL(arpt_register_table);
+EXPORT_SYMBOL(arpt_unregister_table);
+EXPORT_SYMBOL(arpt_do_table);
+EXPORT_SYMBOL(arpt_register_target);
+EXPORT_SYMBOL(arpt_unregister_target);
+
+module_init(init);
+module_exit(fini);
+MODULE_LICENSE("GPL");
diff -Nru a/net/ipv4/netfilter/arptable_filter.c b/net/ipv4/netfilter/arptable_filter.c
--- /dev/null	Wed Dec 31 16:00:00 1969
+++ b/net/ipv4/netfilter/arptable_filter.c	Fri Mar 15 17:51:04 2002
@@ -0,0 +1,174 @@
+/*
+ * Filtering ARP tables module.
+ *
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/netfilter_arp/arp_tables.h>
+
+#define FILTER_VALID_HOOKS ((1 << NF_ARP_IN) | (1 << NF_ARP_OUT))
+
+/* Standard entry. */
+struct arpt_standard
+{
+	struct arpt_entry entry;
+	struct arpt_standard_target target;
+};
+
+struct arpt_error_target
+{
+	struct arpt_entry_target target;
+	char errorname[ARPT_FUNCTION_MAXNAMELEN];
+};
+
+struct arpt_error
+{
+	struct arpt_entry entry;
+	struct arpt_error_target target;
+};
+
+static struct
+{
+	struct arpt_replace repl;
+	struct arpt_standard entries[2];
+	struct arpt_error term;
+} initial_table __initdata
+= { { "filter", FILTER_VALID_HOOKS, 3,
+      sizeof(struct arpt_standard) * 2 + sizeof(struct arpt_error),
+      { [NF_ARP_IN] 0,
+	[NF_ARP_OUT] sizeof(struct arpt_standard) },
+      { [NF_ARP_IN] 0,
+	[NF_ARP_OUT] sizeof(struct arpt_standard), },
+      0, NULL, { } },
+    {
+	    /* ARP_IN */
+	    {
+		    {
+			    {
+				    { 0 }, { 0 }, { 0 }, { 0 },
+				    0, 0,
+				    { { 0, }, { 0, } },
+				    { { 0, }, { 0, } },
+				    0, 0,
+				    0, 0,
+				    0, 0,
+				    "", "", { 0 }, { 0 },
+				    0, 0
+			    },
+			    sizeof(struct arpt_entry),
+			    sizeof(struct arpt_standard),
+			    0,
+			    { 0, 0 }, { } },
+		    { { { { ARPT_ALIGN(sizeof(struct arpt_standard_target)), "" } }, { } },
+		      -NF_ACCEPT - 1 }
+	    },
+	    /* ARP_OUT */
+	    {
+		    {
+			    {
+				    { 0 }, { 0 }, { 0 }, { 0 },
+				    0, 0,
+				    { { 0, }, { 0, } },
+				    { { 0, }, { 0, } },
+				    0, 0,
+				    0, 0,
+				    0, 0,
+				    "", "", { 0 }, { 0 },
+				    0, 0
+			    },
+			    sizeof(struct arpt_entry),
+			    sizeof(struct arpt_standard),
+			    0,
+			    { 0, 0 }, { } },
+		    { { { { ARPT_ALIGN(sizeof(struct arpt_standard_target)), "" } }, { } },
+		      -NF_ACCEPT - 1 }
+	    }
+    },
+    /* ERROR */
+    {
+	    {
+		    {
+			    { 0 }, { 0 }, { 0 }, { 0 },
+			    0, 0,
+			    { { 0, }, { 0, } },
+			    { { 0, }, { 0, } },
+			    0, 0,
+			    0, 0,
+			    0, 0,
+			    "", "", { 0 }, { 0 },
+			    0, 0
+		    },
+		    sizeof(struct arpt_entry),
+		    sizeof(struct arpt_error),
+		    0,
+		    { 0, 0 }, { } },
+	    { { { { ARPT_ALIGN(sizeof(struct arpt_error_target)), ARPT_ERROR_TARGET } },
+		{ } },
+	      "ERROR"
+	    }
+    }
+};
+
+static struct arpt_table packet_filter
+= { { NULL, NULL }, "filter", &initial_table.repl,
+    FILTER_VALID_HOOKS, RW_LOCK_UNLOCKED, NULL, THIS_MODULE };
+
+/* The work comes in here from netfilter.c */
+static unsigned int arpt_hook(unsigned int hook,
+			      struct sk_buff **pskb,
+			      const struct net_device *in,
+			      const struct net_device *out,
+			      int (*okfn)(struct sk_buff *))
+{
+	return arpt_do_table(pskb, hook, in, out, &packet_filter, NULL);
+}
+
+static struct nf_hook_ops arpt_ops[]
+= { { { NULL, NULL }, arpt_hook, NF_ARP, NF_ARP_IN, 0 },
+    { { NULL, NULL }, arpt_hook, NF_ARP, NF_ARP_OUT, 0 }
+};
+
+static int __init init(void)
+{
+	int ret;
+
+	/* Register table */
+	ret = arpt_register_table(&packet_filter);
+	if (ret < 0)
+		return ret;
+
+	/* Register hooks */
+	ret = nf_register_hook(&arpt_ops[0]);
+	if (ret < 0)
+		goto cleanup_table;
+
+	ret = nf_register_hook(&arpt_ops[1]);
+	if (ret < 0)
+		goto cleanup_hook0;
+
+	return ret;
+
+cleanup_hook0:
+	nf_unregister_hook(&arpt_ops[0]);
+
+cleanup_table:
+	arpt_unregister_table(&packet_filter);
+
+	return ret;
+}
+
+static void __exit fini(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < sizeof(arpt_ops)/sizeof(struct nf_hook_ops); i++)
+		nf_unregister_hook(&arpt_ops[i]);
+
+	arpt_unregister_table(&packet_filter);
+}
+
+module_init(init);
+module_exit(fini);
+MODULE_LICENSE("GPL");
diff -Nru a/net/ipv4/netfilter/ip_conntrack_core.c b/net/ipv4/netfilter/ip_conntrack_core.c
--- a/net/ipv4/netfilter/ip_conntrack_core.c	Fri Mar 15 17:51:00 2002
+++ b/net/ipv4/netfilter/ip_conntrack_core.c	Fri Mar 15 17:51:00 2002
@@ -969,9 +969,12 @@
 static int
 getorigdst(struct sock *sk, int optval, void *user, int *len)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct ip_conntrack_tuple_hash *h;
-	struct ip_conntrack_tuple tuple = { { sk->rcv_saddr, { sk->sport } },
-					    { sk->daddr, { sk->dport },
+	struct ip_conntrack_tuple tuple = { { inet->rcv_saddr,
+						{ inet->sport } },
+					    { inet->daddr,
+						{ inet->dport },
 					      IPPROTO_TCP } };
 
 	/* We only do TCP at the moment: is there a better way? */
diff -Nru a/net/ipv4/netfilter/ip_conntrack_standalone.c b/net/ipv4/netfilter/ip_conntrack_standalone.c
--- a/net/ipv4/netfilter/ip_conntrack_standalone.c	Fri Mar 15 17:51:03 2002
+++ b/net/ipv4/netfilter/ip_conntrack_standalone.c	Fri Mar 15 17:51:03 2002
@@ -15,6 +15,7 @@
 #include <linux/skbuff.h>
 #include <linux/proc_fs.h>
 #include <linux/version.h>
+#include <linux/brlock.h>
 #include <net/checksum.h>
 
 #define ASSERT_READ_LOCK(x) MUST_BE_READ_LOCKED(&ip_conntrack_lock)
@@ -35,6 +36,11 @@
 struct module *ip_conntrack_module = THIS_MODULE;
 MODULE_LICENSE("GPL");
 
+static int kill_proto(const struct ip_conntrack *i, void *data)
+{
+	return (i->tuplehash[IP_CT_DIR_ORIGINAL].dst.protonum == 
+			*((u_int8_t *) data));
+}
 
 static unsigned int
 print_tuple(char *buffer, const struct ip_conntrack_tuple *tuple,
@@ -304,12 +310,24 @@
 	return ret;
 }
 
-/* FIXME: Implement this --RR */
-#if 0
 void ip_conntrack_protocol_unregister(struct ip_conntrack_protocol *proto)
 {
+	WRITE_LOCK(&ip_conntrack_lock);
+
+	/* find_proto() returns proto_generic in case there is no protocol 
+	 * helper. So this should be enough - HW */
+	LIST_DELETE(&protocol_list, proto);
+	WRITE_UNLOCK(&ip_conntrack_lock);
+	
+	/* Somebody could be still looking at the proto in bh. */
+	br_write_lock_bh(BR_NETPROTO_LOCK);
+	br_write_unlock_bh(BR_NETPROTO_LOCK);
+
+	/* Remove all contrack entries for this protocol */
+	ip_ct_selective_cleanup(kill_proto, &proto->proto);
+
+	MOD_DEC_USE_COUNT;
 }
-#endif
 
 static int __init init(void)
 {
@@ -325,6 +343,7 @@
 module_exit(fini);
 
 EXPORT_SYMBOL(ip_conntrack_protocol_register);
+EXPORT_SYMBOL(ip_conntrack_protocol_unregister);
 EXPORT_SYMBOL(invert_tuplepr);
 EXPORT_SYMBOL(ip_conntrack_alter_reply);
 EXPORT_SYMBOL(ip_conntrack_destroyed);
@@ -335,6 +354,7 @@
 EXPORT_SYMBOL(ip_ct_selective_cleanup);
 EXPORT_SYMBOL(ip_ct_refresh);
 EXPORT_SYMBOL(ip_conntrack_expect_related);
+EXPORT_SYMBOL(ip_conntrack_unexpect_related);
 EXPORT_SYMBOL(ip_conntrack_tuple_taken);
 EXPORT_SYMBOL(ip_ct_gather_frags);
 EXPORT_SYMBOL(ip_conntrack_htable_size);
diff -Nru a/net/ipv4/netfilter/ip_nat_core.c b/net/ipv4/netfilter/ip_nat_core.c
--- a/net/ipv4/netfilter/ip_nat_core.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv4/netfilter/ip_nat_core.c	Fri Mar 15 17:51:01 2002
@@ -314,6 +314,7 @@
 			 * do_extra_mangle last time. */
 			*other_ipp = saved_ip;
 
+#ifdef CONFIG_IP_NF_NAT_LOCAL
 			if (hooknum == NF_IP_LOCAL_OUT
 			    && *var_ipp != orig_dstip
 			    && !do_extra_mangle(*var_ipp, other_ipp)) {
@@ -324,6 +325,7 @@
 				 * anyway. */
 				continue;
 			}
+#endif
 
 			/* Count how many others map onto this. */
 			score = count_maps(tuple->src.ip, tuple->dst.ip,
@@ -367,11 +369,13 @@
 		else {
 			/* Only do extra mangle when required (breaks
                            socket binding) */
+#ifdef CONFIG_IP_NF_NAT_LOCAL
 			if (tuple->dst.ip != mr->range[0].min_ip
 			    && hooknum == NF_IP_LOCAL_OUT
 			    && !do_extra_mangle(mr->range[0].min_ip,
 						&tuple->src.ip))
 				return NULL;
+#endif
 			tuple->dst.ip = mr->range[0].min_ip;
 		}
 	}
@@ -494,7 +498,10 @@
 static unsigned int opposite_hook[NF_IP_NUMHOOKS]
 = { [NF_IP_PRE_ROUTING] = NF_IP_POST_ROUTING,
     [NF_IP_POST_ROUTING] = NF_IP_PRE_ROUTING,
-    [NF_IP_LOCAL_OUT] = NF_IP_POST_ROUTING
+#ifdef CONFIG_IP_NF_NAT_LOCAL
+    [NF_IP_LOCAL_OUT] = NF_IP_LOCAL_IN,
+    [NF_IP_LOCAL_IN] = NF_IP_LOCAL_OUT,
+#endif
 };
 
 unsigned int
diff -Nru a/net/ipv4/netfilter/ip_nat_rule.c b/net/ipv4/netfilter/ip_nat_rule.c
--- a/net/ipv4/netfilter/ip_nat_rule.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/netfilter/ip_nat_rule.c	Fri Mar 15 17:51:02 2002
@@ -140,8 +140,12 @@
 	struct ip_conntrack *ct;
 	enum ip_conntrack_info ctinfo;
 
+#ifdef CONFIG_IP_NF_NAT_LOCAL
 	IP_NF_ASSERT(hooknum == NF_IP_PRE_ROUTING
 		     || hooknum == NF_IP_LOCAL_OUT);
+#else
+	IP_NF_ASSERT(hooknum == NF_IP_PRE_ROUTING);
+#endif
 
 	ct = ip_conntrack_get(*pskb, &ctinfo);
 
@@ -210,7 +214,7 @@
 
 	/* Only allow these for NAT. */
 	if (strcmp(tablename, "nat") != 0) {
-		DEBUGP("SNAT: wrong table %s\n", tablename);
+		DEBUGP("DNAT: wrong table %s\n", tablename);
 		return 0;
 	}
 
@@ -218,6 +222,14 @@
 		DEBUGP("DNAT: hook mask 0x%x bad\n", hook_mask);
 		return 0;
 	}
+	
+#ifndef CONFIG_IP_NF_NAT_LOCAL
+	if (hook_mask & (1 << NF_IP_LOCAL_OUT)) {
+		DEBUGP("DNAT: CONFIG_IP_NF_NAT_LOCAL not enabled\n");
+		return 0;
+	}
+#endif
+
 	return 1;
 }
 
diff -Nru a/net/ipv4/netfilter/ip_nat_standalone.c b/net/ipv4/netfilter/ip_nat_standalone.c
--- a/net/ipv4/netfilter/ip_nat_standalone.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/netfilter/ip_nat_standalone.c	Fri Mar 15 17:51:02 2002
@@ -42,7 +42,8 @@
 #define HOOKNAME(hooknum) ((hooknum) == NF_IP_POST_ROUTING ? "POST_ROUTING"  \
 			   : ((hooknum) == NF_IP_PRE_ROUTING ? "PRE_ROUTING" \
 			      : ((hooknum) == NF_IP_LOCAL_OUT ? "LOCAL_OUT"  \
-				 : "*ERROR*")))
+			         : ((hooknum) == NF_IP_LOCAL_IN ? "LOCAL_IN"  \
+				    : "*ERROR*")))
 
 static unsigned int
 ip_nat_fn(unsigned int hooknum,
@@ -95,6 +96,12 @@
 		}
 		/* Fall thru... (Only ICMPs can be IP_CT_IS_REPLY) */
 	case IP_CT_NEW:
+#ifdef CONFIG_IP_NF_NAT_LOCAL
+		/* LOCAL_IN hook doesn't have a chain and thus doesn't care
+		 * about new packets -HW */
+		if (hooknum == NF_IP_LOCAL_IN)
+			return NF_ACCEPT;
+#endif
 		info = &ct->nat.info;
 
 		WRITE_LOCK(&ip_nat_lock);
@@ -205,6 +212,11 @@
 static struct nf_hook_ops ip_nat_local_out_ops
 = { { NULL, NULL }, ip_nat_local_fn, PF_INET, NF_IP_LOCAL_OUT, NF_IP_PRI_NAT_DST };
 
+#ifdef CONFIG_IP_NF_NAT_LOCAL
+static struct nf_hook_ops ip_nat_local_in_ops
+= { { NULL, NULL }, ip_nat_fn, PF_INET, NF_IP_LOCAL_IN, NF_IP_PRI_NAT_SRC };
+#endif
+
 /* Protocol registration. */
 int ip_nat_protocol_register(struct ip_nat_protocol *proto)
 {
@@ -273,6 +285,13 @@
 		printk("ip_nat_init: can't register local out hook.\n");
 		goto cleanup_outops;
 	}
+#ifdef CONFIG_IP_NF_NAT_LOCAL
+	ret = nf_register_hook(&ip_nat_local_in_ops);
+	if (ret < 0) {
+		printk("ip_nat_init: can't register local in hook.\n");
+		goto cleanup_localoutops;
+	}
+#endif
 	if (ip_conntrack_module)
 		__MOD_INC_USE_COUNT(ip_conntrack_module);
 	return ret;
@@ -280,6 +299,10 @@
  cleanup:
 	if (ip_conntrack_module)
 		__MOD_DEC_USE_COUNT(ip_conntrack_module);
+#ifdef CONFIG_IP_NF_NAT_LOCAL
+	nf_unregister_hook(&ip_nat_local_in_ops);
+ cleanup_localoutops:
+#endif
 	nf_unregister_hook(&ip_nat_local_out_ops);
  cleanup_outops:
 	nf_unregister_hook(&ip_nat_out_ops);
@@ -308,6 +331,8 @@
 module_exit(fini);
 
 EXPORT_SYMBOL(ip_nat_setup_info);
+EXPORT_SYMBOL(ip_nat_protocol_register);
+EXPORT_SYMBOL(ip_nat_protocol_unregister);
 EXPORT_SYMBOL(ip_nat_helper_register);
 EXPORT_SYMBOL(ip_nat_helper_unregister);
 EXPORT_SYMBOL(ip_nat_expect_register);
@@ -316,4 +341,5 @@
 EXPORT_SYMBOL(ip_nat_mangle_tcp_packet);
 EXPORT_SYMBOL(ip_nat_seq_adjust);
 EXPORT_SYMBOL(ip_nat_delete_sack);
+EXPORT_SYMBOL(ip_nat_used_tuple);
 MODULE_LICENSE("GPL");
diff -Nru a/net/ipv4/netfilter/ipt_REJECT.c b/net/ipv4/netfilter/ipt_REJECT.c
--- a/net/ipv4/netfilter/ipt_REJECT.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/netfilter/ipt_REJECT.c	Fri Mar 15 17:51:02 2002
@@ -234,11 +234,8 @@
 	iph->tos=tos;
 	iph->tot_len = htons(length);
 
-	/* This abbreviates icmp->send->ip_build_xmit->ip_dont_fragment */
-	if (!ipv4_config.no_pmtu_disc
-	    && !(rt->u.dst.mxlock&(1<<RTAX_MTU)))
-		iph->frag_off = htons(IP_DF);
-	else iph->frag_off = 0;
+	/* PMTU discovery never applies to ICMP packets. */
+	iph->frag_off = 0;
 
 	iph->ttl = MAXTTL;
 	ip_select_ident(iph, &rt->u.dst, NULL);
diff -Nru a/net/ipv4/raw.c b/net/ipv4/raw.c
--- a/net/ipv4/raw.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv4/raw.c	Fri Mar 15 17:51:01 2002
@@ -70,7 +70,8 @@
 
 static void raw_v4_hash(struct sock *sk)
 {
-	struct sock **skp = &raw_v4_htable[sk->num & (RAWV4_HTABLE_SIZE - 1)];
+	struct sock **skp = &raw_v4_htable[inet_sk(sk)->num &
+					   (RAWV4_HTABLE_SIZE - 1)];
 
 	write_lock_bh(&raw_v4_lock);
 	if ((sk->next = *skp) != NULL)
@@ -103,9 +104,11 @@
 	struct sock *s = sk;
 
 	for (s = sk; s; s = s->next) {
-		if (s->num == num 				&&
-		    !(s->daddr && s->daddr != raddr) 		&&
-		    !(s->rcv_saddr && s->rcv_saddr != laddr)	&&
+		struct inet_opt *inet = inet_sk(s);
+
+		if (inet->num == num 					&&
+		    !(inet->daddr && inet->daddr != raddr) 		&&
+		    !(inet->rcv_saddr && inet->rcv_saddr != laddr)	&&
 		    !(s->bound_dev_if && s->bound_dev_if != dif))
 			break; /* gotcha */
 	}
@@ -364,10 +367,10 @@
 		err = -EINVAL;
 		if (sk->state != TCP_ESTABLISHED) 
 			goto out;
-		daddr = sk->daddr;
+		daddr = inet->daddr;
 	}
 
-	ipc.addr = sk->saddr;
+	ipc.addr = inet->saddr;
 	ipc.opt = NULL;
 	ipc.oif = sk->bound_dev_if;
 
@@ -458,6 +461,7 @@
 /* This gets rid of all the nasties in af_inet. -DaveM */
 static int raw_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct sockaddr_in *addr = (struct sockaddr_in *) uaddr;
 	int ret = -EINVAL;
 	int chk_addr_ret;
@@ -469,9 +473,9 @@
 	if (addr->sin_addr.s_addr && chk_addr_ret != RTN_LOCAL &&
 	    chk_addr_ret != RTN_MULTICAST && chk_addr_ret != RTN_BROADCAST)
 		goto out;
-	sk->rcv_saddr = sk->saddr = addr->sin_addr.s_addr;
+	inet->rcv_saddr = inet->saddr = addr->sin_addr.s_addr;
 	if (chk_addr_ret == RTN_MULTICAST || chk_addr_ret == RTN_BROADCAST)
-		sk->saddr = 0;  /* Use device */
+		inet->saddr = 0;  /* Use device */
 	sk_dst_reset(sk);
 	ret = 0;
 out:	return ret;
@@ -534,7 +538,7 @@
 static int raw_init(struct sock *sk)
 {
 	struct raw_opt *tp = raw4_sk(sk);
-	if (sk->num == IPPROTO_ICMP)
+	if (inet_sk(sk)->num == IPPROTO_ICMP)
 		memset(&tp->filter, 0, sizeof(tp->filter));
 	return 0;
 }
@@ -574,7 +578,7 @@
 		return ip_setsockopt(sk, level, optname, optval, optlen);
 
 	if (optname == ICMP_FILTER) {
-		if (sk->num != IPPROTO_ICMP)
+		if (inet_sk(sk)->num != IPPROTO_ICMP)
 			return -EOPNOTSUPP;
 		else
 			return raw_seticmpfilter(sk, optval, optlen);
@@ -589,7 +593,7 @@
 		return ip_getsockopt(sk, level, optname, optval, optlen);
 
 	if (optname == ICMP_FILTER) {
-		if (sk->num != IPPROTO_ICMP)
+		if (inet_sk(sk)->num != IPPROTO_ICMP)
 			return -EOPNOTSUPP;
 		else
 			return raw_geticmpfilter(sk, optval, optlen);
@@ -627,13 +631,14 @@
 
 static void get_raw_sock(struct sock *sp, char *tmpbuf, int i)
 {
-	unsigned int dest = sp->daddr,
-		     src = sp->rcv_saddr;
+	struct inet_opt *inet = inet_sk(sp);
+	unsigned int dest = inet->daddr,
+		     src = inet->rcv_saddr;
 	__u16 destp = 0,
-	      srcp  = sp->num;
+	      srcp  = inet->num;
 
 	sprintf(tmpbuf, "%4d: %08X:%04X %08X:%04X"
-		" %02X %08X:%08X %02X:%08lX %08X %5d %8d %ld %d %p",
+		" %02X %08X:%08X %02X:%08lX %08X %5d %8d %lu %d %p",
 		i, src, srcp, dest, destp, sp->state, 
 		atomic_read(&sp->wmem_alloc), atomic_read(&sp->rmem_alloc),
 		0, 0L, 0,
diff -Nru a/net/ipv4/tcp.c b/net/ipv4/tcp.c
--- a/net/ipv4/tcp.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/tcp.c	Fri Mar 15 17:51:02 2002
@@ -524,6 +524,7 @@
 
 int tcp_listen_start(struct sock *sk)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct tcp_opt *tp = tcp_sk(sk);
 	struct tcp_listen_opt *lopt;
 
@@ -552,8 +553,8 @@
 	 * after validation is complete.
 	 */
 	sk->state = TCP_LISTEN;
-	if (sk->prot->get_port(sk, sk->num) == 0) {
-		sk->sport = htons(sk->num);
+	if (!sk->prot->get_port(sk, inet->num)) {
+		inet->sport = htons(inet->num);
 
 		sk_dst_reset(sk);
 		sk->prot->hash(sk);
@@ -1786,8 +1787,8 @@
 	/* It cannot be in hash table! */
 	BUG_TRAP(sk->pprev==NULL);
 
-	/* If it has not 0 sk->num, it must be bound */
-	BUG_TRAP(!sk->num || sk->prev!=NULL);
+	/* If it has not 0 inet_sk(sk)->num, it must be bound */
+	BUG_TRAP(!inet_sk(sk)->num || sk->prev);
 
 #ifdef TCP_DEBUG
 	if (sk->zapped) {
@@ -1988,6 +1989,7 @@
 
 int tcp_disconnect(struct sock *sk, int flags)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct tcp_opt *tp = tcp_sk(sk);
 	int old_state;
 	int err = 0;
@@ -2015,11 +2017,10 @@
   	tcp_writequeue_purge(sk);
   	__skb_queue_purge(&tp->out_of_order_queue);
 
-	sk->dport = 0;
+	inet->dport = 0;
 
 	if (!(sk->userlocks&SOCK_BINDADDR_LOCK)) {
-		sk->rcv_saddr = 0;
-		sk->saddr = 0;
+		inet->rcv_saddr = inet->saddr = 0;
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
 		if (sk->family == PF_INET6) {
 			struct ipv6_pinfo *np = inet6_sk(sk);
@@ -2049,7 +2050,7 @@
 	tcp_sack_reset(tp);
 	__sk_dst_reset(sk);
 
-	BUG_TRAP(!sk->num || sk->prev);
+	BUG_TRAP(!inet->num || sk->prev);
 
 	sk->error_report(sk);
 	return err;
diff -Nru a/net/ipv4/tcp_diag.c b/net/ipv4/tcp_diag.c
--- a/net/ipv4/tcp_diag.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv4/tcp_diag.c	Fri Mar 15 17:51:01 2002
@@ -44,6 +44,7 @@
 static int tcpdiag_fill(struct sk_buff *skb, struct sock *sk,
 			int ext, u32 pid, u32 seq)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct tcp_opt *tp = tcp_sk(sk);
 	struct tcpdiagmsg *r;
 	struct nlmsghdr  *nlh;
@@ -64,10 +65,6 @@
 	r->tcpdiag_timer = 0;
 	r->tcpdiag_retrans = 0;
 
-	r->id.tcpdiag_sport = sk->sport;
-	r->id.tcpdiag_dport = sk->dport;
-	r->id.tcpdiag_src[0] = sk->rcv_saddr;
-	r->id.tcpdiag_dst[0] = sk->daddr;
 	r->id.tcpdiag_if = sk->bound_dev_if;
 	*((struct sock **)&r->id.tcpdiag_cookie) = sk;
 
@@ -77,6 +74,10 @@
 		if (tmo < 0)
 			tmo = 0;
 
+		r->id.tcpdiag_sport = tw->sport;
+		r->id.tcpdiag_dport = tw->dport;
+		r->id.tcpdiag_src[0] = tw->rcv_saddr;
+		r->id.tcpdiag_dst[0] = tw->daddr;
 		r->tcpdiag_state = tw->substate;
 		r->tcpdiag_timer = 3;
 		r->tcpdiag_expires = (tmo*1000+HZ-1)/HZ;
@@ -94,6 +95,11 @@
 		return skb->len;
 	}
 
+	r->id.tcpdiag_sport = inet->sport;
+	r->id.tcpdiag_dport = inet->dport;
+	r->id.tcpdiag_src[0] = inet->rcv_saddr;
+	r->id.tcpdiag_dst[0] = inet->daddr;
+
 #ifdef CONFIG_IPV6
 	if (r->tcpdiag_family == AF_INET6) {
 		struct ipv6_pinfo *np = inet6_sk(sk);
@@ -291,6 +297,7 @@
 {
 	while (len > 0) {
 		int yes = 1;
+		struct inet_opt *inet = inet_sk(sk);
 		struct tcpdiag_bc_op *op = (struct tcpdiag_bc_op*)bc;
 
 		switch (op->code) {
@@ -300,16 +307,16 @@
 			yes = 0;
 			break;
 		case TCPDIAG_BC_S_GE:
-			yes = (sk->num >= op[1].no);
+			yes = inet->num >= op[1].no;
 			break;
 		case TCPDIAG_BC_S_LE:
-			yes = (sk->num <= op[1].no);
+			yes = inet->num <= op[1].no;
 			break;
 		case TCPDIAG_BC_D_GE:
-			yes = (ntohs(sk->dport) >= op[1].no);
+			yes = ntohs(inet->dport) >= op[1].no;
 			break;
 		case TCPDIAG_BC_D_LE:
-			yes = (ntohs(sk->dport) <= op[1].no);
+			yes = ntohs(inet->dport) <= op[1].no;
 			break;
 		case TCPDIAG_BC_AUTO:
 			yes = !(sk->userlocks&SOCK_BINDPORT_LOCK);
@@ -321,7 +328,8 @@
 			u32 *addr;
 
 			if (cond->port != -1 &&
-			    cond->port != (op->code == TCPDIAG_BC_S_COND ? sk->num : ntohs(sk->dport))) {
+			    cond->port != (op->code == TCPDIAG_BC_S_COND ?
+					     inet->num : ntohs(inet->dport))) {
 				yes = 0;
 				break;
 			}
@@ -341,9 +349,9 @@
 #endif
 			{
 				if (op->code == TCPDIAG_BC_S_COND)
-					addr = &sk->rcv_saddr;
+					addr = &inet->rcv_saddr;
 				else
-					addr = &sk->daddr;
+					addr = &inet->daddr;
 			}
 
 			if (bitstring_match(addr, cond->addr, cond->prefix_len))
@@ -453,12 +461,14 @@
 			for (sk = tcp_listening_hash[i], num = 0;
 			     sk != NULL;
 			     sk = sk->next, num++) {
+				struct inet_opt *inet = inet_sk(sk);
 				if (num < s_num)
 					continue;
 				if (!(r->tcpdiag_states&TCPF_LISTEN) ||
 				    r->id.tcpdiag_dport)
 					continue;
-				if (r->id.tcpdiag_sport != sk->sport && r->id.tcpdiag_sport)
+				if (r->id.tcpdiag_sport != inet->sport &&
+				    r->id.tcpdiag_sport)
 					continue;
 				if (bc && !tcpdiag_bc_run(RTA_DATA(bc), RTA_PAYLOAD(bc), sk))
 					continue;
@@ -491,13 +501,16 @@
 		for (sk = head->chain, num = 0;
 		     sk != NULL;
 		     sk = sk->next, num++) {
+			struct inet_opt *inet = inet_sk(sk);
+
 			if (num < s_num)
 				continue;
 			if (!(r->tcpdiag_states&(1<<sk->state)))
 				continue;
-			if (r->id.tcpdiag_sport != sk->sport && r->id.tcpdiag_sport)
+			if (r->id.tcpdiag_sport != inet->sport &&
+			    r->id.tcpdiag_sport)
 				continue;
-			if (r->id.tcpdiag_dport != sk->dport && r->id.tcpdiag_dport)
+			if (r->id.tcpdiag_dport != inet->dport && r->id.tcpdiag_dport)
 				continue;
 			if (bc && !tcpdiag_bc_run(RTA_DATA(bc), RTA_PAYLOAD(bc), sk))
 				continue;
@@ -513,13 +526,17 @@
 			for (sk = tcp_ehash[i+tcp_ehash_size].chain;
 			     sk != NULL;
 			     sk = sk->next, num++) {
+				struct inet_opt *inet = inet_sk(sk);
+
 				if (num < s_num)
 					continue;
 				if (!(r->tcpdiag_states&(1<<sk->zapped)))
 					continue;
-				if (r->id.tcpdiag_sport != sk->sport && r->id.tcpdiag_sport)
+				if (r->id.tcpdiag_sport != inet->sport &&
+				    r->id.tcpdiag_sport)
 					continue;
-				if (r->id.tcpdiag_dport != sk->dport && r->id.tcpdiag_dport)
+				if (r->id.tcpdiag_dport != inet->dport &&
+				    r->id.tcpdiag_dport)
 					continue;
 				if (bc && !tcpdiag_bc_run(RTA_DATA(bc), RTA_PAYLOAD(bc), sk))
 					continue;
diff -Nru a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c
--- a/net/ipv4/tcp_input.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/tcp_input.c	Fri Mar 15 17:51:02 2002
@@ -1329,9 +1329,10 @@
 #if FASTRETRANS_DEBUG > 1
 static void DBGUNDO(struct sock *sk, struct tcp_opt *tp, const char *msg)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	printk(KERN_DEBUG "Undo %s %u.%u.%u.%u/%u c%u l%u ss%u/%u p%u\n",
 	       msg,
-	       NIPQUAD(sk->daddr), ntohs(sk->dport),
+	       NIPQUAD(inet->daddr), ntohs(inet->dport),
 	       tp->snd_cwnd, tp->left_out,
 	       tp->snd_ssthresh, tp->prior_ssthresh, tp->packets_out);
 }
@@ -2570,15 +2571,12 @@
 			__set_current_state(TASK_RUNNING);
 
 			local_bh_enable();
-			if (skb_copy_datagram_iovec(skb, 0, tp->ucopy.iov,
-						    chunk)) {
-				sk->err = EFAULT;
-				sk->error_report(sk);
+			if (!skb_copy_datagram_iovec(skb, 0, tp->ucopy.iov, chunk)) {
+				tp->ucopy.len -= chunk;
+				tp->copied_seq += chunk;
+				eaten = (chunk == skb->len && !th->fin);
 			}
 			local_bh_disable();
-			tp->ucopy.len -= chunk;
-			tp->copied_seq += chunk;
-			eaten = (chunk == skb->len && !th->fin);
 		}
 
 		if (eaten <= 0) {
@@ -3178,17 +3176,8 @@
 						       tp->ucopy.iov);
 
 	if (!err) {
-update:
-		tp->ucopy.len  -= chunk;
+		tp->ucopy.len -= chunk;
 		tp->copied_seq += chunk;
-		local_bh_disable();
-		return 0;
-	}
-
-	if (err == -EFAULT) {
-		sk->err = EFAULT;
-		sk->error_report(sk);
-		goto update;
 	}
 
 	local_bh_disable();
@@ -3327,19 +3316,16 @@
 			    tp->copied_seq == tp->rcv_nxt &&
 			    len - tcp_header_len <= tp->ucopy.len &&
 			    sk->lock.users) {
-				eaten = 1;
-
-				NET_INC_STATS_BH(TCPHPHitsToUser);
-
 				__set_current_state(TASK_RUNNING);
 
-				if (tcp_copy_to_iovec(sk, skb, tcp_header_len))
-					goto csum_error;
-
-				__skb_pull(skb,tcp_header_len);
-
-				tp->rcv_nxt = TCP_SKB_CB(skb)->end_seq;
-			} else {
+				if (!tcp_copy_to_iovec(sk, skb, tcp_header_len)) {
+					__skb_pull(skb, tcp_header_len);
+					tp->rcv_nxt = TCP_SKB_CB(skb)->end_seq;
+					NET_INC_STATS_BH(TCPHPHitsToUser);
+					eaten = 1;
+				}
+			}
+			if (!eaten) {
 				if (tcp_checksum_complete_user(sk, skb))
 					goto csum_error;
 
diff -Nru a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
--- a/net/ipv4/tcp_ipv4.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/tcp_ipv4.c	Fri Mar 15 17:51:02 2002
@@ -109,10 +109,11 @@
 
 static __inline__ int tcp_sk_hashfn(struct sock *sk)
 {
-	__u32 laddr = sk->rcv_saddr;
-	__u16 lport = sk->num;
-	__u32 faddr = sk->daddr;
-	__u16 fport = sk->dport;
+	struct inet_opt *inet = inet_sk(sk);
+	__u32 laddr = inet->rcv_saddr;
+	__u16 lport = inet->num;
+	__u32 faddr = inet->daddr;
+	__u16 fport = inet->dport;
 
 	return tcp_hashfn(laddr, lport, faddr, fport);
 }
@@ -141,7 +142,8 @@
 /* Caller must disable local BH processing. */
 static __inline__ void __tcp_inherit_port(struct sock *sk, struct sock *child)
 {
-	struct tcp_bind_hashbucket *head = &tcp_bhash[tcp_bhashfn(child->num)];
+	struct tcp_bind_hashbucket *head =
+				&tcp_bhash[tcp_bhashfn(inet_sk(child)->num)];
 	struct tcp_bind_bucket *tb;
 
 	spin_lock(&head->lock);
@@ -163,7 +165,7 @@
 
 static inline void tcp_bind_hash(struct sock *sk, struct tcp_bind_bucket *tb, unsigned short snum) 
 { 
-	sk->num = snum; 
+	inet_sk(sk)->num = snum; 
 	if ((sk->bind_next = tb->owners) != NULL)
 		tb->owners->bind_pprev = &sk->bind_next;
 	tb->owners = sk;
@@ -173,6 +175,7 @@
 
 static inline int tcp_bind_conflict(struct sock *sk, struct tcp_bind_bucket *tb)
 { 
+	struct inet_opt *inet = inet_sk(sk);
 	struct sock *sk2 = tb->owners;
 	int sk_reuse = sk->reuse;
 	
@@ -182,9 +185,10 @@
 			if (!sk_reuse	||
 			    !sk2->reuse	||
 			    sk2->state == TCP_LISTEN) {
-				if (!sk2->rcv_saddr	||
-				    !sk->rcv_saddr	||
-				    (sk2->rcv_saddr == sk->rcv_saddr))
+				struct inet_opt *inet2 = inet_sk(sk2);
+				if (!inet2->rcv_saddr	||
+				    !inet->rcv_saddr	||
+				    (inet2->rcv_saddr == inet->rcv_saddr))
 					break;
 			}
 		}
@@ -281,7 +285,8 @@
  */
 __inline__ void __tcp_put_port(struct sock *sk)
 {
-	struct tcp_bind_hashbucket *head = &tcp_bhash[tcp_bhashfn(sk->num)];
+	struct inet_opt *inet = inet_sk(sk);
+	struct tcp_bind_hashbucket *head = &tcp_bhash[tcp_bhashfn(inet->num)];
 	struct tcp_bind_bucket *tb;
 
 	spin_lock(&head->lock);
@@ -290,7 +295,7 @@
 		sk->bind_next->bind_pprev = sk->bind_pprev;
 	*(sk->bind_pprev) = sk->bind_next;
 	sk->prev = NULL;
-	sk->num = 0;
+	inet->num = 0;
 	if (tb->owners == NULL) {
 		if (tb->next)
 			tb->next->pprev = tb->pprev;
@@ -409,8 +414,10 @@
 
 	hiscore=0;
 	for(; sk; sk = sk->next) {
-		if(sk->num == hnum) {
-			__u32 rcv_saddr = sk->rcv_saddr;
+		struct inet_opt *inet = inet_sk(sk);
+
+		if(inet->num == hnum) {
+			__u32 rcv_saddr = inet->rcv_saddr;
 
 			score = 1;
 			if(rcv_saddr) {
@@ -442,9 +449,11 @@
 	read_lock(&tcp_lhash_lock);
 	sk = tcp_listening_hash[tcp_lhashfn(hnum)];
 	if (sk) {
-		if (sk->num == hnum &&
+		struct inet_opt *inet = inet_sk(sk);
+
+		if (inet->num == hnum &&
 		    sk->next == NULL &&
-		    (!sk->rcv_saddr || sk->rcv_saddr == daddr) &&
+		    (!inet->rcv_saddr || inet->rcv_saddr == daddr) &&
 		    !sk->bound_dev_if)
 			goto sherry_cache;
 		sk = __tcp_v4_lookup_listener(sk, daddr, hnum, dif);
@@ -531,12 +540,13 @@
 
 static int tcp_v4_check_established(struct sock *sk)
 {
-	u32 daddr = sk->rcv_saddr;
-	u32 saddr = sk->daddr;
+	struct inet_opt *inet = inet_sk(sk);
+	u32 daddr = inet->rcv_saddr;
+	u32 saddr = inet->daddr;
 	int dif = sk->bound_dev_if;
 	TCP_V4_ADDR_COOKIE(acookie, saddr, daddr)
-	__u32 ports = TCP_COMBINED_PORTS(sk->dport, sk->num);
-	int hash = tcp_hashfn(daddr, sk->num, saddr, sk->dport);
+	__u32 ports = TCP_COMBINED_PORTS(inet->dport, inet->num);
+	int hash = tcp_hashfn(daddr, inet->num, saddr, inet->dport);
 	struct tcp_ehash_bucket *head = &tcp_ehash[hash];
 	struct sock *sk2, **skp;
 	struct tcp_tw_bucket *tw;
@@ -625,7 +635,7 @@
 
 int tcp_v4_hash_connecting(struct sock *sk)
 {
-	unsigned short snum = sk->num;
+	unsigned short snum = inet_sk(sk)->num;
 	struct tcp_bind_hashbucket *head = &tcp_bhash[tcp_bhashfn(snum)];
 	struct tcp_bind_bucket *tb = (struct tcp_bind_bucket *)sk->prev;
 
@@ -667,7 +677,7 @@
 		nexthop = inet->opt->faddr;
 	}
 
-	tmp = ip_route_connect(&rt, nexthop, sk->saddr,
+	tmp = ip_route_connect(&rt, nexthop, inet->saddr,
 			       RT_CONN_FLAGS(sk), sk->bound_dev_if);
 	if (tmp < 0)
 		return tmp;
@@ -689,11 +699,11 @@
 	if (buff == NULL)
 		goto failure;
 
-	if (!sk->saddr)
-		sk->saddr = rt->rt_src;
-	sk->rcv_saddr = sk->saddr;
+	if (!inet->saddr)
+		inet->saddr = rt->rt_src;
+	inet->rcv_saddr = inet->saddr;
 
-	if (tp->ts_recent_stamp && sk->daddr != daddr) {
+	if (tp->ts_recent_stamp && inet->daddr != daddr) {
 		/* Reset inherited state */
 		tp->ts_recent	    = 0;
 		tp->ts_recent_stamp = 0;
@@ -716,12 +726,13 @@
 		}
 	}
 
-	sk->dport = usin->sin_port;
-	sk->daddr = daddr;
+	inet->dport = usin->sin_port;
+	inet->daddr = daddr;
 
 	if (!tp->write_seq)
-		tp->write_seq = secure_tcp_sequence_number(sk->saddr, sk->daddr,
-							   sk->sport,
+		tp->write_seq = secure_tcp_sequence_number(inet->saddr,
+							   inet->daddr,
+							   inet->sport,
 							   usin->sin_port);
 
 	tp->ext_header_len = 0;
@@ -738,7 +749,7 @@
 failure:
 	__sk_dst_reset(sk);
 	sk->route_caps = 0;
-	sk->dport = 0;
+	inet->dport = 0;
 	return err;
 }
 
@@ -1018,11 +1029,13 @@
 void tcp_v4_send_check(struct sock *sk, struct tcphdr *th, int len, 
 		       struct sk_buff *skb)
 {
+	struct inet_opt *inet = inet_sk(sk);
+
 	if (skb->ip_summed == CHECKSUM_HW) {
-		th->check = ~tcp_v4_check(th, len, sk->saddr, sk->daddr, 0);
+		th->check = ~tcp_v4_check(th, len, inet->saddr, inet->daddr, 0);
 		skb->csum = offsetof(struct tcphdr, check);
 	} else {
-		th->check = tcp_v4_check(th, len, sk->saddr, sk->daddr,
+		th->check = tcp_v4_check(th, len, inet->saddr, inet->daddr,
 					 csum_partial((char *)th, th->doff<<2, skb->csum));
 	}
 }
@@ -1448,10 +1461,10 @@
 	newsk->route_caps = dst->dev->features;
 
 	newtp = tcp_sk(newsk);
-	newsk->daddr = req->af.v4_req.rmt_addr;
-	newsk->saddr = req->af.v4_req.loc_addr;
-	newsk->rcv_saddr = req->af.v4_req.loc_addr;
 	newinet = inet_sk(newsk);
+	newinet->daddr = req->af.v4_req.rmt_addr;
+	newinet->rcv_saddr = req->af.v4_req.loc_addr;
+	newinet->saddr = req->af.v4_req.loc_addr;
 	newinet->opt = req->af.v4_req.opt;
 	req->af.v4_req.opt = NULL;
 	newinet->mc_index = tcp_v4_iif(skb);
@@ -1736,9 +1749,9 @@
 	struct inet_opt *inet = inet_sk(sk);
 	int err;
 	struct rtable *rt;
-	__u32 old_saddr = sk->saddr;
+	__u32 old_saddr = inet->saddr;
 	__u32 new_saddr;
-	__u32 daddr = sk->daddr;
+	__u32 daddr = inet->daddr;
 
 	if (inet->opt && inet->opt->srr)
 		daddr = inet->opt->faddr;
@@ -1759,14 +1772,14 @@
 		return 0;
 
 	if (sysctl_ip_dynaddr > 1) {
-		printk(KERN_INFO "tcp_v4_rebuild_header(): shifting sk->saddr "
-		       "from %d.%d.%d.%d to %d.%d.%d.%d\n",
+		printk(KERN_INFO "tcp_v4_rebuild_header(): shifting inet->"
+				 "saddr from %d.%d.%d.%d to %d.%d.%d.%d\n",
 		       NIPQUAD(old_saddr), 
 		       NIPQUAD(new_saddr));
 	}
 
-	sk->saddr = new_saddr;
-	sk->rcv_saddr = new_saddr;
+	inet->saddr = new_saddr;
+	inet->rcv_saddr = new_saddr;
 
 	/* XXX The only one ugly spot where we need to
 	 * XXX really change the sockets identity after
@@ -1791,11 +1804,11 @@
 		return 0;
 
 	/* Reroute. */
-	daddr = sk->daddr;
+	daddr = inet->daddr;
 	if (inet->opt && inet->opt->srr)
 		daddr = inet->opt->faddr;
 
-	err = ip_route_output(&rt, daddr, sk->saddr,
+	err = ip_route_output(&rt, daddr, inet->saddr,
 			      RT_CONN_FLAGS(sk), sk->bound_dev_if);
 	if (!err) {
 		__sk_dst_set(sk, &rt->u.dst);
@@ -1818,10 +1831,11 @@
 static void v4_addr2sockaddr(struct sock *sk, struct sockaddr * uaddr)
 {
 	struct sockaddr_in *sin = (struct sockaddr_in *) uaddr;
+	struct inet_opt *inet = inet_sk(sk);
 
 	sin->sin_family		= AF_INET;
-	sin->sin_addr.s_addr	= sk->daddr;
-	sin->sin_port		= sk->dport;
+	sin->sin_addr.s_addr	= inet->daddr;
+	sin->sin_port		= inet->dport;
 }
 
 /* VJ's idea. Save last timestamp seen from this destination
@@ -1832,13 +1846,14 @@
 
 int tcp_v4_remember_stamp(struct sock *sk)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct tcp_opt *tp = tcp_sk(sk);
 	struct rtable *rt = (struct rtable*)__sk_dst_get(sk);
 	struct inet_peer *peer = NULL;
 	int release_it = 0;
 
-	if (rt == NULL || rt->rt_dst != sk->daddr) {
-		peer = inet_getpeer(sk->daddr, 1);
+	if (rt == NULL || rt->rt_dst != inet->daddr) {
+		peer = inet_getpeer(inet->daddr, 1);
 		release_it = 1;
 	} else {
 		if (rt->peer == NULL)
@@ -1979,7 +1994,7 @@
 		" %02X %08X:%08X %02X:%08X %08X %5d %8d %u %d %p",
 		i,
 		req->af.v4_req.loc_addr,
-		ntohs(sk->sport),
+		ntohs(inet_sk(sk)->sport),
 		req->af.v4_req.rmt_addr,
 		ntohs(req->rmt_port),
 		TCP_SYN_RECV,
@@ -2002,11 +2017,12 @@
 	int timer_active;
 	unsigned long timer_expires;
 	struct tcp_opt *tp = tcp_sk(sp);
+	struct inet_opt *inet = inet_sk(sp);
 
-	dest  = sp->daddr;
-	src   = sp->rcv_saddr;
-	destp = ntohs(sp->dport);
-	srcp  = ntohs(sp->sport);
+	dest  = inet->daddr;
+	src   = inet->rcv_saddr;
+	destp = ntohs(inet->dport);
+	srcp  = ntohs(inet->sport);
 	if (tp->pending == TCP_TIME_RETRANS) {
 		timer_active	= 1;
 		timer_expires	= tp->timeout;
diff -Nru a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c
--- a/net/ipv4/tcp_minisocks.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv4/tcp_minisocks.c	Fri Mar 15 17:51:02 2002
@@ -75,17 +75,16 @@
 	/* Disassociate with bind bucket. */
 	bhead = &tcp_bhash[tcp_bhashfn(tw->num)];
 	spin_lock(&bhead->lock);
-	if ((tb = tw->tb) != NULL) {
-		if(tw->bind_next)
-			tw->bind_next->bind_pprev = tw->bind_pprev;
-		*(tw->bind_pprev) = tw->bind_next;
-		tw->tb = NULL;
-		if (tb->owners == NULL) {
-			if (tb->next)
-				tb->next->pprev = tb->pprev;
-			*(tb->pprev) = tb->next;
-			kmem_cache_free(tcp_bucket_cachep, tb);
-		}
+	tb = tw->tb;
+	if(tw->bind_next)
+		tw->bind_next->bind_pprev = tw->bind_pprev;
+	*(tw->bind_pprev) = tw->bind_next;
+	tw->tb = NULL;
+	if (tb->owners == NULL) {
+		if (tb->next)
+			tb->next->pprev = tb->pprev;
+		*(tb->pprev) = tb->next;
+		kmem_cache_free(tcp_bucket_cachep, tb);
 	}
 	spin_unlock(&bhead->lock);
 
@@ -304,9 +303,23 @@
 	struct tcp_bind_hashbucket *bhead;
 	struct sock **head, *sktw;
 
+	/* Step 1: Put TW into bind hash. Original socket stays there too.
+	   Note, that any socket with inet_sk(sk)->num != 0 MUST be bound in
+	   binding cache, even if it is closed.
+	 */
+	bhead = &tcp_bhash[tcp_bhashfn(inet_sk(sk)->num)];
+	spin_lock(&bhead->lock);
+	tw->tb = (struct tcp_bind_bucket *)sk->prev;
+	BUG_TRAP(sk->prev!=NULL);
+	if ((tw->bind_next = tw->tb->owners) != NULL)
+		tw->tb->owners->bind_pprev = &tw->bind_next;
+	tw->tb->owners = (struct sock*)tw;
+	tw->bind_pprev = &tw->tb->owners;
+	spin_unlock(&bhead->lock);
+
 	write_lock(&ehead->lock);
 
-	/* Step 1: Remove SK from established hash. */
+	/* Step 2: Remove SK from established hash. */
 	if (sk->pprev) {
 		if(sk->next)
 			sk->next->pprev = sk->pprev;
@@ -315,7 +328,7 @@
 		sock_prot_dec_use(sk->prot);
 	}
 
-	/* Step 2: Hash TW into TIMEWAIT half of established hash table. */
+	/* Step 3: Hash TW into TIMEWAIT half of established hash table. */
 	head = &(ehead + tcp_ehash_size)->chain;
 	sktw = (struct sock *)tw;
 	if((sktw->next = *head) != NULL)
@@ -325,20 +338,6 @@
 	atomic_inc(&tw->refcnt);
 
 	write_unlock(&ehead->lock);
-
-	/* Step 3: Put TW into bind hash. Original socket stays there too.
-	   Note, that any socket with sk->num!=0 MUST be bound in binding
-	   cache, even if it is closed.
-	 */
-	bhead = &tcp_bhash[tcp_bhashfn(sk->num)];
-	spin_lock(&bhead->lock);
-	tw->tb = (struct tcp_bind_bucket *)sk->prev;
-	BUG_TRAP(sk->prev!=NULL);
-	if ((tw->bind_next = tw->tb->owners) != NULL)
-		tw->tb->owners->bind_pprev = &tw->bind_next;
-	tw->tb->owners = (struct sock*)tw;
-	tw->bind_pprev = &tw->tb->owners;
-	spin_unlock(&bhead->lock);
 }
 
 /* 
@@ -357,17 +356,18 @@
 		tw = kmem_cache_alloc(tcp_timewait_cachep, SLAB_ATOMIC);
 
 	if(tw != NULL) {
+		struct inet_opt *inet = inet_sk(sk);
 		int rto = (tp->rto<<2) - (tp->rto>>1);
 
 		/* Give us an identity. */
-		tw->daddr	= sk->daddr;
-		tw->rcv_saddr	= sk->rcv_saddr;
+		tw->daddr	= inet->daddr;
+		tw->rcv_saddr	= inet->rcv_saddr;
 		tw->bound_dev_if= sk->bound_dev_if;
-		tw->num		= sk->num;
+		tw->num		= inet->num;
 		tw->state	= TCP_TIME_WAIT;
 		tw->substate	= state;
-		tw->sport	= sk->sport;
-		tw->dport	= sk->dport;
+		tw->sport	= inet->sport;
+		tw->dport	= inet->dport;
 		tw->family	= sk->family;
 		tw->reuse	= sk->reuse;
 		tw->rcv_wscale	= tp->rcv_wscale;
@@ -660,7 +660,7 @@
 		newsk->prev = NULL;
 
 		/* Clone the TCP header template */
-		newsk->dport = req->rmt_port;
+		inet_sk(newsk)->dport = req->rmt_port;
 
 		sock_lock_init(newsk);
 		bh_lock_sock(newsk);
diff -Nru a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c
--- a/net/ipv4/tcp_output.c	Fri Mar 15 17:51:03 2002
+++ b/net/ipv4/tcp_output.c	Fri Mar 15 17:51:03 2002
@@ -188,6 +188,7 @@
 int tcp_transmit_skb(struct sock *sk, struct sk_buff *skb)
 {
 	if(skb != NULL) {
+		struct inet_opt *inet = inet_sk(sk);
 		struct tcp_opt *tp = tcp_sk(sk);
 		struct tcp_skb_cb *tcb = TCP_SKB_CB(skb);
 		int tcp_header_size = tp->tcp_header_len;
@@ -227,8 +228,8 @@
 		skb_set_owner_w(skb, sk);
 
 		/* Build TCP header and checksum it. */
-		th->source		= sk->sport;
-		th->dest		= sk->dport;
+		th->source		= inet->sport;
+		th->dest		= inet->dport;
 		th->seq			= htonl(tcb->seq);
 		th->ack_seq		= htonl(tp->rcv_nxt);
 		*(((__u16 *)th) + 6)	= htons(((tcp_header_size >> 2) << 12) | tcb->flags);
@@ -1120,7 +1121,7 @@
 	th->syn = 1;
 	th->ack = 1;
 	TCP_ECN_make_synack(req, th);
-	th->source = sk->sport;
+	th->source = inet_sk(sk)->sport;
 	th->dest = req->rmt_port;
 	TCP_SKB_CB(skb)->seq = req->snt_isn;
 	TCP_SKB_CB(skb)->end_seq = TCP_SKB_CB(skb)->seq + 1;
diff -Nru a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c
--- a/net/ipv4/tcp_timer.c	Fri Mar 15 17:51:03 2002
+++ b/net/ipv4/tcp_timer.c	Fri Mar 15 17:51:03 2002
@@ -334,10 +334,12 @@
 		 * we cannot allow such beasts to hang infinitely.
 		 */
 #ifdef TCP_DEBUG
-		if (net_ratelimit())
+		if (net_ratelimit()) {
+			struct inet_opt *inet = inet_sk(sk);
 			printk(KERN_DEBUG "TCP: Treason uncloaked! Peer %u.%u.%u.%u:%u/%u shrinks window %u:%u. Repaired.\n",
-			       NIPQUAD(sk->daddr), htons(sk->dport), sk->num,
-			       tp->snd_una, tp->snd_nxt);
+			       NIPQUAD(inet->daddr), htons(inet->dport),
+			       inet->num, tp->snd_una, tp->snd_nxt);
+		}
 #endif
 		if (tcp_time_stamp - tp->rcv_tstamp > TCP_RTO_MAX) {
 			tcp_write_err(sk);
diff -Nru a/net/ipv4/udp.c b/net/ipv4/udp.c
--- a/net/ipv4/udp.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv4/udp.c	Fri Mar 15 17:51:01 2002
@@ -108,6 +108,8 @@
 
 static int udp_v4_get_port(struct sock *sk, unsigned short snum)
 {
+	struct inet_opt *inet = inet_sk(sk);
+
 	write_lock_bh(&udp_hash_lock);
 	if (snum == 0) {
 		int best_size_so_far, best, result, i;
@@ -118,11 +120,11 @@
 		best_size_so_far = 32767;
 		best = result = udp_port_rover;
 		for (i = 0; i < UDP_HTABLE_SIZE; i++, result++) {
-			struct sock *sk;
+			struct sock *sk2;
 			int size;
 
-			sk = udp_hash[result & (UDP_HTABLE_SIZE - 1)];
-			if (!sk) {
+			sk2 = udp_hash[result & (UDP_HTABLE_SIZE - 1)];
+			if (!sk2) {
 				if (result > sysctl_local_port_range[1])
 					result = sysctl_local_port_range[0] +
 						((result - sysctl_local_port_range[0]) &
@@ -133,7 +135,7 @@
 			do {
 				if (++size >= best_size_so_far)
 					goto next;
-			} while ((sk = sk->next) != NULL);
+			} while ((sk2 = sk2->next) != NULL);
 			best_size_so_far = size;
 			best = result;
 		next:;
@@ -157,17 +159,19 @@
 		for (sk2 = udp_hash[snum & (UDP_HTABLE_SIZE - 1)];
 		     sk2 != NULL;
 		     sk2 = sk2->next) {
-			if (sk2->num == snum &&
+			struct inet_opt *inet2 = inet_sk(sk2);
+
+			if (inet2->num == snum &&
 			    sk2 != sk &&
 			    sk2->bound_dev_if == sk->bound_dev_if &&
-			    (!sk2->rcv_saddr ||
-			     !sk->rcv_saddr ||
-			     sk2->rcv_saddr == sk->rcv_saddr) &&
+			    (!inet2->rcv_saddr ||
+			     !inet->rcv_saddr ||
+			     inet2->rcv_saddr == inet->rcv_saddr) &&
 			    (!sk2->reuse || !sk->reuse))
 				goto fail;
 		}
 	}
-	sk->num = snum;
+	inet->num = snum;
 	if (sk->pprev == NULL) {
 		struct sock **skp = &udp_hash[snum & (UDP_HTABLE_SIZE - 1)];
 		if ((sk->next = *skp) != NULL)
@@ -198,7 +202,7 @@
 			sk->next->pprev = sk->pprev;
 		*sk->pprev = sk->next;
 		sk->pprev = NULL;
-		sk->num = 0;
+		inet_sk(sk)->num = 0;
 		sock_prot_dec_use(sk->prot);
 		__sock_put(sk);
 	}
@@ -215,20 +219,22 @@
 	int badness = -1;
 
 	for(sk = udp_hash[hnum & (UDP_HTABLE_SIZE - 1)]; sk != NULL; sk = sk->next) {
-		if(sk->num == hnum) {
+		struct inet_opt *inet = inet_sk(sk);
+
+		if (inet->num == hnum) {
 			int score = 0;
-			if(sk->rcv_saddr) {
-				if(sk->rcv_saddr != daddr)
+			if (inet->rcv_saddr) {
+				if (inet->rcv_saddr != daddr)
 					continue;
 				score++;
 			}
-			if(sk->daddr) {
-				if(sk->daddr != saddr)
+			if (inet->daddr) {
+				if (inet->daddr != saddr)
 					continue;
 				score++;
 			}
-			if(sk->dport) {
-				if(sk->dport != sport)
+			if (inet->dport) {
+				if (inet->dport != sport)
 					continue;
 				score++;
 			}
@@ -269,10 +275,12 @@
 	struct sock *s = sk;
 	unsigned short hnum = ntohs(loc_port);
 	for(; s; s = s->next) {
-		if ((s->num != hnum)					||
-		    (s->daddr && s->daddr!=rmt_addr)			||
-		    (s->dport != rmt_port && s->dport != 0)			||
-		    (s->rcv_saddr  && s->rcv_saddr != loc_addr)		||
+		struct inet_opt *inet = inet_sk(s);
+
+		if (inet->num != hnum					||
+		    (inet->daddr && inet->daddr != rmt_addr)		||
+		    (inet->dport != rmt_port && inet->dport)		||
+		    (inet->rcv_saddr && inet->rcv_saddr != loc_addr)	||
 		    (s->bound_dev_if && s->bound_dev_if != dif))
 			continue;
 		break;
@@ -469,15 +477,15 @@
 	} else {
 		if (sk->state != TCP_ESTABLISHED)
 			return -ENOTCONN;
-		ufh.daddr = sk->daddr;
-		ufh.uh.dest = sk->dport;
+		ufh.daddr   = inet->daddr;
+		ufh.uh.dest = inet->dport;
 		/* Open fast path for connected socket.
 		   Route will not be used, if at least one option is set.
 		 */
 		connected = 1;
   	}
-	ipc.addr = sk->saddr;
-	ufh.uh.source = sk->sport;
+	ipc.addr = inet->saddr;
+	ufh.uh.source = inet->sport;
 
 	ipc.opt = NULL;
 	ipc.oif = sk->bound_dev_if;
@@ -728,7 +736,7 @@
 
 	sk_dst_reset(sk);
 
-	err = ip_route_connect(&rt, usin->sin_addr.s_addr, sk->saddr,
+	err = ip_route_connect(&rt, usin->sin_addr.s_addr, inet->saddr,
 			       RT_CONN_FLAGS(sk), sk->bound_dev_if);
 	if (err)
 		return err;
@@ -736,12 +744,12 @@
 		ip_rt_put(rt);
 		return -EACCES;
 	}
-  	if(!sk->saddr)
-	  	sk->saddr = rt->rt_src;		/* Update source address */
-	if(!sk->rcv_saddr)
-		sk->rcv_saddr = rt->rt_src;
-	sk->daddr = rt->rt_dst;
-	sk->dport = usin->sin_port;
+  	if (!inet->saddr)
+	  	inet->saddr = rt->rt_src;	/* Update source address */
+	if (!inet->rcv_saddr)
+		inet->rcv_saddr = rt->rt_src;
+	inet->daddr = rt->rt_dst;
+	inet->dport = usin->sin_port;
 	sk->state = TCP_ESTABLISHED;
 	inet->id = jiffies;
 
@@ -751,17 +759,17 @@
 
 int udp_disconnect(struct sock *sk, int flags)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	/*
 	 *	1003.1g - break association.
 	 */
 	 
 	sk->state = TCP_CLOSE;
-	sk->daddr = 0;
-	sk->dport = 0;
+	inet->daddr = 0;
+	inet->dport = 0;
 	sk->bound_dev_if = 0;
 	if (!(sk->userlocks&SOCK_BINDADDR_LOCK)) {
-		sk->rcv_saddr = 0;
-		sk->saddr = 0;
+		inet->rcv_saddr = inet->saddr = 0;
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
 		if (sk->family == PF_INET6) {
 			struct ipv6_pinfo *np = inet6_sk(sk);
@@ -773,7 +781,7 @@
 	}
 	if (!(sk->userlocks&SOCK_BINDPORT_LOCK)) {
 		sk->prot->unhash(sk);
-		sk->sport = 0;
+		inet->sport = 0;
 	}
 	sk_dst_reset(sk);
 	return 0;
@@ -962,15 +970,16 @@
 
 static void get_udp_sock(struct sock *sp, char *tmpbuf, int i)
 {
+	struct inet_opt *inet = inet_sk(sp);
 	unsigned int dest, src;
 	__u16 destp, srcp;
 
-	dest  = sp->daddr;
-	src   = sp->rcv_saddr;
-	destp = ntohs(sp->dport);
-	srcp  = ntohs(sp->sport);
+	dest  = inet->daddr;
+	src   = inet->rcv_saddr;
+	destp = ntohs(inet->dport);
+	srcp  = ntohs(inet->sport);
 	sprintf(tmpbuf, "%4d: %08X:%04X %08X:%04X"
-		" %02X %08X:%08X %02X:%08lX %08X %5d %8d %ld %d %p",
+		" %02X %08X:%08X %02X:%08lX %08X %5d %8d %lu %d %p",
 		i, src, srcp, dest, destp, sp->state, 
 		atomic_read(&sp->wmem_alloc), atomic_read(&sp->rmem_alloc),
 		0, 0L, 0,
diff -Nru a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c
--- a/net/ipv6/af_inet6.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv6/af_inet6.c	Fri Mar 15 17:51:01 2002
@@ -200,7 +200,7 @@
 	inet = inet_sk(sk);
 
 	if (SOCK_RAW == sock->type) {
-		sk->num = protocol;
+		inet->num = protocol;
 		if (IPPROTO_RAW == protocol)
 			inet->hdrincl = 1;
 	}
@@ -241,12 +241,12 @@
 #endif
 	MOD_INC_USE_COUNT;
 
-	if (sk->num) {
+	if (inet->num) {
 		/* It assumes that any protocol which allows
 		 * the user to assign a number at socket
 		 * creation time automatically shares.
 		 */
-		sk->sport = ntohs(sk->num);
+		inet->sport = ntohs(inet->num);
 		sk->prot->hash(sk);
 	}
 	if (sk->prot->init) {
@@ -278,6 +278,7 @@
 {
 	struct sockaddr_in6 *addr=(struct sockaddr_in6 *)uaddr;
 	struct sock *sk = sock->sk;
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	__u32 v4addr = 0;
 	unsigned short snum;
@@ -318,8 +319,7 @@
 	lock_sock(sk);
 
 	/* Check these errors (active socket, double bind). */
-	if ((sk->state != TCP_CLOSE)			||
-	    (sk->num != 0)) {
+	if (sk->state != TCP_CLOSE || inet->num) {
 		release_sock(sk);
 		return -EINVAL;
 	}
@@ -340,8 +340,8 @@
 		}
 	}
 
-	sk->rcv_saddr = v4addr;
-	sk->saddr = v4addr;
+	inet->rcv_saddr = v4addr;
+	inet->saddr = v4addr;
 
 	ipv6_addr_copy(&np->rcv_saddr, &addr->sin6_addr);
 		
@@ -350,8 +350,7 @@
 
 	/* Make sure we are allowed to bind here. */
 	if (sk->prot->get_port(sk, snum) != 0) {
-		sk->rcv_saddr = 0;
-		sk->saddr = 0;
+		inet->rcv_saddr = inet->saddr = 0;
 		memset(&np->rcv_saddr, 0, sizeof(struct in6_addr));
 		memset(&np->saddr, 0, sizeof(struct in6_addr));
 
@@ -363,9 +362,9 @@
 		sk->userlocks |= SOCK_BINDADDR_LOCK;
 	if (snum)
 		sk->userlocks |= SOCK_BINDPORT_LOCK;
-	sk->sport = ntohs(sk->num);
-	sk->dport = 0;
-	sk->daddr = 0;
+	inet->sport = ntohs(inet->num);
+	inet->dport = 0;
+	inet->daddr = 0;
 	release_sock(sk);
 
 	return 0;
@@ -421,17 +420,18 @@
 {
 	struct sockaddr_in6 *sin=(struct sockaddr_in6 *)uaddr;
 	struct sock *sk = sock->sk;
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
   
 	sin->sin6_family = AF_INET6;
 	sin->sin6_flowinfo = 0;
 	sin->sin6_scope_id = 0;
 	if (peer) {
-		if (!sk->dport)
+		if (!inet->dport)
 			return -ENOTCONN;
 		if (((1<<sk->state)&(TCPF_CLOSE|TCPF_SYN_SENT)) && peer == 1)
 			return -ENOTCONN;
-		sin->sin6_port = sk->dport;
+		sin->sin6_port = inet->dport;
 		memcpy(&sin->sin6_addr, &np->daddr, sizeof(struct in6_addr));
 		if (np->sndflow)
 			sin->sin6_flowinfo = np->flow_label;
@@ -443,7 +443,7 @@
 			memcpy(&sin->sin6_addr, &np->rcv_saddr,
 			       sizeof(struct in6_addr));
 
-		sin->sin6_port = sk->sport;
+		sin->sin6_port = inet->sport;
 	}
 	if (ipv6_addr_type(&sin->sin6_addr) & IPV6_ADDR_LINKLOCAL)
 		sin->sin6_scope_id = sk->bound_dev_if;
@@ -675,6 +675,11 @@
 	 */
 	inet6_register_protosw(&rawv6_protosw);
 
+	/* Register the family here so that the init calls below will
+	 * be able to create sockets. (?? is this dangerous ??)
+	 */
+	(void) sock_register(&inet6_family_ops);
+	
 	/*
 	 *	ipngwg API draft makes clear that the correct semantics
 	 *	for TCP and UDP is to consider one TCP and UDP instance
@@ -719,9 +724,6 @@
 	udpv6_init();
 	tcpv6_init();
 
-	/* Now the userspace is allowed to create INET6 sockets. */
-	(void) sock_register(&inet6_family_ops);
-	
 	return 0;
 
 #ifdef CONFIG_PROC_FS
diff -Nru a/net/ipv6/ipv6_sockglue.c b/net/ipv6/ipv6_sockglue.c
--- a/net/ipv6/ipv6_sockglue.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv6/ipv6_sockglue.c	Fri Mar 15 17:51:01 2002
@@ -79,7 +79,7 @@
 	struct ip6_ra_chain *ra, *new_ra, **rap;
 
 	/* RA packet may be delivered ONLY to IPPROTO_RAW socket */
-	if (sk->type != SOCK_RAW || sk->num != IPPROTO_RAW)
+	if (sk->type != SOCK_RAW || inet_sk(sk)->num != IPPROTO_RAW)
 		return -EINVAL;
 
 	new_ra = (sel>=0) ? kmalloc(sizeof(*new_ra), GFP_KERNEL) : NULL;
@@ -283,7 +283,7 @@
 			if (opt) {
 				struct tcp_opt *tp = tcp_sk(sk);
 				if (!((1<<sk->state)&(TCPF_LISTEN|TCPF_CLOSE))
-				    && sk->daddr != LOOPBACK4_IPV6) {
+				    && inet_sk(sk)->daddr != LOOPBACK4_IPV6) {
 					tp->ext_header_len = opt->opt_flen + opt->opt_nflen;
 					tcp_sync_mss(sk, tp->pmtu_cookie);
 				}
diff -Nru a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c
--- a/net/ipv6/ndisc.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv6/ndisc.c	Fri Mar 15 17:51:01 2002
@@ -84,58 +84,63 @@
 static void pndisc_destructor(struct pneigh_entry *n);
 static void pndisc_redo(struct sk_buff *skb);
 
-static struct neigh_ops ndisc_generic_ops =
-{
-	AF_INET6,
-	NULL,
-	ndisc_solicit,
-	ndisc_error_report,
-	neigh_resolve_output,
-	neigh_connected_output,
-	dev_queue_xmit,
-	dev_queue_xmit
+static struct neigh_ops ndisc_generic_ops = {
+	family:			AF_INET6,
+	solicit:		ndisc_solicit,
+	error_report:		ndisc_error_report,
+	output:			neigh_resolve_output,
+	connected_output:	neigh_connected_output,
+	hh_output:		dev_queue_xmit,
+	queue_xmit:		dev_queue_xmit,
 };
 
-static struct neigh_ops ndisc_hh_ops =
-{
-	AF_INET6,
-	NULL,
-	ndisc_solicit,
-	ndisc_error_report,
-	neigh_resolve_output,
-	neigh_resolve_output,
-	dev_queue_xmit,
-	dev_queue_xmit
+static struct neigh_ops ndisc_hh_ops = {
+	family:			AF_INET6,
+	solicit:		ndisc_solicit,
+	error_report:		ndisc_error_report,
+	output:			neigh_resolve_output,
+	connected_output:	neigh_resolve_output,
+	hh_output:		dev_queue_xmit,
+	queue_xmit:		dev_queue_xmit,
 };
 
 
-static struct neigh_ops ndisc_direct_ops =
-{
-	AF_INET6,
-	NULL,
-	NULL,
-	NULL,
-	dev_queue_xmit,
-	dev_queue_xmit,
-	dev_queue_xmit,
-	dev_queue_xmit
+static struct neigh_ops ndisc_direct_ops = {
+	family:			AF_INET6,
+	output:			dev_queue_xmit,
+	connected_output:	dev_queue_xmit,
+	hh_output:		dev_queue_xmit,
+	queue_xmit:		dev_queue_xmit,
 };
 
-struct neigh_table nd_tbl =
-{
-	NULL,
-	AF_INET6,
-	sizeof(struct neighbour) + sizeof(struct in6_addr),
-	sizeof(struct in6_addr),
-	ndisc_hash,
-	ndisc_constructor,
-	pndisc_constructor,
-	pndisc_destructor,
-	pndisc_redo,
-	"ndisc_cache",
-        { NULL, NULL, &nd_tbl, 0, NULL, NULL,
-		  30*HZ, 1*HZ, 60*HZ, 30*HZ, 5*HZ, 3, 3, 0, 3, 1*HZ, (8*HZ)/10, 64, 0 },
-	30*HZ, 128, 512, 1024,
+struct neigh_table nd_tbl = {
+	family:		AF_INET6,
+	entry_size:	sizeof(struct neighbour) + sizeof(struct in6_addr),
+	key_len:	sizeof(struct in6_addr),
+	hash:		ndisc_hash,
+	constructor:	ndisc_constructor,
+	pconstructor:	pndisc_constructor,
+	pdestructor:	pndisc_destructor,
+	proxy_redo:	pndisc_redo,
+	id:		"ndisc_cache",
+	parms: {
+		tbl:			&nd_tbl,
+		base_reachable_time:	30 * HZ,
+		retrans_time:		 1 * HZ,
+		gc_staletime:		60 * HZ,
+		reachable_time:		30 * HZ,
+		delay_probe_time:	 5 * HZ,
+		queue_len:		 3,
+		ucast_probes:		 3,
+		mcast_probes:		 3,
+		anycast_delay:		 1 * HZ,
+		proxy_delay:		(8 * HZ) / 10,
+		proxy_qlen:		64,
+	},
+	gc_interval:	  30 * HZ,
+	gc_thresh1:	 128,
+	gc_thresh2:	 512,
+	gc_thresh3:	1024,
 };
 
 #define NDISC_OPT_SPACE(len) (((len)+2+7)&~7)
diff -Nru a/net/ipv6/raw.c b/net/ipv6/raw.c
--- a/net/ipv6/raw.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv6/raw.c	Fri Mar 15 17:51:02 2002
@@ -50,7 +50,8 @@
 
 static void raw_v6_hash(struct sock *sk)
 {
-	struct sock **skp = &raw_v6_htable[sk->num & (RAWV6_HTABLE_SIZE - 1)];
+	struct sock **skp = &raw_v6_htable[inet_sk(sk)->num &
+					   (RAWV6_HTABLE_SIZE - 1)];
 
 	write_lock_bh(&raw_v6_lock);
 	if ((sk->next = *skp) != NULL)
@@ -85,7 +86,7 @@
 	int addr_type = ipv6_addr_type(loc_addr);
 
 	for(s = sk; s; s = s->next) {
-		if(s->num == num) {
+		if (inet_sk(s)->num == num) {
 			struct ipv6_pinfo *np = inet6_sk(s);
 
 			if (!ipv6_addr_any(&np->daddr) &&
@@ -186,6 +187,7 @@
 /* This cleans up af_inet6 a bit. -DaveM */
 static int rawv6_bind(struct sock *sk, struct sockaddr *uaddr, int addr_len)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct sockaddr_in6 *addr = (struct sockaddr_in6 *) uaddr;
 	__u32 v4addr = 0;
@@ -233,8 +235,7 @@
 		}
 	}
 
-	sk->rcv_saddr = v4addr;
-	sk->saddr = v4addr;
+	inet->rcv_saddr = inet->saddr = v4addr;
 	ipv6_addr_copy(&np->rcv_saddr, &addr->sin6_addr);
 	if (!(addr_type & IPV6_ADDR_MULTICAST))
 		ipv6_addr_copy(&np->saddr, &addr->sin6_addr);
@@ -439,6 +440,7 @@
 {
 	struct ipv6_txoptions opt_space;
 	struct sockaddr_in6 * sin6 = (struct sockaddr_in6 *) msg->msg_name;
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct ipv6_txoptions *opt = NULL;
 	struct ip6_flowlabel *flowlabel = NULL;
@@ -478,7 +480,7 @@
 		proto = ntohs(sin6->sin6_port);
 
 		if (!proto)
-			proto = sk->num;
+			proto = inet->num;
 
 		if (proto > 255)
 			return(-EINVAL);
@@ -507,7 +509,7 @@
 		if (sk->state != TCP_ESTABLISHED) 
 			return(-EINVAL);
 		
-		proto = sk->num;
+		proto = inet->num;
 		daddr = &np->daddr;
 		fl.fl6_flowlabel = np->flow_label;
 	}
@@ -635,7 +637,7 @@
 			break;
 
 		case SOL_ICMPV6:
-			if (sk->num != IPPROTO_ICMPV6)
+			if (inet_sk(sk)->num != IPPROTO_ICMPV6)
 				return -EOPNOTSUPP;
 			return rawv6_seticmpfilter(sk, level, optname, optval,
 						   optlen);
@@ -678,7 +680,7 @@
 			break;
 
 		case SOL_ICMPV6:
-			if (sk->num != IPPROTO_ICMPV6)
+			if (inet_sk(sk)->num != IPPROTO_ICMPV6)
 				return -EOPNOTSUPP;
 			return rawv6_geticmpfilter(sk, level, optname, optval,
 						   optlen);
@@ -741,7 +743,7 @@
 
 static void rawv6_close(struct sock *sk, long timeout)
 {
-	if (sk->num == IPPROTO_RAW)
+	if (inet_sk(sk)->num == IPPROTO_RAW)
 		ip6_ra_control(sk, -1, NULL);
 
 	inet_sock_release(sk);
@@ -764,10 +766,10 @@
 	dest  = &np->daddr;
 	src   = &np->rcv_saddr;
 	destp = 0;
-	srcp  = sp->num;
+	srcp  = inet_sk(sp)->num;
 	sprintf(tmpbuf,
 		"%4d: %08X%08X%08X%08X:%04X %08X%08X%08X%08X:%04X "
-		"%02X %08X:%08X %02X:%08lX %08X %5d %8d %ld %d %p",
+		"%02X %08X:%08X %02X:%08lX %08X %5d %8d %lu %d %p",
 		i,
 		src->s6_addr32[0], src->s6_addr32[1],
 		src->s6_addr32[2], src->s6_addr32[3], srcp,
diff -Nru a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c
--- a/net/ipv6/tcp_ipv6.c	Fri Mar 15 17:51:01 2002
+++ b/net/ipv6/tcp_ipv6.c	Fri Mar 15 17:51:01 2002
@@ -76,11 +76,12 @@
 
 static __inline__ int tcp_v6_sk_hashfn(struct sock *sk)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct in6_addr *laddr = &np->rcv_saddr;
 	struct in6_addr *faddr = &np->daddr;
-	__u16 lport = sk->num;
-	__u16 fport = sk->dport;
+	__u16 lport = inet->num;
+	__u16 fport = inet->dport;
 	return tcp_v6_hashfn(laddr, lport, faddr, fport);
 }
 
@@ -153,14 +154,15 @@
 					    !sk2->reuse	||
 					    sk2->state == TCP_LISTEN) {
 						/* NOTE: IPv6 tw bucket have different format */
-						if (!sk2->rcv_saddr	||
+						if (!inet_sk(sk2)->rcv_saddr ||
 						    addr_type == IPV6_ADDR_ANY ||
 						    !ipv6_addr_cmp(&np->rcv_saddr,
 								   sk2->state != TCP_TIME_WAIT ?
 								   &np2->rcv_saddr :
 								   &((struct tcp_tw_bucket*)sk)->v6_rcv_saddr) ||
 						    (addr_type==IPV6_ADDR_MAPPED && sk2->family==AF_INET &&
-						     sk->rcv_saddr==sk2->rcv_saddr))
+						     inet_sk(sk)->rcv_saddr ==
+						     inet_sk(sk2)->rcv_saddr))
 							break;
 					}
 				}
@@ -185,7 +187,7 @@
 		tb->fastreuse = 0;
 
 success:
-	sk->num = snum;
+	inet_sk(sk)->num = snum;
 	if (sk->prev == NULL) {
 		if ((sk->bind_next = tb->owners) != NULL)
 			tb->owners->bind_pprev = &sk->bind_next;
@@ -255,7 +257,7 @@
 	read_lock(&tcp_lhash_lock);
 	sk = tcp_listening_hash[tcp_lhashfn(hnum)];
 	for(; sk; sk = sk->next) {
-		if((sk->num == hnum) && (sk->family == PF_INET6)) {
+		if (inet_sk(sk)->num == hnum && sk->family == PF_INET6) {
 			struct ipv6_pinfo *np = inet6_sk(sk);
 			
 			score = 1;
@@ -313,9 +315,11 @@
 	}
 	/* Must check for a TIME_WAIT'er before going to listener hash. */
 	for(sk = (head + tcp_ehash_size)->chain; sk; sk = sk->next) {
-		if(*((__u32 *)&(sk->dport))	== ports	&&
+		/* FIXME: acme: check this... */
+		struct tcp_tw_bucket *tw = (struct tcp_tw_bucket *)sk;
+
+		if(*((__u32 *)&(tw->dport))	== ports	&&
 		   sk->family			== PF_INET6) {
-			struct tcp_tw_bucket *tw = (struct tcp_tw_bucket *)sk;
 			if(!ipv6_addr_cmp(&tw->v6_daddr, saddr)	&&
 			   !ipv6_addr_cmp(&tw->v6_rcv_saddr, daddr) &&
 			   (!sk->bound_dev_if || sk->bound_dev_if == dif))
@@ -424,12 +428,13 @@
 
 static int tcp_v6_check_established(struct sock *sk)
 {
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct in6_addr *daddr = &np->rcv_saddr;
 	struct in6_addr *saddr = &np->daddr;
 	int dif = sk->bound_dev_if;
-	u32 ports = TCP_COMBINED_PORTS(sk->dport, sk->num);
-	int hash = tcp_v6_hashfn(daddr, sk->num, saddr, sk->dport);
+	u32 ports = TCP_COMBINED_PORTS(inet->dport, inet->num);
+	int hash = tcp_v6_hashfn(daddr, inet->num, saddr, inet->dport);
 	struct tcp_ehash_bucket *head = &tcp_ehash[hash];
 	struct sock *sk2, **skp;
 	struct tcp_tw_bucket *tw;
@@ -439,7 +444,7 @@
 	for(skp = &(head + tcp_ehash_size)->chain; (sk2=*skp)!=NULL; skp = &sk2->next) {
 		tw = (struct tcp_tw_bucket*)sk2;
 
-		if(*((__u32 *)&(sk2->dport))	== ports	&&
+		if(*((__u32 *)&(tw->dport))	== ports	&&
 		   sk2->family			== PF_INET6	&&
 		   !ipv6_addr_cmp(&tw->v6_daddr, saddr)		&&
 		   !ipv6_addr_cmp(&tw->v6_rcv_saddr, daddr)	&&
@@ -496,7 +501,7 @@
 
 static int tcp_v6_hash_connecting(struct sock *sk)
 {
-	unsigned short snum = sk->num;
+	unsigned short snum = inet_sk(sk)->num;
 	struct tcp_bind_hashbucket *head = &tcp_bhash[tcp_bhashfn(snum)];
 	struct tcp_bind_bucket *tb = head->chain;
 
@@ -522,6 +527,7 @@
 			  int addr_len)
 {
 	struct sockaddr_in6 *usin = (struct sockaddr_in6 *) uaddr;
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct tcp_opt *tp = tcp_sk(sk);
 	struct in6_addr *saddr = NULL;
@@ -618,9 +624,9 @@
 			goto failure;
 		} else {
 			ipv6_addr_set(&np->saddr, 0, 0, htonl(0x0000FFFF),
-				      sk->saddr);
+				      inet->saddr);
 			ipv6_addr_set(&np->rcv_saddr, 0, 0, htonl(0x0000FFFF),
-				      sk->rcv_saddr);
+				      inet->rcv_saddr);
 		}
 
 		return err;
@@ -634,7 +640,7 @@
 	fl.fl6_src = saddr;
 	fl.oif = sk->bound_dev_if;
 	fl.uli_u.ports.dport = usin->sin6_port;
-	fl.uli_u.ports.sport = sk->sport;
+	fl.uli_u.ports.sport = inet->sport;
 
 	if (np->opt && np->opt->srcrt) {
 		struct rt0_hdr *rt0 = (struct rt0_hdr *)np->opt->srcrt;
@@ -662,7 +668,7 @@
 	/* set the source address */
 	ipv6_addr_copy(&np->rcv_saddr, saddr);
 	ipv6_addr_copy(&np->saddr, saddr);
-	sk->rcv_saddr= LOOPBACK4_IPV6;
+	inet->rcv_saddr = LOOPBACK4_IPV6;
 
 	tp->ext_header_len = 0;
 	if (np->opt)
@@ -675,7 +681,7 @@
 	if (buff == NULL)
 		goto failure;
 
-	sk->dport = usin->sin6_port;
+	inet->dport = usin->sin6_port;
 
 	/*
 	 *	Init variables
@@ -684,7 +690,8 @@
 	if (!tp->write_seq)
 		tp->write_seq = secure_tcpv6_sequence_number(np->saddr.s6_addr32,
 							     np->daddr.s6_addr32,
-							     sk->sport, sk->dport);
+							     inet->sport,
+							     inet->dport);
 
 	err = tcp_connect(sk, buff);
 	if (err == 0)
@@ -692,7 +699,7 @@
 
 failure:
 	__sk_dst_reset(sk);
-	sk->dport = 0;
+	inet->dport = 0;
 	sk->route_caps = 0;
 	return err;
 }
@@ -750,6 +757,7 @@
 		dst = __sk_dst_check(sk, np->dst_cookie);
 
 		if (dst == NULL) {
+			struct inet_opt *inet = inet_sk(sk);
 			struct flowi fl;
 
 			/* BUGGG_FUTURE: Again, it is not clear how
@@ -760,8 +768,8 @@
 			fl.nl_u.ip6_u.daddr = &np->daddr;
 			fl.nl_u.ip6_u.saddr = &np->saddr;
 			fl.oif = sk->bound_dev_if;
-			fl.uli_u.ports.dport = sk->dport;
-			fl.uli_u.ports.sport = sk->sport;
+			fl.uli_u.ports.dport = inet->dport;
+			fl.uli_u.ports.sport = inet->sport;
 
 			dst = ip6_route_output(sk, &fl);
 		} else
@@ -850,7 +858,7 @@
 	fl.fl6_flowlabel = 0;
 	fl.oif = req->af.v6_req.iif;
 	fl.uli_u.ports.dport = req->rmt_port;
-	fl.uli_u.ports.sport = sk->sport;
+	fl.uli_u.ports.sport = inet_sk(sk)->sport;
 
 	if (dst == NULL) {
 		opt = np->opt;
@@ -1245,14 +1253,15 @@
 		if (newsk == NULL) 
 			return NULL;
 
+		newinet = inet_sk(newsk);
 		newnp = inet6_sk(newsk);
 		newtp = tcp_sk(newsk);
 
 		ipv6_addr_set(&newnp->daddr, 0, 0, htonl(0x0000FFFF),
-			      newsk->daddr);
+			      newinet->daddr);
 
 		ipv6_addr_set(&newnp->saddr, 0, 0, htonl(0x0000FFFF),
-			      newsk->saddr);
+			      newinet->saddr);
 
 		ipv6_addr_copy(&newnp->rcv_saddr, &newnp->saddr);
 
@@ -1303,7 +1312,7 @@
 		fl.fl6_flowlabel = 0;
 		fl.oif = sk->bound_dev_if;
 		fl.uli_u.ports.dport = req->rmt_port;
-		fl.uli_u.ports.sport = sk->sport;
+		fl.uli_u.ports.sport = inet_sk(sk)->sport;
 
 		dst = ip6_route_output(sk, &fl);
 	}
@@ -1376,9 +1385,7 @@
 	newtp->advmss = dst->advmss;
 	tcp_initialize_rcv_mss(newsk);
 
-	newsk->daddr	 = LOOPBACK4_IPV6;
-	newsk->saddr	 = LOOPBACK4_IPV6;
-	newsk->rcv_saddr = LOOPBACK4_IPV6;
+	newinet->daddr = newinet->saddr = newinet->rcv_saddr = LOOPBACK4_IPV6;
 
 	__tcp_v6_hash(newsk);
 	tcp_inherit_port(sk, newsk);
@@ -1680,6 +1687,7 @@
 	dst = __sk_dst_check(sk, np->dst_cookie);
 
 	if (dst == NULL) {
+		struct inet_opt *inet = inet_sk(sk);
 		struct flowi fl;
 
 		fl.proto = IPPROTO_TCP;
@@ -1687,8 +1695,8 @@
 		fl.nl_u.ip6_u.saddr = &np->saddr;
 		fl.fl6_flowlabel = np->flow_label;
 		fl.oif = sk->bound_dev_if;
-		fl.uli_u.ports.dport = sk->dport;
-		fl.uli_u.ports.sport = sk->sport;
+		fl.uli_u.ports.dport = inet->dport;
+		fl.uli_u.ports.sport = inet->sport;
 
 		if (np->opt && np->opt->srcrt) {
 			struct rt0_hdr *rt0 = (struct rt0_hdr *) np->opt->srcrt;
@@ -1714,6 +1722,7 @@
 static int tcp_v6_xmit(struct sk_buff *skb)
 {
 	struct sock *sk = skb->sk;
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct flowi fl;
 	struct dst_entry *dst;
@@ -1724,8 +1733,8 @@
 	fl.fl6_flowlabel = np->flow_label;
 	IP6_ECN_flow_xmit(sk, fl.fl6_flowlabel);
 	fl.oif = sk->bound_dev_if;
-	fl.uli_u.ports.sport = sk->sport;
-	fl.uli_u.ports.dport = sk->dport;
+	fl.uli_u.ports.sport = inet->sport;
+	fl.uli_u.ports.dport = inet->dport;
 
 	if (np->opt && np->opt->srcrt) {
 		struct rt0_hdr *rt0 = (struct rt0_hdr *) np->opt->srcrt;
@@ -1761,7 +1770,7 @@
 
 	sin6->sin6_family = AF_INET6;
 	memcpy(&sin6->sin6_addr, &np->daddr, sizeof(struct in6_addr));
-	sin6->sin6_port	= sk->dport;
+	sin6->sin6_port	= inet_sk(sk)->dport;
 	/* We do not store received flowlabel for TCP */
 	sin6->sin6_flowinfo = 0;
 	sin6->sin6_scope_id = 0;
@@ -1903,7 +1912,7 @@
 		i,
 		src->s6_addr32[0], src->s6_addr32[1],
 		src->s6_addr32[2], src->s6_addr32[3],
-		ntohs(sk->sport),
+		ntohs(inet_sk(sk)->sport),
 		dest->s6_addr32[0], dest->s6_addr32[1],
 		dest->s6_addr32[2], dest->s6_addr32[3],
 		ntohs(req->rmt_port),
@@ -1924,13 +1933,14 @@
 	__u16 destp, srcp;
 	int timer_active;
 	unsigned long timer_expires;
+	struct inet_opt *inet = inet_sk(sp);
 	struct tcp_opt *tp = tcp_sk(sp);
 	struct ipv6_pinfo *np = inet6_sk(sp);
 
 	dest  = &np->daddr;
 	src   = &np->rcv_saddr;
-	destp = ntohs(sp->dport);
-	srcp  = ntohs(sp->sport);
+	destp = ntohs(inet->dport);
+	srcp  = ntohs(inet->sport);
 	if (tp->pending == TCP_TIME_RETRANS) {
 		timer_active	= 1;
 		timer_expires	= tp->timeout;
diff -Nru a/net/ipv6/udp.c b/net/ipv6/udp.c
--- a/net/ipv6/udp.c	Fri Mar 15 17:51:02 2002
+++ b/net/ipv6/udp.c	Fri Mar 15 17:51:02 2002
@@ -65,11 +65,11 @@
 		best_size_so_far = 32767;
 		best = result = udp_port_rover;
 		for (i = 0; i < UDP_HTABLE_SIZE; i++, result++) {
-			struct sock *sk;
+			struct sock *sk2;
 			int size;
 
-			sk = udp_hash[result & (UDP_HTABLE_SIZE - 1)];
-			if (!sk) {
+			sk2 = udp_hash[result & (UDP_HTABLE_SIZE - 1)];
+			if (!sk2) {
 				if (result > sysctl_local_port_range[1])
 					result = sysctl_local_port_range[0] +
 						((result - sysctl_local_port_range[0]) &
@@ -80,7 +80,7 @@
 			do {
 				if (++size >= best_size_so_far)
 					goto next;
-			} while ((sk = sk->next) != NULL);
+			} while ((sk2 = sk2->next) != NULL);
 			best_size_so_far = size;
 			best = result;
 		next:;
@@ -104,23 +104,24 @@
 		for (sk2 = udp_hash[snum & (UDP_HTABLE_SIZE - 1)];
 		     sk2 != NULL;
 		     sk2 = sk2->next) {
+			struct inet_opt *inet2 = inet_sk(sk2);
 			struct ipv6_pinfo *np2 = inet6_sk(sk2);
 
-			if (sk2->num == snum &&
+			if (inet2->num == snum &&
 			    sk2 != sk &&
 			    sk2->bound_dev_if == sk->bound_dev_if &&
-			    (!sk2->rcv_saddr ||
+			    (!inet2->rcv_saddr ||
 			     addr_type == IPV6_ADDR_ANY ||
 			     !ipv6_addr_cmp(&np->rcv_saddr, &np2->rcv_saddr) ||
 			     (addr_type == IPV6_ADDR_MAPPED &&
 			      sk2->family == AF_INET &&
-			      sk->rcv_saddr == sk2->rcv_saddr)) &&
+			      inet_sk(sk)->rcv_saddr == inet2->rcv_saddr)) &&
 			    (!sk2->reuse || !sk->reuse))
 				goto fail;
 		}
 	}
 
-	sk->num = snum;
+	inet_sk(sk)->num = snum;
 	if (sk->pprev == NULL) {
 		struct sock **skp = &udp_hash[snum & (UDP_HTABLE_SIZE - 1)];
 		if ((sk->next = *skp) != NULL)
@@ -151,7 +152,7 @@
 			sk->next->pprev = sk->pprev;
 		*sk->pprev = sk->next;
 		sk->pprev = NULL;
-		sk->num = 0;
+		inet_sk(sk)->num = 0;
 		sock_prot_dec_use(sk->prot);
 		__sock_put(sk);
 	}
@@ -167,12 +168,13 @@
 
  	read_lock(&udp_hash_lock);
 	for(sk = udp_hash[hnum & (UDP_HTABLE_SIZE - 1)]; sk != NULL; sk = sk->next) {
-		if((sk->num == hnum)		&&
-		   (sk->family == PF_INET6)) {
+		struct inet_opt *inet = inet_sk(sk);
+
+		if (inet->num == hnum && sk->family == PF_INET6) {
 			struct ipv6_pinfo *np = inet6_sk(sk);
 			int score = 0;
-			if(sk->dport) {
-				if(sk->dport != sport)
+			if (inet->dport) {
+				if (inet->dport != sport)
 					continue;
 				score++;
 			}
@@ -213,6 +215,7 @@
 int udpv6_connect(struct sock *sk, struct sockaddr *uaddr, int addr_len)
 {
 	struct sockaddr_in6	*usin = (struct sockaddr_in6 *) uaddr;
+	struct inet_opt      	*inet = inet_sk(sk);
 	struct ipv6_pinfo      	*np = inet6_sk(sk);
 	struct in6_addr		*daddr;
 	struct in6_addr		saddr;
@@ -268,16 +271,16 @@
 		if (err < 0)
 			return err;
 		
-		ipv6_addr_set(&np->daddr, 0, 0, htonl(0x0000ffff), sk->daddr);
+		ipv6_addr_set(&np->daddr, 0, 0, htonl(0x0000ffff), inet->daddr);
 
 		if (ipv6_addr_any(&np->saddr)) {
 			ipv6_addr_set(&np->saddr, 0, 0, htonl(0x0000ffff),
-				      sk->saddr);
+				      inet->saddr);
 		}
 
 		if (ipv6_addr_any(&np->rcv_saddr)) {
 			ipv6_addr_set(&np->rcv_saddr, 0, 0, htonl(0x0000ffff),
-				      sk->rcv_saddr);
+				      inet->rcv_saddr);
 		}
 		return 0;
 	}
@@ -300,7 +303,7 @@
 	ipv6_addr_copy(&np->daddr, daddr);
 	np->flow_label = fl.fl6_flowlabel;
 
-	sk->dport = usin->sin6_port;
+	inet->dport = usin->sin6_port;
 
 	/*
 	 *	Check for a route to destination an obtain the
@@ -311,8 +314,8 @@
 	fl.fl6_dst = &np->daddr;
 	fl.fl6_src = &saddr;
 	fl.oif = sk->bound_dev_if;
-	fl.uli_u.ports.dport = sk->dport;
-	fl.uli_u.ports.sport = sk->sport;
+	fl.uli_u.ports.dport = inet->dport;
+	fl.uli_u.ports.sport = inet->sport;
 
 	if (flowlabel) {
 		if (flowlabel->opt && flowlabel->opt->srcrt) {
@@ -344,7 +347,7 @@
 
 		if (ipv6_addr_any(&np->rcv_saddr)) {
 			ipv6_addr_copy(&np->rcv_saddr, &saddr);
-			sk->rcv_saddr = LOOPBACK4_IPV6;
+			inet->rcv_saddr = LOOPBACK4_IPV6;
 		}
 		sk->state = TCP_ESTABLISHED;
 	}
@@ -528,10 +531,12 @@
 	struct sock *s = sk;
 	unsigned short num = ntohs(loc_port);
 	for(; s; s = s->next) {
-		if(s->num == num) {
+		struct inet_opt *inet = inet_sk(s);
+
+		if (inet->num == num) {
 			struct ipv6_pinfo *np = inet6_sk(s);
-			if(s->dport) {
-				if(s->dport != rmt_port)
+			if (inet->dport) {
+				if (inet->dport != rmt_port)
 					continue;
 			}
 			if (!ipv6_addr_any(&np->daddr) &&
@@ -757,6 +762,7 @@
 {
 	struct ipv6_txoptions opt_space;
 	struct udpv6fakehdr udh;
+	struct inet_opt *inet = inet_sk(sk);
 	struct ipv6_pinfo *np = inet6_sk(sk);
 	struct sockaddr_in6 *sin6 = (struct sockaddr_in6 *) msg->msg_name;
 	struct ipv6_txoptions *opt = NULL;
@@ -818,7 +824,7 @@
 		if (sk->state != TCP_ESTABLISHED)
 			return -ENOTCONN;
 
-		udh.uh.dest = sk->dport;
+		udh.uh.dest = inet->dport;
 		daddr = &np->daddr;
 		fl.fl6_flowlabel = np->flow_label;
 	}
@@ -867,7 +873,7 @@
 	if (opt && opt->srcrt)
 		udh.daddr = daddr;
 
-	udh.uh.source = sk->sport;
+	udh.uh.source = inet->sport;
 	udh.uh.len = len < 0x10000 ? htons(len) : 0;
 	udh.uh.check = 0;
 	udh.iov = msg->msg_iov;
@@ -905,17 +911,18 @@
 
 static void get_udp6_sock(struct sock *sp, char *tmpbuf, int i)
 {
+	struct inet_opt *inet = inet_sk(sp);
 	struct ipv6_pinfo *np = inet6_sk(sp);
 	struct in6_addr *dest, *src;
 	__u16 destp, srcp;
 
 	dest  = &np->daddr;
 	src   = &np->rcv_saddr;
-	destp = ntohs(sp->dport);
-	srcp  = ntohs(sp->sport);
+	destp = ntohs(inet->dport);
+	srcp  = ntohs(inet->sport);
 	sprintf(tmpbuf,
 		"%4d: %08X%08X%08X%08X:%04X %08X%08X%08X%08X:%04X "
-		"%02X %08X:%08X %02X:%08lX %08X %5d %8d %ld %d %p",
+		"%02X %08X:%08X %02X:%08lX %08X %5d %8d %lu %d %p",
 		i,
 		src->s6_addr32[0], src->s6_addr32[1],
 		src->s6_addr32[2], src->s6_addr32[3], srcp,
diff -Nru a/net/ipx/af_spx.c b/net/ipx/af_spx.c
--- a/net/ipx/af_spx.c	Fri Mar 15 17:51:03 2002
+++ b/net/ipx/af_spx.c	Fri Mar 15 17:51:03 2002
@@ -8,6 +8,7 @@
  *	Developers:
  *      Jay Schulist    <jschlst@samba.org>
  *	Jim Freeman	<jfree@caldera.com>
+ *	Arnaldo Carvalho de Melo <acme@conectiva.com.br>
  *
  *	Changes:
  *	Alan Cox	:	Fixed an skb_unshare check for NULL
@@ -22,6 +23,8 @@
  *				of the alloc count to follow rmt_seq.
  *	Arnaldo C. Melo :	Use a private slabcache for the old tp_pinfo
  *				struct sock member, use spx_sk and ipx_sk
+ *	Arnaldo C. Melo :	Big CodingStyle cleanup, fixes some lock leaks,
+ *				removes a leftover of the slabcache patch.
  *
  *	This program is free software; you can redistribute it and/or
  *      modify it under the terms of the GNU General Public License
@@ -44,7 +47,7 @@
 #include <linux/unistd.h>
 #include <linux/poll.h>
 
-static struct proto_ops *ipx_operations;
+static struct proto_ops *ipx_ops;
 static struct proto_ops spx_ops;
 static __u16  connids;
 
@@ -60,7 +63,8 @@
 			but the right spx buffers are looked at and
 			there is no question on the type of the socket
 			*/
-static unsigned int spx_datagram_poll(struct file * file, struct socket *sock, poll_table *wait)
+static unsigned int spx_datagram_poll(struct file * file, struct socket *sock,
+				      poll_table *wait)
 {
 	struct sock *sk = sock->sk;
 	struct spx_opt *pdata = spx_sk(sk);
@@ -84,15 +88,14 @@
 		mask |= POLLHUP;
 	/* connection hasn't started yet? */
 	if (sk->state == TCP_SYN_SENT)
-		return mask;
+		goto out;
 
 	/* writable? */
 	if (sock_writeable(sk))
 		mask |= POLLOUT | POLLWRNORM | POLLWRBAND;
 	else
 		set_bit(SOCK_ASYNC_NOSPACE,&sk->socket->flags);
-
-	return mask;
+out:	return mask;
 }
 
 /* Create the SPX specific data */
@@ -123,43 +126,42 @@
 	skb_queue_head_init(&pdata->transmit_queue);
 	skb_queue_head_init(&pdata->retransmit_queue);
 
-        return (0);
+        return 0;
 }
 
 static int spx_create(struct socket *sock, int protocol)
 {
 	struct sock *sk;
+	int rc = -ENOMEM;
+
+        MOD_INC_USE_COUNT;
 
-	/*
-	 *	Called on connection receive so cannot be GFP_KERNEL
-	 */
-	 
+	/* Called on connection receive so cannot be GFP_KERNEL */
 	sk = sk_alloc(PF_IPX, GFP_ATOMIC, 1);
-	if(sk == NULL)
-                return (-ENOMEM);
+	if (!sk)
+		goto decmod;
 
-	switch(sock->type)
-        {
+	rc = -ESOCKTNOSUPPORT;
+	switch (sock->type) {
                 case SOCK_SEQPACKET:
 			sock->ops = &spx_ops;
 			break;
 		default:
 			sk_free(sk);
-                        return (-ESOCKTNOSUPPORT);
+			goto out;
         }
 
+	rc = 0;
 	sock_init_data(sock, sk);
 	spx_sock_init(sk);
 	sk->data_ready  = spx_rcv;
 	sk->destruct 	= NULL;
         sk->no_check 	= 1;
-
-        MOD_INC_USE_COUNT;
-
-	return (0);
+out:	return rc;
+decmod:	MOD_DEC_USE_COUNT;
+	goto out;
 }
 
-
 void spx_close_socket(struct sock *sk)
 {
 	struct spx_opt *pdata = spx_sk(sk);
@@ -173,18 +175,12 @@
 void spx_destroy_socket(struct sock *sk)
 {
 	struct spx_opt *pdata = spx_sk(sk);
-	struct sk_buff *skb;
 
         ipx_remove_socket(sk);
-        while((skb = skb_dequeue(&sk->receive_queue)) != NULL)
-                kfree_skb(skb);
-	while((skb = skb_dequeue(&pdata->transmit_queue)) != NULL)
-                kfree_skb(skb);
-	while((skb = skb_dequeue(&pdata->retransmit_queue)) != NULL)
-		kfree_skb(skb);
-	while((skb = skb_dequeue(&pdata->rcv_queue)) != NULL)
-                kfree_skb(skb);
-
+	skb_queue_purge(&sk->receive_queue);
+	skb_queue_purge(&pdata->transmit_queue);
+	skb_queue_purge(&pdata->retransmit_queue);
+	skb_queue_purge(&pdata->rcv_queue);
         sk_free(sk);
 	MOD_DEC_USE_COUNT;
 }
@@ -195,14 +191,13 @@
  	struct sock *sk = sock->sk;
 	struct spx_opt *pdata = spx_sk(sk);
 
-	if(sk == NULL)
-		return (0);
-	if(!sk->dead)
+	if (!sk)
+		goto out;
+	if (!sk->dead)
                 sk->state_change(sk);
         sk->dead = 1;
 
-	if(pdata->state != SPX_CLOSED)
-	{
+	if (pdata->state != SPX_CLOSED) {
 		spx_transmit(sk, NULL, DISCON, 0);
 		spx_close_socket(sk);
 	}
@@ -210,111 +205,101 @@
 	sock->sk	= NULL;
 	sk->socket 	= NULL;
 	spx_destroy_socket(sk);
-
-        return (0);
+out:	return 0;
 }
 
 /* Move a socket into listening state. */
 static int spx_listen(struct socket *sock, int backlog)
 {
         struct sock *sk = sock->sk;
+	int rc = -EINVAL;
 
-        if(sock->state != SS_UNCONNECTED)
-                return (-EINVAL);
-	if(sock->type != SOCK_SEQPACKET)
-		return (-EOPNOTSUPP);
-        if(sk->zapped != 0)
-                return (-EAGAIN);
-
+        if (sock->state != SS_UNCONNECTED)
+		goto out;
+	rc = -EOPNOTSUPP;
+	if (sock->type != SOCK_SEQPACKET)
+		goto out;
+	rc = -EAGAIN;
+        if (sk->zapped)
+		goto out;
+	rc = 0;
         sk->max_ack_backlog = backlog;
-        if(sk->state != TCP_LISTEN)
-        {
+        if (sk->state != TCP_LISTEN) {
                 sk->ack_backlog = 0;
                 sk->state = TCP_LISTEN;
         }
         sk->socket->flags |= __SO_ACCEPTCON;
-
-        return (0);
+out:	return rc;
 }
 
 /* Accept a pending SPX connection */
 static int spx_accept(struct socket *sock, struct socket *newsock, int flags)
 {
-        struct sock *sk;
+        struct sock *sk = sock->sk;
         struct sock *newsk;
         struct sk_buff *skb;
-	int err;
-
-	if(sock->sk == NULL)
-		return (-EINVAL);
-	sk = sock->sk;
-
-        if((sock->state != SS_UNCONNECTED) || !(sock->flags & __SO_ACCEPTCON))
-                return (-EINVAL);
-        if(sock->type != SOCK_SEQPACKET)
-		return (-EOPNOTSUPP);
-	if(sk->state != TCP_LISTEN)
-                return (-EINVAL);
+	int rc = -EINVAL;
 
+	if (!sk || sk->state != TCP_LISTEN ||
+	    sock->state != SS_UNCONNECTED || !(sock->flags & __SO_ACCEPTCON))
+		goto out;
+	rc = -EOPNOTSUPP;
+        if (sock->type != SOCK_SEQPACKET)
+		goto out;
 	cli();
 	do {
 		skb = skb_dequeue(&sk->receive_queue);
-		if(skb == NULL)
-		{
-                	if(flags & O_NONBLOCK)
-			{
-                                sti();
-                                return (-EWOULDBLOCK);
-                        }
+		if (!skb) {
+			rc = -EWOULDBLOCK;
+                	if (flags & O_NONBLOCK)
+				goto out_unlock;
                 	interruptible_sleep_on(sk->sleep);
-                	if(signal_pending(current))
-                	{
-                        	sti();
-                        	return (-ERESTARTSYS);
-                	}
+                        rc = -ERESTARTSYS;
+                	if (signal_pending(current))
+				goto out_unlock;
 		}
-	} while (skb == NULL);
+	} while (!skb);
 
 	newsk 		= skb->sk;
         newsk->pair 	= NULL;
 	sti();
 
-	err = spx_transmit(newsk, skb, CONACK, 0);   /* Connection ACK */
-	if(err)
-		return (err);
-
+	rc = spx_transmit(newsk, skb, CONACK, 0);   /* Connection ACK */
+	if (rc)
+		goto out;
 	/* Now attach up the new socket */
 	sock->sk 	= NULL;
         sk->ack_backlog--;
         newsock->sk 	= newsk;
 	newsk->state 	= TCP_ESTABLISHED;
 	ipx_sk(newsk)->dest_addr = spx_sk(newsk)->dest_addr;
-
-	return (0);
+out:	return rc;
+out_unlock:
+	sti();
+	goto out;
 }
 
 /* Build a connection to an SPX socket */
 static int spx_connect(struct socket *sock, struct sockaddr *uaddr,
-                int addr_len, int flags)
+		       int addr_len, int flags)
 {
 	struct sock *sk = sock->sk;
         struct spx_opt *pdata = spx_sk(sk);
         struct sockaddr_ipx src;
 	struct sk_buff *skb;
-	int size, err;
+	int size = sizeof(src);
+	int rc = ipx_ops->getname(sock, (struct sockaddr *)&src, &size, 0);
 
-	size = sizeof(src);
-	err  = ipx_operations->getname(sock, (struct sockaddr *)&src, &size, 0);
-	if(err)
-		return (err);
+	if (rc)
+		goto out;
 
         pdata->source_addr.net	= src.sipx_network;
         memcpy(pdata->source_addr.node, src.sipx_node, IPX_NODE_LEN);
         pdata->source_addr.sock = (unsigned short)src.sipx_port;
 
-	err = ipx_operations->connect(sock, uaddr, addr_len, flags);
-        if(err)
-                return (err);
+	rc = ipx_ops->connect(sock, uaddr, addr_len, flags);
+        if (rc)
+                goto out;
 
         pdata->dest_addr = ipx_sk(sk)->dest_addr;
 	pdata->state	 = SPX_CONNECTING;
@@ -322,42 +307,36 @@
         sk->state	 = TCP_SYN_SENT;
 
         /* Send Connection request */
-	err = spx_transmit(sk, NULL, CONREQ, 0);
-        if(err)
-                return (err);
+	rc = spx_transmit(sk, NULL, CONREQ, 0);
+        if (rc)
+                goto out;
 
 	cli();
         do {
                 skb = skb_dequeue(&sk->receive_queue);
-                if(skb == NULL)
-                {
-                        if(flags & O_NONBLOCK)
-                        {
-                                sti();
-                                return (-EWOULDBLOCK);
-                        }
+                if (!skb) {
+			rc = -EWOULDBLOCK;
+                        if (flags & O_NONBLOCK)
+				goto unlock;
                         interruptible_sleep_on(sk->sleep);
-                        if(signal_pending(current))
-                        {
-                                sti();
-                                return (-ERESTARTSYS);
-                        }
+			rc = -ERESTARTSYS;
+                        if (signal_pending(current))
+				goto unlock;
                 }
-        } while (skb == NULL);
+        } while (!skb);
 
-        if(pdata->state == SPX_CLOSED)
-        {
-		sti();
+	rc = -ETIMEDOUT;
+        if (pdata->state == SPX_CLOSED) {
                 del_timer(&pdata->watchdog);
-                return (-ETIMEDOUT);
+		goto unlock;
         }
 
+	rc = 0;
 	sock->state	= SS_CONNECTED;
 	sk->state 	= TCP_ESTABLISHED;
 	kfree_skb(skb);
-	sti();
-
-        return (0);
+unlock:	sti();
+out:	return rc;
 }
 
 /*
@@ -371,56 +350,59 @@
  */
 static inline unsigned long spx_calc_rtt(int tries)
 {
-        if(tries < 1)
-                return (RETRY_TIME);
-        if(tries > 5)
-                return (MAX_RETRY_DELAY);
-        return (tries * HZ);
+	int rc;
+
+        if (tries < 1)
+                rc = RETRY_TIME;
+	else if (tries > 5)
+                rc = MAX_RETRY_DELAY;
+	else
+		rc = tries * HZ;
+	return rc;
 }
 
 static int spx_route_skb(struct spx_opt *pdata, struct sk_buff *skb, int type)
 {
-	struct sk_buff *skb2;
-	int err = 0;
+	int rc = -ENOBUFS;
 
 	skb = skb_unshare(skb, GFP_ATOMIC);
-	if(skb == NULL)
-		return (-ENOBUFS);
-
-	switch(type)
-	{
-		case (CONREQ):
-		case (DATA):
-			if(!skb_queue_empty(&pdata->retransmit_queue))
-			{
+	if (!skb)
+		goto out;
+	rc = 0;
+
+	switch (type) {
+		case CONREQ:
+		case DATA:
+			if (!skb_queue_empty(&pdata->retransmit_queue)) {
 				skb_queue_tail(&pdata->transmit_queue, skb);
-				return 0;
+				goto out;
 			}
-
-		case (TQUEUE):
+		case TQUEUE: {
+			struct sk_buff *skb2;
 			pdata->retransmit.expires = jiffies + spx_calc_rtt(0);
 			add_timer(&pdata->retransmit);
 
 			skb2 = skb_clone(skb, GFP_NOIO);
-	                if(skb2 == NULL)
-        	                return -ENOBUFS;
+	                if (!skb2) {
+				rc = -ENOBUFS;
+        	                goto out;
+			}
         	        skb_queue_tail(&pdata->retransmit_queue, skb2);
-
-		case (ACK):
-		case (CONACK):
-		case (WDREQ):
-		case (WDACK):
-		case (DISCON):
-		case (DISACK):
-		case (RETRAN):
-		default:
-			/* Send data */
-        		err = ipxrtr_route_skb(skb);
-        		if(err)
+			/* Fall thru */
+		}
+		case ACK:
+		case CONACK:
+		case WDREQ:
+		case WDACK:
+		case DISCON:
+		case DISACK:
+		case RETRAN:
+		default: /* Send data */
+        		rc = ipxrtr_route_skb(skb);
+        		if (rc)
                 		kfree_skb(skb);
 	}
-
-	return (err);
+out:	return rc;
 }
 
 /* SPX packet transmit engine */
@@ -429,25 +411,27 @@
         struct spx_opt *pdata = spx_sk(sk);
         struct ipxspxhdr *ipxh;
 	unsigned long flags;
-	int err;
+	int rc;
 
-	if(skb == NULL)
-	{
+	if (!skb) {
 		int offset  = ipx_if_offset(pdata->dest_addr.net);
         	int size    = offset + sizeof(struct ipxspxhdr);
 
-        	if (offset < 0) /* ENETUNREACH */
-        		return(-ENETUNREACH);
+		rc = -ENETUNREACH;
+        	if (offset < 0)
+        		goto out;
 
 		save_flags(flags);
 		cli();
         	skb = sock_alloc_send_skb(sk, size, 0, &err);
-        	if(skb == NULL) {
+		rc = -ENOMEM;
+        	if (!skb) {
 			restore_flags(flags);
-                	return (-ENOMEM);
+                	goto out;
 		}
         	skb_reserve(skb, offset);
-        	skb->h.raw = skb->nh.raw = skb_put(skb,sizeof(struct ipxspxhdr));
+        	skb->h.raw = skb->nh.raw =
+				skb_put(skb, sizeof(struct ipxspxhdr));
 		restore_flags(flags);
 	}
 
@@ -471,40 +455,39 @@
 	/* Reset/Set WD timer */
         mod_timer(&pdata->watchdog, jiffies+VERIFY_TIMEOUT);
 
-	switch(type)
-	{
-		case (DATA):	/* Data */
+	switch (type) {
+		case DATA:	/* Data */
 			ipxh->ipx.ipx_pktsize 	= htons(SPX_SYS_PKT_LEN + len);
 			ipxh->spx.cctl 		= (CCTL_ACK | CCTL_EOM);
                 	pdata->sequence++;
 			break;
 
-		case (ACK):	/* ACK */
+		case ACK:	/* ACK */
 			pdata->rmt_seq++;
-		case (WDACK):	/* WD ACK */
-		case (CONACK):	/* Connection ACK */
+		case WDACK:	/* WD ACK */
+		case CONACK:	/* Connection ACK */
 			ipxh->spx.cctl 		= CCTL_SYS;
 			ipxh->spx.ackseq 	= htons(pdata->rmt_seq);
 			break;
 
-		case (CONREQ):	/* Connection Request */
+		case CONREQ:	/* Connection Request */
 			del_timer(&pdata->watchdog);
-		case (WDREQ):	/* WD Request */
+		case WDREQ:	/* WD Request */
 			pdata->source_connid    = htons(connids++);
                 	pdata->dest_connid      = 0xFFFF;
                 	pdata->alloc 		= 3 + pdata->rmt_seq;
-			ipxh->spx.cctl          = (CCTL_ACK | CCTL_SYS);
+			ipxh->spx.cctl          = CCTL_ACK | CCTL_SYS;
 			ipxh->spx.sconn         = pdata->source_connid;
 		        ipxh->spx.dconn         = pdata->dest_connid;
 		        ipxh->spx.allocseq      = htons(pdata->alloc);
 			break;
 
-		case (DISCON):	/* Informed Disconnect */
+		case DISCON:	/* Informed Disconnect */
 			ipxh->spx.cctl 		= CCTL_ACK;
 			ipxh->spx.dtype 	= SPX_DTYPE_ECONN;
 			break;
 
-		case (DISACK):	/* Informed Disconnect ACK */
+		case DISACK:	/* Informed Disconnect ACK */
 			ipxh->spx.cctl  	= 0;
 			ipxh->spx.dtype 	= SPX_DTYPE_ECACK;
 			ipxh->spx.sequence 	= 0;
@@ -512,11 +495,13 @@
 			break;
 
 		default:
-			return (-EOPNOTSUPP);
+			rc = -EOPNOTSUPP;
+			goto out;
 	}
 
 	/* Send data */
-        return (spx_route_skb(pdata, skb, type));
+        rc = spx_route_skb(pdata, skb, type);
+out:	return rc;
 }
 
 /* Check the state of the connection and send a WD request if needed. */
@@ -526,19 +511,16 @@
         struct spx_opt *pdata = spx_sk(sk);
 
         del_timer(&pdata->watchdog);
-	if(pdata->state == SPX_CLOSED)
-                return;
-	if(pdata->retries > pdata->max_retries)
-        {
+	if (pdata->state == SPX_CLOSED)
+                goto out;
+	if (pdata->retries > pdata->max_retries) {
 		spx_close_socket(sk);	/* Unilateral Abort */
-                return;
+                goto out;
         }
-
         /* Send WD request */
 	spx_transmit(sk, NULL, WDREQ, 0);
 	pdata->retries++;
-
-        return;
+out:;
 }
 
 static void spx_retransmit(unsigned long data)
@@ -547,22 +529,19 @@
         struct spx_opt *pdata = spx_sk(sk);
 	struct sk_buff *skb;
 	unsigned long flags;
-	int err;
 
 	del_timer(&pdata->retransmit);
-	if(pdata->state == SPX_CLOSED)
-		return;
-	if(pdata->retransmits > RETRY_COUNT)
-	{
+	if (pdata->state == SPX_CLOSED)
+		goto out;
+	if (pdata->retransmits > RETRY_COUNT) {
 		spx_close_socket(sk);   /* Unilateral Abort */
-                return;
+                goto out;
         }
-
 	/* Need to leave skb on the queue, aye the fear */
 	save_flags(flags);
 	cli();
 	skb = skb_peek(&pdata->retransmit_queue);
-	if(skb_cloned(skb))
+	if (skb_cloned(skb))
                 skb = skb_copy(skb, GFP_ATOMIC);
         else
                 skb = skb_clone(skb, GFP_ATOMIC);
@@ -571,67 +550,60 @@
 	pdata->retransmit.expires = jiffies + spx_calc_rtt(pdata->retransmits);
 	add_timer(&pdata->retransmit);
 
-	err = spx_route_skb(pdata, skb, RETRAN);
+	spx_route_skb(pdata, skb, RETRAN);
 	pdata->retransmits++;
-
-	return;
+out:;
 }
 
 /* Check packet for retransmission, ConReqAck aware */
 static int spx_retransmit_chk(struct spx_opt *pdata, int ackseq, int type)
 {
 	struct ipxspxhdr *ipxh;
-	struct sk_buff *skb;
-
-	skb = skb_dequeue(&pdata->retransmit_queue);
-	if(!skb)
-		return (-ENOENT);
+	int rc = -ENOENT;
+	struct sk_buff *skb = skb_dequeue(&pdata->retransmit_queue);
 
+	if (!skb)
+		goto out;
+	rc = 0;
 	/* Check Data/ACK seq */
-	switch(type)
-	{
+	switch (type) {
 		case ACK:	/* Check Sequence, Should == 1 */
 			ipxh = (struct ipxspxhdr *)skb->nh.raw;
-			if(!(ntohs(ipxh->spx.sequence) - htons(ackseq)))
+			if (!(ntohs(ipxh->spx.sequence) - htons(ackseq)))
 				break;
-
 		case CONACK:
 			del_timer(&pdata->retransmit);
 			pdata->retransmits = 0;
 			kfree_skb(skb);
-			if(skb_queue_empty(&pdata->retransmit_queue))
-			{
+			if (skb_queue_empty(&pdata->retransmit_queue)) {
 				skb = skb_dequeue(&pdata->transmit_queue);
-				if(skb != NULL)
+				if (skb)
 					spx_route_skb(pdata, skb, TQUEUE);
 			}
-			return (0);
+			goto out;
 	}
 
 	skb_queue_head(&pdata->retransmit_queue, skb);
-	return (-1);
+	rc = -1;
+out:	return rc;
 }
 
 /* SPX packet receive engine */
 void spx_rcv(struct sock *sk, int bytes)
 {
-	struct sk_buff *skb;
 	struct ipxspxhdr *ipxh;
 	struct spx_opt *pdata = spx_sk(sk);
+	struct sk_buff *skb = skb_dequeue(&sk->receive_queue);
 
-	skb = skb_dequeue(&sk->receive_queue);
-	if(skb == NULL)
-		return;
+	if (!skb)
+		goto out;
 	ipxh = (struct ipxspxhdr *)skb->nh.raw;
 
 	/* Can't receive on a closed connection */
-        if((pdata->state == SPX_CLOSED) && (ipxh->spx.sequence != 0))
-		goto toss_skb;
-	if(ntohs(ipxh->ipx.ipx_pktsize) < SPX_SYS_PKT_LEN)
-		goto toss_skb;
-        if(ipxh->ipx.ipx_type != IPX_TYPE_SPX)
-		goto toss_skb;
-        if(ntohs(ipxh->spx.ackseq) > pdata->sequence)
+        if ((pdata->state == SPX_CLOSED && ipxh->spx.sequence) ||
+	    ntohs(ipxh->ipx.ipx_pktsize) < SPX_SYS_PKT_LEN ||
+            ipxh->ipx.ipx_type != IPX_TYPE_SPX ||
+            ntohs(ipxh->spx.ackseq) > pdata->sequence)
 		goto toss_skb;
 
 	/* Reset WD timer on any received packet */
@@ -640,13 +612,11 @@
 	pdata->watchdog.expires = jiffies + ABORT_TIMEOUT;
         add_timer(&pdata->watchdog);
 
-	switch(ipxh->spx.cctl)
-	{
+	switch (ipxh->spx.cctl) {
 		case (CCTL_SYS | CCTL_ACK):
-			if((ipxh->spx.sequence == 0)	/* ConReq */
-				&& (ipxh->spx.ackseq == 0)
-				&& (ipxh->spx.dconn == 0xFFFF))
-			{
+			if (!ipxh->spx.sequence	&& /* ConReq */
+			    !ipxh->spx.ackseq &&
+			    ipxh->spx.dconn == 0xFFFF) {
 				pdata->state		= SPX_CONNECTED;
 				pdata->dest_addr        = ipxh->ipx.ipx_source;
 				pdata->source_addr      = ipxh->ipx.ipx_dest;
@@ -655,63 +625,57 @@
 
 				skb_queue_tail(&sk->receive_queue, skb);
 				wake_up_interruptible(sk->sleep);
-			}
-			else	/* WD Request */
+			} else	/* WD Request */
 				spx_transmit(sk, skb, WDACK, 0);
-			goto finish;
+			goto out;
 
 		case CCTL_SYS:	/* ACK */
-			if((ipxh->spx.dtype == 0)       /* ConReq ACK */
-                                && (ipxh->spx.sconn != 0xFFFF)
-                                && (ipxh->spx.dconn != 0xFFFF)
-                                && (ipxh->spx.sequence == 0)
-                                && (ipxh->spx.ackseq == 0)
-                                && (pdata->state != SPX_CONNECTED))
-                        {
+			if (!ipxh->spx.dtype &&      /* ConReq ACK */
+                            ipxh->spx.sconn != 0xFFFF &&
+                            ipxh->spx.dconn != 0xFFFF &&
+                            !ipxh->spx.sequence &&
+                            !ipxh->spx.ackseq &&
+                            pdata->state != SPX_CONNECTED) {
                                 pdata->state = SPX_CONNECTED;
 				pdata->dest_connid = ipxh->spx.sconn;
 
-				if(spx_retransmit_chk(pdata, 0, CONACK) < 0)
+				if (spx_retransmit_chk(pdata, 0, CONACK) < 0)
 					goto toss_skb;
 
                                 skb_queue_tail(&sk->receive_queue, skb);
                                 wake_up_interruptible(sk->sleep);
-                                goto finish;
+                                goto out;
                         }
 
 			spx_retransmit_chk(pdata, ipxh->spx.ackseq, ACK);
 			goto toss_skb;
 
-		case (CCTL_ACK):
+		case CCTL_ACK:
 			/* Informed Disconnect */
-			if(ipxh->spx.dtype == SPX_DTYPE_ECONN)
-			{
-				
+			if (ipxh->spx.dtype == SPX_DTYPE_ECONN) {
 				spx_transmit(sk, skb, DISACK, 0);
 				spx_close_socket(sk);
-				goto finish;
+				goto out;
 			}
 			/* Fall through */
-
 		default:
-			if(ntohs(ipxh->spx.sequence) == pdata->rmt_seq)
-			{
+			if (ntohs(ipxh->spx.sequence) == pdata->rmt_seq) {
 				pdata->rmt_seq = ntohs(ipxh->spx.sequence);
 				pdata->rmt_ack = ntohs(ipxh->spx.ackseq);
 				pdata->alloc   = pdata->rmt_seq + 3;
-				if(pdata->rmt_ack > 0 || pdata->rmt_ack == 0)
-					spx_retransmit_chk(pdata,pdata->rmt_ack, ACK);
+				if (pdata->rmt_ack > 0 || !pdata->rmt_ack)
+					spx_retransmit_chk(pdata,
+							   pdata->rmt_ack, ACK);
 
 				skb_queue_tail(&pdata->rcv_queue, skb);
 				wake_up_interruptible(sk->sleep);
-				if(ipxh->spx.cctl&CCTL_ACK)
+				if (ipxh->spx.cctl&CCTL_ACK)
 					spx_transmit(sk, NULL, ACK, 0);
-				goto finish;
+				goto out;
 			}
 
-			if(ipxh->spx.dtype == SPX_DTYPE_ECACK)
-			{
-				if(pdata->state != SPX_CLOSED)
+			if (ipxh->spx.dtype == SPX_DTYPE_ECACK) {
+				if (pdata->state != SPX_CLOSED)
 					spx_close_socket(sk);
 				goto toss_skb;
 			}
@@ -719,51 +683,48 @@
 
 toss_skb:	/* Catch All */
 	kfree_skb(skb);
-finish:
-        return;
+out:;
 }
 
 /* Get message/packet data from user-land */
 static int spx_sendmsg(struct socket *sock, struct msghdr *msg, int len,
-			struct scm_cookie *scm)
+		       struct scm_cookie *scm)
 {
 	struct sock *sk = sock->sk;
 	int flags = msg->msg_flags;
 	struct sk_buff *skb;
-	int err, offset, size;
+	int offset, size, rc = -EMSGSIZE;
 
-	if(len > 534)
-                return (-EMSGSIZE);
-        if(sk->zapped)
-                return (-ENOTCONN); /* Socket not bound */
-	if(flags&~MSG_DONTWAIT)
-                return (-EINVAL);
+	if (len > 534)
+		goto out;
+	rc = -ENOTCONN; /* Socket not bound */
+        if (sk->zapped)
+		goto out;
+	rc = -EINVAL;
+	if (flags & ~MSG_DONTWAIT)
+		goto out;
 
 	offset	= ipx_if_offset(spx_sk(sk)->dest_addr.net);
         size 	= offset + sizeof(struct ipxspxhdr) + len;
 
 	cli();
-        skb  	= sock_alloc_send_skb(sk, size, flags&MSG_DONTWAIT, &err);
+        skb = sock_alloc_send_skb(sk, size, flags&MSG_DONTWAIT, &rc);
 	sti();
-        if(skb == NULL)
-                return (err);
-
+        if (!skb)
+                goto out;
 	skb->sk = sk;
         skb_reserve(skb, offset);
 	skb->h.raw = skb->nh.raw = skb_put(skb, sizeof(struct ipxspxhdr));
 
-	err = memcpy_fromiovec(skb_put(skb, len), msg->msg_iov, len);
-	if(err)
-        {
+	rc = -EFAULT;
+	if (memcpy_fromiovec(skb_put(skb, len), msg->msg_iov, len)) {
                 kfree_skb(skb);
-                return (-EFAULT);
+		goto out;
         }
-
-	err = spx_transmit(sk, skb, DATA, len);
-	if(err)
-		return (-EAGAIN);
-
-        return (len);
+	rc = len;
+	if (!spx_transmit(sk, skb, DATA, len))
+		rc = -EAGAIN;
+out:	return rc;
 }
 
 /* Send message/packet data to user-land */
@@ -775,70 +736,67 @@
 	struct sock *sk = sock->sk;
 	struct spx_opt *pdata = spx_sk(sk);
 	struct sockaddr_ipx *sipx = (struct sockaddr_ipx *)msg->msg_name;
-	int copied, err;
-
-        if(sk->zapped)
-                return (-ENOTCONN); /* Socket not bound */
+	int copied, rc = -ENOTCONN;
 
+        if (sk->zapped) /* Socket not bound */
+		goto out;
 	lock_sock(sk);
 restart:
-        while(skb_queue_empty(&pdata->rcv_queue))      /* No data */
-        {
+        while (skb_queue_empty(&pdata->rcv_queue)) {      /* No data */
                 /* Socket errors? */
-                err = sock_error(sk);
-                if(err)
-			return (err);
-
+                rc = sock_error(sk);
+                if (rc)
+			goto out_release_sock;
                 /* Socket shut down? */
-                if(sk->shutdown & RCV_SHUTDOWN)
-			return (-ESHUTDOWN);
-
+		rc = -ESHUTDOWN;
+                if (sk->shutdown & RCV_SHUTDOWN)
+			goto out_release_sock;
                 /* handle signals */
-                if(signal_pending(current))
-			return (-ERESTARTSYS);
-
+		rc = -ERESTARTSYS;
+                if (signal_pending(current))
+			goto out_release_sock;
                 /* User doesn't want to wait */
-                if(flags&MSG_DONTWAIT)
-			return (-EAGAIN);
-
+		rc = -EAGAIN;
+                if (flags & MSG_DONTWAIT)
+			goto out_release_sock;
 		release_sock(sk);
         	save_flags(flags);
         	cli();
-        	if(skb_peek(&pdata->rcv_queue) == NULL)
+        	if (!skb_peek(&pdata->rcv_queue))
                 	interruptible_sleep_on(sk->sleep);
         	restore_flags(flags);
         	lock_sock(sk);
         }
 
         skb = skb_dequeue(&pdata->rcv_queue);
-        if(skb == NULL) 
+        if (!skb) 
 		goto restart;
 
 	ispxh 	= (struct ipxspxhdr *)skb->nh.raw;
 	copied 	= ntohs(ispxh->ipx.ipx_pktsize) - SPX_SYS_PKT_LEN;
-        if(copied > size)
-	{
+        if (copied > size) {
                 copied = size;
                 msg->msg_flags |= MSG_TRUNC;
         }
 
-	err = memcpy_toiovec(msg->msg_iov, skb->nh.raw+SPX_SYS_PKT_LEN, copied);
-        if(err)
-                return (-EFAULT);
+	rc = -EFAULT;
+	if (memcpy_toiovec(msg->msg_iov, skb->nh.raw + SPX_SYS_PKT_LEN, copied))
+		goto out_kfree_skb;
 
 	msg->msg_namelen = sizeof(*sipx);
-	if(sipx)
-	{
+	if (sipx) {
 		sipx->sipx_family	= AF_IPX;
                 sipx->sipx_port		= ispxh->ipx.ipx_source.sock;
                 memcpy(sipx->sipx_node,ispxh->ipx.ipx_source.node,IPX_NODE_LEN);
                 sipx->sipx_network	= ispxh->ipx.ipx_source.net;
                 sipx->sipx_type 	= ispxh->ipx.ipx_type;
         }
+	rc = copied;
+out_kfree_skb:
 	kfree_skb(skb);
-        release_sock(sk);
-
-	return (copied);
+out_release_sock:
+	release_sock(sk);
+out:	return rc;
 }
 
 /*
@@ -847,41 +805,31 @@
 
 static int spx_bind(struct socket *sock, struct sockaddr *uaddr, int addr_len)
 {
-        int err;
-        err = ipx_operations->bind(sock, uaddr, addr_len);
-        return (err);
+        return ipx_ops->bind(sock, uaddr, addr_len);
 }
 
 static int spx_getname (struct socket *sock, struct sockaddr *uaddr,
                          int *usockaddr_len, int peer)
 {
-	int err;
-	err = ipx_operations->getname(sock, uaddr, usockaddr_len, peer);
-	return (err);
+	return ipx_ops->getname(sock, uaddr, usockaddr_len, peer);
 }
 
 static int spx_ioctl (struct socket *sock, unsigned int cmd,
                          unsigned long arg)
 {
-	int err;
-	err = ipx_operations->ioctl(sock, cmd, arg);
-	return (err);
+	return ipx_ops->ioctl(sock, cmd, arg);
 }
 
 static int spx_setsockopt(struct socket *sock, int level, int optname,
                          char *optval, int optlen)
 {
-	int err;
-	err = ipx_operations->setsockopt(sock, level, optname, optval, optlen);
-	return (err);
+	return ipx_ops->setsockopt(sock, level, optname, optval, optlen);
 }
 
 static int spx_getsockopt(struct socket *sock, int level, int optname,
                          char *optval, int *optlen)
 {
-	int err;
-	err = ipx_operations->getsockopt(sock, level, optname, optval, optlen);
-	return (err);
+	return ipx_ops->getsockopt(sock, level, optname, optval, optlen);
 }
 
 static struct proto_ops SOCKOPS_WRAPPED(spx_ops) = {
@@ -911,16 +859,13 @@
 static struct net_proto_family spx_family_ops = {
 	family:	 PF_IPX,
 	create:	 spx_create,
-	sk_size: sizeof(struct sock) + sizeof(struct ipx_opt) +
-		 sizeof(struct spx_opt),
 };
 
-static char banner[] __initdata = KERN_INFO "NET4: Sequenced Packet eXchange (SPX) 0.02 for Linux NET4.0\n";
+static char banner[] __initdata =
+	KERN_INFO "NET4: Sequenced Packet eXchange (SPX) 0.03\n";
 
 static int __init spx_proto_init(void)
 {
-	int error;
-
 	connids = (__u16)jiffies;	/* initalize random */
 
         /* allocate our sock slab cache */
@@ -933,8 +878,7 @@
                 printk(KERN_CRIT __FUNCTION__
                         ": Cannot create spx_sock SLAB cache!\n");
 
-	error = ipx_register_spx(&ipx_operations, &spx_family_ops);
-        if (error)
+	if (ipx_register_spx(&ipx_ops, &spx_family_ops))
                 printk(KERN_ERR "SPX: unable to register with IPX.\n");
 
 	/* route socket(PF_IPX, SOCK_SEQPACKET) calls through spx_create() */
@@ -942,11 +886,12 @@
 	printk(banner);
 	return 0;
 }
-module_init(spx_proto_init);
 
 static void __exit spx_proto_finito(void)
 {
 	ipx_unregister_spx();
-	return;
 }
+
+module_init(spx_proto_init);
 module_exit(spx_proto_finito);
+MODULE_LICENSE("GPL");
diff -Nru a/net/irda/af_irda.c b/net/irda/af_irda.c
--- a/net/irda/af_irda.c	Fri Mar 15 17:51:02 2002
+++ b/net/irda/af_irda.c	Fri Mar 15 17:51:02 2002
@@ -1700,7 +1700,7 @@
 
 		if (sk->state == TCP_ESTABLISHED) {
 			if ((self->tx_flow == FLOW_START) && 
-			    (sk->sndbuf - (int)atomic_read(&sk->wmem_alloc) >= SOCK_MIN_WRITE_SPACE))
+			    sock_writeable(sk))
 			{
 				mask |= POLLOUT | POLLWRNORM | POLLWRBAND;
 			}
@@ -1708,13 +1708,13 @@
 		break;
 	case SOCK_SEQPACKET:
 		if ((self->tx_flow == FLOW_START) && 
-		    (sk->sndbuf - (int)atomic_read(&sk->wmem_alloc) >= SOCK_MIN_WRITE_SPACE))
+		    sock_writeable(sk))
 		{	
 			mask |= POLLOUT | POLLWRNORM | POLLWRBAND;
 		}
 		break;
 	case SOCK_DGRAM:
-		if (sk->sndbuf - (int)atomic_read(&sk->wmem_alloc) >= SOCK_MIN_WRITE_SPACE)
+		if (sock_writeable(sk))
 			mask |= POLLOUT | POLLWRNORM | POLLWRBAND;
 		break;
 	default:
diff -Nru a/net/netsyms.c b/net/netsyms.c
--- a/net/netsyms.c	Fri Mar 15 17:51:02 2002
+++ b/net/netsyms.c	Fri Mar 15 17:51:02 2002
@@ -490,6 +490,7 @@
 EXPORT_SYMBOL(skb_clone);
 EXPORT_SYMBOL(skb_copy);
 EXPORT_SYMBOL(netif_rx);
+EXPORT_SYMBOL(netif_receive_skb);
 EXPORT_SYMBOL(dev_add_pack);
 EXPORT_SYMBOL(dev_remove_pack);
 EXPORT_SYMBOL(dev_get);
@@ -587,5 +588,12 @@
 
 EXPORT_SYMBOL(net_call_rx_atomic);
 EXPORT_SYMBOL(softnet_data);
+
+#if defined(CONFIG_NET_RADIO) || defined(CONFIG_NET_PCMCIA_RADIO)
+/* Don't include the whole header mess for a single function */
+union iwreq_data;
+extern void wireless_send_event(struct net_device *dev, unsigned int cmd, union iwreq_data *wrqu, char *extra);
+EXPORT_SYMBOL(wireless_send_event);
+#endif	/* CONFIG_NET_RADIO || CONFIG_NET_PCMCIA_RADIO */
 
 #endif  /* CONFIG_NET */
diff -Nru a/net/packet/af_packet.c b/net/packet/af_packet.c
--- a/net/packet/af_packet.c	Fri Mar 15 17:51:01 2002
+++ b/net/packet/af_packet.c	Fri Mar 15 17:51:01 2002
@@ -180,6 +180,7 @@
 	spinlock_t		bind_lock;
 	char			running;	/* prot_hook is attached*/
 	int			ifindex;	/* bound device		*/
+	unsigned short		num;
 	struct tpacket_stats	stats;
 #ifdef CONFIG_PACKET_MULTICAST
 	struct packet_mclist	*mclist;
@@ -678,8 +679,10 @@
 	 */
 	 
 	if (saddr == NULL) {
-		ifindex	= pkt_sk(sk)->ifindex;
-		proto	= sk->num;
+		struct packet_opt *po = pkt_sk(sk);
+
+		ifindex	= po->ifindex;
+		proto	= po->num;
 		addr	= NULL;
 	} else {
 		err = -EINVAL;
@@ -839,7 +842,7 @@
 		po->running = 0;
 	}
 
-	sk->num = protocol;
+	po->num = protocol;
 	po->prot_hook.type = protocol;
 	po->prot_hook.dev = dev;
 
@@ -894,7 +897,7 @@
 
 	dev = dev_get_by_name(name);
 	if (dev) {
-		err = packet_do_bind(sk, dev, sk->num);
+		err = packet_do_bind(sk, dev, pkt_sk(sk)->num);
 		dev_put(dev);
 	}
 	return err;
@@ -924,7 +927,7 @@
 		if (dev == NULL)
 			goto out;
 	}
-	err = packet_do_bind(sk, dev, sll->sll_protocol ? : sk->num);
+	err = packet_do_bind(sk, dev, sll->sll_protocol ? : pkt_sk(sk)->num);
 	if (dev)
 		dev_put(dev);
 
@@ -972,7 +975,7 @@
 		goto out_free;
 	memset(po, 0, sizeof(*po));
 	sk->family = PF_PACKET;
-	sk->num = protocol;
+	po->num = protocol;
 
 	sk->destruct = packet_sock_destruct;
 	atomic_inc(&packet_socks_nr);
@@ -1131,7 +1134,7 @@
 
 	sll->sll_family = AF_PACKET;
 	sll->sll_ifindex = po->ifindex;
-	sll->sll_protocol = sk->num;
+	sll->sll_protocol = po->num;
 	dev = dev_get_by_index(po->ifindex);
 	if (dev) {
 		sll->sll_hatype = dev->type;
@@ -1410,7 +1413,8 @@
 			break;
 		case NETDEV_UP:
 			spin_lock(&po->bind_lock);
-			if (dev->ifindex == po->ifindex && sk->num && po->running==0) {
+			if (dev->ifindex == po->ifindex && po->num &&
+			    !po->running) {
 				dev_add_pack(&po->prot_hook);
 				sock_hold(sk);
 				po->running = 1;
@@ -1861,7 +1865,7 @@
 			     s,
 			     atomic_read(&s->refcnt),
 			     s->type,
-			     ntohs(s->num),
+			     ntohs(po->num),
 			     po->ifindex,
 			     po->running,
 			     atomic_read(&s->rmem_alloc),
diff -Nru a/net/sched/sch_gred.c b/net/sched/sch_gred.c
--- a/net/sched/sch_gred.c	Fri Mar 15 17:51:02 2002
+++ b/net/sched/sch_gred.c	Fri Mar 15 17:51:02 2002
@@ -7,7 +7,7 @@
  *              as published by the Free Software Foundation; either version
  *              2 of the License, or (at your option) any later version.
  *
- * Authors:    J Hadi Salim (hadi@nortelnetworks.com) 1998,1999
+ * Authors:    J Hadi Salim (hadi@cyberus.ca) 1998-2002
  *
  *             991129: -  Bug fix with grio mode
  *		       - a better sing. AvgQ mode with Grio(WRED)
@@ -436,7 +436,7 @@
 		if (table->tab[table->def] == NULL) {
 			table->tab[table->def]=
 				kmalloc(sizeof(struct gred_sched_data), GFP_KERNEL);
-			if (NULL == table->tab[ctl->DP])
+			if (NULL == table->tab[table->def])
 				return -ENOMEM;
 
 			memset(table->tab[table->def], 0,
@@ -498,7 +498,7 @@
 {
 	unsigned long qave;
 	struct rtattr *rta;
-	struct tc_gred_qopt *opt;
+	struct tc_gred_qopt *opt = NULL ;
 	struct tc_gred_qopt *dst;
 	struct gred_sched *table = (struct gred_sched *)sch->data;
 	struct gred_sched_data *q;
@@ -520,7 +520,6 @@
 
 	if (!table->initd) {
 		DPRINTK("NO GRED Queues setup!\n");
-		return -1;
 	}
 
 	for (i=0;i<MAX_DPs;i++) {
@@ -577,9 +576,12 @@
 	RTA_PUT(skb, TCA_GRED_PARMS, sizeof(struct tc_gred_qopt)*MAX_DPs, opt);
 	rta->rta_len = skb->tail - b;
 
+	kfree(opt);
 	return skb->len;
 
 rtattr_failure:
+	if (opt)
+		kfree(opt);
 	DPRINTK("gred_dump: FAILURE!!!!\n");
 
 /* also free the opt struct here */
diff -Nru a/net/socket.c b/net/socket.c
--- a/net/socket.c	Fri Mar 15 17:51:02 2002
+++ b/net/socket.c	Fri Mar 15 17:51:02 2002
@@ -263,13 +263,6 @@
 }
 
 #define SOCKFS_MAGIC 0x534F434B
-static int sockfs_statfs(struct super_block *sb, struct statfs *buf)
-{
-	buf->f_type = SOCKFS_MAGIC;
-	buf->f_bsize = 1024;
-	buf->f_namelen = 255;
-	return 0;
-}
 
 static kmem_cache_t * sock_inode_cachep;
 
@@ -321,7 +314,7 @@
 static struct super_operations sockfs_ops = {
 	alloc_inode:	sock_alloc_inode,
 	destroy_inode:	sock_destroy_inode,
-	statfs:		sockfs_statfs,
+	statfs:		simple_statfs,
 };
 
 static int sockfs_fill_super(struct super_block *sb, void *data, int silent)
@@ -359,6 +352,7 @@
 static struct file_system_type sock_fs_type = {
 	name:		"sockfs",
 	get_sb:		sockfs_get_sb,
+	kill_sb:	kill_anon_super,
 	fs_flags:	FS_NOMOUNT,
 };
 static int sockfs_delete_dentry(struct dentry *dentry)
diff -Nru a/net/sunrpc/sunrpc_syms.c b/net/sunrpc/sunrpc_syms.c
--- a/net/sunrpc/sunrpc_syms.c	Fri Mar 15 17:51:03 2002
+++ b/net/sunrpc/sunrpc_syms.c	Fri Mar 15 17:51:03 2002
@@ -77,6 +77,7 @@
 EXPORT_SYMBOL(svc_recv);
 EXPORT_SYMBOL(svc_wake_up);
 EXPORT_SYMBOL(svc_makesock);
+EXPORT_SYMBOL(svc_reserve);
 
 /* RPC statistics */
 #ifdef CONFIG_PROC_FS
diff -Nru a/net/sunrpc/svcsock.c b/net/sunrpc/svcsock.c
--- a/net/sunrpc/svcsock.c	Fri Mar 15 17:51:01 2002
+++ b/net/sunrpc/svcsock.c	Fri Mar 15 17:51:01 2002
@@ -1161,7 +1161,8 @@
 
 	/* Register socket with portmapper */
 	if (*errp >= 0 && pmap_register)
-		*errp = svc_register(serv, inet->protocol, ntohs(inet->sport));
+		*errp = svc_register(serv, inet->protocol,
+				     ntohs(inet_sk(inet)->sport));
 
 	if (*errp < 0) {
 		inet->user_data = NULL;
diff -Nru a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c
--- a/net/sunrpc/xprt.c	Fri Mar 15 17:51:01 2002
+++ b/net/sunrpc/xprt.c	Fri Mar 15 17:51:01 2002
@@ -67,9 +67,6 @@
 
 #include <asm/uaccess.h>
 
-/* Following value should be > 32k + RPC overhead */
-#define XPRT_MIN_WRITE_SPACE (35000 + SOCK_MIN_WRITE_SPACE)
-
 extern spinlock_t rpc_queue_lock;
 
 /*
@@ -1099,9 +1096,8 @@
 	if (xprt->shutdown)
 		return;
 
-
-	/* Wait until we have enough socket memory */
-	if (sock_wspace(sk) < min_t(int, sk->sndbuf,XPRT_MIN_WRITE_SPACE))
+	/* Wait until we have enough socket memory. */
+	if (sock_writeable(sk))
 		return;
 
 	if (!xprt_test_and_set_wspace(xprt)) {
diff -Nru a/net/unix/af_unix.c b/net/unix/af_unix.c
--- a/net/unix/af_unix.c	Fri Mar 15 17:51:03 2002
+++ b/net/unix/af_unix.c	Fri Mar 15 17:51:03 2002
@@ -1767,7 +1767,7 @@
 		struct unix_sock *u = unix_sk(s);
 		unix_state_rlock(s);
 
-		len+=sprintf(buffer+len,"%p: %08X %08X %08X %04X %02X %5ld",
+		len+=sprintf(buffer+len,"%p: %08X %08X %08X %04X %02X %5lu",
 			s,
 			atomic_read(&s->refcnt),
 			0,
diff -Nru a/sound/core/rtctimer.c b/sound/core/rtctimer.c
--- a/sound/core/rtctimer.c	Fri Mar 15 17:51:02 2002
+++ b/sound/core/rtctimer.c	Fri Mar 15 17:51:02 2002
@@ -76,7 +76,7 @@
 static int
 rtctimer_open(snd_timer_t *t)
 {
-	err = rtc_register(&rtc_task);
+	int err = rtc_register(&rtc_task);
 	if (err < 0)
 		return err;
 	t->private_data = &rtc_task;
diff -Nru a/sound/oss/btaudio.c b/sound/oss/btaudio.c
--- a/sound/oss/btaudio.c	Fri Mar 15 17:51:02 2002
+++ b/sound/oss/btaudio.c	Fri Mar 15 17:51:02 2002
@@ -1,7 +1,7 @@
 /*
     btaudio - bt878 audio dma driver for linux 2.4.x
 
-    (c) 2000 Gerd Knorr <kraxel@bytesex.org>
+    (c) 2000-2002 Gerd Knorr <kraxel@bytesex.org>
 
     This program is free software; you can redistribute it and/or modify
     it under the terms of the GNU General Public License as published by
@@ -33,6 +33,7 @@
 #include <linux/sound.h>
 #include <linux/soundcard.h>
 #include <linux/slab.h>
+#include <linux/kdev_t.h>
 #include <asm/uaccess.h>
 #include <asm/io.h>
 
@@ -151,6 +152,7 @@
 static unsigned int mixer = -1;
 static unsigned int debug = 0;
 static unsigned int irq_debug = 0;
+static int latency = -1;
 static int digital = 1;
 static int analog = 1;
 static int rate = 32000;
@@ -682,7 +684,7 @@
 		return put_user((bta->channels)-1, (int *)arg);
 
         case SNDCTL_DSP_CHANNELS:
-		if (!analog) {
+		if (!bta->analog) {
 			if (get_user(val, (int*)arg))
 				return -EFAULT;
 			bta->channels    = (val > 1) ? 2 : 1;
@@ -697,7 +699,7 @@
 		return put_user(bta->channels, (int *)arg);
 		
         case SNDCTL_DSP_GETFMTS: /* Returns a mask */
-		if (analog)
+		if (bta->analog)
 			return put_user(AFMT_S16_LE|AFMT_S8, (int*)arg);
 		else
 			return put_user(AFMT_S16_LE, (int*)arg);
@@ -706,7 +708,7 @@
 		if (get_user(val, (int*)arg))
 			return -EFAULT;
                 if (val != AFMT_QUERY) {
-			if (analog)
+			if (bta->analog)
 				bta->bits = (val == AFMT_S8) ? 8 : 16;
 			else
 				bta->bits = 16;
@@ -783,7 +785,7 @@
 
 	poll_wait(file, &bta->readq, wait);
 
-	if (0 == bta->read_count)
+	if (0 != bta->read_count)
 		mask |= (POLLIN | POLLRDNORM);
 
 	return mask;
@@ -873,7 +875,7 @@
 				   const struct pci_device_id *pci_id)
 {
 	struct btaudio *bta;
-	unsigned char revision,latency;
+	unsigned char revision,lat;
 	int rc = -EBUSY;
 
 	if (pci_enable_device(pci_dev))
@@ -885,6 +887,10 @@
 	}
 
 	bta = kmalloc(sizeof(*bta),GFP_ATOMIC);
+	if (!bta) {
+		rc = -ENOMEM;
+		goto fail0;
+	}
 	memset(bta,0,sizeof(*bta));
 
 	bta->pci  = pci_dev;
@@ -906,13 +912,18 @@
 	init_MUTEX(&bta->lock);
         init_waitqueue_head(&bta->readq);
 
+	if (-1 != latency) {
+		printk(KERN_INFO "btaudio: setting pci latency timer to %d\n",
+		       latency);
+		pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, latency);
+	}
         pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &revision);
-        pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &latency);
+        pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
         printk(KERN_INFO "btaudio: Bt%x (rev %d) at %02x:%02x.%x, ",
 	       pci_dev->device,revision,pci_dev->bus->number,
 	       PCI_SLOT(pci_dev->devfn),PCI_FUNC(pci_dev->devfn));
-        printk("irq: %d, latency: %d, memory: 0x%lx\n",
-	       bta->irq, latency, bta->mem);
+        printk("irq: %d, latency: %d, mmio: 0x%lx\n",
+	       bta->irq, lat, bta->mem);
 
 	/* init hw */
         btwrite(0, REG_GPIO_DMA_CTL);
@@ -936,6 +947,8 @@
 			       "btaudio: can't register digital dsp (rc=%d)\n",rc);
 			goto fail2;
 		}
+		printk(KERN_INFO "btaudio: registered device dsp%d [digital]\n",
+		       bta->dsp_digital >> 4);
 	}
 	if (analog) {
 		rc = bta->dsp_analog =
@@ -945,16 +958,17 @@
 			       "btaudio: can't register analog dsp (rc=%d)\n",rc);
 			goto fail3;
 		}
+		printk(KERN_INFO "btaudio: registered device dsp%d [analog]\n",
+		       bta->dsp_analog >> 4);
 		rc = bta->mixer_dev = register_sound_mixer(&btaudio_mixer_fops,mixer);
 		if (rc < 0) {
 			printk(KERN_WARNING
 			       "btaudio: can't register mixer (rc=%d)\n",rc);
 			goto fail4;
 		}
+		printk(KERN_INFO "btaudio: registered device mixer%d\n",
+		       bta->mixer_dev >> 4);
 	}
-	if (debug)
-		printk(KERN_DEBUG "btaudio: minors: digital=%d, analog=%d, mixer=%d\n",
-		       bta->dsp_digital, bta->dsp_analog, bta->mixer_dev);
 
 	/* hook into linked list */
 	bta->next = btaudios;
@@ -971,9 +985,10 @@
  fail2:
         free_irq(bta->irq,bta);	
  fail1:
+	kfree(bta);
+ fail0:
 	release_mem_region(pci_resource_start(pci_dev,0),
 			   pci_resource_len(pci_dev,0));
-	kfree(bta);
 	return rc;
 }
 
@@ -1033,16 +1048,16 @@
         remove:   __devexit_p(btaudio_remove),
 };
 
-int btaudio_init_module(void)
+static int btaudio_init_module(void)
 {
 	printk(KERN_INFO "btaudio: driver version 0.6 loaded [%s%s%s]\n",
-	       analog ? "analog" : "",
+	       digital ? "digital" : "",
 	       analog && digital ? "+" : "",
-	       digital ? "digital" : "");
+	       analog ? "analog" : "");
 	return pci_module_init(&btaudio_pci_driver);
 }
 
-void btaudio_cleanup_module(void)
+static void btaudio_cleanup_module(void)
 {
 	pci_unregister_driver(&btaudio_pci_driver);
 	return;
@@ -1059,6 +1074,8 @@
 MODULE_PARM(digital,"i");
 MODULE_PARM(analog,"i");
 MODULE_PARM(rate,"i");
+MODULE_PARM(latency,"i");
+MODULE_PARM_DESC(latency,"pci latency timer");
 
 MODULE_DEVICE_TABLE(pci, btaudio_pci_tbl);
 MODULE_DESCRIPTION("bt878 audio dma driver");
diff -Nru a/sound/oss/es1370.c b/sound/oss/es1370.c
--- a/sound/oss/es1370.c	Fri Mar 15 17:51:03 2002
+++ b/sound/oss/es1370.c	Fri Mar 15 17:51:03 2002
@@ -374,6 +374,10 @@
 		unsigned subdivision;
 	} dma_dac1, dma_dac2, dma_adc;
 
+	/* The following buffer is used to point the phantom write channel to. */
+	unsigned char *bugbuf_cpu;
+	dma_addr_t bugbuf_dma;
+
 	/* midi stuff */
 	struct {
 		unsigned ird, iwr, icnt;
@@ -392,13 +396,6 @@
 
 static LIST_HEAD(devs);
 
-/*
- * The following buffer is used to point the phantom write channel to,
- * so that it cannot wreak havoc. The attribute makes sure it doesn't
- * cross a page boundary and ensures dword alignment for the DMA engine
- */
-static unsigned char bugbuf[16] __attribute__ ((aligned (16)));
-
 /* --------------------------------------------------------------------- */
 
 static inline unsigned ld2(unsigned int x)
@@ -2653,8 +2650,9 @@
 	outl(s->ctrl, s->io+ES1370_REG_CONTROL);
 	outl(s->sctrl, s->io+ES1370_REG_SERIAL_CONTROL);
 	/* point phantom write channel to "bugbuf" */
+	s->bugbuf_cpu = pci_alloc_consistent(pcidev,16,&s->bugbuf_dma);
 	outl((ES1370_REG_PHANTOM_FRAMEADR >> 8) & 15, s->io+ES1370_REG_MEMPAGE);
-	outl(virt_to_bus(bugbuf), s->io+(ES1370_REG_PHANTOM_FRAMEADR & 0xff));
+	outl(s->bugbuf_dma, s->io+(ES1370_REG_PHANTOM_FRAMEADR & 0xff));
 	outl(0, s->io+(ES1370_REG_PHANTOM_FRAMECNT & 0xff));
 	pci_set_master(pcidev);  /* enable bus mastering */
 	wrcodec(s, 0x16, 3); /* no RST, PD */
@@ -2721,6 +2719,7 @@
 	unregister_sound_mixer(s->dev_mixer);
 	unregister_sound_dsp(s->dev_dac);
 	unregister_sound_midi(s->dev_midi);
+	pci_free_consistent(dev, 16, s->bugbuf_cpu, s->bugbuf_dma);
 	kfree(s);
 	pci_set_drvdata(dev, NULL);
 }
diff -Nru a/sound/oss/via82cxxx_audio.c b/sound/oss/via82cxxx_audio.c
--- a/sound/oss/via82cxxx_audio.c	Fri Mar 15 17:51:02 2002
+++ b/sound/oss/via82cxxx_audio.c	Fri Mar 15 17:51:02 2002
@@ -2049,7 +2049,7 @@
 	while ((count > 0) && (chan->slop_len < chan->frag_size)) {
 		size_t slop_left = chan->frag_size - chan->slop_len;
 		void *base = chan->pgtbl[n / (PAGE_SIZE / chan->frag_size)].cpuaddr;
-		unsigned ofs = n % (PAGE_SIZE / chan->frag_size);
+		unsigned ofs = (n % (PAGE_SIZE / chan->frag_size)) * chan->frag_size;
 
 		size = (count < slop_left) ? count : slop_left;
 		if (copy_to_user (userbuf,
